1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Driver for Marvell PPv2 network controller for Armada 375 SoC. 4 * 5 * Copyright (C) 2014 Marvell 6 * 7 * Marcin Wojtas <mw@semihalf.com> 8 */ 9 10 #include <linux/acpi.h> 11 #include <linux/kernel.h> 12 #include <linux/netdevice.h> 13 #include <linux/etherdevice.h> 14 #include <linux/platform_device.h> 15 #include <linux/skbuff.h> 16 #include <linux/inetdevice.h> 17 #include <linux/mbus.h> 18 #include <linux/module.h> 19 #include <linux/mfd/syscon.h> 20 #include <linux/interrupt.h> 21 #include <linux/cpumask.h> 22 #include <linux/of.h> 23 #include <linux/of_irq.h> 24 #include <linux/of_mdio.h> 25 #include <linux/of_net.h> 26 #include <linux/of_address.h> 27 #include <linux/of_device.h> 28 #include <linux/phy.h> 29 #include <linux/phylink.h> 30 #include <linux/phy/phy.h> 31 #include <linux/ptp_classify.h> 32 #include <linux/clk.h> 33 #include <linux/hrtimer.h> 34 #include <linux/ktime.h> 35 #include <linux/regmap.h> 36 #include <uapi/linux/ppp_defs.h> 37 #include <net/ip.h> 38 #include <net/ipv6.h> 39 #include <net/tso.h> 40 #include <linux/bpf_trace.h> 41 42 #include "mvpp2.h" 43 #include "mvpp2_prs.h" 44 #include "mvpp2_cls.h" 45 46 enum mvpp2_bm_pool_log_num { 47 MVPP2_BM_SHORT, 48 MVPP2_BM_LONG, 49 MVPP2_BM_JUMBO, 50 MVPP2_BM_POOLS_NUM 51 }; 52 53 static struct { 54 int pkt_size; 55 int buf_num; 56 } mvpp2_pools[MVPP2_BM_POOLS_NUM]; 57 58 /* The prototype is added here to be used in start_dev when using ACPI. This 59 * will be removed once phylink is used for all modes (dt+ACPI). 60 */ 61 static void mvpp2_acpi_start(struct mvpp2_port *port); 62 63 /* Queue modes */ 64 #define MVPP2_QDIST_SINGLE_MODE 0 65 #define MVPP2_QDIST_MULTI_MODE 1 66 67 static int queue_mode = MVPP2_QDIST_MULTI_MODE; 68 69 module_param(queue_mode, int, 0444); 70 MODULE_PARM_DESC(queue_mode, "Set queue_mode (single=0, multi=1)"); 71 72 /* Utility/helper methods */ 73 74 void mvpp2_write(struct mvpp2 *priv, u32 offset, u32 data) 75 { 76 writel(data, priv->swth_base[0] + offset); 77 } 78 79 u32 mvpp2_read(struct mvpp2 *priv, u32 offset) 80 { 81 return readl(priv->swth_base[0] + offset); 82 } 83 84 static u32 mvpp2_read_relaxed(struct mvpp2 *priv, u32 offset) 85 { 86 return readl_relaxed(priv->swth_base[0] + offset); 87 } 88 89 static inline u32 mvpp2_cpu_to_thread(struct mvpp2 *priv, int cpu) 90 { 91 return cpu % priv->nthreads; 92 } 93 94 static struct page_pool * 95 mvpp2_create_page_pool(struct device *dev, int num, int len, 96 enum dma_data_direction dma_dir) 97 { 98 struct page_pool_params pp_params = { 99 /* internal DMA mapping in page_pool */ 100 .flags = PP_FLAG_DMA_MAP | PP_FLAG_DMA_SYNC_DEV, 101 .pool_size = num, 102 .nid = NUMA_NO_NODE, 103 .dev = dev, 104 .dma_dir = dma_dir, 105 .offset = MVPP2_SKB_HEADROOM, 106 .max_len = len, 107 }; 108 109 return page_pool_create(&pp_params); 110 } 111 112 /* These accessors should be used to access: 113 * 114 * - per-thread registers, where each thread has its own copy of the 115 * register. 116 * 117 * MVPP2_BM_VIRT_ALLOC_REG 118 * MVPP2_BM_ADDR_HIGH_ALLOC 119 * MVPP22_BM_ADDR_HIGH_RLS_REG 120 * MVPP2_BM_VIRT_RLS_REG 121 * MVPP2_ISR_RX_TX_CAUSE_REG 122 * MVPP2_ISR_RX_TX_MASK_REG 123 * MVPP2_TXQ_NUM_REG 124 * MVPP2_AGGR_TXQ_UPDATE_REG 125 * MVPP2_TXQ_RSVD_REQ_REG 126 * MVPP2_TXQ_RSVD_RSLT_REG 127 * MVPP2_TXQ_SENT_REG 128 * MVPP2_RXQ_NUM_REG 129 * 130 * - global registers that must be accessed through a specific thread 131 * window, because they are related to an access to a per-thread 132 * register 133 * 134 * MVPP2_BM_PHY_ALLOC_REG (related to MVPP2_BM_VIRT_ALLOC_REG) 135 * MVPP2_BM_PHY_RLS_REG (related to MVPP2_BM_VIRT_RLS_REG) 136 * MVPP2_RXQ_THRESH_REG (related to MVPP2_RXQ_NUM_REG) 137 * MVPP2_RXQ_DESC_ADDR_REG (related to MVPP2_RXQ_NUM_REG) 138 * MVPP2_RXQ_DESC_SIZE_REG (related to MVPP2_RXQ_NUM_REG) 139 * MVPP2_RXQ_INDEX_REG (related to MVPP2_RXQ_NUM_REG) 140 * MVPP2_TXQ_PENDING_REG (related to MVPP2_TXQ_NUM_REG) 141 * MVPP2_TXQ_DESC_ADDR_REG (related to MVPP2_TXQ_NUM_REG) 142 * MVPP2_TXQ_DESC_SIZE_REG (related to MVPP2_TXQ_NUM_REG) 143 * MVPP2_TXQ_INDEX_REG (related to MVPP2_TXQ_NUM_REG) 144 * MVPP2_TXQ_PENDING_REG (related to MVPP2_TXQ_NUM_REG) 145 * MVPP2_TXQ_PREF_BUF_REG (related to MVPP2_TXQ_NUM_REG) 146 * MVPP2_TXQ_PREF_BUF_REG (related to MVPP2_TXQ_NUM_REG) 147 */ 148 static void mvpp2_thread_write(struct mvpp2 *priv, unsigned int thread, 149 u32 offset, u32 data) 150 { 151 writel(data, priv->swth_base[thread] + offset); 152 } 153 154 static u32 mvpp2_thread_read(struct mvpp2 *priv, unsigned int thread, 155 u32 offset) 156 { 157 return readl(priv->swth_base[thread] + offset); 158 } 159 160 static void mvpp2_thread_write_relaxed(struct mvpp2 *priv, unsigned int thread, 161 u32 offset, u32 data) 162 { 163 writel_relaxed(data, priv->swth_base[thread] + offset); 164 } 165 166 static u32 mvpp2_thread_read_relaxed(struct mvpp2 *priv, unsigned int thread, 167 u32 offset) 168 { 169 return readl_relaxed(priv->swth_base[thread] + offset); 170 } 171 172 static dma_addr_t mvpp2_txdesc_dma_addr_get(struct mvpp2_port *port, 173 struct mvpp2_tx_desc *tx_desc) 174 { 175 if (port->priv->hw_version == MVPP21) 176 return le32_to_cpu(tx_desc->pp21.buf_dma_addr); 177 else 178 return le64_to_cpu(tx_desc->pp22.buf_dma_addr_ptp) & 179 MVPP2_DESC_DMA_MASK; 180 } 181 182 static void mvpp2_txdesc_dma_addr_set(struct mvpp2_port *port, 183 struct mvpp2_tx_desc *tx_desc, 184 dma_addr_t dma_addr) 185 { 186 dma_addr_t addr, offset; 187 188 addr = dma_addr & ~MVPP2_TX_DESC_ALIGN; 189 offset = dma_addr & MVPP2_TX_DESC_ALIGN; 190 191 if (port->priv->hw_version == MVPP21) { 192 tx_desc->pp21.buf_dma_addr = cpu_to_le32(addr); 193 tx_desc->pp21.packet_offset = offset; 194 } else { 195 __le64 val = cpu_to_le64(addr); 196 197 tx_desc->pp22.buf_dma_addr_ptp &= ~cpu_to_le64(MVPP2_DESC_DMA_MASK); 198 tx_desc->pp22.buf_dma_addr_ptp |= val; 199 tx_desc->pp22.packet_offset = offset; 200 } 201 } 202 203 static size_t mvpp2_txdesc_size_get(struct mvpp2_port *port, 204 struct mvpp2_tx_desc *tx_desc) 205 { 206 if (port->priv->hw_version == MVPP21) 207 return le16_to_cpu(tx_desc->pp21.data_size); 208 else 209 return le16_to_cpu(tx_desc->pp22.data_size); 210 } 211 212 static void mvpp2_txdesc_size_set(struct mvpp2_port *port, 213 struct mvpp2_tx_desc *tx_desc, 214 size_t size) 215 { 216 if (port->priv->hw_version == MVPP21) 217 tx_desc->pp21.data_size = cpu_to_le16(size); 218 else 219 tx_desc->pp22.data_size = cpu_to_le16(size); 220 } 221 222 static void mvpp2_txdesc_txq_set(struct mvpp2_port *port, 223 struct mvpp2_tx_desc *tx_desc, 224 unsigned int txq) 225 { 226 if (port->priv->hw_version == MVPP21) 227 tx_desc->pp21.phys_txq = txq; 228 else 229 tx_desc->pp22.phys_txq = txq; 230 } 231 232 static void mvpp2_txdesc_cmd_set(struct mvpp2_port *port, 233 struct mvpp2_tx_desc *tx_desc, 234 unsigned int command) 235 { 236 if (port->priv->hw_version == MVPP21) 237 tx_desc->pp21.command = cpu_to_le32(command); 238 else 239 tx_desc->pp22.command = cpu_to_le32(command); 240 } 241 242 static unsigned int mvpp2_txdesc_offset_get(struct mvpp2_port *port, 243 struct mvpp2_tx_desc *tx_desc) 244 { 245 if (port->priv->hw_version == MVPP21) 246 return tx_desc->pp21.packet_offset; 247 else 248 return tx_desc->pp22.packet_offset; 249 } 250 251 static dma_addr_t mvpp2_rxdesc_dma_addr_get(struct mvpp2_port *port, 252 struct mvpp2_rx_desc *rx_desc) 253 { 254 if (port->priv->hw_version == MVPP21) 255 return le32_to_cpu(rx_desc->pp21.buf_dma_addr); 256 else 257 return le64_to_cpu(rx_desc->pp22.buf_dma_addr_key_hash) & 258 MVPP2_DESC_DMA_MASK; 259 } 260 261 static unsigned long mvpp2_rxdesc_cookie_get(struct mvpp2_port *port, 262 struct mvpp2_rx_desc *rx_desc) 263 { 264 if (port->priv->hw_version == MVPP21) 265 return le32_to_cpu(rx_desc->pp21.buf_cookie); 266 else 267 return le64_to_cpu(rx_desc->pp22.buf_cookie_misc) & 268 MVPP2_DESC_DMA_MASK; 269 } 270 271 static size_t mvpp2_rxdesc_size_get(struct mvpp2_port *port, 272 struct mvpp2_rx_desc *rx_desc) 273 { 274 if (port->priv->hw_version == MVPP21) 275 return le16_to_cpu(rx_desc->pp21.data_size); 276 else 277 return le16_to_cpu(rx_desc->pp22.data_size); 278 } 279 280 static u32 mvpp2_rxdesc_status_get(struct mvpp2_port *port, 281 struct mvpp2_rx_desc *rx_desc) 282 { 283 if (port->priv->hw_version == MVPP21) 284 return le32_to_cpu(rx_desc->pp21.status); 285 else 286 return le32_to_cpu(rx_desc->pp22.status); 287 } 288 289 static void mvpp2_txq_inc_get(struct mvpp2_txq_pcpu *txq_pcpu) 290 { 291 txq_pcpu->txq_get_index++; 292 if (txq_pcpu->txq_get_index == txq_pcpu->size) 293 txq_pcpu->txq_get_index = 0; 294 } 295 296 static void mvpp2_txq_inc_put(struct mvpp2_port *port, 297 struct mvpp2_txq_pcpu *txq_pcpu, 298 void *data, 299 struct mvpp2_tx_desc *tx_desc, 300 enum mvpp2_tx_buf_type buf_type) 301 { 302 struct mvpp2_txq_pcpu_buf *tx_buf = 303 txq_pcpu->buffs + txq_pcpu->txq_put_index; 304 tx_buf->type = buf_type; 305 if (buf_type == MVPP2_TYPE_SKB) 306 tx_buf->skb = data; 307 else 308 tx_buf->xdpf = data; 309 tx_buf->size = mvpp2_txdesc_size_get(port, tx_desc); 310 tx_buf->dma = mvpp2_txdesc_dma_addr_get(port, tx_desc) + 311 mvpp2_txdesc_offset_get(port, tx_desc); 312 txq_pcpu->txq_put_index++; 313 if (txq_pcpu->txq_put_index == txq_pcpu->size) 314 txq_pcpu->txq_put_index = 0; 315 } 316 317 /* Get number of maximum RXQ */ 318 static int mvpp2_get_nrxqs(struct mvpp2 *priv) 319 { 320 unsigned int nrxqs; 321 322 if (priv->hw_version == MVPP22 && queue_mode == MVPP2_QDIST_SINGLE_MODE) 323 return 1; 324 325 /* According to the PPv2.2 datasheet and our experiments on 326 * PPv2.1, RX queues have an allocation granularity of 4 (when 327 * more than a single one on PPv2.2). 328 * Round up to nearest multiple of 4. 329 */ 330 nrxqs = (num_possible_cpus() + 3) & ~0x3; 331 if (nrxqs > MVPP2_PORT_MAX_RXQ) 332 nrxqs = MVPP2_PORT_MAX_RXQ; 333 334 return nrxqs; 335 } 336 337 /* Get number of physical egress port */ 338 static inline int mvpp2_egress_port(struct mvpp2_port *port) 339 { 340 return MVPP2_MAX_TCONT + port->id; 341 } 342 343 /* Get number of physical TXQ */ 344 static inline int mvpp2_txq_phys(int port, int txq) 345 { 346 return (MVPP2_MAX_TCONT + port) * MVPP2_MAX_TXQ + txq; 347 } 348 349 /* Returns a struct page if page_pool is set, otherwise a buffer */ 350 static void *mvpp2_frag_alloc(const struct mvpp2_bm_pool *pool, 351 struct page_pool *page_pool) 352 { 353 if (page_pool) 354 return page_pool_dev_alloc_pages(page_pool); 355 356 if (likely(pool->frag_size <= PAGE_SIZE)) 357 return netdev_alloc_frag(pool->frag_size); 358 359 return kmalloc(pool->frag_size, GFP_ATOMIC); 360 } 361 362 static void mvpp2_frag_free(const struct mvpp2_bm_pool *pool, 363 struct page_pool *page_pool, void *data) 364 { 365 if (page_pool) 366 page_pool_put_full_page(page_pool, virt_to_head_page(data), false); 367 else if (likely(pool->frag_size <= PAGE_SIZE)) 368 skb_free_frag(data); 369 else 370 kfree(data); 371 } 372 373 /* Buffer Manager configuration routines */ 374 375 /* Create pool */ 376 static int mvpp2_bm_pool_create(struct device *dev, struct mvpp2 *priv, 377 struct mvpp2_bm_pool *bm_pool, int size) 378 { 379 u32 val; 380 381 /* Number of buffer pointers must be a multiple of 16, as per 382 * hardware constraints 383 */ 384 if (!IS_ALIGNED(size, 16)) 385 return -EINVAL; 386 387 /* PPv2.1 needs 8 bytes per buffer pointer, PPv2.2 needs 16 388 * bytes per buffer pointer 389 */ 390 if (priv->hw_version == MVPP21) 391 bm_pool->size_bytes = 2 * sizeof(u32) * size; 392 else 393 bm_pool->size_bytes = 2 * sizeof(u64) * size; 394 395 bm_pool->virt_addr = dma_alloc_coherent(dev, bm_pool->size_bytes, 396 &bm_pool->dma_addr, 397 GFP_KERNEL); 398 if (!bm_pool->virt_addr) 399 return -ENOMEM; 400 401 if (!IS_ALIGNED((unsigned long)bm_pool->virt_addr, 402 MVPP2_BM_POOL_PTR_ALIGN)) { 403 dma_free_coherent(dev, bm_pool->size_bytes, 404 bm_pool->virt_addr, bm_pool->dma_addr); 405 dev_err(dev, "BM pool %d is not %d bytes aligned\n", 406 bm_pool->id, MVPP2_BM_POOL_PTR_ALIGN); 407 return -ENOMEM; 408 } 409 410 mvpp2_write(priv, MVPP2_BM_POOL_BASE_REG(bm_pool->id), 411 lower_32_bits(bm_pool->dma_addr)); 412 mvpp2_write(priv, MVPP2_BM_POOL_SIZE_REG(bm_pool->id), size); 413 414 val = mvpp2_read(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id)); 415 val |= MVPP2_BM_START_MASK; 416 mvpp2_write(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id), val); 417 418 bm_pool->size = size; 419 bm_pool->pkt_size = 0; 420 bm_pool->buf_num = 0; 421 422 return 0; 423 } 424 425 /* Set pool buffer size */ 426 static void mvpp2_bm_pool_bufsize_set(struct mvpp2 *priv, 427 struct mvpp2_bm_pool *bm_pool, 428 int buf_size) 429 { 430 u32 val; 431 432 bm_pool->buf_size = buf_size; 433 434 val = ALIGN(buf_size, 1 << MVPP2_POOL_BUF_SIZE_OFFSET); 435 mvpp2_write(priv, MVPP2_POOL_BUF_SIZE_REG(bm_pool->id), val); 436 } 437 438 static void mvpp2_bm_bufs_get_addrs(struct device *dev, struct mvpp2 *priv, 439 struct mvpp2_bm_pool *bm_pool, 440 dma_addr_t *dma_addr, 441 phys_addr_t *phys_addr) 442 { 443 unsigned int thread = mvpp2_cpu_to_thread(priv, get_cpu()); 444 445 *dma_addr = mvpp2_thread_read(priv, thread, 446 MVPP2_BM_PHY_ALLOC_REG(bm_pool->id)); 447 *phys_addr = mvpp2_thread_read(priv, thread, MVPP2_BM_VIRT_ALLOC_REG); 448 449 if (priv->hw_version == MVPP22) { 450 u32 val; 451 u32 dma_addr_highbits, phys_addr_highbits; 452 453 val = mvpp2_thread_read(priv, thread, MVPP22_BM_ADDR_HIGH_ALLOC); 454 dma_addr_highbits = (val & MVPP22_BM_ADDR_HIGH_PHYS_MASK); 455 phys_addr_highbits = (val & MVPP22_BM_ADDR_HIGH_VIRT_MASK) >> 456 MVPP22_BM_ADDR_HIGH_VIRT_SHIFT; 457 458 if (sizeof(dma_addr_t) == 8) 459 *dma_addr |= (u64)dma_addr_highbits << 32; 460 461 if (sizeof(phys_addr_t) == 8) 462 *phys_addr |= (u64)phys_addr_highbits << 32; 463 } 464 465 put_cpu(); 466 } 467 468 /* Free all buffers from the pool */ 469 static void mvpp2_bm_bufs_free(struct device *dev, struct mvpp2 *priv, 470 struct mvpp2_bm_pool *bm_pool, int buf_num) 471 { 472 struct page_pool *pp = NULL; 473 int i; 474 475 if (buf_num > bm_pool->buf_num) { 476 WARN(1, "Pool does not have so many bufs pool(%d) bufs(%d)\n", 477 bm_pool->id, buf_num); 478 buf_num = bm_pool->buf_num; 479 } 480 481 if (priv->percpu_pools) 482 pp = priv->page_pool[bm_pool->id]; 483 484 for (i = 0; i < buf_num; i++) { 485 dma_addr_t buf_dma_addr; 486 phys_addr_t buf_phys_addr; 487 void *data; 488 489 mvpp2_bm_bufs_get_addrs(dev, priv, bm_pool, 490 &buf_dma_addr, &buf_phys_addr); 491 492 if (!pp) 493 dma_unmap_single(dev, buf_dma_addr, 494 bm_pool->buf_size, DMA_FROM_DEVICE); 495 496 data = (void *)phys_to_virt(buf_phys_addr); 497 if (!data) 498 break; 499 500 mvpp2_frag_free(bm_pool, pp, data); 501 } 502 503 /* Update BM driver with number of buffers removed from pool */ 504 bm_pool->buf_num -= i; 505 } 506 507 /* Check number of buffers in BM pool */ 508 static int mvpp2_check_hw_buf_num(struct mvpp2 *priv, struct mvpp2_bm_pool *bm_pool) 509 { 510 int buf_num = 0; 511 512 buf_num += mvpp2_read(priv, MVPP2_BM_POOL_PTRS_NUM_REG(bm_pool->id)) & 513 MVPP22_BM_POOL_PTRS_NUM_MASK; 514 buf_num += mvpp2_read(priv, MVPP2_BM_BPPI_PTRS_NUM_REG(bm_pool->id)) & 515 MVPP2_BM_BPPI_PTR_NUM_MASK; 516 517 /* HW has one buffer ready which is not reflected in the counters */ 518 if (buf_num) 519 buf_num += 1; 520 521 return buf_num; 522 } 523 524 /* Cleanup pool */ 525 static int mvpp2_bm_pool_destroy(struct device *dev, struct mvpp2 *priv, 526 struct mvpp2_bm_pool *bm_pool) 527 { 528 int buf_num; 529 u32 val; 530 531 buf_num = mvpp2_check_hw_buf_num(priv, bm_pool); 532 mvpp2_bm_bufs_free(dev, priv, bm_pool, buf_num); 533 534 /* Check buffer counters after free */ 535 buf_num = mvpp2_check_hw_buf_num(priv, bm_pool); 536 if (buf_num) { 537 WARN(1, "cannot free all buffers in pool %d, buf_num left %d\n", 538 bm_pool->id, bm_pool->buf_num); 539 return 0; 540 } 541 542 val = mvpp2_read(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id)); 543 val |= MVPP2_BM_STOP_MASK; 544 mvpp2_write(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id), val); 545 546 if (priv->percpu_pools) { 547 page_pool_destroy(priv->page_pool[bm_pool->id]); 548 priv->page_pool[bm_pool->id] = NULL; 549 } 550 551 dma_free_coherent(dev, bm_pool->size_bytes, 552 bm_pool->virt_addr, 553 bm_pool->dma_addr); 554 return 0; 555 } 556 557 static int mvpp2_bm_pools_init(struct device *dev, struct mvpp2 *priv) 558 { 559 int i, err, size, poolnum = MVPP2_BM_POOLS_NUM; 560 struct mvpp2_bm_pool *bm_pool; 561 562 if (priv->percpu_pools) 563 poolnum = mvpp2_get_nrxqs(priv) * 2; 564 565 /* Create all pools with maximum size */ 566 size = MVPP2_BM_POOL_SIZE_MAX; 567 for (i = 0; i < poolnum; i++) { 568 bm_pool = &priv->bm_pools[i]; 569 bm_pool->id = i; 570 err = mvpp2_bm_pool_create(dev, priv, bm_pool, size); 571 if (err) 572 goto err_unroll_pools; 573 mvpp2_bm_pool_bufsize_set(priv, bm_pool, 0); 574 } 575 return 0; 576 577 err_unroll_pools: 578 dev_err(dev, "failed to create BM pool %d, size %d\n", i, size); 579 for (i = i - 1; i >= 0; i--) 580 mvpp2_bm_pool_destroy(dev, priv, &priv->bm_pools[i]); 581 return err; 582 } 583 584 static int mvpp2_bm_init(struct device *dev, struct mvpp2 *priv) 585 { 586 enum dma_data_direction dma_dir = DMA_FROM_DEVICE; 587 int i, err, poolnum = MVPP2_BM_POOLS_NUM; 588 struct mvpp2_port *port; 589 590 if (priv->percpu_pools) { 591 for (i = 0; i < priv->port_count; i++) { 592 port = priv->port_list[i]; 593 if (port->xdp_prog) { 594 dma_dir = DMA_BIDIRECTIONAL; 595 break; 596 } 597 } 598 599 poolnum = mvpp2_get_nrxqs(priv) * 2; 600 for (i = 0; i < poolnum; i++) { 601 /* the pool in use */ 602 int pn = i / (poolnum / 2); 603 604 priv->page_pool[i] = 605 mvpp2_create_page_pool(dev, 606 mvpp2_pools[pn].buf_num, 607 mvpp2_pools[pn].pkt_size, 608 dma_dir); 609 if (IS_ERR(priv->page_pool[i])) { 610 int j; 611 612 for (j = 0; j < i; j++) { 613 page_pool_destroy(priv->page_pool[j]); 614 priv->page_pool[j] = NULL; 615 } 616 return PTR_ERR(priv->page_pool[i]); 617 } 618 } 619 } 620 621 dev_info(dev, "using %d %s buffers\n", poolnum, 622 priv->percpu_pools ? "per-cpu" : "shared"); 623 624 for (i = 0; i < poolnum; i++) { 625 /* Mask BM all interrupts */ 626 mvpp2_write(priv, MVPP2_BM_INTR_MASK_REG(i), 0); 627 /* Clear BM cause register */ 628 mvpp2_write(priv, MVPP2_BM_INTR_CAUSE_REG(i), 0); 629 } 630 631 /* Allocate and initialize BM pools */ 632 priv->bm_pools = devm_kcalloc(dev, poolnum, 633 sizeof(*priv->bm_pools), GFP_KERNEL); 634 if (!priv->bm_pools) 635 return -ENOMEM; 636 637 err = mvpp2_bm_pools_init(dev, priv); 638 if (err < 0) 639 return err; 640 return 0; 641 } 642 643 static void mvpp2_setup_bm_pool(void) 644 { 645 /* Short pool */ 646 mvpp2_pools[MVPP2_BM_SHORT].buf_num = MVPP2_BM_SHORT_BUF_NUM; 647 mvpp2_pools[MVPP2_BM_SHORT].pkt_size = MVPP2_BM_SHORT_PKT_SIZE; 648 649 /* Long pool */ 650 mvpp2_pools[MVPP2_BM_LONG].buf_num = MVPP2_BM_LONG_BUF_NUM; 651 mvpp2_pools[MVPP2_BM_LONG].pkt_size = MVPP2_BM_LONG_PKT_SIZE; 652 653 /* Jumbo pool */ 654 mvpp2_pools[MVPP2_BM_JUMBO].buf_num = MVPP2_BM_JUMBO_BUF_NUM; 655 mvpp2_pools[MVPP2_BM_JUMBO].pkt_size = MVPP2_BM_JUMBO_PKT_SIZE; 656 } 657 658 /* Attach long pool to rxq */ 659 static void mvpp2_rxq_long_pool_set(struct mvpp2_port *port, 660 int lrxq, int long_pool) 661 { 662 u32 val, mask; 663 int prxq; 664 665 /* Get queue physical ID */ 666 prxq = port->rxqs[lrxq]->id; 667 668 if (port->priv->hw_version == MVPP21) 669 mask = MVPP21_RXQ_POOL_LONG_MASK; 670 else 671 mask = MVPP22_RXQ_POOL_LONG_MASK; 672 673 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(prxq)); 674 val &= ~mask; 675 val |= (long_pool << MVPP2_RXQ_POOL_LONG_OFFS) & mask; 676 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(prxq), val); 677 } 678 679 /* Attach short pool to rxq */ 680 static void mvpp2_rxq_short_pool_set(struct mvpp2_port *port, 681 int lrxq, int short_pool) 682 { 683 u32 val, mask; 684 int prxq; 685 686 /* Get queue physical ID */ 687 prxq = port->rxqs[lrxq]->id; 688 689 if (port->priv->hw_version == MVPP21) 690 mask = MVPP21_RXQ_POOL_SHORT_MASK; 691 else 692 mask = MVPP22_RXQ_POOL_SHORT_MASK; 693 694 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(prxq)); 695 val &= ~mask; 696 val |= (short_pool << MVPP2_RXQ_POOL_SHORT_OFFS) & mask; 697 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(prxq), val); 698 } 699 700 static void *mvpp2_buf_alloc(struct mvpp2_port *port, 701 struct mvpp2_bm_pool *bm_pool, 702 struct page_pool *page_pool, 703 dma_addr_t *buf_dma_addr, 704 phys_addr_t *buf_phys_addr, 705 gfp_t gfp_mask) 706 { 707 dma_addr_t dma_addr; 708 struct page *page; 709 void *data; 710 711 data = mvpp2_frag_alloc(bm_pool, page_pool); 712 if (!data) 713 return NULL; 714 715 if (page_pool) { 716 page = (struct page *)data; 717 dma_addr = page_pool_get_dma_addr(page); 718 data = page_to_virt(page); 719 } else { 720 dma_addr = dma_map_single(port->dev->dev.parent, data, 721 MVPP2_RX_BUF_SIZE(bm_pool->pkt_size), 722 DMA_FROM_DEVICE); 723 if (unlikely(dma_mapping_error(port->dev->dev.parent, dma_addr))) { 724 mvpp2_frag_free(bm_pool, NULL, data); 725 return NULL; 726 } 727 } 728 *buf_dma_addr = dma_addr; 729 *buf_phys_addr = virt_to_phys(data); 730 731 return data; 732 } 733 734 /* Release buffer to BM */ 735 static inline void mvpp2_bm_pool_put(struct mvpp2_port *port, int pool, 736 dma_addr_t buf_dma_addr, 737 phys_addr_t buf_phys_addr) 738 { 739 unsigned int thread = mvpp2_cpu_to_thread(port->priv, get_cpu()); 740 unsigned long flags = 0; 741 742 if (test_bit(thread, &port->priv->lock_map)) 743 spin_lock_irqsave(&port->bm_lock[thread], flags); 744 745 if (port->priv->hw_version == MVPP22) { 746 u32 val = 0; 747 748 if (sizeof(dma_addr_t) == 8) 749 val |= upper_32_bits(buf_dma_addr) & 750 MVPP22_BM_ADDR_HIGH_PHYS_RLS_MASK; 751 752 if (sizeof(phys_addr_t) == 8) 753 val |= (upper_32_bits(buf_phys_addr) 754 << MVPP22_BM_ADDR_HIGH_VIRT_RLS_SHIFT) & 755 MVPP22_BM_ADDR_HIGH_VIRT_RLS_MASK; 756 757 mvpp2_thread_write_relaxed(port->priv, thread, 758 MVPP22_BM_ADDR_HIGH_RLS_REG, val); 759 } 760 761 /* MVPP2_BM_VIRT_RLS_REG is not interpreted by HW, and simply 762 * returned in the "cookie" field of the RX 763 * descriptor. Instead of storing the virtual address, we 764 * store the physical address 765 */ 766 mvpp2_thread_write_relaxed(port->priv, thread, 767 MVPP2_BM_VIRT_RLS_REG, buf_phys_addr); 768 mvpp2_thread_write_relaxed(port->priv, thread, 769 MVPP2_BM_PHY_RLS_REG(pool), buf_dma_addr); 770 771 if (test_bit(thread, &port->priv->lock_map)) 772 spin_unlock_irqrestore(&port->bm_lock[thread], flags); 773 774 put_cpu(); 775 } 776 777 /* Allocate buffers for the pool */ 778 static int mvpp2_bm_bufs_add(struct mvpp2_port *port, 779 struct mvpp2_bm_pool *bm_pool, int buf_num) 780 { 781 int i, buf_size, total_size; 782 dma_addr_t dma_addr; 783 phys_addr_t phys_addr; 784 struct page_pool *pp = NULL; 785 void *buf; 786 787 if (port->priv->percpu_pools && 788 bm_pool->pkt_size > MVPP2_BM_LONG_PKT_SIZE) { 789 netdev_err(port->dev, 790 "attempted to use jumbo frames with per-cpu pools"); 791 return 0; 792 } 793 794 buf_size = MVPP2_RX_BUF_SIZE(bm_pool->pkt_size); 795 total_size = MVPP2_RX_TOTAL_SIZE(buf_size); 796 797 if (buf_num < 0 || 798 (buf_num + bm_pool->buf_num > bm_pool->size)) { 799 netdev_err(port->dev, 800 "cannot allocate %d buffers for pool %d\n", 801 buf_num, bm_pool->id); 802 return 0; 803 } 804 805 if (port->priv->percpu_pools) 806 pp = port->priv->page_pool[bm_pool->id]; 807 for (i = 0; i < buf_num; i++) { 808 buf = mvpp2_buf_alloc(port, bm_pool, pp, &dma_addr, 809 &phys_addr, GFP_KERNEL); 810 if (!buf) 811 break; 812 813 mvpp2_bm_pool_put(port, bm_pool->id, dma_addr, 814 phys_addr); 815 } 816 817 /* Update BM driver with number of buffers added to pool */ 818 bm_pool->buf_num += i; 819 820 netdev_dbg(port->dev, 821 "pool %d: pkt_size=%4d, buf_size=%4d, total_size=%4d\n", 822 bm_pool->id, bm_pool->pkt_size, buf_size, total_size); 823 824 netdev_dbg(port->dev, 825 "pool %d: %d of %d buffers added\n", 826 bm_pool->id, i, buf_num); 827 return i; 828 } 829 830 /* Notify the driver that BM pool is being used as specific type and return the 831 * pool pointer on success 832 */ 833 static struct mvpp2_bm_pool * 834 mvpp2_bm_pool_use(struct mvpp2_port *port, unsigned pool, int pkt_size) 835 { 836 struct mvpp2_bm_pool *new_pool = &port->priv->bm_pools[pool]; 837 int num; 838 839 if ((port->priv->percpu_pools && pool > mvpp2_get_nrxqs(port->priv) * 2) || 840 (!port->priv->percpu_pools && pool >= MVPP2_BM_POOLS_NUM)) { 841 netdev_err(port->dev, "Invalid pool %d\n", pool); 842 return NULL; 843 } 844 845 /* Allocate buffers in case BM pool is used as long pool, but packet 846 * size doesn't match MTU or BM pool hasn't being used yet 847 */ 848 if (new_pool->pkt_size == 0) { 849 int pkts_num; 850 851 /* Set default buffer number or free all the buffers in case 852 * the pool is not empty 853 */ 854 pkts_num = new_pool->buf_num; 855 if (pkts_num == 0) { 856 if (port->priv->percpu_pools) { 857 if (pool < port->nrxqs) 858 pkts_num = mvpp2_pools[MVPP2_BM_SHORT].buf_num; 859 else 860 pkts_num = mvpp2_pools[MVPP2_BM_LONG].buf_num; 861 } else { 862 pkts_num = mvpp2_pools[pool].buf_num; 863 } 864 } else { 865 mvpp2_bm_bufs_free(port->dev->dev.parent, 866 port->priv, new_pool, pkts_num); 867 } 868 869 new_pool->pkt_size = pkt_size; 870 new_pool->frag_size = 871 SKB_DATA_ALIGN(MVPP2_RX_BUF_SIZE(pkt_size)) + 872 MVPP2_SKB_SHINFO_SIZE; 873 874 /* Allocate buffers for this pool */ 875 num = mvpp2_bm_bufs_add(port, new_pool, pkts_num); 876 if (num != pkts_num) { 877 WARN(1, "pool %d: %d of %d allocated\n", 878 new_pool->id, num, pkts_num); 879 return NULL; 880 } 881 } 882 883 mvpp2_bm_pool_bufsize_set(port->priv, new_pool, 884 MVPP2_RX_BUF_SIZE(new_pool->pkt_size)); 885 886 return new_pool; 887 } 888 889 static struct mvpp2_bm_pool * 890 mvpp2_bm_pool_use_percpu(struct mvpp2_port *port, int type, 891 unsigned int pool, int pkt_size) 892 { 893 struct mvpp2_bm_pool *new_pool = &port->priv->bm_pools[pool]; 894 int num; 895 896 if (pool > port->nrxqs * 2) { 897 netdev_err(port->dev, "Invalid pool %d\n", pool); 898 return NULL; 899 } 900 901 /* Allocate buffers in case BM pool is used as long pool, but packet 902 * size doesn't match MTU or BM pool hasn't being used yet 903 */ 904 if (new_pool->pkt_size == 0) { 905 int pkts_num; 906 907 /* Set default buffer number or free all the buffers in case 908 * the pool is not empty 909 */ 910 pkts_num = new_pool->buf_num; 911 if (pkts_num == 0) 912 pkts_num = mvpp2_pools[type].buf_num; 913 else 914 mvpp2_bm_bufs_free(port->dev->dev.parent, 915 port->priv, new_pool, pkts_num); 916 917 new_pool->pkt_size = pkt_size; 918 new_pool->frag_size = 919 SKB_DATA_ALIGN(MVPP2_RX_BUF_SIZE(pkt_size)) + 920 MVPP2_SKB_SHINFO_SIZE; 921 922 /* Allocate buffers for this pool */ 923 num = mvpp2_bm_bufs_add(port, new_pool, pkts_num); 924 if (num != pkts_num) { 925 WARN(1, "pool %d: %d of %d allocated\n", 926 new_pool->id, num, pkts_num); 927 return NULL; 928 } 929 } 930 931 mvpp2_bm_pool_bufsize_set(port->priv, new_pool, 932 MVPP2_RX_BUF_SIZE(new_pool->pkt_size)); 933 934 return new_pool; 935 } 936 937 /* Initialize pools for swf, shared buffers variant */ 938 static int mvpp2_swf_bm_pool_init_shared(struct mvpp2_port *port) 939 { 940 enum mvpp2_bm_pool_log_num long_log_pool, short_log_pool; 941 int rxq; 942 943 /* If port pkt_size is higher than 1518B: 944 * HW Long pool - SW Jumbo pool, HW Short pool - SW Long pool 945 * else: HW Long pool - SW Long pool, HW Short pool - SW Short pool 946 */ 947 if (port->pkt_size > MVPP2_BM_LONG_PKT_SIZE) { 948 long_log_pool = MVPP2_BM_JUMBO; 949 short_log_pool = MVPP2_BM_LONG; 950 } else { 951 long_log_pool = MVPP2_BM_LONG; 952 short_log_pool = MVPP2_BM_SHORT; 953 } 954 955 if (!port->pool_long) { 956 port->pool_long = 957 mvpp2_bm_pool_use(port, long_log_pool, 958 mvpp2_pools[long_log_pool].pkt_size); 959 if (!port->pool_long) 960 return -ENOMEM; 961 962 port->pool_long->port_map |= BIT(port->id); 963 964 for (rxq = 0; rxq < port->nrxqs; rxq++) 965 mvpp2_rxq_long_pool_set(port, rxq, port->pool_long->id); 966 } 967 968 if (!port->pool_short) { 969 port->pool_short = 970 mvpp2_bm_pool_use(port, short_log_pool, 971 mvpp2_pools[short_log_pool].pkt_size); 972 if (!port->pool_short) 973 return -ENOMEM; 974 975 port->pool_short->port_map |= BIT(port->id); 976 977 for (rxq = 0; rxq < port->nrxqs; rxq++) 978 mvpp2_rxq_short_pool_set(port, rxq, 979 port->pool_short->id); 980 } 981 982 return 0; 983 } 984 985 /* Initialize pools for swf, percpu buffers variant */ 986 static int mvpp2_swf_bm_pool_init_percpu(struct mvpp2_port *port) 987 { 988 struct mvpp2_bm_pool *bm_pool; 989 int i; 990 991 for (i = 0; i < port->nrxqs; i++) { 992 bm_pool = mvpp2_bm_pool_use_percpu(port, MVPP2_BM_SHORT, i, 993 mvpp2_pools[MVPP2_BM_SHORT].pkt_size); 994 if (!bm_pool) 995 return -ENOMEM; 996 997 bm_pool->port_map |= BIT(port->id); 998 mvpp2_rxq_short_pool_set(port, i, bm_pool->id); 999 } 1000 1001 for (i = 0; i < port->nrxqs; i++) { 1002 bm_pool = mvpp2_bm_pool_use_percpu(port, MVPP2_BM_LONG, i + port->nrxqs, 1003 mvpp2_pools[MVPP2_BM_LONG].pkt_size); 1004 if (!bm_pool) 1005 return -ENOMEM; 1006 1007 bm_pool->port_map |= BIT(port->id); 1008 mvpp2_rxq_long_pool_set(port, i, bm_pool->id); 1009 } 1010 1011 port->pool_long = NULL; 1012 port->pool_short = NULL; 1013 1014 return 0; 1015 } 1016 1017 static int mvpp2_swf_bm_pool_init(struct mvpp2_port *port) 1018 { 1019 if (port->priv->percpu_pools) 1020 return mvpp2_swf_bm_pool_init_percpu(port); 1021 else 1022 return mvpp2_swf_bm_pool_init_shared(port); 1023 } 1024 1025 static void mvpp2_set_hw_csum(struct mvpp2_port *port, 1026 enum mvpp2_bm_pool_log_num new_long_pool) 1027 { 1028 const netdev_features_t csums = NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM; 1029 1030 /* Update L4 checksum when jumbo enable/disable on port. 1031 * Only port 0 supports hardware checksum offload due to 1032 * the Tx FIFO size limitation. 1033 * Also, don't set NETIF_F_HW_CSUM because L3_offset in TX descriptor 1034 * has 7 bits, so the maximum L3 offset is 128. 1035 */ 1036 if (new_long_pool == MVPP2_BM_JUMBO && port->id != 0) { 1037 port->dev->features &= ~csums; 1038 port->dev->hw_features &= ~csums; 1039 } else { 1040 port->dev->features |= csums; 1041 port->dev->hw_features |= csums; 1042 } 1043 } 1044 1045 static int mvpp2_bm_update_mtu(struct net_device *dev, int mtu) 1046 { 1047 struct mvpp2_port *port = netdev_priv(dev); 1048 enum mvpp2_bm_pool_log_num new_long_pool; 1049 int pkt_size = MVPP2_RX_PKT_SIZE(mtu); 1050 1051 if (port->priv->percpu_pools) 1052 goto out_set; 1053 1054 /* If port MTU is higher than 1518B: 1055 * HW Long pool - SW Jumbo pool, HW Short pool - SW Long pool 1056 * else: HW Long pool - SW Long pool, HW Short pool - SW Short pool 1057 */ 1058 if (pkt_size > MVPP2_BM_LONG_PKT_SIZE) 1059 new_long_pool = MVPP2_BM_JUMBO; 1060 else 1061 new_long_pool = MVPP2_BM_LONG; 1062 1063 if (new_long_pool != port->pool_long->id) { 1064 /* Remove port from old short & long pool */ 1065 port->pool_long = mvpp2_bm_pool_use(port, port->pool_long->id, 1066 port->pool_long->pkt_size); 1067 port->pool_long->port_map &= ~BIT(port->id); 1068 port->pool_long = NULL; 1069 1070 port->pool_short = mvpp2_bm_pool_use(port, port->pool_short->id, 1071 port->pool_short->pkt_size); 1072 port->pool_short->port_map &= ~BIT(port->id); 1073 port->pool_short = NULL; 1074 1075 port->pkt_size = pkt_size; 1076 1077 /* Add port to new short & long pool */ 1078 mvpp2_swf_bm_pool_init(port); 1079 1080 mvpp2_set_hw_csum(port, new_long_pool); 1081 } 1082 1083 out_set: 1084 dev->mtu = mtu; 1085 dev->wanted_features = dev->features; 1086 1087 netdev_update_features(dev); 1088 return 0; 1089 } 1090 1091 static inline void mvpp2_interrupts_enable(struct mvpp2_port *port) 1092 { 1093 int i, sw_thread_mask = 0; 1094 1095 for (i = 0; i < port->nqvecs; i++) 1096 sw_thread_mask |= port->qvecs[i].sw_thread_mask; 1097 1098 mvpp2_write(port->priv, MVPP2_ISR_ENABLE_REG(port->id), 1099 MVPP2_ISR_ENABLE_INTERRUPT(sw_thread_mask)); 1100 } 1101 1102 static inline void mvpp2_interrupts_disable(struct mvpp2_port *port) 1103 { 1104 int i, sw_thread_mask = 0; 1105 1106 for (i = 0; i < port->nqvecs; i++) 1107 sw_thread_mask |= port->qvecs[i].sw_thread_mask; 1108 1109 mvpp2_write(port->priv, MVPP2_ISR_ENABLE_REG(port->id), 1110 MVPP2_ISR_DISABLE_INTERRUPT(sw_thread_mask)); 1111 } 1112 1113 static inline void mvpp2_qvec_interrupt_enable(struct mvpp2_queue_vector *qvec) 1114 { 1115 struct mvpp2_port *port = qvec->port; 1116 1117 mvpp2_write(port->priv, MVPP2_ISR_ENABLE_REG(port->id), 1118 MVPP2_ISR_ENABLE_INTERRUPT(qvec->sw_thread_mask)); 1119 } 1120 1121 static inline void mvpp2_qvec_interrupt_disable(struct mvpp2_queue_vector *qvec) 1122 { 1123 struct mvpp2_port *port = qvec->port; 1124 1125 mvpp2_write(port->priv, MVPP2_ISR_ENABLE_REG(port->id), 1126 MVPP2_ISR_DISABLE_INTERRUPT(qvec->sw_thread_mask)); 1127 } 1128 1129 /* Mask the current thread's Rx/Tx interrupts 1130 * Called by on_each_cpu(), guaranteed to run with migration disabled, 1131 * using smp_processor_id() is OK. 1132 */ 1133 static void mvpp2_interrupts_mask(void *arg) 1134 { 1135 struct mvpp2_port *port = arg; 1136 1137 /* If the thread isn't used, don't do anything */ 1138 if (smp_processor_id() > port->priv->nthreads) 1139 return; 1140 1141 mvpp2_thread_write(port->priv, 1142 mvpp2_cpu_to_thread(port->priv, smp_processor_id()), 1143 MVPP2_ISR_RX_TX_MASK_REG(port->id), 0); 1144 } 1145 1146 /* Unmask the current thread's Rx/Tx interrupts. 1147 * Called by on_each_cpu(), guaranteed to run with migration disabled, 1148 * using smp_processor_id() is OK. 1149 */ 1150 static void mvpp2_interrupts_unmask(void *arg) 1151 { 1152 struct mvpp2_port *port = arg; 1153 u32 val; 1154 1155 /* If the thread isn't used, don't do anything */ 1156 if (smp_processor_id() > port->priv->nthreads) 1157 return; 1158 1159 val = MVPP2_CAUSE_MISC_SUM_MASK | 1160 MVPP2_CAUSE_RXQ_OCCUP_DESC_ALL_MASK(port->priv->hw_version); 1161 if (port->has_tx_irqs) 1162 val |= MVPP2_CAUSE_TXQ_OCCUP_DESC_ALL_MASK; 1163 1164 mvpp2_thread_write(port->priv, 1165 mvpp2_cpu_to_thread(port->priv, smp_processor_id()), 1166 MVPP2_ISR_RX_TX_MASK_REG(port->id), val); 1167 } 1168 1169 static void 1170 mvpp2_shared_interrupt_mask_unmask(struct mvpp2_port *port, bool mask) 1171 { 1172 u32 val; 1173 int i; 1174 1175 if (port->priv->hw_version != MVPP22) 1176 return; 1177 1178 if (mask) 1179 val = 0; 1180 else 1181 val = MVPP2_CAUSE_RXQ_OCCUP_DESC_ALL_MASK(MVPP22); 1182 1183 for (i = 0; i < port->nqvecs; i++) { 1184 struct mvpp2_queue_vector *v = port->qvecs + i; 1185 1186 if (v->type != MVPP2_QUEUE_VECTOR_SHARED) 1187 continue; 1188 1189 mvpp2_thread_write(port->priv, v->sw_thread_id, 1190 MVPP2_ISR_RX_TX_MASK_REG(port->id), val); 1191 } 1192 } 1193 1194 /* Only GOP port 0 has an XLG MAC */ 1195 static bool mvpp2_port_supports_xlg(struct mvpp2_port *port) 1196 { 1197 return port->gop_id == 0; 1198 } 1199 1200 static bool mvpp2_port_supports_rgmii(struct mvpp2_port *port) 1201 { 1202 return !(port->priv->hw_version == MVPP22 && port->gop_id == 0); 1203 } 1204 1205 /* Port configuration routines */ 1206 static bool mvpp2_is_xlg(phy_interface_t interface) 1207 { 1208 return interface == PHY_INTERFACE_MODE_10GBASER || 1209 interface == PHY_INTERFACE_MODE_XAUI; 1210 } 1211 1212 static void mvpp2_modify(void __iomem *ptr, u32 mask, u32 set) 1213 { 1214 u32 old, val; 1215 1216 old = val = readl(ptr); 1217 val &= ~mask; 1218 val |= set; 1219 if (old != val) 1220 writel(val, ptr); 1221 } 1222 1223 static void mvpp22_gop_init_rgmii(struct mvpp2_port *port) 1224 { 1225 struct mvpp2 *priv = port->priv; 1226 u32 val; 1227 1228 regmap_read(priv->sysctrl_base, GENCONF_PORT_CTRL0, &val); 1229 val |= GENCONF_PORT_CTRL0_BUS_WIDTH_SELECT; 1230 regmap_write(priv->sysctrl_base, GENCONF_PORT_CTRL0, val); 1231 1232 regmap_read(priv->sysctrl_base, GENCONF_CTRL0, &val); 1233 if (port->gop_id == 2) 1234 val |= GENCONF_CTRL0_PORT0_RGMII | GENCONF_CTRL0_PORT1_RGMII; 1235 else if (port->gop_id == 3) 1236 val |= GENCONF_CTRL0_PORT1_RGMII_MII; 1237 regmap_write(priv->sysctrl_base, GENCONF_CTRL0, val); 1238 } 1239 1240 static void mvpp22_gop_init_sgmii(struct mvpp2_port *port) 1241 { 1242 struct mvpp2 *priv = port->priv; 1243 u32 val; 1244 1245 regmap_read(priv->sysctrl_base, GENCONF_PORT_CTRL0, &val); 1246 val |= GENCONF_PORT_CTRL0_BUS_WIDTH_SELECT | 1247 GENCONF_PORT_CTRL0_RX_DATA_SAMPLE; 1248 regmap_write(priv->sysctrl_base, GENCONF_PORT_CTRL0, val); 1249 1250 if (port->gop_id > 1) { 1251 regmap_read(priv->sysctrl_base, GENCONF_CTRL0, &val); 1252 if (port->gop_id == 2) 1253 val &= ~GENCONF_CTRL0_PORT0_RGMII; 1254 else if (port->gop_id == 3) 1255 val &= ~GENCONF_CTRL0_PORT1_RGMII_MII; 1256 regmap_write(priv->sysctrl_base, GENCONF_CTRL0, val); 1257 } 1258 } 1259 1260 static void mvpp22_gop_init_10gkr(struct mvpp2_port *port) 1261 { 1262 struct mvpp2 *priv = port->priv; 1263 void __iomem *mpcs = priv->iface_base + MVPP22_MPCS_BASE(port->gop_id); 1264 void __iomem *xpcs = priv->iface_base + MVPP22_XPCS_BASE(port->gop_id); 1265 u32 val; 1266 1267 val = readl(xpcs + MVPP22_XPCS_CFG0); 1268 val &= ~(MVPP22_XPCS_CFG0_PCS_MODE(0x3) | 1269 MVPP22_XPCS_CFG0_ACTIVE_LANE(0x3)); 1270 val |= MVPP22_XPCS_CFG0_ACTIVE_LANE(2); 1271 writel(val, xpcs + MVPP22_XPCS_CFG0); 1272 1273 val = readl(mpcs + MVPP22_MPCS_CTRL); 1274 val &= ~MVPP22_MPCS_CTRL_FWD_ERR_CONN; 1275 writel(val, mpcs + MVPP22_MPCS_CTRL); 1276 1277 val = readl(mpcs + MVPP22_MPCS_CLK_RESET); 1278 val &= ~MVPP22_MPCS_CLK_RESET_DIV_RATIO(0x7); 1279 val |= MVPP22_MPCS_CLK_RESET_DIV_RATIO(1); 1280 writel(val, mpcs + MVPP22_MPCS_CLK_RESET); 1281 } 1282 1283 static int mvpp22_gop_init(struct mvpp2_port *port) 1284 { 1285 struct mvpp2 *priv = port->priv; 1286 u32 val; 1287 1288 if (!priv->sysctrl_base) 1289 return 0; 1290 1291 switch (port->phy_interface) { 1292 case PHY_INTERFACE_MODE_RGMII: 1293 case PHY_INTERFACE_MODE_RGMII_ID: 1294 case PHY_INTERFACE_MODE_RGMII_RXID: 1295 case PHY_INTERFACE_MODE_RGMII_TXID: 1296 if (!mvpp2_port_supports_rgmii(port)) 1297 goto invalid_conf; 1298 mvpp22_gop_init_rgmii(port); 1299 break; 1300 case PHY_INTERFACE_MODE_SGMII: 1301 case PHY_INTERFACE_MODE_1000BASEX: 1302 case PHY_INTERFACE_MODE_2500BASEX: 1303 mvpp22_gop_init_sgmii(port); 1304 break; 1305 case PHY_INTERFACE_MODE_10GBASER: 1306 if (!mvpp2_port_supports_xlg(port)) 1307 goto invalid_conf; 1308 mvpp22_gop_init_10gkr(port); 1309 break; 1310 default: 1311 goto unsupported_conf; 1312 } 1313 1314 regmap_read(priv->sysctrl_base, GENCONF_PORT_CTRL1, &val); 1315 val |= GENCONF_PORT_CTRL1_RESET(port->gop_id) | 1316 GENCONF_PORT_CTRL1_EN(port->gop_id); 1317 regmap_write(priv->sysctrl_base, GENCONF_PORT_CTRL1, val); 1318 1319 regmap_read(priv->sysctrl_base, GENCONF_PORT_CTRL0, &val); 1320 val |= GENCONF_PORT_CTRL0_CLK_DIV_PHASE_CLR; 1321 regmap_write(priv->sysctrl_base, GENCONF_PORT_CTRL0, val); 1322 1323 regmap_read(priv->sysctrl_base, GENCONF_SOFT_RESET1, &val); 1324 val |= GENCONF_SOFT_RESET1_GOP; 1325 regmap_write(priv->sysctrl_base, GENCONF_SOFT_RESET1, val); 1326 1327 unsupported_conf: 1328 return 0; 1329 1330 invalid_conf: 1331 netdev_err(port->dev, "Invalid port configuration\n"); 1332 return -EINVAL; 1333 } 1334 1335 static void mvpp22_gop_unmask_irq(struct mvpp2_port *port) 1336 { 1337 u32 val; 1338 1339 if (phy_interface_mode_is_rgmii(port->phy_interface) || 1340 phy_interface_mode_is_8023z(port->phy_interface) || 1341 port->phy_interface == PHY_INTERFACE_MODE_SGMII) { 1342 /* Enable the GMAC link status irq for this port */ 1343 val = readl(port->base + MVPP22_GMAC_INT_SUM_MASK); 1344 val |= MVPP22_GMAC_INT_SUM_MASK_LINK_STAT; 1345 writel(val, port->base + MVPP22_GMAC_INT_SUM_MASK); 1346 } 1347 1348 if (mvpp2_port_supports_xlg(port)) { 1349 /* Enable the XLG/GIG irqs for this port */ 1350 val = readl(port->base + MVPP22_XLG_EXT_INT_MASK); 1351 if (mvpp2_is_xlg(port->phy_interface)) 1352 val |= MVPP22_XLG_EXT_INT_MASK_XLG; 1353 else 1354 val |= MVPP22_XLG_EXT_INT_MASK_GIG; 1355 writel(val, port->base + MVPP22_XLG_EXT_INT_MASK); 1356 } 1357 } 1358 1359 static void mvpp22_gop_mask_irq(struct mvpp2_port *port) 1360 { 1361 u32 val; 1362 1363 if (mvpp2_port_supports_xlg(port)) { 1364 val = readl(port->base + MVPP22_XLG_EXT_INT_MASK); 1365 val &= ~(MVPP22_XLG_EXT_INT_MASK_XLG | 1366 MVPP22_XLG_EXT_INT_MASK_GIG); 1367 writel(val, port->base + MVPP22_XLG_EXT_INT_MASK); 1368 } 1369 1370 if (phy_interface_mode_is_rgmii(port->phy_interface) || 1371 phy_interface_mode_is_8023z(port->phy_interface) || 1372 port->phy_interface == PHY_INTERFACE_MODE_SGMII) { 1373 val = readl(port->base + MVPP22_GMAC_INT_SUM_MASK); 1374 val &= ~MVPP22_GMAC_INT_SUM_MASK_LINK_STAT; 1375 writel(val, port->base + MVPP22_GMAC_INT_SUM_MASK); 1376 } 1377 } 1378 1379 static void mvpp22_gop_setup_irq(struct mvpp2_port *port) 1380 { 1381 u32 val; 1382 1383 mvpp2_modify(port->base + MVPP22_GMAC_INT_SUM_MASK, 1384 MVPP22_GMAC_INT_SUM_MASK_PTP, 1385 MVPP22_GMAC_INT_SUM_MASK_PTP); 1386 1387 if (port->phylink || 1388 phy_interface_mode_is_rgmii(port->phy_interface) || 1389 phy_interface_mode_is_8023z(port->phy_interface) || 1390 port->phy_interface == PHY_INTERFACE_MODE_SGMII) { 1391 val = readl(port->base + MVPP22_GMAC_INT_MASK); 1392 val |= MVPP22_GMAC_INT_MASK_LINK_STAT; 1393 writel(val, port->base + MVPP22_GMAC_INT_MASK); 1394 } 1395 1396 if (mvpp2_port_supports_xlg(port)) { 1397 val = readl(port->base + MVPP22_XLG_INT_MASK); 1398 val |= MVPP22_XLG_INT_MASK_LINK; 1399 writel(val, port->base + MVPP22_XLG_INT_MASK); 1400 1401 mvpp2_modify(port->base + MVPP22_XLG_EXT_INT_MASK, 1402 MVPP22_XLG_EXT_INT_MASK_PTP, 1403 MVPP22_XLG_EXT_INT_MASK_PTP); 1404 } 1405 1406 mvpp22_gop_unmask_irq(port); 1407 } 1408 1409 /* Sets the PHY mode of the COMPHY (which configures the serdes lanes). 1410 * 1411 * The PHY mode used by the PPv2 driver comes from the network subsystem, while 1412 * the one given to the COMPHY comes from the generic PHY subsystem. Hence they 1413 * differ. 1414 * 1415 * The COMPHY configures the serdes lanes regardless of the actual use of the 1416 * lanes by the physical layer. This is why configurations like 1417 * "PPv2 (2500BaseX) - COMPHY (2500SGMII)" are valid. 1418 */ 1419 static int mvpp22_comphy_init(struct mvpp2_port *port) 1420 { 1421 int ret; 1422 1423 if (!port->comphy) 1424 return 0; 1425 1426 ret = phy_set_mode_ext(port->comphy, PHY_MODE_ETHERNET, 1427 port->phy_interface); 1428 if (ret) 1429 return ret; 1430 1431 return phy_power_on(port->comphy); 1432 } 1433 1434 static void mvpp2_port_enable(struct mvpp2_port *port) 1435 { 1436 u32 val; 1437 1438 if (mvpp2_port_supports_xlg(port) && 1439 mvpp2_is_xlg(port->phy_interface)) { 1440 val = readl(port->base + MVPP22_XLG_CTRL0_REG); 1441 val |= MVPP22_XLG_CTRL0_PORT_EN; 1442 val &= ~MVPP22_XLG_CTRL0_MIB_CNT_DIS; 1443 writel(val, port->base + MVPP22_XLG_CTRL0_REG); 1444 } else { 1445 val = readl(port->base + MVPP2_GMAC_CTRL_0_REG); 1446 val |= MVPP2_GMAC_PORT_EN_MASK; 1447 val |= MVPP2_GMAC_MIB_CNTR_EN_MASK; 1448 writel(val, port->base + MVPP2_GMAC_CTRL_0_REG); 1449 } 1450 } 1451 1452 static void mvpp2_port_disable(struct mvpp2_port *port) 1453 { 1454 u32 val; 1455 1456 if (mvpp2_port_supports_xlg(port) && 1457 mvpp2_is_xlg(port->phy_interface)) { 1458 val = readl(port->base + MVPP22_XLG_CTRL0_REG); 1459 val &= ~MVPP22_XLG_CTRL0_PORT_EN; 1460 writel(val, port->base + MVPP22_XLG_CTRL0_REG); 1461 } 1462 1463 val = readl(port->base + MVPP2_GMAC_CTRL_0_REG); 1464 val &= ~(MVPP2_GMAC_PORT_EN_MASK); 1465 writel(val, port->base + MVPP2_GMAC_CTRL_0_REG); 1466 } 1467 1468 /* Set IEEE 802.3x Flow Control Xon Packet Transmission Mode */ 1469 static void mvpp2_port_periodic_xon_disable(struct mvpp2_port *port) 1470 { 1471 u32 val; 1472 1473 val = readl(port->base + MVPP2_GMAC_CTRL_1_REG) & 1474 ~MVPP2_GMAC_PERIODIC_XON_EN_MASK; 1475 writel(val, port->base + MVPP2_GMAC_CTRL_1_REG); 1476 } 1477 1478 /* Configure loopback port */ 1479 static void mvpp2_port_loopback_set(struct mvpp2_port *port, 1480 const struct phylink_link_state *state) 1481 { 1482 u32 val; 1483 1484 val = readl(port->base + MVPP2_GMAC_CTRL_1_REG); 1485 1486 if (state->speed == 1000) 1487 val |= MVPP2_GMAC_GMII_LB_EN_MASK; 1488 else 1489 val &= ~MVPP2_GMAC_GMII_LB_EN_MASK; 1490 1491 if (phy_interface_mode_is_8023z(state->interface) || 1492 state->interface == PHY_INTERFACE_MODE_SGMII) 1493 val |= MVPP2_GMAC_PCS_LB_EN_MASK; 1494 else 1495 val &= ~MVPP2_GMAC_PCS_LB_EN_MASK; 1496 1497 writel(val, port->base + MVPP2_GMAC_CTRL_1_REG); 1498 } 1499 1500 enum { 1501 ETHTOOL_XDP_REDIRECT, 1502 ETHTOOL_XDP_PASS, 1503 ETHTOOL_XDP_DROP, 1504 ETHTOOL_XDP_TX, 1505 ETHTOOL_XDP_TX_ERR, 1506 ETHTOOL_XDP_XMIT, 1507 ETHTOOL_XDP_XMIT_ERR, 1508 }; 1509 1510 struct mvpp2_ethtool_counter { 1511 unsigned int offset; 1512 const char string[ETH_GSTRING_LEN]; 1513 bool reg_is_64b; 1514 }; 1515 1516 static u64 mvpp2_read_count(struct mvpp2_port *port, 1517 const struct mvpp2_ethtool_counter *counter) 1518 { 1519 u64 val; 1520 1521 val = readl(port->stats_base + counter->offset); 1522 if (counter->reg_is_64b) 1523 val += (u64)readl(port->stats_base + counter->offset + 4) << 32; 1524 1525 return val; 1526 } 1527 1528 /* Some counters are accessed indirectly by first writing an index to 1529 * MVPP2_CTRS_IDX. The index can represent various resources depending on the 1530 * register we access, it can be a hit counter for some classification tables, 1531 * a counter specific to a rxq, a txq or a buffer pool. 1532 */ 1533 static u32 mvpp2_read_index(struct mvpp2 *priv, u32 index, u32 reg) 1534 { 1535 mvpp2_write(priv, MVPP2_CTRS_IDX, index); 1536 return mvpp2_read(priv, reg); 1537 } 1538 1539 /* Due to the fact that software statistics and hardware statistics are, by 1540 * design, incremented at different moments in the chain of packet processing, 1541 * it is very likely that incoming packets could have been dropped after being 1542 * counted by hardware but before reaching software statistics (most probably 1543 * multicast packets), and in the oppposite way, during transmission, FCS bytes 1544 * are added in between as well as TSO skb will be split and header bytes added. 1545 * Hence, statistics gathered from userspace with ifconfig (software) and 1546 * ethtool (hardware) cannot be compared. 1547 */ 1548 static const struct mvpp2_ethtool_counter mvpp2_ethtool_mib_regs[] = { 1549 { MVPP2_MIB_GOOD_OCTETS_RCVD, "good_octets_received", true }, 1550 { MVPP2_MIB_BAD_OCTETS_RCVD, "bad_octets_received" }, 1551 { MVPP2_MIB_CRC_ERRORS_SENT, "crc_errors_sent" }, 1552 { MVPP2_MIB_UNICAST_FRAMES_RCVD, "unicast_frames_received" }, 1553 { MVPP2_MIB_BROADCAST_FRAMES_RCVD, "broadcast_frames_received" }, 1554 { MVPP2_MIB_MULTICAST_FRAMES_RCVD, "multicast_frames_received" }, 1555 { MVPP2_MIB_FRAMES_64_OCTETS, "frames_64_octets" }, 1556 { MVPP2_MIB_FRAMES_65_TO_127_OCTETS, "frames_65_to_127_octet" }, 1557 { MVPP2_MIB_FRAMES_128_TO_255_OCTETS, "frames_128_to_255_octet" }, 1558 { MVPP2_MIB_FRAMES_256_TO_511_OCTETS, "frames_256_to_511_octet" }, 1559 { MVPP2_MIB_FRAMES_512_TO_1023_OCTETS, "frames_512_to_1023_octet" }, 1560 { MVPP2_MIB_FRAMES_1024_TO_MAX_OCTETS, "frames_1024_to_max_octet" }, 1561 { MVPP2_MIB_GOOD_OCTETS_SENT, "good_octets_sent", true }, 1562 { MVPP2_MIB_UNICAST_FRAMES_SENT, "unicast_frames_sent" }, 1563 { MVPP2_MIB_MULTICAST_FRAMES_SENT, "multicast_frames_sent" }, 1564 { MVPP2_MIB_BROADCAST_FRAMES_SENT, "broadcast_frames_sent" }, 1565 { MVPP2_MIB_FC_SENT, "fc_sent" }, 1566 { MVPP2_MIB_FC_RCVD, "fc_received" }, 1567 { MVPP2_MIB_RX_FIFO_OVERRUN, "rx_fifo_overrun" }, 1568 { MVPP2_MIB_UNDERSIZE_RCVD, "undersize_received" }, 1569 { MVPP2_MIB_FRAGMENTS_RCVD, "fragments_received" }, 1570 { MVPP2_MIB_OVERSIZE_RCVD, "oversize_received" }, 1571 { MVPP2_MIB_JABBER_RCVD, "jabber_received" }, 1572 { MVPP2_MIB_MAC_RCV_ERROR, "mac_receive_error" }, 1573 { MVPP2_MIB_BAD_CRC_EVENT, "bad_crc_event" }, 1574 { MVPP2_MIB_COLLISION, "collision" }, 1575 { MVPP2_MIB_LATE_COLLISION, "late_collision" }, 1576 }; 1577 1578 static const struct mvpp2_ethtool_counter mvpp2_ethtool_port_regs[] = { 1579 { MVPP2_OVERRUN_ETH_DROP, "rx_fifo_or_parser_overrun_drops" }, 1580 { MVPP2_CLS_ETH_DROP, "rx_classifier_drops" }, 1581 }; 1582 1583 static const struct mvpp2_ethtool_counter mvpp2_ethtool_txq_regs[] = { 1584 { MVPP2_TX_DESC_ENQ_CTR, "txq_%d_desc_enqueue" }, 1585 { MVPP2_TX_DESC_ENQ_TO_DDR_CTR, "txq_%d_desc_enqueue_to_ddr" }, 1586 { MVPP2_TX_BUFF_ENQ_TO_DDR_CTR, "txq_%d_buff_euqueue_to_ddr" }, 1587 { MVPP2_TX_DESC_ENQ_HW_FWD_CTR, "txq_%d_desc_hardware_forwarded" }, 1588 { MVPP2_TX_PKTS_DEQ_CTR, "txq_%d_packets_dequeued" }, 1589 { MVPP2_TX_PKTS_FULL_QUEUE_DROP_CTR, "txq_%d_queue_full_drops" }, 1590 { MVPP2_TX_PKTS_EARLY_DROP_CTR, "txq_%d_packets_early_drops" }, 1591 { MVPP2_TX_PKTS_BM_DROP_CTR, "txq_%d_packets_bm_drops" }, 1592 { MVPP2_TX_PKTS_BM_MC_DROP_CTR, "txq_%d_packets_rep_bm_drops" }, 1593 }; 1594 1595 static const struct mvpp2_ethtool_counter mvpp2_ethtool_rxq_regs[] = { 1596 { MVPP2_RX_DESC_ENQ_CTR, "rxq_%d_desc_enqueue" }, 1597 { MVPP2_RX_PKTS_FULL_QUEUE_DROP_CTR, "rxq_%d_queue_full_drops" }, 1598 { MVPP2_RX_PKTS_EARLY_DROP_CTR, "rxq_%d_packets_early_drops" }, 1599 { MVPP2_RX_PKTS_BM_DROP_CTR, "rxq_%d_packets_bm_drops" }, 1600 }; 1601 1602 static const struct mvpp2_ethtool_counter mvpp2_ethtool_xdp[] = { 1603 { ETHTOOL_XDP_REDIRECT, "rx_xdp_redirect", }, 1604 { ETHTOOL_XDP_PASS, "rx_xdp_pass", }, 1605 { ETHTOOL_XDP_DROP, "rx_xdp_drop", }, 1606 { ETHTOOL_XDP_TX, "rx_xdp_tx", }, 1607 { ETHTOOL_XDP_TX_ERR, "rx_xdp_tx_errors", }, 1608 { ETHTOOL_XDP_XMIT, "tx_xdp_xmit", }, 1609 { ETHTOOL_XDP_XMIT_ERR, "tx_xdp_xmit_errors", }, 1610 }; 1611 1612 #define MVPP2_N_ETHTOOL_STATS(ntxqs, nrxqs) (ARRAY_SIZE(mvpp2_ethtool_mib_regs) + \ 1613 ARRAY_SIZE(mvpp2_ethtool_port_regs) + \ 1614 (ARRAY_SIZE(mvpp2_ethtool_txq_regs) * (ntxqs)) + \ 1615 (ARRAY_SIZE(mvpp2_ethtool_rxq_regs) * (nrxqs)) + \ 1616 ARRAY_SIZE(mvpp2_ethtool_xdp)) 1617 1618 static void mvpp2_ethtool_get_strings(struct net_device *netdev, u32 sset, 1619 u8 *data) 1620 { 1621 struct mvpp2_port *port = netdev_priv(netdev); 1622 int i, q; 1623 1624 if (sset != ETH_SS_STATS) 1625 return; 1626 1627 for (i = 0; i < ARRAY_SIZE(mvpp2_ethtool_mib_regs); i++) { 1628 strscpy(data, mvpp2_ethtool_mib_regs[i].string, 1629 ETH_GSTRING_LEN); 1630 data += ETH_GSTRING_LEN; 1631 } 1632 1633 for (i = 0; i < ARRAY_SIZE(mvpp2_ethtool_port_regs); i++) { 1634 strscpy(data, mvpp2_ethtool_port_regs[i].string, 1635 ETH_GSTRING_LEN); 1636 data += ETH_GSTRING_LEN; 1637 } 1638 1639 for (q = 0; q < port->ntxqs; q++) { 1640 for (i = 0; i < ARRAY_SIZE(mvpp2_ethtool_txq_regs); i++) { 1641 snprintf(data, ETH_GSTRING_LEN, 1642 mvpp2_ethtool_txq_regs[i].string, q); 1643 data += ETH_GSTRING_LEN; 1644 } 1645 } 1646 1647 for (q = 0; q < port->nrxqs; q++) { 1648 for (i = 0; i < ARRAY_SIZE(mvpp2_ethtool_rxq_regs); i++) { 1649 snprintf(data, ETH_GSTRING_LEN, 1650 mvpp2_ethtool_rxq_regs[i].string, 1651 q); 1652 data += ETH_GSTRING_LEN; 1653 } 1654 } 1655 1656 for (i = 0; i < ARRAY_SIZE(mvpp2_ethtool_xdp); i++) { 1657 strscpy(data, mvpp2_ethtool_xdp[i].string, 1658 ETH_GSTRING_LEN); 1659 data += ETH_GSTRING_LEN; 1660 } 1661 } 1662 1663 static void 1664 mvpp2_get_xdp_stats(struct mvpp2_port *port, struct mvpp2_pcpu_stats *xdp_stats) 1665 { 1666 unsigned int start; 1667 unsigned int cpu; 1668 1669 /* Gather XDP Statistics */ 1670 for_each_possible_cpu(cpu) { 1671 struct mvpp2_pcpu_stats *cpu_stats; 1672 u64 xdp_redirect; 1673 u64 xdp_pass; 1674 u64 xdp_drop; 1675 u64 xdp_xmit; 1676 u64 xdp_xmit_err; 1677 u64 xdp_tx; 1678 u64 xdp_tx_err; 1679 1680 cpu_stats = per_cpu_ptr(port->stats, cpu); 1681 do { 1682 start = u64_stats_fetch_begin_irq(&cpu_stats->syncp); 1683 xdp_redirect = cpu_stats->xdp_redirect; 1684 xdp_pass = cpu_stats->xdp_pass; 1685 xdp_drop = cpu_stats->xdp_drop; 1686 xdp_xmit = cpu_stats->xdp_xmit; 1687 xdp_xmit_err = cpu_stats->xdp_xmit_err; 1688 xdp_tx = cpu_stats->xdp_tx; 1689 xdp_tx_err = cpu_stats->xdp_tx_err; 1690 } while (u64_stats_fetch_retry_irq(&cpu_stats->syncp, start)); 1691 1692 xdp_stats->xdp_redirect += xdp_redirect; 1693 xdp_stats->xdp_pass += xdp_pass; 1694 xdp_stats->xdp_drop += xdp_drop; 1695 xdp_stats->xdp_xmit += xdp_xmit; 1696 xdp_stats->xdp_xmit_err += xdp_xmit_err; 1697 xdp_stats->xdp_tx += xdp_tx; 1698 xdp_stats->xdp_tx_err += xdp_tx_err; 1699 } 1700 } 1701 1702 static void mvpp2_read_stats(struct mvpp2_port *port) 1703 { 1704 struct mvpp2_pcpu_stats xdp_stats = {}; 1705 const struct mvpp2_ethtool_counter *s; 1706 u64 *pstats; 1707 int i, q; 1708 1709 pstats = port->ethtool_stats; 1710 1711 for (i = 0; i < ARRAY_SIZE(mvpp2_ethtool_mib_regs); i++) 1712 *pstats++ += mvpp2_read_count(port, &mvpp2_ethtool_mib_regs[i]); 1713 1714 for (i = 0; i < ARRAY_SIZE(mvpp2_ethtool_port_regs); i++) 1715 *pstats++ += mvpp2_read(port->priv, 1716 mvpp2_ethtool_port_regs[i].offset + 1717 4 * port->id); 1718 1719 for (q = 0; q < port->ntxqs; q++) 1720 for (i = 0; i < ARRAY_SIZE(mvpp2_ethtool_txq_regs); i++) 1721 *pstats++ += mvpp2_read_index(port->priv, 1722 MVPP22_CTRS_TX_CTR(port->id, q), 1723 mvpp2_ethtool_txq_regs[i].offset); 1724 1725 /* Rxqs are numbered from 0 from the user standpoint, but not from the 1726 * driver's. We need to add the port->first_rxq offset. 1727 */ 1728 for (q = 0; q < port->nrxqs; q++) 1729 for (i = 0; i < ARRAY_SIZE(mvpp2_ethtool_rxq_regs); i++) 1730 *pstats++ += mvpp2_read_index(port->priv, 1731 port->first_rxq + q, 1732 mvpp2_ethtool_rxq_regs[i].offset); 1733 1734 /* Gather XDP Statistics */ 1735 mvpp2_get_xdp_stats(port, &xdp_stats); 1736 1737 for (i = 0, s = mvpp2_ethtool_xdp; 1738 s < mvpp2_ethtool_xdp + ARRAY_SIZE(mvpp2_ethtool_xdp); 1739 s++, i++) { 1740 switch (s->offset) { 1741 case ETHTOOL_XDP_REDIRECT: 1742 *pstats++ = xdp_stats.xdp_redirect; 1743 break; 1744 case ETHTOOL_XDP_PASS: 1745 *pstats++ = xdp_stats.xdp_pass; 1746 break; 1747 case ETHTOOL_XDP_DROP: 1748 *pstats++ = xdp_stats.xdp_drop; 1749 break; 1750 case ETHTOOL_XDP_TX: 1751 *pstats++ = xdp_stats.xdp_tx; 1752 break; 1753 case ETHTOOL_XDP_TX_ERR: 1754 *pstats++ = xdp_stats.xdp_tx_err; 1755 break; 1756 case ETHTOOL_XDP_XMIT: 1757 *pstats++ = xdp_stats.xdp_xmit; 1758 break; 1759 case ETHTOOL_XDP_XMIT_ERR: 1760 *pstats++ = xdp_stats.xdp_xmit_err; 1761 break; 1762 } 1763 } 1764 } 1765 1766 static void mvpp2_gather_hw_statistics(struct work_struct *work) 1767 { 1768 struct delayed_work *del_work = to_delayed_work(work); 1769 struct mvpp2_port *port = container_of(del_work, struct mvpp2_port, 1770 stats_work); 1771 1772 mutex_lock(&port->gather_stats_lock); 1773 1774 mvpp2_read_stats(port); 1775 1776 /* No need to read again the counters right after this function if it 1777 * was called asynchronously by the user (ie. use of ethtool). 1778 */ 1779 cancel_delayed_work(&port->stats_work); 1780 queue_delayed_work(port->priv->stats_queue, &port->stats_work, 1781 MVPP2_MIB_COUNTERS_STATS_DELAY); 1782 1783 mutex_unlock(&port->gather_stats_lock); 1784 } 1785 1786 static void mvpp2_ethtool_get_stats(struct net_device *dev, 1787 struct ethtool_stats *stats, u64 *data) 1788 { 1789 struct mvpp2_port *port = netdev_priv(dev); 1790 1791 /* Update statistics for the given port, then take the lock to avoid 1792 * concurrent accesses on the ethtool_stats structure during its copy. 1793 */ 1794 mvpp2_gather_hw_statistics(&port->stats_work.work); 1795 1796 mutex_lock(&port->gather_stats_lock); 1797 memcpy(data, port->ethtool_stats, 1798 sizeof(u64) * MVPP2_N_ETHTOOL_STATS(port->ntxqs, port->nrxqs)); 1799 mutex_unlock(&port->gather_stats_lock); 1800 } 1801 1802 static int mvpp2_ethtool_get_sset_count(struct net_device *dev, int sset) 1803 { 1804 struct mvpp2_port *port = netdev_priv(dev); 1805 1806 if (sset == ETH_SS_STATS) 1807 return MVPP2_N_ETHTOOL_STATS(port->ntxqs, port->nrxqs); 1808 1809 return -EOPNOTSUPP; 1810 } 1811 1812 static void mvpp2_mac_reset_assert(struct mvpp2_port *port) 1813 { 1814 u32 val; 1815 1816 val = readl(port->base + MVPP2_GMAC_CTRL_2_REG) | 1817 MVPP2_GMAC_PORT_RESET_MASK; 1818 writel(val, port->base + MVPP2_GMAC_CTRL_2_REG); 1819 1820 if (port->priv->hw_version == MVPP22 && port->gop_id == 0) { 1821 val = readl(port->base + MVPP22_XLG_CTRL0_REG) & 1822 ~MVPP22_XLG_CTRL0_MAC_RESET_DIS; 1823 writel(val, port->base + MVPP22_XLG_CTRL0_REG); 1824 } 1825 } 1826 1827 static void mvpp22_pcs_reset_assert(struct mvpp2_port *port) 1828 { 1829 struct mvpp2 *priv = port->priv; 1830 void __iomem *mpcs, *xpcs; 1831 u32 val; 1832 1833 if (port->priv->hw_version != MVPP22 || port->gop_id != 0) 1834 return; 1835 1836 mpcs = priv->iface_base + MVPP22_MPCS_BASE(port->gop_id); 1837 xpcs = priv->iface_base + MVPP22_XPCS_BASE(port->gop_id); 1838 1839 val = readl(mpcs + MVPP22_MPCS_CLK_RESET); 1840 val &= ~(MAC_CLK_RESET_MAC | MAC_CLK_RESET_SD_RX | MAC_CLK_RESET_SD_TX); 1841 val |= MVPP22_MPCS_CLK_RESET_DIV_SET; 1842 writel(val, mpcs + MVPP22_MPCS_CLK_RESET); 1843 1844 val = readl(xpcs + MVPP22_XPCS_CFG0); 1845 writel(val & ~MVPP22_XPCS_CFG0_RESET_DIS, xpcs + MVPP22_XPCS_CFG0); 1846 } 1847 1848 static void mvpp22_pcs_reset_deassert(struct mvpp2_port *port) 1849 { 1850 struct mvpp2 *priv = port->priv; 1851 void __iomem *mpcs, *xpcs; 1852 u32 val; 1853 1854 if (port->priv->hw_version != MVPP22 || port->gop_id != 0) 1855 return; 1856 1857 mpcs = priv->iface_base + MVPP22_MPCS_BASE(port->gop_id); 1858 xpcs = priv->iface_base + MVPP22_XPCS_BASE(port->gop_id); 1859 1860 switch (port->phy_interface) { 1861 case PHY_INTERFACE_MODE_10GBASER: 1862 val = readl(mpcs + MVPP22_MPCS_CLK_RESET); 1863 val |= MAC_CLK_RESET_MAC | MAC_CLK_RESET_SD_RX | 1864 MAC_CLK_RESET_SD_TX; 1865 val &= ~MVPP22_MPCS_CLK_RESET_DIV_SET; 1866 writel(val, mpcs + MVPP22_MPCS_CLK_RESET); 1867 break; 1868 case PHY_INTERFACE_MODE_XAUI: 1869 case PHY_INTERFACE_MODE_RXAUI: 1870 val = readl(xpcs + MVPP22_XPCS_CFG0); 1871 writel(val | MVPP22_XPCS_CFG0_RESET_DIS, xpcs + MVPP22_XPCS_CFG0); 1872 break; 1873 default: 1874 break; 1875 } 1876 } 1877 1878 /* Change maximum receive size of the port */ 1879 static inline void mvpp2_gmac_max_rx_size_set(struct mvpp2_port *port) 1880 { 1881 u32 val; 1882 1883 val = readl(port->base + MVPP2_GMAC_CTRL_0_REG); 1884 val &= ~MVPP2_GMAC_MAX_RX_SIZE_MASK; 1885 val |= (((port->pkt_size - MVPP2_MH_SIZE) / 2) << 1886 MVPP2_GMAC_MAX_RX_SIZE_OFFS); 1887 writel(val, port->base + MVPP2_GMAC_CTRL_0_REG); 1888 } 1889 1890 /* Change maximum receive size of the port */ 1891 static inline void mvpp2_xlg_max_rx_size_set(struct mvpp2_port *port) 1892 { 1893 u32 val; 1894 1895 val = readl(port->base + MVPP22_XLG_CTRL1_REG); 1896 val &= ~MVPP22_XLG_CTRL1_FRAMESIZELIMIT_MASK; 1897 val |= ((port->pkt_size - MVPP2_MH_SIZE) / 2) << 1898 MVPP22_XLG_CTRL1_FRAMESIZELIMIT_OFFS; 1899 writel(val, port->base + MVPP22_XLG_CTRL1_REG); 1900 } 1901 1902 /* Set defaults to the MVPP2 port */ 1903 static void mvpp2_defaults_set(struct mvpp2_port *port) 1904 { 1905 int tx_port_num, val, queue, lrxq; 1906 1907 if (port->priv->hw_version == MVPP21) { 1908 /* Update TX FIFO MIN Threshold */ 1909 val = readl(port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG); 1910 val &= ~MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK; 1911 /* Min. TX threshold must be less than minimal packet length */ 1912 val |= MVPP2_GMAC_TX_FIFO_MIN_TH_MASK(64 - 4 - 2); 1913 writel(val, port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG); 1914 } 1915 1916 /* Disable Legacy WRR, Disable EJP, Release from reset */ 1917 tx_port_num = mvpp2_egress_port(port); 1918 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, 1919 tx_port_num); 1920 mvpp2_write(port->priv, MVPP2_TXP_SCHED_CMD_1_REG, 0); 1921 1922 /* Set TXQ scheduling to Round-Robin */ 1923 mvpp2_write(port->priv, MVPP2_TXP_SCHED_FIXED_PRIO_REG, 0); 1924 1925 /* Close bandwidth for all queues */ 1926 for (queue = 0; queue < MVPP2_MAX_TXQ; queue++) 1927 mvpp2_write(port->priv, 1928 MVPP2_TXQ_SCHED_TOKEN_CNTR_REG(queue), 0); 1929 1930 /* Set refill period to 1 usec, refill tokens 1931 * and bucket size to maximum 1932 */ 1933 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PERIOD_REG, 1934 port->priv->tclk / USEC_PER_SEC); 1935 val = mvpp2_read(port->priv, MVPP2_TXP_SCHED_REFILL_REG); 1936 val &= ~MVPP2_TXP_REFILL_PERIOD_ALL_MASK; 1937 val |= MVPP2_TXP_REFILL_PERIOD_MASK(1); 1938 val |= MVPP2_TXP_REFILL_TOKENS_ALL_MASK; 1939 mvpp2_write(port->priv, MVPP2_TXP_SCHED_REFILL_REG, val); 1940 val = MVPP2_TXP_TOKEN_SIZE_MAX; 1941 mvpp2_write(port->priv, MVPP2_TXP_SCHED_TOKEN_SIZE_REG, val); 1942 1943 /* Set MaximumLowLatencyPacketSize value to 256 */ 1944 mvpp2_write(port->priv, MVPP2_RX_CTRL_REG(port->id), 1945 MVPP2_RX_USE_PSEUDO_FOR_CSUM_MASK | 1946 MVPP2_RX_LOW_LATENCY_PKT_SIZE(256)); 1947 1948 /* Enable Rx cache snoop */ 1949 for (lrxq = 0; lrxq < port->nrxqs; lrxq++) { 1950 queue = port->rxqs[lrxq]->id; 1951 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(queue)); 1952 val |= MVPP2_SNOOP_PKT_SIZE_MASK | 1953 MVPP2_SNOOP_BUF_HDR_MASK; 1954 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(queue), val); 1955 } 1956 1957 /* At default, mask all interrupts to all present cpus */ 1958 mvpp2_interrupts_disable(port); 1959 } 1960 1961 /* Enable/disable receiving packets */ 1962 static void mvpp2_ingress_enable(struct mvpp2_port *port) 1963 { 1964 u32 val; 1965 int lrxq, queue; 1966 1967 for (lrxq = 0; lrxq < port->nrxqs; lrxq++) { 1968 queue = port->rxqs[lrxq]->id; 1969 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(queue)); 1970 val &= ~MVPP2_RXQ_DISABLE_MASK; 1971 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(queue), val); 1972 } 1973 } 1974 1975 static void mvpp2_ingress_disable(struct mvpp2_port *port) 1976 { 1977 u32 val; 1978 int lrxq, queue; 1979 1980 for (lrxq = 0; lrxq < port->nrxqs; lrxq++) { 1981 queue = port->rxqs[lrxq]->id; 1982 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(queue)); 1983 val |= MVPP2_RXQ_DISABLE_MASK; 1984 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(queue), val); 1985 } 1986 } 1987 1988 /* Enable transmit via physical egress queue 1989 * - HW starts take descriptors from DRAM 1990 */ 1991 static void mvpp2_egress_enable(struct mvpp2_port *port) 1992 { 1993 u32 qmap; 1994 int queue; 1995 int tx_port_num = mvpp2_egress_port(port); 1996 1997 /* Enable all initialized TXs. */ 1998 qmap = 0; 1999 for (queue = 0; queue < port->ntxqs; queue++) { 2000 struct mvpp2_tx_queue *txq = port->txqs[queue]; 2001 2002 if (txq->descs) 2003 qmap |= (1 << queue); 2004 } 2005 2006 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num); 2007 mvpp2_write(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG, qmap); 2008 } 2009 2010 /* Disable transmit via physical egress queue 2011 * - HW doesn't take descriptors from DRAM 2012 */ 2013 static void mvpp2_egress_disable(struct mvpp2_port *port) 2014 { 2015 u32 reg_data; 2016 int delay; 2017 int tx_port_num = mvpp2_egress_port(port); 2018 2019 /* Issue stop command for active channels only */ 2020 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num); 2021 reg_data = (mvpp2_read(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG)) & 2022 MVPP2_TXP_SCHED_ENQ_MASK; 2023 if (reg_data != 0) 2024 mvpp2_write(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG, 2025 (reg_data << MVPP2_TXP_SCHED_DISQ_OFFSET)); 2026 2027 /* Wait for all Tx activity to terminate. */ 2028 delay = 0; 2029 do { 2030 if (delay >= MVPP2_TX_DISABLE_TIMEOUT_MSEC) { 2031 netdev_warn(port->dev, 2032 "Tx stop timed out, status=0x%08x\n", 2033 reg_data); 2034 break; 2035 } 2036 mdelay(1); 2037 delay++; 2038 2039 /* Check port TX Command register that all 2040 * Tx queues are stopped 2041 */ 2042 reg_data = mvpp2_read(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG); 2043 } while (reg_data & MVPP2_TXP_SCHED_ENQ_MASK); 2044 } 2045 2046 /* Rx descriptors helper methods */ 2047 2048 /* Get number of Rx descriptors occupied by received packets */ 2049 static inline int 2050 mvpp2_rxq_received(struct mvpp2_port *port, int rxq_id) 2051 { 2052 u32 val = mvpp2_read(port->priv, MVPP2_RXQ_STATUS_REG(rxq_id)); 2053 2054 return val & MVPP2_RXQ_OCCUPIED_MASK; 2055 } 2056 2057 /* Update Rx queue status with the number of occupied and available 2058 * Rx descriptor slots. 2059 */ 2060 static inline void 2061 mvpp2_rxq_status_update(struct mvpp2_port *port, int rxq_id, 2062 int used_count, int free_count) 2063 { 2064 /* Decrement the number of used descriptors and increment count 2065 * increment the number of free descriptors. 2066 */ 2067 u32 val = used_count | (free_count << MVPP2_RXQ_NUM_NEW_OFFSET); 2068 2069 mvpp2_write(port->priv, MVPP2_RXQ_STATUS_UPDATE_REG(rxq_id), val); 2070 } 2071 2072 /* Get pointer to next RX descriptor to be processed by SW */ 2073 static inline struct mvpp2_rx_desc * 2074 mvpp2_rxq_next_desc_get(struct mvpp2_rx_queue *rxq) 2075 { 2076 int rx_desc = rxq->next_desc_to_proc; 2077 2078 rxq->next_desc_to_proc = MVPP2_QUEUE_NEXT_DESC(rxq, rx_desc); 2079 prefetch(rxq->descs + rxq->next_desc_to_proc); 2080 return rxq->descs + rx_desc; 2081 } 2082 2083 /* Set rx queue offset */ 2084 static void mvpp2_rxq_offset_set(struct mvpp2_port *port, 2085 int prxq, int offset) 2086 { 2087 u32 val; 2088 2089 /* Convert offset from bytes to units of 32 bytes */ 2090 offset = offset >> 5; 2091 2092 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(prxq)); 2093 val &= ~MVPP2_RXQ_PACKET_OFFSET_MASK; 2094 2095 /* Offset is in */ 2096 val |= ((offset << MVPP2_RXQ_PACKET_OFFSET_OFFS) & 2097 MVPP2_RXQ_PACKET_OFFSET_MASK); 2098 2099 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(prxq), val); 2100 } 2101 2102 /* Tx descriptors helper methods */ 2103 2104 /* Get pointer to next Tx descriptor to be processed (send) by HW */ 2105 static struct mvpp2_tx_desc * 2106 mvpp2_txq_next_desc_get(struct mvpp2_tx_queue *txq) 2107 { 2108 int tx_desc = txq->next_desc_to_proc; 2109 2110 txq->next_desc_to_proc = MVPP2_QUEUE_NEXT_DESC(txq, tx_desc); 2111 return txq->descs + tx_desc; 2112 } 2113 2114 /* Update HW with number of aggregated Tx descriptors to be sent 2115 * 2116 * Called only from mvpp2_tx(), so migration is disabled, using 2117 * smp_processor_id() is OK. 2118 */ 2119 static void mvpp2_aggr_txq_pend_desc_add(struct mvpp2_port *port, int pending) 2120 { 2121 /* aggregated access - relevant TXQ number is written in TX desc */ 2122 mvpp2_thread_write(port->priv, 2123 mvpp2_cpu_to_thread(port->priv, smp_processor_id()), 2124 MVPP2_AGGR_TXQ_UPDATE_REG, pending); 2125 } 2126 2127 /* Check if there are enough free descriptors in aggregated txq. 2128 * If not, update the number of occupied descriptors and repeat the check. 2129 * 2130 * Called only from mvpp2_tx(), so migration is disabled, using 2131 * smp_processor_id() is OK. 2132 */ 2133 static int mvpp2_aggr_desc_num_check(struct mvpp2_port *port, 2134 struct mvpp2_tx_queue *aggr_txq, int num) 2135 { 2136 if ((aggr_txq->count + num) > MVPP2_AGGR_TXQ_SIZE) { 2137 /* Update number of occupied aggregated Tx descriptors */ 2138 unsigned int thread = 2139 mvpp2_cpu_to_thread(port->priv, smp_processor_id()); 2140 u32 val = mvpp2_read_relaxed(port->priv, 2141 MVPP2_AGGR_TXQ_STATUS_REG(thread)); 2142 2143 aggr_txq->count = val & MVPP2_AGGR_TXQ_PENDING_MASK; 2144 2145 if ((aggr_txq->count + num) > MVPP2_AGGR_TXQ_SIZE) 2146 return -ENOMEM; 2147 } 2148 return 0; 2149 } 2150 2151 /* Reserved Tx descriptors allocation request 2152 * 2153 * Called only from mvpp2_txq_reserved_desc_num_proc(), itself called 2154 * only by mvpp2_tx(), so migration is disabled, using 2155 * smp_processor_id() is OK. 2156 */ 2157 static int mvpp2_txq_alloc_reserved_desc(struct mvpp2_port *port, 2158 struct mvpp2_tx_queue *txq, int num) 2159 { 2160 unsigned int thread = mvpp2_cpu_to_thread(port->priv, smp_processor_id()); 2161 struct mvpp2 *priv = port->priv; 2162 u32 val; 2163 2164 val = (txq->id << MVPP2_TXQ_RSVD_REQ_Q_OFFSET) | num; 2165 mvpp2_thread_write_relaxed(priv, thread, MVPP2_TXQ_RSVD_REQ_REG, val); 2166 2167 val = mvpp2_thread_read_relaxed(priv, thread, MVPP2_TXQ_RSVD_RSLT_REG); 2168 2169 return val & MVPP2_TXQ_RSVD_RSLT_MASK; 2170 } 2171 2172 /* Check if there are enough reserved descriptors for transmission. 2173 * If not, request chunk of reserved descriptors and check again. 2174 */ 2175 static int mvpp2_txq_reserved_desc_num_proc(struct mvpp2_port *port, 2176 struct mvpp2_tx_queue *txq, 2177 struct mvpp2_txq_pcpu *txq_pcpu, 2178 int num) 2179 { 2180 int req, desc_count; 2181 unsigned int thread; 2182 2183 if (txq_pcpu->reserved_num >= num) 2184 return 0; 2185 2186 /* Not enough descriptors reserved! Update the reserved descriptor 2187 * count and check again. 2188 */ 2189 2190 desc_count = 0; 2191 /* Compute total of used descriptors */ 2192 for (thread = 0; thread < port->priv->nthreads; thread++) { 2193 struct mvpp2_txq_pcpu *txq_pcpu_aux; 2194 2195 txq_pcpu_aux = per_cpu_ptr(txq->pcpu, thread); 2196 desc_count += txq_pcpu_aux->count; 2197 desc_count += txq_pcpu_aux->reserved_num; 2198 } 2199 2200 req = max(MVPP2_CPU_DESC_CHUNK, num - txq_pcpu->reserved_num); 2201 desc_count += req; 2202 2203 if (desc_count > 2204 (txq->size - (MVPP2_MAX_THREADS * MVPP2_CPU_DESC_CHUNK))) 2205 return -ENOMEM; 2206 2207 txq_pcpu->reserved_num += mvpp2_txq_alloc_reserved_desc(port, txq, req); 2208 2209 /* OK, the descriptor could have been updated: check again. */ 2210 if (txq_pcpu->reserved_num < num) 2211 return -ENOMEM; 2212 return 0; 2213 } 2214 2215 /* Release the last allocated Tx descriptor. Useful to handle DMA 2216 * mapping failures in the Tx path. 2217 */ 2218 static void mvpp2_txq_desc_put(struct mvpp2_tx_queue *txq) 2219 { 2220 if (txq->next_desc_to_proc == 0) 2221 txq->next_desc_to_proc = txq->last_desc - 1; 2222 else 2223 txq->next_desc_to_proc--; 2224 } 2225 2226 /* Set Tx descriptors fields relevant for CSUM calculation */ 2227 static u32 mvpp2_txq_desc_csum(int l3_offs, __be16 l3_proto, 2228 int ip_hdr_len, int l4_proto) 2229 { 2230 u32 command; 2231 2232 /* fields: L3_offset, IP_hdrlen, L3_type, G_IPv4_chk, 2233 * G_L4_chk, L4_type required only for checksum calculation 2234 */ 2235 command = (l3_offs << MVPP2_TXD_L3_OFF_SHIFT); 2236 command |= (ip_hdr_len << MVPP2_TXD_IP_HLEN_SHIFT); 2237 command |= MVPP2_TXD_IP_CSUM_DISABLE; 2238 2239 if (l3_proto == htons(ETH_P_IP)) { 2240 command &= ~MVPP2_TXD_IP_CSUM_DISABLE; /* enable IPv4 csum */ 2241 command &= ~MVPP2_TXD_L3_IP6; /* enable IPv4 */ 2242 } else { 2243 command |= MVPP2_TXD_L3_IP6; /* enable IPv6 */ 2244 } 2245 2246 if (l4_proto == IPPROTO_TCP) { 2247 command &= ~MVPP2_TXD_L4_UDP; /* enable TCP */ 2248 command &= ~MVPP2_TXD_L4_CSUM_FRAG; /* generate L4 csum */ 2249 } else if (l4_proto == IPPROTO_UDP) { 2250 command |= MVPP2_TXD_L4_UDP; /* enable UDP */ 2251 command &= ~MVPP2_TXD_L4_CSUM_FRAG; /* generate L4 csum */ 2252 } else { 2253 command |= MVPP2_TXD_L4_CSUM_NOT; 2254 } 2255 2256 return command; 2257 } 2258 2259 /* Get number of sent descriptors and decrement counter. 2260 * The number of sent descriptors is returned. 2261 * Per-thread access 2262 * 2263 * Called only from mvpp2_txq_done(), called from mvpp2_tx() 2264 * (migration disabled) and from the TX completion tasklet (migration 2265 * disabled) so using smp_processor_id() is OK. 2266 */ 2267 static inline int mvpp2_txq_sent_desc_proc(struct mvpp2_port *port, 2268 struct mvpp2_tx_queue *txq) 2269 { 2270 u32 val; 2271 2272 /* Reading status reg resets transmitted descriptor counter */ 2273 val = mvpp2_thread_read_relaxed(port->priv, 2274 mvpp2_cpu_to_thread(port->priv, smp_processor_id()), 2275 MVPP2_TXQ_SENT_REG(txq->id)); 2276 2277 return (val & MVPP2_TRANSMITTED_COUNT_MASK) >> 2278 MVPP2_TRANSMITTED_COUNT_OFFSET; 2279 } 2280 2281 /* Called through on_each_cpu(), so runs on all CPUs, with migration 2282 * disabled, therefore using smp_processor_id() is OK. 2283 */ 2284 static void mvpp2_txq_sent_counter_clear(void *arg) 2285 { 2286 struct mvpp2_port *port = arg; 2287 int queue; 2288 2289 /* If the thread isn't used, don't do anything */ 2290 if (smp_processor_id() > port->priv->nthreads) 2291 return; 2292 2293 for (queue = 0; queue < port->ntxqs; queue++) { 2294 int id = port->txqs[queue]->id; 2295 2296 mvpp2_thread_read(port->priv, 2297 mvpp2_cpu_to_thread(port->priv, smp_processor_id()), 2298 MVPP2_TXQ_SENT_REG(id)); 2299 } 2300 } 2301 2302 /* Set max sizes for Tx queues */ 2303 static void mvpp2_txp_max_tx_size_set(struct mvpp2_port *port) 2304 { 2305 u32 val, size, mtu; 2306 int txq, tx_port_num; 2307 2308 mtu = port->pkt_size * 8; 2309 if (mtu > MVPP2_TXP_MTU_MAX) 2310 mtu = MVPP2_TXP_MTU_MAX; 2311 2312 /* WA for wrong Token bucket update: Set MTU value = 3*real MTU value */ 2313 mtu = 3 * mtu; 2314 2315 /* Indirect access to registers */ 2316 tx_port_num = mvpp2_egress_port(port); 2317 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num); 2318 2319 /* Set MTU */ 2320 val = mvpp2_read(port->priv, MVPP2_TXP_SCHED_MTU_REG); 2321 val &= ~MVPP2_TXP_MTU_MAX; 2322 val |= mtu; 2323 mvpp2_write(port->priv, MVPP2_TXP_SCHED_MTU_REG, val); 2324 2325 /* TXP token size and all TXQs token size must be larger that MTU */ 2326 val = mvpp2_read(port->priv, MVPP2_TXP_SCHED_TOKEN_SIZE_REG); 2327 size = val & MVPP2_TXP_TOKEN_SIZE_MAX; 2328 if (size < mtu) { 2329 size = mtu; 2330 val &= ~MVPP2_TXP_TOKEN_SIZE_MAX; 2331 val |= size; 2332 mvpp2_write(port->priv, MVPP2_TXP_SCHED_TOKEN_SIZE_REG, val); 2333 } 2334 2335 for (txq = 0; txq < port->ntxqs; txq++) { 2336 val = mvpp2_read(port->priv, 2337 MVPP2_TXQ_SCHED_TOKEN_SIZE_REG(txq)); 2338 size = val & MVPP2_TXQ_TOKEN_SIZE_MAX; 2339 2340 if (size < mtu) { 2341 size = mtu; 2342 val &= ~MVPP2_TXQ_TOKEN_SIZE_MAX; 2343 val |= size; 2344 mvpp2_write(port->priv, 2345 MVPP2_TXQ_SCHED_TOKEN_SIZE_REG(txq), 2346 val); 2347 } 2348 } 2349 } 2350 2351 /* Set the number of packets that will be received before Rx interrupt 2352 * will be generated by HW. 2353 */ 2354 static void mvpp2_rx_pkts_coal_set(struct mvpp2_port *port, 2355 struct mvpp2_rx_queue *rxq) 2356 { 2357 unsigned int thread = mvpp2_cpu_to_thread(port->priv, get_cpu()); 2358 2359 if (rxq->pkts_coal > MVPP2_OCCUPIED_THRESH_MASK) 2360 rxq->pkts_coal = MVPP2_OCCUPIED_THRESH_MASK; 2361 2362 mvpp2_thread_write(port->priv, thread, MVPP2_RXQ_NUM_REG, rxq->id); 2363 mvpp2_thread_write(port->priv, thread, MVPP2_RXQ_THRESH_REG, 2364 rxq->pkts_coal); 2365 2366 put_cpu(); 2367 } 2368 2369 /* For some reason in the LSP this is done on each CPU. Why ? */ 2370 static void mvpp2_tx_pkts_coal_set(struct mvpp2_port *port, 2371 struct mvpp2_tx_queue *txq) 2372 { 2373 unsigned int thread = mvpp2_cpu_to_thread(port->priv, get_cpu()); 2374 u32 val; 2375 2376 if (txq->done_pkts_coal > MVPP2_TXQ_THRESH_MASK) 2377 txq->done_pkts_coal = MVPP2_TXQ_THRESH_MASK; 2378 2379 val = (txq->done_pkts_coal << MVPP2_TXQ_THRESH_OFFSET); 2380 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_NUM_REG, txq->id); 2381 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_THRESH_REG, val); 2382 2383 put_cpu(); 2384 } 2385 2386 static u32 mvpp2_usec_to_cycles(u32 usec, unsigned long clk_hz) 2387 { 2388 u64 tmp = (u64)clk_hz * usec; 2389 2390 do_div(tmp, USEC_PER_SEC); 2391 2392 return tmp > U32_MAX ? U32_MAX : tmp; 2393 } 2394 2395 static u32 mvpp2_cycles_to_usec(u32 cycles, unsigned long clk_hz) 2396 { 2397 u64 tmp = (u64)cycles * USEC_PER_SEC; 2398 2399 do_div(tmp, clk_hz); 2400 2401 return tmp > U32_MAX ? U32_MAX : tmp; 2402 } 2403 2404 /* Set the time delay in usec before Rx interrupt */ 2405 static void mvpp2_rx_time_coal_set(struct mvpp2_port *port, 2406 struct mvpp2_rx_queue *rxq) 2407 { 2408 unsigned long freq = port->priv->tclk; 2409 u32 val = mvpp2_usec_to_cycles(rxq->time_coal, freq); 2410 2411 if (val > MVPP2_MAX_ISR_RX_THRESHOLD) { 2412 rxq->time_coal = 2413 mvpp2_cycles_to_usec(MVPP2_MAX_ISR_RX_THRESHOLD, freq); 2414 2415 /* re-evaluate to get actual register value */ 2416 val = mvpp2_usec_to_cycles(rxq->time_coal, freq); 2417 } 2418 2419 mvpp2_write(port->priv, MVPP2_ISR_RX_THRESHOLD_REG(rxq->id), val); 2420 } 2421 2422 static void mvpp2_tx_time_coal_set(struct mvpp2_port *port) 2423 { 2424 unsigned long freq = port->priv->tclk; 2425 u32 val = mvpp2_usec_to_cycles(port->tx_time_coal, freq); 2426 2427 if (val > MVPP2_MAX_ISR_TX_THRESHOLD) { 2428 port->tx_time_coal = 2429 mvpp2_cycles_to_usec(MVPP2_MAX_ISR_TX_THRESHOLD, freq); 2430 2431 /* re-evaluate to get actual register value */ 2432 val = mvpp2_usec_to_cycles(port->tx_time_coal, freq); 2433 } 2434 2435 mvpp2_write(port->priv, MVPP2_ISR_TX_THRESHOLD_REG(port->id), val); 2436 } 2437 2438 /* Free Tx queue skbuffs */ 2439 static void mvpp2_txq_bufs_free(struct mvpp2_port *port, 2440 struct mvpp2_tx_queue *txq, 2441 struct mvpp2_txq_pcpu *txq_pcpu, int num) 2442 { 2443 int i; 2444 2445 for (i = 0; i < num; i++) { 2446 struct mvpp2_txq_pcpu_buf *tx_buf = 2447 txq_pcpu->buffs + txq_pcpu->txq_get_index; 2448 2449 if (!IS_TSO_HEADER(txq_pcpu, tx_buf->dma) && 2450 tx_buf->type != MVPP2_TYPE_XDP_TX) 2451 dma_unmap_single(port->dev->dev.parent, tx_buf->dma, 2452 tx_buf->size, DMA_TO_DEVICE); 2453 if (tx_buf->type == MVPP2_TYPE_SKB && tx_buf->skb) 2454 dev_kfree_skb_any(tx_buf->skb); 2455 else if (tx_buf->type == MVPP2_TYPE_XDP_TX || 2456 tx_buf->type == MVPP2_TYPE_XDP_NDO) 2457 xdp_return_frame(tx_buf->xdpf); 2458 2459 mvpp2_txq_inc_get(txq_pcpu); 2460 } 2461 } 2462 2463 static inline struct mvpp2_rx_queue *mvpp2_get_rx_queue(struct mvpp2_port *port, 2464 u32 cause) 2465 { 2466 int queue = fls(cause) - 1; 2467 2468 return port->rxqs[queue]; 2469 } 2470 2471 static inline struct mvpp2_tx_queue *mvpp2_get_tx_queue(struct mvpp2_port *port, 2472 u32 cause) 2473 { 2474 int queue = fls(cause) - 1; 2475 2476 return port->txqs[queue]; 2477 } 2478 2479 /* Handle end of transmission */ 2480 static void mvpp2_txq_done(struct mvpp2_port *port, struct mvpp2_tx_queue *txq, 2481 struct mvpp2_txq_pcpu *txq_pcpu) 2482 { 2483 struct netdev_queue *nq = netdev_get_tx_queue(port->dev, txq->log_id); 2484 int tx_done; 2485 2486 if (txq_pcpu->thread != mvpp2_cpu_to_thread(port->priv, smp_processor_id())) 2487 netdev_err(port->dev, "wrong cpu on the end of Tx processing\n"); 2488 2489 tx_done = mvpp2_txq_sent_desc_proc(port, txq); 2490 if (!tx_done) 2491 return; 2492 mvpp2_txq_bufs_free(port, txq, txq_pcpu, tx_done); 2493 2494 txq_pcpu->count -= tx_done; 2495 2496 if (netif_tx_queue_stopped(nq)) 2497 if (txq_pcpu->count <= txq_pcpu->wake_threshold) 2498 netif_tx_wake_queue(nq); 2499 } 2500 2501 static unsigned int mvpp2_tx_done(struct mvpp2_port *port, u32 cause, 2502 unsigned int thread) 2503 { 2504 struct mvpp2_tx_queue *txq; 2505 struct mvpp2_txq_pcpu *txq_pcpu; 2506 unsigned int tx_todo = 0; 2507 2508 while (cause) { 2509 txq = mvpp2_get_tx_queue(port, cause); 2510 if (!txq) 2511 break; 2512 2513 txq_pcpu = per_cpu_ptr(txq->pcpu, thread); 2514 2515 if (txq_pcpu->count) { 2516 mvpp2_txq_done(port, txq, txq_pcpu); 2517 tx_todo += txq_pcpu->count; 2518 } 2519 2520 cause &= ~(1 << txq->log_id); 2521 } 2522 return tx_todo; 2523 } 2524 2525 /* Rx/Tx queue initialization/cleanup methods */ 2526 2527 /* Allocate and initialize descriptors for aggr TXQ */ 2528 static int mvpp2_aggr_txq_init(struct platform_device *pdev, 2529 struct mvpp2_tx_queue *aggr_txq, 2530 unsigned int thread, struct mvpp2 *priv) 2531 { 2532 u32 txq_dma; 2533 2534 /* Allocate memory for TX descriptors */ 2535 aggr_txq->descs = dma_alloc_coherent(&pdev->dev, 2536 MVPP2_AGGR_TXQ_SIZE * MVPP2_DESC_ALIGNED_SIZE, 2537 &aggr_txq->descs_dma, GFP_KERNEL); 2538 if (!aggr_txq->descs) 2539 return -ENOMEM; 2540 2541 aggr_txq->last_desc = MVPP2_AGGR_TXQ_SIZE - 1; 2542 2543 /* Aggr TXQ no reset WA */ 2544 aggr_txq->next_desc_to_proc = mvpp2_read(priv, 2545 MVPP2_AGGR_TXQ_INDEX_REG(thread)); 2546 2547 /* Set Tx descriptors queue starting address indirect 2548 * access 2549 */ 2550 if (priv->hw_version == MVPP21) 2551 txq_dma = aggr_txq->descs_dma; 2552 else 2553 txq_dma = aggr_txq->descs_dma >> 2554 MVPP22_AGGR_TXQ_DESC_ADDR_OFFS; 2555 2556 mvpp2_write(priv, MVPP2_AGGR_TXQ_DESC_ADDR_REG(thread), txq_dma); 2557 mvpp2_write(priv, MVPP2_AGGR_TXQ_DESC_SIZE_REG(thread), 2558 MVPP2_AGGR_TXQ_SIZE); 2559 2560 return 0; 2561 } 2562 2563 /* Create a specified Rx queue */ 2564 static int mvpp2_rxq_init(struct mvpp2_port *port, 2565 struct mvpp2_rx_queue *rxq) 2566 { 2567 struct mvpp2 *priv = port->priv; 2568 unsigned int thread; 2569 u32 rxq_dma; 2570 int err; 2571 2572 rxq->size = port->rx_ring_size; 2573 2574 /* Allocate memory for RX descriptors */ 2575 rxq->descs = dma_alloc_coherent(port->dev->dev.parent, 2576 rxq->size * MVPP2_DESC_ALIGNED_SIZE, 2577 &rxq->descs_dma, GFP_KERNEL); 2578 if (!rxq->descs) 2579 return -ENOMEM; 2580 2581 rxq->last_desc = rxq->size - 1; 2582 2583 /* Zero occupied and non-occupied counters - direct access */ 2584 mvpp2_write(port->priv, MVPP2_RXQ_STATUS_REG(rxq->id), 0); 2585 2586 /* Set Rx descriptors queue starting address - indirect access */ 2587 thread = mvpp2_cpu_to_thread(port->priv, get_cpu()); 2588 mvpp2_thread_write(port->priv, thread, MVPP2_RXQ_NUM_REG, rxq->id); 2589 if (port->priv->hw_version == MVPP21) 2590 rxq_dma = rxq->descs_dma; 2591 else 2592 rxq_dma = rxq->descs_dma >> MVPP22_DESC_ADDR_OFFS; 2593 mvpp2_thread_write(port->priv, thread, MVPP2_RXQ_DESC_ADDR_REG, rxq_dma); 2594 mvpp2_thread_write(port->priv, thread, MVPP2_RXQ_DESC_SIZE_REG, rxq->size); 2595 mvpp2_thread_write(port->priv, thread, MVPP2_RXQ_INDEX_REG, 0); 2596 put_cpu(); 2597 2598 /* Set Offset */ 2599 mvpp2_rxq_offset_set(port, rxq->id, MVPP2_SKB_HEADROOM); 2600 2601 /* Set coalescing pkts and time */ 2602 mvpp2_rx_pkts_coal_set(port, rxq); 2603 mvpp2_rx_time_coal_set(port, rxq); 2604 2605 /* Add number of descriptors ready for receiving packets */ 2606 mvpp2_rxq_status_update(port, rxq->id, 0, rxq->size); 2607 2608 if (priv->percpu_pools) { 2609 err = xdp_rxq_info_reg(&rxq->xdp_rxq_short, port->dev, rxq->id); 2610 if (err < 0) 2611 goto err_free_dma; 2612 2613 err = xdp_rxq_info_reg(&rxq->xdp_rxq_long, port->dev, rxq->id); 2614 if (err < 0) 2615 goto err_unregister_rxq_short; 2616 2617 /* Every RXQ has a pool for short and another for long packets */ 2618 err = xdp_rxq_info_reg_mem_model(&rxq->xdp_rxq_short, 2619 MEM_TYPE_PAGE_POOL, 2620 priv->page_pool[rxq->logic_rxq]); 2621 if (err < 0) 2622 goto err_unregister_rxq_long; 2623 2624 err = xdp_rxq_info_reg_mem_model(&rxq->xdp_rxq_long, 2625 MEM_TYPE_PAGE_POOL, 2626 priv->page_pool[rxq->logic_rxq + 2627 port->nrxqs]); 2628 if (err < 0) 2629 goto err_unregister_mem_rxq_short; 2630 } 2631 2632 return 0; 2633 2634 err_unregister_mem_rxq_short: 2635 xdp_rxq_info_unreg_mem_model(&rxq->xdp_rxq_short); 2636 err_unregister_rxq_long: 2637 xdp_rxq_info_unreg(&rxq->xdp_rxq_long); 2638 err_unregister_rxq_short: 2639 xdp_rxq_info_unreg(&rxq->xdp_rxq_short); 2640 err_free_dma: 2641 dma_free_coherent(port->dev->dev.parent, 2642 rxq->size * MVPP2_DESC_ALIGNED_SIZE, 2643 rxq->descs, rxq->descs_dma); 2644 return err; 2645 } 2646 2647 /* Push packets received by the RXQ to BM pool */ 2648 static void mvpp2_rxq_drop_pkts(struct mvpp2_port *port, 2649 struct mvpp2_rx_queue *rxq) 2650 { 2651 int rx_received, i; 2652 2653 rx_received = mvpp2_rxq_received(port, rxq->id); 2654 if (!rx_received) 2655 return; 2656 2657 for (i = 0; i < rx_received; i++) { 2658 struct mvpp2_rx_desc *rx_desc = mvpp2_rxq_next_desc_get(rxq); 2659 u32 status = mvpp2_rxdesc_status_get(port, rx_desc); 2660 int pool; 2661 2662 pool = (status & MVPP2_RXD_BM_POOL_ID_MASK) >> 2663 MVPP2_RXD_BM_POOL_ID_OFFS; 2664 2665 mvpp2_bm_pool_put(port, pool, 2666 mvpp2_rxdesc_dma_addr_get(port, rx_desc), 2667 mvpp2_rxdesc_cookie_get(port, rx_desc)); 2668 } 2669 mvpp2_rxq_status_update(port, rxq->id, rx_received, rx_received); 2670 } 2671 2672 /* Cleanup Rx queue */ 2673 static void mvpp2_rxq_deinit(struct mvpp2_port *port, 2674 struct mvpp2_rx_queue *rxq) 2675 { 2676 unsigned int thread; 2677 2678 if (xdp_rxq_info_is_reg(&rxq->xdp_rxq_short)) 2679 xdp_rxq_info_unreg(&rxq->xdp_rxq_short); 2680 2681 if (xdp_rxq_info_is_reg(&rxq->xdp_rxq_long)) 2682 xdp_rxq_info_unreg(&rxq->xdp_rxq_long); 2683 2684 mvpp2_rxq_drop_pkts(port, rxq); 2685 2686 if (rxq->descs) 2687 dma_free_coherent(port->dev->dev.parent, 2688 rxq->size * MVPP2_DESC_ALIGNED_SIZE, 2689 rxq->descs, 2690 rxq->descs_dma); 2691 2692 rxq->descs = NULL; 2693 rxq->last_desc = 0; 2694 rxq->next_desc_to_proc = 0; 2695 rxq->descs_dma = 0; 2696 2697 /* Clear Rx descriptors queue starting address and size; 2698 * free descriptor number 2699 */ 2700 mvpp2_write(port->priv, MVPP2_RXQ_STATUS_REG(rxq->id), 0); 2701 thread = mvpp2_cpu_to_thread(port->priv, get_cpu()); 2702 mvpp2_thread_write(port->priv, thread, MVPP2_RXQ_NUM_REG, rxq->id); 2703 mvpp2_thread_write(port->priv, thread, MVPP2_RXQ_DESC_ADDR_REG, 0); 2704 mvpp2_thread_write(port->priv, thread, MVPP2_RXQ_DESC_SIZE_REG, 0); 2705 put_cpu(); 2706 } 2707 2708 /* Create and initialize a Tx queue */ 2709 static int mvpp2_txq_init(struct mvpp2_port *port, 2710 struct mvpp2_tx_queue *txq) 2711 { 2712 u32 val; 2713 unsigned int thread; 2714 int desc, desc_per_txq, tx_port_num; 2715 struct mvpp2_txq_pcpu *txq_pcpu; 2716 2717 txq->size = port->tx_ring_size; 2718 2719 /* Allocate memory for Tx descriptors */ 2720 txq->descs = dma_alloc_coherent(port->dev->dev.parent, 2721 txq->size * MVPP2_DESC_ALIGNED_SIZE, 2722 &txq->descs_dma, GFP_KERNEL); 2723 if (!txq->descs) 2724 return -ENOMEM; 2725 2726 txq->last_desc = txq->size - 1; 2727 2728 /* Set Tx descriptors queue starting address - indirect access */ 2729 thread = mvpp2_cpu_to_thread(port->priv, get_cpu()); 2730 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_NUM_REG, txq->id); 2731 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_DESC_ADDR_REG, 2732 txq->descs_dma); 2733 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_DESC_SIZE_REG, 2734 txq->size & MVPP2_TXQ_DESC_SIZE_MASK); 2735 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_INDEX_REG, 0); 2736 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_RSVD_CLR_REG, 2737 txq->id << MVPP2_TXQ_RSVD_CLR_OFFSET); 2738 val = mvpp2_thread_read(port->priv, thread, MVPP2_TXQ_PENDING_REG); 2739 val &= ~MVPP2_TXQ_PENDING_MASK; 2740 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_PENDING_REG, val); 2741 2742 /* Calculate base address in prefetch buffer. We reserve 16 descriptors 2743 * for each existing TXQ. 2744 * TCONTS for PON port must be continuous from 0 to MVPP2_MAX_TCONT 2745 * GBE ports assumed to be continuous from 0 to MVPP2_MAX_PORTS 2746 */ 2747 desc_per_txq = 16; 2748 desc = (port->id * MVPP2_MAX_TXQ * desc_per_txq) + 2749 (txq->log_id * desc_per_txq); 2750 2751 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_PREF_BUF_REG, 2752 MVPP2_PREF_BUF_PTR(desc) | MVPP2_PREF_BUF_SIZE_16 | 2753 MVPP2_PREF_BUF_THRESH(desc_per_txq / 2)); 2754 put_cpu(); 2755 2756 /* WRR / EJP configuration - indirect access */ 2757 tx_port_num = mvpp2_egress_port(port); 2758 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num); 2759 2760 val = mvpp2_read(port->priv, MVPP2_TXQ_SCHED_REFILL_REG(txq->log_id)); 2761 val &= ~MVPP2_TXQ_REFILL_PERIOD_ALL_MASK; 2762 val |= MVPP2_TXQ_REFILL_PERIOD_MASK(1); 2763 val |= MVPP2_TXQ_REFILL_TOKENS_ALL_MASK; 2764 mvpp2_write(port->priv, MVPP2_TXQ_SCHED_REFILL_REG(txq->log_id), val); 2765 2766 val = MVPP2_TXQ_TOKEN_SIZE_MAX; 2767 mvpp2_write(port->priv, MVPP2_TXQ_SCHED_TOKEN_SIZE_REG(txq->log_id), 2768 val); 2769 2770 for (thread = 0; thread < port->priv->nthreads; thread++) { 2771 txq_pcpu = per_cpu_ptr(txq->pcpu, thread); 2772 txq_pcpu->size = txq->size; 2773 txq_pcpu->buffs = kmalloc_array(txq_pcpu->size, 2774 sizeof(*txq_pcpu->buffs), 2775 GFP_KERNEL); 2776 if (!txq_pcpu->buffs) 2777 return -ENOMEM; 2778 2779 txq_pcpu->count = 0; 2780 txq_pcpu->reserved_num = 0; 2781 txq_pcpu->txq_put_index = 0; 2782 txq_pcpu->txq_get_index = 0; 2783 txq_pcpu->tso_headers = NULL; 2784 2785 txq_pcpu->stop_threshold = txq->size - MVPP2_MAX_SKB_DESCS; 2786 txq_pcpu->wake_threshold = txq_pcpu->stop_threshold / 2; 2787 2788 txq_pcpu->tso_headers = 2789 dma_alloc_coherent(port->dev->dev.parent, 2790 txq_pcpu->size * TSO_HEADER_SIZE, 2791 &txq_pcpu->tso_headers_dma, 2792 GFP_KERNEL); 2793 if (!txq_pcpu->tso_headers) 2794 return -ENOMEM; 2795 } 2796 2797 return 0; 2798 } 2799 2800 /* Free allocated TXQ resources */ 2801 static void mvpp2_txq_deinit(struct mvpp2_port *port, 2802 struct mvpp2_tx_queue *txq) 2803 { 2804 struct mvpp2_txq_pcpu *txq_pcpu; 2805 unsigned int thread; 2806 2807 for (thread = 0; thread < port->priv->nthreads; thread++) { 2808 txq_pcpu = per_cpu_ptr(txq->pcpu, thread); 2809 kfree(txq_pcpu->buffs); 2810 2811 if (txq_pcpu->tso_headers) 2812 dma_free_coherent(port->dev->dev.parent, 2813 txq_pcpu->size * TSO_HEADER_SIZE, 2814 txq_pcpu->tso_headers, 2815 txq_pcpu->tso_headers_dma); 2816 2817 txq_pcpu->tso_headers = NULL; 2818 } 2819 2820 if (txq->descs) 2821 dma_free_coherent(port->dev->dev.parent, 2822 txq->size * MVPP2_DESC_ALIGNED_SIZE, 2823 txq->descs, txq->descs_dma); 2824 2825 txq->descs = NULL; 2826 txq->last_desc = 0; 2827 txq->next_desc_to_proc = 0; 2828 txq->descs_dma = 0; 2829 2830 /* Set minimum bandwidth for disabled TXQs */ 2831 mvpp2_write(port->priv, MVPP2_TXQ_SCHED_TOKEN_CNTR_REG(txq->log_id), 0); 2832 2833 /* Set Tx descriptors queue starting address and size */ 2834 thread = mvpp2_cpu_to_thread(port->priv, get_cpu()); 2835 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_NUM_REG, txq->id); 2836 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_DESC_ADDR_REG, 0); 2837 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_DESC_SIZE_REG, 0); 2838 put_cpu(); 2839 } 2840 2841 /* Cleanup Tx ports */ 2842 static void mvpp2_txq_clean(struct mvpp2_port *port, struct mvpp2_tx_queue *txq) 2843 { 2844 struct mvpp2_txq_pcpu *txq_pcpu; 2845 int delay, pending; 2846 unsigned int thread = mvpp2_cpu_to_thread(port->priv, get_cpu()); 2847 u32 val; 2848 2849 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_NUM_REG, txq->id); 2850 val = mvpp2_thread_read(port->priv, thread, MVPP2_TXQ_PREF_BUF_REG); 2851 val |= MVPP2_TXQ_DRAIN_EN_MASK; 2852 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_PREF_BUF_REG, val); 2853 2854 /* The napi queue has been stopped so wait for all packets 2855 * to be transmitted. 2856 */ 2857 delay = 0; 2858 do { 2859 if (delay >= MVPP2_TX_PENDING_TIMEOUT_MSEC) { 2860 netdev_warn(port->dev, 2861 "port %d: cleaning queue %d timed out\n", 2862 port->id, txq->log_id); 2863 break; 2864 } 2865 mdelay(1); 2866 delay++; 2867 2868 pending = mvpp2_thread_read(port->priv, thread, 2869 MVPP2_TXQ_PENDING_REG); 2870 pending &= MVPP2_TXQ_PENDING_MASK; 2871 } while (pending); 2872 2873 val &= ~MVPP2_TXQ_DRAIN_EN_MASK; 2874 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_PREF_BUF_REG, val); 2875 put_cpu(); 2876 2877 for (thread = 0; thread < port->priv->nthreads; thread++) { 2878 txq_pcpu = per_cpu_ptr(txq->pcpu, thread); 2879 2880 /* Release all packets */ 2881 mvpp2_txq_bufs_free(port, txq, txq_pcpu, txq_pcpu->count); 2882 2883 /* Reset queue */ 2884 txq_pcpu->count = 0; 2885 txq_pcpu->txq_put_index = 0; 2886 txq_pcpu->txq_get_index = 0; 2887 } 2888 } 2889 2890 /* Cleanup all Tx queues */ 2891 static void mvpp2_cleanup_txqs(struct mvpp2_port *port) 2892 { 2893 struct mvpp2_tx_queue *txq; 2894 int queue; 2895 u32 val; 2896 2897 val = mvpp2_read(port->priv, MVPP2_TX_PORT_FLUSH_REG); 2898 2899 /* Reset Tx ports and delete Tx queues */ 2900 val |= MVPP2_TX_PORT_FLUSH_MASK(port->id); 2901 mvpp2_write(port->priv, MVPP2_TX_PORT_FLUSH_REG, val); 2902 2903 for (queue = 0; queue < port->ntxqs; queue++) { 2904 txq = port->txqs[queue]; 2905 mvpp2_txq_clean(port, txq); 2906 mvpp2_txq_deinit(port, txq); 2907 } 2908 2909 on_each_cpu(mvpp2_txq_sent_counter_clear, port, 1); 2910 2911 val &= ~MVPP2_TX_PORT_FLUSH_MASK(port->id); 2912 mvpp2_write(port->priv, MVPP2_TX_PORT_FLUSH_REG, val); 2913 } 2914 2915 /* Cleanup all Rx queues */ 2916 static void mvpp2_cleanup_rxqs(struct mvpp2_port *port) 2917 { 2918 int queue; 2919 2920 for (queue = 0; queue < port->nrxqs; queue++) 2921 mvpp2_rxq_deinit(port, port->rxqs[queue]); 2922 } 2923 2924 /* Init all Rx queues for port */ 2925 static int mvpp2_setup_rxqs(struct mvpp2_port *port) 2926 { 2927 int queue, err; 2928 2929 for (queue = 0; queue < port->nrxqs; queue++) { 2930 err = mvpp2_rxq_init(port, port->rxqs[queue]); 2931 if (err) 2932 goto err_cleanup; 2933 } 2934 return 0; 2935 2936 err_cleanup: 2937 mvpp2_cleanup_rxqs(port); 2938 return err; 2939 } 2940 2941 /* Init all tx queues for port */ 2942 static int mvpp2_setup_txqs(struct mvpp2_port *port) 2943 { 2944 struct mvpp2_tx_queue *txq; 2945 int queue, err; 2946 2947 for (queue = 0; queue < port->ntxqs; queue++) { 2948 txq = port->txqs[queue]; 2949 err = mvpp2_txq_init(port, txq); 2950 if (err) 2951 goto err_cleanup; 2952 2953 /* Assign this queue to a CPU */ 2954 if (queue < num_possible_cpus()) 2955 netif_set_xps_queue(port->dev, cpumask_of(queue), queue); 2956 } 2957 2958 if (port->has_tx_irqs) { 2959 mvpp2_tx_time_coal_set(port); 2960 for (queue = 0; queue < port->ntxqs; queue++) { 2961 txq = port->txqs[queue]; 2962 mvpp2_tx_pkts_coal_set(port, txq); 2963 } 2964 } 2965 2966 on_each_cpu(mvpp2_txq_sent_counter_clear, port, 1); 2967 return 0; 2968 2969 err_cleanup: 2970 mvpp2_cleanup_txqs(port); 2971 return err; 2972 } 2973 2974 /* The callback for per-port interrupt */ 2975 static irqreturn_t mvpp2_isr(int irq, void *dev_id) 2976 { 2977 struct mvpp2_queue_vector *qv = dev_id; 2978 2979 mvpp2_qvec_interrupt_disable(qv); 2980 2981 napi_schedule(&qv->napi); 2982 2983 return IRQ_HANDLED; 2984 } 2985 2986 static void mvpp2_isr_handle_ptp_queue(struct mvpp2_port *port, int nq) 2987 { 2988 struct skb_shared_hwtstamps shhwtstamps; 2989 struct mvpp2_hwtstamp_queue *queue; 2990 struct sk_buff *skb; 2991 void __iomem *ptp_q; 2992 unsigned int id; 2993 u32 r0, r1, r2; 2994 2995 ptp_q = port->priv->iface_base + MVPP22_PTP_BASE(port->gop_id); 2996 if (nq) 2997 ptp_q += MVPP22_PTP_TX_Q1_R0 - MVPP22_PTP_TX_Q0_R0; 2998 2999 queue = &port->tx_hwtstamp_queue[nq]; 3000 3001 while (1) { 3002 r0 = readl_relaxed(ptp_q + MVPP22_PTP_TX_Q0_R0) & 0xffff; 3003 if (!r0) 3004 break; 3005 3006 r1 = readl_relaxed(ptp_q + MVPP22_PTP_TX_Q0_R1) & 0xffff; 3007 r2 = readl_relaxed(ptp_q + MVPP22_PTP_TX_Q0_R2) & 0xffff; 3008 3009 id = (r0 >> 1) & 31; 3010 3011 skb = queue->skb[id]; 3012 queue->skb[id] = NULL; 3013 if (skb) { 3014 u32 ts = r2 << 19 | r1 << 3 | r0 >> 13; 3015 3016 mvpp22_tai_tstamp(port->priv->tai, ts, &shhwtstamps); 3017 skb_tstamp_tx(skb, &shhwtstamps); 3018 dev_kfree_skb_any(skb); 3019 } 3020 } 3021 } 3022 3023 static void mvpp2_isr_handle_ptp(struct mvpp2_port *port) 3024 { 3025 void __iomem *ptp; 3026 u32 val; 3027 3028 ptp = port->priv->iface_base + MVPP22_PTP_BASE(port->gop_id); 3029 val = readl(ptp + MVPP22_PTP_INT_CAUSE); 3030 if (val & MVPP22_PTP_INT_CAUSE_QUEUE0) 3031 mvpp2_isr_handle_ptp_queue(port, 0); 3032 if (val & MVPP22_PTP_INT_CAUSE_QUEUE1) 3033 mvpp2_isr_handle_ptp_queue(port, 1); 3034 } 3035 3036 static void mvpp2_isr_handle_link(struct mvpp2_port *port, bool link) 3037 { 3038 struct net_device *dev = port->dev; 3039 3040 if (port->phylink) { 3041 phylink_mac_change(port->phylink, link); 3042 return; 3043 } 3044 3045 if (!netif_running(dev)) 3046 return; 3047 3048 if (link) { 3049 mvpp2_interrupts_enable(port); 3050 3051 mvpp2_egress_enable(port); 3052 mvpp2_ingress_enable(port); 3053 netif_carrier_on(dev); 3054 netif_tx_wake_all_queues(dev); 3055 } else { 3056 netif_tx_stop_all_queues(dev); 3057 netif_carrier_off(dev); 3058 mvpp2_ingress_disable(port); 3059 mvpp2_egress_disable(port); 3060 3061 mvpp2_interrupts_disable(port); 3062 } 3063 } 3064 3065 static void mvpp2_isr_handle_xlg(struct mvpp2_port *port) 3066 { 3067 bool link; 3068 u32 val; 3069 3070 val = readl(port->base + MVPP22_XLG_INT_STAT); 3071 if (val & MVPP22_XLG_INT_STAT_LINK) { 3072 val = readl(port->base + MVPP22_XLG_STATUS); 3073 link = (val & MVPP22_XLG_STATUS_LINK_UP); 3074 mvpp2_isr_handle_link(port, link); 3075 } 3076 } 3077 3078 static void mvpp2_isr_handle_gmac_internal(struct mvpp2_port *port) 3079 { 3080 bool link; 3081 u32 val; 3082 3083 if (phy_interface_mode_is_rgmii(port->phy_interface) || 3084 phy_interface_mode_is_8023z(port->phy_interface) || 3085 port->phy_interface == PHY_INTERFACE_MODE_SGMII) { 3086 val = readl(port->base + MVPP22_GMAC_INT_STAT); 3087 if (val & MVPP22_GMAC_INT_STAT_LINK) { 3088 val = readl(port->base + MVPP2_GMAC_STATUS0); 3089 link = (val & MVPP2_GMAC_STATUS0_LINK_UP); 3090 mvpp2_isr_handle_link(port, link); 3091 } 3092 } 3093 } 3094 3095 /* Per-port interrupt for link status changes */ 3096 static irqreturn_t mvpp2_port_isr(int irq, void *dev_id) 3097 { 3098 struct mvpp2_port *port = (struct mvpp2_port *)dev_id; 3099 u32 val; 3100 3101 mvpp22_gop_mask_irq(port); 3102 3103 if (mvpp2_port_supports_xlg(port) && 3104 mvpp2_is_xlg(port->phy_interface)) { 3105 /* Check the external status register */ 3106 val = readl(port->base + MVPP22_XLG_EXT_INT_STAT); 3107 if (val & MVPP22_XLG_EXT_INT_STAT_XLG) 3108 mvpp2_isr_handle_xlg(port); 3109 if (val & MVPP22_XLG_EXT_INT_STAT_PTP) 3110 mvpp2_isr_handle_ptp(port); 3111 } else { 3112 /* If it's not the XLG, we must be using the GMAC. 3113 * Check the summary status. 3114 */ 3115 val = readl(port->base + MVPP22_GMAC_INT_SUM_STAT); 3116 if (val & MVPP22_GMAC_INT_SUM_STAT_INTERNAL) 3117 mvpp2_isr_handle_gmac_internal(port); 3118 if (val & MVPP22_GMAC_INT_SUM_STAT_PTP) 3119 mvpp2_isr_handle_ptp(port); 3120 } 3121 3122 mvpp22_gop_unmask_irq(port); 3123 return IRQ_HANDLED; 3124 } 3125 3126 static enum hrtimer_restart mvpp2_hr_timer_cb(struct hrtimer *timer) 3127 { 3128 struct net_device *dev; 3129 struct mvpp2_port *port; 3130 struct mvpp2_port_pcpu *port_pcpu; 3131 unsigned int tx_todo, cause; 3132 3133 port_pcpu = container_of(timer, struct mvpp2_port_pcpu, tx_done_timer); 3134 dev = port_pcpu->dev; 3135 3136 if (!netif_running(dev)) 3137 return HRTIMER_NORESTART; 3138 3139 port_pcpu->timer_scheduled = false; 3140 port = netdev_priv(dev); 3141 3142 /* Process all the Tx queues */ 3143 cause = (1 << port->ntxqs) - 1; 3144 tx_todo = mvpp2_tx_done(port, cause, 3145 mvpp2_cpu_to_thread(port->priv, smp_processor_id())); 3146 3147 /* Set the timer in case not all the packets were processed */ 3148 if (tx_todo && !port_pcpu->timer_scheduled) { 3149 port_pcpu->timer_scheduled = true; 3150 hrtimer_forward_now(&port_pcpu->tx_done_timer, 3151 MVPP2_TXDONE_HRTIMER_PERIOD_NS); 3152 3153 return HRTIMER_RESTART; 3154 } 3155 return HRTIMER_NORESTART; 3156 } 3157 3158 /* Main RX/TX processing routines */ 3159 3160 /* Display more error info */ 3161 static void mvpp2_rx_error(struct mvpp2_port *port, 3162 struct mvpp2_rx_desc *rx_desc) 3163 { 3164 u32 status = mvpp2_rxdesc_status_get(port, rx_desc); 3165 size_t sz = mvpp2_rxdesc_size_get(port, rx_desc); 3166 char *err_str = NULL; 3167 3168 switch (status & MVPP2_RXD_ERR_CODE_MASK) { 3169 case MVPP2_RXD_ERR_CRC: 3170 err_str = "crc"; 3171 break; 3172 case MVPP2_RXD_ERR_OVERRUN: 3173 err_str = "overrun"; 3174 break; 3175 case MVPP2_RXD_ERR_RESOURCE: 3176 err_str = "resource"; 3177 break; 3178 } 3179 if (err_str && net_ratelimit()) 3180 netdev_err(port->dev, 3181 "bad rx status %08x (%s error), size=%zu\n", 3182 status, err_str, sz); 3183 } 3184 3185 /* Handle RX checksum offload */ 3186 static void mvpp2_rx_csum(struct mvpp2_port *port, u32 status, 3187 struct sk_buff *skb) 3188 { 3189 if (((status & MVPP2_RXD_L3_IP4) && 3190 !(status & MVPP2_RXD_IP4_HEADER_ERR)) || 3191 (status & MVPP2_RXD_L3_IP6)) 3192 if (((status & MVPP2_RXD_L4_UDP) || 3193 (status & MVPP2_RXD_L4_TCP)) && 3194 (status & MVPP2_RXD_L4_CSUM_OK)) { 3195 skb->csum = 0; 3196 skb->ip_summed = CHECKSUM_UNNECESSARY; 3197 return; 3198 } 3199 3200 skb->ip_summed = CHECKSUM_NONE; 3201 } 3202 3203 /* Allocate a new skb and add it to BM pool */ 3204 static int mvpp2_rx_refill(struct mvpp2_port *port, 3205 struct mvpp2_bm_pool *bm_pool, 3206 struct page_pool *page_pool, int pool) 3207 { 3208 dma_addr_t dma_addr; 3209 phys_addr_t phys_addr; 3210 void *buf; 3211 3212 buf = mvpp2_buf_alloc(port, bm_pool, page_pool, 3213 &dma_addr, &phys_addr, GFP_ATOMIC); 3214 if (!buf) 3215 return -ENOMEM; 3216 3217 mvpp2_bm_pool_put(port, pool, dma_addr, phys_addr); 3218 3219 return 0; 3220 } 3221 3222 /* Handle tx checksum */ 3223 static u32 mvpp2_skb_tx_csum(struct mvpp2_port *port, struct sk_buff *skb) 3224 { 3225 if (skb->ip_summed == CHECKSUM_PARTIAL) { 3226 int ip_hdr_len = 0; 3227 u8 l4_proto; 3228 __be16 l3_proto = vlan_get_protocol(skb); 3229 3230 if (l3_proto == htons(ETH_P_IP)) { 3231 struct iphdr *ip4h = ip_hdr(skb); 3232 3233 /* Calculate IPv4 checksum and L4 checksum */ 3234 ip_hdr_len = ip4h->ihl; 3235 l4_proto = ip4h->protocol; 3236 } else if (l3_proto == htons(ETH_P_IPV6)) { 3237 struct ipv6hdr *ip6h = ipv6_hdr(skb); 3238 3239 /* Read l4_protocol from one of IPv6 extra headers */ 3240 if (skb_network_header_len(skb) > 0) 3241 ip_hdr_len = (skb_network_header_len(skb) >> 2); 3242 l4_proto = ip6h->nexthdr; 3243 } else { 3244 return MVPP2_TXD_L4_CSUM_NOT; 3245 } 3246 3247 return mvpp2_txq_desc_csum(skb_network_offset(skb), 3248 l3_proto, ip_hdr_len, l4_proto); 3249 } 3250 3251 return MVPP2_TXD_L4_CSUM_NOT | MVPP2_TXD_IP_CSUM_DISABLE; 3252 } 3253 3254 static void mvpp2_xdp_finish_tx(struct mvpp2_port *port, u16 txq_id, int nxmit, int nxmit_byte) 3255 { 3256 unsigned int thread = mvpp2_cpu_to_thread(port->priv, smp_processor_id()); 3257 struct mvpp2_tx_queue *aggr_txq; 3258 struct mvpp2_txq_pcpu *txq_pcpu; 3259 struct mvpp2_tx_queue *txq; 3260 struct netdev_queue *nq; 3261 3262 txq = port->txqs[txq_id]; 3263 txq_pcpu = per_cpu_ptr(txq->pcpu, thread); 3264 nq = netdev_get_tx_queue(port->dev, txq_id); 3265 aggr_txq = &port->priv->aggr_txqs[thread]; 3266 3267 txq_pcpu->reserved_num -= nxmit; 3268 txq_pcpu->count += nxmit; 3269 aggr_txq->count += nxmit; 3270 3271 /* Enable transmit */ 3272 wmb(); 3273 mvpp2_aggr_txq_pend_desc_add(port, nxmit); 3274 3275 if (txq_pcpu->count >= txq_pcpu->stop_threshold) 3276 netif_tx_stop_queue(nq); 3277 3278 /* Finalize TX processing */ 3279 if (!port->has_tx_irqs && txq_pcpu->count >= txq->done_pkts_coal) 3280 mvpp2_txq_done(port, txq, txq_pcpu); 3281 } 3282 3283 static int 3284 mvpp2_xdp_submit_frame(struct mvpp2_port *port, u16 txq_id, 3285 struct xdp_frame *xdpf, bool dma_map) 3286 { 3287 unsigned int thread = mvpp2_cpu_to_thread(port->priv, smp_processor_id()); 3288 u32 tx_cmd = MVPP2_TXD_L4_CSUM_NOT | MVPP2_TXD_IP_CSUM_DISABLE | 3289 MVPP2_TXD_F_DESC | MVPP2_TXD_L_DESC; 3290 enum mvpp2_tx_buf_type buf_type; 3291 struct mvpp2_txq_pcpu *txq_pcpu; 3292 struct mvpp2_tx_queue *aggr_txq; 3293 struct mvpp2_tx_desc *tx_desc; 3294 struct mvpp2_tx_queue *txq; 3295 int ret = MVPP2_XDP_TX; 3296 dma_addr_t dma_addr; 3297 3298 txq = port->txqs[txq_id]; 3299 txq_pcpu = per_cpu_ptr(txq->pcpu, thread); 3300 aggr_txq = &port->priv->aggr_txqs[thread]; 3301 3302 /* Check number of available descriptors */ 3303 if (mvpp2_aggr_desc_num_check(port, aggr_txq, 1) || 3304 mvpp2_txq_reserved_desc_num_proc(port, txq, txq_pcpu, 1)) { 3305 ret = MVPP2_XDP_DROPPED; 3306 goto out; 3307 } 3308 3309 /* Get a descriptor for the first part of the packet */ 3310 tx_desc = mvpp2_txq_next_desc_get(aggr_txq); 3311 mvpp2_txdesc_txq_set(port, tx_desc, txq->id); 3312 mvpp2_txdesc_size_set(port, tx_desc, xdpf->len); 3313 3314 if (dma_map) { 3315 /* XDP_REDIRECT or AF_XDP */ 3316 dma_addr = dma_map_single(port->dev->dev.parent, xdpf->data, 3317 xdpf->len, DMA_TO_DEVICE); 3318 3319 if (unlikely(dma_mapping_error(port->dev->dev.parent, dma_addr))) { 3320 mvpp2_txq_desc_put(txq); 3321 ret = MVPP2_XDP_DROPPED; 3322 goto out; 3323 } 3324 3325 buf_type = MVPP2_TYPE_XDP_NDO; 3326 } else { 3327 /* XDP_TX */ 3328 struct page *page = virt_to_page(xdpf->data); 3329 3330 dma_addr = page_pool_get_dma_addr(page) + 3331 sizeof(*xdpf) + xdpf->headroom; 3332 dma_sync_single_for_device(port->dev->dev.parent, dma_addr, 3333 xdpf->len, DMA_BIDIRECTIONAL); 3334 3335 buf_type = MVPP2_TYPE_XDP_TX; 3336 } 3337 3338 mvpp2_txdesc_dma_addr_set(port, tx_desc, dma_addr); 3339 3340 mvpp2_txdesc_cmd_set(port, tx_desc, tx_cmd); 3341 mvpp2_txq_inc_put(port, txq_pcpu, xdpf, tx_desc, buf_type); 3342 3343 out: 3344 return ret; 3345 } 3346 3347 static int 3348 mvpp2_xdp_xmit_back(struct mvpp2_port *port, struct xdp_buff *xdp) 3349 { 3350 struct mvpp2_pcpu_stats *stats = this_cpu_ptr(port->stats); 3351 struct xdp_frame *xdpf; 3352 u16 txq_id; 3353 int ret; 3354 3355 xdpf = xdp_convert_buff_to_frame(xdp); 3356 if (unlikely(!xdpf)) 3357 return MVPP2_XDP_DROPPED; 3358 3359 /* The first of the TX queues are used for XPS, 3360 * the second half for XDP_TX 3361 */ 3362 txq_id = mvpp2_cpu_to_thread(port->priv, smp_processor_id()) + (port->ntxqs / 2); 3363 3364 ret = mvpp2_xdp_submit_frame(port, txq_id, xdpf, false); 3365 if (ret == MVPP2_XDP_TX) { 3366 u64_stats_update_begin(&stats->syncp); 3367 stats->tx_bytes += xdpf->len; 3368 stats->tx_packets++; 3369 stats->xdp_tx++; 3370 u64_stats_update_end(&stats->syncp); 3371 3372 mvpp2_xdp_finish_tx(port, txq_id, 1, xdpf->len); 3373 } else { 3374 u64_stats_update_begin(&stats->syncp); 3375 stats->xdp_tx_err++; 3376 u64_stats_update_end(&stats->syncp); 3377 } 3378 3379 return ret; 3380 } 3381 3382 static int 3383 mvpp2_xdp_xmit(struct net_device *dev, int num_frame, 3384 struct xdp_frame **frames, u32 flags) 3385 { 3386 struct mvpp2_port *port = netdev_priv(dev); 3387 int i, nxmit_byte = 0, nxmit = num_frame; 3388 struct mvpp2_pcpu_stats *stats; 3389 u16 txq_id; 3390 u32 ret; 3391 3392 if (unlikely(test_bit(0, &port->state))) 3393 return -ENETDOWN; 3394 3395 if (unlikely(flags & ~XDP_XMIT_FLAGS_MASK)) 3396 return -EINVAL; 3397 3398 /* The first of the TX queues are used for XPS, 3399 * the second half for XDP_TX 3400 */ 3401 txq_id = mvpp2_cpu_to_thread(port->priv, smp_processor_id()) + (port->ntxqs / 2); 3402 3403 for (i = 0; i < num_frame; i++) { 3404 ret = mvpp2_xdp_submit_frame(port, txq_id, frames[i], true); 3405 if (ret == MVPP2_XDP_TX) { 3406 nxmit_byte += frames[i]->len; 3407 } else { 3408 xdp_return_frame_rx_napi(frames[i]); 3409 nxmit--; 3410 } 3411 } 3412 3413 if (likely(nxmit > 0)) 3414 mvpp2_xdp_finish_tx(port, txq_id, nxmit, nxmit_byte); 3415 3416 stats = this_cpu_ptr(port->stats); 3417 u64_stats_update_begin(&stats->syncp); 3418 stats->tx_bytes += nxmit_byte; 3419 stats->tx_packets += nxmit; 3420 stats->xdp_xmit += nxmit; 3421 stats->xdp_xmit_err += num_frame - nxmit; 3422 u64_stats_update_end(&stats->syncp); 3423 3424 return nxmit; 3425 } 3426 3427 static int 3428 mvpp2_run_xdp(struct mvpp2_port *port, struct mvpp2_rx_queue *rxq, 3429 struct bpf_prog *prog, struct xdp_buff *xdp, 3430 struct page_pool *pp, struct mvpp2_pcpu_stats *stats) 3431 { 3432 unsigned int len, sync, err; 3433 struct page *page; 3434 u32 ret, act; 3435 3436 len = xdp->data_end - xdp->data_hard_start - MVPP2_SKB_HEADROOM; 3437 act = bpf_prog_run_xdp(prog, xdp); 3438 3439 /* Due xdp_adjust_tail: DMA sync for_device cover max len CPU touch */ 3440 sync = xdp->data_end - xdp->data_hard_start - MVPP2_SKB_HEADROOM; 3441 sync = max(sync, len); 3442 3443 switch (act) { 3444 case XDP_PASS: 3445 stats->xdp_pass++; 3446 ret = MVPP2_XDP_PASS; 3447 break; 3448 case XDP_REDIRECT: 3449 err = xdp_do_redirect(port->dev, xdp, prog); 3450 if (unlikely(err)) { 3451 ret = MVPP2_XDP_DROPPED; 3452 page = virt_to_head_page(xdp->data); 3453 page_pool_put_page(pp, page, sync, true); 3454 } else { 3455 ret = MVPP2_XDP_REDIR; 3456 stats->xdp_redirect++; 3457 } 3458 break; 3459 case XDP_TX: 3460 ret = mvpp2_xdp_xmit_back(port, xdp); 3461 if (ret != MVPP2_XDP_TX) { 3462 page = virt_to_head_page(xdp->data); 3463 page_pool_put_page(pp, page, sync, true); 3464 } 3465 break; 3466 default: 3467 bpf_warn_invalid_xdp_action(act); 3468 fallthrough; 3469 case XDP_ABORTED: 3470 trace_xdp_exception(port->dev, prog, act); 3471 fallthrough; 3472 case XDP_DROP: 3473 page = virt_to_head_page(xdp->data); 3474 page_pool_put_page(pp, page, sync, true); 3475 ret = MVPP2_XDP_DROPPED; 3476 stats->xdp_drop++; 3477 break; 3478 } 3479 3480 return ret; 3481 } 3482 3483 /* Main rx processing */ 3484 static int mvpp2_rx(struct mvpp2_port *port, struct napi_struct *napi, 3485 int rx_todo, struct mvpp2_rx_queue *rxq) 3486 { 3487 struct net_device *dev = port->dev; 3488 struct mvpp2_pcpu_stats ps = {}; 3489 enum dma_data_direction dma_dir; 3490 struct bpf_prog *xdp_prog; 3491 struct xdp_buff xdp; 3492 int rx_received; 3493 int rx_done = 0; 3494 u32 xdp_ret = 0; 3495 3496 rcu_read_lock(); 3497 3498 xdp_prog = READ_ONCE(port->xdp_prog); 3499 3500 /* Get number of received packets and clamp the to-do */ 3501 rx_received = mvpp2_rxq_received(port, rxq->id); 3502 if (rx_todo > rx_received) 3503 rx_todo = rx_received; 3504 3505 while (rx_done < rx_todo) { 3506 struct mvpp2_rx_desc *rx_desc = mvpp2_rxq_next_desc_get(rxq); 3507 struct mvpp2_bm_pool *bm_pool; 3508 struct page_pool *pp = NULL; 3509 struct sk_buff *skb; 3510 unsigned int frag_size; 3511 dma_addr_t dma_addr; 3512 phys_addr_t phys_addr; 3513 u32 rx_status, timestamp; 3514 int pool, rx_bytes, err, ret; 3515 void *data; 3516 3517 rx_done++; 3518 rx_status = mvpp2_rxdesc_status_get(port, rx_desc); 3519 rx_bytes = mvpp2_rxdesc_size_get(port, rx_desc); 3520 rx_bytes -= MVPP2_MH_SIZE; 3521 dma_addr = mvpp2_rxdesc_dma_addr_get(port, rx_desc); 3522 phys_addr = mvpp2_rxdesc_cookie_get(port, rx_desc); 3523 data = (void *)phys_to_virt(phys_addr); 3524 3525 pool = (rx_status & MVPP2_RXD_BM_POOL_ID_MASK) >> 3526 MVPP2_RXD_BM_POOL_ID_OFFS; 3527 bm_pool = &port->priv->bm_pools[pool]; 3528 3529 /* In case of an error, release the requested buffer pointer 3530 * to the Buffer Manager. This request process is controlled 3531 * by the hardware, and the information about the buffer is 3532 * comprised by the RX descriptor. 3533 */ 3534 if (rx_status & MVPP2_RXD_ERR_SUMMARY) 3535 goto err_drop_frame; 3536 3537 if (port->priv->percpu_pools) { 3538 pp = port->priv->page_pool[pool]; 3539 dma_dir = page_pool_get_dma_dir(pp); 3540 } else { 3541 dma_dir = DMA_FROM_DEVICE; 3542 } 3543 3544 dma_sync_single_for_cpu(dev->dev.parent, dma_addr, 3545 rx_bytes + MVPP2_MH_SIZE, 3546 dma_dir); 3547 3548 /* Prefetch header */ 3549 prefetch(data); 3550 3551 if (bm_pool->frag_size > PAGE_SIZE) 3552 frag_size = 0; 3553 else 3554 frag_size = bm_pool->frag_size; 3555 3556 if (xdp_prog) { 3557 xdp.data_hard_start = data; 3558 xdp.data = data + MVPP2_MH_SIZE + MVPP2_SKB_HEADROOM; 3559 xdp.data_end = xdp.data + rx_bytes; 3560 xdp.frame_sz = PAGE_SIZE; 3561 3562 if (bm_pool->pkt_size == MVPP2_BM_SHORT_PKT_SIZE) 3563 xdp.rxq = &rxq->xdp_rxq_short; 3564 else 3565 xdp.rxq = &rxq->xdp_rxq_long; 3566 3567 xdp_set_data_meta_invalid(&xdp); 3568 3569 ret = mvpp2_run_xdp(port, rxq, xdp_prog, &xdp, pp, &ps); 3570 3571 if (ret) { 3572 xdp_ret |= ret; 3573 err = mvpp2_rx_refill(port, bm_pool, pp, pool); 3574 if (err) { 3575 netdev_err(port->dev, "failed to refill BM pools\n"); 3576 goto err_drop_frame; 3577 } 3578 3579 ps.rx_packets++; 3580 ps.rx_bytes += rx_bytes; 3581 continue; 3582 } 3583 } 3584 3585 skb = build_skb(data, frag_size); 3586 if (!skb) { 3587 netdev_warn(port->dev, "skb build failed\n"); 3588 goto err_drop_frame; 3589 } 3590 3591 /* If we have RX hardware timestamping enabled, grab the 3592 * timestamp from the queue and convert. 3593 */ 3594 if (mvpp22_rx_hwtstamping(port)) { 3595 timestamp = le32_to_cpu(rx_desc->pp22.timestamp); 3596 mvpp22_tai_tstamp(port->priv->tai, timestamp, 3597 skb_hwtstamps(skb)); 3598 } 3599 3600 err = mvpp2_rx_refill(port, bm_pool, pp, pool); 3601 if (err) { 3602 netdev_err(port->dev, "failed to refill BM pools\n"); 3603 dev_kfree_skb_any(skb); 3604 goto err_drop_frame; 3605 } 3606 3607 if (pp) 3608 page_pool_release_page(pp, virt_to_page(data)); 3609 else 3610 dma_unmap_single_attrs(dev->dev.parent, dma_addr, 3611 bm_pool->buf_size, DMA_FROM_DEVICE, 3612 DMA_ATTR_SKIP_CPU_SYNC); 3613 3614 ps.rx_packets++; 3615 ps.rx_bytes += rx_bytes; 3616 3617 skb_reserve(skb, MVPP2_MH_SIZE + MVPP2_SKB_HEADROOM); 3618 skb_put(skb, rx_bytes); 3619 skb->protocol = eth_type_trans(skb, dev); 3620 mvpp2_rx_csum(port, rx_status, skb); 3621 3622 napi_gro_receive(napi, skb); 3623 continue; 3624 3625 err_drop_frame: 3626 dev->stats.rx_errors++; 3627 mvpp2_rx_error(port, rx_desc); 3628 /* Return the buffer to the pool */ 3629 mvpp2_bm_pool_put(port, pool, dma_addr, phys_addr); 3630 } 3631 3632 rcu_read_unlock(); 3633 3634 if (xdp_ret & MVPP2_XDP_REDIR) 3635 xdp_do_flush_map(); 3636 3637 if (ps.rx_packets) { 3638 struct mvpp2_pcpu_stats *stats = this_cpu_ptr(port->stats); 3639 3640 u64_stats_update_begin(&stats->syncp); 3641 stats->rx_packets += ps.rx_packets; 3642 stats->rx_bytes += ps.rx_bytes; 3643 /* xdp */ 3644 stats->xdp_redirect += ps.xdp_redirect; 3645 stats->xdp_pass += ps.xdp_pass; 3646 stats->xdp_drop += ps.xdp_drop; 3647 u64_stats_update_end(&stats->syncp); 3648 } 3649 3650 /* Update Rx queue management counters */ 3651 wmb(); 3652 mvpp2_rxq_status_update(port, rxq->id, rx_done, rx_done); 3653 3654 return rx_todo; 3655 } 3656 3657 static inline void 3658 tx_desc_unmap_put(struct mvpp2_port *port, struct mvpp2_tx_queue *txq, 3659 struct mvpp2_tx_desc *desc) 3660 { 3661 unsigned int thread = mvpp2_cpu_to_thread(port->priv, smp_processor_id()); 3662 struct mvpp2_txq_pcpu *txq_pcpu = per_cpu_ptr(txq->pcpu, thread); 3663 3664 dma_addr_t buf_dma_addr = 3665 mvpp2_txdesc_dma_addr_get(port, desc); 3666 size_t buf_sz = 3667 mvpp2_txdesc_size_get(port, desc); 3668 if (!IS_TSO_HEADER(txq_pcpu, buf_dma_addr)) 3669 dma_unmap_single(port->dev->dev.parent, buf_dma_addr, 3670 buf_sz, DMA_TO_DEVICE); 3671 mvpp2_txq_desc_put(txq); 3672 } 3673 3674 static void mvpp2_txdesc_clear_ptp(struct mvpp2_port *port, 3675 struct mvpp2_tx_desc *desc) 3676 { 3677 /* We only need to clear the low bits */ 3678 if (port->priv->hw_version != MVPP21) 3679 desc->pp22.ptp_descriptor &= 3680 cpu_to_le32(~MVPP22_PTP_DESC_MASK_LOW); 3681 } 3682 3683 static bool mvpp2_tx_hw_tstamp(struct mvpp2_port *port, 3684 struct mvpp2_tx_desc *tx_desc, 3685 struct sk_buff *skb) 3686 { 3687 struct mvpp2_hwtstamp_queue *queue; 3688 unsigned int mtype, type, i; 3689 struct ptp_header *hdr; 3690 u64 ptpdesc; 3691 3692 if (port->priv->hw_version == MVPP21 || 3693 port->tx_hwtstamp_type == HWTSTAMP_TX_OFF) 3694 return false; 3695 3696 type = ptp_classify_raw(skb); 3697 if (!type) 3698 return false; 3699 3700 hdr = ptp_parse_header(skb, type); 3701 if (!hdr) 3702 return false; 3703 3704 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 3705 3706 ptpdesc = MVPP22_PTP_MACTIMESTAMPINGEN | 3707 MVPP22_PTP_ACTION_CAPTURE; 3708 queue = &port->tx_hwtstamp_queue[0]; 3709 3710 switch (type & PTP_CLASS_VMASK) { 3711 case PTP_CLASS_V1: 3712 ptpdesc |= MVPP22_PTP_PACKETFORMAT(MVPP22_PTP_PKT_FMT_PTPV1); 3713 break; 3714 3715 case PTP_CLASS_V2: 3716 ptpdesc |= MVPP22_PTP_PACKETFORMAT(MVPP22_PTP_PKT_FMT_PTPV2); 3717 mtype = hdr->tsmt & 15; 3718 /* Direct PTP Sync messages to queue 1 */ 3719 if (mtype == 0) { 3720 ptpdesc |= MVPP22_PTP_TIMESTAMPQUEUESELECT; 3721 queue = &port->tx_hwtstamp_queue[1]; 3722 } 3723 break; 3724 } 3725 3726 /* Take a reference on the skb and insert into our queue */ 3727 i = queue->next; 3728 queue->next = (i + 1) & 31; 3729 if (queue->skb[i]) 3730 dev_kfree_skb_any(queue->skb[i]); 3731 queue->skb[i] = skb_get(skb); 3732 3733 ptpdesc |= MVPP22_PTP_TIMESTAMPENTRYID(i); 3734 3735 /* 3736 * 3:0 - PTPAction 3737 * 6:4 - PTPPacketFormat 3738 * 7 - PTP_CF_WraparoundCheckEn 3739 * 9:8 - IngressTimestampSeconds[1:0] 3740 * 10 - Reserved 3741 * 11 - MACTimestampingEn 3742 * 17:12 - PTP_TimestampQueueEntryID[5:0] 3743 * 18 - PTPTimestampQueueSelect 3744 * 19 - UDPChecksumUpdateEn 3745 * 27:20 - TimestampOffset 3746 * PTP, NTPTransmit, OWAMP/TWAMP - L3 to PTP header 3747 * NTPTs, Y.1731 - L3 to timestamp entry 3748 * 35:28 - UDP Checksum Offset 3749 * 3750 * stored in tx descriptor bits 75:64 (11:0) and 191:168 (35:12) 3751 */ 3752 tx_desc->pp22.ptp_descriptor &= 3753 cpu_to_le32(~MVPP22_PTP_DESC_MASK_LOW); 3754 tx_desc->pp22.ptp_descriptor |= 3755 cpu_to_le32(ptpdesc & MVPP22_PTP_DESC_MASK_LOW); 3756 tx_desc->pp22.buf_dma_addr_ptp &= cpu_to_le64(~0xffffff0000000000ULL); 3757 tx_desc->pp22.buf_dma_addr_ptp |= cpu_to_le64((ptpdesc >> 12) << 40); 3758 3759 return true; 3760 } 3761 3762 /* Handle tx fragmentation processing */ 3763 static int mvpp2_tx_frag_process(struct mvpp2_port *port, struct sk_buff *skb, 3764 struct mvpp2_tx_queue *aggr_txq, 3765 struct mvpp2_tx_queue *txq) 3766 { 3767 unsigned int thread = mvpp2_cpu_to_thread(port->priv, smp_processor_id()); 3768 struct mvpp2_txq_pcpu *txq_pcpu = per_cpu_ptr(txq->pcpu, thread); 3769 struct mvpp2_tx_desc *tx_desc; 3770 int i; 3771 dma_addr_t buf_dma_addr; 3772 3773 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { 3774 skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 3775 void *addr = skb_frag_address(frag); 3776 3777 tx_desc = mvpp2_txq_next_desc_get(aggr_txq); 3778 mvpp2_txdesc_clear_ptp(port, tx_desc); 3779 mvpp2_txdesc_txq_set(port, tx_desc, txq->id); 3780 mvpp2_txdesc_size_set(port, tx_desc, skb_frag_size(frag)); 3781 3782 buf_dma_addr = dma_map_single(port->dev->dev.parent, addr, 3783 skb_frag_size(frag), 3784 DMA_TO_DEVICE); 3785 if (dma_mapping_error(port->dev->dev.parent, buf_dma_addr)) { 3786 mvpp2_txq_desc_put(txq); 3787 goto cleanup; 3788 } 3789 3790 mvpp2_txdesc_dma_addr_set(port, tx_desc, buf_dma_addr); 3791 3792 if (i == (skb_shinfo(skb)->nr_frags - 1)) { 3793 /* Last descriptor */ 3794 mvpp2_txdesc_cmd_set(port, tx_desc, 3795 MVPP2_TXD_L_DESC); 3796 mvpp2_txq_inc_put(port, txq_pcpu, skb, tx_desc, MVPP2_TYPE_SKB); 3797 } else { 3798 /* Descriptor in the middle: Not First, Not Last */ 3799 mvpp2_txdesc_cmd_set(port, tx_desc, 0); 3800 mvpp2_txq_inc_put(port, txq_pcpu, NULL, tx_desc, MVPP2_TYPE_SKB); 3801 } 3802 } 3803 3804 return 0; 3805 cleanup: 3806 /* Release all descriptors that were used to map fragments of 3807 * this packet, as well as the corresponding DMA mappings 3808 */ 3809 for (i = i - 1; i >= 0; i--) { 3810 tx_desc = txq->descs + i; 3811 tx_desc_unmap_put(port, txq, tx_desc); 3812 } 3813 3814 return -ENOMEM; 3815 } 3816 3817 static inline void mvpp2_tso_put_hdr(struct sk_buff *skb, 3818 struct net_device *dev, 3819 struct mvpp2_tx_queue *txq, 3820 struct mvpp2_tx_queue *aggr_txq, 3821 struct mvpp2_txq_pcpu *txq_pcpu, 3822 int hdr_sz) 3823 { 3824 struct mvpp2_port *port = netdev_priv(dev); 3825 struct mvpp2_tx_desc *tx_desc = mvpp2_txq_next_desc_get(aggr_txq); 3826 dma_addr_t addr; 3827 3828 mvpp2_txdesc_clear_ptp(port, tx_desc); 3829 mvpp2_txdesc_txq_set(port, tx_desc, txq->id); 3830 mvpp2_txdesc_size_set(port, tx_desc, hdr_sz); 3831 3832 addr = txq_pcpu->tso_headers_dma + 3833 txq_pcpu->txq_put_index * TSO_HEADER_SIZE; 3834 mvpp2_txdesc_dma_addr_set(port, tx_desc, addr); 3835 3836 mvpp2_txdesc_cmd_set(port, tx_desc, mvpp2_skb_tx_csum(port, skb) | 3837 MVPP2_TXD_F_DESC | 3838 MVPP2_TXD_PADDING_DISABLE); 3839 mvpp2_txq_inc_put(port, txq_pcpu, NULL, tx_desc, MVPP2_TYPE_SKB); 3840 } 3841 3842 static inline int mvpp2_tso_put_data(struct sk_buff *skb, 3843 struct net_device *dev, struct tso_t *tso, 3844 struct mvpp2_tx_queue *txq, 3845 struct mvpp2_tx_queue *aggr_txq, 3846 struct mvpp2_txq_pcpu *txq_pcpu, 3847 int sz, bool left, bool last) 3848 { 3849 struct mvpp2_port *port = netdev_priv(dev); 3850 struct mvpp2_tx_desc *tx_desc = mvpp2_txq_next_desc_get(aggr_txq); 3851 dma_addr_t buf_dma_addr; 3852 3853 mvpp2_txdesc_clear_ptp(port, tx_desc); 3854 mvpp2_txdesc_txq_set(port, tx_desc, txq->id); 3855 mvpp2_txdesc_size_set(port, tx_desc, sz); 3856 3857 buf_dma_addr = dma_map_single(dev->dev.parent, tso->data, sz, 3858 DMA_TO_DEVICE); 3859 if (unlikely(dma_mapping_error(dev->dev.parent, buf_dma_addr))) { 3860 mvpp2_txq_desc_put(txq); 3861 return -ENOMEM; 3862 } 3863 3864 mvpp2_txdesc_dma_addr_set(port, tx_desc, buf_dma_addr); 3865 3866 if (!left) { 3867 mvpp2_txdesc_cmd_set(port, tx_desc, MVPP2_TXD_L_DESC); 3868 if (last) { 3869 mvpp2_txq_inc_put(port, txq_pcpu, skb, tx_desc, MVPP2_TYPE_SKB); 3870 return 0; 3871 } 3872 } else { 3873 mvpp2_txdesc_cmd_set(port, tx_desc, 0); 3874 } 3875 3876 mvpp2_txq_inc_put(port, txq_pcpu, NULL, tx_desc, MVPP2_TYPE_SKB); 3877 return 0; 3878 } 3879 3880 static int mvpp2_tx_tso(struct sk_buff *skb, struct net_device *dev, 3881 struct mvpp2_tx_queue *txq, 3882 struct mvpp2_tx_queue *aggr_txq, 3883 struct mvpp2_txq_pcpu *txq_pcpu) 3884 { 3885 struct mvpp2_port *port = netdev_priv(dev); 3886 int hdr_sz, i, len, descs = 0; 3887 struct tso_t tso; 3888 3889 /* Check number of available descriptors */ 3890 if (mvpp2_aggr_desc_num_check(port, aggr_txq, tso_count_descs(skb)) || 3891 mvpp2_txq_reserved_desc_num_proc(port, txq, txq_pcpu, 3892 tso_count_descs(skb))) 3893 return 0; 3894 3895 hdr_sz = tso_start(skb, &tso); 3896 3897 len = skb->len - hdr_sz; 3898 while (len > 0) { 3899 int left = min_t(int, skb_shinfo(skb)->gso_size, len); 3900 char *hdr = txq_pcpu->tso_headers + 3901 txq_pcpu->txq_put_index * TSO_HEADER_SIZE; 3902 3903 len -= left; 3904 descs++; 3905 3906 tso_build_hdr(skb, hdr, &tso, left, len == 0); 3907 mvpp2_tso_put_hdr(skb, dev, txq, aggr_txq, txq_pcpu, hdr_sz); 3908 3909 while (left > 0) { 3910 int sz = min_t(int, tso.size, left); 3911 left -= sz; 3912 descs++; 3913 3914 if (mvpp2_tso_put_data(skb, dev, &tso, txq, aggr_txq, 3915 txq_pcpu, sz, left, len == 0)) 3916 goto release; 3917 tso_build_data(skb, &tso, sz); 3918 } 3919 } 3920 3921 return descs; 3922 3923 release: 3924 for (i = descs - 1; i >= 0; i--) { 3925 struct mvpp2_tx_desc *tx_desc = txq->descs + i; 3926 tx_desc_unmap_put(port, txq, tx_desc); 3927 } 3928 return 0; 3929 } 3930 3931 /* Main tx processing */ 3932 static netdev_tx_t mvpp2_tx(struct sk_buff *skb, struct net_device *dev) 3933 { 3934 struct mvpp2_port *port = netdev_priv(dev); 3935 struct mvpp2_tx_queue *txq, *aggr_txq; 3936 struct mvpp2_txq_pcpu *txq_pcpu; 3937 struct mvpp2_tx_desc *tx_desc; 3938 dma_addr_t buf_dma_addr; 3939 unsigned long flags = 0; 3940 unsigned int thread; 3941 int frags = 0; 3942 u16 txq_id; 3943 u32 tx_cmd; 3944 3945 thread = mvpp2_cpu_to_thread(port->priv, smp_processor_id()); 3946 3947 txq_id = skb_get_queue_mapping(skb); 3948 txq = port->txqs[txq_id]; 3949 txq_pcpu = per_cpu_ptr(txq->pcpu, thread); 3950 aggr_txq = &port->priv->aggr_txqs[thread]; 3951 3952 if (test_bit(thread, &port->priv->lock_map)) 3953 spin_lock_irqsave(&port->tx_lock[thread], flags); 3954 3955 if (skb_is_gso(skb)) { 3956 frags = mvpp2_tx_tso(skb, dev, txq, aggr_txq, txq_pcpu); 3957 goto out; 3958 } 3959 frags = skb_shinfo(skb)->nr_frags + 1; 3960 3961 /* Check number of available descriptors */ 3962 if (mvpp2_aggr_desc_num_check(port, aggr_txq, frags) || 3963 mvpp2_txq_reserved_desc_num_proc(port, txq, txq_pcpu, frags)) { 3964 frags = 0; 3965 goto out; 3966 } 3967 3968 /* Get a descriptor for the first part of the packet */ 3969 tx_desc = mvpp2_txq_next_desc_get(aggr_txq); 3970 if (!(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) || 3971 !mvpp2_tx_hw_tstamp(port, tx_desc, skb)) 3972 mvpp2_txdesc_clear_ptp(port, tx_desc); 3973 mvpp2_txdesc_txq_set(port, tx_desc, txq->id); 3974 mvpp2_txdesc_size_set(port, tx_desc, skb_headlen(skb)); 3975 3976 buf_dma_addr = dma_map_single(dev->dev.parent, skb->data, 3977 skb_headlen(skb), DMA_TO_DEVICE); 3978 if (unlikely(dma_mapping_error(dev->dev.parent, buf_dma_addr))) { 3979 mvpp2_txq_desc_put(txq); 3980 frags = 0; 3981 goto out; 3982 } 3983 3984 mvpp2_txdesc_dma_addr_set(port, tx_desc, buf_dma_addr); 3985 3986 tx_cmd = mvpp2_skb_tx_csum(port, skb); 3987 3988 if (frags == 1) { 3989 /* First and Last descriptor */ 3990 tx_cmd |= MVPP2_TXD_F_DESC | MVPP2_TXD_L_DESC; 3991 mvpp2_txdesc_cmd_set(port, tx_desc, tx_cmd); 3992 mvpp2_txq_inc_put(port, txq_pcpu, skb, tx_desc, MVPP2_TYPE_SKB); 3993 } else { 3994 /* First but not Last */ 3995 tx_cmd |= MVPP2_TXD_F_DESC | MVPP2_TXD_PADDING_DISABLE; 3996 mvpp2_txdesc_cmd_set(port, tx_desc, tx_cmd); 3997 mvpp2_txq_inc_put(port, txq_pcpu, NULL, tx_desc, MVPP2_TYPE_SKB); 3998 3999 /* Continue with other skb fragments */ 4000 if (mvpp2_tx_frag_process(port, skb, aggr_txq, txq)) { 4001 tx_desc_unmap_put(port, txq, tx_desc); 4002 frags = 0; 4003 } 4004 } 4005 4006 out: 4007 if (frags > 0) { 4008 struct mvpp2_pcpu_stats *stats = per_cpu_ptr(port->stats, thread); 4009 struct netdev_queue *nq = netdev_get_tx_queue(dev, txq_id); 4010 4011 txq_pcpu->reserved_num -= frags; 4012 txq_pcpu->count += frags; 4013 aggr_txq->count += frags; 4014 4015 /* Enable transmit */ 4016 wmb(); 4017 mvpp2_aggr_txq_pend_desc_add(port, frags); 4018 4019 if (txq_pcpu->count >= txq_pcpu->stop_threshold) 4020 netif_tx_stop_queue(nq); 4021 4022 u64_stats_update_begin(&stats->syncp); 4023 stats->tx_packets++; 4024 stats->tx_bytes += skb->len; 4025 u64_stats_update_end(&stats->syncp); 4026 } else { 4027 dev->stats.tx_dropped++; 4028 dev_kfree_skb_any(skb); 4029 } 4030 4031 /* Finalize TX processing */ 4032 if (!port->has_tx_irqs && txq_pcpu->count >= txq->done_pkts_coal) 4033 mvpp2_txq_done(port, txq, txq_pcpu); 4034 4035 /* Set the timer in case not all frags were processed */ 4036 if (!port->has_tx_irqs && txq_pcpu->count <= frags && 4037 txq_pcpu->count > 0) { 4038 struct mvpp2_port_pcpu *port_pcpu = per_cpu_ptr(port->pcpu, thread); 4039 4040 if (!port_pcpu->timer_scheduled) { 4041 port_pcpu->timer_scheduled = true; 4042 hrtimer_start(&port_pcpu->tx_done_timer, 4043 MVPP2_TXDONE_HRTIMER_PERIOD_NS, 4044 HRTIMER_MODE_REL_PINNED_SOFT); 4045 } 4046 } 4047 4048 if (test_bit(thread, &port->priv->lock_map)) 4049 spin_unlock_irqrestore(&port->tx_lock[thread], flags); 4050 4051 return NETDEV_TX_OK; 4052 } 4053 4054 static inline void mvpp2_cause_error(struct net_device *dev, int cause) 4055 { 4056 if (cause & MVPP2_CAUSE_FCS_ERR_MASK) 4057 netdev_err(dev, "FCS error\n"); 4058 if (cause & MVPP2_CAUSE_RX_FIFO_OVERRUN_MASK) 4059 netdev_err(dev, "rx fifo overrun error\n"); 4060 if (cause & MVPP2_CAUSE_TX_FIFO_UNDERRUN_MASK) 4061 netdev_err(dev, "tx fifo underrun error\n"); 4062 } 4063 4064 static int mvpp2_poll(struct napi_struct *napi, int budget) 4065 { 4066 u32 cause_rx_tx, cause_rx, cause_tx, cause_misc; 4067 int rx_done = 0; 4068 struct mvpp2_port *port = netdev_priv(napi->dev); 4069 struct mvpp2_queue_vector *qv; 4070 unsigned int thread = mvpp2_cpu_to_thread(port->priv, smp_processor_id()); 4071 4072 qv = container_of(napi, struct mvpp2_queue_vector, napi); 4073 4074 /* Rx/Tx cause register 4075 * 4076 * Bits 0-15: each bit indicates received packets on the Rx queue 4077 * (bit 0 is for Rx queue 0). 4078 * 4079 * Bits 16-23: each bit indicates transmitted packets on the Tx queue 4080 * (bit 16 is for Tx queue 0). 4081 * 4082 * Each CPU has its own Rx/Tx cause register 4083 */ 4084 cause_rx_tx = mvpp2_thread_read_relaxed(port->priv, qv->sw_thread_id, 4085 MVPP2_ISR_RX_TX_CAUSE_REG(port->id)); 4086 4087 cause_misc = cause_rx_tx & MVPP2_CAUSE_MISC_SUM_MASK; 4088 if (cause_misc) { 4089 mvpp2_cause_error(port->dev, cause_misc); 4090 4091 /* Clear the cause register */ 4092 mvpp2_write(port->priv, MVPP2_ISR_MISC_CAUSE_REG, 0); 4093 mvpp2_thread_write(port->priv, thread, 4094 MVPP2_ISR_RX_TX_CAUSE_REG(port->id), 4095 cause_rx_tx & ~MVPP2_CAUSE_MISC_SUM_MASK); 4096 } 4097 4098 if (port->has_tx_irqs) { 4099 cause_tx = cause_rx_tx & MVPP2_CAUSE_TXQ_OCCUP_DESC_ALL_MASK; 4100 if (cause_tx) { 4101 cause_tx >>= MVPP2_CAUSE_TXQ_OCCUP_DESC_ALL_OFFSET; 4102 mvpp2_tx_done(port, cause_tx, qv->sw_thread_id); 4103 } 4104 } 4105 4106 /* Process RX packets */ 4107 cause_rx = cause_rx_tx & 4108 MVPP2_CAUSE_RXQ_OCCUP_DESC_ALL_MASK(port->priv->hw_version); 4109 cause_rx <<= qv->first_rxq; 4110 cause_rx |= qv->pending_cause_rx; 4111 while (cause_rx && budget > 0) { 4112 int count; 4113 struct mvpp2_rx_queue *rxq; 4114 4115 rxq = mvpp2_get_rx_queue(port, cause_rx); 4116 if (!rxq) 4117 break; 4118 4119 count = mvpp2_rx(port, napi, budget, rxq); 4120 rx_done += count; 4121 budget -= count; 4122 if (budget > 0) { 4123 /* Clear the bit associated to this Rx queue 4124 * so that next iteration will continue from 4125 * the next Rx queue. 4126 */ 4127 cause_rx &= ~(1 << rxq->logic_rxq); 4128 } 4129 } 4130 4131 if (budget > 0) { 4132 cause_rx = 0; 4133 napi_complete_done(napi, rx_done); 4134 4135 mvpp2_qvec_interrupt_enable(qv); 4136 } 4137 qv->pending_cause_rx = cause_rx; 4138 return rx_done; 4139 } 4140 4141 static void mvpp22_mode_reconfigure(struct mvpp2_port *port) 4142 { 4143 u32 ctrl3; 4144 4145 /* Set the GMAC & XLG MAC in reset */ 4146 mvpp2_mac_reset_assert(port); 4147 4148 /* Set the MPCS and XPCS in reset */ 4149 mvpp22_pcs_reset_assert(port); 4150 4151 /* comphy reconfiguration */ 4152 mvpp22_comphy_init(port); 4153 4154 /* gop reconfiguration */ 4155 mvpp22_gop_init(port); 4156 4157 mvpp22_pcs_reset_deassert(port); 4158 4159 if (mvpp2_port_supports_xlg(port)) { 4160 ctrl3 = readl(port->base + MVPP22_XLG_CTRL3_REG); 4161 ctrl3 &= ~MVPP22_XLG_CTRL3_MACMODESELECT_MASK; 4162 4163 if (mvpp2_is_xlg(port->phy_interface)) 4164 ctrl3 |= MVPP22_XLG_CTRL3_MACMODESELECT_10G; 4165 else 4166 ctrl3 |= MVPP22_XLG_CTRL3_MACMODESELECT_GMAC; 4167 4168 writel(ctrl3, port->base + MVPP22_XLG_CTRL3_REG); 4169 } 4170 4171 if (mvpp2_port_supports_xlg(port) && mvpp2_is_xlg(port->phy_interface)) 4172 mvpp2_xlg_max_rx_size_set(port); 4173 else 4174 mvpp2_gmac_max_rx_size_set(port); 4175 } 4176 4177 /* Set hw internals when starting port */ 4178 static void mvpp2_start_dev(struct mvpp2_port *port) 4179 { 4180 int i; 4181 4182 mvpp2_txp_max_tx_size_set(port); 4183 4184 for (i = 0; i < port->nqvecs; i++) 4185 napi_enable(&port->qvecs[i].napi); 4186 4187 /* Enable interrupts on all threads */ 4188 mvpp2_interrupts_enable(port); 4189 4190 if (port->priv->hw_version == MVPP22) 4191 mvpp22_mode_reconfigure(port); 4192 4193 if (port->phylink) { 4194 phylink_start(port->phylink); 4195 } else { 4196 mvpp2_acpi_start(port); 4197 } 4198 4199 netif_tx_start_all_queues(port->dev); 4200 4201 clear_bit(0, &port->state); 4202 } 4203 4204 /* Set hw internals when stopping port */ 4205 static void mvpp2_stop_dev(struct mvpp2_port *port) 4206 { 4207 int i; 4208 4209 set_bit(0, &port->state); 4210 4211 /* Disable interrupts on all threads */ 4212 mvpp2_interrupts_disable(port); 4213 4214 for (i = 0; i < port->nqvecs; i++) 4215 napi_disable(&port->qvecs[i].napi); 4216 4217 if (port->phylink) 4218 phylink_stop(port->phylink); 4219 phy_power_off(port->comphy); 4220 } 4221 4222 static int mvpp2_check_ringparam_valid(struct net_device *dev, 4223 struct ethtool_ringparam *ring) 4224 { 4225 u16 new_rx_pending = ring->rx_pending; 4226 u16 new_tx_pending = ring->tx_pending; 4227 4228 if (ring->rx_pending == 0 || ring->tx_pending == 0) 4229 return -EINVAL; 4230 4231 if (ring->rx_pending > MVPP2_MAX_RXD_MAX) 4232 new_rx_pending = MVPP2_MAX_RXD_MAX; 4233 else if (!IS_ALIGNED(ring->rx_pending, 16)) 4234 new_rx_pending = ALIGN(ring->rx_pending, 16); 4235 4236 if (ring->tx_pending > MVPP2_MAX_TXD_MAX) 4237 new_tx_pending = MVPP2_MAX_TXD_MAX; 4238 else if (!IS_ALIGNED(ring->tx_pending, 32)) 4239 new_tx_pending = ALIGN(ring->tx_pending, 32); 4240 4241 /* The Tx ring size cannot be smaller than the minimum number of 4242 * descriptors needed for TSO. 4243 */ 4244 if (new_tx_pending < MVPP2_MAX_SKB_DESCS) 4245 new_tx_pending = ALIGN(MVPP2_MAX_SKB_DESCS, 32); 4246 4247 if (ring->rx_pending != new_rx_pending) { 4248 netdev_info(dev, "illegal Rx ring size value %d, round to %d\n", 4249 ring->rx_pending, new_rx_pending); 4250 ring->rx_pending = new_rx_pending; 4251 } 4252 4253 if (ring->tx_pending != new_tx_pending) { 4254 netdev_info(dev, "illegal Tx ring size value %d, round to %d\n", 4255 ring->tx_pending, new_tx_pending); 4256 ring->tx_pending = new_tx_pending; 4257 } 4258 4259 return 0; 4260 } 4261 4262 static void mvpp21_get_mac_address(struct mvpp2_port *port, unsigned char *addr) 4263 { 4264 u32 mac_addr_l, mac_addr_m, mac_addr_h; 4265 4266 mac_addr_l = readl(port->base + MVPP2_GMAC_CTRL_1_REG); 4267 mac_addr_m = readl(port->priv->lms_base + MVPP2_SRC_ADDR_MIDDLE); 4268 mac_addr_h = readl(port->priv->lms_base + MVPP2_SRC_ADDR_HIGH); 4269 addr[0] = (mac_addr_h >> 24) & 0xFF; 4270 addr[1] = (mac_addr_h >> 16) & 0xFF; 4271 addr[2] = (mac_addr_h >> 8) & 0xFF; 4272 addr[3] = mac_addr_h & 0xFF; 4273 addr[4] = mac_addr_m & 0xFF; 4274 addr[5] = (mac_addr_l >> MVPP2_GMAC_SA_LOW_OFFS) & 0xFF; 4275 } 4276 4277 static int mvpp2_irqs_init(struct mvpp2_port *port) 4278 { 4279 int err, i; 4280 4281 for (i = 0; i < port->nqvecs; i++) { 4282 struct mvpp2_queue_vector *qv = port->qvecs + i; 4283 4284 if (qv->type == MVPP2_QUEUE_VECTOR_PRIVATE) { 4285 qv->mask = kzalloc(cpumask_size(), GFP_KERNEL); 4286 if (!qv->mask) { 4287 err = -ENOMEM; 4288 goto err; 4289 } 4290 4291 irq_set_status_flags(qv->irq, IRQ_NO_BALANCING); 4292 } 4293 4294 err = request_irq(qv->irq, mvpp2_isr, 0, port->dev->name, qv); 4295 if (err) 4296 goto err; 4297 4298 if (qv->type == MVPP2_QUEUE_VECTOR_PRIVATE) { 4299 unsigned int cpu; 4300 4301 for_each_present_cpu(cpu) { 4302 if (mvpp2_cpu_to_thread(port->priv, cpu) == 4303 qv->sw_thread_id) 4304 cpumask_set_cpu(cpu, qv->mask); 4305 } 4306 4307 irq_set_affinity_hint(qv->irq, qv->mask); 4308 } 4309 } 4310 4311 return 0; 4312 err: 4313 for (i = 0; i < port->nqvecs; i++) { 4314 struct mvpp2_queue_vector *qv = port->qvecs + i; 4315 4316 irq_set_affinity_hint(qv->irq, NULL); 4317 kfree(qv->mask); 4318 qv->mask = NULL; 4319 free_irq(qv->irq, qv); 4320 } 4321 4322 return err; 4323 } 4324 4325 static void mvpp2_irqs_deinit(struct mvpp2_port *port) 4326 { 4327 int i; 4328 4329 for (i = 0; i < port->nqvecs; i++) { 4330 struct mvpp2_queue_vector *qv = port->qvecs + i; 4331 4332 irq_set_affinity_hint(qv->irq, NULL); 4333 kfree(qv->mask); 4334 qv->mask = NULL; 4335 irq_clear_status_flags(qv->irq, IRQ_NO_BALANCING); 4336 free_irq(qv->irq, qv); 4337 } 4338 } 4339 4340 static bool mvpp22_rss_is_supported(void) 4341 { 4342 return queue_mode == MVPP2_QDIST_MULTI_MODE; 4343 } 4344 4345 static int mvpp2_open(struct net_device *dev) 4346 { 4347 struct mvpp2_port *port = netdev_priv(dev); 4348 struct mvpp2 *priv = port->priv; 4349 unsigned char mac_bcast[ETH_ALEN] = { 4350 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }; 4351 bool valid = false; 4352 int err; 4353 4354 err = mvpp2_prs_mac_da_accept(port, mac_bcast, true); 4355 if (err) { 4356 netdev_err(dev, "mvpp2_prs_mac_da_accept BC failed\n"); 4357 return err; 4358 } 4359 err = mvpp2_prs_mac_da_accept(port, dev->dev_addr, true); 4360 if (err) { 4361 netdev_err(dev, "mvpp2_prs_mac_da_accept own addr failed\n"); 4362 return err; 4363 } 4364 err = mvpp2_prs_tag_mode_set(port->priv, port->id, MVPP2_TAG_TYPE_MH); 4365 if (err) { 4366 netdev_err(dev, "mvpp2_prs_tag_mode_set failed\n"); 4367 return err; 4368 } 4369 err = mvpp2_prs_def_flow(port); 4370 if (err) { 4371 netdev_err(dev, "mvpp2_prs_def_flow failed\n"); 4372 return err; 4373 } 4374 4375 /* Allocate the Rx/Tx queues */ 4376 err = mvpp2_setup_rxqs(port); 4377 if (err) { 4378 netdev_err(port->dev, "cannot allocate Rx queues\n"); 4379 return err; 4380 } 4381 4382 err = mvpp2_setup_txqs(port); 4383 if (err) { 4384 netdev_err(port->dev, "cannot allocate Tx queues\n"); 4385 goto err_cleanup_rxqs; 4386 } 4387 4388 err = mvpp2_irqs_init(port); 4389 if (err) { 4390 netdev_err(port->dev, "cannot init IRQs\n"); 4391 goto err_cleanup_txqs; 4392 } 4393 4394 /* Phylink isn't supported yet in ACPI mode */ 4395 if (port->of_node) { 4396 err = phylink_of_phy_connect(port->phylink, port->of_node, 0); 4397 if (err) { 4398 netdev_err(port->dev, "could not attach PHY (%d)\n", 4399 err); 4400 goto err_free_irq; 4401 } 4402 4403 valid = true; 4404 } 4405 4406 if (priv->hw_version == MVPP22 && port->port_irq) { 4407 err = request_irq(port->port_irq, mvpp2_port_isr, 0, 4408 dev->name, port); 4409 if (err) { 4410 netdev_err(port->dev, 4411 "cannot request port link/ptp IRQ %d\n", 4412 port->port_irq); 4413 goto err_free_irq; 4414 } 4415 4416 mvpp22_gop_setup_irq(port); 4417 4418 /* In default link is down */ 4419 netif_carrier_off(port->dev); 4420 4421 valid = true; 4422 } else { 4423 port->port_irq = 0; 4424 } 4425 4426 if (!valid) { 4427 netdev_err(port->dev, 4428 "invalid configuration: no dt or link IRQ"); 4429 goto err_free_irq; 4430 } 4431 4432 /* Unmask interrupts on all CPUs */ 4433 on_each_cpu(mvpp2_interrupts_unmask, port, 1); 4434 mvpp2_shared_interrupt_mask_unmask(port, false); 4435 4436 mvpp2_start_dev(port); 4437 4438 /* Start hardware statistics gathering */ 4439 queue_delayed_work(priv->stats_queue, &port->stats_work, 4440 MVPP2_MIB_COUNTERS_STATS_DELAY); 4441 4442 return 0; 4443 4444 err_free_irq: 4445 mvpp2_irqs_deinit(port); 4446 err_cleanup_txqs: 4447 mvpp2_cleanup_txqs(port); 4448 err_cleanup_rxqs: 4449 mvpp2_cleanup_rxqs(port); 4450 return err; 4451 } 4452 4453 static int mvpp2_stop(struct net_device *dev) 4454 { 4455 struct mvpp2_port *port = netdev_priv(dev); 4456 struct mvpp2_port_pcpu *port_pcpu; 4457 unsigned int thread; 4458 4459 mvpp2_stop_dev(port); 4460 4461 /* Mask interrupts on all threads */ 4462 on_each_cpu(mvpp2_interrupts_mask, port, 1); 4463 mvpp2_shared_interrupt_mask_unmask(port, true); 4464 4465 if (port->phylink) 4466 phylink_disconnect_phy(port->phylink); 4467 if (port->port_irq) 4468 free_irq(port->port_irq, port); 4469 4470 mvpp2_irqs_deinit(port); 4471 if (!port->has_tx_irqs) { 4472 for (thread = 0; thread < port->priv->nthreads; thread++) { 4473 port_pcpu = per_cpu_ptr(port->pcpu, thread); 4474 4475 hrtimer_cancel(&port_pcpu->tx_done_timer); 4476 port_pcpu->timer_scheduled = false; 4477 } 4478 } 4479 mvpp2_cleanup_rxqs(port); 4480 mvpp2_cleanup_txqs(port); 4481 4482 cancel_delayed_work_sync(&port->stats_work); 4483 4484 mvpp2_mac_reset_assert(port); 4485 mvpp22_pcs_reset_assert(port); 4486 4487 return 0; 4488 } 4489 4490 static int mvpp2_prs_mac_da_accept_list(struct mvpp2_port *port, 4491 struct netdev_hw_addr_list *list) 4492 { 4493 struct netdev_hw_addr *ha; 4494 int ret; 4495 4496 netdev_hw_addr_list_for_each(ha, list) { 4497 ret = mvpp2_prs_mac_da_accept(port, ha->addr, true); 4498 if (ret) 4499 return ret; 4500 } 4501 4502 return 0; 4503 } 4504 4505 static void mvpp2_set_rx_promisc(struct mvpp2_port *port, bool enable) 4506 { 4507 if (!enable && (port->dev->features & NETIF_F_HW_VLAN_CTAG_FILTER)) 4508 mvpp2_prs_vid_enable_filtering(port); 4509 else 4510 mvpp2_prs_vid_disable_filtering(port); 4511 4512 mvpp2_prs_mac_promisc_set(port->priv, port->id, 4513 MVPP2_PRS_L2_UNI_CAST, enable); 4514 4515 mvpp2_prs_mac_promisc_set(port->priv, port->id, 4516 MVPP2_PRS_L2_MULTI_CAST, enable); 4517 } 4518 4519 static void mvpp2_set_rx_mode(struct net_device *dev) 4520 { 4521 struct mvpp2_port *port = netdev_priv(dev); 4522 4523 /* Clear the whole UC and MC list */ 4524 mvpp2_prs_mac_del_all(port); 4525 4526 if (dev->flags & IFF_PROMISC) { 4527 mvpp2_set_rx_promisc(port, true); 4528 return; 4529 } 4530 4531 mvpp2_set_rx_promisc(port, false); 4532 4533 if (netdev_uc_count(dev) > MVPP2_PRS_MAC_UC_FILT_MAX || 4534 mvpp2_prs_mac_da_accept_list(port, &dev->uc)) 4535 mvpp2_prs_mac_promisc_set(port->priv, port->id, 4536 MVPP2_PRS_L2_UNI_CAST, true); 4537 4538 if (dev->flags & IFF_ALLMULTI) { 4539 mvpp2_prs_mac_promisc_set(port->priv, port->id, 4540 MVPP2_PRS_L2_MULTI_CAST, true); 4541 return; 4542 } 4543 4544 if (netdev_mc_count(dev) > MVPP2_PRS_MAC_MC_FILT_MAX || 4545 mvpp2_prs_mac_da_accept_list(port, &dev->mc)) 4546 mvpp2_prs_mac_promisc_set(port->priv, port->id, 4547 MVPP2_PRS_L2_MULTI_CAST, true); 4548 } 4549 4550 static int mvpp2_set_mac_address(struct net_device *dev, void *p) 4551 { 4552 const struct sockaddr *addr = p; 4553 int err; 4554 4555 if (!is_valid_ether_addr(addr->sa_data)) 4556 return -EADDRNOTAVAIL; 4557 4558 err = mvpp2_prs_update_mac_da(dev, addr->sa_data); 4559 if (err) { 4560 /* Reconfigure parser accept the original MAC address */ 4561 mvpp2_prs_update_mac_da(dev, dev->dev_addr); 4562 netdev_err(dev, "failed to change MAC address\n"); 4563 } 4564 return err; 4565 } 4566 4567 /* Shut down all the ports, reconfigure the pools as percpu or shared, 4568 * then bring up again all ports. 4569 */ 4570 static int mvpp2_bm_switch_buffers(struct mvpp2 *priv, bool percpu) 4571 { 4572 int numbufs = MVPP2_BM_POOLS_NUM, i; 4573 struct mvpp2_port *port = NULL; 4574 bool status[MVPP2_MAX_PORTS]; 4575 4576 for (i = 0; i < priv->port_count; i++) { 4577 port = priv->port_list[i]; 4578 status[i] = netif_running(port->dev); 4579 if (status[i]) 4580 mvpp2_stop(port->dev); 4581 } 4582 4583 /* nrxqs is the same for all ports */ 4584 if (priv->percpu_pools) 4585 numbufs = port->nrxqs * 2; 4586 4587 for (i = 0; i < numbufs; i++) 4588 mvpp2_bm_pool_destroy(port->dev->dev.parent, priv, &priv->bm_pools[i]); 4589 4590 devm_kfree(port->dev->dev.parent, priv->bm_pools); 4591 priv->percpu_pools = percpu; 4592 mvpp2_bm_init(port->dev->dev.parent, priv); 4593 4594 for (i = 0; i < priv->port_count; i++) { 4595 port = priv->port_list[i]; 4596 mvpp2_swf_bm_pool_init(port); 4597 if (status[i]) 4598 mvpp2_open(port->dev); 4599 } 4600 4601 return 0; 4602 } 4603 4604 static int mvpp2_change_mtu(struct net_device *dev, int mtu) 4605 { 4606 struct mvpp2_port *port = netdev_priv(dev); 4607 bool running = netif_running(dev); 4608 struct mvpp2 *priv = port->priv; 4609 int err; 4610 4611 if (!IS_ALIGNED(MVPP2_RX_PKT_SIZE(mtu), 8)) { 4612 netdev_info(dev, "illegal MTU value %d, round to %d\n", mtu, 4613 ALIGN(MVPP2_RX_PKT_SIZE(mtu), 8)); 4614 mtu = ALIGN(MVPP2_RX_PKT_SIZE(mtu), 8); 4615 } 4616 4617 if (MVPP2_RX_PKT_SIZE(mtu) > MVPP2_BM_LONG_PKT_SIZE) { 4618 if (port->xdp_prog) { 4619 netdev_err(dev, "Jumbo frames are not supported with XDP\n"); 4620 return -EINVAL; 4621 } 4622 if (priv->percpu_pools) { 4623 netdev_warn(dev, "mtu %d too high, switching to shared buffers", mtu); 4624 mvpp2_bm_switch_buffers(priv, false); 4625 } 4626 } else { 4627 bool jumbo = false; 4628 int i; 4629 4630 for (i = 0; i < priv->port_count; i++) 4631 if (priv->port_list[i] != port && 4632 MVPP2_RX_PKT_SIZE(priv->port_list[i]->dev->mtu) > 4633 MVPP2_BM_LONG_PKT_SIZE) { 4634 jumbo = true; 4635 break; 4636 } 4637 4638 /* No port is using jumbo frames */ 4639 if (!jumbo) { 4640 dev_info(port->dev->dev.parent, 4641 "all ports have a low MTU, switching to per-cpu buffers"); 4642 mvpp2_bm_switch_buffers(priv, true); 4643 } 4644 } 4645 4646 if (running) 4647 mvpp2_stop_dev(port); 4648 4649 err = mvpp2_bm_update_mtu(dev, mtu); 4650 if (err) { 4651 netdev_err(dev, "failed to change MTU\n"); 4652 /* Reconfigure BM to the original MTU */ 4653 mvpp2_bm_update_mtu(dev, dev->mtu); 4654 } else { 4655 port->pkt_size = MVPP2_RX_PKT_SIZE(mtu); 4656 } 4657 4658 if (running) { 4659 mvpp2_start_dev(port); 4660 mvpp2_egress_enable(port); 4661 mvpp2_ingress_enable(port); 4662 } 4663 4664 return err; 4665 } 4666 4667 static int mvpp2_check_pagepool_dma(struct mvpp2_port *port) 4668 { 4669 enum dma_data_direction dma_dir = DMA_FROM_DEVICE; 4670 struct mvpp2 *priv = port->priv; 4671 int err = -1, i; 4672 4673 if (!priv->percpu_pools) 4674 return err; 4675 4676 if (!priv->page_pool[0]) 4677 return -ENOMEM; 4678 4679 for (i = 0; i < priv->port_count; i++) { 4680 port = priv->port_list[i]; 4681 if (port->xdp_prog) { 4682 dma_dir = DMA_BIDIRECTIONAL; 4683 break; 4684 } 4685 } 4686 4687 /* All pools are equal in terms of DMA direction */ 4688 if (priv->page_pool[0]->p.dma_dir != dma_dir) 4689 err = mvpp2_bm_switch_buffers(priv, true); 4690 4691 return err; 4692 } 4693 4694 static void 4695 mvpp2_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats) 4696 { 4697 struct mvpp2_port *port = netdev_priv(dev); 4698 unsigned int start; 4699 unsigned int cpu; 4700 4701 for_each_possible_cpu(cpu) { 4702 struct mvpp2_pcpu_stats *cpu_stats; 4703 u64 rx_packets; 4704 u64 rx_bytes; 4705 u64 tx_packets; 4706 u64 tx_bytes; 4707 4708 cpu_stats = per_cpu_ptr(port->stats, cpu); 4709 do { 4710 start = u64_stats_fetch_begin_irq(&cpu_stats->syncp); 4711 rx_packets = cpu_stats->rx_packets; 4712 rx_bytes = cpu_stats->rx_bytes; 4713 tx_packets = cpu_stats->tx_packets; 4714 tx_bytes = cpu_stats->tx_bytes; 4715 } while (u64_stats_fetch_retry_irq(&cpu_stats->syncp, start)); 4716 4717 stats->rx_packets += rx_packets; 4718 stats->rx_bytes += rx_bytes; 4719 stats->tx_packets += tx_packets; 4720 stats->tx_bytes += tx_bytes; 4721 } 4722 4723 stats->rx_errors = dev->stats.rx_errors; 4724 stats->rx_dropped = dev->stats.rx_dropped; 4725 stats->tx_dropped = dev->stats.tx_dropped; 4726 } 4727 4728 static int mvpp2_set_ts_config(struct mvpp2_port *port, struct ifreq *ifr) 4729 { 4730 struct hwtstamp_config config; 4731 void __iomem *ptp; 4732 u32 gcr, int_mask; 4733 4734 if (copy_from_user(&config, ifr->ifr_data, sizeof(config))) 4735 return -EFAULT; 4736 4737 if (config.flags) 4738 return -EINVAL; 4739 4740 if (config.tx_type != HWTSTAMP_TX_OFF && 4741 config.tx_type != HWTSTAMP_TX_ON) 4742 return -ERANGE; 4743 4744 ptp = port->priv->iface_base + MVPP22_PTP_BASE(port->gop_id); 4745 4746 int_mask = gcr = 0; 4747 if (config.tx_type != HWTSTAMP_TX_OFF) { 4748 gcr |= MVPP22_PTP_GCR_TSU_ENABLE | MVPP22_PTP_GCR_TX_RESET; 4749 int_mask |= MVPP22_PTP_INT_MASK_QUEUE1 | 4750 MVPP22_PTP_INT_MASK_QUEUE0; 4751 } 4752 4753 /* It seems we must also release the TX reset when enabling the TSU */ 4754 if (config.rx_filter != HWTSTAMP_FILTER_NONE) 4755 gcr |= MVPP22_PTP_GCR_TSU_ENABLE | MVPP22_PTP_GCR_RX_RESET | 4756 MVPP22_PTP_GCR_TX_RESET; 4757 4758 if (gcr & MVPP22_PTP_GCR_TSU_ENABLE) 4759 mvpp22_tai_start(port->priv->tai); 4760 4761 if (config.rx_filter != HWTSTAMP_FILTER_NONE) { 4762 config.rx_filter = HWTSTAMP_FILTER_ALL; 4763 mvpp2_modify(ptp + MVPP22_PTP_GCR, 4764 MVPP22_PTP_GCR_RX_RESET | 4765 MVPP22_PTP_GCR_TX_RESET | 4766 MVPP22_PTP_GCR_TSU_ENABLE, gcr); 4767 port->rx_hwtstamp = true; 4768 } else { 4769 port->rx_hwtstamp = false; 4770 mvpp2_modify(ptp + MVPP22_PTP_GCR, 4771 MVPP22_PTP_GCR_RX_RESET | 4772 MVPP22_PTP_GCR_TX_RESET | 4773 MVPP22_PTP_GCR_TSU_ENABLE, gcr); 4774 } 4775 4776 mvpp2_modify(ptp + MVPP22_PTP_INT_MASK, 4777 MVPP22_PTP_INT_MASK_QUEUE1 | 4778 MVPP22_PTP_INT_MASK_QUEUE0, int_mask); 4779 4780 if (!(gcr & MVPP22_PTP_GCR_TSU_ENABLE)) 4781 mvpp22_tai_stop(port->priv->tai); 4782 4783 port->tx_hwtstamp_type = config.tx_type; 4784 4785 if (copy_to_user(ifr->ifr_data, &config, sizeof(config))) 4786 return -EFAULT; 4787 4788 return 0; 4789 } 4790 4791 static int mvpp2_get_ts_config(struct mvpp2_port *port, struct ifreq *ifr) 4792 { 4793 struct hwtstamp_config config; 4794 4795 memset(&config, 0, sizeof(config)); 4796 4797 config.tx_type = port->tx_hwtstamp_type; 4798 config.rx_filter = port->rx_hwtstamp ? 4799 HWTSTAMP_FILTER_ALL : HWTSTAMP_FILTER_NONE; 4800 4801 if (copy_to_user(ifr->ifr_data, &config, sizeof(config))) 4802 return -EFAULT; 4803 4804 return 0; 4805 } 4806 4807 static int mvpp2_ethtool_get_ts_info(struct net_device *dev, 4808 struct ethtool_ts_info *info) 4809 { 4810 struct mvpp2_port *port = netdev_priv(dev); 4811 4812 if (!port->hwtstamp) 4813 return -EOPNOTSUPP; 4814 4815 info->phc_index = mvpp22_tai_ptp_clock_index(port->priv->tai); 4816 info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE | 4817 SOF_TIMESTAMPING_RX_SOFTWARE | 4818 SOF_TIMESTAMPING_SOFTWARE | 4819 SOF_TIMESTAMPING_TX_HARDWARE | 4820 SOF_TIMESTAMPING_RX_HARDWARE | 4821 SOF_TIMESTAMPING_RAW_HARDWARE; 4822 info->tx_types = BIT(HWTSTAMP_TX_OFF) | 4823 BIT(HWTSTAMP_TX_ON); 4824 info->rx_filters = BIT(HWTSTAMP_FILTER_NONE) | 4825 BIT(HWTSTAMP_FILTER_ALL); 4826 4827 return 0; 4828 } 4829 4830 static int mvpp2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) 4831 { 4832 struct mvpp2_port *port = netdev_priv(dev); 4833 4834 switch (cmd) { 4835 case SIOCSHWTSTAMP: 4836 if (port->hwtstamp) 4837 return mvpp2_set_ts_config(port, ifr); 4838 break; 4839 4840 case SIOCGHWTSTAMP: 4841 if (port->hwtstamp) 4842 return mvpp2_get_ts_config(port, ifr); 4843 break; 4844 } 4845 4846 if (!port->phylink) 4847 return -ENOTSUPP; 4848 4849 return phylink_mii_ioctl(port->phylink, ifr, cmd); 4850 } 4851 4852 static int mvpp2_vlan_rx_add_vid(struct net_device *dev, __be16 proto, u16 vid) 4853 { 4854 struct mvpp2_port *port = netdev_priv(dev); 4855 int ret; 4856 4857 ret = mvpp2_prs_vid_entry_add(port, vid); 4858 if (ret) 4859 netdev_err(dev, "rx-vlan-filter offloading cannot accept more than %d VIDs per port\n", 4860 MVPP2_PRS_VLAN_FILT_MAX - 1); 4861 return ret; 4862 } 4863 4864 static int mvpp2_vlan_rx_kill_vid(struct net_device *dev, __be16 proto, u16 vid) 4865 { 4866 struct mvpp2_port *port = netdev_priv(dev); 4867 4868 mvpp2_prs_vid_entry_remove(port, vid); 4869 return 0; 4870 } 4871 4872 static int mvpp2_set_features(struct net_device *dev, 4873 netdev_features_t features) 4874 { 4875 netdev_features_t changed = dev->features ^ features; 4876 struct mvpp2_port *port = netdev_priv(dev); 4877 4878 if (changed & NETIF_F_HW_VLAN_CTAG_FILTER) { 4879 if (features & NETIF_F_HW_VLAN_CTAG_FILTER) { 4880 mvpp2_prs_vid_enable_filtering(port); 4881 } else { 4882 /* Invalidate all registered VID filters for this 4883 * port 4884 */ 4885 mvpp2_prs_vid_remove_all(port); 4886 4887 mvpp2_prs_vid_disable_filtering(port); 4888 } 4889 } 4890 4891 if (changed & NETIF_F_RXHASH) { 4892 if (features & NETIF_F_RXHASH) 4893 mvpp22_port_rss_enable(port); 4894 else 4895 mvpp22_port_rss_disable(port); 4896 } 4897 4898 return 0; 4899 } 4900 4901 static int mvpp2_xdp_setup(struct mvpp2_port *port, struct netdev_bpf *bpf) 4902 { 4903 struct bpf_prog *prog = bpf->prog, *old_prog; 4904 bool running = netif_running(port->dev); 4905 bool reset = !prog != !port->xdp_prog; 4906 4907 if (port->dev->mtu > ETH_DATA_LEN) { 4908 NL_SET_ERR_MSG_MOD(bpf->extack, "XDP is not supported with jumbo frames enabled"); 4909 return -EOPNOTSUPP; 4910 } 4911 4912 if (!port->priv->percpu_pools) { 4913 NL_SET_ERR_MSG_MOD(bpf->extack, "Per CPU Pools required for XDP"); 4914 return -EOPNOTSUPP; 4915 } 4916 4917 if (port->ntxqs < num_possible_cpus() * 2) { 4918 NL_SET_ERR_MSG_MOD(bpf->extack, "XDP_TX needs two TX queues per CPU"); 4919 return -EOPNOTSUPP; 4920 } 4921 4922 /* device is up and bpf is added/removed, must setup the RX queues */ 4923 if (running && reset) 4924 mvpp2_stop(port->dev); 4925 4926 old_prog = xchg(&port->xdp_prog, prog); 4927 if (old_prog) 4928 bpf_prog_put(old_prog); 4929 4930 /* bpf is just replaced, RXQ and MTU are already setup */ 4931 if (!reset) 4932 return 0; 4933 4934 /* device was up, restore the link */ 4935 if (running) 4936 mvpp2_open(port->dev); 4937 4938 /* Check Page Pool DMA Direction */ 4939 mvpp2_check_pagepool_dma(port); 4940 4941 return 0; 4942 } 4943 4944 static int mvpp2_xdp(struct net_device *dev, struct netdev_bpf *xdp) 4945 { 4946 struct mvpp2_port *port = netdev_priv(dev); 4947 4948 switch (xdp->command) { 4949 case XDP_SETUP_PROG: 4950 return mvpp2_xdp_setup(port, xdp); 4951 default: 4952 return -EINVAL; 4953 } 4954 } 4955 4956 /* Ethtool methods */ 4957 4958 static int mvpp2_ethtool_nway_reset(struct net_device *dev) 4959 { 4960 struct mvpp2_port *port = netdev_priv(dev); 4961 4962 if (!port->phylink) 4963 return -ENOTSUPP; 4964 4965 return phylink_ethtool_nway_reset(port->phylink); 4966 } 4967 4968 /* Set interrupt coalescing for ethtools */ 4969 static int mvpp2_ethtool_set_coalesce(struct net_device *dev, 4970 struct ethtool_coalesce *c) 4971 { 4972 struct mvpp2_port *port = netdev_priv(dev); 4973 int queue; 4974 4975 for (queue = 0; queue < port->nrxqs; queue++) { 4976 struct mvpp2_rx_queue *rxq = port->rxqs[queue]; 4977 4978 rxq->time_coal = c->rx_coalesce_usecs; 4979 rxq->pkts_coal = c->rx_max_coalesced_frames; 4980 mvpp2_rx_pkts_coal_set(port, rxq); 4981 mvpp2_rx_time_coal_set(port, rxq); 4982 } 4983 4984 if (port->has_tx_irqs) { 4985 port->tx_time_coal = c->tx_coalesce_usecs; 4986 mvpp2_tx_time_coal_set(port); 4987 } 4988 4989 for (queue = 0; queue < port->ntxqs; queue++) { 4990 struct mvpp2_tx_queue *txq = port->txqs[queue]; 4991 4992 txq->done_pkts_coal = c->tx_max_coalesced_frames; 4993 4994 if (port->has_tx_irqs) 4995 mvpp2_tx_pkts_coal_set(port, txq); 4996 } 4997 4998 return 0; 4999 } 5000 5001 /* get coalescing for ethtools */ 5002 static int mvpp2_ethtool_get_coalesce(struct net_device *dev, 5003 struct ethtool_coalesce *c) 5004 { 5005 struct mvpp2_port *port = netdev_priv(dev); 5006 5007 c->rx_coalesce_usecs = port->rxqs[0]->time_coal; 5008 c->rx_max_coalesced_frames = port->rxqs[0]->pkts_coal; 5009 c->tx_max_coalesced_frames = port->txqs[0]->done_pkts_coal; 5010 c->tx_coalesce_usecs = port->tx_time_coal; 5011 return 0; 5012 } 5013 5014 static void mvpp2_ethtool_get_drvinfo(struct net_device *dev, 5015 struct ethtool_drvinfo *drvinfo) 5016 { 5017 strlcpy(drvinfo->driver, MVPP2_DRIVER_NAME, 5018 sizeof(drvinfo->driver)); 5019 strlcpy(drvinfo->version, MVPP2_DRIVER_VERSION, 5020 sizeof(drvinfo->version)); 5021 strlcpy(drvinfo->bus_info, dev_name(&dev->dev), 5022 sizeof(drvinfo->bus_info)); 5023 } 5024 5025 static void mvpp2_ethtool_get_ringparam(struct net_device *dev, 5026 struct ethtool_ringparam *ring) 5027 { 5028 struct mvpp2_port *port = netdev_priv(dev); 5029 5030 ring->rx_max_pending = MVPP2_MAX_RXD_MAX; 5031 ring->tx_max_pending = MVPP2_MAX_TXD_MAX; 5032 ring->rx_pending = port->rx_ring_size; 5033 ring->tx_pending = port->tx_ring_size; 5034 } 5035 5036 static int mvpp2_ethtool_set_ringparam(struct net_device *dev, 5037 struct ethtool_ringparam *ring) 5038 { 5039 struct mvpp2_port *port = netdev_priv(dev); 5040 u16 prev_rx_ring_size = port->rx_ring_size; 5041 u16 prev_tx_ring_size = port->tx_ring_size; 5042 int err; 5043 5044 err = mvpp2_check_ringparam_valid(dev, ring); 5045 if (err) 5046 return err; 5047 5048 if (!netif_running(dev)) { 5049 port->rx_ring_size = ring->rx_pending; 5050 port->tx_ring_size = ring->tx_pending; 5051 return 0; 5052 } 5053 5054 /* The interface is running, so we have to force a 5055 * reallocation of the queues 5056 */ 5057 mvpp2_stop_dev(port); 5058 mvpp2_cleanup_rxqs(port); 5059 mvpp2_cleanup_txqs(port); 5060 5061 port->rx_ring_size = ring->rx_pending; 5062 port->tx_ring_size = ring->tx_pending; 5063 5064 err = mvpp2_setup_rxqs(port); 5065 if (err) { 5066 /* Reallocate Rx queues with the original ring size */ 5067 port->rx_ring_size = prev_rx_ring_size; 5068 ring->rx_pending = prev_rx_ring_size; 5069 err = mvpp2_setup_rxqs(port); 5070 if (err) 5071 goto err_out; 5072 } 5073 err = mvpp2_setup_txqs(port); 5074 if (err) { 5075 /* Reallocate Tx queues with the original ring size */ 5076 port->tx_ring_size = prev_tx_ring_size; 5077 ring->tx_pending = prev_tx_ring_size; 5078 err = mvpp2_setup_txqs(port); 5079 if (err) 5080 goto err_clean_rxqs; 5081 } 5082 5083 mvpp2_start_dev(port); 5084 mvpp2_egress_enable(port); 5085 mvpp2_ingress_enable(port); 5086 5087 return 0; 5088 5089 err_clean_rxqs: 5090 mvpp2_cleanup_rxqs(port); 5091 err_out: 5092 netdev_err(dev, "failed to change ring parameters"); 5093 return err; 5094 } 5095 5096 static void mvpp2_ethtool_get_pause_param(struct net_device *dev, 5097 struct ethtool_pauseparam *pause) 5098 { 5099 struct mvpp2_port *port = netdev_priv(dev); 5100 5101 if (!port->phylink) 5102 return; 5103 5104 phylink_ethtool_get_pauseparam(port->phylink, pause); 5105 } 5106 5107 static int mvpp2_ethtool_set_pause_param(struct net_device *dev, 5108 struct ethtool_pauseparam *pause) 5109 { 5110 struct mvpp2_port *port = netdev_priv(dev); 5111 5112 if (!port->phylink) 5113 return -ENOTSUPP; 5114 5115 return phylink_ethtool_set_pauseparam(port->phylink, pause); 5116 } 5117 5118 static int mvpp2_ethtool_get_link_ksettings(struct net_device *dev, 5119 struct ethtool_link_ksettings *cmd) 5120 { 5121 struct mvpp2_port *port = netdev_priv(dev); 5122 5123 if (!port->phylink) 5124 return -ENOTSUPP; 5125 5126 return phylink_ethtool_ksettings_get(port->phylink, cmd); 5127 } 5128 5129 static int mvpp2_ethtool_set_link_ksettings(struct net_device *dev, 5130 const struct ethtool_link_ksettings *cmd) 5131 { 5132 struct mvpp2_port *port = netdev_priv(dev); 5133 5134 if (!port->phylink) 5135 return -ENOTSUPP; 5136 5137 return phylink_ethtool_ksettings_set(port->phylink, cmd); 5138 } 5139 5140 static int mvpp2_ethtool_get_rxnfc(struct net_device *dev, 5141 struct ethtool_rxnfc *info, u32 *rules) 5142 { 5143 struct mvpp2_port *port = netdev_priv(dev); 5144 int ret = 0, i, loc = 0; 5145 5146 if (!mvpp22_rss_is_supported()) 5147 return -EOPNOTSUPP; 5148 5149 switch (info->cmd) { 5150 case ETHTOOL_GRXFH: 5151 ret = mvpp2_ethtool_rxfh_get(port, info); 5152 break; 5153 case ETHTOOL_GRXRINGS: 5154 info->data = port->nrxqs; 5155 break; 5156 case ETHTOOL_GRXCLSRLCNT: 5157 info->rule_cnt = port->n_rfs_rules; 5158 break; 5159 case ETHTOOL_GRXCLSRULE: 5160 ret = mvpp2_ethtool_cls_rule_get(port, info); 5161 break; 5162 case ETHTOOL_GRXCLSRLALL: 5163 for (i = 0; i < MVPP2_N_RFS_ENTRIES_PER_FLOW; i++) { 5164 if (port->rfs_rules[i]) 5165 rules[loc++] = i; 5166 } 5167 break; 5168 default: 5169 return -ENOTSUPP; 5170 } 5171 5172 return ret; 5173 } 5174 5175 static int mvpp2_ethtool_set_rxnfc(struct net_device *dev, 5176 struct ethtool_rxnfc *info) 5177 { 5178 struct mvpp2_port *port = netdev_priv(dev); 5179 int ret = 0; 5180 5181 if (!mvpp22_rss_is_supported()) 5182 return -EOPNOTSUPP; 5183 5184 switch (info->cmd) { 5185 case ETHTOOL_SRXFH: 5186 ret = mvpp2_ethtool_rxfh_set(port, info); 5187 break; 5188 case ETHTOOL_SRXCLSRLINS: 5189 ret = mvpp2_ethtool_cls_rule_ins(port, info); 5190 break; 5191 case ETHTOOL_SRXCLSRLDEL: 5192 ret = mvpp2_ethtool_cls_rule_del(port, info); 5193 break; 5194 default: 5195 return -EOPNOTSUPP; 5196 } 5197 return ret; 5198 } 5199 5200 static u32 mvpp2_ethtool_get_rxfh_indir_size(struct net_device *dev) 5201 { 5202 return mvpp22_rss_is_supported() ? MVPP22_RSS_TABLE_ENTRIES : 0; 5203 } 5204 5205 static int mvpp2_ethtool_get_rxfh(struct net_device *dev, u32 *indir, u8 *key, 5206 u8 *hfunc) 5207 { 5208 struct mvpp2_port *port = netdev_priv(dev); 5209 int ret = 0; 5210 5211 if (!mvpp22_rss_is_supported()) 5212 return -EOPNOTSUPP; 5213 5214 if (indir) 5215 ret = mvpp22_port_rss_ctx_indir_get(port, 0, indir); 5216 5217 if (hfunc) 5218 *hfunc = ETH_RSS_HASH_CRC32; 5219 5220 return ret; 5221 } 5222 5223 static int mvpp2_ethtool_set_rxfh(struct net_device *dev, const u32 *indir, 5224 const u8 *key, const u8 hfunc) 5225 { 5226 struct mvpp2_port *port = netdev_priv(dev); 5227 int ret = 0; 5228 5229 if (!mvpp22_rss_is_supported()) 5230 return -EOPNOTSUPP; 5231 5232 if (hfunc != ETH_RSS_HASH_NO_CHANGE && hfunc != ETH_RSS_HASH_CRC32) 5233 return -EOPNOTSUPP; 5234 5235 if (key) 5236 return -EOPNOTSUPP; 5237 5238 if (indir) 5239 ret = mvpp22_port_rss_ctx_indir_set(port, 0, indir); 5240 5241 return ret; 5242 } 5243 5244 static int mvpp2_ethtool_get_rxfh_context(struct net_device *dev, u32 *indir, 5245 u8 *key, u8 *hfunc, u32 rss_context) 5246 { 5247 struct mvpp2_port *port = netdev_priv(dev); 5248 int ret = 0; 5249 5250 if (!mvpp22_rss_is_supported()) 5251 return -EOPNOTSUPP; 5252 if (rss_context >= MVPP22_N_RSS_TABLES) 5253 return -EINVAL; 5254 5255 if (hfunc) 5256 *hfunc = ETH_RSS_HASH_CRC32; 5257 5258 if (indir) 5259 ret = mvpp22_port_rss_ctx_indir_get(port, rss_context, indir); 5260 5261 return ret; 5262 } 5263 5264 static int mvpp2_ethtool_set_rxfh_context(struct net_device *dev, 5265 const u32 *indir, const u8 *key, 5266 const u8 hfunc, u32 *rss_context, 5267 bool delete) 5268 { 5269 struct mvpp2_port *port = netdev_priv(dev); 5270 int ret; 5271 5272 if (!mvpp22_rss_is_supported()) 5273 return -EOPNOTSUPP; 5274 5275 if (hfunc != ETH_RSS_HASH_NO_CHANGE && hfunc != ETH_RSS_HASH_CRC32) 5276 return -EOPNOTSUPP; 5277 5278 if (key) 5279 return -EOPNOTSUPP; 5280 5281 if (delete) 5282 return mvpp22_port_rss_ctx_delete(port, *rss_context); 5283 5284 if (*rss_context == ETH_RXFH_CONTEXT_ALLOC) { 5285 ret = mvpp22_port_rss_ctx_create(port, rss_context); 5286 if (ret) 5287 return ret; 5288 } 5289 5290 return mvpp22_port_rss_ctx_indir_set(port, *rss_context, indir); 5291 } 5292 /* Device ops */ 5293 5294 static const struct net_device_ops mvpp2_netdev_ops = { 5295 .ndo_open = mvpp2_open, 5296 .ndo_stop = mvpp2_stop, 5297 .ndo_start_xmit = mvpp2_tx, 5298 .ndo_set_rx_mode = mvpp2_set_rx_mode, 5299 .ndo_set_mac_address = mvpp2_set_mac_address, 5300 .ndo_change_mtu = mvpp2_change_mtu, 5301 .ndo_get_stats64 = mvpp2_get_stats64, 5302 .ndo_do_ioctl = mvpp2_ioctl, 5303 .ndo_vlan_rx_add_vid = mvpp2_vlan_rx_add_vid, 5304 .ndo_vlan_rx_kill_vid = mvpp2_vlan_rx_kill_vid, 5305 .ndo_set_features = mvpp2_set_features, 5306 .ndo_bpf = mvpp2_xdp, 5307 .ndo_xdp_xmit = mvpp2_xdp_xmit, 5308 }; 5309 5310 static const struct ethtool_ops mvpp2_eth_tool_ops = { 5311 .supported_coalesce_params = ETHTOOL_COALESCE_USECS | 5312 ETHTOOL_COALESCE_MAX_FRAMES, 5313 .nway_reset = mvpp2_ethtool_nway_reset, 5314 .get_link = ethtool_op_get_link, 5315 .get_ts_info = mvpp2_ethtool_get_ts_info, 5316 .set_coalesce = mvpp2_ethtool_set_coalesce, 5317 .get_coalesce = mvpp2_ethtool_get_coalesce, 5318 .get_drvinfo = mvpp2_ethtool_get_drvinfo, 5319 .get_ringparam = mvpp2_ethtool_get_ringparam, 5320 .set_ringparam = mvpp2_ethtool_set_ringparam, 5321 .get_strings = mvpp2_ethtool_get_strings, 5322 .get_ethtool_stats = mvpp2_ethtool_get_stats, 5323 .get_sset_count = mvpp2_ethtool_get_sset_count, 5324 .get_pauseparam = mvpp2_ethtool_get_pause_param, 5325 .set_pauseparam = mvpp2_ethtool_set_pause_param, 5326 .get_link_ksettings = mvpp2_ethtool_get_link_ksettings, 5327 .set_link_ksettings = mvpp2_ethtool_set_link_ksettings, 5328 .get_rxnfc = mvpp2_ethtool_get_rxnfc, 5329 .set_rxnfc = mvpp2_ethtool_set_rxnfc, 5330 .get_rxfh_indir_size = mvpp2_ethtool_get_rxfh_indir_size, 5331 .get_rxfh = mvpp2_ethtool_get_rxfh, 5332 .set_rxfh = mvpp2_ethtool_set_rxfh, 5333 .get_rxfh_context = mvpp2_ethtool_get_rxfh_context, 5334 .set_rxfh_context = mvpp2_ethtool_set_rxfh_context, 5335 }; 5336 5337 /* Used for PPv2.1, or PPv2.2 with the old Device Tree binding that 5338 * had a single IRQ defined per-port. 5339 */ 5340 static int mvpp2_simple_queue_vectors_init(struct mvpp2_port *port, 5341 struct device_node *port_node) 5342 { 5343 struct mvpp2_queue_vector *v = &port->qvecs[0]; 5344 5345 v->first_rxq = 0; 5346 v->nrxqs = port->nrxqs; 5347 v->type = MVPP2_QUEUE_VECTOR_SHARED; 5348 v->sw_thread_id = 0; 5349 v->sw_thread_mask = *cpumask_bits(cpu_online_mask); 5350 v->port = port; 5351 v->irq = irq_of_parse_and_map(port_node, 0); 5352 if (v->irq <= 0) 5353 return -EINVAL; 5354 netif_napi_add(port->dev, &v->napi, mvpp2_poll, 5355 NAPI_POLL_WEIGHT); 5356 5357 port->nqvecs = 1; 5358 5359 return 0; 5360 } 5361 5362 static int mvpp2_multi_queue_vectors_init(struct mvpp2_port *port, 5363 struct device_node *port_node) 5364 { 5365 struct mvpp2 *priv = port->priv; 5366 struct mvpp2_queue_vector *v; 5367 int i, ret; 5368 5369 switch (queue_mode) { 5370 case MVPP2_QDIST_SINGLE_MODE: 5371 port->nqvecs = priv->nthreads + 1; 5372 break; 5373 case MVPP2_QDIST_MULTI_MODE: 5374 port->nqvecs = priv->nthreads; 5375 break; 5376 } 5377 5378 for (i = 0; i < port->nqvecs; i++) { 5379 char irqname[16]; 5380 5381 v = port->qvecs + i; 5382 5383 v->port = port; 5384 v->type = MVPP2_QUEUE_VECTOR_PRIVATE; 5385 v->sw_thread_id = i; 5386 v->sw_thread_mask = BIT(i); 5387 5388 if (port->flags & MVPP2_F_DT_COMPAT) 5389 snprintf(irqname, sizeof(irqname), "tx-cpu%d", i); 5390 else 5391 snprintf(irqname, sizeof(irqname), "hif%d", i); 5392 5393 if (queue_mode == MVPP2_QDIST_MULTI_MODE) { 5394 v->first_rxq = i; 5395 v->nrxqs = 1; 5396 } else if (queue_mode == MVPP2_QDIST_SINGLE_MODE && 5397 i == (port->nqvecs - 1)) { 5398 v->first_rxq = 0; 5399 v->nrxqs = port->nrxqs; 5400 v->type = MVPP2_QUEUE_VECTOR_SHARED; 5401 5402 if (port->flags & MVPP2_F_DT_COMPAT) 5403 strncpy(irqname, "rx-shared", sizeof(irqname)); 5404 } 5405 5406 if (port_node) 5407 v->irq = of_irq_get_byname(port_node, irqname); 5408 else 5409 v->irq = fwnode_irq_get(port->fwnode, i); 5410 if (v->irq <= 0) { 5411 ret = -EINVAL; 5412 goto err; 5413 } 5414 5415 netif_napi_add(port->dev, &v->napi, mvpp2_poll, 5416 NAPI_POLL_WEIGHT); 5417 } 5418 5419 return 0; 5420 5421 err: 5422 for (i = 0; i < port->nqvecs; i++) 5423 irq_dispose_mapping(port->qvecs[i].irq); 5424 return ret; 5425 } 5426 5427 static int mvpp2_queue_vectors_init(struct mvpp2_port *port, 5428 struct device_node *port_node) 5429 { 5430 if (port->has_tx_irqs) 5431 return mvpp2_multi_queue_vectors_init(port, port_node); 5432 else 5433 return mvpp2_simple_queue_vectors_init(port, port_node); 5434 } 5435 5436 static void mvpp2_queue_vectors_deinit(struct mvpp2_port *port) 5437 { 5438 int i; 5439 5440 for (i = 0; i < port->nqvecs; i++) 5441 irq_dispose_mapping(port->qvecs[i].irq); 5442 } 5443 5444 /* Configure Rx queue group interrupt for this port */ 5445 static void mvpp2_rx_irqs_setup(struct mvpp2_port *port) 5446 { 5447 struct mvpp2 *priv = port->priv; 5448 u32 val; 5449 int i; 5450 5451 if (priv->hw_version == MVPP21) { 5452 mvpp2_write(priv, MVPP21_ISR_RXQ_GROUP_REG(port->id), 5453 port->nrxqs); 5454 return; 5455 } 5456 5457 /* Handle the more complicated PPv2.2 case */ 5458 for (i = 0; i < port->nqvecs; i++) { 5459 struct mvpp2_queue_vector *qv = port->qvecs + i; 5460 5461 if (!qv->nrxqs) 5462 continue; 5463 5464 val = qv->sw_thread_id; 5465 val |= port->id << MVPP22_ISR_RXQ_GROUP_INDEX_GROUP_OFFSET; 5466 mvpp2_write(priv, MVPP22_ISR_RXQ_GROUP_INDEX_REG, val); 5467 5468 val = qv->first_rxq; 5469 val |= qv->nrxqs << MVPP22_ISR_RXQ_SUB_GROUP_SIZE_OFFSET; 5470 mvpp2_write(priv, MVPP22_ISR_RXQ_SUB_GROUP_CONFIG_REG, val); 5471 } 5472 } 5473 5474 /* Initialize port HW */ 5475 static int mvpp2_port_init(struct mvpp2_port *port) 5476 { 5477 struct device *dev = port->dev->dev.parent; 5478 struct mvpp2 *priv = port->priv; 5479 struct mvpp2_txq_pcpu *txq_pcpu; 5480 unsigned int thread; 5481 int queue, err; 5482 5483 /* Checks for hardware constraints */ 5484 if (port->first_rxq + port->nrxqs > 5485 MVPP2_MAX_PORTS * priv->max_port_rxqs) 5486 return -EINVAL; 5487 5488 if (port->nrxqs > priv->max_port_rxqs || port->ntxqs > MVPP2_MAX_TXQ) 5489 return -EINVAL; 5490 5491 /* Disable port */ 5492 mvpp2_egress_disable(port); 5493 mvpp2_port_disable(port); 5494 5495 port->tx_time_coal = MVPP2_TXDONE_COAL_USEC; 5496 5497 port->txqs = devm_kcalloc(dev, port->ntxqs, sizeof(*port->txqs), 5498 GFP_KERNEL); 5499 if (!port->txqs) 5500 return -ENOMEM; 5501 5502 /* Associate physical Tx queues to this port and initialize. 5503 * The mapping is predefined. 5504 */ 5505 for (queue = 0; queue < port->ntxqs; queue++) { 5506 int queue_phy_id = mvpp2_txq_phys(port->id, queue); 5507 struct mvpp2_tx_queue *txq; 5508 5509 txq = devm_kzalloc(dev, sizeof(*txq), GFP_KERNEL); 5510 if (!txq) { 5511 err = -ENOMEM; 5512 goto err_free_percpu; 5513 } 5514 5515 txq->pcpu = alloc_percpu(struct mvpp2_txq_pcpu); 5516 if (!txq->pcpu) { 5517 err = -ENOMEM; 5518 goto err_free_percpu; 5519 } 5520 5521 txq->id = queue_phy_id; 5522 txq->log_id = queue; 5523 txq->done_pkts_coal = MVPP2_TXDONE_COAL_PKTS_THRESH; 5524 for (thread = 0; thread < priv->nthreads; thread++) { 5525 txq_pcpu = per_cpu_ptr(txq->pcpu, thread); 5526 txq_pcpu->thread = thread; 5527 } 5528 5529 port->txqs[queue] = txq; 5530 } 5531 5532 port->rxqs = devm_kcalloc(dev, port->nrxqs, sizeof(*port->rxqs), 5533 GFP_KERNEL); 5534 if (!port->rxqs) { 5535 err = -ENOMEM; 5536 goto err_free_percpu; 5537 } 5538 5539 /* Allocate and initialize Rx queue for this port */ 5540 for (queue = 0; queue < port->nrxqs; queue++) { 5541 struct mvpp2_rx_queue *rxq; 5542 5543 /* Map physical Rx queue to port's logical Rx queue */ 5544 rxq = devm_kzalloc(dev, sizeof(*rxq), GFP_KERNEL); 5545 if (!rxq) { 5546 err = -ENOMEM; 5547 goto err_free_percpu; 5548 } 5549 /* Map this Rx queue to a physical queue */ 5550 rxq->id = port->first_rxq + queue; 5551 rxq->port = port->id; 5552 rxq->logic_rxq = queue; 5553 5554 port->rxqs[queue] = rxq; 5555 } 5556 5557 mvpp2_rx_irqs_setup(port); 5558 5559 /* Create Rx descriptor rings */ 5560 for (queue = 0; queue < port->nrxqs; queue++) { 5561 struct mvpp2_rx_queue *rxq = port->rxqs[queue]; 5562 5563 rxq->size = port->rx_ring_size; 5564 rxq->pkts_coal = MVPP2_RX_COAL_PKTS; 5565 rxq->time_coal = MVPP2_RX_COAL_USEC; 5566 } 5567 5568 mvpp2_ingress_disable(port); 5569 5570 /* Port default configuration */ 5571 mvpp2_defaults_set(port); 5572 5573 /* Port's classifier configuration */ 5574 mvpp2_cls_oversize_rxq_set(port); 5575 mvpp2_cls_port_config(port); 5576 5577 if (mvpp22_rss_is_supported()) 5578 mvpp22_port_rss_init(port); 5579 5580 /* Provide an initial Rx packet size */ 5581 port->pkt_size = MVPP2_RX_PKT_SIZE(port->dev->mtu); 5582 5583 /* Initialize pools for swf */ 5584 err = mvpp2_swf_bm_pool_init(port); 5585 if (err) 5586 goto err_free_percpu; 5587 5588 /* Clear all port stats */ 5589 mvpp2_read_stats(port); 5590 memset(port->ethtool_stats, 0, 5591 MVPP2_N_ETHTOOL_STATS(port->ntxqs, port->nrxqs) * sizeof(u64)); 5592 5593 return 0; 5594 5595 err_free_percpu: 5596 for (queue = 0; queue < port->ntxqs; queue++) { 5597 if (!port->txqs[queue]) 5598 continue; 5599 free_percpu(port->txqs[queue]->pcpu); 5600 } 5601 return err; 5602 } 5603 5604 static bool mvpp22_port_has_legacy_tx_irqs(struct device_node *port_node, 5605 unsigned long *flags) 5606 { 5607 char *irqs[5] = { "rx-shared", "tx-cpu0", "tx-cpu1", "tx-cpu2", 5608 "tx-cpu3" }; 5609 int i; 5610 5611 for (i = 0; i < 5; i++) 5612 if (of_property_match_string(port_node, "interrupt-names", 5613 irqs[i]) < 0) 5614 return false; 5615 5616 *flags |= MVPP2_F_DT_COMPAT; 5617 return true; 5618 } 5619 5620 /* Checks if the port dt description has the required Tx interrupts: 5621 * - PPv2.1: there are no such interrupts. 5622 * - PPv2.2: 5623 * - The old DTs have: "rx-shared", "tx-cpuX" with X in [0...3] 5624 * - The new ones have: "hifX" with X in [0..8] 5625 * 5626 * All those variants are supported to keep the backward compatibility. 5627 */ 5628 static bool mvpp2_port_has_irqs(struct mvpp2 *priv, 5629 struct device_node *port_node, 5630 unsigned long *flags) 5631 { 5632 char name[5]; 5633 int i; 5634 5635 /* ACPI */ 5636 if (!port_node) 5637 return true; 5638 5639 if (priv->hw_version == MVPP21) 5640 return false; 5641 5642 if (mvpp22_port_has_legacy_tx_irqs(port_node, flags)) 5643 return true; 5644 5645 for (i = 0; i < MVPP2_MAX_THREADS; i++) { 5646 snprintf(name, 5, "hif%d", i); 5647 if (of_property_match_string(port_node, "interrupt-names", 5648 name) < 0) 5649 return false; 5650 } 5651 5652 return true; 5653 } 5654 5655 static void mvpp2_port_copy_mac_addr(struct net_device *dev, struct mvpp2 *priv, 5656 struct fwnode_handle *fwnode, 5657 char **mac_from) 5658 { 5659 struct mvpp2_port *port = netdev_priv(dev); 5660 char hw_mac_addr[ETH_ALEN] = {0}; 5661 char fw_mac_addr[ETH_ALEN]; 5662 5663 if (fwnode_get_mac_address(fwnode, fw_mac_addr, ETH_ALEN)) { 5664 *mac_from = "firmware node"; 5665 ether_addr_copy(dev->dev_addr, fw_mac_addr); 5666 return; 5667 } 5668 5669 if (priv->hw_version == MVPP21) { 5670 mvpp21_get_mac_address(port, hw_mac_addr); 5671 if (is_valid_ether_addr(hw_mac_addr)) { 5672 *mac_from = "hardware"; 5673 ether_addr_copy(dev->dev_addr, hw_mac_addr); 5674 return; 5675 } 5676 } 5677 5678 *mac_from = "random"; 5679 eth_hw_addr_random(dev); 5680 } 5681 5682 static struct mvpp2_port *mvpp2_phylink_to_port(struct phylink_config *config) 5683 { 5684 return container_of(config, struct mvpp2_port, phylink_config); 5685 } 5686 5687 static struct mvpp2_port *mvpp2_pcs_to_port(struct phylink_pcs *pcs) 5688 { 5689 return container_of(pcs, struct mvpp2_port, phylink_pcs); 5690 } 5691 5692 static void mvpp2_xlg_pcs_get_state(struct phylink_pcs *pcs, 5693 struct phylink_link_state *state) 5694 { 5695 struct mvpp2_port *port = mvpp2_pcs_to_port(pcs); 5696 u32 val; 5697 5698 state->speed = SPEED_10000; 5699 state->duplex = 1; 5700 state->an_complete = 1; 5701 5702 val = readl(port->base + MVPP22_XLG_STATUS); 5703 state->link = !!(val & MVPP22_XLG_STATUS_LINK_UP); 5704 5705 state->pause = 0; 5706 val = readl(port->base + MVPP22_XLG_CTRL0_REG); 5707 if (val & MVPP22_XLG_CTRL0_TX_FLOW_CTRL_EN) 5708 state->pause |= MLO_PAUSE_TX; 5709 if (val & MVPP22_XLG_CTRL0_RX_FLOW_CTRL_EN) 5710 state->pause |= MLO_PAUSE_RX; 5711 } 5712 5713 static int mvpp2_xlg_pcs_config(struct phylink_pcs *pcs, 5714 unsigned int mode, 5715 phy_interface_t interface, 5716 const unsigned long *advertising, 5717 bool permit_pause_to_mac) 5718 { 5719 return 0; 5720 } 5721 5722 static const struct phylink_pcs_ops mvpp2_phylink_xlg_pcs_ops = { 5723 .pcs_get_state = mvpp2_xlg_pcs_get_state, 5724 .pcs_config = mvpp2_xlg_pcs_config, 5725 }; 5726 5727 static void mvpp2_gmac_pcs_get_state(struct phylink_pcs *pcs, 5728 struct phylink_link_state *state) 5729 { 5730 struct mvpp2_port *port = mvpp2_pcs_to_port(pcs); 5731 u32 val; 5732 5733 val = readl(port->base + MVPP2_GMAC_STATUS0); 5734 5735 state->an_complete = !!(val & MVPP2_GMAC_STATUS0_AN_COMPLETE); 5736 state->link = !!(val & MVPP2_GMAC_STATUS0_LINK_UP); 5737 state->duplex = !!(val & MVPP2_GMAC_STATUS0_FULL_DUPLEX); 5738 5739 switch (port->phy_interface) { 5740 case PHY_INTERFACE_MODE_1000BASEX: 5741 state->speed = SPEED_1000; 5742 break; 5743 case PHY_INTERFACE_MODE_2500BASEX: 5744 state->speed = SPEED_2500; 5745 break; 5746 default: 5747 if (val & MVPP2_GMAC_STATUS0_GMII_SPEED) 5748 state->speed = SPEED_1000; 5749 else if (val & MVPP2_GMAC_STATUS0_MII_SPEED) 5750 state->speed = SPEED_100; 5751 else 5752 state->speed = SPEED_10; 5753 } 5754 5755 state->pause = 0; 5756 if (val & MVPP2_GMAC_STATUS0_RX_PAUSE) 5757 state->pause |= MLO_PAUSE_RX; 5758 if (val & MVPP2_GMAC_STATUS0_TX_PAUSE) 5759 state->pause |= MLO_PAUSE_TX; 5760 } 5761 5762 static int mvpp2_gmac_pcs_config(struct phylink_pcs *pcs, unsigned int mode, 5763 phy_interface_t interface, 5764 const unsigned long *advertising, 5765 bool permit_pause_to_mac) 5766 { 5767 struct mvpp2_port *port = mvpp2_pcs_to_port(pcs); 5768 u32 mask, val, an, old_an, changed; 5769 5770 mask = MVPP2_GMAC_IN_BAND_AUTONEG_BYPASS | 5771 MVPP2_GMAC_IN_BAND_AUTONEG | 5772 MVPP2_GMAC_AN_SPEED_EN | 5773 MVPP2_GMAC_FLOW_CTRL_AUTONEG | 5774 MVPP2_GMAC_AN_DUPLEX_EN; 5775 5776 if (phylink_autoneg_inband(mode)) { 5777 mask |= MVPP2_GMAC_CONFIG_MII_SPEED | 5778 MVPP2_GMAC_CONFIG_GMII_SPEED | 5779 MVPP2_GMAC_CONFIG_FULL_DUPLEX; 5780 val = MVPP2_GMAC_IN_BAND_AUTONEG; 5781 5782 if (interface == PHY_INTERFACE_MODE_SGMII) { 5783 /* SGMII mode receives the speed and duplex from PHY */ 5784 val |= MVPP2_GMAC_AN_SPEED_EN | 5785 MVPP2_GMAC_AN_DUPLEX_EN; 5786 } else { 5787 /* 802.3z mode has fixed speed and duplex */ 5788 val |= MVPP2_GMAC_CONFIG_GMII_SPEED | 5789 MVPP2_GMAC_CONFIG_FULL_DUPLEX; 5790 5791 /* The FLOW_CTRL_AUTONEG bit selects either the hardware 5792 * automatically or the bits in MVPP22_GMAC_CTRL_4_REG 5793 * manually controls the GMAC pause modes. 5794 */ 5795 if (permit_pause_to_mac) 5796 val |= MVPP2_GMAC_FLOW_CTRL_AUTONEG; 5797 5798 /* Configure advertisement bits */ 5799 mask |= MVPP2_GMAC_FC_ADV_EN | MVPP2_GMAC_FC_ADV_ASM_EN; 5800 if (phylink_test(advertising, Pause)) 5801 val |= MVPP2_GMAC_FC_ADV_EN; 5802 if (phylink_test(advertising, Asym_Pause)) 5803 val |= MVPP2_GMAC_FC_ADV_ASM_EN; 5804 } 5805 } else { 5806 val = 0; 5807 } 5808 5809 old_an = an = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG); 5810 an = (an & ~mask) | val; 5811 changed = an ^ old_an; 5812 if (changed) 5813 writel(an, port->base + MVPP2_GMAC_AUTONEG_CONFIG); 5814 5815 /* We are only interested in the advertisement bits changing */ 5816 return changed & (MVPP2_GMAC_FC_ADV_EN | MVPP2_GMAC_FC_ADV_ASM_EN); 5817 } 5818 5819 static void mvpp2_gmac_pcs_an_restart(struct phylink_pcs *pcs) 5820 { 5821 struct mvpp2_port *port = mvpp2_pcs_to_port(pcs); 5822 u32 val = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG); 5823 5824 writel(val | MVPP2_GMAC_IN_BAND_RESTART_AN, 5825 port->base + MVPP2_GMAC_AUTONEG_CONFIG); 5826 writel(val & ~MVPP2_GMAC_IN_BAND_RESTART_AN, 5827 port->base + MVPP2_GMAC_AUTONEG_CONFIG); 5828 } 5829 5830 static const struct phylink_pcs_ops mvpp2_phylink_gmac_pcs_ops = { 5831 .pcs_get_state = mvpp2_gmac_pcs_get_state, 5832 .pcs_config = mvpp2_gmac_pcs_config, 5833 .pcs_an_restart = mvpp2_gmac_pcs_an_restart, 5834 }; 5835 5836 static void mvpp2_phylink_validate(struct phylink_config *config, 5837 unsigned long *supported, 5838 struct phylink_link_state *state) 5839 { 5840 struct mvpp2_port *port = mvpp2_phylink_to_port(config); 5841 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, }; 5842 5843 /* Invalid combinations */ 5844 switch (state->interface) { 5845 case PHY_INTERFACE_MODE_10GBASER: 5846 case PHY_INTERFACE_MODE_XAUI: 5847 if (!mvpp2_port_supports_xlg(port)) 5848 goto empty_set; 5849 break; 5850 case PHY_INTERFACE_MODE_RGMII: 5851 case PHY_INTERFACE_MODE_RGMII_ID: 5852 case PHY_INTERFACE_MODE_RGMII_RXID: 5853 case PHY_INTERFACE_MODE_RGMII_TXID: 5854 if (!mvpp2_port_supports_rgmii(port)) 5855 goto empty_set; 5856 break; 5857 default: 5858 break; 5859 } 5860 5861 phylink_set(mask, Autoneg); 5862 phylink_set_port_modes(mask); 5863 phylink_set(mask, Pause); 5864 phylink_set(mask, Asym_Pause); 5865 5866 switch (state->interface) { 5867 case PHY_INTERFACE_MODE_10GBASER: 5868 case PHY_INTERFACE_MODE_XAUI: 5869 case PHY_INTERFACE_MODE_NA: 5870 if (mvpp2_port_supports_xlg(port)) { 5871 phylink_set(mask, 10000baseT_Full); 5872 phylink_set(mask, 10000baseCR_Full); 5873 phylink_set(mask, 10000baseSR_Full); 5874 phylink_set(mask, 10000baseLR_Full); 5875 phylink_set(mask, 10000baseLRM_Full); 5876 phylink_set(mask, 10000baseER_Full); 5877 phylink_set(mask, 10000baseKR_Full); 5878 } 5879 if (state->interface != PHY_INTERFACE_MODE_NA) 5880 break; 5881 fallthrough; 5882 case PHY_INTERFACE_MODE_RGMII: 5883 case PHY_INTERFACE_MODE_RGMII_ID: 5884 case PHY_INTERFACE_MODE_RGMII_RXID: 5885 case PHY_INTERFACE_MODE_RGMII_TXID: 5886 case PHY_INTERFACE_MODE_SGMII: 5887 phylink_set(mask, 10baseT_Half); 5888 phylink_set(mask, 10baseT_Full); 5889 phylink_set(mask, 100baseT_Half); 5890 phylink_set(mask, 100baseT_Full); 5891 phylink_set(mask, 1000baseT_Full); 5892 phylink_set(mask, 1000baseX_Full); 5893 if (state->interface != PHY_INTERFACE_MODE_NA) 5894 break; 5895 fallthrough; 5896 case PHY_INTERFACE_MODE_1000BASEX: 5897 case PHY_INTERFACE_MODE_2500BASEX: 5898 if (port->comphy || 5899 state->interface != PHY_INTERFACE_MODE_2500BASEX) { 5900 phylink_set(mask, 1000baseT_Full); 5901 phylink_set(mask, 1000baseX_Full); 5902 } 5903 if (port->comphy || 5904 state->interface == PHY_INTERFACE_MODE_2500BASEX) { 5905 phylink_set(mask, 2500baseT_Full); 5906 phylink_set(mask, 2500baseX_Full); 5907 } 5908 break; 5909 default: 5910 goto empty_set; 5911 } 5912 5913 bitmap_and(supported, supported, mask, __ETHTOOL_LINK_MODE_MASK_NBITS); 5914 bitmap_and(state->advertising, state->advertising, mask, 5915 __ETHTOOL_LINK_MODE_MASK_NBITS); 5916 5917 phylink_helper_basex_speed(state); 5918 return; 5919 5920 empty_set: 5921 bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS); 5922 } 5923 5924 static void mvpp2_xlg_config(struct mvpp2_port *port, unsigned int mode, 5925 const struct phylink_link_state *state) 5926 { 5927 u32 val; 5928 5929 mvpp2_modify(port->base + MVPP22_XLG_CTRL0_REG, 5930 MVPP22_XLG_CTRL0_MAC_RESET_DIS, 5931 MVPP22_XLG_CTRL0_MAC_RESET_DIS); 5932 mvpp2_modify(port->base + MVPP22_XLG_CTRL4_REG, 5933 MVPP22_XLG_CTRL4_MACMODSELECT_GMAC | 5934 MVPP22_XLG_CTRL4_EN_IDLE_CHECK | 5935 MVPP22_XLG_CTRL4_FWD_FC | MVPP22_XLG_CTRL4_FWD_PFC, 5936 MVPP22_XLG_CTRL4_FWD_FC | MVPP22_XLG_CTRL4_FWD_PFC); 5937 5938 /* Wait for reset to deassert */ 5939 do { 5940 val = readl(port->base + MVPP22_XLG_CTRL0_REG); 5941 } while (!(val & MVPP22_XLG_CTRL0_MAC_RESET_DIS)); 5942 } 5943 5944 static void mvpp2_gmac_config(struct mvpp2_port *port, unsigned int mode, 5945 const struct phylink_link_state *state) 5946 { 5947 u32 old_ctrl0, ctrl0; 5948 u32 old_ctrl2, ctrl2; 5949 u32 old_ctrl4, ctrl4; 5950 5951 old_ctrl0 = ctrl0 = readl(port->base + MVPP2_GMAC_CTRL_0_REG); 5952 old_ctrl2 = ctrl2 = readl(port->base + MVPP2_GMAC_CTRL_2_REG); 5953 old_ctrl4 = ctrl4 = readl(port->base + MVPP22_GMAC_CTRL_4_REG); 5954 5955 ctrl0 &= ~MVPP2_GMAC_PORT_TYPE_MASK; 5956 ctrl2 &= ~(MVPP2_GMAC_INBAND_AN_MASK | MVPP2_GMAC_PCS_ENABLE_MASK); 5957 5958 /* Configure port type */ 5959 if (phy_interface_mode_is_8023z(state->interface)) { 5960 ctrl2 |= MVPP2_GMAC_PCS_ENABLE_MASK; 5961 ctrl4 &= ~MVPP22_CTRL4_EXT_PIN_GMII_SEL; 5962 ctrl4 |= MVPP22_CTRL4_SYNC_BYPASS_DIS | 5963 MVPP22_CTRL4_DP_CLK_SEL | 5964 MVPP22_CTRL4_QSGMII_BYPASS_ACTIVE; 5965 } else if (state->interface == PHY_INTERFACE_MODE_SGMII) { 5966 ctrl2 |= MVPP2_GMAC_PCS_ENABLE_MASK | MVPP2_GMAC_INBAND_AN_MASK; 5967 ctrl4 &= ~MVPP22_CTRL4_EXT_PIN_GMII_SEL; 5968 ctrl4 |= MVPP22_CTRL4_SYNC_BYPASS_DIS | 5969 MVPP22_CTRL4_DP_CLK_SEL | 5970 MVPP22_CTRL4_QSGMII_BYPASS_ACTIVE; 5971 } else if (phy_interface_mode_is_rgmii(state->interface)) { 5972 ctrl4 &= ~MVPP22_CTRL4_DP_CLK_SEL; 5973 ctrl4 |= MVPP22_CTRL4_EXT_PIN_GMII_SEL | 5974 MVPP22_CTRL4_SYNC_BYPASS_DIS | 5975 MVPP22_CTRL4_QSGMII_BYPASS_ACTIVE; 5976 } 5977 5978 /* Configure negotiation style */ 5979 if (!phylink_autoneg_inband(mode)) { 5980 /* Phy or fixed speed - no in-band AN, nothing to do, leave the 5981 * configured speed, duplex and flow control as-is. 5982 */ 5983 } else if (state->interface == PHY_INTERFACE_MODE_SGMII) { 5984 /* SGMII in-band mode receives the speed and duplex from 5985 * the PHY. Flow control information is not received. */ 5986 } else if (phy_interface_mode_is_8023z(state->interface)) { 5987 /* 1000BaseX and 2500BaseX ports cannot negotiate speed nor can 5988 * they negotiate duplex: they are always operating with a fixed 5989 * speed of 1000/2500Mbps in full duplex, so force 1000/2500 5990 * speed and full duplex here. 5991 */ 5992 ctrl0 |= MVPP2_GMAC_PORT_TYPE_MASK; 5993 } 5994 5995 if (old_ctrl0 != ctrl0) 5996 writel(ctrl0, port->base + MVPP2_GMAC_CTRL_0_REG); 5997 if (old_ctrl2 != ctrl2) 5998 writel(ctrl2, port->base + MVPP2_GMAC_CTRL_2_REG); 5999 if (old_ctrl4 != ctrl4) 6000 writel(ctrl4, port->base + MVPP22_GMAC_CTRL_4_REG); 6001 } 6002 6003 static int mvpp2__mac_prepare(struct phylink_config *config, unsigned int mode, 6004 phy_interface_t interface) 6005 { 6006 struct mvpp2_port *port = mvpp2_phylink_to_port(config); 6007 6008 /* Check for invalid configuration */ 6009 if (mvpp2_is_xlg(interface) && port->gop_id != 0) { 6010 netdev_err(port->dev, "Invalid mode on %s\n", port->dev->name); 6011 return -EINVAL; 6012 } 6013 6014 if (port->phy_interface != interface || 6015 phylink_autoneg_inband(mode)) { 6016 /* Force the link down when changing the interface or if in 6017 * in-band mode to ensure we do not change the configuration 6018 * while the hardware is indicating link is up. We force both 6019 * XLG and GMAC down to ensure that they're both in a known 6020 * state. 6021 */ 6022 mvpp2_modify(port->base + MVPP2_GMAC_AUTONEG_CONFIG, 6023 MVPP2_GMAC_FORCE_LINK_PASS | 6024 MVPP2_GMAC_FORCE_LINK_DOWN, 6025 MVPP2_GMAC_FORCE_LINK_DOWN); 6026 6027 if (mvpp2_port_supports_xlg(port)) 6028 mvpp2_modify(port->base + MVPP22_XLG_CTRL0_REG, 6029 MVPP22_XLG_CTRL0_FORCE_LINK_PASS | 6030 MVPP22_XLG_CTRL0_FORCE_LINK_DOWN, 6031 MVPP22_XLG_CTRL0_FORCE_LINK_DOWN); 6032 } 6033 6034 /* Make sure the port is disabled when reconfiguring the mode */ 6035 mvpp2_port_disable(port); 6036 6037 if (port->phy_interface != interface) { 6038 /* Place GMAC into reset */ 6039 mvpp2_modify(port->base + MVPP2_GMAC_CTRL_2_REG, 6040 MVPP2_GMAC_PORT_RESET_MASK, 6041 MVPP2_GMAC_PORT_RESET_MASK); 6042 6043 if (port->priv->hw_version == MVPP22) { 6044 mvpp22_gop_mask_irq(port); 6045 6046 phy_power_off(port->comphy); 6047 } 6048 } 6049 6050 /* Select the appropriate PCS operations depending on the 6051 * configured interface mode. We will only switch to a mode 6052 * that the validate() checks have already passed. 6053 */ 6054 if (mvpp2_is_xlg(interface)) 6055 port->phylink_pcs.ops = &mvpp2_phylink_xlg_pcs_ops; 6056 else 6057 port->phylink_pcs.ops = &mvpp2_phylink_gmac_pcs_ops; 6058 6059 return 0; 6060 } 6061 6062 static int mvpp2_mac_prepare(struct phylink_config *config, unsigned int mode, 6063 phy_interface_t interface) 6064 { 6065 struct mvpp2_port *port = mvpp2_phylink_to_port(config); 6066 int ret; 6067 6068 ret = mvpp2__mac_prepare(config, mode, interface); 6069 if (ret == 0) 6070 phylink_set_pcs(port->phylink, &port->phylink_pcs); 6071 6072 return ret; 6073 } 6074 6075 static void mvpp2_mac_config(struct phylink_config *config, unsigned int mode, 6076 const struct phylink_link_state *state) 6077 { 6078 struct mvpp2_port *port = mvpp2_phylink_to_port(config); 6079 6080 /* mac (re)configuration */ 6081 if (mvpp2_is_xlg(state->interface)) 6082 mvpp2_xlg_config(port, mode, state); 6083 else if (phy_interface_mode_is_rgmii(state->interface) || 6084 phy_interface_mode_is_8023z(state->interface) || 6085 state->interface == PHY_INTERFACE_MODE_SGMII) 6086 mvpp2_gmac_config(port, mode, state); 6087 6088 if (port->priv->hw_version == MVPP21 && port->flags & MVPP2_F_LOOPBACK) 6089 mvpp2_port_loopback_set(port, state); 6090 } 6091 6092 static int mvpp2_mac_finish(struct phylink_config *config, unsigned int mode, 6093 phy_interface_t interface) 6094 { 6095 struct mvpp2_port *port = mvpp2_phylink_to_port(config); 6096 6097 if (port->priv->hw_version == MVPP22 && 6098 port->phy_interface != interface) { 6099 port->phy_interface = interface; 6100 6101 /* Reconfigure the serdes lanes */ 6102 mvpp22_mode_reconfigure(port); 6103 6104 /* Unmask interrupts */ 6105 mvpp22_gop_unmask_irq(port); 6106 } 6107 6108 if (!mvpp2_is_xlg(interface)) { 6109 /* Release GMAC reset and wait */ 6110 mvpp2_modify(port->base + MVPP2_GMAC_CTRL_2_REG, 6111 MVPP2_GMAC_PORT_RESET_MASK, 0); 6112 6113 while (readl(port->base + MVPP2_GMAC_CTRL_2_REG) & 6114 MVPP2_GMAC_PORT_RESET_MASK) 6115 continue; 6116 } 6117 6118 mvpp2_port_enable(port); 6119 6120 /* Allow the link to come up if in in-band mode, otherwise the 6121 * link is forced via mac_link_down()/mac_link_up() 6122 */ 6123 if (phylink_autoneg_inband(mode)) { 6124 if (mvpp2_is_xlg(interface)) 6125 mvpp2_modify(port->base + MVPP22_XLG_CTRL0_REG, 6126 MVPP22_XLG_CTRL0_FORCE_LINK_PASS | 6127 MVPP22_XLG_CTRL0_FORCE_LINK_DOWN, 0); 6128 else 6129 mvpp2_modify(port->base + MVPP2_GMAC_AUTONEG_CONFIG, 6130 MVPP2_GMAC_FORCE_LINK_PASS | 6131 MVPP2_GMAC_FORCE_LINK_DOWN, 0); 6132 } 6133 6134 return 0; 6135 } 6136 6137 static void mvpp2_mac_link_up(struct phylink_config *config, 6138 struct phy_device *phy, 6139 unsigned int mode, phy_interface_t interface, 6140 int speed, int duplex, 6141 bool tx_pause, bool rx_pause) 6142 { 6143 struct mvpp2_port *port = mvpp2_phylink_to_port(config); 6144 u32 val; 6145 6146 if (mvpp2_is_xlg(interface)) { 6147 if (!phylink_autoneg_inband(mode)) { 6148 val = MVPP22_XLG_CTRL0_FORCE_LINK_PASS; 6149 if (tx_pause) 6150 val |= MVPP22_XLG_CTRL0_TX_FLOW_CTRL_EN; 6151 if (rx_pause) 6152 val |= MVPP22_XLG_CTRL0_RX_FLOW_CTRL_EN; 6153 6154 mvpp2_modify(port->base + MVPP22_XLG_CTRL0_REG, 6155 MVPP22_XLG_CTRL0_FORCE_LINK_DOWN | 6156 MVPP22_XLG_CTRL0_FORCE_LINK_PASS | 6157 MVPP22_XLG_CTRL0_TX_FLOW_CTRL_EN | 6158 MVPP22_XLG_CTRL0_RX_FLOW_CTRL_EN, val); 6159 } 6160 } else { 6161 if (!phylink_autoneg_inband(mode)) { 6162 val = MVPP2_GMAC_FORCE_LINK_PASS; 6163 6164 if (speed == SPEED_1000 || speed == SPEED_2500) 6165 val |= MVPP2_GMAC_CONFIG_GMII_SPEED; 6166 else if (speed == SPEED_100) 6167 val |= MVPP2_GMAC_CONFIG_MII_SPEED; 6168 6169 if (duplex == DUPLEX_FULL) 6170 val |= MVPP2_GMAC_CONFIG_FULL_DUPLEX; 6171 6172 mvpp2_modify(port->base + MVPP2_GMAC_AUTONEG_CONFIG, 6173 MVPP2_GMAC_FORCE_LINK_DOWN | 6174 MVPP2_GMAC_FORCE_LINK_PASS | 6175 MVPP2_GMAC_CONFIG_MII_SPEED | 6176 MVPP2_GMAC_CONFIG_GMII_SPEED | 6177 MVPP2_GMAC_CONFIG_FULL_DUPLEX, val); 6178 } 6179 6180 /* We can always update the flow control enable bits; 6181 * these will only be effective if flow control AN 6182 * (MVPP2_GMAC_FLOW_CTRL_AUTONEG) is disabled. 6183 */ 6184 val = 0; 6185 if (tx_pause) 6186 val |= MVPP22_CTRL4_TX_FC_EN; 6187 if (rx_pause) 6188 val |= MVPP22_CTRL4_RX_FC_EN; 6189 6190 mvpp2_modify(port->base + MVPP22_GMAC_CTRL_4_REG, 6191 MVPP22_CTRL4_RX_FC_EN | MVPP22_CTRL4_TX_FC_EN, 6192 val); 6193 } 6194 6195 mvpp2_port_enable(port); 6196 6197 mvpp2_egress_enable(port); 6198 mvpp2_ingress_enable(port); 6199 netif_tx_wake_all_queues(port->dev); 6200 } 6201 6202 static void mvpp2_mac_link_down(struct phylink_config *config, 6203 unsigned int mode, phy_interface_t interface) 6204 { 6205 struct mvpp2_port *port = mvpp2_phylink_to_port(config); 6206 u32 val; 6207 6208 if (!phylink_autoneg_inband(mode)) { 6209 if (mvpp2_is_xlg(interface)) { 6210 val = readl(port->base + MVPP22_XLG_CTRL0_REG); 6211 val &= ~MVPP22_XLG_CTRL0_FORCE_LINK_PASS; 6212 val |= MVPP22_XLG_CTRL0_FORCE_LINK_DOWN; 6213 writel(val, port->base + MVPP22_XLG_CTRL0_REG); 6214 } else { 6215 val = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG); 6216 val &= ~MVPP2_GMAC_FORCE_LINK_PASS; 6217 val |= MVPP2_GMAC_FORCE_LINK_DOWN; 6218 writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG); 6219 } 6220 } 6221 6222 netif_tx_stop_all_queues(port->dev); 6223 mvpp2_egress_disable(port); 6224 mvpp2_ingress_disable(port); 6225 6226 mvpp2_port_disable(port); 6227 } 6228 6229 static const struct phylink_mac_ops mvpp2_phylink_ops = { 6230 .validate = mvpp2_phylink_validate, 6231 .mac_prepare = mvpp2_mac_prepare, 6232 .mac_config = mvpp2_mac_config, 6233 .mac_finish = mvpp2_mac_finish, 6234 .mac_link_up = mvpp2_mac_link_up, 6235 .mac_link_down = mvpp2_mac_link_down, 6236 }; 6237 6238 /* Work-around for ACPI */ 6239 static void mvpp2_acpi_start(struct mvpp2_port *port) 6240 { 6241 /* Phylink isn't used as of now for ACPI, so the MAC has to be 6242 * configured manually when the interface is started. This will 6243 * be removed as soon as the phylink ACPI support lands in. 6244 */ 6245 struct phylink_link_state state = { 6246 .interface = port->phy_interface, 6247 }; 6248 mvpp2__mac_prepare(&port->phylink_config, MLO_AN_INBAND, 6249 port->phy_interface); 6250 mvpp2_mac_config(&port->phylink_config, MLO_AN_INBAND, &state); 6251 port->phylink_pcs.ops->pcs_config(&port->phylink_pcs, MLO_AN_INBAND, 6252 port->phy_interface, 6253 state.advertising, false); 6254 mvpp2_mac_finish(&port->phylink_config, MLO_AN_INBAND, 6255 port->phy_interface); 6256 mvpp2_mac_link_up(&port->phylink_config, NULL, 6257 MLO_AN_INBAND, port->phy_interface, 6258 SPEED_UNKNOWN, DUPLEX_UNKNOWN, false, false); 6259 } 6260 6261 /* Ports initialization */ 6262 static int mvpp2_port_probe(struct platform_device *pdev, 6263 struct fwnode_handle *port_fwnode, 6264 struct mvpp2 *priv) 6265 { 6266 struct phy *comphy = NULL; 6267 struct mvpp2_port *port; 6268 struct mvpp2_port_pcpu *port_pcpu; 6269 struct device_node *port_node = to_of_node(port_fwnode); 6270 netdev_features_t features; 6271 struct net_device *dev; 6272 struct phylink *phylink; 6273 char *mac_from = ""; 6274 unsigned int ntxqs, nrxqs, thread; 6275 unsigned long flags = 0; 6276 bool has_tx_irqs; 6277 u32 id; 6278 int phy_mode; 6279 int err, i; 6280 6281 has_tx_irqs = mvpp2_port_has_irqs(priv, port_node, &flags); 6282 if (!has_tx_irqs && queue_mode == MVPP2_QDIST_MULTI_MODE) { 6283 dev_err(&pdev->dev, 6284 "not enough IRQs to support multi queue mode\n"); 6285 return -EINVAL; 6286 } 6287 6288 ntxqs = MVPP2_MAX_TXQ; 6289 nrxqs = mvpp2_get_nrxqs(priv); 6290 6291 dev = alloc_etherdev_mqs(sizeof(*port), ntxqs, nrxqs); 6292 if (!dev) 6293 return -ENOMEM; 6294 6295 phy_mode = fwnode_get_phy_mode(port_fwnode); 6296 if (phy_mode < 0) { 6297 dev_err(&pdev->dev, "incorrect phy mode\n"); 6298 err = phy_mode; 6299 goto err_free_netdev; 6300 } 6301 6302 /* 6303 * Rewrite 10GBASE-KR to 10GBASE-R for compatibility with existing DT. 6304 * Existing usage of 10GBASE-KR is not correct; no backplane 6305 * negotiation is done, and this driver does not actually support 6306 * 10GBASE-KR. 6307 */ 6308 if (phy_mode == PHY_INTERFACE_MODE_10GKR) 6309 phy_mode = PHY_INTERFACE_MODE_10GBASER; 6310 6311 if (port_node) { 6312 comphy = devm_of_phy_get(&pdev->dev, port_node, NULL); 6313 if (IS_ERR(comphy)) { 6314 if (PTR_ERR(comphy) == -EPROBE_DEFER) { 6315 err = -EPROBE_DEFER; 6316 goto err_free_netdev; 6317 } 6318 comphy = NULL; 6319 } 6320 } 6321 6322 if (fwnode_property_read_u32(port_fwnode, "port-id", &id)) { 6323 err = -EINVAL; 6324 dev_err(&pdev->dev, "missing port-id value\n"); 6325 goto err_free_netdev; 6326 } 6327 6328 dev->tx_queue_len = MVPP2_MAX_TXD_MAX; 6329 dev->watchdog_timeo = 5 * HZ; 6330 dev->netdev_ops = &mvpp2_netdev_ops; 6331 dev->ethtool_ops = &mvpp2_eth_tool_ops; 6332 6333 port = netdev_priv(dev); 6334 port->dev = dev; 6335 port->fwnode = port_fwnode; 6336 port->has_phy = !!of_find_property(port_node, "phy", NULL); 6337 port->ntxqs = ntxqs; 6338 port->nrxqs = nrxqs; 6339 port->priv = priv; 6340 port->has_tx_irqs = has_tx_irqs; 6341 port->flags = flags; 6342 6343 err = mvpp2_queue_vectors_init(port, port_node); 6344 if (err) 6345 goto err_free_netdev; 6346 6347 if (port_node) 6348 port->port_irq = of_irq_get_byname(port_node, "link"); 6349 else 6350 port->port_irq = fwnode_irq_get(port_fwnode, port->nqvecs + 1); 6351 if (port->port_irq == -EPROBE_DEFER) { 6352 err = -EPROBE_DEFER; 6353 goto err_deinit_qvecs; 6354 } 6355 if (port->port_irq <= 0) 6356 /* the link irq is optional */ 6357 port->port_irq = 0; 6358 6359 if (fwnode_property_read_bool(port_fwnode, "marvell,loopback")) 6360 port->flags |= MVPP2_F_LOOPBACK; 6361 6362 port->id = id; 6363 if (priv->hw_version == MVPP21) 6364 port->first_rxq = port->id * port->nrxqs; 6365 else 6366 port->first_rxq = port->id * priv->max_port_rxqs; 6367 6368 port->of_node = port_node; 6369 port->phy_interface = phy_mode; 6370 port->comphy = comphy; 6371 6372 if (priv->hw_version == MVPP21) { 6373 port->base = devm_platform_ioremap_resource(pdev, 2 + id); 6374 if (IS_ERR(port->base)) { 6375 err = PTR_ERR(port->base); 6376 goto err_free_irq; 6377 } 6378 6379 port->stats_base = port->priv->lms_base + 6380 MVPP21_MIB_COUNTERS_OFFSET + 6381 port->gop_id * MVPP21_MIB_COUNTERS_PORT_SZ; 6382 } else { 6383 if (fwnode_property_read_u32(port_fwnode, "gop-port-id", 6384 &port->gop_id)) { 6385 err = -EINVAL; 6386 dev_err(&pdev->dev, "missing gop-port-id value\n"); 6387 goto err_deinit_qvecs; 6388 } 6389 6390 port->base = priv->iface_base + MVPP22_GMAC_BASE(port->gop_id); 6391 port->stats_base = port->priv->iface_base + 6392 MVPP22_MIB_COUNTERS_OFFSET + 6393 port->gop_id * MVPP22_MIB_COUNTERS_PORT_SZ; 6394 6395 /* We may want a property to describe whether we should use 6396 * MAC hardware timestamping. 6397 */ 6398 if (priv->tai) 6399 port->hwtstamp = true; 6400 } 6401 6402 /* Alloc per-cpu and ethtool stats */ 6403 port->stats = netdev_alloc_pcpu_stats(struct mvpp2_pcpu_stats); 6404 if (!port->stats) { 6405 err = -ENOMEM; 6406 goto err_free_irq; 6407 } 6408 6409 port->ethtool_stats = devm_kcalloc(&pdev->dev, 6410 MVPP2_N_ETHTOOL_STATS(ntxqs, nrxqs), 6411 sizeof(u64), GFP_KERNEL); 6412 if (!port->ethtool_stats) { 6413 err = -ENOMEM; 6414 goto err_free_stats; 6415 } 6416 6417 mutex_init(&port->gather_stats_lock); 6418 INIT_DELAYED_WORK(&port->stats_work, mvpp2_gather_hw_statistics); 6419 6420 mvpp2_port_copy_mac_addr(dev, priv, port_fwnode, &mac_from); 6421 6422 port->tx_ring_size = MVPP2_MAX_TXD_DFLT; 6423 port->rx_ring_size = MVPP2_MAX_RXD_DFLT; 6424 SET_NETDEV_DEV(dev, &pdev->dev); 6425 6426 err = mvpp2_port_init(port); 6427 if (err < 0) { 6428 dev_err(&pdev->dev, "failed to init port %d\n", id); 6429 goto err_free_stats; 6430 } 6431 6432 mvpp2_port_periodic_xon_disable(port); 6433 6434 mvpp2_mac_reset_assert(port); 6435 mvpp22_pcs_reset_assert(port); 6436 6437 port->pcpu = alloc_percpu(struct mvpp2_port_pcpu); 6438 if (!port->pcpu) { 6439 err = -ENOMEM; 6440 goto err_free_txq_pcpu; 6441 } 6442 6443 if (!port->has_tx_irqs) { 6444 for (thread = 0; thread < priv->nthreads; thread++) { 6445 port_pcpu = per_cpu_ptr(port->pcpu, thread); 6446 6447 hrtimer_init(&port_pcpu->tx_done_timer, CLOCK_MONOTONIC, 6448 HRTIMER_MODE_REL_PINNED_SOFT); 6449 port_pcpu->tx_done_timer.function = mvpp2_hr_timer_cb; 6450 port_pcpu->timer_scheduled = false; 6451 port_pcpu->dev = dev; 6452 } 6453 } 6454 6455 features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | 6456 NETIF_F_TSO; 6457 dev->features = features | NETIF_F_RXCSUM; 6458 dev->hw_features |= features | NETIF_F_RXCSUM | NETIF_F_GRO | 6459 NETIF_F_HW_VLAN_CTAG_FILTER; 6460 6461 if (mvpp22_rss_is_supported()) { 6462 dev->hw_features |= NETIF_F_RXHASH; 6463 dev->features |= NETIF_F_NTUPLE; 6464 } 6465 6466 if (!port->priv->percpu_pools) 6467 mvpp2_set_hw_csum(port, port->pool_long->id); 6468 6469 dev->vlan_features |= features; 6470 dev->gso_max_segs = MVPP2_MAX_TSO_SEGS; 6471 dev->priv_flags |= IFF_UNICAST_FLT; 6472 6473 /* MTU range: 68 - 9704 */ 6474 dev->min_mtu = ETH_MIN_MTU; 6475 /* 9704 == 9728 - 20 and rounding to 8 */ 6476 dev->max_mtu = MVPP2_BM_JUMBO_PKT_SIZE; 6477 dev->dev.of_node = port_node; 6478 6479 /* Phylink isn't used w/ ACPI as of now */ 6480 if (port_node) { 6481 port->phylink_config.dev = &dev->dev; 6482 port->phylink_config.type = PHYLINK_NETDEV; 6483 6484 phylink = phylink_create(&port->phylink_config, port_fwnode, 6485 phy_mode, &mvpp2_phylink_ops); 6486 if (IS_ERR(phylink)) { 6487 err = PTR_ERR(phylink); 6488 goto err_free_port_pcpu; 6489 } 6490 port->phylink = phylink; 6491 } else { 6492 port->phylink = NULL; 6493 } 6494 6495 /* Cycle the comphy to power it down, saving 270mW per port - 6496 * don't worry about an error powering it up. When the comphy 6497 * driver does this, we can remove this code. 6498 */ 6499 if (port->comphy) { 6500 err = mvpp22_comphy_init(port); 6501 if (err == 0) 6502 phy_power_off(port->comphy); 6503 } 6504 6505 err = register_netdev(dev); 6506 if (err < 0) { 6507 dev_err(&pdev->dev, "failed to register netdev\n"); 6508 goto err_phylink; 6509 } 6510 netdev_info(dev, "Using %s mac address %pM\n", mac_from, dev->dev_addr); 6511 6512 priv->port_list[priv->port_count++] = port; 6513 6514 return 0; 6515 6516 err_phylink: 6517 if (port->phylink) 6518 phylink_destroy(port->phylink); 6519 err_free_port_pcpu: 6520 free_percpu(port->pcpu); 6521 err_free_txq_pcpu: 6522 for (i = 0; i < port->ntxqs; i++) 6523 free_percpu(port->txqs[i]->pcpu); 6524 err_free_stats: 6525 free_percpu(port->stats); 6526 err_free_irq: 6527 if (port->port_irq) 6528 irq_dispose_mapping(port->port_irq); 6529 err_deinit_qvecs: 6530 mvpp2_queue_vectors_deinit(port); 6531 err_free_netdev: 6532 free_netdev(dev); 6533 return err; 6534 } 6535 6536 /* Ports removal routine */ 6537 static void mvpp2_port_remove(struct mvpp2_port *port) 6538 { 6539 int i; 6540 6541 unregister_netdev(port->dev); 6542 if (port->phylink) 6543 phylink_destroy(port->phylink); 6544 free_percpu(port->pcpu); 6545 free_percpu(port->stats); 6546 for (i = 0; i < port->ntxqs; i++) 6547 free_percpu(port->txqs[i]->pcpu); 6548 mvpp2_queue_vectors_deinit(port); 6549 if (port->port_irq) 6550 irq_dispose_mapping(port->port_irq); 6551 free_netdev(port->dev); 6552 } 6553 6554 /* Initialize decoding windows */ 6555 static void mvpp2_conf_mbus_windows(const struct mbus_dram_target_info *dram, 6556 struct mvpp2 *priv) 6557 { 6558 u32 win_enable; 6559 int i; 6560 6561 for (i = 0; i < 6; i++) { 6562 mvpp2_write(priv, MVPP2_WIN_BASE(i), 0); 6563 mvpp2_write(priv, MVPP2_WIN_SIZE(i), 0); 6564 6565 if (i < 4) 6566 mvpp2_write(priv, MVPP2_WIN_REMAP(i), 0); 6567 } 6568 6569 win_enable = 0; 6570 6571 for (i = 0; i < dram->num_cs; i++) { 6572 const struct mbus_dram_window *cs = dram->cs + i; 6573 6574 mvpp2_write(priv, MVPP2_WIN_BASE(i), 6575 (cs->base & 0xffff0000) | (cs->mbus_attr << 8) | 6576 dram->mbus_dram_target_id); 6577 6578 mvpp2_write(priv, MVPP2_WIN_SIZE(i), 6579 (cs->size - 1) & 0xffff0000); 6580 6581 win_enable |= (1 << i); 6582 } 6583 6584 mvpp2_write(priv, MVPP2_BASE_ADDR_ENABLE, win_enable); 6585 } 6586 6587 /* Initialize Rx FIFO's */ 6588 static void mvpp2_rx_fifo_init(struct mvpp2 *priv) 6589 { 6590 int port; 6591 6592 for (port = 0; port < MVPP2_MAX_PORTS; port++) { 6593 mvpp2_write(priv, MVPP2_RX_DATA_FIFO_SIZE_REG(port), 6594 MVPP2_RX_FIFO_PORT_DATA_SIZE_4KB); 6595 mvpp2_write(priv, MVPP2_RX_ATTR_FIFO_SIZE_REG(port), 6596 MVPP2_RX_FIFO_PORT_ATTR_SIZE_4KB); 6597 } 6598 6599 mvpp2_write(priv, MVPP2_RX_MIN_PKT_SIZE_REG, 6600 MVPP2_RX_FIFO_PORT_MIN_PKT); 6601 mvpp2_write(priv, MVPP2_RX_FIFO_INIT_REG, 0x1); 6602 } 6603 6604 static void mvpp22_rx_fifo_init(struct mvpp2 *priv) 6605 { 6606 int port; 6607 6608 /* The FIFO size parameters are set depending on the maximum speed a 6609 * given port can handle: 6610 * - Port 0: 10Gbps 6611 * - Port 1: 2.5Gbps 6612 * - Ports 2 and 3: 1Gbps 6613 */ 6614 6615 mvpp2_write(priv, MVPP2_RX_DATA_FIFO_SIZE_REG(0), 6616 MVPP2_RX_FIFO_PORT_DATA_SIZE_32KB); 6617 mvpp2_write(priv, MVPP2_RX_ATTR_FIFO_SIZE_REG(0), 6618 MVPP2_RX_FIFO_PORT_ATTR_SIZE_32KB); 6619 6620 mvpp2_write(priv, MVPP2_RX_DATA_FIFO_SIZE_REG(1), 6621 MVPP2_RX_FIFO_PORT_DATA_SIZE_8KB); 6622 mvpp2_write(priv, MVPP2_RX_ATTR_FIFO_SIZE_REG(1), 6623 MVPP2_RX_FIFO_PORT_ATTR_SIZE_8KB); 6624 6625 for (port = 2; port < MVPP2_MAX_PORTS; port++) { 6626 mvpp2_write(priv, MVPP2_RX_DATA_FIFO_SIZE_REG(port), 6627 MVPP2_RX_FIFO_PORT_DATA_SIZE_4KB); 6628 mvpp2_write(priv, MVPP2_RX_ATTR_FIFO_SIZE_REG(port), 6629 MVPP2_RX_FIFO_PORT_ATTR_SIZE_4KB); 6630 } 6631 6632 mvpp2_write(priv, MVPP2_RX_MIN_PKT_SIZE_REG, 6633 MVPP2_RX_FIFO_PORT_MIN_PKT); 6634 mvpp2_write(priv, MVPP2_RX_FIFO_INIT_REG, 0x1); 6635 } 6636 6637 /* Initialize Tx FIFO's: the total FIFO size is 19kB on PPv2.2 and 10G 6638 * interfaces must have a Tx FIFO size of 10kB. As only port 0 can do 10G, 6639 * configure its Tx FIFO size to 10kB and the others ports Tx FIFO size to 3kB. 6640 */ 6641 static void mvpp22_tx_fifo_init(struct mvpp2 *priv) 6642 { 6643 int port, size, thrs; 6644 6645 for (port = 0; port < MVPP2_MAX_PORTS; port++) { 6646 if (port == 0) { 6647 size = MVPP22_TX_FIFO_DATA_SIZE_10KB; 6648 thrs = MVPP2_TX_FIFO_THRESHOLD_10KB; 6649 } else { 6650 size = MVPP22_TX_FIFO_DATA_SIZE_3KB; 6651 thrs = MVPP2_TX_FIFO_THRESHOLD_3KB; 6652 } 6653 mvpp2_write(priv, MVPP22_TX_FIFO_SIZE_REG(port), size); 6654 mvpp2_write(priv, MVPP22_TX_FIFO_THRESH_REG(port), thrs); 6655 } 6656 } 6657 6658 static void mvpp2_axi_init(struct mvpp2 *priv) 6659 { 6660 u32 val, rdval, wrval; 6661 6662 mvpp2_write(priv, MVPP22_BM_ADDR_HIGH_RLS_REG, 0x0); 6663 6664 /* AXI Bridge Configuration */ 6665 6666 rdval = MVPP22_AXI_CODE_CACHE_RD_CACHE 6667 << MVPP22_AXI_ATTR_CACHE_OFFS; 6668 rdval |= MVPP22_AXI_CODE_DOMAIN_OUTER_DOM 6669 << MVPP22_AXI_ATTR_DOMAIN_OFFS; 6670 6671 wrval = MVPP22_AXI_CODE_CACHE_WR_CACHE 6672 << MVPP22_AXI_ATTR_CACHE_OFFS; 6673 wrval |= MVPP22_AXI_CODE_DOMAIN_OUTER_DOM 6674 << MVPP22_AXI_ATTR_DOMAIN_OFFS; 6675 6676 /* BM */ 6677 mvpp2_write(priv, MVPP22_AXI_BM_WR_ATTR_REG, wrval); 6678 mvpp2_write(priv, MVPP22_AXI_BM_RD_ATTR_REG, rdval); 6679 6680 /* Descriptors */ 6681 mvpp2_write(priv, MVPP22_AXI_AGGRQ_DESCR_RD_ATTR_REG, rdval); 6682 mvpp2_write(priv, MVPP22_AXI_TXQ_DESCR_WR_ATTR_REG, wrval); 6683 mvpp2_write(priv, MVPP22_AXI_TXQ_DESCR_RD_ATTR_REG, rdval); 6684 mvpp2_write(priv, MVPP22_AXI_RXQ_DESCR_WR_ATTR_REG, wrval); 6685 6686 /* Buffer Data */ 6687 mvpp2_write(priv, MVPP22_AXI_TX_DATA_RD_ATTR_REG, rdval); 6688 mvpp2_write(priv, MVPP22_AXI_RX_DATA_WR_ATTR_REG, wrval); 6689 6690 val = MVPP22_AXI_CODE_CACHE_NON_CACHE 6691 << MVPP22_AXI_CODE_CACHE_OFFS; 6692 val |= MVPP22_AXI_CODE_DOMAIN_SYSTEM 6693 << MVPP22_AXI_CODE_DOMAIN_OFFS; 6694 mvpp2_write(priv, MVPP22_AXI_RD_NORMAL_CODE_REG, val); 6695 mvpp2_write(priv, MVPP22_AXI_WR_NORMAL_CODE_REG, val); 6696 6697 val = MVPP22_AXI_CODE_CACHE_RD_CACHE 6698 << MVPP22_AXI_CODE_CACHE_OFFS; 6699 val |= MVPP22_AXI_CODE_DOMAIN_OUTER_DOM 6700 << MVPP22_AXI_CODE_DOMAIN_OFFS; 6701 6702 mvpp2_write(priv, MVPP22_AXI_RD_SNOOP_CODE_REG, val); 6703 6704 val = MVPP22_AXI_CODE_CACHE_WR_CACHE 6705 << MVPP22_AXI_CODE_CACHE_OFFS; 6706 val |= MVPP22_AXI_CODE_DOMAIN_OUTER_DOM 6707 << MVPP22_AXI_CODE_DOMAIN_OFFS; 6708 6709 mvpp2_write(priv, MVPP22_AXI_WR_SNOOP_CODE_REG, val); 6710 } 6711 6712 /* Initialize network controller common part HW */ 6713 static int mvpp2_init(struct platform_device *pdev, struct mvpp2 *priv) 6714 { 6715 const struct mbus_dram_target_info *dram_target_info; 6716 int err, i; 6717 u32 val; 6718 6719 /* MBUS windows configuration */ 6720 dram_target_info = mv_mbus_dram_info(); 6721 if (dram_target_info) 6722 mvpp2_conf_mbus_windows(dram_target_info, priv); 6723 6724 if (priv->hw_version == MVPP22) 6725 mvpp2_axi_init(priv); 6726 6727 /* Disable HW PHY polling */ 6728 if (priv->hw_version == MVPP21) { 6729 val = readl(priv->lms_base + MVPP2_PHY_AN_CFG0_REG); 6730 val |= MVPP2_PHY_AN_STOP_SMI0_MASK; 6731 writel(val, priv->lms_base + MVPP2_PHY_AN_CFG0_REG); 6732 } else { 6733 val = readl(priv->iface_base + MVPP22_SMI_MISC_CFG_REG); 6734 val &= ~MVPP22_SMI_POLLING_EN; 6735 writel(val, priv->iface_base + MVPP22_SMI_MISC_CFG_REG); 6736 } 6737 6738 /* Allocate and initialize aggregated TXQs */ 6739 priv->aggr_txqs = devm_kcalloc(&pdev->dev, MVPP2_MAX_THREADS, 6740 sizeof(*priv->aggr_txqs), 6741 GFP_KERNEL); 6742 if (!priv->aggr_txqs) 6743 return -ENOMEM; 6744 6745 for (i = 0; i < MVPP2_MAX_THREADS; i++) { 6746 priv->aggr_txqs[i].id = i; 6747 priv->aggr_txqs[i].size = MVPP2_AGGR_TXQ_SIZE; 6748 err = mvpp2_aggr_txq_init(pdev, &priv->aggr_txqs[i], i, priv); 6749 if (err < 0) 6750 return err; 6751 } 6752 6753 /* Fifo Init */ 6754 if (priv->hw_version == MVPP21) { 6755 mvpp2_rx_fifo_init(priv); 6756 } else { 6757 mvpp22_rx_fifo_init(priv); 6758 mvpp22_tx_fifo_init(priv); 6759 } 6760 6761 if (priv->hw_version == MVPP21) 6762 writel(MVPP2_EXT_GLOBAL_CTRL_DEFAULT, 6763 priv->lms_base + MVPP2_MNG_EXTENDED_GLOBAL_CTRL_REG); 6764 6765 /* Allow cache snoop when transmiting packets */ 6766 mvpp2_write(priv, MVPP2_TX_SNOOP_REG, 0x1); 6767 6768 /* Buffer Manager initialization */ 6769 err = mvpp2_bm_init(&pdev->dev, priv); 6770 if (err < 0) 6771 return err; 6772 6773 /* Parser default initialization */ 6774 err = mvpp2_prs_default_init(pdev, priv); 6775 if (err < 0) 6776 return err; 6777 6778 /* Classifier default initialization */ 6779 mvpp2_cls_init(priv); 6780 6781 return 0; 6782 } 6783 6784 static int mvpp2_probe(struct platform_device *pdev) 6785 { 6786 const struct acpi_device_id *acpi_id; 6787 struct fwnode_handle *fwnode = pdev->dev.fwnode; 6788 struct fwnode_handle *port_fwnode; 6789 struct mvpp2 *priv; 6790 struct resource *res; 6791 void __iomem *base; 6792 int i, shared; 6793 int err; 6794 6795 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); 6796 if (!priv) 6797 return -ENOMEM; 6798 6799 if (has_acpi_companion(&pdev->dev)) { 6800 acpi_id = acpi_match_device(pdev->dev.driver->acpi_match_table, 6801 &pdev->dev); 6802 if (!acpi_id) 6803 return -EINVAL; 6804 priv->hw_version = (unsigned long)acpi_id->driver_data; 6805 } else { 6806 priv->hw_version = 6807 (unsigned long)of_device_get_match_data(&pdev->dev); 6808 } 6809 6810 /* multi queue mode isn't supported on PPV2.1, fallback to single 6811 * mode 6812 */ 6813 if (priv->hw_version == MVPP21) 6814 queue_mode = MVPP2_QDIST_SINGLE_MODE; 6815 6816 base = devm_platform_ioremap_resource(pdev, 0); 6817 if (IS_ERR(base)) 6818 return PTR_ERR(base); 6819 6820 if (priv->hw_version == MVPP21) { 6821 priv->lms_base = devm_platform_ioremap_resource(pdev, 1); 6822 if (IS_ERR(priv->lms_base)) 6823 return PTR_ERR(priv->lms_base); 6824 } else { 6825 res = platform_get_resource(pdev, IORESOURCE_MEM, 1); 6826 if (has_acpi_companion(&pdev->dev)) { 6827 /* In case the MDIO memory region is declared in 6828 * the ACPI, it can already appear as 'in-use' 6829 * in the OS. Because it is overlapped by second 6830 * region of the network controller, make 6831 * sure it is released, before requesting it again. 6832 * The care is taken by mvpp2 driver to avoid 6833 * concurrent access to this memory region. 6834 */ 6835 release_resource(res); 6836 } 6837 priv->iface_base = devm_ioremap_resource(&pdev->dev, res); 6838 if (IS_ERR(priv->iface_base)) 6839 return PTR_ERR(priv->iface_base); 6840 } 6841 6842 if (priv->hw_version == MVPP22 && dev_of_node(&pdev->dev)) { 6843 priv->sysctrl_base = 6844 syscon_regmap_lookup_by_phandle(pdev->dev.of_node, 6845 "marvell,system-controller"); 6846 if (IS_ERR(priv->sysctrl_base)) 6847 /* The system controller regmap is optional for dt 6848 * compatibility reasons. When not provided, the 6849 * configuration of the GoP relies on the 6850 * firmware/bootloader. 6851 */ 6852 priv->sysctrl_base = NULL; 6853 } 6854 6855 if (priv->hw_version == MVPP22 && 6856 mvpp2_get_nrxqs(priv) * 2 <= MVPP2_BM_MAX_POOLS) 6857 priv->percpu_pools = 1; 6858 6859 mvpp2_setup_bm_pool(); 6860 6861 6862 priv->nthreads = min_t(unsigned int, num_present_cpus(), 6863 MVPP2_MAX_THREADS); 6864 6865 shared = num_present_cpus() - priv->nthreads; 6866 if (shared > 0) 6867 bitmap_fill(&priv->lock_map, 6868 min_t(int, shared, MVPP2_MAX_THREADS)); 6869 6870 for (i = 0; i < MVPP2_MAX_THREADS; i++) { 6871 u32 addr_space_sz; 6872 6873 addr_space_sz = (priv->hw_version == MVPP21 ? 6874 MVPP21_ADDR_SPACE_SZ : MVPP22_ADDR_SPACE_SZ); 6875 priv->swth_base[i] = base + i * addr_space_sz; 6876 } 6877 6878 if (priv->hw_version == MVPP21) 6879 priv->max_port_rxqs = 8; 6880 else 6881 priv->max_port_rxqs = 32; 6882 6883 if (dev_of_node(&pdev->dev)) { 6884 priv->pp_clk = devm_clk_get(&pdev->dev, "pp_clk"); 6885 if (IS_ERR(priv->pp_clk)) 6886 return PTR_ERR(priv->pp_clk); 6887 err = clk_prepare_enable(priv->pp_clk); 6888 if (err < 0) 6889 return err; 6890 6891 priv->gop_clk = devm_clk_get(&pdev->dev, "gop_clk"); 6892 if (IS_ERR(priv->gop_clk)) { 6893 err = PTR_ERR(priv->gop_clk); 6894 goto err_pp_clk; 6895 } 6896 err = clk_prepare_enable(priv->gop_clk); 6897 if (err < 0) 6898 goto err_pp_clk; 6899 6900 if (priv->hw_version == MVPP22) { 6901 priv->mg_clk = devm_clk_get(&pdev->dev, "mg_clk"); 6902 if (IS_ERR(priv->mg_clk)) { 6903 err = PTR_ERR(priv->mg_clk); 6904 goto err_gop_clk; 6905 } 6906 6907 err = clk_prepare_enable(priv->mg_clk); 6908 if (err < 0) 6909 goto err_gop_clk; 6910 6911 priv->mg_core_clk = devm_clk_get(&pdev->dev, "mg_core_clk"); 6912 if (IS_ERR(priv->mg_core_clk)) { 6913 priv->mg_core_clk = NULL; 6914 } else { 6915 err = clk_prepare_enable(priv->mg_core_clk); 6916 if (err < 0) 6917 goto err_mg_clk; 6918 } 6919 } 6920 6921 priv->axi_clk = devm_clk_get(&pdev->dev, "axi_clk"); 6922 if (IS_ERR(priv->axi_clk)) { 6923 err = PTR_ERR(priv->axi_clk); 6924 if (err == -EPROBE_DEFER) 6925 goto err_mg_core_clk; 6926 priv->axi_clk = NULL; 6927 } else { 6928 err = clk_prepare_enable(priv->axi_clk); 6929 if (err < 0) 6930 goto err_mg_core_clk; 6931 } 6932 6933 /* Get system's tclk rate */ 6934 priv->tclk = clk_get_rate(priv->pp_clk); 6935 } else if (device_property_read_u32(&pdev->dev, "clock-frequency", 6936 &priv->tclk)) { 6937 dev_err(&pdev->dev, "missing clock-frequency value\n"); 6938 return -EINVAL; 6939 } 6940 6941 if (priv->hw_version == MVPP22) { 6942 err = dma_set_mask(&pdev->dev, MVPP2_DESC_DMA_MASK); 6943 if (err) 6944 goto err_axi_clk; 6945 /* Sadly, the BM pools all share the same register to 6946 * store the high 32 bits of their address. So they 6947 * must all have the same high 32 bits, which forces 6948 * us to restrict coherent memory to DMA_BIT_MASK(32). 6949 */ 6950 err = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32)); 6951 if (err) 6952 goto err_axi_clk; 6953 } 6954 6955 /* Initialize network controller */ 6956 err = mvpp2_init(pdev, priv); 6957 if (err < 0) { 6958 dev_err(&pdev->dev, "failed to initialize controller\n"); 6959 goto err_axi_clk; 6960 } 6961 6962 err = mvpp22_tai_probe(&pdev->dev, priv); 6963 if (err < 0) 6964 goto err_axi_clk; 6965 6966 /* Initialize ports */ 6967 fwnode_for_each_available_child_node(fwnode, port_fwnode) { 6968 err = mvpp2_port_probe(pdev, port_fwnode, priv); 6969 if (err < 0) 6970 goto err_port_probe; 6971 } 6972 6973 if (priv->port_count == 0) { 6974 dev_err(&pdev->dev, "no ports enabled\n"); 6975 err = -ENODEV; 6976 goto err_axi_clk; 6977 } 6978 6979 /* Statistics must be gathered regularly because some of them (like 6980 * packets counters) are 32-bit registers and could overflow quite 6981 * quickly. For instance, a 10Gb link used at full bandwidth with the 6982 * smallest packets (64B) will overflow a 32-bit counter in less than 6983 * 30 seconds. Then, use a workqueue to fill 64-bit counters. 6984 */ 6985 snprintf(priv->queue_name, sizeof(priv->queue_name), 6986 "stats-wq-%s%s", netdev_name(priv->port_list[0]->dev), 6987 priv->port_count > 1 ? "+" : ""); 6988 priv->stats_queue = create_singlethread_workqueue(priv->queue_name); 6989 if (!priv->stats_queue) { 6990 err = -ENOMEM; 6991 goto err_port_probe; 6992 } 6993 6994 mvpp2_dbgfs_init(priv, pdev->name); 6995 6996 platform_set_drvdata(pdev, priv); 6997 return 0; 6998 6999 err_port_probe: 7000 i = 0; 7001 fwnode_for_each_available_child_node(fwnode, port_fwnode) { 7002 if (priv->port_list[i]) 7003 mvpp2_port_remove(priv->port_list[i]); 7004 i++; 7005 } 7006 err_axi_clk: 7007 clk_disable_unprepare(priv->axi_clk); 7008 7009 err_mg_core_clk: 7010 if (priv->hw_version == MVPP22) 7011 clk_disable_unprepare(priv->mg_core_clk); 7012 err_mg_clk: 7013 if (priv->hw_version == MVPP22) 7014 clk_disable_unprepare(priv->mg_clk); 7015 err_gop_clk: 7016 clk_disable_unprepare(priv->gop_clk); 7017 err_pp_clk: 7018 clk_disable_unprepare(priv->pp_clk); 7019 return err; 7020 } 7021 7022 static int mvpp2_remove(struct platform_device *pdev) 7023 { 7024 struct mvpp2 *priv = platform_get_drvdata(pdev); 7025 struct fwnode_handle *fwnode = pdev->dev.fwnode; 7026 int i = 0, poolnum = MVPP2_BM_POOLS_NUM; 7027 struct fwnode_handle *port_fwnode; 7028 7029 mvpp2_dbgfs_cleanup(priv); 7030 7031 fwnode_for_each_available_child_node(fwnode, port_fwnode) { 7032 if (priv->port_list[i]) { 7033 mutex_destroy(&priv->port_list[i]->gather_stats_lock); 7034 mvpp2_port_remove(priv->port_list[i]); 7035 } 7036 i++; 7037 } 7038 7039 destroy_workqueue(priv->stats_queue); 7040 7041 if (priv->percpu_pools) 7042 poolnum = mvpp2_get_nrxqs(priv) * 2; 7043 7044 for (i = 0; i < poolnum; i++) { 7045 struct mvpp2_bm_pool *bm_pool = &priv->bm_pools[i]; 7046 7047 mvpp2_bm_pool_destroy(&pdev->dev, priv, bm_pool); 7048 } 7049 7050 for (i = 0; i < MVPP2_MAX_THREADS; i++) { 7051 struct mvpp2_tx_queue *aggr_txq = &priv->aggr_txqs[i]; 7052 7053 dma_free_coherent(&pdev->dev, 7054 MVPP2_AGGR_TXQ_SIZE * MVPP2_DESC_ALIGNED_SIZE, 7055 aggr_txq->descs, 7056 aggr_txq->descs_dma); 7057 } 7058 7059 if (is_acpi_node(port_fwnode)) 7060 return 0; 7061 7062 clk_disable_unprepare(priv->axi_clk); 7063 clk_disable_unprepare(priv->mg_core_clk); 7064 clk_disable_unprepare(priv->mg_clk); 7065 clk_disable_unprepare(priv->pp_clk); 7066 clk_disable_unprepare(priv->gop_clk); 7067 7068 return 0; 7069 } 7070 7071 static const struct of_device_id mvpp2_match[] = { 7072 { 7073 .compatible = "marvell,armada-375-pp2", 7074 .data = (void *)MVPP21, 7075 }, 7076 { 7077 .compatible = "marvell,armada-7k-pp22", 7078 .data = (void *)MVPP22, 7079 }, 7080 { } 7081 }; 7082 MODULE_DEVICE_TABLE(of, mvpp2_match); 7083 7084 #ifdef CONFIG_ACPI 7085 static const struct acpi_device_id mvpp2_acpi_match[] = { 7086 { "MRVL0110", MVPP22 }, 7087 { }, 7088 }; 7089 MODULE_DEVICE_TABLE(acpi, mvpp2_acpi_match); 7090 #endif 7091 7092 static struct platform_driver mvpp2_driver = { 7093 .probe = mvpp2_probe, 7094 .remove = mvpp2_remove, 7095 .driver = { 7096 .name = MVPP2_DRIVER_NAME, 7097 .of_match_table = mvpp2_match, 7098 .acpi_match_table = ACPI_PTR(mvpp2_acpi_match), 7099 }, 7100 }; 7101 7102 module_platform_driver(mvpp2_driver); 7103 7104 MODULE_DESCRIPTION("Marvell PPv2 Ethernet Driver - www.marvell.com"); 7105 MODULE_AUTHOR("Marcin Wojtas <mw@semihalf.com>"); 7106 MODULE_LICENSE("GPL v2"); 7107