1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Driver for Marvell PPv2 network controller for Armada 375 SoC. 4 * 5 * Copyright (C) 2014 Marvell 6 * 7 * Marcin Wojtas <mw@semihalf.com> 8 */ 9 10 #include <linux/acpi.h> 11 #include <linux/kernel.h> 12 #include <linux/netdevice.h> 13 #include <linux/etherdevice.h> 14 #include <linux/platform_device.h> 15 #include <linux/skbuff.h> 16 #include <linux/inetdevice.h> 17 #include <linux/mbus.h> 18 #include <linux/module.h> 19 #include <linux/mfd/syscon.h> 20 #include <linux/interrupt.h> 21 #include <linux/cpumask.h> 22 #include <linux/of.h> 23 #include <linux/of_irq.h> 24 #include <linux/of_mdio.h> 25 #include <linux/of_net.h> 26 #include <linux/of_address.h> 27 #include <linux/of_device.h> 28 #include <linux/phy.h> 29 #include <linux/phylink.h> 30 #include <linux/phy/phy.h> 31 #include <linux/clk.h> 32 #include <linux/hrtimer.h> 33 #include <linux/ktime.h> 34 #include <linux/regmap.h> 35 #include <uapi/linux/ppp_defs.h> 36 #include <net/ip.h> 37 #include <net/ipv6.h> 38 #include <net/tso.h> 39 40 #include "mvpp2.h" 41 #include "mvpp2_prs.h" 42 #include "mvpp2_cls.h" 43 44 enum mvpp2_bm_pool_log_num { 45 MVPP2_BM_SHORT, 46 MVPP2_BM_LONG, 47 MVPP2_BM_JUMBO, 48 MVPP2_BM_POOLS_NUM 49 }; 50 51 static struct { 52 int pkt_size; 53 int buf_num; 54 } mvpp2_pools[MVPP2_BM_POOLS_NUM]; 55 56 /* The prototype is added here to be used in start_dev when using ACPI. This 57 * will be removed once phylink is used for all modes (dt+ACPI). 58 */ 59 static void mvpp2_mac_config(struct phylink_config *config, unsigned int mode, 60 const struct phylink_link_state *state); 61 static void mvpp2_mac_link_up(struct phylink_config *config, unsigned int mode, 62 phy_interface_t interface, struct phy_device *phy); 63 64 /* Queue modes */ 65 #define MVPP2_QDIST_SINGLE_MODE 0 66 #define MVPP2_QDIST_MULTI_MODE 1 67 68 static int queue_mode = MVPP2_QDIST_MULTI_MODE; 69 70 module_param(queue_mode, int, 0444); 71 MODULE_PARM_DESC(queue_mode, "Set queue_mode (single=0, multi=1)"); 72 73 /* Utility/helper methods */ 74 75 void mvpp2_write(struct mvpp2 *priv, u32 offset, u32 data) 76 { 77 writel(data, priv->swth_base[0] + offset); 78 } 79 80 u32 mvpp2_read(struct mvpp2 *priv, u32 offset) 81 { 82 return readl(priv->swth_base[0] + offset); 83 } 84 85 static u32 mvpp2_read_relaxed(struct mvpp2 *priv, u32 offset) 86 { 87 return readl_relaxed(priv->swth_base[0] + offset); 88 } 89 90 static inline u32 mvpp2_cpu_to_thread(struct mvpp2 *priv, int cpu) 91 { 92 return cpu % priv->nthreads; 93 } 94 95 /* These accessors should be used to access: 96 * 97 * - per-thread registers, where each thread has its own copy of the 98 * register. 99 * 100 * MVPP2_BM_VIRT_ALLOC_REG 101 * MVPP2_BM_ADDR_HIGH_ALLOC 102 * MVPP22_BM_ADDR_HIGH_RLS_REG 103 * MVPP2_BM_VIRT_RLS_REG 104 * MVPP2_ISR_RX_TX_CAUSE_REG 105 * MVPP2_ISR_RX_TX_MASK_REG 106 * MVPP2_TXQ_NUM_REG 107 * MVPP2_AGGR_TXQ_UPDATE_REG 108 * MVPP2_TXQ_RSVD_REQ_REG 109 * MVPP2_TXQ_RSVD_RSLT_REG 110 * MVPP2_TXQ_SENT_REG 111 * MVPP2_RXQ_NUM_REG 112 * 113 * - global registers that must be accessed through a specific thread 114 * window, because they are related to an access to a per-thread 115 * register 116 * 117 * MVPP2_BM_PHY_ALLOC_REG (related to MVPP2_BM_VIRT_ALLOC_REG) 118 * MVPP2_BM_PHY_RLS_REG (related to MVPP2_BM_VIRT_RLS_REG) 119 * MVPP2_RXQ_THRESH_REG (related to MVPP2_RXQ_NUM_REG) 120 * MVPP2_RXQ_DESC_ADDR_REG (related to MVPP2_RXQ_NUM_REG) 121 * MVPP2_RXQ_DESC_SIZE_REG (related to MVPP2_RXQ_NUM_REG) 122 * MVPP2_RXQ_INDEX_REG (related to MVPP2_RXQ_NUM_REG) 123 * MVPP2_TXQ_PENDING_REG (related to MVPP2_TXQ_NUM_REG) 124 * MVPP2_TXQ_DESC_ADDR_REG (related to MVPP2_TXQ_NUM_REG) 125 * MVPP2_TXQ_DESC_SIZE_REG (related to MVPP2_TXQ_NUM_REG) 126 * MVPP2_TXQ_INDEX_REG (related to MVPP2_TXQ_NUM_REG) 127 * MVPP2_TXQ_PENDING_REG (related to MVPP2_TXQ_NUM_REG) 128 * MVPP2_TXQ_PREF_BUF_REG (related to MVPP2_TXQ_NUM_REG) 129 * MVPP2_TXQ_PREF_BUF_REG (related to MVPP2_TXQ_NUM_REG) 130 */ 131 static void mvpp2_thread_write(struct mvpp2 *priv, unsigned int thread, 132 u32 offset, u32 data) 133 { 134 writel(data, priv->swth_base[thread] + offset); 135 } 136 137 static u32 mvpp2_thread_read(struct mvpp2 *priv, unsigned int thread, 138 u32 offset) 139 { 140 return readl(priv->swth_base[thread] + offset); 141 } 142 143 static void mvpp2_thread_write_relaxed(struct mvpp2 *priv, unsigned int thread, 144 u32 offset, u32 data) 145 { 146 writel_relaxed(data, priv->swth_base[thread] + offset); 147 } 148 149 static u32 mvpp2_thread_read_relaxed(struct mvpp2 *priv, unsigned int thread, 150 u32 offset) 151 { 152 return readl_relaxed(priv->swth_base[thread] + offset); 153 } 154 155 static dma_addr_t mvpp2_txdesc_dma_addr_get(struct mvpp2_port *port, 156 struct mvpp2_tx_desc *tx_desc) 157 { 158 if (port->priv->hw_version == MVPP21) 159 return le32_to_cpu(tx_desc->pp21.buf_dma_addr); 160 else 161 return le64_to_cpu(tx_desc->pp22.buf_dma_addr_ptp) & 162 MVPP2_DESC_DMA_MASK; 163 } 164 165 static void mvpp2_txdesc_dma_addr_set(struct mvpp2_port *port, 166 struct mvpp2_tx_desc *tx_desc, 167 dma_addr_t dma_addr) 168 { 169 dma_addr_t addr, offset; 170 171 addr = dma_addr & ~MVPP2_TX_DESC_ALIGN; 172 offset = dma_addr & MVPP2_TX_DESC_ALIGN; 173 174 if (port->priv->hw_version == MVPP21) { 175 tx_desc->pp21.buf_dma_addr = cpu_to_le32(addr); 176 tx_desc->pp21.packet_offset = offset; 177 } else { 178 __le64 val = cpu_to_le64(addr); 179 180 tx_desc->pp22.buf_dma_addr_ptp &= ~cpu_to_le64(MVPP2_DESC_DMA_MASK); 181 tx_desc->pp22.buf_dma_addr_ptp |= val; 182 tx_desc->pp22.packet_offset = offset; 183 } 184 } 185 186 static size_t mvpp2_txdesc_size_get(struct mvpp2_port *port, 187 struct mvpp2_tx_desc *tx_desc) 188 { 189 if (port->priv->hw_version == MVPP21) 190 return le16_to_cpu(tx_desc->pp21.data_size); 191 else 192 return le16_to_cpu(tx_desc->pp22.data_size); 193 } 194 195 static void mvpp2_txdesc_size_set(struct mvpp2_port *port, 196 struct mvpp2_tx_desc *tx_desc, 197 size_t size) 198 { 199 if (port->priv->hw_version == MVPP21) 200 tx_desc->pp21.data_size = cpu_to_le16(size); 201 else 202 tx_desc->pp22.data_size = cpu_to_le16(size); 203 } 204 205 static void mvpp2_txdesc_txq_set(struct mvpp2_port *port, 206 struct mvpp2_tx_desc *tx_desc, 207 unsigned int txq) 208 { 209 if (port->priv->hw_version == MVPP21) 210 tx_desc->pp21.phys_txq = txq; 211 else 212 tx_desc->pp22.phys_txq = txq; 213 } 214 215 static void mvpp2_txdesc_cmd_set(struct mvpp2_port *port, 216 struct mvpp2_tx_desc *tx_desc, 217 unsigned int command) 218 { 219 if (port->priv->hw_version == MVPP21) 220 tx_desc->pp21.command = cpu_to_le32(command); 221 else 222 tx_desc->pp22.command = cpu_to_le32(command); 223 } 224 225 static unsigned int mvpp2_txdesc_offset_get(struct mvpp2_port *port, 226 struct mvpp2_tx_desc *tx_desc) 227 { 228 if (port->priv->hw_version == MVPP21) 229 return tx_desc->pp21.packet_offset; 230 else 231 return tx_desc->pp22.packet_offset; 232 } 233 234 static dma_addr_t mvpp2_rxdesc_dma_addr_get(struct mvpp2_port *port, 235 struct mvpp2_rx_desc *rx_desc) 236 { 237 if (port->priv->hw_version == MVPP21) 238 return le32_to_cpu(rx_desc->pp21.buf_dma_addr); 239 else 240 return le64_to_cpu(rx_desc->pp22.buf_dma_addr_key_hash) & 241 MVPP2_DESC_DMA_MASK; 242 } 243 244 static unsigned long mvpp2_rxdesc_cookie_get(struct mvpp2_port *port, 245 struct mvpp2_rx_desc *rx_desc) 246 { 247 if (port->priv->hw_version == MVPP21) 248 return le32_to_cpu(rx_desc->pp21.buf_cookie); 249 else 250 return le64_to_cpu(rx_desc->pp22.buf_cookie_misc) & 251 MVPP2_DESC_DMA_MASK; 252 } 253 254 static size_t mvpp2_rxdesc_size_get(struct mvpp2_port *port, 255 struct mvpp2_rx_desc *rx_desc) 256 { 257 if (port->priv->hw_version == MVPP21) 258 return le16_to_cpu(rx_desc->pp21.data_size); 259 else 260 return le16_to_cpu(rx_desc->pp22.data_size); 261 } 262 263 static u32 mvpp2_rxdesc_status_get(struct mvpp2_port *port, 264 struct mvpp2_rx_desc *rx_desc) 265 { 266 if (port->priv->hw_version == MVPP21) 267 return le32_to_cpu(rx_desc->pp21.status); 268 else 269 return le32_to_cpu(rx_desc->pp22.status); 270 } 271 272 static void mvpp2_txq_inc_get(struct mvpp2_txq_pcpu *txq_pcpu) 273 { 274 txq_pcpu->txq_get_index++; 275 if (txq_pcpu->txq_get_index == txq_pcpu->size) 276 txq_pcpu->txq_get_index = 0; 277 } 278 279 static void mvpp2_txq_inc_put(struct mvpp2_port *port, 280 struct mvpp2_txq_pcpu *txq_pcpu, 281 struct sk_buff *skb, 282 struct mvpp2_tx_desc *tx_desc) 283 { 284 struct mvpp2_txq_pcpu_buf *tx_buf = 285 txq_pcpu->buffs + txq_pcpu->txq_put_index; 286 tx_buf->skb = skb; 287 tx_buf->size = mvpp2_txdesc_size_get(port, tx_desc); 288 tx_buf->dma = mvpp2_txdesc_dma_addr_get(port, tx_desc) + 289 mvpp2_txdesc_offset_get(port, tx_desc); 290 txq_pcpu->txq_put_index++; 291 if (txq_pcpu->txq_put_index == txq_pcpu->size) 292 txq_pcpu->txq_put_index = 0; 293 } 294 295 /* Get number of physical egress port */ 296 static inline int mvpp2_egress_port(struct mvpp2_port *port) 297 { 298 return MVPP2_MAX_TCONT + port->id; 299 } 300 301 /* Get number of physical TXQ */ 302 static inline int mvpp2_txq_phys(int port, int txq) 303 { 304 return (MVPP2_MAX_TCONT + port) * MVPP2_MAX_TXQ + txq; 305 } 306 307 static void *mvpp2_frag_alloc(const struct mvpp2_bm_pool *pool) 308 { 309 if (likely(pool->frag_size <= PAGE_SIZE)) 310 return netdev_alloc_frag(pool->frag_size); 311 else 312 return kmalloc(pool->frag_size, GFP_ATOMIC); 313 } 314 315 static void mvpp2_frag_free(const struct mvpp2_bm_pool *pool, void *data) 316 { 317 if (likely(pool->frag_size <= PAGE_SIZE)) 318 skb_free_frag(data); 319 else 320 kfree(data); 321 } 322 323 /* Buffer Manager configuration routines */ 324 325 /* Create pool */ 326 static int mvpp2_bm_pool_create(struct platform_device *pdev, 327 struct mvpp2 *priv, 328 struct mvpp2_bm_pool *bm_pool, int size) 329 { 330 u32 val; 331 332 /* Number of buffer pointers must be a multiple of 16, as per 333 * hardware constraints 334 */ 335 if (!IS_ALIGNED(size, 16)) 336 return -EINVAL; 337 338 /* PPv2.1 needs 8 bytes per buffer pointer, PPv2.2 needs 16 339 * bytes per buffer pointer 340 */ 341 if (priv->hw_version == MVPP21) 342 bm_pool->size_bytes = 2 * sizeof(u32) * size; 343 else 344 bm_pool->size_bytes = 2 * sizeof(u64) * size; 345 346 bm_pool->virt_addr = dma_alloc_coherent(&pdev->dev, bm_pool->size_bytes, 347 &bm_pool->dma_addr, 348 GFP_KERNEL); 349 if (!bm_pool->virt_addr) 350 return -ENOMEM; 351 352 if (!IS_ALIGNED((unsigned long)bm_pool->virt_addr, 353 MVPP2_BM_POOL_PTR_ALIGN)) { 354 dma_free_coherent(&pdev->dev, bm_pool->size_bytes, 355 bm_pool->virt_addr, bm_pool->dma_addr); 356 dev_err(&pdev->dev, "BM pool %d is not %d bytes aligned\n", 357 bm_pool->id, MVPP2_BM_POOL_PTR_ALIGN); 358 return -ENOMEM; 359 } 360 361 mvpp2_write(priv, MVPP2_BM_POOL_BASE_REG(bm_pool->id), 362 lower_32_bits(bm_pool->dma_addr)); 363 mvpp2_write(priv, MVPP2_BM_POOL_SIZE_REG(bm_pool->id), size); 364 365 val = mvpp2_read(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id)); 366 val |= MVPP2_BM_START_MASK; 367 mvpp2_write(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id), val); 368 369 bm_pool->size = size; 370 bm_pool->pkt_size = 0; 371 bm_pool->buf_num = 0; 372 373 return 0; 374 } 375 376 /* Set pool buffer size */ 377 static void mvpp2_bm_pool_bufsize_set(struct mvpp2 *priv, 378 struct mvpp2_bm_pool *bm_pool, 379 int buf_size) 380 { 381 u32 val; 382 383 bm_pool->buf_size = buf_size; 384 385 val = ALIGN(buf_size, 1 << MVPP2_POOL_BUF_SIZE_OFFSET); 386 mvpp2_write(priv, MVPP2_POOL_BUF_SIZE_REG(bm_pool->id), val); 387 } 388 389 static void mvpp2_bm_bufs_get_addrs(struct device *dev, struct mvpp2 *priv, 390 struct mvpp2_bm_pool *bm_pool, 391 dma_addr_t *dma_addr, 392 phys_addr_t *phys_addr) 393 { 394 unsigned int thread = mvpp2_cpu_to_thread(priv, get_cpu()); 395 396 *dma_addr = mvpp2_thread_read(priv, thread, 397 MVPP2_BM_PHY_ALLOC_REG(bm_pool->id)); 398 *phys_addr = mvpp2_thread_read(priv, thread, MVPP2_BM_VIRT_ALLOC_REG); 399 400 if (priv->hw_version == MVPP22) { 401 u32 val; 402 u32 dma_addr_highbits, phys_addr_highbits; 403 404 val = mvpp2_thread_read(priv, thread, MVPP22_BM_ADDR_HIGH_ALLOC); 405 dma_addr_highbits = (val & MVPP22_BM_ADDR_HIGH_PHYS_MASK); 406 phys_addr_highbits = (val & MVPP22_BM_ADDR_HIGH_VIRT_MASK) >> 407 MVPP22_BM_ADDR_HIGH_VIRT_SHIFT; 408 409 if (sizeof(dma_addr_t) == 8) 410 *dma_addr |= (u64)dma_addr_highbits << 32; 411 412 if (sizeof(phys_addr_t) == 8) 413 *phys_addr |= (u64)phys_addr_highbits << 32; 414 } 415 416 put_cpu(); 417 } 418 419 /* Free all buffers from the pool */ 420 static void mvpp2_bm_bufs_free(struct device *dev, struct mvpp2 *priv, 421 struct mvpp2_bm_pool *bm_pool, int buf_num) 422 { 423 int i; 424 425 if (buf_num > bm_pool->buf_num) { 426 WARN(1, "Pool does not have so many bufs pool(%d) bufs(%d)\n", 427 bm_pool->id, buf_num); 428 buf_num = bm_pool->buf_num; 429 } 430 431 for (i = 0; i < buf_num; i++) { 432 dma_addr_t buf_dma_addr; 433 phys_addr_t buf_phys_addr; 434 void *data; 435 436 mvpp2_bm_bufs_get_addrs(dev, priv, bm_pool, 437 &buf_dma_addr, &buf_phys_addr); 438 439 dma_unmap_single(dev, buf_dma_addr, 440 bm_pool->buf_size, DMA_FROM_DEVICE); 441 442 data = (void *)phys_to_virt(buf_phys_addr); 443 if (!data) 444 break; 445 446 mvpp2_frag_free(bm_pool, data); 447 } 448 449 /* Update BM driver with number of buffers removed from pool */ 450 bm_pool->buf_num -= i; 451 } 452 453 /* Check number of buffers in BM pool */ 454 static int mvpp2_check_hw_buf_num(struct mvpp2 *priv, struct mvpp2_bm_pool *bm_pool) 455 { 456 int buf_num = 0; 457 458 buf_num += mvpp2_read(priv, MVPP2_BM_POOL_PTRS_NUM_REG(bm_pool->id)) & 459 MVPP22_BM_POOL_PTRS_NUM_MASK; 460 buf_num += mvpp2_read(priv, MVPP2_BM_BPPI_PTRS_NUM_REG(bm_pool->id)) & 461 MVPP2_BM_BPPI_PTR_NUM_MASK; 462 463 /* HW has one buffer ready which is not reflected in the counters */ 464 if (buf_num) 465 buf_num += 1; 466 467 return buf_num; 468 } 469 470 /* Cleanup pool */ 471 static int mvpp2_bm_pool_destroy(struct platform_device *pdev, 472 struct mvpp2 *priv, 473 struct mvpp2_bm_pool *bm_pool) 474 { 475 int buf_num; 476 u32 val; 477 478 buf_num = mvpp2_check_hw_buf_num(priv, bm_pool); 479 mvpp2_bm_bufs_free(&pdev->dev, priv, bm_pool, buf_num); 480 481 /* Check buffer counters after free */ 482 buf_num = mvpp2_check_hw_buf_num(priv, bm_pool); 483 if (buf_num) { 484 WARN(1, "cannot free all buffers in pool %d, buf_num left %d\n", 485 bm_pool->id, bm_pool->buf_num); 486 return 0; 487 } 488 489 val = mvpp2_read(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id)); 490 val |= MVPP2_BM_STOP_MASK; 491 mvpp2_write(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id), val); 492 493 dma_free_coherent(&pdev->dev, bm_pool->size_bytes, 494 bm_pool->virt_addr, 495 bm_pool->dma_addr); 496 return 0; 497 } 498 499 static int mvpp2_bm_pools_init(struct platform_device *pdev, 500 struct mvpp2 *priv) 501 { 502 int i, err, size; 503 struct mvpp2_bm_pool *bm_pool; 504 505 /* Create all pools with maximum size */ 506 size = MVPP2_BM_POOL_SIZE_MAX; 507 for (i = 0; i < MVPP2_BM_POOLS_NUM; i++) { 508 bm_pool = &priv->bm_pools[i]; 509 bm_pool->id = i; 510 err = mvpp2_bm_pool_create(pdev, priv, bm_pool, size); 511 if (err) 512 goto err_unroll_pools; 513 mvpp2_bm_pool_bufsize_set(priv, bm_pool, 0); 514 } 515 return 0; 516 517 err_unroll_pools: 518 dev_err(&pdev->dev, "failed to create BM pool %d, size %d\n", i, size); 519 for (i = i - 1; i >= 0; i--) 520 mvpp2_bm_pool_destroy(pdev, priv, &priv->bm_pools[i]); 521 return err; 522 } 523 524 static int mvpp2_bm_init(struct platform_device *pdev, struct mvpp2 *priv) 525 { 526 int i, err; 527 528 for (i = 0; i < MVPP2_BM_POOLS_NUM; i++) { 529 /* Mask BM all interrupts */ 530 mvpp2_write(priv, MVPP2_BM_INTR_MASK_REG(i), 0); 531 /* Clear BM cause register */ 532 mvpp2_write(priv, MVPP2_BM_INTR_CAUSE_REG(i), 0); 533 } 534 535 /* Allocate and initialize BM pools */ 536 priv->bm_pools = devm_kcalloc(&pdev->dev, MVPP2_BM_POOLS_NUM, 537 sizeof(*priv->bm_pools), GFP_KERNEL); 538 if (!priv->bm_pools) 539 return -ENOMEM; 540 541 err = mvpp2_bm_pools_init(pdev, priv); 542 if (err < 0) 543 return err; 544 return 0; 545 } 546 547 static void mvpp2_setup_bm_pool(void) 548 { 549 /* Short pool */ 550 mvpp2_pools[MVPP2_BM_SHORT].buf_num = MVPP2_BM_SHORT_BUF_NUM; 551 mvpp2_pools[MVPP2_BM_SHORT].pkt_size = MVPP2_BM_SHORT_PKT_SIZE; 552 553 /* Long pool */ 554 mvpp2_pools[MVPP2_BM_LONG].buf_num = MVPP2_BM_LONG_BUF_NUM; 555 mvpp2_pools[MVPP2_BM_LONG].pkt_size = MVPP2_BM_LONG_PKT_SIZE; 556 557 /* Jumbo pool */ 558 mvpp2_pools[MVPP2_BM_JUMBO].buf_num = MVPP2_BM_JUMBO_BUF_NUM; 559 mvpp2_pools[MVPP2_BM_JUMBO].pkt_size = MVPP2_BM_JUMBO_PKT_SIZE; 560 } 561 562 /* Attach long pool to rxq */ 563 static void mvpp2_rxq_long_pool_set(struct mvpp2_port *port, 564 int lrxq, int long_pool) 565 { 566 u32 val, mask; 567 int prxq; 568 569 /* Get queue physical ID */ 570 prxq = port->rxqs[lrxq]->id; 571 572 if (port->priv->hw_version == MVPP21) 573 mask = MVPP21_RXQ_POOL_LONG_MASK; 574 else 575 mask = MVPP22_RXQ_POOL_LONG_MASK; 576 577 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(prxq)); 578 val &= ~mask; 579 val |= (long_pool << MVPP2_RXQ_POOL_LONG_OFFS) & mask; 580 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(prxq), val); 581 } 582 583 /* Attach short pool to rxq */ 584 static void mvpp2_rxq_short_pool_set(struct mvpp2_port *port, 585 int lrxq, int short_pool) 586 { 587 u32 val, mask; 588 int prxq; 589 590 /* Get queue physical ID */ 591 prxq = port->rxqs[lrxq]->id; 592 593 if (port->priv->hw_version == MVPP21) 594 mask = MVPP21_RXQ_POOL_SHORT_MASK; 595 else 596 mask = MVPP22_RXQ_POOL_SHORT_MASK; 597 598 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(prxq)); 599 val &= ~mask; 600 val |= (short_pool << MVPP2_RXQ_POOL_SHORT_OFFS) & mask; 601 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(prxq), val); 602 } 603 604 static void *mvpp2_buf_alloc(struct mvpp2_port *port, 605 struct mvpp2_bm_pool *bm_pool, 606 dma_addr_t *buf_dma_addr, 607 phys_addr_t *buf_phys_addr, 608 gfp_t gfp_mask) 609 { 610 dma_addr_t dma_addr; 611 void *data; 612 613 data = mvpp2_frag_alloc(bm_pool); 614 if (!data) 615 return NULL; 616 617 dma_addr = dma_map_single(port->dev->dev.parent, data, 618 MVPP2_RX_BUF_SIZE(bm_pool->pkt_size), 619 DMA_FROM_DEVICE); 620 if (unlikely(dma_mapping_error(port->dev->dev.parent, dma_addr))) { 621 mvpp2_frag_free(bm_pool, data); 622 return NULL; 623 } 624 *buf_dma_addr = dma_addr; 625 *buf_phys_addr = virt_to_phys(data); 626 627 return data; 628 } 629 630 /* Release buffer to BM */ 631 static inline void mvpp2_bm_pool_put(struct mvpp2_port *port, int pool, 632 dma_addr_t buf_dma_addr, 633 phys_addr_t buf_phys_addr) 634 { 635 unsigned int thread = mvpp2_cpu_to_thread(port->priv, get_cpu()); 636 unsigned long flags = 0; 637 638 if (test_bit(thread, &port->priv->lock_map)) 639 spin_lock_irqsave(&port->bm_lock[thread], flags); 640 641 if (port->priv->hw_version == MVPP22) { 642 u32 val = 0; 643 644 if (sizeof(dma_addr_t) == 8) 645 val |= upper_32_bits(buf_dma_addr) & 646 MVPP22_BM_ADDR_HIGH_PHYS_RLS_MASK; 647 648 if (sizeof(phys_addr_t) == 8) 649 val |= (upper_32_bits(buf_phys_addr) 650 << MVPP22_BM_ADDR_HIGH_VIRT_RLS_SHIFT) & 651 MVPP22_BM_ADDR_HIGH_VIRT_RLS_MASK; 652 653 mvpp2_thread_write_relaxed(port->priv, thread, 654 MVPP22_BM_ADDR_HIGH_RLS_REG, val); 655 } 656 657 /* MVPP2_BM_VIRT_RLS_REG is not interpreted by HW, and simply 658 * returned in the "cookie" field of the RX 659 * descriptor. Instead of storing the virtual address, we 660 * store the physical address 661 */ 662 mvpp2_thread_write_relaxed(port->priv, thread, 663 MVPP2_BM_VIRT_RLS_REG, buf_phys_addr); 664 mvpp2_thread_write_relaxed(port->priv, thread, 665 MVPP2_BM_PHY_RLS_REG(pool), buf_dma_addr); 666 667 if (test_bit(thread, &port->priv->lock_map)) 668 spin_unlock_irqrestore(&port->bm_lock[thread], flags); 669 670 put_cpu(); 671 } 672 673 /* Allocate buffers for the pool */ 674 static int mvpp2_bm_bufs_add(struct mvpp2_port *port, 675 struct mvpp2_bm_pool *bm_pool, int buf_num) 676 { 677 int i, buf_size, total_size; 678 dma_addr_t dma_addr; 679 phys_addr_t phys_addr; 680 void *buf; 681 682 buf_size = MVPP2_RX_BUF_SIZE(bm_pool->pkt_size); 683 total_size = MVPP2_RX_TOTAL_SIZE(buf_size); 684 685 if (buf_num < 0 || 686 (buf_num + bm_pool->buf_num > bm_pool->size)) { 687 netdev_err(port->dev, 688 "cannot allocate %d buffers for pool %d\n", 689 buf_num, bm_pool->id); 690 return 0; 691 } 692 693 for (i = 0; i < buf_num; i++) { 694 buf = mvpp2_buf_alloc(port, bm_pool, &dma_addr, 695 &phys_addr, GFP_KERNEL); 696 if (!buf) 697 break; 698 699 mvpp2_bm_pool_put(port, bm_pool->id, dma_addr, 700 phys_addr); 701 } 702 703 /* Update BM driver with number of buffers added to pool */ 704 bm_pool->buf_num += i; 705 706 netdev_dbg(port->dev, 707 "pool %d: pkt_size=%4d, buf_size=%4d, total_size=%4d\n", 708 bm_pool->id, bm_pool->pkt_size, buf_size, total_size); 709 710 netdev_dbg(port->dev, 711 "pool %d: %d of %d buffers added\n", 712 bm_pool->id, i, buf_num); 713 return i; 714 } 715 716 /* Notify the driver that BM pool is being used as specific type and return the 717 * pool pointer on success 718 */ 719 static struct mvpp2_bm_pool * 720 mvpp2_bm_pool_use(struct mvpp2_port *port, unsigned pool, int pkt_size) 721 { 722 struct mvpp2_bm_pool *new_pool = &port->priv->bm_pools[pool]; 723 int num; 724 725 if (pool >= MVPP2_BM_POOLS_NUM) { 726 netdev_err(port->dev, "Invalid pool %d\n", pool); 727 return NULL; 728 } 729 730 /* Allocate buffers in case BM pool is used as long pool, but packet 731 * size doesn't match MTU or BM pool hasn't being used yet 732 */ 733 if (new_pool->pkt_size == 0) { 734 int pkts_num; 735 736 /* Set default buffer number or free all the buffers in case 737 * the pool is not empty 738 */ 739 pkts_num = new_pool->buf_num; 740 if (pkts_num == 0) 741 pkts_num = mvpp2_pools[pool].buf_num; 742 else 743 mvpp2_bm_bufs_free(port->dev->dev.parent, 744 port->priv, new_pool, pkts_num); 745 746 new_pool->pkt_size = pkt_size; 747 new_pool->frag_size = 748 SKB_DATA_ALIGN(MVPP2_RX_BUF_SIZE(pkt_size)) + 749 MVPP2_SKB_SHINFO_SIZE; 750 751 /* Allocate buffers for this pool */ 752 num = mvpp2_bm_bufs_add(port, new_pool, pkts_num); 753 if (num != pkts_num) { 754 WARN(1, "pool %d: %d of %d allocated\n", 755 new_pool->id, num, pkts_num); 756 return NULL; 757 } 758 } 759 760 mvpp2_bm_pool_bufsize_set(port->priv, new_pool, 761 MVPP2_RX_BUF_SIZE(new_pool->pkt_size)); 762 763 return new_pool; 764 } 765 766 /* Initialize pools for swf */ 767 static int mvpp2_swf_bm_pool_init(struct mvpp2_port *port) 768 { 769 int rxq; 770 enum mvpp2_bm_pool_log_num long_log_pool, short_log_pool; 771 772 /* If port pkt_size is higher than 1518B: 773 * HW Long pool - SW Jumbo pool, HW Short pool - SW Long pool 774 * else: HW Long pool - SW Long pool, HW Short pool - SW Short pool 775 */ 776 if (port->pkt_size > MVPP2_BM_LONG_PKT_SIZE) { 777 long_log_pool = MVPP2_BM_JUMBO; 778 short_log_pool = MVPP2_BM_LONG; 779 } else { 780 long_log_pool = MVPP2_BM_LONG; 781 short_log_pool = MVPP2_BM_SHORT; 782 } 783 784 if (!port->pool_long) { 785 port->pool_long = 786 mvpp2_bm_pool_use(port, long_log_pool, 787 mvpp2_pools[long_log_pool].pkt_size); 788 if (!port->pool_long) 789 return -ENOMEM; 790 791 port->pool_long->port_map |= BIT(port->id); 792 793 for (rxq = 0; rxq < port->nrxqs; rxq++) 794 mvpp2_rxq_long_pool_set(port, rxq, port->pool_long->id); 795 } 796 797 if (!port->pool_short) { 798 port->pool_short = 799 mvpp2_bm_pool_use(port, short_log_pool, 800 mvpp2_pools[short_log_pool].pkt_size); 801 if (!port->pool_short) 802 return -ENOMEM; 803 804 port->pool_short->port_map |= BIT(port->id); 805 806 for (rxq = 0; rxq < port->nrxqs; rxq++) 807 mvpp2_rxq_short_pool_set(port, rxq, 808 port->pool_short->id); 809 } 810 811 return 0; 812 } 813 814 static int mvpp2_bm_update_mtu(struct net_device *dev, int mtu) 815 { 816 struct mvpp2_port *port = netdev_priv(dev); 817 enum mvpp2_bm_pool_log_num new_long_pool; 818 int pkt_size = MVPP2_RX_PKT_SIZE(mtu); 819 820 /* If port MTU is higher than 1518B: 821 * HW Long pool - SW Jumbo pool, HW Short pool - SW Long pool 822 * else: HW Long pool - SW Long pool, HW Short pool - SW Short pool 823 */ 824 if (pkt_size > MVPP2_BM_LONG_PKT_SIZE) 825 new_long_pool = MVPP2_BM_JUMBO; 826 else 827 new_long_pool = MVPP2_BM_LONG; 828 829 if (new_long_pool != port->pool_long->id) { 830 /* Remove port from old short & long pool */ 831 port->pool_long = mvpp2_bm_pool_use(port, port->pool_long->id, 832 port->pool_long->pkt_size); 833 port->pool_long->port_map &= ~BIT(port->id); 834 port->pool_long = NULL; 835 836 port->pool_short = mvpp2_bm_pool_use(port, port->pool_short->id, 837 port->pool_short->pkt_size); 838 port->pool_short->port_map &= ~BIT(port->id); 839 port->pool_short = NULL; 840 841 port->pkt_size = pkt_size; 842 843 /* Add port to new short & long pool */ 844 mvpp2_swf_bm_pool_init(port); 845 846 /* Update L4 checksum when jumbo enable/disable on port */ 847 if (new_long_pool == MVPP2_BM_JUMBO && port->id != 0) { 848 dev->features &= ~(NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM); 849 dev->hw_features &= ~(NETIF_F_IP_CSUM | 850 NETIF_F_IPV6_CSUM); 851 } else { 852 dev->features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM; 853 dev->hw_features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM; 854 } 855 } 856 857 dev->mtu = mtu; 858 dev->wanted_features = dev->features; 859 860 netdev_update_features(dev); 861 return 0; 862 } 863 864 static inline void mvpp2_interrupts_enable(struct mvpp2_port *port) 865 { 866 int i, sw_thread_mask = 0; 867 868 for (i = 0; i < port->nqvecs; i++) 869 sw_thread_mask |= port->qvecs[i].sw_thread_mask; 870 871 mvpp2_write(port->priv, MVPP2_ISR_ENABLE_REG(port->id), 872 MVPP2_ISR_ENABLE_INTERRUPT(sw_thread_mask)); 873 } 874 875 static inline void mvpp2_interrupts_disable(struct mvpp2_port *port) 876 { 877 int i, sw_thread_mask = 0; 878 879 for (i = 0; i < port->nqvecs; i++) 880 sw_thread_mask |= port->qvecs[i].sw_thread_mask; 881 882 mvpp2_write(port->priv, MVPP2_ISR_ENABLE_REG(port->id), 883 MVPP2_ISR_DISABLE_INTERRUPT(sw_thread_mask)); 884 } 885 886 static inline void mvpp2_qvec_interrupt_enable(struct mvpp2_queue_vector *qvec) 887 { 888 struct mvpp2_port *port = qvec->port; 889 890 mvpp2_write(port->priv, MVPP2_ISR_ENABLE_REG(port->id), 891 MVPP2_ISR_ENABLE_INTERRUPT(qvec->sw_thread_mask)); 892 } 893 894 static inline void mvpp2_qvec_interrupt_disable(struct mvpp2_queue_vector *qvec) 895 { 896 struct mvpp2_port *port = qvec->port; 897 898 mvpp2_write(port->priv, MVPP2_ISR_ENABLE_REG(port->id), 899 MVPP2_ISR_DISABLE_INTERRUPT(qvec->sw_thread_mask)); 900 } 901 902 /* Mask the current thread's Rx/Tx interrupts 903 * Called by on_each_cpu(), guaranteed to run with migration disabled, 904 * using smp_processor_id() is OK. 905 */ 906 static void mvpp2_interrupts_mask(void *arg) 907 { 908 struct mvpp2_port *port = arg; 909 910 /* If the thread isn't used, don't do anything */ 911 if (smp_processor_id() > port->priv->nthreads) 912 return; 913 914 mvpp2_thread_write(port->priv, 915 mvpp2_cpu_to_thread(port->priv, smp_processor_id()), 916 MVPP2_ISR_RX_TX_MASK_REG(port->id), 0); 917 } 918 919 /* Unmask the current thread's Rx/Tx interrupts. 920 * Called by on_each_cpu(), guaranteed to run with migration disabled, 921 * using smp_processor_id() is OK. 922 */ 923 static void mvpp2_interrupts_unmask(void *arg) 924 { 925 struct mvpp2_port *port = arg; 926 u32 val; 927 928 /* If the thread isn't used, don't do anything */ 929 if (smp_processor_id() > port->priv->nthreads) 930 return; 931 932 val = MVPP2_CAUSE_MISC_SUM_MASK | 933 MVPP2_CAUSE_RXQ_OCCUP_DESC_ALL_MASK(port->priv->hw_version); 934 if (port->has_tx_irqs) 935 val |= MVPP2_CAUSE_TXQ_OCCUP_DESC_ALL_MASK; 936 937 mvpp2_thread_write(port->priv, 938 mvpp2_cpu_to_thread(port->priv, smp_processor_id()), 939 MVPP2_ISR_RX_TX_MASK_REG(port->id), val); 940 } 941 942 static void 943 mvpp2_shared_interrupt_mask_unmask(struct mvpp2_port *port, bool mask) 944 { 945 u32 val; 946 int i; 947 948 if (port->priv->hw_version != MVPP22) 949 return; 950 951 if (mask) 952 val = 0; 953 else 954 val = MVPP2_CAUSE_RXQ_OCCUP_DESC_ALL_MASK(MVPP22); 955 956 for (i = 0; i < port->nqvecs; i++) { 957 struct mvpp2_queue_vector *v = port->qvecs + i; 958 959 if (v->type != MVPP2_QUEUE_VECTOR_SHARED) 960 continue; 961 962 mvpp2_thread_write(port->priv, v->sw_thread_id, 963 MVPP2_ISR_RX_TX_MASK_REG(port->id), val); 964 } 965 } 966 967 /* Port configuration routines */ 968 static bool mvpp2_is_xlg(phy_interface_t interface) 969 { 970 return interface == PHY_INTERFACE_MODE_10GKR || 971 interface == PHY_INTERFACE_MODE_XAUI; 972 } 973 974 static void mvpp22_gop_init_rgmii(struct mvpp2_port *port) 975 { 976 struct mvpp2 *priv = port->priv; 977 u32 val; 978 979 regmap_read(priv->sysctrl_base, GENCONF_PORT_CTRL0, &val); 980 val |= GENCONF_PORT_CTRL0_BUS_WIDTH_SELECT; 981 regmap_write(priv->sysctrl_base, GENCONF_PORT_CTRL0, val); 982 983 regmap_read(priv->sysctrl_base, GENCONF_CTRL0, &val); 984 if (port->gop_id == 2) 985 val |= GENCONF_CTRL0_PORT0_RGMII | GENCONF_CTRL0_PORT1_RGMII; 986 else if (port->gop_id == 3) 987 val |= GENCONF_CTRL0_PORT1_RGMII_MII; 988 regmap_write(priv->sysctrl_base, GENCONF_CTRL0, val); 989 } 990 991 static void mvpp22_gop_init_sgmii(struct mvpp2_port *port) 992 { 993 struct mvpp2 *priv = port->priv; 994 u32 val; 995 996 regmap_read(priv->sysctrl_base, GENCONF_PORT_CTRL0, &val); 997 val |= GENCONF_PORT_CTRL0_BUS_WIDTH_SELECT | 998 GENCONF_PORT_CTRL0_RX_DATA_SAMPLE; 999 regmap_write(priv->sysctrl_base, GENCONF_PORT_CTRL0, val); 1000 1001 if (port->gop_id > 1) { 1002 regmap_read(priv->sysctrl_base, GENCONF_CTRL0, &val); 1003 if (port->gop_id == 2) 1004 val &= ~GENCONF_CTRL0_PORT0_RGMII; 1005 else if (port->gop_id == 3) 1006 val &= ~GENCONF_CTRL0_PORT1_RGMII_MII; 1007 regmap_write(priv->sysctrl_base, GENCONF_CTRL0, val); 1008 } 1009 } 1010 1011 static void mvpp22_gop_init_10gkr(struct mvpp2_port *port) 1012 { 1013 struct mvpp2 *priv = port->priv; 1014 void __iomem *mpcs = priv->iface_base + MVPP22_MPCS_BASE(port->gop_id); 1015 void __iomem *xpcs = priv->iface_base + MVPP22_XPCS_BASE(port->gop_id); 1016 u32 val; 1017 1018 val = readl(xpcs + MVPP22_XPCS_CFG0); 1019 val &= ~(MVPP22_XPCS_CFG0_PCS_MODE(0x3) | 1020 MVPP22_XPCS_CFG0_ACTIVE_LANE(0x3)); 1021 val |= MVPP22_XPCS_CFG0_ACTIVE_LANE(2); 1022 writel(val, xpcs + MVPP22_XPCS_CFG0); 1023 1024 val = readl(mpcs + MVPP22_MPCS_CTRL); 1025 val &= ~MVPP22_MPCS_CTRL_FWD_ERR_CONN; 1026 writel(val, mpcs + MVPP22_MPCS_CTRL); 1027 1028 val = readl(mpcs + MVPP22_MPCS_CLK_RESET); 1029 val &= ~MVPP22_MPCS_CLK_RESET_DIV_RATIO(0x7); 1030 val |= MVPP22_MPCS_CLK_RESET_DIV_RATIO(1); 1031 writel(val, mpcs + MVPP22_MPCS_CLK_RESET); 1032 } 1033 1034 static int mvpp22_gop_init(struct mvpp2_port *port) 1035 { 1036 struct mvpp2 *priv = port->priv; 1037 u32 val; 1038 1039 if (!priv->sysctrl_base) 1040 return 0; 1041 1042 switch (port->phy_interface) { 1043 case PHY_INTERFACE_MODE_RGMII: 1044 case PHY_INTERFACE_MODE_RGMII_ID: 1045 case PHY_INTERFACE_MODE_RGMII_RXID: 1046 case PHY_INTERFACE_MODE_RGMII_TXID: 1047 if (port->gop_id == 0) 1048 goto invalid_conf; 1049 mvpp22_gop_init_rgmii(port); 1050 break; 1051 case PHY_INTERFACE_MODE_SGMII: 1052 case PHY_INTERFACE_MODE_1000BASEX: 1053 case PHY_INTERFACE_MODE_2500BASEX: 1054 mvpp22_gop_init_sgmii(port); 1055 break; 1056 case PHY_INTERFACE_MODE_10GKR: 1057 if (port->gop_id != 0) 1058 goto invalid_conf; 1059 mvpp22_gop_init_10gkr(port); 1060 break; 1061 default: 1062 goto unsupported_conf; 1063 } 1064 1065 regmap_read(priv->sysctrl_base, GENCONF_PORT_CTRL1, &val); 1066 val |= GENCONF_PORT_CTRL1_RESET(port->gop_id) | 1067 GENCONF_PORT_CTRL1_EN(port->gop_id); 1068 regmap_write(priv->sysctrl_base, GENCONF_PORT_CTRL1, val); 1069 1070 regmap_read(priv->sysctrl_base, GENCONF_PORT_CTRL0, &val); 1071 val |= GENCONF_PORT_CTRL0_CLK_DIV_PHASE_CLR; 1072 regmap_write(priv->sysctrl_base, GENCONF_PORT_CTRL0, val); 1073 1074 regmap_read(priv->sysctrl_base, GENCONF_SOFT_RESET1, &val); 1075 val |= GENCONF_SOFT_RESET1_GOP; 1076 regmap_write(priv->sysctrl_base, GENCONF_SOFT_RESET1, val); 1077 1078 unsupported_conf: 1079 return 0; 1080 1081 invalid_conf: 1082 netdev_err(port->dev, "Invalid port configuration\n"); 1083 return -EINVAL; 1084 } 1085 1086 static void mvpp22_gop_unmask_irq(struct mvpp2_port *port) 1087 { 1088 u32 val; 1089 1090 if (phy_interface_mode_is_rgmii(port->phy_interface) || 1091 phy_interface_mode_is_8023z(port->phy_interface) || 1092 port->phy_interface == PHY_INTERFACE_MODE_SGMII) { 1093 /* Enable the GMAC link status irq for this port */ 1094 val = readl(port->base + MVPP22_GMAC_INT_SUM_MASK); 1095 val |= MVPP22_GMAC_INT_SUM_MASK_LINK_STAT; 1096 writel(val, port->base + MVPP22_GMAC_INT_SUM_MASK); 1097 } 1098 1099 if (port->gop_id == 0) { 1100 /* Enable the XLG/GIG irqs for this port */ 1101 val = readl(port->base + MVPP22_XLG_EXT_INT_MASK); 1102 if (mvpp2_is_xlg(port->phy_interface)) 1103 val |= MVPP22_XLG_EXT_INT_MASK_XLG; 1104 else 1105 val |= MVPP22_XLG_EXT_INT_MASK_GIG; 1106 writel(val, port->base + MVPP22_XLG_EXT_INT_MASK); 1107 } 1108 } 1109 1110 static void mvpp22_gop_mask_irq(struct mvpp2_port *port) 1111 { 1112 u32 val; 1113 1114 if (port->gop_id == 0) { 1115 val = readl(port->base + MVPP22_XLG_EXT_INT_MASK); 1116 val &= ~(MVPP22_XLG_EXT_INT_MASK_XLG | 1117 MVPP22_XLG_EXT_INT_MASK_GIG); 1118 writel(val, port->base + MVPP22_XLG_EXT_INT_MASK); 1119 } 1120 1121 if (phy_interface_mode_is_rgmii(port->phy_interface) || 1122 phy_interface_mode_is_8023z(port->phy_interface) || 1123 port->phy_interface == PHY_INTERFACE_MODE_SGMII) { 1124 val = readl(port->base + MVPP22_GMAC_INT_SUM_MASK); 1125 val &= ~MVPP22_GMAC_INT_SUM_MASK_LINK_STAT; 1126 writel(val, port->base + MVPP22_GMAC_INT_SUM_MASK); 1127 } 1128 } 1129 1130 static void mvpp22_gop_setup_irq(struct mvpp2_port *port) 1131 { 1132 u32 val; 1133 1134 if (port->phylink || 1135 phy_interface_mode_is_rgmii(port->phy_interface) || 1136 phy_interface_mode_is_8023z(port->phy_interface) || 1137 port->phy_interface == PHY_INTERFACE_MODE_SGMII) { 1138 val = readl(port->base + MVPP22_GMAC_INT_MASK); 1139 val |= MVPP22_GMAC_INT_MASK_LINK_STAT; 1140 writel(val, port->base + MVPP22_GMAC_INT_MASK); 1141 } 1142 1143 if (port->gop_id == 0) { 1144 val = readl(port->base + MVPP22_XLG_INT_MASK); 1145 val |= MVPP22_XLG_INT_MASK_LINK; 1146 writel(val, port->base + MVPP22_XLG_INT_MASK); 1147 } 1148 1149 mvpp22_gop_unmask_irq(port); 1150 } 1151 1152 /* Sets the PHY mode of the COMPHY (which configures the serdes lanes). 1153 * 1154 * The PHY mode used by the PPv2 driver comes from the network subsystem, while 1155 * the one given to the COMPHY comes from the generic PHY subsystem. Hence they 1156 * differ. 1157 * 1158 * The COMPHY configures the serdes lanes regardless of the actual use of the 1159 * lanes by the physical layer. This is why configurations like 1160 * "PPv2 (2500BaseX) - COMPHY (2500SGMII)" are valid. 1161 */ 1162 static int mvpp22_comphy_init(struct mvpp2_port *port) 1163 { 1164 int ret; 1165 1166 if (!port->comphy) 1167 return 0; 1168 1169 ret = phy_set_mode_ext(port->comphy, PHY_MODE_ETHERNET, 1170 port->phy_interface); 1171 if (ret) 1172 return ret; 1173 1174 return phy_power_on(port->comphy); 1175 } 1176 1177 static void mvpp2_port_enable(struct mvpp2_port *port) 1178 { 1179 u32 val; 1180 1181 /* Only GOP port 0 has an XLG MAC */ 1182 if (port->gop_id == 0 && mvpp2_is_xlg(port->phy_interface)) { 1183 val = readl(port->base + MVPP22_XLG_CTRL0_REG); 1184 val |= MVPP22_XLG_CTRL0_PORT_EN; 1185 val &= ~MVPP22_XLG_CTRL0_MIB_CNT_DIS; 1186 writel(val, port->base + MVPP22_XLG_CTRL0_REG); 1187 } else { 1188 val = readl(port->base + MVPP2_GMAC_CTRL_0_REG); 1189 val |= MVPP2_GMAC_PORT_EN_MASK; 1190 val |= MVPP2_GMAC_MIB_CNTR_EN_MASK; 1191 writel(val, port->base + MVPP2_GMAC_CTRL_0_REG); 1192 } 1193 } 1194 1195 static void mvpp2_port_disable(struct mvpp2_port *port) 1196 { 1197 u32 val; 1198 1199 /* Only GOP port 0 has an XLG MAC */ 1200 if (port->gop_id == 0 && mvpp2_is_xlg(port->phy_interface)) { 1201 val = readl(port->base + MVPP22_XLG_CTRL0_REG); 1202 val &= ~MVPP22_XLG_CTRL0_PORT_EN; 1203 writel(val, port->base + MVPP22_XLG_CTRL0_REG); 1204 } 1205 1206 val = readl(port->base + MVPP2_GMAC_CTRL_0_REG); 1207 val &= ~(MVPP2_GMAC_PORT_EN_MASK); 1208 writel(val, port->base + MVPP2_GMAC_CTRL_0_REG); 1209 } 1210 1211 /* Set IEEE 802.3x Flow Control Xon Packet Transmission Mode */ 1212 static void mvpp2_port_periodic_xon_disable(struct mvpp2_port *port) 1213 { 1214 u32 val; 1215 1216 val = readl(port->base + MVPP2_GMAC_CTRL_1_REG) & 1217 ~MVPP2_GMAC_PERIODIC_XON_EN_MASK; 1218 writel(val, port->base + MVPP2_GMAC_CTRL_1_REG); 1219 } 1220 1221 /* Configure loopback port */ 1222 static void mvpp2_port_loopback_set(struct mvpp2_port *port, 1223 const struct phylink_link_state *state) 1224 { 1225 u32 val; 1226 1227 val = readl(port->base + MVPP2_GMAC_CTRL_1_REG); 1228 1229 if (state->speed == 1000) 1230 val |= MVPP2_GMAC_GMII_LB_EN_MASK; 1231 else 1232 val &= ~MVPP2_GMAC_GMII_LB_EN_MASK; 1233 1234 if (phy_interface_mode_is_8023z(port->phy_interface) || 1235 port->phy_interface == PHY_INTERFACE_MODE_SGMII) 1236 val |= MVPP2_GMAC_PCS_LB_EN_MASK; 1237 else 1238 val &= ~MVPP2_GMAC_PCS_LB_EN_MASK; 1239 1240 writel(val, port->base + MVPP2_GMAC_CTRL_1_REG); 1241 } 1242 1243 struct mvpp2_ethtool_counter { 1244 unsigned int offset; 1245 const char string[ETH_GSTRING_LEN]; 1246 bool reg_is_64b; 1247 }; 1248 1249 static u64 mvpp2_read_count(struct mvpp2_port *port, 1250 const struct mvpp2_ethtool_counter *counter) 1251 { 1252 u64 val; 1253 1254 val = readl(port->stats_base + counter->offset); 1255 if (counter->reg_is_64b) 1256 val += (u64)readl(port->stats_base + counter->offset + 4) << 32; 1257 1258 return val; 1259 } 1260 1261 /* Some counters are accessed indirectly by first writing an index to 1262 * MVPP2_CTRS_IDX. The index can represent various resources depending on the 1263 * register we access, it can be a hit counter for some classification tables, 1264 * a counter specific to a rxq, a txq or a buffer pool. 1265 */ 1266 static u32 mvpp2_read_index(struct mvpp2 *priv, u32 index, u32 reg) 1267 { 1268 mvpp2_write(priv, MVPP2_CTRS_IDX, index); 1269 return mvpp2_read(priv, reg); 1270 } 1271 1272 /* Due to the fact that software statistics and hardware statistics are, by 1273 * design, incremented at different moments in the chain of packet processing, 1274 * it is very likely that incoming packets could have been dropped after being 1275 * counted by hardware but before reaching software statistics (most probably 1276 * multicast packets), and in the oppposite way, during transmission, FCS bytes 1277 * are added in between as well as TSO skb will be split and header bytes added. 1278 * Hence, statistics gathered from userspace with ifconfig (software) and 1279 * ethtool (hardware) cannot be compared. 1280 */ 1281 static const struct mvpp2_ethtool_counter mvpp2_ethtool_mib_regs[] = { 1282 { MVPP2_MIB_GOOD_OCTETS_RCVD, "good_octets_received", true }, 1283 { MVPP2_MIB_BAD_OCTETS_RCVD, "bad_octets_received" }, 1284 { MVPP2_MIB_CRC_ERRORS_SENT, "crc_errors_sent" }, 1285 { MVPP2_MIB_UNICAST_FRAMES_RCVD, "unicast_frames_received" }, 1286 { MVPP2_MIB_BROADCAST_FRAMES_RCVD, "broadcast_frames_received" }, 1287 { MVPP2_MIB_MULTICAST_FRAMES_RCVD, "multicast_frames_received" }, 1288 { MVPP2_MIB_FRAMES_64_OCTETS, "frames_64_octets" }, 1289 { MVPP2_MIB_FRAMES_65_TO_127_OCTETS, "frames_65_to_127_octet" }, 1290 { MVPP2_MIB_FRAMES_128_TO_255_OCTETS, "frames_128_to_255_octet" }, 1291 { MVPP2_MIB_FRAMES_256_TO_511_OCTETS, "frames_256_to_511_octet" }, 1292 { MVPP2_MIB_FRAMES_512_TO_1023_OCTETS, "frames_512_to_1023_octet" }, 1293 { MVPP2_MIB_FRAMES_1024_TO_MAX_OCTETS, "frames_1024_to_max_octet" }, 1294 { MVPP2_MIB_GOOD_OCTETS_SENT, "good_octets_sent", true }, 1295 { MVPP2_MIB_UNICAST_FRAMES_SENT, "unicast_frames_sent" }, 1296 { MVPP2_MIB_MULTICAST_FRAMES_SENT, "multicast_frames_sent" }, 1297 { MVPP2_MIB_BROADCAST_FRAMES_SENT, "broadcast_frames_sent" }, 1298 { MVPP2_MIB_FC_SENT, "fc_sent" }, 1299 { MVPP2_MIB_FC_RCVD, "fc_received" }, 1300 { MVPP2_MIB_RX_FIFO_OVERRUN, "rx_fifo_overrun" }, 1301 { MVPP2_MIB_UNDERSIZE_RCVD, "undersize_received" }, 1302 { MVPP2_MIB_FRAGMENTS_RCVD, "fragments_received" }, 1303 { MVPP2_MIB_OVERSIZE_RCVD, "oversize_received" }, 1304 { MVPP2_MIB_JABBER_RCVD, "jabber_received" }, 1305 { MVPP2_MIB_MAC_RCV_ERROR, "mac_receive_error" }, 1306 { MVPP2_MIB_BAD_CRC_EVENT, "bad_crc_event" }, 1307 { MVPP2_MIB_COLLISION, "collision" }, 1308 { MVPP2_MIB_LATE_COLLISION, "late_collision" }, 1309 }; 1310 1311 static const struct mvpp2_ethtool_counter mvpp2_ethtool_port_regs[] = { 1312 { MVPP2_OVERRUN_ETH_DROP, "rx_fifo_or_parser_overrun_drops" }, 1313 { MVPP2_CLS_ETH_DROP, "rx_classifier_drops" }, 1314 }; 1315 1316 static const struct mvpp2_ethtool_counter mvpp2_ethtool_txq_regs[] = { 1317 { MVPP2_TX_DESC_ENQ_CTR, "txq_%d_desc_enqueue" }, 1318 { MVPP2_TX_DESC_ENQ_TO_DDR_CTR, "txq_%d_desc_enqueue_to_ddr" }, 1319 { MVPP2_TX_BUFF_ENQ_TO_DDR_CTR, "txq_%d_buff_euqueue_to_ddr" }, 1320 { MVPP2_TX_DESC_ENQ_HW_FWD_CTR, "txq_%d_desc_hardware_forwarded" }, 1321 { MVPP2_TX_PKTS_DEQ_CTR, "txq_%d_packets_dequeued" }, 1322 { MVPP2_TX_PKTS_FULL_QUEUE_DROP_CTR, "txq_%d_queue_full_drops" }, 1323 { MVPP2_TX_PKTS_EARLY_DROP_CTR, "txq_%d_packets_early_drops" }, 1324 { MVPP2_TX_PKTS_BM_DROP_CTR, "txq_%d_packets_bm_drops" }, 1325 { MVPP2_TX_PKTS_BM_MC_DROP_CTR, "txq_%d_packets_rep_bm_drops" }, 1326 }; 1327 1328 static const struct mvpp2_ethtool_counter mvpp2_ethtool_rxq_regs[] = { 1329 { MVPP2_RX_DESC_ENQ_CTR, "rxq_%d_desc_enqueue" }, 1330 { MVPP2_RX_PKTS_FULL_QUEUE_DROP_CTR, "rxq_%d_queue_full_drops" }, 1331 { MVPP2_RX_PKTS_EARLY_DROP_CTR, "rxq_%d_packets_early_drops" }, 1332 { MVPP2_RX_PKTS_BM_DROP_CTR, "rxq_%d_packets_bm_drops" }, 1333 }; 1334 1335 #define MVPP2_N_ETHTOOL_STATS(ntxqs, nrxqs) (ARRAY_SIZE(mvpp2_ethtool_mib_regs) + \ 1336 ARRAY_SIZE(mvpp2_ethtool_port_regs) + \ 1337 (ARRAY_SIZE(mvpp2_ethtool_txq_regs) * (ntxqs)) + \ 1338 (ARRAY_SIZE(mvpp2_ethtool_rxq_regs) * (nrxqs))) 1339 1340 static void mvpp2_ethtool_get_strings(struct net_device *netdev, u32 sset, 1341 u8 *data) 1342 { 1343 struct mvpp2_port *port = netdev_priv(netdev); 1344 int i, q; 1345 1346 if (sset != ETH_SS_STATS) 1347 return; 1348 1349 for (i = 0; i < ARRAY_SIZE(mvpp2_ethtool_mib_regs); i++) { 1350 strscpy(data, mvpp2_ethtool_mib_regs[i].string, 1351 ETH_GSTRING_LEN); 1352 data += ETH_GSTRING_LEN; 1353 } 1354 1355 for (i = 0; i < ARRAY_SIZE(mvpp2_ethtool_port_regs); i++) { 1356 strscpy(data, mvpp2_ethtool_port_regs[i].string, 1357 ETH_GSTRING_LEN); 1358 data += ETH_GSTRING_LEN; 1359 } 1360 1361 for (q = 0; q < port->ntxqs; q++) { 1362 for (i = 0; i < ARRAY_SIZE(mvpp2_ethtool_txq_regs); i++) { 1363 snprintf(data, ETH_GSTRING_LEN, 1364 mvpp2_ethtool_txq_regs[i].string, q); 1365 data += ETH_GSTRING_LEN; 1366 } 1367 } 1368 1369 for (q = 0; q < port->nrxqs; q++) { 1370 for (i = 0; i < ARRAY_SIZE(mvpp2_ethtool_rxq_regs); i++) { 1371 snprintf(data, ETH_GSTRING_LEN, 1372 mvpp2_ethtool_rxq_regs[i].string, 1373 q); 1374 data += ETH_GSTRING_LEN; 1375 } 1376 } 1377 } 1378 1379 static void mvpp2_read_stats(struct mvpp2_port *port) 1380 { 1381 u64 *pstats; 1382 int i, q; 1383 1384 pstats = port->ethtool_stats; 1385 1386 for (i = 0; i < ARRAY_SIZE(mvpp2_ethtool_mib_regs); i++) 1387 *pstats++ += mvpp2_read_count(port, &mvpp2_ethtool_mib_regs[i]); 1388 1389 for (i = 0; i < ARRAY_SIZE(mvpp2_ethtool_port_regs); i++) 1390 *pstats++ += mvpp2_read(port->priv, 1391 mvpp2_ethtool_port_regs[i].offset + 1392 4 * port->id); 1393 1394 for (q = 0; q < port->ntxqs; q++) 1395 for (i = 0; i < ARRAY_SIZE(mvpp2_ethtool_txq_regs); i++) 1396 *pstats++ += mvpp2_read_index(port->priv, 1397 MVPP22_CTRS_TX_CTR(port->id, i), 1398 mvpp2_ethtool_txq_regs[i].offset); 1399 1400 /* Rxqs are numbered from 0 from the user standpoint, but not from the 1401 * driver's. We need to add the port->first_rxq offset. 1402 */ 1403 for (q = 0; q < port->nrxqs; q++) 1404 for (i = 0; i < ARRAY_SIZE(mvpp2_ethtool_rxq_regs); i++) 1405 *pstats++ += mvpp2_read_index(port->priv, 1406 port->first_rxq + i, 1407 mvpp2_ethtool_rxq_regs[i].offset); 1408 } 1409 1410 static void mvpp2_gather_hw_statistics(struct work_struct *work) 1411 { 1412 struct delayed_work *del_work = to_delayed_work(work); 1413 struct mvpp2_port *port = container_of(del_work, struct mvpp2_port, 1414 stats_work); 1415 1416 mutex_lock(&port->gather_stats_lock); 1417 1418 mvpp2_read_stats(port); 1419 1420 /* No need to read again the counters right after this function if it 1421 * was called asynchronously by the user (ie. use of ethtool). 1422 */ 1423 cancel_delayed_work(&port->stats_work); 1424 queue_delayed_work(port->priv->stats_queue, &port->stats_work, 1425 MVPP2_MIB_COUNTERS_STATS_DELAY); 1426 1427 mutex_unlock(&port->gather_stats_lock); 1428 } 1429 1430 static void mvpp2_ethtool_get_stats(struct net_device *dev, 1431 struct ethtool_stats *stats, u64 *data) 1432 { 1433 struct mvpp2_port *port = netdev_priv(dev); 1434 1435 /* Update statistics for the given port, then take the lock to avoid 1436 * concurrent accesses on the ethtool_stats structure during its copy. 1437 */ 1438 mvpp2_gather_hw_statistics(&port->stats_work.work); 1439 1440 mutex_lock(&port->gather_stats_lock); 1441 memcpy(data, port->ethtool_stats, 1442 sizeof(u64) * MVPP2_N_ETHTOOL_STATS(port->ntxqs, port->nrxqs)); 1443 mutex_unlock(&port->gather_stats_lock); 1444 } 1445 1446 static int mvpp2_ethtool_get_sset_count(struct net_device *dev, int sset) 1447 { 1448 struct mvpp2_port *port = netdev_priv(dev); 1449 1450 if (sset == ETH_SS_STATS) 1451 return MVPP2_N_ETHTOOL_STATS(port->ntxqs, port->nrxqs); 1452 1453 return -EOPNOTSUPP; 1454 } 1455 1456 static void mvpp2_mac_reset_assert(struct mvpp2_port *port) 1457 { 1458 u32 val; 1459 1460 val = readl(port->base + MVPP2_GMAC_CTRL_2_REG) | 1461 MVPP2_GMAC_PORT_RESET_MASK; 1462 writel(val, port->base + MVPP2_GMAC_CTRL_2_REG); 1463 1464 if (port->priv->hw_version == MVPP22 && port->gop_id == 0) { 1465 val = readl(port->base + MVPP22_XLG_CTRL0_REG) & 1466 ~MVPP22_XLG_CTRL0_MAC_RESET_DIS; 1467 writel(val, port->base + MVPP22_XLG_CTRL0_REG); 1468 } 1469 } 1470 1471 static void mvpp22_pcs_reset_assert(struct mvpp2_port *port) 1472 { 1473 struct mvpp2 *priv = port->priv; 1474 void __iomem *mpcs, *xpcs; 1475 u32 val; 1476 1477 if (port->priv->hw_version != MVPP22 || port->gop_id != 0) 1478 return; 1479 1480 mpcs = priv->iface_base + MVPP22_MPCS_BASE(port->gop_id); 1481 xpcs = priv->iface_base + MVPP22_XPCS_BASE(port->gop_id); 1482 1483 val = readl(mpcs + MVPP22_MPCS_CLK_RESET); 1484 val &= ~(MAC_CLK_RESET_MAC | MAC_CLK_RESET_SD_RX | MAC_CLK_RESET_SD_TX); 1485 val |= MVPP22_MPCS_CLK_RESET_DIV_SET; 1486 writel(val, mpcs + MVPP22_MPCS_CLK_RESET); 1487 1488 val = readl(xpcs + MVPP22_XPCS_CFG0); 1489 writel(val & ~MVPP22_XPCS_CFG0_RESET_DIS, xpcs + MVPP22_XPCS_CFG0); 1490 } 1491 1492 static void mvpp22_pcs_reset_deassert(struct mvpp2_port *port) 1493 { 1494 struct mvpp2 *priv = port->priv; 1495 void __iomem *mpcs, *xpcs; 1496 u32 val; 1497 1498 if (port->priv->hw_version != MVPP22 || port->gop_id != 0) 1499 return; 1500 1501 mpcs = priv->iface_base + MVPP22_MPCS_BASE(port->gop_id); 1502 xpcs = priv->iface_base + MVPP22_XPCS_BASE(port->gop_id); 1503 1504 switch (port->phy_interface) { 1505 case PHY_INTERFACE_MODE_10GKR: 1506 val = readl(mpcs + MVPP22_MPCS_CLK_RESET); 1507 val |= MAC_CLK_RESET_MAC | MAC_CLK_RESET_SD_RX | 1508 MAC_CLK_RESET_SD_TX; 1509 val &= ~MVPP22_MPCS_CLK_RESET_DIV_SET; 1510 writel(val, mpcs + MVPP22_MPCS_CLK_RESET); 1511 break; 1512 case PHY_INTERFACE_MODE_XAUI: 1513 case PHY_INTERFACE_MODE_RXAUI: 1514 val = readl(xpcs + MVPP22_XPCS_CFG0); 1515 writel(val | MVPP22_XPCS_CFG0_RESET_DIS, xpcs + MVPP22_XPCS_CFG0); 1516 break; 1517 default: 1518 break; 1519 } 1520 } 1521 1522 /* Change maximum receive size of the port */ 1523 static inline void mvpp2_gmac_max_rx_size_set(struct mvpp2_port *port) 1524 { 1525 u32 val; 1526 1527 val = readl(port->base + MVPP2_GMAC_CTRL_0_REG); 1528 val &= ~MVPP2_GMAC_MAX_RX_SIZE_MASK; 1529 val |= (((port->pkt_size - MVPP2_MH_SIZE) / 2) << 1530 MVPP2_GMAC_MAX_RX_SIZE_OFFS); 1531 writel(val, port->base + MVPP2_GMAC_CTRL_0_REG); 1532 } 1533 1534 /* Change maximum receive size of the port */ 1535 static inline void mvpp2_xlg_max_rx_size_set(struct mvpp2_port *port) 1536 { 1537 u32 val; 1538 1539 val = readl(port->base + MVPP22_XLG_CTRL1_REG); 1540 val &= ~MVPP22_XLG_CTRL1_FRAMESIZELIMIT_MASK; 1541 val |= ((port->pkt_size - MVPP2_MH_SIZE) / 2) << 1542 MVPP22_XLG_CTRL1_FRAMESIZELIMIT_OFFS; 1543 writel(val, port->base + MVPP22_XLG_CTRL1_REG); 1544 } 1545 1546 /* Set defaults to the MVPP2 port */ 1547 static void mvpp2_defaults_set(struct mvpp2_port *port) 1548 { 1549 int tx_port_num, val, queue, lrxq; 1550 1551 if (port->priv->hw_version == MVPP21) { 1552 /* Update TX FIFO MIN Threshold */ 1553 val = readl(port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG); 1554 val &= ~MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK; 1555 /* Min. TX threshold must be less than minimal packet length */ 1556 val |= MVPP2_GMAC_TX_FIFO_MIN_TH_MASK(64 - 4 - 2); 1557 writel(val, port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG); 1558 } 1559 1560 /* Disable Legacy WRR, Disable EJP, Release from reset */ 1561 tx_port_num = mvpp2_egress_port(port); 1562 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, 1563 tx_port_num); 1564 mvpp2_write(port->priv, MVPP2_TXP_SCHED_CMD_1_REG, 0); 1565 1566 /* Set TXQ scheduling to Round-Robin */ 1567 mvpp2_write(port->priv, MVPP2_TXP_SCHED_FIXED_PRIO_REG, 0); 1568 1569 /* Close bandwidth for all queues */ 1570 for (queue = 0; queue < MVPP2_MAX_TXQ; queue++) 1571 mvpp2_write(port->priv, 1572 MVPP2_TXQ_SCHED_TOKEN_CNTR_REG(queue), 0); 1573 1574 /* Set refill period to 1 usec, refill tokens 1575 * and bucket size to maximum 1576 */ 1577 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PERIOD_REG, 1578 port->priv->tclk / USEC_PER_SEC); 1579 val = mvpp2_read(port->priv, MVPP2_TXP_SCHED_REFILL_REG); 1580 val &= ~MVPP2_TXP_REFILL_PERIOD_ALL_MASK; 1581 val |= MVPP2_TXP_REFILL_PERIOD_MASK(1); 1582 val |= MVPP2_TXP_REFILL_TOKENS_ALL_MASK; 1583 mvpp2_write(port->priv, MVPP2_TXP_SCHED_REFILL_REG, val); 1584 val = MVPP2_TXP_TOKEN_SIZE_MAX; 1585 mvpp2_write(port->priv, MVPP2_TXP_SCHED_TOKEN_SIZE_REG, val); 1586 1587 /* Set MaximumLowLatencyPacketSize value to 256 */ 1588 mvpp2_write(port->priv, MVPP2_RX_CTRL_REG(port->id), 1589 MVPP2_RX_USE_PSEUDO_FOR_CSUM_MASK | 1590 MVPP2_RX_LOW_LATENCY_PKT_SIZE(256)); 1591 1592 /* Enable Rx cache snoop */ 1593 for (lrxq = 0; lrxq < port->nrxqs; lrxq++) { 1594 queue = port->rxqs[lrxq]->id; 1595 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(queue)); 1596 val |= MVPP2_SNOOP_PKT_SIZE_MASK | 1597 MVPP2_SNOOP_BUF_HDR_MASK; 1598 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(queue), val); 1599 } 1600 1601 /* At default, mask all interrupts to all present cpus */ 1602 mvpp2_interrupts_disable(port); 1603 } 1604 1605 /* Enable/disable receiving packets */ 1606 static void mvpp2_ingress_enable(struct mvpp2_port *port) 1607 { 1608 u32 val; 1609 int lrxq, queue; 1610 1611 for (lrxq = 0; lrxq < port->nrxqs; lrxq++) { 1612 queue = port->rxqs[lrxq]->id; 1613 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(queue)); 1614 val &= ~MVPP2_RXQ_DISABLE_MASK; 1615 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(queue), val); 1616 } 1617 } 1618 1619 static void mvpp2_ingress_disable(struct mvpp2_port *port) 1620 { 1621 u32 val; 1622 int lrxq, queue; 1623 1624 for (lrxq = 0; lrxq < port->nrxqs; lrxq++) { 1625 queue = port->rxqs[lrxq]->id; 1626 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(queue)); 1627 val |= MVPP2_RXQ_DISABLE_MASK; 1628 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(queue), val); 1629 } 1630 } 1631 1632 /* Enable transmit via physical egress queue 1633 * - HW starts take descriptors from DRAM 1634 */ 1635 static void mvpp2_egress_enable(struct mvpp2_port *port) 1636 { 1637 u32 qmap; 1638 int queue; 1639 int tx_port_num = mvpp2_egress_port(port); 1640 1641 /* Enable all initialized TXs. */ 1642 qmap = 0; 1643 for (queue = 0; queue < port->ntxqs; queue++) { 1644 struct mvpp2_tx_queue *txq = port->txqs[queue]; 1645 1646 if (txq->descs) 1647 qmap |= (1 << queue); 1648 } 1649 1650 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num); 1651 mvpp2_write(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG, qmap); 1652 } 1653 1654 /* Disable transmit via physical egress queue 1655 * - HW doesn't take descriptors from DRAM 1656 */ 1657 static void mvpp2_egress_disable(struct mvpp2_port *port) 1658 { 1659 u32 reg_data; 1660 int delay; 1661 int tx_port_num = mvpp2_egress_port(port); 1662 1663 /* Issue stop command for active channels only */ 1664 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num); 1665 reg_data = (mvpp2_read(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG)) & 1666 MVPP2_TXP_SCHED_ENQ_MASK; 1667 if (reg_data != 0) 1668 mvpp2_write(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG, 1669 (reg_data << MVPP2_TXP_SCHED_DISQ_OFFSET)); 1670 1671 /* Wait for all Tx activity to terminate. */ 1672 delay = 0; 1673 do { 1674 if (delay >= MVPP2_TX_DISABLE_TIMEOUT_MSEC) { 1675 netdev_warn(port->dev, 1676 "Tx stop timed out, status=0x%08x\n", 1677 reg_data); 1678 break; 1679 } 1680 mdelay(1); 1681 delay++; 1682 1683 /* Check port TX Command register that all 1684 * Tx queues are stopped 1685 */ 1686 reg_data = mvpp2_read(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG); 1687 } while (reg_data & MVPP2_TXP_SCHED_ENQ_MASK); 1688 } 1689 1690 /* Rx descriptors helper methods */ 1691 1692 /* Get number of Rx descriptors occupied by received packets */ 1693 static inline int 1694 mvpp2_rxq_received(struct mvpp2_port *port, int rxq_id) 1695 { 1696 u32 val = mvpp2_read(port->priv, MVPP2_RXQ_STATUS_REG(rxq_id)); 1697 1698 return val & MVPP2_RXQ_OCCUPIED_MASK; 1699 } 1700 1701 /* Update Rx queue status with the number of occupied and available 1702 * Rx descriptor slots. 1703 */ 1704 static inline void 1705 mvpp2_rxq_status_update(struct mvpp2_port *port, int rxq_id, 1706 int used_count, int free_count) 1707 { 1708 /* Decrement the number of used descriptors and increment count 1709 * increment the number of free descriptors. 1710 */ 1711 u32 val = used_count | (free_count << MVPP2_RXQ_NUM_NEW_OFFSET); 1712 1713 mvpp2_write(port->priv, MVPP2_RXQ_STATUS_UPDATE_REG(rxq_id), val); 1714 } 1715 1716 /* Get pointer to next RX descriptor to be processed by SW */ 1717 static inline struct mvpp2_rx_desc * 1718 mvpp2_rxq_next_desc_get(struct mvpp2_rx_queue *rxq) 1719 { 1720 int rx_desc = rxq->next_desc_to_proc; 1721 1722 rxq->next_desc_to_proc = MVPP2_QUEUE_NEXT_DESC(rxq, rx_desc); 1723 prefetch(rxq->descs + rxq->next_desc_to_proc); 1724 return rxq->descs + rx_desc; 1725 } 1726 1727 /* Set rx queue offset */ 1728 static void mvpp2_rxq_offset_set(struct mvpp2_port *port, 1729 int prxq, int offset) 1730 { 1731 u32 val; 1732 1733 /* Convert offset from bytes to units of 32 bytes */ 1734 offset = offset >> 5; 1735 1736 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(prxq)); 1737 val &= ~MVPP2_RXQ_PACKET_OFFSET_MASK; 1738 1739 /* Offset is in */ 1740 val |= ((offset << MVPP2_RXQ_PACKET_OFFSET_OFFS) & 1741 MVPP2_RXQ_PACKET_OFFSET_MASK); 1742 1743 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(prxq), val); 1744 } 1745 1746 /* Tx descriptors helper methods */ 1747 1748 /* Get pointer to next Tx descriptor to be processed (send) by HW */ 1749 static struct mvpp2_tx_desc * 1750 mvpp2_txq_next_desc_get(struct mvpp2_tx_queue *txq) 1751 { 1752 int tx_desc = txq->next_desc_to_proc; 1753 1754 txq->next_desc_to_proc = MVPP2_QUEUE_NEXT_DESC(txq, tx_desc); 1755 return txq->descs + tx_desc; 1756 } 1757 1758 /* Update HW with number of aggregated Tx descriptors to be sent 1759 * 1760 * Called only from mvpp2_tx(), so migration is disabled, using 1761 * smp_processor_id() is OK. 1762 */ 1763 static void mvpp2_aggr_txq_pend_desc_add(struct mvpp2_port *port, int pending) 1764 { 1765 /* aggregated access - relevant TXQ number is written in TX desc */ 1766 mvpp2_thread_write(port->priv, 1767 mvpp2_cpu_to_thread(port->priv, smp_processor_id()), 1768 MVPP2_AGGR_TXQ_UPDATE_REG, pending); 1769 } 1770 1771 /* Check if there are enough free descriptors in aggregated txq. 1772 * If not, update the number of occupied descriptors and repeat the check. 1773 * 1774 * Called only from mvpp2_tx(), so migration is disabled, using 1775 * smp_processor_id() is OK. 1776 */ 1777 static int mvpp2_aggr_desc_num_check(struct mvpp2_port *port, 1778 struct mvpp2_tx_queue *aggr_txq, int num) 1779 { 1780 if ((aggr_txq->count + num) > MVPP2_AGGR_TXQ_SIZE) { 1781 /* Update number of occupied aggregated Tx descriptors */ 1782 unsigned int thread = 1783 mvpp2_cpu_to_thread(port->priv, smp_processor_id()); 1784 u32 val = mvpp2_read_relaxed(port->priv, 1785 MVPP2_AGGR_TXQ_STATUS_REG(thread)); 1786 1787 aggr_txq->count = val & MVPP2_AGGR_TXQ_PENDING_MASK; 1788 1789 if ((aggr_txq->count + num) > MVPP2_AGGR_TXQ_SIZE) 1790 return -ENOMEM; 1791 } 1792 return 0; 1793 } 1794 1795 /* Reserved Tx descriptors allocation request 1796 * 1797 * Called only from mvpp2_txq_reserved_desc_num_proc(), itself called 1798 * only by mvpp2_tx(), so migration is disabled, using 1799 * smp_processor_id() is OK. 1800 */ 1801 static int mvpp2_txq_alloc_reserved_desc(struct mvpp2_port *port, 1802 struct mvpp2_tx_queue *txq, int num) 1803 { 1804 unsigned int thread = mvpp2_cpu_to_thread(port->priv, smp_processor_id()); 1805 struct mvpp2 *priv = port->priv; 1806 u32 val; 1807 1808 val = (txq->id << MVPP2_TXQ_RSVD_REQ_Q_OFFSET) | num; 1809 mvpp2_thread_write_relaxed(priv, thread, MVPP2_TXQ_RSVD_REQ_REG, val); 1810 1811 val = mvpp2_thread_read_relaxed(priv, thread, MVPP2_TXQ_RSVD_RSLT_REG); 1812 1813 return val & MVPP2_TXQ_RSVD_RSLT_MASK; 1814 } 1815 1816 /* Check if there are enough reserved descriptors for transmission. 1817 * If not, request chunk of reserved descriptors and check again. 1818 */ 1819 static int mvpp2_txq_reserved_desc_num_proc(struct mvpp2_port *port, 1820 struct mvpp2_tx_queue *txq, 1821 struct mvpp2_txq_pcpu *txq_pcpu, 1822 int num) 1823 { 1824 int req, desc_count; 1825 unsigned int thread; 1826 1827 if (txq_pcpu->reserved_num >= num) 1828 return 0; 1829 1830 /* Not enough descriptors reserved! Update the reserved descriptor 1831 * count and check again. 1832 */ 1833 1834 desc_count = 0; 1835 /* Compute total of used descriptors */ 1836 for (thread = 0; thread < port->priv->nthreads; thread++) { 1837 struct mvpp2_txq_pcpu *txq_pcpu_aux; 1838 1839 txq_pcpu_aux = per_cpu_ptr(txq->pcpu, thread); 1840 desc_count += txq_pcpu_aux->count; 1841 desc_count += txq_pcpu_aux->reserved_num; 1842 } 1843 1844 req = max(MVPP2_CPU_DESC_CHUNK, num - txq_pcpu->reserved_num); 1845 desc_count += req; 1846 1847 if (desc_count > 1848 (txq->size - (MVPP2_MAX_THREADS * MVPP2_CPU_DESC_CHUNK))) 1849 return -ENOMEM; 1850 1851 txq_pcpu->reserved_num += mvpp2_txq_alloc_reserved_desc(port, txq, req); 1852 1853 /* OK, the descriptor could have been updated: check again. */ 1854 if (txq_pcpu->reserved_num < num) 1855 return -ENOMEM; 1856 return 0; 1857 } 1858 1859 /* Release the last allocated Tx descriptor. Useful to handle DMA 1860 * mapping failures in the Tx path. 1861 */ 1862 static void mvpp2_txq_desc_put(struct mvpp2_tx_queue *txq) 1863 { 1864 if (txq->next_desc_to_proc == 0) 1865 txq->next_desc_to_proc = txq->last_desc - 1; 1866 else 1867 txq->next_desc_to_proc--; 1868 } 1869 1870 /* Set Tx descriptors fields relevant for CSUM calculation */ 1871 static u32 mvpp2_txq_desc_csum(int l3_offs, __be16 l3_proto, 1872 int ip_hdr_len, int l4_proto) 1873 { 1874 u32 command; 1875 1876 /* fields: L3_offset, IP_hdrlen, L3_type, G_IPv4_chk, 1877 * G_L4_chk, L4_type required only for checksum calculation 1878 */ 1879 command = (l3_offs << MVPP2_TXD_L3_OFF_SHIFT); 1880 command |= (ip_hdr_len << MVPP2_TXD_IP_HLEN_SHIFT); 1881 command |= MVPP2_TXD_IP_CSUM_DISABLE; 1882 1883 if (l3_proto == htons(ETH_P_IP)) { 1884 command &= ~MVPP2_TXD_IP_CSUM_DISABLE; /* enable IPv4 csum */ 1885 command &= ~MVPP2_TXD_L3_IP6; /* enable IPv4 */ 1886 } else { 1887 command |= MVPP2_TXD_L3_IP6; /* enable IPv6 */ 1888 } 1889 1890 if (l4_proto == IPPROTO_TCP) { 1891 command &= ~MVPP2_TXD_L4_UDP; /* enable TCP */ 1892 command &= ~MVPP2_TXD_L4_CSUM_FRAG; /* generate L4 csum */ 1893 } else if (l4_proto == IPPROTO_UDP) { 1894 command |= MVPP2_TXD_L4_UDP; /* enable UDP */ 1895 command &= ~MVPP2_TXD_L4_CSUM_FRAG; /* generate L4 csum */ 1896 } else { 1897 command |= MVPP2_TXD_L4_CSUM_NOT; 1898 } 1899 1900 return command; 1901 } 1902 1903 /* Get number of sent descriptors and decrement counter. 1904 * The number of sent descriptors is returned. 1905 * Per-thread access 1906 * 1907 * Called only from mvpp2_txq_done(), called from mvpp2_tx() 1908 * (migration disabled) and from the TX completion tasklet (migration 1909 * disabled) so using smp_processor_id() is OK. 1910 */ 1911 static inline int mvpp2_txq_sent_desc_proc(struct mvpp2_port *port, 1912 struct mvpp2_tx_queue *txq) 1913 { 1914 u32 val; 1915 1916 /* Reading status reg resets transmitted descriptor counter */ 1917 val = mvpp2_thread_read_relaxed(port->priv, 1918 mvpp2_cpu_to_thread(port->priv, smp_processor_id()), 1919 MVPP2_TXQ_SENT_REG(txq->id)); 1920 1921 return (val & MVPP2_TRANSMITTED_COUNT_MASK) >> 1922 MVPP2_TRANSMITTED_COUNT_OFFSET; 1923 } 1924 1925 /* Called through on_each_cpu(), so runs on all CPUs, with migration 1926 * disabled, therefore using smp_processor_id() is OK. 1927 */ 1928 static void mvpp2_txq_sent_counter_clear(void *arg) 1929 { 1930 struct mvpp2_port *port = arg; 1931 int queue; 1932 1933 /* If the thread isn't used, don't do anything */ 1934 if (smp_processor_id() > port->priv->nthreads) 1935 return; 1936 1937 for (queue = 0; queue < port->ntxqs; queue++) { 1938 int id = port->txqs[queue]->id; 1939 1940 mvpp2_thread_read(port->priv, 1941 mvpp2_cpu_to_thread(port->priv, smp_processor_id()), 1942 MVPP2_TXQ_SENT_REG(id)); 1943 } 1944 } 1945 1946 /* Set max sizes for Tx queues */ 1947 static void mvpp2_txp_max_tx_size_set(struct mvpp2_port *port) 1948 { 1949 u32 val, size, mtu; 1950 int txq, tx_port_num; 1951 1952 mtu = port->pkt_size * 8; 1953 if (mtu > MVPP2_TXP_MTU_MAX) 1954 mtu = MVPP2_TXP_MTU_MAX; 1955 1956 /* WA for wrong Token bucket update: Set MTU value = 3*real MTU value */ 1957 mtu = 3 * mtu; 1958 1959 /* Indirect access to registers */ 1960 tx_port_num = mvpp2_egress_port(port); 1961 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num); 1962 1963 /* Set MTU */ 1964 val = mvpp2_read(port->priv, MVPP2_TXP_SCHED_MTU_REG); 1965 val &= ~MVPP2_TXP_MTU_MAX; 1966 val |= mtu; 1967 mvpp2_write(port->priv, MVPP2_TXP_SCHED_MTU_REG, val); 1968 1969 /* TXP token size and all TXQs token size must be larger that MTU */ 1970 val = mvpp2_read(port->priv, MVPP2_TXP_SCHED_TOKEN_SIZE_REG); 1971 size = val & MVPP2_TXP_TOKEN_SIZE_MAX; 1972 if (size < mtu) { 1973 size = mtu; 1974 val &= ~MVPP2_TXP_TOKEN_SIZE_MAX; 1975 val |= size; 1976 mvpp2_write(port->priv, MVPP2_TXP_SCHED_TOKEN_SIZE_REG, val); 1977 } 1978 1979 for (txq = 0; txq < port->ntxqs; txq++) { 1980 val = mvpp2_read(port->priv, 1981 MVPP2_TXQ_SCHED_TOKEN_SIZE_REG(txq)); 1982 size = val & MVPP2_TXQ_TOKEN_SIZE_MAX; 1983 1984 if (size < mtu) { 1985 size = mtu; 1986 val &= ~MVPP2_TXQ_TOKEN_SIZE_MAX; 1987 val |= size; 1988 mvpp2_write(port->priv, 1989 MVPP2_TXQ_SCHED_TOKEN_SIZE_REG(txq), 1990 val); 1991 } 1992 } 1993 } 1994 1995 /* Set the number of packets that will be received before Rx interrupt 1996 * will be generated by HW. 1997 */ 1998 static void mvpp2_rx_pkts_coal_set(struct mvpp2_port *port, 1999 struct mvpp2_rx_queue *rxq) 2000 { 2001 unsigned int thread = mvpp2_cpu_to_thread(port->priv, get_cpu()); 2002 2003 if (rxq->pkts_coal > MVPP2_OCCUPIED_THRESH_MASK) 2004 rxq->pkts_coal = MVPP2_OCCUPIED_THRESH_MASK; 2005 2006 mvpp2_thread_write(port->priv, thread, MVPP2_RXQ_NUM_REG, rxq->id); 2007 mvpp2_thread_write(port->priv, thread, MVPP2_RXQ_THRESH_REG, 2008 rxq->pkts_coal); 2009 2010 put_cpu(); 2011 } 2012 2013 /* For some reason in the LSP this is done on each CPU. Why ? */ 2014 static void mvpp2_tx_pkts_coal_set(struct mvpp2_port *port, 2015 struct mvpp2_tx_queue *txq) 2016 { 2017 unsigned int thread = mvpp2_cpu_to_thread(port->priv, get_cpu()); 2018 u32 val; 2019 2020 if (txq->done_pkts_coal > MVPP2_TXQ_THRESH_MASK) 2021 txq->done_pkts_coal = MVPP2_TXQ_THRESH_MASK; 2022 2023 val = (txq->done_pkts_coal << MVPP2_TXQ_THRESH_OFFSET); 2024 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_NUM_REG, txq->id); 2025 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_THRESH_REG, val); 2026 2027 put_cpu(); 2028 } 2029 2030 static u32 mvpp2_usec_to_cycles(u32 usec, unsigned long clk_hz) 2031 { 2032 u64 tmp = (u64)clk_hz * usec; 2033 2034 do_div(tmp, USEC_PER_SEC); 2035 2036 return tmp > U32_MAX ? U32_MAX : tmp; 2037 } 2038 2039 static u32 mvpp2_cycles_to_usec(u32 cycles, unsigned long clk_hz) 2040 { 2041 u64 tmp = (u64)cycles * USEC_PER_SEC; 2042 2043 do_div(tmp, clk_hz); 2044 2045 return tmp > U32_MAX ? U32_MAX : tmp; 2046 } 2047 2048 /* Set the time delay in usec before Rx interrupt */ 2049 static void mvpp2_rx_time_coal_set(struct mvpp2_port *port, 2050 struct mvpp2_rx_queue *rxq) 2051 { 2052 unsigned long freq = port->priv->tclk; 2053 u32 val = mvpp2_usec_to_cycles(rxq->time_coal, freq); 2054 2055 if (val > MVPP2_MAX_ISR_RX_THRESHOLD) { 2056 rxq->time_coal = 2057 mvpp2_cycles_to_usec(MVPP2_MAX_ISR_RX_THRESHOLD, freq); 2058 2059 /* re-evaluate to get actual register value */ 2060 val = mvpp2_usec_to_cycles(rxq->time_coal, freq); 2061 } 2062 2063 mvpp2_write(port->priv, MVPP2_ISR_RX_THRESHOLD_REG(rxq->id), val); 2064 } 2065 2066 static void mvpp2_tx_time_coal_set(struct mvpp2_port *port) 2067 { 2068 unsigned long freq = port->priv->tclk; 2069 u32 val = mvpp2_usec_to_cycles(port->tx_time_coal, freq); 2070 2071 if (val > MVPP2_MAX_ISR_TX_THRESHOLD) { 2072 port->tx_time_coal = 2073 mvpp2_cycles_to_usec(MVPP2_MAX_ISR_TX_THRESHOLD, freq); 2074 2075 /* re-evaluate to get actual register value */ 2076 val = mvpp2_usec_to_cycles(port->tx_time_coal, freq); 2077 } 2078 2079 mvpp2_write(port->priv, MVPP2_ISR_TX_THRESHOLD_REG(port->id), val); 2080 } 2081 2082 /* Free Tx queue skbuffs */ 2083 static void mvpp2_txq_bufs_free(struct mvpp2_port *port, 2084 struct mvpp2_tx_queue *txq, 2085 struct mvpp2_txq_pcpu *txq_pcpu, int num) 2086 { 2087 int i; 2088 2089 for (i = 0; i < num; i++) { 2090 struct mvpp2_txq_pcpu_buf *tx_buf = 2091 txq_pcpu->buffs + txq_pcpu->txq_get_index; 2092 2093 if (!IS_TSO_HEADER(txq_pcpu, tx_buf->dma)) 2094 dma_unmap_single(port->dev->dev.parent, tx_buf->dma, 2095 tx_buf->size, DMA_TO_DEVICE); 2096 if (tx_buf->skb) 2097 dev_kfree_skb_any(tx_buf->skb); 2098 2099 mvpp2_txq_inc_get(txq_pcpu); 2100 } 2101 } 2102 2103 static inline struct mvpp2_rx_queue *mvpp2_get_rx_queue(struct mvpp2_port *port, 2104 u32 cause) 2105 { 2106 int queue = fls(cause) - 1; 2107 2108 return port->rxqs[queue]; 2109 } 2110 2111 static inline struct mvpp2_tx_queue *mvpp2_get_tx_queue(struct mvpp2_port *port, 2112 u32 cause) 2113 { 2114 int queue = fls(cause) - 1; 2115 2116 return port->txqs[queue]; 2117 } 2118 2119 /* Handle end of transmission */ 2120 static void mvpp2_txq_done(struct mvpp2_port *port, struct mvpp2_tx_queue *txq, 2121 struct mvpp2_txq_pcpu *txq_pcpu) 2122 { 2123 struct netdev_queue *nq = netdev_get_tx_queue(port->dev, txq->log_id); 2124 int tx_done; 2125 2126 if (txq_pcpu->thread != mvpp2_cpu_to_thread(port->priv, smp_processor_id())) 2127 netdev_err(port->dev, "wrong cpu on the end of Tx processing\n"); 2128 2129 tx_done = mvpp2_txq_sent_desc_proc(port, txq); 2130 if (!tx_done) 2131 return; 2132 mvpp2_txq_bufs_free(port, txq, txq_pcpu, tx_done); 2133 2134 txq_pcpu->count -= tx_done; 2135 2136 if (netif_tx_queue_stopped(nq)) 2137 if (txq_pcpu->count <= txq_pcpu->wake_threshold) 2138 netif_tx_wake_queue(nq); 2139 } 2140 2141 static unsigned int mvpp2_tx_done(struct mvpp2_port *port, u32 cause, 2142 unsigned int thread) 2143 { 2144 struct mvpp2_tx_queue *txq; 2145 struct mvpp2_txq_pcpu *txq_pcpu; 2146 unsigned int tx_todo = 0; 2147 2148 while (cause) { 2149 txq = mvpp2_get_tx_queue(port, cause); 2150 if (!txq) 2151 break; 2152 2153 txq_pcpu = per_cpu_ptr(txq->pcpu, thread); 2154 2155 if (txq_pcpu->count) { 2156 mvpp2_txq_done(port, txq, txq_pcpu); 2157 tx_todo += txq_pcpu->count; 2158 } 2159 2160 cause &= ~(1 << txq->log_id); 2161 } 2162 return tx_todo; 2163 } 2164 2165 /* Rx/Tx queue initialization/cleanup methods */ 2166 2167 /* Allocate and initialize descriptors for aggr TXQ */ 2168 static int mvpp2_aggr_txq_init(struct platform_device *pdev, 2169 struct mvpp2_tx_queue *aggr_txq, 2170 unsigned int thread, struct mvpp2 *priv) 2171 { 2172 u32 txq_dma; 2173 2174 /* Allocate memory for TX descriptors */ 2175 aggr_txq->descs = dma_alloc_coherent(&pdev->dev, 2176 MVPP2_AGGR_TXQ_SIZE * MVPP2_DESC_ALIGNED_SIZE, 2177 &aggr_txq->descs_dma, GFP_KERNEL); 2178 if (!aggr_txq->descs) 2179 return -ENOMEM; 2180 2181 aggr_txq->last_desc = MVPP2_AGGR_TXQ_SIZE - 1; 2182 2183 /* Aggr TXQ no reset WA */ 2184 aggr_txq->next_desc_to_proc = mvpp2_read(priv, 2185 MVPP2_AGGR_TXQ_INDEX_REG(thread)); 2186 2187 /* Set Tx descriptors queue starting address indirect 2188 * access 2189 */ 2190 if (priv->hw_version == MVPP21) 2191 txq_dma = aggr_txq->descs_dma; 2192 else 2193 txq_dma = aggr_txq->descs_dma >> 2194 MVPP22_AGGR_TXQ_DESC_ADDR_OFFS; 2195 2196 mvpp2_write(priv, MVPP2_AGGR_TXQ_DESC_ADDR_REG(thread), txq_dma); 2197 mvpp2_write(priv, MVPP2_AGGR_TXQ_DESC_SIZE_REG(thread), 2198 MVPP2_AGGR_TXQ_SIZE); 2199 2200 return 0; 2201 } 2202 2203 /* Create a specified Rx queue */ 2204 static int mvpp2_rxq_init(struct mvpp2_port *port, 2205 struct mvpp2_rx_queue *rxq) 2206 2207 { 2208 unsigned int thread; 2209 u32 rxq_dma; 2210 2211 rxq->size = port->rx_ring_size; 2212 2213 /* Allocate memory for RX descriptors */ 2214 rxq->descs = dma_alloc_coherent(port->dev->dev.parent, 2215 rxq->size * MVPP2_DESC_ALIGNED_SIZE, 2216 &rxq->descs_dma, GFP_KERNEL); 2217 if (!rxq->descs) 2218 return -ENOMEM; 2219 2220 rxq->last_desc = rxq->size - 1; 2221 2222 /* Zero occupied and non-occupied counters - direct access */ 2223 mvpp2_write(port->priv, MVPP2_RXQ_STATUS_REG(rxq->id), 0); 2224 2225 /* Set Rx descriptors queue starting address - indirect access */ 2226 thread = mvpp2_cpu_to_thread(port->priv, get_cpu()); 2227 mvpp2_thread_write(port->priv, thread, MVPP2_RXQ_NUM_REG, rxq->id); 2228 if (port->priv->hw_version == MVPP21) 2229 rxq_dma = rxq->descs_dma; 2230 else 2231 rxq_dma = rxq->descs_dma >> MVPP22_DESC_ADDR_OFFS; 2232 mvpp2_thread_write(port->priv, thread, MVPP2_RXQ_DESC_ADDR_REG, rxq_dma); 2233 mvpp2_thread_write(port->priv, thread, MVPP2_RXQ_DESC_SIZE_REG, rxq->size); 2234 mvpp2_thread_write(port->priv, thread, MVPP2_RXQ_INDEX_REG, 0); 2235 put_cpu(); 2236 2237 /* Set Offset */ 2238 mvpp2_rxq_offset_set(port, rxq->id, NET_SKB_PAD); 2239 2240 /* Set coalescing pkts and time */ 2241 mvpp2_rx_pkts_coal_set(port, rxq); 2242 mvpp2_rx_time_coal_set(port, rxq); 2243 2244 /* Add number of descriptors ready for receiving packets */ 2245 mvpp2_rxq_status_update(port, rxq->id, 0, rxq->size); 2246 2247 return 0; 2248 } 2249 2250 /* Push packets received by the RXQ to BM pool */ 2251 static void mvpp2_rxq_drop_pkts(struct mvpp2_port *port, 2252 struct mvpp2_rx_queue *rxq) 2253 { 2254 int rx_received, i; 2255 2256 rx_received = mvpp2_rxq_received(port, rxq->id); 2257 if (!rx_received) 2258 return; 2259 2260 for (i = 0; i < rx_received; i++) { 2261 struct mvpp2_rx_desc *rx_desc = mvpp2_rxq_next_desc_get(rxq); 2262 u32 status = mvpp2_rxdesc_status_get(port, rx_desc); 2263 int pool; 2264 2265 pool = (status & MVPP2_RXD_BM_POOL_ID_MASK) >> 2266 MVPP2_RXD_BM_POOL_ID_OFFS; 2267 2268 mvpp2_bm_pool_put(port, pool, 2269 mvpp2_rxdesc_dma_addr_get(port, rx_desc), 2270 mvpp2_rxdesc_cookie_get(port, rx_desc)); 2271 } 2272 mvpp2_rxq_status_update(port, rxq->id, rx_received, rx_received); 2273 } 2274 2275 /* Cleanup Rx queue */ 2276 static void mvpp2_rxq_deinit(struct mvpp2_port *port, 2277 struct mvpp2_rx_queue *rxq) 2278 { 2279 unsigned int thread; 2280 2281 mvpp2_rxq_drop_pkts(port, rxq); 2282 2283 if (rxq->descs) 2284 dma_free_coherent(port->dev->dev.parent, 2285 rxq->size * MVPP2_DESC_ALIGNED_SIZE, 2286 rxq->descs, 2287 rxq->descs_dma); 2288 2289 rxq->descs = NULL; 2290 rxq->last_desc = 0; 2291 rxq->next_desc_to_proc = 0; 2292 rxq->descs_dma = 0; 2293 2294 /* Clear Rx descriptors queue starting address and size; 2295 * free descriptor number 2296 */ 2297 mvpp2_write(port->priv, MVPP2_RXQ_STATUS_REG(rxq->id), 0); 2298 thread = mvpp2_cpu_to_thread(port->priv, get_cpu()); 2299 mvpp2_thread_write(port->priv, thread, MVPP2_RXQ_NUM_REG, rxq->id); 2300 mvpp2_thread_write(port->priv, thread, MVPP2_RXQ_DESC_ADDR_REG, 0); 2301 mvpp2_thread_write(port->priv, thread, MVPP2_RXQ_DESC_SIZE_REG, 0); 2302 put_cpu(); 2303 } 2304 2305 /* Create and initialize a Tx queue */ 2306 static int mvpp2_txq_init(struct mvpp2_port *port, 2307 struct mvpp2_tx_queue *txq) 2308 { 2309 u32 val; 2310 unsigned int thread; 2311 int desc, desc_per_txq, tx_port_num; 2312 struct mvpp2_txq_pcpu *txq_pcpu; 2313 2314 txq->size = port->tx_ring_size; 2315 2316 /* Allocate memory for Tx descriptors */ 2317 txq->descs = dma_alloc_coherent(port->dev->dev.parent, 2318 txq->size * MVPP2_DESC_ALIGNED_SIZE, 2319 &txq->descs_dma, GFP_KERNEL); 2320 if (!txq->descs) 2321 return -ENOMEM; 2322 2323 txq->last_desc = txq->size - 1; 2324 2325 /* Set Tx descriptors queue starting address - indirect access */ 2326 thread = mvpp2_cpu_to_thread(port->priv, get_cpu()); 2327 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_NUM_REG, txq->id); 2328 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_DESC_ADDR_REG, 2329 txq->descs_dma); 2330 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_DESC_SIZE_REG, 2331 txq->size & MVPP2_TXQ_DESC_SIZE_MASK); 2332 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_INDEX_REG, 0); 2333 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_RSVD_CLR_REG, 2334 txq->id << MVPP2_TXQ_RSVD_CLR_OFFSET); 2335 val = mvpp2_thread_read(port->priv, thread, MVPP2_TXQ_PENDING_REG); 2336 val &= ~MVPP2_TXQ_PENDING_MASK; 2337 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_PENDING_REG, val); 2338 2339 /* Calculate base address in prefetch buffer. We reserve 16 descriptors 2340 * for each existing TXQ. 2341 * TCONTS for PON port must be continuous from 0 to MVPP2_MAX_TCONT 2342 * GBE ports assumed to be continuous from 0 to MVPP2_MAX_PORTS 2343 */ 2344 desc_per_txq = 16; 2345 desc = (port->id * MVPP2_MAX_TXQ * desc_per_txq) + 2346 (txq->log_id * desc_per_txq); 2347 2348 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_PREF_BUF_REG, 2349 MVPP2_PREF_BUF_PTR(desc) | MVPP2_PREF_BUF_SIZE_16 | 2350 MVPP2_PREF_BUF_THRESH(desc_per_txq / 2)); 2351 put_cpu(); 2352 2353 /* WRR / EJP configuration - indirect access */ 2354 tx_port_num = mvpp2_egress_port(port); 2355 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num); 2356 2357 val = mvpp2_read(port->priv, MVPP2_TXQ_SCHED_REFILL_REG(txq->log_id)); 2358 val &= ~MVPP2_TXQ_REFILL_PERIOD_ALL_MASK; 2359 val |= MVPP2_TXQ_REFILL_PERIOD_MASK(1); 2360 val |= MVPP2_TXQ_REFILL_TOKENS_ALL_MASK; 2361 mvpp2_write(port->priv, MVPP2_TXQ_SCHED_REFILL_REG(txq->log_id), val); 2362 2363 val = MVPP2_TXQ_TOKEN_SIZE_MAX; 2364 mvpp2_write(port->priv, MVPP2_TXQ_SCHED_TOKEN_SIZE_REG(txq->log_id), 2365 val); 2366 2367 for (thread = 0; thread < port->priv->nthreads; thread++) { 2368 txq_pcpu = per_cpu_ptr(txq->pcpu, thread); 2369 txq_pcpu->size = txq->size; 2370 txq_pcpu->buffs = kmalloc_array(txq_pcpu->size, 2371 sizeof(*txq_pcpu->buffs), 2372 GFP_KERNEL); 2373 if (!txq_pcpu->buffs) 2374 return -ENOMEM; 2375 2376 txq_pcpu->count = 0; 2377 txq_pcpu->reserved_num = 0; 2378 txq_pcpu->txq_put_index = 0; 2379 txq_pcpu->txq_get_index = 0; 2380 txq_pcpu->tso_headers = NULL; 2381 2382 txq_pcpu->stop_threshold = txq->size - MVPP2_MAX_SKB_DESCS; 2383 txq_pcpu->wake_threshold = txq_pcpu->stop_threshold / 2; 2384 2385 txq_pcpu->tso_headers = 2386 dma_alloc_coherent(port->dev->dev.parent, 2387 txq_pcpu->size * TSO_HEADER_SIZE, 2388 &txq_pcpu->tso_headers_dma, 2389 GFP_KERNEL); 2390 if (!txq_pcpu->tso_headers) 2391 return -ENOMEM; 2392 } 2393 2394 return 0; 2395 } 2396 2397 /* Free allocated TXQ resources */ 2398 static void mvpp2_txq_deinit(struct mvpp2_port *port, 2399 struct mvpp2_tx_queue *txq) 2400 { 2401 struct mvpp2_txq_pcpu *txq_pcpu; 2402 unsigned int thread; 2403 2404 for (thread = 0; thread < port->priv->nthreads; thread++) { 2405 txq_pcpu = per_cpu_ptr(txq->pcpu, thread); 2406 kfree(txq_pcpu->buffs); 2407 2408 if (txq_pcpu->tso_headers) 2409 dma_free_coherent(port->dev->dev.parent, 2410 txq_pcpu->size * TSO_HEADER_SIZE, 2411 txq_pcpu->tso_headers, 2412 txq_pcpu->tso_headers_dma); 2413 2414 txq_pcpu->tso_headers = NULL; 2415 } 2416 2417 if (txq->descs) 2418 dma_free_coherent(port->dev->dev.parent, 2419 txq->size * MVPP2_DESC_ALIGNED_SIZE, 2420 txq->descs, txq->descs_dma); 2421 2422 txq->descs = NULL; 2423 txq->last_desc = 0; 2424 txq->next_desc_to_proc = 0; 2425 txq->descs_dma = 0; 2426 2427 /* Set minimum bandwidth for disabled TXQs */ 2428 mvpp2_write(port->priv, MVPP2_TXQ_SCHED_TOKEN_CNTR_REG(txq->log_id), 0); 2429 2430 /* Set Tx descriptors queue starting address and size */ 2431 thread = mvpp2_cpu_to_thread(port->priv, get_cpu()); 2432 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_NUM_REG, txq->id); 2433 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_DESC_ADDR_REG, 0); 2434 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_DESC_SIZE_REG, 0); 2435 put_cpu(); 2436 } 2437 2438 /* Cleanup Tx ports */ 2439 static void mvpp2_txq_clean(struct mvpp2_port *port, struct mvpp2_tx_queue *txq) 2440 { 2441 struct mvpp2_txq_pcpu *txq_pcpu; 2442 int delay, pending; 2443 unsigned int thread = mvpp2_cpu_to_thread(port->priv, get_cpu()); 2444 u32 val; 2445 2446 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_NUM_REG, txq->id); 2447 val = mvpp2_thread_read(port->priv, thread, MVPP2_TXQ_PREF_BUF_REG); 2448 val |= MVPP2_TXQ_DRAIN_EN_MASK; 2449 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_PREF_BUF_REG, val); 2450 2451 /* The napi queue has been stopped so wait for all packets 2452 * to be transmitted. 2453 */ 2454 delay = 0; 2455 do { 2456 if (delay >= MVPP2_TX_PENDING_TIMEOUT_MSEC) { 2457 netdev_warn(port->dev, 2458 "port %d: cleaning queue %d timed out\n", 2459 port->id, txq->log_id); 2460 break; 2461 } 2462 mdelay(1); 2463 delay++; 2464 2465 pending = mvpp2_thread_read(port->priv, thread, 2466 MVPP2_TXQ_PENDING_REG); 2467 pending &= MVPP2_TXQ_PENDING_MASK; 2468 } while (pending); 2469 2470 val &= ~MVPP2_TXQ_DRAIN_EN_MASK; 2471 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_PREF_BUF_REG, val); 2472 put_cpu(); 2473 2474 for (thread = 0; thread < port->priv->nthreads; thread++) { 2475 txq_pcpu = per_cpu_ptr(txq->pcpu, thread); 2476 2477 /* Release all packets */ 2478 mvpp2_txq_bufs_free(port, txq, txq_pcpu, txq_pcpu->count); 2479 2480 /* Reset queue */ 2481 txq_pcpu->count = 0; 2482 txq_pcpu->txq_put_index = 0; 2483 txq_pcpu->txq_get_index = 0; 2484 } 2485 } 2486 2487 /* Cleanup all Tx queues */ 2488 static void mvpp2_cleanup_txqs(struct mvpp2_port *port) 2489 { 2490 struct mvpp2_tx_queue *txq; 2491 int queue; 2492 u32 val; 2493 2494 val = mvpp2_read(port->priv, MVPP2_TX_PORT_FLUSH_REG); 2495 2496 /* Reset Tx ports and delete Tx queues */ 2497 val |= MVPP2_TX_PORT_FLUSH_MASK(port->id); 2498 mvpp2_write(port->priv, MVPP2_TX_PORT_FLUSH_REG, val); 2499 2500 for (queue = 0; queue < port->ntxqs; queue++) { 2501 txq = port->txqs[queue]; 2502 mvpp2_txq_clean(port, txq); 2503 mvpp2_txq_deinit(port, txq); 2504 } 2505 2506 on_each_cpu(mvpp2_txq_sent_counter_clear, port, 1); 2507 2508 val &= ~MVPP2_TX_PORT_FLUSH_MASK(port->id); 2509 mvpp2_write(port->priv, MVPP2_TX_PORT_FLUSH_REG, val); 2510 } 2511 2512 /* Cleanup all Rx queues */ 2513 static void mvpp2_cleanup_rxqs(struct mvpp2_port *port) 2514 { 2515 int queue; 2516 2517 for (queue = 0; queue < port->nrxqs; queue++) 2518 mvpp2_rxq_deinit(port, port->rxqs[queue]); 2519 } 2520 2521 /* Init all Rx queues for port */ 2522 static int mvpp2_setup_rxqs(struct mvpp2_port *port) 2523 { 2524 int queue, err; 2525 2526 for (queue = 0; queue < port->nrxqs; queue++) { 2527 err = mvpp2_rxq_init(port, port->rxqs[queue]); 2528 if (err) 2529 goto err_cleanup; 2530 } 2531 return 0; 2532 2533 err_cleanup: 2534 mvpp2_cleanup_rxqs(port); 2535 return err; 2536 } 2537 2538 /* Init all tx queues for port */ 2539 static int mvpp2_setup_txqs(struct mvpp2_port *port) 2540 { 2541 struct mvpp2_tx_queue *txq; 2542 int queue, err, cpu; 2543 2544 for (queue = 0; queue < port->ntxqs; queue++) { 2545 txq = port->txqs[queue]; 2546 err = mvpp2_txq_init(port, txq); 2547 if (err) 2548 goto err_cleanup; 2549 2550 /* Assign this queue to a CPU */ 2551 cpu = queue % num_present_cpus(); 2552 netif_set_xps_queue(port->dev, cpumask_of(cpu), queue); 2553 } 2554 2555 if (port->has_tx_irqs) { 2556 mvpp2_tx_time_coal_set(port); 2557 for (queue = 0; queue < port->ntxqs; queue++) { 2558 txq = port->txqs[queue]; 2559 mvpp2_tx_pkts_coal_set(port, txq); 2560 } 2561 } 2562 2563 on_each_cpu(mvpp2_txq_sent_counter_clear, port, 1); 2564 return 0; 2565 2566 err_cleanup: 2567 mvpp2_cleanup_txqs(port); 2568 return err; 2569 } 2570 2571 /* The callback for per-port interrupt */ 2572 static irqreturn_t mvpp2_isr(int irq, void *dev_id) 2573 { 2574 struct mvpp2_queue_vector *qv = dev_id; 2575 2576 mvpp2_qvec_interrupt_disable(qv); 2577 2578 napi_schedule(&qv->napi); 2579 2580 return IRQ_HANDLED; 2581 } 2582 2583 /* Per-port interrupt for link status changes */ 2584 static irqreturn_t mvpp2_link_status_isr(int irq, void *dev_id) 2585 { 2586 struct mvpp2_port *port = (struct mvpp2_port *)dev_id; 2587 struct net_device *dev = port->dev; 2588 bool event = false, link = false; 2589 u32 val; 2590 2591 mvpp22_gop_mask_irq(port); 2592 2593 if (port->gop_id == 0 && mvpp2_is_xlg(port->phy_interface)) { 2594 val = readl(port->base + MVPP22_XLG_INT_STAT); 2595 if (val & MVPP22_XLG_INT_STAT_LINK) { 2596 event = true; 2597 val = readl(port->base + MVPP22_XLG_STATUS); 2598 if (val & MVPP22_XLG_STATUS_LINK_UP) 2599 link = true; 2600 } 2601 } else if (phy_interface_mode_is_rgmii(port->phy_interface) || 2602 phy_interface_mode_is_8023z(port->phy_interface) || 2603 port->phy_interface == PHY_INTERFACE_MODE_SGMII) { 2604 val = readl(port->base + MVPP22_GMAC_INT_STAT); 2605 if (val & MVPP22_GMAC_INT_STAT_LINK) { 2606 event = true; 2607 val = readl(port->base + MVPP2_GMAC_STATUS0); 2608 if (val & MVPP2_GMAC_STATUS0_LINK_UP) 2609 link = true; 2610 } 2611 } 2612 2613 if (port->phylink) { 2614 phylink_mac_change(port->phylink, link); 2615 goto handled; 2616 } 2617 2618 if (!netif_running(dev) || !event) 2619 goto handled; 2620 2621 if (link) { 2622 mvpp2_interrupts_enable(port); 2623 2624 mvpp2_egress_enable(port); 2625 mvpp2_ingress_enable(port); 2626 netif_carrier_on(dev); 2627 netif_tx_wake_all_queues(dev); 2628 } else { 2629 netif_tx_stop_all_queues(dev); 2630 netif_carrier_off(dev); 2631 mvpp2_ingress_disable(port); 2632 mvpp2_egress_disable(port); 2633 2634 mvpp2_interrupts_disable(port); 2635 } 2636 2637 handled: 2638 mvpp22_gop_unmask_irq(port); 2639 return IRQ_HANDLED; 2640 } 2641 2642 static void mvpp2_timer_set(struct mvpp2_port_pcpu *port_pcpu) 2643 { 2644 ktime_t interval; 2645 2646 if (!port_pcpu->timer_scheduled) { 2647 port_pcpu->timer_scheduled = true; 2648 interval = MVPP2_TXDONE_HRTIMER_PERIOD_NS; 2649 hrtimer_start(&port_pcpu->tx_done_timer, interval, 2650 HRTIMER_MODE_REL_PINNED); 2651 } 2652 } 2653 2654 static void mvpp2_tx_proc_cb(unsigned long data) 2655 { 2656 struct net_device *dev = (struct net_device *)data; 2657 struct mvpp2_port *port = netdev_priv(dev); 2658 struct mvpp2_port_pcpu *port_pcpu; 2659 unsigned int tx_todo, cause; 2660 2661 port_pcpu = per_cpu_ptr(port->pcpu, 2662 mvpp2_cpu_to_thread(port->priv, smp_processor_id())); 2663 2664 if (!netif_running(dev)) 2665 return; 2666 port_pcpu->timer_scheduled = false; 2667 2668 /* Process all the Tx queues */ 2669 cause = (1 << port->ntxqs) - 1; 2670 tx_todo = mvpp2_tx_done(port, cause, 2671 mvpp2_cpu_to_thread(port->priv, smp_processor_id())); 2672 2673 /* Set the timer in case not all the packets were processed */ 2674 if (tx_todo) 2675 mvpp2_timer_set(port_pcpu); 2676 } 2677 2678 static enum hrtimer_restart mvpp2_hr_timer_cb(struct hrtimer *timer) 2679 { 2680 struct mvpp2_port_pcpu *port_pcpu = container_of(timer, 2681 struct mvpp2_port_pcpu, 2682 tx_done_timer); 2683 2684 tasklet_schedule(&port_pcpu->tx_done_tasklet); 2685 2686 return HRTIMER_NORESTART; 2687 } 2688 2689 /* Main RX/TX processing routines */ 2690 2691 /* Display more error info */ 2692 static void mvpp2_rx_error(struct mvpp2_port *port, 2693 struct mvpp2_rx_desc *rx_desc) 2694 { 2695 u32 status = mvpp2_rxdesc_status_get(port, rx_desc); 2696 size_t sz = mvpp2_rxdesc_size_get(port, rx_desc); 2697 char *err_str = NULL; 2698 2699 switch (status & MVPP2_RXD_ERR_CODE_MASK) { 2700 case MVPP2_RXD_ERR_CRC: 2701 err_str = "crc"; 2702 break; 2703 case MVPP2_RXD_ERR_OVERRUN: 2704 err_str = "overrun"; 2705 break; 2706 case MVPP2_RXD_ERR_RESOURCE: 2707 err_str = "resource"; 2708 break; 2709 } 2710 if (err_str && net_ratelimit()) 2711 netdev_err(port->dev, 2712 "bad rx status %08x (%s error), size=%zu\n", 2713 status, err_str, sz); 2714 } 2715 2716 /* Handle RX checksum offload */ 2717 static void mvpp2_rx_csum(struct mvpp2_port *port, u32 status, 2718 struct sk_buff *skb) 2719 { 2720 if (((status & MVPP2_RXD_L3_IP4) && 2721 !(status & MVPP2_RXD_IP4_HEADER_ERR)) || 2722 (status & MVPP2_RXD_L3_IP6)) 2723 if (((status & MVPP2_RXD_L4_UDP) || 2724 (status & MVPP2_RXD_L4_TCP)) && 2725 (status & MVPP2_RXD_L4_CSUM_OK)) { 2726 skb->csum = 0; 2727 skb->ip_summed = CHECKSUM_UNNECESSARY; 2728 return; 2729 } 2730 2731 skb->ip_summed = CHECKSUM_NONE; 2732 } 2733 2734 /* Reuse skb if possible, or allocate a new skb and add it to BM pool */ 2735 static int mvpp2_rx_refill(struct mvpp2_port *port, 2736 struct mvpp2_bm_pool *bm_pool, int pool) 2737 { 2738 dma_addr_t dma_addr; 2739 phys_addr_t phys_addr; 2740 void *buf; 2741 2742 /* No recycle or too many buffers are in use, so allocate a new skb */ 2743 buf = mvpp2_buf_alloc(port, bm_pool, &dma_addr, &phys_addr, 2744 GFP_ATOMIC); 2745 if (!buf) 2746 return -ENOMEM; 2747 2748 mvpp2_bm_pool_put(port, pool, dma_addr, phys_addr); 2749 2750 return 0; 2751 } 2752 2753 /* Handle tx checksum */ 2754 static u32 mvpp2_skb_tx_csum(struct mvpp2_port *port, struct sk_buff *skb) 2755 { 2756 if (skb->ip_summed == CHECKSUM_PARTIAL) { 2757 int ip_hdr_len = 0; 2758 u8 l4_proto; 2759 __be16 l3_proto = vlan_get_protocol(skb); 2760 2761 if (l3_proto == htons(ETH_P_IP)) { 2762 struct iphdr *ip4h = ip_hdr(skb); 2763 2764 /* Calculate IPv4 checksum and L4 checksum */ 2765 ip_hdr_len = ip4h->ihl; 2766 l4_proto = ip4h->protocol; 2767 } else if (l3_proto == htons(ETH_P_IPV6)) { 2768 struct ipv6hdr *ip6h = ipv6_hdr(skb); 2769 2770 /* Read l4_protocol from one of IPv6 extra headers */ 2771 if (skb_network_header_len(skb) > 0) 2772 ip_hdr_len = (skb_network_header_len(skb) >> 2); 2773 l4_proto = ip6h->nexthdr; 2774 } else { 2775 return MVPP2_TXD_L4_CSUM_NOT; 2776 } 2777 2778 return mvpp2_txq_desc_csum(skb_network_offset(skb), 2779 l3_proto, ip_hdr_len, l4_proto); 2780 } 2781 2782 return MVPP2_TXD_L4_CSUM_NOT | MVPP2_TXD_IP_CSUM_DISABLE; 2783 } 2784 2785 /* Main rx processing */ 2786 static int mvpp2_rx(struct mvpp2_port *port, struct napi_struct *napi, 2787 int rx_todo, struct mvpp2_rx_queue *rxq) 2788 { 2789 struct net_device *dev = port->dev; 2790 int rx_received; 2791 int rx_done = 0; 2792 u32 rcvd_pkts = 0; 2793 u32 rcvd_bytes = 0; 2794 2795 /* Get number of received packets and clamp the to-do */ 2796 rx_received = mvpp2_rxq_received(port, rxq->id); 2797 if (rx_todo > rx_received) 2798 rx_todo = rx_received; 2799 2800 while (rx_done < rx_todo) { 2801 struct mvpp2_rx_desc *rx_desc = mvpp2_rxq_next_desc_get(rxq); 2802 struct mvpp2_bm_pool *bm_pool; 2803 struct sk_buff *skb; 2804 unsigned int frag_size; 2805 dma_addr_t dma_addr; 2806 phys_addr_t phys_addr; 2807 u32 rx_status; 2808 int pool, rx_bytes, err; 2809 void *data; 2810 2811 rx_done++; 2812 rx_status = mvpp2_rxdesc_status_get(port, rx_desc); 2813 rx_bytes = mvpp2_rxdesc_size_get(port, rx_desc); 2814 rx_bytes -= MVPP2_MH_SIZE; 2815 dma_addr = mvpp2_rxdesc_dma_addr_get(port, rx_desc); 2816 phys_addr = mvpp2_rxdesc_cookie_get(port, rx_desc); 2817 data = (void *)phys_to_virt(phys_addr); 2818 2819 pool = (rx_status & MVPP2_RXD_BM_POOL_ID_MASK) >> 2820 MVPP2_RXD_BM_POOL_ID_OFFS; 2821 bm_pool = &port->priv->bm_pools[pool]; 2822 2823 /* In case of an error, release the requested buffer pointer 2824 * to the Buffer Manager. This request process is controlled 2825 * by the hardware, and the information about the buffer is 2826 * comprised by the RX descriptor. 2827 */ 2828 if (rx_status & MVPP2_RXD_ERR_SUMMARY) { 2829 err_drop_frame: 2830 dev->stats.rx_errors++; 2831 mvpp2_rx_error(port, rx_desc); 2832 /* Return the buffer to the pool */ 2833 mvpp2_bm_pool_put(port, pool, dma_addr, phys_addr); 2834 continue; 2835 } 2836 2837 if (bm_pool->frag_size > PAGE_SIZE) 2838 frag_size = 0; 2839 else 2840 frag_size = bm_pool->frag_size; 2841 2842 skb = build_skb(data, frag_size); 2843 if (!skb) { 2844 netdev_warn(port->dev, "skb build failed\n"); 2845 goto err_drop_frame; 2846 } 2847 2848 err = mvpp2_rx_refill(port, bm_pool, pool); 2849 if (err) { 2850 netdev_err(port->dev, "failed to refill BM pools\n"); 2851 goto err_drop_frame; 2852 } 2853 2854 dma_unmap_single(dev->dev.parent, dma_addr, 2855 bm_pool->buf_size, DMA_FROM_DEVICE); 2856 2857 rcvd_pkts++; 2858 rcvd_bytes += rx_bytes; 2859 2860 skb_reserve(skb, MVPP2_MH_SIZE + NET_SKB_PAD); 2861 skb_put(skb, rx_bytes); 2862 skb->protocol = eth_type_trans(skb, dev); 2863 mvpp2_rx_csum(port, rx_status, skb); 2864 2865 napi_gro_receive(napi, skb); 2866 } 2867 2868 if (rcvd_pkts) { 2869 struct mvpp2_pcpu_stats *stats = this_cpu_ptr(port->stats); 2870 2871 u64_stats_update_begin(&stats->syncp); 2872 stats->rx_packets += rcvd_pkts; 2873 stats->rx_bytes += rcvd_bytes; 2874 u64_stats_update_end(&stats->syncp); 2875 } 2876 2877 /* Update Rx queue management counters */ 2878 wmb(); 2879 mvpp2_rxq_status_update(port, rxq->id, rx_done, rx_done); 2880 2881 return rx_todo; 2882 } 2883 2884 static inline void 2885 tx_desc_unmap_put(struct mvpp2_port *port, struct mvpp2_tx_queue *txq, 2886 struct mvpp2_tx_desc *desc) 2887 { 2888 unsigned int thread = mvpp2_cpu_to_thread(port->priv, smp_processor_id()); 2889 struct mvpp2_txq_pcpu *txq_pcpu = per_cpu_ptr(txq->pcpu, thread); 2890 2891 dma_addr_t buf_dma_addr = 2892 mvpp2_txdesc_dma_addr_get(port, desc); 2893 size_t buf_sz = 2894 mvpp2_txdesc_size_get(port, desc); 2895 if (!IS_TSO_HEADER(txq_pcpu, buf_dma_addr)) 2896 dma_unmap_single(port->dev->dev.parent, buf_dma_addr, 2897 buf_sz, DMA_TO_DEVICE); 2898 mvpp2_txq_desc_put(txq); 2899 } 2900 2901 /* Handle tx fragmentation processing */ 2902 static int mvpp2_tx_frag_process(struct mvpp2_port *port, struct sk_buff *skb, 2903 struct mvpp2_tx_queue *aggr_txq, 2904 struct mvpp2_tx_queue *txq) 2905 { 2906 unsigned int thread = mvpp2_cpu_to_thread(port->priv, smp_processor_id()); 2907 struct mvpp2_txq_pcpu *txq_pcpu = per_cpu_ptr(txq->pcpu, thread); 2908 struct mvpp2_tx_desc *tx_desc; 2909 int i; 2910 dma_addr_t buf_dma_addr; 2911 2912 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { 2913 skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 2914 void *addr = skb_frag_address(frag); 2915 2916 tx_desc = mvpp2_txq_next_desc_get(aggr_txq); 2917 mvpp2_txdesc_txq_set(port, tx_desc, txq->id); 2918 mvpp2_txdesc_size_set(port, tx_desc, skb_frag_size(frag)); 2919 2920 buf_dma_addr = dma_map_single(port->dev->dev.parent, addr, 2921 skb_frag_size(frag), 2922 DMA_TO_DEVICE); 2923 if (dma_mapping_error(port->dev->dev.parent, buf_dma_addr)) { 2924 mvpp2_txq_desc_put(txq); 2925 goto cleanup; 2926 } 2927 2928 mvpp2_txdesc_dma_addr_set(port, tx_desc, buf_dma_addr); 2929 2930 if (i == (skb_shinfo(skb)->nr_frags - 1)) { 2931 /* Last descriptor */ 2932 mvpp2_txdesc_cmd_set(port, tx_desc, 2933 MVPP2_TXD_L_DESC); 2934 mvpp2_txq_inc_put(port, txq_pcpu, skb, tx_desc); 2935 } else { 2936 /* Descriptor in the middle: Not First, Not Last */ 2937 mvpp2_txdesc_cmd_set(port, tx_desc, 0); 2938 mvpp2_txq_inc_put(port, txq_pcpu, NULL, tx_desc); 2939 } 2940 } 2941 2942 return 0; 2943 cleanup: 2944 /* Release all descriptors that were used to map fragments of 2945 * this packet, as well as the corresponding DMA mappings 2946 */ 2947 for (i = i - 1; i >= 0; i--) { 2948 tx_desc = txq->descs + i; 2949 tx_desc_unmap_put(port, txq, tx_desc); 2950 } 2951 2952 return -ENOMEM; 2953 } 2954 2955 static inline void mvpp2_tso_put_hdr(struct sk_buff *skb, 2956 struct net_device *dev, 2957 struct mvpp2_tx_queue *txq, 2958 struct mvpp2_tx_queue *aggr_txq, 2959 struct mvpp2_txq_pcpu *txq_pcpu, 2960 int hdr_sz) 2961 { 2962 struct mvpp2_port *port = netdev_priv(dev); 2963 struct mvpp2_tx_desc *tx_desc = mvpp2_txq_next_desc_get(aggr_txq); 2964 dma_addr_t addr; 2965 2966 mvpp2_txdesc_txq_set(port, tx_desc, txq->id); 2967 mvpp2_txdesc_size_set(port, tx_desc, hdr_sz); 2968 2969 addr = txq_pcpu->tso_headers_dma + 2970 txq_pcpu->txq_put_index * TSO_HEADER_SIZE; 2971 mvpp2_txdesc_dma_addr_set(port, tx_desc, addr); 2972 2973 mvpp2_txdesc_cmd_set(port, tx_desc, mvpp2_skb_tx_csum(port, skb) | 2974 MVPP2_TXD_F_DESC | 2975 MVPP2_TXD_PADDING_DISABLE); 2976 mvpp2_txq_inc_put(port, txq_pcpu, NULL, tx_desc); 2977 } 2978 2979 static inline int mvpp2_tso_put_data(struct sk_buff *skb, 2980 struct net_device *dev, struct tso_t *tso, 2981 struct mvpp2_tx_queue *txq, 2982 struct mvpp2_tx_queue *aggr_txq, 2983 struct mvpp2_txq_pcpu *txq_pcpu, 2984 int sz, bool left, bool last) 2985 { 2986 struct mvpp2_port *port = netdev_priv(dev); 2987 struct mvpp2_tx_desc *tx_desc = mvpp2_txq_next_desc_get(aggr_txq); 2988 dma_addr_t buf_dma_addr; 2989 2990 mvpp2_txdesc_txq_set(port, tx_desc, txq->id); 2991 mvpp2_txdesc_size_set(port, tx_desc, sz); 2992 2993 buf_dma_addr = dma_map_single(dev->dev.parent, tso->data, sz, 2994 DMA_TO_DEVICE); 2995 if (unlikely(dma_mapping_error(dev->dev.parent, buf_dma_addr))) { 2996 mvpp2_txq_desc_put(txq); 2997 return -ENOMEM; 2998 } 2999 3000 mvpp2_txdesc_dma_addr_set(port, tx_desc, buf_dma_addr); 3001 3002 if (!left) { 3003 mvpp2_txdesc_cmd_set(port, tx_desc, MVPP2_TXD_L_DESC); 3004 if (last) { 3005 mvpp2_txq_inc_put(port, txq_pcpu, skb, tx_desc); 3006 return 0; 3007 } 3008 } else { 3009 mvpp2_txdesc_cmd_set(port, tx_desc, 0); 3010 } 3011 3012 mvpp2_txq_inc_put(port, txq_pcpu, NULL, tx_desc); 3013 return 0; 3014 } 3015 3016 static int mvpp2_tx_tso(struct sk_buff *skb, struct net_device *dev, 3017 struct mvpp2_tx_queue *txq, 3018 struct mvpp2_tx_queue *aggr_txq, 3019 struct mvpp2_txq_pcpu *txq_pcpu) 3020 { 3021 struct mvpp2_port *port = netdev_priv(dev); 3022 struct tso_t tso; 3023 int hdr_sz = skb_transport_offset(skb) + tcp_hdrlen(skb); 3024 int i, len, descs = 0; 3025 3026 /* Check number of available descriptors */ 3027 if (mvpp2_aggr_desc_num_check(port, aggr_txq, tso_count_descs(skb)) || 3028 mvpp2_txq_reserved_desc_num_proc(port, txq, txq_pcpu, 3029 tso_count_descs(skb))) 3030 return 0; 3031 3032 tso_start(skb, &tso); 3033 len = skb->len - hdr_sz; 3034 while (len > 0) { 3035 int left = min_t(int, skb_shinfo(skb)->gso_size, len); 3036 char *hdr = txq_pcpu->tso_headers + 3037 txq_pcpu->txq_put_index * TSO_HEADER_SIZE; 3038 3039 len -= left; 3040 descs++; 3041 3042 tso_build_hdr(skb, hdr, &tso, left, len == 0); 3043 mvpp2_tso_put_hdr(skb, dev, txq, aggr_txq, txq_pcpu, hdr_sz); 3044 3045 while (left > 0) { 3046 int sz = min_t(int, tso.size, left); 3047 left -= sz; 3048 descs++; 3049 3050 if (mvpp2_tso_put_data(skb, dev, &tso, txq, aggr_txq, 3051 txq_pcpu, sz, left, len == 0)) 3052 goto release; 3053 tso_build_data(skb, &tso, sz); 3054 } 3055 } 3056 3057 return descs; 3058 3059 release: 3060 for (i = descs - 1; i >= 0; i--) { 3061 struct mvpp2_tx_desc *tx_desc = txq->descs + i; 3062 tx_desc_unmap_put(port, txq, tx_desc); 3063 } 3064 return 0; 3065 } 3066 3067 /* Main tx processing */ 3068 static netdev_tx_t mvpp2_tx(struct sk_buff *skb, struct net_device *dev) 3069 { 3070 struct mvpp2_port *port = netdev_priv(dev); 3071 struct mvpp2_tx_queue *txq, *aggr_txq; 3072 struct mvpp2_txq_pcpu *txq_pcpu; 3073 struct mvpp2_tx_desc *tx_desc; 3074 dma_addr_t buf_dma_addr; 3075 unsigned long flags = 0; 3076 unsigned int thread; 3077 int frags = 0; 3078 u16 txq_id; 3079 u32 tx_cmd; 3080 3081 thread = mvpp2_cpu_to_thread(port->priv, smp_processor_id()); 3082 3083 txq_id = skb_get_queue_mapping(skb); 3084 txq = port->txqs[txq_id]; 3085 txq_pcpu = per_cpu_ptr(txq->pcpu, thread); 3086 aggr_txq = &port->priv->aggr_txqs[thread]; 3087 3088 if (test_bit(thread, &port->priv->lock_map)) 3089 spin_lock_irqsave(&port->tx_lock[thread], flags); 3090 3091 if (skb_is_gso(skb)) { 3092 frags = mvpp2_tx_tso(skb, dev, txq, aggr_txq, txq_pcpu); 3093 goto out; 3094 } 3095 frags = skb_shinfo(skb)->nr_frags + 1; 3096 3097 /* Check number of available descriptors */ 3098 if (mvpp2_aggr_desc_num_check(port, aggr_txq, frags) || 3099 mvpp2_txq_reserved_desc_num_proc(port, txq, txq_pcpu, frags)) { 3100 frags = 0; 3101 goto out; 3102 } 3103 3104 /* Get a descriptor for the first part of the packet */ 3105 tx_desc = mvpp2_txq_next_desc_get(aggr_txq); 3106 mvpp2_txdesc_txq_set(port, tx_desc, txq->id); 3107 mvpp2_txdesc_size_set(port, tx_desc, skb_headlen(skb)); 3108 3109 buf_dma_addr = dma_map_single(dev->dev.parent, skb->data, 3110 skb_headlen(skb), DMA_TO_DEVICE); 3111 if (unlikely(dma_mapping_error(dev->dev.parent, buf_dma_addr))) { 3112 mvpp2_txq_desc_put(txq); 3113 frags = 0; 3114 goto out; 3115 } 3116 3117 mvpp2_txdesc_dma_addr_set(port, tx_desc, buf_dma_addr); 3118 3119 tx_cmd = mvpp2_skb_tx_csum(port, skb); 3120 3121 if (frags == 1) { 3122 /* First and Last descriptor */ 3123 tx_cmd |= MVPP2_TXD_F_DESC | MVPP2_TXD_L_DESC; 3124 mvpp2_txdesc_cmd_set(port, tx_desc, tx_cmd); 3125 mvpp2_txq_inc_put(port, txq_pcpu, skb, tx_desc); 3126 } else { 3127 /* First but not Last */ 3128 tx_cmd |= MVPP2_TXD_F_DESC | MVPP2_TXD_PADDING_DISABLE; 3129 mvpp2_txdesc_cmd_set(port, tx_desc, tx_cmd); 3130 mvpp2_txq_inc_put(port, txq_pcpu, NULL, tx_desc); 3131 3132 /* Continue with other skb fragments */ 3133 if (mvpp2_tx_frag_process(port, skb, aggr_txq, txq)) { 3134 tx_desc_unmap_put(port, txq, tx_desc); 3135 frags = 0; 3136 } 3137 } 3138 3139 out: 3140 if (frags > 0) { 3141 struct mvpp2_pcpu_stats *stats = per_cpu_ptr(port->stats, thread); 3142 struct netdev_queue *nq = netdev_get_tx_queue(dev, txq_id); 3143 3144 txq_pcpu->reserved_num -= frags; 3145 txq_pcpu->count += frags; 3146 aggr_txq->count += frags; 3147 3148 /* Enable transmit */ 3149 wmb(); 3150 mvpp2_aggr_txq_pend_desc_add(port, frags); 3151 3152 if (txq_pcpu->count >= txq_pcpu->stop_threshold) 3153 netif_tx_stop_queue(nq); 3154 3155 u64_stats_update_begin(&stats->syncp); 3156 stats->tx_packets++; 3157 stats->tx_bytes += skb->len; 3158 u64_stats_update_end(&stats->syncp); 3159 } else { 3160 dev->stats.tx_dropped++; 3161 dev_kfree_skb_any(skb); 3162 } 3163 3164 /* Finalize TX processing */ 3165 if (!port->has_tx_irqs && txq_pcpu->count >= txq->done_pkts_coal) 3166 mvpp2_txq_done(port, txq, txq_pcpu); 3167 3168 /* Set the timer in case not all frags were processed */ 3169 if (!port->has_tx_irqs && txq_pcpu->count <= frags && 3170 txq_pcpu->count > 0) { 3171 struct mvpp2_port_pcpu *port_pcpu = per_cpu_ptr(port->pcpu, thread); 3172 3173 mvpp2_timer_set(port_pcpu); 3174 } 3175 3176 if (test_bit(thread, &port->priv->lock_map)) 3177 spin_unlock_irqrestore(&port->tx_lock[thread], flags); 3178 3179 return NETDEV_TX_OK; 3180 } 3181 3182 static inline void mvpp2_cause_error(struct net_device *dev, int cause) 3183 { 3184 if (cause & MVPP2_CAUSE_FCS_ERR_MASK) 3185 netdev_err(dev, "FCS error\n"); 3186 if (cause & MVPP2_CAUSE_RX_FIFO_OVERRUN_MASK) 3187 netdev_err(dev, "rx fifo overrun error\n"); 3188 if (cause & MVPP2_CAUSE_TX_FIFO_UNDERRUN_MASK) 3189 netdev_err(dev, "tx fifo underrun error\n"); 3190 } 3191 3192 static int mvpp2_poll(struct napi_struct *napi, int budget) 3193 { 3194 u32 cause_rx_tx, cause_rx, cause_tx, cause_misc; 3195 int rx_done = 0; 3196 struct mvpp2_port *port = netdev_priv(napi->dev); 3197 struct mvpp2_queue_vector *qv; 3198 unsigned int thread = mvpp2_cpu_to_thread(port->priv, smp_processor_id()); 3199 3200 qv = container_of(napi, struct mvpp2_queue_vector, napi); 3201 3202 /* Rx/Tx cause register 3203 * 3204 * Bits 0-15: each bit indicates received packets on the Rx queue 3205 * (bit 0 is for Rx queue 0). 3206 * 3207 * Bits 16-23: each bit indicates transmitted packets on the Tx queue 3208 * (bit 16 is for Tx queue 0). 3209 * 3210 * Each CPU has its own Rx/Tx cause register 3211 */ 3212 cause_rx_tx = mvpp2_thread_read_relaxed(port->priv, qv->sw_thread_id, 3213 MVPP2_ISR_RX_TX_CAUSE_REG(port->id)); 3214 3215 cause_misc = cause_rx_tx & MVPP2_CAUSE_MISC_SUM_MASK; 3216 if (cause_misc) { 3217 mvpp2_cause_error(port->dev, cause_misc); 3218 3219 /* Clear the cause register */ 3220 mvpp2_write(port->priv, MVPP2_ISR_MISC_CAUSE_REG, 0); 3221 mvpp2_thread_write(port->priv, thread, 3222 MVPP2_ISR_RX_TX_CAUSE_REG(port->id), 3223 cause_rx_tx & ~MVPP2_CAUSE_MISC_SUM_MASK); 3224 } 3225 3226 if (port->has_tx_irqs) { 3227 cause_tx = cause_rx_tx & MVPP2_CAUSE_TXQ_OCCUP_DESC_ALL_MASK; 3228 if (cause_tx) { 3229 cause_tx >>= MVPP2_CAUSE_TXQ_OCCUP_DESC_ALL_OFFSET; 3230 mvpp2_tx_done(port, cause_tx, qv->sw_thread_id); 3231 } 3232 } 3233 3234 /* Process RX packets */ 3235 cause_rx = cause_rx_tx & 3236 MVPP2_CAUSE_RXQ_OCCUP_DESC_ALL_MASK(port->priv->hw_version); 3237 cause_rx <<= qv->first_rxq; 3238 cause_rx |= qv->pending_cause_rx; 3239 while (cause_rx && budget > 0) { 3240 int count; 3241 struct mvpp2_rx_queue *rxq; 3242 3243 rxq = mvpp2_get_rx_queue(port, cause_rx); 3244 if (!rxq) 3245 break; 3246 3247 count = mvpp2_rx(port, napi, budget, rxq); 3248 rx_done += count; 3249 budget -= count; 3250 if (budget > 0) { 3251 /* Clear the bit associated to this Rx queue 3252 * so that next iteration will continue from 3253 * the next Rx queue. 3254 */ 3255 cause_rx &= ~(1 << rxq->logic_rxq); 3256 } 3257 } 3258 3259 if (budget > 0) { 3260 cause_rx = 0; 3261 napi_complete_done(napi, rx_done); 3262 3263 mvpp2_qvec_interrupt_enable(qv); 3264 } 3265 qv->pending_cause_rx = cause_rx; 3266 return rx_done; 3267 } 3268 3269 static void mvpp22_mode_reconfigure(struct mvpp2_port *port) 3270 { 3271 u32 ctrl3; 3272 3273 /* Set the GMAC & XLG MAC in reset */ 3274 mvpp2_mac_reset_assert(port); 3275 3276 /* Set the MPCS and XPCS in reset */ 3277 mvpp22_pcs_reset_assert(port); 3278 3279 /* comphy reconfiguration */ 3280 mvpp22_comphy_init(port); 3281 3282 /* gop reconfiguration */ 3283 mvpp22_gop_init(port); 3284 3285 mvpp22_pcs_reset_deassert(port); 3286 3287 /* Only GOP port 0 has an XLG MAC */ 3288 if (port->gop_id == 0) { 3289 ctrl3 = readl(port->base + MVPP22_XLG_CTRL3_REG); 3290 ctrl3 &= ~MVPP22_XLG_CTRL3_MACMODESELECT_MASK; 3291 3292 if (mvpp2_is_xlg(port->phy_interface)) 3293 ctrl3 |= MVPP22_XLG_CTRL3_MACMODESELECT_10G; 3294 else 3295 ctrl3 |= MVPP22_XLG_CTRL3_MACMODESELECT_GMAC; 3296 3297 writel(ctrl3, port->base + MVPP22_XLG_CTRL3_REG); 3298 } 3299 3300 if (port->gop_id == 0 && mvpp2_is_xlg(port->phy_interface)) 3301 mvpp2_xlg_max_rx_size_set(port); 3302 else 3303 mvpp2_gmac_max_rx_size_set(port); 3304 } 3305 3306 /* Set hw internals when starting port */ 3307 static void mvpp2_start_dev(struct mvpp2_port *port) 3308 { 3309 int i; 3310 3311 mvpp2_txp_max_tx_size_set(port); 3312 3313 for (i = 0; i < port->nqvecs; i++) 3314 napi_enable(&port->qvecs[i].napi); 3315 3316 /* Enable interrupts on all threads */ 3317 mvpp2_interrupts_enable(port); 3318 3319 if (port->priv->hw_version == MVPP22) 3320 mvpp22_mode_reconfigure(port); 3321 3322 if (port->phylink) { 3323 phylink_start(port->phylink); 3324 } else { 3325 /* Phylink isn't used as of now for ACPI, so the MAC has to be 3326 * configured manually when the interface is started. This will 3327 * be removed as soon as the phylink ACPI support lands in. 3328 */ 3329 struct phylink_link_state state = { 3330 .interface = port->phy_interface, 3331 }; 3332 mvpp2_mac_config(&port->phylink_config, MLO_AN_INBAND, &state); 3333 mvpp2_mac_link_up(&port->phylink_config, MLO_AN_INBAND, 3334 port->phy_interface, NULL); 3335 } 3336 3337 netif_tx_start_all_queues(port->dev); 3338 } 3339 3340 /* Set hw internals when stopping port */ 3341 static void mvpp2_stop_dev(struct mvpp2_port *port) 3342 { 3343 int i; 3344 3345 /* Disable interrupts on all threads */ 3346 mvpp2_interrupts_disable(port); 3347 3348 for (i = 0; i < port->nqvecs; i++) 3349 napi_disable(&port->qvecs[i].napi); 3350 3351 if (port->phylink) 3352 phylink_stop(port->phylink); 3353 phy_power_off(port->comphy); 3354 } 3355 3356 static int mvpp2_check_ringparam_valid(struct net_device *dev, 3357 struct ethtool_ringparam *ring) 3358 { 3359 u16 new_rx_pending = ring->rx_pending; 3360 u16 new_tx_pending = ring->tx_pending; 3361 3362 if (ring->rx_pending == 0 || ring->tx_pending == 0) 3363 return -EINVAL; 3364 3365 if (ring->rx_pending > MVPP2_MAX_RXD_MAX) 3366 new_rx_pending = MVPP2_MAX_RXD_MAX; 3367 else if (!IS_ALIGNED(ring->rx_pending, 16)) 3368 new_rx_pending = ALIGN(ring->rx_pending, 16); 3369 3370 if (ring->tx_pending > MVPP2_MAX_TXD_MAX) 3371 new_tx_pending = MVPP2_MAX_TXD_MAX; 3372 else if (!IS_ALIGNED(ring->tx_pending, 32)) 3373 new_tx_pending = ALIGN(ring->tx_pending, 32); 3374 3375 /* The Tx ring size cannot be smaller than the minimum number of 3376 * descriptors needed for TSO. 3377 */ 3378 if (new_tx_pending < MVPP2_MAX_SKB_DESCS) 3379 new_tx_pending = ALIGN(MVPP2_MAX_SKB_DESCS, 32); 3380 3381 if (ring->rx_pending != new_rx_pending) { 3382 netdev_info(dev, "illegal Rx ring size value %d, round to %d\n", 3383 ring->rx_pending, new_rx_pending); 3384 ring->rx_pending = new_rx_pending; 3385 } 3386 3387 if (ring->tx_pending != new_tx_pending) { 3388 netdev_info(dev, "illegal Tx ring size value %d, round to %d\n", 3389 ring->tx_pending, new_tx_pending); 3390 ring->tx_pending = new_tx_pending; 3391 } 3392 3393 return 0; 3394 } 3395 3396 static void mvpp21_get_mac_address(struct mvpp2_port *port, unsigned char *addr) 3397 { 3398 u32 mac_addr_l, mac_addr_m, mac_addr_h; 3399 3400 mac_addr_l = readl(port->base + MVPP2_GMAC_CTRL_1_REG); 3401 mac_addr_m = readl(port->priv->lms_base + MVPP2_SRC_ADDR_MIDDLE); 3402 mac_addr_h = readl(port->priv->lms_base + MVPP2_SRC_ADDR_HIGH); 3403 addr[0] = (mac_addr_h >> 24) & 0xFF; 3404 addr[1] = (mac_addr_h >> 16) & 0xFF; 3405 addr[2] = (mac_addr_h >> 8) & 0xFF; 3406 addr[3] = mac_addr_h & 0xFF; 3407 addr[4] = mac_addr_m & 0xFF; 3408 addr[5] = (mac_addr_l >> MVPP2_GMAC_SA_LOW_OFFS) & 0xFF; 3409 } 3410 3411 static int mvpp2_irqs_init(struct mvpp2_port *port) 3412 { 3413 int err, i; 3414 3415 for (i = 0; i < port->nqvecs; i++) { 3416 struct mvpp2_queue_vector *qv = port->qvecs + i; 3417 3418 if (qv->type == MVPP2_QUEUE_VECTOR_PRIVATE) { 3419 qv->mask = kzalloc(cpumask_size(), GFP_KERNEL); 3420 if (!qv->mask) { 3421 err = -ENOMEM; 3422 goto err; 3423 } 3424 3425 irq_set_status_flags(qv->irq, IRQ_NO_BALANCING); 3426 } 3427 3428 err = request_irq(qv->irq, mvpp2_isr, 0, port->dev->name, qv); 3429 if (err) 3430 goto err; 3431 3432 if (qv->type == MVPP2_QUEUE_VECTOR_PRIVATE) { 3433 unsigned int cpu; 3434 3435 for_each_present_cpu(cpu) { 3436 if (mvpp2_cpu_to_thread(port->priv, cpu) == 3437 qv->sw_thread_id) 3438 cpumask_set_cpu(cpu, qv->mask); 3439 } 3440 3441 irq_set_affinity_hint(qv->irq, qv->mask); 3442 } 3443 } 3444 3445 return 0; 3446 err: 3447 for (i = 0; i < port->nqvecs; i++) { 3448 struct mvpp2_queue_vector *qv = port->qvecs + i; 3449 3450 irq_set_affinity_hint(qv->irq, NULL); 3451 kfree(qv->mask); 3452 qv->mask = NULL; 3453 free_irq(qv->irq, qv); 3454 } 3455 3456 return err; 3457 } 3458 3459 static void mvpp2_irqs_deinit(struct mvpp2_port *port) 3460 { 3461 int i; 3462 3463 for (i = 0; i < port->nqvecs; i++) { 3464 struct mvpp2_queue_vector *qv = port->qvecs + i; 3465 3466 irq_set_affinity_hint(qv->irq, NULL); 3467 kfree(qv->mask); 3468 qv->mask = NULL; 3469 irq_clear_status_flags(qv->irq, IRQ_NO_BALANCING); 3470 free_irq(qv->irq, qv); 3471 } 3472 } 3473 3474 static bool mvpp22_rss_is_supported(void) 3475 { 3476 return queue_mode == MVPP2_QDIST_MULTI_MODE; 3477 } 3478 3479 static int mvpp2_open(struct net_device *dev) 3480 { 3481 struct mvpp2_port *port = netdev_priv(dev); 3482 struct mvpp2 *priv = port->priv; 3483 unsigned char mac_bcast[ETH_ALEN] = { 3484 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }; 3485 bool valid = false; 3486 int err; 3487 3488 err = mvpp2_prs_mac_da_accept(port, mac_bcast, true); 3489 if (err) { 3490 netdev_err(dev, "mvpp2_prs_mac_da_accept BC failed\n"); 3491 return err; 3492 } 3493 err = mvpp2_prs_mac_da_accept(port, dev->dev_addr, true); 3494 if (err) { 3495 netdev_err(dev, "mvpp2_prs_mac_da_accept own addr failed\n"); 3496 return err; 3497 } 3498 err = mvpp2_prs_tag_mode_set(port->priv, port->id, MVPP2_TAG_TYPE_MH); 3499 if (err) { 3500 netdev_err(dev, "mvpp2_prs_tag_mode_set failed\n"); 3501 return err; 3502 } 3503 err = mvpp2_prs_def_flow(port); 3504 if (err) { 3505 netdev_err(dev, "mvpp2_prs_def_flow failed\n"); 3506 return err; 3507 } 3508 3509 /* Allocate the Rx/Tx queues */ 3510 err = mvpp2_setup_rxqs(port); 3511 if (err) { 3512 netdev_err(port->dev, "cannot allocate Rx queues\n"); 3513 return err; 3514 } 3515 3516 err = mvpp2_setup_txqs(port); 3517 if (err) { 3518 netdev_err(port->dev, "cannot allocate Tx queues\n"); 3519 goto err_cleanup_rxqs; 3520 } 3521 3522 err = mvpp2_irqs_init(port); 3523 if (err) { 3524 netdev_err(port->dev, "cannot init IRQs\n"); 3525 goto err_cleanup_txqs; 3526 } 3527 3528 /* Phylink isn't supported yet in ACPI mode */ 3529 if (port->of_node) { 3530 err = phylink_of_phy_connect(port->phylink, port->of_node, 0); 3531 if (err) { 3532 netdev_err(port->dev, "could not attach PHY (%d)\n", 3533 err); 3534 goto err_free_irq; 3535 } 3536 3537 valid = true; 3538 } 3539 3540 if (priv->hw_version == MVPP22 && port->link_irq && !port->phylink) { 3541 err = request_irq(port->link_irq, mvpp2_link_status_isr, 0, 3542 dev->name, port); 3543 if (err) { 3544 netdev_err(port->dev, "cannot request link IRQ %d\n", 3545 port->link_irq); 3546 goto err_free_irq; 3547 } 3548 3549 mvpp22_gop_setup_irq(port); 3550 3551 /* In default link is down */ 3552 netif_carrier_off(port->dev); 3553 3554 valid = true; 3555 } else { 3556 port->link_irq = 0; 3557 } 3558 3559 if (!valid) { 3560 netdev_err(port->dev, 3561 "invalid configuration: no dt or link IRQ"); 3562 goto err_free_irq; 3563 } 3564 3565 /* Unmask interrupts on all CPUs */ 3566 on_each_cpu(mvpp2_interrupts_unmask, port, 1); 3567 mvpp2_shared_interrupt_mask_unmask(port, false); 3568 3569 mvpp2_start_dev(port); 3570 3571 /* Start hardware statistics gathering */ 3572 queue_delayed_work(priv->stats_queue, &port->stats_work, 3573 MVPP2_MIB_COUNTERS_STATS_DELAY); 3574 3575 return 0; 3576 3577 err_free_irq: 3578 mvpp2_irqs_deinit(port); 3579 err_cleanup_txqs: 3580 mvpp2_cleanup_txqs(port); 3581 err_cleanup_rxqs: 3582 mvpp2_cleanup_rxqs(port); 3583 return err; 3584 } 3585 3586 static int mvpp2_stop(struct net_device *dev) 3587 { 3588 struct mvpp2_port *port = netdev_priv(dev); 3589 struct mvpp2_port_pcpu *port_pcpu; 3590 unsigned int thread; 3591 3592 mvpp2_stop_dev(port); 3593 3594 /* Mask interrupts on all threads */ 3595 on_each_cpu(mvpp2_interrupts_mask, port, 1); 3596 mvpp2_shared_interrupt_mask_unmask(port, true); 3597 3598 if (port->phylink) 3599 phylink_disconnect_phy(port->phylink); 3600 if (port->link_irq) 3601 free_irq(port->link_irq, port); 3602 3603 mvpp2_irqs_deinit(port); 3604 if (!port->has_tx_irqs) { 3605 for (thread = 0; thread < port->priv->nthreads; thread++) { 3606 port_pcpu = per_cpu_ptr(port->pcpu, thread); 3607 3608 hrtimer_cancel(&port_pcpu->tx_done_timer); 3609 port_pcpu->timer_scheduled = false; 3610 tasklet_kill(&port_pcpu->tx_done_tasklet); 3611 } 3612 } 3613 mvpp2_cleanup_rxqs(port); 3614 mvpp2_cleanup_txqs(port); 3615 3616 cancel_delayed_work_sync(&port->stats_work); 3617 3618 mvpp2_mac_reset_assert(port); 3619 mvpp22_pcs_reset_assert(port); 3620 3621 return 0; 3622 } 3623 3624 static int mvpp2_prs_mac_da_accept_list(struct mvpp2_port *port, 3625 struct netdev_hw_addr_list *list) 3626 { 3627 struct netdev_hw_addr *ha; 3628 int ret; 3629 3630 netdev_hw_addr_list_for_each(ha, list) { 3631 ret = mvpp2_prs_mac_da_accept(port, ha->addr, true); 3632 if (ret) 3633 return ret; 3634 } 3635 3636 return 0; 3637 } 3638 3639 static void mvpp2_set_rx_promisc(struct mvpp2_port *port, bool enable) 3640 { 3641 if (!enable && (port->dev->features & NETIF_F_HW_VLAN_CTAG_FILTER)) 3642 mvpp2_prs_vid_enable_filtering(port); 3643 else 3644 mvpp2_prs_vid_disable_filtering(port); 3645 3646 mvpp2_prs_mac_promisc_set(port->priv, port->id, 3647 MVPP2_PRS_L2_UNI_CAST, enable); 3648 3649 mvpp2_prs_mac_promisc_set(port->priv, port->id, 3650 MVPP2_PRS_L2_MULTI_CAST, enable); 3651 } 3652 3653 static void mvpp2_set_rx_mode(struct net_device *dev) 3654 { 3655 struct mvpp2_port *port = netdev_priv(dev); 3656 3657 /* Clear the whole UC and MC list */ 3658 mvpp2_prs_mac_del_all(port); 3659 3660 if (dev->flags & IFF_PROMISC) { 3661 mvpp2_set_rx_promisc(port, true); 3662 return; 3663 } 3664 3665 mvpp2_set_rx_promisc(port, false); 3666 3667 if (netdev_uc_count(dev) > MVPP2_PRS_MAC_UC_FILT_MAX || 3668 mvpp2_prs_mac_da_accept_list(port, &dev->uc)) 3669 mvpp2_prs_mac_promisc_set(port->priv, port->id, 3670 MVPP2_PRS_L2_UNI_CAST, true); 3671 3672 if (dev->flags & IFF_ALLMULTI) { 3673 mvpp2_prs_mac_promisc_set(port->priv, port->id, 3674 MVPP2_PRS_L2_MULTI_CAST, true); 3675 return; 3676 } 3677 3678 if (netdev_mc_count(dev) > MVPP2_PRS_MAC_MC_FILT_MAX || 3679 mvpp2_prs_mac_da_accept_list(port, &dev->mc)) 3680 mvpp2_prs_mac_promisc_set(port->priv, port->id, 3681 MVPP2_PRS_L2_MULTI_CAST, true); 3682 } 3683 3684 static int mvpp2_set_mac_address(struct net_device *dev, void *p) 3685 { 3686 const struct sockaddr *addr = p; 3687 int err; 3688 3689 if (!is_valid_ether_addr(addr->sa_data)) 3690 return -EADDRNOTAVAIL; 3691 3692 err = mvpp2_prs_update_mac_da(dev, addr->sa_data); 3693 if (err) { 3694 /* Reconfigure parser accept the original MAC address */ 3695 mvpp2_prs_update_mac_da(dev, dev->dev_addr); 3696 netdev_err(dev, "failed to change MAC address\n"); 3697 } 3698 return err; 3699 } 3700 3701 static int mvpp2_change_mtu(struct net_device *dev, int mtu) 3702 { 3703 struct mvpp2_port *port = netdev_priv(dev); 3704 int err; 3705 3706 if (!IS_ALIGNED(MVPP2_RX_PKT_SIZE(mtu), 8)) { 3707 netdev_info(dev, "illegal MTU value %d, round to %d\n", mtu, 3708 ALIGN(MVPP2_RX_PKT_SIZE(mtu), 8)); 3709 mtu = ALIGN(MVPP2_RX_PKT_SIZE(mtu), 8); 3710 } 3711 3712 if (!netif_running(dev)) { 3713 err = mvpp2_bm_update_mtu(dev, mtu); 3714 if (!err) { 3715 port->pkt_size = MVPP2_RX_PKT_SIZE(mtu); 3716 return 0; 3717 } 3718 3719 /* Reconfigure BM to the original MTU */ 3720 err = mvpp2_bm_update_mtu(dev, dev->mtu); 3721 if (err) 3722 goto log_error; 3723 } 3724 3725 mvpp2_stop_dev(port); 3726 3727 err = mvpp2_bm_update_mtu(dev, mtu); 3728 if (!err) { 3729 port->pkt_size = MVPP2_RX_PKT_SIZE(mtu); 3730 goto out_start; 3731 } 3732 3733 /* Reconfigure BM to the original MTU */ 3734 err = mvpp2_bm_update_mtu(dev, dev->mtu); 3735 if (err) 3736 goto log_error; 3737 3738 out_start: 3739 mvpp2_start_dev(port); 3740 mvpp2_egress_enable(port); 3741 mvpp2_ingress_enable(port); 3742 3743 return 0; 3744 log_error: 3745 netdev_err(dev, "failed to change MTU\n"); 3746 return err; 3747 } 3748 3749 static void 3750 mvpp2_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats) 3751 { 3752 struct mvpp2_port *port = netdev_priv(dev); 3753 unsigned int start; 3754 unsigned int cpu; 3755 3756 for_each_possible_cpu(cpu) { 3757 struct mvpp2_pcpu_stats *cpu_stats; 3758 u64 rx_packets; 3759 u64 rx_bytes; 3760 u64 tx_packets; 3761 u64 tx_bytes; 3762 3763 cpu_stats = per_cpu_ptr(port->stats, cpu); 3764 do { 3765 start = u64_stats_fetch_begin_irq(&cpu_stats->syncp); 3766 rx_packets = cpu_stats->rx_packets; 3767 rx_bytes = cpu_stats->rx_bytes; 3768 tx_packets = cpu_stats->tx_packets; 3769 tx_bytes = cpu_stats->tx_bytes; 3770 } while (u64_stats_fetch_retry_irq(&cpu_stats->syncp, start)); 3771 3772 stats->rx_packets += rx_packets; 3773 stats->rx_bytes += rx_bytes; 3774 stats->tx_packets += tx_packets; 3775 stats->tx_bytes += tx_bytes; 3776 } 3777 3778 stats->rx_errors = dev->stats.rx_errors; 3779 stats->rx_dropped = dev->stats.rx_dropped; 3780 stats->tx_dropped = dev->stats.tx_dropped; 3781 } 3782 3783 static int mvpp2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) 3784 { 3785 struct mvpp2_port *port = netdev_priv(dev); 3786 3787 if (!port->phylink) 3788 return -ENOTSUPP; 3789 3790 return phylink_mii_ioctl(port->phylink, ifr, cmd); 3791 } 3792 3793 static int mvpp2_vlan_rx_add_vid(struct net_device *dev, __be16 proto, u16 vid) 3794 { 3795 struct mvpp2_port *port = netdev_priv(dev); 3796 int ret; 3797 3798 ret = mvpp2_prs_vid_entry_add(port, vid); 3799 if (ret) 3800 netdev_err(dev, "rx-vlan-filter offloading cannot accept more than %d VIDs per port\n", 3801 MVPP2_PRS_VLAN_FILT_MAX - 1); 3802 return ret; 3803 } 3804 3805 static int mvpp2_vlan_rx_kill_vid(struct net_device *dev, __be16 proto, u16 vid) 3806 { 3807 struct mvpp2_port *port = netdev_priv(dev); 3808 3809 mvpp2_prs_vid_entry_remove(port, vid); 3810 return 0; 3811 } 3812 3813 static int mvpp2_set_features(struct net_device *dev, 3814 netdev_features_t features) 3815 { 3816 netdev_features_t changed = dev->features ^ features; 3817 struct mvpp2_port *port = netdev_priv(dev); 3818 3819 if (changed & NETIF_F_HW_VLAN_CTAG_FILTER) { 3820 if (features & NETIF_F_HW_VLAN_CTAG_FILTER) { 3821 mvpp2_prs_vid_enable_filtering(port); 3822 } else { 3823 /* Invalidate all registered VID filters for this 3824 * port 3825 */ 3826 mvpp2_prs_vid_remove_all(port); 3827 3828 mvpp2_prs_vid_disable_filtering(port); 3829 } 3830 } 3831 3832 if (changed & NETIF_F_RXHASH) { 3833 if (features & NETIF_F_RXHASH) 3834 mvpp22_port_rss_enable(port); 3835 else 3836 mvpp22_port_rss_disable(port); 3837 } 3838 3839 return 0; 3840 } 3841 3842 /* Ethtool methods */ 3843 3844 static int mvpp2_ethtool_nway_reset(struct net_device *dev) 3845 { 3846 struct mvpp2_port *port = netdev_priv(dev); 3847 3848 if (!port->phylink) 3849 return -ENOTSUPP; 3850 3851 return phylink_ethtool_nway_reset(port->phylink); 3852 } 3853 3854 /* Set interrupt coalescing for ethtools */ 3855 static int mvpp2_ethtool_set_coalesce(struct net_device *dev, 3856 struct ethtool_coalesce *c) 3857 { 3858 struct mvpp2_port *port = netdev_priv(dev); 3859 int queue; 3860 3861 for (queue = 0; queue < port->nrxqs; queue++) { 3862 struct mvpp2_rx_queue *rxq = port->rxqs[queue]; 3863 3864 rxq->time_coal = c->rx_coalesce_usecs; 3865 rxq->pkts_coal = c->rx_max_coalesced_frames; 3866 mvpp2_rx_pkts_coal_set(port, rxq); 3867 mvpp2_rx_time_coal_set(port, rxq); 3868 } 3869 3870 if (port->has_tx_irqs) { 3871 port->tx_time_coal = c->tx_coalesce_usecs; 3872 mvpp2_tx_time_coal_set(port); 3873 } 3874 3875 for (queue = 0; queue < port->ntxqs; queue++) { 3876 struct mvpp2_tx_queue *txq = port->txqs[queue]; 3877 3878 txq->done_pkts_coal = c->tx_max_coalesced_frames; 3879 3880 if (port->has_tx_irqs) 3881 mvpp2_tx_pkts_coal_set(port, txq); 3882 } 3883 3884 return 0; 3885 } 3886 3887 /* get coalescing for ethtools */ 3888 static int mvpp2_ethtool_get_coalesce(struct net_device *dev, 3889 struct ethtool_coalesce *c) 3890 { 3891 struct mvpp2_port *port = netdev_priv(dev); 3892 3893 c->rx_coalesce_usecs = port->rxqs[0]->time_coal; 3894 c->rx_max_coalesced_frames = port->rxqs[0]->pkts_coal; 3895 c->tx_max_coalesced_frames = port->txqs[0]->done_pkts_coal; 3896 c->tx_coalesce_usecs = port->tx_time_coal; 3897 return 0; 3898 } 3899 3900 static void mvpp2_ethtool_get_drvinfo(struct net_device *dev, 3901 struct ethtool_drvinfo *drvinfo) 3902 { 3903 strlcpy(drvinfo->driver, MVPP2_DRIVER_NAME, 3904 sizeof(drvinfo->driver)); 3905 strlcpy(drvinfo->version, MVPP2_DRIVER_VERSION, 3906 sizeof(drvinfo->version)); 3907 strlcpy(drvinfo->bus_info, dev_name(&dev->dev), 3908 sizeof(drvinfo->bus_info)); 3909 } 3910 3911 static void mvpp2_ethtool_get_ringparam(struct net_device *dev, 3912 struct ethtool_ringparam *ring) 3913 { 3914 struct mvpp2_port *port = netdev_priv(dev); 3915 3916 ring->rx_max_pending = MVPP2_MAX_RXD_MAX; 3917 ring->tx_max_pending = MVPP2_MAX_TXD_MAX; 3918 ring->rx_pending = port->rx_ring_size; 3919 ring->tx_pending = port->tx_ring_size; 3920 } 3921 3922 static int mvpp2_ethtool_set_ringparam(struct net_device *dev, 3923 struct ethtool_ringparam *ring) 3924 { 3925 struct mvpp2_port *port = netdev_priv(dev); 3926 u16 prev_rx_ring_size = port->rx_ring_size; 3927 u16 prev_tx_ring_size = port->tx_ring_size; 3928 int err; 3929 3930 err = mvpp2_check_ringparam_valid(dev, ring); 3931 if (err) 3932 return err; 3933 3934 if (!netif_running(dev)) { 3935 port->rx_ring_size = ring->rx_pending; 3936 port->tx_ring_size = ring->tx_pending; 3937 return 0; 3938 } 3939 3940 /* The interface is running, so we have to force a 3941 * reallocation of the queues 3942 */ 3943 mvpp2_stop_dev(port); 3944 mvpp2_cleanup_rxqs(port); 3945 mvpp2_cleanup_txqs(port); 3946 3947 port->rx_ring_size = ring->rx_pending; 3948 port->tx_ring_size = ring->tx_pending; 3949 3950 err = mvpp2_setup_rxqs(port); 3951 if (err) { 3952 /* Reallocate Rx queues with the original ring size */ 3953 port->rx_ring_size = prev_rx_ring_size; 3954 ring->rx_pending = prev_rx_ring_size; 3955 err = mvpp2_setup_rxqs(port); 3956 if (err) 3957 goto err_out; 3958 } 3959 err = mvpp2_setup_txqs(port); 3960 if (err) { 3961 /* Reallocate Tx queues with the original ring size */ 3962 port->tx_ring_size = prev_tx_ring_size; 3963 ring->tx_pending = prev_tx_ring_size; 3964 err = mvpp2_setup_txqs(port); 3965 if (err) 3966 goto err_clean_rxqs; 3967 } 3968 3969 mvpp2_start_dev(port); 3970 mvpp2_egress_enable(port); 3971 mvpp2_ingress_enable(port); 3972 3973 return 0; 3974 3975 err_clean_rxqs: 3976 mvpp2_cleanup_rxqs(port); 3977 err_out: 3978 netdev_err(dev, "failed to change ring parameters"); 3979 return err; 3980 } 3981 3982 static void mvpp2_ethtool_get_pause_param(struct net_device *dev, 3983 struct ethtool_pauseparam *pause) 3984 { 3985 struct mvpp2_port *port = netdev_priv(dev); 3986 3987 if (!port->phylink) 3988 return; 3989 3990 phylink_ethtool_get_pauseparam(port->phylink, pause); 3991 } 3992 3993 static int mvpp2_ethtool_set_pause_param(struct net_device *dev, 3994 struct ethtool_pauseparam *pause) 3995 { 3996 struct mvpp2_port *port = netdev_priv(dev); 3997 3998 if (!port->phylink) 3999 return -ENOTSUPP; 4000 4001 return phylink_ethtool_set_pauseparam(port->phylink, pause); 4002 } 4003 4004 static int mvpp2_ethtool_get_link_ksettings(struct net_device *dev, 4005 struct ethtool_link_ksettings *cmd) 4006 { 4007 struct mvpp2_port *port = netdev_priv(dev); 4008 4009 if (!port->phylink) 4010 return -ENOTSUPP; 4011 4012 return phylink_ethtool_ksettings_get(port->phylink, cmd); 4013 } 4014 4015 static int mvpp2_ethtool_set_link_ksettings(struct net_device *dev, 4016 const struct ethtool_link_ksettings *cmd) 4017 { 4018 struct mvpp2_port *port = netdev_priv(dev); 4019 4020 if (!port->phylink) 4021 return -ENOTSUPP; 4022 4023 return phylink_ethtool_ksettings_set(port->phylink, cmd); 4024 } 4025 4026 static int mvpp2_ethtool_get_rxnfc(struct net_device *dev, 4027 struct ethtool_rxnfc *info, u32 *rules) 4028 { 4029 struct mvpp2_port *port = netdev_priv(dev); 4030 int ret = 0, i, loc = 0; 4031 4032 if (!mvpp22_rss_is_supported()) 4033 return -EOPNOTSUPP; 4034 4035 switch (info->cmd) { 4036 case ETHTOOL_GRXFH: 4037 ret = mvpp2_ethtool_rxfh_get(port, info); 4038 break; 4039 case ETHTOOL_GRXRINGS: 4040 info->data = port->nrxqs; 4041 break; 4042 case ETHTOOL_GRXCLSRLCNT: 4043 info->rule_cnt = port->n_rfs_rules; 4044 break; 4045 case ETHTOOL_GRXCLSRULE: 4046 ret = mvpp2_ethtool_cls_rule_get(port, info); 4047 break; 4048 case ETHTOOL_GRXCLSRLALL: 4049 for (i = 0; i < MVPP2_N_RFS_ENTRIES_PER_FLOW; i++) { 4050 if (port->rfs_rules[i]) 4051 rules[loc++] = i; 4052 } 4053 break; 4054 default: 4055 return -ENOTSUPP; 4056 } 4057 4058 return ret; 4059 } 4060 4061 static int mvpp2_ethtool_set_rxnfc(struct net_device *dev, 4062 struct ethtool_rxnfc *info) 4063 { 4064 struct mvpp2_port *port = netdev_priv(dev); 4065 int ret = 0; 4066 4067 if (!mvpp22_rss_is_supported()) 4068 return -EOPNOTSUPP; 4069 4070 switch (info->cmd) { 4071 case ETHTOOL_SRXFH: 4072 ret = mvpp2_ethtool_rxfh_set(port, info); 4073 break; 4074 case ETHTOOL_SRXCLSRLINS: 4075 ret = mvpp2_ethtool_cls_rule_ins(port, info); 4076 break; 4077 case ETHTOOL_SRXCLSRLDEL: 4078 ret = mvpp2_ethtool_cls_rule_del(port, info); 4079 break; 4080 default: 4081 return -EOPNOTSUPP; 4082 } 4083 return ret; 4084 } 4085 4086 static u32 mvpp2_ethtool_get_rxfh_indir_size(struct net_device *dev) 4087 { 4088 return mvpp22_rss_is_supported() ? MVPP22_RSS_TABLE_ENTRIES : 0; 4089 } 4090 4091 static int mvpp2_ethtool_get_rxfh(struct net_device *dev, u32 *indir, u8 *key, 4092 u8 *hfunc) 4093 { 4094 struct mvpp2_port *port = netdev_priv(dev); 4095 int ret = 0; 4096 4097 if (!mvpp22_rss_is_supported()) 4098 return -EOPNOTSUPP; 4099 4100 if (indir) 4101 ret = mvpp22_port_rss_ctx_indir_get(port, 0, indir); 4102 4103 if (hfunc) 4104 *hfunc = ETH_RSS_HASH_CRC32; 4105 4106 return ret; 4107 } 4108 4109 static int mvpp2_ethtool_set_rxfh(struct net_device *dev, const u32 *indir, 4110 const u8 *key, const u8 hfunc) 4111 { 4112 struct mvpp2_port *port = netdev_priv(dev); 4113 int ret = 0; 4114 4115 if (!mvpp22_rss_is_supported()) 4116 return -EOPNOTSUPP; 4117 4118 if (hfunc != ETH_RSS_HASH_NO_CHANGE && hfunc != ETH_RSS_HASH_CRC32) 4119 return -EOPNOTSUPP; 4120 4121 if (key) 4122 return -EOPNOTSUPP; 4123 4124 if (indir) 4125 ret = mvpp22_port_rss_ctx_indir_set(port, 0, indir); 4126 4127 return ret; 4128 } 4129 4130 static int mvpp2_ethtool_get_rxfh_context(struct net_device *dev, u32 *indir, 4131 u8 *key, u8 *hfunc, u32 rss_context) 4132 { 4133 struct mvpp2_port *port = netdev_priv(dev); 4134 int ret = 0; 4135 4136 if (!mvpp22_rss_is_supported()) 4137 return -EOPNOTSUPP; 4138 4139 if (hfunc) 4140 *hfunc = ETH_RSS_HASH_CRC32; 4141 4142 if (indir) 4143 ret = mvpp22_port_rss_ctx_indir_get(port, rss_context, indir); 4144 4145 return ret; 4146 } 4147 4148 static int mvpp2_ethtool_set_rxfh_context(struct net_device *dev, 4149 const u32 *indir, const u8 *key, 4150 const u8 hfunc, u32 *rss_context, 4151 bool delete) 4152 { 4153 struct mvpp2_port *port = netdev_priv(dev); 4154 int ret; 4155 4156 if (!mvpp22_rss_is_supported()) 4157 return -EOPNOTSUPP; 4158 4159 if (hfunc != ETH_RSS_HASH_NO_CHANGE && hfunc != ETH_RSS_HASH_CRC32) 4160 return -EOPNOTSUPP; 4161 4162 if (key) 4163 return -EOPNOTSUPP; 4164 4165 if (delete) 4166 return mvpp22_port_rss_ctx_delete(port, *rss_context); 4167 4168 if (*rss_context == ETH_RXFH_CONTEXT_ALLOC) { 4169 ret = mvpp22_port_rss_ctx_create(port, rss_context); 4170 if (ret) 4171 return ret; 4172 } 4173 4174 return mvpp22_port_rss_ctx_indir_set(port, *rss_context, indir); 4175 } 4176 /* Device ops */ 4177 4178 static const struct net_device_ops mvpp2_netdev_ops = { 4179 .ndo_open = mvpp2_open, 4180 .ndo_stop = mvpp2_stop, 4181 .ndo_start_xmit = mvpp2_tx, 4182 .ndo_set_rx_mode = mvpp2_set_rx_mode, 4183 .ndo_set_mac_address = mvpp2_set_mac_address, 4184 .ndo_change_mtu = mvpp2_change_mtu, 4185 .ndo_get_stats64 = mvpp2_get_stats64, 4186 .ndo_do_ioctl = mvpp2_ioctl, 4187 .ndo_vlan_rx_add_vid = mvpp2_vlan_rx_add_vid, 4188 .ndo_vlan_rx_kill_vid = mvpp2_vlan_rx_kill_vid, 4189 .ndo_set_features = mvpp2_set_features, 4190 }; 4191 4192 static const struct ethtool_ops mvpp2_eth_tool_ops = { 4193 .nway_reset = mvpp2_ethtool_nway_reset, 4194 .get_link = ethtool_op_get_link, 4195 .set_coalesce = mvpp2_ethtool_set_coalesce, 4196 .get_coalesce = mvpp2_ethtool_get_coalesce, 4197 .get_drvinfo = mvpp2_ethtool_get_drvinfo, 4198 .get_ringparam = mvpp2_ethtool_get_ringparam, 4199 .set_ringparam = mvpp2_ethtool_set_ringparam, 4200 .get_strings = mvpp2_ethtool_get_strings, 4201 .get_ethtool_stats = mvpp2_ethtool_get_stats, 4202 .get_sset_count = mvpp2_ethtool_get_sset_count, 4203 .get_pauseparam = mvpp2_ethtool_get_pause_param, 4204 .set_pauseparam = mvpp2_ethtool_set_pause_param, 4205 .get_link_ksettings = mvpp2_ethtool_get_link_ksettings, 4206 .set_link_ksettings = mvpp2_ethtool_set_link_ksettings, 4207 .get_rxnfc = mvpp2_ethtool_get_rxnfc, 4208 .set_rxnfc = mvpp2_ethtool_set_rxnfc, 4209 .get_rxfh_indir_size = mvpp2_ethtool_get_rxfh_indir_size, 4210 .get_rxfh = mvpp2_ethtool_get_rxfh, 4211 .set_rxfh = mvpp2_ethtool_set_rxfh, 4212 .get_rxfh_context = mvpp2_ethtool_get_rxfh_context, 4213 .set_rxfh_context = mvpp2_ethtool_set_rxfh_context, 4214 }; 4215 4216 /* Used for PPv2.1, or PPv2.2 with the old Device Tree binding that 4217 * had a single IRQ defined per-port. 4218 */ 4219 static int mvpp2_simple_queue_vectors_init(struct mvpp2_port *port, 4220 struct device_node *port_node) 4221 { 4222 struct mvpp2_queue_vector *v = &port->qvecs[0]; 4223 4224 v->first_rxq = 0; 4225 v->nrxqs = port->nrxqs; 4226 v->type = MVPP2_QUEUE_VECTOR_SHARED; 4227 v->sw_thread_id = 0; 4228 v->sw_thread_mask = *cpumask_bits(cpu_online_mask); 4229 v->port = port; 4230 v->irq = irq_of_parse_and_map(port_node, 0); 4231 if (v->irq <= 0) 4232 return -EINVAL; 4233 netif_napi_add(port->dev, &v->napi, mvpp2_poll, 4234 NAPI_POLL_WEIGHT); 4235 4236 port->nqvecs = 1; 4237 4238 return 0; 4239 } 4240 4241 static int mvpp2_multi_queue_vectors_init(struct mvpp2_port *port, 4242 struct device_node *port_node) 4243 { 4244 struct mvpp2 *priv = port->priv; 4245 struct mvpp2_queue_vector *v; 4246 int i, ret; 4247 4248 switch (queue_mode) { 4249 case MVPP2_QDIST_SINGLE_MODE: 4250 port->nqvecs = priv->nthreads + 1; 4251 break; 4252 case MVPP2_QDIST_MULTI_MODE: 4253 port->nqvecs = priv->nthreads; 4254 break; 4255 } 4256 4257 for (i = 0; i < port->nqvecs; i++) { 4258 char irqname[16]; 4259 4260 v = port->qvecs + i; 4261 4262 v->port = port; 4263 v->type = MVPP2_QUEUE_VECTOR_PRIVATE; 4264 v->sw_thread_id = i; 4265 v->sw_thread_mask = BIT(i); 4266 4267 if (port->flags & MVPP2_F_DT_COMPAT) 4268 snprintf(irqname, sizeof(irqname), "tx-cpu%d", i); 4269 else 4270 snprintf(irqname, sizeof(irqname), "hif%d", i); 4271 4272 if (queue_mode == MVPP2_QDIST_MULTI_MODE) { 4273 v->first_rxq = i; 4274 v->nrxqs = 1; 4275 } else if (queue_mode == MVPP2_QDIST_SINGLE_MODE && 4276 i == (port->nqvecs - 1)) { 4277 v->first_rxq = 0; 4278 v->nrxqs = port->nrxqs; 4279 v->type = MVPP2_QUEUE_VECTOR_SHARED; 4280 4281 if (port->flags & MVPP2_F_DT_COMPAT) 4282 strncpy(irqname, "rx-shared", sizeof(irqname)); 4283 } 4284 4285 if (port_node) 4286 v->irq = of_irq_get_byname(port_node, irqname); 4287 else 4288 v->irq = fwnode_irq_get(port->fwnode, i); 4289 if (v->irq <= 0) { 4290 ret = -EINVAL; 4291 goto err; 4292 } 4293 4294 netif_napi_add(port->dev, &v->napi, mvpp2_poll, 4295 NAPI_POLL_WEIGHT); 4296 } 4297 4298 return 0; 4299 4300 err: 4301 for (i = 0; i < port->nqvecs; i++) 4302 irq_dispose_mapping(port->qvecs[i].irq); 4303 return ret; 4304 } 4305 4306 static int mvpp2_queue_vectors_init(struct mvpp2_port *port, 4307 struct device_node *port_node) 4308 { 4309 if (port->has_tx_irqs) 4310 return mvpp2_multi_queue_vectors_init(port, port_node); 4311 else 4312 return mvpp2_simple_queue_vectors_init(port, port_node); 4313 } 4314 4315 static void mvpp2_queue_vectors_deinit(struct mvpp2_port *port) 4316 { 4317 int i; 4318 4319 for (i = 0; i < port->nqvecs; i++) 4320 irq_dispose_mapping(port->qvecs[i].irq); 4321 } 4322 4323 /* Configure Rx queue group interrupt for this port */ 4324 static void mvpp2_rx_irqs_setup(struct mvpp2_port *port) 4325 { 4326 struct mvpp2 *priv = port->priv; 4327 u32 val; 4328 int i; 4329 4330 if (priv->hw_version == MVPP21) { 4331 mvpp2_write(priv, MVPP21_ISR_RXQ_GROUP_REG(port->id), 4332 port->nrxqs); 4333 return; 4334 } 4335 4336 /* Handle the more complicated PPv2.2 case */ 4337 for (i = 0; i < port->nqvecs; i++) { 4338 struct mvpp2_queue_vector *qv = port->qvecs + i; 4339 4340 if (!qv->nrxqs) 4341 continue; 4342 4343 val = qv->sw_thread_id; 4344 val |= port->id << MVPP22_ISR_RXQ_GROUP_INDEX_GROUP_OFFSET; 4345 mvpp2_write(priv, MVPP22_ISR_RXQ_GROUP_INDEX_REG, val); 4346 4347 val = qv->first_rxq; 4348 val |= qv->nrxqs << MVPP22_ISR_RXQ_SUB_GROUP_SIZE_OFFSET; 4349 mvpp2_write(priv, MVPP22_ISR_RXQ_SUB_GROUP_CONFIG_REG, val); 4350 } 4351 } 4352 4353 /* Initialize port HW */ 4354 static int mvpp2_port_init(struct mvpp2_port *port) 4355 { 4356 struct device *dev = port->dev->dev.parent; 4357 struct mvpp2 *priv = port->priv; 4358 struct mvpp2_txq_pcpu *txq_pcpu; 4359 unsigned int thread; 4360 int queue, err; 4361 4362 /* Checks for hardware constraints */ 4363 if (port->first_rxq + port->nrxqs > 4364 MVPP2_MAX_PORTS * priv->max_port_rxqs) 4365 return -EINVAL; 4366 4367 if (port->nrxqs > priv->max_port_rxqs || port->ntxqs > MVPP2_MAX_TXQ) 4368 return -EINVAL; 4369 4370 /* Disable port */ 4371 mvpp2_egress_disable(port); 4372 mvpp2_port_disable(port); 4373 4374 port->tx_time_coal = MVPP2_TXDONE_COAL_USEC; 4375 4376 port->txqs = devm_kcalloc(dev, port->ntxqs, sizeof(*port->txqs), 4377 GFP_KERNEL); 4378 if (!port->txqs) 4379 return -ENOMEM; 4380 4381 /* Associate physical Tx queues to this port and initialize. 4382 * The mapping is predefined. 4383 */ 4384 for (queue = 0; queue < port->ntxqs; queue++) { 4385 int queue_phy_id = mvpp2_txq_phys(port->id, queue); 4386 struct mvpp2_tx_queue *txq; 4387 4388 txq = devm_kzalloc(dev, sizeof(*txq), GFP_KERNEL); 4389 if (!txq) { 4390 err = -ENOMEM; 4391 goto err_free_percpu; 4392 } 4393 4394 txq->pcpu = alloc_percpu(struct mvpp2_txq_pcpu); 4395 if (!txq->pcpu) { 4396 err = -ENOMEM; 4397 goto err_free_percpu; 4398 } 4399 4400 txq->id = queue_phy_id; 4401 txq->log_id = queue; 4402 txq->done_pkts_coal = MVPP2_TXDONE_COAL_PKTS_THRESH; 4403 for (thread = 0; thread < priv->nthreads; thread++) { 4404 txq_pcpu = per_cpu_ptr(txq->pcpu, thread); 4405 txq_pcpu->thread = thread; 4406 } 4407 4408 port->txqs[queue] = txq; 4409 } 4410 4411 port->rxqs = devm_kcalloc(dev, port->nrxqs, sizeof(*port->rxqs), 4412 GFP_KERNEL); 4413 if (!port->rxqs) { 4414 err = -ENOMEM; 4415 goto err_free_percpu; 4416 } 4417 4418 /* Allocate and initialize Rx queue for this port */ 4419 for (queue = 0; queue < port->nrxqs; queue++) { 4420 struct mvpp2_rx_queue *rxq; 4421 4422 /* Map physical Rx queue to port's logical Rx queue */ 4423 rxq = devm_kzalloc(dev, sizeof(*rxq), GFP_KERNEL); 4424 if (!rxq) { 4425 err = -ENOMEM; 4426 goto err_free_percpu; 4427 } 4428 /* Map this Rx queue to a physical queue */ 4429 rxq->id = port->first_rxq + queue; 4430 rxq->port = port->id; 4431 rxq->logic_rxq = queue; 4432 4433 port->rxqs[queue] = rxq; 4434 } 4435 4436 mvpp2_rx_irqs_setup(port); 4437 4438 /* Create Rx descriptor rings */ 4439 for (queue = 0; queue < port->nrxqs; queue++) { 4440 struct mvpp2_rx_queue *rxq = port->rxqs[queue]; 4441 4442 rxq->size = port->rx_ring_size; 4443 rxq->pkts_coal = MVPP2_RX_COAL_PKTS; 4444 rxq->time_coal = MVPP2_RX_COAL_USEC; 4445 } 4446 4447 mvpp2_ingress_disable(port); 4448 4449 /* Port default configuration */ 4450 mvpp2_defaults_set(port); 4451 4452 /* Port's classifier configuration */ 4453 mvpp2_cls_oversize_rxq_set(port); 4454 mvpp2_cls_port_config(port); 4455 4456 if (mvpp22_rss_is_supported()) 4457 mvpp22_port_rss_init(port); 4458 4459 /* Provide an initial Rx packet size */ 4460 port->pkt_size = MVPP2_RX_PKT_SIZE(port->dev->mtu); 4461 4462 /* Initialize pools for swf */ 4463 err = mvpp2_swf_bm_pool_init(port); 4464 if (err) 4465 goto err_free_percpu; 4466 4467 /* Clear all port stats */ 4468 mvpp2_read_stats(port); 4469 memset(port->ethtool_stats, 0, 4470 MVPP2_N_ETHTOOL_STATS(port->ntxqs, port->nrxqs) * sizeof(u64)); 4471 4472 return 0; 4473 4474 err_free_percpu: 4475 for (queue = 0; queue < port->ntxqs; queue++) { 4476 if (!port->txqs[queue]) 4477 continue; 4478 free_percpu(port->txqs[queue]->pcpu); 4479 } 4480 return err; 4481 } 4482 4483 static bool mvpp22_port_has_legacy_tx_irqs(struct device_node *port_node, 4484 unsigned long *flags) 4485 { 4486 char *irqs[5] = { "rx-shared", "tx-cpu0", "tx-cpu1", "tx-cpu2", 4487 "tx-cpu3" }; 4488 int i; 4489 4490 for (i = 0; i < 5; i++) 4491 if (of_property_match_string(port_node, "interrupt-names", 4492 irqs[i]) < 0) 4493 return false; 4494 4495 *flags |= MVPP2_F_DT_COMPAT; 4496 return true; 4497 } 4498 4499 /* Checks if the port dt description has the required Tx interrupts: 4500 * - PPv2.1: there are no such interrupts. 4501 * - PPv2.2: 4502 * - The old DTs have: "rx-shared", "tx-cpuX" with X in [0...3] 4503 * - The new ones have: "hifX" with X in [0..8] 4504 * 4505 * All those variants are supported to keep the backward compatibility. 4506 */ 4507 static bool mvpp2_port_has_irqs(struct mvpp2 *priv, 4508 struct device_node *port_node, 4509 unsigned long *flags) 4510 { 4511 char name[5]; 4512 int i; 4513 4514 /* ACPI */ 4515 if (!port_node) 4516 return true; 4517 4518 if (priv->hw_version == MVPP21) 4519 return false; 4520 4521 if (mvpp22_port_has_legacy_tx_irqs(port_node, flags)) 4522 return true; 4523 4524 for (i = 0; i < MVPP2_MAX_THREADS; i++) { 4525 snprintf(name, 5, "hif%d", i); 4526 if (of_property_match_string(port_node, "interrupt-names", 4527 name) < 0) 4528 return false; 4529 } 4530 4531 return true; 4532 } 4533 4534 static void mvpp2_port_copy_mac_addr(struct net_device *dev, struct mvpp2 *priv, 4535 struct fwnode_handle *fwnode, 4536 char **mac_from) 4537 { 4538 struct mvpp2_port *port = netdev_priv(dev); 4539 char hw_mac_addr[ETH_ALEN] = {0}; 4540 char fw_mac_addr[ETH_ALEN]; 4541 4542 if (fwnode_get_mac_address(fwnode, fw_mac_addr, ETH_ALEN)) { 4543 *mac_from = "firmware node"; 4544 ether_addr_copy(dev->dev_addr, fw_mac_addr); 4545 return; 4546 } 4547 4548 if (priv->hw_version == MVPP21) { 4549 mvpp21_get_mac_address(port, hw_mac_addr); 4550 if (is_valid_ether_addr(hw_mac_addr)) { 4551 *mac_from = "hardware"; 4552 ether_addr_copy(dev->dev_addr, hw_mac_addr); 4553 return; 4554 } 4555 } 4556 4557 *mac_from = "random"; 4558 eth_hw_addr_random(dev); 4559 } 4560 4561 static void mvpp2_phylink_validate(struct phylink_config *config, 4562 unsigned long *supported, 4563 struct phylink_link_state *state) 4564 { 4565 struct mvpp2_port *port = container_of(config, struct mvpp2_port, 4566 phylink_config); 4567 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, }; 4568 4569 /* Invalid combinations */ 4570 switch (state->interface) { 4571 case PHY_INTERFACE_MODE_10GKR: 4572 case PHY_INTERFACE_MODE_XAUI: 4573 if (port->gop_id != 0) 4574 goto empty_set; 4575 break; 4576 case PHY_INTERFACE_MODE_RGMII: 4577 case PHY_INTERFACE_MODE_RGMII_ID: 4578 case PHY_INTERFACE_MODE_RGMII_RXID: 4579 case PHY_INTERFACE_MODE_RGMII_TXID: 4580 if (port->priv->hw_version == MVPP22 && port->gop_id == 0) 4581 goto empty_set; 4582 break; 4583 default: 4584 break; 4585 } 4586 4587 phylink_set(mask, Autoneg); 4588 phylink_set_port_modes(mask); 4589 phylink_set(mask, Pause); 4590 phylink_set(mask, Asym_Pause); 4591 4592 switch (state->interface) { 4593 case PHY_INTERFACE_MODE_10GKR: 4594 case PHY_INTERFACE_MODE_XAUI: 4595 case PHY_INTERFACE_MODE_NA: 4596 if (port->gop_id == 0) { 4597 phylink_set(mask, 10000baseT_Full); 4598 phylink_set(mask, 10000baseCR_Full); 4599 phylink_set(mask, 10000baseSR_Full); 4600 phylink_set(mask, 10000baseLR_Full); 4601 phylink_set(mask, 10000baseLRM_Full); 4602 phylink_set(mask, 10000baseER_Full); 4603 phylink_set(mask, 10000baseKR_Full); 4604 } 4605 /* Fall-through */ 4606 case PHY_INTERFACE_MODE_RGMII: 4607 case PHY_INTERFACE_MODE_RGMII_ID: 4608 case PHY_INTERFACE_MODE_RGMII_RXID: 4609 case PHY_INTERFACE_MODE_RGMII_TXID: 4610 case PHY_INTERFACE_MODE_SGMII: 4611 phylink_set(mask, 10baseT_Half); 4612 phylink_set(mask, 10baseT_Full); 4613 phylink_set(mask, 100baseT_Half); 4614 phylink_set(mask, 100baseT_Full); 4615 /* Fall-through */ 4616 case PHY_INTERFACE_MODE_1000BASEX: 4617 case PHY_INTERFACE_MODE_2500BASEX: 4618 phylink_set(mask, 1000baseT_Full); 4619 phylink_set(mask, 1000baseX_Full); 4620 phylink_set(mask, 2500baseT_Full); 4621 phylink_set(mask, 2500baseX_Full); 4622 break; 4623 default: 4624 goto empty_set; 4625 } 4626 4627 bitmap_and(supported, supported, mask, __ETHTOOL_LINK_MODE_MASK_NBITS); 4628 bitmap_and(state->advertising, state->advertising, mask, 4629 __ETHTOOL_LINK_MODE_MASK_NBITS); 4630 return; 4631 4632 empty_set: 4633 bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS); 4634 } 4635 4636 static void mvpp22_xlg_link_state(struct mvpp2_port *port, 4637 struct phylink_link_state *state) 4638 { 4639 u32 val; 4640 4641 state->speed = SPEED_10000; 4642 state->duplex = 1; 4643 state->an_complete = 1; 4644 4645 val = readl(port->base + MVPP22_XLG_STATUS); 4646 state->link = !!(val & MVPP22_XLG_STATUS_LINK_UP); 4647 4648 state->pause = 0; 4649 val = readl(port->base + MVPP22_XLG_CTRL0_REG); 4650 if (val & MVPP22_XLG_CTRL0_TX_FLOW_CTRL_EN) 4651 state->pause |= MLO_PAUSE_TX; 4652 if (val & MVPP22_XLG_CTRL0_RX_FLOW_CTRL_EN) 4653 state->pause |= MLO_PAUSE_RX; 4654 } 4655 4656 static void mvpp2_gmac_link_state(struct mvpp2_port *port, 4657 struct phylink_link_state *state) 4658 { 4659 u32 val; 4660 4661 val = readl(port->base + MVPP2_GMAC_STATUS0); 4662 4663 state->an_complete = !!(val & MVPP2_GMAC_STATUS0_AN_COMPLETE); 4664 state->link = !!(val & MVPP2_GMAC_STATUS0_LINK_UP); 4665 state->duplex = !!(val & MVPP2_GMAC_STATUS0_FULL_DUPLEX); 4666 4667 switch (port->phy_interface) { 4668 case PHY_INTERFACE_MODE_1000BASEX: 4669 state->speed = SPEED_1000; 4670 break; 4671 case PHY_INTERFACE_MODE_2500BASEX: 4672 state->speed = SPEED_2500; 4673 break; 4674 default: 4675 if (val & MVPP2_GMAC_STATUS0_GMII_SPEED) 4676 state->speed = SPEED_1000; 4677 else if (val & MVPP2_GMAC_STATUS0_MII_SPEED) 4678 state->speed = SPEED_100; 4679 else 4680 state->speed = SPEED_10; 4681 } 4682 4683 state->pause = 0; 4684 if (val & MVPP2_GMAC_STATUS0_RX_PAUSE) 4685 state->pause |= MLO_PAUSE_RX; 4686 if (val & MVPP2_GMAC_STATUS0_TX_PAUSE) 4687 state->pause |= MLO_PAUSE_TX; 4688 } 4689 4690 static int mvpp2_phylink_mac_link_state(struct phylink_config *config, 4691 struct phylink_link_state *state) 4692 { 4693 struct mvpp2_port *port = container_of(config, struct mvpp2_port, 4694 phylink_config); 4695 4696 if (port->priv->hw_version == MVPP22 && port->gop_id == 0) { 4697 u32 mode = readl(port->base + MVPP22_XLG_CTRL3_REG); 4698 mode &= MVPP22_XLG_CTRL3_MACMODESELECT_MASK; 4699 4700 if (mode == MVPP22_XLG_CTRL3_MACMODESELECT_10G) { 4701 mvpp22_xlg_link_state(port, state); 4702 return 1; 4703 } 4704 } 4705 4706 mvpp2_gmac_link_state(port, state); 4707 return 1; 4708 } 4709 4710 static void mvpp2_mac_an_restart(struct phylink_config *config) 4711 { 4712 struct mvpp2_port *port = container_of(config, struct mvpp2_port, 4713 phylink_config); 4714 u32 val = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG); 4715 4716 writel(val | MVPP2_GMAC_IN_BAND_RESTART_AN, 4717 port->base + MVPP2_GMAC_AUTONEG_CONFIG); 4718 writel(val & ~MVPP2_GMAC_IN_BAND_RESTART_AN, 4719 port->base + MVPP2_GMAC_AUTONEG_CONFIG); 4720 } 4721 4722 static void mvpp2_xlg_config(struct mvpp2_port *port, unsigned int mode, 4723 const struct phylink_link_state *state) 4724 { 4725 u32 old_ctrl0, ctrl0; 4726 u32 old_ctrl4, ctrl4; 4727 4728 old_ctrl0 = ctrl0 = readl(port->base + MVPP22_XLG_CTRL0_REG); 4729 old_ctrl4 = ctrl4 = readl(port->base + MVPP22_XLG_CTRL4_REG); 4730 4731 ctrl0 |= MVPP22_XLG_CTRL0_MAC_RESET_DIS; 4732 4733 if (state->pause & MLO_PAUSE_TX) 4734 ctrl0 |= MVPP22_XLG_CTRL0_TX_FLOW_CTRL_EN; 4735 else 4736 ctrl0 &= ~MVPP22_XLG_CTRL0_TX_FLOW_CTRL_EN; 4737 4738 if (state->pause & MLO_PAUSE_RX) 4739 ctrl0 |= MVPP22_XLG_CTRL0_RX_FLOW_CTRL_EN; 4740 else 4741 ctrl0 &= ~MVPP22_XLG_CTRL0_RX_FLOW_CTRL_EN; 4742 4743 ctrl4 &= ~MVPP22_XLG_CTRL4_MACMODSELECT_GMAC; 4744 ctrl4 |= MVPP22_XLG_CTRL4_FWD_FC | MVPP22_XLG_CTRL4_FWD_PFC | 4745 MVPP22_XLG_CTRL4_EN_IDLE_CHECK; 4746 4747 if (old_ctrl0 != ctrl0) 4748 writel(ctrl0, port->base + MVPP22_XLG_CTRL0_REG); 4749 if (old_ctrl4 != ctrl4) 4750 writel(ctrl4, port->base + MVPP22_XLG_CTRL4_REG); 4751 4752 if (!(old_ctrl0 & MVPP22_XLG_CTRL0_MAC_RESET_DIS)) { 4753 while (!(readl(port->base + MVPP22_XLG_CTRL0_REG) & 4754 MVPP22_XLG_CTRL0_MAC_RESET_DIS)) 4755 continue; 4756 } 4757 } 4758 4759 static void mvpp2_gmac_config(struct mvpp2_port *port, unsigned int mode, 4760 const struct phylink_link_state *state) 4761 { 4762 u32 old_an, an; 4763 u32 old_ctrl0, ctrl0; 4764 u32 old_ctrl2, ctrl2; 4765 u32 old_ctrl4, ctrl4; 4766 4767 old_an = an = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG); 4768 old_ctrl0 = ctrl0 = readl(port->base + MVPP2_GMAC_CTRL_0_REG); 4769 old_ctrl2 = ctrl2 = readl(port->base + MVPP2_GMAC_CTRL_2_REG); 4770 old_ctrl4 = ctrl4 = readl(port->base + MVPP22_GMAC_CTRL_4_REG); 4771 4772 an &= ~(MVPP2_GMAC_CONFIG_MII_SPEED | MVPP2_GMAC_CONFIG_GMII_SPEED | 4773 MVPP2_GMAC_AN_SPEED_EN | MVPP2_GMAC_FC_ADV_EN | 4774 MVPP2_GMAC_FC_ADV_ASM_EN | MVPP2_GMAC_FLOW_CTRL_AUTONEG | 4775 MVPP2_GMAC_CONFIG_FULL_DUPLEX | MVPP2_GMAC_AN_DUPLEX_EN | 4776 MVPP2_GMAC_IN_BAND_AUTONEG | MVPP2_GMAC_IN_BAND_AUTONEG_BYPASS); 4777 ctrl0 &= ~MVPP2_GMAC_PORT_TYPE_MASK; 4778 ctrl2 &= ~(MVPP2_GMAC_INBAND_AN_MASK | MVPP2_GMAC_PORT_RESET_MASK | 4779 MVPP2_GMAC_PCS_ENABLE_MASK); 4780 ctrl4 &= ~(MVPP22_CTRL4_RX_FC_EN | MVPP22_CTRL4_TX_FC_EN); 4781 4782 /* Configure port type */ 4783 if (phy_interface_mode_is_8023z(state->interface)) { 4784 ctrl2 |= MVPP2_GMAC_PCS_ENABLE_MASK; 4785 ctrl4 &= ~MVPP22_CTRL4_EXT_PIN_GMII_SEL; 4786 ctrl4 |= MVPP22_CTRL4_SYNC_BYPASS_DIS | 4787 MVPP22_CTRL4_DP_CLK_SEL | 4788 MVPP22_CTRL4_QSGMII_BYPASS_ACTIVE; 4789 } else if (state->interface == PHY_INTERFACE_MODE_SGMII) { 4790 ctrl2 |= MVPP2_GMAC_PCS_ENABLE_MASK | MVPP2_GMAC_INBAND_AN_MASK; 4791 ctrl4 &= ~MVPP22_CTRL4_EXT_PIN_GMII_SEL; 4792 ctrl4 |= MVPP22_CTRL4_SYNC_BYPASS_DIS | 4793 MVPP22_CTRL4_DP_CLK_SEL | 4794 MVPP22_CTRL4_QSGMII_BYPASS_ACTIVE; 4795 } else if (phy_interface_mode_is_rgmii(state->interface)) { 4796 ctrl4 &= ~MVPP22_CTRL4_DP_CLK_SEL; 4797 ctrl4 |= MVPP22_CTRL4_EXT_PIN_GMII_SEL | 4798 MVPP22_CTRL4_SYNC_BYPASS_DIS | 4799 MVPP22_CTRL4_QSGMII_BYPASS_ACTIVE; 4800 } 4801 4802 /* Configure advertisement bits */ 4803 if (phylink_test(state->advertising, Pause)) 4804 an |= MVPP2_GMAC_FC_ADV_EN; 4805 if (phylink_test(state->advertising, Asym_Pause)) 4806 an |= MVPP2_GMAC_FC_ADV_ASM_EN; 4807 4808 /* Configure negotiation style */ 4809 if (!phylink_autoneg_inband(mode)) { 4810 /* Phy or fixed speed - no in-band AN */ 4811 if (state->duplex) 4812 an |= MVPP2_GMAC_CONFIG_FULL_DUPLEX; 4813 4814 if (state->speed == SPEED_1000 || state->speed == SPEED_2500) 4815 an |= MVPP2_GMAC_CONFIG_GMII_SPEED; 4816 else if (state->speed == SPEED_100) 4817 an |= MVPP2_GMAC_CONFIG_MII_SPEED; 4818 4819 if (state->pause & MLO_PAUSE_TX) 4820 ctrl4 |= MVPP22_CTRL4_TX_FC_EN; 4821 if (state->pause & MLO_PAUSE_RX) 4822 ctrl4 |= MVPP22_CTRL4_RX_FC_EN; 4823 } else if (state->interface == PHY_INTERFACE_MODE_SGMII) { 4824 /* SGMII in-band mode receives the speed and duplex from 4825 * the PHY. Flow control information is not received. */ 4826 an &= ~(MVPP2_GMAC_FORCE_LINK_DOWN | MVPP2_GMAC_FORCE_LINK_PASS); 4827 an |= MVPP2_GMAC_IN_BAND_AUTONEG | 4828 MVPP2_GMAC_AN_SPEED_EN | 4829 MVPP2_GMAC_AN_DUPLEX_EN; 4830 4831 if (state->pause & MLO_PAUSE_TX) 4832 ctrl4 |= MVPP22_CTRL4_TX_FC_EN; 4833 if (state->pause & MLO_PAUSE_RX) 4834 ctrl4 |= MVPP22_CTRL4_RX_FC_EN; 4835 } else if (phy_interface_mode_is_8023z(state->interface)) { 4836 /* 1000BaseX and 2500BaseX ports cannot negotiate speed nor can 4837 * they negotiate duplex: they are always operating with a fixed 4838 * speed of 1000/2500Mbps in full duplex, so force 1000/2500 4839 * speed and full duplex here. 4840 */ 4841 ctrl0 |= MVPP2_GMAC_PORT_TYPE_MASK; 4842 an &= ~(MVPP2_GMAC_FORCE_LINK_DOWN | MVPP2_GMAC_FORCE_LINK_PASS); 4843 an |= MVPP2_GMAC_IN_BAND_AUTONEG | 4844 MVPP2_GMAC_CONFIG_GMII_SPEED | 4845 MVPP2_GMAC_CONFIG_FULL_DUPLEX; 4846 4847 if (state->pause & MLO_PAUSE_AN && state->an_enabled) { 4848 an |= MVPP2_GMAC_FLOW_CTRL_AUTONEG; 4849 } else { 4850 if (state->pause & MLO_PAUSE_TX) 4851 ctrl4 |= MVPP22_CTRL4_TX_FC_EN; 4852 if (state->pause & MLO_PAUSE_RX) 4853 ctrl4 |= MVPP22_CTRL4_RX_FC_EN; 4854 } 4855 } 4856 4857 /* Some fields of the auto-negotiation register require the port to be down when 4858 * their value is updated. 4859 */ 4860 #define MVPP2_GMAC_AN_PORT_DOWN_MASK \ 4861 (MVPP2_GMAC_IN_BAND_AUTONEG | \ 4862 MVPP2_GMAC_IN_BAND_AUTONEG_BYPASS | \ 4863 MVPP2_GMAC_CONFIG_MII_SPEED | MVPP2_GMAC_CONFIG_GMII_SPEED | \ 4864 MVPP2_GMAC_AN_SPEED_EN | MVPP2_GMAC_CONFIG_FULL_DUPLEX | \ 4865 MVPP2_GMAC_AN_DUPLEX_EN) 4866 4867 if ((old_ctrl0 ^ ctrl0) & MVPP2_GMAC_PORT_TYPE_MASK || 4868 (old_ctrl2 ^ ctrl2) & MVPP2_GMAC_INBAND_AN_MASK || 4869 (old_an ^ an) & MVPP2_GMAC_AN_PORT_DOWN_MASK) { 4870 /* Force link down */ 4871 old_an &= ~MVPP2_GMAC_FORCE_LINK_PASS; 4872 old_an |= MVPP2_GMAC_FORCE_LINK_DOWN; 4873 writel(old_an, port->base + MVPP2_GMAC_AUTONEG_CONFIG); 4874 4875 /* Set the GMAC in a reset state - do this in a way that 4876 * ensures we clear it below. 4877 */ 4878 old_ctrl2 |= MVPP2_GMAC_PORT_RESET_MASK; 4879 writel(old_ctrl2, port->base + MVPP2_GMAC_CTRL_2_REG); 4880 } 4881 4882 if (old_ctrl0 != ctrl0) 4883 writel(ctrl0, port->base + MVPP2_GMAC_CTRL_0_REG); 4884 if (old_ctrl2 != ctrl2) 4885 writel(ctrl2, port->base + MVPP2_GMAC_CTRL_2_REG); 4886 if (old_ctrl4 != ctrl4) 4887 writel(ctrl4, port->base + MVPP22_GMAC_CTRL_4_REG); 4888 if (old_an != an) 4889 writel(an, port->base + MVPP2_GMAC_AUTONEG_CONFIG); 4890 4891 if (old_ctrl2 & MVPP2_GMAC_PORT_RESET_MASK) { 4892 while (readl(port->base + MVPP2_GMAC_CTRL_2_REG) & 4893 MVPP2_GMAC_PORT_RESET_MASK) 4894 continue; 4895 } 4896 } 4897 4898 static void mvpp2_mac_config(struct phylink_config *config, unsigned int mode, 4899 const struct phylink_link_state *state) 4900 { 4901 struct net_device *dev = to_net_dev(config->dev); 4902 struct mvpp2_port *port = netdev_priv(dev); 4903 bool change_interface = port->phy_interface != state->interface; 4904 4905 /* Check for invalid configuration */ 4906 if (mvpp2_is_xlg(state->interface) && port->gop_id != 0) { 4907 netdev_err(dev, "Invalid mode on %s\n", dev->name); 4908 return; 4909 } 4910 4911 /* Make sure the port is disabled when reconfiguring the mode */ 4912 mvpp2_port_disable(port); 4913 4914 if (port->priv->hw_version == MVPP22 && change_interface) { 4915 mvpp22_gop_mask_irq(port); 4916 4917 port->phy_interface = state->interface; 4918 4919 /* Reconfigure the serdes lanes */ 4920 phy_power_off(port->comphy); 4921 mvpp22_mode_reconfigure(port); 4922 } 4923 4924 /* mac (re)configuration */ 4925 if (mvpp2_is_xlg(state->interface)) 4926 mvpp2_xlg_config(port, mode, state); 4927 else if (phy_interface_mode_is_rgmii(state->interface) || 4928 phy_interface_mode_is_8023z(state->interface) || 4929 state->interface == PHY_INTERFACE_MODE_SGMII) 4930 mvpp2_gmac_config(port, mode, state); 4931 4932 if (port->priv->hw_version == MVPP21 && port->flags & MVPP2_F_LOOPBACK) 4933 mvpp2_port_loopback_set(port, state); 4934 4935 if (port->priv->hw_version == MVPP22 && change_interface) 4936 mvpp22_gop_unmask_irq(port); 4937 4938 mvpp2_port_enable(port); 4939 } 4940 4941 static void mvpp2_mac_link_up(struct phylink_config *config, unsigned int mode, 4942 phy_interface_t interface, struct phy_device *phy) 4943 { 4944 struct net_device *dev = to_net_dev(config->dev); 4945 struct mvpp2_port *port = netdev_priv(dev); 4946 u32 val; 4947 4948 if (!phylink_autoneg_inband(mode)) { 4949 if (mvpp2_is_xlg(interface)) { 4950 val = readl(port->base + MVPP22_XLG_CTRL0_REG); 4951 val &= ~MVPP22_XLG_CTRL0_FORCE_LINK_DOWN; 4952 val |= MVPP22_XLG_CTRL0_FORCE_LINK_PASS; 4953 writel(val, port->base + MVPP22_XLG_CTRL0_REG); 4954 } else { 4955 val = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG); 4956 val &= ~MVPP2_GMAC_FORCE_LINK_DOWN; 4957 val |= MVPP2_GMAC_FORCE_LINK_PASS; 4958 writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG); 4959 } 4960 } 4961 4962 mvpp2_port_enable(port); 4963 4964 mvpp2_egress_enable(port); 4965 mvpp2_ingress_enable(port); 4966 netif_tx_wake_all_queues(dev); 4967 } 4968 4969 static void mvpp2_mac_link_down(struct phylink_config *config, 4970 unsigned int mode, phy_interface_t interface) 4971 { 4972 struct net_device *dev = to_net_dev(config->dev); 4973 struct mvpp2_port *port = netdev_priv(dev); 4974 u32 val; 4975 4976 if (!phylink_autoneg_inband(mode)) { 4977 if (mvpp2_is_xlg(interface)) { 4978 val = readl(port->base + MVPP22_XLG_CTRL0_REG); 4979 val &= ~MVPP22_XLG_CTRL0_FORCE_LINK_PASS; 4980 val |= MVPP22_XLG_CTRL0_FORCE_LINK_DOWN; 4981 writel(val, port->base + MVPP22_XLG_CTRL0_REG); 4982 } else { 4983 val = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG); 4984 val &= ~MVPP2_GMAC_FORCE_LINK_PASS; 4985 val |= MVPP2_GMAC_FORCE_LINK_DOWN; 4986 writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG); 4987 } 4988 } 4989 4990 netif_tx_stop_all_queues(dev); 4991 mvpp2_egress_disable(port); 4992 mvpp2_ingress_disable(port); 4993 4994 mvpp2_port_disable(port); 4995 } 4996 4997 static const struct phylink_mac_ops mvpp2_phylink_ops = { 4998 .validate = mvpp2_phylink_validate, 4999 .mac_link_state = mvpp2_phylink_mac_link_state, 5000 .mac_an_restart = mvpp2_mac_an_restart, 5001 .mac_config = mvpp2_mac_config, 5002 .mac_link_up = mvpp2_mac_link_up, 5003 .mac_link_down = mvpp2_mac_link_down, 5004 }; 5005 5006 /* Ports initialization */ 5007 static int mvpp2_port_probe(struct platform_device *pdev, 5008 struct fwnode_handle *port_fwnode, 5009 struct mvpp2 *priv) 5010 { 5011 struct phy *comphy = NULL; 5012 struct mvpp2_port *port; 5013 struct mvpp2_port_pcpu *port_pcpu; 5014 struct device_node *port_node = to_of_node(port_fwnode); 5015 netdev_features_t features; 5016 struct net_device *dev; 5017 struct phylink *phylink; 5018 char *mac_from = ""; 5019 unsigned int ntxqs, nrxqs, thread; 5020 unsigned long flags = 0; 5021 bool has_tx_irqs; 5022 u32 id; 5023 int phy_mode; 5024 int err, i; 5025 5026 has_tx_irqs = mvpp2_port_has_irqs(priv, port_node, &flags); 5027 if (!has_tx_irqs && queue_mode == MVPP2_QDIST_MULTI_MODE) { 5028 dev_err(&pdev->dev, 5029 "not enough IRQs to support multi queue mode\n"); 5030 return -EINVAL; 5031 } 5032 5033 ntxqs = MVPP2_MAX_TXQ; 5034 if (priv->hw_version == MVPP22 && queue_mode == MVPP2_QDIST_SINGLE_MODE) { 5035 nrxqs = 1; 5036 } else { 5037 /* According to the PPv2.2 datasheet and our experiments on 5038 * PPv2.1, RX queues have an allocation granularity of 4 (when 5039 * more than a single one on PPv2.2). 5040 * Round up to nearest multiple of 4. 5041 */ 5042 nrxqs = (num_possible_cpus() + 3) & ~0x3; 5043 if (nrxqs > MVPP2_PORT_MAX_RXQ) 5044 nrxqs = MVPP2_PORT_MAX_RXQ; 5045 } 5046 5047 dev = alloc_etherdev_mqs(sizeof(*port), ntxqs, nrxqs); 5048 if (!dev) 5049 return -ENOMEM; 5050 5051 phy_mode = fwnode_get_phy_mode(port_fwnode); 5052 if (phy_mode < 0) { 5053 dev_err(&pdev->dev, "incorrect phy mode\n"); 5054 err = phy_mode; 5055 goto err_free_netdev; 5056 } 5057 5058 if (port_node) { 5059 comphy = devm_of_phy_get(&pdev->dev, port_node, NULL); 5060 if (IS_ERR(comphy)) { 5061 if (PTR_ERR(comphy) == -EPROBE_DEFER) { 5062 err = -EPROBE_DEFER; 5063 goto err_free_netdev; 5064 } 5065 comphy = NULL; 5066 } 5067 } 5068 5069 if (fwnode_property_read_u32(port_fwnode, "port-id", &id)) { 5070 err = -EINVAL; 5071 dev_err(&pdev->dev, "missing port-id value\n"); 5072 goto err_free_netdev; 5073 } 5074 5075 dev->tx_queue_len = MVPP2_MAX_TXD_MAX; 5076 dev->watchdog_timeo = 5 * HZ; 5077 dev->netdev_ops = &mvpp2_netdev_ops; 5078 dev->ethtool_ops = &mvpp2_eth_tool_ops; 5079 5080 port = netdev_priv(dev); 5081 port->dev = dev; 5082 port->fwnode = port_fwnode; 5083 port->has_phy = !!of_find_property(port_node, "phy", NULL); 5084 port->ntxqs = ntxqs; 5085 port->nrxqs = nrxqs; 5086 port->priv = priv; 5087 port->has_tx_irqs = has_tx_irqs; 5088 port->flags = flags; 5089 5090 err = mvpp2_queue_vectors_init(port, port_node); 5091 if (err) 5092 goto err_free_netdev; 5093 5094 if (port_node) 5095 port->link_irq = of_irq_get_byname(port_node, "link"); 5096 else 5097 port->link_irq = fwnode_irq_get(port_fwnode, port->nqvecs + 1); 5098 if (port->link_irq == -EPROBE_DEFER) { 5099 err = -EPROBE_DEFER; 5100 goto err_deinit_qvecs; 5101 } 5102 if (port->link_irq <= 0) 5103 /* the link irq is optional */ 5104 port->link_irq = 0; 5105 5106 if (fwnode_property_read_bool(port_fwnode, "marvell,loopback")) 5107 port->flags |= MVPP2_F_LOOPBACK; 5108 5109 port->id = id; 5110 if (priv->hw_version == MVPP21) 5111 port->first_rxq = port->id * port->nrxqs; 5112 else 5113 port->first_rxq = port->id * priv->max_port_rxqs; 5114 5115 port->of_node = port_node; 5116 port->phy_interface = phy_mode; 5117 port->comphy = comphy; 5118 5119 if (priv->hw_version == MVPP21) { 5120 port->base = devm_platform_ioremap_resource(pdev, 2 + id); 5121 if (IS_ERR(port->base)) { 5122 err = PTR_ERR(port->base); 5123 goto err_free_irq; 5124 } 5125 5126 port->stats_base = port->priv->lms_base + 5127 MVPP21_MIB_COUNTERS_OFFSET + 5128 port->gop_id * MVPP21_MIB_COUNTERS_PORT_SZ; 5129 } else { 5130 if (fwnode_property_read_u32(port_fwnode, "gop-port-id", 5131 &port->gop_id)) { 5132 err = -EINVAL; 5133 dev_err(&pdev->dev, "missing gop-port-id value\n"); 5134 goto err_deinit_qvecs; 5135 } 5136 5137 port->base = priv->iface_base + MVPP22_GMAC_BASE(port->gop_id); 5138 port->stats_base = port->priv->iface_base + 5139 MVPP22_MIB_COUNTERS_OFFSET + 5140 port->gop_id * MVPP22_MIB_COUNTERS_PORT_SZ; 5141 } 5142 5143 /* Alloc per-cpu and ethtool stats */ 5144 port->stats = netdev_alloc_pcpu_stats(struct mvpp2_pcpu_stats); 5145 if (!port->stats) { 5146 err = -ENOMEM; 5147 goto err_free_irq; 5148 } 5149 5150 port->ethtool_stats = devm_kcalloc(&pdev->dev, 5151 MVPP2_N_ETHTOOL_STATS(ntxqs, nrxqs), 5152 sizeof(u64), GFP_KERNEL); 5153 if (!port->ethtool_stats) { 5154 err = -ENOMEM; 5155 goto err_free_stats; 5156 } 5157 5158 mutex_init(&port->gather_stats_lock); 5159 INIT_DELAYED_WORK(&port->stats_work, mvpp2_gather_hw_statistics); 5160 5161 mvpp2_port_copy_mac_addr(dev, priv, port_fwnode, &mac_from); 5162 5163 port->tx_ring_size = MVPP2_MAX_TXD_DFLT; 5164 port->rx_ring_size = MVPP2_MAX_RXD_DFLT; 5165 SET_NETDEV_DEV(dev, &pdev->dev); 5166 5167 err = mvpp2_port_init(port); 5168 if (err < 0) { 5169 dev_err(&pdev->dev, "failed to init port %d\n", id); 5170 goto err_free_stats; 5171 } 5172 5173 mvpp2_port_periodic_xon_disable(port); 5174 5175 mvpp2_mac_reset_assert(port); 5176 mvpp22_pcs_reset_assert(port); 5177 5178 port->pcpu = alloc_percpu(struct mvpp2_port_pcpu); 5179 if (!port->pcpu) { 5180 err = -ENOMEM; 5181 goto err_free_txq_pcpu; 5182 } 5183 5184 if (!port->has_tx_irqs) { 5185 for (thread = 0; thread < priv->nthreads; thread++) { 5186 port_pcpu = per_cpu_ptr(port->pcpu, thread); 5187 5188 hrtimer_init(&port_pcpu->tx_done_timer, CLOCK_MONOTONIC, 5189 HRTIMER_MODE_REL_PINNED); 5190 port_pcpu->tx_done_timer.function = mvpp2_hr_timer_cb; 5191 port_pcpu->timer_scheduled = false; 5192 5193 tasklet_init(&port_pcpu->tx_done_tasklet, 5194 mvpp2_tx_proc_cb, 5195 (unsigned long)dev); 5196 } 5197 } 5198 5199 features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | 5200 NETIF_F_TSO; 5201 dev->features = features | NETIF_F_RXCSUM; 5202 dev->hw_features |= features | NETIF_F_RXCSUM | NETIF_F_GRO | 5203 NETIF_F_HW_VLAN_CTAG_FILTER; 5204 5205 if (mvpp22_rss_is_supported()) { 5206 dev->hw_features |= NETIF_F_RXHASH; 5207 dev->features |= NETIF_F_NTUPLE; 5208 } 5209 5210 if (port->pool_long->id == MVPP2_BM_JUMBO && port->id != 0) { 5211 dev->features &= ~(NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM); 5212 dev->hw_features &= ~(NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM); 5213 } 5214 5215 dev->vlan_features |= features; 5216 dev->gso_max_segs = MVPP2_MAX_TSO_SEGS; 5217 dev->priv_flags |= IFF_UNICAST_FLT; 5218 5219 /* MTU range: 68 - 9704 */ 5220 dev->min_mtu = ETH_MIN_MTU; 5221 /* 9704 == 9728 - 20 and rounding to 8 */ 5222 dev->max_mtu = MVPP2_BM_JUMBO_PKT_SIZE; 5223 dev->dev.of_node = port_node; 5224 5225 /* Phylink isn't used w/ ACPI as of now */ 5226 if (port_node) { 5227 port->phylink_config.dev = &dev->dev; 5228 port->phylink_config.type = PHYLINK_NETDEV; 5229 5230 phylink = phylink_create(&port->phylink_config, port_fwnode, 5231 phy_mode, &mvpp2_phylink_ops); 5232 if (IS_ERR(phylink)) { 5233 err = PTR_ERR(phylink); 5234 goto err_free_port_pcpu; 5235 } 5236 port->phylink = phylink; 5237 } else { 5238 port->phylink = NULL; 5239 } 5240 5241 err = register_netdev(dev); 5242 if (err < 0) { 5243 dev_err(&pdev->dev, "failed to register netdev\n"); 5244 goto err_phylink; 5245 } 5246 netdev_info(dev, "Using %s mac address %pM\n", mac_from, dev->dev_addr); 5247 5248 priv->port_list[priv->port_count++] = port; 5249 5250 return 0; 5251 5252 err_phylink: 5253 if (port->phylink) 5254 phylink_destroy(port->phylink); 5255 err_free_port_pcpu: 5256 free_percpu(port->pcpu); 5257 err_free_txq_pcpu: 5258 for (i = 0; i < port->ntxqs; i++) 5259 free_percpu(port->txqs[i]->pcpu); 5260 err_free_stats: 5261 free_percpu(port->stats); 5262 err_free_irq: 5263 if (port->link_irq) 5264 irq_dispose_mapping(port->link_irq); 5265 err_deinit_qvecs: 5266 mvpp2_queue_vectors_deinit(port); 5267 err_free_netdev: 5268 free_netdev(dev); 5269 return err; 5270 } 5271 5272 /* Ports removal routine */ 5273 static void mvpp2_port_remove(struct mvpp2_port *port) 5274 { 5275 int i; 5276 5277 unregister_netdev(port->dev); 5278 if (port->phylink) 5279 phylink_destroy(port->phylink); 5280 free_percpu(port->pcpu); 5281 free_percpu(port->stats); 5282 for (i = 0; i < port->ntxqs; i++) 5283 free_percpu(port->txqs[i]->pcpu); 5284 mvpp2_queue_vectors_deinit(port); 5285 if (port->link_irq) 5286 irq_dispose_mapping(port->link_irq); 5287 free_netdev(port->dev); 5288 } 5289 5290 /* Initialize decoding windows */ 5291 static void mvpp2_conf_mbus_windows(const struct mbus_dram_target_info *dram, 5292 struct mvpp2 *priv) 5293 { 5294 u32 win_enable; 5295 int i; 5296 5297 for (i = 0; i < 6; i++) { 5298 mvpp2_write(priv, MVPP2_WIN_BASE(i), 0); 5299 mvpp2_write(priv, MVPP2_WIN_SIZE(i), 0); 5300 5301 if (i < 4) 5302 mvpp2_write(priv, MVPP2_WIN_REMAP(i), 0); 5303 } 5304 5305 win_enable = 0; 5306 5307 for (i = 0; i < dram->num_cs; i++) { 5308 const struct mbus_dram_window *cs = dram->cs + i; 5309 5310 mvpp2_write(priv, MVPP2_WIN_BASE(i), 5311 (cs->base & 0xffff0000) | (cs->mbus_attr << 8) | 5312 dram->mbus_dram_target_id); 5313 5314 mvpp2_write(priv, MVPP2_WIN_SIZE(i), 5315 (cs->size - 1) & 0xffff0000); 5316 5317 win_enable |= (1 << i); 5318 } 5319 5320 mvpp2_write(priv, MVPP2_BASE_ADDR_ENABLE, win_enable); 5321 } 5322 5323 /* Initialize Rx FIFO's */ 5324 static void mvpp2_rx_fifo_init(struct mvpp2 *priv) 5325 { 5326 int port; 5327 5328 for (port = 0; port < MVPP2_MAX_PORTS; port++) { 5329 mvpp2_write(priv, MVPP2_RX_DATA_FIFO_SIZE_REG(port), 5330 MVPP2_RX_FIFO_PORT_DATA_SIZE_4KB); 5331 mvpp2_write(priv, MVPP2_RX_ATTR_FIFO_SIZE_REG(port), 5332 MVPP2_RX_FIFO_PORT_ATTR_SIZE_4KB); 5333 } 5334 5335 mvpp2_write(priv, MVPP2_RX_MIN_PKT_SIZE_REG, 5336 MVPP2_RX_FIFO_PORT_MIN_PKT); 5337 mvpp2_write(priv, MVPP2_RX_FIFO_INIT_REG, 0x1); 5338 } 5339 5340 static void mvpp22_rx_fifo_init(struct mvpp2 *priv) 5341 { 5342 int port; 5343 5344 /* The FIFO size parameters are set depending on the maximum speed a 5345 * given port can handle: 5346 * - Port 0: 10Gbps 5347 * - Port 1: 2.5Gbps 5348 * - Ports 2 and 3: 1Gbps 5349 */ 5350 5351 mvpp2_write(priv, MVPP2_RX_DATA_FIFO_SIZE_REG(0), 5352 MVPP2_RX_FIFO_PORT_DATA_SIZE_32KB); 5353 mvpp2_write(priv, MVPP2_RX_ATTR_FIFO_SIZE_REG(0), 5354 MVPP2_RX_FIFO_PORT_ATTR_SIZE_32KB); 5355 5356 mvpp2_write(priv, MVPP2_RX_DATA_FIFO_SIZE_REG(1), 5357 MVPP2_RX_FIFO_PORT_DATA_SIZE_8KB); 5358 mvpp2_write(priv, MVPP2_RX_ATTR_FIFO_SIZE_REG(1), 5359 MVPP2_RX_FIFO_PORT_ATTR_SIZE_8KB); 5360 5361 for (port = 2; port < MVPP2_MAX_PORTS; port++) { 5362 mvpp2_write(priv, MVPP2_RX_DATA_FIFO_SIZE_REG(port), 5363 MVPP2_RX_FIFO_PORT_DATA_SIZE_4KB); 5364 mvpp2_write(priv, MVPP2_RX_ATTR_FIFO_SIZE_REG(port), 5365 MVPP2_RX_FIFO_PORT_ATTR_SIZE_4KB); 5366 } 5367 5368 mvpp2_write(priv, MVPP2_RX_MIN_PKT_SIZE_REG, 5369 MVPP2_RX_FIFO_PORT_MIN_PKT); 5370 mvpp2_write(priv, MVPP2_RX_FIFO_INIT_REG, 0x1); 5371 } 5372 5373 /* Initialize Tx FIFO's: the total FIFO size is 19kB on PPv2.2 and 10G 5374 * interfaces must have a Tx FIFO size of 10kB. As only port 0 can do 10G, 5375 * configure its Tx FIFO size to 10kB and the others ports Tx FIFO size to 3kB. 5376 */ 5377 static void mvpp22_tx_fifo_init(struct mvpp2 *priv) 5378 { 5379 int port, size, thrs; 5380 5381 for (port = 0; port < MVPP2_MAX_PORTS; port++) { 5382 if (port == 0) { 5383 size = MVPP22_TX_FIFO_DATA_SIZE_10KB; 5384 thrs = MVPP2_TX_FIFO_THRESHOLD_10KB; 5385 } else { 5386 size = MVPP22_TX_FIFO_DATA_SIZE_3KB; 5387 thrs = MVPP2_TX_FIFO_THRESHOLD_3KB; 5388 } 5389 mvpp2_write(priv, MVPP22_TX_FIFO_SIZE_REG(port), size); 5390 mvpp2_write(priv, MVPP22_TX_FIFO_THRESH_REG(port), thrs); 5391 } 5392 } 5393 5394 static void mvpp2_axi_init(struct mvpp2 *priv) 5395 { 5396 u32 val, rdval, wrval; 5397 5398 mvpp2_write(priv, MVPP22_BM_ADDR_HIGH_RLS_REG, 0x0); 5399 5400 /* AXI Bridge Configuration */ 5401 5402 rdval = MVPP22_AXI_CODE_CACHE_RD_CACHE 5403 << MVPP22_AXI_ATTR_CACHE_OFFS; 5404 rdval |= MVPP22_AXI_CODE_DOMAIN_OUTER_DOM 5405 << MVPP22_AXI_ATTR_DOMAIN_OFFS; 5406 5407 wrval = MVPP22_AXI_CODE_CACHE_WR_CACHE 5408 << MVPP22_AXI_ATTR_CACHE_OFFS; 5409 wrval |= MVPP22_AXI_CODE_DOMAIN_OUTER_DOM 5410 << MVPP22_AXI_ATTR_DOMAIN_OFFS; 5411 5412 /* BM */ 5413 mvpp2_write(priv, MVPP22_AXI_BM_WR_ATTR_REG, wrval); 5414 mvpp2_write(priv, MVPP22_AXI_BM_RD_ATTR_REG, rdval); 5415 5416 /* Descriptors */ 5417 mvpp2_write(priv, MVPP22_AXI_AGGRQ_DESCR_RD_ATTR_REG, rdval); 5418 mvpp2_write(priv, MVPP22_AXI_TXQ_DESCR_WR_ATTR_REG, wrval); 5419 mvpp2_write(priv, MVPP22_AXI_TXQ_DESCR_RD_ATTR_REG, rdval); 5420 mvpp2_write(priv, MVPP22_AXI_RXQ_DESCR_WR_ATTR_REG, wrval); 5421 5422 /* Buffer Data */ 5423 mvpp2_write(priv, MVPP22_AXI_TX_DATA_RD_ATTR_REG, rdval); 5424 mvpp2_write(priv, MVPP22_AXI_RX_DATA_WR_ATTR_REG, wrval); 5425 5426 val = MVPP22_AXI_CODE_CACHE_NON_CACHE 5427 << MVPP22_AXI_CODE_CACHE_OFFS; 5428 val |= MVPP22_AXI_CODE_DOMAIN_SYSTEM 5429 << MVPP22_AXI_CODE_DOMAIN_OFFS; 5430 mvpp2_write(priv, MVPP22_AXI_RD_NORMAL_CODE_REG, val); 5431 mvpp2_write(priv, MVPP22_AXI_WR_NORMAL_CODE_REG, val); 5432 5433 val = MVPP22_AXI_CODE_CACHE_RD_CACHE 5434 << MVPP22_AXI_CODE_CACHE_OFFS; 5435 val |= MVPP22_AXI_CODE_DOMAIN_OUTER_DOM 5436 << MVPP22_AXI_CODE_DOMAIN_OFFS; 5437 5438 mvpp2_write(priv, MVPP22_AXI_RD_SNOOP_CODE_REG, val); 5439 5440 val = MVPP22_AXI_CODE_CACHE_WR_CACHE 5441 << MVPP22_AXI_CODE_CACHE_OFFS; 5442 val |= MVPP22_AXI_CODE_DOMAIN_OUTER_DOM 5443 << MVPP22_AXI_CODE_DOMAIN_OFFS; 5444 5445 mvpp2_write(priv, MVPP22_AXI_WR_SNOOP_CODE_REG, val); 5446 } 5447 5448 /* Initialize network controller common part HW */ 5449 static int mvpp2_init(struct platform_device *pdev, struct mvpp2 *priv) 5450 { 5451 const struct mbus_dram_target_info *dram_target_info; 5452 int err, i; 5453 u32 val; 5454 5455 /* MBUS windows configuration */ 5456 dram_target_info = mv_mbus_dram_info(); 5457 if (dram_target_info) 5458 mvpp2_conf_mbus_windows(dram_target_info, priv); 5459 5460 if (priv->hw_version == MVPP22) 5461 mvpp2_axi_init(priv); 5462 5463 /* Disable HW PHY polling */ 5464 if (priv->hw_version == MVPP21) { 5465 val = readl(priv->lms_base + MVPP2_PHY_AN_CFG0_REG); 5466 val |= MVPP2_PHY_AN_STOP_SMI0_MASK; 5467 writel(val, priv->lms_base + MVPP2_PHY_AN_CFG0_REG); 5468 } else { 5469 val = readl(priv->iface_base + MVPP22_SMI_MISC_CFG_REG); 5470 val &= ~MVPP22_SMI_POLLING_EN; 5471 writel(val, priv->iface_base + MVPP22_SMI_MISC_CFG_REG); 5472 } 5473 5474 /* Allocate and initialize aggregated TXQs */ 5475 priv->aggr_txqs = devm_kcalloc(&pdev->dev, MVPP2_MAX_THREADS, 5476 sizeof(*priv->aggr_txqs), 5477 GFP_KERNEL); 5478 if (!priv->aggr_txqs) 5479 return -ENOMEM; 5480 5481 for (i = 0; i < MVPP2_MAX_THREADS; i++) { 5482 priv->aggr_txqs[i].id = i; 5483 priv->aggr_txqs[i].size = MVPP2_AGGR_TXQ_SIZE; 5484 err = mvpp2_aggr_txq_init(pdev, &priv->aggr_txqs[i], i, priv); 5485 if (err < 0) 5486 return err; 5487 } 5488 5489 /* Fifo Init */ 5490 if (priv->hw_version == MVPP21) { 5491 mvpp2_rx_fifo_init(priv); 5492 } else { 5493 mvpp22_rx_fifo_init(priv); 5494 mvpp22_tx_fifo_init(priv); 5495 } 5496 5497 if (priv->hw_version == MVPP21) 5498 writel(MVPP2_EXT_GLOBAL_CTRL_DEFAULT, 5499 priv->lms_base + MVPP2_MNG_EXTENDED_GLOBAL_CTRL_REG); 5500 5501 /* Allow cache snoop when transmiting packets */ 5502 mvpp2_write(priv, MVPP2_TX_SNOOP_REG, 0x1); 5503 5504 /* Buffer Manager initialization */ 5505 err = mvpp2_bm_init(pdev, priv); 5506 if (err < 0) 5507 return err; 5508 5509 /* Parser default initialization */ 5510 err = mvpp2_prs_default_init(pdev, priv); 5511 if (err < 0) 5512 return err; 5513 5514 /* Classifier default initialization */ 5515 mvpp2_cls_init(priv); 5516 5517 return 0; 5518 } 5519 5520 static int mvpp2_probe(struct platform_device *pdev) 5521 { 5522 const struct acpi_device_id *acpi_id; 5523 struct fwnode_handle *fwnode = pdev->dev.fwnode; 5524 struct fwnode_handle *port_fwnode; 5525 struct mvpp2 *priv; 5526 struct resource *res; 5527 void __iomem *base; 5528 int i, shared; 5529 int err; 5530 5531 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); 5532 if (!priv) 5533 return -ENOMEM; 5534 5535 if (has_acpi_companion(&pdev->dev)) { 5536 acpi_id = acpi_match_device(pdev->dev.driver->acpi_match_table, 5537 &pdev->dev); 5538 if (!acpi_id) 5539 return -EINVAL; 5540 priv->hw_version = (unsigned long)acpi_id->driver_data; 5541 } else { 5542 priv->hw_version = 5543 (unsigned long)of_device_get_match_data(&pdev->dev); 5544 } 5545 5546 /* multi queue mode isn't supported on PPV2.1, fallback to single 5547 * mode 5548 */ 5549 if (priv->hw_version == MVPP21) 5550 queue_mode = MVPP2_QDIST_SINGLE_MODE; 5551 5552 base = devm_platform_ioremap_resource(pdev, 0); 5553 if (IS_ERR(base)) 5554 return PTR_ERR(base); 5555 5556 if (priv->hw_version == MVPP21) { 5557 priv->lms_base = devm_platform_ioremap_resource(pdev, 1); 5558 if (IS_ERR(priv->lms_base)) 5559 return PTR_ERR(priv->lms_base); 5560 } else { 5561 res = platform_get_resource(pdev, IORESOURCE_MEM, 1); 5562 if (has_acpi_companion(&pdev->dev)) { 5563 /* In case the MDIO memory region is declared in 5564 * the ACPI, it can already appear as 'in-use' 5565 * in the OS. Because it is overlapped by second 5566 * region of the network controller, make 5567 * sure it is released, before requesting it again. 5568 * The care is taken by mvpp2 driver to avoid 5569 * concurrent access to this memory region. 5570 */ 5571 release_resource(res); 5572 } 5573 priv->iface_base = devm_ioremap_resource(&pdev->dev, res); 5574 if (IS_ERR(priv->iface_base)) 5575 return PTR_ERR(priv->iface_base); 5576 } 5577 5578 if (priv->hw_version == MVPP22 && dev_of_node(&pdev->dev)) { 5579 priv->sysctrl_base = 5580 syscon_regmap_lookup_by_phandle(pdev->dev.of_node, 5581 "marvell,system-controller"); 5582 if (IS_ERR(priv->sysctrl_base)) 5583 /* The system controller regmap is optional for dt 5584 * compatibility reasons. When not provided, the 5585 * configuration of the GoP relies on the 5586 * firmware/bootloader. 5587 */ 5588 priv->sysctrl_base = NULL; 5589 } 5590 5591 mvpp2_setup_bm_pool(); 5592 5593 5594 priv->nthreads = min_t(unsigned int, num_present_cpus(), 5595 MVPP2_MAX_THREADS); 5596 5597 shared = num_present_cpus() - priv->nthreads; 5598 if (shared > 0) 5599 bitmap_fill(&priv->lock_map, 5600 min_t(int, shared, MVPP2_MAX_THREADS)); 5601 5602 for (i = 0; i < MVPP2_MAX_THREADS; i++) { 5603 u32 addr_space_sz; 5604 5605 addr_space_sz = (priv->hw_version == MVPP21 ? 5606 MVPP21_ADDR_SPACE_SZ : MVPP22_ADDR_SPACE_SZ); 5607 priv->swth_base[i] = base + i * addr_space_sz; 5608 } 5609 5610 if (priv->hw_version == MVPP21) 5611 priv->max_port_rxqs = 8; 5612 else 5613 priv->max_port_rxqs = 32; 5614 5615 if (dev_of_node(&pdev->dev)) { 5616 priv->pp_clk = devm_clk_get(&pdev->dev, "pp_clk"); 5617 if (IS_ERR(priv->pp_clk)) 5618 return PTR_ERR(priv->pp_clk); 5619 err = clk_prepare_enable(priv->pp_clk); 5620 if (err < 0) 5621 return err; 5622 5623 priv->gop_clk = devm_clk_get(&pdev->dev, "gop_clk"); 5624 if (IS_ERR(priv->gop_clk)) { 5625 err = PTR_ERR(priv->gop_clk); 5626 goto err_pp_clk; 5627 } 5628 err = clk_prepare_enable(priv->gop_clk); 5629 if (err < 0) 5630 goto err_pp_clk; 5631 5632 if (priv->hw_version == MVPP22) { 5633 priv->mg_clk = devm_clk_get(&pdev->dev, "mg_clk"); 5634 if (IS_ERR(priv->mg_clk)) { 5635 err = PTR_ERR(priv->mg_clk); 5636 goto err_gop_clk; 5637 } 5638 5639 err = clk_prepare_enable(priv->mg_clk); 5640 if (err < 0) 5641 goto err_gop_clk; 5642 5643 priv->mg_core_clk = devm_clk_get(&pdev->dev, "mg_core_clk"); 5644 if (IS_ERR(priv->mg_core_clk)) { 5645 priv->mg_core_clk = NULL; 5646 } else { 5647 err = clk_prepare_enable(priv->mg_core_clk); 5648 if (err < 0) 5649 goto err_mg_clk; 5650 } 5651 } 5652 5653 priv->axi_clk = devm_clk_get(&pdev->dev, "axi_clk"); 5654 if (IS_ERR(priv->axi_clk)) { 5655 err = PTR_ERR(priv->axi_clk); 5656 if (err == -EPROBE_DEFER) 5657 goto err_mg_core_clk; 5658 priv->axi_clk = NULL; 5659 } else { 5660 err = clk_prepare_enable(priv->axi_clk); 5661 if (err < 0) 5662 goto err_mg_core_clk; 5663 } 5664 5665 /* Get system's tclk rate */ 5666 priv->tclk = clk_get_rate(priv->pp_clk); 5667 } else if (device_property_read_u32(&pdev->dev, "clock-frequency", 5668 &priv->tclk)) { 5669 dev_err(&pdev->dev, "missing clock-frequency value\n"); 5670 return -EINVAL; 5671 } 5672 5673 if (priv->hw_version == MVPP22) { 5674 err = dma_set_mask(&pdev->dev, MVPP2_DESC_DMA_MASK); 5675 if (err) 5676 goto err_axi_clk; 5677 /* Sadly, the BM pools all share the same register to 5678 * store the high 32 bits of their address. So they 5679 * must all have the same high 32 bits, which forces 5680 * us to restrict coherent memory to DMA_BIT_MASK(32). 5681 */ 5682 err = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32)); 5683 if (err) 5684 goto err_axi_clk; 5685 } 5686 5687 /* Initialize network controller */ 5688 err = mvpp2_init(pdev, priv); 5689 if (err < 0) { 5690 dev_err(&pdev->dev, "failed to initialize controller\n"); 5691 goto err_axi_clk; 5692 } 5693 5694 /* Initialize ports */ 5695 fwnode_for_each_available_child_node(fwnode, port_fwnode) { 5696 err = mvpp2_port_probe(pdev, port_fwnode, priv); 5697 if (err < 0) 5698 goto err_port_probe; 5699 } 5700 5701 if (priv->port_count == 0) { 5702 dev_err(&pdev->dev, "no ports enabled\n"); 5703 err = -ENODEV; 5704 goto err_axi_clk; 5705 } 5706 5707 /* Statistics must be gathered regularly because some of them (like 5708 * packets counters) are 32-bit registers and could overflow quite 5709 * quickly. For instance, a 10Gb link used at full bandwidth with the 5710 * smallest packets (64B) will overflow a 32-bit counter in less than 5711 * 30 seconds. Then, use a workqueue to fill 64-bit counters. 5712 */ 5713 snprintf(priv->queue_name, sizeof(priv->queue_name), 5714 "stats-wq-%s%s", netdev_name(priv->port_list[0]->dev), 5715 priv->port_count > 1 ? "+" : ""); 5716 priv->stats_queue = create_singlethread_workqueue(priv->queue_name); 5717 if (!priv->stats_queue) { 5718 err = -ENOMEM; 5719 goto err_port_probe; 5720 } 5721 5722 mvpp2_dbgfs_init(priv, pdev->name); 5723 5724 platform_set_drvdata(pdev, priv); 5725 return 0; 5726 5727 err_port_probe: 5728 i = 0; 5729 fwnode_for_each_available_child_node(fwnode, port_fwnode) { 5730 if (priv->port_list[i]) 5731 mvpp2_port_remove(priv->port_list[i]); 5732 i++; 5733 } 5734 err_axi_clk: 5735 clk_disable_unprepare(priv->axi_clk); 5736 5737 err_mg_core_clk: 5738 if (priv->hw_version == MVPP22) 5739 clk_disable_unprepare(priv->mg_core_clk); 5740 err_mg_clk: 5741 if (priv->hw_version == MVPP22) 5742 clk_disable_unprepare(priv->mg_clk); 5743 err_gop_clk: 5744 clk_disable_unprepare(priv->gop_clk); 5745 err_pp_clk: 5746 clk_disable_unprepare(priv->pp_clk); 5747 return err; 5748 } 5749 5750 static int mvpp2_remove(struct platform_device *pdev) 5751 { 5752 struct mvpp2 *priv = platform_get_drvdata(pdev); 5753 struct fwnode_handle *fwnode = pdev->dev.fwnode; 5754 struct fwnode_handle *port_fwnode; 5755 int i = 0; 5756 5757 mvpp2_dbgfs_cleanup(priv); 5758 5759 flush_workqueue(priv->stats_queue); 5760 destroy_workqueue(priv->stats_queue); 5761 5762 fwnode_for_each_available_child_node(fwnode, port_fwnode) { 5763 if (priv->port_list[i]) { 5764 mutex_destroy(&priv->port_list[i]->gather_stats_lock); 5765 mvpp2_port_remove(priv->port_list[i]); 5766 } 5767 i++; 5768 } 5769 5770 for (i = 0; i < MVPP2_BM_POOLS_NUM; i++) { 5771 struct mvpp2_bm_pool *bm_pool = &priv->bm_pools[i]; 5772 5773 mvpp2_bm_pool_destroy(pdev, priv, bm_pool); 5774 } 5775 5776 for (i = 0; i < MVPP2_MAX_THREADS; i++) { 5777 struct mvpp2_tx_queue *aggr_txq = &priv->aggr_txqs[i]; 5778 5779 dma_free_coherent(&pdev->dev, 5780 MVPP2_AGGR_TXQ_SIZE * MVPP2_DESC_ALIGNED_SIZE, 5781 aggr_txq->descs, 5782 aggr_txq->descs_dma); 5783 } 5784 5785 if (is_acpi_node(port_fwnode)) 5786 return 0; 5787 5788 clk_disable_unprepare(priv->axi_clk); 5789 clk_disable_unprepare(priv->mg_core_clk); 5790 clk_disable_unprepare(priv->mg_clk); 5791 clk_disable_unprepare(priv->pp_clk); 5792 clk_disable_unprepare(priv->gop_clk); 5793 5794 return 0; 5795 } 5796 5797 static const struct of_device_id mvpp2_match[] = { 5798 { 5799 .compatible = "marvell,armada-375-pp2", 5800 .data = (void *)MVPP21, 5801 }, 5802 { 5803 .compatible = "marvell,armada-7k-pp22", 5804 .data = (void *)MVPP22, 5805 }, 5806 { } 5807 }; 5808 MODULE_DEVICE_TABLE(of, mvpp2_match); 5809 5810 static const struct acpi_device_id mvpp2_acpi_match[] = { 5811 { "MRVL0110", MVPP22 }, 5812 { }, 5813 }; 5814 MODULE_DEVICE_TABLE(acpi, mvpp2_acpi_match); 5815 5816 static struct platform_driver mvpp2_driver = { 5817 .probe = mvpp2_probe, 5818 .remove = mvpp2_remove, 5819 .driver = { 5820 .name = MVPP2_DRIVER_NAME, 5821 .of_match_table = mvpp2_match, 5822 .acpi_match_table = ACPI_PTR(mvpp2_acpi_match), 5823 }, 5824 }; 5825 5826 module_platform_driver(mvpp2_driver); 5827 5828 MODULE_DESCRIPTION("Marvell PPv2 Ethernet Driver - www.marvell.com"); 5829 MODULE_AUTHOR("Marcin Wojtas <mw@semihalf.com>"); 5830 MODULE_LICENSE("GPL v2"); 5831