1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Driver for Marvell PPv2 network controller for Armada 375 SoC. 4 * 5 * Copyright (C) 2014 Marvell 6 * 7 * Marcin Wojtas <mw@semihalf.com> 8 */ 9 10 #include <linux/acpi.h> 11 #include <linux/kernel.h> 12 #include <linux/netdevice.h> 13 #include <linux/etherdevice.h> 14 #include <linux/platform_device.h> 15 #include <linux/skbuff.h> 16 #include <linux/inetdevice.h> 17 #include <linux/mbus.h> 18 #include <linux/module.h> 19 #include <linux/mfd/syscon.h> 20 #include <linux/interrupt.h> 21 #include <linux/cpumask.h> 22 #include <linux/of.h> 23 #include <linux/of_irq.h> 24 #include <linux/of_mdio.h> 25 #include <linux/of_net.h> 26 #include <linux/of_address.h> 27 #include <linux/phy.h> 28 #include <linux/phylink.h> 29 #include <linux/phy/phy.h> 30 #include <linux/ptp_classify.h> 31 #include <linux/clk.h> 32 #include <linux/hrtimer.h> 33 #include <linux/ktime.h> 34 #include <linux/regmap.h> 35 #include <uapi/linux/ppp_defs.h> 36 #include <net/ip.h> 37 #include <net/ipv6.h> 38 #include <net/tso.h> 39 #include <linux/bpf_trace.h> 40 41 #include "mvpp2.h" 42 #include "mvpp2_prs.h" 43 #include "mvpp2_cls.h" 44 45 enum mvpp2_bm_pool_log_num { 46 MVPP2_BM_SHORT, 47 MVPP2_BM_LONG, 48 MVPP2_BM_JUMBO, 49 MVPP2_BM_POOLS_NUM 50 }; 51 52 static struct { 53 int pkt_size; 54 int buf_num; 55 } mvpp2_pools[MVPP2_BM_POOLS_NUM]; 56 57 /* The prototype is added here to be used in start_dev when using ACPI. This 58 * will be removed once phylink is used for all modes (dt+ACPI). 59 */ 60 static void mvpp2_acpi_start(struct mvpp2_port *port); 61 62 /* Queue modes */ 63 #define MVPP2_QDIST_SINGLE_MODE 0 64 #define MVPP2_QDIST_MULTI_MODE 1 65 66 static int queue_mode = MVPP2_QDIST_MULTI_MODE; 67 68 module_param(queue_mode, int, 0444); 69 MODULE_PARM_DESC(queue_mode, "Set queue_mode (single=0, multi=1)"); 70 71 /* Utility/helper methods */ 72 73 void mvpp2_write(struct mvpp2 *priv, u32 offset, u32 data) 74 { 75 writel(data, priv->swth_base[0] + offset); 76 } 77 78 u32 mvpp2_read(struct mvpp2 *priv, u32 offset) 79 { 80 return readl(priv->swth_base[0] + offset); 81 } 82 83 static u32 mvpp2_read_relaxed(struct mvpp2 *priv, u32 offset) 84 { 85 return readl_relaxed(priv->swth_base[0] + offset); 86 } 87 88 static inline u32 mvpp2_cpu_to_thread(struct mvpp2 *priv, int cpu) 89 { 90 return cpu % priv->nthreads; 91 } 92 93 static void mvpp2_cm3_write(struct mvpp2 *priv, u32 offset, u32 data) 94 { 95 writel(data, priv->cm3_base + offset); 96 } 97 98 static u32 mvpp2_cm3_read(struct mvpp2 *priv, u32 offset) 99 { 100 return readl(priv->cm3_base + offset); 101 } 102 103 static struct page_pool * 104 mvpp2_create_page_pool(struct device *dev, int num, int len, 105 enum dma_data_direction dma_dir) 106 { 107 struct page_pool_params pp_params = { 108 /* internal DMA mapping in page_pool */ 109 .flags = PP_FLAG_DMA_MAP | PP_FLAG_DMA_SYNC_DEV, 110 .pool_size = num, 111 .nid = NUMA_NO_NODE, 112 .dev = dev, 113 .dma_dir = dma_dir, 114 .offset = MVPP2_SKB_HEADROOM, 115 .max_len = len, 116 }; 117 118 return page_pool_create(&pp_params); 119 } 120 121 /* These accessors should be used to access: 122 * 123 * - per-thread registers, where each thread has its own copy of the 124 * register. 125 * 126 * MVPP2_BM_VIRT_ALLOC_REG 127 * MVPP2_BM_ADDR_HIGH_ALLOC 128 * MVPP22_BM_ADDR_HIGH_RLS_REG 129 * MVPP2_BM_VIRT_RLS_REG 130 * MVPP2_ISR_RX_TX_CAUSE_REG 131 * MVPP2_ISR_RX_TX_MASK_REG 132 * MVPP2_TXQ_NUM_REG 133 * MVPP2_AGGR_TXQ_UPDATE_REG 134 * MVPP2_TXQ_RSVD_REQ_REG 135 * MVPP2_TXQ_RSVD_RSLT_REG 136 * MVPP2_TXQ_SENT_REG 137 * MVPP2_RXQ_NUM_REG 138 * 139 * - global registers that must be accessed through a specific thread 140 * window, because they are related to an access to a per-thread 141 * register 142 * 143 * MVPP2_BM_PHY_ALLOC_REG (related to MVPP2_BM_VIRT_ALLOC_REG) 144 * MVPP2_BM_PHY_RLS_REG (related to MVPP2_BM_VIRT_RLS_REG) 145 * MVPP2_RXQ_THRESH_REG (related to MVPP2_RXQ_NUM_REG) 146 * MVPP2_RXQ_DESC_ADDR_REG (related to MVPP2_RXQ_NUM_REG) 147 * MVPP2_RXQ_DESC_SIZE_REG (related to MVPP2_RXQ_NUM_REG) 148 * MVPP2_RXQ_INDEX_REG (related to MVPP2_RXQ_NUM_REG) 149 * MVPP2_TXQ_PENDING_REG (related to MVPP2_TXQ_NUM_REG) 150 * MVPP2_TXQ_DESC_ADDR_REG (related to MVPP2_TXQ_NUM_REG) 151 * MVPP2_TXQ_DESC_SIZE_REG (related to MVPP2_TXQ_NUM_REG) 152 * MVPP2_TXQ_INDEX_REG (related to MVPP2_TXQ_NUM_REG) 153 * MVPP2_TXQ_PENDING_REG (related to MVPP2_TXQ_NUM_REG) 154 * MVPP2_TXQ_PREF_BUF_REG (related to MVPP2_TXQ_NUM_REG) 155 * MVPP2_TXQ_PREF_BUF_REG (related to MVPP2_TXQ_NUM_REG) 156 */ 157 static void mvpp2_thread_write(struct mvpp2 *priv, unsigned int thread, 158 u32 offset, u32 data) 159 { 160 writel(data, priv->swth_base[thread] + offset); 161 } 162 163 static u32 mvpp2_thread_read(struct mvpp2 *priv, unsigned int thread, 164 u32 offset) 165 { 166 return readl(priv->swth_base[thread] + offset); 167 } 168 169 static void mvpp2_thread_write_relaxed(struct mvpp2 *priv, unsigned int thread, 170 u32 offset, u32 data) 171 { 172 writel_relaxed(data, priv->swth_base[thread] + offset); 173 } 174 175 static u32 mvpp2_thread_read_relaxed(struct mvpp2 *priv, unsigned int thread, 176 u32 offset) 177 { 178 return readl_relaxed(priv->swth_base[thread] + offset); 179 } 180 181 static dma_addr_t mvpp2_txdesc_dma_addr_get(struct mvpp2_port *port, 182 struct mvpp2_tx_desc *tx_desc) 183 { 184 if (port->priv->hw_version == MVPP21) 185 return le32_to_cpu(tx_desc->pp21.buf_dma_addr); 186 else 187 return le64_to_cpu(tx_desc->pp22.buf_dma_addr_ptp) & 188 MVPP2_DESC_DMA_MASK; 189 } 190 191 static void mvpp2_txdesc_dma_addr_set(struct mvpp2_port *port, 192 struct mvpp2_tx_desc *tx_desc, 193 dma_addr_t dma_addr) 194 { 195 dma_addr_t addr, offset; 196 197 addr = dma_addr & ~MVPP2_TX_DESC_ALIGN; 198 offset = dma_addr & MVPP2_TX_DESC_ALIGN; 199 200 if (port->priv->hw_version == MVPP21) { 201 tx_desc->pp21.buf_dma_addr = cpu_to_le32(addr); 202 tx_desc->pp21.packet_offset = offset; 203 } else { 204 __le64 val = cpu_to_le64(addr); 205 206 tx_desc->pp22.buf_dma_addr_ptp &= ~cpu_to_le64(MVPP2_DESC_DMA_MASK); 207 tx_desc->pp22.buf_dma_addr_ptp |= val; 208 tx_desc->pp22.packet_offset = offset; 209 } 210 } 211 212 static size_t mvpp2_txdesc_size_get(struct mvpp2_port *port, 213 struct mvpp2_tx_desc *tx_desc) 214 { 215 if (port->priv->hw_version == MVPP21) 216 return le16_to_cpu(tx_desc->pp21.data_size); 217 else 218 return le16_to_cpu(tx_desc->pp22.data_size); 219 } 220 221 static void mvpp2_txdesc_size_set(struct mvpp2_port *port, 222 struct mvpp2_tx_desc *tx_desc, 223 size_t size) 224 { 225 if (port->priv->hw_version == MVPP21) 226 tx_desc->pp21.data_size = cpu_to_le16(size); 227 else 228 tx_desc->pp22.data_size = cpu_to_le16(size); 229 } 230 231 static void mvpp2_txdesc_txq_set(struct mvpp2_port *port, 232 struct mvpp2_tx_desc *tx_desc, 233 unsigned int txq) 234 { 235 if (port->priv->hw_version == MVPP21) 236 tx_desc->pp21.phys_txq = txq; 237 else 238 tx_desc->pp22.phys_txq = txq; 239 } 240 241 static void mvpp2_txdesc_cmd_set(struct mvpp2_port *port, 242 struct mvpp2_tx_desc *tx_desc, 243 unsigned int command) 244 { 245 if (port->priv->hw_version == MVPP21) 246 tx_desc->pp21.command = cpu_to_le32(command); 247 else 248 tx_desc->pp22.command = cpu_to_le32(command); 249 } 250 251 static unsigned int mvpp2_txdesc_offset_get(struct mvpp2_port *port, 252 struct mvpp2_tx_desc *tx_desc) 253 { 254 if (port->priv->hw_version == MVPP21) 255 return tx_desc->pp21.packet_offset; 256 else 257 return tx_desc->pp22.packet_offset; 258 } 259 260 static dma_addr_t mvpp2_rxdesc_dma_addr_get(struct mvpp2_port *port, 261 struct mvpp2_rx_desc *rx_desc) 262 { 263 if (port->priv->hw_version == MVPP21) 264 return le32_to_cpu(rx_desc->pp21.buf_dma_addr); 265 else 266 return le64_to_cpu(rx_desc->pp22.buf_dma_addr_key_hash) & 267 MVPP2_DESC_DMA_MASK; 268 } 269 270 static unsigned long mvpp2_rxdesc_cookie_get(struct mvpp2_port *port, 271 struct mvpp2_rx_desc *rx_desc) 272 { 273 if (port->priv->hw_version == MVPP21) 274 return le32_to_cpu(rx_desc->pp21.buf_cookie); 275 else 276 return le64_to_cpu(rx_desc->pp22.buf_cookie_misc) & 277 MVPP2_DESC_DMA_MASK; 278 } 279 280 static size_t mvpp2_rxdesc_size_get(struct mvpp2_port *port, 281 struct mvpp2_rx_desc *rx_desc) 282 { 283 if (port->priv->hw_version == MVPP21) 284 return le16_to_cpu(rx_desc->pp21.data_size); 285 else 286 return le16_to_cpu(rx_desc->pp22.data_size); 287 } 288 289 static u32 mvpp2_rxdesc_status_get(struct mvpp2_port *port, 290 struct mvpp2_rx_desc *rx_desc) 291 { 292 if (port->priv->hw_version == MVPP21) 293 return le32_to_cpu(rx_desc->pp21.status); 294 else 295 return le32_to_cpu(rx_desc->pp22.status); 296 } 297 298 static void mvpp2_txq_inc_get(struct mvpp2_txq_pcpu *txq_pcpu) 299 { 300 txq_pcpu->txq_get_index++; 301 if (txq_pcpu->txq_get_index == txq_pcpu->size) 302 txq_pcpu->txq_get_index = 0; 303 } 304 305 static void mvpp2_txq_inc_put(struct mvpp2_port *port, 306 struct mvpp2_txq_pcpu *txq_pcpu, 307 void *data, 308 struct mvpp2_tx_desc *tx_desc, 309 enum mvpp2_tx_buf_type buf_type) 310 { 311 struct mvpp2_txq_pcpu_buf *tx_buf = 312 txq_pcpu->buffs + txq_pcpu->txq_put_index; 313 tx_buf->type = buf_type; 314 if (buf_type == MVPP2_TYPE_SKB) 315 tx_buf->skb = data; 316 else 317 tx_buf->xdpf = data; 318 tx_buf->size = mvpp2_txdesc_size_get(port, tx_desc); 319 tx_buf->dma = mvpp2_txdesc_dma_addr_get(port, tx_desc) + 320 mvpp2_txdesc_offset_get(port, tx_desc); 321 txq_pcpu->txq_put_index++; 322 if (txq_pcpu->txq_put_index == txq_pcpu->size) 323 txq_pcpu->txq_put_index = 0; 324 } 325 326 /* Get number of maximum RXQ */ 327 static int mvpp2_get_nrxqs(struct mvpp2 *priv) 328 { 329 unsigned int nrxqs; 330 331 if (priv->hw_version >= MVPP22 && queue_mode == MVPP2_QDIST_SINGLE_MODE) 332 return 1; 333 334 /* According to the PPv2.2 datasheet and our experiments on 335 * PPv2.1, RX queues have an allocation granularity of 4 (when 336 * more than a single one on PPv2.2). 337 * Round up to nearest multiple of 4. 338 */ 339 nrxqs = (num_possible_cpus() + 3) & ~0x3; 340 if (nrxqs > MVPP2_PORT_MAX_RXQ) 341 nrxqs = MVPP2_PORT_MAX_RXQ; 342 343 return nrxqs; 344 } 345 346 /* Get number of physical egress port */ 347 static inline int mvpp2_egress_port(struct mvpp2_port *port) 348 { 349 return MVPP2_MAX_TCONT + port->id; 350 } 351 352 /* Get number of physical TXQ */ 353 static inline int mvpp2_txq_phys(int port, int txq) 354 { 355 return (MVPP2_MAX_TCONT + port) * MVPP2_MAX_TXQ + txq; 356 } 357 358 /* Returns a struct page if page_pool is set, otherwise a buffer */ 359 static void *mvpp2_frag_alloc(const struct mvpp2_bm_pool *pool, 360 struct page_pool *page_pool) 361 { 362 if (page_pool) 363 return page_pool_dev_alloc_pages(page_pool); 364 365 if (likely(pool->frag_size <= PAGE_SIZE)) 366 return netdev_alloc_frag(pool->frag_size); 367 368 return kmalloc(pool->frag_size, GFP_ATOMIC); 369 } 370 371 static void mvpp2_frag_free(const struct mvpp2_bm_pool *pool, 372 struct page_pool *page_pool, void *data) 373 { 374 if (page_pool) 375 page_pool_put_full_page(page_pool, virt_to_head_page(data), false); 376 else if (likely(pool->frag_size <= PAGE_SIZE)) 377 skb_free_frag(data); 378 else 379 kfree(data); 380 } 381 382 /* Buffer Manager configuration routines */ 383 384 /* Create pool */ 385 static int mvpp2_bm_pool_create(struct device *dev, struct mvpp2 *priv, 386 struct mvpp2_bm_pool *bm_pool, int size) 387 { 388 u32 val; 389 390 /* Number of buffer pointers must be a multiple of 16, as per 391 * hardware constraints 392 */ 393 if (!IS_ALIGNED(size, 16)) 394 return -EINVAL; 395 396 /* PPv2.1 needs 8 bytes per buffer pointer, PPv2.2 and PPv2.3 needs 16 397 * bytes per buffer pointer 398 */ 399 if (priv->hw_version == MVPP21) 400 bm_pool->size_bytes = 2 * sizeof(u32) * size; 401 else 402 bm_pool->size_bytes = 2 * sizeof(u64) * size; 403 404 bm_pool->virt_addr = dma_alloc_coherent(dev, bm_pool->size_bytes, 405 &bm_pool->dma_addr, 406 GFP_KERNEL); 407 if (!bm_pool->virt_addr) 408 return -ENOMEM; 409 410 if (!IS_ALIGNED((unsigned long)bm_pool->virt_addr, 411 MVPP2_BM_POOL_PTR_ALIGN)) { 412 dma_free_coherent(dev, bm_pool->size_bytes, 413 bm_pool->virt_addr, bm_pool->dma_addr); 414 dev_err(dev, "BM pool %d is not %d bytes aligned\n", 415 bm_pool->id, MVPP2_BM_POOL_PTR_ALIGN); 416 return -ENOMEM; 417 } 418 419 mvpp2_write(priv, MVPP2_BM_POOL_BASE_REG(bm_pool->id), 420 lower_32_bits(bm_pool->dma_addr)); 421 mvpp2_write(priv, MVPP2_BM_POOL_SIZE_REG(bm_pool->id), size); 422 423 val = mvpp2_read(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id)); 424 val |= MVPP2_BM_START_MASK; 425 426 val &= ~MVPP2_BM_LOW_THRESH_MASK; 427 val &= ~MVPP2_BM_HIGH_THRESH_MASK; 428 429 /* Set 8 Pools BPPI threshold for MVPP23 */ 430 if (priv->hw_version == MVPP23) { 431 val |= MVPP2_BM_LOW_THRESH_VALUE(MVPP23_BM_BPPI_LOW_THRESH); 432 val |= MVPP2_BM_HIGH_THRESH_VALUE(MVPP23_BM_BPPI_HIGH_THRESH); 433 } else { 434 val |= MVPP2_BM_LOW_THRESH_VALUE(MVPP2_BM_BPPI_LOW_THRESH); 435 val |= MVPP2_BM_HIGH_THRESH_VALUE(MVPP2_BM_BPPI_HIGH_THRESH); 436 } 437 438 mvpp2_write(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id), val); 439 440 bm_pool->size = size; 441 bm_pool->pkt_size = 0; 442 bm_pool->buf_num = 0; 443 444 return 0; 445 } 446 447 /* Set pool buffer size */ 448 static void mvpp2_bm_pool_bufsize_set(struct mvpp2 *priv, 449 struct mvpp2_bm_pool *bm_pool, 450 int buf_size) 451 { 452 u32 val; 453 454 bm_pool->buf_size = buf_size; 455 456 val = ALIGN(buf_size, 1 << MVPP2_POOL_BUF_SIZE_OFFSET); 457 mvpp2_write(priv, MVPP2_POOL_BUF_SIZE_REG(bm_pool->id), val); 458 } 459 460 static void mvpp2_bm_bufs_get_addrs(struct device *dev, struct mvpp2 *priv, 461 struct mvpp2_bm_pool *bm_pool, 462 dma_addr_t *dma_addr, 463 phys_addr_t *phys_addr) 464 { 465 unsigned int thread = mvpp2_cpu_to_thread(priv, get_cpu()); 466 467 *dma_addr = mvpp2_thread_read(priv, thread, 468 MVPP2_BM_PHY_ALLOC_REG(bm_pool->id)); 469 *phys_addr = mvpp2_thread_read(priv, thread, MVPP2_BM_VIRT_ALLOC_REG); 470 471 if (priv->hw_version >= MVPP22) { 472 u32 val; 473 u32 dma_addr_highbits, phys_addr_highbits; 474 475 val = mvpp2_thread_read(priv, thread, MVPP22_BM_ADDR_HIGH_ALLOC); 476 dma_addr_highbits = (val & MVPP22_BM_ADDR_HIGH_PHYS_MASK); 477 phys_addr_highbits = (val & MVPP22_BM_ADDR_HIGH_VIRT_MASK) >> 478 MVPP22_BM_ADDR_HIGH_VIRT_SHIFT; 479 480 if (sizeof(dma_addr_t) == 8) 481 *dma_addr |= (u64)dma_addr_highbits << 32; 482 483 if (sizeof(phys_addr_t) == 8) 484 *phys_addr |= (u64)phys_addr_highbits << 32; 485 } 486 487 put_cpu(); 488 } 489 490 /* Free all buffers from the pool */ 491 static void mvpp2_bm_bufs_free(struct device *dev, struct mvpp2 *priv, 492 struct mvpp2_bm_pool *bm_pool, int buf_num) 493 { 494 struct page_pool *pp = NULL; 495 int i; 496 497 if (buf_num > bm_pool->buf_num) { 498 WARN(1, "Pool does not have so many bufs pool(%d) bufs(%d)\n", 499 bm_pool->id, buf_num); 500 buf_num = bm_pool->buf_num; 501 } 502 503 if (priv->percpu_pools) 504 pp = priv->page_pool[bm_pool->id]; 505 506 for (i = 0; i < buf_num; i++) { 507 dma_addr_t buf_dma_addr; 508 phys_addr_t buf_phys_addr; 509 void *data; 510 511 mvpp2_bm_bufs_get_addrs(dev, priv, bm_pool, 512 &buf_dma_addr, &buf_phys_addr); 513 514 if (!pp) 515 dma_unmap_single(dev, buf_dma_addr, 516 bm_pool->buf_size, DMA_FROM_DEVICE); 517 518 data = (void *)phys_to_virt(buf_phys_addr); 519 if (!data) 520 break; 521 522 mvpp2_frag_free(bm_pool, pp, data); 523 } 524 525 /* Update BM driver with number of buffers removed from pool */ 526 bm_pool->buf_num -= i; 527 } 528 529 /* Check number of buffers in BM pool */ 530 static int mvpp2_check_hw_buf_num(struct mvpp2 *priv, struct mvpp2_bm_pool *bm_pool) 531 { 532 int buf_num = 0; 533 534 buf_num += mvpp2_read(priv, MVPP2_BM_POOL_PTRS_NUM_REG(bm_pool->id)) & 535 MVPP22_BM_POOL_PTRS_NUM_MASK; 536 buf_num += mvpp2_read(priv, MVPP2_BM_BPPI_PTRS_NUM_REG(bm_pool->id)) & 537 MVPP2_BM_BPPI_PTR_NUM_MASK; 538 539 /* HW has one buffer ready which is not reflected in the counters */ 540 if (buf_num) 541 buf_num += 1; 542 543 return buf_num; 544 } 545 546 /* Cleanup pool */ 547 static int mvpp2_bm_pool_destroy(struct device *dev, struct mvpp2 *priv, 548 struct mvpp2_bm_pool *bm_pool) 549 { 550 int buf_num; 551 u32 val; 552 553 buf_num = mvpp2_check_hw_buf_num(priv, bm_pool); 554 mvpp2_bm_bufs_free(dev, priv, bm_pool, buf_num); 555 556 /* Check buffer counters after free */ 557 buf_num = mvpp2_check_hw_buf_num(priv, bm_pool); 558 if (buf_num) { 559 WARN(1, "cannot free all buffers in pool %d, buf_num left %d\n", 560 bm_pool->id, bm_pool->buf_num); 561 return 0; 562 } 563 564 val = mvpp2_read(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id)); 565 val |= MVPP2_BM_STOP_MASK; 566 mvpp2_write(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id), val); 567 568 if (priv->percpu_pools) { 569 page_pool_destroy(priv->page_pool[bm_pool->id]); 570 priv->page_pool[bm_pool->id] = NULL; 571 } 572 573 dma_free_coherent(dev, bm_pool->size_bytes, 574 bm_pool->virt_addr, 575 bm_pool->dma_addr); 576 return 0; 577 } 578 579 static int mvpp2_bm_pools_init(struct device *dev, struct mvpp2 *priv) 580 { 581 int i, err, size, poolnum = MVPP2_BM_POOLS_NUM; 582 struct mvpp2_bm_pool *bm_pool; 583 584 if (priv->percpu_pools) 585 poolnum = mvpp2_get_nrxqs(priv) * 2; 586 587 /* Create all pools with maximum size */ 588 size = MVPP2_BM_POOL_SIZE_MAX; 589 for (i = 0; i < poolnum; i++) { 590 bm_pool = &priv->bm_pools[i]; 591 bm_pool->id = i; 592 err = mvpp2_bm_pool_create(dev, priv, bm_pool, size); 593 if (err) 594 goto err_unroll_pools; 595 mvpp2_bm_pool_bufsize_set(priv, bm_pool, 0); 596 } 597 return 0; 598 599 err_unroll_pools: 600 dev_err(dev, "failed to create BM pool %d, size %d\n", i, size); 601 for (i = i - 1; i >= 0; i--) 602 mvpp2_bm_pool_destroy(dev, priv, &priv->bm_pools[i]); 603 return err; 604 } 605 606 /* Routine enable PPv23 8 pool mode */ 607 static void mvpp23_bm_set_8pool_mode(struct mvpp2 *priv) 608 { 609 int val; 610 611 val = mvpp2_read(priv, MVPP22_BM_POOL_BASE_ADDR_HIGH_REG); 612 val |= MVPP23_BM_8POOL_MODE; 613 mvpp2_write(priv, MVPP22_BM_POOL_BASE_ADDR_HIGH_REG, val); 614 } 615 616 static int mvpp2_bm_init(struct device *dev, struct mvpp2 *priv) 617 { 618 enum dma_data_direction dma_dir = DMA_FROM_DEVICE; 619 int i, err, poolnum = MVPP2_BM_POOLS_NUM; 620 struct mvpp2_port *port; 621 622 if (priv->percpu_pools) { 623 for (i = 0; i < priv->port_count; i++) { 624 port = priv->port_list[i]; 625 if (port->xdp_prog) { 626 dma_dir = DMA_BIDIRECTIONAL; 627 break; 628 } 629 } 630 631 poolnum = mvpp2_get_nrxqs(priv) * 2; 632 for (i = 0; i < poolnum; i++) { 633 /* the pool in use */ 634 int pn = i / (poolnum / 2); 635 636 priv->page_pool[i] = 637 mvpp2_create_page_pool(dev, 638 mvpp2_pools[pn].buf_num, 639 mvpp2_pools[pn].pkt_size, 640 dma_dir); 641 if (IS_ERR(priv->page_pool[i])) { 642 int j; 643 644 for (j = 0; j < i; j++) { 645 page_pool_destroy(priv->page_pool[j]); 646 priv->page_pool[j] = NULL; 647 } 648 return PTR_ERR(priv->page_pool[i]); 649 } 650 } 651 } 652 653 dev_info(dev, "using %d %s buffers\n", poolnum, 654 priv->percpu_pools ? "per-cpu" : "shared"); 655 656 for (i = 0; i < poolnum; i++) { 657 /* Mask BM all interrupts */ 658 mvpp2_write(priv, MVPP2_BM_INTR_MASK_REG(i), 0); 659 /* Clear BM cause register */ 660 mvpp2_write(priv, MVPP2_BM_INTR_CAUSE_REG(i), 0); 661 } 662 663 /* Allocate and initialize BM pools */ 664 priv->bm_pools = devm_kcalloc(dev, poolnum, 665 sizeof(*priv->bm_pools), GFP_KERNEL); 666 if (!priv->bm_pools) 667 return -ENOMEM; 668 669 if (priv->hw_version == MVPP23) 670 mvpp23_bm_set_8pool_mode(priv); 671 672 err = mvpp2_bm_pools_init(dev, priv); 673 if (err < 0) 674 return err; 675 return 0; 676 } 677 678 static void mvpp2_setup_bm_pool(void) 679 { 680 /* Short pool */ 681 mvpp2_pools[MVPP2_BM_SHORT].buf_num = MVPP2_BM_SHORT_BUF_NUM; 682 mvpp2_pools[MVPP2_BM_SHORT].pkt_size = MVPP2_BM_SHORT_PKT_SIZE; 683 684 /* Long pool */ 685 mvpp2_pools[MVPP2_BM_LONG].buf_num = MVPP2_BM_LONG_BUF_NUM; 686 mvpp2_pools[MVPP2_BM_LONG].pkt_size = MVPP2_BM_LONG_PKT_SIZE; 687 688 /* Jumbo pool */ 689 mvpp2_pools[MVPP2_BM_JUMBO].buf_num = MVPP2_BM_JUMBO_BUF_NUM; 690 mvpp2_pools[MVPP2_BM_JUMBO].pkt_size = MVPP2_BM_JUMBO_PKT_SIZE; 691 } 692 693 /* Attach long pool to rxq */ 694 static void mvpp2_rxq_long_pool_set(struct mvpp2_port *port, 695 int lrxq, int long_pool) 696 { 697 u32 val, mask; 698 int prxq; 699 700 /* Get queue physical ID */ 701 prxq = port->rxqs[lrxq]->id; 702 703 if (port->priv->hw_version == MVPP21) 704 mask = MVPP21_RXQ_POOL_LONG_MASK; 705 else 706 mask = MVPP22_RXQ_POOL_LONG_MASK; 707 708 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(prxq)); 709 val &= ~mask; 710 val |= (long_pool << MVPP2_RXQ_POOL_LONG_OFFS) & mask; 711 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(prxq), val); 712 } 713 714 /* Attach short pool to rxq */ 715 static void mvpp2_rxq_short_pool_set(struct mvpp2_port *port, 716 int lrxq, int short_pool) 717 { 718 u32 val, mask; 719 int prxq; 720 721 /* Get queue physical ID */ 722 prxq = port->rxqs[lrxq]->id; 723 724 if (port->priv->hw_version == MVPP21) 725 mask = MVPP21_RXQ_POOL_SHORT_MASK; 726 else 727 mask = MVPP22_RXQ_POOL_SHORT_MASK; 728 729 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(prxq)); 730 val &= ~mask; 731 val |= (short_pool << MVPP2_RXQ_POOL_SHORT_OFFS) & mask; 732 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(prxq), val); 733 } 734 735 static void *mvpp2_buf_alloc(struct mvpp2_port *port, 736 struct mvpp2_bm_pool *bm_pool, 737 struct page_pool *page_pool, 738 dma_addr_t *buf_dma_addr, 739 phys_addr_t *buf_phys_addr, 740 gfp_t gfp_mask) 741 { 742 dma_addr_t dma_addr; 743 struct page *page; 744 void *data; 745 746 data = mvpp2_frag_alloc(bm_pool, page_pool); 747 if (!data) 748 return NULL; 749 750 if (page_pool) { 751 page = (struct page *)data; 752 dma_addr = page_pool_get_dma_addr(page); 753 data = page_to_virt(page); 754 } else { 755 dma_addr = dma_map_single(port->dev->dev.parent, data, 756 MVPP2_RX_BUF_SIZE(bm_pool->pkt_size), 757 DMA_FROM_DEVICE); 758 if (unlikely(dma_mapping_error(port->dev->dev.parent, dma_addr))) { 759 mvpp2_frag_free(bm_pool, NULL, data); 760 return NULL; 761 } 762 } 763 *buf_dma_addr = dma_addr; 764 *buf_phys_addr = virt_to_phys(data); 765 766 return data; 767 } 768 769 /* Routine enable flow control for RXQs condition */ 770 static void mvpp2_rxq_enable_fc(struct mvpp2_port *port) 771 { 772 int val, cm3_state, host_id, q; 773 int fq = port->first_rxq; 774 unsigned long flags; 775 776 spin_lock_irqsave(&port->priv->mss_spinlock, flags); 777 778 /* Remove Flow control enable bit to prevent race between FW and Kernel 779 * If Flow control was enabled, it would be re-enabled. 780 */ 781 val = mvpp2_cm3_read(port->priv, MSS_FC_COM_REG); 782 cm3_state = (val & FLOW_CONTROL_ENABLE_BIT); 783 val &= ~FLOW_CONTROL_ENABLE_BIT; 784 mvpp2_cm3_write(port->priv, MSS_FC_COM_REG, val); 785 786 /* Set same Flow control for all RXQs */ 787 for (q = 0; q < port->nrxqs; q++) { 788 /* Set stop and start Flow control RXQ thresholds */ 789 val = MSS_THRESHOLD_START; 790 val |= (MSS_THRESHOLD_STOP << MSS_RXQ_TRESH_STOP_OFFS); 791 mvpp2_cm3_write(port->priv, MSS_RXQ_TRESH_REG(q, fq), val); 792 793 val = mvpp2_cm3_read(port->priv, MSS_RXQ_ASS_REG(q, fq)); 794 /* Set RXQ port ID */ 795 val &= ~(MSS_RXQ_ASS_PORTID_MASK << MSS_RXQ_ASS_Q_BASE(q, fq)); 796 val |= (port->id << MSS_RXQ_ASS_Q_BASE(q, fq)); 797 val &= ~(MSS_RXQ_ASS_HOSTID_MASK << (MSS_RXQ_ASS_Q_BASE(q, fq) 798 + MSS_RXQ_ASS_HOSTID_OFFS)); 799 800 /* Calculate RXQ host ID: 801 * In Single queue mode: Host ID equal to Host ID used for 802 * shared RX interrupt 803 * In Multi queue mode: Host ID equal to number of 804 * RXQ ID / number of CoS queues 805 * In Single resource mode: Host ID always equal to 0 806 */ 807 if (queue_mode == MVPP2_QDIST_SINGLE_MODE) 808 host_id = port->nqvecs; 809 else if (queue_mode == MVPP2_QDIST_MULTI_MODE) 810 host_id = q; 811 else 812 host_id = 0; 813 814 /* Set RXQ host ID */ 815 val |= (host_id << (MSS_RXQ_ASS_Q_BASE(q, fq) 816 + MSS_RXQ_ASS_HOSTID_OFFS)); 817 818 mvpp2_cm3_write(port->priv, MSS_RXQ_ASS_REG(q, fq), val); 819 } 820 821 /* Notify Firmware that Flow control config space ready for update */ 822 val = mvpp2_cm3_read(port->priv, MSS_FC_COM_REG); 823 val |= FLOW_CONTROL_UPDATE_COMMAND_BIT; 824 val |= cm3_state; 825 mvpp2_cm3_write(port->priv, MSS_FC_COM_REG, val); 826 827 spin_unlock_irqrestore(&port->priv->mss_spinlock, flags); 828 } 829 830 /* Routine disable flow control for RXQs condition */ 831 static void mvpp2_rxq_disable_fc(struct mvpp2_port *port) 832 { 833 int val, cm3_state, q; 834 unsigned long flags; 835 int fq = port->first_rxq; 836 837 spin_lock_irqsave(&port->priv->mss_spinlock, flags); 838 839 /* Remove Flow control enable bit to prevent race between FW and Kernel 840 * If Flow control was enabled, it would be re-enabled. 841 */ 842 val = mvpp2_cm3_read(port->priv, MSS_FC_COM_REG); 843 cm3_state = (val & FLOW_CONTROL_ENABLE_BIT); 844 val &= ~FLOW_CONTROL_ENABLE_BIT; 845 mvpp2_cm3_write(port->priv, MSS_FC_COM_REG, val); 846 847 /* Disable Flow control for all RXQs */ 848 for (q = 0; q < port->nrxqs; q++) { 849 /* Set threshold 0 to disable Flow control */ 850 val = 0; 851 val |= (0 << MSS_RXQ_TRESH_STOP_OFFS); 852 mvpp2_cm3_write(port->priv, MSS_RXQ_TRESH_REG(q, fq), val); 853 854 val = mvpp2_cm3_read(port->priv, MSS_RXQ_ASS_REG(q, fq)); 855 856 val &= ~(MSS_RXQ_ASS_PORTID_MASK << MSS_RXQ_ASS_Q_BASE(q, fq)); 857 858 val &= ~(MSS_RXQ_ASS_HOSTID_MASK << (MSS_RXQ_ASS_Q_BASE(q, fq) 859 + MSS_RXQ_ASS_HOSTID_OFFS)); 860 861 mvpp2_cm3_write(port->priv, MSS_RXQ_ASS_REG(q, fq), val); 862 } 863 864 /* Notify Firmware that Flow control config space ready for update */ 865 val = mvpp2_cm3_read(port->priv, MSS_FC_COM_REG); 866 val |= FLOW_CONTROL_UPDATE_COMMAND_BIT; 867 val |= cm3_state; 868 mvpp2_cm3_write(port->priv, MSS_FC_COM_REG, val); 869 870 spin_unlock_irqrestore(&port->priv->mss_spinlock, flags); 871 } 872 873 /* Routine disable/enable flow control for BM pool condition */ 874 static void mvpp2_bm_pool_update_fc(struct mvpp2_port *port, 875 struct mvpp2_bm_pool *pool, 876 bool en) 877 { 878 int val, cm3_state; 879 unsigned long flags; 880 881 spin_lock_irqsave(&port->priv->mss_spinlock, flags); 882 883 /* Remove Flow control enable bit to prevent race between FW and Kernel 884 * If Flow control were enabled, it would be re-enabled. 885 */ 886 val = mvpp2_cm3_read(port->priv, MSS_FC_COM_REG); 887 cm3_state = (val & FLOW_CONTROL_ENABLE_BIT); 888 val &= ~FLOW_CONTROL_ENABLE_BIT; 889 mvpp2_cm3_write(port->priv, MSS_FC_COM_REG, val); 890 891 /* Check if BM pool should be enabled/disable */ 892 if (en) { 893 /* Set BM pool start and stop thresholds per port */ 894 val = mvpp2_cm3_read(port->priv, MSS_BUF_POOL_REG(pool->id)); 895 val |= MSS_BUF_POOL_PORT_OFFS(port->id); 896 val &= ~MSS_BUF_POOL_START_MASK; 897 val |= (MSS_THRESHOLD_START << MSS_BUF_POOL_START_OFFS); 898 val &= ~MSS_BUF_POOL_STOP_MASK; 899 val |= MSS_THRESHOLD_STOP; 900 mvpp2_cm3_write(port->priv, MSS_BUF_POOL_REG(pool->id), val); 901 } else { 902 /* Remove BM pool from the port */ 903 val = mvpp2_cm3_read(port->priv, MSS_BUF_POOL_REG(pool->id)); 904 val &= ~MSS_BUF_POOL_PORT_OFFS(port->id); 905 906 /* Zero BM pool start and stop thresholds to disable pool 907 * flow control if pool empty (not used by any port) 908 */ 909 if (!pool->buf_num) { 910 val &= ~MSS_BUF_POOL_START_MASK; 911 val &= ~MSS_BUF_POOL_STOP_MASK; 912 } 913 914 mvpp2_cm3_write(port->priv, MSS_BUF_POOL_REG(pool->id), val); 915 } 916 917 /* Notify Firmware that Flow control config space ready for update */ 918 val = mvpp2_cm3_read(port->priv, MSS_FC_COM_REG); 919 val |= FLOW_CONTROL_UPDATE_COMMAND_BIT; 920 val |= cm3_state; 921 mvpp2_cm3_write(port->priv, MSS_FC_COM_REG, val); 922 923 spin_unlock_irqrestore(&port->priv->mss_spinlock, flags); 924 } 925 926 /* disable/enable flow control for BM pool on all ports */ 927 static void mvpp2_bm_pool_update_priv_fc(struct mvpp2 *priv, bool en) 928 { 929 struct mvpp2_port *port; 930 int i; 931 932 for (i = 0; i < priv->port_count; i++) { 933 port = priv->port_list[i]; 934 if (port->priv->percpu_pools) { 935 for (i = 0; i < port->nrxqs; i++) 936 mvpp2_bm_pool_update_fc(port, &port->priv->bm_pools[i], 937 port->tx_fc & en); 938 } else { 939 mvpp2_bm_pool_update_fc(port, port->pool_long, port->tx_fc & en); 940 mvpp2_bm_pool_update_fc(port, port->pool_short, port->tx_fc & en); 941 } 942 } 943 } 944 945 static int mvpp2_enable_global_fc(struct mvpp2 *priv) 946 { 947 int val, timeout = 0; 948 949 /* Enable global flow control. In this stage global 950 * flow control enabled, but still disabled per port. 951 */ 952 val = mvpp2_cm3_read(priv, MSS_FC_COM_REG); 953 val |= FLOW_CONTROL_ENABLE_BIT; 954 mvpp2_cm3_write(priv, MSS_FC_COM_REG, val); 955 956 /* Check if Firmware running and disable FC if not*/ 957 val |= FLOW_CONTROL_UPDATE_COMMAND_BIT; 958 mvpp2_cm3_write(priv, MSS_FC_COM_REG, val); 959 960 while (timeout < MSS_FC_MAX_TIMEOUT) { 961 val = mvpp2_cm3_read(priv, MSS_FC_COM_REG); 962 963 if (!(val & FLOW_CONTROL_UPDATE_COMMAND_BIT)) 964 return 0; 965 usleep_range(10, 20); 966 timeout++; 967 } 968 969 priv->global_tx_fc = false; 970 return -EOPNOTSUPP; 971 } 972 973 /* Release buffer to BM */ 974 static inline void mvpp2_bm_pool_put(struct mvpp2_port *port, int pool, 975 dma_addr_t buf_dma_addr, 976 phys_addr_t buf_phys_addr) 977 { 978 unsigned int thread = mvpp2_cpu_to_thread(port->priv, get_cpu()); 979 unsigned long flags = 0; 980 981 if (test_bit(thread, &port->priv->lock_map)) 982 spin_lock_irqsave(&port->bm_lock[thread], flags); 983 984 if (port->priv->hw_version >= MVPP22) { 985 u32 val = 0; 986 987 if (sizeof(dma_addr_t) == 8) 988 val |= upper_32_bits(buf_dma_addr) & 989 MVPP22_BM_ADDR_HIGH_PHYS_RLS_MASK; 990 991 if (sizeof(phys_addr_t) == 8) 992 val |= (upper_32_bits(buf_phys_addr) 993 << MVPP22_BM_ADDR_HIGH_VIRT_RLS_SHIFT) & 994 MVPP22_BM_ADDR_HIGH_VIRT_RLS_MASK; 995 996 mvpp2_thread_write_relaxed(port->priv, thread, 997 MVPP22_BM_ADDR_HIGH_RLS_REG, val); 998 } 999 1000 /* MVPP2_BM_VIRT_RLS_REG is not interpreted by HW, and simply 1001 * returned in the "cookie" field of the RX 1002 * descriptor. Instead of storing the virtual address, we 1003 * store the physical address 1004 */ 1005 mvpp2_thread_write_relaxed(port->priv, thread, 1006 MVPP2_BM_VIRT_RLS_REG, buf_phys_addr); 1007 mvpp2_thread_write_relaxed(port->priv, thread, 1008 MVPP2_BM_PHY_RLS_REG(pool), buf_dma_addr); 1009 1010 if (test_bit(thread, &port->priv->lock_map)) 1011 spin_unlock_irqrestore(&port->bm_lock[thread], flags); 1012 1013 put_cpu(); 1014 } 1015 1016 /* Allocate buffers for the pool */ 1017 static int mvpp2_bm_bufs_add(struct mvpp2_port *port, 1018 struct mvpp2_bm_pool *bm_pool, int buf_num) 1019 { 1020 int i, buf_size, total_size; 1021 dma_addr_t dma_addr; 1022 phys_addr_t phys_addr; 1023 struct page_pool *pp = NULL; 1024 void *buf; 1025 1026 if (port->priv->percpu_pools && 1027 bm_pool->pkt_size > MVPP2_BM_LONG_PKT_SIZE) { 1028 netdev_err(port->dev, 1029 "attempted to use jumbo frames with per-cpu pools"); 1030 return 0; 1031 } 1032 1033 buf_size = MVPP2_RX_BUF_SIZE(bm_pool->pkt_size); 1034 total_size = MVPP2_RX_TOTAL_SIZE(buf_size); 1035 1036 if (buf_num < 0 || 1037 (buf_num + bm_pool->buf_num > bm_pool->size)) { 1038 netdev_err(port->dev, 1039 "cannot allocate %d buffers for pool %d\n", 1040 buf_num, bm_pool->id); 1041 return 0; 1042 } 1043 1044 if (port->priv->percpu_pools) 1045 pp = port->priv->page_pool[bm_pool->id]; 1046 for (i = 0; i < buf_num; i++) { 1047 buf = mvpp2_buf_alloc(port, bm_pool, pp, &dma_addr, 1048 &phys_addr, GFP_KERNEL); 1049 if (!buf) 1050 break; 1051 1052 mvpp2_bm_pool_put(port, bm_pool->id, dma_addr, 1053 phys_addr); 1054 } 1055 1056 /* Update BM driver with number of buffers added to pool */ 1057 bm_pool->buf_num += i; 1058 1059 netdev_dbg(port->dev, 1060 "pool %d: pkt_size=%4d, buf_size=%4d, total_size=%4d\n", 1061 bm_pool->id, bm_pool->pkt_size, buf_size, total_size); 1062 1063 netdev_dbg(port->dev, 1064 "pool %d: %d of %d buffers added\n", 1065 bm_pool->id, i, buf_num); 1066 return i; 1067 } 1068 1069 /* Notify the driver that BM pool is being used as specific type and return the 1070 * pool pointer on success 1071 */ 1072 static struct mvpp2_bm_pool * 1073 mvpp2_bm_pool_use(struct mvpp2_port *port, unsigned pool, int pkt_size) 1074 { 1075 struct mvpp2_bm_pool *new_pool = &port->priv->bm_pools[pool]; 1076 int num; 1077 1078 if ((port->priv->percpu_pools && pool > mvpp2_get_nrxqs(port->priv) * 2) || 1079 (!port->priv->percpu_pools && pool >= MVPP2_BM_POOLS_NUM)) { 1080 netdev_err(port->dev, "Invalid pool %d\n", pool); 1081 return NULL; 1082 } 1083 1084 /* Allocate buffers in case BM pool is used as long pool, but packet 1085 * size doesn't match MTU or BM pool hasn't being used yet 1086 */ 1087 if (new_pool->pkt_size == 0) { 1088 int pkts_num; 1089 1090 /* Set default buffer number or free all the buffers in case 1091 * the pool is not empty 1092 */ 1093 pkts_num = new_pool->buf_num; 1094 if (pkts_num == 0) { 1095 if (port->priv->percpu_pools) { 1096 if (pool < port->nrxqs) 1097 pkts_num = mvpp2_pools[MVPP2_BM_SHORT].buf_num; 1098 else 1099 pkts_num = mvpp2_pools[MVPP2_BM_LONG].buf_num; 1100 } else { 1101 pkts_num = mvpp2_pools[pool].buf_num; 1102 } 1103 } else { 1104 mvpp2_bm_bufs_free(port->dev->dev.parent, 1105 port->priv, new_pool, pkts_num); 1106 } 1107 1108 new_pool->pkt_size = pkt_size; 1109 new_pool->frag_size = 1110 SKB_DATA_ALIGN(MVPP2_RX_BUF_SIZE(pkt_size)) + 1111 MVPP2_SKB_SHINFO_SIZE; 1112 1113 /* Allocate buffers for this pool */ 1114 num = mvpp2_bm_bufs_add(port, new_pool, pkts_num); 1115 if (num != pkts_num) { 1116 WARN(1, "pool %d: %d of %d allocated\n", 1117 new_pool->id, num, pkts_num); 1118 return NULL; 1119 } 1120 } 1121 1122 mvpp2_bm_pool_bufsize_set(port->priv, new_pool, 1123 MVPP2_RX_BUF_SIZE(new_pool->pkt_size)); 1124 1125 return new_pool; 1126 } 1127 1128 static struct mvpp2_bm_pool * 1129 mvpp2_bm_pool_use_percpu(struct mvpp2_port *port, int type, 1130 unsigned int pool, int pkt_size) 1131 { 1132 struct mvpp2_bm_pool *new_pool = &port->priv->bm_pools[pool]; 1133 int num; 1134 1135 if (pool > port->nrxqs * 2) { 1136 netdev_err(port->dev, "Invalid pool %d\n", pool); 1137 return NULL; 1138 } 1139 1140 /* Allocate buffers in case BM pool is used as long pool, but packet 1141 * size doesn't match MTU or BM pool hasn't being used yet 1142 */ 1143 if (new_pool->pkt_size == 0) { 1144 int pkts_num; 1145 1146 /* Set default buffer number or free all the buffers in case 1147 * the pool is not empty 1148 */ 1149 pkts_num = new_pool->buf_num; 1150 if (pkts_num == 0) 1151 pkts_num = mvpp2_pools[type].buf_num; 1152 else 1153 mvpp2_bm_bufs_free(port->dev->dev.parent, 1154 port->priv, new_pool, pkts_num); 1155 1156 new_pool->pkt_size = pkt_size; 1157 new_pool->frag_size = 1158 SKB_DATA_ALIGN(MVPP2_RX_BUF_SIZE(pkt_size)) + 1159 MVPP2_SKB_SHINFO_SIZE; 1160 1161 /* Allocate buffers for this pool */ 1162 num = mvpp2_bm_bufs_add(port, new_pool, pkts_num); 1163 if (num != pkts_num) { 1164 WARN(1, "pool %d: %d of %d allocated\n", 1165 new_pool->id, num, pkts_num); 1166 return NULL; 1167 } 1168 } 1169 1170 mvpp2_bm_pool_bufsize_set(port->priv, new_pool, 1171 MVPP2_RX_BUF_SIZE(new_pool->pkt_size)); 1172 1173 return new_pool; 1174 } 1175 1176 /* Initialize pools for swf, shared buffers variant */ 1177 static int mvpp2_swf_bm_pool_init_shared(struct mvpp2_port *port) 1178 { 1179 enum mvpp2_bm_pool_log_num long_log_pool, short_log_pool; 1180 int rxq; 1181 1182 /* If port pkt_size is higher than 1518B: 1183 * HW Long pool - SW Jumbo pool, HW Short pool - SW Long pool 1184 * else: HW Long pool - SW Long pool, HW Short pool - SW Short pool 1185 */ 1186 if (port->pkt_size > MVPP2_BM_LONG_PKT_SIZE) { 1187 long_log_pool = MVPP2_BM_JUMBO; 1188 short_log_pool = MVPP2_BM_LONG; 1189 } else { 1190 long_log_pool = MVPP2_BM_LONG; 1191 short_log_pool = MVPP2_BM_SHORT; 1192 } 1193 1194 if (!port->pool_long) { 1195 port->pool_long = 1196 mvpp2_bm_pool_use(port, long_log_pool, 1197 mvpp2_pools[long_log_pool].pkt_size); 1198 if (!port->pool_long) 1199 return -ENOMEM; 1200 1201 port->pool_long->port_map |= BIT(port->id); 1202 1203 for (rxq = 0; rxq < port->nrxqs; rxq++) 1204 mvpp2_rxq_long_pool_set(port, rxq, port->pool_long->id); 1205 } 1206 1207 if (!port->pool_short) { 1208 port->pool_short = 1209 mvpp2_bm_pool_use(port, short_log_pool, 1210 mvpp2_pools[short_log_pool].pkt_size); 1211 if (!port->pool_short) 1212 return -ENOMEM; 1213 1214 port->pool_short->port_map |= BIT(port->id); 1215 1216 for (rxq = 0; rxq < port->nrxqs; rxq++) 1217 mvpp2_rxq_short_pool_set(port, rxq, 1218 port->pool_short->id); 1219 } 1220 1221 return 0; 1222 } 1223 1224 /* Initialize pools for swf, percpu buffers variant */ 1225 static int mvpp2_swf_bm_pool_init_percpu(struct mvpp2_port *port) 1226 { 1227 struct mvpp2_bm_pool *bm_pool; 1228 int i; 1229 1230 for (i = 0; i < port->nrxqs; i++) { 1231 bm_pool = mvpp2_bm_pool_use_percpu(port, MVPP2_BM_SHORT, i, 1232 mvpp2_pools[MVPP2_BM_SHORT].pkt_size); 1233 if (!bm_pool) 1234 return -ENOMEM; 1235 1236 bm_pool->port_map |= BIT(port->id); 1237 mvpp2_rxq_short_pool_set(port, i, bm_pool->id); 1238 } 1239 1240 for (i = 0; i < port->nrxqs; i++) { 1241 bm_pool = mvpp2_bm_pool_use_percpu(port, MVPP2_BM_LONG, i + port->nrxqs, 1242 mvpp2_pools[MVPP2_BM_LONG].pkt_size); 1243 if (!bm_pool) 1244 return -ENOMEM; 1245 1246 bm_pool->port_map |= BIT(port->id); 1247 mvpp2_rxq_long_pool_set(port, i, bm_pool->id); 1248 } 1249 1250 port->pool_long = NULL; 1251 port->pool_short = NULL; 1252 1253 return 0; 1254 } 1255 1256 static int mvpp2_swf_bm_pool_init(struct mvpp2_port *port) 1257 { 1258 if (port->priv->percpu_pools) 1259 return mvpp2_swf_bm_pool_init_percpu(port); 1260 else 1261 return mvpp2_swf_bm_pool_init_shared(port); 1262 } 1263 1264 static void mvpp2_set_hw_csum(struct mvpp2_port *port, 1265 enum mvpp2_bm_pool_log_num new_long_pool) 1266 { 1267 const netdev_features_t csums = NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM; 1268 1269 /* Update L4 checksum when jumbo enable/disable on port. 1270 * Only port 0 supports hardware checksum offload due to 1271 * the Tx FIFO size limitation. 1272 * Also, don't set NETIF_F_HW_CSUM because L3_offset in TX descriptor 1273 * has 7 bits, so the maximum L3 offset is 128. 1274 */ 1275 if (new_long_pool == MVPP2_BM_JUMBO && port->id != 0) { 1276 port->dev->features &= ~csums; 1277 port->dev->hw_features &= ~csums; 1278 } else { 1279 port->dev->features |= csums; 1280 port->dev->hw_features |= csums; 1281 } 1282 } 1283 1284 static int mvpp2_bm_update_mtu(struct net_device *dev, int mtu) 1285 { 1286 struct mvpp2_port *port = netdev_priv(dev); 1287 enum mvpp2_bm_pool_log_num new_long_pool; 1288 int pkt_size = MVPP2_RX_PKT_SIZE(mtu); 1289 1290 if (port->priv->percpu_pools) 1291 goto out_set; 1292 1293 /* If port MTU is higher than 1518B: 1294 * HW Long pool - SW Jumbo pool, HW Short pool - SW Long pool 1295 * else: HW Long pool - SW Long pool, HW Short pool - SW Short pool 1296 */ 1297 if (pkt_size > MVPP2_BM_LONG_PKT_SIZE) 1298 new_long_pool = MVPP2_BM_JUMBO; 1299 else 1300 new_long_pool = MVPP2_BM_LONG; 1301 1302 if (new_long_pool != port->pool_long->id) { 1303 if (port->tx_fc) { 1304 if (pkt_size > MVPP2_BM_LONG_PKT_SIZE) 1305 mvpp2_bm_pool_update_fc(port, 1306 port->pool_short, 1307 false); 1308 else 1309 mvpp2_bm_pool_update_fc(port, port->pool_long, 1310 false); 1311 } 1312 1313 /* Remove port from old short & long pool */ 1314 port->pool_long = mvpp2_bm_pool_use(port, port->pool_long->id, 1315 port->pool_long->pkt_size); 1316 port->pool_long->port_map &= ~BIT(port->id); 1317 port->pool_long = NULL; 1318 1319 port->pool_short = mvpp2_bm_pool_use(port, port->pool_short->id, 1320 port->pool_short->pkt_size); 1321 port->pool_short->port_map &= ~BIT(port->id); 1322 port->pool_short = NULL; 1323 1324 port->pkt_size = pkt_size; 1325 1326 /* Add port to new short & long pool */ 1327 mvpp2_swf_bm_pool_init(port); 1328 1329 mvpp2_set_hw_csum(port, new_long_pool); 1330 1331 if (port->tx_fc) { 1332 if (pkt_size > MVPP2_BM_LONG_PKT_SIZE) 1333 mvpp2_bm_pool_update_fc(port, port->pool_long, 1334 true); 1335 else 1336 mvpp2_bm_pool_update_fc(port, port->pool_short, 1337 true); 1338 } 1339 1340 /* Update L4 checksum when jumbo enable/disable on port */ 1341 if (new_long_pool == MVPP2_BM_JUMBO && port->id != 0) { 1342 dev->features &= ~(NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM); 1343 dev->hw_features &= ~(NETIF_F_IP_CSUM | 1344 NETIF_F_IPV6_CSUM); 1345 } else { 1346 dev->features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM; 1347 dev->hw_features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM; 1348 } 1349 } 1350 1351 out_set: 1352 dev->mtu = mtu; 1353 dev->wanted_features = dev->features; 1354 1355 netdev_update_features(dev); 1356 return 0; 1357 } 1358 1359 static inline void mvpp2_interrupts_enable(struct mvpp2_port *port) 1360 { 1361 int i, sw_thread_mask = 0; 1362 1363 for (i = 0; i < port->nqvecs; i++) 1364 sw_thread_mask |= port->qvecs[i].sw_thread_mask; 1365 1366 mvpp2_write(port->priv, MVPP2_ISR_ENABLE_REG(port->id), 1367 MVPP2_ISR_ENABLE_INTERRUPT(sw_thread_mask)); 1368 } 1369 1370 static inline void mvpp2_interrupts_disable(struct mvpp2_port *port) 1371 { 1372 int i, sw_thread_mask = 0; 1373 1374 for (i = 0; i < port->nqvecs; i++) 1375 sw_thread_mask |= port->qvecs[i].sw_thread_mask; 1376 1377 mvpp2_write(port->priv, MVPP2_ISR_ENABLE_REG(port->id), 1378 MVPP2_ISR_DISABLE_INTERRUPT(sw_thread_mask)); 1379 } 1380 1381 static inline void mvpp2_qvec_interrupt_enable(struct mvpp2_queue_vector *qvec) 1382 { 1383 struct mvpp2_port *port = qvec->port; 1384 1385 mvpp2_write(port->priv, MVPP2_ISR_ENABLE_REG(port->id), 1386 MVPP2_ISR_ENABLE_INTERRUPT(qvec->sw_thread_mask)); 1387 } 1388 1389 static inline void mvpp2_qvec_interrupt_disable(struct mvpp2_queue_vector *qvec) 1390 { 1391 struct mvpp2_port *port = qvec->port; 1392 1393 mvpp2_write(port->priv, MVPP2_ISR_ENABLE_REG(port->id), 1394 MVPP2_ISR_DISABLE_INTERRUPT(qvec->sw_thread_mask)); 1395 } 1396 1397 /* Mask the current thread's Rx/Tx interrupts 1398 * Called by on_each_cpu(), guaranteed to run with migration disabled, 1399 * using smp_processor_id() is OK. 1400 */ 1401 static void mvpp2_interrupts_mask(void *arg) 1402 { 1403 struct mvpp2_port *port = arg; 1404 int cpu = smp_processor_id(); 1405 u32 thread; 1406 1407 /* If the thread isn't used, don't do anything */ 1408 if (cpu > port->priv->nthreads) 1409 return; 1410 1411 thread = mvpp2_cpu_to_thread(port->priv, cpu); 1412 1413 mvpp2_thread_write(port->priv, thread, 1414 MVPP2_ISR_RX_TX_MASK_REG(port->id), 0); 1415 mvpp2_thread_write(port->priv, thread, 1416 MVPP2_ISR_RX_ERR_CAUSE_REG(port->id), 0); 1417 } 1418 1419 /* Unmask the current thread's Rx/Tx interrupts. 1420 * Called by on_each_cpu(), guaranteed to run with migration disabled, 1421 * using smp_processor_id() is OK. 1422 */ 1423 static void mvpp2_interrupts_unmask(void *arg) 1424 { 1425 struct mvpp2_port *port = arg; 1426 int cpu = smp_processor_id(); 1427 u32 val, thread; 1428 1429 /* If the thread isn't used, don't do anything */ 1430 if (cpu >= port->priv->nthreads) 1431 return; 1432 1433 thread = mvpp2_cpu_to_thread(port->priv, cpu); 1434 1435 val = MVPP2_CAUSE_MISC_SUM_MASK | 1436 MVPP2_CAUSE_RXQ_OCCUP_DESC_ALL_MASK(port->priv->hw_version); 1437 if (port->has_tx_irqs) 1438 val |= MVPP2_CAUSE_TXQ_OCCUP_DESC_ALL_MASK; 1439 1440 mvpp2_thread_write(port->priv, thread, 1441 MVPP2_ISR_RX_TX_MASK_REG(port->id), val); 1442 mvpp2_thread_write(port->priv, thread, 1443 MVPP2_ISR_RX_ERR_CAUSE_REG(port->id), 1444 MVPP2_ISR_RX_ERR_CAUSE_NONOCC_MASK); 1445 } 1446 1447 static void 1448 mvpp2_shared_interrupt_mask_unmask(struct mvpp2_port *port, bool mask) 1449 { 1450 u32 val; 1451 int i; 1452 1453 if (port->priv->hw_version == MVPP21) 1454 return; 1455 1456 if (mask) 1457 val = 0; 1458 else 1459 val = MVPP2_CAUSE_RXQ_OCCUP_DESC_ALL_MASK(MVPP22); 1460 1461 for (i = 0; i < port->nqvecs; i++) { 1462 struct mvpp2_queue_vector *v = port->qvecs + i; 1463 1464 if (v->type != MVPP2_QUEUE_VECTOR_SHARED) 1465 continue; 1466 1467 mvpp2_thread_write(port->priv, v->sw_thread_id, 1468 MVPP2_ISR_RX_TX_MASK_REG(port->id), val); 1469 mvpp2_thread_write(port->priv, v->sw_thread_id, 1470 MVPP2_ISR_RX_ERR_CAUSE_REG(port->id), 1471 MVPP2_ISR_RX_ERR_CAUSE_NONOCC_MASK); 1472 } 1473 } 1474 1475 /* Only GOP port 0 has an XLG MAC */ 1476 static bool mvpp2_port_supports_xlg(struct mvpp2_port *port) 1477 { 1478 return port->gop_id == 0; 1479 } 1480 1481 static bool mvpp2_port_supports_rgmii(struct mvpp2_port *port) 1482 { 1483 return !(port->priv->hw_version >= MVPP22 && port->gop_id == 0); 1484 } 1485 1486 /* Port configuration routines */ 1487 static bool mvpp2_is_xlg(phy_interface_t interface) 1488 { 1489 return interface == PHY_INTERFACE_MODE_10GBASER || 1490 interface == PHY_INTERFACE_MODE_5GBASER || 1491 interface == PHY_INTERFACE_MODE_XAUI; 1492 } 1493 1494 static void mvpp2_modify(void __iomem *ptr, u32 mask, u32 set) 1495 { 1496 u32 old, val; 1497 1498 old = val = readl(ptr); 1499 val &= ~mask; 1500 val |= set; 1501 if (old != val) 1502 writel(val, ptr); 1503 } 1504 1505 static void mvpp22_gop_init_rgmii(struct mvpp2_port *port) 1506 { 1507 struct mvpp2 *priv = port->priv; 1508 u32 val; 1509 1510 regmap_read(priv->sysctrl_base, GENCONF_PORT_CTRL0, &val); 1511 val |= GENCONF_PORT_CTRL0_BUS_WIDTH_SELECT; 1512 regmap_write(priv->sysctrl_base, GENCONF_PORT_CTRL0, val); 1513 1514 regmap_read(priv->sysctrl_base, GENCONF_CTRL0, &val); 1515 if (port->gop_id == 2) 1516 val |= GENCONF_CTRL0_PORT2_RGMII; 1517 else if (port->gop_id == 3) 1518 val |= GENCONF_CTRL0_PORT3_RGMII_MII; 1519 regmap_write(priv->sysctrl_base, GENCONF_CTRL0, val); 1520 } 1521 1522 static void mvpp22_gop_init_sgmii(struct mvpp2_port *port) 1523 { 1524 struct mvpp2 *priv = port->priv; 1525 u32 val; 1526 1527 regmap_read(priv->sysctrl_base, GENCONF_PORT_CTRL0, &val); 1528 val |= GENCONF_PORT_CTRL0_BUS_WIDTH_SELECT | 1529 GENCONF_PORT_CTRL0_RX_DATA_SAMPLE; 1530 regmap_write(priv->sysctrl_base, GENCONF_PORT_CTRL0, val); 1531 1532 if (port->gop_id > 1) { 1533 regmap_read(priv->sysctrl_base, GENCONF_CTRL0, &val); 1534 if (port->gop_id == 2) 1535 val &= ~GENCONF_CTRL0_PORT2_RGMII; 1536 else if (port->gop_id == 3) 1537 val &= ~GENCONF_CTRL0_PORT3_RGMII_MII; 1538 regmap_write(priv->sysctrl_base, GENCONF_CTRL0, val); 1539 } 1540 } 1541 1542 static void mvpp22_gop_init_10gkr(struct mvpp2_port *port) 1543 { 1544 struct mvpp2 *priv = port->priv; 1545 void __iomem *mpcs = priv->iface_base + MVPP22_MPCS_BASE(port->gop_id); 1546 void __iomem *xpcs = priv->iface_base + MVPP22_XPCS_BASE(port->gop_id); 1547 u32 val; 1548 1549 val = readl(xpcs + MVPP22_XPCS_CFG0); 1550 val &= ~(MVPP22_XPCS_CFG0_PCS_MODE(0x3) | 1551 MVPP22_XPCS_CFG0_ACTIVE_LANE(0x3)); 1552 val |= MVPP22_XPCS_CFG0_ACTIVE_LANE(2); 1553 writel(val, xpcs + MVPP22_XPCS_CFG0); 1554 1555 val = readl(mpcs + MVPP22_MPCS_CTRL); 1556 val &= ~MVPP22_MPCS_CTRL_FWD_ERR_CONN; 1557 writel(val, mpcs + MVPP22_MPCS_CTRL); 1558 1559 val = readl(mpcs + MVPP22_MPCS_CLK_RESET); 1560 val &= ~MVPP22_MPCS_CLK_RESET_DIV_RATIO(0x7); 1561 val |= MVPP22_MPCS_CLK_RESET_DIV_RATIO(1); 1562 writel(val, mpcs + MVPP22_MPCS_CLK_RESET); 1563 } 1564 1565 static void mvpp22_gop_fca_enable_periodic(struct mvpp2_port *port, bool en) 1566 { 1567 struct mvpp2 *priv = port->priv; 1568 void __iomem *fca = priv->iface_base + MVPP22_FCA_BASE(port->gop_id); 1569 u32 val; 1570 1571 val = readl(fca + MVPP22_FCA_CONTROL_REG); 1572 val &= ~MVPP22_FCA_ENABLE_PERIODIC; 1573 if (en) 1574 val |= MVPP22_FCA_ENABLE_PERIODIC; 1575 writel(val, fca + MVPP22_FCA_CONTROL_REG); 1576 } 1577 1578 static void mvpp22_gop_fca_set_timer(struct mvpp2_port *port, u32 timer) 1579 { 1580 struct mvpp2 *priv = port->priv; 1581 void __iomem *fca = priv->iface_base + MVPP22_FCA_BASE(port->gop_id); 1582 u32 lsb, msb; 1583 1584 lsb = timer & MVPP22_FCA_REG_MASK; 1585 msb = timer >> MVPP22_FCA_REG_SIZE; 1586 1587 writel(lsb, fca + MVPP22_PERIODIC_COUNTER_LSB_REG); 1588 writel(msb, fca + MVPP22_PERIODIC_COUNTER_MSB_REG); 1589 } 1590 1591 /* Set Flow Control timer x100 faster than pause quanta to ensure that link 1592 * partner won't send traffic if port is in XOFF mode. 1593 */ 1594 static void mvpp22_gop_fca_set_periodic_timer(struct mvpp2_port *port) 1595 { 1596 u32 timer; 1597 1598 timer = (port->priv->tclk / (USEC_PER_SEC * FC_CLK_DIVIDER)) 1599 * FC_QUANTA; 1600 1601 mvpp22_gop_fca_enable_periodic(port, false); 1602 1603 mvpp22_gop_fca_set_timer(port, timer); 1604 1605 mvpp22_gop_fca_enable_periodic(port, true); 1606 } 1607 1608 static int mvpp22_gop_init(struct mvpp2_port *port, phy_interface_t interface) 1609 { 1610 struct mvpp2 *priv = port->priv; 1611 u32 val; 1612 1613 if (!priv->sysctrl_base) 1614 return 0; 1615 1616 switch (interface) { 1617 case PHY_INTERFACE_MODE_RGMII: 1618 case PHY_INTERFACE_MODE_RGMII_ID: 1619 case PHY_INTERFACE_MODE_RGMII_RXID: 1620 case PHY_INTERFACE_MODE_RGMII_TXID: 1621 if (!mvpp2_port_supports_rgmii(port)) 1622 goto invalid_conf; 1623 mvpp22_gop_init_rgmii(port); 1624 break; 1625 case PHY_INTERFACE_MODE_SGMII: 1626 case PHY_INTERFACE_MODE_1000BASEX: 1627 case PHY_INTERFACE_MODE_2500BASEX: 1628 mvpp22_gop_init_sgmii(port); 1629 break; 1630 case PHY_INTERFACE_MODE_5GBASER: 1631 case PHY_INTERFACE_MODE_10GBASER: 1632 if (!mvpp2_port_supports_xlg(port)) 1633 goto invalid_conf; 1634 mvpp22_gop_init_10gkr(port); 1635 break; 1636 default: 1637 goto unsupported_conf; 1638 } 1639 1640 regmap_read(priv->sysctrl_base, GENCONF_PORT_CTRL1, &val); 1641 val |= GENCONF_PORT_CTRL1_RESET(port->gop_id) | 1642 GENCONF_PORT_CTRL1_EN(port->gop_id); 1643 regmap_write(priv->sysctrl_base, GENCONF_PORT_CTRL1, val); 1644 1645 regmap_read(priv->sysctrl_base, GENCONF_PORT_CTRL0, &val); 1646 val |= GENCONF_PORT_CTRL0_CLK_DIV_PHASE_CLR; 1647 regmap_write(priv->sysctrl_base, GENCONF_PORT_CTRL0, val); 1648 1649 regmap_read(priv->sysctrl_base, GENCONF_SOFT_RESET1, &val); 1650 val |= GENCONF_SOFT_RESET1_GOP; 1651 regmap_write(priv->sysctrl_base, GENCONF_SOFT_RESET1, val); 1652 1653 mvpp22_gop_fca_set_periodic_timer(port); 1654 1655 unsupported_conf: 1656 return 0; 1657 1658 invalid_conf: 1659 netdev_err(port->dev, "Invalid port configuration\n"); 1660 return -EINVAL; 1661 } 1662 1663 static void mvpp22_gop_unmask_irq(struct mvpp2_port *port) 1664 { 1665 u32 val; 1666 1667 if (phy_interface_mode_is_rgmii(port->phy_interface) || 1668 phy_interface_mode_is_8023z(port->phy_interface) || 1669 port->phy_interface == PHY_INTERFACE_MODE_SGMII) { 1670 /* Enable the GMAC link status irq for this port */ 1671 val = readl(port->base + MVPP22_GMAC_INT_SUM_MASK); 1672 val |= MVPP22_GMAC_INT_SUM_MASK_LINK_STAT; 1673 writel(val, port->base + MVPP22_GMAC_INT_SUM_MASK); 1674 } 1675 1676 if (mvpp2_port_supports_xlg(port)) { 1677 /* Enable the XLG/GIG irqs for this port */ 1678 val = readl(port->base + MVPP22_XLG_EXT_INT_MASK); 1679 if (mvpp2_is_xlg(port->phy_interface)) 1680 val |= MVPP22_XLG_EXT_INT_MASK_XLG; 1681 else 1682 val |= MVPP22_XLG_EXT_INT_MASK_GIG; 1683 writel(val, port->base + MVPP22_XLG_EXT_INT_MASK); 1684 } 1685 } 1686 1687 static void mvpp22_gop_mask_irq(struct mvpp2_port *port) 1688 { 1689 u32 val; 1690 1691 if (mvpp2_port_supports_xlg(port)) { 1692 val = readl(port->base + MVPP22_XLG_EXT_INT_MASK); 1693 val &= ~(MVPP22_XLG_EXT_INT_MASK_XLG | 1694 MVPP22_XLG_EXT_INT_MASK_GIG); 1695 writel(val, port->base + MVPP22_XLG_EXT_INT_MASK); 1696 } 1697 1698 if (phy_interface_mode_is_rgmii(port->phy_interface) || 1699 phy_interface_mode_is_8023z(port->phy_interface) || 1700 port->phy_interface == PHY_INTERFACE_MODE_SGMII) { 1701 val = readl(port->base + MVPP22_GMAC_INT_SUM_MASK); 1702 val &= ~MVPP22_GMAC_INT_SUM_MASK_LINK_STAT; 1703 writel(val, port->base + MVPP22_GMAC_INT_SUM_MASK); 1704 } 1705 } 1706 1707 static void mvpp22_gop_setup_irq(struct mvpp2_port *port) 1708 { 1709 u32 val; 1710 1711 mvpp2_modify(port->base + MVPP22_GMAC_INT_SUM_MASK, 1712 MVPP22_GMAC_INT_SUM_MASK_PTP, 1713 MVPP22_GMAC_INT_SUM_MASK_PTP); 1714 1715 if (port->phylink || 1716 phy_interface_mode_is_rgmii(port->phy_interface) || 1717 phy_interface_mode_is_8023z(port->phy_interface) || 1718 port->phy_interface == PHY_INTERFACE_MODE_SGMII) { 1719 val = readl(port->base + MVPP22_GMAC_INT_MASK); 1720 val |= MVPP22_GMAC_INT_MASK_LINK_STAT; 1721 writel(val, port->base + MVPP22_GMAC_INT_MASK); 1722 } 1723 1724 if (mvpp2_port_supports_xlg(port)) { 1725 val = readl(port->base + MVPP22_XLG_INT_MASK); 1726 val |= MVPP22_XLG_INT_MASK_LINK; 1727 writel(val, port->base + MVPP22_XLG_INT_MASK); 1728 1729 mvpp2_modify(port->base + MVPP22_XLG_EXT_INT_MASK, 1730 MVPP22_XLG_EXT_INT_MASK_PTP, 1731 MVPP22_XLG_EXT_INT_MASK_PTP); 1732 } 1733 1734 mvpp22_gop_unmask_irq(port); 1735 } 1736 1737 /* Sets the PHY mode of the COMPHY (which configures the serdes lanes). 1738 * 1739 * The PHY mode used by the PPv2 driver comes from the network subsystem, while 1740 * the one given to the COMPHY comes from the generic PHY subsystem. Hence they 1741 * differ. 1742 * 1743 * The COMPHY configures the serdes lanes regardless of the actual use of the 1744 * lanes by the physical layer. This is why configurations like 1745 * "PPv2 (2500BaseX) - COMPHY (2500SGMII)" are valid. 1746 */ 1747 static int mvpp22_comphy_init(struct mvpp2_port *port, 1748 phy_interface_t interface) 1749 { 1750 int ret; 1751 1752 if (!port->comphy) 1753 return 0; 1754 1755 ret = phy_set_mode_ext(port->comphy, PHY_MODE_ETHERNET, interface); 1756 if (ret) 1757 return ret; 1758 1759 return phy_power_on(port->comphy); 1760 } 1761 1762 static void mvpp2_port_enable(struct mvpp2_port *port) 1763 { 1764 u32 val; 1765 1766 if (mvpp2_port_supports_xlg(port) && 1767 mvpp2_is_xlg(port->phy_interface)) { 1768 val = readl(port->base + MVPP22_XLG_CTRL0_REG); 1769 val |= MVPP22_XLG_CTRL0_PORT_EN; 1770 val &= ~MVPP22_XLG_CTRL0_MIB_CNT_DIS; 1771 writel(val, port->base + MVPP22_XLG_CTRL0_REG); 1772 } else { 1773 val = readl(port->base + MVPP2_GMAC_CTRL_0_REG); 1774 val |= MVPP2_GMAC_PORT_EN_MASK; 1775 val |= MVPP2_GMAC_MIB_CNTR_EN_MASK; 1776 writel(val, port->base + MVPP2_GMAC_CTRL_0_REG); 1777 } 1778 } 1779 1780 static void mvpp2_port_disable(struct mvpp2_port *port) 1781 { 1782 u32 val; 1783 1784 if (mvpp2_port_supports_xlg(port) && 1785 mvpp2_is_xlg(port->phy_interface)) { 1786 val = readl(port->base + MVPP22_XLG_CTRL0_REG); 1787 val &= ~MVPP22_XLG_CTRL0_PORT_EN; 1788 writel(val, port->base + MVPP22_XLG_CTRL0_REG); 1789 } 1790 1791 val = readl(port->base + MVPP2_GMAC_CTRL_0_REG); 1792 val &= ~(MVPP2_GMAC_PORT_EN_MASK); 1793 writel(val, port->base + MVPP2_GMAC_CTRL_0_REG); 1794 } 1795 1796 /* Set IEEE 802.3x Flow Control Xon Packet Transmission Mode */ 1797 static void mvpp2_port_periodic_xon_disable(struct mvpp2_port *port) 1798 { 1799 u32 val; 1800 1801 val = readl(port->base + MVPP2_GMAC_CTRL_1_REG) & 1802 ~MVPP2_GMAC_PERIODIC_XON_EN_MASK; 1803 writel(val, port->base + MVPP2_GMAC_CTRL_1_REG); 1804 } 1805 1806 /* Configure loopback port */ 1807 static void mvpp2_port_loopback_set(struct mvpp2_port *port, 1808 const struct phylink_link_state *state) 1809 { 1810 u32 val; 1811 1812 val = readl(port->base + MVPP2_GMAC_CTRL_1_REG); 1813 1814 if (state->speed == 1000) 1815 val |= MVPP2_GMAC_GMII_LB_EN_MASK; 1816 else 1817 val &= ~MVPP2_GMAC_GMII_LB_EN_MASK; 1818 1819 if (phy_interface_mode_is_8023z(state->interface) || 1820 state->interface == PHY_INTERFACE_MODE_SGMII) 1821 val |= MVPP2_GMAC_PCS_LB_EN_MASK; 1822 else 1823 val &= ~MVPP2_GMAC_PCS_LB_EN_MASK; 1824 1825 writel(val, port->base + MVPP2_GMAC_CTRL_1_REG); 1826 } 1827 1828 enum { 1829 ETHTOOL_XDP_REDIRECT, 1830 ETHTOOL_XDP_PASS, 1831 ETHTOOL_XDP_DROP, 1832 ETHTOOL_XDP_TX, 1833 ETHTOOL_XDP_TX_ERR, 1834 ETHTOOL_XDP_XMIT, 1835 ETHTOOL_XDP_XMIT_ERR, 1836 }; 1837 1838 struct mvpp2_ethtool_counter { 1839 unsigned int offset; 1840 const char string[ETH_GSTRING_LEN]; 1841 bool reg_is_64b; 1842 }; 1843 1844 static u64 mvpp2_read_count(struct mvpp2_port *port, 1845 const struct mvpp2_ethtool_counter *counter) 1846 { 1847 u64 val; 1848 1849 val = readl(port->stats_base + counter->offset); 1850 if (counter->reg_is_64b) 1851 val += (u64)readl(port->stats_base + counter->offset + 4) << 32; 1852 1853 return val; 1854 } 1855 1856 /* Some counters are accessed indirectly by first writing an index to 1857 * MVPP2_CTRS_IDX. The index can represent various resources depending on the 1858 * register we access, it can be a hit counter for some classification tables, 1859 * a counter specific to a rxq, a txq or a buffer pool. 1860 */ 1861 static u32 mvpp2_read_index(struct mvpp2 *priv, u32 index, u32 reg) 1862 { 1863 mvpp2_write(priv, MVPP2_CTRS_IDX, index); 1864 return mvpp2_read(priv, reg); 1865 } 1866 1867 /* Due to the fact that software statistics and hardware statistics are, by 1868 * design, incremented at different moments in the chain of packet processing, 1869 * it is very likely that incoming packets could have been dropped after being 1870 * counted by hardware but before reaching software statistics (most probably 1871 * multicast packets), and in the opposite way, during transmission, FCS bytes 1872 * are added in between as well as TSO skb will be split and header bytes added. 1873 * Hence, statistics gathered from userspace with ifconfig (software) and 1874 * ethtool (hardware) cannot be compared. 1875 */ 1876 static const struct mvpp2_ethtool_counter mvpp2_ethtool_mib_regs[] = { 1877 { MVPP2_MIB_GOOD_OCTETS_RCVD, "good_octets_received", true }, 1878 { MVPP2_MIB_BAD_OCTETS_RCVD, "bad_octets_received" }, 1879 { MVPP2_MIB_CRC_ERRORS_SENT, "crc_errors_sent" }, 1880 { MVPP2_MIB_UNICAST_FRAMES_RCVD, "unicast_frames_received" }, 1881 { MVPP2_MIB_BROADCAST_FRAMES_RCVD, "broadcast_frames_received" }, 1882 { MVPP2_MIB_MULTICAST_FRAMES_RCVD, "multicast_frames_received" }, 1883 { MVPP2_MIB_FRAMES_64_OCTETS, "frames_64_octets" }, 1884 { MVPP2_MIB_FRAMES_65_TO_127_OCTETS, "frames_65_to_127_octet" }, 1885 { MVPP2_MIB_FRAMES_128_TO_255_OCTETS, "frames_128_to_255_octet" }, 1886 { MVPP2_MIB_FRAMES_256_TO_511_OCTETS, "frames_256_to_511_octet" }, 1887 { MVPP2_MIB_FRAMES_512_TO_1023_OCTETS, "frames_512_to_1023_octet" }, 1888 { MVPP2_MIB_FRAMES_1024_TO_MAX_OCTETS, "frames_1024_to_max_octet" }, 1889 { MVPP2_MIB_GOOD_OCTETS_SENT, "good_octets_sent", true }, 1890 { MVPP2_MIB_UNICAST_FRAMES_SENT, "unicast_frames_sent" }, 1891 { MVPP2_MIB_MULTICAST_FRAMES_SENT, "multicast_frames_sent" }, 1892 { MVPP2_MIB_BROADCAST_FRAMES_SENT, "broadcast_frames_sent" }, 1893 { MVPP2_MIB_FC_SENT, "fc_sent" }, 1894 { MVPP2_MIB_FC_RCVD, "fc_received" }, 1895 { MVPP2_MIB_RX_FIFO_OVERRUN, "rx_fifo_overrun" }, 1896 { MVPP2_MIB_UNDERSIZE_RCVD, "undersize_received" }, 1897 { MVPP2_MIB_FRAGMENTS_RCVD, "fragments_received" }, 1898 { MVPP2_MIB_OVERSIZE_RCVD, "oversize_received" }, 1899 { MVPP2_MIB_JABBER_RCVD, "jabber_received" }, 1900 { MVPP2_MIB_MAC_RCV_ERROR, "mac_receive_error" }, 1901 { MVPP2_MIB_BAD_CRC_EVENT, "bad_crc_event" }, 1902 { MVPP2_MIB_COLLISION, "collision" }, 1903 { MVPP2_MIB_LATE_COLLISION, "late_collision" }, 1904 }; 1905 1906 static const struct mvpp2_ethtool_counter mvpp2_ethtool_port_regs[] = { 1907 { MVPP2_OVERRUN_ETH_DROP, "rx_fifo_or_parser_overrun_drops" }, 1908 { MVPP2_CLS_ETH_DROP, "rx_classifier_drops" }, 1909 }; 1910 1911 static const struct mvpp2_ethtool_counter mvpp2_ethtool_txq_regs[] = { 1912 { MVPP2_TX_DESC_ENQ_CTR, "txq_%d_desc_enqueue" }, 1913 { MVPP2_TX_DESC_ENQ_TO_DDR_CTR, "txq_%d_desc_enqueue_to_ddr" }, 1914 { MVPP2_TX_BUFF_ENQ_TO_DDR_CTR, "txq_%d_buff_euqueue_to_ddr" }, 1915 { MVPP2_TX_DESC_ENQ_HW_FWD_CTR, "txq_%d_desc_hardware_forwarded" }, 1916 { MVPP2_TX_PKTS_DEQ_CTR, "txq_%d_packets_dequeued" }, 1917 { MVPP2_TX_PKTS_FULL_QUEUE_DROP_CTR, "txq_%d_queue_full_drops" }, 1918 { MVPP2_TX_PKTS_EARLY_DROP_CTR, "txq_%d_packets_early_drops" }, 1919 { MVPP2_TX_PKTS_BM_DROP_CTR, "txq_%d_packets_bm_drops" }, 1920 { MVPP2_TX_PKTS_BM_MC_DROP_CTR, "txq_%d_packets_rep_bm_drops" }, 1921 }; 1922 1923 static const struct mvpp2_ethtool_counter mvpp2_ethtool_rxq_regs[] = { 1924 { MVPP2_RX_DESC_ENQ_CTR, "rxq_%d_desc_enqueue" }, 1925 { MVPP2_RX_PKTS_FULL_QUEUE_DROP_CTR, "rxq_%d_queue_full_drops" }, 1926 { MVPP2_RX_PKTS_EARLY_DROP_CTR, "rxq_%d_packets_early_drops" }, 1927 { MVPP2_RX_PKTS_BM_DROP_CTR, "rxq_%d_packets_bm_drops" }, 1928 }; 1929 1930 static const struct mvpp2_ethtool_counter mvpp2_ethtool_xdp[] = { 1931 { ETHTOOL_XDP_REDIRECT, "rx_xdp_redirect", }, 1932 { ETHTOOL_XDP_PASS, "rx_xdp_pass", }, 1933 { ETHTOOL_XDP_DROP, "rx_xdp_drop", }, 1934 { ETHTOOL_XDP_TX, "rx_xdp_tx", }, 1935 { ETHTOOL_XDP_TX_ERR, "rx_xdp_tx_errors", }, 1936 { ETHTOOL_XDP_XMIT, "tx_xdp_xmit", }, 1937 { ETHTOOL_XDP_XMIT_ERR, "tx_xdp_xmit_errors", }, 1938 }; 1939 1940 #define MVPP2_N_ETHTOOL_STATS(ntxqs, nrxqs) (ARRAY_SIZE(mvpp2_ethtool_mib_regs) + \ 1941 ARRAY_SIZE(mvpp2_ethtool_port_regs) + \ 1942 (ARRAY_SIZE(mvpp2_ethtool_txq_regs) * (ntxqs)) + \ 1943 (ARRAY_SIZE(mvpp2_ethtool_rxq_regs) * (nrxqs)) + \ 1944 ARRAY_SIZE(mvpp2_ethtool_xdp)) 1945 1946 static void mvpp2_ethtool_get_strings(struct net_device *netdev, u32 sset, 1947 u8 *data) 1948 { 1949 struct mvpp2_port *port = netdev_priv(netdev); 1950 int i, q; 1951 1952 if (sset != ETH_SS_STATS) 1953 return; 1954 1955 for (i = 0; i < ARRAY_SIZE(mvpp2_ethtool_mib_regs); i++) { 1956 strscpy(data, mvpp2_ethtool_mib_regs[i].string, 1957 ETH_GSTRING_LEN); 1958 data += ETH_GSTRING_LEN; 1959 } 1960 1961 for (i = 0; i < ARRAY_SIZE(mvpp2_ethtool_port_regs); i++) { 1962 strscpy(data, mvpp2_ethtool_port_regs[i].string, 1963 ETH_GSTRING_LEN); 1964 data += ETH_GSTRING_LEN; 1965 } 1966 1967 for (q = 0; q < port->ntxqs; q++) { 1968 for (i = 0; i < ARRAY_SIZE(mvpp2_ethtool_txq_regs); i++) { 1969 snprintf(data, ETH_GSTRING_LEN, 1970 mvpp2_ethtool_txq_regs[i].string, q); 1971 data += ETH_GSTRING_LEN; 1972 } 1973 } 1974 1975 for (q = 0; q < port->nrxqs; q++) { 1976 for (i = 0; i < ARRAY_SIZE(mvpp2_ethtool_rxq_regs); i++) { 1977 snprintf(data, ETH_GSTRING_LEN, 1978 mvpp2_ethtool_rxq_regs[i].string, 1979 q); 1980 data += ETH_GSTRING_LEN; 1981 } 1982 } 1983 1984 for (i = 0; i < ARRAY_SIZE(mvpp2_ethtool_xdp); i++) { 1985 strscpy(data, mvpp2_ethtool_xdp[i].string, 1986 ETH_GSTRING_LEN); 1987 data += ETH_GSTRING_LEN; 1988 } 1989 } 1990 1991 static void 1992 mvpp2_get_xdp_stats(struct mvpp2_port *port, struct mvpp2_pcpu_stats *xdp_stats) 1993 { 1994 unsigned int start; 1995 unsigned int cpu; 1996 1997 /* Gather XDP Statistics */ 1998 for_each_possible_cpu(cpu) { 1999 struct mvpp2_pcpu_stats *cpu_stats; 2000 u64 xdp_redirect; 2001 u64 xdp_pass; 2002 u64 xdp_drop; 2003 u64 xdp_xmit; 2004 u64 xdp_xmit_err; 2005 u64 xdp_tx; 2006 u64 xdp_tx_err; 2007 2008 cpu_stats = per_cpu_ptr(port->stats, cpu); 2009 do { 2010 start = u64_stats_fetch_begin(&cpu_stats->syncp); 2011 xdp_redirect = cpu_stats->xdp_redirect; 2012 xdp_pass = cpu_stats->xdp_pass; 2013 xdp_drop = cpu_stats->xdp_drop; 2014 xdp_xmit = cpu_stats->xdp_xmit; 2015 xdp_xmit_err = cpu_stats->xdp_xmit_err; 2016 xdp_tx = cpu_stats->xdp_tx; 2017 xdp_tx_err = cpu_stats->xdp_tx_err; 2018 } while (u64_stats_fetch_retry(&cpu_stats->syncp, start)); 2019 2020 xdp_stats->xdp_redirect += xdp_redirect; 2021 xdp_stats->xdp_pass += xdp_pass; 2022 xdp_stats->xdp_drop += xdp_drop; 2023 xdp_stats->xdp_xmit += xdp_xmit; 2024 xdp_stats->xdp_xmit_err += xdp_xmit_err; 2025 xdp_stats->xdp_tx += xdp_tx; 2026 xdp_stats->xdp_tx_err += xdp_tx_err; 2027 } 2028 } 2029 2030 static void mvpp2_read_stats(struct mvpp2_port *port) 2031 { 2032 struct mvpp2_pcpu_stats xdp_stats = {}; 2033 const struct mvpp2_ethtool_counter *s; 2034 u64 *pstats; 2035 int i, q; 2036 2037 pstats = port->ethtool_stats; 2038 2039 for (i = 0; i < ARRAY_SIZE(mvpp2_ethtool_mib_regs); i++) 2040 *pstats++ += mvpp2_read_count(port, &mvpp2_ethtool_mib_regs[i]); 2041 2042 for (i = 0; i < ARRAY_SIZE(mvpp2_ethtool_port_regs); i++) 2043 *pstats++ += mvpp2_read(port->priv, 2044 mvpp2_ethtool_port_regs[i].offset + 2045 4 * port->id); 2046 2047 for (q = 0; q < port->ntxqs; q++) 2048 for (i = 0; i < ARRAY_SIZE(mvpp2_ethtool_txq_regs); i++) 2049 *pstats++ += mvpp2_read_index(port->priv, 2050 MVPP22_CTRS_TX_CTR(port->id, q), 2051 mvpp2_ethtool_txq_regs[i].offset); 2052 2053 /* Rxqs are numbered from 0 from the user standpoint, but not from the 2054 * driver's. We need to add the port->first_rxq offset. 2055 */ 2056 for (q = 0; q < port->nrxqs; q++) 2057 for (i = 0; i < ARRAY_SIZE(mvpp2_ethtool_rxq_regs); i++) 2058 *pstats++ += mvpp2_read_index(port->priv, 2059 port->first_rxq + q, 2060 mvpp2_ethtool_rxq_regs[i].offset); 2061 2062 /* Gather XDP Statistics */ 2063 mvpp2_get_xdp_stats(port, &xdp_stats); 2064 2065 for (i = 0, s = mvpp2_ethtool_xdp; 2066 s < mvpp2_ethtool_xdp + ARRAY_SIZE(mvpp2_ethtool_xdp); 2067 s++, i++) { 2068 switch (s->offset) { 2069 case ETHTOOL_XDP_REDIRECT: 2070 *pstats++ = xdp_stats.xdp_redirect; 2071 break; 2072 case ETHTOOL_XDP_PASS: 2073 *pstats++ = xdp_stats.xdp_pass; 2074 break; 2075 case ETHTOOL_XDP_DROP: 2076 *pstats++ = xdp_stats.xdp_drop; 2077 break; 2078 case ETHTOOL_XDP_TX: 2079 *pstats++ = xdp_stats.xdp_tx; 2080 break; 2081 case ETHTOOL_XDP_TX_ERR: 2082 *pstats++ = xdp_stats.xdp_tx_err; 2083 break; 2084 case ETHTOOL_XDP_XMIT: 2085 *pstats++ = xdp_stats.xdp_xmit; 2086 break; 2087 case ETHTOOL_XDP_XMIT_ERR: 2088 *pstats++ = xdp_stats.xdp_xmit_err; 2089 break; 2090 } 2091 } 2092 } 2093 2094 static void mvpp2_gather_hw_statistics(struct work_struct *work) 2095 { 2096 struct delayed_work *del_work = to_delayed_work(work); 2097 struct mvpp2_port *port = container_of(del_work, struct mvpp2_port, 2098 stats_work); 2099 2100 mutex_lock(&port->gather_stats_lock); 2101 2102 mvpp2_read_stats(port); 2103 2104 /* No need to read again the counters right after this function if it 2105 * was called asynchronously by the user (ie. use of ethtool). 2106 */ 2107 cancel_delayed_work(&port->stats_work); 2108 queue_delayed_work(port->priv->stats_queue, &port->stats_work, 2109 MVPP2_MIB_COUNTERS_STATS_DELAY); 2110 2111 mutex_unlock(&port->gather_stats_lock); 2112 } 2113 2114 static void mvpp2_ethtool_get_stats(struct net_device *dev, 2115 struct ethtool_stats *stats, u64 *data) 2116 { 2117 struct mvpp2_port *port = netdev_priv(dev); 2118 2119 /* Update statistics for the given port, then take the lock to avoid 2120 * concurrent accesses on the ethtool_stats structure during its copy. 2121 */ 2122 mvpp2_gather_hw_statistics(&port->stats_work.work); 2123 2124 mutex_lock(&port->gather_stats_lock); 2125 memcpy(data, port->ethtool_stats, 2126 sizeof(u64) * MVPP2_N_ETHTOOL_STATS(port->ntxqs, port->nrxqs)); 2127 mutex_unlock(&port->gather_stats_lock); 2128 } 2129 2130 static int mvpp2_ethtool_get_sset_count(struct net_device *dev, int sset) 2131 { 2132 struct mvpp2_port *port = netdev_priv(dev); 2133 2134 if (sset == ETH_SS_STATS) 2135 return MVPP2_N_ETHTOOL_STATS(port->ntxqs, port->nrxqs); 2136 2137 return -EOPNOTSUPP; 2138 } 2139 2140 static void mvpp2_mac_reset_assert(struct mvpp2_port *port) 2141 { 2142 u32 val; 2143 2144 val = readl(port->base + MVPP2_GMAC_CTRL_2_REG) | 2145 MVPP2_GMAC_PORT_RESET_MASK; 2146 writel(val, port->base + MVPP2_GMAC_CTRL_2_REG); 2147 2148 if (port->priv->hw_version >= MVPP22 && port->gop_id == 0) { 2149 val = readl(port->base + MVPP22_XLG_CTRL0_REG) & 2150 ~MVPP22_XLG_CTRL0_MAC_RESET_DIS; 2151 writel(val, port->base + MVPP22_XLG_CTRL0_REG); 2152 } 2153 } 2154 2155 static void mvpp22_pcs_reset_assert(struct mvpp2_port *port) 2156 { 2157 struct mvpp2 *priv = port->priv; 2158 void __iomem *mpcs, *xpcs; 2159 u32 val; 2160 2161 if (port->priv->hw_version == MVPP21 || port->gop_id != 0) 2162 return; 2163 2164 mpcs = priv->iface_base + MVPP22_MPCS_BASE(port->gop_id); 2165 xpcs = priv->iface_base + MVPP22_XPCS_BASE(port->gop_id); 2166 2167 val = readl(mpcs + MVPP22_MPCS_CLK_RESET); 2168 val &= ~(MAC_CLK_RESET_MAC | MAC_CLK_RESET_SD_RX | MAC_CLK_RESET_SD_TX); 2169 val |= MVPP22_MPCS_CLK_RESET_DIV_SET; 2170 writel(val, mpcs + MVPP22_MPCS_CLK_RESET); 2171 2172 val = readl(xpcs + MVPP22_XPCS_CFG0); 2173 writel(val & ~MVPP22_XPCS_CFG0_RESET_DIS, xpcs + MVPP22_XPCS_CFG0); 2174 } 2175 2176 static void mvpp22_pcs_reset_deassert(struct mvpp2_port *port, 2177 phy_interface_t interface) 2178 { 2179 struct mvpp2 *priv = port->priv; 2180 void __iomem *mpcs, *xpcs; 2181 u32 val; 2182 2183 if (port->priv->hw_version == MVPP21 || port->gop_id != 0) 2184 return; 2185 2186 mpcs = priv->iface_base + MVPP22_MPCS_BASE(port->gop_id); 2187 xpcs = priv->iface_base + MVPP22_XPCS_BASE(port->gop_id); 2188 2189 switch (interface) { 2190 case PHY_INTERFACE_MODE_5GBASER: 2191 case PHY_INTERFACE_MODE_10GBASER: 2192 val = readl(mpcs + MVPP22_MPCS_CLK_RESET); 2193 val |= MAC_CLK_RESET_MAC | MAC_CLK_RESET_SD_RX | 2194 MAC_CLK_RESET_SD_TX; 2195 val &= ~MVPP22_MPCS_CLK_RESET_DIV_SET; 2196 writel(val, mpcs + MVPP22_MPCS_CLK_RESET); 2197 break; 2198 case PHY_INTERFACE_MODE_XAUI: 2199 case PHY_INTERFACE_MODE_RXAUI: 2200 val = readl(xpcs + MVPP22_XPCS_CFG0); 2201 writel(val | MVPP22_XPCS_CFG0_RESET_DIS, xpcs + MVPP22_XPCS_CFG0); 2202 break; 2203 default: 2204 break; 2205 } 2206 } 2207 2208 /* Change maximum receive size of the port */ 2209 static inline void mvpp2_gmac_max_rx_size_set(struct mvpp2_port *port) 2210 { 2211 u32 val; 2212 2213 val = readl(port->base + MVPP2_GMAC_CTRL_0_REG); 2214 val &= ~MVPP2_GMAC_MAX_RX_SIZE_MASK; 2215 val |= (((port->pkt_size - MVPP2_MH_SIZE) / 2) << 2216 MVPP2_GMAC_MAX_RX_SIZE_OFFS); 2217 writel(val, port->base + MVPP2_GMAC_CTRL_0_REG); 2218 } 2219 2220 /* Change maximum receive size of the port */ 2221 static inline void mvpp2_xlg_max_rx_size_set(struct mvpp2_port *port) 2222 { 2223 u32 val; 2224 2225 val = readl(port->base + MVPP22_XLG_CTRL1_REG); 2226 val &= ~MVPP22_XLG_CTRL1_FRAMESIZELIMIT_MASK; 2227 val |= ((port->pkt_size - MVPP2_MH_SIZE) / 2) << 2228 MVPP22_XLG_CTRL1_FRAMESIZELIMIT_OFFS; 2229 writel(val, port->base + MVPP22_XLG_CTRL1_REG); 2230 } 2231 2232 /* Set defaults to the MVPP2 port */ 2233 static void mvpp2_defaults_set(struct mvpp2_port *port) 2234 { 2235 int tx_port_num, val, queue, lrxq; 2236 2237 if (port->priv->hw_version == MVPP21) { 2238 /* Update TX FIFO MIN Threshold */ 2239 val = readl(port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG); 2240 val &= ~MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK; 2241 /* Min. TX threshold must be less than minimal packet length */ 2242 val |= MVPP2_GMAC_TX_FIFO_MIN_TH_MASK(64 - 4 - 2); 2243 writel(val, port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG); 2244 } 2245 2246 /* Disable Legacy WRR, Disable EJP, Release from reset */ 2247 tx_port_num = mvpp2_egress_port(port); 2248 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, 2249 tx_port_num); 2250 mvpp2_write(port->priv, MVPP2_TXP_SCHED_CMD_1_REG, 0); 2251 2252 /* Set TXQ scheduling to Round-Robin */ 2253 mvpp2_write(port->priv, MVPP2_TXP_SCHED_FIXED_PRIO_REG, 0); 2254 2255 /* Close bandwidth for all queues */ 2256 for (queue = 0; queue < MVPP2_MAX_TXQ; queue++) 2257 mvpp2_write(port->priv, 2258 MVPP2_TXQ_SCHED_TOKEN_CNTR_REG(queue), 0); 2259 2260 /* Set refill period to 1 usec, refill tokens 2261 * and bucket size to maximum 2262 */ 2263 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PERIOD_REG, 2264 port->priv->tclk / USEC_PER_SEC); 2265 val = mvpp2_read(port->priv, MVPP2_TXP_SCHED_REFILL_REG); 2266 val &= ~MVPP2_TXP_REFILL_PERIOD_ALL_MASK; 2267 val |= MVPP2_TXP_REFILL_PERIOD_MASK(1); 2268 val |= MVPP2_TXP_REFILL_TOKENS_ALL_MASK; 2269 mvpp2_write(port->priv, MVPP2_TXP_SCHED_REFILL_REG, val); 2270 val = MVPP2_TXP_TOKEN_SIZE_MAX; 2271 mvpp2_write(port->priv, MVPP2_TXP_SCHED_TOKEN_SIZE_REG, val); 2272 2273 /* Set MaximumLowLatencyPacketSize value to 256 */ 2274 mvpp2_write(port->priv, MVPP2_RX_CTRL_REG(port->id), 2275 MVPP2_RX_USE_PSEUDO_FOR_CSUM_MASK | 2276 MVPP2_RX_LOW_LATENCY_PKT_SIZE(256)); 2277 2278 /* Enable Rx cache snoop */ 2279 for (lrxq = 0; lrxq < port->nrxqs; lrxq++) { 2280 queue = port->rxqs[lrxq]->id; 2281 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(queue)); 2282 val |= MVPP2_SNOOP_PKT_SIZE_MASK | 2283 MVPP2_SNOOP_BUF_HDR_MASK; 2284 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(queue), val); 2285 } 2286 2287 /* At default, mask all interrupts to all present cpus */ 2288 mvpp2_interrupts_disable(port); 2289 } 2290 2291 /* Enable/disable receiving packets */ 2292 static void mvpp2_ingress_enable(struct mvpp2_port *port) 2293 { 2294 u32 val; 2295 int lrxq, queue; 2296 2297 for (lrxq = 0; lrxq < port->nrxqs; lrxq++) { 2298 queue = port->rxqs[lrxq]->id; 2299 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(queue)); 2300 val &= ~MVPP2_RXQ_DISABLE_MASK; 2301 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(queue), val); 2302 } 2303 } 2304 2305 static void mvpp2_ingress_disable(struct mvpp2_port *port) 2306 { 2307 u32 val; 2308 int lrxq, queue; 2309 2310 for (lrxq = 0; lrxq < port->nrxqs; lrxq++) { 2311 queue = port->rxqs[lrxq]->id; 2312 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(queue)); 2313 val |= MVPP2_RXQ_DISABLE_MASK; 2314 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(queue), val); 2315 } 2316 } 2317 2318 /* Enable transmit via physical egress queue 2319 * - HW starts take descriptors from DRAM 2320 */ 2321 static void mvpp2_egress_enable(struct mvpp2_port *port) 2322 { 2323 u32 qmap; 2324 int queue; 2325 int tx_port_num = mvpp2_egress_port(port); 2326 2327 /* Enable all initialized TXs. */ 2328 qmap = 0; 2329 for (queue = 0; queue < port->ntxqs; queue++) { 2330 struct mvpp2_tx_queue *txq = port->txqs[queue]; 2331 2332 if (txq->descs) 2333 qmap |= (1 << queue); 2334 } 2335 2336 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num); 2337 mvpp2_write(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG, qmap); 2338 } 2339 2340 /* Disable transmit via physical egress queue 2341 * - HW doesn't take descriptors from DRAM 2342 */ 2343 static void mvpp2_egress_disable(struct mvpp2_port *port) 2344 { 2345 u32 reg_data; 2346 int delay; 2347 int tx_port_num = mvpp2_egress_port(port); 2348 2349 /* Issue stop command for active channels only */ 2350 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num); 2351 reg_data = (mvpp2_read(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG)) & 2352 MVPP2_TXP_SCHED_ENQ_MASK; 2353 if (reg_data != 0) 2354 mvpp2_write(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG, 2355 (reg_data << MVPP2_TXP_SCHED_DISQ_OFFSET)); 2356 2357 /* Wait for all Tx activity to terminate. */ 2358 delay = 0; 2359 do { 2360 if (delay >= MVPP2_TX_DISABLE_TIMEOUT_MSEC) { 2361 netdev_warn(port->dev, 2362 "Tx stop timed out, status=0x%08x\n", 2363 reg_data); 2364 break; 2365 } 2366 mdelay(1); 2367 delay++; 2368 2369 /* Check port TX Command register that all 2370 * Tx queues are stopped 2371 */ 2372 reg_data = mvpp2_read(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG); 2373 } while (reg_data & MVPP2_TXP_SCHED_ENQ_MASK); 2374 } 2375 2376 /* Rx descriptors helper methods */ 2377 2378 /* Get number of Rx descriptors occupied by received packets */ 2379 static inline int 2380 mvpp2_rxq_received(struct mvpp2_port *port, int rxq_id) 2381 { 2382 u32 val = mvpp2_read(port->priv, MVPP2_RXQ_STATUS_REG(rxq_id)); 2383 2384 return val & MVPP2_RXQ_OCCUPIED_MASK; 2385 } 2386 2387 /* Update Rx queue status with the number of occupied and available 2388 * Rx descriptor slots. 2389 */ 2390 static inline void 2391 mvpp2_rxq_status_update(struct mvpp2_port *port, int rxq_id, 2392 int used_count, int free_count) 2393 { 2394 /* Decrement the number of used descriptors and increment count 2395 * increment the number of free descriptors. 2396 */ 2397 u32 val = used_count | (free_count << MVPP2_RXQ_NUM_NEW_OFFSET); 2398 2399 mvpp2_write(port->priv, MVPP2_RXQ_STATUS_UPDATE_REG(rxq_id), val); 2400 } 2401 2402 /* Get pointer to next RX descriptor to be processed by SW */ 2403 static inline struct mvpp2_rx_desc * 2404 mvpp2_rxq_next_desc_get(struct mvpp2_rx_queue *rxq) 2405 { 2406 int rx_desc = rxq->next_desc_to_proc; 2407 2408 rxq->next_desc_to_proc = MVPP2_QUEUE_NEXT_DESC(rxq, rx_desc); 2409 prefetch(rxq->descs + rxq->next_desc_to_proc); 2410 return rxq->descs + rx_desc; 2411 } 2412 2413 /* Set rx queue offset */ 2414 static void mvpp2_rxq_offset_set(struct mvpp2_port *port, 2415 int prxq, int offset) 2416 { 2417 u32 val; 2418 2419 /* Convert offset from bytes to units of 32 bytes */ 2420 offset = offset >> 5; 2421 2422 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(prxq)); 2423 val &= ~MVPP2_RXQ_PACKET_OFFSET_MASK; 2424 2425 /* Offset is in */ 2426 val |= ((offset << MVPP2_RXQ_PACKET_OFFSET_OFFS) & 2427 MVPP2_RXQ_PACKET_OFFSET_MASK); 2428 2429 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(prxq), val); 2430 } 2431 2432 /* Tx descriptors helper methods */ 2433 2434 /* Get pointer to next Tx descriptor to be processed (send) by HW */ 2435 static struct mvpp2_tx_desc * 2436 mvpp2_txq_next_desc_get(struct mvpp2_tx_queue *txq) 2437 { 2438 int tx_desc = txq->next_desc_to_proc; 2439 2440 txq->next_desc_to_proc = MVPP2_QUEUE_NEXT_DESC(txq, tx_desc); 2441 return txq->descs + tx_desc; 2442 } 2443 2444 /* Update HW with number of aggregated Tx descriptors to be sent 2445 * 2446 * Called only from mvpp2_tx(), so migration is disabled, using 2447 * smp_processor_id() is OK. 2448 */ 2449 static void mvpp2_aggr_txq_pend_desc_add(struct mvpp2_port *port, int pending) 2450 { 2451 /* aggregated access - relevant TXQ number is written in TX desc */ 2452 mvpp2_thread_write(port->priv, 2453 mvpp2_cpu_to_thread(port->priv, smp_processor_id()), 2454 MVPP2_AGGR_TXQ_UPDATE_REG, pending); 2455 } 2456 2457 /* Check if there are enough free descriptors in aggregated txq. 2458 * If not, update the number of occupied descriptors and repeat the check. 2459 * 2460 * Called only from mvpp2_tx(), so migration is disabled, using 2461 * smp_processor_id() is OK. 2462 */ 2463 static int mvpp2_aggr_desc_num_check(struct mvpp2_port *port, 2464 struct mvpp2_tx_queue *aggr_txq, int num) 2465 { 2466 if ((aggr_txq->count + num) > MVPP2_AGGR_TXQ_SIZE) { 2467 /* Update number of occupied aggregated Tx descriptors */ 2468 unsigned int thread = 2469 mvpp2_cpu_to_thread(port->priv, smp_processor_id()); 2470 u32 val = mvpp2_read_relaxed(port->priv, 2471 MVPP2_AGGR_TXQ_STATUS_REG(thread)); 2472 2473 aggr_txq->count = val & MVPP2_AGGR_TXQ_PENDING_MASK; 2474 2475 if ((aggr_txq->count + num) > MVPP2_AGGR_TXQ_SIZE) 2476 return -ENOMEM; 2477 } 2478 return 0; 2479 } 2480 2481 /* Reserved Tx descriptors allocation request 2482 * 2483 * Called only from mvpp2_txq_reserved_desc_num_proc(), itself called 2484 * only by mvpp2_tx(), so migration is disabled, using 2485 * smp_processor_id() is OK. 2486 */ 2487 static int mvpp2_txq_alloc_reserved_desc(struct mvpp2_port *port, 2488 struct mvpp2_tx_queue *txq, int num) 2489 { 2490 unsigned int thread = mvpp2_cpu_to_thread(port->priv, smp_processor_id()); 2491 struct mvpp2 *priv = port->priv; 2492 u32 val; 2493 2494 val = (txq->id << MVPP2_TXQ_RSVD_REQ_Q_OFFSET) | num; 2495 mvpp2_thread_write_relaxed(priv, thread, MVPP2_TXQ_RSVD_REQ_REG, val); 2496 2497 val = mvpp2_thread_read_relaxed(priv, thread, MVPP2_TXQ_RSVD_RSLT_REG); 2498 2499 return val & MVPP2_TXQ_RSVD_RSLT_MASK; 2500 } 2501 2502 /* Check if there are enough reserved descriptors for transmission. 2503 * If not, request chunk of reserved descriptors and check again. 2504 */ 2505 static int mvpp2_txq_reserved_desc_num_proc(struct mvpp2_port *port, 2506 struct mvpp2_tx_queue *txq, 2507 struct mvpp2_txq_pcpu *txq_pcpu, 2508 int num) 2509 { 2510 int req, desc_count; 2511 unsigned int thread; 2512 2513 if (txq_pcpu->reserved_num >= num) 2514 return 0; 2515 2516 /* Not enough descriptors reserved! Update the reserved descriptor 2517 * count and check again. 2518 */ 2519 2520 desc_count = 0; 2521 /* Compute total of used descriptors */ 2522 for (thread = 0; thread < port->priv->nthreads; thread++) { 2523 struct mvpp2_txq_pcpu *txq_pcpu_aux; 2524 2525 txq_pcpu_aux = per_cpu_ptr(txq->pcpu, thread); 2526 desc_count += txq_pcpu_aux->count; 2527 desc_count += txq_pcpu_aux->reserved_num; 2528 } 2529 2530 req = max(MVPP2_CPU_DESC_CHUNK, num - txq_pcpu->reserved_num); 2531 desc_count += req; 2532 2533 if (desc_count > 2534 (txq->size - (MVPP2_MAX_THREADS * MVPP2_CPU_DESC_CHUNK))) 2535 return -ENOMEM; 2536 2537 txq_pcpu->reserved_num += mvpp2_txq_alloc_reserved_desc(port, txq, req); 2538 2539 /* OK, the descriptor could have been updated: check again. */ 2540 if (txq_pcpu->reserved_num < num) 2541 return -ENOMEM; 2542 return 0; 2543 } 2544 2545 /* Release the last allocated Tx descriptor. Useful to handle DMA 2546 * mapping failures in the Tx path. 2547 */ 2548 static void mvpp2_txq_desc_put(struct mvpp2_tx_queue *txq) 2549 { 2550 if (txq->next_desc_to_proc == 0) 2551 txq->next_desc_to_proc = txq->last_desc - 1; 2552 else 2553 txq->next_desc_to_proc--; 2554 } 2555 2556 /* Set Tx descriptors fields relevant for CSUM calculation */ 2557 static u32 mvpp2_txq_desc_csum(int l3_offs, __be16 l3_proto, 2558 int ip_hdr_len, int l4_proto) 2559 { 2560 u32 command; 2561 2562 /* fields: L3_offset, IP_hdrlen, L3_type, G_IPv4_chk, 2563 * G_L4_chk, L4_type required only for checksum calculation 2564 */ 2565 command = (l3_offs << MVPP2_TXD_L3_OFF_SHIFT); 2566 command |= (ip_hdr_len << MVPP2_TXD_IP_HLEN_SHIFT); 2567 command |= MVPP2_TXD_IP_CSUM_DISABLE; 2568 2569 if (l3_proto == htons(ETH_P_IP)) { 2570 command &= ~MVPP2_TXD_IP_CSUM_DISABLE; /* enable IPv4 csum */ 2571 command &= ~MVPP2_TXD_L3_IP6; /* enable IPv4 */ 2572 } else { 2573 command |= MVPP2_TXD_L3_IP6; /* enable IPv6 */ 2574 } 2575 2576 if (l4_proto == IPPROTO_TCP) { 2577 command &= ~MVPP2_TXD_L4_UDP; /* enable TCP */ 2578 command &= ~MVPP2_TXD_L4_CSUM_FRAG; /* generate L4 csum */ 2579 } else if (l4_proto == IPPROTO_UDP) { 2580 command |= MVPP2_TXD_L4_UDP; /* enable UDP */ 2581 command &= ~MVPP2_TXD_L4_CSUM_FRAG; /* generate L4 csum */ 2582 } else { 2583 command |= MVPP2_TXD_L4_CSUM_NOT; 2584 } 2585 2586 return command; 2587 } 2588 2589 /* Get number of sent descriptors and decrement counter. 2590 * The number of sent descriptors is returned. 2591 * Per-thread access 2592 * 2593 * Called only from mvpp2_txq_done(), called from mvpp2_tx() 2594 * (migration disabled) and from the TX completion tasklet (migration 2595 * disabled) so using smp_processor_id() is OK. 2596 */ 2597 static inline int mvpp2_txq_sent_desc_proc(struct mvpp2_port *port, 2598 struct mvpp2_tx_queue *txq) 2599 { 2600 u32 val; 2601 2602 /* Reading status reg resets transmitted descriptor counter */ 2603 val = mvpp2_thread_read_relaxed(port->priv, 2604 mvpp2_cpu_to_thread(port->priv, smp_processor_id()), 2605 MVPP2_TXQ_SENT_REG(txq->id)); 2606 2607 return (val & MVPP2_TRANSMITTED_COUNT_MASK) >> 2608 MVPP2_TRANSMITTED_COUNT_OFFSET; 2609 } 2610 2611 /* Called through on_each_cpu(), so runs on all CPUs, with migration 2612 * disabled, therefore using smp_processor_id() is OK. 2613 */ 2614 static void mvpp2_txq_sent_counter_clear(void *arg) 2615 { 2616 struct mvpp2_port *port = arg; 2617 int queue; 2618 2619 /* If the thread isn't used, don't do anything */ 2620 if (smp_processor_id() >= port->priv->nthreads) 2621 return; 2622 2623 for (queue = 0; queue < port->ntxqs; queue++) { 2624 int id = port->txqs[queue]->id; 2625 2626 mvpp2_thread_read(port->priv, 2627 mvpp2_cpu_to_thread(port->priv, smp_processor_id()), 2628 MVPP2_TXQ_SENT_REG(id)); 2629 } 2630 } 2631 2632 /* Set max sizes for Tx queues */ 2633 static void mvpp2_txp_max_tx_size_set(struct mvpp2_port *port) 2634 { 2635 u32 val, size, mtu; 2636 int txq, tx_port_num; 2637 2638 mtu = port->pkt_size * 8; 2639 if (mtu > MVPP2_TXP_MTU_MAX) 2640 mtu = MVPP2_TXP_MTU_MAX; 2641 2642 /* WA for wrong Token bucket update: Set MTU value = 3*real MTU value */ 2643 mtu = 3 * mtu; 2644 2645 /* Indirect access to registers */ 2646 tx_port_num = mvpp2_egress_port(port); 2647 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num); 2648 2649 /* Set MTU */ 2650 val = mvpp2_read(port->priv, MVPP2_TXP_SCHED_MTU_REG); 2651 val &= ~MVPP2_TXP_MTU_MAX; 2652 val |= mtu; 2653 mvpp2_write(port->priv, MVPP2_TXP_SCHED_MTU_REG, val); 2654 2655 /* TXP token size and all TXQs token size must be larger that MTU */ 2656 val = mvpp2_read(port->priv, MVPP2_TXP_SCHED_TOKEN_SIZE_REG); 2657 size = val & MVPP2_TXP_TOKEN_SIZE_MAX; 2658 if (size < mtu) { 2659 size = mtu; 2660 val &= ~MVPP2_TXP_TOKEN_SIZE_MAX; 2661 val |= size; 2662 mvpp2_write(port->priv, MVPP2_TXP_SCHED_TOKEN_SIZE_REG, val); 2663 } 2664 2665 for (txq = 0; txq < port->ntxqs; txq++) { 2666 val = mvpp2_read(port->priv, 2667 MVPP2_TXQ_SCHED_TOKEN_SIZE_REG(txq)); 2668 size = val & MVPP2_TXQ_TOKEN_SIZE_MAX; 2669 2670 if (size < mtu) { 2671 size = mtu; 2672 val &= ~MVPP2_TXQ_TOKEN_SIZE_MAX; 2673 val |= size; 2674 mvpp2_write(port->priv, 2675 MVPP2_TXQ_SCHED_TOKEN_SIZE_REG(txq), 2676 val); 2677 } 2678 } 2679 } 2680 2681 /* Set the number of non-occupied descriptors threshold */ 2682 static void mvpp2_set_rxq_free_tresh(struct mvpp2_port *port, 2683 struct mvpp2_rx_queue *rxq) 2684 { 2685 u32 val; 2686 2687 mvpp2_write(port->priv, MVPP2_RXQ_NUM_REG, rxq->id); 2688 2689 val = mvpp2_read(port->priv, MVPP2_RXQ_THRESH_REG); 2690 val &= ~MVPP2_RXQ_NON_OCCUPIED_MASK; 2691 val |= MSS_THRESHOLD_STOP << MVPP2_RXQ_NON_OCCUPIED_OFFSET; 2692 mvpp2_write(port->priv, MVPP2_RXQ_THRESH_REG, val); 2693 } 2694 2695 /* Set the number of packets that will be received before Rx interrupt 2696 * will be generated by HW. 2697 */ 2698 static void mvpp2_rx_pkts_coal_set(struct mvpp2_port *port, 2699 struct mvpp2_rx_queue *rxq) 2700 { 2701 unsigned int thread = mvpp2_cpu_to_thread(port->priv, get_cpu()); 2702 2703 if (rxq->pkts_coal > MVPP2_OCCUPIED_THRESH_MASK) 2704 rxq->pkts_coal = MVPP2_OCCUPIED_THRESH_MASK; 2705 2706 mvpp2_thread_write(port->priv, thread, MVPP2_RXQ_NUM_REG, rxq->id); 2707 mvpp2_thread_write(port->priv, thread, MVPP2_RXQ_THRESH_REG, 2708 rxq->pkts_coal); 2709 2710 put_cpu(); 2711 } 2712 2713 /* For some reason in the LSP this is done on each CPU. Why ? */ 2714 static void mvpp2_tx_pkts_coal_set(struct mvpp2_port *port, 2715 struct mvpp2_tx_queue *txq) 2716 { 2717 unsigned int thread; 2718 u32 val; 2719 2720 if (txq->done_pkts_coal > MVPP2_TXQ_THRESH_MASK) 2721 txq->done_pkts_coal = MVPP2_TXQ_THRESH_MASK; 2722 2723 val = (txq->done_pkts_coal << MVPP2_TXQ_THRESH_OFFSET); 2724 /* PKT-coalescing registers are per-queue + per-thread */ 2725 for (thread = 0; thread < MVPP2_MAX_THREADS; thread++) { 2726 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_NUM_REG, txq->id); 2727 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_THRESH_REG, val); 2728 } 2729 } 2730 2731 static u32 mvpp2_usec_to_cycles(u32 usec, unsigned long clk_hz) 2732 { 2733 u64 tmp = (u64)clk_hz * usec; 2734 2735 do_div(tmp, USEC_PER_SEC); 2736 2737 return tmp > U32_MAX ? U32_MAX : tmp; 2738 } 2739 2740 static u32 mvpp2_cycles_to_usec(u32 cycles, unsigned long clk_hz) 2741 { 2742 u64 tmp = (u64)cycles * USEC_PER_SEC; 2743 2744 do_div(tmp, clk_hz); 2745 2746 return tmp > U32_MAX ? U32_MAX : tmp; 2747 } 2748 2749 /* Set the time delay in usec before Rx interrupt */ 2750 static void mvpp2_rx_time_coal_set(struct mvpp2_port *port, 2751 struct mvpp2_rx_queue *rxq) 2752 { 2753 unsigned long freq = port->priv->tclk; 2754 u32 val = mvpp2_usec_to_cycles(rxq->time_coal, freq); 2755 2756 if (val > MVPP2_MAX_ISR_RX_THRESHOLD) { 2757 rxq->time_coal = 2758 mvpp2_cycles_to_usec(MVPP2_MAX_ISR_RX_THRESHOLD, freq); 2759 2760 /* re-evaluate to get actual register value */ 2761 val = mvpp2_usec_to_cycles(rxq->time_coal, freq); 2762 } 2763 2764 mvpp2_write(port->priv, MVPP2_ISR_RX_THRESHOLD_REG(rxq->id), val); 2765 } 2766 2767 static void mvpp2_tx_time_coal_set(struct mvpp2_port *port) 2768 { 2769 unsigned long freq = port->priv->tclk; 2770 u32 val = mvpp2_usec_to_cycles(port->tx_time_coal, freq); 2771 2772 if (val > MVPP2_MAX_ISR_TX_THRESHOLD) { 2773 port->tx_time_coal = 2774 mvpp2_cycles_to_usec(MVPP2_MAX_ISR_TX_THRESHOLD, freq); 2775 2776 /* re-evaluate to get actual register value */ 2777 val = mvpp2_usec_to_cycles(port->tx_time_coal, freq); 2778 } 2779 2780 mvpp2_write(port->priv, MVPP2_ISR_TX_THRESHOLD_REG(port->id), val); 2781 } 2782 2783 /* Free Tx queue skbuffs */ 2784 static void mvpp2_txq_bufs_free(struct mvpp2_port *port, 2785 struct mvpp2_tx_queue *txq, 2786 struct mvpp2_txq_pcpu *txq_pcpu, int num) 2787 { 2788 struct xdp_frame_bulk bq; 2789 int i; 2790 2791 xdp_frame_bulk_init(&bq); 2792 2793 rcu_read_lock(); /* need for xdp_return_frame_bulk */ 2794 2795 for (i = 0; i < num; i++) { 2796 struct mvpp2_txq_pcpu_buf *tx_buf = 2797 txq_pcpu->buffs + txq_pcpu->txq_get_index; 2798 2799 if (!IS_TSO_HEADER(txq_pcpu, tx_buf->dma) && 2800 tx_buf->type != MVPP2_TYPE_XDP_TX) 2801 dma_unmap_single(port->dev->dev.parent, tx_buf->dma, 2802 tx_buf->size, DMA_TO_DEVICE); 2803 if (tx_buf->type == MVPP2_TYPE_SKB && tx_buf->skb) 2804 dev_kfree_skb_any(tx_buf->skb); 2805 else if (tx_buf->type == MVPP2_TYPE_XDP_TX || 2806 tx_buf->type == MVPP2_TYPE_XDP_NDO) 2807 xdp_return_frame_bulk(tx_buf->xdpf, &bq); 2808 2809 mvpp2_txq_inc_get(txq_pcpu); 2810 } 2811 xdp_flush_frame_bulk(&bq); 2812 2813 rcu_read_unlock(); 2814 } 2815 2816 static inline struct mvpp2_rx_queue *mvpp2_get_rx_queue(struct mvpp2_port *port, 2817 u32 cause) 2818 { 2819 int queue = fls(cause) - 1; 2820 2821 return port->rxqs[queue]; 2822 } 2823 2824 static inline struct mvpp2_tx_queue *mvpp2_get_tx_queue(struct mvpp2_port *port, 2825 u32 cause) 2826 { 2827 int queue = fls(cause) - 1; 2828 2829 return port->txqs[queue]; 2830 } 2831 2832 /* Handle end of transmission */ 2833 static void mvpp2_txq_done(struct mvpp2_port *port, struct mvpp2_tx_queue *txq, 2834 struct mvpp2_txq_pcpu *txq_pcpu) 2835 { 2836 struct netdev_queue *nq = netdev_get_tx_queue(port->dev, txq->log_id); 2837 int tx_done; 2838 2839 if (txq_pcpu->thread != mvpp2_cpu_to_thread(port->priv, smp_processor_id())) 2840 netdev_err(port->dev, "wrong cpu on the end of Tx processing\n"); 2841 2842 tx_done = mvpp2_txq_sent_desc_proc(port, txq); 2843 if (!tx_done) 2844 return; 2845 mvpp2_txq_bufs_free(port, txq, txq_pcpu, tx_done); 2846 2847 txq_pcpu->count -= tx_done; 2848 2849 if (netif_tx_queue_stopped(nq)) 2850 if (txq_pcpu->count <= txq_pcpu->wake_threshold) 2851 netif_tx_wake_queue(nq); 2852 } 2853 2854 static unsigned int mvpp2_tx_done(struct mvpp2_port *port, u32 cause, 2855 unsigned int thread) 2856 { 2857 struct mvpp2_tx_queue *txq; 2858 struct mvpp2_txq_pcpu *txq_pcpu; 2859 unsigned int tx_todo = 0; 2860 2861 while (cause) { 2862 txq = mvpp2_get_tx_queue(port, cause); 2863 if (!txq) 2864 break; 2865 2866 txq_pcpu = per_cpu_ptr(txq->pcpu, thread); 2867 2868 if (txq_pcpu->count) { 2869 mvpp2_txq_done(port, txq, txq_pcpu); 2870 tx_todo += txq_pcpu->count; 2871 } 2872 2873 cause &= ~(1 << txq->log_id); 2874 } 2875 return tx_todo; 2876 } 2877 2878 /* Rx/Tx queue initialization/cleanup methods */ 2879 2880 /* Allocate and initialize descriptors for aggr TXQ */ 2881 static int mvpp2_aggr_txq_init(struct platform_device *pdev, 2882 struct mvpp2_tx_queue *aggr_txq, 2883 unsigned int thread, struct mvpp2 *priv) 2884 { 2885 u32 txq_dma; 2886 2887 /* Allocate memory for TX descriptors */ 2888 aggr_txq->descs = dma_alloc_coherent(&pdev->dev, 2889 MVPP2_AGGR_TXQ_SIZE * MVPP2_DESC_ALIGNED_SIZE, 2890 &aggr_txq->descs_dma, GFP_KERNEL); 2891 if (!aggr_txq->descs) 2892 return -ENOMEM; 2893 2894 aggr_txq->last_desc = MVPP2_AGGR_TXQ_SIZE - 1; 2895 2896 /* Aggr TXQ no reset WA */ 2897 aggr_txq->next_desc_to_proc = mvpp2_read(priv, 2898 MVPP2_AGGR_TXQ_INDEX_REG(thread)); 2899 2900 /* Set Tx descriptors queue starting address indirect 2901 * access 2902 */ 2903 if (priv->hw_version == MVPP21) 2904 txq_dma = aggr_txq->descs_dma; 2905 else 2906 txq_dma = aggr_txq->descs_dma >> 2907 MVPP22_AGGR_TXQ_DESC_ADDR_OFFS; 2908 2909 mvpp2_write(priv, MVPP2_AGGR_TXQ_DESC_ADDR_REG(thread), txq_dma); 2910 mvpp2_write(priv, MVPP2_AGGR_TXQ_DESC_SIZE_REG(thread), 2911 MVPP2_AGGR_TXQ_SIZE); 2912 2913 return 0; 2914 } 2915 2916 /* Create a specified Rx queue */ 2917 static int mvpp2_rxq_init(struct mvpp2_port *port, 2918 struct mvpp2_rx_queue *rxq) 2919 { 2920 struct mvpp2 *priv = port->priv; 2921 unsigned int thread; 2922 u32 rxq_dma; 2923 int err; 2924 2925 rxq->size = port->rx_ring_size; 2926 2927 /* Allocate memory for RX descriptors */ 2928 rxq->descs = dma_alloc_coherent(port->dev->dev.parent, 2929 rxq->size * MVPP2_DESC_ALIGNED_SIZE, 2930 &rxq->descs_dma, GFP_KERNEL); 2931 if (!rxq->descs) 2932 return -ENOMEM; 2933 2934 rxq->last_desc = rxq->size - 1; 2935 2936 /* Zero occupied and non-occupied counters - direct access */ 2937 mvpp2_write(port->priv, MVPP2_RXQ_STATUS_REG(rxq->id), 0); 2938 2939 /* Set Rx descriptors queue starting address - indirect access */ 2940 thread = mvpp2_cpu_to_thread(port->priv, get_cpu()); 2941 mvpp2_thread_write(port->priv, thread, MVPP2_RXQ_NUM_REG, rxq->id); 2942 if (port->priv->hw_version == MVPP21) 2943 rxq_dma = rxq->descs_dma; 2944 else 2945 rxq_dma = rxq->descs_dma >> MVPP22_DESC_ADDR_OFFS; 2946 mvpp2_thread_write(port->priv, thread, MVPP2_RXQ_DESC_ADDR_REG, rxq_dma); 2947 mvpp2_thread_write(port->priv, thread, MVPP2_RXQ_DESC_SIZE_REG, rxq->size); 2948 mvpp2_thread_write(port->priv, thread, MVPP2_RXQ_INDEX_REG, 0); 2949 put_cpu(); 2950 2951 /* Set Offset */ 2952 mvpp2_rxq_offset_set(port, rxq->id, MVPP2_SKB_HEADROOM); 2953 2954 /* Set coalescing pkts and time */ 2955 mvpp2_rx_pkts_coal_set(port, rxq); 2956 mvpp2_rx_time_coal_set(port, rxq); 2957 2958 /* Set the number of non occupied descriptors threshold */ 2959 mvpp2_set_rxq_free_tresh(port, rxq); 2960 2961 /* Add number of descriptors ready for receiving packets */ 2962 mvpp2_rxq_status_update(port, rxq->id, 0, rxq->size); 2963 2964 if (priv->percpu_pools) { 2965 err = xdp_rxq_info_reg(&rxq->xdp_rxq_short, port->dev, rxq->logic_rxq, 0); 2966 if (err < 0) 2967 goto err_free_dma; 2968 2969 err = xdp_rxq_info_reg(&rxq->xdp_rxq_long, port->dev, rxq->logic_rxq, 0); 2970 if (err < 0) 2971 goto err_unregister_rxq_short; 2972 2973 /* Every RXQ has a pool for short and another for long packets */ 2974 err = xdp_rxq_info_reg_mem_model(&rxq->xdp_rxq_short, 2975 MEM_TYPE_PAGE_POOL, 2976 priv->page_pool[rxq->logic_rxq]); 2977 if (err < 0) 2978 goto err_unregister_rxq_long; 2979 2980 err = xdp_rxq_info_reg_mem_model(&rxq->xdp_rxq_long, 2981 MEM_TYPE_PAGE_POOL, 2982 priv->page_pool[rxq->logic_rxq + 2983 port->nrxqs]); 2984 if (err < 0) 2985 goto err_unregister_mem_rxq_short; 2986 } 2987 2988 return 0; 2989 2990 err_unregister_mem_rxq_short: 2991 xdp_rxq_info_unreg_mem_model(&rxq->xdp_rxq_short); 2992 err_unregister_rxq_long: 2993 xdp_rxq_info_unreg(&rxq->xdp_rxq_long); 2994 err_unregister_rxq_short: 2995 xdp_rxq_info_unreg(&rxq->xdp_rxq_short); 2996 err_free_dma: 2997 dma_free_coherent(port->dev->dev.parent, 2998 rxq->size * MVPP2_DESC_ALIGNED_SIZE, 2999 rxq->descs, rxq->descs_dma); 3000 return err; 3001 } 3002 3003 /* Push packets received by the RXQ to BM pool */ 3004 static void mvpp2_rxq_drop_pkts(struct mvpp2_port *port, 3005 struct mvpp2_rx_queue *rxq) 3006 { 3007 int rx_received, i; 3008 3009 rx_received = mvpp2_rxq_received(port, rxq->id); 3010 if (!rx_received) 3011 return; 3012 3013 for (i = 0; i < rx_received; i++) { 3014 struct mvpp2_rx_desc *rx_desc = mvpp2_rxq_next_desc_get(rxq); 3015 u32 status = mvpp2_rxdesc_status_get(port, rx_desc); 3016 int pool; 3017 3018 pool = (status & MVPP2_RXD_BM_POOL_ID_MASK) >> 3019 MVPP2_RXD_BM_POOL_ID_OFFS; 3020 3021 mvpp2_bm_pool_put(port, pool, 3022 mvpp2_rxdesc_dma_addr_get(port, rx_desc), 3023 mvpp2_rxdesc_cookie_get(port, rx_desc)); 3024 } 3025 mvpp2_rxq_status_update(port, rxq->id, rx_received, rx_received); 3026 } 3027 3028 /* Cleanup Rx queue */ 3029 static void mvpp2_rxq_deinit(struct mvpp2_port *port, 3030 struct mvpp2_rx_queue *rxq) 3031 { 3032 unsigned int thread; 3033 3034 if (xdp_rxq_info_is_reg(&rxq->xdp_rxq_short)) 3035 xdp_rxq_info_unreg(&rxq->xdp_rxq_short); 3036 3037 if (xdp_rxq_info_is_reg(&rxq->xdp_rxq_long)) 3038 xdp_rxq_info_unreg(&rxq->xdp_rxq_long); 3039 3040 mvpp2_rxq_drop_pkts(port, rxq); 3041 3042 if (rxq->descs) 3043 dma_free_coherent(port->dev->dev.parent, 3044 rxq->size * MVPP2_DESC_ALIGNED_SIZE, 3045 rxq->descs, 3046 rxq->descs_dma); 3047 3048 rxq->descs = NULL; 3049 rxq->last_desc = 0; 3050 rxq->next_desc_to_proc = 0; 3051 rxq->descs_dma = 0; 3052 3053 /* Clear Rx descriptors queue starting address and size; 3054 * free descriptor number 3055 */ 3056 mvpp2_write(port->priv, MVPP2_RXQ_STATUS_REG(rxq->id), 0); 3057 thread = mvpp2_cpu_to_thread(port->priv, get_cpu()); 3058 mvpp2_thread_write(port->priv, thread, MVPP2_RXQ_NUM_REG, rxq->id); 3059 mvpp2_thread_write(port->priv, thread, MVPP2_RXQ_DESC_ADDR_REG, 0); 3060 mvpp2_thread_write(port->priv, thread, MVPP2_RXQ_DESC_SIZE_REG, 0); 3061 put_cpu(); 3062 } 3063 3064 /* Create and initialize a Tx queue */ 3065 static int mvpp2_txq_init(struct mvpp2_port *port, 3066 struct mvpp2_tx_queue *txq) 3067 { 3068 u32 val; 3069 unsigned int thread; 3070 int desc, desc_per_txq, tx_port_num; 3071 struct mvpp2_txq_pcpu *txq_pcpu; 3072 3073 txq->size = port->tx_ring_size; 3074 3075 /* Allocate memory for Tx descriptors */ 3076 txq->descs = dma_alloc_coherent(port->dev->dev.parent, 3077 txq->size * MVPP2_DESC_ALIGNED_SIZE, 3078 &txq->descs_dma, GFP_KERNEL); 3079 if (!txq->descs) 3080 return -ENOMEM; 3081 3082 txq->last_desc = txq->size - 1; 3083 3084 /* Set Tx descriptors queue starting address - indirect access */ 3085 thread = mvpp2_cpu_to_thread(port->priv, get_cpu()); 3086 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_NUM_REG, txq->id); 3087 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_DESC_ADDR_REG, 3088 txq->descs_dma); 3089 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_DESC_SIZE_REG, 3090 txq->size & MVPP2_TXQ_DESC_SIZE_MASK); 3091 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_INDEX_REG, 0); 3092 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_RSVD_CLR_REG, 3093 txq->id << MVPP2_TXQ_RSVD_CLR_OFFSET); 3094 val = mvpp2_thread_read(port->priv, thread, MVPP2_TXQ_PENDING_REG); 3095 val &= ~MVPP2_TXQ_PENDING_MASK; 3096 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_PENDING_REG, val); 3097 3098 /* Calculate base address in prefetch buffer. We reserve 16 descriptors 3099 * for each existing TXQ. 3100 * TCONTS for PON port must be continuous from 0 to MVPP2_MAX_TCONT 3101 * GBE ports assumed to be continuous from 0 to MVPP2_MAX_PORTS 3102 */ 3103 desc_per_txq = 16; 3104 desc = (port->id * MVPP2_MAX_TXQ * desc_per_txq) + 3105 (txq->log_id * desc_per_txq); 3106 3107 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_PREF_BUF_REG, 3108 MVPP2_PREF_BUF_PTR(desc) | MVPP2_PREF_BUF_SIZE_16 | 3109 MVPP2_PREF_BUF_THRESH(desc_per_txq / 2)); 3110 put_cpu(); 3111 3112 /* WRR / EJP configuration - indirect access */ 3113 tx_port_num = mvpp2_egress_port(port); 3114 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num); 3115 3116 val = mvpp2_read(port->priv, MVPP2_TXQ_SCHED_REFILL_REG(txq->log_id)); 3117 val &= ~MVPP2_TXQ_REFILL_PERIOD_ALL_MASK; 3118 val |= MVPP2_TXQ_REFILL_PERIOD_MASK(1); 3119 val |= MVPP2_TXQ_REFILL_TOKENS_ALL_MASK; 3120 mvpp2_write(port->priv, MVPP2_TXQ_SCHED_REFILL_REG(txq->log_id), val); 3121 3122 val = MVPP2_TXQ_TOKEN_SIZE_MAX; 3123 mvpp2_write(port->priv, MVPP2_TXQ_SCHED_TOKEN_SIZE_REG(txq->log_id), 3124 val); 3125 3126 for (thread = 0; thread < port->priv->nthreads; thread++) { 3127 txq_pcpu = per_cpu_ptr(txq->pcpu, thread); 3128 txq_pcpu->size = txq->size; 3129 txq_pcpu->buffs = kmalloc_array(txq_pcpu->size, 3130 sizeof(*txq_pcpu->buffs), 3131 GFP_KERNEL); 3132 if (!txq_pcpu->buffs) 3133 return -ENOMEM; 3134 3135 txq_pcpu->count = 0; 3136 txq_pcpu->reserved_num = 0; 3137 txq_pcpu->txq_put_index = 0; 3138 txq_pcpu->txq_get_index = 0; 3139 txq_pcpu->tso_headers = NULL; 3140 3141 txq_pcpu->stop_threshold = txq->size - MVPP2_MAX_SKB_DESCS; 3142 txq_pcpu->wake_threshold = txq_pcpu->stop_threshold / 2; 3143 3144 txq_pcpu->tso_headers = 3145 dma_alloc_coherent(port->dev->dev.parent, 3146 txq_pcpu->size * TSO_HEADER_SIZE, 3147 &txq_pcpu->tso_headers_dma, 3148 GFP_KERNEL); 3149 if (!txq_pcpu->tso_headers) 3150 return -ENOMEM; 3151 } 3152 3153 return 0; 3154 } 3155 3156 /* Free allocated TXQ resources */ 3157 static void mvpp2_txq_deinit(struct mvpp2_port *port, 3158 struct mvpp2_tx_queue *txq) 3159 { 3160 struct mvpp2_txq_pcpu *txq_pcpu; 3161 unsigned int thread; 3162 3163 for (thread = 0; thread < port->priv->nthreads; thread++) { 3164 txq_pcpu = per_cpu_ptr(txq->pcpu, thread); 3165 kfree(txq_pcpu->buffs); 3166 3167 if (txq_pcpu->tso_headers) 3168 dma_free_coherent(port->dev->dev.parent, 3169 txq_pcpu->size * TSO_HEADER_SIZE, 3170 txq_pcpu->tso_headers, 3171 txq_pcpu->tso_headers_dma); 3172 3173 txq_pcpu->tso_headers = NULL; 3174 } 3175 3176 if (txq->descs) 3177 dma_free_coherent(port->dev->dev.parent, 3178 txq->size * MVPP2_DESC_ALIGNED_SIZE, 3179 txq->descs, txq->descs_dma); 3180 3181 txq->descs = NULL; 3182 txq->last_desc = 0; 3183 txq->next_desc_to_proc = 0; 3184 txq->descs_dma = 0; 3185 3186 /* Set minimum bandwidth for disabled TXQs */ 3187 mvpp2_write(port->priv, MVPP2_TXQ_SCHED_TOKEN_CNTR_REG(txq->log_id), 0); 3188 3189 /* Set Tx descriptors queue starting address and size */ 3190 thread = mvpp2_cpu_to_thread(port->priv, get_cpu()); 3191 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_NUM_REG, txq->id); 3192 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_DESC_ADDR_REG, 0); 3193 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_DESC_SIZE_REG, 0); 3194 put_cpu(); 3195 } 3196 3197 /* Cleanup Tx ports */ 3198 static void mvpp2_txq_clean(struct mvpp2_port *port, struct mvpp2_tx_queue *txq) 3199 { 3200 struct mvpp2_txq_pcpu *txq_pcpu; 3201 int delay, pending; 3202 unsigned int thread = mvpp2_cpu_to_thread(port->priv, get_cpu()); 3203 u32 val; 3204 3205 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_NUM_REG, txq->id); 3206 val = mvpp2_thread_read(port->priv, thread, MVPP2_TXQ_PREF_BUF_REG); 3207 val |= MVPP2_TXQ_DRAIN_EN_MASK; 3208 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_PREF_BUF_REG, val); 3209 3210 /* The napi queue has been stopped so wait for all packets 3211 * to be transmitted. 3212 */ 3213 delay = 0; 3214 do { 3215 if (delay >= MVPP2_TX_PENDING_TIMEOUT_MSEC) { 3216 netdev_warn(port->dev, 3217 "port %d: cleaning queue %d timed out\n", 3218 port->id, txq->log_id); 3219 break; 3220 } 3221 mdelay(1); 3222 delay++; 3223 3224 pending = mvpp2_thread_read(port->priv, thread, 3225 MVPP2_TXQ_PENDING_REG); 3226 pending &= MVPP2_TXQ_PENDING_MASK; 3227 } while (pending); 3228 3229 val &= ~MVPP2_TXQ_DRAIN_EN_MASK; 3230 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_PREF_BUF_REG, val); 3231 put_cpu(); 3232 3233 for (thread = 0; thread < port->priv->nthreads; thread++) { 3234 txq_pcpu = per_cpu_ptr(txq->pcpu, thread); 3235 3236 /* Release all packets */ 3237 mvpp2_txq_bufs_free(port, txq, txq_pcpu, txq_pcpu->count); 3238 3239 /* Reset queue */ 3240 txq_pcpu->count = 0; 3241 txq_pcpu->txq_put_index = 0; 3242 txq_pcpu->txq_get_index = 0; 3243 } 3244 } 3245 3246 /* Cleanup all Tx queues */ 3247 static void mvpp2_cleanup_txqs(struct mvpp2_port *port) 3248 { 3249 struct mvpp2_tx_queue *txq; 3250 int queue; 3251 u32 val; 3252 3253 val = mvpp2_read(port->priv, MVPP2_TX_PORT_FLUSH_REG); 3254 3255 /* Reset Tx ports and delete Tx queues */ 3256 val |= MVPP2_TX_PORT_FLUSH_MASK(port->id); 3257 mvpp2_write(port->priv, MVPP2_TX_PORT_FLUSH_REG, val); 3258 3259 for (queue = 0; queue < port->ntxqs; queue++) { 3260 txq = port->txqs[queue]; 3261 mvpp2_txq_clean(port, txq); 3262 mvpp2_txq_deinit(port, txq); 3263 } 3264 3265 on_each_cpu(mvpp2_txq_sent_counter_clear, port, 1); 3266 3267 val &= ~MVPP2_TX_PORT_FLUSH_MASK(port->id); 3268 mvpp2_write(port->priv, MVPP2_TX_PORT_FLUSH_REG, val); 3269 } 3270 3271 /* Cleanup all Rx queues */ 3272 static void mvpp2_cleanup_rxqs(struct mvpp2_port *port) 3273 { 3274 int queue; 3275 3276 for (queue = 0; queue < port->nrxqs; queue++) 3277 mvpp2_rxq_deinit(port, port->rxqs[queue]); 3278 3279 if (port->tx_fc) 3280 mvpp2_rxq_disable_fc(port); 3281 } 3282 3283 /* Init all Rx queues for port */ 3284 static int mvpp2_setup_rxqs(struct mvpp2_port *port) 3285 { 3286 int queue, err; 3287 3288 for (queue = 0; queue < port->nrxqs; queue++) { 3289 err = mvpp2_rxq_init(port, port->rxqs[queue]); 3290 if (err) 3291 goto err_cleanup; 3292 } 3293 3294 if (port->tx_fc) 3295 mvpp2_rxq_enable_fc(port); 3296 3297 return 0; 3298 3299 err_cleanup: 3300 mvpp2_cleanup_rxqs(port); 3301 return err; 3302 } 3303 3304 /* Init all tx queues for port */ 3305 static int mvpp2_setup_txqs(struct mvpp2_port *port) 3306 { 3307 struct mvpp2_tx_queue *txq; 3308 int queue, err; 3309 3310 for (queue = 0; queue < port->ntxqs; queue++) { 3311 txq = port->txqs[queue]; 3312 err = mvpp2_txq_init(port, txq); 3313 if (err) 3314 goto err_cleanup; 3315 3316 /* Assign this queue to a CPU */ 3317 if (queue < num_possible_cpus()) 3318 netif_set_xps_queue(port->dev, cpumask_of(queue), queue); 3319 } 3320 3321 if (port->has_tx_irqs) { 3322 mvpp2_tx_time_coal_set(port); 3323 for (queue = 0; queue < port->ntxqs; queue++) { 3324 txq = port->txqs[queue]; 3325 mvpp2_tx_pkts_coal_set(port, txq); 3326 } 3327 } 3328 3329 on_each_cpu(mvpp2_txq_sent_counter_clear, port, 1); 3330 return 0; 3331 3332 err_cleanup: 3333 mvpp2_cleanup_txqs(port); 3334 return err; 3335 } 3336 3337 /* The callback for per-port interrupt */ 3338 static irqreturn_t mvpp2_isr(int irq, void *dev_id) 3339 { 3340 struct mvpp2_queue_vector *qv = dev_id; 3341 3342 mvpp2_qvec_interrupt_disable(qv); 3343 3344 napi_schedule(&qv->napi); 3345 3346 return IRQ_HANDLED; 3347 } 3348 3349 static void mvpp2_isr_handle_ptp_queue(struct mvpp2_port *port, int nq) 3350 { 3351 struct skb_shared_hwtstamps shhwtstamps; 3352 struct mvpp2_hwtstamp_queue *queue; 3353 struct sk_buff *skb; 3354 void __iomem *ptp_q; 3355 unsigned int id; 3356 u32 r0, r1, r2; 3357 3358 ptp_q = port->priv->iface_base + MVPP22_PTP_BASE(port->gop_id); 3359 if (nq) 3360 ptp_q += MVPP22_PTP_TX_Q1_R0 - MVPP22_PTP_TX_Q0_R0; 3361 3362 queue = &port->tx_hwtstamp_queue[nq]; 3363 3364 while (1) { 3365 r0 = readl_relaxed(ptp_q + MVPP22_PTP_TX_Q0_R0) & 0xffff; 3366 if (!r0) 3367 break; 3368 3369 r1 = readl_relaxed(ptp_q + MVPP22_PTP_TX_Q0_R1) & 0xffff; 3370 r2 = readl_relaxed(ptp_q + MVPP22_PTP_TX_Q0_R2) & 0xffff; 3371 3372 id = (r0 >> 1) & 31; 3373 3374 skb = queue->skb[id]; 3375 queue->skb[id] = NULL; 3376 if (skb) { 3377 u32 ts = r2 << 19 | r1 << 3 | r0 >> 13; 3378 3379 mvpp22_tai_tstamp(port->priv->tai, ts, &shhwtstamps); 3380 skb_tstamp_tx(skb, &shhwtstamps); 3381 dev_kfree_skb_any(skb); 3382 } 3383 } 3384 } 3385 3386 static void mvpp2_isr_handle_ptp(struct mvpp2_port *port) 3387 { 3388 void __iomem *ptp; 3389 u32 val; 3390 3391 ptp = port->priv->iface_base + MVPP22_PTP_BASE(port->gop_id); 3392 val = readl(ptp + MVPP22_PTP_INT_CAUSE); 3393 if (val & MVPP22_PTP_INT_CAUSE_QUEUE0) 3394 mvpp2_isr_handle_ptp_queue(port, 0); 3395 if (val & MVPP22_PTP_INT_CAUSE_QUEUE1) 3396 mvpp2_isr_handle_ptp_queue(port, 1); 3397 } 3398 3399 static void mvpp2_isr_handle_link(struct mvpp2_port *port, bool link) 3400 { 3401 struct net_device *dev = port->dev; 3402 3403 if (port->phylink) { 3404 phylink_mac_change(port->phylink, link); 3405 return; 3406 } 3407 3408 if (!netif_running(dev)) 3409 return; 3410 3411 if (link) { 3412 mvpp2_interrupts_enable(port); 3413 3414 mvpp2_egress_enable(port); 3415 mvpp2_ingress_enable(port); 3416 netif_carrier_on(dev); 3417 netif_tx_wake_all_queues(dev); 3418 } else { 3419 netif_tx_stop_all_queues(dev); 3420 netif_carrier_off(dev); 3421 mvpp2_ingress_disable(port); 3422 mvpp2_egress_disable(port); 3423 3424 mvpp2_interrupts_disable(port); 3425 } 3426 } 3427 3428 static void mvpp2_isr_handle_xlg(struct mvpp2_port *port) 3429 { 3430 bool link; 3431 u32 val; 3432 3433 val = readl(port->base + MVPP22_XLG_INT_STAT); 3434 if (val & MVPP22_XLG_INT_STAT_LINK) { 3435 val = readl(port->base + MVPP22_XLG_STATUS); 3436 link = (val & MVPP22_XLG_STATUS_LINK_UP); 3437 mvpp2_isr_handle_link(port, link); 3438 } 3439 } 3440 3441 static void mvpp2_isr_handle_gmac_internal(struct mvpp2_port *port) 3442 { 3443 bool link; 3444 u32 val; 3445 3446 if (phy_interface_mode_is_rgmii(port->phy_interface) || 3447 phy_interface_mode_is_8023z(port->phy_interface) || 3448 port->phy_interface == PHY_INTERFACE_MODE_SGMII) { 3449 val = readl(port->base + MVPP22_GMAC_INT_STAT); 3450 if (val & MVPP22_GMAC_INT_STAT_LINK) { 3451 val = readl(port->base + MVPP2_GMAC_STATUS0); 3452 link = (val & MVPP2_GMAC_STATUS0_LINK_UP); 3453 mvpp2_isr_handle_link(port, link); 3454 } 3455 } 3456 } 3457 3458 /* Per-port interrupt for link status changes */ 3459 static irqreturn_t mvpp2_port_isr(int irq, void *dev_id) 3460 { 3461 struct mvpp2_port *port = (struct mvpp2_port *)dev_id; 3462 u32 val; 3463 3464 mvpp22_gop_mask_irq(port); 3465 3466 if (mvpp2_port_supports_xlg(port) && 3467 mvpp2_is_xlg(port->phy_interface)) { 3468 /* Check the external status register */ 3469 val = readl(port->base + MVPP22_XLG_EXT_INT_STAT); 3470 if (val & MVPP22_XLG_EXT_INT_STAT_XLG) 3471 mvpp2_isr_handle_xlg(port); 3472 if (val & MVPP22_XLG_EXT_INT_STAT_PTP) 3473 mvpp2_isr_handle_ptp(port); 3474 } else { 3475 /* If it's not the XLG, we must be using the GMAC. 3476 * Check the summary status. 3477 */ 3478 val = readl(port->base + MVPP22_GMAC_INT_SUM_STAT); 3479 if (val & MVPP22_GMAC_INT_SUM_STAT_INTERNAL) 3480 mvpp2_isr_handle_gmac_internal(port); 3481 if (val & MVPP22_GMAC_INT_SUM_STAT_PTP) 3482 mvpp2_isr_handle_ptp(port); 3483 } 3484 3485 mvpp22_gop_unmask_irq(port); 3486 return IRQ_HANDLED; 3487 } 3488 3489 static enum hrtimer_restart mvpp2_hr_timer_cb(struct hrtimer *timer) 3490 { 3491 struct net_device *dev; 3492 struct mvpp2_port *port; 3493 struct mvpp2_port_pcpu *port_pcpu; 3494 unsigned int tx_todo, cause; 3495 3496 port_pcpu = container_of(timer, struct mvpp2_port_pcpu, tx_done_timer); 3497 dev = port_pcpu->dev; 3498 3499 if (!netif_running(dev)) 3500 return HRTIMER_NORESTART; 3501 3502 port_pcpu->timer_scheduled = false; 3503 port = netdev_priv(dev); 3504 3505 /* Process all the Tx queues */ 3506 cause = (1 << port->ntxqs) - 1; 3507 tx_todo = mvpp2_tx_done(port, cause, 3508 mvpp2_cpu_to_thread(port->priv, smp_processor_id())); 3509 3510 /* Set the timer in case not all the packets were processed */ 3511 if (tx_todo && !port_pcpu->timer_scheduled) { 3512 port_pcpu->timer_scheduled = true; 3513 hrtimer_forward_now(&port_pcpu->tx_done_timer, 3514 MVPP2_TXDONE_HRTIMER_PERIOD_NS); 3515 3516 return HRTIMER_RESTART; 3517 } 3518 return HRTIMER_NORESTART; 3519 } 3520 3521 /* Main RX/TX processing routines */ 3522 3523 /* Display more error info */ 3524 static void mvpp2_rx_error(struct mvpp2_port *port, 3525 struct mvpp2_rx_desc *rx_desc) 3526 { 3527 u32 status = mvpp2_rxdesc_status_get(port, rx_desc); 3528 size_t sz = mvpp2_rxdesc_size_get(port, rx_desc); 3529 char *err_str = NULL; 3530 3531 switch (status & MVPP2_RXD_ERR_CODE_MASK) { 3532 case MVPP2_RXD_ERR_CRC: 3533 err_str = "crc"; 3534 break; 3535 case MVPP2_RXD_ERR_OVERRUN: 3536 err_str = "overrun"; 3537 break; 3538 case MVPP2_RXD_ERR_RESOURCE: 3539 err_str = "resource"; 3540 break; 3541 } 3542 if (err_str && net_ratelimit()) 3543 netdev_err(port->dev, 3544 "bad rx status %08x (%s error), size=%zu\n", 3545 status, err_str, sz); 3546 } 3547 3548 /* Handle RX checksum offload */ 3549 static int mvpp2_rx_csum(struct mvpp2_port *port, u32 status) 3550 { 3551 if (((status & MVPP2_RXD_L3_IP4) && 3552 !(status & MVPP2_RXD_IP4_HEADER_ERR)) || 3553 (status & MVPP2_RXD_L3_IP6)) 3554 if (((status & MVPP2_RXD_L4_UDP) || 3555 (status & MVPP2_RXD_L4_TCP)) && 3556 (status & MVPP2_RXD_L4_CSUM_OK)) 3557 return CHECKSUM_UNNECESSARY; 3558 3559 return CHECKSUM_NONE; 3560 } 3561 3562 /* Allocate a new skb and add it to BM pool */ 3563 static int mvpp2_rx_refill(struct mvpp2_port *port, 3564 struct mvpp2_bm_pool *bm_pool, 3565 struct page_pool *page_pool, int pool) 3566 { 3567 dma_addr_t dma_addr; 3568 phys_addr_t phys_addr; 3569 void *buf; 3570 3571 buf = mvpp2_buf_alloc(port, bm_pool, page_pool, 3572 &dma_addr, &phys_addr, GFP_ATOMIC); 3573 if (!buf) 3574 return -ENOMEM; 3575 3576 mvpp2_bm_pool_put(port, pool, dma_addr, phys_addr); 3577 3578 return 0; 3579 } 3580 3581 /* Handle tx checksum */ 3582 static u32 mvpp2_skb_tx_csum(struct mvpp2_port *port, struct sk_buff *skb) 3583 { 3584 if (skb->ip_summed == CHECKSUM_PARTIAL) { 3585 int ip_hdr_len = 0; 3586 u8 l4_proto; 3587 __be16 l3_proto = vlan_get_protocol(skb); 3588 3589 if (l3_proto == htons(ETH_P_IP)) { 3590 struct iphdr *ip4h = ip_hdr(skb); 3591 3592 /* Calculate IPv4 checksum and L4 checksum */ 3593 ip_hdr_len = ip4h->ihl; 3594 l4_proto = ip4h->protocol; 3595 } else if (l3_proto == htons(ETH_P_IPV6)) { 3596 struct ipv6hdr *ip6h = ipv6_hdr(skb); 3597 3598 /* Read l4_protocol from one of IPv6 extra headers */ 3599 if (skb_network_header_len(skb) > 0) 3600 ip_hdr_len = (skb_network_header_len(skb) >> 2); 3601 l4_proto = ip6h->nexthdr; 3602 } else { 3603 return MVPP2_TXD_L4_CSUM_NOT; 3604 } 3605 3606 return mvpp2_txq_desc_csum(skb_network_offset(skb), 3607 l3_proto, ip_hdr_len, l4_proto); 3608 } 3609 3610 return MVPP2_TXD_L4_CSUM_NOT | MVPP2_TXD_IP_CSUM_DISABLE; 3611 } 3612 3613 static void mvpp2_xdp_finish_tx(struct mvpp2_port *port, u16 txq_id, int nxmit, int nxmit_byte) 3614 { 3615 unsigned int thread = mvpp2_cpu_to_thread(port->priv, smp_processor_id()); 3616 struct mvpp2_tx_queue *aggr_txq; 3617 struct mvpp2_txq_pcpu *txq_pcpu; 3618 struct mvpp2_tx_queue *txq; 3619 struct netdev_queue *nq; 3620 3621 txq = port->txqs[txq_id]; 3622 txq_pcpu = per_cpu_ptr(txq->pcpu, thread); 3623 nq = netdev_get_tx_queue(port->dev, txq_id); 3624 aggr_txq = &port->priv->aggr_txqs[thread]; 3625 3626 txq_pcpu->reserved_num -= nxmit; 3627 txq_pcpu->count += nxmit; 3628 aggr_txq->count += nxmit; 3629 3630 /* Enable transmit */ 3631 wmb(); 3632 mvpp2_aggr_txq_pend_desc_add(port, nxmit); 3633 3634 if (txq_pcpu->count >= txq_pcpu->stop_threshold) 3635 netif_tx_stop_queue(nq); 3636 3637 /* Finalize TX processing */ 3638 if (!port->has_tx_irqs && txq_pcpu->count >= txq->done_pkts_coal) 3639 mvpp2_txq_done(port, txq, txq_pcpu); 3640 } 3641 3642 static int 3643 mvpp2_xdp_submit_frame(struct mvpp2_port *port, u16 txq_id, 3644 struct xdp_frame *xdpf, bool dma_map) 3645 { 3646 unsigned int thread = mvpp2_cpu_to_thread(port->priv, smp_processor_id()); 3647 u32 tx_cmd = MVPP2_TXD_L4_CSUM_NOT | MVPP2_TXD_IP_CSUM_DISABLE | 3648 MVPP2_TXD_F_DESC | MVPP2_TXD_L_DESC; 3649 enum mvpp2_tx_buf_type buf_type; 3650 struct mvpp2_txq_pcpu *txq_pcpu; 3651 struct mvpp2_tx_queue *aggr_txq; 3652 struct mvpp2_tx_desc *tx_desc; 3653 struct mvpp2_tx_queue *txq; 3654 int ret = MVPP2_XDP_TX; 3655 dma_addr_t dma_addr; 3656 3657 txq = port->txqs[txq_id]; 3658 txq_pcpu = per_cpu_ptr(txq->pcpu, thread); 3659 aggr_txq = &port->priv->aggr_txqs[thread]; 3660 3661 /* Check number of available descriptors */ 3662 if (mvpp2_aggr_desc_num_check(port, aggr_txq, 1) || 3663 mvpp2_txq_reserved_desc_num_proc(port, txq, txq_pcpu, 1)) { 3664 ret = MVPP2_XDP_DROPPED; 3665 goto out; 3666 } 3667 3668 /* Get a descriptor for the first part of the packet */ 3669 tx_desc = mvpp2_txq_next_desc_get(aggr_txq); 3670 mvpp2_txdesc_txq_set(port, tx_desc, txq->id); 3671 mvpp2_txdesc_size_set(port, tx_desc, xdpf->len); 3672 3673 if (dma_map) { 3674 /* XDP_REDIRECT or AF_XDP */ 3675 dma_addr = dma_map_single(port->dev->dev.parent, xdpf->data, 3676 xdpf->len, DMA_TO_DEVICE); 3677 3678 if (unlikely(dma_mapping_error(port->dev->dev.parent, dma_addr))) { 3679 mvpp2_txq_desc_put(txq); 3680 ret = MVPP2_XDP_DROPPED; 3681 goto out; 3682 } 3683 3684 buf_type = MVPP2_TYPE_XDP_NDO; 3685 } else { 3686 /* XDP_TX */ 3687 struct page *page = virt_to_page(xdpf->data); 3688 3689 dma_addr = page_pool_get_dma_addr(page) + 3690 sizeof(*xdpf) + xdpf->headroom; 3691 dma_sync_single_for_device(port->dev->dev.parent, dma_addr, 3692 xdpf->len, DMA_BIDIRECTIONAL); 3693 3694 buf_type = MVPP2_TYPE_XDP_TX; 3695 } 3696 3697 mvpp2_txdesc_dma_addr_set(port, tx_desc, dma_addr); 3698 3699 mvpp2_txdesc_cmd_set(port, tx_desc, tx_cmd); 3700 mvpp2_txq_inc_put(port, txq_pcpu, xdpf, tx_desc, buf_type); 3701 3702 out: 3703 return ret; 3704 } 3705 3706 static int 3707 mvpp2_xdp_xmit_back(struct mvpp2_port *port, struct xdp_buff *xdp) 3708 { 3709 struct mvpp2_pcpu_stats *stats = this_cpu_ptr(port->stats); 3710 struct xdp_frame *xdpf; 3711 u16 txq_id; 3712 int ret; 3713 3714 xdpf = xdp_convert_buff_to_frame(xdp); 3715 if (unlikely(!xdpf)) 3716 return MVPP2_XDP_DROPPED; 3717 3718 /* The first of the TX queues are used for XPS, 3719 * the second half for XDP_TX 3720 */ 3721 txq_id = mvpp2_cpu_to_thread(port->priv, smp_processor_id()) + (port->ntxqs / 2); 3722 3723 ret = mvpp2_xdp_submit_frame(port, txq_id, xdpf, false); 3724 if (ret == MVPP2_XDP_TX) { 3725 u64_stats_update_begin(&stats->syncp); 3726 stats->tx_bytes += xdpf->len; 3727 stats->tx_packets++; 3728 stats->xdp_tx++; 3729 u64_stats_update_end(&stats->syncp); 3730 3731 mvpp2_xdp_finish_tx(port, txq_id, 1, xdpf->len); 3732 } else { 3733 u64_stats_update_begin(&stats->syncp); 3734 stats->xdp_tx_err++; 3735 u64_stats_update_end(&stats->syncp); 3736 } 3737 3738 return ret; 3739 } 3740 3741 static int 3742 mvpp2_xdp_xmit(struct net_device *dev, int num_frame, 3743 struct xdp_frame **frames, u32 flags) 3744 { 3745 struct mvpp2_port *port = netdev_priv(dev); 3746 int i, nxmit_byte = 0, nxmit = 0; 3747 struct mvpp2_pcpu_stats *stats; 3748 u16 txq_id; 3749 u32 ret; 3750 3751 if (unlikely(test_bit(0, &port->state))) 3752 return -ENETDOWN; 3753 3754 if (unlikely(flags & ~XDP_XMIT_FLAGS_MASK)) 3755 return -EINVAL; 3756 3757 /* The first of the TX queues are used for XPS, 3758 * the second half for XDP_TX 3759 */ 3760 txq_id = mvpp2_cpu_to_thread(port->priv, smp_processor_id()) + (port->ntxqs / 2); 3761 3762 for (i = 0; i < num_frame; i++) { 3763 ret = mvpp2_xdp_submit_frame(port, txq_id, frames[i], true); 3764 if (ret != MVPP2_XDP_TX) 3765 break; 3766 3767 nxmit_byte += frames[i]->len; 3768 nxmit++; 3769 } 3770 3771 if (likely(nxmit > 0)) 3772 mvpp2_xdp_finish_tx(port, txq_id, nxmit, nxmit_byte); 3773 3774 stats = this_cpu_ptr(port->stats); 3775 u64_stats_update_begin(&stats->syncp); 3776 stats->tx_bytes += nxmit_byte; 3777 stats->tx_packets += nxmit; 3778 stats->xdp_xmit += nxmit; 3779 stats->xdp_xmit_err += num_frame - nxmit; 3780 u64_stats_update_end(&stats->syncp); 3781 3782 return nxmit; 3783 } 3784 3785 static int 3786 mvpp2_run_xdp(struct mvpp2_port *port, struct bpf_prog *prog, 3787 struct xdp_buff *xdp, struct page_pool *pp, 3788 struct mvpp2_pcpu_stats *stats) 3789 { 3790 unsigned int len, sync, err; 3791 struct page *page; 3792 u32 ret, act; 3793 3794 len = xdp->data_end - xdp->data_hard_start - MVPP2_SKB_HEADROOM; 3795 act = bpf_prog_run_xdp(prog, xdp); 3796 3797 /* Due xdp_adjust_tail: DMA sync for_device cover max len CPU touch */ 3798 sync = xdp->data_end - xdp->data_hard_start - MVPP2_SKB_HEADROOM; 3799 sync = max(sync, len); 3800 3801 switch (act) { 3802 case XDP_PASS: 3803 stats->xdp_pass++; 3804 ret = MVPP2_XDP_PASS; 3805 break; 3806 case XDP_REDIRECT: 3807 err = xdp_do_redirect(port->dev, xdp, prog); 3808 if (unlikely(err)) { 3809 ret = MVPP2_XDP_DROPPED; 3810 page = virt_to_head_page(xdp->data); 3811 page_pool_put_page(pp, page, sync, true); 3812 } else { 3813 ret = MVPP2_XDP_REDIR; 3814 stats->xdp_redirect++; 3815 } 3816 break; 3817 case XDP_TX: 3818 ret = mvpp2_xdp_xmit_back(port, xdp); 3819 if (ret != MVPP2_XDP_TX) { 3820 page = virt_to_head_page(xdp->data); 3821 page_pool_put_page(pp, page, sync, true); 3822 } 3823 break; 3824 default: 3825 bpf_warn_invalid_xdp_action(port->dev, prog, act); 3826 fallthrough; 3827 case XDP_ABORTED: 3828 trace_xdp_exception(port->dev, prog, act); 3829 fallthrough; 3830 case XDP_DROP: 3831 page = virt_to_head_page(xdp->data); 3832 page_pool_put_page(pp, page, sync, true); 3833 ret = MVPP2_XDP_DROPPED; 3834 stats->xdp_drop++; 3835 break; 3836 } 3837 3838 return ret; 3839 } 3840 3841 static void mvpp2_buff_hdr_pool_put(struct mvpp2_port *port, struct mvpp2_rx_desc *rx_desc, 3842 int pool, u32 rx_status) 3843 { 3844 phys_addr_t phys_addr, phys_addr_next; 3845 dma_addr_t dma_addr, dma_addr_next; 3846 struct mvpp2_buff_hdr *buff_hdr; 3847 3848 phys_addr = mvpp2_rxdesc_dma_addr_get(port, rx_desc); 3849 dma_addr = mvpp2_rxdesc_cookie_get(port, rx_desc); 3850 3851 do { 3852 buff_hdr = (struct mvpp2_buff_hdr *)phys_to_virt(phys_addr); 3853 3854 phys_addr_next = le32_to_cpu(buff_hdr->next_phys_addr); 3855 dma_addr_next = le32_to_cpu(buff_hdr->next_dma_addr); 3856 3857 if (port->priv->hw_version >= MVPP22) { 3858 phys_addr_next |= ((u64)buff_hdr->next_phys_addr_high << 32); 3859 dma_addr_next |= ((u64)buff_hdr->next_dma_addr_high << 32); 3860 } 3861 3862 mvpp2_bm_pool_put(port, pool, dma_addr, phys_addr); 3863 3864 phys_addr = phys_addr_next; 3865 dma_addr = dma_addr_next; 3866 3867 } while (!MVPP2_B_HDR_INFO_IS_LAST(le16_to_cpu(buff_hdr->info))); 3868 } 3869 3870 /* Main rx processing */ 3871 static int mvpp2_rx(struct mvpp2_port *port, struct napi_struct *napi, 3872 int rx_todo, struct mvpp2_rx_queue *rxq) 3873 { 3874 struct net_device *dev = port->dev; 3875 struct mvpp2_pcpu_stats ps = {}; 3876 enum dma_data_direction dma_dir; 3877 struct bpf_prog *xdp_prog; 3878 struct xdp_buff xdp; 3879 int rx_received; 3880 int rx_done = 0; 3881 u32 xdp_ret = 0; 3882 3883 xdp_prog = READ_ONCE(port->xdp_prog); 3884 3885 /* Get number of received packets and clamp the to-do */ 3886 rx_received = mvpp2_rxq_received(port, rxq->id); 3887 if (rx_todo > rx_received) 3888 rx_todo = rx_received; 3889 3890 while (rx_done < rx_todo) { 3891 struct mvpp2_rx_desc *rx_desc = mvpp2_rxq_next_desc_get(rxq); 3892 struct mvpp2_bm_pool *bm_pool; 3893 struct page_pool *pp = NULL; 3894 struct sk_buff *skb; 3895 unsigned int frag_size; 3896 dma_addr_t dma_addr; 3897 phys_addr_t phys_addr; 3898 u32 rx_status, timestamp; 3899 int pool, rx_bytes, err, ret; 3900 struct page *page; 3901 void *data; 3902 3903 phys_addr = mvpp2_rxdesc_cookie_get(port, rx_desc); 3904 data = (void *)phys_to_virt(phys_addr); 3905 page = virt_to_page(data); 3906 prefetch(page); 3907 3908 rx_done++; 3909 rx_status = mvpp2_rxdesc_status_get(port, rx_desc); 3910 rx_bytes = mvpp2_rxdesc_size_get(port, rx_desc); 3911 rx_bytes -= MVPP2_MH_SIZE; 3912 dma_addr = mvpp2_rxdesc_dma_addr_get(port, rx_desc); 3913 3914 pool = (rx_status & MVPP2_RXD_BM_POOL_ID_MASK) >> 3915 MVPP2_RXD_BM_POOL_ID_OFFS; 3916 bm_pool = &port->priv->bm_pools[pool]; 3917 3918 if (port->priv->percpu_pools) { 3919 pp = port->priv->page_pool[pool]; 3920 dma_dir = page_pool_get_dma_dir(pp); 3921 } else { 3922 dma_dir = DMA_FROM_DEVICE; 3923 } 3924 3925 dma_sync_single_for_cpu(dev->dev.parent, dma_addr, 3926 rx_bytes + MVPP2_MH_SIZE, 3927 dma_dir); 3928 3929 /* Buffer header not supported */ 3930 if (rx_status & MVPP2_RXD_BUF_HDR) 3931 goto err_drop_frame; 3932 3933 /* In case of an error, release the requested buffer pointer 3934 * to the Buffer Manager. This request process is controlled 3935 * by the hardware, and the information about the buffer is 3936 * comprised by the RX descriptor. 3937 */ 3938 if (rx_status & MVPP2_RXD_ERR_SUMMARY) 3939 goto err_drop_frame; 3940 3941 /* Prefetch header */ 3942 prefetch(data + MVPP2_MH_SIZE + MVPP2_SKB_HEADROOM); 3943 3944 if (bm_pool->frag_size > PAGE_SIZE) 3945 frag_size = 0; 3946 else 3947 frag_size = bm_pool->frag_size; 3948 3949 if (xdp_prog) { 3950 struct xdp_rxq_info *xdp_rxq; 3951 3952 if (bm_pool->pkt_size == MVPP2_BM_SHORT_PKT_SIZE) 3953 xdp_rxq = &rxq->xdp_rxq_short; 3954 else 3955 xdp_rxq = &rxq->xdp_rxq_long; 3956 3957 xdp_init_buff(&xdp, PAGE_SIZE, xdp_rxq); 3958 xdp_prepare_buff(&xdp, data, 3959 MVPP2_MH_SIZE + MVPP2_SKB_HEADROOM, 3960 rx_bytes, false); 3961 3962 ret = mvpp2_run_xdp(port, xdp_prog, &xdp, pp, &ps); 3963 3964 if (ret) { 3965 xdp_ret |= ret; 3966 err = mvpp2_rx_refill(port, bm_pool, pp, pool); 3967 if (err) { 3968 netdev_err(port->dev, "failed to refill BM pools\n"); 3969 goto err_drop_frame; 3970 } 3971 3972 ps.rx_packets++; 3973 ps.rx_bytes += rx_bytes; 3974 continue; 3975 } 3976 } 3977 3978 skb = build_skb(data, frag_size); 3979 if (!skb) { 3980 netdev_warn(port->dev, "skb build failed\n"); 3981 goto err_drop_frame; 3982 } 3983 3984 /* If we have RX hardware timestamping enabled, grab the 3985 * timestamp from the queue and convert. 3986 */ 3987 if (mvpp22_rx_hwtstamping(port)) { 3988 timestamp = le32_to_cpu(rx_desc->pp22.timestamp); 3989 mvpp22_tai_tstamp(port->priv->tai, timestamp, 3990 skb_hwtstamps(skb)); 3991 } 3992 3993 err = mvpp2_rx_refill(port, bm_pool, pp, pool); 3994 if (err) { 3995 netdev_err(port->dev, "failed to refill BM pools\n"); 3996 dev_kfree_skb_any(skb); 3997 goto err_drop_frame; 3998 } 3999 4000 if (pp) 4001 skb_mark_for_recycle(skb); 4002 else 4003 dma_unmap_single_attrs(dev->dev.parent, dma_addr, 4004 bm_pool->buf_size, DMA_FROM_DEVICE, 4005 DMA_ATTR_SKIP_CPU_SYNC); 4006 4007 ps.rx_packets++; 4008 ps.rx_bytes += rx_bytes; 4009 4010 skb_reserve(skb, MVPP2_MH_SIZE + MVPP2_SKB_HEADROOM); 4011 skb_put(skb, rx_bytes); 4012 skb->ip_summed = mvpp2_rx_csum(port, rx_status); 4013 skb->protocol = eth_type_trans(skb, dev); 4014 4015 napi_gro_receive(napi, skb); 4016 continue; 4017 4018 err_drop_frame: 4019 dev->stats.rx_errors++; 4020 mvpp2_rx_error(port, rx_desc); 4021 /* Return the buffer to the pool */ 4022 if (rx_status & MVPP2_RXD_BUF_HDR) 4023 mvpp2_buff_hdr_pool_put(port, rx_desc, pool, rx_status); 4024 else 4025 mvpp2_bm_pool_put(port, pool, dma_addr, phys_addr); 4026 } 4027 4028 if (xdp_ret & MVPP2_XDP_REDIR) 4029 xdp_do_flush_map(); 4030 4031 if (ps.rx_packets) { 4032 struct mvpp2_pcpu_stats *stats = this_cpu_ptr(port->stats); 4033 4034 u64_stats_update_begin(&stats->syncp); 4035 stats->rx_packets += ps.rx_packets; 4036 stats->rx_bytes += ps.rx_bytes; 4037 /* xdp */ 4038 stats->xdp_redirect += ps.xdp_redirect; 4039 stats->xdp_pass += ps.xdp_pass; 4040 stats->xdp_drop += ps.xdp_drop; 4041 u64_stats_update_end(&stats->syncp); 4042 } 4043 4044 /* Update Rx queue management counters */ 4045 wmb(); 4046 mvpp2_rxq_status_update(port, rxq->id, rx_done, rx_done); 4047 4048 return rx_todo; 4049 } 4050 4051 static inline void 4052 tx_desc_unmap_put(struct mvpp2_port *port, struct mvpp2_tx_queue *txq, 4053 struct mvpp2_tx_desc *desc) 4054 { 4055 unsigned int thread = mvpp2_cpu_to_thread(port->priv, smp_processor_id()); 4056 struct mvpp2_txq_pcpu *txq_pcpu = per_cpu_ptr(txq->pcpu, thread); 4057 4058 dma_addr_t buf_dma_addr = 4059 mvpp2_txdesc_dma_addr_get(port, desc); 4060 size_t buf_sz = 4061 mvpp2_txdesc_size_get(port, desc); 4062 if (!IS_TSO_HEADER(txq_pcpu, buf_dma_addr)) 4063 dma_unmap_single(port->dev->dev.parent, buf_dma_addr, 4064 buf_sz, DMA_TO_DEVICE); 4065 mvpp2_txq_desc_put(txq); 4066 } 4067 4068 static void mvpp2_txdesc_clear_ptp(struct mvpp2_port *port, 4069 struct mvpp2_tx_desc *desc) 4070 { 4071 /* We only need to clear the low bits */ 4072 if (port->priv->hw_version >= MVPP22) 4073 desc->pp22.ptp_descriptor &= 4074 cpu_to_le32(~MVPP22_PTP_DESC_MASK_LOW); 4075 } 4076 4077 static bool mvpp2_tx_hw_tstamp(struct mvpp2_port *port, 4078 struct mvpp2_tx_desc *tx_desc, 4079 struct sk_buff *skb) 4080 { 4081 struct mvpp2_hwtstamp_queue *queue; 4082 unsigned int mtype, type, i; 4083 struct ptp_header *hdr; 4084 u64 ptpdesc; 4085 4086 if (port->priv->hw_version == MVPP21 || 4087 port->tx_hwtstamp_type == HWTSTAMP_TX_OFF) 4088 return false; 4089 4090 type = ptp_classify_raw(skb); 4091 if (!type) 4092 return false; 4093 4094 hdr = ptp_parse_header(skb, type); 4095 if (!hdr) 4096 return false; 4097 4098 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 4099 4100 ptpdesc = MVPP22_PTP_MACTIMESTAMPINGEN | 4101 MVPP22_PTP_ACTION_CAPTURE; 4102 queue = &port->tx_hwtstamp_queue[0]; 4103 4104 switch (type & PTP_CLASS_VMASK) { 4105 case PTP_CLASS_V1: 4106 ptpdesc |= MVPP22_PTP_PACKETFORMAT(MVPP22_PTP_PKT_FMT_PTPV1); 4107 break; 4108 4109 case PTP_CLASS_V2: 4110 ptpdesc |= MVPP22_PTP_PACKETFORMAT(MVPP22_PTP_PKT_FMT_PTPV2); 4111 mtype = hdr->tsmt & 15; 4112 /* Direct PTP Sync messages to queue 1 */ 4113 if (mtype == 0) { 4114 ptpdesc |= MVPP22_PTP_TIMESTAMPQUEUESELECT; 4115 queue = &port->tx_hwtstamp_queue[1]; 4116 } 4117 break; 4118 } 4119 4120 /* Take a reference on the skb and insert into our queue */ 4121 i = queue->next; 4122 queue->next = (i + 1) & 31; 4123 if (queue->skb[i]) 4124 dev_kfree_skb_any(queue->skb[i]); 4125 queue->skb[i] = skb_get(skb); 4126 4127 ptpdesc |= MVPP22_PTP_TIMESTAMPENTRYID(i); 4128 4129 /* 4130 * 3:0 - PTPAction 4131 * 6:4 - PTPPacketFormat 4132 * 7 - PTP_CF_WraparoundCheckEn 4133 * 9:8 - IngressTimestampSeconds[1:0] 4134 * 10 - Reserved 4135 * 11 - MACTimestampingEn 4136 * 17:12 - PTP_TimestampQueueEntryID[5:0] 4137 * 18 - PTPTimestampQueueSelect 4138 * 19 - UDPChecksumUpdateEn 4139 * 27:20 - TimestampOffset 4140 * PTP, NTPTransmit, OWAMP/TWAMP - L3 to PTP header 4141 * NTPTs, Y.1731 - L3 to timestamp entry 4142 * 35:28 - UDP Checksum Offset 4143 * 4144 * stored in tx descriptor bits 75:64 (11:0) and 191:168 (35:12) 4145 */ 4146 tx_desc->pp22.ptp_descriptor &= 4147 cpu_to_le32(~MVPP22_PTP_DESC_MASK_LOW); 4148 tx_desc->pp22.ptp_descriptor |= 4149 cpu_to_le32(ptpdesc & MVPP22_PTP_DESC_MASK_LOW); 4150 tx_desc->pp22.buf_dma_addr_ptp &= cpu_to_le64(~0xffffff0000000000ULL); 4151 tx_desc->pp22.buf_dma_addr_ptp |= cpu_to_le64((ptpdesc >> 12) << 40); 4152 4153 return true; 4154 } 4155 4156 /* Handle tx fragmentation processing */ 4157 static int mvpp2_tx_frag_process(struct mvpp2_port *port, struct sk_buff *skb, 4158 struct mvpp2_tx_queue *aggr_txq, 4159 struct mvpp2_tx_queue *txq) 4160 { 4161 unsigned int thread = mvpp2_cpu_to_thread(port->priv, smp_processor_id()); 4162 struct mvpp2_txq_pcpu *txq_pcpu = per_cpu_ptr(txq->pcpu, thread); 4163 struct mvpp2_tx_desc *tx_desc; 4164 int i; 4165 dma_addr_t buf_dma_addr; 4166 4167 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { 4168 skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 4169 void *addr = skb_frag_address(frag); 4170 4171 tx_desc = mvpp2_txq_next_desc_get(aggr_txq); 4172 mvpp2_txdesc_clear_ptp(port, tx_desc); 4173 mvpp2_txdesc_txq_set(port, tx_desc, txq->id); 4174 mvpp2_txdesc_size_set(port, tx_desc, skb_frag_size(frag)); 4175 4176 buf_dma_addr = dma_map_single(port->dev->dev.parent, addr, 4177 skb_frag_size(frag), 4178 DMA_TO_DEVICE); 4179 if (dma_mapping_error(port->dev->dev.parent, buf_dma_addr)) { 4180 mvpp2_txq_desc_put(txq); 4181 goto cleanup; 4182 } 4183 4184 mvpp2_txdesc_dma_addr_set(port, tx_desc, buf_dma_addr); 4185 4186 if (i == (skb_shinfo(skb)->nr_frags - 1)) { 4187 /* Last descriptor */ 4188 mvpp2_txdesc_cmd_set(port, tx_desc, 4189 MVPP2_TXD_L_DESC); 4190 mvpp2_txq_inc_put(port, txq_pcpu, skb, tx_desc, MVPP2_TYPE_SKB); 4191 } else { 4192 /* Descriptor in the middle: Not First, Not Last */ 4193 mvpp2_txdesc_cmd_set(port, tx_desc, 0); 4194 mvpp2_txq_inc_put(port, txq_pcpu, NULL, tx_desc, MVPP2_TYPE_SKB); 4195 } 4196 } 4197 4198 return 0; 4199 cleanup: 4200 /* Release all descriptors that were used to map fragments of 4201 * this packet, as well as the corresponding DMA mappings 4202 */ 4203 for (i = i - 1; i >= 0; i--) { 4204 tx_desc = txq->descs + i; 4205 tx_desc_unmap_put(port, txq, tx_desc); 4206 } 4207 4208 return -ENOMEM; 4209 } 4210 4211 static inline void mvpp2_tso_put_hdr(struct sk_buff *skb, 4212 struct net_device *dev, 4213 struct mvpp2_tx_queue *txq, 4214 struct mvpp2_tx_queue *aggr_txq, 4215 struct mvpp2_txq_pcpu *txq_pcpu, 4216 int hdr_sz) 4217 { 4218 struct mvpp2_port *port = netdev_priv(dev); 4219 struct mvpp2_tx_desc *tx_desc = mvpp2_txq_next_desc_get(aggr_txq); 4220 dma_addr_t addr; 4221 4222 mvpp2_txdesc_clear_ptp(port, tx_desc); 4223 mvpp2_txdesc_txq_set(port, tx_desc, txq->id); 4224 mvpp2_txdesc_size_set(port, tx_desc, hdr_sz); 4225 4226 addr = txq_pcpu->tso_headers_dma + 4227 txq_pcpu->txq_put_index * TSO_HEADER_SIZE; 4228 mvpp2_txdesc_dma_addr_set(port, tx_desc, addr); 4229 4230 mvpp2_txdesc_cmd_set(port, tx_desc, mvpp2_skb_tx_csum(port, skb) | 4231 MVPP2_TXD_F_DESC | 4232 MVPP2_TXD_PADDING_DISABLE); 4233 mvpp2_txq_inc_put(port, txq_pcpu, NULL, tx_desc, MVPP2_TYPE_SKB); 4234 } 4235 4236 static inline int mvpp2_tso_put_data(struct sk_buff *skb, 4237 struct net_device *dev, struct tso_t *tso, 4238 struct mvpp2_tx_queue *txq, 4239 struct mvpp2_tx_queue *aggr_txq, 4240 struct mvpp2_txq_pcpu *txq_pcpu, 4241 int sz, bool left, bool last) 4242 { 4243 struct mvpp2_port *port = netdev_priv(dev); 4244 struct mvpp2_tx_desc *tx_desc = mvpp2_txq_next_desc_get(aggr_txq); 4245 dma_addr_t buf_dma_addr; 4246 4247 mvpp2_txdesc_clear_ptp(port, tx_desc); 4248 mvpp2_txdesc_txq_set(port, tx_desc, txq->id); 4249 mvpp2_txdesc_size_set(port, tx_desc, sz); 4250 4251 buf_dma_addr = dma_map_single(dev->dev.parent, tso->data, sz, 4252 DMA_TO_DEVICE); 4253 if (unlikely(dma_mapping_error(dev->dev.parent, buf_dma_addr))) { 4254 mvpp2_txq_desc_put(txq); 4255 return -ENOMEM; 4256 } 4257 4258 mvpp2_txdesc_dma_addr_set(port, tx_desc, buf_dma_addr); 4259 4260 if (!left) { 4261 mvpp2_txdesc_cmd_set(port, tx_desc, MVPP2_TXD_L_DESC); 4262 if (last) { 4263 mvpp2_txq_inc_put(port, txq_pcpu, skb, tx_desc, MVPP2_TYPE_SKB); 4264 return 0; 4265 } 4266 } else { 4267 mvpp2_txdesc_cmd_set(port, tx_desc, 0); 4268 } 4269 4270 mvpp2_txq_inc_put(port, txq_pcpu, NULL, tx_desc, MVPP2_TYPE_SKB); 4271 return 0; 4272 } 4273 4274 static int mvpp2_tx_tso(struct sk_buff *skb, struct net_device *dev, 4275 struct mvpp2_tx_queue *txq, 4276 struct mvpp2_tx_queue *aggr_txq, 4277 struct mvpp2_txq_pcpu *txq_pcpu) 4278 { 4279 struct mvpp2_port *port = netdev_priv(dev); 4280 int hdr_sz, i, len, descs = 0; 4281 struct tso_t tso; 4282 4283 /* Check number of available descriptors */ 4284 if (mvpp2_aggr_desc_num_check(port, aggr_txq, tso_count_descs(skb)) || 4285 mvpp2_txq_reserved_desc_num_proc(port, txq, txq_pcpu, 4286 tso_count_descs(skb))) 4287 return 0; 4288 4289 hdr_sz = tso_start(skb, &tso); 4290 4291 len = skb->len - hdr_sz; 4292 while (len > 0) { 4293 int left = min_t(int, skb_shinfo(skb)->gso_size, len); 4294 char *hdr = txq_pcpu->tso_headers + 4295 txq_pcpu->txq_put_index * TSO_HEADER_SIZE; 4296 4297 len -= left; 4298 descs++; 4299 4300 tso_build_hdr(skb, hdr, &tso, left, len == 0); 4301 mvpp2_tso_put_hdr(skb, dev, txq, aggr_txq, txq_pcpu, hdr_sz); 4302 4303 while (left > 0) { 4304 int sz = min_t(int, tso.size, left); 4305 left -= sz; 4306 descs++; 4307 4308 if (mvpp2_tso_put_data(skb, dev, &tso, txq, aggr_txq, 4309 txq_pcpu, sz, left, len == 0)) 4310 goto release; 4311 tso_build_data(skb, &tso, sz); 4312 } 4313 } 4314 4315 return descs; 4316 4317 release: 4318 for (i = descs - 1; i >= 0; i--) { 4319 struct mvpp2_tx_desc *tx_desc = txq->descs + i; 4320 tx_desc_unmap_put(port, txq, tx_desc); 4321 } 4322 return 0; 4323 } 4324 4325 /* Main tx processing */ 4326 static netdev_tx_t mvpp2_tx(struct sk_buff *skb, struct net_device *dev) 4327 { 4328 struct mvpp2_port *port = netdev_priv(dev); 4329 struct mvpp2_tx_queue *txq, *aggr_txq; 4330 struct mvpp2_txq_pcpu *txq_pcpu; 4331 struct mvpp2_tx_desc *tx_desc; 4332 dma_addr_t buf_dma_addr; 4333 unsigned long flags = 0; 4334 unsigned int thread; 4335 int frags = 0; 4336 u16 txq_id; 4337 u32 tx_cmd; 4338 4339 thread = mvpp2_cpu_to_thread(port->priv, smp_processor_id()); 4340 4341 txq_id = skb_get_queue_mapping(skb); 4342 txq = port->txqs[txq_id]; 4343 txq_pcpu = per_cpu_ptr(txq->pcpu, thread); 4344 aggr_txq = &port->priv->aggr_txqs[thread]; 4345 4346 if (test_bit(thread, &port->priv->lock_map)) 4347 spin_lock_irqsave(&port->tx_lock[thread], flags); 4348 4349 if (skb_is_gso(skb)) { 4350 frags = mvpp2_tx_tso(skb, dev, txq, aggr_txq, txq_pcpu); 4351 goto out; 4352 } 4353 frags = skb_shinfo(skb)->nr_frags + 1; 4354 4355 /* Check number of available descriptors */ 4356 if (mvpp2_aggr_desc_num_check(port, aggr_txq, frags) || 4357 mvpp2_txq_reserved_desc_num_proc(port, txq, txq_pcpu, frags)) { 4358 frags = 0; 4359 goto out; 4360 } 4361 4362 /* Get a descriptor for the first part of the packet */ 4363 tx_desc = mvpp2_txq_next_desc_get(aggr_txq); 4364 if (!(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) || 4365 !mvpp2_tx_hw_tstamp(port, tx_desc, skb)) 4366 mvpp2_txdesc_clear_ptp(port, tx_desc); 4367 mvpp2_txdesc_txq_set(port, tx_desc, txq->id); 4368 mvpp2_txdesc_size_set(port, tx_desc, skb_headlen(skb)); 4369 4370 buf_dma_addr = dma_map_single(dev->dev.parent, skb->data, 4371 skb_headlen(skb), DMA_TO_DEVICE); 4372 if (unlikely(dma_mapping_error(dev->dev.parent, buf_dma_addr))) { 4373 mvpp2_txq_desc_put(txq); 4374 frags = 0; 4375 goto out; 4376 } 4377 4378 mvpp2_txdesc_dma_addr_set(port, tx_desc, buf_dma_addr); 4379 4380 tx_cmd = mvpp2_skb_tx_csum(port, skb); 4381 4382 if (frags == 1) { 4383 /* First and Last descriptor */ 4384 tx_cmd |= MVPP2_TXD_F_DESC | MVPP2_TXD_L_DESC; 4385 mvpp2_txdesc_cmd_set(port, tx_desc, tx_cmd); 4386 mvpp2_txq_inc_put(port, txq_pcpu, skb, tx_desc, MVPP2_TYPE_SKB); 4387 } else { 4388 /* First but not Last */ 4389 tx_cmd |= MVPP2_TXD_F_DESC | MVPP2_TXD_PADDING_DISABLE; 4390 mvpp2_txdesc_cmd_set(port, tx_desc, tx_cmd); 4391 mvpp2_txq_inc_put(port, txq_pcpu, NULL, tx_desc, MVPP2_TYPE_SKB); 4392 4393 /* Continue with other skb fragments */ 4394 if (mvpp2_tx_frag_process(port, skb, aggr_txq, txq)) { 4395 tx_desc_unmap_put(port, txq, tx_desc); 4396 frags = 0; 4397 } 4398 } 4399 4400 out: 4401 if (frags > 0) { 4402 struct mvpp2_pcpu_stats *stats = per_cpu_ptr(port->stats, thread); 4403 struct netdev_queue *nq = netdev_get_tx_queue(dev, txq_id); 4404 4405 txq_pcpu->reserved_num -= frags; 4406 txq_pcpu->count += frags; 4407 aggr_txq->count += frags; 4408 4409 /* Enable transmit */ 4410 wmb(); 4411 mvpp2_aggr_txq_pend_desc_add(port, frags); 4412 4413 if (txq_pcpu->count >= txq_pcpu->stop_threshold) 4414 netif_tx_stop_queue(nq); 4415 4416 u64_stats_update_begin(&stats->syncp); 4417 stats->tx_packets++; 4418 stats->tx_bytes += skb->len; 4419 u64_stats_update_end(&stats->syncp); 4420 } else { 4421 dev->stats.tx_dropped++; 4422 dev_kfree_skb_any(skb); 4423 } 4424 4425 /* Finalize TX processing */ 4426 if (!port->has_tx_irqs && txq_pcpu->count >= txq->done_pkts_coal) 4427 mvpp2_txq_done(port, txq, txq_pcpu); 4428 4429 /* Set the timer in case not all frags were processed */ 4430 if (!port->has_tx_irqs && txq_pcpu->count <= frags && 4431 txq_pcpu->count > 0) { 4432 struct mvpp2_port_pcpu *port_pcpu = per_cpu_ptr(port->pcpu, thread); 4433 4434 if (!port_pcpu->timer_scheduled) { 4435 port_pcpu->timer_scheduled = true; 4436 hrtimer_start(&port_pcpu->tx_done_timer, 4437 MVPP2_TXDONE_HRTIMER_PERIOD_NS, 4438 HRTIMER_MODE_REL_PINNED_SOFT); 4439 } 4440 } 4441 4442 if (test_bit(thread, &port->priv->lock_map)) 4443 spin_unlock_irqrestore(&port->tx_lock[thread], flags); 4444 4445 return NETDEV_TX_OK; 4446 } 4447 4448 static inline void mvpp2_cause_error(struct net_device *dev, int cause) 4449 { 4450 if (cause & MVPP2_CAUSE_FCS_ERR_MASK) 4451 netdev_err(dev, "FCS error\n"); 4452 if (cause & MVPP2_CAUSE_RX_FIFO_OVERRUN_MASK) 4453 netdev_err(dev, "rx fifo overrun error\n"); 4454 if (cause & MVPP2_CAUSE_TX_FIFO_UNDERRUN_MASK) 4455 netdev_err(dev, "tx fifo underrun error\n"); 4456 } 4457 4458 static int mvpp2_poll(struct napi_struct *napi, int budget) 4459 { 4460 u32 cause_rx_tx, cause_rx, cause_tx, cause_misc; 4461 int rx_done = 0; 4462 struct mvpp2_port *port = netdev_priv(napi->dev); 4463 struct mvpp2_queue_vector *qv; 4464 unsigned int thread = mvpp2_cpu_to_thread(port->priv, smp_processor_id()); 4465 4466 qv = container_of(napi, struct mvpp2_queue_vector, napi); 4467 4468 /* Rx/Tx cause register 4469 * 4470 * Bits 0-15: each bit indicates received packets on the Rx queue 4471 * (bit 0 is for Rx queue 0). 4472 * 4473 * Bits 16-23: each bit indicates transmitted packets on the Tx queue 4474 * (bit 16 is for Tx queue 0). 4475 * 4476 * Each CPU has its own Rx/Tx cause register 4477 */ 4478 cause_rx_tx = mvpp2_thread_read_relaxed(port->priv, qv->sw_thread_id, 4479 MVPP2_ISR_RX_TX_CAUSE_REG(port->id)); 4480 4481 cause_misc = cause_rx_tx & MVPP2_CAUSE_MISC_SUM_MASK; 4482 if (cause_misc) { 4483 mvpp2_cause_error(port->dev, cause_misc); 4484 4485 /* Clear the cause register */ 4486 mvpp2_write(port->priv, MVPP2_ISR_MISC_CAUSE_REG, 0); 4487 mvpp2_thread_write(port->priv, thread, 4488 MVPP2_ISR_RX_TX_CAUSE_REG(port->id), 4489 cause_rx_tx & ~MVPP2_CAUSE_MISC_SUM_MASK); 4490 } 4491 4492 if (port->has_tx_irqs) { 4493 cause_tx = cause_rx_tx & MVPP2_CAUSE_TXQ_OCCUP_DESC_ALL_MASK; 4494 if (cause_tx) { 4495 cause_tx >>= MVPP2_CAUSE_TXQ_OCCUP_DESC_ALL_OFFSET; 4496 mvpp2_tx_done(port, cause_tx, qv->sw_thread_id); 4497 } 4498 } 4499 4500 /* Process RX packets */ 4501 cause_rx = cause_rx_tx & 4502 MVPP2_CAUSE_RXQ_OCCUP_DESC_ALL_MASK(port->priv->hw_version); 4503 cause_rx <<= qv->first_rxq; 4504 cause_rx |= qv->pending_cause_rx; 4505 while (cause_rx && budget > 0) { 4506 int count; 4507 struct mvpp2_rx_queue *rxq; 4508 4509 rxq = mvpp2_get_rx_queue(port, cause_rx); 4510 if (!rxq) 4511 break; 4512 4513 count = mvpp2_rx(port, napi, budget, rxq); 4514 rx_done += count; 4515 budget -= count; 4516 if (budget > 0) { 4517 /* Clear the bit associated to this Rx queue 4518 * so that next iteration will continue from 4519 * the next Rx queue. 4520 */ 4521 cause_rx &= ~(1 << rxq->logic_rxq); 4522 } 4523 } 4524 4525 if (budget > 0) { 4526 cause_rx = 0; 4527 napi_complete_done(napi, rx_done); 4528 4529 mvpp2_qvec_interrupt_enable(qv); 4530 } 4531 qv->pending_cause_rx = cause_rx; 4532 return rx_done; 4533 } 4534 4535 static void mvpp22_mode_reconfigure(struct mvpp2_port *port, 4536 phy_interface_t interface) 4537 { 4538 u32 ctrl3; 4539 4540 /* Set the GMAC & XLG MAC in reset */ 4541 mvpp2_mac_reset_assert(port); 4542 4543 /* Set the MPCS and XPCS in reset */ 4544 mvpp22_pcs_reset_assert(port); 4545 4546 /* comphy reconfiguration */ 4547 mvpp22_comphy_init(port, interface); 4548 4549 /* gop reconfiguration */ 4550 mvpp22_gop_init(port, interface); 4551 4552 mvpp22_pcs_reset_deassert(port, interface); 4553 4554 if (mvpp2_port_supports_xlg(port)) { 4555 ctrl3 = readl(port->base + MVPP22_XLG_CTRL3_REG); 4556 ctrl3 &= ~MVPP22_XLG_CTRL3_MACMODESELECT_MASK; 4557 4558 if (mvpp2_is_xlg(interface)) 4559 ctrl3 |= MVPP22_XLG_CTRL3_MACMODESELECT_10G; 4560 else 4561 ctrl3 |= MVPP22_XLG_CTRL3_MACMODESELECT_GMAC; 4562 4563 writel(ctrl3, port->base + MVPP22_XLG_CTRL3_REG); 4564 } 4565 4566 if (mvpp2_port_supports_xlg(port) && mvpp2_is_xlg(interface)) 4567 mvpp2_xlg_max_rx_size_set(port); 4568 else 4569 mvpp2_gmac_max_rx_size_set(port); 4570 } 4571 4572 /* Set hw internals when starting port */ 4573 static void mvpp2_start_dev(struct mvpp2_port *port) 4574 { 4575 int i; 4576 4577 mvpp2_txp_max_tx_size_set(port); 4578 4579 for (i = 0; i < port->nqvecs; i++) 4580 napi_enable(&port->qvecs[i].napi); 4581 4582 /* Enable interrupts on all threads */ 4583 mvpp2_interrupts_enable(port); 4584 4585 if (port->priv->hw_version >= MVPP22) 4586 mvpp22_mode_reconfigure(port, port->phy_interface); 4587 4588 if (port->phylink) { 4589 phylink_start(port->phylink); 4590 } else { 4591 mvpp2_acpi_start(port); 4592 } 4593 4594 netif_tx_start_all_queues(port->dev); 4595 4596 clear_bit(0, &port->state); 4597 } 4598 4599 /* Set hw internals when stopping port */ 4600 static void mvpp2_stop_dev(struct mvpp2_port *port) 4601 { 4602 int i; 4603 4604 set_bit(0, &port->state); 4605 4606 /* Disable interrupts on all threads */ 4607 mvpp2_interrupts_disable(port); 4608 4609 for (i = 0; i < port->nqvecs; i++) 4610 napi_disable(&port->qvecs[i].napi); 4611 4612 if (port->phylink) 4613 phylink_stop(port->phylink); 4614 phy_power_off(port->comphy); 4615 } 4616 4617 static int mvpp2_check_ringparam_valid(struct net_device *dev, 4618 struct ethtool_ringparam *ring) 4619 { 4620 u16 new_rx_pending = ring->rx_pending; 4621 u16 new_tx_pending = ring->tx_pending; 4622 4623 if (ring->rx_pending == 0 || ring->tx_pending == 0) 4624 return -EINVAL; 4625 4626 if (ring->rx_pending > MVPP2_MAX_RXD_MAX) 4627 new_rx_pending = MVPP2_MAX_RXD_MAX; 4628 else if (ring->rx_pending < MSS_THRESHOLD_START) 4629 new_rx_pending = MSS_THRESHOLD_START; 4630 else if (!IS_ALIGNED(ring->rx_pending, 16)) 4631 new_rx_pending = ALIGN(ring->rx_pending, 16); 4632 4633 if (ring->tx_pending > MVPP2_MAX_TXD_MAX) 4634 new_tx_pending = MVPP2_MAX_TXD_MAX; 4635 else if (!IS_ALIGNED(ring->tx_pending, 32)) 4636 new_tx_pending = ALIGN(ring->tx_pending, 32); 4637 4638 /* The Tx ring size cannot be smaller than the minimum number of 4639 * descriptors needed for TSO. 4640 */ 4641 if (new_tx_pending < MVPP2_MAX_SKB_DESCS) 4642 new_tx_pending = ALIGN(MVPP2_MAX_SKB_DESCS, 32); 4643 4644 if (ring->rx_pending != new_rx_pending) { 4645 netdev_info(dev, "illegal Rx ring size value %d, round to %d\n", 4646 ring->rx_pending, new_rx_pending); 4647 ring->rx_pending = new_rx_pending; 4648 } 4649 4650 if (ring->tx_pending != new_tx_pending) { 4651 netdev_info(dev, "illegal Tx ring size value %d, round to %d\n", 4652 ring->tx_pending, new_tx_pending); 4653 ring->tx_pending = new_tx_pending; 4654 } 4655 4656 return 0; 4657 } 4658 4659 static void mvpp21_get_mac_address(struct mvpp2_port *port, unsigned char *addr) 4660 { 4661 u32 mac_addr_l, mac_addr_m, mac_addr_h; 4662 4663 mac_addr_l = readl(port->base + MVPP2_GMAC_CTRL_1_REG); 4664 mac_addr_m = readl(port->priv->lms_base + MVPP2_SRC_ADDR_MIDDLE); 4665 mac_addr_h = readl(port->priv->lms_base + MVPP2_SRC_ADDR_HIGH); 4666 addr[0] = (mac_addr_h >> 24) & 0xFF; 4667 addr[1] = (mac_addr_h >> 16) & 0xFF; 4668 addr[2] = (mac_addr_h >> 8) & 0xFF; 4669 addr[3] = mac_addr_h & 0xFF; 4670 addr[4] = mac_addr_m & 0xFF; 4671 addr[5] = (mac_addr_l >> MVPP2_GMAC_SA_LOW_OFFS) & 0xFF; 4672 } 4673 4674 static int mvpp2_irqs_init(struct mvpp2_port *port) 4675 { 4676 int err, i; 4677 4678 for (i = 0; i < port->nqvecs; i++) { 4679 struct mvpp2_queue_vector *qv = port->qvecs + i; 4680 4681 if (qv->type == MVPP2_QUEUE_VECTOR_PRIVATE) { 4682 qv->mask = kzalloc(cpumask_size(), GFP_KERNEL); 4683 if (!qv->mask) { 4684 err = -ENOMEM; 4685 goto err; 4686 } 4687 4688 irq_set_status_flags(qv->irq, IRQ_NO_BALANCING); 4689 } 4690 4691 err = request_irq(qv->irq, mvpp2_isr, 0, port->dev->name, qv); 4692 if (err) 4693 goto err; 4694 4695 if (qv->type == MVPP2_QUEUE_VECTOR_PRIVATE) { 4696 unsigned int cpu; 4697 4698 for_each_present_cpu(cpu) { 4699 if (mvpp2_cpu_to_thread(port->priv, cpu) == 4700 qv->sw_thread_id) 4701 cpumask_set_cpu(cpu, qv->mask); 4702 } 4703 4704 irq_set_affinity_hint(qv->irq, qv->mask); 4705 } 4706 } 4707 4708 return 0; 4709 err: 4710 for (i = 0; i < port->nqvecs; i++) { 4711 struct mvpp2_queue_vector *qv = port->qvecs + i; 4712 4713 irq_set_affinity_hint(qv->irq, NULL); 4714 kfree(qv->mask); 4715 qv->mask = NULL; 4716 free_irq(qv->irq, qv); 4717 } 4718 4719 return err; 4720 } 4721 4722 static void mvpp2_irqs_deinit(struct mvpp2_port *port) 4723 { 4724 int i; 4725 4726 for (i = 0; i < port->nqvecs; i++) { 4727 struct mvpp2_queue_vector *qv = port->qvecs + i; 4728 4729 irq_set_affinity_hint(qv->irq, NULL); 4730 kfree(qv->mask); 4731 qv->mask = NULL; 4732 irq_clear_status_flags(qv->irq, IRQ_NO_BALANCING); 4733 free_irq(qv->irq, qv); 4734 } 4735 } 4736 4737 static bool mvpp22_rss_is_supported(struct mvpp2_port *port) 4738 { 4739 return (queue_mode == MVPP2_QDIST_MULTI_MODE) && 4740 !(port->flags & MVPP2_F_LOOPBACK); 4741 } 4742 4743 static int mvpp2_open(struct net_device *dev) 4744 { 4745 struct mvpp2_port *port = netdev_priv(dev); 4746 struct mvpp2 *priv = port->priv; 4747 unsigned char mac_bcast[ETH_ALEN] = { 4748 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }; 4749 bool valid = false; 4750 int err; 4751 4752 err = mvpp2_prs_mac_da_accept(port, mac_bcast, true); 4753 if (err) { 4754 netdev_err(dev, "mvpp2_prs_mac_da_accept BC failed\n"); 4755 return err; 4756 } 4757 err = mvpp2_prs_mac_da_accept(port, dev->dev_addr, true); 4758 if (err) { 4759 netdev_err(dev, "mvpp2_prs_mac_da_accept own addr failed\n"); 4760 return err; 4761 } 4762 err = mvpp2_prs_tag_mode_set(port->priv, port->id, MVPP2_TAG_TYPE_MH); 4763 if (err) { 4764 netdev_err(dev, "mvpp2_prs_tag_mode_set failed\n"); 4765 return err; 4766 } 4767 err = mvpp2_prs_def_flow(port); 4768 if (err) { 4769 netdev_err(dev, "mvpp2_prs_def_flow failed\n"); 4770 return err; 4771 } 4772 4773 /* Allocate the Rx/Tx queues */ 4774 err = mvpp2_setup_rxqs(port); 4775 if (err) { 4776 netdev_err(port->dev, "cannot allocate Rx queues\n"); 4777 return err; 4778 } 4779 4780 err = mvpp2_setup_txqs(port); 4781 if (err) { 4782 netdev_err(port->dev, "cannot allocate Tx queues\n"); 4783 goto err_cleanup_rxqs; 4784 } 4785 4786 err = mvpp2_irqs_init(port); 4787 if (err) { 4788 netdev_err(port->dev, "cannot init IRQs\n"); 4789 goto err_cleanup_txqs; 4790 } 4791 4792 if (port->phylink) { 4793 err = phylink_fwnode_phy_connect(port->phylink, port->fwnode, 0); 4794 if (err) { 4795 netdev_err(port->dev, "could not attach PHY (%d)\n", 4796 err); 4797 goto err_free_irq; 4798 } 4799 4800 valid = true; 4801 } 4802 4803 if (priv->hw_version >= MVPP22 && port->port_irq) { 4804 err = request_irq(port->port_irq, mvpp2_port_isr, 0, 4805 dev->name, port); 4806 if (err) { 4807 netdev_err(port->dev, 4808 "cannot request port link/ptp IRQ %d\n", 4809 port->port_irq); 4810 goto err_free_irq; 4811 } 4812 4813 mvpp22_gop_setup_irq(port); 4814 4815 /* In default link is down */ 4816 netif_carrier_off(port->dev); 4817 4818 valid = true; 4819 } else { 4820 port->port_irq = 0; 4821 } 4822 4823 if (!valid) { 4824 netdev_err(port->dev, 4825 "invalid configuration: no dt or link IRQ"); 4826 err = -ENOENT; 4827 goto err_free_irq; 4828 } 4829 4830 /* Unmask interrupts on all CPUs */ 4831 on_each_cpu(mvpp2_interrupts_unmask, port, 1); 4832 mvpp2_shared_interrupt_mask_unmask(port, false); 4833 4834 mvpp2_start_dev(port); 4835 4836 /* Start hardware statistics gathering */ 4837 queue_delayed_work(priv->stats_queue, &port->stats_work, 4838 MVPP2_MIB_COUNTERS_STATS_DELAY); 4839 4840 return 0; 4841 4842 err_free_irq: 4843 mvpp2_irqs_deinit(port); 4844 err_cleanup_txqs: 4845 mvpp2_cleanup_txqs(port); 4846 err_cleanup_rxqs: 4847 mvpp2_cleanup_rxqs(port); 4848 return err; 4849 } 4850 4851 static int mvpp2_stop(struct net_device *dev) 4852 { 4853 struct mvpp2_port *port = netdev_priv(dev); 4854 struct mvpp2_port_pcpu *port_pcpu; 4855 unsigned int thread; 4856 4857 mvpp2_stop_dev(port); 4858 4859 /* Mask interrupts on all threads */ 4860 on_each_cpu(mvpp2_interrupts_mask, port, 1); 4861 mvpp2_shared_interrupt_mask_unmask(port, true); 4862 4863 if (port->phylink) 4864 phylink_disconnect_phy(port->phylink); 4865 if (port->port_irq) 4866 free_irq(port->port_irq, port); 4867 4868 mvpp2_irqs_deinit(port); 4869 if (!port->has_tx_irqs) { 4870 for (thread = 0; thread < port->priv->nthreads; thread++) { 4871 port_pcpu = per_cpu_ptr(port->pcpu, thread); 4872 4873 hrtimer_cancel(&port_pcpu->tx_done_timer); 4874 port_pcpu->timer_scheduled = false; 4875 } 4876 } 4877 mvpp2_cleanup_rxqs(port); 4878 mvpp2_cleanup_txqs(port); 4879 4880 cancel_delayed_work_sync(&port->stats_work); 4881 4882 mvpp2_mac_reset_assert(port); 4883 mvpp22_pcs_reset_assert(port); 4884 4885 return 0; 4886 } 4887 4888 static int mvpp2_prs_mac_da_accept_list(struct mvpp2_port *port, 4889 struct netdev_hw_addr_list *list) 4890 { 4891 struct netdev_hw_addr *ha; 4892 int ret; 4893 4894 netdev_hw_addr_list_for_each(ha, list) { 4895 ret = mvpp2_prs_mac_da_accept(port, ha->addr, true); 4896 if (ret) 4897 return ret; 4898 } 4899 4900 return 0; 4901 } 4902 4903 static void mvpp2_set_rx_promisc(struct mvpp2_port *port, bool enable) 4904 { 4905 if (!enable && (port->dev->features & NETIF_F_HW_VLAN_CTAG_FILTER)) 4906 mvpp2_prs_vid_enable_filtering(port); 4907 else 4908 mvpp2_prs_vid_disable_filtering(port); 4909 4910 mvpp2_prs_mac_promisc_set(port->priv, port->id, 4911 MVPP2_PRS_L2_UNI_CAST, enable); 4912 4913 mvpp2_prs_mac_promisc_set(port->priv, port->id, 4914 MVPP2_PRS_L2_MULTI_CAST, enable); 4915 } 4916 4917 static void mvpp2_set_rx_mode(struct net_device *dev) 4918 { 4919 struct mvpp2_port *port = netdev_priv(dev); 4920 4921 /* Clear the whole UC and MC list */ 4922 mvpp2_prs_mac_del_all(port); 4923 4924 if (dev->flags & IFF_PROMISC) { 4925 mvpp2_set_rx_promisc(port, true); 4926 return; 4927 } 4928 4929 mvpp2_set_rx_promisc(port, false); 4930 4931 if (netdev_uc_count(dev) > MVPP2_PRS_MAC_UC_FILT_MAX || 4932 mvpp2_prs_mac_da_accept_list(port, &dev->uc)) 4933 mvpp2_prs_mac_promisc_set(port->priv, port->id, 4934 MVPP2_PRS_L2_UNI_CAST, true); 4935 4936 if (dev->flags & IFF_ALLMULTI) { 4937 mvpp2_prs_mac_promisc_set(port->priv, port->id, 4938 MVPP2_PRS_L2_MULTI_CAST, true); 4939 return; 4940 } 4941 4942 if (netdev_mc_count(dev) > MVPP2_PRS_MAC_MC_FILT_MAX || 4943 mvpp2_prs_mac_da_accept_list(port, &dev->mc)) 4944 mvpp2_prs_mac_promisc_set(port->priv, port->id, 4945 MVPP2_PRS_L2_MULTI_CAST, true); 4946 } 4947 4948 static int mvpp2_set_mac_address(struct net_device *dev, void *p) 4949 { 4950 const struct sockaddr *addr = p; 4951 int err; 4952 4953 if (!is_valid_ether_addr(addr->sa_data)) 4954 return -EADDRNOTAVAIL; 4955 4956 err = mvpp2_prs_update_mac_da(dev, addr->sa_data); 4957 if (err) { 4958 /* Reconfigure parser accept the original MAC address */ 4959 mvpp2_prs_update_mac_da(dev, dev->dev_addr); 4960 netdev_err(dev, "failed to change MAC address\n"); 4961 } 4962 return err; 4963 } 4964 4965 /* Shut down all the ports, reconfigure the pools as percpu or shared, 4966 * then bring up again all ports. 4967 */ 4968 static int mvpp2_bm_switch_buffers(struct mvpp2 *priv, bool percpu) 4969 { 4970 bool change_percpu = (percpu != priv->percpu_pools); 4971 int numbufs = MVPP2_BM_POOLS_NUM, i; 4972 struct mvpp2_port *port = NULL; 4973 bool status[MVPP2_MAX_PORTS]; 4974 4975 for (i = 0; i < priv->port_count; i++) { 4976 port = priv->port_list[i]; 4977 status[i] = netif_running(port->dev); 4978 if (status[i]) 4979 mvpp2_stop(port->dev); 4980 } 4981 4982 /* nrxqs is the same for all ports */ 4983 if (priv->percpu_pools) 4984 numbufs = port->nrxqs * 2; 4985 4986 if (change_percpu) 4987 mvpp2_bm_pool_update_priv_fc(priv, false); 4988 4989 for (i = 0; i < numbufs; i++) 4990 mvpp2_bm_pool_destroy(port->dev->dev.parent, priv, &priv->bm_pools[i]); 4991 4992 devm_kfree(port->dev->dev.parent, priv->bm_pools); 4993 priv->percpu_pools = percpu; 4994 mvpp2_bm_init(port->dev->dev.parent, priv); 4995 4996 for (i = 0; i < priv->port_count; i++) { 4997 port = priv->port_list[i]; 4998 if (percpu && port->ntxqs >= num_possible_cpus() * 2) 4999 xdp_set_features_flag(port->dev, 5000 NETDEV_XDP_ACT_BASIC | 5001 NETDEV_XDP_ACT_REDIRECT | 5002 NETDEV_XDP_ACT_NDO_XMIT); 5003 else 5004 xdp_clear_features_flag(port->dev); 5005 5006 mvpp2_swf_bm_pool_init(port); 5007 if (status[i]) 5008 mvpp2_open(port->dev); 5009 } 5010 5011 if (change_percpu) 5012 mvpp2_bm_pool_update_priv_fc(priv, true); 5013 5014 return 0; 5015 } 5016 5017 static int mvpp2_change_mtu(struct net_device *dev, int mtu) 5018 { 5019 struct mvpp2_port *port = netdev_priv(dev); 5020 bool running = netif_running(dev); 5021 struct mvpp2 *priv = port->priv; 5022 int err; 5023 5024 if (!IS_ALIGNED(MVPP2_RX_PKT_SIZE(mtu), 8)) { 5025 netdev_info(dev, "illegal MTU value %d, round to %d\n", mtu, 5026 ALIGN(MVPP2_RX_PKT_SIZE(mtu), 8)); 5027 mtu = ALIGN(MVPP2_RX_PKT_SIZE(mtu), 8); 5028 } 5029 5030 if (port->xdp_prog && mtu > MVPP2_MAX_RX_BUF_SIZE) { 5031 netdev_err(dev, "Illegal MTU value %d (> %d) for XDP mode\n", 5032 mtu, (int)MVPP2_MAX_RX_BUF_SIZE); 5033 return -EINVAL; 5034 } 5035 5036 if (MVPP2_RX_PKT_SIZE(mtu) > MVPP2_BM_LONG_PKT_SIZE) { 5037 if (priv->percpu_pools) { 5038 netdev_warn(dev, "mtu %d too high, switching to shared buffers", mtu); 5039 mvpp2_bm_switch_buffers(priv, false); 5040 } 5041 } else { 5042 bool jumbo = false; 5043 int i; 5044 5045 for (i = 0; i < priv->port_count; i++) 5046 if (priv->port_list[i] != port && 5047 MVPP2_RX_PKT_SIZE(priv->port_list[i]->dev->mtu) > 5048 MVPP2_BM_LONG_PKT_SIZE) { 5049 jumbo = true; 5050 break; 5051 } 5052 5053 /* No port is using jumbo frames */ 5054 if (!jumbo) { 5055 dev_info(port->dev->dev.parent, 5056 "all ports have a low MTU, switching to per-cpu buffers"); 5057 mvpp2_bm_switch_buffers(priv, true); 5058 } 5059 } 5060 5061 if (running) 5062 mvpp2_stop_dev(port); 5063 5064 err = mvpp2_bm_update_mtu(dev, mtu); 5065 if (err) { 5066 netdev_err(dev, "failed to change MTU\n"); 5067 /* Reconfigure BM to the original MTU */ 5068 mvpp2_bm_update_mtu(dev, dev->mtu); 5069 } else { 5070 port->pkt_size = MVPP2_RX_PKT_SIZE(mtu); 5071 } 5072 5073 if (running) { 5074 mvpp2_start_dev(port); 5075 mvpp2_egress_enable(port); 5076 mvpp2_ingress_enable(port); 5077 } 5078 5079 return err; 5080 } 5081 5082 static int mvpp2_check_pagepool_dma(struct mvpp2_port *port) 5083 { 5084 enum dma_data_direction dma_dir = DMA_FROM_DEVICE; 5085 struct mvpp2 *priv = port->priv; 5086 int err = -1, i; 5087 5088 if (!priv->percpu_pools) 5089 return err; 5090 5091 if (!priv->page_pool[0]) 5092 return -ENOMEM; 5093 5094 for (i = 0; i < priv->port_count; i++) { 5095 port = priv->port_list[i]; 5096 if (port->xdp_prog) { 5097 dma_dir = DMA_BIDIRECTIONAL; 5098 break; 5099 } 5100 } 5101 5102 /* All pools are equal in terms of DMA direction */ 5103 if (priv->page_pool[0]->p.dma_dir != dma_dir) 5104 err = mvpp2_bm_switch_buffers(priv, true); 5105 5106 return err; 5107 } 5108 5109 static void 5110 mvpp2_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats) 5111 { 5112 struct mvpp2_port *port = netdev_priv(dev); 5113 unsigned int start; 5114 unsigned int cpu; 5115 5116 for_each_possible_cpu(cpu) { 5117 struct mvpp2_pcpu_stats *cpu_stats; 5118 u64 rx_packets; 5119 u64 rx_bytes; 5120 u64 tx_packets; 5121 u64 tx_bytes; 5122 5123 cpu_stats = per_cpu_ptr(port->stats, cpu); 5124 do { 5125 start = u64_stats_fetch_begin(&cpu_stats->syncp); 5126 rx_packets = cpu_stats->rx_packets; 5127 rx_bytes = cpu_stats->rx_bytes; 5128 tx_packets = cpu_stats->tx_packets; 5129 tx_bytes = cpu_stats->tx_bytes; 5130 } while (u64_stats_fetch_retry(&cpu_stats->syncp, start)); 5131 5132 stats->rx_packets += rx_packets; 5133 stats->rx_bytes += rx_bytes; 5134 stats->tx_packets += tx_packets; 5135 stats->tx_bytes += tx_bytes; 5136 } 5137 5138 stats->rx_errors = dev->stats.rx_errors; 5139 stats->rx_dropped = dev->stats.rx_dropped; 5140 stats->tx_dropped = dev->stats.tx_dropped; 5141 } 5142 5143 static int mvpp2_set_ts_config(struct mvpp2_port *port, struct ifreq *ifr) 5144 { 5145 struct hwtstamp_config config; 5146 void __iomem *ptp; 5147 u32 gcr, int_mask; 5148 5149 if (copy_from_user(&config, ifr->ifr_data, sizeof(config))) 5150 return -EFAULT; 5151 5152 if (config.tx_type != HWTSTAMP_TX_OFF && 5153 config.tx_type != HWTSTAMP_TX_ON) 5154 return -ERANGE; 5155 5156 ptp = port->priv->iface_base + MVPP22_PTP_BASE(port->gop_id); 5157 5158 int_mask = gcr = 0; 5159 if (config.tx_type != HWTSTAMP_TX_OFF) { 5160 gcr |= MVPP22_PTP_GCR_TSU_ENABLE | MVPP22_PTP_GCR_TX_RESET; 5161 int_mask |= MVPP22_PTP_INT_MASK_QUEUE1 | 5162 MVPP22_PTP_INT_MASK_QUEUE0; 5163 } 5164 5165 /* It seems we must also release the TX reset when enabling the TSU */ 5166 if (config.rx_filter != HWTSTAMP_FILTER_NONE) 5167 gcr |= MVPP22_PTP_GCR_TSU_ENABLE | MVPP22_PTP_GCR_RX_RESET | 5168 MVPP22_PTP_GCR_TX_RESET; 5169 5170 if (gcr & MVPP22_PTP_GCR_TSU_ENABLE) 5171 mvpp22_tai_start(port->priv->tai); 5172 5173 if (config.rx_filter != HWTSTAMP_FILTER_NONE) { 5174 config.rx_filter = HWTSTAMP_FILTER_ALL; 5175 mvpp2_modify(ptp + MVPP22_PTP_GCR, 5176 MVPP22_PTP_GCR_RX_RESET | 5177 MVPP22_PTP_GCR_TX_RESET | 5178 MVPP22_PTP_GCR_TSU_ENABLE, gcr); 5179 port->rx_hwtstamp = true; 5180 } else { 5181 port->rx_hwtstamp = false; 5182 mvpp2_modify(ptp + MVPP22_PTP_GCR, 5183 MVPP22_PTP_GCR_RX_RESET | 5184 MVPP22_PTP_GCR_TX_RESET | 5185 MVPP22_PTP_GCR_TSU_ENABLE, gcr); 5186 } 5187 5188 mvpp2_modify(ptp + MVPP22_PTP_INT_MASK, 5189 MVPP22_PTP_INT_MASK_QUEUE1 | 5190 MVPP22_PTP_INT_MASK_QUEUE0, int_mask); 5191 5192 if (!(gcr & MVPP22_PTP_GCR_TSU_ENABLE)) 5193 mvpp22_tai_stop(port->priv->tai); 5194 5195 port->tx_hwtstamp_type = config.tx_type; 5196 5197 if (copy_to_user(ifr->ifr_data, &config, sizeof(config))) 5198 return -EFAULT; 5199 5200 return 0; 5201 } 5202 5203 static int mvpp2_get_ts_config(struct mvpp2_port *port, struct ifreq *ifr) 5204 { 5205 struct hwtstamp_config config; 5206 5207 memset(&config, 0, sizeof(config)); 5208 5209 config.tx_type = port->tx_hwtstamp_type; 5210 config.rx_filter = port->rx_hwtstamp ? 5211 HWTSTAMP_FILTER_ALL : HWTSTAMP_FILTER_NONE; 5212 5213 if (copy_to_user(ifr->ifr_data, &config, sizeof(config))) 5214 return -EFAULT; 5215 5216 return 0; 5217 } 5218 5219 static int mvpp2_ethtool_get_ts_info(struct net_device *dev, 5220 struct ethtool_ts_info *info) 5221 { 5222 struct mvpp2_port *port = netdev_priv(dev); 5223 5224 if (!port->hwtstamp) 5225 return -EOPNOTSUPP; 5226 5227 info->phc_index = mvpp22_tai_ptp_clock_index(port->priv->tai); 5228 info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE | 5229 SOF_TIMESTAMPING_RX_SOFTWARE | 5230 SOF_TIMESTAMPING_SOFTWARE | 5231 SOF_TIMESTAMPING_TX_HARDWARE | 5232 SOF_TIMESTAMPING_RX_HARDWARE | 5233 SOF_TIMESTAMPING_RAW_HARDWARE; 5234 info->tx_types = BIT(HWTSTAMP_TX_OFF) | 5235 BIT(HWTSTAMP_TX_ON); 5236 info->rx_filters = BIT(HWTSTAMP_FILTER_NONE) | 5237 BIT(HWTSTAMP_FILTER_ALL); 5238 5239 return 0; 5240 } 5241 5242 static int mvpp2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) 5243 { 5244 struct mvpp2_port *port = netdev_priv(dev); 5245 5246 switch (cmd) { 5247 case SIOCSHWTSTAMP: 5248 if (port->hwtstamp) 5249 return mvpp2_set_ts_config(port, ifr); 5250 break; 5251 5252 case SIOCGHWTSTAMP: 5253 if (port->hwtstamp) 5254 return mvpp2_get_ts_config(port, ifr); 5255 break; 5256 } 5257 5258 if (!port->phylink) 5259 return -ENOTSUPP; 5260 5261 return phylink_mii_ioctl(port->phylink, ifr, cmd); 5262 } 5263 5264 static int mvpp2_vlan_rx_add_vid(struct net_device *dev, __be16 proto, u16 vid) 5265 { 5266 struct mvpp2_port *port = netdev_priv(dev); 5267 int ret; 5268 5269 ret = mvpp2_prs_vid_entry_add(port, vid); 5270 if (ret) 5271 netdev_err(dev, "rx-vlan-filter offloading cannot accept more than %d VIDs per port\n", 5272 MVPP2_PRS_VLAN_FILT_MAX - 1); 5273 return ret; 5274 } 5275 5276 static int mvpp2_vlan_rx_kill_vid(struct net_device *dev, __be16 proto, u16 vid) 5277 { 5278 struct mvpp2_port *port = netdev_priv(dev); 5279 5280 mvpp2_prs_vid_entry_remove(port, vid); 5281 return 0; 5282 } 5283 5284 static int mvpp2_set_features(struct net_device *dev, 5285 netdev_features_t features) 5286 { 5287 netdev_features_t changed = dev->features ^ features; 5288 struct mvpp2_port *port = netdev_priv(dev); 5289 5290 if (changed & NETIF_F_HW_VLAN_CTAG_FILTER) { 5291 if (features & NETIF_F_HW_VLAN_CTAG_FILTER) { 5292 mvpp2_prs_vid_enable_filtering(port); 5293 } else { 5294 /* Invalidate all registered VID filters for this 5295 * port 5296 */ 5297 mvpp2_prs_vid_remove_all(port); 5298 5299 mvpp2_prs_vid_disable_filtering(port); 5300 } 5301 } 5302 5303 if (changed & NETIF_F_RXHASH) { 5304 if (features & NETIF_F_RXHASH) 5305 mvpp22_port_rss_enable(port); 5306 else 5307 mvpp22_port_rss_disable(port); 5308 } 5309 5310 return 0; 5311 } 5312 5313 static int mvpp2_xdp_setup(struct mvpp2_port *port, struct netdev_bpf *bpf) 5314 { 5315 struct bpf_prog *prog = bpf->prog, *old_prog; 5316 bool running = netif_running(port->dev); 5317 bool reset = !prog != !port->xdp_prog; 5318 5319 if (port->dev->mtu > MVPP2_MAX_RX_BUF_SIZE) { 5320 NL_SET_ERR_MSG_MOD(bpf->extack, "MTU too large for XDP"); 5321 return -EOPNOTSUPP; 5322 } 5323 5324 if (!port->priv->percpu_pools) { 5325 NL_SET_ERR_MSG_MOD(bpf->extack, "Per CPU Pools required for XDP"); 5326 return -EOPNOTSUPP; 5327 } 5328 5329 if (port->ntxqs < num_possible_cpus() * 2) { 5330 NL_SET_ERR_MSG_MOD(bpf->extack, "XDP_TX needs two TX queues per CPU"); 5331 return -EOPNOTSUPP; 5332 } 5333 5334 /* device is up and bpf is added/removed, must setup the RX queues */ 5335 if (running && reset) 5336 mvpp2_stop(port->dev); 5337 5338 old_prog = xchg(&port->xdp_prog, prog); 5339 if (old_prog) 5340 bpf_prog_put(old_prog); 5341 5342 /* bpf is just replaced, RXQ and MTU are already setup */ 5343 if (!reset) 5344 return 0; 5345 5346 /* device was up, restore the link */ 5347 if (running) 5348 mvpp2_open(port->dev); 5349 5350 /* Check Page Pool DMA Direction */ 5351 mvpp2_check_pagepool_dma(port); 5352 5353 return 0; 5354 } 5355 5356 static int mvpp2_xdp(struct net_device *dev, struct netdev_bpf *xdp) 5357 { 5358 struct mvpp2_port *port = netdev_priv(dev); 5359 5360 switch (xdp->command) { 5361 case XDP_SETUP_PROG: 5362 return mvpp2_xdp_setup(port, xdp); 5363 default: 5364 return -EINVAL; 5365 } 5366 } 5367 5368 /* Ethtool methods */ 5369 5370 static int mvpp2_ethtool_nway_reset(struct net_device *dev) 5371 { 5372 struct mvpp2_port *port = netdev_priv(dev); 5373 5374 if (!port->phylink) 5375 return -ENOTSUPP; 5376 5377 return phylink_ethtool_nway_reset(port->phylink); 5378 } 5379 5380 /* Set interrupt coalescing for ethtools */ 5381 static int 5382 mvpp2_ethtool_set_coalesce(struct net_device *dev, 5383 struct ethtool_coalesce *c, 5384 struct kernel_ethtool_coalesce *kernel_coal, 5385 struct netlink_ext_ack *extack) 5386 { 5387 struct mvpp2_port *port = netdev_priv(dev); 5388 int queue; 5389 5390 for (queue = 0; queue < port->nrxqs; queue++) { 5391 struct mvpp2_rx_queue *rxq = port->rxqs[queue]; 5392 5393 rxq->time_coal = c->rx_coalesce_usecs; 5394 rxq->pkts_coal = c->rx_max_coalesced_frames; 5395 mvpp2_rx_pkts_coal_set(port, rxq); 5396 mvpp2_rx_time_coal_set(port, rxq); 5397 } 5398 5399 if (port->has_tx_irqs) { 5400 port->tx_time_coal = c->tx_coalesce_usecs; 5401 mvpp2_tx_time_coal_set(port); 5402 } 5403 5404 for (queue = 0; queue < port->ntxqs; queue++) { 5405 struct mvpp2_tx_queue *txq = port->txqs[queue]; 5406 5407 txq->done_pkts_coal = c->tx_max_coalesced_frames; 5408 5409 if (port->has_tx_irqs) 5410 mvpp2_tx_pkts_coal_set(port, txq); 5411 } 5412 5413 return 0; 5414 } 5415 5416 /* get coalescing for ethtools */ 5417 static int 5418 mvpp2_ethtool_get_coalesce(struct net_device *dev, 5419 struct ethtool_coalesce *c, 5420 struct kernel_ethtool_coalesce *kernel_coal, 5421 struct netlink_ext_ack *extack) 5422 { 5423 struct mvpp2_port *port = netdev_priv(dev); 5424 5425 c->rx_coalesce_usecs = port->rxqs[0]->time_coal; 5426 c->rx_max_coalesced_frames = port->rxqs[0]->pkts_coal; 5427 c->tx_max_coalesced_frames = port->txqs[0]->done_pkts_coal; 5428 c->tx_coalesce_usecs = port->tx_time_coal; 5429 return 0; 5430 } 5431 5432 static void mvpp2_ethtool_get_drvinfo(struct net_device *dev, 5433 struct ethtool_drvinfo *drvinfo) 5434 { 5435 strscpy(drvinfo->driver, MVPP2_DRIVER_NAME, 5436 sizeof(drvinfo->driver)); 5437 strscpy(drvinfo->version, MVPP2_DRIVER_VERSION, 5438 sizeof(drvinfo->version)); 5439 strscpy(drvinfo->bus_info, dev_name(&dev->dev), 5440 sizeof(drvinfo->bus_info)); 5441 } 5442 5443 static void 5444 mvpp2_ethtool_get_ringparam(struct net_device *dev, 5445 struct ethtool_ringparam *ring, 5446 struct kernel_ethtool_ringparam *kernel_ring, 5447 struct netlink_ext_ack *extack) 5448 { 5449 struct mvpp2_port *port = netdev_priv(dev); 5450 5451 ring->rx_max_pending = MVPP2_MAX_RXD_MAX; 5452 ring->tx_max_pending = MVPP2_MAX_TXD_MAX; 5453 ring->rx_pending = port->rx_ring_size; 5454 ring->tx_pending = port->tx_ring_size; 5455 } 5456 5457 static int 5458 mvpp2_ethtool_set_ringparam(struct net_device *dev, 5459 struct ethtool_ringparam *ring, 5460 struct kernel_ethtool_ringparam *kernel_ring, 5461 struct netlink_ext_ack *extack) 5462 { 5463 struct mvpp2_port *port = netdev_priv(dev); 5464 u16 prev_rx_ring_size = port->rx_ring_size; 5465 u16 prev_tx_ring_size = port->tx_ring_size; 5466 int err; 5467 5468 err = mvpp2_check_ringparam_valid(dev, ring); 5469 if (err) 5470 return err; 5471 5472 if (!netif_running(dev)) { 5473 port->rx_ring_size = ring->rx_pending; 5474 port->tx_ring_size = ring->tx_pending; 5475 return 0; 5476 } 5477 5478 /* The interface is running, so we have to force a 5479 * reallocation of the queues 5480 */ 5481 mvpp2_stop_dev(port); 5482 mvpp2_cleanup_rxqs(port); 5483 mvpp2_cleanup_txqs(port); 5484 5485 port->rx_ring_size = ring->rx_pending; 5486 port->tx_ring_size = ring->tx_pending; 5487 5488 err = mvpp2_setup_rxqs(port); 5489 if (err) { 5490 /* Reallocate Rx queues with the original ring size */ 5491 port->rx_ring_size = prev_rx_ring_size; 5492 ring->rx_pending = prev_rx_ring_size; 5493 err = mvpp2_setup_rxqs(port); 5494 if (err) 5495 goto err_out; 5496 } 5497 err = mvpp2_setup_txqs(port); 5498 if (err) { 5499 /* Reallocate Tx queues with the original ring size */ 5500 port->tx_ring_size = prev_tx_ring_size; 5501 ring->tx_pending = prev_tx_ring_size; 5502 err = mvpp2_setup_txqs(port); 5503 if (err) 5504 goto err_clean_rxqs; 5505 } 5506 5507 mvpp2_start_dev(port); 5508 mvpp2_egress_enable(port); 5509 mvpp2_ingress_enable(port); 5510 5511 return 0; 5512 5513 err_clean_rxqs: 5514 mvpp2_cleanup_rxqs(port); 5515 err_out: 5516 netdev_err(dev, "failed to change ring parameters"); 5517 return err; 5518 } 5519 5520 static void mvpp2_ethtool_get_pause_param(struct net_device *dev, 5521 struct ethtool_pauseparam *pause) 5522 { 5523 struct mvpp2_port *port = netdev_priv(dev); 5524 5525 if (!port->phylink) 5526 return; 5527 5528 phylink_ethtool_get_pauseparam(port->phylink, pause); 5529 } 5530 5531 static int mvpp2_ethtool_set_pause_param(struct net_device *dev, 5532 struct ethtool_pauseparam *pause) 5533 { 5534 struct mvpp2_port *port = netdev_priv(dev); 5535 5536 if (!port->phylink) 5537 return -ENOTSUPP; 5538 5539 return phylink_ethtool_set_pauseparam(port->phylink, pause); 5540 } 5541 5542 static int mvpp2_ethtool_get_link_ksettings(struct net_device *dev, 5543 struct ethtool_link_ksettings *cmd) 5544 { 5545 struct mvpp2_port *port = netdev_priv(dev); 5546 5547 if (!port->phylink) 5548 return -ENOTSUPP; 5549 5550 return phylink_ethtool_ksettings_get(port->phylink, cmd); 5551 } 5552 5553 static int mvpp2_ethtool_set_link_ksettings(struct net_device *dev, 5554 const struct ethtool_link_ksettings *cmd) 5555 { 5556 struct mvpp2_port *port = netdev_priv(dev); 5557 5558 if (!port->phylink) 5559 return -ENOTSUPP; 5560 5561 return phylink_ethtool_ksettings_set(port->phylink, cmd); 5562 } 5563 5564 static int mvpp2_ethtool_get_rxnfc(struct net_device *dev, 5565 struct ethtool_rxnfc *info, u32 *rules) 5566 { 5567 struct mvpp2_port *port = netdev_priv(dev); 5568 int ret = 0, i, loc = 0; 5569 5570 if (!mvpp22_rss_is_supported(port)) 5571 return -EOPNOTSUPP; 5572 5573 switch (info->cmd) { 5574 case ETHTOOL_GRXFH: 5575 ret = mvpp2_ethtool_rxfh_get(port, info); 5576 break; 5577 case ETHTOOL_GRXRINGS: 5578 info->data = port->nrxqs; 5579 break; 5580 case ETHTOOL_GRXCLSRLCNT: 5581 info->rule_cnt = port->n_rfs_rules; 5582 break; 5583 case ETHTOOL_GRXCLSRULE: 5584 ret = mvpp2_ethtool_cls_rule_get(port, info); 5585 break; 5586 case ETHTOOL_GRXCLSRLALL: 5587 for (i = 0; i < MVPP2_N_RFS_ENTRIES_PER_FLOW; i++) { 5588 if (port->rfs_rules[i]) 5589 rules[loc++] = i; 5590 } 5591 break; 5592 default: 5593 return -ENOTSUPP; 5594 } 5595 5596 return ret; 5597 } 5598 5599 static int mvpp2_ethtool_set_rxnfc(struct net_device *dev, 5600 struct ethtool_rxnfc *info) 5601 { 5602 struct mvpp2_port *port = netdev_priv(dev); 5603 int ret = 0; 5604 5605 if (!mvpp22_rss_is_supported(port)) 5606 return -EOPNOTSUPP; 5607 5608 switch (info->cmd) { 5609 case ETHTOOL_SRXFH: 5610 ret = mvpp2_ethtool_rxfh_set(port, info); 5611 break; 5612 case ETHTOOL_SRXCLSRLINS: 5613 ret = mvpp2_ethtool_cls_rule_ins(port, info); 5614 break; 5615 case ETHTOOL_SRXCLSRLDEL: 5616 ret = mvpp2_ethtool_cls_rule_del(port, info); 5617 break; 5618 default: 5619 return -EOPNOTSUPP; 5620 } 5621 return ret; 5622 } 5623 5624 static u32 mvpp2_ethtool_get_rxfh_indir_size(struct net_device *dev) 5625 { 5626 struct mvpp2_port *port = netdev_priv(dev); 5627 5628 return mvpp22_rss_is_supported(port) ? MVPP22_RSS_TABLE_ENTRIES : 0; 5629 } 5630 5631 static int mvpp2_ethtool_get_rxfh(struct net_device *dev, u32 *indir, u8 *key, 5632 u8 *hfunc) 5633 { 5634 struct mvpp2_port *port = netdev_priv(dev); 5635 int ret = 0; 5636 5637 if (!mvpp22_rss_is_supported(port)) 5638 return -EOPNOTSUPP; 5639 5640 if (indir) 5641 ret = mvpp22_port_rss_ctx_indir_get(port, 0, indir); 5642 5643 if (hfunc) 5644 *hfunc = ETH_RSS_HASH_CRC32; 5645 5646 return ret; 5647 } 5648 5649 static int mvpp2_ethtool_set_rxfh(struct net_device *dev, const u32 *indir, 5650 const u8 *key, const u8 hfunc) 5651 { 5652 struct mvpp2_port *port = netdev_priv(dev); 5653 int ret = 0; 5654 5655 if (!mvpp22_rss_is_supported(port)) 5656 return -EOPNOTSUPP; 5657 5658 if (hfunc != ETH_RSS_HASH_NO_CHANGE && hfunc != ETH_RSS_HASH_CRC32) 5659 return -EOPNOTSUPP; 5660 5661 if (key) 5662 return -EOPNOTSUPP; 5663 5664 if (indir) 5665 ret = mvpp22_port_rss_ctx_indir_set(port, 0, indir); 5666 5667 return ret; 5668 } 5669 5670 static int mvpp2_ethtool_get_rxfh_context(struct net_device *dev, u32 *indir, 5671 u8 *key, u8 *hfunc, u32 rss_context) 5672 { 5673 struct mvpp2_port *port = netdev_priv(dev); 5674 int ret = 0; 5675 5676 if (!mvpp22_rss_is_supported(port)) 5677 return -EOPNOTSUPP; 5678 if (rss_context >= MVPP22_N_RSS_TABLES) 5679 return -EINVAL; 5680 5681 if (hfunc) 5682 *hfunc = ETH_RSS_HASH_CRC32; 5683 5684 if (indir) 5685 ret = mvpp22_port_rss_ctx_indir_get(port, rss_context, indir); 5686 5687 return ret; 5688 } 5689 5690 static int mvpp2_ethtool_set_rxfh_context(struct net_device *dev, 5691 const u32 *indir, const u8 *key, 5692 const u8 hfunc, u32 *rss_context, 5693 bool delete) 5694 { 5695 struct mvpp2_port *port = netdev_priv(dev); 5696 int ret; 5697 5698 if (!mvpp22_rss_is_supported(port)) 5699 return -EOPNOTSUPP; 5700 5701 if (hfunc != ETH_RSS_HASH_NO_CHANGE && hfunc != ETH_RSS_HASH_CRC32) 5702 return -EOPNOTSUPP; 5703 5704 if (key) 5705 return -EOPNOTSUPP; 5706 5707 if (delete) 5708 return mvpp22_port_rss_ctx_delete(port, *rss_context); 5709 5710 if (*rss_context == ETH_RXFH_CONTEXT_ALLOC) { 5711 ret = mvpp22_port_rss_ctx_create(port, rss_context); 5712 if (ret) 5713 return ret; 5714 } 5715 5716 return mvpp22_port_rss_ctx_indir_set(port, *rss_context, indir); 5717 } 5718 /* Device ops */ 5719 5720 static const struct net_device_ops mvpp2_netdev_ops = { 5721 .ndo_open = mvpp2_open, 5722 .ndo_stop = mvpp2_stop, 5723 .ndo_start_xmit = mvpp2_tx, 5724 .ndo_set_rx_mode = mvpp2_set_rx_mode, 5725 .ndo_set_mac_address = mvpp2_set_mac_address, 5726 .ndo_change_mtu = mvpp2_change_mtu, 5727 .ndo_get_stats64 = mvpp2_get_stats64, 5728 .ndo_eth_ioctl = mvpp2_ioctl, 5729 .ndo_vlan_rx_add_vid = mvpp2_vlan_rx_add_vid, 5730 .ndo_vlan_rx_kill_vid = mvpp2_vlan_rx_kill_vid, 5731 .ndo_set_features = mvpp2_set_features, 5732 .ndo_bpf = mvpp2_xdp, 5733 .ndo_xdp_xmit = mvpp2_xdp_xmit, 5734 }; 5735 5736 static const struct ethtool_ops mvpp2_eth_tool_ops = { 5737 .supported_coalesce_params = ETHTOOL_COALESCE_USECS | 5738 ETHTOOL_COALESCE_MAX_FRAMES, 5739 .nway_reset = mvpp2_ethtool_nway_reset, 5740 .get_link = ethtool_op_get_link, 5741 .get_ts_info = mvpp2_ethtool_get_ts_info, 5742 .set_coalesce = mvpp2_ethtool_set_coalesce, 5743 .get_coalesce = mvpp2_ethtool_get_coalesce, 5744 .get_drvinfo = mvpp2_ethtool_get_drvinfo, 5745 .get_ringparam = mvpp2_ethtool_get_ringparam, 5746 .set_ringparam = mvpp2_ethtool_set_ringparam, 5747 .get_strings = mvpp2_ethtool_get_strings, 5748 .get_ethtool_stats = mvpp2_ethtool_get_stats, 5749 .get_sset_count = mvpp2_ethtool_get_sset_count, 5750 .get_pauseparam = mvpp2_ethtool_get_pause_param, 5751 .set_pauseparam = mvpp2_ethtool_set_pause_param, 5752 .get_link_ksettings = mvpp2_ethtool_get_link_ksettings, 5753 .set_link_ksettings = mvpp2_ethtool_set_link_ksettings, 5754 .get_rxnfc = mvpp2_ethtool_get_rxnfc, 5755 .set_rxnfc = mvpp2_ethtool_set_rxnfc, 5756 .get_rxfh_indir_size = mvpp2_ethtool_get_rxfh_indir_size, 5757 .get_rxfh = mvpp2_ethtool_get_rxfh, 5758 .set_rxfh = mvpp2_ethtool_set_rxfh, 5759 .get_rxfh_context = mvpp2_ethtool_get_rxfh_context, 5760 .set_rxfh_context = mvpp2_ethtool_set_rxfh_context, 5761 }; 5762 5763 /* Used for PPv2.1, or PPv2.2 with the old Device Tree binding that 5764 * had a single IRQ defined per-port. 5765 */ 5766 static int mvpp2_simple_queue_vectors_init(struct mvpp2_port *port, 5767 struct device_node *port_node) 5768 { 5769 struct mvpp2_queue_vector *v = &port->qvecs[0]; 5770 5771 v->first_rxq = 0; 5772 v->nrxqs = port->nrxqs; 5773 v->type = MVPP2_QUEUE_VECTOR_SHARED; 5774 v->sw_thread_id = 0; 5775 v->sw_thread_mask = *cpumask_bits(cpu_online_mask); 5776 v->port = port; 5777 v->irq = irq_of_parse_and_map(port_node, 0); 5778 if (v->irq <= 0) 5779 return -EINVAL; 5780 netif_napi_add(port->dev, &v->napi, mvpp2_poll); 5781 5782 port->nqvecs = 1; 5783 5784 return 0; 5785 } 5786 5787 static int mvpp2_multi_queue_vectors_init(struct mvpp2_port *port, 5788 struct device_node *port_node) 5789 { 5790 struct mvpp2 *priv = port->priv; 5791 struct mvpp2_queue_vector *v; 5792 int i, ret; 5793 5794 switch (queue_mode) { 5795 case MVPP2_QDIST_SINGLE_MODE: 5796 port->nqvecs = priv->nthreads + 1; 5797 break; 5798 case MVPP2_QDIST_MULTI_MODE: 5799 port->nqvecs = priv->nthreads; 5800 break; 5801 } 5802 5803 for (i = 0; i < port->nqvecs; i++) { 5804 char irqname[16]; 5805 5806 v = port->qvecs + i; 5807 5808 v->port = port; 5809 v->type = MVPP2_QUEUE_VECTOR_PRIVATE; 5810 v->sw_thread_id = i; 5811 v->sw_thread_mask = BIT(i); 5812 5813 if (port->flags & MVPP2_F_DT_COMPAT) 5814 snprintf(irqname, sizeof(irqname), "tx-cpu%d", i); 5815 else 5816 snprintf(irqname, sizeof(irqname), "hif%d", i); 5817 5818 if (queue_mode == MVPP2_QDIST_MULTI_MODE) { 5819 v->first_rxq = i; 5820 v->nrxqs = 1; 5821 } else if (queue_mode == MVPP2_QDIST_SINGLE_MODE && 5822 i == (port->nqvecs - 1)) { 5823 v->first_rxq = 0; 5824 v->nrxqs = port->nrxqs; 5825 v->type = MVPP2_QUEUE_VECTOR_SHARED; 5826 5827 if (port->flags & MVPP2_F_DT_COMPAT) 5828 strncpy(irqname, "rx-shared", sizeof(irqname)); 5829 } 5830 5831 if (port_node) 5832 v->irq = of_irq_get_byname(port_node, irqname); 5833 else 5834 v->irq = fwnode_irq_get(port->fwnode, i); 5835 if (v->irq <= 0) { 5836 ret = -EINVAL; 5837 goto err; 5838 } 5839 5840 netif_napi_add(port->dev, &v->napi, mvpp2_poll); 5841 } 5842 5843 return 0; 5844 5845 err: 5846 for (i = 0; i < port->nqvecs; i++) 5847 irq_dispose_mapping(port->qvecs[i].irq); 5848 return ret; 5849 } 5850 5851 static int mvpp2_queue_vectors_init(struct mvpp2_port *port, 5852 struct device_node *port_node) 5853 { 5854 if (port->has_tx_irqs) 5855 return mvpp2_multi_queue_vectors_init(port, port_node); 5856 else 5857 return mvpp2_simple_queue_vectors_init(port, port_node); 5858 } 5859 5860 static void mvpp2_queue_vectors_deinit(struct mvpp2_port *port) 5861 { 5862 int i; 5863 5864 for (i = 0; i < port->nqvecs; i++) 5865 irq_dispose_mapping(port->qvecs[i].irq); 5866 } 5867 5868 /* Configure Rx queue group interrupt for this port */ 5869 static void mvpp2_rx_irqs_setup(struct mvpp2_port *port) 5870 { 5871 struct mvpp2 *priv = port->priv; 5872 u32 val; 5873 int i; 5874 5875 if (priv->hw_version == MVPP21) { 5876 mvpp2_write(priv, MVPP21_ISR_RXQ_GROUP_REG(port->id), 5877 port->nrxqs); 5878 return; 5879 } 5880 5881 /* Handle the more complicated PPv2.2 and PPv2.3 case */ 5882 for (i = 0; i < port->nqvecs; i++) { 5883 struct mvpp2_queue_vector *qv = port->qvecs + i; 5884 5885 if (!qv->nrxqs) 5886 continue; 5887 5888 val = qv->sw_thread_id; 5889 val |= port->id << MVPP22_ISR_RXQ_GROUP_INDEX_GROUP_OFFSET; 5890 mvpp2_write(priv, MVPP22_ISR_RXQ_GROUP_INDEX_REG, val); 5891 5892 val = qv->first_rxq; 5893 val |= qv->nrxqs << MVPP22_ISR_RXQ_SUB_GROUP_SIZE_OFFSET; 5894 mvpp2_write(priv, MVPP22_ISR_RXQ_SUB_GROUP_CONFIG_REG, val); 5895 } 5896 } 5897 5898 /* Initialize port HW */ 5899 static int mvpp2_port_init(struct mvpp2_port *port) 5900 { 5901 struct device *dev = port->dev->dev.parent; 5902 struct mvpp2 *priv = port->priv; 5903 struct mvpp2_txq_pcpu *txq_pcpu; 5904 unsigned int thread; 5905 int queue, err, val; 5906 5907 /* Checks for hardware constraints */ 5908 if (port->first_rxq + port->nrxqs > 5909 MVPP2_MAX_PORTS * priv->max_port_rxqs) 5910 return -EINVAL; 5911 5912 if (port->nrxqs > priv->max_port_rxqs || port->ntxqs > MVPP2_MAX_TXQ) 5913 return -EINVAL; 5914 5915 /* Disable port */ 5916 mvpp2_egress_disable(port); 5917 mvpp2_port_disable(port); 5918 5919 if (mvpp2_is_xlg(port->phy_interface)) { 5920 val = readl(port->base + MVPP22_XLG_CTRL0_REG); 5921 val &= ~MVPP22_XLG_CTRL0_FORCE_LINK_PASS; 5922 val |= MVPP22_XLG_CTRL0_FORCE_LINK_DOWN; 5923 writel(val, port->base + MVPP22_XLG_CTRL0_REG); 5924 } else { 5925 val = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG); 5926 val &= ~MVPP2_GMAC_FORCE_LINK_PASS; 5927 val |= MVPP2_GMAC_FORCE_LINK_DOWN; 5928 writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG); 5929 } 5930 5931 port->tx_time_coal = MVPP2_TXDONE_COAL_USEC; 5932 5933 port->txqs = devm_kcalloc(dev, port->ntxqs, sizeof(*port->txqs), 5934 GFP_KERNEL); 5935 if (!port->txqs) 5936 return -ENOMEM; 5937 5938 /* Associate physical Tx queues to this port and initialize. 5939 * The mapping is predefined. 5940 */ 5941 for (queue = 0; queue < port->ntxqs; queue++) { 5942 int queue_phy_id = mvpp2_txq_phys(port->id, queue); 5943 struct mvpp2_tx_queue *txq; 5944 5945 txq = devm_kzalloc(dev, sizeof(*txq), GFP_KERNEL); 5946 if (!txq) { 5947 err = -ENOMEM; 5948 goto err_free_percpu; 5949 } 5950 5951 txq->pcpu = alloc_percpu(struct mvpp2_txq_pcpu); 5952 if (!txq->pcpu) { 5953 err = -ENOMEM; 5954 goto err_free_percpu; 5955 } 5956 5957 txq->id = queue_phy_id; 5958 txq->log_id = queue; 5959 txq->done_pkts_coal = MVPP2_TXDONE_COAL_PKTS_THRESH; 5960 for (thread = 0; thread < priv->nthreads; thread++) { 5961 txq_pcpu = per_cpu_ptr(txq->pcpu, thread); 5962 txq_pcpu->thread = thread; 5963 } 5964 5965 port->txqs[queue] = txq; 5966 } 5967 5968 port->rxqs = devm_kcalloc(dev, port->nrxqs, sizeof(*port->rxqs), 5969 GFP_KERNEL); 5970 if (!port->rxqs) { 5971 err = -ENOMEM; 5972 goto err_free_percpu; 5973 } 5974 5975 /* Allocate and initialize Rx queue for this port */ 5976 for (queue = 0; queue < port->nrxqs; queue++) { 5977 struct mvpp2_rx_queue *rxq; 5978 5979 /* Map physical Rx queue to port's logical Rx queue */ 5980 rxq = devm_kzalloc(dev, sizeof(*rxq), GFP_KERNEL); 5981 if (!rxq) { 5982 err = -ENOMEM; 5983 goto err_free_percpu; 5984 } 5985 /* Map this Rx queue to a physical queue */ 5986 rxq->id = port->first_rxq + queue; 5987 rxq->port = port->id; 5988 rxq->logic_rxq = queue; 5989 5990 port->rxqs[queue] = rxq; 5991 } 5992 5993 mvpp2_rx_irqs_setup(port); 5994 5995 /* Create Rx descriptor rings */ 5996 for (queue = 0; queue < port->nrxqs; queue++) { 5997 struct mvpp2_rx_queue *rxq = port->rxqs[queue]; 5998 5999 rxq->size = port->rx_ring_size; 6000 rxq->pkts_coal = MVPP2_RX_COAL_PKTS; 6001 rxq->time_coal = MVPP2_RX_COAL_USEC; 6002 } 6003 6004 mvpp2_ingress_disable(port); 6005 6006 /* Port default configuration */ 6007 mvpp2_defaults_set(port); 6008 6009 /* Port's classifier configuration */ 6010 mvpp2_cls_oversize_rxq_set(port); 6011 mvpp2_cls_port_config(port); 6012 6013 if (mvpp22_rss_is_supported(port)) 6014 mvpp22_port_rss_init(port); 6015 6016 /* Provide an initial Rx packet size */ 6017 port->pkt_size = MVPP2_RX_PKT_SIZE(port->dev->mtu); 6018 6019 /* Initialize pools for swf */ 6020 err = mvpp2_swf_bm_pool_init(port); 6021 if (err) 6022 goto err_free_percpu; 6023 6024 /* Clear all port stats */ 6025 mvpp2_read_stats(port); 6026 memset(port->ethtool_stats, 0, 6027 MVPP2_N_ETHTOOL_STATS(port->ntxqs, port->nrxqs) * sizeof(u64)); 6028 6029 return 0; 6030 6031 err_free_percpu: 6032 for (queue = 0; queue < port->ntxqs; queue++) { 6033 if (!port->txqs[queue]) 6034 continue; 6035 free_percpu(port->txqs[queue]->pcpu); 6036 } 6037 return err; 6038 } 6039 6040 static bool mvpp22_port_has_legacy_tx_irqs(struct device_node *port_node, 6041 unsigned long *flags) 6042 { 6043 char *irqs[5] = { "rx-shared", "tx-cpu0", "tx-cpu1", "tx-cpu2", 6044 "tx-cpu3" }; 6045 int i; 6046 6047 for (i = 0; i < 5; i++) 6048 if (of_property_match_string(port_node, "interrupt-names", 6049 irqs[i]) < 0) 6050 return false; 6051 6052 *flags |= MVPP2_F_DT_COMPAT; 6053 return true; 6054 } 6055 6056 /* Checks if the port dt description has the required Tx interrupts: 6057 * - PPv2.1: there are no such interrupts. 6058 * - PPv2.2 and PPv2.3: 6059 * - The old DTs have: "rx-shared", "tx-cpuX" with X in [0...3] 6060 * - The new ones have: "hifX" with X in [0..8] 6061 * 6062 * All those variants are supported to keep the backward compatibility. 6063 */ 6064 static bool mvpp2_port_has_irqs(struct mvpp2 *priv, 6065 struct device_node *port_node, 6066 unsigned long *flags) 6067 { 6068 char name[5]; 6069 int i; 6070 6071 /* ACPI */ 6072 if (!port_node) 6073 return true; 6074 6075 if (priv->hw_version == MVPP21) 6076 return false; 6077 6078 if (mvpp22_port_has_legacy_tx_irqs(port_node, flags)) 6079 return true; 6080 6081 for (i = 0; i < MVPP2_MAX_THREADS; i++) { 6082 snprintf(name, 5, "hif%d", i); 6083 if (of_property_match_string(port_node, "interrupt-names", 6084 name) < 0) 6085 return false; 6086 } 6087 6088 return true; 6089 } 6090 6091 static int mvpp2_port_copy_mac_addr(struct net_device *dev, struct mvpp2 *priv, 6092 struct fwnode_handle *fwnode, 6093 char **mac_from) 6094 { 6095 struct mvpp2_port *port = netdev_priv(dev); 6096 char hw_mac_addr[ETH_ALEN] = {0}; 6097 char fw_mac_addr[ETH_ALEN]; 6098 int ret; 6099 6100 if (!fwnode_get_mac_address(fwnode, fw_mac_addr)) { 6101 *mac_from = "firmware node"; 6102 eth_hw_addr_set(dev, fw_mac_addr); 6103 return 0; 6104 } 6105 6106 if (priv->hw_version == MVPP21) { 6107 mvpp21_get_mac_address(port, hw_mac_addr); 6108 if (is_valid_ether_addr(hw_mac_addr)) { 6109 *mac_from = "hardware"; 6110 eth_hw_addr_set(dev, hw_mac_addr); 6111 return 0; 6112 } 6113 } 6114 6115 /* Only valid on OF enabled platforms */ 6116 ret = of_get_mac_address_nvmem(to_of_node(fwnode), fw_mac_addr); 6117 if (ret == -EPROBE_DEFER) 6118 return ret; 6119 if (!ret) { 6120 *mac_from = "nvmem cell"; 6121 eth_hw_addr_set(dev, fw_mac_addr); 6122 return 0; 6123 } 6124 6125 *mac_from = "random"; 6126 eth_hw_addr_random(dev); 6127 6128 return 0; 6129 } 6130 6131 static struct mvpp2_port *mvpp2_phylink_to_port(struct phylink_config *config) 6132 { 6133 return container_of(config, struct mvpp2_port, phylink_config); 6134 } 6135 6136 static struct mvpp2_port *mvpp2_pcs_xlg_to_port(struct phylink_pcs *pcs) 6137 { 6138 return container_of(pcs, struct mvpp2_port, pcs_xlg); 6139 } 6140 6141 static struct mvpp2_port *mvpp2_pcs_gmac_to_port(struct phylink_pcs *pcs) 6142 { 6143 return container_of(pcs, struct mvpp2_port, pcs_gmac); 6144 } 6145 6146 static void mvpp2_xlg_pcs_get_state(struct phylink_pcs *pcs, 6147 struct phylink_link_state *state) 6148 { 6149 struct mvpp2_port *port = mvpp2_pcs_xlg_to_port(pcs); 6150 u32 val; 6151 6152 if (port->phy_interface == PHY_INTERFACE_MODE_5GBASER) 6153 state->speed = SPEED_5000; 6154 else 6155 state->speed = SPEED_10000; 6156 state->duplex = 1; 6157 state->an_complete = 1; 6158 6159 val = readl(port->base + MVPP22_XLG_STATUS); 6160 state->link = !!(val & MVPP22_XLG_STATUS_LINK_UP); 6161 6162 state->pause = 0; 6163 val = readl(port->base + MVPP22_XLG_CTRL0_REG); 6164 if (val & MVPP22_XLG_CTRL0_TX_FLOW_CTRL_EN) 6165 state->pause |= MLO_PAUSE_TX; 6166 if (val & MVPP22_XLG_CTRL0_RX_FLOW_CTRL_EN) 6167 state->pause |= MLO_PAUSE_RX; 6168 } 6169 6170 static int mvpp2_xlg_pcs_config(struct phylink_pcs *pcs, unsigned int neg_mode, 6171 phy_interface_t interface, 6172 const unsigned long *advertising, 6173 bool permit_pause_to_mac) 6174 { 6175 return 0; 6176 } 6177 6178 static const struct phylink_pcs_ops mvpp2_phylink_xlg_pcs_ops = { 6179 .pcs_get_state = mvpp2_xlg_pcs_get_state, 6180 .pcs_config = mvpp2_xlg_pcs_config, 6181 }; 6182 6183 static int mvpp2_gmac_pcs_validate(struct phylink_pcs *pcs, 6184 unsigned long *supported, 6185 const struct phylink_link_state *state) 6186 { 6187 /* When in 802.3z mode, we must have AN enabled: 6188 * Bit 2 Field InBandAnEn In-band Auto-Negotiation enable. ... 6189 * When <PortType> = 1 (1000BASE-X) this field must be set to 1. 6190 */ 6191 if (phy_interface_mode_is_8023z(state->interface) && 6192 !phylink_test(state->advertising, Autoneg)) 6193 return -EINVAL; 6194 6195 return 0; 6196 } 6197 6198 static void mvpp2_gmac_pcs_get_state(struct phylink_pcs *pcs, 6199 struct phylink_link_state *state) 6200 { 6201 struct mvpp2_port *port = mvpp2_pcs_gmac_to_port(pcs); 6202 u32 val; 6203 6204 val = readl(port->base + MVPP2_GMAC_STATUS0); 6205 6206 state->an_complete = !!(val & MVPP2_GMAC_STATUS0_AN_COMPLETE); 6207 state->link = !!(val & MVPP2_GMAC_STATUS0_LINK_UP); 6208 state->duplex = !!(val & MVPP2_GMAC_STATUS0_FULL_DUPLEX); 6209 6210 switch (port->phy_interface) { 6211 case PHY_INTERFACE_MODE_1000BASEX: 6212 state->speed = SPEED_1000; 6213 break; 6214 case PHY_INTERFACE_MODE_2500BASEX: 6215 state->speed = SPEED_2500; 6216 break; 6217 default: 6218 if (val & MVPP2_GMAC_STATUS0_GMII_SPEED) 6219 state->speed = SPEED_1000; 6220 else if (val & MVPP2_GMAC_STATUS0_MII_SPEED) 6221 state->speed = SPEED_100; 6222 else 6223 state->speed = SPEED_10; 6224 } 6225 6226 state->pause = 0; 6227 if (val & MVPP2_GMAC_STATUS0_RX_PAUSE) 6228 state->pause |= MLO_PAUSE_RX; 6229 if (val & MVPP2_GMAC_STATUS0_TX_PAUSE) 6230 state->pause |= MLO_PAUSE_TX; 6231 } 6232 6233 static int mvpp2_gmac_pcs_config(struct phylink_pcs *pcs, unsigned int neg_mode, 6234 phy_interface_t interface, 6235 const unsigned long *advertising, 6236 bool permit_pause_to_mac) 6237 { 6238 struct mvpp2_port *port = mvpp2_pcs_gmac_to_port(pcs); 6239 u32 mask, val, an, old_an, changed; 6240 6241 mask = MVPP2_GMAC_IN_BAND_AUTONEG_BYPASS | 6242 MVPP2_GMAC_IN_BAND_AUTONEG | 6243 MVPP2_GMAC_AN_SPEED_EN | 6244 MVPP2_GMAC_FLOW_CTRL_AUTONEG | 6245 MVPP2_GMAC_AN_DUPLEX_EN; 6246 6247 if (neg_mode == PHYLINK_PCS_NEG_INBAND_ENABLED) { 6248 mask |= MVPP2_GMAC_CONFIG_MII_SPEED | 6249 MVPP2_GMAC_CONFIG_GMII_SPEED | 6250 MVPP2_GMAC_CONFIG_FULL_DUPLEX; 6251 val = MVPP2_GMAC_IN_BAND_AUTONEG; 6252 6253 if (interface == PHY_INTERFACE_MODE_SGMII) { 6254 /* SGMII mode receives the speed and duplex from PHY */ 6255 val |= MVPP2_GMAC_AN_SPEED_EN | 6256 MVPP2_GMAC_AN_DUPLEX_EN; 6257 } else { 6258 /* 802.3z mode has fixed speed and duplex */ 6259 val |= MVPP2_GMAC_CONFIG_GMII_SPEED | 6260 MVPP2_GMAC_CONFIG_FULL_DUPLEX; 6261 6262 /* The FLOW_CTRL_AUTONEG bit selects either the hardware 6263 * automatically or the bits in MVPP22_GMAC_CTRL_4_REG 6264 * manually controls the GMAC pause modes. 6265 */ 6266 if (permit_pause_to_mac) 6267 val |= MVPP2_GMAC_FLOW_CTRL_AUTONEG; 6268 6269 /* Configure advertisement bits */ 6270 mask |= MVPP2_GMAC_FC_ADV_EN | MVPP2_GMAC_FC_ADV_ASM_EN; 6271 if (phylink_test(advertising, Pause)) 6272 val |= MVPP2_GMAC_FC_ADV_EN; 6273 if (phylink_test(advertising, Asym_Pause)) 6274 val |= MVPP2_GMAC_FC_ADV_ASM_EN; 6275 } 6276 } else { 6277 val = 0; 6278 } 6279 6280 old_an = an = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG); 6281 an = (an & ~mask) | val; 6282 changed = an ^ old_an; 6283 if (changed) 6284 writel(an, port->base + MVPP2_GMAC_AUTONEG_CONFIG); 6285 6286 /* We are only interested in the advertisement bits changing */ 6287 return changed & (MVPP2_GMAC_FC_ADV_EN | MVPP2_GMAC_FC_ADV_ASM_EN); 6288 } 6289 6290 static void mvpp2_gmac_pcs_an_restart(struct phylink_pcs *pcs) 6291 { 6292 struct mvpp2_port *port = mvpp2_pcs_gmac_to_port(pcs); 6293 u32 val = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG); 6294 6295 writel(val | MVPP2_GMAC_IN_BAND_RESTART_AN, 6296 port->base + MVPP2_GMAC_AUTONEG_CONFIG); 6297 writel(val & ~MVPP2_GMAC_IN_BAND_RESTART_AN, 6298 port->base + MVPP2_GMAC_AUTONEG_CONFIG); 6299 } 6300 6301 static const struct phylink_pcs_ops mvpp2_phylink_gmac_pcs_ops = { 6302 .pcs_validate = mvpp2_gmac_pcs_validate, 6303 .pcs_get_state = mvpp2_gmac_pcs_get_state, 6304 .pcs_config = mvpp2_gmac_pcs_config, 6305 .pcs_an_restart = mvpp2_gmac_pcs_an_restart, 6306 }; 6307 6308 static void mvpp2_xlg_config(struct mvpp2_port *port, unsigned int mode, 6309 const struct phylink_link_state *state) 6310 { 6311 u32 val; 6312 6313 mvpp2_modify(port->base + MVPP22_XLG_CTRL0_REG, 6314 MVPP22_XLG_CTRL0_MAC_RESET_DIS, 6315 MVPP22_XLG_CTRL0_MAC_RESET_DIS); 6316 mvpp2_modify(port->base + MVPP22_XLG_CTRL4_REG, 6317 MVPP22_XLG_CTRL4_MACMODSELECT_GMAC | 6318 MVPP22_XLG_CTRL4_EN_IDLE_CHECK | 6319 MVPP22_XLG_CTRL4_FWD_FC | MVPP22_XLG_CTRL4_FWD_PFC, 6320 MVPP22_XLG_CTRL4_FWD_FC | MVPP22_XLG_CTRL4_FWD_PFC); 6321 6322 /* Wait for reset to deassert */ 6323 do { 6324 val = readl(port->base + MVPP22_XLG_CTRL0_REG); 6325 } while (!(val & MVPP22_XLG_CTRL0_MAC_RESET_DIS)); 6326 } 6327 6328 static void mvpp2_gmac_config(struct mvpp2_port *port, unsigned int mode, 6329 const struct phylink_link_state *state) 6330 { 6331 u32 old_ctrl0, ctrl0; 6332 u32 old_ctrl2, ctrl2; 6333 u32 old_ctrl4, ctrl4; 6334 6335 old_ctrl0 = ctrl0 = readl(port->base + MVPP2_GMAC_CTRL_0_REG); 6336 old_ctrl2 = ctrl2 = readl(port->base + MVPP2_GMAC_CTRL_2_REG); 6337 old_ctrl4 = ctrl4 = readl(port->base + MVPP22_GMAC_CTRL_4_REG); 6338 6339 ctrl0 &= ~MVPP2_GMAC_PORT_TYPE_MASK; 6340 ctrl2 &= ~(MVPP2_GMAC_INBAND_AN_MASK | MVPP2_GMAC_PCS_ENABLE_MASK | MVPP2_GMAC_FLOW_CTRL_MASK); 6341 6342 /* Configure port type */ 6343 if (phy_interface_mode_is_8023z(state->interface)) { 6344 ctrl2 |= MVPP2_GMAC_PCS_ENABLE_MASK; 6345 ctrl4 &= ~MVPP22_CTRL4_EXT_PIN_GMII_SEL; 6346 ctrl4 |= MVPP22_CTRL4_SYNC_BYPASS_DIS | 6347 MVPP22_CTRL4_DP_CLK_SEL | 6348 MVPP22_CTRL4_QSGMII_BYPASS_ACTIVE; 6349 } else if (state->interface == PHY_INTERFACE_MODE_SGMII) { 6350 ctrl2 |= MVPP2_GMAC_PCS_ENABLE_MASK | MVPP2_GMAC_INBAND_AN_MASK; 6351 ctrl4 &= ~MVPP22_CTRL4_EXT_PIN_GMII_SEL; 6352 ctrl4 |= MVPP22_CTRL4_SYNC_BYPASS_DIS | 6353 MVPP22_CTRL4_DP_CLK_SEL | 6354 MVPP22_CTRL4_QSGMII_BYPASS_ACTIVE; 6355 } else if (phy_interface_mode_is_rgmii(state->interface)) { 6356 ctrl4 &= ~MVPP22_CTRL4_DP_CLK_SEL; 6357 ctrl4 |= MVPP22_CTRL4_EXT_PIN_GMII_SEL | 6358 MVPP22_CTRL4_SYNC_BYPASS_DIS | 6359 MVPP22_CTRL4_QSGMII_BYPASS_ACTIVE; 6360 } 6361 6362 /* Configure negotiation style */ 6363 if (!phylink_autoneg_inband(mode)) { 6364 /* Phy or fixed speed - no in-band AN, nothing to do, leave the 6365 * configured speed, duplex and flow control as-is. 6366 */ 6367 } else if (state->interface == PHY_INTERFACE_MODE_SGMII) { 6368 /* SGMII in-band mode receives the speed and duplex from 6369 * the PHY. Flow control information is not received. */ 6370 } else if (phy_interface_mode_is_8023z(state->interface)) { 6371 /* 1000BaseX and 2500BaseX ports cannot negotiate speed nor can 6372 * they negotiate duplex: they are always operating with a fixed 6373 * speed of 1000/2500Mbps in full duplex, so force 1000/2500 6374 * speed and full duplex here. 6375 */ 6376 ctrl0 |= MVPP2_GMAC_PORT_TYPE_MASK; 6377 } 6378 6379 if (old_ctrl0 != ctrl0) 6380 writel(ctrl0, port->base + MVPP2_GMAC_CTRL_0_REG); 6381 if (old_ctrl2 != ctrl2) 6382 writel(ctrl2, port->base + MVPP2_GMAC_CTRL_2_REG); 6383 if (old_ctrl4 != ctrl4) 6384 writel(ctrl4, port->base + MVPP22_GMAC_CTRL_4_REG); 6385 } 6386 6387 static struct phylink_pcs *mvpp2_select_pcs(struct phylink_config *config, 6388 phy_interface_t interface) 6389 { 6390 struct mvpp2_port *port = mvpp2_phylink_to_port(config); 6391 6392 /* Select the appropriate PCS operations depending on the 6393 * configured interface mode. We will only switch to a mode 6394 * that the validate() checks have already passed. 6395 */ 6396 if (mvpp2_is_xlg(interface)) 6397 return &port->pcs_xlg; 6398 else 6399 return &port->pcs_gmac; 6400 } 6401 6402 static int mvpp2_mac_prepare(struct phylink_config *config, unsigned int mode, 6403 phy_interface_t interface) 6404 { 6405 struct mvpp2_port *port = mvpp2_phylink_to_port(config); 6406 6407 /* Check for invalid configuration */ 6408 if (mvpp2_is_xlg(interface) && port->gop_id != 0) { 6409 netdev_err(port->dev, "Invalid mode on %s\n", port->dev->name); 6410 return -EINVAL; 6411 } 6412 6413 if (port->phy_interface != interface || 6414 phylink_autoneg_inband(mode)) { 6415 /* Force the link down when changing the interface or if in 6416 * in-band mode to ensure we do not change the configuration 6417 * while the hardware is indicating link is up. We force both 6418 * XLG and GMAC down to ensure that they're both in a known 6419 * state. 6420 */ 6421 mvpp2_modify(port->base + MVPP2_GMAC_AUTONEG_CONFIG, 6422 MVPP2_GMAC_FORCE_LINK_PASS | 6423 MVPP2_GMAC_FORCE_LINK_DOWN, 6424 MVPP2_GMAC_FORCE_LINK_DOWN); 6425 6426 if (mvpp2_port_supports_xlg(port)) 6427 mvpp2_modify(port->base + MVPP22_XLG_CTRL0_REG, 6428 MVPP22_XLG_CTRL0_FORCE_LINK_PASS | 6429 MVPP22_XLG_CTRL0_FORCE_LINK_DOWN, 6430 MVPP22_XLG_CTRL0_FORCE_LINK_DOWN); 6431 } 6432 6433 /* Make sure the port is disabled when reconfiguring the mode */ 6434 mvpp2_port_disable(port); 6435 6436 if (port->phy_interface != interface) { 6437 /* Place GMAC into reset */ 6438 mvpp2_modify(port->base + MVPP2_GMAC_CTRL_2_REG, 6439 MVPP2_GMAC_PORT_RESET_MASK, 6440 MVPP2_GMAC_PORT_RESET_MASK); 6441 6442 if (port->priv->hw_version >= MVPP22) { 6443 mvpp22_gop_mask_irq(port); 6444 6445 phy_power_off(port->comphy); 6446 6447 /* Reconfigure the serdes lanes */ 6448 mvpp22_mode_reconfigure(port, interface); 6449 } 6450 } 6451 6452 return 0; 6453 } 6454 6455 static void mvpp2_mac_config(struct phylink_config *config, unsigned int mode, 6456 const struct phylink_link_state *state) 6457 { 6458 struct mvpp2_port *port = mvpp2_phylink_to_port(config); 6459 6460 /* mac (re)configuration */ 6461 if (mvpp2_is_xlg(state->interface)) 6462 mvpp2_xlg_config(port, mode, state); 6463 else if (phy_interface_mode_is_rgmii(state->interface) || 6464 phy_interface_mode_is_8023z(state->interface) || 6465 state->interface == PHY_INTERFACE_MODE_SGMII) 6466 mvpp2_gmac_config(port, mode, state); 6467 6468 if (port->priv->hw_version == MVPP21 && port->flags & MVPP2_F_LOOPBACK) 6469 mvpp2_port_loopback_set(port, state); 6470 } 6471 6472 static int mvpp2_mac_finish(struct phylink_config *config, unsigned int mode, 6473 phy_interface_t interface) 6474 { 6475 struct mvpp2_port *port = mvpp2_phylink_to_port(config); 6476 6477 if (port->priv->hw_version >= MVPP22 && 6478 port->phy_interface != interface) { 6479 port->phy_interface = interface; 6480 6481 /* Unmask interrupts */ 6482 mvpp22_gop_unmask_irq(port); 6483 } 6484 6485 if (!mvpp2_is_xlg(interface)) { 6486 /* Release GMAC reset and wait */ 6487 mvpp2_modify(port->base + MVPP2_GMAC_CTRL_2_REG, 6488 MVPP2_GMAC_PORT_RESET_MASK, 0); 6489 6490 while (readl(port->base + MVPP2_GMAC_CTRL_2_REG) & 6491 MVPP2_GMAC_PORT_RESET_MASK) 6492 continue; 6493 } 6494 6495 mvpp2_port_enable(port); 6496 6497 /* Allow the link to come up if in in-band mode, otherwise the 6498 * link is forced via mac_link_down()/mac_link_up() 6499 */ 6500 if (phylink_autoneg_inband(mode)) { 6501 if (mvpp2_is_xlg(interface)) 6502 mvpp2_modify(port->base + MVPP22_XLG_CTRL0_REG, 6503 MVPP22_XLG_CTRL0_FORCE_LINK_PASS | 6504 MVPP22_XLG_CTRL0_FORCE_LINK_DOWN, 0); 6505 else 6506 mvpp2_modify(port->base + MVPP2_GMAC_AUTONEG_CONFIG, 6507 MVPP2_GMAC_FORCE_LINK_PASS | 6508 MVPP2_GMAC_FORCE_LINK_DOWN, 0); 6509 } 6510 6511 return 0; 6512 } 6513 6514 static void mvpp2_mac_link_up(struct phylink_config *config, 6515 struct phy_device *phy, 6516 unsigned int mode, phy_interface_t interface, 6517 int speed, int duplex, 6518 bool tx_pause, bool rx_pause) 6519 { 6520 struct mvpp2_port *port = mvpp2_phylink_to_port(config); 6521 u32 val; 6522 int i; 6523 6524 if (mvpp2_is_xlg(interface)) { 6525 if (!phylink_autoneg_inband(mode)) { 6526 val = MVPP22_XLG_CTRL0_FORCE_LINK_PASS; 6527 if (tx_pause) 6528 val |= MVPP22_XLG_CTRL0_TX_FLOW_CTRL_EN; 6529 if (rx_pause) 6530 val |= MVPP22_XLG_CTRL0_RX_FLOW_CTRL_EN; 6531 6532 mvpp2_modify(port->base + MVPP22_XLG_CTRL0_REG, 6533 MVPP22_XLG_CTRL0_FORCE_LINK_DOWN | 6534 MVPP22_XLG_CTRL0_FORCE_LINK_PASS | 6535 MVPP22_XLG_CTRL0_TX_FLOW_CTRL_EN | 6536 MVPP22_XLG_CTRL0_RX_FLOW_CTRL_EN, val); 6537 } 6538 } else { 6539 if (!phylink_autoneg_inband(mode)) { 6540 val = MVPP2_GMAC_FORCE_LINK_PASS; 6541 6542 if (speed == SPEED_1000 || speed == SPEED_2500) 6543 val |= MVPP2_GMAC_CONFIG_GMII_SPEED; 6544 else if (speed == SPEED_100) 6545 val |= MVPP2_GMAC_CONFIG_MII_SPEED; 6546 6547 if (duplex == DUPLEX_FULL) 6548 val |= MVPP2_GMAC_CONFIG_FULL_DUPLEX; 6549 6550 mvpp2_modify(port->base + MVPP2_GMAC_AUTONEG_CONFIG, 6551 MVPP2_GMAC_FORCE_LINK_DOWN | 6552 MVPP2_GMAC_FORCE_LINK_PASS | 6553 MVPP2_GMAC_CONFIG_MII_SPEED | 6554 MVPP2_GMAC_CONFIG_GMII_SPEED | 6555 MVPP2_GMAC_CONFIG_FULL_DUPLEX, val); 6556 } 6557 6558 /* We can always update the flow control enable bits; 6559 * these will only be effective if flow control AN 6560 * (MVPP2_GMAC_FLOW_CTRL_AUTONEG) is disabled. 6561 */ 6562 val = 0; 6563 if (tx_pause) 6564 val |= MVPP22_CTRL4_TX_FC_EN; 6565 if (rx_pause) 6566 val |= MVPP22_CTRL4_RX_FC_EN; 6567 6568 mvpp2_modify(port->base + MVPP22_GMAC_CTRL_4_REG, 6569 MVPP22_CTRL4_RX_FC_EN | MVPP22_CTRL4_TX_FC_EN, 6570 val); 6571 } 6572 6573 if (port->priv->global_tx_fc) { 6574 port->tx_fc = tx_pause; 6575 if (tx_pause) 6576 mvpp2_rxq_enable_fc(port); 6577 else 6578 mvpp2_rxq_disable_fc(port); 6579 if (port->priv->percpu_pools) { 6580 for (i = 0; i < port->nrxqs; i++) 6581 mvpp2_bm_pool_update_fc(port, &port->priv->bm_pools[i], tx_pause); 6582 } else { 6583 mvpp2_bm_pool_update_fc(port, port->pool_long, tx_pause); 6584 mvpp2_bm_pool_update_fc(port, port->pool_short, tx_pause); 6585 } 6586 if (port->priv->hw_version == MVPP23) 6587 mvpp23_rx_fifo_fc_en(port->priv, port->id, tx_pause); 6588 } 6589 6590 mvpp2_port_enable(port); 6591 6592 mvpp2_egress_enable(port); 6593 mvpp2_ingress_enable(port); 6594 netif_tx_wake_all_queues(port->dev); 6595 } 6596 6597 static void mvpp2_mac_link_down(struct phylink_config *config, 6598 unsigned int mode, phy_interface_t interface) 6599 { 6600 struct mvpp2_port *port = mvpp2_phylink_to_port(config); 6601 u32 val; 6602 6603 if (!phylink_autoneg_inband(mode)) { 6604 if (mvpp2_is_xlg(interface)) { 6605 val = readl(port->base + MVPP22_XLG_CTRL0_REG); 6606 val &= ~MVPP22_XLG_CTRL0_FORCE_LINK_PASS; 6607 val |= MVPP22_XLG_CTRL0_FORCE_LINK_DOWN; 6608 writel(val, port->base + MVPP22_XLG_CTRL0_REG); 6609 } else { 6610 val = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG); 6611 val &= ~MVPP2_GMAC_FORCE_LINK_PASS; 6612 val |= MVPP2_GMAC_FORCE_LINK_DOWN; 6613 writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG); 6614 } 6615 } 6616 6617 netif_tx_stop_all_queues(port->dev); 6618 mvpp2_egress_disable(port); 6619 mvpp2_ingress_disable(port); 6620 6621 mvpp2_port_disable(port); 6622 } 6623 6624 static const struct phylink_mac_ops mvpp2_phylink_ops = { 6625 .mac_select_pcs = mvpp2_select_pcs, 6626 .mac_prepare = mvpp2_mac_prepare, 6627 .mac_config = mvpp2_mac_config, 6628 .mac_finish = mvpp2_mac_finish, 6629 .mac_link_up = mvpp2_mac_link_up, 6630 .mac_link_down = mvpp2_mac_link_down, 6631 }; 6632 6633 /* Work-around for ACPI */ 6634 static void mvpp2_acpi_start(struct mvpp2_port *port) 6635 { 6636 /* Phylink isn't used as of now for ACPI, so the MAC has to be 6637 * configured manually when the interface is started. This will 6638 * be removed as soon as the phylink ACPI support lands in. 6639 */ 6640 struct phylink_link_state state = { 6641 .interface = port->phy_interface, 6642 }; 6643 struct phylink_pcs *pcs; 6644 6645 pcs = mvpp2_select_pcs(&port->phylink_config, port->phy_interface); 6646 6647 mvpp2_mac_prepare(&port->phylink_config, MLO_AN_INBAND, 6648 port->phy_interface); 6649 mvpp2_mac_config(&port->phylink_config, MLO_AN_INBAND, &state); 6650 pcs->ops->pcs_config(pcs, PHYLINK_PCS_NEG_INBAND_ENABLED, 6651 port->phy_interface, state.advertising, 6652 false); 6653 mvpp2_mac_finish(&port->phylink_config, MLO_AN_INBAND, 6654 port->phy_interface); 6655 mvpp2_mac_link_up(&port->phylink_config, NULL, 6656 MLO_AN_INBAND, port->phy_interface, 6657 SPEED_UNKNOWN, DUPLEX_UNKNOWN, false, false); 6658 } 6659 6660 /* In order to ensure backward compatibility for ACPI, check if the port 6661 * firmware node comprises the necessary description allowing to use phylink. 6662 */ 6663 static bool mvpp2_use_acpi_compat_mode(struct fwnode_handle *port_fwnode) 6664 { 6665 if (!is_acpi_node(port_fwnode)) 6666 return false; 6667 6668 return (!fwnode_property_present(port_fwnode, "phy-handle") && 6669 !fwnode_property_present(port_fwnode, "managed") && 6670 !fwnode_get_named_child_node(port_fwnode, "fixed-link")); 6671 } 6672 6673 /* Ports initialization */ 6674 static int mvpp2_port_probe(struct platform_device *pdev, 6675 struct fwnode_handle *port_fwnode, 6676 struct mvpp2 *priv) 6677 { 6678 struct phy *comphy = NULL; 6679 struct mvpp2_port *port; 6680 struct mvpp2_port_pcpu *port_pcpu; 6681 struct device_node *port_node = to_of_node(port_fwnode); 6682 netdev_features_t features; 6683 struct net_device *dev; 6684 struct phylink *phylink; 6685 char *mac_from = ""; 6686 unsigned int ntxqs, nrxqs, thread; 6687 unsigned long flags = 0; 6688 bool has_tx_irqs; 6689 u32 id; 6690 int phy_mode; 6691 int err, i; 6692 6693 has_tx_irqs = mvpp2_port_has_irqs(priv, port_node, &flags); 6694 if (!has_tx_irqs && queue_mode == MVPP2_QDIST_MULTI_MODE) { 6695 dev_err(&pdev->dev, 6696 "not enough IRQs to support multi queue mode\n"); 6697 return -EINVAL; 6698 } 6699 6700 ntxqs = MVPP2_MAX_TXQ; 6701 nrxqs = mvpp2_get_nrxqs(priv); 6702 6703 dev = alloc_etherdev_mqs(sizeof(*port), ntxqs, nrxqs); 6704 if (!dev) 6705 return -ENOMEM; 6706 6707 phy_mode = fwnode_get_phy_mode(port_fwnode); 6708 if (phy_mode < 0) { 6709 dev_err(&pdev->dev, "incorrect phy mode\n"); 6710 err = phy_mode; 6711 goto err_free_netdev; 6712 } 6713 6714 /* 6715 * Rewrite 10GBASE-KR to 10GBASE-R for compatibility with existing DT. 6716 * Existing usage of 10GBASE-KR is not correct; no backplane 6717 * negotiation is done, and this driver does not actually support 6718 * 10GBASE-KR. 6719 */ 6720 if (phy_mode == PHY_INTERFACE_MODE_10GKR) 6721 phy_mode = PHY_INTERFACE_MODE_10GBASER; 6722 6723 if (port_node) { 6724 comphy = devm_of_phy_get(&pdev->dev, port_node, NULL); 6725 if (IS_ERR(comphy)) { 6726 if (PTR_ERR(comphy) == -EPROBE_DEFER) { 6727 err = -EPROBE_DEFER; 6728 goto err_free_netdev; 6729 } 6730 comphy = NULL; 6731 } 6732 } 6733 6734 if (fwnode_property_read_u32(port_fwnode, "port-id", &id)) { 6735 err = -EINVAL; 6736 dev_err(&pdev->dev, "missing port-id value\n"); 6737 goto err_free_netdev; 6738 } 6739 6740 dev->tx_queue_len = MVPP2_MAX_TXD_MAX; 6741 dev->watchdog_timeo = 5 * HZ; 6742 dev->netdev_ops = &mvpp2_netdev_ops; 6743 dev->ethtool_ops = &mvpp2_eth_tool_ops; 6744 6745 port = netdev_priv(dev); 6746 port->dev = dev; 6747 port->fwnode = port_fwnode; 6748 port->ntxqs = ntxqs; 6749 port->nrxqs = nrxqs; 6750 port->priv = priv; 6751 port->has_tx_irqs = has_tx_irqs; 6752 port->flags = flags; 6753 6754 err = mvpp2_queue_vectors_init(port, port_node); 6755 if (err) 6756 goto err_free_netdev; 6757 6758 if (port_node) 6759 port->port_irq = of_irq_get_byname(port_node, "link"); 6760 else 6761 port->port_irq = fwnode_irq_get(port_fwnode, port->nqvecs + 1); 6762 if (port->port_irq == -EPROBE_DEFER) { 6763 err = -EPROBE_DEFER; 6764 goto err_deinit_qvecs; 6765 } 6766 if (port->port_irq <= 0) 6767 /* the link irq is optional */ 6768 port->port_irq = 0; 6769 6770 if (fwnode_property_read_bool(port_fwnode, "marvell,loopback")) 6771 port->flags |= MVPP2_F_LOOPBACK; 6772 6773 port->id = id; 6774 if (priv->hw_version == MVPP21) 6775 port->first_rxq = port->id * port->nrxqs; 6776 else 6777 port->first_rxq = port->id * priv->max_port_rxqs; 6778 6779 port->of_node = port_node; 6780 port->phy_interface = phy_mode; 6781 port->comphy = comphy; 6782 6783 if (priv->hw_version == MVPP21) { 6784 port->base = devm_platform_ioremap_resource(pdev, 2 + id); 6785 if (IS_ERR(port->base)) { 6786 err = PTR_ERR(port->base); 6787 goto err_free_irq; 6788 } 6789 6790 port->stats_base = port->priv->lms_base + 6791 MVPP21_MIB_COUNTERS_OFFSET + 6792 port->gop_id * MVPP21_MIB_COUNTERS_PORT_SZ; 6793 } else { 6794 if (fwnode_property_read_u32(port_fwnode, "gop-port-id", 6795 &port->gop_id)) { 6796 err = -EINVAL; 6797 dev_err(&pdev->dev, "missing gop-port-id value\n"); 6798 goto err_deinit_qvecs; 6799 } 6800 6801 port->base = priv->iface_base + MVPP22_GMAC_BASE(port->gop_id); 6802 port->stats_base = port->priv->iface_base + 6803 MVPP22_MIB_COUNTERS_OFFSET + 6804 port->gop_id * MVPP22_MIB_COUNTERS_PORT_SZ; 6805 6806 /* We may want a property to describe whether we should use 6807 * MAC hardware timestamping. 6808 */ 6809 if (priv->tai) 6810 port->hwtstamp = true; 6811 } 6812 6813 /* Alloc per-cpu and ethtool stats */ 6814 port->stats = netdev_alloc_pcpu_stats(struct mvpp2_pcpu_stats); 6815 if (!port->stats) { 6816 err = -ENOMEM; 6817 goto err_free_irq; 6818 } 6819 6820 port->ethtool_stats = devm_kcalloc(&pdev->dev, 6821 MVPP2_N_ETHTOOL_STATS(ntxqs, nrxqs), 6822 sizeof(u64), GFP_KERNEL); 6823 if (!port->ethtool_stats) { 6824 err = -ENOMEM; 6825 goto err_free_stats; 6826 } 6827 6828 mutex_init(&port->gather_stats_lock); 6829 INIT_DELAYED_WORK(&port->stats_work, mvpp2_gather_hw_statistics); 6830 6831 err = mvpp2_port_copy_mac_addr(dev, priv, port_fwnode, &mac_from); 6832 if (err < 0) 6833 goto err_free_stats; 6834 6835 port->tx_ring_size = MVPP2_MAX_TXD_DFLT; 6836 port->rx_ring_size = MVPP2_MAX_RXD_DFLT; 6837 SET_NETDEV_DEV(dev, &pdev->dev); 6838 6839 err = mvpp2_port_init(port); 6840 if (err < 0) { 6841 dev_err(&pdev->dev, "failed to init port %d\n", id); 6842 goto err_free_stats; 6843 } 6844 6845 mvpp2_port_periodic_xon_disable(port); 6846 6847 mvpp2_mac_reset_assert(port); 6848 mvpp22_pcs_reset_assert(port); 6849 6850 port->pcpu = alloc_percpu(struct mvpp2_port_pcpu); 6851 if (!port->pcpu) { 6852 err = -ENOMEM; 6853 goto err_free_txq_pcpu; 6854 } 6855 6856 if (!port->has_tx_irqs) { 6857 for (thread = 0; thread < priv->nthreads; thread++) { 6858 port_pcpu = per_cpu_ptr(port->pcpu, thread); 6859 6860 hrtimer_init(&port_pcpu->tx_done_timer, CLOCK_MONOTONIC, 6861 HRTIMER_MODE_REL_PINNED_SOFT); 6862 port_pcpu->tx_done_timer.function = mvpp2_hr_timer_cb; 6863 port_pcpu->timer_scheduled = false; 6864 port_pcpu->dev = dev; 6865 } 6866 } 6867 6868 features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | 6869 NETIF_F_TSO; 6870 dev->features = features | NETIF_F_RXCSUM; 6871 dev->hw_features |= features | NETIF_F_RXCSUM | NETIF_F_GRO | 6872 NETIF_F_HW_VLAN_CTAG_FILTER; 6873 6874 if (mvpp22_rss_is_supported(port)) { 6875 dev->hw_features |= NETIF_F_RXHASH; 6876 dev->features |= NETIF_F_NTUPLE; 6877 } 6878 6879 if (!port->priv->percpu_pools) 6880 mvpp2_set_hw_csum(port, port->pool_long->id); 6881 else if (port->ntxqs >= num_possible_cpus() * 2) 6882 dev->xdp_features = NETDEV_XDP_ACT_BASIC | 6883 NETDEV_XDP_ACT_REDIRECT | 6884 NETDEV_XDP_ACT_NDO_XMIT; 6885 6886 dev->vlan_features |= features; 6887 netif_set_tso_max_segs(dev, MVPP2_MAX_TSO_SEGS); 6888 6889 dev->priv_flags |= IFF_UNICAST_FLT; 6890 6891 /* MTU range: 68 - 9704 */ 6892 dev->min_mtu = ETH_MIN_MTU; 6893 /* 9704 == 9728 - 20 and rounding to 8 */ 6894 dev->max_mtu = MVPP2_BM_JUMBO_PKT_SIZE; 6895 dev->dev.of_node = port_node; 6896 6897 port->pcs_gmac.ops = &mvpp2_phylink_gmac_pcs_ops; 6898 port->pcs_gmac.neg_mode = true; 6899 port->pcs_xlg.ops = &mvpp2_phylink_xlg_pcs_ops; 6900 port->pcs_xlg.neg_mode = true; 6901 6902 if (!mvpp2_use_acpi_compat_mode(port_fwnode)) { 6903 port->phylink_config.dev = &dev->dev; 6904 port->phylink_config.type = PHYLINK_NETDEV; 6905 port->phylink_config.mac_capabilities = 6906 MAC_2500FD | MAC_1000FD | MAC_100 | MAC_10; 6907 6908 if (port->priv->global_tx_fc) 6909 port->phylink_config.mac_capabilities |= 6910 MAC_SYM_PAUSE | MAC_ASYM_PAUSE; 6911 6912 if (mvpp2_port_supports_xlg(port)) { 6913 /* If a COMPHY is present, we can support any of 6914 * the serdes modes and switch between them. 6915 */ 6916 if (comphy) { 6917 __set_bit(PHY_INTERFACE_MODE_5GBASER, 6918 port->phylink_config.supported_interfaces); 6919 __set_bit(PHY_INTERFACE_MODE_10GBASER, 6920 port->phylink_config.supported_interfaces); 6921 __set_bit(PHY_INTERFACE_MODE_XAUI, 6922 port->phylink_config.supported_interfaces); 6923 } else if (phy_mode == PHY_INTERFACE_MODE_5GBASER) { 6924 __set_bit(PHY_INTERFACE_MODE_5GBASER, 6925 port->phylink_config.supported_interfaces); 6926 } else if (phy_mode == PHY_INTERFACE_MODE_10GBASER) { 6927 __set_bit(PHY_INTERFACE_MODE_10GBASER, 6928 port->phylink_config.supported_interfaces); 6929 } else if (phy_mode == PHY_INTERFACE_MODE_XAUI) { 6930 __set_bit(PHY_INTERFACE_MODE_XAUI, 6931 port->phylink_config.supported_interfaces); 6932 } 6933 6934 if (comphy) 6935 port->phylink_config.mac_capabilities |= 6936 MAC_10000FD | MAC_5000FD; 6937 else if (phy_mode == PHY_INTERFACE_MODE_5GBASER) 6938 port->phylink_config.mac_capabilities |= 6939 MAC_5000FD; 6940 else 6941 port->phylink_config.mac_capabilities |= 6942 MAC_10000FD; 6943 } 6944 6945 if (mvpp2_port_supports_rgmii(port)) 6946 phy_interface_set_rgmii(port->phylink_config.supported_interfaces); 6947 6948 if (comphy) { 6949 /* If a COMPHY is present, we can support any of the 6950 * serdes modes and switch between them. 6951 */ 6952 __set_bit(PHY_INTERFACE_MODE_SGMII, 6953 port->phylink_config.supported_interfaces); 6954 __set_bit(PHY_INTERFACE_MODE_1000BASEX, 6955 port->phylink_config.supported_interfaces); 6956 __set_bit(PHY_INTERFACE_MODE_2500BASEX, 6957 port->phylink_config.supported_interfaces); 6958 } else if (phy_mode == PHY_INTERFACE_MODE_2500BASEX) { 6959 /* No COMPHY, with only 2500BASE-X mode supported */ 6960 __set_bit(PHY_INTERFACE_MODE_2500BASEX, 6961 port->phylink_config.supported_interfaces); 6962 } else if (phy_mode == PHY_INTERFACE_MODE_1000BASEX || 6963 phy_mode == PHY_INTERFACE_MODE_SGMII) { 6964 /* No COMPHY, we can switch between 1000BASE-X and SGMII 6965 */ 6966 __set_bit(PHY_INTERFACE_MODE_1000BASEX, 6967 port->phylink_config.supported_interfaces); 6968 __set_bit(PHY_INTERFACE_MODE_SGMII, 6969 port->phylink_config.supported_interfaces); 6970 } 6971 6972 phylink = phylink_create(&port->phylink_config, port_fwnode, 6973 phy_mode, &mvpp2_phylink_ops); 6974 if (IS_ERR(phylink)) { 6975 err = PTR_ERR(phylink); 6976 goto err_free_port_pcpu; 6977 } 6978 port->phylink = phylink; 6979 } else { 6980 dev_warn(&pdev->dev, "Use link irqs for port#%d. FW update required\n", port->id); 6981 port->phylink = NULL; 6982 } 6983 6984 /* Cycle the comphy to power it down, saving 270mW per port - 6985 * don't worry about an error powering it up. When the comphy 6986 * driver does this, we can remove this code. 6987 */ 6988 if (port->comphy) { 6989 err = mvpp22_comphy_init(port, port->phy_interface); 6990 if (err == 0) 6991 phy_power_off(port->comphy); 6992 } 6993 6994 err = register_netdev(dev); 6995 if (err < 0) { 6996 dev_err(&pdev->dev, "failed to register netdev\n"); 6997 goto err_phylink; 6998 } 6999 netdev_info(dev, "Using %s mac address %pM\n", mac_from, dev->dev_addr); 7000 7001 priv->port_list[priv->port_count++] = port; 7002 7003 return 0; 7004 7005 err_phylink: 7006 if (port->phylink) 7007 phylink_destroy(port->phylink); 7008 err_free_port_pcpu: 7009 free_percpu(port->pcpu); 7010 err_free_txq_pcpu: 7011 for (i = 0; i < port->ntxqs; i++) 7012 free_percpu(port->txqs[i]->pcpu); 7013 err_free_stats: 7014 free_percpu(port->stats); 7015 err_free_irq: 7016 if (port->port_irq) 7017 irq_dispose_mapping(port->port_irq); 7018 err_deinit_qvecs: 7019 mvpp2_queue_vectors_deinit(port); 7020 err_free_netdev: 7021 free_netdev(dev); 7022 return err; 7023 } 7024 7025 /* Ports removal routine */ 7026 static void mvpp2_port_remove(struct mvpp2_port *port) 7027 { 7028 int i; 7029 7030 unregister_netdev(port->dev); 7031 if (port->phylink) 7032 phylink_destroy(port->phylink); 7033 free_percpu(port->pcpu); 7034 free_percpu(port->stats); 7035 for (i = 0; i < port->ntxqs; i++) 7036 free_percpu(port->txqs[i]->pcpu); 7037 mvpp2_queue_vectors_deinit(port); 7038 if (port->port_irq) 7039 irq_dispose_mapping(port->port_irq); 7040 free_netdev(port->dev); 7041 } 7042 7043 /* Initialize decoding windows */ 7044 static void mvpp2_conf_mbus_windows(const struct mbus_dram_target_info *dram, 7045 struct mvpp2 *priv) 7046 { 7047 u32 win_enable; 7048 int i; 7049 7050 for (i = 0; i < 6; i++) { 7051 mvpp2_write(priv, MVPP2_WIN_BASE(i), 0); 7052 mvpp2_write(priv, MVPP2_WIN_SIZE(i), 0); 7053 7054 if (i < 4) 7055 mvpp2_write(priv, MVPP2_WIN_REMAP(i), 0); 7056 } 7057 7058 win_enable = 0; 7059 7060 for (i = 0; i < dram->num_cs; i++) { 7061 const struct mbus_dram_window *cs = dram->cs + i; 7062 7063 mvpp2_write(priv, MVPP2_WIN_BASE(i), 7064 (cs->base & 0xffff0000) | (cs->mbus_attr << 8) | 7065 dram->mbus_dram_target_id); 7066 7067 mvpp2_write(priv, MVPP2_WIN_SIZE(i), 7068 (cs->size - 1) & 0xffff0000); 7069 7070 win_enable |= (1 << i); 7071 } 7072 7073 mvpp2_write(priv, MVPP2_BASE_ADDR_ENABLE, win_enable); 7074 } 7075 7076 /* Initialize Rx FIFO's */ 7077 static void mvpp2_rx_fifo_init(struct mvpp2 *priv) 7078 { 7079 int port; 7080 7081 for (port = 0; port < MVPP2_MAX_PORTS; port++) { 7082 mvpp2_write(priv, MVPP2_RX_DATA_FIFO_SIZE_REG(port), 7083 MVPP2_RX_FIFO_PORT_DATA_SIZE_4KB); 7084 mvpp2_write(priv, MVPP2_RX_ATTR_FIFO_SIZE_REG(port), 7085 MVPP2_RX_FIFO_PORT_ATTR_SIZE_4KB); 7086 } 7087 7088 mvpp2_write(priv, MVPP2_RX_MIN_PKT_SIZE_REG, 7089 MVPP2_RX_FIFO_PORT_MIN_PKT); 7090 mvpp2_write(priv, MVPP2_RX_FIFO_INIT_REG, 0x1); 7091 } 7092 7093 static void mvpp22_rx_fifo_set_hw(struct mvpp2 *priv, int port, int data_size) 7094 { 7095 int attr_size = MVPP2_RX_FIFO_PORT_ATTR_SIZE(data_size); 7096 7097 mvpp2_write(priv, MVPP2_RX_DATA_FIFO_SIZE_REG(port), data_size); 7098 mvpp2_write(priv, MVPP2_RX_ATTR_FIFO_SIZE_REG(port), attr_size); 7099 } 7100 7101 /* Initialize TX FIFO's: the total FIFO size is 48kB on PPv2.2 and PPv2.3. 7102 * 4kB fixed space must be assigned for the loopback port. 7103 * Redistribute remaining avialable 44kB space among all active ports. 7104 * Guarantee minimum 32kB for 10G port and 8kB for port 1, capable of 2.5G 7105 * SGMII link. 7106 */ 7107 static void mvpp22_rx_fifo_init(struct mvpp2 *priv) 7108 { 7109 int remaining_ports_count; 7110 unsigned long port_map; 7111 int size_remainder; 7112 int port, size; 7113 7114 /* The loopback requires fixed 4kB of the FIFO space assignment. */ 7115 mvpp22_rx_fifo_set_hw(priv, MVPP2_LOOPBACK_PORT_INDEX, 7116 MVPP2_RX_FIFO_PORT_DATA_SIZE_4KB); 7117 port_map = priv->port_map & ~BIT(MVPP2_LOOPBACK_PORT_INDEX); 7118 7119 /* Set RX FIFO size to 0 for inactive ports. */ 7120 for_each_clear_bit(port, &port_map, MVPP2_LOOPBACK_PORT_INDEX) 7121 mvpp22_rx_fifo_set_hw(priv, port, 0); 7122 7123 /* Assign remaining RX FIFO space among all active ports. */ 7124 size_remainder = MVPP2_RX_FIFO_PORT_DATA_SIZE_44KB; 7125 remaining_ports_count = hweight_long(port_map); 7126 7127 for_each_set_bit(port, &port_map, MVPP2_LOOPBACK_PORT_INDEX) { 7128 if (remaining_ports_count == 1) 7129 size = size_remainder; 7130 else if (port == 0) 7131 size = max(size_remainder / remaining_ports_count, 7132 MVPP2_RX_FIFO_PORT_DATA_SIZE_32KB); 7133 else if (port == 1) 7134 size = max(size_remainder / remaining_ports_count, 7135 MVPP2_RX_FIFO_PORT_DATA_SIZE_8KB); 7136 else 7137 size = size_remainder / remaining_ports_count; 7138 7139 size_remainder -= size; 7140 remaining_ports_count--; 7141 7142 mvpp22_rx_fifo_set_hw(priv, port, size); 7143 } 7144 7145 mvpp2_write(priv, MVPP2_RX_MIN_PKT_SIZE_REG, 7146 MVPP2_RX_FIFO_PORT_MIN_PKT); 7147 mvpp2_write(priv, MVPP2_RX_FIFO_INIT_REG, 0x1); 7148 } 7149 7150 /* Configure Rx FIFO Flow control thresholds */ 7151 static void mvpp23_rx_fifo_fc_set_tresh(struct mvpp2 *priv) 7152 { 7153 int port, val; 7154 7155 /* Port 0: maximum speed -10Gb/s port 7156 * required by spec RX FIFO threshold 9KB 7157 * Port 1: maximum speed -5Gb/s port 7158 * required by spec RX FIFO threshold 4KB 7159 * Port 2: maximum speed -1Gb/s port 7160 * required by spec RX FIFO threshold 2KB 7161 */ 7162 7163 /* Without loopback port */ 7164 for (port = 0; port < (MVPP2_MAX_PORTS - 1); port++) { 7165 if (port == 0) { 7166 val = (MVPP23_PORT0_FIFO_TRSH / MVPP2_RX_FC_TRSH_UNIT) 7167 << MVPP2_RX_FC_TRSH_OFFS; 7168 val &= MVPP2_RX_FC_TRSH_MASK; 7169 mvpp2_write(priv, MVPP2_RX_FC_REG(port), val); 7170 } else if (port == 1) { 7171 val = (MVPP23_PORT1_FIFO_TRSH / MVPP2_RX_FC_TRSH_UNIT) 7172 << MVPP2_RX_FC_TRSH_OFFS; 7173 val &= MVPP2_RX_FC_TRSH_MASK; 7174 mvpp2_write(priv, MVPP2_RX_FC_REG(port), val); 7175 } else { 7176 val = (MVPP23_PORT2_FIFO_TRSH / MVPP2_RX_FC_TRSH_UNIT) 7177 << MVPP2_RX_FC_TRSH_OFFS; 7178 val &= MVPP2_RX_FC_TRSH_MASK; 7179 mvpp2_write(priv, MVPP2_RX_FC_REG(port), val); 7180 } 7181 } 7182 } 7183 7184 /* Configure Rx FIFO Flow control thresholds */ 7185 void mvpp23_rx_fifo_fc_en(struct mvpp2 *priv, int port, bool en) 7186 { 7187 int val; 7188 7189 val = mvpp2_read(priv, MVPP2_RX_FC_REG(port)); 7190 7191 if (en) 7192 val |= MVPP2_RX_FC_EN; 7193 else 7194 val &= ~MVPP2_RX_FC_EN; 7195 7196 mvpp2_write(priv, MVPP2_RX_FC_REG(port), val); 7197 } 7198 7199 static void mvpp22_tx_fifo_set_hw(struct mvpp2 *priv, int port, int size) 7200 { 7201 int threshold = MVPP2_TX_FIFO_THRESHOLD(size); 7202 7203 mvpp2_write(priv, MVPP22_TX_FIFO_SIZE_REG(port), size); 7204 mvpp2_write(priv, MVPP22_TX_FIFO_THRESH_REG(port), threshold); 7205 } 7206 7207 /* Initialize TX FIFO's: the total FIFO size is 19kB on PPv2.2 and PPv2.3. 7208 * 1kB fixed space must be assigned for the loopback port. 7209 * Redistribute remaining avialable 18kB space among all active ports. 7210 * The 10G interface should use 10kB (which is maximum possible size 7211 * per single port). 7212 */ 7213 static void mvpp22_tx_fifo_init(struct mvpp2 *priv) 7214 { 7215 int remaining_ports_count; 7216 unsigned long port_map; 7217 int size_remainder; 7218 int port, size; 7219 7220 /* The loopback requires fixed 1kB of the FIFO space assignment. */ 7221 mvpp22_tx_fifo_set_hw(priv, MVPP2_LOOPBACK_PORT_INDEX, 7222 MVPP22_TX_FIFO_DATA_SIZE_1KB); 7223 port_map = priv->port_map & ~BIT(MVPP2_LOOPBACK_PORT_INDEX); 7224 7225 /* Set TX FIFO size to 0 for inactive ports. */ 7226 for_each_clear_bit(port, &port_map, MVPP2_LOOPBACK_PORT_INDEX) 7227 mvpp22_tx_fifo_set_hw(priv, port, 0); 7228 7229 /* Assign remaining TX FIFO space among all active ports. */ 7230 size_remainder = MVPP22_TX_FIFO_DATA_SIZE_18KB; 7231 remaining_ports_count = hweight_long(port_map); 7232 7233 for_each_set_bit(port, &port_map, MVPP2_LOOPBACK_PORT_INDEX) { 7234 if (remaining_ports_count == 1) 7235 size = min(size_remainder, 7236 MVPP22_TX_FIFO_DATA_SIZE_10KB); 7237 else if (port == 0) 7238 size = MVPP22_TX_FIFO_DATA_SIZE_10KB; 7239 else 7240 size = size_remainder / remaining_ports_count; 7241 7242 size_remainder -= size; 7243 remaining_ports_count--; 7244 7245 mvpp22_tx_fifo_set_hw(priv, port, size); 7246 } 7247 } 7248 7249 static void mvpp2_axi_init(struct mvpp2 *priv) 7250 { 7251 u32 val, rdval, wrval; 7252 7253 mvpp2_write(priv, MVPP22_BM_ADDR_HIGH_RLS_REG, 0x0); 7254 7255 /* AXI Bridge Configuration */ 7256 7257 rdval = MVPP22_AXI_CODE_CACHE_RD_CACHE 7258 << MVPP22_AXI_ATTR_CACHE_OFFS; 7259 rdval |= MVPP22_AXI_CODE_DOMAIN_OUTER_DOM 7260 << MVPP22_AXI_ATTR_DOMAIN_OFFS; 7261 7262 wrval = MVPP22_AXI_CODE_CACHE_WR_CACHE 7263 << MVPP22_AXI_ATTR_CACHE_OFFS; 7264 wrval |= MVPP22_AXI_CODE_DOMAIN_OUTER_DOM 7265 << MVPP22_AXI_ATTR_DOMAIN_OFFS; 7266 7267 /* BM */ 7268 mvpp2_write(priv, MVPP22_AXI_BM_WR_ATTR_REG, wrval); 7269 mvpp2_write(priv, MVPP22_AXI_BM_RD_ATTR_REG, rdval); 7270 7271 /* Descriptors */ 7272 mvpp2_write(priv, MVPP22_AXI_AGGRQ_DESCR_RD_ATTR_REG, rdval); 7273 mvpp2_write(priv, MVPP22_AXI_TXQ_DESCR_WR_ATTR_REG, wrval); 7274 mvpp2_write(priv, MVPP22_AXI_TXQ_DESCR_RD_ATTR_REG, rdval); 7275 mvpp2_write(priv, MVPP22_AXI_RXQ_DESCR_WR_ATTR_REG, wrval); 7276 7277 /* Buffer Data */ 7278 mvpp2_write(priv, MVPP22_AXI_TX_DATA_RD_ATTR_REG, rdval); 7279 mvpp2_write(priv, MVPP22_AXI_RX_DATA_WR_ATTR_REG, wrval); 7280 7281 val = MVPP22_AXI_CODE_CACHE_NON_CACHE 7282 << MVPP22_AXI_CODE_CACHE_OFFS; 7283 val |= MVPP22_AXI_CODE_DOMAIN_SYSTEM 7284 << MVPP22_AXI_CODE_DOMAIN_OFFS; 7285 mvpp2_write(priv, MVPP22_AXI_RD_NORMAL_CODE_REG, val); 7286 mvpp2_write(priv, MVPP22_AXI_WR_NORMAL_CODE_REG, val); 7287 7288 val = MVPP22_AXI_CODE_CACHE_RD_CACHE 7289 << MVPP22_AXI_CODE_CACHE_OFFS; 7290 val |= MVPP22_AXI_CODE_DOMAIN_OUTER_DOM 7291 << MVPP22_AXI_CODE_DOMAIN_OFFS; 7292 7293 mvpp2_write(priv, MVPP22_AXI_RD_SNOOP_CODE_REG, val); 7294 7295 val = MVPP22_AXI_CODE_CACHE_WR_CACHE 7296 << MVPP22_AXI_CODE_CACHE_OFFS; 7297 val |= MVPP22_AXI_CODE_DOMAIN_OUTER_DOM 7298 << MVPP22_AXI_CODE_DOMAIN_OFFS; 7299 7300 mvpp2_write(priv, MVPP22_AXI_WR_SNOOP_CODE_REG, val); 7301 } 7302 7303 /* Initialize network controller common part HW */ 7304 static int mvpp2_init(struct platform_device *pdev, struct mvpp2 *priv) 7305 { 7306 const struct mbus_dram_target_info *dram_target_info; 7307 int err, i; 7308 u32 val; 7309 7310 /* MBUS windows configuration */ 7311 dram_target_info = mv_mbus_dram_info(); 7312 if (dram_target_info) 7313 mvpp2_conf_mbus_windows(dram_target_info, priv); 7314 7315 if (priv->hw_version >= MVPP22) 7316 mvpp2_axi_init(priv); 7317 7318 /* Disable HW PHY polling */ 7319 if (priv->hw_version == MVPP21) { 7320 val = readl(priv->lms_base + MVPP2_PHY_AN_CFG0_REG); 7321 val |= MVPP2_PHY_AN_STOP_SMI0_MASK; 7322 writel(val, priv->lms_base + MVPP2_PHY_AN_CFG0_REG); 7323 } else { 7324 val = readl(priv->iface_base + MVPP22_SMI_MISC_CFG_REG); 7325 val &= ~MVPP22_SMI_POLLING_EN; 7326 writel(val, priv->iface_base + MVPP22_SMI_MISC_CFG_REG); 7327 } 7328 7329 /* Allocate and initialize aggregated TXQs */ 7330 priv->aggr_txqs = devm_kcalloc(&pdev->dev, MVPP2_MAX_THREADS, 7331 sizeof(*priv->aggr_txqs), 7332 GFP_KERNEL); 7333 if (!priv->aggr_txqs) 7334 return -ENOMEM; 7335 7336 for (i = 0; i < MVPP2_MAX_THREADS; i++) { 7337 priv->aggr_txqs[i].id = i; 7338 priv->aggr_txqs[i].size = MVPP2_AGGR_TXQ_SIZE; 7339 err = mvpp2_aggr_txq_init(pdev, &priv->aggr_txqs[i], i, priv); 7340 if (err < 0) 7341 return err; 7342 } 7343 7344 /* Fifo Init */ 7345 if (priv->hw_version == MVPP21) { 7346 mvpp2_rx_fifo_init(priv); 7347 } else { 7348 mvpp22_rx_fifo_init(priv); 7349 mvpp22_tx_fifo_init(priv); 7350 if (priv->hw_version == MVPP23) 7351 mvpp23_rx_fifo_fc_set_tresh(priv); 7352 } 7353 7354 if (priv->hw_version == MVPP21) 7355 writel(MVPP2_EXT_GLOBAL_CTRL_DEFAULT, 7356 priv->lms_base + MVPP2_MNG_EXTENDED_GLOBAL_CTRL_REG); 7357 7358 /* Allow cache snoop when transmiting packets */ 7359 mvpp2_write(priv, MVPP2_TX_SNOOP_REG, 0x1); 7360 7361 /* Buffer Manager initialization */ 7362 err = mvpp2_bm_init(&pdev->dev, priv); 7363 if (err < 0) 7364 return err; 7365 7366 /* Parser default initialization */ 7367 err = mvpp2_prs_default_init(pdev, priv); 7368 if (err < 0) 7369 return err; 7370 7371 /* Classifier default initialization */ 7372 mvpp2_cls_init(priv); 7373 7374 return 0; 7375 } 7376 7377 static int mvpp2_get_sram(struct platform_device *pdev, 7378 struct mvpp2 *priv) 7379 { 7380 struct resource *res; 7381 void __iomem *base; 7382 7383 res = platform_get_resource(pdev, IORESOURCE_MEM, 2); 7384 if (!res) { 7385 if (has_acpi_companion(&pdev->dev)) 7386 dev_warn(&pdev->dev, "ACPI is too old, Flow control not supported\n"); 7387 else 7388 dev_warn(&pdev->dev, "DT is too old, Flow control not supported\n"); 7389 return 0; 7390 } 7391 7392 base = devm_ioremap_resource(&pdev->dev, res); 7393 if (IS_ERR(base)) 7394 return PTR_ERR(base); 7395 7396 priv->cm3_base = base; 7397 return 0; 7398 } 7399 7400 static int mvpp2_probe(struct platform_device *pdev) 7401 { 7402 struct fwnode_handle *fwnode = pdev->dev.fwnode; 7403 struct fwnode_handle *port_fwnode; 7404 struct mvpp2 *priv; 7405 struct resource *res; 7406 void __iomem *base; 7407 int i, shared; 7408 int err; 7409 7410 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); 7411 if (!priv) 7412 return -ENOMEM; 7413 7414 priv->hw_version = (unsigned long)device_get_match_data(&pdev->dev); 7415 7416 /* multi queue mode isn't supported on PPV2.1, fallback to single 7417 * mode 7418 */ 7419 if (priv->hw_version == MVPP21) 7420 queue_mode = MVPP2_QDIST_SINGLE_MODE; 7421 7422 base = devm_platform_ioremap_resource(pdev, 0); 7423 if (IS_ERR(base)) 7424 return PTR_ERR(base); 7425 7426 if (priv->hw_version == MVPP21) { 7427 priv->lms_base = devm_platform_ioremap_resource(pdev, 1); 7428 if (IS_ERR(priv->lms_base)) 7429 return PTR_ERR(priv->lms_base); 7430 } else { 7431 res = platform_get_resource(pdev, IORESOURCE_MEM, 1); 7432 if (!res) { 7433 dev_err(&pdev->dev, "Invalid resource\n"); 7434 return -EINVAL; 7435 } 7436 if (has_acpi_companion(&pdev->dev)) { 7437 /* In case the MDIO memory region is declared in 7438 * the ACPI, it can already appear as 'in-use' 7439 * in the OS. Because it is overlapped by second 7440 * region of the network controller, make 7441 * sure it is released, before requesting it again. 7442 * The care is taken by mvpp2 driver to avoid 7443 * concurrent access to this memory region. 7444 */ 7445 release_resource(res); 7446 } 7447 priv->iface_base = devm_ioremap_resource(&pdev->dev, res); 7448 if (IS_ERR(priv->iface_base)) 7449 return PTR_ERR(priv->iface_base); 7450 7451 /* Map CM3 SRAM */ 7452 err = mvpp2_get_sram(pdev, priv); 7453 if (err) 7454 dev_warn(&pdev->dev, "Fail to alloc CM3 SRAM\n"); 7455 7456 /* Enable global Flow Control only if handler to SRAM not NULL */ 7457 if (priv->cm3_base) 7458 priv->global_tx_fc = true; 7459 } 7460 7461 if (priv->hw_version >= MVPP22 && dev_of_node(&pdev->dev)) { 7462 priv->sysctrl_base = 7463 syscon_regmap_lookup_by_phandle(pdev->dev.of_node, 7464 "marvell,system-controller"); 7465 if (IS_ERR(priv->sysctrl_base)) 7466 /* The system controller regmap is optional for dt 7467 * compatibility reasons. When not provided, the 7468 * configuration of the GoP relies on the 7469 * firmware/bootloader. 7470 */ 7471 priv->sysctrl_base = NULL; 7472 } 7473 7474 if (priv->hw_version >= MVPP22 && 7475 mvpp2_get_nrxqs(priv) * 2 <= MVPP2_BM_MAX_POOLS) 7476 priv->percpu_pools = 1; 7477 7478 mvpp2_setup_bm_pool(); 7479 7480 7481 priv->nthreads = min_t(unsigned int, num_present_cpus(), 7482 MVPP2_MAX_THREADS); 7483 7484 shared = num_present_cpus() - priv->nthreads; 7485 if (shared > 0) 7486 bitmap_set(&priv->lock_map, 0, 7487 min_t(int, shared, MVPP2_MAX_THREADS)); 7488 7489 for (i = 0; i < MVPP2_MAX_THREADS; i++) { 7490 u32 addr_space_sz; 7491 7492 addr_space_sz = (priv->hw_version == MVPP21 ? 7493 MVPP21_ADDR_SPACE_SZ : MVPP22_ADDR_SPACE_SZ); 7494 priv->swth_base[i] = base + i * addr_space_sz; 7495 } 7496 7497 if (priv->hw_version == MVPP21) 7498 priv->max_port_rxqs = 8; 7499 else 7500 priv->max_port_rxqs = 32; 7501 7502 if (dev_of_node(&pdev->dev)) { 7503 priv->pp_clk = devm_clk_get(&pdev->dev, "pp_clk"); 7504 if (IS_ERR(priv->pp_clk)) 7505 return PTR_ERR(priv->pp_clk); 7506 err = clk_prepare_enable(priv->pp_clk); 7507 if (err < 0) 7508 return err; 7509 7510 priv->gop_clk = devm_clk_get(&pdev->dev, "gop_clk"); 7511 if (IS_ERR(priv->gop_clk)) { 7512 err = PTR_ERR(priv->gop_clk); 7513 goto err_pp_clk; 7514 } 7515 err = clk_prepare_enable(priv->gop_clk); 7516 if (err < 0) 7517 goto err_pp_clk; 7518 7519 if (priv->hw_version >= MVPP22) { 7520 priv->mg_clk = devm_clk_get(&pdev->dev, "mg_clk"); 7521 if (IS_ERR(priv->mg_clk)) { 7522 err = PTR_ERR(priv->mg_clk); 7523 goto err_gop_clk; 7524 } 7525 7526 err = clk_prepare_enable(priv->mg_clk); 7527 if (err < 0) 7528 goto err_gop_clk; 7529 7530 priv->mg_core_clk = devm_clk_get_optional(&pdev->dev, "mg_core_clk"); 7531 if (IS_ERR(priv->mg_core_clk)) { 7532 err = PTR_ERR(priv->mg_core_clk); 7533 goto err_mg_clk; 7534 } 7535 7536 err = clk_prepare_enable(priv->mg_core_clk); 7537 if (err < 0) 7538 goto err_mg_clk; 7539 } 7540 7541 priv->axi_clk = devm_clk_get_optional(&pdev->dev, "axi_clk"); 7542 if (IS_ERR(priv->axi_clk)) { 7543 err = PTR_ERR(priv->axi_clk); 7544 goto err_mg_core_clk; 7545 } 7546 7547 err = clk_prepare_enable(priv->axi_clk); 7548 if (err < 0) 7549 goto err_mg_core_clk; 7550 7551 /* Get system's tclk rate */ 7552 priv->tclk = clk_get_rate(priv->pp_clk); 7553 } else { 7554 err = device_property_read_u32(&pdev->dev, "clock-frequency", &priv->tclk); 7555 if (err) { 7556 dev_err(&pdev->dev, "missing clock-frequency value\n"); 7557 return err; 7558 } 7559 } 7560 7561 if (priv->hw_version >= MVPP22) { 7562 err = dma_set_mask(&pdev->dev, MVPP2_DESC_DMA_MASK); 7563 if (err) 7564 goto err_axi_clk; 7565 /* Sadly, the BM pools all share the same register to 7566 * store the high 32 bits of their address. So they 7567 * must all have the same high 32 bits, which forces 7568 * us to restrict coherent memory to DMA_BIT_MASK(32). 7569 */ 7570 err = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32)); 7571 if (err) 7572 goto err_axi_clk; 7573 } 7574 7575 /* Map DTS-active ports. Should be done before FIFO mvpp2_init */ 7576 fwnode_for_each_available_child_node(fwnode, port_fwnode) { 7577 if (!fwnode_property_read_u32(port_fwnode, "port-id", &i)) 7578 priv->port_map |= BIT(i); 7579 } 7580 7581 if (mvpp2_read(priv, MVPP2_VER_ID_REG) == MVPP2_VER_PP23) 7582 priv->hw_version = MVPP23; 7583 7584 /* Init mss lock */ 7585 spin_lock_init(&priv->mss_spinlock); 7586 7587 /* Initialize network controller */ 7588 err = mvpp2_init(pdev, priv); 7589 if (err < 0) { 7590 dev_err(&pdev->dev, "failed to initialize controller\n"); 7591 goto err_axi_clk; 7592 } 7593 7594 err = mvpp22_tai_probe(&pdev->dev, priv); 7595 if (err < 0) 7596 goto err_axi_clk; 7597 7598 /* Initialize ports */ 7599 fwnode_for_each_available_child_node(fwnode, port_fwnode) { 7600 err = mvpp2_port_probe(pdev, port_fwnode, priv); 7601 if (err < 0) 7602 goto err_port_probe; 7603 } 7604 7605 if (priv->port_count == 0) { 7606 dev_err(&pdev->dev, "no ports enabled\n"); 7607 err = -ENODEV; 7608 goto err_axi_clk; 7609 } 7610 7611 /* Statistics must be gathered regularly because some of them (like 7612 * packets counters) are 32-bit registers and could overflow quite 7613 * quickly. For instance, a 10Gb link used at full bandwidth with the 7614 * smallest packets (64B) will overflow a 32-bit counter in less than 7615 * 30 seconds. Then, use a workqueue to fill 64-bit counters. 7616 */ 7617 snprintf(priv->queue_name, sizeof(priv->queue_name), 7618 "stats-wq-%s%s", netdev_name(priv->port_list[0]->dev), 7619 priv->port_count > 1 ? "+" : ""); 7620 priv->stats_queue = create_singlethread_workqueue(priv->queue_name); 7621 if (!priv->stats_queue) { 7622 err = -ENOMEM; 7623 goto err_port_probe; 7624 } 7625 7626 if (priv->global_tx_fc && priv->hw_version >= MVPP22) { 7627 err = mvpp2_enable_global_fc(priv); 7628 if (err) 7629 dev_warn(&pdev->dev, "Minimum of CM3 firmware 18.09 and chip revision B0 required for flow control\n"); 7630 } 7631 7632 mvpp2_dbgfs_init(priv, pdev->name); 7633 7634 platform_set_drvdata(pdev, priv); 7635 return 0; 7636 7637 err_port_probe: 7638 fwnode_handle_put(port_fwnode); 7639 7640 i = 0; 7641 fwnode_for_each_available_child_node(fwnode, port_fwnode) { 7642 if (priv->port_list[i]) 7643 mvpp2_port_remove(priv->port_list[i]); 7644 i++; 7645 } 7646 err_axi_clk: 7647 clk_disable_unprepare(priv->axi_clk); 7648 err_mg_core_clk: 7649 clk_disable_unprepare(priv->mg_core_clk); 7650 err_mg_clk: 7651 clk_disable_unprepare(priv->mg_clk); 7652 err_gop_clk: 7653 clk_disable_unprepare(priv->gop_clk); 7654 err_pp_clk: 7655 clk_disable_unprepare(priv->pp_clk); 7656 return err; 7657 } 7658 7659 static int mvpp2_remove(struct platform_device *pdev) 7660 { 7661 struct mvpp2 *priv = platform_get_drvdata(pdev); 7662 struct fwnode_handle *fwnode = pdev->dev.fwnode; 7663 int i = 0, poolnum = MVPP2_BM_POOLS_NUM; 7664 struct fwnode_handle *port_fwnode; 7665 7666 mvpp2_dbgfs_cleanup(priv); 7667 7668 fwnode_for_each_available_child_node(fwnode, port_fwnode) { 7669 if (priv->port_list[i]) { 7670 mutex_destroy(&priv->port_list[i]->gather_stats_lock); 7671 mvpp2_port_remove(priv->port_list[i]); 7672 } 7673 i++; 7674 } 7675 7676 destroy_workqueue(priv->stats_queue); 7677 7678 if (priv->percpu_pools) 7679 poolnum = mvpp2_get_nrxqs(priv) * 2; 7680 7681 for (i = 0; i < poolnum; i++) { 7682 struct mvpp2_bm_pool *bm_pool = &priv->bm_pools[i]; 7683 7684 mvpp2_bm_pool_destroy(&pdev->dev, priv, bm_pool); 7685 } 7686 7687 for (i = 0; i < MVPP2_MAX_THREADS; i++) { 7688 struct mvpp2_tx_queue *aggr_txq = &priv->aggr_txqs[i]; 7689 7690 dma_free_coherent(&pdev->dev, 7691 MVPP2_AGGR_TXQ_SIZE * MVPP2_DESC_ALIGNED_SIZE, 7692 aggr_txq->descs, 7693 aggr_txq->descs_dma); 7694 } 7695 7696 if (is_acpi_node(port_fwnode)) 7697 return 0; 7698 7699 clk_disable_unprepare(priv->axi_clk); 7700 clk_disable_unprepare(priv->mg_core_clk); 7701 clk_disable_unprepare(priv->mg_clk); 7702 clk_disable_unprepare(priv->pp_clk); 7703 clk_disable_unprepare(priv->gop_clk); 7704 7705 return 0; 7706 } 7707 7708 static const struct of_device_id mvpp2_match[] = { 7709 { 7710 .compatible = "marvell,armada-375-pp2", 7711 .data = (void *)MVPP21, 7712 }, 7713 { 7714 .compatible = "marvell,armada-7k-pp22", 7715 .data = (void *)MVPP22, 7716 }, 7717 { } 7718 }; 7719 MODULE_DEVICE_TABLE(of, mvpp2_match); 7720 7721 #ifdef CONFIG_ACPI 7722 static const struct acpi_device_id mvpp2_acpi_match[] = { 7723 { "MRVL0110", MVPP22 }, 7724 { }, 7725 }; 7726 MODULE_DEVICE_TABLE(acpi, mvpp2_acpi_match); 7727 #endif 7728 7729 static struct platform_driver mvpp2_driver = { 7730 .probe = mvpp2_probe, 7731 .remove = mvpp2_remove, 7732 .driver = { 7733 .name = MVPP2_DRIVER_NAME, 7734 .of_match_table = mvpp2_match, 7735 .acpi_match_table = ACPI_PTR(mvpp2_acpi_match), 7736 }, 7737 }; 7738 7739 static int __init mvpp2_driver_init(void) 7740 { 7741 return platform_driver_register(&mvpp2_driver); 7742 } 7743 module_init(mvpp2_driver_init); 7744 7745 static void __exit mvpp2_driver_exit(void) 7746 { 7747 platform_driver_unregister(&mvpp2_driver); 7748 mvpp2_dbgfs_exit(); 7749 } 7750 module_exit(mvpp2_driver_exit); 7751 7752 MODULE_DESCRIPTION("Marvell PPv2 Ethernet Driver - www.marvell.com"); 7753 MODULE_AUTHOR("Marcin Wojtas <mw@semihalf.com>"); 7754 MODULE_LICENSE("GPL v2"); 7755