1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Driver for Marvell PPv2 network controller for Armada 375 SoC. 4 * 5 * Copyright (C) 2014 Marvell 6 * 7 * Marcin Wojtas <mw@semihalf.com> 8 */ 9 10 #include <linux/acpi.h> 11 #include <linux/kernel.h> 12 #include <linux/netdevice.h> 13 #include <linux/etherdevice.h> 14 #include <linux/platform_device.h> 15 #include <linux/skbuff.h> 16 #include <linux/inetdevice.h> 17 #include <linux/mbus.h> 18 #include <linux/module.h> 19 #include <linux/mfd/syscon.h> 20 #include <linux/interrupt.h> 21 #include <linux/cpumask.h> 22 #include <linux/of.h> 23 #include <linux/of_irq.h> 24 #include <linux/of_mdio.h> 25 #include <linux/of_net.h> 26 #include <linux/of_address.h> 27 #include <linux/of_device.h> 28 #include <linux/phy.h> 29 #include <linux/phylink.h> 30 #include <linux/phy/phy.h> 31 #include <linux/ptp_classify.h> 32 #include <linux/clk.h> 33 #include <linux/hrtimer.h> 34 #include <linux/ktime.h> 35 #include <linux/regmap.h> 36 #include <uapi/linux/ppp_defs.h> 37 #include <net/ip.h> 38 #include <net/ipv6.h> 39 #include <net/tso.h> 40 #include <linux/bpf_trace.h> 41 42 #include "mvpp2.h" 43 #include "mvpp2_prs.h" 44 #include "mvpp2_cls.h" 45 46 enum mvpp2_bm_pool_log_num { 47 MVPP2_BM_SHORT, 48 MVPP2_BM_LONG, 49 MVPP2_BM_JUMBO, 50 MVPP2_BM_POOLS_NUM 51 }; 52 53 static struct { 54 int pkt_size; 55 int buf_num; 56 } mvpp2_pools[MVPP2_BM_POOLS_NUM]; 57 58 /* The prototype is added here to be used in start_dev when using ACPI. This 59 * will be removed once phylink is used for all modes (dt+ACPI). 60 */ 61 static void mvpp2_acpi_start(struct mvpp2_port *port); 62 63 /* Queue modes */ 64 #define MVPP2_QDIST_SINGLE_MODE 0 65 #define MVPP2_QDIST_MULTI_MODE 1 66 67 static int queue_mode = MVPP2_QDIST_MULTI_MODE; 68 69 module_param(queue_mode, int, 0444); 70 MODULE_PARM_DESC(queue_mode, "Set queue_mode (single=0, multi=1)"); 71 72 /* Utility/helper methods */ 73 74 void mvpp2_write(struct mvpp2 *priv, u32 offset, u32 data) 75 { 76 writel(data, priv->swth_base[0] + offset); 77 } 78 79 u32 mvpp2_read(struct mvpp2 *priv, u32 offset) 80 { 81 return readl(priv->swth_base[0] + offset); 82 } 83 84 static u32 mvpp2_read_relaxed(struct mvpp2 *priv, u32 offset) 85 { 86 return readl_relaxed(priv->swth_base[0] + offset); 87 } 88 89 static inline u32 mvpp2_cpu_to_thread(struct mvpp2 *priv, int cpu) 90 { 91 return cpu % priv->nthreads; 92 } 93 94 static void mvpp2_cm3_write(struct mvpp2 *priv, u32 offset, u32 data) 95 { 96 writel(data, priv->cm3_base + offset); 97 } 98 99 static u32 mvpp2_cm3_read(struct mvpp2 *priv, u32 offset) 100 { 101 return readl(priv->cm3_base + offset); 102 } 103 104 static struct page_pool * 105 mvpp2_create_page_pool(struct device *dev, int num, int len, 106 enum dma_data_direction dma_dir) 107 { 108 struct page_pool_params pp_params = { 109 /* internal DMA mapping in page_pool */ 110 .flags = PP_FLAG_DMA_MAP | PP_FLAG_DMA_SYNC_DEV, 111 .pool_size = num, 112 .nid = NUMA_NO_NODE, 113 .dev = dev, 114 .dma_dir = dma_dir, 115 .offset = MVPP2_SKB_HEADROOM, 116 .max_len = len, 117 }; 118 119 return page_pool_create(&pp_params); 120 } 121 122 /* These accessors should be used to access: 123 * 124 * - per-thread registers, where each thread has its own copy of the 125 * register. 126 * 127 * MVPP2_BM_VIRT_ALLOC_REG 128 * MVPP2_BM_ADDR_HIGH_ALLOC 129 * MVPP22_BM_ADDR_HIGH_RLS_REG 130 * MVPP2_BM_VIRT_RLS_REG 131 * MVPP2_ISR_RX_TX_CAUSE_REG 132 * MVPP2_ISR_RX_TX_MASK_REG 133 * MVPP2_TXQ_NUM_REG 134 * MVPP2_AGGR_TXQ_UPDATE_REG 135 * MVPP2_TXQ_RSVD_REQ_REG 136 * MVPP2_TXQ_RSVD_RSLT_REG 137 * MVPP2_TXQ_SENT_REG 138 * MVPP2_RXQ_NUM_REG 139 * 140 * - global registers that must be accessed through a specific thread 141 * window, because they are related to an access to a per-thread 142 * register 143 * 144 * MVPP2_BM_PHY_ALLOC_REG (related to MVPP2_BM_VIRT_ALLOC_REG) 145 * MVPP2_BM_PHY_RLS_REG (related to MVPP2_BM_VIRT_RLS_REG) 146 * MVPP2_RXQ_THRESH_REG (related to MVPP2_RXQ_NUM_REG) 147 * MVPP2_RXQ_DESC_ADDR_REG (related to MVPP2_RXQ_NUM_REG) 148 * MVPP2_RXQ_DESC_SIZE_REG (related to MVPP2_RXQ_NUM_REG) 149 * MVPP2_RXQ_INDEX_REG (related to MVPP2_RXQ_NUM_REG) 150 * MVPP2_TXQ_PENDING_REG (related to MVPP2_TXQ_NUM_REG) 151 * MVPP2_TXQ_DESC_ADDR_REG (related to MVPP2_TXQ_NUM_REG) 152 * MVPP2_TXQ_DESC_SIZE_REG (related to MVPP2_TXQ_NUM_REG) 153 * MVPP2_TXQ_INDEX_REG (related to MVPP2_TXQ_NUM_REG) 154 * MVPP2_TXQ_PENDING_REG (related to MVPP2_TXQ_NUM_REG) 155 * MVPP2_TXQ_PREF_BUF_REG (related to MVPP2_TXQ_NUM_REG) 156 * MVPP2_TXQ_PREF_BUF_REG (related to MVPP2_TXQ_NUM_REG) 157 */ 158 static void mvpp2_thread_write(struct mvpp2 *priv, unsigned int thread, 159 u32 offset, u32 data) 160 { 161 writel(data, priv->swth_base[thread] + offset); 162 } 163 164 static u32 mvpp2_thread_read(struct mvpp2 *priv, unsigned int thread, 165 u32 offset) 166 { 167 return readl(priv->swth_base[thread] + offset); 168 } 169 170 static void mvpp2_thread_write_relaxed(struct mvpp2 *priv, unsigned int thread, 171 u32 offset, u32 data) 172 { 173 writel_relaxed(data, priv->swth_base[thread] + offset); 174 } 175 176 static u32 mvpp2_thread_read_relaxed(struct mvpp2 *priv, unsigned int thread, 177 u32 offset) 178 { 179 return readl_relaxed(priv->swth_base[thread] + offset); 180 } 181 182 static dma_addr_t mvpp2_txdesc_dma_addr_get(struct mvpp2_port *port, 183 struct mvpp2_tx_desc *tx_desc) 184 { 185 if (port->priv->hw_version == MVPP21) 186 return le32_to_cpu(tx_desc->pp21.buf_dma_addr); 187 else 188 return le64_to_cpu(tx_desc->pp22.buf_dma_addr_ptp) & 189 MVPP2_DESC_DMA_MASK; 190 } 191 192 static void mvpp2_txdesc_dma_addr_set(struct mvpp2_port *port, 193 struct mvpp2_tx_desc *tx_desc, 194 dma_addr_t dma_addr) 195 { 196 dma_addr_t addr, offset; 197 198 addr = dma_addr & ~MVPP2_TX_DESC_ALIGN; 199 offset = dma_addr & MVPP2_TX_DESC_ALIGN; 200 201 if (port->priv->hw_version == MVPP21) { 202 tx_desc->pp21.buf_dma_addr = cpu_to_le32(addr); 203 tx_desc->pp21.packet_offset = offset; 204 } else { 205 __le64 val = cpu_to_le64(addr); 206 207 tx_desc->pp22.buf_dma_addr_ptp &= ~cpu_to_le64(MVPP2_DESC_DMA_MASK); 208 tx_desc->pp22.buf_dma_addr_ptp |= val; 209 tx_desc->pp22.packet_offset = offset; 210 } 211 } 212 213 static size_t mvpp2_txdesc_size_get(struct mvpp2_port *port, 214 struct mvpp2_tx_desc *tx_desc) 215 { 216 if (port->priv->hw_version == MVPP21) 217 return le16_to_cpu(tx_desc->pp21.data_size); 218 else 219 return le16_to_cpu(tx_desc->pp22.data_size); 220 } 221 222 static void mvpp2_txdesc_size_set(struct mvpp2_port *port, 223 struct mvpp2_tx_desc *tx_desc, 224 size_t size) 225 { 226 if (port->priv->hw_version == MVPP21) 227 tx_desc->pp21.data_size = cpu_to_le16(size); 228 else 229 tx_desc->pp22.data_size = cpu_to_le16(size); 230 } 231 232 static void mvpp2_txdesc_txq_set(struct mvpp2_port *port, 233 struct mvpp2_tx_desc *tx_desc, 234 unsigned int txq) 235 { 236 if (port->priv->hw_version == MVPP21) 237 tx_desc->pp21.phys_txq = txq; 238 else 239 tx_desc->pp22.phys_txq = txq; 240 } 241 242 static void mvpp2_txdesc_cmd_set(struct mvpp2_port *port, 243 struct mvpp2_tx_desc *tx_desc, 244 unsigned int command) 245 { 246 if (port->priv->hw_version == MVPP21) 247 tx_desc->pp21.command = cpu_to_le32(command); 248 else 249 tx_desc->pp22.command = cpu_to_le32(command); 250 } 251 252 static unsigned int mvpp2_txdesc_offset_get(struct mvpp2_port *port, 253 struct mvpp2_tx_desc *tx_desc) 254 { 255 if (port->priv->hw_version == MVPP21) 256 return tx_desc->pp21.packet_offset; 257 else 258 return tx_desc->pp22.packet_offset; 259 } 260 261 static dma_addr_t mvpp2_rxdesc_dma_addr_get(struct mvpp2_port *port, 262 struct mvpp2_rx_desc *rx_desc) 263 { 264 if (port->priv->hw_version == MVPP21) 265 return le32_to_cpu(rx_desc->pp21.buf_dma_addr); 266 else 267 return le64_to_cpu(rx_desc->pp22.buf_dma_addr_key_hash) & 268 MVPP2_DESC_DMA_MASK; 269 } 270 271 static unsigned long mvpp2_rxdesc_cookie_get(struct mvpp2_port *port, 272 struct mvpp2_rx_desc *rx_desc) 273 { 274 if (port->priv->hw_version == MVPP21) 275 return le32_to_cpu(rx_desc->pp21.buf_cookie); 276 else 277 return le64_to_cpu(rx_desc->pp22.buf_cookie_misc) & 278 MVPP2_DESC_DMA_MASK; 279 } 280 281 static size_t mvpp2_rxdesc_size_get(struct mvpp2_port *port, 282 struct mvpp2_rx_desc *rx_desc) 283 { 284 if (port->priv->hw_version == MVPP21) 285 return le16_to_cpu(rx_desc->pp21.data_size); 286 else 287 return le16_to_cpu(rx_desc->pp22.data_size); 288 } 289 290 static u32 mvpp2_rxdesc_status_get(struct mvpp2_port *port, 291 struct mvpp2_rx_desc *rx_desc) 292 { 293 if (port->priv->hw_version == MVPP21) 294 return le32_to_cpu(rx_desc->pp21.status); 295 else 296 return le32_to_cpu(rx_desc->pp22.status); 297 } 298 299 static void mvpp2_txq_inc_get(struct mvpp2_txq_pcpu *txq_pcpu) 300 { 301 txq_pcpu->txq_get_index++; 302 if (txq_pcpu->txq_get_index == txq_pcpu->size) 303 txq_pcpu->txq_get_index = 0; 304 } 305 306 static void mvpp2_txq_inc_put(struct mvpp2_port *port, 307 struct mvpp2_txq_pcpu *txq_pcpu, 308 void *data, 309 struct mvpp2_tx_desc *tx_desc, 310 enum mvpp2_tx_buf_type buf_type) 311 { 312 struct mvpp2_txq_pcpu_buf *tx_buf = 313 txq_pcpu->buffs + txq_pcpu->txq_put_index; 314 tx_buf->type = buf_type; 315 if (buf_type == MVPP2_TYPE_SKB) 316 tx_buf->skb = data; 317 else 318 tx_buf->xdpf = data; 319 tx_buf->size = mvpp2_txdesc_size_get(port, tx_desc); 320 tx_buf->dma = mvpp2_txdesc_dma_addr_get(port, tx_desc) + 321 mvpp2_txdesc_offset_get(port, tx_desc); 322 txq_pcpu->txq_put_index++; 323 if (txq_pcpu->txq_put_index == txq_pcpu->size) 324 txq_pcpu->txq_put_index = 0; 325 } 326 327 /* Get number of maximum RXQ */ 328 static int mvpp2_get_nrxqs(struct mvpp2 *priv) 329 { 330 unsigned int nrxqs; 331 332 if (priv->hw_version >= MVPP22 && queue_mode == MVPP2_QDIST_SINGLE_MODE) 333 return 1; 334 335 /* According to the PPv2.2 datasheet and our experiments on 336 * PPv2.1, RX queues have an allocation granularity of 4 (when 337 * more than a single one on PPv2.2). 338 * Round up to nearest multiple of 4. 339 */ 340 nrxqs = (num_possible_cpus() + 3) & ~0x3; 341 if (nrxqs > MVPP2_PORT_MAX_RXQ) 342 nrxqs = MVPP2_PORT_MAX_RXQ; 343 344 return nrxqs; 345 } 346 347 /* Get number of physical egress port */ 348 static inline int mvpp2_egress_port(struct mvpp2_port *port) 349 { 350 return MVPP2_MAX_TCONT + port->id; 351 } 352 353 /* Get number of physical TXQ */ 354 static inline int mvpp2_txq_phys(int port, int txq) 355 { 356 return (MVPP2_MAX_TCONT + port) * MVPP2_MAX_TXQ + txq; 357 } 358 359 /* Returns a struct page if page_pool is set, otherwise a buffer */ 360 static void *mvpp2_frag_alloc(const struct mvpp2_bm_pool *pool, 361 struct page_pool *page_pool) 362 { 363 if (page_pool) 364 return page_pool_dev_alloc_pages(page_pool); 365 366 if (likely(pool->frag_size <= PAGE_SIZE)) 367 return netdev_alloc_frag(pool->frag_size); 368 369 return kmalloc(pool->frag_size, GFP_ATOMIC); 370 } 371 372 static void mvpp2_frag_free(const struct mvpp2_bm_pool *pool, 373 struct page_pool *page_pool, void *data) 374 { 375 if (page_pool) 376 page_pool_put_full_page(page_pool, virt_to_head_page(data), false); 377 else if (likely(pool->frag_size <= PAGE_SIZE)) 378 skb_free_frag(data); 379 else 380 kfree(data); 381 } 382 383 /* Buffer Manager configuration routines */ 384 385 /* Create pool */ 386 static int mvpp2_bm_pool_create(struct device *dev, struct mvpp2 *priv, 387 struct mvpp2_bm_pool *bm_pool, int size) 388 { 389 u32 val; 390 391 /* Number of buffer pointers must be a multiple of 16, as per 392 * hardware constraints 393 */ 394 if (!IS_ALIGNED(size, 16)) 395 return -EINVAL; 396 397 /* PPv2.1 needs 8 bytes per buffer pointer, PPv2.2 and PPv2.3 needs 16 398 * bytes per buffer pointer 399 */ 400 if (priv->hw_version == MVPP21) 401 bm_pool->size_bytes = 2 * sizeof(u32) * size; 402 else 403 bm_pool->size_bytes = 2 * sizeof(u64) * size; 404 405 bm_pool->virt_addr = dma_alloc_coherent(dev, bm_pool->size_bytes, 406 &bm_pool->dma_addr, 407 GFP_KERNEL); 408 if (!bm_pool->virt_addr) 409 return -ENOMEM; 410 411 if (!IS_ALIGNED((unsigned long)bm_pool->virt_addr, 412 MVPP2_BM_POOL_PTR_ALIGN)) { 413 dma_free_coherent(dev, bm_pool->size_bytes, 414 bm_pool->virt_addr, bm_pool->dma_addr); 415 dev_err(dev, "BM pool %d is not %d bytes aligned\n", 416 bm_pool->id, MVPP2_BM_POOL_PTR_ALIGN); 417 return -ENOMEM; 418 } 419 420 mvpp2_write(priv, MVPP2_BM_POOL_BASE_REG(bm_pool->id), 421 lower_32_bits(bm_pool->dma_addr)); 422 mvpp2_write(priv, MVPP2_BM_POOL_SIZE_REG(bm_pool->id), size); 423 424 val = mvpp2_read(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id)); 425 val |= MVPP2_BM_START_MASK; 426 427 val &= ~MVPP2_BM_LOW_THRESH_MASK; 428 val &= ~MVPP2_BM_HIGH_THRESH_MASK; 429 430 /* Set 8 Pools BPPI threshold for MVPP23 */ 431 if (priv->hw_version == MVPP23) { 432 val |= MVPP2_BM_LOW_THRESH_VALUE(MVPP23_BM_BPPI_LOW_THRESH); 433 val |= MVPP2_BM_HIGH_THRESH_VALUE(MVPP23_BM_BPPI_HIGH_THRESH); 434 } else { 435 val |= MVPP2_BM_LOW_THRESH_VALUE(MVPP2_BM_BPPI_LOW_THRESH); 436 val |= MVPP2_BM_HIGH_THRESH_VALUE(MVPP2_BM_BPPI_HIGH_THRESH); 437 } 438 439 mvpp2_write(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id), val); 440 441 bm_pool->size = size; 442 bm_pool->pkt_size = 0; 443 bm_pool->buf_num = 0; 444 445 return 0; 446 } 447 448 /* Set pool buffer size */ 449 static void mvpp2_bm_pool_bufsize_set(struct mvpp2 *priv, 450 struct mvpp2_bm_pool *bm_pool, 451 int buf_size) 452 { 453 u32 val; 454 455 bm_pool->buf_size = buf_size; 456 457 val = ALIGN(buf_size, 1 << MVPP2_POOL_BUF_SIZE_OFFSET); 458 mvpp2_write(priv, MVPP2_POOL_BUF_SIZE_REG(bm_pool->id), val); 459 } 460 461 static void mvpp2_bm_bufs_get_addrs(struct device *dev, struct mvpp2 *priv, 462 struct mvpp2_bm_pool *bm_pool, 463 dma_addr_t *dma_addr, 464 phys_addr_t *phys_addr) 465 { 466 unsigned int thread = mvpp2_cpu_to_thread(priv, get_cpu()); 467 468 *dma_addr = mvpp2_thread_read(priv, thread, 469 MVPP2_BM_PHY_ALLOC_REG(bm_pool->id)); 470 *phys_addr = mvpp2_thread_read(priv, thread, MVPP2_BM_VIRT_ALLOC_REG); 471 472 if (priv->hw_version >= MVPP22) { 473 u32 val; 474 u32 dma_addr_highbits, phys_addr_highbits; 475 476 val = mvpp2_thread_read(priv, thread, MVPP22_BM_ADDR_HIGH_ALLOC); 477 dma_addr_highbits = (val & MVPP22_BM_ADDR_HIGH_PHYS_MASK); 478 phys_addr_highbits = (val & MVPP22_BM_ADDR_HIGH_VIRT_MASK) >> 479 MVPP22_BM_ADDR_HIGH_VIRT_SHIFT; 480 481 if (sizeof(dma_addr_t) == 8) 482 *dma_addr |= (u64)dma_addr_highbits << 32; 483 484 if (sizeof(phys_addr_t) == 8) 485 *phys_addr |= (u64)phys_addr_highbits << 32; 486 } 487 488 put_cpu(); 489 } 490 491 /* Free all buffers from the pool */ 492 static void mvpp2_bm_bufs_free(struct device *dev, struct mvpp2 *priv, 493 struct mvpp2_bm_pool *bm_pool, int buf_num) 494 { 495 struct page_pool *pp = NULL; 496 int i; 497 498 if (buf_num > bm_pool->buf_num) { 499 WARN(1, "Pool does not have so many bufs pool(%d) bufs(%d)\n", 500 bm_pool->id, buf_num); 501 buf_num = bm_pool->buf_num; 502 } 503 504 if (priv->percpu_pools) 505 pp = priv->page_pool[bm_pool->id]; 506 507 for (i = 0; i < buf_num; i++) { 508 dma_addr_t buf_dma_addr; 509 phys_addr_t buf_phys_addr; 510 void *data; 511 512 mvpp2_bm_bufs_get_addrs(dev, priv, bm_pool, 513 &buf_dma_addr, &buf_phys_addr); 514 515 if (!pp) 516 dma_unmap_single(dev, buf_dma_addr, 517 bm_pool->buf_size, DMA_FROM_DEVICE); 518 519 data = (void *)phys_to_virt(buf_phys_addr); 520 if (!data) 521 break; 522 523 mvpp2_frag_free(bm_pool, pp, data); 524 } 525 526 /* Update BM driver with number of buffers removed from pool */ 527 bm_pool->buf_num -= i; 528 } 529 530 /* Check number of buffers in BM pool */ 531 static int mvpp2_check_hw_buf_num(struct mvpp2 *priv, struct mvpp2_bm_pool *bm_pool) 532 { 533 int buf_num = 0; 534 535 buf_num += mvpp2_read(priv, MVPP2_BM_POOL_PTRS_NUM_REG(bm_pool->id)) & 536 MVPP22_BM_POOL_PTRS_NUM_MASK; 537 buf_num += mvpp2_read(priv, MVPP2_BM_BPPI_PTRS_NUM_REG(bm_pool->id)) & 538 MVPP2_BM_BPPI_PTR_NUM_MASK; 539 540 /* HW has one buffer ready which is not reflected in the counters */ 541 if (buf_num) 542 buf_num += 1; 543 544 return buf_num; 545 } 546 547 /* Cleanup pool */ 548 static int mvpp2_bm_pool_destroy(struct device *dev, struct mvpp2 *priv, 549 struct mvpp2_bm_pool *bm_pool) 550 { 551 int buf_num; 552 u32 val; 553 554 buf_num = mvpp2_check_hw_buf_num(priv, bm_pool); 555 mvpp2_bm_bufs_free(dev, priv, bm_pool, buf_num); 556 557 /* Check buffer counters after free */ 558 buf_num = mvpp2_check_hw_buf_num(priv, bm_pool); 559 if (buf_num) { 560 WARN(1, "cannot free all buffers in pool %d, buf_num left %d\n", 561 bm_pool->id, bm_pool->buf_num); 562 return 0; 563 } 564 565 val = mvpp2_read(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id)); 566 val |= MVPP2_BM_STOP_MASK; 567 mvpp2_write(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id), val); 568 569 if (priv->percpu_pools) { 570 page_pool_destroy(priv->page_pool[bm_pool->id]); 571 priv->page_pool[bm_pool->id] = NULL; 572 } 573 574 dma_free_coherent(dev, bm_pool->size_bytes, 575 bm_pool->virt_addr, 576 bm_pool->dma_addr); 577 return 0; 578 } 579 580 static int mvpp2_bm_pools_init(struct device *dev, struct mvpp2 *priv) 581 { 582 int i, err, size, poolnum = MVPP2_BM_POOLS_NUM; 583 struct mvpp2_bm_pool *bm_pool; 584 585 if (priv->percpu_pools) 586 poolnum = mvpp2_get_nrxqs(priv) * 2; 587 588 /* Create all pools with maximum size */ 589 size = MVPP2_BM_POOL_SIZE_MAX; 590 for (i = 0; i < poolnum; i++) { 591 bm_pool = &priv->bm_pools[i]; 592 bm_pool->id = i; 593 err = mvpp2_bm_pool_create(dev, priv, bm_pool, size); 594 if (err) 595 goto err_unroll_pools; 596 mvpp2_bm_pool_bufsize_set(priv, bm_pool, 0); 597 } 598 return 0; 599 600 err_unroll_pools: 601 dev_err(dev, "failed to create BM pool %d, size %d\n", i, size); 602 for (i = i - 1; i >= 0; i--) 603 mvpp2_bm_pool_destroy(dev, priv, &priv->bm_pools[i]); 604 return err; 605 } 606 607 /* Routine enable PPv23 8 pool mode */ 608 static void mvpp23_bm_set_8pool_mode(struct mvpp2 *priv) 609 { 610 int val; 611 612 val = mvpp2_read(priv, MVPP22_BM_POOL_BASE_ADDR_HIGH_REG); 613 val |= MVPP23_BM_8POOL_MODE; 614 mvpp2_write(priv, MVPP22_BM_POOL_BASE_ADDR_HIGH_REG, val); 615 } 616 617 static int mvpp2_bm_init(struct device *dev, struct mvpp2 *priv) 618 { 619 enum dma_data_direction dma_dir = DMA_FROM_DEVICE; 620 int i, err, poolnum = MVPP2_BM_POOLS_NUM; 621 struct mvpp2_port *port; 622 623 if (priv->percpu_pools) { 624 for (i = 0; i < priv->port_count; i++) { 625 port = priv->port_list[i]; 626 if (port->xdp_prog) { 627 dma_dir = DMA_BIDIRECTIONAL; 628 break; 629 } 630 } 631 632 poolnum = mvpp2_get_nrxqs(priv) * 2; 633 for (i = 0; i < poolnum; i++) { 634 /* the pool in use */ 635 int pn = i / (poolnum / 2); 636 637 priv->page_pool[i] = 638 mvpp2_create_page_pool(dev, 639 mvpp2_pools[pn].buf_num, 640 mvpp2_pools[pn].pkt_size, 641 dma_dir); 642 if (IS_ERR(priv->page_pool[i])) { 643 int j; 644 645 for (j = 0; j < i; j++) { 646 page_pool_destroy(priv->page_pool[j]); 647 priv->page_pool[j] = NULL; 648 } 649 return PTR_ERR(priv->page_pool[i]); 650 } 651 } 652 } 653 654 dev_info(dev, "using %d %s buffers\n", poolnum, 655 priv->percpu_pools ? "per-cpu" : "shared"); 656 657 for (i = 0; i < poolnum; i++) { 658 /* Mask BM all interrupts */ 659 mvpp2_write(priv, MVPP2_BM_INTR_MASK_REG(i), 0); 660 /* Clear BM cause register */ 661 mvpp2_write(priv, MVPP2_BM_INTR_CAUSE_REG(i), 0); 662 } 663 664 /* Allocate and initialize BM pools */ 665 priv->bm_pools = devm_kcalloc(dev, poolnum, 666 sizeof(*priv->bm_pools), GFP_KERNEL); 667 if (!priv->bm_pools) 668 return -ENOMEM; 669 670 if (priv->hw_version == MVPP23) 671 mvpp23_bm_set_8pool_mode(priv); 672 673 err = mvpp2_bm_pools_init(dev, priv); 674 if (err < 0) 675 return err; 676 return 0; 677 } 678 679 static void mvpp2_setup_bm_pool(void) 680 { 681 /* Short pool */ 682 mvpp2_pools[MVPP2_BM_SHORT].buf_num = MVPP2_BM_SHORT_BUF_NUM; 683 mvpp2_pools[MVPP2_BM_SHORT].pkt_size = MVPP2_BM_SHORT_PKT_SIZE; 684 685 /* Long pool */ 686 mvpp2_pools[MVPP2_BM_LONG].buf_num = MVPP2_BM_LONG_BUF_NUM; 687 mvpp2_pools[MVPP2_BM_LONG].pkt_size = MVPP2_BM_LONG_PKT_SIZE; 688 689 /* Jumbo pool */ 690 mvpp2_pools[MVPP2_BM_JUMBO].buf_num = MVPP2_BM_JUMBO_BUF_NUM; 691 mvpp2_pools[MVPP2_BM_JUMBO].pkt_size = MVPP2_BM_JUMBO_PKT_SIZE; 692 } 693 694 /* Attach long pool to rxq */ 695 static void mvpp2_rxq_long_pool_set(struct mvpp2_port *port, 696 int lrxq, int long_pool) 697 { 698 u32 val, mask; 699 int prxq; 700 701 /* Get queue physical ID */ 702 prxq = port->rxqs[lrxq]->id; 703 704 if (port->priv->hw_version == MVPP21) 705 mask = MVPP21_RXQ_POOL_LONG_MASK; 706 else 707 mask = MVPP22_RXQ_POOL_LONG_MASK; 708 709 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(prxq)); 710 val &= ~mask; 711 val |= (long_pool << MVPP2_RXQ_POOL_LONG_OFFS) & mask; 712 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(prxq), val); 713 } 714 715 /* Attach short pool to rxq */ 716 static void mvpp2_rxq_short_pool_set(struct mvpp2_port *port, 717 int lrxq, int short_pool) 718 { 719 u32 val, mask; 720 int prxq; 721 722 /* Get queue physical ID */ 723 prxq = port->rxqs[lrxq]->id; 724 725 if (port->priv->hw_version == MVPP21) 726 mask = MVPP21_RXQ_POOL_SHORT_MASK; 727 else 728 mask = MVPP22_RXQ_POOL_SHORT_MASK; 729 730 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(prxq)); 731 val &= ~mask; 732 val |= (short_pool << MVPP2_RXQ_POOL_SHORT_OFFS) & mask; 733 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(prxq), val); 734 } 735 736 static void *mvpp2_buf_alloc(struct mvpp2_port *port, 737 struct mvpp2_bm_pool *bm_pool, 738 struct page_pool *page_pool, 739 dma_addr_t *buf_dma_addr, 740 phys_addr_t *buf_phys_addr, 741 gfp_t gfp_mask) 742 { 743 dma_addr_t dma_addr; 744 struct page *page; 745 void *data; 746 747 data = mvpp2_frag_alloc(bm_pool, page_pool); 748 if (!data) 749 return NULL; 750 751 if (page_pool) { 752 page = (struct page *)data; 753 dma_addr = page_pool_get_dma_addr(page); 754 data = page_to_virt(page); 755 } else { 756 dma_addr = dma_map_single(port->dev->dev.parent, data, 757 MVPP2_RX_BUF_SIZE(bm_pool->pkt_size), 758 DMA_FROM_DEVICE); 759 if (unlikely(dma_mapping_error(port->dev->dev.parent, dma_addr))) { 760 mvpp2_frag_free(bm_pool, NULL, data); 761 return NULL; 762 } 763 } 764 *buf_dma_addr = dma_addr; 765 *buf_phys_addr = virt_to_phys(data); 766 767 return data; 768 } 769 770 /* Routine enable flow control for RXQs condition */ 771 static void mvpp2_rxq_enable_fc(struct mvpp2_port *port) 772 { 773 int val, cm3_state, host_id, q; 774 int fq = port->first_rxq; 775 unsigned long flags; 776 777 spin_lock_irqsave(&port->priv->mss_spinlock, flags); 778 779 /* Remove Flow control enable bit to prevent race between FW and Kernel 780 * If Flow control was enabled, it would be re-enabled. 781 */ 782 val = mvpp2_cm3_read(port->priv, MSS_FC_COM_REG); 783 cm3_state = (val & FLOW_CONTROL_ENABLE_BIT); 784 val &= ~FLOW_CONTROL_ENABLE_BIT; 785 mvpp2_cm3_write(port->priv, MSS_FC_COM_REG, val); 786 787 /* Set same Flow control for all RXQs */ 788 for (q = 0; q < port->nrxqs; q++) { 789 /* Set stop and start Flow control RXQ thresholds */ 790 val = MSS_THRESHOLD_START; 791 val |= (MSS_THRESHOLD_STOP << MSS_RXQ_TRESH_STOP_OFFS); 792 mvpp2_cm3_write(port->priv, MSS_RXQ_TRESH_REG(q, fq), val); 793 794 val = mvpp2_cm3_read(port->priv, MSS_RXQ_ASS_REG(q, fq)); 795 /* Set RXQ port ID */ 796 val &= ~(MSS_RXQ_ASS_PORTID_MASK << MSS_RXQ_ASS_Q_BASE(q, fq)); 797 val |= (port->id << MSS_RXQ_ASS_Q_BASE(q, fq)); 798 val &= ~(MSS_RXQ_ASS_HOSTID_MASK << (MSS_RXQ_ASS_Q_BASE(q, fq) 799 + MSS_RXQ_ASS_HOSTID_OFFS)); 800 801 /* Calculate RXQ host ID: 802 * In Single queue mode: Host ID equal to Host ID used for 803 * shared RX interrupt 804 * In Multi queue mode: Host ID equal to number of 805 * RXQ ID / number of CoS queues 806 * In Single resource mode: Host ID always equal to 0 807 */ 808 if (queue_mode == MVPP2_QDIST_SINGLE_MODE) 809 host_id = port->nqvecs; 810 else if (queue_mode == MVPP2_QDIST_MULTI_MODE) 811 host_id = q; 812 else 813 host_id = 0; 814 815 /* Set RXQ host ID */ 816 val |= (host_id << (MSS_RXQ_ASS_Q_BASE(q, fq) 817 + MSS_RXQ_ASS_HOSTID_OFFS)); 818 819 mvpp2_cm3_write(port->priv, MSS_RXQ_ASS_REG(q, fq), val); 820 } 821 822 /* Notify Firmware that Flow control config space ready for update */ 823 val = mvpp2_cm3_read(port->priv, MSS_FC_COM_REG); 824 val |= FLOW_CONTROL_UPDATE_COMMAND_BIT; 825 val |= cm3_state; 826 mvpp2_cm3_write(port->priv, MSS_FC_COM_REG, val); 827 828 spin_unlock_irqrestore(&port->priv->mss_spinlock, flags); 829 } 830 831 /* Routine disable flow control for RXQs condition */ 832 static void mvpp2_rxq_disable_fc(struct mvpp2_port *port) 833 { 834 int val, cm3_state, q; 835 unsigned long flags; 836 int fq = port->first_rxq; 837 838 spin_lock_irqsave(&port->priv->mss_spinlock, flags); 839 840 /* Remove Flow control enable bit to prevent race between FW and Kernel 841 * If Flow control was enabled, it would be re-enabled. 842 */ 843 val = mvpp2_cm3_read(port->priv, MSS_FC_COM_REG); 844 cm3_state = (val & FLOW_CONTROL_ENABLE_BIT); 845 val &= ~FLOW_CONTROL_ENABLE_BIT; 846 mvpp2_cm3_write(port->priv, MSS_FC_COM_REG, val); 847 848 /* Disable Flow control for all RXQs */ 849 for (q = 0; q < port->nrxqs; q++) { 850 /* Set threshold 0 to disable Flow control */ 851 val = 0; 852 val |= (0 << MSS_RXQ_TRESH_STOP_OFFS); 853 mvpp2_cm3_write(port->priv, MSS_RXQ_TRESH_REG(q, fq), val); 854 855 val = mvpp2_cm3_read(port->priv, MSS_RXQ_ASS_REG(q, fq)); 856 857 val &= ~(MSS_RXQ_ASS_PORTID_MASK << MSS_RXQ_ASS_Q_BASE(q, fq)); 858 859 val &= ~(MSS_RXQ_ASS_HOSTID_MASK << (MSS_RXQ_ASS_Q_BASE(q, fq) 860 + MSS_RXQ_ASS_HOSTID_OFFS)); 861 862 mvpp2_cm3_write(port->priv, MSS_RXQ_ASS_REG(q, fq), val); 863 } 864 865 /* Notify Firmware that Flow control config space ready for update */ 866 val = mvpp2_cm3_read(port->priv, MSS_FC_COM_REG); 867 val |= FLOW_CONTROL_UPDATE_COMMAND_BIT; 868 val |= cm3_state; 869 mvpp2_cm3_write(port->priv, MSS_FC_COM_REG, val); 870 871 spin_unlock_irqrestore(&port->priv->mss_spinlock, flags); 872 } 873 874 /* Routine disable/enable flow control for BM pool condition */ 875 static void mvpp2_bm_pool_update_fc(struct mvpp2_port *port, 876 struct mvpp2_bm_pool *pool, 877 bool en) 878 { 879 int val, cm3_state; 880 unsigned long flags; 881 882 spin_lock_irqsave(&port->priv->mss_spinlock, flags); 883 884 /* Remove Flow control enable bit to prevent race between FW and Kernel 885 * If Flow control were enabled, it would be re-enabled. 886 */ 887 val = mvpp2_cm3_read(port->priv, MSS_FC_COM_REG); 888 cm3_state = (val & FLOW_CONTROL_ENABLE_BIT); 889 val &= ~FLOW_CONTROL_ENABLE_BIT; 890 mvpp2_cm3_write(port->priv, MSS_FC_COM_REG, val); 891 892 /* Check if BM pool should be enabled/disable */ 893 if (en) { 894 /* Set BM pool start and stop thresholds per port */ 895 val = mvpp2_cm3_read(port->priv, MSS_BUF_POOL_REG(pool->id)); 896 val |= MSS_BUF_POOL_PORT_OFFS(port->id); 897 val &= ~MSS_BUF_POOL_START_MASK; 898 val |= (MSS_THRESHOLD_START << MSS_BUF_POOL_START_OFFS); 899 val &= ~MSS_BUF_POOL_STOP_MASK; 900 val |= MSS_THRESHOLD_STOP; 901 mvpp2_cm3_write(port->priv, MSS_BUF_POOL_REG(pool->id), val); 902 } else { 903 /* Remove BM pool from the port */ 904 val = mvpp2_cm3_read(port->priv, MSS_BUF_POOL_REG(pool->id)); 905 val &= ~MSS_BUF_POOL_PORT_OFFS(port->id); 906 907 /* Zero BM pool start and stop thresholds to disable pool 908 * flow control if pool empty (not used by any port) 909 */ 910 if (!pool->buf_num) { 911 val &= ~MSS_BUF_POOL_START_MASK; 912 val &= ~MSS_BUF_POOL_STOP_MASK; 913 } 914 915 mvpp2_cm3_write(port->priv, MSS_BUF_POOL_REG(pool->id), val); 916 } 917 918 /* Notify Firmware that Flow control config space ready for update */ 919 val = mvpp2_cm3_read(port->priv, MSS_FC_COM_REG); 920 val |= FLOW_CONTROL_UPDATE_COMMAND_BIT; 921 val |= cm3_state; 922 mvpp2_cm3_write(port->priv, MSS_FC_COM_REG, val); 923 924 spin_unlock_irqrestore(&port->priv->mss_spinlock, flags); 925 } 926 927 /* disable/enable flow control for BM pool on all ports */ 928 static void mvpp2_bm_pool_update_priv_fc(struct mvpp2 *priv, bool en) 929 { 930 struct mvpp2_port *port; 931 int i; 932 933 for (i = 0; i < priv->port_count; i++) { 934 port = priv->port_list[i]; 935 if (port->priv->percpu_pools) { 936 for (i = 0; i < port->nrxqs; i++) 937 mvpp2_bm_pool_update_fc(port, &port->priv->bm_pools[i], 938 port->tx_fc & en); 939 } else { 940 mvpp2_bm_pool_update_fc(port, port->pool_long, port->tx_fc & en); 941 mvpp2_bm_pool_update_fc(port, port->pool_short, port->tx_fc & en); 942 } 943 } 944 } 945 946 static int mvpp2_enable_global_fc(struct mvpp2 *priv) 947 { 948 int val, timeout = 0; 949 950 /* Enable global flow control. In this stage global 951 * flow control enabled, but still disabled per port. 952 */ 953 val = mvpp2_cm3_read(priv, MSS_FC_COM_REG); 954 val |= FLOW_CONTROL_ENABLE_BIT; 955 mvpp2_cm3_write(priv, MSS_FC_COM_REG, val); 956 957 /* Check if Firmware running and disable FC if not*/ 958 val |= FLOW_CONTROL_UPDATE_COMMAND_BIT; 959 mvpp2_cm3_write(priv, MSS_FC_COM_REG, val); 960 961 while (timeout < MSS_FC_MAX_TIMEOUT) { 962 val = mvpp2_cm3_read(priv, MSS_FC_COM_REG); 963 964 if (!(val & FLOW_CONTROL_UPDATE_COMMAND_BIT)) 965 return 0; 966 usleep_range(10, 20); 967 timeout++; 968 } 969 970 priv->global_tx_fc = false; 971 return -EOPNOTSUPP; 972 } 973 974 /* Release buffer to BM */ 975 static inline void mvpp2_bm_pool_put(struct mvpp2_port *port, int pool, 976 dma_addr_t buf_dma_addr, 977 phys_addr_t buf_phys_addr) 978 { 979 unsigned int thread = mvpp2_cpu_to_thread(port->priv, get_cpu()); 980 unsigned long flags = 0; 981 982 if (test_bit(thread, &port->priv->lock_map)) 983 spin_lock_irqsave(&port->bm_lock[thread], flags); 984 985 if (port->priv->hw_version >= MVPP22) { 986 u32 val = 0; 987 988 if (sizeof(dma_addr_t) == 8) 989 val |= upper_32_bits(buf_dma_addr) & 990 MVPP22_BM_ADDR_HIGH_PHYS_RLS_MASK; 991 992 if (sizeof(phys_addr_t) == 8) 993 val |= (upper_32_bits(buf_phys_addr) 994 << MVPP22_BM_ADDR_HIGH_VIRT_RLS_SHIFT) & 995 MVPP22_BM_ADDR_HIGH_VIRT_RLS_MASK; 996 997 mvpp2_thread_write_relaxed(port->priv, thread, 998 MVPP22_BM_ADDR_HIGH_RLS_REG, val); 999 } 1000 1001 /* MVPP2_BM_VIRT_RLS_REG is not interpreted by HW, and simply 1002 * returned in the "cookie" field of the RX 1003 * descriptor. Instead of storing the virtual address, we 1004 * store the physical address 1005 */ 1006 mvpp2_thread_write_relaxed(port->priv, thread, 1007 MVPP2_BM_VIRT_RLS_REG, buf_phys_addr); 1008 mvpp2_thread_write_relaxed(port->priv, thread, 1009 MVPP2_BM_PHY_RLS_REG(pool), buf_dma_addr); 1010 1011 if (test_bit(thread, &port->priv->lock_map)) 1012 spin_unlock_irqrestore(&port->bm_lock[thread], flags); 1013 1014 put_cpu(); 1015 } 1016 1017 /* Allocate buffers for the pool */ 1018 static int mvpp2_bm_bufs_add(struct mvpp2_port *port, 1019 struct mvpp2_bm_pool *bm_pool, int buf_num) 1020 { 1021 int i, buf_size, total_size; 1022 dma_addr_t dma_addr; 1023 phys_addr_t phys_addr; 1024 struct page_pool *pp = NULL; 1025 void *buf; 1026 1027 if (port->priv->percpu_pools && 1028 bm_pool->pkt_size > MVPP2_BM_LONG_PKT_SIZE) { 1029 netdev_err(port->dev, 1030 "attempted to use jumbo frames with per-cpu pools"); 1031 return 0; 1032 } 1033 1034 buf_size = MVPP2_RX_BUF_SIZE(bm_pool->pkt_size); 1035 total_size = MVPP2_RX_TOTAL_SIZE(buf_size); 1036 1037 if (buf_num < 0 || 1038 (buf_num + bm_pool->buf_num > bm_pool->size)) { 1039 netdev_err(port->dev, 1040 "cannot allocate %d buffers for pool %d\n", 1041 buf_num, bm_pool->id); 1042 return 0; 1043 } 1044 1045 if (port->priv->percpu_pools) 1046 pp = port->priv->page_pool[bm_pool->id]; 1047 for (i = 0; i < buf_num; i++) { 1048 buf = mvpp2_buf_alloc(port, bm_pool, pp, &dma_addr, 1049 &phys_addr, GFP_KERNEL); 1050 if (!buf) 1051 break; 1052 1053 mvpp2_bm_pool_put(port, bm_pool->id, dma_addr, 1054 phys_addr); 1055 } 1056 1057 /* Update BM driver with number of buffers added to pool */ 1058 bm_pool->buf_num += i; 1059 1060 netdev_dbg(port->dev, 1061 "pool %d: pkt_size=%4d, buf_size=%4d, total_size=%4d\n", 1062 bm_pool->id, bm_pool->pkt_size, buf_size, total_size); 1063 1064 netdev_dbg(port->dev, 1065 "pool %d: %d of %d buffers added\n", 1066 bm_pool->id, i, buf_num); 1067 return i; 1068 } 1069 1070 /* Notify the driver that BM pool is being used as specific type and return the 1071 * pool pointer on success 1072 */ 1073 static struct mvpp2_bm_pool * 1074 mvpp2_bm_pool_use(struct mvpp2_port *port, unsigned pool, int pkt_size) 1075 { 1076 struct mvpp2_bm_pool *new_pool = &port->priv->bm_pools[pool]; 1077 int num; 1078 1079 if ((port->priv->percpu_pools && pool > mvpp2_get_nrxqs(port->priv) * 2) || 1080 (!port->priv->percpu_pools && pool >= MVPP2_BM_POOLS_NUM)) { 1081 netdev_err(port->dev, "Invalid pool %d\n", pool); 1082 return NULL; 1083 } 1084 1085 /* Allocate buffers in case BM pool is used as long pool, but packet 1086 * size doesn't match MTU or BM pool hasn't being used yet 1087 */ 1088 if (new_pool->pkt_size == 0) { 1089 int pkts_num; 1090 1091 /* Set default buffer number or free all the buffers in case 1092 * the pool is not empty 1093 */ 1094 pkts_num = new_pool->buf_num; 1095 if (pkts_num == 0) { 1096 if (port->priv->percpu_pools) { 1097 if (pool < port->nrxqs) 1098 pkts_num = mvpp2_pools[MVPP2_BM_SHORT].buf_num; 1099 else 1100 pkts_num = mvpp2_pools[MVPP2_BM_LONG].buf_num; 1101 } else { 1102 pkts_num = mvpp2_pools[pool].buf_num; 1103 } 1104 } else { 1105 mvpp2_bm_bufs_free(port->dev->dev.parent, 1106 port->priv, new_pool, pkts_num); 1107 } 1108 1109 new_pool->pkt_size = pkt_size; 1110 new_pool->frag_size = 1111 SKB_DATA_ALIGN(MVPP2_RX_BUF_SIZE(pkt_size)) + 1112 MVPP2_SKB_SHINFO_SIZE; 1113 1114 /* Allocate buffers for this pool */ 1115 num = mvpp2_bm_bufs_add(port, new_pool, pkts_num); 1116 if (num != pkts_num) { 1117 WARN(1, "pool %d: %d of %d allocated\n", 1118 new_pool->id, num, pkts_num); 1119 return NULL; 1120 } 1121 } 1122 1123 mvpp2_bm_pool_bufsize_set(port->priv, new_pool, 1124 MVPP2_RX_BUF_SIZE(new_pool->pkt_size)); 1125 1126 return new_pool; 1127 } 1128 1129 static struct mvpp2_bm_pool * 1130 mvpp2_bm_pool_use_percpu(struct mvpp2_port *port, int type, 1131 unsigned int pool, int pkt_size) 1132 { 1133 struct mvpp2_bm_pool *new_pool = &port->priv->bm_pools[pool]; 1134 int num; 1135 1136 if (pool > port->nrxqs * 2) { 1137 netdev_err(port->dev, "Invalid pool %d\n", pool); 1138 return NULL; 1139 } 1140 1141 /* Allocate buffers in case BM pool is used as long pool, but packet 1142 * size doesn't match MTU or BM pool hasn't being used yet 1143 */ 1144 if (new_pool->pkt_size == 0) { 1145 int pkts_num; 1146 1147 /* Set default buffer number or free all the buffers in case 1148 * the pool is not empty 1149 */ 1150 pkts_num = new_pool->buf_num; 1151 if (pkts_num == 0) 1152 pkts_num = mvpp2_pools[type].buf_num; 1153 else 1154 mvpp2_bm_bufs_free(port->dev->dev.parent, 1155 port->priv, new_pool, pkts_num); 1156 1157 new_pool->pkt_size = pkt_size; 1158 new_pool->frag_size = 1159 SKB_DATA_ALIGN(MVPP2_RX_BUF_SIZE(pkt_size)) + 1160 MVPP2_SKB_SHINFO_SIZE; 1161 1162 /* Allocate buffers for this pool */ 1163 num = mvpp2_bm_bufs_add(port, new_pool, pkts_num); 1164 if (num != pkts_num) { 1165 WARN(1, "pool %d: %d of %d allocated\n", 1166 new_pool->id, num, pkts_num); 1167 return NULL; 1168 } 1169 } 1170 1171 mvpp2_bm_pool_bufsize_set(port->priv, new_pool, 1172 MVPP2_RX_BUF_SIZE(new_pool->pkt_size)); 1173 1174 return new_pool; 1175 } 1176 1177 /* Initialize pools for swf, shared buffers variant */ 1178 static int mvpp2_swf_bm_pool_init_shared(struct mvpp2_port *port) 1179 { 1180 enum mvpp2_bm_pool_log_num long_log_pool, short_log_pool; 1181 int rxq; 1182 1183 /* If port pkt_size is higher than 1518B: 1184 * HW Long pool - SW Jumbo pool, HW Short pool - SW Long pool 1185 * else: HW Long pool - SW Long pool, HW Short pool - SW Short pool 1186 */ 1187 if (port->pkt_size > MVPP2_BM_LONG_PKT_SIZE) { 1188 long_log_pool = MVPP2_BM_JUMBO; 1189 short_log_pool = MVPP2_BM_LONG; 1190 } else { 1191 long_log_pool = MVPP2_BM_LONG; 1192 short_log_pool = MVPP2_BM_SHORT; 1193 } 1194 1195 if (!port->pool_long) { 1196 port->pool_long = 1197 mvpp2_bm_pool_use(port, long_log_pool, 1198 mvpp2_pools[long_log_pool].pkt_size); 1199 if (!port->pool_long) 1200 return -ENOMEM; 1201 1202 port->pool_long->port_map |= BIT(port->id); 1203 1204 for (rxq = 0; rxq < port->nrxqs; rxq++) 1205 mvpp2_rxq_long_pool_set(port, rxq, port->pool_long->id); 1206 } 1207 1208 if (!port->pool_short) { 1209 port->pool_short = 1210 mvpp2_bm_pool_use(port, short_log_pool, 1211 mvpp2_pools[short_log_pool].pkt_size); 1212 if (!port->pool_short) 1213 return -ENOMEM; 1214 1215 port->pool_short->port_map |= BIT(port->id); 1216 1217 for (rxq = 0; rxq < port->nrxqs; rxq++) 1218 mvpp2_rxq_short_pool_set(port, rxq, 1219 port->pool_short->id); 1220 } 1221 1222 return 0; 1223 } 1224 1225 /* Initialize pools for swf, percpu buffers variant */ 1226 static int mvpp2_swf_bm_pool_init_percpu(struct mvpp2_port *port) 1227 { 1228 struct mvpp2_bm_pool *bm_pool; 1229 int i; 1230 1231 for (i = 0; i < port->nrxqs; i++) { 1232 bm_pool = mvpp2_bm_pool_use_percpu(port, MVPP2_BM_SHORT, i, 1233 mvpp2_pools[MVPP2_BM_SHORT].pkt_size); 1234 if (!bm_pool) 1235 return -ENOMEM; 1236 1237 bm_pool->port_map |= BIT(port->id); 1238 mvpp2_rxq_short_pool_set(port, i, bm_pool->id); 1239 } 1240 1241 for (i = 0; i < port->nrxqs; i++) { 1242 bm_pool = mvpp2_bm_pool_use_percpu(port, MVPP2_BM_LONG, i + port->nrxqs, 1243 mvpp2_pools[MVPP2_BM_LONG].pkt_size); 1244 if (!bm_pool) 1245 return -ENOMEM; 1246 1247 bm_pool->port_map |= BIT(port->id); 1248 mvpp2_rxq_long_pool_set(port, i, bm_pool->id); 1249 } 1250 1251 port->pool_long = NULL; 1252 port->pool_short = NULL; 1253 1254 return 0; 1255 } 1256 1257 static int mvpp2_swf_bm_pool_init(struct mvpp2_port *port) 1258 { 1259 if (port->priv->percpu_pools) 1260 return mvpp2_swf_bm_pool_init_percpu(port); 1261 else 1262 return mvpp2_swf_bm_pool_init_shared(port); 1263 } 1264 1265 static void mvpp2_set_hw_csum(struct mvpp2_port *port, 1266 enum mvpp2_bm_pool_log_num new_long_pool) 1267 { 1268 const netdev_features_t csums = NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM; 1269 1270 /* Update L4 checksum when jumbo enable/disable on port. 1271 * Only port 0 supports hardware checksum offload due to 1272 * the Tx FIFO size limitation. 1273 * Also, don't set NETIF_F_HW_CSUM because L3_offset in TX descriptor 1274 * has 7 bits, so the maximum L3 offset is 128. 1275 */ 1276 if (new_long_pool == MVPP2_BM_JUMBO && port->id != 0) { 1277 port->dev->features &= ~csums; 1278 port->dev->hw_features &= ~csums; 1279 } else { 1280 port->dev->features |= csums; 1281 port->dev->hw_features |= csums; 1282 } 1283 } 1284 1285 static int mvpp2_bm_update_mtu(struct net_device *dev, int mtu) 1286 { 1287 struct mvpp2_port *port = netdev_priv(dev); 1288 enum mvpp2_bm_pool_log_num new_long_pool; 1289 int pkt_size = MVPP2_RX_PKT_SIZE(mtu); 1290 1291 if (port->priv->percpu_pools) 1292 goto out_set; 1293 1294 /* If port MTU is higher than 1518B: 1295 * HW Long pool - SW Jumbo pool, HW Short pool - SW Long pool 1296 * else: HW Long pool - SW Long pool, HW Short pool - SW Short pool 1297 */ 1298 if (pkt_size > MVPP2_BM_LONG_PKT_SIZE) 1299 new_long_pool = MVPP2_BM_JUMBO; 1300 else 1301 new_long_pool = MVPP2_BM_LONG; 1302 1303 if (new_long_pool != port->pool_long->id) { 1304 if (port->tx_fc) { 1305 if (pkt_size > MVPP2_BM_LONG_PKT_SIZE) 1306 mvpp2_bm_pool_update_fc(port, 1307 port->pool_short, 1308 false); 1309 else 1310 mvpp2_bm_pool_update_fc(port, port->pool_long, 1311 false); 1312 } 1313 1314 /* Remove port from old short & long pool */ 1315 port->pool_long = mvpp2_bm_pool_use(port, port->pool_long->id, 1316 port->pool_long->pkt_size); 1317 port->pool_long->port_map &= ~BIT(port->id); 1318 port->pool_long = NULL; 1319 1320 port->pool_short = mvpp2_bm_pool_use(port, port->pool_short->id, 1321 port->pool_short->pkt_size); 1322 port->pool_short->port_map &= ~BIT(port->id); 1323 port->pool_short = NULL; 1324 1325 port->pkt_size = pkt_size; 1326 1327 /* Add port to new short & long pool */ 1328 mvpp2_swf_bm_pool_init(port); 1329 1330 mvpp2_set_hw_csum(port, new_long_pool); 1331 1332 if (port->tx_fc) { 1333 if (pkt_size > MVPP2_BM_LONG_PKT_SIZE) 1334 mvpp2_bm_pool_update_fc(port, port->pool_long, 1335 true); 1336 else 1337 mvpp2_bm_pool_update_fc(port, port->pool_short, 1338 true); 1339 } 1340 1341 /* Update L4 checksum when jumbo enable/disable on port */ 1342 if (new_long_pool == MVPP2_BM_JUMBO && port->id != 0) { 1343 dev->features &= ~(NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM); 1344 dev->hw_features &= ~(NETIF_F_IP_CSUM | 1345 NETIF_F_IPV6_CSUM); 1346 } else { 1347 dev->features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM; 1348 dev->hw_features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM; 1349 } 1350 } 1351 1352 out_set: 1353 dev->mtu = mtu; 1354 dev->wanted_features = dev->features; 1355 1356 netdev_update_features(dev); 1357 return 0; 1358 } 1359 1360 static inline void mvpp2_interrupts_enable(struct mvpp2_port *port) 1361 { 1362 int i, sw_thread_mask = 0; 1363 1364 for (i = 0; i < port->nqvecs; i++) 1365 sw_thread_mask |= port->qvecs[i].sw_thread_mask; 1366 1367 mvpp2_write(port->priv, MVPP2_ISR_ENABLE_REG(port->id), 1368 MVPP2_ISR_ENABLE_INTERRUPT(sw_thread_mask)); 1369 } 1370 1371 static inline void mvpp2_interrupts_disable(struct mvpp2_port *port) 1372 { 1373 int i, sw_thread_mask = 0; 1374 1375 for (i = 0; i < port->nqvecs; i++) 1376 sw_thread_mask |= port->qvecs[i].sw_thread_mask; 1377 1378 mvpp2_write(port->priv, MVPP2_ISR_ENABLE_REG(port->id), 1379 MVPP2_ISR_DISABLE_INTERRUPT(sw_thread_mask)); 1380 } 1381 1382 static inline void mvpp2_qvec_interrupt_enable(struct mvpp2_queue_vector *qvec) 1383 { 1384 struct mvpp2_port *port = qvec->port; 1385 1386 mvpp2_write(port->priv, MVPP2_ISR_ENABLE_REG(port->id), 1387 MVPP2_ISR_ENABLE_INTERRUPT(qvec->sw_thread_mask)); 1388 } 1389 1390 static inline void mvpp2_qvec_interrupt_disable(struct mvpp2_queue_vector *qvec) 1391 { 1392 struct mvpp2_port *port = qvec->port; 1393 1394 mvpp2_write(port->priv, MVPP2_ISR_ENABLE_REG(port->id), 1395 MVPP2_ISR_DISABLE_INTERRUPT(qvec->sw_thread_mask)); 1396 } 1397 1398 /* Mask the current thread's Rx/Tx interrupts 1399 * Called by on_each_cpu(), guaranteed to run with migration disabled, 1400 * using smp_processor_id() is OK. 1401 */ 1402 static void mvpp2_interrupts_mask(void *arg) 1403 { 1404 struct mvpp2_port *port = arg; 1405 int cpu = smp_processor_id(); 1406 u32 thread; 1407 1408 /* If the thread isn't used, don't do anything */ 1409 if (cpu > port->priv->nthreads) 1410 return; 1411 1412 thread = mvpp2_cpu_to_thread(port->priv, cpu); 1413 1414 mvpp2_thread_write(port->priv, thread, 1415 MVPP2_ISR_RX_TX_MASK_REG(port->id), 0); 1416 mvpp2_thread_write(port->priv, thread, 1417 MVPP2_ISR_RX_ERR_CAUSE_REG(port->id), 0); 1418 } 1419 1420 /* Unmask the current thread's Rx/Tx interrupts. 1421 * Called by on_each_cpu(), guaranteed to run with migration disabled, 1422 * using smp_processor_id() is OK. 1423 */ 1424 static void mvpp2_interrupts_unmask(void *arg) 1425 { 1426 struct mvpp2_port *port = arg; 1427 int cpu = smp_processor_id(); 1428 u32 val, thread; 1429 1430 /* If the thread isn't used, don't do anything */ 1431 if (cpu >= port->priv->nthreads) 1432 return; 1433 1434 thread = mvpp2_cpu_to_thread(port->priv, cpu); 1435 1436 val = MVPP2_CAUSE_MISC_SUM_MASK | 1437 MVPP2_CAUSE_RXQ_OCCUP_DESC_ALL_MASK(port->priv->hw_version); 1438 if (port->has_tx_irqs) 1439 val |= MVPP2_CAUSE_TXQ_OCCUP_DESC_ALL_MASK; 1440 1441 mvpp2_thread_write(port->priv, thread, 1442 MVPP2_ISR_RX_TX_MASK_REG(port->id), val); 1443 mvpp2_thread_write(port->priv, thread, 1444 MVPP2_ISR_RX_ERR_CAUSE_REG(port->id), 1445 MVPP2_ISR_RX_ERR_CAUSE_NONOCC_MASK); 1446 } 1447 1448 static void 1449 mvpp2_shared_interrupt_mask_unmask(struct mvpp2_port *port, bool mask) 1450 { 1451 u32 val; 1452 int i; 1453 1454 if (port->priv->hw_version == MVPP21) 1455 return; 1456 1457 if (mask) 1458 val = 0; 1459 else 1460 val = MVPP2_CAUSE_RXQ_OCCUP_DESC_ALL_MASK(MVPP22); 1461 1462 for (i = 0; i < port->nqvecs; i++) { 1463 struct mvpp2_queue_vector *v = port->qvecs + i; 1464 1465 if (v->type != MVPP2_QUEUE_VECTOR_SHARED) 1466 continue; 1467 1468 mvpp2_thread_write(port->priv, v->sw_thread_id, 1469 MVPP2_ISR_RX_TX_MASK_REG(port->id), val); 1470 mvpp2_thread_write(port->priv, v->sw_thread_id, 1471 MVPP2_ISR_RX_ERR_CAUSE_REG(port->id), 1472 MVPP2_ISR_RX_ERR_CAUSE_NONOCC_MASK); 1473 } 1474 } 1475 1476 /* Only GOP port 0 has an XLG MAC */ 1477 static bool mvpp2_port_supports_xlg(struct mvpp2_port *port) 1478 { 1479 return port->gop_id == 0; 1480 } 1481 1482 static bool mvpp2_port_supports_rgmii(struct mvpp2_port *port) 1483 { 1484 return !(port->priv->hw_version >= MVPP22 && port->gop_id == 0); 1485 } 1486 1487 /* Port configuration routines */ 1488 static bool mvpp2_is_xlg(phy_interface_t interface) 1489 { 1490 return interface == PHY_INTERFACE_MODE_10GBASER || 1491 interface == PHY_INTERFACE_MODE_XAUI; 1492 } 1493 1494 static void mvpp2_modify(void __iomem *ptr, u32 mask, u32 set) 1495 { 1496 u32 old, val; 1497 1498 old = val = readl(ptr); 1499 val &= ~mask; 1500 val |= set; 1501 if (old != val) 1502 writel(val, ptr); 1503 } 1504 1505 static void mvpp22_gop_init_rgmii(struct mvpp2_port *port) 1506 { 1507 struct mvpp2 *priv = port->priv; 1508 u32 val; 1509 1510 regmap_read(priv->sysctrl_base, GENCONF_PORT_CTRL0, &val); 1511 val |= GENCONF_PORT_CTRL0_BUS_WIDTH_SELECT; 1512 regmap_write(priv->sysctrl_base, GENCONF_PORT_CTRL0, val); 1513 1514 regmap_read(priv->sysctrl_base, GENCONF_CTRL0, &val); 1515 if (port->gop_id == 2) 1516 val |= GENCONF_CTRL0_PORT2_RGMII; 1517 else if (port->gop_id == 3) 1518 val |= GENCONF_CTRL0_PORT3_RGMII_MII; 1519 regmap_write(priv->sysctrl_base, GENCONF_CTRL0, val); 1520 } 1521 1522 static void mvpp22_gop_init_sgmii(struct mvpp2_port *port) 1523 { 1524 struct mvpp2 *priv = port->priv; 1525 u32 val; 1526 1527 regmap_read(priv->sysctrl_base, GENCONF_PORT_CTRL0, &val); 1528 val |= GENCONF_PORT_CTRL0_BUS_WIDTH_SELECT | 1529 GENCONF_PORT_CTRL0_RX_DATA_SAMPLE; 1530 regmap_write(priv->sysctrl_base, GENCONF_PORT_CTRL0, val); 1531 1532 if (port->gop_id > 1) { 1533 regmap_read(priv->sysctrl_base, GENCONF_CTRL0, &val); 1534 if (port->gop_id == 2) 1535 val &= ~GENCONF_CTRL0_PORT2_RGMII; 1536 else if (port->gop_id == 3) 1537 val &= ~GENCONF_CTRL0_PORT3_RGMII_MII; 1538 regmap_write(priv->sysctrl_base, GENCONF_CTRL0, val); 1539 } 1540 } 1541 1542 static void mvpp22_gop_init_10gkr(struct mvpp2_port *port) 1543 { 1544 struct mvpp2 *priv = port->priv; 1545 void __iomem *mpcs = priv->iface_base + MVPP22_MPCS_BASE(port->gop_id); 1546 void __iomem *xpcs = priv->iface_base + MVPP22_XPCS_BASE(port->gop_id); 1547 u32 val; 1548 1549 val = readl(xpcs + MVPP22_XPCS_CFG0); 1550 val &= ~(MVPP22_XPCS_CFG0_PCS_MODE(0x3) | 1551 MVPP22_XPCS_CFG0_ACTIVE_LANE(0x3)); 1552 val |= MVPP22_XPCS_CFG0_ACTIVE_LANE(2); 1553 writel(val, xpcs + MVPP22_XPCS_CFG0); 1554 1555 val = readl(mpcs + MVPP22_MPCS_CTRL); 1556 val &= ~MVPP22_MPCS_CTRL_FWD_ERR_CONN; 1557 writel(val, mpcs + MVPP22_MPCS_CTRL); 1558 1559 val = readl(mpcs + MVPP22_MPCS_CLK_RESET); 1560 val &= ~MVPP22_MPCS_CLK_RESET_DIV_RATIO(0x7); 1561 val |= MVPP22_MPCS_CLK_RESET_DIV_RATIO(1); 1562 writel(val, mpcs + MVPP22_MPCS_CLK_RESET); 1563 } 1564 1565 static void mvpp22_gop_fca_enable_periodic(struct mvpp2_port *port, bool en) 1566 { 1567 struct mvpp2 *priv = port->priv; 1568 void __iomem *fca = priv->iface_base + MVPP22_FCA_BASE(port->gop_id); 1569 u32 val; 1570 1571 val = readl(fca + MVPP22_FCA_CONTROL_REG); 1572 val &= ~MVPP22_FCA_ENABLE_PERIODIC; 1573 if (en) 1574 val |= MVPP22_FCA_ENABLE_PERIODIC; 1575 writel(val, fca + MVPP22_FCA_CONTROL_REG); 1576 } 1577 1578 static void mvpp22_gop_fca_set_timer(struct mvpp2_port *port, u32 timer) 1579 { 1580 struct mvpp2 *priv = port->priv; 1581 void __iomem *fca = priv->iface_base + MVPP22_FCA_BASE(port->gop_id); 1582 u32 lsb, msb; 1583 1584 lsb = timer & MVPP22_FCA_REG_MASK; 1585 msb = timer >> MVPP22_FCA_REG_SIZE; 1586 1587 writel(lsb, fca + MVPP22_PERIODIC_COUNTER_LSB_REG); 1588 writel(msb, fca + MVPP22_PERIODIC_COUNTER_MSB_REG); 1589 } 1590 1591 /* Set Flow Control timer x100 faster than pause quanta to ensure that link 1592 * partner won't send traffic if port is in XOFF mode. 1593 */ 1594 static void mvpp22_gop_fca_set_periodic_timer(struct mvpp2_port *port) 1595 { 1596 u32 timer; 1597 1598 timer = (port->priv->tclk / (USEC_PER_SEC * FC_CLK_DIVIDER)) 1599 * FC_QUANTA; 1600 1601 mvpp22_gop_fca_enable_periodic(port, false); 1602 1603 mvpp22_gop_fca_set_timer(port, timer); 1604 1605 mvpp22_gop_fca_enable_periodic(port, true); 1606 } 1607 1608 static int mvpp22_gop_init(struct mvpp2_port *port, phy_interface_t interface) 1609 { 1610 struct mvpp2 *priv = port->priv; 1611 u32 val; 1612 1613 if (!priv->sysctrl_base) 1614 return 0; 1615 1616 switch (interface) { 1617 case PHY_INTERFACE_MODE_RGMII: 1618 case PHY_INTERFACE_MODE_RGMII_ID: 1619 case PHY_INTERFACE_MODE_RGMII_RXID: 1620 case PHY_INTERFACE_MODE_RGMII_TXID: 1621 if (!mvpp2_port_supports_rgmii(port)) 1622 goto invalid_conf; 1623 mvpp22_gop_init_rgmii(port); 1624 break; 1625 case PHY_INTERFACE_MODE_SGMII: 1626 case PHY_INTERFACE_MODE_1000BASEX: 1627 case PHY_INTERFACE_MODE_2500BASEX: 1628 mvpp22_gop_init_sgmii(port); 1629 break; 1630 case PHY_INTERFACE_MODE_10GBASER: 1631 if (!mvpp2_port_supports_xlg(port)) 1632 goto invalid_conf; 1633 mvpp22_gop_init_10gkr(port); 1634 break; 1635 default: 1636 goto unsupported_conf; 1637 } 1638 1639 regmap_read(priv->sysctrl_base, GENCONF_PORT_CTRL1, &val); 1640 val |= GENCONF_PORT_CTRL1_RESET(port->gop_id) | 1641 GENCONF_PORT_CTRL1_EN(port->gop_id); 1642 regmap_write(priv->sysctrl_base, GENCONF_PORT_CTRL1, val); 1643 1644 regmap_read(priv->sysctrl_base, GENCONF_PORT_CTRL0, &val); 1645 val |= GENCONF_PORT_CTRL0_CLK_DIV_PHASE_CLR; 1646 regmap_write(priv->sysctrl_base, GENCONF_PORT_CTRL0, val); 1647 1648 regmap_read(priv->sysctrl_base, GENCONF_SOFT_RESET1, &val); 1649 val |= GENCONF_SOFT_RESET1_GOP; 1650 regmap_write(priv->sysctrl_base, GENCONF_SOFT_RESET1, val); 1651 1652 mvpp22_gop_fca_set_periodic_timer(port); 1653 1654 unsupported_conf: 1655 return 0; 1656 1657 invalid_conf: 1658 netdev_err(port->dev, "Invalid port configuration\n"); 1659 return -EINVAL; 1660 } 1661 1662 static void mvpp22_gop_unmask_irq(struct mvpp2_port *port) 1663 { 1664 u32 val; 1665 1666 if (phy_interface_mode_is_rgmii(port->phy_interface) || 1667 phy_interface_mode_is_8023z(port->phy_interface) || 1668 port->phy_interface == PHY_INTERFACE_MODE_SGMII) { 1669 /* Enable the GMAC link status irq for this port */ 1670 val = readl(port->base + MVPP22_GMAC_INT_SUM_MASK); 1671 val |= MVPP22_GMAC_INT_SUM_MASK_LINK_STAT; 1672 writel(val, port->base + MVPP22_GMAC_INT_SUM_MASK); 1673 } 1674 1675 if (mvpp2_port_supports_xlg(port)) { 1676 /* Enable the XLG/GIG irqs for this port */ 1677 val = readl(port->base + MVPP22_XLG_EXT_INT_MASK); 1678 if (mvpp2_is_xlg(port->phy_interface)) 1679 val |= MVPP22_XLG_EXT_INT_MASK_XLG; 1680 else 1681 val |= MVPP22_XLG_EXT_INT_MASK_GIG; 1682 writel(val, port->base + MVPP22_XLG_EXT_INT_MASK); 1683 } 1684 } 1685 1686 static void mvpp22_gop_mask_irq(struct mvpp2_port *port) 1687 { 1688 u32 val; 1689 1690 if (mvpp2_port_supports_xlg(port)) { 1691 val = readl(port->base + MVPP22_XLG_EXT_INT_MASK); 1692 val &= ~(MVPP22_XLG_EXT_INT_MASK_XLG | 1693 MVPP22_XLG_EXT_INT_MASK_GIG); 1694 writel(val, port->base + MVPP22_XLG_EXT_INT_MASK); 1695 } 1696 1697 if (phy_interface_mode_is_rgmii(port->phy_interface) || 1698 phy_interface_mode_is_8023z(port->phy_interface) || 1699 port->phy_interface == PHY_INTERFACE_MODE_SGMII) { 1700 val = readl(port->base + MVPP22_GMAC_INT_SUM_MASK); 1701 val &= ~MVPP22_GMAC_INT_SUM_MASK_LINK_STAT; 1702 writel(val, port->base + MVPP22_GMAC_INT_SUM_MASK); 1703 } 1704 } 1705 1706 static void mvpp22_gop_setup_irq(struct mvpp2_port *port) 1707 { 1708 u32 val; 1709 1710 mvpp2_modify(port->base + MVPP22_GMAC_INT_SUM_MASK, 1711 MVPP22_GMAC_INT_SUM_MASK_PTP, 1712 MVPP22_GMAC_INT_SUM_MASK_PTP); 1713 1714 if (port->phylink || 1715 phy_interface_mode_is_rgmii(port->phy_interface) || 1716 phy_interface_mode_is_8023z(port->phy_interface) || 1717 port->phy_interface == PHY_INTERFACE_MODE_SGMII) { 1718 val = readl(port->base + MVPP22_GMAC_INT_MASK); 1719 val |= MVPP22_GMAC_INT_MASK_LINK_STAT; 1720 writel(val, port->base + MVPP22_GMAC_INT_MASK); 1721 } 1722 1723 if (mvpp2_port_supports_xlg(port)) { 1724 val = readl(port->base + MVPP22_XLG_INT_MASK); 1725 val |= MVPP22_XLG_INT_MASK_LINK; 1726 writel(val, port->base + MVPP22_XLG_INT_MASK); 1727 1728 mvpp2_modify(port->base + MVPP22_XLG_EXT_INT_MASK, 1729 MVPP22_XLG_EXT_INT_MASK_PTP, 1730 MVPP22_XLG_EXT_INT_MASK_PTP); 1731 } 1732 1733 mvpp22_gop_unmask_irq(port); 1734 } 1735 1736 /* Sets the PHY mode of the COMPHY (which configures the serdes lanes). 1737 * 1738 * The PHY mode used by the PPv2 driver comes from the network subsystem, while 1739 * the one given to the COMPHY comes from the generic PHY subsystem. Hence they 1740 * differ. 1741 * 1742 * The COMPHY configures the serdes lanes regardless of the actual use of the 1743 * lanes by the physical layer. This is why configurations like 1744 * "PPv2 (2500BaseX) - COMPHY (2500SGMII)" are valid. 1745 */ 1746 static int mvpp22_comphy_init(struct mvpp2_port *port, 1747 phy_interface_t interface) 1748 { 1749 int ret; 1750 1751 if (!port->comphy) 1752 return 0; 1753 1754 ret = phy_set_mode_ext(port->comphy, PHY_MODE_ETHERNET, interface); 1755 if (ret) 1756 return ret; 1757 1758 return phy_power_on(port->comphy); 1759 } 1760 1761 static void mvpp2_port_enable(struct mvpp2_port *port) 1762 { 1763 u32 val; 1764 1765 if (mvpp2_port_supports_xlg(port) && 1766 mvpp2_is_xlg(port->phy_interface)) { 1767 val = readl(port->base + MVPP22_XLG_CTRL0_REG); 1768 val |= MVPP22_XLG_CTRL0_PORT_EN; 1769 val &= ~MVPP22_XLG_CTRL0_MIB_CNT_DIS; 1770 writel(val, port->base + MVPP22_XLG_CTRL0_REG); 1771 } else { 1772 val = readl(port->base + MVPP2_GMAC_CTRL_0_REG); 1773 val |= MVPP2_GMAC_PORT_EN_MASK; 1774 val |= MVPP2_GMAC_MIB_CNTR_EN_MASK; 1775 writel(val, port->base + MVPP2_GMAC_CTRL_0_REG); 1776 } 1777 } 1778 1779 static void mvpp2_port_disable(struct mvpp2_port *port) 1780 { 1781 u32 val; 1782 1783 if (mvpp2_port_supports_xlg(port) && 1784 mvpp2_is_xlg(port->phy_interface)) { 1785 val = readl(port->base + MVPP22_XLG_CTRL0_REG); 1786 val &= ~MVPP22_XLG_CTRL0_PORT_EN; 1787 writel(val, port->base + MVPP22_XLG_CTRL0_REG); 1788 } 1789 1790 val = readl(port->base + MVPP2_GMAC_CTRL_0_REG); 1791 val &= ~(MVPP2_GMAC_PORT_EN_MASK); 1792 writel(val, port->base + MVPP2_GMAC_CTRL_0_REG); 1793 } 1794 1795 /* Set IEEE 802.3x Flow Control Xon Packet Transmission Mode */ 1796 static void mvpp2_port_periodic_xon_disable(struct mvpp2_port *port) 1797 { 1798 u32 val; 1799 1800 val = readl(port->base + MVPP2_GMAC_CTRL_1_REG) & 1801 ~MVPP2_GMAC_PERIODIC_XON_EN_MASK; 1802 writel(val, port->base + MVPP2_GMAC_CTRL_1_REG); 1803 } 1804 1805 /* Configure loopback port */ 1806 static void mvpp2_port_loopback_set(struct mvpp2_port *port, 1807 const struct phylink_link_state *state) 1808 { 1809 u32 val; 1810 1811 val = readl(port->base + MVPP2_GMAC_CTRL_1_REG); 1812 1813 if (state->speed == 1000) 1814 val |= MVPP2_GMAC_GMII_LB_EN_MASK; 1815 else 1816 val &= ~MVPP2_GMAC_GMII_LB_EN_MASK; 1817 1818 if (phy_interface_mode_is_8023z(state->interface) || 1819 state->interface == PHY_INTERFACE_MODE_SGMII) 1820 val |= MVPP2_GMAC_PCS_LB_EN_MASK; 1821 else 1822 val &= ~MVPP2_GMAC_PCS_LB_EN_MASK; 1823 1824 writel(val, port->base + MVPP2_GMAC_CTRL_1_REG); 1825 } 1826 1827 enum { 1828 ETHTOOL_XDP_REDIRECT, 1829 ETHTOOL_XDP_PASS, 1830 ETHTOOL_XDP_DROP, 1831 ETHTOOL_XDP_TX, 1832 ETHTOOL_XDP_TX_ERR, 1833 ETHTOOL_XDP_XMIT, 1834 ETHTOOL_XDP_XMIT_ERR, 1835 }; 1836 1837 struct mvpp2_ethtool_counter { 1838 unsigned int offset; 1839 const char string[ETH_GSTRING_LEN]; 1840 bool reg_is_64b; 1841 }; 1842 1843 static u64 mvpp2_read_count(struct mvpp2_port *port, 1844 const struct mvpp2_ethtool_counter *counter) 1845 { 1846 u64 val; 1847 1848 val = readl(port->stats_base + counter->offset); 1849 if (counter->reg_is_64b) 1850 val += (u64)readl(port->stats_base + counter->offset + 4) << 32; 1851 1852 return val; 1853 } 1854 1855 /* Some counters are accessed indirectly by first writing an index to 1856 * MVPP2_CTRS_IDX. The index can represent various resources depending on the 1857 * register we access, it can be a hit counter for some classification tables, 1858 * a counter specific to a rxq, a txq or a buffer pool. 1859 */ 1860 static u32 mvpp2_read_index(struct mvpp2 *priv, u32 index, u32 reg) 1861 { 1862 mvpp2_write(priv, MVPP2_CTRS_IDX, index); 1863 return mvpp2_read(priv, reg); 1864 } 1865 1866 /* Due to the fact that software statistics and hardware statistics are, by 1867 * design, incremented at different moments in the chain of packet processing, 1868 * it is very likely that incoming packets could have been dropped after being 1869 * counted by hardware but before reaching software statistics (most probably 1870 * multicast packets), and in the oppposite way, during transmission, FCS bytes 1871 * are added in between as well as TSO skb will be split and header bytes added. 1872 * Hence, statistics gathered from userspace with ifconfig (software) and 1873 * ethtool (hardware) cannot be compared. 1874 */ 1875 static const struct mvpp2_ethtool_counter mvpp2_ethtool_mib_regs[] = { 1876 { MVPP2_MIB_GOOD_OCTETS_RCVD, "good_octets_received", true }, 1877 { MVPP2_MIB_BAD_OCTETS_RCVD, "bad_octets_received" }, 1878 { MVPP2_MIB_CRC_ERRORS_SENT, "crc_errors_sent" }, 1879 { MVPP2_MIB_UNICAST_FRAMES_RCVD, "unicast_frames_received" }, 1880 { MVPP2_MIB_BROADCAST_FRAMES_RCVD, "broadcast_frames_received" }, 1881 { MVPP2_MIB_MULTICAST_FRAMES_RCVD, "multicast_frames_received" }, 1882 { MVPP2_MIB_FRAMES_64_OCTETS, "frames_64_octets" }, 1883 { MVPP2_MIB_FRAMES_65_TO_127_OCTETS, "frames_65_to_127_octet" }, 1884 { MVPP2_MIB_FRAMES_128_TO_255_OCTETS, "frames_128_to_255_octet" }, 1885 { MVPP2_MIB_FRAMES_256_TO_511_OCTETS, "frames_256_to_511_octet" }, 1886 { MVPP2_MIB_FRAMES_512_TO_1023_OCTETS, "frames_512_to_1023_octet" }, 1887 { MVPP2_MIB_FRAMES_1024_TO_MAX_OCTETS, "frames_1024_to_max_octet" }, 1888 { MVPP2_MIB_GOOD_OCTETS_SENT, "good_octets_sent", true }, 1889 { MVPP2_MIB_UNICAST_FRAMES_SENT, "unicast_frames_sent" }, 1890 { MVPP2_MIB_MULTICAST_FRAMES_SENT, "multicast_frames_sent" }, 1891 { MVPP2_MIB_BROADCAST_FRAMES_SENT, "broadcast_frames_sent" }, 1892 { MVPP2_MIB_FC_SENT, "fc_sent" }, 1893 { MVPP2_MIB_FC_RCVD, "fc_received" }, 1894 { MVPP2_MIB_RX_FIFO_OVERRUN, "rx_fifo_overrun" }, 1895 { MVPP2_MIB_UNDERSIZE_RCVD, "undersize_received" }, 1896 { MVPP2_MIB_FRAGMENTS_RCVD, "fragments_received" }, 1897 { MVPP2_MIB_OVERSIZE_RCVD, "oversize_received" }, 1898 { MVPP2_MIB_JABBER_RCVD, "jabber_received" }, 1899 { MVPP2_MIB_MAC_RCV_ERROR, "mac_receive_error" }, 1900 { MVPP2_MIB_BAD_CRC_EVENT, "bad_crc_event" }, 1901 { MVPP2_MIB_COLLISION, "collision" }, 1902 { MVPP2_MIB_LATE_COLLISION, "late_collision" }, 1903 }; 1904 1905 static const struct mvpp2_ethtool_counter mvpp2_ethtool_port_regs[] = { 1906 { MVPP2_OVERRUN_ETH_DROP, "rx_fifo_or_parser_overrun_drops" }, 1907 { MVPP2_CLS_ETH_DROP, "rx_classifier_drops" }, 1908 }; 1909 1910 static const struct mvpp2_ethtool_counter mvpp2_ethtool_txq_regs[] = { 1911 { MVPP2_TX_DESC_ENQ_CTR, "txq_%d_desc_enqueue" }, 1912 { MVPP2_TX_DESC_ENQ_TO_DDR_CTR, "txq_%d_desc_enqueue_to_ddr" }, 1913 { MVPP2_TX_BUFF_ENQ_TO_DDR_CTR, "txq_%d_buff_euqueue_to_ddr" }, 1914 { MVPP2_TX_DESC_ENQ_HW_FWD_CTR, "txq_%d_desc_hardware_forwarded" }, 1915 { MVPP2_TX_PKTS_DEQ_CTR, "txq_%d_packets_dequeued" }, 1916 { MVPP2_TX_PKTS_FULL_QUEUE_DROP_CTR, "txq_%d_queue_full_drops" }, 1917 { MVPP2_TX_PKTS_EARLY_DROP_CTR, "txq_%d_packets_early_drops" }, 1918 { MVPP2_TX_PKTS_BM_DROP_CTR, "txq_%d_packets_bm_drops" }, 1919 { MVPP2_TX_PKTS_BM_MC_DROP_CTR, "txq_%d_packets_rep_bm_drops" }, 1920 }; 1921 1922 static const struct mvpp2_ethtool_counter mvpp2_ethtool_rxq_regs[] = { 1923 { MVPP2_RX_DESC_ENQ_CTR, "rxq_%d_desc_enqueue" }, 1924 { MVPP2_RX_PKTS_FULL_QUEUE_DROP_CTR, "rxq_%d_queue_full_drops" }, 1925 { MVPP2_RX_PKTS_EARLY_DROP_CTR, "rxq_%d_packets_early_drops" }, 1926 { MVPP2_RX_PKTS_BM_DROP_CTR, "rxq_%d_packets_bm_drops" }, 1927 }; 1928 1929 static const struct mvpp2_ethtool_counter mvpp2_ethtool_xdp[] = { 1930 { ETHTOOL_XDP_REDIRECT, "rx_xdp_redirect", }, 1931 { ETHTOOL_XDP_PASS, "rx_xdp_pass", }, 1932 { ETHTOOL_XDP_DROP, "rx_xdp_drop", }, 1933 { ETHTOOL_XDP_TX, "rx_xdp_tx", }, 1934 { ETHTOOL_XDP_TX_ERR, "rx_xdp_tx_errors", }, 1935 { ETHTOOL_XDP_XMIT, "tx_xdp_xmit", }, 1936 { ETHTOOL_XDP_XMIT_ERR, "tx_xdp_xmit_errors", }, 1937 }; 1938 1939 #define MVPP2_N_ETHTOOL_STATS(ntxqs, nrxqs) (ARRAY_SIZE(mvpp2_ethtool_mib_regs) + \ 1940 ARRAY_SIZE(mvpp2_ethtool_port_regs) + \ 1941 (ARRAY_SIZE(mvpp2_ethtool_txq_regs) * (ntxqs)) + \ 1942 (ARRAY_SIZE(mvpp2_ethtool_rxq_regs) * (nrxqs)) + \ 1943 ARRAY_SIZE(mvpp2_ethtool_xdp)) 1944 1945 static void mvpp2_ethtool_get_strings(struct net_device *netdev, u32 sset, 1946 u8 *data) 1947 { 1948 struct mvpp2_port *port = netdev_priv(netdev); 1949 int i, q; 1950 1951 if (sset != ETH_SS_STATS) 1952 return; 1953 1954 for (i = 0; i < ARRAY_SIZE(mvpp2_ethtool_mib_regs); i++) { 1955 strscpy(data, mvpp2_ethtool_mib_regs[i].string, 1956 ETH_GSTRING_LEN); 1957 data += ETH_GSTRING_LEN; 1958 } 1959 1960 for (i = 0; i < ARRAY_SIZE(mvpp2_ethtool_port_regs); i++) { 1961 strscpy(data, mvpp2_ethtool_port_regs[i].string, 1962 ETH_GSTRING_LEN); 1963 data += ETH_GSTRING_LEN; 1964 } 1965 1966 for (q = 0; q < port->ntxqs; q++) { 1967 for (i = 0; i < ARRAY_SIZE(mvpp2_ethtool_txq_regs); i++) { 1968 snprintf(data, ETH_GSTRING_LEN, 1969 mvpp2_ethtool_txq_regs[i].string, q); 1970 data += ETH_GSTRING_LEN; 1971 } 1972 } 1973 1974 for (q = 0; q < port->nrxqs; q++) { 1975 for (i = 0; i < ARRAY_SIZE(mvpp2_ethtool_rxq_regs); i++) { 1976 snprintf(data, ETH_GSTRING_LEN, 1977 mvpp2_ethtool_rxq_regs[i].string, 1978 q); 1979 data += ETH_GSTRING_LEN; 1980 } 1981 } 1982 1983 for (i = 0; i < ARRAY_SIZE(mvpp2_ethtool_xdp); i++) { 1984 strscpy(data, mvpp2_ethtool_xdp[i].string, 1985 ETH_GSTRING_LEN); 1986 data += ETH_GSTRING_LEN; 1987 } 1988 } 1989 1990 static void 1991 mvpp2_get_xdp_stats(struct mvpp2_port *port, struct mvpp2_pcpu_stats *xdp_stats) 1992 { 1993 unsigned int start; 1994 unsigned int cpu; 1995 1996 /* Gather XDP Statistics */ 1997 for_each_possible_cpu(cpu) { 1998 struct mvpp2_pcpu_stats *cpu_stats; 1999 u64 xdp_redirect; 2000 u64 xdp_pass; 2001 u64 xdp_drop; 2002 u64 xdp_xmit; 2003 u64 xdp_xmit_err; 2004 u64 xdp_tx; 2005 u64 xdp_tx_err; 2006 2007 cpu_stats = per_cpu_ptr(port->stats, cpu); 2008 do { 2009 start = u64_stats_fetch_begin_irq(&cpu_stats->syncp); 2010 xdp_redirect = cpu_stats->xdp_redirect; 2011 xdp_pass = cpu_stats->xdp_pass; 2012 xdp_drop = cpu_stats->xdp_drop; 2013 xdp_xmit = cpu_stats->xdp_xmit; 2014 xdp_xmit_err = cpu_stats->xdp_xmit_err; 2015 xdp_tx = cpu_stats->xdp_tx; 2016 xdp_tx_err = cpu_stats->xdp_tx_err; 2017 } while (u64_stats_fetch_retry_irq(&cpu_stats->syncp, start)); 2018 2019 xdp_stats->xdp_redirect += xdp_redirect; 2020 xdp_stats->xdp_pass += xdp_pass; 2021 xdp_stats->xdp_drop += xdp_drop; 2022 xdp_stats->xdp_xmit += xdp_xmit; 2023 xdp_stats->xdp_xmit_err += xdp_xmit_err; 2024 xdp_stats->xdp_tx += xdp_tx; 2025 xdp_stats->xdp_tx_err += xdp_tx_err; 2026 } 2027 } 2028 2029 static void mvpp2_read_stats(struct mvpp2_port *port) 2030 { 2031 struct mvpp2_pcpu_stats xdp_stats = {}; 2032 const struct mvpp2_ethtool_counter *s; 2033 u64 *pstats; 2034 int i, q; 2035 2036 pstats = port->ethtool_stats; 2037 2038 for (i = 0; i < ARRAY_SIZE(mvpp2_ethtool_mib_regs); i++) 2039 *pstats++ += mvpp2_read_count(port, &mvpp2_ethtool_mib_regs[i]); 2040 2041 for (i = 0; i < ARRAY_SIZE(mvpp2_ethtool_port_regs); i++) 2042 *pstats++ += mvpp2_read(port->priv, 2043 mvpp2_ethtool_port_regs[i].offset + 2044 4 * port->id); 2045 2046 for (q = 0; q < port->ntxqs; q++) 2047 for (i = 0; i < ARRAY_SIZE(mvpp2_ethtool_txq_regs); i++) 2048 *pstats++ += mvpp2_read_index(port->priv, 2049 MVPP22_CTRS_TX_CTR(port->id, q), 2050 mvpp2_ethtool_txq_regs[i].offset); 2051 2052 /* Rxqs are numbered from 0 from the user standpoint, but not from the 2053 * driver's. We need to add the port->first_rxq offset. 2054 */ 2055 for (q = 0; q < port->nrxqs; q++) 2056 for (i = 0; i < ARRAY_SIZE(mvpp2_ethtool_rxq_regs); i++) 2057 *pstats++ += mvpp2_read_index(port->priv, 2058 port->first_rxq + q, 2059 mvpp2_ethtool_rxq_regs[i].offset); 2060 2061 /* Gather XDP Statistics */ 2062 mvpp2_get_xdp_stats(port, &xdp_stats); 2063 2064 for (i = 0, s = mvpp2_ethtool_xdp; 2065 s < mvpp2_ethtool_xdp + ARRAY_SIZE(mvpp2_ethtool_xdp); 2066 s++, i++) { 2067 switch (s->offset) { 2068 case ETHTOOL_XDP_REDIRECT: 2069 *pstats++ = xdp_stats.xdp_redirect; 2070 break; 2071 case ETHTOOL_XDP_PASS: 2072 *pstats++ = xdp_stats.xdp_pass; 2073 break; 2074 case ETHTOOL_XDP_DROP: 2075 *pstats++ = xdp_stats.xdp_drop; 2076 break; 2077 case ETHTOOL_XDP_TX: 2078 *pstats++ = xdp_stats.xdp_tx; 2079 break; 2080 case ETHTOOL_XDP_TX_ERR: 2081 *pstats++ = xdp_stats.xdp_tx_err; 2082 break; 2083 case ETHTOOL_XDP_XMIT: 2084 *pstats++ = xdp_stats.xdp_xmit; 2085 break; 2086 case ETHTOOL_XDP_XMIT_ERR: 2087 *pstats++ = xdp_stats.xdp_xmit_err; 2088 break; 2089 } 2090 } 2091 } 2092 2093 static void mvpp2_gather_hw_statistics(struct work_struct *work) 2094 { 2095 struct delayed_work *del_work = to_delayed_work(work); 2096 struct mvpp2_port *port = container_of(del_work, struct mvpp2_port, 2097 stats_work); 2098 2099 mutex_lock(&port->gather_stats_lock); 2100 2101 mvpp2_read_stats(port); 2102 2103 /* No need to read again the counters right after this function if it 2104 * was called asynchronously by the user (ie. use of ethtool). 2105 */ 2106 cancel_delayed_work(&port->stats_work); 2107 queue_delayed_work(port->priv->stats_queue, &port->stats_work, 2108 MVPP2_MIB_COUNTERS_STATS_DELAY); 2109 2110 mutex_unlock(&port->gather_stats_lock); 2111 } 2112 2113 static void mvpp2_ethtool_get_stats(struct net_device *dev, 2114 struct ethtool_stats *stats, u64 *data) 2115 { 2116 struct mvpp2_port *port = netdev_priv(dev); 2117 2118 /* Update statistics for the given port, then take the lock to avoid 2119 * concurrent accesses on the ethtool_stats structure during its copy. 2120 */ 2121 mvpp2_gather_hw_statistics(&port->stats_work.work); 2122 2123 mutex_lock(&port->gather_stats_lock); 2124 memcpy(data, port->ethtool_stats, 2125 sizeof(u64) * MVPP2_N_ETHTOOL_STATS(port->ntxqs, port->nrxqs)); 2126 mutex_unlock(&port->gather_stats_lock); 2127 } 2128 2129 static int mvpp2_ethtool_get_sset_count(struct net_device *dev, int sset) 2130 { 2131 struct mvpp2_port *port = netdev_priv(dev); 2132 2133 if (sset == ETH_SS_STATS) 2134 return MVPP2_N_ETHTOOL_STATS(port->ntxqs, port->nrxqs); 2135 2136 return -EOPNOTSUPP; 2137 } 2138 2139 static void mvpp2_mac_reset_assert(struct mvpp2_port *port) 2140 { 2141 u32 val; 2142 2143 val = readl(port->base + MVPP2_GMAC_CTRL_2_REG) | 2144 MVPP2_GMAC_PORT_RESET_MASK; 2145 writel(val, port->base + MVPP2_GMAC_CTRL_2_REG); 2146 2147 if (port->priv->hw_version >= MVPP22 && port->gop_id == 0) { 2148 val = readl(port->base + MVPP22_XLG_CTRL0_REG) & 2149 ~MVPP22_XLG_CTRL0_MAC_RESET_DIS; 2150 writel(val, port->base + MVPP22_XLG_CTRL0_REG); 2151 } 2152 } 2153 2154 static void mvpp22_pcs_reset_assert(struct mvpp2_port *port) 2155 { 2156 struct mvpp2 *priv = port->priv; 2157 void __iomem *mpcs, *xpcs; 2158 u32 val; 2159 2160 if (port->priv->hw_version == MVPP21 || port->gop_id != 0) 2161 return; 2162 2163 mpcs = priv->iface_base + MVPP22_MPCS_BASE(port->gop_id); 2164 xpcs = priv->iface_base + MVPP22_XPCS_BASE(port->gop_id); 2165 2166 val = readl(mpcs + MVPP22_MPCS_CLK_RESET); 2167 val &= ~(MAC_CLK_RESET_MAC | MAC_CLK_RESET_SD_RX | MAC_CLK_RESET_SD_TX); 2168 val |= MVPP22_MPCS_CLK_RESET_DIV_SET; 2169 writel(val, mpcs + MVPP22_MPCS_CLK_RESET); 2170 2171 val = readl(xpcs + MVPP22_XPCS_CFG0); 2172 writel(val & ~MVPP22_XPCS_CFG0_RESET_DIS, xpcs + MVPP22_XPCS_CFG0); 2173 } 2174 2175 static void mvpp22_pcs_reset_deassert(struct mvpp2_port *port, 2176 phy_interface_t interface) 2177 { 2178 struct mvpp2 *priv = port->priv; 2179 void __iomem *mpcs, *xpcs; 2180 u32 val; 2181 2182 if (port->priv->hw_version == MVPP21 || port->gop_id != 0) 2183 return; 2184 2185 mpcs = priv->iface_base + MVPP22_MPCS_BASE(port->gop_id); 2186 xpcs = priv->iface_base + MVPP22_XPCS_BASE(port->gop_id); 2187 2188 switch (interface) { 2189 case PHY_INTERFACE_MODE_10GBASER: 2190 val = readl(mpcs + MVPP22_MPCS_CLK_RESET); 2191 val |= MAC_CLK_RESET_MAC | MAC_CLK_RESET_SD_RX | 2192 MAC_CLK_RESET_SD_TX; 2193 val &= ~MVPP22_MPCS_CLK_RESET_DIV_SET; 2194 writel(val, mpcs + MVPP22_MPCS_CLK_RESET); 2195 break; 2196 case PHY_INTERFACE_MODE_XAUI: 2197 case PHY_INTERFACE_MODE_RXAUI: 2198 val = readl(xpcs + MVPP22_XPCS_CFG0); 2199 writel(val | MVPP22_XPCS_CFG0_RESET_DIS, xpcs + MVPP22_XPCS_CFG0); 2200 break; 2201 default: 2202 break; 2203 } 2204 } 2205 2206 /* Change maximum receive size of the port */ 2207 static inline void mvpp2_gmac_max_rx_size_set(struct mvpp2_port *port) 2208 { 2209 u32 val; 2210 2211 val = readl(port->base + MVPP2_GMAC_CTRL_0_REG); 2212 val &= ~MVPP2_GMAC_MAX_RX_SIZE_MASK; 2213 val |= (((port->pkt_size - MVPP2_MH_SIZE) / 2) << 2214 MVPP2_GMAC_MAX_RX_SIZE_OFFS); 2215 writel(val, port->base + MVPP2_GMAC_CTRL_0_REG); 2216 } 2217 2218 /* Change maximum receive size of the port */ 2219 static inline void mvpp2_xlg_max_rx_size_set(struct mvpp2_port *port) 2220 { 2221 u32 val; 2222 2223 val = readl(port->base + MVPP22_XLG_CTRL1_REG); 2224 val &= ~MVPP22_XLG_CTRL1_FRAMESIZELIMIT_MASK; 2225 val |= ((port->pkt_size - MVPP2_MH_SIZE) / 2) << 2226 MVPP22_XLG_CTRL1_FRAMESIZELIMIT_OFFS; 2227 writel(val, port->base + MVPP22_XLG_CTRL1_REG); 2228 } 2229 2230 /* Set defaults to the MVPP2 port */ 2231 static void mvpp2_defaults_set(struct mvpp2_port *port) 2232 { 2233 int tx_port_num, val, queue, lrxq; 2234 2235 if (port->priv->hw_version == MVPP21) { 2236 /* Update TX FIFO MIN Threshold */ 2237 val = readl(port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG); 2238 val &= ~MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK; 2239 /* Min. TX threshold must be less than minimal packet length */ 2240 val |= MVPP2_GMAC_TX_FIFO_MIN_TH_MASK(64 - 4 - 2); 2241 writel(val, port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG); 2242 } 2243 2244 /* Disable Legacy WRR, Disable EJP, Release from reset */ 2245 tx_port_num = mvpp2_egress_port(port); 2246 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, 2247 tx_port_num); 2248 mvpp2_write(port->priv, MVPP2_TXP_SCHED_CMD_1_REG, 0); 2249 2250 /* Set TXQ scheduling to Round-Robin */ 2251 mvpp2_write(port->priv, MVPP2_TXP_SCHED_FIXED_PRIO_REG, 0); 2252 2253 /* Close bandwidth for all queues */ 2254 for (queue = 0; queue < MVPP2_MAX_TXQ; queue++) 2255 mvpp2_write(port->priv, 2256 MVPP2_TXQ_SCHED_TOKEN_CNTR_REG(queue), 0); 2257 2258 /* Set refill period to 1 usec, refill tokens 2259 * and bucket size to maximum 2260 */ 2261 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PERIOD_REG, 2262 port->priv->tclk / USEC_PER_SEC); 2263 val = mvpp2_read(port->priv, MVPP2_TXP_SCHED_REFILL_REG); 2264 val &= ~MVPP2_TXP_REFILL_PERIOD_ALL_MASK; 2265 val |= MVPP2_TXP_REFILL_PERIOD_MASK(1); 2266 val |= MVPP2_TXP_REFILL_TOKENS_ALL_MASK; 2267 mvpp2_write(port->priv, MVPP2_TXP_SCHED_REFILL_REG, val); 2268 val = MVPP2_TXP_TOKEN_SIZE_MAX; 2269 mvpp2_write(port->priv, MVPP2_TXP_SCHED_TOKEN_SIZE_REG, val); 2270 2271 /* Set MaximumLowLatencyPacketSize value to 256 */ 2272 mvpp2_write(port->priv, MVPP2_RX_CTRL_REG(port->id), 2273 MVPP2_RX_USE_PSEUDO_FOR_CSUM_MASK | 2274 MVPP2_RX_LOW_LATENCY_PKT_SIZE(256)); 2275 2276 /* Enable Rx cache snoop */ 2277 for (lrxq = 0; lrxq < port->nrxqs; lrxq++) { 2278 queue = port->rxqs[lrxq]->id; 2279 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(queue)); 2280 val |= MVPP2_SNOOP_PKT_SIZE_MASK | 2281 MVPP2_SNOOP_BUF_HDR_MASK; 2282 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(queue), val); 2283 } 2284 2285 /* At default, mask all interrupts to all present cpus */ 2286 mvpp2_interrupts_disable(port); 2287 } 2288 2289 /* Enable/disable receiving packets */ 2290 static void mvpp2_ingress_enable(struct mvpp2_port *port) 2291 { 2292 u32 val; 2293 int lrxq, queue; 2294 2295 for (lrxq = 0; lrxq < port->nrxqs; lrxq++) { 2296 queue = port->rxqs[lrxq]->id; 2297 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(queue)); 2298 val &= ~MVPP2_RXQ_DISABLE_MASK; 2299 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(queue), val); 2300 } 2301 } 2302 2303 static void mvpp2_ingress_disable(struct mvpp2_port *port) 2304 { 2305 u32 val; 2306 int lrxq, queue; 2307 2308 for (lrxq = 0; lrxq < port->nrxqs; lrxq++) { 2309 queue = port->rxqs[lrxq]->id; 2310 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(queue)); 2311 val |= MVPP2_RXQ_DISABLE_MASK; 2312 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(queue), val); 2313 } 2314 } 2315 2316 /* Enable transmit via physical egress queue 2317 * - HW starts take descriptors from DRAM 2318 */ 2319 static void mvpp2_egress_enable(struct mvpp2_port *port) 2320 { 2321 u32 qmap; 2322 int queue; 2323 int tx_port_num = mvpp2_egress_port(port); 2324 2325 /* Enable all initialized TXs. */ 2326 qmap = 0; 2327 for (queue = 0; queue < port->ntxqs; queue++) { 2328 struct mvpp2_tx_queue *txq = port->txqs[queue]; 2329 2330 if (txq->descs) 2331 qmap |= (1 << queue); 2332 } 2333 2334 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num); 2335 mvpp2_write(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG, qmap); 2336 } 2337 2338 /* Disable transmit via physical egress queue 2339 * - HW doesn't take descriptors from DRAM 2340 */ 2341 static void mvpp2_egress_disable(struct mvpp2_port *port) 2342 { 2343 u32 reg_data; 2344 int delay; 2345 int tx_port_num = mvpp2_egress_port(port); 2346 2347 /* Issue stop command for active channels only */ 2348 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num); 2349 reg_data = (mvpp2_read(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG)) & 2350 MVPP2_TXP_SCHED_ENQ_MASK; 2351 if (reg_data != 0) 2352 mvpp2_write(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG, 2353 (reg_data << MVPP2_TXP_SCHED_DISQ_OFFSET)); 2354 2355 /* Wait for all Tx activity to terminate. */ 2356 delay = 0; 2357 do { 2358 if (delay >= MVPP2_TX_DISABLE_TIMEOUT_MSEC) { 2359 netdev_warn(port->dev, 2360 "Tx stop timed out, status=0x%08x\n", 2361 reg_data); 2362 break; 2363 } 2364 mdelay(1); 2365 delay++; 2366 2367 /* Check port TX Command register that all 2368 * Tx queues are stopped 2369 */ 2370 reg_data = mvpp2_read(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG); 2371 } while (reg_data & MVPP2_TXP_SCHED_ENQ_MASK); 2372 } 2373 2374 /* Rx descriptors helper methods */ 2375 2376 /* Get number of Rx descriptors occupied by received packets */ 2377 static inline int 2378 mvpp2_rxq_received(struct mvpp2_port *port, int rxq_id) 2379 { 2380 u32 val = mvpp2_read(port->priv, MVPP2_RXQ_STATUS_REG(rxq_id)); 2381 2382 return val & MVPP2_RXQ_OCCUPIED_MASK; 2383 } 2384 2385 /* Update Rx queue status with the number of occupied and available 2386 * Rx descriptor slots. 2387 */ 2388 static inline void 2389 mvpp2_rxq_status_update(struct mvpp2_port *port, int rxq_id, 2390 int used_count, int free_count) 2391 { 2392 /* Decrement the number of used descriptors and increment count 2393 * increment the number of free descriptors. 2394 */ 2395 u32 val = used_count | (free_count << MVPP2_RXQ_NUM_NEW_OFFSET); 2396 2397 mvpp2_write(port->priv, MVPP2_RXQ_STATUS_UPDATE_REG(rxq_id), val); 2398 } 2399 2400 /* Get pointer to next RX descriptor to be processed by SW */ 2401 static inline struct mvpp2_rx_desc * 2402 mvpp2_rxq_next_desc_get(struct mvpp2_rx_queue *rxq) 2403 { 2404 int rx_desc = rxq->next_desc_to_proc; 2405 2406 rxq->next_desc_to_proc = MVPP2_QUEUE_NEXT_DESC(rxq, rx_desc); 2407 prefetch(rxq->descs + rxq->next_desc_to_proc); 2408 return rxq->descs + rx_desc; 2409 } 2410 2411 /* Set rx queue offset */ 2412 static void mvpp2_rxq_offset_set(struct mvpp2_port *port, 2413 int prxq, int offset) 2414 { 2415 u32 val; 2416 2417 /* Convert offset from bytes to units of 32 bytes */ 2418 offset = offset >> 5; 2419 2420 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(prxq)); 2421 val &= ~MVPP2_RXQ_PACKET_OFFSET_MASK; 2422 2423 /* Offset is in */ 2424 val |= ((offset << MVPP2_RXQ_PACKET_OFFSET_OFFS) & 2425 MVPP2_RXQ_PACKET_OFFSET_MASK); 2426 2427 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(prxq), val); 2428 } 2429 2430 /* Tx descriptors helper methods */ 2431 2432 /* Get pointer to next Tx descriptor to be processed (send) by HW */ 2433 static struct mvpp2_tx_desc * 2434 mvpp2_txq_next_desc_get(struct mvpp2_tx_queue *txq) 2435 { 2436 int tx_desc = txq->next_desc_to_proc; 2437 2438 txq->next_desc_to_proc = MVPP2_QUEUE_NEXT_DESC(txq, tx_desc); 2439 return txq->descs + tx_desc; 2440 } 2441 2442 /* Update HW with number of aggregated Tx descriptors to be sent 2443 * 2444 * Called only from mvpp2_tx(), so migration is disabled, using 2445 * smp_processor_id() is OK. 2446 */ 2447 static void mvpp2_aggr_txq_pend_desc_add(struct mvpp2_port *port, int pending) 2448 { 2449 /* aggregated access - relevant TXQ number is written in TX desc */ 2450 mvpp2_thread_write(port->priv, 2451 mvpp2_cpu_to_thread(port->priv, smp_processor_id()), 2452 MVPP2_AGGR_TXQ_UPDATE_REG, pending); 2453 } 2454 2455 /* Check if there are enough free descriptors in aggregated txq. 2456 * If not, update the number of occupied descriptors and repeat the check. 2457 * 2458 * Called only from mvpp2_tx(), so migration is disabled, using 2459 * smp_processor_id() is OK. 2460 */ 2461 static int mvpp2_aggr_desc_num_check(struct mvpp2_port *port, 2462 struct mvpp2_tx_queue *aggr_txq, int num) 2463 { 2464 if ((aggr_txq->count + num) > MVPP2_AGGR_TXQ_SIZE) { 2465 /* Update number of occupied aggregated Tx descriptors */ 2466 unsigned int thread = 2467 mvpp2_cpu_to_thread(port->priv, smp_processor_id()); 2468 u32 val = mvpp2_read_relaxed(port->priv, 2469 MVPP2_AGGR_TXQ_STATUS_REG(thread)); 2470 2471 aggr_txq->count = val & MVPP2_AGGR_TXQ_PENDING_MASK; 2472 2473 if ((aggr_txq->count + num) > MVPP2_AGGR_TXQ_SIZE) 2474 return -ENOMEM; 2475 } 2476 return 0; 2477 } 2478 2479 /* Reserved Tx descriptors allocation request 2480 * 2481 * Called only from mvpp2_txq_reserved_desc_num_proc(), itself called 2482 * only by mvpp2_tx(), so migration is disabled, using 2483 * smp_processor_id() is OK. 2484 */ 2485 static int mvpp2_txq_alloc_reserved_desc(struct mvpp2_port *port, 2486 struct mvpp2_tx_queue *txq, int num) 2487 { 2488 unsigned int thread = mvpp2_cpu_to_thread(port->priv, smp_processor_id()); 2489 struct mvpp2 *priv = port->priv; 2490 u32 val; 2491 2492 val = (txq->id << MVPP2_TXQ_RSVD_REQ_Q_OFFSET) | num; 2493 mvpp2_thread_write_relaxed(priv, thread, MVPP2_TXQ_RSVD_REQ_REG, val); 2494 2495 val = mvpp2_thread_read_relaxed(priv, thread, MVPP2_TXQ_RSVD_RSLT_REG); 2496 2497 return val & MVPP2_TXQ_RSVD_RSLT_MASK; 2498 } 2499 2500 /* Check if there are enough reserved descriptors for transmission. 2501 * If not, request chunk of reserved descriptors and check again. 2502 */ 2503 static int mvpp2_txq_reserved_desc_num_proc(struct mvpp2_port *port, 2504 struct mvpp2_tx_queue *txq, 2505 struct mvpp2_txq_pcpu *txq_pcpu, 2506 int num) 2507 { 2508 int req, desc_count; 2509 unsigned int thread; 2510 2511 if (txq_pcpu->reserved_num >= num) 2512 return 0; 2513 2514 /* Not enough descriptors reserved! Update the reserved descriptor 2515 * count and check again. 2516 */ 2517 2518 desc_count = 0; 2519 /* Compute total of used descriptors */ 2520 for (thread = 0; thread < port->priv->nthreads; thread++) { 2521 struct mvpp2_txq_pcpu *txq_pcpu_aux; 2522 2523 txq_pcpu_aux = per_cpu_ptr(txq->pcpu, thread); 2524 desc_count += txq_pcpu_aux->count; 2525 desc_count += txq_pcpu_aux->reserved_num; 2526 } 2527 2528 req = max(MVPP2_CPU_DESC_CHUNK, num - txq_pcpu->reserved_num); 2529 desc_count += req; 2530 2531 if (desc_count > 2532 (txq->size - (MVPP2_MAX_THREADS * MVPP2_CPU_DESC_CHUNK))) 2533 return -ENOMEM; 2534 2535 txq_pcpu->reserved_num += mvpp2_txq_alloc_reserved_desc(port, txq, req); 2536 2537 /* OK, the descriptor could have been updated: check again. */ 2538 if (txq_pcpu->reserved_num < num) 2539 return -ENOMEM; 2540 return 0; 2541 } 2542 2543 /* Release the last allocated Tx descriptor. Useful to handle DMA 2544 * mapping failures in the Tx path. 2545 */ 2546 static void mvpp2_txq_desc_put(struct mvpp2_tx_queue *txq) 2547 { 2548 if (txq->next_desc_to_proc == 0) 2549 txq->next_desc_to_proc = txq->last_desc - 1; 2550 else 2551 txq->next_desc_to_proc--; 2552 } 2553 2554 /* Set Tx descriptors fields relevant for CSUM calculation */ 2555 static u32 mvpp2_txq_desc_csum(int l3_offs, __be16 l3_proto, 2556 int ip_hdr_len, int l4_proto) 2557 { 2558 u32 command; 2559 2560 /* fields: L3_offset, IP_hdrlen, L3_type, G_IPv4_chk, 2561 * G_L4_chk, L4_type required only for checksum calculation 2562 */ 2563 command = (l3_offs << MVPP2_TXD_L3_OFF_SHIFT); 2564 command |= (ip_hdr_len << MVPP2_TXD_IP_HLEN_SHIFT); 2565 command |= MVPP2_TXD_IP_CSUM_DISABLE; 2566 2567 if (l3_proto == htons(ETH_P_IP)) { 2568 command &= ~MVPP2_TXD_IP_CSUM_DISABLE; /* enable IPv4 csum */ 2569 command &= ~MVPP2_TXD_L3_IP6; /* enable IPv4 */ 2570 } else { 2571 command |= MVPP2_TXD_L3_IP6; /* enable IPv6 */ 2572 } 2573 2574 if (l4_proto == IPPROTO_TCP) { 2575 command &= ~MVPP2_TXD_L4_UDP; /* enable TCP */ 2576 command &= ~MVPP2_TXD_L4_CSUM_FRAG; /* generate L4 csum */ 2577 } else if (l4_proto == IPPROTO_UDP) { 2578 command |= MVPP2_TXD_L4_UDP; /* enable UDP */ 2579 command &= ~MVPP2_TXD_L4_CSUM_FRAG; /* generate L4 csum */ 2580 } else { 2581 command |= MVPP2_TXD_L4_CSUM_NOT; 2582 } 2583 2584 return command; 2585 } 2586 2587 /* Get number of sent descriptors and decrement counter. 2588 * The number of sent descriptors is returned. 2589 * Per-thread access 2590 * 2591 * Called only from mvpp2_txq_done(), called from mvpp2_tx() 2592 * (migration disabled) and from the TX completion tasklet (migration 2593 * disabled) so using smp_processor_id() is OK. 2594 */ 2595 static inline int mvpp2_txq_sent_desc_proc(struct mvpp2_port *port, 2596 struct mvpp2_tx_queue *txq) 2597 { 2598 u32 val; 2599 2600 /* Reading status reg resets transmitted descriptor counter */ 2601 val = mvpp2_thread_read_relaxed(port->priv, 2602 mvpp2_cpu_to_thread(port->priv, smp_processor_id()), 2603 MVPP2_TXQ_SENT_REG(txq->id)); 2604 2605 return (val & MVPP2_TRANSMITTED_COUNT_MASK) >> 2606 MVPP2_TRANSMITTED_COUNT_OFFSET; 2607 } 2608 2609 /* Called through on_each_cpu(), so runs on all CPUs, with migration 2610 * disabled, therefore using smp_processor_id() is OK. 2611 */ 2612 static void mvpp2_txq_sent_counter_clear(void *arg) 2613 { 2614 struct mvpp2_port *port = arg; 2615 int queue; 2616 2617 /* If the thread isn't used, don't do anything */ 2618 if (smp_processor_id() >= port->priv->nthreads) 2619 return; 2620 2621 for (queue = 0; queue < port->ntxqs; queue++) { 2622 int id = port->txqs[queue]->id; 2623 2624 mvpp2_thread_read(port->priv, 2625 mvpp2_cpu_to_thread(port->priv, smp_processor_id()), 2626 MVPP2_TXQ_SENT_REG(id)); 2627 } 2628 } 2629 2630 /* Set max sizes for Tx queues */ 2631 static void mvpp2_txp_max_tx_size_set(struct mvpp2_port *port) 2632 { 2633 u32 val, size, mtu; 2634 int txq, tx_port_num; 2635 2636 mtu = port->pkt_size * 8; 2637 if (mtu > MVPP2_TXP_MTU_MAX) 2638 mtu = MVPP2_TXP_MTU_MAX; 2639 2640 /* WA for wrong Token bucket update: Set MTU value = 3*real MTU value */ 2641 mtu = 3 * mtu; 2642 2643 /* Indirect access to registers */ 2644 tx_port_num = mvpp2_egress_port(port); 2645 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num); 2646 2647 /* Set MTU */ 2648 val = mvpp2_read(port->priv, MVPP2_TXP_SCHED_MTU_REG); 2649 val &= ~MVPP2_TXP_MTU_MAX; 2650 val |= mtu; 2651 mvpp2_write(port->priv, MVPP2_TXP_SCHED_MTU_REG, val); 2652 2653 /* TXP token size and all TXQs token size must be larger that MTU */ 2654 val = mvpp2_read(port->priv, MVPP2_TXP_SCHED_TOKEN_SIZE_REG); 2655 size = val & MVPP2_TXP_TOKEN_SIZE_MAX; 2656 if (size < mtu) { 2657 size = mtu; 2658 val &= ~MVPP2_TXP_TOKEN_SIZE_MAX; 2659 val |= size; 2660 mvpp2_write(port->priv, MVPP2_TXP_SCHED_TOKEN_SIZE_REG, val); 2661 } 2662 2663 for (txq = 0; txq < port->ntxqs; txq++) { 2664 val = mvpp2_read(port->priv, 2665 MVPP2_TXQ_SCHED_TOKEN_SIZE_REG(txq)); 2666 size = val & MVPP2_TXQ_TOKEN_SIZE_MAX; 2667 2668 if (size < mtu) { 2669 size = mtu; 2670 val &= ~MVPP2_TXQ_TOKEN_SIZE_MAX; 2671 val |= size; 2672 mvpp2_write(port->priv, 2673 MVPP2_TXQ_SCHED_TOKEN_SIZE_REG(txq), 2674 val); 2675 } 2676 } 2677 } 2678 2679 /* Set the number of non-occupied descriptors threshold */ 2680 static void mvpp2_set_rxq_free_tresh(struct mvpp2_port *port, 2681 struct mvpp2_rx_queue *rxq) 2682 { 2683 u32 val; 2684 2685 mvpp2_write(port->priv, MVPP2_RXQ_NUM_REG, rxq->id); 2686 2687 val = mvpp2_read(port->priv, MVPP2_RXQ_THRESH_REG); 2688 val &= ~MVPP2_RXQ_NON_OCCUPIED_MASK; 2689 val |= MSS_THRESHOLD_STOP << MVPP2_RXQ_NON_OCCUPIED_OFFSET; 2690 mvpp2_write(port->priv, MVPP2_RXQ_THRESH_REG, val); 2691 } 2692 2693 /* Set the number of packets that will be received before Rx interrupt 2694 * will be generated by HW. 2695 */ 2696 static void mvpp2_rx_pkts_coal_set(struct mvpp2_port *port, 2697 struct mvpp2_rx_queue *rxq) 2698 { 2699 unsigned int thread = mvpp2_cpu_to_thread(port->priv, get_cpu()); 2700 2701 if (rxq->pkts_coal > MVPP2_OCCUPIED_THRESH_MASK) 2702 rxq->pkts_coal = MVPP2_OCCUPIED_THRESH_MASK; 2703 2704 mvpp2_thread_write(port->priv, thread, MVPP2_RXQ_NUM_REG, rxq->id); 2705 mvpp2_thread_write(port->priv, thread, MVPP2_RXQ_THRESH_REG, 2706 rxq->pkts_coal); 2707 2708 put_cpu(); 2709 } 2710 2711 /* For some reason in the LSP this is done on each CPU. Why ? */ 2712 static void mvpp2_tx_pkts_coal_set(struct mvpp2_port *port, 2713 struct mvpp2_tx_queue *txq) 2714 { 2715 unsigned int thread; 2716 u32 val; 2717 2718 if (txq->done_pkts_coal > MVPP2_TXQ_THRESH_MASK) 2719 txq->done_pkts_coal = MVPP2_TXQ_THRESH_MASK; 2720 2721 val = (txq->done_pkts_coal << MVPP2_TXQ_THRESH_OFFSET); 2722 /* PKT-coalescing registers are per-queue + per-thread */ 2723 for (thread = 0; thread < MVPP2_MAX_THREADS; thread++) { 2724 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_NUM_REG, txq->id); 2725 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_THRESH_REG, val); 2726 } 2727 } 2728 2729 static u32 mvpp2_usec_to_cycles(u32 usec, unsigned long clk_hz) 2730 { 2731 u64 tmp = (u64)clk_hz * usec; 2732 2733 do_div(tmp, USEC_PER_SEC); 2734 2735 return tmp > U32_MAX ? U32_MAX : tmp; 2736 } 2737 2738 static u32 mvpp2_cycles_to_usec(u32 cycles, unsigned long clk_hz) 2739 { 2740 u64 tmp = (u64)cycles * USEC_PER_SEC; 2741 2742 do_div(tmp, clk_hz); 2743 2744 return tmp > U32_MAX ? U32_MAX : tmp; 2745 } 2746 2747 /* Set the time delay in usec before Rx interrupt */ 2748 static void mvpp2_rx_time_coal_set(struct mvpp2_port *port, 2749 struct mvpp2_rx_queue *rxq) 2750 { 2751 unsigned long freq = port->priv->tclk; 2752 u32 val = mvpp2_usec_to_cycles(rxq->time_coal, freq); 2753 2754 if (val > MVPP2_MAX_ISR_RX_THRESHOLD) { 2755 rxq->time_coal = 2756 mvpp2_cycles_to_usec(MVPP2_MAX_ISR_RX_THRESHOLD, freq); 2757 2758 /* re-evaluate to get actual register value */ 2759 val = mvpp2_usec_to_cycles(rxq->time_coal, freq); 2760 } 2761 2762 mvpp2_write(port->priv, MVPP2_ISR_RX_THRESHOLD_REG(rxq->id), val); 2763 } 2764 2765 static void mvpp2_tx_time_coal_set(struct mvpp2_port *port) 2766 { 2767 unsigned long freq = port->priv->tclk; 2768 u32 val = mvpp2_usec_to_cycles(port->tx_time_coal, freq); 2769 2770 if (val > MVPP2_MAX_ISR_TX_THRESHOLD) { 2771 port->tx_time_coal = 2772 mvpp2_cycles_to_usec(MVPP2_MAX_ISR_TX_THRESHOLD, freq); 2773 2774 /* re-evaluate to get actual register value */ 2775 val = mvpp2_usec_to_cycles(port->tx_time_coal, freq); 2776 } 2777 2778 mvpp2_write(port->priv, MVPP2_ISR_TX_THRESHOLD_REG(port->id), val); 2779 } 2780 2781 /* Free Tx queue skbuffs */ 2782 static void mvpp2_txq_bufs_free(struct mvpp2_port *port, 2783 struct mvpp2_tx_queue *txq, 2784 struct mvpp2_txq_pcpu *txq_pcpu, int num) 2785 { 2786 struct xdp_frame_bulk bq; 2787 int i; 2788 2789 xdp_frame_bulk_init(&bq); 2790 2791 rcu_read_lock(); /* need for xdp_return_frame_bulk */ 2792 2793 for (i = 0; i < num; i++) { 2794 struct mvpp2_txq_pcpu_buf *tx_buf = 2795 txq_pcpu->buffs + txq_pcpu->txq_get_index; 2796 2797 if (!IS_TSO_HEADER(txq_pcpu, tx_buf->dma) && 2798 tx_buf->type != MVPP2_TYPE_XDP_TX) 2799 dma_unmap_single(port->dev->dev.parent, tx_buf->dma, 2800 tx_buf->size, DMA_TO_DEVICE); 2801 if (tx_buf->type == MVPP2_TYPE_SKB && tx_buf->skb) 2802 dev_kfree_skb_any(tx_buf->skb); 2803 else if (tx_buf->type == MVPP2_TYPE_XDP_TX || 2804 tx_buf->type == MVPP2_TYPE_XDP_NDO) 2805 xdp_return_frame_bulk(tx_buf->xdpf, &bq); 2806 2807 mvpp2_txq_inc_get(txq_pcpu); 2808 } 2809 xdp_flush_frame_bulk(&bq); 2810 2811 rcu_read_unlock(); 2812 } 2813 2814 static inline struct mvpp2_rx_queue *mvpp2_get_rx_queue(struct mvpp2_port *port, 2815 u32 cause) 2816 { 2817 int queue = fls(cause) - 1; 2818 2819 return port->rxqs[queue]; 2820 } 2821 2822 static inline struct mvpp2_tx_queue *mvpp2_get_tx_queue(struct mvpp2_port *port, 2823 u32 cause) 2824 { 2825 int queue = fls(cause) - 1; 2826 2827 return port->txqs[queue]; 2828 } 2829 2830 /* Handle end of transmission */ 2831 static void mvpp2_txq_done(struct mvpp2_port *port, struct mvpp2_tx_queue *txq, 2832 struct mvpp2_txq_pcpu *txq_pcpu) 2833 { 2834 struct netdev_queue *nq = netdev_get_tx_queue(port->dev, txq->log_id); 2835 int tx_done; 2836 2837 if (txq_pcpu->thread != mvpp2_cpu_to_thread(port->priv, smp_processor_id())) 2838 netdev_err(port->dev, "wrong cpu on the end of Tx processing\n"); 2839 2840 tx_done = mvpp2_txq_sent_desc_proc(port, txq); 2841 if (!tx_done) 2842 return; 2843 mvpp2_txq_bufs_free(port, txq, txq_pcpu, tx_done); 2844 2845 txq_pcpu->count -= tx_done; 2846 2847 if (netif_tx_queue_stopped(nq)) 2848 if (txq_pcpu->count <= txq_pcpu->wake_threshold) 2849 netif_tx_wake_queue(nq); 2850 } 2851 2852 static unsigned int mvpp2_tx_done(struct mvpp2_port *port, u32 cause, 2853 unsigned int thread) 2854 { 2855 struct mvpp2_tx_queue *txq; 2856 struct mvpp2_txq_pcpu *txq_pcpu; 2857 unsigned int tx_todo = 0; 2858 2859 while (cause) { 2860 txq = mvpp2_get_tx_queue(port, cause); 2861 if (!txq) 2862 break; 2863 2864 txq_pcpu = per_cpu_ptr(txq->pcpu, thread); 2865 2866 if (txq_pcpu->count) { 2867 mvpp2_txq_done(port, txq, txq_pcpu); 2868 tx_todo += txq_pcpu->count; 2869 } 2870 2871 cause &= ~(1 << txq->log_id); 2872 } 2873 return tx_todo; 2874 } 2875 2876 /* Rx/Tx queue initialization/cleanup methods */ 2877 2878 /* Allocate and initialize descriptors for aggr TXQ */ 2879 static int mvpp2_aggr_txq_init(struct platform_device *pdev, 2880 struct mvpp2_tx_queue *aggr_txq, 2881 unsigned int thread, struct mvpp2 *priv) 2882 { 2883 u32 txq_dma; 2884 2885 /* Allocate memory for TX descriptors */ 2886 aggr_txq->descs = dma_alloc_coherent(&pdev->dev, 2887 MVPP2_AGGR_TXQ_SIZE * MVPP2_DESC_ALIGNED_SIZE, 2888 &aggr_txq->descs_dma, GFP_KERNEL); 2889 if (!aggr_txq->descs) 2890 return -ENOMEM; 2891 2892 aggr_txq->last_desc = MVPP2_AGGR_TXQ_SIZE - 1; 2893 2894 /* Aggr TXQ no reset WA */ 2895 aggr_txq->next_desc_to_proc = mvpp2_read(priv, 2896 MVPP2_AGGR_TXQ_INDEX_REG(thread)); 2897 2898 /* Set Tx descriptors queue starting address indirect 2899 * access 2900 */ 2901 if (priv->hw_version == MVPP21) 2902 txq_dma = aggr_txq->descs_dma; 2903 else 2904 txq_dma = aggr_txq->descs_dma >> 2905 MVPP22_AGGR_TXQ_DESC_ADDR_OFFS; 2906 2907 mvpp2_write(priv, MVPP2_AGGR_TXQ_DESC_ADDR_REG(thread), txq_dma); 2908 mvpp2_write(priv, MVPP2_AGGR_TXQ_DESC_SIZE_REG(thread), 2909 MVPP2_AGGR_TXQ_SIZE); 2910 2911 return 0; 2912 } 2913 2914 /* Create a specified Rx queue */ 2915 static int mvpp2_rxq_init(struct mvpp2_port *port, 2916 struct mvpp2_rx_queue *rxq) 2917 { 2918 struct mvpp2 *priv = port->priv; 2919 unsigned int thread; 2920 u32 rxq_dma; 2921 int err; 2922 2923 rxq->size = port->rx_ring_size; 2924 2925 /* Allocate memory for RX descriptors */ 2926 rxq->descs = dma_alloc_coherent(port->dev->dev.parent, 2927 rxq->size * MVPP2_DESC_ALIGNED_SIZE, 2928 &rxq->descs_dma, GFP_KERNEL); 2929 if (!rxq->descs) 2930 return -ENOMEM; 2931 2932 rxq->last_desc = rxq->size - 1; 2933 2934 /* Zero occupied and non-occupied counters - direct access */ 2935 mvpp2_write(port->priv, MVPP2_RXQ_STATUS_REG(rxq->id), 0); 2936 2937 /* Set Rx descriptors queue starting address - indirect access */ 2938 thread = mvpp2_cpu_to_thread(port->priv, get_cpu()); 2939 mvpp2_thread_write(port->priv, thread, MVPP2_RXQ_NUM_REG, rxq->id); 2940 if (port->priv->hw_version == MVPP21) 2941 rxq_dma = rxq->descs_dma; 2942 else 2943 rxq_dma = rxq->descs_dma >> MVPP22_DESC_ADDR_OFFS; 2944 mvpp2_thread_write(port->priv, thread, MVPP2_RXQ_DESC_ADDR_REG, rxq_dma); 2945 mvpp2_thread_write(port->priv, thread, MVPP2_RXQ_DESC_SIZE_REG, rxq->size); 2946 mvpp2_thread_write(port->priv, thread, MVPP2_RXQ_INDEX_REG, 0); 2947 put_cpu(); 2948 2949 /* Set Offset */ 2950 mvpp2_rxq_offset_set(port, rxq->id, MVPP2_SKB_HEADROOM); 2951 2952 /* Set coalescing pkts and time */ 2953 mvpp2_rx_pkts_coal_set(port, rxq); 2954 mvpp2_rx_time_coal_set(port, rxq); 2955 2956 /* Set the number of non occupied descriptors threshold */ 2957 mvpp2_set_rxq_free_tresh(port, rxq); 2958 2959 /* Add number of descriptors ready for receiving packets */ 2960 mvpp2_rxq_status_update(port, rxq->id, 0, rxq->size); 2961 2962 if (priv->percpu_pools) { 2963 err = xdp_rxq_info_reg(&rxq->xdp_rxq_short, port->dev, rxq->id, 0); 2964 if (err < 0) 2965 goto err_free_dma; 2966 2967 err = xdp_rxq_info_reg(&rxq->xdp_rxq_long, port->dev, rxq->id, 0); 2968 if (err < 0) 2969 goto err_unregister_rxq_short; 2970 2971 /* Every RXQ has a pool for short and another for long packets */ 2972 err = xdp_rxq_info_reg_mem_model(&rxq->xdp_rxq_short, 2973 MEM_TYPE_PAGE_POOL, 2974 priv->page_pool[rxq->logic_rxq]); 2975 if (err < 0) 2976 goto err_unregister_rxq_long; 2977 2978 err = xdp_rxq_info_reg_mem_model(&rxq->xdp_rxq_long, 2979 MEM_TYPE_PAGE_POOL, 2980 priv->page_pool[rxq->logic_rxq + 2981 port->nrxqs]); 2982 if (err < 0) 2983 goto err_unregister_mem_rxq_short; 2984 } 2985 2986 return 0; 2987 2988 err_unregister_mem_rxq_short: 2989 xdp_rxq_info_unreg_mem_model(&rxq->xdp_rxq_short); 2990 err_unregister_rxq_long: 2991 xdp_rxq_info_unreg(&rxq->xdp_rxq_long); 2992 err_unregister_rxq_short: 2993 xdp_rxq_info_unreg(&rxq->xdp_rxq_short); 2994 err_free_dma: 2995 dma_free_coherent(port->dev->dev.parent, 2996 rxq->size * MVPP2_DESC_ALIGNED_SIZE, 2997 rxq->descs, rxq->descs_dma); 2998 return err; 2999 } 3000 3001 /* Push packets received by the RXQ to BM pool */ 3002 static void mvpp2_rxq_drop_pkts(struct mvpp2_port *port, 3003 struct mvpp2_rx_queue *rxq) 3004 { 3005 int rx_received, i; 3006 3007 rx_received = mvpp2_rxq_received(port, rxq->id); 3008 if (!rx_received) 3009 return; 3010 3011 for (i = 0; i < rx_received; i++) { 3012 struct mvpp2_rx_desc *rx_desc = mvpp2_rxq_next_desc_get(rxq); 3013 u32 status = mvpp2_rxdesc_status_get(port, rx_desc); 3014 int pool; 3015 3016 pool = (status & MVPP2_RXD_BM_POOL_ID_MASK) >> 3017 MVPP2_RXD_BM_POOL_ID_OFFS; 3018 3019 mvpp2_bm_pool_put(port, pool, 3020 mvpp2_rxdesc_dma_addr_get(port, rx_desc), 3021 mvpp2_rxdesc_cookie_get(port, rx_desc)); 3022 } 3023 mvpp2_rxq_status_update(port, rxq->id, rx_received, rx_received); 3024 } 3025 3026 /* Cleanup Rx queue */ 3027 static void mvpp2_rxq_deinit(struct mvpp2_port *port, 3028 struct mvpp2_rx_queue *rxq) 3029 { 3030 unsigned int thread; 3031 3032 if (xdp_rxq_info_is_reg(&rxq->xdp_rxq_short)) 3033 xdp_rxq_info_unreg(&rxq->xdp_rxq_short); 3034 3035 if (xdp_rxq_info_is_reg(&rxq->xdp_rxq_long)) 3036 xdp_rxq_info_unreg(&rxq->xdp_rxq_long); 3037 3038 mvpp2_rxq_drop_pkts(port, rxq); 3039 3040 if (rxq->descs) 3041 dma_free_coherent(port->dev->dev.parent, 3042 rxq->size * MVPP2_DESC_ALIGNED_SIZE, 3043 rxq->descs, 3044 rxq->descs_dma); 3045 3046 rxq->descs = NULL; 3047 rxq->last_desc = 0; 3048 rxq->next_desc_to_proc = 0; 3049 rxq->descs_dma = 0; 3050 3051 /* Clear Rx descriptors queue starting address and size; 3052 * free descriptor number 3053 */ 3054 mvpp2_write(port->priv, MVPP2_RXQ_STATUS_REG(rxq->id), 0); 3055 thread = mvpp2_cpu_to_thread(port->priv, get_cpu()); 3056 mvpp2_thread_write(port->priv, thread, MVPP2_RXQ_NUM_REG, rxq->id); 3057 mvpp2_thread_write(port->priv, thread, MVPP2_RXQ_DESC_ADDR_REG, 0); 3058 mvpp2_thread_write(port->priv, thread, MVPP2_RXQ_DESC_SIZE_REG, 0); 3059 put_cpu(); 3060 } 3061 3062 /* Create and initialize a Tx queue */ 3063 static int mvpp2_txq_init(struct mvpp2_port *port, 3064 struct mvpp2_tx_queue *txq) 3065 { 3066 u32 val; 3067 unsigned int thread; 3068 int desc, desc_per_txq, tx_port_num; 3069 struct mvpp2_txq_pcpu *txq_pcpu; 3070 3071 txq->size = port->tx_ring_size; 3072 3073 /* Allocate memory for Tx descriptors */ 3074 txq->descs = dma_alloc_coherent(port->dev->dev.parent, 3075 txq->size * MVPP2_DESC_ALIGNED_SIZE, 3076 &txq->descs_dma, GFP_KERNEL); 3077 if (!txq->descs) 3078 return -ENOMEM; 3079 3080 txq->last_desc = txq->size - 1; 3081 3082 /* Set Tx descriptors queue starting address - indirect access */ 3083 thread = mvpp2_cpu_to_thread(port->priv, get_cpu()); 3084 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_NUM_REG, txq->id); 3085 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_DESC_ADDR_REG, 3086 txq->descs_dma); 3087 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_DESC_SIZE_REG, 3088 txq->size & MVPP2_TXQ_DESC_SIZE_MASK); 3089 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_INDEX_REG, 0); 3090 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_RSVD_CLR_REG, 3091 txq->id << MVPP2_TXQ_RSVD_CLR_OFFSET); 3092 val = mvpp2_thread_read(port->priv, thread, MVPP2_TXQ_PENDING_REG); 3093 val &= ~MVPP2_TXQ_PENDING_MASK; 3094 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_PENDING_REG, val); 3095 3096 /* Calculate base address in prefetch buffer. We reserve 16 descriptors 3097 * for each existing TXQ. 3098 * TCONTS for PON port must be continuous from 0 to MVPP2_MAX_TCONT 3099 * GBE ports assumed to be continuous from 0 to MVPP2_MAX_PORTS 3100 */ 3101 desc_per_txq = 16; 3102 desc = (port->id * MVPP2_MAX_TXQ * desc_per_txq) + 3103 (txq->log_id * desc_per_txq); 3104 3105 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_PREF_BUF_REG, 3106 MVPP2_PREF_BUF_PTR(desc) | MVPP2_PREF_BUF_SIZE_16 | 3107 MVPP2_PREF_BUF_THRESH(desc_per_txq / 2)); 3108 put_cpu(); 3109 3110 /* WRR / EJP configuration - indirect access */ 3111 tx_port_num = mvpp2_egress_port(port); 3112 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num); 3113 3114 val = mvpp2_read(port->priv, MVPP2_TXQ_SCHED_REFILL_REG(txq->log_id)); 3115 val &= ~MVPP2_TXQ_REFILL_PERIOD_ALL_MASK; 3116 val |= MVPP2_TXQ_REFILL_PERIOD_MASK(1); 3117 val |= MVPP2_TXQ_REFILL_TOKENS_ALL_MASK; 3118 mvpp2_write(port->priv, MVPP2_TXQ_SCHED_REFILL_REG(txq->log_id), val); 3119 3120 val = MVPP2_TXQ_TOKEN_SIZE_MAX; 3121 mvpp2_write(port->priv, MVPP2_TXQ_SCHED_TOKEN_SIZE_REG(txq->log_id), 3122 val); 3123 3124 for (thread = 0; thread < port->priv->nthreads; thread++) { 3125 txq_pcpu = per_cpu_ptr(txq->pcpu, thread); 3126 txq_pcpu->size = txq->size; 3127 txq_pcpu->buffs = kmalloc_array(txq_pcpu->size, 3128 sizeof(*txq_pcpu->buffs), 3129 GFP_KERNEL); 3130 if (!txq_pcpu->buffs) 3131 return -ENOMEM; 3132 3133 txq_pcpu->count = 0; 3134 txq_pcpu->reserved_num = 0; 3135 txq_pcpu->txq_put_index = 0; 3136 txq_pcpu->txq_get_index = 0; 3137 txq_pcpu->tso_headers = NULL; 3138 3139 txq_pcpu->stop_threshold = txq->size - MVPP2_MAX_SKB_DESCS; 3140 txq_pcpu->wake_threshold = txq_pcpu->stop_threshold / 2; 3141 3142 txq_pcpu->tso_headers = 3143 dma_alloc_coherent(port->dev->dev.parent, 3144 txq_pcpu->size * TSO_HEADER_SIZE, 3145 &txq_pcpu->tso_headers_dma, 3146 GFP_KERNEL); 3147 if (!txq_pcpu->tso_headers) 3148 return -ENOMEM; 3149 } 3150 3151 return 0; 3152 } 3153 3154 /* Free allocated TXQ resources */ 3155 static void mvpp2_txq_deinit(struct mvpp2_port *port, 3156 struct mvpp2_tx_queue *txq) 3157 { 3158 struct mvpp2_txq_pcpu *txq_pcpu; 3159 unsigned int thread; 3160 3161 for (thread = 0; thread < port->priv->nthreads; thread++) { 3162 txq_pcpu = per_cpu_ptr(txq->pcpu, thread); 3163 kfree(txq_pcpu->buffs); 3164 3165 if (txq_pcpu->tso_headers) 3166 dma_free_coherent(port->dev->dev.parent, 3167 txq_pcpu->size * TSO_HEADER_SIZE, 3168 txq_pcpu->tso_headers, 3169 txq_pcpu->tso_headers_dma); 3170 3171 txq_pcpu->tso_headers = NULL; 3172 } 3173 3174 if (txq->descs) 3175 dma_free_coherent(port->dev->dev.parent, 3176 txq->size * MVPP2_DESC_ALIGNED_SIZE, 3177 txq->descs, txq->descs_dma); 3178 3179 txq->descs = NULL; 3180 txq->last_desc = 0; 3181 txq->next_desc_to_proc = 0; 3182 txq->descs_dma = 0; 3183 3184 /* Set minimum bandwidth for disabled TXQs */ 3185 mvpp2_write(port->priv, MVPP2_TXQ_SCHED_TOKEN_CNTR_REG(txq->log_id), 0); 3186 3187 /* Set Tx descriptors queue starting address and size */ 3188 thread = mvpp2_cpu_to_thread(port->priv, get_cpu()); 3189 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_NUM_REG, txq->id); 3190 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_DESC_ADDR_REG, 0); 3191 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_DESC_SIZE_REG, 0); 3192 put_cpu(); 3193 } 3194 3195 /* Cleanup Tx ports */ 3196 static void mvpp2_txq_clean(struct mvpp2_port *port, struct mvpp2_tx_queue *txq) 3197 { 3198 struct mvpp2_txq_pcpu *txq_pcpu; 3199 int delay, pending; 3200 unsigned int thread = mvpp2_cpu_to_thread(port->priv, get_cpu()); 3201 u32 val; 3202 3203 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_NUM_REG, txq->id); 3204 val = mvpp2_thread_read(port->priv, thread, MVPP2_TXQ_PREF_BUF_REG); 3205 val |= MVPP2_TXQ_DRAIN_EN_MASK; 3206 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_PREF_BUF_REG, val); 3207 3208 /* The napi queue has been stopped so wait for all packets 3209 * to be transmitted. 3210 */ 3211 delay = 0; 3212 do { 3213 if (delay >= MVPP2_TX_PENDING_TIMEOUT_MSEC) { 3214 netdev_warn(port->dev, 3215 "port %d: cleaning queue %d timed out\n", 3216 port->id, txq->log_id); 3217 break; 3218 } 3219 mdelay(1); 3220 delay++; 3221 3222 pending = mvpp2_thread_read(port->priv, thread, 3223 MVPP2_TXQ_PENDING_REG); 3224 pending &= MVPP2_TXQ_PENDING_MASK; 3225 } while (pending); 3226 3227 val &= ~MVPP2_TXQ_DRAIN_EN_MASK; 3228 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_PREF_BUF_REG, val); 3229 put_cpu(); 3230 3231 for (thread = 0; thread < port->priv->nthreads; thread++) { 3232 txq_pcpu = per_cpu_ptr(txq->pcpu, thread); 3233 3234 /* Release all packets */ 3235 mvpp2_txq_bufs_free(port, txq, txq_pcpu, txq_pcpu->count); 3236 3237 /* Reset queue */ 3238 txq_pcpu->count = 0; 3239 txq_pcpu->txq_put_index = 0; 3240 txq_pcpu->txq_get_index = 0; 3241 } 3242 } 3243 3244 /* Cleanup all Tx queues */ 3245 static void mvpp2_cleanup_txqs(struct mvpp2_port *port) 3246 { 3247 struct mvpp2_tx_queue *txq; 3248 int queue; 3249 u32 val; 3250 3251 val = mvpp2_read(port->priv, MVPP2_TX_PORT_FLUSH_REG); 3252 3253 /* Reset Tx ports and delete Tx queues */ 3254 val |= MVPP2_TX_PORT_FLUSH_MASK(port->id); 3255 mvpp2_write(port->priv, MVPP2_TX_PORT_FLUSH_REG, val); 3256 3257 for (queue = 0; queue < port->ntxqs; queue++) { 3258 txq = port->txqs[queue]; 3259 mvpp2_txq_clean(port, txq); 3260 mvpp2_txq_deinit(port, txq); 3261 } 3262 3263 on_each_cpu(mvpp2_txq_sent_counter_clear, port, 1); 3264 3265 val &= ~MVPP2_TX_PORT_FLUSH_MASK(port->id); 3266 mvpp2_write(port->priv, MVPP2_TX_PORT_FLUSH_REG, val); 3267 } 3268 3269 /* Cleanup all Rx queues */ 3270 static void mvpp2_cleanup_rxqs(struct mvpp2_port *port) 3271 { 3272 int queue; 3273 3274 for (queue = 0; queue < port->nrxqs; queue++) 3275 mvpp2_rxq_deinit(port, port->rxqs[queue]); 3276 3277 if (port->tx_fc) 3278 mvpp2_rxq_disable_fc(port); 3279 } 3280 3281 /* Init all Rx queues for port */ 3282 static int mvpp2_setup_rxqs(struct mvpp2_port *port) 3283 { 3284 int queue, err; 3285 3286 for (queue = 0; queue < port->nrxqs; queue++) { 3287 err = mvpp2_rxq_init(port, port->rxqs[queue]); 3288 if (err) 3289 goto err_cleanup; 3290 } 3291 3292 if (port->tx_fc) 3293 mvpp2_rxq_enable_fc(port); 3294 3295 return 0; 3296 3297 err_cleanup: 3298 mvpp2_cleanup_rxqs(port); 3299 return err; 3300 } 3301 3302 /* Init all tx queues for port */ 3303 static int mvpp2_setup_txqs(struct mvpp2_port *port) 3304 { 3305 struct mvpp2_tx_queue *txq; 3306 int queue, err; 3307 3308 for (queue = 0; queue < port->ntxqs; queue++) { 3309 txq = port->txqs[queue]; 3310 err = mvpp2_txq_init(port, txq); 3311 if (err) 3312 goto err_cleanup; 3313 3314 /* Assign this queue to a CPU */ 3315 if (queue < num_possible_cpus()) 3316 netif_set_xps_queue(port->dev, cpumask_of(queue), queue); 3317 } 3318 3319 if (port->has_tx_irqs) { 3320 mvpp2_tx_time_coal_set(port); 3321 for (queue = 0; queue < port->ntxqs; queue++) { 3322 txq = port->txqs[queue]; 3323 mvpp2_tx_pkts_coal_set(port, txq); 3324 } 3325 } 3326 3327 on_each_cpu(mvpp2_txq_sent_counter_clear, port, 1); 3328 return 0; 3329 3330 err_cleanup: 3331 mvpp2_cleanup_txqs(port); 3332 return err; 3333 } 3334 3335 /* The callback for per-port interrupt */ 3336 static irqreturn_t mvpp2_isr(int irq, void *dev_id) 3337 { 3338 struct mvpp2_queue_vector *qv = dev_id; 3339 3340 mvpp2_qvec_interrupt_disable(qv); 3341 3342 napi_schedule(&qv->napi); 3343 3344 return IRQ_HANDLED; 3345 } 3346 3347 static void mvpp2_isr_handle_ptp_queue(struct mvpp2_port *port, int nq) 3348 { 3349 struct skb_shared_hwtstamps shhwtstamps; 3350 struct mvpp2_hwtstamp_queue *queue; 3351 struct sk_buff *skb; 3352 void __iomem *ptp_q; 3353 unsigned int id; 3354 u32 r0, r1, r2; 3355 3356 ptp_q = port->priv->iface_base + MVPP22_PTP_BASE(port->gop_id); 3357 if (nq) 3358 ptp_q += MVPP22_PTP_TX_Q1_R0 - MVPP22_PTP_TX_Q0_R0; 3359 3360 queue = &port->tx_hwtstamp_queue[nq]; 3361 3362 while (1) { 3363 r0 = readl_relaxed(ptp_q + MVPP22_PTP_TX_Q0_R0) & 0xffff; 3364 if (!r0) 3365 break; 3366 3367 r1 = readl_relaxed(ptp_q + MVPP22_PTP_TX_Q0_R1) & 0xffff; 3368 r2 = readl_relaxed(ptp_q + MVPP22_PTP_TX_Q0_R2) & 0xffff; 3369 3370 id = (r0 >> 1) & 31; 3371 3372 skb = queue->skb[id]; 3373 queue->skb[id] = NULL; 3374 if (skb) { 3375 u32 ts = r2 << 19 | r1 << 3 | r0 >> 13; 3376 3377 mvpp22_tai_tstamp(port->priv->tai, ts, &shhwtstamps); 3378 skb_tstamp_tx(skb, &shhwtstamps); 3379 dev_kfree_skb_any(skb); 3380 } 3381 } 3382 } 3383 3384 static void mvpp2_isr_handle_ptp(struct mvpp2_port *port) 3385 { 3386 void __iomem *ptp; 3387 u32 val; 3388 3389 ptp = port->priv->iface_base + MVPP22_PTP_BASE(port->gop_id); 3390 val = readl(ptp + MVPP22_PTP_INT_CAUSE); 3391 if (val & MVPP22_PTP_INT_CAUSE_QUEUE0) 3392 mvpp2_isr_handle_ptp_queue(port, 0); 3393 if (val & MVPP22_PTP_INT_CAUSE_QUEUE1) 3394 mvpp2_isr_handle_ptp_queue(port, 1); 3395 } 3396 3397 static void mvpp2_isr_handle_link(struct mvpp2_port *port, bool link) 3398 { 3399 struct net_device *dev = port->dev; 3400 3401 if (port->phylink) { 3402 phylink_mac_change(port->phylink, link); 3403 return; 3404 } 3405 3406 if (!netif_running(dev)) 3407 return; 3408 3409 if (link) { 3410 mvpp2_interrupts_enable(port); 3411 3412 mvpp2_egress_enable(port); 3413 mvpp2_ingress_enable(port); 3414 netif_carrier_on(dev); 3415 netif_tx_wake_all_queues(dev); 3416 } else { 3417 netif_tx_stop_all_queues(dev); 3418 netif_carrier_off(dev); 3419 mvpp2_ingress_disable(port); 3420 mvpp2_egress_disable(port); 3421 3422 mvpp2_interrupts_disable(port); 3423 } 3424 } 3425 3426 static void mvpp2_isr_handle_xlg(struct mvpp2_port *port) 3427 { 3428 bool link; 3429 u32 val; 3430 3431 val = readl(port->base + MVPP22_XLG_INT_STAT); 3432 if (val & MVPP22_XLG_INT_STAT_LINK) { 3433 val = readl(port->base + MVPP22_XLG_STATUS); 3434 link = (val & MVPP22_XLG_STATUS_LINK_UP); 3435 mvpp2_isr_handle_link(port, link); 3436 } 3437 } 3438 3439 static void mvpp2_isr_handle_gmac_internal(struct mvpp2_port *port) 3440 { 3441 bool link; 3442 u32 val; 3443 3444 if (phy_interface_mode_is_rgmii(port->phy_interface) || 3445 phy_interface_mode_is_8023z(port->phy_interface) || 3446 port->phy_interface == PHY_INTERFACE_MODE_SGMII) { 3447 val = readl(port->base + MVPP22_GMAC_INT_STAT); 3448 if (val & MVPP22_GMAC_INT_STAT_LINK) { 3449 val = readl(port->base + MVPP2_GMAC_STATUS0); 3450 link = (val & MVPP2_GMAC_STATUS0_LINK_UP); 3451 mvpp2_isr_handle_link(port, link); 3452 } 3453 } 3454 } 3455 3456 /* Per-port interrupt for link status changes */ 3457 static irqreturn_t mvpp2_port_isr(int irq, void *dev_id) 3458 { 3459 struct mvpp2_port *port = (struct mvpp2_port *)dev_id; 3460 u32 val; 3461 3462 mvpp22_gop_mask_irq(port); 3463 3464 if (mvpp2_port_supports_xlg(port) && 3465 mvpp2_is_xlg(port->phy_interface)) { 3466 /* Check the external status register */ 3467 val = readl(port->base + MVPP22_XLG_EXT_INT_STAT); 3468 if (val & MVPP22_XLG_EXT_INT_STAT_XLG) 3469 mvpp2_isr_handle_xlg(port); 3470 if (val & MVPP22_XLG_EXT_INT_STAT_PTP) 3471 mvpp2_isr_handle_ptp(port); 3472 } else { 3473 /* If it's not the XLG, we must be using the GMAC. 3474 * Check the summary status. 3475 */ 3476 val = readl(port->base + MVPP22_GMAC_INT_SUM_STAT); 3477 if (val & MVPP22_GMAC_INT_SUM_STAT_INTERNAL) 3478 mvpp2_isr_handle_gmac_internal(port); 3479 if (val & MVPP22_GMAC_INT_SUM_STAT_PTP) 3480 mvpp2_isr_handle_ptp(port); 3481 } 3482 3483 mvpp22_gop_unmask_irq(port); 3484 return IRQ_HANDLED; 3485 } 3486 3487 static enum hrtimer_restart mvpp2_hr_timer_cb(struct hrtimer *timer) 3488 { 3489 struct net_device *dev; 3490 struct mvpp2_port *port; 3491 struct mvpp2_port_pcpu *port_pcpu; 3492 unsigned int tx_todo, cause; 3493 3494 port_pcpu = container_of(timer, struct mvpp2_port_pcpu, tx_done_timer); 3495 dev = port_pcpu->dev; 3496 3497 if (!netif_running(dev)) 3498 return HRTIMER_NORESTART; 3499 3500 port_pcpu->timer_scheduled = false; 3501 port = netdev_priv(dev); 3502 3503 /* Process all the Tx queues */ 3504 cause = (1 << port->ntxqs) - 1; 3505 tx_todo = mvpp2_tx_done(port, cause, 3506 mvpp2_cpu_to_thread(port->priv, smp_processor_id())); 3507 3508 /* Set the timer in case not all the packets were processed */ 3509 if (tx_todo && !port_pcpu->timer_scheduled) { 3510 port_pcpu->timer_scheduled = true; 3511 hrtimer_forward_now(&port_pcpu->tx_done_timer, 3512 MVPP2_TXDONE_HRTIMER_PERIOD_NS); 3513 3514 return HRTIMER_RESTART; 3515 } 3516 return HRTIMER_NORESTART; 3517 } 3518 3519 /* Main RX/TX processing routines */ 3520 3521 /* Display more error info */ 3522 static void mvpp2_rx_error(struct mvpp2_port *port, 3523 struct mvpp2_rx_desc *rx_desc) 3524 { 3525 u32 status = mvpp2_rxdesc_status_get(port, rx_desc); 3526 size_t sz = mvpp2_rxdesc_size_get(port, rx_desc); 3527 char *err_str = NULL; 3528 3529 switch (status & MVPP2_RXD_ERR_CODE_MASK) { 3530 case MVPP2_RXD_ERR_CRC: 3531 err_str = "crc"; 3532 break; 3533 case MVPP2_RXD_ERR_OVERRUN: 3534 err_str = "overrun"; 3535 break; 3536 case MVPP2_RXD_ERR_RESOURCE: 3537 err_str = "resource"; 3538 break; 3539 } 3540 if (err_str && net_ratelimit()) 3541 netdev_err(port->dev, 3542 "bad rx status %08x (%s error), size=%zu\n", 3543 status, err_str, sz); 3544 } 3545 3546 /* Handle RX checksum offload */ 3547 static int mvpp2_rx_csum(struct mvpp2_port *port, u32 status) 3548 { 3549 if (((status & MVPP2_RXD_L3_IP4) && 3550 !(status & MVPP2_RXD_IP4_HEADER_ERR)) || 3551 (status & MVPP2_RXD_L3_IP6)) 3552 if (((status & MVPP2_RXD_L4_UDP) || 3553 (status & MVPP2_RXD_L4_TCP)) && 3554 (status & MVPP2_RXD_L4_CSUM_OK)) 3555 return CHECKSUM_UNNECESSARY; 3556 3557 return CHECKSUM_NONE; 3558 } 3559 3560 /* Allocate a new skb and add it to BM pool */ 3561 static int mvpp2_rx_refill(struct mvpp2_port *port, 3562 struct mvpp2_bm_pool *bm_pool, 3563 struct page_pool *page_pool, int pool) 3564 { 3565 dma_addr_t dma_addr; 3566 phys_addr_t phys_addr; 3567 void *buf; 3568 3569 buf = mvpp2_buf_alloc(port, bm_pool, page_pool, 3570 &dma_addr, &phys_addr, GFP_ATOMIC); 3571 if (!buf) 3572 return -ENOMEM; 3573 3574 mvpp2_bm_pool_put(port, pool, dma_addr, phys_addr); 3575 3576 return 0; 3577 } 3578 3579 /* Handle tx checksum */ 3580 static u32 mvpp2_skb_tx_csum(struct mvpp2_port *port, struct sk_buff *skb) 3581 { 3582 if (skb->ip_summed == CHECKSUM_PARTIAL) { 3583 int ip_hdr_len = 0; 3584 u8 l4_proto; 3585 __be16 l3_proto = vlan_get_protocol(skb); 3586 3587 if (l3_proto == htons(ETH_P_IP)) { 3588 struct iphdr *ip4h = ip_hdr(skb); 3589 3590 /* Calculate IPv4 checksum and L4 checksum */ 3591 ip_hdr_len = ip4h->ihl; 3592 l4_proto = ip4h->protocol; 3593 } else if (l3_proto == htons(ETH_P_IPV6)) { 3594 struct ipv6hdr *ip6h = ipv6_hdr(skb); 3595 3596 /* Read l4_protocol from one of IPv6 extra headers */ 3597 if (skb_network_header_len(skb) > 0) 3598 ip_hdr_len = (skb_network_header_len(skb) >> 2); 3599 l4_proto = ip6h->nexthdr; 3600 } else { 3601 return MVPP2_TXD_L4_CSUM_NOT; 3602 } 3603 3604 return mvpp2_txq_desc_csum(skb_network_offset(skb), 3605 l3_proto, ip_hdr_len, l4_proto); 3606 } 3607 3608 return MVPP2_TXD_L4_CSUM_NOT | MVPP2_TXD_IP_CSUM_DISABLE; 3609 } 3610 3611 static void mvpp2_xdp_finish_tx(struct mvpp2_port *port, u16 txq_id, int nxmit, int nxmit_byte) 3612 { 3613 unsigned int thread = mvpp2_cpu_to_thread(port->priv, smp_processor_id()); 3614 struct mvpp2_tx_queue *aggr_txq; 3615 struct mvpp2_txq_pcpu *txq_pcpu; 3616 struct mvpp2_tx_queue *txq; 3617 struct netdev_queue *nq; 3618 3619 txq = port->txqs[txq_id]; 3620 txq_pcpu = per_cpu_ptr(txq->pcpu, thread); 3621 nq = netdev_get_tx_queue(port->dev, txq_id); 3622 aggr_txq = &port->priv->aggr_txqs[thread]; 3623 3624 txq_pcpu->reserved_num -= nxmit; 3625 txq_pcpu->count += nxmit; 3626 aggr_txq->count += nxmit; 3627 3628 /* Enable transmit */ 3629 wmb(); 3630 mvpp2_aggr_txq_pend_desc_add(port, nxmit); 3631 3632 if (txq_pcpu->count >= txq_pcpu->stop_threshold) 3633 netif_tx_stop_queue(nq); 3634 3635 /* Finalize TX processing */ 3636 if (!port->has_tx_irqs && txq_pcpu->count >= txq->done_pkts_coal) 3637 mvpp2_txq_done(port, txq, txq_pcpu); 3638 } 3639 3640 static int 3641 mvpp2_xdp_submit_frame(struct mvpp2_port *port, u16 txq_id, 3642 struct xdp_frame *xdpf, bool dma_map) 3643 { 3644 unsigned int thread = mvpp2_cpu_to_thread(port->priv, smp_processor_id()); 3645 u32 tx_cmd = MVPP2_TXD_L4_CSUM_NOT | MVPP2_TXD_IP_CSUM_DISABLE | 3646 MVPP2_TXD_F_DESC | MVPP2_TXD_L_DESC; 3647 enum mvpp2_tx_buf_type buf_type; 3648 struct mvpp2_txq_pcpu *txq_pcpu; 3649 struct mvpp2_tx_queue *aggr_txq; 3650 struct mvpp2_tx_desc *tx_desc; 3651 struct mvpp2_tx_queue *txq; 3652 int ret = MVPP2_XDP_TX; 3653 dma_addr_t dma_addr; 3654 3655 txq = port->txqs[txq_id]; 3656 txq_pcpu = per_cpu_ptr(txq->pcpu, thread); 3657 aggr_txq = &port->priv->aggr_txqs[thread]; 3658 3659 /* Check number of available descriptors */ 3660 if (mvpp2_aggr_desc_num_check(port, aggr_txq, 1) || 3661 mvpp2_txq_reserved_desc_num_proc(port, txq, txq_pcpu, 1)) { 3662 ret = MVPP2_XDP_DROPPED; 3663 goto out; 3664 } 3665 3666 /* Get a descriptor for the first part of the packet */ 3667 tx_desc = mvpp2_txq_next_desc_get(aggr_txq); 3668 mvpp2_txdesc_txq_set(port, tx_desc, txq->id); 3669 mvpp2_txdesc_size_set(port, tx_desc, xdpf->len); 3670 3671 if (dma_map) { 3672 /* XDP_REDIRECT or AF_XDP */ 3673 dma_addr = dma_map_single(port->dev->dev.parent, xdpf->data, 3674 xdpf->len, DMA_TO_DEVICE); 3675 3676 if (unlikely(dma_mapping_error(port->dev->dev.parent, dma_addr))) { 3677 mvpp2_txq_desc_put(txq); 3678 ret = MVPP2_XDP_DROPPED; 3679 goto out; 3680 } 3681 3682 buf_type = MVPP2_TYPE_XDP_NDO; 3683 } else { 3684 /* XDP_TX */ 3685 struct page *page = virt_to_page(xdpf->data); 3686 3687 dma_addr = page_pool_get_dma_addr(page) + 3688 sizeof(*xdpf) + xdpf->headroom; 3689 dma_sync_single_for_device(port->dev->dev.parent, dma_addr, 3690 xdpf->len, DMA_BIDIRECTIONAL); 3691 3692 buf_type = MVPP2_TYPE_XDP_TX; 3693 } 3694 3695 mvpp2_txdesc_dma_addr_set(port, tx_desc, dma_addr); 3696 3697 mvpp2_txdesc_cmd_set(port, tx_desc, tx_cmd); 3698 mvpp2_txq_inc_put(port, txq_pcpu, xdpf, tx_desc, buf_type); 3699 3700 out: 3701 return ret; 3702 } 3703 3704 static int 3705 mvpp2_xdp_xmit_back(struct mvpp2_port *port, struct xdp_buff *xdp) 3706 { 3707 struct mvpp2_pcpu_stats *stats = this_cpu_ptr(port->stats); 3708 struct xdp_frame *xdpf; 3709 u16 txq_id; 3710 int ret; 3711 3712 xdpf = xdp_convert_buff_to_frame(xdp); 3713 if (unlikely(!xdpf)) 3714 return MVPP2_XDP_DROPPED; 3715 3716 /* The first of the TX queues are used for XPS, 3717 * the second half for XDP_TX 3718 */ 3719 txq_id = mvpp2_cpu_to_thread(port->priv, smp_processor_id()) + (port->ntxqs / 2); 3720 3721 ret = mvpp2_xdp_submit_frame(port, txq_id, xdpf, false); 3722 if (ret == MVPP2_XDP_TX) { 3723 u64_stats_update_begin(&stats->syncp); 3724 stats->tx_bytes += xdpf->len; 3725 stats->tx_packets++; 3726 stats->xdp_tx++; 3727 u64_stats_update_end(&stats->syncp); 3728 3729 mvpp2_xdp_finish_tx(port, txq_id, 1, xdpf->len); 3730 } else { 3731 u64_stats_update_begin(&stats->syncp); 3732 stats->xdp_tx_err++; 3733 u64_stats_update_end(&stats->syncp); 3734 } 3735 3736 return ret; 3737 } 3738 3739 static int 3740 mvpp2_xdp_xmit(struct net_device *dev, int num_frame, 3741 struct xdp_frame **frames, u32 flags) 3742 { 3743 struct mvpp2_port *port = netdev_priv(dev); 3744 int i, nxmit_byte = 0, nxmit = 0; 3745 struct mvpp2_pcpu_stats *stats; 3746 u16 txq_id; 3747 u32 ret; 3748 3749 if (unlikely(test_bit(0, &port->state))) 3750 return -ENETDOWN; 3751 3752 if (unlikely(flags & ~XDP_XMIT_FLAGS_MASK)) 3753 return -EINVAL; 3754 3755 /* The first of the TX queues are used for XPS, 3756 * the second half for XDP_TX 3757 */ 3758 txq_id = mvpp2_cpu_to_thread(port->priv, smp_processor_id()) + (port->ntxqs / 2); 3759 3760 for (i = 0; i < num_frame; i++) { 3761 ret = mvpp2_xdp_submit_frame(port, txq_id, frames[i], true); 3762 if (ret != MVPP2_XDP_TX) 3763 break; 3764 3765 nxmit_byte += frames[i]->len; 3766 nxmit++; 3767 } 3768 3769 if (likely(nxmit > 0)) 3770 mvpp2_xdp_finish_tx(port, txq_id, nxmit, nxmit_byte); 3771 3772 stats = this_cpu_ptr(port->stats); 3773 u64_stats_update_begin(&stats->syncp); 3774 stats->tx_bytes += nxmit_byte; 3775 stats->tx_packets += nxmit; 3776 stats->xdp_xmit += nxmit; 3777 stats->xdp_xmit_err += num_frame - nxmit; 3778 u64_stats_update_end(&stats->syncp); 3779 3780 return nxmit; 3781 } 3782 3783 static int 3784 mvpp2_run_xdp(struct mvpp2_port *port, struct bpf_prog *prog, 3785 struct xdp_buff *xdp, struct page_pool *pp, 3786 struct mvpp2_pcpu_stats *stats) 3787 { 3788 unsigned int len, sync, err; 3789 struct page *page; 3790 u32 ret, act; 3791 3792 len = xdp->data_end - xdp->data_hard_start - MVPP2_SKB_HEADROOM; 3793 act = bpf_prog_run_xdp(prog, xdp); 3794 3795 /* Due xdp_adjust_tail: DMA sync for_device cover max len CPU touch */ 3796 sync = xdp->data_end - xdp->data_hard_start - MVPP2_SKB_HEADROOM; 3797 sync = max(sync, len); 3798 3799 switch (act) { 3800 case XDP_PASS: 3801 stats->xdp_pass++; 3802 ret = MVPP2_XDP_PASS; 3803 break; 3804 case XDP_REDIRECT: 3805 err = xdp_do_redirect(port->dev, xdp, prog); 3806 if (unlikely(err)) { 3807 ret = MVPP2_XDP_DROPPED; 3808 page = virt_to_head_page(xdp->data); 3809 page_pool_put_page(pp, page, sync, true); 3810 } else { 3811 ret = MVPP2_XDP_REDIR; 3812 stats->xdp_redirect++; 3813 } 3814 break; 3815 case XDP_TX: 3816 ret = mvpp2_xdp_xmit_back(port, xdp); 3817 if (ret != MVPP2_XDP_TX) { 3818 page = virt_to_head_page(xdp->data); 3819 page_pool_put_page(pp, page, sync, true); 3820 } 3821 break; 3822 default: 3823 bpf_warn_invalid_xdp_action(act); 3824 fallthrough; 3825 case XDP_ABORTED: 3826 trace_xdp_exception(port->dev, prog, act); 3827 fallthrough; 3828 case XDP_DROP: 3829 page = virt_to_head_page(xdp->data); 3830 page_pool_put_page(pp, page, sync, true); 3831 ret = MVPP2_XDP_DROPPED; 3832 stats->xdp_drop++; 3833 break; 3834 } 3835 3836 return ret; 3837 } 3838 3839 static void mvpp2_buff_hdr_pool_put(struct mvpp2_port *port, struct mvpp2_rx_desc *rx_desc, 3840 int pool, u32 rx_status) 3841 { 3842 phys_addr_t phys_addr, phys_addr_next; 3843 dma_addr_t dma_addr, dma_addr_next; 3844 struct mvpp2_buff_hdr *buff_hdr; 3845 3846 phys_addr = mvpp2_rxdesc_dma_addr_get(port, rx_desc); 3847 dma_addr = mvpp2_rxdesc_cookie_get(port, rx_desc); 3848 3849 do { 3850 buff_hdr = (struct mvpp2_buff_hdr *)phys_to_virt(phys_addr); 3851 3852 phys_addr_next = le32_to_cpu(buff_hdr->next_phys_addr); 3853 dma_addr_next = le32_to_cpu(buff_hdr->next_dma_addr); 3854 3855 if (port->priv->hw_version >= MVPP22) { 3856 phys_addr_next |= ((u64)buff_hdr->next_phys_addr_high << 32); 3857 dma_addr_next |= ((u64)buff_hdr->next_dma_addr_high << 32); 3858 } 3859 3860 mvpp2_bm_pool_put(port, pool, dma_addr, phys_addr); 3861 3862 phys_addr = phys_addr_next; 3863 dma_addr = dma_addr_next; 3864 3865 } while (!MVPP2_B_HDR_INFO_IS_LAST(le16_to_cpu(buff_hdr->info))); 3866 } 3867 3868 /* Main rx processing */ 3869 static int mvpp2_rx(struct mvpp2_port *port, struct napi_struct *napi, 3870 int rx_todo, struct mvpp2_rx_queue *rxq) 3871 { 3872 struct net_device *dev = port->dev; 3873 struct mvpp2_pcpu_stats ps = {}; 3874 enum dma_data_direction dma_dir; 3875 struct bpf_prog *xdp_prog; 3876 struct xdp_buff xdp; 3877 int rx_received; 3878 int rx_done = 0; 3879 u32 xdp_ret = 0; 3880 3881 xdp_prog = READ_ONCE(port->xdp_prog); 3882 3883 /* Get number of received packets and clamp the to-do */ 3884 rx_received = mvpp2_rxq_received(port, rxq->id); 3885 if (rx_todo > rx_received) 3886 rx_todo = rx_received; 3887 3888 while (rx_done < rx_todo) { 3889 struct mvpp2_rx_desc *rx_desc = mvpp2_rxq_next_desc_get(rxq); 3890 struct mvpp2_bm_pool *bm_pool; 3891 struct page_pool *pp = NULL; 3892 struct sk_buff *skb; 3893 unsigned int frag_size; 3894 dma_addr_t dma_addr; 3895 phys_addr_t phys_addr; 3896 u32 rx_status, timestamp; 3897 int pool, rx_bytes, err, ret; 3898 struct page *page; 3899 void *data; 3900 3901 phys_addr = mvpp2_rxdesc_cookie_get(port, rx_desc); 3902 data = (void *)phys_to_virt(phys_addr); 3903 page = virt_to_page(data); 3904 prefetch(page); 3905 3906 rx_done++; 3907 rx_status = mvpp2_rxdesc_status_get(port, rx_desc); 3908 rx_bytes = mvpp2_rxdesc_size_get(port, rx_desc); 3909 rx_bytes -= MVPP2_MH_SIZE; 3910 dma_addr = mvpp2_rxdesc_dma_addr_get(port, rx_desc); 3911 3912 pool = (rx_status & MVPP2_RXD_BM_POOL_ID_MASK) >> 3913 MVPP2_RXD_BM_POOL_ID_OFFS; 3914 bm_pool = &port->priv->bm_pools[pool]; 3915 3916 if (port->priv->percpu_pools) { 3917 pp = port->priv->page_pool[pool]; 3918 dma_dir = page_pool_get_dma_dir(pp); 3919 } else { 3920 dma_dir = DMA_FROM_DEVICE; 3921 } 3922 3923 dma_sync_single_for_cpu(dev->dev.parent, dma_addr, 3924 rx_bytes + MVPP2_MH_SIZE, 3925 dma_dir); 3926 3927 /* Buffer header not supported */ 3928 if (rx_status & MVPP2_RXD_BUF_HDR) 3929 goto err_drop_frame; 3930 3931 /* In case of an error, release the requested buffer pointer 3932 * to the Buffer Manager. This request process is controlled 3933 * by the hardware, and the information about the buffer is 3934 * comprised by the RX descriptor. 3935 */ 3936 if (rx_status & MVPP2_RXD_ERR_SUMMARY) 3937 goto err_drop_frame; 3938 3939 /* Prefetch header */ 3940 prefetch(data + MVPP2_MH_SIZE + MVPP2_SKB_HEADROOM); 3941 3942 if (bm_pool->frag_size > PAGE_SIZE) 3943 frag_size = 0; 3944 else 3945 frag_size = bm_pool->frag_size; 3946 3947 if (xdp_prog) { 3948 struct xdp_rxq_info *xdp_rxq; 3949 3950 if (bm_pool->pkt_size == MVPP2_BM_SHORT_PKT_SIZE) 3951 xdp_rxq = &rxq->xdp_rxq_short; 3952 else 3953 xdp_rxq = &rxq->xdp_rxq_long; 3954 3955 xdp_init_buff(&xdp, PAGE_SIZE, xdp_rxq); 3956 xdp_prepare_buff(&xdp, data, 3957 MVPP2_MH_SIZE + MVPP2_SKB_HEADROOM, 3958 rx_bytes, false); 3959 3960 ret = mvpp2_run_xdp(port, xdp_prog, &xdp, pp, &ps); 3961 3962 if (ret) { 3963 xdp_ret |= ret; 3964 err = mvpp2_rx_refill(port, bm_pool, pp, pool); 3965 if (err) { 3966 netdev_err(port->dev, "failed to refill BM pools\n"); 3967 goto err_drop_frame; 3968 } 3969 3970 ps.rx_packets++; 3971 ps.rx_bytes += rx_bytes; 3972 continue; 3973 } 3974 } 3975 3976 skb = build_skb(data, frag_size); 3977 if (!skb) { 3978 netdev_warn(port->dev, "skb build failed\n"); 3979 goto err_drop_frame; 3980 } 3981 3982 /* If we have RX hardware timestamping enabled, grab the 3983 * timestamp from the queue and convert. 3984 */ 3985 if (mvpp22_rx_hwtstamping(port)) { 3986 timestamp = le32_to_cpu(rx_desc->pp22.timestamp); 3987 mvpp22_tai_tstamp(port->priv->tai, timestamp, 3988 skb_hwtstamps(skb)); 3989 } 3990 3991 err = mvpp2_rx_refill(port, bm_pool, pp, pool); 3992 if (err) { 3993 netdev_err(port->dev, "failed to refill BM pools\n"); 3994 dev_kfree_skb_any(skb); 3995 goto err_drop_frame; 3996 } 3997 3998 if (pp) 3999 skb_mark_for_recycle(skb); 4000 else 4001 dma_unmap_single_attrs(dev->dev.parent, dma_addr, 4002 bm_pool->buf_size, DMA_FROM_DEVICE, 4003 DMA_ATTR_SKIP_CPU_SYNC); 4004 4005 ps.rx_packets++; 4006 ps.rx_bytes += rx_bytes; 4007 4008 skb_reserve(skb, MVPP2_MH_SIZE + MVPP2_SKB_HEADROOM); 4009 skb_put(skb, rx_bytes); 4010 skb->ip_summed = mvpp2_rx_csum(port, rx_status); 4011 skb->protocol = eth_type_trans(skb, dev); 4012 4013 napi_gro_receive(napi, skb); 4014 continue; 4015 4016 err_drop_frame: 4017 dev->stats.rx_errors++; 4018 mvpp2_rx_error(port, rx_desc); 4019 /* Return the buffer to the pool */ 4020 if (rx_status & MVPP2_RXD_BUF_HDR) 4021 mvpp2_buff_hdr_pool_put(port, rx_desc, pool, rx_status); 4022 else 4023 mvpp2_bm_pool_put(port, pool, dma_addr, phys_addr); 4024 } 4025 4026 if (xdp_ret & MVPP2_XDP_REDIR) 4027 xdp_do_flush_map(); 4028 4029 if (ps.rx_packets) { 4030 struct mvpp2_pcpu_stats *stats = this_cpu_ptr(port->stats); 4031 4032 u64_stats_update_begin(&stats->syncp); 4033 stats->rx_packets += ps.rx_packets; 4034 stats->rx_bytes += ps.rx_bytes; 4035 /* xdp */ 4036 stats->xdp_redirect += ps.xdp_redirect; 4037 stats->xdp_pass += ps.xdp_pass; 4038 stats->xdp_drop += ps.xdp_drop; 4039 u64_stats_update_end(&stats->syncp); 4040 } 4041 4042 /* Update Rx queue management counters */ 4043 wmb(); 4044 mvpp2_rxq_status_update(port, rxq->id, rx_done, rx_done); 4045 4046 return rx_todo; 4047 } 4048 4049 static inline void 4050 tx_desc_unmap_put(struct mvpp2_port *port, struct mvpp2_tx_queue *txq, 4051 struct mvpp2_tx_desc *desc) 4052 { 4053 unsigned int thread = mvpp2_cpu_to_thread(port->priv, smp_processor_id()); 4054 struct mvpp2_txq_pcpu *txq_pcpu = per_cpu_ptr(txq->pcpu, thread); 4055 4056 dma_addr_t buf_dma_addr = 4057 mvpp2_txdesc_dma_addr_get(port, desc); 4058 size_t buf_sz = 4059 mvpp2_txdesc_size_get(port, desc); 4060 if (!IS_TSO_HEADER(txq_pcpu, buf_dma_addr)) 4061 dma_unmap_single(port->dev->dev.parent, buf_dma_addr, 4062 buf_sz, DMA_TO_DEVICE); 4063 mvpp2_txq_desc_put(txq); 4064 } 4065 4066 static void mvpp2_txdesc_clear_ptp(struct mvpp2_port *port, 4067 struct mvpp2_tx_desc *desc) 4068 { 4069 /* We only need to clear the low bits */ 4070 if (port->priv->hw_version >= MVPP22) 4071 desc->pp22.ptp_descriptor &= 4072 cpu_to_le32(~MVPP22_PTP_DESC_MASK_LOW); 4073 } 4074 4075 static bool mvpp2_tx_hw_tstamp(struct mvpp2_port *port, 4076 struct mvpp2_tx_desc *tx_desc, 4077 struct sk_buff *skb) 4078 { 4079 struct mvpp2_hwtstamp_queue *queue; 4080 unsigned int mtype, type, i; 4081 struct ptp_header *hdr; 4082 u64 ptpdesc; 4083 4084 if (port->priv->hw_version == MVPP21 || 4085 port->tx_hwtstamp_type == HWTSTAMP_TX_OFF) 4086 return false; 4087 4088 type = ptp_classify_raw(skb); 4089 if (!type) 4090 return false; 4091 4092 hdr = ptp_parse_header(skb, type); 4093 if (!hdr) 4094 return false; 4095 4096 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 4097 4098 ptpdesc = MVPP22_PTP_MACTIMESTAMPINGEN | 4099 MVPP22_PTP_ACTION_CAPTURE; 4100 queue = &port->tx_hwtstamp_queue[0]; 4101 4102 switch (type & PTP_CLASS_VMASK) { 4103 case PTP_CLASS_V1: 4104 ptpdesc |= MVPP22_PTP_PACKETFORMAT(MVPP22_PTP_PKT_FMT_PTPV1); 4105 break; 4106 4107 case PTP_CLASS_V2: 4108 ptpdesc |= MVPP22_PTP_PACKETFORMAT(MVPP22_PTP_PKT_FMT_PTPV2); 4109 mtype = hdr->tsmt & 15; 4110 /* Direct PTP Sync messages to queue 1 */ 4111 if (mtype == 0) { 4112 ptpdesc |= MVPP22_PTP_TIMESTAMPQUEUESELECT; 4113 queue = &port->tx_hwtstamp_queue[1]; 4114 } 4115 break; 4116 } 4117 4118 /* Take a reference on the skb and insert into our queue */ 4119 i = queue->next; 4120 queue->next = (i + 1) & 31; 4121 if (queue->skb[i]) 4122 dev_kfree_skb_any(queue->skb[i]); 4123 queue->skb[i] = skb_get(skb); 4124 4125 ptpdesc |= MVPP22_PTP_TIMESTAMPENTRYID(i); 4126 4127 /* 4128 * 3:0 - PTPAction 4129 * 6:4 - PTPPacketFormat 4130 * 7 - PTP_CF_WraparoundCheckEn 4131 * 9:8 - IngressTimestampSeconds[1:0] 4132 * 10 - Reserved 4133 * 11 - MACTimestampingEn 4134 * 17:12 - PTP_TimestampQueueEntryID[5:0] 4135 * 18 - PTPTimestampQueueSelect 4136 * 19 - UDPChecksumUpdateEn 4137 * 27:20 - TimestampOffset 4138 * PTP, NTPTransmit, OWAMP/TWAMP - L3 to PTP header 4139 * NTPTs, Y.1731 - L3 to timestamp entry 4140 * 35:28 - UDP Checksum Offset 4141 * 4142 * stored in tx descriptor bits 75:64 (11:0) and 191:168 (35:12) 4143 */ 4144 tx_desc->pp22.ptp_descriptor &= 4145 cpu_to_le32(~MVPP22_PTP_DESC_MASK_LOW); 4146 tx_desc->pp22.ptp_descriptor |= 4147 cpu_to_le32(ptpdesc & MVPP22_PTP_DESC_MASK_LOW); 4148 tx_desc->pp22.buf_dma_addr_ptp &= cpu_to_le64(~0xffffff0000000000ULL); 4149 tx_desc->pp22.buf_dma_addr_ptp |= cpu_to_le64((ptpdesc >> 12) << 40); 4150 4151 return true; 4152 } 4153 4154 /* Handle tx fragmentation processing */ 4155 static int mvpp2_tx_frag_process(struct mvpp2_port *port, struct sk_buff *skb, 4156 struct mvpp2_tx_queue *aggr_txq, 4157 struct mvpp2_tx_queue *txq) 4158 { 4159 unsigned int thread = mvpp2_cpu_to_thread(port->priv, smp_processor_id()); 4160 struct mvpp2_txq_pcpu *txq_pcpu = per_cpu_ptr(txq->pcpu, thread); 4161 struct mvpp2_tx_desc *tx_desc; 4162 int i; 4163 dma_addr_t buf_dma_addr; 4164 4165 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { 4166 skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 4167 void *addr = skb_frag_address(frag); 4168 4169 tx_desc = mvpp2_txq_next_desc_get(aggr_txq); 4170 mvpp2_txdesc_clear_ptp(port, tx_desc); 4171 mvpp2_txdesc_txq_set(port, tx_desc, txq->id); 4172 mvpp2_txdesc_size_set(port, tx_desc, skb_frag_size(frag)); 4173 4174 buf_dma_addr = dma_map_single(port->dev->dev.parent, addr, 4175 skb_frag_size(frag), 4176 DMA_TO_DEVICE); 4177 if (dma_mapping_error(port->dev->dev.parent, buf_dma_addr)) { 4178 mvpp2_txq_desc_put(txq); 4179 goto cleanup; 4180 } 4181 4182 mvpp2_txdesc_dma_addr_set(port, tx_desc, buf_dma_addr); 4183 4184 if (i == (skb_shinfo(skb)->nr_frags - 1)) { 4185 /* Last descriptor */ 4186 mvpp2_txdesc_cmd_set(port, tx_desc, 4187 MVPP2_TXD_L_DESC); 4188 mvpp2_txq_inc_put(port, txq_pcpu, skb, tx_desc, MVPP2_TYPE_SKB); 4189 } else { 4190 /* Descriptor in the middle: Not First, Not Last */ 4191 mvpp2_txdesc_cmd_set(port, tx_desc, 0); 4192 mvpp2_txq_inc_put(port, txq_pcpu, NULL, tx_desc, MVPP2_TYPE_SKB); 4193 } 4194 } 4195 4196 return 0; 4197 cleanup: 4198 /* Release all descriptors that were used to map fragments of 4199 * this packet, as well as the corresponding DMA mappings 4200 */ 4201 for (i = i - 1; i >= 0; i--) { 4202 tx_desc = txq->descs + i; 4203 tx_desc_unmap_put(port, txq, tx_desc); 4204 } 4205 4206 return -ENOMEM; 4207 } 4208 4209 static inline void mvpp2_tso_put_hdr(struct sk_buff *skb, 4210 struct net_device *dev, 4211 struct mvpp2_tx_queue *txq, 4212 struct mvpp2_tx_queue *aggr_txq, 4213 struct mvpp2_txq_pcpu *txq_pcpu, 4214 int hdr_sz) 4215 { 4216 struct mvpp2_port *port = netdev_priv(dev); 4217 struct mvpp2_tx_desc *tx_desc = mvpp2_txq_next_desc_get(aggr_txq); 4218 dma_addr_t addr; 4219 4220 mvpp2_txdesc_clear_ptp(port, tx_desc); 4221 mvpp2_txdesc_txq_set(port, tx_desc, txq->id); 4222 mvpp2_txdesc_size_set(port, tx_desc, hdr_sz); 4223 4224 addr = txq_pcpu->tso_headers_dma + 4225 txq_pcpu->txq_put_index * TSO_HEADER_SIZE; 4226 mvpp2_txdesc_dma_addr_set(port, tx_desc, addr); 4227 4228 mvpp2_txdesc_cmd_set(port, tx_desc, mvpp2_skb_tx_csum(port, skb) | 4229 MVPP2_TXD_F_DESC | 4230 MVPP2_TXD_PADDING_DISABLE); 4231 mvpp2_txq_inc_put(port, txq_pcpu, NULL, tx_desc, MVPP2_TYPE_SKB); 4232 } 4233 4234 static inline int mvpp2_tso_put_data(struct sk_buff *skb, 4235 struct net_device *dev, struct tso_t *tso, 4236 struct mvpp2_tx_queue *txq, 4237 struct mvpp2_tx_queue *aggr_txq, 4238 struct mvpp2_txq_pcpu *txq_pcpu, 4239 int sz, bool left, bool last) 4240 { 4241 struct mvpp2_port *port = netdev_priv(dev); 4242 struct mvpp2_tx_desc *tx_desc = mvpp2_txq_next_desc_get(aggr_txq); 4243 dma_addr_t buf_dma_addr; 4244 4245 mvpp2_txdesc_clear_ptp(port, tx_desc); 4246 mvpp2_txdesc_txq_set(port, tx_desc, txq->id); 4247 mvpp2_txdesc_size_set(port, tx_desc, sz); 4248 4249 buf_dma_addr = dma_map_single(dev->dev.parent, tso->data, sz, 4250 DMA_TO_DEVICE); 4251 if (unlikely(dma_mapping_error(dev->dev.parent, buf_dma_addr))) { 4252 mvpp2_txq_desc_put(txq); 4253 return -ENOMEM; 4254 } 4255 4256 mvpp2_txdesc_dma_addr_set(port, tx_desc, buf_dma_addr); 4257 4258 if (!left) { 4259 mvpp2_txdesc_cmd_set(port, tx_desc, MVPP2_TXD_L_DESC); 4260 if (last) { 4261 mvpp2_txq_inc_put(port, txq_pcpu, skb, tx_desc, MVPP2_TYPE_SKB); 4262 return 0; 4263 } 4264 } else { 4265 mvpp2_txdesc_cmd_set(port, tx_desc, 0); 4266 } 4267 4268 mvpp2_txq_inc_put(port, txq_pcpu, NULL, tx_desc, MVPP2_TYPE_SKB); 4269 return 0; 4270 } 4271 4272 static int mvpp2_tx_tso(struct sk_buff *skb, struct net_device *dev, 4273 struct mvpp2_tx_queue *txq, 4274 struct mvpp2_tx_queue *aggr_txq, 4275 struct mvpp2_txq_pcpu *txq_pcpu) 4276 { 4277 struct mvpp2_port *port = netdev_priv(dev); 4278 int hdr_sz, i, len, descs = 0; 4279 struct tso_t tso; 4280 4281 /* Check number of available descriptors */ 4282 if (mvpp2_aggr_desc_num_check(port, aggr_txq, tso_count_descs(skb)) || 4283 mvpp2_txq_reserved_desc_num_proc(port, txq, txq_pcpu, 4284 tso_count_descs(skb))) 4285 return 0; 4286 4287 hdr_sz = tso_start(skb, &tso); 4288 4289 len = skb->len - hdr_sz; 4290 while (len > 0) { 4291 int left = min_t(int, skb_shinfo(skb)->gso_size, len); 4292 char *hdr = txq_pcpu->tso_headers + 4293 txq_pcpu->txq_put_index * TSO_HEADER_SIZE; 4294 4295 len -= left; 4296 descs++; 4297 4298 tso_build_hdr(skb, hdr, &tso, left, len == 0); 4299 mvpp2_tso_put_hdr(skb, dev, txq, aggr_txq, txq_pcpu, hdr_sz); 4300 4301 while (left > 0) { 4302 int sz = min_t(int, tso.size, left); 4303 left -= sz; 4304 descs++; 4305 4306 if (mvpp2_tso_put_data(skb, dev, &tso, txq, aggr_txq, 4307 txq_pcpu, sz, left, len == 0)) 4308 goto release; 4309 tso_build_data(skb, &tso, sz); 4310 } 4311 } 4312 4313 return descs; 4314 4315 release: 4316 for (i = descs - 1; i >= 0; i--) { 4317 struct mvpp2_tx_desc *tx_desc = txq->descs + i; 4318 tx_desc_unmap_put(port, txq, tx_desc); 4319 } 4320 return 0; 4321 } 4322 4323 /* Main tx processing */ 4324 static netdev_tx_t mvpp2_tx(struct sk_buff *skb, struct net_device *dev) 4325 { 4326 struct mvpp2_port *port = netdev_priv(dev); 4327 struct mvpp2_tx_queue *txq, *aggr_txq; 4328 struct mvpp2_txq_pcpu *txq_pcpu; 4329 struct mvpp2_tx_desc *tx_desc; 4330 dma_addr_t buf_dma_addr; 4331 unsigned long flags = 0; 4332 unsigned int thread; 4333 int frags = 0; 4334 u16 txq_id; 4335 u32 tx_cmd; 4336 4337 thread = mvpp2_cpu_to_thread(port->priv, smp_processor_id()); 4338 4339 txq_id = skb_get_queue_mapping(skb); 4340 txq = port->txqs[txq_id]; 4341 txq_pcpu = per_cpu_ptr(txq->pcpu, thread); 4342 aggr_txq = &port->priv->aggr_txqs[thread]; 4343 4344 if (test_bit(thread, &port->priv->lock_map)) 4345 spin_lock_irqsave(&port->tx_lock[thread], flags); 4346 4347 if (skb_is_gso(skb)) { 4348 frags = mvpp2_tx_tso(skb, dev, txq, aggr_txq, txq_pcpu); 4349 goto out; 4350 } 4351 frags = skb_shinfo(skb)->nr_frags + 1; 4352 4353 /* Check number of available descriptors */ 4354 if (mvpp2_aggr_desc_num_check(port, aggr_txq, frags) || 4355 mvpp2_txq_reserved_desc_num_proc(port, txq, txq_pcpu, frags)) { 4356 frags = 0; 4357 goto out; 4358 } 4359 4360 /* Get a descriptor for the first part of the packet */ 4361 tx_desc = mvpp2_txq_next_desc_get(aggr_txq); 4362 if (!(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) || 4363 !mvpp2_tx_hw_tstamp(port, tx_desc, skb)) 4364 mvpp2_txdesc_clear_ptp(port, tx_desc); 4365 mvpp2_txdesc_txq_set(port, tx_desc, txq->id); 4366 mvpp2_txdesc_size_set(port, tx_desc, skb_headlen(skb)); 4367 4368 buf_dma_addr = dma_map_single(dev->dev.parent, skb->data, 4369 skb_headlen(skb), DMA_TO_DEVICE); 4370 if (unlikely(dma_mapping_error(dev->dev.parent, buf_dma_addr))) { 4371 mvpp2_txq_desc_put(txq); 4372 frags = 0; 4373 goto out; 4374 } 4375 4376 mvpp2_txdesc_dma_addr_set(port, tx_desc, buf_dma_addr); 4377 4378 tx_cmd = mvpp2_skb_tx_csum(port, skb); 4379 4380 if (frags == 1) { 4381 /* First and Last descriptor */ 4382 tx_cmd |= MVPP2_TXD_F_DESC | MVPP2_TXD_L_DESC; 4383 mvpp2_txdesc_cmd_set(port, tx_desc, tx_cmd); 4384 mvpp2_txq_inc_put(port, txq_pcpu, skb, tx_desc, MVPP2_TYPE_SKB); 4385 } else { 4386 /* First but not Last */ 4387 tx_cmd |= MVPP2_TXD_F_DESC | MVPP2_TXD_PADDING_DISABLE; 4388 mvpp2_txdesc_cmd_set(port, tx_desc, tx_cmd); 4389 mvpp2_txq_inc_put(port, txq_pcpu, NULL, tx_desc, MVPP2_TYPE_SKB); 4390 4391 /* Continue with other skb fragments */ 4392 if (mvpp2_tx_frag_process(port, skb, aggr_txq, txq)) { 4393 tx_desc_unmap_put(port, txq, tx_desc); 4394 frags = 0; 4395 } 4396 } 4397 4398 out: 4399 if (frags > 0) { 4400 struct mvpp2_pcpu_stats *stats = per_cpu_ptr(port->stats, thread); 4401 struct netdev_queue *nq = netdev_get_tx_queue(dev, txq_id); 4402 4403 txq_pcpu->reserved_num -= frags; 4404 txq_pcpu->count += frags; 4405 aggr_txq->count += frags; 4406 4407 /* Enable transmit */ 4408 wmb(); 4409 mvpp2_aggr_txq_pend_desc_add(port, frags); 4410 4411 if (txq_pcpu->count >= txq_pcpu->stop_threshold) 4412 netif_tx_stop_queue(nq); 4413 4414 u64_stats_update_begin(&stats->syncp); 4415 stats->tx_packets++; 4416 stats->tx_bytes += skb->len; 4417 u64_stats_update_end(&stats->syncp); 4418 } else { 4419 dev->stats.tx_dropped++; 4420 dev_kfree_skb_any(skb); 4421 } 4422 4423 /* Finalize TX processing */ 4424 if (!port->has_tx_irqs && txq_pcpu->count >= txq->done_pkts_coal) 4425 mvpp2_txq_done(port, txq, txq_pcpu); 4426 4427 /* Set the timer in case not all frags were processed */ 4428 if (!port->has_tx_irqs && txq_pcpu->count <= frags && 4429 txq_pcpu->count > 0) { 4430 struct mvpp2_port_pcpu *port_pcpu = per_cpu_ptr(port->pcpu, thread); 4431 4432 if (!port_pcpu->timer_scheduled) { 4433 port_pcpu->timer_scheduled = true; 4434 hrtimer_start(&port_pcpu->tx_done_timer, 4435 MVPP2_TXDONE_HRTIMER_PERIOD_NS, 4436 HRTIMER_MODE_REL_PINNED_SOFT); 4437 } 4438 } 4439 4440 if (test_bit(thread, &port->priv->lock_map)) 4441 spin_unlock_irqrestore(&port->tx_lock[thread], flags); 4442 4443 return NETDEV_TX_OK; 4444 } 4445 4446 static inline void mvpp2_cause_error(struct net_device *dev, int cause) 4447 { 4448 if (cause & MVPP2_CAUSE_FCS_ERR_MASK) 4449 netdev_err(dev, "FCS error\n"); 4450 if (cause & MVPP2_CAUSE_RX_FIFO_OVERRUN_MASK) 4451 netdev_err(dev, "rx fifo overrun error\n"); 4452 if (cause & MVPP2_CAUSE_TX_FIFO_UNDERRUN_MASK) 4453 netdev_err(dev, "tx fifo underrun error\n"); 4454 } 4455 4456 static int mvpp2_poll(struct napi_struct *napi, int budget) 4457 { 4458 u32 cause_rx_tx, cause_rx, cause_tx, cause_misc; 4459 int rx_done = 0; 4460 struct mvpp2_port *port = netdev_priv(napi->dev); 4461 struct mvpp2_queue_vector *qv; 4462 unsigned int thread = mvpp2_cpu_to_thread(port->priv, smp_processor_id()); 4463 4464 qv = container_of(napi, struct mvpp2_queue_vector, napi); 4465 4466 /* Rx/Tx cause register 4467 * 4468 * Bits 0-15: each bit indicates received packets on the Rx queue 4469 * (bit 0 is for Rx queue 0). 4470 * 4471 * Bits 16-23: each bit indicates transmitted packets on the Tx queue 4472 * (bit 16 is for Tx queue 0). 4473 * 4474 * Each CPU has its own Rx/Tx cause register 4475 */ 4476 cause_rx_tx = mvpp2_thread_read_relaxed(port->priv, qv->sw_thread_id, 4477 MVPP2_ISR_RX_TX_CAUSE_REG(port->id)); 4478 4479 cause_misc = cause_rx_tx & MVPP2_CAUSE_MISC_SUM_MASK; 4480 if (cause_misc) { 4481 mvpp2_cause_error(port->dev, cause_misc); 4482 4483 /* Clear the cause register */ 4484 mvpp2_write(port->priv, MVPP2_ISR_MISC_CAUSE_REG, 0); 4485 mvpp2_thread_write(port->priv, thread, 4486 MVPP2_ISR_RX_TX_CAUSE_REG(port->id), 4487 cause_rx_tx & ~MVPP2_CAUSE_MISC_SUM_MASK); 4488 } 4489 4490 if (port->has_tx_irqs) { 4491 cause_tx = cause_rx_tx & MVPP2_CAUSE_TXQ_OCCUP_DESC_ALL_MASK; 4492 if (cause_tx) { 4493 cause_tx >>= MVPP2_CAUSE_TXQ_OCCUP_DESC_ALL_OFFSET; 4494 mvpp2_tx_done(port, cause_tx, qv->sw_thread_id); 4495 } 4496 } 4497 4498 /* Process RX packets */ 4499 cause_rx = cause_rx_tx & 4500 MVPP2_CAUSE_RXQ_OCCUP_DESC_ALL_MASK(port->priv->hw_version); 4501 cause_rx <<= qv->first_rxq; 4502 cause_rx |= qv->pending_cause_rx; 4503 while (cause_rx && budget > 0) { 4504 int count; 4505 struct mvpp2_rx_queue *rxq; 4506 4507 rxq = mvpp2_get_rx_queue(port, cause_rx); 4508 if (!rxq) 4509 break; 4510 4511 count = mvpp2_rx(port, napi, budget, rxq); 4512 rx_done += count; 4513 budget -= count; 4514 if (budget > 0) { 4515 /* Clear the bit associated to this Rx queue 4516 * so that next iteration will continue from 4517 * the next Rx queue. 4518 */ 4519 cause_rx &= ~(1 << rxq->logic_rxq); 4520 } 4521 } 4522 4523 if (budget > 0) { 4524 cause_rx = 0; 4525 napi_complete_done(napi, rx_done); 4526 4527 mvpp2_qvec_interrupt_enable(qv); 4528 } 4529 qv->pending_cause_rx = cause_rx; 4530 return rx_done; 4531 } 4532 4533 static void mvpp22_mode_reconfigure(struct mvpp2_port *port, 4534 phy_interface_t interface) 4535 { 4536 u32 ctrl3; 4537 4538 /* Set the GMAC & XLG MAC in reset */ 4539 mvpp2_mac_reset_assert(port); 4540 4541 /* Set the MPCS and XPCS in reset */ 4542 mvpp22_pcs_reset_assert(port); 4543 4544 /* comphy reconfiguration */ 4545 mvpp22_comphy_init(port, interface); 4546 4547 /* gop reconfiguration */ 4548 mvpp22_gop_init(port, interface); 4549 4550 mvpp22_pcs_reset_deassert(port, interface); 4551 4552 if (mvpp2_port_supports_xlg(port)) { 4553 ctrl3 = readl(port->base + MVPP22_XLG_CTRL3_REG); 4554 ctrl3 &= ~MVPP22_XLG_CTRL3_MACMODESELECT_MASK; 4555 4556 if (mvpp2_is_xlg(interface)) 4557 ctrl3 |= MVPP22_XLG_CTRL3_MACMODESELECT_10G; 4558 else 4559 ctrl3 |= MVPP22_XLG_CTRL3_MACMODESELECT_GMAC; 4560 4561 writel(ctrl3, port->base + MVPP22_XLG_CTRL3_REG); 4562 } 4563 4564 if (mvpp2_port_supports_xlg(port) && mvpp2_is_xlg(interface)) 4565 mvpp2_xlg_max_rx_size_set(port); 4566 else 4567 mvpp2_gmac_max_rx_size_set(port); 4568 } 4569 4570 /* Set hw internals when starting port */ 4571 static void mvpp2_start_dev(struct mvpp2_port *port) 4572 { 4573 int i; 4574 4575 mvpp2_txp_max_tx_size_set(port); 4576 4577 for (i = 0; i < port->nqvecs; i++) 4578 napi_enable(&port->qvecs[i].napi); 4579 4580 /* Enable interrupts on all threads */ 4581 mvpp2_interrupts_enable(port); 4582 4583 if (port->priv->hw_version >= MVPP22) 4584 mvpp22_mode_reconfigure(port, port->phy_interface); 4585 4586 if (port->phylink) { 4587 phylink_start(port->phylink); 4588 } else { 4589 mvpp2_acpi_start(port); 4590 } 4591 4592 netif_tx_start_all_queues(port->dev); 4593 4594 clear_bit(0, &port->state); 4595 } 4596 4597 /* Set hw internals when stopping port */ 4598 static void mvpp2_stop_dev(struct mvpp2_port *port) 4599 { 4600 int i; 4601 4602 set_bit(0, &port->state); 4603 4604 /* Disable interrupts on all threads */ 4605 mvpp2_interrupts_disable(port); 4606 4607 for (i = 0; i < port->nqvecs; i++) 4608 napi_disable(&port->qvecs[i].napi); 4609 4610 if (port->phylink) 4611 phylink_stop(port->phylink); 4612 phy_power_off(port->comphy); 4613 } 4614 4615 static int mvpp2_check_ringparam_valid(struct net_device *dev, 4616 struct ethtool_ringparam *ring) 4617 { 4618 u16 new_rx_pending = ring->rx_pending; 4619 u16 new_tx_pending = ring->tx_pending; 4620 4621 if (ring->rx_pending == 0 || ring->tx_pending == 0) 4622 return -EINVAL; 4623 4624 if (ring->rx_pending > MVPP2_MAX_RXD_MAX) 4625 new_rx_pending = MVPP2_MAX_RXD_MAX; 4626 else if (ring->rx_pending < MSS_THRESHOLD_START) 4627 new_rx_pending = MSS_THRESHOLD_START; 4628 else if (!IS_ALIGNED(ring->rx_pending, 16)) 4629 new_rx_pending = ALIGN(ring->rx_pending, 16); 4630 4631 if (ring->tx_pending > MVPP2_MAX_TXD_MAX) 4632 new_tx_pending = MVPP2_MAX_TXD_MAX; 4633 else if (!IS_ALIGNED(ring->tx_pending, 32)) 4634 new_tx_pending = ALIGN(ring->tx_pending, 32); 4635 4636 /* The Tx ring size cannot be smaller than the minimum number of 4637 * descriptors needed for TSO. 4638 */ 4639 if (new_tx_pending < MVPP2_MAX_SKB_DESCS) 4640 new_tx_pending = ALIGN(MVPP2_MAX_SKB_DESCS, 32); 4641 4642 if (ring->rx_pending != new_rx_pending) { 4643 netdev_info(dev, "illegal Rx ring size value %d, round to %d\n", 4644 ring->rx_pending, new_rx_pending); 4645 ring->rx_pending = new_rx_pending; 4646 } 4647 4648 if (ring->tx_pending != new_tx_pending) { 4649 netdev_info(dev, "illegal Tx ring size value %d, round to %d\n", 4650 ring->tx_pending, new_tx_pending); 4651 ring->tx_pending = new_tx_pending; 4652 } 4653 4654 return 0; 4655 } 4656 4657 static void mvpp21_get_mac_address(struct mvpp2_port *port, unsigned char *addr) 4658 { 4659 u32 mac_addr_l, mac_addr_m, mac_addr_h; 4660 4661 mac_addr_l = readl(port->base + MVPP2_GMAC_CTRL_1_REG); 4662 mac_addr_m = readl(port->priv->lms_base + MVPP2_SRC_ADDR_MIDDLE); 4663 mac_addr_h = readl(port->priv->lms_base + MVPP2_SRC_ADDR_HIGH); 4664 addr[0] = (mac_addr_h >> 24) & 0xFF; 4665 addr[1] = (mac_addr_h >> 16) & 0xFF; 4666 addr[2] = (mac_addr_h >> 8) & 0xFF; 4667 addr[3] = mac_addr_h & 0xFF; 4668 addr[4] = mac_addr_m & 0xFF; 4669 addr[5] = (mac_addr_l >> MVPP2_GMAC_SA_LOW_OFFS) & 0xFF; 4670 } 4671 4672 static int mvpp2_irqs_init(struct mvpp2_port *port) 4673 { 4674 int err, i; 4675 4676 for (i = 0; i < port->nqvecs; i++) { 4677 struct mvpp2_queue_vector *qv = port->qvecs + i; 4678 4679 if (qv->type == MVPP2_QUEUE_VECTOR_PRIVATE) { 4680 qv->mask = kzalloc(cpumask_size(), GFP_KERNEL); 4681 if (!qv->mask) { 4682 err = -ENOMEM; 4683 goto err; 4684 } 4685 4686 irq_set_status_flags(qv->irq, IRQ_NO_BALANCING); 4687 } 4688 4689 err = request_irq(qv->irq, mvpp2_isr, 0, port->dev->name, qv); 4690 if (err) 4691 goto err; 4692 4693 if (qv->type == MVPP2_QUEUE_VECTOR_PRIVATE) { 4694 unsigned int cpu; 4695 4696 for_each_present_cpu(cpu) { 4697 if (mvpp2_cpu_to_thread(port->priv, cpu) == 4698 qv->sw_thread_id) 4699 cpumask_set_cpu(cpu, qv->mask); 4700 } 4701 4702 irq_set_affinity_hint(qv->irq, qv->mask); 4703 } 4704 } 4705 4706 return 0; 4707 err: 4708 for (i = 0; i < port->nqvecs; i++) { 4709 struct mvpp2_queue_vector *qv = port->qvecs + i; 4710 4711 irq_set_affinity_hint(qv->irq, NULL); 4712 kfree(qv->mask); 4713 qv->mask = NULL; 4714 free_irq(qv->irq, qv); 4715 } 4716 4717 return err; 4718 } 4719 4720 static void mvpp2_irqs_deinit(struct mvpp2_port *port) 4721 { 4722 int i; 4723 4724 for (i = 0; i < port->nqvecs; i++) { 4725 struct mvpp2_queue_vector *qv = port->qvecs + i; 4726 4727 irq_set_affinity_hint(qv->irq, NULL); 4728 kfree(qv->mask); 4729 qv->mask = NULL; 4730 irq_clear_status_flags(qv->irq, IRQ_NO_BALANCING); 4731 free_irq(qv->irq, qv); 4732 } 4733 } 4734 4735 static bool mvpp22_rss_is_supported(struct mvpp2_port *port) 4736 { 4737 return (queue_mode == MVPP2_QDIST_MULTI_MODE) && 4738 !(port->flags & MVPP2_F_LOOPBACK); 4739 } 4740 4741 static int mvpp2_open(struct net_device *dev) 4742 { 4743 struct mvpp2_port *port = netdev_priv(dev); 4744 struct mvpp2 *priv = port->priv; 4745 unsigned char mac_bcast[ETH_ALEN] = { 4746 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }; 4747 bool valid = false; 4748 int err; 4749 4750 err = mvpp2_prs_mac_da_accept(port, mac_bcast, true); 4751 if (err) { 4752 netdev_err(dev, "mvpp2_prs_mac_da_accept BC failed\n"); 4753 return err; 4754 } 4755 err = mvpp2_prs_mac_da_accept(port, dev->dev_addr, true); 4756 if (err) { 4757 netdev_err(dev, "mvpp2_prs_mac_da_accept own addr failed\n"); 4758 return err; 4759 } 4760 err = mvpp2_prs_tag_mode_set(port->priv, port->id, MVPP2_TAG_TYPE_MH); 4761 if (err) { 4762 netdev_err(dev, "mvpp2_prs_tag_mode_set failed\n"); 4763 return err; 4764 } 4765 err = mvpp2_prs_def_flow(port); 4766 if (err) { 4767 netdev_err(dev, "mvpp2_prs_def_flow failed\n"); 4768 return err; 4769 } 4770 4771 /* Allocate the Rx/Tx queues */ 4772 err = mvpp2_setup_rxqs(port); 4773 if (err) { 4774 netdev_err(port->dev, "cannot allocate Rx queues\n"); 4775 return err; 4776 } 4777 4778 err = mvpp2_setup_txqs(port); 4779 if (err) { 4780 netdev_err(port->dev, "cannot allocate Tx queues\n"); 4781 goto err_cleanup_rxqs; 4782 } 4783 4784 err = mvpp2_irqs_init(port); 4785 if (err) { 4786 netdev_err(port->dev, "cannot init IRQs\n"); 4787 goto err_cleanup_txqs; 4788 } 4789 4790 if (port->phylink) { 4791 err = phylink_fwnode_phy_connect(port->phylink, port->fwnode, 0); 4792 if (err) { 4793 netdev_err(port->dev, "could not attach PHY (%d)\n", 4794 err); 4795 goto err_free_irq; 4796 } 4797 4798 valid = true; 4799 } 4800 4801 if (priv->hw_version >= MVPP22 && port->port_irq) { 4802 err = request_irq(port->port_irq, mvpp2_port_isr, 0, 4803 dev->name, port); 4804 if (err) { 4805 netdev_err(port->dev, 4806 "cannot request port link/ptp IRQ %d\n", 4807 port->port_irq); 4808 goto err_free_irq; 4809 } 4810 4811 mvpp22_gop_setup_irq(port); 4812 4813 /* In default link is down */ 4814 netif_carrier_off(port->dev); 4815 4816 valid = true; 4817 } else { 4818 port->port_irq = 0; 4819 } 4820 4821 if (!valid) { 4822 netdev_err(port->dev, 4823 "invalid configuration: no dt or link IRQ"); 4824 err = -ENOENT; 4825 goto err_free_irq; 4826 } 4827 4828 /* Unmask interrupts on all CPUs */ 4829 on_each_cpu(mvpp2_interrupts_unmask, port, 1); 4830 mvpp2_shared_interrupt_mask_unmask(port, false); 4831 4832 mvpp2_start_dev(port); 4833 4834 /* Start hardware statistics gathering */ 4835 queue_delayed_work(priv->stats_queue, &port->stats_work, 4836 MVPP2_MIB_COUNTERS_STATS_DELAY); 4837 4838 return 0; 4839 4840 err_free_irq: 4841 mvpp2_irqs_deinit(port); 4842 err_cleanup_txqs: 4843 mvpp2_cleanup_txqs(port); 4844 err_cleanup_rxqs: 4845 mvpp2_cleanup_rxqs(port); 4846 return err; 4847 } 4848 4849 static int mvpp2_stop(struct net_device *dev) 4850 { 4851 struct mvpp2_port *port = netdev_priv(dev); 4852 struct mvpp2_port_pcpu *port_pcpu; 4853 unsigned int thread; 4854 4855 mvpp2_stop_dev(port); 4856 4857 /* Mask interrupts on all threads */ 4858 on_each_cpu(mvpp2_interrupts_mask, port, 1); 4859 mvpp2_shared_interrupt_mask_unmask(port, true); 4860 4861 if (port->phylink) 4862 phylink_disconnect_phy(port->phylink); 4863 if (port->port_irq) 4864 free_irq(port->port_irq, port); 4865 4866 mvpp2_irqs_deinit(port); 4867 if (!port->has_tx_irqs) { 4868 for (thread = 0; thread < port->priv->nthreads; thread++) { 4869 port_pcpu = per_cpu_ptr(port->pcpu, thread); 4870 4871 hrtimer_cancel(&port_pcpu->tx_done_timer); 4872 port_pcpu->timer_scheduled = false; 4873 } 4874 } 4875 mvpp2_cleanup_rxqs(port); 4876 mvpp2_cleanup_txqs(port); 4877 4878 cancel_delayed_work_sync(&port->stats_work); 4879 4880 mvpp2_mac_reset_assert(port); 4881 mvpp22_pcs_reset_assert(port); 4882 4883 return 0; 4884 } 4885 4886 static int mvpp2_prs_mac_da_accept_list(struct mvpp2_port *port, 4887 struct netdev_hw_addr_list *list) 4888 { 4889 struct netdev_hw_addr *ha; 4890 int ret; 4891 4892 netdev_hw_addr_list_for_each(ha, list) { 4893 ret = mvpp2_prs_mac_da_accept(port, ha->addr, true); 4894 if (ret) 4895 return ret; 4896 } 4897 4898 return 0; 4899 } 4900 4901 static void mvpp2_set_rx_promisc(struct mvpp2_port *port, bool enable) 4902 { 4903 if (!enable && (port->dev->features & NETIF_F_HW_VLAN_CTAG_FILTER)) 4904 mvpp2_prs_vid_enable_filtering(port); 4905 else 4906 mvpp2_prs_vid_disable_filtering(port); 4907 4908 mvpp2_prs_mac_promisc_set(port->priv, port->id, 4909 MVPP2_PRS_L2_UNI_CAST, enable); 4910 4911 mvpp2_prs_mac_promisc_set(port->priv, port->id, 4912 MVPP2_PRS_L2_MULTI_CAST, enable); 4913 } 4914 4915 static void mvpp2_set_rx_mode(struct net_device *dev) 4916 { 4917 struct mvpp2_port *port = netdev_priv(dev); 4918 4919 /* Clear the whole UC and MC list */ 4920 mvpp2_prs_mac_del_all(port); 4921 4922 if (dev->flags & IFF_PROMISC) { 4923 mvpp2_set_rx_promisc(port, true); 4924 return; 4925 } 4926 4927 mvpp2_set_rx_promisc(port, false); 4928 4929 if (netdev_uc_count(dev) > MVPP2_PRS_MAC_UC_FILT_MAX || 4930 mvpp2_prs_mac_da_accept_list(port, &dev->uc)) 4931 mvpp2_prs_mac_promisc_set(port->priv, port->id, 4932 MVPP2_PRS_L2_UNI_CAST, true); 4933 4934 if (dev->flags & IFF_ALLMULTI) { 4935 mvpp2_prs_mac_promisc_set(port->priv, port->id, 4936 MVPP2_PRS_L2_MULTI_CAST, true); 4937 return; 4938 } 4939 4940 if (netdev_mc_count(dev) > MVPP2_PRS_MAC_MC_FILT_MAX || 4941 mvpp2_prs_mac_da_accept_list(port, &dev->mc)) 4942 mvpp2_prs_mac_promisc_set(port->priv, port->id, 4943 MVPP2_PRS_L2_MULTI_CAST, true); 4944 } 4945 4946 static int mvpp2_set_mac_address(struct net_device *dev, void *p) 4947 { 4948 const struct sockaddr *addr = p; 4949 int err; 4950 4951 if (!is_valid_ether_addr(addr->sa_data)) 4952 return -EADDRNOTAVAIL; 4953 4954 err = mvpp2_prs_update_mac_da(dev, addr->sa_data); 4955 if (err) { 4956 /* Reconfigure parser accept the original MAC address */ 4957 mvpp2_prs_update_mac_da(dev, dev->dev_addr); 4958 netdev_err(dev, "failed to change MAC address\n"); 4959 } 4960 return err; 4961 } 4962 4963 /* Shut down all the ports, reconfigure the pools as percpu or shared, 4964 * then bring up again all ports. 4965 */ 4966 static int mvpp2_bm_switch_buffers(struct mvpp2 *priv, bool percpu) 4967 { 4968 bool change_percpu = (percpu != priv->percpu_pools); 4969 int numbufs = MVPP2_BM_POOLS_NUM, i; 4970 struct mvpp2_port *port = NULL; 4971 bool status[MVPP2_MAX_PORTS]; 4972 4973 for (i = 0; i < priv->port_count; i++) { 4974 port = priv->port_list[i]; 4975 status[i] = netif_running(port->dev); 4976 if (status[i]) 4977 mvpp2_stop(port->dev); 4978 } 4979 4980 /* nrxqs is the same for all ports */ 4981 if (priv->percpu_pools) 4982 numbufs = port->nrxqs * 2; 4983 4984 if (change_percpu) 4985 mvpp2_bm_pool_update_priv_fc(priv, false); 4986 4987 for (i = 0; i < numbufs; i++) 4988 mvpp2_bm_pool_destroy(port->dev->dev.parent, priv, &priv->bm_pools[i]); 4989 4990 devm_kfree(port->dev->dev.parent, priv->bm_pools); 4991 priv->percpu_pools = percpu; 4992 mvpp2_bm_init(port->dev->dev.parent, priv); 4993 4994 for (i = 0; i < priv->port_count; i++) { 4995 port = priv->port_list[i]; 4996 mvpp2_swf_bm_pool_init(port); 4997 if (status[i]) 4998 mvpp2_open(port->dev); 4999 } 5000 5001 if (change_percpu) 5002 mvpp2_bm_pool_update_priv_fc(priv, true); 5003 5004 return 0; 5005 } 5006 5007 static int mvpp2_change_mtu(struct net_device *dev, int mtu) 5008 { 5009 struct mvpp2_port *port = netdev_priv(dev); 5010 bool running = netif_running(dev); 5011 struct mvpp2 *priv = port->priv; 5012 int err; 5013 5014 if (!IS_ALIGNED(MVPP2_RX_PKT_SIZE(mtu), 8)) { 5015 netdev_info(dev, "illegal MTU value %d, round to %d\n", mtu, 5016 ALIGN(MVPP2_RX_PKT_SIZE(mtu), 8)); 5017 mtu = ALIGN(MVPP2_RX_PKT_SIZE(mtu), 8); 5018 } 5019 5020 if (MVPP2_RX_PKT_SIZE(mtu) > MVPP2_BM_LONG_PKT_SIZE) { 5021 if (port->xdp_prog) { 5022 netdev_err(dev, "Jumbo frames are not supported with XDP\n"); 5023 return -EINVAL; 5024 } 5025 if (priv->percpu_pools) { 5026 netdev_warn(dev, "mtu %d too high, switching to shared buffers", mtu); 5027 mvpp2_bm_switch_buffers(priv, false); 5028 } 5029 } else { 5030 bool jumbo = false; 5031 int i; 5032 5033 for (i = 0; i < priv->port_count; i++) 5034 if (priv->port_list[i] != port && 5035 MVPP2_RX_PKT_SIZE(priv->port_list[i]->dev->mtu) > 5036 MVPP2_BM_LONG_PKT_SIZE) { 5037 jumbo = true; 5038 break; 5039 } 5040 5041 /* No port is using jumbo frames */ 5042 if (!jumbo) { 5043 dev_info(port->dev->dev.parent, 5044 "all ports have a low MTU, switching to per-cpu buffers"); 5045 mvpp2_bm_switch_buffers(priv, true); 5046 } 5047 } 5048 5049 if (running) 5050 mvpp2_stop_dev(port); 5051 5052 err = mvpp2_bm_update_mtu(dev, mtu); 5053 if (err) { 5054 netdev_err(dev, "failed to change MTU\n"); 5055 /* Reconfigure BM to the original MTU */ 5056 mvpp2_bm_update_mtu(dev, dev->mtu); 5057 } else { 5058 port->pkt_size = MVPP2_RX_PKT_SIZE(mtu); 5059 } 5060 5061 if (running) { 5062 mvpp2_start_dev(port); 5063 mvpp2_egress_enable(port); 5064 mvpp2_ingress_enable(port); 5065 } 5066 5067 return err; 5068 } 5069 5070 static int mvpp2_check_pagepool_dma(struct mvpp2_port *port) 5071 { 5072 enum dma_data_direction dma_dir = DMA_FROM_DEVICE; 5073 struct mvpp2 *priv = port->priv; 5074 int err = -1, i; 5075 5076 if (!priv->percpu_pools) 5077 return err; 5078 5079 if (!priv->page_pool[0]) 5080 return -ENOMEM; 5081 5082 for (i = 0; i < priv->port_count; i++) { 5083 port = priv->port_list[i]; 5084 if (port->xdp_prog) { 5085 dma_dir = DMA_BIDIRECTIONAL; 5086 break; 5087 } 5088 } 5089 5090 /* All pools are equal in terms of DMA direction */ 5091 if (priv->page_pool[0]->p.dma_dir != dma_dir) 5092 err = mvpp2_bm_switch_buffers(priv, true); 5093 5094 return err; 5095 } 5096 5097 static void 5098 mvpp2_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats) 5099 { 5100 struct mvpp2_port *port = netdev_priv(dev); 5101 unsigned int start; 5102 unsigned int cpu; 5103 5104 for_each_possible_cpu(cpu) { 5105 struct mvpp2_pcpu_stats *cpu_stats; 5106 u64 rx_packets; 5107 u64 rx_bytes; 5108 u64 tx_packets; 5109 u64 tx_bytes; 5110 5111 cpu_stats = per_cpu_ptr(port->stats, cpu); 5112 do { 5113 start = u64_stats_fetch_begin_irq(&cpu_stats->syncp); 5114 rx_packets = cpu_stats->rx_packets; 5115 rx_bytes = cpu_stats->rx_bytes; 5116 tx_packets = cpu_stats->tx_packets; 5117 tx_bytes = cpu_stats->tx_bytes; 5118 } while (u64_stats_fetch_retry_irq(&cpu_stats->syncp, start)); 5119 5120 stats->rx_packets += rx_packets; 5121 stats->rx_bytes += rx_bytes; 5122 stats->tx_packets += tx_packets; 5123 stats->tx_bytes += tx_bytes; 5124 } 5125 5126 stats->rx_errors = dev->stats.rx_errors; 5127 stats->rx_dropped = dev->stats.rx_dropped; 5128 stats->tx_dropped = dev->stats.tx_dropped; 5129 } 5130 5131 static int mvpp2_set_ts_config(struct mvpp2_port *port, struct ifreq *ifr) 5132 { 5133 struct hwtstamp_config config; 5134 void __iomem *ptp; 5135 u32 gcr, int_mask; 5136 5137 if (copy_from_user(&config, ifr->ifr_data, sizeof(config))) 5138 return -EFAULT; 5139 5140 if (config.flags) 5141 return -EINVAL; 5142 5143 if (config.tx_type != HWTSTAMP_TX_OFF && 5144 config.tx_type != HWTSTAMP_TX_ON) 5145 return -ERANGE; 5146 5147 ptp = port->priv->iface_base + MVPP22_PTP_BASE(port->gop_id); 5148 5149 int_mask = gcr = 0; 5150 if (config.tx_type != HWTSTAMP_TX_OFF) { 5151 gcr |= MVPP22_PTP_GCR_TSU_ENABLE | MVPP22_PTP_GCR_TX_RESET; 5152 int_mask |= MVPP22_PTP_INT_MASK_QUEUE1 | 5153 MVPP22_PTP_INT_MASK_QUEUE0; 5154 } 5155 5156 /* It seems we must also release the TX reset when enabling the TSU */ 5157 if (config.rx_filter != HWTSTAMP_FILTER_NONE) 5158 gcr |= MVPP22_PTP_GCR_TSU_ENABLE | MVPP22_PTP_GCR_RX_RESET | 5159 MVPP22_PTP_GCR_TX_RESET; 5160 5161 if (gcr & MVPP22_PTP_GCR_TSU_ENABLE) 5162 mvpp22_tai_start(port->priv->tai); 5163 5164 if (config.rx_filter != HWTSTAMP_FILTER_NONE) { 5165 config.rx_filter = HWTSTAMP_FILTER_ALL; 5166 mvpp2_modify(ptp + MVPP22_PTP_GCR, 5167 MVPP22_PTP_GCR_RX_RESET | 5168 MVPP22_PTP_GCR_TX_RESET | 5169 MVPP22_PTP_GCR_TSU_ENABLE, gcr); 5170 port->rx_hwtstamp = true; 5171 } else { 5172 port->rx_hwtstamp = false; 5173 mvpp2_modify(ptp + MVPP22_PTP_GCR, 5174 MVPP22_PTP_GCR_RX_RESET | 5175 MVPP22_PTP_GCR_TX_RESET | 5176 MVPP22_PTP_GCR_TSU_ENABLE, gcr); 5177 } 5178 5179 mvpp2_modify(ptp + MVPP22_PTP_INT_MASK, 5180 MVPP22_PTP_INT_MASK_QUEUE1 | 5181 MVPP22_PTP_INT_MASK_QUEUE0, int_mask); 5182 5183 if (!(gcr & MVPP22_PTP_GCR_TSU_ENABLE)) 5184 mvpp22_tai_stop(port->priv->tai); 5185 5186 port->tx_hwtstamp_type = config.tx_type; 5187 5188 if (copy_to_user(ifr->ifr_data, &config, sizeof(config))) 5189 return -EFAULT; 5190 5191 return 0; 5192 } 5193 5194 static int mvpp2_get_ts_config(struct mvpp2_port *port, struct ifreq *ifr) 5195 { 5196 struct hwtstamp_config config; 5197 5198 memset(&config, 0, sizeof(config)); 5199 5200 config.tx_type = port->tx_hwtstamp_type; 5201 config.rx_filter = port->rx_hwtstamp ? 5202 HWTSTAMP_FILTER_ALL : HWTSTAMP_FILTER_NONE; 5203 5204 if (copy_to_user(ifr->ifr_data, &config, sizeof(config))) 5205 return -EFAULT; 5206 5207 return 0; 5208 } 5209 5210 static int mvpp2_ethtool_get_ts_info(struct net_device *dev, 5211 struct ethtool_ts_info *info) 5212 { 5213 struct mvpp2_port *port = netdev_priv(dev); 5214 5215 if (!port->hwtstamp) 5216 return -EOPNOTSUPP; 5217 5218 info->phc_index = mvpp22_tai_ptp_clock_index(port->priv->tai); 5219 info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE | 5220 SOF_TIMESTAMPING_RX_SOFTWARE | 5221 SOF_TIMESTAMPING_SOFTWARE | 5222 SOF_TIMESTAMPING_TX_HARDWARE | 5223 SOF_TIMESTAMPING_RX_HARDWARE | 5224 SOF_TIMESTAMPING_RAW_HARDWARE; 5225 info->tx_types = BIT(HWTSTAMP_TX_OFF) | 5226 BIT(HWTSTAMP_TX_ON); 5227 info->rx_filters = BIT(HWTSTAMP_FILTER_NONE) | 5228 BIT(HWTSTAMP_FILTER_ALL); 5229 5230 return 0; 5231 } 5232 5233 static int mvpp2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) 5234 { 5235 struct mvpp2_port *port = netdev_priv(dev); 5236 5237 switch (cmd) { 5238 case SIOCSHWTSTAMP: 5239 if (port->hwtstamp) 5240 return mvpp2_set_ts_config(port, ifr); 5241 break; 5242 5243 case SIOCGHWTSTAMP: 5244 if (port->hwtstamp) 5245 return mvpp2_get_ts_config(port, ifr); 5246 break; 5247 } 5248 5249 if (!port->phylink) 5250 return -ENOTSUPP; 5251 5252 return phylink_mii_ioctl(port->phylink, ifr, cmd); 5253 } 5254 5255 static int mvpp2_vlan_rx_add_vid(struct net_device *dev, __be16 proto, u16 vid) 5256 { 5257 struct mvpp2_port *port = netdev_priv(dev); 5258 int ret; 5259 5260 ret = mvpp2_prs_vid_entry_add(port, vid); 5261 if (ret) 5262 netdev_err(dev, "rx-vlan-filter offloading cannot accept more than %d VIDs per port\n", 5263 MVPP2_PRS_VLAN_FILT_MAX - 1); 5264 return ret; 5265 } 5266 5267 static int mvpp2_vlan_rx_kill_vid(struct net_device *dev, __be16 proto, u16 vid) 5268 { 5269 struct mvpp2_port *port = netdev_priv(dev); 5270 5271 mvpp2_prs_vid_entry_remove(port, vid); 5272 return 0; 5273 } 5274 5275 static int mvpp2_set_features(struct net_device *dev, 5276 netdev_features_t features) 5277 { 5278 netdev_features_t changed = dev->features ^ features; 5279 struct mvpp2_port *port = netdev_priv(dev); 5280 5281 if (changed & NETIF_F_HW_VLAN_CTAG_FILTER) { 5282 if (features & NETIF_F_HW_VLAN_CTAG_FILTER) { 5283 mvpp2_prs_vid_enable_filtering(port); 5284 } else { 5285 /* Invalidate all registered VID filters for this 5286 * port 5287 */ 5288 mvpp2_prs_vid_remove_all(port); 5289 5290 mvpp2_prs_vid_disable_filtering(port); 5291 } 5292 } 5293 5294 if (changed & NETIF_F_RXHASH) { 5295 if (features & NETIF_F_RXHASH) 5296 mvpp22_port_rss_enable(port); 5297 else 5298 mvpp22_port_rss_disable(port); 5299 } 5300 5301 return 0; 5302 } 5303 5304 static int mvpp2_xdp_setup(struct mvpp2_port *port, struct netdev_bpf *bpf) 5305 { 5306 struct bpf_prog *prog = bpf->prog, *old_prog; 5307 bool running = netif_running(port->dev); 5308 bool reset = !prog != !port->xdp_prog; 5309 5310 if (port->dev->mtu > ETH_DATA_LEN) { 5311 NL_SET_ERR_MSG_MOD(bpf->extack, "XDP is not supported with jumbo frames enabled"); 5312 return -EOPNOTSUPP; 5313 } 5314 5315 if (!port->priv->percpu_pools) { 5316 NL_SET_ERR_MSG_MOD(bpf->extack, "Per CPU Pools required for XDP"); 5317 return -EOPNOTSUPP; 5318 } 5319 5320 if (port->ntxqs < num_possible_cpus() * 2) { 5321 NL_SET_ERR_MSG_MOD(bpf->extack, "XDP_TX needs two TX queues per CPU"); 5322 return -EOPNOTSUPP; 5323 } 5324 5325 /* device is up and bpf is added/removed, must setup the RX queues */ 5326 if (running && reset) 5327 mvpp2_stop(port->dev); 5328 5329 old_prog = xchg(&port->xdp_prog, prog); 5330 if (old_prog) 5331 bpf_prog_put(old_prog); 5332 5333 /* bpf is just replaced, RXQ and MTU are already setup */ 5334 if (!reset) 5335 return 0; 5336 5337 /* device was up, restore the link */ 5338 if (running) 5339 mvpp2_open(port->dev); 5340 5341 /* Check Page Pool DMA Direction */ 5342 mvpp2_check_pagepool_dma(port); 5343 5344 return 0; 5345 } 5346 5347 static int mvpp2_xdp(struct net_device *dev, struct netdev_bpf *xdp) 5348 { 5349 struct mvpp2_port *port = netdev_priv(dev); 5350 5351 switch (xdp->command) { 5352 case XDP_SETUP_PROG: 5353 return mvpp2_xdp_setup(port, xdp); 5354 default: 5355 return -EINVAL; 5356 } 5357 } 5358 5359 /* Ethtool methods */ 5360 5361 static int mvpp2_ethtool_nway_reset(struct net_device *dev) 5362 { 5363 struct mvpp2_port *port = netdev_priv(dev); 5364 5365 if (!port->phylink) 5366 return -ENOTSUPP; 5367 5368 return phylink_ethtool_nway_reset(port->phylink); 5369 } 5370 5371 /* Set interrupt coalescing for ethtools */ 5372 static int 5373 mvpp2_ethtool_set_coalesce(struct net_device *dev, 5374 struct ethtool_coalesce *c, 5375 struct kernel_ethtool_coalesce *kernel_coal, 5376 struct netlink_ext_ack *extack) 5377 { 5378 struct mvpp2_port *port = netdev_priv(dev); 5379 int queue; 5380 5381 for (queue = 0; queue < port->nrxqs; queue++) { 5382 struct mvpp2_rx_queue *rxq = port->rxqs[queue]; 5383 5384 rxq->time_coal = c->rx_coalesce_usecs; 5385 rxq->pkts_coal = c->rx_max_coalesced_frames; 5386 mvpp2_rx_pkts_coal_set(port, rxq); 5387 mvpp2_rx_time_coal_set(port, rxq); 5388 } 5389 5390 if (port->has_tx_irqs) { 5391 port->tx_time_coal = c->tx_coalesce_usecs; 5392 mvpp2_tx_time_coal_set(port); 5393 } 5394 5395 for (queue = 0; queue < port->ntxqs; queue++) { 5396 struct mvpp2_tx_queue *txq = port->txqs[queue]; 5397 5398 txq->done_pkts_coal = c->tx_max_coalesced_frames; 5399 5400 if (port->has_tx_irqs) 5401 mvpp2_tx_pkts_coal_set(port, txq); 5402 } 5403 5404 return 0; 5405 } 5406 5407 /* get coalescing for ethtools */ 5408 static int 5409 mvpp2_ethtool_get_coalesce(struct net_device *dev, 5410 struct ethtool_coalesce *c, 5411 struct kernel_ethtool_coalesce *kernel_coal, 5412 struct netlink_ext_ack *extack) 5413 { 5414 struct mvpp2_port *port = netdev_priv(dev); 5415 5416 c->rx_coalesce_usecs = port->rxqs[0]->time_coal; 5417 c->rx_max_coalesced_frames = port->rxqs[0]->pkts_coal; 5418 c->tx_max_coalesced_frames = port->txqs[0]->done_pkts_coal; 5419 c->tx_coalesce_usecs = port->tx_time_coal; 5420 return 0; 5421 } 5422 5423 static void mvpp2_ethtool_get_drvinfo(struct net_device *dev, 5424 struct ethtool_drvinfo *drvinfo) 5425 { 5426 strlcpy(drvinfo->driver, MVPP2_DRIVER_NAME, 5427 sizeof(drvinfo->driver)); 5428 strlcpy(drvinfo->version, MVPP2_DRIVER_VERSION, 5429 sizeof(drvinfo->version)); 5430 strlcpy(drvinfo->bus_info, dev_name(&dev->dev), 5431 sizeof(drvinfo->bus_info)); 5432 } 5433 5434 static void mvpp2_ethtool_get_ringparam(struct net_device *dev, 5435 struct ethtool_ringparam *ring) 5436 { 5437 struct mvpp2_port *port = netdev_priv(dev); 5438 5439 ring->rx_max_pending = MVPP2_MAX_RXD_MAX; 5440 ring->tx_max_pending = MVPP2_MAX_TXD_MAX; 5441 ring->rx_pending = port->rx_ring_size; 5442 ring->tx_pending = port->tx_ring_size; 5443 } 5444 5445 static int mvpp2_ethtool_set_ringparam(struct net_device *dev, 5446 struct ethtool_ringparam *ring) 5447 { 5448 struct mvpp2_port *port = netdev_priv(dev); 5449 u16 prev_rx_ring_size = port->rx_ring_size; 5450 u16 prev_tx_ring_size = port->tx_ring_size; 5451 int err; 5452 5453 err = mvpp2_check_ringparam_valid(dev, ring); 5454 if (err) 5455 return err; 5456 5457 if (!netif_running(dev)) { 5458 port->rx_ring_size = ring->rx_pending; 5459 port->tx_ring_size = ring->tx_pending; 5460 return 0; 5461 } 5462 5463 /* The interface is running, so we have to force a 5464 * reallocation of the queues 5465 */ 5466 mvpp2_stop_dev(port); 5467 mvpp2_cleanup_rxqs(port); 5468 mvpp2_cleanup_txqs(port); 5469 5470 port->rx_ring_size = ring->rx_pending; 5471 port->tx_ring_size = ring->tx_pending; 5472 5473 err = mvpp2_setup_rxqs(port); 5474 if (err) { 5475 /* Reallocate Rx queues with the original ring size */ 5476 port->rx_ring_size = prev_rx_ring_size; 5477 ring->rx_pending = prev_rx_ring_size; 5478 err = mvpp2_setup_rxqs(port); 5479 if (err) 5480 goto err_out; 5481 } 5482 err = mvpp2_setup_txqs(port); 5483 if (err) { 5484 /* Reallocate Tx queues with the original ring size */ 5485 port->tx_ring_size = prev_tx_ring_size; 5486 ring->tx_pending = prev_tx_ring_size; 5487 err = mvpp2_setup_txqs(port); 5488 if (err) 5489 goto err_clean_rxqs; 5490 } 5491 5492 mvpp2_start_dev(port); 5493 mvpp2_egress_enable(port); 5494 mvpp2_ingress_enable(port); 5495 5496 return 0; 5497 5498 err_clean_rxqs: 5499 mvpp2_cleanup_rxqs(port); 5500 err_out: 5501 netdev_err(dev, "failed to change ring parameters"); 5502 return err; 5503 } 5504 5505 static void mvpp2_ethtool_get_pause_param(struct net_device *dev, 5506 struct ethtool_pauseparam *pause) 5507 { 5508 struct mvpp2_port *port = netdev_priv(dev); 5509 5510 if (!port->phylink) 5511 return; 5512 5513 phylink_ethtool_get_pauseparam(port->phylink, pause); 5514 } 5515 5516 static int mvpp2_ethtool_set_pause_param(struct net_device *dev, 5517 struct ethtool_pauseparam *pause) 5518 { 5519 struct mvpp2_port *port = netdev_priv(dev); 5520 5521 if (!port->phylink) 5522 return -ENOTSUPP; 5523 5524 return phylink_ethtool_set_pauseparam(port->phylink, pause); 5525 } 5526 5527 static int mvpp2_ethtool_get_link_ksettings(struct net_device *dev, 5528 struct ethtool_link_ksettings *cmd) 5529 { 5530 struct mvpp2_port *port = netdev_priv(dev); 5531 5532 if (!port->phylink) 5533 return -ENOTSUPP; 5534 5535 return phylink_ethtool_ksettings_get(port->phylink, cmd); 5536 } 5537 5538 static int mvpp2_ethtool_set_link_ksettings(struct net_device *dev, 5539 const struct ethtool_link_ksettings *cmd) 5540 { 5541 struct mvpp2_port *port = netdev_priv(dev); 5542 5543 if (!port->phylink) 5544 return -ENOTSUPP; 5545 5546 return phylink_ethtool_ksettings_set(port->phylink, cmd); 5547 } 5548 5549 static int mvpp2_ethtool_get_rxnfc(struct net_device *dev, 5550 struct ethtool_rxnfc *info, u32 *rules) 5551 { 5552 struct mvpp2_port *port = netdev_priv(dev); 5553 int ret = 0, i, loc = 0; 5554 5555 if (!mvpp22_rss_is_supported(port)) 5556 return -EOPNOTSUPP; 5557 5558 switch (info->cmd) { 5559 case ETHTOOL_GRXFH: 5560 ret = mvpp2_ethtool_rxfh_get(port, info); 5561 break; 5562 case ETHTOOL_GRXRINGS: 5563 info->data = port->nrxqs; 5564 break; 5565 case ETHTOOL_GRXCLSRLCNT: 5566 info->rule_cnt = port->n_rfs_rules; 5567 break; 5568 case ETHTOOL_GRXCLSRULE: 5569 ret = mvpp2_ethtool_cls_rule_get(port, info); 5570 break; 5571 case ETHTOOL_GRXCLSRLALL: 5572 for (i = 0; i < MVPP2_N_RFS_ENTRIES_PER_FLOW; i++) { 5573 if (port->rfs_rules[i]) 5574 rules[loc++] = i; 5575 } 5576 break; 5577 default: 5578 return -ENOTSUPP; 5579 } 5580 5581 return ret; 5582 } 5583 5584 static int mvpp2_ethtool_set_rxnfc(struct net_device *dev, 5585 struct ethtool_rxnfc *info) 5586 { 5587 struct mvpp2_port *port = netdev_priv(dev); 5588 int ret = 0; 5589 5590 if (!mvpp22_rss_is_supported(port)) 5591 return -EOPNOTSUPP; 5592 5593 switch (info->cmd) { 5594 case ETHTOOL_SRXFH: 5595 ret = mvpp2_ethtool_rxfh_set(port, info); 5596 break; 5597 case ETHTOOL_SRXCLSRLINS: 5598 ret = mvpp2_ethtool_cls_rule_ins(port, info); 5599 break; 5600 case ETHTOOL_SRXCLSRLDEL: 5601 ret = mvpp2_ethtool_cls_rule_del(port, info); 5602 break; 5603 default: 5604 return -EOPNOTSUPP; 5605 } 5606 return ret; 5607 } 5608 5609 static u32 mvpp2_ethtool_get_rxfh_indir_size(struct net_device *dev) 5610 { 5611 struct mvpp2_port *port = netdev_priv(dev); 5612 5613 return mvpp22_rss_is_supported(port) ? MVPP22_RSS_TABLE_ENTRIES : 0; 5614 } 5615 5616 static int mvpp2_ethtool_get_rxfh(struct net_device *dev, u32 *indir, u8 *key, 5617 u8 *hfunc) 5618 { 5619 struct mvpp2_port *port = netdev_priv(dev); 5620 int ret = 0; 5621 5622 if (!mvpp22_rss_is_supported(port)) 5623 return -EOPNOTSUPP; 5624 5625 if (indir) 5626 ret = mvpp22_port_rss_ctx_indir_get(port, 0, indir); 5627 5628 if (hfunc) 5629 *hfunc = ETH_RSS_HASH_CRC32; 5630 5631 return ret; 5632 } 5633 5634 static int mvpp2_ethtool_set_rxfh(struct net_device *dev, const u32 *indir, 5635 const u8 *key, const u8 hfunc) 5636 { 5637 struct mvpp2_port *port = netdev_priv(dev); 5638 int ret = 0; 5639 5640 if (!mvpp22_rss_is_supported(port)) 5641 return -EOPNOTSUPP; 5642 5643 if (hfunc != ETH_RSS_HASH_NO_CHANGE && hfunc != ETH_RSS_HASH_CRC32) 5644 return -EOPNOTSUPP; 5645 5646 if (key) 5647 return -EOPNOTSUPP; 5648 5649 if (indir) 5650 ret = mvpp22_port_rss_ctx_indir_set(port, 0, indir); 5651 5652 return ret; 5653 } 5654 5655 static int mvpp2_ethtool_get_rxfh_context(struct net_device *dev, u32 *indir, 5656 u8 *key, u8 *hfunc, u32 rss_context) 5657 { 5658 struct mvpp2_port *port = netdev_priv(dev); 5659 int ret = 0; 5660 5661 if (!mvpp22_rss_is_supported(port)) 5662 return -EOPNOTSUPP; 5663 if (rss_context >= MVPP22_N_RSS_TABLES) 5664 return -EINVAL; 5665 5666 if (hfunc) 5667 *hfunc = ETH_RSS_HASH_CRC32; 5668 5669 if (indir) 5670 ret = mvpp22_port_rss_ctx_indir_get(port, rss_context, indir); 5671 5672 return ret; 5673 } 5674 5675 static int mvpp2_ethtool_set_rxfh_context(struct net_device *dev, 5676 const u32 *indir, const u8 *key, 5677 const u8 hfunc, u32 *rss_context, 5678 bool delete) 5679 { 5680 struct mvpp2_port *port = netdev_priv(dev); 5681 int ret; 5682 5683 if (!mvpp22_rss_is_supported(port)) 5684 return -EOPNOTSUPP; 5685 5686 if (hfunc != ETH_RSS_HASH_NO_CHANGE && hfunc != ETH_RSS_HASH_CRC32) 5687 return -EOPNOTSUPP; 5688 5689 if (key) 5690 return -EOPNOTSUPP; 5691 5692 if (delete) 5693 return mvpp22_port_rss_ctx_delete(port, *rss_context); 5694 5695 if (*rss_context == ETH_RXFH_CONTEXT_ALLOC) { 5696 ret = mvpp22_port_rss_ctx_create(port, rss_context); 5697 if (ret) 5698 return ret; 5699 } 5700 5701 return mvpp22_port_rss_ctx_indir_set(port, *rss_context, indir); 5702 } 5703 /* Device ops */ 5704 5705 static const struct net_device_ops mvpp2_netdev_ops = { 5706 .ndo_open = mvpp2_open, 5707 .ndo_stop = mvpp2_stop, 5708 .ndo_start_xmit = mvpp2_tx, 5709 .ndo_set_rx_mode = mvpp2_set_rx_mode, 5710 .ndo_set_mac_address = mvpp2_set_mac_address, 5711 .ndo_change_mtu = mvpp2_change_mtu, 5712 .ndo_get_stats64 = mvpp2_get_stats64, 5713 .ndo_eth_ioctl = mvpp2_ioctl, 5714 .ndo_vlan_rx_add_vid = mvpp2_vlan_rx_add_vid, 5715 .ndo_vlan_rx_kill_vid = mvpp2_vlan_rx_kill_vid, 5716 .ndo_set_features = mvpp2_set_features, 5717 .ndo_bpf = mvpp2_xdp, 5718 .ndo_xdp_xmit = mvpp2_xdp_xmit, 5719 }; 5720 5721 static const struct ethtool_ops mvpp2_eth_tool_ops = { 5722 .supported_coalesce_params = ETHTOOL_COALESCE_USECS | 5723 ETHTOOL_COALESCE_MAX_FRAMES, 5724 .nway_reset = mvpp2_ethtool_nway_reset, 5725 .get_link = ethtool_op_get_link, 5726 .get_ts_info = mvpp2_ethtool_get_ts_info, 5727 .set_coalesce = mvpp2_ethtool_set_coalesce, 5728 .get_coalesce = mvpp2_ethtool_get_coalesce, 5729 .get_drvinfo = mvpp2_ethtool_get_drvinfo, 5730 .get_ringparam = mvpp2_ethtool_get_ringparam, 5731 .set_ringparam = mvpp2_ethtool_set_ringparam, 5732 .get_strings = mvpp2_ethtool_get_strings, 5733 .get_ethtool_stats = mvpp2_ethtool_get_stats, 5734 .get_sset_count = mvpp2_ethtool_get_sset_count, 5735 .get_pauseparam = mvpp2_ethtool_get_pause_param, 5736 .set_pauseparam = mvpp2_ethtool_set_pause_param, 5737 .get_link_ksettings = mvpp2_ethtool_get_link_ksettings, 5738 .set_link_ksettings = mvpp2_ethtool_set_link_ksettings, 5739 .get_rxnfc = mvpp2_ethtool_get_rxnfc, 5740 .set_rxnfc = mvpp2_ethtool_set_rxnfc, 5741 .get_rxfh_indir_size = mvpp2_ethtool_get_rxfh_indir_size, 5742 .get_rxfh = mvpp2_ethtool_get_rxfh, 5743 .set_rxfh = mvpp2_ethtool_set_rxfh, 5744 .get_rxfh_context = mvpp2_ethtool_get_rxfh_context, 5745 .set_rxfh_context = mvpp2_ethtool_set_rxfh_context, 5746 }; 5747 5748 /* Used for PPv2.1, or PPv2.2 with the old Device Tree binding that 5749 * had a single IRQ defined per-port. 5750 */ 5751 static int mvpp2_simple_queue_vectors_init(struct mvpp2_port *port, 5752 struct device_node *port_node) 5753 { 5754 struct mvpp2_queue_vector *v = &port->qvecs[0]; 5755 5756 v->first_rxq = 0; 5757 v->nrxqs = port->nrxqs; 5758 v->type = MVPP2_QUEUE_VECTOR_SHARED; 5759 v->sw_thread_id = 0; 5760 v->sw_thread_mask = *cpumask_bits(cpu_online_mask); 5761 v->port = port; 5762 v->irq = irq_of_parse_and_map(port_node, 0); 5763 if (v->irq <= 0) 5764 return -EINVAL; 5765 netif_napi_add(port->dev, &v->napi, mvpp2_poll, 5766 NAPI_POLL_WEIGHT); 5767 5768 port->nqvecs = 1; 5769 5770 return 0; 5771 } 5772 5773 static int mvpp2_multi_queue_vectors_init(struct mvpp2_port *port, 5774 struct device_node *port_node) 5775 { 5776 struct mvpp2 *priv = port->priv; 5777 struct mvpp2_queue_vector *v; 5778 int i, ret; 5779 5780 switch (queue_mode) { 5781 case MVPP2_QDIST_SINGLE_MODE: 5782 port->nqvecs = priv->nthreads + 1; 5783 break; 5784 case MVPP2_QDIST_MULTI_MODE: 5785 port->nqvecs = priv->nthreads; 5786 break; 5787 } 5788 5789 for (i = 0; i < port->nqvecs; i++) { 5790 char irqname[16]; 5791 5792 v = port->qvecs + i; 5793 5794 v->port = port; 5795 v->type = MVPP2_QUEUE_VECTOR_PRIVATE; 5796 v->sw_thread_id = i; 5797 v->sw_thread_mask = BIT(i); 5798 5799 if (port->flags & MVPP2_F_DT_COMPAT) 5800 snprintf(irqname, sizeof(irqname), "tx-cpu%d", i); 5801 else 5802 snprintf(irqname, sizeof(irqname), "hif%d", i); 5803 5804 if (queue_mode == MVPP2_QDIST_MULTI_MODE) { 5805 v->first_rxq = i; 5806 v->nrxqs = 1; 5807 } else if (queue_mode == MVPP2_QDIST_SINGLE_MODE && 5808 i == (port->nqvecs - 1)) { 5809 v->first_rxq = 0; 5810 v->nrxqs = port->nrxqs; 5811 v->type = MVPP2_QUEUE_VECTOR_SHARED; 5812 5813 if (port->flags & MVPP2_F_DT_COMPAT) 5814 strncpy(irqname, "rx-shared", sizeof(irqname)); 5815 } 5816 5817 if (port_node) 5818 v->irq = of_irq_get_byname(port_node, irqname); 5819 else 5820 v->irq = fwnode_irq_get(port->fwnode, i); 5821 if (v->irq <= 0) { 5822 ret = -EINVAL; 5823 goto err; 5824 } 5825 5826 netif_napi_add(port->dev, &v->napi, mvpp2_poll, 5827 NAPI_POLL_WEIGHT); 5828 } 5829 5830 return 0; 5831 5832 err: 5833 for (i = 0; i < port->nqvecs; i++) 5834 irq_dispose_mapping(port->qvecs[i].irq); 5835 return ret; 5836 } 5837 5838 static int mvpp2_queue_vectors_init(struct mvpp2_port *port, 5839 struct device_node *port_node) 5840 { 5841 if (port->has_tx_irqs) 5842 return mvpp2_multi_queue_vectors_init(port, port_node); 5843 else 5844 return mvpp2_simple_queue_vectors_init(port, port_node); 5845 } 5846 5847 static void mvpp2_queue_vectors_deinit(struct mvpp2_port *port) 5848 { 5849 int i; 5850 5851 for (i = 0; i < port->nqvecs; i++) 5852 irq_dispose_mapping(port->qvecs[i].irq); 5853 } 5854 5855 /* Configure Rx queue group interrupt for this port */ 5856 static void mvpp2_rx_irqs_setup(struct mvpp2_port *port) 5857 { 5858 struct mvpp2 *priv = port->priv; 5859 u32 val; 5860 int i; 5861 5862 if (priv->hw_version == MVPP21) { 5863 mvpp2_write(priv, MVPP21_ISR_RXQ_GROUP_REG(port->id), 5864 port->nrxqs); 5865 return; 5866 } 5867 5868 /* Handle the more complicated PPv2.2 and PPv2.3 case */ 5869 for (i = 0; i < port->nqvecs; i++) { 5870 struct mvpp2_queue_vector *qv = port->qvecs + i; 5871 5872 if (!qv->nrxqs) 5873 continue; 5874 5875 val = qv->sw_thread_id; 5876 val |= port->id << MVPP22_ISR_RXQ_GROUP_INDEX_GROUP_OFFSET; 5877 mvpp2_write(priv, MVPP22_ISR_RXQ_GROUP_INDEX_REG, val); 5878 5879 val = qv->first_rxq; 5880 val |= qv->nrxqs << MVPP22_ISR_RXQ_SUB_GROUP_SIZE_OFFSET; 5881 mvpp2_write(priv, MVPP22_ISR_RXQ_SUB_GROUP_CONFIG_REG, val); 5882 } 5883 } 5884 5885 /* Initialize port HW */ 5886 static int mvpp2_port_init(struct mvpp2_port *port) 5887 { 5888 struct device *dev = port->dev->dev.parent; 5889 struct mvpp2 *priv = port->priv; 5890 struct mvpp2_txq_pcpu *txq_pcpu; 5891 unsigned int thread; 5892 int queue, err, val; 5893 5894 /* Checks for hardware constraints */ 5895 if (port->first_rxq + port->nrxqs > 5896 MVPP2_MAX_PORTS * priv->max_port_rxqs) 5897 return -EINVAL; 5898 5899 if (port->nrxqs > priv->max_port_rxqs || port->ntxqs > MVPP2_MAX_TXQ) 5900 return -EINVAL; 5901 5902 /* Disable port */ 5903 mvpp2_egress_disable(port); 5904 mvpp2_port_disable(port); 5905 5906 if (mvpp2_is_xlg(port->phy_interface)) { 5907 val = readl(port->base + MVPP22_XLG_CTRL0_REG); 5908 val &= ~MVPP22_XLG_CTRL0_FORCE_LINK_PASS; 5909 val |= MVPP22_XLG_CTRL0_FORCE_LINK_DOWN; 5910 writel(val, port->base + MVPP22_XLG_CTRL0_REG); 5911 } else { 5912 val = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG); 5913 val &= ~MVPP2_GMAC_FORCE_LINK_PASS; 5914 val |= MVPP2_GMAC_FORCE_LINK_DOWN; 5915 writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG); 5916 } 5917 5918 port->tx_time_coal = MVPP2_TXDONE_COAL_USEC; 5919 5920 port->txqs = devm_kcalloc(dev, port->ntxqs, sizeof(*port->txqs), 5921 GFP_KERNEL); 5922 if (!port->txqs) 5923 return -ENOMEM; 5924 5925 /* Associate physical Tx queues to this port and initialize. 5926 * The mapping is predefined. 5927 */ 5928 for (queue = 0; queue < port->ntxqs; queue++) { 5929 int queue_phy_id = mvpp2_txq_phys(port->id, queue); 5930 struct mvpp2_tx_queue *txq; 5931 5932 txq = devm_kzalloc(dev, sizeof(*txq), GFP_KERNEL); 5933 if (!txq) { 5934 err = -ENOMEM; 5935 goto err_free_percpu; 5936 } 5937 5938 txq->pcpu = alloc_percpu(struct mvpp2_txq_pcpu); 5939 if (!txq->pcpu) { 5940 err = -ENOMEM; 5941 goto err_free_percpu; 5942 } 5943 5944 txq->id = queue_phy_id; 5945 txq->log_id = queue; 5946 txq->done_pkts_coal = MVPP2_TXDONE_COAL_PKTS_THRESH; 5947 for (thread = 0; thread < priv->nthreads; thread++) { 5948 txq_pcpu = per_cpu_ptr(txq->pcpu, thread); 5949 txq_pcpu->thread = thread; 5950 } 5951 5952 port->txqs[queue] = txq; 5953 } 5954 5955 port->rxqs = devm_kcalloc(dev, port->nrxqs, sizeof(*port->rxqs), 5956 GFP_KERNEL); 5957 if (!port->rxqs) { 5958 err = -ENOMEM; 5959 goto err_free_percpu; 5960 } 5961 5962 /* Allocate and initialize Rx queue for this port */ 5963 for (queue = 0; queue < port->nrxqs; queue++) { 5964 struct mvpp2_rx_queue *rxq; 5965 5966 /* Map physical Rx queue to port's logical Rx queue */ 5967 rxq = devm_kzalloc(dev, sizeof(*rxq), GFP_KERNEL); 5968 if (!rxq) { 5969 err = -ENOMEM; 5970 goto err_free_percpu; 5971 } 5972 /* Map this Rx queue to a physical queue */ 5973 rxq->id = port->first_rxq + queue; 5974 rxq->port = port->id; 5975 rxq->logic_rxq = queue; 5976 5977 port->rxqs[queue] = rxq; 5978 } 5979 5980 mvpp2_rx_irqs_setup(port); 5981 5982 /* Create Rx descriptor rings */ 5983 for (queue = 0; queue < port->nrxqs; queue++) { 5984 struct mvpp2_rx_queue *rxq = port->rxqs[queue]; 5985 5986 rxq->size = port->rx_ring_size; 5987 rxq->pkts_coal = MVPP2_RX_COAL_PKTS; 5988 rxq->time_coal = MVPP2_RX_COAL_USEC; 5989 } 5990 5991 mvpp2_ingress_disable(port); 5992 5993 /* Port default configuration */ 5994 mvpp2_defaults_set(port); 5995 5996 /* Port's classifier configuration */ 5997 mvpp2_cls_oversize_rxq_set(port); 5998 mvpp2_cls_port_config(port); 5999 6000 if (mvpp22_rss_is_supported(port)) 6001 mvpp22_port_rss_init(port); 6002 6003 /* Provide an initial Rx packet size */ 6004 port->pkt_size = MVPP2_RX_PKT_SIZE(port->dev->mtu); 6005 6006 /* Initialize pools for swf */ 6007 err = mvpp2_swf_bm_pool_init(port); 6008 if (err) 6009 goto err_free_percpu; 6010 6011 /* Clear all port stats */ 6012 mvpp2_read_stats(port); 6013 memset(port->ethtool_stats, 0, 6014 MVPP2_N_ETHTOOL_STATS(port->ntxqs, port->nrxqs) * sizeof(u64)); 6015 6016 return 0; 6017 6018 err_free_percpu: 6019 for (queue = 0; queue < port->ntxqs; queue++) { 6020 if (!port->txqs[queue]) 6021 continue; 6022 free_percpu(port->txqs[queue]->pcpu); 6023 } 6024 return err; 6025 } 6026 6027 static bool mvpp22_port_has_legacy_tx_irqs(struct device_node *port_node, 6028 unsigned long *flags) 6029 { 6030 char *irqs[5] = { "rx-shared", "tx-cpu0", "tx-cpu1", "tx-cpu2", 6031 "tx-cpu3" }; 6032 int i; 6033 6034 for (i = 0; i < 5; i++) 6035 if (of_property_match_string(port_node, "interrupt-names", 6036 irqs[i]) < 0) 6037 return false; 6038 6039 *flags |= MVPP2_F_DT_COMPAT; 6040 return true; 6041 } 6042 6043 /* Checks if the port dt description has the required Tx interrupts: 6044 * - PPv2.1: there are no such interrupts. 6045 * - PPv2.2 and PPv2.3: 6046 * - The old DTs have: "rx-shared", "tx-cpuX" with X in [0...3] 6047 * - The new ones have: "hifX" with X in [0..8] 6048 * 6049 * All those variants are supported to keep the backward compatibility. 6050 */ 6051 static bool mvpp2_port_has_irqs(struct mvpp2 *priv, 6052 struct device_node *port_node, 6053 unsigned long *flags) 6054 { 6055 char name[5]; 6056 int i; 6057 6058 /* ACPI */ 6059 if (!port_node) 6060 return true; 6061 6062 if (priv->hw_version == MVPP21) 6063 return false; 6064 6065 if (mvpp22_port_has_legacy_tx_irqs(port_node, flags)) 6066 return true; 6067 6068 for (i = 0; i < MVPP2_MAX_THREADS; i++) { 6069 snprintf(name, 5, "hif%d", i); 6070 if (of_property_match_string(port_node, "interrupt-names", 6071 name) < 0) 6072 return false; 6073 } 6074 6075 return true; 6076 } 6077 6078 static void mvpp2_port_copy_mac_addr(struct net_device *dev, struct mvpp2 *priv, 6079 struct fwnode_handle *fwnode, 6080 char **mac_from) 6081 { 6082 struct mvpp2_port *port = netdev_priv(dev); 6083 char hw_mac_addr[ETH_ALEN] = {0}; 6084 char fw_mac_addr[ETH_ALEN]; 6085 6086 if (!fwnode_get_mac_address(fwnode, fw_mac_addr)) { 6087 *mac_from = "firmware node"; 6088 eth_hw_addr_set(dev, fw_mac_addr); 6089 return; 6090 } 6091 6092 if (priv->hw_version == MVPP21) { 6093 mvpp21_get_mac_address(port, hw_mac_addr); 6094 if (is_valid_ether_addr(hw_mac_addr)) { 6095 *mac_from = "hardware"; 6096 eth_hw_addr_set(dev, hw_mac_addr); 6097 return; 6098 } 6099 } 6100 6101 *mac_from = "random"; 6102 eth_hw_addr_random(dev); 6103 } 6104 6105 static struct mvpp2_port *mvpp2_phylink_to_port(struct phylink_config *config) 6106 { 6107 return container_of(config, struct mvpp2_port, phylink_config); 6108 } 6109 6110 static struct mvpp2_port *mvpp2_pcs_to_port(struct phylink_pcs *pcs) 6111 { 6112 return container_of(pcs, struct mvpp2_port, phylink_pcs); 6113 } 6114 6115 static void mvpp2_xlg_pcs_get_state(struct phylink_pcs *pcs, 6116 struct phylink_link_state *state) 6117 { 6118 struct mvpp2_port *port = mvpp2_pcs_to_port(pcs); 6119 u32 val; 6120 6121 state->speed = SPEED_10000; 6122 state->duplex = 1; 6123 state->an_complete = 1; 6124 6125 val = readl(port->base + MVPP22_XLG_STATUS); 6126 state->link = !!(val & MVPP22_XLG_STATUS_LINK_UP); 6127 6128 state->pause = 0; 6129 val = readl(port->base + MVPP22_XLG_CTRL0_REG); 6130 if (val & MVPP22_XLG_CTRL0_TX_FLOW_CTRL_EN) 6131 state->pause |= MLO_PAUSE_TX; 6132 if (val & MVPP22_XLG_CTRL0_RX_FLOW_CTRL_EN) 6133 state->pause |= MLO_PAUSE_RX; 6134 } 6135 6136 static int mvpp2_xlg_pcs_config(struct phylink_pcs *pcs, 6137 unsigned int mode, 6138 phy_interface_t interface, 6139 const unsigned long *advertising, 6140 bool permit_pause_to_mac) 6141 { 6142 return 0; 6143 } 6144 6145 static const struct phylink_pcs_ops mvpp2_phylink_xlg_pcs_ops = { 6146 .pcs_get_state = mvpp2_xlg_pcs_get_state, 6147 .pcs_config = mvpp2_xlg_pcs_config, 6148 }; 6149 6150 static void mvpp2_gmac_pcs_get_state(struct phylink_pcs *pcs, 6151 struct phylink_link_state *state) 6152 { 6153 struct mvpp2_port *port = mvpp2_pcs_to_port(pcs); 6154 u32 val; 6155 6156 val = readl(port->base + MVPP2_GMAC_STATUS0); 6157 6158 state->an_complete = !!(val & MVPP2_GMAC_STATUS0_AN_COMPLETE); 6159 state->link = !!(val & MVPP2_GMAC_STATUS0_LINK_UP); 6160 state->duplex = !!(val & MVPP2_GMAC_STATUS0_FULL_DUPLEX); 6161 6162 switch (port->phy_interface) { 6163 case PHY_INTERFACE_MODE_1000BASEX: 6164 state->speed = SPEED_1000; 6165 break; 6166 case PHY_INTERFACE_MODE_2500BASEX: 6167 state->speed = SPEED_2500; 6168 break; 6169 default: 6170 if (val & MVPP2_GMAC_STATUS0_GMII_SPEED) 6171 state->speed = SPEED_1000; 6172 else if (val & MVPP2_GMAC_STATUS0_MII_SPEED) 6173 state->speed = SPEED_100; 6174 else 6175 state->speed = SPEED_10; 6176 } 6177 6178 state->pause = 0; 6179 if (val & MVPP2_GMAC_STATUS0_RX_PAUSE) 6180 state->pause |= MLO_PAUSE_RX; 6181 if (val & MVPP2_GMAC_STATUS0_TX_PAUSE) 6182 state->pause |= MLO_PAUSE_TX; 6183 } 6184 6185 static int mvpp2_gmac_pcs_config(struct phylink_pcs *pcs, unsigned int mode, 6186 phy_interface_t interface, 6187 const unsigned long *advertising, 6188 bool permit_pause_to_mac) 6189 { 6190 struct mvpp2_port *port = mvpp2_pcs_to_port(pcs); 6191 u32 mask, val, an, old_an, changed; 6192 6193 mask = MVPP2_GMAC_IN_BAND_AUTONEG_BYPASS | 6194 MVPP2_GMAC_IN_BAND_AUTONEG | 6195 MVPP2_GMAC_AN_SPEED_EN | 6196 MVPP2_GMAC_FLOW_CTRL_AUTONEG | 6197 MVPP2_GMAC_AN_DUPLEX_EN; 6198 6199 if (phylink_autoneg_inband(mode)) { 6200 mask |= MVPP2_GMAC_CONFIG_MII_SPEED | 6201 MVPP2_GMAC_CONFIG_GMII_SPEED | 6202 MVPP2_GMAC_CONFIG_FULL_DUPLEX; 6203 val = MVPP2_GMAC_IN_BAND_AUTONEG; 6204 6205 if (interface == PHY_INTERFACE_MODE_SGMII) { 6206 /* SGMII mode receives the speed and duplex from PHY */ 6207 val |= MVPP2_GMAC_AN_SPEED_EN | 6208 MVPP2_GMAC_AN_DUPLEX_EN; 6209 } else { 6210 /* 802.3z mode has fixed speed and duplex */ 6211 val |= MVPP2_GMAC_CONFIG_GMII_SPEED | 6212 MVPP2_GMAC_CONFIG_FULL_DUPLEX; 6213 6214 /* The FLOW_CTRL_AUTONEG bit selects either the hardware 6215 * automatically or the bits in MVPP22_GMAC_CTRL_4_REG 6216 * manually controls the GMAC pause modes. 6217 */ 6218 if (permit_pause_to_mac) 6219 val |= MVPP2_GMAC_FLOW_CTRL_AUTONEG; 6220 6221 /* Configure advertisement bits */ 6222 mask |= MVPP2_GMAC_FC_ADV_EN | MVPP2_GMAC_FC_ADV_ASM_EN; 6223 if (phylink_test(advertising, Pause)) 6224 val |= MVPP2_GMAC_FC_ADV_EN; 6225 if (phylink_test(advertising, Asym_Pause)) 6226 val |= MVPP2_GMAC_FC_ADV_ASM_EN; 6227 } 6228 } else { 6229 val = 0; 6230 } 6231 6232 old_an = an = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG); 6233 an = (an & ~mask) | val; 6234 changed = an ^ old_an; 6235 if (changed) 6236 writel(an, port->base + MVPP2_GMAC_AUTONEG_CONFIG); 6237 6238 /* We are only interested in the advertisement bits changing */ 6239 return changed & (MVPP2_GMAC_FC_ADV_EN | MVPP2_GMAC_FC_ADV_ASM_EN); 6240 } 6241 6242 static void mvpp2_gmac_pcs_an_restart(struct phylink_pcs *pcs) 6243 { 6244 struct mvpp2_port *port = mvpp2_pcs_to_port(pcs); 6245 u32 val = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG); 6246 6247 writel(val | MVPP2_GMAC_IN_BAND_RESTART_AN, 6248 port->base + MVPP2_GMAC_AUTONEG_CONFIG); 6249 writel(val & ~MVPP2_GMAC_IN_BAND_RESTART_AN, 6250 port->base + MVPP2_GMAC_AUTONEG_CONFIG); 6251 } 6252 6253 static const struct phylink_pcs_ops mvpp2_phylink_gmac_pcs_ops = { 6254 .pcs_get_state = mvpp2_gmac_pcs_get_state, 6255 .pcs_config = mvpp2_gmac_pcs_config, 6256 .pcs_an_restart = mvpp2_gmac_pcs_an_restart, 6257 }; 6258 6259 static void mvpp2_phylink_validate(struct phylink_config *config, 6260 unsigned long *supported, 6261 struct phylink_link_state *state) 6262 { 6263 struct mvpp2_port *port = mvpp2_phylink_to_port(config); 6264 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, }; 6265 6266 /* When in 802.3z mode, we must have AN enabled: 6267 * Bit 2 Field InBandAnEn In-band Auto-Negotiation enable. ... 6268 * When <PortType> = 1 (1000BASE-X) this field must be set to 1. 6269 */ 6270 if (phy_interface_mode_is_8023z(state->interface) && 6271 !phylink_test(state->advertising, Autoneg)) 6272 goto empty_set; 6273 6274 phylink_set(mask, Autoneg); 6275 phylink_set_port_modes(mask); 6276 6277 if (port->priv->global_tx_fc) { 6278 phylink_set(mask, Pause); 6279 phylink_set(mask, Asym_Pause); 6280 } 6281 6282 switch (state->interface) { 6283 case PHY_INTERFACE_MODE_10GBASER: 6284 case PHY_INTERFACE_MODE_XAUI: 6285 if (mvpp2_port_supports_xlg(port)) { 6286 phylink_set_10g_modes(mask); 6287 phylink_set(mask, 10000baseKR_Full); 6288 } 6289 break; 6290 6291 case PHY_INTERFACE_MODE_RGMII: 6292 case PHY_INTERFACE_MODE_RGMII_ID: 6293 case PHY_INTERFACE_MODE_RGMII_RXID: 6294 case PHY_INTERFACE_MODE_RGMII_TXID: 6295 case PHY_INTERFACE_MODE_SGMII: 6296 phylink_set(mask, 10baseT_Half); 6297 phylink_set(mask, 10baseT_Full); 6298 phylink_set(mask, 100baseT_Half); 6299 phylink_set(mask, 100baseT_Full); 6300 phylink_set(mask, 1000baseT_Full); 6301 phylink_set(mask, 1000baseX_Full); 6302 break; 6303 6304 case PHY_INTERFACE_MODE_1000BASEX: 6305 phylink_set(mask, 1000baseT_Full); 6306 phylink_set(mask, 1000baseX_Full); 6307 break; 6308 6309 case PHY_INTERFACE_MODE_2500BASEX: 6310 phylink_set(mask, 2500baseT_Full); 6311 phylink_set(mask, 2500baseX_Full); 6312 break; 6313 6314 default: 6315 goto empty_set; 6316 } 6317 6318 linkmode_and(supported, supported, mask); 6319 linkmode_and(state->advertising, state->advertising, mask); 6320 return; 6321 6322 empty_set: 6323 linkmode_zero(supported); 6324 } 6325 6326 static void mvpp2_xlg_config(struct mvpp2_port *port, unsigned int mode, 6327 const struct phylink_link_state *state) 6328 { 6329 u32 val; 6330 6331 mvpp2_modify(port->base + MVPP22_XLG_CTRL0_REG, 6332 MVPP22_XLG_CTRL0_MAC_RESET_DIS, 6333 MVPP22_XLG_CTRL0_MAC_RESET_DIS); 6334 mvpp2_modify(port->base + MVPP22_XLG_CTRL4_REG, 6335 MVPP22_XLG_CTRL4_MACMODSELECT_GMAC | 6336 MVPP22_XLG_CTRL4_EN_IDLE_CHECK | 6337 MVPP22_XLG_CTRL4_FWD_FC | MVPP22_XLG_CTRL4_FWD_PFC, 6338 MVPP22_XLG_CTRL4_FWD_FC | MVPP22_XLG_CTRL4_FWD_PFC); 6339 6340 /* Wait for reset to deassert */ 6341 do { 6342 val = readl(port->base + MVPP22_XLG_CTRL0_REG); 6343 } while (!(val & MVPP22_XLG_CTRL0_MAC_RESET_DIS)); 6344 } 6345 6346 static void mvpp2_gmac_config(struct mvpp2_port *port, unsigned int mode, 6347 const struct phylink_link_state *state) 6348 { 6349 u32 old_ctrl0, ctrl0; 6350 u32 old_ctrl2, ctrl2; 6351 u32 old_ctrl4, ctrl4; 6352 6353 old_ctrl0 = ctrl0 = readl(port->base + MVPP2_GMAC_CTRL_0_REG); 6354 old_ctrl2 = ctrl2 = readl(port->base + MVPP2_GMAC_CTRL_2_REG); 6355 old_ctrl4 = ctrl4 = readl(port->base + MVPP22_GMAC_CTRL_4_REG); 6356 6357 ctrl0 &= ~MVPP2_GMAC_PORT_TYPE_MASK; 6358 ctrl2 &= ~(MVPP2_GMAC_INBAND_AN_MASK | MVPP2_GMAC_PCS_ENABLE_MASK | MVPP2_GMAC_FLOW_CTRL_MASK); 6359 6360 /* Configure port type */ 6361 if (phy_interface_mode_is_8023z(state->interface)) { 6362 ctrl2 |= MVPP2_GMAC_PCS_ENABLE_MASK; 6363 ctrl4 &= ~MVPP22_CTRL4_EXT_PIN_GMII_SEL; 6364 ctrl4 |= MVPP22_CTRL4_SYNC_BYPASS_DIS | 6365 MVPP22_CTRL4_DP_CLK_SEL | 6366 MVPP22_CTRL4_QSGMII_BYPASS_ACTIVE; 6367 } else if (state->interface == PHY_INTERFACE_MODE_SGMII) { 6368 ctrl2 |= MVPP2_GMAC_PCS_ENABLE_MASK | MVPP2_GMAC_INBAND_AN_MASK; 6369 ctrl4 &= ~MVPP22_CTRL4_EXT_PIN_GMII_SEL; 6370 ctrl4 |= MVPP22_CTRL4_SYNC_BYPASS_DIS | 6371 MVPP22_CTRL4_DP_CLK_SEL | 6372 MVPP22_CTRL4_QSGMII_BYPASS_ACTIVE; 6373 } else if (phy_interface_mode_is_rgmii(state->interface)) { 6374 ctrl4 &= ~MVPP22_CTRL4_DP_CLK_SEL; 6375 ctrl4 |= MVPP22_CTRL4_EXT_PIN_GMII_SEL | 6376 MVPP22_CTRL4_SYNC_BYPASS_DIS | 6377 MVPP22_CTRL4_QSGMII_BYPASS_ACTIVE; 6378 } 6379 6380 /* Configure negotiation style */ 6381 if (!phylink_autoneg_inband(mode)) { 6382 /* Phy or fixed speed - no in-band AN, nothing to do, leave the 6383 * configured speed, duplex and flow control as-is. 6384 */ 6385 } else if (state->interface == PHY_INTERFACE_MODE_SGMII) { 6386 /* SGMII in-band mode receives the speed and duplex from 6387 * the PHY. Flow control information is not received. */ 6388 } else if (phy_interface_mode_is_8023z(state->interface)) { 6389 /* 1000BaseX and 2500BaseX ports cannot negotiate speed nor can 6390 * they negotiate duplex: they are always operating with a fixed 6391 * speed of 1000/2500Mbps in full duplex, so force 1000/2500 6392 * speed and full duplex here. 6393 */ 6394 ctrl0 |= MVPP2_GMAC_PORT_TYPE_MASK; 6395 } 6396 6397 if (old_ctrl0 != ctrl0) 6398 writel(ctrl0, port->base + MVPP2_GMAC_CTRL_0_REG); 6399 if (old_ctrl2 != ctrl2) 6400 writel(ctrl2, port->base + MVPP2_GMAC_CTRL_2_REG); 6401 if (old_ctrl4 != ctrl4) 6402 writel(ctrl4, port->base + MVPP22_GMAC_CTRL_4_REG); 6403 } 6404 6405 static int mvpp2__mac_prepare(struct phylink_config *config, unsigned int mode, 6406 phy_interface_t interface) 6407 { 6408 struct mvpp2_port *port = mvpp2_phylink_to_port(config); 6409 6410 /* Check for invalid configuration */ 6411 if (mvpp2_is_xlg(interface) && port->gop_id != 0) { 6412 netdev_err(port->dev, "Invalid mode on %s\n", port->dev->name); 6413 return -EINVAL; 6414 } 6415 6416 if (port->phy_interface != interface || 6417 phylink_autoneg_inband(mode)) { 6418 /* Force the link down when changing the interface or if in 6419 * in-band mode to ensure we do not change the configuration 6420 * while the hardware is indicating link is up. We force both 6421 * XLG and GMAC down to ensure that they're both in a known 6422 * state. 6423 */ 6424 mvpp2_modify(port->base + MVPP2_GMAC_AUTONEG_CONFIG, 6425 MVPP2_GMAC_FORCE_LINK_PASS | 6426 MVPP2_GMAC_FORCE_LINK_DOWN, 6427 MVPP2_GMAC_FORCE_LINK_DOWN); 6428 6429 if (mvpp2_port_supports_xlg(port)) 6430 mvpp2_modify(port->base + MVPP22_XLG_CTRL0_REG, 6431 MVPP22_XLG_CTRL0_FORCE_LINK_PASS | 6432 MVPP22_XLG_CTRL0_FORCE_LINK_DOWN, 6433 MVPP22_XLG_CTRL0_FORCE_LINK_DOWN); 6434 } 6435 6436 /* Make sure the port is disabled when reconfiguring the mode */ 6437 mvpp2_port_disable(port); 6438 6439 if (port->phy_interface != interface) { 6440 /* Place GMAC into reset */ 6441 mvpp2_modify(port->base + MVPP2_GMAC_CTRL_2_REG, 6442 MVPP2_GMAC_PORT_RESET_MASK, 6443 MVPP2_GMAC_PORT_RESET_MASK); 6444 6445 if (port->priv->hw_version >= MVPP22) { 6446 mvpp22_gop_mask_irq(port); 6447 6448 phy_power_off(port->comphy); 6449 6450 /* Reconfigure the serdes lanes */ 6451 mvpp22_mode_reconfigure(port, interface); 6452 } 6453 } 6454 6455 /* Select the appropriate PCS operations depending on the 6456 * configured interface mode. We will only switch to a mode 6457 * that the validate() checks have already passed. 6458 */ 6459 if (mvpp2_is_xlg(interface)) 6460 port->phylink_pcs.ops = &mvpp2_phylink_xlg_pcs_ops; 6461 else 6462 port->phylink_pcs.ops = &mvpp2_phylink_gmac_pcs_ops; 6463 6464 return 0; 6465 } 6466 6467 static int mvpp2_mac_prepare(struct phylink_config *config, unsigned int mode, 6468 phy_interface_t interface) 6469 { 6470 struct mvpp2_port *port = mvpp2_phylink_to_port(config); 6471 int ret; 6472 6473 ret = mvpp2__mac_prepare(config, mode, interface); 6474 if (ret == 0) 6475 phylink_set_pcs(port->phylink, &port->phylink_pcs); 6476 6477 return ret; 6478 } 6479 6480 static void mvpp2_mac_config(struct phylink_config *config, unsigned int mode, 6481 const struct phylink_link_state *state) 6482 { 6483 struct mvpp2_port *port = mvpp2_phylink_to_port(config); 6484 6485 /* mac (re)configuration */ 6486 if (mvpp2_is_xlg(state->interface)) 6487 mvpp2_xlg_config(port, mode, state); 6488 else if (phy_interface_mode_is_rgmii(state->interface) || 6489 phy_interface_mode_is_8023z(state->interface) || 6490 state->interface == PHY_INTERFACE_MODE_SGMII) 6491 mvpp2_gmac_config(port, mode, state); 6492 6493 if (port->priv->hw_version == MVPP21 && port->flags & MVPP2_F_LOOPBACK) 6494 mvpp2_port_loopback_set(port, state); 6495 } 6496 6497 static int mvpp2_mac_finish(struct phylink_config *config, unsigned int mode, 6498 phy_interface_t interface) 6499 { 6500 struct mvpp2_port *port = mvpp2_phylink_to_port(config); 6501 6502 if (port->priv->hw_version >= MVPP22 && 6503 port->phy_interface != interface) { 6504 port->phy_interface = interface; 6505 6506 /* Unmask interrupts */ 6507 mvpp22_gop_unmask_irq(port); 6508 } 6509 6510 if (!mvpp2_is_xlg(interface)) { 6511 /* Release GMAC reset and wait */ 6512 mvpp2_modify(port->base + MVPP2_GMAC_CTRL_2_REG, 6513 MVPP2_GMAC_PORT_RESET_MASK, 0); 6514 6515 while (readl(port->base + MVPP2_GMAC_CTRL_2_REG) & 6516 MVPP2_GMAC_PORT_RESET_MASK) 6517 continue; 6518 } 6519 6520 mvpp2_port_enable(port); 6521 6522 /* Allow the link to come up if in in-band mode, otherwise the 6523 * link is forced via mac_link_down()/mac_link_up() 6524 */ 6525 if (phylink_autoneg_inband(mode)) { 6526 if (mvpp2_is_xlg(interface)) 6527 mvpp2_modify(port->base + MVPP22_XLG_CTRL0_REG, 6528 MVPP22_XLG_CTRL0_FORCE_LINK_PASS | 6529 MVPP22_XLG_CTRL0_FORCE_LINK_DOWN, 0); 6530 else 6531 mvpp2_modify(port->base + MVPP2_GMAC_AUTONEG_CONFIG, 6532 MVPP2_GMAC_FORCE_LINK_PASS | 6533 MVPP2_GMAC_FORCE_LINK_DOWN, 0); 6534 } 6535 6536 return 0; 6537 } 6538 6539 static void mvpp2_mac_link_up(struct phylink_config *config, 6540 struct phy_device *phy, 6541 unsigned int mode, phy_interface_t interface, 6542 int speed, int duplex, 6543 bool tx_pause, bool rx_pause) 6544 { 6545 struct mvpp2_port *port = mvpp2_phylink_to_port(config); 6546 u32 val; 6547 int i; 6548 6549 if (mvpp2_is_xlg(interface)) { 6550 if (!phylink_autoneg_inband(mode)) { 6551 val = MVPP22_XLG_CTRL0_FORCE_LINK_PASS; 6552 if (tx_pause) 6553 val |= MVPP22_XLG_CTRL0_TX_FLOW_CTRL_EN; 6554 if (rx_pause) 6555 val |= MVPP22_XLG_CTRL0_RX_FLOW_CTRL_EN; 6556 6557 mvpp2_modify(port->base + MVPP22_XLG_CTRL0_REG, 6558 MVPP22_XLG_CTRL0_FORCE_LINK_DOWN | 6559 MVPP22_XLG_CTRL0_FORCE_LINK_PASS | 6560 MVPP22_XLG_CTRL0_TX_FLOW_CTRL_EN | 6561 MVPP22_XLG_CTRL0_RX_FLOW_CTRL_EN, val); 6562 } 6563 } else { 6564 if (!phylink_autoneg_inband(mode)) { 6565 val = MVPP2_GMAC_FORCE_LINK_PASS; 6566 6567 if (speed == SPEED_1000 || speed == SPEED_2500) 6568 val |= MVPP2_GMAC_CONFIG_GMII_SPEED; 6569 else if (speed == SPEED_100) 6570 val |= MVPP2_GMAC_CONFIG_MII_SPEED; 6571 6572 if (duplex == DUPLEX_FULL) 6573 val |= MVPP2_GMAC_CONFIG_FULL_DUPLEX; 6574 6575 mvpp2_modify(port->base + MVPP2_GMAC_AUTONEG_CONFIG, 6576 MVPP2_GMAC_FORCE_LINK_DOWN | 6577 MVPP2_GMAC_FORCE_LINK_PASS | 6578 MVPP2_GMAC_CONFIG_MII_SPEED | 6579 MVPP2_GMAC_CONFIG_GMII_SPEED | 6580 MVPP2_GMAC_CONFIG_FULL_DUPLEX, val); 6581 } 6582 6583 /* We can always update the flow control enable bits; 6584 * these will only be effective if flow control AN 6585 * (MVPP2_GMAC_FLOW_CTRL_AUTONEG) is disabled. 6586 */ 6587 val = 0; 6588 if (tx_pause) 6589 val |= MVPP22_CTRL4_TX_FC_EN; 6590 if (rx_pause) 6591 val |= MVPP22_CTRL4_RX_FC_EN; 6592 6593 mvpp2_modify(port->base + MVPP22_GMAC_CTRL_4_REG, 6594 MVPP22_CTRL4_RX_FC_EN | MVPP22_CTRL4_TX_FC_EN, 6595 val); 6596 } 6597 6598 if (port->priv->global_tx_fc) { 6599 port->tx_fc = tx_pause; 6600 if (tx_pause) 6601 mvpp2_rxq_enable_fc(port); 6602 else 6603 mvpp2_rxq_disable_fc(port); 6604 if (port->priv->percpu_pools) { 6605 for (i = 0; i < port->nrxqs; i++) 6606 mvpp2_bm_pool_update_fc(port, &port->priv->bm_pools[i], tx_pause); 6607 } else { 6608 mvpp2_bm_pool_update_fc(port, port->pool_long, tx_pause); 6609 mvpp2_bm_pool_update_fc(port, port->pool_short, tx_pause); 6610 } 6611 if (port->priv->hw_version == MVPP23) 6612 mvpp23_rx_fifo_fc_en(port->priv, port->id, tx_pause); 6613 } 6614 6615 mvpp2_port_enable(port); 6616 6617 mvpp2_egress_enable(port); 6618 mvpp2_ingress_enable(port); 6619 netif_tx_wake_all_queues(port->dev); 6620 } 6621 6622 static void mvpp2_mac_link_down(struct phylink_config *config, 6623 unsigned int mode, phy_interface_t interface) 6624 { 6625 struct mvpp2_port *port = mvpp2_phylink_to_port(config); 6626 u32 val; 6627 6628 if (!phylink_autoneg_inband(mode)) { 6629 if (mvpp2_is_xlg(interface)) { 6630 val = readl(port->base + MVPP22_XLG_CTRL0_REG); 6631 val &= ~MVPP22_XLG_CTRL0_FORCE_LINK_PASS; 6632 val |= MVPP22_XLG_CTRL0_FORCE_LINK_DOWN; 6633 writel(val, port->base + MVPP22_XLG_CTRL0_REG); 6634 } else { 6635 val = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG); 6636 val &= ~MVPP2_GMAC_FORCE_LINK_PASS; 6637 val |= MVPP2_GMAC_FORCE_LINK_DOWN; 6638 writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG); 6639 } 6640 } 6641 6642 netif_tx_stop_all_queues(port->dev); 6643 mvpp2_egress_disable(port); 6644 mvpp2_ingress_disable(port); 6645 6646 mvpp2_port_disable(port); 6647 } 6648 6649 static const struct phylink_mac_ops mvpp2_phylink_ops = { 6650 .validate = mvpp2_phylink_validate, 6651 .mac_prepare = mvpp2_mac_prepare, 6652 .mac_config = mvpp2_mac_config, 6653 .mac_finish = mvpp2_mac_finish, 6654 .mac_link_up = mvpp2_mac_link_up, 6655 .mac_link_down = mvpp2_mac_link_down, 6656 }; 6657 6658 /* Work-around for ACPI */ 6659 static void mvpp2_acpi_start(struct mvpp2_port *port) 6660 { 6661 /* Phylink isn't used as of now for ACPI, so the MAC has to be 6662 * configured manually when the interface is started. This will 6663 * be removed as soon as the phylink ACPI support lands in. 6664 */ 6665 struct phylink_link_state state = { 6666 .interface = port->phy_interface, 6667 }; 6668 mvpp2__mac_prepare(&port->phylink_config, MLO_AN_INBAND, 6669 port->phy_interface); 6670 mvpp2_mac_config(&port->phylink_config, MLO_AN_INBAND, &state); 6671 port->phylink_pcs.ops->pcs_config(&port->phylink_pcs, MLO_AN_INBAND, 6672 port->phy_interface, 6673 state.advertising, false); 6674 mvpp2_mac_finish(&port->phylink_config, MLO_AN_INBAND, 6675 port->phy_interface); 6676 mvpp2_mac_link_up(&port->phylink_config, NULL, 6677 MLO_AN_INBAND, port->phy_interface, 6678 SPEED_UNKNOWN, DUPLEX_UNKNOWN, false, false); 6679 } 6680 6681 /* In order to ensure backward compatibility for ACPI, check if the port 6682 * firmware node comprises the necessary description allowing to use phylink. 6683 */ 6684 static bool mvpp2_use_acpi_compat_mode(struct fwnode_handle *port_fwnode) 6685 { 6686 if (!is_acpi_node(port_fwnode)) 6687 return false; 6688 6689 return (!fwnode_property_present(port_fwnode, "phy-handle") && 6690 !fwnode_property_present(port_fwnode, "managed") && 6691 !fwnode_get_named_child_node(port_fwnode, "fixed-link")); 6692 } 6693 6694 /* Ports initialization */ 6695 static int mvpp2_port_probe(struct platform_device *pdev, 6696 struct fwnode_handle *port_fwnode, 6697 struct mvpp2 *priv) 6698 { 6699 struct phy *comphy = NULL; 6700 struct mvpp2_port *port; 6701 struct mvpp2_port_pcpu *port_pcpu; 6702 struct device_node *port_node = to_of_node(port_fwnode); 6703 netdev_features_t features; 6704 struct net_device *dev; 6705 struct phylink *phylink; 6706 char *mac_from = ""; 6707 unsigned int ntxqs, nrxqs, thread; 6708 unsigned long flags = 0; 6709 bool has_tx_irqs; 6710 u32 id; 6711 int phy_mode; 6712 int err, i; 6713 6714 has_tx_irqs = mvpp2_port_has_irqs(priv, port_node, &flags); 6715 if (!has_tx_irqs && queue_mode == MVPP2_QDIST_MULTI_MODE) { 6716 dev_err(&pdev->dev, 6717 "not enough IRQs to support multi queue mode\n"); 6718 return -EINVAL; 6719 } 6720 6721 ntxqs = MVPP2_MAX_TXQ; 6722 nrxqs = mvpp2_get_nrxqs(priv); 6723 6724 dev = alloc_etherdev_mqs(sizeof(*port), ntxqs, nrxqs); 6725 if (!dev) 6726 return -ENOMEM; 6727 6728 phy_mode = fwnode_get_phy_mode(port_fwnode); 6729 if (phy_mode < 0) { 6730 dev_err(&pdev->dev, "incorrect phy mode\n"); 6731 err = phy_mode; 6732 goto err_free_netdev; 6733 } 6734 6735 /* 6736 * Rewrite 10GBASE-KR to 10GBASE-R for compatibility with existing DT. 6737 * Existing usage of 10GBASE-KR is not correct; no backplane 6738 * negotiation is done, and this driver does not actually support 6739 * 10GBASE-KR. 6740 */ 6741 if (phy_mode == PHY_INTERFACE_MODE_10GKR) 6742 phy_mode = PHY_INTERFACE_MODE_10GBASER; 6743 6744 if (port_node) { 6745 comphy = devm_of_phy_get(&pdev->dev, port_node, NULL); 6746 if (IS_ERR(comphy)) { 6747 if (PTR_ERR(comphy) == -EPROBE_DEFER) { 6748 err = -EPROBE_DEFER; 6749 goto err_free_netdev; 6750 } 6751 comphy = NULL; 6752 } 6753 } 6754 6755 if (fwnode_property_read_u32(port_fwnode, "port-id", &id)) { 6756 err = -EINVAL; 6757 dev_err(&pdev->dev, "missing port-id value\n"); 6758 goto err_free_netdev; 6759 } 6760 6761 dev->tx_queue_len = MVPP2_MAX_TXD_MAX; 6762 dev->watchdog_timeo = 5 * HZ; 6763 dev->netdev_ops = &mvpp2_netdev_ops; 6764 dev->ethtool_ops = &mvpp2_eth_tool_ops; 6765 6766 port = netdev_priv(dev); 6767 port->dev = dev; 6768 port->fwnode = port_fwnode; 6769 port->ntxqs = ntxqs; 6770 port->nrxqs = nrxqs; 6771 port->priv = priv; 6772 port->has_tx_irqs = has_tx_irqs; 6773 port->flags = flags; 6774 6775 err = mvpp2_queue_vectors_init(port, port_node); 6776 if (err) 6777 goto err_free_netdev; 6778 6779 if (port_node) 6780 port->port_irq = of_irq_get_byname(port_node, "link"); 6781 else 6782 port->port_irq = fwnode_irq_get(port_fwnode, port->nqvecs + 1); 6783 if (port->port_irq == -EPROBE_DEFER) { 6784 err = -EPROBE_DEFER; 6785 goto err_deinit_qvecs; 6786 } 6787 if (port->port_irq <= 0) 6788 /* the link irq is optional */ 6789 port->port_irq = 0; 6790 6791 if (fwnode_property_read_bool(port_fwnode, "marvell,loopback")) 6792 port->flags |= MVPP2_F_LOOPBACK; 6793 6794 port->id = id; 6795 if (priv->hw_version == MVPP21) 6796 port->first_rxq = port->id * port->nrxqs; 6797 else 6798 port->first_rxq = port->id * priv->max_port_rxqs; 6799 6800 port->of_node = port_node; 6801 port->phy_interface = phy_mode; 6802 port->comphy = comphy; 6803 6804 if (priv->hw_version == MVPP21) { 6805 port->base = devm_platform_ioremap_resource(pdev, 2 + id); 6806 if (IS_ERR(port->base)) { 6807 err = PTR_ERR(port->base); 6808 goto err_free_irq; 6809 } 6810 6811 port->stats_base = port->priv->lms_base + 6812 MVPP21_MIB_COUNTERS_OFFSET + 6813 port->gop_id * MVPP21_MIB_COUNTERS_PORT_SZ; 6814 } else { 6815 if (fwnode_property_read_u32(port_fwnode, "gop-port-id", 6816 &port->gop_id)) { 6817 err = -EINVAL; 6818 dev_err(&pdev->dev, "missing gop-port-id value\n"); 6819 goto err_deinit_qvecs; 6820 } 6821 6822 port->base = priv->iface_base + MVPP22_GMAC_BASE(port->gop_id); 6823 port->stats_base = port->priv->iface_base + 6824 MVPP22_MIB_COUNTERS_OFFSET + 6825 port->gop_id * MVPP22_MIB_COUNTERS_PORT_SZ; 6826 6827 /* We may want a property to describe whether we should use 6828 * MAC hardware timestamping. 6829 */ 6830 if (priv->tai) 6831 port->hwtstamp = true; 6832 } 6833 6834 /* Alloc per-cpu and ethtool stats */ 6835 port->stats = netdev_alloc_pcpu_stats(struct mvpp2_pcpu_stats); 6836 if (!port->stats) { 6837 err = -ENOMEM; 6838 goto err_free_irq; 6839 } 6840 6841 port->ethtool_stats = devm_kcalloc(&pdev->dev, 6842 MVPP2_N_ETHTOOL_STATS(ntxqs, nrxqs), 6843 sizeof(u64), GFP_KERNEL); 6844 if (!port->ethtool_stats) { 6845 err = -ENOMEM; 6846 goto err_free_stats; 6847 } 6848 6849 mutex_init(&port->gather_stats_lock); 6850 INIT_DELAYED_WORK(&port->stats_work, mvpp2_gather_hw_statistics); 6851 6852 mvpp2_port_copy_mac_addr(dev, priv, port_fwnode, &mac_from); 6853 6854 port->tx_ring_size = MVPP2_MAX_TXD_DFLT; 6855 port->rx_ring_size = MVPP2_MAX_RXD_DFLT; 6856 SET_NETDEV_DEV(dev, &pdev->dev); 6857 6858 err = mvpp2_port_init(port); 6859 if (err < 0) { 6860 dev_err(&pdev->dev, "failed to init port %d\n", id); 6861 goto err_free_stats; 6862 } 6863 6864 mvpp2_port_periodic_xon_disable(port); 6865 6866 mvpp2_mac_reset_assert(port); 6867 mvpp22_pcs_reset_assert(port); 6868 6869 port->pcpu = alloc_percpu(struct mvpp2_port_pcpu); 6870 if (!port->pcpu) { 6871 err = -ENOMEM; 6872 goto err_free_txq_pcpu; 6873 } 6874 6875 if (!port->has_tx_irqs) { 6876 for (thread = 0; thread < priv->nthreads; thread++) { 6877 port_pcpu = per_cpu_ptr(port->pcpu, thread); 6878 6879 hrtimer_init(&port_pcpu->tx_done_timer, CLOCK_MONOTONIC, 6880 HRTIMER_MODE_REL_PINNED_SOFT); 6881 port_pcpu->tx_done_timer.function = mvpp2_hr_timer_cb; 6882 port_pcpu->timer_scheduled = false; 6883 port_pcpu->dev = dev; 6884 } 6885 } 6886 6887 features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | 6888 NETIF_F_TSO; 6889 dev->features = features | NETIF_F_RXCSUM; 6890 dev->hw_features |= features | NETIF_F_RXCSUM | NETIF_F_GRO | 6891 NETIF_F_HW_VLAN_CTAG_FILTER; 6892 6893 if (mvpp22_rss_is_supported(port)) { 6894 dev->hw_features |= NETIF_F_RXHASH; 6895 dev->features |= NETIF_F_NTUPLE; 6896 } 6897 6898 if (!port->priv->percpu_pools) 6899 mvpp2_set_hw_csum(port, port->pool_long->id); 6900 6901 dev->vlan_features |= features; 6902 dev->gso_max_segs = MVPP2_MAX_TSO_SEGS; 6903 dev->priv_flags |= IFF_UNICAST_FLT; 6904 6905 /* MTU range: 68 - 9704 */ 6906 dev->min_mtu = ETH_MIN_MTU; 6907 /* 9704 == 9728 - 20 and rounding to 8 */ 6908 dev->max_mtu = MVPP2_BM_JUMBO_PKT_SIZE; 6909 dev->dev.of_node = port_node; 6910 6911 if (!mvpp2_use_acpi_compat_mode(port_fwnode)) { 6912 port->phylink_config.dev = &dev->dev; 6913 port->phylink_config.type = PHYLINK_NETDEV; 6914 6915 if (mvpp2_port_supports_xlg(port)) { 6916 __set_bit(PHY_INTERFACE_MODE_10GBASER, 6917 port->phylink_config.supported_interfaces); 6918 __set_bit(PHY_INTERFACE_MODE_XAUI, 6919 port->phylink_config.supported_interfaces); 6920 } 6921 6922 if (mvpp2_port_supports_rgmii(port)) 6923 phy_interface_set_rgmii(port->phylink_config.supported_interfaces); 6924 6925 if (comphy) { 6926 /* If a COMPHY is present, we can support any of the 6927 * serdes modes and switch between them. 6928 */ 6929 __set_bit(PHY_INTERFACE_MODE_SGMII, 6930 port->phylink_config.supported_interfaces); 6931 __set_bit(PHY_INTERFACE_MODE_1000BASEX, 6932 port->phylink_config.supported_interfaces); 6933 __set_bit(PHY_INTERFACE_MODE_2500BASEX, 6934 port->phylink_config.supported_interfaces); 6935 } else if (phy_mode == PHY_INTERFACE_MODE_2500BASEX) { 6936 /* No COMPHY, with only 2500BASE-X mode supported */ 6937 __set_bit(PHY_INTERFACE_MODE_2500BASEX, 6938 port->phylink_config.supported_interfaces); 6939 } else if (phy_mode == PHY_INTERFACE_MODE_1000BASEX || 6940 phy_mode == PHY_INTERFACE_MODE_SGMII) { 6941 /* No COMPHY, we can switch between 1000BASE-X and SGMII 6942 */ 6943 __set_bit(PHY_INTERFACE_MODE_1000BASEX, 6944 port->phylink_config.supported_interfaces); 6945 __set_bit(PHY_INTERFACE_MODE_SGMII, 6946 port->phylink_config.supported_interfaces); 6947 } 6948 6949 phylink = phylink_create(&port->phylink_config, port_fwnode, 6950 phy_mode, &mvpp2_phylink_ops); 6951 if (IS_ERR(phylink)) { 6952 err = PTR_ERR(phylink); 6953 goto err_free_port_pcpu; 6954 } 6955 port->phylink = phylink; 6956 } else { 6957 dev_warn(&pdev->dev, "Use link irqs for port#%d. FW update required\n", port->id); 6958 port->phylink = NULL; 6959 } 6960 6961 /* Cycle the comphy to power it down, saving 270mW per port - 6962 * don't worry about an error powering it up. When the comphy 6963 * driver does this, we can remove this code. 6964 */ 6965 if (port->comphy) { 6966 err = mvpp22_comphy_init(port, port->phy_interface); 6967 if (err == 0) 6968 phy_power_off(port->comphy); 6969 } 6970 6971 err = register_netdev(dev); 6972 if (err < 0) { 6973 dev_err(&pdev->dev, "failed to register netdev\n"); 6974 goto err_phylink; 6975 } 6976 netdev_info(dev, "Using %s mac address %pM\n", mac_from, dev->dev_addr); 6977 6978 priv->port_list[priv->port_count++] = port; 6979 6980 return 0; 6981 6982 err_phylink: 6983 if (port->phylink) 6984 phylink_destroy(port->phylink); 6985 err_free_port_pcpu: 6986 free_percpu(port->pcpu); 6987 err_free_txq_pcpu: 6988 for (i = 0; i < port->ntxqs; i++) 6989 free_percpu(port->txqs[i]->pcpu); 6990 err_free_stats: 6991 free_percpu(port->stats); 6992 err_free_irq: 6993 if (port->port_irq) 6994 irq_dispose_mapping(port->port_irq); 6995 err_deinit_qvecs: 6996 mvpp2_queue_vectors_deinit(port); 6997 err_free_netdev: 6998 free_netdev(dev); 6999 return err; 7000 } 7001 7002 /* Ports removal routine */ 7003 static void mvpp2_port_remove(struct mvpp2_port *port) 7004 { 7005 int i; 7006 7007 unregister_netdev(port->dev); 7008 if (port->phylink) 7009 phylink_destroy(port->phylink); 7010 free_percpu(port->pcpu); 7011 free_percpu(port->stats); 7012 for (i = 0; i < port->ntxqs; i++) 7013 free_percpu(port->txqs[i]->pcpu); 7014 mvpp2_queue_vectors_deinit(port); 7015 if (port->port_irq) 7016 irq_dispose_mapping(port->port_irq); 7017 free_netdev(port->dev); 7018 } 7019 7020 /* Initialize decoding windows */ 7021 static void mvpp2_conf_mbus_windows(const struct mbus_dram_target_info *dram, 7022 struct mvpp2 *priv) 7023 { 7024 u32 win_enable; 7025 int i; 7026 7027 for (i = 0; i < 6; i++) { 7028 mvpp2_write(priv, MVPP2_WIN_BASE(i), 0); 7029 mvpp2_write(priv, MVPP2_WIN_SIZE(i), 0); 7030 7031 if (i < 4) 7032 mvpp2_write(priv, MVPP2_WIN_REMAP(i), 0); 7033 } 7034 7035 win_enable = 0; 7036 7037 for (i = 0; i < dram->num_cs; i++) { 7038 const struct mbus_dram_window *cs = dram->cs + i; 7039 7040 mvpp2_write(priv, MVPP2_WIN_BASE(i), 7041 (cs->base & 0xffff0000) | (cs->mbus_attr << 8) | 7042 dram->mbus_dram_target_id); 7043 7044 mvpp2_write(priv, MVPP2_WIN_SIZE(i), 7045 (cs->size - 1) & 0xffff0000); 7046 7047 win_enable |= (1 << i); 7048 } 7049 7050 mvpp2_write(priv, MVPP2_BASE_ADDR_ENABLE, win_enable); 7051 } 7052 7053 /* Initialize Rx FIFO's */ 7054 static void mvpp2_rx_fifo_init(struct mvpp2 *priv) 7055 { 7056 int port; 7057 7058 for (port = 0; port < MVPP2_MAX_PORTS; port++) { 7059 mvpp2_write(priv, MVPP2_RX_DATA_FIFO_SIZE_REG(port), 7060 MVPP2_RX_FIFO_PORT_DATA_SIZE_4KB); 7061 mvpp2_write(priv, MVPP2_RX_ATTR_FIFO_SIZE_REG(port), 7062 MVPP2_RX_FIFO_PORT_ATTR_SIZE_4KB); 7063 } 7064 7065 mvpp2_write(priv, MVPP2_RX_MIN_PKT_SIZE_REG, 7066 MVPP2_RX_FIFO_PORT_MIN_PKT); 7067 mvpp2_write(priv, MVPP2_RX_FIFO_INIT_REG, 0x1); 7068 } 7069 7070 static void mvpp22_rx_fifo_set_hw(struct mvpp2 *priv, int port, int data_size) 7071 { 7072 int attr_size = MVPP2_RX_FIFO_PORT_ATTR_SIZE(data_size); 7073 7074 mvpp2_write(priv, MVPP2_RX_DATA_FIFO_SIZE_REG(port), data_size); 7075 mvpp2_write(priv, MVPP2_RX_ATTR_FIFO_SIZE_REG(port), attr_size); 7076 } 7077 7078 /* Initialize TX FIFO's: the total FIFO size is 48kB on PPv2.2 and PPv2.3. 7079 * 4kB fixed space must be assigned for the loopback port. 7080 * Redistribute remaining avialable 44kB space among all active ports. 7081 * Guarantee minimum 32kB for 10G port and 8kB for port 1, capable of 2.5G 7082 * SGMII link. 7083 */ 7084 static void mvpp22_rx_fifo_init(struct mvpp2 *priv) 7085 { 7086 int remaining_ports_count; 7087 unsigned long port_map; 7088 int size_remainder; 7089 int port, size; 7090 7091 /* The loopback requires fixed 4kB of the FIFO space assignment. */ 7092 mvpp22_rx_fifo_set_hw(priv, MVPP2_LOOPBACK_PORT_INDEX, 7093 MVPP2_RX_FIFO_PORT_DATA_SIZE_4KB); 7094 port_map = priv->port_map & ~BIT(MVPP2_LOOPBACK_PORT_INDEX); 7095 7096 /* Set RX FIFO size to 0 for inactive ports. */ 7097 for_each_clear_bit(port, &port_map, MVPP2_LOOPBACK_PORT_INDEX) 7098 mvpp22_rx_fifo_set_hw(priv, port, 0); 7099 7100 /* Assign remaining RX FIFO space among all active ports. */ 7101 size_remainder = MVPP2_RX_FIFO_PORT_DATA_SIZE_44KB; 7102 remaining_ports_count = hweight_long(port_map); 7103 7104 for_each_set_bit(port, &port_map, MVPP2_LOOPBACK_PORT_INDEX) { 7105 if (remaining_ports_count == 1) 7106 size = size_remainder; 7107 else if (port == 0) 7108 size = max(size_remainder / remaining_ports_count, 7109 MVPP2_RX_FIFO_PORT_DATA_SIZE_32KB); 7110 else if (port == 1) 7111 size = max(size_remainder / remaining_ports_count, 7112 MVPP2_RX_FIFO_PORT_DATA_SIZE_8KB); 7113 else 7114 size = size_remainder / remaining_ports_count; 7115 7116 size_remainder -= size; 7117 remaining_ports_count--; 7118 7119 mvpp22_rx_fifo_set_hw(priv, port, size); 7120 } 7121 7122 mvpp2_write(priv, MVPP2_RX_MIN_PKT_SIZE_REG, 7123 MVPP2_RX_FIFO_PORT_MIN_PKT); 7124 mvpp2_write(priv, MVPP2_RX_FIFO_INIT_REG, 0x1); 7125 } 7126 7127 /* Configure Rx FIFO Flow control thresholds */ 7128 static void mvpp23_rx_fifo_fc_set_tresh(struct mvpp2 *priv) 7129 { 7130 int port, val; 7131 7132 /* Port 0: maximum speed -10Gb/s port 7133 * required by spec RX FIFO threshold 9KB 7134 * Port 1: maximum speed -5Gb/s port 7135 * required by spec RX FIFO threshold 4KB 7136 * Port 2: maximum speed -1Gb/s port 7137 * required by spec RX FIFO threshold 2KB 7138 */ 7139 7140 /* Without loopback port */ 7141 for (port = 0; port < (MVPP2_MAX_PORTS - 1); port++) { 7142 if (port == 0) { 7143 val = (MVPP23_PORT0_FIFO_TRSH / MVPP2_RX_FC_TRSH_UNIT) 7144 << MVPP2_RX_FC_TRSH_OFFS; 7145 val &= MVPP2_RX_FC_TRSH_MASK; 7146 mvpp2_write(priv, MVPP2_RX_FC_REG(port), val); 7147 } else if (port == 1) { 7148 val = (MVPP23_PORT1_FIFO_TRSH / MVPP2_RX_FC_TRSH_UNIT) 7149 << MVPP2_RX_FC_TRSH_OFFS; 7150 val &= MVPP2_RX_FC_TRSH_MASK; 7151 mvpp2_write(priv, MVPP2_RX_FC_REG(port), val); 7152 } else { 7153 val = (MVPP23_PORT2_FIFO_TRSH / MVPP2_RX_FC_TRSH_UNIT) 7154 << MVPP2_RX_FC_TRSH_OFFS; 7155 val &= MVPP2_RX_FC_TRSH_MASK; 7156 mvpp2_write(priv, MVPP2_RX_FC_REG(port), val); 7157 } 7158 } 7159 } 7160 7161 /* Configure Rx FIFO Flow control thresholds */ 7162 void mvpp23_rx_fifo_fc_en(struct mvpp2 *priv, int port, bool en) 7163 { 7164 int val; 7165 7166 val = mvpp2_read(priv, MVPP2_RX_FC_REG(port)); 7167 7168 if (en) 7169 val |= MVPP2_RX_FC_EN; 7170 else 7171 val &= ~MVPP2_RX_FC_EN; 7172 7173 mvpp2_write(priv, MVPP2_RX_FC_REG(port), val); 7174 } 7175 7176 static void mvpp22_tx_fifo_set_hw(struct mvpp2 *priv, int port, int size) 7177 { 7178 int threshold = MVPP2_TX_FIFO_THRESHOLD(size); 7179 7180 mvpp2_write(priv, MVPP22_TX_FIFO_SIZE_REG(port), size); 7181 mvpp2_write(priv, MVPP22_TX_FIFO_THRESH_REG(port), threshold); 7182 } 7183 7184 /* Initialize TX FIFO's: the total FIFO size is 19kB on PPv2.2 and PPv2.3. 7185 * 1kB fixed space must be assigned for the loopback port. 7186 * Redistribute remaining avialable 18kB space among all active ports. 7187 * The 10G interface should use 10kB (which is maximum possible size 7188 * per single port). 7189 */ 7190 static void mvpp22_tx_fifo_init(struct mvpp2 *priv) 7191 { 7192 int remaining_ports_count; 7193 unsigned long port_map; 7194 int size_remainder; 7195 int port, size; 7196 7197 /* The loopback requires fixed 1kB of the FIFO space assignment. */ 7198 mvpp22_tx_fifo_set_hw(priv, MVPP2_LOOPBACK_PORT_INDEX, 7199 MVPP22_TX_FIFO_DATA_SIZE_1KB); 7200 port_map = priv->port_map & ~BIT(MVPP2_LOOPBACK_PORT_INDEX); 7201 7202 /* Set TX FIFO size to 0 for inactive ports. */ 7203 for_each_clear_bit(port, &port_map, MVPP2_LOOPBACK_PORT_INDEX) 7204 mvpp22_tx_fifo_set_hw(priv, port, 0); 7205 7206 /* Assign remaining TX FIFO space among all active ports. */ 7207 size_remainder = MVPP22_TX_FIFO_DATA_SIZE_18KB; 7208 remaining_ports_count = hweight_long(port_map); 7209 7210 for_each_set_bit(port, &port_map, MVPP2_LOOPBACK_PORT_INDEX) { 7211 if (remaining_ports_count == 1) 7212 size = min(size_remainder, 7213 MVPP22_TX_FIFO_DATA_SIZE_10KB); 7214 else if (port == 0) 7215 size = MVPP22_TX_FIFO_DATA_SIZE_10KB; 7216 else 7217 size = size_remainder / remaining_ports_count; 7218 7219 size_remainder -= size; 7220 remaining_ports_count--; 7221 7222 mvpp22_tx_fifo_set_hw(priv, port, size); 7223 } 7224 } 7225 7226 static void mvpp2_axi_init(struct mvpp2 *priv) 7227 { 7228 u32 val, rdval, wrval; 7229 7230 mvpp2_write(priv, MVPP22_BM_ADDR_HIGH_RLS_REG, 0x0); 7231 7232 /* AXI Bridge Configuration */ 7233 7234 rdval = MVPP22_AXI_CODE_CACHE_RD_CACHE 7235 << MVPP22_AXI_ATTR_CACHE_OFFS; 7236 rdval |= MVPP22_AXI_CODE_DOMAIN_OUTER_DOM 7237 << MVPP22_AXI_ATTR_DOMAIN_OFFS; 7238 7239 wrval = MVPP22_AXI_CODE_CACHE_WR_CACHE 7240 << MVPP22_AXI_ATTR_CACHE_OFFS; 7241 wrval |= MVPP22_AXI_CODE_DOMAIN_OUTER_DOM 7242 << MVPP22_AXI_ATTR_DOMAIN_OFFS; 7243 7244 /* BM */ 7245 mvpp2_write(priv, MVPP22_AXI_BM_WR_ATTR_REG, wrval); 7246 mvpp2_write(priv, MVPP22_AXI_BM_RD_ATTR_REG, rdval); 7247 7248 /* Descriptors */ 7249 mvpp2_write(priv, MVPP22_AXI_AGGRQ_DESCR_RD_ATTR_REG, rdval); 7250 mvpp2_write(priv, MVPP22_AXI_TXQ_DESCR_WR_ATTR_REG, wrval); 7251 mvpp2_write(priv, MVPP22_AXI_TXQ_DESCR_RD_ATTR_REG, rdval); 7252 mvpp2_write(priv, MVPP22_AXI_RXQ_DESCR_WR_ATTR_REG, wrval); 7253 7254 /* Buffer Data */ 7255 mvpp2_write(priv, MVPP22_AXI_TX_DATA_RD_ATTR_REG, rdval); 7256 mvpp2_write(priv, MVPP22_AXI_RX_DATA_WR_ATTR_REG, wrval); 7257 7258 val = MVPP22_AXI_CODE_CACHE_NON_CACHE 7259 << MVPP22_AXI_CODE_CACHE_OFFS; 7260 val |= MVPP22_AXI_CODE_DOMAIN_SYSTEM 7261 << MVPP22_AXI_CODE_DOMAIN_OFFS; 7262 mvpp2_write(priv, MVPP22_AXI_RD_NORMAL_CODE_REG, val); 7263 mvpp2_write(priv, MVPP22_AXI_WR_NORMAL_CODE_REG, val); 7264 7265 val = MVPP22_AXI_CODE_CACHE_RD_CACHE 7266 << MVPP22_AXI_CODE_CACHE_OFFS; 7267 val |= MVPP22_AXI_CODE_DOMAIN_OUTER_DOM 7268 << MVPP22_AXI_CODE_DOMAIN_OFFS; 7269 7270 mvpp2_write(priv, MVPP22_AXI_RD_SNOOP_CODE_REG, val); 7271 7272 val = MVPP22_AXI_CODE_CACHE_WR_CACHE 7273 << MVPP22_AXI_CODE_CACHE_OFFS; 7274 val |= MVPP22_AXI_CODE_DOMAIN_OUTER_DOM 7275 << MVPP22_AXI_CODE_DOMAIN_OFFS; 7276 7277 mvpp2_write(priv, MVPP22_AXI_WR_SNOOP_CODE_REG, val); 7278 } 7279 7280 /* Initialize network controller common part HW */ 7281 static int mvpp2_init(struct platform_device *pdev, struct mvpp2 *priv) 7282 { 7283 const struct mbus_dram_target_info *dram_target_info; 7284 int err, i; 7285 u32 val; 7286 7287 /* MBUS windows configuration */ 7288 dram_target_info = mv_mbus_dram_info(); 7289 if (dram_target_info) 7290 mvpp2_conf_mbus_windows(dram_target_info, priv); 7291 7292 if (priv->hw_version >= MVPP22) 7293 mvpp2_axi_init(priv); 7294 7295 /* Disable HW PHY polling */ 7296 if (priv->hw_version == MVPP21) { 7297 val = readl(priv->lms_base + MVPP2_PHY_AN_CFG0_REG); 7298 val |= MVPP2_PHY_AN_STOP_SMI0_MASK; 7299 writel(val, priv->lms_base + MVPP2_PHY_AN_CFG0_REG); 7300 } else { 7301 val = readl(priv->iface_base + MVPP22_SMI_MISC_CFG_REG); 7302 val &= ~MVPP22_SMI_POLLING_EN; 7303 writel(val, priv->iface_base + MVPP22_SMI_MISC_CFG_REG); 7304 } 7305 7306 /* Allocate and initialize aggregated TXQs */ 7307 priv->aggr_txqs = devm_kcalloc(&pdev->dev, MVPP2_MAX_THREADS, 7308 sizeof(*priv->aggr_txqs), 7309 GFP_KERNEL); 7310 if (!priv->aggr_txqs) 7311 return -ENOMEM; 7312 7313 for (i = 0; i < MVPP2_MAX_THREADS; i++) { 7314 priv->aggr_txqs[i].id = i; 7315 priv->aggr_txqs[i].size = MVPP2_AGGR_TXQ_SIZE; 7316 err = mvpp2_aggr_txq_init(pdev, &priv->aggr_txqs[i], i, priv); 7317 if (err < 0) 7318 return err; 7319 } 7320 7321 /* Fifo Init */ 7322 if (priv->hw_version == MVPP21) { 7323 mvpp2_rx_fifo_init(priv); 7324 } else { 7325 mvpp22_rx_fifo_init(priv); 7326 mvpp22_tx_fifo_init(priv); 7327 if (priv->hw_version == MVPP23) 7328 mvpp23_rx_fifo_fc_set_tresh(priv); 7329 } 7330 7331 if (priv->hw_version == MVPP21) 7332 writel(MVPP2_EXT_GLOBAL_CTRL_DEFAULT, 7333 priv->lms_base + MVPP2_MNG_EXTENDED_GLOBAL_CTRL_REG); 7334 7335 /* Allow cache snoop when transmiting packets */ 7336 mvpp2_write(priv, MVPP2_TX_SNOOP_REG, 0x1); 7337 7338 /* Buffer Manager initialization */ 7339 err = mvpp2_bm_init(&pdev->dev, priv); 7340 if (err < 0) 7341 return err; 7342 7343 /* Parser default initialization */ 7344 err = mvpp2_prs_default_init(pdev, priv); 7345 if (err < 0) 7346 return err; 7347 7348 /* Classifier default initialization */ 7349 mvpp2_cls_init(priv); 7350 7351 return 0; 7352 } 7353 7354 static int mvpp2_get_sram(struct platform_device *pdev, 7355 struct mvpp2 *priv) 7356 { 7357 struct resource *res; 7358 7359 res = platform_get_resource(pdev, IORESOURCE_MEM, 2); 7360 if (!res) { 7361 if (has_acpi_companion(&pdev->dev)) 7362 dev_warn(&pdev->dev, "ACPI is too old, Flow control not supported\n"); 7363 else 7364 dev_warn(&pdev->dev, "DT is too old, Flow control not supported\n"); 7365 return 0; 7366 } 7367 7368 priv->cm3_base = devm_ioremap_resource(&pdev->dev, res); 7369 7370 return PTR_ERR_OR_ZERO(priv->cm3_base); 7371 } 7372 7373 static int mvpp2_probe(struct platform_device *pdev) 7374 { 7375 struct fwnode_handle *fwnode = pdev->dev.fwnode; 7376 struct fwnode_handle *port_fwnode; 7377 struct mvpp2 *priv; 7378 struct resource *res; 7379 void __iomem *base; 7380 int i, shared; 7381 int err; 7382 7383 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); 7384 if (!priv) 7385 return -ENOMEM; 7386 7387 priv->hw_version = (unsigned long)device_get_match_data(&pdev->dev); 7388 7389 /* multi queue mode isn't supported on PPV2.1, fallback to single 7390 * mode 7391 */ 7392 if (priv->hw_version == MVPP21) 7393 queue_mode = MVPP2_QDIST_SINGLE_MODE; 7394 7395 base = devm_platform_ioremap_resource(pdev, 0); 7396 if (IS_ERR(base)) 7397 return PTR_ERR(base); 7398 7399 if (priv->hw_version == MVPP21) { 7400 priv->lms_base = devm_platform_ioremap_resource(pdev, 1); 7401 if (IS_ERR(priv->lms_base)) 7402 return PTR_ERR(priv->lms_base); 7403 } else { 7404 res = platform_get_resource(pdev, IORESOURCE_MEM, 1); 7405 if (!res) { 7406 dev_err(&pdev->dev, "Invalid resource\n"); 7407 return -EINVAL; 7408 } 7409 if (has_acpi_companion(&pdev->dev)) { 7410 /* In case the MDIO memory region is declared in 7411 * the ACPI, it can already appear as 'in-use' 7412 * in the OS. Because it is overlapped by second 7413 * region of the network controller, make 7414 * sure it is released, before requesting it again. 7415 * The care is taken by mvpp2 driver to avoid 7416 * concurrent access to this memory region. 7417 */ 7418 release_resource(res); 7419 } 7420 priv->iface_base = devm_ioremap_resource(&pdev->dev, res); 7421 if (IS_ERR(priv->iface_base)) 7422 return PTR_ERR(priv->iface_base); 7423 7424 /* Map CM3 SRAM */ 7425 err = mvpp2_get_sram(pdev, priv); 7426 if (err) 7427 dev_warn(&pdev->dev, "Fail to alloc CM3 SRAM\n"); 7428 7429 /* Enable global Flow Control only if handler to SRAM not NULL */ 7430 if (priv->cm3_base) 7431 priv->global_tx_fc = true; 7432 } 7433 7434 if (priv->hw_version >= MVPP22 && dev_of_node(&pdev->dev)) { 7435 priv->sysctrl_base = 7436 syscon_regmap_lookup_by_phandle(pdev->dev.of_node, 7437 "marvell,system-controller"); 7438 if (IS_ERR(priv->sysctrl_base)) 7439 /* The system controller regmap is optional for dt 7440 * compatibility reasons. When not provided, the 7441 * configuration of the GoP relies on the 7442 * firmware/bootloader. 7443 */ 7444 priv->sysctrl_base = NULL; 7445 } 7446 7447 if (priv->hw_version >= MVPP22 && 7448 mvpp2_get_nrxqs(priv) * 2 <= MVPP2_BM_MAX_POOLS) 7449 priv->percpu_pools = 1; 7450 7451 mvpp2_setup_bm_pool(); 7452 7453 7454 priv->nthreads = min_t(unsigned int, num_present_cpus(), 7455 MVPP2_MAX_THREADS); 7456 7457 shared = num_present_cpus() - priv->nthreads; 7458 if (shared > 0) 7459 bitmap_fill(&priv->lock_map, 7460 min_t(int, shared, MVPP2_MAX_THREADS)); 7461 7462 for (i = 0; i < MVPP2_MAX_THREADS; i++) { 7463 u32 addr_space_sz; 7464 7465 addr_space_sz = (priv->hw_version == MVPP21 ? 7466 MVPP21_ADDR_SPACE_SZ : MVPP22_ADDR_SPACE_SZ); 7467 priv->swth_base[i] = base + i * addr_space_sz; 7468 } 7469 7470 if (priv->hw_version == MVPP21) 7471 priv->max_port_rxqs = 8; 7472 else 7473 priv->max_port_rxqs = 32; 7474 7475 if (dev_of_node(&pdev->dev)) { 7476 priv->pp_clk = devm_clk_get(&pdev->dev, "pp_clk"); 7477 if (IS_ERR(priv->pp_clk)) 7478 return PTR_ERR(priv->pp_clk); 7479 err = clk_prepare_enable(priv->pp_clk); 7480 if (err < 0) 7481 return err; 7482 7483 priv->gop_clk = devm_clk_get(&pdev->dev, "gop_clk"); 7484 if (IS_ERR(priv->gop_clk)) { 7485 err = PTR_ERR(priv->gop_clk); 7486 goto err_pp_clk; 7487 } 7488 err = clk_prepare_enable(priv->gop_clk); 7489 if (err < 0) 7490 goto err_pp_clk; 7491 7492 if (priv->hw_version >= MVPP22) { 7493 priv->mg_clk = devm_clk_get(&pdev->dev, "mg_clk"); 7494 if (IS_ERR(priv->mg_clk)) { 7495 err = PTR_ERR(priv->mg_clk); 7496 goto err_gop_clk; 7497 } 7498 7499 err = clk_prepare_enable(priv->mg_clk); 7500 if (err < 0) 7501 goto err_gop_clk; 7502 7503 priv->mg_core_clk = devm_clk_get_optional(&pdev->dev, "mg_core_clk"); 7504 if (IS_ERR(priv->mg_core_clk)) { 7505 err = PTR_ERR(priv->mg_core_clk); 7506 goto err_mg_clk; 7507 } 7508 7509 err = clk_prepare_enable(priv->mg_core_clk); 7510 if (err < 0) 7511 goto err_mg_clk; 7512 } 7513 7514 priv->axi_clk = devm_clk_get_optional(&pdev->dev, "axi_clk"); 7515 if (IS_ERR(priv->axi_clk)) { 7516 err = PTR_ERR(priv->axi_clk); 7517 goto err_mg_core_clk; 7518 } 7519 7520 err = clk_prepare_enable(priv->axi_clk); 7521 if (err < 0) 7522 goto err_mg_core_clk; 7523 7524 /* Get system's tclk rate */ 7525 priv->tclk = clk_get_rate(priv->pp_clk); 7526 } else { 7527 err = device_property_read_u32(&pdev->dev, "clock-frequency", &priv->tclk); 7528 if (err) { 7529 dev_err(&pdev->dev, "missing clock-frequency value\n"); 7530 return err; 7531 } 7532 } 7533 7534 if (priv->hw_version >= MVPP22) { 7535 err = dma_set_mask(&pdev->dev, MVPP2_DESC_DMA_MASK); 7536 if (err) 7537 goto err_axi_clk; 7538 /* Sadly, the BM pools all share the same register to 7539 * store the high 32 bits of their address. So they 7540 * must all have the same high 32 bits, which forces 7541 * us to restrict coherent memory to DMA_BIT_MASK(32). 7542 */ 7543 err = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32)); 7544 if (err) 7545 goto err_axi_clk; 7546 } 7547 7548 /* Map DTS-active ports. Should be done before FIFO mvpp2_init */ 7549 fwnode_for_each_available_child_node(fwnode, port_fwnode) { 7550 if (!fwnode_property_read_u32(port_fwnode, "port-id", &i)) 7551 priv->port_map |= BIT(i); 7552 } 7553 7554 if (mvpp2_read(priv, MVPP2_VER_ID_REG) == MVPP2_VER_PP23) 7555 priv->hw_version = MVPP23; 7556 7557 /* Init mss lock */ 7558 spin_lock_init(&priv->mss_spinlock); 7559 7560 /* Initialize network controller */ 7561 err = mvpp2_init(pdev, priv); 7562 if (err < 0) { 7563 dev_err(&pdev->dev, "failed to initialize controller\n"); 7564 goto err_axi_clk; 7565 } 7566 7567 err = mvpp22_tai_probe(&pdev->dev, priv); 7568 if (err < 0) 7569 goto err_axi_clk; 7570 7571 /* Initialize ports */ 7572 fwnode_for_each_available_child_node(fwnode, port_fwnode) { 7573 err = mvpp2_port_probe(pdev, port_fwnode, priv); 7574 if (err < 0) 7575 goto err_port_probe; 7576 } 7577 7578 if (priv->port_count == 0) { 7579 dev_err(&pdev->dev, "no ports enabled\n"); 7580 err = -ENODEV; 7581 goto err_axi_clk; 7582 } 7583 7584 /* Statistics must be gathered regularly because some of them (like 7585 * packets counters) are 32-bit registers and could overflow quite 7586 * quickly. For instance, a 10Gb link used at full bandwidth with the 7587 * smallest packets (64B) will overflow a 32-bit counter in less than 7588 * 30 seconds. Then, use a workqueue to fill 64-bit counters. 7589 */ 7590 snprintf(priv->queue_name, sizeof(priv->queue_name), 7591 "stats-wq-%s%s", netdev_name(priv->port_list[0]->dev), 7592 priv->port_count > 1 ? "+" : ""); 7593 priv->stats_queue = create_singlethread_workqueue(priv->queue_name); 7594 if (!priv->stats_queue) { 7595 err = -ENOMEM; 7596 goto err_port_probe; 7597 } 7598 7599 if (priv->global_tx_fc && priv->hw_version >= MVPP22) { 7600 err = mvpp2_enable_global_fc(priv); 7601 if (err) 7602 dev_warn(&pdev->dev, "Minimum of CM3 firmware 18.09 and chip revision B0 required for flow control\n"); 7603 } 7604 7605 mvpp2_dbgfs_init(priv, pdev->name); 7606 7607 platform_set_drvdata(pdev, priv); 7608 return 0; 7609 7610 err_port_probe: 7611 fwnode_handle_put(port_fwnode); 7612 7613 i = 0; 7614 fwnode_for_each_available_child_node(fwnode, port_fwnode) { 7615 if (priv->port_list[i]) 7616 mvpp2_port_remove(priv->port_list[i]); 7617 i++; 7618 } 7619 err_axi_clk: 7620 clk_disable_unprepare(priv->axi_clk); 7621 err_mg_core_clk: 7622 clk_disable_unprepare(priv->mg_core_clk); 7623 err_mg_clk: 7624 clk_disable_unprepare(priv->mg_clk); 7625 err_gop_clk: 7626 clk_disable_unprepare(priv->gop_clk); 7627 err_pp_clk: 7628 clk_disable_unprepare(priv->pp_clk); 7629 return err; 7630 } 7631 7632 static int mvpp2_remove(struct platform_device *pdev) 7633 { 7634 struct mvpp2 *priv = platform_get_drvdata(pdev); 7635 struct fwnode_handle *fwnode = pdev->dev.fwnode; 7636 int i = 0, poolnum = MVPP2_BM_POOLS_NUM; 7637 struct fwnode_handle *port_fwnode; 7638 7639 mvpp2_dbgfs_cleanup(priv); 7640 7641 fwnode_for_each_available_child_node(fwnode, port_fwnode) { 7642 if (priv->port_list[i]) { 7643 mutex_destroy(&priv->port_list[i]->gather_stats_lock); 7644 mvpp2_port_remove(priv->port_list[i]); 7645 } 7646 i++; 7647 } 7648 7649 destroy_workqueue(priv->stats_queue); 7650 7651 if (priv->percpu_pools) 7652 poolnum = mvpp2_get_nrxqs(priv) * 2; 7653 7654 for (i = 0; i < poolnum; i++) { 7655 struct mvpp2_bm_pool *bm_pool = &priv->bm_pools[i]; 7656 7657 mvpp2_bm_pool_destroy(&pdev->dev, priv, bm_pool); 7658 } 7659 7660 for (i = 0; i < MVPP2_MAX_THREADS; i++) { 7661 struct mvpp2_tx_queue *aggr_txq = &priv->aggr_txqs[i]; 7662 7663 dma_free_coherent(&pdev->dev, 7664 MVPP2_AGGR_TXQ_SIZE * MVPP2_DESC_ALIGNED_SIZE, 7665 aggr_txq->descs, 7666 aggr_txq->descs_dma); 7667 } 7668 7669 if (is_acpi_node(port_fwnode)) 7670 return 0; 7671 7672 clk_disable_unprepare(priv->axi_clk); 7673 clk_disable_unprepare(priv->mg_core_clk); 7674 clk_disable_unprepare(priv->mg_clk); 7675 clk_disable_unprepare(priv->pp_clk); 7676 clk_disable_unprepare(priv->gop_clk); 7677 7678 return 0; 7679 } 7680 7681 static const struct of_device_id mvpp2_match[] = { 7682 { 7683 .compatible = "marvell,armada-375-pp2", 7684 .data = (void *)MVPP21, 7685 }, 7686 { 7687 .compatible = "marvell,armada-7k-pp22", 7688 .data = (void *)MVPP22, 7689 }, 7690 { } 7691 }; 7692 MODULE_DEVICE_TABLE(of, mvpp2_match); 7693 7694 #ifdef CONFIG_ACPI 7695 static const struct acpi_device_id mvpp2_acpi_match[] = { 7696 { "MRVL0110", MVPP22 }, 7697 { }, 7698 }; 7699 MODULE_DEVICE_TABLE(acpi, mvpp2_acpi_match); 7700 #endif 7701 7702 static struct platform_driver mvpp2_driver = { 7703 .probe = mvpp2_probe, 7704 .remove = mvpp2_remove, 7705 .driver = { 7706 .name = MVPP2_DRIVER_NAME, 7707 .of_match_table = mvpp2_match, 7708 .acpi_match_table = ACPI_PTR(mvpp2_acpi_match), 7709 }, 7710 }; 7711 7712 module_platform_driver(mvpp2_driver); 7713 7714 MODULE_DESCRIPTION("Marvell PPv2 Ethernet Driver - www.marvell.com"); 7715 MODULE_AUTHOR("Marcin Wojtas <mw@semihalf.com>"); 7716 MODULE_LICENSE("GPL v2"); 7717