1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Definitions for Marvell PPv2 network controller for Armada 375 SoC. 4 * 5 * Copyright (C) 2014 Marvell 6 * 7 * Marcin Wojtas <mw@semihalf.com> 8 */ 9 #ifndef _MVPP2_H_ 10 #define _MVPP2_H_ 11 12 #include <linux/interrupt.h> 13 #include <linux/kernel.h> 14 #include <linux/netdevice.h> 15 #include <linux/net_tstamp.h> 16 #include <linux/phy.h> 17 #include <linux/phylink.h> 18 #include <net/flow_offload.h> 19 #include <net/page_pool.h> 20 #include <linux/bpf.h> 21 #include <net/xdp.h> 22 23 /* The PacketOffset field is measured in units of 32 bytes and is 3 bits wide, 24 * so the maximum offset is 7 * 32 = 224 25 */ 26 #define MVPP2_SKB_HEADROOM min(max(XDP_PACKET_HEADROOM, NET_SKB_PAD), 224) 27 28 #define MVPP2_XDP_PASS 0 29 #define MVPP2_XDP_DROPPED BIT(0) 30 #define MVPP2_XDP_TX BIT(1) 31 #define MVPP2_XDP_REDIR BIT(2) 32 33 /* Fifo Registers */ 34 #define MVPP2_RX_DATA_FIFO_SIZE_REG(port) (0x00 + 4 * (port)) 35 #define MVPP2_RX_ATTR_FIFO_SIZE_REG(port) (0x20 + 4 * (port)) 36 #define MVPP2_RX_MIN_PKT_SIZE_REG 0x60 37 #define MVPP2_RX_FIFO_INIT_REG 0x64 38 #define MVPP22_TX_FIFO_THRESH_REG(port) (0x8840 + 4 * (port)) 39 #define MVPP22_TX_FIFO_SIZE_REG(port) (0x8860 + 4 * (port)) 40 41 /* RX DMA Top Registers */ 42 #define MVPP2_RX_CTRL_REG(port) (0x140 + 4 * (port)) 43 #define MVPP2_RX_LOW_LATENCY_PKT_SIZE(s) (((s) & 0xfff) << 16) 44 #define MVPP2_RX_USE_PSEUDO_FOR_CSUM_MASK BIT(31) 45 #define MVPP2_POOL_BUF_SIZE_REG(pool) (0x180 + 4 * (pool)) 46 #define MVPP2_POOL_BUF_SIZE_OFFSET 5 47 #define MVPP2_RXQ_CONFIG_REG(rxq) (0x800 + 4 * (rxq)) 48 #define MVPP2_SNOOP_PKT_SIZE_MASK 0x1ff 49 #define MVPP2_SNOOP_BUF_HDR_MASK BIT(9) 50 #define MVPP2_RXQ_POOL_SHORT_OFFS 20 51 #define MVPP21_RXQ_POOL_SHORT_MASK 0x700000 52 #define MVPP22_RXQ_POOL_SHORT_MASK 0xf00000 53 #define MVPP2_RXQ_POOL_LONG_OFFS 24 54 #define MVPP21_RXQ_POOL_LONG_MASK 0x7000000 55 #define MVPP22_RXQ_POOL_LONG_MASK 0xf000000 56 #define MVPP2_RXQ_PACKET_OFFSET_OFFS 28 57 #define MVPP2_RXQ_PACKET_OFFSET_MASK 0x70000000 58 #define MVPP2_RXQ_DISABLE_MASK BIT(31) 59 60 /* Top Registers */ 61 #define MVPP2_MH_REG(port) (0x5040 + 4 * (port)) 62 #define MVPP2_DSA_EXTENDED BIT(5) 63 64 /* Parser Registers */ 65 #define MVPP2_PRS_INIT_LOOKUP_REG 0x1000 66 #define MVPP2_PRS_PORT_LU_MAX 0xf 67 #define MVPP2_PRS_PORT_LU_MASK(port) (0xff << ((port) * 4)) 68 #define MVPP2_PRS_PORT_LU_VAL(port, val) ((val) << ((port) * 4)) 69 #define MVPP2_PRS_INIT_OFFS_REG(port) (0x1004 + ((port) & 4)) 70 #define MVPP2_PRS_INIT_OFF_MASK(port) (0x3f << (((port) % 4) * 8)) 71 #define MVPP2_PRS_INIT_OFF_VAL(port, val) ((val) << (((port) % 4) * 8)) 72 #define MVPP2_PRS_MAX_LOOP_REG(port) (0x100c + ((port) & 4)) 73 #define MVPP2_PRS_MAX_LOOP_MASK(port) (0xff << (((port) % 4) * 8)) 74 #define MVPP2_PRS_MAX_LOOP_VAL(port, val) ((val) << (((port) % 4) * 8)) 75 #define MVPP2_PRS_TCAM_IDX_REG 0x1100 76 #define MVPP2_PRS_TCAM_DATA_REG(idx) (0x1104 + (idx) * 4) 77 #define MVPP2_PRS_TCAM_INV_MASK BIT(31) 78 #define MVPP2_PRS_SRAM_IDX_REG 0x1200 79 #define MVPP2_PRS_SRAM_DATA_REG(idx) (0x1204 + (idx) * 4) 80 #define MVPP2_PRS_TCAM_CTRL_REG 0x1230 81 #define MVPP2_PRS_TCAM_EN_MASK BIT(0) 82 #define MVPP2_PRS_TCAM_HIT_IDX_REG 0x1240 83 #define MVPP2_PRS_TCAM_HIT_CNT_REG 0x1244 84 #define MVPP2_PRS_TCAM_HIT_CNT_MASK GENMASK(15, 0) 85 86 /* RSS Registers */ 87 #define MVPP22_RSS_INDEX 0x1500 88 #define MVPP22_RSS_INDEX_TABLE_ENTRY(idx) (idx) 89 #define MVPP22_RSS_INDEX_TABLE(idx) ((idx) << 8) 90 #define MVPP22_RSS_INDEX_QUEUE(idx) ((idx) << 16) 91 #define MVPP22_RXQ2RSS_TABLE 0x1504 92 #define MVPP22_RSS_TABLE_POINTER(p) (p) 93 #define MVPP22_RSS_TABLE_ENTRY 0x1508 94 #define MVPP22_RSS_WIDTH 0x150c 95 96 /* Classifier Registers */ 97 #define MVPP2_CLS_MODE_REG 0x1800 98 #define MVPP2_CLS_MODE_ACTIVE_MASK BIT(0) 99 #define MVPP2_CLS_PORT_WAY_REG 0x1810 100 #define MVPP2_CLS_PORT_WAY_MASK(port) (1 << (port)) 101 #define MVPP2_CLS_LKP_INDEX_REG 0x1814 102 #define MVPP2_CLS_LKP_INDEX_WAY_OFFS 6 103 #define MVPP2_CLS_LKP_TBL_REG 0x1818 104 #define MVPP2_CLS_LKP_TBL_RXQ_MASK 0xff 105 #define MVPP2_CLS_LKP_FLOW_PTR(flow) ((flow) << 16) 106 #define MVPP2_CLS_LKP_TBL_LOOKUP_EN_MASK BIT(25) 107 #define MVPP2_CLS_FLOW_INDEX_REG 0x1820 108 #define MVPP2_CLS_FLOW_TBL0_REG 0x1824 109 #define MVPP2_CLS_FLOW_TBL0_LAST BIT(0) 110 #define MVPP2_CLS_FLOW_TBL0_ENG_MASK 0x7 111 #define MVPP2_CLS_FLOW_TBL0_OFFS 1 112 #define MVPP2_CLS_FLOW_TBL0_ENG(x) ((x) << 1) 113 #define MVPP2_CLS_FLOW_TBL0_PORT_ID_MASK 0xff 114 #define MVPP2_CLS_FLOW_TBL0_PORT_ID(port) ((port) << 4) 115 #define MVPP2_CLS_FLOW_TBL0_PORT_ID_SEL BIT(23) 116 #define MVPP2_CLS_FLOW_TBL1_REG 0x1828 117 #define MVPP2_CLS_FLOW_TBL1_N_FIELDS_MASK 0x7 118 #define MVPP2_CLS_FLOW_TBL1_N_FIELDS(x) (x) 119 #define MVPP2_CLS_FLOW_TBL1_LU_TYPE(lu) (((lu) & 0x3f) << 3) 120 #define MVPP2_CLS_FLOW_TBL1_PRIO_MASK 0x3f 121 #define MVPP2_CLS_FLOW_TBL1_PRIO(x) ((x) << 9) 122 #define MVPP2_CLS_FLOW_TBL1_SEQ_MASK 0x7 123 #define MVPP2_CLS_FLOW_TBL1_SEQ(x) ((x) << 15) 124 #define MVPP2_CLS_FLOW_TBL2_REG 0x182c 125 #define MVPP2_CLS_FLOW_TBL2_FLD_MASK 0x3f 126 #define MVPP2_CLS_FLOW_TBL2_FLD_OFFS(n) ((n) * 6) 127 #define MVPP2_CLS_FLOW_TBL2_FLD(n, x) ((x) << ((n) * 6)) 128 #define MVPP2_CLS_OVERSIZE_RXQ_LOW_REG(port) (0x1980 + ((port) * 4)) 129 #define MVPP2_CLS_OVERSIZE_RXQ_LOW_BITS 3 130 #define MVPP2_CLS_OVERSIZE_RXQ_LOW_MASK 0x7 131 #define MVPP2_CLS_SWFWD_P2HQ_REG(port) (0x19b0 + ((port) * 4)) 132 #define MVPP2_CLS_SWFWD_PCTRL_REG 0x19d0 133 #define MVPP2_CLS_SWFWD_PCTRL_MASK(port) (1 << (port)) 134 135 /* Classifier C2 engine Registers */ 136 #define MVPP22_CLS_C2_TCAM_IDX 0x1b00 137 #define MVPP22_CLS_C2_TCAM_DATA0 0x1b10 138 #define MVPP22_CLS_C2_TCAM_DATA1 0x1b14 139 #define MVPP22_CLS_C2_TCAM_DATA2 0x1b18 140 #define MVPP22_CLS_C2_TCAM_DATA3 0x1b1c 141 #define MVPP22_CLS_C2_TCAM_DATA4 0x1b20 142 #define MVPP22_CLS_C2_LU_TYPE(lu) ((lu) & 0x3f) 143 #define MVPP22_CLS_C2_PORT_ID(port) ((port) << 8) 144 #define MVPP22_CLS_C2_PORT_MASK (0xff << 8) 145 #define MVPP22_CLS_C2_TCAM_INV 0x1b24 146 #define MVPP22_CLS_C2_TCAM_INV_BIT BIT(31) 147 #define MVPP22_CLS_C2_HIT_CTR 0x1b50 148 #define MVPP22_CLS_C2_ACT 0x1b60 149 #define MVPP22_CLS_C2_ACT_RSS_EN(act) (((act) & 0x3) << 19) 150 #define MVPP22_CLS_C2_ACT_FWD(act) (((act) & 0x7) << 13) 151 #define MVPP22_CLS_C2_ACT_QHIGH(act) (((act) & 0x3) << 11) 152 #define MVPP22_CLS_C2_ACT_QLOW(act) (((act) & 0x3) << 9) 153 #define MVPP22_CLS_C2_ACT_COLOR(act) ((act) & 0x7) 154 #define MVPP22_CLS_C2_ATTR0 0x1b64 155 #define MVPP22_CLS_C2_ATTR0_QHIGH(qh) (((qh) & 0x1f) << 24) 156 #define MVPP22_CLS_C2_ATTR0_QHIGH_MASK 0x1f 157 #define MVPP22_CLS_C2_ATTR0_QHIGH_OFFS 24 158 #define MVPP22_CLS_C2_ATTR0_QLOW(ql) (((ql) & 0x7) << 21) 159 #define MVPP22_CLS_C2_ATTR0_QLOW_MASK 0x7 160 #define MVPP22_CLS_C2_ATTR0_QLOW_OFFS 21 161 #define MVPP22_CLS_C2_ATTR1 0x1b68 162 #define MVPP22_CLS_C2_ATTR2 0x1b6c 163 #define MVPP22_CLS_C2_ATTR2_RSS_EN BIT(30) 164 #define MVPP22_CLS_C2_ATTR3 0x1b70 165 #define MVPP22_CLS_C2_TCAM_CTRL 0x1b90 166 #define MVPP22_CLS_C2_TCAM_BYPASS_FIFO BIT(0) 167 168 /* Descriptor Manager Top Registers */ 169 #define MVPP2_RXQ_NUM_REG 0x2040 170 #define MVPP2_RXQ_DESC_ADDR_REG 0x2044 171 #define MVPP22_DESC_ADDR_OFFS 8 172 #define MVPP2_RXQ_DESC_SIZE_REG 0x2048 173 #define MVPP2_RXQ_DESC_SIZE_MASK 0x3ff0 174 #define MVPP2_RXQ_STATUS_UPDATE_REG(rxq) (0x3000 + 4 * (rxq)) 175 #define MVPP2_RXQ_NUM_PROCESSED_OFFSET 0 176 #define MVPP2_RXQ_NUM_NEW_OFFSET 16 177 #define MVPP2_RXQ_STATUS_REG(rxq) (0x3400 + 4 * (rxq)) 178 #define MVPP2_RXQ_OCCUPIED_MASK 0x3fff 179 #define MVPP2_RXQ_NON_OCCUPIED_OFFSET 16 180 #define MVPP2_RXQ_NON_OCCUPIED_MASK 0x3fff0000 181 #define MVPP2_RXQ_THRESH_REG 0x204c 182 #define MVPP2_OCCUPIED_THRESH_OFFSET 0 183 #define MVPP2_OCCUPIED_THRESH_MASK 0x3fff 184 #define MVPP2_RXQ_INDEX_REG 0x2050 185 #define MVPP2_TXQ_NUM_REG 0x2080 186 #define MVPP2_TXQ_DESC_ADDR_REG 0x2084 187 #define MVPP2_TXQ_DESC_SIZE_REG 0x2088 188 #define MVPP2_TXQ_DESC_SIZE_MASK 0x3ff0 189 #define MVPP2_TXQ_THRESH_REG 0x2094 190 #define MVPP2_TXQ_THRESH_OFFSET 16 191 #define MVPP2_TXQ_THRESH_MASK 0x3fff 192 #define MVPP2_AGGR_TXQ_UPDATE_REG 0x2090 193 #define MVPP2_TXQ_INDEX_REG 0x2098 194 #define MVPP2_TXQ_PREF_BUF_REG 0x209c 195 #define MVPP2_PREF_BUF_PTR(desc) ((desc) & 0xfff) 196 #define MVPP2_PREF_BUF_SIZE_4 (BIT(12) | BIT(13)) 197 #define MVPP2_PREF_BUF_SIZE_16 (BIT(12) | BIT(14)) 198 #define MVPP2_PREF_BUF_THRESH(val) ((val) << 17) 199 #define MVPP2_TXQ_DRAIN_EN_MASK BIT(31) 200 #define MVPP2_TXQ_PENDING_REG 0x20a0 201 #define MVPP2_TXQ_PENDING_MASK 0x3fff 202 #define MVPP2_TXQ_INT_STATUS_REG 0x20a4 203 #define MVPP2_TXQ_SENT_REG(txq) (0x3c00 + 4 * (txq)) 204 #define MVPP2_TRANSMITTED_COUNT_OFFSET 16 205 #define MVPP2_TRANSMITTED_COUNT_MASK 0x3fff0000 206 #define MVPP2_TXQ_RSVD_REQ_REG 0x20b0 207 #define MVPP2_TXQ_RSVD_REQ_Q_OFFSET 16 208 #define MVPP2_TXQ_RSVD_RSLT_REG 0x20b4 209 #define MVPP2_TXQ_RSVD_RSLT_MASK 0x3fff 210 #define MVPP2_TXQ_RSVD_CLR_REG 0x20b8 211 #define MVPP2_TXQ_RSVD_CLR_OFFSET 16 212 #define MVPP2_AGGR_TXQ_DESC_ADDR_REG(cpu) (0x2100 + 4 * (cpu)) 213 #define MVPP22_AGGR_TXQ_DESC_ADDR_OFFS 8 214 #define MVPP2_AGGR_TXQ_DESC_SIZE_REG(cpu) (0x2140 + 4 * (cpu)) 215 #define MVPP2_AGGR_TXQ_DESC_SIZE_MASK 0x3ff0 216 #define MVPP2_AGGR_TXQ_STATUS_REG(cpu) (0x2180 + 4 * (cpu)) 217 #define MVPP2_AGGR_TXQ_PENDING_MASK 0x3fff 218 #define MVPP2_AGGR_TXQ_INDEX_REG(cpu) (0x21c0 + 4 * (cpu)) 219 220 /* MBUS bridge registers */ 221 #define MVPP2_WIN_BASE(w) (0x4000 + ((w) << 2)) 222 #define MVPP2_WIN_SIZE(w) (0x4020 + ((w) << 2)) 223 #define MVPP2_WIN_REMAP(w) (0x4040 + ((w) << 2)) 224 #define MVPP2_BASE_ADDR_ENABLE 0x4060 225 226 /* AXI Bridge Registers */ 227 #define MVPP22_AXI_BM_WR_ATTR_REG 0x4100 228 #define MVPP22_AXI_BM_RD_ATTR_REG 0x4104 229 #define MVPP22_AXI_AGGRQ_DESCR_RD_ATTR_REG 0x4110 230 #define MVPP22_AXI_TXQ_DESCR_WR_ATTR_REG 0x4114 231 #define MVPP22_AXI_TXQ_DESCR_RD_ATTR_REG 0x4118 232 #define MVPP22_AXI_RXQ_DESCR_WR_ATTR_REG 0x411c 233 #define MVPP22_AXI_RX_DATA_WR_ATTR_REG 0x4120 234 #define MVPP22_AXI_TX_DATA_RD_ATTR_REG 0x4130 235 #define MVPP22_AXI_RD_NORMAL_CODE_REG 0x4150 236 #define MVPP22_AXI_RD_SNOOP_CODE_REG 0x4154 237 #define MVPP22_AXI_WR_NORMAL_CODE_REG 0x4160 238 #define MVPP22_AXI_WR_SNOOP_CODE_REG 0x4164 239 240 /* Values for AXI Bridge registers */ 241 #define MVPP22_AXI_ATTR_CACHE_OFFS 0 242 #define MVPP22_AXI_ATTR_DOMAIN_OFFS 12 243 244 #define MVPP22_AXI_CODE_CACHE_OFFS 0 245 #define MVPP22_AXI_CODE_DOMAIN_OFFS 4 246 247 #define MVPP22_AXI_CODE_CACHE_NON_CACHE 0x3 248 #define MVPP22_AXI_CODE_CACHE_WR_CACHE 0x7 249 #define MVPP22_AXI_CODE_CACHE_RD_CACHE 0xb 250 251 #define MVPP22_AXI_CODE_DOMAIN_OUTER_DOM 2 252 #define MVPP22_AXI_CODE_DOMAIN_SYSTEM 3 253 254 /* Interrupt Cause and Mask registers */ 255 #define MVPP2_ISR_TX_THRESHOLD_REG(port) (0x5140 + 4 * (port)) 256 #define MVPP2_MAX_ISR_TX_THRESHOLD 0xfffff0 257 258 #define MVPP2_ISR_RX_THRESHOLD_REG(rxq) (0x5200 + 4 * (rxq)) 259 #define MVPP2_MAX_ISR_RX_THRESHOLD 0xfffff0 260 #define MVPP21_ISR_RXQ_GROUP_REG(port) (0x5400 + 4 * (port)) 261 262 #define MVPP22_ISR_RXQ_GROUP_INDEX_REG 0x5400 263 #define MVPP22_ISR_RXQ_GROUP_INDEX_SUBGROUP_MASK 0xf 264 #define MVPP22_ISR_RXQ_GROUP_INDEX_GROUP_MASK 0x380 265 #define MVPP22_ISR_RXQ_GROUP_INDEX_GROUP_OFFSET 7 266 267 #define MVPP22_ISR_RXQ_GROUP_INDEX_SUBGROUP_MASK 0xf 268 #define MVPP22_ISR_RXQ_GROUP_INDEX_GROUP_MASK 0x380 269 270 #define MVPP22_ISR_RXQ_SUB_GROUP_CONFIG_REG 0x5404 271 #define MVPP22_ISR_RXQ_SUB_GROUP_STARTQ_MASK 0x1f 272 #define MVPP22_ISR_RXQ_SUB_GROUP_SIZE_MASK 0xf00 273 #define MVPP22_ISR_RXQ_SUB_GROUP_SIZE_OFFSET 8 274 275 #define MVPP2_ISR_ENABLE_REG(port) (0x5420 + 4 * (port)) 276 #define MVPP2_ISR_ENABLE_INTERRUPT(mask) ((mask) & 0xffff) 277 #define MVPP2_ISR_DISABLE_INTERRUPT(mask) (((mask) << 16) & 0xffff0000) 278 #define MVPP2_ISR_RX_TX_CAUSE_REG(port) (0x5480 + 4 * (port)) 279 #define MVPP2_CAUSE_RXQ_OCCUP_DESC_ALL_MASK(version) \ 280 ((version) == MVPP21 ? 0xffff : 0xff) 281 #define MVPP2_CAUSE_TXQ_OCCUP_DESC_ALL_MASK 0xff0000 282 #define MVPP2_CAUSE_TXQ_OCCUP_DESC_ALL_OFFSET 16 283 #define MVPP2_CAUSE_RX_FIFO_OVERRUN_MASK BIT(24) 284 #define MVPP2_CAUSE_FCS_ERR_MASK BIT(25) 285 #define MVPP2_CAUSE_TX_FIFO_UNDERRUN_MASK BIT(26) 286 #define MVPP2_CAUSE_TX_EXCEPTION_SUM_MASK BIT(29) 287 #define MVPP2_CAUSE_RX_EXCEPTION_SUM_MASK BIT(30) 288 #define MVPP2_CAUSE_MISC_SUM_MASK BIT(31) 289 #define MVPP2_ISR_RX_TX_MASK_REG(port) (0x54a0 + 4 * (port)) 290 #define MVPP2_ISR_PON_RX_TX_MASK_REG 0x54bc 291 #define MVPP2_PON_CAUSE_RXQ_OCCUP_DESC_ALL_MASK 0xffff 292 #define MVPP2_PON_CAUSE_TXP_OCCUP_DESC_ALL_MASK 0x3fc00000 293 #define MVPP2_PON_CAUSE_MISC_SUM_MASK BIT(31) 294 #define MVPP2_ISR_MISC_CAUSE_REG 0x55b0 295 296 /* Buffer Manager registers */ 297 #define MVPP2_BM_POOL_BASE_REG(pool) (0x6000 + ((pool) * 4)) 298 #define MVPP2_BM_POOL_BASE_ADDR_MASK 0xfffff80 299 #define MVPP2_BM_POOL_SIZE_REG(pool) (0x6040 + ((pool) * 4)) 300 #define MVPP2_BM_POOL_SIZE_MASK 0xfff0 301 #define MVPP2_BM_POOL_READ_PTR_REG(pool) (0x6080 + ((pool) * 4)) 302 #define MVPP2_BM_POOL_GET_READ_PTR_MASK 0xfff0 303 #define MVPP2_BM_POOL_PTRS_NUM_REG(pool) (0x60c0 + ((pool) * 4)) 304 #define MVPP2_BM_POOL_PTRS_NUM_MASK 0xfff0 305 #define MVPP2_BM_BPPI_READ_PTR_REG(pool) (0x6100 + ((pool) * 4)) 306 #define MVPP2_BM_BPPI_PTRS_NUM_REG(pool) (0x6140 + ((pool) * 4)) 307 #define MVPP2_BM_BPPI_PTR_NUM_MASK 0x7ff 308 #define MVPP22_BM_POOL_PTRS_NUM_MASK 0xfff8 309 #define MVPP2_BM_BPPI_PREFETCH_FULL_MASK BIT(16) 310 #define MVPP2_BM_POOL_CTRL_REG(pool) (0x6200 + ((pool) * 4)) 311 #define MVPP2_BM_START_MASK BIT(0) 312 #define MVPP2_BM_STOP_MASK BIT(1) 313 #define MVPP2_BM_STATE_MASK BIT(4) 314 #define MVPP2_BM_LOW_THRESH_OFFS 8 315 #define MVPP2_BM_LOW_THRESH_MASK 0x7f00 316 #define MVPP2_BM_LOW_THRESH_VALUE(val) ((val) << \ 317 MVPP2_BM_LOW_THRESH_OFFS) 318 #define MVPP2_BM_HIGH_THRESH_OFFS 16 319 #define MVPP2_BM_HIGH_THRESH_MASK 0x7f0000 320 #define MVPP2_BM_HIGH_THRESH_VALUE(val) ((val) << \ 321 MVPP2_BM_HIGH_THRESH_OFFS) 322 #define MVPP2_BM_INTR_CAUSE_REG(pool) (0x6240 + ((pool) * 4)) 323 #define MVPP2_BM_RELEASED_DELAY_MASK BIT(0) 324 #define MVPP2_BM_ALLOC_FAILED_MASK BIT(1) 325 #define MVPP2_BM_BPPE_EMPTY_MASK BIT(2) 326 #define MVPP2_BM_BPPE_FULL_MASK BIT(3) 327 #define MVPP2_BM_AVAILABLE_BP_LOW_MASK BIT(4) 328 #define MVPP2_BM_INTR_MASK_REG(pool) (0x6280 + ((pool) * 4)) 329 #define MVPP2_BM_PHY_ALLOC_REG(pool) (0x6400 + ((pool) * 4)) 330 #define MVPP2_BM_PHY_ALLOC_GRNTD_MASK BIT(0) 331 #define MVPP2_BM_VIRT_ALLOC_REG 0x6440 332 #define MVPP22_BM_ADDR_HIGH_ALLOC 0x6444 333 #define MVPP22_BM_ADDR_HIGH_PHYS_MASK 0xff 334 #define MVPP22_BM_ADDR_HIGH_VIRT_MASK 0xff00 335 #define MVPP22_BM_ADDR_HIGH_VIRT_SHIFT 8 336 #define MVPP2_BM_PHY_RLS_REG(pool) (0x6480 + ((pool) * 4)) 337 #define MVPP2_BM_PHY_RLS_MC_BUFF_MASK BIT(0) 338 #define MVPP2_BM_PHY_RLS_PRIO_EN_MASK BIT(1) 339 #define MVPP2_BM_PHY_RLS_GRNTD_MASK BIT(2) 340 #define MVPP2_BM_VIRT_RLS_REG 0x64c0 341 #define MVPP22_BM_ADDR_HIGH_RLS_REG 0x64c4 342 #define MVPP22_BM_ADDR_HIGH_PHYS_RLS_MASK 0xff 343 #define MVPP22_BM_ADDR_HIGH_VIRT_RLS_MASK 0xff00 344 #define MVPP22_BM_ADDR_HIGH_VIRT_RLS_SHIFT 8 345 346 /* Packet Processor per-port counters */ 347 #define MVPP2_OVERRUN_ETH_DROP 0x7000 348 #define MVPP2_CLS_ETH_DROP 0x7020 349 350 /* Hit counters registers */ 351 #define MVPP2_CTRS_IDX 0x7040 352 #define MVPP22_CTRS_TX_CTR(port, txq) ((txq) | ((port) << 3) | BIT(7)) 353 #define MVPP2_TX_DESC_ENQ_CTR 0x7100 354 #define MVPP2_TX_DESC_ENQ_TO_DDR_CTR 0x7104 355 #define MVPP2_TX_BUFF_ENQ_TO_DDR_CTR 0x7108 356 #define MVPP2_TX_DESC_ENQ_HW_FWD_CTR 0x710c 357 #define MVPP2_RX_DESC_ENQ_CTR 0x7120 358 #define MVPP2_TX_PKTS_DEQ_CTR 0x7130 359 #define MVPP2_TX_PKTS_FULL_QUEUE_DROP_CTR 0x7200 360 #define MVPP2_TX_PKTS_EARLY_DROP_CTR 0x7204 361 #define MVPP2_TX_PKTS_BM_DROP_CTR 0x7208 362 #define MVPP2_TX_PKTS_BM_MC_DROP_CTR 0x720c 363 #define MVPP2_RX_PKTS_FULL_QUEUE_DROP_CTR 0x7220 364 #define MVPP2_RX_PKTS_EARLY_DROP_CTR 0x7224 365 #define MVPP2_RX_PKTS_BM_DROP_CTR 0x7228 366 #define MVPP2_CLS_DEC_TBL_HIT_CTR 0x7700 367 #define MVPP2_CLS_FLOW_TBL_HIT_CTR 0x7704 368 369 /* TX Scheduler registers */ 370 #define MVPP2_TXP_SCHED_PORT_INDEX_REG 0x8000 371 #define MVPP2_TXP_SCHED_Q_CMD_REG 0x8004 372 #define MVPP2_TXP_SCHED_ENQ_MASK 0xff 373 #define MVPP2_TXP_SCHED_DISQ_OFFSET 8 374 #define MVPP2_TXP_SCHED_CMD_1_REG 0x8010 375 #define MVPP2_TXP_SCHED_FIXED_PRIO_REG 0x8014 376 #define MVPP2_TXP_SCHED_PERIOD_REG 0x8018 377 #define MVPP2_TXP_SCHED_MTU_REG 0x801c 378 #define MVPP2_TXP_MTU_MAX 0x7FFFF 379 #define MVPP2_TXP_SCHED_REFILL_REG 0x8020 380 #define MVPP2_TXP_REFILL_TOKENS_ALL_MASK 0x7ffff 381 #define MVPP2_TXP_REFILL_PERIOD_ALL_MASK 0x3ff00000 382 #define MVPP2_TXP_REFILL_PERIOD_MASK(v) ((v) << 20) 383 #define MVPP2_TXP_SCHED_TOKEN_SIZE_REG 0x8024 384 #define MVPP2_TXP_TOKEN_SIZE_MAX 0xffffffff 385 #define MVPP2_TXQ_SCHED_REFILL_REG(q) (0x8040 + ((q) << 2)) 386 #define MVPP2_TXQ_REFILL_TOKENS_ALL_MASK 0x7ffff 387 #define MVPP2_TXQ_REFILL_PERIOD_ALL_MASK 0x3ff00000 388 #define MVPP2_TXQ_REFILL_PERIOD_MASK(v) ((v) << 20) 389 #define MVPP2_TXQ_SCHED_TOKEN_SIZE_REG(q) (0x8060 + ((q) << 2)) 390 #define MVPP2_TXQ_TOKEN_SIZE_MAX 0x7fffffff 391 #define MVPP2_TXQ_SCHED_TOKEN_CNTR_REG(q) (0x8080 + ((q) << 2)) 392 #define MVPP2_TXQ_TOKEN_CNTR_MAX 0xffffffff 393 394 /* TX general registers */ 395 #define MVPP2_TX_SNOOP_REG 0x8800 396 #define MVPP2_TX_PORT_FLUSH_REG 0x8810 397 #define MVPP2_TX_PORT_FLUSH_MASK(port) (1 << (port)) 398 399 /* LMS registers */ 400 #define MVPP2_SRC_ADDR_MIDDLE 0x24 401 #define MVPP2_SRC_ADDR_HIGH 0x28 402 #define MVPP2_PHY_AN_CFG0_REG 0x34 403 #define MVPP2_PHY_AN_STOP_SMI0_MASK BIT(7) 404 #define MVPP2_MNG_EXTENDED_GLOBAL_CTRL_REG 0x305c 405 #define MVPP2_EXT_GLOBAL_CTRL_DEFAULT 0x27 406 407 /* Per-port registers */ 408 #define MVPP2_GMAC_CTRL_0_REG 0x0 409 #define MVPP2_GMAC_PORT_EN_MASK BIT(0) 410 #define MVPP2_GMAC_PORT_TYPE_MASK BIT(1) 411 #define MVPP2_GMAC_MAX_RX_SIZE_OFFS 2 412 #define MVPP2_GMAC_MAX_RX_SIZE_MASK 0x7ffc 413 #define MVPP2_GMAC_MIB_CNTR_EN_MASK BIT(15) 414 #define MVPP2_GMAC_CTRL_1_REG 0x4 415 #define MVPP2_GMAC_PERIODIC_XON_EN_MASK BIT(1) 416 #define MVPP2_GMAC_GMII_LB_EN_MASK BIT(5) 417 #define MVPP2_GMAC_PCS_LB_EN_BIT 6 418 #define MVPP2_GMAC_PCS_LB_EN_MASK BIT(6) 419 #define MVPP2_GMAC_SA_LOW_OFFS 7 420 #define MVPP2_GMAC_CTRL_2_REG 0x8 421 #define MVPP2_GMAC_INBAND_AN_MASK BIT(0) 422 #define MVPP2_GMAC_FLOW_CTRL_MASK GENMASK(2, 1) 423 #define MVPP2_GMAC_PCS_ENABLE_MASK BIT(3) 424 #define MVPP2_GMAC_INTERNAL_CLK_MASK BIT(4) 425 #define MVPP2_GMAC_DISABLE_PADDING BIT(5) 426 #define MVPP2_GMAC_PORT_RESET_MASK BIT(6) 427 #define MVPP2_GMAC_AUTONEG_CONFIG 0xc 428 #define MVPP2_GMAC_FORCE_LINK_DOWN BIT(0) 429 #define MVPP2_GMAC_FORCE_LINK_PASS BIT(1) 430 #define MVPP2_GMAC_IN_BAND_AUTONEG BIT(2) 431 #define MVPP2_GMAC_IN_BAND_AUTONEG_BYPASS BIT(3) 432 #define MVPP2_GMAC_IN_BAND_RESTART_AN BIT(4) 433 #define MVPP2_GMAC_CONFIG_MII_SPEED BIT(5) 434 #define MVPP2_GMAC_CONFIG_GMII_SPEED BIT(6) 435 #define MVPP2_GMAC_AN_SPEED_EN BIT(7) 436 #define MVPP2_GMAC_FC_ADV_EN BIT(9) 437 #define MVPP2_GMAC_FC_ADV_ASM_EN BIT(10) 438 #define MVPP2_GMAC_FLOW_CTRL_AUTONEG BIT(11) 439 #define MVPP2_GMAC_CONFIG_FULL_DUPLEX BIT(12) 440 #define MVPP2_GMAC_AN_DUPLEX_EN BIT(13) 441 #define MVPP2_GMAC_STATUS0 0x10 442 #define MVPP2_GMAC_STATUS0_LINK_UP BIT(0) 443 #define MVPP2_GMAC_STATUS0_GMII_SPEED BIT(1) 444 #define MVPP2_GMAC_STATUS0_MII_SPEED BIT(2) 445 #define MVPP2_GMAC_STATUS0_FULL_DUPLEX BIT(3) 446 #define MVPP2_GMAC_STATUS0_RX_PAUSE BIT(4) 447 #define MVPP2_GMAC_STATUS0_TX_PAUSE BIT(5) 448 #define MVPP2_GMAC_STATUS0_AN_COMPLETE BIT(11) 449 #define MVPP2_GMAC_PORT_FIFO_CFG_1_REG 0x1c 450 #define MVPP2_GMAC_TX_FIFO_MIN_TH_OFFS 6 451 #define MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK 0x1fc0 452 #define MVPP2_GMAC_TX_FIFO_MIN_TH_MASK(v) (((v) << 6) & \ 453 MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK) 454 #define MVPP22_GMAC_INT_STAT 0x20 455 #define MVPP22_GMAC_INT_STAT_LINK BIT(1) 456 #define MVPP22_GMAC_INT_MASK 0x24 457 #define MVPP22_GMAC_INT_MASK_LINK_STAT BIT(1) 458 #define MVPP22_GMAC_CTRL_4_REG 0x90 459 #define MVPP22_CTRL4_EXT_PIN_GMII_SEL BIT(0) 460 #define MVPP22_CTRL4_RX_FC_EN BIT(3) 461 #define MVPP22_CTRL4_TX_FC_EN BIT(4) 462 #define MVPP22_CTRL4_DP_CLK_SEL BIT(5) 463 #define MVPP22_CTRL4_SYNC_BYPASS_DIS BIT(6) 464 #define MVPP22_CTRL4_QSGMII_BYPASS_ACTIVE BIT(7) 465 #define MVPP22_GMAC_INT_SUM_STAT 0xa0 466 #define MVPP22_GMAC_INT_SUM_STAT_INTERNAL BIT(1) 467 #define MVPP22_GMAC_INT_SUM_STAT_PTP BIT(2) 468 #define MVPP22_GMAC_INT_SUM_MASK 0xa4 469 #define MVPP22_GMAC_INT_SUM_MASK_LINK_STAT BIT(1) 470 #define MVPP22_GMAC_INT_SUM_MASK_PTP BIT(2) 471 472 /* Per-port XGMAC registers. PPv2.2 only, only for GOP port 0, 473 * relative to port->base. 474 */ 475 #define MVPP22_XLG_CTRL0_REG 0x100 476 #define MVPP22_XLG_CTRL0_PORT_EN BIT(0) 477 #define MVPP22_XLG_CTRL0_MAC_RESET_DIS BIT(1) 478 #define MVPP22_XLG_CTRL0_FORCE_LINK_DOWN BIT(2) 479 #define MVPP22_XLG_CTRL0_FORCE_LINK_PASS BIT(3) 480 #define MVPP22_XLG_CTRL0_RX_FLOW_CTRL_EN BIT(7) 481 #define MVPP22_XLG_CTRL0_TX_FLOW_CTRL_EN BIT(8) 482 #define MVPP22_XLG_CTRL0_MIB_CNT_DIS BIT(14) 483 #define MVPP22_XLG_CTRL1_REG 0x104 484 #define MVPP22_XLG_CTRL1_FRAMESIZELIMIT_OFFS 0 485 #define MVPP22_XLG_CTRL1_FRAMESIZELIMIT_MASK 0x1fff 486 #define MVPP22_XLG_STATUS 0x10c 487 #define MVPP22_XLG_STATUS_LINK_UP BIT(0) 488 #define MVPP22_XLG_INT_STAT 0x114 489 #define MVPP22_XLG_INT_STAT_LINK BIT(1) 490 #define MVPP22_XLG_INT_MASK 0x118 491 #define MVPP22_XLG_INT_MASK_LINK BIT(1) 492 #define MVPP22_XLG_CTRL3_REG 0x11c 493 #define MVPP22_XLG_CTRL3_MACMODESELECT_MASK (7 << 13) 494 #define MVPP22_XLG_CTRL3_MACMODESELECT_GMAC (0 << 13) 495 #define MVPP22_XLG_CTRL3_MACMODESELECT_10G (1 << 13) 496 #define MVPP22_XLG_EXT_INT_STAT 0x158 497 #define MVPP22_XLG_EXT_INT_STAT_XLG BIT(1) 498 #define MVPP22_XLG_EXT_INT_STAT_PTP BIT(7) 499 #define MVPP22_XLG_EXT_INT_MASK 0x15c 500 #define MVPP22_XLG_EXT_INT_MASK_XLG BIT(1) 501 #define MVPP22_XLG_EXT_INT_MASK_GIG BIT(2) 502 #define MVPP22_XLG_EXT_INT_MASK_PTP BIT(7) 503 #define MVPP22_XLG_CTRL4_REG 0x184 504 #define MVPP22_XLG_CTRL4_FWD_FC BIT(5) 505 #define MVPP22_XLG_CTRL4_FWD_PFC BIT(6) 506 #define MVPP22_XLG_CTRL4_MACMODSELECT_GMAC BIT(12) 507 #define MVPP22_XLG_CTRL4_EN_IDLE_CHECK BIT(14) 508 509 /* SMI registers. PPv2.2 only, relative to priv->iface_base. */ 510 #define MVPP22_SMI_MISC_CFG_REG 0x1204 511 #define MVPP22_SMI_POLLING_EN BIT(10) 512 513 /* TAI registers, PPv2.2 only, relative to priv->iface_base */ 514 #define MVPP22_TAI_INT_CAUSE 0x1400 515 #define MVPP22_TAI_INT_MASK 0x1404 516 #define MVPP22_TAI_CR0 0x1408 517 #define MVPP22_TAI_CR1 0x140c 518 #define MVPP22_TAI_TCFCR0 0x1410 519 #define MVPP22_TAI_TCFCR1 0x1414 520 #define MVPP22_TAI_TCFCR2 0x1418 521 #define MVPP22_TAI_FATWR 0x141c 522 #define MVPP22_TAI_TOD_STEP_NANO_CR 0x1420 523 #define MVPP22_TAI_TOD_STEP_FRAC_HIGH 0x1424 524 #define MVPP22_TAI_TOD_STEP_FRAC_LOW 0x1428 525 #define MVPP22_TAI_TAPDC_HIGH 0x142c 526 #define MVPP22_TAI_TAPDC_LOW 0x1430 527 #define MVPP22_TAI_TGTOD_SEC_HIGH 0x1434 528 #define MVPP22_TAI_TGTOD_SEC_MED 0x1438 529 #define MVPP22_TAI_TGTOD_SEC_LOW 0x143c 530 #define MVPP22_TAI_TGTOD_NANO_HIGH 0x1440 531 #define MVPP22_TAI_TGTOD_NANO_LOW 0x1444 532 #define MVPP22_TAI_TGTOD_FRAC_HIGH 0x1448 533 #define MVPP22_TAI_TGTOD_FRAC_LOW 0x144c 534 #define MVPP22_TAI_TLV_SEC_HIGH 0x1450 535 #define MVPP22_TAI_TLV_SEC_MED 0x1454 536 #define MVPP22_TAI_TLV_SEC_LOW 0x1458 537 #define MVPP22_TAI_TLV_NANO_HIGH 0x145c 538 #define MVPP22_TAI_TLV_NANO_LOW 0x1460 539 #define MVPP22_TAI_TLV_FRAC_HIGH 0x1464 540 #define MVPP22_TAI_TLV_FRAC_LOW 0x1468 541 #define MVPP22_TAI_TCV0_SEC_HIGH 0x146c 542 #define MVPP22_TAI_TCV0_SEC_MED 0x1470 543 #define MVPP22_TAI_TCV0_SEC_LOW 0x1474 544 #define MVPP22_TAI_TCV0_NANO_HIGH 0x1478 545 #define MVPP22_TAI_TCV0_NANO_LOW 0x147c 546 #define MVPP22_TAI_TCV0_FRAC_HIGH 0x1480 547 #define MVPP22_TAI_TCV0_FRAC_LOW 0x1484 548 #define MVPP22_TAI_TCV1_SEC_HIGH 0x1488 549 #define MVPP22_TAI_TCV1_SEC_MED 0x148c 550 #define MVPP22_TAI_TCV1_SEC_LOW 0x1490 551 #define MVPP22_TAI_TCV1_NANO_HIGH 0x1494 552 #define MVPP22_TAI_TCV1_NANO_LOW 0x1498 553 #define MVPP22_TAI_TCV1_FRAC_HIGH 0x149c 554 #define MVPP22_TAI_TCV1_FRAC_LOW 0x14a0 555 #define MVPP22_TAI_TCSR 0x14a4 556 #define MVPP22_TAI_TUC_LSB 0x14a8 557 #define MVPP22_TAI_GFM_SEC_HIGH 0x14ac 558 #define MVPP22_TAI_GFM_SEC_MED 0x14b0 559 #define MVPP22_TAI_GFM_SEC_LOW 0x14b4 560 #define MVPP22_TAI_GFM_NANO_HIGH 0x14b8 561 #define MVPP22_TAI_GFM_NANO_LOW 0x14bc 562 #define MVPP22_TAI_GFM_FRAC_HIGH 0x14c0 563 #define MVPP22_TAI_GFM_FRAC_LOW 0x14c4 564 #define MVPP22_TAI_PCLK_DA_HIGH 0x14c8 565 #define MVPP22_TAI_PCLK_DA_LOW 0x14cc 566 #define MVPP22_TAI_CTCR 0x14d0 567 #define MVPP22_TAI_PCLK_CCC_HIGH 0x14d4 568 #define MVPP22_TAI_PCLK_CCC_LOW 0x14d8 569 #define MVPP22_TAI_DTC_HIGH 0x14dc 570 #define MVPP22_TAI_DTC_LOW 0x14e0 571 #define MVPP22_TAI_CCC_HIGH 0x14e4 572 #define MVPP22_TAI_CCC_LOW 0x14e8 573 #define MVPP22_TAI_ICICE 0x14f4 574 #define MVPP22_TAI_ICICC_LOW 0x14f8 575 #define MVPP22_TAI_TUC_MSB 0x14fc 576 577 #define MVPP22_GMAC_BASE(port) (0x7000 + (port) * 0x1000 + 0xe00) 578 579 #define MVPP2_CAUSE_TXQ_SENT_DESC_ALL_MASK 0xff 580 581 /* Descriptor ring Macros */ 582 #define MVPP2_QUEUE_NEXT_DESC(q, index) \ 583 (((index) < (q)->last_desc) ? ((index) + 1) : 0) 584 585 /* XPCS registers. PPv2.2 only */ 586 #define MVPP22_MPCS_BASE(port) (0x7000 + (port) * 0x1000) 587 #define MVPP22_MPCS_CTRL 0x14 588 #define MVPP22_MPCS_CTRL_FWD_ERR_CONN BIT(10) 589 #define MVPP22_MPCS_CLK_RESET 0x14c 590 #define MAC_CLK_RESET_SD_TX BIT(0) 591 #define MAC_CLK_RESET_SD_RX BIT(1) 592 #define MAC_CLK_RESET_MAC BIT(2) 593 #define MVPP22_MPCS_CLK_RESET_DIV_RATIO(n) ((n) << 4) 594 #define MVPP22_MPCS_CLK_RESET_DIV_SET BIT(11) 595 596 /* XPCS registers. PPv2.2 only */ 597 #define MVPP22_XPCS_BASE(port) (0x7400 + (port) * 0x1000) 598 #define MVPP22_XPCS_CFG0 0x0 599 #define MVPP22_XPCS_CFG0_RESET_DIS BIT(0) 600 #define MVPP22_XPCS_CFG0_PCS_MODE(n) ((n) << 3) 601 #define MVPP22_XPCS_CFG0_ACTIVE_LANE(n) ((n) << 5) 602 603 /* PTP registers. PPv2.2 only */ 604 #define MVPP22_PTP_BASE(port) (0x7800 + (port * 0x1000)) 605 #define MVPP22_PTP_INT_CAUSE 0x00 606 #define MVPP22_PTP_INT_CAUSE_QUEUE1 BIT(6) 607 #define MVPP22_PTP_INT_CAUSE_QUEUE0 BIT(5) 608 #define MVPP22_PTP_INT_MASK 0x04 609 #define MVPP22_PTP_INT_MASK_QUEUE1 BIT(6) 610 #define MVPP22_PTP_INT_MASK_QUEUE0 BIT(5) 611 #define MVPP22_PTP_GCR 0x08 612 #define MVPP22_PTP_GCR_RX_RESET BIT(13) 613 #define MVPP22_PTP_GCR_TX_RESET BIT(1) 614 #define MVPP22_PTP_GCR_TSU_ENABLE BIT(0) 615 #define MVPP22_PTP_TX_Q0_R0 0x0c 616 #define MVPP22_PTP_TX_Q0_R1 0x10 617 #define MVPP22_PTP_TX_Q0_R2 0x14 618 #define MVPP22_PTP_TX_Q1_R0 0x18 619 #define MVPP22_PTP_TX_Q1_R1 0x1c 620 #define MVPP22_PTP_TX_Q1_R2 0x20 621 #define MVPP22_PTP_TPCR 0x24 622 #define MVPP22_PTP_V1PCR 0x28 623 #define MVPP22_PTP_V2PCR 0x2c 624 #define MVPP22_PTP_Y1731PCR 0x30 625 #define MVPP22_PTP_NTPTSPCR 0x34 626 #define MVPP22_PTP_NTPRXPCR 0x38 627 #define MVPP22_PTP_NTPTXPCR 0x3c 628 #define MVPP22_PTP_WAMPPCR 0x40 629 #define MVPP22_PTP_NAPCR 0x44 630 #define MVPP22_PTP_FAPCR 0x48 631 #define MVPP22_PTP_CAPCR 0x50 632 #define MVPP22_PTP_ATAPCR 0x54 633 #define MVPP22_PTP_ACTAPCR 0x58 634 #define MVPP22_PTP_CATAPCR 0x5c 635 #define MVPP22_PTP_CACTAPCR 0x60 636 #define MVPP22_PTP_AITAPCR 0x64 637 #define MVPP22_PTP_CAITAPCR 0x68 638 #define MVPP22_PTP_CITAPCR 0x6c 639 #define MVPP22_PTP_NTP_OFF_HIGH 0x70 640 #define MVPP22_PTP_NTP_OFF_LOW 0x74 641 #define MVPP22_PTP_TX_PIPE_STATUS_DELAY 0x78 642 643 /* System controller registers. Accessed through a regmap. */ 644 #define GENCONF_SOFT_RESET1 0x1108 645 #define GENCONF_SOFT_RESET1_GOP BIT(6) 646 #define GENCONF_PORT_CTRL0 0x1110 647 #define GENCONF_PORT_CTRL0_BUS_WIDTH_SELECT BIT(1) 648 #define GENCONF_PORT_CTRL0_RX_DATA_SAMPLE BIT(29) 649 #define GENCONF_PORT_CTRL0_CLK_DIV_PHASE_CLR BIT(31) 650 #define GENCONF_PORT_CTRL1 0x1114 651 #define GENCONF_PORT_CTRL1_EN(p) BIT(p) 652 #define GENCONF_PORT_CTRL1_RESET(p) (BIT(p) << 28) 653 #define GENCONF_CTRL0 0x1120 654 #define GENCONF_CTRL0_PORT0_RGMII BIT(0) 655 #define GENCONF_CTRL0_PORT1_RGMII_MII BIT(1) 656 #define GENCONF_CTRL0_PORT1_RGMII BIT(2) 657 658 /* Various constants */ 659 660 /* Coalescing */ 661 #define MVPP2_TXDONE_COAL_PKTS_THRESH 64 662 #define MVPP2_TXDONE_HRTIMER_PERIOD_NS 1000000UL 663 #define MVPP2_TXDONE_COAL_USEC 1000 664 #define MVPP2_RX_COAL_PKTS 32 665 #define MVPP2_RX_COAL_USEC 64 666 667 /* The two bytes Marvell header. Either contains a special value used 668 * by Marvell switches when a specific hardware mode is enabled (not 669 * supported by this driver) or is filled automatically by zeroes on 670 * the RX side. Those two bytes being at the front of the Ethernet 671 * header, they allow to have the IP header aligned on a 4 bytes 672 * boundary automatically: the hardware skips those two bytes on its 673 * own. 674 */ 675 #define MVPP2_MH_SIZE 2 676 #define MVPP2_ETH_TYPE_LEN 2 677 #define MVPP2_PPPOE_HDR_SIZE 8 678 #define MVPP2_VLAN_TAG_LEN 4 679 #define MVPP2_VLAN_TAG_EDSA_LEN 8 680 681 /* Lbtd 802.3 type */ 682 #define MVPP2_IP_LBDT_TYPE 0xfffa 683 684 #define MVPP2_TX_CSUM_MAX_SIZE 9800 685 686 /* Timeout constants */ 687 #define MVPP2_TX_DISABLE_TIMEOUT_MSEC 1000 688 #define MVPP2_TX_PENDING_TIMEOUT_MSEC 1000 689 690 #define MVPP2_TX_MTU_MAX 0x7ffff 691 692 /* Maximum number of T-CONTs of PON port */ 693 #define MVPP2_MAX_TCONT 16 694 695 /* Maximum number of supported ports */ 696 #define MVPP2_MAX_PORTS 4 697 698 /* Maximum number of TXQs used by single port */ 699 #define MVPP2_MAX_TXQ 8 700 701 /* MVPP2_MAX_TSO_SEGS is the maximum number of fragments to allow in the GSO 702 * skb. As we need a maxium of two descriptors per fragments (1 header, 1 data), 703 * multiply this value by two to count the maximum number of skb descs needed. 704 */ 705 #define MVPP2_MAX_TSO_SEGS 300 706 #define MVPP2_MAX_SKB_DESCS (MVPP2_MAX_TSO_SEGS * 2 + MAX_SKB_FRAGS) 707 708 /* Max number of RXQs per port */ 709 #define MVPP2_PORT_MAX_RXQ 32 710 711 /* Max number of Rx descriptors */ 712 #define MVPP2_MAX_RXD_MAX 1024 713 #define MVPP2_MAX_RXD_DFLT 128 714 715 /* Max number of Tx descriptors */ 716 #define MVPP2_MAX_TXD_MAX 2048 717 #define MVPP2_MAX_TXD_DFLT 1024 718 719 /* Amount of Tx descriptors that can be reserved at once by CPU */ 720 #define MVPP2_CPU_DESC_CHUNK 64 721 722 /* Max number of Tx descriptors in each aggregated queue */ 723 #define MVPP2_AGGR_TXQ_SIZE 256 724 725 /* Descriptor aligned size */ 726 #define MVPP2_DESC_ALIGNED_SIZE 32 727 728 /* Descriptor alignment mask */ 729 #define MVPP2_TX_DESC_ALIGN (MVPP2_DESC_ALIGNED_SIZE - 1) 730 731 /* RX FIFO constants */ 732 #define MVPP2_RX_FIFO_PORT_DATA_SIZE_32KB 0x8000 733 #define MVPP2_RX_FIFO_PORT_DATA_SIZE_8KB 0x2000 734 #define MVPP2_RX_FIFO_PORT_DATA_SIZE_4KB 0x1000 735 #define MVPP2_RX_FIFO_PORT_ATTR_SIZE_32KB 0x200 736 #define MVPP2_RX_FIFO_PORT_ATTR_SIZE_8KB 0x80 737 #define MVPP2_RX_FIFO_PORT_ATTR_SIZE_4KB 0x40 738 #define MVPP2_RX_FIFO_PORT_MIN_PKT 0x80 739 740 /* TX FIFO constants */ 741 #define MVPP22_TX_FIFO_DATA_SIZE_10KB 0xa 742 #define MVPP22_TX_FIFO_DATA_SIZE_3KB 0x3 743 #define MVPP2_TX_FIFO_THRESHOLD_MIN 256 744 #define MVPP2_TX_FIFO_THRESHOLD_10KB \ 745 (MVPP22_TX_FIFO_DATA_SIZE_10KB * 1024 - MVPP2_TX_FIFO_THRESHOLD_MIN) 746 #define MVPP2_TX_FIFO_THRESHOLD_3KB \ 747 (MVPP22_TX_FIFO_DATA_SIZE_3KB * 1024 - MVPP2_TX_FIFO_THRESHOLD_MIN) 748 749 /* RX buffer constants */ 750 #define MVPP2_SKB_SHINFO_SIZE \ 751 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) 752 753 #define MVPP2_RX_PKT_SIZE(mtu) \ 754 ALIGN((mtu) + MVPP2_MH_SIZE + MVPP2_VLAN_TAG_LEN + \ 755 ETH_HLEN + ETH_FCS_LEN, cache_line_size()) 756 757 #define MVPP2_RX_BUF_SIZE(pkt_size) ((pkt_size) + MVPP2_SKB_HEADROOM) 758 #define MVPP2_RX_TOTAL_SIZE(buf_size) ((buf_size) + MVPP2_SKB_SHINFO_SIZE) 759 #define MVPP2_RX_MAX_PKT_SIZE(total_size) \ 760 ((total_size) - MVPP2_SKB_HEADROOM - MVPP2_SKB_SHINFO_SIZE) 761 762 #define MVPP2_MAX_RX_BUF_SIZE (PAGE_SIZE - MVPP2_SKB_SHINFO_SIZE - MVPP2_SKB_HEADROOM) 763 764 #define MVPP2_BIT_TO_BYTE(bit) ((bit) / 8) 765 #define MVPP2_BIT_TO_WORD(bit) ((bit) / 32) 766 #define MVPP2_BIT_IN_WORD(bit) ((bit) % 32) 767 768 #define MVPP2_N_PRS_FLOWS 52 769 #define MVPP2_N_RFS_ENTRIES_PER_FLOW 4 770 771 /* There are 7 supported high-level flows */ 772 #define MVPP2_N_RFS_RULES (MVPP2_N_RFS_ENTRIES_PER_FLOW * 7) 773 774 /* RSS constants */ 775 #define MVPP22_N_RSS_TABLES 8 776 #define MVPP22_RSS_TABLE_ENTRIES 32 777 778 /* IPv6 max L3 address size */ 779 #define MVPP2_MAX_L3_ADDR_SIZE 16 780 781 /* Port flags */ 782 #define MVPP2_F_LOOPBACK BIT(0) 783 #define MVPP2_F_DT_COMPAT BIT(1) 784 785 /* Marvell tag types */ 786 enum mvpp2_tag_type { 787 MVPP2_TAG_TYPE_NONE = 0, 788 MVPP2_TAG_TYPE_MH = 1, 789 MVPP2_TAG_TYPE_DSA = 2, 790 MVPP2_TAG_TYPE_EDSA = 3, 791 MVPP2_TAG_TYPE_VLAN = 4, 792 MVPP2_TAG_TYPE_LAST = 5 793 }; 794 795 /* L2 cast enum */ 796 enum mvpp2_prs_l2_cast { 797 MVPP2_PRS_L2_UNI_CAST, 798 MVPP2_PRS_L2_MULTI_CAST, 799 }; 800 801 /* L3 cast enum */ 802 enum mvpp2_prs_l3_cast { 803 MVPP2_PRS_L3_UNI_CAST, 804 MVPP2_PRS_L3_MULTI_CAST, 805 MVPP2_PRS_L3_BROAD_CAST 806 }; 807 808 /* PTP descriptor constants. The low bits of the descriptor are stored 809 * separately from the high bits. 810 */ 811 #define MVPP22_PTP_DESC_MASK_LOW 0xfff 812 813 /* PTPAction */ 814 enum mvpp22_ptp_action { 815 MVPP22_PTP_ACTION_NONE = 0, 816 MVPP22_PTP_ACTION_FORWARD = 1, 817 MVPP22_PTP_ACTION_CAPTURE = 3, 818 /* The following have not been verified */ 819 MVPP22_PTP_ACTION_ADDTIME = 4, 820 MVPP22_PTP_ACTION_ADDCORRECTEDTIME = 5, 821 MVPP22_PTP_ACTION_CAPTUREADDTIME = 6, 822 MVPP22_PTP_ACTION_CAPTUREADDCORRECTEDTIME = 7, 823 MVPP22_PTP_ACTION_ADDINGRESSTIME = 8, 824 MVPP22_PTP_ACTION_CAPTUREADDINGRESSTIME = 9, 825 MVPP22_PTP_ACTION_CAPTUREINGRESSTIME = 10, 826 }; 827 828 /* PTPPacketFormat */ 829 enum mvpp22_ptp_packet_format { 830 MVPP22_PTP_PKT_FMT_PTPV2 = 0, 831 MVPP22_PTP_PKT_FMT_PTPV1 = 1, 832 MVPP22_PTP_PKT_FMT_Y1731 = 2, 833 MVPP22_PTP_PKT_FMT_NTPTS = 3, 834 MVPP22_PTP_PKT_FMT_NTPRX = 4, 835 MVPP22_PTP_PKT_FMT_NTPTX = 5, 836 MVPP22_PTP_PKT_FMT_TWAMP = 6, 837 }; 838 839 #define MVPP22_PTP_ACTION(x) (((x) & 15) << 0) 840 #define MVPP22_PTP_PACKETFORMAT(x) (((x) & 7) << 4) 841 #define MVPP22_PTP_MACTIMESTAMPINGEN BIT(11) 842 #define MVPP22_PTP_TIMESTAMPENTRYID(x) (((x) & 31) << 12) 843 #define MVPP22_PTP_TIMESTAMPQUEUESELECT BIT(18) 844 845 /* BM constants */ 846 #define MVPP2_BM_JUMBO_BUF_NUM 512 847 #define MVPP2_BM_LONG_BUF_NUM 1024 848 #define MVPP2_BM_SHORT_BUF_NUM 2048 849 #define MVPP2_BM_POOL_SIZE_MAX (16*1024 - MVPP2_BM_POOL_PTR_ALIGN/4) 850 #define MVPP2_BM_POOL_PTR_ALIGN 128 851 #define MVPP2_BM_MAX_POOLS 8 852 853 /* BM cookie (32 bits) definition */ 854 #define MVPP2_BM_COOKIE_POOL_OFFS 8 855 #define MVPP2_BM_COOKIE_CPU_OFFS 24 856 857 #define MVPP2_BM_SHORT_FRAME_SIZE 704 /* frame size 128 */ 858 #define MVPP2_BM_LONG_FRAME_SIZE 2240 /* frame size 1664 */ 859 #define MVPP2_BM_JUMBO_FRAME_SIZE 10432 /* frame size 9856 */ 860 /* BM short pool packet size 861 * These value assure that for SWF the total number 862 * of bytes allocated for each buffer will be 512 863 */ 864 #define MVPP2_BM_SHORT_PKT_SIZE MVPP2_RX_MAX_PKT_SIZE(MVPP2_BM_SHORT_FRAME_SIZE) 865 #define MVPP2_BM_LONG_PKT_SIZE MVPP2_RX_MAX_PKT_SIZE(MVPP2_BM_LONG_FRAME_SIZE) 866 #define MVPP2_BM_JUMBO_PKT_SIZE MVPP2_RX_MAX_PKT_SIZE(MVPP2_BM_JUMBO_FRAME_SIZE) 867 868 #define MVPP21_ADDR_SPACE_SZ 0 869 #define MVPP22_ADDR_SPACE_SZ SZ_64K 870 871 #define MVPP2_MAX_THREADS 9 872 #define MVPP2_MAX_QVECS MVPP2_MAX_THREADS 873 874 /* GMAC MIB Counters register definitions */ 875 #define MVPP21_MIB_COUNTERS_OFFSET 0x1000 876 #define MVPP21_MIB_COUNTERS_PORT_SZ 0x400 877 #define MVPP22_MIB_COUNTERS_OFFSET 0x0 878 #define MVPP22_MIB_COUNTERS_PORT_SZ 0x100 879 880 #define MVPP2_MIB_GOOD_OCTETS_RCVD 0x0 881 #define MVPP2_MIB_BAD_OCTETS_RCVD 0x8 882 #define MVPP2_MIB_CRC_ERRORS_SENT 0xc 883 #define MVPP2_MIB_UNICAST_FRAMES_RCVD 0x10 884 #define MVPP2_MIB_BROADCAST_FRAMES_RCVD 0x18 885 #define MVPP2_MIB_MULTICAST_FRAMES_RCVD 0x1c 886 #define MVPP2_MIB_FRAMES_64_OCTETS 0x20 887 #define MVPP2_MIB_FRAMES_65_TO_127_OCTETS 0x24 888 #define MVPP2_MIB_FRAMES_128_TO_255_OCTETS 0x28 889 #define MVPP2_MIB_FRAMES_256_TO_511_OCTETS 0x2c 890 #define MVPP2_MIB_FRAMES_512_TO_1023_OCTETS 0x30 891 #define MVPP2_MIB_FRAMES_1024_TO_MAX_OCTETS 0x34 892 #define MVPP2_MIB_GOOD_OCTETS_SENT 0x38 893 #define MVPP2_MIB_UNICAST_FRAMES_SENT 0x40 894 #define MVPP2_MIB_MULTICAST_FRAMES_SENT 0x48 895 #define MVPP2_MIB_BROADCAST_FRAMES_SENT 0x4c 896 #define MVPP2_MIB_FC_SENT 0x54 897 #define MVPP2_MIB_FC_RCVD 0x58 898 #define MVPP2_MIB_RX_FIFO_OVERRUN 0x5c 899 #define MVPP2_MIB_UNDERSIZE_RCVD 0x60 900 #define MVPP2_MIB_FRAGMENTS_RCVD 0x64 901 #define MVPP2_MIB_OVERSIZE_RCVD 0x68 902 #define MVPP2_MIB_JABBER_RCVD 0x6c 903 #define MVPP2_MIB_MAC_RCV_ERROR 0x70 904 #define MVPP2_MIB_BAD_CRC_EVENT 0x74 905 #define MVPP2_MIB_COLLISION 0x78 906 #define MVPP2_MIB_LATE_COLLISION 0x7c 907 908 #define MVPP2_MIB_COUNTERS_STATS_DELAY (1 * HZ) 909 910 #define MVPP2_DESC_DMA_MASK DMA_BIT_MASK(40) 911 912 struct mvpp2_tai; 913 914 /* Definitions */ 915 struct mvpp2_dbgfs_entries; 916 917 struct mvpp2_rss_table { 918 u32 indir[MVPP22_RSS_TABLE_ENTRIES]; 919 }; 920 921 /* Shared Packet Processor resources */ 922 struct mvpp2 { 923 /* Shared registers' base addresses */ 924 void __iomem *lms_base; 925 void __iomem *iface_base; 926 927 /* On PPv2.2, each "software thread" can access the base 928 * register through a separate address space, each 64 KB apart 929 * from each other. Typically, such address spaces will be 930 * used per CPU. 931 */ 932 void __iomem *swth_base[MVPP2_MAX_THREADS]; 933 934 /* On PPv2.2, some port control registers are located into the system 935 * controller space. These registers are accessible through a regmap. 936 */ 937 struct regmap *sysctrl_base; 938 939 /* Common clocks */ 940 struct clk *pp_clk; 941 struct clk *gop_clk; 942 struct clk *mg_clk; 943 struct clk *mg_core_clk; 944 struct clk *axi_clk; 945 946 /* List of pointers to port structures */ 947 int port_count; 948 struct mvpp2_port *port_list[MVPP2_MAX_PORTS]; 949 struct mvpp2_tai *tai; 950 951 /* Number of Tx threads used */ 952 unsigned int nthreads; 953 /* Map of threads needing locking */ 954 unsigned long lock_map; 955 956 /* Aggregated TXQs */ 957 struct mvpp2_tx_queue *aggr_txqs; 958 959 /* Are we using page_pool with per-cpu pools? */ 960 int percpu_pools; 961 962 /* BM pools */ 963 struct mvpp2_bm_pool *bm_pools; 964 965 /* PRS shadow table */ 966 struct mvpp2_prs_shadow *prs_shadow; 967 /* PRS auxiliary table for double vlan entries control */ 968 bool *prs_double_vlans; 969 970 /* Tclk value */ 971 u32 tclk; 972 973 /* HW version */ 974 enum { MVPP21, MVPP22 } hw_version; 975 976 /* Maximum number of RXQs per port */ 977 unsigned int max_port_rxqs; 978 979 /* Workqueue to gather hardware statistics */ 980 char queue_name[30]; 981 struct workqueue_struct *stats_queue; 982 983 /* Debugfs root entry */ 984 struct dentry *dbgfs_dir; 985 986 /* Debugfs entries private data */ 987 struct mvpp2_dbgfs_entries *dbgfs_entries; 988 989 /* RSS Indirection tables */ 990 struct mvpp2_rss_table *rss_tables[MVPP22_N_RSS_TABLES]; 991 992 /* page_pool allocator */ 993 struct page_pool *page_pool[MVPP2_PORT_MAX_RXQ]; 994 }; 995 996 struct mvpp2_pcpu_stats { 997 struct u64_stats_sync syncp; 998 u64 rx_packets; 999 u64 rx_bytes; 1000 u64 tx_packets; 1001 u64 tx_bytes; 1002 /* XDP */ 1003 u64 xdp_redirect; 1004 u64 xdp_pass; 1005 u64 xdp_drop; 1006 u64 xdp_xmit; 1007 u64 xdp_xmit_err; 1008 u64 xdp_tx; 1009 u64 xdp_tx_err; 1010 }; 1011 1012 /* Per-CPU port control */ 1013 struct mvpp2_port_pcpu { 1014 struct hrtimer tx_done_timer; 1015 struct net_device *dev; 1016 bool timer_scheduled; 1017 }; 1018 1019 struct mvpp2_queue_vector { 1020 int irq; 1021 struct napi_struct napi; 1022 enum { MVPP2_QUEUE_VECTOR_SHARED, MVPP2_QUEUE_VECTOR_PRIVATE } type; 1023 int sw_thread_id; 1024 u16 sw_thread_mask; 1025 int first_rxq; 1026 int nrxqs; 1027 u32 pending_cause_rx; 1028 struct mvpp2_port *port; 1029 struct cpumask *mask; 1030 }; 1031 1032 /* Internal represention of a Flow Steering rule */ 1033 struct mvpp2_rfs_rule { 1034 /* Rule location inside the flow*/ 1035 int loc; 1036 1037 /* Flow type, such as TCP_V4_FLOW, IP6_FLOW, etc. */ 1038 int flow_type; 1039 1040 /* Index of the C2 TCAM entry handling this rule */ 1041 int c2_index; 1042 1043 /* Header fields that needs to be extracted to match this flow */ 1044 u16 hek_fields; 1045 1046 /* CLS engine : only c2 is supported for now. */ 1047 u8 engine; 1048 1049 /* TCAM key and mask for C2-based steering. These fields should be 1050 * encapsulated in a union should we add more engines. 1051 */ 1052 u64 c2_tcam; 1053 u64 c2_tcam_mask; 1054 1055 struct flow_rule *flow; 1056 }; 1057 1058 struct mvpp2_ethtool_fs { 1059 struct mvpp2_rfs_rule rule; 1060 struct ethtool_rxnfc rxnfc; 1061 }; 1062 1063 struct mvpp2_hwtstamp_queue { 1064 struct sk_buff *skb[32]; 1065 u8 next; 1066 }; 1067 1068 struct mvpp2_port { 1069 u8 id; 1070 1071 /* Index of the port from the "group of ports" complex point 1072 * of view. This is specific to PPv2.2. 1073 */ 1074 int gop_id; 1075 1076 int port_irq; 1077 1078 struct mvpp2 *priv; 1079 1080 /* Firmware node associated to the port */ 1081 struct fwnode_handle *fwnode; 1082 1083 /* Is a PHY always connected to the port */ 1084 bool has_phy; 1085 1086 /* Per-port registers' base address */ 1087 void __iomem *base; 1088 void __iomem *stats_base; 1089 1090 struct mvpp2_rx_queue **rxqs; 1091 unsigned int nrxqs; 1092 struct mvpp2_tx_queue **txqs; 1093 unsigned int ntxqs; 1094 struct net_device *dev; 1095 1096 struct bpf_prog *xdp_prog; 1097 1098 int pkt_size; 1099 1100 /* Per-CPU port control */ 1101 struct mvpp2_port_pcpu __percpu *pcpu; 1102 1103 /* Protect the BM refills and the Tx paths when a thread is used on more 1104 * than a single CPU. 1105 */ 1106 spinlock_t bm_lock[MVPP2_MAX_THREADS]; 1107 spinlock_t tx_lock[MVPP2_MAX_THREADS]; 1108 1109 /* Flags */ 1110 unsigned long flags; 1111 1112 u16 tx_ring_size; 1113 u16 rx_ring_size; 1114 struct mvpp2_pcpu_stats __percpu *stats; 1115 u64 *ethtool_stats; 1116 1117 unsigned long state; 1118 1119 /* Per-port work and its lock to gather hardware statistics */ 1120 struct mutex gather_stats_lock; 1121 struct delayed_work stats_work; 1122 1123 struct device_node *of_node; 1124 1125 phy_interface_t phy_interface; 1126 struct phylink *phylink; 1127 struct phylink_config phylink_config; 1128 struct phylink_pcs phylink_pcs; 1129 struct phy *comphy; 1130 1131 struct mvpp2_bm_pool *pool_long; 1132 struct mvpp2_bm_pool *pool_short; 1133 1134 /* Index of first port's physical RXQ */ 1135 u8 first_rxq; 1136 1137 struct mvpp2_queue_vector qvecs[MVPP2_MAX_QVECS]; 1138 unsigned int nqvecs; 1139 bool has_tx_irqs; 1140 1141 u32 tx_time_coal; 1142 1143 /* List of steering rules active on that port */ 1144 struct mvpp2_ethtool_fs *rfs_rules[MVPP2_N_RFS_ENTRIES_PER_FLOW]; 1145 int n_rfs_rules; 1146 1147 /* Each port has its own view of the rss contexts, so that it can number 1148 * them from 0 1149 */ 1150 int rss_ctx[MVPP22_N_RSS_TABLES]; 1151 1152 bool hwtstamp; 1153 bool rx_hwtstamp; 1154 enum hwtstamp_tx_types tx_hwtstamp_type; 1155 struct mvpp2_hwtstamp_queue tx_hwtstamp_queue[2]; 1156 }; 1157 1158 /* The mvpp2_tx_desc and mvpp2_rx_desc structures describe the 1159 * layout of the transmit and reception DMA descriptors, and their 1160 * layout is therefore defined by the hardware design 1161 */ 1162 1163 #define MVPP2_TXD_L3_OFF_SHIFT 0 1164 #define MVPP2_TXD_IP_HLEN_SHIFT 8 1165 #define MVPP2_TXD_L4_CSUM_FRAG BIT(13) 1166 #define MVPP2_TXD_L4_CSUM_NOT BIT(14) 1167 #define MVPP2_TXD_IP_CSUM_DISABLE BIT(15) 1168 #define MVPP2_TXD_PADDING_DISABLE BIT(23) 1169 #define MVPP2_TXD_L4_UDP BIT(24) 1170 #define MVPP2_TXD_L3_IP6 BIT(26) 1171 #define MVPP2_TXD_L_DESC BIT(28) 1172 #define MVPP2_TXD_F_DESC BIT(29) 1173 1174 #define MVPP2_RXD_ERR_SUMMARY BIT(15) 1175 #define MVPP2_RXD_ERR_CODE_MASK (BIT(13) | BIT(14)) 1176 #define MVPP2_RXD_ERR_CRC 0x0 1177 #define MVPP2_RXD_ERR_OVERRUN BIT(13) 1178 #define MVPP2_RXD_ERR_RESOURCE (BIT(13) | BIT(14)) 1179 #define MVPP2_RXD_BM_POOL_ID_OFFS 16 1180 #define MVPP2_RXD_BM_POOL_ID_MASK (BIT(16) | BIT(17) | BIT(18)) 1181 #define MVPP2_RXD_HWF_SYNC BIT(21) 1182 #define MVPP2_RXD_L4_CSUM_OK BIT(22) 1183 #define MVPP2_RXD_IP4_HEADER_ERR BIT(24) 1184 #define MVPP2_RXD_L4_TCP BIT(25) 1185 #define MVPP2_RXD_L4_UDP BIT(26) 1186 #define MVPP2_RXD_L3_IP4 BIT(28) 1187 #define MVPP2_RXD_L3_IP6 BIT(30) 1188 #define MVPP2_RXD_BUF_HDR BIT(31) 1189 1190 /* HW TX descriptor for PPv2.1 */ 1191 struct mvpp21_tx_desc { 1192 __le32 command; /* Options used by HW for packet transmitting.*/ 1193 u8 packet_offset; /* the offset from the buffer beginning */ 1194 u8 phys_txq; /* destination queue ID */ 1195 __le16 data_size; /* data size of transmitted packet in bytes */ 1196 __le32 buf_dma_addr; /* physical addr of transmitted buffer */ 1197 __le32 buf_cookie; /* cookie for access to TX buffer in tx path */ 1198 __le32 reserved1[3]; /* hw_cmd (for future use, BM, PON, PNC) */ 1199 __le32 reserved2; /* reserved (for future use) */ 1200 }; 1201 1202 /* HW RX descriptor for PPv2.1 */ 1203 struct mvpp21_rx_desc { 1204 __le32 status; /* info about received packet */ 1205 __le16 reserved1; /* parser_info (for future use, PnC) */ 1206 __le16 data_size; /* size of received packet in bytes */ 1207 __le32 buf_dma_addr; /* physical address of the buffer */ 1208 __le32 buf_cookie; /* cookie for access to RX buffer in rx path */ 1209 __le16 reserved2; /* gem_port_id (for future use, PON) */ 1210 __le16 reserved3; /* csum_l4 (for future use, PnC) */ 1211 u8 reserved4; /* bm_qset (for future use, BM) */ 1212 u8 reserved5; 1213 __le16 reserved6; /* classify_info (for future use, PnC) */ 1214 __le32 reserved7; /* flow_id (for future use, PnC) */ 1215 __le32 reserved8; 1216 }; 1217 1218 /* HW TX descriptor for PPv2.2 */ 1219 struct mvpp22_tx_desc { 1220 __le32 command; 1221 u8 packet_offset; 1222 u8 phys_txq; 1223 __le16 data_size; 1224 __le32 ptp_descriptor; 1225 __le32 reserved2; 1226 __le64 buf_dma_addr_ptp; 1227 __le64 buf_cookie_misc; 1228 }; 1229 1230 /* HW RX descriptor for PPv2.2 */ 1231 struct mvpp22_rx_desc { 1232 __le32 status; 1233 __le16 reserved1; 1234 __le16 data_size; 1235 __le32 reserved2; 1236 __le32 timestamp; 1237 __le64 buf_dma_addr_key_hash; 1238 __le64 buf_cookie_misc; 1239 }; 1240 1241 /* Opaque type used by the driver to manipulate the HW TX and RX 1242 * descriptors 1243 */ 1244 struct mvpp2_tx_desc { 1245 union { 1246 struct mvpp21_tx_desc pp21; 1247 struct mvpp22_tx_desc pp22; 1248 }; 1249 }; 1250 1251 struct mvpp2_rx_desc { 1252 union { 1253 struct mvpp21_rx_desc pp21; 1254 struct mvpp22_rx_desc pp22; 1255 }; 1256 }; 1257 1258 enum mvpp2_tx_buf_type { 1259 MVPP2_TYPE_SKB, 1260 MVPP2_TYPE_XDP_TX, 1261 MVPP2_TYPE_XDP_NDO, 1262 }; 1263 1264 struct mvpp2_txq_pcpu_buf { 1265 enum mvpp2_tx_buf_type type; 1266 1267 /* Transmitted SKB */ 1268 union { 1269 struct xdp_frame *xdpf; 1270 struct sk_buff *skb; 1271 }; 1272 1273 /* Physical address of transmitted buffer */ 1274 dma_addr_t dma; 1275 1276 /* Size transmitted */ 1277 size_t size; 1278 }; 1279 1280 /* Per-CPU Tx queue control */ 1281 struct mvpp2_txq_pcpu { 1282 unsigned int thread; 1283 1284 /* Number of Tx DMA descriptors in the descriptor ring */ 1285 int size; 1286 1287 /* Number of currently used Tx DMA descriptor in the 1288 * descriptor ring 1289 */ 1290 int count; 1291 1292 int wake_threshold; 1293 int stop_threshold; 1294 1295 /* Number of Tx DMA descriptors reserved for each CPU */ 1296 int reserved_num; 1297 1298 /* Infos about transmitted buffers */ 1299 struct mvpp2_txq_pcpu_buf *buffs; 1300 1301 /* Index of last TX DMA descriptor that was inserted */ 1302 int txq_put_index; 1303 1304 /* Index of the TX DMA descriptor to be cleaned up */ 1305 int txq_get_index; 1306 1307 /* DMA buffer for TSO headers */ 1308 char *tso_headers; 1309 dma_addr_t tso_headers_dma; 1310 }; 1311 1312 struct mvpp2_tx_queue { 1313 /* Physical number of this Tx queue */ 1314 u8 id; 1315 1316 /* Logical number of this Tx queue */ 1317 u8 log_id; 1318 1319 /* Number of Tx DMA descriptors in the descriptor ring */ 1320 int size; 1321 1322 /* Number of currently used Tx DMA descriptor in the descriptor ring */ 1323 int count; 1324 1325 /* Per-CPU control of physical Tx queues */ 1326 struct mvpp2_txq_pcpu __percpu *pcpu; 1327 1328 u32 done_pkts_coal; 1329 1330 /* Virtual address of thex Tx DMA descriptors array */ 1331 struct mvpp2_tx_desc *descs; 1332 1333 /* DMA address of the Tx DMA descriptors array */ 1334 dma_addr_t descs_dma; 1335 1336 /* Index of the last Tx DMA descriptor */ 1337 int last_desc; 1338 1339 /* Index of the next Tx DMA descriptor to process */ 1340 int next_desc_to_proc; 1341 }; 1342 1343 struct mvpp2_rx_queue { 1344 /* RX queue number, in the range 0-31 for physical RXQs */ 1345 u8 id; 1346 1347 /* Num of rx descriptors in the rx descriptor ring */ 1348 int size; 1349 1350 u32 pkts_coal; 1351 u32 time_coal; 1352 1353 /* Virtual address of the RX DMA descriptors array */ 1354 struct mvpp2_rx_desc *descs; 1355 1356 /* DMA address of the RX DMA descriptors array */ 1357 dma_addr_t descs_dma; 1358 1359 /* Index of the last RX DMA descriptor */ 1360 int last_desc; 1361 1362 /* Index of the next RX DMA descriptor to process */ 1363 int next_desc_to_proc; 1364 1365 /* ID of port to which physical RXQ is mapped */ 1366 int port; 1367 1368 /* Port's logic RXQ number to which physical RXQ is mapped */ 1369 int logic_rxq; 1370 1371 /* XDP memory accounting */ 1372 struct xdp_rxq_info xdp_rxq_short; 1373 struct xdp_rxq_info xdp_rxq_long; 1374 }; 1375 1376 struct mvpp2_bm_pool { 1377 /* Pool number in the range 0-7 */ 1378 int id; 1379 1380 /* Buffer Pointers Pool External (BPPE) size */ 1381 int size; 1382 /* BPPE size in bytes */ 1383 int size_bytes; 1384 /* Number of buffers for this pool */ 1385 int buf_num; 1386 /* Pool buffer size */ 1387 int buf_size; 1388 /* Packet size */ 1389 int pkt_size; 1390 int frag_size; 1391 1392 /* BPPE virtual base address */ 1393 u32 *virt_addr; 1394 /* BPPE DMA base address */ 1395 dma_addr_t dma_addr; 1396 1397 /* Ports using BM pool */ 1398 u32 port_map; 1399 }; 1400 1401 #define IS_TSO_HEADER(txq_pcpu, addr) \ 1402 ((addr) >= (txq_pcpu)->tso_headers_dma && \ 1403 (addr) < (txq_pcpu)->tso_headers_dma + \ 1404 (txq_pcpu)->size * TSO_HEADER_SIZE) 1405 1406 #define MVPP2_DRIVER_NAME "mvpp2" 1407 #define MVPP2_DRIVER_VERSION "1.0" 1408 1409 void mvpp2_write(struct mvpp2 *priv, u32 offset, u32 data); 1410 u32 mvpp2_read(struct mvpp2 *priv, u32 offset); 1411 1412 void mvpp2_dbgfs_init(struct mvpp2 *priv, const char *name); 1413 1414 void mvpp2_dbgfs_cleanup(struct mvpp2 *priv); 1415 1416 #ifdef CONFIG_MVPP2_PTP 1417 int mvpp22_tai_probe(struct device *dev, struct mvpp2 *priv); 1418 void mvpp22_tai_tstamp(struct mvpp2_tai *tai, u32 tstamp, 1419 struct skb_shared_hwtstamps *hwtstamp); 1420 void mvpp22_tai_start(struct mvpp2_tai *tai); 1421 void mvpp22_tai_stop(struct mvpp2_tai *tai); 1422 int mvpp22_tai_ptp_clock_index(struct mvpp2_tai *tai); 1423 #else 1424 static inline int mvpp22_tai_probe(struct device *dev, struct mvpp2 *priv) 1425 { 1426 return 0; 1427 } 1428 static inline void mvpp22_tai_tstamp(struct mvpp2_tai *tai, u32 tstamp, 1429 struct skb_shared_hwtstamps *hwtstamp) 1430 { 1431 } 1432 static inline void mvpp22_tai_start(struct mvpp2_tai *tai) 1433 { 1434 } 1435 static inline void mvpp22_tai_stop(struct mvpp2_tai *tai) 1436 { 1437 } 1438 static inline int mvpp22_tai_ptp_clock_index(struct mvpp2_tai *tai) 1439 { 1440 return -1; 1441 } 1442 #endif 1443 1444 static inline bool mvpp22_rx_hwtstamping(struct mvpp2_port *port) 1445 { 1446 return IS_ENABLED(CONFIG_MVPP2_PTP) && port->rx_hwtstamp; 1447 } 1448 #endif 1449