1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Definitions for Marvell PPv2 network controller for Armada 375 SoC. 4 * 5 * Copyright (C) 2014 Marvell 6 * 7 * Marcin Wojtas <mw@semihalf.com> 8 */ 9 #ifndef _MVPP2_H_ 10 #define _MVPP2_H_ 11 12 #include <linux/interrupt.h> 13 #include <linux/kernel.h> 14 #include <linux/netdevice.h> 15 #include <linux/phy.h> 16 #include <linux/phylink.h> 17 #include <net/flow_offload.h> 18 #include <net/page_pool.h> 19 #include <linux/bpf.h> 20 #include <net/xdp.h> 21 22 /* The PacketOffset field is measured in units of 32 bytes and is 3 bits wide, 23 * so the maximum offset is 7 * 32 = 224 24 */ 25 #define MVPP2_SKB_HEADROOM min(max(XDP_PACKET_HEADROOM, NET_SKB_PAD), 224) 26 27 #define MVPP2_XDP_PASS 0 28 #define MVPP2_XDP_DROPPED BIT(0) 29 #define MVPP2_XDP_TX BIT(1) 30 #define MVPP2_XDP_REDIR BIT(2) 31 32 /* Fifo Registers */ 33 #define MVPP2_RX_DATA_FIFO_SIZE_REG(port) (0x00 + 4 * (port)) 34 #define MVPP2_RX_ATTR_FIFO_SIZE_REG(port) (0x20 + 4 * (port)) 35 #define MVPP2_RX_MIN_PKT_SIZE_REG 0x60 36 #define MVPP2_RX_FIFO_INIT_REG 0x64 37 #define MVPP22_TX_FIFO_THRESH_REG(port) (0x8840 + 4 * (port)) 38 #define MVPP22_TX_FIFO_SIZE_REG(port) (0x8860 + 4 * (port)) 39 40 /* RX DMA Top Registers */ 41 #define MVPP2_RX_CTRL_REG(port) (0x140 + 4 * (port)) 42 #define MVPP2_RX_LOW_LATENCY_PKT_SIZE(s) (((s) & 0xfff) << 16) 43 #define MVPP2_RX_USE_PSEUDO_FOR_CSUM_MASK BIT(31) 44 #define MVPP2_POOL_BUF_SIZE_REG(pool) (0x180 + 4 * (pool)) 45 #define MVPP2_POOL_BUF_SIZE_OFFSET 5 46 #define MVPP2_RXQ_CONFIG_REG(rxq) (0x800 + 4 * (rxq)) 47 #define MVPP2_SNOOP_PKT_SIZE_MASK 0x1ff 48 #define MVPP2_SNOOP_BUF_HDR_MASK BIT(9) 49 #define MVPP2_RXQ_POOL_SHORT_OFFS 20 50 #define MVPP21_RXQ_POOL_SHORT_MASK 0x700000 51 #define MVPP22_RXQ_POOL_SHORT_MASK 0xf00000 52 #define MVPP2_RXQ_POOL_LONG_OFFS 24 53 #define MVPP21_RXQ_POOL_LONG_MASK 0x7000000 54 #define MVPP22_RXQ_POOL_LONG_MASK 0xf000000 55 #define MVPP2_RXQ_PACKET_OFFSET_OFFS 28 56 #define MVPP2_RXQ_PACKET_OFFSET_MASK 0x70000000 57 #define MVPP2_RXQ_DISABLE_MASK BIT(31) 58 59 /* Top Registers */ 60 #define MVPP2_MH_REG(port) (0x5040 + 4 * (port)) 61 #define MVPP2_DSA_EXTENDED BIT(5) 62 63 /* Parser Registers */ 64 #define MVPP2_PRS_INIT_LOOKUP_REG 0x1000 65 #define MVPP2_PRS_PORT_LU_MAX 0xf 66 #define MVPP2_PRS_PORT_LU_MASK(port) (0xff << ((port) * 4)) 67 #define MVPP2_PRS_PORT_LU_VAL(port, val) ((val) << ((port) * 4)) 68 #define MVPP2_PRS_INIT_OFFS_REG(port) (0x1004 + ((port) & 4)) 69 #define MVPP2_PRS_INIT_OFF_MASK(port) (0x3f << (((port) % 4) * 8)) 70 #define MVPP2_PRS_INIT_OFF_VAL(port, val) ((val) << (((port) % 4) * 8)) 71 #define MVPP2_PRS_MAX_LOOP_REG(port) (0x100c + ((port) & 4)) 72 #define MVPP2_PRS_MAX_LOOP_MASK(port) (0xff << (((port) % 4) * 8)) 73 #define MVPP2_PRS_MAX_LOOP_VAL(port, val) ((val) << (((port) % 4) * 8)) 74 #define MVPP2_PRS_TCAM_IDX_REG 0x1100 75 #define MVPP2_PRS_TCAM_DATA_REG(idx) (0x1104 + (idx) * 4) 76 #define MVPP2_PRS_TCAM_INV_MASK BIT(31) 77 #define MVPP2_PRS_SRAM_IDX_REG 0x1200 78 #define MVPP2_PRS_SRAM_DATA_REG(idx) (0x1204 + (idx) * 4) 79 #define MVPP2_PRS_TCAM_CTRL_REG 0x1230 80 #define MVPP2_PRS_TCAM_EN_MASK BIT(0) 81 #define MVPP2_PRS_TCAM_HIT_IDX_REG 0x1240 82 #define MVPP2_PRS_TCAM_HIT_CNT_REG 0x1244 83 #define MVPP2_PRS_TCAM_HIT_CNT_MASK GENMASK(15, 0) 84 85 /* RSS Registers */ 86 #define MVPP22_RSS_INDEX 0x1500 87 #define MVPP22_RSS_INDEX_TABLE_ENTRY(idx) (idx) 88 #define MVPP22_RSS_INDEX_TABLE(idx) ((idx) << 8) 89 #define MVPP22_RSS_INDEX_QUEUE(idx) ((idx) << 16) 90 #define MVPP22_RXQ2RSS_TABLE 0x1504 91 #define MVPP22_RSS_TABLE_POINTER(p) (p) 92 #define MVPP22_RSS_TABLE_ENTRY 0x1508 93 #define MVPP22_RSS_WIDTH 0x150c 94 95 /* Classifier Registers */ 96 #define MVPP2_CLS_MODE_REG 0x1800 97 #define MVPP2_CLS_MODE_ACTIVE_MASK BIT(0) 98 #define MVPP2_CLS_PORT_WAY_REG 0x1810 99 #define MVPP2_CLS_PORT_WAY_MASK(port) (1 << (port)) 100 #define MVPP2_CLS_LKP_INDEX_REG 0x1814 101 #define MVPP2_CLS_LKP_INDEX_WAY_OFFS 6 102 #define MVPP2_CLS_LKP_TBL_REG 0x1818 103 #define MVPP2_CLS_LKP_TBL_RXQ_MASK 0xff 104 #define MVPP2_CLS_LKP_FLOW_PTR(flow) ((flow) << 16) 105 #define MVPP2_CLS_LKP_TBL_LOOKUP_EN_MASK BIT(25) 106 #define MVPP2_CLS_FLOW_INDEX_REG 0x1820 107 #define MVPP2_CLS_FLOW_TBL0_REG 0x1824 108 #define MVPP2_CLS_FLOW_TBL0_LAST BIT(0) 109 #define MVPP2_CLS_FLOW_TBL0_ENG_MASK 0x7 110 #define MVPP2_CLS_FLOW_TBL0_OFFS 1 111 #define MVPP2_CLS_FLOW_TBL0_ENG(x) ((x) << 1) 112 #define MVPP2_CLS_FLOW_TBL0_PORT_ID_MASK 0xff 113 #define MVPP2_CLS_FLOW_TBL0_PORT_ID(port) ((port) << 4) 114 #define MVPP2_CLS_FLOW_TBL0_PORT_ID_SEL BIT(23) 115 #define MVPP2_CLS_FLOW_TBL1_REG 0x1828 116 #define MVPP2_CLS_FLOW_TBL1_N_FIELDS_MASK 0x7 117 #define MVPP2_CLS_FLOW_TBL1_N_FIELDS(x) (x) 118 #define MVPP2_CLS_FLOW_TBL1_LU_TYPE(lu) (((lu) & 0x3f) << 3) 119 #define MVPP2_CLS_FLOW_TBL1_PRIO_MASK 0x3f 120 #define MVPP2_CLS_FLOW_TBL1_PRIO(x) ((x) << 9) 121 #define MVPP2_CLS_FLOW_TBL1_SEQ_MASK 0x7 122 #define MVPP2_CLS_FLOW_TBL1_SEQ(x) ((x) << 15) 123 #define MVPP2_CLS_FLOW_TBL2_REG 0x182c 124 #define MVPP2_CLS_FLOW_TBL2_FLD_MASK 0x3f 125 #define MVPP2_CLS_FLOW_TBL2_FLD_OFFS(n) ((n) * 6) 126 #define MVPP2_CLS_FLOW_TBL2_FLD(n, x) ((x) << ((n) * 6)) 127 #define MVPP2_CLS_OVERSIZE_RXQ_LOW_REG(port) (0x1980 + ((port) * 4)) 128 #define MVPP2_CLS_OVERSIZE_RXQ_LOW_BITS 3 129 #define MVPP2_CLS_OVERSIZE_RXQ_LOW_MASK 0x7 130 #define MVPP2_CLS_SWFWD_P2HQ_REG(port) (0x19b0 + ((port) * 4)) 131 #define MVPP2_CLS_SWFWD_PCTRL_REG 0x19d0 132 #define MVPP2_CLS_SWFWD_PCTRL_MASK(port) (1 << (port)) 133 134 /* Classifier C2 engine Registers */ 135 #define MVPP22_CLS_C2_TCAM_IDX 0x1b00 136 #define MVPP22_CLS_C2_TCAM_DATA0 0x1b10 137 #define MVPP22_CLS_C2_TCAM_DATA1 0x1b14 138 #define MVPP22_CLS_C2_TCAM_DATA2 0x1b18 139 #define MVPP22_CLS_C2_TCAM_DATA3 0x1b1c 140 #define MVPP22_CLS_C2_TCAM_DATA4 0x1b20 141 #define MVPP22_CLS_C2_LU_TYPE(lu) ((lu) & 0x3f) 142 #define MVPP22_CLS_C2_PORT_ID(port) ((port) << 8) 143 #define MVPP22_CLS_C2_PORT_MASK (0xff << 8) 144 #define MVPP22_CLS_C2_TCAM_INV 0x1b24 145 #define MVPP22_CLS_C2_TCAM_INV_BIT BIT(31) 146 #define MVPP22_CLS_C2_HIT_CTR 0x1b50 147 #define MVPP22_CLS_C2_ACT 0x1b60 148 #define MVPP22_CLS_C2_ACT_RSS_EN(act) (((act) & 0x3) << 19) 149 #define MVPP22_CLS_C2_ACT_FWD(act) (((act) & 0x7) << 13) 150 #define MVPP22_CLS_C2_ACT_QHIGH(act) (((act) & 0x3) << 11) 151 #define MVPP22_CLS_C2_ACT_QLOW(act) (((act) & 0x3) << 9) 152 #define MVPP22_CLS_C2_ACT_COLOR(act) ((act) & 0x7) 153 #define MVPP22_CLS_C2_ATTR0 0x1b64 154 #define MVPP22_CLS_C2_ATTR0_QHIGH(qh) (((qh) & 0x1f) << 24) 155 #define MVPP22_CLS_C2_ATTR0_QHIGH_MASK 0x1f 156 #define MVPP22_CLS_C2_ATTR0_QHIGH_OFFS 24 157 #define MVPP22_CLS_C2_ATTR0_QLOW(ql) (((ql) & 0x7) << 21) 158 #define MVPP22_CLS_C2_ATTR0_QLOW_MASK 0x7 159 #define MVPP22_CLS_C2_ATTR0_QLOW_OFFS 21 160 #define MVPP22_CLS_C2_ATTR1 0x1b68 161 #define MVPP22_CLS_C2_ATTR2 0x1b6c 162 #define MVPP22_CLS_C2_ATTR2_RSS_EN BIT(30) 163 #define MVPP22_CLS_C2_ATTR3 0x1b70 164 #define MVPP22_CLS_C2_TCAM_CTRL 0x1b90 165 #define MVPP22_CLS_C2_TCAM_BYPASS_FIFO BIT(0) 166 167 /* Descriptor Manager Top Registers */ 168 #define MVPP2_RXQ_NUM_REG 0x2040 169 #define MVPP2_RXQ_DESC_ADDR_REG 0x2044 170 #define MVPP22_DESC_ADDR_OFFS 8 171 #define MVPP2_RXQ_DESC_SIZE_REG 0x2048 172 #define MVPP2_RXQ_DESC_SIZE_MASK 0x3ff0 173 #define MVPP2_RXQ_STATUS_UPDATE_REG(rxq) (0x3000 + 4 * (rxq)) 174 #define MVPP2_RXQ_NUM_PROCESSED_OFFSET 0 175 #define MVPP2_RXQ_NUM_NEW_OFFSET 16 176 #define MVPP2_RXQ_STATUS_REG(rxq) (0x3400 + 4 * (rxq)) 177 #define MVPP2_RXQ_OCCUPIED_MASK 0x3fff 178 #define MVPP2_RXQ_NON_OCCUPIED_OFFSET 16 179 #define MVPP2_RXQ_NON_OCCUPIED_MASK 0x3fff0000 180 #define MVPP2_RXQ_THRESH_REG 0x204c 181 #define MVPP2_OCCUPIED_THRESH_OFFSET 0 182 #define MVPP2_OCCUPIED_THRESH_MASK 0x3fff 183 #define MVPP2_RXQ_INDEX_REG 0x2050 184 #define MVPP2_TXQ_NUM_REG 0x2080 185 #define MVPP2_TXQ_DESC_ADDR_REG 0x2084 186 #define MVPP2_TXQ_DESC_SIZE_REG 0x2088 187 #define MVPP2_TXQ_DESC_SIZE_MASK 0x3ff0 188 #define MVPP2_TXQ_THRESH_REG 0x2094 189 #define MVPP2_TXQ_THRESH_OFFSET 16 190 #define MVPP2_TXQ_THRESH_MASK 0x3fff 191 #define MVPP2_AGGR_TXQ_UPDATE_REG 0x2090 192 #define MVPP2_TXQ_INDEX_REG 0x2098 193 #define MVPP2_TXQ_PREF_BUF_REG 0x209c 194 #define MVPP2_PREF_BUF_PTR(desc) ((desc) & 0xfff) 195 #define MVPP2_PREF_BUF_SIZE_4 (BIT(12) | BIT(13)) 196 #define MVPP2_PREF_BUF_SIZE_16 (BIT(12) | BIT(14)) 197 #define MVPP2_PREF_BUF_THRESH(val) ((val) << 17) 198 #define MVPP2_TXQ_DRAIN_EN_MASK BIT(31) 199 #define MVPP2_TXQ_PENDING_REG 0x20a0 200 #define MVPP2_TXQ_PENDING_MASK 0x3fff 201 #define MVPP2_TXQ_INT_STATUS_REG 0x20a4 202 #define MVPP2_TXQ_SENT_REG(txq) (0x3c00 + 4 * (txq)) 203 #define MVPP2_TRANSMITTED_COUNT_OFFSET 16 204 #define MVPP2_TRANSMITTED_COUNT_MASK 0x3fff0000 205 #define MVPP2_TXQ_RSVD_REQ_REG 0x20b0 206 #define MVPP2_TXQ_RSVD_REQ_Q_OFFSET 16 207 #define MVPP2_TXQ_RSVD_RSLT_REG 0x20b4 208 #define MVPP2_TXQ_RSVD_RSLT_MASK 0x3fff 209 #define MVPP2_TXQ_RSVD_CLR_REG 0x20b8 210 #define MVPP2_TXQ_RSVD_CLR_OFFSET 16 211 #define MVPP2_AGGR_TXQ_DESC_ADDR_REG(cpu) (0x2100 + 4 * (cpu)) 212 #define MVPP22_AGGR_TXQ_DESC_ADDR_OFFS 8 213 #define MVPP2_AGGR_TXQ_DESC_SIZE_REG(cpu) (0x2140 + 4 * (cpu)) 214 #define MVPP2_AGGR_TXQ_DESC_SIZE_MASK 0x3ff0 215 #define MVPP2_AGGR_TXQ_STATUS_REG(cpu) (0x2180 + 4 * (cpu)) 216 #define MVPP2_AGGR_TXQ_PENDING_MASK 0x3fff 217 #define MVPP2_AGGR_TXQ_INDEX_REG(cpu) (0x21c0 + 4 * (cpu)) 218 219 /* MBUS bridge registers */ 220 #define MVPP2_WIN_BASE(w) (0x4000 + ((w) << 2)) 221 #define MVPP2_WIN_SIZE(w) (0x4020 + ((w) << 2)) 222 #define MVPP2_WIN_REMAP(w) (0x4040 + ((w) << 2)) 223 #define MVPP2_BASE_ADDR_ENABLE 0x4060 224 225 /* AXI Bridge Registers */ 226 #define MVPP22_AXI_BM_WR_ATTR_REG 0x4100 227 #define MVPP22_AXI_BM_RD_ATTR_REG 0x4104 228 #define MVPP22_AXI_AGGRQ_DESCR_RD_ATTR_REG 0x4110 229 #define MVPP22_AXI_TXQ_DESCR_WR_ATTR_REG 0x4114 230 #define MVPP22_AXI_TXQ_DESCR_RD_ATTR_REG 0x4118 231 #define MVPP22_AXI_RXQ_DESCR_WR_ATTR_REG 0x411c 232 #define MVPP22_AXI_RX_DATA_WR_ATTR_REG 0x4120 233 #define MVPP22_AXI_TX_DATA_RD_ATTR_REG 0x4130 234 #define MVPP22_AXI_RD_NORMAL_CODE_REG 0x4150 235 #define MVPP22_AXI_RD_SNOOP_CODE_REG 0x4154 236 #define MVPP22_AXI_WR_NORMAL_CODE_REG 0x4160 237 #define MVPP22_AXI_WR_SNOOP_CODE_REG 0x4164 238 239 /* Values for AXI Bridge registers */ 240 #define MVPP22_AXI_ATTR_CACHE_OFFS 0 241 #define MVPP22_AXI_ATTR_DOMAIN_OFFS 12 242 243 #define MVPP22_AXI_CODE_CACHE_OFFS 0 244 #define MVPP22_AXI_CODE_DOMAIN_OFFS 4 245 246 #define MVPP22_AXI_CODE_CACHE_NON_CACHE 0x3 247 #define MVPP22_AXI_CODE_CACHE_WR_CACHE 0x7 248 #define MVPP22_AXI_CODE_CACHE_RD_CACHE 0xb 249 250 #define MVPP22_AXI_CODE_DOMAIN_OUTER_DOM 2 251 #define MVPP22_AXI_CODE_DOMAIN_SYSTEM 3 252 253 /* Interrupt Cause and Mask registers */ 254 #define MVPP2_ISR_TX_THRESHOLD_REG(port) (0x5140 + 4 * (port)) 255 #define MVPP2_MAX_ISR_TX_THRESHOLD 0xfffff0 256 257 #define MVPP2_ISR_RX_THRESHOLD_REG(rxq) (0x5200 + 4 * (rxq)) 258 #define MVPP2_MAX_ISR_RX_THRESHOLD 0xfffff0 259 #define MVPP21_ISR_RXQ_GROUP_REG(port) (0x5400 + 4 * (port)) 260 261 #define MVPP22_ISR_RXQ_GROUP_INDEX_REG 0x5400 262 #define MVPP22_ISR_RXQ_GROUP_INDEX_SUBGROUP_MASK 0xf 263 #define MVPP22_ISR_RXQ_GROUP_INDEX_GROUP_MASK 0x380 264 #define MVPP22_ISR_RXQ_GROUP_INDEX_GROUP_OFFSET 7 265 266 #define MVPP22_ISR_RXQ_GROUP_INDEX_SUBGROUP_MASK 0xf 267 #define MVPP22_ISR_RXQ_GROUP_INDEX_GROUP_MASK 0x380 268 269 #define MVPP22_ISR_RXQ_SUB_GROUP_CONFIG_REG 0x5404 270 #define MVPP22_ISR_RXQ_SUB_GROUP_STARTQ_MASK 0x1f 271 #define MVPP22_ISR_RXQ_SUB_GROUP_SIZE_MASK 0xf00 272 #define MVPP22_ISR_RXQ_SUB_GROUP_SIZE_OFFSET 8 273 274 #define MVPP2_ISR_ENABLE_REG(port) (0x5420 + 4 * (port)) 275 #define MVPP2_ISR_ENABLE_INTERRUPT(mask) ((mask) & 0xffff) 276 #define MVPP2_ISR_DISABLE_INTERRUPT(mask) (((mask) << 16) & 0xffff0000) 277 #define MVPP2_ISR_RX_TX_CAUSE_REG(port) (0x5480 + 4 * (port)) 278 #define MVPP2_CAUSE_RXQ_OCCUP_DESC_ALL_MASK(version) \ 279 ((version) == MVPP21 ? 0xffff : 0xff) 280 #define MVPP2_CAUSE_TXQ_OCCUP_DESC_ALL_MASK 0xff0000 281 #define MVPP2_CAUSE_TXQ_OCCUP_DESC_ALL_OFFSET 16 282 #define MVPP2_CAUSE_RX_FIFO_OVERRUN_MASK BIT(24) 283 #define MVPP2_CAUSE_FCS_ERR_MASK BIT(25) 284 #define MVPP2_CAUSE_TX_FIFO_UNDERRUN_MASK BIT(26) 285 #define MVPP2_CAUSE_TX_EXCEPTION_SUM_MASK BIT(29) 286 #define MVPP2_CAUSE_RX_EXCEPTION_SUM_MASK BIT(30) 287 #define MVPP2_CAUSE_MISC_SUM_MASK BIT(31) 288 #define MVPP2_ISR_RX_TX_MASK_REG(port) (0x54a0 + 4 * (port)) 289 #define MVPP2_ISR_PON_RX_TX_MASK_REG 0x54bc 290 #define MVPP2_PON_CAUSE_RXQ_OCCUP_DESC_ALL_MASK 0xffff 291 #define MVPP2_PON_CAUSE_TXP_OCCUP_DESC_ALL_MASK 0x3fc00000 292 #define MVPP2_PON_CAUSE_MISC_SUM_MASK BIT(31) 293 #define MVPP2_ISR_MISC_CAUSE_REG 0x55b0 294 295 /* Buffer Manager registers */ 296 #define MVPP2_BM_POOL_BASE_REG(pool) (0x6000 + ((pool) * 4)) 297 #define MVPP2_BM_POOL_BASE_ADDR_MASK 0xfffff80 298 #define MVPP2_BM_POOL_SIZE_REG(pool) (0x6040 + ((pool) * 4)) 299 #define MVPP2_BM_POOL_SIZE_MASK 0xfff0 300 #define MVPP2_BM_POOL_READ_PTR_REG(pool) (0x6080 + ((pool) * 4)) 301 #define MVPP2_BM_POOL_GET_READ_PTR_MASK 0xfff0 302 #define MVPP2_BM_POOL_PTRS_NUM_REG(pool) (0x60c0 + ((pool) * 4)) 303 #define MVPP2_BM_POOL_PTRS_NUM_MASK 0xfff0 304 #define MVPP2_BM_BPPI_READ_PTR_REG(pool) (0x6100 + ((pool) * 4)) 305 #define MVPP2_BM_BPPI_PTRS_NUM_REG(pool) (0x6140 + ((pool) * 4)) 306 #define MVPP2_BM_BPPI_PTR_NUM_MASK 0x7ff 307 #define MVPP22_BM_POOL_PTRS_NUM_MASK 0xfff8 308 #define MVPP2_BM_BPPI_PREFETCH_FULL_MASK BIT(16) 309 #define MVPP2_BM_POOL_CTRL_REG(pool) (0x6200 + ((pool) * 4)) 310 #define MVPP2_BM_START_MASK BIT(0) 311 #define MVPP2_BM_STOP_MASK BIT(1) 312 #define MVPP2_BM_STATE_MASK BIT(4) 313 #define MVPP2_BM_LOW_THRESH_OFFS 8 314 #define MVPP2_BM_LOW_THRESH_MASK 0x7f00 315 #define MVPP2_BM_LOW_THRESH_VALUE(val) ((val) << \ 316 MVPP2_BM_LOW_THRESH_OFFS) 317 #define MVPP2_BM_HIGH_THRESH_OFFS 16 318 #define MVPP2_BM_HIGH_THRESH_MASK 0x7f0000 319 #define MVPP2_BM_HIGH_THRESH_VALUE(val) ((val) << \ 320 MVPP2_BM_HIGH_THRESH_OFFS) 321 #define MVPP2_BM_INTR_CAUSE_REG(pool) (0x6240 + ((pool) * 4)) 322 #define MVPP2_BM_RELEASED_DELAY_MASK BIT(0) 323 #define MVPP2_BM_ALLOC_FAILED_MASK BIT(1) 324 #define MVPP2_BM_BPPE_EMPTY_MASK BIT(2) 325 #define MVPP2_BM_BPPE_FULL_MASK BIT(3) 326 #define MVPP2_BM_AVAILABLE_BP_LOW_MASK BIT(4) 327 #define MVPP2_BM_INTR_MASK_REG(pool) (0x6280 + ((pool) * 4)) 328 #define MVPP2_BM_PHY_ALLOC_REG(pool) (0x6400 + ((pool) * 4)) 329 #define MVPP2_BM_PHY_ALLOC_GRNTD_MASK BIT(0) 330 #define MVPP2_BM_VIRT_ALLOC_REG 0x6440 331 #define MVPP22_BM_ADDR_HIGH_ALLOC 0x6444 332 #define MVPP22_BM_ADDR_HIGH_PHYS_MASK 0xff 333 #define MVPP22_BM_ADDR_HIGH_VIRT_MASK 0xff00 334 #define MVPP22_BM_ADDR_HIGH_VIRT_SHIFT 8 335 #define MVPP2_BM_PHY_RLS_REG(pool) (0x6480 + ((pool) * 4)) 336 #define MVPP2_BM_PHY_RLS_MC_BUFF_MASK BIT(0) 337 #define MVPP2_BM_PHY_RLS_PRIO_EN_MASK BIT(1) 338 #define MVPP2_BM_PHY_RLS_GRNTD_MASK BIT(2) 339 #define MVPP2_BM_VIRT_RLS_REG 0x64c0 340 #define MVPP22_BM_ADDR_HIGH_RLS_REG 0x64c4 341 #define MVPP22_BM_ADDR_HIGH_PHYS_RLS_MASK 0xff 342 #define MVPP22_BM_ADDR_HIGH_VIRT_RLS_MASK 0xff00 343 #define MVPP22_BM_ADDR_HIGH_VIRT_RLS_SHIFT 8 344 345 /* Packet Processor per-port counters */ 346 #define MVPP2_OVERRUN_ETH_DROP 0x7000 347 #define MVPP2_CLS_ETH_DROP 0x7020 348 349 /* Hit counters registers */ 350 #define MVPP2_CTRS_IDX 0x7040 351 #define MVPP22_CTRS_TX_CTR(port, txq) ((txq) | ((port) << 3) | BIT(7)) 352 #define MVPP2_TX_DESC_ENQ_CTR 0x7100 353 #define MVPP2_TX_DESC_ENQ_TO_DDR_CTR 0x7104 354 #define MVPP2_TX_BUFF_ENQ_TO_DDR_CTR 0x7108 355 #define MVPP2_TX_DESC_ENQ_HW_FWD_CTR 0x710c 356 #define MVPP2_RX_DESC_ENQ_CTR 0x7120 357 #define MVPP2_TX_PKTS_DEQ_CTR 0x7130 358 #define MVPP2_TX_PKTS_FULL_QUEUE_DROP_CTR 0x7200 359 #define MVPP2_TX_PKTS_EARLY_DROP_CTR 0x7204 360 #define MVPP2_TX_PKTS_BM_DROP_CTR 0x7208 361 #define MVPP2_TX_PKTS_BM_MC_DROP_CTR 0x720c 362 #define MVPP2_RX_PKTS_FULL_QUEUE_DROP_CTR 0x7220 363 #define MVPP2_RX_PKTS_EARLY_DROP_CTR 0x7224 364 #define MVPP2_RX_PKTS_BM_DROP_CTR 0x7228 365 #define MVPP2_CLS_DEC_TBL_HIT_CTR 0x7700 366 #define MVPP2_CLS_FLOW_TBL_HIT_CTR 0x7704 367 368 /* TX Scheduler registers */ 369 #define MVPP2_TXP_SCHED_PORT_INDEX_REG 0x8000 370 #define MVPP2_TXP_SCHED_Q_CMD_REG 0x8004 371 #define MVPP2_TXP_SCHED_ENQ_MASK 0xff 372 #define MVPP2_TXP_SCHED_DISQ_OFFSET 8 373 #define MVPP2_TXP_SCHED_CMD_1_REG 0x8010 374 #define MVPP2_TXP_SCHED_FIXED_PRIO_REG 0x8014 375 #define MVPP2_TXP_SCHED_PERIOD_REG 0x8018 376 #define MVPP2_TXP_SCHED_MTU_REG 0x801c 377 #define MVPP2_TXP_MTU_MAX 0x7FFFF 378 #define MVPP2_TXP_SCHED_REFILL_REG 0x8020 379 #define MVPP2_TXP_REFILL_TOKENS_ALL_MASK 0x7ffff 380 #define MVPP2_TXP_REFILL_PERIOD_ALL_MASK 0x3ff00000 381 #define MVPP2_TXP_REFILL_PERIOD_MASK(v) ((v) << 20) 382 #define MVPP2_TXP_SCHED_TOKEN_SIZE_REG 0x8024 383 #define MVPP2_TXP_TOKEN_SIZE_MAX 0xffffffff 384 #define MVPP2_TXQ_SCHED_REFILL_REG(q) (0x8040 + ((q) << 2)) 385 #define MVPP2_TXQ_REFILL_TOKENS_ALL_MASK 0x7ffff 386 #define MVPP2_TXQ_REFILL_PERIOD_ALL_MASK 0x3ff00000 387 #define MVPP2_TXQ_REFILL_PERIOD_MASK(v) ((v) << 20) 388 #define MVPP2_TXQ_SCHED_TOKEN_SIZE_REG(q) (0x8060 + ((q) << 2)) 389 #define MVPP2_TXQ_TOKEN_SIZE_MAX 0x7fffffff 390 #define MVPP2_TXQ_SCHED_TOKEN_CNTR_REG(q) (0x8080 + ((q) << 2)) 391 #define MVPP2_TXQ_TOKEN_CNTR_MAX 0xffffffff 392 393 /* TX general registers */ 394 #define MVPP2_TX_SNOOP_REG 0x8800 395 #define MVPP2_TX_PORT_FLUSH_REG 0x8810 396 #define MVPP2_TX_PORT_FLUSH_MASK(port) (1 << (port)) 397 398 /* LMS registers */ 399 #define MVPP2_SRC_ADDR_MIDDLE 0x24 400 #define MVPP2_SRC_ADDR_HIGH 0x28 401 #define MVPP2_PHY_AN_CFG0_REG 0x34 402 #define MVPP2_PHY_AN_STOP_SMI0_MASK BIT(7) 403 #define MVPP2_MNG_EXTENDED_GLOBAL_CTRL_REG 0x305c 404 #define MVPP2_EXT_GLOBAL_CTRL_DEFAULT 0x27 405 406 /* Per-port registers */ 407 #define MVPP2_GMAC_CTRL_0_REG 0x0 408 #define MVPP2_GMAC_PORT_EN_MASK BIT(0) 409 #define MVPP2_GMAC_PORT_TYPE_MASK BIT(1) 410 #define MVPP2_GMAC_MAX_RX_SIZE_OFFS 2 411 #define MVPP2_GMAC_MAX_RX_SIZE_MASK 0x7ffc 412 #define MVPP2_GMAC_MIB_CNTR_EN_MASK BIT(15) 413 #define MVPP2_GMAC_CTRL_1_REG 0x4 414 #define MVPP2_GMAC_PERIODIC_XON_EN_MASK BIT(1) 415 #define MVPP2_GMAC_GMII_LB_EN_MASK BIT(5) 416 #define MVPP2_GMAC_PCS_LB_EN_BIT 6 417 #define MVPP2_GMAC_PCS_LB_EN_MASK BIT(6) 418 #define MVPP2_GMAC_SA_LOW_OFFS 7 419 #define MVPP2_GMAC_CTRL_2_REG 0x8 420 #define MVPP2_GMAC_INBAND_AN_MASK BIT(0) 421 #define MVPP2_GMAC_FLOW_CTRL_MASK GENMASK(2, 1) 422 #define MVPP2_GMAC_PCS_ENABLE_MASK BIT(3) 423 #define MVPP2_GMAC_INTERNAL_CLK_MASK BIT(4) 424 #define MVPP2_GMAC_DISABLE_PADDING BIT(5) 425 #define MVPP2_GMAC_PORT_RESET_MASK BIT(6) 426 #define MVPP2_GMAC_AUTONEG_CONFIG 0xc 427 #define MVPP2_GMAC_FORCE_LINK_DOWN BIT(0) 428 #define MVPP2_GMAC_FORCE_LINK_PASS BIT(1) 429 #define MVPP2_GMAC_IN_BAND_AUTONEG BIT(2) 430 #define MVPP2_GMAC_IN_BAND_AUTONEG_BYPASS BIT(3) 431 #define MVPP2_GMAC_IN_BAND_RESTART_AN BIT(4) 432 #define MVPP2_GMAC_CONFIG_MII_SPEED BIT(5) 433 #define MVPP2_GMAC_CONFIG_GMII_SPEED BIT(6) 434 #define MVPP2_GMAC_AN_SPEED_EN BIT(7) 435 #define MVPP2_GMAC_FC_ADV_EN BIT(9) 436 #define MVPP2_GMAC_FC_ADV_ASM_EN BIT(10) 437 #define MVPP2_GMAC_FLOW_CTRL_AUTONEG BIT(11) 438 #define MVPP2_GMAC_CONFIG_FULL_DUPLEX BIT(12) 439 #define MVPP2_GMAC_AN_DUPLEX_EN BIT(13) 440 #define MVPP2_GMAC_STATUS0 0x10 441 #define MVPP2_GMAC_STATUS0_LINK_UP BIT(0) 442 #define MVPP2_GMAC_STATUS0_GMII_SPEED BIT(1) 443 #define MVPP2_GMAC_STATUS0_MII_SPEED BIT(2) 444 #define MVPP2_GMAC_STATUS0_FULL_DUPLEX BIT(3) 445 #define MVPP2_GMAC_STATUS0_RX_PAUSE BIT(4) 446 #define MVPP2_GMAC_STATUS0_TX_PAUSE BIT(5) 447 #define MVPP2_GMAC_STATUS0_AN_COMPLETE BIT(11) 448 #define MVPP2_GMAC_PORT_FIFO_CFG_1_REG 0x1c 449 #define MVPP2_GMAC_TX_FIFO_MIN_TH_OFFS 6 450 #define MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK 0x1fc0 451 #define MVPP2_GMAC_TX_FIFO_MIN_TH_MASK(v) (((v) << 6) & \ 452 MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK) 453 #define MVPP22_GMAC_INT_STAT 0x20 454 #define MVPP22_GMAC_INT_STAT_LINK BIT(1) 455 #define MVPP22_GMAC_INT_MASK 0x24 456 #define MVPP22_GMAC_INT_MASK_LINK_STAT BIT(1) 457 #define MVPP22_GMAC_CTRL_4_REG 0x90 458 #define MVPP22_CTRL4_EXT_PIN_GMII_SEL BIT(0) 459 #define MVPP22_CTRL4_RX_FC_EN BIT(3) 460 #define MVPP22_CTRL4_TX_FC_EN BIT(4) 461 #define MVPP22_CTRL4_DP_CLK_SEL BIT(5) 462 #define MVPP22_CTRL4_SYNC_BYPASS_DIS BIT(6) 463 #define MVPP22_CTRL4_QSGMII_BYPASS_ACTIVE BIT(7) 464 #define MVPP22_GMAC_INT_SUM_MASK 0xa4 465 #define MVPP22_GMAC_INT_SUM_MASK_LINK_STAT BIT(1) 466 467 /* Per-port XGMAC registers. PPv2.2 only, only for GOP port 0, 468 * relative to port->base. 469 */ 470 #define MVPP22_XLG_CTRL0_REG 0x100 471 #define MVPP22_XLG_CTRL0_PORT_EN BIT(0) 472 #define MVPP22_XLG_CTRL0_MAC_RESET_DIS BIT(1) 473 #define MVPP22_XLG_CTRL0_FORCE_LINK_DOWN BIT(2) 474 #define MVPP22_XLG_CTRL0_FORCE_LINK_PASS BIT(3) 475 #define MVPP22_XLG_CTRL0_RX_FLOW_CTRL_EN BIT(7) 476 #define MVPP22_XLG_CTRL0_TX_FLOW_CTRL_EN BIT(8) 477 #define MVPP22_XLG_CTRL0_MIB_CNT_DIS BIT(14) 478 #define MVPP22_XLG_CTRL1_REG 0x104 479 #define MVPP22_XLG_CTRL1_FRAMESIZELIMIT_OFFS 0 480 #define MVPP22_XLG_CTRL1_FRAMESIZELIMIT_MASK 0x1fff 481 #define MVPP22_XLG_STATUS 0x10c 482 #define MVPP22_XLG_STATUS_LINK_UP BIT(0) 483 #define MVPP22_XLG_INT_STAT 0x114 484 #define MVPP22_XLG_INT_STAT_LINK BIT(1) 485 #define MVPP22_XLG_INT_MASK 0x118 486 #define MVPP22_XLG_INT_MASK_LINK BIT(1) 487 #define MVPP22_XLG_CTRL3_REG 0x11c 488 #define MVPP22_XLG_CTRL3_MACMODESELECT_MASK (7 << 13) 489 #define MVPP22_XLG_CTRL3_MACMODESELECT_GMAC (0 << 13) 490 #define MVPP22_XLG_CTRL3_MACMODESELECT_10G (1 << 13) 491 #define MVPP22_XLG_EXT_INT_MASK 0x15c 492 #define MVPP22_XLG_EXT_INT_MASK_XLG BIT(1) 493 #define MVPP22_XLG_EXT_INT_MASK_GIG BIT(2) 494 #define MVPP22_XLG_CTRL4_REG 0x184 495 #define MVPP22_XLG_CTRL4_FWD_FC BIT(5) 496 #define MVPP22_XLG_CTRL4_FWD_PFC BIT(6) 497 #define MVPP22_XLG_CTRL4_MACMODSELECT_GMAC BIT(12) 498 #define MVPP22_XLG_CTRL4_EN_IDLE_CHECK BIT(14) 499 500 /* SMI registers. PPv2.2 only, relative to priv->iface_base. */ 501 #define MVPP22_SMI_MISC_CFG_REG 0x1204 502 #define MVPP22_SMI_POLLING_EN BIT(10) 503 504 #define MVPP22_GMAC_BASE(port) (0x7000 + (port) * 0x1000 + 0xe00) 505 506 #define MVPP2_CAUSE_TXQ_SENT_DESC_ALL_MASK 0xff 507 508 /* Descriptor ring Macros */ 509 #define MVPP2_QUEUE_NEXT_DESC(q, index) \ 510 (((index) < (q)->last_desc) ? ((index) + 1) : 0) 511 512 /* XPCS registers. PPv2.2 only */ 513 #define MVPP22_MPCS_BASE(port) (0x7000 + (port) * 0x1000) 514 #define MVPP22_MPCS_CTRL 0x14 515 #define MVPP22_MPCS_CTRL_FWD_ERR_CONN BIT(10) 516 #define MVPP22_MPCS_CLK_RESET 0x14c 517 #define MAC_CLK_RESET_SD_TX BIT(0) 518 #define MAC_CLK_RESET_SD_RX BIT(1) 519 #define MAC_CLK_RESET_MAC BIT(2) 520 #define MVPP22_MPCS_CLK_RESET_DIV_RATIO(n) ((n) << 4) 521 #define MVPP22_MPCS_CLK_RESET_DIV_SET BIT(11) 522 523 /* XPCS registers. PPv2.2 only */ 524 #define MVPP22_XPCS_BASE(port) (0x7400 + (port) * 0x1000) 525 #define MVPP22_XPCS_CFG0 0x0 526 #define MVPP22_XPCS_CFG0_RESET_DIS BIT(0) 527 #define MVPP22_XPCS_CFG0_PCS_MODE(n) ((n) << 3) 528 #define MVPP22_XPCS_CFG0_ACTIVE_LANE(n) ((n) << 5) 529 530 /* System controller registers. Accessed through a regmap. */ 531 #define GENCONF_SOFT_RESET1 0x1108 532 #define GENCONF_SOFT_RESET1_GOP BIT(6) 533 #define GENCONF_PORT_CTRL0 0x1110 534 #define GENCONF_PORT_CTRL0_BUS_WIDTH_SELECT BIT(1) 535 #define GENCONF_PORT_CTRL0_RX_DATA_SAMPLE BIT(29) 536 #define GENCONF_PORT_CTRL0_CLK_DIV_PHASE_CLR BIT(31) 537 #define GENCONF_PORT_CTRL1 0x1114 538 #define GENCONF_PORT_CTRL1_EN(p) BIT(p) 539 #define GENCONF_PORT_CTRL1_RESET(p) (BIT(p) << 28) 540 #define GENCONF_CTRL0 0x1120 541 #define GENCONF_CTRL0_PORT0_RGMII BIT(0) 542 #define GENCONF_CTRL0_PORT1_RGMII_MII BIT(1) 543 #define GENCONF_CTRL0_PORT1_RGMII BIT(2) 544 545 /* Various constants */ 546 547 /* Coalescing */ 548 #define MVPP2_TXDONE_COAL_PKTS_THRESH 64 549 #define MVPP2_TXDONE_HRTIMER_PERIOD_NS 1000000UL 550 #define MVPP2_TXDONE_COAL_USEC 1000 551 #define MVPP2_RX_COAL_PKTS 32 552 #define MVPP2_RX_COAL_USEC 64 553 554 /* The two bytes Marvell header. Either contains a special value used 555 * by Marvell switches when a specific hardware mode is enabled (not 556 * supported by this driver) or is filled automatically by zeroes on 557 * the RX side. Those two bytes being at the front of the Ethernet 558 * header, they allow to have the IP header aligned on a 4 bytes 559 * boundary automatically: the hardware skips those two bytes on its 560 * own. 561 */ 562 #define MVPP2_MH_SIZE 2 563 #define MVPP2_ETH_TYPE_LEN 2 564 #define MVPP2_PPPOE_HDR_SIZE 8 565 #define MVPP2_VLAN_TAG_LEN 4 566 #define MVPP2_VLAN_TAG_EDSA_LEN 8 567 568 /* Lbtd 802.3 type */ 569 #define MVPP2_IP_LBDT_TYPE 0xfffa 570 571 #define MVPP2_TX_CSUM_MAX_SIZE 9800 572 573 /* Timeout constants */ 574 #define MVPP2_TX_DISABLE_TIMEOUT_MSEC 1000 575 #define MVPP2_TX_PENDING_TIMEOUT_MSEC 1000 576 577 #define MVPP2_TX_MTU_MAX 0x7ffff 578 579 /* Maximum number of T-CONTs of PON port */ 580 #define MVPP2_MAX_TCONT 16 581 582 /* Maximum number of supported ports */ 583 #define MVPP2_MAX_PORTS 4 584 585 /* Maximum number of TXQs used by single port */ 586 #define MVPP2_MAX_TXQ 8 587 588 /* MVPP2_MAX_TSO_SEGS is the maximum number of fragments to allow in the GSO 589 * skb. As we need a maxium of two descriptors per fragments (1 header, 1 data), 590 * multiply this value by two to count the maximum number of skb descs needed. 591 */ 592 #define MVPP2_MAX_TSO_SEGS 300 593 #define MVPP2_MAX_SKB_DESCS (MVPP2_MAX_TSO_SEGS * 2 + MAX_SKB_FRAGS) 594 595 /* Max number of RXQs per port */ 596 #define MVPP2_PORT_MAX_RXQ 32 597 598 /* Max number of Rx descriptors */ 599 #define MVPP2_MAX_RXD_MAX 1024 600 #define MVPP2_MAX_RXD_DFLT 128 601 602 /* Max number of Tx descriptors */ 603 #define MVPP2_MAX_TXD_MAX 2048 604 #define MVPP2_MAX_TXD_DFLT 1024 605 606 /* Amount of Tx descriptors that can be reserved at once by CPU */ 607 #define MVPP2_CPU_DESC_CHUNK 64 608 609 /* Max number of Tx descriptors in each aggregated queue */ 610 #define MVPP2_AGGR_TXQ_SIZE 256 611 612 /* Descriptor aligned size */ 613 #define MVPP2_DESC_ALIGNED_SIZE 32 614 615 /* Descriptor alignment mask */ 616 #define MVPP2_TX_DESC_ALIGN (MVPP2_DESC_ALIGNED_SIZE - 1) 617 618 /* RX FIFO constants */ 619 #define MVPP2_RX_FIFO_PORT_DATA_SIZE_32KB 0x8000 620 #define MVPP2_RX_FIFO_PORT_DATA_SIZE_8KB 0x2000 621 #define MVPP2_RX_FIFO_PORT_DATA_SIZE_4KB 0x1000 622 #define MVPP2_RX_FIFO_PORT_ATTR_SIZE_32KB 0x200 623 #define MVPP2_RX_FIFO_PORT_ATTR_SIZE_8KB 0x80 624 #define MVPP2_RX_FIFO_PORT_ATTR_SIZE_4KB 0x40 625 #define MVPP2_RX_FIFO_PORT_MIN_PKT 0x80 626 627 /* TX FIFO constants */ 628 #define MVPP22_TX_FIFO_DATA_SIZE_10KB 0xa 629 #define MVPP22_TX_FIFO_DATA_SIZE_3KB 0x3 630 #define MVPP2_TX_FIFO_THRESHOLD_MIN 256 631 #define MVPP2_TX_FIFO_THRESHOLD_10KB \ 632 (MVPP22_TX_FIFO_DATA_SIZE_10KB * 1024 - MVPP2_TX_FIFO_THRESHOLD_MIN) 633 #define MVPP2_TX_FIFO_THRESHOLD_3KB \ 634 (MVPP22_TX_FIFO_DATA_SIZE_3KB * 1024 - MVPP2_TX_FIFO_THRESHOLD_MIN) 635 636 /* RX buffer constants */ 637 #define MVPP2_SKB_SHINFO_SIZE \ 638 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) 639 640 #define MVPP2_RX_PKT_SIZE(mtu) \ 641 ALIGN((mtu) + MVPP2_MH_SIZE + MVPP2_VLAN_TAG_LEN + \ 642 ETH_HLEN + ETH_FCS_LEN, cache_line_size()) 643 644 #define MVPP2_RX_BUF_SIZE(pkt_size) ((pkt_size) + MVPP2_SKB_HEADROOM) 645 #define MVPP2_RX_TOTAL_SIZE(buf_size) ((buf_size) + MVPP2_SKB_SHINFO_SIZE) 646 #define MVPP2_RX_MAX_PKT_SIZE(total_size) \ 647 ((total_size) - MVPP2_SKB_HEADROOM - MVPP2_SKB_SHINFO_SIZE) 648 649 #define MVPP2_MAX_RX_BUF_SIZE (PAGE_SIZE - MVPP2_SKB_SHINFO_SIZE - MVPP2_SKB_HEADROOM) 650 651 #define MVPP2_BIT_TO_BYTE(bit) ((bit) / 8) 652 #define MVPP2_BIT_TO_WORD(bit) ((bit) / 32) 653 #define MVPP2_BIT_IN_WORD(bit) ((bit) % 32) 654 655 #define MVPP2_N_PRS_FLOWS 52 656 #define MVPP2_N_RFS_ENTRIES_PER_FLOW 4 657 658 /* There are 7 supported high-level flows */ 659 #define MVPP2_N_RFS_RULES (MVPP2_N_RFS_ENTRIES_PER_FLOW * 7) 660 661 /* RSS constants */ 662 #define MVPP22_N_RSS_TABLES 8 663 #define MVPP22_RSS_TABLE_ENTRIES 32 664 665 /* IPv6 max L3 address size */ 666 #define MVPP2_MAX_L3_ADDR_SIZE 16 667 668 /* Port flags */ 669 #define MVPP2_F_LOOPBACK BIT(0) 670 #define MVPP2_F_DT_COMPAT BIT(1) 671 672 /* Marvell tag types */ 673 enum mvpp2_tag_type { 674 MVPP2_TAG_TYPE_NONE = 0, 675 MVPP2_TAG_TYPE_MH = 1, 676 MVPP2_TAG_TYPE_DSA = 2, 677 MVPP2_TAG_TYPE_EDSA = 3, 678 MVPP2_TAG_TYPE_VLAN = 4, 679 MVPP2_TAG_TYPE_LAST = 5 680 }; 681 682 /* L2 cast enum */ 683 enum mvpp2_prs_l2_cast { 684 MVPP2_PRS_L2_UNI_CAST, 685 MVPP2_PRS_L2_MULTI_CAST, 686 }; 687 688 /* L3 cast enum */ 689 enum mvpp2_prs_l3_cast { 690 MVPP2_PRS_L3_UNI_CAST, 691 MVPP2_PRS_L3_MULTI_CAST, 692 MVPP2_PRS_L3_BROAD_CAST 693 }; 694 695 /* BM constants */ 696 #define MVPP2_BM_JUMBO_BUF_NUM 512 697 #define MVPP2_BM_LONG_BUF_NUM 1024 698 #define MVPP2_BM_SHORT_BUF_NUM 2048 699 #define MVPP2_BM_POOL_SIZE_MAX (16*1024 - MVPP2_BM_POOL_PTR_ALIGN/4) 700 #define MVPP2_BM_POOL_PTR_ALIGN 128 701 #define MVPP2_BM_MAX_POOLS 8 702 703 /* BM cookie (32 bits) definition */ 704 #define MVPP2_BM_COOKIE_POOL_OFFS 8 705 #define MVPP2_BM_COOKIE_CPU_OFFS 24 706 707 #define MVPP2_BM_SHORT_FRAME_SIZE 704 /* frame size 128 */ 708 #define MVPP2_BM_LONG_FRAME_SIZE 2240 /* frame size 1664 */ 709 #define MVPP2_BM_JUMBO_FRAME_SIZE 10432 /* frame size 9856 */ 710 /* BM short pool packet size 711 * These value assure that for SWF the total number 712 * of bytes allocated for each buffer will be 512 713 */ 714 #define MVPP2_BM_SHORT_PKT_SIZE MVPP2_RX_MAX_PKT_SIZE(MVPP2_BM_SHORT_FRAME_SIZE) 715 #define MVPP2_BM_LONG_PKT_SIZE MVPP2_RX_MAX_PKT_SIZE(MVPP2_BM_LONG_FRAME_SIZE) 716 #define MVPP2_BM_JUMBO_PKT_SIZE MVPP2_RX_MAX_PKT_SIZE(MVPP2_BM_JUMBO_FRAME_SIZE) 717 718 #define MVPP21_ADDR_SPACE_SZ 0 719 #define MVPP22_ADDR_SPACE_SZ SZ_64K 720 721 #define MVPP2_MAX_THREADS 9 722 #define MVPP2_MAX_QVECS MVPP2_MAX_THREADS 723 724 /* GMAC MIB Counters register definitions */ 725 #define MVPP21_MIB_COUNTERS_OFFSET 0x1000 726 #define MVPP21_MIB_COUNTERS_PORT_SZ 0x400 727 #define MVPP22_MIB_COUNTERS_OFFSET 0x0 728 #define MVPP22_MIB_COUNTERS_PORT_SZ 0x100 729 730 #define MVPP2_MIB_GOOD_OCTETS_RCVD 0x0 731 #define MVPP2_MIB_BAD_OCTETS_RCVD 0x8 732 #define MVPP2_MIB_CRC_ERRORS_SENT 0xc 733 #define MVPP2_MIB_UNICAST_FRAMES_RCVD 0x10 734 #define MVPP2_MIB_BROADCAST_FRAMES_RCVD 0x18 735 #define MVPP2_MIB_MULTICAST_FRAMES_RCVD 0x1c 736 #define MVPP2_MIB_FRAMES_64_OCTETS 0x20 737 #define MVPP2_MIB_FRAMES_65_TO_127_OCTETS 0x24 738 #define MVPP2_MIB_FRAMES_128_TO_255_OCTETS 0x28 739 #define MVPP2_MIB_FRAMES_256_TO_511_OCTETS 0x2c 740 #define MVPP2_MIB_FRAMES_512_TO_1023_OCTETS 0x30 741 #define MVPP2_MIB_FRAMES_1024_TO_MAX_OCTETS 0x34 742 #define MVPP2_MIB_GOOD_OCTETS_SENT 0x38 743 #define MVPP2_MIB_UNICAST_FRAMES_SENT 0x40 744 #define MVPP2_MIB_MULTICAST_FRAMES_SENT 0x48 745 #define MVPP2_MIB_BROADCAST_FRAMES_SENT 0x4c 746 #define MVPP2_MIB_FC_SENT 0x54 747 #define MVPP2_MIB_FC_RCVD 0x58 748 #define MVPP2_MIB_RX_FIFO_OVERRUN 0x5c 749 #define MVPP2_MIB_UNDERSIZE_RCVD 0x60 750 #define MVPP2_MIB_FRAGMENTS_RCVD 0x64 751 #define MVPP2_MIB_OVERSIZE_RCVD 0x68 752 #define MVPP2_MIB_JABBER_RCVD 0x6c 753 #define MVPP2_MIB_MAC_RCV_ERROR 0x70 754 #define MVPP2_MIB_BAD_CRC_EVENT 0x74 755 #define MVPP2_MIB_COLLISION 0x78 756 #define MVPP2_MIB_LATE_COLLISION 0x7c 757 758 #define MVPP2_MIB_COUNTERS_STATS_DELAY (1 * HZ) 759 760 #define MVPP2_DESC_DMA_MASK DMA_BIT_MASK(40) 761 762 /* Definitions */ 763 struct mvpp2_dbgfs_entries; 764 765 struct mvpp2_rss_table { 766 u32 indir[MVPP22_RSS_TABLE_ENTRIES]; 767 }; 768 769 /* Shared Packet Processor resources */ 770 struct mvpp2 { 771 /* Shared registers' base addresses */ 772 void __iomem *lms_base; 773 void __iomem *iface_base; 774 775 /* On PPv2.2, each "software thread" can access the base 776 * register through a separate address space, each 64 KB apart 777 * from each other. Typically, such address spaces will be 778 * used per CPU. 779 */ 780 void __iomem *swth_base[MVPP2_MAX_THREADS]; 781 782 /* On PPv2.2, some port control registers are located into the system 783 * controller space. These registers are accessible through a regmap. 784 */ 785 struct regmap *sysctrl_base; 786 787 /* Common clocks */ 788 struct clk *pp_clk; 789 struct clk *gop_clk; 790 struct clk *mg_clk; 791 struct clk *mg_core_clk; 792 struct clk *axi_clk; 793 794 /* List of pointers to port structures */ 795 int port_count; 796 struct mvpp2_port *port_list[MVPP2_MAX_PORTS]; 797 798 /* Number of Tx threads used */ 799 unsigned int nthreads; 800 /* Map of threads needing locking */ 801 unsigned long lock_map; 802 803 /* Aggregated TXQs */ 804 struct mvpp2_tx_queue *aggr_txqs; 805 806 /* Are we using page_pool with per-cpu pools? */ 807 int percpu_pools; 808 809 /* BM pools */ 810 struct mvpp2_bm_pool *bm_pools; 811 812 /* PRS shadow table */ 813 struct mvpp2_prs_shadow *prs_shadow; 814 /* PRS auxiliary table for double vlan entries control */ 815 bool *prs_double_vlans; 816 817 /* Tclk value */ 818 u32 tclk; 819 820 /* HW version */ 821 enum { MVPP21, MVPP22 } hw_version; 822 823 /* Maximum number of RXQs per port */ 824 unsigned int max_port_rxqs; 825 826 /* Workqueue to gather hardware statistics */ 827 char queue_name[30]; 828 struct workqueue_struct *stats_queue; 829 830 /* Debugfs root entry */ 831 struct dentry *dbgfs_dir; 832 833 /* Debugfs entries private data */ 834 struct mvpp2_dbgfs_entries *dbgfs_entries; 835 836 /* RSS Indirection tables */ 837 struct mvpp2_rss_table *rss_tables[MVPP22_N_RSS_TABLES]; 838 839 /* page_pool allocator */ 840 struct page_pool *page_pool[MVPP2_PORT_MAX_RXQ]; 841 }; 842 843 struct mvpp2_pcpu_stats { 844 struct u64_stats_sync syncp; 845 u64 rx_packets; 846 u64 rx_bytes; 847 u64 tx_packets; 848 u64 tx_bytes; 849 /* XDP */ 850 u64 xdp_redirect; 851 u64 xdp_pass; 852 u64 xdp_drop; 853 u64 xdp_xmit; 854 u64 xdp_xmit_err; 855 u64 xdp_tx; 856 u64 xdp_tx_err; 857 }; 858 859 /* Per-CPU port control */ 860 struct mvpp2_port_pcpu { 861 struct hrtimer tx_done_timer; 862 struct net_device *dev; 863 bool timer_scheduled; 864 }; 865 866 struct mvpp2_queue_vector { 867 int irq; 868 struct napi_struct napi; 869 enum { MVPP2_QUEUE_VECTOR_SHARED, MVPP2_QUEUE_VECTOR_PRIVATE } type; 870 int sw_thread_id; 871 u16 sw_thread_mask; 872 int first_rxq; 873 int nrxqs; 874 u32 pending_cause_rx; 875 struct mvpp2_port *port; 876 struct cpumask *mask; 877 }; 878 879 /* Internal represention of a Flow Steering rule */ 880 struct mvpp2_rfs_rule { 881 /* Rule location inside the flow*/ 882 int loc; 883 884 /* Flow type, such as TCP_V4_FLOW, IP6_FLOW, etc. */ 885 int flow_type; 886 887 /* Index of the C2 TCAM entry handling this rule */ 888 int c2_index; 889 890 /* Header fields that needs to be extracted to match this flow */ 891 u16 hek_fields; 892 893 /* CLS engine : only c2 is supported for now. */ 894 u8 engine; 895 896 /* TCAM key and mask for C2-based steering. These fields should be 897 * encapsulated in a union should we add more engines. 898 */ 899 u64 c2_tcam; 900 u64 c2_tcam_mask; 901 902 struct flow_rule *flow; 903 }; 904 905 struct mvpp2_ethtool_fs { 906 struct mvpp2_rfs_rule rule; 907 struct ethtool_rxnfc rxnfc; 908 }; 909 910 struct mvpp2_port { 911 u8 id; 912 913 /* Index of the port from the "group of ports" complex point 914 * of view. This is specific to PPv2.2. 915 */ 916 int gop_id; 917 918 int link_irq; 919 920 struct mvpp2 *priv; 921 922 /* Firmware node associated to the port */ 923 struct fwnode_handle *fwnode; 924 925 /* Is a PHY always connected to the port */ 926 bool has_phy; 927 928 /* Per-port registers' base address */ 929 void __iomem *base; 930 void __iomem *stats_base; 931 932 struct mvpp2_rx_queue **rxqs; 933 unsigned int nrxqs; 934 struct mvpp2_tx_queue **txqs; 935 unsigned int ntxqs; 936 struct net_device *dev; 937 938 struct bpf_prog *xdp_prog; 939 940 int pkt_size; 941 942 /* Per-CPU port control */ 943 struct mvpp2_port_pcpu __percpu *pcpu; 944 945 /* Protect the BM refills and the Tx paths when a thread is used on more 946 * than a single CPU. 947 */ 948 spinlock_t bm_lock[MVPP2_MAX_THREADS]; 949 spinlock_t tx_lock[MVPP2_MAX_THREADS]; 950 951 /* Flags */ 952 unsigned long flags; 953 954 u16 tx_ring_size; 955 u16 rx_ring_size; 956 struct mvpp2_pcpu_stats __percpu *stats; 957 u64 *ethtool_stats; 958 959 unsigned long state; 960 961 /* Per-port work and its lock to gather hardware statistics */ 962 struct mutex gather_stats_lock; 963 struct delayed_work stats_work; 964 965 struct device_node *of_node; 966 967 phy_interface_t phy_interface; 968 struct phylink *phylink; 969 struct phylink_config phylink_config; 970 struct phy *comphy; 971 972 struct mvpp2_bm_pool *pool_long; 973 struct mvpp2_bm_pool *pool_short; 974 975 /* Index of first port's physical RXQ */ 976 u8 first_rxq; 977 978 struct mvpp2_queue_vector qvecs[MVPP2_MAX_QVECS]; 979 unsigned int nqvecs; 980 bool has_tx_irqs; 981 982 u32 tx_time_coal; 983 984 /* List of steering rules active on that port */ 985 struct mvpp2_ethtool_fs *rfs_rules[MVPP2_N_RFS_ENTRIES_PER_FLOW]; 986 int n_rfs_rules; 987 988 /* Each port has its own view of the rss contexts, so that it can number 989 * them from 0 990 */ 991 int rss_ctx[MVPP22_N_RSS_TABLES]; 992 }; 993 994 /* The mvpp2_tx_desc and mvpp2_rx_desc structures describe the 995 * layout of the transmit and reception DMA descriptors, and their 996 * layout is therefore defined by the hardware design 997 */ 998 999 #define MVPP2_TXD_L3_OFF_SHIFT 0 1000 #define MVPP2_TXD_IP_HLEN_SHIFT 8 1001 #define MVPP2_TXD_L4_CSUM_FRAG BIT(13) 1002 #define MVPP2_TXD_L4_CSUM_NOT BIT(14) 1003 #define MVPP2_TXD_IP_CSUM_DISABLE BIT(15) 1004 #define MVPP2_TXD_PADDING_DISABLE BIT(23) 1005 #define MVPP2_TXD_L4_UDP BIT(24) 1006 #define MVPP2_TXD_L3_IP6 BIT(26) 1007 #define MVPP2_TXD_L_DESC BIT(28) 1008 #define MVPP2_TXD_F_DESC BIT(29) 1009 1010 #define MVPP2_RXD_ERR_SUMMARY BIT(15) 1011 #define MVPP2_RXD_ERR_CODE_MASK (BIT(13) | BIT(14)) 1012 #define MVPP2_RXD_ERR_CRC 0x0 1013 #define MVPP2_RXD_ERR_OVERRUN BIT(13) 1014 #define MVPP2_RXD_ERR_RESOURCE (BIT(13) | BIT(14)) 1015 #define MVPP2_RXD_BM_POOL_ID_OFFS 16 1016 #define MVPP2_RXD_BM_POOL_ID_MASK (BIT(16) | BIT(17) | BIT(18)) 1017 #define MVPP2_RXD_HWF_SYNC BIT(21) 1018 #define MVPP2_RXD_L4_CSUM_OK BIT(22) 1019 #define MVPP2_RXD_IP4_HEADER_ERR BIT(24) 1020 #define MVPP2_RXD_L4_TCP BIT(25) 1021 #define MVPP2_RXD_L4_UDP BIT(26) 1022 #define MVPP2_RXD_L3_IP4 BIT(28) 1023 #define MVPP2_RXD_L3_IP6 BIT(30) 1024 #define MVPP2_RXD_BUF_HDR BIT(31) 1025 1026 /* HW TX descriptor for PPv2.1 */ 1027 struct mvpp21_tx_desc { 1028 __le32 command; /* Options used by HW for packet transmitting.*/ 1029 u8 packet_offset; /* the offset from the buffer beginning */ 1030 u8 phys_txq; /* destination queue ID */ 1031 __le16 data_size; /* data size of transmitted packet in bytes */ 1032 __le32 buf_dma_addr; /* physical addr of transmitted buffer */ 1033 __le32 buf_cookie; /* cookie for access to TX buffer in tx path */ 1034 __le32 reserved1[3]; /* hw_cmd (for future use, BM, PON, PNC) */ 1035 __le32 reserved2; /* reserved (for future use) */ 1036 }; 1037 1038 /* HW RX descriptor for PPv2.1 */ 1039 struct mvpp21_rx_desc { 1040 __le32 status; /* info about received packet */ 1041 __le16 reserved1; /* parser_info (for future use, PnC) */ 1042 __le16 data_size; /* size of received packet in bytes */ 1043 __le32 buf_dma_addr; /* physical address of the buffer */ 1044 __le32 buf_cookie; /* cookie for access to RX buffer in rx path */ 1045 __le16 reserved2; /* gem_port_id (for future use, PON) */ 1046 __le16 reserved3; /* csum_l4 (for future use, PnC) */ 1047 u8 reserved4; /* bm_qset (for future use, BM) */ 1048 u8 reserved5; 1049 __le16 reserved6; /* classify_info (for future use, PnC) */ 1050 __le32 reserved7; /* flow_id (for future use, PnC) */ 1051 __le32 reserved8; 1052 }; 1053 1054 /* HW TX descriptor for PPv2.2 */ 1055 struct mvpp22_tx_desc { 1056 __le32 command; 1057 u8 packet_offset; 1058 u8 phys_txq; 1059 __le16 data_size; 1060 __le64 reserved1; 1061 __le64 buf_dma_addr_ptp; 1062 __le64 buf_cookie_misc; 1063 }; 1064 1065 /* HW RX descriptor for PPv2.2 */ 1066 struct mvpp22_rx_desc { 1067 __le32 status; 1068 __le16 reserved1; 1069 __le16 data_size; 1070 __le32 reserved2; 1071 __le32 reserved3; 1072 __le64 buf_dma_addr_key_hash; 1073 __le64 buf_cookie_misc; 1074 }; 1075 1076 /* Opaque type used by the driver to manipulate the HW TX and RX 1077 * descriptors 1078 */ 1079 struct mvpp2_tx_desc { 1080 union { 1081 struct mvpp21_tx_desc pp21; 1082 struct mvpp22_tx_desc pp22; 1083 }; 1084 }; 1085 1086 struct mvpp2_rx_desc { 1087 union { 1088 struct mvpp21_rx_desc pp21; 1089 struct mvpp22_rx_desc pp22; 1090 }; 1091 }; 1092 1093 enum mvpp2_tx_buf_type { 1094 MVPP2_TYPE_SKB, 1095 MVPP2_TYPE_XDP_TX, 1096 MVPP2_TYPE_XDP_NDO, 1097 }; 1098 1099 struct mvpp2_txq_pcpu_buf { 1100 enum mvpp2_tx_buf_type type; 1101 1102 /* Transmitted SKB */ 1103 union { 1104 struct xdp_frame *xdpf; 1105 struct sk_buff *skb; 1106 }; 1107 1108 /* Physical address of transmitted buffer */ 1109 dma_addr_t dma; 1110 1111 /* Size transmitted */ 1112 size_t size; 1113 }; 1114 1115 /* Per-CPU Tx queue control */ 1116 struct mvpp2_txq_pcpu { 1117 unsigned int thread; 1118 1119 /* Number of Tx DMA descriptors in the descriptor ring */ 1120 int size; 1121 1122 /* Number of currently used Tx DMA descriptor in the 1123 * descriptor ring 1124 */ 1125 int count; 1126 1127 int wake_threshold; 1128 int stop_threshold; 1129 1130 /* Number of Tx DMA descriptors reserved for each CPU */ 1131 int reserved_num; 1132 1133 /* Infos about transmitted buffers */ 1134 struct mvpp2_txq_pcpu_buf *buffs; 1135 1136 /* Index of last TX DMA descriptor that was inserted */ 1137 int txq_put_index; 1138 1139 /* Index of the TX DMA descriptor to be cleaned up */ 1140 int txq_get_index; 1141 1142 /* DMA buffer for TSO headers */ 1143 char *tso_headers; 1144 dma_addr_t tso_headers_dma; 1145 }; 1146 1147 struct mvpp2_tx_queue { 1148 /* Physical number of this Tx queue */ 1149 u8 id; 1150 1151 /* Logical number of this Tx queue */ 1152 u8 log_id; 1153 1154 /* Number of Tx DMA descriptors in the descriptor ring */ 1155 int size; 1156 1157 /* Number of currently used Tx DMA descriptor in the descriptor ring */ 1158 int count; 1159 1160 /* Per-CPU control of physical Tx queues */ 1161 struct mvpp2_txq_pcpu __percpu *pcpu; 1162 1163 u32 done_pkts_coal; 1164 1165 /* Virtual address of thex Tx DMA descriptors array */ 1166 struct mvpp2_tx_desc *descs; 1167 1168 /* DMA address of the Tx DMA descriptors array */ 1169 dma_addr_t descs_dma; 1170 1171 /* Index of the last Tx DMA descriptor */ 1172 int last_desc; 1173 1174 /* Index of the next Tx DMA descriptor to process */ 1175 int next_desc_to_proc; 1176 }; 1177 1178 struct mvpp2_rx_queue { 1179 /* RX queue number, in the range 0-31 for physical RXQs */ 1180 u8 id; 1181 1182 /* Num of rx descriptors in the rx descriptor ring */ 1183 int size; 1184 1185 u32 pkts_coal; 1186 u32 time_coal; 1187 1188 /* Virtual address of the RX DMA descriptors array */ 1189 struct mvpp2_rx_desc *descs; 1190 1191 /* DMA address of the RX DMA descriptors array */ 1192 dma_addr_t descs_dma; 1193 1194 /* Index of the last RX DMA descriptor */ 1195 int last_desc; 1196 1197 /* Index of the next RX DMA descriptor to process */ 1198 int next_desc_to_proc; 1199 1200 /* ID of port to which physical RXQ is mapped */ 1201 int port; 1202 1203 /* Port's logic RXQ number to which physical RXQ is mapped */ 1204 int logic_rxq; 1205 1206 /* XDP memory accounting */ 1207 struct xdp_rxq_info xdp_rxq_short; 1208 struct xdp_rxq_info xdp_rxq_long; 1209 }; 1210 1211 struct mvpp2_bm_pool { 1212 /* Pool number in the range 0-7 */ 1213 int id; 1214 1215 /* Buffer Pointers Pool External (BPPE) size */ 1216 int size; 1217 /* BPPE size in bytes */ 1218 int size_bytes; 1219 /* Number of buffers for this pool */ 1220 int buf_num; 1221 /* Pool buffer size */ 1222 int buf_size; 1223 /* Packet size */ 1224 int pkt_size; 1225 int frag_size; 1226 1227 /* BPPE virtual base address */ 1228 u32 *virt_addr; 1229 /* BPPE DMA base address */ 1230 dma_addr_t dma_addr; 1231 1232 /* Ports using BM pool */ 1233 u32 port_map; 1234 }; 1235 1236 #define IS_TSO_HEADER(txq_pcpu, addr) \ 1237 ((addr) >= (txq_pcpu)->tso_headers_dma && \ 1238 (addr) < (txq_pcpu)->tso_headers_dma + \ 1239 (txq_pcpu)->size * TSO_HEADER_SIZE) 1240 1241 #define MVPP2_DRIVER_NAME "mvpp2" 1242 #define MVPP2_DRIVER_VERSION "1.0" 1243 1244 void mvpp2_write(struct mvpp2 *priv, u32 offset, u32 data); 1245 u32 mvpp2_read(struct mvpp2 *priv, u32 offset); 1246 1247 void mvpp2_dbgfs_init(struct mvpp2 *priv, const char *name); 1248 1249 void mvpp2_dbgfs_cleanup(struct mvpp2 *priv); 1250 1251 #endif 1252