1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Definitions for Marvell PPv2 network controller for Armada 375 SoC. 4 * 5 * Copyright (C) 2014 Marvell 6 * 7 * Marcin Wojtas <mw@semihalf.com> 8 */ 9 #ifndef _MVPP2_H_ 10 #define _MVPP2_H_ 11 12 #include <linux/interrupt.h> 13 #include <linux/kernel.h> 14 #include <linux/netdevice.h> 15 #include <linux/phy.h> 16 #include <linux/phylink.h> 17 #include <net/flow_offload.h> 18 19 /* Fifo Registers */ 20 #define MVPP2_RX_DATA_FIFO_SIZE_REG(port) (0x00 + 4 * (port)) 21 #define MVPP2_RX_ATTR_FIFO_SIZE_REG(port) (0x20 + 4 * (port)) 22 #define MVPP2_RX_MIN_PKT_SIZE_REG 0x60 23 #define MVPP2_RX_FIFO_INIT_REG 0x64 24 #define MVPP22_TX_FIFO_THRESH_REG(port) (0x8840 + 4 * (port)) 25 #define MVPP22_TX_FIFO_SIZE_REG(port) (0x8860 + 4 * (port)) 26 27 /* RX DMA Top Registers */ 28 #define MVPP2_RX_CTRL_REG(port) (0x140 + 4 * (port)) 29 #define MVPP2_RX_LOW_LATENCY_PKT_SIZE(s) (((s) & 0xfff) << 16) 30 #define MVPP2_RX_USE_PSEUDO_FOR_CSUM_MASK BIT(31) 31 #define MVPP2_POOL_BUF_SIZE_REG(pool) (0x180 + 4 * (pool)) 32 #define MVPP2_POOL_BUF_SIZE_OFFSET 5 33 #define MVPP2_RXQ_CONFIG_REG(rxq) (0x800 + 4 * (rxq)) 34 #define MVPP2_SNOOP_PKT_SIZE_MASK 0x1ff 35 #define MVPP2_SNOOP_BUF_HDR_MASK BIT(9) 36 #define MVPP2_RXQ_POOL_SHORT_OFFS 20 37 #define MVPP21_RXQ_POOL_SHORT_MASK 0x700000 38 #define MVPP22_RXQ_POOL_SHORT_MASK 0xf00000 39 #define MVPP2_RXQ_POOL_LONG_OFFS 24 40 #define MVPP21_RXQ_POOL_LONG_MASK 0x7000000 41 #define MVPP22_RXQ_POOL_LONG_MASK 0xf000000 42 #define MVPP2_RXQ_PACKET_OFFSET_OFFS 28 43 #define MVPP2_RXQ_PACKET_OFFSET_MASK 0x70000000 44 #define MVPP2_RXQ_DISABLE_MASK BIT(31) 45 46 /* Top Registers */ 47 #define MVPP2_MH_REG(port) (0x5040 + 4 * (port)) 48 #define MVPP2_DSA_EXTENDED BIT(5) 49 50 /* Parser Registers */ 51 #define MVPP2_PRS_INIT_LOOKUP_REG 0x1000 52 #define MVPP2_PRS_PORT_LU_MAX 0xf 53 #define MVPP2_PRS_PORT_LU_MASK(port) (0xff << ((port) * 4)) 54 #define MVPP2_PRS_PORT_LU_VAL(port, val) ((val) << ((port) * 4)) 55 #define MVPP2_PRS_INIT_OFFS_REG(port) (0x1004 + ((port) & 4)) 56 #define MVPP2_PRS_INIT_OFF_MASK(port) (0x3f << (((port) % 4) * 8)) 57 #define MVPP2_PRS_INIT_OFF_VAL(port, val) ((val) << (((port) % 4) * 8)) 58 #define MVPP2_PRS_MAX_LOOP_REG(port) (0x100c + ((port) & 4)) 59 #define MVPP2_PRS_MAX_LOOP_MASK(port) (0xff << (((port) % 4) * 8)) 60 #define MVPP2_PRS_MAX_LOOP_VAL(port, val) ((val) << (((port) % 4) * 8)) 61 #define MVPP2_PRS_TCAM_IDX_REG 0x1100 62 #define MVPP2_PRS_TCAM_DATA_REG(idx) (0x1104 + (idx) * 4) 63 #define MVPP2_PRS_TCAM_INV_MASK BIT(31) 64 #define MVPP2_PRS_SRAM_IDX_REG 0x1200 65 #define MVPP2_PRS_SRAM_DATA_REG(idx) (0x1204 + (idx) * 4) 66 #define MVPP2_PRS_TCAM_CTRL_REG 0x1230 67 #define MVPP2_PRS_TCAM_EN_MASK BIT(0) 68 #define MVPP2_PRS_TCAM_HIT_IDX_REG 0x1240 69 #define MVPP2_PRS_TCAM_HIT_CNT_REG 0x1244 70 #define MVPP2_PRS_TCAM_HIT_CNT_MASK GENMASK(15, 0) 71 72 /* RSS Registers */ 73 #define MVPP22_RSS_INDEX 0x1500 74 #define MVPP22_RSS_INDEX_TABLE_ENTRY(idx) (idx) 75 #define MVPP22_RSS_INDEX_TABLE(idx) ((idx) << 8) 76 #define MVPP22_RSS_INDEX_QUEUE(idx) ((idx) << 16) 77 #define MVPP22_RXQ2RSS_TABLE 0x1504 78 #define MVPP22_RSS_TABLE_POINTER(p) (p) 79 #define MVPP22_RSS_TABLE_ENTRY 0x1508 80 #define MVPP22_RSS_WIDTH 0x150c 81 82 /* Classifier Registers */ 83 #define MVPP2_CLS_MODE_REG 0x1800 84 #define MVPP2_CLS_MODE_ACTIVE_MASK BIT(0) 85 #define MVPP2_CLS_PORT_WAY_REG 0x1810 86 #define MVPP2_CLS_PORT_WAY_MASK(port) (1 << (port)) 87 #define MVPP2_CLS_LKP_INDEX_REG 0x1814 88 #define MVPP2_CLS_LKP_INDEX_WAY_OFFS 6 89 #define MVPP2_CLS_LKP_TBL_REG 0x1818 90 #define MVPP2_CLS_LKP_TBL_RXQ_MASK 0xff 91 #define MVPP2_CLS_LKP_FLOW_PTR(flow) ((flow) << 16) 92 #define MVPP2_CLS_LKP_TBL_LOOKUP_EN_MASK BIT(25) 93 #define MVPP2_CLS_FLOW_INDEX_REG 0x1820 94 #define MVPP2_CLS_FLOW_TBL0_REG 0x1824 95 #define MVPP2_CLS_FLOW_TBL0_LAST BIT(0) 96 #define MVPP2_CLS_FLOW_TBL0_ENG_MASK 0x7 97 #define MVPP2_CLS_FLOW_TBL0_OFFS 1 98 #define MVPP2_CLS_FLOW_TBL0_ENG(x) ((x) << 1) 99 #define MVPP2_CLS_FLOW_TBL0_PORT_ID_MASK 0xff 100 #define MVPP2_CLS_FLOW_TBL0_PORT_ID(port) ((port) << 4) 101 #define MVPP2_CLS_FLOW_TBL0_PORT_ID_SEL BIT(23) 102 #define MVPP2_CLS_FLOW_TBL1_REG 0x1828 103 #define MVPP2_CLS_FLOW_TBL1_N_FIELDS_MASK 0x7 104 #define MVPP2_CLS_FLOW_TBL1_N_FIELDS(x) (x) 105 #define MVPP2_CLS_FLOW_TBL1_LU_TYPE(lu) (((lu) & 0x3f) << 3) 106 #define MVPP2_CLS_FLOW_TBL1_PRIO_MASK 0x3f 107 #define MVPP2_CLS_FLOW_TBL1_PRIO(x) ((x) << 9) 108 #define MVPP2_CLS_FLOW_TBL1_SEQ_MASK 0x7 109 #define MVPP2_CLS_FLOW_TBL1_SEQ(x) ((x) << 15) 110 #define MVPP2_CLS_FLOW_TBL2_REG 0x182c 111 #define MVPP2_CLS_FLOW_TBL2_FLD_MASK 0x3f 112 #define MVPP2_CLS_FLOW_TBL2_FLD_OFFS(n) ((n) * 6) 113 #define MVPP2_CLS_FLOW_TBL2_FLD(n, x) ((x) << ((n) * 6)) 114 #define MVPP2_CLS_OVERSIZE_RXQ_LOW_REG(port) (0x1980 + ((port) * 4)) 115 #define MVPP2_CLS_OVERSIZE_RXQ_LOW_BITS 3 116 #define MVPP2_CLS_OVERSIZE_RXQ_LOW_MASK 0x7 117 #define MVPP2_CLS_SWFWD_P2HQ_REG(port) (0x19b0 + ((port) * 4)) 118 #define MVPP2_CLS_SWFWD_PCTRL_REG 0x19d0 119 #define MVPP2_CLS_SWFWD_PCTRL_MASK(port) (1 << (port)) 120 121 /* Classifier C2 engine Registers */ 122 #define MVPP22_CLS_C2_TCAM_IDX 0x1b00 123 #define MVPP22_CLS_C2_TCAM_DATA0 0x1b10 124 #define MVPP22_CLS_C2_TCAM_DATA1 0x1b14 125 #define MVPP22_CLS_C2_TCAM_DATA2 0x1b18 126 #define MVPP22_CLS_C2_TCAM_DATA3 0x1b1c 127 #define MVPP22_CLS_C2_TCAM_DATA4 0x1b20 128 #define MVPP22_CLS_C2_LU_TYPE(lu) ((lu) & 0x3f) 129 #define MVPP22_CLS_C2_PORT_ID(port) ((port) << 8) 130 #define MVPP22_CLS_C2_PORT_MASK (0xff << 8) 131 #define MVPP22_CLS_C2_TCAM_INV 0x1b24 132 #define MVPP22_CLS_C2_TCAM_INV_BIT BIT(31) 133 #define MVPP22_CLS_C2_HIT_CTR 0x1b50 134 #define MVPP22_CLS_C2_ACT 0x1b60 135 #define MVPP22_CLS_C2_ACT_RSS_EN(act) (((act) & 0x3) << 19) 136 #define MVPP22_CLS_C2_ACT_FWD(act) (((act) & 0x7) << 13) 137 #define MVPP22_CLS_C2_ACT_QHIGH(act) (((act) & 0x3) << 11) 138 #define MVPP22_CLS_C2_ACT_QLOW(act) (((act) & 0x3) << 9) 139 #define MVPP22_CLS_C2_ACT_COLOR(act) ((act) & 0x7) 140 #define MVPP22_CLS_C2_ATTR0 0x1b64 141 #define MVPP22_CLS_C2_ATTR0_QHIGH(qh) (((qh) & 0x1f) << 24) 142 #define MVPP22_CLS_C2_ATTR0_QHIGH_MASK 0x1f 143 #define MVPP22_CLS_C2_ATTR0_QHIGH_OFFS 24 144 #define MVPP22_CLS_C2_ATTR0_QLOW(ql) (((ql) & 0x7) << 21) 145 #define MVPP22_CLS_C2_ATTR0_QLOW_MASK 0x7 146 #define MVPP22_CLS_C2_ATTR0_QLOW_OFFS 21 147 #define MVPP22_CLS_C2_ATTR1 0x1b68 148 #define MVPP22_CLS_C2_ATTR2 0x1b6c 149 #define MVPP22_CLS_C2_ATTR2_RSS_EN BIT(30) 150 #define MVPP22_CLS_C2_ATTR3 0x1b70 151 #define MVPP22_CLS_C2_TCAM_CTRL 0x1b90 152 #define MVPP22_CLS_C2_TCAM_BYPASS_FIFO BIT(0) 153 154 /* Descriptor Manager Top Registers */ 155 #define MVPP2_RXQ_NUM_REG 0x2040 156 #define MVPP2_RXQ_DESC_ADDR_REG 0x2044 157 #define MVPP22_DESC_ADDR_OFFS 8 158 #define MVPP2_RXQ_DESC_SIZE_REG 0x2048 159 #define MVPP2_RXQ_DESC_SIZE_MASK 0x3ff0 160 #define MVPP2_RXQ_STATUS_UPDATE_REG(rxq) (0x3000 + 4 * (rxq)) 161 #define MVPP2_RXQ_NUM_PROCESSED_OFFSET 0 162 #define MVPP2_RXQ_NUM_NEW_OFFSET 16 163 #define MVPP2_RXQ_STATUS_REG(rxq) (0x3400 + 4 * (rxq)) 164 #define MVPP2_RXQ_OCCUPIED_MASK 0x3fff 165 #define MVPP2_RXQ_NON_OCCUPIED_OFFSET 16 166 #define MVPP2_RXQ_NON_OCCUPIED_MASK 0x3fff0000 167 #define MVPP2_RXQ_THRESH_REG 0x204c 168 #define MVPP2_OCCUPIED_THRESH_OFFSET 0 169 #define MVPP2_OCCUPIED_THRESH_MASK 0x3fff 170 #define MVPP2_RXQ_INDEX_REG 0x2050 171 #define MVPP2_TXQ_NUM_REG 0x2080 172 #define MVPP2_TXQ_DESC_ADDR_REG 0x2084 173 #define MVPP2_TXQ_DESC_SIZE_REG 0x2088 174 #define MVPP2_TXQ_DESC_SIZE_MASK 0x3ff0 175 #define MVPP2_TXQ_THRESH_REG 0x2094 176 #define MVPP2_TXQ_THRESH_OFFSET 16 177 #define MVPP2_TXQ_THRESH_MASK 0x3fff 178 #define MVPP2_AGGR_TXQ_UPDATE_REG 0x2090 179 #define MVPP2_TXQ_INDEX_REG 0x2098 180 #define MVPP2_TXQ_PREF_BUF_REG 0x209c 181 #define MVPP2_PREF_BUF_PTR(desc) ((desc) & 0xfff) 182 #define MVPP2_PREF_BUF_SIZE_4 (BIT(12) | BIT(13)) 183 #define MVPP2_PREF_BUF_SIZE_16 (BIT(12) | BIT(14)) 184 #define MVPP2_PREF_BUF_THRESH(val) ((val) << 17) 185 #define MVPP2_TXQ_DRAIN_EN_MASK BIT(31) 186 #define MVPP2_TXQ_PENDING_REG 0x20a0 187 #define MVPP2_TXQ_PENDING_MASK 0x3fff 188 #define MVPP2_TXQ_INT_STATUS_REG 0x20a4 189 #define MVPP2_TXQ_SENT_REG(txq) (0x3c00 + 4 * (txq)) 190 #define MVPP2_TRANSMITTED_COUNT_OFFSET 16 191 #define MVPP2_TRANSMITTED_COUNT_MASK 0x3fff0000 192 #define MVPP2_TXQ_RSVD_REQ_REG 0x20b0 193 #define MVPP2_TXQ_RSVD_REQ_Q_OFFSET 16 194 #define MVPP2_TXQ_RSVD_RSLT_REG 0x20b4 195 #define MVPP2_TXQ_RSVD_RSLT_MASK 0x3fff 196 #define MVPP2_TXQ_RSVD_CLR_REG 0x20b8 197 #define MVPP2_TXQ_RSVD_CLR_OFFSET 16 198 #define MVPP2_AGGR_TXQ_DESC_ADDR_REG(cpu) (0x2100 + 4 * (cpu)) 199 #define MVPP22_AGGR_TXQ_DESC_ADDR_OFFS 8 200 #define MVPP2_AGGR_TXQ_DESC_SIZE_REG(cpu) (0x2140 + 4 * (cpu)) 201 #define MVPP2_AGGR_TXQ_DESC_SIZE_MASK 0x3ff0 202 #define MVPP2_AGGR_TXQ_STATUS_REG(cpu) (0x2180 + 4 * (cpu)) 203 #define MVPP2_AGGR_TXQ_PENDING_MASK 0x3fff 204 #define MVPP2_AGGR_TXQ_INDEX_REG(cpu) (0x21c0 + 4 * (cpu)) 205 206 /* MBUS bridge registers */ 207 #define MVPP2_WIN_BASE(w) (0x4000 + ((w) << 2)) 208 #define MVPP2_WIN_SIZE(w) (0x4020 + ((w) << 2)) 209 #define MVPP2_WIN_REMAP(w) (0x4040 + ((w) << 2)) 210 #define MVPP2_BASE_ADDR_ENABLE 0x4060 211 212 /* AXI Bridge Registers */ 213 #define MVPP22_AXI_BM_WR_ATTR_REG 0x4100 214 #define MVPP22_AXI_BM_RD_ATTR_REG 0x4104 215 #define MVPP22_AXI_AGGRQ_DESCR_RD_ATTR_REG 0x4110 216 #define MVPP22_AXI_TXQ_DESCR_WR_ATTR_REG 0x4114 217 #define MVPP22_AXI_TXQ_DESCR_RD_ATTR_REG 0x4118 218 #define MVPP22_AXI_RXQ_DESCR_WR_ATTR_REG 0x411c 219 #define MVPP22_AXI_RX_DATA_WR_ATTR_REG 0x4120 220 #define MVPP22_AXI_TX_DATA_RD_ATTR_REG 0x4130 221 #define MVPP22_AXI_RD_NORMAL_CODE_REG 0x4150 222 #define MVPP22_AXI_RD_SNOOP_CODE_REG 0x4154 223 #define MVPP22_AXI_WR_NORMAL_CODE_REG 0x4160 224 #define MVPP22_AXI_WR_SNOOP_CODE_REG 0x4164 225 226 /* Values for AXI Bridge registers */ 227 #define MVPP22_AXI_ATTR_CACHE_OFFS 0 228 #define MVPP22_AXI_ATTR_DOMAIN_OFFS 12 229 230 #define MVPP22_AXI_CODE_CACHE_OFFS 0 231 #define MVPP22_AXI_CODE_DOMAIN_OFFS 4 232 233 #define MVPP22_AXI_CODE_CACHE_NON_CACHE 0x3 234 #define MVPP22_AXI_CODE_CACHE_WR_CACHE 0x7 235 #define MVPP22_AXI_CODE_CACHE_RD_CACHE 0xb 236 237 #define MVPP22_AXI_CODE_DOMAIN_OUTER_DOM 2 238 #define MVPP22_AXI_CODE_DOMAIN_SYSTEM 3 239 240 /* Interrupt Cause and Mask registers */ 241 #define MVPP2_ISR_TX_THRESHOLD_REG(port) (0x5140 + 4 * (port)) 242 #define MVPP2_MAX_ISR_TX_THRESHOLD 0xfffff0 243 244 #define MVPP2_ISR_RX_THRESHOLD_REG(rxq) (0x5200 + 4 * (rxq)) 245 #define MVPP2_MAX_ISR_RX_THRESHOLD 0xfffff0 246 #define MVPP21_ISR_RXQ_GROUP_REG(port) (0x5400 + 4 * (port)) 247 248 #define MVPP22_ISR_RXQ_GROUP_INDEX_REG 0x5400 249 #define MVPP22_ISR_RXQ_GROUP_INDEX_SUBGROUP_MASK 0xf 250 #define MVPP22_ISR_RXQ_GROUP_INDEX_GROUP_MASK 0x380 251 #define MVPP22_ISR_RXQ_GROUP_INDEX_GROUP_OFFSET 7 252 253 #define MVPP22_ISR_RXQ_GROUP_INDEX_SUBGROUP_MASK 0xf 254 #define MVPP22_ISR_RXQ_GROUP_INDEX_GROUP_MASK 0x380 255 256 #define MVPP22_ISR_RXQ_SUB_GROUP_CONFIG_REG 0x5404 257 #define MVPP22_ISR_RXQ_SUB_GROUP_STARTQ_MASK 0x1f 258 #define MVPP22_ISR_RXQ_SUB_GROUP_SIZE_MASK 0xf00 259 #define MVPP22_ISR_RXQ_SUB_GROUP_SIZE_OFFSET 8 260 261 #define MVPP2_ISR_ENABLE_REG(port) (0x5420 + 4 * (port)) 262 #define MVPP2_ISR_ENABLE_INTERRUPT(mask) ((mask) & 0xffff) 263 #define MVPP2_ISR_DISABLE_INTERRUPT(mask) (((mask) << 16) & 0xffff0000) 264 #define MVPP2_ISR_RX_TX_CAUSE_REG(port) (0x5480 + 4 * (port)) 265 #define MVPP2_CAUSE_RXQ_OCCUP_DESC_ALL_MASK(version) \ 266 ((version) == MVPP21 ? 0xffff : 0xff) 267 #define MVPP2_CAUSE_TXQ_OCCUP_DESC_ALL_MASK 0xff0000 268 #define MVPP2_CAUSE_TXQ_OCCUP_DESC_ALL_OFFSET 16 269 #define MVPP2_CAUSE_RX_FIFO_OVERRUN_MASK BIT(24) 270 #define MVPP2_CAUSE_FCS_ERR_MASK BIT(25) 271 #define MVPP2_CAUSE_TX_FIFO_UNDERRUN_MASK BIT(26) 272 #define MVPP2_CAUSE_TX_EXCEPTION_SUM_MASK BIT(29) 273 #define MVPP2_CAUSE_RX_EXCEPTION_SUM_MASK BIT(30) 274 #define MVPP2_CAUSE_MISC_SUM_MASK BIT(31) 275 #define MVPP2_ISR_RX_TX_MASK_REG(port) (0x54a0 + 4 * (port)) 276 #define MVPP2_ISR_PON_RX_TX_MASK_REG 0x54bc 277 #define MVPP2_PON_CAUSE_RXQ_OCCUP_DESC_ALL_MASK 0xffff 278 #define MVPP2_PON_CAUSE_TXP_OCCUP_DESC_ALL_MASK 0x3fc00000 279 #define MVPP2_PON_CAUSE_MISC_SUM_MASK BIT(31) 280 #define MVPP2_ISR_MISC_CAUSE_REG 0x55b0 281 282 /* Buffer Manager registers */ 283 #define MVPP2_BM_POOL_BASE_REG(pool) (0x6000 + ((pool) * 4)) 284 #define MVPP2_BM_POOL_BASE_ADDR_MASK 0xfffff80 285 #define MVPP2_BM_POOL_SIZE_REG(pool) (0x6040 + ((pool) * 4)) 286 #define MVPP2_BM_POOL_SIZE_MASK 0xfff0 287 #define MVPP2_BM_POOL_READ_PTR_REG(pool) (0x6080 + ((pool) * 4)) 288 #define MVPP2_BM_POOL_GET_READ_PTR_MASK 0xfff0 289 #define MVPP2_BM_POOL_PTRS_NUM_REG(pool) (0x60c0 + ((pool) * 4)) 290 #define MVPP2_BM_POOL_PTRS_NUM_MASK 0xfff0 291 #define MVPP2_BM_BPPI_READ_PTR_REG(pool) (0x6100 + ((pool) * 4)) 292 #define MVPP2_BM_BPPI_PTRS_NUM_REG(pool) (0x6140 + ((pool) * 4)) 293 #define MVPP2_BM_BPPI_PTR_NUM_MASK 0x7ff 294 #define MVPP22_BM_POOL_PTRS_NUM_MASK 0xfff8 295 #define MVPP2_BM_BPPI_PREFETCH_FULL_MASK BIT(16) 296 #define MVPP2_BM_POOL_CTRL_REG(pool) (0x6200 + ((pool) * 4)) 297 #define MVPP2_BM_START_MASK BIT(0) 298 #define MVPP2_BM_STOP_MASK BIT(1) 299 #define MVPP2_BM_STATE_MASK BIT(4) 300 #define MVPP2_BM_LOW_THRESH_OFFS 8 301 #define MVPP2_BM_LOW_THRESH_MASK 0x7f00 302 #define MVPP2_BM_LOW_THRESH_VALUE(val) ((val) << \ 303 MVPP2_BM_LOW_THRESH_OFFS) 304 #define MVPP2_BM_HIGH_THRESH_OFFS 16 305 #define MVPP2_BM_HIGH_THRESH_MASK 0x7f0000 306 #define MVPP2_BM_HIGH_THRESH_VALUE(val) ((val) << \ 307 MVPP2_BM_HIGH_THRESH_OFFS) 308 #define MVPP2_BM_INTR_CAUSE_REG(pool) (0x6240 + ((pool) * 4)) 309 #define MVPP2_BM_RELEASED_DELAY_MASK BIT(0) 310 #define MVPP2_BM_ALLOC_FAILED_MASK BIT(1) 311 #define MVPP2_BM_BPPE_EMPTY_MASK BIT(2) 312 #define MVPP2_BM_BPPE_FULL_MASK BIT(3) 313 #define MVPP2_BM_AVAILABLE_BP_LOW_MASK BIT(4) 314 #define MVPP2_BM_INTR_MASK_REG(pool) (0x6280 + ((pool) * 4)) 315 #define MVPP2_BM_PHY_ALLOC_REG(pool) (0x6400 + ((pool) * 4)) 316 #define MVPP2_BM_PHY_ALLOC_GRNTD_MASK BIT(0) 317 #define MVPP2_BM_VIRT_ALLOC_REG 0x6440 318 #define MVPP22_BM_ADDR_HIGH_ALLOC 0x6444 319 #define MVPP22_BM_ADDR_HIGH_PHYS_MASK 0xff 320 #define MVPP22_BM_ADDR_HIGH_VIRT_MASK 0xff00 321 #define MVPP22_BM_ADDR_HIGH_VIRT_SHIFT 8 322 #define MVPP2_BM_PHY_RLS_REG(pool) (0x6480 + ((pool) * 4)) 323 #define MVPP2_BM_PHY_RLS_MC_BUFF_MASK BIT(0) 324 #define MVPP2_BM_PHY_RLS_PRIO_EN_MASK BIT(1) 325 #define MVPP2_BM_PHY_RLS_GRNTD_MASK BIT(2) 326 #define MVPP2_BM_VIRT_RLS_REG 0x64c0 327 #define MVPP22_BM_ADDR_HIGH_RLS_REG 0x64c4 328 #define MVPP22_BM_ADDR_HIGH_PHYS_RLS_MASK 0xff 329 #define MVPP22_BM_ADDR_HIGH_VIRT_RLS_MASK 0xff00 330 #define MVPP22_BM_ADDR_HIGH_VIRT_RLS_SHIFT 8 331 332 /* Packet Processor per-port counters */ 333 #define MVPP2_OVERRUN_ETH_DROP 0x7000 334 #define MVPP2_CLS_ETH_DROP 0x7020 335 336 /* Hit counters registers */ 337 #define MVPP2_CTRS_IDX 0x7040 338 #define MVPP22_CTRS_TX_CTR(port, txq) ((txq) | ((port) << 3) | BIT(7)) 339 #define MVPP2_TX_DESC_ENQ_CTR 0x7100 340 #define MVPP2_TX_DESC_ENQ_TO_DDR_CTR 0x7104 341 #define MVPP2_TX_BUFF_ENQ_TO_DDR_CTR 0x7108 342 #define MVPP2_TX_DESC_ENQ_HW_FWD_CTR 0x710c 343 #define MVPP2_RX_DESC_ENQ_CTR 0x7120 344 #define MVPP2_TX_PKTS_DEQ_CTR 0x7130 345 #define MVPP2_TX_PKTS_FULL_QUEUE_DROP_CTR 0x7200 346 #define MVPP2_TX_PKTS_EARLY_DROP_CTR 0x7204 347 #define MVPP2_TX_PKTS_BM_DROP_CTR 0x7208 348 #define MVPP2_TX_PKTS_BM_MC_DROP_CTR 0x720c 349 #define MVPP2_RX_PKTS_FULL_QUEUE_DROP_CTR 0x7220 350 #define MVPP2_RX_PKTS_EARLY_DROP_CTR 0x7224 351 #define MVPP2_RX_PKTS_BM_DROP_CTR 0x7228 352 #define MVPP2_CLS_DEC_TBL_HIT_CTR 0x7700 353 #define MVPP2_CLS_FLOW_TBL_HIT_CTR 0x7704 354 355 /* TX Scheduler registers */ 356 #define MVPP2_TXP_SCHED_PORT_INDEX_REG 0x8000 357 #define MVPP2_TXP_SCHED_Q_CMD_REG 0x8004 358 #define MVPP2_TXP_SCHED_ENQ_MASK 0xff 359 #define MVPP2_TXP_SCHED_DISQ_OFFSET 8 360 #define MVPP2_TXP_SCHED_CMD_1_REG 0x8010 361 #define MVPP2_TXP_SCHED_FIXED_PRIO_REG 0x8014 362 #define MVPP2_TXP_SCHED_PERIOD_REG 0x8018 363 #define MVPP2_TXP_SCHED_MTU_REG 0x801c 364 #define MVPP2_TXP_MTU_MAX 0x7FFFF 365 #define MVPP2_TXP_SCHED_REFILL_REG 0x8020 366 #define MVPP2_TXP_REFILL_TOKENS_ALL_MASK 0x7ffff 367 #define MVPP2_TXP_REFILL_PERIOD_ALL_MASK 0x3ff00000 368 #define MVPP2_TXP_REFILL_PERIOD_MASK(v) ((v) << 20) 369 #define MVPP2_TXP_SCHED_TOKEN_SIZE_REG 0x8024 370 #define MVPP2_TXP_TOKEN_SIZE_MAX 0xffffffff 371 #define MVPP2_TXQ_SCHED_REFILL_REG(q) (0x8040 + ((q) << 2)) 372 #define MVPP2_TXQ_REFILL_TOKENS_ALL_MASK 0x7ffff 373 #define MVPP2_TXQ_REFILL_PERIOD_ALL_MASK 0x3ff00000 374 #define MVPP2_TXQ_REFILL_PERIOD_MASK(v) ((v) << 20) 375 #define MVPP2_TXQ_SCHED_TOKEN_SIZE_REG(q) (0x8060 + ((q) << 2)) 376 #define MVPP2_TXQ_TOKEN_SIZE_MAX 0x7fffffff 377 #define MVPP2_TXQ_SCHED_TOKEN_CNTR_REG(q) (0x8080 + ((q) << 2)) 378 #define MVPP2_TXQ_TOKEN_CNTR_MAX 0xffffffff 379 380 /* TX general registers */ 381 #define MVPP2_TX_SNOOP_REG 0x8800 382 #define MVPP2_TX_PORT_FLUSH_REG 0x8810 383 #define MVPP2_TX_PORT_FLUSH_MASK(port) (1 << (port)) 384 385 /* LMS registers */ 386 #define MVPP2_SRC_ADDR_MIDDLE 0x24 387 #define MVPP2_SRC_ADDR_HIGH 0x28 388 #define MVPP2_PHY_AN_CFG0_REG 0x34 389 #define MVPP2_PHY_AN_STOP_SMI0_MASK BIT(7) 390 #define MVPP2_MNG_EXTENDED_GLOBAL_CTRL_REG 0x305c 391 #define MVPP2_EXT_GLOBAL_CTRL_DEFAULT 0x27 392 393 /* Per-port registers */ 394 #define MVPP2_GMAC_CTRL_0_REG 0x0 395 #define MVPP2_GMAC_PORT_EN_MASK BIT(0) 396 #define MVPP2_GMAC_PORT_TYPE_MASK BIT(1) 397 #define MVPP2_GMAC_MAX_RX_SIZE_OFFS 2 398 #define MVPP2_GMAC_MAX_RX_SIZE_MASK 0x7ffc 399 #define MVPP2_GMAC_MIB_CNTR_EN_MASK BIT(15) 400 #define MVPP2_GMAC_CTRL_1_REG 0x4 401 #define MVPP2_GMAC_PERIODIC_XON_EN_MASK BIT(1) 402 #define MVPP2_GMAC_GMII_LB_EN_MASK BIT(5) 403 #define MVPP2_GMAC_PCS_LB_EN_BIT 6 404 #define MVPP2_GMAC_PCS_LB_EN_MASK BIT(6) 405 #define MVPP2_GMAC_SA_LOW_OFFS 7 406 #define MVPP2_GMAC_CTRL_2_REG 0x8 407 #define MVPP2_GMAC_INBAND_AN_MASK BIT(0) 408 #define MVPP2_GMAC_FLOW_CTRL_MASK GENMASK(2, 1) 409 #define MVPP2_GMAC_PCS_ENABLE_MASK BIT(3) 410 #define MVPP2_GMAC_INTERNAL_CLK_MASK BIT(4) 411 #define MVPP2_GMAC_DISABLE_PADDING BIT(5) 412 #define MVPP2_GMAC_PORT_RESET_MASK BIT(6) 413 #define MVPP2_GMAC_AUTONEG_CONFIG 0xc 414 #define MVPP2_GMAC_FORCE_LINK_DOWN BIT(0) 415 #define MVPP2_GMAC_FORCE_LINK_PASS BIT(1) 416 #define MVPP2_GMAC_IN_BAND_AUTONEG BIT(2) 417 #define MVPP2_GMAC_IN_BAND_AUTONEG_BYPASS BIT(3) 418 #define MVPP2_GMAC_IN_BAND_RESTART_AN BIT(4) 419 #define MVPP2_GMAC_CONFIG_MII_SPEED BIT(5) 420 #define MVPP2_GMAC_CONFIG_GMII_SPEED BIT(6) 421 #define MVPP2_GMAC_AN_SPEED_EN BIT(7) 422 #define MVPP2_GMAC_FC_ADV_EN BIT(9) 423 #define MVPP2_GMAC_FC_ADV_ASM_EN BIT(10) 424 #define MVPP2_GMAC_FLOW_CTRL_AUTONEG BIT(11) 425 #define MVPP2_GMAC_CONFIG_FULL_DUPLEX BIT(12) 426 #define MVPP2_GMAC_AN_DUPLEX_EN BIT(13) 427 #define MVPP2_GMAC_STATUS0 0x10 428 #define MVPP2_GMAC_STATUS0_LINK_UP BIT(0) 429 #define MVPP2_GMAC_STATUS0_GMII_SPEED BIT(1) 430 #define MVPP2_GMAC_STATUS0_MII_SPEED BIT(2) 431 #define MVPP2_GMAC_STATUS0_FULL_DUPLEX BIT(3) 432 #define MVPP2_GMAC_STATUS0_RX_PAUSE BIT(4) 433 #define MVPP2_GMAC_STATUS0_TX_PAUSE BIT(5) 434 #define MVPP2_GMAC_STATUS0_AN_COMPLETE BIT(11) 435 #define MVPP2_GMAC_PORT_FIFO_CFG_1_REG 0x1c 436 #define MVPP2_GMAC_TX_FIFO_MIN_TH_OFFS 6 437 #define MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK 0x1fc0 438 #define MVPP2_GMAC_TX_FIFO_MIN_TH_MASK(v) (((v) << 6) & \ 439 MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK) 440 #define MVPP22_GMAC_INT_STAT 0x20 441 #define MVPP22_GMAC_INT_STAT_LINK BIT(1) 442 #define MVPP22_GMAC_INT_MASK 0x24 443 #define MVPP22_GMAC_INT_MASK_LINK_STAT BIT(1) 444 #define MVPP22_GMAC_CTRL_4_REG 0x90 445 #define MVPP22_CTRL4_EXT_PIN_GMII_SEL BIT(0) 446 #define MVPP22_CTRL4_RX_FC_EN BIT(3) 447 #define MVPP22_CTRL4_TX_FC_EN BIT(4) 448 #define MVPP22_CTRL4_DP_CLK_SEL BIT(5) 449 #define MVPP22_CTRL4_SYNC_BYPASS_DIS BIT(6) 450 #define MVPP22_CTRL4_QSGMII_BYPASS_ACTIVE BIT(7) 451 #define MVPP22_GMAC_INT_SUM_MASK 0xa4 452 #define MVPP22_GMAC_INT_SUM_MASK_LINK_STAT BIT(1) 453 454 /* Per-port XGMAC registers. PPv2.2 only, only for GOP port 0, 455 * relative to port->base. 456 */ 457 #define MVPP22_XLG_CTRL0_REG 0x100 458 #define MVPP22_XLG_CTRL0_PORT_EN BIT(0) 459 #define MVPP22_XLG_CTRL0_MAC_RESET_DIS BIT(1) 460 #define MVPP22_XLG_CTRL0_FORCE_LINK_DOWN BIT(2) 461 #define MVPP22_XLG_CTRL0_FORCE_LINK_PASS BIT(3) 462 #define MVPP22_XLG_CTRL0_RX_FLOW_CTRL_EN BIT(7) 463 #define MVPP22_XLG_CTRL0_TX_FLOW_CTRL_EN BIT(8) 464 #define MVPP22_XLG_CTRL0_MIB_CNT_DIS BIT(14) 465 #define MVPP22_XLG_CTRL1_REG 0x104 466 #define MVPP22_XLG_CTRL1_FRAMESIZELIMIT_OFFS 0 467 #define MVPP22_XLG_CTRL1_FRAMESIZELIMIT_MASK 0x1fff 468 #define MVPP22_XLG_STATUS 0x10c 469 #define MVPP22_XLG_STATUS_LINK_UP BIT(0) 470 #define MVPP22_XLG_INT_STAT 0x114 471 #define MVPP22_XLG_INT_STAT_LINK BIT(1) 472 #define MVPP22_XLG_INT_MASK 0x118 473 #define MVPP22_XLG_INT_MASK_LINK BIT(1) 474 #define MVPP22_XLG_CTRL3_REG 0x11c 475 #define MVPP22_XLG_CTRL3_MACMODESELECT_MASK (7 << 13) 476 #define MVPP22_XLG_CTRL3_MACMODESELECT_GMAC (0 << 13) 477 #define MVPP22_XLG_CTRL3_MACMODESELECT_10G (1 << 13) 478 #define MVPP22_XLG_EXT_INT_MASK 0x15c 479 #define MVPP22_XLG_EXT_INT_MASK_XLG BIT(1) 480 #define MVPP22_XLG_EXT_INT_MASK_GIG BIT(2) 481 #define MVPP22_XLG_CTRL4_REG 0x184 482 #define MVPP22_XLG_CTRL4_FWD_FC BIT(5) 483 #define MVPP22_XLG_CTRL4_FWD_PFC BIT(6) 484 #define MVPP22_XLG_CTRL4_MACMODSELECT_GMAC BIT(12) 485 #define MVPP22_XLG_CTRL4_EN_IDLE_CHECK BIT(14) 486 487 /* SMI registers. PPv2.2 only, relative to priv->iface_base. */ 488 #define MVPP22_SMI_MISC_CFG_REG 0x1204 489 #define MVPP22_SMI_POLLING_EN BIT(10) 490 491 #define MVPP22_GMAC_BASE(port) (0x7000 + (port) * 0x1000 + 0xe00) 492 493 #define MVPP2_CAUSE_TXQ_SENT_DESC_ALL_MASK 0xff 494 495 /* Descriptor ring Macros */ 496 #define MVPP2_QUEUE_NEXT_DESC(q, index) \ 497 (((index) < (q)->last_desc) ? ((index) + 1) : 0) 498 499 /* XPCS registers. PPv2.2 only */ 500 #define MVPP22_MPCS_BASE(port) (0x7000 + (port) * 0x1000) 501 #define MVPP22_MPCS_CTRL 0x14 502 #define MVPP22_MPCS_CTRL_FWD_ERR_CONN BIT(10) 503 #define MVPP22_MPCS_CLK_RESET 0x14c 504 #define MAC_CLK_RESET_SD_TX BIT(0) 505 #define MAC_CLK_RESET_SD_RX BIT(1) 506 #define MAC_CLK_RESET_MAC BIT(2) 507 #define MVPP22_MPCS_CLK_RESET_DIV_RATIO(n) ((n) << 4) 508 #define MVPP22_MPCS_CLK_RESET_DIV_SET BIT(11) 509 510 /* XPCS registers. PPv2.2 only */ 511 #define MVPP22_XPCS_BASE(port) (0x7400 + (port) * 0x1000) 512 #define MVPP22_XPCS_CFG0 0x0 513 #define MVPP22_XPCS_CFG0_RESET_DIS BIT(0) 514 #define MVPP22_XPCS_CFG0_PCS_MODE(n) ((n) << 3) 515 #define MVPP22_XPCS_CFG0_ACTIVE_LANE(n) ((n) << 5) 516 517 /* System controller registers. Accessed through a regmap. */ 518 #define GENCONF_SOFT_RESET1 0x1108 519 #define GENCONF_SOFT_RESET1_GOP BIT(6) 520 #define GENCONF_PORT_CTRL0 0x1110 521 #define GENCONF_PORT_CTRL0_BUS_WIDTH_SELECT BIT(1) 522 #define GENCONF_PORT_CTRL0_RX_DATA_SAMPLE BIT(29) 523 #define GENCONF_PORT_CTRL0_CLK_DIV_PHASE_CLR BIT(31) 524 #define GENCONF_PORT_CTRL1 0x1114 525 #define GENCONF_PORT_CTRL1_EN(p) BIT(p) 526 #define GENCONF_PORT_CTRL1_RESET(p) (BIT(p) << 28) 527 #define GENCONF_CTRL0 0x1120 528 #define GENCONF_CTRL0_PORT0_RGMII BIT(0) 529 #define GENCONF_CTRL0_PORT1_RGMII_MII BIT(1) 530 #define GENCONF_CTRL0_PORT1_RGMII BIT(2) 531 532 /* Various constants */ 533 534 /* Coalescing */ 535 #define MVPP2_TXDONE_COAL_PKTS_THRESH 64 536 #define MVPP2_TXDONE_HRTIMER_PERIOD_NS 1000000UL 537 #define MVPP2_TXDONE_COAL_USEC 1000 538 #define MVPP2_RX_COAL_PKTS 32 539 #define MVPP2_RX_COAL_USEC 64 540 541 /* The two bytes Marvell header. Either contains a special value used 542 * by Marvell switches when a specific hardware mode is enabled (not 543 * supported by this driver) or is filled automatically by zeroes on 544 * the RX side. Those two bytes being at the front of the Ethernet 545 * header, they allow to have the IP header aligned on a 4 bytes 546 * boundary automatically: the hardware skips those two bytes on its 547 * own. 548 */ 549 #define MVPP2_MH_SIZE 2 550 #define MVPP2_ETH_TYPE_LEN 2 551 #define MVPP2_PPPOE_HDR_SIZE 8 552 #define MVPP2_VLAN_TAG_LEN 4 553 #define MVPP2_VLAN_TAG_EDSA_LEN 8 554 555 /* Lbtd 802.3 type */ 556 #define MVPP2_IP_LBDT_TYPE 0xfffa 557 558 #define MVPP2_TX_CSUM_MAX_SIZE 9800 559 560 /* Timeout constants */ 561 #define MVPP2_TX_DISABLE_TIMEOUT_MSEC 1000 562 #define MVPP2_TX_PENDING_TIMEOUT_MSEC 1000 563 564 #define MVPP2_TX_MTU_MAX 0x7ffff 565 566 /* Maximum number of T-CONTs of PON port */ 567 #define MVPP2_MAX_TCONT 16 568 569 /* Maximum number of supported ports */ 570 #define MVPP2_MAX_PORTS 4 571 572 /* Maximum number of TXQs used by single port */ 573 #define MVPP2_MAX_TXQ 8 574 575 /* MVPP2_MAX_TSO_SEGS is the maximum number of fragments to allow in the GSO 576 * skb. As we need a maxium of two descriptors per fragments (1 header, 1 data), 577 * multiply this value by two to count the maximum number of skb descs needed. 578 */ 579 #define MVPP2_MAX_TSO_SEGS 300 580 #define MVPP2_MAX_SKB_DESCS (MVPP2_MAX_TSO_SEGS * 2 + MAX_SKB_FRAGS) 581 582 /* Max number of RXQs per port */ 583 #define MVPP2_PORT_MAX_RXQ 32 584 585 /* Max number of Rx descriptors */ 586 #define MVPP2_MAX_RXD_MAX 1024 587 #define MVPP2_MAX_RXD_DFLT 128 588 589 /* Max number of Tx descriptors */ 590 #define MVPP2_MAX_TXD_MAX 2048 591 #define MVPP2_MAX_TXD_DFLT 1024 592 593 /* Amount of Tx descriptors that can be reserved at once by CPU */ 594 #define MVPP2_CPU_DESC_CHUNK 64 595 596 /* Max number of Tx descriptors in each aggregated queue */ 597 #define MVPP2_AGGR_TXQ_SIZE 256 598 599 /* Descriptor aligned size */ 600 #define MVPP2_DESC_ALIGNED_SIZE 32 601 602 /* Descriptor alignment mask */ 603 #define MVPP2_TX_DESC_ALIGN (MVPP2_DESC_ALIGNED_SIZE - 1) 604 605 /* RX FIFO constants */ 606 #define MVPP2_RX_FIFO_PORT_DATA_SIZE_32KB 0x8000 607 #define MVPP2_RX_FIFO_PORT_DATA_SIZE_8KB 0x2000 608 #define MVPP2_RX_FIFO_PORT_DATA_SIZE_4KB 0x1000 609 #define MVPP2_RX_FIFO_PORT_ATTR_SIZE_32KB 0x200 610 #define MVPP2_RX_FIFO_PORT_ATTR_SIZE_8KB 0x80 611 #define MVPP2_RX_FIFO_PORT_ATTR_SIZE_4KB 0x40 612 #define MVPP2_RX_FIFO_PORT_MIN_PKT 0x80 613 614 /* TX FIFO constants */ 615 #define MVPP22_TX_FIFO_DATA_SIZE_10KB 0xa 616 #define MVPP22_TX_FIFO_DATA_SIZE_3KB 0x3 617 #define MVPP2_TX_FIFO_THRESHOLD_MIN 256 618 #define MVPP2_TX_FIFO_THRESHOLD_10KB \ 619 (MVPP22_TX_FIFO_DATA_SIZE_10KB * 1024 - MVPP2_TX_FIFO_THRESHOLD_MIN) 620 #define MVPP2_TX_FIFO_THRESHOLD_3KB \ 621 (MVPP22_TX_FIFO_DATA_SIZE_3KB * 1024 - MVPP2_TX_FIFO_THRESHOLD_MIN) 622 623 /* RX buffer constants */ 624 #define MVPP2_SKB_SHINFO_SIZE \ 625 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) 626 627 #define MVPP2_RX_PKT_SIZE(mtu) \ 628 ALIGN((mtu) + MVPP2_MH_SIZE + MVPP2_VLAN_TAG_LEN + \ 629 ETH_HLEN + ETH_FCS_LEN, cache_line_size()) 630 631 #define MVPP2_RX_BUF_SIZE(pkt_size) ((pkt_size) + NET_SKB_PAD) 632 #define MVPP2_RX_TOTAL_SIZE(buf_size) ((buf_size) + MVPP2_SKB_SHINFO_SIZE) 633 #define MVPP2_RX_MAX_PKT_SIZE(total_size) \ 634 ((total_size) - NET_SKB_PAD - MVPP2_SKB_SHINFO_SIZE) 635 636 #define MVPP2_BIT_TO_BYTE(bit) ((bit) / 8) 637 #define MVPP2_BIT_TO_WORD(bit) ((bit) / 32) 638 #define MVPP2_BIT_IN_WORD(bit) ((bit) % 32) 639 640 #define MVPP2_N_PRS_FLOWS 52 641 #define MVPP2_N_RFS_ENTRIES_PER_FLOW 4 642 643 /* There are 7 supported high-level flows */ 644 #define MVPP2_N_RFS_RULES (MVPP2_N_RFS_ENTRIES_PER_FLOW * 7) 645 646 /* RSS constants */ 647 #define MVPP22_N_RSS_TABLES 8 648 #define MVPP22_RSS_TABLE_ENTRIES 32 649 650 /* IPv6 max L3 address size */ 651 #define MVPP2_MAX_L3_ADDR_SIZE 16 652 653 /* Port flags */ 654 #define MVPP2_F_LOOPBACK BIT(0) 655 #define MVPP2_F_DT_COMPAT BIT(1) 656 657 /* Marvell tag types */ 658 enum mvpp2_tag_type { 659 MVPP2_TAG_TYPE_NONE = 0, 660 MVPP2_TAG_TYPE_MH = 1, 661 MVPP2_TAG_TYPE_DSA = 2, 662 MVPP2_TAG_TYPE_EDSA = 3, 663 MVPP2_TAG_TYPE_VLAN = 4, 664 MVPP2_TAG_TYPE_LAST = 5 665 }; 666 667 /* L2 cast enum */ 668 enum mvpp2_prs_l2_cast { 669 MVPP2_PRS_L2_UNI_CAST, 670 MVPP2_PRS_L2_MULTI_CAST, 671 }; 672 673 /* L3 cast enum */ 674 enum mvpp2_prs_l3_cast { 675 MVPP2_PRS_L3_UNI_CAST, 676 MVPP2_PRS_L3_MULTI_CAST, 677 MVPP2_PRS_L3_BROAD_CAST 678 }; 679 680 /* BM constants */ 681 #define MVPP2_BM_JUMBO_BUF_NUM 512 682 #define MVPP2_BM_LONG_BUF_NUM 1024 683 #define MVPP2_BM_SHORT_BUF_NUM 2048 684 #define MVPP2_BM_POOL_SIZE_MAX (16*1024 - MVPP2_BM_POOL_PTR_ALIGN/4) 685 #define MVPP2_BM_POOL_PTR_ALIGN 128 686 #define MVPP2_BM_MAX_POOLS 8 687 688 /* BM cookie (32 bits) definition */ 689 #define MVPP2_BM_COOKIE_POOL_OFFS 8 690 #define MVPP2_BM_COOKIE_CPU_OFFS 24 691 692 #define MVPP2_BM_SHORT_FRAME_SIZE 512 693 #define MVPP2_BM_LONG_FRAME_SIZE 2048 694 #define MVPP2_BM_JUMBO_FRAME_SIZE 10240 695 /* BM short pool packet size 696 * These value assure that for SWF the total number 697 * of bytes allocated for each buffer will be 512 698 */ 699 #define MVPP2_BM_SHORT_PKT_SIZE MVPP2_RX_MAX_PKT_SIZE(MVPP2_BM_SHORT_FRAME_SIZE) 700 #define MVPP2_BM_LONG_PKT_SIZE MVPP2_RX_MAX_PKT_SIZE(MVPP2_BM_LONG_FRAME_SIZE) 701 #define MVPP2_BM_JUMBO_PKT_SIZE MVPP2_RX_MAX_PKT_SIZE(MVPP2_BM_JUMBO_FRAME_SIZE) 702 703 #define MVPP21_ADDR_SPACE_SZ 0 704 #define MVPP22_ADDR_SPACE_SZ SZ_64K 705 706 #define MVPP2_MAX_THREADS 9 707 #define MVPP2_MAX_QVECS MVPP2_MAX_THREADS 708 709 /* GMAC MIB Counters register definitions */ 710 #define MVPP21_MIB_COUNTERS_OFFSET 0x1000 711 #define MVPP21_MIB_COUNTERS_PORT_SZ 0x400 712 #define MVPP22_MIB_COUNTERS_OFFSET 0x0 713 #define MVPP22_MIB_COUNTERS_PORT_SZ 0x100 714 715 #define MVPP2_MIB_GOOD_OCTETS_RCVD 0x0 716 #define MVPP2_MIB_BAD_OCTETS_RCVD 0x8 717 #define MVPP2_MIB_CRC_ERRORS_SENT 0xc 718 #define MVPP2_MIB_UNICAST_FRAMES_RCVD 0x10 719 #define MVPP2_MIB_BROADCAST_FRAMES_RCVD 0x18 720 #define MVPP2_MIB_MULTICAST_FRAMES_RCVD 0x1c 721 #define MVPP2_MIB_FRAMES_64_OCTETS 0x20 722 #define MVPP2_MIB_FRAMES_65_TO_127_OCTETS 0x24 723 #define MVPP2_MIB_FRAMES_128_TO_255_OCTETS 0x28 724 #define MVPP2_MIB_FRAMES_256_TO_511_OCTETS 0x2c 725 #define MVPP2_MIB_FRAMES_512_TO_1023_OCTETS 0x30 726 #define MVPP2_MIB_FRAMES_1024_TO_MAX_OCTETS 0x34 727 #define MVPP2_MIB_GOOD_OCTETS_SENT 0x38 728 #define MVPP2_MIB_UNICAST_FRAMES_SENT 0x40 729 #define MVPP2_MIB_MULTICAST_FRAMES_SENT 0x48 730 #define MVPP2_MIB_BROADCAST_FRAMES_SENT 0x4c 731 #define MVPP2_MIB_FC_SENT 0x54 732 #define MVPP2_MIB_FC_RCVD 0x58 733 #define MVPP2_MIB_RX_FIFO_OVERRUN 0x5c 734 #define MVPP2_MIB_UNDERSIZE_RCVD 0x60 735 #define MVPP2_MIB_FRAGMENTS_RCVD 0x64 736 #define MVPP2_MIB_OVERSIZE_RCVD 0x68 737 #define MVPP2_MIB_JABBER_RCVD 0x6c 738 #define MVPP2_MIB_MAC_RCV_ERROR 0x70 739 #define MVPP2_MIB_BAD_CRC_EVENT 0x74 740 #define MVPP2_MIB_COLLISION 0x78 741 #define MVPP2_MIB_LATE_COLLISION 0x7c 742 743 #define MVPP2_MIB_COUNTERS_STATS_DELAY (1 * HZ) 744 745 #define MVPP2_DESC_DMA_MASK DMA_BIT_MASK(40) 746 747 /* Definitions */ 748 struct mvpp2_dbgfs_entries; 749 750 struct mvpp2_rss_table { 751 u32 indir[MVPP22_RSS_TABLE_ENTRIES]; 752 }; 753 754 /* Shared Packet Processor resources */ 755 struct mvpp2 { 756 /* Shared registers' base addresses */ 757 void __iomem *lms_base; 758 void __iomem *iface_base; 759 760 /* On PPv2.2, each "software thread" can access the base 761 * register through a separate address space, each 64 KB apart 762 * from each other. Typically, such address spaces will be 763 * used per CPU. 764 */ 765 void __iomem *swth_base[MVPP2_MAX_THREADS]; 766 767 /* On PPv2.2, some port control registers are located into the system 768 * controller space. These registers are accessible through a regmap. 769 */ 770 struct regmap *sysctrl_base; 771 772 /* Common clocks */ 773 struct clk *pp_clk; 774 struct clk *gop_clk; 775 struct clk *mg_clk; 776 struct clk *mg_core_clk; 777 struct clk *axi_clk; 778 779 /* List of pointers to port structures */ 780 int port_count; 781 struct mvpp2_port *port_list[MVPP2_MAX_PORTS]; 782 783 /* Number of Tx threads used */ 784 unsigned int nthreads; 785 /* Map of threads needing locking */ 786 unsigned long lock_map; 787 788 /* Aggregated TXQs */ 789 struct mvpp2_tx_queue *aggr_txqs; 790 791 /* Are we using page_pool with per-cpu pools? */ 792 int percpu_pools; 793 794 /* BM pools */ 795 struct mvpp2_bm_pool *bm_pools; 796 797 /* PRS shadow table */ 798 struct mvpp2_prs_shadow *prs_shadow; 799 /* PRS auxiliary table for double vlan entries control */ 800 bool *prs_double_vlans; 801 802 /* Tclk value */ 803 u32 tclk; 804 805 /* HW version */ 806 enum { MVPP21, MVPP22 } hw_version; 807 808 /* Maximum number of RXQs per port */ 809 unsigned int max_port_rxqs; 810 811 /* Workqueue to gather hardware statistics */ 812 char queue_name[30]; 813 struct workqueue_struct *stats_queue; 814 815 /* Debugfs root entry */ 816 struct dentry *dbgfs_dir; 817 818 /* Debugfs entries private data */ 819 struct mvpp2_dbgfs_entries *dbgfs_entries; 820 821 /* RSS Indirection tables */ 822 struct mvpp2_rss_table *rss_tables[MVPP22_N_RSS_TABLES]; 823 }; 824 825 struct mvpp2_pcpu_stats { 826 struct u64_stats_sync syncp; 827 u64 rx_packets; 828 u64 rx_bytes; 829 u64 tx_packets; 830 u64 tx_bytes; 831 }; 832 833 /* Per-CPU port control */ 834 struct mvpp2_port_pcpu { 835 struct hrtimer tx_done_timer; 836 struct net_device *dev; 837 bool timer_scheduled; 838 }; 839 840 struct mvpp2_queue_vector { 841 int irq; 842 struct napi_struct napi; 843 enum { MVPP2_QUEUE_VECTOR_SHARED, MVPP2_QUEUE_VECTOR_PRIVATE } type; 844 int sw_thread_id; 845 u16 sw_thread_mask; 846 int first_rxq; 847 int nrxqs; 848 u32 pending_cause_rx; 849 struct mvpp2_port *port; 850 struct cpumask *mask; 851 }; 852 853 /* Internal represention of a Flow Steering rule */ 854 struct mvpp2_rfs_rule { 855 /* Rule location inside the flow*/ 856 int loc; 857 858 /* Flow type, such as TCP_V4_FLOW, IP6_FLOW, etc. */ 859 int flow_type; 860 861 /* Index of the C2 TCAM entry handling this rule */ 862 int c2_index; 863 864 /* Header fields that needs to be extracted to match this flow */ 865 u16 hek_fields; 866 867 /* CLS engine : only c2 is supported for now. */ 868 u8 engine; 869 870 /* TCAM key and mask for C2-based steering. These fields should be 871 * encapsulated in a union should we add more engines. 872 */ 873 u64 c2_tcam; 874 u64 c2_tcam_mask; 875 876 struct flow_rule *flow; 877 }; 878 879 struct mvpp2_ethtool_fs { 880 struct mvpp2_rfs_rule rule; 881 struct ethtool_rxnfc rxnfc; 882 }; 883 884 struct mvpp2_port { 885 u8 id; 886 887 /* Index of the port from the "group of ports" complex point 888 * of view. This is specific to PPv2.2. 889 */ 890 int gop_id; 891 892 int link_irq; 893 894 struct mvpp2 *priv; 895 896 /* Firmware node associated to the port */ 897 struct fwnode_handle *fwnode; 898 899 /* Is a PHY always connected to the port */ 900 bool has_phy; 901 902 /* Per-port registers' base address */ 903 void __iomem *base; 904 void __iomem *stats_base; 905 906 struct mvpp2_rx_queue **rxqs; 907 unsigned int nrxqs; 908 struct mvpp2_tx_queue **txqs; 909 unsigned int ntxqs; 910 struct net_device *dev; 911 912 int pkt_size; 913 914 /* Per-CPU port control */ 915 struct mvpp2_port_pcpu __percpu *pcpu; 916 917 /* Protect the BM refills and the Tx paths when a thread is used on more 918 * than a single CPU. 919 */ 920 spinlock_t bm_lock[MVPP2_MAX_THREADS]; 921 spinlock_t tx_lock[MVPP2_MAX_THREADS]; 922 923 /* Flags */ 924 unsigned long flags; 925 926 u16 tx_ring_size; 927 u16 rx_ring_size; 928 struct mvpp2_pcpu_stats __percpu *stats; 929 u64 *ethtool_stats; 930 931 /* Per-port work and its lock to gather hardware statistics */ 932 struct mutex gather_stats_lock; 933 struct delayed_work stats_work; 934 935 struct device_node *of_node; 936 937 phy_interface_t phy_interface; 938 struct phylink *phylink; 939 struct phylink_config phylink_config; 940 struct phy *comphy; 941 942 struct mvpp2_bm_pool *pool_long; 943 struct mvpp2_bm_pool *pool_short; 944 945 /* Index of first port's physical RXQ */ 946 u8 first_rxq; 947 948 struct mvpp2_queue_vector qvecs[MVPP2_MAX_QVECS]; 949 unsigned int nqvecs; 950 bool has_tx_irqs; 951 952 u32 tx_time_coal; 953 954 /* List of steering rules active on that port */ 955 struct mvpp2_ethtool_fs *rfs_rules[MVPP2_N_RFS_ENTRIES_PER_FLOW]; 956 int n_rfs_rules; 957 958 /* Each port has its own view of the rss contexts, so that it can number 959 * them from 0 960 */ 961 int rss_ctx[MVPP22_N_RSS_TABLES]; 962 }; 963 964 /* The mvpp2_tx_desc and mvpp2_rx_desc structures describe the 965 * layout of the transmit and reception DMA descriptors, and their 966 * layout is therefore defined by the hardware design 967 */ 968 969 #define MVPP2_TXD_L3_OFF_SHIFT 0 970 #define MVPP2_TXD_IP_HLEN_SHIFT 8 971 #define MVPP2_TXD_L4_CSUM_FRAG BIT(13) 972 #define MVPP2_TXD_L4_CSUM_NOT BIT(14) 973 #define MVPP2_TXD_IP_CSUM_DISABLE BIT(15) 974 #define MVPP2_TXD_PADDING_DISABLE BIT(23) 975 #define MVPP2_TXD_L4_UDP BIT(24) 976 #define MVPP2_TXD_L3_IP6 BIT(26) 977 #define MVPP2_TXD_L_DESC BIT(28) 978 #define MVPP2_TXD_F_DESC BIT(29) 979 980 #define MVPP2_RXD_ERR_SUMMARY BIT(15) 981 #define MVPP2_RXD_ERR_CODE_MASK (BIT(13) | BIT(14)) 982 #define MVPP2_RXD_ERR_CRC 0x0 983 #define MVPP2_RXD_ERR_OVERRUN BIT(13) 984 #define MVPP2_RXD_ERR_RESOURCE (BIT(13) | BIT(14)) 985 #define MVPP2_RXD_BM_POOL_ID_OFFS 16 986 #define MVPP2_RXD_BM_POOL_ID_MASK (BIT(16) | BIT(17) | BIT(18)) 987 #define MVPP2_RXD_HWF_SYNC BIT(21) 988 #define MVPP2_RXD_L4_CSUM_OK BIT(22) 989 #define MVPP2_RXD_IP4_HEADER_ERR BIT(24) 990 #define MVPP2_RXD_L4_TCP BIT(25) 991 #define MVPP2_RXD_L4_UDP BIT(26) 992 #define MVPP2_RXD_L3_IP4 BIT(28) 993 #define MVPP2_RXD_L3_IP6 BIT(30) 994 #define MVPP2_RXD_BUF_HDR BIT(31) 995 996 /* HW TX descriptor for PPv2.1 */ 997 struct mvpp21_tx_desc { 998 __le32 command; /* Options used by HW for packet transmitting.*/ 999 u8 packet_offset; /* the offset from the buffer beginning */ 1000 u8 phys_txq; /* destination queue ID */ 1001 __le16 data_size; /* data size of transmitted packet in bytes */ 1002 __le32 buf_dma_addr; /* physical addr of transmitted buffer */ 1003 __le32 buf_cookie; /* cookie for access to TX buffer in tx path */ 1004 __le32 reserved1[3]; /* hw_cmd (for future use, BM, PON, PNC) */ 1005 __le32 reserved2; /* reserved (for future use) */ 1006 }; 1007 1008 /* HW RX descriptor for PPv2.1 */ 1009 struct mvpp21_rx_desc { 1010 __le32 status; /* info about received packet */ 1011 __le16 reserved1; /* parser_info (for future use, PnC) */ 1012 __le16 data_size; /* size of received packet in bytes */ 1013 __le32 buf_dma_addr; /* physical address of the buffer */ 1014 __le32 buf_cookie; /* cookie for access to RX buffer in rx path */ 1015 __le16 reserved2; /* gem_port_id (for future use, PON) */ 1016 __le16 reserved3; /* csum_l4 (for future use, PnC) */ 1017 u8 reserved4; /* bm_qset (for future use, BM) */ 1018 u8 reserved5; 1019 __le16 reserved6; /* classify_info (for future use, PnC) */ 1020 __le32 reserved7; /* flow_id (for future use, PnC) */ 1021 __le32 reserved8; 1022 }; 1023 1024 /* HW TX descriptor for PPv2.2 */ 1025 struct mvpp22_tx_desc { 1026 __le32 command; 1027 u8 packet_offset; 1028 u8 phys_txq; 1029 __le16 data_size; 1030 __le64 reserved1; 1031 __le64 buf_dma_addr_ptp; 1032 __le64 buf_cookie_misc; 1033 }; 1034 1035 /* HW RX descriptor for PPv2.2 */ 1036 struct mvpp22_rx_desc { 1037 __le32 status; 1038 __le16 reserved1; 1039 __le16 data_size; 1040 __le32 reserved2; 1041 __le32 reserved3; 1042 __le64 buf_dma_addr_key_hash; 1043 __le64 buf_cookie_misc; 1044 }; 1045 1046 /* Opaque type used by the driver to manipulate the HW TX and RX 1047 * descriptors 1048 */ 1049 struct mvpp2_tx_desc { 1050 union { 1051 struct mvpp21_tx_desc pp21; 1052 struct mvpp22_tx_desc pp22; 1053 }; 1054 }; 1055 1056 struct mvpp2_rx_desc { 1057 union { 1058 struct mvpp21_rx_desc pp21; 1059 struct mvpp22_rx_desc pp22; 1060 }; 1061 }; 1062 1063 struct mvpp2_txq_pcpu_buf { 1064 /* Transmitted SKB */ 1065 struct sk_buff *skb; 1066 1067 /* Physical address of transmitted buffer */ 1068 dma_addr_t dma; 1069 1070 /* Size transmitted */ 1071 size_t size; 1072 }; 1073 1074 /* Per-CPU Tx queue control */ 1075 struct mvpp2_txq_pcpu { 1076 unsigned int thread; 1077 1078 /* Number of Tx DMA descriptors in the descriptor ring */ 1079 int size; 1080 1081 /* Number of currently used Tx DMA descriptor in the 1082 * descriptor ring 1083 */ 1084 int count; 1085 1086 int wake_threshold; 1087 int stop_threshold; 1088 1089 /* Number of Tx DMA descriptors reserved for each CPU */ 1090 int reserved_num; 1091 1092 /* Infos about transmitted buffers */ 1093 struct mvpp2_txq_pcpu_buf *buffs; 1094 1095 /* Index of last TX DMA descriptor that was inserted */ 1096 int txq_put_index; 1097 1098 /* Index of the TX DMA descriptor to be cleaned up */ 1099 int txq_get_index; 1100 1101 /* DMA buffer for TSO headers */ 1102 char *tso_headers; 1103 dma_addr_t tso_headers_dma; 1104 }; 1105 1106 struct mvpp2_tx_queue { 1107 /* Physical number of this Tx queue */ 1108 u8 id; 1109 1110 /* Logical number of this Tx queue */ 1111 u8 log_id; 1112 1113 /* Number of Tx DMA descriptors in the descriptor ring */ 1114 int size; 1115 1116 /* Number of currently used Tx DMA descriptor in the descriptor ring */ 1117 int count; 1118 1119 /* Per-CPU control of physical Tx queues */ 1120 struct mvpp2_txq_pcpu __percpu *pcpu; 1121 1122 u32 done_pkts_coal; 1123 1124 /* Virtual address of thex Tx DMA descriptors array */ 1125 struct mvpp2_tx_desc *descs; 1126 1127 /* DMA address of the Tx DMA descriptors array */ 1128 dma_addr_t descs_dma; 1129 1130 /* Index of the last Tx DMA descriptor */ 1131 int last_desc; 1132 1133 /* Index of the next Tx DMA descriptor to process */ 1134 int next_desc_to_proc; 1135 }; 1136 1137 struct mvpp2_rx_queue { 1138 /* RX queue number, in the range 0-31 for physical RXQs */ 1139 u8 id; 1140 1141 /* Num of rx descriptors in the rx descriptor ring */ 1142 int size; 1143 1144 u32 pkts_coal; 1145 u32 time_coal; 1146 1147 /* Virtual address of the RX DMA descriptors array */ 1148 struct mvpp2_rx_desc *descs; 1149 1150 /* DMA address of the RX DMA descriptors array */ 1151 dma_addr_t descs_dma; 1152 1153 /* Index of the last RX DMA descriptor */ 1154 int last_desc; 1155 1156 /* Index of the next RX DMA descriptor to process */ 1157 int next_desc_to_proc; 1158 1159 /* ID of port to which physical RXQ is mapped */ 1160 int port; 1161 1162 /* Port's logic RXQ number to which physical RXQ is mapped */ 1163 int logic_rxq; 1164 }; 1165 1166 struct mvpp2_bm_pool { 1167 /* Pool number in the range 0-7 */ 1168 int id; 1169 1170 /* Buffer Pointers Pool External (BPPE) size */ 1171 int size; 1172 /* BPPE size in bytes */ 1173 int size_bytes; 1174 /* Number of buffers for this pool */ 1175 int buf_num; 1176 /* Pool buffer size */ 1177 int buf_size; 1178 /* Packet size */ 1179 int pkt_size; 1180 int frag_size; 1181 1182 /* BPPE virtual base address */ 1183 u32 *virt_addr; 1184 /* BPPE DMA base address */ 1185 dma_addr_t dma_addr; 1186 1187 /* Ports using BM pool */ 1188 u32 port_map; 1189 }; 1190 1191 #define IS_TSO_HEADER(txq_pcpu, addr) \ 1192 ((addr) >= (txq_pcpu)->tso_headers_dma && \ 1193 (addr) < (txq_pcpu)->tso_headers_dma + \ 1194 (txq_pcpu)->size * TSO_HEADER_SIZE) 1195 1196 #define MVPP2_DRIVER_NAME "mvpp2" 1197 #define MVPP2_DRIVER_VERSION "1.0" 1198 1199 void mvpp2_write(struct mvpp2 *priv, u32 offset, u32 data); 1200 u32 mvpp2_read(struct mvpp2 *priv, u32 offset); 1201 1202 void mvpp2_dbgfs_init(struct mvpp2 *priv, const char *name); 1203 1204 void mvpp2_dbgfs_cleanup(struct mvpp2 *priv); 1205 1206 #endif 1207