1 /* 2 * Driver for Marvell NETA network card for Armada XP and Armada 370 SoCs. 3 * 4 * Copyright (C) 2012 Marvell 5 * 6 * Rami Rosen <rosenr@marvell.com> 7 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> 8 * 9 * This file is licensed under the terms of the GNU General Public 10 * License version 2. This program is licensed "as is" without any 11 * warranty of any kind, whether express or implied. 12 */ 13 14 #include <linux/clk.h> 15 #include <linux/cpu.h> 16 #include <linux/etherdevice.h> 17 #include <linux/if_vlan.h> 18 #include <linux/inetdevice.h> 19 #include <linux/interrupt.h> 20 #include <linux/io.h> 21 #include <linux/kernel.h> 22 #include <linux/mbus.h> 23 #include <linux/module.h> 24 #include <linux/netdevice.h> 25 #include <linux/of.h> 26 #include <linux/of_address.h> 27 #include <linux/of_irq.h> 28 #include <linux/of_mdio.h> 29 #include <linux/of_net.h> 30 #include <linux/phy/phy.h> 31 #include <linux/phy.h> 32 #include <linux/phylink.h> 33 #include <linux/platform_device.h> 34 #include <linux/skbuff.h> 35 #include <net/hwbm.h> 36 #include "mvneta_bm.h" 37 #include <net/ip.h> 38 #include <net/ipv6.h> 39 #include <net/tso.h> 40 #include <net/page_pool.h> 41 #include <linux/bpf_trace.h> 42 43 /* Registers */ 44 #define MVNETA_RXQ_CONFIG_REG(q) (0x1400 + ((q) << 2)) 45 #define MVNETA_RXQ_HW_BUF_ALLOC BIT(0) 46 #define MVNETA_RXQ_SHORT_POOL_ID_SHIFT 4 47 #define MVNETA_RXQ_SHORT_POOL_ID_MASK 0x30 48 #define MVNETA_RXQ_LONG_POOL_ID_SHIFT 6 49 #define MVNETA_RXQ_LONG_POOL_ID_MASK 0xc0 50 #define MVNETA_RXQ_PKT_OFFSET_ALL_MASK (0xf << 8) 51 #define MVNETA_RXQ_PKT_OFFSET_MASK(offs) ((offs) << 8) 52 #define MVNETA_RXQ_THRESHOLD_REG(q) (0x14c0 + ((q) << 2)) 53 #define MVNETA_RXQ_NON_OCCUPIED(v) ((v) << 16) 54 #define MVNETA_RXQ_BASE_ADDR_REG(q) (0x1480 + ((q) << 2)) 55 #define MVNETA_RXQ_SIZE_REG(q) (0x14a0 + ((q) << 2)) 56 #define MVNETA_RXQ_BUF_SIZE_SHIFT 19 57 #define MVNETA_RXQ_BUF_SIZE_MASK (0x1fff << 19) 58 #define MVNETA_RXQ_STATUS_REG(q) (0x14e0 + ((q) << 2)) 59 #define MVNETA_RXQ_OCCUPIED_ALL_MASK 0x3fff 60 #define MVNETA_RXQ_STATUS_UPDATE_REG(q) (0x1500 + ((q) << 2)) 61 #define MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT 16 62 #define MVNETA_RXQ_ADD_NON_OCCUPIED_MAX 255 63 #define MVNETA_PORT_POOL_BUFFER_SZ_REG(pool) (0x1700 + ((pool) << 2)) 64 #define MVNETA_PORT_POOL_BUFFER_SZ_SHIFT 3 65 #define MVNETA_PORT_POOL_BUFFER_SZ_MASK 0xfff8 66 #define MVNETA_PORT_RX_RESET 0x1cc0 67 #define MVNETA_PORT_RX_DMA_RESET BIT(0) 68 #define MVNETA_PHY_ADDR 0x2000 69 #define MVNETA_PHY_ADDR_MASK 0x1f 70 #define MVNETA_MBUS_RETRY 0x2010 71 #define MVNETA_UNIT_INTR_CAUSE 0x2080 72 #define MVNETA_UNIT_CONTROL 0x20B0 73 #define MVNETA_PHY_POLLING_ENABLE BIT(1) 74 #define MVNETA_WIN_BASE(w) (0x2200 + ((w) << 3)) 75 #define MVNETA_WIN_SIZE(w) (0x2204 + ((w) << 3)) 76 #define MVNETA_WIN_REMAP(w) (0x2280 + ((w) << 2)) 77 #define MVNETA_BASE_ADDR_ENABLE 0x2290 78 #define MVNETA_ACCESS_PROTECT_ENABLE 0x2294 79 #define MVNETA_PORT_CONFIG 0x2400 80 #define MVNETA_UNI_PROMISC_MODE BIT(0) 81 #define MVNETA_DEF_RXQ(q) ((q) << 1) 82 #define MVNETA_DEF_RXQ_ARP(q) ((q) << 4) 83 #define MVNETA_TX_UNSET_ERR_SUM BIT(12) 84 #define MVNETA_DEF_RXQ_TCP(q) ((q) << 16) 85 #define MVNETA_DEF_RXQ_UDP(q) ((q) << 19) 86 #define MVNETA_DEF_RXQ_BPDU(q) ((q) << 22) 87 #define MVNETA_RX_CSUM_WITH_PSEUDO_HDR BIT(25) 88 #define MVNETA_PORT_CONFIG_DEFL_VALUE(q) (MVNETA_DEF_RXQ(q) | \ 89 MVNETA_DEF_RXQ_ARP(q) | \ 90 MVNETA_DEF_RXQ_TCP(q) | \ 91 MVNETA_DEF_RXQ_UDP(q) | \ 92 MVNETA_DEF_RXQ_BPDU(q) | \ 93 MVNETA_TX_UNSET_ERR_SUM | \ 94 MVNETA_RX_CSUM_WITH_PSEUDO_HDR) 95 #define MVNETA_PORT_CONFIG_EXTEND 0x2404 96 #define MVNETA_MAC_ADDR_LOW 0x2414 97 #define MVNETA_MAC_ADDR_HIGH 0x2418 98 #define MVNETA_SDMA_CONFIG 0x241c 99 #define MVNETA_SDMA_BRST_SIZE_16 4 100 #define MVNETA_RX_BRST_SZ_MASK(burst) ((burst) << 1) 101 #define MVNETA_RX_NO_DATA_SWAP BIT(4) 102 #define MVNETA_TX_NO_DATA_SWAP BIT(5) 103 #define MVNETA_DESC_SWAP BIT(6) 104 #define MVNETA_TX_BRST_SZ_MASK(burst) ((burst) << 22) 105 #define MVNETA_PORT_STATUS 0x2444 106 #define MVNETA_TX_IN_PRGRS BIT(1) 107 #define MVNETA_TX_FIFO_EMPTY BIT(8) 108 #define MVNETA_RX_MIN_FRAME_SIZE 0x247c 109 /* Only exists on Armada XP and Armada 370 */ 110 #define MVNETA_SERDES_CFG 0x24A0 111 #define MVNETA_SGMII_SERDES_PROTO 0x0cc7 112 #define MVNETA_QSGMII_SERDES_PROTO 0x0667 113 #define MVNETA_HSGMII_SERDES_PROTO 0x1107 114 #define MVNETA_TYPE_PRIO 0x24bc 115 #define MVNETA_FORCE_UNI BIT(21) 116 #define MVNETA_TXQ_CMD_1 0x24e4 117 #define MVNETA_TXQ_CMD 0x2448 118 #define MVNETA_TXQ_DISABLE_SHIFT 8 119 #define MVNETA_TXQ_ENABLE_MASK 0x000000ff 120 #define MVNETA_RX_DISCARD_FRAME_COUNT 0x2484 121 #define MVNETA_OVERRUN_FRAME_COUNT 0x2488 122 #define MVNETA_GMAC_CLOCK_DIVIDER 0x24f4 123 #define MVNETA_GMAC_1MS_CLOCK_ENABLE BIT(31) 124 #define MVNETA_ACC_MODE 0x2500 125 #define MVNETA_BM_ADDRESS 0x2504 126 #define MVNETA_CPU_MAP(cpu) (0x2540 + ((cpu) << 2)) 127 #define MVNETA_CPU_RXQ_ACCESS_ALL_MASK 0x000000ff 128 #define MVNETA_CPU_TXQ_ACCESS_ALL_MASK 0x0000ff00 129 #define MVNETA_CPU_RXQ_ACCESS(rxq) BIT(rxq) 130 #define MVNETA_CPU_TXQ_ACCESS(txq) BIT(txq + 8) 131 #define MVNETA_RXQ_TIME_COAL_REG(q) (0x2580 + ((q) << 2)) 132 133 /* Exception Interrupt Port/Queue Cause register 134 * 135 * Their behavior depend of the mapping done using the PCPX2Q 136 * registers. For a given CPU if the bit associated to a queue is not 137 * set, then for the register a read from this CPU will always return 138 * 0 and a write won't do anything 139 */ 140 141 #define MVNETA_INTR_NEW_CAUSE 0x25a0 142 #define MVNETA_INTR_NEW_MASK 0x25a4 143 144 /* bits 0..7 = TXQ SENT, one bit per queue. 145 * bits 8..15 = RXQ OCCUP, one bit per queue. 146 * bits 16..23 = RXQ FREE, one bit per queue. 147 * bit 29 = OLD_REG_SUM, see old reg ? 148 * bit 30 = TX_ERR_SUM, one bit for 4 ports 149 * bit 31 = MISC_SUM, one bit for 4 ports 150 */ 151 #define MVNETA_TX_INTR_MASK(nr_txqs) (((1 << nr_txqs) - 1) << 0) 152 #define MVNETA_TX_INTR_MASK_ALL (0xff << 0) 153 #define MVNETA_RX_INTR_MASK(nr_rxqs) (((1 << nr_rxqs) - 1) << 8) 154 #define MVNETA_RX_INTR_MASK_ALL (0xff << 8) 155 #define MVNETA_MISCINTR_INTR_MASK BIT(31) 156 157 #define MVNETA_INTR_OLD_CAUSE 0x25a8 158 #define MVNETA_INTR_OLD_MASK 0x25ac 159 160 /* Data Path Port/Queue Cause Register */ 161 #define MVNETA_INTR_MISC_CAUSE 0x25b0 162 #define MVNETA_INTR_MISC_MASK 0x25b4 163 164 #define MVNETA_CAUSE_PHY_STATUS_CHANGE BIT(0) 165 #define MVNETA_CAUSE_LINK_CHANGE BIT(1) 166 #define MVNETA_CAUSE_PTP BIT(4) 167 168 #define MVNETA_CAUSE_INTERNAL_ADDR_ERR BIT(7) 169 #define MVNETA_CAUSE_RX_OVERRUN BIT(8) 170 #define MVNETA_CAUSE_RX_CRC_ERROR BIT(9) 171 #define MVNETA_CAUSE_RX_LARGE_PKT BIT(10) 172 #define MVNETA_CAUSE_TX_UNDERUN BIT(11) 173 #define MVNETA_CAUSE_PRBS_ERR BIT(12) 174 #define MVNETA_CAUSE_PSC_SYNC_CHANGE BIT(13) 175 #define MVNETA_CAUSE_SERDES_SYNC_ERR BIT(14) 176 177 #define MVNETA_CAUSE_BMU_ALLOC_ERR_SHIFT 16 178 #define MVNETA_CAUSE_BMU_ALLOC_ERR_ALL_MASK (0xF << MVNETA_CAUSE_BMU_ALLOC_ERR_SHIFT) 179 #define MVNETA_CAUSE_BMU_ALLOC_ERR_MASK(pool) (1 << (MVNETA_CAUSE_BMU_ALLOC_ERR_SHIFT + (pool))) 180 181 #define MVNETA_CAUSE_TXQ_ERROR_SHIFT 24 182 #define MVNETA_CAUSE_TXQ_ERROR_ALL_MASK (0xFF << MVNETA_CAUSE_TXQ_ERROR_SHIFT) 183 #define MVNETA_CAUSE_TXQ_ERROR_MASK(q) (1 << (MVNETA_CAUSE_TXQ_ERROR_SHIFT + (q))) 184 185 #define MVNETA_INTR_ENABLE 0x25b8 186 #define MVNETA_TXQ_INTR_ENABLE_ALL_MASK 0x0000ff00 187 #define MVNETA_RXQ_INTR_ENABLE_ALL_MASK 0x000000ff 188 189 #define MVNETA_RXQ_CMD 0x2680 190 #define MVNETA_RXQ_DISABLE_SHIFT 8 191 #define MVNETA_RXQ_ENABLE_MASK 0x000000ff 192 #define MVETH_TXQ_TOKEN_COUNT_REG(q) (0x2700 + ((q) << 4)) 193 #define MVETH_TXQ_TOKEN_CFG_REG(q) (0x2704 + ((q) << 4)) 194 #define MVNETA_GMAC_CTRL_0 0x2c00 195 #define MVNETA_GMAC_MAX_RX_SIZE_SHIFT 2 196 #define MVNETA_GMAC_MAX_RX_SIZE_MASK 0x7ffc 197 #define MVNETA_GMAC0_PORT_1000BASE_X BIT(1) 198 #define MVNETA_GMAC0_PORT_ENABLE BIT(0) 199 #define MVNETA_GMAC_CTRL_2 0x2c08 200 #define MVNETA_GMAC2_INBAND_AN_ENABLE BIT(0) 201 #define MVNETA_GMAC2_PCS_ENABLE BIT(3) 202 #define MVNETA_GMAC2_PORT_RGMII BIT(4) 203 #define MVNETA_GMAC2_PORT_RESET BIT(6) 204 #define MVNETA_GMAC_STATUS 0x2c10 205 #define MVNETA_GMAC_LINK_UP BIT(0) 206 #define MVNETA_GMAC_SPEED_1000 BIT(1) 207 #define MVNETA_GMAC_SPEED_100 BIT(2) 208 #define MVNETA_GMAC_FULL_DUPLEX BIT(3) 209 #define MVNETA_GMAC_RX_FLOW_CTRL_ENABLE BIT(4) 210 #define MVNETA_GMAC_TX_FLOW_CTRL_ENABLE BIT(5) 211 #define MVNETA_GMAC_RX_FLOW_CTRL_ACTIVE BIT(6) 212 #define MVNETA_GMAC_TX_FLOW_CTRL_ACTIVE BIT(7) 213 #define MVNETA_GMAC_AN_COMPLETE BIT(11) 214 #define MVNETA_GMAC_SYNC_OK BIT(14) 215 #define MVNETA_GMAC_AUTONEG_CONFIG 0x2c0c 216 #define MVNETA_GMAC_FORCE_LINK_DOWN BIT(0) 217 #define MVNETA_GMAC_FORCE_LINK_PASS BIT(1) 218 #define MVNETA_GMAC_INBAND_AN_ENABLE BIT(2) 219 #define MVNETA_GMAC_AN_BYPASS_ENABLE BIT(3) 220 #define MVNETA_GMAC_INBAND_RESTART_AN BIT(4) 221 #define MVNETA_GMAC_CONFIG_MII_SPEED BIT(5) 222 #define MVNETA_GMAC_CONFIG_GMII_SPEED BIT(6) 223 #define MVNETA_GMAC_AN_SPEED_EN BIT(7) 224 #define MVNETA_GMAC_CONFIG_FLOW_CTRL BIT(8) 225 #define MVNETA_GMAC_ADVERT_SYM_FLOW_CTRL BIT(9) 226 #define MVNETA_GMAC_AN_FLOW_CTRL_EN BIT(11) 227 #define MVNETA_GMAC_CONFIG_FULL_DUPLEX BIT(12) 228 #define MVNETA_GMAC_AN_DUPLEX_EN BIT(13) 229 #define MVNETA_GMAC_CTRL_4 0x2c90 230 #define MVNETA_GMAC4_SHORT_PREAMBLE_ENABLE BIT(1) 231 #define MVNETA_MIB_COUNTERS_BASE 0x3000 232 #define MVNETA_MIB_LATE_COLLISION 0x7c 233 #define MVNETA_DA_FILT_SPEC_MCAST 0x3400 234 #define MVNETA_DA_FILT_OTH_MCAST 0x3500 235 #define MVNETA_DA_FILT_UCAST_BASE 0x3600 236 #define MVNETA_TXQ_BASE_ADDR_REG(q) (0x3c00 + ((q) << 2)) 237 #define MVNETA_TXQ_SIZE_REG(q) (0x3c20 + ((q) << 2)) 238 #define MVNETA_TXQ_SENT_THRESH_ALL_MASK 0x3fff0000 239 #define MVNETA_TXQ_SENT_THRESH_MASK(coal) ((coal) << 16) 240 #define MVNETA_TXQ_UPDATE_REG(q) (0x3c60 + ((q) << 2)) 241 #define MVNETA_TXQ_DEC_SENT_SHIFT 16 242 #define MVNETA_TXQ_DEC_SENT_MASK 0xff 243 #define MVNETA_TXQ_STATUS_REG(q) (0x3c40 + ((q) << 2)) 244 #define MVNETA_TXQ_SENT_DESC_SHIFT 16 245 #define MVNETA_TXQ_SENT_DESC_MASK 0x3fff0000 246 #define MVNETA_PORT_TX_RESET 0x3cf0 247 #define MVNETA_PORT_TX_DMA_RESET BIT(0) 248 #define MVNETA_TX_MTU 0x3e0c 249 #define MVNETA_TX_TOKEN_SIZE 0x3e14 250 #define MVNETA_TX_TOKEN_SIZE_MAX 0xffffffff 251 #define MVNETA_TXQ_TOKEN_SIZE_REG(q) (0x3e40 + ((q) << 2)) 252 #define MVNETA_TXQ_TOKEN_SIZE_MAX 0x7fffffff 253 254 #define MVNETA_LPI_CTRL_0 0x2cc0 255 #define MVNETA_LPI_CTRL_1 0x2cc4 256 #define MVNETA_LPI_REQUEST_ENABLE BIT(0) 257 #define MVNETA_LPI_CTRL_2 0x2cc8 258 #define MVNETA_LPI_STATUS 0x2ccc 259 260 #define MVNETA_CAUSE_TXQ_SENT_DESC_ALL_MASK 0xff 261 262 /* Descriptor ring Macros */ 263 #define MVNETA_QUEUE_NEXT_DESC(q, index) \ 264 (((index) < (q)->last_desc) ? ((index) + 1) : 0) 265 266 /* Various constants */ 267 268 /* Coalescing */ 269 #define MVNETA_TXDONE_COAL_PKTS 0 /* interrupt per packet */ 270 #define MVNETA_RX_COAL_PKTS 32 271 #define MVNETA_RX_COAL_USEC 100 272 273 /* The two bytes Marvell header. Either contains a special value used 274 * by Marvell switches when a specific hardware mode is enabled (not 275 * supported by this driver) or is filled automatically by zeroes on 276 * the RX side. Those two bytes being at the front of the Ethernet 277 * header, they allow to have the IP header aligned on a 4 bytes 278 * boundary automatically: the hardware skips those two bytes on its 279 * own. 280 */ 281 #define MVNETA_MH_SIZE 2 282 283 #define MVNETA_VLAN_TAG_LEN 4 284 285 #define MVNETA_TX_CSUM_DEF_SIZE 1600 286 #define MVNETA_TX_CSUM_MAX_SIZE 9800 287 #define MVNETA_ACC_MODE_EXT1 1 288 #define MVNETA_ACC_MODE_EXT2 2 289 290 #define MVNETA_MAX_DECODE_WIN 6 291 292 /* Timeout constants */ 293 #define MVNETA_TX_DISABLE_TIMEOUT_MSEC 1000 294 #define MVNETA_RX_DISABLE_TIMEOUT_MSEC 1000 295 #define MVNETA_TX_FIFO_EMPTY_TIMEOUT 10000 296 297 #define MVNETA_TX_MTU_MAX 0x3ffff 298 299 /* The RSS lookup table actually has 256 entries but we do not use 300 * them yet 301 */ 302 #define MVNETA_RSS_LU_TABLE_SIZE 1 303 304 /* Max number of Rx descriptors */ 305 #define MVNETA_MAX_RXD 512 306 307 /* Max number of Tx descriptors */ 308 #define MVNETA_MAX_TXD 1024 309 310 /* Max number of allowed TCP segments for software TSO */ 311 #define MVNETA_MAX_TSO_SEGS 100 312 313 #define MVNETA_MAX_SKB_DESCS (MVNETA_MAX_TSO_SEGS * 2 + MAX_SKB_FRAGS) 314 315 /* descriptor aligned size */ 316 #define MVNETA_DESC_ALIGNED_SIZE 32 317 318 /* Number of bytes to be taken into account by HW when putting incoming data 319 * to the buffers. It is needed in case NET_SKB_PAD exceeds maximum packet 320 * offset supported in MVNETA_RXQ_CONFIG_REG(q) registers. 321 */ 322 #define MVNETA_RX_PKT_OFFSET_CORRECTION 64 323 324 #define MVNETA_RX_PKT_SIZE(mtu) \ 325 ALIGN((mtu) + MVNETA_MH_SIZE + MVNETA_VLAN_TAG_LEN + \ 326 ETH_HLEN + ETH_FCS_LEN, \ 327 cache_line_size()) 328 329 /* Driver assumes that the last 3 bits are 0 */ 330 #define MVNETA_SKB_HEADROOM ALIGN(max(NET_SKB_PAD, XDP_PACKET_HEADROOM), 8) 331 #define MVNETA_SKB_PAD (SKB_DATA_ALIGN(sizeof(struct skb_shared_info) + \ 332 MVNETA_SKB_HEADROOM)) 333 #define MVNETA_SKB_SIZE(len) (SKB_DATA_ALIGN(len) + MVNETA_SKB_PAD) 334 #define MVNETA_MAX_RX_BUF_SIZE (PAGE_SIZE - MVNETA_SKB_PAD) 335 336 #define IS_TSO_HEADER(txq, addr) \ 337 ((addr >= txq->tso_hdrs_phys) && \ 338 (addr < txq->tso_hdrs_phys + txq->size * TSO_HEADER_SIZE)) 339 340 #define MVNETA_RX_GET_BM_POOL_ID(rxd) \ 341 (((rxd)->status & MVNETA_RXD_BM_POOL_MASK) >> MVNETA_RXD_BM_POOL_SHIFT) 342 343 enum { 344 ETHTOOL_STAT_EEE_WAKEUP, 345 ETHTOOL_STAT_SKB_ALLOC_ERR, 346 ETHTOOL_STAT_REFILL_ERR, 347 ETHTOOL_XDP_REDIRECT, 348 ETHTOOL_XDP_PASS, 349 ETHTOOL_XDP_DROP, 350 ETHTOOL_XDP_TX, 351 ETHTOOL_XDP_TX_ERR, 352 ETHTOOL_XDP_XMIT, 353 ETHTOOL_XDP_XMIT_ERR, 354 ETHTOOL_MAX_STATS, 355 }; 356 357 struct mvneta_statistic { 358 unsigned short offset; 359 unsigned short type; 360 const char name[ETH_GSTRING_LEN]; 361 }; 362 363 #define T_REG_32 32 364 #define T_REG_64 64 365 #define T_SW 1 366 367 #define MVNETA_XDP_PASS 0 368 #define MVNETA_XDP_DROPPED BIT(0) 369 #define MVNETA_XDP_TX BIT(1) 370 #define MVNETA_XDP_REDIR BIT(2) 371 372 static const struct mvneta_statistic mvneta_statistics[] = { 373 { 0x3000, T_REG_64, "good_octets_received", }, 374 { 0x3010, T_REG_32, "good_frames_received", }, 375 { 0x3008, T_REG_32, "bad_octets_received", }, 376 { 0x3014, T_REG_32, "bad_frames_received", }, 377 { 0x3018, T_REG_32, "broadcast_frames_received", }, 378 { 0x301c, T_REG_32, "multicast_frames_received", }, 379 { 0x3050, T_REG_32, "unrec_mac_control_received", }, 380 { 0x3058, T_REG_32, "good_fc_received", }, 381 { 0x305c, T_REG_32, "bad_fc_received", }, 382 { 0x3060, T_REG_32, "undersize_received", }, 383 { 0x3064, T_REG_32, "fragments_received", }, 384 { 0x3068, T_REG_32, "oversize_received", }, 385 { 0x306c, T_REG_32, "jabber_received", }, 386 { 0x3070, T_REG_32, "mac_receive_error", }, 387 { 0x3074, T_REG_32, "bad_crc_event", }, 388 { 0x3078, T_REG_32, "collision", }, 389 { 0x307c, T_REG_32, "late_collision", }, 390 { 0x2484, T_REG_32, "rx_discard", }, 391 { 0x2488, T_REG_32, "rx_overrun", }, 392 { 0x3020, T_REG_32, "frames_64_octets", }, 393 { 0x3024, T_REG_32, "frames_65_to_127_octets", }, 394 { 0x3028, T_REG_32, "frames_128_to_255_octets", }, 395 { 0x302c, T_REG_32, "frames_256_to_511_octets", }, 396 { 0x3030, T_REG_32, "frames_512_to_1023_octets", }, 397 { 0x3034, T_REG_32, "frames_1024_to_max_octets", }, 398 { 0x3038, T_REG_64, "good_octets_sent", }, 399 { 0x3040, T_REG_32, "good_frames_sent", }, 400 { 0x3044, T_REG_32, "excessive_collision", }, 401 { 0x3048, T_REG_32, "multicast_frames_sent", }, 402 { 0x304c, T_REG_32, "broadcast_frames_sent", }, 403 { 0x3054, T_REG_32, "fc_sent", }, 404 { 0x300c, T_REG_32, "internal_mac_transmit_err", }, 405 { ETHTOOL_STAT_EEE_WAKEUP, T_SW, "eee_wakeup_errors", }, 406 { ETHTOOL_STAT_SKB_ALLOC_ERR, T_SW, "skb_alloc_errors", }, 407 { ETHTOOL_STAT_REFILL_ERR, T_SW, "refill_errors", }, 408 { ETHTOOL_XDP_REDIRECT, T_SW, "rx_xdp_redirect", }, 409 { ETHTOOL_XDP_PASS, T_SW, "rx_xdp_pass", }, 410 { ETHTOOL_XDP_DROP, T_SW, "rx_xdp_drop", }, 411 { ETHTOOL_XDP_TX, T_SW, "rx_xdp_tx", }, 412 { ETHTOOL_XDP_TX_ERR, T_SW, "rx_xdp_tx_errors", }, 413 { ETHTOOL_XDP_XMIT, T_SW, "tx_xdp_xmit", }, 414 { ETHTOOL_XDP_XMIT_ERR, T_SW, "tx_xdp_xmit_errors", }, 415 }; 416 417 struct mvneta_stats { 418 u64 rx_packets; 419 u64 rx_bytes; 420 u64 tx_packets; 421 u64 tx_bytes; 422 /* xdp */ 423 u64 xdp_redirect; 424 u64 xdp_pass; 425 u64 xdp_drop; 426 u64 xdp_xmit; 427 u64 xdp_xmit_err; 428 u64 xdp_tx; 429 u64 xdp_tx_err; 430 }; 431 432 struct mvneta_ethtool_stats { 433 struct mvneta_stats ps; 434 u64 skb_alloc_error; 435 u64 refill_error; 436 }; 437 438 struct mvneta_pcpu_stats { 439 struct u64_stats_sync syncp; 440 441 struct mvneta_ethtool_stats es; 442 u64 rx_dropped; 443 u64 rx_errors; 444 }; 445 446 struct mvneta_pcpu_port { 447 /* Pointer to the shared port */ 448 struct mvneta_port *pp; 449 450 /* Pointer to the CPU-local NAPI struct */ 451 struct napi_struct napi; 452 453 /* Cause of the previous interrupt */ 454 u32 cause_rx_tx; 455 }; 456 457 enum { 458 __MVNETA_DOWN, 459 }; 460 461 struct mvneta_port { 462 u8 id; 463 struct mvneta_pcpu_port __percpu *ports; 464 struct mvneta_pcpu_stats __percpu *stats; 465 466 unsigned long state; 467 468 int pkt_size; 469 void __iomem *base; 470 struct mvneta_rx_queue *rxqs; 471 struct mvneta_tx_queue *txqs; 472 struct net_device *dev; 473 struct hlist_node node_online; 474 struct hlist_node node_dead; 475 int rxq_def; 476 /* Protect the access to the percpu interrupt registers, 477 * ensuring that the configuration remains coherent. 478 */ 479 spinlock_t lock; 480 bool is_stopped; 481 482 u32 cause_rx_tx; 483 struct napi_struct napi; 484 485 struct bpf_prog *xdp_prog; 486 487 /* Core clock */ 488 struct clk *clk; 489 /* AXI clock */ 490 struct clk *clk_bus; 491 u8 mcast_count[256]; 492 u16 tx_ring_size; 493 u16 rx_ring_size; 494 495 phy_interface_t phy_interface; 496 struct device_node *dn; 497 unsigned int tx_csum_limit; 498 struct phylink *phylink; 499 struct phylink_config phylink_config; 500 struct phy *comphy; 501 502 struct mvneta_bm *bm_priv; 503 struct mvneta_bm_pool *pool_long; 504 struct mvneta_bm_pool *pool_short; 505 int bm_win_id; 506 507 bool eee_enabled; 508 bool eee_active; 509 bool tx_lpi_enabled; 510 511 u64 ethtool_stats[ARRAY_SIZE(mvneta_statistics)]; 512 513 u32 indir[MVNETA_RSS_LU_TABLE_SIZE]; 514 515 /* Flags for special SoC configurations */ 516 bool neta_armada3700; 517 u16 rx_offset_correction; 518 const struct mbus_dram_target_info *dram_target_info; 519 }; 520 521 /* The mvneta_tx_desc and mvneta_rx_desc structures describe the 522 * layout of the transmit and reception DMA descriptors, and their 523 * layout is therefore defined by the hardware design 524 */ 525 526 #define MVNETA_TX_L3_OFF_SHIFT 0 527 #define MVNETA_TX_IP_HLEN_SHIFT 8 528 #define MVNETA_TX_L4_UDP BIT(16) 529 #define MVNETA_TX_L3_IP6 BIT(17) 530 #define MVNETA_TXD_IP_CSUM BIT(18) 531 #define MVNETA_TXD_Z_PAD BIT(19) 532 #define MVNETA_TXD_L_DESC BIT(20) 533 #define MVNETA_TXD_F_DESC BIT(21) 534 #define MVNETA_TXD_FLZ_DESC (MVNETA_TXD_Z_PAD | \ 535 MVNETA_TXD_L_DESC | \ 536 MVNETA_TXD_F_DESC) 537 #define MVNETA_TX_L4_CSUM_FULL BIT(30) 538 #define MVNETA_TX_L4_CSUM_NOT BIT(31) 539 540 #define MVNETA_RXD_ERR_CRC 0x0 541 #define MVNETA_RXD_BM_POOL_SHIFT 13 542 #define MVNETA_RXD_BM_POOL_MASK (BIT(13) | BIT(14)) 543 #define MVNETA_RXD_ERR_SUMMARY BIT(16) 544 #define MVNETA_RXD_ERR_OVERRUN BIT(17) 545 #define MVNETA_RXD_ERR_LEN BIT(18) 546 #define MVNETA_RXD_ERR_RESOURCE (BIT(17) | BIT(18)) 547 #define MVNETA_RXD_ERR_CODE_MASK (BIT(17) | BIT(18)) 548 #define MVNETA_RXD_L3_IP4 BIT(25) 549 #define MVNETA_RXD_LAST_DESC BIT(26) 550 #define MVNETA_RXD_FIRST_DESC BIT(27) 551 #define MVNETA_RXD_FIRST_LAST_DESC (MVNETA_RXD_FIRST_DESC | \ 552 MVNETA_RXD_LAST_DESC) 553 #define MVNETA_RXD_L4_CSUM_OK BIT(30) 554 555 #if defined(__LITTLE_ENDIAN) 556 struct mvneta_tx_desc { 557 u32 command; /* Options used by HW for packet transmitting.*/ 558 u16 reserved1; /* csum_l4 (for future use) */ 559 u16 data_size; /* Data size of transmitted packet in bytes */ 560 u32 buf_phys_addr; /* Physical addr of transmitted buffer */ 561 u32 reserved2; /* hw_cmd - (for future use, PMT) */ 562 u32 reserved3[4]; /* Reserved - (for future use) */ 563 }; 564 565 struct mvneta_rx_desc { 566 u32 status; /* Info about received packet */ 567 u16 reserved1; /* pnc_info - (for future use, PnC) */ 568 u16 data_size; /* Size of received packet in bytes */ 569 570 u32 buf_phys_addr; /* Physical address of the buffer */ 571 u32 reserved2; /* pnc_flow_id (for future use, PnC) */ 572 573 u32 buf_cookie; /* cookie for access to RX buffer in rx path */ 574 u16 reserved3; /* prefetch_cmd, for future use */ 575 u16 reserved4; /* csum_l4 - (for future use, PnC) */ 576 577 u32 reserved5; /* pnc_extra PnC (for future use, PnC) */ 578 u32 reserved6; /* hw_cmd (for future use, PnC and HWF) */ 579 }; 580 #else 581 struct mvneta_tx_desc { 582 u16 data_size; /* Data size of transmitted packet in bytes */ 583 u16 reserved1; /* csum_l4 (for future use) */ 584 u32 command; /* Options used by HW for packet transmitting.*/ 585 u32 reserved2; /* hw_cmd - (for future use, PMT) */ 586 u32 buf_phys_addr; /* Physical addr of transmitted buffer */ 587 u32 reserved3[4]; /* Reserved - (for future use) */ 588 }; 589 590 struct mvneta_rx_desc { 591 u16 data_size; /* Size of received packet in bytes */ 592 u16 reserved1; /* pnc_info - (for future use, PnC) */ 593 u32 status; /* Info about received packet */ 594 595 u32 reserved2; /* pnc_flow_id (for future use, PnC) */ 596 u32 buf_phys_addr; /* Physical address of the buffer */ 597 598 u16 reserved4; /* csum_l4 - (for future use, PnC) */ 599 u16 reserved3; /* prefetch_cmd, for future use */ 600 u32 buf_cookie; /* cookie for access to RX buffer in rx path */ 601 602 u32 reserved5; /* pnc_extra PnC (for future use, PnC) */ 603 u32 reserved6; /* hw_cmd (for future use, PnC and HWF) */ 604 }; 605 #endif 606 607 enum mvneta_tx_buf_type { 608 MVNETA_TYPE_SKB, 609 MVNETA_TYPE_XDP_TX, 610 MVNETA_TYPE_XDP_NDO, 611 }; 612 613 struct mvneta_tx_buf { 614 enum mvneta_tx_buf_type type; 615 union { 616 struct xdp_frame *xdpf; 617 struct sk_buff *skb; 618 }; 619 }; 620 621 struct mvneta_tx_queue { 622 /* Number of this TX queue, in the range 0-7 */ 623 u8 id; 624 625 /* Number of TX DMA descriptors in the descriptor ring */ 626 int size; 627 628 /* Number of currently used TX DMA descriptor in the 629 * descriptor ring 630 */ 631 int count; 632 int pending; 633 int tx_stop_threshold; 634 int tx_wake_threshold; 635 636 /* Array of transmitted buffers */ 637 struct mvneta_tx_buf *buf; 638 639 /* Index of last TX DMA descriptor that was inserted */ 640 int txq_put_index; 641 642 /* Index of the TX DMA descriptor to be cleaned up */ 643 int txq_get_index; 644 645 u32 done_pkts_coal; 646 647 /* Virtual address of the TX DMA descriptors array */ 648 struct mvneta_tx_desc *descs; 649 650 /* DMA address of the TX DMA descriptors array */ 651 dma_addr_t descs_phys; 652 653 /* Index of the last TX DMA descriptor */ 654 int last_desc; 655 656 /* Index of the next TX DMA descriptor to process */ 657 int next_desc_to_proc; 658 659 /* DMA buffers for TSO headers */ 660 char *tso_hdrs; 661 662 /* DMA address of TSO headers */ 663 dma_addr_t tso_hdrs_phys; 664 665 /* Affinity mask for CPUs*/ 666 cpumask_t affinity_mask; 667 }; 668 669 struct mvneta_rx_queue { 670 /* rx queue number, in the range 0-7 */ 671 u8 id; 672 673 /* num of rx descriptors in the rx descriptor ring */ 674 int size; 675 676 u32 pkts_coal; 677 u32 time_coal; 678 679 /* page_pool */ 680 struct page_pool *page_pool; 681 struct xdp_rxq_info xdp_rxq; 682 683 /* Virtual address of the RX buffer */ 684 void **buf_virt_addr; 685 686 /* Virtual address of the RX DMA descriptors array */ 687 struct mvneta_rx_desc *descs; 688 689 /* DMA address of the RX DMA descriptors array */ 690 dma_addr_t descs_phys; 691 692 /* Index of the last RX DMA descriptor */ 693 int last_desc; 694 695 /* Index of the next RX DMA descriptor to process */ 696 int next_desc_to_proc; 697 698 /* Index of first RX DMA descriptor to refill */ 699 int first_to_refill; 700 u32 refill_num; 701 }; 702 703 static enum cpuhp_state online_hpstate; 704 /* The hardware supports eight (8) rx queues, but we are only allowing 705 * the first one to be used. Therefore, let's just allocate one queue. 706 */ 707 static int rxq_number = 8; 708 static int txq_number = 8; 709 710 static int rxq_def; 711 712 static int rx_copybreak __read_mostly = 256; 713 714 /* HW BM need that each port be identify by a unique ID */ 715 static int global_port_id; 716 717 #define MVNETA_DRIVER_NAME "mvneta" 718 #define MVNETA_DRIVER_VERSION "1.0" 719 720 /* Utility/helper methods */ 721 722 /* Write helper method */ 723 static void mvreg_write(struct mvneta_port *pp, u32 offset, u32 data) 724 { 725 writel(data, pp->base + offset); 726 } 727 728 /* Read helper method */ 729 static u32 mvreg_read(struct mvneta_port *pp, u32 offset) 730 { 731 return readl(pp->base + offset); 732 } 733 734 /* Increment txq get counter */ 735 static void mvneta_txq_inc_get(struct mvneta_tx_queue *txq) 736 { 737 txq->txq_get_index++; 738 if (txq->txq_get_index == txq->size) 739 txq->txq_get_index = 0; 740 } 741 742 /* Increment txq put counter */ 743 static void mvneta_txq_inc_put(struct mvneta_tx_queue *txq) 744 { 745 txq->txq_put_index++; 746 if (txq->txq_put_index == txq->size) 747 txq->txq_put_index = 0; 748 } 749 750 751 /* Clear all MIB counters */ 752 static void mvneta_mib_counters_clear(struct mvneta_port *pp) 753 { 754 int i; 755 u32 dummy; 756 757 /* Perform dummy reads from MIB counters */ 758 for (i = 0; i < MVNETA_MIB_LATE_COLLISION; i += 4) 759 dummy = mvreg_read(pp, (MVNETA_MIB_COUNTERS_BASE + i)); 760 dummy = mvreg_read(pp, MVNETA_RX_DISCARD_FRAME_COUNT); 761 dummy = mvreg_read(pp, MVNETA_OVERRUN_FRAME_COUNT); 762 } 763 764 /* Get System Network Statistics */ 765 static void 766 mvneta_get_stats64(struct net_device *dev, 767 struct rtnl_link_stats64 *stats) 768 { 769 struct mvneta_port *pp = netdev_priv(dev); 770 unsigned int start; 771 int cpu; 772 773 for_each_possible_cpu(cpu) { 774 struct mvneta_pcpu_stats *cpu_stats; 775 u64 rx_packets; 776 u64 rx_bytes; 777 u64 rx_dropped; 778 u64 rx_errors; 779 u64 tx_packets; 780 u64 tx_bytes; 781 782 cpu_stats = per_cpu_ptr(pp->stats, cpu); 783 do { 784 start = u64_stats_fetch_begin_irq(&cpu_stats->syncp); 785 rx_packets = cpu_stats->es.ps.rx_packets; 786 rx_bytes = cpu_stats->es.ps.rx_bytes; 787 rx_dropped = cpu_stats->rx_dropped; 788 rx_errors = cpu_stats->rx_errors; 789 tx_packets = cpu_stats->es.ps.tx_packets; 790 tx_bytes = cpu_stats->es.ps.tx_bytes; 791 } while (u64_stats_fetch_retry_irq(&cpu_stats->syncp, start)); 792 793 stats->rx_packets += rx_packets; 794 stats->rx_bytes += rx_bytes; 795 stats->rx_dropped += rx_dropped; 796 stats->rx_errors += rx_errors; 797 stats->tx_packets += tx_packets; 798 stats->tx_bytes += tx_bytes; 799 } 800 801 stats->tx_dropped = dev->stats.tx_dropped; 802 } 803 804 /* Rx descriptors helper methods */ 805 806 /* Checks whether the RX descriptor having this status is both the first 807 * and the last descriptor for the RX packet. Each RX packet is currently 808 * received through a single RX descriptor, so not having each RX 809 * descriptor with its first and last bits set is an error 810 */ 811 static int mvneta_rxq_desc_is_first_last(u32 status) 812 { 813 return (status & MVNETA_RXD_FIRST_LAST_DESC) == 814 MVNETA_RXD_FIRST_LAST_DESC; 815 } 816 817 /* Add number of descriptors ready to receive new packets */ 818 static void mvneta_rxq_non_occup_desc_add(struct mvneta_port *pp, 819 struct mvneta_rx_queue *rxq, 820 int ndescs) 821 { 822 /* Only MVNETA_RXQ_ADD_NON_OCCUPIED_MAX (255) descriptors can 823 * be added at once 824 */ 825 while (ndescs > MVNETA_RXQ_ADD_NON_OCCUPIED_MAX) { 826 mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id), 827 (MVNETA_RXQ_ADD_NON_OCCUPIED_MAX << 828 MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT)); 829 ndescs -= MVNETA_RXQ_ADD_NON_OCCUPIED_MAX; 830 } 831 832 mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id), 833 (ndescs << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT)); 834 } 835 836 /* Get number of RX descriptors occupied by received packets */ 837 static int mvneta_rxq_busy_desc_num_get(struct mvneta_port *pp, 838 struct mvneta_rx_queue *rxq) 839 { 840 u32 val; 841 842 val = mvreg_read(pp, MVNETA_RXQ_STATUS_REG(rxq->id)); 843 return val & MVNETA_RXQ_OCCUPIED_ALL_MASK; 844 } 845 846 /* Update num of rx desc called upon return from rx path or 847 * from mvneta_rxq_drop_pkts(). 848 */ 849 static void mvneta_rxq_desc_num_update(struct mvneta_port *pp, 850 struct mvneta_rx_queue *rxq, 851 int rx_done, int rx_filled) 852 { 853 u32 val; 854 855 if ((rx_done <= 0xff) && (rx_filled <= 0xff)) { 856 val = rx_done | 857 (rx_filled << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT); 858 mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id), val); 859 return; 860 } 861 862 /* Only 255 descriptors can be added at once */ 863 while ((rx_done > 0) || (rx_filled > 0)) { 864 if (rx_done <= 0xff) { 865 val = rx_done; 866 rx_done = 0; 867 } else { 868 val = 0xff; 869 rx_done -= 0xff; 870 } 871 if (rx_filled <= 0xff) { 872 val |= rx_filled << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT; 873 rx_filled = 0; 874 } else { 875 val |= 0xff << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT; 876 rx_filled -= 0xff; 877 } 878 mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id), val); 879 } 880 } 881 882 /* Get pointer to next RX descriptor to be processed by SW */ 883 static struct mvneta_rx_desc * 884 mvneta_rxq_next_desc_get(struct mvneta_rx_queue *rxq) 885 { 886 int rx_desc = rxq->next_desc_to_proc; 887 888 rxq->next_desc_to_proc = MVNETA_QUEUE_NEXT_DESC(rxq, rx_desc); 889 prefetch(rxq->descs + rxq->next_desc_to_proc); 890 return rxq->descs + rx_desc; 891 } 892 893 /* Change maximum receive size of the port. */ 894 static void mvneta_max_rx_size_set(struct mvneta_port *pp, int max_rx_size) 895 { 896 u32 val; 897 898 val = mvreg_read(pp, MVNETA_GMAC_CTRL_0); 899 val &= ~MVNETA_GMAC_MAX_RX_SIZE_MASK; 900 val |= ((max_rx_size - MVNETA_MH_SIZE) / 2) << 901 MVNETA_GMAC_MAX_RX_SIZE_SHIFT; 902 mvreg_write(pp, MVNETA_GMAC_CTRL_0, val); 903 } 904 905 906 /* Set rx queue offset */ 907 static void mvneta_rxq_offset_set(struct mvneta_port *pp, 908 struct mvneta_rx_queue *rxq, 909 int offset) 910 { 911 u32 val; 912 913 val = mvreg_read(pp, MVNETA_RXQ_CONFIG_REG(rxq->id)); 914 val &= ~MVNETA_RXQ_PKT_OFFSET_ALL_MASK; 915 916 /* Offset is in */ 917 val |= MVNETA_RXQ_PKT_OFFSET_MASK(offset >> 3); 918 mvreg_write(pp, MVNETA_RXQ_CONFIG_REG(rxq->id), val); 919 } 920 921 922 /* Tx descriptors helper methods */ 923 924 /* Update HW with number of TX descriptors to be sent */ 925 static void mvneta_txq_pend_desc_add(struct mvneta_port *pp, 926 struct mvneta_tx_queue *txq, 927 int pend_desc) 928 { 929 u32 val; 930 931 pend_desc += txq->pending; 932 933 /* Only 255 Tx descriptors can be added at once */ 934 do { 935 val = min(pend_desc, 255); 936 mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val); 937 pend_desc -= val; 938 } while (pend_desc > 0); 939 txq->pending = 0; 940 } 941 942 /* Get pointer to next TX descriptor to be processed (send) by HW */ 943 static struct mvneta_tx_desc * 944 mvneta_txq_next_desc_get(struct mvneta_tx_queue *txq) 945 { 946 int tx_desc = txq->next_desc_to_proc; 947 948 txq->next_desc_to_proc = MVNETA_QUEUE_NEXT_DESC(txq, tx_desc); 949 return txq->descs + tx_desc; 950 } 951 952 /* Release the last allocated TX descriptor. Useful to handle DMA 953 * mapping failures in the TX path. 954 */ 955 static void mvneta_txq_desc_put(struct mvneta_tx_queue *txq) 956 { 957 if (txq->next_desc_to_proc == 0) 958 txq->next_desc_to_proc = txq->last_desc - 1; 959 else 960 txq->next_desc_to_proc--; 961 } 962 963 /* Set rxq buf size */ 964 static void mvneta_rxq_buf_size_set(struct mvneta_port *pp, 965 struct mvneta_rx_queue *rxq, 966 int buf_size) 967 { 968 u32 val; 969 970 val = mvreg_read(pp, MVNETA_RXQ_SIZE_REG(rxq->id)); 971 972 val &= ~MVNETA_RXQ_BUF_SIZE_MASK; 973 val |= ((buf_size >> 3) << MVNETA_RXQ_BUF_SIZE_SHIFT); 974 975 mvreg_write(pp, MVNETA_RXQ_SIZE_REG(rxq->id), val); 976 } 977 978 /* Disable buffer management (BM) */ 979 static void mvneta_rxq_bm_disable(struct mvneta_port *pp, 980 struct mvneta_rx_queue *rxq) 981 { 982 u32 val; 983 984 val = mvreg_read(pp, MVNETA_RXQ_CONFIG_REG(rxq->id)); 985 val &= ~MVNETA_RXQ_HW_BUF_ALLOC; 986 mvreg_write(pp, MVNETA_RXQ_CONFIG_REG(rxq->id), val); 987 } 988 989 /* Enable buffer management (BM) */ 990 static void mvneta_rxq_bm_enable(struct mvneta_port *pp, 991 struct mvneta_rx_queue *rxq) 992 { 993 u32 val; 994 995 val = mvreg_read(pp, MVNETA_RXQ_CONFIG_REG(rxq->id)); 996 val |= MVNETA_RXQ_HW_BUF_ALLOC; 997 mvreg_write(pp, MVNETA_RXQ_CONFIG_REG(rxq->id), val); 998 } 999 1000 /* Notify HW about port's assignment of pool for bigger packets */ 1001 static void mvneta_rxq_long_pool_set(struct mvneta_port *pp, 1002 struct mvneta_rx_queue *rxq) 1003 { 1004 u32 val; 1005 1006 val = mvreg_read(pp, MVNETA_RXQ_CONFIG_REG(rxq->id)); 1007 val &= ~MVNETA_RXQ_LONG_POOL_ID_MASK; 1008 val |= (pp->pool_long->id << MVNETA_RXQ_LONG_POOL_ID_SHIFT); 1009 1010 mvreg_write(pp, MVNETA_RXQ_CONFIG_REG(rxq->id), val); 1011 } 1012 1013 /* Notify HW about port's assignment of pool for smaller packets */ 1014 static void mvneta_rxq_short_pool_set(struct mvneta_port *pp, 1015 struct mvneta_rx_queue *rxq) 1016 { 1017 u32 val; 1018 1019 val = mvreg_read(pp, MVNETA_RXQ_CONFIG_REG(rxq->id)); 1020 val &= ~MVNETA_RXQ_SHORT_POOL_ID_MASK; 1021 val |= (pp->pool_short->id << MVNETA_RXQ_SHORT_POOL_ID_SHIFT); 1022 1023 mvreg_write(pp, MVNETA_RXQ_CONFIG_REG(rxq->id), val); 1024 } 1025 1026 /* Set port's receive buffer size for assigned BM pool */ 1027 static inline void mvneta_bm_pool_bufsize_set(struct mvneta_port *pp, 1028 int buf_size, 1029 u8 pool_id) 1030 { 1031 u32 val; 1032 1033 if (!IS_ALIGNED(buf_size, 8)) { 1034 dev_warn(pp->dev->dev.parent, 1035 "illegal buf_size value %d, round to %d\n", 1036 buf_size, ALIGN(buf_size, 8)); 1037 buf_size = ALIGN(buf_size, 8); 1038 } 1039 1040 val = mvreg_read(pp, MVNETA_PORT_POOL_BUFFER_SZ_REG(pool_id)); 1041 val |= buf_size & MVNETA_PORT_POOL_BUFFER_SZ_MASK; 1042 mvreg_write(pp, MVNETA_PORT_POOL_BUFFER_SZ_REG(pool_id), val); 1043 } 1044 1045 /* Configure MBUS window in order to enable access BM internal SRAM */ 1046 static int mvneta_mbus_io_win_set(struct mvneta_port *pp, u32 base, u32 wsize, 1047 u8 target, u8 attr) 1048 { 1049 u32 win_enable, win_protect; 1050 int i; 1051 1052 win_enable = mvreg_read(pp, MVNETA_BASE_ADDR_ENABLE); 1053 1054 if (pp->bm_win_id < 0) { 1055 /* Find first not occupied window */ 1056 for (i = 0; i < MVNETA_MAX_DECODE_WIN; i++) { 1057 if (win_enable & (1 << i)) { 1058 pp->bm_win_id = i; 1059 break; 1060 } 1061 } 1062 if (i == MVNETA_MAX_DECODE_WIN) 1063 return -ENOMEM; 1064 } else { 1065 i = pp->bm_win_id; 1066 } 1067 1068 mvreg_write(pp, MVNETA_WIN_BASE(i), 0); 1069 mvreg_write(pp, MVNETA_WIN_SIZE(i), 0); 1070 1071 if (i < 4) 1072 mvreg_write(pp, MVNETA_WIN_REMAP(i), 0); 1073 1074 mvreg_write(pp, MVNETA_WIN_BASE(i), (base & 0xffff0000) | 1075 (attr << 8) | target); 1076 1077 mvreg_write(pp, MVNETA_WIN_SIZE(i), (wsize - 1) & 0xffff0000); 1078 1079 win_protect = mvreg_read(pp, MVNETA_ACCESS_PROTECT_ENABLE); 1080 win_protect |= 3 << (2 * i); 1081 mvreg_write(pp, MVNETA_ACCESS_PROTECT_ENABLE, win_protect); 1082 1083 win_enable &= ~(1 << i); 1084 mvreg_write(pp, MVNETA_BASE_ADDR_ENABLE, win_enable); 1085 1086 return 0; 1087 } 1088 1089 static int mvneta_bm_port_mbus_init(struct mvneta_port *pp) 1090 { 1091 u32 wsize; 1092 u8 target, attr; 1093 int err; 1094 1095 /* Get BM window information */ 1096 err = mvebu_mbus_get_io_win_info(pp->bm_priv->bppi_phys_addr, &wsize, 1097 &target, &attr); 1098 if (err < 0) 1099 return err; 1100 1101 pp->bm_win_id = -1; 1102 1103 /* Open NETA -> BM window */ 1104 err = mvneta_mbus_io_win_set(pp, pp->bm_priv->bppi_phys_addr, wsize, 1105 target, attr); 1106 if (err < 0) { 1107 netdev_info(pp->dev, "fail to configure mbus window to BM\n"); 1108 return err; 1109 } 1110 return 0; 1111 } 1112 1113 /* Assign and initialize pools for port. In case of fail 1114 * buffer manager will remain disabled for current port. 1115 */ 1116 static int mvneta_bm_port_init(struct platform_device *pdev, 1117 struct mvneta_port *pp) 1118 { 1119 struct device_node *dn = pdev->dev.of_node; 1120 u32 long_pool_id, short_pool_id; 1121 1122 if (!pp->neta_armada3700) { 1123 int ret; 1124 1125 ret = mvneta_bm_port_mbus_init(pp); 1126 if (ret) 1127 return ret; 1128 } 1129 1130 if (of_property_read_u32(dn, "bm,pool-long", &long_pool_id)) { 1131 netdev_info(pp->dev, "missing long pool id\n"); 1132 return -EINVAL; 1133 } 1134 1135 /* Create port's long pool depending on mtu */ 1136 pp->pool_long = mvneta_bm_pool_use(pp->bm_priv, long_pool_id, 1137 MVNETA_BM_LONG, pp->id, 1138 MVNETA_RX_PKT_SIZE(pp->dev->mtu)); 1139 if (!pp->pool_long) { 1140 netdev_info(pp->dev, "fail to obtain long pool for port\n"); 1141 return -ENOMEM; 1142 } 1143 1144 pp->pool_long->port_map |= 1 << pp->id; 1145 1146 mvneta_bm_pool_bufsize_set(pp, pp->pool_long->buf_size, 1147 pp->pool_long->id); 1148 1149 /* If short pool id is not defined, assume using single pool */ 1150 if (of_property_read_u32(dn, "bm,pool-short", &short_pool_id)) 1151 short_pool_id = long_pool_id; 1152 1153 /* Create port's short pool */ 1154 pp->pool_short = mvneta_bm_pool_use(pp->bm_priv, short_pool_id, 1155 MVNETA_BM_SHORT, pp->id, 1156 MVNETA_BM_SHORT_PKT_SIZE); 1157 if (!pp->pool_short) { 1158 netdev_info(pp->dev, "fail to obtain short pool for port\n"); 1159 mvneta_bm_pool_destroy(pp->bm_priv, pp->pool_long, 1 << pp->id); 1160 return -ENOMEM; 1161 } 1162 1163 if (short_pool_id != long_pool_id) { 1164 pp->pool_short->port_map |= 1 << pp->id; 1165 mvneta_bm_pool_bufsize_set(pp, pp->pool_short->buf_size, 1166 pp->pool_short->id); 1167 } 1168 1169 return 0; 1170 } 1171 1172 /* Update settings of a pool for bigger packets */ 1173 static void mvneta_bm_update_mtu(struct mvneta_port *pp, int mtu) 1174 { 1175 struct mvneta_bm_pool *bm_pool = pp->pool_long; 1176 struct hwbm_pool *hwbm_pool = &bm_pool->hwbm_pool; 1177 int num; 1178 1179 /* Release all buffers from long pool */ 1180 mvneta_bm_bufs_free(pp->bm_priv, bm_pool, 1 << pp->id); 1181 if (hwbm_pool->buf_num) { 1182 WARN(1, "cannot free all buffers in pool %d\n", 1183 bm_pool->id); 1184 goto bm_mtu_err; 1185 } 1186 1187 bm_pool->pkt_size = MVNETA_RX_PKT_SIZE(mtu); 1188 bm_pool->buf_size = MVNETA_RX_BUF_SIZE(bm_pool->pkt_size); 1189 hwbm_pool->frag_size = SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) + 1190 SKB_DATA_ALIGN(MVNETA_RX_BUF_SIZE(bm_pool->pkt_size)); 1191 1192 /* Fill entire long pool */ 1193 num = hwbm_pool_add(hwbm_pool, hwbm_pool->size); 1194 if (num != hwbm_pool->size) { 1195 WARN(1, "pool %d: %d of %d allocated\n", 1196 bm_pool->id, num, hwbm_pool->size); 1197 goto bm_mtu_err; 1198 } 1199 mvneta_bm_pool_bufsize_set(pp, bm_pool->buf_size, bm_pool->id); 1200 1201 return; 1202 1203 bm_mtu_err: 1204 mvneta_bm_pool_destroy(pp->bm_priv, pp->pool_long, 1 << pp->id); 1205 mvneta_bm_pool_destroy(pp->bm_priv, pp->pool_short, 1 << pp->id); 1206 1207 pp->bm_priv = NULL; 1208 pp->rx_offset_correction = MVNETA_SKB_HEADROOM; 1209 mvreg_write(pp, MVNETA_ACC_MODE, MVNETA_ACC_MODE_EXT1); 1210 netdev_info(pp->dev, "fail to update MTU, fall back to software BM\n"); 1211 } 1212 1213 /* Start the Ethernet port RX and TX activity */ 1214 static void mvneta_port_up(struct mvneta_port *pp) 1215 { 1216 int queue; 1217 u32 q_map; 1218 1219 /* Enable all initialized TXs. */ 1220 q_map = 0; 1221 for (queue = 0; queue < txq_number; queue++) { 1222 struct mvneta_tx_queue *txq = &pp->txqs[queue]; 1223 if (txq->descs) 1224 q_map |= (1 << queue); 1225 } 1226 mvreg_write(pp, MVNETA_TXQ_CMD, q_map); 1227 1228 q_map = 0; 1229 /* Enable all initialized RXQs. */ 1230 for (queue = 0; queue < rxq_number; queue++) { 1231 struct mvneta_rx_queue *rxq = &pp->rxqs[queue]; 1232 1233 if (rxq->descs) 1234 q_map |= (1 << queue); 1235 } 1236 mvreg_write(pp, MVNETA_RXQ_CMD, q_map); 1237 } 1238 1239 /* Stop the Ethernet port activity */ 1240 static void mvneta_port_down(struct mvneta_port *pp) 1241 { 1242 u32 val; 1243 int count; 1244 1245 /* Stop Rx port activity. Check port Rx activity. */ 1246 val = mvreg_read(pp, MVNETA_RXQ_CMD) & MVNETA_RXQ_ENABLE_MASK; 1247 1248 /* Issue stop command for active channels only */ 1249 if (val != 0) 1250 mvreg_write(pp, MVNETA_RXQ_CMD, 1251 val << MVNETA_RXQ_DISABLE_SHIFT); 1252 1253 /* Wait for all Rx activity to terminate. */ 1254 count = 0; 1255 do { 1256 if (count++ >= MVNETA_RX_DISABLE_TIMEOUT_MSEC) { 1257 netdev_warn(pp->dev, 1258 "TIMEOUT for RX stopped ! rx_queue_cmd: 0x%08x\n", 1259 val); 1260 break; 1261 } 1262 mdelay(1); 1263 1264 val = mvreg_read(pp, MVNETA_RXQ_CMD); 1265 } while (val & MVNETA_RXQ_ENABLE_MASK); 1266 1267 /* Stop Tx port activity. Check port Tx activity. Issue stop 1268 * command for active channels only 1269 */ 1270 val = (mvreg_read(pp, MVNETA_TXQ_CMD)) & MVNETA_TXQ_ENABLE_MASK; 1271 1272 if (val != 0) 1273 mvreg_write(pp, MVNETA_TXQ_CMD, 1274 (val << MVNETA_TXQ_DISABLE_SHIFT)); 1275 1276 /* Wait for all Tx activity to terminate. */ 1277 count = 0; 1278 do { 1279 if (count++ >= MVNETA_TX_DISABLE_TIMEOUT_MSEC) { 1280 netdev_warn(pp->dev, 1281 "TIMEOUT for TX stopped status=0x%08x\n", 1282 val); 1283 break; 1284 } 1285 mdelay(1); 1286 1287 /* Check TX Command reg that all Txqs are stopped */ 1288 val = mvreg_read(pp, MVNETA_TXQ_CMD); 1289 1290 } while (val & MVNETA_TXQ_ENABLE_MASK); 1291 1292 /* Double check to verify that TX FIFO is empty */ 1293 count = 0; 1294 do { 1295 if (count++ >= MVNETA_TX_FIFO_EMPTY_TIMEOUT) { 1296 netdev_warn(pp->dev, 1297 "TX FIFO empty timeout status=0x%08x\n", 1298 val); 1299 break; 1300 } 1301 mdelay(1); 1302 1303 val = mvreg_read(pp, MVNETA_PORT_STATUS); 1304 } while (!(val & MVNETA_TX_FIFO_EMPTY) && 1305 (val & MVNETA_TX_IN_PRGRS)); 1306 1307 udelay(200); 1308 } 1309 1310 /* Enable the port by setting the port enable bit of the MAC control register */ 1311 static void mvneta_port_enable(struct mvneta_port *pp) 1312 { 1313 u32 val; 1314 1315 /* Enable port */ 1316 val = mvreg_read(pp, MVNETA_GMAC_CTRL_0); 1317 val |= MVNETA_GMAC0_PORT_ENABLE; 1318 mvreg_write(pp, MVNETA_GMAC_CTRL_0, val); 1319 } 1320 1321 /* Disable the port and wait for about 200 usec before retuning */ 1322 static void mvneta_port_disable(struct mvneta_port *pp) 1323 { 1324 u32 val; 1325 1326 /* Reset the Enable bit in the Serial Control Register */ 1327 val = mvreg_read(pp, MVNETA_GMAC_CTRL_0); 1328 val &= ~MVNETA_GMAC0_PORT_ENABLE; 1329 mvreg_write(pp, MVNETA_GMAC_CTRL_0, val); 1330 1331 udelay(200); 1332 } 1333 1334 /* Multicast tables methods */ 1335 1336 /* Set all entries in Unicast MAC Table; queue==-1 means reject all */ 1337 static void mvneta_set_ucast_table(struct mvneta_port *pp, int queue) 1338 { 1339 int offset; 1340 u32 val; 1341 1342 if (queue == -1) { 1343 val = 0; 1344 } else { 1345 val = 0x1 | (queue << 1); 1346 val |= (val << 24) | (val << 16) | (val << 8); 1347 } 1348 1349 for (offset = 0; offset <= 0xc; offset += 4) 1350 mvreg_write(pp, MVNETA_DA_FILT_UCAST_BASE + offset, val); 1351 } 1352 1353 /* Set all entries in Special Multicast MAC Table; queue==-1 means reject all */ 1354 static void mvneta_set_special_mcast_table(struct mvneta_port *pp, int queue) 1355 { 1356 int offset; 1357 u32 val; 1358 1359 if (queue == -1) { 1360 val = 0; 1361 } else { 1362 val = 0x1 | (queue << 1); 1363 val |= (val << 24) | (val << 16) | (val << 8); 1364 } 1365 1366 for (offset = 0; offset <= 0xfc; offset += 4) 1367 mvreg_write(pp, MVNETA_DA_FILT_SPEC_MCAST + offset, val); 1368 1369 } 1370 1371 /* Set all entries in Other Multicast MAC Table. queue==-1 means reject all */ 1372 static void mvneta_set_other_mcast_table(struct mvneta_port *pp, int queue) 1373 { 1374 int offset; 1375 u32 val; 1376 1377 if (queue == -1) { 1378 memset(pp->mcast_count, 0, sizeof(pp->mcast_count)); 1379 val = 0; 1380 } else { 1381 memset(pp->mcast_count, 1, sizeof(pp->mcast_count)); 1382 val = 0x1 | (queue << 1); 1383 val |= (val << 24) | (val << 16) | (val << 8); 1384 } 1385 1386 for (offset = 0; offset <= 0xfc; offset += 4) 1387 mvreg_write(pp, MVNETA_DA_FILT_OTH_MCAST + offset, val); 1388 } 1389 1390 static void mvneta_percpu_unmask_interrupt(void *arg) 1391 { 1392 struct mvneta_port *pp = arg; 1393 1394 /* All the queue are unmasked, but actually only the ones 1395 * mapped to this CPU will be unmasked 1396 */ 1397 mvreg_write(pp, MVNETA_INTR_NEW_MASK, 1398 MVNETA_RX_INTR_MASK_ALL | 1399 MVNETA_TX_INTR_MASK_ALL | 1400 MVNETA_MISCINTR_INTR_MASK); 1401 } 1402 1403 static void mvneta_percpu_mask_interrupt(void *arg) 1404 { 1405 struct mvneta_port *pp = arg; 1406 1407 /* All the queue are masked, but actually only the ones 1408 * mapped to this CPU will be masked 1409 */ 1410 mvreg_write(pp, MVNETA_INTR_NEW_MASK, 0); 1411 mvreg_write(pp, MVNETA_INTR_OLD_MASK, 0); 1412 mvreg_write(pp, MVNETA_INTR_MISC_MASK, 0); 1413 } 1414 1415 static void mvneta_percpu_clear_intr_cause(void *arg) 1416 { 1417 struct mvneta_port *pp = arg; 1418 1419 /* All the queue are cleared, but actually only the ones 1420 * mapped to this CPU will be cleared 1421 */ 1422 mvreg_write(pp, MVNETA_INTR_NEW_CAUSE, 0); 1423 mvreg_write(pp, MVNETA_INTR_MISC_CAUSE, 0); 1424 mvreg_write(pp, MVNETA_INTR_OLD_CAUSE, 0); 1425 } 1426 1427 /* This method sets defaults to the NETA port: 1428 * Clears interrupt Cause and Mask registers. 1429 * Clears all MAC tables. 1430 * Sets defaults to all registers. 1431 * Resets RX and TX descriptor rings. 1432 * Resets PHY. 1433 * This method can be called after mvneta_port_down() to return the port 1434 * settings to defaults. 1435 */ 1436 static void mvneta_defaults_set(struct mvneta_port *pp) 1437 { 1438 int cpu; 1439 int queue; 1440 u32 val; 1441 int max_cpu = num_present_cpus(); 1442 1443 /* Clear all Cause registers */ 1444 on_each_cpu(mvneta_percpu_clear_intr_cause, pp, true); 1445 1446 /* Mask all interrupts */ 1447 on_each_cpu(mvneta_percpu_mask_interrupt, pp, true); 1448 mvreg_write(pp, MVNETA_INTR_ENABLE, 0); 1449 1450 /* Enable MBUS Retry bit16 */ 1451 mvreg_write(pp, MVNETA_MBUS_RETRY, 0x20); 1452 1453 /* Set CPU queue access map. CPUs are assigned to the RX and 1454 * TX queues modulo their number. If there is only one TX 1455 * queue then it is assigned to the CPU associated to the 1456 * default RX queue. 1457 */ 1458 for_each_present_cpu(cpu) { 1459 int rxq_map = 0, txq_map = 0; 1460 int rxq, txq; 1461 if (!pp->neta_armada3700) { 1462 for (rxq = 0; rxq < rxq_number; rxq++) 1463 if ((rxq % max_cpu) == cpu) 1464 rxq_map |= MVNETA_CPU_RXQ_ACCESS(rxq); 1465 1466 for (txq = 0; txq < txq_number; txq++) 1467 if ((txq % max_cpu) == cpu) 1468 txq_map |= MVNETA_CPU_TXQ_ACCESS(txq); 1469 1470 /* With only one TX queue we configure a special case 1471 * which will allow to get all the irq on a single 1472 * CPU 1473 */ 1474 if (txq_number == 1) 1475 txq_map = (cpu == pp->rxq_def) ? 1476 MVNETA_CPU_TXQ_ACCESS(1) : 0; 1477 1478 } else { 1479 txq_map = MVNETA_CPU_TXQ_ACCESS_ALL_MASK; 1480 rxq_map = MVNETA_CPU_RXQ_ACCESS_ALL_MASK; 1481 } 1482 1483 mvreg_write(pp, MVNETA_CPU_MAP(cpu), rxq_map | txq_map); 1484 } 1485 1486 /* Reset RX and TX DMAs */ 1487 mvreg_write(pp, MVNETA_PORT_RX_RESET, MVNETA_PORT_RX_DMA_RESET); 1488 mvreg_write(pp, MVNETA_PORT_TX_RESET, MVNETA_PORT_TX_DMA_RESET); 1489 1490 /* Disable Legacy WRR, Disable EJP, Release from reset */ 1491 mvreg_write(pp, MVNETA_TXQ_CMD_1, 0); 1492 for (queue = 0; queue < txq_number; queue++) { 1493 mvreg_write(pp, MVETH_TXQ_TOKEN_COUNT_REG(queue), 0); 1494 mvreg_write(pp, MVETH_TXQ_TOKEN_CFG_REG(queue), 0); 1495 } 1496 1497 mvreg_write(pp, MVNETA_PORT_TX_RESET, 0); 1498 mvreg_write(pp, MVNETA_PORT_RX_RESET, 0); 1499 1500 /* Set Port Acceleration Mode */ 1501 if (pp->bm_priv) 1502 /* HW buffer management + legacy parser */ 1503 val = MVNETA_ACC_MODE_EXT2; 1504 else 1505 /* SW buffer management + legacy parser */ 1506 val = MVNETA_ACC_MODE_EXT1; 1507 mvreg_write(pp, MVNETA_ACC_MODE, val); 1508 1509 if (pp->bm_priv) 1510 mvreg_write(pp, MVNETA_BM_ADDRESS, pp->bm_priv->bppi_phys_addr); 1511 1512 /* Update val of portCfg register accordingly with all RxQueue types */ 1513 val = MVNETA_PORT_CONFIG_DEFL_VALUE(pp->rxq_def); 1514 mvreg_write(pp, MVNETA_PORT_CONFIG, val); 1515 1516 val = 0; 1517 mvreg_write(pp, MVNETA_PORT_CONFIG_EXTEND, val); 1518 mvreg_write(pp, MVNETA_RX_MIN_FRAME_SIZE, 64); 1519 1520 /* Build PORT_SDMA_CONFIG_REG */ 1521 val = 0; 1522 1523 /* Default burst size */ 1524 val |= MVNETA_TX_BRST_SZ_MASK(MVNETA_SDMA_BRST_SIZE_16); 1525 val |= MVNETA_RX_BRST_SZ_MASK(MVNETA_SDMA_BRST_SIZE_16); 1526 val |= MVNETA_RX_NO_DATA_SWAP | MVNETA_TX_NO_DATA_SWAP; 1527 1528 #if defined(__BIG_ENDIAN) 1529 val |= MVNETA_DESC_SWAP; 1530 #endif 1531 1532 /* Assign port SDMA configuration */ 1533 mvreg_write(pp, MVNETA_SDMA_CONFIG, val); 1534 1535 /* Disable PHY polling in hardware, since we're using the 1536 * kernel phylib to do this. 1537 */ 1538 val = mvreg_read(pp, MVNETA_UNIT_CONTROL); 1539 val &= ~MVNETA_PHY_POLLING_ENABLE; 1540 mvreg_write(pp, MVNETA_UNIT_CONTROL, val); 1541 1542 mvneta_set_ucast_table(pp, -1); 1543 mvneta_set_special_mcast_table(pp, -1); 1544 mvneta_set_other_mcast_table(pp, -1); 1545 1546 /* Set port interrupt enable register - default enable all */ 1547 mvreg_write(pp, MVNETA_INTR_ENABLE, 1548 (MVNETA_RXQ_INTR_ENABLE_ALL_MASK 1549 | MVNETA_TXQ_INTR_ENABLE_ALL_MASK)); 1550 1551 mvneta_mib_counters_clear(pp); 1552 } 1553 1554 /* Set max sizes for tx queues */ 1555 static void mvneta_txq_max_tx_size_set(struct mvneta_port *pp, int max_tx_size) 1556 1557 { 1558 u32 val, size, mtu; 1559 int queue; 1560 1561 mtu = max_tx_size * 8; 1562 if (mtu > MVNETA_TX_MTU_MAX) 1563 mtu = MVNETA_TX_MTU_MAX; 1564 1565 /* Set MTU */ 1566 val = mvreg_read(pp, MVNETA_TX_MTU); 1567 val &= ~MVNETA_TX_MTU_MAX; 1568 val |= mtu; 1569 mvreg_write(pp, MVNETA_TX_MTU, val); 1570 1571 /* TX token size and all TXQs token size must be larger that MTU */ 1572 val = mvreg_read(pp, MVNETA_TX_TOKEN_SIZE); 1573 1574 size = val & MVNETA_TX_TOKEN_SIZE_MAX; 1575 if (size < mtu) { 1576 size = mtu; 1577 val &= ~MVNETA_TX_TOKEN_SIZE_MAX; 1578 val |= size; 1579 mvreg_write(pp, MVNETA_TX_TOKEN_SIZE, val); 1580 } 1581 for (queue = 0; queue < txq_number; queue++) { 1582 val = mvreg_read(pp, MVNETA_TXQ_TOKEN_SIZE_REG(queue)); 1583 1584 size = val & MVNETA_TXQ_TOKEN_SIZE_MAX; 1585 if (size < mtu) { 1586 size = mtu; 1587 val &= ~MVNETA_TXQ_TOKEN_SIZE_MAX; 1588 val |= size; 1589 mvreg_write(pp, MVNETA_TXQ_TOKEN_SIZE_REG(queue), val); 1590 } 1591 } 1592 } 1593 1594 /* Set unicast address */ 1595 static void mvneta_set_ucast_addr(struct mvneta_port *pp, u8 last_nibble, 1596 int queue) 1597 { 1598 unsigned int unicast_reg; 1599 unsigned int tbl_offset; 1600 unsigned int reg_offset; 1601 1602 /* Locate the Unicast table entry */ 1603 last_nibble = (0xf & last_nibble); 1604 1605 /* offset from unicast tbl base */ 1606 tbl_offset = (last_nibble / 4) * 4; 1607 1608 /* offset within the above reg */ 1609 reg_offset = last_nibble % 4; 1610 1611 unicast_reg = mvreg_read(pp, (MVNETA_DA_FILT_UCAST_BASE + tbl_offset)); 1612 1613 if (queue == -1) { 1614 /* Clear accepts frame bit at specified unicast DA tbl entry */ 1615 unicast_reg &= ~(0xff << (8 * reg_offset)); 1616 } else { 1617 unicast_reg &= ~(0xff << (8 * reg_offset)); 1618 unicast_reg |= ((0x01 | (queue << 1)) << (8 * reg_offset)); 1619 } 1620 1621 mvreg_write(pp, (MVNETA_DA_FILT_UCAST_BASE + tbl_offset), unicast_reg); 1622 } 1623 1624 /* Set mac address */ 1625 static void mvneta_mac_addr_set(struct mvneta_port *pp, unsigned char *addr, 1626 int queue) 1627 { 1628 unsigned int mac_h; 1629 unsigned int mac_l; 1630 1631 if (queue != -1) { 1632 mac_l = (addr[4] << 8) | (addr[5]); 1633 mac_h = (addr[0] << 24) | (addr[1] << 16) | 1634 (addr[2] << 8) | (addr[3] << 0); 1635 1636 mvreg_write(pp, MVNETA_MAC_ADDR_LOW, mac_l); 1637 mvreg_write(pp, MVNETA_MAC_ADDR_HIGH, mac_h); 1638 } 1639 1640 /* Accept frames of this address */ 1641 mvneta_set_ucast_addr(pp, addr[5], queue); 1642 } 1643 1644 /* Set the number of packets that will be received before RX interrupt 1645 * will be generated by HW. 1646 */ 1647 static void mvneta_rx_pkts_coal_set(struct mvneta_port *pp, 1648 struct mvneta_rx_queue *rxq, u32 value) 1649 { 1650 mvreg_write(pp, MVNETA_RXQ_THRESHOLD_REG(rxq->id), 1651 value | MVNETA_RXQ_NON_OCCUPIED(0)); 1652 } 1653 1654 /* Set the time delay in usec before RX interrupt will be generated by 1655 * HW. 1656 */ 1657 static void mvneta_rx_time_coal_set(struct mvneta_port *pp, 1658 struct mvneta_rx_queue *rxq, u32 value) 1659 { 1660 u32 val; 1661 unsigned long clk_rate; 1662 1663 clk_rate = clk_get_rate(pp->clk); 1664 val = (clk_rate / 1000000) * value; 1665 1666 mvreg_write(pp, MVNETA_RXQ_TIME_COAL_REG(rxq->id), val); 1667 } 1668 1669 /* Set threshold for TX_DONE pkts coalescing */ 1670 static void mvneta_tx_done_pkts_coal_set(struct mvneta_port *pp, 1671 struct mvneta_tx_queue *txq, u32 value) 1672 { 1673 u32 val; 1674 1675 val = mvreg_read(pp, MVNETA_TXQ_SIZE_REG(txq->id)); 1676 1677 val &= ~MVNETA_TXQ_SENT_THRESH_ALL_MASK; 1678 val |= MVNETA_TXQ_SENT_THRESH_MASK(value); 1679 1680 mvreg_write(pp, MVNETA_TXQ_SIZE_REG(txq->id), val); 1681 } 1682 1683 /* Handle rx descriptor fill by setting buf_cookie and buf_phys_addr */ 1684 static void mvneta_rx_desc_fill(struct mvneta_rx_desc *rx_desc, 1685 u32 phys_addr, void *virt_addr, 1686 struct mvneta_rx_queue *rxq) 1687 { 1688 int i; 1689 1690 rx_desc->buf_phys_addr = phys_addr; 1691 i = rx_desc - rxq->descs; 1692 rxq->buf_virt_addr[i] = virt_addr; 1693 } 1694 1695 /* Decrement sent descriptors counter */ 1696 static void mvneta_txq_sent_desc_dec(struct mvneta_port *pp, 1697 struct mvneta_tx_queue *txq, 1698 int sent_desc) 1699 { 1700 u32 val; 1701 1702 /* Only 255 TX descriptors can be updated at once */ 1703 while (sent_desc > 0xff) { 1704 val = 0xff << MVNETA_TXQ_DEC_SENT_SHIFT; 1705 mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val); 1706 sent_desc = sent_desc - 0xff; 1707 } 1708 1709 val = sent_desc << MVNETA_TXQ_DEC_SENT_SHIFT; 1710 mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val); 1711 } 1712 1713 /* Get number of TX descriptors already sent by HW */ 1714 static int mvneta_txq_sent_desc_num_get(struct mvneta_port *pp, 1715 struct mvneta_tx_queue *txq) 1716 { 1717 u32 val; 1718 int sent_desc; 1719 1720 val = mvreg_read(pp, MVNETA_TXQ_STATUS_REG(txq->id)); 1721 sent_desc = (val & MVNETA_TXQ_SENT_DESC_MASK) >> 1722 MVNETA_TXQ_SENT_DESC_SHIFT; 1723 1724 return sent_desc; 1725 } 1726 1727 /* Get number of sent descriptors and decrement counter. 1728 * The number of sent descriptors is returned. 1729 */ 1730 static int mvneta_txq_sent_desc_proc(struct mvneta_port *pp, 1731 struct mvneta_tx_queue *txq) 1732 { 1733 int sent_desc; 1734 1735 /* Get number of sent descriptors */ 1736 sent_desc = mvneta_txq_sent_desc_num_get(pp, txq); 1737 1738 /* Decrement sent descriptors counter */ 1739 if (sent_desc) 1740 mvneta_txq_sent_desc_dec(pp, txq, sent_desc); 1741 1742 return sent_desc; 1743 } 1744 1745 /* Set TXQ descriptors fields relevant for CSUM calculation */ 1746 static u32 mvneta_txq_desc_csum(int l3_offs, int l3_proto, 1747 int ip_hdr_len, int l4_proto) 1748 { 1749 u32 command; 1750 1751 /* Fields: L3_offset, IP_hdrlen, L3_type, G_IPv4_chk, 1752 * G_L4_chk, L4_type; required only for checksum 1753 * calculation 1754 */ 1755 command = l3_offs << MVNETA_TX_L3_OFF_SHIFT; 1756 command |= ip_hdr_len << MVNETA_TX_IP_HLEN_SHIFT; 1757 1758 if (l3_proto == htons(ETH_P_IP)) 1759 command |= MVNETA_TXD_IP_CSUM; 1760 else 1761 command |= MVNETA_TX_L3_IP6; 1762 1763 if (l4_proto == IPPROTO_TCP) 1764 command |= MVNETA_TX_L4_CSUM_FULL; 1765 else if (l4_proto == IPPROTO_UDP) 1766 command |= MVNETA_TX_L4_UDP | MVNETA_TX_L4_CSUM_FULL; 1767 else 1768 command |= MVNETA_TX_L4_CSUM_NOT; 1769 1770 return command; 1771 } 1772 1773 1774 /* Display more error info */ 1775 static void mvneta_rx_error(struct mvneta_port *pp, 1776 struct mvneta_rx_desc *rx_desc) 1777 { 1778 struct mvneta_pcpu_stats *stats = this_cpu_ptr(pp->stats); 1779 u32 status = rx_desc->status; 1780 1781 /* update per-cpu counter */ 1782 u64_stats_update_begin(&stats->syncp); 1783 stats->rx_errors++; 1784 u64_stats_update_end(&stats->syncp); 1785 1786 switch (status & MVNETA_RXD_ERR_CODE_MASK) { 1787 case MVNETA_RXD_ERR_CRC: 1788 netdev_err(pp->dev, "bad rx status %08x (crc error), size=%d\n", 1789 status, rx_desc->data_size); 1790 break; 1791 case MVNETA_RXD_ERR_OVERRUN: 1792 netdev_err(pp->dev, "bad rx status %08x (overrun error), size=%d\n", 1793 status, rx_desc->data_size); 1794 break; 1795 case MVNETA_RXD_ERR_LEN: 1796 netdev_err(pp->dev, "bad rx status %08x (max frame length error), size=%d\n", 1797 status, rx_desc->data_size); 1798 break; 1799 case MVNETA_RXD_ERR_RESOURCE: 1800 netdev_err(pp->dev, "bad rx status %08x (resource error), size=%d\n", 1801 status, rx_desc->data_size); 1802 break; 1803 } 1804 } 1805 1806 /* Handle RX checksum offload based on the descriptor's status */ 1807 static void mvneta_rx_csum(struct mvneta_port *pp, u32 status, 1808 struct sk_buff *skb) 1809 { 1810 if ((pp->dev->features & NETIF_F_RXCSUM) && 1811 (status & MVNETA_RXD_L3_IP4) && 1812 (status & MVNETA_RXD_L4_CSUM_OK)) { 1813 skb->csum = 0; 1814 skb->ip_summed = CHECKSUM_UNNECESSARY; 1815 return; 1816 } 1817 1818 skb->ip_summed = CHECKSUM_NONE; 1819 } 1820 1821 /* Return tx queue pointer (find last set bit) according to <cause> returned 1822 * form tx_done reg. <cause> must not be null. The return value is always a 1823 * valid queue for matching the first one found in <cause>. 1824 */ 1825 static struct mvneta_tx_queue *mvneta_tx_done_policy(struct mvneta_port *pp, 1826 u32 cause) 1827 { 1828 int queue = fls(cause) - 1; 1829 1830 return &pp->txqs[queue]; 1831 } 1832 1833 /* Free tx queue skbuffs */ 1834 static void mvneta_txq_bufs_free(struct mvneta_port *pp, 1835 struct mvneta_tx_queue *txq, int num, 1836 struct netdev_queue *nq) 1837 { 1838 unsigned int bytes_compl = 0, pkts_compl = 0; 1839 int i; 1840 1841 for (i = 0; i < num; i++) { 1842 struct mvneta_tx_buf *buf = &txq->buf[txq->txq_get_index]; 1843 struct mvneta_tx_desc *tx_desc = txq->descs + 1844 txq->txq_get_index; 1845 1846 mvneta_txq_inc_get(txq); 1847 1848 if (!IS_TSO_HEADER(txq, tx_desc->buf_phys_addr) && 1849 buf->type != MVNETA_TYPE_XDP_TX) 1850 dma_unmap_single(pp->dev->dev.parent, 1851 tx_desc->buf_phys_addr, 1852 tx_desc->data_size, DMA_TO_DEVICE); 1853 if (buf->type == MVNETA_TYPE_SKB && buf->skb) { 1854 bytes_compl += buf->skb->len; 1855 pkts_compl++; 1856 dev_kfree_skb_any(buf->skb); 1857 } else if (buf->type == MVNETA_TYPE_XDP_TX || 1858 buf->type == MVNETA_TYPE_XDP_NDO) { 1859 xdp_return_frame(buf->xdpf); 1860 } 1861 } 1862 1863 netdev_tx_completed_queue(nq, pkts_compl, bytes_compl); 1864 } 1865 1866 /* Handle end of transmission */ 1867 static void mvneta_txq_done(struct mvneta_port *pp, 1868 struct mvneta_tx_queue *txq) 1869 { 1870 struct netdev_queue *nq = netdev_get_tx_queue(pp->dev, txq->id); 1871 int tx_done; 1872 1873 tx_done = mvneta_txq_sent_desc_proc(pp, txq); 1874 if (!tx_done) 1875 return; 1876 1877 mvneta_txq_bufs_free(pp, txq, tx_done, nq); 1878 1879 txq->count -= tx_done; 1880 1881 if (netif_tx_queue_stopped(nq)) { 1882 if (txq->count <= txq->tx_wake_threshold) 1883 netif_tx_wake_queue(nq); 1884 } 1885 } 1886 1887 /* Refill processing for SW buffer management */ 1888 /* Allocate page per descriptor */ 1889 static int mvneta_rx_refill(struct mvneta_port *pp, 1890 struct mvneta_rx_desc *rx_desc, 1891 struct mvneta_rx_queue *rxq, 1892 gfp_t gfp_mask) 1893 { 1894 dma_addr_t phys_addr; 1895 struct page *page; 1896 1897 page = page_pool_alloc_pages(rxq->page_pool, 1898 gfp_mask | __GFP_NOWARN); 1899 if (!page) 1900 return -ENOMEM; 1901 1902 phys_addr = page_pool_get_dma_addr(page) + pp->rx_offset_correction; 1903 mvneta_rx_desc_fill(rx_desc, phys_addr, page, rxq); 1904 1905 return 0; 1906 } 1907 1908 /* Handle tx checksum */ 1909 static u32 mvneta_skb_tx_csum(struct mvneta_port *pp, struct sk_buff *skb) 1910 { 1911 if (skb->ip_summed == CHECKSUM_PARTIAL) { 1912 int ip_hdr_len = 0; 1913 __be16 l3_proto = vlan_get_protocol(skb); 1914 u8 l4_proto; 1915 1916 if (l3_proto == htons(ETH_P_IP)) { 1917 struct iphdr *ip4h = ip_hdr(skb); 1918 1919 /* Calculate IPv4 checksum and L4 checksum */ 1920 ip_hdr_len = ip4h->ihl; 1921 l4_proto = ip4h->protocol; 1922 } else if (l3_proto == htons(ETH_P_IPV6)) { 1923 struct ipv6hdr *ip6h = ipv6_hdr(skb); 1924 1925 /* Read l4_protocol from one of IPv6 extra headers */ 1926 if (skb_network_header_len(skb) > 0) 1927 ip_hdr_len = (skb_network_header_len(skb) >> 2); 1928 l4_proto = ip6h->nexthdr; 1929 } else 1930 return MVNETA_TX_L4_CSUM_NOT; 1931 1932 return mvneta_txq_desc_csum(skb_network_offset(skb), 1933 l3_proto, ip_hdr_len, l4_proto); 1934 } 1935 1936 return MVNETA_TX_L4_CSUM_NOT; 1937 } 1938 1939 /* Drop packets received by the RXQ and free buffers */ 1940 static void mvneta_rxq_drop_pkts(struct mvneta_port *pp, 1941 struct mvneta_rx_queue *rxq) 1942 { 1943 int rx_done, i; 1944 1945 rx_done = mvneta_rxq_busy_desc_num_get(pp, rxq); 1946 if (rx_done) 1947 mvneta_rxq_desc_num_update(pp, rxq, rx_done, rx_done); 1948 1949 if (pp->bm_priv) { 1950 for (i = 0; i < rx_done; i++) { 1951 struct mvneta_rx_desc *rx_desc = 1952 mvneta_rxq_next_desc_get(rxq); 1953 u8 pool_id = MVNETA_RX_GET_BM_POOL_ID(rx_desc); 1954 struct mvneta_bm_pool *bm_pool; 1955 1956 bm_pool = &pp->bm_priv->bm_pools[pool_id]; 1957 /* Return dropped buffer to the pool */ 1958 mvneta_bm_pool_put_bp(pp->bm_priv, bm_pool, 1959 rx_desc->buf_phys_addr); 1960 } 1961 return; 1962 } 1963 1964 for (i = 0; i < rxq->size; i++) { 1965 struct mvneta_rx_desc *rx_desc = rxq->descs + i; 1966 void *data = rxq->buf_virt_addr[i]; 1967 if (!data || !(rx_desc->buf_phys_addr)) 1968 continue; 1969 1970 page_pool_put_full_page(rxq->page_pool, data, false); 1971 } 1972 if (xdp_rxq_info_is_reg(&rxq->xdp_rxq)) 1973 xdp_rxq_info_unreg(&rxq->xdp_rxq); 1974 page_pool_destroy(rxq->page_pool); 1975 rxq->page_pool = NULL; 1976 } 1977 1978 static void 1979 mvneta_update_stats(struct mvneta_port *pp, 1980 struct mvneta_stats *ps) 1981 { 1982 struct mvneta_pcpu_stats *stats = this_cpu_ptr(pp->stats); 1983 1984 u64_stats_update_begin(&stats->syncp); 1985 stats->es.ps.rx_packets += ps->rx_packets; 1986 stats->es.ps.rx_bytes += ps->rx_bytes; 1987 /* xdp */ 1988 stats->es.ps.xdp_redirect += ps->xdp_redirect; 1989 stats->es.ps.xdp_pass += ps->xdp_pass; 1990 stats->es.ps.xdp_drop += ps->xdp_drop; 1991 u64_stats_update_end(&stats->syncp); 1992 } 1993 1994 static inline 1995 int mvneta_rx_refill_queue(struct mvneta_port *pp, struct mvneta_rx_queue *rxq) 1996 { 1997 struct mvneta_rx_desc *rx_desc; 1998 int curr_desc = rxq->first_to_refill; 1999 int i; 2000 2001 for (i = 0; (i < rxq->refill_num) && (i < 64); i++) { 2002 rx_desc = rxq->descs + curr_desc; 2003 if (!(rx_desc->buf_phys_addr)) { 2004 if (mvneta_rx_refill(pp, rx_desc, rxq, GFP_ATOMIC)) { 2005 struct mvneta_pcpu_stats *stats; 2006 2007 pr_err("Can't refill queue %d. Done %d from %d\n", 2008 rxq->id, i, rxq->refill_num); 2009 2010 stats = this_cpu_ptr(pp->stats); 2011 u64_stats_update_begin(&stats->syncp); 2012 stats->es.refill_error++; 2013 u64_stats_update_end(&stats->syncp); 2014 break; 2015 } 2016 } 2017 curr_desc = MVNETA_QUEUE_NEXT_DESC(rxq, curr_desc); 2018 } 2019 rxq->refill_num -= i; 2020 rxq->first_to_refill = curr_desc; 2021 2022 return i; 2023 } 2024 2025 static void 2026 mvneta_xdp_put_buff(struct mvneta_port *pp, struct mvneta_rx_queue *rxq, 2027 struct xdp_buff *xdp, int sync_len, bool napi) 2028 { 2029 struct skb_shared_info *sinfo = xdp_get_shared_info_from_buff(xdp); 2030 int i; 2031 2032 page_pool_put_page(rxq->page_pool, virt_to_head_page(xdp->data), 2033 sync_len, napi); 2034 for (i = 0; i < sinfo->nr_frags; i++) 2035 page_pool_put_full_page(rxq->page_pool, 2036 skb_frag_page(&sinfo->frags[i]), napi); 2037 } 2038 2039 static int 2040 mvneta_xdp_submit_frame(struct mvneta_port *pp, struct mvneta_tx_queue *txq, 2041 struct xdp_frame *xdpf, bool dma_map) 2042 { 2043 struct mvneta_tx_desc *tx_desc; 2044 struct mvneta_tx_buf *buf; 2045 dma_addr_t dma_addr; 2046 2047 if (txq->count >= txq->tx_stop_threshold) 2048 return MVNETA_XDP_DROPPED; 2049 2050 tx_desc = mvneta_txq_next_desc_get(txq); 2051 2052 buf = &txq->buf[txq->txq_put_index]; 2053 if (dma_map) { 2054 /* ndo_xdp_xmit */ 2055 dma_addr = dma_map_single(pp->dev->dev.parent, xdpf->data, 2056 xdpf->len, DMA_TO_DEVICE); 2057 if (dma_mapping_error(pp->dev->dev.parent, dma_addr)) { 2058 mvneta_txq_desc_put(txq); 2059 return MVNETA_XDP_DROPPED; 2060 } 2061 buf->type = MVNETA_TYPE_XDP_NDO; 2062 } else { 2063 struct page *page = virt_to_page(xdpf->data); 2064 2065 dma_addr = page_pool_get_dma_addr(page) + 2066 sizeof(*xdpf) + xdpf->headroom; 2067 dma_sync_single_for_device(pp->dev->dev.parent, dma_addr, 2068 xdpf->len, DMA_BIDIRECTIONAL); 2069 buf->type = MVNETA_TYPE_XDP_TX; 2070 } 2071 buf->xdpf = xdpf; 2072 2073 tx_desc->command = MVNETA_TXD_FLZ_DESC; 2074 tx_desc->buf_phys_addr = dma_addr; 2075 tx_desc->data_size = xdpf->len; 2076 2077 mvneta_txq_inc_put(txq); 2078 txq->pending++; 2079 txq->count++; 2080 2081 return MVNETA_XDP_TX; 2082 } 2083 2084 static int 2085 mvneta_xdp_xmit_back(struct mvneta_port *pp, struct xdp_buff *xdp) 2086 { 2087 struct mvneta_pcpu_stats *stats = this_cpu_ptr(pp->stats); 2088 struct mvneta_tx_queue *txq; 2089 struct netdev_queue *nq; 2090 struct xdp_frame *xdpf; 2091 int cpu; 2092 u32 ret; 2093 2094 xdpf = xdp_convert_buff_to_frame(xdp); 2095 if (unlikely(!xdpf)) 2096 return MVNETA_XDP_DROPPED; 2097 2098 cpu = smp_processor_id(); 2099 txq = &pp->txqs[cpu % txq_number]; 2100 nq = netdev_get_tx_queue(pp->dev, txq->id); 2101 2102 __netif_tx_lock(nq, cpu); 2103 ret = mvneta_xdp_submit_frame(pp, txq, xdpf, false); 2104 if (ret == MVNETA_XDP_TX) { 2105 u64_stats_update_begin(&stats->syncp); 2106 stats->es.ps.tx_bytes += xdpf->len; 2107 stats->es.ps.tx_packets++; 2108 stats->es.ps.xdp_tx++; 2109 u64_stats_update_end(&stats->syncp); 2110 2111 mvneta_txq_pend_desc_add(pp, txq, 0); 2112 } else { 2113 u64_stats_update_begin(&stats->syncp); 2114 stats->es.ps.xdp_tx_err++; 2115 u64_stats_update_end(&stats->syncp); 2116 } 2117 __netif_tx_unlock(nq); 2118 2119 return ret; 2120 } 2121 2122 static int 2123 mvneta_xdp_xmit(struct net_device *dev, int num_frame, 2124 struct xdp_frame **frames, u32 flags) 2125 { 2126 struct mvneta_port *pp = netdev_priv(dev); 2127 struct mvneta_pcpu_stats *stats = this_cpu_ptr(pp->stats); 2128 int i, nxmit_byte = 0, nxmit = num_frame; 2129 int cpu = smp_processor_id(); 2130 struct mvneta_tx_queue *txq; 2131 struct netdev_queue *nq; 2132 u32 ret; 2133 2134 if (unlikely(test_bit(__MVNETA_DOWN, &pp->state))) 2135 return -ENETDOWN; 2136 2137 if (unlikely(flags & ~XDP_XMIT_FLAGS_MASK)) 2138 return -EINVAL; 2139 2140 txq = &pp->txqs[cpu % txq_number]; 2141 nq = netdev_get_tx_queue(pp->dev, txq->id); 2142 2143 __netif_tx_lock(nq, cpu); 2144 for (i = 0; i < num_frame; i++) { 2145 ret = mvneta_xdp_submit_frame(pp, txq, frames[i], true); 2146 if (ret == MVNETA_XDP_TX) { 2147 nxmit_byte += frames[i]->len; 2148 } else { 2149 xdp_return_frame_rx_napi(frames[i]); 2150 nxmit--; 2151 } 2152 } 2153 2154 if (unlikely(flags & XDP_XMIT_FLUSH)) 2155 mvneta_txq_pend_desc_add(pp, txq, 0); 2156 __netif_tx_unlock(nq); 2157 2158 u64_stats_update_begin(&stats->syncp); 2159 stats->es.ps.tx_bytes += nxmit_byte; 2160 stats->es.ps.tx_packets += nxmit; 2161 stats->es.ps.xdp_xmit += nxmit; 2162 stats->es.ps.xdp_xmit_err += num_frame - nxmit; 2163 u64_stats_update_end(&stats->syncp); 2164 2165 return nxmit; 2166 } 2167 2168 static int 2169 mvneta_run_xdp(struct mvneta_port *pp, struct mvneta_rx_queue *rxq, 2170 struct bpf_prog *prog, struct xdp_buff *xdp, 2171 u32 frame_sz, struct mvneta_stats *stats) 2172 { 2173 unsigned int len, data_len, sync; 2174 u32 ret, act; 2175 2176 len = xdp->data_end - xdp->data_hard_start - pp->rx_offset_correction; 2177 data_len = xdp->data_end - xdp->data; 2178 act = bpf_prog_run_xdp(prog, xdp); 2179 2180 /* Due xdp_adjust_tail: DMA sync for_device cover max len CPU touch */ 2181 sync = xdp->data_end - xdp->data_hard_start - pp->rx_offset_correction; 2182 sync = max(sync, len); 2183 2184 switch (act) { 2185 case XDP_PASS: 2186 stats->xdp_pass++; 2187 return MVNETA_XDP_PASS; 2188 case XDP_REDIRECT: { 2189 int err; 2190 2191 err = xdp_do_redirect(pp->dev, xdp, prog); 2192 if (unlikely(err)) { 2193 mvneta_xdp_put_buff(pp, rxq, xdp, sync, true); 2194 ret = MVNETA_XDP_DROPPED; 2195 } else { 2196 ret = MVNETA_XDP_REDIR; 2197 stats->xdp_redirect++; 2198 } 2199 break; 2200 } 2201 case XDP_TX: 2202 ret = mvneta_xdp_xmit_back(pp, xdp); 2203 if (ret != MVNETA_XDP_TX) 2204 mvneta_xdp_put_buff(pp, rxq, xdp, sync, true); 2205 break; 2206 default: 2207 bpf_warn_invalid_xdp_action(act); 2208 fallthrough; 2209 case XDP_ABORTED: 2210 trace_xdp_exception(pp->dev, prog, act); 2211 fallthrough; 2212 case XDP_DROP: 2213 mvneta_xdp_put_buff(pp, rxq, xdp, sync, true); 2214 ret = MVNETA_XDP_DROPPED; 2215 stats->xdp_drop++; 2216 break; 2217 } 2218 2219 stats->rx_bytes += frame_sz + xdp->data_end - xdp->data - data_len; 2220 stats->rx_packets++; 2221 2222 return ret; 2223 } 2224 2225 static void 2226 mvneta_swbm_rx_frame(struct mvneta_port *pp, 2227 struct mvneta_rx_desc *rx_desc, 2228 struct mvneta_rx_queue *rxq, 2229 struct xdp_buff *xdp, int *size, 2230 struct page *page, 2231 struct mvneta_stats *stats) 2232 { 2233 unsigned char *data = page_address(page); 2234 int data_len = -MVNETA_MH_SIZE, len; 2235 struct net_device *dev = pp->dev; 2236 enum dma_data_direction dma_dir; 2237 struct skb_shared_info *sinfo; 2238 2239 if (MVNETA_SKB_SIZE(rx_desc->data_size) > PAGE_SIZE) { 2240 len = MVNETA_MAX_RX_BUF_SIZE; 2241 data_len += len; 2242 } else { 2243 len = rx_desc->data_size; 2244 data_len += len - ETH_FCS_LEN; 2245 } 2246 2247 dma_dir = page_pool_get_dma_dir(rxq->page_pool); 2248 dma_sync_single_for_cpu(dev->dev.parent, 2249 rx_desc->buf_phys_addr, 2250 len, dma_dir); 2251 2252 /* Prefetch header */ 2253 prefetch(data); 2254 2255 xdp->data_hard_start = data; 2256 xdp->data = data + pp->rx_offset_correction + MVNETA_MH_SIZE; 2257 xdp->data_end = xdp->data + data_len; 2258 xdp_set_data_meta_invalid(xdp); 2259 2260 sinfo = xdp_get_shared_info_from_buff(xdp); 2261 sinfo->nr_frags = 0; 2262 2263 *size = rx_desc->data_size - len; 2264 rx_desc->buf_phys_addr = 0; 2265 } 2266 2267 static void 2268 mvneta_swbm_add_rx_fragment(struct mvneta_port *pp, 2269 struct mvneta_rx_desc *rx_desc, 2270 struct mvneta_rx_queue *rxq, 2271 struct xdp_buff *xdp, int *size, 2272 struct page *page) 2273 { 2274 struct skb_shared_info *sinfo = xdp_get_shared_info_from_buff(xdp); 2275 struct net_device *dev = pp->dev; 2276 enum dma_data_direction dma_dir; 2277 int data_len, len; 2278 2279 if (*size > MVNETA_MAX_RX_BUF_SIZE) { 2280 len = MVNETA_MAX_RX_BUF_SIZE; 2281 data_len = len; 2282 } else { 2283 len = *size; 2284 data_len = len - ETH_FCS_LEN; 2285 } 2286 dma_dir = page_pool_get_dma_dir(rxq->page_pool); 2287 dma_sync_single_for_cpu(dev->dev.parent, 2288 rx_desc->buf_phys_addr, 2289 len, dma_dir); 2290 2291 if (data_len > 0 && sinfo->nr_frags < MAX_SKB_FRAGS) { 2292 skb_frag_t *frag = &sinfo->frags[sinfo->nr_frags]; 2293 2294 skb_frag_off_set(frag, pp->rx_offset_correction); 2295 skb_frag_size_set(frag, data_len); 2296 __skb_frag_set_page(frag, page); 2297 sinfo->nr_frags++; 2298 2299 rx_desc->buf_phys_addr = 0; 2300 } 2301 *size -= len; 2302 } 2303 2304 static struct sk_buff * 2305 mvneta_swbm_build_skb(struct mvneta_port *pp, struct mvneta_rx_queue *rxq, 2306 struct xdp_buff *xdp, u32 desc_status) 2307 { 2308 struct skb_shared_info *sinfo = xdp_get_shared_info_from_buff(xdp); 2309 int i, num_frags = sinfo->nr_frags; 2310 skb_frag_t frags[MAX_SKB_FRAGS]; 2311 struct sk_buff *skb; 2312 2313 memcpy(frags, sinfo->frags, sizeof(skb_frag_t) * num_frags); 2314 2315 skb = build_skb(xdp->data_hard_start, PAGE_SIZE); 2316 if (!skb) 2317 return ERR_PTR(-ENOMEM); 2318 2319 page_pool_release_page(rxq->page_pool, virt_to_page(xdp->data)); 2320 2321 skb_reserve(skb, xdp->data - xdp->data_hard_start); 2322 skb_put(skb, xdp->data_end - xdp->data); 2323 mvneta_rx_csum(pp, desc_status, skb); 2324 2325 for (i = 0; i < num_frags; i++) { 2326 struct page *page = skb_frag_page(&frags[i]); 2327 2328 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, 2329 page, skb_frag_off(&frags[i]), 2330 skb_frag_size(&frags[i]), PAGE_SIZE); 2331 page_pool_release_page(rxq->page_pool, page); 2332 } 2333 2334 return skb; 2335 } 2336 2337 /* Main rx processing when using software buffer management */ 2338 static int mvneta_rx_swbm(struct napi_struct *napi, 2339 struct mvneta_port *pp, int budget, 2340 struct mvneta_rx_queue *rxq) 2341 { 2342 int rx_proc = 0, rx_todo, refill, size = 0; 2343 struct net_device *dev = pp->dev; 2344 struct xdp_buff xdp_buf = { 2345 .frame_sz = PAGE_SIZE, 2346 .rxq = &rxq->xdp_rxq, 2347 }; 2348 struct mvneta_stats ps = {}; 2349 struct bpf_prog *xdp_prog; 2350 u32 desc_status, frame_sz; 2351 2352 /* Get number of received packets */ 2353 rx_todo = mvneta_rxq_busy_desc_num_get(pp, rxq); 2354 2355 rcu_read_lock(); 2356 xdp_prog = READ_ONCE(pp->xdp_prog); 2357 2358 /* Fairness NAPI loop */ 2359 while (rx_proc < budget && rx_proc < rx_todo) { 2360 struct mvneta_rx_desc *rx_desc = mvneta_rxq_next_desc_get(rxq); 2361 u32 rx_status, index; 2362 struct sk_buff *skb; 2363 struct page *page; 2364 2365 index = rx_desc - rxq->descs; 2366 page = (struct page *)rxq->buf_virt_addr[index]; 2367 2368 rx_status = rx_desc->status; 2369 rx_proc++; 2370 rxq->refill_num++; 2371 2372 if (rx_status & MVNETA_RXD_FIRST_DESC) { 2373 /* Check errors only for FIRST descriptor */ 2374 if (rx_status & MVNETA_RXD_ERR_SUMMARY) { 2375 mvneta_rx_error(pp, rx_desc); 2376 goto next; 2377 } 2378 2379 size = rx_desc->data_size; 2380 frame_sz = size - ETH_FCS_LEN; 2381 desc_status = rx_desc->status; 2382 2383 mvneta_swbm_rx_frame(pp, rx_desc, rxq, &xdp_buf, 2384 &size, page, &ps); 2385 } else { 2386 if (unlikely(!xdp_buf.data_hard_start)) 2387 continue; 2388 2389 mvneta_swbm_add_rx_fragment(pp, rx_desc, rxq, &xdp_buf, 2390 &size, page); 2391 } /* Middle or Last descriptor */ 2392 2393 if (!(rx_status & MVNETA_RXD_LAST_DESC)) 2394 /* no last descriptor this time */ 2395 continue; 2396 2397 if (size) { 2398 mvneta_xdp_put_buff(pp, rxq, &xdp_buf, -1, true); 2399 goto next; 2400 } 2401 2402 if (xdp_prog && 2403 mvneta_run_xdp(pp, rxq, xdp_prog, &xdp_buf, frame_sz, &ps)) 2404 goto next; 2405 2406 skb = mvneta_swbm_build_skb(pp, rxq, &xdp_buf, desc_status); 2407 if (IS_ERR(skb)) { 2408 struct mvneta_pcpu_stats *stats = this_cpu_ptr(pp->stats); 2409 2410 mvneta_xdp_put_buff(pp, rxq, &xdp_buf, -1, true); 2411 2412 u64_stats_update_begin(&stats->syncp); 2413 stats->es.skb_alloc_error++; 2414 stats->rx_dropped++; 2415 u64_stats_update_end(&stats->syncp); 2416 2417 goto next; 2418 } 2419 2420 ps.rx_bytes += skb->len; 2421 ps.rx_packets++; 2422 2423 skb->protocol = eth_type_trans(skb, dev); 2424 napi_gro_receive(napi, skb); 2425 next: 2426 xdp_buf.data_hard_start = NULL; 2427 } 2428 rcu_read_unlock(); 2429 2430 if (xdp_buf.data_hard_start) 2431 mvneta_xdp_put_buff(pp, rxq, &xdp_buf, -1, true); 2432 2433 if (ps.xdp_redirect) 2434 xdp_do_flush_map(); 2435 2436 if (ps.rx_packets) 2437 mvneta_update_stats(pp, &ps); 2438 2439 /* return some buffers to hardware queue, one at a time is too slow */ 2440 refill = mvneta_rx_refill_queue(pp, rxq); 2441 2442 /* Update rxq management counters */ 2443 mvneta_rxq_desc_num_update(pp, rxq, rx_proc, refill); 2444 2445 return ps.rx_packets; 2446 } 2447 2448 /* Main rx processing when using hardware buffer management */ 2449 static int mvneta_rx_hwbm(struct napi_struct *napi, 2450 struct mvneta_port *pp, int rx_todo, 2451 struct mvneta_rx_queue *rxq) 2452 { 2453 struct net_device *dev = pp->dev; 2454 int rx_done; 2455 u32 rcvd_pkts = 0; 2456 u32 rcvd_bytes = 0; 2457 2458 /* Get number of received packets */ 2459 rx_done = mvneta_rxq_busy_desc_num_get(pp, rxq); 2460 2461 if (rx_todo > rx_done) 2462 rx_todo = rx_done; 2463 2464 rx_done = 0; 2465 2466 /* Fairness NAPI loop */ 2467 while (rx_done < rx_todo) { 2468 struct mvneta_rx_desc *rx_desc = mvneta_rxq_next_desc_get(rxq); 2469 struct mvneta_bm_pool *bm_pool = NULL; 2470 struct sk_buff *skb; 2471 unsigned char *data; 2472 dma_addr_t phys_addr; 2473 u32 rx_status, frag_size; 2474 int rx_bytes, err; 2475 u8 pool_id; 2476 2477 rx_done++; 2478 rx_status = rx_desc->status; 2479 rx_bytes = rx_desc->data_size - (ETH_FCS_LEN + MVNETA_MH_SIZE); 2480 data = (u8 *)(uintptr_t)rx_desc->buf_cookie; 2481 phys_addr = rx_desc->buf_phys_addr; 2482 pool_id = MVNETA_RX_GET_BM_POOL_ID(rx_desc); 2483 bm_pool = &pp->bm_priv->bm_pools[pool_id]; 2484 2485 if (!mvneta_rxq_desc_is_first_last(rx_status) || 2486 (rx_status & MVNETA_RXD_ERR_SUMMARY)) { 2487 err_drop_frame_ret_pool: 2488 /* Return the buffer to the pool */ 2489 mvneta_bm_pool_put_bp(pp->bm_priv, bm_pool, 2490 rx_desc->buf_phys_addr); 2491 err_drop_frame: 2492 mvneta_rx_error(pp, rx_desc); 2493 /* leave the descriptor untouched */ 2494 continue; 2495 } 2496 2497 if (rx_bytes <= rx_copybreak) { 2498 /* better copy a small frame and not unmap the DMA region */ 2499 skb = netdev_alloc_skb_ip_align(dev, rx_bytes); 2500 if (unlikely(!skb)) 2501 goto err_drop_frame_ret_pool; 2502 2503 dma_sync_single_range_for_cpu(&pp->bm_priv->pdev->dev, 2504 rx_desc->buf_phys_addr, 2505 MVNETA_MH_SIZE + NET_SKB_PAD, 2506 rx_bytes, 2507 DMA_FROM_DEVICE); 2508 skb_put_data(skb, data + MVNETA_MH_SIZE + NET_SKB_PAD, 2509 rx_bytes); 2510 2511 skb->protocol = eth_type_trans(skb, dev); 2512 mvneta_rx_csum(pp, rx_status, skb); 2513 napi_gro_receive(napi, skb); 2514 2515 rcvd_pkts++; 2516 rcvd_bytes += rx_bytes; 2517 2518 /* Return the buffer to the pool */ 2519 mvneta_bm_pool_put_bp(pp->bm_priv, bm_pool, 2520 rx_desc->buf_phys_addr); 2521 2522 /* leave the descriptor and buffer untouched */ 2523 continue; 2524 } 2525 2526 /* Refill processing */ 2527 err = hwbm_pool_refill(&bm_pool->hwbm_pool, GFP_ATOMIC); 2528 if (err) { 2529 struct mvneta_pcpu_stats *stats; 2530 2531 netdev_err(dev, "Linux processing - Can't refill\n"); 2532 2533 stats = this_cpu_ptr(pp->stats); 2534 u64_stats_update_begin(&stats->syncp); 2535 stats->es.refill_error++; 2536 u64_stats_update_end(&stats->syncp); 2537 2538 goto err_drop_frame_ret_pool; 2539 } 2540 2541 frag_size = bm_pool->hwbm_pool.frag_size; 2542 2543 skb = build_skb(data, frag_size > PAGE_SIZE ? 0 : frag_size); 2544 2545 /* After refill old buffer has to be unmapped regardless 2546 * the skb is successfully built or not. 2547 */ 2548 dma_unmap_single(&pp->bm_priv->pdev->dev, phys_addr, 2549 bm_pool->buf_size, DMA_FROM_DEVICE); 2550 if (!skb) 2551 goto err_drop_frame; 2552 2553 rcvd_pkts++; 2554 rcvd_bytes += rx_bytes; 2555 2556 /* Linux processing */ 2557 skb_reserve(skb, MVNETA_MH_SIZE + NET_SKB_PAD); 2558 skb_put(skb, rx_bytes); 2559 2560 skb->protocol = eth_type_trans(skb, dev); 2561 2562 mvneta_rx_csum(pp, rx_status, skb); 2563 2564 napi_gro_receive(napi, skb); 2565 } 2566 2567 if (rcvd_pkts) { 2568 struct mvneta_pcpu_stats *stats = this_cpu_ptr(pp->stats); 2569 2570 u64_stats_update_begin(&stats->syncp); 2571 stats->es.ps.rx_packets += rcvd_pkts; 2572 stats->es.ps.rx_bytes += rcvd_bytes; 2573 u64_stats_update_end(&stats->syncp); 2574 } 2575 2576 /* Update rxq management counters */ 2577 mvneta_rxq_desc_num_update(pp, rxq, rx_done, rx_done); 2578 2579 return rx_done; 2580 } 2581 2582 static inline void 2583 mvneta_tso_put_hdr(struct sk_buff *skb, 2584 struct mvneta_port *pp, struct mvneta_tx_queue *txq) 2585 { 2586 int hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb); 2587 struct mvneta_tx_buf *buf = &txq->buf[txq->txq_put_index]; 2588 struct mvneta_tx_desc *tx_desc; 2589 2590 tx_desc = mvneta_txq_next_desc_get(txq); 2591 tx_desc->data_size = hdr_len; 2592 tx_desc->command = mvneta_skb_tx_csum(pp, skb); 2593 tx_desc->command |= MVNETA_TXD_F_DESC; 2594 tx_desc->buf_phys_addr = txq->tso_hdrs_phys + 2595 txq->txq_put_index * TSO_HEADER_SIZE; 2596 buf->type = MVNETA_TYPE_SKB; 2597 buf->skb = NULL; 2598 2599 mvneta_txq_inc_put(txq); 2600 } 2601 2602 static inline int 2603 mvneta_tso_put_data(struct net_device *dev, struct mvneta_tx_queue *txq, 2604 struct sk_buff *skb, char *data, int size, 2605 bool last_tcp, bool is_last) 2606 { 2607 struct mvneta_tx_buf *buf = &txq->buf[txq->txq_put_index]; 2608 struct mvneta_tx_desc *tx_desc; 2609 2610 tx_desc = mvneta_txq_next_desc_get(txq); 2611 tx_desc->data_size = size; 2612 tx_desc->buf_phys_addr = dma_map_single(dev->dev.parent, data, 2613 size, DMA_TO_DEVICE); 2614 if (unlikely(dma_mapping_error(dev->dev.parent, 2615 tx_desc->buf_phys_addr))) { 2616 mvneta_txq_desc_put(txq); 2617 return -ENOMEM; 2618 } 2619 2620 tx_desc->command = 0; 2621 buf->type = MVNETA_TYPE_SKB; 2622 buf->skb = NULL; 2623 2624 if (last_tcp) { 2625 /* last descriptor in the TCP packet */ 2626 tx_desc->command = MVNETA_TXD_L_DESC; 2627 2628 /* last descriptor in SKB */ 2629 if (is_last) 2630 buf->skb = skb; 2631 } 2632 mvneta_txq_inc_put(txq); 2633 return 0; 2634 } 2635 2636 static int mvneta_tx_tso(struct sk_buff *skb, struct net_device *dev, 2637 struct mvneta_tx_queue *txq) 2638 { 2639 int hdr_len, total_len, data_left; 2640 int desc_count = 0; 2641 struct mvneta_port *pp = netdev_priv(dev); 2642 struct tso_t tso; 2643 int i; 2644 2645 /* Count needed descriptors */ 2646 if ((txq->count + tso_count_descs(skb)) >= txq->size) 2647 return 0; 2648 2649 if (skb_headlen(skb) < (skb_transport_offset(skb) + tcp_hdrlen(skb))) { 2650 pr_info("*** Is this even possible???!?!?\n"); 2651 return 0; 2652 } 2653 2654 /* Initialize the TSO handler, and prepare the first payload */ 2655 hdr_len = tso_start(skb, &tso); 2656 2657 total_len = skb->len - hdr_len; 2658 while (total_len > 0) { 2659 char *hdr; 2660 2661 data_left = min_t(int, skb_shinfo(skb)->gso_size, total_len); 2662 total_len -= data_left; 2663 desc_count++; 2664 2665 /* prepare packet headers: MAC + IP + TCP */ 2666 hdr = txq->tso_hdrs + txq->txq_put_index * TSO_HEADER_SIZE; 2667 tso_build_hdr(skb, hdr, &tso, data_left, total_len == 0); 2668 2669 mvneta_tso_put_hdr(skb, pp, txq); 2670 2671 while (data_left > 0) { 2672 int size; 2673 desc_count++; 2674 2675 size = min_t(int, tso.size, data_left); 2676 2677 if (mvneta_tso_put_data(dev, txq, skb, 2678 tso.data, size, 2679 size == data_left, 2680 total_len == 0)) 2681 goto err_release; 2682 data_left -= size; 2683 2684 tso_build_data(skb, &tso, size); 2685 } 2686 } 2687 2688 return desc_count; 2689 2690 err_release: 2691 /* Release all used data descriptors; header descriptors must not 2692 * be DMA-unmapped. 2693 */ 2694 for (i = desc_count - 1; i >= 0; i--) { 2695 struct mvneta_tx_desc *tx_desc = txq->descs + i; 2696 if (!IS_TSO_HEADER(txq, tx_desc->buf_phys_addr)) 2697 dma_unmap_single(pp->dev->dev.parent, 2698 tx_desc->buf_phys_addr, 2699 tx_desc->data_size, 2700 DMA_TO_DEVICE); 2701 mvneta_txq_desc_put(txq); 2702 } 2703 return 0; 2704 } 2705 2706 /* Handle tx fragmentation processing */ 2707 static int mvneta_tx_frag_process(struct mvneta_port *pp, struct sk_buff *skb, 2708 struct mvneta_tx_queue *txq) 2709 { 2710 struct mvneta_tx_desc *tx_desc; 2711 int i, nr_frags = skb_shinfo(skb)->nr_frags; 2712 2713 for (i = 0; i < nr_frags; i++) { 2714 struct mvneta_tx_buf *buf = &txq->buf[txq->txq_put_index]; 2715 skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 2716 void *addr = skb_frag_address(frag); 2717 2718 tx_desc = mvneta_txq_next_desc_get(txq); 2719 tx_desc->data_size = skb_frag_size(frag); 2720 2721 tx_desc->buf_phys_addr = 2722 dma_map_single(pp->dev->dev.parent, addr, 2723 tx_desc->data_size, DMA_TO_DEVICE); 2724 2725 if (dma_mapping_error(pp->dev->dev.parent, 2726 tx_desc->buf_phys_addr)) { 2727 mvneta_txq_desc_put(txq); 2728 goto error; 2729 } 2730 2731 if (i == nr_frags - 1) { 2732 /* Last descriptor */ 2733 tx_desc->command = MVNETA_TXD_L_DESC | MVNETA_TXD_Z_PAD; 2734 buf->skb = skb; 2735 } else { 2736 /* Descriptor in the middle: Not First, Not Last */ 2737 tx_desc->command = 0; 2738 buf->skb = NULL; 2739 } 2740 buf->type = MVNETA_TYPE_SKB; 2741 mvneta_txq_inc_put(txq); 2742 } 2743 2744 return 0; 2745 2746 error: 2747 /* Release all descriptors that were used to map fragments of 2748 * this packet, as well as the corresponding DMA mappings 2749 */ 2750 for (i = i - 1; i >= 0; i--) { 2751 tx_desc = txq->descs + i; 2752 dma_unmap_single(pp->dev->dev.parent, 2753 tx_desc->buf_phys_addr, 2754 tx_desc->data_size, 2755 DMA_TO_DEVICE); 2756 mvneta_txq_desc_put(txq); 2757 } 2758 2759 return -ENOMEM; 2760 } 2761 2762 /* Main tx processing */ 2763 static netdev_tx_t mvneta_tx(struct sk_buff *skb, struct net_device *dev) 2764 { 2765 struct mvneta_port *pp = netdev_priv(dev); 2766 u16 txq_id = skb_get_queue_mapping(skb); 2767 struct mvneta_tx_queue *txq = &pp->txqs[txq_id]; 2768 struct mvneta_tx_buf *buf = &txq->buf[txq->txq_put_index]; 2769 struct mvneta_tx_desc *tx_desc; 2770 int len = skb->len; 2771 int frags = 0; 2772 u32 tx_cmd; 2773 2774 if (!netif_running(dev)) 2775 goto out; 2776 2777 if (skb_is_gso(skb)) { 2778 frags = mvneta_tx_tso(skb, dev, txq); 2779 goto out; 2780 } 2781 2782 frags = skb_shinfo(skb)->nr_frags + 1; 2783 2784 /* Get a descriptor for the first part of the packet */ 2785 tx_desc = mvneta_txq_next_desc_get(txq); 2786 2787 tx_cmd = mvneta_skb_tx_csum(pp, skb); 2788 2789 tx_desc->data_size = skb_headlen(skb); 2790 2791 tx_desc->buf_phys_addr = dma_map_single(dev->dev.parent, skb->data, 2792 tx_desc->data_size, 2793 DMA_TO_DEVICE); 2794 if (unlikely(dma_mapping_error(dev->dev.parent, 2795 tx_desc->buf_phys_addr))) { 2796 mvneta_txq_desc_put(txq); 2797 frags = 0; 2798 goto out; 2799 } 2800 2801 buf->type = MVNETA_TYPE_SKB; 2802 if (frags == 1) { 2803 /* First and Last descriptor */ 2804 tx_cmd |= MVNETA_TXD_FLZ_DESC; 2805 tx_desc->command = tx_cmd; 2806 buf->skb = skb; 2807 mvneta_txq_inc_put(txq); 2808 } else { 2809 /* First but not Last */ 2810 tx_cmd |= MVNETA_TXD_F_DESC; 2811 buf->skb = NULL; 2812 mvneta_txq_inc_put(txq); 2813 tx_desc->command = tx_cmd; 2814 /* Continue with other skb fragments */ 2815 if (mvneta_tx_frag_process(pp, skb, txq)) { 2816 dma_unmap_single(dev->dev.parent, 2817 tx_desc->buf_phys_addr, 2818 tx_desc->data_size, 2819 DMA_TO_DEVICE); 2820 mvneta_txq_desc_put(txq); 2821 frags = 0; 2822 goto out; 2823 } 2824 } 2825 2826 out: 2827 if (frags > 0) { 2828 struct netdev_queue *nq = netdev_get_tx_queue(dev, txq_id); 2829 struct mvneta_pcpu_stats *stats = this_cpu_ptr(pp->stats); 2830 2831 netdev_tx_sent_queue(nq, len); 2832 2833 txq->count += frags; 2834 if (txq->count >= txq->tx_stop_threshold) 2835 netif_tx_stop_queue(nq); 2836 2837 if (!netdev_xmit_more() || netif_xmit_stopped(nq) || 2838 txq->pending + frags > MVNETA_TXQ_DEC_SENT_MASK) 2839 mvneta_txq_pend_desc_add(pp, txq, frags); 2840 else 2841 txq->pending += frags; 2842 2843 u64_stats_update_begin(&stats->syncp); 2844 stats->es.ps.tx_bytes += len; 2845 stats->es.ps.tx_packets++; 2846 u64_stats_update_end(&stats->syncp); 2847 } else { 2848 dev->stats.tx_dropped++; 2849 dev_kfree_skb_any(skb); 2850 } 2851 2852 return NETDEV_TX_OK; 2853 } 2854 2855 2856 /* Free tx resources, when resetting a port */ 2857 static void mvneta_txq_done_force(struct mvneta_port *pp, 2858 struct mvneta_tx_queue *txq) 2859 2860 { 2861 struct netdev_queue *nq = netdev_get_tx_queue(pp->dev, txq->id); 2862 int tx_done = txq->count; 2863 2864 mvneta_txq_bufs_free(pp, txq, tx_done, nq); 2865 2866 /* reset txq */ 2867 txq->count = 0; 2868 txq->txq_put_index = 0; 2869 txq->txq_get_index = 0; 2870 } 2871 2872 /* Handle tx done - called in softirq context. The <cause_tx_done> argument 2873 * must be a valid cause according to MVNETA_TXQ_INTR_MASK_ALL. 2874 */ 2875 static void mvneta_tx_done_gbe(struct mvneta_port *pp, u32 cause_tx_done) 2876 { 2877 struct mvneta_tx_queue *txq; 2878 struct netdev_queue *nq; 2879 int cpu = smp_processor_id(); 2880 2881 while (cause_tx_done) { 2882 txq = mvneta_tx_done_policy(pp, cause_tx_done); 2883 2884 nq = netdev_get_tx_queue(pp->dev, txq->id); 2885 __netif_tx_lock(nq, cpu); 2886 2887 if (txq->count) 2888 mvneta_txq_done(pp, txq); 2889 2890 __netif_tx_unlock(nq); 2891 cause_tx_done &= ~((1 << txq->id)); 2892 } 2893 } 2894 2895 /* Compute crc8 of the specified address, using a unique algorithm , 2896 * according to hw spec, different than generic crc8 algorithm 2897 */ 2898 static int mvneta_addr_crc(unsigned char *addr) 2899 { 2900 int crc = 0; 2901 int i; 2902 2903 for (i = 0; i < ETH_ALEN; i++) { 2904 int j; 2905 2906 crc = (crc ^ addr[i]) << 8; 2907 for (j = 7; j >= 0; j--) { 2908 if (crc & (0x100 << j)) 2909 crc ^= 0x107 << j; 2910 } 2911 } 2912 2913 return crc; 2914 } 2915 2916 /* This method controls the net device special MAC multicast support. 2917 * The Special Multicast Table for MAC addresses supports MAC of the form 2918 * 0x01-00-5E-00-00-XX (where XX is between 0x00 and 0xFF). 2919 * The MAC DA[7:0] bits are used as a pointer to the Special Multicast 2920 * Table entries in the DA-Filter table. This method set the Special 2921 * Multicast Table appropriate entry. 2922 */ 2923 static void mvneta_set_special_mcast_addr(struct mvneta_port *pp, 2924 unsigned char last_byte, 2925 int queue) 2926 { 2927 unsigned int smc_table_reg; 2928 unsigned int tbl_offset; 2929 unsigned int reg_offset; 2930 2931 /* Register offset from SMC table base */ 2932 tbl_offset = (last_byte / 4); 2933 /* Entry offset within the above reg */ 2934 reg_offset = last_byte % 4; 2935 2936 smc_table_reg = mvreg_read(pp, (MVNETA_DA_FILT_SPEC_MCAST 2937 + tbl_offset * 4)); 2938 2939 if (queue == -1) 2940 smc_table_reg &= ~(0xff << (8 * reg_offset)); 2941 else { 2942 smc_table_reg &= ~(0xff << (8 * reg_offset)); 2943 smc_table_reg |= ((0x01 | (queue << 1)) << (8 * reg_offset)); 2944 } 2945 2946 mvreg_write(pp, MVNETA_DA_FILT_SPEC_MCAST + tbl_offset * 4, 2947 smc_table_reg); 2948 } 2949 2950 /* This method controls the network device Other MAC multicast support. 2951 * The Other Multicast Table is used for multicast of another type. 2952 * A CRC-8 is used as an index to the Other Multicast Table entries 2953 * in the DA-Filter table. 2954 * The method gets the CRC-8 value from the calling routine and 2955 * sets the Other Multicast Table appropriate entry according to the 2956 * specified CRC-8 . 2957 */ 2958 static void mvneta_set_other_mcast_addr(struct mvneta_port *pp, 2959 unsigned char crc8, 2960 int queue) 2961 { 2962 unsigned int omc_table_reg; 2963 unsigned int tbl_offset; 2964 unsigned int reg_offset; 2965 2966 tbl_offset = (crc8 / 4) * 4; /* Register offset from OMC table base */ 2967 reg_offset = crc8 % 4; /* Entry offset within the above reg */ 2968 2969 omc_table_reg = mvreg_read(pp, MVNETA_DA_FILT_OTH_MCAST + tbl_offset); 2970 2971 if (queue == -1) { 2972 /* Clear accepts frame bit at specified Other DA table entry */ 2973 omc_table_reg &= ~(0xff << (8 * reg_offset)); 2974 } else { 2975 omc_table_reg &= ~(0xff << (8 * reg_offset)); 2976 omc_table_reg |= ((0x01 | (queue << 1)) << (8 * reg_offset)); 2977 } 2978 2979 mvreg_write(pp, MVNETA_DA_FILT_OTH_MCAST + tbl_offset, omc_table_reg); 2980 } 2981 2982 /* The network device supports multicast using two tables: 2983 * 1) Special Multicast Table for MAC addresses of the form 2984 * 0x01-00-5E-00-00-XX (where XX is between 0x00 and 0xFF). 2985 * The MAC DA[7:0] bits are used as a pointer to the Special Multicast 2986 * Table entries in the DA-Filter table. 2987 * 2) Other Multicast Table for multicast of another type. A CRC-8 value 2988 * is used as an index to the Other Multicast Table entries in the 2989 * DA-Filter table. 2990 */ 2991 static int mvneta_mcast_addr_set(struct mvneta_port *pp, unsigned char *p_addr, 2992 int queue) 2993 { 2994 unsigned char crc_result = 0; 2995 2996 if (memcmp(p_addr, "\x01\x00\x5e\x00\x00", 5) == 0) { 2997 mvneta_set_special_mcast_addr(pp, p_addr[5], queue); 2998 return 0; 2999 } 3000 3001 crc_result = mvneta_addr_crc(p_addr); 3002 if (queue == -1) { 3003 if (pp->mcast_count[crc_result] == 0) { 3004 netdev_info(pp->dev, "No valid Mcast for crc8=0x%02x\n", 3005 crc_result); 3006 return -EINVAL; 3007 } 3008 3009 pp->mcast_count[crc_result]--; 3010 if (pp->mcast_count[crc_result] != 0) { 3011 netdev_info(pp->dev, 3012 "After delete there are %d valid Mcast for crc8=0x%02x\n", 3013 pp->mcast_count[crc_result], crc_result); 3014 return -EINVAL; 3015 } 3016 } else 3017 pp->mcast_count[crc_result]++; 3018 3019 mvneta_set_other_mcast_addr(pp, crc_result, queue); 3020 3021 return 0; 3022 } 3023 3024 /* Configure Fitering mode of Ethernet port */ 3025 static void mvneta_rx_unicast_promisc_set(struct mvneta_port *pp, 3026 int is_promisc) 3027 { 3028 u32 port_cfg_reg, val; 3029 3030 port_cfg_reg = mvreg_read(pp, MVNETA_PORT_CONFIG); 3031 3032 val = mvreg_read(pp, MVNETA_TYPE_PRIO); 3033 3034 /* Set / Clear UPM bit in port configuration register */ 3035 if (is_promisc) { 3036 /* Accept all Unicast addresses */ 3037 port_cfg_reg |= MVNETA_UNI_PROMISC_MODE; 3038 val |= MVNETA_FORCE_UNI; 3039 mvreg_write(pp, MVNETA_MAC_ADDR_LOW, 0xffff); 3040 mvreg_write(pp, MVNETA_MAC_ADDR_HIGH, 0xffffffff); 3041 } else { 3042 /* Reject all Unicast addresses */ 3043 port_cfg_reg &= ~MVNETA_UNI_PROMISC_MODE; 3044 val &= ~MVNETA_FORCE_UNI; 3045 } 3046 3047 mvreg_write(pp, MVNETA_PORT_CONFIG, port_cfg_reg); 3048 mvreg_write(pp, MVNETA_TYPE_PRIO, val); 3049 } 3050 3051 /* register unicast and multicast addresses */ 3052 static void mvneta_set_rx_mode(struct net_device *dev) 3053 { 3054 struct mvneta_port *pp = netdev_priv(dev); 3055 struct netdev_hw_addr *ha; 3056 3057 if (dev->flags & IFF_PROMISC) { 3058 /* Accept all: Multicast + Unicast */ 3059 mvneta_rx_unicast_promisc_set(pp, 1); 3060 mvneta_set_ucast_table(pp, pp->rxq_def); 3061 mvneta_set_special_mcast_table(pp, pp->rxq_def); 3062 mvneta_set_other_mcast_table(pp, pp->rxq_def); 3063 } else { 3064 /* Accept single Unicast */ 3065 mvneta_rx_unicast_promisc_set(pp, 0); 3066 mvneta_set_ucast_table(pp, -1); 3067 mvneta_mac_addr_set(pp, dev->dev_addr, pp->rxq_def); 3068 3069 if (dev->flags & IFF_ALLMULTI) { 3070 /* Accept all multicast */ 3071 mvneta_set_special_mcast_table(pp, pp->rxq_def); 3072 mvneta_set_other_mcast_table(pp, pp->rxq_def); 3073 } else { 3074 /* Accept only initialized multicast */ 3075 mvneta_set_special_mcast_table(pp, -1); 3076 mvneta_set_other_mcast_table(pp, -1); 3077 3078 if (!netdev_mc_empty(dev)) { 3079 netdev_for_each_mc_addr(ha, dev) { 3080 mvneta_mcast_addr_set(pp, ha->addr, 3081 pp->rxq_def); 3082 } 3083 } 3084 } 3085 } 3086 } 3087 3088 /* Interrupt handling - the callback for request_irq() */ 3089 static irqreturn_t mvneta_isr(int irq, void *dev_id) 3090 { 3091 struct mvneta_port *pp = (struct mvneta_port *)dev_id; 3092 3093 mvreg_write(pp, MVNETA_INTR_NEW_MASK, 0); 3094 napi_schedule(&pp->napi); 3095 3096 return IRQ_HANDLED; 3097 } 3098 3099 /* Interrupt handling - the callback for request_percpu_irq() */ 3100 static irqreturn_t mvneta_percpu_isr(int irq, void *dev_id) 3101 { 3102 struct mvneta_pcpu_port *port = (struct mvneta_pcpu_port *)dev_id; 3103 3104 disable_percpu_irq(port->pp->dev->irq); 3105 napi_schedule(&port->napi); 3106 3107 return IRQ_HANDLED; 3108 } 3109 3110 static void mvneta_link_change(struct mvneta_port *pp) 3111 { 3112 u32 gmac_stat = mvreg_read(pp, MVNETA_GMAC_STATUS); 3113 3114 phylink_mac_change(pp->phylink, !!(gmac_stat & MVNETA_GMAC_LINK_UP)); 3115 } 3116 3117 /* NAPI handler 3118 * Bits 0 - 7 of the causeRxTx register indicate that are transmitted 3119 * packets on the corresponding TXQ (Bit 0 is for TX queue 1). 3120 * Bits 8 -15 of the cause Rx Tx register indicate that are received 3121 * packets on the corresponding RXQ (Bit 8 is for RX queue 0). 3122 * Each CPU has its own causeRxTx register 3123 */ 3124 static int mvneta_poll(struct napi_struct *napi, int budget) 3125 { 3126 int rx_done = 0; 3127 u32 cause_rx_tx; 3128 int rx_queue; 3129 struct mvneta_port *pp = netdev_priv(napi->dev); 3130 struct mvneta_pcpu_port *port = this_cpu_ptr(pp->ports); 3131 3132 if (!netif_running(pp->dev)) { 3133 napi_complete(napi); 3134 return rx_done; 3135 } 3136 3137 /* Read cause register */ 3138 cause_rx_tx = mvreg_read(pp, MVNETA_INTR_NEW_CAUSE); 3139 if (cause_rx_tx & MVNETA_MISCINTR_INTR_MASK) { 3140 u32 cause_misc = mvreg_read(pp, MVNETA_INTR_MISC_CAUSE); 3141 3142 mvreg_write(pp, MVNETA_INTR_MISC_CAUSE, 0); 3143 3144 if (cause_misc & (MVNETA_CAUSE_PHY_STATUS_CHANGE | 3145 MVNETA_CAUSE_LINK_CHANGE)) 3146 mvneta_link_change(pp); 3147 } 3148 3149 /* Release Tx descriptors */ 3150 if (cause_rx_tx & MVNETA_TX_INTR_MASK_ALL) { 3151 mvneta_tx_done_gbe(pp, (cause_rx_tx & MVNETA_TX_INTR_MASK_ALL)); 3152 cause_rx_tx &= ~MVNETA_TX_INTR_MASK_ALL; 3153 } 3154 3155 /* For the case where the last mvneta_poll did not process all 3156 * RX packets 3157 */ 3158 cause_rx_tx |= pp->neta_armada3700 ? pp->cause_rx_tx : 3159 port->cause_rx_tx; 3160 3161 rx_queue = fls(((cause_rx_tx >> 8) & 0xff)); 3162 if (rx_queue) { 3163 rx_queue = rx_queue - 1; 3164 if (pp->bm_priv) 3165 rx_done = mvneta_rx_hwbm(napi, pp, budget, 3166 &pp->rxqs[rx_queue]); 3167 else 3168 rx_done = mvneta_rx_swbm(napi, pp, budget, 3169 &pp->rxqs[rx_queue]); 3170 } 3171 3172 if (rx_done < budget) { 3173 cause_rx_tx = 0; 3174 napi_complete_done(napi, rx_done); 3175 3176 if (pp->neta_armada3700) { 3177 unsigned long flags; 3178 3179 local_irq_save(flags); 3180 mvreg_write(pp, MVNETA_INTR_NEW_MASK, 3181 MVNETA_RX_INTR_MASK(rxq_number) | 3182 MVNETA_TX_INTR_MASK(txq_number) | 3183 MVNETA_MISCINTR_INTR_MASK); 3184 local_irq_restore(flags); 3185 } else { 3186 enable_percpu_irq(pp->dev->irq, 0); 3187 } 3188 } 3189 3190 if (pp->neta_armada3700) 3191 pp->cause_rx_tx = cause_rx_tx; 3192 else 3193 port->cause_rx_tx = cause_rx_tx; 3194 3195 return rx_done; 3196 } 3197 3198 static int mvneta_create_page_pool(struct mvneta_port *pp, 3199 struct mvneta_rx_queue *rxq, int size) 3200 { 3201 struct bpf_prog *xdp_prog = READ_ONCE(pp->xdp_prog); 3202 struct page_pool_params pp_params = { 3203 .order = 0, 3204 .flags = PP_FLAG_DMA_MAP | PP_FLAG_DMA_SYNC_DEV, 3205 .pool_size = size, 3206 .nid = NUMA_NO_NODE, 3207 .dev = pp->dev->dev.parent, 3208 .dma_dir = xdp_prog ? DMA_BIDIRECTIONAL : DMA_FROM_DEVICE, 3209 .offset = pp->rx_offset_correction, 3210 .max_len = MVNETA_MAX_RX_BUF_SIZE, 3211 }; 3212 int err; 3213 3214 rxq->page_pool = page_pool_create(&pp_params); 3215 if (IS_ERR(rxq->page_pool)) { 3216 err = PTR_ERR(rxq->page_pool); 3217 rxq->page_pool = NULL; 3218 return err; 3219 } 3220 3221 err = xdp_rxq_info_reg(&rxq->xdp_rxq, pp->dev, rxq->id); 3222 if (err < 0) 3223 goto err_free_pp; 3224 3225 err = xdp_rxq_info_reg_mem_model(&rxq->xdp_rxq, MEM_TYPE_PAGE_POOL, 3226 rxq->page_pool); 3227 if (err) 3228 goto err_unregister_rxq; 3229 3230 return 0; 3231 3232 err_unregister_rxq: 3233 xdp_rxq_info_unreg(&rxq->xdp_rxq); 3234 err_free_pp: 3235 page_pool_destroy(rxq->page_pool); 3236 rxq->page_pool = NULL; 3237 return err; 3238 } 3239 3240 /* Handle rxq fill: allocates rxq skbs; called when initializing a port */ 3241 static int mvneta_rxq_fill(struct mvneta_port *pp, struct mvneta_rx_queue *rxq, 3242 int num) 3243 { 3244 int i, err; 3245 3246 err = mvneta_create_page_pool(pp, rxq, num); 3247 if (err < 0) 3248 return err; 3249 3250 for (i = 0; i < num; i++) { 3251 memset(rxq->descs + i, 0, sizeof(struct mvneta_rx_desc)); 3252 if (mvneta_rx_refill(pp, rxq->descs + i, rxq, 3253 GFP_KERNEL) != 0) { 3254 netdev_err(pp->dev, 3255 "%s:rxq %d, %d of %d buffs filled\n", 3256 __func__, rxq->id, i, num); 3257 break; 3258 } 3259 } 3260 3261 /* Add this number of RX descriptors as non occupied (ready to 3262 * get packets) 3263 */ 3264 mvneta_rxq_non_occup_desc_add(pp, rxq, i); 3265 3266 return i; 3267 } 3268 3269 /* Free all packets pending transmit from all TXQs and reset TX port */ 3270 static void mvneta_tx_reset(struct mvneta_port *pp) 3271 { 3272 int queue; 3273 3274 /* free the skb's in the tx ring */ 3275 for (queue = 0; queue < txq_number; queue++) 3276 mvneta_txq_done_force(pp, &pp->txqs[queue]); 3277 3278 mvreg_write(pp, MVNETA_PORT_TX_RESET, MVNETA_PORT_TX_DMA_RESET); 3279 mvreg_write(pp, MVNETA_PORT_TX_RESET, 0); 3280 } 3281 3282 static void mvneta_rx_reset(struct mvneta_port *pp) 3283 { 3284 mvreg_write(pp, MVNETA_PORT_RX_RESET, MVNETA_PORT_RX_DMA_RESET); 3285 mvreg_write(pp, MVNETA_PORT_RX_RESET, 0); 3286 } 3287 3288 /* Rx/Tx queue initialization/cleanup methods */ 3289 3290 static int mvneta_rxq_sw_init(struct mvneta_port *pp, 3291 struct mvneta_rx_queue *rxq) 3292 { 3293 rxq->size = pp->rx_ring_size; 3294 3295 /* Allocate memory for RX descriptors */ 3296 rxq->descs = dma_alloc_coherent(pp->dev->dev.parent, 3297 rxq->size * MVNETA_DESC_ALIGNED_SIZE, 3298 &rxq->descs_phys, GFP_KERNEL); 3299 if (!rxq->descs) 3300 return -ENOMEM; 3301 3302 rxq->last_desc = rxq->size - 1; 3303 3304 return 0; 3305 } 3306 3307 static void mvneta_rxq_hw_init(struct mvneta_port *pp, 3308 struct mvneta_rx_queue *rxq) 3309 { 3310 /* Set Rx descriptors queue starting address */ 3311 mvreg_write(pp, MVNETA_RXQ_BASE_ADDR_REG(rxq->id), rxq->descs_phys); 3312 mvreg_write(pp, MVNETA_RXQ_SIZE_REG(rxq->id), rxq->size); 3313 3314 /* Set coalescing pkts and time */ 3315 mvneta_rx_pkts_coal_set(pp, rxq, rxq->pkts_coal); 3316 mvneta_rx_time_coal_set(pp, rxq, rxq->time_coal); 3317 3318 if (!pp->bm_priv) { 3319 /* Set Offset */ 3320 mvneta_rxq_offset_set(pp, rxq, 0); 3321 mvneta_rxq_buf_size_set(pp, rxq, PAGE_SIZE < SZ_64K ? 3322 MVNETA_MAX_RX_BUF_SIZE : 3323 MVNETA_RX_BUF_SIZE(pp->pkt_size)); 3324 mvneta_rxq_bm_disable(pp, rxq); 3325 mvneta_rxq_fill(pp, rxq, rxq->size); 3326 } else { 3327 /* Set Offset */ 3328 mvneta_rxq_offset_set(pp, rxq, 3329 NET_SKB_PAD - pp->rx_offset_correction); 3330 3331 mvneta_rxq_bm_enable(pp, rxq); 3332 /* Fill RXQ with buffers from RX pool */ 3333 mvneta_rxq_long_pool_set(pp, rxq); 3334 mvneta_rxq_short_pool_set(pp, rxq); 3335 mvneta_rxq_non_occup_desc_add(pp, rxq, rxq->size); 3336 } 3337 } 3338 3339 /* Create a specified RX queue */ 3340 static int mvneta_rxq_init(struct mvneta_port *pp, 3341 struct mvneta_rx_queue *rxq) 3342 3343 { 3344 int ret; 3345 3346 ret = mvneta_rxq_sw_init(pp, rxq); 3347 if (ret < 0) 3348 return ret; 3349 3350 mvneta_rxq_hw_init(pp, rxq); 3351 3352 return 0; 3353 } 3354 3355 /* Cleanup Rx queue */ 3356 static void mvneta_rxq_deinit(struct mvneta_port *pp, 3357 struct mvneta_rx_queue *rxq) 3358 { 3359 mvneta_rxq_drop_pkts(pp, rxq); 3360 3361 if (rxq->descs) 3362 dma_free_coherent(pp->dev->dev.parent, 3363 rxq->size * MVNETA_DESC_ALIGNED_SIZE, 3364 rxq->descs, 3365 rxq->descs_phys); 3366 3367 rxq->descs = NULL; 3368 rxq->last_desc = 0; 3369 rxq->next_desc_to_proc = 0; 3370 rxq->descs_phys = 0; 3371 rxq->first_to_refill = 0; 3372 rxq->refill_num = 0; 3373 } 3374 3375 static int mvneta_txq_sw_init(struct mvneta_port *pp, 3376 struct mvneta_tx_queue *txq) 3377 { 3378 int cpu; 3379 3380 txq->size = pp->tx_ring_size; 3381 3382 /* A queue must always have room for at least one skb. 3383 * Therefore, stop the queue when the free entries reaches 3384 * the maximum number of descriptors per skb. 3385 */ 3386 txq->tx_stop_threshold = txq->size - MVNETA_MAX_SKB_DESCS; 3387 txq->tx_wake_threshold = txq->tx_stop_threshold / 2; 3388 3389 /* Allocate memory for TX descriptors */ 3390 txq->descs = dma_alloc_coherent(pp->dev->dev.parent, 3391 txq->size * MVNETA_DESC_ALIGNED_SIZE, 3392 &txq->descs_phys, GFP_KERNEL); 3393 if (!txq->descs) 3394 return -ENOMEM; 3395 3396 txq->last_desc = txq->size - 1; 3397 3398 txq->buf = kmalloc_array(txq->size, sizeof(*txq->buf), GFP_KERNEL); 3399 if (!txq->buf) { 3400 dma_free_coherent(pp->dev->dev.parent, 3401 txq->size * MVNETA_DESC_ALIGNED_SIZE, 3402 txq->descs, txq->descs_phys); 3403 return -ENOMEM; 3404 } 3405 3406 /* Allocate DMA buffers for TSO MAC/IP/TCP headers */ 3407 txq->tso_hdrs = dma_alloc_coherent(pp->dev->dev.parent, 3408 txq->size * TSO_HEADER_SIZE, 3409 &txq->tso_hdrs_phys, GFP_KERNEL); 3410 if (!txq->tso_hdrs) { 3411 kfree(txq->buf); 3412 dma_free_coherent(pp->dev->dev.parent, 3413 txq->size * MVNETA_DESC_ALIGNED_SIZE, 3414 txq->descs, txq->descs_phys); 3415 return -ENOMEM; 3416 } 3417 3418 /* Setup XPS mapping */ 3419 if (txq_number > 1) 3420 cpu = txq->id % num_present_cpus(); 3421 else 3422 cpu = pp->rxq_def % num_present_cpus(); 3423 cpumask_set_cpu(cpu, &txq->affinity_mask); 3424 netif_set_xps_queue(pp->dev, &txq->affinity_mask, txq->id); 3425 3426 return 0; 3427 } 3428 3429 static void mvneta_txq_hw_init(struct mvneta_port *pp, 3430 struct mvneta_tx_queue *txq) 3431 { 3432 /* Set maximum bandwidth for enabled TXQs */ 3433 mvreg_write(pp, MVETH_TXQ_TOKEN_CFG_REG(txq->id), 0x03ffffff); 3434 mvreg_write(pp, MVETH_TXQ_TOKEN_COUNT_REG(txq->id), 0x3fffffff); 3435 3436 /* Set Tx descriptors queue starting address */ 3437 mvreg_write(pp, MVNETA_TXQ_BASE_ADDR_REG(txq->id), txq->descs_phys); 3438 mvreg_write(pp, MVNETA_TXQ_SIZE_REG(txq->id), txq->size); 3439 3440 mvneta_tx_done_pkts_coal_set(pp, txq, txq->done_pkts_coal); 3441 } 3442 3443 /* Create and initialize a tx queue */ 3444 static int mvneta_txq_init(struct mvneta_port *pp, 3445 struct mvneta_tx_queue *txq) 3446 { 3447 int ret; 3448 3449 ret = mvneta_txq_sw_init(pp, txq); 3450 if (ret < 0) 3451 return ret; 3452 3453 mvneta_txq_hw_init(pp, txq); 3454 3455 return 0; 3456 } 3457 3458 /* Free allocated resources when mvneta_txq_init() fails to allocate memory*/ 3459 static void mvneta_txq_sw_deinit(struct mvneta_port *pp, 3460 struct mvneta_tx_queue *txq) 3461 { 3462 struct netdev_queue *nq = netdev_get_tx_queue(pp->dev, txq->id); 3463 3464 kfree(txq->buf); 3465 3466 if (txq->tso_hdrs) 3467 dma_free_coherent(pp->dev->dev.parent, 3468 txq->size * TSO_HEADER_SIZE, 3469 txq->tso_hdrs, txq->tso_hdrs_phys); 3470 if (txq->descs) 3471 dma_free_coherent(pp->dev->dev.parent, 3472 txq->size * MVNETA_DESC_ALIGNED_SIZE, 3473 txq->descs, txq->descs_phys); 3474 3475 netdev_tx_reset_queue(nq); 3476 3477 txq->descs = NULL; 3478 txq->last_desc = 0; 3479 txq->next_desc_to_proc = 0; 3480 txq->descs_phys = 0; 3481 } 3482 3483 static void mvneta_txq_hw_deinit(struct mvneta_port *pp, 3484 struct mvneta_tx_queue *txq) 3485 { 3486 /* Set minimum bandwidth for disabled TXQs */ 3487 mvreg_write(pp, MVETH_TXQ_TOKEN_CFG_REG(txq->id), 0); 3488 mvreg_write(pp, MVETH_TXQ_TOKEN_COUNT_REG(txq->id), 0); 3489 3490 /* Set Tx descriptors queue starting address and size */ 3491 mvreg_write(pp, MVNETA_TXQ_BASE_ADDR_REG(txq->id), 0); 3492 mvreg_write(pp, MVNETA_TXQ_SIZE_REG(txq->id), 0); 3493 } 3494 3495 static void mvneta_txq_deinit(struct mvneta_port *pp, 3496 struct mvneta_tx_queue *txq) 3497 { 3498 mvneta_txq_sw_deinit(pp, txq); 3499 mvneta_txq_hw_deinit(pp, txq); 3500 } 3501 3502 /* Cleanup all Tx queues */ 3503 static void mvneta_cleanup_txqs(struct mvneta_port *pp) 3504 { 3505 int queue; 3506 3507 for (queue = 0; queue < txq_number; queue++) 3508 mvneta_txq_deinit(pp, &pp->txqs[queue]); 3509 } 3510 3511 /* Cleanup all Rx queues */ 3512 static void mvneta_cleanup_rxqs(struct mvneta_port *pp) 3513 { 3514 int queue; 3515 3516 for (queue = 0; queue < rxq_number; queue++) 3517 mvneta_rxq_deinit(pp, &pp->rxqs[queue]); 3518 } 3519 3520 3521 /* Init all Rx queues */ 3522 static int mvneta_setup_rxqs(struct mvneta_port *pp) 3523 { 3524 int queue; 3525 3526 for (queue = 0; queue < rxq_number; queue++) { 3527 int err = mvneta_rxq_init(pp, &pp->rxqs[queue]); 3528 3529 if (err) { 3530 netdev_err(pp->dev, "%s: can't create rxq=%d\n", 3531 __func__, queue); 3532 mvneta_cleanup_rxqs(pp); 3533 return err; 3534 } 3535 } 3536 3537 return 0; 3538 } 3539 3540 /* Init all tx queues */ 3541 static int mvneta_setup_txqs(struct mvneta_port *pp) 3542 { 3543 int queue; 3544 3545 for (queue = 0; queue < txq_number; queue++) { 3546 int err = mvneta_txq_init(pp, &pp->txqs[queue]); 3547 if (err) { 3548 netdev_err(pp->dev, "%s: can't create txq=%d\n", 3549 __func__, queue); 3550 mvneta_cleanup_txqs(pp); 3551 return err; 3552 } 3553 } 3554 3555 return 0; 3556 } 3557 3558 static int mvneta_comphy_init(struct mvneta_port *pp, phy_interface_t interface) 3559 { 3560 int ret; 3561 3562 ret = phy_set_mode_ext(pp->comphy, PHY_MODE_ETHERNET, interface); 3563 if (ret) 3564 return ret; 3565 3566 return phy_power_on(pp->comphy); 3567 } 3568 3569 static int mvneta_config_interface(struct mvneta_port *pp, 3570 phy_interface_t interface) 3571 { 3572 int ret = 0; 3573 3574 if (pp->comphy) { 3575 if (interface == PHY_INTERFACE_MODE_SGMII || 3576 interface == PHY_INTERFACE_MODE_1000BASEX || 3577 interface == PHY_INTERFACE_MODE_2500BASEX) { 3578 ret = mvneta_comphy_init(pp, interface); 3579 } 3580 } else { 3581 switch (interface) { 3582 case PHY_INTERFACE_MODE_QSGMII: 3583 mvreg_write(pp, MVNETA_SERDES_CFG, 3584 MVNETA_QSGMII_SERDES_PROTO); 3585 break; 3586 3587 case PHY_INTERFACE_MODE_SGMII: 3588 case PHY_INTERFACE_MODE_1000BASEX: 3589 mvreg_write(pp, MVNETA_SERDES_CFG, 3590 MVNETA_SGMII_SERDES_PROTO); 3591 break; 3592 3593 case PHY_INTERFACE_MODE_2500BASEX: 3594 mvreg_write(pp, MVNETA_SERDES_CFG, 3595 MVNETA_HSGMII_SERDES_PROTO); 3596 break; 3597 default: 3598 break; 3599 } 3600 } 3601 3602 pp->phy_interface = interface; 3603 3604 return ret; 3605 } 3606 3607 static void mvneta_start_dev(struct mvneta_port *pp) 3608 { 3609 int cpu; 3610 3611 WARN_ON(mvneta_config_interface(pp, pp->phy_interface)); 3612 3613 mvneta_max_rx_size_set(pp, pp->pkt_size); 3614 mvneta_txq_max_tx_size_set(pp, pp->pkt_size); 3615 3616 /* start the Rx/Tx activity */ 3617 mvneta_port_enable(pp); 3618 3619 if (!pp->neta_armada3700) { 3620 /* Enable polling on the port */ 3621 for_each_online_cpu(cpu) { 3622 struct mvneta_pcpu_port *port = 3623 per_cpu_ptr(pp->ports, cpu); 3624 3625 napi_enable(&port->napi); 3626 } 3627 } else { 3628 napi_enable(&pp->napi); 3629 } 3630 3631 /* Unmask interrupts. It has to be done from each CPU */ 3632 on_each_cpu(mvneta_percpu_unmask_interrupt, pp, true); 3633 3634 mvreg_write(pp, MVNETA_INTR_MISC_MASK, 3635 MVNETA_CAUSE_PHY_STATUS_CHANGE | 3636 MVNETA_CAUSE_LINK_CHANGE); 3637 3638 phylink_start(pp->phylink); 3639 3640 /* We may have called phylink_speed_down before */ 3641 phylink_speed_up(pp->phylink); 3642 3643 netif_tx_start_all_queues(pp->dev); 3644 3645 clear_bit(__MVNETA_DOWN, &pp->state); 3646 } 3647 3648 static void mvneta_stop_dev(struct mvneta_port *pp) 3649 { 3650 unsigned int cpu; 3651 3652 set_bit(__MVNETA_DOWN, &pp->state); 3653 3654 if (device_may_wakeup(&pp->dev->dev)) 3655 phylink_speed_down(pp->phylink, false); 3656 3657 phylink_stop(pp->phylink); 3658 3659 if (!pp->neta_armada3700) { 3660 for_each_online_cpu(cpu) { 3661 struct mvneta_pcpu_port *port = 3662 per_cpu_ptr(pp->ports, cpu); 3663 3664 napi_disable(&port->napi); 3665 } 3666 } else { 3667 napi_disable(&pp->napi); 3668 } 3669 3670 netif_carrier_off(pp->dev); 3671 3672 mvneta_port_down(pp); 3673 netif_tx_stop_all_queues(pp->dev); 3674 3675 /* Stop the port activity */ 3676 mvneta_port_disable(pp); 3677 3678 /* Clear all ethernet port interrupts */ 3679 on_each_cpu(mvneta_percpu_clear_intr_cause, pp, true); 3680 3681 /* Mask all ethernet port interrupts */ 3682 on_each_cpu(mvneta_percpu_mask_interrupt, pp, true); 3683 3684 mvneta_tx_reset(pp); 3685 mvneta_rx_reset(pp); 3686 3687 WARN_ON(phy_power_off(pp->comphy)); 3688 } 3689 3690 static void mvneta_percpu_enable(void *arg) 3691 { 3692 struct mvneta_port *pp = arg; 3693 3694 enable_percpu_irq(pp->dev->irq, IRQ_TYPE_NONE); 3695 } 3696 3697 static void mvneta_percpu_disable(void *arg) 3698 { 3699 struct mvneta_port *pp = arg; 3700 3701 disable_percpu_irq(pp->dev->irq); 3702 } 3703 3704 /* Change the device mtu */ 3705 static int mvneta_change_mtu(struct net_device *dev, int mtu) 3706 { 3707 struct mvneta_port *pp = netdev_priv(dev); 3708 int ret; 3709 3710 if (!IS_ALIGNED(MVNETA_RX_PKT_SIZE(mtu), 8)) { 3711 netdev_info(dev, "Illegal MTU value %d, rounding to %d\n", 3712 mtu, ALIGN(MVNETA_RX_PKT_SIZE(mtu), 8)); 3713 mtu = ALIGN(MVNETA_RX_PKT_SIZE(mtu), 8); 3714 } 3715 3716 if (pp->xdp_prog && mtu > MVNETA_MAX_RX_BUF_SIZE) { 3717 netdev_info(dev, "Illegal MTU value %d for XDP mode\n", mtu); 3718 return -EINVAL; 3719 } 3720 3721 dev->mtu = mtu; 3722 3723 if (!netif_running(dev)) { 3724 if (pp->bm_priv) 3725 mvneta_bm_update_mtu(pp, mtu); 3726 3727 netdev_update_features(dev); 3728 return 0; 3729 } 3730 3731 /* The interface is running, so we have to force a 3732 * reallocation of the queues 3733 */ 3734 mvneta_stop_dev(pp); 3735 on_each_cpu(mvneta_percpu_disable, pp, true); 3736 3737 mvneta_cleanup_txqs(pp); 3738 mvneta_cleanup_rxqs(pp); 3739 3740 if (pp->bm_priv) 3741 mvneta_bm_update_mtu(pp, mtu); 3742 3743 pp->pkt_size = MVNETA_RX_PKT_SIZE(dev->mtu); 3744 3745 ret = mvneta_setup_rxqs(pp); 3746 if (ret) { 3747 netdev_err(dev, "unable to setup rxqs after MTU change\n"); 3748 return ret; 3749 } 3750 3751 ret = mvneta_setup_txqs(pp); 3752 if (ret) { 3753 netdev_err(dev, "unable to setup txqs after MTU change\n"); 3754 return ret; 3755 } 3756 3757 on_each_cpu(mvneta_percpu_enable, pp, true); 3758 mvneta_start_dev(pp); 3759 3760 netdev_update_features(dev); 3761 3762 return 0; 3763 } 3764 3765 static netdev_features_t mvneta_fix_features(struct net_device *dev, 3766 netdev_features_t features) 3767 { 3768 struct mvneta_port *pp = netdev_priv(dev); 3769 3770 if (pp->tx_csum_limit && dev->mtu > pp->tx_csum_limit) { 3771 features &= ~(NETIF_F_IP_CSUM | NETIF_F_TSO); 3772 netdev_info(dev, 3773 "Disable IP checksum for MTU greater than %dB\n", 3774 pp->tx_csum_limit); 3775 } 3776 3777 return features; 3778 } 3779 3780 /* Get mac address */ 3781 static void mvneta_get_mac_addr(struct mvneta_port *pp, unsigned char *addr) 3782 { 3783 u32 mac_addr_l, mac_addr_h; 3784 3785 mac_addr_l = mvreg_read(pp, MVNETA_MAC_ADDR_LOW); 3786 mac_addr_h = mvreg_read(pp, MVNETA_MAC_ADDR_HIGH); 3787 addr[0] = (mac_addr_h >> 24) & 0xFF; 3788 addr[1] = (mac_addr_h >> 16) & 0xFF; 3789 addr[2] = (mac_addr_h >> 8) & 0xFF; 3790 addr[3] = mac_addr_h & 0xFF; 3791 addr[4] = (mac_addr_l >> 8) & 0xFF; 3792 addr[5] = mac_addr_l & 0xFF; 3793 } 3794 3795 /* Handle setting mac address */ 3796 static int mvneta_set_mac_addr(struct net_device *dev, void *addr) 3797 { 3798 struct mvneta_port *pp = netdev_priv(dev); 3799 struct sockaddr *sockaddr = addr; 3800 int ret; 3801 3802 ret = eth_prepare_mac_addr_change(dev, addr); 3803 if (ret < 0) 3804 return ret; 3805 /* Remove previous address table entry */ 3806 mvneta_mac_addr_set(pp, dev->dev_addr, -1); 3807 3808 /* Set new addr in hw */ 3809 mvneta_mac_addr_set(pp, sockaddr->sa_data, pp->rxq_def); 3810 3811 eth_commit_mac_addr_change(dev, addr); 3812 return 0; 3813 } 3814 3815 static void mvneta_validate(struct phylink_config *config, 3816 unsigned long *supported, 3817 struct phylink_link_state *state) 3818 { 3819 struct net_device *ndev = to_net_dev(config->dev); 3820 struct mvneta_port *pp = netdev_priv(ndev); 3821 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, }; 3822 3823 /* We only support QSGMII, SGMII, 802.3z and RGMII modes */ 3824 if (state->interface != PHY_INTERFACE_MODE_NA && 3825 state->interface != PHY_INTERFACE_MODE_QSGMII && 3826 state->interface != PHY_INTERFACE_MODE_SGMII && 3827 !phy_interface_mode_is_8023z(state->interface) && 3828 !phy_interface_mode_is_rgmii(state->interface)) { 3829 bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS); 3830 return; 3831 } 3832 3833 /* Allow all the expected bits */ 3834 phylink_set(mask, Autoneg); 3835 phylink_set_port_modes(mask); 3836 3837 /* Asymmetric pause is unsupported */ 3838 phylink_set(mask, Pause); 3839 3840 /* Half-duplex at speeds higher than 100Mbit is unsupported */ 3841 if (pp->comphy || state->interface != PHY_INTERFACE_MODE_2500BASEX) { 3842 phylink_set(mask, 1000baseT_Full); 3843 phylink_set(mask, 1000baseX_Full); 3844 } 3845 if (pp->comphy || state->interface == PHY_INTERFACE_MODE_2500BASEX) { 3846 phylink_set(mask, 2500baseT_Full); 3847 phylink_set(mask, 2500baseX_Full); 3848 } 3849 3850 if (!phy_interface_mode_is_8023z(state->interface)) { 3851 /* 10M and 100M are only supported in non-802.3z mode */ 3852 phylink_set(mask, 10baseT_Half); 3853 phylink_set(mask, 10baseT_Full); 3854 phylink_set(mask, 100baseT_Half); 3855 phylink_set(mask, 100baseT_Full); 3856 } 3857 3858 bitmap_and(supported, supported, mask, 3859 __ETHTOOL_LINK_MODE_MASK_NBITS); 3860 bitmap_and(state->advertising, state->advertising, mask, 3861 __ETHTOOL_LINK_MODE_MASK_NBITS); 3862 3863 /* We can only operate at 2500BaseX or 1000BaseX. If requested 3864 * to advertise both, only report advertising at 2500BaseX. 3865 */ 3866 phylink_helper_basex_speed(state); 3867 } 3868 3869 static void mvneta_mac_pcs_get_state(struct phylink_config *config, 3870 struct phylink_link_state *state) 3871 { 3872 struct net_device *ndev = to_net_dev(config->dev); 3873 struct mvneta_port *pp = netdev_priv(ndev); 3874 u32 gmac_stat; 3875 3876 gmac_stat = mvreg_read(pp, MVNETA_GMAC_STATUS); 3877 3878 if (gmac_stat & MVNETA_GMAC_SPEED_1000) 3879 state->speed = 3880 state->interface == PHY_INTERFACE_MODE_2500BASEX ? 3881 SPEED_2500 : SPEED_1000; 3882 else if (gmac_stat & MVNETA_GMAC_SPEED_100) 3883 state->speed = SPEED_100; 3884 else 3885 state->speed = SPEED_10; 3886 3887 state->an_complete = !!(gmac_stat & MVNETA_GMAC_AN_COMPLETE); 3888 state->link = !!(gmac_stat & MVNETA_GMAC_LINK_UP); 3889 state->duplex = !!(gmac_stat & MVNETA_GMAC_FULL_DUPLEX); 3890 3891 state->pause = 0; 3892 if (gmac_stat & MVNETA_GMAC_RX_FLOW_CTRL_ENABLE) 3893 state->pause |= MLO_PAUSE_RX; 3894 if (gmac_stat & MVNETA_GMAC_TX_FLOW_CTRL_ENABLE) 3895 state->pause |= MLO_PAUSE_TX; 3896 } 3897 3898 static void mvneta_mac_an_restart(struct phylink_config *config) 3899 { 3900 struct net_device *ndev = to_net_dev(config->dev); 3901 struct mvneta_port *pp = netdev_priv(ndev); 3902 u32 gmac_an = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG); 3903 3904 mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, 3905 gmac_an | MVNETA_GMAC_INBAND_RESTART_AN); 3906 mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, 3907 gmac_an & ~MVNETA_GMAC_INBAND_RESTART_AN); 3908 } 3909 3910 static void mvneta_mac_config(struct phylink_config *config, unsigned int mode, 3911 const struct phylink_link_state *state) 3912 { 3913 struct net_device *ndev = to_net_dev(config->dev); 3914 struct mvneta_port *pp = netdev_priv(ndev); 3915 u32 new_ctrl0, gmac_ctrl0 = mvreg_read(pp, MVNETA_GMAC_CTRL_0); 3916 u32 new_ctrl2, gmac_ctrl2 = mvreg_read(pp, MVNETA_GMAC_CTRL_2); 3917 u32 new_ctrl4, gmac_ctrl4 = mvreg_read(pp, MVNETA_GMAC_CTRL_4); 3918 u32 new_clk, gmac_clk = mvreg_read(pp, MVNETA_GMAC_CLOCK_DIVIDER); 3919 u32 new_an, gmac_an = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG); 3920 3921 new_ctrl0 = gmac_ctrl0 & ~MVNETA_GMAC0_PORT_1000BASE_X; 3922 new_ctrl2 = gmac_ctrl2 & ~(MVNETA_GMAC2_INBAND_AN_ENABLE | 3923 MVNETA_GMAC2_PORT_RESET); 3924 new_ctrl4 = gmac_ctrl4 & ~(MVNETA_GMAC4_SHORT_PREAMBLE_ENABLE); 3925 new_clk = gmac_clk & ~MVNETA_GMAC_1MS_CLOCK_ENABLE; 3926 new_an = gmac_an & ~(MVNETA_GMAC_INBAND_AN_ENABLE | 3927 MVNETA_GMAC_INBAND_RESTART_AN | 3928 MVNETA_GMAC_AN_SPEED_EN | 3929 MVNETA_GMAC_ADVERT_SYM_FLOW_CTRL | 3930 MVNETA_GMAC_AN_FLOW_CTRL_EN | 3931 MVNETA_GMAC_AN_DUPLEX_EN); 3932 3933 /* Even though it might look weird, when we're configured in 3934 * SGMII or QSGMII mode, the RGMII bit needs to be set. 3935 */ 3936 new_ctrl2 |= MVNETA_GMAC2_PORT_RGMII; 3937 3938 if (state->interface == PHY_INTERFACE_MODE_QSGMII || 3939 state->interface == PHY_INTERFACE_MODE_SGMII || 3940 phy_interface_mode_is_8023z(state->interface)) 3941 new_ctrl2 |= MVNETA_GMAC2_PCS_ENABLE; 3942 3943 if (phylink_test(state->advertising, Pause)) 3944 new_an |= MVNETA_GMAC_ADVERT_SYM_FLOW_CTRL; 3945 3946 if (!phylink_autoneg_inband(mode)) { 3947 /* Phy or fixed speed - nothing to do, leave the 3948 * configured speed, duplex and flow control as-is. 3949 */ 3950 } else if (state->interface == PHY_INTERFACE_MODE_SGMII) { 3951 /* SGMII mode receives the state from the PHY */ 3952 new_ctrl2 |= MVNETA_GMAC2_INBAND_AN_ENABLE; 3953 new_clk |= MVNETA_GMAC_1MS_CLOCK_ENABLE; 3954 new_an = (new_an & ~(MVNETA_GMAC_FORCE_LINK_DOWN | 3955 MVNETA_GMAC_FORCE_LINK_PASS | 3956 MVNETA_GMAC_CONFIG_MII_SPEED | 3957 MVNETA_GMAC_CONFIG_GMII_SPEED | 3958 MVNETA_GMAC_CONFIG_FULL_DUPLEX)) | 3959 MVNETA_GMAC_INBAND_AN_ENABLE | 3960 MVNETA_GMAC_AN_SPEED_EN | 3961 MVNETA_GMAC_AN_DUPLEX_EN; 3962 } else { 3963 /* 802.3z negotiation - only 1000base-X */ 3964 new_ctrl0 |= MVNETA_GMAC0_PORT_1000BASE_X; 3965 new_clk |= MVNETA_GMAC_1MS_CLOCK_ENABLE; 3966 new_an = (new_an & ~(MVNETA_GMAC_FORCE_LINK_DOWN | 3967 MVNETA_GMAC_FORCE_LINK_PASS | 3968 MVNETA_GMAC_CONFIG_MII_SPEED)) | 3969 MVNETA_GMAC_INBAND_AN_ENABLE | 3970 MVNETA_GMAC_CONFIG_GMII_SPEED | 3971 /* The MAC only supports FD mode */ 3972 MVNETA_GMAC_CONFIG_FULL_DUPLEX; 3973 3974 if (state->pause & MLO_PAUSE_AN && state->an_enabled) 3975 new_an |= MVNETA_GMAC_AN_FLOW_CTRL_EN; 3976 } 3977 3978 /* Armada 370 documentation says we can only change the port mode 3979 * and in-band enable when the link is down, so force it down 3980 * while making these changes. We also do this for GMAC_CTRL2 */ 3981 if ((new_ctrl0 ^ gmac_ctrl0) & MVNETA_GMAC0_PORT_1000BASE_X || 3982 (new_ctrl2 ^ gmac_ctrl2) & MVNETA_GMAC2_INBAND_AN_ENABLE || 3983 (new_an ^ gmac_an) & MVNETA_GMAC_INBAND_AN_ENABLE) { 3984 mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, 3985 (gmac_an & ~MVNETA_GMAC_FORCE_LINK_PASS) | 3986 MVNETA_GMAC_FORCE_LINK_DOWN); 3987 } 3988 3989 3990 /* When at 2.5G, the link partner can send frames with shortened 3991 * preambles. 3992 */ 3993 if (state->interface == PHY_INTERFACE_MODE_2500BASEX) 3994 new_ctrl4 |= MVNETA_GMAC4_SHORT_PREAMBLE_ENABLE; 3995 3996 if (pp->phy_interface != state->interface) { 3997 if (pp->comphy) 3998 WARN_ON(phy_power_off(pp->comphy)); 3999 WARN_ON(mvneta_config_interface(pp, state->interface)); 4000 } 4001 4002 if (new_ctrl0 != gmac_ctrl0) 4003 mvreg_write(pp, MVNETA_GMAC_CTRL_0, new_ctrl0); 4004 if (new_ctrl2 != gmac_ctrl2) 4005 mvreg_write(pp, MVNETA_GMAC_CTRL_2, new_ctrl2); 4006 if (new_ctrl4 != gmac_ctrl4) 4007 mvreg_write(pp, MVNETA_GMAC_CTRL_4, new_ctrl4); 4008 if (new_clk != gmac_clk) 4009 mvreg_write(pp, MVNETA_GMAC_CLOCK_DIVIDER, new_clk); 4010 if (new_an != gmac_an) 4011 mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, new_an); 4012 4013 if (gmac_ctrl2 & MVNETA_GMAC2_PORT_RESET) { 4014 while ((mvreg_read(pp, MVNETA_GMAC_CTRL_2) & 4015 MVNETA_GMAC2_PORT_RESET) != 0) 4016 continue; 4017 } 4018 } 4019 4020 static void mvneta_set_eee(struct mvneta_port *pp, bool enable) 4021 { 4022 u32 lpi_ctl1; 4023 4024 lpi_ctl1 = mvreg_read(pp, MVNETA_LPI_CTRL_1); 4025 if (enable) 4026 lpi_ctl1 |= MVNETA_LPI_REQUEST_ENABLE; 4027 else 4028 lpi_ctl1 &= ~MVNETA_LPI_REQUEST_ENABLE; 4029 mvreg_write(pp, MVNETA_LPI_CTRL_1, lpi_ctl1); 4030 } 4031 4032 static void mvneta_mac_link_down(struct phylink_config *config, 4033 unsigned int mode, phy_interface_t interface) 4034 { 4035 struct net_device *ndev = to_net_dev(config->dev); 4036 struct mvneta_port *pp = netdev_priv(ndev); 4037 u32 val; 4038 4039 mvneta_port_down(pp); 4040 4041 if (!phylink_autoneg_inband(mode)) { 4042 val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG); 4043 val &= ~MVNETA_GMAC_FORCE_LINK_PASS; 4044 val |= MVNETA_GMAC_FORCE_LINK_DOWN; 4045 mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val); 4046 } 4047 4048 pp->eee_active = false; 4049 mvneta_set_eee(pp, false); 4050 } 4051 4052 static void mvneta_mac_link_up(struct phylink_config *config, 4053 struct phy_device *phy, 4054 unsigned int mode, phy_interface_t interface, 4055 int speed, int duplex, 4056 bool tx_pause, bool rx_pause) 4057 { 4058 struct net_device *ndev = to_net_dev(config->dev); 4059 struct mvneta_port *pp = netdev_priv(ndev); 4060 u32 val; 4061 4062 if (!phylink_autoneg_inband(mode)) { 4063 val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG); 4064 val &= ~(MVNETA_GMAC_FORCE_LINK_DOWN | 4065 MVNETA_GMAC_CONFIG_MII_SPEED | 4066 MVNETA_GMAC_CONFIG_GMII_SPEED | 4067 MVNETA_GMAC_CONFIG_FLOW_CTRL | 4068 MVNETA_GMAC_CONFIG_FULL_DUPLEX); 4069 val |= MVNETA_GMAC_FORCE_LINK_PASS; 4070 4071 if (speed == SPEED_1000 || speed == SPEED_2500) 4072 val |= MVNETA_GMAC_CONFIG_GMII_SPEED; 4073 else if (speed == SPEED_100) 4074 val |= MVNETA_GMAC_CONFIG_MII_SPEED; 4075 4076 if (duplex == DUPLEX_FULL) 4077 val |= MVNETA_GMAC_CONFIG_FULL_DUPLEX; 4078 4079 if (tx_pause || rx_pause) 4080 val |= MVNETA_GMAC_CONFIG_FLOW_CTRL; 4081 4082 mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val); 4083 } else { 4084 /* When inband doesn't cover flow control or flow control is 4085 * disabled, we need to manually configure it. This bit will 4086 * only have effect if MVNETA_GMAC_AN_FLOW_CTRL_EN is unset. 4087 */ 4088 val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG); 4089 val &= ~MVNETA_GMAC_CONFIG_FLOW_CTRL; 4090 4091 if (tx_pause || rx_pause) 4092 val |= MVNETA_GMAC_CONFIG_FLOW_CTRL; 4093 4094 mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val); 4095 } 4096 4097 mvneta_port_up(pp); 4098 4099 if (phy && pp->eee_enabled) { 4100 pp->eee_active = phy_init_eee(phy, 0) >= 0; 4101 mvneta_set_eee(pp, pp->eee_active && pp->tx_lpi_enabled); 4102 } 4103 } 4104 4105 static const struct phylink_mac_ops mvneta_phylink_ops = { 4106 .validate = mvneta_validate, 4107 .mac_pcs_get_state = mvneta_mac_pcs_get_state, 4108 .mac_an_restart = mvneta_mac_an_restart, 4109 .mac_config = mvneta_mac_config, 4110 .mac_link_down = mvneta_mac_link_down, 4111 .mac_link_up = mvneta_mac_link_up, 4112 }; 4113 4114 static int mvneta_mdio_probe(struct mvneta_port *pp) 4115 { 4116 struct ethtool_wolinfo wol = { .cmd = ETHTOOL_GWOL }; 4117 int err = phylink_of_phy_connect(pp->phylink, pp->dn, 0); 4118 4119 if (err) 4120 netdev_err(pp->dev, "could not attach PHY: %d\n", err); 4121 4122 phylink_ethtool_get_wol(pp->phylink, &wol); 4123 device_set_wakeup_capable(&pp->dev->dev, !!wol.supported); 4124 4125 /* PHY WoL may be enabled but device wakeup disabled */ 4126 if (wol.supported) 4127 device_set_wakeup_enable(&pp->dev->dev, !!wol.wolopts); 4128 4129 return err; 4130 } 4131 4132 static void mvneta_mdio_remove(struct mvneta_port *pp) 4133 { 4134 phylink_disconnect_phy(pp->phylink); 4135 } 4136 4137 /* Electing a CPU must be done in an atomic way: it should be done 4138 * after or before the removal/insertion of a CPU and this function is 4139 * not reentrant. 4140 */ 4141 static void mvneta_percpu_elect(struct mvneta_port *pp) 4142 { 4143 int elected_cpu = 0, max_cpu, cpu, i = 0; 4144 4145 /* Use the cpu associated to the rxq when it is online, in all 4146 * the other cases, use the cpu 0 which can't be offline. 4147 */ 4148 if (cpu_online(pp->rxq_def)) 4149 elected_cpu = pp->rxq_def; 4150 4151 max_cpu = num_present_cpus(); 4152 4153 for_each_online_cpu(cpu) { 4154 int rxq_map = 0, txq_map = 0; 4155 int rxq; 4156 4157 for (rxq = 0; rxq < rxq_number; rxq++) 4158 if ((rxq % max_cpu) == cpu) 4159 rxq_map |= MVNETA_CPU_RXQ_ACCESS(rxq); 4160 4161 if (cpu == elected_cpu) 4162 /* Map the default receive queue queue to the 4163 * elected CPU 4164 */ 4165 rxq_map |= MVNETA_CPU_RXQ_ACCESS(pp->rxq_def); 4166 4167 /* We update the TX queue map only if we have one 4168 * queue. In this case we associate the TX queue to 4169 * the CPU bound to the default RX queue 4170 */ 4171 if (txq_number == 1) 4172 txq_map = (cpu == elected_cpu) ? 4173 MVNETA_CPU_TXQ_ACCESS(1) : 0; 4174 else 4175 txq_map = mvreg_read(pp, MVNETA_CPU_MAP(cpu)) & 4176 MVNETA_CPU_TXQ_ACCESS_ALL_MASK; 4177 4178 mvreg_write(pp, MVNETA_CPU_MAP(cpu), rxq_map | txq_map); 4179 4180 /* Update the interrupt mask on each CPU according the 4181 * new mapping 4182 */ 4183 smp_call_function_single(cpu, mvneta_percpu_unmask_interrupt, 4184 pp, true); 4185 i++; 4186 4187 } 4188 }; 4189 4190 static int mvneta_cpu_online(unsigned int cpu, struct hlist_node *node) 4191 { 4192 int other_cpu; 4193 struct mvneta_port *pp = hlist_entry_safe(node, struct mvneta_port, 4194 node_online); 4195 struct mvneta_pcpu_port *port = per_cpu_ptr(pp->ports, cpu); 4196 4197 4198 spin_lock(&pp->lock); 4199 /* 4200 * Configuring the driver for a new CPU while the driver is 4201 * stopping is racy, so just avoid it. 4202 */ 4203 if (pp->is_stopped) { 4204 spin_unlock(&pp->lock); 4205 return 0; 4206 } 4207 netif_tx_stop_all_queues(pp->dev); 4208 4209 /* 4210 * We have to synchronise on tha napi of each CPU except the one 4211 * just being woken up 4212 */ 4213 for_each_online_cpu(other_cpu) { 4214 if (other_cpu != cpu) { 4215 struct mvneta_pcpu_port *other_port = 4216 per_cpu_ptr(pp->ports, other_cpu); 4217 4218 napi_synchronize(&other_port->napi); 4219 } 4220 } 4221 4222 /* Mask all ethernet port interrupts */ 4223 on_each_cpu(mvneta_percpu_mask_interrupt, pp, true); 4224 napi_enable(&port->napi); 4225 4226 /* 4227 * Enable per-CPU interrupts on the CPU that is 4228 * brought up. 4229 */ 4230 mvneta_percpu_enable(pp); 4231 4232 /* 4233 * Enable per-CPU interrupt on the one CPU we care 4234 * about. 4235 */ 4236 mvneta_percpu_elect(pp); 4237 4238 /* Unmask all ethernet port interrupts */ 4239 on_each_cpu(mvneta_percpu_unmask_interrupt, pp, true); 4240 mvreg_write(pp, MVNETA_INTR_MISC_MASK, 4241 MVNETA_CAUSE_PHY_STATUS_CHANGE | 4242 MVNETA_CAUSE_LINK_CHANGE); 4243 netif_tx_start_all_queues(pp->dev); 4244 spin_unlock(&pp->lock); 4245 return 0; 4246 } 4247 4248 static int mvneta_cpu_down_prepare(unsigned int cpu, struct hlist_node *node) 4249 { 4250 struct mvneta_port *pp = hlist_entry_safe(node, struct mvneta_port, 4251 node_online); 4252 struct mvneta_pcpu_port *port = per_cpu_ptr(pp->ports, cpu); 4253 4254 /* 4255 * Thanks to this lock we are sure that any pending cpu election is 4256 * done. 4257 */ 4258 spin_lock(&pp->lock); 4259 /* Mask all ethernet port interrupts */ 4260 on_each_cpu(mvneta_percpu_mask_interrupt, pp, true); 4261 spin_unlock(&pp->lock); 4262 4263 napi_synchronize(&port->napi); 4264 napi_disable(&port->napi); 4265 /* Disable per-CPU interrupts on the CPU that is brought down. */ 4266 mvneta_percpu_disable(pp); 4267 return 0; 4268 } 4269 4270 static int mvneta_cpu_dead(unsigned int cpu, struct hlist_node *node) 4271 { 4272 struct mvneta_port *pp = hlist_entry_safe(node, struct mvneta_port, 4273 node_dead); 4274 4275 /* Check if a new CPU must be elected now this on is down */ 4276 spin_lock(&pp->lock); 4277 mvneta_percpu_elect(pp); 4278 spin_unlock(&pp->lock); 4279 /* Unmask all ethernet port interrupts */ 4280 on_each_cpu(mvneta_percpu_unmask_interrupt, pp, true); 4281 mvreg_write(pp, MVNETA_INTR_MISC_MASK, 4282 MVNETA_CAUSE_PHY_STATUS_CHANGE | 4283 MVNETA_CAUSE_LINK_CHANGE); 4284 netif_tx_start_all_queues(pp->dev); 4285 return 0; 4286 } 4287 4288 static int mvneta_open(struct net_device *dev) 4289 { 4290 struct mvneta_port *pp = netdev_priv(dev); 4291 int ret; 4292 4293 pp->pkt_size = MVNETA_RX_PKT_SIZE(pp->dev->mtu); 4294 4295 ret = mvneta_setup_rxqs(pp); 4296 if (ret) 4297 return ret; 4298 4299 ret = mvneta_setup_txqs(pp); 4300 if (ret) 4301 goto err_cleanup_rxqs; 4302 4303 /* Connect to port interrupt line */ 4304 if (pp->neta_armada3700) 4305 ret = request_irq(pp->dev->irq, mvneta_isr, 0, 4306 dev->name, pp); 4307 else 4308 ret = request_percpu_irq(pp->dev->irq, mvneta_percpu_isr, 4309 dev->name, pp->ports); 4310 if (ret) { 4311 netdev_err(pp->dev, "cannot request irq %d\n", pp->dev->irq); 4312 goto err_cleanup_txqs; 4313 } 4314 4315 if (!pp->neta_armada3700) { 4316 /* Enable per-CPU interrupt on all the CPU to handle our RX 4317 * queue interrupts 4318 */ 4319 on_each_cpu(mvneta_percpu_enable, pp, true); 4320 4321 pp->is_stopped = false; 4322 /* Register a CPU notifier to handle the case where our CPU 4323 * might be taken offline. 4324 */ 4325 ret = cpuhp_state_add_instance_nocalls(online_hpstate, 4326 &pp->node_online); 4327 if (ret) 4328 goto err_free_irq; 4329 4330 ret = cpuhp_state_add_instance_nocalls(CPUHP_NET_MVNETA_DEAD, 4331 &pp->node_dead); 4332 if (ret) 4333 goto err_free_online_hp; 4334 } 4335 4336 ret = mvneta_mdio_probe(pp); 4337 if (ret < 0) { 4338 netdev_err(dev, "cannot probe MDIO bus\n"); 4339 goto err_free_dead_hp; 4340 } 4341 4342 mvneta_start_dev(pp); 4343 4344 return 0; 4345 4346 err_free_dead_hp: 4347 if (!pp->neta_armada3700) 4348 cpuhp_state_remove_instance_nocalls(CPUHP_NET_MVNETA_DEAD, 4349 &pp->node_dead); 4350 err_free_online_hp: 4351 if (!pp->neta_armada3700) 4352 cpuhp_state_remove_instance_nocalls(online_hpstate, 4353 &pp->node_online); 4354 err_free_irq: 4355 if (pp->neta_armada3700) { 4356 free_irq(pp->dev->irq, pp); 4357 } else { 4358 on_each_cpu(mvneta_percpu_disable, pp, true); 4359 free_percpu_irq(pp->dev->irq, pp->ports); 4360 } 4361 err_cleanup_txqs: 4362 mvneta_cleanup_txqs(pp); 4363 err_cleanup_rxqs: 4364 mvneta_cleanup_rxqs(pp); 4365 return ret; 4366 } 4367 4368 /* Stop the port, free port interrupt line */ 4369 static int mvneta_stop(struct net_device *dev) 4370 { 4371 struct mvneta_port *pp = netdev_priv(dev); 4372 4373 if (!pp->neta_armada3700) { 4374 /* Inform that we are stopping so we don't want to setup the 4375 * driver for new CPUs in the notifiers. The code of the 4376 * notifier for CPU online is protected by the same spinlock, 4377 * so when we get the lock, the notifer work is done. 4378 */ 4379 spin_lock(&pp->lock); 4380 pp->is_stopped = true; 4381 spin_unlock(&pp->lock); 4382 4383 mvneta_stop_dev(pp); 4384 mvneta_mdio_remove(pp); 4385 4386 cpuhp_state_remove_instance_nocalls(online_hpstate, 4387 &pp->node_online); 4388 cpuhp_state_remove_instance_nocalls(CPUHP_NET_MVNETA_DEAD, 4389 &pp->node_dead); 4390 on_each_cpu(mvneta_percpu_disable, pp, true); 4391 free_percpu_irq(dev->irq, pp->ports); 4392 } else { 4393 mvneta_stop_dev(pp); 4394 mvneta_mdio_remove(pp); 4395 free_irq(dev->irq, pp); 4396 } 4397 4398 mvneta_cleanup_rxqs(pp); 4399 mvneta_cleanup_txqs(pp); 4400 4401 return 0; 4402 } 4403 4404 static int mvneta_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) 4405 { 4406 struct mvneta_port *pp = netdev_priv(dev); 4407 4408 return phylink_mii_ioctl(pp->phylink, ifr, cmd); 4409 } 4410 4411 static int mvneta_xdp_setup(struct net_device *dev, struct bpf_prog *prog, 4412 struct netlink_ext_ack *extack) 4413 { 4414 bool need_update, running = netif_running(dev); 4415 struct mvneta_port *pp = netdev_priv(dev); 4416 struct bpf_prog *old_prog; 4417 4418 if (prog && dev->mtu > MVNETA_MAX_RX_BUF_SIZE) { 4419 NL_SET_ERR_MSG_MOD(extack, "Jumbo frames not supported on XDP"); 4420 return -EOPNOTSUPP; 4421 } 4422 4423 if (pp->bm_priv) { 4424 NL_SET_ERR_MSG_MOD(extack, 4425 "Hardware Buffer Management not supported on XDP"); 4426 return -EOPNOTSUPP; 4427 } 4428 4429 need_update = !!pp->xdp_prog != !!prog; 4430 if (running && need_update) 4431 mvneta_stop(dev); 4432 4433 old_prog = xchg(&pp->xdp_prog, prog); 4434 if (old_prog) 4435 bpf_prog_put(old_prog); 4436 4437 if (running && need_update) 4438 return mvneta_open(dev); 4439 4440 return 0; 4441 } 4442 4443 static int mvneta_xdp(struct net_device *dev, struct netdev_bpf *xdp) 4444 { 4445 switch (xdp->command) { 4446 case XDP_SETUP_PROG: 4447 return mvneta_xdp_setup(dev, xdp->prog, xdp->extack); 4448 default: 4449 return -EINVAL; 4450 } 4451 } 4452 4453 /* Ethtool methods */ 4454 4455 /* Set link ksettings (phy address, speed) for ethtools */ 4456 static int 4457 mvneta_ethtool_set_link_ksettings(struct net_device *ndev, 4458 const struct ethtool_link_ksettings *cmd) 4459 { 4460 struct mvneta_port *pp = netdev_priv(ndev); 4461 4462 return phylink_ethtool_ksettings_set(pp->phylink, cmd); 4463 } 4464 4465 /* Get link ksettings for ethtools */ 4466 static int 4467 mvneta_ethtool_get_link_ksettings(struct net_device *ndev, 4468 struct ethtool_link_ksettings *cmd) 4469 { 4470 struct mvneta_port *pp = netdev_priv(ndev); 4471 4472 return phylink_ethtool_ksettings_get(pp->phylink, cmd); 4473 } 4474 4475 static int mvneta_ethtool_nway_reset(struct net_device *dev) 4476 { 4477 struct mvneta_port *pp = netdev_priv(dev); 4478 4479 return phylink_ethtool_nway_reset(pp->phylink); 4480 } 4481 4482 /* Set interrupt coalescing for ethtools */ 4483 static int mvneta_ethtool_set_coalesce(struct net_device *dev, 4484 struct ethtool_coalesce *c) 4485 { 4486 struct mvneta_port *pp = netdev_priv(dev); 4487 int queue; 4488 4489 for (queue = 0; queue < rxq_number; queue++) { 4490 struct mvneta_rx_queue *rxq = &pp->rxqs[queue]; 4491 rxq->time_coal = c->rx_coalesce_usecs; 4492 rxq->pkts_coal = c->rx_max_coalesced_frames; 4493 mvneta_rx_pkts_coal_set(pp, rxq, rxq->pkts_coal); 4494 mvneta_rx_time_coal_set(pp, rxq, rxq->time_coal); 4495 } 4496 4497 for (queue = 0; queue < txq_number; queue++) { 4498 struct mvneta_tx_queue *txq = &pp->txqs[queue]; 4499 txq->done_pkts_coal = c->tx_max_coalesced_frames; 4500 mvneta_tx_done_pkts_coal_set(pp, txq, txq->done_pkts_coal); 4501 } 4502 4503 return 0; 4504 } 4505 4506 /* get coalescing for ethtools */ 4507 static int mvneta_ethtool_get_coalesce(struct net_device *dev, 4508 struct ethtool_coalesce *c) 4509 { 4510 struct mvneta_port *pp = netdev_priv(dev); 4511 4512 c->rx_coalesce_usecs = pp->rxqs[0].time_coal; 4513 c->rx_max_coalesced_frames = pp->rxqs[0].pkts_coal; 4514 4515 c->tx_max_coalesced_frames = pp->txqs[0].done_pkts_coal; 4516 return 0; 4517 } 4518 4519 4520 static void mvneta_ethtool_get_drvinfo(struct net_device *dev, 4521 struct ethtool_drvinfo *drvinfo) 4522 { 4523 strlcpy(drvinfo->driver, MVNETA_DRIVER_NAME, 4524 sizeof(drvinfo->driver)); 4525 strlcpy(drvinfo->version, MVNETA_DRIVER_VERSION, 4526 sizeof(drvinfo->version)); 4527 strlcpy(drvinfo->bus_info, dev_name(&dev->dev), 4528 sizeof(drvinfo->bus_info)); 4529 } 4530 4531 4532 static void mvneta_ethtool_get_ringparam(struct net_device *netdev, 4533 struct ethtool_ringparam *ring) 4534 { 4535 struct mvneta_port *pp = netdev_priv(netdev); 4536 4537 ring->rx_max_pending = MVNETA_MAX_RXD; 4538 ring->tx_max_pending = MVNETA_MAX_TXD; 4539 ring->rx_pending = pp->rx_ring_size; 4540 ring->tx_pending = pp->tx_ring_size; 4541 } 4542 4543 static int mvneta_ethtool_set_ringparam(struct net_device *dev, 4544 struct ethtool_ringparam *ring) 4545 { 4546 struct mvneta_port *pp = netdev_priv(dev); 4547 4548 if ((ring->rx_pending == 0) || (ring->tx_pending == 0)) 4549 return -EINVAL; 4550 pp->rx_ring_size = ring->rx_pending < MVNETA_MAX_RXD ? 4551 ring->rx_pending : MVNETA_MAX_RXD; 4552 4553 pp->tx_ring_size = clamp_t(u16, ring->tx_pending, 4554 MVNETA_MAX_SKB_DESCS * 2, MVNETA_MAX_TXD); 4555 if (pp->tx_ring_size != ring->tx_pending) 4556 netdev_warn(dev, "TX queue size set to %u (requested %u)\n", 4557 pp->tx_ring_size, ring->tx_pending); 4558 4559 if (netif_running(dev)) { 4560 mvneta_stop(dev); 4561 if (mvneta_open(dev)) { 4562 netdev_err(dev, 4563 "error on opening device after ring param change\n"); 4564 return -ENOMEM; 4565 } 4566 } 4567 4568 return 0; 4569 } 4570 4571 static void mvneta_ethtool_get_pauseparam(struct net_device *dev, 4572 struct ethtool_pauseparam *pause) 4573 { 4574 struct mvneta_port *pp = netdev_priv(dev); 4575 4576 phylink_ethtool_get_pauseparam(pp->phylink, pause); 4577 } 4578 4579 static int mvneta_ethtool_set_pauseparam(struct net_device *dev, 4580 struct ethtool_pauseparam *pause) 4581 { 4582 struct mvneta_port *pp = netdev_priv(dev); 4583 4584 return phylink_ethtool_set_pauseparam(pp->phylink, pause); 4585 } 4586 4587 static void mvneta_ethtool_get_strings(struct net_device *netdev, u32 sset, 4588 u8 *data) 4589 { 4590 if (sset == ETH_SS_STATS) { 4591 int i; 4592 4593 for (i = 0; i < ARRAY_SIZE(mvneta_statistics); i++) 4594 memcpy(data + i * ETH_GSTRING_LEN, 4595 mvneta_statistics[i].name, ETH_GSTRING_LEN); 4596 } 4597 } 4598 4599 static void 4600 mvneta_ethtool_update_pcpu_stats(struct mvneta_port *pp, 4601 struct mvneta_ethtool_stats *es) 4602 { 4603 unsigned int start; 4604 int cpu; 4605 4606 for_each_possible_cpu(cpu) { 4607 struct mvneta_pcpu_stats *stats; 4608 u64 skb_alloc_error; 4609 u64 refill_error; 4610 u64 xdp_redirect; 4611 u64 xdp_xmit_err; 4612 u64 xdp_tx_err; 4613 u64 xdp_pass; 4614 u64 xdp_drop; 4615 u64 xdp_xmit; 4616 u64 xdp_tx; 4617 4618 stats = per_cpu_ptr(pp->stats, cpu); 4619 do { 4620 start = u64_stats_fetch_begin_irq(&stats->syncp); 4621 skb_alloc_error = stats->es.skb_alloc_error; 4622 refill_error = stats->es.refill_error; 4623 xdp_redirect = stats->es.ps.xdp_redirect; 4624 xdp_pass = stats->es.ps.xdp_pass; 4625 xdp_drop = stats->es.ps.xdp_drop; 4626 xdp_xmit = stats->es.ps.xdp_xmit; 4627 xdp_xmit_err = stats->es.ps.xdp_xmit_err; 4628 xdp_tx = stats->es.ps.xdp_tx; 4629 xdp_tx_err = stats->es.ps.xdp_tx_err; 4630 } while (u64_stats_fetch_retry_irq(&stats->syncp, start)); 4631 4632 es->skb_alloc_error += skb_alloc_error; 4633 es->refill_error += refill_error; 4634 es->ps.xdp_redirect += xdp_redirect; 4635 es->ps.xdp_pass += xdp_pass; 4636 es->ps.xdp_drop += xdp_drop; 4637 es->ps.xdp_xmit += xdp_xmit; 4638 es->ps.xdp_xmit_err += xdp_xmit_err; 4639 es->ps.xdp_tx += xdp_tx; 4640 es->ps.xdp_tx_err += xdp_tx_err; 4641 } 4642 } 4643 4644 static void mvneta_ethtool_update_stats(struct mvneta_port *pp) 4645 { 4646 struct mvneta_ethtool_stats stats = {}; 4647 const struct mvneta_statistic *s; 4648 void __iomem *base = pp->base; 4649 u32 high, low; 4650 u64 val; 4651 int i; 4652 4653 mvneta_ethtool_update_pcpu_stats(pp, &stats); 4654 for (i = 0, s = mvneta_statistics; 4655 s < mvneta_statistics + ARRAY_SIZE(mvneta_statistics); 4656 s++, i++) { 4657 switch (s->type) { 4658 case T_REG_32: 4659 val = readl_relaxed(base + s->offset); 4660 pp->ethtool_stats[i] += val; 4661 break; 4662 case T_REG_64: 4663 /* Docs say to read low 32-bit then high */ 4664 low = readl_relaxed(base + s->offset); 4665 high = readl_relaxed(base + s->offset + 4); 4666 val = (u64)high << 32 | low; 4667 pp->ethtool_stats[i] += val; 4668 break; 4669 case T_SW: 4670 switch (s->offset) { 4671 case ETHTOOL_STAT_EEE_WAKEUP: 4672 val = phylink_get_eee_err(pp->phylink); 4673 pp->ethtool_stats[i] += val; 4674 break; 4675 case ETHTOOL_STAT_SKB_ALLOC_ERR: 4676 pp->ethtool_stats[i] = stats.skb_alloc_error; 4677 break; 4678 case ETHTOOL_STAT_REFILL_ERR: 4679 pp->ethtool_stats[i] = stats.refill_error; 4680 break; 4681 case ETHTOOL_XDP_REDIRECT: 4682 pp->ethtool_stats[i] = stats.ps.xdp_redirect; 4683 break; 4684 case ETHTOOL_XDP_PASS: 4685 pp->ethtool_stats[i] = stats.ps.xdp_pass; 4686 break; 4687 case ETHTOOL_XDP_DROP: 4688 pp->ethtool_stats[i] = stats.ps.xdp_drop; 4689 break; 4690 case ETHTOOL_XDP_TX: 4691 pp->ethtool_stats[i] = stats.ps.xdp_tx; 4692 break; 4693 case ETHTOOL_XDP_TX_ERR: 4694 pp->ethtool_stats[i] = stats.ps.xdp_tx_err; 4695 break; 4696 case ETHTOOL_XDP_XMIT: 4697 pp->ethtool_stats[i] = stats.ps.xdp_xmit; 4698 break; 4699 case ETHTOOL_XDP_XMIT_ERR: 4700 pp->ethtool_stats[i] = stats.ps.xdp_xmit_err; 4701 break; 4702 } 4703 break; 4704 } 4705 } 4706 } 4707 4708 static void mvneta_ethtool_get_stats(struct net_device *dev, 4709 struct ethtool_stats *stats, u64 *data) 4710 { 4711 struct mvneta_port *pp = netdev_priv(dev); 4712 int i; 4713 4714 mvneta_ethtool_update_stats(pp); 4715 4716 for (i = 0; i < ARRAY_SIZE(mvneta_statistics); i++) 4717 *data++ = pp->ethtool_stats[i]; 4718 } 4719 4720 static int mvneta_ethtool_get_sset_count(struct net_device *dev, int sset) 4721 { 4722 if (sset == ETH_SS_STATS) 4723 return ARRAY_SIZE(mvneta_statistics); 4724 return -EOPNOTSUPP; 4725 } 4726 4727 static u32 mvneta_ethtool_get_rxfh_indir_size(struct net_device *dev) 4728 { 4729 return MVNETA_RSS_LU_TABLE_SIZE; 4730 } 4731 4732 static int mvneta_ethtool_get_rxnfc(struct net_device *dev, 4733 struct ethtool_rxnfc *info, 4734 u32 *rules __always_unused) 4735 { 4736 switch (info->cmd) { 4737 case ETHTOOL_GRXRINGS: 4738 info->data = rxq_number; 4739 return 0; 4740 case ETHTOOL_GRXFH: 4741 return -EOPNOTSUPP; 4742 default: 4743 return -EOPNOTSUPP; 4744 } 4745 } 4746 4747 static int mvneta_config_rss(struct mvneta_port *pp) 4748 { 4749 int cpu; 4750 u32 val; 4751 4752 netif_tx_stop_all_queues(pp->dev); 4753 4754 on_each_cpu(mvneta_percpu_mask_interrupt, pp, true); 4755 4756 if (!pp->neta_armada3700) { 4757 /* We have to synchronise on the napi of each CPU */ 4758 for_each_online_cpu(cpu) { 4759 struct mvneta_pcpu_port *pcpu_port = 4760 per_cpu_ptr(pp->ports, cpu); 4761 4762 napi_synchronize(&pcpu_port->napi); 4763 napi_disable(&pcpu_port->napi); 4764 } 4765 } else { 4766 napi_synchronize(&pp->napi); 4767 napi_disable(&pp->napi); 4768 } 4769 4770 pp->rxq_def = pp->indir[0]; 4771 4772 /* Update unicast mapping */ 4773 mvneta_set_rx_mode(pp->dev); 4774 4775 /* Update val of portCfg register accordingly with all RxQueue types */ 4776 val = MVNETA_PORT_CONFIG_DEFL_VALUE(pp->rxq_def); 4777 mvreg_write(pp, MVNETA_PORT_CONFIG, val); 4778 4779 /* Update the elected CPU matching the new rxq_def */ 4780 spin_lock(&pp->lock); 4781 mvneta_percpu_elect(pp); 4782 spin_unlock(&pp->lock); 4783 4784 if (!pp->neta_armada3700) { 4785 /* We have to synchronise on the napi of each CPU */ 4786 for_each_online_cpu(cpu) { 4787 struct mvneta_pcpu_port *pcpu_port = 4788 per_cpu_ptr(pp->ports, cpu); 4789 4790 napi_enable(&pcpu_port->napi); 4791 } 4792 } else { 4793 napi_enable(&pp->napi); 4794 } 4795 4796 netif_tx_start_all_queues(pp->dev); 4797 4798 return 0; 4799 } 4800 4801 static int mvneta_ethtool_set_rxfh(struct net_device *dev, const u32 *indir, 4802 const u8 *key, const u8 hfunc) 4803 { 4804 struct mvneta_port *pp = netdev_priv(dev); 4805 4806 /* Current code for Armada 3700 doesn't support RSS features yet */ 4807 if (pp->neta_armada3700) 4808 return -EOPNOTSUPP; 4809 4810 /* We require at least one supported parameter to be changed 4811 * and no change in any of the unsupported parameters 4812 */ 4813 if (key || 4814 (hfunc != ETH_RSS_HASH_NO_CHANGE && hfunc != ETH_RSS_HASH_TOP)) 4815 return -EOPNOTSUPP; 4816 4817 if (!indir) 4818 return 0; 4819 4820 memcpy(pp->indir, indir, MVNETA_RSS_LU_TABLE_SIZE); 4821 4822 return mvneta_config_rss(pp); 4823 } 4824 4825 static int mvneta_ethtool_get_rxfh(struct net_device *dev, u32 *indir, u8 *key, 4826 u8 *hfunc) 4827 { 4828 struct mvneta_port *pp = netdev_priv(dev); 4829 4830 /* Current code for Armada 3700 doesn't support RSS features yet */ 4831 if (pp->neta_armada3700) 4832 return -EOPNOTSUPP; 4833 4834 if (hfunc) 4835 *hfunc = ETH_RSS_HASH_TOP; 4836 4837 if (!indir) 4838 return 0; 4839 4840 memcpy(indir, pp->indir, MVNETA_RSS_LU_TABLE_SIZE); 4841 4842 return 0; 4843 } 4844 4845 static void mvneta_ethtool_get_wol(struct net_device *dev, 4846 struct ethtool_wolinfo *wol) 4847 { 4848 struct mvneta_port *pp = netdev_priv(dev); 4849 4850 phylink_ethtool_get_wol(pp->phylink, wol); 4851 } 4852 4853 static int mvneta_ethtool_set_wol(struct net_device *dev, 4854 struct ethtool_wolinfo *wol) 4855 { 4856 struct mvneta_port *pp = netdev_priv(dev); 4857 int ret; 4858 4859 ret = phylink_ethtool_set_wol(pp->phylink, wol); 4860 if (!ret) 4861 device_set_wakeup_enable(&dev->dev, !!wol->wolopts); 4862 4863 return ret; 4864 } 4865 4866 static int mvneta_ethtool_get_eee(struct net_device *dev, 4867 struct ethtool_eee *eee) 4868 { 4869 struct mvneta_port *pp = netdev_priv(dev); 4870 u32 lpi_ctl0; 4871 4872 lpi_ctl0 = mvreg_read(pp, MVNETA_LPI_CTRL_0); 4873 4874 eee->eee_enabled = pp->eee_enabled; 4875 eee->eee_active = pp->eee_active; 4876 eee->tx_lpi_enabled = pp->tx_lpi_enabled; 4877 eee->tx_lpi_timer = (lpi_ctl0) >> 8; // * scale; 4878 4879 return phylink_ethtool_get_eee(pp->phylink, eee); 4880 } 4881 4882 static int mvneta_ethtool_set_eee(struct net_device *dev, 4883 struct ethtool_eee *eee) 4884 { 4885 struct mvneta_port *pp = netdev_priv(dev); 4886 u32 lpi_ctl0; 4887 4888 /* The Armada 37x documents do not give limits for this other than 4889 * it being an 8-bit register. */ 4890 if (eee->tx_lpi_enabled && eee->tx_lpi_timer > 255) 4891 return -EINVAL; 4892 4893 lpi_ctl0 = mvreg_read(pp, MVNETA_LPI_CTRL_0); 4894 lpi_ctl0 &= ~(0xff << 8); 4895 lpi_ctl0 |= eee->tx_lpi_timer << 8; 4896 mvreg_write(pp, MVNETA_LPI_CTRL_0, lpi_ctl0); 4897 4898 pp->eee_enabled = eee->eee_enabled; 4899 pp->tx_lpi_enabled = eee->tx_lpi_enabled; 4900 4901 mvneta_set_eee(pp, eee->tx_lpi_enabled && eee->eee_enabled); 4902 4903 return phylink_ethtool_set_eee(pp->phylink, eee); 4904 } 4905 4906 static const struct net_device_ops mvneta_netdev_ops = { 4907 .ndo_open = mvneta_open, 4908 .ndo_stop = mvneta_stop, 4909 .ndo_start_xmit = mvneta_tx, 4910 .ndo_set_rx_mode = mvneta_set_rx_mode, 4911 .ndo_set_mac_address = mvneta_set_mac_addr, 4912 .ndo_change_mtu = mvneta_change_mtu, 4913 .ndo_fix_features = mvneta_fix_features, 4914 .ndo_get_stats64 = mvneta_get_stats64, 4915 .ndo_do_ioctl = mvneta_ioctl, 4916 .ndo_bpf = mvneta_xdp, 4917 .ndo_xdp_xmit = mvneta_xdp_xmit, 4918 }; 4919 4920 static const struct ethtool_ops mvneta_eth_tool_ops = { 4921 .supported_coalesce_params = ETHTOOL_COALESCE_RX_USECS | 4922 ETHTOOL_COALESCE_MAX_FRAMES, 4923 .nway_reset = mvneta_ethtool_nway_reset, 4924 .get_link = ethtool_op_get_link, 4925 .set_coalesce = mvneta_ethtool_set_coalesce, 4926 .get_coalesce = mvneta_ethtool_get_coalesce, 4927 .get_drvinfo = mvneta_ethtool_get_drvinfo, 4928 .get_ringparam = mvneta_ethtool_get_ringparam, 4929 .set_ringparam = mvneta_ethtool_set_ringparam, 4930 .get_pauseparam = mvneta_ethtool_get_pauseparam, 4931 .set_pauseparam = mvneta_ethtool_set_pauseparam, 4932 .get_strings = mvneta_ethtool_get_strings, 4933 .get_ethtool_stats = mvneta_ethtool_get_stats, 4934 .get_sset_count = mvneta_ethtool_get_sset_count, 4935 .get_rxfh_indir_size = mvneta_ethtool_get_rxfh_indir_size, 4936 .get_rxnfc = mvneta_ethtool_get_rxnfc, 4937 .get_rxfh = mvneta_ethtool_get_rxfh, 4938 .set_rxfh = mvneta_ethtool_set_rxfh, 4939 .get_link_ksettings = mvneta_ethtool_get_link_ksettings, 4940 .set_link_ksettings = mvneta_ethtool_set_link_ksettings, 4941 .get_wol = mvneta_ethtool_get_wol, 4942 .set_wol = mvneta_ethtool_set_wol, 4943 .get_eee = mvneta_ethtool_get_eee, 4944 .set_eee = mvneta_ethtool_set_eee, 4945 }; 4946 4947 /* Initialize hw */ 4948 static int mvneta_init(struct device *dev, struct mvneta_port *pp) 4949 { 4950 int queue; 4951 4952 /* Disable port */ 4953 mvneta_port_disable(pp); 4954 4955 /* Set port default values */ 4956 mvneta_defaults_set(pp); 4957 4958 pp->txqs = devm_kcalloc(dev, txq_number, sizeof(*pp->txqs), GFP_KERNEL); 4959 if (!pp->txqs) 4960 return -ENOMEM; 4961 4962 /* Initialize TX descriptor rings */ 4963 for (queue = 0; queue < txq_number; queue++) { 4964 struct mvneta_tx_queue *txq = &pp->txqs[queue]; 4965 txq->id = queue; 4966 txq->size = pp->tx_ring_size; 4967 txq->done_pkts_coal = MVNETA_TXDONE_COAL_PKTS; 4968 } 4969 4970 pp->rxqs = devm_kcalloc(dev, rxq_number, sizeof(*pp->rxqs), GFP_KERNEL); 4971 if (!pp->rxqs) 4972 return -ENOMEM; 4973 4974 /* Create Rx descriptor rings */ 4975 for (queue = 0; queue < rxq_number; queue++) { 4976 struct mvneta_rx_queue *rxq = &pp->rxqs[queue]; 4977 rxq->id = queue; 4978 rxq->size = pp->rx_ring_size; 4979 rxq->pkts_coal = MVNETA_RX_COAL_PKTS; 4980 rxq->time_coal = MVNETA_RX_COAL_USEC; 4981 rxq->buf_virt_addr 4982 = devm_kmalloc_array(pp->dev->dev.parent, 4983 rxq->size, 4984 sizeof(*rxq->buf_virt_addr), 4985 GFP_KERNEL); 4986 if (!rxq->buf_virt_addr) 4987 return -ENOMEM; 4988 } 4989 4990 return 0; 4991 } 4992 4993 /* platform glue : initialize decoding windows */ 4994 static void mvneta_conf_mbus_windows(struct mvneta_port *pp, 4995 const struct mbus_dram_target_info *dram) 4996 { 4997 u32 win_enable; 4998 u32 win_protect; 4999 int i; 5000 5001 for (i = 0; i < 6; i++) { 5002 mvreg_write(pp, MVNETA_WIN_BASE(i), 0); 5003 mvreg_write(pp, MVNETA_WIN_SIZE(i), 0); 5004 5005 if (i < 4) 5006 mvreg_write(pp, MVNETA_WIN_REMAP(i), 0); 5007 } 5008 5009 win_enable = 0x3f; 5010 win_protect = 0; 5011 5012 if (dram) { 5013 for (i = 0; i < dram->num_cs; i++) { 5014 const struct mbus_dram_window *cs = dram->cs + i; 5015 5016 mvreg_write(pp, MVNETA_WIN_BASE(i), 5017 (cs->base & 0xffff0000) | 5018 (cs->mbus_attr << 8) | 5019 dram->mbus_dram_target_id); 5020 5021 mvreg_write(pp, MVNETA_WIN_SIZE(i), 5022 (cs->size - 1) & 0xffff0000); 5023 5024 win_enable &= ~(1 << i); 5025 win_protect |= 3 << (2 * i); 5026 } 5027 } else { 5028 /* For Armada3700 open default 4GB Mbus window, leaving 5029 * arbitration of target/attribute to a different layer 5030 * of configuration. 5031 */ 5032 mvreg_write(pp, MVNETA_WIN_SIZE(0), 0xffff0000); 5033 win_enable &= ~BIT(0); 5034 win_protect = 3; 5035 } 5036 5037 mvreg_write(pp, MVNETA_BASE_ADDR_ENABLE, win_enable); 5038 mvreg_write(pp, MVNETA_ACCESS_PROTECT_ENABLE, win_protect); 5039 } 5040 5041 /* Power up the port */ 5042 static int mvneta_port_power_up(struct mvneta_port *pp, int phy_mode) 5043 { 5044 /* MAC Cause register should be cleared */ 5045 mvreg_write(pp, MVNETA_UNIT_INTR_CAUSE, 0); 5046 5047 if (phy_mode != PHY_INTERFACE_MODE_QSGMII && 5048 phy_mode != PHY_INTERFACE_MODE_SGMII && 5049 !phy_interface_mode_is_8023z(phy_mode) && 5050 !phy_interface_mode_is_rgmii(phy_mode)) 5051 return -EINVAL; 5052 5053 return 0; 5054 } 5055 5056 /* Device initialization routine */ 5057 static int mvneta_probe(struct platform_device *pdev) 5058 { 5059 struct device_node *dn = pdev->dev.of_node; 5060 struct device_node *bm_node; 5061 struct mvneta_port *pp; 5062 struct net_device *dev; 5063 struct phylink *phylink; 5064 struct phy *comphy; 5065 const char *dt_mac_addr; 5066 char hw_mac_addr[ETH_ALEN]; 5067 phy_interface_t phy_mode; 5068 const char *mac_from; 5069 int tx_csum_limit; 5070 int err; 5071 int cpu; 5072 5073 dev = devm_alloc_etherdev_mqs(&pdev->dev, sizeof(struct mvneta_port), 5074 txq_number, rxq_number); 5075 if (!dev) 5076 return -ENOMEM; 5077 5078 dev->irq = irq_of_parse_and_map(dn, 0); 5079 if (dev->irq == 0) 5080 return -EINVAL; 5081 5082 err = of_get_phy_mode(dn, &phy_mode); 5083 if (err) { 5084 dev_err(&pdev->dev, "incorrect phy-mode\n"); 5085 goto err_free_irq; 5086 } 5087 5088 comphy = devm_of_phy_get(&pdev->dev, dn, NULL); 5089 if (comphy == ERR_PTR(-EPROBE_DEFER)) { 5090 err = -EPROBE_DEFER; 5091 goto err_free_irq; 5092 } else if (IS_ERR(comphy)) { 5093 comphy = NULL; 5094 } 5095 5096 pp = netdev_priv(dev); 5097 spin_lock_init(&pp->lock); 5098 5099 pp->phylink_config.dev = &dev->dev; 5100 pp->phylink_config.type = PHYLINK_NETDEV; 5101 5102 phylink = phylink_create(&pp->phylink_config, pdev->dev.fwnode, 5103 phy_mode, &mvneta_phylink_ops); 5104 if (IS_ERR(phylink)) { 5105 err = PTR_ERR(phylink); 5106 goto err_free_irq; 5107 } 5108 5109 dev->tx_queue_len = MVNETA_MAX_TXD; 5110 dev->watchdog_timeo = 5 * HZ; 5111 dev->netdev_ops = &mvneta_netdev_ops; 5112 5113 dev->ethtool_ops = &mvneta_eth_tool_ops; 5114 5115 pp->phylink = phylink; 5116 pp->comphy = comphy; 5117 pp->phy_interface = phy_mode; 5118 pp->dn = dn; 5119 5120 pp->rxq_def = rxq_def; 5121 pp->indir[0] = rxq_def; 5122 5123 /* Get special SoC configurations */ 5124 if (of_device_is_compatible(dn, "marvell,armada-3700-neta")) 5125 pp->neta_armada3700 = true; 5126 5127 pp->clk = devm_clk_get(&pdev->dev, "core"); 5128 if (IS_ERR(pp->clk)) 5129 pp->clk = devm_clk_get(&pdev->dev, NULL); 5130 if (IS_ERR(pp->clk)) { 5131 err = PTR_ERR(pp->clk); 5132 goto err_free_phylink; 5133 } 5134 5135 clk_prepare_enable(pp->clk); 5136 5137 pp->clk_bus = devm_clk_get(&pdev->dev, "bus"); 5138 if (!IS_ERR(pp->clk_bus)) 5139 clk_prepare_enable(pp->clk_bus); 5140 5141 pp->base = devm_platform_ioremap_resource(pdev, 0); 5142 if (IS_ERR(pp->base)) { 5143 err = PTR_ERR(pp->base); 5144 goto err_clk; 5145 } 5146 5147 /* Alloc per-cpu port structure */ 5148 pp->ports = alloc_percpu(struct mvneta_pcpu_port); 5149 if (!pp->ports) { 5150 err = -ENOMEM; 5151 goto err_clk; 5152 } 5153 5154 /* Alloc per-cpu stats */ 5155 pp->stats = netdev_alloc_pcpu_stats(struct mvneta_pcpu_stats); 5156 if (!pp->stats) { 5157 err = -ENOMEM; 5158 goto err_free_ports; 5159 } 5160 5161 dt_mac_addr = of_get_mac_address(dn); 5162 if (!IS_ERR(dt_mac_addr)) { 5163 mac_from = "device tree"; 5164 ether_addr_copy(dev->dev_addr, dt_mac_addr); 5165 } else { 5166 mvneta_get_mac_addr(pp, hw_mac_addr); 5167 if (is_valid_ether_addr(hw_mac_addr)) { 5168 mac_from = "hardware"; 5169 memcpy(dev->dev_addr, hw_mac_addr, ETH_ALEN); 5170 } else { 5171 mac_from = "random"; 5172 eth_hw_addr_random(dev); 5173 } 5174 } 5175 5176 if (!of_property_read_u32(dn, "tx-csum-limit", &tx_csum_limit)) { 5177 if (tx_csum_limit < 0 || 5178 tx_csum_limit > MVNETA_TX_CSUM_MAX_SIZE) { 5179 tx_csum_limit = MVNETA_TX_CSUM_DEF_SIZE; 5180 dev_info(&pdev->dev, 5181 "Wrong TX csum limit in DT, set to %dB\n", 5182 MVNETA_TX_CSUM_DEF_SIZE); 5183 } 5184 } else if (of_device_is_compatible(dn, "marvell,armada-370-neta")) { 5185 tx_csum_limit = MVNETA_TX_CSUM_DEF_SIZE; 5186 } else { 5187 tx_csum_limit = MVNETA_TX_CSUM_MAX_SIZE; 5188 } 5189 5190 pp->tx_csum_limit = tx_csum_limit; 5191 5192 pp->dram_target_info = mv_mbus_dram_info(); 5193 /* Armada3700 requires setting default configuration of Mbus 5194 * windows, however without using filled mbus_dram_target_info 5195 * structure. 5196 */ 5197 if (pp->dram_target_info || pp->neta_armada3700) 5198 mvneta_conf_mbus_windows(pp, pp->dram_target_info); 5199 5200 pp->tx_ring_size = MVNETA_MAX_TXD; 5201 pp->rx_ring_size = MVNETA_MAX_RXD; 5202 5203 pp->dev = dev; 5204 SET_NETDEV_DEV(dev, &pdev->dev); 5205 5206 pp->id = global_port_id++; 5207 5208 /* Obtain access to BM resources if enabled and already initialized */ 5209 bm_node = of_parse_phandle(dn, "buffer-manager", 0); 5210 if (bm_node) { 5211 pp->bm_priv = mvneta_bm_get(bm_node); 5212 if (pp->bm_priv) { 5213 err = mvneta_bm_port_init(pdev, pp); 5214 if (err < 0) { 5215 dev_info(&pdev->dev, 5216 "use SW buffer management\n"); 5217 mvneta_bm_put(pp->bm_priv); 5218 pp->bm_priv = NULL; 5219 } 5220 } 5221 /* Set RX packet offset correction for platforms, whose 5222 * NET_SKB_PAD, exceeds 64B. It should be 64B for 64-bit 5223 * platforms and 0B for 32-bit ones. 5224 */ 5225 pp->rx_offset_correction = max(0, 5226 NET_SKB_PAD - 5227 MVNETA_RX_PKT_OFFSET_CORRECTION); 5228 } 5229 of_node_put(bm_node); 5230 5231 /* sw buffer management */ 5232 if (!pp->bm_priv) 5233 pp->rx_offset_correction = MVNETA_SKB_HEADROOM; 5234 5235 err = mvneta_init(&pdev->dev, pp); 5236 if (err < 0) 5237 goto err_netdev; 5238 5239 err = mvneta_port_power_up(pp, pp->phy_interface); 5240 if (err < 0) { 5241 dev_err(&pdev->dev, "can't power up port\n"); 5242 return err; 5243 } 5244 5245 /* Armada3700 network controller does not support per-cpu 5246 * operation, so only single NAPI should be initialized. 5247 */ 5248 if (pp->neta_armada3700) { 5249 netif_napi_add(dev, &pp->napi, mvneta_poll, NAPI_POLL_WEIGHT); 5250 } else { 5251 for_each_present_cpu(cpu) { 5252 struct mvneta_pcpu_port *port = 5253 per_cpu_ptr(pp->ports, cpu); 5254 5255 netif_napi_add(dev, &port->napi, mvneta_poll, 5256 NAPI_POLL_WEIGHT); 5257 port->pp = pp; 5258 } 5259 } 5260 5261 dev->features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | 5262 NETIF_F_TSO | NETIF_F_RXCSUM; 5263 dev->hw_features |= dev->features; 5264 dev->vlan_features |= dev->features; 5265 dev->priv_flags |= IFF_LIVE_ADDR_CHANGE; 5266 dev->gso_max_segs = MVNETA_MAX_TSO_SEGS; 5267 5268 /* MTU range: 68 - 9676 */ 5269 dev->min_mtu = ETH_MIN_MTU; 5270 /* 9676 == 9700 - 20 and rounding to 8 */ 5271 dev->max_mtu = 9676; 5272 5273 err = register_netdev(dev); 5274 if (err < 0) { 5275 dev_err(&pdev->dev, "failed to register\n"); 5276 goto err_netdev; 5277 } 5278 5279 netdev_info(dev, "Using %s mac address %pM\n", mac_from, 5280 dev->dev_addr); 5281 5282 platform_set_drvdata(pdev, pp->dev); 5283 5284 return 0; 5285 5286 err_netdev: 5287 if (pp->bm_priv) { 5288 mvneta_bm_pool_destroy(pp->bm_priv, pp->pool_long, 1 << pp->id); 5289 mvneta_bm_pool_destroy(pp->bm_priv, pp->pool_short, 5290 1 << pp->id); 5291 mvneta_bm_put(pp->bm_priv); 5292 } 5293 free_percpu(pp->stats); 5294 err_free_ports: 5295 free_percpu(pp->ports); 5296 err_clk: 5297 clk_disable_unprepare(pp->clk_bus); 5298 clk_disable_unprepare(pp->clk); 5299 err_free_phylink: 5300 if (pp->phylink) 5301 phylink_destroy(pp->phylink); 5302 err_free_irq: 5303 irq_dispose_mapping(dev->irq); 5304 return err; 5305 } 5306 5307 /* Device removal routine */ 5308 static int mvneta_remove(struct platform_device *pdev) 5309 { 5310 struct net_device *dev = platform_get_drvdata(pdev); 5311 struct mvneta_port *pp = netdev_priv(dev); 5312 5313 unregister_netdev(dev); 5314 clk_disable_unprepare(pp->clk_bus); 5315 clk_disable_unprepare(pp->clk); 5316 free_percpu(pp->ports); 5317 free_percpu(pp->stats); 5318 irq_dispose_mapping(dev->irq); 5319 phylink_destroy(pp->phylink); 5320 5321 if (pp->bm_priv) { 5322 mvneta_bm_pool_destroy(pp->bm_priv, pp->pool_long, 1 << pp->id); 5323 mvneta_bm_pool_destroy(pp->bm_priv, pp->pool_short, 5324 1 << pp->id); 5325 mvneta_bm_put(pp->bm_priv); 5326 } 5327 5328 return 0; 5329 } 5330 5331 #ifdef CONFIG_PM_SLEEP 5332 static int mvneta_suspend(struct device *device) 5333 { 5334 int queue; 5335 struct net_device *dev = dev_get_drvdata(device); 5336 struct mvneta_port *pp = netdev_priv(dev); 5337 5338 if (!netif_running(dev)) 5339 goto clean_exit; 5340 5341 if (!pp->neta_armada3700) { 5342 spin_lock(&pp->lock); 5343 pp->is_stopped = true; 5344 spin_unlock(&pp->lock); 5345 5346 cpuhp_state_remove_instance_nocalls(online_hpstate, 5347 &pp->node_online); 5348 cpuhp_state_remove_instance_nocalls(CPUHP_NET_MVNETA_DEAD, 5349 &pp->node_dead); 5350 } 5351 5352 rtnl_lock(); 5353 mvneta_stop_dev(pp); 5354 rtnl_unlock(); 5355 5356 for (queue = 0; queue < rxq_number; queue++) { 5357 struct mvneta_rx_queue *rxq = &pp->rxqs[queue]; 5358 5359 mvneta_rxq_drop_pkts(pp, rxq); 5360 } 5361 5362 for (queue = 0; queue < txq_number; queue++) { 5363 struct mvneta_tx_queue *txq = &pp->txqs[queue]; 5364 5365 mvneta_txq_hw_deinit(pp, txq); 5366 } 5367 5368 clean_exit: 5369 netif_device_detach(dev); 5370 clk_disable_unprepare(pp->clk_bus); 5371 clk_disable_unprepare(pp->clk); 5372 5373 return 0; 5374 } 5375 5376 static int mvneta_resume(struct device *device) 5377 { 5378 struct platform_device *pdev = to_platform_device(device); 5379 struct net_device *dev = dev_get_drvdata(device); 5380 struct mvneta_port *pp = netdev_priv(dev); 5381 int err, queue; 5382 5383 clk_prepare_enable(pp->clk); 5384 if (!IS_ERR(pp->clk_bus)) 5385 clk_prepare_enable(pp->clk_bus); 5386 if (pp->dram_target_info || pp->neta_armada3700) 5387 mvneta_conf_mbus_windows(pp, pp->dram_target_info); 5388 if (pp->bm_priv) { 5389 err = mvneta_bm_port_init(pdev, pp); 5390 if (err < 0) { 5391 dev_info(&pdev->dev, "use SW buffer management\n"); 5392 pp->rx_offset_correction = MVNETA_SKB_HEADROOM; 5393 pp->bm_priv = NULL; 5394 } 5395 } 5396 mvneta_defaults_set(pp); 5397 err = mvneta_port_power_up(pp, pp->phy_interface); 5398 if (err < 0) { 5399 dev_err(device, "can't power up port\n"); 5400 return err; 5401 } 5402 5403 netif_device_attach(dev); 5404 5405 if (!netif_running(dev)) 5406 return 0; 5407 5408 for (queue = 0; queue < rxq_number; queue++) { 5409 struct mvneta_rx_queue *rxq = &pp->rxqs[queue]; 5410 5411 rxq->next_desc_to_proc = 0; 5412 mvneta_rxq_hw_init(pp, rxq); 5413 } 5414 5415 for (queue = 0; queue < txq_number; queue++) { 5416 struct mvneta_tx_queue *txq = &pp->txqs[queue]; 5417 5418 txq->next_desc_to_proc = 0; 5419 mvneta_txq_hw_init(pp, txq); 5420 } 5421 5422 if (!pp->neta_armada3700) { 5423 spin_lock(&pp->lock); 5424 pp->is_stopped = false; 5425 spin_unlock(&pp->lock); 5426 cpuhp_state_add_instance_nocalls(online_hpstate, 5427 &pp->node_online); 5428 cpuhp_state_add_instance_nocalls(CPUHP_NET_MVNETA_DEAD, 5429 &pp->node_dead); 5430 } 5431 5432 rtnl_lock(); 5433 mvneta_start_dev(pp); 5434 rtnl_unlock(); 5435 mvneta_set_rx_mode(dev); 5436 5437 return 0; 5438 } 5439 #endif 5440 5441 static SIMPLE_DEV_PM_OPS(mvneta_pm_ops, mvneta_suspend, mvneta_resume); 5442 5443 static const struct of_device_id mvneta_match[] = { 5444 { .compatible = "marvell,armada-370-neta" }, 5445 { .compatible = "marvell,armada-xp-neta" }, 5446 { .compatible = "marvell,armada-3700-neta" }, 5447 { } 5448 }; 5449 MODULE_DEVICE_TABLE(of, mvneta_match); 5450 5451 static struct platform_driver mvneta_driver = { 5452 .probe = mvneta_probe, 5453 .remove = mvneta_remove, 5454 .driver = { 5455 .name = MVNETA_DRIVER_NAME, 5456 .of_match_table = mvneta_match, 5457 .pm = &mvneta_pm_ops, 5458 }, 5459 }; 5460 5461 static int __init mvneta_driver_init(void) 5462 { 5463 int ret; 5464 5465 ret = cpuhp_setup_state_multi(CPUHP_AP_ONLINE_DYN, "net/mvneta:online", 5466 mvneta_cpu_online, 5467 mvneta_cpu_down_prepare); 5468 if (ret < 0) 5469 goto out; 5470 online_hpstate = ret; 5471 ret = cpuhp_setup_state_multi(CPUHP_NET_MVNETA_DEAD, "net/mvneta:dead", 5472 NULL, mvneta_cpu_dead); 5473 if (ret) 5474 goto err_dead; 5475 5476 ret = platform_driver_register(&mvneta_driver); 5477 if (ret) 5478 goto err; 5479 return 0; 5480 5481 err: 5482 cpuhp_remove_multi_state(CPUHP_NET_MVNETA_DEAD); 5483 err_dead: 5484 cpuhp_remove_multi_state(online_hpstate); 5485 out: 5486 return ret; 5487 } 5488 module_init(mvneta_driver_init); 5489 5490 static void __exit mvneta_driver_exit(void) 5491 { 5492 platform_driver_unregister(&mvneta_driver); 5493 cpuhp_remove_multi_state(CPUHP_NET_MVNETA_DEAD); 5494 cpuhp_remove_multi_state(online_hpstate); 5495 } 5496 module_exit(mvneta_driver_exit); 5497 5498 MODULE_DESCRIPTION("Marvell NETA Ethernet Driver - www.marvell.com"); 5499 MODULE_AUTHOR("Rami Rosen <rosenr@marvell.com>, Thomas Petazzoni <thomas.petazzoni@free-electrons.com>"); 5500 MODULE_LICENSE("GPL"); 5501 5502 module_param(rxq_number, int, 0444); 5503 module_param(txq_number, int, 0444); 5504 5505 module_param(rxq_def, int, 0444); 5506 module_param(rx_copybreak, int, 0644); 5507