1 /* 2 * Driver for Marvell NETA network card for Armada XP and Armada 370 SoCs. 3 * 4 * Copyright (C) 2012 Marvell 5 * 6 * Rami Rosen <rosenr@marvell.com> 7 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> 8 * 9 * This file is licensed under the terms of the GNU General Public 10 * License version 2. This program is licensed "as is" without any 11 * warranty of any kind, whether express or implied. 12 */ 13 14 #include <linux/clk.h> 15 #include <linux/cpu.h> 16 #include <linux/etherdevice.h> 17 #include <linux/if_vlan.h> 18 #include <linux/inetdevice.h> 19 #include <linux/interrupt.h> 20 #include <linux/io.h> 21 #include <linux/kernel.h> 22 #include <linux/mbus.h> 23 #include <linux/module.h> 24 #include <linux/netdevice.h> 25 #include <linux/of.h> 26 #include <linux/of_address.h> 27 #include <linux/of_irq.h> 28 #include <linux/of_mdio.h> 29 #include <linux/of_net.h> 30 #include <linux/phy/phy.h> 31 #include <linux/phy.h> 32 #include <linux/phylink.h> 33 #include <linux/platform_device.h> 34 #include <linux/skbuff.h> 35 #include <net/hwbm.h> 36 #include "mvneta_bm.h" 37 #include <net/ip.h> 38 #include <net/ipv6.h> 39 #include <net/tso.h> 40 #include <net/page_pool.h> 41 #include <linux/bpf_trace.h> 42 43 /* Registers */ 44 #define MVNETA_RXQ_CONFIG_REG(q) (0x1400 + ((q) << 2)) 45 #define MVNETA_RXQ_HW_BUF_ALLOC BIT(0) 46 #define MVNETA_RXQ_SHORT_POOL_ID_SHIFT 4 47 #define MVNETA_RXQ_SHORT_POOL_ID_MASK 0x30 48 #define MVNETA_RXQ_LONG_POOL_ID_SHIFT 6 49 #define MVNETA_RXQ_LONG_POOL_ID_MASK 0xc0 50 #define MVNETA_RXQ_PKT_OFFSET_ALL_MASK (0xf << 8) 51 #define MVNETA_RXQ_PKT_OFFSET_MASK(offs) ((offs) << 8) 52 #define MVNETA_RXQ_THRESHOLD_REG(q) (0x14c0 + ((q) << 2)) 53 #define MVNETA_RXQ_NON_OCCUPIED(v) ((v) << 16) 54 #define MVNETA_RXQ_BASE_ADDR_REG(q) (0x1480 + ((q) << 2)) 55 #define MVNETA_RXQ_SIZE_REG(q) (0x14a0 + ((q) << 2)) 56 #define MVNETA_RXQ_BUF_SIZE_SHIFT 19 57 #define MVNETA_RXQ_BUF_SIZE_MASK (0x1fff << 19) 58 #define MVNETA_RXQ_STATUS_REG(q) (0x14e0 + ((q) << 2)) 59 #define MVNETA_RXQ_OCCUPIED_ALL_MASK 0x3fff 60 #define MVNETA_RXQ_STATUS_UPDATE_REG(q) (0x1500 + ((q) << 2)) 61 #define MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT 16 62 #define MVNETA_RXQ_ADD_NON_OCCUPIED_MAX 255 63 #define MVNETA_PORT_POOL_BUFFER_SZ_REG(pool) (0x1700 + ((pool) << 2)) 64 #define MVNETA_PORT_POOL_BUFFER_SZ_SHIFT 3 65 #define MVNETA_PORT_POOL_BUFFER_SZ_MASK 0xfff8 66 #define MVNETA_PORT_RX_RESET 0x1cc0 67 #define MVNETA_PORT_RX_DMA_RESET BIT(0) 68 #define MVNETA_PHY_ADDR 0x2000 69 #define MVNETA_PHY_ADDR_MASK 0x1f 70 #define MVNETA_MBUS_RETRY 0x2010 71 #define MVNETA_UNIT_INTR_CAUSE 0x2080 72 #define MVNETA_UNIT_CONTROL 0x20B0 73 #define MVNETA_PHY_POLLING_ENABLE BIT(1) 74 #define MVNETA_WIN_BASE(w) (0x2200 + ((w) << 3)) 75 #define MVNETA_WIN_SIZE(w) (0x2204 + ((w) << 3)) 76 #define MVNETA_WIN_REMAP(w) (0x2280 + ((w) << 2)) 77 #define MVNETA_BASE_ADDR_ENABLE 0x2290 78 #define MVNETA_ACCESS_PROTECT_ENABLE 0x2294 79 #define MVNETA_PORT_CONFIG 0x2400 80 #define MVNETA_UNI_PROMISC_MODE BIT(0) 81 #define MVNETA_DEF_RXQ(q) ((q) << 1) 82 #define MVNETA_DEF_RXQ_ARP(q) ((q) << 4) 83 #define MVNETA_TX_UNSET_ERR_SUM BIT(12) 84 #define MVNETA_DEF_RXQ_TCP(q) ((q) << 16) 85 #define MVNETA_DEF_RXQ_UDP(q) ((q) << 19) 86 #define MVNETA_DEF_RXQ_BPDU(q) ((q) << 22) 87 #define MVNETA_RX_CSUM_WITH_PSEUDO_HDR BIT(25) 88 #define MVNETA_PORT_CONFIG_DEFL_VALUE(q) (MVNETA_DEF_RXQ(q) | \ 89 MVNETA_DEF_RXQ_ARP(q) | \ 90 MVNETA_DEF_RXQ_TCP(q) | \ 91 MVNETA_DEF_RXQ_UDP(q) | \ 92 MVNETA_DEF_RXQ_BPDU(q) | \ 93 MVNETA_TX_UNSET_ERR_SUM | \ 94 MVNETA_RX_CSUM_WITH_PSEUDO_HDR) 95 #define MVNETA_PORT_CONFIG_EXTEND 0x2404 96 #define MVNETA_MAC_ADDR_LOW 0x2414 97 #define MVNETA_MAC_ADDR_HIGH 0x2418 98 #define MVNETA_SDMA_CONFIG 0x241c 99 #define MVNETA_SDMA_BRST_SIZE_16 4 100 #define MVNETA_RX_BRST_SZ_MASK(burst) ((burst) << 1) 101 #define MVNETA_RX_NO_DATA_SWAP BIT(4) 102 #define MVNETA_TX_NO_DATA_SWAP BIT(5) 103 #define MVNETA_DESC_SWAP BIT(6) 104 #define MVNETA_TX_BRST_SZ_MASK(burst) ((burst) << 22) 105 #define MVNETA_PORT_STATUS 0x2444 106 #define MVNETA_TX_IN_PRGRS BIT(1) 107 #define MVNETA_TX_FIFO_EMPTY BIT(8) 108 #define MVNETA_RX_MIN_FRAME_SIZE 0x247c 109 /* Only exists on Armada XP and Armada 370 */ 110 #define MVNETA_SERDES_CFG 0x24A0 111 #define MVNETA_SGMII_SERDES_PROTO 0x0cc7 112 #define MVNETA_QSGMII_SERDES_PROTO 0x0667 113 #define MVNETA_HSGMII_SERDES_PROTO 0x1107 114 #define MVNETA_TYPE_PRIO 0x24bc 115 #define MVNETA_FORCE_UNI BIT(21) 116 #define MVNETA_TXQ_CMD_1 0x24e4 117 #define MVNETA_TXQ_CMD 0x2448 118 #define MVNETA_TXQ_DISABLE_SHIFT 8 119 #define MVNETA_TXQ_ENABLE_MASK 0x000000ff 120 #define MVNETA_RX_DISCARD_FRAME_COUNT 0x2484 121 #define MVNETA_OVERRUN_FRAME_COUNT 0x2488 122 #define MVNETA_GMAC_CLOCK_DIVIDER 0x24f4 123 #define MVNETA_GMAC_1MS_CLOCK_ENABLE BIT(31) 124 #define MVNETA_ACC_MODE 0x2500 125 #define MVNETA_BM_ADDRESS 0x2504 126 #define MVNETA_CPU_MAP(cpu) (0x2540 + ((cpu) << 2)) 127 #define MVNETA_CPU_RXQ_ACCESS_ALL_MASK 0x000000ff 128 #define MVNETA_CPU_TXQ_ACCESS_ALL_MASK 0x0000ff00 129 #define MVNETA_CPU_RXQ_ACCESS(rxq) BIT(rxq) 130 #define MVNETA_CPU_TXQ_ACCESS(txq) BIT(txq + 8) 131 #define MVNETA_RXQ_TIME_COAL_REG(q) (0x2580 + ((q) << 2)) 132 133 /* Exception Interrupt Port/Queue Cause register 134 * 135 * Their behavior depend of the mapping done using the PCPX2Q 136 * registers. For a given CPU if the bit associated to a queue is not 137 * set, then for the register a read from this CPU will always return 138 * 0 and a write won't do anything 139 */ 140 141 #define MVNETA_INTR_NEW_CAUSE 0x25a0 142 #define MVNETA_INTR_NEW_MASK 0x25a4 143 144 /* bits 0..7 = TXQ SENT, one bit per queue. 145 * bits 8..15 = RXQ OCCUP, one bit per queue. 146 * bits 16..23 = RXQ FREE, one bit per queue. 147 * bit 29 = OLD_REG_SUM, see old reg ? 148 * bit 30 = TX_ERR_SUM, one bit for 4 ports 149 * bit 31 = MISC_SUM, one bit for 4 ports 150 */ 151 #define MVNETA_TX_INTR_MASK(nr_txqs) (((1 << nr_txqs) - 1) << 0) 152 #define MVNETA_TX_INTR_MASK_ALL (0xff << 0) 153 #define MVNETA_RX_INTR_MASK(nr_rxqs) (((1 << nr_rxqs) - 1) << 8) 154 #define MVNETA_RX_INTR_MASK_ALL (0xff << 8) 155 #define MVNETA_MISCINTR_INTR_MASK BIT(31) 156 157 #define MVNETA_INTR_OLD_CAUSE 0x25a8 158 #define MVNETA_INTR_OLD_MASK 0x25ac 159 160 /* Data Path Port/Queue Cause Register */ 161 #define MVNETA_INTR_MISC_CAUSE 0x25b0 162 #define MVNETA_INTR_MISC_MASK 0x25b4 163 164 #define MVNETA_CAUSE_PHY_STATUS_CHANGE BIT(0) 165 #define MVNETA_CAUSE_LINK_CHANGE BIT(1) 166 #define MVNETA_CAUSE_PTP BIT(4) 167 168 #define MVNETA_CAUSE_INTERNAL_ADDR_ERR BIT(7) 169 #define MVNETA_CAUSE_RX_OVERRUN BIT(8) 170 #define MVNETA_CAUSE_RX_CRC_ERROR BIT(9) 171 #define MVNETA_CAUSE_RX_LARGE_PKT BIT(10) 172 #define MVNETA_CAUSE_TX_UNDERUN BIT(11) 173 #define MVNETA_CAUSE_PRBS_ERR BIT(12) 174 #define MVNETA_CAUSE_PSC_SYNC_CHANGE BIT(13) 175 #define MVNETA_CAUSE_SERDES_SYNC_ERR BIT(14) 176 177 #define MVNETA_CAUSE_BMU_ALLOC_ERR_SHIFT 16 178 #define MVNETA_CAUSE_BMU_ALLOC_ERR_ALL_MASK (0xF << MVNETA_CAUSE_BMU_ALLOC_ERR_SHIFT) 179 #define MVNETA_CAUSE_BMU_ALLOC_ERR_MASK(pool) (1 << (MVNETA_CAUSE_BMU_ALLOC_ERR_SHIFT + (pool))) 180 181 #define MVNETA_CAUSE_TXQ_ERROR_SHIFT 24 182 #define MVNETA_CAUSE_TXQ_ERROR_ALL_MASK (0xFF << MVNETA_CAUSE_TXQ_ERROR_SHIFT) 183 #define MVNETA_CAUSE_TXQ_ERROR_MASK(q) (1 << (MVNETA_CAUSE_TXQ_ERROR_SHIFT + (q))) 184 185 #define MVNETA_INTR_ENABLE 0x25b8 186 #define MVNETA_TXQ_INTR_ENABLE_ALL_MASK 0x0000ff00 187 #define MVNETA_RXQ_INTR_ENABLE_ALL_MASK 0x000000ff 188 189 #define MVNETA_RXQ_CMD 0x2680 190 #define MVNETA_RXQ_DISABLE_SHIFT 8 191 #define MVNETA_RXQ_ENABLE_MASK 0x000000ff 192 #define MVETH_TXQ_TOKEN_COUNT_REG(q) (0x2700 + ((q) << 4)) 193 #define MVETH_TXQ_TOKEN_CFG_REG(q) (0x2704 + ((q) << 4)) 194 #define MVNETA_GMAC_CTRL_0 0x2c00 195 #define MVNETA_GMAC_MAX_RX_SIZE_SHIFT 2 196 #define MVNETA_GMAC_MAX_RX_SIZE_MASK 0x7ffc 197 #define MVNETA_GMAC0_PORT_1000BASE_X BIT(1) 198 #define MVNETA_GMAC0_PORT_ENABLE BIT(0) 199 #define MVNETA_GMAC_CTRL_2 0x2c08 200 #define MVNETA_GMAC2_INBAND_AN_ENABLE BIT(0) 201 #define MVNETA_GMAC2_PCS_ENABLE BIT(3) 202 #define MVNETA_GMAC2_PORT_RGMII BIT(4) 203 #define MVNETA_GMAC2_PORT_RESET BIT(6) 204 #define MVNETA_GMAC_STATUS 0x2c10 205 #define MVNETA_GMAC_LINK_UP BIT(0) 206 #define MVNETA_GMAC_SPEED_1000 BIT(1) 207 #define MVNETA_GMAC_SPEED_100 BIT(2) 208 #define MVNETA_GMAC_FULL_DUPLEX BIT(3) 209 #define MVNETA_GMAC_RX_FLOW_CTRL_ENABLE BIT(4) 210 #define MVNETA_GMAC_TX_FLOW_CTRL_ENABLE BIT(5) 211 #define MVNETA_GMAC_RX_FLOW_CTRL_ACTIVE BIT(6) 212 #define MVNETA_GMAC_TX_FLOW_CTRL_ACTIVE BIT(7) 213 #define MVNETA_GMAC_AN_COMPLETE BIT(11) 214 #define MVNETA_GMAC_SYNC_OK BIT(14) 215 #define MVNETA_GMAC_AUTONEG_CONFIG 0x2c0c 216 #define MVNETA_GMAC_FORCE_LINK_DOWN BIT(0) 217 #define MVNETA_GMAC_FORCE_LINK_PASS BIT(1) 218 #define MVNETA_GMAC_INBAND_AN_ENABLE BIT(2) 219 #define MVNETA_GMAC_AN_BYPASS_ENABLE BIT(3) 220 #define MVNETA_GMAC_INBAND_RESTART_AN BIT(4) 221 #define MVNETA_GMAC_CONFIG_MII_SPEED BIT(5) 222 #define MVNETA_GMAC_CONFIG_GMII_SPEED BIT(6) 223 #define MVNETA_GMAC_AN_SPEED_EN BIT(7) 224 #define MVNETA_GMAC_CONFIG_FLOW_CTRL BIT(8) 225 #define MVNETA_GMAC_ADVERT_SYM_FLOW_CTRL BIT(9) 226 #define MVNETA_GMAC_AN_FLOW_CTRL_EN BIT(11) 227 #define MVNETA_GMAC_CONFIG_FULL_DUPLEX BIT(12) 228 #define MVNETA_GMAC_AN_DUPLEX_EN BIT(13) 229 #define MVNETA_GMAC_CTRL_4 0x2c90 230 #define MVNETA_GMAC4_SHORT_PREAMBLE_ENABLE BIT(1) 231 #define MVNETA_MIB_COUNTERS_BASE 0x3000 232 #define MVNETA_MIB_LATE_COLLISION 0x7c 233 #define MVNETA_DA_FILT_SPEC_MCAST 0x3400 234 #define MVNETA_DA_FILT_OTH_MCAST 0x3500 235 #define MVNETA_DA_FILT_UCAST_BASE 0x3600 236 #define MVNETA_TXQ_BASE_ADDR_REG(q) (0x3c00 + ((q) << 2)) 237 #define MVNETA_TXQ_SIZE_REG(q) (0x3c20 + ((q) << 2)) 238 #define MVNETA_TXQ_SENT_THRESH_ALL_MASK 0x3fff0000 239 #define MVNETA_TXQ_SENT_THRESH_MASK(coal) ((coal) << 16) 240 #define MVNETA_TXQ_UPDATE_REG(q) (0x3c60 + ((q) << 2)) 241 #define MVNETA_TXQ_DEC_SENT_SHIFT 16 242 #define MVNETA_TXQ_DEC_SENT_MASK 0xff 243 #define MVNETA_TXQ_STATUS_REG(q) (0x3c40 + ((q) << 2)) 244 #define MVNETA_TXQ_SENT_DESC_SHIFT 16 245 #define MVNETA_TXQ_SENT_DESC_MASK 0x3fff0000 246 #define MVNETA_PORT_TX_RESET 0x3cf0 247 #define MVNETA_PORT_TX_DMA_RESET BIT(0) 248 #define MVNETA_TX_MTU 0x3e0c 249 #define MVNETA_TX_TOKEN_SIZE 0x3e14 250 #define MVNETA_TX_TOKEN_SIZE_MAX 0xffffffff 251 #define MVNETA_TXQ_TOKEN_SIZE_REG(q) (0x3e40 + ((q) << 2)) 252 #define MVNETA_TXQ_TOKEN_SIZE_MAX 0x7fffffff 253 254 #define MVNETA_LPI_CTRL_0 0x2cc0 255 #define MVNETA_LPI_CTRL_1 0x2cc4 256 #define MVNETA_LPI_REQUEST_ENABLE BIT(0) 257 #define MVNETA_LPI_CTRL_2 0x2cc8 258 #define MVNETA_LPI_STATUS 0x2ccc 259 260 #define MVNETA_CAUSE_TXQ_SENT_DESC_ALL_MASK 0xff 261 262 /* Descriptor ring Macros */ 263 #define MVNETA_QUEUE_NEXT_DESC(q, index) \ 264 (((index) < (q)->last_desc) ? ((index) + 1) : 0) 265 266 /* Various constants */ 267 268 /* Coalescing */ 269 #define MVNETA_TXDONE_COAL_PKTS 0 /* interrupt per packet */ 270 #define MVNETA_RX_COAL_PKTS 32 271 #define MVNETA_RX_COAL_USEC 100 272 273 /* The two bytes Marvell header. Either contains a special value used 274 * by Marvell switches when a specific hardware mode is enabled (not 275 * supported by this driver) or is filled automatically by zeroes on 276 * the RX side. Those two bytes being at the front of the Ethernet 277 * header, they allow to have the IP header aligned on a 4 bytes 278 * boundary automatically: the hardware skips those two bytes on its 279 * own. 280 */ 281 #define MVNETA_MH_SIZE 2 282 283 #define MVNETA_VLAN_TAG_LEN 4 284 285 #define MVNETA_TX_CSUM_DEF_SIZE 1600 286 #define MVNETA_TX_CSUM_MAX_SIZE 9800 287 #define MVNETA_ACC_MODE_EXT1 1 288 #define MVNETA_ACC_MODE_EXT2 2 289 290 #define MVNETA_MAX_DECODE_WIN 6 291 292 /* Timeout constants */ 293 #define MVNETA_TX_DISABLE_TIMEOUT_MSEC 1000 294 #define MVNETA_RX_DISABLE_TIMEOUT_MSEC 1000 295 #define MVNETA_TX_FIFO_EMPTY_TIMEOUT 10000 296 297 #define MVNETA_TX_MTU_MAX 0x3ffff 298 299 /* The RSS lookup table actually has 256 entries but we do not use 300 * them yet 301 */ 302 #define MVNETA_RSS_LU_TABLE_SIZE 1 303 304 /* Max number of Rx descriptors */ 305 #define MVNETA_MAX_RXD 512 306 307 /* Max number of Tx descriptors */ 308 #define MVNETA_MAX_TXD 1024 309 310 /* Max number of allowed TCP segments for software TSO */ 311 #define MVNETA_MAX_TSO_SEGS 100 312 313 #define MVNETA_MAX_SKB_DESCS (MVNETA_MAX_TSO_SEGS * 2 + MAX_SKB_FRAGS) 314 315 /* descriptor aligned size */ 316 #define MVNETA_DESC_ALIGNED_SIZE 32 317 318 /* Number of bytes to be taken into account by HW when putting incoming data 319 * to the buffers. It is needed in case NET_SKB_PAD exceeds maximum packet 320 * offset supported in MVNETA_RXQ_CONFIG_REG(q) registers. 321 */ 322 #define MVNETA_RX_PKT_OFFSET_CORRECTION 64 323 324 #define MVNETA_RX_PKT_SIZE(mtu) \ 325 ALIGN((mtu) + MVNETA_MH_SIZE + MVNETA_VLAN_TAG_LEN + \ 326 ETH_HLEN + ETH_FCS_LEN, \ 327 cache_line_size()) 328 329 /* Driver assumes that the last 3 bits are 0 */ 330 #define MVNETA_SKB_HEADROOM ALIGN(max(NET_SKB_PAD, XDP_PACKET_HEADROOM), 8) 331 #define MVNETA_SKB_PAD (SKB_DATA_ALIGN(sizeof(struct skb_shared_info) + \ 332 MVNETA_SKB_HEADROOM)) 333 #define MVNETA_MAX_RX_BUF_SIZE (PAGE_SIZE - MVNETA_SKB_PAD) 334 335 #define IS_TSO_HEADER(txq, addr) \ 336 ((addr >= txq->tso_hdrs_phys) && \ 337 (addr < txq->tso_hdrs_phys + txq->size * TSO_HEADER_SIZE)) 338 339 #define MVNETA_RX_GET_BM_POOL_ID(rxd) \ 340 (((rxd)->status & MVNETA_RXD_BM_POOL_MASK) >> MVNETA_RXD_BM_POOL_SHIFT) 341 342 enum { 343 ETHTOOL_STAT_EEE_WAKEUP, 344 ETHTOOL_STAT_SKB_ALLOC_ERR, 345 ETHTOOL_STAT_REFILL_ERR, 346 ETHTOOL_XDP_REDIRECT, 347 ETHTOOL_XDP_PASS, 348 ETHTOOL_XDP_DROP, 349 ETHTOOL_XDP_TX, 350 ETHTOOL_XDP_TX_ERR, 351 ETHTOOL_XDP_XMIT, 352 ETHTOOL_XDP_XMIT_ERR, 353 ETHTOOL_MAX_STATS, 354 }; 355 356 struct mvneta_statistic { 357 unsigned short offset; 358 unsigned short type; 359 const char name[ETH_GSTRING_LEN]; 360 }; 361 362 #define T_REG_32 32 363 #define T_REG_64 64 364 #define T_SW 1 365 366 #define MVNETA_XDP_PASS 0 367 #define MVNETA_XDP_DROPPED BIT(0) 368 #define MVNETA_XDP_TX BIT(1) 369 #define MVNETA_XDP_REDIR BIT(2) 370 371 static const struct mvneta_statistic mvneta_statistics[] = { 372 { 0x3000, T_REG_64, "good_octets_received", }, 373 { 0x3010, T_REG_32, "good_frames_received", }, 374 { 0x3008, T_REG_32, "bad_octets_received", }, 375 { 0x3014, T_REG_32, "bad_frames_received", }, 376 { 0x3018, T_REG_32, "broadcast_frames_received", }, 377 { 0x301c, T_REG_32, "multicast_frames_received", }, 378 { 0x3050, T_REG_32, "unrec_mac_control_received", }, 379 { 0x3058, T_REG_32, "good_fc_received", }, 380 { 0x305c, T_REG_32, "bad_fc_received", }, 381 { 0x3060, T_REG_32, "undersize_received", }, 382 { 0x3064, T_REG_32, "fragments_received", }, 383 { 0x3068, T_REG_32, "oversize_received", }, 384 { 0x306c, T_REG_32, "jabber_received", }, 385 { 0x3070, T_REG_32, "mac_receive_error", }, 386 { 0x3074, T_REG_32, "bad_crc_event", }, 387 { 0x3078, T_REG_32, "collision", }, 388 { 0x307c, T_REG_32, "late_collision", }, 389 { 0x2484, T_REG_32, "rx_discard", }, 390 { 0x2488, T_REG_32, "rx_overrun", }, 391 { 0x3020, T_REG_32, "frames_64_octets", }, 392 { 0x3024, T_REG_32, "frames_65_to_127_octets", }, 393 { 0x3028, T_REG_32, "frames_128_to_255_octets", }, 394 { 0x302c, T_REG_32, "frames_256_to_511_octets", }, 395 { 0x3030, T_REG_32, "frames_512_to_1023_octets", }, 396 { 0x3034, T_REG_32, "frames_1024_to_max_octets", }, 397 { 0x3038, T_REG_64, "good_octets_sent", }, 398 { 0x3040, T_REG_32, "good_frames_sent", }, 399 { 0x3044, T_REG_32, "excessive_collision", }, 400 { 0x3048, T_REG_32, "multicast_frames_sent", }, 401 { 0x304c, T_REG_32, "broadcast_frames_sent", }, 402 { 0x3054, T_REG_32, "fc_sent", }, 403 { 0x300c, T_REG_32, "internal_mac_transmit_err", }, 404 { ETHTOOL_STAT_EEE_WAKEUP, T_SW, "eee_wakeup_errors", }, 405 { ETHTOOL_STAT_SKB_ALLOC_ERR, T_SW, "skb_alloc_errors", }, 406 { ETHTOOL_STAT_REFILL_ERR, T_SW, "refill_errors", }, 407 { ETHTOOL_XDP_REDIRECT, T_SW, "rx_xdp_redirect", }, 408 { ETHTOOL_XDP_PASS, T_SW, "rx_xdp_pass", }, 409 { ETHTOOL_XDP_DROP, T_SW, "rx_xdp_drop", }, 410 { ETHTOOL_XDP_TX, T_SW, "rx_xdp_tx", }, 411 { ETHTOOL_XDP_TX_ERR, T_SW, "rx_xdp_tx_errors", }, 412 { ETHTOOL_XDP_XMIT, T_SW, "tx_xdp_xmit", }, 413 { ETHTOOL_XDP_XMIT_ERR, T_SW, "tx_xdp_xmit_errors", }, 414 }; 415 416 struct mvneta_stats { 417 u64 rx_packets; 418 u64 rx_bytes; 419 u64 tx_packets; 420 u64 tx_bytes; 421 /* xdp */ 422 u64 xdp_redirect; 423 u64 xdp_pass; 424 u64 xdp_drop; 425 u64 xdp_xmit; 426 u64 xdp_xmit_err; 427 u64 xdp_tx; 428 u64 xdp_tx_err; 429 }; 430 431 struct mvneta_ethtool_stats { 432 struct mvneta_stats ps; 433 u64 skb_alloc_error; 434 u64 refill_error; 435 }; 436 437 struct mvneta_pcpu_stats { 438 struct u64_stats_sync syncp; 439 440 struct mvneta_ethtool_stats es; 441 u64 rx_dropped; 442 u64 rx_errors; 443 }; 444 445 struct mvneta_pcpu_port { 446 /* Pointer to the shared port */ 447 struct mvneta_port *pp; 448 449 /* Pointer to the CPU-local NAPI struct */ 450 struct napi_struct napi; 451 452 /* Cause of the previous interrupt */ 453 u32 cause_rx_tx; 454 }; 455 456 enum { 457 __MVNETA_DOWN, 458 }; 459 460 struct mvneta_port { 461 u8 id; 462 struct mvneta_pcpu_port __percpu *ports; 463 struct mvneta_pcpu_stats __percpu *stats; 464 465 unsigned long state; 466 467 int pkt_size; 468 void __iomem *base; 469 struct mvneta_rx_queue *rxqs; 470 struct mvneta_tx_queue *txqs; 471 struct net_device *dev; 472 struct hlist_node node_online; 473 struct hlist_node node_dead; 474 int rxq_def; 475 /* Protect the access to the percpu interrupt registers, 476 * ensuring that the configuration remains coherent. 477 */ 478 spinlock_t lock; 479 bool is_stopped; 480 481 u32 cause_rx_tx; 482 struct napi_struct napi; 483 484 struct bpf_prog *xdp_prog; 485 486 /* Core clock */ 487 struct clk *clk; 488 /* AXI clock */ 489 struct clk *clk_bus; 490 u8 mcast_count[256]; 491 u16 tx_ring_size; 492 u16 rx_ring_size; 493 494 phy_interface_t phy_interface; 495 struct device_node *dn; 496 unsigned int tx_csum_limit; 497 struct phylink *phylink; 498 struct phylink_config phylink_config; 499 struct phy *comphy; 500 501 struct mvneta_bm *bm_priv; 502 struct mvneta_bm_pool *pool_long; 503 struct mvneta_bm_pool *pool_short; 504 int bm_win_id; 505 506 bool eee_enabled; 507 bool eee_active; 508 bool tx_lpi_enabled; 509 510 u64 ethtool_stats[ARRAY_SIZE(mvneta_statistics)]; 511 512 u32 indir[MVNETA_RSS_LU_TABLE_SIZE]; 513 514 /* Flags for special SoC configurations */ 515 bool neta_armada3700; 516 u16 rx_offset_correction; 517 const struct mbus_dram_target_info *dram_target_info; 518 }; 519 520 /* The mvneta_tx_desc and mvneta_rx_desc structures describe the 521 * layout of the transmit and reception DMA descriptors, and their 522 * layout is therefore defined by the hardware design 523 */ 524 525 #define MVNETA_TX_L3_OFF_SHIFT 0 526 #define MVNETA_TX_IP_HLEN_SHIFT 8 527 #define MVNETA_TX_L4_UDP BIT(16) 528 #define MVNETA_TX_L3_IP6 BIT(17) 529 #define MVNETA_TXD_IP_CSUM BIT(18) 530 #define MVNETA_TXD_Z_PAD BIT(19) 531 #define MVNETA_TXD_L_DESC BIT(20) 532 #define MVNETA_TXD_F_DESC BIT(21) 533 #define MVNETA_TXD_FLZ_DESC (MVNETA_TXD_Z_PAD | \ 534 MVNETA_TXD_L_DESC | \ 535 MVNETA_TXD_F_DESC) 536 #define MVNETA_TX_L4_CSUM_FULL BIT(30) 537 #define MVNETA_TX_L4_CSUM_NOT BIT(31) 538 539 #define MVNETA_RXD_ERR_CRC 0x0 540 #define MVNETA_RXD_BM_POOL_SHIFT 13 541 #define MVNETA_RXD_BM_POOL_MASK (BIT(13) | BIT(14)) 542 #define MVNETA_RXD_ERR_SUMMARY BIT(16) 543 #define MVNETA_RXD_ERR_OVERRUN BIT(17) 544 #define MVNETA_RXD_ERR_LEN BIT(18) 545 #define MVNETA_RXD_ERR_RESOURCE (BIT(17) | BIT(18)) 546 #define MVNETA_RXD_ERR_CODE_MASK (BIT(17) | BIT(18)) 547 #define MVNETA_RXD_L3_IP4 BIT(25) 548 #define MVNETA_RXD_LAST_DESC BIT(26) 549 #define MVNETA_RXD_FIRST_DESC BIT(27) 550 #define MVNETA_RXD_FIRST_LAST_DESC (MVNETA_RXD_FIRST_DESC | \ 551 MVNETA_RXD_LAST_DESC) 552 #define MVNETA_RXD_L4_CSUM_OK BIT(30) 553 554 #if defined(__LITTLE_ENDIAN) 555 struct mvneta_tx_desc { 556 u32 command; /* Options used by HW for packet transmitting.*/ 557 u16 reserved1; /* csum_l4 (for future use) */ 558 u16 data_size; /* Data size of transmitted packet in bytes */ 559 u32 buf_phys_addr; /* Physical addr of transmitted buffer */ 560 u32 reserved2; /* hw_cmd - (for future use, PMT) */ 561 u32 reserved3[4]; /* Reserved - (for future use) */ 562 }; 563 564 struct mvneta_rx_desc { 565 u32 status; /* Info about received packet */ 566 u16 reserved1; /* pnc_info - (for future use, PnC) */ 567 u16 data_size; /* Size of received packet in bytes */ 568 569 u32 buf_phys_addr; /* Physical address of the buffer */ 570 u32 reserved2; /* pnc_flow_id (for future use, PnC) */ 571 572 u32 buf_cookie; /* cookie for access to RX buffer in rx path */ 573 u16 reserved3; /* prefetch_cmd, for future use */ 574 u16 reserved4; /* csum_l4 - (for future use, PnC) */ 575 576 u32 reserved5; /* pnc_extra PnC (for future use, PnC) */ 577 u32 reserved6; /* hw_cmd (for future use, PnC and HWF) */ 578 }; 579 #else 580 struct mvneta_tx_desc { 581 u16 data_size; /* Data size of transmitted packet in bytes */ 582 u16 reserved1; /* csum_l4 (for future use) */ 583 u32 command; /* Options used by HW for packet transmitting.*/ 584 u32 reserved2; /* hw_cmd - (for future use, PMT) */ 585 u32 buf_phys_addr; /* Physical addr of transmitted buffer */ 586 u32 reserved3[4]; /* Reserved - (for future use) */ 587 }; 588 589 struct mvneta_rx_desc { 590 u16 data_size; /* Size of received packet in bytes */ 591 u16 reserved1; /* pnc_info - (for future use, PnC) */ 592 u32 status; /* Info about received packet */ 593 594 u32 reserved2; /* pnc_flow_id (for future use, PnC) */ 595 u32 buf_phys_addr; /* Physical address of the buffer */ 596 597 u16 reserved4; /* csum_l4 - (for future use, PnC) */ 598 u16 reserved3; /* prefetch_cmd, for future use */ 599 u32 buf_cookie; /* cookie for access to RX buffer in rx path */ 600 601 u32 reserved5; /* pnc_extra PnC (for future use, PnC) */ 602 u32 reserved6; /* hw_cmd (for future use, PnC and HWF) */ 603 }; 604 #endif 605 606 enum mvneta_tx_buf_type { 607 MVNETA_TYPE_SKB, 608 MVNETA_TYPE_XDP_TX, 609 MVNETA_TYPE_XDP_NDO, 610 }; 611 612 struct mvneta_tx_buf { 613 enum mvneta_tx_buf_type type; 614 union { 615 struct xdp_frame *xdpf; 616 struct sk_buff *skb; 617 }; 618 }; 619 620 struct mvneta_tx_queue { 621 /* Number of this TX queue, in the range 0-7 */ 622 u8 id; 623 624 /* Number of TX DMA descriptors in the descriptor ring */ 625 int size; 626 627 /* Number of currently used TX DMA descriptor in the 628 * descriptor ring 629 */ 630 int count; 631 int pending; 632 int tx_stop_threshold; 633 int tx_wake_threshold; 634 635 /* Array of transmitted buffers */ 636 struct mvneta_tx_buf *buf; 637 638 /* Index of last TX DMA descriptor that was inserted */ 639 int txq_put_index; 640 641 /* Index of the TX DMA descriptor to be cleaned up */ 642 int txq_get_index; 643 644 u32 done_pkts_coal; 645 646 /* Virtual address of the TX DMA descriptors array */ 647 struct mvneta_tx_desc *descs; 648 649 /* DMA address of the TX DMA descriptors array */ 650 dma_addr_t descs_phys; 651 652 /* Index of the last TX DMA descriptor */ 653 int last_desc; 654 655 /* Index of the next TX DMA descriptor to process */ 656 int next_desc_to_proc; 657 658 /* DMA buffers for TSO headers */ 659 char *tso_hdrs; 660 661 /* DMA address of TSO headers */ 662 dma_addr_t tso_hdrs_phys; 663 664 /* Affinity mask for CPUs*/ 665 cpumask_t affinity_mask; 666 }; 667 668 struct mvneta_rx_queue { 669 /* rx queue number, in the range 0-7 */ 670 u8 id; 671 672 /* num of rx descriptors in the rx descriptor ring */ 673 int size; 674 675 u32 pkts_coal; 676 u32 time_coal; 677 678 /* page_pool */ 679 struct page_pool *page_pool; 680 struct xdp_rxq_info xdp_rxq; 681 682 /* Virtual address of the RX buffer */ 683 void **buf_virt_addr; 684 685 /* Virtual address of the RX DMA descriptors array */ 686 struct mvneta_rx_desc *descs; 687 688 /* DMA address of the RX DMA descriptors array */ 689 dma_addr_t descs_phys; 690 691 /* Index of the last RX DMA descriptor */ 692 int last_desc; 693 694 /* Index of the next RX DMA descriptor to process */ 695 int next_desc_to_proc; 696 697 /* Index of first RX DMA descriptor to refill */ 698 int first_to_refill; 699 u32 refill_num; 700 }; 701 702 static enum cpuhp_state online_hpstate; 703 /* The hardware supports eight (8) rx queues, but we are only allowing 704 * the first one to be used. Therefore, let's just allocate one queue. 705 */ 706 static int rxq_number = 8; 707 static int txq_number = 8; 708 709 static int rxq_def; 710 711 static int rx_copybreak __read_mostly = 256; 712 713 /* HW BM need that each port be identify by a unique ID */ 714 static int global_port_id; 715 716 #define MVNETA_DRIVER_NAME "mvneta" 717 #define MVNETA_DRIVER_VERSION "1.0" 718 719 /* Utility/helper methods */ 720 721 /* Write helper method */ 722 static void mvreg_write(struct mvneta_port *pp, u32 offset, u32 data) 723 { 724 writel(data, pp->base + offset); 725 } 726 727 /* Read helper method */ 728 static u32 mvreg_read(struct mvneta_port *pp, u32 offset) 729 { 730 return readl(pp->base + offset); 731 } 732 733 /* Increment txq get counter */ 734 static void mvneta_txq_inc_get(struct mvneta_tx_queue *txq) 735 { 736 txq->txq_get_index++; 737 if (txq->txq_get_index == txq->size) 738 txq->txq_get_index = 0; 739 } 740 741 /* Increment txq put counter */ 742 static void mvneta_txq_inc_put(struct mvneta_tx_queue *txq) 743 { 744 txq->txq_put_index++; 745 if (txq->txq_put_index == txq->size) 746 txq->txq_put_index = 0; 747 } 748 749 750 /* Clear all MIB counters */ 751 static void mvneta_mib_counters_clear(struct mvneta_port *pp) 752 { 753 int i; 754 755 /* Perform dummy reads from MIB counters */ 756 for (i = 0; i < MVNETA_MIB_LATE_COLLISION; i += 4) 757 mvreg_read(pp, (MVNETA_MIB_COUNTERS_BASE + i)); 758 mvreg_read(pp, MVNETA_RX_DISCARD_FRAME_COUNT); 759 mvreg_read(pp, MVNETA_OVERRUN_FRAME_COUNT); 760 } 761 762 /* Get System Network Statistics */ 763 static void 764 mvneta_get_stats64(struct net_device *dev, 765 struct rtnl_link_stats64 *stats) 766 { 767 struct mvneta_port *pp = netdev_priv(dev); 768 unsigned int start; 769 int cpu; 770 771 for_each_possible_cpu(cpu) { 772 struct mvneta_pcpu_stats *cpu_stats; 773 u64 rx_packets; 774 u64 rx_bytes; 775 u64 rx_dropped; 776 u64 rx_errors; 777 u64 tx_packets; 778 u64 tx_bytes; 779 780 cpu_stats = per_cpu_ptr(pp->stats, cpu); 781 do { 782 start = u64_stats_fetch_begin_irq(&cpu_stats->syncp); 783 rx_packets = cpu_stats->es.ps.rx_packets; 784 rx_bytes = cpu_stats->es.ps.rx_bytes; 785 rx_dropped = cpu_stats->rx_dropped; 786 rx_errors = cpu_stats->rx_errors; 787 tx_packets = cpu_stats->es.ps.tx_packets; 788 tx_bytes = cpu_stats->es.ps.tx_bytes; 789 } while (u64_stats_fetch_retry_irq(&cpu_stats->syncp, start)); 790 791 stats->rx_packets += rx_packets; 792 stats->rx_bytes += rx_bytes; 793 stats->rx_dropped += rx_dropped; 794 stats->rx_errors += rx_errors; 795 stats->tx_packets += tx_packets; 796 stats->tx_bytes += tx_bytes; 797 } 798 799 stats->tx_dropped = dev->stats.tx_dropped; 800 } 801 802 /* Rx descriptors helper methods */ 803 804 /* Checks whether the RX descriptor having this status is both the first 805 * and the last descriptor for the RX packet. Each RX packet is currently 806 * received through a single RX descriptor, so not having each RX 807 * descriptor with its first and last bits set is an error 808 */ 809 static int mvneta_rxq_desc_is_first_last(u32 status) 810 { 811 return (status & MVNETA_RXD_FIRST_LAST_DESC) == 812 MVNETA_RXD_FIRST_LAST_DESC; 813 } 814 815 /* Add number of descriptors ready to receive new packets */ 816 static void mvneta_rxq_non_occup_desc_add(struct mvneta_port *pp, 817 struct mvneta_rx_queue *rxq, 818 int ndescs) 819 { 820 /* Only MVNETA_RXQ_ADD_NON_OCCUPIED_MAX (255) descriptors can 821 * be added at once 822 */ 823 while (ndescs > MVNETA_RXQ_ADD_NON_OCCUPIED_MAX) { 824 mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id), 825 (MVNETA_RXQ_ADD_NON_OCCUPIED_MAX << 826 MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT)); 827 ndescs -= MVNETA_RXQ_ADD_NON_OCCUPIED_MAX; 828 } 829 830 mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id), 831 (ndescs << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT)); 832 } 833 834 /* Get number of RX descriptors occupied by received packets */ 835 static int mvneta_rxq_busy_desc_num_get(struct mvneta_port *pp, 836 struct mvneta_rx_queue *rxq) 837 { 838 u32 val; 839 840 val = mvreg_read(pp, MVNETA_RXQ_STATUS_REG(rxq->id)); 841 return val & MVNETA_RXQ_OCCUPIED_ALL_MASK; 842 } 843 844 /* Update num of rx desc called upon return from rx path or 845 * from mvneta_rxq_drop_pkts(). 846 */ 847 static void mvneta_rxq_desc_num_update(struct mvneta_port *pp, 848 struct mvneta_rx_queue *rxq, 849 int rx_done, int rx_filled) 850 { 851 u32 val; 852 853 if ((rx_done <= 0xff) && (rx_filled <= 0xff)) { 854 val = rx_done | 855 (rx_filled << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT); 856 mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id), val); 857 return; 858 } 859 860 /* Only 255 descriptors can be added at once */ 861 while ((rx_done > 0) || (rx_filled > 0)) { 862 if (rx_done <= 0xff) { 863 val = rx_done; 864 rx_done = 0; 865 } else { 866 val = 0xff; 867 rx_done -= 0xff; 868 } 869 if (rx_filled <= 0xff) { 870 val |= rx_filled << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT; 871 rx_filled = 0; 872 } else { 873 val |= 0xff << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT; 874 rx_filled -= 0xff; 875 } 876 mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id), val); 877 } 878 } 879 880 /* Get pointer to next RX descriptor to be processed by SW */ 881 static struct mvneta_rx_desc * 882 mvneta_rxq_next_desc_get(struct mvneta_rx_queue *rxq) 883 { 884 int rx_desc = rxq->next_desc_to_proc; 885 886 rxq->next_desc_to_proc = MVNETA_QUEUE_NEXT_DESC(rxq, rx_desc); 887 prefetch(rxq->descs + rxq->next_desc_to_proc); 888 return rxq->descs + rx_desc; 889 } 890 891 /* Change maximum receive size of the port. */ 892 static void mvneta_max_rx_size_set(struct mvneta_port *pp, int max_rx_size) 893 { 894 u32 val; 895 896 val = mvreg_read(pp, MVNETA_GMAC_CTRL_0); 897 val &= ~MVNETA_GMAC_MAX_RX_SIZE_MASK; 898 val |= ((max_rx_size - MVNETA_MH_SIZE) / 2) << 899 MVNETA_GMAC_MAX_RX_SIZE_SHIFT; 900 mvreg_write(pp, MVNETA_GMAC_CTRL_0, val); 901 } 902 903 904 /* Set rx queue offset */ 905 static void mvneta_rxq_offset_set(struct mvneta_port *pp, 906 struct mvneta_rx_queue *rxq, 907 int offset) 908 { 909 u32 val; 910 911 val = mvreg_read(pp, MVNETA_RXQ_CONFIG_REG(rxq->id)); 912 val &= ~MVNETA_RXQ_PKT_OFFSET_ALL_MASK; 913 914 /* Offset is in */ 915 val |= MVNETA_RXQ_PKT_OFFSET_MASK(offset >> 3); 916 mvreg_write(pp, MVNETA_RXQ_CONFIG_REG(rxq->id), val); 917 } 918 919 920 /* Tx descriptors helper methods */ 921 922 /* Update HW with number of TX descriptors to be sent */ 923 static void mvneta_txq_pend_desc_add(struct mvneta_port *pp, 924 struct mvneta_tx_queue *txq, 925 int pend_desc) 926 { 927 u32 val; 928 929 pend_desc += txq->pending; 930 931 /* Only 255 Tx descriptors can be added at once */ 932 do { 933 val = min(pend_desc, 255); 934 mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val); 935 pend_desc -= val; 936 } while (pend_desc > 0); 937 txq->pending = 0; 938 } 939 940 /* Get pointer to next TX descriptor to be processed (send) by HW */ 941 static struct mvneta_tx_desc * 942 mvneta_txq_next_desc_get(struct mvneta_tx_queue *txq) 943 { 944 int tx_desc = txq->next_desc_to_proc; 945 946 txq->next_desc_to_proc = MVNETA_QUEUE_NEXT_DESC(txq, tx_desc); 947 return txq->descs + tx_desc; 948 } 949 950 /* Release the last allocated TX descriptor. Useful to handle DMA 951 * mapping failures in the TX path. 952 */ 953 static void mvneta_txq_desc_put(struct mvneta_tx_queue *txq) 954 { 955 if (txq->next_desc_to_proc == 0) 956 txq->next_desc_to_proc = txq->last_desc - 1; 957 else 958 txq->next_desc_to_proc--; 959 } 960 961 /* Set rxq buf size */ 962 static void mvneta_rxq_buf_size_set(struct mvneta_port *pp, 963 struct mvneta_rx_queue *rxq, 964 int buf_size) 965 { 966 u32 val; 967 968 val = mvreg_read(pp, MVNETA_RXQ_SIZE_REG(rxq->id)); 969 970 val &= ~MVNETA_RXQ_BUF_SIZE_MASK; 971 val |= ((buf_size >> 3) << MVNETA_RXQ_BUF_SIZE_SHIFT); 972 973 mvreg_write(pp, MVNETA_RXQ_SIZE_REG(rxq->id), val); 974 } 975 976 /* Disable buffer management (BM) */ 977 static void mvneta_rxq_bm_disable(struct mvneta_port *pp, 978 struct mvneta_rx_queue *rxq) 979 { 980 u32 val; 981 982 val = mvreg_read(pp, MVNETA_RXQ_CONFIG_REG(rxq->id)); 983 val &= ~MVNETA_RXQ_HW_BUF_ALLOC; 984 mvreg_write(pp, MVNETA_RXQ_CONFIG_REG(rxq->id), val); 985 } 986 987 /* Enable buffer management (BM) */ 988 static void mvneta_rxq_bm_enable(struct mvneta_port *pp, 989 struct mvneta_rx_queue *rxq) 990 { 991 u32 val; 992 993 val = mvreg_read(pp, MVNETA_RXQ_CONFIG_REG(rxq->id)); 994 val |= MVNETA_RXQ_HW_BUF_ALLOC; 995 mvreg_write(pp, MVNETA_RXQ_CONFIG_REG(rxq->id), val); 996 } 997 998 /* Notify HW about port's assignment of pool for bigger packets */ 999 static void mvneta_rxq_long_pool_set(struct mvneta_port *pp, 1000 struct mvneta_rx_queue *rxq) 1001 { 1002 u32 val; 1003 1004 val = mvreg_read(pp, MVNETA_RXQ_CONFIG_REG(rxq->id)); 1005 val &= ~MVNETA_RXQ_LONG_POOL_ID_MASK; 1006 val |= (pp->pool_long->id << MVNETA_RXQ_LONG_POOL_ID_SHIFT); 1007 1008 mvreg_write(pp, MVNETA_RXQ_CONFIG_REG(rxq->id), val); 1009 } 1010 1011 /* Notify HW about port's assignment of pool for smaller packets */ 1012 static void mvneta_rxq_short_pool_set(struct mvneta_port *pp, 1013 struct mvneta_rx_queue *rxq) 1014 { 1015 u32 val; 1016 1017 val = mvreg_read(pp, MVNETA_RXQ_CONFIG_REG(rxq->id)); 1018 val &= ~MVNETA_RXQ_SHORT_POOL_ID_MASK; 1019 val |= (pp->pool_short->id << MVNETA_RXQ_SHORT_POOL_ID_SHIFT); 1020 1021 mvreg_write(pp, MVNETA_RXQ_CONFIG_REG(rxq->id), val); 1022 } 1023 1024 /* Set port's receive buffer size for assigned BM pool */ 1025 static inline void mvneta_bm_pool_bufsize_set(struct mvneta_port *pp, 1026 int buf_size, 1027 u8 pool_id) 1028 { 1029 u32 val; 1030 1031 if (!IS_ALIGNED(buf_size, 8)) { 1032 dev_warn(pp->dev->dev.parent, 1033 "illegal buf_size value %d, round to %d\n", 1034 buf_size, ALIGN(buf_size, 8)); 1035 buf_size = ALIGN(buf_size, 8); 1036 } 1037 1038 val = mvreg_read(pp, MVNETA_PORT_POOL_BUFFER_SZ_REG(pool_id)); 1039 val |= buf_size & MVNETA_PORT_POOL_BUFFER_SZ_MASK; 1040 mvreg_write(pp, MVNETA_PORT_POOL_BUFFER_SZ_REG(pool_id), val); 1041 } 1042 1043 /* Configure MBUS window in order to enable access BM internal SRAM */ 1044 static int mvneta_mbus_io_win_set(struct mvneta_port *pp, u32 base, u32 wsize, 1045 u8 target, u8 attr) 1046 { 1047 u32 win_enable, win_protect; 1048 int i; 1049 1050 win_enable = mvreg_read(pp, MVNETA_BASE_ADDR_ENABLE); 1051 1052 if (pp->bm_win_id < 0) { 1053 /* Find first not occupied window */ 1054 for (i = 0; i < MVNETA_MAX_DECODE_WIN; i++) { 1055 if (win_enable & (1 << i)) { 1056 pp->bm_win_id = i; 1057 break; 1058 } 1059 } 1060 if (i == MVNETA_MAX_DECODE_WIN) 1061 return -ENOMEM; 1062 } else { 1063 i = pp->bm_win_id; 1064 } 1065 1066 mvreg_write(pp, MVNETA_WIN_BASE(i), 0); 1067 mvreg_write(pp, MVNETA_WIN_SIZE(i), 0); 1068 1069 if (i < 4) 1070 mvreg_write(pp, MVNETA_WIN_REMAP(i), 0); 1071 1072 mvreg_write(pp, MVNETA_WIN_BASE(i), (base & 0xffff0000) | 1073 (attr << 8) | target); 1074 1075 mvreg_write(pp, MVNETA_WIN_SIZE(i), (wsize - 1) & 0xffff0000); 1076 1077 win_protect = mvreg_read(pp, MVNETA_ACCESS_PROTECT_ENABLE); 1078 win_protect |= 3 << (2 * i); 1079 mvreg_write(pp, MVNETA_ACCESS_PROTECT_ENABLE, win_protect); 1080 1081 win_enable &= ~(1 << i); 1082 mvreg_write(pp, MVNETA_BASE_ADDR_ENABLE, win_enable); 1083 1084 return 0; 1085 } 1086 1087 static int mvneta_bm_port_mbus_init(struct mvneta_port *pp) 1088 { 1089 u32 wsize; 1090 u8 target, attr; 1091 int err; 1092 1093 /* Get BM window information */ 1094 err = mvebu_mbus_get_io_win_info(pp->bm_priv->bppi_phys_addr, &wsize, 1095 &target, &attr); 1096 if (err < 0) 1097 return err; 1098 1099 pp->bm_win_id = -1; 1100 1101 /* Open NETA -> BM window */ 1102 err = mvneta_mbus_io_win_set(pp, pp->bm_priv->bppi_phys_addr, wsize, 1103 target, attr); 1104 if (err < 0) { 1105 netdev_info(pp->dev, "fail to configure mbus window to BM\n"); 1106 return err; 1107 } 1108 return 0; 1109 } 1110 1111 /* Assign and initialize pools for port. In case of fail 1112 * buffer manager will remain disabled for current port. 1113 */ 1114 static int mvneta_bm_port_init(struct platform_device *pdev, 1115 struct mvneta_port *pp) 1116 { 1117 struct device_node *dn = pdev->dev.of_node; 1118 u32 long_pool_id, short_pool_id; 1119 1120 if (!pp->neta_armada3700) { 1121 int ret; 1122 1123 ret = mvneta_bm_port_mbus_init(pp); 1124 if (ret) 1125 return ret; 1126 } 1127 1128 if (of_property_read_u32(dn, "bm,pool-long", &long_pool_id)) { 1129 netdev_info(pp->dev, "missing long pool id\n"); 1130 return -EINVAL; 1131 } 1132 1133 /* Create port's long pool depending on mtu */ 1134 pp->pool_long = mvneta_bm_pool_use(pp->bm_priv, long_pool_id, 1135 MVNETA_BM_LONG, pp->id, 1136 MVNETA_RX_PKT_SIZE(pp->dev->mtu)); 1137 if (!pp->pool_long) { 1138 netdev_info(pp->dev, "fail to obtain long pool for port\n"); 1139 return -ENOMEM; 1140 } 1141 1142 pp->pool_long->port_map |= 1 << pp->id; 1143 1144 mvneta_bm_pool_bufsize_set(pp, pp->pool_long->buf_size, 1145 pp->pool_long->id); 1146 1147 /* If short pool id is not defined, assume using single pool */ 1148 if (of_property_read_u32(dn, "bm,pool-short", &short_pool_id)) 1149 short_pool_id = long_pool_id; 1150 1151 /* Create port's short pool */ 1152 pp->pool_short = mvneta_bm_pool_use(pp->bm_priv, short_pool_id, 1153 MVNETA_BM_SHORT, pp->id, 1154 MVNETA_BM_SHORT_PKT_SIZE); 1155 if (!pp->pool_short) { 1156 netdev_info(pp->dev, "fail to obtain short pool for port\n"); 1157 mvneta_bm_pool_destroy(pp->bm_priv, pp->pool_long, 1 << pp->id); 1158 return -ENOMEM; 1159 } 1160 1161 if (short_pool_id != long_pool_id) { 1162 pp->pool_short->port_map |= 1 << pp->id; 1163 mvneta_bm_pool_bufsize_set(pp, pp->pool_short->buf_size, 1164 pp->pool_short->id); 1165 } 1166 1167 return 0; 1168 } 1169 1170 /* Update settings of a pool for bigger packets */ 1171 static void mvneta_bm_update_mtu(struct mvneta_port *pp, int mtu) 1172 { 1173 struct mvneta_bm_pool *bm_pool = pp->pool_long; 1174 struct hwbm_pool *hwbm_pool = &bm_pool->hwbm_pool; 1175 int num; 1176 1177 /* Release all buffers from long pool */ 1178 mvneta_bm_bufs_free(pp->bm_priv, bm_pool, 1 << pp->id); 1179 if (hwbm_pool->buf_num) { 1180 WARN(1, "cannot free all buffers in pool %d\n", 1181 bm_pool->id); 1182 goto bm_mtu_err; 1183 } 1184 1185 bm_pool->pkt_size = MVNETA_RX_PKT_SIZE(mtu); 1186 bm_pool->buf_size = MVNETA_RX_BUF_SIZE(bm_pool->pkt_size); 1187 hwbm_pool->frag_size = SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) + 1188 SKB_DATA_ALIGN(MVNETA_RX_BUF_SIZE(bm_pool->pkt_size)); 1189 1190 /* Fill entire long pool */ 1191 num = hwbm_pool_add(hwbm_pool, hwbm_pool->size); 1192 if (num != hwbm_pool->size) { 1193 WARN(1, "pool %d: %d of %d allocated\n", 1194 bm_pool->id, num, hwbm_pool->size); 1195 goto bm_mtu_err; 1196 } 1197 mvneta_bm_pool_bufsize_set(pp, bm_pool->buf_size, bm_pool->id); 1198 1199 return; 1200 1201 bm_mtu_err: 1202 mvneta_bm_pool_destroy(pp->bm_priv, pp->pool_long, 1 << pp->id); 1203 mvneta_bm_pool_destroy(pp->bm_priv, pp->pool_short, 1 << pp->id); 1204 1205 pp->bm_priv = NULL; 1206 pp->rx_offset_correction = MVNETA_SKB_HEADROOM; 1207 mvreg_write(pp, MVNETA_ACC_MODE, MVNETA_ACC_MODE_EXT1); 1208 netdev_info(pp->dev, "fail to update MTU, fall back to software BM\n"); 1209 } 1210 1211 /* Start the Ethernet port RX and TX activity */ 1212 static void mvneta_port_up(struct mvneta_port *pp) 1213 { 1214 int queue; 1215 u32 q_map; 1216 1217 /* Enable all initialized TXs. */ 1218 q_map = 0; 1219 for (queue = 0; queue < txq_number; queue++) { 1220 struct mvneta_tx_queue *txq = &pp->txqs[queue]; 1221 if (txq->descs) 1222 q_map |= (1 << queue); 1223 } 1224 mvreg_write(pp, MVNETA_TXQ_CMD, q_map); 1225 1226 q_map = 0; 1227 /* Enable all initialized RXQs. */ 1228 for (queue = 0; queue < rxq_number; queue++) { 1229 struct mvneta_rx_queue *rxq = &pp->rxqs[queue]; 1230 1231 if (rxq->descs) 1232 q_map |= (1 << queue); 1233 } 1234 mvreg_write(pp, MVNETA_RXQ_CMD, q_map); 1235 } 1236 1237 /* Stop the Ethernet port activity */ 1238 static void mvneta_port_down(struct mvneta_port *pp) 1239 { 1240 u32 val; 1241 int count; 1242 1243 /* Stop Rx port activity. Check port Rx activity. */ 1244 val = mvreg_read(pp, MVNETA_RXQ_CMD) & MVNETA_RXQ_ENABLE_MASK; 1245 1246 /* Issue stop command for active channels only */ 1247 if (val != 0) 1248 mvreg_write(pp, MVNETA_RXQ_CMD, 1249 val << MVNETA_RXQ_DISABLE_SHIFT); 1250 1251 /* Wait for all Rx activity to terminate. */ 1252 count = 0; 1253 do { 1254 if (count++ >= MVNETA_RX_DISABLE_TIMEOUT_MSEC) { 1255 netdev_warn(pp->dev, 1256 "TIMEOUT for RX stopped ! rx_queue_cmd: 0x%08x\n", 1257 val); 1258 break; 1259 } 1260 mdelay(1); 1261 1262 val = mvreg_read(pp, MVNETA_RXQ_CMD); 1263 } while (val & MVNETA_RXQ_ENABLE_MASK); 1264 1265 /* Stop Tx port activity. Check port Tx activity. Issue stop 1266 * command for active channels only 1267 */ 1268 val = (mvreg_read(pp, MVNETA_TXQ_CMD)) & MVNETA_TXQ_ENABLE_MASK; 1269 1270 if (val != 0) 1271 mvreg_write(pp, MVNETA_TXQ_CMD, 1272 (val << MVNETA_TXQ_DISABLE_SHIFT)); 1273 1274 /* Wait for all Tx activity to terminate. */ 1275 count = 0; 1276 do { 1277 if (count++ >= MVNETA_TX_DISABLE_TIMEOUT_MSEC) { 1278 netdev_warn(pp->dev, 1279 "TIMEOUT for TX stopped status=0x%08x\n", 1280 val); 1281 break; 1282 } 1283 mdelay(1); 1284 1285 /* Check TX Command reg that all Txqs are stopped */ 1286 val = mvreg_read(pp, MVNETA_TXQ_CMD); 1287 1288 } while (val & MVNETA_TXQ_ENABLE_MASK); 1289 1290 /* Double check to verify that TX FIFO is empty */ 1291 count = 0; 1292 do { 1293 if (count++ >= MVNETA_TX_FIFO_EMPTY_TIMEOUT) { 1294 netdev_warn(pp->dev, 1295 "TX FIFO empty timeout status=0x%08x\n", 1296 val); 1297 break; 1298 } 1299 mdelay(1); 1300 1301 val = mvreg_read(pp, MVNETA_PORT_STATUS); 1302 } while (!(val & MVNETA_TX_FIFO_EMPTY) && 1303 (val & MVNETA_TX_IN_PRGRS)); 1304 1305 udelay(200); 1306 } 1307 1308 /* Enable the port by setting the port enable bit of the MAC control register */ 1309 static void mvneta_port_enable(struct mvneta_port *pp) 1310 { 1311 u32 val; 1312 1313 /* Enable port */ 1314 val = mvreg_read(pp, MVNETA_GMAC_CTRL_0); 1315 val |= MVNETA_GMAC0_PORT_ENABLE; 1316 mvreg_write(pp, MVNETA_GMAC_CTRL_0, val); 1317 } 1318 1319 /* Disable the port and wait for about 200 usec before retuning */ 1320 static void mvneta_port_disable(struct mvneta_port *pp) 1321 { 1322 u32 val; 1323 1324 /* Reset the Enable bit in the Serial Control Register */ 1325 val = mvreg_read(pp, MVNETA_GMAC_CTRL_0); 1326 val &= ~MVNETA_GMAC0_PORT_ENABLE; 1327 mvreg_write(pp, MVNETA_GMAC_CTRL_0, val); 1328 1329 udelay(200); 1330 } 1331 1332 /* Multicast tables methods */ 1333 1334 /* Set all entries in Unicast MAC Table; queue==-1 means reject all */ 1335 static void mvneta_set_ucast_table(struct mvneta_port *pp, int queue) 1336 { 1337 int offset; 1338 u32 val; 1339 1340 if (queue == -1) { 1341 val = 0; 1342 } else { 1343 val = 0x1 | (queue << 1); 1344 val |= (val << 24) | (val << 16) | (val << 8); 1345 } 1346 1347 for (offset = 0; offset <= 0xc; offset += 4) 1348 mvreg_write(pp, MVNETA_DA_FILT_UCAST_BASE + offset, val); 1349 } 1350 1351 /* Set all entries in Special Multicast MAC Table; queue==-1 means reject all */ 1352 static void mvneta_set_special_mcast_table(struct mvneta_port *pp, int queue) 1353 { 1354 int offset; 1355 u32 val; 1356 1357 if (queue == -1) { 1358 val = 0; 1359 } else { 1360 val = 0x1 | (queue << 1); 1361 val |= (val << 24) | (val << 16) | (val << 8); 1362 } 1363 1364 for (offset = 0; offset <= 0xfc; offset += 4) 1365 mvreg_write(pp, MVNETA_DA_FILT_SPEC_MCAST + offset, val); 1366 1367 } 1368 1369 /* Set all entries in Other Multicast MAC Table. queue==-1 means reject all */ 1370 static void mvneta_set_other_mcast_table(struct mvneta_port *pp, int queue) 1371 { 1372 int offset; 1373 u32 val; 1374 1375 if (queue == -1) { 1376 memset(pp->mcast_count, 0, sizeof(pp->mcast_count)); 1377 val = 0; 1378 } else { 1379 memset(pp->mcast_count, 1, sizeof(pp->mcast_count)); 1380 val = 0x1 | (queue << 1); 1381 val |= (val << 24) | (val << 16) | (val << 8); 1382 } 1383 1384 for (offset = 0; offset <= 0xfc; offset += 4) 1385 mvreg_write(pp, MVNETA_DA_FILT_OTH_MCAST + offset, val); 1386 } 1387 1388 static void mvneta_percpu_unmask_interrupt(void *arg) 1389 { 1390 struct mvneta_port *pp = arg; 1391 1392 /* All the queue are unmasked, but actually only the ones 1393 * mapped to this CPU will be unmasked 1394 */ 1395 mvreg_write(pp, MVNETA_INTR_NEW_MASK, 1396 MVNETA_RX_INTR_MASK_ALL | 1397 MVNETA_TX_INTR_MASK_ALL | 1398 MVNETA_MISCINTR_INTR_MASK); 1399 } 1400 1401 static void mvneta_percpu_mask_interrupt(void *arg) 1402 { 1403 struct mvneta_port *pp = arg; 1404 1405 /* All the queue are masked, but actually only the ones 1406 * mapped to this CPU will be masked 1407 */ 1408 mvreg_write(pp, MVNETA_INTR_NEW_MASK, 0); 1409 mvreg_write(pp, MVNETA_INTR_OLD_MASK, 0); 1410 mvreg_write(pp, MVNETA_INTR_MISC_MASK, 0); 1411 } 1412 1413 static void mvneta_percpu_clear_intr_cause(void *arg) 1414 { 1415 struct mvneta_port *pp = arg; 1416 1417 /* All the queue are cleared, but actually only the ones 1418 * mapped to this CPU will be cleared 1419 */ 1420 mvreg_write(pp, MVNETA_INTR_NEW_CAUSE, 0); 1421 mvreg_write(pp, MVNETA_INTR_MISC_CAUSE, 0); 1422 mvreg_write(pp, MVNETA_INTR_OLD_CAUSE, 0); 1423 } 1424 1425 /* This method sets defaults to the NETA port: 1426 * Clears interrupt Cause and Mask registers. 1427 * Clears all MAC tables. 1428 * Sets defaults to all registers. 1429 * Resets RX and TX descriptor rings. 1430 * Resets PHY. 1431 * This method can be called after mvneta_port_down() to return the port 1432 * settings to defaults. 1433 */ 1434 static void mvneta_defaults_set(struct mvneta_port *pp) 1435 { 1436 int cpu; 1437 int queue; 1438 u32 val; 1439 int max_cpu = num_present_cpus(); 1440 1441 /* Clear all Cause registers */ 1442 on_each_cpu(mvneta_percpu_clear_intr_cause, pp, true); 1443 1444 /* Mask all interrupts */ 1445 on_each_cpu(mvneta_percpu_mask_interrupt, pp, true); 1446 mvreg_write(pp, MVNETA_INTR_ENABLE, 0); 1447 1448 /* Enable MBUS Retry bit16 */ 1449 mvreg_write(pp, MVNETA_MBUS_RETRY, 0x20); 1450 1451 /* Set CPU queue access map. CPUs are assigned to the RX and 1452 * TX queues modulo their number. If there is only one TX 1453 * queue then it is assigned to the CPU associated to the 1454 * default RX queue. 1455 */ 1456 for_each_present_cpu(cpu) { 1457 int rxq_map = 0, txq_map = 0; 1458 int rxq, txq; 1459 if (!pp->neta_armada3700) { 1460 for (rxq = 0; rxq < rxq_number; rxq++) 1461 if ((rxq % max_cpu) == cpu) 1462 rxq_map |= MVNETA_CPU_RXQ_ACCESS(rxq); 1463 1464 for (txq = 0; txq < txq_number; txq++) 1465 if ((txq % max_cpu) == cpu) 1466 txq_map |= MVNETA_CPU_TXQ_ACCESS(txq); 1467 1468 /* With only one TX queue we configure a special case 1469 * which will allow to get all the irq on a single 1470 * CPU 1471 */ 1472 if (txq_number == 1) 1473 txq_map = (cpu == pp->rxq_def) ? 1474 MVNETA_CPU_TXQ_ACCESS(1) : 0; 1475 1476 } else { 1477 txq_map = MVNETA_CPU_TXQ_ACCESS_ALL_MASK; 1478 rxq_map = MVNETA_CPU_RXQ_ACCESS_ALL_MASK; 1479 } 1480 1481 mvreg_write(pp, MVNETA_CPU_MAP(cpu), rxq_map | txq_map); 1482 } 1483 1484 /* Reset RX and TX DMAs */ 1485 mvreg_write(pp, MVNETA_PORT_RX_RESET, MVNETA_PORT_RX_DMA_RESET); 1486 mvreg_write(pp, MVNETA_PORT_TX_RESET, MVNETA_PORT_TX_DMA_RESET); 1487 1488 /* Disable Legacy WRR, Disable EJP, Release from reset */ 1489 mvreg_write(pp, MVNETA_TXQ_CMD_1, 0); 1490 for (queue = 0; queue < txq_number; queue++) { 1491 mvreg_write(pp, MVETH_TXQ_TOKEN_COUNT_REG(queue), 0); 1492 mvreg_write(pp, MVETH_TXQ_TOKEN_CFG_REG(queue), 0); 1493 } 1494 1495 mvreg_write(pp, MVNETA_PORT_TX_RESET, 0); 1496 mvreg_write(pp, MVNETA_PORT_RX_RESET, 0); 1497 1498 /* Set Port Acceleration Mode */ 1499 if (pp->bm_priv) 1500 /* HW buffer management + legacy parser */ 1501 val = MVNETA_ACC_MODE_EXT2; 1502 else 1503 /* SW buffer management + legacy parser */ 1504 val = MVNETA_ACC_MODE_EXT1; 1505 mvreg_write(pp, MVNETA_ACC_MODE, val); 1506 1507 if (pp->bm_priv) 1508 mvreg_write(pp, MVNETA_BM_ADDRESS, pp->bm_priv->bppi_phys_addr); 1509 1510 /* Update val of portCfg register accordingly with all RxQueue types */ 1511 val = MVNETA_PORT_CONFIG_DEFL_VALUE(pp->rxq_def); 1512 mvreg_write(pp, MVNETA_PORT_CONFIG, val); 1513 1514 val = 0; 1515 mvreg_write(pp, MVNETA_PORT_CONFIG_EXTEND, val); 1516 mvreg_write(pp, MVNETA_RX_MIN_FRAME_SIZE, 64); 1517 1518 /* Build PORT_SDMA_CONFIG_REG */ 1519 val = 0; 1520 1521 /* Default burst size */ 1522 val |= MVNETA_TX_BRST_SZ_MASK(MVNETA_SDMA_BRST_SIZE_16); 1523 val |= MVNETA_RX_BRST_SZ_MASK(MVNETA_SDMA_BRST_SIZE_16); 1524 val |= MVNETA_RX_NO_DATA_SWAP | MVNETA_TX_NO_DATA_SWAP; 1525 1526 #if defined(__BIG_ENDIAN) 1527 val |= MVNETA_DESC_SWAP; 1528 #endif 1529 1530 /* Assign port SDMA configuration */ 1531 mvreg_write(pp, MVNETA_SDMA_CONFIG, val); 1532 1533 /* Disable PHY polling in hardware, since we're using the 1534 * kernel phylib to do this. 1535 */ 1536 val = mvreg_read(pp, MVNETA_UNIT_CONTROL); 1537 val &= ~MVNETA_PHY_POLLING_ENABLE; 1538 mvreg_write(pp, MVNETA_UNIT_CONTROL, val); 1539 1540 mvneta_set_ucast_table(pp, -1); 1541 mvneta_set_special_mcast_table(pp, -1); 1542 mvneta_set_other_mcast_table(pp, -1); 1543 1544 /* Set port interrupt enable register - default enable all */ 1545 mvreg_write(pp, MVNETA_INTR_ENABLE, 1546 (MVNETA_RXQ_INTR_ENABLE_ALL_MASK 1547 | MVNETA_TXQ_INTR_ENABLE_ALL_MASK)); 1548 1549 mvneta_mib_counters_clear(pp); 1550 } 1551 1552 /* Set max sizes for tx queues */ 1553 static void mvneta_txq_max_tx_size_set(struct mvneta_port *pp, int max_tx_size) 1554 1555 { 1556 u32 val, size, mtu; 1557 int queue; 1558 1559 mtu = max_tx_size * 8; 1560 if (mtu > MVNETA_TX_MTU_MAX) 1561 mtu = MVNETA_TX_MTU_MAX; 1562 1563 /* Set MTU */ 1564 val = mvreg_read(pp, MVNETA_TX_MTU); 1565 val &= ~MVNETA_TX_MTU_MAX; 1566 val |= mtu; 1567 mvreg_write(pp, MVNETA_TX_MTU, val); 1568 1569 /* TX token size and all TXQs token size must be larger that MTU */ 1570 val = mvreg_read(pp, MVNETA_TX_TOKEN_SIZE); 1571 1572 size = val & MVNETA_TX_TOKEN_SIZE_MAX; 1573 if (size < mtu) { 1574 size = mtu; 1575 val &= ~MVNETA_TX_TOKEN_SIZE_MAX; 1576 val |= size; 1577 mvreg_write(pp, MVNETA_TX_TOKEN_SIZE, val); 1578 } 1579 for (queue = 0; queue < txq_number; queue++) { 1580 val = mvreg_read(pp, MVNETA_TXQ_TOKEN_SIZE_REG(queue)); 1581 1582 size = val & MVNETA_TXQ_TOKEN_SIZE_MAX; 1583 if (size < mtu) { 1584 size = mtu; 1585 val &= ~MVNETA_TXQ_TOKEN_SIZE_MAX; 1586 val |= size; 1587 mvreg_write(pp, MVNETA_TXQ_TOKEN_SIZE_REG(queue), val); 1588 } 1589 } 1590 } 1591 1592 /* Set unicast address */ 1593 static void mvneta_set_ucast_addr(struct mvneta_port *pp, u8 last_nibble, 1594 int queue) 1595 { 1596 unsigned int unicast_reg; 1597 unsigned int tbl_offset; 1598 unsigned int reg_offset; 1599 1600 /* Locate the Unicast table entry */ 1601 last_nibble = (0xf & last_nibble); 1602 1603 /* offset from unicast tbl base */ 1604 tbl_offset = (last_nibble / 4) * 4; 1605 1606 /* offset within the above reg */ 1607 reg_offset = last_nibble % 4; 1608 1609 unicast_reg = mvreg_read(pp, (MVNETA_DA_FILT_UCAST_BASE + tbl_offset)); 1610 1611 if (queue == -1) { 1612 /* Clear accepts frame bit at specified unicast DA tbl entry */ 1613 unicast_reg &= ~(0xff << (8 * reg_offset)); 1614 } else { 1615 unicast_reg &= ~(0xff << (8 * reg_offset)); 1616 unicast_reg |= ((0x01 | (queue << 1)) << (8 * reg_offset)); 1617 } 1618 1619 mvreg_write(pp, (MVNETA_DA_FILT_UCAST_BASE + tbl_offset), unicast_reg); 1620 } 1621 1622 /* Set mac address */ 1623 static void mvneta_mac_addr_set(struct mvneta_port *pp, unsigned char *addr, 1624 int queue) 1625 { 1626 unsigned int mac_h; 1627 unsigned int mac_l; 1628 1629 if (queue != -1) { 1630 mac_l = (addr[4] << 8) | (addr[5]); 1631 mac_h = (addr[0] << 24) | (addr[1] << 16) | 1632 (addr[2] << 8) | (addr[3] << 0); 1633 1634 mvreg_write(pp, MVNETA_MAC_ADDR_LOW, mac_l); 1635 mvreg_write(pp, MVNETA_MAC_ADDR_HIGH, mac_h); 1636 } 1637 1638 /* Accept frames of this address */ 1639 mvneta_set_ucast_addr(pp, addr[5], queue); 1640 } 1641 1642 /* Set the number of packets that will be received before RX interrupt 1643 * will be generated by HW. 1644 */ 1645 static void mvneta_rx_pkts_coal_set(struct mvneta_port *pp, 1646 struct mvneta_rx_queue *rxq, u32 value) 1647 { 1648 mvreg_write(pp, MVNETA_RXQ_THRESHOLD_REG(rxq->id), 1649 value | MVNETA_RXQ_NON_OCCUPIED(0)); 1650 } 1651 1652 /* Set the time delay in usec before RX interrupt will be generated by 1653 * HW. 1654 */ 1655 static void mvneta_rx_time_coal_set(struct mvneta_port *pp, 1656 struct mvneta_rx_queue *rxq, u32 value) 1657 { 1658 u32 val; 1659 unsigned long clk_rate; 1660 1661 clk_rate = clk_get_rate(pp->clk); 1662 val = (clk_rate / 1000000) * value; 1663 1664 mvreg_write(pp, MVNETA_RXQ_TIME_COAL_REG(rxq->id), val); 1665 } 1666 1667 /* Set threshold for TX_DONE pkts coalescing */ 1668 static void mvneta_tx_done_pkts_coal_set(struct mvneta_port *pp, 1669 struct mvneta_tx_queue *txq, u32 value) 1670 { 1671 u32 val; 1672 1673 val = mvreg_read(pp, MVNETA_TXQ_SIZE_REG(txq->id)); 1674 1675 val &= ~MVNETA_TXQ_SENT_THRESH_ALL_MASK; 1676 val |= MVNETA_TXQ_SENT_THRESH_MASK(value); 1677 1678 mvreg_write(pp, MVNETA_TXQ_SIZE_REG(txq->id), val); 1679 } 1680 1681 /* Handle rx descriptor fill by setting buf_cookie and buf_phys_addr */ 1682 static void mvneta_rx_desc_fill(struct mvneta_rx_desc *rx_desc, 1683 u32 phys_addr, void *virt_addr, 1684 struct mvneta_rx_queue *rxq) 1685 { 1686 int i; 1687 1688 rx_desc->buf_phys_addr = phys_addr; 1689 i = rx_desc - rxq->descs; 1690 rxq->buf_virt_addr[i] = virt_addr; 1691 } 1692 1693 /* Decrement sent descriptors counter */ 1694 static void mvneta_txq_sent_desc_dec(struct mvneta_port *pp, 1695 struct mvneta_tx_queue *txq, 1696 int sent_desc) 1697 { 1698 u32 val; 1699 1700 /* Only 255 TX descriptors can be updated at once */ 1701 while (sent_desc > 0xff) { 1702 val = 0xff << MVNETA_TXQ_DEC_SENT_SHIFT; 1703 mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val); 1704 sent_desc = sent_desc - 0xff; 1705 } 1706 1707 val = sent_desc << MVNETA_TXQ_DEC_SENT_SHIFT; 1708 mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val); 1709 } 1710 1711 /* Get number of TX descriptors already sent by HW */ 1712 static int mvneta_txq_sent_desc_num_get(struct mvneta_port *pp, 1713 struct mvneta_tx_queue *txq) 1714 { 1715 u32 val; 1716 int sent_desc; 1717 1718 val = mvreg_read(pp, MVNETA_TXQ_STATUS_REG(txq->id)); 1719 sent_desc = (val & MVNETA_TXQ_SENT_DESC_MASK) >> 1720 MVNETA_TXQ_SENT_DESC_SHIFT; 1721 1722 return sent_desc; 1723 } 1724 1725 /* Get number of sent descriptors and decrement counter. 1726 * The number of sent descriptors is returned. 1727 */ 1728 static int mvneta_txq_sent_desc_proc(struct mvneta_port *pp, 1729 struct mvneta_tx_queue *txq) 1730 { 1731 int sent_desc; 1732 1733 /* Get number of sent descriptors */ 1734 sent_desc = mvneta_txq_sent_desc_num_get(pp, txq); 1735 1736 /* Decrement sent descriptors counter */ 1737 if (sent_desc) 1738 mvneta_txq_sent_desc_dec(pp, txq, sent_desc); 1739 1740 return sent_desc; 1741 } 1742 1743 /* Set TXQ descriptors fields relevant for CSUM calculation */ 1744 static u32 mvneta_txq_desc_csum(int l3_offs, int l3_proto, 1745 int ip_hdr_len, int l4_proto) 1746 { 1747 u32 command; 1748 1749 /* Fields: L3_offset, IP_hdrlen, L3_type, G_IPv4_chk, 1750 * G_L4_chk, L4_type; required only for checksum 1751 * calculation 1752 */ 1753 command = l3_offs << MVNETA_TX_L3_OFF_SHIFT; 1754 command |= ip_hdr_len << MVNETA_TX_IP_HLEN_SHIFT; 1755 1756 if (l3_proto == htons(ETH_P_IP)) 1757 command |= MVNETA_TXD_IP_CSUM; 1758 else 1759 command |= MVNETA_TX_L3_IP6; 1760 1761 if (l4_proto == IPPROTO_TCP) 1762 command |= MVNETA_TX_L4_CSUM_FULL; 1763 else if (l4_proto == IPPROTO_UDP) 1764 command |= MVNETA_TX_L4_UDP | MVNETA_TX_L4_CSUM_FULL; 1765 else 1766 command |= MVNETA_TX_L4_CSUM_NOT; 1767 1768 return command; 1769 } 1770 1771 1772 /* Display more error info */ 1773 static void mvneta_rx_error(struct mvneta_port *pp, 1774 struct mvneta_rx_desc *rx_desc) 1775 { 1776 struct mvneta_pcpu_stats *stats = this_cpu_ptr(pp->stats); 1777 u32 status = rx_desc->status; 1778 1779 /* update per-cpu counter */ 1780 u64_stats_update_begin(&stats->syncp); 1781 stats->rx_errors++; 1782 u64_stats_update_end(&stats->syncp); 1783 1784 switch (status & MVNETA_RXD_ERR_CODE_MASK) { 1785 case MVNETA_RXD_ERR_CRC: 1786 netdev_err(pp->dev, "bad rx status %08x (crc error), size=%d\n", 1787 status, rx_desc->data_size); 1788 break; 1789 case MVNETA_RXD_ERR_OVERRUN: 1790 netdev_err(pp->dev, "bad rx status %08x (overrun error), size=%d\n", 1791 status, rx_desc->data_size); 1792 break; 1793 case MVNETA_RXD_ERR_LEN: 1794 netdev_err(pp->dev, "bad rx status %08x (max frame length error), size=%d\n", 1795 status, rx_desc->data_size); 1796 break; 1797 case MVNETA_RXD_ERR_RESOURCE: 1798 netdev_err(pp->dev, "bad rx status %08x (resource error), size=%d\n", 1799 status, rx_desc->data_size); 1800 break; 1801 } 1802 } 1803 1804 /* Handle RX checksum offload based on the descriptor's status */ 1805 static void mvneta_rx_csum(struct mvneta_port *pp, u32 status, 1806 struct sk_buff *skb) 1807 { 1808 if ((pp->dev->features & NETIF_F_RXCSUM) && 1809 (status & MVNETA_RXD_L3_IP4) && 1810 (status & MVNETA_RXD_L4_CSUM_OK)) { 1811 skb->csum = 0; 1812 skb->ip_summed = CHECKSUM_UNNECESSARY; 1813 return; 1814 } 1815 1816 skb->ip_summed = CHECKSUM_NONE; 1817 } 1818 1819 /* Return tx queue pointer (find last set bit) according to <cause> returned 1820 * form tx_done reg. <cause> must not be null. The return value is always a 1821 * valid queue for matching the first one found in <cause>. 1822 */ 1823 static struct mvneta_tx_queue *mvneta_tx_done_policy(struct mvneta_port *pp, 1824 u32 cause) 1825 { 1826 int queue = fls(cause) - 1; 1827 1828 return &pp->txqs[queue]; 1829 } 1830 1831 /* Free tx queue skbuffs */ 1832 static void mvneta_txq_bufs_free(struct mvneta_port *pp, 1833 struct mvneta_tx_queue *txq, int num, 1834 struct netdev_queue *nq, bool napi) 1835 { 1836 unsigned int bytes_compl = 0, pkts_compl = 0; 1837 int i; 1838 1839 for (i = 0; i < num; i++) { 1840 struct mvneta_tx_buf *buf = &txq->buf[txq->txq_get_index]; 1841 struct mvneta_tx_desc *tx_desc = txq->descs + 1842 txq->txq_get_index; 1843 1844 mvneta_txq_inc_get(txq); 1845 1846 if (!IS_TSO_HEADER(txq, tx_desc->buf_phys_addr) && 1847 buf->type != MVNETA_TYPE_XDP_TX) 1848 dma_unmap_single(pp->dev->dev.parent, 1849 tx_desc->buf_phys_addr, 1850 tx_desc->data_size, DMA_TO_DEVICE); 1851 if (buf->type == MVNETA_TYPE_SKB && buf->skb) { 1852 bytes_compl += buf->skb->len; 1853 pkts_compl++; 1854 dev_kfree_skb_any(buf->skb); 1855 } else if (buf->type == MVNETA_TYPE_XDP_TX || 1856 buf->type == MVNETA_TYPE_XDP_NDO) { 1857 if (napi && buf->type == MVNETA_TYPE_XDP_TX) 1858 xdp_return_frame_rx_napi(buf->xdpf); 1859 else 1860 xdp_return_frame(buf->xdpf); 1861 } 1862 } 1863 1864 netdev_tx_completed_queue(nq, pkts_compl, bytes_compl); 1865 } 1866 1867 /* Handle end of transmission */ 1868 static void mvneta_txq_done(struct mvneta_port *pp, 1869 struct mvneta_tx_queue *txq) 1870 { 1871 struct netdev_queue *nq = netdev_get_tx_queue(pp->dev, txq->id); 1872 int tx_done; 1873 1874 tx_done = mvneta_txq_sent_desc_proc(pp, txq); 1875 if (!tx_done) 1876 return; 1877 1878 mvneta_txq_bufs_free(pp, txq, tx_done, nq, true); 1879 1880 txq->count -= tx_done; 1881 1882 if (netif_tx_queue_stopped(nq)) { 1883 if (txq->count <= txq->tx_wake_threshold) 1884 netif_tx_wake_queue(nq); 1885 } 1886 } 1887 1888 /* Refill processing for SW buffer management */ 1889 /* Allocate page per descriptor */ 1890 static int mvneta_rx_refill(struct mvneta_port *pp, 1891 struct mvneta_rx_desc *rx_desc, 1892 struct mvneta_rx_queue *rxq, 1893 gfp_t gfp_mask) 1894 { 1895 dma_addr_t phys_addr; 1896 struct page *page; 1897 1898 page = page_pool_alloc_pages(rxq->page_pool, 1899 gfp_mask | __GFP_NOWARN); 1900 if (!page) 1901 return -ENOMEM; 1902 1903 phys_addr = page_pool_get_dma_addr(page) + pp->rx_offset_correction; 1904 mvneta_rx_desc_fill(rx_desc, phys_addr, page, rxq); 1905 1906 return 0; 1907 } 1908 1909 /* Handle tx checksum */ 1910 static u32 mvneta_skb_tx_csum(struct mvneta_port *pp, struct sk_buff *skb) 1911 { 1912 if (skb->ip_summed == CHECKSUM_PARTIAL) { 1913 int ip_hdr_len = 0; 1914 __be16 l3_proto = vlan_get_protocol(skb); 1915 u8 l4_proto; 1916 1917 if (l3_proto == htons(ETH_P_IP)) { 1918 struct iphdr *ip4h = ip_hdr(skb); 1919 1920 /* Calculate IPv4 checksum and L4 checksum */ 1921 ip_hdr_len = ip4h->ihl; 1922 l4_proto = ip4h->protocol; 1923 } else if (l3_proto == htons(ETH_P_IPV6)) { 1924 struct ipv6hdr *ip6h = ipv6_hdr(skb); 1925 1926 /* Read l4_protocol from one of IPv6 extra headers */ 1927 if (skb_network_header_len(skb) > 0) 1928 ip_hdr_len = (skb_network_header_len(skb) >> 2); 1929 l4_proto = ip6h->nexthdr; 1930 } else 1931 return MVNETA_TX_L4_CSUM_NOT; 1932 1933 return mvneta_txq_desc_csum(skb_network_offset(skb), 1934 l3_proto, ip_hdr_len, l4_proto); 1935 } 1936 1937 return MVNETA_TX_L4_CSUM_NOT; 1938 } 1939 1940 /* Drop packets received by the RXQ and free buffers */ 1941 static void mvneta_rxq_drop_pkts(struct mvneta_port *pp, 1942 struct mvneta_rx_queue *rxq) 1943 { 1944 int rx_done, i; 1945 1946 rx_done = mvneta_rxq_busy_desc_num_get(pp, rxq); 1947 if (rx_done) 1948 mvneta_rxq_desc_num_update(pp, rxq, rx_done, rx_done); 1949 1950 if (pp->bm_priv) { 1951 for (i = 0; i < rx_done; i++) { 1952 struct mvneta_rx_desc *rx_desc = 1953 mvneta_rxq_next_desc_get(rxq); 1954 u8 pool_id = MVNETA_RX_GET_BM_POOL_ID(rx_desc); 1955 struct mvneta_bm_pool *bm_pool; 1956 1957 bm_pool = &pp->bm_priv->bm_pools[pool_id]; 1958 /* Return dropped buffer to the pool */ 1959 mvneta_bm_pool_put_bp(pp->bm_priv, bm_pool, 1960 rx_desc->buf_phys_addr); 1961 } 1962 return; 1963 } 1964 1965 for (i = 0; i < rxq->size; i++) { 1966 struct mvneta_rx_desc *rx_desc = rxq->descs + i; 1967 void *data = rxq->buf_virt_addr[i]; 1968 if (!data || !(rx_desc->buf_phys_addr)) 1969 continue; 1970 1971 page_pool_put_full_page(rxq->page_pool, data, false); 1972 } 1973 if (xdp_rxq_info_is_reg(&rxq->xdp_rxq)) 1974 xdp_rxq_info_unreg(&rxq->xdp_rxq); 1975 page_pool_destroy(rxq->page_pool); 1976 rxq->page_pool = NULL; 1977 } 1978 1979 static void 1980 mvneta_update_stats(struct mvneta_port *pp, 1981 struct mvneta_stats *ps) 1982 { 1983 struct mvneta_pcpu_stats *stats = this_cpu_ptr(pp->stats); 1984 1985 u64_stats_update_begin(&stats->syncp); 1986 stats->es.ps.rx_packets += ps->rx_packets; 1987 stats->es.ps.rx_bytes += ps->rx_bytes; 1988 /* xdp */ 1989 stats->es.ps.xdp_redirect += ps->xdp_redirect; 1990 stats->es.ps.xdp_pass += ps->xdp_pass; 1991 stats->es.ps.xdp_drop += ps->xdp_drop; 1992 u64_stats_update_end(&stats->syncp); 1993 } 1994 1995 static inline 1996 int mvneta_rx_refill_queue(struct mvneta_port *pp, struct mvneta_rx_queue *rxq) 1997 { 1998 struct mvneta_rx_desc *rx_desc; 1999 int curr_desc = rxq->first_to_refill; 2000 int i; 2001 2002 for (i = 0; (i < rxq->refill_num) && (i < 64); i++) { 2003 rx_desc = rxq->descs + curr_desc; 2004 if (!(rx_desc->buf_phys_addr)) { 2005 if (mvneta_rx_refill(pp, rx_desc, rxq, GFP_ATOMIC)) { 2006 struct mvneta_pcpu_stats *stats; 2007 2008 pr_err("Can't refill queue %d. Done %d from %d\n", 2009 rxq->id, i, rxq->refill_num); 2010 2011 stats = this_cpu_ptr(pp->stats); 2012 u64_stats_update_begin(&stats->syncp); 2013 stats->es.refill_error++; 2014 u64_stats_update_end(&stats->syncp); 2015 break; 2016 } 2017 } 2018 curr_desc = MVNETA_QUEUE_NEXT_DESC(rxq, curr_desc); 2019 } 2020 rxq->refill_num -= i; 2021 rxq->first_to_refill = curr_desc; 2022 2023 return i; 2024 } 2025 2026 static void 2027 mvneta_xdp_put_buff(struct mvneta_port *pp, struct mvneta_rx_queue *rxq, 2028 struct xdp_buff *xdp, int sync_len, bool napi) 2029 { 2030 struct skb_shared_info *sinfo = xdp_get_shared_info_from_buff(xdp); 2031 int i; 2032 2033 for (i = 0; i < sinfo->nr_frags; i++) 2034 page_pool_put_full_page(rxq->page_pool, 2035 skb_frag_page(&sinfo->frags[i]), napi); 2036 page_pool_put_page(rxq->page_pool, virt_to_head_page(xdp->data), 2037 sync_len, napi); 2038 } 2039 2040 static int 2041 mvneta_xdp_submit_frame(struct mvneta_port *pp, struct mvneta_tx_queue *txq, 2042 struct xdp_frame *xdpf, bool dma_map) 2043 { 2044 struct mvneta_tx_desc *tx_desc; 2045 struct mvneta_tx_buf *buf; 2046 dma_addr_t dma_addr; 2047 2048 if (txq->count >= txq->tx_stop_threshold) 2049 return MVNETA_XDP_DROPPED; 2050 2051 tx_desc = mvneta_txq_next_desc_get(txq); 2052 2053 buf = &txq->buf[txq->txq_put_index]; 2054 if (dma_map) { 2055 /* ndo_xdp_xmit */ 2056 dma_addr = dma_map_single(pp->dev->dev.parent, xdpf->data, 2057 xdpf->len, DMA_TO_DEVICE); 2058 if (dma_mapping_error(pp->dev->dev.parent, dma_addr)) { 2059 mvneta_txq_desc_put(txq); 2060 return MVNETA_XDP_DROPPED; 2061 } 2062 buf->type = MVNETA_TYPE_XDP_NDO; 2063 } else { 2064 struct page *page = virt_to_page(xdpf->data); 2065 2066 dma_addr = page_pool_get_dma_addr(page) + 2067 sizeof(*xdpf) + xdpf->headroom; 2068 dma_sync_single_for_device(pp->dev->dev.parent, dma_addr, 2069 xdpf->len, DMA_BIDIRECTIONAL); 2070 buf->type = MVNETA_TYPE_XDP_TX; 2071 } 2072 buf->xdpf = xdpf; 2073 2074 tx_desc->command = MVNETA_TXD_FLZ_DESC; 2075 tx_desc->buf_phys_addr = dma_addr; 2076 tx_desc->data_size = xdpf->len; 2077 2078 mvneta_txq_inc_put(txq); 2079 txq->pending++; 2080 txq->count++; 2081 2082 return MVNETA_XDP_TX; 2083 } 2084 2085 static int 2086 mvneta_xdp_xmit_back(struct mvneta_port *pp, struct xdp_buff *xdp) 2087 { 2088 struct mvneta_pcpu_stats *stats = this_cpu_ptr(pp->stats); 2089 struct mvneta_tx_queue *txq; 2090 struct netdev_queue *nq; 2091 struct xdp_frame *xdpf; 2092 int cpu; 2093 u32 ret; 2094 2095 xdpf = xdp_convert_buff_to_frame(xdp); 2096 if (unlikely(!xdpf)) 2097 return MVNETA_XDP_DROPPED; 2098 2099 cpu = smp_processor_id(); 2100 txq = &pp->txqs[cpu % txq_number]; 2101 nq = netdev_get_tx_queue(pp->dev, txq->id); 2102 2103 __netif_tx_lock(nq, cpu); 2104 ret = mvneta_xdp_submit_frame(pp, txq, xdpf, false); 2105 if (ret == MVNETA_XDP_TX) { 2106 u64_stats_update_begin(&stats->syncp); 2107 stats->es.ps.tx_bytes += xdpf->len; 2108 stats->es.ps.tx_packets++; 2109 stats->es.ps.xdp_tx++; 2110 u64_stats_update_end(&stats->syncp); 2111 2112 mvneta_txq_pend_desc_add(pp, txq, 0); 2113 } else { 2114 u64_stats_update_begin(&stats->syncp); 2115 stats->es.ps.xdp_tx_err++; 2116 u64_stats_update_end(&stats->syncp); 2117 } 2118 __netif_tx_unlock(nq); 2119 2120 return ret; 2121 } 2122 2123 static int 2124 mvneta_xdp_xmit(struct net_device *dev, int num_frame, 2125 struct xdp_frame **frames, u32 flags) 2126 { 2127 struct mvneta_port *pp = netdev_priv(dev); 2128 struct mvneta_pcpu_stats *stats = this_cpu_ptr(pp->stats); 2129 int i, nxmit_byte = 0, nxmit = num_frame; 2130 int cpu = smp_processor_id(); 2131 struct mvneta_tx_queue *txq; 2132 struct netdev_queue *nq; 2133 u32 ret; 2134 2135 if (unlikely(test_bit(__MVNETA_DOWN, &pp->state))) 2136 return -ENETDOWN; 2137 2138 if (unlikely(flags & ~XDP_XMIT_FLAGS_MASK)) 2139 return -EINVAL; 2140 2141 txq = &pp->txqs[cpu % txq_number]; 2142 nq = netdev_get_tx_queue(pp->dev, txq->id); 2143 2144 __netif_tx_lock(nq, cpu); 2145 for (i = 0; i < num_frame; i++) { 2146 ret = mvneta_xdp_submit_frame(pp, txq, frames[i], true); 2147 if (ret == MVNETA_XDP_TX) { 2148 nxmit_byte += frames[i]->len; 2149 } else { 2150 xdp_return_frame_rx_napi(frames[i]); 2151 nxmit--; 2152 } 2153 } 2154 2155 if (unlikely(flags & XDP_XMIT_FLUSH)) 2156 mvneta_txq_pend_desc_add(pp, txq, 0); 2157 __netif_tx_unlock(nq); 2158 2159 u64_stats_update_begin(&stats->syncp); 2160 stats->es.ps.tx_bytes += nxmit_byte; 2161 stats->es.ps.tx_packets += nxmit; 2162 stats->es.ps.xdp_xmit += nxmit; 2163 stats->es.ps.xdp_xmit_err += num_frame - nxmit; 2164 u64_stats_update_end(&stats->syncp); 2165 2166 return nxmit; 2167 } 2168 2169 static int 2170 mvneta_run_xdp(struct mvneta_port *pp, struct mvneta_rx_queue *rxq, 2171 struct bpf_prog *prog, struct xdp_buff *xdp, 2172 u32 frame_sz, struct mvneta_stats *stats) 2173 { 2174 unsigned int len, data_len, sync; 2175 u32 ret, act; 2176 2177 len = xdp->data_end - xdp->data_hard_start - pp->rx_offset_correction; 2178 data_len = xdp->data_end - xdp->data; 2179 act = bpf_prog_run_xdp(prog, xdp); 2180 2181 /* Due xdp_adjust_tail: DMA sync for_device cover max len CPU touch */ 2182 sync = xdp->data_end - xdp->data_hard_start - pp->rx_offset_correction; 2183 sync = max(sync, len); 2184 2185 switch (act) { 2186 case XDP_PASS: 2187 stats->xdp_pass++; 2188 return MVNETA_XDP_PASS; 2189 case XDP_REDIRECT: { 2190 int err; 2191 2192 err = xdp_do_redirect(pp->dev, xdp, prog); 2193 if (unlikely(err)) { 2194 mvneta_xdp_put_buff(pp, rxq, xdp, sync, true); 2195 ret = MVNETA_XDP_DROPPED; 2196 } else { 2197 ret = MVNETA_XDP_REDIR; 2198 stats->xdp_redirect++; 2199 } 2200 break; 2201 } 2202 case XDP_TX: 2203 ret = mvneta_xdp_xmit_back(pp, xdp); 2204 if (ret != MVNETA_XDP_TX) 2205 mvneta_xdp_put_buff(pp, rxq, xdp, sync, true); 2206 break; 2207 default: 2208 bpf_warn_invalid_xdp_action(act); 2209 fallthrough; 2210 case XDP_ABORTED: 2211 trace_xdp_exception(pp->dev, prog, act); 2212 fallthrough; 2213 case XDP_DROP: 2214 mvneta_xdp_put_buff(pp, rxq, xdp, sync, true); 2215 ret = MVNETA_XDP_DROPPED; 2216 stats->xdp_drop++; 2217 break; 2218 } 2219 2220 stats->rx_bytes += frame_sz + xdp->data_end - xdp->data - data_len; 2221 stats->rx_packets++; 2222 2223 return ret; 2224 } 2225 2226 static void 2227 mvneta_swbm_rx_frame(struct mvneta_port *pp, 2228 struct mvneta_rx_desc *rx_desc, 2229 struct mvneta_rx_queue *rxq, 2230 struct xdp_buff *xdp, int *size, 2231 struct page *page) 2232 { 2233 unsigned char *data = page_address(page); 2234 int data_len = -MVNETA_MH_SIZE, len; 2235 struct net_device *dev = pp->dev; 2236 enum dma_data_direction dma_dir; 2237 struct skb_shared_info *sinfo; 2238 2239 if (*size > MVNETA_MAX_RX_BUF_SIZE) { 2240 len = MVNETA_MAX_RX_BUF_SIZE; 2241 data_len += len; 2242 } else { 2243 len = *size; 2244 data_len += len - ETH_FCS_LEN; 2245 } 2246 *size = *size - len; 2247 2248 dma_dir = page_pool_get_dma_dir(rxq->page_pool); 2249 dma_sync_single_for_cpu(dev->dev.parent, 2250 rx_desc->buf_phys_addr, 2251 len, dma_dir); 2252 2253 rx_desc->buf_phys_addr = 0; 2254 2255 /* Prefetch header */ 2256 prefetch(data); 2257 2258 xdp->data_hard_start = data; 2259 xdp->data = data + pp->rx_offset_correction + MVNETA_MH_SIZE; 2260 xdp->data_end = xdp->data + data_len; 2261 xdp_set_data_meta_invalid(xdp); 2262 2263 sinfo = xdp_get_shared_info_from_buff(xdp); 2264 sinfo->nr_frags = 0; 2265 } 2266 2267 static void 2268 mvneta_swbm_add_rx_fragment(struct mvneta_port *pp, 2269 struct mvneta_rx_desc *rx_desc, 2270 struct mvneta_rx_queue *rxq, 2271 struct xdp_buff *xdp, int *size, 2272 struct page *page) 2273 { 2274 struct skb_shared_info *sinfo = xdp_get_shared_info_from_buff(xdp); 2275 struct net_device *dev = pp->dev; 2276 enum dma_data_direction dma_dir; 2277 int data_len, len; 2278 2279 if (*size > MVNETA_MAX_RX_BUF_SIZE) { 2280 len = MVNETA_MAX_RX_BUF_SIZE; 2281 data_len = len; 2282 } else { 2283 len = *size; 2284 data_len = len - ETH_FCS_LEN; 2285 } 2286 dma_dir = page_pool_get_dma_dir(rxq->page_pool); 2287 dma_sync_single_for_cpu(dev->dev.parent, 2288 rx_desc->buf_phys_addr, 2289 len, dma_dir); 2290 2291 if (data_len > 0 && sinfo->nr_frags < MAX_SKB_FRAGS) { 2292 skb_frag_t *frag = &sinfo->frags[sinfo->nr_frags]; 2293 2294 skb_frag_off_set(frag, pp->rx_offset_correction); 2295 skb_frag_size_set(frag, data_len); 2296 __skb_frag_set_page(frag, page); 2297 sinfo->nr_frags++; 2298 2299 rx_desc->buf_phys_addr = 0; 2300 } 2301 *size -= len; 2302 } 2303 2304 static struct sk_buff * 2305 mvneta_swbm_build_skb(struct mvneta_port *pp, struct mvneta_rx_queue *rxq, 2306 struct xdp_buff *xdp, u32 desc_status) 2307 { 2308 struct skb_shared_info *sinfo = xdp_get_shared_info_from_buff(xdp); 2309 int i, num_frags = sinfo->nr_frags; 2310 struct sk_buff *skb; 2311 2312 skb = build_skb(xdp->data_hard_start, PAGE_SIZE); 2313 if (!skb) 2314 return ERR_PTR(-ENOMEM); 2315 2316 page_pool_release_page(rxq->page_pool, virt_to_page(xdp->data)); 2317 2318 skb_reserve(skb, xdp->data - xdp->data_hard_start); 2319 skb_put(skb, xdp->data_end - xdp->data); 2320 mvneta_rx_csum(pp, desc_status, skb); 2321 2322 for (i = 0; i < num_frags; i++) { 2323 skb_frag_t *frag = &sinfo->frags[i]; 2324 2325 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, 2326 skb_frag_page(frag), skb_frag_off(frag), 2327 skb_frag_size(frag), PAGE_SIZE); 2328 page_pool_release_page(rxq->page_pool, skb_frag_page(frag)); 2329 } 2330 2331 return skb; 2332 } 2333 2334 /* Main rx processing when using software buffer management */ 2335 static int mvneta_rx_swbm(struct napi_struct *napi, 2336 struct mvneta_port *pp, int budget, 2337 struct mvneta_rx_queue *rxq) 2338 { 2339 int rx_proc = 0, rx_todo, refill, size = 0; 2340 struct net_device *dev = pp->dev; 2341 struct xdp_buff xdp_buf = { 2342 .frame_sz = PAGE_SIZE, 2343 .rxq = &rxq->xdp_rxq, 2344 }; 2345 struct mvneta_stats ps = {}; 2346 struct bpf_prog *xdp_prog; 2347 u32 desc_status, frame_sz; 2348 2349 /* Get number of received packets */ 2350 rx_todo = mvneta_rxq_busy_desc_num_get(pp, rxq); 2351 2352 rcu_read_lock(); 2353 xdp_prog = READ_ONCE(pp->xdp_prog); 2354 2355 /* Fairness NAPI loop */ 2356 while (rx_proc < budget && rx_proc < rx_todo) { 2357 struct mvneta_rx_desc *rx_desc = mvneta_rxq_next_desc_get(rxq); 2358 u32 rx_status, index; 2359 struct sk_buff *skb; 2360 struct page *page; 2361 2362 index = rx_desc - rxq->descs; 2363 page = (struct page *)rxq->buf_virt_addr[index]; 2364 2365 rx_status = rx_desc->status; 2366 rx_proc++; 2367 rxq->refill_num++; 2368 2369 if (rx_status & MVNETA_RXD_FIRST_DESC) { 2370 /* Check errors only for FIRST descriptor */ 2371 if (rx_status & MVNETA_RXD_ERR_SUMMARY) { 2372 mvneta_rx_error(pp, rx_desc); 2373 goto next; 2374 } 2375 2376 size = rx_desc->data_size; 2377 frame_sz = size - ETH_FCS_LEN; 2378 desc_status = rx_status; 2379 2380 mvneta_swbm_rx_frame(pp, rx_desc, rxq, &xdp_buf, 2381 &size, page); 2382 } else { 2383 if (unlikely(!xdp_buf.data_hard_start)) { 2384 rx_desc->buf_phys_addr = 0; 2385 page_pool_put_full_page(rxq->page_pool, page, 2386 true); 2387 continue; 2388 } 2389 2390 mvneta_swbm_add_rx_fragment(pp, rx_desc, rxq, &xdp_buf, 2391 &size, page); 2392 } /* Middle or Last descriptor */ 2393 2394 if (!(rx_status & MVNETA_RXD_LAST_DESC)) 2395 /* no last descriptor this time */ 2396 continue; 2397 2398 if (size) { 2399 mvneta_xdp_put_buff(pp, rxq, &xdp_buf, -1, true); 2400 goto next; 2401 } 2402 2403 if (xdp_prog && 2404 mvneta_run_xdp(pp, rxq, xdp_prog, &xdp_buf, frame_sz, &ps)) 2405 goto next; 2406 2407 skb = mvneta_swbm_build_skb(pp, rxq, &xdp_buf, desc_status); 2408 if (IS_ERR(skb)) { 2409 struct mvneta_pcpu_stats *stats = this_cpu_ptr(pp->stats); 2410 2411 mvneta_xdp_put_buff(pp, rxq, &xdp_buf, -1, true); 2412 2413 u64_stats_update_begin(&stats->syncp); 2414 stats->es.skb_alloc_error++; 2415 stats->rx_dropped++; 2416 u64_stats_update_end(&stats->syncp); 2417 2418 goto next; 2419 } 2420 2421 ps.rx_bytes += skb->len; 2422 ps.rx_packets++; 2423 2424 skb->protocol = eth_type_trans(skb, dev); 2425 napi_gro_receive(napi, skb); 2426 next: 2427 xdp_buf.data_hard_start = NULL; 2428 } 2429 rcu_read_unlock(); 2430 2431 if (xdp_buf.data_hard_start) 2432 mvneta_xdp_put_buff(pp, rxq, &xdp_buf, -1, true); 2433 2434 if (ps.xdp_redirect) 2435 xdp_do_flush_map(); 2436 2437 if (ps.rx_packets) 2438 mvneta_update_stats(pp, &ps); 2439 2440 /* return some buffers to hardware queue, one at a time is too slow */ 2441 refill = mvneta_rx_refill_queue(pp, rxq); 2442 2443 /* Update rxq management counters */ 2444 mvneta_rxq_desc_num_update(pp, rxq, rx_proc, refill); 2445 2446 return ps.rx_packets; 2447 } 2448 2449 /* Main rx processing when using hardware buffer management */ 2450 static int mvneta_rx_hwbm(struct napi_struct *napi, 2451 struct mvneta_port *pp, int rx_todo, 2452 struct mvneta_rx_queue *rxq) 2453 { 2454 struct net_device *dev = pp->dev; 2455 int rx_done; 2456 u32 rcvd_pkts = 0; 2457 u32 rcvd_bytes = 0; 2458 2459 /* Get number of received packets */ 2460 rx_done = mvneta_rxq_busy_desc_num_get(pp, rxq); 2461 2462 if (rx_todo > rx_done) 2463 rx_todo = rx_done; 2464 2465 rx_done = 0; 2466 2467 /* Fairness NAPI loop */ 2468 while (rx_done < rx_todo) { 2469 struct mvneta_rx_desc *rx_desc = mvneta_rxq_next_desc_get(rxq); 2470 struct mvneta_bm_pool *bm_pool = NULL; 2471 struct sk_buff *skb; 2472 unsigned char *data; 2473 dma_addr_t phys_addr; 2474 u32 rx_status, frag_size; 2475 int rx_bytes, err; 2476 u8 pool_id; 2477 2478 rx_done++; 2479 rx_status = rx_desc->status; 2480 rx_bytes = rx_desc->data_size - (ETH_FCS_LEN + MVNETA_MH_SIZE); 2481 data = (u8 *)(uintptr_t)rx_desc->buf_cookie; 2482 phys_addr = rx_desc->buf_phys_addr; 2483 pool_id = MVNETA_RX_GET_BM_POOL_ID(rx_desc); 2484 bm_pool = &pp->bm_priv->bm_pools[pool_id]; 2485 2486 if (!mvneta_rxq_desc_is_first_last(rx_status) || 2487 (rx_status & MVNETA_RXD_ERR_SUMMARY)) { 2488 err_drop_frame_ret_pool: 2489 /* Return the buffer to the pool */ 2490 mvneta_bm_pool_put_bp(pp->bm_priv, bm_pool, 2491 rx_desc->buf_phys_addr); 2492 err_drop_frame: 2493 mvneta_rx_error(pp, rx_desc); 2494 /* leave the descriptor untouched */ 2495 continue; 2496 } 2497 2498 if (rx_bytes <= rx_copybreak) { 2499 /* better copy a small frame and not unmap the DMA region */ 2500 skb = netdev_alloc_skb_ip_align(dev, rx_bytes); 2501 if (unlikely(!skb)) 2502 goto err_drop_frame_ret_pool; 2503 2504 dma_sync_single_range_for_cpu(&pp->bm_priv->pdev->dev, 2505 rx_desc->buf_phys_addr, 2506 MVNETA_MH_SIZE + NET_SKB_PAD, 2507 rx_bytes, 2508 DMA_FROM_DEVICE); 2509 skb_put_data(skb, data + MVNETA_MH_SIZE + NET_SKB_PAD, 2510 rx_bytes); 2511 2512 skb->protocol = eth_type_trans(skb, dev); 2513 mvneta_rx_csum(pp, rx_status, skb); 2514 napi_gro_receive(napi, skb); 2515 2516 rcvd_pkts++; 2517 rcvd_bytes += rx_bytes; 2518 2519 /* Return the buffer to the pool */ 2520 mvneta_bm_pool_put_bp(pp->bm_priv, bm_pool, 2521 rx_desc->buf_phys_addr); 2522 2523 /* leave the descriptor and buffer untouched */ 2524 continue; 2525 } 2526 2527 /* Refill processing */ 2528 err = hwbm_pool_refill(&bm_pool->hwbm_pool, GFP_ATOMIC); 2529 if (err) { 2530 struct mvneta_pcpu_stats *stats; 2531 2532 netdev_err(dev, "Linux processing - Can't refill\n"); 2533 2534 stats = this_cpu_ptr(pp->stats); 2535 u64_stats_update_begin(&stats->syncp); 2536 stats->es.refill_error++; 2537 u64_stats_update_end(&stats->syncp); 2538 2539 goto err_drop_frame_ret_pool; 2540 } 2541 2542 frag_size = bm_pool->hwbm_pool.frag_size; 2543 2544 skb = build_skb(data, frag_size > PAGE_SIZE ? 0 : frag_size); 2545 2546 /* After refill old buffer has to be unmapped regardless 2547 * the skb is successfully built or not. 2548 */ 2549 dma_unmap_single(&pp->bm_priv->pdev->dev, phys_addr, 2550 bm_pool->buf_size, DMA_FROM_DEVICE); 2551 if (!skb) 2552 goto err_drop_frame; 2553 2554 rcvd_pkts++; 2555 rcvd_bytes += rx_bytes; 2556 2557 /* Linux processing */ 2558 skb_reserve(skb, MVNETA_MH_SIZE + NET_SKB_PAD); 2559 skb_put(skb, rx_bytes); 2560 2561 skb->protocol = eth_type_trans(skb, dev); 2562 2563 mvneta_rx_csum(pp, rx_status, skb); 2564 2565 napi_gro_receive(napi, skb); 2566 } 2567 2568 if (rcvd_pkts) { 2569 struct mvneta_pcpu_stats *stats = this_cpu_ptr(pp->stats); 2570 2571 u64_stats_update_begin(&stats->syncp); 2572 stats->es.ps.rx_packets += rcvd_pkts; 2573 stats->es.ps.rx_bytes += rcvd_bytes; 2574 u64_stats_update_end(&stats->syncp); 2575 } 2576 2577 /* Update rxq management counters */ 2578 mvneta_rxq_desc_num_update(pp, rxq, rx_done, rx_done); 2579 2580 return rx_done; 2581 } 2582 2583 static inline void 2584 mvneta_tso_put_hdr(struct sk_buff *skb, 2585 struct mvneta_port *pp, struct mvneta_tx_queue *txq) 2586 { 2587 int hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb); 2588 struct mvneta_tx_buf *buf = &txq->buf[txq->txq_put_index]; 2589 struct mvneta_tx_desc *tx_desc; 2590 2591 tx_desc = mvneta_txq_next_desc_get(txq); 2592 tx_desc->data_size = hdr_len; 2593 tx_desc->command = mvneta_skb_tx_csum(pp, skb); 2594 tx_desc->command |= MVNETA_TXD_F_DESC; 2595 tx_desc->buf_phys_addr = txq->tso_hdrs_phys + 2596 txq->txq_put_index * TSO_HEADER_SIZE; 2597 buf->type = MVNETA_TYPE_SKB; 2598 buf->skb = NULL; 2599 2600 mvneta_txq_inc_put(txq); 2601 } 2602 2603 static inline int 2604 mvneta_tso_put_data(struct net_device *dev, struct mvneta_tx_queue *txq, 2605 struct sk_buff *skb, char *data, int size, 2606 bool last_tcp, bool is_last) 2607 { 2608 struct mvneta_tx_buf *buf = &txq->buf[txq->txq_put_index]; 2609 struct mvneta_tx_desc *tx_desc; 2610 2611 tx_desc = mvneta_txq_next_desc_get(txq); 2612 tx_desc->data_size = size; 2613 tx_desc->buf_phys_addr = dma_map_single(dev->dev.parent, data, 2614 size, DMA_TO_DEVICE); 2615 if (unlikely(dma_mapping_error(dev->dev.parent, 2616 tx_desc->buf_phys_addr))) { 2617 mvneta_txq_desc_put(txq); 2618 return -ENOMEM; 2619 } 2620 2621 tx_desc->command = 0; 2622 buf->type = MVNETA_TYPE_SKB; 2623 buf->skb = NULL; 2624 2625 if (last_tcp) { 2626 /* last descriptor in the TCP packet */ 2627 tx_desc->command = MVNETA_TXD_L_DESC; 2628 2629 /* last descriptor in SKB */ 2630 if (is_last) 2631 buf->skb = skb; 2632 } 2633 mvneta_txq_inc_put(txq); 2634 return 0; 2635 } 2636 2637 static int mvneta_tx_tso(struct sk_buff *skb, struct net_device *dev, 2638 struct mvneta_tx_queue *txq) 2639 { 2640 int hdr_len, total_len, data_left; 2641 int desc_count = 0; 2642 struct mvneta_port *pp = netdev_priv(dev); 2643 struct tso_t tso; 2644 int i; 2645 2646 /* Count needed descriptors */ 2647 if ((txq->count + tso_count_descs(skb)) >= txq->size) 2648 return 0; 2649 2650 if (skb_headlen(skb) < (skb_transport_offset(skb) + tcp_hdrlen(skb))) { 2651 pr_info("*** Is this even possible???!?!?\n"); 2652 return 0; 2653 } 2654 2655 /* Initialize the TSO handler, and prepare the first payload */ 2656 hdr_len = tso_start(skb, &tso); 2657 2658 total_len = skb->len - hdr_len; 2659 while (total_len > 0) { 2660 char *hdr; 2661 2662 data_left = min_t(int, skb_shinfo(skb)->gso_size, total_len); 2663 total_len -= data_left; 2664 desc_count++; 2665 2666 /* prepare packet headers: MAC + IP + TCP */ 2667 hdr = txq->tso_hdrs + txq->txq_put_index * TSO_HEADER_SIZE; 2668 tso_build_hdr(skb, hdr, &tso, data_left, total_len == 0); 2669 2670 mvneta_tso_put_hdr(skb, pp, txq); 2671 2672 while (data_left > 0) { 2673 int size; 2674 desc_count++; 2675 2676 size = min_t(int, tso.size, data_left); 2677 2678 if (mvneta_tso_put_data(dev, txq, skb, 2679 tso.data, size, 2680 size == data_left, 2681 total_len == 0)) 2682 goto err_release; 2683 data_left -= size; 2684 2685 tso_build_data(skb, &tso, size); 2686 } 2687 } 2688 2689 return desc_count; 2690 2691 err_release: 2692 /* Release all used data descriptors; header descriptors must not 2693 * be DMA-unmapped. 2694 */ 2695 for (i = desc_count - 1; i >= 0; i--) { 2696 struct mvneta_tx_desc *tx_desc = txq->descs + i; 2697 if (!IS_TSO_HEADER(txq, tx_desc->buf_phys_addr)) 2698 dma_unmap_single(pp->dev->dev.parent, 2699 tx_desc->buf_phys_addr, 2700 tx_desc->data_size, 2701 DMA_TO_DEVICE); 2702 mvneta_txq_desc_put(txq); 2703 } 2704 return 0; 2705 } 2706 2707 /* Handle tx fragmentation processing */ 2708 static int mvneta_tx_frag_process(struct mvneta_port *pp, struct sk_buff *skb, 2709 struct mvneta_tx_queue *txq) 2710 { 2711 struct mvneta_tx_desc *tx_desc; 2712 int i, nr_frags = skb_shinfo(skb)->nr_frags; 2713 2714 for (i = 0; i < nr_frags; i++) { 2715 struct mvneta_tx_buf *buf = &txq->buf[txq->txq_put_index]; 2716 skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 2717 void *addr = skb_frag_address(frag); 2718 2719 tx_desc = mvneta_txq_next_desc_get(txq); 2720 tx_desc->data_size = skb_frag_size(frag); 2721 2722 tx_desc->buf_phys_addr = 2723 dma_map_single(pp->dev->dev.parent, addr, 2724 tx_desc->data_size, DMA_TO_DEVICE); 2725 2726 if (dma_mapping_error(pp->dev->dev.parent, 2727 tx_desc->buf_phys_addr)) { 2728 mvneta_txq_desc_put(txq); 2729 goto error; 2730 } 2731 2732 if (i == nr_frags - 1) { 2733 /* Last descriptor */ 2734 tx_desc->command = MVNETA_TXD_L_DESC | MVNETA_TXD_Z_PAD; 2735 buf->skb = skb; 2736 } else { 2737 /* Descriptor in the middle: Not First, Not Last */ 2738 tx_desc->command = 0; 2739 buf->skb = NULL; 2740 } 2741 buf->type = MVNETA_TYPE_SKB; 2742 mvneta_txq_inc_put(txq); 2743 } 2744 2745 return 0; 2746 2747 error: 2748 /* Release all descriptors that were used to map fragments of 2749 * this packet, as well as the corresponding DMA mappings 2750 */ 2751 for (i = i - 1; i >= 0; i--) { 2752 tx_desc = txq->descs + i; 2753 dma_unmap_single(pp->dev->dev.parent, 2754 tx_desc->buf_phys_addr, 2755 tx_desc->data_size, 2756 DMA_TO_DEVICE); 2757 mvneta_txq_desc_put(txq); 2758 } 2759 2760 return -ENOMEM; 2761 } 2762 2763 /* Main tx processing */ 2764 static netdev_tx_t mvneta_tx(struct sk_buff *skb, struct net_device *dev) 2765 { 2766 struct mvneta_port *pp = netdev_priv(dev); 2767 u16 txq_id = skb_get_queue_mapping(skb); 2768 struct mvneta_tx_queue *txq = &pp->txqs[txq_id]; 2769 struct mvneta_tx_buf *buf = &txq->buf[txq->txq_put_index]; 2770 struct mvneta_tx_desc *tx_desc; 2771 int len = skb->len; 2772 int frags = 0; 2773 u32 tx_cmd; 2774 2775 if (!netif_running(dev)) 2776 goto out; 2777 2778 if (skb_is_gso(skb)) { 2779 frags = mvneta_tx_tso(skb, dev, txq); 2780 goto out; 2781 } 2782 2783 frags = skb_shinfo(skb)->nr_frags + 1; 2784 2785 /* Get a descriptor for the first part of the packet */ 2786 tx_desc = mvneta_txq_next_desc_get(txq); 2787 2788 tx_cmd = mvneta_skb_tx_csum(pp, skb); 2789 2790 tx_desc->data_size = skb_headlen(skb); 2791 2792 tx_desc->buf_phys_addr = dma_map_single(dev->dev.parent, skb->data, 2793 tx_desc->data_size, 2794 DMA_TO_DEVICE); 2795 if (unlikely(dma_mapping_error(dev->dev.parent, 2796 tx_desc->buf_phys_addr))) { 2797 mvneta_txq_desc_put(txq); 2798 frags = 0; 2799 goto out; 2800 } 2801 2802 buf->type = MVNETA_TYPE_SKB; 2803 if (frags == 1) { 2804 /* First and Last descriptor */ 2805 tx_cmd |= MVNETA_TXD_FLZ_DESC; 2806 tx_desc->command = tx_cmd; 2807 buf->skb = skb; 2808 mvneta_txq_inc_put(txq); 2809 } else { 2810 /* First but not Last */ 2811 tx_cmd |= MVNETA_TXD_F_DESC; 2812 buf->skb = NULL; 2813 mvneta_txq_inc_put(txq); 2814 tx_desc->command = tx_cmd; 2815 /* Continue with other skb fragments */ 2816 if (mvneta_tx_frag_process(pp, skb, txq)) { 2817 dma_unmap_single(dev->dev.parent, 2818 tx_desc->buf_phys_addr, 2819 tx_desc->data_size, 2820 DMA_TO_DEVICE); 2821 mvneta_txq_desc_put(txq); 2822 frags = 0; 2823 goto out; 2824 } 2825 } 2826 2827 out: 2828 if (frags > 0) { 2829 struct netdev_queue *nq = netdev_get_tx_queue(dev, txq_id); 2830 struct mvneta_pcpu_stats *stats = this_cpu_ptr(pp->stats); 2831 2832 netdev_tx_sent_queue(nq, len); 2833 2834 txq->count += frags; 2835 if (txq->count >= txq->tx_stop_threshold) 2836 netif_tx_stop_queue(nq); 2837 2838 if (!netdev_xmit_more() || netif_xmit_stopped(nq) || 2839 txq->pending + frags > MVNETA_TXQ_DEC_SENT_MASK) 2840 mvneta_txq_pend_desc_add(pp, txq, frags); 2841 else 2842 txq->pending += frags; 2843 2844 u64_stats_update_begin(&stats->syncp); 2845 stats->es.ps.tx_bytes += len; 2846 stats->es.ps.tx_packets++; 2847 u64_stats_update_end(&stats->syncp); 2848 } else { 2849 dev->stats.tx_dropped++; 2850 dev_kfree_skb_any(skb); 2851 } 2852 2853 return NETDEV_TX_OK; 2854 } 2855 2856 2857 /* Free tx resources, when resetting a port */ 2858 static void mvneta_txq_done_force(struct mvneta_port *pp, 2859 struct mvneta_tx_queue *txq) 2860 2861 { 2862 struct netdev_queue *nq = netdev_get_tx_queue(pp->dev, txq->id); 2863 int tx_done = txq->count; 2864 2865 mvneta_txq_bufs_free(pp, txq, tx_done, nq, false); 2866 2867 /* reset txq */ 2868 txq->count = 0; 2869 txq->txq_put_index = 0; 2870 txq->txq_get_index = 0; 2871 } 2872 2873 /* Handle tx done - called in softirq context. The <cause_tx_done> argument 2874 * must be a valid cause according to MVNETA_TXQ_INTR_MASK_ALL. 2875 */ 2876 static void mvneta_tx_done_gbe(struct mvneta_port *pp, u32 cause_tx_done) 2877 { 2878 struct mvneta_tx_queue *txq; 2879 struct netdev_queue *nq; 2880 int cpu = smp_processor_id(); 2881 2882 while (cause_tx_done) { 2883 txq = mvneta_tx_done_policy(pp, cause_tx_done); 2884 2885 nq = netdev_get_tx_queue(pp->dev, txq->id); 2886 __netif_tx_lock(nq, cpu); 2887 2888 if (txq->count) 2889 mvneta_txq_done(pp, txq); 2890 2891 __netif_tx_unlock(nq); 2892 cause_tx_done &= ~((1 << txq->id)); 2893 } 2894 } 2895 2896 /* Compute crc8 of the specified address, using a unique algorithm , 2897 * according to hw spec, different than generic crc8 algorithm 2898 */ 2899 static int mvneta_addr_crc(unsigned char *addr) 2900 { 2901 int crc = 0; 2902 int i; 2903 2904 for (i = 0; i < ETH_ALEN; i++) { 2905 int j; 2906 2907 crc = (crc ^ addr[i]) << 8; 2908 for (j = 7; j >= 0; j--) { 2909 if (crc & (0x100 << j)) 2910 crc ^= 0x107 << j; 2911 } 2912 } 2913 2914 return crc; 2915 } 2916 2917 /* This method controls the net device special MAC multicast support. 2918 * The Special Multicast Table for MAC addresses supports MAC of the form 2919 * 0x01-00-5E-00-00-XX (where XX is between 0x00 and 0xFF). 2920 * The MAC DA[7:0] bits are used as a pointer to the Special Multicast 2921 * Table entries in the DA-Filter table. This method set the Special 2922 * Multicast Table appropriate entry. 2923 */ 2924 static void mvneta_set_special_mcast_addr(struct mvneta_port *pp, 2925 unsigned char last_byte, 2926 int queue) 2927 { 2928 unsigned int smc_table_reg; 2929 unsigned int tbl_offset; 2930 unsigned int reg_offset; 2931 2932 /* Register offset from SMC table base */ 2933 tbl_offset = (last_byte / 4); 2934 /* Entry offset within the above reg */ 2935 reg_offset = last_byte % 4; 2936 2937 smc_table_reg = mvreg_read(pp, (MVNETA_DA_FILT_SPEC_MCAST 2938 + tbl_offset * 4)); 2939 2940 if (queue == -1) 2941 smc_table_reg &= ~(0xff << (8 * reg_offset)); 2942 else { 2943 smc_table_reg &= ~(0xff << (8 * reg_offset)); 2944 smc_table_reg |= ((0x01 | (queue << 1)) << (8 * reg_offset)); 2945 } 2946 2947 mvreg_write(pp, MVNETA_DA_FILT_SPEC_MCAST + tbl_offset * 4, 2948 smc_table_reg); 2949 } 2950 2951 /* This method controls the network device Other MAC multicast support. 2952 * The Other Multicast Table is used for multicast of another type. 2953 * A CRC-8 is used as an index to the Other Multicast Table entries 2954 * in the DA-Filter table. 2955 * The method gets the CRC-8 value from the calling routine and 2956 * sets the Other Multicast Table appropriate entry according to the 2957 * specified CRC-8 . 2958 */ 2959 static void mvneta_set_other_mcast_addr(struct mvneta_port *pp, 2960 unsigned char crc8, 2961 int queue) 2962 { 2963 unsigned int omc_table_reg; 2964 unsigned int tbl_offset; 2965 unsigned int reg_offset; 2966 2967 tbl_offset = (crc8 / 4) * 4; /* Register offset from OMC table base */ 2968 reg_offset = crc8 % 4; /* Entry offset within the above reg */ 2969 2970 omc_table_reg = mvreg_read(pp, MVNETA_DA_FILT_OTH_MCAST + tbl_offset); 2971 2972 if (queue == -1) { 2973 /* Clear accepts frame bit at specified Other DA table entry */ 2974 omc_table_reg &= ~(0xff << (8 * reg_offset)); 2975 } else { 2976 omc_table_reg &= ~(0xff << (8 * reg_offset)); 2977 omc_table_reg |= ((0x01 | (queue << 1)) << (8 * reg_offset)); 2978 } 2979 2980 mvreg_write(pp, MVNETA_DA_FILT_OTH_MCAST + tbl_offset, omc_table_reg); 2981 } 2982 2983 /* The network device supports multicast using two tables: 2984 * 1) Special Multicast Table for MAC addresses of the form 2985 * 0x01-00-5E-00-00-XX (where XX is between 0x00 and 0xFF). 2986 * The MAC DA[7:0] bits are used as a pointer to the Special Multicast 2987 * Table entries in the DA-Filter table. 2988 * 2) Other Multicast Table for multicast of another type. A CRC-8 value 2989 * is used as an index to the Other Multicast Table entries in the 2990 * DA-Filter table. 2991 */ 2992 static int mvneta_mcast_addr_set(struct mvneta_port *pp, unsigned char *p_addr, 2993 int queue) 2994 { 2995 unsigned char crc_result = 0; 2996 2997 if (memcmp(p_addr, "\x01\x00\x5e\x00\x00", 5) == 0) { 2998 mvneta_set_special_mcast_addr(pp, p_addr[5], queue); 2999 return 0; 3000 } 3001 3002 crc_result = mvneta_addr_crc(p_addr); 3003 if (queue == -1) { 3004 if (pp->mcast_count[crc_result] == 0) { 3005 netdev_info(pp->dev, "No valid Mcast for crc8=0x%02x\n", 3006 crc_result); 3007 return -EINVAL; 3008 } 3009 3010 pp->mcast_count[crc_result]--; 3011 if (pp->mcast_count[crc_result] != 0) { 3012 netdev_info(pp->dev, 3013 "After delete there are %d valid Mcast for crc8=0x%02x\n", 3014 pp->mcast_count[crc_result], crc_result); 3015 return -EINVAL; 3016 } 3017 } else 3018 pp->mcast_count[crc_result]++; 3019 3020 mvneta_set_other_mcast_addr(pp, crc_result, queue); 3021 3022 return 0; 3023 } 3024 3025 /* Configure Fitering mode of Ethernet port */ 3026 static void mvneta_rx_unicast_promisc_set(struct mvneta_port *pp, 3027 int is_promisc) 3028 { 3029 u32 port_cfg_reg, val; 3030 3031 port_cfg_reg = mvreg_read(pp, MVNETA_PORT_CONFIG); 3032 3033 val = mvreg_read(pp, MVNETA_TYPE_PRIO); 3034 3035 /* Set / Clear UPM bit in port configuration register */ 3036 if (is_promisc) { 3037 /* Accept all Unicast addresses */ 3038 port_cfg_reg |= MVNETA_UNI_PROMISC_MODE; 3039 val |= MVNETA_FORCE_UNI; 3040 mvreg_write(pp, MVNETA_MAC_ADDR_LOW, 0xffff); 3041 mvreg_write(pp, MVNETA_MAC_ADDR_HIGH, 0xffffffff); 3042 } else { 3043 /* Reject all Unicast addresses */ 3044 port_cfg_reg &= ~MVNETA_UNI_PROMISC_MODE; 3045 val &= ~MVNETA_FORCE_UNI; 3046 } 3047 3048 mvreg_write(pp, MVNETA_PORT_CONFIG, port_cfg_reg); 3049 mvreg_write(pp, MVNETA_TYPE_PRIO, val); 3050 } 3051 3052 /* register unicast and multicast addresses */ 3053 static void mvneta_set_rx_mode(struct net_device *dev) 3054 { 3055 struct mvneta_port *pp = netdev_priv(dev); 3056 struct netdev_hw_addr *ha; 3057 3058 if (dev->flags & IFF_PROMISC) { 3059 /* Accept all: Multicast + Unicast */ 3060 mvneta_rx_unicast_promisc_set(pp, 1); 3061 mvneta_set_ucast_table(pp, pp->rxq_def); 3062 mvneta_set_special_mcast_table(pp, pp->rxq_def); 3063 mvneta_set_other_mcast_table(pp, pp->rxq_def); 3064 } else { 3065 /* Accept single Unicast */ 3066 mvneta_rx_unicast_promisc_set(pp, 0); 3067 mvneta_set_ucast_table(pp, -1); 3068 mvneta_mac_addr_set(pp, dev->dev_addr, pp->rxq_def); 3069 3070 if (dev->flags & IFF_ALLMULTI) { 3071 /* Accept all multicast */ 3072 mvneta_set_special_mcast_table(pp, pp->rxq_def); 3073 mvneta_set_other_mcast_table(pp, pp->rxq_def); 3074 } else { 3075 /* Accept only initialized multicast */ 3076 mvneta_set_special_mcast_table(pp, -1); 3077 mvneta_set_other_mcast_table(pp, -1); 3078 3079 if (!netdev_mc_empty(dev)) { 3080 netdev_for_each_mc_addr(ha, dev) { 3081 mvneta_mcast_addr_set(pp, ha->addr, 3082 pp->rxq_def); 3083 } 3084 } 3085 } 3086 } 3087 } 3088 3089 /* Interrupt handling - the callback for request_irq() */ 3090 static irqreturn_t mvneta_isr(int irq, void *dev_id) 3091 { 3092 struct mvneta_port *pp = (struct mvneta_port *)dev_id; 3093 3094 mvreg_write(pp, MVNETA_INTR_NEW_MASK, 0); 3095 napi_schedule(&pp->napi); 3096 3097 return IRQ_HANDLED; 3098 } 3099 3100 /* Interrupt handling - the callback for request_percpu_irq() */ 3101 static irqreturn_t mvneta_percpu_isr(int irq, void *dev_id) 3102 { 3103 struct mvneta_pcpu_port *port = (struct mvneta_pcpu_port *)dev_id; 3104 3105 disable_percpu_irq(port->pp->dev->irq); 3106 napi_schedule(&port->napi); 3107 3108 return IRQ_HANDLED; 3109 } 3110 3111 static void mvneta_link_change(struct mvneta_port *pp) 3112 { 3113 u32 gmac_stat = mvreg_read(pp, MVNETA_GMAC_STATUS); 3114 3115 phylink_mac_change(pp->phylink, !!(gmac_stat & MVNETA_GMAC_LINK_UP)); 3116 } 3117 3118 /* NAPI handler 3119 * Bits 0 - 7 of the causeRxTx register indicate that are transmitted 3120 * packets on the corresponding TXQ (Bit 0 is for TX queue 1). 3121 * Bits 8 -15 of the cause Rx Tx register indicate that are received 3122 * packets on the corresponding RXQ (Bit 8 is for RX queue 0). 3123 * Each CPU has its own causeRxTx register 3124 */ 3125 static int mvneta_poll(struct napi_struct *napi, int budget) 3126 { 3127 int rx_done = 0; 3128 u32 cause_rx_tx; 3129 int rx_queue; 3130 struct mvneta_port *pp = netdev_priv(napi->dev); 3131 struct mvneta_pcpu_port *port = this_cpu_ptr(pp->ports); 3132 3133 if (!netif_running(pp->dev)) { 3134 napi_complete(napi); 3135 return rx_done; 3136 } 3137 3138 /* Read cause register */ 3139 cause_rx_tx = mvreg_read(pp, MVNETA_INTR_NEW_CAUSE); 3140 if (cause_rx_tx & MVNETA_MISCINTR_INTR_MASK) { 3141 u32 cause_misc = mvreg_read(pp, MVNETA_INTR_MISC_CAUSE); 3142 3143 mvreg_write(pp, MVNETA_INTR_MISC_CAUSE, 0); 3144 3145 if (cause_misc & (MVNETA_CAUSE_PHY_STATUS_CHANGE | 3146 MVNETA_CAUSE_LINK_CHANGE)) 3147 mvneta_link_change(pp); 3148 } 3149 3150 /* Release Tx descriptors */ 3151 if (cause_rx_tx & MVNETA_TX_INTR_MASK_ALL) { 3152 mvneta_tx_done_gbe(pp, (cause_rx_tx & MVNETA_TX_INTR_MASK_ALL)); 3153 cause_rx_tx &= ~MVNETA_TX_INTR_MASK_ALL; 3154 } 3155 3156 /* For the case where the last mvneta_poll did not process all 3157 * RX packets 3158 */ 3159 cause_rx_tx |= pp->neta_armada3700 ? pp->cause_rx_tx : 3160 port->cause_rx_tx; 3161 3162 rx_queue = fls(((cause_rx_tx >> 8) & 0xff)); 3163 if (rx_queue) { 3164 rx_queue = rx_queue - 1; 3165 if (pp->bm_priv) 3166 rx_done = mvneta_rx_hwbm(napi, pp, budget, 3167 &pp->rxqs[rx_queue]); 3168 else 3169 rx_done = mvneta_rx_swbm(napi, pp, budget, 3170 &pp->rxqs[rx_queue]); 3171 } 3172 3173 if (rx_done < budget) { 3174 cause_rx_tx = 0; 3175 napi_complete_done(napi, rx_done); 3176 3177 if (pp->neta_armada3700) { 3178 unsigned long flags; 3179 3180 local_irq_save(flags); 3181 mvreg_write(pp, MVNETA_INTR_NEW_MASK, 3182 MVNETA_RX_INTR_MASK(rxq_number) | 3183 MVNETA_TX_INTR_MASK(txq_number) | 3184 MVNETA_MISCINTR_INTR_MASK); 3185 local_irq_restore(flags); 3186 } else { 3187 enable_percpu_irq(pp->dev->irq, 0); 3188 } 3189 } 3190 3191 if (pp->neta_armada3700) 3192 pp->cause_rx_tx = cause_rx_tx; 3193 else 3194 port->cause_rx_tx = cause_rx_tx; 3195 3196 return rx_done; 3197 } 3198 3199 static int mvneta_create_page_pool(struct mvneta_port *pp, 3200 struct mvneta_rx_queue *rxq, int size) 3201 { 3202 struct bpf_prog *xdp_prog = READ_ONCE(pp->xdp_prog); 3203 struct page_pool_params pp_params = { 3204 .order = 0, 3205 .flags = PP_FLAG_DMA_MAP | PP_FLAG_DMA_SYNC_DEV, 3206 .pool_size = size, 3207 .nid = NUMA_NO_NODE, 3208 .dev = pp->dev->dev.parent, 3209 .dma_dir = xdp_prog ? DMA_BIDIRECTIONAL : DMA_FROM_DEVICE, 3210 .offset = pp->rx_offset_correction, 3211 .max_len = MVNETA_MAX_RX_BUF_SIZE, 3212 }; 3213 int err; 3214 3215 rxq->page_pool = page_pool_create(&pp_params); 3216 if (IS_ERR(rxq->page_pool)) { 3217 err = PTR_ERR(rxq->page_pool); 3218 rxq->page_pool = NULL; 3219 return err; 3220 } 3221 3222 err = xdp_rxq_info_reg(&rxq->xdp_rxq, pp->dev, rxq->id); 3223 if (err < 0) 3224 goto err_free_pp; 3225 3226 err = xdp_rxq_info_reg_mem_model(&rxq->xdp_rxq, MEM_TYPE_PAGE_POOL, 3227 rxq->page_pool); 3228 if (err) 3229 goto err_unregister_rxq; 3230 3231 return 0; 3232 3233 err_unregister_rxq: 3234 xdp_rxq_info_unreg(&rxq->xdp_rxq); 3235 err_free_pp: 3236 page_pool_destroy(rxq->page_pool); 3237 rxq->page_pool = NULL; 3238 return err; 3239 } 3240 3241 /* Handle rxq fill: allocates rxq skbs; called when initializing a port */ 3242 static int mvneta_rxq_fill(struct mvneta_port *pp, struct mvneta_rx_queue *rxq, 3243 int num) 3244 { 3245 int i, err; 3246 3247 err = mvneta_create_page_pool(pp, rxq, num); 3248 if (err < 0) 3249 return err; 3250 3251 for (i = 0; i < num; i++) { 3252 memset(rxq->descs + i, 0, sizeof(struct mvneta_rx_desc)); 3253 if (mvneta_rx_refill(pp, rxq->descs + i, rxq, 3254 GFP_KERNEL) != 0) { 3255 netdev_err(pp->dev, 3256 "%s:rxq %d, %d of %d buffs filled\n", 3257 __func__, rxq->id, i, num); 3258 break; 3259 } 3260 } 3261 3262 /* Add this number of RX descriptors as non occupied (ready to 3263 * get packets) 3264 */ 3265 mvneta_rxq_non_occup_desc_add(pp, rxq, i); 3266 3267 return i; 3268 } 3269 3270 /* Free all packets pending transmit from all TXQs and reset TX port */ 3271 static void mvneta_tx_reset(struct mvneta_port *pp) 3272 { 3273 int queue; 3274 3275 /* free the skb's in the tx ring */ 3276 for (queue = 0; queue < txq_number; queue++) 3277 mvneta_txq_done_force(pp, &pp->txqs[queue]); 3278 3279 mvreg_write(pp, MVNETA_PORT_TX_RESET, MVNETA_PORT_TX_DMA_RESET); 3280 mvreg_write(pp, MVNETA_PORT_TX_RESET, 0); 3281 } 3282 3283 static void mvneta_rx_reset(struct mvneta_port *pp) 3284 { 3285 mvreg_write(pp, MVNETA_PORT_RX_RESET, MVNETA_PORT_RX_DMA_RESET); 3286 mvreg_write(pp, MVNETA_PORT_RX_RESET, 0); 3287 } 3288 3289 /* Rx/Tx queue initialization/cleanup methods */ 3290 3291 static int mvneta_rxq_sw_init(struct mvneta_port *pp, 3292 struct mvneta_rx_queue *rxq) 3293 { 3294 rxq->size = pp->rx_ring_size; 3295 3296 /* Allocate memory for RX descriptors */ 3297 rxq->descs = dma_alloc_coherent(pp->dev->dev.parent, 3298 rxq->size * MVNETA_DESC_ALIGNED_SIZE, 3299 &rxq->descs_phys, GFP_KERNEL); 3300 if (!rxq->descs) 3301 return -ENOMEM; 3302 3303 rxq->last_desc = rxq->size - 1; 3304 3305 return 0; 3306 } 3307 3308 static void mvneta_rxq_hw_init(struct mvneta_port *pp, 3309 struct mvneta_rx_queue *rxq) 3310 { 3311 /* Set Rx descriptors queue starting address */ 3312 mvreg_write(pp, MVNETA_RXQ_BASE_ADDR_REG(rxq->id), rxq->descs_phys); 3313 mvreg_write(pp, MVNETA_RXQ_SIZE_REG(rxq->id), rxq->size); 3314 3315 /* Set coalescing pkts and time */ 3316 mvneta_rx_pkts_coal_set(pp, rxq, rxq->pkts_coal); 3317 mvneta_rx_time_coal_set(pp, rxq, rxq->time_coal); 3318 3319 if (!pp->bm_priv) { 3320 /* Set Offset */ 3321 mvneta_rxq_offset_set(pp, rxq, 0); 3322 mvneta_rxq_buf_size_set(pp, rxq, PAGE_SIZE < SZ_64K ? 3323 MVNETA_MAX_RX_BUF_SIZE : 3324 MVNETA_RX_BUF_SIZE(pp->pkt_size)); 3325 mvneta_rxq_bm_disable(pp, rxq); 3326 mvneta_rxq_fill(pp, rxq, rxq->size); 3327 } else { 3328 /* Set Offset */ 3329 mvneta_rxq_offset_set(pp, rxq, 3330 NET_SKB_PAD - pp->rx_offset_correction); 3331 3332 mvneta_rxq_bm_enable(pp, rxq); 3333 /* Fill RXQ with buffers from RX pool */ 3334 mvneta_rxq_long_pool_set(pp, rxq); 3335 mvneta_rxq_short_pool_set(pp, rxq); 3336 mvneta_rxq_non_occup_desc_add(pp, rxq, rxq->size); 3337 } 3338 } 3339 3340 /* Create a specified RX queue */ 3341 static int mvneta_rxq_init(struct mvneta_port *pp, 3342 struct mvneta_rx_queue *rxq) 3343 3344 { 3345 int ret; 3346 3347 ret = mvneta_rxq_sw_init(pp, rxq); 3348 if (ret < 0) 3349 return ret; 3350 3351 mvneta_rxq_hw_init(pp, rxq); 3352 3353 return 0; 3354 } 3355 3356 /* Cleanup Rx queue */ 3357 static void mvneta_rxq_deinit(struct mvneta_port *pp, 3358 struct mvneta_rx_queue *rxq) 3359 { 3360 mvneta_rxq_drop_pkts(pp, rxq); 3361 3362 if (rxq->descs) 3363 dma_free_coherent(pp->dev->dev.parent, 3364 rxq->size * MVNETA_DESC_ALIGNED_SIZE, 3365 rxq->descs, 3366 rxq->descs_phys); 3367 3368 rxq->descs = NULL; 3369 rxq->last_desc = 0; 3370 rxq->next_desc_to_proc = 0; 3371 rxq->descs_phys = 0; 3372 rxq->first_to_refill = 0; 3373 rxq->refill_num = 0; 3374 } 3375 3376 static int mvneta_txq_sw_init(struct mvneta_port *pp, 3377 struct mvneta_tx_queue *txq) 3378 { 3379 int cpu; 3380 3381 txq->size = pp->tx_ring_size; 3382 3383 /* A queue must always have room for at least one skb. 3384 * Therefore, stop the queue when the free entries reaches 3385 * the maximum number of descriptors per skb. 3386 */ 3387 txq->tx_stop_threshold = txq->size - MVNETA_MAX_SKB_DESCS; 3388 txq->tx_wake_threshold = txq->tx_stop_threshold / 2; 3389 3390 /* Allocate memory for TX descriptors */ 3391 txq->descs = dma_alloc_coherent(pp->dev->dev.parent, 3392 txq->size * MVNETA_DESC_ALIGNED_SIZE, 3393 &txq->descs_phys, GFP_KERNEL); 3394 if (!txq->descs) 3395 return -ENOMEM; 3396 3397 txq->last_desc = txq->size - 1; 3398 3399 txq->buf = kmalloc_array(txq->size, sizeof(*txq->buf), GFP_KERNEL); 3400 if (!txq->buf) 3401 return -ENOMEM; 3402 3403 /* Allocate DMA buffers for TSO MAC/IP/TCP headers */ 3404 txq->tso_hdrs = dma_alloc_coherent(pp->dev->dev.parent, 3405 txq->size * TSO_HEADER_SIZE, 3406 &txq->tso_hdrs_phys, GFP_KERNEL); 3407 if (!txq->tso_hdrs) 3408 return -ENOMEM; 3409 3410 /* Setup XPS mapping */ 3411 if (txq_number > 1) 3412 cpu = txq->id % num_present_cpus(); 3413 else 3414 cpu = pp->rxq_def % num_present_cpus(); 3415 cpumask_set_cpu(cpu, &txq->affinity_mask); 3416 netif_set_xps_queue(pp->dev, &txq->affinity_mask, txq->id); 3417 3418 return 0; 3419 } 3420 3421 static void mvneta_txq_hw_init(struct mvneta_port *pp, 3422 struct mvneta_tx_queue *txq) 3423 { 3424 /* Set maximum bandwidth for enabled TXQs */ 3425 mvreg_write(pp, MVETH_TXQ_TOKEN_CFG_REG(txq->id), 0x03ffffff); 3426 mvreg_write(pp, MVETH_TXQ_TOKEN_COUNT_REG(txq->id), 0x3fffffff); 3427 3428 /* Set Tx descriptors queue starting address */ 3429 mvreg_write(pp, MVNETA_TXQ_BASE_ADDR_REG(txq->id), txq->descs_phys); 3430 mvreg_write(pp, MVNETA_TXQ_SIZE_REG(txq->id), txq->size); 3431 3432 mvneta_tx_done_pkts_coal_set(pp, txq, txq->done_pkts_coal); 3433 } 3434 3435 /* Create and initialize a tx queue */ 3436 static int mvneta_txq_init(struct mvneta_port *pp, 3437 struct mvneta_tx_queue *txq) 3438 { 3439 int ret; 3440 3441 ret = mvneta_txq_sw_init(pp, txq); 3442 if (ret < 0) 3443 return ret; 3444 3445 mvneta_txq_hw_init(pp, txq); 3446 3447 return 0; 3448 } 3449 3450 /* Free allocated resources when mvneta_txq_init() fails to allocate memory*/ 3451 static void mvneta_txq_sw_deinit(struct mvneta_port *pp, 3452 struct mvneta_tx_queue *txq) 3453 { 3454 struct netdev_queue *nq = netdev_get_tx_queue(pp->dev, txq->id); 3455 3456 kfree(txq->buf); 3457 3458 if (txq->tso_hdrs) 3459 dma_free_coherent(pp->dev->dev.parent, 3460 txq->size * TSO_HEADER_SIZE, 3461 txq->tso_hdrs, txq->tso_hdrs_phys); 3462 if (txq->descs) 3463 dma_free_coherent(pp->dev->dev.parent, 3464 txq->size * MVNETA_DESC_ALIGNED_SIZE, 3465 txq->descs, txq->descs_phys); 3466 3467 netdev_tx_reset_queue(nq); 3468 3469 txq->descs = NULL; 3470 txq->last_desc = 0; 3471 txq->next_desc_to_proc = 0; 3472 txq->descs_phys = 0; 3473 } 3474 3475 static void mvneta_txq_hw_deinit(struct mvneta_port *pp, 3476 struct mvneta_tx_queue *txq) 3477 { 3478 /* Set minimum bandwidth for disabled TXQs */ 3479 mvreg_write(pp, MVETH_TXQ_TOKEN_CFG_REG(txq->id), 0); 3480 mvreg_write(pp, MVETH_TXQ_TOKEN_COUNT_REG(txq->id), 0); 3481 3482 /* Set Tx descriptors queue starting address and size */ 3483 mvreg_write(pp, MVNETA_TXQ_BASE_ADDR_REG(txq->id), 0); 3484 mvreg_write(pp, MVNETA_TXQ_SIZE_REG(txq->id), 0); 3485 } 3486 3487 static void mvneta_txq_deinit(struct mvneta_port *pp, 3488 struct mvneta_tx_queue *txq) 3489 { 3490 mvneta_txq_sw_deinit(pp, txq); 3491 mvneta_txq_hw_deinit(pp, txq); 3492 } 3493 3494 /* Cleanup all Tx queues */ 3495 static void mvneta_cleanup_txqs(struct mvneta_port *pp) 3496 { 3497 int queue; 3498 3499 for (queue = 0; queue < txq_number; queue++) 3500 mvneta_txq_deinit(pp, &pp->txqs[queue]); 3501 } 3502 3503 /* Cleanup all Rx queues */ 3504 static void mvneta_cleanup_rxqs(struct mvneta_port *pp) 3505 { 3506 int queue; 3507 3508 for (queue = 0; queue < rxq_number; queue++) 3509 mvneta_rxq_deinit(pp, &pp->rxqs[queue]); 3510 } 3511 3512 3513 /* Init all Rx queues */ 3514 static int mvneta_setup_rxqs(struct mvneta_port *pp) 3515 { 3516 int queue; 3517 3518 for (queue = 0; queue < rxq_number; queue++) { 3519 int err = mvneta_rxq_init(pp, &pp->rxqs[queue]); 3520 3521 if (err) { 3522 netdev_err(pp->dev, "%s: can't create rxq=%d\n", 3523 __func__, queue); 3524 mvneta_cleanup_rxqs(pp); 3525 return err; 3526 } 3527 } 3528 3529 return 0; 3530 } 3531 3532 /* Init all tx queues */ 3533 static int mvneta_setup_txqs(struct mvneta_port *pp) 3534 { 3535 int queue; 3536 3537 for (queue = 0; queue < txq_number; queue++) { 3538 int err = mvneta_txq_init(pp, &pp->txqs[queue]); 3539 if (err) { 3540 netdev_err(pp->dev, "%s: can't create txq=%d\n", 3541 __func__, queue); 3542 mvneta_cleanup_txqs(pp); 3543 return err; 3544 } 3545 } 3546 3547 return 0; 3548 } 3549 3550 static int mvneta_comphy_init(struct mvneta_port *pp, phy_interface_t interface) 3551 { 3552 int ret; 3553 3554 ret = phy_set_mode_ext(pp->comphy, PHY_MODE_ETHERNET, interface); 3555 if (ret) 3556 return ret; 3557 3558 return phy_power_on(pp->comphy); 3559 } 3560 3561 static int mvneta_config_interface(struct mvneta_port *pp, 3562 phy_interface_t interface) 3563 { 3564 int ret = 0; 3565 3566 if (pp->comphy) { 3567 if (interface == PHY_INTERFACE_MODE_SGMII || 3568 interface == PHY_INTERFACE_MODE_1000BASEX || 3569 interface == PHY_INTERFACE_MODE_2500BASEX) { 3570 ret = mvneta_comphy_init(pp, interface); 3571 } 3572 } else { 3573 switch (interface) { 3574 case PHY_INTERFACE_MODE_QSGMII: 3575 mvreg_write(pp, MVNETA_SERDES_CFG, 3576 MVNETA_QSGMII_SERDES_PROTO); 3577 break; 3578 3579 case PHY_INTERFACE_MODE_SGMII: 3580 case PHY_INTERFACE_MODE_1000BASEX: 3581 mvreg_write(pp, MVNETA_SERDES_CFG, 3582 MVNETA_SGMII_SERDES_PROTO); 3583 break; 3584 3585 case PHY_INTERFACE_MODE_2500BASEX: 3586 mvreg_write(pp, MVNETA_SERDES_CFG, 3587 MVNETA_HSGMII_SERDES_PROTO); 3588 break; 3589 default: 3590 break; 3591 } 3592 } 3593 3594 pp->phy_interface = interface; 3595 3596 return ret; 3597 } 3598 3599 static void mvneta_start_dev(struct mvneta_port *pp) 3600 { 3601 int cpu; 3602 3603 WARN_ON(mvneta_config_interface(pp, pp->phy_interface)); 3604 3605 mvneta_max_rx_size_set(pp, pp->pkt_size); 3606 mvneta_txq_max_tx_size_set(pp, pp->pkt_size); 3607 3608 /* start the Rx/Tx activity */ 3609 mvneta_port_enable(pp); 3610 3611 if (!pp->neta_armada3700) { 3612 /* Enable polling on the port */ 3613 for_each_online_cpu(cpu) { 3614 struct mvneta_pcpu_port *port = 3615 per_cpu_ptr(pp->ports, cpu); 3616 3617 napi_enable(&port->napi); 3618 } 3619 } else { 3620 napi_enable(&pp->napi); 3621 } 3622 3623 /* Unmask interrupts. It has to be done from each CPU */ 3624 on_each_cpu(mvneta_percpu_unmask_interrupt, pp, true); 3625 3626 mvreg_write(pp, MVNETA_INTR_MISC_MASK, 3627 MVNETA_CAUSE_PHY_STATUS_CHANGE | 3628 MVNETA_CAUSE_LINK_CHANGE); 3629 3630 phylink_start(pp->phylink); 3631 3632 /* We may have called phylink_speed_down before */ 3633 phylink_speed_up(pp->phylink); 3634 3635 netif_tx_start_all_queues(pp->dev); 3636 3637 clear_bit(__MVNETA_DOWN, &pp->state); 3638 } 3639 3640 static void mvneta_stop_dev(struct mvneta_port *pp) 3641 { 3642 unsigned int cpu; 3643 3644 set_bit(__MVNETA_DOWN, &pp->state); 3645 3646 if (device_may_wakeup(&pp->dev->dev)) 3647 phylink_speed_down(pp->phylink, false); 3648 3649 phylink_stop(pp->phylink); 3650 3651 if (!pp->neta_armada3700) { 3652 for_each_online_cpu(cpu) { 3653 struct mvneta_pcpu_port *port = 3654 per_cpu_ptr(pp->ports, cpu); 3655 3656 napi_disable(&port->napi); 3657 } 3658 } else { 3659 napi_disable(&pp->napi); 3660 } 3661 3662 netif_carrier_off(pp->dev); 3663 3664 mvneta_port_down(pp); 3665 netif_tx_stop_all_queues(pp->dev); 3666 3667 /* Stop the port activity */ 3668 mvneta_port_disable(pp); 3669 3670 /* Clear all ethernet port interrupts */ 3671 on_each_cpu(mvneta_percpu_clear_intr_cause, pp, true); 3672 3673 /* Mask all ethernet port interrupts */ 3674 on_each_cpu(mvneta_percpu_mask_interrupt, pp, true); 3675 3676 mvneta_tx_reset(pp); 3677 mvneta_rx_reset(pp); 3678 3679 WARN_ON(phy_power_off(pp->comphy)); 3680 } 3681 3682 static void mvneta_percpu_enable(void *arg) 3683 { 3684 struct mvneta_port *pp = arg; 3685 3686 enable_percpu_irq(pp->dev->irq, IRQ_TYPE_NONE); 3687 } 3688 3689 static void mvneta_percpu_disable(void *arg) 3690 { 3691 struct mvneta_port *pp = arg; 3692 3693 disable_percpu_irq(pp->dev->irq); 3694 } 3695 3696 /* Change the device mtu */ 3697 static int mvneta_change_mtu(struct net_device *dev, int mtu) 3698 { 3699 struct mvneta_port *pp = netdev_priv(dev); 3700 int ret; 3701 3702 if (!IS_ALIGNED(MVNETA_RX_PKT_SIZE(mtu), 8)) { 3703 netdev_info(dev, "Illegal MTU value %d, rounding to %d\n", 3704 mtu, ALIGN(MVNETA_RX_PKT_SIZE(mtu), 8)); 3705 mtu = ALIGN(MVNETA_RX_PKT_SIZE(mtu), 8); 3706 } 3707 3708 if (pp->xdp_prog && mtu > MVNETA_MAX_RX_BUF_SIZE) { 3709 netdev_info(dev, "Illegal MTU value %d for XDP mode\n", mtu); 3710 return -EINVAL; 3711 } 3712 3713 dev->mtu = mtu; 3714 3715 if (!netif_running(dev)) { 3716 if (pp->bm_priv) 3717 mvneta_bm_update_mtu(pp, mtu); 3718 3719 netdev_update_features(dev); 3720 return 0; 3721 } 3722 3723 /* The interface is running, so we have to force a 3724 * reallocation of the queues 3725 */ 3726 mvneta_stop_dev(pp); 3727 on_each_cpu(mvneta_percpu_disable, pp, true); 3728 3729 mvneta_cleanup_txqs(pp); 3730 mvneta_cleanup_rxqs(pp); 3731 3732 if (pp->bm_priv) 3733 mvneta_bm_update_mtu(pp, mtu); 3734 3735 pp->pkt_size = MVNETA_RX_PKT_SIZE(dev->mtu); 3736 3737 ret = mvneta_setup_rxqs(pp); 3738 if (ret) { 3739 netdev_err(dev, "unable to setup rxqs after MTU change\n"); 3740 return ret; 3741 } 3742 3743 ret = mvneta_setup_txqs(pp); 3744 if (ret) { 3745 netdev_err(dev, "unable to setup txqs after MTU change\n"); 3746 return ret; 3747 } 3748 3749 on_each_cpu(mvneta_percpu_enable, pp, true); 3750 mvneta_start_dev(pp); 3751 3752 netdev_update_features(dev); 3753 3754 return 0; 3755 } 3756 3757 static netdev_features_t mvneta_fix_features(struct net_device *dev, 3758 netdev_features_t features) 3759 { 3760 struct mvneta_port *pp = netdev_priv(dev); 3761 3762 if (pp->tx_csum_limit && dev->mtu > pp->tx_csum_limit) { 3763 features &= ~(NETIF_F_IP_CSUM | NETIF_F_TSO); 3764 netdev_info(dev, 3765 "Disable IP checksum for MTU greater than %dB\n", 3766 pp->tx_csum_limit); 3767 } 3768 3769 return features; 3770 } 3771 3772 /* Get mac address */ 3773 static void mvneta_get_mac_addr(struct mvneta_port *pp, unsigned char *addr) 3774 { 3775 u32 mac_addr_l, mac_addr_h; 3776 3777 mac_addr_l = mvreg_read(pp, MVNETA_MAC_ADDR_LOW); 3778 mac_addr_h = mvreg_read(pp, MVNETA_MAC_ADDR_HIGH); 3779 addr[0] = (mac_addr_h >> 24) & 0xFF; 3780 addr[1] = (mac_addr_h >> 16) & 0xFF; 3781 addr[2] = (mac_addr_h >> 8) & 0xFF; 3782 addr[3] = mac_addr_h & 0xFF; 3783 addr[4] = (mac_addr_l >> 8) & 0xFF; 3784 addr[5] = mac_addr_l & 0xFF; 3785 } 3786 3787 /* Handle setting mac address */ 3788 static int mvneta_set_mac_addr(struct net_device *dev, void *addr) 3789 { 3790 struct mvneta_port *pp = netdev_priv(dev); 3791 struct sockaddr *sockaddr = addr; 3792 int ret; 3793 3794 ret = eth_prepare_mac_addr_change(dev, addr); 3795 if (ret < 0) 3796 return ret; 3797 /* Remove previous address table entry */ 3798 mvneta_mac_addr_set(pp, dev->dev_addr, -1); 3799 3800 /* Set new addr in hw */ 3801 mvneta_mac_addr_set(pp, sockaddr->sa_data, pp->rxq_def); 3802 3803 eth_commit_mac_addr_change(dev, addr); 3804 return 0; 3805 } 3806 3807 static void mvneta_validate(struct phylink_config *config, 3808 unsigned long *supported, 3809 struct phylink_link_state *state) 3810 { 3811 struct net_device *ndev = to_net_dev(config->dev); 3812 struct mvneta_port *pp = netdev_priv(ndev); 3813 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, }; 3814 3815 /* We only support QSGMII, SGMII, 802.3z and RGMII modes */ 3816 if (state->interface != PHY_INTERFACE_MODE_NA && 3817 state->interface != PHY_INTERFACE_MODE_QSGMII && 3818 state->interface != PHY_INTERFACE_MODE_SGMII && 3819 !phy_interface_mode_is_8023z(state->interface) && 3820 !phy_interface_mode_is_rgmii(state->interface)) { 3821 bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS); 3822 return; 3823 } 3824 3825 /* Allow all the expected bits */ 3826 phylink_set(mask, Autoneg); 3827 phylink_set_port_modes(mask); 3828 3829 /* Asymmetric pause is unsupported */ 3830 phylink_set(mask, Pause); 3831 3832 /* Half-duplex at speeds higher than 100Mbit is unsupported */ 3833 if (pp->comphy || state->interface != PHY_INTERFACE_MODE_2500BASEX) { 3834 phylink_set(mask, 1000baseT_Full); 3835 phylink_set(mask, 1000baseX_Full); 3836 } 3837 if (pp->comphy || state->interface == PHY_INTERFACE_MODE_2500BASEX) { 3838 phylink_set(mask, 2500baseT_Full); 3839 phylink_set(mask, 2500baseX_Full); 3840 } 3841 3842 if (!phy_interface_mode_is_8023z(state->interface)) { 3843 /* 10M and 100M are only supported in non-802.3z mode */ 3844 phylink_set(mask, 10baseT_Half); 3845 phylink_set(mask, 10baseT_Full); 3846 phylink_set(mask, 100baseT_Half); 3847 phylink_set(mask, 100baseT_Full); 3848 } 3849 3850 bitmap_and(supported, supported, mask, 3851 __ETHTOOL_LINK_MODE_MASK_NBITS); 3852 bitmap_and(state->advertising, state->advertising, mask, 3853 __ETHTOOL_LINK_MODE_MASK_NBITS); 3854 3855 /* We can only operate at 2500BaseX or 1000BaseX. If requested 3856 * to advertise both, only report advertising at 2500BaseX. 3857 */ 3858 phylink_helper_basex_speed(state); 3859 } 3860 3861 static void mvneta_mac_pcs_get_state(struct phylink_config *config, 3862 struct phylink_link_state *state) 3863 { 3864 struct net_device *ndev = to_net_dev(config->dev); 3865 struct mvneta_port *pp = netdev_priv(ndev); 3866 u32 gmac_stat; 3867 3868 gmac_stat = mvreg_read(pp, MVNETA_GMAC_STATUS); 3869 3870 if (gmac_stat & MVNETA_GMAC_SPEED_1000) 3871 state->speed = 3872 state->interface == PHY_INTERFACE_MODE_2500BASEX ? 3873 SPEED_2500 : SPEED_1000; 3874 else if (gmac_stat & MVNETA_GMAC_SPEED_100) 3875 state->speed = SPEED_100; 3876 else 3877 state->speed = SPEED_10; 3878 3879 state->an_complete = !!(gmac_stat & MVNETA_GMAC_AN_COMPLETE); 3880 state->link = !!(gmac_stat & MVNETA_GMAC_LINK_UP); 3881 state->duplex = !!(gmac_stat & MVNETA_GMAC_FULL_DUPLEX); 3882 3883 state->pause = 0; 3884 if (gmac_stat & MVNETA_GMAC_RX_FLOW_CTRL_ENABLE) 3885 state->pause |= MLO_PAUSE_RX; 3886 if (gmac_stat & MVNETA_GMAC_TX_FLOW_CTRL_ENABLE) 3887 state->pause |= MLO_PAUSE_TX; 3888 } 3889 3890 static void mvneta_mac_an_restart(struct phylink_config *config) 3891 { 3892 struct net_device *ndev = to_net_dev(config->dev); 3893 struct mvneta_port *pp = netdev_priv(ndev); 3894 u32 gmac_an = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG); 3895 3896 mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, 3897 gmac_an | MVNETA_GMAC_INBAND_RESTART_AN); 3898 mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, 3899 gmac_an & ~MVNETA_GMAC_INBAND_RESTART_AN); 3900 } 3901 3902 static void mvneta_mac_config(struct phylink_config *config, unsigned int mode, 3903 const struct phylink_link_state *state) 3904 { 3905 struct net_device *ndev = to_net_dev(config->dev); 3906 struct mvneta_port *pp = netdev_priv(ndev); 3907 u32 new_ctrl0, gmac_ctrl0 = mvreg_read(pp, MVNETA_GMAC_CTRL_0); 3908 u32 new_ctrl2, gmac_ctrl2 = mvreg_read(pp, MVNETA_GMAC_CTRL_2); 3909 u32 new_ctrl4, gmac_ctrl4 = mvreg_read(pp, MVNETA_GMAC_CTRL_4); 3910 u32 new_clk, gmac_clk = mvreg_read(pp, MVNETA_GMAC_CLOCK_DIVIDER); 3911 u32 new_an, gmac_an = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG); 3912 3913 new_ctrl0 = gmac_ctrl0 & ~MVNETA_GMAC0_PORT_1000BASE_X; 3914 new_ctrl2 = gmac_ctrl2 & ~(MVNETA_GMAC2_INBAND_AN_ENABLE | 3915 MVNETA_GMAC2_PORT_RESET); 3916 new_ctrl4 = gmac_ctrl4 & ~(MVNETA_GMAC4_SHORT_PREAMBLE_ENABLE); 3917 new_clk = gmac_clk & ~MVNETA_GMAC_1MS_CLOCK_ENABLE; 3918 new_an = gmac_an & ~(MVNETA_GMAC_INBAND_AN_ENABLE | 3919 MVNETA_GMAC_INBAND_RESTART_AN | 3920 MVNETA_GMAC_AN_SPEED_EN | 3921 MVNETA_GMAC_ADVERT_SYM_FLOW_CTRL | 3922 MVNETA_GMAC_AN_FLOW_CTRL_EN | 3923 MVNETA_GMAC_AN_DUPLEX_EN); 3924 3925 /* Even though it might look weird, when we're configured in 3926 * SGMII or QSGMII mode, the RGMII bit needs to be set. 3927 */ 3928 new_ctrl2 |= MVNETA_GMAC2_PORT_RGMII; 3929 3930 if (state->interface == PHY_INTERFACE_MODE_QSGMII || 3931 state->interface == PHY_INTERFACE_MODE_SGMII || 3932 phy_interface_mode_is_8023z(state->interface)) 3933 new_ctrl2 |= MVNETA_GMAC2_PCS_ENABLE; 3934 3935 if (phylink_test(state->advertising, Pause)) 3936 new_an |= MVNETA_GMAC_ADVERT_SYM_FLOW_CTRL; 3937 3938 if (!phylink_autoneg_inband(mode)) { 3939 /* Phy or fixed speed - nothing to do, leave the 3940 * configured speed, duplex and flow control as-is. 3941 */ 3942 } else if (state->interface == PHY_INTERFACE_MODE_SGMII) { 3943 /* SGMII mode receives the state from the PHY */ 3944 new_ctrl2 |= MVNETA_GMAC2_INBAND_AN_ENABLE; 3945 new_clk |= MVNETA_GMAC_1MS_CLOCK_ENABLE; 3946 new_an = (new_an & ~(MVNETA_GMAC_FORCE_LINK_DOWN | 3947 MVNETA_GMAC_FORCE_LINK_PASS | 3948 MVNETA_GMAC_CONFIG_MII_SPEED | 3949 MVNETA_GMAC_CONFIG_GMII_SPEED | 3950 MVNETA_GMAC_CONFIG_FULL_DUPLEX)) | 3951 MVNETA_GMAC_INBAND_AN_ENABLE | 3952 MVNETA_GMAC_AN_SPEED_EN | 3953 MVNETA_GMAC_AN_DUPLEX_EN; 3954 } else { 3955 /* 802.3z negotiation - only 1000base-X */ 3956 new_ctrl0 |= MVNETA_GMAC0_PORT_1000BASE_X; 3957 new_clk |= MVNETA_GMAC_1MS_CLOCK_ENABLE; 3958 new_an = (new_an & ~(MVNETA_GMAC_FORCE_LINK_DOWN | 3959 MVNETA_GMAC_FORCE_LINK_PASS | 3960 MVNETA_GMAC_CONFIG_MII_SPEED)) | 3961 MVNETA_GMAC_INBAND_AN_ENABLE | 3962 MVNETA_GMAC_CONFIG_GMII_SPEED | 3963 /* The MAC only supports FD mode */ 3964 MVNETA_GMAC_CONFIG_FULL_DUPLEX; 3965 3966 if (state->pause & MLO_PAUSE_AN && state->an_enabled) 3967 new_an |= MVNETA_GMAC_AN_FLOW_CTRL_EN; 3968 } 3969 3970 /* Armada 370 documentation says we can only change the port mode 3971 * and in-band enable when the link is down, so force it down 3972 * while making these changes. We also do this for GMAC_CTRL2 */ 3973 if ((new_ctrl0 ^ gmac_ctrl0) & MVNETA_GMAC0_PORT_1000BASE_X || 3974 (new_ctrl2 ^ gmac_ctrl2) & MVNETA_GMAC2_INBAND_AN_ENABLE || 3975 (new_an ^ gmac_an) & MVNETA_GMAC_INBAND_AN_ENABLE) { 3976 mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, 3977 (gmac_an & ~MVNETA_GMAC_FORCE_LINK_PASS) | 3978 MVNETA_GMAC_FORCE_LINK_DOWN); 3979 } 3980 3981 3982 /* When at 2.5G, the link partner can send frames with shortened 3983 * preambles. 3984 */ 3985 if (state->interface == PHY_INTERFACE_MODE_2500BASEX) 3986 new_ctrl4 |= MVNETA_GMAC4_SHORT_PREAMBLE_ENABLE; 3987 3988 if (pp->phy_interface != state->interface) { 3989 if (pp->comphy) 3990 WARN_ON(phy_power_off(pp->comphy)); 3991 WARN_ON(mvneta_config_interface(pp, state->interface)); 3992 } 3993 3994 if (new_ctrl0 != gmac_ctrl0) 3995 mvreg_write(pp, MVNETA_GMAC_CTRL_0, new_ctrl0); 3996 if (new_ctrl2 != gmac_ctrl2) 3997 mvreg_write(pp, MVNETA_GMAC_CTRL_2, new_ctrl2); 3998 if (new_ctrl4 != gmac_ctrl4) 3999 mvreg_write(pp, MVNETA_GMAC_CTRL_4, new_ctrl4); 4000 if (new_clk != gmac_clk) 4001 mvreg_write(pp, MVNETA_GMAC_CLOCK_DIVIDER, new_clk); 4002 if (new_an != gmac_an) 4003 mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, new_an); 4004 4005 if (gmac_ctrl2 & MVNETA_GMAC2_PORT_RESET) { 4006 while ((mvreg_read(pp, MVNETA_GMAC_CTRL_2) & 4007 MVNETA_GMAC2_PORT_RESET) != 0) 4008 continue; 4009 } 4010 } 4011 4012 static void mvneta_set_eee(struct mvneta_port *pp, bool enable) 4013 { 4014 u32 lpi_ctl1; 4015 4016 lpi_ctl1 = mvreg_read(pp, MVNETA_LPI_CTRL_1); 4017 if (enable) 4018 lpi_ctl1 |= MVNETA_LPI_REQUEST_ENABLE; 4019 else 4020 lpi_ctl1 &= ~MVNETA_LPI_REQUEST_ENABLE; 4021 mvreg_write(pp, MVNETA_LPI_CTRL_1, lpi_ctl1); 4022 } 4023 4024 static void mvneta_mac_link_down(struct phylink_config *config, 4025 unsigned int mode, phy_interface_t interface) 4026 { 4027 struct net_device *ndev = to_net_dev(config->dev); 4028 struct mvneta_port *pp = netdev_priv(ndev); 4029 u32 val; 4030 4031 mvneta_port_down(pp); 4032 4033 if (!phylink_autoneg_inband(mode)) { 4034 val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG); 4035 val &= ~MVNETA_GMAC_FORCE_LINK_PASS; 4036 val |= MVNETA_GMAC_FORCE_LINK_DOWN; 4037 mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val); 4038 } 4039 4040 pp->eee_active = false; 4041 mvneta_set_eee(pp, false); 4042 } 4043 4044 static void mvneta_mac_link_up(struct phylink_config *config, 4045 struct phy_device *phy, 4046 unsigned int mode, phy_interface_t interface, 4047 int speed, int duplex, 4048 bool tx_pause, bool rx_pause) 4049 { 4050 struct net_device *ndev = to_net_dev(config->dev); 4051 struct mvneta_port *pp = netdev_priv(ndev); 4052 u32 val; 4053 4054 if (!phylink_autoneg_inband(mode)) { 4055 val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG); 4056 val &= ~(MVNETA_GMAC_FORCE_LINK_DOWN | 4057 MVNETA_GMAC_CONFIG_MII_SPEED | 4058 MVNETA_GMAC_CONFIG_GMII_SPEED | 4059 MVNETA_GMAC_CONFIG_FLOW_CTRL | 4060 MVNETA_GMAC_CONFIG_FULL_DUPLEX); 4061 val |= MVNETA_GMAC_FORCE_LINK_PASS; 4062 4063 if (speed == SPEED_1000 || speed == SPEED_2500) 4064 val |= MVNETA_GMAC_CONFIG_GMII_SPEED; 4065 else if (speed == SPEED_100) 4066 val |= MVNETA_GMAC_CONFIG_MII_SPEED; 4067 4068 if (duplex == DUPLEX_FULL) 4069 val |= MVNETA_GMAC_CONFIG_FULL_DUPLEX; 4070 4071 if (tx_pause || rx_pause) 4072 val |= MVNETA_GMAC_CONFIG_FLOW_CTRL; 4073 4074 mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val); 4075 } else { 4076 /* When inband doesn't cover flow control or flow control is 4077 * disabled, we need to manually configure it. This bit will 4078 * only have effect if MVNETA_GMAC_AN_FLOW_CTRL_EN is unset. 4079 */ 4080 val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG); 4081 val &= ~MVNETA_GMAC_CONFIG_FLOW_CTRL; 4082 4083 if (tx_pause || rx_pause) 4084 val |= MVNETA_GMAC_CONFIG_FLOW_CTRL; 4085 4086 mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val); 4087 } 4088 4089 mvneta_port_up(pp); 4090 4091 if (phy && pp->eee_enabled) { 4092 pp->eee_active = phy_init_eee(phy, 0) >= 0; 4093 mvneta_set_eee(pp, pp->eee_active && pp->tx_lpi_enabled); 4094 } 4095 } 4096 4097 static const struct phylink_mac_ops mvneta_phylink_ops = { 4098 .validate = mvneta_validate, 4099 .mac_pcs_get_state = mvneta_mac_pcs_get_state, 4100 .mac_an_restart = mvneta_mac_an_restart, 4101 .mac_config = mvneta_mac_config, 4102 .mac_link_down = mvneta_mac_link_down, 4103 .mac_link_up = mvneta_mac_link_up, 4104 }; 4105 4106 static int mvneta_mdio_probe(struct mvneta_port *pp) 4107 { 4108 struct ethtool_wolinfo wol = { .cmd = ETHTOOL_GWOL }; 4109 int err = phylink_of_phy_connect(pp->phylink, pp->dn, 0); 4110 4111 if (err) 4112 netdev_err(pp->dev, "could not attach PHY: %d\n", err); 4113 4114 phylink_ethtool_get_wol(pp->phylink, &wol); 4115 device_set_wakeup_capable(&pp->dev->dev, !!wol.supported); 4116 4117 /* PHY WoL may be enabled but device wakeup disabled */ 4118 if (wol.supported) 4119 device_set_wakeup_enable(&pp->dev->dev, !!wol.wolopts); 4120 4121 return err; 4122 } 4123 4124 static void mvneta_mdio_remove(struct mvneta_port *pp) 4125 { 4126 phylink_disconnect_phy(pp->phylink); 4127 } 4128 4129 /* Electing a CPU must be done in an atomic way: it should be done 4130 * after or before the removal/insertion of a CPU and this function is 4131 * not reentrant. 4132 */ 4133 static void mvneta_percpu_elect(struct mvneta_port *pp) 4134 { 4135 int elected_cpu = 0, max_cpu, cpu, i = 0; 4136 4137 /* Use the cpu associated to the rxq when it is online, in all 4138 * the other cases, use the cpu 0 which can't be offline. 4139 */ 4140 if (cpu_online(pp->rxq_def)) 4141 elected_cpu = pp->rxq_def; 4142 4143 max_cpu = num_present_cpus(); 4144 4145 for_each_online_cpu(cpu) { 4146 int rxq_map = 0, txq_map = 0; 4147 int rxq; 4148 4149 for (rxq = 0; rxq < rxq_number; rxq++) 4150 if ((rxq % max_cpu) == cpu) 4151 rxq_map |= MVNETA_CPU_RXQ_ACCESS(rxq); 4152 4153 if (cpu == elected_cpu) 4154 /* Map the default receive queue queue to the 4155 * elected CPU 4156 */ 4157 rxq_map |= MVNETA_CPU_RXQ_ACCESS(pp->rxq_def); 4158 4159 /* We update the TX queue map only if we have one 4160 * queue. In this case we associate the TX queue to 4161 * the CPU bound to the default RX queue 4162 */ 4163 if (txq_number == 1) 4164 txq_map = (cpu == elected_cpu) ? 4165 MVNETA_CPU_TXQ_ACCESS(1) : 0; 4166 else 4167 txq_map = mvreg_read(pp, MVNETA_CPU_MAP(cpu)) & 4168 MVNETA_CPU_TXQ_ACCESS_ALL_MASK; 4169 4170 mvreg_write(pp, MVNETA_CPU_MAP(cpu), rxq_map | txq_map); 4171 4172 /* Update the interrupt mask on each CPU according the 4173 * new mapping 4174 */ 4175 smp_call_function_single(cpu, mvneta_percpu_unmask_interrupt, 4176 pp, true); 4177 i++; 4178 4179 } 4180 }; 4181 4182 static int mvneta_cpu_online(unsigned int cpu, struct hlist_node *node) 4183 { 4184 int other_cpu; 4185 struct mvneta_port *pp = hlist_entry_safe(node, struct mvneta_port, 4186 node_online); 4187 struct mvneta_pcpu_port *port = per_cpu_ptr(pp->ports, cpu); 4188 4189 4190 spin_lock(&pp->lock); 4191 /* 4192 * Configuring the driver for a new CPU while the driver is 4193 * stopping is racy, so just avoid it. 4194 */ 4195 if (pp->is_stopped) { 4196 spin_unlock(&pp->lock); 4197 return 0; 4198 } 4199 netif_tx_stop_all_queues(pp->dev); 4200 4201 /* 4202 * We have to synchronise on tha napi of each CPU except the one 4203 * just being woken up 4204 */ 4205 for_each_online_cpu(other_cpu) { 4206 if (other_cpu != cpu) { 4207 struct mvneta_pcpu_port *other_port = 4208 per_cpu_ptr(pp->ports, other_cpu); 4209 4210 napi_synchronize(&other_port->napi); 4211 } 4212 } 4213 4214 /* Mask all ethernet port interrupts */ 4215 on_each_cpu(mvneta_percpu_mask_interrupt, pp, true); 4216 napi_enable(&port->napi); 4217 4218 /* 4219 * Enable per-CPU interrupts on the CPU that is 4220 * brought up. 4221 */ 4222 mvneta_percpu_enable(pp); 4223 4224 /* 4225 * Enable per-CPU interrupt on the one CPU we care 4226 * about. 4227 */ 4228 mvneta_percpu_elect(pp); 4229 4230 /* Unmask all ethernet port interrupts */ 4231 on_each_cpu(mvneta_percpu_unmask_interrupt, pp, true); 4232 mvreg_write(pp, MVNETA_INTR_MISC_MASK, 4233 MVNETA_CAUSE_PHY_STATUS_CHANGE | 4234 MVNETA_CAUSE_LINK_CHANGE); 4235 netif_tx_start_all_queues(pp->dev); 4236 spin_unlock(&pp->lock); 4237 return 0; 4238 } 4239 4240 static int mvneta_cpu_down_prepare(unsigned int cpu, struct hlist_node *node) 4241 { 4242 struct mvneta_port *pp = hlist_entry_safe(node, struct mvneta_port, 4243 node_online); 4244 struct mvneta_pcpu_port *port = per_cpu_ptr(pp->ports, cpu); 4245 4246 /* 4247 * Thanks to this lock we are sure that any pending cpu election is 4248 * done. 4249 */ 4250 spin_lock(&pp->lock); 4251 /* Mask all ethernet port interrupts */ 4252 on_each_cpu(mvneta_percpu_mask_interrupt, pp, true); 4253 spin_unlock(&pp->lock); 4254 4255 napi_synchronize(&port->napi); 4256 napi_disable(&port->napi); 4257 /* Disable per-CPU interrupts on the CPU that is brought down. */ 4258 mvneta_percpu_disable(pp); 4259 return 0; 4260 } 4261 4262 static int mvneta_cpu_dead(unsigned int cpu, struct hlist_node *node) 4263 { 4264 struct mvneta_port *pp = hlist_entry_safe(node, struct mvneta_port, 4265 node_dead); 4266 4267 /* Check if a new CPU must be elected now this on is down */ 4268 spin_lock(&pp->lock); 4269 mvneta_percpu_elect(pp); 4270 spin_unlock(&pp->lock); 4271 /* Unmask all ethernet port interrupts */ 4272 on_each_cpu(mvneta_percpu_unmask_interrupt, pp, true); 4273 mvreg_write(pp, MVNETA_INTR_MISC_MASK, 4274 MVNETA_CAUSE_PHY_STATUS_CHANGE | 4275 MVNETA_CAUSE_LINK_CHANGE); 4276 netif_tx_start_all_queues(pp->dev); 4277 return 0; 4278 } 4279 4280 static int mvneta_open(struct net_device *dev) 4281 { 4282 struct mvneta_port *pp = netdev_priv(dev); 4283 int ret; 4284 4285 pp->pkt_size = MVNETA_RX_PKT_SIZE(pp->dev->mtu); 4286 4287 ret = mvneta_setup_rxqs(pp); 4288 if (ret) 4289 return ret; 4290 4291 ret = mvneta_setup_txqs(pp); 4292 if (ret) 4293 goto err_cleanup_rxqs; 4294 4295 /* Connect to port interrupt line */ 4296 if (pp->neta_armada3700) 4297 ret = request_irq(pp->dev->irq, mvneta_isr, 0, 4298 dev->name, pp); 4299 else 4300 ret = request_percpu_irq(pp->dev->irq, mvneta_percpu_isr, 4301 dev->name, pp->ports); 4302 if (ret) { 4303 netdev_err(pp->dev, "cannot request irq %d\n", pp->dev->irq); 4304 goto err_cleanup_txqs; 4305 } 4306 4307 if (!pp->neta_armada3700) { 4308 /* Enable per-CPU interrupt on all the CPU to handle our RX 4309 * queue interrupts 4310 */ 4311 on_each_cpu(mvneta_percpu_enable, pp, true); 4312 4313 pp->is_stopped = false; 4314 /* Register a CPU notifier to handle the case where our CPU 4315 * might be taken offline. 4316 */ 4317 ret = cpuhp_state_add_instance_nocalls(online_hpstate, 4318 &pp->node_online); 4319 if (ret) 4320 goto err_free_irq; 4321 4322 ret = cpuhp_state_add_instance_nocalls(CPUHP_NET_MVNETA_DEAD, 4323 &pp->node_dead); 4324 if (ret) 4325 goto err_free_online_hp; 4326 } 4327 4328 ret = mvneta_mdio_probe(pp); 4329 if (ret < 0) { 4330 netdev_err(dev, "cannot probe MDIO bus\n"); 4331 goto err_free_dead_hp; 4332 } 4333 4334 mvneta_start_dev(pp); 4335 4336 return 0; 4337 4338 err_free_dead_hp: 4339 if (!pp->neta_armada3700) 4340 cpuhp_state_remove_instance_nocalls(CPUHP_NET_MVNETA_DEAD, 4341 &pp->node_dead); 4342 err_free_online_hp: 4343 if (!pp->neta_armada3700) 4344 cpuhp_state_remove_instance_nocalls(online_hpstate, 4345 &pp->node_online); 4346 err_free_irq: 4347 if (pp->neta_armada3700) { 4348 free_irq(pp->dev->irq, pp); 4349 } else { 4350 on_each_cpu(mvneta_percpu_disable, pp, true); 4351 free_percpu_irq(pp->dev->irq, pp->ports); 4352 } 4353 err_cleanup_txqs: 4354 mvneta_cleanup_txqs(pp); 4355 err_cleanup_rxqs: 4356 mvneta_cleanup_rxqs(pp); 4357 return ret; 4358 } 4359 4360 /* Stop the port, free port interrupt line */ 4361 static int mvneta_stop(struct net_device *dev) 4362 { 4363 struct mvneta_port *pp = netdev_priv(dev); 4364 4365 if (!pp->neta_armada3700) { 4366 /* Inform that we are stopping so we don't want to setup the 4367 * driver for new CPUs in the notifiers. The code of the 4368 * notifier for CPU online is protected by the same spinlock, 4369 * so when we get the lock, the notifer work is done. 4370 */ 4371 spin_lock(&pp->lock); 4372 pp->is_stopped = true; 4373 spin_unlock(&pp->lock); 4374 4375 mvneta_stop_dev(pp); 4376 mvneta_mdio_remove(pp); 4377 4378 cpuhp_state_remove_instance_nocalls(online_hpstate, 4379 &pp->node_online); 4380 cpuhp_state_remove_instance_nocalls(CPUHP_NET_MVNETA_DEAD, 4381 &pp->node_dead); 4382 on_each_cpu(mvneta_percpu_disable, pp, true); 4383 free_percpu_irq(dev->irq, pp->ports); 4384 } else { 4385 mvneta_stop_dev(pp); 4386 mvneta_mdio_remove(pp); 4387 free_irq(dev->irq, pp); 4388 } 4389 4390 mvneta_cleanup_rxqs(pp); 4391 mvneta_cleanup_txqs(pp); 4392 4393 return 0; 4394 } 4395 4396 static int mvneta_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) 4397 { 4398 struct mvneta_port *pp = netdev_priv(dev); 4399 4400 return phylink_mii_ioctl(pp->phylink, ifr, cmd); 4401 } 4402 4403 static int mvneta_xdp_setup(struct net_device *dev, struct bpf_prog *prog, 4404 struct netlink_ext_ack *extack) 4405 { 4406 bool need_update, running = netif_running(dev); 4407 struct mvneta_port *pp = netdev_priv(dev); 4408 struct bpf_prog *old_prog; 4409 4410 if (prog && dev->mtu > MVNETA_MAX_RX_BUF_SIZE) { 4411 NL_SET_ERR_MSG_MOD(extack, "Jumbo frames not supported on XDP"); 4412 return -EOPNOTSUPP; 4413 } 4414 4415 if (pp->bm_priv) { 4416 NL_SET_ERR_MSG_MOD(extack, 4417 "Hardware Buffer Management not supported on XDP"); 4418 return -EOPNOTSUPP; 4419 } 4420 4421 need_update = !!pp->xdp_prog != !!prog; 4422 if (running && need_update) 4423 mvneta_stop(dev); 4424 4425 old_prog = xchg(&pp->xdp_prog, prog); 4426 if (old_prog) 4427 bpf_prog_put(old_prog); 4428 4429 if (running && need_update) 4430 return mvneta_open(dev); 4431 4432 return 0; 4433 } 4434 4435 static int mvneta_xdp(struct net_device *dev, struct netdev_bpf *xdp) 4436 { 4437 switch (xdp->command) { 4438 case XDP_SETUP_PROG: 4439 return mvneta_xdp_setup(dev, xdp->prog, xdp->extack); 4440 default: 4441 return -EINVAL; 4442 } 4443 } 4444 4445 /* Ethtool methods */ 4446 4447 /* Set link ksettings (phy address, speed) for ethtools */ 4448 static int 4449 mvneta_ethtool_set_link_ksettings(struct net_device *ndev, 4450 const struct ethtool_link_ksettings *cmd) 4451 { 4452 struct mvneta_port *pp = netdev_priv(ndev); 4453 4454 return phylink_ethtool_ksettings_set(pp->phylink, cmd); 4455 } 4456 4457 /* Get link ksettings for ethtools */ 4458 static int 4459 mvneta_ethtool_get_link_ksettings(struct net_device *ndev, 4460 struct ethtool_link_ksettings *cmd) 4461 { 4462 struct mvneta_port *pp = netdev_priv(ndev); 4463 4464 return phylink_ethtool_ksettings_get(pp->phylink, cmd); 4465 } 4466 4467 static int mvneta_ethtool_nway_reset(struct net_device *dev) 4468 { 4469 struct mvneta_port *pp = netdev_priv(dev); 4470 4471 return phylink_ethtool_nway_reset(pp->phylink); 4472 } 4473 4474 /* Set interrupt coalescing for ethtools */ 4475 static int mvneta_ethtool_set_coalesce(struct net_device *dev, 4476 struct ethtool_coalesce *c) 4477 { 4478 struct mvneta_port *pp = netdev_priv(dev); 4479 int queue; 4480 4481 for (queue = 0; queue < rxq_number; queue++) { 4482 struct mvneta_rx_queue *rxq = &pp->rxqs[queue]; 4483 rxq->time_coal = c->rx_coalesce_usecs; 4484 rxq->pkts_coal = c->rx_max_coalesced_frames; 4485 mvneta_rx_pkts_coal_set(pp, rxq, rxq->pkts_coal); 4486 mvneta_rx_time_coal_set(pp, rxq, rxq->time_coal); 4487 } 4488 4489 for (queue = 0; queue < txq_number; queue++) { 4490 struct mvneta_tx_queue *txq = &pp->txqs[queue]; 4491 txq->done_pkts_coal = c->tx_max_coalesced_frames; 4492 mvneta_tx_done_pkts_coal_set(pp, txq, txq->done_pkts_coal); 4493 } 4494 4495 return 0; 4496 } 4497 4498 /* get coalescing for ethtools */ 4499 static int mvneta_ethtool_get_coalesce(struct net_device *dev, 4500 struct ethtool_coalesce *c) 4501 { 4502 struct mvneta_port *pp = netdev_priv(dev); 4503 4504 c->rx_coalesce_usecs = pp->rxqs[0].time_coal; 4505 c->rx_max_coalesced_frames = pp->rxqs[0].pkts_coal; 4506 4507 c->tx_max_coalesced_frames = pp->txqs[0].done_pkts_coal; 4508 return 0; 4509 } 4510 4511 4512 static void mvneta_ethtool_get_drvinfo(struct net_device *dev, 4513 struct ethtool_drvinfo *drvinfo) 4514 { 4515 strlcpy(drvinfo->driver, MVNETA_DRIVER_NAME, 4516 sizeof(drvinfo->driver)); 4517 strlcpy(drvinfo->version, MVNETA_DRIVER_VERSION, 4518 sizeof(drvinfo->version)); 4519 strlcpy(drvinfo->bus_info, dev_name(&dev->dev), 4520 sizeof(drvinfo->bus_info)); 4521 } 4522 4523 4524 static void mvneta_ethtool_get_ringparam(struct net_device *netdev, 4525 struct ethtool_ringparam *ring) 4526 { 4527 struct mvneta_port *pp = netdev_priv(netdev); 4528 4529 ring->rx_max_pending = MVNETA_MAX_RXD; 4530 ring->tx_max_pending = MVNETA_MAX_TXD; 4531 ring->rx_pending = pp->rx_ring_size; 4532 ring->tx_pending = pp->tx_ring_size; 4533 } 4534 4535 static int mvneta_ethtool_set_ringparam(struct net_device *dev, 4536 struct ethtool_ringparam *ring) 4537 { 4538 struct mvneta_port *pp = netdev_priv(dev); 4539 4540 if ((ring->rx_pending == 0) || (ring->tx_pending == 0)) 4541 return -EINVAL; 4542 pp->rx_ring_size = ring->rx_pending < MVNETA_MAX_RXD ? 4543 ring->rx_pending : MVNETA_MAX_RXD; 4544 4545 pp->tx_ring_size = clamp_t(u16, ring->tx_pending, 4546 MVNETA_MAX_SKB_DESCS * 2, MVNETA_MAX_TXD); 4547 if (pp->tx_ring_size != ring->tx_pending) 4548 netdev_warn(dev, "TX queue size set to %u (requested %u)\n", 4549 pp->tx_ring_size, ring->tx_pending); 4550 4551 if (netif_running(dev)) { 4552 mvneta_stop(dev); 4553 if (mvneta_open(dev)) { 4554 netdev_err(dev, 4555 "error on opening device after ring param change\n"); 4556 return -ENOMEM; 4557 } 4558 } 4559 4560 return 0; 4561 } 4562 4563 static void mvneta_ethtool_get_pauseparam(struct net_device *dev, 4564 struct ethtool_pauseparam *pause) 4565 { 4566 struct mvneta_port *pp = netdev_priv(dev); 4567 4568 phylink_ethtool_get_pauseparam(pp->phylink, pause); 4569 } 4570 4571 static int mvneta_ethtool_set_pauseparam(struct net_device *dev, 4572 struct ethtool_pauseparam *pause) 4573 { 4574 struct mvneta_port *pp = netdev_priv(dev); 4575 4576 return phylink_ethtool_set_pauseparam(pp->phylink, pause); 4577 } 4578 4579 static void mvneta_ethtool_get_strings(struct net_device *netdev, u32 sset, 4580 u8 *data) 4581 { 4582 if (sset == ETH_SS_STATS) { 4583 int i; 4584 4585 for (i = 0; i < ARRAY_SIZE(mvneta_statistics); i++) 4586 memcpy(data + i * ETH_GSTRING_LEN, 4587 mvneta_statistics[i].name, ETH_GSTRING_LEN); 4588 } 4589 } 4590 4591 static void 4592 mvneta_ethtool_update_pcpu_stats(struct mvneta_port *pp, 4593 struct mvneta_ethtool_stats *es) 4594 { 4595 unsigned int start; 4596 int cpu; 4597 4598 for_each_possible_cpu(cpu) { 4599 struct mvneta_pcpu_stats *stats; 4600 u64 skb_alloc_error; 4601 u64 refill_error; 4602 u64 xdp_redirect; 4603 u64 xdp_xmit_err; 4604 u64 xdp_tx_err; 4605 u64 xdp_pass; 4606 u64 xdp_drop; 4607 u64 xdp_xmit; 4608 u64 xdp_tx; 4609 4610 stats = per_cpu_ptr(pp->stats, cpu); 4611 do { 4612 start = u64_stats_fetch_begin_irq(&stats->syncp); 4613 skb_alloc_error = stats->es.skb_alloc_error; 4614 refill_error = stats->es.refill_error; 4615 xdp_redirect = stats->es.ps.xdp_redirect; 4616 xdp_pass = stats->es.ps.xdp_pass; 4617 xdp_drop = stats->es.ps.xdp_drop; 4618 xdp_xmit = stats->es.ps.xdp_xmit; 4619 xdp_xmit_err = stats->es.ps.xdp_xmit_err; 4620 xdp_tx = stats->es.ps.xdp_tx; 4621 xdp_tx_err = stats->es.ps.xdp_tx_err; 4622 } while (u64_stats_fetch_retry_irq(&stats->syncp, start)); 4623 4624 es->skb_alloc_error += skb_alloc_error; 4625 es->refill_error += refill_error; 4626 es->ps.xdp_redirect += xdp_redirect; 4627 es->ps.xdp_pass += xdp_pass; 4628 es->ps.xdp_drop += xdp_drop; 4629 es->ps.xdp_xmit += xdp_xmit; 4630 es->ps.xdp_xmit_err += xdp_xmit_err; 4631 es->ps.xdp_tx += xdp_tx; 4632 es->ps.xdp_tx_err += xdp_tx_err; 4633 } 4634 } 4635 4636 static void mvneta_ethtool_update_stats(struct mvneta_port *pp) 4637 { 4638 struct mvneta_ethtool_stats stats = {}; 4639 const struct mvneta_statistic *s; 4640 void __iomem *base = pp->base; 4641 u32 high, low; 4642 u64 val; 4643 int i; 4644 4645 mvneta_ethtool_update_pcpu_stats(pp, &stats); 4646 for (i = 0, s = mvneta_statistics; 4647 s < mvneta_statistics + ARRAY_SIZE(mvneta_statistics); 4648 s++, i++) { 4649 switch (s->type) { 4650 case T_REG_32: 4651 val = readl_relaxed(base + s->offset); 4652 pp->ethtool_stats[i] += val; 4653 break; 4654 case T_REG_64: 4655 /* Docs say to read low 32-bit then high */ 4656 low = readl_relaxed(base + s->offset); 4657 high = readl_relaxed(base + s->offset + 4); 4658 val = (u64)high << 32 | low; 4659 pp->ethtool_stats[i] += val; 4660 break; 4661 case T_SW: 4662 switch (s->offset) { 4663 case ETHTOOL_STAT_EEE_WAKEUP: 4664 val = phylink_get_eee_err(pp->phylink); 4665 pp->ethtool_stats[i] += val; 4666 break; 4667 case ETHTOOL_STAT_SKB_ALLOC_ERR: 4668 pp->ethtool_stats[i] = stats.skb_alloc_error; 4669 break; 4670 case ETHTOOL_STAT_REFILL_ERR: 4671 pp->ethtool_stats[i] = stats.refill_error; 4672 break; 4673 case ETHTOOL_XDP_REDIRECT: 4674 pp->ethtool_stats[i] = stats.ps.xdp_redirect; 4675 break; 4676 case ETHTOOL_XDP_PASS: 4677 pp->ethtool_stats[i] = stats.ps.xdp_pass; 4678 break; 4679 case ETHTOOL_XDP_DROP: 4680 pp->ethtool_stats[i] = stats.ps.xdp_drop; 4681 break; 4682 case ETHTOOL_XDP_TX: 4683 pp->ethtool_stats[i] = stats.ps.xdp_tx; 4684 break; 4685 case ETHTOOL_XDP_TX_ERR: 4686 pp->ethtool_stats[i] = stats.ps.xdp_tx_err; 4687 break; 4688 case ETHTOOL_XDP_XMIT: 4689 pp->ethtool_stats[i] = stats.ps.xdp_xmit; 4690 break; 4691 case ETHTOOL_XDP_XMIT_ERR: 4692 pp->ethtool_stats[i] = stats.ps.xdp_xmit_err; 4693 break; 4694 } 4695 break; 4696 } 4697 } 4698 } 4699 4700 static void mvneta_ethtool_get_stats(struct net_device *dev, 4701 struct ethtool_stats *stats, u64 *data) 4702 { 4703 struct mvneta_port *pp = netdev_priv(dev); 4704 int i; 4705 4706 mvneta_ethtool_update_stats(pp); 4707 4708 for (i = 0; i < ARRAY_SIZE(mvneta_statistics); i++) 4709 *data++ = pp->ethtool_stats[i]; 4710 } 4711 4712 static int mvneta_ethtool_get_sset_count(struct net_device *dev, int sset) 4713 { 4714 if (sset == ETH_SS_STATS) 4715 return ARRAY_SIZE(mvneta_statistics); 4716 return -EOPNOTSUPP; 4717 } 4718 4719 static u32 mvneta_ethtool_get_rxfh_indir_size(struct net_device *dev) 4720 { 4721 return MVNETA_RSS_LU_TABLE_SIZE; 4722 } 4723 4724 static int mvneta_ethtool_get_rxnfc(struct net_device *dev, 4725 struct ethtool_rxnfc *info, 4726 u32 *rules __always_unused) 4727 { 4728 switch (info->cmd) { 4729 case ETHTOOL_GRXRINGS: 4730 info->data = rxq_number; 4731 return 0; 4732 case ETHTOOL_GRXFH: 4733 return -EOPNOTSUPP; 4734 default: 4735 return -EOPNOTSUPP; 4736 } 4737 } 4738 4739 static int mvneta_config_rss(struct mvneta_port *pp) 4740 { 4741 int cpu; 4742 u32 val; 4743 4744 netif_tx_stop_all_queues(pp->dev); 4745 4746 on_each_cpu(mvneta_percpu_mask_interrupt, pp, true); 4747 4748 if (!pp->neta_armada3700) { 4749 /* We have to synchronise on the napi of each CPU */ 4750 for_each_online_cpu(cpu) { 4751 struct mvneta_pcpu_port *pcpu_port = 4752 per_cpu_ptr(pp->ports, cpu); 4753 4754 napi_synchronize(&pcpu_port->napi); 4755 napi_disable(&pcpu_port->napi); 4756 } 4757 } else { 4758 napi_synchronize(&pp->napi); 4759 napi_disable(&pp->napi); 4760 } 4761 4762 pp->rxq_def = pp->indir[0]; 4763 4764 /* Update unicast mapping */ 4765 mvneta_set_rx_mode(pp->dev); 4766 4767 /* Update val of portCfg register accordingly with all RxQueue types */ 4768 val = MVNETA_PORT_CONFIG_DEFL_VALUE(pp->rxq_def); 4769 mvreg_write(pp, MVNETA_PORT_CONFIG, val); 4770 4771 /* Update the elected CPU matching the new rxq_def */ 4772 spin_lock(&pp->lock); 4773 mvneta_percpu_elect(pp); 4774 spin_unlock(&pp->lock); 4775 4776 if (!pp->neta_armada3700) { 4777 /* We have to synchronise on the napi of each CPU */ 4778 for_each_online_cpu(cpu) { 4779 struct mvneta_pcpu_port *pcpu_port = 4780 per_cpu_ptr(pp->ports, cpu); 4781 4782 napi_enable(&pcpu_port->napi); 4783 } 4784 } else { 4785 napi_enable(&pp->napi); 4786 } 4787 4788 netif_tx_start_all_queues(pp->dev); 4789 4790 return 0; 4791 } 4792 4793 static int mvneta_ethtool_set_rxfh(struct net_device *dev, const u32 *indir, 4794 const u8 *key, const u8 hfunc) 4795 { 4796 struct mvneta_port *pp = netdev_priv(dev); 4797 4798 /* Current code for Armada 3700 doesn't support RSS features yet */ 4799 if (pp->neta_armada3700) 4800 return -EOPNOTSUPP; 4801 4802 /* We require at least one supported parameter to be changed 4803 * and no change in any of the unsupported parameters 4804 */ 4805 if (key || 4806 (hfunc != ETH_RSS_HASH_NO_CHANGE && hfunc != ETH_RSS_HASH_TOP)) 4807 return -EOPNOTSUPP; 4808 4809 if (!indir) 4810 return 0; 4811 4812 memcpy(pp->indir, indir, MVNETA_RSS_LU_TABLE_SIZE); 4813 4814 return mvneta_config_rss(pp); 4815 } 4816 4817 static int mvneta_ethtool_get_rxfh(struct net_device *dev, u32 *indir, u8 *key, 4818 u8 *hfunc) 4819 { 4820 struct mvneta_port *pp = netdev_priv(dev); 4821 4822 /* Current code for Armada 3700 doesn't support RSS features yet */ 4823 if (pp->neta_armada3700) 4824 return -EOPNOTSUPP; 4825 4826 if (hfunc) 4827 *hfunc = ETH_RSS_HASH_TOP; 4828 4829 if (!indir) 4830 return 0; 4831 4832 memcpy(indir, pp->indir, MVNETA_RSS_LU_TABLE_SIZE); 4833 4834 return 0; 4835 } 4836 4837 static void mvneta_ethtool_get_wol(struct net_device *dev, 4838 struct ethtool_wolinfo *wol) 4839 { 4840 struct mvneta_port *pp = netdev_priv(dev); 4841 4842 phylink_ethtool_get_wol(pp->phylink, wol); 4843 } 4844 4845 static int mvneta_ethtool_set_wol(struct net_device *dev, 4846 struct ethtool_wolinfo *wol) 4847 { 4848 struct mvneta_port *pp = netdev_priv(dev); 4849 int ret; 4850 4851 ret = phylink_ethtool_set_wol(pp->phylink, wol); 4852 if (!ret) 4853 device_set_wakeup_enable(&dev->dev, !!wol->wolopts); 4854 4855 return ret; 4856 } 4857 4858 static int mvneta_ethtool_get_eee(struct net_device *dev, 4859 struct ethtool_eee *eee) 4860 { 4861 struct mvneta_port *pp = netdev_priv(dev); 4862 u32 lpi_ctl0; 4863 4864 lpi_ctl0 = mvreg_read(pp, MVNETA_LPI_CTRL_0); 4865 4866 eee->eee_enabled = pp->eee_enabled; 4867 eee->eee_active = pp->eee_active; 4868 eee->tx_lpi_enabled = pp->tx_lpi_enabled; 4869 eee->tx_lpi_timer = (lpi_ctl0) >> 8; // * scale; 4870 4871 return phylink_ethtool_get_eee(pp->phylink, eee); 4872 } 4873 4874 static int mvneta_ethtool_set_eee(struct net_device *dev, 4875 struct ethtool_eee *eee) 4876 { 4877 struct mvneta_port *pp = netdev_priv(dev); 4878 u32 lpi_ctl0; 4879 4880 /* The Armada 37x documents do not give limits for this other than 4881 * it being an 8-bit register. */ 4882 if (eee->tx_lpi_enabled && eee->tx_lpi_timer > 255) 4883 return -EINVAL; 4884 4885 lpi_ctl0 = mvreg_read(pp, MVNETA_LPI_CTRL_0); 4886 lpi_ctl0 &= ~(0xff << 8); 4887 lpi_ctl0 |= eee->tx_lpi_timer << 8; 4888 mvreg_write(pp, MVNETA_LPI_CTRL_0, lpi_ctl0); 4889 4890 pp->eee_enabled = eee->eee_enabled; 4891 pp->tx_lpi_enabled = eee->tx_lpi_enabled; 4892 4893 mvneta_set_eee(pp, eee->tx_lpi_enabled && eee->eee_enabled); 4894 4895 return phylink_ethtool_set_eee(pp->phylink, eee); 4896 } 4897 4898 static const struct net_device_ops mvneta_netdev_ops = { 4899 .ndo_open = mvneta_open, 4900 .ndo_stop = mvneta_stop, 4901 .ndo_start_xmit = mvneta_tx, 4902 .ndo_set_rx_mode = mvneta_set_rx_mode, 4903 .ndo_set_mac_address = mvneta_set_mac_addr, 4904 .ndo_change_mtu = mvneta_change_mtu, 4905 .ndo_fix_features = mvneta_fix_features, 4906 .ndo_get_stats64 = mvneta_get_stats64, 4907 .ndo_do_ioctl = mvneta_ioctl, 4908 .ndo_bpf = mvneta_xdp, 4909 .ndo_xdp_xmit = mvneta_xdp_xmit, 4910 }; 4911 4912 static const struct ethtool_ops mvneta_eth_tool_ops = { 4913 .supported_coalesce_params = ETHTOOL_COALESCE_RX_USECS | 4914 ETHTOOL_COALESCE_MAX_FRAMES, 4915 .nway_reset = mvneta_ethtool_nway_reset, 4916 .get_link = ethtool_op_get_link, 4917 .set_coalesce = mvneta_ethtool_set_coalesce, 4918 .get_coalesce = mvneta_ethtool_get_coalesce, 4919 .get_drvinfo = mvneta_ethtool_get_drvinfo, 4920 .get_ringparam = mvneta_ethtool_get_ringparam, 4921 .set_ringparam = mvneta_ethtool_set_ringparam, 4922 .get_pauseparam = mvneta_ethtool_get_pauseparam, 4923 .set_pauseparam = mvneta_ethtool_set_pauseparam, 4924 .get_strings = mvneta_ethtool_get_strings, 4925 .get_ethtool_stats = mvneta_ethtool_get_stats, 4926 .get_sset_count = mvneta_ethtool_get_sset_count, 4927 .get_rxfh_indir_size = mvneta_ethtool_get_rxfh_indir_size, 4928 .get_rxnfc = mvneta_ethtool_get_rxnfc, 4929 .get_rxfh = mvneta_ethtool_get_rxfh, 4930 .set_rxfh = mvneta_ethtool_set_rxfh, 4931 .get_link_ksettings = mvneta_ethtool_get_link_ksettings, 4932 .set_link_ksettings = mvneta_ethtool_set_link_ksettings, 4933 .get_wol = mvneta_ethtool_get_wol, 4934 .set_wol = mvneta_ethtool_set_wol, 4935 .get_eee = mvneta_ethtool_get_eee, 4936 .set_eee = mvneta_ethtool_set_eee, 4937 }; 4938 4939 /* Initialize hw */ 4940 static int mvneta_init(struct device *dev, struct mvneta_port *pp) 4941 { 4942 int queue; 4943 4944 /* Disable port */ 4945 mvneta_port_disable(pp); 4946 4947 /* Set port default values */ 4948 mvneta_defaults_set(pp); 4949 4950 pp->txqs = devm_kcalloc(dev, txq_number, sizeof(*pp->txqs), GFP_KERNEL); 4951 if (!pp->txqs) 4952 return -ENOMEM; 4953 4954 /* Initialize TX descriptor rings */ 4955 for (queue = 0; queue < txq_number; queue++) { 4956 struct mvneta_tx_queue *txq = &pp->txqs[queue]; 4957 txq->id = queue; 4958 txq->size = pp->tx_ring_size; 4959 txq->done_pkts_coal = MVNETA_TXDONE_COAL_PKTS; 4960 } 4961 4962 pp->rxqs = devm_kcalloc(dev, rxq_number, sizeof(*pp->rxqs), GFP_KERNEL); 4963 if (!pp->rxqs) 4964 return -ENOMEM; 4965 4966 /* Create Rx descriptor rings */ 4967 for (queue = 0; queue < rxq_number; queue++) { 4968 struct mvneta_rx_queue *rxq = &pp->rxqs[queue]; 4969 rxq->id = queue; 4970 rxq->size = pp->rx_ring_size; 4971 rxq->pkts_coal = MVNETA_RX_COAL_PKTS; 4972 rxq->time_coal = MVNETA_RX_COAL_USEC; 4973 rxq->buf_virt_addr 4974 = devm_kmalloc_array(pp->dev->dev.parent, 4975 rxq->size, 4976 sizeof(*rxq->buf_virt_addr), 4977 GFP_KERNEL); 4978 if (!rxq->buf_virt_addr) 4979 return -ENOMEM; 4980 } 4981 4982 return 0; 4983 } 4984 4985 /* platform glue : initialize decoding windows */ 4986 static void mvneta_conf_mbus_windows(struct mvneta_port *pp, 4987 const struct mbus_dram_target_info *dram) 4988 { 4989 u32 win_enable; 4990 u32 win_protect; 4991 int i; 4992 4993 for (i = 0; i < 6; i++) { 4994 mvreg_write(pp, MVNETA_WIN_BASE(i), 0); 4995 mvreg_write(pp, MVNETA_WIN_SIZE(i), 0); 4996 4997 if (i < 4) 4998 mvreg_write(pp, MVNETA_WIN_REMAP(i), 0); 4999 } 5000 5001 win_enable = 0x3f; 5002 win_protect = 0; 5003 5004 if (dram) { 5005 for (i = 0; i < dram->num_cs; i++) { 5006 const struct mbus_dram_window *cs = dram->cs + i; 5007 5008 mvreg_write(pp, MVNETA_WIN_BASE(i), 5009 (cs->base & 0xffff0000) | 5010 (cs->mbus_attr << 8) | 5011 dram->mbus_dram_target_id); 5012 5013 mvreg_write(pp, MVNETA_WIN_SIZE(i), 5014 (cs->size - 1) & 0xffff0000); 5015 5016 win_enable &= ~(1 << i); 5017 win_protect |= 3 << (2 * i); 5018 } 5019 } else { 5020 /* For Armada3700 open default 4GB Mbus window, leaving 5021 * arbitration of target/attribute to a different layer 5022 * of configuration. 5023 */ 5024 mvreg_write(pp, MVNETA_WIN_SIZE(0), 0xffff0000); 5025 win_enable &= ~BIT(0); 5026 win_protect = 3; 5027 } 5028 5029 mvreg_write(pp, MVNETA_BASE_ADDR_ENABLE, win_enable); 5030 mvreg_write(pp, MVNETA_ACCESS_PROTECT_ENABLE, win_protect); 5031 } 5032 5033 /* Power up the port */ 5034 static int mvneta_port_power_up(struct mvneta_port *pp, int phy_mode) 5035 { 5036 /* MAC Cause register should be cleared */ 5037 mvreg_write(pp, MVNETA_UNIT_INTR_CAUSE, 0); 5038 5039 if (phy_mode != PHY_INTERFACE_MODE_QSGMII && 5040 phy_mode != PHY_INTERFACE_MODE_SGMII && 5041 !phy_interface_mode_is_8023z(phy_mode) && 5042 !phy_interface_mode_is_rgmii(phy_mode)) 5043 return -EINVAL; 5044 5045 return 0; 5046 } 5047 5048 /* Device initialization routine */ 5049 static int mvneta_probe(struct platform_device *pdev) 5050 { 5051 struct device_node *dn = pdev->dev.of_node; 5052 struct device_node *bm_node; 5053 struct mvneta_port *pp; 5054 struct net_device *dev; 5055 struct phylink *phylink; 5056 struct phy *comphy; 5057 const char *dt_mac_addr; 5058 char hw_mac_addr[ETH_ALEN]; 5059 phy_interface_t phy_mode; 5060 const char *mac_from; 5061 int tx_csum_limit; 5062 int err; 5063 int cpu; 5064 5065 dev = devm_alloc_etherdev_mqs(&pdev->dev, sizeof(struct mvneta_port), 5066 txq_number, rxq_number); 5067 if (!dev) 5068 return -ENOMEM; 5069 5070 dev->irq = irq_of_parse_and_map(dn, 0); 5071 if (dev->irq == 0) 5072 return -EINVAL; 5073 5074 err = of_get_phy_mode(dn, &phy_mode); 5075 if (err) { 5076 dev_err(&pdev->dev, "incorrect phy-mode\n"); 5077 goto err_free_irq; 5078 } 5079 5080 comphy = devm_of_phy_get(&pdev->dev, dn, NULL); 5081 if (comphy == ERR_PTR(-EPROBE_DEFER)) { 5082 err = -EPROBE_DEFER; 5083 goto err_free_irq; 5084 } else if (IS_ERR(comphy)) { 5085 comphy = NULL; 5086 } 5087 5088 pp = netdev_priv(dev); 5089 spin_lock_init(&pp->lock); 5090 5091 pp->phylink_config.dev = &dev->dev; 5092 pp->phylink_config.type = PHYLINK_NETDEV; 5093 5094 phylink = phylink_create(&pp->phylink_config, pdev->dev.fwnode, 5095 phy_mode, &mvneta_phylink_ops); 5096 if (IS_ERR(phylink)) { 5097 err = PTR_ERR(phylink); 5098 goto err_free_irq; 5099 } 5100 5101 dev->tx_queue_len = MVNETA_MAX_TXD; 5102 dev->watchdog_timeo = 5 * HZ; 5103 dev->netdev_ops = &mvneta_netdev_ops; 5104 5105 dev->ethtool_ops = &mvneta_eth_tool_ops; 5106 5107 pp->phylink = phylink; 5108 pp->comphy = comphy; 5109 pp->phy_interface = phy_mode; 5110 pp->dn = dn; 5111 5112 pp->rxq_def = rxq_def; 5113 pp->indir[0] = rxq_def; 5114 5115 /* Get special SoC configurations */ 5116 if (of_device_is_compatible(dn, "marvell,armada-3700-neta")) 5117 pp->neta_armada3700 = true; 5118 5119 pp->clk = devm_clk_get(&pdev->dev, "core"); 5120 if (IS_ERR(pp->clk)) 5121 pp->clk = devm_clk_get(&pdev->dev, NULL); 5122 if (IS_ERR(pp->clk)) { 5123 err = PTR_ERR(pp->clk); 5124 goto err_free_phylink; 5125 } 5126 5127 clk_prepare_enable(pp->clk); 5128 5129 pp->clk_bus = devm_clk_get(&pdev->dev, "bus"); 5130 if (!IS_ERR(pp->clk_bus)) 5131 clk_prepare_enable(pp->clk_bus); 5132 5133 pp->base = devm_platform_ioremap_resource(pdev, 0); 5134 if (IS_ERR(pp->base)) { 5135 err = PTR_ERR(pp->base); 5136 goto err_clk; 5137 } 5138 5139 /* Alloc per-cpu port structure */ 5140 pp->ports = alloc_percpu(struct mvneta_pcpu_port); 5141 if (!pp->ports) { 5142 err = -ENOMEM; 5143 goto err_clk; 5144 } 5145 5146 /* Alloc per-cpu stats */ 5147 pp->stats = netdev_alloc_pcpu_stats(struct mvneta_pcpu_stats); 5148 if (!pp->stats) { 5149 err = -ENOMEM; 5150 goto err_free_ports; 5151 } 5152 5153 dt_mac_addr = of_get_mac_address(dn); 5154 if (!IS_ERR(dt_mac_addr)) { 5155 mac_from = "device tree"; 5156 ether_addr_copy(dev->dev_addr, dt_mac_addr); 5157 } else { 5158 mvneta_get_mac_addr(pp, hw_mac_addr); 5159 if (is_valid_ether_addr(hw_mac_addr)) { 5160 mac_from = "hardware"; 5161 memcpy(dev->dev_addr, hw_mac_addr, ETH_ALEN); 5162 } else { 5163 mac_from = "random"; 5164 eth_hw_addr_random(dev); 5165 } 5166 } 5167 5168 if (!of_property_read_u32(dn, "tx-csum-limit", &tx_csum_limit)) { 5169 if (tx_csum_limit < 0 || 5170 tx_csum_limit > MVNETA_TX_CSUM_MAX_SIZE) { 5171 tx_csum_limit = MVNETA_TX_CSUM_DEF_SIZE; 5172 dev_info(&pdev->dev, 5173 "Wrong TX csum limit in DT, set to %dB\n", 5174 MVNETA_TX_CSUM_DEF_SIZE); 5175 } 5176 } else if (of_device_is_compatible(dn, "marvell,armada-370-neta")) { 5177 tx_csum_limit = MVNETA_TX_CSUM_DEF_SIZE; 5178 } else { 5179 tx_csum_limit = MVNETA_TX_CSUM_MAX_SIZE; 5180 } 5181 5182 pp->tx_csum_limit = tx_csum_limit; 5183 5184 pp->dram_target_info = mv_mbus_dram_info(); 5185 /* Armada3700 requires setting default configuration of Mbus 5186 * windows, however without using filled mbus_dram_target_info 5187 * structure. 5188 */ 5189 if (pp->dram_target_info || pp->neta_armada3700) 5190 mvneta_conf_mbus_windows(pp, pp->dram_target_info); 5191 5192 pp->tx_ring_size = MVNETA_MAX_TXD; 5193 pp->rx_ring_size = MVNETA_MAX_RXD; 5194 5195 pp->dev = dev; 5196 SET_NETDEV_DEV(dev, &pdev->dev); 5197 5198 pp->id = global_port_id++; 5199 5200 /* Obtain access to BM resources if enabled and already initialized */ 5201 bm_node = of_parse_phandle(dn, "buffer-manager", 0); 5202 if (bm_node) { 5203 pp->bm_priv = mvneta_bm_get(bm_node); 5204 if (pp->bm_priv) { 5205 err = mvneta_bm_port_init(pdev, pp); 5206 if (err < 0) { 5207 dev_info(&pdev->dev, 5208 "use SW buffer management\n"); 5209 mvneta_bm_put(pp->bm_priv); 5210 pp->bm_priv = NULL; 5211 } 5212 } 5213 /* Set RX packet offset correction for platforms, whose 5214 * NET_SKB_PAD, exceeds 64B. It should be 64B for 64-bit 5215 * platforms and 0B for 32-bit ones. 5216 */ 5217 pp->rx_offset_correction = max(0, 5218 NET_SKB_PAD - 5219 MVNETA_RX_PKT_OFFSET_CORRECTION); 5220 } 5221 of_node_put(bm_node); 5222 5223 /* sw buffer management */ 5224 if (!pp->bm_priv) 5225 pp->rx_offset_correction = MVNETA_SKB_HEADROOM; 5226 5227 err = mvneta_init(&pdev->dev, pp); 5228 if (err < 0) 5229 goto err_netdev; 5230 5231 err = mvneta_port_power_up(pp, pp->phy_interface); 5232 if (err < 0) { 5233 dev_err(&pdev->dev, "can't power up port\n"); 5234 return err; 5235 } 5236 5237 /* Armada3700 network controller does not support per-cpu 5238 * operation, so only single NAPI should be initialized. 5239 */ 5240 if (pp->neta_armada3700) { 5241 netif_napi_add(dev, &pp->napi, mvneta_poll, NAPI_POLL_WEIGHT); 5242 } else { 5243 for_each_present_cpu(cpu) { 5244 struct mvneta_pcpu_port *port = 5245 per_cpu_ptr(pp->ports, cpu); 5246 5247 netif_napi_add(dev, &port->napi, mvneta_poll, 5248 NAPI_POLL_WEIGHT); 5249 port->pp = pp; 5250 } 5251 } 5252 5253 dev->features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | 5254 NETIF_F_TSO | NETIF_F_RXCSUM; 5255 dev->hw_features |= dev->features; 5256 dev->vlan_features |= dev->features; 5257 dev->priv_flags |= IFF_LIVE_ADDR_CHANGE; 5258 dev->gso_max_segs = MVNETA_MAX_TSO_SEGS; 5259 5260 /* MTU range: 68 - 9676 */ 5261 dev->min_mtu = ETH_MIN_MTU; 5262 /* 9676 == 9700 - 20 and rounding to 8 */ 5263 dev->max_mtu = 9676; 5264 5265 err = register_netdev(dev); 5266 if (err < 0) { 5267 dev_err(&pdev->dev, "failed to register\n"); 5268 goto err_netdev; 5269 } 5270 5271 netdev_info(dev, "Using %s mac address %pM\n", mac_from, 5272 dev->dev_addr); 5273 5274 platform_set_drvdata(pdev, pp->dev); 5275 5276 return 0; 5277 5278 err_netdev: 5279 if (pp->bm_priv) { 5280 mvneta_bm_pool_destroy(pp->bm_priv, pp->pool_long, 1 << pp->id); 5281 mvneta_bm_pool_destroy(pp->bm_priv, pp->pool_short, 5282 1 << pp->id); 5283 mvneta_bm_put(pp->bm_priv); 5284 } 5285 free_percpu(pp->stats); 5286 err_free_ports: 5287 free_percpu(pp->ports); 5288 err_clk: 5289 clk_disable_unprepare(pp->clk_bus); 5290 clk_disable_unprepare(pp->clk); 5291 err_free_phylink: 5292 if (pp->phylink) 5293 phylink_destroy(pp->phylink); 5294 err_free_irq: 5295 irq_dispose_mapping(dev->irq); 5296 return err; 5297 } 5298 5299 /* Device removal routine */ 5300 static int mvneta_remove(struct platform_device *pdev) 5301 { 5302 struct net_device *dev = platform_get_drvdata(pdev); 5303 struct mvneta_port *pp = netdev_priv(dev); 5304 5305 unregister_netdev(dev); 5306 clk_disable_unprepare(pp->clk_bus); 5307 clk_disable_unprepare(pp->clk); 5308 free_percpu(pp->ports); 5309 free_percpu(pp->stats); 5310 irq_dispose_mapping(dev->irq); 5311 phylink_destroy(pp->phylink); 5312 5313 if (pp->bm_priv) { 5314 mvneta_bm_pool_destroy(pp->bm_priv, pp->pool_long, 1 << pp->id); 5315 mvneta_bm_pool_destroy(pp->bm_priv, pp->pool_short, 5316 1 << pp->id); 5317 mvneta_bm_put(pp->bm_priv); 5318 } 5319 5320 return 0; 5321 } 5322 5323 #ifdef CONFIG_PM_SLEEP 5324 static int mvneta_suspend(struct device *device) 5325 { 5326 int queue; 5327 struct net_device *dev = dev_get_drvdata(device); 5328 struct mvneta_port *pp = netdev_priv(dev); 5329 5330 if (!netif_running(dev)) 5331 goto clean_exit; 5332 5333 if (!pp->neta_armada3700) { 5334 spin_lock(&pp->lock); 5335 pp->is_stopped = true; 5336 spin_unlock(&pp->lock); 5337 5338 cpuhp_state_remove_instance_nocalls(online_hpstate, 5339 &pp->node_online); 5340 cpuhp_state_remove_instance_nocalls(CPUHP_NET_MVNETA_DEAD, 5341 &pp->node_dead); 5342 } 5343 5344 rtnl_lock(); 5345 mvneta_stop_dev(pp); 5346 rtnl_unlock(); 5347 5348 for (queue = 0; queue < rxq_number; queue++) { 5349 struct mvneta_rx_queue *rxq = &pp->rxqs[queue]; 5350 5351 mvneta_rxq_drop_pkts(pp, rxq); 5352 } 5353 5354 for (queue = 0; queue < txq_number; queue++) { 5355 struct mvneta_tx_queue *txq = &pp->txqs[queue]; 5356 5357 mvneta_txq_hw_deinit(pp, txq); 5358 } 5359 5360 clean_exit: 5361 netif_device_detach(dev); 5362 clk_disable_unprepare(pp->clk_bus); 5363 clk_disable_unprepare(pp->clk); 5364 5365 return 0; 5366 } 5367 5368 static int mvneta_resume(struct device *device) 5369 { 5370 struct platform_device *pdev = to_platform_device(device); 5371 struct net_device *dev = dev_get_drvdata(device); 5372 struct mvneta_port *pp = netdev_priv(dev); 5373 int err, queue; 5374 5375 clk_prepare_enable(pp->clk); 5376 if (!IS_ERR(pp->clk_bus)) 5377 clk_prepare_enable(pp->clk_bus); 5378 if (pp->dram_target_info || pp->neta_armada3700) 5379 mvneta_conf_mbus_windows(pp, pp->dram_target_info); 5380 if (pp->bm_priv) { 5381 err = mvneta_bm_port_init(pdev, pp); 5382 if (err < 0) { 5383 dev_info(&pdev->dev, "use SW buffer management\n"); 5384 pp->rx_offset_correction = MVNETA_SKB_HEADROOM; 5385 pp->bm_priv = NULL; 5386 } 5387 } 5388 mvneta_defaults_set(pp); 5389 err = mvneta_port_power_up(pp, pp->phy_interface); 5390 if (err < 0) { 5391 dev_err(device, "can't power up port\n"); 5392 return err; 5393 } 5394 5395 netif_device_attach(dev); 5396 5397 if (!netif_running(dev)) 5398 return 0; 5399 5400 for (queue = 0; queue < rxq_number; queue++) { 5401 struct mvneta_rx_queue *rxq = &pp->rxqs[queue]; 5402 5403 rxq->next_desc_to_proc = 0; 5404 mvneta_rxq_hw_init(pp, rxq); 5405 } 5406 5407 for (queue = 0; queue < txq_number; queue++) { 5408 struct mvneta_tx_queue *txq = &pp->txqs[queue]; 5409 5410 txq->next_desc_to_proc = 0; 5411 mvneta_txq_hw_init(pp, txq); 5412 } 5413 5414 if (!pp->neta_armada3700) { 5415 spin_lock(&pp->lock); 5416 pp->is_stopped = false; 5417 spin_unlock(&pp->lock); 5418 cpuhp_state_add_instance_nocalls(online_hpstate, 5419 &pp->node_online); 5420 cpuhp_state_add_instance_nocalls(CPUHP_NET_MVNETA_DEAD, 5421 &pp->node_dead); 5422 } 5423 5424 rtnl_lock(); 5425 mvneta_start_dev(pp); 5426 rtnl_unlock(); 5427 mvneta_set_rx_mode(dev); 5428 5429 return 0; 5430 } 5431 #endif 5432 5433 static SIMPLE_DEV_PM_OPS(mvneta_pm_ops, mvneta_suspend, mvneta_resume); 5434 5435 static const struct of_device_id mvneta_match[] = { 5436 { .compatible = "marvell,armada-370-neta" }, 5437 { .compatible = "marvell,armada-xp-neta" }, 5438 { .compatible = "marvell,armada-3700-neta" }, 5439 { } 5440 }; 5441 MODULE_DEVICE_TABLE(of, mvneta_match); 5442 5443 static struct platform_driver mvneta_driver = { 5444 .probe = mvneta_probe, 5445 .remove = mvneta_remove, 5446 .driver = { 5447 .name = MVNETA_DRIVER_NAME, 5448 .of_match_table = mvneta_match, 5449 .pm = &mvneta_pm_ops, 5450 }, 5451 }; 5452 5453 static int __init mvneta_driver_init(void) 5454 { 5455 int ret; 5456 5457 ret = cpuhp_setup_state_multi(CPUHP_AP_ONLINE_DYN, "net/mvneta:online", 5458 mvneta_cpu_online, 5459 mvneta_cpu_down_prepare); 5460 if (ret < 0) 5461 goto out; 5462 online_hpstate = ret; 5463 ret = cpuhp_setup_state_multi(CPUHP_NET_MVNETA_DEAD, "net/mvneta:dead", 5464 NULL, mvneta_cpu_dead); 5465 if (ret) 5466 goto err_dead; 5467 5468 ret = platform_driver_register(&mvneta_driver); 5469 if (ret) 5470 goto err; 5471 return 0; 5472 5473 err: 5474 cpuhp_remove_multi_state(CPUHP_NET_MVNETA_DEAD); 5475 err_dead: 5476 cpuhp_remove_multi_state(online_hpstate); 5477 out: 5478 return ret; 5479 } 5480 module_init(mvneta_driver_init); 5481 5482 static void __exit mvneta_driver_exit(void) 5483 { 5484 platform_driver_unregister(&mvneta_driver); 5485 cpuhp_remove_multi_state(CPUHP_NET_MVNETA_DEAD); 5486 cpuhp_remove_multi_state(online_hpstate); 5487 } 5488 module_exit(mvneta_driver_exit); 5489 5490 MODULE_DESCRIPTION("Marvell NETA Ethernet Driver - www.marvell.com"); 5491 MODULE_AUTHOR("Rami Rosen <rosenr@marvell.com>, Thomas Petazzoni <thomas.petazzoni@free-electrons.com>"); 5492 MODULE_LICENSE("GPL"); 5493 5494 module_param(rxq_number, int, 0444); 5495 module_param(txq_number, int, 0444); 5496 5497 module_param(rxq_def, int, 0444); 5498 module_param(rx_copybreak, int, 0644); 5499