1c5aff182SThomas Petazzoni /* 2c5aff182SThomas Petazzoni * Driver for Marvell NETA network card for Armada XP and Armada 370 SoCs. 3c5aff182SThomas Petazzoni * 4c5aff182SThomas Petazzoni * Copyright (C) 2012 Marvell 5c5aff182SThomas Petazzoni * 6c5aff182SThomas Petazzoni * Rami Rosen <rosenr@marvell.com> 7c5aff182SThomas Petazzoni * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> 8c5aff182SThomas Petazzoni * 9c5aff182SThomas Petazzoni * This file is licensed under the terms of the GNU General Public 10c5aff182SThomas Petazzoni * License version 2. This program is licensed "as is" without any 11c5aff182SThomas Petazzoni * warranty of any kind, whether express or implied. 12c5aff182SThomas Petazzoni */ 13c5aff182SThomas Petazzoni 14c5aff182SThomas Petazzoni #include <linux/kernel.h> 15c5aff182SThomas Petazzoni #include <linux/netdevice.h> 16c5aff182SThomas Petazzoni #include <linux/etherdevice.h> 17c5aff182SThomas Petazzoni #include <linux/platform_device.h> 18c5aff182SThomas Petazzoni #include <linux/skbuff.h> 19c5aff182SThomas Petazzoni #include <linux/inetdevice.h> 20c5aff182SThomas Petazzoni #include <linux/mbus.h> 21c5aff182SThomas Petazzoni #include <linux/module.h> 22c5aff182SThomas Petazzoni #include <linux/interrupt.h> 232d39d120SDavid S. Miller #include <linux/if_vlan.h> 24c5aff182SThomas Petazzoni #include <net/ip.h> 25c5aff182SThomas Petazzoni #include <net/ipv6.h> 26c3f0dd38SThomas Petazzoni #include <linux/io.h> 272adb719dSEzequiel Garcia #include <net/tso.h> 28c5aff182SThomas Petazzoni #include <linux/of.h> 29c5aff182SThomas Petazzoni #include <linux/of_irq.h> 30c5aff182SThomas Petazzoni #include <linux/of_mdio.h> 31c5aff182SThomas Petazzoni #include <linux/of_net.h> 32c5aff182SThomas Petazzoni #include <linux/of_address.h> 33c5aff182SThomas Petazzoni #include <linux/phy.h> 34189dd626SThomas Petazzoni #include <linux/clk.h> 35f8642885SMaxime Ripard #include <linux/cpu.h> 36c5aff182SThomas Petazzoni 37c5aff182SThomas Petazzoni /* Registers */ 38c5aff182SThomas Petazzoni #define MVNETA_RXQ_CONFIG_REG(q) (0x1400 + ((q) << 2)) 39c5aff182SThomas Petazzoni #define MVNETA_RXQ_HW_BUF_ALLOC BIT(1) 40c5aff182SThomas Petazzoni #define MVNETA_RXQ_PKT_OFFSET_ALL_MASK (0xf << 8) 41c5aff182SThomas Petazzoni #define MVNETA_RXQ_PKT_OFFSET_MASK(offs) ((offs) << 8) 42c5aff182SThomas Petazzoni #define MVNETA_RXQ_THRESHOLD_REG(q) (0x14c0 + ((q) << 2)) 43c5aff182SThomas Petazzoni #define MVNETA_RXQ_NON_OCCUPIED(v) ((v) << 16) 44c5aff182SThomas Petazzoni #define MVNETA_RXQ_BASE_ADDR_REG(q) (0x1480 + ((q) << 2)) 45c5aff182SThomas Petazzoni #define MVNETA_RXQ_SIZE_REG(q) (0x14a0 + ((q) << 2)) 46c5aff182SThomas Petazzoni #define MVNETA_RXQ_BUF_SIZE_SHIFT 19 47c5aff182SThomas Petazzoni #define MVNETA_RXQ_BUF_SIZE_MASK (0x1fff << 19) 48c5aff182SThomas Petazzoni #define MVNETA_RXQ_STATUS_REG(q) (0x14e0 + ((q) << 2)) 49c5aff182SThomas Petazzoni #define MVNETA_RXQ_OCCUPIED_ALL_MASK 0x3fff 50c5aff182SThomas Petazzoni #define MVNETA_RXQ_STATUS_UPDATE_REG(q) (0x1500 + ((q) << 2)) 51c5aff182SThomas Petazzoni #define MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT 16 52c5aff182SThomas Petazzoni #define MVNETA_RXQ_ADD_NON_OCCUPIED_MAX 255 53c5aff182SThomas Petazzoni #define MVNETA_PORT_RX_RESET 0x1cc0 54c5aff182SThomas Petazzoni #define MVNETA_PORT_RX_DMA_RESET BIT(0) 55c5aff182SThomas Petazzoni #define MVNETA_PHY_ADDR 0x2000 56c5aff182SThomas Petazzoni #define MVNETA_PHY_ADDR_MASK 0x1f 57c5aff182SThomas Petazzoni #define MVNETA_MBUS_RETRY 0x2010 58c5aff182SThomas Petazzoni #define MVNETA_UNIT_INTR_CAUSE 0x2080 59c5aff182SThomas Petazzoni #define MVNETA_UNIT_CONTROL 0x20B0 60c5aff182SThomas Petazzoni #define MVNETA_PHY_POLLING_ENABLE BIT(1) 61c5aff182SThomas Petazzoni #define MVNETA_WIN_BASE(w) (0x2200 + ((w) << 3)) 62c5aff182SThomas Petazzoni #define MVNETA_WIN_SIZE(w) (0x2204 + ((w) << 3)) 63c5aff182SThomas Petazzoni #define MVNETA_WIN_REMAP(w) (0x2280 + ((w) << 2)) 64c5aff182SThomas Petazzoni #define MVNETA_BASE_ADDR_ENABLE 0x2290 65c5aff182SThomas Petazzoni #define MVNETA_PORT_CONFIG 0x2400 66c5aff182SThomas Petazzoni #define MVNETA_UNI_PROMISC_MODE BIT(0) 67c5aff182SThomas Petazzoni #define MVNETA_DEF_RXQ(q) ((q) << 1) 68c5aff182SThomas Petazzoni #define MVNETA_DEF_RXQ_ARP(q) ((q) << 4) 69c5aff182SThomas Petazzoni #define MVNETA_TX_UNSET_ERR_SUM BIT(12) 70c5aff182SThomas Petazzoni #define MVNETA_DEF_RXQ_TCP(q) ((q) << 16) 71c5aff182SThomas Petazzoni #define MVNETA_DEF_RXQ_UDP(q) ((q) << 19) 72c5aff182SThomas Petazzoni #define MVNETA_DEF_RXQ_BPDU(q) ((q) << 22) 73c5aff182SThomas Petazzoni #define MVNETA_RX_CSUM_WITH_PSEUDO_HDR BIT(25) 74c5aff182SThomas Petazzoni #define MVNETA_PORT_CONFIG_DEFL_VALUE(q) (MVNETA_DEF_RXQ(q) | \ 75c5aff182SThomas Petazzoni MVNETA_DEF_RXQ_ARP(q) | \ 76c5aff182SThomas Petazzoni MVNETA_DEF_RXQ_TCP(q) | \ 77c5aff182SThomas Petazzoni MVNETA_DEF_RXQ_UDP(q) | \ 78c5aff182SThomas Petazzoni MVNETA_DEF_RXQ_BPDU(q) | \ 79c5aff182SThomas Petazzoni MVNETA_TX_UNSET_ERR_SUM | \ 80c5aff182SThomas Petazzoni MVNETA_RX_CSUM_WITH_PSEUDO_HDR) 81c5aff182SThomas Petazzoni #define MVNETA_PORT_CONFIG_EXTEND 0x2404 82c5aff182SThomas Petazzoni #define MVNETA_MAC_ADDR_LOW 0x2414 83c5aff182SThomas Petazzoni #define MVNETA_MAC_ADDR_HIGH 0x2418 84c5aff182SThomas Petazzoni #define MVNETA_SDMA_CONFIG 0x241c 85c5aff182SThomas Petazzoni #define MVNETA_SDMA_BRST_SIZE_16 4 86c5aff182SThomas Petazzoni #define MVNETA_RX_BRST_SZ_MASK(burst) ((burst) << 1) 87c5aff182SThomas Petazzoni #define MVNETA_RX_NO_DATA_SWAP BIT(4) 88c5aff182SThomas Petazzoni #define MVNETA_TX_NO_DATA_SWAP BIT(5) 899ad8fef6SThomas Petazzoni #define MVNETA_DESC_SWAP BIT(6) 90c5aff182SThomas Petazzoni #define MVNETA_TX_BRST_SZ_MASK(burst) ((burst) << 22) 91c5aff182SThomas Petazzoni #define MVNETA_PORT_STATUS 0x2444 92c5aff182SThomas Petazzoni #define MVNETA_TX_IN_PRGRS BIT(1) 93c5aff182SThomas Petazzoni #define MVNETA_TX_FIFO_EMPTY BIT(8) 94c5aff182SThomas Petazzoni #define MVNETA_RX_MIN_FRAME_SIZE 0x247c 953f1dd4bcSThomas Petazzoni #define MVNETA_SERDES_CFG 0x24A0 965445eaf3SArnaud Patard \(Rtp\) #define MVNETA_SGMII_SERDES_PROTO 0x0cc7 973f1dd4bcSThomas Petazzoni #define MVNETA_QSGMII_SERDES_PROTO 0x0667 98c5aff182SThomas Petazzoni #define MVNETA_TYPE_PRIO 0x24bc 99c5aff182SThomas Petazzoni #define MVNETA_FORCE_UNI BIT(21) 100c5aff182SThomas Petazzoni #define MVNETA_TXQ_CMD_1 0x24e4 101c5aff182SThomas Petazzoni #define MVNETA_TXQ_CMD 0x2448 102c5aff182SThomas Petazzoni #define MVNETA_TXQ_DISABLE_SHIFT 8 103c5aff182SThomas Petazzoni #define MVNETA_TXQ_ENABLE_MASK 0x000000ff 104898b2970SStas Sergeev #define MVNETA_GMAC_CLOCK_DIVIDER 0x24f4 105898b2970SStas Sergeev #define MVNETA_GMAC_1MS_CLOCK_ENABLE BIT(31) 106c5aff182SThomas Petazzoni #define MVNETA_ACC_MODE 0x2500 107c5aff182SThomas Petazzoni #define MVNETA_CPU_MAP(cpu) (0x2540 + ((cpu) << 2)) 108c5aff182SThomas Petazzoni #define MVNETA_CPU_RXQ_ACCESS_ALL_MASK 0x000000ff 109c5aff182SThomas Petazzoni #define MVNETA_CPU_TXQ_ACCESS_ALL_MASK 0x0000ff00 110c5aff182SThomas Petazzoni #define MVNETA_RXQ_TIME_COAL_REG(q) (0x2580 + ((q) << 2)) 11140ba35e7Swilly tarreau 11240ba35e7Swilly tarreau /* Exception Interrupt Port/Queue Cause register */ 11340ba35e7Swilly tarreau 114c5aff182SThomas Petazzoni #define MVNETA_INTR_NEW_CAUSE 0x25a0 115c5aff182SThomas Petazzoni #define MVNETA_INTR_NEW_MASK 0x25a4 11640ba35e7Swilly tarreau 11740ba35e7Swilly tarreau /* bits 0..7 = TXQ SENT, one bit per queue. 11840ba35e7Swilly tarreau * bits 8..15 = RXQ OCCUP, one bit per queue. 11940ba35e7Swilly tarreau * bits 16..23 = RXQ FREE, one bit per queue. 12040ba35e7Swilly tarreau * bit 29 = OLD_REG_SUM, see old reg ? 12140ba35e7Swilly tarreau * bit 30 = TX_ERR_SUM, one bit for 4 ports 12240ba35e7Swilly tarreau * bit 31 = MISC_SUM, one bit for 4 ports 12340ba35e7Swilly tarreau */ 12440ba35e7Swilly tarreau #define MVNETA_TX_INTR_MASK(nr_txqs) (((1 << nr_txqs) - 1) << 0) 12540ba35e7Swilly tarreau #define MVNETA_TX_INTR_MASK_ALL (0xff << 0) 12640ba35e7Swilly tarreau #define MVNETA_RX_INTR_MASK(nr_rxqs) (((1 << nr_rxqs) - 1) << 8) 12740ba35e7Swilly tarreau #define MVNETA_RX_INTR_MASK_ALL (0xff << 8) 128898b2970SStas Sergeev #define MVNETA_MISCINTR_INTR_MASK BIT(31) 12940ba35e7Swilly tarreau 130c5aff182SThomas Petazzoni #define MVNETA_INTR_OLD_CAUSE 0x25a8 131c5aff182SThomas Petazzoni #define MVNETA_INTR_OLD_MASK 0x25ac 13240ba35e7Swilly tarreau 13340ba35e7Swilly tarreau /* Data Path Port/Queue Cause Register */ 134c5aff182SThomas Petazzoni #define MVNETA_INTR_MISC_CAUSE 0x25b0 135c5aff182SThomas Petazzoni #define MVNETA_INTR_MISC_MASK 0x25b4 13640ba35e7Swilly tarreau 13740ba35e7Swilly tarreau #define MVNETA_CAUSE_PHY_STATUS_CHANGE BIT(0) 13840ba35e7Swilly tarreau #define MVNETA_CAUSE_LINK_CHANGE BIT(1) 13940ba35e7Swilly tarreau #define MVNETA_CAUSE_PTP BIT(4) 14040ba35e7Swilly tarreau 14140ba35e7Swilly tarreau #define MVNETA_CAUSE_INTERNAL_ADDR_ERR BIT(7) 14240ba35e7Swilly tarreau #define MVNETA_CAUSE_RX_OVERRUN BIT(8) 14340ba35e7Swilly tarreau #define MVNETA_CAUSE_RX_CRC_ERROR BIT(9) 14440ba35e7Swilly tarreau #define MVNETA_CAUSE_RX_LARGE_PKT BIT(10) 14540ba35e7Swilly tarreau #define MVNETA_CAUSE_TX_UNDERUN BIT(11) 14640ba35e7Swilly tarreau #define MVNETA_CAUSE_PRBS_ERR BIT(12) 14740ba35e7Swilly tarreau #define MVNETA_CAUSE_PSC_SYNC_CHANGE BIT(13) 14840ba35e7Swilly tarreau #define MVNETA_CAUSE_SERDES_SYNC_ERR BIT(14) 14940ba35e7Swilly tarreau 15040ba35e7Swilly tarreau #define MVNETA_CAUSE_BMU_ALLOC_ERR_SHIFT 16 15140ba35e7Swilly tarreau #define MVNETA_CAUSE_BMU_ALLOC_ERR_ALL_MASK (0xF << MVNETA_CAUSE_BMU_ALLOC_ERR_SHIFT) 15240ba35e7Swilly tarreau #define MVNETA_CAUSE_BMU_ALLOC_ERR_MASK(pool) (1 << (MVNETA_CAUSE_BMU_ALLOC_ERR_SHIFT + (pool))) 15340ba35e7Swilly tarreau 15440ba35e7Swilly tarreau #define MVNETA_CAUSE_TXQ_ERROR_SHIFT 24 15540ba35e7Swilly tarreau #define MVNETA_CAUSE_TXQ_ERROR_ALL_MASK (0xFF << MVNETA_CAUSE_TXQ_ERROR_SHIFT) 15640ba35e7Swilly tarreau #define MVNETA_CAUSE_TXQ_ERROR_MASK(q) (1 << (MVNETA_CAUSE_TXQ_ERROR_SHIFT + (q))) 15740ba35e7Swilly tarreau 158c5aff182SThomas Petazzoni #define MVNETA_INTR_ENABLE 0x25b8 159c5aff182SThomas Petazzoni #define MVNETA_TXQ_INTR_ENABLE_ALL_MASK 0x0000ff00 16040ba35e7Swilly tarreau #define MVNETA_RXQ_INTR_ENABLE_ALL_MASK 0xff000000 // note: neta says it's 0x000000FF 16140ba35e7Swilly tarreau 162c5aff182SThomas Petazzoni #define MVNETA_RXQ_CMD 0x2680 163c5aff182SThomas Petazzoni #define MVNETA_RXQ_DISABLE_SHIFT 8 164c5aff182SThomas Petazzoni #define MVNETA_RXQ_ENABLE_MASK 0x000000ff 165c5aff182SThomas Petazzoni #define MVETH_TXQ_TOKEN_COUNT_REG(q) (0x2700 + ((q) << 4)) 166c5aff182SThomas Petazzoni #define MVETH_TXQ_TOKEN_CFG_REG(q) (0x2704 + ((q) << 4)) 167c5aff182SThomas Petazzoni #define MVNETA_GMAC_CTRL_0 0x2c00 168c5aff182SThomas Petazzoni #define MVNETA_GMAC_MAX_RX_SIZE_SHIFT 2 169c5aff182SThomas Petazzoni #define MVNETA_GMAC_MAX_RX_SIZE_MASK 0x7ffc 170c5aff182SThomas Petazzoni #define MVNETA_GMAC0_PORT_ENABLE BIT(0) 171c5aff182SThomas Petazzoni #define MVNETA_GMAC_CTRL_2 0x2c08 172898b2970SStas Sergeev #define MVNETA_GMAC2_INBAND_AN_ENABLE BIT(0) 173a79121d3SThomas Petazzoni #define MVNETA_GMAC2_PCS_ENABLE BIT(3) 174c5aff182SThomas Petazzoni #define MVNETA_GMAC2_PORT_RGMII BIT(4) 175c5aff182SThomas Petazzoni #define MVNETA_GMAC2_PORT_RESET BIT(6) 176c5aff182SThomas Petazzoni #define MVNETA_GMAC_STATUS 0x2c10 177c5aff182SThomas Petazzoni #define MVNETA_GMAC_LINK_UP BIT(0) 178c5aff182SThomas Petazzoni #define MVNETA_GMAC_SPEED_1000 BIT(1) 179c5aff182SThomas Petazzoni #define MVNETA_GMAC_SPEED_100 BIT(2) 180c5aff182SThomas Petazzoni #define MVNETA_GMAC_FULL_DUPLEX BIT(3) 181c5aff182SThomas Petazzoni #define MVNETA_GMAC_RX_FLOW_CTRL_ENABLE BIT(4) 182c5aff182SThomas Petazzoni #define MVNETA_GMAC_TX_FLOW_CTRL_ENABLE BIT(5) 183c5aff182SThomas Petazzoni #define MVNETA_GMAC_RX_FLOW_CTRL_ACTIVE BIT(6) 184c5aff182SThomas Petazzoni #define MVNETA_GMAC_TX_FLOW_CTRL_ACTIVE BIT(7) 185c5aff182SThomas Petazzoni #define MVNETA_GMAC_AUTONEG_CONFIG 0x2c0c 186c5aff182SThomas Petazzoni #define MVNETA_GMAC_FORCE_LINK_DOWN BIT(0) 187c5aff182SThomas Petazzoni #define MVNETA_GMAC_FORCE_LINK_PASS BIT(1) 188898b2970SStas Sergeev #define MVNETA_GMAC_INBAND_AN_ENABLE BIT(2) 189c5aff182SThomas Petazzoni #define MVNETA_GMAC_CONFIG_MII_SPEED BIT(5) 190c5aff182SThomas Petazzoni #define MVNETA_GMAC_CONFIG_GMII_SPEED BIT(6) 19171408602SThomas Petazzoni #define MVNETA_GMAC_AN_SPEED_EN BIT(7) 192898b2970SStas Sergeev #define MVNETA_GMAC_AN_FLOW_CTRL_EN BIT(11) 193c5aff182SThomas Petazzoni #define MVNETA_GMAC_CONFIG_FULL_DUPLEX BIT(12) 19471408602SThomas Petazzoni #define MVNETA_GMAC_AN_DUPLEX_EN BIT(13) 195c5aff182SThomas Petazzoni #define MVNETA_MIB_COUNTERS_BASE 0x3080 196c5aff182SThomas Petazzoni #define MVNETA_MIB_LATE_COLLISION 0x7c 197c5aff182SThomas Petazzoni #define MVNETA_DA_FILT_SPEC_MCAST 0x3400 198c5aff182SThomas Petazzoni #define MVNETA_DA_FILT_OTH_MCAST 0x3500 199c5aff182SThomas Petazzoni #define MVNETA_DA_FILT_UCAST_BASE 0x3600 200c5aff182SThomas Petazzoni #define MVNETA_TXQ_BASE_ADDR_REG(q) (0x3c00 + ((q) << 2)) 201c5aff182SThomas Petazzoni #define MVNETA_TXQ_SIZE_REG(q) (0x3c20 + ((q) << 2)) 202c5aff182SThomas Petazzoni #define MVNETA_TXQ_SENT_THRESH_ALL_MASK 0x3fff0000 203c5aff182SThomas Petazzoni #define MVNETA_TXQ_SENT_THRESH_MASK(coal) ((coal) << 16) 204c5aff182SThomas Petazzoni #define MVNETA_TXQ_UPDATE_REG(q) (0x3c60 + ((q) << 2)) 205c5aff182SThomas Petazzoni #define MVNETA_TXQ_DEC_SENT_SHIFT 16 206c5aff182SThomas Petazzoni #define MVNETA_TXQ_STATUS_REG(q) (0x3c40 + ((q) << 2)) 207c5aff182SThomas Petazzoni #define MVNETA_TXQ_SENT_DESC_SHIFT 16 208c5aff182SThomas Petazzoni #define MVNETA_TXQ_SENT_DESC_MASK 0x3fff0000 209c5aff182SThomas Petazzoni #define MVNETA_PORT_TX_RESET 0x3cf0 210c5aff182SThomas Petazzoni #define MVNETA_PORT_TX_DMA_RESET BIT(0) 211c5aff182SThomas Petazzoni #define MVNETA_TX_MTU 0x3e0c 212c5aff182SThomas Petazzoni #define MVNETA_TX_TOKEN_SIZE 0x3e14 213c5aff182SThomas Petazzoni #define MVNETA_TX_TOKEN_SIZE_MAX 0xffffffff 214c5aff182SThomas Petazzoni #define MVNETA_TXQ_TOKEN_SIZE_REG(q) (0x3e40 + ((q) << 2)) 215c5aff182SThomas Petazzoni #define MVNETA_TXQ_TOKEN_SIZE_MAX 0x7fffffff 216c5aff182SThomas Petazzoni 217c5aff182SThomas Petazzoni #define MVNETA_CAUSE_TXQ_SENT_DESC_ALL_MASK 0xff 218c5aff182SThomas Petazzoni 219c5aff182SThomas Petazzoni /* Descriptor ring Macros */ 220c5aff182SThomas Petazzoni #define MVNETA_QUEUE_NEXT_DESC(q, index) \ 221c5aff182SThomas Petazzoni (((index) < (q)->last_desc) ? ((index) + 1) : 0) 222c5aff182SThomas Petazzoni 223c5aff182SThomas Petazzoni /* Various constants */ 224c5aff182SThomas Petazzoni 225c5aff182SThomas Petazzoni /* Coalescing */ 226aebea2baSwilly tarreau #define MVNETA_TXDONE_COAL_PKTS 1 227c5aff182SThomas Petazzoni #define MVNETA_RX_COAL_PKTS 32 228c5aff182SThomas Petazzoni #define MVNETA_RX_COAL_USEC 100 229c5aff182SThomas Petazzoni 2306a20c175SThomas Petazzoni /* The two bytes Marvell header. Either contains a special value used 231c5aff182SThomas Petazzoni * by Marvell switches when a specific hardware mode is enabled (not 232c5aff182SThomas Petazzoni * supported by this driver) or is filled automatically by zeroes on 233c5aff182SThomas Petazzoni * the RX side. Those two bytes being at the front of the Ethernet 234c5aff182SThomas Petazzoni * header, they allow to have the IP header aligned on a 4 bytes 235c5aff182SThomas Petazzoni * boundary automatically: the hardware skips those two bytes on its 236c5aff182SThomas Petazzoni * own. 237c5aff182SThomas Petazzoni */ 238c5aff182SThomas Petazzoni #define MVNETA_MH_SIZE 2 239c5aff182SThomas Petazzoni 240c5aff182SThomas Petazzoni #define MVNETA_VLAN_TAG_LEN 4 241c5aff182SThomas Petazzoni 242c5aff182SThomas Petazzoni #define MVNETA_CPU_D_CACHE_LINE_SIZE 32 243c5aff182SThomas Petazzoni #define MVNETA_TX_CSUM_MAX_SIZE 9800 244c5aff182SThomas Petazzoni #define MVNETA_ACC_MODE_EXT 1 245c5aff182SThomas Petazzoni 246c5aff182SThomas Petazzoni /* Timeout constants */ 247c5aff182SThomas Petazzoni #define MVNETA_TX_DISABLE_TIMEOUT_MSEC 1000 248c5aff182SThomas Petazzoni #define MVNETA_RX_DISABLE_TIMEOUT_MSEC 1000 249c5aff182SThomas Petazzoni #define MVNETA_TX_FIFO_EMPTY_TIMEOUT 10000 250c5aff182SThomas Petazzoni 251c5aff182SThomas Petazzoni #define MVNETA_TX_MTU_MAX 0x3ffff 252c5aff182SThomas Petazzoni 2532adb719dSEzequiel Garcia /* TSO header size */ 2542adb719dSEzequiel Garcia #define TSO_HEADER_SIZE 128 2552adb719dSEzequiel Garcia 256c5aff182SThomas Petazzoni /* Max number of Rx descriptors */ 257c5aff182SThomas Petazzoni #define MVNETA_MAX_RXD 128 258c5aff182SThomas Petazzoni 259c5aff182SThomas Petazzoni /* Max number of Tx descriptors */ 260c5aff182SThomas Petazzoni #define MVNETA_MAX_TXD 532 261c5aff182SThomas Petazzoni 2628eef5f97SEzequiel Garcia /* Max number of allowed TCP segments for software TSO */ 2638eef5f97SEzequiel Garcia #define MVNETA_MAX_TSO_SEGS 100 2648eef5f97SEzequiel Garcia 2658eef5f97SEzequiel Garcia #define MVNETA_MAX_SKB_DESCS (MVNETA_MAX_TSO_SEGS * 2 + MAX_SKB_FRAGS) 2668eef5f97SEzequiel Garcia 267c5aff182SThomas Petazzoni /* descriptor aligned size */ 268c5aff182SThomas Petazzoni #define MVNETA_DESC_ALIGNED_SIZE 32 269c5aff182SThomas Petazzoni 270c5aff182SThomas Petazzoni #define MVNETA_RX_PKT_SIZE(mtu) \ 271c5aff182SThomas Petazzoni ALIGN((mtu) + MVNETA_MH_SIZE + MVNETA_VLAN_TAG_LEN + \ 272c5aff182SThomas Petazzoni ETH_HLEN + ETH_FCS_LEN, \ 273c5aff182SThomas Petazzoni MVNETA_CPU_D_CACHE_LINE_SIZE) 274c5aff182SThomas Petazzoni 2752e3173a3SEzequiel Garcia #define IS_TSO_HEADER(txq, addr) \ 2762e3173a3SEzequiel Garcia ((addr >= txq->tso_hdrs_phys) && \ 2772e3173a3SEzequiel Garcia (addr < txq->tso_hdrs_phys + txq->size * TSO_HEADER_SIZE)) 2782e3173a3SEzequiel Garcia 279c5aff182SThomas Petazzoni #define MVNETA_RX_BUF_SIZE(pkt_size) ((pkt_size) + NET_SKB_PAD) 280c5aff182SThomas Petazzoni 28174c41b04Swilly tarreau struct mvneta_pcpu_stats { 282c5aff182SThomas Petazzoni struct u64_stats_sync syncp; 28374c41b04Swilly tarreau u64 rx_packets; 28474c41b04Swilly tarreau u64 rx_bytes; 28574c41b04Swilly tarreau u64 tx_packets; 28674c41b04Swilly tarreau u64 tx_bytes; 287c5aff182SThomas Petazzoni }; 288c5aff182SThomas Petazzoni 28912bb03b4SMaxime Ripard struct mvneta_pcpu_port { 29012bb03b4SMaxime Ripard /* Pointer to the shared port */ 29112bb03b4SMaxime Ripard struct mvneta_port *pp; 29212bb03b4SMaxime Ripard 29312bb03b4SMaxime Ripard /* Pointer to the CPU-local NAPI struct */ 29412bb03b4SMaxime Ripard struct napi_struct napi; 29512bb03b4SMaxime Ripard 29612bb03b4SMaxime Ripard /* Cause of the previous interrupt */ 29712bb03b4SMaxime Ripard u32 cause_rx_tx; 29812bb03b4SMaxime Ripard }; 29912bb03b4SMaxime Ripard 300c5aff182SThomas Petazzoni struct mvneta_port { 30112bb03b4SMaxime Ripard struct mvneta_pcpu_port __percpu *ports; 30212bb03b4SMaxime Ripard struct mvneta_pcpu_stats __percpu *stats; 30312bb03b4SMaxime Ripard 304c5aff182SThomas Petazzoni int pkt_size; 3058ec2cd48Swilly tarreau unsigned int frag_size; 306c5aff182SThomas Petazzoni void __iomem *base; 307c5aff182SThomas Petazzoni struct mvneta_rx_queue *rxqs; 308c5aff182SThomas Petazzoni struct mvneta_tx_queue *txqs; 309c5aff182SThomas Petazzoni struct net_device *dev; 310f8642885SMaxime Ripard struct notifier_block cpu_notifier; 311c5aff182SThomas Petazzoni 312c5aff182SThomas Petazzoni /* Core clock */ 313189dd626SThomas Petazzoni struct clk *clk; 314c5aff182SThomas Petazzoni u8 mcast_count[256]; 315c5aff182SThomas Petazzoni u16 tx_ring_size; 316c5aff182SThomas Petazzoni u16 rx_ring_size; 317c5aff182SThomas Petazzoni 318c5aff182SThomas Petazzoni struct mii_bus *mii_bus; 319c5aff182SThomas Petazzoni struct phy_device *phy_dev; 320c5aff182SThomas Petazzoni phy_interface_t phy_interface; 321c5aff182SThomas Petazzoni struct device_node *phy_node; 322c5aff182SThomas Petazzoni unsigned int link; 323c5aff182SThomas Petazzoni unsigned int duplex; 324c5aff182SThomas Petazzoni unsigned int speed; 325b65657fcSSimon Guinot unsigned int tx_csum_limit; 326898b2970SStas Sergeev int use_inband_status:1; 327c5aff182SThomas Petazzoni }; 328c5aff182SThomas Petazzoni 3296a20c175SThomas Petazzoni /* The mvneta_tx_desc and mvneta_rx_desc structures describe the 330c5aff182SThomas Petazzoni * layout of the transmit and reception DMA descriptors, and their 331c5aff182SThomas Petazzoni * layout is therefore defined by the hardware design 332c5aff182SThomas Petazzoni */ 3336083ed44SThomas Petazzoni 334c5aff182SThomas Petazzoni #define MVNETA_TX_L3_OFF_SHIFT 0 335c5aff182SThomas Petazzoni #define MVNETA_TX_IP_HLEN_SHIFT 8 336c5aff182SThomas Petazzoni #define MVNETA_TX_L4_UDP BIT(16) 337c5aff182SThomas Petazzoni #define MVNETA_TX_L3_IP6 BIT(17) 338c5aff182SThomas Petazzoni #define MVNETA_TXD_IP_CSUM BIT(18) 339c5aff182SThomas Petazzoni #define MVNETA_TXD_Z_PAD BIT(19) 340c5aff182SThomas Petazzoni #define MVNETA_TXD_L_DESC BIT(20) 341c5aff182SThomas Petazzoni #define MVNETA_TXD_F_DESC BIT(21) 342c5aff182SThomas Petazzoni #define MVNETA_TXD_FLZ_DESC (MVNETA_TXD_Z_PAD | \ 343c5aff182SThomas Petazzoni MVNETA_TXD_L_DESC | \ 344c5aff182SThomas Petazzoni MVNETA_TXD_F_DESC) 345c5aff182SThomas Petazzoni #define MVNETA_TX_L4_CSUM_FULL BIT(30) 346c5aff182SThomas Petazzoni #define MVNETA_TX_L4_CSUM_NOT BIT(31) 347c5aff182SThomas Petazzoni 348c5aff182SThomas Petazzoni #define MVNETA_RXD_ERR_CRC 0x0 349c5aff182SThomas Petazzoni #define MVNETA_RXD_ERR_SUMMARY BIT(16) 350c5aff182SThomas Petazzoni #define MVNETA_RXD_ERR_OVERRUN BIT(17) 351c5aff182SThomas Petazzoni #define MVNETA_RXD_ERR_LEN BIT(18) 352c5aff182SThomas Petazzoni #define MVNETA_RXD_ERR_RESOURCE (BIT(17) | BIT(18)) 353c5aff182SThomas Petazzoni #define MVNETA_RXD_ERR_CODE_MASK (BIT(17) | BIT(18)) 354c5aff182SThomas Petazzoni #define MVNETA_RXD_L3_IP4 BIT(25) 355c5aff182SThomas Petazzoni #define MVNETA_RXD_FIRST_LAST_DESC (BIT(26) | BIT(27)) 356c5aff182SThomas Petazzoni #define MVNETA_RXD_L4_CSUM_OK BIT(30) 357c5aff182SThomas Petazzoni 3589ad8fef6SThomas Petazzoni #if defined(__LITTLE_ENDIAN) 3596083ed44SThomas Petazzoni struct mvneta_tx_desc { 3606083ed44SThomas Petazzoni u32 command; /* Options used by HW for packet transmitting.*/ 3616083ed44SThomas Petazzoni u16 reserverd1; /* csum_l4 (for future use) */ 3626083ed44SThomas Petazzoni u16 data_size; /* Data size of transmitted packet in bytes */ 3636083ed44SThomas Petazzoni u32 buf_phys_addr; /* Physical addr of transmitted buffer */ 3646083ed44SThomas Petazzoni u32 reserved2; /* hw_cmd - (for future use, PMT) */ 3656083ed44SThomas Petazzoni u32 reserved3[4]; /* Reserved - (for future use) */ 3666083ed44SThomas Petazzoni }; 3676083ed44SThomas Petazzoni 3686083ed44SThomas Petazzoni struct mvneta_rx_desc { 3696083ed44SThomas Petazzoni u32 status; /* Info about received packet */ 370c5aff182SThomas Petazzoni u16 reserved1; /* pnc_info - (for future use, PnC) */ 371c5aff182SThomas Petazzoni u16 data_size; /* Size of received packet in bytes */ 3726083ed44SThomas Petazzoni 373c5aff182SThomas Petazzoni u32 buf_phys_addr; /* Physical address of the buffer */ 374c5aff182SThomas Petazzoni u32 reserved2; /* pnc_flow_id (for future use, PnC) */ 3756083ed44SThomas Petazzoni 376c5aff182SThomas Petazzoni u32 buf_cookie; /* cookie for access to RX buffer in rx path */ 377c5aff182SThomas Petazzoni u16 reserved3; /* prefetch_cmd, for future use */ 378c5aff182SThomas Petazzoni u16 reserved4; /* csum_l4 - (for future use, PnC) */ 3796083ed44SThomas Petazzoni 380c5aff182SThomas Petazzoni u32 reserved5; /* pnc_extra PnC (for future use, PnC) */ 381c5aff182SThomas Petazzoni u32 reserved6; /* hw_cmd (for future use, PnC and HWF) */ 382c5aff182SThomas Petazzoni }; 3839ad8fef6SThomas Petazzoni #else 3849ad8fef6SThomas Petazzoni struct mvneta_tx_desc { 3859ad8fef6SThomas Petazzoni u16 data_size; /* Data size of transmitted packet in bytes */ 3869ad8fef6SThomas Petazzoni u16 reserverd1; /* csum_l4 (for future use) */ 3879ad8fef6SThomas Petazzoni u32 command; /* Options used by HW for packet transmitting.*/ 3889ad8fef6SThomas Petazzoni u32 reserved2; /* hw_cmd - (for future use, PMT) */ 3899ad8fef6SThomas Petazzoni u32 buf_phys_addr; /* Physical addr of transmitted buffer */ 3909ad8fef6SThomas Petazzoni u32 reserved3[4]; /* Reserved - (for future use) */ 3919ad8fef6SThomas Petazzoni }; 3929ad8fef6SThomas Petazzoni 3939ad8fef6SThomas Petazzoni struct mvneta_rx_desc { 3949ad8fef6SThomas Petazzoni u16 data_size; /* Size of received packet in bytes */ 3959ad8fef6SThomas Petazzoni u16 reserved1; /* pnc_info - (for future use, PnC) */ 3969ad8fef6SThomas Petazzoni u32 status; /* Info about received packet */ 3979ad8fef6SThomas Petazzoni 3989ad8fef6SThomas Petazzoni u32 reserved2; /* pnc_flow_id (for future use, PnC) */ 3999ad8fef6SThomas Petazzoni u32 buf_phys_addr; /* Physical address of the buffer */ 4009ad8fef6SThomas Petazzoni 4019ad8fef6SThomas Petazzoni u16 reserved4; /* csum_l4 - (for future use, PnC) */ 4029ad8fef6SThomas Petazzoni u16 reserved3; /* prefetch_cmd, for future use */ 4039ad8fef6SThomas Petazzoni u32 buf_cookie; /* cookie for access to RX buffer in rx path */ 4049ad8fef6SThomas Petazzoni 4059ad8fef6SThomas Petazzoni u32 reserved5; /* pnc_extra PnC (for future use, PnC) */ 4069ad8fef6SThomas Petazzoni u32 reserved6; /* hw_cmd (for future use, PnC and HWF) */ 4079ad8fef6SThomas Petazzoni }; 4089ad8fef6SThomas Petazzoni #endif 409c5aff182SThomas Petazzoni 410c5aff182SThomas Petazzoni struct mvneta_tx_queue { 411c5aff182SThomas Petazzoni /* Number of this TX queue, in the range 0-7 */ 412c5aff182SThomas Petazzoni u8 id; 413c5aff182SThomas Petazzoni 414c5aff182SThomas Petazzoni /* Number of TX DMA descriptors in the descriptor ring */ 415c5aff182SThomas Petazzoni int size; 416c5aff182SThomas Petazzoni 417c5aff182SThomas Petazzoni /* Number of currently used TX DMA descriptor in the 4186a20c175SThomas Petazzoni * descriptor ring 4196a20c175SThomas Petazzoni */ 420c5aff182SThomas Petazzoni int count; 4218eef5f97SEzequiel Garcia int tx_stop_threshold; 4228eef5f97SEzequiel Garcia int tx_wake_threshold; 423c5aff182SThomas Petazzoni 424c5aff182SThomas Petazzoni /* Array of transmitted skb */ 425c5aff182SThomas Petazzoni struct sk_buff **tx_skb; 426c5aff182SThomas Petazzoni 427c5aff182SThomas Petazzoni /* Index of last TX DMA descriptor that was inserted */ 428c5aff182SThomas Petazzoni int txq_put_index; 429c5aff182SThomas Petazzoni 430c5aff182SThomas Petazzoni /* Index of the TX DMA descriptor to be cleaned up */ 431c5aff182SThomas Petazzoni int txq_get_index; 432c5aff182SThomas Petazzoni 433c5aff182SThomas Petazzoni u32 done_pkts_coal; 434c5aff182SThomas Petazzoni 435c5aff182SThomas Petazzoni /* Virtual address of the TX DMA descriptors array */ 436c5aff182SThomas Petazzoni struct mvneta_tx_desc *descs; 437c5aff182SThomas Petazzoni 438c5aff182SThomas Petazzoni /* DMA address of the TX DMA descriptors array */ 439c5aff182SThomas Petazzoni dma_addr_t descs_phys; 440c5aff182SThomas Petazzoni 441c5aff182SThomas Petazzoni /* Index of the last TX DMA descriptor */ 442c5aff182SThomas Petazzoni int last_desc; 443c5aff182SThomas Petazzoni 444c5aff182SThomas Petazzoni /* Index of the next TX DMA descriptor to process */ 445c5aff182SThomas Petazzoni int next_desc_to_proc; 4462adb719dSEzequiel Garcia 4472adb719dSEzequiel Garcia /* DMA buffers for TSO headers */ 4482adb719dSEzequiel Garcia char *tso_hdrs; 4492adb719dSEzequiel Garcia 4502adb719dSEzequiel Garcia /* DMA address of TSO headers */ 4512adb719dSEzequiel Garcia dma_addr_t tso_hdrs_phys; 452c5aff182SThomas Petazzoni }; 453c5aff182SThomas Petazzoni 454c5aff182SThomas Petazzoni struct mvneta_rx_queue { 455c5aff182SThomas Petazzoni /* rx queue number, in the range 0-7 */ 456c5aff182SThomas Petazzoni u8 id; 457c5aff182SThomas Petazzoni 458c5aff182SThomas Petazzoni /* num of rx descriptors in the rx descriptor ring */ 459c5aff182SThomas Petazzoni int size; 460c5aff182SThomas Petazzoni 461c5aff182SThomas Petazzoni /* counter of times when mvneta_refill() failed */ 462c5aff182SThomas Petazzoni int missed; 463c5aff182SThomas Petazzoni 464c5aff182SThomas Petazzoni u32 pkts_coal; 465c5aff182SThomas Petazzoni u32 time_coal; 466c5aff182SThomas Petazzoni 467c5aff182SThomas Petazzoni /* Virtual address of the RX DMA descriptors array */ 468c5aff182SThomas Petazzoni struct mvneta_rx_desc *descs; 469c5aff182SThomas Petazzoni 470c5aff182SThomas Petazzoni /* DMA address of the RX DMA descriptors array */ 471c5aff182SThomas Petazzoni dma_addr_t descs_phys; 472c5aff182SThomas Petazzoni 473c5aff182SThomas Petazzoni /* Index of the last RX DMA descriptor */ 474c5aff182SThomas Petazzoni int last_desc; 475c5aff182SThomas Petazzoni 476c5aff182SThomas Petazzoni /* Index of the next RX DMA descriptor to process */ 477c5aff182SThomas Petazzoni int next_desc_to_proc; 478c5aff182SThomas Petazzoni }; 479c5aff182SThomas Petazzoni 480edadb7faSEzequiel Garcia /* The hardware supports eight (8) rx queues, but we are only allowing 481edadb7faSEzequiel Garcia * the first one to be used. Therefore, let's just allocate one queue. 482edadb7faSEzequiel Garcia */ 483d8936657SMaxime Ripard static int rxq_number = 8; 484c5aff182SThomas Petazzoni static int txq_number = 8; 485c5aff182SThomas Petazzoni 486c5aff182SThomas Petazzoni static int rxq_def; 487c5aff182SThomas Petazzoni 488f19fadfcSwilly tarreau static int rx_copybreak __read_mostly = 256; 489f19fadfcSwilly tarreau 490c5aff182SThomas Petazzoni #define MVNETA_DRIVER_NAME "mvneta" 491c5aff182SThomas Petazzoni #define MVNETA_DRIVER_VERSION "1.0" 492c5aff182SThomas Petazzoni 493c5aff182SThomas Petazzoni /* Utility/helper methods */ 494c5aff182SThomas Petazzoni 495c5aff182SThomas Petazzoni /* Write helper method */ 496c5aff182SThomas Petazzoni static void mvreg_write(struct mvneta_port *pp, u32 offset, u32 data) 497c5aff182SThomas Petazzoni { 498c5aff182SThomas Petazzoni writel(data, pp->base + offset); 499c5aff182SThomas Petazzoni } 500c5aff182SThomas Petazzoni 501c5aff182SThomas Petazzoni /* Read helper method */ 502c5aff182SThomas Petazzoni static u32 mvreg_read(struct mvneta_port *pp, u32 offset) 503c5aff182SThomas Petazzoni { 504c5aff182SThomas Petazzoni return readl(pp->base + offset); 505c5aff182SThomas Petazzoni } 506c5aff182SThomas Petazzoni 507c5aff182SThomas Petazzoni /* Increment txq get counter */ 508c5aff182SThomas Petazzoni static void mvneta_txq_inc_get(struct mvneta_tx_queue *txq) 509c5aff182SThomas Petazzoni { 510c5aff182SThomas Petazzoni txq->txq_get_index++; 511c5aff182SThomas Petazzoni if (txq->txq_get_index == txq->size) 512c5aff182SThomas Petazzoni txq->txq_get_index = 0; 513c5aff182SThomas Petazzoni } 514c5aff182SThomas Petazzoni 515c5aff182SThomas Petazzoni /* Increment txq put counter */ 516c5aff182SThomas Petazzoni static void mvneta_txq_inc_put(struct mvneta_tx_queue *txq) 517c5aff182SThomas Petazzoni { 518c5aff182SThomas Petazzoni txq->txq_put_index++; 519c5aff182SThomas Petazzoni if (txq->txq_put_index == txq->size) 520c5aff182SThomas Petazzoni txq->txq_put_index = 0; 521c5aff182SThomas Petazzoni } 522c5aff182SThomas Petazzoni 523c5aff182SThomas Petazzoni 524c5aff182SThomas Petazzoni /* Clear all MIB counters */ 525c5aff182SThomas Petazzoni static void mvneta_mib_counters_clear(struct mvneta_port *pp) 526c5aff182SThomas Petazzoni { 527c5aff182SThomas Petazzoni int i; 528c5aff182SThomas Petazzoni u32 dummy; 529c5aff182SThomas Petazzoni 530c5aff182SThomas Petazzoni /* Perform dummy reads from MIB counters */ 531c5aff182SThomas Petazzoni for (i = 0; i < MVNETA_MIB_LATE_COLLISION; i += 4) 532c5aff182SThomas Petazzoni dummy = mvreg_read(pp, (MVNETA_MIB_COUNTERS_BASE + i)); 533c5aff182SThomas Petazzoni } 534c5aff182SThomas Petazzoni 535c5aff182SThomas Petazzoni /* Get System Network Statistics */ 536c5aff182SThomas Petazzoni struct rtnl_link_stats64 *mvneta_get_stats64(struct net_device *dev, 537c5aff182SThomas Petazzoni struct rtnl_link_stats64 *stats) 538c5aff182SThomas Petazzoni { 539c5aff182SThomas Petazzoni struct mvneta_port *pp = netdev_priv(dev); 540c5aff182SThomas Petazzoni unsigned int start; 54174c41b04Swilly tarreau int cpu; 542c5aff182SThomas Petazzoni 54374c41b04Swilly tarreau for_each_possible_cpu(cpu) { 54474c41b04Swilly tarreau struct mvneta_pcpu_stats *cpu_stats; 54574c41b04Swilly tarreau u64 rx_packets; 54674c41b04Swilly tarreau u64 rx_bytes; 54774c41b04Swilly tarreau u64 tx_packets; 54874c41b04Swilly tarreau u64 tx_bytes; 549c5aff182SThomas Petazzoni 55074c41b04Swilly tarreau cpu_stats = per_cpu_ptr(pp->stats, cpu); 551c5aff182SThomas Petazzoni do { 55257a7744eSEric W. Biederman start = u64_stats_fetch_begin_irq(&cpu_stats->syncp); 55374c41b04Swilly tarreau rx_packets = cpu_stats->rx_packets; 55474c41b04Swilly tarreau rx_bytes = cpu_stats->rx_bytes; 55574c41b04Swilly tarreau tx_packets = cpu_stats->tx_packets; 55674c41b04Swilly tarreau tx_bytes = cpu_stats->tx_bytes; 55757a7744eSEric W. Biederman } while (u64_stats_fetch_retry_irq(&cpu_stats->syncp, start)); 558c5aff182SThomas Petazzoni 55974c41b04Swilly tarreau stats->rx_packets += rx_packets; 56074c41b04Swilly tarreau stats->rx_bytes += rx_bytes; 56174c41b04Swilly tarreau stats->tx_packets += tx_packets; 56274c41b04Swilly tarreau stats->tx_bytes += tx_bytes; 56374c41b04Swilly tarreau } 564c5aff182SThomas Petazzoni 565c5aff182SThomas Petazzoni stats->rx_errors = dev->stats.rx_errors; 566c5aff182SThomas Petazzoni stats->rx_dropped = dev->stats.rx_dropped; 567c5aff182SThomas Petazzoni 568c5aff182SThomas Petazzoni stats->tx_dropped = dev->stats.tx_dropped; 569c5aff182SThomas Petazzoni 570c5aff182SThomas Petazzoni return stats; 571c5aff182SThomas Petazzoni } 572c5aff182SThomas Petazzoni 573c5aff182SThomas Petazzoni /* Rx descriptors helper methods */ 574c5aff182SThomas Petazzoni 5755428213cSwilly tarreau /* Checks whether the RX descriptor having this status is both the first 5765428213cSwilly tarreau * and the last descriptor for the RX packet. Each RX packet is currently 577c5aff182SThomas Petazzoni * received through a single RX descriptor, so not having each RX 578c5aff182SThomas Petazzoni * descriptor with its first and last bits set is an error 579c5aff182SThomas Petazzoni */ 5805428213cSwilly tarreau static int mvneta_rxq_desc_is_first_last(u32 status) 581c5aff182SThomas Petazzoni { 5825428213cSwilly tarreau return (status & MVNETA_RXD_FIRST_LAST_DESC) == 583c5aff182SThomas Petazzoni MVNETA_RXD_FIRST_LAST_DESC; 584c5aff182SThomas Petazzoni } 585c5aff182SThomas Petazzoni 586c5aff182SThomas Petazzoni /* Add number of descriptors ready to receive new packets */ 587c5aff182SThomas Petazzoni static void mvneta_rxq_non_occup_desc_add(struct mvneta_port *pp, 588c5aff182SThomas Petazzoni struct mvneta_rx_queue *rxq, 589c5aff182SThomas Petazzoni int ndescs) 590c5aff182SThomas Petazzoni { 591c5aff182SThomas Petazzoni /* Only MVNETA_RXQ_ADD_NON_OCCUPIED_MAX (255) descriptors can 5926a20c175SThomas Petazzoni * be added at once 5936a20c175SThomas Petazzoni */ 594c5aff182SThomas Petazzoni while (ndescs > MVNETA_RXQ_ADD_NON_OCCUPIED_MAX) { 595c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id), 596c5aff182SThomas Petazzoni (MVNETA_RXQ_ADD_NON_OCCUPIED_MAX << 597c5aff182SThomas Petazzoni MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT)); 598c5aff182SThomas Petazzoni ndescs -= MVNETA_RXQ_ADD_NON_OCCUPIED_MAX; 599c5aff182SThomas Petazzoni } 600c5aff182SThomas Petazzoni 601c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id), 602c5aff182SThomas Petazzoni (ndescs << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT)); 603c5aff182SThomas Petazzoni } 604c5aff182SThomas Petazzoni 605c5aff182SThomas Petazzoni /* Get number of RX descriptors occupied by received packets */ 606c5aff182SThomas Petazzoni static int mvneta_rxq_busy_desc_num_get(struct mvneta_port *pp, 607c5aff182SThomas Petazzoni struct mvneta_rx_queue *rxq) 608c5aff182SThomas Petazzoni { 609c5aff182SThomas Petazzoni u32 val; 610c5aff182SThomas Petazzoni 611c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_RXQ_STATUS_REG(rxq->id)); 612c5aff182SThomas Petazzoni return val & MVNETA_RXQ_OCCUPIED_ALL_MASK; 613c5aff182SThomas Petazzoni } 614c5aff182SThomas Petazzoni 6156a20c175SThomas Petazzoni /* Update num of rx desc called upon return from rx path or 616c5aff182SThomas Petazzoni * from mvneta_rxq_drop_pkts(). 617c5aff182SThomas Petazzoni */ 618c5aff182SThomas Petazzoni static void mvneta_rxq_desc_num_update(struct mvneta_port *pp, 619c5aff182SThomas Petazzoni struct mvneta_rx_queue *rxq, 620c5aff182SThomas Petazzoni int rx_done, int rx_filled) 621c5aff182SThomas Petazzoni { 622c5aff182SThomas Petazzoni u32 val; 623c5aff182SThomas Petazzoni 624c5aff182SThomas Petazzoni if ((rx_done <= 0xff) && (rx_filled <= 0xff)) { 625c5aff182SThomas Petazzoni val = rx_done | 626c5aff182SThomas Petazzoni (rx_filled << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT); 627c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id), val); 628c5aff182SThomas Petazzoni return; 629c5aff182SThomas Petazzoni } 630c5aff182SThomas Petazzoni 631c5aff182SThomas Petazzoni /* Only 255 descriptors can be added at once */ 632c5aff182SThomas Petazzoni while ((rx_done > 0) || (rx_filled > 0)) { 633c5aff182SThomas Petazzoni if (rx_done <= 0xff) { 634c5aff182SThomas Petazzoni val = rx_done; 635c5aff182SThomas Petazzoni rx_done = 0; 636c5aff182SThomas Petazzoni } else { 637c5aff182SThomas Petazzoni val = 0xff; 638c5aff182SThomas Petazzoni rx_done -= 0xff; 639c5aff182SThomas Petazzoni } 640c5aff182SThomas Petazzoni if (rx_filled <= 0xff) { 641c5aff182SThomas Petazzoni val |= rx_filled << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT; 642c5aff182SThomas Petazzoni rx_filled = 0; 643c5aff182SThomas Petazzoni } else { 644c5aff182SThomas Petazzoni val |= 0xff << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT; 645c5aff182SThomas Petazzoni rx_filled -= 0xff; 646c5aff182SThomas Petazzoni } 647c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id), val); 648c5aff182SThomas Petazzoni } 649c5aff182SThomas Petazzoni } 650c5aff182SThomas Petazzoni 651c5aff182SThomas Petazzoni /* Get pointer to next RX descriptor to be processed by SW */ 652c5aff182SThomas Petazzoni static struct mvneta_rx_desc * 653c5aff182SThomas Petazzoni mvneta_rxq_next_desc_get(struct mvneta_rx_queue *rxq) 654c5aff182SThomas Petazzoni { 655c5aff182SThomas Petazzoni int rx_desc = rxq->next_desc_to_proc; 656c5aff182SThomas Petazzoni 657c5aff182SThomas Petazzoni rxq->next_desc_to_proc = MVNETA_QUEUE_NEXT_DESC(rxq, rx_desc); 65834e4179dSwilly tarreau prefetch(rxq->descs + rxq->next_desc_to_proc); 659c5aff182SThomas Petazzoni return rxq->descs + rx_desc; 660c5aff182SThomas Petazzoni } 661c5aff182SThomas Petazzoni 662c5aff182SThomas Petazzoni /* Change maximum receive size of the port. */ 663c5aff182SThomas Petazzoni static void mvneta_max_rx_size_set(struct mvneta_port *pp, int max_rx_size) 664c5aff182SThomas Petazzoni { 665c5aff182SThomas Petazzoni u32 val; 666c5aff182SThomas Petazzoni 667c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_GMAC_CTRL_0); 668c5aff182SThomas Petazzoni val &= ~MVNETA_GMAC_MAX_RX_SIZE_MASK; 669c5aff182SThomas Petazzoni val |= ((max_rx_size - MVNETA_MH_SIZE) / 2) << 670c5aff182SThomas Petazzoni MVNETA_GMAC_MAX_RX_SIZE_SHIFT; 671c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_GMAC_CTRL_0, val); 672c5aff182SThomas Petazzoni } 673c5aff182SThomas Petazzoni 674c5aff182SThomas Petazzoni 675c5aff182SThomas Petazzoni /* Set rx queue offset */ 676c5aff182SThomas Petazzoni static void mvneta_rxq_offset_set(struct mvneta_port *pp, 677c5aff182SThomas Petazzoni struct mvneta_rx_queue *rxq, 678c5aff182SThomas Petazzoni int offset) 679c5aff182SThomas Petazzoni { 680c5aff182SThomas Petazzoni u32 val; 681c5aff182SThomas Petazzoni 682c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_RXQ_CONFIG_REG(rxq->id)); 683c5aff182SThomas Petazzoni val &= ~MVNETA_RXQ_PKT_OFFSET_ALL_MASK; 684c5aff182SThomas Petazzoni 685c5aff182SThomas Petazzoni /* Offset is in */ 686c5aff182SThomas Petazzoni val |= MVNETA_RXQ_PKT_OFFSET_MASK(offset >> 3); 687c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_RXQ_CONFIG_REG(rxq->id), val); 688c5aff182SThomas Petazzoni } 689c5aff182SThomas Petazzoni 690c5aff182SThomas Petazzoni 691c5aff182SThomas Petazzoni /* Tx descriptors helper methods */ 692c5aff182SThomas Petazzoni 693c5aff182SThomas Petazzoni /* Update HW with number of TX descriptors to be sent */ 694c5aff182SThomas Petazzoni static void mvneta_txq_pend_desc_add(struct mvneta_port *pp, 695c5aff182SThomas Petazzoni struct mvneta_tx_queue *txq, 696c5aff182SThomas Petazzoni int pend_desc) 697c5aff182SThomas Petazzoni { 698c5aff182SThomas Petazzoni u32 val; 699c5aff182SThomas Petazzoni 700c5aff182SThomas Petazzoni /* Only 255 descriptors can be added at once ; Assume caller 7016a20c175SThomas Petazzoni * process TX desriptors in quanta less than 256 7026a20c175SThomas Petazzoni */ 703c5aff182SThomas Petazzoni val = pend_desc; 704c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val); 705c5aff182SThomas Petazzoni } 706c5aff182SThomas Petazzoni 707c5aff182SThomas Petazzoni /* Get pointer to next TX descriptor to be processed (send) by HW */ 708c5aff182SThomas Petazzoni static struct mvneta_tx_desc * 709c5aff182SThomas Petazzoni mvneta_txq_next_desc_get(struct mvneta_tx_queue *txq) 710c5aff182SThomas Petazzoni { 711c5aff182SThomas Petazzoni int tx_desc = txq->next_desc_to_proc; 712c5aff182SThomas Petazzoni 713c5aff182SThomas Petazzoni txq->next_desc_to_proc = MVNETA_QUEUE_NEXT_DESC(txq, tx_desc); 714c5aff182SThomas Petazzoni return txq->descs + tx_desc; 715c5aff182SThomas Petazzoni } 716c5aff182SThomas Petazzoni 717c5aff182SThomas Petazzoni /* Release the last allocated TX descriptor. Useful to handle DMA 7186a20c175SThomas Petazzoni * mapping failures in the TX path. 7196a20c175SThomas Petazzoni */ 720c5aff182SThomas Petazzoni static void mvneta_txq_desc_put(struct mvneta_tx_queue *txq) 721c5aff182SThomas Petazzoni { 722c5aff182SThomas Petazzoni if (txq->next_desc_to_proc == 0) 723c5aff182SThomas Petazzoni txq->next_desc_to_proc = txq->last_desc - 1; 724c5aff182SThomas Petazzoni else 725c5aff182SThomas Petazzoni txq->next_desc_to_proc--; 726c5aff182SThomas Petazzoni } 727c5aff182SThomas Petazzoni 728c5aff182SThomas Petazzoni /* Set rxq buf size */ 729c5aff182SThomas Petazzoni static void mvneta_rxq_buf_size_set(struct mvneta_port *pp, 730c5aff182SThomas Petazzoni struct mvneta_rx_queue *rxq, 731c5aff182SThomas Petazzoni int buf_size) 732c5aff182SThomas Petazzoni { 733c5aff182SThomas Petazzoni u32 val; 734c5aff182SThomas Petazzoni 735c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_RXQ_SIZE_REG(rxq->id)); 736c5aff182SThomas Petazzoni 737c5aff182SThomas Petazzoni val &= ~MVNETA_RXQ_BUF_SIZE_MASK; 738c5aff182SThomas Petazzoni val |= ((buf_size >> 3) << MVNETA_RXQ_BUF_SIZE_SHIFT); 739c5aff182SThomas Petazzoni 740c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_RXQ_SIZE_REG(rxq->id), val); 741c5aff182SThomas Petazzoni } 742c5aff182SThomas Petazzoni 743c5aff182SThomas Petazzoni /* Disable buffer management (BM) */ 744c5aff182SThomas Petazzoni static void mvneta_rxq_bm_disable(struct mvneta_port *pp, 745c5aff182SThomas Petazzoni struct mvneta_rx_queue *rxq) 746c5aff182SThomas Petazzoni { 747c5aff182SThomas Petazzoni u32 val; 748c5aff182SThomas Petazzoni 749c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_RXQ_CONFIG_REG(rxq->id)); 750c5aff182SThomas Petazzoni val &= ~MVNETA_RXQ_HW_BUF_ALLOC; 751c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_RXQ_CONFIG_REG(rxq->id), val); 752c5aff182SThomas Petazzoni } 753c5aff182SThomas Petazzoni 754c5aff182SThomas Petazzoni /* Start the Ethernet port RX and TX activity */ 755c5aff182SThomas Petazzoni static void mvneta_port_up(struct mvneta_port *pp) 756c5aff182SThomas Petazzoni { 757c5aff182SThomas Petazzoni int queue; 758c5aff182SThomas Petazzoni u32 q_map; 759c5aff182SThomas Petazzoni 760c5aff182SThomas Petazzoni /* Enable all initialized TXs. */ 761c5aff182SThomas Petazzoni mvneta_mib_counters_clear(pp); 762c5aff182SThomas Petazzoni q_map = 0; 763c5aff182SThomas Petazzoni for (queue = 0; queue < txq_number; queue++) { 764c5aff182SThomas Petazzoni struct mvneta_tx_queue *txq = &pp->txqs[queue]; 765c5aff182SThomas Petazzoni if (txq->descs != NULL) 766c5aff182SThomas Petazzoni q_map |= (1 << queue); 767c5aff182SThomas Petazzoni } 768c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_TXQ_CMD, q_map); 769c5aff182SThomas Petazzoni 770c5aff182SThomas Petazzoni /* Enable all initialized RXQs. */ 771d8936657SMaxime Ripard mvreg_write(pp, MVNETA_RXQ_CMD, BIT(rxq_def)); 772c5aff182SThomas Petazzoni } 773c5aff182SThomas Petazzoni 774c5aff182SThomas Petazzoni /* Stop the Ethernet port activity */ 775c5aff182SThomas Petazzoni static void mvneta_port_down(struct mvneta_port *pp) 776c5aff182SThomas Petazzoni { 777c5aff182SThomas Petazzoni u32 val; 778c5aff182SThomas Petazzoni int count; 779c5aff182SThomas Petazzoni 780c5aff182SThomas Petazzoni /* Stop Rx port activity. Check port Rx activity. */ 781c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_RXQ_CMD) & MVNETA_RXQ_ENABLE_MASK; 782c5aff182SThomas Petazzoni 783c5aff182SThomas Petazzoni /* Issue stop command for active channels only */ 784c5aff182SThomas Petazzoni if (val != 0) 785c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_RXQ_CMD, 786c5aff182SThomas Petazzoni val << MVNETA_RXQ_DISABLE_SHIFT); 787c5aff182SThomas Petazzoni 788c5aff182SThomas Petazzoni /* Wait for all Rx activity to terminate. */ 789c5aff182SThomas Petazzoni count = 0; 790c5aff182SThomas Petazzoni do { 791c5aff182SThomas Petazzoni if (count++ >= MVNETA_RX_DISABLE_TIMEOUT_MSEC) { 792c5aff182SThomas Petazzoni netdev_warn(pp->dev, 793c5aff182SThomas Petazzoni "TIMEOUT for RX stopped ! rx_queue_cmd: 0x08%x\n", 794c5aff182SThomas Petazzoni val); 795c5aff182SThomas Petazzoni break; 796c5aff182SThomas Petazzoni } 797c5aff182SThomas Petazzoni mdelay(1); 798c5aff182SThomas Petazzoni 799c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_RXQ_CMD); 800c5aff182SThomas Petazzoni } while (val & 0xff); 801c5aff182SThomas Petazzoni 802c5aff182SThomas Petazzoni /* Stop Tx port activity. Check port Tx activity. Issue stop 8036a20c175SThomas Petazzoni * command for active channels only 8046a20c175SThomas Petazzoni */ 805c5aff182SThomas Petazzoni val = (mvreg_read(pp, MVNETA_TXQ_CMD)) & MVNETA_TXQ_ENABLE_MASK; 806c5aff182SThomas Petazzoni 807c5aff182SThomas Petazzoni if (val != 0) 808c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_TXQ_CMD, 809c5aff182SThomas Petazzoni (val << MVNETA_TXQ_DISABLE_SHIFT)); 810c5aff182SThomas Petazzoni 811c5aff182SThomas Petazzoni /* Wait for all Tx activity to terminate. */ 812c5aff182SThomas Petazzoni count = 0; 813c5aff182SThomas Petazzoni do { 814c5aff182SThomas Petazzoni if (count++ >= MVNETA_TX_DISABLE_TIMEOUT_MSEC) { 815c5aff182SThomas Petazzoni netdev_warn(pp->dev, 816c5aff182SThomas Petazzoni "TIMEOUT for TX stopped status=0x%08x\n", 817c5aff182SThomas Petazzoni val); 818c5aff182SThomas Petazzoni break; 819c5aff182SThomas Petazzoni } 820c5aff182SThomas Petazzoni mdelay(1); 821c5aff182SThomas Petazzoni 822c5aff182SThomas Petazzoni /* Check TX Command reg that all Txqs are stopped */ 823c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_TXQ_CMD); 824c5aff182SThomas Petazzoni 825c5aff182SThomas Petazzoni } while (val & 0xff); 826c5aff182SThomas Petazzoni 827c5aff182SThomas Petazzoni /* Double check to verify that TX FIFO is empty */ 828c5aff182SThomas Petazzoni count = 0; 829c5aff182SThomas Petazzoni do { 830c5aff182SThomas Petazzoni if (count++ >= MVNETA_TX_FIFO_EMPTY_TIMEOUT) { 831c5aff182SThomas Petazzoni netdev_warn(pp->dev, 832c5aff182SThomas Petazzoni "TX FIFO empty timeout status=0x08%x\n", 833c5aff182SThomas Petazzoni val); 834c5aff182SThomas Petazzoni break; 835c5aff182SThomas Petazzoni } 836c5aff182SThomas Petazzoni mdelay(1); 837c5aff182SThomas Petazzoni 838c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_PORT_STATUS); 839c5aff182SThomas Petazzoni } while (!(val & MVNETA_TX_FIFO_EMPTY) && 840c5aff182SThomas Petazzoni (val & MVNETA_TX_IN_PRGRS)); 841c5aff182SThomas Petazzoni 842c5aff182SThomas Petazzoni udelay(200); 843c5aff182SThomas Petazzoni } 844c5aff182SThomas Petazzoni 845c5aff182SThomas Petazzoni /* Enable the port by setting the port enable bit of the MAC control register */ 846c5aff182SThomas Petazzoni static void mvneta_port_enable(struct mvneta_port *pp) 847c5aff182SThomas Petazzoni { 848c5aff182SThomas Petazzoni u32 val; 849c5aff182SThomas Petazzoni 850c5aff182SThomas Petazzoni /* Enable port */ 851c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_GMAC_CTRL_0); 852c5aff182SThomas Petazzoni val |= MVNETA_GMAC0_PORT_ENABLE; 853c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_GMAC_CTRL_0, val); 854c5aff182SThomas Petazzoni } 855c5aff182SThomas Petazzoni 856c5aff182SThomas Petazzoni /* Disable the port and wait for about 200 usec before retuning */ 857c5aff182SThomas Petazzoni static void mvneta_port_disable(struct mvneta_port *pp) 858c5aff182SThomas Petazzoni { 859c5aff182SThomas Petazzoni u32 val; 860c5aff182SThomas Petazzoni 861c5aff182SThomas Petazzoni /* Reset the Enable bit in the Serial Control Register */ 862c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_GMAC_CTRL_0); 863c5aff182SThomas Petazzoni val &= ~MVNETA_GMAC0_PORT_ENABLE; 864c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_GMAC_CTRL_0, val); 865c5aff182SThomas Petazzoni 866c5aff182SThomas Petazzoni udelay(200); 867c5aff182SThomas Petazzoni } 868c5aff182SThomas Petazzoni 869c5aff182SThomas Petazzoni /* Multicast tables methods */ 870c5aff182SThomas Petazzoni 871c5aff182SThomas Petazzoni /* Set all entries in Unicast MAC Table; queue==-1 means reject all */ 872c5aff182SThomas Petazzoni static void mvneta_set_ucast_table(struct mvneta_port *pp, int queue) 873c5aff182SThomas Petazzoni { 874c5aff182SThomas Petazzoni int offset; 875c5aff182SThomas Petazzoni u32 val; 876c5aff182SThomas Petazzoni 877c5aff182SThomas Petazzoni if (queue == -1) { 878c5aff182SThomas Petazzoni val = 0; 879c5aff182SThomas Petazzoni } else { 880c5aff182SThomas Petazzoni val = 0x1 | (queue << 1); 881c5aff182SThomas Petazzoni val |= (val << 24) | (val << 16) | (val << 8); 882c5aff182SThomas Petazzoni } 883c5aff182SThomas Petazzoni 884c5aff182SThomas Petazzoni for (offset = 0; offset <= 0xc; offset += 4) 885c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_DA_FILT_UCAST_BASE + offset, val); 886c5aff182SThomas Petazzoni } 887c5aff182SThomas Petazzoni 888c5aff182SThomas Petazzoni /* Set all entries in Special Multicast MAC Table; queue==-1 means reject all */ 889c5aff182SThomas Petazzoni static void mvneta_set_special_mcast_table(struct mvneta_port *pp, int queue) 890c5aff182SThomas Petazzoni { 891c5aff182SThomas Petazzoni int offset; 892c5aff182SThomas Petazzoni u32 val; 893c5aff182SThomas Petazzoni 894c5aff182SThomas Petazzoni if (queue == -1) { 895c5aff182SThomas Petazzoni val = 0; 896c5aff182SThomas Petazzoni } else { 897c5aff182SThomas Petazzoni val = 0x1 | (queue << 1); 898c5aff182SThomas Petazzoni val |= (val << 24) | (val << 16) | (val << 8); 899c5aff182SThomas Petazzoni } 900c5aff182SThomas Petazzoni 901c5aff182SThomas Petazzoni for (offset = 0; offset <= 0xfc; offset += 4) 902c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_DA_FILT_SPEC_MCAST + offset, val); 903c5aff182SThomas Petazzoni 904c5aff182SThomas Petazzoni } 905c5aff182SThomas Petazzoni 906c5aff182SThomas Petazzoni /* Set all entries in Other Multicast MAC Table. queue==-1 means reject all */ 907c5aff182SThomas Petazzoni static void mvneta_set_other_mcast_table(struct mvneta_port *pp, int queue) 908c5aff182SThomas Petazzoni { 909c5aff182SThomas Petazzoni int offset; 910c5aff182SThomas Petazzoni u32 val; 911c5aff182SThomas Petazzoni 912c5aff182SThomas Petazzoni if (queue == -1) { 913c5aff182SThomas Petazzoni memset(pp->mcast_count, 0, sizeof(pp->mcast_count)); 914c5aff182SThomas Petazzoni val = 0; 915c5aff182SThomas Petazzoni } else { 916c5aff182SThomas Petazzoni memset(pp->mcast_count, 1, sizeof(pp->mcast_count)); 917c5aff182SThomas Petazzoni val = 0x1 | (queue << 1); 918c5aff182SThomas Petazzoni val |= (val << 24) | (val << 16) | (val << 8); 919c5aff182SThomas Petazzoni } 920c5aff182SThomas Petazzoni 921c5aff182SThomas Petazzoni for (offset = 0; offset <= 0xfc; offset += 4) 922c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_DA_FILT_OTH_MCAST + offset, val); 923c5aff182SThomas Petazzoni } 924c5aff182SThomas Petazzoni 925c5aff182SThomas Petazzoni /* This method sets defaults to the NETA port: 926c5aff182SThomas Petazzoni * Clears interrupt Cause and Mask registers. 927c5aff182SThomas Petazzoni * Clears all MAC tables. 928c5aff182SThomas Petazzoni * Sets defaults to all registers. 929c5aff182SThomas Petazzoni * Resets RX and TX descriptor rings. 930c5aff182SThomas Petazzoni * Resets PHY. 931c5aff182SThomas Petazzoni * This method can be called after mvneta_port_down() to return the port 932c5aff182SThomas Petazzoni * settings to defaults. 933c5aff182SThomas Petazzoni */ 934c5aff182SThomas Petazzoni static void mvneta_defaults_set(struct mvneta_port *pp) 935c5aff182SThomas Petazzoni { 936c5aff182SThomas Petazzoni int cpu; 937c5aff182SThomas Petazzoni int queue; 938c5aff182SThomas Petazzoni u32 val; 939c5aff182SThomas Petazzoni 940c5aff182SThomas Petazzoni /* Clear all Cause registers */ 941c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_INTR_NEW_CAUSE, 0); 942c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_INTR_OLD_CAUSE, 0); 943c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_INTR_MISC_CAUSE, 0); 944c5aff182SThomas Petazzoni 945c5aff182SThomas Petazzoni /* Mask all interrupts */ 946c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_INTR_NEW_MASK, 0); 947c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_INTR_OLD_MASK, 0); 948c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_INTR_MISC_MASK, 0); 949c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_INTR_ENABLE, 0); 950c5aff182SThomas Petazzoni 951c5aff182SThomas Petazzoni /* Enable MBUS Retry bit16 */ 952c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_MBUS_RETRY, 0x20); 953c5aff182SThomas Petazzoni 954c5aff182SThomas Petazzoni /* Set CPU queue access map - all CPUs have access to all RX 9556a20c175SThomas Petazzoni * queues and to all TX queues 9566a20c175SThomas Petazzoni */ 9572502d0efSMaxime Ripard for_each_present_cpu(cpu) 958c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_CPU_MAP(cpu), 959c5aff182SThomas Petazzoni (MVNETA_CPU_RXQ_ACCESS_ALL_MASK | 960c5aff182SThomas Petazzoni MVNETA_CPU_TXQ_ACCESS_ALL_MASK)); 961c5aff182SThomas Petazzoni 962c5aff182SThomas Petazzoni /* Reset RX and TX DMAs */ 963c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_PORT_RX_RESET, MVNETA_PORT_RX_DMA_RESET); 964c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_PORT_TX_RESET, MVNETA_PORT_TX_DMA_RESET); 965c5aff182SThomas Petazzoni 966c5aff182SThomas Petazzoni /* Disable Legacy WRR, Disable EJP, Release from reset */ 967c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_TXQ_CMD_1, 0); 968c5aff182SThomas Petazzoni for (queue = 0; queue < txq_number; queue++) { 969c5aff182SThomas Petazzoni mvreg_write(pp, MVETH_TXQ_TOKEN_COUNT_REG(queue), 0); 970c5aff182SThomas Petazzoni mvreg_write(pp, MVETH_TXQ_TOKEN_CFG_REG(queue), 0); 971c5aff182SThomas Petazzoni } 972c5aff182SThomas Petazzoni 973c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_PORT_TX_RESET, 0); 974c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_PORT_RX_RESET, 0); 975c5aff182SThomas Petazzoni 976c5aff182SThomas Petazzoni /* Set Port Acceleration Mode */ 977c5aff182SThomas Petazzoni val = MVNETA_ACC_MODE_EXT; 978c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_ACC_MODE, val); 979c5aff182SThomas Petazzoni 980c5aff182SThomas Petazzoni /* Update val of portCfg register accordingly with all RxQueue types */ 981c5aff182SThomas Petazzoni val = MVNETA_PORT_CONFIG_DEFL_VALUE(rxq_def); 982c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_PORT_CONFIG, val); 983c5aff182SThomas Petazzoni 984c5aff182SThomas Petazzoni val = 0; 985c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_PORT_CONFIG_EXTEND, val); 986c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_RX_MIN_FRAME_SIZE, 64); 987c5aff182SThomas Petazzoni 988c5aff182SThomas Petazzoni /* Build PORT_SDMA_CONFIG_REG */ 989c5aff182SThomas Petazzoni val = 0; 990c5aff182SThomas Petazzoni 991c5aff182SThomas Petazzoni /* Default burst size */ 992c5aff182SThomas Petazzoni val |= MVNETA_TX_BRST_SZ_MASK(MVNETA_SDMA_BRST_SIZE_16); 993c5aff182SThomas Petazzoni val |= MVNETA_RX_BRST_SZ_MASK(MVNETA_SDMA_BRST_SIZE_16); 9949ad8fef6SThomas Petazzoni val |= MVNETA_RX_NO_DATA_SWAP | MVNETA_TX_NO_DATA_SWAP; 995c5aff182SThomas Petazzoni 9969ad8fef6SThomas Petazzoni #if defined(__BIG_ENDIAN) 9979ad8fef6SThomas Petazzoni val |= MVNETA_DESC_SWAP; 9989ad8fef6SThomas Petazzoni #endif 999c5aff182SThomas Petazzoni 1000c5aff182SThomas Petazzoni /* Assign port SDMA configuration */ 1001c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_SDMA_CONFIG, val); 1002c5aff182SThomas Petazzoni 100371408602SThomas Petazzoni /* Disable PHY polling in hardware, since we're using the 100471408602SThomas Petazzoni * kernel phylib to do this. 100571408602SThomas Petazzoni */ 100671408602SThomas Petazzoni val = mvreg_read(pp, MVNETA_UNIT_CONTROL); 100771408602SThomas Petazzoni val &= ~MVNETA_PHY_POLLING_ENABLE; 100871408602SThomas Petazzoni mvreg_write(pp, MVNETA_UNIT_CONTROL, val); 100971408602SThomas Petazzoni 1010898b2970SStas Sergeev if (pp->use_inband_status) { 1011898b2970SStas Sergeev val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG); 1012898b2970SStas Sergeev val &= ~(MVNETA_GMAC_FORCE_LINK_PASS | 1013898b2970SStas Sergeev MVNETA_GMAC_FORCE_LINK_DOWN | 1014898b2970SStas Sergeev MVNETA_GMAC_AN_FLOW_CTRL_EN); 1015898b2970SStas Sergeev val |= MVNETA_GMAC_INBAND_AN_ENABLE | 1016898b2970SStas Sergeev MVNETA_GMAC_AN_SPEED_EN | 1017898b2970SStas Sergeev MVNETA_GMAC_AN_DUPLEX_EN; 1018898b2970SStas Sergeev mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val); 1019898b2970SStas Sergeev val = mvreg_read(pp, MVNETA_GMAC_CLOCK_DIVIDER); 1020898b2970SStas Sergeev val |= MVNETA_GMAC_1MS_CLOCK_ENABLE; 1021898b2970SStas Sergeev mvreg_write(pp, MVNETA_GMAC_CLOCK_DIVIDER, val); 1022538761b7SStas Sergeev } else { 1023538761b7SStas Sergeev val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG); 1024538761b7SStas Sergeev val &= ~(MVNETA_GMAC_INBAND_AN_ENABLE | 1025538761b7SStas Sergeev MVNETA_GMAC_AN_SPEED_EN | 1026538761b7SStas Sergeev MVNETA_GMAC_AN_DUPLEX_EN); 1027538761b7SStas Sergeev mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val); 1028898b2970SStas Sergeev } 1029898b2970SStas Sergeev 1030c5aff182SThomas Petazzoni mvneta_set_ucast_table(pp, -1); 1031c5aff182SThomas Petazzoni mvneta_set_special_mcast_table(pp, -1); 1032c5aff182SThomas Petazzoni mvneta_set_other_mcast_table(pp, -1); 1033c5aff182SThomas Petazzoni 1034c5aff182SThomas Petazzoni /* Set port interrupt enable register - default enable all */ 1035c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_INTR_ENABLE, 1036c5aff182SThomas Petazzoni (MVNETA_RXQ_INTR_ENABLE_ALL_MASK 1037c5aff182SThomas Petazzoni | MVNETA_TXQ_INTR_ENABLE_ALL_MASK)); 1038c5aff182SThomas Petazzoni } 1039c5aff182SThomas Petazzoni 1040c5aff182SThomas Petazzoni /* Set max sizes for tx queues */ 1041c5aff182SThomas Petazzoni static void mvneta_txq_max_tx_size_set(struct mvneta_port *pp, int max_tx_size) 1042c5aff182SThomas Petazzoni 1043c5aff182SThomas Petazzoni { 1044c5aff182SThomas Petazzoni u32 val, size, mtu; 1045c5aff182SThomas Petazzoni int queue; 1046c5aff182SThomas Petazzoni 1047c5aff182SThomas Petazzoni mtu = max_tx_size * 8; 1048c5aff182SThomas Petazzoni if (mtu > MVNETA_TX_MTU_MAX) 1049c5aff182SThomas Petazzoni mtu = MVNETA_TX_MTU_MAX; 1050c5aff182SThomas Petazzoni 1051c5aff182SThomas Petazzoni /* Set MTU */ 1052c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_TX_MTU); 1053c5aff182SThomas Petazzoni val &= ~MVNETA_TX_MTU_MAX; 1054c5aff182SThomas Petazzoni val |= mtu; 1055c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_TX_MTU, val); 1056c5aff182SThomas Petazzoni 1057c5aff182SThomas Petazzoni /* TX token size and all TXQs token size must be larger that MTU */ 1058c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_TX_TOKEN_SIZE); 1059c5aff182SThomas Petazzoni 1060c5aff182SThomas Petazzoni size = val & MVNETA_TX_TOKEN_SIZE_MAX; 1061c5aff182SThomas Petazzoni if (size < mtu) { 1062c5aff182SThomas Petazzoni size = mtu; 1063c5aff182SThomas Petazzoni val &= ~MVNETA_TX_TOKEN_SIZE_MAX; 1064c5aff182SThomas Petazzoni val |= size; 1065c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_TX_TOKEN_SIZE, val); 1066c5aff182SThomas Petazzoni } 1067c5aff182SThomas Petazzoni for (queue = 0; queue < txq_number; queue++) { 1068c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_TXQ_TOKEN_SIZE_REG(queue)); 1069c5aff182SThomas Petazzoni 1070c5aff182SThomas Petazzoni size = val & MVNETA_TXQ_TOKEN_SIZE_MAX; 1071c5aff182SThomas Petazzoni if (size < mtu) { 1072c5aff182SThomas Petazzoni size = mtu; 1073c5aff182SThomas Petazzoni val &= ~MVNETA_TXQ_TOKEN_SIZE_MAX; 1074c5aff182SThomas Petazzoni val |= size; 1075c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_TXQ_TOKEN_SIZE_REG(queue), val); 1076c5aff182SThomas Petazzoni } 1077c5aff182SThomas Petazzoni } 1078c5aff182SThomas Petazzoni } 1079c5aff182SThomas Petazzoni 1080c5aff182SThomas Petazzoni /* Set unicast address */ 1081c5aff182SThomas Petazzoni static void mvneta_set_ucast_addr(struct mvneta_port *pp, u8 last_nibble, 1082c5aff182SThomas Petazzoni int queue) 1083c5aff182SThomas Petazzoni { 1084c5aff182SThomas Petazzoni unsigned int unicast_reg; 1085c5aff182SThomas Petazzoni unsigned int tbl_offset; 1086c5aff182SThomas Petazzoni unsigned int reg_offset; 1087c5aff182SThomas Petazzoni 1088c5aff182SThomas Petazzoni /* Locate the Unicast table entry */ 1089c5aff182SThomas Petazzoni last_nibble = (0xf & last_nibble); 1090c5aff182SThomas Petazzoni 1091c5aff182SThomas Petazzoni /* offset from unicast tbl base */ 1092c5aff182SThomas Petazzoni tbl_offset = (last_nibble / 4) * 4; 1093c5aff182SThomas Petazzoni 1094c5aff182SThomas Petazzoni /* offset within the above reg */ 1095c5aff182SThomas Petazzoni reg_offset = last_nibble % 4; 1096c5aff182SThomas Petazzoni 1097c5aff182SThomas Petazzoni unicast_reg = mvreg_read(pp, (MVNETA_DA_FILT_UCAST_BASE + tbl_offset)); 1098c5aff182SThomas Petazzoni 1099c5aff182SThomas Petazzoni if (queue == -1) { 1100c5aff182SThomas Petazzoni /* Clear accepts frame bit at specified unicast DA tbl entry */ 1101c5aff182SThomas Petazzoni unicast_reg &= ~(0xff << (8 * reg_offset)); 1102c5aff182SThomas Petazzoni } else { 1103c5aff182SThomas Petazzoni unicast_reg &= ~(0xff << (8 * reg_offset)); 1104c5aff182SThomas Petazzoni unicast_reg |= ((0x01 | (queue << 1)) << (8 * reg_offset)); 1105c5aff182SThomas Petazzoni } 1106c5aff182SThomas Petazzoni 1107c5aff182SThomas Petazzoni mvreg_write(pp, (MVNETA_DA_FILT_UCAST_BASE + tbl_offset), unicast_reg); 1108c5aff182SThomas Petazzoni } 1109c5aff182SThomas Petazzoni 1110c5aff182SThomas Petazzoni /* Set mac address */ 1111c5aff182SThomas Petazzoni static void mvneta_mac_addr_set(struct mvneta_port *pp, unsigned char *addr, 1112c5aff182SThomas Petazzoni int queue) 1113c5aff182SThomas Petazzoni { 1114c5aff182SThomas Petazzoni unsigned int mac_h; 1115c5aff182SThomas Petazzoni unsigned int mac_l; 1116c5aff182SThomas Petazzoni 1117c5aff182SThomas Petazzoni if (queue != -1) { 1118c5aff182SThomas Petazzoni mac_l = (addr[4] << 8) | (addr[5]); 1119c5aff182SThomas Petazzoni mac_h = (addr[0] << 24) | (addr[1] << 16) | 1120c5aff182SThomas Petazzoni (addr[2] << 8) | (addr[3] << 0); 1121c5aff182SThomas Petazzoni 1122c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_MAC_ADDR_LOW, mac_l); 1123c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_MAC_ADDR_HIGH, mac_h); 1124c5aff182SThomas Petazzoni } 1125c5aff182SThomas Petazzoni 1126c5aff182SThomas Petazzoni /* Accept frames of this address */ 1127c5aff182SThomas Petazzoni mvneta_set_ucast_addr(pp, addr[5], queue); 1128c5aff182SThomas Petazzoni } 1129c5aff182SThomas Petazzoni 11306a20c175SThomas Petazzoni /* Set the number of packets that will be received before RX interrupt 11316a20c175SThomas Petazzoni * will be generated by HW. 1132c5aff182SThomas Petazzoni */ 1133c5aff182SThomas Petazzoni static void mvneta_rx_pkts_coal_set(struct mvneta_port *pp, 1134c5aff182SThomas Petazzoni struct mvneta_rx_queue *rxq, u32 value) 1135c5aff182SThomas Petazzoni { 1136c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_RXQ_THRESHOLD_REG(rxq->id), 1137c5aff182SThomas Petazzoni value | MVNETA_RXQ_NON_OCCUPIED(0)); 1138c5aff182SThomas Petazzoni rxq->pkts_coal = value; 1139c5aff182SThomas Petazzoni } 1140c5aff182SThomas Petazzoni 11416a20c175SThomas Petazzoni /* Set the time delay in usec before RX interrupt will be generated by 11426a20c175SThomas Petazzoni * HW. 1143c5aff182SThomas Petazzoni */ 1144c5aff182SThomas Petazzoni static void mvneta_rx_time_coal_set(struct mvneta_port *pp, 1145c5aff182SThomas Petazzoni struct mvneta_rx_queue *rxq, u32 value) 1146c5aff182SThomas Petazzoni { 1147189dd626SThomas Petazzoni u32 val; 1148189dd626SThomas Petazzoni unsigned long clk_rate; 1149189dd626SThomas Petazzoni 1150189dd626SThomas Petazzoni clk_rate = clk_get_rate(pp->clk); 1151189dd626SThomas Petazzoni val = (clk_rate / 1000000) * value; 1152c5aff182SThomas Petazzoni 1153c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_RXQ_TIME_COAL_REG(rxq->id), val); 1154c5aff182SThomas Petazzoni rxq->time_coal = value; 1155c5aff182SThomas Petazzoni } 1156c5aff182SThomas Petazzoni 1157c5aff182SThomas Petazzoni /* Set threshold for TX_DONE pkts coalescing */ 1158c5aff182SThomas Petazzoni static void mvneta_tx_done_pkts_coal_set(struct mvneta_port *pp, 1159c5aff182SThomas Petazzoni struct mvneta_tx_queue *txq, u32 value) 1160c5aff182SThomas Petazzoni { 1161c5aff182SThomas Petazzoni u32 val; 1162c5aff182SThomas Petazzoni 1163c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_TXQ_SIZE_REG(txq->id)); 1164c5aff182SThomas Petazzoni 1165c5aff182SThomas Petazzoni val &= ~MVNETA_TXQ_SENT_THRESH_ALL_MASK; 1166c5aff182SThomas Petazzoni val |= MVNETA_TXQ_SENT_THRESH_MASK(value); 1167c5aff182SThomas Petazzoni 1168c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_TXQ_SIZE_REG(txq->id), val); 1169c5aff182SThomas Petazzoni 1170c5aff182SThomas Petazzoni txq->done_pkts_coal = value; 1171c5aff182SThomas Petazzoni } 1172c5aff182SThomas Petazzoni 1173c5aff182SThomas Petazzoni /* Handle rx descriptor fill by setting buf_cookie and buf_phys_addr */ 1174c5aff182SThomas Petazzoni static void mvneta_rx_desc_fill(struct mvneta_rx_desc *rx_desc, 1175c5aff182SThomas Petazzoni u32 phys_addr, u32 cookie) 1176c5aff182SThomas Petazzoni { 1177c5aff182SThomas Petazzoni rx_desc->buf_cookie = cookie; 1178c5aff182SThomas Petazzoni rx_desc->buf_phys_addr = phys_addr; 1179c5aff182SThomas Petazzoni } 1180c5aff182SThomas Petazzoni 1181c5aff182SThomas Petazzoni /* Decrement sent descriptors counter */ 1182c5aff182SThomas Petazzoni static void mvneta_txq_sent_desc_dec(struct mvneta_port *pp, 1183c5aff182SThomas Petazzoni struct mvneta_tx_queue *txq, 1184c5aff182SThomas Petazzoni int sent_desc) 1185c5aff182SThomas Petazzoni { 1186c5aff182SThomas Petazzoni u32 val; 1187c5aff182SThomas Petazzoni 1188c5aff182SThomas Petazzoni /* Only 255 TX descriptors can be updated at once */ 1189c5aff182SThomas Petazzoni while (sent_desc > 0xff) { 1190c5aff182SThomas Petazzoni val = 0xff << MVNETA_TXQ_DEC_SENT_SHIFT; 1191c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val); 1192c5aff182SThomas Petazzoni sent_desc = sent_desc - 0xff; 1193c5aff182SThomas Petazzoni } 1194c5aff182SThomas Petazzoni 1195c5aff182SThomas Petazzoni val = sent_desc << MVNETA_TXQ_DEC_SENT_SHIFT; 1196c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val); 1197c5aff182SThomas Petazzoni } 1198c5aff182SThomas Petazzoni 1199c5aff182SThomas Petazzoni /* Get number of TX descriptors already sent by HW */ 1200c5aff182SThomas Petazzoni static int mvneta_txq_sent_desc_num_get(struct mvneta_port *pp, 1201c5aff182SThomas Petazzoni struct mvneta_tx_queue *txq) 1202c5aff182SThomas Petazzoni { 1203c5aff182SThomas Petazzoni u32 val; 1204c5aff182SThomas Petazzoni int sent_desc; 1205c5aff182SThomas Petazzoni 1206c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_TXQ_STATUS_REG(txq->id)); 1207c5aff182SThomas Petazzoni sent_desc = (val & MVNETA_TXQ_SENT_DESC_MASK) >> 1208c5aff182SThomas Petazzoni MVNETA_TXQ_SENT_DESC_SHIFT; 1209c5aff182SThomas Petazzoni 1210c5aff182SThomas Petazzoni return sent_desc; 1211c5aff182SThomas Petazzoni } 1212c5aff182SThomas Petazzoni 12136a20c175SThomas Petazzoni /* Get number of sent descriptors and decrement counter. 1214c5aff182SThomas Petazzoni * The number of sent descriptors is returned. 1215c5aff182SThomas Petazzoni */ 1216c5aff182SThomas Petazzoni static int mvneta_txq_sent_desc_proc(struct mvneta_port *pp, 1217c5aff182SThomas Petazzoni struct mvneta_tx_queue *txq) 1218c5aff182SThomas Petazzoni { 1219c5aff182SThomas Petazzoni int sent_desc; 1220c5aff182SThomas Petazzoni 1221c5aff182SThomas Petazzoni /* Get number of sent descriptors */ 1222c5aff182SThomas Petazzoni sent_desc = mvneta_txq_sent_desc_num_get(pp, txq); 1223c5aff182SThomas Petazzoni 1224c5aff182SThomas Petazzoni /* Decrement sent descriptors counter */ 1225c5aff182SThomas Petazzoni if (sent_desc) 1226c5aff182SThomas Petazzoni mvneta_txq_sent_desc_dec(pp, txq, sent_desc); 1227c5aff182SThomas Petazzoni 1228c5aff182SThomas Petazzoni return sent_desc; 1229c5aff182SThomas Petazzoni } 1230c5aff182SThomas Petazzoni 1231c5aff182SThomas Petazzoni /* Set TXQ descriptors fields relevant for CSUM calculation */ 1232c5aff182SThomas Petazzoni static u32 mvneta_txq_desc_csum(int l3_offs, int l3_proto, 1233c5aff182SThomas Petazzoni int ip_hdr_len, int l4_proto) 1234c5aff182SThomas Petazzoni { 1235c5aff182SThomas Petazzoni u32 command; 1236c5aff182SThomas Petazzoni 1237c5aff182SThomas Petazzoni /* Fields: L3_offset, IP_hdrlen, L3_type, G_IPv4_chk, 12386a20c175SThomas Petazzoni * G_L4_chk, L4_type; required only for checksum 12396a20c175SThomas Petazzoni * calculation 12406a20c175SThomas Petazzoni */ 1241c5aff182SThomas Petazzoni command = l3_offs << MVNETA_TX_L3_OFF_SHIFT; 1242c5aff182SThomas Petazzoni command |= ip_hdr_len << MVNETA_TX_IP_HLEN_SHIFT; 1243c5aff182SThomas Petazzoni 12440a198587SThomas Fitzsimmons if (l3_proto == htons(ETH_P_IP)) 1245c5aff182SThomas Petazzoni command |= MVNETA_TXD_IP_CSUM; 1246c5aff182SThomas Petazzoni else 1247c5aff182SThomas Petazzoni command |= MVNETA_TX_L3_IP6; 1248c5aff182SThomas Petazzoni 1249c5aff182SThomas Petazzoni if (l4_proto == IPPROTO_TCP) 1250c5aff182SThomas Petazzoni command |= MVNETA_TX_L4_CSUM_FULL; 1251c5aff182SThomas Petazzoni else if (l4_proto == IPPROTO_UDP) 1252c5aff182SThomas Petazzoni command |= MVNETA_TX_L4_UDP | MVNETA_TX_L4_CSUM_FULL; 1253c5aff182SThomas Petazzoni else 1254c5aff182SThomas Petazzoni command |= MVNETA_TX_L4_CSUM_NOT; 1255c5aff182SThomas Petazzoni 1256c5aff182SThomas Petazzoni return command; 1257c5aff182SThomas Petazzoni } 1258c5aff182SThomas Petazzoni 1259c5aff182SThomas Petazzoni 1260c5aff182SThomas Petazzoni /* Display more error info */ 1261c5aff182SThomas Petazzoni static void mvneta_rx_error(struct mvneta_port *pp, 1262c5aff182SThomas Petazzoni struct mvneta_rx_desc *rx_desc) 1263c5aff182SThomas Petazzoni { 1264c5aff182SThomas Petazzoni u32 status = rx_desc->status; 1265c5aff182SThomas Petazzoni 12665428213cSwilly tarreau if (!mvneta_rxq_desc_is_first_last(status)) { 1267c5aff182SThomas Petazzoni netdev_err(pp->dev, 1268c5aff182SThomas Petazzoni "bad rx status %08x (buffer oversize), size=%d\n", 12695428213cSwilly tarreau status, rx_desc->data_size); 1270c5aff182SThomas Petazzoni return; 1271c5aff182SThomas Petazzoni } 1272c5aff182SThomas Petazzoni 1273c5aff182SThomas Petazzoni switch (status & MVNETA_RXD_ERR_CODE_MASK) { 1274c5aff182SThomas Petazzoni case MVNETA_RXD_ERR_CRC: 1275c5aff182SThomas Petazzoni netdev_err(pp->dev, "bad rx status %08x (crc error), size=%d\n", 1276c5aff182SThomas Petazzoni status, rx_desc->data_size); 1277c5aff182SThomas Petazzoni break; 1278c5aff182SThomas Petazzoni case MVNETA_RXD_ERR_OVERRUN: 1279c5aff182SThomas Petazzoni netdev_err(pp->dev, "bad rx status %08x (overrun error), size=%d\n", 1280c5aff182SThomas Petazzoni status, rx_desc->data_size); 1281c5aff182SThomas Petazzoni break; 1282c5aff182SThomas Petazzoni case MVNETA_RXD_ERR_LEN: 1283c5aff182SThomas Petazzoni netdev_err(pp->dev, "bad rx status %08x (max frame length error), size=%d\n", 1284c5aff182SThomas Petazzoni status, rx_desc->data_size); 1285c5aff182SThomas Petazzoni break; 1286c5aff182SThomas Petazzoni case MVNETA_RXD_ERR_RESOURCE: 1287c5aff182SThomas Petazzoni netdev_err(pp->dev, "bad rx status %08x (resource error), size=%d\n", 1288c5aff182SThomas Petazzoni status, rx_desc->data_size); 1289c5aff182SThomas Petazzoni break; 1290c5aff182SThomas Petazzoni } 1291c5aff182SThomas Petazzoni } 1292c5aff182SThomas Petazzoni 12935428213cSwilly tarreau /* Handle RX checksum offload based on the descriptor's status */ 12945428213cSwilly tarreau static void mvneta_rx_csum(struct mvneta_port *pp, u32 status, 1295c5aff182SThomas Petazzoni struct sk_buff *skb) 1296c5aff182SThomas Petazzoni { 12975428213cSwilly tarreau if ((status & MVNETA_RXD_L3_IP4) && 12985428213cSwilly tarreau (status & MVNETA_RXD_L4_CSUM_OK)) { 1299c5aff182SThomas Petazzoni skb->csum = 0; 1300c5aff182SThomas Petazzoni skb->ip_summed = CHECKSUM_UNNECESSARY; 1301c5aff182SThomas Petazzoni return; 1302c5aff182SThomas Petazzoni } 1303c5aff182SThomas Petazzoni 1304c5aff182SThomas Petazzoni skb->ip_summed = CHECKSUM_NONE; 1305c5aff182SThomas Petazzoni } 1306c5aff182SThomas Petazzoni 13076c498974Swilly tarreau /* Return tx queue pointer (find last set bit) according to <cause> returned 13086c498974Swilly tarreau * form tx_done reg. <cause> must not be null. The return value is always a 13096c498974Swilly tarreau * valid queue for matching the first one found in <cause>. 13106c498974Swilly tarreau */ 1311c5aff182SThomas Petazzoni static struct mvneta_tx_queue *mvneta_tx_done_policy(struct mvneta_port *pp, 1312c5aff182SThomas Petazzoni u32 cause) 1313c5aff182SThomas Petazzoni { 1314c5aff182SThomas Petazzoni int queue = fls(cause) - 1; 1315c5aff182SThomas Petazzoni 13166c498974Swilly tarreau return &pp->txqs[queue]; 1317c5aff182SThomas Petazzoni } 1318c5aff182SThomas Petazzoni 1319c5aff182SThomas Petazzoni /* Free tx queue skbuffs */ 1320c5aff182SThomas Petazzoni static void mvneta_txq_bufs_free(struct mvneta_port *pp, 1321c5aff182SThomas Petazzoni struct mvneta_tx_queue *txq, int num) 1322c5aff182SThomas Petazzoni { 1323c5aff182SThomas Petazzoni int i; 1324c5aff182SThomas Petazzoni 1325c5aff182SThomas Petazzoni for (i = 0; i < num; i++) { 1326c5aff182SThomas Petazzoni struct mvneta_tx_desc *tx_desc = txq->descs + 1327c5aff182SThomas Petazzoni txq->txq_get_index; 1328c5aff182SThomas Petazzoni struct sk_buff *skb = txq->tx_skb[txq->txq_get_index]; 1329c5aff182SThomas Petazzoni 1330c5aff182SThomas Petazzoni mvneta_txq_inc_get(txq); 1331c5aff182SThomas Petazzoni 13322e3173a3SEzequiel Garcia if (!IS_TSO_HEADER(txq, tx_desc->buf_phys_addr)) 13332e3173a3SEzequiel Garcia dma_unmap_single(pp->dev->dev.parent, 13342e3173a3SEzequiel Garcia tx_desc->buf_phys_addr, 1335c5aff182SThomas Petazzoni tx_desc->data_size, DMA_TO_DEVICE); 1336ba7e46efSEzequiel Garcia if (!skb) 1337ba7e46efSEzequiel Garcia continue; 1338c5aff182SThomas Petazzoni dev_kfree_skb_any(skb); 1339c5aff182SThomas Petazzoni } 1340c5aff182SThomas Petazzoni } 1341c5aff182SThomas Petazzoni 1342c5aff182SThomas Petazzoni /* Handle end of transmission */ 1343cd713199SArnaud Ebalard static void mvneta_txq_done(struct mvneta_port *pp, 1344c5aff182SThomas Petazzoni struct mvneta_tx_queue *txq) 1345c5aff182SThomas Petazzoni { 1346c5aff182SThomas Petazzoni struct netdev_queue *nq = netdev_get_tx_queue(pp->dev, txq->id); 1347c5aff182SThomas Petazzoni int tx_done; 1348c5aff182SThomas Petazzoni 1349c5aff182SThomas Petazzoni tx_done = mvneta_txq_sent_desc_proc(pp, txq); 1350cd713199SArnaud Ebalard if (!tx_done) 1351cd713199SArnaud Ebalard return; 1352cd713199SArnaud Ebalard 1353c5aff182SThomas Petazzoni mvneta_txq_bufs_free(pp, txq, tx_done); 1354c5aff182SThomas Petazzoni 1355c5aff182SThomas Petazzoni txq->count -= tx_done; 1356c5aff182SThomas Petazzoni 1357c5aff182SThomas Petazzoni if (netif_tx_queue_stopped(nq)) { 13588eef5f97SEzequiel Garcia if (txq->count <= txq->tx_wake_threshold) 1359c5aff182SThomas Petazzoni netif_tx_wake_queue(nq); 1360c5aff182SThomas Petazzoni } 1361c5aff182SThomas Petazzoni } 1362c5aff182SThomas Petazzoni 13638ec2cd48Swilly tarreau static void *mvneta_frag_alloc(const struct mvneta_port *pp) 13648ec2cd48Swilly tarreau { 13658ec2cd48Swilly tarreau if (likely(pp->frag_size <= PAGE_SIZE)) 13668ec2cd48Swilly tarreau return netdev_alloc_frag(pp->frag_size); 13678ec2cd48Swilly tarreau else 13688ec2cd48Swilly tarreau return kmalloc(pp->frag_size, GFP_ATOMIC); 13698ec2cd48Swilly tarreau } 13708ec2cd48Swilly tarreau 13718ec2cd48Swilly tarreau static void mvneta_frag_free(const struct mvneta_port *pp, void *data) 13728ec2cd48Swilly tarreau { 13738ec2cd48Swilly tarreau if (likely(pp->frag_size <= PAGE_SIZE)) 137413dc0d2bSAlexander Duyck skb_free_frag(data); 13758ec2cd48Swilly tarreau else 13768ec2cd48Swilly tarreau kfree(data); 13778ec2cd48Swilly tarreau } 13788ec2cd48Swilly tarreau 1379c5aff182SThomas Petazzoni /* Refill processing */ 1380c5aff182SThomas Petazzoni static int mvneta_rx_refill(struct mvneta_port *pp, 1381c5aff182SThomas Petazzoni struct mvneta_rx_desc *rx_desc) 1382c5aff182SThomas Petazzoni 1383c5aff182SThomas Petazzoni { 1384c5aff182SThomas Petazzoni dma_addr_t phys_addr; 13858ec2cd48Swilly tarreau void *data; 1386c5aff182SThomas Petazzoni 13878ec2cd48Swilly tarreau data = mvneta_frag_alloc(pp); 13888ec2cd48Swilly tarreau if (!data) 1389c5aff182SThomas Petazzoni return -ENOMEM; 1390c5aff182SThomas Petazzoni 13918ec2cd48Swilly tarreau phys_addr = dma_map_single(pp->dev->dev.parent, data, 1392c5aff182SThomas Petazzoni MVNETA_RX_BUF_SIZE(pp->pkt_size), 1393c5aff182SThomas Petazzoni DMA_FROM_DEVICE); 1394c5aff182SThomas Petazzoni if (unlikely(dma_mapping_error(pp->dev->dev.parent, phys_addr))) { 13958ec2cd48Swilly tarreau mvneta_frag_free(pp, data); 1396c5aff182SThomas Petazzoni return -ENOMEM; 1397c5aff182SThomas Petazzoni } 1398c5aff182SThomas Petazzoni 13998ec2cd48Swilly tarreau mvneta_rx_desc_fill(rx_desc, phys_addr, (u32)data); 1400c5aff182SThomas Petazzoni return 0; 1401c5aff182SThomas Petazzoni } 1402c5aff182SThomas Petazzoni 1403c5aff182SThomas Petazzoni /* Handle tx checksum */ 1404c5aff182SThomas Petazzoni static u32 mvneta_skb_tx_csum(struct mvneta_port *pp, struct sk_buff *skb) 1405c5aff182SThomas Petazzoni { 1406c5aff182SThomas Petazzoni if (skb->ip_summed == CHECKSUM_PARTIAL) { 1407c5aff182SThomas Petazzoni int ip_hdr_len = 0; 1408817dbfa5SVlad Yasevich __be16 l3_proto = vlan_get_protocol(skb); 1409c5aff182SThomas Petazzoni u8 l4_proto; 1410c5aff182SThomas Petazzoni 1411817dbfa5SVlad Yasevich if (l3_proto == htons(ETH_P_IP)) { 1412c5aff182SThomas Petazzoni struct iphdr *ip4h = ip_hdr(skb); 1413c5aff182SThomas Petazzoni 1414c5aff182SThomas Petazzoni /* Calculate IPv4 checksum and L4 checksum */ 1415c5aff182SThomas Petazzoni ip_hdr_len = ip4h->ihl; 1416c5aff182SThomas Petazzoni l4_proto = ip4h->protocol; 1417817dbfa5SVlad Yasevich } else if (l3_proto == htons(ETH_P_IPV6)) { 1418c5aff182SThomas Petazzoni struct ipv6hdr *ip6h = ipv6_hdr(skb); 1419c5aff182SThomas Petazzoni 1420c5aff182SThomas Petazzoni /* Read l4_protocol from one of IPv6 extra headers */ 1421c5aff182SThomas Petazzoni if (skb_network_header_len(skb) > 0) 1422c5aff182SThomas Petazzoni ip_hdr_len = (skb_network_header_len(skb) >> 2); 1423c5aff182SThomas Petazzoni l4_proto = ip6h->nexthdr; 1424c5aff182SThomas Petazzoni } else 1425c5aff182SThomas Petazzoni return MVNETA_TX_L4_CSUM_NOT; 1426c5aff182SThomas Petazzoni 1427c5aff182SThomas Petazzoni return mvneta_txq_desc_csum(skb_network_offset(skb), 1428817dbfa5SVlad Yasevich l3_proto, ip_hdr_len, l4_proto); 1429c5aff182SThomas Petazzoni } 1430c5aff182SThomas Petazzoni 1431c5aff182SThomas Petazzoni return MVNETA_TX_L4_CSUM_NOT; 1432c5aff182SThomas Petazzoni } 1433c5aff182SThomas Petazzoni 1434c5aff182SThomas Petazzoni /* Drop packets received by the RXQ and free buffers */ 1435c5aff182SThomas Petazzoni static void mvneta_rxq_drop_pkts(struct mvneta_port *pp, 1436c5aff182SThomas Petazzoni struct mvneta_rx_queue *rxq) 1437c5aff182SThomas Petazzoni { 1438c5aff182SThomas Petazzoni int rx_done, i; 1439c5aff182SThomas Petazzoni 1440c5aff182SThomas Petazzoni rx_done = mvneta_rxq_busy_desc_num_get(pp, rxq); 1441c5aff182SThomas Petazzoni for (i = 0; i < rxq->size; i++) { 1442c5aff182SThomas Petazzoni struct mvneta_rx_desc *rx_desc = rxq->descs + i; 14438ec2cd48Swilly tarreau void *data = (void *)rx_desc->buf_cookie; 1444c5aff182SThomas Petazzoni 14458ec2cd48Swilly tarreau mvneta_frag_free(pp, data); 1446c5aff182SThomas Petazzoni dma_unmap_single(pp->dev->dev.parent, rx_desc->buf_phys_addr, 1447a328f3a0SEzequiel Garcia MVNETA_RX_BUF_SIZE(pp->pkt_size), DMA_FROM_DEVICE); 1448c5aff182SThomas Petazzoni } 1449c5aff182SThomas Petazzoni 1450c5aff182SThomas Petazzoni if (rx_done) 1451c5aff182SThomas Petazzoni mvneta_rxq_desc_num_update(pp, rxq, rx_done, rx_done); 1452c5aff182SThomas Petazzoni } 1453c5aff182SThomas Petazzoni 1454c5aff182SThomas Petazzoni /* Main rx processing */ 1455c5aff182SThomas Petazzoni static int mvneta_rx(struct mvneta_port *pp, int rx_todo, 1456c5aff182SThomas Petazzoni struct mvneta_rx_queue *rxq) 1457c5aff182SThomas Petazzoni { 145812bb03b4SMaxime Ripard struct mvneta_pcpu_port *port = this_cpu_ptr(pp->ports); 1459c5aff182SThomas Petazzoni struct net_device *dev = pp->dev; 1460a84e3289SSimon Guinot int rx_done; 1461dc4277ddSwilly tarreau u32 rcvd_pkts = 0; 1462dc4277ddSwilly tarreau u32 rcvd_bytes = 0; 1463c5aff182SThomas Petazzoni 1464c5aff182SThomas Petazzoni /* Get number of received packets */ 1465c5aff182SThomas Petazzoni rx_done = mvneta_rxq_busy_desc_num_get(pp, rxq); 1466c5aff182SThomas Petazzoni 1467c5aff182SThomas Petazzoni if (rx_todo > rx_done) 1468c5aff182SThomas Petazzoni rx_todo = rx_done; 1469c5aff182SThomas Petazzoni 1470c5aff182SThomas Petazzoni rx_done = 0; 1471c5aff182SThomas Petazzoni 1472c5aff182SThomas Petazzoni /* Fairness NAPI loop */ 1473c5aff182SThomas Petazzoni while (rx_done < rx_todo) { 1474c5aff182SThomas Petazzoni struct mvneta_rx_desc *rx_desc = mvneta_rxq_next_desc_get(rxq); 1475c5aff182SThomas Petazzoni struct sk_buff *skb; 14768ec2cd48Swilly tarreau unsigned char *data; 1477daf158d0SSimon Guinot dma_addr_t phys_addr; 1478c5aff182SThomas Petazzoni u32 rx_status; 1479c5aff182SThomas Petazzoni int rx_bytes, err; 1480c5aff182SThomas Petazzoni 1481c5aff182SThomas Petazzoni rx_done++; 1482c5aff182SThomas Petazzoni rx_status = rx_desc->status; 1483f19fadfcSwilly tarreau rx_bytes = rx_desc->data_size - (ETH_FCS_LEN + MVNETA_MH_SIZE); 14848ec2cd48Swilly tarreau data = (unsigned char *)rx_desc->buf_cookie; 1485daf158d0SSimon Guinot phys_addr = rx_desc->buf_phys_addr; 1486c5aff182SThomas Petazzoni 14875428213cSwilly tarreau if (!mvneta_rxq_desc_is_first_last(rx_status) || 1488f19fadfcSwilly tarreau (rx_status & MVNETA_RXD_ERR_SUMMARY)) { 1489f19fadfcSwilly tarreau err_drop_frame: 1490c5aff182SThomas Petazzoni dev->stats.rx_errors++; 1491c5aff182SThomas Petazzoni mvneta_rx_error(pp, rx_desc); 14928ec2cd48Swilly tarreau /* leave the descriptor untouched */ 1493c5aff182SThomas Petazzoni continue; 1494c5aff182SThomas Petazzoni } 1495c5aff182SThomas Petazzoni 1496f19fadfcSwilly tarreau if (rx_bytes <= rx_copybreak) { 1497f19fadfcSwilly tarreau /* better copy a small frame and not unmap the DMA region */ 1498f19fadfcSwilly tarreau skb = netdev_alloc_skb_ip_align(dev, rx_bytes); 1499f19fadfcSwilly tarreau if (unlikely(!skb)) 1500f19fadfcSwilly tarreau goto err_drop_frame; 1501f19fadfcSwilly tarreau 1502f19fadfcSwilly tarreau dma_sync_single_range_for_cpu(dev->dev.parent, 1503f19fadfcSwilly tarreau rx_desc->buf_phys_addr, 1504f19fadfcSwilly tarreau MVNETA_MH_SIZE + NET_SKB_PAD, 1505f19fadfcSwilly tarreau rx_bytes, 1506f19fadfcSwilly tarreau DMA_FROM_DEVICE); 1507f19fadfcSwilly tarreau memcpy(skb_put(skb, rx_bytes), 1508f19fadfcSwilly tarreau data + MVNETA_MH_SIZE + NET_SKB_PAD, 1509f19fadfcSwilly tarreau rx_bytes); 1510f19fadfcSwilly tarreau 1511f19fadfcSwilly tarreau skb->protocol = eth_type_trans(skb, dev); 1512f19fadfcSwilly tarreau mvneta_rx_csum(pp, rx_status, skb); 151312bb03b4SMaxime Ripard napi_gro_receive(&port->napi, skb); 1514f19fadfcSwilly tarreau 1515f19fadfcSwilly tarreau rcvd_pkts++; 1516f19fadfcSwilly tarreau rcvd_bytes += rx_bytes; 1517f19fadfcSwilly tarreau 1518f19fadfcSwilly tarreau /* leave the descriptor and buffer untouched */ 1519f19fadfcSwilly tarreau continue; 1520f19fadfcSwilly tarreau } 1521f19fadfcSwilly tarreau 1522a84e3289SSimon Guinot /* Refill processing */ 1523a84e3289SSimon Guinot err = mvneta_rx_refill(pp, rx_desc); 1524a84e3289SSimon Guinot if (err) { 1525a84e3289SSimon Guinot netdev_err(dev, "Linux processing - Can't refill\n"); 1526a84e3289SSimon Guinot rxq->missed++; 1527a84e3289SSimon Guinot goto err_drop_frame; 1528a84e3289SSimon Guinot } 1529a84e3289SSimon Guinot 1530f19fadfcSwilly tarreau skb = build_skb(data, pp->frag_size > PAGE_SIZE ? 0 : pp->frag_size); 1531f19fadfcSwilly tarreau if (!skb) 1532f19fadfcSwilly tarreau goto err_drop_frame; 1533f19fadfcSwilly tarreau 1534daf158d0SSimon Guinot dma_unmap_single(dev->dev.parent, phys_addr, 1535a328f3a0SEzequiel Garcia MVNETA_RX_BUF_SIZE(pp->pkt_size), DMA_FROM_DEVICE); 1536c5aff182SThomas Petazzoni 1537dc4277ddSwilly tarreau rcvd_pkts++; 1538dc4277ddSwilly tarreau rcvd_bytes += rx_bytes; 1539c5aff182SThomas Petazzoni 1540c5aff182SThomas Petazzoni /* Linux processing */ 15418ec2cd48Swilly tarreau skb_reserve(skb, MVNETA_MH_SIZE + NET_SKB_PAD); 1542c5aff182SThomas Petazzoni skb_put(skb, rx_bytes); 1543c5aff182SThomas Petazzoni 1544c5aff182SThomas Petazzoni skb->protocol = eth_type_trans(skb, dev); 1545c5aff182SThomas Petazzoni 15465428213cSwilly tarreau mvneta_rx_csum(pp, rx_status, skb); 1547c5aff182SThomas Petazzoni 154812bb03b4SMaxime Ripard napi_gro_receive(&port->napi, skb); 1549c5aff182SThomas Petazzoni } 1550c5aff182SThomas Petazzoni 1551dc4277ddSwilly tarreau if (rcvd_pkts) { 155274c41b04Swilly tarreau struct mvneta_pcpu_stats *stats = this_cpu_ptr(pp->stats); 155374c41b04Swilly tarreau 155474c41b04Swilly tarreau u64_stats_update_begin(&stats->syncp); 155574c41b04Swilly tarreau stats->rx_packets += rcvd_pkts; 155674c41b04Swilly tarreau stats->rx_bytes += rcvd_bytes; 155774c41b04Swilly tarreau u64_stats_update_end(&stats->syncp); 1558dc4277ddSwilly tarreau } 1559dc4277ddSwilly tarreau 1560c5aff182SThomas Petazzoni /* Update rxq management counters */ 1561a84e3289SSimon Guinot mvneta_rxq_desc_num_update(pp, rxq, rx_done, rx_done); 1562c5aff182SThomas Petazzoni 1563c5aff182SThomas Petazzoni return rx_done; 1564c5aff182SThomas Petazzoni } 1565c5aff182SThomas Petazzoni 15662adb719dSEzequiel Garcia static inline void 15672adb719dSEzequiel Garcia mvneta_tso_put_hdr(struct sk_buff *skb, 15682adb719dSEzequiel Garcia struct mvneta_port *pp, struct mvneta_tx_queue *txq) 15692adb719dSEzequiel Garcia { 15702adb719dSEzequiel Garcia struct mvneta_tx_desc *tx_desc; 15712adb719dSEzequiel Garcia int hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb); 15722adb719dSEzequiel Garcia 15732adb719dSEzequiel Garcia txq->tx_skb[txq->txq_put_index] = NULL; 15742adb719dSEzequiel Garcia tx_desc = mvneta_txq_next_desc_get(txq); 15752adb719dSEzequiel Garcia tx_desc->data_size = hdr_len; 15762adb719dSEzequiel Garcia tx_desc->command = mvneta_skb_tx_csum(pp, skb); 15772adb719dSEzequiel Garcia tx_desc->command |= MVNETA_TXD_F_DESC; 15782adb719dSEzequiel Garcia tx_desc->buf_phys_addr = txq->tso_hdrs_phys + 15792adb719dSEzequiel Garcia txq->txq_put_index * TSO_HEADER_SIZE; 15802adb719dSEzequiel Garcia mvneta_txq_inc_put(txq); 15812adb719dSEzequiel Garcia } 15822adb719dSEzequiel Garcia 15832adb719dSEzequiel Garcia static inline int 15842adb719dSEzequiel Garcia mvneta_tso_put_data(struct net_device *dev, struct mvneta_tx_queue *txq, 15852adb719dSEzequiel Garcia struct sk_buff *skb, char *data, int size, 15862adb719dSEzequiel Garcia bool last_tcp, bool is_last) 15872adb719dSEzequiel Garcia { 15882adb719dSEzequiel Garcia struct mvneta_tx_desc *tx_desc; 15892adb719dSEzequiel Garcia 15902adb719dSEzequiel Garcia tx_desc = mvneta_txq_next_desc_get(txq); 15912adb719dSEzequiel Garcia tx_desc->data_size = size; 15922adb719dSEzequiel Garcia tx_desc->buf_phys_addr = dma_map_single(dev->dev.parent, data, 15932adb719dSEzequiel Garcia size, DMA_TO_DEVICE); 15942adb719dSEzequiel Garcia if (unlikely(dma_mapping_error(dev->dev.parent, 15952adb719dSEzequiel Garcia tx_desc->buf_phys_addr))) { 15962adb719dSEzequiel Garcia mvneta_txq_desc_put(txq); 15972adb719dSEzequiel Garcia return -ENOMEM; 15982adb719dSEzequiel Garcia } 15992adb719dSEzequiel Garcia 16002adb719dSEzequiel Garcia tx_desc->command = 0; 16012adb719dSEzequiel Garcia txq->tx_skb[txq->txq_put_index] = NULL; 16022adb719dSEzequiel Garcia 16032adb719dSEzequiel Garcia if (last_tcp) { 16042adb719dSEzequiel Garcia /* last descriptor in the TCP packet */ 16052adb719dSEzequiel Garcia tx_desc->command = MVNETA_TXD_L_DESC; 16062adb719dSEzequiel Garcia 16072adb719dSEzequiel Garcia /* last descriptor in SKB */ 16082adb719dSEzequiel Garcia if (is_last) 16092adb719dSEzequiel Garcia txq->tx_skb[txq->txq_put_index] = skb; 16102adb719dSEzequiel Garcia } 16112adb719dSEzequiel Garcia mvneta_txq_inc_put(txq); 16122adb719dSEzequiel Garcia return 0; 16132adb719dSEzequiel Garcia } 16142adb719dSEzequiel Garcia 16152adb719dSEzequiel Garcia static int mvneta_tx_tso(struct sk_buff *skb, struct net_device *dev, 16162adb719dSEzequiel Garcia struct mvneta_tx_queue *txq) 16172adb719dSEzequiel Garcia { 16182adb719dSEzequiel Garcia int total_len, data_left; 16192adb719dSEzequiel Garcia int desc_count = 0; 16202adb719dSEzequiel Garcia struct mvneta_port *pp = netdev_priv(dev); 16212adb719dSEzequiel Garcia struct tso_t tso; 16222adb719dSEzequiel Garcia int hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb); 16232adb719dSEzequiel Garcia int i; 16242adb719dSEzequiel Garcia 16252adb719dSEzequiel Garcia /* Count needed descriptors */ 16262adb719dSEzequiel Garcia if ((txq->count + tso_count_descs(skb)) >= txq->size) 16272adb719dSEzequiel Garcia return 0; 16282adb719dSEzequiel Garcia 16292adb719dSEzequiel Garcia if (skb_headlen(skb) < (skb_transport_offset(skb) + tcp_hdrlen(skb))) { 16302adb719dSEzequiel Garcia pr_info("*** Is this even possible???!?!?\n"); 16312adb719dSEzequiel Garcia return 0; 16322adb719dSEzequiel Garcia } 16332adb719dSEzequiel Garcia 16342adb719dSEzequiel Garcia /* Initialize the TSO handler, and prepare the first payload */ 16352adb719dSEzequiel Garcia tso_start(skb, &tso); 16362adb719dSEzequiel Garcia 16372adb719dSEzequiel Garcia total_len = skb->len - hdr_len; 16382adb719dSEzequiel Garcia while (total_len > 0) { 16392adb719dSEzequiel Garcia char *hdr; 16402adb719dSEzequiel Garcia 16412adb719dSEzequiel Garcia data_left = min_t(int, skb_shinfo(skb)->gso_size, total_len); 16422adb719dSEzequiel Garcia total_len -= data_left; 16432adb719dSEzequiel Garcia desc_count++; 16442adb719dSEzequiel Garcia 16452adb719dSEzequiel Garcia /* prepare packet headers: MAC + IP + TCP */ 16462adb719dSEzequiel Garcia hdr = txq->tso_hdrs + txq->txq_put_index * TSO_HEADER_SIZE; 16472adb719dSEzequiel Garcia tso_build_hdr(skb, hdr, &tso, data_left, total_len == 0); 16482adb719dSEzequiel Garcia 16492adb719dSEzequiel Garcia mvneta_tso_put_hdr(skb, pp, txq); 16502adb719dSEzequiel Garcia 16512adb719dSEzequiel Garcia while (data_left > 0) { 16522adb719dSEzequiel Garcia int size; 16532adb719dSEzequiel Garcia desc_count++; 16542adb719dSEzequiel Garcia 16552adb719dSEzequiel Garcia size = min_t(int, tso.size, data_left); 16562adb719dSEzequiel Garcia 16572adb719dSEzequiel Garcia if (mvneta_tso_put_data(dev, txq, skb, 16582adb719dSEzequiel Garcia tso.data, size, 16592adb719dSEzequiel Garcia size == data_left, 16602adb719dSEzequiel Garcia total_len == 0)) 16612adb719dSEzequiel Garcia goto err_release; 16622adb719dSEzequiel Garcia data_left -= size; 16632adb719dSEzequiel Garcia 16642adb719dSEzequiel Garcia tso_build_data(skb, &tso, size); 16652adb719dSEzequiel Garcia } 16662adb719dSEzequiel Garcia } 16672adb719dSEzequiel Garcia 16682adb719dSEzequiel Garcia return desc_count; 16692adb719dSEzequiel Garcia 16702adb719dSEzequiel Garcia err_release: 16712adb719dSEzequiel Garcia /* Release all used data descriptors; header descriptors must not 16722adb719dSEzequiel Garcia * be DMA-unmapped. 16732adb719dSEzequiel Garcia */ 16742adb719dSEzequiel Garcia for (i = desc_count - 1; i >= 0; i--) { 16752adb719dSEzequiel Garcia struct mvneta_tx_desc *tx_desc = txq->descs + i; 16762e3173a3SEzequiel Garcia if (!IS_TSO_HEADER(txq, tx_desc->buf_phys_addr)) 16772adb719dSEzequiel Garcia dma_unmap_single(pp->dev->dev.parent, 16782adb719dSEzequiel Garcia tx_desc->buf_phys_addr, 16792adb719dSEzequiel Garcia tx_desc->data_size, 16802adb719dSEzequiel Garcia DMA_TO_DEVICE); 16812adb719dSEzequiel Garcia mvneta_txq_desc_put(txq); 16822adb719dSEzequiel Garcia } 16832adb719dSEzequiel Garcia return 0; 16842adb719dSEzequiel Garcia } 16852adb719dSEzequiel Garcia 1686c5aff182SThomas Petazzoni /* Handle tx fragmentation processing */ 1687c5aff182SThomas Petazzoni static int mvneta_tx_frag_process(struct mvneta_port *pp, struct sk_buff *skb, 1688c5aff182SThomas Petazzoni struct mvneta_tx_queue *txq) 1689c5aff182SThomas Petazzoni { 1690c5aff182SThomas Petazzoni struct mvneta_tx_desc *tx_desc; 16913d4ea02fSEzequiel Garcia int i, nr_frags = skb_shinfo(skb)->nr_frags; 1692c5aff182SThomas Petazzoni 16933d4ea02fSEzequiel Garcia for (i = 0; i < nr_frags; i++) { 1694c5aff182SThomas Petazzoni skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 1695c5aff182SThomas Petazzoni void *addr = page_address(frag->page.p) + frag->page_offset; 1696c5aff182SThomas Petazzoni 1697c5aff182SThomas Petazzoni tx_desc = mvneta_txq_next_desc_get(txq); 1698c5aff182SThomas Petazzoni tx_desc->data_size = frag->size; 1699c5aff182SThomas Petazzoni 1700c5aff182SThomas Petazzoni tx_desc->buf_phys_addr = 1701c5aff182SThomas Petazzoni dma_map_single(pp->dev->dev.parent, addr, 1702c5aff182SThomas Petazzoni tx_desc->data_size, DMA_TO_DEVICE); 1703c5aff182SThomas Petazzoni 1704c5aff182SThomas Petazzoni if (dma_mapping_error(pp->dev->dev.parent, 1705c5aff182SThomas Petazzoni tx_desc->buf_phys_addr)) { 1706c5aff182SThomas Petazzoni mvneta_txq_desc_put(txq); 1707c5aff182SThomas Petazzoni goto error; 1708c5aff182SThomas Petazzoni } 1709c5aff182SThomas Petazzoni 17103d4ea02fSEzequiel Garcia if (i == nr_frags - 1) { 1711c5aff182SThomas Petazzoni /* Last descriptor */ 1712c5aff182SThomas Petazzoni tx_desc->command = MVNETA_TXD_L_DESC | MVNETA_TXD_Z_PAD; 1713c5aff182SThomas Petazzoni txq->tx_skb[txq->txq_put_index] = skb; 1714c5aff182SThomas Petazzoni } else { 1715c5aff182SThomas Petazzoni /* Descriptor in the middle: Not First, Not Last */ 1716c5aff182SThomas Petazzoni tx_desc->command = 0; 1717c5aff182SThomas Petazzoni txq->tx_skb[txq->txq_put_index] = NULL; 1718c5aff182SThomas Petazzoni } 17193d4ea02fSEzequiel Garcia mvneta_txq_inc_put(txq); 1720c5aff182SThomas Petazzoni } 1721c5aff182SThomas Petazzoni 1722c5aff182SThomas Petazzoni return 0; 1723c5aff182SThomas Petazzoni 1724c5aff182SThomas Petazzoni error: 1725c5aff182SThomas Petazzoni /* Release all descriptors that were used to map fragments of 17266a20c175SThomas Petazzoni * this packet, as well as the corresponding DMA mappings 17276a20c175SThomas Petazzoni */ 1728c5aff182SThomas Petazzoni for (i = i - 1; i >= 0; i--) { 1729c5aff182SThomas Petazzoni tx_desc = txq->descs + i; 1730c5aff182SThomas Petazzoni dma_unmap_single(pp->dev->dev.parent, 1731c5aff182SThomas Petazzoni tx_desc->buf_phys_addr, 1732c5aff182SThomas Petazzoni tx_desc->data_size, 1733c5aff182SThomas Petazzoni DMA_TO_DEVICE); 1734c5aff182SThomas Petazzoni mvneta_txq_desc_put(txq); 1735c5aff182SThomas Petazzoni } 1736c5aff182SThomas Petazzoni 1737c5aff182SThomas Petazzoni return -ENOMEM; 1738c5aff182SThomas Petazzoni } 1739c5aff182SThomas Petazzoni 1740c5aff182SThomas Petazzoni /* Main tx processing */ 1741c5aff182SThomas Petazzoni static int mvneta_tx(struct sk_buff *skb, struct net_device *dev) 1742c5aff182SThomas Petazzoni { 1743c5aff182SThomas Petazzoni struct mvneta_port *pp = netdev_priv(dev); 1744ee40a116SWilly Tarreau u16 txq_id = skb_get_queue_mapping(skb); 1745ee40a116SWilly Tarreau struct mvneta_tx_queue *txq = &pp->txqs[txq_id]; 1746c5aff182SThomas Petazzoni struct mvneta_tx_desc *tx_desc; 17475f478b41SEric Dumazet int len = skb->len; 1748c5aff182SThomas Petazzoni int frags = 0; 1749c5aff182SThomas Petazzoni u32 tx_cmd; 1750c5aff182SThomas Petazzoni 1751c5aff182SThomas Petazzoni if (!netif_running(dev)) 1752c5aff182SThomas Petazzoni goto out; 1753c5aff182SThomas Petazzoni 17542adb719dSEzequiel Garcia if (skb_is_gso(skb)) { 17552adb719dSEzequiel Garcia frags = mvneta_tx_tso(skb, dev, txq); 17562adb719dSEzequiel Garcia goto out; 17572adb719dSEzequiel Garcia } 17582adb719dSEzequiel Garcia 1759c5aff182SThomas Petazzoni frags = skb_shinfo(skb)->nr_frags + 1; 1760c5aff182SThomas Petazzoni 1761c5aff182SThomas Petazzoni /* Get a descriptor for the first part of the packet */ 1762c5aff182SThomas Petazzoni tx_desc = mvneta_txq_next_desc_get(txq); 1763c5aff182SThomas Petazzoni 1764c5aff182SThomas Petazzoni tx_cmd = mvneta_skb_tx_csum(pp, skb); 1765c5aff182SThomas Petazzoni 1766c5aff182SThomas Petazzoni tx_desc->data_size = skb_headlen(skb); 1767c5aff182SThomas Petazzoni 1768c5aff182SThomas Petazzoni tx_desc->buf_phys_addr = dma_map_single(dev->dev.parent, skb->data, 1769c5aff182SThomas Petazzoni tx_desc->data_size, 1770c5aff182SThomas Petazzoni DMA_TO_DEVICE); 1771c5aff182SThomas Petazzoni if (unlikely(dma_mapping_error(dev->dev.parent, 1772c5aff182SThomas Petazzoni tx_desc->buf_phys_addr))) { 1773c5aff182SThomas Petazzoni mvneta_txq_desc_put(txq); 1774c5aff182SThomas Petazzoni frags = 0; 1775c5aff182SThomas Petazzoni goto out; 1776c5aff182SThomas Petazzoni } 1777c5aff182SThomas Petazzoni 1778c5aff182SThomas Petazzoni if (frags == 1) { 1779c5aff182SThomas Petazzoni /* First and Last descriptor */ 1780c5aff182SThomas Petazzoni tx_cmd |= MVNETA_TXD_FLZ_DESC; 1781c5aff182SThomas Petazzoni tx_desc->command = tx_cmd; 1782c5aff182SThomas Petazzoni txq->tx_skb[txq->txq_put_index] = skb; 1783c5aff182SThomas Petazzoni mvneta_txq_inc_put(txq); 1784c5aff182SThomas Petazzoni } else { 1785c5aff182SThomas Petazzoni /* First but not Last */ 1786c5aff182SThomas Petazzoni tx_cmd |= MVNETA_TXD_F_DESC; 1787c5aff182SThomas Petazzoni txq->tx_skb[txq->txq_put_index] = NULL; 1788c5aff182SThomas Petazzoni mvneta_txq_inc_put(txq); 1789c5aff182SThomas Petazzoni tx_desc->command = tx_cmd; 1790c5aff182SThomas Petazzoni /* Continue with other skb fragments */ 1791c5aff182SThomas Petazzoni if (mvneta_tx_frag_process(pp, skb, txq)) { 1792c5aff182SThomas Petazzoni dma_unmap_single(dev->dev.parent, 1793c5aff182SThomas Petazzoni tx_desc->buf_phys_addr, 1794c5aff182SThomas Petazzoni tx_desc->data_size, 1795c5aff182SThomas Petazzoni DMA_TO_DEVICE); 1796c5aff182SThomas Petazzoni mvneta_txq_desc_put(txq); 1797c5aff182SThomas Petazzoni frags = 0; 1798c5aff182SThomas Petazzoni goto out; 1799c5aff182SThomas Petazzoni } 1800c5aff182SThomas Petazzoni } 1801c5aff182SThomas Petazzoni 1802e19d2ddaSEzequiel Garcia out: 1803e19d2ddaSEzequiel Garcia if (frags > 0) { 1804e19d2ddaSEzequiel Garcia struct mvneta_pcpu_stats *stats = this_cpu_ptr(pp->stats); 1805e19d2ddaSEzequiel Garcia struct netdev_queue *nq = netdev_get_tx_queue(dev, txq_id); 1806e19d2ddaSEzequiel Garcia 1807c5aff182SThomas Petazzoni txq->count += frags; 1808c5aff182SThomas Petazzoni mvneta_txq_pend_desc_add(pp, txq, frags); 1809c5aff182SThomas Petazzoni 18108eef5f97SEzequiel Garcia if (txq->count >= txq->tx_stop_threshold) 1811c5aff182SThomas Petazzoni netif_tx_stop_queue(nq); 1812c5aff182SThomas Petazzoni 181374c41b04Swilly tarreau u64_stats_update_begin(&stats->syncp); 181474c41b04Swilly tarreau stats->tx_packets++; 18155f478b41SEric Dumazet stats->tx_bytes += len; 181674c41b04Swilly tarreau u64_stats_update_end(&stats->syncp); 1817c5aff182SThomas Petazzoni } else { 1818c5aff182SThomas Petazzoni dev->stats.tx_dropped++; 1819c5aff182SThomas Petazzoni dev_kfree_skb_any(skb); 1820c5aff182SThomas Petazzoni } 1821c5aff182SThomas Petazzoni 1822c5aff182SThomas Petazzoni return NETDEV_TX_OK; 1823c5aff182SThomas Petazzoni } 1824c5aff182SThomas Petazzoni 1825c5aff182SThomas Petazzoni 1826c5aff182SThomas Petazzoni /* Free tx resources, when resetting a port */ 1827c5aff182SThomas Petazzoni static void mvneta_txq_done_force(struct mvneta_port *pp, 1828c5aff182SThomas Petazzoni struct mvneta_tx_queue *txq) 1829c5aff182SThomas Petazzoni 1830c5aff182SThomas Petazzoni { 1831c5aff182SThomas Petazzoni int tx_done = txq->count; 1832c5aff182SThomas Petazzoni 1833c5aff182SThomas Petazzoni mvneta_txq_bufs_free(pp, txq, tx_done); 1834c5aff182SThomas Petazzoni 1835c5aff182SThomas Petazzoni /* reset txq */ 1836c5aff182SThomas Petazzoni txq->count = 0; 1837c5aff182SThomas Petazzoni txq->txq_put_index = 0; 1838c5aff182SThomas Petazzoni txq->txq_get_index = 0; 1839c5aff182SThomas Petazzoni } 1840c5aff182SThomas Petazzoni 18416c498974Swilly tarreau /* Handle tx done - called in softirq context. The <cause_tx_done> argument 18426c498974Swilly tarreau * must be a valid cause according to MVNETA_TXQ_INTR_MASK_ALL. 18436c498974Swilly tarreau */ 18440713a86aSArnaud Ebalard static void mvneta_tx_done_gbe(struct mvneta_port *pp, u32 cause_tx_done) 1845c5aff182SThomas Petazzoni { 1846c5aff182SThomas Petazzoni struct mvneta_tx_queue *txq; 1847c5aff182SThomas Petazzoni struct netdev_queue *nq; 1848c5aff182SThomas Petazzoni 18496c498974Swilly tarreau while (cause_tx_done) { 1850c5aff182SThomas Petazzoni txq = mvneta_tx_done_policy(pp, cause_tx_done); 1851c5aff182SThomas Petazzoni 1852c5aff182SThomas Petazzoni nq = netdev_get_tx_queue(pp->dev, txq->id); 1853c5aff182SThomas Petazzoni __netif_tx_lock(nq, smp_processor_id()); 1854c5aff182SThomas Petazzoni 18550713a86aSArnaud Ebalard if (txq->count) 18560713a86aSArnaud Ebalard mvneta_txq_done(pp, txq); 1857c5aff182SThomas Petazzoni 1858c5aff182SThomas Petazzoni __netif_tx_unlock(nq); 1859c5aff182SThomas Petazzoni cause_tx_done &= ~((1 << txq->id)); 1860c5aff182SThomas Petazzoni } 1861c5aff182SThomas Petazzoni } 1862c5aff182SThomas Petazzoni 18636a20c175SThomas Petazzoni /* Compute crc8 of the specified address, using a unique algorithm , 1864c5aff182SThomas Petazzoni * according to hw spec, different than generic crc8 algorithm 1865c5aff182SThomas Petazzoni */ 1866c5aff182SThomas Petazzoni static int mvneta_addr_crc(unsigned char *addr) 1867c5aff182SThomas Petazzoni { 1868c5aff182SThomas Petazzoni int crc = 0; 1869c5aff182SThomas Petazzoni int i; 1870c5aff182SThomas Petazzoni 1871c5aff182SThomas Petazzoni for (i = 0; i < ETH_ALEN; i++) { 1872c5aff182SThomas Petazzoni int j; 1873c5aff182SThomas Petazzoni 1874c5aff182SThomas Petazzoni crc = (crc ^ addr[i]) << 8; 1875c5aff182SThomas Petazzoni for (j = 7; j >= 0; j--) { 1876c5aff182SThomas Petazzoni if (crc & (0x100 << j)) 1877c5aff182SThomas Petazzoni crc ^= 0x107 << j; 1878c5aff182SThomas Petazzoni } 1879c5aff182SThomas Petazzoni } 1880c5aff182SThomas Petazzoni 1881c5aff182SThomas Petazzoni return crc; 1882c5aff182SThomas Petazzoni } 1883c5aff182SThomas Petazzoni 1884c5aff182SThomas Petazzoni /* This method controls the net device special MAC multicast support. 1885c5aff182SThomas Petazzoni * The Special Multicast Table for MAC addresses supports MAC of the form 1886c5aff182SThomas Petazzoni * 0x01-00-5E-00-00-XX (where XX is between 0x00 and 0xFF). 1887c5aff182SThomas Petazzoni * The MAC DA[7:0] bits are used as a pointer to the Special Multicast 1888c5aff182SThomas Petazzoni * Table entries in the DA-Filter table. This method set the Special 1889c5aff182SThomas Petazzoni * Multicast Table appropriate entry. 1890c5aff182SThomas Petazzoni */ 1891c5aff182SThomas Petazzoni static void mvneta_set_special_mcast_addr(struct mvneta_port *pp, 1892c5aff182SThomas Petazzoni unsigned char last_byte, 1893c5aff182SThomas Petazzoni int queue) 1894c5aff182SThomas Petazzoni { 1895c5aff182SThomas Petazzoni unsigned int smc_table_reg; 1896c5aff182SThomas Petazzoni unsigned int tbl_offset; 1897c5aff182SThomas Petazzoni unsigned int reg_offset; 1898c5aff182SThomas Petazzoni 1899c5aff182SThomas Petazzoni /* Register offset from SMC table base */ 1900c5aff182SThomas Petazzoni tbl_offset = (last_byte / 4); 1901c5aff182SThomas Petazzoni /* Entry offset within the above reg */ 1902c5aff182SThomas Petazzoni reg_offset = last_byte % 4; 1903c5aff182SThomas Petazzoni 1904c5aff182SThomas Petazzoni smc_table_reg = mvreg_read(pp, (MVNETA_DA_FILT_SPEC_MCAST 1905c5aff182SThomas Petazzoni + tbl_offset * 4)); 1906c5aff182SThomas Petazzoni 1907c5aff182SThomas Petazzoni if (queue == -1) 1908c5aff182SThomas Petazzoni smc_table_reg &= ~(0xff << (8 * reg_offset)); 1909c5aff182SThomas Petazzoni else { 1910c5aff182SThomas Petazzoni smc_table_reg &= ~(0xff << (8 * reg_offset)); 1911c5aff182SThomas Petazzoni smc_table_reg |= ((0x01 | (queue << 1)) << (8 * reg_offset)); 1912c5aff182SThomas Petazzoni } 1913c5aff182SThomas Petazzoni 1914c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_DA_FILT_SPEC_MCAST + tbl_offset * 4, 1915c5aff182SThomas Petazzoni smc_table_reg); 1916c5aff182SThomas Petazzoni } 1917c5aff182SThomas Petazzoni 1918c5aff182SThomas Petazzoni /* This method controls the network device Other MAC multicast support. 1919c5aff182SThomas Petazzoni * The Other Multicast Table is used for multicast of another type. 1920c5aff182SThomas Petazzoni * A CRC-8 is used as an index to the Other Multicast Table entries 1921c5aff182SThomas Petazzoni * in the DA-Filter table. 1922c5aff182SThomas Petazzoni * The method gets the CRC-8 value from the calling routine and 1923c5aff182SThomas Petazzoni * sets the Other Multicast Table appropriate entry according to the 1924c5aff182SThomas Petazzoni * specified CRC-8 . 1925c5aff182SThomas Petazzoni */ 1926c5aff182SThomas Petazzoni static void mvneta_set_other_mcast_addr(struct mvneta_port *pp, 1927c5aff182SThomas Petazzoni unsigned char crc8, 1928c5aff182SThomas Petazzoni int queue) 1929c5aff182SThomas Petazzoni { 1930c5aff182SThomas Petazzoni unsigned int omc_table_reg; 1931c5aff182SThomas Petazzoni unsigned int tbl_offset; 1932c5aff182SThomas Petazzoni unsigned int reg_offset; 1933c5aff182SThomas Petazzoni 1934c5aff182SThomas Petazzoni tbl_offset = (crc8 / 4) * 4; /* Register offset from OMC table base */ 1935c5aff182SThomas Petazzoni reg_offset = crc8 % 4; /* Entry offset within the above reg */ 1936c5aff182SThomas Petazzoni 1937c5aff182SThomas Petazzoni omc_table_reg = mvreg_read(pp, MVNETA_DA_FILT_OTH_MCAST + tbl_offset); 1938c5aff182SThomas Petazzoni 1939c5aff182SThomas Petazzoni if (queue == -1) { 1940c5aff182SThomas Petazzoni /* Clear accepts frame bit at specified Other DA table entry */ 1941c5aff182SThomas Petazzoni omc_table_reg &= ~(0xff << (8 * reg_offset)); 1942c5aff182SThomas Petazzoni } else { 1943c5aff182SThomas Petazzoni omc_table_reg &= ~(0xff << (8 * reg_offset)); 1944c5aff182SThomas Petazzoni omc_table_reg |= ((0x01 | (queue << 1)) << (8 * reg_offset)); 1945c5aff182SThomas Petazzoni } 1946c5aff182SThomas Petazzoni 1947c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_DA_FILT_OTH_MCAST + tbl_offset, omc_table_reg); 1948c5aff182SThomas Petazzoni } 1949c5aff182SThomas Petazzoni 1950c5aff182SThomas Petazzoni /* The network device supports multicast using two tables: 1951c5aff182SThomas Petazzoni * 1) Special Multicast Table for MAC addresses of the form 1952c5aff182SThomas Petazzoni * 0x01-00-5E-00-00-XX (where XX is between 0x00 and 0xFF). 1953c5aff182SThomas Petazzoni * The MAC DA[7:0] bits are used as a pointer to the Special Multicast 1954c5aff182SThomas Petazzoni * Table entries in the DA-Filter table. 1955c5aff182SThomas Petazzoni * 2) Other Multicast Table for multicast of another type. A CRC-8 value 1956c5aff182SThomas Petazzoni * is used as an index to the Other Multicast Table entries in the 1957c5aff182SThomas Petazzoni * DA-Filter table. 1958c5aff182SThomas Petazzoni */ 1959c5aff182SThomas Petazzoni static int mvneta_mcast_addr_set(struct mvneta_port *pp, unsigned char *p_addr, 1960c5aff182SThomas Petazzoni int queue) 1961c5aff182SThomas Petazzoni { 1962c5aff182SThomas Petazzoni unsigned char crc_result = 0; 1963c5aff182SThomas Petazzoni 1964c5aff182SThomas Petazzoni if (memcmp(p_addr, "\x01\x00\x5e\x00\x00", 5) == 0) { 1965c5aff182SThomas Petazzoni mvneta_set_special_mcast_addr(pp, p_addr[5], queue); 1966c5aff182SThomas Petazzoni return 0; 1967c5aff182SThomas Petazzoni } 1968c5aff182SThomas Petazzoni 1969c5aff182SThomas Petazzoni crc_result = mvneta_addr_crc(p_addr); 1970c5aff182SThomas Petazzoni if (queue == -1) { 1971c5aff182SThomas Petazzoni if (pp->mcast_count[crc_result] == 0) { 1972c5aff182SThomas Petazzoni netdev_info(pp->dev, "No valid Mcast for crc8=0x%02x\n", 1973c5aff182SThomas Petazzoni crc_result); 1974c5aff182SThomas Petazzoni return -EINVAL; 1975c5aff182SThomas Petazzoni } 1976c5aff182SThomas Petazzoni 1977c5aff182SThomas Petazzoni pp->mcast_count[crc_result]--; 1978c5aff182SThomas Petazzoni if (pp->mcast_count[crc_result] != 0) { 1979c5aff182SThomas Petazzoni netdev_info(pp->dev, 1980c5aff182SThomas Petazzoni "After delete there are %d valid Mcast for crc8=0x%02x\n", 1981c5aff182SThomas Petazzoni pp->mcast_count[crc_result], crc_result); 1982c5aff182SThomas Petazzoni return -EINVAL; 1983c5aff182SThomas Petazzoni } 1984c5aff182SThomas Petazzoni } else 1985c5aff182SThomas Petazzoni pp->mcast_count[crc_result]++; 1986c5aff182SThomas Petazzoni 1987c5aff182SThomas Petazzoni mvneta_set_other_mcast_addr(pp, crc_result, queue); 1988c5aff182SThomas Petazzoni 1989c5aff182SThomas Petazzoni return 0; 1990c5aff182SThomas Petazzoni } 1991c5aff182SThomas Petazzoni 1992c5aff182SThomas Petazzoni /* Configure Fitering mode of Ethernet port */ 1993c5aff182SThomas Petazzoni static void mvneta_rx_unicast_promisc_set(struct mvneta_port *pp, 1994c5aff182SThomas Petazzoni int is_promisc) 1995c5aff182SThomas Petazzoni { 1996c5aff182SThomas Petazzoni u32 port_cfg_reg, val; 1997c5aff182SThomas Petazzoni 1998c5aff182SThomas Petazzoni port_cfg_reg = mvreg_read(pp, MVNETA_PORT_CONFIG); 1999c5aff182SThomas Petazzoni 2000c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_TYPE_PRIO); 2001c5aff182SThomas Petazzoni 2002c5aff182SThomas Petazzoni /* Set / Clear UPM bit in port configuration register */ 2003c5aff182SThomas Petazzoni if (is_promisc) { 2004c5aff182SThomas Petazzoni /* Accept all Unicast addresses */ 2005c5aff182SThomas Petazzoni port_cfg_reg |= MVNETA_UNI_PROMISC_MODE; 2006c5aff182SThomas Petazzoni val |= MVNETA_FORCE_UNI; 2007c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_MAC_ADDR_LOW, 0xffff); 2008c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_MAC_ADDR_HIGH, 0xffffffff); 2009c5aff182SThomas Petazzoni } else { 2010c5aff182SThomas Petazzoni /* Reject all Unicast addresses */ 2011c5aff182SThomas Petazzoni port_cfg_reg &= ~MVNETA_UNI_PROMISC_MODE; 2012c5aff182SThomas Petazzoni val &= ~MVNETA_FORCE_UNI; 2013c5aff182SThomas Petazzoni } 2014c5aff182SThomas Petazzoni 2015c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_PORT_CONFIG, port_cfg_reg); 2016c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_TYPE_PRIO, val); 2017c5aff182SThomas Petazzoni } 2018c5aff182SThomas Petazzoni 2019c5aff182SThomas Petazzoni /* register unicast and multicast addresses */ 2020c5aff182SThomas Petazzoni static void mvneta_set_rx_mode(struct net_device *dev) 2021c5aff182SThomas Petazzoni { 2022c5aff182SThomas Petazzoni struct mvneta_port *pp = netdev_priv(dev); 2023c5aff182SThomas Petazzoni struct netdev_hw_addr *ha; 2024c5aff182SThomas Petazzoni 2025c5aff182SThomas Petazzoni if (dev->flags & IFF_PROMISC) { 2026c5aff182SThomas Petazzoni /* Accept all: Multicast + Unicast */ 2027c5aff182SThomas Petazzoni mvneta_rx_unicast_promisc_set(pp, 1); 2028c5aff182SThomas Petazzoni mvneta_set_ucast_table(pp, rxq_def); 2029c5aff182SThomas Petazzoni mvneta_set_special_mcast_table(pp, rxq_def); 2030c5aff182SThomas Petazzoni mvneta_set_other_mcast_table(pp, rxq_def); 2031c5aff182SThomas Petazzoni } else { 2032c5aff182SThomas Petazzoni /* Accept single Unicast */ 2033c5aff182SThomas Petazzoni mvneta_rx_unicast_promisc_set(pp, 0); 2034c5aff182SThomas Petazzoni mvneta_set_ucast_table(pp, -1); 2035c5aff182SThomas Petazzoni mvneta_mac_addr_set(pp, dev->dev_addr, rxq_def); 2036c5aff182SThomas Petazzoni 2037c5aff182SThomas Petazzoni if (dev->flags & IFF_ALLMULTI) { 2038c5aff182SThomas Petazzoni /* Accept all multicast */ 2039c5aff182SThomas Petazzoni mvneta_set_special_mcast_table(pp, rxq_def); 2040c5aff182SThomas Petazzoni mvneta_set_other_mcast_table(pp, rxq_def); 2041c5aff182SThomas Petazzoni } else { 2042c5aff182SThomas Petazzoni /* Accept only initialized multicast */ 2043c5aff182SThomas Petazzoni mvneta_set_special_mcast_table(pp, -1); 2044c5aff182SThomas Petazzoni mvneta_set_other_mcast_table(pp, -1); 2045c5aff182SThomas Petazzoni 2046c5aff182SThomas Petazzoni if (!netdev_mc_empty(dev)) { 2047c5aff182SThomas Petazzoni netdev_for_each_mc_addr(ha, dev) { 2048c5aff182SThomas Petazzoni mvneta_mcast_addr_set(pp, ha->addr, 2049c5aff182SThomas Petazzoni rxq_def); 2050c5aff182SThomas Petazzoni } 2051c5aff182SThomas Petazzoni } 2052c5aff182SThomas Petazzoni } 2053c5aff182SThomas Petazzoni } 2054c5aff182SThomas Petazzoni } 2055c5aff182SThomas Petazzoni 2056c5aff182SThomas Petazzoni /* Interrupt handling - the callback for request_irq() */ 2057c5aff182SThomas Petazzoni static irqreturn_t mvneta_isr(int irq, void *dev_id) 2058c5aff182SThomas Petazzoni { 205912bb03b4SMaxime Ripard struct mvneta_pcpu_port *port = (struct mvneta_pcpu_port *)dev_id; 2060c5aff182SThomas Petazzoni 206112bb03b4SMaxime Ripard disable_percpu_irq(port->pp->dev->irq); 206212bb03b4SMaxime Ripard napi_schedule(&port->napi); 2063c5aff182SThomas Petazzoni 2064c5aff182SThomas Petazzoni return IRQ_HANDLED; 2065c5aff182SThomas Petazzoni } 2066c5aff182SThomas Petazzoni 2067898b2970SStas Sergeev static int mvneta_fixed_link_update(struct mvneta_port *pp, 2068898b2970SStas Sergeev struct phy_device *phy) 2069898b2970SStas Sergeev { 2070898b2970SStas Sergeev struct fixed_phy_status status; 2071898b2970SStas Sergeev struct fixed_phy_status changed = {}; 2072898b2970SStas Sergeev u32 gmac_stat = mvreg_read(pp, MVNETA_GMAC_STATUS); 2073898b2970SStas Sergeev 2074898b2970SStas Sergeev status.link = !!(gmac_stat & MVNETA_GMAC_LINK_UP); 2075898b2970SStas Sergeev if (gmac_stat & MVNETA_GMAC_SPEED_1000) 2076898b2970SStas Sergeev status.speed = SPEED_1000; 2077898b2970SStas Sergeev else if (gmac_stat & MVNETA_GMAC_SPEED_100) 2078898b2970SStas Sergeev status.speed = SPEED_100; 2079898b2970SStas Sergeev else 2080898b2970SStas Sergeev status.speed = SPEED_10; 2081898b2970SStas Sergeev status.duplex = !!(gmac_stat & MVNETA_GMAC_FULL_DUPLEX); 2082898b2970SStas Sergeev changed.link = 1; 2083898b2970SStas Sergeev changed.speed = 1; 2084898b2970SStas Sergeev changed.duplex = 1; 2085898b2970SStas Sergeev fixed_phy_update_state(phy, &status, &changed); 2086898b2970SStas Sergeev return 0; 2087898b2970SStas Sergeev } 2088898b2970SStas Sergeev 2089c5aff182SThomas Petazzoni /* NAPI handler 2090c5aff182SThomas Petazzoni * Bits 0 - 7 of the causeRxTx register indicate that are transmitted 2091c5aff182SThomas Petazzoni * packets on the corresponding TXQ (Bit 0 is for TX queue 1). 2092c5aff182SThomas Petazzoni * Bits 8 -15 of the cause Rx Tx register indicate that are received 2093c5aff182SThomas Petazzoni * packets on the corresponding RXQ (Bit 8 is for RX queue 0). 2094c5aff182SThomas Petazzoni * Each CPU has its own causeRxTx register 2095c5aff182SThomas Petazzoni */ 2096c5aff182SThomas Petazzoni static int mvneta_poll(struct napi_struct *napi, int budget) 2097c5aff182SThomas Petazzoni { 2098c5aff182SThomas Petazzoni int rx_done = 0; 2099c5aff182SThomas Petazzoni u32 cause_rx_tx; 2100c5aff182SThomas Petazzoni struct mvneta_port *pp = netdev_priv(napi->dev); 210112bb03b4SMaxime Ripard struct mvneta_pcpu_port *port = this_cpu_ptr(pp->ports); 2102c5aff182SThomas Petazzoni 2103c5aff182SThomas Petazzoni if (!netif_running(pp->dev)) { 210412bb03b4SMaxime Ripard napi_complete(&port->napi); 2105c5aff182SThomas Petazzoni return rx_done; 2106c5aff182SThomas Petazzoni } 2107c5aff182SThomas Petazzoni 2108c5aff182SThomas Petazzoni /* Read cause register */ 2109898b2970SStas Sergeev cause_rx_tx = mvreg_read(pp, MVNETA_INTR_NEW_CAUSE); 2110898b2970SStas Sergeev if (cause_rx_tx & MVNETA_MISCINTR_INTR_MASK) { 2111898b2970SStas Sergeev u32 cause_misc = mvreg_read(pp, MVNETA_INTR_MISC_CAUSE); 2112898b2970SStas Sergeev 2113898b2970SStas Sergeev mvreg_write(pp, MVNETA_INTR_MISC_CAUSE, 0); 2114898b2970SStas Sergeev if (pp->use_inband_status && (cause_misc & 2115898b2970SStas Sergeev (MVNETA_CAUSE_PHY_STATUS_CHANGE | 2116898b2970SStas Sergeev MVNETA_CAUSE_LINK_CHANGE | 2117898b2970SStas Sergeev MVNETA_CAUSE_PSC_SYNC_CHANGE))) { 2118898b2970SStas Sergeev mvneta_fixed_link_update(pp, pp->phy_dev); 2119898b2970SStas Sergeev } 2120898b2970SStas Sergeev } 212171f6d1b3Swilly tarreau 212271f6d1b3Swilly tarreau /* Release Tx descriptors */ 212371f6d1b3Swilly tarreau if (cause_rx_tx & MVNETA_TX_INTR_MASK_ALL) { 21240713a86aSArnaud Ebalard mvneta_tx_done_gbe(pp, (cause_rx_tx & MVNETA_TX_INTR_MASK_ALL)); 212571f6d1b3Swilly tarreau cause_rx_tx &= ~MVNETA_TX_INTR_MASK_ALL; 212671f6d1b3Swilly tarreau } 2127c5aff182SThomas Petazzoni 21286a20c175SThomas Petazzoni /* For the case where the last mvneta_poll did not process all 2129c5aff182SThomas Petazzoni * RX packets 2130c5aff182SThomas Petazzoni */ 213112bb03b4SMaxime Ripard cause_rx_tx |= port->cause_rx_tx; 2132c5aff182SThomas Petazzoni rx_done = mvneta_rx(pp, budget, &pp->rxqs[rxq_def]); 2133c5aff182SThomas Petazzoni budget -= rx_done; 2134c5aff182SThomas Petazzoni 2135c5aff182SThomas Petazzoni if (budget > 0) { 2136c5aff182SThomas Petazzoni cause_rx_tx = 0; 213712bb03b4SMaxime Ripard napi_complete(&port->napi); 213812bb03b4SMaxime Ripard enable_percpu_irq(pp->dev->irq, 0); 2139c5aff182SThomas Petazzoni } 2140c5aff182SThomas Petazzoni 214112bb03b4SMaxime Ripard port->cause_rx_tx = cause_rx_tx; 2142c5aff182SThomas Petazzoni return rx_done; 2143c5aff182SThomas Petazzoni } 2144c5aff182SThomas Petazzoni 2145c5aff182SThomas Petazzoni /* Handle rxq fill: allocates rxq skbs; called when initializing a port */ 2146c5aff182SThomas Petazzoni static int mvneta_rxq_fill(struct mvneta_port *pp, struct mvneta_rx_queue *rxq, 2147c5aff182SThomas Petazzoni int num) 2148c5aff182SThomas Petazzoni { 2149c5aff182SThomas Petazzoni int i; 2150c5aff182SThomas Petazzoni 2151c5aff182SThomas Petazzoni for (i = 0; i < num; i++) { 2152a1a65ab1Swilly tarreau memset(rxq->descs + i, 0, sizeof(struct mvneta_rx_desc)); 2153a1a65ab1Swilly tarreau if (mvneta_rx_refill(pp, rxq->descs + i) != 0) { 2154a1a65ab1Swilly tarreau netdev_err(pp->dev, "%s:rxq %d, %d of %d buffs filled\n", 2155c5aff182SThomas Petazzoni __func__, rxq->id, i, num); 2156c5aff182SThomas Petazzoni break; 2157c5aff182SThomas Petazzoni } 2158c5aff182SThomas Petazzoni } 2159c5aff182SThomas Petazzoni 2160c5aff182SThomas Petazzoni /* Add this number of RX descriptors as non occupied (ready to 21616a20c175SThomas Petazzoni * get packets) 21626a20c175SThomas Petazzoni */ 2163c5aff182SThomas Petazzoni mvneta_rxq_non_occup_desc_add(pp, rxq, i); 2164c5aff182SThomas Petazzoni 2165c5aff182SThomas Petazzoni return i; 2166c5aff182SThomas Petazzoni } 2167c5aff182SThomas Petazzoni 2168c5aff182SThomas Petazzoni /* Free all packets pending transmit from all TXQs and reset TX port */ 2169c5aff182SThomas Petazzoni static void mvneta_tx_reset(struct mvneta_port *pp) 2170c5aff182SThomas Petazzoni { 2171c5aff182SThomas Petazzoni int queue; 2172c5aff182SThomas Petazzoni 21739672850bSEzequiel Garcia /* free the skb's in the tx ring */ 2174c5aff182SThomas Petazzoni for (queue = 0; queue < txq_number; queue++) 2175c5aff182SThomas Petazzoni mvneta_txq_done_force(pp, &pp->txqs[queue]); 2176c5aff182SThomas Petazzoni 2177c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_PORT_TX_RESET, MVNETA_PORT_TX_DMA_RESET); 2178c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_PORT_TX_RESET, 0); 2179c5aff182SThomas Petazzoni } 2180c5aff182SThomas Petazzoni 2181c5aff182SThomas Petazzoni static void mvneta_rx_reset(struct mvneta_port *pp) 2182c5aff182SThomas Petazzoni { 2183c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_PORT_RX_RESET, MVNETA_PORT_RX_DMA_RESET); 2184c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_PORT_RX_RESET, 0); 2185c5aff182SThomas Petazzoni } 2186c5aff182SThomas Petazzoni 2187c5aff182SThomas Petazzoni /* Rx/Tx queue initialization/cleanup methods */ 2188c5aff182SThomas Petazzoni 2189c5aff182SThomas Petazzoni /* Create a specified RX queue */ 2190c5aff182SThomas Petazzoni static int mvneta_rxq_init(struct mvneta_port *pp, 2191c5aff182SThomas Petazzoni struct mvneta_rx_queue *rxq) 2192c5aff182SThomas Petazzoni 2193c5aff182SThomas Petazzoni { 2194c5aff182SThomas Petazzoni rxq->size = pp->rx_ring_size; 2195c5aff182SThomas Petazzoni 2196c5aff182SThomas Petazzoni /* Allocate memory for RX descriptors */ 2197c5aff182SThomas Petazzoni rxq->descs = dma_alloc_coherent(pp->dev->dev.parent, 2198c5aff182SThomas Petazzoni rxq->size * MVNETA_DESC_ALIGNED_SIZE, 2199c5aff182SThomas Petazzoni &rxq->descs_phys, GFP_KERNEL); 2200d0320f75SJoe Perches if (rxq->descs == NULL) 2201c5aff182SThomas Petazzoni return -ENOMEM; 2202c5aff182SThomas Petazzoni 2203c5aff182SThomas Petazzoni BUG_ON(rxq->descs != 2204c5aff182SThomas Petazzoni PTR_ALIGN(rxq->descs, MVNETA_CPU_D_CACHE_LINE_SIZE)); 2205c5aff182SThomas Petazzoni 2206c5aff182SThomas Petazzoni rxq->last_desc = rxq->size - 1; 2207c5aff182SThomas Petazzoni 2208c5aff182SThomas Petazzoni /* Set Rx descriptors queue starting address */ 2209c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_RXQ_BASE_ADDR_REG(rxq->id), rxq->descs_phys); 2210c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_RXQ_SIZE_REG(rxq->id), rxq->size); 2211c5aff182SThomas Petazzoni 2212c5aff182SThomas Petazzoni /* Set Offset */ 2213c5aff182SThomas Petazzoni mvneta_rxq_offset_set(pp, rxq, NET_SKB_PAD); 2214c5aff182SThomas Petazzoni 2215c5aff182SThomas Petazzoni /* Set coalescing pkts and time */ 2216c5aff182SThomas Petazzoni mvneta_rx_pkts_coal_set(pp, rxq, rxq->pkts_coal); 2217c5aff182SThomas Petazzoni mvneta_rx_time_coal_set(pp, rxq, rxq->time_coal); 2218c5aff182SThomas Petazzoni 2219c5aff182SThomas Petazzoni /* Fill RXQ with buffers from RX pool */ 2220c5aff182SThomas Petazzoni mvneta_rxq_buf_size_set(pp, rxq, MVNETA_RX_BUF_SIZE(pp->pkt_size)); 2221c5aff182SThomas Petazzoni mvneta_rxq_bm_disable(pp, rxq); 2222c5aff182SThomas Petazzoni mvneta_rxq_fill(pp, rxq, rxq->size); 2223c5aff182SThomas Petazzoni 2224c5aff182SThomas Petazzoni return 0; 2225c5aff182SThomas Petazzoni } 2226c5aff182SThomas Petazzoni 2227c5aff182SThomas Petazzoni /* Cleanup Rx queue */ 2228c5aff182SThomas Petazzoni static void mvneta_rxq_deinit(struct mvneta_port *pp, 2229c5aff182SThomas Petazzoni struct mvneta_rx_queue *rxq) 2230c5aff182SThomas Petazzoni { 2231c5aff182SThomas Petazzoni mvneta_rxq_drop_pkts(pp, rxq); 2232c5aff182SThomas Petazzoni 2233c5aff182SThomas Petazzoni if (rxq->descs) 2234c5aff182SThomas Petazzoni dma_free_coherent(pp->dev->dev.parent, 2235c5aff182SThomas Petazzoni rxq->size * MVNETA_DESC_ALIGNED_SIZE, 2236c5aff182SThomas Petazzoni rxq->descs, 2237c5aff182SThomas Petazzoni rxq->descs_phys); 2238c5aff182SThomas Petazzoni 2239c5aff182SThomas Petazzoni rxq->descs = NULL; 2240c5aff182SThomas Petazzoni rxq->last_desc = 0; 2241c5aff182SThomas Petazzoni rxq->next_desc_to_proc = 0; 2242c5aff182SThomas Petazzoni rxq->descs_phys = 0; 2243c5aff182SThomas Petazzoni } 2244c5aff182SThomas Petazzoni 2245c5aff182SThomas Petazzoni /* Create and initialize a tx queue */ 2246c5aff182SThomas Petazzoni static int mvneta_txq_init(struct mvneta_port *pp, 2247c5aff182SThomas Petazzoni struct mvneta_tx_queue *txq) 2248c5aff182SThomas Petazzoni { 2249c5aff182SThomas Petazzoni txq->size = pp->tx_ring_size; 2250c5aff182SThomas Petazzoni 22518eef5f97SEzequiel Garcia /* A queue must always have room for at least one skb. 22528eef5f97SEzequiel Garcia * Therefore, stop the queue when the free entries reaches 22538eef5f97SEzequiel Garcia * the maximum number of descriptors per skb. 22548eef5f97SEzequiel Garcia */ 22558eef5f97SEzequiel Garcia txq->tx_stop_threshold = txq->size - MVNETA_MAX_SKB_DESCS; 22568eef5f97SEzequiel Garcia txq->tx_wake_threshold = txq->tx_stop_threshold / 2; 22578eef5f97SEzequiel Garcia 22588eef5f97SEzequiel Garcia 2259c5aff182SThomas Petazzoni /* Allocate memory for TX descriptors */ 2260c5aff182SThomas Petazzoni txq->descs = dma_alloc_coherent(pp->dev->dev.parent, 2261c5aff182SThomas Petazzoni txq->size * MVNETA_DESC_ALIGNED_SIZE, 2262c5aff182SThomas Petazzoni &txq->descs_phys, GFP_KERNEL); 2263d0320f75SJoe Perches if (txq->descs == NULL) 2264c5aff182SThomas Petazzoni return -ENOMEM; 2265c5aff182SThomas Petazzoni 2266c5aff182SThomas Petazzoni /* Make sure descriptor address is cache line size aligned */ 2267c5aff182SThomas Petazzoni BUG_ON(txq->descs != 2268c5aff182SThomas Petazzoni PTR_ALIGN(txq->descs, MVNETA_CPU_D_CACHE_LINE_SIZE)); 2269c5aff182SThomas Petazzoni 2270c5aff182SThomas Petazzoni txq->last_desc = txq->size - 1; 2271c5aff182SThomas Petazzoni 2272c5aff182SThomas Petazzoni /* Set maximum bandwidth for enabled TXQs */ 2273c5aff182SThomas Petazzoni mvreg_write(pp, MVETH_TXQ_TOKEN_CFG_REG(txq->id), 0x03ffffff); 2274c5aff182SThomas Petazzoni mvreg_write(pp, MVETH_TXQ_TOKEN_COUNT_REG(txq->id), 0x3fffffff); 2275c5aff182SThomas Petazzoni 2276c5aff182SThomas Petazzoni /* Set Tx descriptors queue starting address */ 2277c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_TXQ_BASE_ADDR_REG(txq->id), txq->descs_phys); 2278c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_TXQ_SIZE_REG(txq->id), txq->size); 2279c5aff182SThomas Petazzoni 2280c5aff182SThomas Petazzoni txq->tx_skb = kmalloc(txq->size * sizeof(*txq->tx_skb), GFP_KERNEL); 2281c5aff182SThomas Petazzoni if (txq->tx_skb == NULL) { 2282c5aff182SThomas Petazzoni dma_free_coherent(pp->dev->dev.parent, 2283c5aff182SThomas Petazzoni txq->size * MVNETA_DESC_ALIGNED_SIZE, 2284c5aff182SThomas Petazzoni txq->descs, txq->descs_phys); 2285c5aff182SThomas Petazzoni return -ENOMEM; 2286c5aff182SThomas Petazzoni } 22872adb719dSEzequiel Garcia 22882adb719dSEzequiel Garcia /* Allocate DMA buffers for TSO MAC/IP/TCP headers */ 22892adb719dSEzequiel Garcia txq->tso_hdrs = dma_alloc_coherent(pp->dev->dev.parent, 22902adb719dSEzequiel Garcia txq->size * TSO_HEADER_SIZE, 22912adb719dSEzequiel Garcia &txq->tso_hdrs_phys, GFP_KERNEL); 22922adb719dSEzequiel Garcia if (txq->tso_hdrs == NULL) { 22932adb719dSEzequiel Garcia kfree(txq->tx_skb); 22942adb719dSEzequiel Garcia dma_free_coherent(pp->dev->dev.parent, 22952adb719dSEzequiel Garcia txq->size * MVNETA_DESC_ALIGNED_SIZE, 22962adb719dSEzequiel Garcia txq->descs, txq->descs_phys); 22972adb719dSEzequiel Garcia return -ENOMEM; 22982adb719dSEzequiel Garcia } 2299c5aff182SThomas Petazzoni mvneta_tx_done_pkts_coal_set(pp, txq, txq->done_pkts_coal); 2300c5aff182SThomas Petazzoni 2301c5aff182SThomas Petazzoni return 0; 2302c5aff182SThomas Petazzoni } 2303c5aff182SThomas Petazzoni 2304c5aff182SThomas Petazzoni /* Free allocated resources when mvneta_txq_init() fails to allocate memory*/ 2305c5aff182SThomas Petazzoni static void mvneta_txq_deinit(struct mvneta_port *pp, 2306c5aff182SThomas Petazzoni struct mvneta_tx_queue *txq) 2307c5aff182SThomas Petazzoni { 2308c5aff182SThomas Petazzoni kfree(txq->tx_skb); 2309c5aff182SThomas Petazzoni 23102adb719dSEzequiel Garcia if (txq->tso_hdrs) 23112adb719dSEzequiel Garcia dma_free_coherent(pp->dev->dev.parent, 23122adb719dSEzequiel Garcia txq->size * TSO_HEADER_SIZE, 23132adb719dSEzequiel Garcia txq->tso_hdrs, txq->tso_hdrs_phys); 2314c5aff182SThomas Petazzoni if (txq->descs) 2315c5aff182SThomas Petazzoni dma_free_coherent(pp->dev->dev.parent, 2316c5aff182SThomas Petazzoni txq->size * MVNETA_DESC_ALIGNED_SIZE, 2317c5aff182SThomas Petazzoni txq->descs, txq->descs_phys); 2318c5aff182SThomas Petazzoni 2319c5aff182SThomas Petazzoni txq->descs = NULL; 2320c5aff182SThomas Petazzoni txq->last_desc = 0; 2321c5aff182SThomas Petazzoni txq->next_desc_to_proc = 0; 2322c5aff182SThomas Petazzoni txq->descs_phys = 0; 2323c5aff182SThomas Petazzoni 2324c5aff182SThomas Petazzoni /* Set minimum bandwidth for disabled TXQs */ 2325c5aff182SThomas Petazzoni mvreg_write(pp, MVETH_TXQ_TOKEN_CFG_REG(txq->id), 0); 2326c5aff182SThomas Petazzoni mvreg_write(pp, MVETH_TXQ_TOKEN_COUNT_REG(txq->id), 0); 2327c5aff182SThomas Petazzoni 2328c5aff182SThomas Petazzoni /* Set Tx descriptors queue starting address and size */ 2329c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_TXQ_BASE_ADDR_REG(txq->id), 0); 2330c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_TXQ_SIZE_REG(txq->id), 0); 2331c5aff182SThomas Petazzoni } 2332c5aff182SThomas Petazzoni 2333c5aff182SThomas Petazzoni /* Cleanup all Tx queues */ 2334c5aff182SThomas Petazzoni static void mvneta_cleanup_txqs(struct mvneta_port *pp) 2335c5aff182SThomas Petazzoni { 2336c5aff182SThomas Petazzoni int queue; 2337c5aff182SThomas Petazzoni 2338c5aff182SThomas Petazzoni for (queue = 0; queue < txq_number; queue++) 2339c5aff182SThomas Petazzoni mvneta_txq_deinit(pp, &pp->txqs[queue]); 2340c5aff182SThomas Petazzoni } 2341c5aff182SThomas Petazzoni 2342c5aff182SThomas Petazzoni /* Cleanup all Rx queues */ 2343c5aff182SThomas Petazzoni static void mvneta_cleanup_rxqs(struct mvneta_port *pp) 2344c5aff182SThomas Petazzoni { 2345d8936657SMaxime Ripard mvneta_rxq_deinit(pp, &pp->rxqs[rxq_def]); 2346c5aff182SThomas Petazzoni } 2347c5aff182SThomas Petazzoni 2348c5aff182SThomas Petazzoni 2349c5aff182SThomas Petazzoni /* Init all Rx queues */ 2350c5aff182SThomas Petazzoni static int mvneta_setup_rxqs(struct mvneta_port *pp) 2351c5aff182SThomas Petazzoni { 2352d8936657SMaxime Ripard int err = mvneta_rxq_init(pp, &pp->rxqs[rxq_def]); 2353c5aff182SThomas Petazzoni if (err) { 2354c5aff182SThomas Petazzoni netdev_err(pp->dev, "%s: can't create rxq=%d\n", 2355d8936657SMaxime Ripard __func__, rxq_def); 2356c5aff182SThomas Petazzoni mvneta_cleanup_rxqs(pp); 2357c5aff182SThomas Petazzoni return err; 2358c5aff182SThomas Petazzoni } 2359c5aff182SThomas Petazzoni 2360c5aff182SThomas Petazzoni return 0; 2361c5aff182SThomas Petazzoni } 2362c5aff182SThomas Petazzoni 2363c5aff182SThomas Petazzoni /* Init all tx queues */ 2364c5aff182SThomas Petazzoni static int mvneta_setup_txqs(struct mvneta_port *pp) 2365c5aff182SThomas Petazzoni { 2366c5aff182SThomas Petazzoni int queue; 2367c5aff182SThomas Petazzoni 2368c5aff182SThomas Petazzoni for (queue = 0; queue < txq_number; queue++) { 2369c5aff182SThomas Petazzoni int err = mvneta_txq_init(pp, &pp->txqs[queue]); 2370c5aff182SThomas Petazzoni if (err) { 2371c5aff182SThomas Petazzoni netdev_err(pp->dev, "%s: can't create txq=%d\n", 2372c5aff182SThomas Petazzoni __func__, queue); 2373c5aff182SThomas Petazzoni mvneta_cleanup_txqs(pp); 2374c5aff182SThomas Petazzoni return err; 2375c5aff182SThomas Petazzoni } 2376c5aff182SThomas Petazzoni } 2377c5aff182SThomas Petazzoni 2378c5aff182SThomas Petazzoni return 0; 2379c5aff182SThomas Petazzoni } 2380c5aff182SThomas Petazzoni 2381c5aff182SThomas Petazzoni static void mvneta_start_dev(struct mvneta_port *pp) 2382c5aff182SThomas Petazzoni { 238312bb03b4SMaxime Ripard unsigned int cpu; 238412bb03b4SMaxime Ripard 2385c5aff182SThomas Petazzoni mvneta_max_rx_size_set(pp, pp->pkt_size); 2386c5aff182SThomas Petazzoni mvneta_txq_max_tx_size_set(pp, pp->pkt_size); 2387c5aff182SThomas Petazzoni 2388c5aff182SThomas Petazzoni /* start the Rx/Tx activity */ 2389c5aff182SThomas Petazzoni mvneta_port_enable(pp); 2390c5aff182SThomas Petazzoni 2391c5aff182SThomas Petazzoni /* Enable polling on the port */ 239212bb03b4SMaxime Ripard for_each_present_cpu(cpu) { 239312bb03b4SMaxime Ripard struct mvneta_pcpu_port *port = per_cpu_ptr(pp->ports, cpu); 239412bb03b4SMaxime Ripard 239512bb03b4SMaxime Ripard napi_enable(&port->napi); 239612bb03b4SMaxime Ripard } 2397c5aff182SThomas Petazzoni 2398c5aff182SThomas Petazzoni /* Unmask interrupts */ 2399c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_INTR_NEW_MASK, 2400898b2970SStas Sergeev MVNETA_RX_INTR_MASK(rxq_number) | 2401898b2970SStas Sergeev MVNETA_TX_INTR_MASK(txq_number) | 2402898b2970SStas Sergeev MVNETA_MISCINTR_INTR_MASK); 2403898b2970SStas Sergeev mvreg_write(pp, MVNETA_INTR_MISC_MASK, 2404898b2970SStas Sergeev MVNETA_CAUSE_PHY_STATUS_CHANGE | 2405898b2970SStas Sergeev MVNETA_CAUSE_LINK_CHANGE | 2406898b2970SStas Sergeev MVNETA_CAUSE_PSC_SYNC_CHANGE); 2407c5aff182SThomas Petazzoni 2408c5aff182SThomas Petazzoni phy_start(pp->phy_dev); 2409c5aff182SThomas Petazzoni netif_tx_start_all_queues(pp->dev); 2410c5aff182SThomas Petazzoni } 2411c5aff182SThomas Petazzoni 2412c5aff182SThomas Petazzoni static void mvneta_stop_dev(struct mvneta_port *pp) 2413c5aff182SThomas Petazzoni { 241412bb03b4SMaxime Ripard unsigned int cpu; 241512bb03b4SMaxime Ripard 2416c5aff182SThomas Petazzoni phy_stop(pp->phy_dev); 2417c5aff182SThomas Petazzoni 241812bb03b4SMaxime Ripard for_each_present_cpu(cpu) { 241912bb03b4SMaxime Ripard struct mvneta_pcpu_port *port = per_cpu_ptr(pp->ports, cpu); 242012bb03b4SMaxime Ripard 242112bb03b4SMaxime Ripard napi_disable(&port->napi); 242212bb03b4SMaxime Ripard } 2423c5aff182SThomas Petazzoni 2424c5aff182SThomas Petazzoni netif_carrier_off(pp->dev); 2425c5aff182SThomas Petazzoni 2426c5aff182SThomas Petazzoni mvneta_port_down(pp); 2427c5aff182SThomas Petazzoni netif_tx_stop_all_queues(pp->dev); 2428c5aff182SThomas Petazzoni 2429c5aff182SThomas Petazzoni /* Stop the port activity */ 2430c5aff182SThomas Petazzoni mvneta_port_disable(pp); 2431c5aff182SThomas Petazzoni 2432c5aff182SThomas Petazzoni /* Clear all ethernet port interrupts */ 2433c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_INTR_MISC_CAUSE, 0); 2434c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_INTR_OLD_CAUSE, 0); 2435c5aff182SThomas Petazzoni 2436c5aff182SThomas Petazzoni /* Mask all ethernet port interrupts */ 2437c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_INTR_NEW_MASK, 0); 2438c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_INTR_OLD_MASK, 0); 2439c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_INTR_MISC_MASK, 0); 2440c5aff182SThomas Petazzoni 2441c5aff182SThomas Petazzoni mvneta_tx_reset(pp); 2442c5aff182SThomas Petazzoni mvneta_rx_reset(pp); 2443c5aff182SThomas Petazzoni } 2444c5aff182SThomas Petazzoni 2445c5aff182SThomas Petazzoni /* Return positive if MTU is valid */ 2446c5aff182SThomas Petazzoni static int mvneta_check_mtu_valid(struct net_device *dev, int mtu) 2447c5aff182SThomas Petazzoni { 2448c5aff182SThomas Petazzoni if (mtu < 68) { 2449c5aff182SThomas Petazzoni netdev_err(dev, "cannot change mtu to less than 68\n"); 2450c5aff182SThomas Petazzoni return -EINVAL; 2451c5aff182SThomas Petazzoni } 2452c5aff182SThomas Petazzoni 2453c5aff182SThomas Petazzoni /* 9676 == 9700 - 20 and rounding to 8 */ 2454c5aff182SThomas Petazzoni if (mtu > 9676) { 2455c5aff182SThomas Petazzoni netdev_info(dev, "Illegal MTU value %d, round to 9676\n", mtu); 2456c5aff182SThomas Petazzoni mtu = 9676; 2457c5aff182SThomas Petazzoni } 2458c5aff182SThomas Petazzoni 2459c5aff182SThomas Petazzoni if (!IS_ALIGNED(MVNETA_RX_PKT_SIZE(mtu), 8)) { 2460c5aff182SThomas Petazzoni netdev_info(dev, "Illegal MTU value %d, rounding to %d\n", 2461c5aff182SThomas Petazzoni mtu, ALIGN(MVNETA_RX_PKT_SIZE(mtu), 8)); 2462c5aff182SThomas Petazzoni mtu = ALIGN(MVNETA_RX_PKT_SIZE(mtu), 8); 2463c5aff182SThomas Petazzoni } 2464c5aff182SThomas Petazzoni 2465c5aff182SThomas Petazzoni return mtu; 2466c5aff182SThomas Petazzoni } 2467c5aff182SThomas Petazzoni 2468c5aff182SThomas Petazzoni /* Change the device mtu */ 2469c5aff182SThomas Petazzoni static int mvneta_change_mtu(struct net_device *dev, int mtu) 2470c5aff182SThomas Petazzoni { 2471c5aff182SThomas Petazzoni struct mvneta_port *pp = netdev_priv(dev); 2472c5aff182SThomas Petazzoni int ret; 2473c5aff182SThomas Petazzoni 2474c5aff182SThomas Petazzoni mtu = mvneta_check_mtu_valid(dev, mtu); 2475c5aff182SThomas Petazzoni if (mtu < 0) 2476c5aff182SThomas Petazzoni return -EINVAL; 2477c5aff182SThomas Petazzoni 2478c5aff182SThomas Petazzoni dev->mtu = mtu; 2479c5aff182SThomas Petazzoni 2480b65657fcSSimon Guinot if (!netif_running(dev)) { 2481b65657fcSSimon Guinot netdev_update_features(dev); 2482c5aff182SThomas Petazzoni return 0; 2483b65657fcSSimon Guinot } 2484c5aff182SThomas Petazzoni 24856a20c175SThomas Petazzoni /* The interface is running, so we have to force a 2486a92dbd96SEzequiel Garcia * reallocation of the queues 2487c5aff182SThomas Petazzoni */ 2488c5aff182SThomas Petazzoni mvneta_stop_dev(pp); 2489c5aff182SThomas Petazzoni 2490c5aff182SThomas Petazzoni mvneta_cleanup_txqs(pp); 2491c5aff182SThomas Petazzoni mvneta_cleanup_rxqs(pp); 2492c5aff182SThomas Petazzoni 2493a92dbd96SEzequiel Garcia pp->pkt_size = MVNETA_RX_PKT_SIZE(dev->mtu); 24948ec2cd48Swilly tarreau pp->frag_size = SKB_DATA_ALIGN(MVNETA_RX_BUF_SIZE(pp->pkt_size)) + 24958ec2cd48Swilly tarreau SKB_DATA_ALIGN(sizeof(struct skb_shared_info)); 2496c5aff182SThomas Petazzoni 2497c5aff182SThomas Petazzoni ret = mvneta_setup_rxqs(pp); 2498c5aff182SThomas Petazzoni if (ret) { 2499a92dbd96SEzequiel Garcia netdev_err(dev, "unable to setup rxqs after MTU change\n"); 2500c5aff182SThomas Petazzoni return ret; 2501c5aff182SThomas Petazzoni } 2502c5aff182SThomas Petazzoni 2503a92dbd96SEzequiel Garcia ret = mvneta_setup_txqs(pp); 2504a92dbd96SEzequiel Garcia if (ret) { 2505a92dbd96SEzequiel Garcia netdev_err(dev, "unable to setup txqs after MTU change\n"); 2506a92dbd96SEzequiel Garcia return ret; 2507a92dbd96SEzequiel Garcia } 2508c5aff182SThomas Petazzoni 2509c5aff182SThomas Petazzoni mvneta_start_dev(pp); 2510c5aff182SThomas Petazzoni mvneta_port_up(pp); 2511c5aff182SThomas Petazzoni 2512b65657fcSSimon Guinot netdev_update_features(dev); 2513b65657fcSSimon Guinot 2514c5aff182SThomas Petazzoni return 0; 2515c5aff182SThomas Petazzoni } 2516c5aff182SThomas Petazzoni 2517b65657fcSSimon Guinot static netdev_features_t mvneta_fix_features(struct net_device *dev, 2518b65657fcSSimon Guinot netdev_features_t features) 2519b65657fcSSimon Guinot { 2520b65657fcSSimon Guinot struct mvneta_port *pp = netdev_priv(dev); 2521b65657fcSSimon Guinot 2522b65657fcSSimon Guinot if (pp->tx_csum_limit && dev->mtu > pp->tx_csum_limit) { 2523b65657fcSSimon Guinot features &= ~(NETIF_F_IP_CSUM | NETIF_F_TSO); 2524b65657fcSSimon Guinot netdev_info(dev, 2525b65657fcSSimon Guinot "Disable IP checksum for MTU greater than %dB\n", 2526b65657fcSSimon Guinot pp->tx_csum_limit); 2527b65657fcSSimon Guinot } 2528b65657fcSSimon Guinot 2529b65657fcSSimon Guinot return features; 2530b65657fcSSimon Guinot } 2531b65657fcSSimon Guinot 25328cc3e439SThomas Petazzoni /* Get mac address */ 25338cc3e439SThomas Petazzoni static void mvneta_get_mac_addr(struct mvneta_port *pp, unsigned char *addr) 25348cc3e439SThomas Petazzoni { 25358cc3e439SThomas Petazzoni u32 mac_addr_l, mac_addr_h; 25368cc3e439SThomas Petazzoni 25378cc3e439SThomas Petazzoni mac_addr_l = mvreg_read(pp, MVNETA_MAC_ADDR_LOW); 25388cc3e439SThomas Petazzoni mac_addr_h = mvreg_read(pp, MVNETA_MAC_ADDR_HIGH); 25398cc3e439SThomas Petazzoni addr[0] = (mac_addr_h >> 24) & 0xFF; 25408cc3e439SThomas Petazzoni addr[1] = (mac_addr_h >> 16) & 0xFF; 25418cc3e439SThomas Petazzoni addr[2] = (mac_addr_h >> 8) & 0xFF; 25428cc3e439SThomas Petazzoni addr[3] = mac_addr_h & 0xFF; 25438cc3e439SThomas Petazzoni addr[4] = (mac_addr_l >> 8) & 0xFF; 25448cc3e439SThomas Petazzoni addr[5] = mac_addr_l & 0xFF; 25458cc3e439SThomas Petazzoni } 25468cc3e439SThomas Petazzoni 2547c5aff182SThomas Petazzoni /* Handle setting mac address */ 2548c5aff182SThomas Petazzoni static int mvneta_set_mac_addr(struct net_device *dev, void *addr) 2549c5aff182SThomas Petazzoni { 2550c5aff182SThomas Petazzoni struct mvneta_port *pp = netdev_priv(dev); 2551e68de360SEzequiel Garcia struct sockaddr *sockaddr = addr; 2552e68de360SEzequiel Garcia int ret; 2553c5aff182SThomas Petazzoni 2554e68de360SEzequiel Garcia ret = eth_prepare_mac_addr_change(dev, addr); 2555e68de360SEzequiel Garcia if (ret < 0) 2556e68de360SEzequiel Garcia return ret; 2557c5aff182SThomas Petazzoni /* Remove previous address table entry */ 2558c5aff182SThomas Petazzoni mvneta_mac_addr_set(pp, dev->dev_addr, -1); 2559c5aff182SThomas Petazzoni 2560c5aff182SThomas Petazzoni /* Set new addr in hw */ 2561e68de360SEzequiel Garcia mvneta_mac_addr_set(pp, sockaddr->sa_data, rxq_def); 2562c5aff182SThomas Petazzoni 2563e68de360SEzequiel Garcia eth_commit_mac_addr_change(dev, addr); 2564c5aff182SThomas Petazzoni return 0; 2565c5aff182SThomas Petazzoni } 2566c5aff182SThomas Petazzoni 2567c5aff182SThomas Petazzoni static void mvneta_adjust_link(struct net_device *ndev) 2568c5aff182SThomas Petazzoni { 2569c5aff182SThomas Petazzoni struct mvneta_port *pp = netdev_priv(ndev); 2570c5aff182SThomas Petazzoni struct phy_device *phydev = pp->phy_dev; 2571c5aff182SThomas Petazzoni int status_change = 0; 2572c5aff182SThomas Petazzoni 2573c5aff182SThomas Petazzoni if (phydev->link) { 2574c5aff182SThomas Petazzoni if ((pp->speed != phydev->speed) || 2575c5aff182SThomas Petazzoni (pp->duplex != phydev->duplex)) { 2576c5aff182SThomas Petazzoni u32 val; 2577c5aff182SThomas Petazzoni 2578c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG); 2579c5aff182SThomas Petazzoni val &= ~(MVNETA_GMAC_CONFIG_MII_SPEED | 2580c5aff182SThomas Petazzoni MVNETA_GMAC_CONFIG_GMII_SPEED | 2581898b2970SStas Sergeev MVNETA_GMAC_CONFIG_FULL_DUPLEX); 2582c5aff182SThomas Petazzoni 2583c5aff182SThomas Petazzoni if (phydev->duplex) 2584c5aff182SThomas Petazzoni val |= MVNETA_GMAC_CONFIG_FULL_DUPLEX; 2585c5aff182SThomas Petazzoni 2586c5aff182SThomas Petazzoni if (phydev->speed == SPEED_1000) 2587c5aff182SThomas Petazzoni val |= MVNETA_GMAC_CONFIG_GMII_SPEED; 25884d12bc63SThomas Petazzoni else if (phydev->speed == SPEED_100) 2589c5aff182SThomas Petazzoni val |= MVNETA_GMAC_CONFIG_MII_SPEED; 2590c5aff182SThomas Petazzoni 2591c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val); 2592c5aff182SThomas Petazzoni 2593c5aff182SThomas Petazzoni pp->duplex = phydev->duplex; 2594c5aff182SThomas Petazzoni pp->speed = phydev->speed; 2595c5aff182SThomas Petazzoni } 2596c5aff182SThomas Petazzoni } 2597c5aff182SThomas Petazzoni 2598c5aff182SThomas Petazzoni if (phydev->link != pp->link) { 2599c5aff182SThomas Petazzoni if (!phydev->link) { 2600c5aff182SThomas Petazzoni pp->duplex = -1; 2601c5aff182SThomas Petazzoni pp->speed = 0; 2602c5aff182SThomas Petazzoni } 2603c5aff182SThomas Petazzoni 2604c5aff182SThomas Petazzoni pp->link = phydev->link; 2605c5aff182SThomas Petazzoni status_change = 1; 2606c5aff182SThomas Petazzoni } 2607c5aff182SThomas Petazzoni 2608c5aff182SThomas Petazzoni if (status_change) { 2609c5aff182SThomas Petazzoni if (phydev->link) { 2610898b2970SStas Sergeev if (!pp->use_inband_status) { 2611898b2970SStas Sergeev u32 val = mvreg_read(pp, 2612898b2970SStas Sergeev MVNETA_GMAC_AUTONEG_CONFIG); 2613898b2970SStas Sergeev val &= ~MVNETA_GMAC_FORCE_LINK_DOWN; 2614898b2970SStas Sergeev val |= MVNETA_GMAC_FORCE_LINK_PASS; 2615898b2970SStas Sergeev mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, 2616898b2970SStas Sergeev val); 2617898b2970SStas Sergeev } 2618c5aff182SThomas Petazzoni mvneta_port_up(pp); 2619c5aff182SThomas Petazzoni } else { 2620898b2970SStas Sergeev if (!pp->use_inband_status) { 2621898b2970SStas Sergeev u32 val = mvreg_read(pp, 2622898b2970SStas Sergeev MVNETA_GMAC_AUTONEG_CONFIG); 2623898b2970SStas Sergeev val &= ~MVNETA_GMAC_FORCE_LINK_PASS; 2624898b2970SStas Sergeev val |= MVNETA_GMAC_FORCE_LINK_DOWN; 2625898b2970SStas Sergeev mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, 2626898b2970SStas Sergeev val); 2627898b2970SStas Sergeev } 2628c5aff182SThomas Petazzoni mvneta_port_down(pp); 2629c5aff182SThomas Petazzoni } 26300089b745SEzequiel Garcia phy_print_status(phydev); 2631c5aff182SThomas Petazzoni } 2632c5aff182SThomas Petazzoni } 2633c5aff182SThomas Petazzoni 2634c5aff182SThomas Petazzoni static int mvneta_mdio_probe(struct mvneta_port *pp) 2635c5aff182SThomas Petazzoni { 2636c5aff182SThomas Petazzoni struct phy_device *phy_dev; 2637c5aff182SThomas Petazzoni 2638c5aff182SThomas Petazzoni phy_dev = of_phy_connect(pp->dev, pp->phy_node, mvneta_adjust_link, 0, 2639c5aff182SThomas Petazzoni pp->phy_interface); 2640c5aff182SThomas Petazzoni if (!phy_dev) { 2641c5aff182SThomas Petazzoni netdev_err(pp->dev, "could not find the PHY\n"); 2642c5aff182SThomas Petazzoni return -ENODEV; 2643c5aff182SThomas Petazzoni } 2644c5aff182SThomas Petazzoni 2645c5aff182SThomas Petazzoni phy_dev->supported &= PHY_GBIT_FEATURES; 2646c5aff182SThomas Petazzoni phy_dev->advertising = phy_dev->supported; 2647c5aff182SThomas Petazzoni 2648c5aff182SThomas Petazzoni pp->phy_dev = phy_dev; 2649c5aff182SThomas Petazzoni pp->link = 0; 2650c5aff182SThomas Petazzoni pp->duplex = 0; 2651c5aff182SThomas Petazzoni pp->speed = 0; 2652c5aff182SThomas Petazzoni 2653c5aff182SThomas Petazzoni return 0; 2654c5aff182SThomas Petazzoni } 2655c5aff182SThomas Petazzoni 2656c5aff182SThomas Petazzoni static void mvneta_mdio_remove(struct mvneta_port *pp) 2657c5aff182SThomas Petazzoni { 2658c5aff182SThomas Petazzoni phy_disconnect(pp->phy_dev); 2659c5aff182SThomas Petazzoni pp->phy_dev = NULL; 2660c5aff182SThomas Petazzoni } 2661c5aff182SThomas Petazzoni 2662f8642885SMaxime Ripard static void mvneta_percpu_enable(void *arg) 2663f8642885SMaxime Ripard { 2664f8642885SMaxime Ripard struct mvneta_port *pp = arg; 2665f8642885SMaxime Ripard 2666f8642885SMaxime Ripard enable_percpu_irq(pp->dev->irq, IRQ_TYPE_NONE); 2667f8642885SMaxime Ripard } 2668f8642885SMaxime Ripard 2669f8642885SMaxime Ripard static void mvneta_percpu_disable(void *arg) 2670f8642885SMaxime Ripard { 2671f8642885SMaxime Ripard struct mvneta_port *pp = arg; 2672f8642885SMaxime Ripard 2673f8642885SMaxime Ripard disable_percpu_irq(pp->dev->irq); 2674f8642885SMaxime Ripard } 2675f8642885SMaxime Ripard 2676f8642885SMaxime Ripard static void mvneta_percpu_elect(struct mvneta_port *pp) 2677f8642885SMaxime Ripard { 2678f8642885SMaxime Ripard int online_cpu_idx, cpu, i = 0; 2679f8642885SMaxime Ripard 2680f8642885SMaxime Ripard online_cpu_idx = rxq_def % num_online_cpus(); 2681f8642885SMaxime Ripard 2682f8642885SMaxime Ripard for_each_online_cpu(cpu) { 2683f8642885SMaxime Ripard if (i == online_cpu_idx) 2684f8642885SMaxime Ripard /* Enable per-CPU interrupt on the one CPU we 2685f8642885SMaxime Ripard * just elected 2686f8642885SMaxime Ripard */ 2687f8642885SMaxime Ripard smp_call_function_single(cpu, mvneta_percpu_enable, 2688f8642885SMaxime Ripard pp, true); 2689f8642885SMaxime Ripard else 2690f8642885SMaxime Ripard /* Disable per-CPU interrupt on all the other CPU */ 2691f8642885SMaxime Ripard smp_call_function_single(cpu, mvneta_percpu_disable, 2692f8642885SMaxime Ripard pp, true); 2693f8642885SMaxime Ripard i++; 2694f8642885SMaxime Ripard } 2695f8642885SMaxime Ripard }; 2696f8642885SMaxime Ripard 2697f8642885SMaxime Ripard static int mvneta_percpu_notifier(struct notifier_block *nfb, 2698f8642885SMaxime Ripard unsigned long action, void *hcpu) 2699f8642885SMaxime Ripard { 2700f8642885SMaxime Ripard struct mvneta_port *pp = container_of(nfb, struct mvneta_port, 2701f8642885SMaxime Ripard cpu_notifier); 2702f8642885SMaxime Ripard int cpu = (unsigned long)hcpu, other_cpu; 2703f8642885SMaxime Ripard struct mvneta_pcpu_port *port = per_cpu_ptr(pp->ports, cpu); 2704f8642885SMaxime Ripard 2705f8642885SMaxime Ripard switch (action) { 2706f8642885SMaxime Ripard case CPU_ONLINE: 2707f8642885SMaxime Ripard case CPU_ONLINE_FROZEN: 2708f8642885SMaxime Ripard netif_tx_stop_all_queues(pp->dev); 2709f8642885SMaxime Ripard 2710f8642885SMaxime Ripard /* We have to synchronise on tha napi of each CPU 2711f8642885SMaxime Ripard * except the one just being waked up 2712f8642885SMaxime Ripard */ 2713f8642885SMaxime Ripard for_each_online_cpu(other_cpu) { 2714f8642885SMaxime Ripard if (other_cpu != cpu) { 2715f8642885SMaxime Ripard struct mvneta_pcpu_port *other_port = 2716f8642885SMaxime Ripard per_cpu_ptr(pp->ports, other_cpu); 2717f8642885SMaxime Ripard 2718f8642885SMaxime Ripard napi_synchronize(&other_port->napi); 2719f8642885SMaxime Ripard } 2720f8642885SMaxime Ripard } 2721f8642885SMaxime Ripard 2722f8642885SMaxime Ripard /* Mask all ethernet port interrupts */ 2723f8642885SMaxime Ripard mvreg_write(pp, MVNETA_INTR_NEW_MASK, 0); 2724f8642885SMaxime Ripard mvreg_write(pp, MVNETA_INTR_OLD_MASK, 0); 2725f8642885SMaxime Ripard mvreg_write(pp, MVNETA_INTR_MISC_MASK, 0); 2726f8642885SMaxime Ripard napi_enable(&port->napi); 2727f8642885SMaxime Ripard 2728f8642885SMaxime Ripard /* Enable per-CPU interrupt on the one CPU we care 2729f8642885SMaxime Ripard * about. 2730f8642885SMaxime Ripard */ 2731f8642885SMaxime Ripard mvneta_percpu_elect(pp); 2732f8642885SMaxime Ripard 2733f8642885SMaxime Ripard /* Unmask all ethernet port interrupts */ 2734f8642885SMaxime Ripard mvreg_write(pp, MVNETA_INTR_NEW_MASK, 2735f8642885SMaxime Ripard MVNETA_RX_INTR_MASK(rxq_number) | 2736f8642885SMaxime Ripard MVNETA_TX_INTR_MASK(txq_number) | 2737f8642885SMaxime Ripard MVNETA_MISCINTR_INTR_MASK); 2738f8642885SMaxime Ripard mvreg_write(pp, MVNETA_INTR_MISC_MASK, 2739f8642885SMaxime Ripard MVNETA_CAUSE_PHY_STATUS_CHANGE | 2740f8642885SMaxime Ripard MVNETA_CAUSE_LINK_CHANGE | 2741f8642885SMaxime Ripard MVNETA_CAUSE_PSC_SYNC_CHANGE); 2742f8642885SMaxime Ripard netif_tx_start_all_queues(pp->dev); 2743f8642885SMaxime Ripard break; 2744f8642885SMaxime Ripard case CPU_DOWN_PREPARE: 2745f8642885SMaxime Ripard case CPU_DOWN_PREPARE_FROZEN: 2746f8642885SMaxime Ripard netif_tx_stop_all_queues(pp->dev); 2747f8642885SMaxime Ripard /* Mask all ethernet port interrupts */ 2748f8642885SMaxime Ripard mvreg_write(pp, MVNETA_INTR_NEW_MASK, 0); 2749f8642885SMaxime Ripard mvreg_write(pp, MVNETA_INTR_OLD_MASK, 0); 2750f8642885SMaxime Ripard mvreg_write(pp, MVNETA_INTR_MISC_MASK, 0); 2751f8642885SMaxime Ripard 2752f8642885SMaxime Ripard napi_synchronize(&port->napi); 2753f8642885SMaxime Ripard napi_disable(&port->napi); 2754f8642885SMaxime Ripard /* Disable per-CPU interrupts on the CPU that is 2755f8642885SMaxime Ripard * brought down. 2756f8642885SMaxime Ripard */ 2757f8642885SMaxime Ripard smp_call_function_single(cpu, mvneta_percpu_disable, 2758f8642885SMaxime Ripard pp, true); 2759f8642885SMaxime Ripard 2760f8642885SMaxime Ripard break; 2761f8642885SMaxime Ripard case CPU_DEAD: 2762f8642885SMaxime Ripard case CPU_DEAD_FROZEN: 2763f8642885SMaxime Ripard /* Check if a new CPU must be elected now this on is down */ 2764f8642885SMaxime Ripard mvneta_percpu_elect(pp); 2765f8642885SMaxime Ripard /* Unmask all ethernet port interrupts */ 2766f8642885SMaxime Ripard mvreg_write(pp, MVNETA_INTR_NEW_MASK, 2767f8642885SMaxime Ripard MVNETA_RX_INTR_MASK(rxq_number) | 2768f8642885SMaxime Ripard MVNETA_TX_INTR_MASK(txq_number) | 2769f8642885SMaxime Ripard MVNETA_MISCINTR_INTR_MASK); 2770f8642885SMaxime Ripard mvreg_write(pp, MVNETA_INTR_MISC_MASK, 2771f8642885SMaxime Ripard MVNETA_CAUSE_PHY_STATUS_CHANGE | 2772f8642885SMaxime Ripard MVNETA_CAUSE_LINK_CHANGE | 2773f8642885SMaxime Ripard MVNETA_CAUSE_PSC_SYNC_CHANGE); 2774f8642885SMaxime Ripard netif_tx_start_all_queues(pp->dev); 2775f8642885SMaxime Ripard break; 2776f8642885SMaxime Ripard } 2777f8642885SMaxime Ripard 2778f8642885SMaxime Ripard return NOTIFY_OK; 2779f8642885SMaxime Ripard } 2780f8642885SMaxime Ripard 2781c5aff182SThomas Petazzoni static int mvneta_open(struct net_device *dev) 2782c5aff182SThomas Petazzoni { 2783c5aff182SThomas Petazzoni struct mvneta_port *pp = netdev_priv(dev); 2784c5aff182SThomas Petazzoni int ret; 2785c5aff182SThomas Petazzoni 2786c5aff182SThomas Petazzoni pp->pkt_size = MVNETA_RX_PKT_SIZE(pp->dev->mtu); 27878ec2cd48Swilly tarreau pp->frag_size = SKB_DATA_ALIGN(MVNETA_RX_BUF_SIZE(pp->pkt_size)) + 27888ec2cd48Swilly tarreau SKB_DATA_ALIGN(sizeof(struct skb_shared_info)); 2789c5aff182SThomas Petazzoni 2790c5aff182SThomas Petazzoni ret = mvneta_setup_rxqs(pp); 2791c5aff182SThomas Petazzoni if (ret) 2792c5aff182SThomas Petazzoni return ret; 2793c5aff182SThomas Petazzoni 2794c5aff182SThomas Petazzoni ret = mvneta_setup_txqs(pp); 2795c5aff182SThomas Petazzoni if (ret) 2796c5aff182SThomas Petazzoni goto err_cleanup_rxqs; 2797c5aff182SThomas Petazzoni 2798c5aff182SThomas Petazzoni /* Connect to port interrupt line */ 279912bb03b4SMaxime Ripard ret = request_percpu_irq(pp->dev->irq, mvneta_isr, 280012bb03b4SMaxime Ripard MVNETA_DRIVER_NAME, pp->ports); 2801c5aff182SThomas Petazzoni if (ret) { 2802c5aff182SThomas Petazzoni netdev_err(pp->dev, "cannot request irq %d\n", pp->dev->irq); 2803c5aff182SThomas Petazzoni goto err_cleanup_txqs; 2804c5aff182SThomas Petazzoni } 2805c5aff182SThomas Petazzoni 2806f8642885SMaxime Ripard /* Even though the documentation says that request_percpu_irq 2807f8642885SMaxime Ripard * doesn't enable the interrupts automatically, it actually 2808f8642885SMaxime Ripard * does so on the local CPU. 2809f8642885SMaxime Ripard * 2810f8642885SMaxime Ripard * Make sure it's disabled. 2811f8642885SMaxime Ripard */ 2812f8642885SMaxime Ripard mvneta_percpu_disable(pp); 2813f8642885SMaxime Ripard 2814f8642885SMaxime Ripard /* Elect a CPU to handle our RX queue interrupt */ 2815f8642885SMaxime Ripard mvneta_percpu_elect(pp); 2816f8642885SMaxime Ripard 2817f8642885SMaxime Ripard /* Register a CPU notifier to handle the case where our CPU 2818f8642885SMaxime Ripard * might be taken offline. 2819f8642885SMaxime Ripard */ 2820f8642885SMaxime Ripard register_cpu_notifier(&pp->cpu_notifier); 2821f8642885SMaxime Ripard 2822c5aff182SThomas Petazzoni /* In default link is down */ 2823c5aff182SThomas Petazzoni netif_carrier_off(pp->dev); 2824c5aff182SThomas Petazzoni 2825c5aff182SThomas Petazzoni ret = mvneta_mdio_probe(pp); 2826c5aff182SThomas Petazzoni if (ret < 0) { 2827c5aff182SThomas Petazzoni netdev_err(dev, "cannot probe MDIO bus\n"); 2828c5aff182SThomas Petazzoni goto err_free_irq; 2829c5aff182SThomas Petazzoni } 2830c5aff182SThomas Petazzoni 2831c5aff182SThomas Petazzoni mvneta_start_dev(pp); 2832c5aff182SThomas Petazzoni 2833c5aff182SThomas Petazzoni return 0; 2834c5aff182SThomas Petazzoni 2835c5aff182SThomas Petazzoni err_free_irq: 283612bb03b4SMaxime Ripard free_percpu_irq(pp->dev->irq, pp->ports); 2837c5aff182SThomas Petazzoni err_cleanup_txqs: 2838c5aff182SThomas Petazzoni mvneta_cleanup_txqs(pp); 2839c5aff182SThomas Petazzoni err_cleanup_rxqs: 2840c5aff182SThomas Petazzoni mvneta_cleanup_rxqs(pp); 2841c5aff182SThomas Petazzoni return ret; 2842c5aff182SThomas Petazzoni } 2843c5aff182SThomas Petazzoni 2844c5aff182SThomas Petazzoni /* Stop the port, free port interrupt line */ 2845c5aff182SThomas Petazzoni static int mvneta_stop(struct net_device *dev) 2846c5aff182SThomas Petazzoni { 2847c5aff182SThomas Petazzoni struct mvneta_port *pp = netdev_priv(dev); 2848f8642885SMaxime Ripard int cpu; 2849c5aff182SThomas Petazzoni 2850c5aff182SThomas Petazzoni mvneta_stop_dev(pp); 2851c5aff182SThomas Petazzoni mvneta_mdio_remove(pp); 2852f8642885SMaxime Ripard unregister_cpu_notifier(&pp->cpu_notifier); 2853f8642885SMaxime Ripard for_each_present_cpu(cpu) 2854f8642885SMaxime Ripard smp_call_function_single(cpu, mvneta_percpu_disable, pp, true); 285512bb03b4SMaxime Ripard free_percpu_irq(dev->irq, pp->ports); 2856c5aff182SThomas Petazzoni mvneta_cleanup_rxqs(pp); 2857c5aff182SThomas Petazzoni mvneta_cleanup_txqs(pp); 2858c5aff182SThomas Petazzoni 2859c5aff182SThomas Petazzoni return 0; 2860c5aff182SThomas Petazzoni } 2861c5aff182SThomas Petazzoni 286215f59456SThomas Petazzoni static int mvneta_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) 286315f59456SThomas Petazzoni { 286415f59456SThomas Petazzoni struct mvneta_port *pp = netdev_priv(dev); 286515f59456SThomas Petazzoni 286615f59456SThomas Petazzoni if (!pp->phy_dev) 286715f59456SThomas Petazzoni return -ENOTSUPP; 286815f59456SThomas Petazzoni 2869ecf7b361SStas Sergeev return phy_mii_ioctl(pp->phy_dev, ifr, cmd); 287015f59456SThomas Petazzoni } 287115f59456SThomas Petazzoni 2872c5aff182SThomas Petazzoni /* Ethtool methods */ 2873c5aff182SThomas Petazzoni 2874c5aff182SThomas Petazzoni /* Get settings (phy address, speed) for ethtools */ 2875c5aff182SThomas Petazzoni int mvneta_ethtool_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) 2876c5aff182SThomas Petazzoni { 2877c5aff182SThomas Petazzoni struct mvneta_port *pp = netdev_priv(dev); 2878c5aff182SThomas Petazzoni 2879c5aff182SThomas Petazzoni if (!pp->phy_dev) 2880c5aff182SThomas Petazzoni return -ENODEV; 2881c5aff182SThomas Petazzoni 2882c5aff182SThomas Petazzoni return phy_ethtool_gset(pp->phy_dev, cmd); 2883c5aff182SThomas Petazzoni } 2884c5aff182SThomas Petazzoni 2885c5aff182SThomas Petazzoni /* Set settings (phy address, speed) for ethtools */ 2886c5aff182SThomas Petazzoni int mvneta_ethtool_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) 2887c5aff182SThomas Petazzoni { 2888c5aff182SThomas Petazzoni struct mvneta_port *pp = netdev_priv(dev); 2889c5aff182SThomas Petazzoni 2890c5aff182SThomas Petazzoni if (!pp->phy_dev) 2891c5aff182SThomas Petazzoni return -ENODEV; 2892c5aff182SThomas Petazzoni 2893c5aff182SThomas Petazzoni return phy_ethtool_sset(pp->phy_dev, cmd); 2894c5aff182SThomas Petazzoni } 2895c5aff182SThomas Petazzoni 2896c5aff182SThomas Petazzoni /* Set interrupt coalescing for ethtools */ 2897c5aff182SThomas Petazzoni static int mvneta_ethtool_set_coalesce(struct net_device *dev, 2898c5aff182SThomas Petazzoni struct ethtool_coalesce *c) 2899c5aff182SThomas Petazzoni { 2900c5aff182SThomas Petazzoni struct mvneta_port *pp = netdev_priv(dev); 2901c5aff182SThomas Petazzoni int queue; 2902c5aff182SThomas Petazzoni 2903c5aff182SThomas Petazzoni for (queue = 0; queue < rxq_number; queue++) { 2904c5aff182SThomas Petazzoni struct mvneta_rx_queue *rxq = &pp->rxqs[queue]; 2905c5aff182SThomas Petazzoni rxq->time_coal = c->rx_coalesce_usecs; 2906c5aff182SThomas Petazzoni rxq->pkts_coal = c->rx_max_coalesced_frames; 2907c5aff182SThomas Petazzoni mvneta_rx_pkts_coal_set(pp, rxq, rxq->pkts_coal); 2908c5aff182SThomas Petazzoni mvneta_rx_time_coal_set(pp, rxq, rxq->time_coal); 2909c5aff182SThomas Petazzoni } 2910c5aff182SThomas Petazzoni 2911c5aff182SThomas Petazzoni for (queue = 0; queue < txq_number; queue++) { 2912c5aff182SThomas Petazzoni struct mvneta_tx_queue *txq = &pp->txqs[queue]; 2913c5aff182SThomas Petazzoni txq->done_pkts_coal = c->tx_max_coalesced_frames; 2914c5aff182SThomas Petazzoni mvneta_tx_done_pkts_coal_set(pp, txq, txq->done_pkts_coal); 2915c5aff182SThomas Petazzoni } 2916c5aff182SThomas Petazzoni 2917c5aff182SThomas Petazzoni return 0; 2918c5aff182SThomas Petazzoni } 2919c5aff182SThomas Petazzoni 2920c5aff182SThomas Petazzoni /* get coalescing for ethtools */ 2921c5aff182SThomas Petazzoni static int mvneta_ethtool_get_coalesce(struct net_device *dev, 2922c5aff182SThomas Petazzoni struct ethtool_coalesce *c) 2923c5aff182SThomas Petazzoni { 2924c5aff182SThomas Petazzoni struct mvneta_port *pp = netdev_priv(dev); 2925c5aff182SThomas Petazzoni 2926c5aff182SThomas Petazzoni c->rx_coalesce_usecs = pp->rxqs[0].time_coal; 2927c5aff182SThomas Petazzoni c->rx_max_coalesced_frames = pp->rxqs[0].pkts_coal; 2928c5aff182SThomas Petazzoni 2929c5aff182SThomas Petazzoni c->tx_max_coalesced_frames = pp->txqs[0].done_pkts_coal; 2930c5aff182SThomas Petazzoni return 0; 2931c5aff182SThomas Petazzoni } 2932c5aff182SThomas Petazzoni 2933c5aff182SThomas Petazzoni 2934c5aff182SThomas Petazzoni static void mvneta_ethtool_get_drvinfo(struct net_device *dev, 2935c5aff182SThomas Petazzoni struct ethtool_drvinfo *drvinfo) 2936c5aff182SThomas Petazzoni { 2937c5aff182SThomas Petazzoni strlcpy(drvinfo->driver, MVNETA_DRIVER_NAME, 2938c5aff182SThomas Petazzoni sizeof(drvinfo->driver)); 2939c5aff182SThomas Petazzoni strlcpy(drvinfo->version, MVNETA_DRIVER_VERSION, 2940c5aff182SThomas Petazzoni sizeof(drvinfo->version)); 2941c5aff182SThomas Petazzoni strlcpy(drvinfo->bus_info, dev_name(&dev->dev), 2942c5aff182SThomas Petazzoni sizeof(drvinfo->bus_info)); 2943c5aff182SThomas Petazzoni } 2944c5aff182SThomas Petazzoni 2945c5aff182SThomas Petazzoni 2946c5aff182SThomas Petazzoni static void mvneta_ethtool_get_ringparam(struct net_device *netdev, 2947c5aff182SThomas Petazzoni struct ethtool_ringparam *ring) 2948c5aff182SThomas Petazzoni { 2949c5aff182SThomas Petazzoni struct mvneta_port *pp = netdev_priv(netdev); 2950c5aff182SThomas Petazzoni 2951c5aff182SThomas Petazzoni ring->rx_max_pending = MVNETA_MAX_RXD; 2952c5aff182SThomas Petazzoni ring->tx_max_pending = MVNETA_MAX_TXD; 2953c5aff182SThomas Petazzoni ring->rx_pending = pp->rx_ring_size; 2954c5aff182SThomas Petazzoni ring->tx_pending = pp->tx_ring_size; 2955c5aff182SThomas Petazzoni } 2956c5aff182SThomas Petazzoni 2957c5aff182SThomas Petazzoni static int mvneta_ethtool_set_ringparam(struct net_device *dev, 2958c5aff182SThomas Petazzoni struct ethtool_ringparam *ring) 2959c5aff182SThomas Petazzoni { 2960c5aff182SThomas Petazzoni struct mvneta_port *pp = netdev_priv(dev); 2961c5aff182SThomas Petazzoni 2962c5aff182SThomas Petazzoni if ((ring->rx_pending == 0) || (ring->tx_pending == 0)) 2963c5aff182SThomas Petazzoni return -EINVAL; 2964c5aff182SThomas Petazzoni pp->rx_ring_size = ring->rx_pending < MVNETA_MAX_RXD ? 2965c5aff182SThomas Petazzoni ring->rx_pending : MVNETA_MAX_RXD; 29668eef5f97SEzequiel Garcia 29678eef5f97SEzequiel Garcia pp->tx_ring_size = clamp_t(u16, ring->tx_pending, 29688eef5f97SEzequiel Garcia MVNETA_MAX_SKB_DESCS * 2, MVNETA_MAX_TXD); 29698eef5f97SEzequiel Garcia if (pp->tx_ring_size != ring->tx_pending) 29708eef5f97SEzequiel Garcia netdev_warn(dev, "TX queue size set to %u (requested %u)\n", 29718eef5f97SEzequiel Garcia pp->tx_ring_size, ring->tx_pending); 2972c5aff182SThomas Petazzoni 2973c5aff182SThomas Petazzoni if (netif_running(dev)) { 2974c5aff182SThomas Petazzoni mvneta_stop(dev); 2975c5aff182SThomas Petazzoni if (mvneta_open(dev)) { 2976c5aff182SThomas Petazzoni netdev_err(dev, 2977c5aff182SThomas Petazzoni "error on opening device after ring param change\n"); 2978c5aff182SThomas Petazzoni return -ENOMEM; 2979c5aff182SThomas Petazzoni } 2980c5aff182SThomas Petazzoni } 2981c5aff182SThomas Petazzoni 2982c5aff182SThomas Petazzoni return 0; 2983c5aff182SThomas Petazzoni } 2984c5aff182SThomas Petazzoni 2985c5aff182SThomas Petazzoni static const struct net_device_ops mvneta_netdev_ops = { 2986c5aff182SThomas Petazzoni .ndo_open = mvneta_open, 2987c5aff182SThomas Petazzoni .ndo_stop = mvneta_stop, 2988c5aff182SThomas Petazzoni .ndo_start_xmit = mvneta_tx, 2989c5aff182SThomas Petazzoni .ndo_set_rx_mode = mvneta_set_rx_mode, 2990c5aff182SThomas Petazzoni .ndo_set_mac_address = mvneta_set_mac_addr, 2991c5aff182SThomas Petazzoni .ndo_change_mtu = mvneta_change_mtu, 2992b65657fcSSimon Guinot .ndo_fix_features = mvneta_fix_features, 2993c5aff182SThomas Petazzoni .ndo_get_stats64 = mvneta_get_stats64, 299415f59456SThomas Petazzoni .ndo_do_ioctl = mvneta_ioctl, 2995c5aff182SThomas Petazzoni }; 2996c5aff182SThomas Petazzoni 2997c5aff182SThomas Petazzoni const struct ethtool_ops mvneta_eth_tool_ops = { 2998c5aff182SThomas Petazzoni .get_link = ethtool_op_get_link, 2999c5aff182SThomas Petazzoni .get_settings = mvneta_ethtool_get_settings, 3000c5aff182SThomas Petazzoni .set_settings = mvneta_ethtool_set_settings, 3001c5aff182SThomas Petazzoni .set_coalesce = mvneta_ethtool_set_coalesce, 3002c5aff182SThomas Petazzoni .get_coalesce = mvneta_ethtool_get_coalesce, 3003c5aff182SThomas Petazzoni .get_drvinfo = mvneta_ethtool_get_drvinfo, 3004c5aff182SThomas Petazzoni .get_ringparam = mvneta_ethtool_get_ringparam, 3005c5aff182SThomas Petazzoni .set_ringparam = mvneta_ethtool_set_ringparam, 3006c5aff182SThomas Petazzoni }; 3007c5aff182SThomas Petazzoni 3008c5aff182SThomas Petazzoni /* Initialize hw */ 30099672850bSEzequiel Garcia static int mvneta_init(struct device *dev, struct mvneta_port *pp) 3010c5aff182SThomas Petazzoni { 3011c5aff182SThomas Petazzoni int queue; 3012c5aff182SThomas Petazzoni 3013c5aff182SThomas Petazzoni /* Disable port */ 3014c5aff182SThomas Petazzoni mvneta_port_disable(pp); 3015c5aff182SThomas Petazzoni 3016c5aff182SThomas Petazzoni /* Set port default values */ 3017c5aff182SThomas Petazzoni mvneta_defaults_set(pp); 3018c5aff182SThomas Petazzoni 30199672850bSEzequiel Garcia pp->txqs = devm_kcalloc(dev, txq_number, sizeof(struct mvneta_tx_queue), 3020c5aff182SThomas Petazzoni GFP_KERNEL); 3021c5aff182SThomas Petazzoni if (!pp->txqs) 3022c5aff182SThomas Petazzoni return -ENOMEM; 3023c5aff182SThomas Petazzoni 3024c5aff182SThomas Petazzoni /* Initialize TX descriptor rings */ 3025c5aff182SThomas Petazzoni for (queue = 0; queue < txq_number; queue++) { 3026c5aff182SThomas Petazzoni struct mvneta_tx_queue *txq = &pp->txqs[queue]; 3027c5aff182SThomas Petazzoni txq->id = queue; 3028c5aff182SThomas Petazzoni txq->size = pp->tx_ring_size; 3029c5aff182SThomas Petazzoni txq->done_pkts_coal = MVNETA_TXDONE_COAL_PKTS; 3030c5aff182SThomas Petazzoni } 3031c5aff182SThomas Petazzoni 30329672850bSEzequiel Garcia pp->rxqs = devm_kcalloc(dev, rxq_number, sizeof(struct mvneta_rx_queue), 3033c5aff182SThomas Petazzoni GFP_KERNEL); 30349672850bSEzequiel Garcia if (!pp->rxqs) 3035c5aff182SThomas Petazzoni return -ENOMEM; 3036c5aff182SThomas Petazzoni 3037c5aff182SThomas Petazzoni /* Create Rx descriptor rings */ 3038c5aff182SThomas Petazzoni for (queue = 0; queue < rxq_number; queue++) { 3039c5aff182SThomas Petazzoni struct mvneta_rx_queue *rxq = &pp->rxqs[queue]; 3040c5aff182SThomas Petazzoni rxq->id = queue; 3041c5aff182SThomas Petazzoni rxq->size = pp->rx_ring_size; 3042c5aff182SThomas Petazzoni rxq->pkts_coal = MVNETA_RX_COAL_PKTS; 3043c5aff182SThomas Petazzoni rxq->time_coal = MVNETA_RX_COAL_USEC; 3044c5aff182SThomas Petazzoni } 3045c5aff182SThomas Petazzoni 3046c5aff182SThomas Petazzoni return 0; 3047c5aff182SThomas Petazzoni } 3048c5aff182SThomas Petazzoni 3049c5aff182SThomas Petazzoni /* platform glue : initialize decoding windows */ 305003ce758eSGreg KH static void mvneta_conf_mbus_windows(struct mvneta_port *pp, 3051c5aff182SThomas Petazzoni const struct mbus_dram_target_info *dram) 3052c5aff182SThomas Petazzoni { 3053c5aff182SThomas Petazzoni u32 win_enable; 3054c5aff182SThomas Petazzoni u32 win_protect; 3055c5aff182SThomas Petazzoni int i; 3056c5aff182SThomas Petazzoni 3057c5aff182SThomas Petazzoni for (i = 0; i < 6; i++) { 3058c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_WIN_BASE(i), 0); 3059c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_WIN_SIZE(i), 0); 3060c5aff182SThomas Petazzoni 3061c5aff182SThomas Petazzoni if (i < 4) 3062c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_WIN_REMAP(i), 0); 3063c5aff182SThomas Petazzoni } 3064c5aff182SThomas Petazzoni 3065c5aff182SThomas Petazzoni win_enable = 0x3f; 3066c5aff182SThomas Petazzoni win_protect = 0; 3067c5aff182SThomas Petazzoni 3068c5aff182SThomas Petazzoni for (i = 0; i < dram->num_cs; i++) { 3069c5aff182SThomas Petazzoni const struct mbus_dram_window *cs = dram->cs + i; 3070c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_WIN_BASE(i), (cs->base & 0xffff0000) | 3071c5aff182SThomas Petazzoni (cs->mbus_attr << 8) | dram->mbus_dram_target_id); 3072c5aff182SThomas Petazzoni 3073c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_WIN_SIZE(i), 3074c5aff182SThomas Petazzoni (cs->size - 1) & 0xffff0000); 3075c5aff182SThomas Petazzoni 3076c5aff182SThomas Petazzoni win_enable &= ~(1 << i); 3077c5aff182SThomas Petazzoni win_protect |= 3 << (2 * i); 3078c5aff182SThomas Petazzoni } 3079c5aff182SThomas Petazzoni 3080c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_BASE_ADDR_ENABLE, win_enable); 3081c5aff182SThomas Petazzoni } 3082c5aff182SThomas Petazzoni 3083c5aff182SThomas Petazzoni /* Power up the port */ 30843f1dd4bcSThomas Petazzoni static int mvneta_port_power_up(struct mvneta_port *pp, int phy_mode) 3085c5aff182SThomas Petazzoni { 30863f1dd4bcSThomas Petazzoni u32 ctrl; 3087c5aff182SThomas Petazzoni 3088c5aff182SThomas Petazzoni /* MAC Cause register should be cleared */ 3089c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_UNIT_INTR_CAUSE, 0); 3090c5aff182SThomas Petazzoni 30913f1dd4bcSThomas Petazzoni ctrl = mvreg_read(pp, MVNETA_GMAC_CTRL_2); 3092c5aff182SThomas Petazzoni 30933f1dd4bcSThomas Petazzoni /* Even though it might look weird, when we're configured in 30943f1dd4bcSThomas Petazzoni * SGMII or QSGMII mode, the RGMII bit needs to be set. 30953f1dd4bcSThomas Petazzoni */ 30963f1dd4bcSThomas Petazzoni switch(phy_mode) { 30973f1dd4bcSThomas Petazzoni case PHY_INTERFACE_MODE_QSGMII: 30983f1dd4bcSThomas Petazzoni mvreg_write(pp, MVNETA_SERDES_CFG, MVNETA_QSGMII_SERDES_PROTO); 30993f1dd4bcSThomas Petazzoni ctrl |= MVNETA_GMAC2_PCS_ENABLE | MVNETA_GMAC2_PORT_RGMII; 31003f1dd4bcSThomas Petazzoni break; 31013f1dd4bcSThomas Petazzoni case PHY_INTERFACE_MODE_SGMII: 31023f1dd4bcSThomas Petazzoni mvreg_write(pp, MVNETA_SERDES_CFG, MVNETA_SGMII_SERDES_PROTO); 31033f1dd4bcSThomas Petazzoni ctrl |= MVNETA_GMAC2_PCS_ENABLE | MVNETA_GMAC2_PORT_RGMII; 31043f1dd4bcSThomas Petazzoni break; 31053f1dd4bcSThomas Petazzoni case PHY_INTERFACE_MODE_RGMII: 31063f1dd4bcSThomas Petazzoni case PHY_INTERFACE_MODE_RGMII_ID: 31073f1dd4bcSThomas Petazzoni ctrl |= MVNETA_GMAC2_PORT_RGMII; 31083f1dd4bcSThomas Petazzoni break; 31093f1dd4bcSThomas Petazzoni default: 31103f1dd4bcSThomas Petazzoni return -EINVAL; 31113f1dd4bcSThomas Petazzoni } 3112c5aff182SThomas Petazzoni 3113898b2970SStas Sergeev if (pp->use_inband_status) 3114898b2970SStas Sergeev ctrl |= MVNETA_GMAC2_INBAND_AN_ENABLE; 3115898b2970SStas Sergeev 3116c5aff182SThomas Petazzoni /* Cancel Port Reset */ 31173f1dd4bcSThomas Petazzoni ctrl &= ~MVNETA_GMAC2_PORT_RESET; 31183f1dd4bcSThomas Petazzoni mvreg_write(pp, MVNETA_GMAC_CTRL_2, ctrl); 3119c5aff182SThomas Petazzoni 3120c5aff182SThomas Petazzoni while ((mvreg_read(pp, MVNETA_GMAC_CTRL_2) & 3121c5aff182SThomas Petazzoni MVNETA_GMAC2_PORT_RESET) != 0) 3122c5aff182SThomas Petazzoni continue; 31233f1dd4bcSThomas Petazzoni 31243f1dd4bcSThomas Petazzoni return 0; 3125c5aff182SThomas Petazzoni } 3126c5aff182SThomas Petazzoni 3127c5aff182SThomas Petazzoni /* Device initialization routine */ 312803ce758eSGreg KH static int mvneta_probe(struct platform_device *pdev) 3129c5aff182SThomas Petazzoni { 3130c5aff182SThomas Petazzoni const struct mbus_dram_target_info *dram_target_info; 3131c3f0dd38SThomas Petazzoni struct resource *res; 3132c5aff182SThomas Petazzoni struct device_node *dn = pdev->dev.of_node; 3133c5aff182SThomas Petazzoni struct device_node *phy_node; 3134c5aff182SThomas Petazzoni struct mvneta_port *pp; 3135c5aff182SThomas Petazzoni struct net_device *dev; 31368cc3e439SThomas Petazzoni const char *dt_mac_addr; 31378cc3e439SThomas Petazzoni char hw_mac_addr[ETH_ALEN]; 31388cc3e439SThomas Petazzoni const char *mac_from; 3139f8af8e6eSStas Sergeev const char *managed; 3140c5aff182SThomas Petazzoni int phy_mode; 3141c5aff182SThomas Petazzoni int err; 314212bb03b4SMaxime Ripard int cpu; 3143c5aff182SThomas Petazzoni 3144ee40a116SWilly Tarreau dev = alloc_etherdev_mqs(sizeof(struct mvneta_port), txq_number, rxq_number); 3145c5aff182SThomas Petazzoni if (!dev) 3146c5aff182SThomas Petazzoni return -ENOMEM; 3147c5aff182SThomas Petazzoni 3148c5aff182SThomas Petazzoni dev->irq = irq_of_parse_and_map(dn, 0); 3149c5aff182SThomas Petazzoni if (dev->irq == 0) { 3150c5aff182SThomas Petazzoni err = -EINVAL; 3151c5aff182SThomas Petazzoni goto err_free_netdev; 3152c5aff182SThomas Petazzoni } 3153c5aff182SThomas Petazzoni 3154c5aff182SThomas Petazzoni phy_node = of_parse_phandle(dn, "phy", 0); 3155c5aff182SThomas Petazzoni if (!phy_node) { 315683895bedSThomas Petazzoni if (!of_phy_is_fixed_link(dn)) { 315783895bedSThomas Petazzoni dev_err(&pdev->dev, "no PHY specified\n"); 3158c5aff182SThomas Petazzoni err = -ENODEV; 3159c5aff182SThomas Petazzoni goto err_free_irq; 3160c5aff182SThomas Petazzoni } 3161c5aff182SThomas Petazzoni 316283895bedSThomas Petazzoni err = of_phy_register_fixed_link(dn); 316383895bedSThomas Petazzoni if (err < 0) { 316483895bedSThomas Petazzoni dev_err(&pdev->dev, "cannot register fixed PHY\n"); 316583895bedSThomas Petazzoni goto err_free_irq; 316683895bedSThomas Petazzoni } 316783895bedSThomas Petazzoni 316883895bedSThomas Petazzoni /* In the case of a fixed PHY, the DT node associated 316983895bedSThomas Petazzoni * to the PHY is the Ethernet MAC DT node. 317083895bedSThomas Petazzoni */ 3171c891c24cSUwe Kleine-König phy_node = of_node_get(dn); 317283895bedSThomas Petazzoni } 317383895bedSThomas Petazzoni 3174c5aff182SThomas Petazzoni phy_mode = of_get_phy_mode(dn); 3175c5aff182SThomas Petazzoni if (phy_mode < 0) { 3176c5aff182SThomas Petazzoni dev_err(&pdev->dev, "incorrect phy-mode\n"); 3177c5aff182SThomas Petazzoni err = -EINVAL; 3178c891c24cSUwe Kleine-König goto err_put_phy_node; 3179c5aff182SThomas Petazzoni } 3180c5aff182SThomas Petazzoni 3181c5aff182SThomas Petazzoni dev->tx_queue_len = MVNETA_MAX_TXD; 3182c5aff182SThomas Petazzoni dev->watchdog_timeo = 5 * HZ; 3183c5aff182SThomas Petazzoni dev->netdev_ops = &mvneta_netdev_ops; 3184c5aff182SThomas Petazzoni 31857ad24ea4SWilfried Klaebe dev->ethtool_ops = &mvneta_eth_tool_ops; 3186c5aff182SThomas Petazzoni 3187c5aff182SThomas Petazzoni pp = netdev_priv(dev); 3188c5aff182SThomas Petazzoni pp->phy_node = phy_node; 3189c5aff182SThomas Petazzoni pp->phy_interface = phy_mode; 3190f8af8e6eSStas Sergeev 3191f8af8e6eSStas Sergeev err = of_property_read_string(dn, "managed", &managed); 3192f8af8e6eSStas Sergeev pp->use_inband_status = (err == 0 && 3193f8af8e6eSStas Sergeev strcmp(managed, "in-band-status") == 0); 3194f8642885SMaxime Ripard pp->cpu_notifier.notifier_call = mvneta_percpu_notifier; 3195c5aff182SThomas Petazzoni 3196189dd626SThomas Petazzoni pp->clk = devm_clk_get(&pdev->dev, NULL); 3197189dd626SThomas Petazzoni if (IS_ERR(pp->clk)) { 3198189dd626SThomas Petazzoni err = PTR_ERR(pp->clk); 3199c891c24cSUwe Kleine-König goto err_put_phy_node; 3200189dd626SThomas Petazzoni } 3201189dd626SThomas Petazzoni 3202189dd626SThomas Petazzoni clk_prepare_enable(pp->clk); 3203189dd626SThomas Petazzoni 3204c3f0dd38SThomas Petazzoni res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 3205c3f0dd38SThomas Petazzoni pp->base = devm_ioremap_resource(&pdev->dev, res); 3206c3f0dd38SThomas Petazzoni if (IS_ERR(pp->base)) { 3207c3f0dd38SThomas Petazzoni err = PTR_ERR(pp->base); 32085445eaf3SArnaud Patard \(Rtp\) goto err_clk; 32095445eaf3SArnaud Patard \(Rtp\) } 32105445eaf3SArnaud Patard \(Rtp\) 321112bb03b4SMaxime Ripard /* Alloc per-cpu port structure */ 321212bb03b4SMaxime Ripard pp->ports = alloc_percpu(struct mvneta_pcpu_port); 321312bb03b4SMaxime Ripard if (!pp->ports) { 321412bb03b4SMaxime Ripard err = -ENOMEM; 321512bb03b4SMaxime Ripard goto err_clk; 321612bb03b4SMaxime Ripard } 321712bb03b4SMaxime Ripard 321874c41b04Swilly tarreau /* Alloc per-cpu stats */ 32191c213bd2SWANG Cong pp->stats = netdev_alloc_pcpu_stats(struct mvneta_pcpu_stats); 322074c41b04Swilly tarreau if (!pp->stats) { 322174c41b04Swilly tarreau err = -ENOMEM; 322212bb03b4SMaxime Ripard goto err_free_ports; 322374c41b04Swilly tarreau } 322474c41b04Swilly tarreau 32258cc3e439SThomas Petazzoni dt_mac_addr = of_get_mac_address(dn); 32266c7a9a3cSLuka Perkov if (dt_mac_addr) { 32278cc3e439SThomas Petazzoni mac_from = "device tree"; 32288cc3e439SThomas Petazzoni memcpy(dev->dev_addr, dt_mac_addr, ETH_ALEN); 32298cc3e439SThomas Petazzoni } else { 32308cc3e439SThomas Petazzoni mvneta_get_mac_addr(pp, hw_mac_addr); 32318cc3e439SThomas Petazzoni if (is_valid_ether_addr(hw_mac_addr)) { 32328cc3e439SThomas Petazzoni mac_from = "hardware"; 32338cc3e439SThomas Petazzoni memcpy(dev->dev_addr, hw_mac_addr, ETH_ALEN); 32348cc3e439SThomas Petazzoni } else { 32358cc3e439SThomas Petazzoni mac_from = "random"; 32368cc3e439SThomas Petazzoni eth_hw_addr_random(dev); 32378cc3e439SThomas Petazzoni } 32388cc3e439SThomas Petazzoni } 32398cc3e439SThomas Petazzoni 3240b65657fcSSimon Guinot if (of_device_is_compatible(dn, "marvell,armada-370-neta")) 3241b65657fcSSimon Guinot pp->tx_csum_limit = 1600; 3242b65657fcSSimon Guinot 3243c5aff182SThomas Petazzoni pp->tx_ring_size = MVNETA_MAX_TXD; 3244c5aff182SThomas Petazzoni pp->rx_ring_size = MVNETA_MAX_RXD; 3245c5aff182SThomas Petazzoni 3246c5aff182SThomas Petazzoni pp->dev = dev; 3247c5aff182SThomas Petazzoni SET_NETDEV_DEV(dev, &pdev->dev); 3248c5aff182SThomas Petazzoni 32499672850bSEzequiel Garcia err = mvneta_init(&pdev->dev, pp); 32509672850bSEzequiel Garcia if (err < 0) 325174c41b04Swilly tarreau goto err_free_stats; 32523f1dd4bcSThomas Petazzoni 32533f1dd4bcSThomas Petazzoni err = mvneta_port_power_up(pp, phy_mode); 32543f1dd4bcSThomas Petazzoni if (err < 0) { 32553f1dd4bcSThomas Petazzoni dev_err(&pdev->dev, "can't power up port\n"); 32569672850bSEzequiel Garcia goto err_free_stats; 32573f1dd4bcSThomas Petazzoni } 3258c5aff182SThomas Petazzoni 3259c5aff182SThomas Petazzoni dram_target_info = mv_mbus_dram_info(); 3260c5aff182SThomas Petazzoni if (dram_target_info) 3261c5aff182SThomas Petazzoni mvneta_conf_mbus_windows(pp, dram_target_info); 3262c5aff182SThomas Petazzoni 326312bb03b4SMaxime Ripard for_each_present_cpu(cpu) { 326412bb03b4SMaxime Ripard struct mvneta_pcpu_port *port = per_cpu_ptr(pp->ports, cpu); 326512bb03b4SMaxime Ripard 326612bb03b4SMaxime Ripard netif_napi_add(dev, &port->napi, mvneta_poll, NAPI_POLL_WEIGHT); 326712bb03b4SMaxime Ripard port->pp = pp; 326812bb03b4SMaxime Ripard } 3269c5aff182SThomas Petazzoni 32702adb719dSEzequiel Garcia dev->features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO; 327101ef26caSEzequiel Garcia dev->hw_features |= dev->features; 327201ef26caSEzequiel Garcia dev->vlan_features |= dev->features; 3273b50b72deSwilly tarreau dev->priv_flags |= IFF_UNICAST_FLT; 32748eef5f97SEzequiel Garcia dev->gso_max_segs = MVNETA_MAX_TSO_SEGS; 3275b50b72deSwilly tarreau 3276c5aff182SThomas Petazzoni err = register_netdev(dev); 3277c5aff182SThomas Petazzoni if (err < 0) { 3278c5aff182SThomas Petazzoni dev_err(&pdev->dev, "failed to register\n"); 32799672850bSEzequiel Garcia goto err_free_stats; 3280c5aff182SThomas Petazzoni } 3281c5aff182SThomas Petazzoni 32828cc3e439SThomas Petazzoni netdev_info(dev, "Using %s mac address %pM\n", mac_from, 32838cc3e439SThomas Petazzoni dev->dev_addr); 3284c5aff182SThomas Petazzoni 3285c5aff182SThomas Petazzoni platform_set_drvdata(pdev, pp->dev); 3286c5aff182SThomas Petazzoni 3287898b2970SStas Sergeev if (pp->use_inband_status) { 3288898b2970SStas Sergeev struct phy_device *phy = of_phy_find_device(dn); 3289898b2970SStas Sergeev 3290898b2970SStas Sergeev mvneta_fixed_link_update(pp, phy); 329104d53b20SRussell King 329204d53b20SRussell King put_device(&phy->dev); 3293898b2970SStas Sergeev } 3294898b2970SStas Sergeev 3295c5aff182SThomas Petazzoni return 0; 3296c5aff182SThomas Petazzoni 329774c41b04Swilly tarreau err_free_stats: 329874c41b04Swilly tarreau free_percpu(pp->stats); 329912bb03b4SMaxime Ripard err_free_ports: 330012bb03b4SMaxime Ripard free_percpu(pp->ports); 33015445eaf3SArnaud Patard \(Rtp\) err_clk: 33025445eaf3SArnaud Patard \(Rtp\) clk_disable_unprepare(pp->clk); 3303c891c24cSUwe Kleine-König err_put_phy_node: 3304c891c24cSUwe Kleine-König of_node_put(phy_node); 3305c5aff182SThomas Petazzoni err_free_irq: 3306c5aff182SThomas Petazzoni irq_dispose_mapping(dev->irq); 3307c5aff182SThomas Petazzoni err_free_netdev: 3308c5aff182SThomas Petazzoni free_netdev(dev); 3309c5aff182SThomas Petazzoni return err; 3310c5aff182SThomas Petazzoni } 3311c5aff182SThomas Petazzoni 3312c5aff182SThomas Petazzoni /* Device removal routine */ 331303ce758eSGreg KH static int mvneta_remove(struct platform_device *pdev) 3314c5aff182SThomas Petazzoni { 3315c5aff182SThomas Petazzoni struct net_device *dev = platform_get_drvdata(pdev); 3316c5aff182SThomas Petazzoni struct mvneta_port *pp = netdev_priv(dev); 3317c5aff182SThomas Petazzoni 3318c5aff182SThomas Petazzoni unregister_netdev(dev); 3319189dd626SThomas Petazzoni clk_disable_unprepare(pp->clk); 332012bb03b4SMaxime Ripard free_percpu(pp->ports); 332174c41b04Swilly tarreau free_percpu(pp->stats); 3322c5aff182SThomas Petazzoni irq_dispose_mapping(dev->irq); 3323c891c24cSUwe Kleine-König of_node_put(pp->phy_node); 3324c5aff182SThomas Petazzoni free_netdev(dev); 3325c5aff182SThomas Petazzoni 3326c5aff182SThomas Petazzoni return 0; 3327c5aff182SThomas Petazzoni } 3328c5aff182SThomas Petazzoni 3329c5aff182SThomas Petazzoni static const struct of_device_id mvneta_match[] = { 3330c5aff182SThomas Petazzoni { .compatible = "marvell,armada-370-neta" }, 3331f522a975SSimon Guinot { .compatible = "marvell,armada-xp-neta" }, 3332c5aff182SThomas Petazzoni { } 3333c5aff182SThomas Petazzoni }; 3334c5aff182SThomas Petazzoni MODULE_DEVICE_TABLE(of, mvneta_match); 3335c5aff182SThomas Petazzoni 3336c5aff182SThomas Petazzoni static struct platform_driver mvneta_driver = { 3337c5aff182SThomas Petazzoni .probe = mvneta_probe, 333803ce758eSGreg KH .remove = mvneta_remove, 3339c5aff182SThomas Petazzoni .driver = { 3340c5aff182SThomas Petazzoni .name = MVNETA_DRIVER_NAME, 3341c5aff182SThomas Petazzoni .of_match_table = mvneta_match, 3342c5aff182SThomas Petazzoni }, 3343c5aff182SThomas Petazzoni }; 3344c5aff182SThomas Petazzoni 3345c5aff182SThomas Petazzoni module_platform_driver(mvneta_driver); 3346c5aff182SThomas Petazzoni 3347c5aff182SThomas Petazzoni MODULE_DESCRIPTION("Marvell NETA Ethernet Driver - www.marvell.com"); 3348c5aff182SThomas Petazzoni MODULE_AUTHOR("Rami Rosen <rosenr@marvell.com>, Thomas Petazzoni <thomas.petazzoni@free-electrons.com>"); 3349c5aff182SThomas Petazzoni MODULE_LICENSE("GPL"); 3350c5aff182SThomas Petazzoni 3351c5aff182SThomas Petazzoni module_param(rxq_number, int, S_IRUGO); 3352c5aff182SThomas Petazzoni module_param(txq_number, int, S_IRUGO); 3353c5aff182SThomas Petazzoni 3354c5aff182SThomas Petazzoni module_param(rxq_def, int, S_IRUGO); 3355f19fadfcSwilly tarreau module_param(rx_copybreak, int, S_IRUGO | S_IWUSR); 3356