1c5aff182SThomas Petazzoni /* 2c5aff182SThomas Petazzoni * Driver for Marvell NETA network card for Armada XP and Armada 370 SoCs. 3c5aff182SThomas Petazzoni * 4c5aff182SThomas Petazzoni * Copyright (C) 2012 Marvell 5c5aff182SThomas Petazzoni * 6c5aff182SThomas Petazzoni * Rami Rosen <rosenr@marvell.com> 7c5aff182SThomas Petazzoni * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> 8c5aff182SThomas Petazzoni * 9c5aff182SThomas Petazzoni * This file is licensed under the terms of the GNU General Public 10c5aff182SThomas Petazzoni * License version 2. This program is licensed "as is" without any 11c5aff182SThomas Petazzoni * warranty of any kind, whether express or implied. 12c5aff182SThomas Petazzoni */ 13c5aff182SThomas Petazzoni 140e03f563SJisheng Zhang #include <linux/clk.h> 150e03f563SJisheng Zhang #include <linux/cpu.h> 16c5aff182SThomas Petazzoni #include <linux/etherdevice.h> 170e03f563SJisheng Zhang #include <linux/if_vlan.h> 18c5aff182SThomas Petazzoni #include <linux/inetdevice.h> 190e03f563SJisheng Zhang #include <linux/interrupt.h> 200e03f563SJisheng Zhang #include <linux/io.h> 210e03f563SJisheng Zhang #include <linux/kernel.h> 22c5aff182SThomas Petazzoni #include <linux/mbus.h> 23c5aff182SThomas Petazzoni #include <linux/module.h> 240e03f563SJisheng Zhang #include <linux/netdevice.h> 25c5aff182SThomas Petazzoni #include <linux/of.h> 260e03f563SJisheng Zhang #include <linux/of_address.h> 27c5aff182SThomas Petazzoni #include <linux/of_irq.h> 28c5aff182SThomas Petazzoni #include <linux/of_mdio.h> 29c5aff182SThomas Petazzoni #include <linux/of_net.h> 30a10c1c81SRussell King #include <linux/phy/phy.h> 31c5aff182SThomas Petazzoni #include <linux/phy.h> 32503f9aa9SRussell King #include <linux/phylink.h> 330e03f563SJisheng Zhang #include <linux/platform_device.h> 340e03f563SJisheng Zhang #include <linux/skbuff.h> 35baa11ebcSGregory CLEMENT #include <net/hwbm.h> 36dc35a10fSMarcin Wojtas #include "mvneta_bm.h" 370e03f563SJisheng Zhang #include <net/ip.h> 380e03f563SJisheng Zhang #include <net/ipv6.h> 390e03f563SJisheng Zhang #include <net/tso.h> 40568a3fa2SLorenzo Bianconi #include <net/page_pool.h> 4175fa71e3SMaxime Chevallier #include <net/pkt_cls.h> 420db51da7SLorenzo Bianconi #include <linux/bpf_trace.h> 43c5aff182SThomas Petazzoni 44c5aff182SThomas Petazzoni /* Registers */ 45c5aff182SThomas Petazzoni #define MVNETA_RXQ_CONFIG_REG(q) (0x1400 + ((q) << 2)) 46e5bdf689SMarcin Wojtas #define MVNETA_RXQ_HW_BUF_ALLOC BIT(0) 47dc35a10fSMarcin Wojtas #define MVNETA_RXQ_SHORT_POOL_ID_SHIFT 4 48dc35a10fSMarcin Wojtas #define MVNETA_RXQ_SHORT_POOL_ID_MASK 0x30 49dc35a10fSMarcin Wojtas #define MVNETA_RXQ_LONG_POOL_ID_SHIFT 6 50dc35a10fSMarcin Wojtas #define MVNETA_RXQ_LONG_POOL_ID_MASK 0xc0 51c5aff182SThomas Petazzoni #define MVNETA_RXQ_PKT_OFFSET_ALL_MASK (0xf << 8) 52c5aff182SThomas Petazzoni #define MVNETA_RXQ_PKT_OFFSET_MASK(offs) ((offs) << 8) 53c5aff182SThomas Petazzoni #define MVNETA_RXQ_THRESHOLD_REG(q) (0x14c0 + ((q) << 2)) 54c5aff182SThomas Petazzoni #define MVNETA_RXQ_NON_OCCUPIED(v) ((v) << 16) 55c5aff182SThomas Petazzoni #define MVNETA_RXQ_BASE_ADDR_REG(q) (0x1480 + ((q) << 2)) 56c5aff182SThomas Petazzoni #define MVNETA_RXQ_SIZE_REG(q) (0x14a0 + ((q) << 2)) 57c5aff182SThomas Petazzoni #define MVNETA_RXQ_BUF_SIZE_SHIFT 19 58c5aff182SThomas Petazzoni #define MVNETA_RXQ_BUF_SIZE_MASK (0x1fff << 19) 59c5aff182SThomas Petazzoni #define MVNETA_RXQ_STATUS_REG(q) (0x14e0 + ((q) << 2)) 60c5aff182SThomas Petazzoni #define MVNETA_RXQ_OCCUPIED_ALL_MASK 0x3fff 61c5aff182SThomas Petazzoni #define MVNETA_RXQ_STATUS_UPDATE_REG(q) (0x1500 + ((q) << 2)) 62c5aff182SThomas Petazzoni #define MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT 16 63c5aff182SThomas Petazzoni #define MVNETA_RXQ_ADD_NON_OCCUPIED_MAX 255 64dc35a10fSMarcin Wojtas #define MVNETA_PORT_POOL_BUFFER_SZ_REG(pool) (0x1700 + ((pool) << 2)) 65dc35a10fSMarcin Wojtas #define MVNETA_PORT_POOL_BUFFER_SZ_SHIFT 3 66dc35a10fSMarcin Wojtas #define MVNETA_PORT_POOL_BUFFER_SZ_MASK 0xfff8 67c5aff182SThomas Petazzoni #define MVNETA_PORT_RX_RESET 0x1cc0 68c5aff182SThomas Petazzoni #define MVNETA_PORT_RX_DMA_RESET BIT(0) 69c5aff182SThomas Petazzoni #define MVNETA_PHY_ADDR 0x2000 70c5aff182SThomas Petazzoni #define MVNETA_PHY_ADDR_MASK 0x1f 71c5aff182SThomas Petazzoni #define MVNETA_MBUS_RETRY 0x2010 72c5aff182SThomas Petazzoni #define MVNETA_UNIT_INTR_CAUSE 0x2080 73c5aff182SThomas Petazzoni #define MVNETA_UNIT_CONTROL 0x20B0 74c5aff182SThomas Petazzoni #define MVNETA_PHY_POLLING_ENABLE BIT(1) 75c5aff182SThomas Petazzoni #define MVNETA_WIN_BASE(w) (0x2200 + ((w) << 3)) 76c5aff182SThomas Petazzoni #define MVNETA_WIN_SIZE(w) (0x2204 + ((w) << 3)) 77c5aff182SThomas Petazzoni #define MVNETA_WIN_REMAP(w) (0x2280 + ((w) << 2)) 78c5aff182SThomas Petazzoni #define MVNETA_BASE_ADDR_ENABLE 0x2290 79db6ba9a5SMarcin Wojtas #define MVNETA_ACCESS_PROTECT_ENABLE 0x2294 80c5aff182SThomas Petazzoni #define MVNETA_PORT_CONFIG 0x2400 81c5aff182SThomas Petazzoni #define MVNETA_UNI_PROMISC_MODE BIT(0) 82c5aff182SThomas Petazzoni #define MVNETA_DEF_RXQ(q) ((q) << 1) 83c5aff182SThomas Petazzoni #define MVNETA_DEF_RXQ_ARP(q) ((q) << 4) 84c5aff182SThomas Petazzoni #define MVNETA_TX_UNSET_ERR_SUM BIT(12) 85c5aff182SThomas Petazzoni #define MVNETA_DEF_RXQ_TCP(q) ((q) << 16) 86c5aff182SThomas Petazzoni #define MVNETA_DEF_RXQ_UDP(q) ((q) << 19) 87c5aff182SThomas Petazzoni #define MVNETA_DEF_RXQ_BPDU(q) ((q) << 22) 88c5aff182SThomas Petazzoni #define MVNETA_RX_CSUM_WITH_PSEUDO_HDR BIT(25) 89c5aff182SThomas Petazzoni #define MVNETA_PORT_CONFIG_DEFL_VALUE(q) (MVNETA_DEF_RXQ(q) | \ 90c5aff182SThomas Petazzoni MVNETA_DEF_RXQ_ARP(q) | \ 91c5aff182SThomas Petazzoni MVNETA_DEF_RXQ_TCP(q) | \ 92c5aff182SThomas Petazzoni MVNETA_DEF_RXQ_UDP(q) | \ 93c5aff182SThomas Petazzoni MVNETA_DEF_RXQ_BPDU(q) | \ 94c5aff182SThomas Petazzoni MVNETA_TX_UNSET_ERR_SUM | \ 95c5aff182SThomas Petazzoni MVNETA_RX_CSUM_WITH_PSEUDO_HDR) 96c5aff182SThomas Petazzoni #define MVNETA_PORT_CONFIG_EXTEND 0x2404 97c5aff182SThomas Petazzoni #define MVNETA_MAC_ADDR_LOW 0x2414 98c5aff182SThomas Petazzoni #define MVNETA_MAC_ADDR_HIGH 0x2418 99c5aff182SThomas Petazzoni #define MVNETA_SDMA_CONFIG 0x241c 100c5aff182SThomas Petazzoni #define MVNETA_SDMA_BRST_SIZE_16 4 101c5aff182SThomas Petazzoni #define MVNETA_RX_BRST_SZ_MASK(burst) ((burst) << 1) 102c5aff182SThomas Petazzoni #define MVNETA_RX_NO_DATA_SWAP BIT(4) 103c5aff182SThomas Petazzoni #define MVNETA_TX_NO_DATA_SWAP BIT(5) 1049ad8fef6SThomas Petazzoni #define MVNETA_DESC_SWAP BIT(6) 105c5aff182SThomas Petazzoni #define MVNETA_TX_BRST_SZ_MASK(burst) ((burst) << 22) 1064906887aSMaxime Chevallier #define MVNETA_VLAN_PRIO_TO_RXQ 0x2440 1074906887aSMaxime Chevallier #define MVNETA_VLAN_PRIO_RXQ_MAP(prio, rxq) ((rxq) << ((prio) * 3)) 108c5aff182SThomas Petazzoni #define MVNETA_PORT_STATUS 0x2444 109359f4cddSMaxim Kiselev #define MVNETA_TX_IN_PRGRS BIT(0) 110c5aff182SThomas Petazzoni #define MVNETA_TX_FIFO_EMPTY BIT(8) 111c5aff182SThomas Petazzoni #define MVNETA_RX_MIN_FRAME_SIZE 0x247c 112b4748553SSascha Hauer /* Only exists on Armada XP and Armada 370 */ 1133f1dd4bcSThomas Petazzoni #define MVNETA_SERDES_CFG 0x24A0 1145445eaf3SArnaud Patard \(Rtp\) #define MVNETA_SGMII_SERDES_PROTO 0x0cc7 1153f1dd4bcSThomas Petazzoni #define MVNETA_QSGMII_SERDES_PROTO 0x0667 1161a642ca7SSascha Hauer #define MVNETA_HSGMII_SERDES_PROTO 0x1107 117c5aff182SThomas Petazzoni #define MVNETA_TYPE_PRIO 0x24bc 118c5aff182SThomas Petazzoni #define MVNETA_FORCE_UNI BIT(21) 119c5aff182SThomas Petazzoni #define MVNETA_TXQ_CMD_1 0x24e4 120c5aff182SThomas Petazzoni #define MVNETA_TXQ_CMD 0x2448 121c5aff182SThomas Petazzoni #define MVNETA_TXQ_DISABLE_SHIFT 8 122c5aff182SThomas Petazzoni #define MVNETA_TXQ_ENABLE_MASK 0x000000ff 123e483911fSAndrew Lunn #define MVNETA_RX_DISCARD_FRAME_COUNT 0x2484 124e483911fSAndrew Lunn #define MVNETA_OVERRUN_FRAME_COUNT 0x2488 125898b2970SStas Sergeev #define MVNETA_GMAC_CLOCK_DIVIDER 0x24f4 126898b2970SStas Sergeev #define MVNETA_GMAC_1MS_CLOCK_ENABLE BIT(31) 127c5aff182SThomas Petazzoni #define MVNETA_ACC_MODE 0x2500 128dc35a10fSMarcin Wojtas #define MVNETA_BM_ADDRESS 0x2504 129c5aff182SThomas Petazzoni #define MVNETA_CPU_MAP(cpu) (0x2540 + ((cpu) << 2)) 130c5aff182SThomas Petazzoni #define MVNETA_CPU_RXQ_ACCESS_ALL_MASK 0x000000ff 131c5aff182SThomas Petazzoni #define MVNETA_CPU_TXQ_ACCESS_ALL_MASK 0x0000ff00 1322dcf75e2SGregory CLEMENT #define MVNETA_CPU_RXQ_ACCESS(rxq) BIT(rxq) 13350bf8cb6SGregory CLEMENT #define MVNETA_CPU_TXQ_ACCESS(txq) BIT(txq + 8) 134c5aff182SThomas Petazzoni #define MVNETA_RXQ_TIME_COAL_REG(q) (0x2580 + ((q) << 2)) 13540ba35e7Swilly tarreau 1362dcf75e2SGregory CLEMENT /* Exception Interrupt Port/Queue Cause register 1372dcf75e2SGregory CLEMENT * 1382dcf75e2SGregory CLEMENT * Their behavior depend of the mapping done using the PCPX2Q 1392dcf75e2SGregory CLEMENT * registers. For a given CPU if the bit associated to a queue is not 1402dcf75e2SGregory CLEMENT * set, then for the register a read from this CPU will always return 1412dcf75e2SGregory CLEMENT * 0 and a write won't do anything 1422dcf75e2SGregory CLEMENT */ 14340ba35e7Swilly tarreau 144c5aff182SThomas Petazzoni #define MVNETA_INTR_NEW_CAUSE 0x25a0 145c5aff182SThomas Petazzoni #define MVNETA_INTR_NEW_MASK 0x25a4 14640ba35e7Swilly tarreau 14740ba35e7Swilly tarreau /* bits 0..7 = TXQ SENT, one bit per queue. 14840ba35e7Swilly tarreau * bits 8..15 = RXQ OCCUP, one bit per queue. 14940ba35e7Swilly tarreau * bits 16..23 = RXQ FREE, one bit per queue. 15040ba35e7Swilly tarreau * bit 29 = OLD_REG_SUM, see old reg ? 15140ba35e7Swilly tarreau * bit 30 = TX_ERR_SUM, one bit for 4 ports 15240ba35e7Swilly tarreau * bit 31 = MISC_SUM, one bit for 4 ports 15340ba35e7Swilly tarreau */ 15440ba35e7Swilly tarreau #define MVNETA_TX_INTR_MASK(nr_txqs) (((1 << nr_txqs) - 1) << 0) 15540ba35e7Swilly tarreau #define MVNETA_TX_INTR_MASK_ALL (0xff << 0) 15640ba35e7Swilly tarreau #define MVNETA_RX_INTR_MASK(nr_rxqs) (((1 << nr_rxqs) - 1) << 8) 15740ba35e7Swilly tarreau #define MVNETA_RX_INTR_MASK_ALL (0xff << 8) 158898b2970SStas Sergeev #define MVNETA_MISCINTR_INTR_MASK BIT(31) 15940ba35e7Swilly tarreau 160c5aff182SThomas Petazzoni #define MVNETA_INTR_OLD_CAUSE 0x25a8 161c5aff182SThomas Petazzoni #define MVNETA_INTR_OLD_MASK 0x25ac 16240ba35e7Swilly tarreau 16340ba35e7Swilly tarreau /* Data Path Port/Queue Cause Register */ 164c5aff182SThomas Petazzoni #define MVNETA_INTR_MISC_CAUSE 0x25b0 165c5aff182SThomas Petazzoni #define MVNETA_INTR_MISC_MASK 0x25b4 16640ba35e7Swilly tarreau 16740ba35e7Swilly tarreau #define MVNETA_CAUSE_PHY_STATUS_CHANGE BIT(0) 16840ba35e7Swilly tarreau #define MVNETA_CAUSE_LINK_CHANGE BIT(1) 16940ba35e7Swilly tarreau #define MVNETA_CAUSE_PTP BIT(4) 17040ba35e7Swilly tarreau 17140ba35e7Swilly tarreau #define MVNETA_CAUSE_INTERNAL_ADDR_ERR BIT(7) 17240ba35e7Swilly tarreau #define MVNETA_CAUSE_RX_OVERRUN BIT(8) 17340ba35e7Swilly tarreau #define MVNETA_CAUSE_RX_CRC_ERROR BIT(9) 17440ba35e7Swilly tarreau #define MVNETA_CAUSE_RX_LARGE_PKT BIT(10) 17540ba35e7Swilly tarreau #define MVNETA_CAUSE_TX_UNDERUN BIT(11) 17640ba35e7Swilly tarreau #define MVNETA_CAUSE_PRBS_ERR BIT(12) 17740ba35e7Swilly tarreau #define MVNETA_CAUSE_PSC_SYNC_CHANGE BIT(13) 17840ba35e7Swilly tarreau #define MVNETA_CAUSE_SERDES_SYNC_ERR BIT(14) 17940ba35e7Swilly tarreau 18040ba35e7Swilly tarreau #define MVNETA_CAUSE_BMU_ALLOC_ERR_SHIFT 16 18140ba35e7Swilly tarreau #define MVNETA_CAUSE_BMU_ALLOC_ERR_ALL_MASK (0xF << MVNETA_CAUSE_BMU_ALLOC_ERR_SHIFT) 18240ba35e7Swilly tarreau #define MVNETA_CAUSE_BMU_ALLOC_ERR_MASK(pool) (1 << (MVNETA_CAUSE_BMU_ALLOC_ERR_SHIFT + (pool))) 18340ba35e7Swilly tarreau 18440ba35e7Swilly tarreau #define MVNETA_CAUSE_TXQ_ERROR_SHIFT 24 18540ba35e7Swilly tarreau #define MVNETA_CAUSE_TXQ_ERROR_ALL_MASK (0xFF << MVNETA_CAUSE_TXQ_ERROR_SHIFT) 18640ba35e7Swilly tarreau #define MVNETA_CAUSE_TXQ_ERROR_MASK(q) (1 << (MVNETA_CAUSE_TXQ_ERROR_SHIFT + (q))) 18740ba35e7Swilly tarreau 188c5aff182SThomas Petazzoni #define MVNETA_INTR_ENABLE 0x25b8 189c5aff182SThomas Petazzoni #define MVNETA_TXQ_INTR_ENABLE_ALL_MASK 0x0000ff00 190dc1aadf6SMarcin Wojtas #define MVNETA_RXQ_INTR_ENABLE_ALL_MASK 0x000000ff 19140ba35e7Swilly tarreau 192c5aff182SThomas Petazzoni #define MVNETA_RXQ_CMD 0x2680 193c5aff182SThomas Petazzoni #define MVNETA_RXQ_DISABLE_SHIFT 8 194c5aff182SThomas Petazzoni #define MVNETA_RXQ_ENABLE_MASK 0x000000ff 195c5aff182SThomas Petazzoni #define MVETH_TXQ_TOKEN_COUNT_REG(q) (0x2700 + ((q) << 4)) 196c5aff182SThomas Petazzoni #define MVETH_TXQ_TOKEN_CFG_REG(q) (0x2704 + ((q) << 4)) 197c5aff182SThomas Petazzoni #define MVNETA_GMAC_CTRL_0 0x2c00 198c5aff182SThomas Petazzoni #define MVNETA_GMAC_MAX_RX_SIZE_SHIFT 2 199c5aff182SThomas Petazzoni #define MVNETA_GMAC_MAX_RX_SIZE_MASK 0x7ffc 20022f4bf8aSRussell King #define MVNETA_GMAC0_PORT_1000BASE_X BIT(1) 201c5aff182SThomas Petazzoni #define MVNETA_GMAC0_PORT_ENABLE BIT(0) 202c5aff182SThomas Petazzoni #define MVNETA_GMAC_CTRL_2 0x2c08 203898b2970SStas Sergeev #define MVNETA_GMAC2_INBAND_AN_ENABLE BIT(0) 204a79121d3SThomas Petazzoni #define MVNETA_GMAC2_PCS_ENABLE BIT(3) 205c5aff182SThomas Petazzoni #define MVNETA_GMAC2_PORT_RGMII BIT(4) 206c5aff182SThomas Petazzoni #define MVNETA_GMAC2_PORT_RESET BIT(6) 207c5aff182SThomas Petazzoni #define MVNETA_GMAC_STATUS 0x2c10 208c5aff182SThomas Petazzoni #define MVNETA_GMAC_LINK_UP BIT(0) 209c5aff182SThomas Petazzoni #define MVNETA_GMAC_SPEED_1000 BIT(1) 210c5aff182SThomas Petazzoni #define MVNETA_GMAC_SPEED_100 BIT(2) 211c5aff182SThomas Petazzoni #define MVNETA_GMAC_FULL_DUPLEX BIT(3) 212c5aff182SThomas Petazzoni #define MVNETA_GMAC_RX_FLOW_CTRL_ENABLE BIT(4) 213c5aff182SThomas Petazzoni #define MVNETA_GMAC_TX_FLOW_CTRL_ENABLE BIT(5) 214c5aff182SThomas Petazzoni #define MVNETA_GMAC_RX_FLOW_CTRL_ACTIVE BIT(6) 215c5aff182SThomas Petazzoni #define MVNETA_GMAC_TX_FLOW_CTRL_ACTIVE BIT(7) 216503f9aa9SRussell King #define MVNETA_GMAC_AN_COMPLETE BIT(11) 217503f9aa9SRussell King #define MVNETA_GMAC_SYNC_OK BIT(14) 218c5aff182SThomas Petazzoni #define MVNETA_GMAC_AUTONEG_CONFIG 0x2c0c 219c5aff182SThomas Petazzoni #define MVNETA_GMAC_FORCE_LINK_DOWN BIT(0) 220c5aff182SThomas Petazzoni #define MVNETA_GMAC_FORCE_LINK_PASS BIT(1) 221898b2970SStas Sergeev #define MVNETA_GMAC_INBAND_AN_ENABLE BIT(2) 22222f4bf8aSRussell King #define MVNETA_GMAC_AN_BYPASS_ENABLE BIT(3) 22322f4bf8aSRussell King #define MVNETA_GMAC_INBAND_RESTART_AN BIT(4) 224c5aff182SThomas Petazzoni #define MVNETA_GMAC_CONFIG_MII_SPEED BIT(5) 225c5aff182SThomas Petazzoni #define MVNETA_GMAC_CONFIG_GMII_SPEED BIT(6) 22671408602SThomas Petazzoni #define MVNETA_GMAC_AN_SPEED_EN BIT(7) 22722f4bf8aSRussell King #define MVNETA_GMAC_CONFIG_FLOW_CTRL BIT(8) 22822f4bf8aSRussell King #define MVNETA_GMAC_ADVERT_SYM_FLOW_CTRL BIT(9) 229898b2970SStas Sergeev #define MVNETA_GMAC_AN_FLOW_CTRL_EN BIT(11) 230c5aff182SThomas Petazzoni #define MVNETA_GMAC_CONFIG_FULL_DUPLEX BIT(12) 23171408602SThomas Petazzoni #define MVNETA_GMAC_AN_DUPLEX_EN BIT(13) 232da58a931SMaxime Chevallier #define MVNETA_GMAC_CTRL_4 0x2c90 233da58a931SMaxime Chevallier #define MVNETA_GMAC4_SHORT_PREAMBLE_ENABLE BIT(1) 234e483911fSAndrew Lunn #define MVNETA_MIB_COUNTERS_BASE 0x3000 235c5aff182SThomas Petazzoni #define MVNETA_MIB_LATE_COLLISION 0x7c 236c5aff182SThomas Petazzoni #define MVNETA_DA_FILT_SPEC_MCAST 0x3400 237c5aff182SThomas Petazzoni #define MVNETA_DA_FILT_OTH_MCAST 0x3500 238c5aff182SThomas Petazzoni #define MVNETA_DA_FILT_UCAST_BASE 0x3600 239c5aff182SThomas Petazzoni #define MVNETA_TXQ_BASE_ADDR_REG(q) (0x3c00 + ((q) << 2)) 240c5aff182SThomas Petazzoni #define MVNETA_TXQ_SIZE_REG(q) (0x3c20 + ((q) << 2)) 241c5aff182SThomas Petazzoni #define MVNETA_TXQ_SENT_THRESH_ALL_MASK 0x3fff0000 242c5aff182SThomas Petazzoni #define MVNETA_TXQ_SENT_THRESH_MASK(coal) ((coal) << 16) 243c5aff182SThomas Petazzoni #define MVNETA_TXQ_UPDATE_REG(q) (0x3c60 + ((q) << 2)) 244c5aff182SThomas Petazzoni #define MVNETA_TXQ_DEC_SENT_SHIFT 16 2452a90f7e1SSimon Guinot #define MVNETA_TXQ_DEC_SENT_MASK 0xff 246c5aff182SThomas Petazzoni #define MVNETA_TXQ_STATUS_REG(q) (0x3c40 + ((q) << 2)) 247c5aff182SThomas Petazzoni #define MVNETA_TXQ_SENT_DESC_SHIFT 16 248c5aff182SThomas Petazzoni #define MVNETA_TXQ_SENT_DESC_MASK 0x3fff0000 249c5aff182SThomas Petazzoni #define MVNETA_PORT_TX_RESET 0x3cf0 250c5aff182SThomas Petazzoni #define MVNETA_PORT_TX_DMA_RESET BIT(0) 251c5aff182SThomas Petazzoni #define MVNETA_TX_MTU 0x3e0c 252c5aff182SThomas Petazzoni #define MVNETA_TX_TOKEN_SIZE 0x3e14 253c5aff182SThomas Petazzoni #define MVNETA_TX_TOKEN_SIZE_MAX 0xffffffff 254c5aff182SThomas Petazzoni #define MVNETA_TXQ_TOKEN_SIZE_REG(q) (0x3e40 + ((q) << 2)) 255c5aff182SThomas Petazzoni #define MVNETA_TXQ_TOKEN_SIZE_MAX 0x7fffffff 256c5aff182SThomas Petazzoni 2576d81f451SRussell King #define MVNETA_LPI_CTRL_0 0x2cc0 2586d81f451SRussell King #define MVNETA_LPI_CTRL_1 0x2cc4 2596d81f451SRussell King #define MVNETA_LPI_REQUEST_ENABLE BIT(0) 2606d81f451SRussell King #define MVNETA_LPI_CTRL_2 0x2cc8 2616d81f451SRussell King #define MVNETA_LPI_STATUS 0x2ccc 2626d81f451SRussell King 263c5aff182SThomas Petazzoni #define MVNETA_CAUSE_TXQ_SENT_DESC_ALL_MASK 0xff 264c5aff182SThomas Petazzoni 265c5aff182SThomas Petazzoni /* Descriptor ring Macros */ 266c5aff182SThomas Petazzoni #define MVNETA_QUEUE_NEXT_DESC(q, index) \ 267c5aff182SThomas Petazzoni (((index) < (q)->last_desc) ? ((index) + 1) : 0) 268c5aff182SThomas Petazzoni 269c5aff182SThomas Petazzoni /* Various constants */ 270c5aff182SThomas Petazzoni 271c5aff182SThomas Petazzoni /* Coalescing */ 27206708f81SDmitri Epshtein #define MVNETA_TXDONE_COAL_PKTS 0 /* interrupt per packet */ 273c5aff182SThomas Petazzoni #define MVNETA_RX_COAL_PKTS 32 274c5aff182SThomas Petazzoni #define MVNETA_RX_COAL_USEC 100 275c5aff182SThomas Petazzoni 2766a20c175SThomas Petazzoni /* The two bytes Marvell header. Either contains a special value used 277c5aff182SThomas Petazzoni * by Marvell switches when a specific hardware mode is enabled (not 278c5aff182SThomas Petazzoni * supported by this driver) or is filled automatically by zeroes on 279c5aff182SThomas Petazzoni * the RX side. Those two bytes being at the front of the Ethernet 280c5aff182SThomas Petazzoni * header, they allow to have the IP header aligned on a 4 bytes 281c5aff182SThomas Petazzoni * boundary automatically: the hardware skips those two bytes on its 282c5aff182SThomas Petazzoni * own. 283c5aff182SThomas Petazzoni */ 284c5aff182SThomas Petazzoni #define MVNETA_MH_SIZE 2 285c5aff182SThomas Petazzoni 286c5aff182SThomas Petazzoni #define MVNETA_VLAN_TAG_LEN 4 287c5aff182SThomas Petazzoni 2889110ee07SMarcin Wojtas #define MVNETA_TX_CSUM_DEF_SIZE 1600 289c5aff182SThomas Petazzoni #define MVNETA_TX_CSUM_MAX_SIZE 9800 290dc35a10fSMarcin Wojtas #define MVNETA_ACC_MODE_EXT1 1 291dc35a10fSMarcin Wojtas #define MVNETA_ACC_MODE_EXT2 2 292dc35a10fSMarcin Wojtas 293dc35a10fSMarcin Wojtas #define MVNETA_MAX_DECODE_WIN 6 294c5aff182SThomas Petazzoni 295c5aff182SThomas Petazzoni /* Timeout constants */ 296c5aff182SThomas Petazzoni #define MVNETA_TX_DISABLE_TIMEOUT_MSEC 1000 297c5aff182SThomas Petazzoni #define MVNETA_RX_DISABLE_TIMEOUT_MSEC 1000 298c5aff182SThomas Petazzoni #define MVNETA_TX_FIFO_EMPTY_TIMEOUT 10000 299c5aff182SThomas Petazzoni 300c5aff182SThomas Petazzoni #define MVNETA_TX_MTU_MAX 0x3ffff 301c5aff182SThomas Petazzoni 3029a401deaSGregory CLEMENT /* The RSS lookup table actually has 256 entries but we do not use 3039a401deaSGregory CLEMENT * them yet 3049a401deaSGregory CLEMENT */ 3059a401deaSGregory CLEMENT #define MVNETA_RSS_LU_TABLE_SIZE 1 3069a401deaSGregory CLEMENT 307c5aff182SThomas Petazzoni /* Max number of Rx descriptors */ 308c307e2a8SYelena Krivosheev #define MVNETA_MAX_RXD 512 309c5aff182SThomas Petazzoni 310c5aff182SThomas Petazzoni /* Max number of Tx descriptors */ 311c307e2a8SYelena Krivosheev #define MVNETA_MAX_TXD 1024 312c5aff182SThomas Petazzoni 3138eef5f97SEzequiel Garcia /* Max number of allowed TCP segments for software TSO */ 3148eef5f97SEzequiel Garcia #define MVNETA_MAX_TSO_SEGS 100 3158eef5f97SEzequiel Garcia 3168eef5f97SEzequiel Garcia #define MVNETA_MAX_SKB_DESCS (MVNETA_MAX_TSO_SEGS * 2 + MAX_SKB_FRAGS) 3178eef5f97SEzequiel Garcia 318c5aff182SThomas Petazzoni /* descriptor aligned size */ 319c5aff182SThomas Petazzoni #define MVNETA_DESC_ALIGNED_SIZE 32 320c5aff182SThomas Petazzoni 3218d5047cfSMarcin Wojtas /* Number of bytes to be taken into account by HW when putting incoming data 3228d5047cfSMarcin Wojtas * to the buffers. It is needed in case NET_SKB_PAD exceeds maximum packet 3238d5047cfSMarcin Wojtas * offset supported in MVNETA_RXQ_CONFIG_REG(q) registers. 3248d5047cfSMarcin Wojtas */ 3258d5047cfSMarcin Wojtas #define MVNETA_RX_PKT_OFFSET_CORRECTION 64 3268d5047cfSMarcin Wojtas 327c5aff182SThomas Petazzoni #define MVNETA_RX_PKT_SIZE(mtu) \ 328c5aff182SThomas Petazzoni ALIGN((mtu) + MVNETA_MH_SIZE + MVNETA_VLAN_TAG_LEN + \ 329c5aff182SThomas Petazzoni ETH_HLEN + ETH_FCS_LEN, \ 330c66e98c9SJisheng Zhang cache_line_size()) 331c5aff182SThomas Petazzoni 332ca23cb0bSSven Auhagen /* Driver assumes that the last 3 bits are 0 */ 333e2243720SAlexander Lobakin #define MVNETA_SKB_HEADROOM ALIGN(max(NET_SKB_PAD, XDP_PACKET_HEADROOM), 8) 3348dc9a088SLorenzo Bianconi #define MVNETA_SKB_PAD (SKB_DATA_ALIGN(sizeof(struct skb_shared_info) + \ 3350db51da7SLorenzo Bianconi MVNETA_SKB_HEADROOM)) 3368dc9a088SLorenzo Bianconi #define MVNETA_MAX_RX_BUF_SIZE (PAGE_SIZE - MVNETA_SKB_PAD) 3378dc9a088SLorenzo Bianconi 3382e3173a3SEzequiel Garcia #define IS_TSO_HEADER(txq, addr) \ 3392e3173a3SEzequiel Garcia ((addr >= txq->tso_hdrs_phys) && \ 3402e3173a3SEzequiel Garcia (addr < txq->tso_hdrs_phys + txq->size * TSO_HEADER_SIZE)) 3412e3173a3SEzequiel Garcia 342dc35a10fSMarcin Wojtas #define MVNETA_RX_GET_BM_POOL_ID(rxd) \ 343dc35a10fSMarcin Wojtas (((rxd)->status & MVNETA_RXD_BM_POOL_MASK) >> MVNETA_RXD_BM_POOL_SHIFT) 344c5aff182SThomas Petazzoni 3456d81f451SRussell King enum { 3466d81f451SRussell King ETHTOOL_STAT_EEE_WAKEUP, 34717a96da6SGregory CLEMENT ETHTOOL_STAT_SKB_ALLOC_ERR, 34817a96da6SGregory CLEMENT ETHTOOL_STAT_REFILL_ERR, 3493d866523SLorenzo Bianconi ETHTOOL_XDP_REDIRECT, 3503d866523SLorenzo Bianconi ETHTOOL_XDP_PASS, 3513d866523SLorenzo Bianconi ETHTOOL_XDP_DROP, 3523d866523SLorenzo Bianconi ETHTOOL_XDP_TX, 35315070919SJesper Dangaard Brouer ETHTOOL_XDP_TX_ERR, 35415070919SJesper Dangaard Brouer ETHTOOL_XDP_XMIT, 35515070919SJesper Dangaard Brouer ETHTOOL_XDP_XMIT_ERR, 3566d81f451SRussell King ETHTOOL_MAX_STATS, 3576d81f451SRussell King }; 3586d81f451SRussell King 3599b0cdefaSRussell King struct mvneta_statistic { 3609b0cdefaSRussell King unsigned short offset; 3619b0cdefaSRussell King unsigned short type; 3629b0cdefaSRussell King const char name[ETH_GSTRING_LEN]; 3639b0cdefaSRussell King }; 3649b0cdefaSRussell King 3659b0cdefaSRussell King #define T_REG_32 32 3669b0cdefaSRussell King #define T_REG_64 64 3676d81f451SRussell King #define T_SW 1 3689b0cdefaSRussell King 3696c8a8cfdSLorenzo Bianconi #define MVNETA_XDP_PASS 0 3706c8a8cfdSLorenzo Bianconi #define MVNETA_XDP_DROPPED BIT(0) 3716c8a8cfdSLorenzo Bianconi #define MVNETA_XDP_TX BIT(1) 3726c8a8cfdSLorenzo Bianconi #define MVNETA_XDP_REDIR BIT(2) 3730db51da7SLorenzo Bianconi 3749b0cdefaSRussell King static const struct mvneta_statistic mvneta_statistics[] = { 3759b0cdefaSRussell King { 0x3000, T_REG_64, "good_octets_received", }, 3769b0cdefaSRussell King { 0x3010, T_REG_32, "good_frames_received", }, 3779b0cdefaSRussell King { 0x3008, T_REG_32, "bad_octets_received", }, 3789b0cdefaSRussell King { 0x3014, T_REG_32, "bad_frames_received", }, 3799b0cdefaSRussell King { 0x3018, T_REG_32, "broadcast_frames_received", }, 3809b0cdefaSRussell King { 0x301c, T_REG_32, "multicast_frames_received", }, 3819b0cdefaSRussell King { 0x3050, T_REG_32, "unrec_mac_control_received", }, 3829b0cdefaSRussell King { 0x3058, T_REG_32, "good_fc_received", }, 3839b0cdefaSRussell King { 0x305c, T_REG_32, "bad_fc_received", }, 3849b0cdefaSRussell King { 0x3060, T_REG_32, "undersize_received", }, 3859b0cdefaSRussell King { 0x3064, T_REG_32, "fragments_received", }, 3869b0cdefaSRussell King { 0x3068, T_REG_32, "oversize_received", }, 3879b0cdefaSRussell King { 0x306c, T_REG_32, "jabber_received", }, 3889b0cdefaSRussell King { 0x3070, T_REG_32, "mac_receive_error", }, 3899b0cdefaSRussell King { 0x3074, T_REG_32, "bad_crc_event", }, 3909b0cdefaSRussell King { 0x3078, T_REG_32, "collision", }, 3919b0cdefaSRussell King { 0x307c, T_REG_32, "late_collision", }, 3929b0cdefaSRussell King { 0x2484, T_REG_32, "rx_discard", }, 3939b0cdefaSRussell King { 0x2488, T_REG_32, "rx_overrun", }, 3949b0cdefaSRussell King { 0x3020, T_REG_32, "frames_64_octets", }, 3959b0cdefaSRussell King { 0x3024, T_REG_32, "frames_65_to_127_octets", }, 3969b0cdefaSRussell King { 0x3028, T_REG_32, "frames_128_to_255_octets", }, 3979b0cdefaSRussell King { 0x302c, T_REG_32, "frames_256_to_511_octets", }, 3989b0cdefaSRussell King { 0x3030, T_REG_32, "frames_512_to_1023_octets", }, 3999b0cdefaSRussell King { 0x3034, T_REG_32, "frames_1024_to_max_octets", }, 4009b0cdefaSRussell King { 0x3038, T_REG_64, "good_octets_sent", }, 4019b0cdefaSRussell King { 0x3040, T_REG_32, "good_frames_sent", }, 4029b0cdefaSRussell King { 0x3044, T_REG_32, "excessive_collision", }, 4039b0cdefaSRussell King { 0x3048, T_REG_32, "multicast_frames_sent", }, 4049b0cdefaSRussell King { 0x304c, T_REG_32, "broadcast_frames_sent", }, 4059b0cdefaSRussell King { 0x3054, T_REG_32, "fc_sent", }, 4069b0cdefaSRussell King { 0x300c, T_REG_32, "internal_mac_transmit_err", }, 4076d81f451SRussell King { ETHTOOL_STAT_EEE_WAKEUP, T_SW, "eee_wakeup_errors", }, 40817a96da6SGregory CLEMENT { ETHTOOL_STAT_SKB_ALLOC_ERR, T_SW, "skb_alloc_errors", }, 40917a96da6SGregory CLEMENT { ETHTOOL_STAT_REFILL_ERR, T_SW, "refill_errors", }, 4107d51a015SLorenzo Bianconi { ETHTOOL_XDP_REDIRECT, T_SW, "rx_xdp_redirect", }, 4117d51a015SLorenzo Bianconi { ETHTOOL_XDP_PASS, T_SW, "rx_xdp_pass", }, 4127d51a015SLorenzo Bianconi { ETHTOOL_XDP_DROP, T_SW, "rx_xdp_drop", }, 4137d51a015SLorenzo Bianconi { ETHTOOL_XDP_TX, T_SW, "rx_xdp_tx", }, 41415070919SJesper Dangaard Brouer { ETHTOOL_XDP_TX_ERR, T_SW, "rx_xdp_tx_errors", }, 4157d51a015SLorenzo Bianconi { ETHTOOL_XDP_XMIT, T_SW, "tx_xdp_xmit", }, 41615070919SJesper Dangaard Brouer { ETHTOOL_XDP_XMIT_ERR, T_SW, "tx_xdp_xmit_errors", }, 4179b0cdefaSRussell King }; 4189b0cdefaSRussell King 419320d5441SLorenzo Bianconi struct mvneta_stats { 420320d5441SLorenzo Bianconi u64 rx_packets; 421320d5441SLorenzo Bianconi u64 rx_bytes; 422320d5441SLorenzo Bianconi u64 tx_packets; 423320d5441SLorenzo Bianconi u64 tx_bytes; 4243d866523SLorenzo Bianconi /* xdp */ 4253d866523SLorenzo Bianconi u64 xdp_redirect; 4263d866523SLorenzo Bianconi u64 xdp_pass; 4273d866523SLorenzo Bianconi u64 xdp_drop; 4287d51a015SLorenzo Bianconi u64 xdp_xmit; 42915070919SJesper Dangaard Brouer u64 xdp_xmit_err; 4303d866523SLorenzo Bianconi u64 xdp_tx; 43115070919SJesper Dangaard Brouer u64 xdp_tx_err; 432320d5441SLorenzo Bianconi }; 433320d5441SLorenzo Bianconi 4349ac41f3cSLorenzo Bianconi struct mvneta_ethtool_stats { 435320d5441SLorenzo Bianconi struct mvneta_stats ps; 4369ac41f3cSLorenzo Bianconi u64 skb_alloc_error; 4379ac41f3cSLorenzo Bianconi u64 refill_error; 4389ac41f3cSLorenzo Bianconi }; 4399ac41f3cSLorenzo Bianconi 44074c41b04Swilly tarreau struct mvneta_pcpu_stats { 441c5aff182SThomas Petazzoni struct u64_stats_sync syncp; 4429ac41f3cSLorenzo Bianconi 4439ac41f3cSLorenzo Bianconi struct mvneta_ethtool_stats es; 444c35947b8SLorenzo Bianconi u64 rx_dropped; 445c35947b8SLorenzo Bianconi u64 rx_errors; 446c5aff182SThomas Petazzoni }; 447c5aff182SThomas Petazzoni 44812bb03b4SMaxime Ripard struct mvneta_pcpu_port { 44912bb03b4SMaxime Ripard /* Pointer to the shared port */ 45012bb03b4SMaxime Ripard struct mvneta_port *pp; 45112bb03b4SMaxime Ripard 45212bb03b4SMaxime Ripard /* Pointer to the CPU-local NAPI struct */ 45312bb03b4SMaxime Ripard struct napi_struct napi; 45412bb03b4SMaxime Ripard 45512bb03b4SMaxime Ripard /* Cause of the previous interrupt */ 45612bb03b4SMaxime Ripard u32 cause_rx_tx; 45712bb03b4SMaxime Ripard }; 45812bb03b4SMaxime Ripard 45962a502ccSLorenzo Bianconi enum { 46062a502ccSLorenzo Bianconi __MVNETA_DOWN, 46162a502ccSLorenzo Bianconi }; 46262a502ccSLorenzo Bianconi 463c5aff182SThomas Petazzoni struct mvneta_port { 464dc35a10fSMarcin Wojtas u8 id; 46512bb03b4SMaxime Ripard struct mvneta_pcpu_port __percpu *ports; 46612bb03b4SMaxime Ripard struct mvneta_pcpu_stats __percpu *stats; 46712bb03b4SMaxime Ripard 46862a502ccSLorenzo Bianconi unsigned long state; 46962a502ccSLorenzo Bianconi 470c5aff182SThomas Petazzoni int pkt_size; 471c5aff182SThomas Petazzoni void __iomem *base; 472c5aff182SThomas Petazzoni struct mvneta_rx_queue *rxqs; 473c5aff182SThomas Petazzoni struct mvneta_tx_queue *txqs; 474c5aff182SThomas Petazzoni struct net_device *dev; 47584a3f4dbSSebastian Andrzej Siewior struct hlist_node node_online; 47684a3f4dbSSebastian Andrzej Siewior struct hlist_node node_dead; 47790b74c01SGregory CLEMENT int rxq_def; 4785888511eSGregory CLEMENT /* Protect the access to the percpu interrupt registers, 4795888511eSGregory CLEMENT * ensuring that the configuration remains coherent. 4805888511eSGregory CLEMENT */ 4815888511eSGregory CLEMENT spinlock_t lock; 482120cfa50SGregory CLEMENT bool is_stopped; 483c5aff182SThomas Petazzoni 4842636ac3cSMarcin Wojtas u32 cause_rx_tx; 4852636ac3cSMarcin Wojtas struct napi_struct napi; 4862636ac3cSMarcin Wojtas 4870db51da7SLorenzo Bianconi struct bpf_prog *xdp_prog; 4880db51da7SLorenzo Bianconi 489c5aff182SThomas Petazzoni /* Core clock */ 490189dd626SThomas Petazzoni struct clk *clk; 49115cc4a4aSJisheng Zhang /* AXI clock */ 49215cc4a4aSJisheng Zhang struct clk *clk_bus; 493c5aff182SThomas Petazzoni u8 mcast_count[256]; 494c5aff182SThomas Petazzoni u16 tx_ring_size; 495c5aff182SThomas Petazzoni u16 rx_ring_size; 4964906887aSMaxime Chevallier u8 prio_tc_map[8]; 497c5aff182SThomas Petazzoni 498c5aff182SThomas Petazzoni phy_interface_t phy_interface; 499503f9aa9SRussell King struct device_node *dn; 500b65657fcSSimon Guinot unsigned int tx_csum_limit; 501503f9aa9SRussell King struct phylink *phylink; 50244cc27e4SIoana Ciornei struct phylink_config phylink_config; 503a10c1c81SRussell King struct phy *comphy; 5049b0cdefaSRussell King 505dc35a10fSMarcin Wojtas struct mvneta_bm *bm_priv; 506dc35a10fSMarcin Wojtas struct mvneta_bm_pool *pool_long; 507dc35a10fSMarcin Wojtas struct mvneta_bm_pool *pool_short; 508dc35a10fSMarcin Wojtas int bm_win_id; 509dc35a10fSMarcin Wojtas 5106d81f451SRussell King bool eee_enabled; 5116d81f451SRussell King bool eee_active; 5126d81f451SRussell King bool tx_lpi_enabled; 5136d81f451SRussell King 5149b0cdefaSRussell King u64 ethtool_stats[ARRAY_SIZE(mvneta_statistics)]; 5159a401deaSGregory CLEMENT 5169a401deaSGregory CLEMENT u32 indir[MVNETA_RSS_LU_TABLE_SIZE]; 5172636ac3cSMarcin Wojtas 5182636ac3cSMarcin Wojtas /* Flags for special SoC configurations */ 5192636ac3cSMarcin Wojtas bool neta_armada3700; 5208d5047cfSMarcin Wojtas u16 rx_offset_correction; 5219768b45cSJane Li const struct mbus_dram_target_info *dram_target_info; 522c5aff182SThomas Petazzoni }; 523c5aff182SThomas Petazzoni 5246a20c175SThomas Petazzoni /* The mvneta_tx_desc and mvneta_rx_desc structures describe the 525c5aff182SThomas Petazzoni * layout of the transmit and reception DMA descriptors, and their 526c5aff182SThomas Petazzoni * layout is therefore defined by the hardware design 527c5aff182SThomas Petazzoni */ 5286083ed44SThomas Petazzoni 529c5aff182SThomas Petazzoni #define MVNETA_TX_L3_OFF_SHIFT 0 530c5aff182SThomas Petazzoni #define MVNETA_TX_IP_HLEN_SHIFT 8 531c5aff182SThomas Petazzoni #define MVNETA_TX_L4_UDP BIT(16) 532c5aff182SThomas Petazzoni #define MVNETA_TX_L3_IP6 BIT(17) 533c5aff182SThomas Petazzoni #define MVNETA_TXD_IP_CSUM BIT(18) 534c5aff182SThomas Petazzoni #define MVNETA_TXD_Z_PAD BIT(19) 535c5aff182SThomas Petazzoni #define MVNETA_TXD_L_DESC BIT(20) 536c5aff182SThomas Petazzoni #define MVNETA_TXD_F_DESC BIT(21) 537c5aff182SThomas Petazzoni #define MVNETA_TXD_FLZ_DESC (MVNETA_TXD_Z_PAD | \ 538c5aff182SThomas Petazzoni MVNETA_TXD_L_DESC | \ 539c5aff182SThomas Petazzoni MVNETA_TXD_F_DESC) 540c5aff182SThomas Petazzoni #define MVNETA_TX_L4_CSUM_FULL BIT(30) 541c5aff182SThomas Petazzoni #define MVNETA_TX_L4_CSUM_NOT BIT(31) 542c5aff182SThomas Petazzoni 543c5aff182SThomas Petazzoni #define MVNETA_RXD_ERR_CRC 0x0 544dc35a10fSMarcin Wojtas #define MVNETA_RXD_BM_POOL_SHIFT 13 545dc35a10fSMarcin Wojtas #define MVNETA_RXD_BM_POOL_MASK (BIT(13) | BIT(14)) 546c5aff182SThomas Petazzoni #define MVNETA_RXD_ERR_SUMMARY BIT(16) 547c5aff182SThomas Petazzoni #define MVNETA_RXD_ERR_OVERRUN BIT(17) 548c5aff182SThomas Petazzoni #define MVNETA_RXD_ERR_LEN BIT(18) 549c5aff182SThomas Petazzoni #define MVNETA_RXD_ERR_RESOURCE (BIT(17) | BIT(18)) 550c5aff182SThomas Petazzoni #define MVNETA_RXD_ERR_CODE_MASK (BIT(17) | BIT(18)) 551c5aff182SThomas Petazzoni #define MVNETA_RXD_L3_IP4 BIT(25) 552562e2f46SYelena Krivosheev #define MVNETA_RXD_LAST_DESC BIT(26) 553562e2f46SYelena Krivosheev #define MVNETA_RXD_FIRST_DESC BIT(27) 554562e2f46SYelena Krivosheev #define MVNETA_RXD_FIRST_LAST_DESC (MVNETA_RXD_FIRST_DESC | \ 555562e2f46SYelena Krivosheev MVNETA_RXD_LAST_DESC) 556c5aff182SThomas Petazzoni #define MVNETA_RXD_L4_CSUM_OK BIT(30) 557c5aff182SThomas Petazzoni 5589ad8fef6SThomas Petazzoni #if defined(__LITTLE_ENDIAN) 5596083ed44SThomas Petazzoni struct mvneta_tx_desc { 5606083ed44SThomas Petazzoni u32 command; /* Options used by HW for packet transmitting.*/ 561fbd1d524SAlexandre Belloni u16 reserved1; /* csum_l4 (for future use) */ 5626083ed44SThomas Petazzoni u16 data_size; /* Data size of transmitted packet in bytes */ 5636083ed44SThomas Petazzoni u32 buf_phys_addr; /* Physical addr of transmitted buffer */ 5646083ed44SThomas Petazzoni u32 reserved2; /* hw_cmd - (for future use, PMT) */ 5656083ed44SThomas Petazzoni u32 reserved3[4]; /* Reserved - (for future use) */ 5666083ed44SThomas Petazzoni }; 5676083ed44SThomas Petazzoni 5686083ed44SThomas Petazzoni struct mvneta_rx_desc { 5696083ed44SThomas Petazzoni u32 status; /* Info about received packet */ 570c5aff182SThomas Petazzoni u16 reserved1; /* pnc_info - (for future use, PnC) */ 571c5aff182SThomas Petazzoni u16 data_size; /* Size of received packet in bytes */ 5726083ed44SThomas Petazzoni 573c5aff182SThomas Petazzoni u32 buf_phys_addr; /* Physical address of the buffer */ 574c5aff182SThomas Petazzoni u32 reserved2; /* pnc_flow_id (for future use, PnC) */ 5756083ed44SThomas Petazzoni 576c5aff182SThomas Petazzoni u32 buf_cookie; /* cookie for access to RX buffer in rx path */ 577c5aff182SThomas Petazzoni u16 reserved3; /* prefetch_cmd, for future use */ 578c5aff182SThomas Petazzoni u16 reserved4; /* csum_l4 - (for future use, PnC) */ 5796083ed44SThomas Petazzoni 580c5aff182SThomas Petazzoni u32 reserved5; /* pnc_extra PnC (for future use, PnC) */ 581c5aff182SThomas Petazzoni u32 reserved6; /* hw_cmd (for future use, PnC and HWF) */ 582c5aff182SThomas Petazzoni }; 5839ad8fef6SThomas Petazzoni #else 5849ad8fef6SThomas Petazzoni struct mvneta_tx_desc { 5859ad8fef6SThomas Petazzoni u16 data_size; /* Data size of transmitted packet in bytes */ 586fbd1d524SAlexandre Belloni u16 reserved1; /* csum_l4 (for future use) */ 5879ad8fef6SThomas Petazzoni u32 command; /* Options used by HW for packet transmitting.*/ 5889ad8fef6SThomas Petazzoni u32 reserved2; /* hw_cmd - (for future use, PMT) */ 5899ad8fef6SThomas Petazzoni u32 buf_phys_addr; /* Physical addr of transmitted buffer */ 5909ad8fef6SThomas Petazzoni u32 reserved3[4]; /* Reserved - (for future use) */ 5919ad8fef6SThomas Petazzoni }; 5929ad8fef6SThomas Petazzoni 5939ad8fef6SThomas Petazzoni struct mvneta_rx_desc { 5949ad8fef6SThomas Petazzoni u16 data_size; /* Size of received packet in bytes */ 5959ad8fef6SThomas Petazzoni u16 reserved1; /* pnc_info - (for future use, PnC) */ 5969ad8fef6SThomas Petazzoni u32 status; /* Info about received packet */ 5979ad8fef6SThomas Petazzoni 5989ad8fef6SThomas Petazzoni u32 reserved2; /* pnc_flow_id (for future use, PnC) */ 5999ad8fef6SThomas Petazzoni u32 buf_phys_addr; /* Physical address of the buffer */ 6009ad8fef6SThomas Petazzoni 6019ad8fef6SThomas Petazzoni u16 reserved4; /* csum_l4 - (for future use, PnC) */ 6029ad8fef6SThomas Petazzoni u16 reserved3; /* prefetch_cmd, for future use */ 6039ad8fef6SThomas Petazzoni u32 buf_cookie; /* cookie for access to RX buffer in rx path */ 6049ad8fef6SThomas Petazzoni 6059ad8fef6SThomas Petazzoni u32 reserved5; /* pnc_extra PnC (for future use, PnC) */ 6069ad8fef6SThomas Petazzoni u32 reserved6; /* hw_cmd (for future use, PnC and HWF) */ 6079ad8fef6SThomas Petazzoni }; 6089ad8fef6SThomas Petazzoni #endif 609c5aff182SThomas Petazzoni 6109e58c8b4SLorenzo Bianconi enum mvneta_tx_buf_type { 6119e58c8b4SLorenzo Bianconi MVNETA_TYPE_SKB, 6129e58c8b4SLorenzo Bianconi MVNETA_TYPE_XDP_TX, 6139e58c8b4SLorenzo Bianconi MVNETA_TYPE_XDP_NDO, 6149e58c8b4SLorenzo Bianconi }; 6159e58c8b4SLorenzo Bianconi 6169e58c8b4SLorenzo Bianconi struct mvneta_tx_buf { 6179e58c8b4SLorenzo Bianconi enum mvneta_tx_buf_type type; 6189e58c8b4SLorenzo Bianconi union { 6199e58c8b4SLorenzo Bianconi struct xdp_frame *xdpf; 6209e58c8b4SLorenzo Bianconi struct sk_buff *skb; 6219e58c8b4SLorenzo Bianconi }; 6229e58c8b4SLorenzo Bianconi }; 6239e58c8b4SLorenzo Bianconi 624c5aff182SThomas Petazzoni struct mvneta_tx_queue { 625c5aff182SThomas Petazzoni /* Number of this TX queue, in the range 0-7 */ 626c5aff182SThomas Petazzoni u8 id; 627c5aff182SThomas Petazzoni 628c5aff182SThomas Petazzoni /* Number of TX DMA descriptors in the descriptor ring */ 629c5aff182SThomas Petazzoni int size; 630c5aff182SThomas Petazzoni 631c5aff182SThomas Petazzoni /* Number of currently used TX DMA descriptor in the 6326a20c175SThomas Petazzoni * descriptor ring 6336a20c175SThomas Petazzoni */ 634c5aff182SThomas Petazzoni int count; 6352a90f7e1SSimon Guinot int pending; 6368eef5f97SEzequiel Garcia int tx_stop_threshold; 6378eef5f97SEzequiel Garcia int tx_wake_threshold; 638c5aff182SThomas Petazzoni 6399e58c8b4SLorenzo Bianconi /* Array of transmitted buffers */ 6409e58c8b4SLorenzo Bianconi struct mvneta_tx_buf *buf; 641c5aff182SThomas Petazzoni 642c5aff182SThomas Petazzoni /* Index of last TX DMA descriptor that was inserted */ 643c5aff182SThomas Petazzoni int txq_put_index; 644c5aff182SThomas Petazzoni 645c5aff182SThomas Petazzoni /* Index of the TX DMA descriptor to be cleaned up */ 646c5aff182SThomas Petazzoni int txq_get_index; 647c5aff182SThomas Petazzoni 648c5aff182SThomas Petazzoni u32 done_pkts_coal; 649c5aff182SThomas Petazzoni 650c5aff182SThomas Petazzoni /* Virtual address of the TX DMA descriptors array */ 651c5aff182SThomas Petazzoni struct mvneta_tx_desc *descs; 652c5aff182SThomas Petazzoni 653c5aff182SThomas Petazzoni /* DMA address of the TX DMA descriptors array */ 654c5aff182SThomas Petazzoni dma_addr_t descs_phys; 655c5aff182SThomas Petazzoni 656c5aff182SThomas Petazzoni /* Index of the last TX DMA descriptor */ 657c5aff182SThomas Petazzoni int last_desc; 658c5aff182SThomas Petazzoni 659c5aff182SThomas Petazzoni /* Index of the next TX DMA descriptor to process */ 660c5aff182SThomas Petazzoni int next_desc_to_proc; 6612adb719dSEzequiel Garcia 6622adb719dSEzequiel Garcia /* DMA buffers for TSO headers */ 6632adb719dSEzequiel Garcia char *tso_hdrs; 6642adb719dSEzequiel Garcia 6652adb719dSEzequiel Garcia /* DMA address of TSO headers */ 6662adb719dSEzequiel Garcia dma_addr_t tso_hdrs_phys; 66750bf8cb6SGregory CLEMENT 66850bf8cb6SGregory CLEMENT /* Affinity mask for CPUs*/ 66950bf8cb6SGregory CLEMENT cpumask_t affinity_mask; 670c5aff182SThomas Petazzoni }; 671c5aff182SThomas Petazzoni 672c5aff182SThomas Petazzoni struct mvneta_rx_queue { 673c5aff182SThomas Petazzoni /* rx queue number, in the range 0-7 */ 674c5aff182SThomas Petazzoni u8 id; 675c5aff182SThomas Petazzoni 676c5aff182SThomas Petazzoni /* num of rx descriptors in the rx descriptor ring */ 677c5aff182SThomas Petazzoni int size; 678c5aff182SThomas Petazzoni 679c5aff182SThomas Petazzoni u32 pkts_coal; 680c5aff182SThomas Petazzoni u32 time_coal; 681c5aff182SThomas Petazzoni 682568a3fa2SLorenzo Bianconi /* page_pool */ 683568a3fa2SLorenzo Bianconi struct page_pool *page_pool; 684568a3fa2SLorenzo Bianconi struct xdp_rxq_info xdp_rxq; 685568a3fa2SLorenzo Bianconi 686f88bee1cSGregory CLEMENT /* Virtual address of the RX buffer */ 687f88bee1cSGregory CLEMENT void **buf_virt_addr; 688f88bee1cSGregory CLEMENT 689c5aff182SThomas Petazzoni /* Virtual address of the RX DMA descriptors array */ 690c5aff182SThomas Petazzoni struct mvneta_rx_desc *descs; 691c5aff182SThomas Petazzoni 692c5aff182SThomas Petazzoni /* DMA address of the RX DMA descriptors array */ 693c5aff182SThomas Petazzoni dma_addr_t descs_phys; 694c5aff182SThomas Petazzoni 695c5aff182SThomas Petazzoni /* Index of the last RX DMA descriptor */ 696c5aff182SThomas Petazzoni int last_desc; 697c5aff182SThomas Petazzoni 698c5aff182SThomas Petazzoni /* Index of the next RX DMA descriptor to process */ 699c5aff182SThomas Petazzoni int next_desc_to_proc; 70017a96da6SGregory CLEMENT 701562e2f46SYelena Krivosheev /* Index of first RX DMA descriptor to refill */ 702562e2f46SYelena Krivosheev int first_to_refill; 703562e2f46SYelena Krivosheev u32 refill_num; 704c5aff182SThomas Petazzoni }; 705c5aff182SThomas Petazzoni 70684a3f4dbSSebastian Andrzej Siewior static enum cpuhp_state online_hpstate; 707edadb7faSEzequiel Garcia /* The hardware supports eight (8) rx queues, but we are only allowing 708edadb7faSEzequiel Garcia * the first one to be used. Therefore, let's just allocate one queue. 709edadb7faSEzequiel Garcia */ 710d8936657SMaxime Ripard static int rxq_number = 8; 711c5aff182SThomas Petazzoni static int txq_number = 8; 712c5aff182SThomas Petazzoni 713c5aff182SThomas Petazzoni static int rxq_def; 714c5aff182SThomas Petazzoni 715f19fadfcSwilly tarreau static int rx_copybreak __read_mostly = 256; 716f19fadfcSwilly tarreau 717dc35a10fSMarcin Wojtas /* HW BM need that each port be identify by a unique ID */ 718dc35a10fSMarcin Wojtas static int global_port_id; 719dc35a10fSMarcin Wojtas 720c5aff182SThomas Petazzoni #define MVNETA_DRIVER_NAME "mvneta" 721c5aff182SThomas Petazzoni #define MVNETA_DRIVER_VERSION "1.0" 722c5aff182SThomas Petazzoni 723c5aff182SThomas Petazzoni /* Utility/helper methods */ 724c5aff182SThomas Petazzoni 725c5aff182SThomas Petazzoni /* Write helper method */ 726c5aff182SThomas Petazzoni static void mvreg_write(struct mvneta_port *pp, u32 offset, u32 data) 727c5aff182SThomas Petazzoni { 728c5aff182SThomas Petazzoni writel(data, pp->base + offset); 729c5aff182SThomas Petazzoni } 730c5aff182SThomas Petazzoni 731c5aff182SThomas Petazzoni /* Read helper method */ 732c5aff182SThomas Petazzoni static u32 mvreg_read(struct mvneta_port *pp, u32 offset) 733c5aff182SThomas Petazzoni { 734c5aff182SThomas Petazzoni return readl(pp->base + offset); 735c5aff182SThomas Petazzoni } 736c5aff182SThomas Petazzoni 737c5aff182SThomas Petazzoni /* Increment txq get counter */ 738c5aff182SThomas Petazzoni static void mvneta_txq_inc_get(struct mvneta_tx_queue *txq) 739c5aff182SThomas Petazzoni { 740c5aff182SThomas Petazzoni txq->txq_get_index++; 741c5aff182SThomas Petazzoni if (txq->txq_get_index == txq->size) 742c5aff182SThomas Petazzoni txq->txq_get_index = 0; 743c5aff182SThomas Petazzoni } 744c5aff182SThomas Petazzoni 745c5aff182SThomas Petazzoni /* Increment txq put counter */ 746c5aff182SThomas Petazzoni static void mvneta_txq_inc_put(struct mvneta_tx_queue *txq) 747c5aff182SThomas Petazzoni { 748c5aff182SThomas Petazzoni txq->txq_put_index++; 749c5aff182SThomas Petazzoni if (txq->txq_put_index == txq->size) 750c5aff182SThomas Petazzoni txq->txq_put_index = 0; 751c5aff182SThomas Petazzoni } 752c5aff182SThomas Petazzoni 753c5aff182SThomas Petazzoni 754c5aff182SThomas Petazzoni /* Clear all MIB counters */ 755c5aff182SThomas Petazzoni static void mvneta_mib_counters_clear(struct mvneta_port *pp) 756c5aff182SThomas Petazzoni { 757c5aff182SThomas Petazzoni int i; 758c5aff182SThomas Petazzoni 759c5aff182SThomas Petazzoni /* Perform dummy reads from MIB counters */ 760c5aff182SThomas Petazzoni for (i = 0; i < MVNETA_MIB_LATE_COLLISION; i += 4) 761098c2fc6SZhang Changzhong mvreg_read(pp, (MVNETA_MIB_COUNTERS_BASE + i)); 762098c2fc6SZhang Changzhong mvreg_read(pp, MVNETA_RX_DISCARD_FRAME_COUNT); 763098c2fc6SZhang Changzhong mvreg_read(pp, MVNETA_OVERRUN_FRAME_COUNT); 764c5aff182SThomas Petazzoni } 765c5aff182SThomas Petazzoni 766c5aff182SThomas Petazzoni /* Get System Network Statistics */ 767bc1f4470Sstephen hemminger static void 7682dc0d2b4SBaoyou Xie mvneta_get_stats64(struct net_device *dev, 769c5aff182SThomas Petazzoni struct rtnl_link_stats64 *stats) 770c5aff182SThomas Petazzoni { 771c5aff182SThomas Petazzoni struct mvneta_port *pp = netdev_priv(dev); 772c5aff182SThomas Petazzoni unsigned int start; 77374c41b04Swilly tarreau int cpu; 774c5aff182SThomas Petazzoni 77574c41b04Swilly tarreau for_each_possible_cpu(cpu) { 77674c41b04Swilly tarreau struct mvneta_pcpu_stats *cpu_stats; 77774c41b04Swilly tarreau u64 rx_packets; 77874c41b04Swilly tarreau u64 rx_bytes; 779c35947b8SLorenzo Bianconi u64 rx_dropped; 780c35947b8SLorenzo Bianconi u64 rx_errors; 78174c41b04Swilly tarreau u64 tx_packets; 78274c41b04Swilly tarreau u64 tx_bytes; 783c5aff182SThomas Petazzoni 78474c41b04Swilly tarreau cpu_stats = per_cpu_ptr(pp->stats, cpu); 785c5aff182SThomas Petazzoni do { 78657a7744eSEric W. Biederman start = u64_stats_fetch_begin_irq(&cpu_stats->syncp); 787320d5441SLorenzo Bianconi rx_packets = cpu_stats->es.ps.rx_packets; 788320d5441SLorenzo Bianconi rx_bytes = cpu_stats->es.ps.rx_bytes; 789c35947b8SLorenzo Bianconi rx_dropped = cpu_stats->rx_dropped; 790c35947b8SLorenzo Bianconi rx_errors = cpu_stats->rx_errors; 791320d5441SLorenzo Bianconi tx_packets = cpu_stats->es.ps.tx_packets; 792320d5441SLorenzo Bianconi tx_bytes = cpu_stats->es.ps.tx_bytes; 79357a7744eSEric W. Biederman } while (u64_stats_fetch_retry_irq(&cpu_stats->syncp, start)); 794c5aff182SThomas Petazzoni 79574c41b04Swilly tarreau stats->rx_packets += rx_packets; 79674c41b04Swilly tarreau stats->rx_bytes += rx_bytes; 797c35947b8SLorenzo Bianconi stats->rx_dropped += rx_dropped; 798c35947b8SLorenzo Bianconi stats->rx_errors += rx_errors; 79974c41b04Swilly tarreau stats->tx_packets += tx_packets; 80074c41b04Swilly tarreau stats->tx_bytes += tx_bytes; 80174c41b04Swilly tarreau } 802c5aff182SThomas Petazzoni 803c5aff182SThomas Petazzoni stats->tx_dropped = dev->stats.tx_dropped; 804c5aff182SThomas Petazzoni } 805c5aff182SThomas Petazzoni 806c5aff182SThomas Petazzoni /* Rx descriptors helper methods */ 807c5aff182SThomas Petazzoni 8085428213cSwilly tarreau /* Checks whether the RX descriptor having this status is both the first 8095428213cSwilly tarreau * and the last descriptor for the RX packet. Each RX packet is currently 810c5aff182SThomas Petazzoni * received through a single RX descriptor, so not having each RX 811c5aff182SThomas Petazzoni * descriptor with its first and last bits set is an error 812c5aff182SThomas Petazzoni */ 8135428213cSwilly tarreau static int mvneta_rxq_desc_is_first_last(u32 status) 814c5aff182SThomas Petazzoni { 8155428213cSwilly tarreau return (status & MVNETA_RXD_FIRST_LAST_DESC) == 816c5aff182SThomas Petazzoni MVNETA_RXD_FIRST_LAST_DESC; 817c5aff182SThomas Petazzoni } 818c5aff182SThomas Petazzoni 819c5aff182SThomas Petazzoni /* Add number of descriptors ready to receive new packets */ 820c5aff182SThomas Petazzoni static void mvneta_rxq_non_occup_desc_add(struct mvneta_port *pp, 821c5aff182SThomas Petazzoni struct mvneta_rx_queue *rxq, 822c5aff182SThomas Petazzoni int ndescs) 823c5aff182SThomas Petazzoni { 824c5aff182SThomas Petazzoni /* Only MVNETA_RXQ_ADD_NON_OCCUPIED_MAX (255) descriptors can 8256a20c175SThomas Petazzoni * be added at once 8266a20c175SThomas Petazzoni */ 827c5aff182SThomas Petazzoni while (ndescs > MVNETA_RXQ_ADD_NON_OCCUPIED_MAX) { 828c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id), 829c5aff182SThomas Petazzoni (MVNETA_RXQ_ADD_NON_OCCUPIED_MAX << 830c5aff182SThomas Petazzoni MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT)); 831c5aff182SThomas Petazzoni ndescs -= MVNETA_RXQ_ADD_NON_OCCUPIED_MAX; 832c5aff182SThomas Petazzoni } 833c5aff182SThomas Petazzoni 834c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id), 835c5aff182SThomas Petazzoni (ndescs << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT)); 836c5aff182SThomas Petazzoni } 837c5aff182SThomas Petazzoni 838c5aff182SThomas Petazzoni /* Get number of RX descriptors occupied by received packets */ 839c5aff182SThomas Petazzoni static int mvneta_rxq_busy_desc_num_get(struct mvneta_port *pp, 840c5aff182SThomas Petazzoni struct mvneta_rx_queue *rxq) 841c5aff182SThomas Petazzoni { 842c5aff182SThomas Petazzoni u32 val; 843c5aff182SThomas Petazzoni 844c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_RXQ_STATUS_REG(rxq->id)); 845c5aff182SThomas Petazzoni return val & MVNETA_RXQ_OCCUPIED_ALL_MASK; 846c5aff182SThomas Petazzoni } 847c5aff182SThomas Petazzoni 8486a20c175SThomas Petazzoni /* Update num of rx desc called upon return from rx path or 849c5aff182SThomas Petazzoni * from mvneta_rxq_drop_pkts(). 850c5aff182SThomas Petazzoni */ 851c5aff182SThomas Petazzoni static void mvneta_rxq_desc_num_update(struct mvneta_port *pp, 852c5aff182SThomas Petazzoni struct mvneta_rx_queue *rxq, 853c5aff182SThomas Petazzoni int rx_done, int rx_filled) 854c5aff182SThomas Petazzoni { 855c5aff182SThomas Petazzoni u32 val; 856c5aff182SThomas Petazzoni 857c5aff182SThomas Petazzoni if ((rx_done <= 0xff) && (rx_filled <= 0xff)) { 858c5aff182SThomas Petazzoni val = rx_done | 859c5aff182SThomas Petazzoni (rx_filled << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT); 860c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id), val); 861c5aff182SThomas Petazzoni return; 862c5aff182SThomas Petazzoni } 863c5aff182SThomas Petazzoni 864c5aff182SThomas Petazzoni /* Only 255 descriptors can be added at once */ 865c5aff182SThomas Petazzoni while ((rx_done > 0) || (rx_filled > 0)) { 866c5aff182SThomas Petazzoni if (rx_done <= 0xff) { 867c5aff182SThomas Petazzoni val = rx_done; 868c5aff182SThomas Petazzoni rx_done = 0; 869c5aff182SThomas Petazzoni } else { 870c5aff182SThomas Petazzoni val = 0xff; 871c5aff182SThomas Petazzoni rx_done -= 0xff; 872c5aff182SThomas Petazzoni } 873c5aff182SThomas Petazzoni if (rx_filled <= 0xff) { 874c5aff182SThomas Petazzoni val |= rx_filled << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT; 875c5aff182SThomas Petazzoni rx_filled = 0; 876c5aff182SThomas Petazzoni } else { 877c5aff182SThomas Petazzoni val |= 0xff << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT; 878c5aff182SThomas Petazzoni rx_filled -= 0xff; 879c5aff182SThomas Petazzoni } 880c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id), val); 881c5aff182SThomas Petazzoni } 882c5aff182SThomas Petazzoni } 883c5aff182SThomas Petazzoni 884c5aff182SThomas Petazzoni /* Get pointer to next RX descriptor to be processed by SW */ 885c5aff182SThomas Petazzoni static struct mvneta_rx_desc * 886c5aff182SThomas Petazzoni mvneta_rxq_next_desc_get(struct mvneta_rx_queue *rxq) 887c5aff182SThomas Petazzoni { 888c5aff182SThomas Petazzoni int rx_desc = rxq->next_desc_to_proc; 889c5aff182SThomas Petazzoni 890c5aff182SThomas Petazzoni rxq->next_desc_to_proc = MVNETA_QUEUE_NEXT_DESC(rxq, rx_desc); 89134e4179dSwilly tarreau prefetch(rxq->descs + rxq->next_desc_to_proc); 892c5aff182SThomas Petazzoni return rxq->descs + rx_desc; 893c5aff182SThomas Petazzoni } 894c5aff182SThomas Petazzoni 895c5aff182SThomas Petazzoni /* Change maximum receive size of the port. */ 896c5aff182SThomas Petazzoni static void mvneta_max_rx_size_set(struct mvneta_port *pp, int max_rx_size) 897c5aff182SThomas Petazzoni { 898c5aff182SThomas Petazzoni u32 val; 899c5aff182SThomas Petazzoni 900c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_GMAC_CTRL_0); 901c5aff182SThomas Petazzoni val &= ~MVNETA_GMAC_MAX_RX_SIZE_MASK; 902c5aff182SThomas Petazzoni val |= ((max_rx_size - MVNETA_MH_SIZE) / 2) << 903c5aff182SThomas Petazzoni MVNETA_GMAC_MAX_RX_SIZE_SHIFT; 904c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_GMAC_CTRL_0, val); 905c5aff182SThomas Petazzoni } 906c5aff182SThomas Petazzoni 907c5aff182SThomas Petazzoni 908c5aff182SThomas Petazzoni /* Set rx queue offset */ 909c5aff182SThomas Petazzoni static void mvneta_rxq_offset_set(struct mvneta_port *pp, 910c5aff182SThomas Petazzoni struct mvneta_rx_queue *rxq, 911c5aff182SThomas Petazzoni int offset) 912c5aff182SThomas Petazzoni { 913c5aff182SThomas Petazzoni u32 val; 914c5aff182SThomas Petazzoni 915c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_RXQ_CONFIG_REG(rxq->id)); 916c5aff182SThomas Petazzoni val &= ~MVNETA_RXQ_PKT_OFFSET_ALL_MASK; 917c5aff182SThomas Petazzoni 918c5aff182SThomas Petazzoni /* Offset is in */ 919c5aff182SThomas Petazzoni val |= MVNETA_RXQ_PKT_OFFSET_MASK(offset >> 3); 920c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_RXQ_CONFIG_REG(rxq->id), val); 921c5aff182SThomas Petazzoni } 922c5aff182SThomas Petazzoni 923c5aff182SThomas Petazzoni 924c5aff182SThomas Petazzoni /* Tx descriptors helper methods */ 925c5aff182SThomas Petazzoni 926c5aff182SThomas Petazzoni /* Update HW with number of TX descriptors to be sent */ 927c5aff182SThomas Petazzoni static void mvneta_txq_pend_desc_add(struct mvneta_port *pp, 928c5aff182SThomas Petazzoni struct mvneta_tx_queue *txq, 929c5aff182SThomas Petazzoni int pend_desc) 930c5aff182SThomas Petazzoni { 931c5aff182SThomas Petazzoni u32 val; 932c5aff182SThomas Petazzoni 9330d63785cSSimon Guinot pend_desc += txq->pending; 9340d63785cSSimon Guinot 9350d63785cSSimon Guinot /* Only 255 Tx descriptors can be added at once */ 9360d63785cSSimon Guinot do { 9370d63785cSSimon Guinot val = min(pend_desc, 255); 938c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val); 9390d63785cSSimon Guinot pend_desc -= val; 9400d63785cSSimon Guinot } while (pend_desc > 0); 9412a90f7e1SSimon Guinot txq->pending = 0; 942c5aff182SThomas Petazzoni } 943c5aff182SThomas Petazzoni 944c5aff182SThomas Petazzoni /* Get pointer to next TX descriptor to be processed (send) by HW */ 945c5aff182SThomas Petazzoni static struct mvneta_tx_desc * 946c5aff182SThomas Petazzoni mvneta_txq_next_desc_get(struct mvneta_tx_queue *txq) 947c5aff182SThomas Petazzoni { 948c5aff182SThomas Petazzoni int tx_desc = txq->next_desc_to_proc; 949c5aff182SThomas Petazzoni 950c5aff182SThomas Petazzoni txq->next_desc_to_proc = MVNETA_QUEUE_NEXT_DESC(txq, tx_desc); 951c5aff182SThomas Petazzoni return txq->descs + tx_desc; 952c5aff182SThomas Petazzoni } 953c5aff182SThomas Petazzoni 954c5aff182SThomas Petazzoni /* Release the last allocated TX descriptor. Useful to handle DMA 9556a20c175SThomas Petazzoni * mapping failures in the TX path. 9566a20c175SThomas Petazzoni */ 957c5aff182SThomas Petazzoni static void mvneta_txq_desc_put(struct mvneta_tx_queue *txq) 958c5aff182SThomas Petazzoni { 959c5aff182SThomas Petazzoni if (txq->next_desc_to_proc == 0) 960c5aff182SThomas Petazzoni txq->next_desc_to_proc = txq->last_desc - 1; 961c5aff182SThomas Petazzoni else 962c5aff182SThomas Petazzoni txq->next_desc_to_proc--; 963c5aff182SThomas Petazzoni } 964c5aff182SThomas Petazzoni 965c5aff182SThomas Petazzoni /* Set rxq buf size */ 966c5aff182SThomas Petazzoni static void mvneta_rxq_buf_size_set(struct mvneta_port *pp, 967c5aff182SThomas Petazzoni struct mvneta_rx_queue *rxq, 968c5aff182SThomas Petazzoni int buf_size) 969c5aff182SThomas Petazzoni { 970c5aff182SThomas Petazzoni u32 val; 971c5aff182SThomas Petazzoni 972c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_RXQ_SIZE_REG(rxq->id)); 973c5aff182SThomas Petazzoni 974c5aff182SThomas Petazzoni val &= ~MVNETA_RXQ_BUF_SIZE_MASK; 975c5aff182SThomas Petazzoni val |= ((buf_size >> 3) << MVNETA_RXQ_BUF_SIZE_SHIFT); 976c5aff182SThomas Petazzoni 977c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_RXQ_SIZE_REG(rxq->id), val); 978c5aff182SThomas Petazzoni } 979c5aff182SThomas Petazzoni 980c5aff182SThomas Petazzoni /* Disable buffer management (BM) */ 981c5aff182SThomas Petazzoni static void mvneta_rxq_bm_disable(struct mvneta_port *pp, 982c5aff182SThomas Petazzoni struct mvneta_rx_queue *rxq) 983c5aff182SThomas Petazzoni { 984c5aff182SThomas Petazzoni u32 val; 985c5aff182SThomas Petazzoni 986c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_RXQ_CONFIG_REG(rxq->id)); 987c5aff182SThomas Petazzoni val &= ~MVNETA_RXQ_HW_BUF_ALLOC; 988c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_RXQ_CONFIG_REG(rxq->id), val); 989c5aff182SThomas Petazzoni } 990c5aff182SThomas Petazzoni 991dc35a10fSMarcin Wojtas /* Enable buffer management (BM) */ 992dc35a10fSMarcin Wojtas static void mvneta_rxq_bm_enable(struct mvneta_port *pp, 993dc35a10fSMarcin Wojtas struct mvneta_rx_queue *rxq) 994dc35a10fSMarcin Wojtas { 995dc35a10fSMarcin Wojtas u32 val; 996dc35a10fSMarcin Wojtas 997dc35a10fSMarcin Wojtas val = mvreg_read(pp, MVNETA_RXQ_CONFIG_REG(rxq->id)); 998dc35a10fSMarcin Wojtas val |= MVNETA_RXQ_HW_BUF_ALLOC; 999dc35a10fSMarcin Wojtas mvreg_write(pp, MVNETA_RXQ_CONFIG_REG(rxq->id), val); 1000dc35a10fSMarcin Wojtas } 1001dc35a10fSMarcin Wojtas 1002dc35a10fSMarcin Wojtas /* Notify HW about port's assignment of pool for bigger packets */ 1003dc35a10fSMarcin Wojtas static void mvneta_rxq_long_pool_set(struct mvneta_port *pp, 1004dc35a10fSMarcin Wojtas struct mvneta_rx_queue *rxq) 1005dc35a10fSMarcin Wojtas { 1006dc35a10fSMarcin Wojtas u32 val; 1007dc35a10fSMarcin Wojtas 1008dc35a10fSMarcin Wojtas val = mvreg_read(pp, MVNETA_RXQ_CONFIG_REG(rxq->id)); 1009dc35a10fSMarcin Wojtas val &= ~MVNETA_RXQ_LONG_POOL_ID_MASK; 1010dc35a10fSMarcin Wojtas val |= (pp->pool_long->id << MVNETA_RXQ_LONG_POOL_ID_SHIFT); 1011dc35a10fSMarcin Wojtas 1012dc35a10fSMarcin Wojtas mvreg_write(pp, MVNETA_RXQ_CONFIG_REG(rxq->id), val); 1013dc35a10fSMarcin Wojtas } 1014dc35a10fSMarcin Wojtas 1015dc35a10fSMarcin Wojtas /* Notify HW about port's assignment of pool for smaller packets */ 1016dc35a10fSMarcin Wojtas static void mvneta_rxq_short_pool_set(struct mvneta_port *pp, 1017dc35a10fSMarcin Wojtas struct mvneta_rx_queue *rxq) 1018dc35a10fSMarcin Wojtas { 1019dc35a10fSMarcin Wojtas u32 val; 1020dc35a10fSMarcin Wojtas 1021dc35a10fSMarcin Wojtas val = mvreg_read(pp, MVNETA_RXQ_CONFIG_REG(rxq->id)); 1022dc35a10fSMarcin Wojtas val &= ~MVNETA_RXQ_SHORT_POOL_ID_MASK; 1023dc35a10fSMarcin Wojtas val |= (pp->pool_short->id << MVNETA_RXQ_SHORT_POOL_ID_SHIFT); 1024dc35a10fSMarcin Wojtas 1025dc35a10fSMarcin Wojtas mvreg_write(pp, MVNETA_RXQ_CONFIG_REG(rxq->id), val); 1026dc35a10fSMarcin Wojtas } 1027dc35a10fSMarcin Wojtas 1028dc35a10fSMarcin Wojtas /* Set port's receive buffer size for assigned BM pool */ 1029dc35a10fSMarcin Wojtas static inline void mvneta_bm_pool_bufsize_set(struct mvneta_port *pp, 1030dc35a10fSMarcin Wojtas int buf_size, 1031dc35a10fSMarcin Wojtas u8 pool_id) 1032dc35a10fSMarcin Wojtas { 1033dc35a10fSMarcin Wojtas u32 val; 1034dc35a10fSMarcin Wojtas 1035dc35a10fSMarcin Wojtas if (!IS_ALIGNED(buf_size, 8)) { 1036dc35a10fSMarcin Wojtas dev_warn(pp->dev->dev.parent, 1037dc35a10fSMarcin Wojtas "illegal buf_size value %d, round to %d\n", 1038dc35a10fSMarcin Wojtas buf_size, ALIGN(buf_size, 8)); 1039dc35a10fSMarcin Wojtas buf_size = ALIGN(buf_size, 8); 1040dc35a10fSMarcin Wojtas } 1041dc35a10fSMarcin Wojtas 1042dc35a10fSMarcin Wojtas val = mvreg_read(pp, MVNETA_PORT_POOL_BUFFER_SZ_REG(pool_id)); 1043dc35a10fSMarcin Wojtas val |= buf_size & MVNETA_PORT_POOL_BUFFER_SZ_MASK; 1044dc35a10fSMarcin Wojtas mvreg_write(pp, MVNETA_PORT_POOL_BUFFER_SZ_REG(pool_id), val); 1045dc35a10fSMarcin Wojtas } 1046dc35a10fSMarcin Wojtas 1047dc35a10fSMarcin Wojtas /* Configure MBUS window in order to enable access BM internal SRAM */ 1048dc35a10fSMarcin Wojtas static int mvneta_mbus_io_win_set(struct mvneta_port *pp, u32 base, u32 wsize, 1049dc35a10fSMarcin Wojtas u8 target, u8 attr) 1050dc35a10fSMarcin Wojtas { 1051dc35a10fSMarcin Wojtas u32 win_enable, win_protect; 1052dc35a10fSMarcin Wojtas int i; 1053dc35a10fSMarcin Wojtas 1054dc35a10fSMarcin Wojtas win_enable = mvreg_read(pp, MVNETA_BASE_ADDR_ENABLE); 1055dc35a10fSMarcin Wojtas 1056dc35a10fSMarcin Wojtas if (pp->bm_win_id < 0) { 1057dc35a10fSMarcin Wojtas /* Find first not occupied window */ 1058dc35a10fSMarcin Wojtas for (i = 0; i < MVNETA_MAX_DECODE_WIN; i++) { 1059dc35a10fSMarcin Wojtas if (win_enable & (1 << i)) { 1060dc35a10fSMarcin Wojtas pp->bm_win_id = i; 1061dc35a10fSMarcin Wojtas break; 1062dc35a10fSMarcin Wojtas } 1063dc35a10fSMarcin Wojtas } 1064dc35a10fSMarcin Wojtas if (i == MVNETA_MAX_DECODE_WIN) 1065dc35a10fSMarcin Wojtas return -ENOMEM; 1066dc35a10fSMarcin Wojtas } else { 1067dc35a10fSMarcin Wojtas i = pp->bm_win_id; 1068dc35a10fSMarcin Wojtas } 1069dc35a10fSMarcin Wojtas 1070dc35a10fSMarcin Wojtas mvreg_write(pp, MVNETA_WIN_BASE(i), 0); 1071dc35a10fSMarcin Wojtas mvreg_write(pp, MVNETA_WIN_SIZE(i), 0); 1072dc35a10fSMarcin Wojtas 1073dc35a10fSMarcin Wojtas if (i < 4) 1074dc35a10fSMarcin Wojtas mvreg_write(pp, MVNETA_WIN_REMAP(i), 0); 1075dc35a10fSMarcin Wojtas 1076dc35a10fSMarcin Wojtas mvreg_write(pp, MVNETA_WIN_BASE(i), (base & 0xffff0000) | 1077dc35a10fSMarcin Wojtas (attr << 8) | target); 1078dc35a10fSMarcin Wojtas 1079dc35a10fSMarcin Wojtas mvreg_write(pp, MVNETA_WIN_SIZE(i), (wsize - 1) & 0xffff0000); 1080dc35a10fSMarcin Wojtas 1081dc35a10fSMarcin Wojtas win_protect = mvreg_read(pp, MVNETA_ACCESS_PROTECT_ENABLE); 1082dc35a10fSMarcin Wojtas win_protect |= 3 << (2 * i); 1083dc35a10fSMarcin Wojtas mvreg_write(pp, MVNETA_ACCESS_PROTECT_ENABLE, win_protect); 1084dc35a10fSMarcin Wojtas 1085dc35a10fSMarcin Wojtas win_enable &= ~(1 << i); 1086dc35a10fSMarcin Wojtas mvreg_write(pp, MVNETA_BASE_ADDR_ENABLE, win_enable); 1087dc35a10fSMarcin Wojtas 1088dc35a10fSMarcin Wojtas return 0; 1089dc35a10fSMarcin Wojtas } 1090dc35a10fSMarcin Wojtas 10912636ac3cSMarcin Wojtas static int mvneta_bm_port_mbus_init(struct mvneta_port *pp) 1092dc35a10fSMarcin Wojtas { 10932636ac3cSMarcin Wojtas u32 wsize; 1094dc35a10fSMarcin Wojtas u8 target, attr; 1095dc35a10fSMarcin Wojtas int err; 1096dc35a10fSMarcin Wojtas 1097dc35a10fSMarcin Wojtas /* Get BM window information */ 1098dc35a10fSMarcin Wojtas err = mvebu_mbus_get_io_win_info(pp->bm_priv->bppi_phys_addr, &wsize, 1099dc35a10fSMarcin Wojtas &target, &attr); 1100dc35a10fSMarcin Wojtas if (err < 0) 1101dc35a10fSMarcin Wojtas return err; 1102dc35a10fSMarcin Wojtas 1103dc35a10fSMarcin Wojtas pp->bm_win_id = -1; 1104dc35a10fSMarcin Wojtas 1105dc35a10fSMarcin Wojtas /* Open NETA -> BM window */ 1106dc35a10fSMarcin Wojtas err = mvneta_mbus_io_win_set(pp, pp->bm_priv->bppi_phys_addr, wsize, 1107dc35a10fSMarcin Wojtas target, attr); 1108dc35a10fSMarcin Wojtas if (err < 0) { 1109dc35a10fSMarcin Wojtas netdev_info(pp->dev, "fail to configure mbus window to BM\n"); 1110dc35a10fSMarcin Wojtas return err; 1111dc35a10fSMarcin Wojtas } 11122636ac3cSMarcin Wojtas return 0; 11132636ac3cSMarcin Wojtas } 11142636ac3cSMarcin Wojtas 11152636ac3cSMarcin Wojtas /* Assign and initialize pools for port. In case of fail 11162636ac3cSMarcin Wojtas * buffer manager will remain disabled for current port. 11172636ac3cSMarcin Wojtas */ 11182636ac3cSMarcin Wojtas static int mvneta_bm_port_init(struct platform_device *pdev, 11192636ac3cSMarcin Wojtas struct mvneta_port *pp) 11202636ac3cSMarcin Wojtas { 11212636ac3cSMarcin Wojtas struct device_node *dn = pdev->dev.of_node; 11222636ac3cSMarcin Wojtas u32 long_pool_id, short_pool_id; 11232636ac3cSMarcin Wojtas 11242636ac3cSMarcin Wojtas if (!pp->neta_armada3700) { 11252636ac3cSMarcin Wojtas int ret; 11262636ac3cSMarcin Wojtas 11272636ac3cSMarcin Wojtas ret = mvneta_bm_port_mbus_init(pp); 11282636ac3cSMarcin Wojtas if (ret) 11292636ac3cSMarcin Wojtas return ret; 11302636ac3cSMarcin Wojtas } 1131dc35a10fSMarcin Wojtas 1132dc35a10fSMarcin Wojtas if (of_property_read_u32(dn, "bm,pool-long", &long_pool_id)) { 1133dc35a10fSMarcin Wojtas netdev_info(pp->dev, "missing long pool id\n"); 1134dc35a10fSMarcin Wojtas return -EINVAL; 1135dc35a10fSMarcin Wojtas } 1136dc35a10fSMarcin Wojtas 1137dc35a10fSMarcin Wojtas /* Create port's long pool depending on mtu */ 1138dc35a10fSMarcin Wojtas pp->pool_long = mvneta_bm_pool_use(pp->bm_priv, long_pool_id, 1139dc35a10fSMarcin Wojtas MVNETA_BM_LONG, pp->id, 1140dc35a10fSMarcin Wojtas MVNETA_RX_PKT_SIZE(pp->dev->mtu)); 1141dc35a10fSMarcin Wojtas if (!pp->pool_long) { 1142dc35a10fSMarcin Wojtas netdev_info(pp->dev, "fail to obtain long pool for port\n"); 1143dc35a10fSMarcin Wojtas return -ENOMEM; 1144dc35a10fSMarcin Wojtas } 1145dc35a10fSMarcin Wojtas 1146dc35a10fSMarcin Wojtas pp->pool_long->port_map |= 1 << pp->id; 1147dc35a10fSMarcin Wojtas 1148dc35a10fSMarcin Wojtas mvneta_bm_pool_bufsize_set(pp, pp->pool_long->buf_size, 1149dc35a10fSMarcin Wojtas pp->pool_long->id); 1150dc35a10fSMarcin Wojtas 1151dc35a10fSMarcin Wojtas /* If short pool id is not defined, assume using single pool */ 1152dc35a10fSMarcin Wojtas if (of_property_read_u32(dn, "bm,pool-short", &short_pool_id)) 1153dc35a10fSMarcin Wojtas short_pool_id = long_pool_id; 1154dc35a10fSMarcin Wojtas 1155dc35a10fSMarcin Wojtas /* Create port's short pool */ 1156dc35a10fSMarcin Wojtas pp->pool_short = mvneta_bm_pool_use(pp->bm_priv, short_pool_id, 1157dc35a10fSMarcin Wojtas MVNETA_BM_SHORT, pp->id, 1158dc35a10fSMarcin Wojtas MVNETA_BM_SHORT_PKT_SIZE); 1159dc35a10fSMarcin Wojtas if (!pp->pool_short) { 1160dc35a10fSMarcin Wojtas netdev_info(pp->dev, "fail to obtain short pool for port\n"); 1161dc35a10fSMarcin Wojtas mvneta_bm_pool_destroy(pp->bm_priv, pp->pool_long, 1 << pp->id); 1162dc35a10fSMarcin Wojtas return -ENOMEM; 1163dc35a10fSMarcin Wojtas } 1164dc35a10fSMarcin Wojtas 1165dc35a10fSMarcin Wojtas if (short_pool_id != long_pool_id) { 1166dc35a10fSMarcin Wojtas pp->pool_short->port_map |= 1 << pp->id; 1167dc35a10fSMarcin Wojtas mvneta_bm_pool_bufsize_set(pp, pp->pool_short->buf_size, 1168dc35a10fSMarcin Wojtas pp->pool_short->id); 1169dc35a10fSMarcin Wojtas } 1170dc35a10fSMarcin Wojtas 1171dc35a10fSMarcin Wojtas return 0; 1172dc35a10fSMarcin Wojtas } 1173dc35a10fSMarcin Wojtas 1174dc35a10fSMarcin Wojtas /* Update settings of a pool for bigger packets */ 1175dc35a10fSMarcin Wojtas static void mvneta_bm_update_mtu(struct mvneta_port *pp, int mtu) 1176dc35a10fSMarcin Wojtas { 1177dc35a10fSMarcin Wojtas struct mvneta_bm_pool *bm_pool = pp->pool_long; 1178baa11ebcSGregory CLEMENT struct hwbm_pool *hwbm_pool = &bm_pool->hwbm_pool; 1179dc35a10fSMarcin Wojtas int num; 1180dc35a10fSMarcin Wojtas 1181dc35a10fSMarcin Wojtas /* Release all buffers from long pool */ 1182dc35a10fSMarcin Wojtas mvneta_bm_bufs_free(pp->bm_priv, bm_pool, 1 << pp->id); 1183baa11ebcSGregory CLEMENT if (hwbm_pool->buf_num) { 1184dc35a10fSMarcin Wojtas WARN(1, "cannot free all buffers in pool %d\n", 1185dc35a10fSMarcin Wojtas bm_pool->id); 1186dc35a10fSMarcin Wojtas goto bm_mtu_err; 1187dc35a10fSMarcin Wojtas } 1188dc35a10fSMarcin Wojtas 1189dc35a10fSMarcin Wojtas bm_pool->pkt_size = MVNETA_RX_PKT_SIZE(mtu); 1190dc35a10fSMarcin Wojtas bm_pool->buf_size = MVNETA_RX_BUF_SIZE(bm_pool->pkt_size); 1191baa11ebcSGregory CLEMENT hwbm_pool->frag_size = SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) + 1192dc35a10fSMarcin Wojtas SKB_DATA_ALIGN(MVNETA_RX_BUF_SIZE(bm_pool->pkt_size)); 1193dc35a10fSMarcin Wojtas 1194dc35a10fSMarcin Wojtas /* Fill entire long pool */ 11956dcdd884SSebastian Andrzej Siewior num = hwbm_pool_add(hwbm_pool, hwbm_pool->size); 1196baa11ebcSGregory CLEMENT if (num != hwbm_pool->size) { 1197dc35a10fSMarcin Wojtas WARN(1, "pool %d: %d of %d allocated\n", 1198baa11ebcSGregory CLEMENT bm_pool->id, num, hwbm_pool->size); 1199dc35a10fSMarcin Wojtas goto bm_mtu_err; 1200dc35a10fSMarcin Wojtas } 1201dc35a10fSMarcin Wojtas mvneta_bm_pool_bufsize_set(pp, bm_pool->buf_size, bm_pool->id); 1202dc35a10fSMarcin Wojtas 1203dc35a10fSMarcin Wojtas return; 1204dc35a10fSMarcin Wojtas 1205dc35a10fSMarcin Wojtas bm_mtu_err: 1206dc35a10fSMarcin Wojtas mvneta_bm_pool_destroy(pp->bm_priv, pp->pool_long, 1 << pp->id); 1207dc35a10fSMarcin Wojtas mvneta_bm_pool_destroy(pp->bm_priv, pp->pool_short, 1 << pp->id); 1208dc35a10fSMarcin Wojtas 1209dc35a10fSMarcin Wojtas pp->bm_priv = NULL; 121044efc78dSLorenzo Bianconi pp->rx_offset_correction = MVNETA_SKB_HEADROOM; 1211dc35a10fSMarcin Wojtas mvreg_write(pp, MVNETA_ACC_MODE, MVNETA_ACC_MODE_EXT1); 1212dc35a10fSMarcin Wojtas netdev_info(pp->dev, "fail to update MTU, fall back to software BM\n"); 1213dc35a10fSMarcin Wojtas } 1214dc35a10fSMarcin Wojtas 1215c5aff182SThomas Petazzoni /* Start the Ethernet port RX and TX activity */ 1216c5aff182SThomas Petazzoni static void mvneta_port_up(struct mvneta_port *pp) 1217c5aff182SThomas Petazzoni { 1218c5aff182SThomas Petazzoni int queue; 1219c5aff182SThomas Petazzoni u32 q_map; 1220c5aff182SThomas Petazzoni 1221c5aff182SThomas Petazzoni /* Enable all initialized TXs. */ 1222c5aff182SThomas Petazzoni q_map = 0; 1223c5aff182SThomas Petazzoni for (queue = 0; queue < txq_number; queue++) { 1224c5aff182SThomas Petazzoni struct mvneta_tx_queue *txq = &pp->txqs[queue]; 1225f95936ccSMarkus Elfring if (txq->descs) 1226c5aff182SThomas Petazzoni q_map |= (1 << queue); 1227c5aff182SThomas Petazzoni } 1228c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_TXQ_CMD, q_map); 1229c5aff182SThomas Petazzoni 1230e81b5e01SYelena Krivosheev q_map = 0; 1231c5aff182SThomas Petazzoni /* Enable all initialized RXQs. */ 12322dcf75e2SGregory CLEMENT for (queue = 0; queue < rxq_number; queue++) { 12332dcf75e2SGregory CLEMENT struct mvneta_rx_queue *rxq = &pp->rxqs[queue]; 12342dcf75e2SGregory CLEMENT 1235f95936ccSMarkus Elfring if (rxq->descs) 12362dcf75e2SGregory CLEMENT q_map |= (1 << queue); 12372dcf75e2SGregory CLEMENT } 12382dcf75e2SGregory CLEMENT mvreg_write(pp, MVNETA_RXQ_CMD, q_map); 1239c5aff182SThomas Petazzoni } 1240c5aff182SThomas Petazzoni 1241c5aff182SThomas Petazzoni /* Stop the Ethernet port activity */ 1242c5aff182SThomas Petazzoni static void mvneta_port_down(struct mvneta_port *pp) 1243c5aff182SThomas Petazzoni { 1244c5aff182SThomas Petazzoni u32 val; 1245c5aff182SThomas Petazzoni int count; 1246c5aff182SThomas Petazzoni 1247c5aff182SThomas Petazzoni /* Stop Rx port activity. Check port Rx activity. */ 1248c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_RXQ_CMD) & MVNETA_RXQ_ENABLE_MASK; 1249c5aff182SThomas Petazzoni 1250c5aff182SThomas Petazzoni /* Issue stop command for active channels only */ 1251c5aff182SThomas Petazzoni if (val != 0) 1252c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_RXQ_CMD, 1253c5aff182SThomas Petazzoni val << MVNETA_RXQ_DISABLE_SHIFT); 1254c5aff182SThomas Petazzoni 1255c5aff182SThomas Petazzoni /* Wait for all Rx activity to terminate. */ 1256c5aff182SThomas Petazzoni count = 0; 1257c5aff182SThomas Petazzoni do { 1258c5aff182SThomas Petazzoni if (count++ >= MVNETA_RX_DISABLE_TIMEOUT_MSEC) { 1259c5aff182SThomas Petazzoni netdev_warn(pp->dev, 12600838abb3SDmitri Epshtein "TIMEOUT for RX stopped ! rx_queue_cmd: 0x%08x\n", 1261c5aff182SThomas Petazzoni val); 1262c5aff182SThomas Petazzoni break; 1263c5aff182SThomas Petazzoni } 1264c5aff182SThomas Petazzoni mdelay(1); 1265c5aff182SThomas Petazzoni 1266c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_RXQ_CMD); 1267a3703fb3SDmitri Epshtein } while (val & MVNETA_RXQ_ENABLE_MASK); 1268c5aff182SThomas Petazzoni 1269c5aff182SThomas Petazzoni /* Stop Tx port activity. Check port Tx activity. Issue stop 12706a20c175SThomas Petazzoni * command for active channels only 12716a20c175SThomas Petazzoni */ 1272c5aff182SThomas Petazzoni val = (mvreg_read(pp, MVNETA_TXQ_CMD)) & MVNETA_TXQ_ENABLE_MASK; 1273c5aff182SThomas Petazzoni 1274c5aff182SThomas Petazzoni if (val != 0) 1275c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_TXQ_CMD, 1276c5aff182SThomas Petazzoni (val << MVNETA_TXQ_DISABLE_SHIFT)); 1277c5aff182SThomas Petazzoni 1278c5aff182SThomas Petazzoni /* Wait for all Tx activity to terminate. */ 1279c5aff182SThomas Petazzoni count = 0; 1280c5aff182SThomas Petazzoni do { 1281c5aff182SThomas Petazzoni if (count++ >= MVNETA_TX_DISABLE_TIMEOUT_MSEC) { 1282c5aff182SThomas Petazzoni netdev_warn(pp->dev, 1283c5aff182SThomas Petazzoni "TIMEOUT for TX stopped status=0x%08x\n", 1284c5aff182SThomas Petazzoni val); 1285c5aff182SThomas Petazzoni break; 1286c5aff182SThomas Petazzoni } 1287c5aff182SThomas Petazzoni mdelay(1); 1288c5aff182SThomas Petazzoni 1289c5aff182SThomas Petazzoni /* Check TX Command reg that all Txqs are stopped */ 1290c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_TXQ_CMD); 1291c5aff182SThomas Petazzoni 1292a3703fb3SDmitri Epshtein } while (val & MVNETA_TXQ_ENABLE_MASK); 1293c5aff182SThomas Petazzoni 1294c5aff182SThomas Petazzoni /* Double check to verify that TX FIFO is empty */ 1295c5aff182SThomas Petazzoni count = 0; 1296c5aff182SThomas Petazzoni do { 1297c5aff182SThomas Petazzoni if (count++ >= MVNETA_TX_FIFO_EMPTY_TIMEOUT) { 1298c5aff182SThomas Petazzoni netdev_warn(pp->dev, 12990838abb3SDmitri Epshtein "TX FIFO empty timeout status=0x%08x\n", 1300c5aff182SThomas Petazzoni val); 1301c5aff182SThomas Petazzoni break; 1302c5aff182SThomas Petazzoni } 1303c5aff182SThomas Petazzoni mdelay(1); 1304c5aff182SThomas Petazzoni 1305c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_PORT_STATUS); 1306c5aff182SThomas Petazzoni } while (!(val & MVNETA_TX_FIFO_EMPTY) && 1307c5aff182SThomas Petazzoni (val & MVNETA_TX_IN_PRGRS)); 1308c5aff182SThomas Petazzoni 1309c5aff182SThomas Petazzoni udelay(200); 1310c5aff182SThomas Petazzoni } 1311c5aff182SThomas Petazzoni 1312c5aff182SThomas Petazzoni /* Enable the port by setting the port enable bit of the MAC control register */ 1313c5aff182SThomas Petazzoni static void mvneta_port_enable(struct mvneta_port *pp) 1314c5aff182SThomas Petazzoni { 1315c5aff182SThomas Petazzoni u32 val; 1316c5aff182SThomas Petazzoni 1317c5aff182SThomas Petazzoni /* Enable port */ 1318c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_GMAC_CTRL_0); 1319c5aff182SThomas Petazzoni val |= MVNETA_GMAC0_PORT_ENABLE; 1320c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_GMAC_CTRL_0, val); 1321c5aff182SThomas Petazzoni } 1322c5aff182SThomas Petazzoni 1323c5aff182SThomas Petazzoni /* Disable the port and wait for about 200 usec before retuning */ 1324c5aff182SThomas Petazzoni static void mvneta_port_disable(struct mvneta_port *pp) 1325c5aff182SThomas Petazzoni { 1326c5aff182SThomas Petazzoni u32 val; 1327c5aff182SThomas Petazzoni 1328c5aff182SThomas Petazzoni /* Reset the Enable bit in the Serial Control Register */ 1329c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_GMAC_CTRL_0); 1330c5aff182SThomas Petazzoni val &= ~MVNETA_GMAC0_PORT_ENABLE; 1331c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_GMAC_CTRL_0, val); 1332c5aff182SThomas Petazzoni 1333c5aff182SThomas Petazzoni udelay(200); 1334c5aff182SThomas Petazzoni } 1335c5aff182SThomas Petazzoni 1336c5aff182SThomas Petazzoni /* Multicast tables methods */ 1337c5aff182SThomas Petazzoni 1338c5aff182SThomas Petazzoni /* Set all entries in Unicast MAC Table; queue==-1 means reject all */ 1339c5aff182SThomas Petazzoni static void mvneta_set_ucast_table(struct mvneta_port *pp, int queue) 1340c5aff182SThomas Petazzoni { 1341c5aff182SThomas Petazzoni int offset; 1342c5aff182SThomas Petazzoni u32 val; 1343c5aff182SThomas Petazzoni 1344c5aff182SThomas Petazzoni if (queue == -1) { 1345c5aff182SThomas Petazzoni val = 0; 1346c5aff182SThomas Petazzoni } else { 1347c5aff182SThomas Petazzoni val = 0x1 | (queue << 1); 1348c5aff182SThomas Petazzoni val |= (val << 24) | (val << 16) | (val << 8); 1349c5aff182SThomas Petazzoni } 1350c5aff182SThomas Petazzoni 1351c5aff182SThomas Petazzoni for (offset = 0; offset <= 0xc; offset += 4) 1352c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_DA_FILT_UCAST_BASE + offset, val); 1353c5aff182SThomas Petazzoni } 1354c5aff182SThomas Petazzoni 1355c5aff182SThomas Petazzoni /* Set all entries in Special Multicast MAC Table; queue==-1 means reject all */ 1356c5aff182SThomas Petazzoni static void mvneta_set_special_mcast_table(struct mvneta_port *pp, int queue) 1357c5aff182SThomas Petazzoni { 1358c5aff182SThomas Petazzoni int offset; 1359c5aff182SThomas Petazzoni u32 val; 1360c5aff182SThomas Petazzoni 1361c5aff182SThomas Petazzoni if (queue == -1) { 1362c5aff182SThomas Petazzoni val = 0; 1363c5aff182SThomas Petazzoni } else { 1364c5aff182SThomas Petazzoni val = 0x1 | (queue << 1); 1365c5aff182SThomas Petazzoni val |= (val << 24) | (val << 16) | (val << 8); 1366c5aff182SThomas Petazzoni } 1367c5aff182SThomas Petazzoni 1368c5aff182SThomas Petazzoni for (offset = 0; offset <= 0xfc; offset += 4) 1369c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_DA_FILT_SPEC_MCAST + offset, val); 1370c5aff182SThomas Petazzoni 1371c5aff182SThomas Petazzoni } 1372c5aff182SThomas Petazzoni 1373c5aff182SThomas Petazzoni /* Set all entries in Other Multicast MAC Table. queue==-1 means reject all */ 1374c5aff182SThomas Petazzoni static void mvneta_set_other_mcast_table(struct mvneta_port *pp, int queue) 1375c5aff182SThomas Petazzoni { 1376c5aff182SThomas Petazzoni int offset; 1377c5aff182SThomas Petazzoni u32 val; 1378c5aff182SThomas Petazzoni 1379c5aff182SThomas Petazzoni if (queue == -1) { 1380c5aff182SThomas Petazzoni memset(pp->mcast_count, 0, sizeof(pp->mcast_count)); 1381c5aff182SThomas Petazzoni val = 0; 1382c5aff182SThomas Petazzoni } else { 1383c5aff182SThomas Petazzoni memset(pp->mcast_count, 1, sizeof(pp->mcast_count)); 1384c5aff182SThomas Petazzoni val = 0x1 | (queue << 1); 1385c5aff182SThomas Petazzoni val |= (val << 24) | (val << 16) | (val << 8); 1386c5aff182SThomas Petazzoni } 1387c5aff182SThomas Petazzoni 1388c5aff182SThomas Petazzoni for (offset = 0; offset <= 0xfc; offset += 4) 1389c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_DA_FILT_OTH_MCAST + offset, val); 1390c5aff182SThomas Petazzoni } 1391c5aff182SThomas Petazzoni 1392db488c10SGregory CLEMENT static void mvneta_percpu_unmask_interrupt(void *arg) 1393db488c10SGregory CLEMENT { 1394db488c10SGregory CLEMENT struct mvneta_port *pp = arg; 1395db488c10SGregory CLEMENT 1396db488c10SGregory CLEMENT /* All the queue are unmasked, but actually only the ones 1397db488c10SGregory CLEMENT * mapped to this CPU will be unmasked 1398db488c10SGregory CLEMENT */ 1399db488c10SGregory CLEMENT mvreg_write(pp, MVNETA_INTR_NEW_MASK, 1400db488c10SGregory CLEMENT MVNETA_RX_INTR_MASK_ALL | 1401db488c10SGregory CLEMENT MVNETA_TX_INTR_MASK_ALL | 1402db488c10SGregory CLEMENT MVNETA_MISCINTR_INTR_MASK); 1403db488c10SGregory CLEMENT } 1404db488c10SGregory CLEMENT 1405db488c10SGregory CLEMENT static void mvneta_percpu_mask_interrupt(void *arg) 1406db488c10SGregory CLEMENT { 1407db488c10SGregory CLEMENT struct mvneta_port *pp = arg; 1408db488c10SGregory CLEMENT 1409db488c10SGregory CLEMENT /* All the queue are masked, but actually only the ones 1410db488c10SGregory CLEMENT * mapped to this CPU will be masked 1411db488c10SGregory CLEMENT */ 1412db488c10SGregory CLEMENT mvreg_write(pp, MVNETA_INTR_NEW_MASK, 0); 1413db488c10SGregory CLEMENT mvreg_write(pp, MVNETA_INTR_OLD_MASK, 0); 1414db488c10SGregory CLEMENT mvreg_write(pp, MVNETA_INTR_MISC_MASK, 0); 1415db488c10SGregory CLEMENT } 1416db488c10SGregory CLEMENT 1417db488c10SGregory CLEMENT static void mvneta_percpu_clear_intr_cause(void *arg) 1418db488c10SGregory CLEMENT { 1419db488c10SGregory CLEMENT struct mvneta_port *pp = arg; 1420db488c10SGregory CLEMENT 1421db488c10SGregory CLEMENT /* All the queue are cleared, but actually only the ones 1422db488c10SGregory CLEMENT * mapped to this CPU will be cleared 1423db488c10SGregory CLEMENT */ 1424db488c10SGregory CLEMENT mvreg_write(pp, MVNETA_INTR_NEW_CAUSE, 0); 1425db488c10SGregory CLEMENT mvreg_write(pp, MVNETA_INTR_MISC_CAUSE, 0); 1426db488c10SGregory CLEMENT mvreg_write(pp, MVNETA_INTR_OLD_CAUSE, 0); 1427db488c10SGregory CLEMENT } 1428db488c10SGregory CLEMENT 1429c5aff182SThomas Petazzoni /* This method sets defaults to the NETA port: 1430c5aff182SThomas Petazzoni * Clears interrupt Cause and Mask registers. 1431c5aff182SThomas Petazzoni * Clears all MAC tables. 1432c5aff182SThomas Petazzoni * Sets defaults to all registers. 1433c5aff182SThomas Petazzoni * Resets RX and TX descriptor rings. 1434c5aff182SThomas Petazzoni * Resets PHY. 1435c5aff182SThomas Petazzoni * This method can be called after mvneta_port_down() to return the port 1436c5aff182SThomas Petazzoni * settings to defaults. 1437c5aff182SThomas Petazzoni */ 1438c5aff182SThomas Petazzoni static void mvneta_defaults_set(struct mvneta_port *pp) 1439c5aff182SThomas Petazzoni { 1440c5aff182SThomas Petazzoni int cpu; 1441c5aff182SThomas Petazzoni int queue; 1442c5aff182SThomas Petazzoni u32 val; 14432dcf75e2SGregory CLEMENT int max_cpu = num_present_cpus(); 1444c5aff182SThomas Petazzoni 1445c5aff182SThomas Petazzoni /* Clear all Cause registers */ 1446db488c10SGregory CLEMENT on_each_cpu(mvneta_percpu_clear_intr_cause, pp, true); 1447c5aff182SThomas Petazzoni 1448c5aff182SThomas Petazzoni /* Mask all interrupts */ 1449db488c10SGregory CLEMENT on_each_cpu(mvneta_percpu_mask_interrupt, pp, true); 1450c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_INTR_ENABLE, 0); 1451c5aff182SThomas Petazzoni 1452c5aff182SThomas Petazzoni /* Enable MBUS Retry bit16 */ 1453c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_MBUS_RETRY, 0x20); 1454c5aff182SThomas Petazzoni 145550bf8cb6SGregory CLEMENT /* Set CPU queue access map. CPUs are assigned to the RX and 145650bf8cb6SGregory CLEMENT * TX queues modulo their number. If there is only one TX 145750bf8cb6SGregory CLEMENT * queue then it is assigned to the CPU associated to the 145850bf8cb6SGregory CLEMENT * default RX queue. 14596a20c175SThomas Petazzoni */ 14602dcf75e2SGregory CLEMENT for_each_present_cpu(cpu) { 14612dcf75e2SGregory CLEMENT int rxq_map = 0, txq_map = 0; 146250bf8cb6SGregory CLEMENT int rxq, txq; 14632636ac3cSMarcin Wojtas if (!pp->neta_armada3700) { 14642dcf75e2SGregory CLEMENT for (rxq = 0; rxq < rxq_number; rxq++) 14652dcf75e2SGregory CLEMENT if ((rxq % max_cpu) == cpu) 14662dcf75e2SGregory CLEMENT rxq_map |= MVNETA_CPU_RXQ_ACCESS(rxq); 14672dcf75e2SGregory CLEMENT 146850bf8cb6SGregory CLEMENT for (txq = 0; txq < txq_number; txq++) 146950bf8cb6SGregory CLEMENT if ((txq % max_cpu) == cpu) 147050bf8cb6SGregory CLEMENT txq_map |= MVNETA_CPU_TXQ_ACCESS(txq); 147150bf8cb6SGregory CLEMENT 147250bf8cb6SGregory CLEMENT /* With only one TX queue we configure a special case 147350bf8cb6SGregory CLEMENT * which will allow to get all the irq on a single 147450bf8cb6SGregory CLEMENT * CPU 147550bf8cb6SGregory CLEMENT */ 147650bf8cb6SGregory CLEMENT if (txq_number == 1) 147750bf8cb6SGregory CLEMENT txq_map = (cpu == pp->rxq_def) ? 147850bf8cb6SGregory CLEMENT MVNETA_CPU_TXQ_ACCESS(1) : 0; 14792dcf75e2SGregory CLEMENT 14802636ac3cSMarcin Wojtas } else { 14812636ac3cSMarcin Wojtas txq_map = MVNETA_CPU_TXQ_ACCESS_ALL_MASK; 14822636ac3cSMarcin Wojtas rxq_map = MVNETA_CPU_RXQ_ACCESS_ALL_MASK; 14832636ac3cSMarcin Wojtas } 14842636ac3cSMarcin Wojtas 14852dcf75e2SGregory CLEMENT mvreg_write(pp, MVNETA_CPU_MAP(cpu), rxq_map | txq_map); 14862dcf75e2SGregory CLEMENT } 1487c5aff182SThomas Petazzoni 1488c5aff182SThomas Petazzoni /* Reset RX and TX DMAs */ 1489c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_PORT_RX_RESET, MVNETA_PORT_RX_DMA_RESET); 1490c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_PORT_TX_RESET, MVNETA_PORT_TX_DMA_RESET); 1491c5aff182SThomas Petazzoni 1492c5aff182SThomas Petazzoni /* Disable Legacy WRR, Disable EJP, Release from reset */ 1493c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_TXQ_CMD_1, 0); 1494c5aff182SThomas Petazzoni for (queue = 0; queue < txq_number; queue++) { 1495c5aff182SThomas Petazzoni mvreg_write(pp, MVETH_TXQ_TOKEN_COUNT_REG(queue), 0); 1496c5aff182SThomas Petazzoni mvreg_write(pp, MVETH_TXQ_TOKEN_CFG_REG(queue), 0); 1497c5aff182SThomas Petazzoni } 1498c5aff182SThomas Petazzoni 1499c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_PORT_TX_RESET, 0); 1500c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_PORT_RX_RESET, 0); 1501c5aff182SThomas Petazzoni 1502c5aff182SThomas Petazzoni /* Set Port Acceleration Mode */ 1503dc35a10fSMarcin Wojtas if (pp->bm_priv) 1504dc35a10fSMarcin Wojtas /* HW buffer management + legacy parser */ 1505dc35a10fSMarcin Wojtas val = MVNETA_ACC_MODE_EXT2; 1506dc35a10fSMarcin Wojtas else 1507dc35a10fSMarcin Wojtas /* SW buffer management + legacy parser */ 1508dc35a10fSMarcin Wojtas val = MVNETA_ACC_MODE_EXT1; 1509c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_ACC_MODE, val); 1510c5aff182SThomas Petazzoni 1511dc35a10fSMarcin Wojtas if (pp->bm_priv) 1512dc35a10fSMarcin Wojtas mvreg_write(pp, MVNETA_BM_ADDRESS, pp->bm_priv->bppi_phys_addr); 1513dc35a10fSMarcin Wojtas 1514c5aff182SThomas Petazzoni /* Update val of portCfg register accordingly with all RxQueue types */ 151590b74c01SGregory CLEMENT val = MVNETA_PORT_CONFIG_DEFL_VALUE(pp->rxq_def); 1516c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_PORT_CONFIG, val); 1517c5aff182SThomas Petazzoni 1518c5aff182SThomas Petazzoni val = 0; 1519c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_PORT_CONFIG_EXTEND, val); 1520c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_RX_MIN_FRAME_SIZE, 64); 1521c5aff182SThomas Petazzoni 1522c5aff182SThomas Petazzoni /* Build PORT_SDMA_CONFIG_REG */ 1523c5aff182SThomas Petazzoni val = 0; 1524c5aff182SThomas Petazzoni 1525c5aff182SThomas Petazzoni /* Default burst size */ 1526c5aff182SThomas Petazzoni val |= MVNETA_TX_BRST_SZ_MASK(MVNETA_SDMA_BRST_SIZE_16); 1527c5aff182SThomas Petazzoni val |= MVNETA_RX_BRST_SZ_MASK(MVNETA_SDMA_BRST_SIZE_16); 15289ad8fef6SThomas Petazzoni val |= MVNETA_RX_NO_DATA_SWAP | MVNETA_TX_NO_DATA_SWAP; 1529c5aff182SThomas Petazzoni 15309ad8fef6SThomas Petazzoni #if defined(__BIG_ENDIAN) 15319ad8fef6SThomas Petazzoni val |= MVNETA_DESC_SWAP; 15329ad8fef6SThomas Petazzoni #endif 1533c5aff182SThomas Petazzoni 1534c5aff182SThomas Petazzoni /* Assign port SDMA configuration */ 1535c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_SDMA_CONFIG, val); 1536c5aff182SThomas Petazzoni 153771408602SThomas Petazzoni /* Disable PHY polling in hardware, since we're using the 153871408602SThomas Petazzoni * kernel phylib to do this. 153971408602SThomas Petazzoni */ 154071408602SThomas Petazzoni val = mvreg_read(pp, MVNETA_UNIT_CONTROL); 154171408602SThomas Petazzoni val &= ~MVNETA_PHY_POLLING_ENABLE; 154271408602SThomas Petazzoni mvreg_write(pp, MVNETA_UNIT_CONTROL, val); 154371408602SThomas Petazzoni 1544c5aff182SThomas Petazzoni mvneta_set_ucast_table(pp, -1); 1545c5aff182SThomas Petazzoni mvneta_set_special_mcast_table(pp, -1); 1546c5aff182SThomas Petazzoni mvneta_set_other_mcast_table(pp, -1); 1547c5aff182SThomas Petazzoni 1548c5aff182SThomas Petazzoni /* Set port interrupt enable register - default enable all */ 1549c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_INTR_ENABLE, 1550c5aff182SThomas Petazzoni (MVNETA_RXQ_INTR_ENABLE_ALL_MASK 1551c5aff182SThomas Petazzoni | MVNETA_TXQ_INTR_ENABLE_ALL_MASK)); 1552e483911fSAndrew Lunn 1553e483911fSAndrew Lunn mvneta_mib_counters_clear(pp); 1554c5aff182SThomas Petazzoni } 1555c5aff182SThomas Petazzoni 1556c5aff182SThomas Petazzoni /* Set max sizes for tx queues */ 1557c5aff182SThomas Petazzoni static void mvneta_txq_max_tx_size_set(struct mvneta_port *pp, int max_tx_size) 1558c5aff182SThomas Petazzoni 1559c5aff182SThomas Petazzoni { 1560c5aff182SThomas Petazzoni u32 val, size, mtu; 1561c5aff182SThomas Petazzoni int queue; 1562c5aff182SThomas Petazzoni 1563c5aff182SThomas Petazzoni mtu = max_tx_size * 8; 1564c5aff182SThomas Petazzoni if (mtu > MVNETA_TX_MTU_MAX) 1565c5aff182SThomas Petazzoni mtu = MVNETA_TX_MTU_MAX; 1566c5aff182SThomas Petazzoni 1567c5aff182SThomas Petazzoni /* Set MTU */ 1568c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_TX_MTU); 1569c5aff182SThomas Petazzoni val &= ~MVNETA_TX_MTU_MAX; 1570c5aff182SThomas Petazzoni val |= mtu; 1571c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_TX_MTU, val); 1572c5aff182SThomas Petazzoni 1573c5aff182SThomas Petazzoni /* TX token size and all TXQs token size must be larger that MTU */ 1574c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_TX_TOKEN_SIZE); 1575c5aff182SThomas Petazzoni 1576c5aff182SThomas Petazzoni size = val & MVNETA_TX_TOKEN_SIZE_MAX; 1577c5aff182SThomas Petazzoni if (size < mtu) { 1578c5aff182SThomas Petazzoni size = mtu; 1579c5aff182SThomas Petazzoni val &= ~MVNETA_TX_TOKEN_SIZE_MAX; 1580c5aff182SThomas Petazzoni val |= size; 1581c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_TX_TOKEN_SIZE, val); 1582c5aff182SThomas Petazzoni } 1583c5aff182SThomas Petazzoni for (queue = 0; queue < txq_number; queue++) { 1584c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_TXQ_TOKEN_SIZE_REG(queue)); 1585c5aff182SThomas Petazzoni 1586c5aff182SThomas Petazzoni size = val & MVNETA_TXQ_TOKEN_SIZE_MAX; 1587c5aff182SThomas Petazzoni if (size < mtu) { 1588c5aff182SThomas Petazzoni size = mtu; 1589c5aff182SThomas Petazzoni val &= ~MVNETA_TXQ_TOKEN_SIZE_MAX; 1590c5aff182SThomas Petazzoni val |= size; 1591c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_TXQ_TOKEN_SIZE_REG(queue), val); 1592c5aff182SThomas Petazzoni } 1593c5aff182SThomas Petazzoni } 1594c5aff182SThomas Petazzoni } 1595c5aff182SThomas Petazzoni 1596c5aff182SThomas Petazzoni /* Set unicast address */ 1597c5aff182SThomas Petazzoni static void mvneta_set_ucast_addr(struct mvneta_port *pp, u8 last_nibble, 1598c5aff182SThomas Petazzoni int queue) 1599c5aff182SThomas Petazzoni { 1600c5aff182SThomas Petazzoni unsigned int unicast_reg; 1601c5aff182SThomas Petazzoni unsigned int tbl_offset; 1602c5aff182SThomas Petazzoni unsigned int reg_offset; 1603c5aff182SThomas Petazzoni 1604c5aff182SThomas Petazzoni /* Locate the Unicast table entry */ 1605c5aff182SThomas Petazzoni last_nibble = (0xf & last_nibble); 1606c5aff182SThomas Petazzoni 1607c5aff182SThomas Petazzoni /* offset from unicast tbl base */ 1608c5aff182SThomas Petazzoni tbl_offset = (last_nibble / 4) * 4; 1609c5aff182SThomas Petazzoni 1610c5aff182SThomas Petazzoni /* offset within the above reg */ 1611c5aff182SThomas Petazzoni reg_offset = last_nibble % 4; 1612c5aff182SThomas Petazzoni 1613c5aff182SThomas Petazzoni unicast_reg = mvreg_read(pp, (MVNETA_DA_FILT_UCAST_BASE + tbl_offset)); 1614c5aff182SThomas Petazzoni 1615c5aff182SThomas Petazzoni if (queue == -1) { 1616c5aff182SThomas Petazzoni /* Clear accepts frame bit at specified unicast DA tbl entry */ 1617c5aff182SThomas Petazzoni unicast_reg &= ~(0xff << (8 * reg_offset)); 1618c5aff182SThomas Petazzoni } else { 1619c5aff182SThomas Petazzoni unicast_reg &= ~(0xff << (8 * reg_offset)); 1620c5aff182SThomas Petazzoni unicast_reg |= ((0x01 | (queue << 1)) << (8 * reg_offset)); 1621c5aff182SThomas Petazzoni } 1622c5aff182SThomas Petazzoni 1623c5aff182SThomas Petazzoni mvreg_write(pp, (MVNETA_DA_FILT_UCAST_BASE + tbl_offset), unicast_reg); 1624c5aff182SThomas Petazzoni } 1625c5aff182SThomas Petazzoni 1626c5aff182SThomas Petazzoni /* Set mac address */ 162776660757SJakub Kicinski static void mvneta_mac_addr_set(struct mvneta_port *pp, 162876660757SJakub Kicinski const unsigned char *addr, int queue) 1629c5aff182SThomas Petazzoni { 1630c5aff182SThomas Petazzoni unsigned int mac_h; 1631c5aff182SThomas Petazzoni unsigned int mac_l; 1632c5aff182SThomas Petazzoni 1633c5aff182SThomas Petazzoni if (queue != -1) { 1634c5aff182SThomas Petazzoni mac_l = (addr[4] << 8) | (addr[5]); 1635c5aff182SThomas Petazzoni mac_h = (addr[0] << 24) | (addr[1] << 16) | 1636c5aff182SThomas Petazzoni (addr[2] << 8) | (addr[3] << 0); 1637c5aff182SThomas Petazzoni 1638c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_MAC_ADDR_LOW, mac_l); 1639c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_MAC_ADDR_HIGH, mac_h); 1640c5aff182SThomas Petazzoni } 1641c5aff182SThomas Petazzoni 1642c5aff182SThomas Petazzoni /* Accept frames of this address */ 1643c5aff182SThomas Petazzoni mvneta_set_ucast_addr(pp, addr[5], queue); 1644c5aff182SThomas Petazzoni } 1645c5aff182SThomas Petazzoni 16466a20c175SThomas Petazzoni /* Set the number of packets that will be received before RX interrupt 16476a20c175SThomas Petazzoni * will be generated by HW. 1648c5aff182SThomas Petazzoni */ 1649c5aff182SThomas Petazzoni static void mvneta_rx_pkts_coal_set(struct mvneta_port *pp, 1650c5aff182SThomas Petazzoni struct mvneta_rx_queue *rxq, u32 value) 1651c5aff182SThomas Petazzoni { 1652c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_RXQ_THRESHOLD_REG(rxq->id), 1653c5aff182SThomas Petazzoni value | MVNETA_RXQ_NON_OCCUPIED(0)); 1654c5aff182SThomas Petazzoni } 1655c5aff182SThomas Petazzoni 16566a20c175SThomas Petazzoni /* Set the time delay in usec before RX interrupt will be generated by 16576a20c175SThomas Petazzoni * HW. 1658c5aff182SThomas Petazzoni */ 1659c5aff182SThomas Petazzoni static void mvneta_rx_time_coal_set(struct mvneta_port *pp, 1660c5aff182SThomas Petazzoni struct mvneta_rx_queue *rxq, u32 value) 1661c5aff182SThomas Petazzoni { 1662189dd626SThomas Petazzoni u32 val; 1663189dd626SThomas Petazzoni unsigned long clk_rate; 1664189dd626SThomas Petazzoni 1665189dd626SThomas Petazzoni clk_rate = clk_get_rate(pp->clk); 1666189dd626SThomas Petazzoni val = (clk_rate / 1000000) * value; 1667c5aff182SThomas Petazzoni 1668c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_RXQ_TIME_COAL_REG(rxq->id), val); 1669c5aff182SThomas Petazzoni } 1670c5aff182SThomas Petazzoni 1671c5aff182SThomas Petazzoni /* Set threshold for TX_DONE pkts coalescing */ 1672c5aff182SThomas Petazzoni static void mvneta_tx_done_pkts_coal_set(struct mvneta_port *pp, 1673c5aff182SThomas Petazzoni struct mvneta_tx_queue *txq, u32 value) 1674c5aff182SThomas Petazzoni { 1675c5aff182SThomas Petazzoni u32 val; 1676c5aff182SThomas Petazzoni 1677c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_TXQ_SIZE_REG(txq->id)); 1678c5aff182SThomas Petazzoni 1679c5aff182SThomas Petazzoni val &= ~MVNETA_TXQ_SENT_THRESH_ALL_MASK; 1680c5aff182SThomas Petazzoni val |= MVNETA_TXQ_SENT_THRESH_MASK(value); 1681c5aff182SThomas Petazzoni 1682c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_TXQ_SIZE_REG(txq->id), val); 1683c5aff182SThomas Petazzoni } 1684c5aff182SThomas Petazzoni 1685c5aff182SThomas Petazzoni /* Handle rx descriptor fill by setting buf_cookie and buf_phys_addr */ 1686c5aff182SThomas Petazzoni static void mvneta_rx_desc_fill(struct mvneta_rx_desc *rx_desc, 1687f88bee1cSGregory CLEMENT u32 phys_addr, void *virt_addr, 1688f88bee1cSGregory CLEMENT struct mvneta_rx_queue *rxq) 1689c5aff182SThomas Petazzoni { 1690f88bee1cSGregory CLEMENT int i; 1691f88bee1cSGregory CLEMENT 1692c5aff182SThomas Petazzoni rx_desc->buf_phys_addr = phys_addr; 1693f88bee1cSGregory CLEMENT i = rx_desc - rxq->descs; 1694f88bee1cSGregory CLEMENT rxq->buf_virt_addr[i] = virt_addr; 1695c5aff182SThomas Petazzoni } 1696c5aff182SThomas Petazzoni 1697c5aff182SThomas Petazzoni /* Decrement sent descriptors counter */ 1698c5aff182SThomas Petazzoni static void mvneta_txq_sent_desc_dec(struct mvneta_port *pp, 1699c5aff182SThomas Petazzoni struct mvneta_tx_queue *txq, 1700c5aff182SThomas Petazzoni int sent_desc) 1701c5aff182SThomas Petazzoni { 1702c5aff182SThomas Petazzoni u32 val; 1703c5aff182SThomas Petazzoni 1704c5aff182SThomas Petazzoni /* Only 255 TX descriptors can be updated at once */ 1705c5aff182SThomas Petazzoni while (sent_desc > 0xff) { 1706c5aff182SThomas Petazzoni val = 0xff << MVNETA_TXQ_DEC_SENT_SHIFT; 1707c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val); 1708c5aff182SThomas Petazzoni sent_desc = sent_desc - 0xff; 1709c5aff182SThomas Petazzoni } 1710c5aff182SThomas Petazzoni 1711c5aff182SThomas Petazzoni val = sent_desc << MVNETA_TXQ_DEC_SENT_SHIFT; 1712c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val); 1713c5aff182SThomas Petazzoni } 1714c5aff182SThomas Petazzoni 1715c5aff182SThomas Petazzoni /* Get number of TX descriptors already sent by HW */ 1716c5aff182SThomas Petazzoni static int mvneta_txq_sent_desc_num_get(struct mvneta_port *pp, 1717c5aff182SThomas Petazzoni struct mvneta_tx_queue *txq) 1718c5aff182SThomas Petazzoni { 1719c5aff182SThomas Petazzoni u32 val; 1720c5aff182SThomas Petazzoni int sent_desc; 1721c5aff182SThomas Petazzoni 1722c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_TXQ_STATUS_REG(txq->id)); 1723c5aff182SThomas Petazzoni sent_desc = (val & MVNETA_TXQ_SENT_DESC_MASK) >> 1724c5aff182SThomas Petazzoni MVNETA_TXQ_SENT_DESC_SHIFT; 1725c5aff182SThomas Petazzoni 1726c5aff182SThomas Petazzoni return sent_desc; 1727c5aff182SThomas Petazzoni } 1728c5aff182SThomas Petazzoni 17296a20c175SThomas Petazzoni /* Get number of sent descriptors and decrement counter. 1730c5aff182SThomas Petazzoni * The number of sent descriptors is returned. 1731c5aff182SThomas Petazzoni */ 1732c5aff182SThomas Petazzoni static int mvneta_txq_sent_desc_proc(struct mvneta_port *pp, 1733c5aff182SThomas Petazzoni struct mvneta_tx_queue *txq) 1734c5aff182SThomas Petazzoni { 1735c5aff182SThomas Petazzoni int sent_desc; 1736c5aff182SThomas Petazzoni 1737c5aff182SThomas Petazzoni /* Get number of sent descriptors */ 1738c5aff182SThomas Petazzoni sent_desc = mvneta_txq_sent_desc_num_get(pp, txq); 1739c5aff182SThomas Petazzoni 1740c5aff182SThomas Petazzoni /* Decrement sent descriptors counter */ 1741c5aff182SThomas Petazzoni if (sent_desc) 1742c5aff182SThomas Petazzoni mvneta_txq_sent_desc_dec(pp, txq, sent_desc); 1743c5aff182SThomas Petazzoni 1744c5aff182SThomas Petazzoni return sent_desc; 1745c5aff182SThomas Petazzoni } 1746c5aff182SThomas Petazzoni 1747c5aff182SThomas Petazzoni /* Set TXQ descriptors fields relevant for CSUM calculation */ 1748c5aff182SThomas Petazzoni static u32 mvneta_txq_desc_csum(int l3_offs, int l3_proto, 1749c5aff182SThomas Petazzoni int ip_hdr_len, int l4_proto) 1750c5aff182SThomas Petazzoni { 1751c5aff182SThomas Petazzoni u32 command; 1752c5aff182SThomas Petazzoni 1753c5aff182SThomas Petazzoni /* Fields: L3_offset, IP_hdrlen, L3_type, G_IPv4_chk, 17546a20c175SThomas Petazzoni * G_L4_chk, L4_type; required only for checksum 17556a20c175SThomas Petazzoni * calculation 17566a20c175SThomas Petazzoni */ 1757c5aff182SThomas Petazzoni command = l3_offs << MVNETA_TX_L3_OFF_SHIFT; 1758c5aff182SThomas Petazzoni command |= ip_hdr_len << MVNETA_TX_IP_HLEN_SHIFT; 1759c5aff182SThomas Petazzoni 17600a198587SThomas Fitzsimmons if (l3_proto == htons(ETH_P_IP)) 1761c5aff182SThomas Petazzoni command |= MVNETA_TXD_IP_CSUM; 1762c5aff182SThomas Petazzoni else 1763c5aff182SThomas Petazzoni command |= MVNETA_TX_L3_IP6; 1764c5aff182SThomas Petazzoni 1765c5aff182SThomas Petazzoni if (l4_proto == IPPROTO_TCP) 1766c5aff182SThomas Petazzoni command |= MVNETA_TX_L4_CSUM_FULL; 1767c5aff182SThomas Petazzoni else if (l4_proto == IPPROTO_UDP) 1768c5aff182SThomas Petazzoni command |= MVNETA_TX_L4_UDP | MVNETA_TX_L4_CSUM_FULL; 1769c5aff182SThomas Petazzoni else 1770c5aff182SThomas Petazzoni command |= MVNETA_TX_L4_CSUM_NOT; 1771c5aff182SThomas Petazzoni 1772c5aff182SThomas Petazzoni return command; 1773c5aff182SThomas Petazzoni } 1774c5aff182SThomas Petazzoni 1775c5aff182SThomas Petazzoni 1776c5aff182SThomas Petazzoni /* Display more error info */ 1777c5aff182SThomas Petazzoni static void mvneta_rx_error(struct mvneta_port *pp, 1778c5aff182SThomas Petazzoni struct mvneta_rx_desc *rx_desc) 1779c5aff182SThomas Petazzoni { 1780c35947b8SLorenzo Bianconi struct mvneta_pcpu_stats *stats = this_cpu_ptr(pp->stats); 1781c5aff182SThomas Petazzoni u32 status = rx_desc->status; 1782c5aff182SThomas Petazzoni 1783c35947b8SLorenzo Bianconi /* update per-cpu counter */ 1784c35947b8SLorenzo Bianconi u64_stats_update_begin(&stats->syncp); 1785c35947b8SLorenzo Bianconi stats->rx_errors++; 1786c35947b8SLorenzo Bianconi u64_stats_update_end(&stats->syncp); 1787c35947b8SLorenzo Bianconi 1788c5aff182SThomas Petazzoni switch (status & MVNETA_RXD_ERR_CODE_MASK) { 1789c5aff182SThomas Petazzoni case MVNETA_RXD_ERR_CRC: 1790c5aff182SThomas Petazzoni netdev_err(pp->dev, "bad rx status %08x (crc error), size=%d\n", 1791c5aff182SThomas Petazzoni status, rx_desc->data_size); 1792c5aff182SThomas Petazzoni break; 1793c5aff182SThomas Petazzoni case MVNETA_RXD_ERR_OVERRUN: 1794c5aff182SThomas Petazzoni netdev_err(pp->dev, "bad rx status %08x (overrun error), size=%d\n", 1795c5aff182SThomas Petazzoni status, rx_desc->data_size); 1796c5aff182SThomas Petazzoni break; 1797c5aff182SThomas Petazzoni case MVNETA_RXD_ERR_LEN: 1798c5aff182SThomas Petazzoni netdev_err(pp->dev, "bad rx status %08x (max frame length error), size=%d\n", 1799c5aff182SThomas Petazzoni status, rx_desc->data_size); 1800c5aff182SThomas Petazzoni break; 1801c5aff182SThomas Petazzoni case MVNETA_RXD_ERR_RESOURCE: 1802c5aff182SThomas Petazzoni netdev_err(pp->dev, "bad rx status %08x (resource error), size=%d\n", 1803c5aff182SThomas Petazzoni status, rx_desc->data_size); 1804c5aff182SThomas Petazzoni break; 1805c5aff182SThomas Petazzoni } 1806c5aff182SThomas Petazzoni } 1807c5aff182SThomas Petazzoni 18085428213cSwilly tarreau /* Handle RX checksum offload based on the descriptor's status */ 1809aff0824dSLorenzo Bianconi static int mvneta_rx_csum(struct mvneta_port *pp, u32 status) 1810c5aff182SThomas Petazzoni { 1811f945cec8SYelena Krivosheev if ((pp->dev->features & NETIF_F_RXCSUM) && 1812f945cec8SYelena Krivosheev (status & MVNETA_RXD_L3_IP4) && 1813aff0824dSLorenzo Bianconi (status & MVNETA_RXD_L4_CSUM_OK)) 1814aff0824dSLorenzo Bianconi return CHECKSUM_UNNECESSARY; 1815c5aff182SThomas Petazzoni 1816aff0824dSLorenzo Bianconi return CHECKSUM_NONE; 1817c5aff182SThomas Petazzoni } 1818c5aff182SThomas Petazzoni 18196c498974Swilly tarreau /* Return tx queue pointer (find last set bit) according to <cause> returned 18206c498974Swilly tarreau * form tx_done reg. <cause> must not be null. The return value is always a 18216c498974Swilly tarreau * valid queue for matching the first one found in <cause>. 18226c498974Swilly tarreau */ 1823c5aff182SThomas Petazzoni static struct mvneta_tx_queue *mvneta_tx_done_policy(struct mvneta_port *pp, 1824c5aff182SThomas Petazzoni u32 cause) 1825c5aff182SThomas Petazzoni { 1826c5aff182SThomas Petazzoni int queue = fls(cause) - 1; 1827c5aff182SThomas Petazzoni 18286c498974Swilly tarreau return &pp->txqs[queue]; 1829c5aff182SThomas Petazzoni } 1830c5aff182SThomas Petazzoni 1831c5aff182SThomas Petazzoni /* Free tx queue skbuffs */ 1832c5aff182SThomas Petazzoni static void mvneta_txq_bufs_free(struct mvneta_port *pp, 1833a29b6235SMarcin Wojtas struct mvneta_tx_queue *txq, int num, 1834632bb64fSLorenzo Bianconi struct netdev_queue *nq, bool napi) 1835c5aff182SThomas Petazzoni { 1836a29b6235SMarcin Wojtas unsigned int bytes_compl = 0, pkts_compl = 0; 18372f9d0939SLorenzo Bianconi struct xdp_frame_bulk bq; 1838c5aff182SThomas Petazzoni int i; 1839c5aff182SThomas Petazzoni 18402f9d0939SLorenzo Bianconi xdp_frame_bulk_init(&bq); 18412f9d0939SLorenzo Bianconi 18422f9d0939SLorenzo Bianconi rcu_read_lock(); /* need for xdp_return_frame_bulk */ 18432f9d0939SLorenzo Bianconi 1844c5aff182SThomas Petazzoni for (i = 0; i < num; i++) { 18459e58c8b4SLorenzo Bianconi struct mvneta_tx_buf *buf = &txq->buf[txq->txq_get_index]; 1846c5aff182SThomas Petazzoni struct mvneta_tx_desc *tx_desc = txq->descs + 1847c5aff182SThomas Petazzoni txq->txq_get_index; 1848a29b6235SMarcin Wojtas 1849c5aff182SThomas Petazzoni mvneta_txq_inc_get(txq); 1850c5aff182SThomas Petazzoni 1851b0a43db9SLorenzo Bianconi if (!IS_TSO_HEADER(txq, tx_desc->buf_phys_addr) && 1852b0a43db9SLorenzo Bianconi buf->type != MVNETA_TYPE_XDP_TX) 18532e3173a3SEzequiel Garcia dma_unmap_single(pp->dev->dev.parent, 18542e3173a3SEzequiel Garcia tx_desc->buf_phys_addr, 1855c5aff182SThomas Petazzoni tx_desc->data_size, DMA_TO_DEVICE); 1856b0a43db9SLorenzo Bianconi if (buf->type == MVNETA_TYPE_SKB && buf->skb) { 18579e58c8b4SLorenzo Bianconi bytes_compl += buf->skb->len; 18589e58c8b4SLorenzo Bianconi pkts_compl++; 18599e58c8b4SLorenzo Bianconi dev_kfree_skb_any(buf->skb); 1860b0a43db9SLorenzo Bianconi } else if (buf->type == MVNETA_TYPE_XDP_TX || 1861b0a43db9SLorenzo Bianconi buf->type == MVNETA_TYPE_XDP_NDO) { 1862632bb64fSLorenzo Bianconi if (napi && buf->type == MVNETA_TYPE_XDP_TX) 1863632bb64fSLorenzo Bianconi xdp_return_frame_rx_napi(buf->xdpf); 1864632bb64fSLorenzo Bianconi else 18652f9d0939SLorenzo Bianconi xdp_return_frame_bulk(buf->xdpf, &bq); 1866b0a43db9SLorenzo Bianconi } 1867c5aff182SThomas Petazzoni } 18682f9d0939SLorenzo Bianconi xdp_flush_frame_bulk(&bq); 18692f9d0939SLorenzo Bianconi 18702f9d0939SLorenzo Bianconi rcu_read_unlock(); 1871a29b6235SMarcin Wojtas 1872a29b6235SMarcin Wojtas netdev_tx_completed_queue(nq, pkts_compl, bytes_compl); 1873c5aff182SThomas Petazzoni } 1874c5aff182SThomas Petazzoni 1875c5aff182SThomas Petazzoni /* Handle end of transmission */ 1876cd713199SArnaud Ebalard static void mvneta_txq_done(struct mvneta_port *pp, 1877c5aff182SThomas Petazzoni struct mvneta_tx_queue *txq) 1878c5aff182SThomas Petazzoni { 1879c5aff182SThomas Petazzoni struct netdev_queue *nq = netdev_get_tx_queue(pp->dev, txq->id); 1880c5aff182SThomas Petazzoni int tx_done; 1881c5aff182SThomas Petazzoni 1882c5aff182SThomas Petazzoni tx_done = mvneta_txq_sent_desc_proc(pp, txq); 1883cd713199SArnaud Ebalard if (!tx_done) 1884cd713199SArnaud Ebalard return; 1885cd713199SArnaud Ebalard 1886632bb64fSLorenzo Bianconi mvneta_txq_bufs_free(pp, txq, tx_done, nq, true); 1887c5aff182SThomas Petazzoni 1888c5aff182SThomas Petazzoni txq->count -= tx_done; 1889c5aff182SThomas Petazzoni 1890c5aff182SThomas Petazzoni if (netif_tx_queue_stopped(nq)) { 18918eef5f97SEzequiel Garcia if (txq->count <= txq->tx_wake_threshold) 1892c5aff182SThomas Petazzoni netif_tx_wake_queue(nq); 1893c5aff182SThomas Petazzoni } 1894c5aff182SThomas Petazzoni } 1895c5aff182SThomas Petazzoni 1896dc35a10fSMarcin Wojtas /* Refill processing for SW buffer management */ 18977e47fd84SGregory CLEMENT /* Allocate page per descriptor */ 1898c5aff182SThomas Petazzoni static int mvneta_rx_refill(struct mvneta_port *pp, 1899f88bee1cSGregory CLEMENT struct mvneta_rx_desc *rx_desc, 19007e47fd84SGregory CLEMENT struct mvneta_rx_queue *rxq, 19017e47fd84SGregory CLEMENT gfp_t gfp_mask) 1902c5aff182SThomas Petazzoni { 1903c5aff182SThomas Petazzoni dma_addr_t phys_addr; 19047e47fd84SGregory CLEMENT struct page *page; 1905c5aff182SThomas Petazzoni 1906568a3fa2SLorenzo Bianconi page = page_pool_alloc_pages(rxq->page_pool, 1907568a3fa2SLorenzo Bianconi gfp_mask | __GFP_NOWARN); 19087e47fd84SGregory CLEMENT if (!page) 1909c5aff182SThomas Petazzoni return -ENOMEM; 1910c5aff182SThomas Petazzoni 1911568a3fa2SLorenzo Bianconi phys_addr = page_pool_get_dma_addr(page) + pp->rx_offset_correction; 19127e47fd84SGregory CLEMENT mvneta_rx_desc_fill(rx_desc, phys_addr, page, rxq); 1913568a3fa2SLorenzo Bianconi 1914c5aff182SThomas Petazzoni return 0; 1915c5aff182SThomas Petazzoni } 1916c5aff182SThomas Petazzoni 1917c5aff182SThomas Petazzoni /* Handle tx checksum */ 191820d446f2SYuval Shaia static u32 mvneta_skb_tx_csum(struct sk_buff *skb) 1919c5aff182SThomas Petazzoni { 1920c5aff182SThomas Petazzoni if (skb->ip_summed == CHECKSUM_PARTIAL) { 1921c5aff182SThomas Petazzoni int ip_hdr_len = 0; 1922817dbfa5SVlad Yasevich __be16 l3_proto = vlan_get_protocol(skb); 1923c5aff182SThomas Petazzoni u8 l4_proto; 1924c5aff182SThomas Petazzoni 1925817dbfa5SVlad Yasevich if (l3_proto == htons(ETH_P_IP)) { 1926c5aff182SThomas Petazzoni struct iphdr *ip4h = ip_hdr(skb); 1927c5aff182SThomas Petazzoni 1928c5aff182SThomas Petazzoni /* Calculate IPv4 checksum and L4 checksum */ 1929c5aff182SThomas Petazzoni ip_hdr_len = ip4h->ihl; 1930c5aff182SThomas Petazzoni l4_proto = ip4h->protocol; 1931817dbfa5SVlad Yasevich } else if (l3_proto == htons(ETH_P_IPV6)) { 1932c5aff182SThomas Petazzoni struct ipv6hdr *ip6h = ipv6_hdr(skb); 1933c5aff182SThomas Petazzoni 1934c5aff182SThomas Petazzoni /* Read l4_protocol from one of IPv6 extra headers */ 1935c5aff182SThomas Petazzoni if (skb_network_header_len(skb) > 0) 1936c5aff182SThomas Petazzoni ip_hdr_len = (skb_network_header_len(skb) >> 2); 1937c5aff182SThomas Petazzoni l4_proto = ip6h->nexthdr; 1938c5aff182SThomas Petazzoni } else 1939c5aff182SThomas Petazzoni return MVNETA_TX_L4_CSUM_NOT; 1940c5aff182SThomas Petazzoni 1941c5aff182SThomas Petazzoni return mvneta_txq_desc_csum(skb_network_offset(skb), 1942817dbfa5SVlad Yasevich l3_proto, ip_hdr_len, l4_proto); 1943c5aff182SThomas Petazzoni } 1944c5aff182SThomas Petazzoni 1945c5aff182SThomas Petazzoni return MVNETA_TX_L4_CSUM_NOT; 1946c5aff182SThomas Petazzoni } 1947c5aff182SThomas Petazzoni 1948c5aff182SThomas Petazzoni /* Drop packets received by the RXQ and free buffers */ 1949c5aff182SThomas Petazzoni static void mvneta_rxq_drop_pkts(struct mvneta_port *pp, 1950c5aff182SThomas Petazzoni struct mvneta_rx_queue *rxq) 1951c5aff182SThomas Petazzoni { 1952c5aff182SThomas Petazzoni int rx_done, i; 1953c5aff182SThomas Petazzoni 1954c5aff182SThomas Petazzoni rx_done = mvneta_rxq_busy_desc_num_get(pp, rxq); 1955dc35a10fSMarcin Wojtas if (rx_done) 1956dc35a10fSMarcin Wojtas mvneta_rxq_desc_num_update(pp, rxq, rx_done, rx_done); 1957dc35a10fSMarcin Wojtas 1958dc35a10fSMarcin Wojtas if (pp->bm_priv) { 1959dc35a10fSMarcin Wojtas for (i = 0; i < rx_done; i++) { 1960dc35a10fSMarcin Wojtas struct mvneta_rx_desc *rx_desc = 1961dc35a10fSMarcin Wojtas mvneta_rxq_next_desc_get(rxq); 1962dc35a10fSMarcin Wojtas u8 pool_id = MVNETA_RX_GET_BM_POOL_ID(rx_desc); 1963dc35a10fSMarcin Wojtas struct mvneta_bm_pool *bm_pool; 1964dc35a10fSMarcin Wojtas 1965dc35a10fSMarcin Wojtas bm_pool = &pp->bm_priv->bm_pools[pool_id]; 1966dc35a10fSMarcin Wojtas /* Return dropped buffer to the pool */ 1967dc35a10fSMarcin Wojtas mvneta_bm_pool_put_bp(pp->bm_priv, bm_pool, 1968dc35a10fSMarcin Wojtas rx_desc->buf_phys_addr); 1969dc35a10fSMarcin Wojtas } 1970dc35a10fSMarcin Wojtas return; 1971dc35a10fSMarcin Wojtas } 1972dc35a10fSMarcin Wojtas 1973c5aff182SThomas Petazzoni for (i = 0; i < rxq->size; i++) { 1974c5aff182SThomas Petazzoni struct mvneta_rx_desc *rx_desc = rxq->descs + i; 1975f88bee1cSGregory CLEMENT void *data = rxq->buf_virt_addr[i]; 1976562e2f46SYelena Krivosheev if (!data || !(rx_desc->buf_phys_addr)) 1977562e2f46SYelena Krivosheev continue; 1978c5aff182SThomas Petazzoni 1979458de8a9SIlias Apalodimas page_pool_put_full_page(rxq->page_pool, data, false); 1980dc35a10fSMarcin Wojtas } 1981568a3fa2SLorenzo Bianconi if (xdp_rxq_info_is_reg(&rxq->xdp_rxq)) 1982568a3fa2SLorenzo Bianconi xdp_rxq_info_unreg(&rxq->xdp_rxq); 1983568a3fa2SLorenzo Bianconi page_pool_destroy(rxq->page_pool); 1984568a3fa2SLorenzo Bianconi rxq->page_pool = NULL; 1985c5aff182SThomas Petazzoni } 1986c5aff182SThomas Petazzoni 1987ff519e2aSLorenzo Bianconi static void 1988320d5441SLorenzo Bianconi mvneta_update_stats(struct mvneta_port *pp, 1989320d5441SLorenzo Bianconi struct mvneta_stats *ps) 1990ff519e2aSLorenzo Bianconi { 1991ff519e2aSLorenzo Bianconi struct mvneta_pcpu_stats *stats = this_cpu_ptr(pp->stats); 1992ff519e2aSLorenzo Bianconi 1993ff519e2aSLorenzo Bianconi u64_stats_update_begin(&stats->syncp); 1994320d5441SLorenzo Bianconi stats->es.ps.rx_packets += ps->rx_packets; 1995320d5441SLorenzo Bianconi stats->es.ps.rx_bytes += ps->rx_bytes; 19963d866523SLorenzo Bianconi /* xdp */ 19973d866523SLorenzo Bianconi stats->es.ps.xdp_redirect += ps->xdp_redirect; 19983d866523SLorenzo Bianconi stats->es.ps.xdp_pass += ps->xdp_pass; 19993d866523SLorenzo Bianconi stats->es.ps.xdp_drop += ps->xdp_drop; 2000ff519e2aSLorenzo Bianconi u64_stats_update_end(&stats->syncp); 2001ff519e2aSLorenzo Bianconi } 2002ff519e2aSLorenzo Bianconi 2003562e2f46SYelena Krivosheev static inline 2004562e2f46SYelena Krivosheev int mvneta_rx_refill_queue(struct mvneta_port *pp, struct mvneta_rx_queue *rxq) 2005562e2f46SYelena Krivosheev { 2006562e2f46SYelena Krivosheev struct mvneta_rx_desc *rx_desc; 2007562e2f46SYelena Krivosheev int curr_desc = rxq->first_to_refill; 2008562e2f46SYelena Krivosheev int i; 2009562e2f46SYelena Krivosheev 2010562e2f46SYelena Krivosheev for (i = 0; (i < rxq->refill_num) && (i < 64); i++) { 2011562e2f46SYelena Krivosheev rx_desc = rxq->descs + curr_desc; 2012562e2f46SYelena Krivosheev if (!(rx_desc->buf_phys_addr)) { 2013562e2f46SYelena Krivosheev if (mvneta_rx_refill(pp, rx_desc, rxq, GFP_ATOMIC)) { 20149ac41f3cSLorenzo Bianconi struct mvneta_pcpu_stats *stats; 20159ac41f3cSLorenzo Bianconi 2016562e2f46SYelena Krivosheev pr_err("Can't refill queue %d. Done %d from %d\n", 2017562e2f46SYelena Krivosheev rxq->id, i, rxq->refill_num); 20189ac41f3cSLorenzo Bianconi 20199ac41f3cSLorenzo Bianconi stats = this_cpu_ptr(pp->stats); 20209ac41f3cSLorenzo Bianconi u64_stats_update_begin(&stats->syncp); 20219ac41f3cSLorenzo Bianconi stats->es.refill_error++; 20229ac41f3cSLorenzo Bianconi u64_stats_update_end(&stats->syncp); 2023562e2f46SYelena Krivosheev break; 2024562e2f46SYelena Krivosheev } 2025562e2f46SYelena Krivosheev } 2026562e2f46SYelena Krivosheev curr_desc = MVNETA_QUEUE_NEXT_DESC(rxq, curr_desc); 2027562e2f46SYelena Krivosheev } 2028562e2f46SYelena Krivosheev rxq->refill_num -= i; 2029562e2f46SYelena Krivosheev rxq->first_to_refill = curr_desc; 2030562e2f46SYelena Krivosheev 2031562e2f46SYelena Krivosheev return i; 2032562e2f46SYelena Krivosheev } 2033562e2f46SYelena Krivosheev 2034ca0e0146SLorenzo Bianconi static void 2035ca0e0146SLorenzo Bianconi mvneta_xdp_put_buff(struct mvneta_port *pp, struct mvneta_rx_queue *rxq, 2036eb33f118SLorenzo Bianconi struct xdp_buff *xdp, struct skb_shared_info *sinfo, 2037eb33f118SLorenzo Bianconi int sync_len) 2038ca0e0146SLorenzo Bianconi { 2039ca0e0146SLorenzo Bianconi int i; 2040ca0e0146SLorenzo Bianconi 2041ca0e0146SLorenzo Bianconi for (i = 0; i < sinfo->nr_frags; i++) 2042ca0e0146SLorenzo Bianconi page_pool_put_full_page(rxq->page_pool, 2043eb33f118SLorenzo Bianconi skb_frag_page(&sinfo->frags[i]), true); 20449d3b2d3eSLorenzo Bianconi page_pool_put_page(rxq->page_pool, virt_to_head_page(xdp->data), 2045eb33f118SLorenzo Bianconi sync_len, true); 2046ca0e0146SLorenzo Bianconi } 2047ca0e0146SLorenzo Bianconi 20488dc9a088SLorenzo Bianconi static int 2049b0a43db9SLorenzo Bianconi mvneta_xdp_submit_frame(struct mvneta_port *pp, struct mvneta_tx_queue *txq, 2050b0a43db9SLorenzo Bianconi struct xdp_frame *xdpf, bool dma_map) 2051b0a43db9SLorenzo Bianconi { 2052b0a43db9SLorenzo Bianconi struct mvneta_tx_desc *tx_desc; 2053b0a43db9SLorenzo Bianconi struct mvneta_tx_buf *buf; 2054b0a43db9SLorenzo Bianconi dma_addr_t dma_addr; 2055b0a43db9SLorenzo Bianconi 2056b0a43db9SLorenzo Bianconi if (txq->count >= txq->tx_stop_threshold) 2057b0a43db9SLorenzo Bianconi return MVNETA_XDP_DROPPED; 2058b0a43db9SLorenzo Bianconi 2059b0a43db9SLorenzo Bianconi tx_desc = mvneta_txq_next_desc_get(txq); 2060b0a43db9SLorenzo Bianconi 2061b0a43db9SLorenzo Bianconi buf = &txq->buf[txq->txq_put_index]; 2062b0a43db9SLorenzo Bianconi if (dma_map) { 2063b0a43db9SLorenzo Bianconi /* ndo_xdp_xmit */ 2064b0a43db9SLorenzo Bianconi dma_addr = dma_map_single(pp->dev->dev.parent, xdpf->data, 2065b0a43db9SLorenzo Bianconi xdpf->len, DMA_TO_DEVICE); 2066b0a43db9SLorenzo Bianconi if (dma_mapping_error(pp->dev->dev.parent, dma_addr)) { 2067b0a43db9SLorenzo Bianconi mvneta_txq_desc_put(txq); 2068b0a43db9SLorenzo Bianconi return MVNETA_XDP_DROPPED; 2069b0a43db9SLorenzo Bianconi } 2070b0a43db9SLorenzo Bianconi buf->type = MVNETA_TYPE_XDP_NDO; 2071b0a43db9SLorenzo Bianconi } else { 2072b0a43db9SLorenzo Bianconi struct page *page = virt_to_page(xdpf->data); 2073b0a43db9SLorenzo Bianconi 2074b0a43db9SLorenzo Bianconi dma_addr = page_pool_get_dma_addr(page) + 2075b0a43db9SLorenzo Bianconi sizeof(*xdpf) + xdpf->headroom; 2076b0a43db9SLorenzo Bianconi dma_sync_single_for_device(pp->dev->dev.parent, dma_addr, 2077b0a43db9SLorenzo Bianconi xdpf->len, DMA_BIDIRECTIONAL); 2078b0a43db9SLorenzo Bianconi buf->type = MVNETA_TYPE_XDP_TX; 2079b0a43db9SLorenzo Bianconi } 2080b0a43db9SLorenzo Bianconi buf->xdpf = xdpf; 2081b0a43db9SLorenzo Bianconi 2082b0a43db9SLorenzo Bianconi tx_desc->command = MVNETA_TXD_FLZ_DESC; 2083b0a43db9SLorenzo Bianconi tx_desc->buf_phys_addr = dma_addr; 2084b0a43db9SLorenzo Bianconi tx_desc->data_size = xdpf->len; 2085b0a43db9SLorenzo Bianconi 2086b0a43db9SLorenzo Bianconi mvneta_txq_inc_put(txq); 2087b0a43db9SLorenzo Bianconi txq->pending++; 2088b0a43db9SLorenzo Bianconi txq->count++; 2089b0a43db9SLorenzo Bianconi 2090b0a43db9SLorenzo Bianconi return MVNETA_XDP_TX; 2091b0a43db9SLorenzo Bianconi } 2092b0a43db9SLorenzo Bianconi 2093b0a43db9SLorenzo Bianconi static int 2094b0a43db9SLorenzo Bianconi mvneta_xdp_xmit_back(struct mvneta_port *pp, struct xdp_buff *xdp) 2095b0a43db9SLorenzo Bianconi { 209615070919SJesper Dangaard Brouer struct mvneta_pcpu_stats *stats = this_cpu_ptr(pp->stats); 2097b0a43db9SLorenzo Bianconi struct mvneta_tx_queue *txq; 2098b0a43db9SLorenzo Bianconi struct netdev_queue *nq; 2099b0a43db9SLorenzo Bianconi struct xdp_frame *xdpf; 2100b0a43db9SLorenzo Bianconi int cpu; 2101b0a43db9SLorenzo Bianconi u32 ret; 2102b0a43db9SLorenzo Bianconi 21031b698fa5SLorenzo Bianconi xdpf = xdp_convert_buff_to_frame(xdp); 2104b0a43db9SLorenzo Bianconi if (unlikely(!xdpf)) 2105b0a43db9SLorenzo Bianconi return MVNETA_XDP_DROPPED; 2106b0a43db9SLorenzo Bianconi 2107b0a43db9SLorenzo Bianconi cpu = smp_processor_id(); 2108b0a43db9SLorenzo Bianconi txq = &pp->txqs[cpu % txq_number]; 2109b0a43db9SLorenzo Bianconi nq = netdev_get_tx_queue(pp->dev, txq->id); 2110b0a43db9SLorenzo Bianconi 2111b0a43db9SLorenzo Bianconi __netif_tx_lock(nq, cpu); 2112b0a43db9SLorenzo Bianconi ret = mvneta_xdp_submit_frame(pp, txq, xdpf, false); 21137d51a015SLorenzo Bianconi if (ret == MVNETA_XDP_TX) { 21147d51a015SLorenzo Bianconi u64_stats_update_begin(&stats->syncp); 21157d51a015SLorenzo Bianconi stats->es.ps.tx_bytes += xdpf->len; 21167d51a015SLorenzo Bianconi stats->es.ps.tx_packets++; 21177d51a015SLorenzo Bianconi stats->es.ps.xdp_tx++; 21187d51a015SLorenzo Bianconi u64_stats_update_end(&stats->syncp); 21197d51a015SLorenzo Bianconi 2120b0a43db9SLorenzo Bianconi mvneta_txq_pend_desc_add(pp, txq, 0); 212115070919SJesper Dangaard Brouer } else { 212215070919SJesper Dangaard Brouer u64_stats_update_begin(&stats->syncp); 212315070919SJesper Dangaard Brouer stats->es.ps.xdp_tx_err++; 212415070919SJesper Dangaard Brouer u64_stats_update_end(&stats->syncp); 21257d51a015SLorenzo Bianconi } 2126b0a43db9SLorenzo Bianconi __netif_tx_unlock(nq); 2127b0a43db9SLorenzo Bianconi 2128b0a43db9SLorenzo Bianconi return ret; 2129b0a43db9SLorenzo Bianconi } 2130b0a43db9SLorenzo Bianconi 2131b0a43db9SLorenzo Bianconi static int 2132b0a43db9SLorenzo Bianconi mvneta_xdp_xmit(struct net_device *dev, int num_frame, 2133b0a43db9SLorenzo Bianconi struct xdp_frame **frames, u32 flags) 2134b0a43db9SLorenzo Bianconi { 2135b0a43db9SLorenzo Bianconi struct mvneta_port *pp = netdev_priv(dev); 21367d51a015SLorenzo Bianconi struct mvneta_pcpu_stats *stats = this_cpu_ptr(pp->stats); 2137fdc13979SLorenzo Bianconi int i, nxmit_byte = 0, nxmit = 0; 2138b0a43db9SLorenzo Bianconi int cpu = smp_processor_id(); 2139b0a43db9SLorenzo Bianconi struct mvneta_tx_queue *txq; 2140b0a43db9SLorenzo Bianconi struct netdev_queue *nq; 2141b0a43db9SLorenzo Bianconi u32 ret; 2142b0a43db9SLorenzo Bianconi 214362a502ccSLorenzo Bianconi if (unlikely(test_bit(__MVNETA_DOWN, &pp->state))) 214462a502ccSLorenzo Bianconi return -ENETDOWN; 214562a502ccSLorenzo Bianconi 2146b0a43db9SLorenzo Bianconi if (unlikely(flags & ~XDP_XMIT_FLAGS_MASK)) 2147b0a43db9SLorenzo Bianconi return -EINVAL; 2148b0a43db9SLorenzo Bianconi 2149b0a43db9SLorenzo Bianconi txq = &pp->txqs[cpu % txq_number]; 2150b0a43db9SLorenzo Bianconi nq = netdev_get_tx_queue(pp->dev, txq->id); 2151b0a43db9SLorenzo Bianconi 2152b0a43db9SLorenzo Bianconi __netif_tx_lock(nq, cpu); 2153b0a43db9SLorenzo Bianconi for (i = 0; i < num_frame; i++) { 2154b0a43db9SLorenzo Bianconi ret = mvneta_xdp_submit_frame(pp, txq, frames[i], true); 2155fdc13979SLorenzo Bianconi if (ret != MVNETA_XDP_TX) 2156fdc13979SLorenzo Bianconi break; 2157fdc13979SLorenzo Bianconi 21587d51a015SLorenzo Bianconi nxmit_byte += frames[i]->len; 2159fdc13979SLorenzo Bianconi nxmit++; 2160b0a43db9SLorenzo Bianconi } 2161b0a43db9SLorenzo Bianconi 2162b0a43db9SLorenzo Bianconi if (unlikely(flags & XDP_XMIT_FLUSH)) 2163b0a43db9SLorenzo Bianconi mvneta_txq_pend_desc_add(pp, txq, 0); 2164b0a43db9SLorenzo Bianconi __netif_tx_unlock(nq); 2165b0a43db9SLorenzo Bianconi 21667d51a015SLorenzo Bianconi u64_stats_update_begin(&stats->syncp); 21677d51a015SLorenzo Bianconi stats->es.ps.tx_bytes += nxmit_byte; 21687d51a015SLorenzo Bianconi stats->es.ps.tx_packets += nxmit; 21697d51a015SLorenzo Bianconi stats->es.ps.xdp_xmit += nxmit; 217015070919SJesper Dangaard Brouer stats->es.ps.xdp_xmit_err += num_frame - nxmit; 21717d51a015SLorenzo Bianconi u64_stats_update_end(&stats->syncp); 21727d51a015SLorenzo Bianconi 21737d51a015SLorenzo Bianconi return nxmit; 2174b0a43db9SLorenzo Bianconi } 2175b0a43db9SLorenzo Bianconi 2176b0a43db9SLorenzo Bianconi static int 21770db51da7SLorenzo Bianconi mvneta_run_xdp(struct mvneta_port *pp, struct mvneta_rx_queue *rxq, 2178320d5441SLorenzo Bianconi struct bpf_prog *prog, struct xdp_buff *xdp, 21797d1643ebSLorenzo Bianconi u32 frame_sz, struct mvneta_stats *stats) 21800db51da7SLorenzo Bianconi { 2181eb33f118SLorenzo Bianconi struct skb_shared_info *sinfo = xdp_get_shared_info_from_buff(xdp); 21827d1643ebSLorenzo Bianconi unsigned int len, data_len, sync; 21838c4df83fSLorenzo Bianconi u32 ret, act; 21848c4df83fSLorenzo Bianconi 21858c4df83fSLorenzo Bianconi len = xdp->data_end - xdp->data_hard_start - pp->rx_offset_correction; 21867d1643ebSLorenzo Bianconi data_len = xdp->data_end - xdp->data; 21878c4df83fSLorenzo Bianconi act = bpf_prog_run_xdp(prog, xdp); 21880db51da7SLorenzo Bianconi 2189494f44d5SJesper Dangaard Brouer /* Due xdp_adjust_tail: DMA sync for_device cover max len CPU touch */ 2190494f44d5SJesper Dangaard Brouer sync = xdp->data_end - xdp->data_hard_start - pp->rx_offset_correction; 2191494f44d5SJesper Dangaard Brouer sync = max(sync, len); 2192494f44d5SJesper Dangaard Brouer 21930db51da7SLorenzo Bianconi switch (act) { 21940db51da7SLorenzo Bianconi case XDP_PASS: 21953d866523SLorenzo Bianconi stats->xdp_pass++; 2196320d5441SLorenzo Bianconi return MVNETA_XDP_PASS; 21970db51da7SLorenzo Bianconi case XDP_REDIRECT: { 21980db51da7SLorenzo Bianconi int err; 21990db51da7SLorenzo Bianconi 22000db51da7SLorenzo Bianconi err = xdp_do_redirect(pp->dev, xdp, prog); 220115070919SJesper Dangaard Brouer if (unlikely(err)) { 2202eb33f118SLorenzo Bianconi mvneta_xdp_put_buff(pp, rxq, xdp, sinfo, sync); 22030db51da7SLorenzo Bianconi ret = MVNETA_XDP_DROPPED; 22040db51da7SLorenzo Bianconi } else { 22050db51da7SLorenzo Bianconi ret = MVNETA_XDP_REDIR; 22063d866523SLorenzo Bianconi stats->xdp_redirect++; 22070db51da7SLorenzo Bianconi } 22080db51da7SLorenzo Bianconi break; 22090db51da7SLorenzo Bianconi } 2210b0a43db9SLorenzo Bianconi case XDP_TX: 2211b0a43db9SLorenzo Bianconi ret = mvneta_xdp_xmit_back(pp, xdp); 22127d1643ebSLorenzo Bianconi if (ret != MVNETA_XDP_TX) 2213eb33f118SLorenzo Bianconi mvneta_xdp_put_buff(pp, rxq, xdp, sinfo, sync); 2214b0a43db9SLorenzo Bianconi break; 22150db51da7SLorenzo Bianconi default: 22160db51da7SLorenzo Bianconi bpf_warn_invalid_xdp_action(act); 2217df561f66SGustavo A. R. Silva fallthrough; 22180db51da7SLorenzo Bianconi case XDP_ABORTED: 22190db51da7SLorenzo Bianconi trace_xdp_exception(pp->dev, prog, act); 2220df561f66SGustavo A. R. Silva fallthrough; 22210db51da7SLorenzo Bianconi case XDP_DROP: 2222eb33f118SLorenzo Bianconi mvneta_xdp_put_buff(pp, rxq, xdp, sinfo, sync); 22230db51da7SLorenzo Bianconi ret = MVNETA_XDP_DROPPED; 22243d866523SLorenzo Bianconi stats->xdp_drop++; 22250db51da7SLorenzo Bianconi break; 22260db51da7SLorenzo Bianconi } 22270db51da7SLorenzo Bianconi 22287d1643ebSLorenzo Bianconi stats->rx_bytes += frame_sz + xdp->data_end - xdp->data - data_len; 2229320d5441SLorenzo Bianconi stats->rx_packets++; 2230320d5441SLorenzo Bianconi 22310db51da7SLorenzo Bianconi return ret; 22320db51da7SLorenzo Bianconi } 22330db51da7SLorenzo Bianconi 2234afda408bSLorenzo Bianconi static void 22358dc9a088SLorenzo Bianconi mvneta_swbm_rx_frame(struct mvneta_port *pp, 22368dc9a088SLorenzo Bianconi struct mvneta_rx_desc *rx_desc, 22378dc9a088SLorenzo Bianconi struct mvneta_rx_queue *rxq, 2238c7a3a8cdSLorenzo Bianconi struct xdp_buff *xdp, int *size, 22393a8c4ad1SLorenzo Bianconi struct page *page) 22408dc9a088SLorenzo Bianconi { 22418dc9a088SLorenzo Bianconi unsigned char *data = page_address(page); 22428dc9a088SLorenzo Bianconi int data_len = -MVNETA_MH_SIZE, len; 22438dc9a088SLorenzo Bianconi struct net_device *dev = pp->dev; 22448dc9a088SLorenzo Bianconi enum dma_data_direction dma_dir; 2245ca0e0146SLorenzo Bianconi struct skb_shared_info *sinfo; 22468dc9a088SLorenzo Bianconi 2247879456beSLorenzo Bianconi if (*size > MVNETA_MAX_RX_BUF_SIZE) { 22488dc9a088SLorenzo Bianconi len = MVNETA_MAX_RX_BUF_SIZE; 22498dc9a088SLorenzo Bianconi data_len += len; 22508dc9a088SLorenzo Bianconi } else { 2251879456beSLorenzo Bianconi len = *size; 22528dc9a088SLorenzo Bianconi data_len += len - ETH_FCS_LEN; 22538dc9a088SLorenzo Bianconi } 2254879456beSLorenzo Bianconi *size = *size - len; 22558dc9a088SLorenzo Bianconi 22568dc9a088SLorenzo Bianconi dma_dir = page_pool_get_dma_dir(rxq->page_pool); 22578dc9a088SLorenzo Bianconi dma_sync_single_for_cpu(dev->dev.parent, 22588dc9a088SLorenzo Bianconi rx_desc->buf_phys_addr, 22598dc9a088SLorenzo Bianconi len, dma_dir); 22608dc9a088SLorenzo Bianconi 2261879456beSLorenzo Bianconi rx_desc->buf_phys_addr = 0; 2262879456beSLorenzo Bianconi 2263fa383f6bSLorenzo Bianconi /* Prefetch header */ 2264fa383f6bSLorenzo Bianconi prefetch(data); 2265be9df4afSLorenzo Bianconi xdp_prepare_buff(xdp, data, pp->rx_offset_correction + MVNETA_MH_SIZE, 2266be9df4afSLorenzo Bianconi data_len, false); 22670db51da7SLorenzo Bianconi 2268ca0e0146SLorenzo Bianconi sinfo = xdp_get_shared_info_from_buff(xdp); 2269ca0e0146SLorenzo Bianconi sinfo->nr_frags = 0; 22708dc9a088SLorenzo Bianconi } 22718dc9a088SLorenzo Bianconi 22728dc9a088SLorenzo Bianconi static void 22738dc9a088SLorenzo Bianconi mvneta_swbm_add_rx_fragment(struct mvneta_port *pp, 22748dc9a088SLorenzo Bianconi struct mvneta_rx_desc *rx_desc, 22758dc9a088SLorenzo Bianconi struct mvneta_rx_queue *rxq, 2276c7a3a8cdSLorenzo Bianconi struct xdp_buff *xdp, int *size, 2277039fbc47SLorenzo Bianconi struct skb_shared_info *xdp_sinfo, 22788dc9a088SLorenzo Bianconi struct page *page) 22798dc9a088SLorenzo Bianconi { 22808dc9a088SLorenzo Bianconi struct net_device *dev = pp->dev; 22818dc9a088SLorenzo Bianconi enum dma_data_direction dma_dir; 22828dc9a088SLorenzo Bianconi int data_len, len; 22838dc9a088SLorenzo Bianconi 2284c7a3a8cdSLorenzo Bianconi if (*size > MVNETA_MAX_RX_BUF_SIZE) { 22858dc9a088SLorenzo Bianconi len = MVNETA_MAX_RX_BUF_SIZE; 22868dc9a088SLorenzo Bianconi data_len = len; 22878dc9a088SLorenzo Bianconi } else { 2288c7a3a8cdSLorenzo Bianconi len = *size; 22898dc9a088SLorenzo Bianconi data_len = len - ETH_FCS_LEN; 22908dc9a088SLorenzo Bianconi } 22918dc9a088SLorenzo Bianconi dma_dir = page_pool_get_dma_dir(rxq->page_pool); 22928dc9a088SLorenzo Bianconi dma_sync_single_for_cpu(dev->dev.parent, 22938dc9a088SLorenzo Bianconi rx_desc->buf_phys_addr, 22948dc9a088SLorenzo Bianconi len, dma_dir); 22959c79a8abSLorenzo Bianconi rx_desc->buf_phys_addr = 0; 2296ca0e0146SLorenzo Bianconi 2297039fbc47SLorenzo Bianconi if (data_len > 0 && xdp_sinfo->nr_frags < MAX_SKB_FRAGS) { 2298039fbc47SLorenzo Bianconi skb_frag_t *frag = &xdp_sinfo->frags[xdp_sinfo->nr_frags++]; 2299ca0e0146SLorenzo Bianconi 2300ca0e0146SLorenzo Bianconi skb_frag_off_set(frag, pp->rx_offset_correction); 2301ca0e0146SLorenzo Bianconi skb_frag_size_set(frag, data_len); 2302ca0e0146SLorenzo Bianconi __skb_frag_set_page(frag, page); 23036ff63a15SLorenzo Bianconi } else { 23046ff63a15SLorenzo Bianconi page_pool_put_full_page(rxq->page_pool, page, true); 23056ff63a15SLorenzo Bianconi } 2306039fbc47SLorenzo Bianconi 2307039fbc47SLorenzo Bianconi /* last fragment */ 2308039fbc47SLorenzo Bianconi if (len == *size) { 2309039fbc47SLorenzo Bianconi struct skb_shared_info *sinfo; 2310039fbc47SLorenzo Bianconi 2311039fbc47SLorenzo Bianconi sinfo = xdp_get_shared_info_from_buff(xdp); 2312039fbc47SLorenzo Bianconi sinfo->nr_frags = xdp_sinfo->nr_frags; 2313039fbc47SLorenzo Bianconi memcpy(sinfo->frags, xdp_sinfo->frags, 2314039fbc47SLorenzo Bianconi sinfo->nr_frags * sizeof(skb_frag_t)); 2315039fbc47SLorenzo Bianconi } 2316c7a3a8cdSLorenzo Bianconi *size -= len; 23178dc9a088SLorenzo Bianconi } 23188dc9a088SLorenzo Bianconi 2319ca0e0146SLorenzo Bianconi static struct sk_buff * 2320e4017570SMatteo Croce mvneta_swbm_build_skb(struct mvneta_port *pp, struct page_pool *pool, 2321ca0e0146SLorenzo Bianconi struct xdp_buff *xdp, u32 desc_status) 2322ca0e0146SLorenzo Bianconi { 2323ca0e0146SLorenzo Bianconi struct skb_shared_info *sinfo = xdp_get_shared_info_from_buff(xdp); 2324ca0e0146SLorenzo Bianconi int i, num_frags = sinfo->nr_frags; 2325ca0e0146SLorenzo Bianconi struct sk_buff *skb; 2326ca0e0146SLorenzo Bianconi 2327ca0e0146SLorenzo Bianconi skb = build_skb(xdp->data_hard_start, PAGE_SIZE); 2328ca0e0146SLorenzo Bianconi if (!skb) 2329ca0e0146SLorenzo Bianconi return ERR_PTR(-ENOMEM); 2330ca0e0146SLorenzo Bianconi 233157f05bc2SYunsheng Lin skb_mark_for_recycle(skb); 2332ca0e0146SLorenzo Bianconi 2333ca0e0146SLorenzo Bianconi skb_reserve(skb, xdp->data - xdp->data_hard_start); 2334ca0e0146SLorenzo Bianconi skb_put(skb, xdp->data_end - xdp->data); 2335aff0824dSLorenzo Bianconi skb->ip_summed = mvneta_rx_csum(pp, desc_status); 2336ca0e0146SLorenzo Bianconi 2337ca0e0146SLorenzo Bianconi for (i = 0; i < num_frags; i++) { 233852731441SLorenzo Bianconi skb_frag_t *frag = &sinfo->frags[i]; 2339ca0e0146SLorenzo Bianconi 2340ca0e0146SLorenzo Bianconi skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, 234152731441SLorenzo Bianconi skb_frag_page(frag), skb_frag_off(frag), 234252731441SLorenzo Bianconi skb_frag_size(frag), PAGE_SIZE); 2343ca0e0146SLorenzo Bianconi } 2344ca0e0146SLorenzo Bianconi 2345ca0e0146SLorenzo Bianconi return skb; 2346ca0e0146SLorenzo Bianconi } 2347ca0e0146SLorenzo Bianconi 2348dc35a10fSMarcin Wojtas /* Main rx processing when using software buffer management */ 23497a86f05fSAndrew Lunn static int mvneta_rx_swbm(struct napi_struct *napi, 2350562e2f46SYelena Krivosheev struct mvneta_port *pp, int budget, 2351c5aff182SThomas Petazzoni struct mvneta_rx_queue *rxq) 2352c5aff182SThomas Petazzoni { 2353c7a3a8cdSLorenzo Bianconi int rx_proc = 0, rx_todo, refill, size = 0; 2354c5aff182SThomas Petazzoni struct net_device *dev = pp->dev; 2355039fbc47SLorenzo Bianconi struct skb_shared_info sinfo; 2356320d5441SLorenzo Bianconi struct mvneta_stats ps = {}; 23570db51da7SLorenzo Bianconi struct bpf_prog *xdp_prog; 23587d1643ebSLorenzo Bianconi u32 desc_status, frame_sz; 235905c748f7SLorenzo Bianconi struct xdp_buff xdp_buf; 236005c748f7SLorenzo Bianconi 236143b5169dSLorenzo Bianconi xdp_init_buff(&xdp_buf, PAGE_SIZE, &rxq->xdp_rxq); 236205c748f7SLorenzo Bianconi xdp_buf.data_hard_start = NULL; 2363c5aff182SThomas Petazzoni 2364039fbc47SLorenzo Bianconi sinfo.nr_frags = 0; 2365039fbc47SLorenzo Bianconi 2366c5aff182SThomas Petazzoni /* Get number of received packets */ 2367562e2f46SYelena Krivosheev rx_todo = mvneta_rxq_busy_desc_num_get(pp, rxq); 2368c5aff182SThomas Petazzoni 23690db51da7SLorenzo Bianconi xdp_prog = READ_ONCE(pp->xdp_prog); 23700db51da7SLorenzo Bianconi 2371c5aff182SThomas Petazzoni /* Fairness NAPI loop */ 23728dc9a088SLorenzo Bianconi while (rx_proc < budget && rx_proc < rx_todo) { 2373c5aff182SThomas Petazzoni struct mvneta_rx_desc *rx_desc = mvneta_rxq_next_desc_get(rxq); 23748dc9a088SLorenzo Bianconi u32 rx_status, index; 2375ca0e0146SLorenzo Bianconi struct sk_buff *skb; 23767e47fd84SGregory CLEMENT struct page *page; 2377c5aff182SThomas Petazzoni 2378f88bee1cSGregory CLEMENT index = rx_desc - rxq->descs; 23797e47fd84SGregory CLEMENT page = (struct page *)rxq->buf_virt_addr[index]; 2380c5aff182SThomas Petazzoni 2381562e2f46SYelena Krivosheev rx_status = rx_desc->status; 2382562e2f46SYelena Krivosheev rx_proc++; 2383562e2f46SYelena Krivosheev rxq->refill_num++; 2384562e2f46SYelena Krivosheev 2385562e2f46SYelena Krivosheev if (rx_status & MVNETA_RXD_FIRST_DESC) { 2386562e2f46SYelena Krivosheev /* Check errors only for FIRST descriptor */ 2387562e2f46SYelena Krivosheev if (rx_status & MVNETA_RXD_ERR_SUMMARY) { 23882eecb2e0SYelena Krivosheev mvneta_rx_error(pp, rx_desc); 2389ca0e0146SLorenzo Bianconi goto next; 2390c5aff182SThomas Petazzoni } 2391c5aff182SThomas Petazzoni 2392c7a3a8cdSLorenzo Bianconi size = rx_desc->data_size; 2393c7a3a8cdSLorenzo Bianconi frame_sz = size - ETH_FCS_LEN; 2394879456beSLorenzo Bianconi desc_status = rx_status; 23957d1643ebSLorenzo Bianconi 2396c7a3a8cdSLorenzo Bianconi mvneta_swbm_rx_frame(pp, rx_desc, rxq, &xdp_buf, 23973a8c4ad1SLorenzo Bianconi &size, page); 2398562e2f46SYelena Krivosheev } else { 2399b6e11785SLorenzo Bianconi if (unlikely(!xdp_buf.data_hard_start)) { 2400b6e11785SLorenzo Bianconi rx_desc->buf_phys_addr = 0; 2401b6e11785SLorenzo Bianconi page_pool_put_full_page(rxq->page_pool, page, 2402b6e11785SLorenzo Bianconi true); 2403039fbc47SLorenzo Bianconi goto next; 2404b6e11785SLorenzo Bianconi } 2405ca0e0146SLorenzo Bianconi 2406ca0e0146SLorenzo Bianconi mvneta_swbm_add_rx_fragment(pp, rx_desc, rxq, &xdp_buf, 2407039fbc47SLorenzo Bianconi &size, &sinfo, page); 2408562e2f46SYelena Krivosheev } /* Middle or Last descriptor */ 2409562e2f46SYelena Krivosheev 2410562e2f46SYelena Krivosheev if (!(rx_status & MVNETA_RXD_LAST_DESC)) 2411562e2f46SYelena Krivosheev /* no last descriptor this time */ 2412562e2f46SYelena Krivosheev continue; 2413562e2f46SYelena Krivosheev 2414c7a3a8cdSLorenzo Bianconi if (size) { 2415039fbc47SLorenzo Bianconi mvneta_xdp_put_buff(pp, rxq, &xdp_buf, &sinfo, -1); 2416ca0e0146SLorenzo Bianconi goto next; 2417562e2f46SYelena Krivosheev } 2418320d5441SLorenzo Bianconi 2419afda408bSLorenzo Bianconi if (xdp_prog && 24207d1643ebSLorenzo Bianconi mvneta_run_xdp(pp, rxq, xdp_prog, &xdp_buf, frame_sz, &ps)) 2421afda408bSLorenzo Bianconi goto next; 2422afda408bSLorenzo Bianconi 2423e4017570SMatteo Croce skb = mvneta_swbm_build_skb(pp, rxq->page_pool, &xdp_buf, desc_status); 2424ca0e0146SLorenzo Bianconi if (IS_ERR(skb)) { 2425ca0e0146SLorenzo Bianconi struct mvneta_pcpu_stats *stats = this_cpu_ptr(pp->stats); 2426ca0e0146SLorenzo Bianconi 2427039fbc47SLorenzo Bianconi mvneta_xdp_put_buff(pp, rxq, &xdp_buf, &sinfo, -1); 2428ca0e0146SLorenzo Bianconi 2429ca0e0146SLorenzo Bianconi u64_stats_update_begin(&stats->syncp); 2430ca0e0146SLorenzo Bianconi stats->es.skb_alloc_error++; 2431ca0e0146SLorenzo Bianconi stats->rx_dropped++; 2432ca0e0146SLorenzo Bianconi u64_stats_update_end(&stats->syncp); 2433ca0e0146SLorenzo Bianconi 2434ca0e0146SLorenzo Bianconi goto next; 2435ca0e0146SLorenzo Bianconi } 2436ca0e0146SLorenzo Bianconi 2437ca0e0146SLorenzo Bianconi ps.rx_bytes += skb->len; 2438320d5441SLorenzo Bianconi ps.rx_packets++; 2439c5aff182SThomas Petazzoni 2440ca0e0146SLorenzo Bianconi skb->protocol = eth_type_trans(skb, dev); 2441ca0e0146SLorenzo Bianconi napi_gro_receive(napi, skb); 2442ca0e0146SLorenzo Bianconi next: 2443ca0e0146SLorenzo Bianconi xdp_buf.data_hard_start = NULL; 2444039fbc47SLorenzo Bianconi sinfo.nr_frags = 0; 2445c5aff182SThomas Petazzoni } 24460db51da7SLorenzo Bianconi 2447039fbc47SLorenzo Bianconi if (xdp_buf.data_hard_start) 2448039fbc47SLorenzo Bianconi mvneta_xdp_put_buff(pp, rxq, &xdp_buf, &sinfo, -1); 2449ca0e0146SLorenzo Bianconi 24506c8a8cfdSLorenzo Bianconi if (ps.xdp_redirect) 24510db51da7SLorenzo Bianconi xdp_do_flush_map(); 2452c5aff182SThomas Petazzoni 2453320d5441SLorenzo Bianconi if (ps.rx_packets) 2454320d5441SLorenzo Bianconi mvneta_update_stats(pp, &ps); 2455dc4277ddSwilly tarreau 2456562e2f46SYelena Krivosheev /* return some buffers to hardware queue, one at a time is too slow */ 2457562e2f46SYelena Krivosheev refill = mvneta_rx_refill_queue(pp, rxq); 2458c5aff182SThomas Petazzoni 2459562e2f46SYelena Krivosheev /* Update rxq management counters */ 2460562e2f46SYelena Krivosheev mvneta_rxq_desc_num_update(pp, rxq, rx_proc, refill); 2461562e2f46SYelena Krivosheev 2462320d5441SLorenzo Bianconi return ps.rx_packets; 2463c5aff182SThomas Petazzoni } 2464c5aff182SThomas Petazzoni 2465dc35a10fSMarcin Wojtas /* Main rx processing when using hardware buffer management */ 24667a86f05fSAndrew Lunn static int mvneta_rx_hwbm(struct napi_struct *napi, 24677a86f05fSAndrew Lunn struct mvneta_port *pp, int rx_todo, 2468dc35a10fSMarcin Wojtas struct mvneta_rx_queue *rxq) 2469dc35a10fSMarcin Wojtas { 2470dc35a10fSMarcin Wojtas struct net_device *dev = pp->dev; 2471dc35a10fSMarcin Wojtas int rx_done; 2472dc35a10fSMarcin Wojtas u32 rcvd_pkts = 0; 2473dc35a10fSMarcin Wojtas u32 rcvd_bytes = 0; 2474dc35a10fSMarcin Wojtas 2475dc35a10fSMarcin Wojtas /* Get number of received packets */ 2476dc35a10fSMarcin Wojtas rx_done = mvneta_rxq_busy_desc_num_get(pp, rxq); 2477dc35a10fSMarcin Wojtas 2478dc35a10fSMarcin Wojtas if (rx_todo > rx_done) 2479dc35a10fSMarcin Wojtas rx_todo = rx_done; 2480dc35a10fSMarcin Wojtas 2481dc35a10fSMarcin Wojtas rx_done = 0; 2482dc35a10fSMarcin Wojtas 2483dc35a10fSMarcin Wojtas /* Fairness NAPI loop */ 2484dc35a10fSMarcin Wojtas while (rx_done < rx_todo) { 2485dc35a10fSMarcin Wojtas struct mvneta_rx_desc *rx_desc = mvneta_rxq_next_desc_get(rxq); 2486dc35a10fSMarcin Wojtas struct mvneta_bm_pool *bm_pool = NULL; 2487dc35a10fSMarcin Wojtas struct sk_buff *skb; 2488dc35a10fSMarcin Wojtas unsigned char *data; 2489dc35a10fSMarcin Wojtas dma_addr_t phys_addr; 2490dc35a10fSMarcin Wojtas u32 rx_status, frag_size; 2491dc35a10fSMarcin Wojtas int rx_bytes, err; 2492dc35a10fSMarcin Wojtas u8 pool_id; 2493dc35a10fSMarcin Wojtas 2494dc35a10fSMarcin Wojtas rx_done++; 2495dc35a10fSMarcin Wojtas rx_status = rx_desc->status; 2496dc35a10fSMarcin Wojtas rx_bytes = rx_desc->data_size - (ETH_FCS_LEN + MVNETA_MH_SIZE); 2497f88bee1cSGregory CLEMENT data = (u8 *)(uintptr_t)rx_desc->buf_cookie; 2498dc35a10fSMarcin Wojtas phys_addr = rx_desc->buf_phys_addr; 2499dc35a10fSMarcin Wojtas pool_id = MVNETA_RX_GET_BM_POOL_ID(rx_desc); 2500dc35a10fSMarcin Wojtas bm_pool = &pp->bm_priv->bm_pools[pool_id]; 2501dc35a10fSMarcin Wojtas 2502dc35a10fSMarcin Wojtas if (!mvneta_rxq_desc_is_first_last(rx_status) || 2503dc35a10fSMarcin Wojtas (rx_status & MVNETA_RXD_ERR_SUMMARY)) { 2504dc35a10fSMarcin Wojtas err_drop_frame_ret_pool: 2505dc35a10fSMarcin Wojtas /* Return the buffer to the pool */ 2506dc35a10fSMarcin Wojtas mvneta_bm_pool_put_bp(pp->bm_priv, bm_pool, 2507dc35a10fSMarcin Wojtas rx_desc->buf_phys_addr); 2508dc35a10fSMarcin Wojtas err_drop_frame: 2509dc35a10fSMarcin Wojtas mvneta_rx_error(pp, rx_desc); 2510dc35a10fSMarcin Wojtas /* leave the descriptor untouched */ 2511dc35a10fSMarcin Wojtas continue; 2512dc35a10fSMarcin Wojtas } 2513dc35a10fSMarcin Wojtas 2514dc35a10fSMarcin Wojtas if (rx_bytes <= rx_copybreak) { 2515dc35a10fSMarcin Wojtas /* better copy a small frame and not unmap the DMA region */ 2516dc35a10fSMarcin Wojtas skb = netdev_alloc_skb_ip_align(dev, rx_bytes); 2517dc35a10fSMarcin Wojtas if (unlikely(!skb)) 2518dc35a10fSMarcin Wojtas goto err_drop_frame_ret_pool; 2519dc35a10fSMarcin Wojtas 2520a8fef9baSRussell King dma_sync_single_range_for_cpu(&pp->bm_priv->pdev->dev, 2521dc35a10fSMarcin Wojtas rx_desc->buf_phys_addr, 2522dc35a10fSMarcin Wojtas MVNETA_MH_SIZE + NET_SKB_PAD, 2523dc35a10fSMarcin Wojtas rx_bytes, 2524dc35a10fSMarcin Wojtas DMA_FROM_DEVICE); 252559ae1d12SJohannes Berg skb_put_data(skb, data + MVNETA_MH_SIZE + NET_SKB_PAD, 2526dc35a10fSMarcin Wojtas rx_bytes); 2527dc35a10fSMarcin Wojtas 2528dc35a10fSMarcin Wojtas skb->protocol = eth_type_trans(skb, dev); 2529aff0824dSLorenzo Bianconi skb->ip_summed = mvneta_rx_csum(pp, rx_status); 25307a86f05fSAndrew Lunn napi_gro_receive(napi, skb); 2531dc35a10fSMarcin Wojtas 2532dc35a10fSMarcin Wojtas rcvd_pkts++; 2533dc35a10fSMarcin Wojtas rcvd_bytes += rx_bytes; 2534dc35a10fSMarcin Wojtas 2535dc35a10fSMarcin Wojtas /* Return the buffer to the pool */ 2536dc35a10fSMarcin Wojtas mvneta_bm_pool_put_bp(pp->bm_priv, bm_pool, 2537dc35a10fSMarcin Wojtas rx_desc->buf_phys_addr); 2538dc35a10fSMarcin Wojtas 2539dc35a10fSMarcin Wojtas /* leave the descriptor and buffer untouched */ 2540dc35a10fSMarcin Wojtas continue; 2541dc35a10fSMarcin Wojtas } 2542dc35a10fSMarcin Wojtas 2543dc35a10fSMarcin Wojtas /* Refill processing */ 2544baa11ebcSGregory CLEMENT err = hwbm_pool_refill(&bm_pool->hwbm_pool, GFP_ATOMIC); 2545dc35a10fSMarcin Wojtas if (err) { 25469ac41f3cSLorenzo Bianconi struct mvneta_pcpu_stats *stats; 25479ac41f3cSLorenzo Bianconi 2548dc35a10fSMarcin Wojtas netdev_err(dev, "Linux processing - Can't refill\n"); 25499ac41f3cSLorenzo Bianconi 25509ac41f3cSLorenzo Bianconi stats = this_cpu_ptr(pp->stats); 25519ac41f3cSLorenzo Bianconi u64_stats_update_begin(&stats->syncp); 25529ac41f3cSLorenzo Bianconi stats->es.refill_error++; 25539ac41f3cSLorenzo Bianconi u64_stats_update_end(&stats->syncp); 25549ac41f3cSLorenzo Bianconi 2555dc35a10fSMarcin Wojtas goto err_drop_frame_ret_pool; 2556dc35a10fSMarcin Wojtas } 2557dc35a10fSMarcin Wojtas 2558baa11ebcSGregory CLEMENT frag_size = bm_pool->hwbm_pool.frag_size; 2559dc35a10fSMarcin Wojtas 2560dc35a10fSMarcin Wojtas skb = build_skb(data, frag_size > PAGE_SIZE ? 0 : frag_size); 2561dc35a10fSMarcin Wojtas 2562dc35a10fSMarcin Wojtas /* After refill old buffer has to be unmapped regardless 2563dc35a10fSMarcin Wojtas * the skb is successfully built or not. 2564dc35a10fSMarcin Wojtas */ 2565dc35a10fSMarcin Wojtas dma_unmap_single(&pp->bm_priv->pdev->dev, phys_addr, 2566dc35a10fSMarcin Wojtas bm_pool->buf_size, DMA_FROM_DEVICE); 2567dc35a10fSMarcin Wojtas if (!skb) 2568dc35a10fSMarcin Wojtas goto err_drop_frame; 2569dc35a10fSMarcin Wojtas 2570dc35a10fSMarcin Wojtas rcvd_pkts++; 2571dc35a10fSMarcin Wojtas rcvd_bytes += rx_bytes; 2572dc35a10fSMarcin Wojtas 2573dc35a10fSMarcin Wojtas /* Linux processing */ 2574dc35a10fSMarcin Wojtas skb_reserve(skb, MVNETA_MH_SIZE + NET_SKB_PAD); 2575dc35a10fSMarcin Wojtas skb_put(skb, rx_bytes); 2576dc35a10fSMarcin Wojtas 2577dc35a10fSMarcin Wojtas skb->protocol = eth_type_trans(skb, dev); 2578aff0824dSLorenzo Bianconi skb->ip_summed = mvneta_rx_csum(pp, rx_status); 2579dc35a10fSMarcin Wojtas 25807a86f05fSAndrew Lunn napi_gro_receive(napi, skb); 2581dc35a10fSMarcin Wojtas } 2582dc35a10fSMarcin Wojtas 258369de66fcSLorenzo Bianconi if (rcvd_pkts) { 258469de66fcSLorenzo Bianconi struct mvneta_pcpu_stats *stats = this_cpu_ptr(pp->stats); 258569de66fcSLorenzo Bianconi 258669de66fcSLorenzo Bianconi u64_stats_update_begin(&stats->syncp); 2587320d5441SLorenzo Bianconi stats->es.ps.rx_packets += rcvd_pkts; 2588320d5441SLorenzo Bianconi stats->es.ps.rx_bytes += rcvd_bytes; 258969de66fcSLorenzo Bianconi u64_stats_update_end(&stats->syncp); 259069de66fcSLorenzo Bianconi } 2591dc35a10fSMarcin Wojtas 2592dc35a10fSMarcin Wojtas /* Update rxq management counters */ 2593dc35a10fSMarcin Wojtas mvneta_rxq_desc_num_update(pp, rxq, rx_done, rx_done); 2594dc35a10fSMarcin Wojtas 2595dc35a10fSMarcin Wojtas return rx_done; 2596dc35a10fSMarcin Wojtas } 2597dc35a10fSMarcin Wojtas 25982adb719dSEzequiel Garcia static inline void 259920d446f2SYuval Shaia mvneta_tso_put_hdr(struct sk_buff *skb, struct mvneta_tx_queue *txq) 26002adb719dSEzequiel Garcia { 26012adb719dSEzequiel Garcia int hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb); 26029e58c8b4SLorenzo Bianconi struct mvneta_tx_buf *buf = &txq->buf[txq->txq_put_index]; 26039e58c8b4SLorenzo Bianconi struct mvneta_tx_desc *tx_desc; 26042adb719dSEzequiel Garcia 26052adb719dSEzequiel Garcia tx_desc = mvneta_txq_next_desc_get(txq); 26062adb719dSEzequiel Garcia tx_desc->data_size = hdr_len; 260720d446f2SYuval Shaia tx_desc->command = mvneta_skb_tx_csum(skb); 26082adb719dSEzequiel Garcia tx_desc->command |= MVNETA_TXD_F_DESC; 26092adb719dSEzequiel Garcia tx_desc->buf_phys_addr = txq->tso_hdrs_phys + 26102adb719dSEzequiel Garcia txq->txq_put_index * TSO_HEADER_SIZE; 26119e58c8b4SLorenzo Bianconi buf->type = MVNETA_TYPE_SKB; 26129e58c8b4SLorenzo Bianconi buf->skb = NULL; 26139e58c8b4SLorenzo Bianconi 26142adb719dSEzequiel Garcia mvneta_txq_inc_put(txq); 26152adb719dSEzequiel Garcia } 26162adb719dSEzequiel Garcia 26172adb719dSEzequiel Garcia static inline int 26182adb719dSEzequiel Garcia mvneta_tso_put_data(struct net_device *dev, struct mvneta_tx_queue *txq, 26192adb719dSEzequiel Garcia struct sk_buff *skb, char *data, int size, 26202adb719dSEzequiel Garcia bool last_tcp, bool is_last) 26212adb719dSEzequiel Garcia { 26229e58c8b4SLorenzo Bianconi struct mvneta_tx_buf *buf = &txq->buf[txq->txq_put_index]; 26232adb719dSEzequiel Garcia struct mvneta_tx_desc *tx_desc; 26242adb719dSEzequiel Garcia 26252adb719dSEzequiel Garcia tx_desc = mvneta_txq_next_desc_get(txq); 26262adb719dSEzequiel Garcia tx_desc->data_size = size; 26272adb719dSEzequiel Garcia tx_desc->buf_phys_addr = dma_map_single(dev->dev.parent, data, 26282adb719dSEzequiel Garcia size, DMA_TO_DEVICE); 26292adb719dSEzequiel Garcia if (unlikely(dma_mapping_error(dev->dev.parent, 26302adb719dSEzequiel Garcia tx_desc->buf_phys_addr))) { 26312adb719dSEzequiel Garcia mvneta_txq_desc_put(txq); 26322adb719dSEzequiel Garcia return -ENOMEM; 26332adb719dSEzequiel Garcia } 26342adb719dSEzequiel Garcia 26352adb719dSEzequiel Garcia tx_desc->command = 0; 26369e58c8b4SLorenzo Bianconi buf->type = MVNETA_TYPE_SKB; 26379e58c8b4SLorenzo Bianconi buf->skb = NULL; 26382adb719dSEzequiel Garcia 26392adb719dSEzequiel Garcia if (last_tcp) { 26402adb719dSEzequiel Garcia /* last descriptor in the TCP packet */ 26412adb719dSEzequiel Garcia tx_desc->command = MVNETA_TXD_L_DESC; 26422adb719dSEzequiel Garcia 26432adb719dSEzequiel Garcia /* last descriptor in SKB */ 26442adb719dSEzequiel Garcia if (is_last) 26459e58c8b4SLorenzo Bianconi buf->skb = skb; 26462adb719dSEzequiel Garcia } 26472adb719dSEzequiel Garcia mvneta_txq_inc_put(txq); 26482adb719dSEzequiel Garcia return 0; 26492adb719dSEzequiel Garcia } 26502adb719dSEzequiel Garcia 26512adb719dSEzequiel Garcia static int mvneta_tx_tso(struct sk_buff *skb, struct net_device *dev, 26522adb719dSEzequiel Garcia struct mvneta_tx_queue *txq) 26532adb719dSEzequiel Garcia { 2654761b331cSEric Dumazet int hdr_len, total_len, data_left; 26552adb719dSEzequiel Garcia int desc_count = 0; 26562adb719dSEzequiel Garcia struct mvneta_port *pp = netdev_priv(dev); 26572adb719dSEzequiel Garcia struct tso_t tso; 26582adb719dSEzequiel Garcia int i; 26592adb719dSEzequiel Garcia 26602adb719dSEzequiel Garcia /* Count needed descriptors */ 26612adb719dSEzequiel Garcia if ((txq->count + tso_count_descs(skb)) >= txq->size) 26622adb719dSEzequiel Garcia return 0; 26632adb719dSEzequiel Garcia 26642adb719dSEzequiel Garcia if (skb_headlen(skb) < (skb_transport_offset(skb) + tcp_hdrlen(skb))) { 2665fa660684SColin Ian King pr_info("*** Is this even possible?\n"); 26662adb719dSEzequiel Garcia return 0; 26672adb719dSEzequiel Garcia } 26682adb719dSEzequiel Garcia 26692adb719dSEzequiel Garcia /* Initialize the TSO handler, and prepare the first payload */ 2670761b331cSEric Dumazet hdr_len = tso_start(skb, &tso); 26712adb719dSEzequiel Garcia 26722adb719dSEzequiel Garcia total_len = skb->len - hdr_len; 26732adb719dSEzequiel Garcia while (total_len > 0) { 26742adb719dSEzequiel Garcia char *hdr; 26752adb719dSEzequiel Garcia 26762adb719dSEzequiel Garcia data_left = min_t(int, skb_shinfo(skb)->gso_size, total_len); 26772adb719dSEzequiel Garcia total_len -= data_left; 26782adb719dSEzequiel Garcia desc_count++; 26792adb719dSEzequiel Garcia 26802adb719dSEzequiel Garcia /* prepare packet headers: MAC + IP + TCP */ 26812adb719dSEzequiel Garcia hdr = txq->tso_hdrs + txq->txq_put_index * TSO_HEADER_SIZE; 26822adb719dSEzequiel Garcia tso_build_hdr(skb, hdr, &tso, data_left, total_len == 0); 26832adb719dSEzequiel Garcia 268420d446f2SYuval Shaia mvneta_tso_put_hdr(skb, txq); 26852adb719dSEzequiel Garcia 26862adb719dSEzequiel Garcia while (data_left > 0) { 26872adb719dSEzequiel Garcia int size; 26882adb719dSEzequiel Garcia desc_count++; 26892adb719dSEzequiel Garcia 26902adb719dSEzequiel Garcia size = min_t(int, tso.size, data_left); 26912adb719dSEzequiel Garcia 26922adb719dSEzequiel Garcia if (mvneta_tso_put_data(dev, txq, skb, 26932adb719dSEzequiel Garcia tso.data, size, 26942adb719dSEzequiel Garcia size == data_left, 26952adb719dSEzequiel Garcia total_len == 0)) 26962adb719dSEzequiel Garcia goto err_release; 26972adb719dSEzequiel Garcia data_left -= size; 26982adb719dSEzequiel Garcia 26992adb719dSEzequiel Garcia tso_build_data(skb, &tso, size); 27002adb719dSEzequiel Garcia } 27012adb719dSEzequiel Garcia } 27022adb719dSEzequiel Garcia 27032adb719dSEzequiel Garcia return desc_count; 27042adb719dSEzequiel Garcia 27052adb719dSEzequiel Garcia err_release: 27062adb719dSEzequiel Garcia /* Release all used data descriptors; header descriptors must not 27072adb719dSEzequiel Garcia * be DMA-unmapped. 27082adb719dSEzequiel Garcia */ 27092adb719dSEzequiel Garcia for (i = desc_count - 1; i >= 0; i--) { 27102adb719dSEzequiel Garcia struct mvneta_tx_desc *tx_desc = txq->descs + i; 27112e3173a3SEzequiel Garcia if (!IS_TSO_HEADER(txq, tx_desc->buf_phys_addr)) 27122adb719dSEzequiel Garcia dma_unmap_single(pp->dev->dev.parent, 27132adb719dSEzequiel Garcia tx_desc->buf_phys_addr, 27142adb719dSEzequiel Garcia tx_desc->data_size, 27152adb719dSEzequiel Garcia DMA_TO_DEVICE); 27162adb719dSEzequiel Garcia mvneta_txq_desc_put(txq); 27172adb719dSEzequiel Garcia } 27182adb719dSEzequiel Garcia return 0; 27192adb719dSEzequiel Garcia } 27202adb719dSEzequiel Garcia 2721c5aff182SThomas Petazzoni /* Handle tx fragmentation processing */ 2722c5aff182SThomas Petazzoni static int mvneta_tx_frag_process(struct mvneta_port *pp, struct sk_buff *skb, 2723c5aff182SThomas Petazzoni struct mvneta_tx_queue *txq) 2724c5aff182SThomas Petazzoni { 2725c5aff182SThomas Petazzoni struct mvneta_tx_desc *tx_desc; 27263d4ea02fSEzequiel Garcia int i, nr_frags = skb_shinfo(skb)->nr_frags; 2727c5aff182SThomas Petazzoni 27283d4ea02fSEzequiel Garcia for (i = 0; i < nr_frags; i++) { 27299e58c8b4SLorenzo Bianconi struct mvneta_tx_buf *buf = &txq->buf[txq->txq_put_index]; 2730c5aff182SThomas Petazzoni skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 2731d7840976SMatthew Wilcox (Oracle) void *addr = skb_frag_address(frag); 2732c5aff182SThomas Petazzoni 2733c5aff182SThomas Petazzoni tx_desc = mvneta_txq_next_desc_get(txq); 2734d7840976SMatthew Wilcox (Oracle) tx_desc->data_size = skb_frag_size(frag); 2735c5aff182SThomas Petazzoni 2736c5aff182SThomas Petazzoni tx_desc->buf_phys_addr = 2737c5aff182SThomas Petazzoni dma_map_single(pp->dev->dev.parent, addr, 2738c5aff182SThomas Petazzoni tx_desc->data_size, DMA_TO_DEVICE); 2739c5aff182SThomas Petazzoni 2740c5aff182SThomas Petazzoni if (dma_mapping_error(pp->dev->dev.parent, 2741c5aff182SThomas Petazzoni tx_desc->buf_phys_addr)) { 2742c5aff182SThomas Petazzoni mvneta_txq_desc_put(txq); 2743c5aff182SThomas Petazzoni goto error; 2744c5aff182SThomas Petazzoni } 2745c5aff182SThomas Petazzoni 27463d4ea02fSEzequiel Garcia if (i == nr_frags - 1) { 2747c5aff182SThomas Petazzoni /* Last descriptor */ 2748c5aff182SThomas Petazzoni tx_desc->command = MVNETA_TXD_L_DESC | MVNETA_TXD_Z_PAD; 27499e58c8b4SLorenzo Bianconi buf->skb = skb; 2750c5aff182SThomas Petazzoni } else { 2751c5aff182SThomas Petazzoni /* Descriptor in the middle: Not First, Not Last */ 2752c5aff182SThomas Petazzoni tx_desc->command = 0; 27539e58c8b4SLorenzo Bianconi buf->skb = NULL; 2754c5aff182SThomas Petazzoni } 27559e58c8b4SLorenzo Bianconi buf->type = MVNETA_TYPE_SKB; 27563d4ea02fSEzequiel Garcia mvneta_txq_inc_put(txq); 2757c5aff182SThomas Petazzoni } 2758c5aff182SThomas Petazzoni 2759c5aff182SThomas Petazzoni return 0; 2760c5aff182SThomas Petazzoni 2761c5aff182SThomas Petazzoni error: 2762c5aff182SThomas Petazzoni /* Release all descriptors that were used to map fragments of 27636a20c175SThomas Petazzoni * this packet, as well as the corresponding DMA mappings 27646a20c175SThomas Petazzoni */ 2765c5aff182SThomas Petazzoni for (i = i - 1; i >= 0; i--) { 2766c5aff182SThomas Petazzoni tx_desc = txq->descs + i; 2767c5aff182SThomas Petazzoni dma_unmap_single(pp->dev->dev.parent, 2768c5aff182SThomas Petazzoni tx_desc->buf_phys_addr, 2769c5aff182SThomas Petazzoni tx_desc->data_size, 2770c5aff182SThomas Petazzoni DMA_TO_DEVICE); 2771c5aff182SThomas Petazzoni mvneta_txq_desc_put(txq); 2772c5aff182SThomas Petazzoni } 2773c5aff182SThomas Petazzoni 2774c5aff182SThomas Petazzoni return -ENOMEM; 2775c5aff182SThomas Petazzoni } 2776c5aff182SThomas Petazzoni 2777c5aff182SThomas Petazzoni /* Main tx processing */ 2778f03508ceSYueHaibing static netdev_tx_t mvneta_tx(struct sk_buff *skb, struct net_device *dev) 2779c5aff182SThomas Petazzoni { 2780c5aff182SThomas Petazzoni struct mvneta_port *pp = netdev_priv(dev); 2781ee40a116SWilly Tarreau u16 txq_id = skb_get_queue_mapping(skb); 2782ee40a116SWilly Tarreau struct mvneta_tx_queue *txq = &pp->txqs[txq_id]; 27839e58c8b4SLorenzo Bianconi struct mvneta_tx_buf *buf = &txq->buf[txq->txq_put_index]; 2784c5aff182SThomas Petazzoni struct mvneta_tx_desc *tx_desc; 27855f478b41SEric Dumazet int len = skb->len; 2786c5aff182SThomas Petazzoni int frags = 0; 2787c5aff182SThomas Petazzoni u32 tx_cmd; 2788c5aff182SThomas Petazzoni 2789c5aff182SThomas Petazzoni if (!netif_running(dev)) 2790c5aff182SThomas Petazzoni goto out; 2791c5aff182SThomas Petazzoni 27922adb719dSEzequiel Garcia if (skb_is_gso(skb)) { 27932adb719dSEzequiel Garcia frags = mvneta_tx_tso(skb, dev, txq); 27942adb719dSEzequiel Garcia goto out; 27952adb719dSEzequiel Garcia } 27962adb719dSEzequiel Garcia 2797c5aff182SThomas Petazzoni frags = skb_shinfo(skb)->nr_frags + 1; 2798c5aff182SThomas Petazzoni 2799c5aff182SThomas Petazzoni /* Get a descriptor for the first part of the packet */ 2800c5aff182SThomas Petazzoni tx_desc = mvneta_txq_next_desc_get(txq); 2801c5aff182SThomas Petazzoni 280220d446f2SYuval Shaia tx_cmd = mvneta_skb_tx_csum(skb); 2803c5aff182SThomas Petazzoni 2804c5aff182SThomas Petazzoni tx_desc->data_size = skb_headlen(skb); 2805c5aff182SThomas Petazzoni 2806c5aff182SThomas Petazzoni tx_desc->buf_phys_addr = dma_map_single(dev->dev.parent, skb->data, 2807c5aff182SThomas Petazzoni tx_desc->data_size, 2808c5aff182SThomas Petazzoni DMA_TO_DEVICE); 2809c5aff182SThomas Petazzoni if (unlikely(dma_mapping_error(dev->dev.parent, 2810c5aff182SThomas Petazzoni tx_desc->buf_phys_addr))) { 2811c5aff182SThomas Petazzoni mvneta_txq_desc_put(txq); 2812c5aff182SThomas Petazzoni frags = 0; 2813c5aff182SThomas Petazzoni goto out; 2814c5aff182SThomas Petazzoni } 2815c5aff182SThomas Petazzoni 28169e58c8b4SLorenzo Bianconi buf->type = MVNETA_TYPE_SKB; 2817c5aff182SThomas Petazzoni if (frags == 1) { 2818c5aff182SThomas Petazzoni /* First and Last descriptor */ 2819c5aff182SThomas Petazzoni tx_cmd |= MVNETA_TXD_FLZ_DESC; 2820c5aff182SThomas Petazzoni tx_desc->command = tx_cmd; 28219e58c8b4SLorenzo Bianconi buf->skb = skb; 2822c5aff182SThomas Petazzoni mvneta_txq_inc_put(txq); 2823c5aff182SThomas Petazzoni } else { 2824c5aff182SThomas Petazzoni /* First but not Last */ 2825c5aff182SThomas Petazzoni tx_cmd |= MVNETA_TXD_F_DESC; 28269e58c8b4SLorenzo Bianconi buf->skb = NULL; 2827c5aff182SThomas Petazzoni mvneta_txq_inc_put(txq); 2828c5aff182SThomas Petazzoni tx_desc->command = tx_cmd; 2829c5aff182SThomas Petazzoni /* Continue with other skb fragments */ 2830c5aff182SThomas Petazzoni if (mvneta_tx_frag_process(pp, skb, txq)) { 2831c5aff182SThomas Petazzoni dma_unmap_single(dev->dev.parent, 2832c5aff182SThomas Petazzoni tx_desc->buf_phys_addr, 2833c5aff182SThomas Petazzoni tx_desc->data_size, 2834c5aff182SThomas Petazzoni DMA_TO_DEVICE); 2835c5aff182SThomas Petazzoni mvneta_txq_desc_put(txq); 2836c5aff182SThomas Petazzoni frags = 0; 2837c5aff182SThomas Petazzoni goto out; 2838c5aff182SThomas Petazzoni } 2839c5aff182SThomas Petazzoni } 2840c5aff182SThomas Petazzoni 2841e19d2ddaSEzequiel Garcia out: 2842e19d2ddaSEzequiel Garcia if (frags > 0) { 2843e19d2ddaSEzequiel Garcia struct netdev_queue *nq = netdev_get_tx_queue(dev, txq_id); 284469de66fcSLorenzo Bianconi struct mvneta_pcpu_stats *stats = this_cpu_ptr(pp->stats); 2845e19d2ddaSEzequiel Garcia 2846a29b6235SMarcin Wojtas netdev_tx_sent_queue(nq, len); 2847a29b6235SMarcin Wojtas 2848c5aff182SThomas Petazzoni txq->count += frags; 28498eef5f97SEzequiel Garcia if (txq->count >= txq->tx_stop_threshold) 2850c5aff182SThomas Petazzoni netif_tx_stop_queue(nq); 2851c5aff182SThomas Petazzoni 28526b16f9eeSFlorian Westphal if (!netdev_xmit_more() || netif_xmit_stopped(nq) || 28532a90f7e1SSimon Guinot txq->pending + frags > MVNETA_TXQ_DEC_SENT_MASK) 28542a90f7e1SSimon Guinot mvneta_txq_pend_desc_add(pp, txq, frags); 28552a90f7e1SSimon Guinot else 28562a90f7e1SSimon Guinot txq->pending += frags; 28572a90f7e1SSimon Guinot 285869de66fcSLorenzo Bianconi u64_stats_update_begin(&stats->syncp); 2859320d5441SLorenzo Bianconi stats->es.ps.tx_bytes += len; 2860320d5441SLorenzo Bianconi stats->es.ps.tx_packets++; 286169de66fcSLorenzo Bianconi u64_stats_update_end(&stats->syncp); 2862c5aff182SThomas Petazzoni } else { 2863c5aff182SThomas Petazzoni dev->stats.tx_dropped++; 2864c5aff182SThomas Petazzoni dev_kfree_skb_any(skb); 2865c5aff182SThomas Petazzoni } 2866c5aff182SThomas Petazzoni 2867c5aff182SThomas Petazzoni return NETDEV_TX_OK; 2868c5aff182SThomas Petazzoni } 2869c5aff182SThomas Petazzoni 2870c5aff182SThomas Petazzoni 2871c5aff182SThomas Petazzoni /* Free tx resources, when resetting a port */ 2872c5aff182SThomas Petazzoni static void mvneta_txq_done_force(struct mvneta_port *pp, 2873c5aff182SThomas Petazzoni struct mvneta_tx_queue *txq) 2874c5aff182SThomas Petazzoni 2875c5aff182SThomas Petazzoni { 2876a29b6235SMarcin Wojtas struct netdev_queue *nq = netdev_get_tx_queue(pp->dev, txq->id); 2877c5aff182SThomas Petazzoni int tx_done = txq->count; 2878c5aff182SThomas Petazzoni 2879632bb64fSLorenzo Bianconi mvneta_txq_bufs_free(pp, txq, tx_done, nq, false); 2880c5aff182SThomas Petazzoni 2881c5aff182SThomas Petazzoni /* reset txq */ 2882c5aff182SThomas Petazzoni txq->count = 0; 2883c5aff182SThomas Petazzoni txq->txq_put_index = 0; 2884c5aff182SThomas Petazzoni txq->txq_get_index = 0; 2885c5aff182SThomas Petazzoni } 2886c5aff182SThomas Petazzoni 28876c498974Swilly tarreau /* Handle tx done - called in softirq context. The <cause_tx_done> argument 28886c498974Swilly tarreau * must be a valid cause according to MVNETA_TXQ_INTR_MASK_ALL. 28896c498974Swilly tarreau */ 28900713a86aSArnaud Ebalard static void mvneta_tx_done_gbe(struct mvneta_port *pp, u32 cause_tx_done) 2891c5aff182SThomas Petazzoni { 2892c5aff182SThomas Petazzoni struct mvneta_tx_queue *txq; 2893c5aff182SThomas Petazzoni struct netdev_queue *nq; 2894bd9f1ee3SJisheng Zhang int cpu = smp_processor_id(); 2895c5aff182SThomas Petazzoni 28966c498974Swilly tarreau while (cause_tx_done) { 2897c5aff182SThomas Petazzoni txq = mvneta_tx_done_policy(pp, cause_tx_done); 2898c5aff182SThomas Petazzoni 2899c5aff182SThomas Petazzoni nq = netdev_get_tx_queue(pp->dev, txq->id); 2900bd9f1ee3SJisheng Zhang __netif_tx_lock(nq, cpu); 2901c5aff182SThomas Petazzoni 29020713a86aSArnaud Ebalard if (txq->count) 29030713a86aSArnaud Ebalard mvneta_txq_done(pp, txq); 2904c5aff182SThomas Petazzoni 2905c5aff182SThomas Petazzoni __netif_tx_unlock(nq); 2906c5aff182SThomas Petazzoni cause_tx_done &= ~((1 << txq->id)); 2907c5aff182SThomas Petazzoni } 2908c5aff182SThomas Petazzoni } 2909c5aff182SThomas Petazzoni 29106a20c175SThomas Petazzoni /* Compute crc8 of the specified address, using a unique algorithm , 2911c5aff182SThomas Petazzoni * according to hw spec, different than generic crc8 algorithm 2912c5aff182SThomas Petazzoni */ 2913c5aff182SThomas Petazzoni static int mvneta_addr_crc(unsigned char *addr) 2914c5aff182SThomas Petazzoni { 2915c5aff182SThomas Petazzoni int crc = 0; 2916c5aff182SThomas Petazzoni int i; 2917c5aff182SThomas Petazzoni 2918c5aff182SThomas Petazzoni for (i = 0; i < ETH_ALEN; i++) { 2919c5aff182SThomas Petazzoni int j; 2920c5aff182SThomas Petazzoni 2921c5aff182SThomas Petazzoni crc = (crc ^ addr[i]) << 8; 2922c5aff182SThomas Petazzoni for (j = 7; j >= 0; j--) { 2923c5aff182SThomas Petazzoni if (crc & (0x100 << j)) 2924c5aff182SThomas Petazzoni crc ^= 0x107 << j; 2925c5aff182SThomas Petazzoni } 2926c5aff182SThomas Petazzoni } 2927c5aff182SThomas Petazzoni 2928c5aff182SThomas Petazzoni return crc; 2929c5aff182SThomas Petazzoni } 2930c5aff182SThomas Petazzoni 2931c5aff182SThomas Petazzoni /* This method controls the net device special MAC multicast support. 2932c5aff182SThomas Petazzoni * The Special Multicast Table for MAC addresses supports MAC of the form 2933c5aff182SThomas Petazzoni * 0x01-00-5E-00-00-XX (where XX is between 0x00 and 0xFF). 2934c5aff182SThomas Petazzoni * The MAC DA[7:0] bits are used as a pointer to the Special Multicast 2935c5aff182SThomas Petazzoni * Table entries in the DA-Filter table. This method set the Special 2936c5aff182SThomas Petazzoni * Multicast Table appropriate entry. 2937c5aff182SThomas Petazzoni */ 2938c5aff182SThomas Petazzoni static void mvneta_set_special_mcast_addr(struct mvneta_port *pp, 2939c5aff182SThomas Petazzoni unsigned char last_byte, 2940c5aff182SThomas Petazzoni int queue) 2941c5aff182SThomas Petazzoni { 2942c5aff182SThomas Petazzoni unsigned int smc_table_reg; 2943c5aff182SThomas Petazzoni unsigned int tbl_offset; 2944c5aff182SThomas Petazzoni unsigned int reg_offset; 2945c5aff182SThomas Petazzoni 2946c5aff182SThomas Petazzoni /* Register offset from SMC table base */ 2947c5aff182SThomas Petazzoni tbl_offset = (last_byte / 4); 2948c5aff182SThomas Petazzoni /* Entry offset within the above reg */ 2949c5aff182SThomas Petazzoni reg_offset = last_byte % 4; 2950c5aff182SThomas Petazzoni 2951c5aff182SThomas Petazzoni smc_table_reg = mvreg_read(pp, (MVNETA_DA_FILT_SPEC_MCAST 2952c5aff182SThomas Petazzoni + tbl_offset * 4)); 2953c5aff182SThomas Petazzoni 2954c5aff182SThomas Petazzoni if (queue == -1) 2955c5aff182SThomas Petazzoni smc_table_reg &= ~(0xff << (8 * reg_offset)); 2956c5aff182SThomas Petazzoni else { 2957c5aff182SThomas Petazzoni smc_table_reg &= ~(0xff << (8 * reg_offset)); 2958c5aff182SThomas Petazzoni smc_table_reg |= ((0x01 | (queue << 1)) << (8 * reg_offset)); 2959c5aff182SThomas Petazzoni } 2960c5aff182SThomas Petazzoni 2961c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_DA_FILT_SPEC_MCAST + tbl_offset * 4, 2962c5aff182SThomas Petazzoni smc_table_reg); 2963c5aff182SThomas Petazzoni } 2964c5aff182SThomas Petazzoni 2965c5aff182SThomas Petazzoni /* This method controls the network device Other MAC multicast support. 2966c5aff182SThomas Petazzoni * The Other Multicast Table is used for multicast of another type. 2967c5aff182SThomas Petazzoni * A CRC-8 is used as an index to the Other Multicast Table entries 2968c5aff182SThomas Petazzoni * in the DA-Filter table. 2969c5aff182SThomas Petazzoni * The method gets the CRC-8 value from the calling routine and 2970c5aff182SThomas Petazzoni * sets the Other Multicast Table appropriate entry according to the 2971c5aff182SThomas Petazzoni * specified CRC-8 . 2972c5aff182SThomas Petazzoni */ 2973c5aff182SThomas Petazzoni static void mvneta_set_other_mcast_addr(struct mvneta_port *pp, 2974c5aff182SThomas Petazzoni unsigned char crc8, 2975c5aff182SThomas Petazzoni int queue) 2976c5aff182SThomas Petazzoni { 2977c5aff182SThomas Petazzoni unsigned int omc_table_reg; 2978c5aff182SThomas Petazzoni unsigned int tbl_offset; 2979c5aff182SThomas Petazzoni unsigned int reg_offset; 2980c5aff182SThomas Petazzoni 2981c5aff182SThomas Petazzoni tbl_offset = (crc8 / 4) * 4; /* Register offset from OMC table base */ 2982c5aff182SThomas Petazzoni reg_offset = crc8 % 4; /* Entry offset within the above reg */ 2983c5aff182SThomas Petazzoni 2984c5aff182SThomas Petazzoni omc_table_reg = mvreg_read(pp, MVNETA_DA_FILT_OTH_MCAST + tbl_offset); 2985c5aff182SThomas Petazzoni 2986c5aff182SThomas Petazzoni if (queue == -1) { 2987c5aff182SThomas Petazzoni /* Clear accepts frame bit at specified Other DA table entry */ 2988c5aff182SThomas Petazzoni omc_table_reg &= ~(0xff << (8 * reg_offset)); 2989c5aff182SThomas Petazzoni } else { 2990c5aff182SThomas Petazzoni omc_table_reg &= ~(0xff << (8 * reg_offset)); 2991c5aff182SThomas Petazzoni omc_table_reg |= ((0x01 | (queue << 1)) << (8 * reg_offset)); 2992c5aff182SThomas Petazzoni } 2993c5aff182SThomas Petazzoni 2994c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_DA_FILT_OTH_MCAST + tbl_offset, omc_table_reg); 2995c5aff182SThomas Petazzoni } 2996c5aff182SThomas Petazzoni 2997c5aff182SThomas Petazzoni /* The network device supports multicast using two tables: 2998c5aff182SThomas Petazzoni * 1) Special Multicast Table for MAC addresses of the form 2999c5aff182SThomas Petazzoni * 0x01-00-5E-00-00-XX (where XX is between 0x00 and 0xFF). 3000c5aff182SThomas Petazzoni * The MAC DA[7:0] bits are used as a pointer to the Special Multicast 3001c5aff182SThomas Petazzoni * Table entries in the DA-Filter table. 3002c5aff182SThomas Petazzoni * 2) Other Multicast Table for multicast of another type. A CRC-8 value 3003c5aff182SThomas Petazzoni * is used as an index to the Other Multicast Table entries in the 3004c5aff182SThomas Petazzoni * DA-Filter table. 3005c5aff182SThomas Petazzoni */ 3006c5aff182SThomas Petazzoni static int mvneta_mcast_addr_set(struct mvneta_port *pp, unsigned char *p_addr, 3007c5aff182SThomas Petazzoni int queue) 3008c5aff182SThomas Petazzoni { 3009c5aff182SThomas Petazzoni unsigned char crc_result = 0; 3010c5aff182SThomas Petazzoni 3011c5aff182SThomas Petazzoni if (memcmp(p_addr, "\x01\x00\x5e\x00\x00", 5) == 0) { 3012c5aff182SThomas Petazzoni mvneta_set_special_mcast_addr(pp, p_addr[5], queue); 3013c5aff182SThomas Petazzoni return 0; 3014c5aff182SThomas Petazzoni } 3015c5aff182SThomas Petazzoni 3016c5aff182SThomas Petazzoni crc_result = mvneta_addr_crc(p_addr); 3017c5aff182SThomas Petazzoni if (queue == -1) { 3018c5aff182SThomas Petazzoni if (pp->mcast_count[crc_result] == 0) { 3019c5aff182SThomas Petazzoni netdev_info(pp->dev, "No valid Mcast for crc8=0x%02x\n", 3020c5aff182SThomas Petazzoni crc_result); 3021c5aff182SThomas Petazzoni return -EINVAL; 3022c5aff182SThomas Petazzoni } 3023c5aff182SThomas Petazzoni 3024c5aff182SThomas Petazzoni pp->mcast_count[crc_result]--; 3025c5aff182SThomas Petazzoni if (pp->mcast_count[crc_result] != 0) { 3026c5aff182SThomas Petazzoni netdev_info(pp->dev, 3027c5aff182SThomas Petazzoni "After delete there are %d valid Mcast for crc8=0x%02x\n", 3028c5aff182SThomas Petazzoni pp->mcast_count[crc_result], crc_result); 3029c5aff182SThomas Petazzoni return -EINVAL; 3030c5aff182SThomas Petazzoni } 3031c5aff182SThomas Petazzoni } else 3032c5aff182SThomas Petazzoni pp->mcast_count[crc_result]++; 3033c5aff182SThomas Petazzoni 3034c5aff182SThomas Petazzoni mvneta_set_other_mcast_addr(pp, crc_result, queue); 3035c5aff182SThomas Petazzoni 3036c5aff182SThomas Petazzoni return 0; 3037c5aff182SThomas Petazzoni } 3038c5aff182SThomas Petazzoni 3039c5aff182SThomas Petazzoni /* Configure Fitering mode of Ethernet port */ 3040c5aff182SThomas Petazzoni static void mvneta_rx_unicast_promisc_set(struct mvneta_port *pp, 3041c5aff182SThomas Petazzoni int is_promisc) 3042c5aff182SThomas Petazzoni { 3043c5aff182SThomas Petazzoni u32 port_cfg_reg, val; 3044c5aff182SThomas Petazzoni 3045c5aff182SThomas Petazzoni port_cfg_reg = mvreg_read(pp, MVNETA_PORT_CONFIG); 3046c5aff182SThomas Petazzoni 3047c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_TYPE_PRIO); 3048c5aff182SThomas Petazzoni 3049c5aff182SThomas Petazzoni /* Set / Clear UPM bit in port configuration register */ 3050c5aff182SThomas Petazzoni if (is_promisc) { 3051c5aff182SThomas Petazzoni /* Accept all Unicast addresses */ 3052c5aff182SThomas Petazzoni port_cfg_reg |= MVNETA_UNI_PROMISC_MODE; 3053c5aff182SThomas Petazzoni val |= MVNETA_FORCE_UNI; 3054c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_MAC_ADDR_LOW, 0xffff); 3055c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_MAC_ADDR_HIGH, 0xffffffff); 3056c5aff182SThomas Petazzoni } else { 3057c5aff182SThomas Petazzoni /* Reject all Unicast addresses */ 3058c5aff182SThomas Petazzoni port_cfg_reg &= ~MVNETA_UNI_PROMISC_MODE; 3059c5aff182SThomas Petazzoni val &= ~MVNETA_FORCE_UNI; 3060c5aff182SThomas Petazzoni } 3061c5aff182SThomas Petazzoni 3062c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_PORT_CONFIG, port_cfg_reg); 3063c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_TYPE_PRIO, val); 3064c5aff182SThomas Petazzoni } 3065c5aff182SThomas Petazzoni 3066c5aff182SThomas Petazzoni /* register unicast and multicast addresses */ 3067c5aff182SThomas Petazzoni static void mvneta_set_rx_mode(struct net_device *dev) 3068c5aff182SThomas Petazzoni { 3069c5aff182SThomas Petazzoni struct mvneta_port *pp = netdev_priv(dev); 3070c5aff182SThomas Petazzoni struct netdev_hw_addr *ha; 3071c5aff182SThomas Petazzoni 3072c5aff182SThomas Petazzoni if (dev->flags & IFF_PROMISC) { 3073c5aff182SThomas Petazzoni /* Accept all: Multicast + Unicast */ 3074c5aff182SThomas Petazzoni mvneta_rx_unicast_promisc_set(pp, 1); 307590b74c01SGregory CLEMENT mvneta_set_ucast_table(pp, pp->rxq_def); 307690b74c01SGregory CLEMENT mvneta_set_special_mcast_table(pp, pp->rxq_def); 307790b74c01SGregory CLEMENT mvneta_set_other_mcast_table(pp, pp->rxq_def); 3078c5aff182SThomas Petazzoni } else { 3079c5aff182SThomas Petazzoni /* Accept single Unicast */ 3080c5aff182SThomas Petazzoni mvneta_rx_unicast_promisc_set(pp, 0); 3081c5aff182SThomas Petazzoni mvneta_set_ucast_table(pp, -1); 308290b74c01SGregory CLEMENT mvneta_mac_addr_set(pp, dev->dev_addr, pp->rxq_def); 3083c5aff182SThomas Petazzoni 3084c5aff182SThomas Petazzoni if (dev->flags & IFF_ALLMULTI) { 3085c5aff182SThomas Petazzoni /* Accept all multicast */ 308690b74c01SGregory CLEMENT mvneta_set_special_mcast_table(pp, pp->rxq_def); 308790b74c01SGregory CLEMENT mvneta_set_other_mcast_table(pp, pp->rxq_def); 3088c5aff182SThomas Petazzoni } else { 3089c5aff182SThomas Petazzoni /* Accept only initialized multicast */ 3090c5aff182SThomas Petazzoni mvneta_set_special_mcast_table(pp, -1); 3091c5aff182SThomas Petazzoni mvneta_set_other_mcast_table(pp, -1); 3092c5aff182SThomas Petazzoni 3093c5aff182SThomas Petazzoni if (!netdev_mc_empty(dev)) { 3094c5aff182SThomas Petazzoni netdev_for_each_mc_addr(ha, dev) { 3095c5aff182SThomas Petazzoni mvneta_mcast_addr_set(pp, ha->addr, 309690b74c01SGregory CLEMENT pp->rxq_def); 3097c5aff182SThomas Petazzoni } 3098c5aff182SThomas Petazzoni } 3099c5aff182SThomas Petazzoni } 3100c5aff182SThomas Petazzoni } 3101c5aff182SThomas Petazzoni } 3102c5aff182SThomas Petazzoni 3103c5aff182SThomas Petazzoni /* Interrupt handling - the callback for request_irq() */ 3104c5aff182SThomas Petazzoni static irqreturn_t mvneta_isr(int irq, void *dev_id) 3105c5aff182SThomas Petazzoni { 31062636ac3cSMarcin Wojtas struct mvneta_port *pp = (struct mvneta_port *)dev_id; 31072636ac3cSMarcin Wojtas 31082636ac3cSMarcin Wojtas mvreg_write(pp, MVNETA_INTR_NEW_MASK, 0); 31092636ac3cSMarcin Wojtas napi_schedule(&pp->napi); 31102636ac3cSMarcin Wojtas 31112636ac3cSMarcin Wojtas return IRQ_HANDLED; 31122636ac3cSMarcin Wojtas } 31132636ac3cSMarcin Wojtas 31142636ac3cSMarcin Wojtas /* Interrupt handling - the callback for request_percpu_irq() */ 31152636ac3cSMarcin Wojtas static irqreturn_t mvneta_percpu_isr(int irq, void *dev_id) 31162636ac3cSMarcin Wojtas { 311712bb03b4SMaxime Ripard struct mvneta_pcpu_port *port = (struct mvneta_pcpu_port *)dev_id; 3118c5aff182SThomas Petazzoni 311912bb03b4SMaxime Ripard disable_percpu_irq(port->pp->dev->irq); 312012bb03b4SMaxime Ripard napi_schedule(&port->napi); 3121c5aff182SThomas Petazzoni 3122c5aff182SThomas Petazzoni return IRQ_HANDLED; 3123c5aff182SThomas Petazzoni } 3124c5aff182SThomas Petazzoni 3125503f9aa9SRussell King static void mvneta_link_change(struct mvneta_port *pp) 3126898b2970SStas Sergeev { 3127898b2970SStas Sergeev u32 gmac_stat = mvreg_read(pp, MVNETA_GMAC_STATUS); 3128898b2970SStas Sergeev 3129503f9aa9SRussell King phylink_mac_change(pp->phylink, !!(gmac_stat & MVNETA_GMAC_LINK_UP)); 3130898b2970SStas Sergeev } 3131898b2970SStas Sergeev 3132c5aff182SThomas Petazzoni /* NAPI handler 3133c5aff182SThomas Petazzoni * Bits 0 - 7 of the causeRxTx register indicate that are transmitted 3134c5aff182SThomas Petazzoni * packets on the corresponding TXQ (Bit 0 is for TX queue 1). 3135c5aff182SThomas Petazzoni * Bits 8 -15 of the cause Rx Tx register indicate that are received 3136c5aff182SThomas Petazzoni * packets on the corresponding RXQ (Bit 8 is for RX queue 0). 3137c5aff182SThomas Petazzoni * Each CPU has its own causeRxTx register 3138c5aff182SThomas Petazzoni */ 3139c5aff182SThomas Petazzoni static int mvneta_poll(struct napi_struct *napi, int budget) 3140c5aff182SThomas Petazzoni { 3141c5aff182SThomas Petazzoni int rx_done = 0; 3142c5aff182SThomas Petazzoni u32 cause_rx_tx; 31432dcf75e2SGregory CLEMENT int rx_queue; 3144c5aff182SThomas Petazzoni struct mvneta_port *pp = netdev_priv(napi->dev); 314512bb03b4SMaxime Ripard struct mvneta_pcpu_port *port = this_cpu_ptr(pp->ports); 3146c5aff182SThomas Petazzoni 3147c5aff182SThomas Petazzoni if (!netif_running(pp->dev)) { 31482636ac3cSMarcin Wojtas napi_complete(napi); 3149c5aff182SThomas Petazzoni return rx_done; 3150c5aff182SThomas Petazzoni } 3151c5aff182SThomas Petazzoni 3152c5aff182SThomas Petazzoni /* Read cause register */ 3153898b2970SStas Sergeev cause_rx_tx = mvreg_read(pp, MVNETA_INTR_NEW_CAUSE); 3154898b2970SStas Sergeev if (cause_rx_tx & MVNETA_MISCINTR_INTR_MASK) { 3155898b2970SStas Sergeev u32 cause_misc = mvreg_read(pp, MVNETA_INTR_MISC_CAUSE); 3156898b2970SStas Sergeev 3157898b2970SStas Sergeev mvreg_write(pp, MVNETA_INTR_MISC_CAUSE, 0); 3158503f9aa9SRussell King 3159503f9aa9SRussell King if (cause_misc & (MVNETA_CAUSE_PHY_STATUS_CHANGE | 3160856b2cc5SRussell King MVNETA_CAUSE_LINK_CHANGE)) 3161503f9aa9SRussell King mvneta_link_change(pp); 3162898b2970SStas Sergeev } 316371f6d1b3Swilly tarreau 316471f6d1b3Swilly tarreau /* Release Tx descriptors */ 316571f6d1b3Swilly tarreau if (cause_rx_tx & MVNETA_TX_INTR_MASK_ALL) { 31660713a86aSArnaud Ebalard mvneta_tx_done_gbe(pp, (cause_rx_tx & MVNETA_TX_INTR_MASK_ALL)); 316771f6d1b3Swilly tarreau cause_rx_tx &= ~MVNETA_TX_INTR_MASK_ALL; 316871f6d1b3Swilly tarreau } 3169c5aff182SThomas Petazzoni 31706a20c175SThomas Petazzoni /* For the case where the last mvneta_poll did not process all 3171c5aff182SThomas Petazzoni * RX packets 3172c5aff182SThomas Petazzoni */ 31732636ac3cSMarcin Wojtas cause_rx_tx |= pp->neta_armada3700 ? pp->cause_rx_tx : 31742636ac3cSMarcin Wojtas port->cause_rx_tx; 31752dcf75e2SGregory CLEMENT 3176065fd83eSJisheng Zhang rx_queue = fls(((cause_rx_tx >> 8) & 0xff)); 31772dcf75e2SGregory CLEMENT if (rx_queue) { 31782dcf75e2SGregory CLEMENT rx_queue = rx_queue - 1; 3179dc35a10fSMarcin Wojtas if (pp->bm_priv) 31807a86f05fSAndrew Lunn rx_done = mvneta_rx_hwbm(napi, pp, budget, 31817a86f05fSAndrew Lunn &pp->rxqs[rx_queue]); 3182dc35a10fSMarcin Wojtas else 31837a86f05fSAndrew Lunn rx_done = mvneta_rx_swbm(napi, pp, budget, 31847a86f05fSAndrew Lunn &pp->rxqs[rx_queue]); 31852dcf75e2SGregory CLEMENT } 31862dcf75e2SGregory CLEMENT 31876ad20165SEric Dumazet if (rx_done < budget) { 3188c5aff182SThomas Petazzoni cause_rx_tx = 0; 31896ad20165SEric Dumazet napi_complete_done(napi, rx_done); 31902636ac3cSMarcin Wojtas 31912636ac3cSMarcin Wojtas if (pp->neta_armada3700) { 31922636ac3cSMarcin Wojtas unsigned long flags; 31932636ac3cSMarcin Wojtas 31942636ac3cSMarcin Wojtas local_irq_save(flags); 31952636ac3cSMarcin Wojtas mvreg_write(pp, MVNETA_INTR_NEW_MASK, 31962636ac3cSMarcin Wojtas MVNETA_RX_INTR_MASK(rxq_number) | 31972636ac3cSMarcin Wojtas MVNETA_TX_INTR_MASK(txq_number) | 31982636ac3cSMarcin Wojtas MVNETA_MISCINTR_INTR_MASK); 31992636ac3cSMarcin Wojtas local_irq_restore(flags); 32002636ac3cSMarcin Wojtas } else { 320112bb03b4SMaxime Ripard enable_percpu_irq(pp->dev->irq, 0); 3202c5aff182SThomas Petazzoni } 32032636ac3cSMarcin Wojtas } 3204c5aff182SThomas Petazzoni 32052636ac3cSMarcin Wojtas if (pp->neta_armada3700) 32062636ac3cSMarcin Wojtas pp->cause_rx_tx = cause_rx_tx; 32072636ac3cSMarcin Wojtas else 320812bb03b4SMaxime Ripard port->cause_rx_tx = cause_rx_tx; 32092636ac3cSMarcin Wojtas 3210c5aff182SThomas Petazzoni return rx_done; 3211c5aff182SThomas Petazzoni } 3212c5aff182SThomas Petazzoni 3213568a3fa2SLorenzo Bianconi static int mvneta_create_page_pool(struct mvneta_port *pp, 3214568a3fa2SLorenzo Bianconi struct mvneta_rx_queue *rxq, int size) 3215568a3fa2SLorenzo Bianconi { 32160db51da7SLorenzo Bianconi struct bpf_prog *xdp_prog = READ_ONCE(pp->xdp_prog); 3217568a3fa2SLorenzo Bianconi struct page_pool_params pp_params = { 3218568a3fa2SLorenzo Bianconi .order = 0, 321907e13edbSLorenzo Bianconi .flags = PP_FLAG_DMA_MAP | PP_FLAG_DMA_SYNC_DEV, 3220568a3fa2SLorenzo Bianconi .pool_size = size, 32211657adccSLorenzo Bianconi .nid = NUMA_NO_NODE, 3222568a3fa2SLorenzo Bianconi .dev = pp->dev->dev.parent, 32230db51da7SLorenzo Bianconi .dma_dir = xdp_prog ? DMA_BIDIRECTIONAL : DMA_FROM_DEVICE, 322407e13edbSLorenzo Bianconi .offset = pp->rx_offset_correction, 322507e13edbSLorenzo Bianconi .max_len = MVNETA_MAX_RX_BUF_SIZE, 3226568a3fa2SLorenzo Bianconi }; 3227568a3fa2SLorenzo Bianconi int err; 3228568a3fa2SLorenzo Bianconi 3229568a3fa2SLorenzo Bianconi rxq->page_pool = page_pool_create(&pp_params); 3230568a3fa2SLorenzo Bianconi if (IS_ERR(rxq->page_pool)) { 3231568a3fa2SLorenzo Bianconi err = PTR_ERR(rxq->page_pool); 3232568a3fa2SLorenzo Bianconi rxq->page_pool = NULL; 3233568a3fa2SLorenzo Bianconi return err; 3234568a3fa2SLorenzo Bianconi } 3235568a3fa2SLorenzo Bianconi 3236b02e5a0eSBjörn Töpel err = xdp_rxq_info_reg(&rxq->xdp_rxq, pp->dev, rxq->id, 0); 3237568a3fa2SLorenzo Bianconi if (err < 0) 3238568a3fa2SLorenzo Bianconi goto err_free_pp; 3239568a3fa2SLorenzo Bianconi 3240568a3fa2SLorenzo Bianconi err = xdp_rxq_info_reg_mem_model(&rxq->xdp_rxq, MEM_TYPE_PAGE_POOL, 3241568a3fa2SLorenzo Bianconi rxq->page_pool); 3242568a3fa2SLorenzo Bianconi if (err) 3243568a3fa2SLorenzo Bianconi goto err_unregister_rxq; 3244568a3fa2SLorenzo Bianconi 3245568a3fa2SLorenzo Bianconi return 0; 3246568a3fa2SLorenzo Bianconi 3247568a3fa2SLorenzo Bianconi err_unregister_rxq: 3248568a3fa2SLorenzo Bianconi xdp_rxq_info_unreg(&rxq->xdp_rxq); 3249568a3fa2SLorenzo Bianconi err_free_pp: 3250568a3fa2SLorenzo Bianconi page_pool_destroy(rxq->page_pool); 3251568a3fa2SLorenzo Bianconi rxq->page_pool = NULL; 3252568a3fa2SLorenzo Bianconi return err; 3253568a3fa2SLorenzo Bianconi } 3254568a3fa2SLorenzo Bianconi 3255c5aff182SThomas Petazzoni /* Handle rxq fill: allocates rxq skbs; called when initializing a port */ 3256c5aff182SThomas Petazzoni static int mvneta_rxq_fill(struct mvneta_port *pp, struct mvneta_rx_queue *rxq, 3257c5aff182SThomas Petazzoni int num) 3258c5aff182SThomas Petazzoni { 3259568a3fa2SLorenzo Bianconi int i, err; 3260568a3fa2SLorenzo Bianconi 3261568a3fa2SLorenzo Bianconi err = mvneta_create_page_pool(pp, rxq, num); 3262568a3fa2SLorenzo Bianconi if (err < 0) 3263568a3fa2SLorenzo Bianconi return err; 3264c5aff182SThomas Petazzoni 3265c5aff182SThomas Petazzoni for (i = 0; i < num; i++) { 3266a1a65ab1Swilly tarreau memset(rxq->descs + i, 0, sizeof(struct mvneta_rx_desc)); 32677e47fd84SGregory CLEMENT if (mvneta_rx_refill(pp, rxq->descs + i, rxq, 32687e47fd84SGregory CLEMENT GFP_KERNEL) != 0) { 32697e47fd84SGregory CLEMENT netdev_err(pp->dev, 32707e47fd84SGregory CLEMENT "%s:rxq %d, %d of %d buffs filled\n", 3271c5aff182SThomas Petazzoni __func__, rxq->id, i, num); 3272c5aff182SThomas Petazzoni break; 3273c5aff182SThomas Petazzoni } 3274c5aff182SThomas Petazzoni } 3275c5aff182SThomas Petazzoni 3276c5aff182SThomas Petazzoni /* Add this number of RX descriptors as non occupied (ready to 32776a20c175SThomas Petazzoni * get packets) 32786a20c175SThomas Petazzoni */ 3279c5aff182SThomas Petazzoni mvneta_rxq_non_occup_desc_add(pp, rxq, i); 3280c5aff182SThomas Petazzoni 3281c5aff182SThomas Petazzoni return i; 3282c5aff182SThomas Petazzoni } 3283c5aff182SThomas Petazzoni 3284c5aff182SThomas Petazzoni /* Free all packets pending transmit from all TXQs and reset TX port */ 3285c5aff182SThomas Petazzoni static void mvneta_tx_reset(struct mvneta_port *pp) 3286c5aff182SThomas Petazzoni { 3287c5aff182SThomas Petazzoni int queue; 3288c5aff182SThomas Petazzoni 32899672850bSEzequiel Garcia /* free the skb's in the tx ring */ 3290c5aff182SThomas Petazzoni for (queue = 0; queue < txq_number; queue++) 3291c5aff182SThomas Petazzoni mvneta_txq_done_force(pp, &pp->txqs[queue]); 3292c5aff182SThomas Petazzoni 3293c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_PORT_TX_RESET, MVNETA_PORT_TX_DMA_RESET); 3294c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_PORT_TX_RESET, 0); 3295c5aff182SThomas Petazzoni } 3296c5aff182SThomas Petazzoni 3297c5aff182SThomas Petazzoni static void mvneta_rx_reset(struct mvneta_port *pp) 3298c5aff182SThomas Petazzoni { 3299c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_PORT_RX_RESET, MVNETA_PORT_RX_DMA_RESET); 3300c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_PORT_RX_RESET, 0); 3301c5aff182SThomas Petazzoni } 3302c5aff182SThomas Petazzoni 3303c5aff182SThomas Petazzoni /* Rx/Tx queue initialization/cleanup methods */ 3304c5aff182SThomas Petazzoni 33054a188a63SJisheng Zhang static int mvneta_rxq_sw_init(struct mvneta_port *pp, 3306c5aff182SThomas Petazzoni struct mvneta_rx_queue *rxq) 3307c5aff182SThomas Petazzoni { 3308c5aff182SThomas Petazzoni rxq->size = pp->rx_ring_size; 3309c5aff182SThomas Petazzoni 3310c5aff182SThomas Petazzoni /* Allocate memory for RX descriptors */ 3311c5aff182SThomas Petazzoni rxq->descs = dma_alloc_coherent(pp->dev->dev.parent, 3312c5aff182SThomas Petazzoni rxq->size * MVNETA_DESC_ALIGNED_SIZE, 3313c5aff182SThomas Petazzoni &rxq->descs_phys, GFP_KERNEL); 3314f95936ccSMarkus Elfring if (!rxq->descs) 3315c5aff182SThomas Petazzoni return -ENOMEM; 3316c5aff182SThomas Petazzoni 3317c5aff182SThomas Petazzoni rxq->last_desc = rxq->size - 1; 3318c5aff182SThomas Petazzoni 33194a188a63SJisheng Zhang return 0; 33204a188a63SJisheng Zhang } 33214a188a63SJisheng Zhang 33224a188a63SJisheng Zhang static void mvneta_rxq_hw_init(struct mvneta_port *pp, 33234a188a63SJisheng Zhang struct mvneta_rx_queue *rxq) 33244a188a63SJisheng Zhang { 3325c5aff182SThomas Petazzoni /* Set Rx descriptors queue starting address */ 3326c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_RXQ_BASE_ADDR_REG(rxq->id), rxq->descs_phys); 3327c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_RXQ_SIZE_REG(rxq->id), rxq->size); 3328c5aff182SThomas Petazzoni 3329c5aff182SThomas Petazzoni /* Set coalescing pkts and time */ 3330c5aff182SThomas Petazzoni mvneta_rx_pkts_coal_set(pp, rxq, rxq->pkts_coal); 3331c5aff182SThomas Petazzoni mvneta_rx_time_coal_set(pp, rxq, rxq->time_coal); 3332c5aff182SThomas Petazzoni 3333dc35a10fSMarcin Wojtas if (!pp->bm_priv) { 3334562e2f46SYelena Krivosheev /* Set Offset */ 3335562e2f46SYelena Krivosheev mvneta_rxq_offset_set(pp, rxq, 0); 3336e735fd55SMarcin Wojtas mvneta_rxq_buf_size_set(pp, rxq, PAGE_SIZE < SZ_64K ? 33378dc9a088SLorenzo Bianconi MVNETA_MAX_RX_BUF_SIZE : 3338e735fd55SMarcin Wojtas MVNETA_RX_BUF_SIZE(pp->pkt_size)); 3339c5aff182SThomas Petazzoni mvneta_rxq_bm_disable(pp, rxq); 3340e9f64999SGregory CLEMENT mvneta_rxq_fill(pp, rxq, rxq->size); 3341dc35a10fSMarcin Wojtas } else { 3342562e2f46SYelena Krivosheev /* Set Offset */ 3343562e2f46SYelena Krivosheev mvneta_rxq_offset_set(pp, rxq, 3344562e2f46SYelena Krivosheev NET_SKB_PAD - pp->rx_offset_correction); 3345562e2f46SYelena Krivosheev 3346dc35a10fSMarcin Wojtas mvneta_rxq_bm_enable(pp, rxq); 3347562e2f46SYelena Krivosheev /* Fill RXQ with buffers from RX pool */ 3348dc35a10fSMarcin Wojtas mvneta_rxq_long_pool_set(pp, rxq); 3349dc35a10fSMarcin Wojtas mvneta_rxq_short_pool_set(pp, rxq); 3350e9f64999SGregory CLEMENT mvneta_rxq_non_occup_desc_add(pp, rxq, rxq->size); 3351dc35a10fSMarcin Wojtas } 33524a188a63SJisheng Zhang } 33534a188a63SJisheng Zhang 33544a188a63SJisheng Zhang /* Create a specified RX queue */ 33554a188a63SJisheng Zhang static int mvneta_rxq_init(struct mvneta_port *pp, 33564a188a63SJisheng Zhang struct mvneta_rx_queue *rxq) 33574a188a63SJisheng Zhang 33584a188a63SJisheng Zhang { 33594a188a63SJisheng Zhang int ret; 33604a188a63SJisheng Zhang 33614a188a63SJisheng Zhang ret = mvneta_rxq_sw_init(pp, rxq); 33624a188a63SJisheng Zhang if (ret < 0) 33634a188a63SJisheng Zhang return ret; 33644a188a63SJisheng Zhang 33654a188a63SJisheng Zhang mvneta_rxq_hw_init(pp, rxq); 3366dc35a10fSMarcin Wojtas 3367c5aff182SThomas Petazzoni return 0; 3368c5aff182SThomas Petazzoni } 3369c5aff182SThomas Petazzoni 3370c5aff182SThomas Petazzoni /* Cleanup Rx queue */ 3371c5aff182SThomas Petazzoni static void mvneta_rxq_deinit(struct mvneta_port *pp, 3372c5aff182SThomas Petazzoni struct mvneta_rx_queue *rxq) 3373c5aff182SThomas Petazzoni { 3374c5aff182SThomas Petazzoni mvneta_rxq_drop_pkts(pp, rxq); 3375c5aff182SThomas Petazzoni 3376c5aff182SThomas Petazzoni if (rxq->descs) 3377c5aff182SThomas Petazzoni dma_free_coherent(pp->dev->dev.parent, 3378c5aff182SThomas Petazzoni rxq->size * MVNETA_DESC_ALIGNED_SIZE, 3379c5aff182SThomas Petazzoni rxq->descs, 3380c5aff182SThomas Petazzoni rxq->descs_phys); 3381c5aff182SThomas Petazzoni 3382c5aff182SThomas Petazzoni rxq->descs = NULL; 3383c5aff182SThomas Petazzoni rxq->last_desc = 0; 3384c5aff182SThomas Petazzoni rxq->next_desc_to_proc = 0; 3385c5aff182SThomas Petazzoni rxq->descs_phys = 0; 3386562e2f46SYelena Krivosheev rxq->first_to_refill = 0; 3387562e2f46SYelena Krivosheev rxq->refill_num = 0; 3388c5aff182SThomas Petazzoni } 3389c5aff182SThomas Petazzoni 33904a188a63SJisheng Zhang static int mvneta_txq_sw_init(struct mvneta_port *pp, 3391c5aff182SThomas Petazzoni struct mvneta_tx_queue *txq) 3392c5aff182SThomas Petazzoni { 339350bf8cb6SGregory CLEMENT int cpu; 339450bf8cb6SGregory CLEMENT 3395c5aff182SThomas Petazzoni txq->size = pp->tx_ring_size; 3396c5aff182SThomas Petazzoni 33978eef5f97SEzequiel Garcia /* A queue must always have room for at least one skb. 33988eef5f97SEzequiel Garcia * Therefore, stop the queue when the free entries reaches 33998eef5f97SEzequiel Garcia * the maximum number of descriptors per skb. 34008eef5f97SEzequiel Garcia */ 34018eef5f97SEzequiel Garcia txq->tx_stop_threshold = txq->size - MVNETA_MAX_SKB_DESCS; 34028eef5f97SEzequiel Garcia txq->tx_wake_threshold = txq->tx_stop_threshold / 2; 34038eef5f97SEzequiel Garcia 3404c5aff182SThomas Petazzoni /* Allocate memory for TX descriptors */ 3405c5aff182SThomas Petazzoni txq->descs = dma_alloc_coherent(pp->dev->dev.parent, 3406c5aff182SThomas Petazzoni txq->size * MVNETA_DESC_ALIGNED_SIZE, 3407c5aff182SThomas Petazzoni &txq->descs_phys, GFP_KERNEL); 3408f95936ccSMarkus Elfring if (!txq->descs) 3409c5aff182SThomas Petazzoni return -ENOMEM; 3410c5aff182SThomas Petazzoni 3411c5aff182SThomas Petazzoni txq->last_desc = txq->size - 1; 3412c5aff182SThomas Petazzoni 34139e58c8b4SLorenzo Bianconi txq->buf = kmalloc_array(txq->size, sizeof(*txq->buf), GFP_KERNEL); 3414f4544e53STom Rix if (!txq->buf) 3415c5aff182SThomas Petazzoni return -ENOMEM; 34162adb719dSEzequiel Garcia 34172adb719dSEzequiel Garcia /* Allocate DMA buffers for TSO MAC/IP/TCP headers */ 34182adb719dSEzequiel Garcia txq->tso_hdrs = dma_alloc_coherent(pp->dev->dev.parent, 34192adb719dSEzequiel Garcia txq->size * TSO_HEADER_SIZE, 34202adb719dSEzequiel Garcia &txq->tso_hdrs_phys, GFP_KERNEL); 3421f4544e53STom Rix if (!txq->tso_hdrs) 34222adb719dSEzequiel Garcia return -ENOMEM; 3423c5aff182SThomas Petazzoni 342450bf8cb6SGregory CLEMENT /* Setup XPS mapping */ 3425cf9bf871SMaxime Chevallier if (pp->neta_armada3700) 3426cf9bf871SMaxime Chevallier cpu = 0; 3427cf9bf871SMaxime Chevallier else if (txq_number > 1) 342850bf8cb6SGregory CLEMENT cpu = txq->id % num_present_cpus(); 342950bf8cb6SGregory CLEMENT else 343050bf8cb6SGregory CLEMENT cpu = pp->rxq_def % num_present_cpus(); 343150bf8cb6SGregory CLEMENT cpumask_set_cpu(cpu, &txq->affinity_mask); 343250bf8cb6SGregory CLEMENT netif_set_xps_queue(pp->dev, &txq->affinity_mask, txq->id); 343350bf8cb6SGregory CLEMENT 3434c5aff182SThomas Petazzoni return 0; 3435c5aff182SThomas Petazzoni } 3436c5aff182SThomas Petazzoni 34374a188a63SJisheng Zhang static void mvneta_txq_hw_init(struct mvneta_port *pp, 34384a188a63SJisheng Zhang struct mvneta_tx_queue *txq) 34394a188a63SJisheng Zhang { 34404a188a63SJisheng Zhang /* Set maximum bandwidth for enabled TXQs */ 34414a188a63SJisheng Zhang mvreg_write(pp, MVETH_TXQ_TOKEN_CFG_REG(txq->id), 0x03ffffff); 34424a188a63SJisheng Zhang mvreg_write(pp, MVETH_TXQ_TOKEN_COUNT_REG(txq->id), 0x3fffffff); 34434a188a63SJisheng Zhang 34444a188a63SJisheng Zhang /* Set Tx descriptors queue starting address */ 34454a188a63SJisheng Zhang mvreg_write(pp, MVNETA_TXQ_BASE_ADDR_REG(txq->id), txq->descs_phys); 34464a188a63SJisheng Zhang mvreg_write(pp, MVNETA_TXQ_SIZE_REG(txq->id), txq->size); 34474a188a63SJisheng Zhang 34484a188a63SJisheng Zhang mvneta_tx_done_pkts_coal_set(pp, txq, txq->done_pkts_coal); 34494a188a63SJisheng Zhang } 34504a188a63SJisheng Zhang 34514a188a63SJisheng Zhang /* Create and initialize a tx queue */ 34524a188a63SJisheng Zhang static int mvneta_txq_init(struct mvneta_port *pp, 34534a188a63SJisheng Zhang struct mvneta_tx_queue *txq) 34544a188a63SJisheng Zhang { 34554a188a63SJisheng Zhang int ret; 34564a188a63SJisheng Zhang 34574a188a63SJisheng Zhang ret = mvneta_txq_sw_init(pp, txq); 34584a188a63SJisheng Zhang if (ret < 0) 34594a188a63SJisheng Zhang return ret; 34604a188a63SJisheng Zhang 34614a188a63SJisheng Zhang mvneta_txq_hw_init(pp, txq); 34624a188a63SJisheng Zhang 34634a188a63SJisheng Zhang return 0; 34644a188a63SJisheng Zhang } 34654a188a63SJisheng Zhang 3466c5aff182SThomas Petazzoni /* Free allocated resources when mvneta_txq_init() fails to allocate memory*/ 34674a188a63SJisheng Zhang static void mvneta_txq_sw_deinit(struct mvneta_port *pp, 3468c5aff182SThomas Petazzoni struct mvneta_tx_queue *txq) 3469c5aff182SThomas Petazzoni { 3470a29b6235SMarcin Wojtas struct netdev_queue *nq = netdev_get_tx_queue(pp->dev, txq->id); 3471a29b6235SMarcin Wojtas 34729e58c8b4SLorenzo Bianconi kfree(txq->buf); 3473c5aff182SThomas Petazzoni 34742adb719dSEzequiel Garcia if (txq->tso_hdrs) 34752adb719dSEzequiel Garcia dma_free_coherent(pp->dev->dev.parent, 34762adb719dSEzequiel Garcia txq->size * TSO_HEADER_SIZE, 34772adb719dSEzequiel Garcia txq->tso_hdrs, txq->tso_hdrs_phys); 3478c5aff182SThomas Petazzoni if (txq->descs) 3479c5aff182SThomas Petazzoni dma_free_coherent(pp->dev->dev.parent, 3480c5aff182SThomas Petazzoni txq->size * MVNETA_DESC_ALIGNED_SIZE, 3481c5aff182SThomas Petazzoni txq->descs, txq->descs_phys); 3482c5aff182SThomas Petazzoni 3483a29b6235SMarcin Wojtas netdev_tx_reset_queue(nq); 3484a29b6235SMarcin Wojtas 3485c5aff182SThomas Petazzoni txq->descs = NULL; 3486c5aff182SThomas Petazzoni txq->last_desc = 0; 3487c5aff182SThomas Petazzoni txq->next_desc_to_proc = 0; 3488c5aff182SThomas Petazzoni txq->descs_phys = 0; 34894a188a63SJisheng Zhang } 3490c5aff182SThomas Petazzoni 34914a188a63SJisheng Zhang static void mvneta_txq_hw_deinit(struct mvneta_port *pp, 34924a188a63SJisheng Zhang struct mvneta_tx_queue *txq) 34934a188a63SJisheng Zhang { 3494c5aff182SThomas Petazzoni /* Set minimum bandwidth for disabled TXQs */ 3495c5aff182SThomas Petazzoni mvreg_write(pp, MVETH_TXQ_TOKEN_CFG_REG(txq->id), 0); 3496c5aff182SThomas Petazzoni mvreg_write(pp, MVETH_TXQ_TOKEN_COUNT_REG(txq->id), 0); 3497c5aff182SThomas Petazzoni 3498c5aff182SThomas Petazzoni /* Set Tx descriptors queue starting address and size */ 3499c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_TXQ_BASE_ADDR_REG(txq->id), 0); 3500c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_TXQ_SIZE_REG(txq->id), 0); 3501c5aff182SThomas Petazzoni } 3502c5aff182SThomas Petazzoni 35034a188a63SJisheng Zhang static void mvneta_txq_deinit(struct mvneta_port *pp, 35044a188a63SJisheng Zhang struct mvneta_tx_queue *txq) 35054a188a63SJisheng Zhang { 35064a188a63SJisheng Zhang mvneta_txq_sw_deinit(pp, txq); 35074a188a63SJisheng Zhang mvneta_txq_hw_deinit(pp, txq); 35084a188a63SJisheng Zhang } 35094a188a63SJisheng Zhang 3510c5aff182SThomas Petazzoni /* Cleanup all Tx queues */ 3511c5aff182SThomas Petazzoni static void mvneta_cleanup_txqs(struct mvneta_port *pp) 3512c5aff182SThomas Petazzoni { 3513c5aff182SThomas Petazzoni int queue; 3514c5aff182SThomas Petazzoni 3515c5aff182SThomas Petazzoni for (queue = 0; queue < txq_number; queue++) 3516c5aff182SThomas Petazzoni mvneta_txq_deinit(pp, &pp->txqs[queue]); 3517c5aff182SThomas Petazzoni } 3518c5aff182SThomas Petazzoni 3519c5aff182SThomas Petazzoni /* Cleanup all Rx queues */ 3520c5aff182SThomas Petazzoni static void mvneta_cleanup_rxqs(struct mvneta_port *pp) 3521c5aff182SThomas Petazzoni { 35222dcf75e2SGregory CLEMENT int queue; 35232dcf75e2SGregory CLEMENT 3524ca5902a6SYelena Krivosheev for (queue = 0; queue < rxq_number; queue++) 35252dcf75e2SGregory CLEMENT mvneta_rxq_deinit(pp, &pp->rxqs[queue]); 3526c5aff182SThomas Petazzoni } 3527c5aff182SThomas Petazzoni 3528c5aff182SThomas Petazzoni 3529c5aff182SThomas Petazzoni /* Init all Rx queues */ 3530c5aff182SThomas Petazzoni static int mvneta_setup_rxqs(struct mvneta_port *pp) 3531c5aff182SThomas Petazzoni { 35322dcf75e2SGregory CLEMENT int queue; 35332dcf75e2SGregory CLEMENT 35342dcf75e2SGregory CLEMENT for (queue = 0; queue < rxq_number; queue++) { 35352dcf75e2SGregory CLEMENT int err = mvneta_rxq_init(pp, &pp->rxqs[queue]); 35362dcf75e2SGregory CLEMENT 3537c5aff182SThomas Petazzoni if (err) { 3538c5aff182SThomas Petazzoni netdev_err(pp->dev, "%s: can't create rxq=%d\n", 35392dcf75e2SGregory CLEMENT __func__, queue); 3540c5aff182SThomas Petazzoni mvneta_cleanup_rxqs(pp); 3541c5aff182SThomas Petazzoni return err; 3542c5aff182SThomas Petazzoni } 35432dcf75e2SGregory CLEMENT } 3544c5aff182SThomas Petazzoni 3545c5aff182SThomas Petazzoni return 0; 3546c5aff182SThomas Petazzoni } 3547c5aff182SThomas Petazzoni 3548c5aff182SThomas Petazzoni /* Init all tx queues */ 3549c5aff182SThomas Petazzoni static int mvneta_setup_txqs(struct mvneta_port *pp) 3550c5aff182SThomas Petazzoni { 3551c5aff182SThomas Petazzoni int queue; 3552c5aff182SThomas Petazzoni 3553c5aff182SThomas Petazzoni for (queue = 0; queue < txq_number; queue++) { 3554c5aff182SThomas Petazzoni int err = mvneta_txq_init(pp, &pp->txqs[queue]); 3555c5aff182SThomas Petazzoni if (err) { 3556c5aff182SThomas Petazzoni netdev_err(pp->dev, "%s: can't create txq=%d\n", 3557c5aff182SThomas Petazzoni __func__, queue); 3558c5aff182SThomas Petazzoni mvneta_cleanup_txqs(pp); 3559c5aff182SThomas Petazzoni return err; 3560c5aff182SThomas Petazzoni } 3561c5aff182SThomas Petazzoni } 3562c5aff182SThomas Petazzoni 3563c5aff182SThomas Petazzoni return 0; 3564c5aff182SThomas Petazzoni } 3565c5aff182SThomas Petazzoni 3566b4748553SSascha Hauer static int mvneta_comphy_init(struct mvneta_port *pp, phy_interface_t interface) 3567031b922bSMarek Behún { 3568031b922bSMarek Behún int ret; 3569031b922bSMarek Behún 3570b4748553SSascha Hauer ret = phy_set_mode_ext(pp->comphy, PHY_MODE_ETHERNET, interface); 3571031b922bSMarek Behún if (ret) 3572031b922bSMarek Behún return ret; 3573031b922bSMarek Behún 3574031b922bSMarek Behún return phy_power_on(pp->comphy); 3575031b922bSMarek Behún } 3576031b922bSMarek Behún 3577b4748553SSascha Hauer static int mvneta_config_interface(struct mvneta_port *pp, 3578b4748553SSascha Hauer phy_interface_t interface) 3579b4748553SSascha Hauer { 3580b4748553SSascha Hauer int ret = 0; 3581b4748553SSascha Hauer 3582b4748553SSascha Hauer if (pp->comphy) { 3583b4748553SSascha Hauer if (interface == PHY_INTERFACE_MODE_SGMII || 3584b4748553SSascha Hauer interface == PHY_INTERFACE_MODE_1000BASEX || 3585b4748553SSascha Hauer interface == PHY_INTERFACE_MODE_2500BASEX) { 3586b4748553SSascha Hauer ret = mvneta_comphy_init(pp, interface); 3587b4748553SSascha Hauer } 3588b4748553SSascha Hauer } else { 3589b4748553SSascha Hauer switch (interface) { 3590b4748553SSascha Hauer case PHY_INTERFACE_MODE_QSGMII: 3591b4748553SSascha Hauer mvreg_write(pp, MVNETA_SERDES_CFG, 3592b4748553SSascha Hauer MVNETA_QSGMII_SERDES_PROTO); 3593b4748553SSascha Hauer break; 3594b4748553SSascha Hauer 3595b4748553SSascha Hauer case PHY_INTERFACE_MODE_SGMII: 3596b4748553SSascha Hauer case PHY_INTERFACE_MODE_1000BASEX: 3597b4748553SSascha Hauer mvreg_write(pp, MVNETA_SERDES_CFG, 3598b4748553SSascha Hauer MVNETA_SGMII_SERDES_PROTO); 3599b4748553SSascha Hauer break; 36001a642ca7SSascha Hauer 36011a642ca7SSascha Hauer case PHY_INTERFACE_MODE_2500BASEX: 36021a642ca7SSascha Hauer mvreg_write(pp, MVNETA_SERDES_CFG, 36031a642ca7SSascha Hauer MVNETA_HSGMII_SERDES_PROTO); 36041a642ca7SSascha Hauer break; 3605b4748553SSascha Hauer default: 3606d3d239dcSSascha Hauer break; 3607b4748553SSascha Hauer } 3608b4748553SSascha Hauer } 3609b4748553SSascha Hauer 3610b4748553SSascha Hauer pp->phy_interface = interface; 3611b4748553SSascha Hauer 3612b4748553SSascha Hauer return ret; 3613b4748553SSascha Hauer } 3614b4748553SSascha Hauer 3615c5aff182SThomas Petazzoni static void mvneta_start_dev(struct mvneta_port *pp) 3616c5aff182SThomas Petazzoni { 36176b125d63SGregory CLEMENT int cpu; 361812bb03b4SMaxime Ripard 3619b4748553SSascha Hauer WARN_ON(mvneta_config_interface(pp, pp->phy_interface)); 3620a10c1c81SRussell King 3621c5aff182SThomas Petazzoni mvneta_max_rx_size_set(pp, pp->pkt_size); 3622c5aff182SThomas Petazzoni mvneta_txq_max_tx_size_set(pp, pp->pkt_size); 3623c5aff182SThomas Petazzoni 3624c5aff182SThomas Petazzoni /* start the Rx/Tx activity */ 3625c5aff182SThomas Petazzoni mvneta_port_enable(pp); 3626c5aff182SThomas Petazzoni 36272636ac3cSMarcin Wojtas if (!pp->neta_armada3700) { 3628c5aff182SThomas Petazzoni /* Enable polling on the port */ 3629129219e4SGregory CLEMENT for_each_online_cpu(cpu) { 36302636ac3cSMarcin Wojtas struct mvneta_pcpu_port *port = 36312636ac3cSMarcin Wojtas per_cpu_ptr(pp->ports, cpu); 363212bb03b4SMaxime Ripard 363312bb03b4SMaxime Ripard napi_enable(&port->napi); 363412bb03b4SMaxime Ripard } 36352636ac3cSMarcin Wojtas } else { 36362636ac3cSMarcin Wojtas napi_enable(&pp->napi); 36372636ac3cSMarcin Wojtas } 3638c5aff182SThomas Petazzoni 36392dcf75e2SGregory CLEMENT /* Unmask interrupts. It has to be done from each CPU */ 36406b125d63SGregory CLEMENT on_each_cpu(mvneta_percpu_unmask_interrupt, pp, true); 36416b125d63SGregory CLEMENT 3642898b2970SStas Sergeev mvreg_write(pp, MVNETA_INTR_MISC_MASK, 3643898b2970SStas Sergeev MVNETA_CAUSE_PHY_STATUS_CHANGE | 3644856b2cc5SRussell King MVNETA_CAUSE_LINK_CHANGE); 3645c5aff182SThomas Petazzoni 3646503f9aa9SRussell King phylink_start(pp->phylink); 364761b5cc20SDaniel González Cabanelas 36485ba2254bSJisheng Zhang /* We may have called phylink_speed_down before */ 364961b5cc20SDaniel González Cabanelas phylink_speed_up(pp->phylink); 365061b5cc20SDaniel González Cabanelas 3651c5aff182SThomas Petazzoni netif_tx_start_all_queues(pp->dev); 365262a502ccSLorenzo Bianconi 365362a502ccSLorenzo Bianconi clear_bit(__MVNETA_DOWN, &pp->state); 3654c5aff182SThomas Petazzoni } 3655c5aff182SThomas Petazzoni 3656c5aff182SThomas Petazzoni static void mvneta_stop_dev(struct mvneta_port *pp) 3657c5aff182SThomas Petazzoni { 365812bb03b4SMaxime Ripard unsigned int cpu; 365912bb03b4SMaxime Ripard 366062a502ccSLorenzo Bianconi set_bit(__MVNETA_DOWN, &pp->state); 366162a502ccSLorenzo Bianconi 366261b5cc20SDaniel González Cabanelas if (device_may_wakeup(&pp->dev->dev)) 366361b5cc20SDaniel González Cabanelas phylink_speed_down(pp->phylink, false); 366461b5cc20SDaniel González Cabanelas 3665503f9aa9SRussell King phylink_stop(pp->phylink); 3666c5aff182SThomas Petazzoni 36672636ac3cSMarcin Wojtas if (!pp->neta_armada3700) { 3668129219e4SGregory CLEMENT for_each_online_cpu(cpu) { 36692636ac3cSMarcin Wojtas struct mvneta_pcpu_port *port = 36702636ac3cSMarcin Wojtas per_cpu_ptr(pp->ports, cpu); 367112bb03b4SMaxime Ripard 367212bb03b4SMaxime Ripard napi_disable(&port->napi); 367312bb03b4SMaxime Ripard } 36742636ac3cSMarcin Wojtas } else { 36752636ac3cSMarcin Wojtas napi_disable(&pp->napi); 36762636ac3cSMarcin Wojtas } 3677c5aff182SThomas Petazzoni 3678c5aff182SThomas Petazzoni netif_carrier_off(pp->dev); 3679c5aff182SThomas Petazzoni 3680c5aff182SThomas Petazzoni mvneta_port_down(pp); 3681c5aff182SThomas Petazzoni netif_tx_stop_all_queues(pp->dev); 3682c5aff182SThomas Petazzoni 3683c5aff182SThomas Petazzoni /* Stop the port activity */ 3684c5aff182SThomas Petazzoni mvneta_port_disable(pp); 3685c5aff182SThomas Petazzoni 3686c5aff182SThomas Petazzoni /* Clear all ethernet port interrupts */ 3687db488c10SGregory CLEMENT on_each_cpu(mvneta_percpu_clear_intr_cause, pp, true); 3688c5aff182SThomas Petazzoni 3689c5aff182SThomas Petazzoni /* Mask all ethernet port interrupts */ 3690db488c10SGregory CLEMENT on_each_cpu(mvneta_percpu_mask_interrupt, pp, true); 3691c5aff182SThomas Petazzoni 3692c5aff182SThomas Petazzoni mvneta_tx_reset(pp); 3693c5aff182SThomas Petazzoni mvneta_rx_reset(pp); 3694a10c1c81SRussell King 3695a10c1c81SRussell King WARN_ON(phy_power_off(pp->comphy)); 3696c5aff182SThomas Petazzoni } 3697c5aff182SThomas Petazzoni 3698db5dd0dbSMarcin Wojtas static void mvneta_percpu_enable(void *arg) 3699db5dd0dbSMarcin Wojtas { 3700db5dd0dbSMarcin Wojtas struct mvneta_port *pp = arg; 3701db5dd0dbSMarcin Wojtas 3702db5dd0dbSMarcin Wojtas enable_percpu_irq(pp->dev->irq, IRQ_TYPE_NONE); 3703db5dd0dbSMarcin Wojtas } 3704db5dd0dbSMarcin Wojtas 3705db5dd0dbSMarcin Wojtas static void mvneta_percpu_disable(void *arg) 3706db5dd0dbSMarcin Wojtas { 3707db5dd0dbSMarcin Wojtas struct mvneta_port *pp = arg; 3708db5dd0dbSMarcin Wojtas 3709db5dd0dbSMarcin Wojtas disable_percpu_irq(pp->dev->irq); 3710db5dd0dbSMarcin Wojtas } 3711db5dd0dbSMarcin Wojtas 3712c5aff182SThomas Petazzoni /* Change the device mtu */ 3713c5aff182SThomas Petazzoni static int mvneta_change_mtu(struct net_device *dev, int mtu) 3714c5aff182SThomas Petazzoni { 3715c5aff182SThomas Petazzoni struct mvneta_port *pp = netdev_priv(dev); 3716c5aff182SThomas Petazzoni int ret; 3717c5aff182SThomas Petazzoni 37185777987eSJarod Wilson if (!IS_ALIGNED(MVNETA_RX_PKT_SIZE(mtu), 8)) { 37195777987eSJarod Wilson netdev_info(dev, "Illegal MTU value %d, rounding to %d\n", 37205777987eSJarod Wilson mtu, ALIGN(MVNETA_RX_PKT_SIZE(mtu), 8)); 37215777987eSJarod Wilson mtu = ALIGN(MVNETA_RX_PKT_SIZE(mtu), 8); 37225777987eSJarod Wilson } 3723c5aff182SThomas Petazzoni 37240db51da7SLorenzo Bianconi if (pp->xdp_prog && mtu > MVNETA_MAX_RX_BUF_SIZE) { 37250db51da7SLorenzo Bianconi netdev_info(dev, "Illegal MTU value %d for XDP mode\n", mtu); 37260db51da7SLorenzo Bianconi return -EINVAL; 37270db51da7SLorenzo Bianconi } 37280db51da7SLorenzo Bianconi 3729c5aff182SThomas Petazzoni dev->mtu = mtu; 3730c5aff182SThomas Petazzoni 3731b65657fcSSimon Guinot if (!netif_running(dev)) { 3732dc35a10fSMarcin Wojtas if (pp->bm_priv) 3733dc35a10fSMarcin Wojtas mvneta_bm_update_mtu(pp, mtu); 3734dc35a10fSMarcin Wojtas 3735b65657fcSSimon Guinot netdev_update_features(dev); 3736c5aff182SThomas Petazzoni return 0; 3737b65657fcSSimon Guinot } 3738c5aff182SThomas Petazzoni 37396a20c175SThomas Petazzoni /* The interface is running, so we have to force a 3740a92dbd96SEzequiel Garcia * reallocation of the queues 3741c5aff182SThomas Petazzoni */ 3742c5aff182SThomas Petazzoni mvneta_stop_dev(pp); 3743db5dd0dbSMarcin Wojtas on_each_cpu(mvneta_percpu_disable, pp, true); 3744c5aff182SThomas Petazzoni 3745c5aff182SThomas Petazzoni mvneta_cleanup_txqs(pp); 3746c5aff182SThomas Petazzoni mvneta_cleanup_rxqs(pp); 3747c5aff182SThomas Petazzoni 3748dc35a10fSMarcin Wojtas if (pp->bm_priv) 3749dc35a10fSMarcin Wojtas mvneta_bm_update_mtu(pp, mtu); 3750dc35a10fSMarcin Wojtas 3751a92dbd96SEzequiel Garcia pp->pkt_size = MVNETA_RX_PKT_SIZE(dev->mtu); 3752c5aff182SThomas Petazzoni 3753c5aff182SThomas Petazzoni ret = mvneta_setup_rxqs(pp); 3754c5aff182SThomas Petazzoni if (ret) { 3755a92dbd96SEzequiel Garcia netdev_err(dev, "unable to setup rxqs after MTU change\n"); 3756c5aff182SThomas Petazzoni return ret; 3757c5aff182SThomas Petazzoni } 3758c5aff182SThomas Petazzoni 3759a92dbd96SEzequiel Garcia ret = mvneta_setup_txqs(pp); 3760a92dbd96SEzequiel Garcia if (ret) { 3761a92dbd96SEzequiel Garcia netdev_err(dev, "unable to setup txqs after MTU change\n"); 3762a92dbd96SEzequiel Garcia return ret; 3763a92dbd96SEzequiel Garcia } 3764c5aff182SThomas Petazzoni 3765db5dd0dbSMarcin Wojtas on_each_cpu(mvneta_percpu_enable, pp, true); 3766c5aff182SThomas Petazzoni mvneta_start_dev(pp); 3767c5aff182SThomas Petazzoni 3768b65657fcSSimon Guinot netdev_update_features(dev); 3769b65657fcSSimon Guinot 3770c5aff182SThomas Petazzoni return 0; 3771c5aff182SThomas Petazzoni } 3772c5aff182SThomas Petazzoni 3773b65657fcSSimon Guinot static netdev_features_t mvneta_fix_features(struct net_device *dev, 3774b65657fcSSimon Guinot netdev_features_t features) 3775b65657fcSSimon Guinot { 3776b65657fcSSimon Guinot struct mvneta_port *pp = netdev_priv(dev); 3777b65657fcSSimon Guinot 3778b65657fcSSimon Guinot if (pp->tx_csum_limit && dev->mtu > pp->tx_csum_limit) { 3779b65657fcSSimon Guinot features &= ~(NETIF_F_IP_CSUM | NETIF_F_TSO); 3780b65657fcSSimon Guinot netdev_info(dev, 3781b65657fcSSimon Guinot "Disable IP checksum for MTU greater than %dB\n", 3782b65657fcSSimon Guinot pp->tx_csum_limit); 3783b65657fcSSimon Guinot } 3784b65657fcSSimon Guinot 3785b65657fcSSimon Guinot return features; 3786b65657fcSSimon Guinot } 3787b65657fcSSimon Guinot 37888cc3e439SThomas Petazzoni /* Get mac address */ 37898cc3e439SThomas Petazzoni static void mvneta_get_mac_addr(struct mvneta_port *pp, unsigned char *addr) 37908cc3e439SThomas Petazzoni { 37918cc3e439SThomas Petazzoni u32 mac_addr_l, mac_addr_h; 37928cc3e439SThomas Petazzoni 37938cc3e439SThomas Petazzoni mac_addr_l = mvreg_read(pp, MVNETA_MAC_ADDR_LOW); 37948cc3e439SThomas Petazzoni mac_addr_h = mvreg_read(pp, MVNETA_MAC_ADDR_HIGH); 37958cc3e439SThomas Petazzoni addr[0] = (mac_addr_h >> 24) & 0xFF; 37968cc3e439SThomas Petazzoni addr[1] = (mac_addr_h >> 16) & 0xFF; 37978cc3e439SThomas Petazzoni addr[2] = (mac_addr_h >> 8) & 0xFF; 37988cc3e439SThomas Petazzoni addr[3] = mac_addr_h & 0xFF; 37998cc3e439SThomas Petazzoni addr[4] = (mac_addr_l >> 8) & 0xFF; 38008cc3e439SThomas Petazzoni addr[5] = mac_addr_l & 0xFF; 38018cc3e439SThomas Petazzoni } 38028cc3e439SThomas Petazzoni 3803c5aff182SThomas Petazzoni /* Handle setting mac address */ 3804c5aff182SThomas Petazzoni static int mvneta_set_mac_addr(struct net_device *dev, void *addr) 3805c5aff182SThomas Petazzoni { 3806c5aff182SThomas Petazzoni struct mvneta_port *pp = netdev_priv(dev); 3807e68de360SEzequiel Garcia struct sockaddr *sockaddr = addr; 3808e68de360SEzequiel Garcia int ret; 3809c5aff182SThomas Petazzoni 3810e68de360SEzequiel Garcia ret = eth_prepare_mac_addr_change(dev, addr); 3811e68de360SEzequiel Garcia if (ret < 0) 3812e68de360SEzequiel Garcia return ret; 3813c5aff182SThomas Petazzoni /* Remove previous address table entry */ 3814c5aff182SThomas Petazzoni mvneta_mac_addr_set(pp, dev->dev_addr, -1); 3815c5aff182SThomas Petazzoni 3816c5aff182SThomas Petazzoni /* Set new addr in hw */ 381790b74c01SGregory CLEMENT mvneta_mac_addr_set(pp, sockaddr->sa_data, pp->rxq_def); 3818c5aff182SThomas Petazzoni 3819e68de360SEzequiel Garcia eth_commit_mac_addr_change(dev, addr); 3820c5aff182SThomas Petazzoni return 0; 3821c5aff182SThomas Petazzoni } 3822c5aff182SThomas Petazzoni 382344cc27e4SIoana Ciornei static void mvneta_validate(struct phylink_config *config, 382444cc27e4SIoana Ciornei unsigned long *supported, 3825503f9aa9SRussell King struct phylink_link_state *state) 3826503f9aa9SRussell King { 3827c762b7faSRussell King (Oracle) /* We only support QSGMII, SGMII, 802.3z and RGMII modes. 3828c762b7faSRussell King (Oracle) * When in 802.3z mode, we must have AN enabled: 3829c762b7faSRussell King (Oracle) * "Bit 2 Field InBandAnEn In-band Auto-Negotiation enable. ... 3830c762b7faSRussell King (Oracle) * When <PortType> = 1 (1000BASE-X) this field must be set to 1." 3831c762b7faSRussell King (Oracle) */ 3832d9ca7280SRussell King (Oracle) if (phy_interface_mode_is_8023z(state->interface) && 3833d9ca7280SRussell King (Oracle) !phylink_test(state->advertising, Autoneg)) { 38344973056cSSean Anderson linkmode_zero(supported); 3835503f9aa9SRussell King return; 3836503f9aa9SRussell King } 3837503f9aa9SRussell King 383802a0988bSRussell King (Oracle) phylink_generic_validate(config, supported, state); 3839503f9aa9SRussell King } 3840503f9aa9SRussell King 3841d46b7e4fSRussell King static void mvneta_mac_pcs_get_state(struct phylink_config *config, 3842503f9aa9SRussell King struct phylink_link_state *state) 3843c5aff182SThomas Petazzoni { 384444cc27e4SIoana Ciornei struct net_device *ndev = to_net_dev(config->dev); 3845c5aff182SThomas Petazzoni struct mvneta_port *pp = netdev_priv(ndev); 3846503f9aa9SRussell King u32 gmac_stat; 3847c5aff182SThomas Petazzoni 3848503f9aa9SRussell King gmac_stat = mvreg_read(pp, MVNETA_GMAC_STATUS); 3849503f9aa9SRussell King 3850503f9aa9SRussell King if (gmac_stat & MVNETA_GMAC_SPEED_1000) 3851a10c1c81SRussell King state->speed = 3852a10c1c81SRussell King state->interface == PHY_INTERFACE_MODE_2500BASEX ? 3853a10c1c81SRussell King SPEED_2500 : SPEED_1000; 3854503f9aa9SRussell King else if (gmac_stat & MVNETA_GMAC_SPEED_100) 3855503f9aa9SRussell King state->speed = SPEED_100; 3856503f9aa9SRussell King else 3857503f9aa9SRussell King state->speed = SPEED_10; 3858503f9aa9SRussell King 3859503f9aa9SRussell King state->an_complete = !!(gmac_stat & MVNETA_GMAC_AN_COMPLETE); 3860503f9aa9SRussell King state->link = !!(gmac_stat & MVNETA_GMAC_LINK_UP); 3861503f9aa9SRussell King state->duplex = !!(gmac_stat & MVNETA_GMAC_FULL_DUPLEX); 3862503f9aa9SRussell King 3863503f9aa9SRussell King state->pause = 0; 38644932a918SRussell King if (gmac_stat & MVNETA_GMAC_RX_FLOW_CTRL_ENABLE) 38654932a918SRussell King state->pause |= MLO_PAUSE_RX; 38664932a918SRussell King if (gmac_stat & MVNETA_GMAC_TX_FLOW_CTRL_ENABLE) 38674932a918SRussell King state->pause |= MLO_PAUSE_TX; 3868503f9aa9SRussell King } 3869503f9aa9SRussell King 387044cc27e4SIoana Ciornei static void mvneta_mac_an_restart(struct phylink_config *config) 387122f4bf8aSRussell King { 387244cc27e4SIoana Ciornei struct net_device *ndev = to_net_dev(config->dev); 387322f4bf8aSRussell King struct mvneta_port *pp = netdev_priv(ndev); 387422f4bf8aSRussell King u32 gmac_an = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG); 387522f4bf8aSRussell King 387622f4bf8aSRussell King mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, 387722f4bf8aSRussell King gmac_an | MVNETA_GMAC_INBAND_RESTART_AN); 387822f4bf8aSRussell King mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, 387922f4bf8aSRussell King gmac_an & ~MVNETA_GMAC_INBAND_RESTART_AN); 388022f4bf8aSRussell King } 388122f4bf8aSRussell King 388244cc27e4SIoana Ciornei static void mvneta_mac_config(struct phylink_config *config, unsigned int mode, 3883503f9aa9SRussell King const struct phylink_link_state *state) 3884503f9aa9SRussell King { 388544cc27e4SIoana Ciornei struct net_device *ndev = to_net_dev(config->dev); 3886503f9aa9SRussell King struct mvneta_port *pp = netdev_priv(ndev); 388722f4bf8aSRussell King u32 new_ctrl0, gmac_ctrl0 = mvreg_read(pp, MVNETA_GMAC_CTRL_0); 3888503f9aa9SRussell King u32 new_ctrl2, gmac_ctrl2 = mvreg_read(pp, MVNETA_GMAC_CTRL_2); 3889da58a931SMaxime Chevallier u32 new_ctrl4, gmac_ctrl4 = mvreg_read(pp, MVNETA_GMAC_CTRL_4); 3890503f9aa9SRussell King u32 new_clk, gmac_clk = mvreg_read(pp, MVNETA_GMAC_CLOCK_DIVIDER); 3891503f9aa9SRussell King u32 new_an, gmac_an = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG); 3892503f9aa9SRussell King 389322f4bf8aSRussell King new_ctrl0 = gmac_ctrl0 & ~MVNETA_GMAC0_PORT_1000BASE_X; 389432699954SRussell King new_ctrl2 = gmac_ctrl2 & ~(MVNETA_GMAC2_INBAND_AN_ENABLE | 389532699954SRussell King MVNETA_GMAC2_PORT_RESET); 3896da58a931SMaxime Chevallier new_ctrl4 = gmac_ctrl4 & ~(MVNETA_GMAC4_SHORT_PREAMBLE_ENABLE); 3897503f9aa9SRussell King new_clk = gmac_clk & ~MVNETA_GMAC_1MS_CLOCK_ENABLE; 3898503f9aa9SRussell King new_an = gmac_an & ~(MVNETA_GMAC_INBAND_AN_ENABLE | 3899503f9aa9SRussell King MVNETA_GMAC_INBAND_RESTART_AN | 3900503f9aa9SRussell King MVNETA_GMAC_AN_SPEED_EN | 390122f4bf8aSRussell King MVNETA_GMAC_ADVERT_SYM_FLOW_CTRL | 3902503f9aa9SRussell King MVNETA_GMAC_AN_FLOW_CTRL_EN | 3903503f9aa9SRussell King MVNETA_GMAC_AN_DUPLEX_EN); 3904c5aff182SThomas Petazzoni 390532699954SRussell King /* Even though it might look weird, when we're configured in 390632699954SRussell King * SGMII or QSGMII mode, the RGMII bit needs to be set. 390732699954SRussell King */ 390832699954SRussell King new_ctrl2 |= MVNETA_GMAC2_PORT_RGMII; 390932699954SRussell King 391032699954SRussell King if (state->interface == PHY_INTERFACE_MODE_QSGMII || 391122f4bf8aSRussell King state->interface == PHY_INTERFACE_MODE_SGMII || 391222f4bf8aSRussell King phy_interface_mode_is_8023z(state->interface)) 391332699954SRussell King new_ctrl2 |= MVNETA_GMAC2_PCS_ENABLE; 391432699954SRussell King 39154932a918SRussell King if (phylink_test(state->advertising, Pause)) 39164932a918SRussell King new_an |= MVNETA_GMAC_ADVERT_SYM_FLOW_CTRL; 39174932a918SRussell King 3918503f9aa9SRussell King if (!phylink_autoneg_inband(mode)) { 3919ff03f0b1SRussell King /* Phy or fixed speed - nothing to do, leave the 3920ff03f0b1SRussell King * configured speed, duplex and flow control as-is. 3921ff03f0b1SRussell King */ 392222f4bf8aSRussell King } else if (state->interface == PHY_INTERFACE_MODE_SGMII) { 3923503f9aa9SRussell King /* SGMII mode receives the state from the PHY */ 3924503f9aa9SRussell King new_ctrl2 |= MVNETA_GMAC2_INBAND_AN_ENABLE; 3925503f9aa9SRussell King new_clk |= MVNETA_GMAC_1MS_CLOCK_ENABLE; 3926503f9aa9SRussell King new_an = (new_an & ~(MVNETA_GMAC_FORCE_LINK_DOWN | 3927ff03f0b1SRussell King MVNETA_GMAC_FORCE_LINK_PASS | 3928ff03f0b1SRussell King MVNETA_GMAC_CONFIG_MII_SPEED | 3929ff03f0b1SRussell King MVNETA_GMAC_CONFIG_GMII_SPEED | 3930ff03f0b1SRussell King MVNETA_GMAC_CONFIG_FULL_DUPLEX)) | 3931503f9aa9SRussell King MVNETA_GMAC_INBAND_AN_ENABLE | 3932503f9aa9SRussell King MVNETA_GMAC_AN_SPEED_EN | 3933503f9aa9SRussell King MVNETA_GMAC_AN_DUPLEX_EN; 393422f4bf8aSRussell King } else { 393522f4bf8aSRussell King /* 802.3z negotiation - only 1000base-X */ 393622f4bf8aSRussell King new_ctrl0 |= MVNETA_GMAC0_PORT_1000BASE_X; 393722f4bf8aSRussell King new_clk |= MVNETA_GMAC_1MS_CLOCK_ENABLE; 393822f4bf8aSRussell King new_an = (new_an & ~(MVNETA_GMAC_FORCE_LINK_DOWN | 3939ff03f0b1SRussell King MVNETA_GMAC_FORCE_LINK_PASS | 3940ff03f0b1SRussell King MVNETA_GMAC_CONFIG_MII_SPEED)) | 394122f4bf8aSRussell King MVNETA_GMAC_INBAND_AN_ENABLE | 394222f4bf8aSRussell King MVNETA_GMAC_CONFIG_GMII_SPEED | 394322f4bf8aSRussell King /* The MAC only supports FD mode */ 394422f4bf8aSRussell King MVNETA_GMAC_CONFIG_FULL_DUPLEX; 39454932a918SRussell King 39464932a918SRussell King if (state->pause & MLO_PAUSE_AN && state->an_enabled) 39474932a918SRussell King new_an |= MVNETA_GMAC_AN_FLOW_CTRL_EN; 3948c5aff182SThomas Petazzoni } 3949c5aff182SThomas Petazzoni 3950503f9aa9SRussell King /* Armada 370 documentation says we can only change the port mode 3951503f9aa9SRussell King * and in-band enable when the link is down, so force it down 3952df4a17a9SYangyang Li * while making these changes. We also do this for GMAC_CTRL2 3953df4a17a9SYangyang Li */ 395422f4bf8aSRussell King if ((new_ctrl0 ^ gmac_ctrl0) & MVNETA_GMAC0_PORT_1000BASE_X || 395522f4bf8aSRussell King (new_ctrl2 ^ gmac_ctrl2) & MVNETA_GMAC2_INBAND_AN_ENABLE || 3956503f9aa9SRussell King (new_an ^ gmac_an) & MVNETA_GMAC_INBAND_AN_ENABLE) { 3957503f9aa9SRussell King mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, 3958503f9aa9SRussell King (gmac_an & ~MVNETA_GMAC_FORCE_LINK_PASS) | 3959503f9aa9SRussell King MVNETA_GMAC_FORCE_LINK_DOWN); 3960503f9aa9SRussell King } 3961503f9aa9SRussell King 3962a10c1c81SRussell King 3963da58a931SMaxime Chevallier /* When at 2.5G, the link partner can send frames with shortened 3964da58a931SMaxime Chevallier * preambles. 3965da58a931SMaxime Chevallier */ 3966f2ca673dSRussell King if (state->interface == PHY_INTERFACE_MODE_2500BASEX) 3967da58a931SMaxime Chevallier new_ctrl4 |= MVNETA_GMAC4_SHORT_PREAMBLE_ENABLE; 3968da58a931SMaxime Chevallier 3969b4748553SSascha Hauer if (pp->phy_interface != state->interface) { 3970b4748553SSascha Hauer if (pp->comphy) 3971031b922bSMarek Behún WARN_ON(phy_power_off(pp->comphy)); 3972b4748553SSascha Hauer WARN_ON(mvneta_config_interface(pp, state->interface)); 3973031b922bSMarek Behún } 3974a10c1c81SRussell King 397522f4bf8aSRussell King if (new_ctrl0 != gmac_ctrl0) 397622f4bf8aSRussell King mvreg_write(pp, MVNETA_GMAC_CTRL_0, new_ctrl0); 3977503f9aa9SRussell King if (new_ctrl2 != gmac_ctrl2) 3978503f9aa9SRussell King mvreg_write(pp, MVNETA_GMAC_CTRL_2, new_ctrl2); 3979da58a931SMaxime Chevallier if (new_ctrl4 != gmac_ctrl4) 3980da58a931SMaxime Chevallier mvreg_write(pp, MVNETA_GMAC_CTRL_4, new_ctrl4); 3981503f9aa9SRussell King if (new_clk != gmac_clk) 3982503f9aa9SRussell King mvreg_write(pp, MVNETA_GMAC_CLOCK_DIVIDER, new_clk); 3983503f9aa9SRussell King if (new_an != gmac_an) 3984503f9aa9SRussell King mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, new_an); 398532699954SRussell King 398632699954SRussell King if (gmac_ctrl2 & MVNETA_GMAC2_PORT_RESET) { 398732699954SRussell King while ((mvreg_read(pp, MVNETA_GMAC_CTRL_2) & 398832699954SRussell King MVNETA_GMAC2_PORT_RESET) != 0) 398932699954SRussell King continue; 399032699954SRussell King } 3991503f9aa9SRussell King } 3992503f9aa9SRussell King 39936d81f451SRussell King static void mvneta_set_eee(struct mvneta_port *pp, bool enable) 39946d81f451SRussell King { 39956d81f451SRussell King u32 lpi_ctl1; 39966d81f451SRussell King 39976d81f451SRussell King lpi_ctl1 = mvreg_read(pp, MVNETA_LPI_CTRL_1); 39986d81f451SRussell King if (enable) 39996d81f451SRussell King lpi_ctl1 |= MVNETA_LPI_REQUEST_ENABLE; 40006d81f451SRussell King else 40016d81f451SRussell King lpi_ctl1 &= ~MVNETA_LPI_REQUEST_ENABLE; 40026d81f451SRussell King mvreg_write(pp, MVNETA_LPI_CTRL_1, lpi_ctl1); 40036d81f451SRussell King } 40046d81f451SRussell King 400544cc27e4SIoana Ciornei static void mvneta_mac_link_down(struct phylink_config *config, 400644cc27e4SIoana Ciornei unsigned int mode, phy_interface_t interface) 4007fc548b99SRussell King { 400844cc27e4SIoana Ciornei struct net_device *ndev = to_net_dev(config->dev); 4009fc548b99SRussell King struct mvneta_port *pp = netdev_priv(ndev); 4010fc548b99SRussell King u32 val; 4011fc548b99SRussell King 4012503f9aa9SRussell King mvneta_port_down(pp); 4013503f9aa9SRussell King 4014503f9aa9SRussell King if (!phylink_autoneg_inband(mode)) { 4015fc548b99SRussell King val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG); 4016fc548b99SRussell King val &= ~MVNETA_GMAC_FORCE_LINK_PASS; 4017fc548b99SRussell King val |= MVNETA_GMAC_FORCE_LINK_DOWN; 4018fc548b99SRussell King mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val); 4019fc548b99SRussell King } 40206d81f451SRussell King 40216d81f451SRussell King pp->eee_active = false; 40226d81f451SRussell King mvneta_set_eee(pp, false); 4023fc548b99SRussell King } 4024fc548b99SRussell King 402591a208f2SRussell King static void mvneta_mac_link_up(struct phylink_config *config, 402691a208f2SRussell King struct phy_device *phy, 402791a208f2SRussell King unsigned int mode, phy_interface_t interface, 402891a208f2SRussell King int speed, int duplex, 402991a208f2SRussell King bool tx_pause, bool rx_pause) 4030fc548b99SRussell King { 403144cc27e4SIoana Ciornei struct net_device *ndev = to_net_dev(config->dev); 4032fc548b99SRussell King struct mvneta_port *pp = netdev_priv(ndev); 4033fc548b99SRussell King u32 val; 4034fc548b99SRussell King 4035503f9aa9SRussell King if (!phylink_autoneg_inband(mode)) { 4036fc548b99SRussell King val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG); 4037ff03f0b1SRussell King val &= ~(MVNETA_GMAC_FORCE_LINK_DOWN | 4038ff03f0b1SRussell King MVNETA_GMAC_CONFIG_MII_SPEED | 4039ff03f0b1SRussell King MVNETA_GMAC_CONFIG_GMII_SPEED | 4040ff03f0b1SRussell King MVNETA_GMAC_CONFIG_FLOW_CTRL | 4041ff03f0b1SRussell King MVNETA_GMAC_CONFIG_FULL_DUPLEX); 4042fc548b99SRussell King val |= MVNETA_GMAC_FORCE_LINK_PASS; 4043ff03f0b1SRussell King 4044ff03f0b1SRussell King if (speed == SPEED_1000 || speed == SPEED_2500) 4045ff03f0b1SRussell King val |= MVNETA_GMAC_CONFIG_GMII_SPEED; 4046ff03f0b1SRussell King else if (speed == SPEED_100) 4047ff03f0b1SRussell King val |= MVNETA_GMAC_CONFIG_MII_SPEED; 4048ff03f0b1SRussell King 4049ff03f0b1SRussell King if (duplex == DUPLEX_FULL) 4050ff03f0b1SRussell King val |= MVNETA_GMAC_CONFIG_FULL_DUPLEX; 4051ff03f0b1SRussell King 4052ff03f0b1SRussell King if (tx_pause || rx_pause) 4053ff03f0b1SRussell King val |= MVNETA_GMAC_CONFIG_FLOW_CTRL; 4054ff03f0b1SRussell King 4055ff03f0b1SRussell King mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val); 4056ff03f0b1SRussell King } else { 4057ff03f0b1SRussell King /* When inband doesn't cover flow control or flow control is 4058ff03f0b1SRussell King * disabled, we need to manually configure it. This bit will 4059ff03f0b1SRussell King * only have effect if MVNETA_GMAC_AN_FLOW_CTRL_EN is unset. 4060ff03f0b1SRussell King */ 4061ff03f0b1SRussell King val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG); 4062ff03f0b1SRussell King val &= ~MVNETA_GMAC_CONFIG_FLOW_CTRL; 4063ff03f0b1SRussell King 4064ff03f0b1SRussell King if (tx_pause || rx_pause) 4065ff03f0b1SRussell King val |= MVNETA_GMAC_CONFIG_FLOW_CTRL; 4066ff03f0b1SRussell King 4067fc548b99SRussell King mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val); 4068fc548b99SRussell King } 4069fc548b99SRussell King 4070fc548b99SRussell King mvneta_port_up(pp); 40716d81f451SRussell King 40726d81f451SRussell King if (phy && pp->eee_enabled) { 40736d81f451SRussell King pp->eee_active = phy_init_eee(phy, 0) >= 0; 40746d81f451SRussell King mvneta_set_eee(pp, pp->eee_active && pp->tx_lpi_enabled); 40756d81f451SRussell King } 4076fc548b99SRussell King } 4077fc548b99SRussell King 4078503f9aa9SRussell King static const struct phylink_mac_ops mvneta_phylink_ops = { 4079503f9aa9SRussell King .validate = mvneta_validate, 4080d46b7e4fSRussell King .mac_pcs_get_state = mvneta_mac_pcs_get_state, 408122f4bf8aSRussell King .mac_an_restart = mvneta_mac_an_restart, 4082503f9aa9SRussell King .mac_config = mvneta_mac_config, 4083503f9aa9SRussell King .mac_link_down = mvneta_mac_link_down, 4084503f9aa9SRussell King .mac_link_up = mvneta_mac_link_up, 4085503f9aa9SRussell King }; 4086c5aff182SThomas Petazzoni 4087c5aff182SThomas Petazzoni static int mvneta_mdio_probe(struct mvneta_port *pp) 4088c5aff182SThomas Petazzoni { 408982960fffSJisheng Zhang struct ethtool_wolinfo wol = { .cmd = ETHTOOL_GWOL }; 4090503f9aa9SRussell King int err = phylink_of_phy_connect(pp->phylink, pp->dn, 0); 4091c5aff182SThomas Petazzoni 4092503f9aa9SRussell King if (err) 4093503f9aa9SRussell King netdev_err(pp->dev, "could not attach PHY: %d\n", err); 4094c5aff182SThomas Petazzoni 4095503f9aa9SRussell King phylink_ethtool_get_wol(pp->phylink, &wol); 409682960fffSJisheng Zhang device_set_wakeup_capable(&pp->dev->dev, !!wol.supported); 409782960fffSJisheng Zhang 409861b5cc20SDaniel González Cabanelas /* PHY WoL may be enabled but device wakeup disabled */ 409961b5cc20SDaniel González Cabanelas if (wol.supported) 410061b5cc20SDaniel González Cabanelas device_set_wakeup_enable(&pp->dev->dev, !!wol.wolopts); 410161b5cc20SDaniel González Cabanelas 4102503f9aa9SRussell King return err; 4103c5aff182SThomas Petazzoni } 4104c5aff182SThomas Petazzoni 4105c5aff182SThomas Petazzoni static void mvneta_mdio_remove(struct mvneta_port *pp) 4106c5aff182SThomas Petazzoni { 4107503f9aa9SRussell King phylink_disconnect_phy(pp->phylink); 4108c5aff182SThomas Petazzoni } 4109c5aff182SThomas Petazzoni 4110120cfa50SGregory CLEMENT /* Electing a CPU must be done in an atomic way: it should be done 4111120cfa50SGregory CLEMENT * after or before the removal/insertion of a CPU and this function is 4112120cfa50SGregory CLEMENT * not reentrant. 4113120cfa50SGregory CLEMENT */ 4114f8642885SMaxime Ripard static void mvneta_percpu_elect(struct mvneta_port *pp) 4115f8642885SMaxime Ripard { 4116cad5d847SGregory CLEMENT int elected_cpu = 0, max_cpu, cpu, i = 0; 4117f8642885SMaxime Ripard 4118cad5d847SGregory CLEMENT /* Use the cpu associated to the rxq when it is online, in all 4119cad5d847SGregory CLEMENT * the other cases, use the cpu 0 which can't be offline. 4120cad5d847SGregory CLEMENT */ 4121cad5d847SGregory CLEMENT if (cpu_online(pp->rxq_def)) 4122cad5d847SGregory CLEMENT elected_cpu = pp->rxq_def; 4123cad5d847SGregory CLEMENT 41242dcf75e2SGregory CLEMENT max_cpu = num_present_cpus(); 4125f8642885SMaxime Ripard 4126f8642885SMaxime Ripard for_each_online_cpu(cpu) { 41272dcf75e2SGregory CLEMENT int rxq_map = 0, txq_map = 0; 41282dcf75e2SGregory CLEMENT int rxq; 41292dcf75e2SGregory CLEMENT 41302dcf75e2SGregory CLEMENT for (rxq = 0; rxq < rxq_number; rxq++) 41312dcf75e2SGregory CLEMENT if ((rxq % max_cpu) == cpu) 41322dcf75e2SGregory CLEMENT rxq_map |= MVNETA_CPU_RXQ_ACCESS(rxq); 41332dcf75e2SGregory CLEMENT 4134cad5d847SGregory CLEMENT if (cpu == elected_cpu) 4135b52f6425SYangyang Li /* Map the default receive queue to the elected CPU */ 41362dcf75e2SGregory CLEMENT rxq_map |= MVNETA_CPU_RXQ_ACCESS(pp->rxq_def); 413750bf8cb6SGregory CLEMENT 413850bf8cb6SGregory CLEMENT /* We update the TX queue map only if we have one 413950bf8cb6SGregory CLEMENT * queue. In this case we associate the TX queue to 414050bf8cb6SGregory CLEMENT * the CPU bound to the default RX queue 414150bf8cb6SGregory CLEMENT */ 414250bf8cb6SGregory CLEMENT if (txq_number == 1) 4143cad5d847SGregory CLEMENT txq_map = (cpu == elected_cpu) ? 414450bf8cb6SGregory CLEMENT MVNETA_CPU_TXQ_ACCESS(1) : 0; 414550bf8cb6SGregory CLEMENT else 414650bf8cb6SGregory CLEMENT txq_map = mvreg_read(pp, MVNETA_CPU_MAP(cpu)) & 414750bf8cb6SGregory CLEMENT MVNETA_CPU_TXQ_ACCESS_ALL_MASK; 414850bf8cb6SGregory CLEMENT 41492dcf75e2SGregory CLEMENT mvreg_write(pp, MVNETA_CPU_MAP(cpu), rxq_map | txq_map); 41502dcf75e2SGregory CLEMENT 41512dcf75e2SGregory CLEMENT /* Update the interrupt mask on each CPU according the 41522dcf75e2SGregory CLEMENT * new mapping 41532dcf75e2SGregory CLEMENT */ 41542dcf75e2SGregory CLEMENT smp_call_function_single(cpu, mvneta_percpu_unmask_interrupt, 4155f8642885SMaxime Ripard pp, true); 4156f8642885SMaxime Ripard i++; 41572dcf75e2SGregory CLEMENT 4158f8642885SMaxime Ripard } 4159f8642885SMaxime Ripard }; 4160f8642885SMaxime Ripard 416184a3f4dbSSebastian Andrzej Siewior static int mvneta_cpu_online(unsigned int cpu, struct hlist_node *node) 4162f8642885SMaxime Ripard { 416384a3f4dbSSebastian Andrzej Siewior int other_cpu; 416484a3f4dbSSebastian Andrzej Siewior struct mvneta_port *pp = hlist_entry_safe(node, struct mvneta_port, 416584a3f4dbSSebastian Andrzej Siewior node_online); 4166f8642885SMaxime Ripard struct mvneta_pcpu_port *port = per_cpu_ptr(pp->ports, cpu); 4167f8642885SMaxime Ripard 4168cf9bf871SMaxime Chevallier /* Armada 3700's per-cpu interrupt for mvneta is broken, all interrupts 4169cf9bf871SMaxime Chevallier * are routed to CPU 0, so we don't need all the cpu-hotplug support 4170cf9bf871SMaxime Chevallier */ 4171cf9bf871SMaxime Chevallier if (pp->neta_armada3700) 4172cf9bf871SMaxime Chevallier return 0; 417384a3f4dbSSebastian Andrzej Siewior 4174120cfa50SGregory CLEMENT spin_lock(&pp->lock); 417584a3f4dbSSebastian Andrzej Siewior /* 417684a3f4dbSSebastian Andrzej Siewior * Configuring the driver for a new CPU while the driver is 417784a3f4dbSSebastian Andrzej Siewior * stopping is racy, so just avoid it. 4178120cfa50SGregory CLEMENT */ 4179120cfa50SGregory CLEMENT if (pp->is_stopped) { 4180120cfa50SGregory CLEMENT spin_unlock(&pp->lock); 418184a3f4dbSSebastian Andrzej Siewior return 0; 4182120cfa50SGregory CLEMENT } 4183f8642885SMaxime Ripard netif_tx_stop_all_queues(pp->dev); 4184f8642885SMaxime Ripard 418584a3f4dbSSebastian Andrzej Siewior /* 418684a3f4dbSSebastian Andrzej Siewior * We have to synchronise on tha napi of each CPU except the one 418784a3f4dbSSebastian Andrzej Siewior * just being woken up 4188f8642885SMaxime Ripard */ 4189f8642885SMaxime Ripard for_each_online_cpu(other_cpu) { 4190f8642885SMaxime Ripard if (other_cpu != cpu) { 4191f8642885SMaxime Ripard struct mvneta_pcpu_port *other_port = 4192f8642885SMaxime Ripard per_cpu_ptr(pp->ports, other_cpu); 4193f8642885SMaxime Ripard 4194f8642885SMaxime Ripard napi_synchronize(&other_port->napi); 4195f8642885SMaxime Ripard } 4196f8642885SMaxime Ripard } 4197f8642885SMaxime Ripard 4198f8642885SMaxime Ripard /* Mask all ethernet port interrupts */ 4199db488c10SGregory CLEMENT on_each_cpu(mvneta_percpu_mask_interrupt, pp, true); 4200f8642885SMaxime Ripard napi_enable(&port->napi); 4201f8642885SMaxime Ripard 420284a3f4dbSSebastian Andrzej Siewior /* 420384a3f4dbSSebastian Andrzej Siewior * Enable per-CPU interrupts on the CPU that is 42042dcf75e2SGregory CLEMENT * brought up. 42052dcf75e2SGregory CLEMENT */ 42060e28bf93SAnna-Maria Gleixner mvneta_percpu_enable(pp); 42072dcf75e2SGregory CLEMENT 420884a3f4dbSSebastian Andrzej Siewior /* 420984a3f4dbSSebastian Andrzej Siewior * Enable per-CPU interrupt on the one CPU we care 4210f8642885SMaxime Ripard * about. 4211f8642885SMaxime Ripard */ 4212f8642885SMaxime Ripard mvneta_percpu_elect(pp); 4213f8642885SMaxime Ripard 4214db488c10SGregory CLEMENT /* Unmask all ethernet port interrupts */ 4215db488c10SGregory CLEMENT on_each_cpu(mvneta_percpu_unmask_interrupt, pp, true); 4216f8642885SMaxime Ripard mvreg_write(pp, MVNETA_INTR_MISC_MASK, 4217f8642885SMaxime Ripard MVNETA_CAUSE_PHY_STATUS_CHANGE | 4218856b2cc5SRussell King MVNETA_CAUSE_LINK_CHANGE); 4219f8642885SMaxime Ripard netif_tx_start_all_queues(pp->dev); 4220120cfa50SGregory CLEMENT spin_unlock(&pp->lock); 422184a3f4dbSSebastian Andrzej Siewior return 0; 422284a3f4dbSSebastian Andrzej Siewior } 422384a3f4dbSSebastian Andrzej Siewior 422484a3f4dbSSebastian Andrzej Siewior static int mvneta_cpu_down_prepare(unsigned int cpu, struct hlist_node *node) 422584a3f4dbSSebastian Andrzej Siewior { 422684a3f4dbSSebastian Andrzej Siewior struct mvneta_port *pp = hlist_entry_safe(node, struct mvneta_port, 422784a3f4dbSSebastian Andrzej Siewior node_online); 422884a3f4dbSSebastian Andrzej Siewior struct mvneta_pcpu_port *port = per_cpu_ptr(pp->ports, cpu); 422984a3f4dbSSebastian Andrzej Siewior 423084a3f4dbSSebastian Andrzej Siewior /* 423184a3f4dbSSebastian Andrzej Siewior * Thanks to this lock we are sure that any pending cpu election is 423284a3f4dbSSebastian Andrzej Siewior * done. 42335888511eSGregory CLEMENT */ 42345888511eSGregory CLEMENT spin_lock(&pp->lock); 4235f8642885SMaxime Ripard /* Mask all ethernet port interrupts */ 4236db488c10SGregory CLEMENT on_each_cpu(mvneta_percpu_mask_interrupt, pp, true); 42375888511eSGregory CLEMENT spin_unlock(&pp->lock); 4238f8642885SMaxime Ripard 4239f8642885SMaxime Ripard napi_synchronize(&port->napi); 4240f8642885SMaxime Ripard napi_disable(&port->napi); 424184a3f4dbSSebastian Andrzej Siewior /* Disable per-CPU interrupts on the CPU that is brought down. */ 42420e28bf93SAnna-Maria Gleixner mvneta_percpu_disable(pp); 424384a3f4dbSSebastian Andrzej Siewior return 0; 424484a3f4dbSSebastian Andrzej Siewior } 4245f8642885SMaxime Ripard 424684a3f4dbSSebastian Andrzej Siewior static int mvneta_cpu_dead(unsigned int cpu, struct hlist_node *node) 424784a3f4dbSSebastian Andrzej Siewior { 424884a3f4dbSSebastian Andrzej Siewior struct mvneta_port *pp = hlist_entry_safe(node, struct mvneta_port, 424984a3f4dbSSebastian Andrzej Siewior node_dead); 425084a3f4dbSSebastian Andrzej Siewior 4251f8642885SMaxime Ripard /* Check if a new CPU must be elected now this on is down */ 4252120cfa50SGregory CLEMENT spin_lock(&pp->lock); 4253f8642885SMaxime Ripard mvneta_percpu_elect(pp); 4254120cfa50SGregory CLEMENT spin_unlock(&pp->lock); 4255f8642885SMaxime Ripard /* Unmask all ethernet port interrupts */ 4256db488c10SGregory CLEMENT on_each_cpu(mvneta_percpu_unmask_interrupt, pp, true); 4257f8642885SMaxime Ripard mvreg_write(pp, MVNETA_INTR_MISC_MASK, 4258f8642885SMaxime Ripard MVNETA_CAUSE_PHY_STATUS_CHANGE | 4259856b2cc5SRussell King MVNETA_CAUSE_LINK_CHANGE); 4260f8642885SMaxime Ripard netif_tx_start_all_queues(pp->dev); 426184a3f4dbSSebastian Andrzej Siewior return 0; 4262f8642885SMaxime Ripard } 4263f8642885SMaxime Ripard 4264c5aff182SThomas Petazzoni static int mvneta_open(struct net_device *dev) 4265c5aff182SThomas Petazzoni { 4266c5aff182SThomas Petazzoni struct mvneta_port *pp = netdev_priv(dev); 42676b125d63SGregory CLEMENT int ret; 4268c5aff182SThomas Petazzoni 4269c5aff182SThomas Petazzoni pp->pkt_size = MVNETA_RX_PKT_SIZE(pp->dev->mtu); 4270c5aff182SThomas Petazzoni 4271c5aff182SThomas Petazzoni ret = mvneta_setup_rxqs(pp); 4272c5aff182SThomas Petazzoni if (ret) 4273c5aff182SThomas Petazzoni return ret; 4274c5aff182SThomas Petazzoni 4275c5aff182SThomas Petazzoni ret = mvneta_setup_txqs(pp); 4276c5aff182SThomas Petazzoni if (ret) 4277c5aff182SThomas Petazzoni goto err_cleanup_rxqs; 4278c5aff182SThomas Petazzoni 4279c5aff182SThomas Petazzoni /* Connect to port interrupt line */ 42802636ac3cSMarcin Wojtas if (pp->neta_armada3700) 42812636ac3cSMarcin Wojtas ret = request_irq(pp->dev->irq, mvneta_isr, 0, 42822636ac3cSMarcin Wojtas dev->name, pp); 42832636ac3cSMarcin Wojtas else 42842636ac3cSMarcin Wojtas ret = request_percpu_irq(pp->dev->irq, mvneta_percpu_isr, 42852636ac3cSMarcin Wojtas dev->name, pp->ports); 4286c5aff182SThomas Petazzoni if (ret) { 4287c5aff182SThomas Petazzoni netdev_err(pp->dev, "cannot request irq %d\n", pp->dev->irq); 4288c5aff182SThomas Petazzoni goto err_cleanup_txqs; 4289c5aff182SThomas Petazzoni } 4290c5aff182SThomas Petazzoni 42912636ac3cSMarcin Wojtas if (!pp->neta_armada3700) { 42922dcf75e2SGregory CLEMENT /* Enable per-CPU interrupt on all the CPU to handle our RX 42932dcf75e2SGregory CLEMENT * queue interrupts 42942dcf75e2SGregory CLEMENT */ 42956b125d63SGregory CLEMENT on_each_cpu(mvneta_percpu_enable, pp, true); 42962dcf75e2SGregory CLEMENT 4297120cfa50SGregory CLEMENT pp->is_stopped = false; 4298f8642885SMaxime Ripard /* Register a CPU notifier to handle the case where our CPU 4299f8642885SMaxime Ripard * might be taken offline. 4300f8642885SMaxime Ripard */ 430184a3f4dbSSebastian Andrzej Siewior ret = cpuhp_state_add_instance_nocalls(online_hpstate, 430284a3f4dbSSebastian Andrzej Siewior &pp->node_online); 430384a3f4dbSSebastian Andrzej Siewior if (ret) 430484a3f4dbSSebastian Andrzej Siewior goto err_free_irq; 430584a3f4dbSSebastian Andrzej Siewior 430684a3f4dbSSebastian Andrzej Siewior ret = cpuhp_state_add_instance_nocalls(CPUHP_NET_MVNETA_DEAD, 430784a3f4dbSSebastian Andrzej Siewior &pp->node_dead); 430884a3f4dbSSebastian Andrzej Siewior if (ret) 430984a3f4dbSSebastian Andrzej Siewior goto err_free_online_hp; 43102636ac3cSMarcin Wojtas } 4311f8642885SMaxime Ripard 4312c5aff182SThomas Petazzoni ret = mvneta_mdio_probe(pp); 4313c5aff182SThomas Petazzoni if (ret < 0) { 4314c5aff182SThomas Petazzoni netdev_err(dev, "cannot probe MDIO bus\n"); 431584a3f4dbSSebastian Andrzej Siewior goto err_free_dead_hp; 4316c5aff182SThomas Petazzoni } 4317c5aff182SThomas Petazzoni 4318c5aff182SThomas Petazzoni mvneta_start_dev(pp); 4319c5aff182SThomas Petazzoni 4320c5aff182SThomas Petazzoni return 0; 4321c5aff182SThomas Petazzoni 432284a3f4dbSSebastian Andrzej Siewior err_free_dead_hp: 43232636ac3cSMarcin Wojtas if (!pp->neta_armada3700) 432484a3f4dbSSebastian Andrzej Siewior cpuhp_state_remove_instance_nocalls(CPUHP_NET_MVNETA_DEAD, 432584a3f4dbSSebastian Andrzej Siewior &pp->node_dead); 432684a3f4dbSSebastian Andrzej Siewior err_free_online_hp: 43272636ac3cSMarcin Wojtas if (!pp->neta_armada3700) 43282636ac3cSMarcin Wojtas cpuhp_state_remove_instance_nocalls(online_hpstate, 43292636ac3cSMarcin Wojtas &pp->node_online); 4330c5aff182SThomas Petazzoni err_free_irq: 43312636ac3cSMarcin Wojtas if (pp->neta_armada3700) { 43322636ac3cSMarcin Wojtas free_irq(pp->dev->irq, pp); 43332636ac3cSMarcin Wojtas } else { 43343d8c4530SRussell King - ARM Linux on_each_cpu(mvneta_percpu_disable, pp, true); 433512bb03b4SMaxime Ripard free_percpu_irq(pp->dev->irq, pp->ports); 43362636ac3cSMarcin Wojtas } 4337c5aff182SThomas Petazzoni err_cleanup_txqs: 4338c5aff182SThomas Petazzoni mvneta_cleanup_txqs(pp); 4339c5aff182SThomas Petazzoni err_cleanup_rxqs: 4340c5aff182SThomas Petazzoni mvneta_cleanup_rxqs(pp); 4341c5aff182SThomas Petazzoni return ret; 4342c5aff182SThomas Petazzoni } 4343c5aff182SThomas Petazzoni 4344c5aff182SThomas Petazzoni /* Stop the port, free port interrupt line */ 4345c5aff182SThomas Petazzoni static int mvneta_stop(struct net_device *dev) 4346c5aff182SThomas Petazzoni { 4347c5aff182SThomas Petazzoni struct mvneta_port *pp = netdev_priv(dev); 4348c5aff182SThomas Petazzoni 43492636ac3cSMarcin Wojtas if (!pp->neta_armada3700) { 4350120cfa50SGregory CLEMENT /* Inform that we are stopping so we don't want to setup the 43511c2722a9SGregory CLEMENT * driver for new CPUs in the notifiers. The code of the 43521c2722a9SGregory CLEMENT * notifier for CPU online is protected by the same spinlock, 43531c2722a9SGregory CLEMENT * so when we get the lock, the notifer work is done. 4354120cfa50SGregory CLEMENT */ 4355120cfa50SGregory CLEMENT spin_lock(&pp->lock); 4356120cfa50SGregory CLEMENT pp->is_stopped = true; 43571c2722a9SGregory CLEMENT spin_unlock(&pp->lock); 43581c2722a9SGregory CLEMENT 4359c5aff182SThomas Petazzoni mvneta_stop_dev(pp); 4360c5aff182SThomas Petazzoni mvneta_mdio_remove(pp); 436184a3f4dbSSebastian Andrzej Siewior 4362d26aac2dSDan Carpenter cpuhp_state_remove_instance_nocalls(online_hpstate, 4363d26aac2dSDan Carpenter &pp->node_online); 436484a3f4dbSSebastian Andrzej Siewior cpuhp_state_remove_instance_nocalls(CPUHP_NET_MVNETA_DEAD, 436584a3f4dbSSebastian Andrzej Siewior &pp->node_dead); 4366129219e4SGregory CLEMENT on_each_cpu(mvneta_percpu_disable, pp, true); 436712bb03b4SMaxime Ripard free_percpu_irq(dev->irq, pp->ports); 43682636ac3cSMarcin Wojtas } else { 43692636ac3cSMarcin Wojtas mvneta_stop_dev(pp); 43702636ac3cSMarcin Wojtas mvneta_mdio_remove(pp); 43712636ac3cSMarcin Wojtas free_irq(dev->irq, pp); 43722636ac3cSMarcin Wojtas } 43732636ac3cSMarcin Wojtas 4374c5aff182SThomas Petazzoni mvneta_cleanup_rxqs(pp); 4375c5aff182SThomas Petazzoni mvneta_cleanup_txqs(pp); 4376c5aff182SThomas Petazzoni 4377c5aff182SThomas Petazzoni return 0; 4378c5aff182SThomas Petazzoni } 4379c5aff182SThomas Petazzoni 438015f59456SThomas Petazzoni static int mvneta_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) 438115f59456SThomas Petazzoni { 4382503f9aa9SRussell King struct mvneta_port *pp = netdev_priv(dev); 438315f59456SThomas Petazzoni 4384503f9aa9SRussell King return phylink_mii_ioctl(pp->phylink, ifr, cmd); 438515f59456SThomas Petazzoni } 438615f59456SThomas Petazzoni 43870db51da7SLorenzo Bianconi static int mvneta_xdp_setup(struct net_device *dev, struct bpf_prog *prog, 43880db51da7SLorenzo Bianconi struct netlink_ext_ack *extack) 43890db51da7SLorenzo Bianconi { 43900db51da7SLorenzo Bianconi bool need_update, running = netif_running(dev); 43910db51da7SLorenzo Bianconi struct mvneta_port *pp = netdev_priv(dev); 43920db51da7SLorenzo Bianconi struct bpf_prog *old_prog; 43930db51da7SLorenzo Bianconi 43940db51da7SLorenzo Bianconi if (prog && dev->mtu > MVNETA_MAX_RX_BUF_SIZE) { 43950d136f5cSMarek Behún NL_SET_ERR_MSG_MOD(extack, "MTU too large for XDP"); 43960db51da7SLorenzo Bianconi return -EOPNOTSUPP; 43970db51da7SLorenzo Bianconi } 43980db51da7SLorenzo Bianconi 439979572c98SSven Auhagen if (pp->bm_priv) { 440079572c98SSven Auhagen NL_SET_ERR_MSG_MOD(extack, 440179572c98SSven Auhagen "Hardware Buffer Management not supported on XDP"); 440279572c98SSven Auhagen return -EOPNOTSUPP; 440379572c98SSven Auhagen } 440479572c98SSven Auhagen 44050db51da7SLorenzo Bianconi need_update = !!pp->xdp_prog != !!prog; 44060db51da7SLorenzo Bianconi if (running && need_update) 44070db51da7SLorenzo Bianconi mvneta_stop(dev); 44080db51da7SLorenzo Bianconi 44090db51da7SLorenzo Bianconi old_prog = xchg(&pp->xdp_prog, prog); 44100db51da7SLorenzo Bianconi if (old_prog) 44110db51da7SLorenzo Bianconi bpf_prog_put(old_prog); 44120db51da7SLorenzo Bianconi 44130db51da7SLorenzo Bianconi if (running && need_update) 44140db51da7SLorenzo Bianconi return mvneta_open(dev); 44150db51da7SLorenzo Bianconi 44160db51da7SLorenzo Bianconi return 0; 44170db51da7SLorenzo Bianconi } 44180db51da7SLorenzo Bianconi 44190db51da7SLorenzo Bianconi static int mvneta_xdp(struct net_device *dev, struct netdev_bpf *xdp) 44200db51da7SLorenzo Bianconi { 44210db51da7SLorenzo Bianconi switch (xdp->command) { 44220db51da7SLorenzo Bianconi case XDP_SETUP_PROG: 44230db51da7SLorenzo Bianconi return mvneta_xdp_setup(dev, xdp->prog, xdp->extack); 44240db51da7SLorenzo Bianconi default: 44250db51da7SLorenzo Bianconi return -EINVAL; 44260db51da7SLorenzo Bianconi } 44270db51da7SLorenzo Bianconi } 44280db51da7SLorenzo Bianconi 4429c5aff182SThomas Petazzoni /* Ethtool methods */ 4430c5aff182SThomas Petazzoni 4431013ad40dSPhilippe Reynes /* Set link ksettings (phy address, speed) for ethtools */ 44322dc0d2b4SBaoyou Xie static int 44332dc0d2b4SBaoyou Xie mvneta_ethtool_set_link_ksettings(struct net_device *ndev, 4434013ad40dSPhilippe Reynes const struct ethtool_link_ksettings *cmd) 4435c5aff182SThomas Petazzoni { 4436013ad40dSPhilippe Reynes struct mvneta_port *pp = netdev_priv(ndev); 4437c5aff182SThomas Petazzoni 4438503f9aa9SRussell King return phylink_ethtool_ksettings_set(pp->phylink, cmd); 44390c0744fcSStas Sergeev } 44400c0744fcSStas Sergeev 4441503f9aa9SRussell King /* Get link ksettings for ethtools */ 4442503f9aa9SRussell King static int 4443503f9aa9SRussell King mvneta_ethtool_get_link_ksettings(struct net_device *ndev, 4444503f9aa9SRussell King struct ethtool_link_ksettings *cmd) 4445503f9aa9SRussell King { 4446503f9aa9SRussell King struct mvneta_port *pp = netdev_priv(ndev); 44470c0744fcSStas Sergeev 4448503f9aa9SRussell King return phylink_ethtool_ksettings_get(pp->phylink, cmd); 44490c0744fcSStas Sergeev } 44500c0744fcSStas Sergeev 4451503f9aa9SRussell King static int mvneta_ethtool_nway_reset(struct net_device *dev) 4452503f9aa9SRussell King { 4453503f9aa9SRussell King struct mvneta_port *pp = netdev_priv(dev); 4454503f9aa9SRussell King 4455503f9aa9SRussell King return phylink_ethtool_nway_reset(pp->phylink); 4456c5aff182SThomas Petazzoni } 4457c5aff182SThomas Petazzoni 4458c5aff182SThomas Petazzoni /* Set interrupt coalescing for ethtools */ 4459f3ccfda1SYufeng Mo static int 4460f3ccfda1SYufeng Mo mvneta_ethtool_set_coalesce(struct net_device *dev, 4461f3ccfda1SYufeng Mo struct ethtool_coalesce *c, 4462f3ccfda1SYufeng Mo struct kernel_ethtool_coalesce *kernel_coal, 4463f3ccfda1SYufeng Mo struct netlink_ext_ack *extack) 4464c5aff182SThomas Petazzoni { 4465c5aff182SThomas Petazzoni struct mvneta_port *pp = netdev_priv(dev); 4466c5aff182SThomas Petazzoni int queue; 4467c5aff182SThomas Petazzoni 4468c5aff182SThomas Petazzoni for (queue = 0; queue < rxq_number; queue++) { 4469c5aff182SThomas Petazzoni struct mvneta_rx_queue *rxq = &pp->rxqs[queue]; 4470c5aff182SThomas Petazzoni rxq->time_coal = c->rx_coalesce_usecs; 4471c5aff182SThomas Petazzoni rxq->pkts_coal = c->rx_max_coalesced_frames; 4472c5aff182SThomas Petazzoni mvneta_rx_pkts_coal_set(pp, rxq, rxq->pkts_coal); 4473c5aff182SThomas Petazzoni mvneta_rx_time_coal_set(pp, rxq, rxq->time_coal); 4474c5aff182SThomas Petazzoni } 4475c5aff182SThomas Petazzoni 4476c5aff182SThomas Petazzoni for (queue = 0; queue < txq_number; queue++) { 4477c5aff182SThomas Petazzoni struct mvneta_tx_queue *txq = &pp->txqs[queue]; 4478c5aff182SThomas Petazzoni txq->done_pkts_coal = c->tx_max_coalesced_frames; 4479c5aff182SThomas Petazzoni mvneta_tx_done_pkts_coal_set(pp, txq, txq->done_pkts_coal); 4480c5aff182SThomas Petazzoni } 4481c5aff182SThomas Petazzoni 4482c5aff182SThomas Petazzoni return 0; 4483c5aff182SThomas Petazzoni } 4484c5aff182SThomas Petazzoni 4485c5aff182SThomas Petazzoni /* get coalescing for ethtools */ 4486f3ccfda1SYufeng Mo static int 4487f3ccfda1SYufeng Mo mvneta_ethtool_get_coalesce(struct net_device *dev, 4488f3ccfda1SYufeng Mo struct ethtool_coalesce *c, 4489f3ccfda1SYufeng Mo struct kernel_ethtool_coalesce *kernel_coal, 4490f3ccfda1SYufeng Mo struct netlink_ext_ack *extack) 4491c5aff182SThomas Petazzoni { 4492c5aff182SThomas Petazzoni struct mvneta_port *pp = netdev_priv(dev); 4493c5aff182SThomas Petazzoni 4494c5aff182SThomas Petazzoni c->rx_coalesce_usecs = pp->rxqs[0].time_coal; 4495c5aff182SThomas Petazzoni c->rx_max_coalesced_frames = pp->rxqs[0].pkts_coal; 4496c5aff182SThomas Petazzoni 4497c5aff182SThomas Petazzoni c->tx_max_coalesced_frames = pp->txqs[0].done_pkts_coal; 4498c5aff182SThomas Petazzoni return 0; 4499c5aff182SThomas Petazzoni } 4500c5aff182SThomas Petazzoni 4501c5aff182SThomas Petazzoni 4502c5aff182SThomas Petazzoni static void mvneta_ethtool_get_drvinfo(struct net_device *dev, 4503c5aff182SThomas Petazzoni struct ethtool_drvinfo *drvinfo) 4504c5aff182SThomas Petazzoni { 4505c5aff182SThomas Petazzoni strlcpy(drvinfo->driver, MVNETA_DRIVER_NAME, 4506c5aff182SThomas Petazzoni sizeof(drvinfo->driver)); 4507c5aff182SThomas Petazzoni strlcpy(drvinfo->version, MVNETA_DRIVER_VERSION, 4508c5aff182SThomas Petazzoni sizeof(drvinfo->version)); 4509c5aff182SThomas Petazzoni strlcpy(drvinfo->bus_info, dev_name(&dev->dev), 4510c5aff182SThomas Petazzoni sizeof(drvinfo->bus_info)); 4511c5aff182SThomas Petazzoni } 4512c5aff182SThomas Petazzoni 4513c5aff182SThomas Petazzoni 451474624944SHao Chen static void 451574624944SHao Chen mvneta_ethtool_get_ringparam(struct net_device *netdev, 451674624944SHao Chen struct ethtool_ringparam *ring, 451774624944SHao Chen struct kernel_ethtool_ringparam *kernel_ring, 451874624944SHao Chen struct netlink_ext_ack *extack) 4519c5aff182SThomas Petazzoni { 4520c5aff182SThomas Petazzoni struct mvneta_port *pp = netdev_priv(netdev); 4521c5aff182SThomas Petazzoni 4522c5aff182SThomas Petazzoni ring->rx_max_pending = MVNETA_MAX_RXD; 4523c5aff182SThomas Petazzoni ring->tx_max_pending = MVNETA_MAX_TXD; 4524c5aff182SThomas Petazzoni ring->rx_pending = pp->rx_ring_size; 4525c5aff182SThomas Petazzoni ring->tx_pending = pp->tx_ring_size; 4526c5aff182SThomas Petazzoni } 4527c5aff182SThomas Petazzoni 452874624944SHao Chen static int 452974624944SHao Chen mvneta_ethtool_set_ringparam(struct net_device *dev, 453074624944SHao Chen struct ethtool_ringparam *ring, 453174624944SHao Chen struct kernel_ethtool_ringparam *kernel_ring, 453274624944SHao Chen struct netlink_ext_ack *extack) 4533c5aff182SThomas Petazzoni { 4534c5aff182SThomas Petazzoni struct mvneta_port *pp = netdev_priv(dev); 4535c5aff182SThomas Petazzoni 4536c5aff182SThomas Petazzoni if ((ring->rx_pending == 0) || (ring->tx_pending == 0)) 4537c5aff182SThomas Petazzoni return -EINVAL; 4538c5aff182SThomas Petazzoni pp->rx_ring_size = ring->rx_pending < MVNETA_MAX_RXD ? 4539c5aff182SThomas Petazzoni ring->rx_pending : MVNETA_MAX_RXD; 45408eef5f97SEzequiel Garcia 45418eef5f97SEzequiel Garcia pp->tx_ring_size = clamp_t(u16, ring->tx_pending, 45428eef5f97SEzequiel Garcia MVNETA_MAX_SKB_DESCS * 2, MVNETA_MAX_TXD); 45438eef5f97SEzequiel Garcia if (pp->tx_ring_size != ring->tx_pending) 45448eef5f97SEzequiel Garcia netdev_warn(dev, "TX queue size set to %u (requested %u)\n", 45458eef5f97SEzequiel Garcia pp->tx_ring_size, ring->tx_pending); 4546c5aff182SThomas Petazzoni 4547c5aff182SThomas Petazzoni if (netif_running(dev)) { 4548c5aff182SThomas Petazzoni mvneta_stop(dev); 4549c5aff182SThomas Petazzoni if (mvneta_open(dev)) { 4550c5aff182SThomas Petazzoni netdev_err(dev, 4551c5aff182SThomas Petazzoni "error on opening device after ring param change\n"); 4552c5aff182SThomas Petazzoni return -ENOMEM; 4553c5aff182SThomas Petazzoni } 4554c5aff182SThomas Petazzoni } 4555c5aff182SThomas Petazzoni 4556c5aff182SThomas Petazzoni return 0; 4557c5aff182SThomas Petazzoni } 4558c5aff182SThomas Petazzoni 45594932a918SRussell King static void mvneta_ethtool_get_pauseparam(struct net_device *dev, 45604932a918SRussell King struct ethtool_pauseparam *pause) 45614932a918SRussell King { 45624932a918SRussell King struct mvneta_port *pp = netdev_priv(dev); 45634932a918SRussell King 45644932a918SRussell King phylink_ethtool_get_pauseparam(pp->phylink, pause); 45654932a918SRussell King } 45664932a918SRussell King 45674932a918SRussell King static int mvneta_ethtool_set_pauseparam(struct net_device *dev, 45684932a918SRussell King struct ethtool_pauseparam *pause) 45694932a918SRussell King { 45704932a918SRussell King struct mvneta_port *pp = netdev_priv(dev); 45714932a918SRussell King 45724932a918SRussell King return phylink_ethtool_set_pauseparam(pp->phylink, pause); 45734932a918SRussell King } 45744932a918SRussell King 45759b0cdefaSRussell King static void mvneta_ethtool_get_strings(struct net_device *netdev, u32 sset, 45769b0cdefaSRussell King u8 *data) 45779b0cdefaSRussell King { 45789b0cdefaSRussell King if (sset == ETH_SS_STATS) { 45799b0cdefaSRussell King int i; 45809b0cdefaSRussell King 45819b0cdefaSRussell King for (i = 0; i < ARRAY_SIZE(mvneta_statistics); i++) 45829b0cdefaSRussell King memcpy(data + i * ETH_GSTRING_LEN, 45839b0cdefaSRussell King mvneta_statistics[i].name, ETH_GSTRING_LEN); 45849b0cdefaSRussell King } 45859b0cdefaSRussell King } 45869b0cdefaSRussell King 45879ac41f3cSLorenzo Bianconi static void 45889ac41f3cSLorenzo Bianconi mvneta_ethtool_update_pcpu_stats(struct mvneta_port *pp, 45899ac41f3cSLorenzo Bianconi struct mvneta_ethtool_stats *es) 45909ac41f3cSLorenzo Bianconi { 45919ac41f3cSLorenzo Bianconi unsigned int start; 45929ac41f3cSLorenzo Bianconi int cpu; 45939ac41f3cSLorenzo Bianconi 45949ac41f3cSLorenzo Bianconi for_each_possible_cpu(cpu) { 45959ac41f3cSLorenzo Bianconi struct mvneta_pcpu_stats *stats; 45969ac41f3cSLorenzo Bianconi u64 skb_alloc_error; 45979ac41f3cSLorenzo Bianconi u64 refill_error; 45983d866523SLorenzo Bianconi u64 xdp_redirect; 459915070919SJesper Dangaard Brouer u64 xdp_xmit_err; 460015070919SJesper Dangaard Brouer u64 xdp_tx_err; 46013d866523SLorenzo Bianconi u64 xdp_pass; 46023d866523SLorenzo Bianconi u64 xdp_drop; 46037d51a015SLorenzo Bianconi u64 xdp_xmit; 46043d866523SLorenzo Bianconi u64 xdp_tx; 46059ac41f3cSLorenzo Bianconi 46069ac41f3cSLorenzo Bianconi stats = per_cpu_ptr(pp->stats, cpu); 46079ac41f3cSLorenzo Bianconi do { 46089ac41f3cSLorenzo Bianconi start = u64_stats_fetch_begin_irq(&stats->syncp); 46099ac41f3cSLorenzo Bianconi skb_alloc_error = stats->es.skb_alloc_error; 46109ac41f3cSLorenzo Bianconi refill_error = stats->es.refill_error; 46113d866523SLorenzo Bianconi xdp_redirect = stats->es.ps.xdp_redirect; 46123d866523SLorenzo Bianconi xdp_pass = stats->es.ps.xdp_pass; 46133d866523SLorenzo Bianconi xdp_drop = stats->es.ps.xdp_drop; 46147d51a015SLorenzo Bianconi xdp_xmit = stats->es.ps.xdp_xmit; 461515070919SJesper Dangaard Brouer xdp_xmit_err = stats->es.ps.xdp_xmit_err; 46163d866523SLorenzo Bianconi xdp_tx = stats->es.ps.xdp_tx; 461715070919SJesper Dangaard Brouer xdp_tx_err = stats->es.ps.xdp_tx_err; 46189ac41f3cSLorenzo Bianconi } while (u64_stats_fetch_retry_irq(&stats->syncp, start)); 46199ac41f3cSLorenzo Bianconi 46209ac41f3cSLorenzo Bianconi es->skb_alloc_error += skb_alloc_error; 46219ac41f3cSLorenzo Bianconi es->refill_error += refill_error; 46223d866523SLorenzo Bianconi es->ps.xdp_redirect += xdp_redirect; 46233d866523SLorenzo Bianconi es->ps.xdp_pass += xdp_pass; 46243d866523SLorenzo Bianconi es->ps.xdp_drop += xdp_drop; 46257d51a015SLorenzo Bianconi es->ps.xdp_xmit += xdp_xmit; 462615070919SJesper Dangaard Brouer es->ps.xdp_xmit_err += xdp_xmit_err; 46273d866523SLorenzo Bianconi es->ps.xdp_tx += xdp_tx; 462815070919SJesper Dangaard Brouer es->ps.xdp_tx_err += xdp_tx_err; 46299ac41f3cSLorenzo Bianconi } 46309ac41f3cSLorenzo Bianconi } 46319ac41f3cSLorenzo Bianconi 46329b0cdefaSRussell King static void mvneta_ethtool_update_stats(struct mvneta_port *pp) 46339b0cdefaSRussell King { 46349ac41f3cSLorenzo Bianconi struct mvneta_ethtool_stats stats = {}; 46359b0cdefaSRussell King const struct mvneta_statistic *s; 46369b0cdefaSRussell King void __iomem *base = pp->base; 46376d81f451SRussell King u32 high, low; 46386d81f451SRussell King u64 val; 46399b0cdefaSRussell King int i; 46409b0cdefaSRussell King 46419ac41f3cSLorenzo Bianconi mvneta_ethtool_update_pcpu_stats(pp, &stats); 46429b0cdefaSRussell King for (i = 0, s = mvneta_statistics; 46439b0cdefaSRussell King s < mvneta_statistics + ARRAY_SIZE(mvneta_statistics); 46449b0cdefaSRussell King s++, i++) { 46459b0cdefaSRussell King switch (s->type) { 46469b0cdefaSRussell King case T_REG_32: 46479b0cdefaSRussell King val = readl_relaxed(base + s->offset); 46489ac41f3cSLorenzo Bianconi pp->ethtool_stats[i] += val; 46499b0cdefaSRussell King break; 46509b0cdefaSRussell King case T_REG_64: 46519b0cdefaSRussell King /* Docs say to read low 32-bit then high */ 46529b0cdefaSRussell King low = readl_relaxed(base + s->offset); 46539b0cdefaSRussell King high = readl_relaxed(base + s->offset + 4); 46546d81f451SRussell King val = (u64)high << 32 | low; 46559ac41f3cSLorenzo Bianconi pp->ethtool_stats[i] += val; 46566d81f451SRussell King break; 46576d81f451SRussell King case T_SW: 46586d81f451SRussell King switch (s->offset) { 46596d81f451SRussell King case ETHTOOL_STAT_EEE_WAKEUP: 46606d81f451SRussell King val = phylink_get_eee_err(pp->phylink); 46619ac41f3cSLorenzo Bianconi pp->ethtool_stats[i] += val; 46629b0cdefaSRussell King break; 466317a96da6SGregory CLEMENT case ETHTOOL_STAT_SKB_ALLOC_ERR: 46649ac41f3cSLorenzo Bianconi pp->ethtool_stats[i] = stats.skb_alloc_error; 466517a96da6SGregory CLEMENT break; 466617a96da6SGregory CLEMENT case ETHTOOL_STAT_REFILL_ERR: 46679ac41f3cSLorenzo Bianconi pp->ethtool_stats[i] = stats.refill_error; 466817a96da6SGregory CLEMENT break; 46693d866523SLorenzo Bianconi case ETHTOOL_XDP_REDIRECT: 46703d866523SLorenzo Bianconi pp->ethtool_stats[i] = stats.ps.xdp_redirect; 46713d866523SLorenzo Bianconi break; 46723d866523SLorenzo Bianconi case ETHTOOL_XDP_PASS: 46733d866523SLorenzo Bianconi pp->ethtool_stats[i] = stats.ps.xdp_pass; 46743d866523SLorenzo Bianconi break; 46753d866523SLorenzo Bianconi case ETHTOOL_XDP_DROP: 46763d866523SLorenzo Bianconi pp->ethtool_stats[i] = stats.ps.xdp_drop; 46773d866523SLorenzo Bianconi break; 46783d866523SLorenzo Bianconi case ETHTOOL_XDP_TX: 46793d866523SLorenzo Bianconi pp->ethtool_stats[i] = stats.ps.xdp_tx; 46803d866523SLorenzo Bianconi break; 468115070919SJesper Dangaard Brouer case ETHTOOL_XDP_TX_ERR: 468215070919SJesper Dangaard Brouer pp->ethtool_stats[i] = stats.ps.xdp_tx_err; 468315070919SJesper Dangaard Brouer break; 46847d51a015SLorenzo Bianconi case ETHTOOL_XDP_XMIT: 46857d51a015SLorenzo Bianconi pp->ethtool_stats[i] = stats.ps.xdp_xmit; 46867d51a015SLorenzo Bianconi break; 468715070919SJesper Dangaard Brouer case ETHTOOL_XDP_XMIT_ERR: 468815070919SJesper Dangaard Brouer pp->ethtool_stats[i] = stats.ps.xdp_xmit_err; 468915070919SJesper Dangaard Brouer break; 46909b0cdefaSRussell King } 46916d81f451SRussell King break; 46926d81f451SRussell King } 46939b0cdefaSRussell King } 46949b0cdefaSRussell King } 46959b0cdefaSRussell King 46969b0cdefaSRussell King static void mvneta_ethtool_get_stats(struct net_device *dev, 46979b0cdefaSRussell King struct ethtool_stats *stats, u64 *data) 46989b0cdefaSRussell King { 46999b0cdefaSRussell King struct mvneta_port *pp = netdev_priv(dev); 47009b0cdefaSRussell King int i; 47019b0cdefaSRussell King 47029b0cdefaSRussell King mvneta_ethtool_update_stats(pp); 47039b0cdefaSRussell King 47049b0cdefaSRussell King for (i = 0; i < ARRAY_SIZE(mvneta_statistics); i++) 47059b0cdefaSRussell King *data++ = pp->ethtool_stats[i]; 47069b0cdefaSRussell King } 47079b0cdefaSRussell King 47089b0cdefaSRussell King static int mvneta_ethtool_get_sset_count(struct net_device *dev, int sset) 47099b0cdefaSRussell King { 47109b0cdefaSRussell King if (sset == ETH_SS_STATS) 47119b0cdefaSRussell King return ARRAY_SIZE(mvneta_statistics); 47129b0cdefaSRussell King return -EOPNOTSUPP; 47139b0cdefaSRussell King } 47149b0cdefaSRussell King 47159a401deaSGregory CLEMENT static u32 mvneta_ethtool_get_rxfh_indir_size(struct net_device *dev) 47169a401deaSGregory CLEMENT { 47179a401deaSGregory CLEMENT return MVNETA_RSS_LU_TABLE_SIZE; 47189a401deaSGregory CLEMENT } 47199a401deaSGregory CLEMENT 47209a401deaSGregory CLEMENT static int mvneta_ethtool_get_rxnfc(struct net_device *dev, 47219a401deaSGregory CLEMENT struct ethtool_rxnfc *info, 47229a401deaSGregory CLEMENT u32 *rules __always_unused) 47239a401deaSGregory CLEMENT { 47249a401deaSGregory CLEMENT switch (info->cmd) { 47259a401deaSGregory CLEMENT case ETHTOOL_GRXRINGS: 47269a401deaSGregory CLEMENT info->data = rxq_number; 47279a401deaSGregory CLEMENT return 0; 47289a401deaSGregory CLEMENT case ETHTOOL_GRXFH: 47299a401deaSGregory CLEMENT return -EOPNOTSUPP; 47309a401deaSGregory CLEMENT default: 47319a401deaSGregory CLEMENT return -EOPNOTSUPP; 47329a401deaSGregory CLEMENT } 47339a401deaSGregory CLEMENT } 47349a401deaSGregory CLEMENT 47359a401deaSGregory CLEMENT static int mvneta_config_rss(struct mvneta_port *pp) 47369a401deaSGregory CLEMENT { 47379a401deaSGregory CLEMENT int cpu; 47389a401deaSGregory CLEMENT u32 val; 47399a401deaSGregory CLEMENT 47409a401deaSGregory CLEMENT netif_tx_stop_all_queues(pp->dev); 47419a401deaSGregory CLEMENT 47426b125d63SGregory CLEMENT on_each_cpu(mvneta_percpu_mask_interrupt, pp, true); 47439a401deaSGregory CLEMENT 47440f5c6c30SJisheng Zhang if (!pp->neta_armada3700) { 47459a401deaSGregory CLEMENT /* We have to synchronise on the napi of each CPU */ 47469a401deaSGregory CLEMENT for_each_online_cpu(cpu) { 47479a401deaSGregory CLEMENT struct mvneta_pcpu_port *pcpu_port = 47489a401deaSGregory CLEMENT per_cpu_ptr(pp->ports, cpu); 47499a401deaSGregory CLEMENT 47509a401deaSGregory CLEMENT napi_synchronize(&pcpu_port->napi); 47519a401deaSGregory CLEMENT napi_disable(&pcpu_port->napi); 47529a401deaSGregory CLEMENT } 47530f5c6c30SJisheng Zhang } else { 47540f5c6c30SJisheng Zhang napi_synchronize(&pp->napi); 47550f5c6c30SJisheng Zhang napi_disable(&pp->napi); 47560f5c6c30SJisheng Zhang } 47579a401deaSGregory CLEMENT 47589a401deaSGregory CLEMENT pp->rxq_def = pp->indir[0]; 47599a401deaSGregory CLEMENT 47609a401deaSGregory CLEMENT /* Update unicast mapping */ 47619a401deaSGregory CLEMENT mvneta_set_rx_mode(pp->dev); 47629a401deaSGregory CLEMENT 47639a401deaSGregory CLEMENT /* Update val of portCfg register accordingly with all RxQueue types */ 47649a401deaSGregory CLEMENT val = MVNETA_PORT_CONFIG_DEFL_VALUE(pp->rxq_def); 47659a401deaSGregory CLEMENT mvreg_write(pp, MVNETA_PORT_CONFIG, val); 47669a401deaSGregory CLEMENT 47679a401deaSGregory CLEMENT /* Update the elected CPU matching the new rxq_def */ 4768120cfa50SGregory CLEMENT spin_lock(&pp->lock); 47699a401deaSGregory CLEMENT mvneta_percpu_elect(pp); 4770120cfa50SGregory CLEMENT spin_unlock(&pp->lock); 47719a401deaSGregory CLEMENT 47720f5c6c30SJisheng Zhang if (!pp->neta_armada3700) { 47739a401deaSGregory CLEMENT /* We have to synchronise on the napi of each CPU */ 47749a401deaSGregory CLEMENT for_each_online_cpu(cpu) { 47759a401deaSGregory CLEMENT struct mvneta_pcpu_port *pcpu_port = 47769a401deaSGregory CLEMENT per_cpu_ptr(pp->ports, cpu); 47779a401deaSGregory CLEMENT 47789a401deaSGregory CLEMENT napi_enable(&pcpu_port->napi); 47799a401deaSGregory CLEMENT } 47800f5c6c30SJisheng Zhang } else { 47810f5c6c30SJisheng Zhang napi_enable(&pp->napi); 47820f5c6c30SJisheng Zhang } 47839a401deaSGregory CLEMENT 47849a401deaSGregory CLEMENT netif_tx_start_all_queues(pp->dev); 47859a401deaSGregory CLEMENT 47869a401deaSGregory CLEMENT return 0; 47879a401deaSGregory CLEMENT } 47889a401deaSGregory CLEMENT 47899a401deaSGregory CLEMENT static int mvneta_ethtool_set_rxfh(struct net_device *dev, const u32 *indir, 47909a401deaSGregory CLEMENT const u8 *key, const u8 hfunc) 47919a401deaSGregory CLEMENT { 47929a401deaSGregory CLEMENT struct mvneta_port *pp = netdev_priv(dev); 47932636ac3cSMarcin Wojtas 47942636ac3cSMarcin Wojtas /* Current code for Armada 3700 doesn't support RSS features yet */ 47952636ac3cSMarcin Wojtas if (pp->neta_armada3700) 47962636ac3cSMarcin Wojtas return -EOPNOTSUPP; 47972636ac3cSMarcin Wojtas 47989a401deaSGregory CLEMENT /* We require at least one supported parameter to be changed 47999a401deaSGregory CLEMENT * and no change in any of the unsupported parameters 48009a401deaSGregory CLEMENT */ 48019a401deaSGregory CLEMENT if (key || 48029a401deaSGregory CLEMENT (hfunc != ETH_RSS_HASH_NO_CHANGE && hfunc != ETH_RSS_HASH_TOP)) 48039a401deaSGregory CLEMENT return -EOPNOTSUPP; 48049a401deaSGregory CLEMENT 48059a401deaSGregory CLEMENT if (!indir) 48069a401deaSGregory CLEMENT return 0; 48079a401deaSGregory CLEMENT 48089a401deaSGregory CLEMENT memcpy(pp->indir, indir, MVNETA_RSS_LU_TABLE_SIZE); 48099a401deaSGregory CLEMENT 48109a401deaSGregory CLEMENT return mvneta_config_rss(pp); 48119a401deaSGregory CLEMENT } 48129a401deaSGregory CLEMENT 48139a401deaSGregory CLEMENT static int mvneta_ethtool_get_rxfh(struct net_device *dev, u32 *indir, u8 *key, 48149a401deaSGregory CLEMENT u8 *hfunc) 48159a401deaSGregory CLEMENT { 48169a401deaSGregory CLEMENT struct mvneta_port *pp = netdev_priv(dev); 48179a401deaSGregory CLEMENT 48182636ac3cSMarcin Wojtas /* Current code for Armada 3700 doesn't support RSS features yet */ 48192636ac3cSMarcin Wojtas if (pp->neta_armada3700) 48202636ac3cSMarcin Wojtas return -EOPNOTSUPP; 48212636ac3cSMarcin Wojtas 48229a401deaSGregory CLEMENT if (hfunc) 48239a401deaSGregory CLEMENT *hfunc = ETH_RSS_HASH_TOP; 48249a401deaSGregory CLEMENT 48259a401deaSGregory CLEMENT if (!indir) 48269a401deaSGregory CLEMENT return 0; 48279a401deaSGregory CLEMENT 48289a401deaSGregory CLEMENT memcpy(indir, pp->indir, MVNETA_RSS_LU_TABLE_SIZE); 48299a401deaSGregory CLEMENT 48309a401deaSGregory CLEMENT return 0; 48319a401deaSGregory CLEMENT } 48329a401deaSGregory CLEMENT 4833b60a00f9SJingju Hou static void mvneta_ethtool_get_wol(struct net_device *dev, 4834b60a00f9SJingju Hou struct ethtool_wolinfo *wol) 4835b60a00f9SJingju Hou { 4836503f9aa9SRussell King struct mvneta_port *pp = netdev_priv(dev); 4837b60a00f9SJingju Hou 4838503f9aa9SRussell King phylink_ethtool_get_wol(pp->phylink, wol); 4839b60a00f9SJingju Hou } 4840b60a00f9SJingju Hou 4841b60a00f9SJingju Hou static int mvneta_ethtool_set_wol(struct net_device *dev, 4842b60a00f9SJingju Hou struct ethtool_wolinfo *wol) 4843b60a00f9SJingju Hou { 4844503f9aa9SRussell King struct mvneta_port *pp = netdev_priv(dev); 484582960fffSJisheng Zhang int ret; 484682960fffSJisheng Zhang 4847503f9aa9SRussell King ret = phylink_ethtool_set_wol(pp->phylink, wol); 484882960fffSJisheng Zhang if (!ret) 484982960fffSJisheng Zhang device_set_wakeup_enable(&dev->dev, !!wol->wolopts); 485082960fffSJisheng Zhang 485182960fffSJisheng Zhang return ret; 4852b60a00f9SJingju Hou } 4853b60a00f9SJingju Hou 48546d81f451SRussell King static int mvneta_ethtool_get_eee(struct net_device *dev, 48556d81f451SRussell King struct ethtool_eee *eee) 48566d81f451SRussell King { 48576d81f451SRussell King struct mvneta_port *pp = netdev_priv(dev); 48586d81f451SRussell King u32 lpi_ctl0; 48596d81f451SRussell King 48606d81f451SRussell King lpi_ctl0 = mvreg_read(pp, MVNETA_LPI_CTRL_0); 48616d81f451SRussell King 48626d81f451SRussell King eee->eee_enabled = pp->eee_enabled; 48636d81f451SRussell King eee->eee_active = pp->eee_active; 48646d81f451SRussell King eee->tx_lpi_enabled = pp->tx_lpi_enabled; 48656d81f451SRussell King eee->tx_lpi_timer = (lpi_ctl0) >> 8; // * scale; 48666d81f451SRussell King 48676d81f451SRussell King return phylink_ethtool_get_eee(pp->phylink, eee); 48686d81f451SRussell King } 48696d81f451SRussell King 48706d81f451SRussell King static int mvneta_ethtool_set_eee(struct net_device *dev, 48716d81f451SRussell King struct ethtool_eee *eee) 48726d81f451SRussell King { 48736d81f451SRussell King struct mvneta_port *pp = netdev_priv(dev); 48746d81f451SRussell King u32 lpi_ctl0; 48756d81f451SRussell King 48766d81f451SRussell King /* The Armada 37x documents do not give limits for this other than 4877df4a17a9SYangyang Li * it being an 8-bit register. 4878df4a17a9SYangyang Li */ 4879e4a3e9ffSYueHaibing if (eee->tx_lpi_enabled && eee->tx_lpi_timer > 255) 48806d81f451SRussell King return -EINVAL; 48816d81f451SRussell King 48826d81f451SRussell King lpi_ctl0 = mvreg_read(pp, MVNETA_LPI_CTRL_0); 48836d81f451SRussell King lpi_ctl0 &= ~(0xff << 8); 48846d81f451SRussell King lpi_ctl0 |= eee->tx_lpi_timer << 8; 48856d81f451SRussell King mvreg_write(pp, MVNETA_LPI_CTRL_0, lpi_ctl0); 48866d81f451SRussell King 48876d81f451SRussell King pp->eee_enabled = eee->eee_enabled; 48886d81f451SRussell King pp->tx_lpi_enabled = eee->tx_lpi_enabled; 48896d81f451SRussell King 48906d81f451SRussell King mvneta_set_eee(pp, eee->tx_lpi_enabled && eee->eee_enabled); 48916d81f451SRussell King 48926d81f451SRussell King return phylink_ethtool_set_eee(pp->phylink, eee); 48936d81f451SRussell King } 48946d81f451SRussell King 48954906887aSMaxime Chevallier static void mvneta_clear_rx_prio_map(struct mvneta_port *pp) 48964906887aSMaxime Chevallier { 48974906887aSMaxime Chevallier mvreg_write(pp, MVNETA_VLAN_PRIO_TO_RXQ, 0); 48984906887aSMaxime Chevallier } 48994906887aSMaxime Chevallier 49004906887aSMaxime Chevallier static void mvneta_setup_rx_prio_map(struct mvneta_port *pp) 49014906887aSMaxime Chevallier { 49024906887aSMaxime Chevallier u32 val = 0; 49034906887aSMaxime Chevallier int i; 49044906887aSMaxime Chevallier 49054906887aSMaxime Chevallier for (i = 0; i < rxq_number; i++) 49064906887aSMaxime Chevallier val |= MVNETA_VLAN_PRIO_RXQ_MAP(i, pp->prio_tc_map[i]); 49074906887aSMaxime Chevallier 49084906887aSMaxime Chevallier mvreg_write(pp, MVNETA_VLAN_PRIO_TO_RXQ, val); 49094906887aSMaxime Chevallier } 49104906887aSMaxime Chevallier 49114906887aSMaxime Chevallier static int mvneta_setup_mqprio(struct net_device *dev, 491275fa71e3SMaxime Chevallier struct tc_mqprio_qopt_offload *mqprio) 49134906887aSMaxime Chevallier { 49144906887aSMaxime Chevallier struct mvneta_port *pp = netdev_priv(dev); 49154906887aSMaxime Chevallier u8 num_tc; 49164906887aSMaxime Chevallier int i; 49174906887aSMaxime Chevallier 4918*e7ca75feSMaxime Chevallier if (mqprio->qopt.hw != TC_MQPRIO_HW_OFFLOAD_TCS) 4919*e7ca75feSMaxime Chevallier return 0; 4920*e7ca75feSMaxime Chevallier 492175fa71e3SMaxime Chevallier num_tc = mqprio->qopt.num_tc; 49224906887aSMaxime Chevallier 49234906887aSMaxime Chevallier if (num_tc > rxq_number) 49244906887aSMaxime Chevallier return -EINVAL; 49254906887aSMaxime Chevallier 49264906887aSMaxime Chevallier if (!num_tc) { 49274906887aSMaxime Chevallier mvneta_clear_rx_prio_map(pp); 49284906887aSMaxime Chevallier netdev_reset_tc(dev); 49294906887aSMaxime Chevallier return 0; 49304906887aSMaxime Chevallier } 49314906887aSMaxime Chevallier 493275fa71e3SMaxime Chevallier memcpy(pp->prio_tc_map, mqprio->qopt.prio_tc_map, 493375fa71e3SMaxime Chevallier sizeof(pp->prio_tc_map)); 49344906887aSMaxime Chevallier 49354906887aSMaxime Chevallier mvneta_setup_rx_prio_map(pp); 49364906887aSMaxime Chevallier 493775fa71e3SMaxime Chevallier netdev_set_num_tc(dev, mqprio->qopt.num_tc); 493875fa71e3SMaxime Chevallier for (i = 0; i < mqprio->qopt.num_tc; i++) 493975fa71e3SMaxime Chevallier netdev_set_tc_queue(dev, i, mqprio->qopt.count[i], 494075fa71e3SMaxime Chevallier mqprio->qopt.offset[i]); 49414906887aSMaxime Chevallier 49424906887aSMaxime Chevallier return 0; 49434906887aSMaxime Chevallier } 49444906887aSMaxime Chevallier 49454906887aSMaxime Chevallier static int mvneta_setup_tc(struct net_device *dev, enum tc_setup_type type, 49464906887aSMaxime Chevallier void *type_data) 49474906887aSMaxime Chevallier { 49484906887aSMaxime Chevallier switch (type) { 49494906887aSMaxime Chevallier case TC_SETUP_QDISC_MQPRIO: 49504906887aSMaxime Chevallier return mvneta_setup_mqprio(dev, type_data); 49514906887aSMaxime Chevallier default: 49524906887aSMaxime Chevallier return -EOPNOTSUPP; 49534906887aSMaxime Chevallier } 49544906887aSMaxime Chevallier } 49554906887aSMaxime Chevallier 4956c5aff182SThomas Petazzoni static const struct net_device_ops mvneta_netdev_ops = { 4957c5aff182SThomas Petazzoni .ndo_open = mvneta_open, 4958c5aff182SThomas Petazzoni .ndo_stop = mvneta_stop, 4959c5aff182SThomas Petazzoni .ndo_start_xmit = mvneta_tx, 4960c5aff182SThomas Petazzoni .ndo_set_rx_mode = mvneta_set_rx_mode, 4961c5aff182SThomas Petazzoni .ndo_set_mac_address = mvneta_set_mac_addr, 4962c5aff182SThomas Petazzoni .ndo_change_mtu = mvneta_change_mtu, 4963b65657fcSSimon Guinot .ndo_fix_features = mvneta_fix_features, 4964c5aff182SThomas Petazzoni .ndo_get_stats64 = mvneta_get_stats64, 4965a7605370SArnd Bergmann .ndo_eth_ioctl = mvneta_ioctl, 49660db51da7SLorenzo Bianconi .ndo_bpf = mvneta_xdp, 4967b0a43db9SLorenzo Bianconi .ndo_xdp_xmit = mvneta_xdp_xmit, 49684906887aSMaxime Chevallier .ndo_setup_tc = mvneta_setup_tc, 4969c5aff182SThomas Petazzoni }; 4970c5aff182SThomas Petazzoni 49714581be42SJisheng Zhang static const struct ethtool_ops mvneta_eth_tool_ops = { 497216e8d8b3SJakub Kicinski .supported_coalesce_params = ETHTOOL_COALESCE_RX_USECS | 497316e8d8b3SJakub Kicinski ETHTOOL_COALESCE_MAX_FRAMES, 4974503f9aa9SRussell King .nway_reset = mvneta_ethtool_nway_reset, 4975c5aff182SThomas Petazzoni .get_link = ethtool_op_get_link, 4976c5aff182SThomas Petazzoni .set_coalesce = mvneta_ethtool_set_coalesce, 4977c5aff182SThomas Petazzoni .get_coalesce = mvneta_ethtool_get_coalesce, 4978c5aff182SThomas Petazzoni .get_drvinfo = mvneta_ethtool_get_drvinfo, 4979c5aff182SThomas Petazzoni .get_ringparam = mvneta_ethtool_get_ringparam, 4980c5aff182SThomas Petazzoni .set_ringparam = mvneta_ethtool_set_ringparam, 49814932a918SRussell King .get_pauseparam = mvneta_ethtool_get_pauseparam, 49824932a918SRussell King .set_pauseparam = mvneta_ethtool_set_pauseparam, 49839b0cdefaSRussell King .get_strings = mvneta_ethtool_get_strings, 49849b0cdefaSRussell King .get_ethtool_stats = mvneta_ethtool_get_stats, 49859b0cdefaSRussell King .get_sset_count = mvneta_ethtool_get_sset_count, 49869a401deaSGregory CLEMENT .get_rxfh_indir_size = mvneta_ethtool_get_rxfh_indir_size, 49879a401deaSGregory CLEMENT .get_rxnfc = mvneta_ethtool_get_rxnfc, 49889a401deaSGregory CLEMENT .get_rxfh = mvneta_ethtool_get_rxfh, 49899a401deaSGregory CLEMENT .set_rxfh = mvneta_ethtool_set_rxfh, 4990503f9aa9SRussell King .get_link_ksettings = mvneta_ethtool_get_link_ksettings, 4991013ad40dSPhilippe Reynes .set_link_ksettings = mvneta_ethtool_set_link_ksettings, 4992b60a00f9SJingju Hou .get_wol = mvneta_ethtool_get_wol, 4993b60a00f9SJingju Hou .set_wol = mvneta_ethtool_set_wol, 49946d81f451SRussell King .get_eee = mvneta_ethtool_get_eee, 49956d81f451SRussell King .set_eee = mvneta_ethtool_set_eee, 4996c5aff182SThomas Petazzoni }; 4997c5aff182SThomas Petazzoni 4998c5aff182SThomas Petazzoni /* Initialize hw */ 49999672850bSEzequiel Garcia static int mvneta_init(struct device *dev, struct mvneta_port *pp) 5000c5aff182SThomas Petazzoni { 5001c5aff182SThomas Petazzoni int queue; 5002c5aff182SThomas Petazzoni 5003c5aff182SThomas Petazzoni /* Disable port */ 5004c5aff182SThomas Petazzoni mvneta_port_disable(pp); 5005c5aff182SThomas Petazzoni 5006c5aff182SThomas Petazzoni /* Set port default values */ 5007c5aff182SThomas Petazzoni mvneta_defaults_set(pp); 5008c5aff182SThomas Petazzoni 50095d6312edSMarkus Elfring pp->txqs = devm_kcalloc(dev, txq_number, sizeof(*pp->txqs), GFP_KERNEL); 5010c5aff182SThomas Petazzoni if (!pp->txqs) 5011c5aff182SThomas Petazzoni return -ENOMEM; 5012c5aff182SThomas Petazzoni 5013c5aff182SThomas Petazzoni /* Initialize TX descriptor rings */ 5014c5aff182SThomas Petazzoni for (queue = 0; queue < txq_number; queue++) { 5015c5aff182SThomas Petazzoni struct mvneta_tx_queue *txq = &pp->txqs[queue]; 5016c5aff182SThomas Petazzoni txq->id = queue; 5017c5aff182SThomas Petazzoni txq->size = pp->tx_ring_size; 5018c5aff182SThomas Petazzoni txq->done_pkts_coal = MVNETA_TXDONE_COAL_PKTS; 5019c5aff182SThomas Petazzoni } 5020c5aff182SThomas Petazzoni 50215d6312edSMarkus Elfring pp->rxqs = devm_kcalloc(dev, rxq_number, sizeof(*pp->rxqs), GFP_KERNEL); 50229672850bSEzequiel Garcia if (!pp->rxqs) 5023c5aff182SThomas Petazzoni return -ENOMEM; 5024c5aff182SThomas Petazzoni 5025c5aff182SThomas Petazzoni /* Create Rx descriptor rings */ 5026c5aff182SThomas Petazzoni for (queue = 0; queue < rxq_number; queue++) { 5027c5aff182SThomas Petazzoni struct mvneta_rx_queue *rxq = &pp->rxqs[queue]; 5028c5aff182SThomas Petazzoni rxq->id = queue; 5029c5aff182SThomas Petazzoni rxq->size = pp->rx_ring_size; 5030c5aff182SThomas Petazzoni rxq->pkts_coal = MVNETA_RX_COAL_PKTS; 5031c5aff182SThomas Petazzoni rxq->time_coal = MVNETA_RX_COAL_USEC; 503229110630SMarkus Elfring rxq->buf_virt_addr 503329110630SMarkus Elfring = devm_kmalloc_array(pp->dev->dev.parent, 503429110630SMarkus Elfring rxq->size, 503529110630SMarkus Elfring sizeof(*rxq->buf_virt_addr), 5036f88bee1cSGregory CLEMENT GFP_KERNEL); 5037f88bee1cSGregory CLEMENT if (!rxq->buf_virt_addr) 5038f88bee1cSGregory CLEMENT return -ENOMEM; 5039c5aff182SThomas Petazzoni } 5040c5aff182SThomas Petazzoni 5041c5aff182SThomas Petazzoni return 0; 5042c5aff182SThomas Petazzoni } 5043c5aff182SThomas Petazzoni 5044c5aff182SThomas Petazzoni /* platform glue : initialize decoding windows */ 504503ce758eSGreg KH static void mvneta_conf_mbus_windows(struct mvneta_port *pp, 5046c5aff182SThomas Petazzoni const struct mbus_dram_target_info *dram) 5047c5aff182SThomas Petazzoni { 5048c5aff182SThomas Petazzoni u32 win_enable; 5049c5aff182SThomas Petazzoni u32 win_protect; 5050c5aff182SThomas Petazzoni int i; 5051c5aff182SThomas Petazzoni 5052c5aff182SThomas Petazzoni for (i = 0; i < 6; i++) { 5053c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_WIN_BASE(i), 0); 5054c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_WIN_SIZE(i), 0); 5055c5aff182SThomas Petazzoni 5056c5aff182SThomas Petazzoni if (i < 4) 5057c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_WIN_REMAP(i), 0); 5058c5aff182SThomas Petazzoni } 5059c5aff182SThomas Petazzoni 5060c5aff182SThomas Petazzoni win_enable = 0x3f; 5061c5aff182SThomas Petazzoni win_protect = 0; 5062c5aff182SThomas Petazzoni 50632636ac3cSMarcin Wojtas if (dram) { 5064c5aff182SThomas Petazzoni for (i = 0; i < dram->num_cs; i++) { 5065c5aff182SThomas Petazzoni const struct mbus_dram_window *cs = dram->cs + i; 50662636ac3cSMarcin Wojtas 50672636ac3cSMarcin Wojtas mvreg_write(pp, MVNETA_WIN_BASE(i), 50682636ac3cSMarcin Wojtas (cs->base & 0xffff0000) | 50692636ac3cSMarcin Wojtas (cs->mbus_attr << 8) | 50702636ac3cSMarcin Wojtas dram->mbus_dram_target_id); 5071c5aff182SThomas Petazzoni 5072c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_WIN_SIZE(i), 5073c5aff182SThomas Petazzoni (cs->size - 1) & 0xffff0000); 5074c5aff182SThomas Petazzoni 5075c5aff182SThomas Petazzoni win_enable &= ~(1 << i); 5076c5aff182SThomas Petazzoni win_protect |= 3 << (2 * i); 5077c5aff182SThomas Petazzoni } 50782636ac3cSMarcin Wojtas } else { 50792636ac3cSMarcin Wojtas /* For Armada3700 open default 4GB Mbus window, leaving 50802636ac3cSMarcin Wojtas * arbitration of target/attribute to a different layer 50812636ac3cSMarcin Wojtas * of configuration. 50822636ac3cSMarcin Wojtas */ 50832636ac3cSMarcin Wojtas mvreg_write(pp, MVNETA_WIN_SIZE(0), 0xffff0000); 50842636ac3cSMarcin Wojtas win_enable &= ~BIT(0); 50852636ac3cSMarcin Wojtas win_protect = 3; 50862636ac3cSMarcin Wojtas } 5087c5aff182SThomas Petazzoni 5088c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_BASE_ADDR_ENABLE, win_enable); 5089db6ba9a5SMarcin Wojtas mvreg_write(pp, MVNETA_ACCESS_PROTECT_ENABLE, win_protect); 5090c5aff182SThomas Petazzoni } 5091c5aff182SThomas Petazzoni 5092c5aff182SThomas Petazzoni /* Power up the port */ 50933f1dd4bcSThomas Petazzoni static int mvneta_port_power_up(struct mvneta_port *pp, int phy_mode) 5094c5aff182SThomas Petazzoni { 5095c5aff182SThomas Petazzoni /* MAC Cause register should be cleared */ 5096c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_UNIT_INTR_CAUSE, 0); 5097c5aff182SThomas Petazzoni 509841c2b6b4SSascha Hauer if (phy_mode != PHY_INTERFACE_MODE_QSGMII && 509941c2b6b4SSascha Hauer phy_mode != PHY_INTERFACE_MODE_SGMII && 510041c2b6b4SSascha Hauer !phy_interface_mode_is_8023z(phy_mode) && 510141c2b6b4SSascha Hauer !phy_interface_mode_is_rgmii(phy_mode)) 51023f1dd4bcSThomas Petazzoni return -EINVAL; 51033f1dd4bcSThomas Petazzoni 51043f1dd4bcSThomas Petazzoni return 0; 5105c5aff182SThomas Petazzoni } 5106c5aff182SThomas Petazzoni 5107c5aff182SThomas Petazzoni /* Device initialization routine */ 510803ce758eSGreg KH static int mvneta_probe(struct platform_device *pdev) 5109c5aff182SThomas Petazzoni { 5110c5aff182SThomas Petazzoni struct device_node *dn = pdev->dev.of_node; 5111dc35a10fSMarcin Wojtas struct device_node *bm_node; 5112c5aff182SThomas Petazzoni struct mvneta_port *pp; 5113c5aff182SThomas Petazzoni struct net_device *dev; 5114503f9aa9SRussell King struct phylink *phylink; 5115a10c1c81SRussell King struct phy *comphy; 51168cc3e439SThomas Petazzoni char hw_mac_addr[ETH_ALEN]; 51170c65b2b9SAndrew Lunn phy_interface_t phy_mode; 51188cc3e439SThomas Petazzoni const char *mac_from; 51199110ee07SMarcin Wojtas int tx_csum_limit; 5120c5aff182SThomas Petazzoni int err; 512112bb03b4SMaxime Ripard int cpu; 5122c5aff182SThomas Petazzoni 5123a3ddd94fSRosen Penev dev = devm_alloc_etherdev_mqs(&pdev->dev, sizeof(struct mvneta_port), 5124a3ddd94fSRosen Penev txq_number, rxq_number); 5125c5aff182SThomas Petazzoni if (!dev) 5126c5aff182SThomas Petazzoni return -ENOMEM; 5127c5aff182SThomas Petazzoni 5128c5aff182SThomas Petazzoni dev->irq = irq_of_parse_and_map(dn, 0); 5129a3ddd94fSRosen Penev if (dev->irq == 0) 5130a3ddd94fSRosen Penev return -EINVAL; 5131c5aff182SThomas Petazzoni 51320c65b2b9SAndrew Lunn err = of_get_phy_mode(dn, &phy_mode); 51330c65b2b9SAndrew Lunn if (err) { 5134c5aff182SThomas Petazzoni dev_err(&pdev->dev, "incorrect phy-mode\n"); 5135503f9aa9SRussell King goto err_free_irq; 5136503f9aa9SRussell King } 5137503f9aa9SRussell King 5138a10c1c81SRussell King comphy = devm_of_phy_get(&pdev->dev, dn, NULL); 5139a10c1c81SRussell King if (comphy == ERR_PTR(-EPROBE_DEFER)) { 5140a10c1c81SRussell King err = -EPROBE_DEFER; 5141a10c1c81SRussell King goto err_free_irq; 5142a10c1c81SRussell King } else if (IS_ERR(comphy)) { 5143a10c1c81SRussell King comphy = NULL; 5144a10c1c81SRussell King } 5145a10c1c81SRussell King 514644cc27e4SIoana Ciornei pp = netdev_priv(dev); 514744cc27e4SIoana Ciornei spin_lock_init(&pp->lock); 514844cc27e4SIoana Ciornei 514944cc27e4SIoana Ciornei pp->phylink_config.dev = &dev->dev; 515044cc27e4SIoana Ciornei pp->phylink_config.type = PHYLINK_NETDEV; 515102a0988bSRussell King (Oracle) pp->phylink_config.mac_capabilities = MAC_SYM_PAUSE | MAC_10 | 515202a0988bSRussell King (Oracle) MAC_100 | MAC_1000FD | MAC_2500FD; 515302a0988bSRussell King (Oracle) 5154fdedb695SRussell King phy_interface_set_rgmii(pp->phylink_config.supported_interfaces); 5155fdedb695SRussell King __set_bit(PHY_INTERFACE_MODE_QSGMII, 5156fdedb695SRussell King pp->phylink_config.supported_interfaces); 5157fdedb695SRussell King if (comphy) { 5158fdedb695SRussell King /* If a COMPHY is present, we can support any of the serdes 5159fdedb695SRussell King * modes and switch between them. 5160fdedb695SRussell King */ 5161fdedb695SRussell King __set_bit(PHY_INTERFACE_MODE_SGMII, 5162fdedb695SRussell King pp->phylink_config.supported_interfaces); 5163fdedb695SRussell King __set_bit(PHY_INTERFACE_MODE_1000BASEX, 5164fdedb695SRussell King pp->phylink_config.supported_interfaces); 5165fdedb695SRussell King __set_bit(PHY_INTERFACE_MODE_2500BASEX, 5166fdedb695SRussell King pp->phylink_config.supported_interfaces); 5167fdedb695SRussell King } else if (phy_mode == PHY_INTERFACE_MODE_2500BASEX) { 5168fdedb695SRussell King /* No COMPHY, with only 2500BASE-X mode supported */ 5169fdedb695SRussell King __set_bit(PHY_INTERFACE_MODE_2500BASEX, 5170fdedb695SRussell King pp->phylink_config.supported_interfaces); 5171fdedb695SRussell King } else if (phy_mode == PHY_INTERFACE_MODE_1000BASEX || 5172fdedb695SRussell King phy_mode == PHY_INTERFACE_MODE_SGMII) { 5173fdedb695SRussell King /* No COMPHY, we can switch between 1000BASE-X and SGMII */ 5174fdedb695SRussell King __set_bit(PHY_INTERFACE_MODE_1000BASEX, 5175fdedb695SRussell King pp->phylink_config.supported_interfaces); 5176fdedb695SRussell King __set_bit(PHY_INTERFACE_MODE_SGMII, 5177fdedb695SRussell King pp->phylink_config.supported_interfaces); 5178fdedb695SRussell King } 517944cc27e4SIoana Ciornei 518044cc27e4SIoana Ciornei phylink = phylink_create(&pp->phylink_config, pdev->dev.fwnode, 518144cc27e4SIoana Ciornei phy_mode, &mvneta_phylink_ops); 5182503f9aa9SRussell King if (IS_ERR(phylink)) { 5183503f9aa9SRussell King err = PTR_ERR(phylink); 5184503f9aa9SRussell King goto err_free_irq; 5185c5aff182SThomas Petazzoni } 5186c5aff182SThomas Petazzoni 5187c5aff182SThomas Petazzoni dev->tx_queue_len = MVNETA_MAX_TXD; 5188c5aff182SThomas Petazzoni dev->watchdog_timeo = 5 * HZ; 5189c5aff182SThomas Petazzoni dev->netdev_ops = &mvneta_netdev_ops; 5190c5aff182SThomas Petazzoni 51917ad24ea4SWilfried Klaebe dev->ethtool_ops = &mvneta_eth_tool_ops; 5192c5aff182SThomas Petazzoni 5193503f9aa9SRussell King pp->phylink = phylink; 5194a10c1c81SRussell King pp->comphy = comphy; 5195c5aff182SThomas Petazzoni pp->phy_interface = phy_mode; 5196503f9aa9SRussell King pp->dn = dn; 5197c5aff182SThomas Petazzoni 519890b74c01SGregory CLEMENT pp->rxq_def = rxq_def; 51999a401deaSGregory CLEMENT pp->indir[0] = rxq_def; 52009a401deaSGregory CLEMENT 52012636ac3cSMarcin Wojtas /* Get special SoC configurations */ 52022636ac3cSMarcin Wojtas if (of_device_is_compatible(dn, "marvell,armada-3700-neta")) 52032636ac3cSMarcin Wojtas pp->neta_armada3700 = true; 52042636ac3cSMarcin Wojtas 52052804ba4eSJisheng Zhang pp->clk = devm_clk_get(&pdev->dev, "core"); 52062804ba4eSJisheng Zhang if (IS_ERR(pp->clk)) 5207189dd626SThomas Petazzoni pp->clk = devm_clk_get(&pdev->dev, NULL); 5208189dd626SThomas Petazzoni if (IS_ERR(pp->clk)) { 5209189dd626SThomas Petazzoni err = PTR_ERR(pp->clk); 5210503f9aa9SRussell King goto err_free_phylink; 5211189dd626SThomas Petazzoni } 5212189dd626SThomas Petazzoni 5213189dd626SThomas Petazzoni clk_prepare_enable(pp->clk); 5214189dd626SThomas Petazzoni 521515cc4a4aSJisheng Zhang pp->clk_bus = devm_clk_get(&pdev->dev, "bus"); 521615cc4a4aSJisheng Zhang if (!IS_ERR(pp->clk_bus)) 521715cc4a4aSJisheng Zhang clk_prepare_enable(pp->clk_bus); 521815cc4a4aSJisheng Zhang 521900c33afbSJisheng Zhang pp->base = devm_platform_ioremap_resource(pdev, 0); 5220c3f0dd38SThomas Petazzoni if (IS_ERR(pp->base)) { 5221c3f0dd38SThomas Petazzoni err = PTR_ERR(pp->base); 52225445eaf3SArnaud Patard \(Rtp\) goto err_clk; 52235445eaf3SArnaud Patard \(Rtp\) } 52245445eaf3SArnaud Patard \(Rtp\) 522512bb03b4SMaxime Ripard /* Alloc per-cpu port structure */ 522612bb03b4SMaxime Ripard pp->ports = alloc_percpu(struct mvneta_pcpu_port); 522712bb03b4SMaxime Ripard if (!pp->ports) { 522812bb03b4SMaxime Ripard err = -ENOMEM; 522912bb03b4SMaxime Ripard goto err_clk; 523012bb03b4SMaxime Ripard } 523112bb03b4SMaxime Ripard 523274c41b04Swilly tarreau /* Alloc per-cpu stats */ 52331c213bd2SWANG Cong pp->stats = netdev_alloc_pcpu_stats(struct mvneta_pcpu_stats); 523474c41b04Swilly tarreau if (!pp->stats) { 523574c41b04Swilly tarreau err = -ENOMEM; 523612bb03b4SMaxime Ripard goto err_free_ports; 523774c41b04Swilly tarreau } 523874c41b04Swilly tarreau 52399ca01b25SJakub Kicinski err = of_get_ethdev_address(dn, dev); 524083216e39SMichael Walle if (!err) { 52418cc3e439SThomas Petazzoni mac_from = "device tree"; 52428cc3e439SThomas Petazzoni } else { 52438cc3e439SThomas Petazzoni mvneta_get_mac_addr(pp, hw_mac_addr); 52448cc3e439SThomas Petazzoni if (is_valid_ether_addr(hw_mac_addr)) { 52458cc3e439SThomas Petazzoni mac_from = "hardware"; 5246a96d317fSJakub Kicinski eth_hw_addr_set(dev, hw_mac_addr); 52478cc3e439SThomas Petazzoni } else { 52488cc3e439SThomas Petazzoni mac_from = "random"; 52498cc3e439SThomas Petazzoni eth_hw_addr_random(dev); 52508cc3e439SThomas Petazzoni } 52518cc3e439SThomas Petazzoni } 52528cc3e439SThomas Petazzoni 52539110ee07SMarcin Wojtas if (!of_property_read_u32(dn, "tx-csum-limit", &tx_csum_limit)) { 52549110ee07SMarcin Wojtas if (tx_csum_limit < 0 || 52559110ee07SMarcin Wojtas tx_csum_limit > MVNETA_TX_CSUM_MAX_SIZE) { 52569110ee07SMarcin Wojtas tx_csum_limit = MVNETA_TX_CSUM_DEF_SIZE; 52579110ee07SMarcin Wojtas dev_info(&pdev->dev, 52589110ee07SMarcin Wojtas "Wrong TX csum limit in DT, set to %dB\n", 52599110ee07SMarcin Wojtas MVNETA_TX_CSUM_DEF_SIZE); 52609110ee07SMarcin Wojtas } 52619110ee07SMarcin Wojtas } else if (of_device_is_compatible(dn, "marvell,armada-370-neta")) { 52629110ee07SMarcin Wojtas tx_csum_limit = MVNETA_TX_CSUM_DEF_SIZE; 52639110ee07SMarcin Wojtas } else { 52649110ee07SMarcin Wojtas tx_csum_limit = MVNETA_TX_CSUM_MAX_SIZE; 52659110ee07SMarcin Wojtas } 52669110ee07SMarcin Wojtas 52679110ee07SMarcin Wojtas pp->tx_csum_limit = tx_csum_limit; 5268b65657fcSSimon Guinot 52699768b45cSJane Li pp->dram_target_info = mv_mbus_dram_info(); 52702636ac3cSMarcin Wojtas /* Armada3700 requires setting default configuration of Mbus 52712636ac3cSMarcin Wojtas * windows, however without using filled mbus_dram_target_info 52722636ac3cSMarcin Wojtas * structure. 52732636ac3cSMarcin Wojtas */ 52749768b45cSJane Li if (pp->dram_target_info || pp->neta_armada3700) 52759768b45cSJane Li mvneta_conf_mbus_windows(pp, pp->dram_target_info); 5276dc35a10fSMarcin Wojtas 5277c5aff182SThomas Petazzoni pp->tx_ring_size = MVNETA_MAX_TXD; 5278c5aff182SThomas Petazzoni pp->rx_ring_size = MVNETA_MAX_RXD; 5279c5aff182SThomas Petazzoni 5280c5aff182SThomas Petazzoni pp->dev = dev; 5281c5aff182SThomas Petazzoni SET_NETDEV_DEV(dev, &pdev->dev); 5282c5aff182SThomas Petazzoni 5283dc35a10fSMarcin Wojtas pp->id = global_port_id++; 5284dc35a10fSMarcin Wojtas 5285dc35a10fSMarcin Wojtas /* Obtain access to BM resources if enabled and already initialized */ 5286dc35a10fSMarcin Wojtas bm_node = of_parse_phandle(dn, "buffer-manager", 0); 5287965cbbecSGregory CLEMENT if (bm_node) { 5288965cbbecSGregory CLEMENT pp->bm_priv = mvneta_bm_get(bm_node); 5289965cbbecSGregory CLEMENT if (pp->bm_priv) { 5290dc35a10fSMarcin Wojtas err = mvneta_bm_port_init(pdev, pp); 5291dc35a10fSMarcin Wojtas if (err < 0) { 5292965cbbecSGregory CLEMENT dev_info(&pdev->dev, 5293965cbbecSGregory CLEMENT "use SW buffer management\n"); 5294965cbbecSGregory CLEMENT mvneta_bm_put(pp->bm_priv); 5295dc35a10fSMarcin Wojtas pp->bm_priv = NULL; 5296dc35a10fSMarcin Wojtas } 5297dc35a10fSMarcin Wojtas } 5298562e2f46SYelena Krivosheev /* Set RX packet offset correction for platforms, whose 5299562e2f46SYelena Krivosheev * NET_SKB_PAD, exceeds 64B. It should be 64B for 64-bit 5300562e2f46SYelena Krivosheev * platforms and 0B for 32-bit ones. 5301562e2f46SYelena Krivosheev */ 5302562e2f46SYelena Krivosheev pp->rx_offset_correction = max(0, 5303562e2f46SYelena Krivosheev NET_SKB_PAD - 5304562e2f46SYelena Krivosheev MVNETA_RX_PKT_OFFSET_CORRECTION); 5305965cbbecSGregory CLEMENT } 5306d4e4da00SPeter Chen of_node_put(bm_node); 5307dc35a10fSMarcin Wojtas 530844efc78dSLorenzo Bianconi /* sw buffer management */ 530944efc78dSLorenzo Bianconi if (!pp->bm_priv) 531044efc78dSLorenzo Bianconi pp->rx_offset_correction = MVNETA_SKB_HEADROOM; 531144efc78dSLorenzo Bianconi 53129672850bSEzequiel Garcia err = mvneta_init(&pdev->dev, pp); 53139672850bSEzequiel Garcia if (err < 0) 5314dc35a10fSMarcin Wojtas goto err_netdev; 53153f1dd4bcSThomas Petazzoni 531641c2b6b4SSascha Hauer err = mvneta_port_power_up(pp, pp->phy_interface); 53173f1dd4bcSThomas Petazzoni if (err < 0) { 53183f1dd4bcSThomas Petazzoni dev_err(&pdev->dev, "can't power up port\n"); 531958f60329SDinghao Liu goto err_netdev; 53203f1dd4bcSThomas Petazzoni } 5321c5aff182SThomas Petazzoni 53222636ac3cSMarcin Wojtas /* Armada3700 network controller does not support per-cpu 53232636ac3cSMarcin Wojtas * operation, so only single NAPI should be initialized. 53242636ac3cSMarcin Wojtas */ 53252636ac3cSMarcin Wojtas if (pp->neta_armada3700) { 53262636ac3cSMarcin Wojtas netif_napi_add(dev, &pp->napi, mvneta_poll, NAPI_POLL_WEIGHT); 53272636ac3cSMarcin Wojtas } else { 532812bb03b4SMaxime Ripard for_each_present_cpu(cpu) { 53292636ac3cSMarcin Wojtas struct mvneta_pcpu_port *port = 53302636ac3cSMarcin Wojtas per_cpu_ptr(pp->ports, cpu); 533112bb03b4SMaxime Ripard 53322636ac3cSMarcin Wojtas netif_napi_add(dev, &port->napi, mvneta_poll, 53332636ac3cSMarcin Wojtas NAPI_POLL_WEIGHT); 533412bb03b4SMaxime Ripard port->pp = pp; 533512bb03b4SMaxime Ripard } 53362636ac3cSMarcin Wojtas } 5337c5aff182SThomas Petazzoni 53387772988aSJisheng Zhang dev->features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | 53397772988aSJisheng Zhang NETIF_F_TSO | NETIF_F_RXCSUM; 534001ef26caSEzequiel Garcia dev->hw_features |= dev->features; 534101ef26caSEzequiel Garcia dev->vlan_features |= dev->features; 534297db8afaSAndrew Lunn dev->priv_flags |= IFF_LIVE_ADDR_CHANGE; 53436d872df3SEric Dumazet netif_set_gso_max_segs(dev, MVNETA_MAX_TSO_SEGS); 5344b50b72deSwilly tarreau 53455777987eSJarod Wilson /* MTU range: 68 - 9676 */ 53465777987eSJarod Wilson dev->min_mtu = ETH_MIN_MTU; 53475777987eSJarod Wilson /* 9676 == 9700 - 20 and rounding to 8 */ 53485777987eSJarod Wilson dev->max_mtu = 9676; 53495777987eSJarod Wilson 5350c5aff182SThomas Petazzoni err = register_netdev(dev); 5351c5aff182SThomas Petazzoni if (err < 0) { 5352c5aff182SThomas Petazzoni dev_err(&pdev->dev, "failed to register\n"); 5353d484e06eSJisheng Zhang goto err_netdev; 5354c5aff182SThomas Petazzoni } 5355c5aff182SThomas Petazzoni 53568cc3e439SThomas Petazzoni netdev_info(dev, "Using %s mac address %pM\n", mac_from, 53578cc3e439SThomas Petazzoni dev->dev_addr); 5358c5aff182SThomas Petazzoni 5359c5aff182SThomas Petazzoni platform_set_drvdata(pdev, pp->dev); 5360c5aff182SThomas Petazzoni 5361c5aff182SThomas Petazzoni return 0; 5362c5aff182SThomas Petazzoni 5363dc35a10fSMarcin Wojtas err_netdev: 5364dc35a10fSMarcin Wojtas if (pp->bm_priv) { 5365dc35a10fSMarcin Wojtas mvneta_bm_pool_destroy(pp->bm_priv, pp->pool_long, 1 << pp->id); 5366dc35a10fSMarcin Wojtas mvneta_bm_pool_destroy(pp->bm_priv, pp->pool_short, 5367dc35a10fSMarcin Wojtas 1 << pp->id); 5368965cbbecSGregory CLEMENT mvneta_bm_put(pp->bm_priv); 5369dc35a10fSMarcin Wojtas } 537074c41b04Swilly tarreau free_percpu(pp->stats); 537112bb03b4SMaxime Ripard err_free_ports: 537212bb03b4SMaxime Ripard free_percpu(pp->ports); 53735445eaf3SArnaud Patard \(Rtp\) err_clk: 537415cc4a4aSJisheng Zhang clk_disable_unprepare(pp->clk_bus); 53755445eaf3SArnaud Patard \(Rtp\) clk_disable_unprepare(pp->clk); 5376503f9aa9SRussell King err_free_phylink: 5377503f9aa9SRussell King if (pp->phylink) 5378503f9aa9SRussell King phylink_destroy(pp->phylink); 5379c5aff182SThomas Petazzoni err_free_irq: 5380c5aff182SThomas Petazzoni irq_dispose_mapping(dev->irq); 5381c5aff182SThomas Petazzoni return err; 5382c5aff182SThomas Petazzoni } 5383c5aff182SThomas Petazzoni 5384c5aff182SThomas Petazzoni /* Device removal routine */ 538503ce758eSGreg KH static int mvneta_remove(struct platform_device *pdev) 5386c5aff182SThomas Petazzoni { 5387c5aff182SThomas Petazzoni struct net_device *dev = platform_get_drvdata(pdev); 5388c5aff182SThomas Petazzoni struct mvneta_port *pp = netdev_priv(dev); 5389c5aff182SThomas Petazzoni 5390c5aff182SThomas Petazzoni unregister_netdev(dev); 539115cc4a4aSJisheng Zhang clk_disable_unprepare(pp->clk_bus); 5392189dd626SThomas Petazzoni clk_disable_unprepare(pp->clk); 539312bb03b4SMaxime Ripard free_percpu(pp->ports); 539474c41b04Swilly tarreau free_percpu(pp->stats); 5395c5aff182SThomas Petazzoni irq_dispose_mapping(dev->irq); 5396503f9aa9SRussell King phylink_destroy(pp->phylink); 5397c5aff182SThomas Petazzoni 5398dc35a10fSMarcin Wojtas if (pp->bm_priv) { 5399dc35a10fSMarcin Wojtas mvneta_bm_pool_destroy(pp->bm_priv, pp->pool_long, 1 << pp->id); 5400dc35a10fSMarcin Wojtas mvneta_bm_pool_destroy(pp->bm_priv, pp->pool_short, 5401dc35a10fSMarcin Wojtas 1 << pp->id); 5402965cbbecSGregory CLEMENT mvneta_bm_put(pp->bm_priv); 5403dc35a10fSMarcin Wojtas } 5404dc35a10fSMarcin Wojtas 5405c5aff182SThomas Petazzoni return 0; 5406c5aff182SThomas Petazzoni } 5407c5aff182SThomas Petazzoni 54089768b45cSJane Li #ifdef CONFIG_PM_SLEEP 54099768b45cSJane Li static int mvneta_suspend(struct device *device) 54109768b45cSJane Li { 54111799cdd2SJisheng Zhang int queue; 54129768b45cSJane Li struct net_device *dev = dev_get_drvdata(device); 54139768b45cSJane Li struct mvneta_port *pp = netdev_priv(dev); 54149768b45cSJane Li 54151799cdd2SJisheng Zhang if (!netif_running(dev)) 54161799cdd2SJisheng Zhang goto clean_exit; 54171799cdd2SJisheng Zhang 54181799cdd2SJisheng Zhang if (!pp->neta_armada3700) { 54191799cdd2SJisheng Zhang spin_lock(&pp->lock); 54201799cdd2SJisheng Zhang pp->is_stopped = true; 54211799cdd2SJisheng Zhang spin_unlock(&pp->lock); 54221799cdd2SJisheng Zhang 54231799cdd2SJisheng Zhang cpuhp_state_remove_instance_nocalls(online_hpstate, 54241799cdd2SJisheng Zhang &pp->node_online); 54251799cdd2SJisheng Zhang cpuhp_state_remove_instance_nocalls(CPUHP_NET_MVNETA_DEAD, 54261799cdd2SJisheng Zhang &pp->node_dead); 54271799cdd2SJisheng Zhang } 54281799cdd2SJisheng Zhang 54293b8bc674SRussell King rtnl_lock(); 54301799cdd2SJisheng Zhang mvneta_stop_dev(pp); 54313b8bc674SRussell King rtnl_unlock(); 54321799cdd2SJisheng Zhang 54331799cdd2SJisheng Zhang for (queue = 0; queue < rxq_number; queue++) { 54341799cdd2SJisheng Zhang struct mvneta_rx_queue *rxq = &pp->rxqs[queue]; 54351799cdd2SJisheng Zhang 54361799cdd2SJisheng Zhang mvneta_rxq_drop_pkts(pp, rxq); 54371799cdd2SJisheng Zhang } 54381799cdd2SJisheng Zhang 54391799cdd2SJisheng Zhang for (queue = 0; queue < txq_number; queue++) { 54401799cdd2SJisheng Zhang struct mvneta_tx_queue *txq = &pp->txqs[queue]; 54411799cdd2SJisheng Zhang 54421799cdd2SJisheng Zhang mvneta_txq_hw_deinit(pp, txq); 54431799cdd2SJisheng Zhang } 54441799cdd2SJisheng Zhang 54451799cdd2SJisheng Zhang clean_exit: 54469768b45cSJane Li netif_device_detach(dev); 54479768b45cSJane Li clk_disable_unprepare(pp->clk_bus); 54489768b45cSJane Li clk_disable_unprepare(pp->clk); 54491799cdd2SJisheng Zhang 54509768b45cSJane Li return 0; 54519768b45cSJane Li } 54529768b45cSJane Li 54539768b45cSJane Li static int mvneta_resume(struct device *device) 54549768b45cSJane Li { 54559768b45cSJane Li struct platform_device *pdev = to_platform_device(device); 54569768b45cSJane Li struct net_device *dev = dev_get_drvdata(device); 54579768b45cSJane Li struct mvneta_port *pp = netdev_priv(dev); 54581799cdd2SJisheng Zhang int err, queue; 54599768b45cSJane Li 54609768b45cSJane Li clk_prepare_enable(pp->clk); 54619768b45cSJane Li if (!IS_ERR(pp->clk_bus)) 54629768b45cSJane Li clk_prepare_enable(pp->clk_bus); 54639768b45cSJane Li if (pp->dram_target_info || pp->neta_armada3700) 54649768b45cSJane Li mvneta_conf_mbus_windows(pp, pp->dram_target_info); 54659768b45cSJane Li if (pp->bm_priv) { 54669768b45cSJane Li err = mvneta_bm_port_init(pdev, pp); 54679768b45cSJane Li if (err < 0) { 54689768b45cSJane Li dev_info(&pdev->dev, "use SW buffer management\n"); 546944efc78dSLorenzo Bianconi pp->rx_offset_correction = MVNETA_SKB_HEADROOM; 54709768b45cSJane Li pp->bm_priv = NULL; 54719768b45cSJane Li } 54729768b45cSJane Li } 54739768b45cSJane Li mvneta_defaults_set(pp); 54749768b45cSJane Li err = mvneta_port_power_up(pp, pp->phy_interface); 54759768b45cSJane Li if (err < 0) { 54769768b45cSJane Li dev_err(device, "can't power up port\n"); 54779768b45cSJane Li return err; 54789768b45cSJane Li } 54799768b45cSJane Li 54809768b45cSJane Li netif_device_attach(dev); 54811799cdd2SJisheng Zhang 54821799cdd2SJisheng Zhang if (!netif_running(dev)) 54831799cdd2SJisheng Zhang return 0; 54841799cdd2SJisheng Zhang 54851799cdd2SJisheng Zhang for (queue = 0; queue < rxq_number; queue++) { 54861799cdd2SJisheng Zhang struct mvneta_rx_queue *rxq = &pp->rxqs[queue]; 54871799cdd2SJisheng Zhang 54881799cdd2SJisheng Zhang rxq->next_desc_to_proc = 0; 54891799cdd2SJisheng Zhang mvneta_rxq_hw_init(pp, rxq); 5490d6956ac8SJisheng Zhang } 54911799cdd2SJisheng Zhang 54921799cdd2SJisheng Zhang for (queue = 0; queue < txq_number; queue++) { 54931799cdd2SJisheng Zhang struct mvneta_tx_queue *txq = &pp->txqs[queue]; 54941799cdd2SJisheng Zhang 54951799cdd2SJisheng Zhang txq->next_desc_to_proc = 0; 54961799cdd2SJisheng Zhang mvneta_txq_hw_init(pp, txq); 54971799cdd2SJisheng Zhang } 54981799cdd2SJisheng Zhang 54991799cdd2SJisheng Zhang if (!pp->neta_armada3700) { 55001799cdd2SJisheng Zhang spin_lock(&pp->lock); 55011799cdd2SJisheng Zhang pp->is_stopped = false; 55021799cdd2SJisheng Zhang spin_unlock(&pp->lock); 55031799cdd2SJisheng Zhang cpuhp_state_add_instance_nocalls(online_hpstate, 55041799cdd2SJisheng Zhang &pp->node_online); 55051799cdd2SJisheng Zhang cpuhp_state_add_instance_nocalls(CPUHP_NET_MVNETA_DEAD, 55061799cdd2SJisheng Zhang &pp->node_dead); 55071799cdd2SJisheng Zhang } 55081799cdd2SJisheng Zhang 55091799cdd2SJisheng Zhang rtnl_lock(); 55101799cdd2SJisheng Zhang mvneta_start_dev(pp); 55113b8bc674SRussell King rtnl_unlock(); 55121799cdd2SJisheng Zhang mvneta_set_rx_mode(dev); 5513d6956ac8SJisheng Zhang 55149768b45cSJane Li return 0; 55159768b45cSJane Li } 55169768b45cSJane Li #endif 55179768b45cSJane Li 55189768b45cSJane Li static SIMPLE_DEV_PM_OPS(mvneta_pm_ops, mvneta_suspend, mvneta_resume); 55199768b45cSJane Li 5520c5aff182SThomas Petazzoni static const struct of_device_id mvneta_match[] = { 5521c5aff182SThomas Petazzoni { .compatible = "marvell,armada-370-neta" }, 5522f522a975SSimon Guinot { .compatible = "marvell,armada-xp-neta" }, 55232636ac3cSMarcin Wojtas { .compatible = "marvell,armada-3700-neta" }, 5524c5aff182SThomas Petazzoni { } 5525c5aff182SThomas Petazzoni }; 5526c5aff182SThomas Petazzoni MODULE_DEVICE_TABLE(of, mvneta_match); 5527c5aff182SThomas Petazzoni 5528c5aff182SThomas Petazzoni static struct platform_driver mvneta_driver = { 5529c5aff182SThomas Petazzoni .probe = mvneta_probe, 553003ce758eSGreg KH .remove = mvneta_remove, 5531c5aff182SThomas Petazzoni .driver = { 5532c5aff182SThomas Petazzoni .name = MVNETA_DRIVER_NAME, 5533c5aff182SThomas Petazzoni .of_match_table = mvneta_match, 55349768b45cSJane Li .pm = &mvneta_pm_ops, 5535c5aff182SThomas Petazzoni }, 5536c5aff182SThomas Petazzoni }; 5537c5aff182SThomas Petazzoni 553884a3f4dbSSebastian Andrzej Siewior static int __init mvneta_driver_init(void) 553984a3f4dbSSebastian Andrzej Siewior { 554084a3f4dbSSebastian Andrzej Siewior int ret; 554184a3f4dbSSebastian Andrzej Siewior 5542664d035cSChristophe JAILLET ret = cpuhp_setup_state_multi(CPUHP_AP_ONLINE_DYN, "net/mvneta:online", 554384a3f4dbSSebastian Andrzej Siewior mvneta_cpu_online, 554484a3f4dbSSebastian Andrzej Siewior mvneta_cpu_down_prepare); 554584a3f4dbSSebastian Andrzej Siewior if (ret < 0) 554684a3f4dbSSebastian Andrzej Siewior goto out; 554784a3f4dbSSebastian Andrzej Siewior online_hpstate = ret; 554884a3f4dbSSebastian Andrzej Siewior ret = cpuhp_setup_state_multi(CPUHP_NET_MVNETA_DEAD, "net/mvneta:dead", 554984a3f4dbSSebastian Andrzej Siewior NULL, mvneta_cpu_dead); 555084a3f4dbSSebastian Andrzej Siewior if (ret) 555184a3f4dbSSebastian Andrzej Siewior goto err_dead; 555284a3f4dbSSebastian Andrzej Siewior 555384a3f4dbSSebastian Andrzej Siewior ret = platform_driver_register(&mvneta_driver); 555484a3f4dbSSebastian Andrzej Siewior if (ret) 555584a3f4dbSSebastian Andrzej Siewior goto err; 555684a3f4dbSSebastian Andrzej Siewior return 0; 555784a3f4dbSSebastian Andrzej Siewior 555884a3f4dbSSebastian Andrzej Siewior err: 555984a3f4dbSSebastian Andrzej Siewior cpuhp_remove_multi_state(CPUHP_NET_MVNETA_DEAD); 556084a3f4dbSSebastian Andrzej Siewior err_dead: 556184a3f4dbSSebastian Andrzej Siewior cpuhp_remove_multi_state(online_hpstate); 556284a3f4dbSSebastian Andrzej Siewior out: 556384a3f4dbSSebastian Andrzej Siewior return ret; 556484a3f4dbSSebastian Andrzej Siewior } 556584a3f4dbSSebastian Andrzej Siewior module_init(mvneta_driver_init); 556684a3f4dbSSebastian Andrzej Siewior 556784a3f4dbSSebastian Andrzej Siewior static void __exit mvneta_driver_exit(void) 556884a3f4dbSSebastian Andrzej Siewior { 556984a3f4dbSSebastian Andrzej Siewior platform_driver_unregister(&mvneta_driver); 557084a3f4dbSSebastian Andrzej Siewior cpuhp_remove_multi_state(CPUHP_NET_MVNETA_DEAD); 557184a3f4dbSSebastian Andrzej Siewior cpuhp_remove_multi_state(online_hpstate); 557284a3f4dbSSebastian Andrzej Siewior } 557384a3f4dbSSebastian Andrzej Siewior module_exit(mvneta_driver_exit); 5574c5aff182SThomas Petazzoni 5575c5aff182SThomas Petazzoni MODULE_DESCRIPTION("Marvell NETA Ethernet Driver - www.marvell.com"); 5576c5aff182SThomas Petazzoni MODULE_AUTHOR("Rami Rosen <rosenr@marvell.com>, Thomas Petazzoni <thomas.petazzoni@free-electrons.com>"); 5577c5aff182SThomas Petazzoni MODULE_LICENSE("GPL"); 5578c5aff182SThomas Petazzoni 5579d3757ba4SJoe Perches module_param(rxq_number, int, 0444); 5580d3757ba4SJoe Perches module_param(txq_number, int, 0444); 5581c5aff182SThomas Petazzoni 5582d3757ba4SJoe Perches module_param(rxq_def, int, 0444); 5583d3757ba4SJoe Perches module_param(rx_copybreak, int, 0644); 5584