1c5aff182SThomas Petazzoni /* 2c5aff182SThomas Petazzoni * Driver for Marvell NETA network card for Armada XP and Armada 370 SoCs. 3c5aff182SThomas Petazzoni * 4c5aff182SThomas Petazzoni * Copyright (C) 2012 Marvell 5c5aff182SThomas Petazzoni * 6c5aff182SThomas Petazzoni * Rami Rosen <rosenr@marvell.com> 7c5aff182SThomas Petazzoni * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> 8c5aff182SThomas Petazzoni * 9c5aff182SThomas Petazzoni * This file is licensed under the terms of the GNU General Public 10c5aff182SThomas Petazzoni * License version 2. This program is licensed "as is" without any 11c5aff182SThomas Petazzoni * warranty of any kind, whether express or implied. 12c5aff182SThomas Petazzoni */ 13c5aff182SThomas Petazzoni 140e03f563SJisheng Zhang #include <linux/clk.h> 150e03f563SJisheng Zhang #include <linux/cpu.h> 16c5aff182SThomas Petazzoni #include <linux/etherdevice.h> 170e03f563SJisheng Zhang #include <linux/if_vlan.h> 18c5aff182SThomas Petazzoni #include <linux/inetdevice.h> 190e03f563SJisheng Zhang #include <linux/interrupt.h> 200e03f563SJisheng Zhang #include <linux/io.h> 210e03f563SJisheng Zhang #include <linux/kernel.h> 22c5aff182SThomas Petazzoni #include <linux/mbus.h> 23c5aff182SThomas Petazzoni #include <linux/module.h> 240e03f563SJisheng Zhang #include <linux/netdevice.h> 25c5aff182SThomas Petazzoni #include <linux/of.h> 260e03f563SJisheng Zhang #include <linux/of_address.h> 27c5aff182SThomas Petazzoni #include <linux/of_irq.h> 28c5aff182SThomas Petazzoni #include <linux/of_mdio.h> 29c5aff182SThomas Petazzoni #include <linux/of_net.h> 30a10c1c81SRussell King #include <linux/phy/phy.h> 31c5aff182SThomas Petazzoni #include <linux/phy.h> 32503f9aa9SRussell King #include <linux/phylink.h> 330e03f563SJisheng Zhang #include <linux/platform_device.h> 340e03f563SJisheng Zhang #include <linux/skbuff.h> 35baa11ebcSGregory CLEMENT #include <net/hwbm.h> 36dc35a10fSMarcin Wojtas #include "mvneta_bm.h" 370e03f563SJisheng Zhang #include <net/ip.h> 380e03f563SJisheng Zhang #include <net/ipv6.h> 390e03f563SJisheng Zhang #include <net/tso.h> 40568a3fa2SLorenzo Bianconi #include <net/page_pool.h> 410db51da7SLorenzo Bianconi #include <linux/bpf_trace.h> 42c5aff182SThomas Petazzoni 43c5aff182SThomas Petazzoni /* Registers */ 44c5aff182SThomas Petazzoni #define MVNETA_RXQ_CONFIG_REG(q) (0x1400 + ((q) << 2)) 45e5bdf689SMarcin Wojtas #define MVNETA_RXQ_HW_BUF_ALLOC BIT(0) 46dc35a10fSMarcin Wojtas #define MVNETA_RXQ_SHORT_POOL_ID_SHIFT 4 47dc35a10fSMarcin Wojtas #define MVNETA_RXQ_SHORT_POOL_ID_MASK 0x30 48dc35a10fSMarcin Wojtas #define MVNETA_RXQ_LONG_POOL_ID_SHIFT 6 49dc35a10fSMarcin Wojtas #define MVNETA_RXQ_LONG_POOL_ID_MASK 0xc0 50c5aff182SThomas Petazzoni #define MVNETA_RXQ_PKT_OFFSET_ALL_MASK (0xf << 8) 51c5aff182SThomas Petazzoni #define MVNETA_RXQ_PKT_OFFSET_MASK(offs) ((offs) << 8) 52c5aff182SThomas Petazzoni #define MVNETA_RXQ_THRESHOLD_REG(q) (0x14c0 + ((q) << 2)) 53c5aff182SThomas Petazzoni #define MVNETA_RXQ_NON_OCCUPIED(v) ((v) << 16) 54c5aff182SThomas Petazzoni #define MVNETA_RXQ_BASE_ADDR_REG(q) (0x1480 + ((q) << 2)) 55c5aff182SThomas Petazzoni #define MVNETA_RXQ_SIZE_REG(q) (0x14a0 + ((q) << 2)) 56c5aff182SThomas Petazzoni #define MVNETA_RXQ_BUF_SIZE_SHIFT 19 57c5aff182SThomas Petazzoni #define MVNETA_RXQ_BUF_SIZE_MASK (0x1fff << 19) 58c5aff182SThomas Petazzoni #define MVNETA_RXQ_STATUS_REG(q) (0x14e0 + ((q) << 2)) 59c5aff182SThomas Petazzoni #define MVNETA_RXQ_OCCUPIED_ALL_MASK 0x3fff 60c5aff182SThomas Petazzoni #define MVNETA_RXQ_STATUS_UPDATE_REG(q) (0x1500 + ((q) << 2)) 61c5aff182SThomas Petazzoni #define MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT 16 62c5aff182SThomas Petazzoni #define MVNETA_RXQ_ADD_NON_OCCUPIED_MAX 255 63dc35a10fSMarcin Wojtas #define MVNETA_PORT_POOL_BUFFER_SZ_REG(pool) (0x1700 + ((pool) << 2)) 64dc35a10fSMarcin Wojtas #define MVNETA_PORT_POOL_BUFFER_SZ_SHIFT 3 65dc35a10fSMarcin Wojtas #define MVNETA_PORT_POOL_BUFFER_SZ_MASK 0xfff8 66c5aff182SThomas Petazzoni #define MVNETA_PORT_RX_RESET 0x1cc0 67c5aff182SThomas Petazzoni #define MVNETA_PORT_RX_DMA_RESET BIT(0) 68c5aff182SThomas Petazzoni #define MVNETA_PHY_ADDR 0x2000 69c5aff182SThomas Petazzoni #define MVNETA_PHY_ADDR_MASK 0x1f 70c5aff182SThomas Petazzoni #define MVNETA_MBUS_RETRY 0x2010 71c5aff182SThomas Petazzoni #define MVNETA_UNIT_INTR_CAUSE 0x2080 72c5aff182SThomas Petazzoni #define MVNETA_UNIT_CONTROL 0x20B0 73c5aff182SThomas Petazzoni #define MVNETA_PHY_POLLING_ENABLE BIT(1) 74c5aff182SThomas Petazzoni #define MVNETA_WIN_BASE(w) (0x2200 + ((w) << 3)) 75c5aff182SThomas Petazzoni #define MVNETA_WIN_SIZE(w) (0x2204 + ((w) << 3)) 76c5aff182SThomas Petazzoni #define MVNETA_WIN_REMAP(w) (0x2280 + ((w) << 2)) 77c5aff182SThomas Petazzoni #define MVNETA_BASE_ADDR_ENABLE 0x2290 78db6ba9a5SMarcin Wojtas #define MVNETA_ACCESS_PROTECT_ENABLE 0x2294 79c5aff182SThomas Petazzoni #define MVNETA_PORT_CONFIG 0x2400 80c5aff182SThomas Petazzoni #define MVNETA_UNI_PROMISC_MODE BIT(0) 81c5aff182SThomas Petazzoni #define MVNETA_DEF_RXQ(q) ((q) << 1) 82c5aff182SThomas Petazzoni #define MVNETA_DEF_RXQ_ARP(q) ((q) << 4) 83c5aff182SThomas Petazzoni #define MVNETA_TX_UNSET_ERR_SUM BIT(12) 84c5aff182SThomas Petazzoni #define MVNETA_DEF_RXQ_TCP(q) ((q) << 16) 85c5aff182SThomas Petazzoni #define MVNETA_DEF_RXQ_UDP(q) ((q) << 19) 86c5aff182SThomas Petazzoni #define MVNETA_DEF_RXQ_BPDU(q) ((q) << 22) 87c5aff182SThomas Petazzoni #define MVNETA_RX_CSUM_WITH_PSEUDO_HDR BIT(25) 88c5aff182SThomas Petazzoni #define MVNETA_PORT_CONFIG_DEFL_VALUE(q) (MVNETA_DEF_RXQ(q) | \ 89c5aff182SThomas Petazzoni MVNETA_DEF_RXQ_ARP(q) | \ 90c5aff182SThomas Petazzoni MVNETA_DEF_RXQ_TCP(q) | \ 91c5aff182SThomas Petazzoni MVNETA_DEF_RXQ_UDP(q) | \ 92c5aff182SThomas Petazzoni MVNETA_DEF_RXQ_BPDU(q) | \ 93c5aff182SThomas Petazzoni MVNETA_TX_UNSET_ERR_SUM | \ 94c5aff182SThomas Petazzoni MVNETA_RX_CSUM_WITH_PSEUDO_HDR) 95c5aff182SThomas Petazzoni #define MVNETA_PORT_CONFIG_EXTEND 0x2404 96c5aff182SThomas Petazzoni #define MVNETA_MAC_ADDR_LOW 0x2414 97c5aff182SThomas Petazzoni #define MVNETA_MAC_ADDR_HIGH 0x2418 98c5aff182SThomas Petazzoni #define MVNETA_SDMA_CONFIG 0x241c 99c5aff182SThomas Petazzoni #define MVNETA_SDMA_BRST_SIZE_16 4 100c5aff182SThomas Petazzoni #define MVNETA_RX_BRST_SZ_MASK(burst) ((burst) << 1) 101c5aff182SThomas Petazzoni #define MVNETA_RX_NO_DATA_SWAP BIT(4) 102c5aff182SThomas Petazzoni #define MVNETA_TX_NO_DATA_SWAP BIT(5) 1039ad8fef6SThomas Petazzoni #define MVNETA_DESC_SWAP BIT(6) 104c5aff182SThomas Petazzoni #define MVNETA_TX_BRST_SZ_MASK(burst) ((burst) << 22) 105c5aff182SThomas Petazzoni #define MVNETA_PORT_STATUS 0x2444 106c5aff182SThomas Petazzoni #define MVNETA_TX_IN_PRGRS BIT(1) 107c5aff182SThomas Petazzoni #define MVNETA_TX_FIFO_EMPTY BIT(8) 108c5aff182SThomas Petazzoni #define MVNETA_RX_MIN_FRAME_SIZE 0x247c 1093f1dd4bcSThomas Petazzoni #define MVNETA_SERDES_CFG 0x24A0 1105445eaf3SArnaud Patard \(Rtp\) #define MVNETA_SGMII_SERDES_PROTO 0x0cc7 1113f1dd4bcSThomas Petazzoni #define MVNETA_QSGMII_SERDES_PROTO 0x0667 112c5aff182SThomas Petazzoni #define MVNETA_TYPE_PRIO 0x24bc 113c5aff182SThomas Petazzoni #define MVNETA_FORCE_UNI BIT(21) 114c5aff182SThomas Petazzoni #define MVNETA_TXQ_CMD_1 0x24e4 115c5aff182SThomas Petazzoni #define MVNETA_TXQ_CMD 0x2448 116c5aff182SThomas Petazzoni #define MVNETA_TXQ_DISABLE_SHIFT 8 117c5aff182SThomas Petazzoni #define MVNETA_TXQ_ENABLE_MASK 0x000000ff 118e483911fSAndrew Lunn #define MVNETA_RX_DISCARD_FRAME_COUNT 0x2484 119e483911fSAndrew Lunn #define MVNETA_OVERRUN_FRAME_COUNT 0x2488 120898b2970SStas Sergeev #define MVNETA_GMAC_CLOCK_DIVIDER 0x24f4 121898b2970SStas Sergeev #define MVNETA_GMAC_1MS_CLOCK_ENABLE BIT(31) 122c5aff182SThomas Petazzoni #define MVNETA_ACC_MODE 0x2500 123dc35a10fSMarcin Wojtas #define MVNETA_BM_ADDRESS 0x2504 124c5aff182SThomas Petazzoni #define MVNETA_CPU_MAP(cpu) (0x2540 + ((cpu) << 2)) 125c5aff182SThomas Petazzoni #define MVNETA_CPU_RXQ_ACCESS_ALL_MASK 0x000000ff 126c5aff182SThomas Petazzoni #define MVNETA_CPU_TXQ_ACCESS_ALL_MASK 0x0000ff00 1272dcf75e2SGregory CLEMENT #define MVNETA_CPU_RXQ_ACCESS(rxq) BIT(rxq) 12850bf8cb6SGregory CLEMENT #define MVNETA_CPU_TXQ_ACCESS(txq) BIT(txq + 8) 129c5aff182SThomas Petazzoni #define MVNETA_RXQ_TIME_COAL_REG(q) (0x2580 + ((q) << 2)) 13040ba35e7Swilly tarreau 1312dcf75e2SGregory CLEMENT /* Exception Interrupt Port/Queue Cause register 1322dcf75e2SGregory CLEMENT * 1332dcf75e2SGregory CLEMENT * Their behavior depend of the mapping done using the PCPX2Q 1342dcf75e2SGregory CLEMENT * registers. For a given CPU if the bit associated to a queue is not 1352dcf75e2SGregory CLEMENT * set, then for the register a read from this CPU will always return 1362dcf75e2SGregory CLEMENT * 0 and a write won't do anything 1372dcf75e2SGregory CLEMENT */ 13840ba35e7Swilly tarreau 139c5aff182SThomas Petazzoni #define MVNETA_INTR_NEW_CAUSE 0x25a0 140c5aff182SThomas Petazzoni #define MVNETA_INTR_NEW_MASK 0x25a4 14140ba35e7Swilly tarreau 14240ba35e7Swilly tarreau /* bits 0..7 = TXQ SENT, one bit per queue. 14340ba35e7Swilly tarreau * bits 8..15 = RXQ OCCUP, one bit per queue. 14440ba35e7Swilly tarreau * bits 16..23 = RXQ FREE, one bit per queue. 14540ba35e7Swilly tarreau * bit 29 = OLD_REG_SUM, see old reg ? 14640ba35e7Swilly tarreau * bit 30 = TX_ERR_SUM, one bit for 4 ports 14740ba35e7Swilly tarreau * bit 31 = MISC_SUM, one bit for 4 ports 14840ba35e7Swilly tarreau */ 14940ba35e7Swilly tarreau #define MVNETA_TX_INTR_MASK(nr_txqs) (((1 << nr_txqs) - 1) << 0) 15040ba35e7Swilly tarreau #define MVNETA_TX_INTR_MASK_ALL (0xff << 0) 15140ba35e7Swilly tarreau #define MVNETA_RX_INTR_MASK(nr_rxqs) (((1 << nr_rxqs) - 1) << 8) 15240ba35e7Swilly tarreau #define MVNETA_RX_INTR_MASK_ALL (0xff << 8) 153898b2970SStas Sergeev #define MVNETA_MISCINTR_INTR_MASK BIT(31) 15440ba35e7Swilly tarreau 155c5aff182SThomas Petazzoni #define MVNETA_INTR_OLD_CAUSE 0x25a8 156c5aff182SThomas Petazzoni #define MVNETA_INTR_OLD_MASK 0x25ac 15740ba35e7Swilly tarreau 15840ba35e7Swilly tarreau /* Data Path Port/Queue Cause Register */ 159c5aff182SThomas Petazzoni #define MVNETA_INTR_MISC_CAUSE 0x25b0 160c5aff182SThomas Petazzoni #define MVNETA_INTR_MISC_MASK 0x25b4 16140ba35e7Swilly tarreau 16240ba35e7Swilly tarreau #define MVNETA_CAUSE_PHY_STATUS_CHANGE BIT(0) 16340ba35e7Swilly tarreau #define MVNETA_CAUSE_LINK_CHANGE BIT(1) 16440ba35e7Swilly tarreau #define MVNETA_CAUSE_PTP BIT(4) 16540ba35e7Swilly tarreau 16640ba35e7Swilly tarreau #define MVNETA_CAUSE_INTERNAL_ADDR_ERR BIT(7) 16740ba35e7Swilly tarreau #define MVNETA_CAUSE_RX_OVERRUN BIT(8) 16840ba35e7Swilly tarreau #define MVNETA_CAUSE_RX_CRC_ERROR BIT(9) 16940ba35e7Swilly tarreau #define MVNETA_CAUSE_RX_LARGE_PKT BIT(10) 17040ba35e7Swilly tarreau #define MVNETA_CAUSE_TX_UNDERUN BIT(11) 17140ba35e7Swilly tarreau #define MVNETA_CAUSE_PRBS_ERR BIT(12) 17240ba35e7Swilly tarreau #define MVNETA_CAUSE_PSC_SYNC_CHANGE BIT(13) 17340ba35e7Swilly tarreau #define MVNETA_CAUSE_SERDES_SYNC_ERR BIT(14) 17440ba35e7Swilly tarreau 17540ba35e7Swilly tarreau #define MVNETA_CAUSE_BMU_ALLOC_ERR_SHIFT 16 17640ba35e7Swilly tarreau #define MVNETA_CAUSE_BMU_ALLOC_ERR_ALL_MASK (0xF << MVNETA_CAUSE_BMU_ALLOC_ERR_SHIFT) 17740ba35e7Swilly tarreau #define MVNETA_CAUSE_BMU_ALLOC_ERR_MASK(pool) (1 << (MVNETA_CAUSE_BMU_ALLOC_ERR_SHIFT + (pool))) 17840ba35e7Swilly tarreau 17940ba35e7Swilly tarreau #define MVNETA_CAUSE_TXQ_ERROR_SHIFT 24 18040ba35e7Swilly tarreau #define MVNETA_CAUSE_TXQ_ERROR_ALL_MASK (0xFF << MVNETA_CAUSE_TXQ_ERROR_SHIFT) 18140ba35e7Swilly tarreau #define MVNETA_CAUSE_TXQ_ERROR_MASK(q) (1 << (MVNETA_CAUSE_TXQ_ERROR_SHIFT + (q))) 18240ba35e7Swilly tarreau 183c5aff182SThomas Petazzoni #define MVNETA_INTR_ENABLE 0x25b8 184c5aff182SThomas Petazzoni #define MVNETA_TXQ_INTR_ENABLE_ALL_MASK 0x0000ff00 185dc1aadf6SMarcin Wojtas #define MVNETA_RXQ_INTR_ENABLE_ALL_MASK 0x000000ff 18640ba35e7Swilly tarreau 187c5aff182SThomas Petazzoni #define MVNETA_RXQ_CMD 0x2680 188c5aff182SThomas Petazzoni #define MVNETA_RXQ_DISABLE_SHIFT 8 189c5aff182SThomas Petazzoni #define MVNETA_RXQ_ENABLE_MASK 0x000000ff 190c5aff182SThomas Petazzoni #define MVETH_TXQ_TOKEN_COUNT_REG(q) (0x2700 + ((q) << 4)) 191c5aff182SThomas Petazzoni #define MVETH_TXQ_TOKEN_CFG_REG(q) (0x2704 + ((q) << 4)) 192c5aff182SThomas Petazzoni #define MVNETA_GMAC_CTRL_0 0x2c00 193c5aff182SThomas Petazzoni #define MVNETA_GMAC_MAX_RX_SIZE_SHIFT 2 194c5aff182SThomas Petazzoni #define MVNETA_GMAC_MAX_RX_SIZE_MASK 0x7ffc 19522f4bf8aSRussell King #define MVNETA_GMAC0_PORT_1000BASE_X BIT(1) 196c5aff182SThomas Petazzoni #define MVNETA_GMAC0_PORT_ENABLE BIT(0) 197c5aff182SThomas Petazzoni #define MVNETA_GMAC_CTRL_2 0x2c08 198898b2970SStas Sergeev #define MVNETA_GMAC2_INBAND_AN_ENABLE BIT(0) 199a79121d3SThomas Petazzoni #define MVNETA_GMAC2_PCS_ENABLE BIT(3) 200c5aff182SThomas Petazzoni #define MVNETA_GMAC2_PORT_RGMII BIT(4) 201c5aff182SThomas Petazzoni #define MVNETA_GMAC2_PORT_RESET BIT(6) 202c5aff182SThomas Petazzoni #define MVNETA_GMAC_STATUS 0x2c10 203c5aff182SThomas Petazzoni #define MVNETA_GMAC_LINK_UP BIT(0) 204c5aff182SThomas Petazzoni #define MVNETA_GMAC_SPEED_1000 BIT(1) 205c5aff182SThomas Petazzoni #define MVNETA_GMAC_SPEED_100 BIT(2) 206c5aff182SThomas Petazzoni #define MVNETA_GMAC_FULL_DUPLEX BIT(3) 207c5aff182SThomas Petazzoni #define MVNETA_GMAC_RX_FLOW_CTRL_ENABLE BIT(4) 208c5aff182SThomas Petazzoni #define MVNETA_GMAC_TX_FLOW_CTRL_ENABLE BIT(5) 209c5aff182SThomas Petazzoni #define MVNETA_GMAC_RX_FLOW_CTRL_ACTIVE BIT(6) 210c5aff182SThomas Petazzoni #define MVNETA_GMAC_TX_FLOW_CTRL_ACTIVE BIT(7) 211503f9aa9SRussell King #define MVNETA_GMAC_AN_COMPLETE BIT(11) 212503f9aa9SRussell King #define MVNETA_GMAC_SYNC_OK BIT(14) 213c5aff182SThomas Petazzoni #define MVNETA_GMAC_AUTONEG_CONFIG 0x2c0c 214c5aff182SThomas Petazzoni #define MVNETA_GMAC_FORCE_LINK_DOWN BIT(0) 215c5aff182SThomas Petazzoni #define MVNETA_GMAC_FORCE_LINK_PASS BIT(1) 216898b2970SStas Sergeev #define MVNETA_GMAC_INBAND_AN_ENABLE BIT(2) 21722f4bf8aSRussell King #define MVNETA_GMAC_AN_BYPASS_ENABLE BIT(3) 21822f4bf8aSRussell King #define MVNETA_GMAC_INBAND_RESTART_AN BIT(4) 219c5aff182SThomas Petazzoni #define MVNETA_GMAC_CONFIG_MII_SPEED BIT(5) 220c5aff182SThomas Petazzoni #define MVNETA_GMAC_CONFIG_GMII_SPEED BIT(6) 22171408602SThomas Petazzoni #define MVNETA_GMAC_AN_SPEED_EN BIT(7) 22222f4bf8aSRussell King #define MVNETA_GMAC_CONFIG_FLOW_CTRL BIT(8) 22322f4bf8aSRussell King #define MVNETA_GMAC_ADVERT_SYM_FLOW_CTRL BIT(9) 224898b2970SStas Sergeev #define MVNETA_GMAC_AN_FLOW_CTRL_EN BIT(11) 225c5aff182SThomas Petazzoni #define MVNETA_GMAC_CONFIG_FULL_DUPLEX BIT(12) 22671408602SThomas Petazzoni #define MVNETA_GMAC_AN_DUPLEX_EN BIT(13) 227da58a931SMaxime Chevallier #define MVNETA_GMAC_CTRL_4 0x2c90 228da58a931SMaxime Chevallier #define MVNETA_GMAC4_SHORT_PREAMBLE_ENABLE BIT(1) 229e483911fSAndrew Lunn #define MVNETA_MIB_COUNTERS_BASE 0x3000 230c5aff182SThomas Petazzoni #define MVNETA_MIB_LATE_COLLISION 0x7c 231c5aff182SThomas Petazzoni #define MVNETA_DA_FILT_SPEC_MCAST 0x3400 232c5aff182SThomas Petazzoni #define MVNETA_DA_FILT_OTH_MCAST 0x3500 233c5aff182SThomas Petazzoni #define MVNETA_DA_FILT_UCAST_BASE 0x3600 234c5aff182SThomas Petazzoni #define MVNETA_TXQ_BASE_ADDR_REG(q) (0x3c00 + ((q) << 2)) 235c5aff182SThomas Petazzoni #define MVNETA_TXQ_SIZE_REG(q) (0x3c20 + ((q) << 2)) 236c5aff182SThomas Petazzoni #define MVNETA_TXQ_SENT_THRESH_ALL_MASK 0x3fff0000 237c5aff182SThomas Petazzoni #define MVNETA_TXQ_SENT_THRESH_MASK(coal) ((coal) << 16) 238c5aff182SThomas Petazzoni #define MVNETA_TXQ_UPDATE_REG(q) (0x3c60 + ((q) << 2)) 239c5aff182SThomas Petazzoni #define MVNETA_TXQ_DEC_SENT_SHIFT 16 2402a90f7e1SSimon Guinot #define MVNETA_TXQ_DEC_SENT_MASK 0xff 241c5aff182SThomas Petazzoni #define MVNETA_TXQ_STATUS_REG(q) (0x3c40 + ((q) << 2)) 242c5aff182SThomas Petazzoni #define MVNETA_TXQ_SENT_DESC_SHIFT 16 243c5aff182SThomas Petazzoni #define MVNETA_TXQ_SENT_DESC_MASK 0x3fff0000 244c5aff182SThomas Petazzoni #define MVNETA_PORT_TX_RESET 0x3cf0 245c5aff182SThomas Petazzoni #define MVNETA_PORT_TX_DMA_RESET BIT(0) 246c5aff182SThomas Petazzoni #define MVNETA_TX_MTU 0x3e0c 247c5aff182SThomas Petazzoni #define MVNETA_TX_TOKEN_SIZE 0x3e14 248c5aff182SThomas Petazzoni #define MVNETA_TX_TOKEN_SIZE_MAX 0xffffffff 249c5aff182SThomas Petazzoni #define MVNETA_TXQ_TOKEN_SIZE_REG(q) (0x3e40 + ((q) << 2)) 250c5aff182SThomas Petazzoni #define MVNETA_TXQ_TOKEN_SIZE_MAX 0x7fffffff 251c5aff182SThomas Petazzoni 2526d81f451SRussell King #define MVNETA_LPI_CTRL_0 0x2cc0 2536d81f451SRussell King #define MVNETA_LPI_CTRL_1 0x2cc4 2546d81f451SRussell King #define MVNETA_LPI_REQUEST_ENABLE BIT(0) 2556d81f451SRussell King #define MVNETA_LPI_CTRL_2 0x2cc8 2566d81f451SRussell King #define MVNETA_LPI_STATUS 0x2ccc 2576d81f451SRussell King 258c5aff182SThomas Petazzoni #define MVNETA_CAUSE_TXQ_SENT_DESC_ALL_MASK 0xff 259c5aff182SThomas Petazzoni 260c5aff182SThomas Petazzoni /* Descriptor ring Macros */ 261c5aff182SThomas Petazzoni #define MVNETA_QUEUE_NEXT_DESC(q, index) \ 262c5aff182SThomas Petazzoni (((index) < (q)->last_desc) ? ((index) + 1) : 0) 263c5aff182SThomas Petazzoni 264c5aff182SThomas Petazzoni /* Various constants */ 265c5aff182SThomas Petazzoni 266c5aff182SThomas Petazzoni /* Coalescing */ 26706708f81SDmitri Epshtein #define MVNETA_TXDONE_COAL_PKTS 0 /* interrupt per packet */ 268c5aff182SThomas Petazzoni #define MVNETA_RX_COAL_PKTS 32 269c5aff182SThomas Petazzoni #define MVNETA_RX_COAL_USEC 100 270c5aff182SThomas Petazzoni 2716a20c175SThomas Petazzoni /* The two bytes Marvell header. Either contains a special value used 272c5aff182SThomas Petazzoni * by Marvell switches when a specific hardware mode is enabled (not 273c5aff182SThomas Petazzoni * supported by this driver) or is filled automatically by zeroes on 274c5aff182SThomas Petazzoni * the RX side. Those two bytes being at the front of the Ethernet 275c5aff182SThomas Petazzoni * header, they allow to have the IP header aligned on a 4 bytes 276c5aff182SThomas Petazzoni * boundary automatically: the hardware skips those two bytes on its 277c5aff182SThomas Petazzoni * own. 278c5aff182SThomas Petazzoni */ 279c5aff182SThomas Petazzoni #define MVNETA_MH_SIZE 2 280c5aff182SThomas Petazzoni 281c5aff182SThomas Petazzoni #define MVNETA_VLAN_TAG_LEN 4 282c5aff182SThomas Petazzoni 2839110ee07SMarcin Wojtas #define MVNETA_TX_CSUM_DEF_SIZE 1600 284c5aff182SThomas Petazzoni #define MVNETA_TX_CSUM_MAX_SIZE 9800 285dc35a10fSMarcin Wojtas #define MVNETA_ACC_MODE_EXT1 1 286dc35a10fSMarcin Wojtas #define MVNETA_ACC_MODE_EXT2 2 287dc35a10fSMarcin Wojtas 288dc35a10fSMarcin Wojtas #define MVNETA_MAX_DECODE_WIN 6 289c5aff182SThomas Petazzoni 290c5aff182SThomas Petazzoni /* Timeout constants */ 291c5aff182SThomas Petazzoni #define MVNETA_TX_DISABLE_TIMEOUT_MSEC 1000 292c5aff182SThomas Petazzoni #define MVNETA_RX_DISABLE_TIMEOUT_MSEC 1000 293c5aff182SThomas Petazzoni #define MVNETA_TX_FIFO_EMPTY_TIMEOUT 10000 294c5aff182SThomas Petazzoni 295c5aff182SThomas Petazzoni #define MVNETA_TX_MTU_MAX 0x3ffff 296c5aff182SThomas Petazzoni 2979a401deaSGregory CLEMENT /* The RSS lookup table actually has 256 entries but we do not use 2989a401deaSGregory CLEMENT * them yet 2999a401deaSGregory CLEMENT */ 3009a401deaSGregory CLEMENT #define MVNETA_RSS_LU_TABLE_SIZE 1 3019a401deaSGregory CLEMENT 302c5aff182SThomas Petazzoni /* Max number of Rx descriptors */ 303c307e2a8SYelena Krivosheev #define MVNETA_MAX_RXD 512 304c5aff182SThomas Petazzoni 305c5aff182SThomas Petazzoni /* Max number of Tx descriptors */ 306c307e2a8SYelena Krivosheev #define MVNETA_MAX_TXD 1024 307c5aff182SThomas Petazzoni 3088eef5f97SEzequiel Garcia /* Max number of allowed TCP segments for software TSO */ 3098eef5f97SEzequiel Garcia #define MVNETA_MAX_TSO_SEGS 100 3108eef5f97SEzequiel Garcia 3118eef5f97SEzequiel Garcia #define MVNETA_MAX_SKB_DESCS (MVNETA_MAX_TSO_SEGS * 2 + MAX_SKB_FRAGS) 3128eef5f97SEzequiel Garcia 313c5aff182SThomas Petazzoni /* descriptor aligned size */ 314c5aff182SThomas Petazzoni #define MVNETA_DESC_ALIGNED_SIZE 32 315c5aff182SThomas Petazzoni 3168d5047cfSMarcin Wojtas /* Number of bytes to be taken into account by HW when putting incoming data 3178d5047cfSMarcin Wojtas * to the buffers. It is needed in case NET_SKB_PAD exceeds maximum packet 3188d5047cfSMarcin Wojtas * offset supported in MVNETA_RXQ_CONFIG_REG(q) registers. 3198d5047cfSMarcin Wojtas */ 3208d5047cfSMarcin Wojtas #define MVNETA_RX_PKT_OFFSET_CORRECTION 64 3218d5047cfSMarcin Wojtas 322c5aff182SThomas Petazzoni #define MVNETA_RX_PKT_SIZE(mtu) \ 323c5aff182SThomas Petazzoni ALIGN((mtu) + MVNETA_MH_SIZE + MVNETA_VLAN_TAG_LEN + \ 324c5aff182SThomas Petazzoni ETH_HLEN + ETH_FCS_LEN, \ 325c66e98c9SJisheng Zhang cache_line_size()) 326c5aff182SThomas Petazzoni 3270db51da7SLorenzo Bianconi #define MVNETA_SKB_HEADROOM (max(XDP_PACKET_HEADROOM, NET_SKB_PAD) + \ 3280db51da7SLorenzo Bianconi NET_IP_ALIGN) 3298dc9a088SLorenzo Bianconi #define MVNETA_SKB_PAD (SKB_DATA_ALIGN(sizeof(struct skb_shared_info) + \ 3300db51da7SLorenzo Bianconi MVNETA_SKB_HEADROOM)) 3318dc9a088SLorenzo Bianconi #define MVNETA_SKB_SIZE(len) (SKB_DATA_ALIGN(len) + MVNETA_SKB_PAD) 3328dc9a088SLorenzo Bianconi #define MVNETA_MAX_RX_BUF_SIZE (PAGE_SIZE - MVNETA_SKB_PAD) 3338dc9a088SLorenzo Bianconi 3342e3173a3SEzequiel Garcia #define IS_TSO_HEADER(txq, addr) \ 3352e3173a3SEzequiel Garcia ((addr >= txq->tso_hdrs_phys) && \ 3362e3173a3SEzequiel Garcia (addr < txq->tso_hdrs_phys + txq->size * TSO_HEADER_SIZE)) 3372e3173a3SEzequiel Garcia 338dc35a10fSMarcin Wojtas #define MVNETA_RX_GET_BM_POOL_ID(rxd) \ 339dc35a10fSMarcin Wojtas (((rxd)->status & MVNETA_RXD_BM_POOL_MASK) >> MVNETA_RXD_BM_POOL_SHIFT) 340c5aff182SThomas Petazzoni 3416d81f451SRussell King enum { 3426d81f451SRussell King ETHTOOL_STAT_EEE_WAKEUP, 34317a96da6SGregory CLEMENT ETHTOOL_STAT_SKB_ALLOC_ERR, 34417a96da6SGregory CLEMENT ETHTOOL_STAT_REFILL_ERR, 3456d81f451SRussell King ETHTOOL_MAX_STATS, 3466d81f451SRussell King }; 3476d81f451SRussell King 3489b0cdefaSRussell King struct mvneta_statistic { 3499b0cdefaSRussell King unsigned short offset; 3509b0cdefaSRussell King unsigned short type; 3519b0cdefaSRussell King const char name[ETH_GSTRING_LEN]; 3529b0cdefaSRussell King }; 3539b0cdefaSRussell King 3549b0cdefaSRussell King #define T_REG_32 32 3559b0cdefaSRussell King #define T_REG_64 64 3566d81f451SRussell King #define T_SW 1 3579b0cdefaSRussell King 3580db51da7SLorenzo Bianconi #define MVNETA_XDP_PASS BIT(0) 3590db51da7SLorenzo Bianconi #define MVNETA_XDP_DROPPED BIT(1) 3600db51da7SLorenzo Bianconi #define MVNETA_XDP_TX BIT(2) 3610db51da7SLorenzo Bianconi #define MVNETA_XDP_REDIR BIT(3) 3620db51da7SLorenzo Bianconi 3639b0cdefaSRussell King static const struct mvneta_statistic mvneta_statistics[] = { 3649b0cdefaSRussell King { 0x3000, T_REG_64, "good_octets_received", }, 3659b0cdefaSRussell King { 0x3010, T_REG_32, "good_frames_received", }, 3669b0cdefaSRussell King { 0x3008, T_REG_32, "bad_octets_received", }, 3679b0cdefaSRussell King { 0x3014, T_REG_32, "bad_frames_received", }, 3689b0cdefaSRussell King { 0x3018, T_REG_32, "broadcast_frames_received", }, 3699b0cdefaSRussell King { 0x301c, T_REG_32, "multicast_frames_received", }, 3709b0cdefaSRussell King { 0x3050, T_REG_32, "unrec_mac_control_received", }, 3719b0cdefaSRussell King { 0x3058, T_REG_32, "good_fc_received", }, 3729b0cdefaSRussell King { 0x305c, T_REG_32, "bad_fc_received", }, 3739b0cdefaSRussell King { 0x3060, T_REG_32, "undersize_received", }, 3749b0cdefaSRussell King { 0x3064, T_REG_32, "fragments_received", }, 3759b0cdefaSRussell King { 0x3068, T_REG_32, "oversize_received", }, 3769b0cdefaSRussell King { 0x306c, T_REG_32, "jabber_received", }, 3779b0cdefaSRussell King { 0x3070, T_REG_32, "mac_receive_error", }, 3789b0cdefaSRussell King { 0x3074, T_REG_32, "bad_crc_event", }, 3799b0cdefaSRussell King { 0x3078, T_REG_32, "collision", }, 3809b0cdefaSRussell King { 0x307c, T_REG_32, "late_collision", }, 3819b0cdefaSRussell King { 0x2484, T_REG_32, "rx_discard", }, 3829b0cdefaSRussell King { 0x2488, T_REG_32, "rx_overrun", }, 3839b0cdefaSRussell King { 0x3020, T_REG_32, "frames_64_octets", }, 3849b0cdefaSRussell King { 0x3024, T_REG_32, "frames_65_to_127_octets", }, 3859b0cdefaSRussell King { 0x3028, T_REG_32, "frames_128_to_255_octets", }, 3869b0cdefaSRussell King { 0x302c, T_REG_32, "frames_256_to_511_octets", }, 3879b0cdefaSRussell King { 0x3030, T_REG_32, "frames_512_to_1023_octets", }, 3889b0cdefaSRussell King { 0x3034, T_REG_32, "frames_1024_to_max_octets", }, 3899b0cdefaSRussell King { 0x3038, T_REG_64, "good_octets_sent", }, 3909b0cdefaSRussell King { 0x3040, T_REG_32, "good_frames_sent", }, 3919b0cdefaSRussell King { 0x3044, T_REG_32, "excessive_collision", }, 3929b0cdefaSRussell King { 0x3048, T_REG_32, "multicast_frames_sent", }, 3939b0cdefaSRussell King { 0x304c, T_REG_32, "broadcast_frames_sent", }, 3949b0cdefaSRussell King { 0x3054, T_REG_32, "fc_sent", }, 3959b0cdefaSRussell King { 0x300c, T_REG_32, "internal_mac_transmit_err", }, 3966d81f451SRussell King { ETHTOOL_STAT_EEE_WAKEUP, T_SW, "eee_wakeup_errors", }, 39717a96da6SGregory CLEMENT { ETHTOOL_STAT_SKB_ALLOC_ERR, T_SW, "skb_alloc_errors", }, 39817a96da6SGregory CLEMENT { ETHTOOL_STAT_REFILL_ERR, T_SW, "refill_errors", }, 3999b0cdefaSRussell King }; 4009b0cdefaSRussell King 40174c41b04Swilly tarreau struct mvneta_pcpu_stats { 402c5aff182SThomas Petazzoni struct u64_stats_sync syncp; 40374c41b04Swilly tarreau u64 rx_packets; 40474c41b04Swilly tarreau u64 rx_bytes; 40574c41b04Swilly tarreau u64 tx_packets; 40674c41b04Swilly tarreau u64 tx_bytes; 407c5aff182SThomas Petazzoni }; 408c5aff182SThomas Petazzoni 40912bb03b4SMaxime Ripard struct mvneta_pcpu_port { 41012bb03b4SMaxime Ripard /* Pointer to the shared port */ 41112bb03b4SMaxime Ripard struct mvneta_port *pp; 41212bb03b4SMaxime Ripard 41312bb03b4SMaxime Ripard /* Pointer to the CPU-local NAPI struct */ 41412bb03b4SMaxime Ripard struct napi_struct napi; 41512bb03b4SMaxime Ripard 41612bb03b4SMaxime Ripard /* Cause of the previous interrupt */ 41712bb03b4SMaxime Ripard u32 cause_rx_tx; 41812bb03b4SMaxime Ripard }; 41912bb03b4SMaxime Ripard 420c5aff182SThomas Petazzoni struct mvneta_port { 421dc35a10fSMarcin Wojtas u8 id; 42212bb03b4SMaxime Ripard struct mvneta_pcpu_port __percpu *ports; 42312bb03b4SMaxime Ripard struct mvneta_pcpu_stats __percpu *stats; 42412bb03b4SMaxime Ripard 425c5aff182SThomas Petazzoni int pkt_size; 426c5aff182SThomas Petazzoni void __iomem *base; 427c5aff182SThomas Petazzoni struct mvneta_rx_queue *rxqs; 428c5aff182SThomas Petazzoni struct mvneta_tx_queue *txqs; 429c5aff182SThomas Petazzoni struct net_device *dev; 43084a3f4dbSSebastian Andrzej Siewior struct hlist_node node_online; 43184a3f4dbSSebastian Andrzej Siewior struct hlist_node node_dead; 43290b74c01SGregory CLEMENT int rxq_def; 4335888511eSGregory CLEMENT /* Protect the access to the percpu interrupt registers, 4345888511eSGregory CLEMENT * ensuring that the configuration remains coherent. 4355888511eSGregory CLEMENT */ 4365888511eSGregory CLEMENT spinlock_t lock; 437120cfa50SGregory CLEMENT bool is_stopped; 438c5aff182SThomas Petazzoni 4392636ac3cSMarcin Wojtas u32 cause_rx_tx; 4402636ac3cSMarcin Wojtas struct napi_struct napi; 4412636ac3cSMarcin Wojtas 4420db51da7SLorenzo Bianconi struct bpf_prog *xdp_prog; 4430db51da7SLorenzo Bianconi 444c5aff182SThomas Petazzoni /* Core clock */ 445189dd626SThomas Petazzoni struct clk *clk; 44615cc4a4aSJisheng Zhang /* AXI clock */ 44715cc4a4aSJisheng Zhang struct clk *clk_bus; 448c5aff182SThomas Petazzoni u8 mcast_count[256]; 449c5aff182SThomas Petazzoni u16 tx_ring_size; 450c5aff182SThomas Petazzoni u16 rx_ring_size; 451c5aff182SThomas Petazzoni 452c5aff182SThomas Petazzoni phy_interface_t phy_interface; 453503f9aa9SRussell King struct device_node *dn; 454b65657fcSSimon Guinot unsigned int tx_csum_limit; 455503f9aa9SRussell King struct phylink *phylink; 45644cc27e4SIoana Ciornei struct phylink_config phylink_config; 457a10c1c81SRussell King struct phy *comphy; 4589b0cdefaSRussell King 459dc35a10fSMarcin Wojtas struct mvneta_bm *bm_priv; 460dc35a10fSMarcin Wojtas struct mvneta_bm_pool *pool_long; 461dc35a10fSMarcin Wojtas struct mvneta_bm_pool *pool_short; 462dc35a10fSMarcin Wojtas int bm_win_id; 463dc35a10fSMarcin Wojtas 4646d81f451SRussell King bool eee_enabled; 4656d81f451SRussell King bool eee_active; 4666d81f451SRussell King bool tx_lpi_enabled; 4676d81f451SRussell King 4689b0cdefaSRussell King u64 ethtool_stats[ARRAY_SIZE(mvneta_statistics)]; 4699a401deaSGregory CLEMENT 4709a401deaSGregory CLEMENT u32 indir[MVNETA_RSS_LU_TABLE_SIZE]; 4712636ac3cSMarcin Wojtas 4722636ac3cSMarcin Wojtas /* Flags for special SoC configurations */ 4732636ac3cSMarcin Wojtas bool neta_armada3700; 4748d5047cfSMarcin Wojtas u16 rx_offset_correction; 4759768b45cSJane Li const struct mbus_dram_target_info *dram_target_info; 476c5aff182SThomas Petazzoni }; 477c5aff182SThomas Petazzoni 4786a20c175SThomas Petazzoni /* The mvneta_tx_desc and mvneta_rx_desc structures describe the 479c5aff182SThomas Petazzoni * layout of the transmit and reception DMA descriptors, and their 480c5aff182SThomas Petazzoni * layout is therefore defined by the hardware design 481c5aff182SThomas Petazzoni */ 4826083ed44SThomas Petazzoni 483c5aff182SThomas Petazzoni #define MVNETA_TX_L3_OFF_SHIFT 0 484c5aff182SThomas Petazzoni #define MVNETA_TX_IP_HLEN_SHIFT 8 485c5aff182SThomas Petazzoni #define MVNETA_TX_L4_UDP BIT(16) 486c5aff182SThomas Petazzoni #define MVNETA_TX_L3_IP6 BIT(17) 487c5aff182SThomas Petazzoni #define MVNETA_TXD_IP_CSUM BIT(18) 488c5aff182SThomas Petazzoni #define MVNETA_TXD_Z_PAD BIT(19) 489c5aff182SThomas Petazzoni #define MVNETA_TXD_L_DESC BIT(20) 490c5aff182SThomas Petazzoni #define MVNETA_TXD_F_DESC BIT(21) 491c5aff182SThomas Petazzoni #define MVNETA_TXD_FLZ_DESC (MVNETA_TXD_Z_PAD | \ 492c5aff182SThomas Petazzoni MVNETA_TXD_L_DESC | \ 493c5aff182SThomas Petazzoni MVNETA_TXD_F_DESC) 494c5aff182SThomas Petazzoni #define MVNETA_TX_L4_CSUM_FULL BIT(30) 495c5aff182SThomas Petazzoni #define MVNETA_TX_L4_CSUM_NOT BIT(31) 496c5aff182SThomas Petazzoni 497c5aff182SThomas Petazzoni #define MVNETA_RXD_ERR_CRC 0x0 498dc35a10fSMarcin Wojtas #define MVNETA_RXD_BM_POOL_SHIFT 13 499dc35a10fSMarcin Wojtas #define MVNETA_RXD_BM_POOL_MASK (BIT(13) | BIT(14)) 500c5aff182SThomas Petazzoni #define MVNETA_RXD_ERR_SUMMARY BIT(16) 501c5aff182SThomas Petazzoni #define MVNETA_RXD_ERR_OVERRUN BIT(17) 502c5aff182SThomas Petazzoni #define MVNETA_RXD_ERR_LEN BIT(18) 503c5aff182SThomas Petazzoni #define MVNETA_RXD_ERR_RESOURCE (BIT(17) | BIT(18)) 504c5aff182SThomas Petazzoni #define MVNETA_RXD_ERR_CODE_MASK (BIT(17) | BIT(18)) 505c5aff182SThomas Petazzoni #define MVNETA_RXD_L3_IP4 BIT(25) 506562e2f46SYelena Krivosheev #define MVNETA_RXD_LAST_DESC BIT(26) 507562e2f46SYelena Krivosheev #define MVNETA_RXD_FIRST_DESC BIT(27) 508562e2f46SYelena Krivosheev #define MVNETA_RXD_FIRST_LAST_DESC (MVNETA_RXD_FIRST_DESC | \ 509562e2f46SYelena Krivosheev MVNETA_RXD_LAST_DESC) 510c5aff182SThomas Petazzoni #define MVNETA_RXD_L4_CSUM_OK BIT(30) 511c5aff182SThomas Petazzoni 5129ad8fef6SThomas Petazzoni #if defined(__LITTLE_ENDIAN) 5136083ed44SThomas Petazzoni struct mvneta_tx_desc { 5146083ed44SThomas Petazzoni u32 command; /* Options used by HW for packet transmitting.*/ 515fbd1d524SAlexandre Belloni u16 reserved1; /* csum_l4 (for future use) */ 5166083ed44SThomas Petazzoni u16 data_size; /* Data size of transmitted packet in bytes */ 5176083ed44SThomas Petazzoni u32 buf_phys_addr; /* Physical addr of transmitted buffer */ 5186083ed44SThomas Petazzoni u32 reserved2; /* hw_cmd - (for future use, PMT) */ 5196083ed44SThomas Petazzoni u32 reserved3[4]; /* Reserved - (for future use) */ 5206083ed44SThomas Petazzoni }; 5216083ed44SThomas Petazzoni 5226083ed44SThomas Petazzoni struct mvneta_rx_desc { 5236083ed44SThomas Petazzoni u32 status; /* Info about received packet */ 524c5aff182SThomas Petazzoni u16 reserved1; /* pnc_info - (for future use, PnC) */ 525c5aff182SThomas Petazzoni u16 data_size; /* Size of received packet in bytes */ 5266083ed44SThomas Petazzoni 527c5aff182SThomas Petazzoni u32 buf_phys_addr; /* Physical address of the buffer */ 528c5aff182SThomas Petazzoni u32 reserved2; /* pnc_flow_id (for future use, PnC) */ 5296083ed44SThomas Petazzoni 530c5aff182SThomas Petazzoni u32 buf_cookie; /* cookie for access to RX buffer in rx path */ 531c5aff182SThomas Petazzoni u16 reserved3; /* prefetch_cmd, for future use */ 532c5aff182SThomas Petazzoni u16 reserved4; /* csum_l4 - (for future use, PnC) */ 5336083ed44SThomas Petazzoni 534c5aff182SThomas Petazzoni u32 reserved5; /* pnc_extra PnC (for future use, PnC) */ 535c5aff182SThomas Petazzoni u32 reserved6; /* hw_cmd (for future use, PnC and HWF) */ 536c5aff182SThomas Petazzoni }; 5379ad8fef6SThomas Petazzoni #else 5389ad8fef6SThomas Petazzoni struct mvneta_tx_desc { 5399ad8fef6SThomas Petazzoni u16 data_size; /* Data size of transmitted packet in bytes */ 540fbd1d524SAlexandre Belloni u16 reserved1; /* csum_l4 (for future use) */ 5419ad8fef6SThomas Petazzoni u32 command; /* Options used by HW for packet transmitting.*/ 5429ad8fef6SThomas Petazzoni u32 reserved2; /* hw_cmd - (for future use, PMT) */ 5439ad8fef6SThomas Petazzoni u32 buf_phys_addr; /* Physical addr of transmitted buffer */ 5449ad8fef6SThomas Petazzoni u32 reserved3[4]; /* Reserved - (for future use) */ 5459ad8fef6SThomas Petazzoni }; 5469ad8fef6SThomas Petazzoni 5479ad8fef6SThomas Petazzoni struct mvneta_rx_desc { 5489ad8fef6SThomas Petazzoni u16 data_size; /* Size of received packet in bytes */ 5499ad8fef6SThomas Petazzoni u16 reserved1; /* pnc_info - (for future use, PnC) */ 5509ad8fef6SThomas Petazzoni u32 status; /* Info about received packet */ 5519ad8fef6SThomas Petazzoni 5529ad8fef6SThomas Petazzoni u32 reserved2; /* pnc_flow_id (for future use, PnC) */ 5539ad8fef6SThomas Petazzoni u32 buf_phys_addr; /* Physical address of the buffer */ 5549ad8fef6SThomas Petazzoni 5559ad8fef6SThomas Petazzoni u16 reserved4; /* csum_l4 - (for future use, PnC) */ 5569ad8fef6SThomas Petazzoni u16 reserved3; /* prefetch_cmd, for future use */ 5579ad8fef6SThomas Petazzoni u32 buf_cookie; /* cookie for access to RX buffer in rx path */ 5589ad8fef6SThomas Petazzoni 5599ad8fef6SThomas Petazzoni u32 reserved5; /* pnc_extra PnC (for future use, PnC) */ 5609ad8fef6SThomas Petazzoni u32 reserved6; /* hw_cmd (for future use, PnC and HWF) */ 5619ad8fef6SThomas Petazzoni }; 5629ad8fef6SThomas Petazzoni #endif 563c5aff182SThomas Petazzoni 5649e58c8b4SLorenzo Bianconi enum mvneta_tx_buf_type { 5659e58c8b4SLorenzo Bianconi MVNETA_TYPE_SKB, 5669e58c8b4SLorenzo Bianconi MVNETA_TYPE_XDP_TX, 5679e58c8b4SLorenzo Bianconi MVNETA_TYPE_XDP_NDO, 5689e58c8b4SLorenzo Bianconi }; 5699e58c8b4SLorenzo Bianconi 5709e58c8b4SLorenzo Bianconi struct mvneta_tx_buf { 5719e58c8b4SLorenzo Bianconi enum mvneta_tx_buf_type type; 5729e58c8b4SLorenzo Bianconi union { 5739e58c8b4SLorenzo Bianconi struct xdp_frame *xdpf; 5749e58c8b4SLorenzo Bianconi struct sk_buff *skb; 5759e58c8b4SLorenzo Bianconi }; 5769e58c8b4SLorenzo Bianconi }; 5779e58c8b4SLorenzo Bianconi 578c5aff182SThomas Petazzoni struct mvneta_tx_queue { 579c5aff182SThomas Petazzoni /* Number of this TX queue, in the range 0-7 */ 580c5aff182SThomas Petazzoni u8 id; 581c5aff182SThomas Petazzoni 582c5aff182SThomas Petazzoni /* Number of TX DMA descriptors in the descriptor ring */ 583c5aff182SThomas Petazzoni int size; 584c5aff182SThomas Petazzoni 585c5aff182SThomas Petazzoni /* Number of currently used TX DMA descriptor in the 5866a20c175SThomas Petazzoni * descriptor ring 5876a20c175SThomas Petazzoni */ 588c5aff182SThomas Petazzoni int count; 5892a90f7e1SSimon Guinot int pending; 5908eef5f97SEzequiel Garcia int tx_stop_threshold; 5918eef5f97SEzequiel Garcia int tx_wake_threshold; 592c5aff182SThomas Petazzoni 5939e58c8b4SLorenzo Bianconi /* Array of transmitted buffers */ 5949e58c8b4SLorenzo Bianconi struct mvneta_tx_buf *buf; 595c5aff182SThomas Petazzoni 596c5aff182SThomas Petazzoni /* Index of last TX DMA descriptor that was inserted */ 597c5aff182SThomas Petazzoni int txq_put_index; 598c5aff182SThomas Petazzoni 599c5aff182SThomas Petazzoni /* Index of the TX DMA descriptor to be cleaned up */ 600c5aff182SThomas Petazzoni int txq_get_index; 601c5aff182SThomas Petazzoni 602c5aff182SThomas Petazzoni u32 done_pkts_coal; 603c5aff182SThomas Petazzoni 604c5aff182SThomas Petazzoni /* Virtual address of the TX DMA descriptors array */ 605c5aff182SThomas Petazzoni struct mvneta_tx_desc *descs; 606c5aff182SThomas Petazzoni 607c5aff182SThomas Petazzoni /* DMA address of the TX DMA descriptors array */ 608c5aff182SThomas Petazzoni dma_addr_t descs_phys; 609c5aff182SThomas Petazzoni 610c5aff182SThomas Petazzoni /* Index of the last TX DMA descriptor */ 611c5aff182SThomas Petazzoni int last_desc; 612c5aff182SThomas Petazzoni 613c5aff182SThomas Petazzoni /* Index of the next TX DMA descriptor to process */ 614c5aff182SThomas Petazzoni int next_desc_to_proc; 6152adb719dSEzequiel Garcia 6162adb719dSEzequiel Garcia /* DMA buffers for TSO headers */ 6172adb719dSEzequiel Garcia char *tso_hdrs; 6182adb719dSEzequiel Garcia 6192adb719dSEzequiel Garcia /* DMA address of TSO headers */ 6202adb719dSEzequiel Garcia dma_addr_t tso_hdrs_phys; 62150bf8cb6SGregory CLEMENT 62250bf8cb6SGregory CLEMENT /* Affinity mask for CPUs*/ 62350bf8cb6SGregory CLEMENT cpumask_t affinity_mask; 624c5aff182SThomas Petazzoni }; 625c5aff182SThomas Petazzoni 626c5aff182SThomas Petazzoni struct mvneta_rx_queue { 627c5aff182SThomas Petazzoni /* rx queue number, in the range 0-7 */ 628c5aff182SThomas Petazzoni u8 id; 629c5aff182SThomas Petazzoni 630c5aff182SThomas Petazzoni /* num of rx descriptors in the rx descriptor ring */ 631c5aff182SThomas Petazzoni int size; 632c5aff182SThomas Petazzoni 633c5aff182SThomas Petazzoni u32 pkts_coal; 634c5aff182SThomas Petazzoni u32 time_coal; 635c5aff182SThomas Petazzoni 636568a3fa2SLorenzo Bianconi /* page_pool */ 637568a3fa2SLorenzo Bianconi struct page_pool *page_pool; 638568a3fa2SLorenzo Bianconi struct xdp_rxq_info xdp_rxq; 639568a3fa2SLorenzo Bianconi 640f88bee1cSGregory CLEMENT /* Virtual address of the RX buffer */ 641f88bee1cSGregory CLEMENT void **buf_virt_addr; 642f88bee1cSGregory CLEMENT 643c5aff182SThomas Petazzoni /* Virtual address of the RX DMA descriptors array */ 644c5aff182SThomas Petazzoni struct mvneta_rx_desc *descs; 645c5aff182SThomas Petazzoni 646c5aff182SThomas Petazzoni /* DMA address of the RX DMA descriptors array */ 647c5aff182SThomas Petazzoni dma_addr_t descs_phys; 648c5aff182SThomas Petazzoni 649c5aff182SThomas Petazzoni /* Index of the last RX DMA descriptor */ 650c5aff182SThomas Petazzoni int last_desc; 651c5aff182SThomas Petazzoni 652c5aff182SThomas Petazzoni /* Index of the next RX DMA descriptor to process */ 653c5aff182SThomas Petazzoni int next_desc_to_proc; 65417a96da6SGregory CLEMENT 655562e2f46SYelena Krivosheev /* Index of first RX DMA descriptor to refill */ 656562e2f46SYelena Krivosheev int first_to_refill; 657562e2f46SYelena Krivosheev u32 refill_num; 658562e2f46SYelena Krivosheev 659562e2f46SYelena Krivosheev /* pointer to uncomplete skb buffer */ 660562e2f46SYelena Krivosheev struct sk_buff *skb; 661562e2f46SYelena Krivosheev int left_size; 662562e2f46SYelena Krivosheev 66317a96da6SGregory CLEMENT /* error counters */ 66417a96da6SGregory CLEMENT u32 skb_alloc_err; 66517a96da6SGregory CLEMENT u32 refill_err; 666c5aff182SThomas Petazzoni }; 667c5aff182SThomas Petazzoni 66884a3f4dbSSebastian Andrzej Siewior static enum cpuhp_state online_hpstate; 669edadb7faSEzequiel Garcia /* The hardware supports eight (8) rx queues, but we are only allowing 670edadb7faSEzequiel Garcia * the first one to be used. Therefore, let's just allocate one queue. 671edadb7faSEzequiel Garcia */ 672d8936657SMaxime Ripard static int rxq_number = 8; 673c5aff182SThomas Petazzoni static int txq_number = 8; 674c5aff182SThomas Petazzoni 675c5aff182SThomas Petazzoni static int rxq_def; 676c5aff182SThomas Petazzoni 677f19fadfcSwilly tarreau static int rx_copybreak __read_mostly = 256; 678f19fadfcSwilly tarreau 679dc35a10fSMarcin Wojtas /* HW BM need that each port be identify by a unique ID */ 680dc35a10fSMarcin Wojtas static int global_port_id; 681dc35a10fSMarcin Wojtas 682c5aff182SThomas Petazzoni #define MVNETA_DRIVER_NAME "mvneta" 683c5aff182SThomas Petazzoni #define MVNETA_DRIVER_VERSION "1.0" 684c5aff182SThomas Petazzoni 685c5aff182SThomas Petazzoni /* Utility/helper methods */ 686c5aff182SThomas Petazzoni 687c5aff182SThomas Petazzoni /* Write helper method */ 688c5aff182SThomas Petazzoni static void mvreg_write(struct mvneta_port *pp, u32 offset, u32 data) 689c5aff182SThomas Petazzoni { 690c5aff182SThomas Petazzoni writel(data, pp->base + offset); 691c5aff182SThomas Petazzoni } 692c5aff182SThomas Petazzoni 693c5aff182SThomas Petazzoni /* Read helper method */ 694c5aff182SThomas Petazzoni static u32 mvreg_read(struct mvneta_port *pp, u32 offset) 695c5aff182SThomas Petazzoni { 696c5aff182SThomas Petazzoni return readl(pp->base + offset); 697c5aff182SThomas Petazzoni } 698c5aff182SThomas Petazzoni 699c5aff182SThomas Petazzoni /* Increment txq get counter */ 700c5aff182SThomas Petazzoni static void mvneta_txq_inc_get(struct mvneta_tx_queue *txq) 701c5aff182SThomas Petazzoni { 702c5aff182SThomas Petazzoni txq->txq_get_index++; 703c5aff182SThomas Petazzoni if (txq->txq_get_index == txq->size) 704c5aff182SThomas Petazzoni txq->txq_get_index = 0; 705c5aff182SThomas Petazzoni } 706c5aff182SThomas Petazzoni 707c5aff182SThomas Petazzoni /* Increment txq put counter */ 708c5aff182SThomas Petazzoni static void mvneta_txq_inc_put(struct mvneta_tx_queue *txq) 709c5aff182SThomas Petazzoni { 710c5aff182SThomas Petazzoni txq->txq_put_index++; 711c5aff182SThomas Petazzoni if (txq->txq_put_index == txq->size) 712c5aff182SThomas Petazzoni txq->txq_put_index = 0; 713c5aff182SThomas Petazzoni } 714c5aff182SThomas Petazzoni 715c5aff182SThomas Petazzoni 716c5aff182SThomas Petazzoni /* Clear all MIB counters */ 717c5aff182SThomas Petazzoni static void mvneta_mib_counters_clear(struct mvneta_port *pp) 718c5aff182SThomas Petazzoni { 719c5aff182SThomas Petazzoni int i; 720c5aff182SThomas Petazzoni u32 dummy; 721c5aff182SThomas Petazzoni 722c5aff182SThomas Petazzoni /* Perform dummy reads from MIB counters */ 723c5aff182SThomas Petazzoni for (i = 0; i < MVNETA_MIB_LATE_COLLISION; i += 4) 724c5aff182SThomas Petazzoni dummy = mvreg_read(pp, (MVNETA_MIB_COUNTERS_BASE + i)); 725e483911fSAndrew Lunn dummy = mvreg_read(pp, MVNETA_RX_DISCARD_FRAME_COUNT); 726e483911fSAndrew Lunn dummy = mvreg_read(pp, MVNETA_OVERRUN_FRAME_COUNT); 727c5aff182SThomas Petazzoni } 728c5aff182SThomas Petazzoni 729c5aff182SThomas Petazzoni /* Get System Network Statistics */ 730bc1f4470Sstephen hemminger static void 7312dc0d2b4SBaoyou Xie mvneta_get_stats64(struct net_device *dev, 732c5aff182SThomas Petazzoni struct rtnl_link_stats64 *stats) 733c5aff182SThomas Petazzoni { 734c5aff182SThomas Petazzoni struct mvneta_port *pp = netdev_priv(dev); 735c5aff182SThomas Petazzoni unsigned int start; 73674c41b04Swilly tarreau int cpu; 737c5aff182SThomas Petazzoni 73874c41b04Swilly tarreau for_each_possible_cpu(cpu) { 73974c41b04Swilly tarreau struct mvneta_pcpu_stats *cpu_stats; 74074c41b04Swilly tarreau u64 rx_packets; 74174c41b04Swilly tarreau u64 rx_bytes; 74274c41b04Swilly tarreau u64 tx_packets; 74374c41b04Swilly tarreau u64 tx_bytes; 744c5aff182SThomas Petazzoni 74574c41b04Swilly tarreau cpu_stats = per_cpu_ptr(pp->stats, cpu); 746c5aff182SThomas Petazzoni do { 74757a7744eSEric W. Biederman start = u64_stats_fetch_begin_irq(&cpu_stats->syncp); 74874c41b04Swilly tarreau rx_packets = cpu_stats->rx_packets; 74974c41b04Swilly tarreau rx_bytes = cpu_stats->rx_bytes; 75074c41b04Swilly tarreau tx_packets = cpu_stats->tx_packets; 75174c41b04Swilly tarreau tx_bytes = cpu_stats->tx_bytes; 75257a7744eSEric W. Biederman } while (u64_stats_fetch_retry_irq(&cpu_stats->syncp, start)); 753c5aff182SThomas Petazzoni 75474c41b04Swilly tarreau stats->rx_packets += rx_packets; 75574c41b04Swilly tarreau stats->rx_bytes += rx_bytes; 75674c41b04Swilly tarreau stats->tx_packets += tx_packets; 75774c41b04Swilly tarreau stats->tx_bytes += tx_bytes; 75874c41b04Swilly tarreau } 759c5aff182SThomas Petazzoni 760c5aff182SThomas Petazzoni stats->rx_errors = dev->stats.rx_errors; 761c5aff182SThomas Petazzoni stats->rx_dropped = dev->stats.rx_dropped; 762c5aff182SThomas Petazzoni 763c5aff182SThomas Petazzoni stats->tx_dropped = dev->stats.tx_dropped; 764c5aff182SThomas Petazzoni } 765c5aff182SThomas Petazzoni 766c5aff182SThomas Petazzoni /* Rx descriptors helper methods */ 767c5aff182SThomas Petazzoni 7685428213cSwilly tarreau /* Checks whether the RX descriptor having this status is both the first 7695428213cSwilly tarreau * and the last descriptor for the RX packet. Each RX packet is currently 770c5aff182SThomas Petazzoni * received through a single RX descriptor, so not having each RX 771c5aff182SThomas Petazzoni * descriptor with its first and last bits set is an error 772c5aff182SThomas Petazzoni */ 7735428213cSwilly tarreau static int mvneta_rxq_desc_is_first_last(u32 status) 774c5aff182SThomas Petazzoni { 7755428213cSwilly tarreau return (status & MVNETA_RXD_FIRST_LAST_DESC) == 776c5aff182SThomas Petazzoni MVNETA_RXD_FIRST_LAST_DESC; 777c5aff182SThomas Petazzoni } 778c5aff182SThomas Petazzoni 779c5aff182SThomas Petazzoni /* Add number of descriptors ready to receive new packets */ 780c5aff182SThomas Petazzoni static void mvneta_rxq_non_occup_desc_add(struct mvneta_port *pp, 781c5aff182SThomas Petazzoni struct mvneta_rx_queue *rxq, 782c5aff182SThomas Petazzoni int ndescs) 783c5aff182SThomas Petazzoni { 784c5aff182SThomas Petazzoni /* Only MVNETA_RXQ_ADD_NON_OCCUPIED_MAX (255) descriptors can 7856a20c175SThomas Petazzoni * be added at once 7866a20c175SThomas Petazzoni */ 787c5aff182SThomas Petazzoni while (ndescs > MVNETA_RXQ_ADD_NON_OCCUPIED_MAX) { 788c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id), 789c5aff182SThomas Petazzoni (MVNETA_RXQ_ADD_NON_OCCUPIED_MAX << 790c5aff182SThomas Petazzoni MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT)); 791c5aff182SThomas Petazzoni ndescs -= MVNETA_RXQ_ADD_NON_OCCUPIED_MAX; 792c5aff182SThomas Petazzoni } 793c5aff182SThomas Petazzoni 794c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id), 795c5aff182SThomas Petazzoni (ndescs << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT)); 796c5aff182SThomas Petazzoni } 797c5aff182SThomas Petazzoni 798c5aff182SThomas Petazzoni /* Get number of RX descriptors occupied by received packets */ 799c5aff182SThomas Petazzoni static int mvneta_rxq_busy_desc_num_get(struct mvneta_port *pp, 800c5aff182SThomas Petazzoni struct mvneta_rx_queue *rxq) 801c5aff182SThomas Petazzoni { 802c5aff182SThomas Petazzoni u32 val; 803c5aff182SThomas Petazzoni 804c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_RXQ_STATUS_REG(rxq->id)); 805c5aff182SThomas Petazzoni return val & MVNETA_RXQ_OCCUPIED_ALL_MASK; 806c5aff182SThomas Petazzoni } 807c5aff182SThomas Petazzoni 8086a20c175SThomas Petazzoni /* Update num of rx desc called upon return from rx path or 809c5aff182SThomas Petazzoni * from mvneta_rxq_drop_pkts(). 810c5aff182SThomas Petazzoni */ 811c5aff182SThomas Petazzoni static void mvneta_rxq_desc_num_update(struct mvneta_port *pp, 812c5aff182SThomas Petazzoni struct mvneta_rx_queue *rxq, 813c5aff182SThomas Petazzoni int rx_done, int rx_filled) 814c5aff182SThomas Petazzoni { 815c5aff182SThomas Petazzoni u32 val; 816c5aff182SThomas Petazzoni 817c5aff182SThomas Petazzoni if ((rx_done <= 0xff) && (rx_filled <= 0xff)) { 818c5aff182SThomas Petazzoni val = rx_done | 819c5aff182SThomas Petazzoni (rx_filled << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT); 820c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id), val); 821c5aff182SThomas Petazzoni return; 822c5aff182SThomas Petazzoni } 823c5aff182SThomas Petazzoni 824c5aff182SThomas Petazzoni /* Only 255 descriptors can be added at once */ 825c5aff182SThomas Petazzoni while ((rx_done > 0) || (rx_filled > 0)) { 826c5aff182SThomas Petazzoni if (rx_done <= 0xff) { 827c5aff182SThomas Petazzoni val = rx_done; 828c5aff182SThomas Petazzoni rx_done = 0; 829c5aff182SThomas Petazzoni } else { 830c5aff182SThomas Petazzoni val = 0xff; 831c5aff182SThomas Petazzoni rx_done -= 0xff; 832c5aff182SThomas Petazzoni } 833c5aff182SThomas Petazzoni if (rx_filled <= 0xff) { 834c5aff182SThomas Petazzoni val |= rx_filled << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT; 835c5aff182SThomas Petazzoni rx_filled = 0; 836c5aff182SThomas Petazzoni } else { 837c5aff182SThomas Petazzoni val |= 0xff << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT; 838c5aff182SThomas Petazzoni rx_filled -= 0xff; 839c5aff182SThomas Petazzoni } 840c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id), val); 841c5aff182SThomas Petazzoni } 842c5aff182SThomas Petazzoni } 843c5aff182SThomas Petazzoni 844c5aff182SThomas Petazzoni /* Get pointer to next RX descriptor to be processed by SW */ 845c5aff182SThomas Petazzoni static struct mvneta_rx_desc * 846c5aff182SThomas Petazzoni mvneta_rxq_next_desc_get(struct mvneta_rx_queue *rxq) 847c5aff182SThomas Petazzoni { 848c5aff182SThomas Petazzoni int rx_desc = rxq->next_desc_to_proc; 849c5aff182SThomas Petazzoni 850c5aff182SThomas Petazzoni rxq->next_desc_to_proc = MVNETA_QUEUE_NEXT_DESC(rxq, rx_desc); 85134e4179dSwilly tarreau prefetch(rxq->descs + rxq->next_desc_to_proc); 852c5aff182SThomas Petazzoni return rxq->descs + rx_desc; 853c5aff182SThomas Petazzoni } 854c5aff182SThomas Petazzoni 855c5aff182SThomas Petazzoni /* Change maximum receive size of the port. */ 856c5aff182SThomas Petazzoni static void mvneta_max_rx_size_set(struct mvneta_port *pp, int max_rx_size) 857c5aff182SThomas Petazzoni { 858c5aff182SThomas Petazzoni u32 val; 859c5aff182SThomas Petazzoni 860c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_GMAC_CTRL_0); 861c5aff182SThomas Petazzoni val &= ~MVNETA_GMAC_MAX_RX_SIZE_MASK; 862c5aff182SThomas Petazzoni val |= ((max_rx_size - MVNETA_MH_SIZE) / 2) << 863c5aff182SThomas Petazzoni MVNETA_GMAC_MAX_RX_SIZE_SHIFT; 864c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_GMAC_CTRL_0, val); 865c5aff182SThomas Petazzoni } 866c5aff182SThomas Petazzoni 867c5aff182SThomas Petazzoni 868c5aff182SThomas Petazzoni /* Set rx queue offset */ 869c5aff182SThomas Petazzoni static void mvneta_rxq_offset_set(struct mvneta_port *pp, 870c5aff182SThomas Petazzoni struct mvneta_rx_queue *rxq, 871c5aff182SThomas Petazzoni int offset) 872c5aff182SThomas Petazzoni { 873c5aff182SThomas Petazzoni u32 val; 874c5aff182SThomas Petazzoni 875c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_RXQ_CONFIG_REG(rxq->id)); 876c5aff182SThomas Petazzoni val &= ~MVNETA_RXQ_PKT_OFFSET_ALL_MASK; 877c5aff182SThomas Petazzoni 878c5aff182SThomas Petazzoni /* Offset is in */ 879c5aff182SThomas Petazzoni val |= MVNETA_RXQ_PKT_OFFSET_MASK(offset >> 3); 880c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_RXQ_CONFIG_REG(rxq->id), val); 881c5aff182SThomas Petazzoni } 882c5aff182SThomas Petazzoni 883c5aff182SThomas Petazzoni 884c5aff182SThomas Petazzoni /* Tx descriptors helper methods */ 885c5aff182SThomas Petazzoni 886c5aff182SThomas Petazzoni /* Update HW with number of TX descriptors to be sent */ 887c5aff182SThomas Petazzoni static void mvneta_txq_pend_desc_add(struct mvneta_port *pp, 888c5aff182SThomas Petazzoni struct mvneta_tx_queue *txq, 889c5aff182SThomas Petazzoni int pend_desc) 890c5aff182SThomas Petazzoni { 891c5aff182SThomas Petazzoni u32 val; 892c5aff182SThomas Petazzoni 8930d63785cSSimon Guinot pend_desc += txq->pending; 8940d63785cSSimon Guinot 8950d63785cSSimon Guinot /* Only 255 Tx descriptors can be added at once */ 8960d63785cSSimon Guinot do { 8970d63785cSSimon Guinot val = min(pend_desc, 255); 898c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val); 8990d63785cSSimon Guinot pend_desc -= val; 9000d63785cSSimon Guinot } while (pend_desc > 0); 9012a90f7e1SSimon Guinot txq->pending = 0; 902c5aff182SThomas Petazzoni } 903c5aff182SThomas Petazzoni 904c5aff182SThomas Petazzoni /* Get pointer to next TX descriptor to be processed (send) by HW */ 905c5aff182SThomas Petazzoni static struct mvneta_tx_desc * 906c5aff182SThomas Petazzoni mvneta_txq_next_desc_get(struct mvneta_tx_queue *txq) 907c5aff182SThomas Petazzoni { 908c5aff182SThomas Petazzoni int tx_desc = txq->next_desc_to_proc; 909c5aff182SThomas Petazzoni 910c5aff182SThomas Petazzoni txq->next_desc_to_proc = MVNETA_QUEUE_NEXT_DESC(txq, tx_desc); 911c5aff182SThomas Petazzoni return txq->descs + tx_desc; 912c5aff182SThomas Petazzoni } 913c5aff182SThomas Petazzoni 914c5aff182SThomas Petazzoni /* Release the last allocated TX descriptor. Useful to handle DMA 9156a20c175SThomas Petazzoni * mapping failures in the TX path. 9166a20c175SThomas Petazzoni */ 917c5aff182SThomas Petazzoni static void mvneta_txq_desc_put(struct mvneta_tx_queue *txq) 918c5aff182SThomas Petazzoni { 919c5aff182SThomas Petazzoni if (txq->next_desc_to_proc == 0) 920c5aff182SThomas Petazzoni txq->next_desc_to_proc = txq->last_desc - 1; 921c5aff182SThomas Petazzoni else 922c5aff182SThomas Petazzoni txq->next_desc_to_proc--; 923c5aff182SThomas Petazzoni } 924c5aff182SThomas Petazzoni 925c5aff182SThomas Petazzoni /* Set rxq buf size */ 926c5aff182SThomas Petazzoni static void mvneta_rxq_buf_size_set(struct mvneta_port *pp, 927c5aff182SThomas Petazzoni struct mvneta_rx_queue *rxq, 928c5aff182SThomas Petazzoni int buf_size) 929c5aff182SThomas Petazzoni { 930c5aff182SThomas Petazzoni u32 val; 931c5aff182SThomas Petazzoni 932c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_RXQ_SIZE_REG(rxq->id)); 933c5aff182SThomas Petazzoni 934c5aff182SThomas Petazzoni val &= ~MVNETA_RXQ_BUF_SIZE_MASK; 935c5aff182SThomas Petazzoni val |= ((buf_size >> 3) << MVNETA_RXQ_BUF_SIZE_SHIFT); 936c5aff182SThomas Petazzoni 937c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_RXQ_SIZE_REG(rxq->id), val); 938c5aff182SThomas Petazzoni } 939c5aff182SThomas Petazzoni 940c5aff182SThomas Petazzoni /* Disable buffer management (BM) */ 941c5aff182SThomas Petazzoni static void mvneta_rxq_bm_disable(struct mvneta_port *pp, 942c5aff182SThomas Petazzoni struct mvneta_rx_queue *rxq) 943c5aff182SThomas Petazzoni { 944c5aff182SThomas Petazzoni u32 val; 945c5aff182SThomas Petazzoni 946c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_RXQ_CONFIG_REG(rxq->id)); 947c5aff182SThomas Petazzoni val &= ~MVNETA_RXQ_HW_BUF_ALLOC; 948c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_RXQ_CONFIG_REG(rxq->id), val); 949c5aff182SThomas Petazzoni } 950c5aff182SThomas Petazzoni 951dc35a10fSMarcin Wojtas /* Enable buffer management (BM) */ 952dc35a10fSMarcin Wojtas static void mvneta_rxq_bm_enable(struct mvneta_port *pp, 953dc35a10fSMarcin Wojtas struct mvneta_rx_queue *rxq) 954dc35a10fSMarcin Wojtas { 955dc35a10fSMarcin Wojtas u32 val; 956dc35a10fSMarcin Wojtas 957dc35a10fSMarcin Wojtas val = mvreg_read(pp, MVNETA_RXQ_CONFIG_REG(rxq->id)); 958dc35a10fSMarcin Wojtas val |= MVNETA_RXQ_HW_BUF_ALLOC; 959dc35a10fSMarcin Wojtas mvreg_write(pp, MVNETA_RXQ_CONFIG_REG(rxq->id), val); 960dc35a10fSMarcin Wojtas } 961dc35a10fSMarcin Wojtas 962dc35a10fSMarcin Wojtas /* Notify HW about port's assignment of pool for bigger packets */ 963dc35a10fSMarcin Wojtas static void mvneta_rxq_long_pool_set(struct mvneta_port *pp, 964dc35a10fSMarcin Wojtas struct mvneta_rx_queue *rxq) 965dc35a10fSMarcin Wojtas { 966dc35a10fSMarcin Wojtas u32 val; 967dc35a10fSMarcin Wojtas 968dc35a10fSMarcin Wojtas val = mvreg_read(pp, MVNETA_RXQ_CONFIG_REG(rxq->id)); 969dc35a10fSMarcin Wojtas val &= ~MVNETA_RXQ_LONG_POOL_ID_MASK; 970dc35a10fSMarcin Wojtas val |= (pp->pool_long->id << MVNETA_RXQ_LONG_POOL_ID_SHIFT); 971dc35a10fSMarcin Wojtas 972dc35a10fSMarcin Wojtas mvreg_write(pp, MVNETA_RXQ_CONFIG_REG(rxq->id), val); 973dc35a10fSMarcin Wojtas } 974dc35a10fSMarcin Wojtas 975dc35a10fSMarcin Wojtas /* Notify HW about port's assignment of pool for smaller packets */ 976dc35a10fSMarcin Wojtas static void mvneta_rxq_short_pool_set(struct mvneta_port *pp, 977dc35a10fSMarcin Wojtas struct mvneta_rx_queue *rxq) 978dc35a10fSMarcin Wojtas { 979dc35a10fSMarcin Wojtas u32 val; 980dc35a10fSMarcin Wojtas 981dc35a10fSMarcin Wojtas val = mvreg_read(pp, MVNETA_RXQ_CONFIG_REG(rxq->id)); 982dc35a10fSMarcin Wojtas val &= ~MVNETA_RXQ_SHORT_POOL_ID_MASK; 983dc35a10fSMarcin Wojtas val |= (pp->pool_short->id << MVNETA_RXQ_SHORT_POOL_ID_SHIFT); 984dc35a10fSMarcin Wojtas 985dc35a10fSMarcin Wojtas mvreg_write(pp, MVNETA_RXQ_CONFIG_REG(rxq->id), val); 986dc35a10fSMarcin Wojtas } 987dc35a10fSMarcin Wojtas 988dc35a10fSMarcin Wojtas /* Set port's receive buffer size for assigned BM pool */ 989dc35a10fSMarcin Wojtas static inline void mvneta_bm_pool_bufsize_set(struct mvneta_port *pp, 990dc35a10fSMarcin Wojtas int buf_size, 991dc35a10fSMarcin Wojtas u8 pool_id) 992dc35a10fSMarcin Wojtas { 993dc35a10fSMarcin Wojtas u32 val; 994dc35a10fSMarcin Wojtas 995dc35a10fSMarcin Wojtas if (!IS_ALIGNED(buf_size, 8)) { 996dc35a10fSMarcin Wojtas dev_warn(pp->dev->dev.parent, 997dc35a10fSMarcin Wojtas "illegal buf_size value %d, round to %d\n", 998dc35a10fSMarcin Wojtas buf_size, ALIGN(buf_size, 8)); 999dc35a10fSMarcin Wojtas buf_size = ALIGN(buf_size, 8); 1000dc35a10fSMarcin Wojtas } 1001dc35a10fSMarcin Wojtas 1002dc35a10fSMarcin Wojtas val = mvreg_read(pp, MVNETA_PORT_POOL_BUFFER_SZ_REG(pool_id)); 1003dc35a10fSMarcin Wojtas val |= buf_size & MVNETA_PORT_POOL_BUFFER_SZ_MASK; 1004dc35a10fSMarcin Wojtas mvreg_write(pp, MVNETA_PORT_POOL_BUFFER_SZ_REG(pool_id), val); 1005dc35a10fSMarcin Wojtas } 1006dc35a10fSMarcin Wojtas 1007dc35a10fSMarcin Wojtas /* Configure MBUS window in order to enable access BM internal SRAM */ 1008dc35a10fSMarcin Wojtas static int mvneta_mbus_io_win_set(struct mvneta_port *pp, u32 base, u32 wsize, 1009dc35a10fSMarcin Wojtas u8 target, u8 attr) 1010dc35a10fSMarcin Wojtas { 1011dc35a10fSMarcin Wojtas u32 win_enable, win_protect; 1012dc35a10fSMarcin Wojtas int i; 1013dc35a10fSMarcin Wojtas 1014dc35a10fSMarcin Wojtas win_enable = mvreg_read(pp, MVNETA_BASE_ADDR_ENABLE); 1015dc35a10fSMarcin Wojtas 1016dc35a10fSMarcin Wojtas if (pp->bm_win_id < 0) { 1017dc35a10fSMarcin Wojtas /* Find first not occupied window */ 1018dc35a10fSMarcin Wojtas for (i = 0; i < MVNETA_MAX_DECODE_WIN; i++) { 1019dc35a10fSMarcin Wojtas if (win_enable & (1 << i)) { 1020dc35a10fSMarcin Wojtas pp->bm_win_id = i; 1021dc35a10fSMarcin Wojtas break; 1022dc35a10fSMarcin Wojtas } 1023dc35a10fSMarcin Wojtas } 1024dc35a10fSMarcin Wojtas if (i == MVNETA_MAX_DECODE_WIN) 1025dc35a10fSMarcin Wojtas return -ENOMEM; 1026dc35a10fSMarcin Wojtas } else { 1027dc35a10fSMarcin Wojtas i = pp->bm_win_id; 1028dc35a10fSMarcin Wojtas } 1029dc35a10fSMarcin Wojtas 1030dc35a10fSMarcin Wojtas mvreg_write(pp, MVNETA_WIN_BASE(i), 0); 1031dc35a10fSMarcin Wojtas mvreg_write(pp, MVNETA_WIN_SIZE(i), 0); 1032dc35a10fSMarcin Wojtas 1033dc35a10fSMarcin Wojtas if (i < 4) 1034dc35a10fSMarcin Wojtas mvreg_write(pp, MVNETA_WIN_REMAP(i), 0); 1035dc35a10fSMarcin Wojtas 1036dc35a10fSMarcin Wojtas mvreg_write(pp, MVNETA_WIN_BASE(i), (base & 0xffff0000) | 1037dc35a10fSMarcin Wojtas (attr << 8) | target); 1038dc35a10fSMarcin Wojtas 1039dc35a10fSMarcin Wojtas mvreg_write(pp, MVNETA_WIN_SIZE(i), (wsize - 1) & 0xffff0000); 1040dc35a10fSMarcin Wojtas 1041dc35a10fSMarcin Wojtas win_protect = mvreg_read(pp, MVNETA_ACCESS_PROTECT_ENABLE); 1042dc35a10fSMarcin Wojtas win_protect |= 3 << (2 * i); 1043dc35a10fSMarcin Wojtas mvreg_write(pp, MVNETA_ACCESS_PROTECT_ENABLE, win_protect); 1044dc35a10fSMarcin Wojtas 1045dc35a10fSMarcin Wojtas win_enable &= ~(1 << i); 1046dc35a10fSMarcin Wojtas mvreg_write(pp, MVNETA_BASE_ADDR_ENABLE, win_enable); 1047dc35a10fSMarcin Wojtas 1048dc35a10fSMarcin Wojtas return 0; 1049dc35a10fSMarcin Wojtas } 1050dc35a10fSMarcin Wojtas 10512636ac3cSMarcin Wojtas static int mvneta_bm_port_mbus_init(struct mvneta_port *pp) 1052dc35a10fSMarcin Wojtas { 10532636ac3cSMarcin Wojtas u32 wsize; 1054dc35a10fSMarcin Wojtas u8 target, attr; 1055dc35a10fSMarcin Wojtas int err; 1056dc35a10fSMarcin Wojtas 1057dc35a10fSMarcin Wojtas /* Get BM window information */ 1058dc35a10fSMarcin Wojtas err = mvebu_mbus_get_io_win_info(pp->bm_priv->bppi_phys_addr, &wsize, 1059dc35a10fSMarcin Wojtas &target, &attr); 1060dc35a10fSMarcin Wojtas if (err < 0) 1061dc35a10fSMarcin Wojtas return err; 1062dc35a10fSMarcin Wojtas 1063dc35a10fSMarcin Wojtas pp->bm_win_id = -1; 1064dc35a10fSMarcin Wojtas 1065dc35a10fSMarcin Wojtas /* Open NETA -> BM window */ 1066dc35a10fSMarcin Wojtas err = mvneta_mbus_io_win_set(pp, pp->bm_priv->bppi_phys_addr, wsize, 1067dc35a10fSMarcin Wojtas target, attr); 1068dc35a10fSMarcin Wojtas if (err < 0) { 1069dc35a10fSMarcin Wojtas netdev_info(pp->dev, "fail to configure mbus window to BM\n"); 1070dc35a10fSMarcin Wojtas return err; 1071dc35a10fSMarcin Wojtas } 10722636ac3cSMarcin Wojtas return 0; 10732636ac3cSMarcin Wojtas } 10742636ac3cSMarcin Wojtas 10752636ac3cSMarcin Wojtas /* Assign and initialize pools for port. In case of fail 10762636ac3cSMarcin Wojtas * buffer manager will remain disabled for current port. 10772636ac3cSMarcin Wojtas */ 10782636ac3cSMarcin Wojtas static int mvneta_bm_port_init(struct platform_device *pdev, 10792636ac3cSMarcin Wojtas struct mvneta_port *pp) 10802636ac3cSMarcin Wojtas { 10812636ac3cSMarcin Wojtas struct device_node *dn = pdev->dev.of_node; 10822636ac3cSMarcin Wojtas u32 long_pool_id, short_pool_id; 10832636ac3cSMarcin Wojtas 10842636ac3cSMarcin Wojtas if (!pp->neta_armada3700) { 10852636ac3cSMarcin Wojtas int ret; 10862636ac3cSMarcin Wojtas 10872636ac3cSMarcin Wojtas ret = mvneta_bm_port_mbus_init(pp); 10882636ac3cSMarcin Wojtas if (ret) 10892636ac3cSMarcin Wojtas return ret; 10902636ac3cSMarcin Wojtas } 1091dc35a10fSMarcin Wojtas 1092dc35a10fSMarcin Wojtas if (of_property_read_u32(dn, "bm,pool-long", &long_pool_id)) { 1093dc35a10fSMarcin Wojtas netdev_info(pp->dev, "missing long pool id\n"); 1094dc35a10fSMarcin Wojtas return -EINVAL; 1095dc35a10fSMarcin Wojtas } 1096dc35a10fSMarcin Wojtas 1097dc35a10fSMarcin Wojtas /* Create port's long pool depending on mtu */ 1098dc35a10fSMarcin Wojtas pp->pool_long = mvneta_bm_pool_use(pp->bm_priv, long_pool_id, 1099dc35a10fSMarcin Wojtas MVNETA_BM_LONG, pp->id, 1100dc35a10fSMarcin Wojtas MVNETA_RX_PKT_SIZE(pp->dev->mtu)); 1101dc35a10fSMarcin Wojtas if (!pp->pool_long) { 1102dc35a10fSMarcin Wojtas netdev_info(pp->dev, "fail to obtain long pool for port\n"); 1103dc35a10fSMarcin Wojtas return -ENOMEM; 1104dc35a10fSMarcin Wojtas } 1105dc35a10fSMarcin Wojtas 1106dc35a10fSMarcin Wojtas pp->pool_long->port_map |= 1 << pp->id; 1107dc35a10fSMarcin Wojtas 1108dc35a10fSMarcin Wojtas mvneta_bm_pool_bufsize_set(pp, pp->pool_long->buf_size, 1109dc35a10fSMarcin Wojtas pp->pool_long->id); 1110dc35a10fSMarcin Wojtas 1111dc35a10fSMarcin Wojtas /* If short pool id is not defined, assume using single pool */ 1112dc35a10fSMarcin Wojtas if (of_property_read_u32(dn, "bm,pool-short", &short_pool_id)) 1113dc35a10fSMarcin Wojtas short_pool_id = long_pool_id; 1114dc35a10fSMarcin Wojtas 1115dc35a10fSMarcin Wojtas /* Create port's short pool */ 1116dc35a10fSMarcin Wojtas pp->pool_short = mvneta_bm_pool_use(pp->bm_priv, short_pool_id, 1117dc35a10fSMarcin Wojtas MVNETA_BM_SHORT, pp->id, 1118dc35a10fSMarcin Wojtas MVNETA_BM_SHORT_PKT_SIZE); 1119dc35a10fSMarcin Wojtas if (!pp->pool_short) { 1120dc35a10fSMarcin Wojtas netdev_info(pp->dev, "fail to obtain short pool for port\n"); 1121dc35a10fSMarcin Wojtas mvneta_bm_pool_destroy(pp->bm_priv, pp->pool_long, 1 << pp->id); 1122dc35a10fSMarcin Wojtas return -ENOMEM; 1123dc35a10fSMarcin Wojtas } 1124dc35a10fSMarcin Wojtas 1125dc35a10fSMarcin Wojtas if (short_pool_id != long_pool_id) { 1126dc35a10fSMarcin Wojtas pp->pool_short->port_map |= 1 << pp->id; 1127dc35a10fSMarcin Wojtas mvneta_bm_pool_bufsize_set(pp, pp->pool_short->buf_size, 1128dc35a10fSMarcin Wojtas pp->pool_short->id); 1129dc35a10fSMarcin Wojtas } 1130dc35a10fSMarcin Wojtas 1131dc35a10fSMarcin Wojtas return 0; 1132dc35a10fSMarcin Wojtas } 1133dc35a10fSMarcin Wojtas 1134dc35a10fSMarcin Wojtas /* Update settings of a pool for bigger packets */ 1135dc35a10fSMarcin Wojtas static void mvneta_bm_update_mtu(struct mvneta_port *pp, int mtu) 1136dc35a10fSMarcin Wojtas { 1137dc35a10fSMarcin Wojtas struct mvneta_bm_pool *bm_pool = pp->pool_long; 1138baa11ebcSGregory CLEMENT struct hwbm_pool *hwbm_pool = &bm_pool->hwbm_pool; 1139dc35a10fSMarcin Wojtas int num; 1140dc35a10fSMarcin Wojtas 1141dc35a10fSMarcin Wojtas /* Release all buffers from long pool */ 1142dc35a10fSMarcin Wojtas mvneta_bm_bufs_free(pp->bm_priv, bm_pool, 1 << pp->id); 1143baa11ebcSGregory CLEMENT if (hwbm_pool->buf_num) { 1144dc35a10fSMarcin Wojtas WARN(1, "cannot free all buffers in pool %d\n", 1145dc35a10fSMarcin Wojtas bm_pool->id); 1146dc35a10fSMarcin Wojtas goto bm_mtu_err; 1147dc35a10fSMarcin Wojtas } 1148dc35a10fSMarcin Wojtas 1149dc35a10fSMarcin Wojtas bm_pool->pkt_size = MVNETA_RX_PKT_SIZE(mtu); 1150dc35a10fSMarcin Wojtas bm_pool->buf_size = MVNETA_RX_BUF_SIZE(bm_pool->pkt_size); 1151baa11ebcSGregory CLEMENT hwbm_pool->frag_size = SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) + 1152dc35a10fSMarcin Wojtas SKB_DATA_ALIGN(MVNETA_RX_BUF_SIZE(bm_pool->pkt_size)); 1153dc35a10fSMarcin Wojtas 1154dc35a10fSMarcin Wojtas /* Fill entire long pool */ 11556dcdd884SSebastian Andrzej Siewior num = hwbm_pool_add(hwbm_pool, hwbm_pool->size); 1156baa11ebcSGregory CLEMENT if (num != hwbm_pool->size) { 1157dc35a10fSMarcin Wojtas WARN(1, "pool %d: %d of %d allocated\n", 1158baa11ebcSGregory CLEMENT bm_pool->id, num, hwbm_pool->size); 1159dc35a10fSMarcin Wojtas goto bm_mtu_err; 1160dc35a10fSMarcin Wojtas } 1161dc35a10fSMarcin Wojtas mvneta_bm_pool_bufsize_set(pp, bm_pool->buf_size, bm_pool->id); 1162dc35a10fSMarcin Wojtas 1163dc35a10fSMarcin Wojtas return; 1164dc35a10fSMarcin Wojtas 1165dc35a10fSMarcin Wojtas bm_mtu_err: 1166dc35a10fSMarcin Wojtas mvneta_bm_pool_destroy(pp->bm_priv, pp->pool_long, 1 << pp->id); 1167dc35a10fSMarcin Wojtas mvneta_bm_pool_destroy(pp->bm_priv, pp->pool_short, 1 << pp->id); 1168dc35a10fSMarcin Wojtas 1169dc35a10fSMarcin Wojtas pp->bm_priv = NULL; 1170dc35a10fSMarcin Wojtas mvreg_write(pp, MVNETA_ACC_MODE, MVNETA_ACC_MODE_EXT1); 1171dc35a10fSMarcin Wojtas netdev_info(pp->dev, "fail to update MTU, fall back to software BM\n"); 1172dc35a10fSMarcin Wojtas } 1173dc35a10fSMarcin Wojtas 1174c5aff182SThomas Petazzoni /* Start the Ethernet port RX and TX activity */ 1175c5aff182SThomas Petazzoni static void mvneta_port_up(struct mvneta_port *pp) 1176c5aff182SThomas Petazzoni { 1177c5aff182SThomas Petazzoni int queue; 1178c5aff182SThomas Petazzoni u32 q_map; 1179c5aff182SThomas Petazzoni 1180c5aff182SThomas Petazzoni /* Enable all initialized TXs. */ 1181c5aff182SThomas Petazzoni q_map = 0; 1182c5aff182SThomas Petazzoni for (queue = 0; queue < txq_number; queue++) { 1183c5aff182SThomas Petazzoni struct mvneta_tx_queue *txq = &pp->txqs[queue]; 1184f95936ccSMarkus Elfring if (txq->descs) 1185c5aff182SThomas Petazzoni q_map |= (1 << queue); 1186c5aff182SThomas Petazzoni } 1187c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_TXQ_CMD, q_map); 1188c5aff182SThomas Petazzoni 1189e81b5e01SYelena Krivosheev q_map = 0; 1190c5aff182SThomas Petazzoni /* Enable all initialized RXQs. */ 11912dcf75e2SGregory CLEMENT for (queue = 0; queue < rxq_number; queue++) { 11922dcf75e2SGregory CLEMENT struct mvneta_rx_queue *rxq = &pp->rxqs[queue]; 11932dcf75e2SGregory CLEMENT 1194f95936ccSMarkus Elfring if (rxq->descs) 11952dcf75e2SGregory CLEMENT q_map |= (1 << queue); 11962dcf75e2SGregory CLEMENT } 11972dcf75e2SGregory CLEMENT mvreg_write(pp, MVNETA_RXQ_CMD, q_map); 1198c5aff182SThomas Petazzoni } 1199c5aff182SThomas Petazzoni 1200c5aff182SThomas Petazzoni /* Stop the Ethernet port activity */ 1201c5aff182SThomas Petazzoni static void mvneta_port_down(struct mvneta_port *pp) 1202c5aff182SThomas Petazzoni { 1203c5aff182SThomas Petazzoni u32 val; 1204c5aff182SThomas Petazzoni int count; 1205c5aff182SThomas Petazzoni 1206c5aff182SThomas Petazzoni /* Stop Rx port activity. Check port Rx activity. */ 1207c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_RXQ_CMD) & MVNETA_RXQ_ENABLE_MASK; 1208c5aff182SThomas Petazzoni 1209c5aff182SThomas Petazzoni /* Issue stop command for active channels only */ 1210c5aff182SThomas Petazzoni if (val != 0) 1211c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_RXQ_CMD, 1212c5aff182SThomas Petazzoni val << MVNETA_RXQ_DISABLE_SHIFT); 1213c5aff182SThomas Petazzoni 1214c5aff182SThomas Petazzoni /* Wait for all Rx activity to terminate. */ 1215c5aff182SThomas Petazzoni count = 0; 1216c5aff182SThomas Petazzoni do { 1217c5aff182SThomas Petazzoni if (count++ >= MVNETA_RX_DISABLE_TIMEOUT_MSEC) { 1218c5aff182SThomas Petazzoni netdev_warn(pp->dev, 12190838abb3SDmitri Epshtein "TIMEOUT for RX stopped ! rx_queue_cmd: 0x%08x\n", 1220c5aff182SThomas Petazzoni val); 1221c5aff182SThomas Petazzoni break; 1222c5aff182SThomas Petazzoni } 1223c5aff182SThomas Petazzoni mdelay(1); 1224c5aff182SThomas Petazzoni 1225c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_RXQ_CMD); 1226a3703fb3SDmitri Epshtein } while (val & MVNETA_RXQ_ENABLE_MASK); 1227c5aff182SThomas Petazzoni 1228c5aff182SThomas Petazzoni /* Stop Tx port activity. Check port Tx activity. Issue stop 12296a20c175SThomas Petazzoni * command for active channels only 12306a20c175SThomas Petazzoni */ 1231c5aff182SThomas Petazzoni val = (mvreg_read(pp, MVNETA_TXQ_CMD)) & MVNETA_TXQ_ENABLE_MASK; 1232c5aff182SThomas Petazzoni 1233c5aff182SThomas Petazzoni if (val != 0) 1234c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_TXQ_CMD, 1235c5aff182SThomas Petazzoni (val << MVNETA_TXQ_DISABLE_SHIFT)); 1236c5aff182SThomas Petazzoni 1237c5aff182SThomas Petazzoni /* Wait for all Tx activity to terminate. */ 1238c5aff182SThomas Petazzoni count = 0; 1239c5aff182SThomas Petazzoni do { 1240c5aff182SThomas Petazzoni if (count++ >= MVNETA_TX_DISABLE_TIMEOUT_MSEC) { 1241c5aff182SThomas Petazzoni netdev_warn(pp->dev, 1242c5aff182SThomas Petazzoni "TIMEOUT for TX stopped status=0x%08x\n", 1243c5aff182SThomas Petazzoni val); 1244c5aff182SThomas Petazzoni break; 1245c5aff182SThomas Petazzoni } 1246c5aff182SThomas Petazzoni mdelay(1); 1247c5aff182SThomas Petazzoni 1248c5aff182SThomas Petazzoni /* Check TX Command reg that all Txqs are stopped */ 1249c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_TXQ_CMD); 1250c5aff182SThomas Petazzoni 1251a3703fb3SDmitri Epshtein } while (val & MVNETA_TXQ_ENABLE_MASK); 1252c5aff182SThomas Petazzoni 1253c5aff182SThomas Petazzoni /* Double check to verify that TX FIFO is empty */ 1254c5aff182SThomas Petazzoni count = 0; 1255c5aff182SThomas Petazzoni do { 1256c5aff182SThomas Petazzoni if (count++ >= MVNETA_TX_FIFO_EMPTY_TIMEOUT) { 1257c5aff182SThomas Petazzoni netdev_warn(pp->dev, 12580838abb3SDmitri Epshtein "TX FIFO empty timeout status=0x%08x\n", 1259c5aff182SThomas Petazzoni val); 1260c5aff182SThomas Petazzoni break; 1261c5aff182SThomas Petazzoni } 1262c5aff182SThomas Petazzoni mdelay(1); 1263c5aff182SThomas Petazzoni 1264c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_PORT_STATUS); 1265c5aff182SThomas Petazzoni } while (!(val & MVNETA_TX_FIFO_EMPTY) && 1266c5aff182SThomas Petazzoni (val & MVNETA_TX_IN_PRGRS)); 1267c5aff182SThomas Petazzoni 1268c5aff182SThomas Petazzoni udelay(200); 1269c5aff182SThomas Petazzoni } 1270c5aff182SThomas Petazzoni 1271c5aff182SThomas Petazzoni /* Enable the port by setting the port enable bit of the MAC control register */ 1272c5aff182SThomas Petazzoni static void mvneta_port_enable(struct mvneta_port *pp) 1273c5aff182SThomas Petazzoni { 1274c5aff182SThomas Petazzoni u32 val; 1275c5aff182SThomas Petazzoni 1276c5aff182SThomas Petazzoni /* Enable port */ 1277c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_GMAC_CTRL_0); 1278c5aff182SThomas Petazzoni val |= MVNETA_GMAC0_PORT_ENABLE; 1279c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_GMAC_CTRL_0, val); 1280c5aff182SThomas Petazzoni } 1281c5aff182SThomas Petazzoni 1282c5aff182SThomas Petazzoni /* Disable the port and wait for about 200 usec before retuning */ 1283c5aff182SThomas Petazzoni static void mvneta_port_disable(struct mvneta_port *pp) 1284c5aff182SThomas Petazzoni { 1285c5aff182SThomas Petazzoni u32 val; 1286c5aff182SThomas Petazzoni 1287c5aff182SThomas Petazzoni /* Reset the Enable bit in the Serial Control Register */ 1288c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_GMAC_CTRL_0); 1289c5aff182SThomas Petazzoni val &= ~MVNETA_GMAC0_PORT_ENABLE; 1290c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_GMAC_CTRL_0, val); 1291c5aff182SThomas Petazzoni 1292c5aff182SThomas Petazzoni udelay(200); 1293c5aff182SThomas Petazzoni } 1294c5aff182SThomas Petazzoni 1295c5aff182SThomas Petazzoni /* Multicast tables methods */ 1296c5aff182SThomas Petazzoni 1297c5aff182SThomas Petazzoni /* Set all entries in Unicast MAC Table; queue==-1 means reject all */ 1298c5aff182SThomas Petazzoni static void mvneta_set_ucast_table(struct mvneta_port *pp, int queue) 1299c5aff182SThomas Petazzoni { 1300c5aff182SThomas Petazzoni int offset; 1301c5aff182SThomas Petazzoni u32 val; 1302c5aff182SThomas Petazzoni 1303c5aff182SThomas Petazzoni if (queue == -1) { 1304c5aff182SThomas Petazzoni val = 0; 1305c5aff182SThomas Petazzoni } else { 1306c5aff182SThomas Petazzoni val = 0x1 | (queue << 1); 1307c5aff182SThomas Petazzoni val |= (val << 24) | (val << 16) | (val << 8); 1308c5aff182SThomas Petazzoni } 1309c5aff182SThomas Petazzoni 1310c5aff182SThomas Petazzoni for (offset = 0; offset <= 0xc; offset += 4) 1311c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_DA_FILT_UCAST_BASE + offset, val); 1312c5aff182SThomas Petazzoni } 1313c5aff182SThomas Petazzoni 1314c5aff182SThomas Petazzoni /* Set all entries in Special Multicast MAC Table; queue==-1 means reject all */ 1315c5aff182SThomas Petazzoni static void mvneta_set_special_mcast_table(struct mvneta_port *pp, int queue) 1316c5aff182SThomas Petazzoni { 1317c5aff182SThomas Petazzoni int offset; 1318c5aff182SThomas Petazzoni u32 val; 1319c5aff182SThomas Petazzoni 1320c5aff182SThomas Petazzoni if (queue == -1) { 1321c5aff182SThomas Petazzoni val = 0; 1322c5aff182SThomas Petazzoni } else { 1323c5aff182SThomas Petazzoni val = 0x1 | (queue << 1); 1324c5aff182SThomas Petazzoni val |= (val << 24) | (val << 16) | (val << 8); 1325c5aff182SThomas Petazzoni } 1326c5aff182SThomas Petazzoni 1327c5aff182SThomas Petazzoni for (offset = 0; offset <= 0xfc; offset += 4) 1328c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_DA_FILT_SPEC_MCAST + offset, val); 1329c5aff182SThomas Petazzoni 1330c5aff182SThomas Petazzoni } 1331c5aff182SThomas Petazzoni 1332c5aff182SThomas Petazzoni /* Set all entries in Other Multicast MAC Table. queue==-1 means reject all */ 1333c5aff182SThomas Petazzoni static void mvneta_set_other_mcast_table(struct mvneta_port *pp, int queue) 1334c5aff182SThomas Petazzoni { 1335c5aff182SThomas Petazzoni int offset; 1336c5aff182SThomas Petazzoni u32 val; 1337c5aff182SThomas Petazzoni 1338c5aff182SThomas Petazzoni if (queue == -1) { 1339c5aff182SThomas Petazzoni memset(pp->mcast_count, 0, sizeof(pp->mcast_count)); 1340c5aff182SThomas Petazzoni val = 0; 1341c5aff182SThomas Petazzoni } else { 1342c5aff182SThomas Petazzoni memset(pp->mcast_count, 1, sizeof(pp->mcast_count)); 1343c5aff182SThomas Petazzoni val = 0x1 | (queue << 1); 1344c5aff182SThomas Petazzoni val |= (val << 24) | (val << 16) | (val << 8); 1345c5aff182SThomas Petazzoni } 1346c5aff182SThomas Petazzoni 1347c5aff182SThomas Petazzoni for (offset = 0; offset <= 0xfc; offset += 4) 1348c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_DA_FILT_OTH_MCAST + offset, val); 1349c5aff182SThomas Petazzoni } 1350c5aff182SThomas Petazzoni 1351db488c10SGregory CLEMENT static void mvneta_percpu_unmask_interrupt(void *arg) 1352db488c10SGregory CLEMENT { 1353db488c10SGregory CLEMENT struct mvneta_port *pp = arg; 1354db488c10SGregory CLEMENT 1355db488c10SGregory CLEMENT /* All the queue are unmasked, but actually only the ones 1356db488c10SGregory CLEMENT * mapped to this CPU will be unmasked 1357db488c10SGregory CLEMENT */ 1358db488c10SGregory CLEMENT mvreg_write(pp, MVNETA_INTR_NEW_MASK, 1359db488c10SGregory CLEMENT MVNETA_RX_INTR_MASK_ALL | 1360db488c10SGregory CLEMENT MVNETA_TX_INTR_MASK_ALL | 1361db488c10SGregory CLEMENT MVNETA_MISCINTR_INTR_MASK); 1362db488c10SGregory CLEMENT } 1363db488c10SGregory CLEMENT 1364db488c10SGregory CLEMENT static void mvneta_percpu_mask_interrupt(void *arg) 1365db488c10SGregory CLEMENT { 1366db488c10SGregory CLEMENT struct mvneta_port *pp = arg; 1367db488c10SGregory CLEMENT 1368db488c10SGregory CLEMENT /* All the queue are masked, but actually only the ones 1369db488c10SGregory CLEMENT * mapped to this CPU will be masked 1370db488c10SGregory CLEMENT */ 1371db488c10SGregory CLEMENT mvreg_write(pp, MVNETA_INTR_NEW_MASK, 0); 1372db488c10SGregory CLEMENT mvreg_write(pp, MVNETA_INTR_OLD_MASK, 0); 1373db488c10SGregory CLEMENT mvreg_write(pp, MVNETA_INTR_MISC_MASK, 0); 1374db488c10SGregory CLEMENT } 1375db488c10SGregory CLEMENT 1376db488c10SGregory CLEMENT static void mvneta_percpu_clear_intr_cause(void *arg) 1377db488c10SGregory CLEMENT { 1378db488c10SGregory CLEMENT struct mvneta_port *pp = arg; 1379db488c10SGregory CLEMENT 1380db488c10SGregory CLEMENT /* All the queue are cleared, but actually only the ones 1381db488c10SGregory CLEMENT * mapped to this CPU will be cleared 1382db488c10SGregory CLEMENT */ 1383db488c10SGregory CLEMENT mvreg_write(pp, MVNETA_INTR_NEW_CAUSE, 0); 1384db488c10SGregory CLEMENT mvreg_write(pp, MVNETA_INTR_MISC_CAUSE, 0); 1385db488c10SGregory CLEMENT mvreg_write(pp, MVNETA_INTR_OLD_CAUSE, 0); 1386db488c10SGregory CLEMENT } 1387db488c10SGregory CLEMENT 1388c5aff182SThomas Petazzoni /* This method sets defaults to the NETA port: 1389c5aff182SThomas Petazzoni * Clears interrupt Cause and Mask registers. 1390c5aff182SThomas Petazzoni * Clears all MAC tables. 1391c5aff182SThomas Petazzoni * Sets defaults to all registers. 1392c5aff182SThomas Petazzoni * Resets RX and TX descriptor rings. 1393c5aff182SThomas Petazzoni * Resets PHY. 1394c5aff182SThomas Petazzoni * This method can be called after mvneta_port_down() to return the port 1395c5aff182SThomas Petazzoni * settings to defaults. 1396c5aff182SThomas Petazzoni */ 1397c5aff182SThomas Petazzoni static void mvneta_defaults_set(struct mvneta_port *pp) 1398c5aff182SThomas Petazzoni { 1399c5aff182SThomas Petazzoni int cpu; 1400c5aff182SThomas Petazzoni int queue; 1401c5aff182SThomas Petazzoni u32 val; 14022dcf75e2SGregory CLEMENT int max_cpu = num_present_cpus(); 1403c5aff182SThomas Petazzoni 1404c5aff182SThomas Petazzoni /* Clear all Cause registers */ 1405db488c10SGregory CLEMENT on_each_cpu(mvneta_percpu_clear_intr_cause, pp, true); 1406c5aff182SThomas Petazzoni 1407c5aff182SThomas Petazzoni /* Mask all interrupts */ 1408db488c10SGregory CLEMENT on_each_cpu(mvneta_percpu_mask_interrupt, pp, true); 1409c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_INTR_ENABLE, 0); 1410c5aff182SThomas Petazzoni 1411c5aff182SThomas Petazzoni /* Enable MBUS Retry bit16 */ 1412c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_MBUS_RETRY, 0x20); 1413c5aff182SThomas Petazzoni 141450bf8cb6SGregory CLEMENT /* Set CPU queue access map. CPUs are assigned to the RX and 141550bf8cb6SGregory CLEMENT * TX queues modulo their number. If there is only one TX 141650bf8cb6SGregory CLEMENT * queue then it is assigned to the CPU associated to the 141750bf8cb6SGregory CLEMENT * default RX queue. 14186a20c175SThomas Petazzoni */ 14192dcf75e2SGregory CLEMENT for_each_present_cpu(cpu) { 14202dcf75e2SGregory CLEMENT int rxq_map = 0, txq_map = 0; 142150bf8cb6SGregory CLEMENT int rxq, txq; 14222636ac3cSMarcin Wojtas if (!pp->neta_armada3700) { 14232dcf75e2SGregory CLEMENT for (rxq = 0; rxq < rxq_number; rxq++) 14242dcf75e2SGregory CLEMENT if ((rxq % max_cpu) == cpu) 14252dcf75e2SGregory CLEMENT rxq_map |= MVNETA_CPU_RXQ_ACCESS(rxq); 14262dcf75e2SGregory CLEMENT 142750bf8cb6SGregory CLEMENT for (txq = 0; txq < txq_number; txq++) 142850bf8cb6SGregory CLEMENT if ((txq % max_cpu) == cpu) 142950bf8cb6SGregory CLEMENT txq_map |= MVNETA_CPU_TXQ_ACCESS(txq); 143050bf8cb6SGregory CLEMENT 143150bf8cb6SGregory CLEMENT /* With only one TX queue we configure a special case 143250bf8cb6SGregory CLEMENT * which will allow to get all the irq on a single 143350bf8cb6SGregory CLEMENT * CPU 143450bf8cb6SGregory CLEMENT */ 143550bf8cb6SGregory CLEMENT if (txq_number == 1) 143650bf8cb6SGregory CLEMENT txq_map = (cpu == pp->rxq_def) ? 143750bf8cb6SGregory CLEMENT MVNETA_CPU_TXQ_ACCESS(1) : 0; 14382dcf75e2SGregory CLEMENT 14392636ac3cSMarcin Wojtas } else { 14402636ac3cSMarcin Wojtas txq_map = MVNETA_CPU_TXQ_ACCESS_ALL_MASK; 14412636ac3cSMarcin Wojtas rxq_map = MVNETA_CPU_RXQ_ACCESS_ALL_MASK; 14422636ac3cSMarcin Wojtas } 14432636ac3cSMarcin Wojtas 14442dcf75e2SGregory CLEMENT mvreg_write(pp, MVNETA_CPU_MAP(cpu), rxq_map | txq_map); 14452dcf75e2SGregory CLEMENT } 1446c5aff182SThomas Petazzoni 1447c5aff182SThomas Petazzoni /* Reset RX and TX DMAs */ 1448c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_PORT_RX_RESET, MVNETA_PORT_RX_DMA_RESET); 1449c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_PORT_TX_RESET, MVNETA_PORT_TX_DMA_RESET); 1450c5aff182SThomas Petazzoni 1451c5aff182SThomas Petazzoni /* Disable Legacy WRR, Disable EJP, Release from reset */ 1452c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_TXQ_CMD_1, 0); 1453c5aff182SThomas Petazzoni for (queue = 0; queue < txq_number; queue++) { 1454c5aff182SThomas Petazzoni mvreg_write(pp, MVETH_TXQ_TOKEN_COUNT_REG(queue), 0); 1455c5aff182SThomas Petazzoni mvreg_write(pp, MVETH_TXQ_TOKEN_CFG_REG(queue), 0); 1456c5aff182SThomas Petazzoni } 1457c5aff182SThomas Petazzoni 1458c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_PORT_TX_RESET, 0); 1459c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_PORT_RX_RESET, 0); 1460c5aff182SThomas Petazzoni 1461c5aff182SThomas Petazzoni /* Set Port Acceleration Mode */ 1462dc35a10fSMarcin Wojtas if (pp->bm_priv) 1463dc35a10fSMarcin Wojtas /* HW buffer management + legacy parser */ 1464dc35a10fSMarcin Wojtas val = MVNETA_ACC_MODE_EXT2; 1465dc35a10fSMarcin Wojtas else 1466dc35a10fSMarcin Wojtas /* SW buffer management + legacy parser */ 1467dc35a10fSMarcin Wojtas val = MVNETA_ACC_MODE_EXT1; 1468c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_ACC_MODE, val); 1469c5aff182SThomas Petazzoni 1470dc35a10fSMarcin Wojtas if (pp->bm_priv) 1471dc35a10fSMarcin Wojtas mvreg_write(pp, MVNETA_BM_ADDRESS, pp->bm_priv->bppi_phys_addr); 1472dc35a10fSMarcin Wojtas 1473c5aff182SThomas Petazzoni /* Update val of portCfg register accordingly with all RxQueue types */ 147490b74c01SGregory CLEMENT val = MVNETA_PORT_CONFIG_DEFL_VALUE(pp->rxq_def); 1475c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_PORT_CONFIG, val); 1476c5aff182SThomas Petazzoni 1477c5aff182SThomas Petazzoni val = 0; 1478c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_PORT_CONFIG_EXTEND, val); 1479c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_RX_MIN_FRAME_SIZE, 64); 1480c5aff182SThomas Petazzoni 1481c5aff182SThomas Petazzoni /* Build PORT_SDMA_CONFIG_REG */ 1482c5aff182SThomas Petazzoni val = 0; 1483c5aff182SThomas Petazzoni 1484c5aff182SThomas Petazzoni /* Default burst size */ 1485c5aff182SThomas Petazzoni val |= MVNETA_TX_BRST_SZ_MASK(MVNETA_SDMA_BRST_SIZE_16); 1486c5aff182SThomas Petazzoni val |= MVNETA_RX_BRST_SZ_MASK(MVNETA_SDMA_BRST_SIZE_16); 14879ad8fef6SThomas Petazzoni val |= MVNETA_RX_NO_DATA_SWAP | MVNETA_TX_NO_DATA_SWAP; 1488c5aff182SThomas Petazzoni 14899ad8fef6SThomas Petazzoni #if defined(__BIG_ENDIAN) 14909ad8fef6SThomas Petazzoni val |= MVNETA_DESC_SWAP; 14919ad8fef6SThomas Petazzoni #endif 1492c5aff182SThomas Petazzoni 1493c5aff182SThomas Petazzoni /* Assign port SDMA configuration */ 1494c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_SDMA_CONFIG, val); 1495c5aff182SThomas Petazzoni 149671408602SThomas Petazzoni /* Disable PHY polling in hardware, since we're using the 149771408602SThomas Petazzoni * kernel phylib to do this. 149871408602SThomas Petazzoni */ 149971408602SThomas Petazzoni val = mvreg_read(pp, MVNETA_UNIT_CONTROL); 150071408602SThomas Petazzoni val &= ~MVNETA_PHY_POLLING_ENABLE; 150171408602SThomas Petazzoni mvreg_write(pp, MVNETA_UNIT_CONTROL, val); 150271408602SThomas Petazzoni 1503c5aff182SThomas Petazzoni mvneta_set_ucast_table(pp, -1); 1504c5aff182SThomas Petazzoni mvneta_set_special_mcast_table(pp, -1); 1505c5aff182SThomas Petazzoni mvneta_set_other_mcast_table(pp, -1); 1506c5aff182SThomas Petazzoni 1507c5aff182SThomas Petazzoni /* Set port interrupt enable register - default enable all */ 1508c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_INTR_ENABLE, 1509c5aff182SThomas Petazzoni (MVNETA_RXQ_INTR_ENABLE_ALL_MASK 1510c5aff182SThomas Petazzoni | MVNETA_TXQ_INTR_ENABLE_ALL_MASK)); 1511e483911fSAndrew Lunn 1512e483911fSAndrew Lunn mvneta_mib_counters_clear(pp); 1513c5aff182SThomas Petazzoni } 1514c5aff182SThomas Petazzoni 1515c5aff182SThomas Petazzoni /* Set max sizes for tx queues */ 1516c5aff182SThomas Petazzoni static void mvneta_txq_max_tx_size_set(struct mvneta_port *pp, int max_tx_size) 1517c5aff182SThomas Petazzoni 1518c5aff182SThomas Petazzoni { 1519c5aff182SThomas Petazzoni u32 val, size, mtu; 1520c5aff182SThomas Petazzoni int queue; 1521c5aff182SThomas Petazzoni 1522c5aff182SThomas Petazzoni mtu = max_tx_size * 8; 1523c5aff182SThomas Petazzoni if (mtu > MVNETA_TX_MTU_MAX) 1524c5aff182SThomas Petazzoni mtu = MVNETA_TX_MTU_MAX; 1525c5aff182SThomas Petazzoni 1526c5aff182SThomas Petazzoni /* Set MTU */ 1527c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_TX_MTU); 1528c5aff182SThomas Petazzoni val &= ~MVNETA_TX_MTU_MAX; 1529c5aff182SThomas Petazzoni val |= mtu; 1530c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_TX_MTU, val); 1531c5aff182SThomas Petazzoni 1532c5aff182SThomas Petazzoni /* TX token size and all TXQs token size must be larger that MTU */ 1533c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_TX_TOKEN_SIZE); 1534c5aff182SThomas Petazzoni 1535c5aff182SThomas Petazzoni size = val & MVNETA_TX_TOKEN_SIZE_MAX; 1536c5aff182SThomas Petazzoni if (size < mtu) { 1537c5aff182SThomas Petazzoni size = mtu; 1538c5aff182SThomas Petazzoni val &= ~MVNETA_TX_TOKEN_SIZE_MAX; 1539c5aff182SThomas Petazzoni val |= size; 1540c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_TX_TOKEN_SIZE, val); 1541c5aff182SThomas Petazzoni } 1542c5aff182SThomas Petazzoni for (queue = 0; queue < txq_number; queue++) { 1543c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_TXQ_TOKEN_SIZE_REG(queue)); 1544c5aff182SThomas Petazzoni 1545c5aff182SThomas Petazzoni size = val & MVNETA_TXQ_TOKEN_SIZE_MAX; 1546c5aff182SThomas Petazzoni if (size < mtu) { 1547c5aff182SThomas Petazzoni size = mtu; 1548c5aff182SThomas Petazzoni val &= ~MVNETA_TXQ_TOKEN_SIZE_MAX; 1549c5aff182SThomas Petazzoni val |= size; 1550c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_TXQ_TOKEN_SIZE_REG(queue), val); 1551c5aff182SThomas Petazzoni } 1552c5aff182SThomas Petazzoni } 1553c5aff182SThomas Petazzoni } 1554c5aff182SThomas Petazzoni 1555c5aff182SThomas Petazzoni /* Set unicast address */ 1556c5aff182SThomas Petazzoni static void mvneta_set_ucast_addr(struct mvneta_port *pp, u8 last_nibble, 1557c5aff182SThomas Petazzoni int queue) 1558c5aff182SThomas Petazzoni { 1559c5aff182SThomas Petazzoni unsigned int unicast_reg; 1560c5aff182SThomas Petazzoni unsigned int tbl_offset; 1561c5aff182SThomas Petazzoni unsigned int reg_offset; 1562c5aff182SThomas Petazzoni 1563c5aff182SThomas Petazzoni /* Locate the Unicast table entry */ 1564c5aff182SThomas Petazzoni last_nibble = (0xf & last_nibble); 1565c5aff182SThomas Petazzoni 1566c5aff182SThomas Petazzoni /* offset from unicast tbl base */ 1567c5aff182SThomas Petazzoni tbl_offset = (last_nibble / 4) * 4; 1568c5aff182SThomas Petazzoni 1569c5aff182SThomas Petazzoni /* offset within the above reg */ 1570c5aff182SThomas Petazzoni reg_offset = last_nibble % 4; 1571c5aff182SThomas Petazzoni 1572c5aff182SThomas Petazzoni unicast_reg = mvreg_read(pp, (MVNETA_DA_FILT_UCAST_BASE + tbl_offset)); 1573c5aff182SThomas Petazzoni 1574c5aff182SThomas Petazzoni if (queue == -1) { 1575c5aff182SThomas Petazzoni /* Clear accepts frame bit at specified unicast DA tbl entry */ 1576c5aff182SThomas Petazzoni unicast_reg &= ~(0xff << (8 * reg_offset)); 1577c5aff182SThomas Petazzoni } else { 1578c5aff182SThomas Petazzoni unicast_reg &= ~(0xff << (8 * reg_offset)); 1579c5aff182SThomas Petazzoni unicast_reg |= ((0x01 | (queue << 1)) << (8 * reg_offset)); 1580c5aff182SThomas Petazzoni } 1581c5aff182SThomas Petazzoni 1582c5aff182SThomas Petazzoni mvreg_write(pp, (MVNETA_DA_FILT_UCAST_BASE + tbl_offset), unicast_reg); 1583c5aff182SThomas Petazzoni } 1584c5aff182SThomas Petazzoni 1585c5aff182SThomas Petazzoni /* Set mac address */ 1586c5aff182SThomas Petazzoni static void mvneta_mac_addr_set(struct mvneta_port *pp, unsigned char *addr, 1587c5aff182SThomas Petazzoni int queue) 1588c5aff182SThomas Petazzoni { 1589c5aff182SThomas Petazzoni unsigned int mac_h; 1590c5aff182SThomas Petazzoni unsigned int mac_l; 1591c5aff182SThomas Petazzoni 1592c5aff182SThomas Petazzoni if (queue != -1) { 1593c5aff182SThomas Petazzoni mac_l = (addr[4] << 8) | (addr[5]); 1594c5aff182SThomas Petazzoni mac_h = (addr[0] << 24) | (addr[1] << 16) | 1595c5aff182SThomas Petazzoni (addr[2] << 8) | (addr[3] << 0); 1596c5aff182SThomas Petazzoni 1597c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_MAC_ADDR_LOW, mac_l); 1598c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_MAC_ADDR_HIGH, mac_h); 1599c5aff182SThomas Petazzoni } 1600c5aff182SThomas Petazzoni 1601c5aff182SThomas Petazzoni /* Accept frames of this address */ 1602c5aff182SThomas Petazzoni mvneta_set_ucast_addr(pp, addr[5], queue); 1603c5aff182SThomas Petazzoni } 1604c5aff182SThomas Petazzoni 16056a20c175SThomas Petazzoni /* Set the number of packets that will be received before RX interrupt 16066a20c175SThomas Petazzoni * will be generated by HW. 1607c5aff182SThomas Petazzoni */ 1608c5aff182SThomas Petazzoni static void mvneta_rx_pkts_coal_set(struct mvneta_port *pp, 1609c5aff182SThomas Petazzoni struct mvneta_rx_queue *rxq, u32 value) 1610c5aff182SThomas Petazzoni { 1611c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_RXQ_THRESHOLD_REG(rxq->id), 1612c5aff182SThomas Petazzoni value | MVNETA_RXQ_NON_OCCUPIED(0)); 1613c5aff182SThomas Petazzoni } 1614c5aff182SThomas Petazzoni 16156a20c175SThomas Petazzoni /* Set the time delay in usec before RX interrupt will be generated by 16166a20c175SThomas Petazzoni * HW. 1617c5aff182SThomas Petazzoni */ 1618c5aff182SThomas Petazzoni static void mvneta_rx_time_coal_set(struct mvneta_port *pp, 1619c5aff182SThomas Petazzoni struct mvneta_rx_queue *rxq, u32 value) 1620c5aff182SThomas Petazzoni { 1621189dd626SThomas Petazzoni u32 val; 1622189dd626SThomas Petazzoni unsigned long clk_rate; 1623189dd626SThomas Petazzoni 1624189dd626SThomas Petazzoni clk_rate = clk_get_rate(pp->clk); 1625189dd626SThomas Petazzoni val = (clk_rate / 1000000) * value; 1626c5aff182SThomas Petazzoni 1627c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_RXQ_TIME_COAL_REG(rxq->id), val); 1628c5aff182SThomas Petazzoni } 1629c5aff182SThomas Petazzoni 1630c5aff182SThomas Petazzoni /* Set threshold for TX_DONE pkts coalescing */ 1631c5aff182SThomas Petazzoni static void mvneta_tx_done_pkts_coal_set(struct mvneta_port *pp, 1632c5aff182SThomas Petazzoni struct mvneta_tx_queue *txq, u32 value) 1633c5aff182SThomas Petazzoni { 1634c5aff182SThomas Petazzoni u32 val; 1635c5aff182SThomas Petazzoni 1636c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_TXQ_SIZE_REG(txq->id)); 1637c5aff182SThomas Petazzoni 1638c5aff182SThomas Petazzoni val &= ~MVNETA_TXQ_SENT_THRESH_ALL_MASK; 1639c5aff182SThomas Petazzoni val |= MVNETA_TXQ_SENT_THRESH_MASK(value); 1640c5aff182SThomas Petazzoni 1641c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_TXQ_SIZE_REG(txq->id), val); 1642c5aff182SThomas Petazzoni } 1643c5aff182SThomas Petazzoni 1644c5aff182SThomas Petazzoni /* Handle rx descriptor fill by setting buf_cookie and buf_phys_addr */ 1645c5aff182SThomas Petazzoni static void mvneta_rx_desc_fill(struct mvneta_rx_desc *rx_desc, 1646f88bee1cSGregory CLEMENT u32 phys_addr, void *virt_addr, 1647f88bee1cSGregory CLEMENT struct mvneta_rx_queue *rxq) 1648c5aff182SThomas Petazzoni { 1649f88bee1cSGregory CLEMENT int i; 1650f88bee1cSGregory CLEMENT 1651c5aff182SThomas Petazzoni rx_desc->buf_phys_addr = phys_addr; 1652f88bee1cSGregory CLEMENT i = rx_desc - rxq->descs; 1653f88bee1cSGregory CLEMENT rxq->buf_virt_addr[i] = virt_addr; 1654c5aff182SThomas Petazzoni } 1655c5aff182SThomas Petazzoni 1656c5aff182SThomas Petazzoni /* Decrement sent descriptors counter */ 1657c5aff182SThomas Petazzoni static void mvneta_txq_sent_desc_dec(struct mvneta_port *pp, 1658c5aff182SThomas Petazzoni struct mvneta_tx_queue *txq, 1659c5aff182SThomas Petazzoni int sent_desc) 1660c5aff182SThomas Petazzoni { 1661c5aff182SThomas Petazzoni u32 val; 1662c5aff182SThomas Petazzoni 1663c5aff182SThomas Petazzoni /* Only 255 TX descriptors can be updated at once */ 1664c5aff182SThomas Petazzoni while (sent_desc > 0xff) { 1665c5aff182SThomas Petazzoni val = 0xff << MVNETA_TXQ_DEC_SENT_SHIFT; 1666c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val); 1667c5aff182SThomas Petazzoni sent_desc = sent_desc - 0xff; 1668c5aff182SThomas Petazzoni } 1669c5aff182SThomas Petazzoni 1670c5aff182SThomas Petazzoni val = sent_desc << MVNETA_TXQ_DEC_SENT_SHIFT; 1671c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val); 1672c5aff182SThomas Petazzoni } 1673c5aff182SThomas Petazzoni 1674c5aff182SThomas Petazzoni /* Get number of TX descriptors already sent by HW */ 1675c5aff182SThomas Petazzoni static int mvneta_txq_sent_desc_num_get(struct mvneta_port *pp, 1676c5aff182SThomas Petazzoni struct mvneta_tx_queue *txq) 1677c5aff182SThomas Petazzoni { 1678c5aff182SThomas Petazzoni u32 val; 1679c5aff182SThomas Petazzoni int sent_desc; 1680c5aff182SThomas Petazzoni 1681c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_TXQ_STATUS_REG(txq->id)); 1682c5aff182SThomas Petazzoni sent_desc = (val & MVNETA_TXQ_SENT_DESC_MASK) >> 1683c5aff182SThomas Petazzoni MVNETA_TXQ_SENT_DESC_SHIFT; 1684c5aff182SThomas Petazzoni 1685c5aff182SThomas Petazzoni return sent_desc; 1686c5aff182SThomas Petazzoni } 1687c5aff182SThomas Petazzoni 16886a20c175SThomas Petazzoni /* Get number of sent descriptors and decrement counter. 1689c5aff182SThomas Petazzoni * The number of sent descriptors is returned. 1690c5aff182SThomas Petazzoni */ 1691c5aff182SThomas Petazzoni static int mvneta_txq_sent_desc_proc(struct mvneta_port *pp, 1692c5aff182SThomas Petazzoni struct mvneta_tx_queue *txq) 1693c5aff182SThomas Petazzoni { 1694c5aff182SThomas Petazzoni int sent_desc; 1695c5aff182SThomas Petazzoni 1696c5aff182SThomas Petazzoni /* Get number of sent descriptors */ 1697c5aff182SThomas Petazzoni sent_desc = mvneta_txq_sent_desc_num_get(pp, txq); 1698c5aff182SThomas Petazzoni 1699c5aff182SThomas Petazzoni /* Decrement sent descriptors counter */ 1700c5aff182SThomas Petazzoni if (sent_desc) 1701c5aff182SThomas Petazzoni mvneta_txq_sent_desc_dec(pp, txq, sent_desc); 1702c5aff182SThomas Petazzoni 1703c5aff182SThomas Petazzoni return sent_desc; 1704c5aff182SThomas Petazzoni } 1705c5aff182SThomas Petazzoni 1706c5aff182SThomas Petazzoni /* Set TXQ descriptors fields relevant for CSUM calculation */ 1707c5aff182SThomas Petazzoni static u32 mvneta_txq_desc_csum(int l3_offs, int l3_proto, 1708c5aff182SThomas Petazzoni int ip_hdr_len, int l4_proto) 1709c5aff182SThomas Petazzoni { 1710c5aff182SThomas Petazzoni u32 command; 1711c5aff182SThomas Petazzoni 1712c5aff182SThomas Petazzoni /* Fields: L3_offset, IP_hdrlen, L3_type, G_IPv4_chk, 17136a20c175SThomas Petazzoni * G_L4_chk, L4_type; required only for checksum 17146a20c175SThomas Petazzoni * calculation 17156a20c175SThomas Petazzoni */ 1716c5aff182SThomas Petazzoni command = l3_offs << MVNETA_TX_L3_OFF_SHIFT; 1717c5aff182SThomas Petazzoni command |= ip_hdr_len << MVNETA_TX_IP_HLEN_SHIFT; 1718c5aff182SThomas Petazzoni 17190a198587SThomas Fitzsimmons if (l3_proto == htons(ETH_P_IP)) 1720c5aff182SThomas Petazzoni command |= MVNETA_TXD_IP_CSUM; 1721c5aff182SThomas Petazzoni else 1722c5aff182SThomas Petazzoni command |= MVNETA_TX_L3_IP6; 1723c5aff182SThomas Petazzoni 1724c5aff182SThomas Petazzoni if (l4_proto == IPPROTO_TCP) 1725c5aff182SThomas Petazzoni command |= MVNETA_TX_L4_CSUM_FULL; 1726c5aff182SThomas Petazzoni else if (l4_proto == IPPROTO_UDP) 1727c5aff182SThomas Petazzoni command |= MVNETA_TX_L4_UDP | MVNETA_TX_L4_CSUM_FULL; 1728c5aff182SThomas Petazzoni else 1729c5aff182SThomas Petazzoni command |= MVNETA_TX_L4_CSUM_NOT; 1730c5aff182SThomas Petazzoni 1731c5aff182SThomas Petazzoni return command; 1732c5aff182SThomas Petazzoni } 1733c5aff182SThomas Petazzoni 1734c5aff182SThomas Petazzoni 1735c5aff182SThomas Petazzoni /* Display more error info */ 1736c5aff182SThomas Petazzoni static void mvneta_rx_error(struct mvneta_port *pp, 1737c5aff182SThomas Petazzoni struct mvneta_rx_desc *rx_desc) 1738c5aff182SThomas Petazzoni { 1739c5aff182SThomas Petazzoni u32 status = rx_desc->status; 1740c5aff182SThomas Petazzoni 1741c5aff182SThomas Petazzoni switch (status & MVNETA_RXD_ERR_CODE_MASK) { 1742c5aff182SThomas Petazzoni case MVNETA_RXD_ERR_CRC: 1743c5aff182SThomas Petazzoni netdev_err(pp->dev, "bad rx status %08x (crc error), size=%d\n", 1744c5aff182SThomas Petazzoni status, rx_desc->data_size); 1745c5aff182SThomas Petazzoni break; 1746c5aff182SThomas Petazzoni case MVNETA_RXD_ERR_OVERRUN: 1747c5aff182SThomas Petazzoni netdev_err(pp->dev, "bad rx status %08x (overrun error), size=%d\n", 1748c5aff182SThomas Petazzoni status, rx_desc->data_size); 1749c5aff182SThomas Petazzoni break; 1750c5aff182SThomas Petazzoni case MVNETA_RXD_ERR_LEN: 1751c5aff182SThomas Petazzoni netdev_err(pp->dev, "bad rx status %08x (max frame length error), size=%d\n", 1752c5aff182SThomas Petazzoni status, rx_desc->data_size); 1753c5aff182SThomas Petazzoni break; 1754c5aff182SThomas Petazzoni case MVNETA_RXD_ERR_RESOURCE: 1755c5aff182SThomas Petazzoni netdev_err(pp->dev, "bad rx status %08x (resource error), size=%d\n", 1756c5aff182SThomas Petazzoni status, rx_desc->data_size); 1757c5aff182SThomas Petazzoni break; 1758c5aff182SThomas Petazzoni } 1759c5aff182SThomas Petazzoni } 1760c5aff182SThomas Petazzoni 17615428213cSwilly tarreau /* Handle RX checksum offload based on the descriptor's status */ 17625428213cSwilly tarreau static void mvneta_rx_csum(struct mvneta_port *pp, u32 status, 1763c5aff182SThomas Petazzoni struct sk_buff *skb) 1764c5aff182SThomas Petazzoni { 1765f945cec8SYelena Krivosheev if ((pp->dev->features & NETIF_F_RXCSUM) && 1766f945cec8SYelena Krivosheev (status & MVNETA_RXD_L3_IP4) && 17675428213cSwilly tarreau (status & MVNETA_RXD_L4_CSUM_OK)) { 1768c5aff182SThomas Petazzoni skb->csum = 0; 1769c5aff182SThomas Petazzoni skb->ip_summed = CHECKSUM_UNNECESSARY; 1770c5aff182SThomas Petazzoni return; 1771c5aff182SThomas Petazzoni } 1772c5aff182SThomas Petazzoni 1773c5aff182SThomas Petazzoni skb->ip_summed = CHECKSUM_NONE; 1774c5aff182SThomas Petazzoni } 1775c5aff182SThomas Petazzoni 17766c498974Swilly tarreau /* Return tx queue pointer (find last set bit) according to <cause> returned 17776c498974Swilly tarreau * form tx_done reg. <cause> must not be null. The return value is always a 17786c498974Swilly tarreau * valid queue for matching the first one found in <cause>. 17796c498974Swilly tarreau */ 1780c5aff182SThomas Petazzoni static struct mvneta_tx_queue *mvneta_tx_done_policy(struct mvneta_port *pp, 1781c5aff182SThomas Petazzoni u32 cause) 1782c5aff182SThomas Petazzoni { 1783c5aff182SThomas Petazzoni int queue = fls(cause) - 1; 1784c5aff182SThomas Petazzoni 17856c498974Swilly tarreau return &pp->txqs[queue]; 1786c5aff182SThomas Petazzoni } 1787c5aff182SThomas Petazzoni 1788c5aff182SThomas Petazzoni /* Free tx queue skbuffs */ 1789c5aff182SThomas Petazzoni static void mvneta_txq_bufs_free(struct mvneta_port *pp, 1790a29b6235SMarcin Wojtas struct mvneta_tx_queue *txq, int num, 1791a29b6235SMarcin Wojtas struct netdev_queue *nq) 1792c5aff182SThomas Petazzoni { 1793a29b6235SMarcin Wojtas unsigned int bytes_compl = 0, pkts_compl = 0; 1794c5aff182SThomas Petazzoni int i; 1795c5aff182SThomas Petazzoni 1796c5aff182SThomas Petazzoni for (i = 0; i < num; i++) { 17979e58c8b4SLorenzo Bianconi struct mvneta_tx_buf *buf = &txq->buf[txq->txq_get_index]; 1798c5aff182SThomas Petazzoni struct mvneta_tx_desc *tx_desc = txq->descs + 1799c5aff182SThomas Petazzoni txq->txq_get_index; 1800a29b6235SMarcin Wojtas 1801c5aff182SThomas Petazzoni mvneta_txq_inc_get(txq); 1802c5aff182SThomas Petazzoni 1803b0a43db9SLorenzo Bianconi if (!IS_TSO_HEADER(txq, tx_desc->buf_phys_addr) && 1804b0a43db9SLorenzo Bianconi buf->type != MVNETA_TYPE_XDP_TX) 18052e3173a3SEzequiel Garcia dma_unmap_single(pp->dev->dev.parent, 18062e3173a3SEzequiel Garcia tx_desc->buf_phys_addr, 1807c5aff182SThomas Petazzoni tx_desc->data_size, DMA_TO_DEVICE); 1808b0a43db9SLorenzo Bianconi if (buf->type == MVNETA_TYPE_SKB && buf->skb) { 18099e58c8b4SLorenzo Bianconi bytes_compl += buf->skb->len; 18109e58c8b4SLorenzo Bianconi pkts_compl++; 18119e58c8b4SLorenzo Bianconi dev_kfree_skb_any(buf->skb); 1812b0a43db9SLorenzo Bianconi } else if (buf->type == MVNETA_TYPE_XDP_TX || 1813b0a43db9SLorenzo Bianconi buf->type == MVNETA_TYPE_XDP_NDO) { 1814b0a43db9SLorenzo Bianconi xdp_return_frame(buf->xdpf); 1815b0a43db9SLorenzo Bianconi } 1816c5aff182SThomas Petazzoni } 1817a29b6235SMarcin Wojtas 1818a29b6235SMarcin Wojtas netdev_tx_completed_queue(nq, pkts_compl, bytes_compl); 1819c5aff182SThomas Petazzoni } 1820c5aff182SThomas Petazzoni 1821c5aff182SThomas Petazzoni /* Handle end of transmission */ 1822cd713199SArnaud Ebalard static void mvneta_txq_done(struct mvneta_port *pp, 1823c5aff182SThomas Petazzoni struct mvneta_tx_queue *txq) 1824c5aff182SThomas Petazzoni { 1825c5aff182SThomas Petazzoni struct netdev_queue *nq = netdev_get_tx_queue(pp->dev, txq->id); 1826c5aff182SThomas Petazzoni int tx_done; 1827c5aff182SThomas Petazzoni 1828c5aff182SThomas Petazzoni tx_done = mvneta_txq_sent_desc_proc(pp, txq); 1829cd713199SArnaud Ebalard if (!tx_done) 1830cd713199SArnaud Ebalard return; 1831cd713199SArnaud Ebalard 1832a29b6235SMarcin Wojtas mvneta_txq_bufs_free(pp, txq, tx_done, nq); 1833c5aff182SThomas Petazzoni 1834c5aff182SThomas Petazzoni txq->count -= tx_done; 1835c5aff182SThomas Petazzoni 1836c5aff182SThomas Petazzoni if (netif_tx_queue_stopped(nq)) { 18378eef5f97SEzequiel Garcia if (txq->count <= txq->tx_wake_threshold) 1838c5aff182SThomas Petazzoni netif_tx_wake_queue(nq); 1839c5aff182SThomas Petazzoni } 1840c5aff182SThomas Petazzoni } 1841c5aff182SThomas Petazzoni 1842dc35a10fSMarcin Wojtas /* Refill processing for SW buffer management */ 18437e47fd84SGregory CLEMENT /* Allocate page per descriptor */ 1844c5aff182SThomas Petazzoni static int mvneta_rx_refill(struct mvneta_port *pp, 1845f88bee1cSGregory CLEMENT struct mvneta_rx_desc *rx_desc, 18467e47fd84SGregory CLEMENT struct mvneta_rx_queue *rxq, 18477e47fd84SGregory CLEMENT gfp_t gfp_mask) 1848c5aff182SThomas Petazzoni { 1849c5aff182SThomas Petazzoni dma_addr_t phys_addr; 18507e47fd84SGregory CLEMENT struct page *page; 1851c5aff182SThomas Petazzoni 1852568a3fa2SLorenzo Bianconi page = page_pool_alloc_pages(rxq->page_pool, 1853568a3fa2SLorenzo Bianconi gfp_mask | __GFP_NOWARN); 18547e47fd84SGregory CLEMENT if (!page) 1855c5aff182SThomas Petazzoni return -ENOMEM; 1856c5aff182SThomas Petazzoni 1857568a3fa2SLorenzo Bianconi phys_addr = page_pool_get_dma_addr(page) + pp->rx_offset_correction; 18587e47fd84SGregory CLEMENT mvneta_rx_desc_fill(rx_desc, phys_addr, page, rxq); 1859568a3fa2SLorenzo Bianconi 1860c5aff182SThomas Petazzoni return 0; 1861c5aff182SThomas Petazzoni } 1862c5aff182SThomas Petazzoni 1863c5aff182SThomas Petazzoni /* Handle tx checksum */ 1864c5aff182SThomas Petazzoni static u32 mvneta_skb_tx_csum(struct mvneta_port *pp, struct sk_buff *skb) 1865c5aff182SThomas Petazzoni { 1866c5aff182SThomas Petazzoni if (skb->ip_summed == CHECKSUM_PARTIAL) { 1867c5aff182SThomas Petazzoni int ip_hdr_len = 0; 1868817dbfa5SVlad Yasevich __be16 l3_proto = vlan_get_protocol(skb); 1869c5aff182SThomas Petazzoni u8 l4_proto; 1870c5aff182SThomas Petazzoni 1871817dbfa5SVlad Yasevich if (l3_proto == htons(ETH_P_IP)) { 1872c5aff182SThomas Petazzoni struct iphdr *ip4h = ip_hdr(skb); 1873c5aff182SThomas Petazzoni 1874c5aff182SThomas Petazzoni /* Calculate IPv4 checksum and L4 checksum */ 1875c5aff182SThomas Petazzoni ip_hdr_len = ip4h->ihl; 1876c5aff182SThomas Petazzoni l4_proto = ip4h->protocol; 1877817dbfa5SVlad Yasevich } else if (l3_proto == htons(ETH_P_IPV6)) { 1878c5aff182SThomas Petazzoni struct ipv6hdr *ip6h = ipv6_hdr(skb); 1879c5aff182SThomas Petazzoni 1880c5aff182SThomas Petazzoni /* Read l4_protocol from one of IPv6 extra headers */ 1881c5aff182SThomas Petazzoni if (skb_network_header_len(skb) > 0) 1882c5aff182SThomas Petazzoni ip_hdr_len = (skb_network_header_len(skb) >> 2); 1883c5aff182SThomas Petazzoni l4_proto = ip6h->nexthdr; 1884c5aff182SThomas Petazzoni } else 1885c5aff182SThomas Petazzoni return MVNETA_TX_L4_CSUM_NOT; 1886c5aff182SThomas Petazzoni 1887c5aff182SThomas Petazzoni return mvneta_txq_desc_csum(skb_network_offset(skb), 1888817dbfa5SVlad Yasevich l3_proto, ip_hdr_len, l4_proto); 1889c5aff182SThomas Petazzoni } 1890c5aff182SThomas Petazzoni 1891c5aff182SThomas Petazzoni return MVNETA_TX_L4_CSUM_NOT; 1892c5aff182SThomas Petazzoni } 1893c5aff182SThomas Petazzoni 1894c5aff182SThomas Petazzoni /* Drop packets received by the RXQ and free buffers */ 1895c5aff182SThomas Petazzoni static void mvneta_rxq_drop_pkts(struct mvneta_port *pp, 1896c5aff182SThomas Petazzoni struct mvneta_rx_queue *rxq) 1897c5aff182SThomas Petazzoni { 1898c5aff182SThomas Petazzoni int rx_done, i; 1899c5aff182SThomas Petazzoni 1900c5aff182SThomas Petazzoni rx_done = mvneta_rxq_busy_desc_num_get(pp, rxq); 1901dc35a10fSMarcin Wojtas if (rx_done) 1902dc35a10fSMarcin Wojtas mvneta_rxq_desc_num_update(pp, rxq, rx_done, rx_done); 1903dc35a10fSMarcin Wojtas 1904dc35a10fSMarcin Wojtas if (pp->bm_priv) { 1905dc35a10fSMarcin Wojtas for (i = 0; i < rx_done; i++) { 1906dc35a10fSMarcin Wojtas struct mvneta_rx_desc *rx_desc = 1907dc35a10fSMarcin Wojtas mvneta_rxq_next_desc_get(rxq); 1908dc35a10fSMarcin Wojtas u8 pool_id = MVNETA_RX_GET_BM_POOL_ID(rx_desc); 1909dc35a10fSMarcin Wojtas struct mvneta_bm_pool *bm_pool; 1910dc35a10fSMarcin Wojtas 1911dc35a10fSMarcin Wojtas bm_pool = &pp->bm_priv->bm_pools[pool_id]; 1912dc35a10fSMarcin Wojtas /* Return dropped buffer to the pool */ 1913dc35a10fSMarcin Wojtas mvneta_bm_pool_put_bp(pp->bm_priv, bm_pool, 1914dc35a10fSMarcin Wojtas rx_desc->buf_phys_addr); 1915dc35a10fSMarcin Wojtas } 1916dc35a10fSMarcin Wojtas return; 1917dc35a10fSMarcin Wojtas } 1918dc35a10fSMarcin Wojtas 1919c5aff182SThomas Petazzoni for (i = 0; i < rxq->size; i++) { 1920c5aff182SThomas Petazzoni struct mvneta_rx_desc *rx_desc = rxq->descs + i; 1921f88bee1cSGregory CLEMENT void *data = rxq->buf_virt_addr[i]; 1922562e2f46SYelena Krivosheev if (!data || !(rx_desc->buf_phys_addr)) 1923562e2f46SYelena Krivosheev continue; 1924c5aff182SThomas Petazzoni 1925568a3fa2SLorenzo Bianconi page_pool_put_page(rxq->page_pool, data, false); 1926dc35a10fSMarcin Wojtas } 1927568a3fa2SLorenzo Bianconi if (xdp_rxq_info_is_reg(&rxq->xdp_rxq)) 1928568a3fa2SLorenzo Bianconi xdp_rxq_info_unreg(&rxq->xdp_rxq); 1929568a3fa2SLorenzo Bianconi page_pool_destroy(rxq->page_pool); 1930568a3fa2SLorenzo Bianconi rxq->page_pool = NULL; 1931c5aff182SThomas Petazzoni } 1932c5aff182SThomas Petazzoni 1933ff519e2aSLorenzo Bianconi static void 1934ff519e2aSLorenzo Bianconi mvneta_update_stats(struct mvneta_port *pp, u32 pkts, 1935ff519e2aSLorenzo Bianconi u32 len, bool tx) 1936ff519e2aSLorenzo Bianconi { 1937ff519e2aSLorenzo Bianconi struct mvneta_pcpu_stats *stats = this_cpu_ptr(pp->stats); 1938ff519e2aSLorenzo Bianconi 1939ff519e2aSLorenzo Bianconi u64_stats_update_begin(&stats->syncp); 1940ff519e2aSLorenzo Bianconi if (tx) { 1941ff519e2aSLorenzo Bianconi stats->tx_packets += pkts; 1942ff519e2aSLorenzo Bianconi stats->tx_bytes += len; 1943ff519e2aSLorenzo Bianconi } else { 1944ff519e2aSLorenzo Bianconi stats->rx_packets += pkts; 1945ff519e2aSLorenzo Bianconi stats->rx_bytes += len; 1946ff519e2aSLorenzo Bianconi } 1947ff519e2aSLorenzo Bianconi u64_stats_update_end(&stats->syncp); 1948ff519e2aSLorenzo Bianconi } 1949ff519e2aSLorenzo Bianconi 1950562e2f46SYelena Krivosheev static inline 1951562e2f46SYelena Krivosheev int mvneta_rx_refill_queue(struct mvneta_port *pp, struct mvneta_rx_queue *rxq) 1952562e2f46SYelena Krivosheev { 1953562e2f46SYelena Krivosheev struct mvneta_rx_desc *rx_desc; 1954562e2f46SYelena Krivosheev int curr_desc = rxq->first_to_refill; 1955562e2f46SYelena Krivosheev int i; 1956562e2f46SYelena Krivosheev 1957562e2f46SYelena Krivosheev for (i = 0; (i < rxq->refill_num) && (i < 64); i++) { 1958562e2f46SYelena Krivosheev rx_desc = rxq->descs + curr_desc; 1959562e2f46SYelena Krivosheev if (!(rx_desc->buf_phys_addr)) { 1960562e2f46SYelena Krivosheev if (mvneta_rx_refill(pp, rx_desc, rxq, GFP_ATOMIC)) { 1961562e2f46SYelena Krivosheev pr_err("Can't refill queue %d. Done %d from %d\n", 1962562e2f46SYelena Krivosheev rxq->id, i, rxq->refill_num); 1963562e2f46SYelena Krivosheev rxq->refill_err++; 1964562e2f46SYelena Krivosheev break; 1965562e2f46SYelena Krivosheev } 1966562e2f46SYelena Krivosheev } 1967562e2f46SYelena Krivosheev curr_desc = MVNETA_QUEUE_NEXT_DESC(rxq, curr_desc); 1968562e2f46SYelena Krivosheev } 1969562e2f46SYelena Krivosheev rxq->refill_num -= i; 1970562e2f46SYelena Krivosheev rxq->first_to_refill = curr_desc; 1971562e2f46SYelena Krivosheev 1972562e2f46SYelena Krivosheev return i; 1973562e2f46SYelena Krivosheev } 1974562e2f46SYelena Krivosheev 19758dc9a088SLorenzo Bianconi static int 1976b0a43db9SLorenzo Bianconi mvneta_xdp_submit_frame(struct mvneta_port *pp, struct mvneta_tx_queue *txq, 1977b0a43db9SLorenzo Bianconi struct xdp_frame *xdpf, bool dma_map) 1978b0a43db9SLorenzo Bianconi { 1979b0a43db9SLorenzo Bianconi struct mvneta_tx_desc *tx_desc; 1980b0a43db9SLorenzo Bianconi struct mvneta_tx_buf *buf; 1981b0a43db9SLorenzo Bianconi dma_addr_t dma_addr; 1982b0a43db9SLorenzo Bianconi 1983b0a43db9SLorenzo Bianconi if (txq->count >= txq->tx_stop_threshold) 1984b0a43db9SLorenzo Bianconi return MVNETA_XDP_DROPPED; 1985b0a43db9SLorenzo Bianconi 1986b0a43db9SLorenzo Bianconi tx_desc = mvneta_txq_next_desc_get(txq); 1987b0a43db9SLorenzo Bianconi 1988b0a43db9SLorenzo Bianconi buf = &txq->buf[txq->txq_put_index]; 1989b0a43db9SLorenzo Bianconi if (dma_map) { 1990b0a43db9SLorenzo Bianconi /* ndo_xdp_xmit */ 1991b0a43db9SLorenzo Bianconi dma_addr = dma_map_single(pp->dev->dev.parent, xdpf->data, 1992b0a43db9SLorenzo Bianconi xdpf->len, DMA_TO_DEVICE); 1993b0a43db9SLorenzo Bianconi if (dma_mapping_error(pp->dev->dev.parent, dma_addr)) { 1994b0a43db9SLorenzo Bianconi mvneta_txq_desc_put(txq); 1995b0a43db9SLorenzo Bianconi return MVNETA_XDP_DROPPED; 1996b0a43db9SLorenzo Bianconi } 1997b0a43db9SLorenzo Bianconi buf->type = MVNETA_TYPE_XDP_NDO; 1998b0a43db9SLorenzo Bianconi } else { 1999b0a43db9SLorenzo Bianconi struct page *page = virt_to_page(xdpf->data); 2000b0a43db9SLorenzo Bianconi 2001b0a43db9SLorenzo Bianconi dma_addr = page_pool_get_dma_addr(page) + 2002b0a43db9SLorenzo Bianconi sizeof(*xdpf) + xdpf->headroom; 2003b0a43db9SLorenzo Bianconi dma_sync_single_for_device(pp->dev->dev.parent, dma_addr, 2004b0a43db9SLorenzo Bianconi xdpf->len, DMA_BIDIRECTIONAL); 2005b0a43db9SLorenzo Bianconi buf->type = MVNETA_TYPE_XDP_TX; 2006b0a43db9SLorenzo Bianconi } 2007b0a43db9SLorenzo Bianconi buf->xdpf = xdpf; 2008b0a43db9SLorenzo Bianconi 2009b0a43db9SLorenzo Bianconi tx_desc->command = MVNETA_TXD_FLZ_DESC; 2010b0a43db9SLorenzo Bianconi tx_desc->buf_phys_addr = dma_addr; 2011b0a43db9SLorenzo Bianconi tx_desc->data_size = xdpf->len; 2012b0a43db9SLorenzo Bianconi 2013b0a43db9SLorenzo Bianconi mvneta_update_stats(pp, 1, xdpf->len, true); 2014b0a43db9SLorenzo Bianconi mvneta_txq_inc_put(txq); 2015b0a43db9SLorenzo Bianconi txq->pending++; 2016b0a43db9SLorenzo Bianconi txq->count++; 2017b0a43db9SLorenzo Bianconi 2018b0a43db9SLorenzo Bianconi return MVNETA_XDP_TX; 2019b0a43db9SLorenzo Bianconi } 2020b0a43db9SLorenzo Bianconi 2021b0a43db9SLorenzo Bianconi static int 2022b0a43db9SLorenzo Bianconi mvneta_xdp_xmit_back(struct mvneta_port *pp, struct xdp_buff *xdp) 2023b0a43db9SLorenzo Bianconi { 2024b0a43db9SLorenzo Bianconi struct mvneta_tx_queue *txq; 2025b0a43db9SLorenzo Bianconi struct netdev_queue *nq; 2026b0a43db9SLorenzo Bianconi struct xdp_frame *xdpf; 2027b0a43db9SLorenzo Bianconi int cpu; 2028b0a43db9SLorenzo Bianconi u32 ret; 2029b0a43db9SLorenzo Bianconi 2030b0a43db9SLorenzo Bianconi xdpf = convert_to_xdp_frame(xdp); 2031b0a43db9SLorenzo Bianconi if (unlikely(!xdpf)) 2032b0a43db9SLorenzo Bianconi return MVNETA_XDP_DROPPED; 2033b0a43db9SLorenzo Bianconi 2034b0a43db9SLorenzo Bianconi cpu = smp_processor_id(); 2035b0a43db9SLorenzo Bianconi txq = &pp->txqs[cpu % txq_number]; 2036b0a43db9SLorenzo Bianconi nq = netdev_get_tx_queue(pp->dev, txq->id); 2037b0a43db9SLorenzo Bianconi 2038b0a43db9SLorenzo Bianconi __netif_tx_lock(nq, cpu); 2039b0a43db9SLorenzo Bianconi ret = mvneta_xdp_submit_frame(pp, txq, xdpf, false); 2040b0a43db9SLorenzo Bianconi if (ret == MVNETA_XDP_TX) 2041b0a43db9SLorenzo Bianconi mvneta_txq_pend_desc_add(pp, txq, 0); 2042b0a43db9SLorenzo Bianconi __netif_tx_unlock(nq); 2043b0a43db9SLorenzo Bianconi 2044b0a43db9SLorenzo Bianconi return ret; 2045b0a43db9SLorenzo Bianconi } 2046b0a43db9SLorenzo Bianconi 2047b0a43db9SLorenzo Bianconi static int 2048b0a43db9SLorenzo Bianconi mvneta_xdp_xmit(struct net_device *dev, int num_frame, 2049b0a43db9SLorenzo Bianconi struct xdp_frame **frames, u32 flags) 2050b0a43db9SLorenzo Bianconi { 2051b0a43db9SLorenzo Bianconi struct mvneta_port *pp = netdev_priv(dev); 2052b0a43db9SLorenzo Bianconi int cpu = smp_processor_id(); 2053b0a43db9SLorenzo Bianconi struct mvneta_tx_queue *txq; 2054b0a43db9SLorenzo Bianconi struct netdev_queue *nq; 2055b0a43db9SLorenzo Bianconi int i, drops = 0; 2056b0a43db9SLorenzo Bianconi u32 ret; 2057b0a43db9SLorenzo Bianconi 2058b0a43db9SLorenzo Bianconi if (unlikely(flags & ~XDP_XMIT_FLAGS_MASK)) 2059b0a43db9SLorenzo Bianconi return -EINVAL; 2060b0a43db9SLorenzo Bianconi 2061b0a43db9SLorenzo Bianconi txq = &pp->txqs[cpu % txq_number]; 2062b0a43db9SLorenzo Bianconi nq = netdev_get_tx_queue(pp->dev, txq->id); 2063b0a43db9SLorenzo Bianconi 2064b0a43db9SLorenzo Bianconi __netif_tx_lock(nq, cpu); 2065b0a43db9SLorenzo Bianconi for (i = 0; i < num_frame; i++) { 2066b0a43db9SLorenzo Bianconi ret = mvneta_xdp_submit_frame(pp, txq, frames[i], true); 2067b0a43db9SLorenzo Bianconi if (ret != MVNETA_XDP_TX) { 2068b0a43db9SLorenzo Bianconi xdp_return_frame_rx_napi(frames[i]); 2069b0a43db9SLorenzo Bianconi drops++; 2070b0a43db9SLorenzo Bianconi } 2071b0a43db9SLorenzo Bianconi } 2072b0a43db9SLorenzo Bianconi 2073b0a43db9SLorenzo Bianconi if (unlikely(flags & XDP_XMIT_FLUSH)) 2074b0a43db9SLorenzo Bianconi mvneta_txq_pend_desc_add(pp, txq, 0); 2075b0a43db9SLorenzo Bianconi __netif_tx_unlock(nq); 2076b0a43db9SLorenzo Bianconi 2077b0a43db9SLorenzo Bianconi return num_frame - drops; 2078b0a43db9SLorenzo Bianconi } 2079b0a43db9SLorenzo Bianconi 2080b0a43db9SLorenzo Bianconi static int 20810db51da7SLorenzo Bianconi mvneta_run_xdp(struct mvneta_port *pp, struct mvneta_rx_queue *rxq, 20820db51da7SLorenzo Bianconi struct bpf_prog *prog, struct xdp_buff *xdp) 20830db51da7SLorenzo Bianconi { 20840db51da7SLorenzo Bianconi u32 ret, act = bpf_prog_run_xdp(prog, xdp); 20850db51da7SLorenzo Bianconi 20860db51da7SLorenzo Bianconi switch (act) { 20870db51da7SLorenzo Bianconi case XDP_PASS: 20880db51da7SLorenzo Bianconi ret = MVNETA_XDP_PASS; 20890db51da7SLorenzo Bianconi break; 20900db51da7SLorenzo Bianconi case XDP_REDIRECT: { 20910db51da7SLorenzo Bianconi int err; 20920db51da7SLorenzo Bianconi 20930db51da7SLorenzo Bianconi err = xdp_do_redirect(pp->dev, xdp, prog); 20940db51da7SLorenzo Bianconi if (err) { 20950db51da7SLorenzo Bianconi ret = MVNETA_XDP_DROPPED; 209607e13edbSLorenzo Bianconi __page_pool_put_page(rxq->page_pool, 209707e13edbSLorenzo Bianconi virt_to_head_page(xdp->data), 209807e13edbSLorenzo Bianconi xdp->data_end - xdp->data_hard_start, 209907e13edbSLorenzo Bianconi true); 21000db51da7SLorenzo Bianconi } else { 21010db51da7SLorenzo Bianconi ret = MVNETA_XDP_REDIR; 21020db51da7SLorenzo Bianconi } 21030db51da7SLorenzo Bianconi break; 21040db51da7SLorenzo Bianconi } 2105b0a43db9SLorenzo Bianconi case XDP_TX: 2106b0a43db9SLorenzo Bianconi ret = mvneta_xdp_xmit_back(pp, xdp); 2107b0a43db9SLorenzo Bianconi if (ret != MVNETA_XDP_TX) 210807e13edbSLorenzo Bianconi __page_pool_put_page(rxq->page_pool, 210907e13edbSLorenzo Bianconi virt_to_head_page(xdp->data), 211007e13edbSLorenzo Bianconi xdp->data_end - xdp->data_hard_start, 211107e13edbSLorenzo Bianconi true); 2112b0a43db9SLorenzo Bianconi break; 21130db51da7SLorenzo Bianconi default: 21140db51da7SLorenzo Bianconi bpf_warn_invalid_xdp_action(act); 21150db51da7SLorenzo Bianconi /* fall through */ 21160db51da7SLorenzo Bianconi case XDP_ABORTED: 21170db51da7SLorenzo Bianconi trace_xdp_exception(pp->dev, prog, act); 21180db51da7SLorenzo Bianconi /* fall through */ 21190db51da7SLorenzo Bianconi case XDP_DROP: 212007e13edbSLorenzo Bianconi __page_pool_put_page(rxq->page_pool, 212107e13edbSLorenzo Bianconi virt_to_head_page(xdp->data), 212207e13edbSLorenzo Bianconi xdp->data_end - xdp->data_hard_start, 212307e13edbSLorenzo Bianconi true); 21240db51da7SLorenzo Bianconi ret = MVNETA_XDP_DROPPED; 21250db51da7SLorenzo Bianconi break; 21260db51da7SLorenzo Bianconi } 21270db51da7SLorenzo Bianconi 21280db51da7SLorenzo Bianconi return ret; 21290db51da7SLorenzo Bianconi } 21300db51da7SLorenzo Bianconi 21310db51da7SLorenzo Bianconi static int 21328dc9a088SLorenzo Bianconi mvneta_swbm_rx_frame(struct mvneta_port *pp, 21338dc9a088SLorenzo Bianconi struct mvneta_rx_desc *rx_desc, 21348dc9a088SLorenzo Bianconi struct mvneta_rx_queue *rxq, 21350db51da7SLorenzo Bianconi struct xdp_buff *xdp, 21360db51da7SLorenzo Bianconi struct bpf_prog *xdp_prog, 21370db51da7SLorenzo Bianconi struct page *page, u32 *xdp_ret) 21388dc9a088SLorenzo Bianconi { 21398dc9a088SLorenzo Bianconi unsigned char *data = page_address(page); 21408dc9a088SLorenzo Bianconi int data_len = -MVNETA_MH_SIZE, len; 21418dc9a088SLorenzo Bianconi struct net_device *dev = pp->dev; 21428dc9a088SLorenzo Bianconi enum dma_data_direction dma_dir; 21438dc9a088SLorenzo Bianconi 21448dc9a088SLorenzo Bianconi if (MVNETA_SKB_SIZE(rx_desc->data_size) > PAGE_SIZE) { 21458dc9a088SLorenzo Bianconi len = MVNETA_MAX_RX_BUF_SIZE; 21468dc9a088SLorenzo Bianconi data_len += len; 21478dc9a088SLorenzo Bianconi } else { 21488dc9a088SLorenzo Bianconi len = rx_desc->data_size; 21498dc9a088SLorenzo Bianconi data_len += len - ETH_FCS_LEN; 21508dc9a088SLorenzo Bianconi } 21518dc9a088SLorenzo Bianconi 21528dc9a088SLorenzo Bianconi dma_dir = page_pool_get_dma_dir(rxq->page_pool); 21538dc9a088SLorenzo Bianconi dma_sync_single_for_cpu(dev->dev.parent, 21548dc9a088SLorenzo Bianconi rx_desc->buf_phys_addr, 21558dc9a088SLorenzo Bianconi len, dma_dir); 21568dc9a088SLorenzo Bianconi 2157fa383f6bSLorenzo Bianconi /* Prefetch header */ 2158fa383f6bSLorenzo Bianconi prefetch(data); 2159fa383f6bSLorenzo Bianconi 21600db51da7SLorenzo Bianconi xdp->data_hard_start = data; 2161b37fa92eSLorenzo Bianconi xdp->data = data + pp->rx_offset_correction + MVNETA_MH_SIZE; 21620db51da7SLorenzo Bianconi xdp->data_end = xdp->data + data_len; 21630db51da7SLorenzo Bianconi xdp_set_data_meta_invalid(xdp); 21640db51da7SLorenzo Bianconi 21650db51da7SLorenzo Bianconi if (xdp_prog) { 21660db51da7SLorenzo Bianconi u32 ret; 21670db51da7SLorenzo Bianconi 21680db51da7SLorenzo Bianconi ret = mvneta_run_xdp(pp, rxq, xdp_prog, xdp); 21690db51da7SLorenzo Bianconi if (ret != MVNETA_XDP_PASS) { 21700db51da7SLorenzo Bianconi mvneta_update_stats(pp, 1, 21710db51da7SLorenzo Bianconi xdp->data_end - xdp->data, 21720db51da7SLorenzo Bianconi false); 21730db51da7SLorenzo Bianconi rx_desc->buf_phys_addr = 0; 21740db51da7SLorenzo Bianconi *xdp_ret |= ret; 21750db51da7SLorenzo Bianconi return ret; 21760db51da7SLorenzo Bianconi } 21770db51da7SLorenzo Bianconi } 21780db51da7SLorenzo Bianconi 21790db51da7SLorenzo Bianconi rxq->skb = build_skb(xdp->data_hard_start, PAGE_SIZE); 21808dc9a088SLorenzo Bianconi if (unlikely(!rxq->skb)) { 21818dc9a088SLorenzo Bianconi netdev_err(dev, 21828dc9a088SLorenzo Bianconi "Can't allocate skb on queue %d\n", 21838dc9a088SLorenzo Bianconi rxq->id); 21848dc9a088SLorenzo Bianconi dev->stats.rx_dropped++; 21858dc9a088SLorenzo Bianconi rxq->skb_alloc_err++; 21868dc9a088SLorenzo Bianconi return -ENOMEM; 21878dc9a088SLorenzo Bianconi } 21888dc9a088SLorenzo Bianconi page_pool_release_page(rxq->page_pool, page); 21898dc9a088SLorenzo Bianconi 21900db51da7SLorenzo Bianconi skb_reserve(rxq->skb, 21910db51da7SLorenzo Bianconi xdp->data - xdp->data_hard_start); 21920db51da7SLorenzo Bianconi skb_put(rxq->skb, xdp->data_end - xdp->data); 21938dc9a088SLorenzo Bianconi mvneta_rx_csum(pp, rx_desc->status, rxq->skb); 21948dc9a088SLorenzo Bianconi 21958dc9a088SLorenzo Bianconi rxq->left_size = rx_desc->data_size - len; 21968dc9a088SLorenzo Bianconi rx_desc->buf_phys_addr = 0; 21978dc9a088SLorenzo Bianconi 21988dc9a088SLorenzo Bianconi return 0; 21998dc9a088SLorenzo Bianconi } 22008dc9a088SLorenzo Bianconi 22018dc9a088SLorenzo Bianconi static void 22028dc9a088SLorenzo Bianconi mvneta_swbm_add_rx_fragment(struct mvneta_port *pp, 22038dc9a088SLorenzo Bianconi struct mvneta_rx_desc *rx_desc, 22048dc9a088SLorenzo Bianconi struct mvneta_rx_queue *rxq, 22058dc9a088SLorenzo Bianconi struct page *page) 22068dc9a088SLorenzo Bianconi { 22078dc9a088SLorenzo Bianconi struct net_device *dev = pp->dev; 22088dc9a088SLorenzo Bianconi enum dma_data_direction dma_dir; 22098dc9a088SLorenzo Bianconi int data_len, len; 22108dc9a088SLorenzo Bianconi 22118dc9a088SLorenzo Bianconi if (rxq->left_size > MVNETA_MAX_RX_BUF_SIZE) { 22128dc9a088SLorenzo Bianconi len = MVNETA_MAX_RX_BUF_SIZE; 22138dc9a088SLorenzo Bianconi data_len = len; 22148dc9a088SLorenzo Bianconi } else { 22158dc9a088SLorenzo Bianconi len = rxq->left_size; 22168dc9a088SLorenzo Bianconi data_len = len - ETH_FCS_LEN; 22178dc9a088SLorenzo Bianconi } 22188dc9a088SLorenzo Bianconi dma_dir = page_pool_get_dma_dir(rxq->page_pool); 22198dc9a088SLorenzo Bianconi dma_sync_single_for_cpu(dev->dev.parent, 22208dc9a088SLorenzo Bianconi rx_desc->buf_phys_addr, 22218dc9a088SLorenzo Bianconi len, dma_dir); 22228dc9a088SLorenzo Bianconi if (data_len > 0) { 22238dc9a088SLorenzo Bianconi /* refill descriptor with new buffer later */ 22248dc9a088SLorenzo Bianconi skb_add_rx_frag(rxq->skb, 22258dc9a088SLorenzo Bianconi skb_shinfo(rxq->skb)->nr_frags, 2226b37fa92eSLorenzo Bianconi page, pp->rx_offset_correction, data_len, 22278dc9a088SLorenzo Bianconi PAGE_SIZE); 22288dc9a088SLorenzo Bianconi } 22298dc9a088SLorenzo Bianconi page_pool_release_page(rxq->page_pool, page); 22308dc9a088SLorenzo Bianconi rx_desc->buf_phys_addr = 0; 22318dc9a088SLorenzo Bianconi rxq->left_size -= len; 22328dc9a088SLorenzo Bianconi } 22338dc9a088SLorenzo Bianconi 2234dc35a10fSMarcin Wojtas /* Main rx processing when using software buffer management */ 22357a86f05fSAndrew Lunn static int mvneta_rx_swbm(struct napi_struct *napi, 2236562e2f46SYelena Krivosheev struct mvneta_port *pp, int budget, 2237c5aff182SThomas Petazzoni struct mvneta_rx_queue *rxq) 2238c5aff182SThomas Petazzoni { 22398dc9a088SLorenzo Bianconi int rcvd_pkts = 0, rcvd_bytes = 0, rx_proc = 0; 2240c5aff182SThomas Petazzoni struct net_device *dev = pp->dev; 22410db51da7SLorenzo Bianconi struct bpf_prog *xdp_prog; 22420db51da7SLorenzo Bianconi struct xdp_buff xdp_buf; 22438dc9a088SLorenzo Bianconi int rx_todo, refill; 22440db51da7SLorenzo Bianconi u32 xdp_ret = 0; 2245c5aff182SThomas Petazzoni 2246c5aff182SThomas Petazzoni /* Get number of received packets */ 2247562e2f46SYelena Krivosheev rx_todo = mvneta_rxq_busy_desc_num_get(pp, rxq); 2248c5aff182SThomas Petazzoni 22490db51da7SLorenzo Bianconi rcu_read_lock(); 22500db51da7SLorenzo Bianconi xdp_prog = READ_ONCE(pp->xdp_prog); 22510db51da7SLorenzo Bianconi xdp_buf.rxq = &rxq->xdp_rxq; 22520db51da7SLorenzo Bianconi 2253c5aff182SThomas Petazzoni /* Fairness NAPI loop */ 22548dc9a088SLorenzo Bianconi while (rx_proc < budget && rx_proc < rx_todo) { 2255c5aff182SThomas Petazzoni struct mvneta_rx_desc *rx_desc = mvneta_rxq_next_desc_get(rxq); 22568dc9a088SLorenzo Bianconi u32 rx_status, index; 22577e47fd84SGregory CLEMENT struct page *page; 2258c5aff182SThomas Petazzoni 2259f88bee1cSGregory CLEMENT index = rx_desc - rxq->descs; 22607e47fd84SGregory CLEMENT page = (struct page *)rxq->buf_virt_addr[index]; 2261c5aff182SThomas Petazzoni 2262562e2f46SYelena Krivosheev rx_status = rx_desc->status; 2263562e2f46SYelena Krivosheev rx_proc++; 2264562e2f46SYelena Krivosheev rxq->refill_num++; 2265562e2f46SYelena Krivosheev 2266562e2f46SYelena Krivosheev if (rx_status & MVNETA_RXD_FIRST_DESC) { 22678dc9a088SLorenzo Bianconi int err; 22688dc9a088SLorenzo Bianconi 2269562e2f46SYelena Krivosheev /* Check errors only for FIRST descriptor */ 2270562e2f46SYelena Krivosheev if (rx_status & MVNETA_RXD_ERR_SUMMARY) { 22712eecb2e0SYelena Krivosheev mvneta_rx_error(pp, rx_desc); 2272c5aff182SThomas Petazzoni dev->stats.rx_errors++; 22738ec2cd48Swilly tarreau /* leave the descriptor untouched */ 2274c5aff182SThomas Petazzoni continue; 2275c5aff182SThomas Petazzoni } 2276c5aff182SThomas Petazzoni 22770db51da7SLorenzo Bianconi err = mvneta_swbm_rx_frame(pp, rx_desc, rxq, &xdp_buf, 22780db51da7SLorenzo Bianconi xdp_prog, page, &xdp_ret); 22798dc9a088SLorenzo Bianconi if (err) 2280f19fadfcSwilly tarreau continue; 2281562e2f46SYelena Krivosheev } else { 2282562e2f46SYelena Krivosheev if (unlikely(!rxq->skb)) { 2283562e2f46SYelena Krivosheev pr_debug("no skb for rx_status 0x%x\n", 2284562e2f46SYelena Krivosheev rx_status); 2285562e2f46SYelena Krivosheev continue; 2286562e2f46SYelena Krivosheev } 22878dc9a088SLorenzo Bianconi mvneta_swbm_add_rx_fragment(pp, rx_desc, rxq, page); 2288562e2f46SYelena Krivosheev } /* Middle or Last descriptor */ 2289562e2f46SYelena Krivosheev 2290562e2f46SYelena Krivosheev if (!(rx_status & MVNETA_RXD_LAST_DESC)) 2291562e2f46SYelena Krivosheev /* no last descriptor this time */ 2292562e2f46SYelena Krivosheev continue; 2293562e2f46SYelena Krivosheev 2294562e2f46SYelena Krivosheev if (rxq->left_size) { 2295562e2f46SYelena Krivosheev pr_err("get last desc, but left_size (%d) != 0\n", 2296562e2f46SYelena Krivosheev rxq->left_size); 2297562e2f46SYelena Krivosheev dev_kfree_skb_any(rxq->skb); 2298562e2f46SYelena Krivosheev rxq->left_size = 0; 2299562e2f46SYelena Krivosheev rxq->skb = NULL; 2300562e2f46SYelena Krivosheev continue; 2301562e2f46SYelena Krivosheev } 2302dc4277ddSwilly tarreau rcvd_pkts++; 2303562e2f46SYelena Krivosheev rcvd_bytes += rxq->skb->len; 2304c5aff182SThomas Petazzoni 2305c5aff182SThomas Petazzoni /* Linux processing */ 2306562e2f46SYelena Krivosheev rxq->skb->protocol = eth_type_trans(rxq->skb, dev); 2307c5aff182SThomas Petazzoni 2308562e2f46SYelena Krivosheev napi_gro_receive(napi, rxq->skb); 2309c5aff182SThomas Petazzoni 2310562e2f46SYelena Krivosheev /* clean uncomplete skb pointer in queue */ 2311562e2f46SYelena Krivosheev rxq->skb = NULL; 2312c5aff182SThomas Petazzoni } 23130db51da7SLorenzo Bianconi rcu_read_unlock(); 23140db51da7SLorenzo Bianconi 23150db51da7SLorenzo Bianconi if (xdp_ret & MVNETA_XDP_REDIR) 23160db51da7SLorenzo Bianconi xdp_do_flush_map(); 2317c5aff182SThomas Petazzoni 2318ff519e2aSLorenzo Bianconi if (rcvd_pkts) 2319ff519e2aSLorenzo Bianconi mvneta_update_stats(pp, rcvd_pkts, rcvd_bytes, false); 2320dc4277ddSwilly tarreau 2321562e2f46SYelena Krivosheev /* return some buffers to hardware queue, one at a time is too slow */ 2322562e2f46SYelena Krivosheev refill = mvneta_rx_refill_queue(pp, rxq); 2323c5aff182SThomas Petazzoni 2324562e2f46SYelena Krivosheev /* Update rxq management counters */ 2325562e2f46SYelena Krivosheev mvneta_rxq_desc_num_update(pp, rxq, rx_proc, refill); 2326562e2f46SYelena Krivosheev 2327562e2f46SYelena Krivosheev return rcvd_pkts; 2328c5aff182SThomas Petazzoni } 2329c5aff182SThomas Petazzoni 2330dc35a10fSMarcin Wojtas /* Main rx processing when using hardware buffer management */ 23317a86f05fSAndrew Lunn static int mvneta_rx_hwbm(struct napi_struct *napi, 23327a86f05fSAndrew Lunn struct mvneta_port *pp, int rx_todo, 2333dc35a10fSMarcin Wojtas struct mvneta_rx_queue *rxq) 2334dc35a10fSMarcin Wojtas { 2335dc35a10fSMarcin Wojtas struct net_device *dev = pp->dev; 2336dc35a10fSMarcin Wojtas int rx_done; 2337dc35a10fSMarcin Wojtas u32 rcvd_pkts = 0; 2338dc35a10fSMarcin Wojtas u32 rcvd_bytes = 0; 2339dc35a10fSMarcin Wojtas 2340dc35a10fSMarcin Wojtas /* Get number of received packets */ 2341dc35a10fSMarcin Wojtas rx_done = mvneta_rxq_busy_desc_num_get(pp, rxq); 2342dc35a10fSMarcin Wojtas 2343dc35a10fSMarcin Wojtas if (rx_todo > rx_done) 2344dc35a10fSMarcin Wojtas rx_todo = rx_done; 2345dc35a10fSMarcin Wojtas 2346dc35a10fSMarcin Wojtas rx_done = 0; 2347dc35a10fSMarcin Wojtas 2348dc35a10fSMarcin Wojtas /* Fairness NAPI loop */ 2349dc35a10fSMarcin Wojtas while (rx_done < rx_todo) { 2350dc35a10fSMarcin Wojtas struct mvneta_rx_desc *rx_desc = mvneta_rxq_next_desc_get(rxq); 2351dc35a10fSMarcin Wojtas struct mvneta_bm_pool *bm_pool = NULL; 2352dc35a10fSMarcin Wojtas struct sk_buff *skb; 2353dc35a10fSMarcin Wojtas unsigned char *data; 2354dc35a10fSMarcin Wojtas dma_addr_t phys_addr; 2355dc35a10fSMarcin Wojtas u32 rx_status, frag_size; 2356dc35a10fSMarcin Wojtas int rx_bytes, err; 2357dc35a10fSMarcin Wojtas u8 pool_id; 2358dc35a10fSMarcin Wojtas 2359dc35a10fSMarcin Wojtas rx_done++; 2360dc35a10fSMarcin Wojtas rx_status = rx_desc->status; 2361dc35a10fSMarcin Wojtas rx_bytes = rx_desc->data_size - (ETH_FCS_LEN + MVNETA_MH_SIZE); 2362f88bee1cSGregory CLEMENT data = (u8 *)(uintptr_t)rx_desc->buf_cookie; 2363dc35a10fSMarcin Wojtas phys_addr = rx_desc->buf_phys_addr; 2364dc35a10fSMarcin Wojtas pool_id = MVNETA_RX_GET_BM_POOL_ID(rx_desc); 2365dc35a10fSMarcin Wojtas bm_pool = &pp->bm_priv->bm_pools[pool_id]; 2366dc35a10fSMarcin Wojtas 2367dc35a10fSMarcin Wojtas if (!mvneta_rxq_desc_is_first_last(rx_status) || 2368dc35a10fSMarcin Wojtas (rx_status & MVNETA_RXD_ERR_SUMMARY)) { 2369dc35a10fSMarcin Wojtas err_drop_frame_ret_pool: 2370dc35a10fSMarcin Wojtas /* Return the buffer to the pool */ 2371dc35a10fSMarcin Wojtas mvneta_bm_pool_put_bp(pp->bm_priv, bm_pool, 2372dc35a10fSMarcin Wojtas rx_desc->buf_phys_addr); 2373dc35a10fSMarcin Wojtas err_drop_frame: 2374dc35a10fSMarcin Wojtas dev->stats.rx_errors++; 2375dc35a10fSMarcin Wojtas mvneta_rx_error(pp, rx_desc); 2376dc35a10fSMarcin Wojtas /* leave the descriptor untouched */ 2377dc35a10fSMarcin Wojtas continue; 2378dc35a10fSMarcin Wojtas } 2379dc35a10fSMarcin Wojtas 2380dc35a10fSMarcin Wojtas if (rx_bytes <= rx_copybreak) { 2381dc35a10fSMarcin Wojtas /* better copy a small frame and not unmap the DMA region */ 2382dc35a10fSMarcin Wojtas skb = netdev_alloc_skb_ip_align(dev, rx_bytes); 2383dc35a10fSMarcin Wojtas if (unlikely(!skb)) 2384dc35a10fSMarcin Wojtas goto err_drop_frame_ret_pool; 2385dc35a10fSMarcin Wojtas 2386a8fef9baSRussell King dma_sync_single_range_for_cpu(&pp->bm_priv->pdev->dev, 2387dc35a10fSMarcin Wojtas rx_desc->buf_phys_addr, 2388dc35a10fSMarcin Wojtas MVNETA_MH_SIZE + NET_SKB_PAD, 2389dc35a10fSMarcin Wojtas rx_bytes, 2390dc35a10fSMarcin Wojtas DMA_FROM_DEVICE); 239159ae1d12SJohannes Berg skb_put_data(skb, data + MVNETA_MH_SIZE + NET_SKB_PAD, 2392dc35a10fSMarcin Wojtas rx_bytes); 2393dc35a10fSMarcin Wojtas 2394dc35a10fSMarcin Wojtas skb->protocol = eth_type_trans(skb, dev); 2395dc35a10fSMarcin Wojtas mvneta_rx_csum(pp, rx_status, skb); 23967a86f05fSAndrew Lunn napi_gro_receive(napi, skb); 2397dc35a10fSMarcin Wojtas 2398dc35a10fSMarcin Wojtas rcvd_pkts++; 2399dc35a10fSMarcin Wojtas rcvd_bytes += rx_bytes; 2400dc35a10fSMarcin Wojtas 2401dc35a10fSMarcin Wojtas /* Return the buffer to the pool */ 2402dc35a10fSMarcin Wojtas mvneta_bm_pool_put_bp(pp->bm_priv, bm_pool, 2403dc35a10fSMarcin Wojtas rx_desc->buf_phys_addr); 2404dc35a10fSMarcin Wojtas 2405dc35a10fSMarcin Wojtas /* leave the descriptor and buffer untouched */ 2406dc35a10fSMarcin Wojtas continue; 2407dc35a10fSMarcin Wojtas } 2408dc35a10fSMarcin Wojtas 2409dc35a10fSMarcin Wojtas /* Refill processing */ 2410baa11ebcSGregory CLEMENT err = hwbm_pool_refill(&bm_pool->hwbm_pool, GFP_ATOMIC); 2411dc35a10fSMarcin Wojtas if (err) { 2412dc35a10fSMarcin Wojtas netdev_err(dev, "Linux processing - Can't refill\n"); 241317a96da6SGregory CLEMENT rxq->refill_err++; 2414dc35a10fSMarcin Wojtas goto err_drop_frame_ret_pool; 2415dc35a10fSMarcin Wojtas } 2416dc35a10fSMarcin Wojtas 2417baa11ebcSGregory CLEMENT frag_size = bm_pool->hwbm_pool.frag_size; 2418dc35a10fSMarcin Wojtas 2419dc35a10fSMarcin Wojtas skb = build_skb(data, frag_size > PAGE_SIZE ? 0 : frag_size); 2420dc35a10fSMarcin Wojtas 2421dc35a10fSMarcin Wojtas /* After refill old buffer has to be unmapped regardless 2422dc35a10fSMarcin Wojtas * the skb is successfully built or not. 2423dc35a10fSMarcin Wojtas */ 2424dc35a10fSMarcin Wojtas dma_unmap_single(&pp->bm_priv->pdev->dev, phys_addr, 2425dc35a10fSMarcin Wojtas bm_pool->buf_size, DMA_FROM_DEVICE); 2426dc35a10fSMarcin Wojtas if (!skb) 2427dc35a10fSMarcin Wojtas goto err_drop_frame; 2428dc35a10fSMarcin Wojtas 2429dc35a10fSMarcin Wojtas rcvd_pkts++; 2430dc35a10fSMarcin Wojtas rcvd_bytes += rx_bytes; 2431dc35a10fSMarcin Wojtas 2432dc35a10fSMarcin Wojtas /* Linux processing */ 2433dc35a10fSMarcin Wojtas skb_reserve(skb, MVNETA_MH_SIZE + NET_SKB_PAD); 2434dc35a10fSMarcin Wojtas skb_put(skb, rx_bytes); 2435dc35a10fSMarcin Wojtas 2436dc35a10fSMarcin Wojtas skb->protocol = eth_type_trans(skb, dev); 2437dc35a10fSMarcin Wojtas 2438dc35a10fSMarcin Wojtas mvneta_rx_csum(pp, rx_status, skb); 2439dc35a10fSMarcin Wojtas 24407a86f05fSAndrew Lunn napi_gro_receive(napi, skb); 2441dc35a10fSMarcin Wojtas } 2442dc35a10fSMarcin Wojtas 2443ff519e2aSLorenzo Bianconi if (rcvd_pkts) 2444ff519e2aSLorenzo Bianconi mvneta_update_stats(pp, rcvd_pkts, rcvd_bytes, false); 2445dc35a10fSMarcin Wojtas 2446dc35a10fSMarcin Wojtas /* Update rxq management counters */ 2447dc35a10fSMarcin Wojtas mvneta_rxq_desc_num_update(pp, rxq, rx_done, rx_done); 2448dc35a10fSMarcin Wojtas 2449dc35a10fSMarcin Wojtas return rx_done; 2450dc35a10fSMarcin Wojtas } 2451dc35a10fSMarcin Wojtas 24522adb719dSEzequiel Garcia static inline void 24532adb719dSEzequiel Garcia mvneta_tso_put_hdr(struct sk_buff *skb, 24542adb719dSEzequiel Garcia struct mvneta_port *pp, struct mvneta_tx_queue *txq) 24552adb719dSEzequiel Garcia { 24562adb719dSEzequiel Garcia int hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb); 24579e58c8b4SLorenzo Bianconi struct mvneta_tx_buf *buf = &txq->buf[txq->txq_put_index]; 24589e58c8b4SLorenzo Bianconi struct mvneta_tx_desc *tx_desc; 24592adb719dSEzequiel Garcia 24602adb719dSEzequiel Garcia tx_desc = mvneta_txq_next_desc_get(txq); 24612adb719dSEzequiel Garcia tx_desc->data_size = hdr_len; 24622adb719dSEzequiel Garcia tx_desc->command = mvneta_skb_tx_csum(pp, skb); 24632adb719dSEzequiel Garcia tx_desc->command |= MVNETA_TXD_F_DESC; 24642adb719dSEzequiel Garcia tx_desc->buf_phys_addr = txq->tso_hdrs_phys + 24652adb719dSEzequiel Garcia txq->txq_put_index * TSO_HEADER_SIZE; 24669e58c8b4SLorenzo Bianconi buf->type = MVNETA_TYPE_SKB; 24679e58c8b4SLorenzo Bianconi buf->skb = NULL; 24689e58c8b4SLorenzo Bianconi 24692adb719dSEzequiel Garcia mvneta_txq_inc_put(txq); 24702adb719dSEzequiel Garcia } 24712adb719dSEzequiel Garcia 24722adb719dSEzequiel Garcia static inline int 24732adb719dSEzequiel Garcia mvneta_tso_put_data(struct net_device *dev, struct mvneta_tx_queue *txq, 24742adb719dSEzequiel Garcia struct sk_buff *skb, char *data, int size, 24752adb719dSEzequiel Garcia bool last_tcp, bool is_last) 24762adb719dSEzequiel Garcia { 24779e58c8b4SLorenzo Bianconi struct mvneta_tx_buf *buf = &txq->buf[txq->txq_put_index]; 24782adb719dSEzequiel Garcia struct mvneta_tx_desc *tx_desc; 24792adb719dSEzequiel Garcia 24802adb719dSEzequiel Garcia tx_desc = mvneta_txq_next_desc_get(txq); 24812adb719dSEzequiel Garcia tx_desc->data_size = size; 24822adb719dSEzequiel Garcia tx_desc->buf_phys_addr = dma_map_single(dev->dev.parent, data, 24832adb719dSEzequiel Garcia size, DMA_TO_DEVICE); 24842adb719dSEzequiel Garcia if (unlikely(dma_mapping_error(dev->dev.parent, 24852adb719dSEzequiel Garcia tx_desc->buf_phys_addr))) { 24862adb719dSEzequiel Garcia mvneta_txq_desc_put(txq); 24872adb719dSEzequiel Garcia return -ENOMEM; 24882adb719dSEzequiel Garcia } 24892adb719dSEzequiel Garcia 24902adb719dSEzequiel Garcia tx_desc->command = 0; 24919e58c8b4SLorenzo Bianconi buf->type = MVNETA_TYPE_SKB; 24929e58c8b4SLorenzo Bianconi buf->skb = NULL; 24932adb719dSEzequiel Garcia 24942adb719dSEzequiel Garcia if (last_tcp) { 24952adb719dSEzequiel Garcia /* last descriptor in the TCP packet */ 24962adb719dSEzequiel Garcia tx_desc->command = MVNETA_TXD_L_DESC; 24972adb719dSEzequiel Garcia 24982adb719dSEzequiel Garcia /* last descriptor in SKB */ 24992adb719dSEzequiel Garcia if (is_last) 25009e58c8b4SLorenzo Bianconi buf->skb = skb; 25012adb719dSEzequiel Garcia } 25022adb719dSEzequiel Garcia mvneta_txq_inc_put(txq); 25032adb719dSEzequiel Garcia return 0; 25042adb719dSEzequiel Garcia } 25052adb719dSEzequiel Garcia 25062adb719dSEzequiel Garcia static int mvneta_tx_tso(struct sk_buff *skb, struct net_device *dev, 25072adb719dSEzequiel Garcia struct mvneta_tx_queue *txq) 25082adb719dSEzequiel Garcia { 25092adb719dSEzequiel Garcia int total_len, data_left; 25102adb719dSEzequiel Garcia int desc_count = 0; 25112adb719dSEzequiel Garcia struct mvneta_port *pp = netdev_priv(dev); 25122adb719dSEzequiel Garcia struct tso_t tso; 25132adb719dSEzequiel Garcia int hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb); 25142adb719dSEzequiel Garcia int i; 25152adb719dSEzequiel Garcia 25162adb719dSEzequiel Garcia /* Count needed descriptors */ 25172adb719dSEzequiel Garcia if ((txq->count + tso_count_descs(skb)) >= txq->size) 25182adb719dSEzequiel Garcia return 0; 25192adb719dSEzequiel Garcia 25202adb719dSEzequiel Garcia if (skb_headlen(skb) < (skb_transport_offset(skb) + tcp_hdrlen(skb))) { 25212adb719dSEzequiel Garcia pr_info("*** Is this even possible???!?!?\n"); 25222adb719dSEzequiel Garcia return 0; 25232adb719dSEzequiel Garcia } 25242adb719dSEzequiel Garcia 25252adb719dSEzequiel Garcia /* Initialize the TSO handler, and prepare the first payload */ 25262adb719dSEzequiel Garcia tso_start(skb, &tso); 25272adb719dSEzequiel Garcia 25282adb719dSEzequiel Garcia total_len = skb->len - hdr_len; 25292adb719dSEzequiel Garcia while (total_len > 0) { 25302adb719dSEzequiel Garcia char *hdr; 25312adb719dSEzequiel Garcia 25322adb719dSEzequiel Garcia data_left = min_t(int, skb_shinfo(skb)->gso_size, total_len); 25332adb719dSEzequiel Garcia total_len -= data_left; 25342adb719dSEzequiel Garcia desc_count++; 25352adb719dSEzequiel Garcia 25362adb719dSEzequiel Garcia /* prepare packet headers: MAC + IP + TCP */ 25372adb719dSEzequiel Garcia hdr = txq->tso_hdrs + txq->txq_put_index * TSO_HEADER_SIZE; 25382adb719dSEzequiel Garcia tso_build_hdr(skb, hdr, &tso, data_left, total_len == 0); 25392adb719dSEzequiel Garcia 25402adb719dSEzequiel Garcia mvneta_tso_put_hdr(skb, pp, txq); 25412adb719dSEzequiel Garcia 25422adb719dSEzequiel Garcia while (data_left > 0) { 25432adb719dSEzequiel Garcia int size; 25442adb719dSEzequiel Garcia desc_count++; 25452adb719dSEzequiel Garcia 25462adb719dSEzequiel Garcia size = min_t(int, tso.size, data_left); 25472adb719dSEzequiel Garcia 25482adb719dSEzequiel Garcia if (mvneta_tso_put_data(dev, txq, skb, 25492adb719dSEzequiel Garcia tso.data, size, 25502adb719dSEzequiel Garcia size == data_left, 25512adb719dSEzequiel Garcia total_len == 0)) 25522adb719dSEzequiel Garcia goto err_release; 25532adb719dSEzequiel Garcia data_left -= size; 25542adb719dSEzequiel Garcia 25552adb719dSEzequiel Garcia tso_build_data(skb, &tso, size); 25562adb719dSEzequiel Garcia } 25572adb719dSEzequiel Garcia } 25582adb719dSEzequiel Garcia 25592adb719dSEzequiel Garcia return desc_count; 25602adb719dSEzequiel Garcia 25612adb719dSEzequiel Garcia err_release: 25622adb719dSEzequiel Garcia /* Release all used data descriptors; header descriptors must not 25632adb719dSEzequiel Garcia * be DMA-unmapped. 25642adb719dSEzequiel Garcia */ 25652adb719dSEzequiel Garcia for (i = desc_count - 1; i >= 0; i--) { 25662adb719dSEzequiel Garcia struct mvneta_tx_desc *tx_desc = txq->descs + i; 25672e3173a3SEzequiel Garcia if (!IS_TSO_HEADER(txq, tx_desc->buf_phys_addr)) 25682adb719dSEzequiel Garcia dma_unmap_single(pp->dev->dev.parent, 25692adb719dSEzequiel Garcia tx_desc->buf_phys_addr, 25702adb719dSEzequiel Garcia tx_desc->data_size, 25712adb719dSEzequiel Garcia DMA_TO_DEVICE); 25722adb719dSEzequiel Garcia mvneta_txq_desc_put(txq); 25732adb719dSEzequiel Garcia } 25742adb719dSEzequiel Garcia return 0; 25752adb719dSEzequiel Garcia } 25762adb719dSEzequiel Garcia 2577c5aff182SThomas Petazzoni /* Handle tx fragmentation processing */ 2578c5aff182SThomas Petazzoni static int mvneta_tx_frag_process(struct mvneta_port *pp, struct sk_buff *skb, 2579c5aff182SThomas Petazzoni struct mvneta_tx_queue *txq) 2580c5aff182SThomas Petazzoni { 2581c5aff182SThomas Petazzoni struct mvneta_tx_desc *tx_desc; 25823d4ea02fSEzequiel Garcia int i, nr_frags = skb_shinfo(skb)->nr_frags; 2583c5aff182SThomas Petazzoni 25843d4ea02fSEzequiel Garcia for (i = 0; i < nr_frags; i++) { 25859e58c8b4SLorenzo Bianconi struct mvneta_tx_buf *buf = &txq->buf[txq->txq_put_index]; 2586c5aff182SThomas Petazzoni skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 2587d7840976SMatthew Wilcox (Oracle) void *addr = skb_frag_address(frag); 2588c5aff182SThomas Petazzoni 2589c5aff182SThomas Petazzoni tx_desc = mvneta_txq_next_desc_get(txq); 2590d7840976SMatthew Wilcox (Oracle) tx_desc->data_size = skb_frag_size(frag); 2591c5aff182SThomas Petazzoni 2592c5aff182SThomas Petazzoni tx_desc->buf_phys_addr = 2593c5aff182SThomas Petazzoni dma_map_single(pp->dev->dev.parent, addr, 2594c5aff182SThomas Petazzoni tx_desc->data_size, DMA_TO_DEVICE); 2595c5aff182SThomas Petazzoni 2596c5aff182SThomas Petazzoni if (dma_mapping_error(pp->dev->dev.parent, 2597c5aff182SThomas Petazzoni tx_desc->buf_phys_addr)) { 2598c5aff182SThomas Petazzoni mvneta_txq_desc_put(txq); 2599c5aff182SThomas Petazzoni goto error; 2600c5aff182SThomas Petazzoni } 2601c5aff182SThomas Petazzoni 26023d4ea02fSEzequiel Garcia if (i == nr_frags - 1) { 2603c5aff182SThomas Petazzoni /* Last descriptor */ 2604c5aff182SThomas Petazzoni tx_desc->command = MVNETA_TXD_L_DESC | MVNETA_TXD_Z_PAD; 26059e58c8b4SLorenzo Bianconi buf->skb = skb; 2606c5aff182SThomas Petazzoni } else { 2607c5aff182SThomas Petazzoni /* Descriptor in the middle: Not First, Not Last */ 2608c5aff182SThomas Petazzoni tx_desc->command = 0; 26099e58c8b4SLorenzo Bianconi buf->skb = NULL; 2610c5aff182SThomas Petazzoni } 26119e58c8b4SLorenzo Bianconi buf->type = MVNETA_TYPE_SKB; 26123d4ea02fSEzequiel Garcia mvneta_txq_inc_put(txq); 2613c5aff182SThomas Petazzoni } 2614c5aff182SThomas Petazzoni 2615c5aff182SThomas Petazzoni return 0; 2616c5aff182SThomas Petazzoni 2617c5aff182SThomas Petazzoni error: 2618c5aff182SThomas Petazzoni /* Release all descriptors that were used to map fragments of 26196a20c175SThomas Petazzoni * this packet, as well as the corresponding DMA mappings 26206a20c175SThomas Petazzoni */ 2621c5aff182SThomas Petazzoni for (i = i - 1; i >= 0; i--) { 2622c5aff182SThomas Petazzoni tx_desc = txq->descs + i; 2623c5aff182SThomas Petazzoni dma_unmap_single(pp->dev->dev.parent, 2624c5aff182SThomas Petazzoni tx_desc->buf_phys_addr, 2625c5aff182SThomas Petazzoni tx_desc->data_size, 2626c5aff182SThomas Petazzoni DMA_TO_DEVICE); 2627c5aff182SThomas Petazzoni mvneta_txq_desc_put(txq); 2628c5aff182SThomas Petazzoni } 2629c5aff182SThomas Petazzoni 2630c5aff182SThomas Petazzoni return -ENOMEM; 2631c5aff182SThomas Petazzoni } 2632c5aff182SThomas Petazzoni 2633c5aff182SThomas Petazzoni /* Main tx processing */ 2634f03508ceSYueHaibing static netdev_tx_t mvneta_tx(struct sk_buff *skb, struct net_device *dev) 2635c5aff182SThomas Petazzoni { 2636c5aff182SThomas Petazzoni struct mvneta_port *pp = netdev_priv(dev); 2637ee40a116SWilly Tarreau u16 txq_id = skb_get_queue_mapping(skb); 2638ee40a116SWilly Tarreau struct mvneta_tx_queue *txq = &pp->txqs[txq_id]; 26399e58c8b4SLorenzo Bianconi struct mvneta_tx_buf *buf = &txq->buf[txq->txq_put_index]; 2640c5aff182SThomas Petazzoni struct mvneta_tx_desc *tx_desc; 26415f478b41SEric Dumazet int len = skb->len; 2642c5aff182SThomas Petazzoni int frags = 0; 2643c5aff182SThomas Petazzoni u32 tx_cmd; 2644c5aff182SThomas Petazzoni 2645c5aff182SThomas Petazzoni if (!netif_running(dev)) 2646c5aff182SThomas Petazzoni goto out; 2647c5aff182SThomas Petazzoni 26482adb719dSEzequiel Garcia if (skb_is_gso(skb)) { 26492adb719dSEzequiel Garcia frags = mvneta_tx_tso(skb, dev, txq); 26502adb719dSEzequiel Garcia goto out; 26512adb719dSEzequiel Garcia } 26522adb719dSEzequiel Garcia 2653c5aff182SThomas Petazzoni frags = skb_shinfo(skb)->nr_frags + 1; 2654c5aff182SThomas Petazzoni 2655c5aff182SThomas Petazzoni /* Get a descriptor for the first part of the packet */ 2656c5aff182SThomas Petazzoni tx_desc = mvneta_txq_next_desc_get(txq); 2657c5aff182SThomas Petazzoni 2658c5aff182SThomas Petazzoni tx_cmd = mvneta_skb_tx_csum(pp, skb); 2659c5aff182SThomas Petazzoni 2660c5aff182SThomas Petazzoni tx_desc->data_size = skb_headlen(skb); 2661c5aff182SThomas Petazzoni 2662c5aff182SThomas Petazzoni tx_desc->buf_phys_addr = dma_map_single(dev->dev.parent, skb->data, 2663c5aff182SThomas Petazzoni tx_desc->data_size, 2664c5aff182SThomas Petazzoni DMA_TO_DEVICE); 2665c5aff182SThomas Petazzoni if (unlikely(dma_mapping_error(dev->dev.parent, 2666c5aff182SThomas Petazzoni tx_desc->buf_phys_addr))) { 2667c5aff182SThomas Petazzoni mvneta_txq_desc_put(txq); 2668c5aff182SThomas Petazzoni frags = 0; 2669c5aff182SThomas Petazzoni goto out; 2670c5aff182SThomas Petazzoni } 2671c5aff182SThomas Petazzoni 26729e58c8b4SLorenzo Bianconi buf->type = MVNETA_TYPE_SKB; 2673c5aff182SThomas Petazzoni if (frags == 1) { 2674c5aff182SThomas Petazzoni /* First and Last descriptor */ 2675c5aff182SThomas Petazzoni tx_cmd |= MVNETA_TXD_FLZ_DESC; 2676c5aff182SThomas Petazzoni tx_desc->command = tx_cmd; 26779e58c8b4SLorenzo Bianconi buf->skb = skb; 2678c5aff182SThomas Petazzoni mvneta_txq_inc_put(txq); 2679c5aff182SThomas Petazzoni } else { 2680c5aff182SThomas Petazzoni /* First but not Last */ 2681c5aff182SThomas Petazzoni tx_cmd |= MVNETA_TXD_F_DESC; 26829e58c8b4SLorenzo Bianconi buf->skb = NULL; 2683c5aff182SThomas Petazzoni mvneta_txq_inc_put(txq); 2684c5aff182SThomas Petazzoni tx_desc->command = tx_cmd; 2685c5aff182SThomas Petazzoni /* Continue with other skb fragments */ 2686c5aff182SThomas Petazzoni if (mvneta_tx_frag_process(pp, skb, txq)) { 2687c5aff182SThomas Petazzoni dma_unmap_single(dev->dev.parent, 2688c5aff182SThomas Petazzoni tx_desc->buf_phys_addr, 2689c5aff182SThomas Petazzoni tx_desc->data_size, 2690c5aff182SThomas Petazzoni DMA_TO_DEVICE); 2691c5aff182SThomas Petazzoni mvneta_txq_desc_put(txq); 2692c5aff182SThomas Petazzoni frags = 0; 2693c5aff182SThomas Petazzoni goto out; 2694c5aff182SThomas Petazzoni } 2695c5aff182SThomas Petazzoni } 2696c5aff182SThomas Petazzoni 2697e19d2ddaSEzequiel Garcia out: 2698e19d2ddaSEzequiel Garcia if (frags > 0) { 2699e19d2ddaSEzequiel Garcia struct netdev_queue *nq = netdev_get_tx_queue(dev, txq_id); 2700e19d2ddaSEzequiel Garcia 2701a29b6235SMarcin Wojtas netdev_tx_sent_queue(nq, len); 2702a29b6235SMarcin Wojtas 2703c5aff182SThomas Petazzoni txq->count += frags; 27048eef5f97SEzequiel Garcia if (txq->count >= txq->tx_stop_threshold) 2705c5aff182SThomas Petazzoni netif_tx_stop_queue(nq); 2706c5aff182SThomas Petazzoni 27076b16f9eeSFlorian Westphal if (!netdev_xmit_more() || netif_xmit_stopped(nq) || 27082a90f7e1SSimon Guinot txq->pending + frags > MVNETA_TXQ_DEC_SENT_MASK) 27092a90f7e1SSimon Guinot mvneta_txq_pend_desc_add(pp, txq, frags); 27102a90f7e1SSimon Guinot else 27112a90f7e1SSimon Guinot txq->pending += frags; 27122a90f7e1SSimon Guinot 2713ff519e2aSLorenzo Bianconi mvneta_update_stats(pp, 1, len, true); 2714c5aff182SThomas Petazzoni } else { 2715c5aff182SThomas Petazzoni dev->stats.tx_dropped++; 2716c5aff182SThomas Petazzoni dev_kfree_skb_any(skb); 2717c5aff182SThomas Petazzoni } 2718c5aff182SThomas Petazzoni 2719c5aff182SThomas Petazzoni return NETDEV_TX_OK; 2720c5aff182SThomas Petazzoni } 2721c5aff182SThomas Petazzoni 2722c5aff182SThomas Petazzoni 2723c5aff182SThomas Petazzoni /* Free tx resources, when resetting a port */ 2724c5aff182SThomas Petazzoni static void mvneta_txq_done_force(struct mvneta_port *pp, 2725c5aff182SThomas Petazzoni struct mvneta_tx_queue *txq) 2726c5aff182SThomas Petazzoni 2727c5aff182SThomas Petazzoni { 2728a29b6235SMarcin Wojtas struct netdev_queue *nq = netdev_get_tx_queue(pp->dev, txq->id); 2729c5aff182SThomas Petazzoni int tx_done = txq->count; 2730c5aff182SThomas Petazzoni 2731a29b6235SMarcin Wojtas mvneta_txq_bufs_free(pp, txq, tx_done, nq); 2732c5aff182SThomas Petazzoni 2733c5aff182SThomas Petazzoni /* reset txq */ 2734c5aff182SThomas Petazzoni txq->count = 0; 2735c5aff182SThomas Petazzoni txq->txq_put_index = 0; 2736c5aff182SThomas Petazzoni txq->txq_get_index = 0; 2737c5aff182SThomas Petazzoni } 2738c5aff182SThomas Petazzoni 27396c498974Swilly tarreau /* Handle tx done - called in softirq context. The <cause_tx_done> argument 27406c498974Swilly tarreau * must be a valid cause according to MVNETA_TXQ_INTR_MASK_ALL. 27416c498974Swilly tarreau */ 27420713a86aSArnaud Ebalard static void mvneta_tx_done_gbe(struct mvneta_port *pp, u32 cause_tx_done) 2743c5aff182SThomas Petazzoni { 2744c5aff182SThomas Petazzoni struct mvneta_tx_queue *txq; 2745c5aff182SThomas Petazzoni struct netdev_queue *nq; 2746bd9f1ee3SJisheng Zhang int cpu = smp_processor_id(); 2747c5aff182SThomas Petazzoni 27486c498974Swilly tarreau while (cause_tx_done) { 2749c5aff182SThomas Petazzoni txq = mvneta_tx_done_policy(pp, cause_tx_done); 2750c5aff182SThomas Petazzoni 2751c5aff182SThomas Petazzoni nq = netdev_get_tx_queue(pp->dev, txq->id); 2752bd9f1ee3SJisheng Zhang __netif_tx_lock(nq, cpu); 2753c5aff182SThomas Petazzoni 27540713a86aSArnaud Ebalard if (txq->count) 27550713a86aSArnaud Ebalard mvneta_txq_done(pp, txq); 2756c5aff182SThomas Petazzoni 2757c5aff182SThomas Petazzoni __netif_tx_unlock(nq); 2758c5aff182SThomas Petazzoni cause_tx_done &= ~((1 << txq->id)); 2759c5aff182SThomas Petazzoni } 2760c5aff182SThomas Petazzoni } 2761c5aff182SThomas Petazzoni 27626a20c175SThomas Petazzoni /* Compute crc8 of the specified address, using a unique algorithm , 2763c5aff182SThomas Petazzoni * according to hw spec, different than generic crc8 algorithm 2764c5aff182SThomas Petazzoni */ 2765c5aff182SThomas Petazzoni static int mvneta_addr_crc(unsigned char *addr) 2766c5aff182SThomas Petazzoni { 2767c5aff182SThomas Petazzoni int crc = 0; 2768c5aff182SThomas Petazzoni int i; 2769c5aff182SThomas Petazzoni 2770c5aff182SThomas Petazzoni for (i = 0; i < ETH_ALEN; i++) { 2771c5aff182SThomas Petazzoni int j; 2772c5aff182SThomas Petazzoni 2773c5aff182SThomas Petazzoni crc = (crc ^ addr[i]) << 8; 2774c5aff182SThomas Petazzoni for (j = 7; j >= 0; j--) { 2775c5aff182SThomas Petazzoni if (crc & (0x100 << j)) 2776c5aff182SThomas Petazzoni crc ^= 0x107 << j; 2777c5aff182SThomas Petazzoni } 2778c5aff182SThomas Petazzoni } 2779c5aff182SThomas Petazzoni 2780c5aff182SThomas Petazzoni return crc; 2781c5aff182SThomas Petazzoni } 2782c5aff182SThomas Petazzoni 2783c5aff182SThomas Petazzoni /* This method controls the net device special MAC multicast support. 2784c5aff182SThomas Petazzoni * The Special Multicast Table for MAC addresses supports MAC of the form 2785c5aff182SThomas Petazzoni * 0x01-00-5E-00-00-XX (where XX is between 0x00 and 0xFF). 2786c5aff182SThomas Petazzoni * The MAC DA[7:0] bits are used as a pointer to the Special Multicast 2787c5aff182SThomas Petazzoni * Table entries in the DA-Filter table. This method set the Special 2788c5aff182SThomas Petazzoni * Multicast Table appropriate entry. 2789c5aff182SThomas Petazzoni */ 2790c5aff182SThomas Petazzoni static void mvneta_set_special_mcast_addr(struct mvneta_port *pp, 2791c5aff182SThomas Petazzoni unsigned char last_byte, 2792c5aff182SThomas Petazzoni int queue) 2793c5aff182SThomas Petazzoni { 2794c5aff182SThomas Petazzoni unsigned int smc_table_reg; 2795c5aff182SThomas Petazzoni unsigned int tbl_offset; 2796c5aff182SThomas Petazzoni unsigned int reg_offset; 2797c5aff182SThomas Petazzoni 2798c5aff182SThomas Petazzoni /* Register offset from SMC table base */ 2799c5aff182SThomas Petazzoni tbl_offset = (last_byte / 4); 2800c5aff182SThomas Petazzoni /* Entry offset within the above reg */ 2801c5aff182SThomas Petazzoni reg_offset = last_byte % 4; 2802c5aff182SThomas Petazzoni 2803c5aff182SThomas Petazzoni smc_table_reg = mvreg_read(pp, (MVNETA_DA_FILT_SPEC_MCAST 2804c5aff182SThomas Petazzoni + tbl_offset * 4)); 2805c5aff182SThomas Petazzoni 2806c5aff182SThomas Petazzoni if (queue == -1) 2807c5aff182SThomas Petazzoni smc_table_reg &= ~(0xff << (8 * reg_offset)); 2808c5aff182SThomas Petazzoni else { 2809c5aff182SThomas Petazzoni smc_table_reg &= ~(0xff << (8 * reg_offset)); 2810c5aff182SThomas Petazzoni smc_table_reg |= ((0x01 | (queue << 1)) << (8 * reg_offset)); 2811c5aff182SThomas Petazzoni } 2812c5aff182SThomas Petazzoni 2813c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_DA_FILT_SPEC_MCAST + tbl_offset * 4, 2814c5aff182SThomas Petazzoni smc_table_reg); 2815c5aff182SThomas Petazzoni } 2816c5aff182SThomas Petazzoni 2817c5aff182SThomas Petazzoni /* This method controls the network device Other MAC multicast support. 2818c5aff182SThomas Petazzoni * The Other Multicast Table is used for multicast of another type. 2819c5aff182SThomas Petazzoni * A CRC-8 is used as an index to the Other Multicast Table entries 2820c5aff182SThomas Petazzoni * in the DA-Filter table. 2821c5aff182SThomas Petazzoni * The method gets the CRC-8 value from the calling routine and 2822c5aff182SThomas Petazzoni * sets the Other Multicast Table appropriate entry according to the 2823c5aff182SThomas Petazzoni * specified CRC-8 . 2824c5aff182SThomas Petazzoni */ 2825c5aff182SThomas Petazzoni static void mvneta_set_other_mcast_addr(struct mvneta_port *pp, 2826c5aff182SThomas Petazzoni unsigned char crc8, 2827c5aff182SThomas Petazzoni int queue) 2828c5aff182SThomas Petazzoni { 2829c5aff182SThomas Petazzoni unsigned int omc_table_reg; 2830c5aff182SThomas Petazzoni unsigned int tbl_offset; 2831c5aff182SThomas Petazzoni unsigned int reg_offset; 2832c5aff182SThomas Petazzoni 2833c5aff182SThomas Petazzoni tbl_offset = (crc8 / 4) * 4; /* Register offset from OMC table base */ 2834c5aff182SThomas Petazzoni reg_offset = crc8 % 4; /* Entry offset within the above reg */ 2835c5aff182SThomas Petazzoni 2836c5aff182SThomas Petazzoni omc_table_reg = mvreg_read(pp, MVNETA_DA_FILT_OTH_MCAST + tbl_offset); 2837c5aff182SThomas Petazzoni 2838c5aff182SThomas Petazzoni if (queue == -1) { 2839c5aff182SThomas Petazzoni /* Clear accepts frame bit at specified Other DA table entry */ 2840c5aff182SThomas Petazzoni omc_table_reg &= ~(0xff << (8 * reg_offset)); 2841c5aff182SThomas Petazzoni } else { 2842c5aff182SThomas Petazzoni omc_table_reg &= ~(0xff << (8 * reg_offset)); 2843c5aff182SThomas Petazzoni omc_table_reg |= ((0x01 | (queue << 1)) << (8 * reg_offset)); 2844c5aff182SThomas Petazzoni } 2845c5aff182SThomas Petazzoni 2846c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_DA_FILT_OTH_MCAST + tbl_offset, omc_table_reg); 2847c5aff182SThomas Petazzoni } 2848c5aff182SThomas Petazzoni 2849c5aff182SThomas Petazzoni /* The network device supports multicast using two tables: 2850c5aff182SThomas Petazzoni * 1) Special Multicast Table for MAC addresses of the form 2851c5aff182SThomas Petazzoni * 0x01-00-5E-00-00-XX (where XX is between 0x00 and 0xFF). 2852c5aff182SThomas Petazzoni * The MAC DA[7:0] bits are used as a pointer to the Special Multicast 2853c5aff182SThomas Petazzoni * Table entries in the DA-Filter table. 2854c5aff182SThomas Petazzoni * 2) Other Multicast Table for multicast of another type. A CRC-8 value 2855c5aff182SThomas Petazzoni * is used as an index to the Other Multicast Table entries in the 2856c5aff182SThomas Petazzoni * DA-Filter table. 2857c5aff182SThomas Petazzoni */ 2858c5aff182SThomas Petazzoni static int mvneta_mcast_addr_set(struct mvneta_port *pp, unsigned char *p_addr, 2859c5aff182SThomas Petazzoni int queue) 2860c5aff182SThomas Petazzoni { 2861c5aff182SThomas Petazzoni unsigned char crc_result = 0; 2862c5aff182SThomas Petazzoni 2863c5aff182SThomas Petazzoni if (memcmp(p_addr, "\x01\x00\x5e\x00\x00", 5) == 0) { 2864c5aff182SThomas Petazzoni mvneta_set_special_mcast_addr(pp, p_addr[5], queue); 2865c5aff182SThomas Petazzoni return 0; 2866c5aff182SThomas Petazzoni } 2867c5aff182SThomas Petazzoni 2868c5aff182SThomas Petazzoni crc_result = mvneta_addr_crc(p_addr); 2869c5aff182SThomas Petazzoni if (queue == -1) { 2870c5aff182SThomas Petazzoni if (pp->mcast_count[crc_result] == 0) { 2871c5aff182SThomas Petazzoni netdev_info(pp->dev, "No valid Mcast for crc8=0x%02x\n", 2872c5aff182SThomas Petazzoni crc_result); 2873c5aff182SThomas Petazzoni return -EINVAL; 2874c5aff182SThomas Petazzoni } 2875c5aff182SThomas Petazzoni 2876c5aff182SThomas Petazzoni pp->mcast_count[crc_result]--; 2877c5aff182SThomas Petazzoni if (pp->mcast_count[crc_result] != 0) { 2878c5aff182SThomas Petazzoni netdev_info(pp->dev, 2879c5aff182SThomas Petazzoni "After delete there are %d valid Mcast for crc8=0x%02x\n", 2880c5aff182SThomas Petazzoni pp->mcast_count[crc_result], crc_result); 2881c5aff182SThomas Petazzoni return -EINVAL; 2882c5aff182SThomas Petazzoni } 2883c5aff182SThomas Petazzoni } else 2884c5aff182SThomas Petazzoni pp->mcast_count[crc_result]++; 2885c5aff182SThomas Petazzoni 2886c5aff182SThomas Petazzoni mvneta_set_other_mcast_addr(pp, crc_result, queue); 2887c5aff182SThomas Petazzoni 2888c5aff182SThomas Petazzoni return 0; 2889c5aff182SThomas Petazzoni } 2890c5aff182SThomas Petazzoni 2891c5aff182SThomas Petazzoni /* Configure Fitering mode of Ethernet port */ 2892c5aff182SThomas Petazzoni static void mvneta_rx_unicast_promisc_set(struct mvneta_port *pp, 2893c5aff182SThomas Petazzoni int is_promisc) 2894c5aff182SThomas Petazzoni { 2895c5aff182SThomas Petazzoni u32 port_cfg_reg, val; 2896c5aff182SThomas Petazzoni 2897c5aff182SThomas Petazzoni port_cfg_reg = mvreg_read(pp, MVNETA_PORT_CONFIG); 2898c5aff182SThomas Petazzoni 2899c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_TYPE_PRIO); 2900c5aff182SThomas Petazzoni 2901c5aff182SThomas Petazzoni /* Set / Clear UPM bit in port configuration register */ 2902c5aff182SThomas Petazzoni if (is_promisc) { 2903c5aff182SThomas Petazzoni /* Accept all Unicast addresses */ 2904c5aff182SThomas Petazzoni port_cfg_reg |= MVNETA_UNI_PROMISC_MODE; 2905c5aff182SThomas Petazzoni val |= MVNETA_FORCE_UNI; 2906c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_MAC_ADDR_LOW, 0xffff); 2907c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_MAC_ADDR_HIGH, 0xffffffff); 2908c5aff182SThomas Petazzoni } else { 2909c5aff182SThomas Petazzoni /* Reject all Unicast addresses */ 2910c5aff182SThomas Petazzoni port_cfg_reg &= ~MVNETA_UNI_PROMISC_MODE; 2911c5aff182SThomas Petazzoni val &= ~MVNETA_FORCE_UNI; 2912c5aff182SThomas Petazzoni } 2913c5aff182SThomas Petazzoni 2914c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_PORT_CONFIG, port_cfg_reg); 2915c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_TYPE_PRIO, val); 2916c5aff182SThomas Petazzoni } 2917c5aff182SThomas Petazzoni 2918c5aff182SThomas Petazzoni /* register unicast and multicast addresses */ 2919c5aff182SThomas Petazzoni static void mvneta_set_rx_mode(struct net_device *dev) 2920c5aff182SThomas Petazzoni { 2921c5aff182SThomas Petazzoni struct mvneta_port *pp = netdev_priv(dev); 2922c5aff182SThomas Petazzoni struct netdev_hw_addr *ha; 2923c5aff182SThomas Petazzoni 2924c5aff182SThomas Petazzoni if (dev->flags & IFF_PROMISC) { 2925c5aff182SThomas Petazzoni /* Accept all: Multicast + Unicast */ 2926c5aff182SThomas Petazzoni mvneta_rx_unicast_promisc_set(pp, 1); 292790b74c01SGregory CLEMENT mvneta_set_ucast_table(pp, pp->rxq_def); 292890b74c01SGregory CLEMENT mvneta_set_special_mcast_table(pp, pp->rxq_def); 292990b74c01SGregory CLEMENT mvneta_set_other_mcast_table(pp, pp->rxq_def); 2930c5aff182SThomas Petazzoni } else { 2931c5aff182SThomas Petazzoni /* Accept single Unicast */ 2932c5aff182SThomas Petazzoni mvneta_rx_unicast_promisc_set(pp, 0); 2933c5aff182SThomas Petazzoni mvneta_set_ucast_table(pp, -1); 293490b74c01SGregory CLEMENT mvneta_mac_addr_set(pp, dev->dev_addr, pp->rxq_def); 2935c5aff182SThomas Petazzoni 2936c5aff182SThomas Petazzoni if (dev->flags & IFF_ALLMULTI) { 2937c5aff182SThomas Petazzoni /* Accept all multicast */ 293890b74c01SGregory CLEMENT mvneta_set_special_mcast_table(pp, pp->rxq_def); 293990b74c01SGregory CLEMENT mvneta_set_other_mcast_table(pp, pp->rxq_def); 2940c5aff182SThomas Petazzoni } else { 2941c5aff182SThomas Petazzoni /* Accept only initialized multicast */ 2942c5aff182SThomas Petazzoni mvneta_set_special_mcast_table(pp, -1); 2943c5aff182SThomas Petazzoni mvneta_set_other_mcast_table(pp, -1); 2944c5aff182SThomas Petazzoni 2945c5aff182SThomas Petazzoni if (!netdev_mc_empty(dev)) { 2946c5aff182SThomas Petazzoni netdev_for_each_mc_addr(ha, dev) { 2947c5aff182SThomas Petazzoni mvneta_mcast_addr_set(pp, ha->addr, 294890b74c01SGregory CLEMENT pp->rxq_def); 2949c5aff182SThomas Petazzoni } 2950c5aff182SThomas Petazzoni } 2951c5aff182SThomas Petazzoni } 2952c5aff182SThomas Petazzoni } 2953c5aff182SThomas Petazzoni } 2954c5aff182SThomas Petazzoni 2955c5aff182SThomas Petazzoni /* Interrupt handling - the callback for request_irq() */ 2956c5aff182SThomas Petazzoni static irqreturn_t mvneta_isr(int irq, void *dev_id) 2957c5aff182SThomas Petazzoni { 29582636ac3cSMarcin Wojtas struct mvneta_port *pp = (struct mvneta_port *)dev_id; 29592636ac3cSMarcin Wojtas 29602636ac3cSMarcin Wojtas mvreg_write(pp, MVNETA_INTR_NEW_MASK, 0); 29612636ac3cSMarcin Wojtas napi_schedule(&pp->napi); 29622636ac3cSMarcin Wojtas 29632636ac3cSMarcin Wojtas return IRQ_HANDLED; 29642636ac3cSMarcin Wojtas } 29652636ac3cSMarcin Wojtas 29662636ac3cSMarcin Wojtas /* Interrupt handling - the callback for request_percpu_irq() */ 29672636ac3cSMarcin Wojtas static irqreturn_t mvneta_percpu_isr(int irq, void *dev_id) 29682636ac3cSMarcin Wojtas { 296912bb03b4SMaxime Ripard struct mvneta_pcpu_port *port = (struct mvneta_pcpu_port *)dev_id; 2970c5aff182SThomas Petazzoni 297112bb03b4SMaxime Ripard disable_percpu_irq(port->pp->dev->irq); 297212bb03b4SMaxime Ripard napi_schedule(&port->napi); 2973c5aff182SThomas Petazzoni 2974c5aff182SThomas Petazzoni return IRQ_HANDLED; 2975c5aff182SThomas Petazzoni } 2976c5aff182SThomas Petazzoni 2977503f9aa9SRussell King static void mvneta_link_change(struct mvneta_port *pp) 2978898b2970SStas Sergeev { 2979898b2970SStas Sergeev u32 gmac_stat = mvreg_read(pp, MVNETA_GMAC_STATUS); 2980898b2970SStas Sergeev 2981503f9aa9SRussell King phylink_mac_change(pp->phylink, !!(gmac_stat & MVNETA_GMAC_LINK_UP)); 2982898b2970SStas Sergeev } 2983898b2970SStas Sergeev 2984c5aff182SThomas Petazzoni /* NAPI handler 2985c5aff182SThomas Petazzoni * Bits 0 - 7 of the causeRxTx register indicate that are transmitted 2986c5aff182SThomas Petazzoni * packets on the corresponding TXQ (Bit 0 is for TX queue 1). 2987c5aff182SThomas Petazzoni * Bits 8 -15 of the cause Rx Tx register indicate that are received 2988c5aff182SThomas Petazzoni * packets on the corresponding RXQ (Bit 8 is for RX queue 0). 2989c5aff182SThomas Petazzoni * Each CPU has its own causeRxTx register 2990c5aff182SThomas Petazzoni */ 2991c5aff182SThomas Petazzoni static int mvneta_poll(struct napi_struct *napi, int budget) 2992c5aff182SThomas Petazzoni { 2993c5aff182SThomas Petazzoni int rx_done = 0; 2994c5aff182SThomas Petazzoni u32 cause_rx_tx; 29952dcf75e2SGregory CLEMENT int rx_queue; 2996c5aff182SThomas Petazzoni struct mvneta_port *pp = netdev_priv(napi->dev); 299712bb03b4SMaxime Ripard struct mvneta_pcpu_port *port = this_cpu_ptr(pp->ports); 2998c5aff182SThomas Petazzoni 2999c5aff182SThomas Petazzoni if (!netif_running(pp->dev)) { 30002636ac3cSMarcin Wojtas napi_complete(napi); 3001c5aff182SThomas Petazzoni return rx_done; 3002c5aff182SThomas Petazzoni } 3003c5aff182SThomas Petazzoni 3004c5aff182SThomas Petazzoni /* Read cause register */ 3005898b2970SStas Sergeev cause_rx_tx = mvreg_read(pp, MVNETA_INTR_NEW_CAUSE); 3006898b2970SStas Sergeev if (cause_rx_tx & MVNETA_MISCINTR_INTR_MASK) { 3007898b2970SStas Sergeev u32 cause_misc = mvreg_read(pp, MVNETA_INTR_MISC_CAUSE); 3008898b2970SStas Sergeev 3009898b2970SStas Sergeev mvreg_write(pp, MVNETA_INTR_MISC_CAUSE, 0); 3010503f9aa9SRussell King 3011503f9aa9SRussell King if (cause_misc & (MVNETA_CAUSE_PHY_STATUS_CHANGE | 3012856b2cc5SRussell King MVNETA_CAUSE_LINK_CHANGE)) 3013503f9aa9SRussell King mvneta_link_change(pp); 3014898b2970SStas Sergeev } 301571f6d1b3Swilly tarreau 301671f6d1b3Swilly tarreau /* Release Tx descriptors */ 301771f6d1b3Swilly tarreau if (cause_rx_tx & MVNETA_TX_INTR_MASK_ALL) { 30180713a86aSArnaud Ebalard mvneta_tx_done_gbe(pp, (cause_rx_tx & MVNETA_TX_INTR_MASK_ALL)); 301971f6d1b3Swilly tarreau cause_rx_tx &= ~MVNETA_TX_INTR_MASK_ALL; 302071f6d1b3Swilly tarreau } 3021c5aff182SThomas Petazzoni 30226a20c175SThomas Petazzoni /* For the case where the last mvneta_poll did not process all 3023c5aff182SThomas Petazzoni * RX packets 3024c5aff182SThomas Petazzoni */ 30252dcf75e2SGregory CLEMENT rx_queue = fls(((cause_rx_tx >> 8) & 0xff)); 30262dcf75e2SGregory CLEMENT 30272636ac3cSMarcin Wojtas cause_rx_tx |= pp->neta_armada3700 ? pp->cause_rx_tx : 30282636ac3cSMarcin Wojtas port->cause_rx_tx; 30292dcf75e2SGregory CLEMENT 30302dcf75e2SGregory CLEMENT if (rx_queue) { 30312dcf75e2SGregory CLEMENT rx_queue = rx_queue - 1; 3032dc35a10fSMarcin Wojtas if (pp->bm_priv) 30337a86f05fSAndrew Lunn rx_done = mvneta_rx_hwbm(napi, pp, budget, 30347a86f05fSAndrew Lunn &pp->rxqs[rx_queue]); 3035dc35a10fSMarcin Wojtas else 30367a86f05fSAndrew Lunn rx_done = mvneta_rx_swbm(napi, pp, budget, 30377a86f05fSAndrew Lunn &pp->rxqs[rx_queue]); 30382dcf75e2SGregory CLEMENT } 30392dcf75e2SGregory CLEMENT 30406ad20165SEric Dumazet if (rx_done < budget) { 3041c5aff182SThomas Petazzoni cause_rx_tx = 0; 30426ad20165SEric Dumazet napi_complete_done(napi, rx_done); 30432636ac3cSMarcin Wojtas 30442636ac3cSMarcin Wojtas if (pp->neta_armada3700) { 30452636ac3cSMarcin Wojtas unsigned long flags; 30462636ac3cSMarcin Wojtas 30472636ac3cSMarcin Wojtas local_irq_save(flags); 30482636ac3cSMarcin Wojtas mvreg_write(pp, MVNETA_INTR_NEW_MASK, 30492636ac3cSMarcin Wojtas MVNETA_RX_INTR_MASK(rxq_number) | 30502636ac3cSMarcin Wojtas MVNETA_TX_INTR_MASK(txq_number) | 30512636ac3cSMarcin Wojtas MVNETA_MISCINTR_INTR_MASK); 30522636ac3cSMarcin Wojtas local_irq_restore(flags); 30532636ac3cSMarcin Wojtas } else { 305412bb03b4SMaxime Ripard enable_percpu_irq(pp->dev->irq, 0); 3055c5aff182SThomas Petazzoni } 30562636ac3cSMarcin Wojtas } 3057c5aff182SThomas Petazzoni 30582636ac3cSMarcin Wojtas if (pp->neta_armada3700) 30592636ac3cSMarcin Wojtas pp->cause_rx_tx = cause_rx_tx; 30602636ac3cSMarcin Wojtas else 306112bb03b4SMaxime Ripard port->cause_rx_tx = cause_rx_tx; 30622636ac3cSMarcin Wojtas 3063c5aff182SThomas Petazzoni return rx_done; 3064c5aff182SThomas Petazzoni } 3065c5aff182SThomas Petazzoni 3066568a3fa2SLorenzo Bianconi static int mvneta_create_page_pool(struct mvneta_port *pp, 3067568a3fa2SLorenzo Bianconi struct mvneta_rx_queue *rxq, int size) 3068568a3fa2SLorenzo Bianconi { 30690db51da7SLorenzo Bianconi struct bpf_prog *xdp_prog = READ_ONCE(pp->xdp_prog); 3070568a3fa2SLorenzo Bianconi struct page_pool_params pp_params = { 3071568a3fa2SLorenzo Bianconi .order = 0, 307207e13edbSLorenzo Bianconi .flags = PP_FLAG_DMA_MAP | PP_FLAG_DMA_SYNC_DEV, 3073568a3fa2SLorenzo Bianconi .pool_size = size, 3074568a3fa2SLorenzo Bianconi .nid = cpu_to_node(0), 3075568a3fa2SLorenzo Bianconi .dev = pp->dev->dev.parent, 30760db51da7SLorenzo Bianconi .dma_dir = xdp_prog ? DMA_BIDIRECTIONAL : DMA_FROM_DEVICE, 307707e13edbSLorenzo Bianconi .offset = pp->rx_offset_correction, 307807e13edbSLorenzo Bianconi .max_len = MVNETA_MAX_RX_BUF_SIZE, 3079568a3fa2SLorenzo Bianconi }; 3080568a3fa2SLorenzo Bianconi int err; 3081568a3fa2SLorenzo Bianconi 3082568a3fa2SLorenzo Bianconi rxq->page_pool = page_pool_create(&pp_params); 3083568a3fa2SLorenzo Bianconi if (IS_ERR(rxq->page_pool)) { 3084568a3fa2SLorenzo Bianconi err = PTR_ERR(rxq->page_pool); 3085568a3fa2SLorenzo Bianconi rxq->page_pool = NULL; 3086568a3fa2SLorenzo Bianconi return err; 3087568a3fa2SLorenzo Bianconi } 3088568a3fa2SLorenzo Bianconi 3089568a3fa2SLorenzo Bianconi err = xdp_rxq_info_reg(&rxq->xdp_rxq, pp->dev, rxq->id); 3090568a3fa2SLorenzo Bianconi if (err < 0) 3091568a3fa2SLorenzo Bianconi goto err_free_pp; 3092568a3fa2SLorenzo Bianconi 3093568a3fa2SLorenzo Bianconi err = xdp_rxq_info_reg_mem_model(&rxq->xdp_rxq, MEM_TYPE_PAGE_POOL, 3094568a3fa2SLorenzo Bianconi rxq->page_pool); 3095568a3fa2SLorenzo Bianconi if (err) 3096568a3fa2SLorenzo Bianconi goto err_unregister_rxq; 3097568a3fa2SLorenzo Bianconi 3098568a3fa2SLorenzo Bianconi return 0; 3099568a3fa2SLorenzo Bianconi 3100568a3fa2SLorenzo Bianconi err_unregister_rxq: 3101568a3fa2SLorenzo Bianconi xdp_rxq_info_unreg(&rxq->xdp_rxq); 3102568a3fa2SLorenzo Bianconi err_free_pp: 3103568a3fa2SLorenzo Bianconi page_pool_destroy(rxq->page_pool); 3104568a3fa2SLorenzo Bianconi rxq->page_pool = NULL; 3105568a3fa2SLorenzo Bianconi return err; 3106568a3fa2SLorenzo Bianconi } 3107568a3fa2SLorenzo Bianconi 3108c5aff182SThomas Petazzoni /* Handle rxq fill: allocates rxq skbs; called when initializing a port */ 3109c5aff182SThomas Petazzoni static int mvneta_rxq_fill(struct mvneta_port *pp, struct mvneta_rx_queue *rxq, 3110c5aff182SThomas Petazzoni int num) 3111c5aff182SThomas Petazzoni { 3112568a3fa2SLorenzo Bianconi int i, err; 3113568a3fa2SLorenzo Bianconi 3114568a3fa2SLorenzo Bianconi err = mvneta_create_page_pool(pp, rxq, num); 3115568a3fa2SLorenzo Bianconi if (err < 0) 3116568a3fa2SLorenzo Bianconi return err; 3117c5aff182SThomas Petazzoni 3118c5aff182SThomas Petazzoni for (i = 0; i < num; i++) { 3119a1a65ab1Swilly tarreau memset(rxq->descs + i, 0, sizeof(struct mvneta_rx_desc)); 31207e47fd84SGregory CLEMENT if (mvneta_rx_refill(pp, rxq->descs + i, rxq, 31217e47fd84SGregory CLEMENT GFP_KERNEL) != 0) { 31227e47fd84SGregory CLEMENT netdev_err(pp->dev, 31237e47fd84SGregory CLEMENT "%s:rxq %d, %d of %d buffs filled\n", 3124c5aff182SThomas Petazzoni __func__, rxq->id, i, num); 3125c5aff182SThomas Petazzoni break; 3126c5aff182SThomas Petazzoni } 3127c5aff182SThomas Petazzoni } 3128c5aff182SThomas Petazzoni 3129c5aff182SThomas Petazzoni /* Add this number of RX descriptors as non occupied (ready to 31306a20c175SThomas Petazzoni * get packets) 31316a20c175SThomas Petazzoni */ 3132c5aff182SThomas Petazzoni mvneta_rxq_non_occup_desc_add(pp, rxq, i); 3133c5aff182SThomas Petazzoni 3134c5aff182SThomas Petazzoni return i; 3135c5aff182SThomas Petazzoni } 3136c5aff182SThomas Petazzoni 3137c5aff182SThomas Petazzoni /* Free all packets pending transmit from all TXQs and reset TX port */ 3138c5aff182SThomas Petazzoni static void mvneta_tx_reset(struct mvneta_port *pp) 3139c5aff182SThomas Petazzoni { 3140c5aff182SThomas Petazzoni int queue; 3141c5aff182SThomas Petazzoni 31429672850bSEzequiel Garcia /* free the skb's in the tx ring */ 3143c5aff182SThomas Petazzoni for (queue = 0; queue < txq_number; queue++) 3144c5aff182SThomas Petazzoni mvneta_txq_done_force(pp, &pp->txqs[queue]); 3145c5aff182SThomas Petazzoni 3146c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_PORT_TX_RESET, MVNETA_PORT_TX_DMA_RESET); 3147c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_PORT_TX_RESET, 0); 3148c5aff182SThomas Petazzoni } 3149c5aff182SThomas Petazzoni 3150c5aff182SThomas Petazzoni static void mvneta_rx_reset(struct mvneta_port *pp) 3151c5aff182SThomas Petazzoni { 3152c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_PORT_RX_RESET, MVNETA_PORT_RX_DMA_RESET); 3153c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_PORT_RX_RESET, 0); 3154c5aff182SThomas Petazzoni } 3155c5aff182SThomas Petazzoni 3156c5aff182SThomas Petazzoni /* Rx/Tx queue initialization/cleanup methods */ 3157c5aff182SThomas Petazzoni 31584a188a63SJisheng Zhang static int mvneta_rxq_sw_init(struct mvneta_port *pp, 3159c5aff182SThomas Petazzoni struct mvneta_rx_queue *rxq) 3160c5aff182SThomas Petazzoni { 3161c5aff182SThomas Petazzoni rxq->size = pp->rx_ring_size; 3162c5aff182SThomas Petazzoni 3163c5aff182SThomas Petazzoni /* Allocate memory for RX descriptors */ 3164c5aff182SThomas Petazzoni rxq->descs = dma_alloc_coherent(pp->dev->dev.parent, 3165c5aff182SThomas Petazzoni rxq->size * MVNETA_DESC_ALIGNED_SIZE, 3166c5aff182SThomas Petazzoni &rxq->descs_phys, GFP_KERNEL); 3167f95936ccSMarkus Elfring if (!rxq->descs) 3168c5aff182SThomas Petazzoni return -ENOMEM; 3169c5aff182SThomas Petazzoni 3170c5aff182SThomas Petazzoni rxq->last_desc = rxq->size - 1; 3171c5aff182SThomas Petazzoni 31724a188a63SJisheng Zhang return 0; 31734a188a63SJisheng Zhang } 31744a188a63SJisheng Zhang 31754a188a63SJisheng Zhang static void mvneta_rxq_hw_init(struct mvneta_port *pp, 31764a188a63SJisheng Zhang struct mvneta_rx_queue *rxq) 31774a188a63SJisheng Zhang { 3178c5aff182SThomas Petazzoni /* Set Rx descriptors queue starting address */ 3179c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_RXQ_BASE_ADDR_REG(rxq->id), rxq->descs_phys); 3180c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_RXQ_SIZE_REG(rxq->id), rxq->size); 3181c5aff182SThomas Petazzoni 3182c5aff182SThomas Petazzoni /* Set coalescing pkts and time */ 3183c5aff182SThomas Petazzoni mvneta_rx_pkts_coal_set(pp, rxq, rxq->pkts_coal); 3184c5aff182SThomas Petazzoni mvneta_rx_time_coal_set(pp, rxq, rxq->time_coal); 3185c5aff182SThomas Petazzoni 3186dc35a10fSMarcin Wojtas if (!pp->bm_priv) { 3187562e2f46SYelena Krivosheev /* Set Offset */ 3188562e2f46SYelena Krivosheev mvneta_rxq_offset_set(pp, rxq, 0); 3189e735fd55SMarcin Wojtas mvneta_rxq_buf_size_set(pp, rxq, PAGE_SIZE < SZ_64K ? 31908dc9a088SLorenzo Bianconi MVNETA_MAX_RX_BUF_SIZE : 3191e735fd55SMarcin Wojtas MVNETA_RX_BUF_SIZE(pp->pkt_size)); 3192c5aff182SThomas Petazzoni mvneta_rxq_bm_disable(pp, rxq); 3193e9f64999SGregory CLEMENT mvneta_rxq_fill(pp, rxq, rxq->size); 3194dc35a10fSMarcin Wojtas } else { 3195562e2f46SYelena Krivosheev /* Set Offset */ 3196562e2f46SYelena Krivosheev mvneta_rxq_offset_set(pp, rxq, 3197562e2f46SYelena Krivosheev NET_SKB_PAD - pp->rx_offset_correction); 3198562e2f46SYelena Krivosheev 3199dc35a10fSMarcin Wojtas mvneta_rxq_bm_enable(pp, rxq); 3200562e2f46SYelena Krivosheev /* Fill RXQ with buffers from RX pool */ 3201dc35a10fSMarcin Wojtas mvneta_rxq_long_pool_set(pp, rxq); 3202dc35a10fSMarcin Wojtas mvneta_rxq_short_pool_set(pp, rxq); 3203e9f64999SGregory CLEMENT mvneta_rxq_non_occup_desc_add(pp, rxq, rxq->size); 3204dc35a10fSMarcin Wojtas } 32054a188a63SJisheng Zhang } 32064a188a63SJisheng Zhang 32074a188a63SJisheng Zhang /* Create a specified RX queue */ 32084a188a63SJisheng Zhang static int mvneta_rxq_init(struct mvneta_port *pp, 32094a188a63SJisheng Zhang struct mvneta_rx_queue *rxq) 32104a188a63SJisheng Zhang 32114a188a63SJisheng Zhang { 32124a188a63SJisheng Zhang int ret; 32134a188a63SJisheng Zhang 32144a188a63SJisheng Zhang ret = mvneta_rxq_sw_init(pp, rxq); 32154a188a63SJisheng Zhang if (ret < 0) 32164a188a63SJisheng Zhang return ret; 32174a188a63SJisheng Zhang 32184a188a63SJisheng Zhang mvneta_rxq_hw_init(pp, rxq); 3219dc35a10fSMarcin Wojtas 3220c5aff182SThomas Petazzoni return 0; 3221c5aff182SThomas Petazzoni } 3222c5aff182SThomas Petazzoni 3223c5aff182SThomas Petazzoni /* Cleanup Rx queue */ 3224c5aff182SThomas Petazzoni static void mvneta_rxq_deinit(struct mvneta_port *pp, 3225c5aff182SThomas Petazzoni struct mvneta_rx_queue *rxq) 3226c5aff182SThomas Petazzoni { 3227c5aff182SThomas Petazzoni mvneta_rxq_drop_pkts(pp, rxq); 3228c5aff182SThomas Petazzoni 3229562e2f46SYelena Krivosheev if (rxq->skb) 3230562e2f46SYelena Krivosheev dev_kfree_skb_any(rxq->skb); 3231562e2f46SYelena Krivosheev 3232c5aff182SThomas Petazzoni if (rxq->descs) 3233c5aff182SThomas Petazzoni dma_free_coherent(pp->dev->dev.parent, 3234c5aff182SThomas Petazzoni rxq->size * MVNETA_DESC_ALIGNED_SIZE, 3235c5aff182SThomas Petazzoni rxq->descs, 3236c5aff182SThomas Petazzoni rxq->descs_phys); 3237c5aff182SThomas Petazzoni 3238c5aff182SThomas Petazzoni rxq->descs = NULL; 3239c5aff182SThomas Petazzoni rxq->last_desc = 0; 3240c5aff182SThomas Petazzoni rxq->next_desc_to_proc = 0; 3241c5aff182SThomas Petazzoni rxq->descs_phys = 0; 3242562e2f46SYelena Krivosheev rxq->first_to_refill = 0; 3243562e2f46SYelena Krivosheev rxq->refill_num = 0; 3244562e2f46SYelena Krivosheev rxq->skb = NULL; 3245562e2f46SYelena Krivosheev rxq->left_size = 0; 3246c5aff182SThomas Petazzoni } 3247c5aff182SThomas Petazzoni 32484a188a63SJisheng Zhang static int mvneta_txq_sw_init(struct mvneta_port *pp, 3249c5aff182SThomas Petazzoni struct mvneta_tx_queue *txq) 3250c5aff182SThomas Petazzoni { 325150bf8cb6SGregory CLEMENT int cpu; 325250bf8cb6SGregory CLEMENT 3253c5aff182SThomas Petazzoni txq->size = pp->tx_ring_size; 3254c5aff182SThomas Petazzoni 32558eef5f97SEzequiel Garcia /* A queue must always have room for at least one skb. 32568eef5f97SEzequiel Garcia * Therefore, stop the queue when the free entries reaches 32578eef5f97SEzequiel Garcia * the maximum number of descriptors per skb. 32588eef5f97SEzequiel Garcia */ 32598eef5f97SEzequiel Garcia txq->tx_stop_threshold = txq->size - MVNETA_MAX_SKB_DESCS; 32608eef5f97SEzequiel Garcia txq->tx_wake_threshold = txq->tx_stop_threshold / 2; 32618eef5f97SEzequiel Garcia 3262c5aff182SThomas Petazzoni /* Allocate memory for TX descriptors */ 3263c5aff182SThomas Petazzoni txq->descs = dma_alloc_coherent(pp->dev->dev.parent, 3264c5aff182SThomas Petazzoni txq->size * MVNETA_DESC_ALIGNED_SIZE, 3265c5aff182SThomas Petazzoni &txq->descs_phys, GFP_KERNEL); 3266f95936ccSMarkus Elfring if (!txq->descs) 3267c5aff182SThomas Petazzoni return -ENOMEM; 3268c5aff182SThomas Petazzoni 3269c5aff182SThomas Petazzoni txq->last_desc = txq->size - 1; 3270c5aff182SThomas Petazzoni 32719e58c8b4SLorenzo Bianconi txq->buf = kmalloc_array(txq->size, sizeof(*txq->buf), GFP_KERNEL); 32729e58c8b4SLorenzo Bianconi if (!txq->buf) { 3273c5aff182SThomas Petazzoni dma_free_coherent(pp->dev->dev.parent, 3274c5aff182SThomas Petazzoni txq->size * MVNETA_DESC_ALIGNED_SIZE, 3275c5aff182SThomas Petazzoni txq->descs, txq->descs_phys); 3276c5aff182SThomas Petazzoni return -ENOMEM; 3277c5aff182SThomas Petazzoni } 32782adb719dSEzequiel Garcia 32792adb719dSEzequiel Garcia /* Allocate DMA buffers for TSO MAC/IP/TCP headers */ 32802adb719dSEzequiel Garcia txq->tso_hdrs = dma_alloc_coherent(pp->dev->dev.parent, 32812adb719dSEzequiel Garcia txq->size * TSO_HEADER_SIZE, 32822adb719dSEzequiel Garcia &txq->tso_hdrs_phys, GFP_KERNEL); 3283f95936ccSMarkus Elfring if (!txq->tso_hdrs) { 32849e58c8b4SLorenzo Bianconi kfree(txq->buf); 32852adb719dSEzequiel Garcia dma_free_coherent(pp->dev->dev.parent, 32862adb719dSEzequiel Garcia txq->size * MVNETA_DESC_ALIGNED_SIZE, 32872adb719dSEzequiel Garcia txq->descs, txq->descs_phys); 32882adb719dSEzequiel Garcia return -ENOMEM; 32892adb719dSEzequiel Garcia } 3290c5aff182SThomas Petazzoni 329150bf8cb6SGregory CLEMENT /* Setup XPS mapping */ 329250bf8cb6SGregory CLEMENT if (txq_number > 1) 329350bf8cb6SGregory CLEMENT cpu = txq->id % num_present_cpus(); 329450bf8cb6SGregory CLEMENT else 329550bf8cb6SGregory CLEMENT cpu = pp->rxq_def % num_present_cpus(); 329650bf8cb6SGregory CLEMENT cpumask_set_cpu(cpu, &txq->affinity_mask); 329750bf8cb6SGregory CLEMENT netif_set_xps_queue(pp->dev, &txq->affinity_mask, txq->id); 329850bf8cb6SGregory CLEMENT 3299c5aff182SThomas Petazzoni return 0; 3300c5aff182SThomas Petazzoni } 3301c5aff182SThomas Petazzoni 33024a188a63SJisheng Zhang static void mvneta_txq_hw_init(struct mvneta_port *pp, 33034a188a63SJisheng Zhang struct mvneta_tx_queue *txq) 33044a188a63SJisheng Zhang { 33054a188a63SJisheng Zhang /* Set maximum bandwidth for enabled TXQs */ 33064a188a63SJisheng Zhang mvreg_write(pp, MVETH_TXQ_TOKEN_CFG_REG(txq->id), 0x03ffffff); 33074a188a63SJisheng Zhang mvreg_write(pp, MVETH_TXQ_TOKEN_COUNT_REG(txq->id), 0x3fffffff); 33084a188a63SJisheng Zhang 33094a188a63SJisheng Zhang /* Set Tx descriptors queue starting address */ 33104a188a63SJisheng Zhang mvreg_write(pp, MVNETA_TXQ_BASE_ADDR_REG(txq->id), txq->descs_phys); 33114a188a63SJisheng Zhang mvreg_write(pp, MVNETA_TXQ_SIZE_REG(txq->id), txq->size); 33124a188a63SJisheng Zhang 33134a188a63SJisheng Zhang mvneta_tx_done_pkts_coal_set(pp, txq, txq->done_pkts_coal); 33144a188a63SJisheng Zhang } 33154a188a63SJisheng Zhang 33164a188a63SJisheng Zhang /* Create and initialize a tx queue */ 33174a188a63SJisheng Zhang static int mvneta_txq_init(struct mvneta_port *pp, 33184a188a63SJisheng Zhang struct mvneta_tx_queue *txq) 33194a188a63SJisheng Zhang { 33204a188a63SJisheng Zhang int ret; 33214a188a63SJisheng Zhang 33224a188a63SJisheng Zhang ret = mvneta_txq_sw_init(pp, txq); 33234a188a63SJisheng Zhang if (ret < 0) 33244a188a63SJisheng Zhang return ret; 33254a188a63SJisheng Zhang 33264a188a63SJisheng Zhang mvneta_txq_hw_init(pp, txq); 33274a188a63SJisheng Zhang 33284a188a63SJisheng Zhang return 0; 33294a188a63SJisheng Zhang } 33304a188a63SJisheng Zhang 3331c5aff182SThomas Petazzoni /* Free allocated resources when mvneta_txq_init() fails to allocate memory*/ 33324a188a63SJisheng Zhang static void mvneta_txq_sw_deinit(struct mvneta_port *pp, 3333c5aff182SThomas Petazzoni struct mvneta_tx_queue *txq) 3334c5aff182SThomas Petazzoni { 3335a29b6235SMarcin Wojtas struct netdev_queue *nq = netdev_get_tx_queue(pp->dev, txq->id); 3336a29b6235SMarcin Wojtas 33379e58c8b4SLorenzo Bianconi kfree(txq->buf); 3338c5aff182SThomas Petazzoni 33392adb719dSEzequiel Garcia if (txq->tso_hdrs) 33402adb719dSEzequiel Garcia dma_free_coherent(pp->dev->dev.parent, 33412adb719dSEzequiel Garcia txq->size * TSO_HEADER_SIZE, 33422adb719dSEzequiel Garcia txq->tso_hdrs, txq->tso_hdrs_phys); 3343c5aff182SThomas Petazzoni if (txq->descs) 3344c5aff182SThomas Petazzoni dma_free_coherent(pp->dev->dev.parent, 3345c5aff182SThomas Petazzoni txq->size * MVNETA_DESC_ALIGNED_SIZE, 3346c5aff182SThomas Petazzoni txq->descs, txq->descs_phys); 3347c5aff182SThomas Petazzoni 3348a29b6235SMarcin Wojtas netdev_tx_reset_queue(nq); 3349a29b6235SMarcin Wojtas 3350c5aff182SThomas Petazzoni txq->descs = NULL; 3351c5aff182SThomas Petazzoni txq->last_desc = 0; 3352c5aff182SThomas Petazzoni txq->next_desc_to_proc = 0; 3353c5aff182SThomas Petazzoni txq->descs_phys = 0; 33544a188a63SJisheng Zhang } 3355c5aff182SThomas Petazzoni 33564a188a63SJisheng Zhang static void mvneta_txq_hw_deinit(struct mvneta_port *pp, 33574a188a63SJisheng Zhang struct mvneta_tx_queue *txq) 33584a188a63SJisheng Zhang { 3359c5aff182SThomas Petazzoni /* Set minimum bandwidth for disabled TXQs */ 3360c5aff182SThomas Petazzoni mvreg_write(pp, MVETH_TXQ_TOKEN_CFG_REG(txq->id), 0); 3361c5aff182SThomas Petazzoni mvreg_write(pp, MVETH_TXQ_TOKEN_COUNT_REG(txq->id), 0); 3362c5aff182SThomas Petazzoni 3363c5aff182SThomas Petazzoni /* Set Tx descriptors queue starting address and size */ 3364c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_TXQ_BASE_ADDR_REG(txq->id), 0); 3365c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_TXQ_SIZE_REG(txq->id), 0); 3366c5aff182SThomas Petazzoni } 3367c5aff182SThomas Petazzoni 33684a188a63SJisheng Zhang static void mvneta_txq_deinit(struct mvneta_port *pp, 33694a188a63SJisheng Zhang struct mvneta_tx_queue *txq) 33704a188a63SJisheng Zhang { 33714a188a63SJisheng Zhang mvneta_txq_sw_deinit(pp, txq); 33724a188a63SJisheng Zhang mvneta_txq_hw_deinit(pp, txq); 33734a188a63SJisheng Zhang } 33744a188a63SJisheng Zhang 3375c5aff182SThomas Petazzoni /* Cleanup all Tx queues */ 3376c5aff182SThomas Petazzoni static void mvneta_cleanup_txqs(struct mvneta_port *pp) 3377c5aff182SThomas Petazzoni { 3378c5aff182SThomas Petazzoni int queue; 3379c5aff182SThomas Petazzoni 3380c5aff182SThomas Petazzoni for (queue = 0; queue < txq_number; queue++) 3381c5aff182SThomas Petazzoni mvneta_txq_deinit(pp, &pp->txqs[queue]); 3382c5aff182SThomas Petazzoni } 3383c5aff182SThomas Petazzoni 3384c5aff182SThomas Petazzoni /* Cleanup all Rx queues */ 3385c5aff182SThomas Petazzoni static void mvneta_cleanup_rxqs(struct mvneta_port *pp) 3386c5aff182SThomas Petazzoni { 33872dcf75e2SGregory CLEMENT int queue; 33882dcf75e2SGregory CLEMENT 3389ca5902a6SYelena Krivosheev for (queue = 0; queue < rxq_number; queue++) 33902dcf75e2SGregory CLEMENT mvneta_rxq_deinit(pp, &pp->rxqs[queue]); 3391c5aff182SThomas Petazzoni } 3392c5aff182SThomas Petazzoni 3393c5aff182SThomas Petazzoni 3394c5aff182SThomas Petazzoni /* Init all Rx queues */ 3395c5aff182SThomas Petazzoni static int mvneta_setup_rxqs(struct mvneta_port *pp) 3396c5aff182SThomas Petazzoni { 33972dcf75e2SGregory CLEMENT int queue; 33982dcf75e2SGregory CLEMENT 33992dcf75e2SGregory CLEMENT for (queue = 0; queue < rxq_number; queue++) { 34002dcf75e2SGregory CLEMENT int err = mvneta_rxq_init(pp, &pp->rxqs[queue]); 34012dcf75e2SGregory CLEMENT 3402c5aff182SThomas Petazzoni if (err) { 3403c5aff182SThomas Petazzoni netdev_err(pp->dev, "%s: can't create rxq=%d\n", 34042dcf75e2SGregory CLEMENT __func__, queue); 3405c5aff182SThomas Petazzoni mvneta_cleanup_rxqs(pp); 3406c5aff182SThomas Petazzoni return err; 3407c5aff182SThomas Petazzoni } 34082dcf75e2SGregory CLEMENT } 3409c5aff182SThomas Petazzoni 3410c5aff182SThomas Petazzoni return 0; 3411c5aff182SThomas Petazzoni } 3412c5aff182SThomas Petazzoni 3413c5aff182SThomas Petazzoni /* Init all tx queues */ 3414c5aff182SThomas Petazzoni static int mvneta_setup_txqs(struct mvneta_port *pp) 3415c5aff182SThomas Petazzoni { 3416c5aff182SThomas Petazzoni int queue; 3417c5aff182SThomas Petazzoni 3418c5aff182SThomas Petazzoni for (queue = 0; queue < txq_number; queue++) { 3419c5aff182SThomas Petazzoni int err = mvneta_txq_init(pp, &pp->txqs[queue]); 3420c5aff182SThomas Petazzoni if (err) { 3421c5aff182SThomas Petazzoni netdev_err(pp->dev, "%s: can't create txq=%d\n", 3422c5aff182SThomas Petazzoni __func__, queue); 3423c5aff182SThomas Petazzoni mvneta_cleanup_txqs(pp); 3424c5aff182SThomas Petazzoni return err; 3425c5aff182SThomas Petazzoni } 3426c5aff182SThomas Petazzoni } 3427c5aff182SThomas Petazzoni 3428c5aff182SThomas Petazzoni return 0; 3429c5aff182SThomas Petazzoni } 3430c5aff182SThomas Petazzoni 3431031b922bSMarek Behún static int mvneta_comphy_init(struct mvneta_port *pp) 3432031b922bSMarek Behún { 3433031b922bSMarek Behún int ret; 3434031b922bSMarek Behún 3435031b922bSMarek Behún if (!pp->comphy) 3436031b922bSMarek Behún return 0; 3437031b922bSMarek Behún 3438031b922bSMarek Behún ret = phy_set_mode_ext(pp->comphy, PHY_MODE_ETHERNET, 3439031b922bSMarek Behún pp->phy_interface); 3440031b922bSMarek Behún if (ret) 3441031b922bSMarek Behún return ret; 3442031b922bSMarek Behún 3443031b922bSMarek Behún return phy_power_on(pp->comphy); 3444031b922bSMarek Behún } 3445031b922bSMarek Behún 3446c5aff182SThomas Petazzoni static void mvneta_start_dev(struct mvneta_port *pp) 3447c5aff182SThomas Petazzoni { 34486b125d63SGregory CLEMENT int cpu; 344912bb03b4SMaxime Ripard 3450031b922bSMarek Behún WARN_ON(mvneta_comphy_init(pp)); 3451a10c1c81SRussell King 3452c5aff182SThomas Petazzoni mvneta_max_rx_size_set(pp, pp->pkt_size); 3453c5aff182SThomas Petazzoni mvneta_txq_max_tx_size_set(pp, pp->pkt_size); 3454c5aff182SThomas Petazzoni 3455c5aff182SThomas Petazzoni /* start the Rx/Tx activity */ 3456c5aff182SThomas Petazzoni mvneta_port_enable(pp); 3457c5aff182SThomas Petazzoni 34582636ac3cSMarcin Wojtas if (!pp->neta_armada3700) { 3459c5aff182SThomas Petazzoni /* Enable polling on the port */ 3460129219e4SGregory CLEMENT for_each_online_cpu(cpu) { 34612636ac3cSMarcin Wojtas struct mvneta_pcpu_port *port = 34622636ac3cSMarcin Wojtas per_cpu_ptr(pp->ports, cpu); 346312bb03b4SMaxime Ripard 346412bb03b4SMaxime Ripard napi_enable(&port->napi); 346512bb03b4SMaxime Ripard } 34662636ac3cSMarcin Wojtas } else { 34672636ac3cSMarcin Wojtas napi_enable(&pp->napi); 34682636ac3cSMarcin Wojtas } 3469c5aff182SThomas Petazzoni 34702dcf75e2SGregory CLEMENT /* Unmask interrupts. It has to be done from each CPU */ 34716b125d63SGregory CLEMENT on_each_cpu(mvneta_percpu_unmask_interrupt, pp, true); 34726b125d63SGregory CLEMENT 3473898b2970SStas Sergeev mvreg_write(pp, MVNETA_INTR_MISC_MASK, 3474898b2970SStas Sergeev MVNETA_CAUSE_PHY_STATUS_CHANGE | 3475856b2cc5SRussell King MVNETA_CAUSE_LINK_CHANGE); 3476c5aff182SThomas Petazzoni 3477503f9aa9SRussell King phylink_start(pp->phylink); 3478c5aff182SThomas Petazzoni netif_tx_start_all_queues(pp->dev); 3479c5aff182SThomas Petazzoni } 3480c5aff182SThomas Petazzoni 3481c5aff182SThomas Petazzoni static void mvneta_stop_dev(struct mvneta_port *pp) 3482c5aff182SThomas Petazzoni { 348312bb03b4SMaxime Ripard unsigned int cpu; 348412bb03b4SMaxime Ripard 3485503f9aa9SRussell King phylink_stop(pp->phylink); 3486c5aff182SThomas Petazzoni 34872636ac3cSMarcin Wojtas if (!pp->neta_armada3700) { 3488129219e4SGregory CLEMENT for_each_online_cpu(cpu) { 34892636ac3cSMarcin Wojtas struct mvneta_pcpu_port *port = 34902636ac3cSMarcin Wojtas per_cpu_ptr(pp->ports, cpu); 349112bb03b4SMaxime Ripard 349212bb03b4SMaxime Ripard napi_disable(&port->napi); 349312bb03b4SMaxime Ripard } 34942636ac3cSMarcin Wojtas } else { 34952636ac3cSMarcin Wojtas napi_disable(&pp->napi); 34962636ac3cSMarcin Wojtas } 3497c5aff182SThomas Petazzoni 3498c5aff182SThomas Petazzoni netif_carrier_off(pp->dev); 3499c5aff182SThomas Petazzoni 3500c5aff182SThomas Petazzoni mvneta_port_down(pp); 3501c5aff182SThomas Petazzoni netif_tx_stop_all_queues(pp->dev); 3502c5aff182SThomas Petazzoni 3503c5aff182SThomas Petazzoni /* Stop the port activity */ 3504c5aff182SThomas Petazzoni mvneta_port_disable(pp); 3505c5aff182SThomas Petazzoni 3506c5aff182SThomas Petazzoni /* Clear all ethernet port interrupts */ 3507db488c10SGregory CLEMENT on_each_cpu(mvneta_percpu_clear_intr_cause, pp, true); 3508c5aff182SThomas Petazzoni 3509c5aff182SThomas Petazzoni /* Mask all ethernet port interrupts */ 3510db488c10SGregory CLEMENT on_each_cpu(mvneta_percpu_mask_interrupt, pp, true); 3511c5aff182SThomas Petazzoni 3512c5aff182SThomas Petazzoni mvneta_tx_reset(pp); 3513c5aff182SThomas Petazzoni mvneta_rx_reset(pp); 3514a10c1c81SRussell King 3515a10c1c81SRussell King WARN_ON(phy_power_off(pp->comphy)); 3516c5aff182SThomas Petazzoni } 3517c5aff182SThomas Petazzoni 3518db5dd0dbSMarcin Wojtas static void mvneta_percpu_enable(void *arg) 3519db5dd0dbSMarcin Wojtas { 3520db5dd0dbSMarcin Wojtas struct mvneta_port *pp = arg; 3521db5dd0dbSMarcin Wojtas 3522db5dd0dbSMarcin Wojtas enable_percpu_irq(pp->dev->irq, IRQ_TYPE_NONE); 3523db5dd0dbSMarcin Wojtas } 3524db5dd0dbSMarcin Wojtas 3525db5dd0dbSMarcin Wojtas static void mvneta_percpu_disable(void *arg) 3526db5dd0dbSMarcin Wojtas { 3527db5dd0dbSMarcin Wojtas struct mvneta_port *pp = arg; 3528db5dd0dbSMarcin Wojtas 3529db5dd0dbSMarcin Wojtas disable_percpu_irq(pp->dev->irq); 3530db5dd0dbSMarcin Wojtas } 3531db5dd0dbSMarcin Wojtas 3532c5aff182SThomas Petazzoni /* Change the device mtu */ 3533c5aff182SThomas Petazzoni static int mvneta_change_mtu(struct net_device *dev, int mtu) 3534c5aff182SThomas Petazzoni { 3535c5aff182SThomas Petazzoni struct mvneta_port *pp = netdev_priv(dev); 3536c5aff182SThomas Petazzoni int ret; 3537c5aff182SThomas Petazzoni 35385777987eSJarod Wilson if (!IS_ALIGNED(MVNETA_RX_PKT_SIZE(mtu), 8)) { 35395777987eSJarod Wilson netdev_info(dev, "Illegal MTU value %d, rounding to %d\n", 35405777987eSJarod Wilson mtu, ALIGN(MVNETA_RX_PKT_SIZE(mtu), 8)); 35415777987eSJarod Wilson mtu = ALIGN(MVNETA_RX_PKT_SIZE(mtu), 8); 35425777987eSJarod Wilson } 3543c5aff182SThomas Petazzoni 35440db51da7SLorenzo Bianconi if (pp->xdp_prog && mtu > MVNETA_MAX_RX_BUF_SIZE) { 35450db51da7SLorenzo Bianconi netdev_info(dev, "Illegal MTU value %d for XDP mode\n", mtu); 35460db51da7SLorenzo Bianconi return -EINVAL; 35470db51da7SLorenzo Bianconi } 35480db51da7SLorenzo Bianconi 3549c5aff182SThomas Petazzoni dev->mtu = mtu; 3550c5aff182SThomas Petazzoni 3551b65657fcSSimon Guinot if (!netif_running(dev)) { 3552dc35a10fSMarcin Wojtas if (pp->bm_priv) 3553dc35a10fSMarcin Wojtas mvneta_bm_update_mtu(pp, mtu); 3554dc35a10fSMarcin Wojtas 3555b65657fcSSimon Guinot netdev_update_features(dev); 3556c5aff182SThomas Petazzoni return 0; 3557b65657fcSSimon Guinot } 3558c5aff182SThomas Petazzoni 35596a20c175SThomas Petazzoni /* The interface is running, so we have to force a 3560a92dbd96SEzequiel Garcia * reallocation of the queues 3561c5aff182SThomas Petazzoni */ 3562c5aff182SThomas Petazzoni mvneta_stop_dev(pp); 3563db5dd0dbSMarcin Wojtas on_each_cpu(mvneta_percpu_disable, pp, true); 3564c5aff182SThomas Petazzoni 3565c5aff182SThomas Petazzoni mvneta_cleanup_txqs(pp); 3566c5aff182SThomas Petazzoni mvneta_cleanup_rxqs(pp); 3567c5aff182SThomas Petazzoni 3568dc35a10fSMarcin Wojtas if (pp->bm_priv) 3569dc35a10fSMarcin Wojtas mvneta_bm_update_mtu(pp, mtu); 3570dc35a10fSMarcin Wojtas 3571a92dbd96SEzequiel Garcia pp->pkt_size = MVNETA_RX_PKT_SIZE(dev->mtu); 3572c5aff182SThomas Petazzoni 3573c5aff182SThomas Petazzoni ret = mvneta_setup_rxqs(pp); 3574c5aff182SThomas Petazzoni if (ret) { 3575a92dbd96SEzequiel Garcia netdev_err(dev, "unable to setup rxqs after MTU change\n"); 3576c5aff182SThomas Petazzoni return ret; 3577c5aff182SThomas Petazzoni } 3578c5aff182SThomas Petazzoni 3579a92dbd96SEzequiel Garcia ret = mvneta_setup_txqs(pp); 3580a92dbd96SEzequiel Garcia if (ret) { 3581a92dbd96SEzequiel Garcia netdev_err(dev, "unable to setup txqs after MTU change\n"); 3582a92dbd96SEzequiel Garcia return ret; 3583a92dbd96SEzequiel Garcia } 3584c5aff182SThomas Petazzoni 3585db5dd0dbSMarcin Wojtas on_each_cpu(mvneta_percpu_enable, pp, true); 3586c5aff182SThomas Petazzoni mvneta_start_dev(pp); 3587c5aff182SThomas Petazzoni 3588b65657fcSSimon Guinot netdev_update_features(dev); 3589b65657fcSSimon Guinot 3590c5aff182SThomas Petazzoni return 0; 3591c5aff182SThomas Petazzoni } 3592c5aff182SThomas Petazzoni 3593b65657fcSSimon Guinot static netdev_features_t mvneta_fix_features(struct net_device *dev, 3594b65657fcSSimon Guinot netdev_features_t features) 3595b65657fcSSimon Guinot { 3596b65657fcSSimon Guinot struct mvneta_port *pp = netdev_priv(dev); 3597b65657fcSSimon Guinot 3598b65657fcSSimon Guinot if (pp->tx_csum_limit && dev->mtu > pp->tx_csum_limit) { 3599b65657fcSSimon Guinot features &= ~(NETIF_F_IP_CSUM | NETIF_F_TSO); 3600b65657fcSSimon Guinot netdev_info(dev, 3601b65657fcSSimon Guinot "Disable IP checksum for MTU greater than %dB\n", 3602b65657fcSSimon Guinot pp->tx_csum_limit); 3603b65657fcSSimon Guinot } 3604b65657fcSSimon Guinot 3605b65657fcSSimon Guinot return features; 3606b65657fcSSimon Guinot } 3607b65657fcSSimon Guinot 36088cc3e439SThomas Petazzoni /* Get mac address */ 36098cc3e439SThomas Petazzoni static void mvneta_get_mac_addr(struct mvneta_port *pp, unsigned char *addr) 36108cc3e439SThomas Petazzoni { 36118cc3e439SThomas Petazzoni u32 mac_addr_l, mac_addr_h; 36128cc3e439SThomas Petazzoni 36138cc3e439SThomas Petazzoni mac_addr_l = mvreg_read(pp, MVNETA_MAC_ADDR_LOW); 36148cc3e439SThomas Petazzoni mac_addr_h = mvreg_read(pp, MVNETA_MAC_ADDR_HIGH); 36158cc3e439SThomas Petazzoni addr[0] = (mac_addr_h >> 24) & 0xFF; 36168cc3e439SThomas Petazzoni addr[1] = (mac_addr_h >> 16) & 0xFF; 36178cc3e439SThomas Petazzoni addr[2] = (mac_addr_h >> 8) & 0xFF; 36188cc3e439SThomas Petazzoni addr[3] = mac_addr_h & 0xFF; 36198cc3e439SThomas Petazzoni addr[4] = (mac_addr_l >> 8) & 0xFF; 36208cc3e439SThomas Petazzoni addr[5] = mac_addr_l & 0xFF; 36218cc3e439SThomas Petazzoni } 36228cc3e439SThomas Petazzoni 3623c5aff182SThomas Petazzoni /* Handle setting mac address */ 3624c5aff182SThomas Petazzoni static int mvneta_set_mac_addr(struct net_device *dev, void *addr) 3625c5aff182SThomas Petazzoni { 3626c5aff182SThomas Petazzoni struct mvneta_port *pp = netdev_priv(dev); 3627e68de360SEzequiel Garcia struct sockaddr *sockaddr = addr; 3628e68de360SEzequiel Garcia int ret; 3629c5aff182SThomas Petazzoni 3630e68de360SEzequiel Garcia ret = eth_prepare_mac_addr_change(dev, addr); 3631e68de360SEzequiel Garcia if (ret < 0) 3632e68de360SEzequiel Garcia return ret; 3633c5aff182SThomas Petazzoni /* Remove previous address table entry */ 3634c5aff182SThomas Petazzoni mvneta_mac_addr_set(pp, dev->dev_addr, -1); 3635c5aff182SThomas Petazzoni 3636c5aff182SThomas Petazzoni /* Set new addr in hw */ 363790b74c01SGregory CLEMENT mvneta_mac_addr_set(pp, sockaddr->sa_data, pp->rxq_def); 3638c5aff182SThomas Petazzoni 3639e68de360SEzequiel Garcia eth_commit_mac_addr_change(dev, addr); 3640c5aff182SThomas Petazzoni return 0; 3641c5aff182SThomas Petazzoni } 3642c5aff182SThomas Petazzoni 364344cc27e4SIoana Ciornei static void mvneta_validate(struct phylink_config *config, 364444cc27e4SIoana Ciornei unsigned long *supported, 3645503f9aa9SRussell King struct phylink_link_state *state) 3646503f9aa9SRussell King { 364744cc27e4SIoana Ciornei struct net_device *ndev = to_net_dev(config->dev); 3648a10c1c81SRussell King struct mvneta_port *pp = netdev_priv(ndev); 3649503f9aa9SRussell King __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, }; 3650503f9aa9SRussell King 365122f4bf8aSRussell King /* We only support QSGMII, SGMII, 802.3z and RGMII modes */ 3652503f9aa9SRussell King if (state->interface != PHY_INTERFACE_MODE_NA && 3653503f9aa9SRussell King state->interface != PHY_INTERFACE_MODE_QSGMII && 3654503f9aa9SRussell King state->interface != PHY_INTERFACE_MODE_SGMII && 365522f4bf8aSRussell King !phy_interface_mode_is_8023z(state->interface) && 3656503f9aa9SRussell King !phy_interface_mode_is_rgmii(state->interface)) { 3657503f9aa9SRussell King bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS); 3658503f9aa9SRussell King return; 3659503f9aa9SRussell King } 3660503f9aa9SRussell King 3661503f9aa9SRussell King /* Allow all the expected bits */ 3662503f9aa9SRussell King phylink_set(mask, Autoneg); 3663503f9aa9SRussell King phylink_set_port_modes(mask); 3664503f9aa9SRussell King 36654932a918SRussell King /* Asymmetric pause is unsupported */ 36664932a918SRussell King phylink_set(mask, Pause); 3667da58a931SMaxime Chevallier 366883e65df6SMaxime Chevallier /* Half-duplex at speeds higher than 100Mbit is unsupported */ 3669a10c1c81SRussell King if (pp->comphy || state->interface != PHY_INTERFACE_MODE_2500BASEX) { 3670503f9aa9SRussell King phylink_set(mask, 1000baseT_Full); 3671503f9aa9SRussell King phylink_set(mask, 1000baseX_Full); 3672a10c1c81SRussell King } 3673a10c1c81SRussell King if (pp->comphy || state->interface == PHY_INTERFACE_MODE_2500BASEX) { 3674eda3d1b0SMaxime Chevallier phylink_set(mask, 2500baseT_Full); 3675a10c1c81SRussell King phylink_set(mask, 2500baseX_Full); 3676a10c1c81SRussell King } 367722f4bf8aSRussell King 367822f4bf8aSRussell King if (!phy_interface_mode_is_8023z(state->interface)) { 367922f4bf8aSRussell King /* 10M and 100M are only supported in non-802.3z mode */ 3680503f9aa9SRussell King phylink_set(mask, 10baseT_Half); 3681503f9aa9SRussell King phylink_set(mask, 10baseT_Full); 3682503f9aa9SRussell King phylink_set(mask, 100baseT_Half); 3683503f9aa9SRussell King phylink_set(mask, 100baseT_Full); 368422f4bf8aSRussell King } 3685503f9aa9SRussell King 3686503f9aa9SRussell King bitmap_and(supported, supported, mask, 3687503f9aa9SRussell King __ETHTOOL_LINK_MODE_MASK_NBITS); 3688503f9aa9SRussell King bitmap_and(state->advertising, state->advertising, mask, 3689503f9aa9SRussell King __ETHTOOL_LINK_MODE_MASK_NBITS); 3690a10c1c81SRussell King 3691a10c1c81SRussell King /* We can only operate at 2500BaseX or 1000BaseX. If requested 3692a10c1c81SRussell King * to advertise both, only report advertising at 2500BaseX. 3693a10c1c81SRussell King */ 3694a10c1c81SRussell King phylink_helper_basex_speed(state); 3695503f9aa9SRussell King } 3696503f9aa9SRussell King 3697d46b7e4fSRussell King static void mvneta_mac_pcs_get_state(struct phylink_config *config, 3698503f9aa9SRussell King struct phylink_link_state *state) 3699c5aff182SThomas Petazzoni { 370044cc27e4SIoana Ciornei struct net_device *ndev = to_net_dev(config->dev); 3701c5aff182SThomas Petazzoni struct mvneta_port *pp = netdev_priv(ndev); 3702503f9aa9SRussell King u32 gmac_stat; 3703c5aff182SThomas Petazzoni 3704503f9aa9SRussell King gmac_stat = mvreg_read(pp, MVNETA_GMAC_STATUS); 3705503f9aa9SRussell King 3706503f9aa9SRussell King if (gmac_stat & MVNETA_GMAC_SPEED_1000) 3707a10c1c81SRussell King state->speed = 3708a10c1c81SRussell King state->interface == PHY_INTERFACE_MODE_2500BASEX ? 3709a10c1c81SRussell King SPEED_2500 : SPEED_1000; 3710503f9aa9SRussell King else if (gmac_stat & MVNETA_GMAC_SPEED_100) 3711503f9aa9SRussell King state->speed = SPEED_100; 3712503f9aa9SRussell King else 3713503f9aa9SRussell King state->speed = SPEED_10; 3714503f9aa9SRussell King 3715503f9aa9SRussell King state->an_complete = !!(gmac_stat & MVNETA_GMAC_AN_COMPLETE); 3716503f9aa9SRussell King state->link = !!(gmac_stat & MVNETA_GMAC_LINK_UP); 3717503f9aa9SRussell King state->duplex = !!(gmac_stat & MVNETA_GMAC_FULL_DUPLEX); 3718503f9aa9SRussell King 3719503f9aa9SRussell King state->pause = 0; 37204932a918SRussell King if (gmac_stat & MVNETA_GMAC_RX_FLOW_CTRL_ENABLE) 37214932a918SRussell King state->pause |= MLO_PAUSE_RX; 37224932a918SRussell King if (gmac_stat & MVNETA_GMAC_TX_FLOW_CTRL_ENABLE) 37234932a918SRussell King state->pause |= MLO_PAUSE_TX; 3724503f9aa9SRussell King } 3725503f9aa9SRussell King 372644cc27e4SIoana Ciornei static void mvneta_mac_an_restart(struct phylink_config *config) 372722f4bf8aSRussell King { 372844cc27e4SIoana Ciornei struct net_device *ndev = to_net_dev(config->dev); 372922f4bf8aSRussell King struct mvneta_port *pp = netdev_priv(ndev); 373022f4bf8aSRussell King u32 gmac_an = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG); 373122f4bf8aSRussell King 373222f4bf8aSRussell King mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, 373322f4bf8aSRussell King gmac_an | MVNETA_GMAC_INBAND_RESTART_AN); 373422f4bf8aSRussell King mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, 373522f4bf8aSRussell King gmac_an & ~MVNETA_GMAC_INBAND_RESTART_AN); 373622f4bf8aSRussell King } 373722f4bf8aSRussell King 373844cc27e4SIoana Ciornei static void mvneta_mac_config(struct phylink_config *config, unsigned int mode, 3739503f9aa9SRussell King const struct phylink_link_state *state) 3740503f9aa9SRussell King { 374144cc27e4SIoana Ciornei struct net_device *ndev = to_net_dev(config->dev); 3742503f9aa9SRussell King struct mvneta_port *pp = netdev_priv(ndev); 374322f4bf8aSRussell King u32 new_ctrl0, gmac_ctrl0 = mvreg_read(pp, MVNETA_GMAC_CTRL_0); 3744503f9aa9SRussell King u32 new_ctrl2, gmac_ctrl2 = mvreg_read(pp, MVNETA_GMAC_CTRL_2); 3745da58a931SMaxime Chevallier u32 new_ctrl4, gmac_ctrl4 = mvreg_read(pp, MVNETA_GMAC_CTRL_4); 3746503f9aa9SRussell King u32 new_clk, gmac_clk = mvreg_read(pp, MVNETA_GMAC_CLOCK_DIVIDER); 3747503f9aa9SRussell King u32 new_an, gmac_an = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG); 3748503f9aa9SRussell King 374922f4bf8aSRussell King new_ctrl0 = gmac_ctrl0 & ~MVNETA_GMAC0_PORT_1000BASE_X; 375032699954SRussell King new_ctrl2 = gmac_ctrl2 & ~(MVNETA_GMAC2_INBAND_AN_ENABLE | 375132699954SRussell King MVNETA_GMAC2_PORT_RESET); 3752da58a931SMaxime Chevallier new_ctrl4 = gmac_ctrl4 & ~(MVNETA_GMAC4_SHORT_PREAMBLE_ENABLE); 3753503f9aa9SRussell King new_clk = gmac_clk & ~MVNETA_GMAC_1MS_CLOCK_ENABLE; 3754503f9aa9SRussell King new_an = gmac_an & ~(MVNETA_GMAC_INBAND_AN_ENABLE | 3755503f9aa9SRussell King MVNETA_GMAC_INBAND_RESTART_AN | 3756503f9aa9SRussell King MVNETA_GMAC_CONFIG_MII_SPEED | 3757c5aff182SThomas Petazzoni MVNETA_GMAC_CONFIG_GMII_SPEED | 3758503f9aa9SRussell King MVNETA_GMAC_AN_SPEED_EN | 375922f4bf8aSRussell King MVNETA_GMAC_ADVERT_SYM_FLOW_CTRL | 376022f4bf8aSRussell King MVNETA_GMAC_CONFIG_FLOW_CTRL | 3761503f9aa9SRussell King MVNETA_GMAC_AN_FLOW_CTRL_EN | 3762503f9aa9SRussell King MVNETA_GMAC_CONFIG_FULL_DUPLEX | 3763503f9aa9SRussell King MVNETA_GMAC_AN_DUPLEX_EN); 3764c5aff182SThomas Petazzoni 376532699954SRussell King /* Even though it might look weird, when we're configured in 376632699954SRussell King * SGMII or QSGMII mode, the RGMII bit needs to be set. 376732699954SRussell King */ 376832699954SRussell King new_ctrl2 |= MVNETA_GMAC2_PORT_RGMII; 376932699954SRussell King 377032699954SRussell King if (state->interface == PHY_INTERFACE_MODE_QSGMII || 377122f4bf8aSRussell King state->interface == PHY_INTERFACE_MODE_SGMII || 377222f4bf8aSRussell King phy_interface_mode_is_8023z(state->interface)) 377332699954SRussell King new_ctrl2 |= MVNETA_GMAC2_PCS_ENABLE; 377432699954SRussell King 37754932a918SRussell King if (phylink_test(state->advertising, Pause)) 37764932a918SRussell King new_an |= MVNETA_GMAC_ADVERT_SYM_FLOW_CTRL; 37774932a918SRussell King if (state->pause & MLO_PAUSE_TXRX_MASK) 37784932a918SRussell King new_an |= MVNETA_GMAC_CONFIG_FLOW_CTRL; 37794932a918SRussell King 3780503f9aa9SRussell King if (!phylink_autoneg_inband(mode)) { 3781503f9aa9SRussell King /* Phy or fixed speed */ 3782503f9aa9SRussell King if (state->duplex) 3783503f9aa9SRussell King new_an |= MVNETA_GMAC_CONFIG_FULL_DUPLEX; 3784c5aff182SThomas Petazzoni 3785da58a931SMaxime Chevallier if (state->speed == SPEED_1000 || state->speed == SPEED_2500) 3786503f9aa9SRussell King new_an |= MVNETA_GMAC_CONFIG_GMII_SPEED; 3787503f9aa9SRussell King else if (state->speed == SPEED_100) 3788503f9aa9SRussell King new_an |= MVNETA_GMAC_CONFIG_MII_SPEED; 378922f4bf8aSRussell King } else if (state->interface == PHY_INTERFACE_MODE_SGMII) { 3790503f9aa9SRussell King /* SGMII mode receives the state from the PHY */ 3791503f9aa9SRussell King new_ctrl2 |= MVNETA_GMAC2_INBAND_AN_ENABLE; 3792503f9aa9SRussell King new_clk |= MVNETA_GMAC_1MS_CLOCK_ENABLE; 3793503f9aa9SRussell King new_an = (new_an & ~(MVNETA_GMAC_FORCE_LINK_DOWN | 3794503f9aa9SRussell King MVNETA_GMAC_FORCE_LINK_PASS)) | 3795503f9aa9SRussell King MVNETA_GMAC_INBAND_AN_ENABLE | 3796503f9aa9SRussell King MVNETA_GMAC_AN_SPEED_EN | 3797503f9aa9SRussell King MVNETA_GMAC_AN_DUPLEX_EN; 379822f4bf8aSRussell King } else { 379922f4bf8aSRussell King /* 802.3z negotiation - only 1000base-X */ 380022f4bf8aSRussell King new_ctrl0 |= MVNETA_GMAC0_PORT_1000BASE_X; 380122f4bf8aSRussell King new_clk |= MVNETA_GMAC_1MS_CLOCK_ENABLE; 380222f4bf8aSRussell King new_an = (new_an & ~(MVNETA_GMAC_FORCE_LINK_DOWN | 380322f4bf8aSRussell King MVNETA_GMAC_FORCE_LINK_PASS)) | 380422f4bf8aSRussell King MVNETA_GMAC_INBAND_AN_ENABLE | 380522f4bf8aSRussell King MVNETA_GMAC_CONFIG_GMII_SPEED | 380622f4bf8aSRussell King /* The MAC only supports FD mode */ 380722f4bf8aSRussell King MVNETA_GMAC_CONFIG_FULL_DUPLEX; 38084932a918SRussell King 38094932a918SRussell King if (state->pause & MLO_PAUSE_AN && state->an_enabled) 38104932a918SRussell King new_an |= MVNETA_GMAC_AN_FLOW_CTRL_EN; 3811c5aff182SThomas Petazzoni } 3812c5aff182SThomas Petazzoni 3813503f9aa9SRussell King /* Armada 370 documentation says we can only change the port mode 3814503f9aa9SRussell King * and in-band enable when the link is down, so force it down 3815503f9aa9SRussell King * while making these changes. We also do this for GMAC_CTRL2 */ 381622f4bf8aSRussell King if ((new_ctrl0 ^ gmac_ctrl0) & MVNETA_GMAC0_PORT_1000BASE_X || 381722f4bf8aSRussell King (new_ctrl2 ^ gmac_ctrl2) & MVNETA_GMAC2_INBAND_AN_ENABLE || 3818503f9aa9SRussell King (new_an ^ gmac_an) & MVNETA_GMAC_INBAND_AN_ENABLE) { 3819503f9aa9SRussell King mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, 3820503f9aa9SRussell King (gmac_an & ~MVNETA_GMAC_FORCE_LINK_PASS) | 3821503f9aa9SRussell King MVNETA_GMAC_FORCE_LINK_DOWN); 3822503f9aa9SRussell King } 3823503f9aa9SRussell King 3824a10c1c81SRussell King 3825da58a931SMaxime Chevallier /* When at 2.5G, the link partner can send frames with shortened 3826da58a931SMaxime Chevallier * preambles. 3827da58a931SMaxime Chevallier */ 3828da58a931SMaxime Chevallier if (state->speed == SPEED_2500) 3829da58a931SMaxime Chevallier new_ctrl4 |= MVNETA_GMAC4_SHORT_PREAMBLE_ENABLE; 3830da58a931SMaxime Chevallier 3831031b922bSMarek Behún if (pp->comphy && pp->phy_interface != state->interface && 3832a10c1c81SRussell King (state->interface == PHY_INTERFACE_MODE_SGMII || 3833a10c1c81SRussell King state->interface == PHY_INTERFACE_MODE_1000BASEX || 3834031b922bSMarek Behún state->interface == PHY_INTERFACE_MODE_2500BASEX)) { 3835031b922bSMarek Behún pp->phy_interface = state->interface; 3836031b922bSMarek Behún 3837031b922bSMarek Behún WARN_ON(phy_power_off(pp->comphy)); 3838031b922bSMarek Behún WARN_ON(mvneta_comphy_init(pp)); 3839031b922bSMarek Behún } 3840a10c1c81SRussell King 384122f4bf8aSRussell King if (new_ctrl0 != gmac_ctrl0) 384222f4bf8aSRussell King mvreg_write(pp, MVNETA_GMAC_CTRL_0, new_ctrl0); 3843503f9aa9SRussell King if (new_ctrl2 != gmac_ctrl2) 3844503f9aa9SRussell King mvreg_write(pp, MVNETA_GMAC_CTRL_2, new_ctrl2); 3845da58a931SMaxime Chevallier if (new_ctrl4 != gmac_ctrl4) 3846da58a931SMaxime Chevallier mvreg_write(pp, MVNETA_GMAC_CTRL_4, new_ctrl4); 3847503f9aa9SRussell King if (new_clk != gmac_clk) 3848503f9aa9SRussell King mvreg_write(pp, MVNETA_GMAC_CLOCK_DIVIDER, new_clk); 3849503f9aa9SRussell King if (new_an != gmac_an) 3850503f9aa9SRussell King mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, new_an); 385132699954SRussell King 385232699954SRussell King if (gmac_ctrl2 & MVNETA_GMAC2_PORT_RESET) { 385332699954SRussell King while ((mvreg_read(pp, MVNETA_GMAC_CTRL_2) & 385432699954SRussell King MVNETA_GMAC2_PORT_RESET) != 0) 385532699954SRussell King continue; 385632699954SRussell King } 3857503f9aa9SRussell King } 3858503f9aa9SRussell King 38596d81f451SRussell King static void mvneta_set_eee(struct mvneta_port *pp, bool enable) 38606d81f451SRussell King { 38616d81f451SRussell King u32 lpi_ctl1; 38626d81f451SRussell King 38636d81f451SRussell King lpi_ctl1 = mvreg_read(pp, MVNETA_LPI_CTRL_1); 38646d81f451SRussell King if (enable) 38656d81f451SRussell King lpi_ctl1 |= MVNETA_LPI_REQUEST_ENABLE; 38666d81f451SRussell King else 38676d81f451SRussell King lpi_ctl1 &= ~MVNETA_LPI_REQUEST_ENABLE; 38686d81f451SRussell King mvreg_write(pp, MVNETA_LPI_CTRL_1, lpi_ctl1); 38696d81f451SRussell King } 38706d81f451SRussell King 387144cc27e4SIoana Ciornei static void mvneta_mac_link_down(struct phylink_config *config, 387244cc27e4SIoana Ciornei unsigned int mode, phy_interface_t interface) 3873fc548b99SRussell King { 387444cc27e4SIoana Ciornei struct net_device *ndev = to_net_dev(config->dev); 3875fc548b99SRussell King struct mvneta_port *pp = netdev_priv(ndev); 3876fc548b99SRussell King u32 val; 3877fc548b99SRussell King 3878503f9aa9SRussell King mvneta_port_down(pp); 3879503f9aa9SRussell King 3880503f9aa9SRussell King if (!phylink_autoneg_inband(mode)) { 3881fc548b99SRussell King val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG); 3882fc548b99SRussell King val &= ~MVNETA_GMAC_FORCE_LINK_PASS; 3883fc548b99SRussell King val |= MVNETA_GMAC_FORCE_LINK_DOWN; 3884fc548b99SRussell King mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val); 3885fc548b99SRussell King } 38866d81f451SRussell King 38876d81f451SRussell King pp->eee_active = false; 38886d81f451SRussell King mvneta_set_eee(pp, false); 3889fc548b99SRussell King } 3890fc548b99SRussell King 389144cc27e4SIoana Ciornei static void mvneta_mac_link_up(struct phylink_config *config, unsigned int mode, 3892c6ab3008SFlorian Fainelli phy_interface_t interface, 3893503f9aa9SRussell King struct phy_device *phy) 3894fc548b99SRussell King { 389544cc27e4SIoana Ciornei struct net_device *ndev = to_net_dev(config->dev); 3896fc548b99SRussell King struct mvneta_port *pp = netdev_priv(ndev); 3897fc548b99SRussell King u32 val; 3898fc548b99SRussell King 3899503f9aa9SRussell King if (!phylink_autoneg_inband(mode)) { 3900fc548b99SRussell King val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG); 3901fc548b99SRussell King val &= ~MVNETA_GMAC_FORCE_LINK_DOWN; 3902fc548b99SRussell King val |= MVNETA_GMAC_FORCE_LINK_PASS; 3903fc548b99SRussell King mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val); 3904fc548b99SRussell King } 3905fc548b99SRussell King 3906fc548b99SRussell King mvneta_port_up(pp); 39076d81f451SRussell King 39086d81f451SRussell King if (phy && pp->eee_enabled) { 39096d81f451SRussell King pp->eee_active = phy_init_eee(phy, 0) >= 0; 39106d81f451SRussell King mvneta_set_eee(pp, pp->eee_active && pp->tx_lpi_enabled); 39116d81f451SRussell King } 3912fc548b99SRussell King } 3913fc548b99SRussell King 3914503f9aa9SRussell King static const struct phylink_mac_ops mvneta_phylink_ops = { 3915503f9aa9SRussell King .validate = mvneta_validate, 3916d46b7e4fSRussell King .mac_pcs_get_state = mvneta_mac_pcs_get_state, 391722f4bf8aSRussell King .mac_an_restart = mvneta_mac_an_restart, 3918503f9aa9SRussell King .mac_config = mvneta_mac_config, 3919503f9aa9SRussell King .mac_link_down = mvneta_mac_link_down, 3920503f9aa9SRussell King .mac_link_up = mvneta_mac_link_up, 3921503f9aa9SRussell King }; 3922c5aff182SThomas Petazzoni 3923c5aff182SThomas Petazzoni static int mvneta_mdio_probe(struct mvneta_port *pp) 3924c5aff182SThomas Petazzoni { 392582960fffSJisheng Zhang struct ethtool_wolinfo wol = { .cmd = ETHTOOL_GWOL }; 3926503f9aa9SRussell King int err = phylink_of_phy_connect(pp->phylink, pp->dn, 0); 3927c5aff182SThomas Petazzoni 3928503f9aa9SRussell King if (err) 3929503f9aa9SRussell King netdev_err(pp->dev, "could not attach PHY: %d\n", err); 3930c5aff182SThomas Petazzoni 3931503f9aa9SRussell King phylink_ethtool_get_wol(pp->phylink, &wol); 393282960fffSJisheng Zhang device_set_wakeup_capable(&pp->dev->dev, !!wol.supported); 393382960fffSJisheng Zhang 3934503f9aa9SRussell King return err; 3935c5aff182SThomas Petazzoni } 3936c5aff182SThomas Petazzoni 3937c5aff182SThomas Petazzoni static void mvneta_mdio_remove(struct mvneta_port *pp) 3938c5aff182SThomas Petazzoni { 3939503f9aa9SRussell King phylink_disconnect_phy(pp->phylink); 3940c5aff182SThomas Petazzoni } 3941c5aff182SThomas Petazzoni 3942120cfa50SGregory CLEMENT /* Electing a CPU must be done in an atomic way: it should be done 3943120cfa50SGregory CLEMENT * after or before the removal/insertion of a CPU and this function is 3944120cfa50SGregory CLEMENT * not reentrant. 3945120cfa50SGregory CLEMENT */ 3946f8642885SMaxime Ripard static void mvneta_percpu_elect(struct mvneta_port *pp) 3947f8642885SMaxime Ripard { 3948cad5d847SGregory CLEMENT int elected_cpu = 0, max_cpu, cpu, i = 0; 3949f8642885SMaxime Ripard 3950cad5d847SGregory CLEMENT /* Use the cpu associated to the rxq when it is online, in all 3951cad5d847SGregory CLEMENT * the other cases, use the cpu 0 which can't be offline. 3952cad5d847SGregory CLEMENT */ 3953cad5d847SGregory CLEMENT if (cpu_online(pp->rxq_def)) 3954cad5d847SGregory CLEMENT elected_cpu = pp->rxq_def; 3955cad5d847SGregory CLEMENT 39562dcf75e2SGregory CLEMENT max_cpu = num_present_cpus(); 3957f8642885SMaxime Ripard 3958f8642885SMaxime Ripard for_each_online_cpu(cpu) { 39592dcf75e2SGregory CLEMENT int rxq_map = 0, txq_map = 0; 39602dcf75e2SGregory CLEMENT int rxq; 39612dcf75e2SGregory CLEMENT 39622dcf75e2SGregory CLEMENT for (rxq = 0; rxq < rxq_number; rxq++) 39632dcf75e2SGregory CLEMENT if ((rxq % max_cpu) == cpu) 39642dcf75e2SGregory CLEMENT rxq_map |= MVNETA_CPU_RXQ_ACCESS(rxq); 39652dcf75e2SGregory CLEMENT 3966cad5d847SGregory CLEMENT if (cpu == elected_cpu) 396750bf8cb6SGregory CLEMENT /* Map the default receive queue queue to the 396850bf8cb6SGregory CLEMENT * elected CPU 3969f8642885SMaxime Ripard */ 39702dcf75e2SGregory CLEMENT rxq_map |= MVNETA_CPU_RXQ_ACCESS(pp->rxq_def); 397150bf8cb6SGregory CLEMENT 397250bf8cb6SGregory CLEMENT /* We update the TX queue map only if we have one 397350bf8cb6SGregory CLEMENT * queue. In this case we associate the TX queue to 397450bf8cb6SGregory CLEMENT * the CPU bound to the default RX queue 397550bf8cb6SGregory CLEMENT */ 397650bf8cb6SGregory CLEMENT if (txq_number == 1) 3977cad5d847SGregory CLEMENT txq_map = (cpu == elected_cpu) ? 397850bf8cb6SGregory CLEMENT MVNETA_CPU_TXQ_ACCESS(1) : 0; 397950bf8cb6SGregory CLEMENT else 398050bf8cb6SGregory CLEMENT txq_map = mvreg_read(pp, MVNETA_CPU_MAP(cpu)) & 398150bf8cb6SGregory CLEMENT MVNETA_CPU_TXQ_ACCESS_ALL_MASK; 398250bf8cb6SGregory CLEMENT 39832dcf75e2SGregory CLEMENT mvreg_write(pp, MVNETA_CPU_MAP(cpu), rxq_map | txq_map); 39842dcf75e2SGregory CLEMENT 39852dcf75e2SGregory CLEMENT /* Update the interrupt mask on each CPU according the 39862dcf75e2SGregory CLEMENT * new mapping 39872dcf75e2SGregory CLEMENT */ 39882dcf75e2SGregory CLEMENT smp_call_function_single(cpu, mvneta_percpu_unmask_interrupt, 3989f8642885SMaxime Ripard pp, true); 3990f8642885SMaxime Ripard i++; 39912dcf75e2SGregory CLEMENT 3992f8642885SMaxime Ripard } 3993f8642885SMaxime Ripard }; 3994f8642885SMaxime Ripard 399584a3f4dbSSebastian Andrzej Siewior static int mvneta_cpu_online(unsigned int cpu, struct hlist_node *node) 3996f8642885SMaxime Ripard { 399784a3f4dbSSebastian Andrzej Siewior int other_cpu; 399884a3f4dbSSebastian Andrzej Siewior struct mvneta_port *pp = hlist_entry_safe(node, struct mvneta_port, 399984a3f4dbSSebastian Andrzej Siewior node_online); 4000f8642885SMaxime Ripard struct mvneta_pcpu_port *port = per_cpu_ptr(pp->ports, cpu); 4001f8642885SMaxime Ripard 400284a3f4dbSSebastian Andrzej Siewior 4003120cfa50SGregory CLEMENT spin_lock(&pp->lock); 400484a3f4dbSSebastian Andrzej Siewior /* 400584a3f4dbSSebastian Andrzej Siewior * Configuring the driver for a new CPU while the driver is 400684a3f4dbSSebastian Andrzej Siewior * stopping is racy, so just avoid it. 4007120cfa50SGregory CLEMENT */ 4008120cfa50SGregory CLEMENT if (pp->is_stopped) { 4009120cfa50SGregory CLEMENT spin_unlock(&pp->lock); 401084a3f4dbSSebastian Andrzej Siewior return 0; 4011120cfa50SGregory CLEMENT } 4012f8642885SMaxime Ripard netif_tx_stop_all_queues(pp->dev); 4013f8642885SMaxime Ripard 401484a3f4dbSSebastian Andrzej Siewior /* 401584a3f4dbSSebastian Andrzej Siewior * We have to synchronise on tha napi of each CPU except the one 401684a3f4dbSSebastian Andrzej Siewior * just being woken up 4017f8642885SMaxime Ripard */ 4018f8642885SMaxime Ripard for_each_online_cpu(other_cpu) { 4019f8642885SMaxime Ripard if (other_cpu != cpu) { 4020f8642885SMaxime Ripard struct mvneta_pcpu_port *other_port = 4021f8642885SMaxime Ripard per_cpu_ptr(pp->ports, other_cpu); 4022f8642885SMaxime Ripard 4023f8642885SMaxime Ripard napi_synchronize(&other_port->napi); 4024f8642885SMaxime Ripard } 4025f8642885SMaxime Ripard } 4026f8642885SMaxime Ripard 4027f8642885SMaxime Ripard /* Mask all ethernet port interrupts */ 4028db488c10SGregory CLEMENT on_each_cpu(mvneta_percpu_mask_interrupt, pp, true); 4029f8642885SMaxime Ripard napi_enable(&port->napi); 4030f8642885SMaxime Ripard 403184a3f4dbSSebastian Andrzej Siewior /* 403284a3f4dbSSebastian Andrzej Siewior * Enable per-CPU interrupts on the CPU that is 40332dcf75e2SGregory CLEMENT * brought up. 40342dcf75e2SGregory CLEMENT */ 40350e28bf93SAnna-Maria Gleixner mvneta_percpu_enable(pp); 40362dcf75e2SGregory CLEMENT 403784a3f4dbSSebastian Andrzej Siewior /* 403884a3f4dbSSebastian Andrzej Siewior * Enable per-CPU interrupt on the one CPU we care 4039f8642885SMaxime Ripard * about. 4040f8642885SMaxime Ripard */ 4041f8642885SMaxime Ripard mvneta_percpu_elect(pp); 4042f8642885SMaxime Ripard 4043db488c10SGregory CLEMENT /* Unmask all ethernet port interrupts */ 4044db488c10SGregory CLEMENT on_each_cpu(mvneta_percpu_unmask_interrupt, pp, true); 4045f8642885SMaxime Ripard mvreg_write(pp, MVNETA_INTR_MISC_MASK, 4046f8642885SMaxime Ripard MVNETA_CAUSE_PHY_STATUS_CHANGE | 4047856b2cc5SRussell King MVNETA_CAUSE_LINK_CHANGE); 4048f8642885SMaxime Ripard netif_tx_start_all_queues(pp->dev); 4049120cfa50SGregory CLEMENT spin_unlock(&pp->lock); 405084a3f4dbSSebastian Andrzej Siewior return 0; 405184a3f4dbSSebastian Andrzej Siewior } 405284a3f4dbSSebastian Andrzej Siewior 405384a3f4dbSSebastian Andrzej Siewior static int mvneta_cpu_down_prepare(unsigned int cpu, struct hlist_node *node) 405484a3f4dbSSebastian Andrzej Siewior { 405584a3f4dbSSebastian Andrzej Siewior struct mvneta_port *pp = hlist_entry_safe(node, struct mvneta_port, 405684a3f4dbSSebastian Andrzej Siewior node_online); 405784a3f4dbSSebastian Andrzej Siewior struct mvneta_pcpu_port *port = per_cpu_ptr(pp->ports, cpu); 405884a3f4dbSSebastian Andrzej Siewior 405984a3f4dbSSebastian Andrzej Siewior /* 406084a3f4dbSSebastian Andrzej Siewior * Thanks to this lock we are sure that any pending cpu election is 406184a3f4dbSSebastian Andrzej Siewior * done. 40625888511eSGregory CLEMENT */ 40635888511eSGregory CLEMENT spin_lock(&pp->lock); 4064f8642885SMaxime Ripard /* Mask all ethernet port interrupts */ 4065db488c10SGregory CLEMENT on_each_cpu(mvneta_percpu_mask_interrupt, pp, true); 40665888511eSGregory CLEMENT spin_unlock(&pp->lock); 4067f8642885SMaxime Ripard 4068f8642885SMaxime Ripard napi_synchronize(&port->napi); 4069f8642885SMaxime Ripard napi_disable(&port->napi); 407084a3f4dbSSebastian Andrzej Siewior /* Disable per-CPU interrupts on the CPU that is brought down. */ 40710e28bf93SAnna-Maria Gleixner mvneta_percpu_disable(pp); 407284a3f4dbSSebastian Andrzej Siewior return 0; 407384a3f4dbSSebastian Andrzej Siewior } 4074f8642885SMaxime Ripard 407584a3f4dbSSebastian Andrzej Siewior static int mvneta_cpu_dead(unsigned int cpu, struct hlist_node *node) 407684a3f4dbSSebastian Andrzej Siewior { 407784a3f4dbSSebastian Andrzej Siewior struct mvneta_port *pp = hlist_entry_safe(node, struct mvneta_port, 407884a3f4dbSSebastian Andrzej Siewior node_dead); 407984a3f4dbSSebastian Andrzej Siewior 4080f8642885SMaxime Ripard /* Check if a new CPU must be elected now this on is down */ 4081120cfa50SGregory CLEMENT spin_lock(&pp->lock); 4082f8642885SMaxime Ripard mvneta_percpu_elect(pp); 4083120cfa50SGregory CLEMENT spin_unlock(&pp->lock); 4084f8642885SMaxime Ripard /* Unmask all ethernet port interrupts */ 4085db488c10SGregory CLEMENT on_each_cpu(mvneta_percpu_unmask_interrupt, pp, true); 4086f8642885SMaxime Ripard mvreg_write(pp, MVNETA_INTR_MISC_MASK, 4087f8642885SMaxime Ripard MVNETA_CAUSE_PHY_STATUS_CHANGE | 4088856b2cc5SRussell King MVNETA_CAUSE_LINK_CHANGE); 4089f8642885SMaxime Ripard netif_tx_start_all_queues(pp->dev); 409084a3f4dbSSebastian Andrzej Siewior return 0; 4091f8642885SMaxime Ripard } 4092f8642885SMaxime Ripard 4093c5aff182SThomas Petazzoni static int mvneta_open(struct net_device *dev) 4094c5aff182SThomas Petazzoni { 4095c5aff182SThomas Petazzoni struct mvneta_port *pp = netdev_priv(dev); 40966b125d63SGregory CLEMENT int ret; 4097c5aff182SThomas Petazzoni 4098c5aff182SThomas Petazzoni pp->pkt_size = MVNETA_RX_PKT_SIZE(pp->dev->mtu); 4099c5aff182SThomas Petazzoni 4100c5aff182SThomas Petazzoni ret = mvneta_setup_rxqs(pp); 4101c5aff182SThomas Petazzoni if (ret) 4102c5aff182SThomas Petazzoni return ret; 4103c5aff182SThomas Petazzoni 4104c5aff182SThomas Petazzoni ret = mvneta_setup_txqs(pp); 4105c5aff182SThomas Petazzoni if (ret) 4106c5aff182SThomas Petazzoni goto err_cleanup_rxqs; 4107c5aff182SThomas Petazzoni 4108c5aff182SThomas Petazzoni /* Connect to port interrupt line */ 41092636ac3cSMarcin Wojtas if (pp->neta_armada3700) 41102636ac3cSMarcin Wojtas ret = request_irq(pp->dev->irq, mvneta_isr, 0, 41112636ac3cSMarcin Wojtas dev->name, pp); 41122636ac3cSMarcin Wojtas else 41132636ac3cSMarcin Wojtas ret = request_percpu_irq(pp->dev->irq, mvneta_percpu_isr, 41142636ac3cSMarcin Wojtas dev->name, pp->ports); 4115c5aff182SThomas Petazzoni if (ret) { 4116c5aff182SThomas Petazzoni netdev_err(pp->dev, "cannot request irq %d\n", pp->dev->irq); 4117c5aff182SThomas Petazzoni goto err_cleanup_txqs; 4118c5aff182SThomas Petazzoni } 4119c5aff182SThomas Petazzoni 41202636ac3cSMarcin Wojtas if (!pp->neta_armada3700) { 41212dcf75e2SGregory CLEMENT /* Enable per-CPU interrupt on all the CPU to handle our RX 41222dcf75e2SGregory CLEMENT * queue interrupts 41232dcf75e2SGregory CLEMENT */ 41246b125d63SGregory CLEMENT on_each_cpu(mvneta_percpu_enable, pp, true); 41252dcf75e2SGregory CLEMENT 4126120cfa50SGregory CLEMENT pp->is_stopped = false; 4127f8642885SMaxime Ripard /* Register a CPU notifier to handle the case where our CPU 4128f8642885SMaxime Ripard * might be taken offline. 4129f8642885SMaxime Ripard */ 413084a3f4dbSSebastian Andrzej Siewior ret = cpuhp_state_add_instance_nocalls(online_hpstate, 413184a3f4dbSSebastian Andrzej Siewior &pp->node_online); 413284a3f4dbSSebastian Andrzej Siewior if (ret) 413384a3f4dbSSebastian Andrzej Siewior goto err_free_irq; 413484a3f4dbSSebastian Andrzej Siewior 413584a3f4dbSSebastian Andrzej Siewior ret = cpuhp_state_add_instance_nocalls(CPUHP_NET_MVNETA_DEAD, 413684a3f4dbSSebastian Andrzej Siewior &pp->node_dead); 413784a3f4dbSSebastian Andrzej Siewior if (ret) 413884a3f4dbSSebastian Andrzej Siewior goto err_free_online_hp; 41392636ac3cSMarcin Wojtas } 4140f8642885SMaxime Ripard 4141c5aff182SThomas Petazzoni ret = mvneta_mdio_probe(pp); 4142c5aff182SThomas Petazzoni if (ret < 0) { 4143c5aff182SThomas Petazzoni netdev_err(dev, "cannot probe MDIO bus\n"); 414484a3f4dbSSebastian Andrzej Siewior goto err_free_dead_hp; 4145c5aff182SThomas Petazzoni } 4146c5aff182SThomas Petazzoni 4147c5aff182SThomas Petazzoni mvneta_start_dev(pp); 4148c5aff182SThomas Petazzoni 4149c5aff182SThomas Petazzoni return 0; 4150c5aff182SThomas Petazzoni 415184a3f4dbSSebastian Andrzej Siewior err_free_dead_hp: 41522636ac3cSMarcin Wojtas if (!pp->neta_armada3700) 415384a3f4dbSSebastian Andrzej Siewior cpuhp_state_remove_instance_nocalls(CPUHP_NET_MVNETA_DEAD, 415484a3f4dbSSebastian Andrzej Siewior &pp->node_dead); 415584a3f4dbSSebastian Andrzej Siewior err_free_online_hp: 41562636ac3cSMarcin Wojtas if (!pp->neta_armada3700) 41572636ac3cSMarcin Wojtas cpuhp_state_remove_instance_nocalls(online_hpstate, 41582636ac3cSMarcin Wojtas &pp->node_online); 4159c5aff182SThomas Petazzoni err_free_irq: 41602636ac3cSMarcin Wojtas if (pp->neta_armada3700) { 41612636ac3cSMarcin Wojtas free_irq(pp->dev->irq, pp); 41622636ac3cSMarcin Wojtas } else { 41633d8c4530SRussell King - ARM Linux on_each_cpu(mvneta_percpu_disable, pp, true); 416412bb03b4SMaxime Ripard free_percpu_irq(pp->dev->irq, pp->ports); 41652636ac3cSMarcin Wojtas } 4166c5aff182SThomas Petazzoni err_cleanup_txqs: 4167c5aff182SThomas Petazzoni mvneta_cleanup_txqs(pp); 4168c5aff182SThomas Petazzoni err_cleanup_rxqs: 4169c5aff182SThomas Petazzoni mvneta_cleanup_rxqs(pp); 4170c5aff182SThomas Petazzoni return ret; 4171c5aff182SThomas Petazzoni } 4172c5aff182SThomas Petazzoni 4173c5aff182SThomas Petazzoni /* Stop the port, free port interrupt line */ 4174c5aff182SThomas Petazzoni static int mvneta_stop(struct net_device *dev) 4175c5aff182SThomas Petazzoni { 4176c5aff182SThomas Petazzoni struct mvneta_port *pp = netdev_priv(dev); 4177c5aff182SThomas Petazzoni 41782636ac3cSMarcin Wojtas if (!pp->neta_armada3700) { 4179120cfa50SGregory CLEMENT /* Inform that we are stopping so we don't want to setup the 41801c2722a9SGregory CLEMENT * driver for new CPUs in the notifiers. The code of the 41811c2722a9SGregory CLEMENT * notifier for CPU online is protected by the same spinlock, 41821c2722a9SGregory CLEMENT * so when we get the lock, the notifer work is done. 4183120cfa50SGregory CLEMENT */ 4184120cfa50SGregory CLEMENT spin_lock(&pp->lock); 4185120cfa50SGregory CLEMENT pp->is_stopped = true; 41861c2722a9SGregory CLEMENT spin_unlock(&pp->lock); 41871c2722a9SGregory CLEMENT 4188c5aff182SThomas Petazzoni mvneta_stop_dev(pp); 4189c5aff182SThomas Petazzoni mvneta_mdio_remove(pp); 419084a3f4dbSSebastian Andrzej Siewior 4191d26aac2dSDan Carpenter cpuhp_state_remove_instance_nocalls(online_hpstate, 4192d26aac2dSDan Carpenter &pp->node_online); 419384a3f4dbSSebastian Andrzej Siewior cpuhp_state_remove_instance_nocalls(CPUHP_NET_MVNETA_DEAD, 419484a3f4dbSSebastian Andrzej Siewior &pp->node_dead); 4195129219e4SGregory CLEMENT on_each_cpu(mvneta_percpu_disable, pp, true); 419612bb03b4SMaxime Ripard free_percpu_irq(dev->irq, pp->ports); 41972636ac3cSMarcin Wojtas } else { 41982636ac3cSMarcin Wojtas mvneta_stop_dev(pp); 41992636ac3cSMarcin Wojtas mvneta_mdio_remove(pp); 42002636ac3cSMarcin Wojtas free_irq(dev->irq, pp); 42012636ac3cSMarcin Wojtas } 42022636ac3cSMarcin Wojtas 4203c5aff182SThomas Petazzoni mvneta_cleanup_rxqs(pp); 4204c5aff182SThomas Petazzoni mvneta_cleanup_txqs(pp); 4205c5aff182SThomas Petazzoni 4206c5aff182SThomas Petazzoni return 0; 4207c5aff182SThomas Petazzoni } 4208c5aff182SThomas Petazzoni 420915f59456SThomas Petazzoni static int mvneta_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) 421015f59456SThomas Petazzoni { 4211503f9aa9SRussell King struct mvneta_port *pp = netdev_priv(dev); 421215f59456SThomas Petazzoni 4213503f9aa9SRussell King return phylink_mii_ioctl(pp->phylink, ifr, cmd); 421415f59456SThomas Petazzoni } 421515f59456SThomas Petazzoni 42160db51da7SLorenzo Bianconi static int mvneta_xdp_setup(struct net_device *dev, struct bpf_prog *prog, 42170db51da7SLorenzo Bianconi struct netlink_ext_ack *extack) 42180db51da7SLorenzo Bianconi { 42190db51da7SLorenzo Bianconi bool need_update, running = netif_running(dev); 42200db51da7SLorenzo Bianconi struct mvneta_port *pp = netdev_priv(dev); 42210db51da7SLorenzo Bianconi struct bpf_prog *old_prog; 42220db51da7SLorenzo Bianconi 42230db51da7SLorenzo Bianconi if (prog && dev->mtu > MVNETA_MAX_RX_BUF_SIZE) { 42240db51da7SLorenzo Bianconi NL_SET_ERR_MSG_MOD(extack, "Jumbo frames not supported on XDP"); 42250db51da7SLorenzo Bianconi return -EOPNOTSUPP; 42260db51da7SLorenzo Bianconi } 42270db51da7SLorenzo Bianconi 42280db51da7SLorenzo Bianconi need_update = !!pp->xdp_prog != !!prog; 42290db51da7SLorenzo Bianconi if (running && need_update) 42300db51da7SLorenzo Bianconi mvneta_stop(dev); 42310db51da7SLorenzo Bianconi 42320db51da7SLorenzo Bianconi old_prog = xchg(&pp->xdp_prog, prog); 42330db51da7SLorenzo Bianconi if (old_prog) 42340db51da7SLorenzo Bianconi bpf_prog_put(old_prog); 42350db51da7SLorenzo Bianconi 42360db51da7SLorenzo Bianconi if (running && need_update) 42370db51da7SLorenzo Bianconi return mvneta_open(dev); 42380db51da7SLorenzo Bianconi 42390db51da7SLorenzo Bianconi return 0; 42400db51da7SLorenzo Bianconi } 42410db51da7SLorenzo Bianconi 42420db51da7SLorenzo Bianconi static int mvneta_xdp(struct net_device *dev, struct netdev_bpf *xdp) 42430db51da7SLorenzo Bianconi { 42440db51da7SLorenzo Bianconi struct mvneta_port *pp = netdev_priv(dev); 42450db51da7SLorenzo Bianconi 42460db51da7SLorenzo Bianconi switch (xdp->command) { 42470db51da7SLorenzo Bianconi case XDP_SETUP_PROG: 42480db51da7SLorenzo Bianconi return mvneta_xdp_setup(dev, xdp->prog, xdp->extack); 42490db51da7SLorenzo Bianconi case XDP_QUERY_PROG: 42500db51da7SLorenzo Bianconi xdp->prog_id = pp->xdp_prog ? pp->xdp_prog->aux->id : 0; 42510db51da7SLorenzo Bianconi return 0; 42520db51da7SLorenzo Bianconi default: 42530db51da7SLorenzo Bianconi return -EINVAL; 42540db51da7SLorenzo Bianconi } 42550db51da7SLorenzo Bianconi } 42560db51da7SLorenzo Bianconi 4257c5aff182SThomas Petazzoni /* Ethtool methods */ 4258c5aff182SThomas Petazzoni 4259013ad40dSPhilippe Reynes /* Set link ksettings (phy address, speed) for ethtools */ 42602dc0d2b4SBaoyou Xie static int 42612dc0d2b4SBaoyou Xie mvneta_ethtool_set_link_ksettings(struct net_device *ndev, 4262013ad40dSPhilippe Reynes const struct ethtool_link_ksettings *cmd) 4263c5aff182SThomas Petazzoni { 4264013ad40dSPhilippe Reynes struct mvneta_port *pp = netdev_priv(ndev); 4265c5aff182SThomas Petazzoni 4266503f9aa9SRussell King return phylink_ethtool_ksettings_set(pp->phylink, cmd); 42670c0744fcSStas Sergeev } 42680c0744fcSStas Sergeev 4269503f9aa9SRussell King /* Get link ksettings for ethtools */ 4270503f9aa9SRussell King static int 4271503f9aa9SRussell King mvneta_ethtool_get_link_ksettings(struct net_device *ndev, 4272503f9aa9SRussell King struct ethtool_link_ksettings *cmd) 4273503f9aa9SRussell King { 4274503f9aa9SRussell King struct mvneta_port *pp = netdev_priv(ndev); 42750c0744fcSStas Sergeev 4276503f9aa9SRussell King return phylink_ethtool_ksettings_get(pp->phylink, cmd); 42770c0744fcSStas Sergeev } 42780c0744fcSStas Sergeev 4279503f9aa9SRussell King static int mvneta_ethtool_nway_reset(struct net_device *dev) 4280503f9aa9SRussell King { 4281503f9aa9SRussell King struct mvneta_port *pp = netdev_priv(dev); 4282503f9aa9SRussell King 4283503f9aa9SRussell King return phylink_ethtool_nway_reset(pp->phylink); 4284c5aff182SThomas Petazzoni } 4285c5aff182SThomas Petazzoni 4286c5aff182SThomas Petazzoni /* Set interrupt coalescing for ethtools */ 4287c5aff182SThomas Petazzoni static int mvneta_ethtool_set_coalesce(struct net_device *dev, 4288c5aff182SThomas Petazzoni struct ethtool_coalesce *c) 4289c5aff182SThomas Petazzoni { 4290c5aff182SThomas Petazzoni struct mvneta_port *pp = netdev_priv(dev); 4291c5aff182SThomas Petazzoni int queue; 4292c5aff182SThomas Petazzoni 4293c5aff182SThomas Petazzoni for (queue = 0; queue < rxq_number; queue++) { 4294c5aff182SThomas Petazzoni struct mvneta_rx_queue *rxq = &pp->rxqs[queue]; 4295c5aff182SThomas Petazzoni rxq->time_coal = c->rx_coalesce_usecs; 4296c5aff182SThomas Petazzoni rxq->pkts_coal = c->rx_max_coalesced_frames; 4297c5aff182SThomas Petazzoni mvneta_rx_pkts_coal_set(pp, rxq, rxq->pkts_coal); 4298c5aff182SThomas Petazzoni mvneta_rx_time_coal_set(pp, rxq, rxq->time_coal); 4299c5aff182SThomas Petazzoni } 4300c5aff182SThomas Petazzoni 4301c5aff182SThomas Petazzoni for (queue = 0; queue < txq_number; queue++) { 4302c5aff182SThomas Petazzoni struct mvneta_tx_queue *txq = &pp->txqs[queue]; 4303c5aff182SThomas Petazzoni txq->done_pkts_coal = c->tx_max_coalesced_frames; 4304c5aff182SThomas Petazzoni mvneta_tx_done_pkts_coal_set(pp, txq, txq->done_pkts_coal); 4305c5aff182SThomas Petazzoni } 4306c5aff182SThomas Petazzoni 4307c5aff182SThomas Petazzoni return 0; 4308c5aff182SThomas Petazzoni } 4309c5aff182SThomas Petazzoni 4310c5aff182SThomas Petazzoni /* get coalescing for ethtools */ 4311c5aff182SThomas Petazzoni static int mvneta_ethtool_get_coalesce(struct net_device *dev, 4312c5aff182SThomas Petazzoni struct ethtool_coalesce *c) 4313c5aff182SThomas Petazzoni { 4314c5aff182SThomas Petazzoni struct mvneta_port *pp = netdev_priv(dev); 4315c5aff182SThomas Petazzoni 4316c5aff182SThomas Petazzoni c->rx_coalesce_usecs = pp->rxqs[0].time_coal; 4317c5aff182SThomas Petazzoni c->rx_max_coalesced_frames = pp->rxqs[0].pkts_coal; 4318c5aff182SThomas Petazzoni 4319c5aff182SThomas Petazzoni c->tx_max_coalesced_frames = pp->txqs[0].done_pkts_coal; 4320c5aff182SThomas Petazzoni return 0; 4321c5aff182SThomas Petazzoni } 4322c5aff182SThomas Petazzoni 4323c5aff182SThomas Petazzoni 4324c5aff182SThomas Petazzoni static void mvneta_ethtool_get_drvinfo(struct net_device *dev, 4325c5aff182SThomas Petazzoni struct ethtool_drvinfo *drvinfo) 4326c5aff182SThomas Petazzoni { 4327c5aff182SThomas Petazzoni strlcpy(drvinfo->driver, MVNETA_DRIVER_NAME, 4328c5aff182SThomas Petazzoni sizeof(drvinfo->driver)); 4329c5aff182SThomas Petazzoni strlcpy(drvinfo->version, MVNETA_DRIVER_VERSION, 4330c5aff182SThomas Petazzoni sizeof(drvinfo->version)); 4331c5aff182SThomas Petazzoni strlcpy(drvinfo->bus_info, dev_name(&dev->dev), 4332c5aff182SThomas Petazzoni sizeof(drvinfo->bus_info)); 4333c5aff182SThomas Petazzoni } 4334c5aff182SThomas Petazzoni 4335c5aff182SThomas Petazzoni 4336c5aff182SThomas Petazzoni static void mvneta_ethtool_get_ringparam(struct net_device *netdev, 4337c5aff182SThomas Petazzoni struct ethtool_ringparam *ring) 4338c5aff182SThomas Petazzoni { 4339c5aff182SThomas Petazzoni struct mvneta_port *pp = netdev_priv(netdev); 4340c5aff182SThomas Petazzoni 4341c5aff182SThomas Petazzoni ring->rx_max_pending = MVNETA_MAX_RXD; 4342c5aff182SThomas Petazzoni ring->tx_max_pending = MVNETA_MAX_TXD; 4343c5aff182SThomas Petazzoni ring->rx_pending = pp->rx_ring_size; 4344c5aff182SThomas Petazzoni ring->tx_pending = pp->tx_ring_size; 4345c5aff182SThomas Petazzoni } 4346c5aff182SThomas Petazzoni 4347c5aff182SThomas Petazzoni static int mvneta_ethtool_set_ringparam(struct net_device *dev, 4348c5aff182SThomas Petazzoni struct ethtool_ringparam *ring) 4349c5aff182SThomas Petazzoni { 4350c5aff182SThomas Petazzoni struct mvneta_port *pp = netdev_priv(dev); 4351c5aff182SThomas Petazzoni 4352c5aff182SThomas Petazzoni if ((ring->rx_pending == 0) || (ring->tx_pending == 0)) 4353c5aff182SThomas Petazzoni return -EINVAL; 4354c5aff182SThomas Petazzoni pp->rx_ring_size = ring->rx_pending < MVNETA_MAX_RXD ? 4355c5aff182SThomas Petazzoni ring->rx_pending : MVNETA_MAX_RXD; 43568eef5f97SEzequiel Garcia 43578eef5f97SEzequiel Garcia pp->tx_ring_size = clamp_t(u16, ring->tx_pending, 43588eef5f97SEzequiel Garcia MVNETA_MAX_SKB_DESCS * 2, MVNETA_MAX_TXD); 43598eef5f97SEzequiel Garcia if (pp->tx_ring_size != ring->tx_pending) 43608eef5f97SEzequiel Garcia netdev_warn(dev, "TX queue size set to %u (requested %u)\n", 43618eef5f97SEzequiel Garcia pp->tx_ring_size, ring->tx_pending); 4362c5aff182SThomas Petazzoni 4363c5aff182SThomas Petazzoni if (netif_running(dev)) { 4364c5aff182SThomas Petazzoni mvneta_stop(dev); 4365c5aff182SThomas Petazzoni if (mvneta_open(dev)) { 4366c5aff182SThomas Petazzoni netdev_err(dev, 4367c5aff182SThomas Petazzoni "error on opening device after ring param change\n"); 4368c5aff182SThomas Petazzoni return -ENOMEM; 4369c5aff182SThomas Petazzoni } 4370c5aff182SThomas Petazzoni } 4371c5aff182SThomas Petazzoni 4372c5aff182SThomas Petazzoni return 0; 4373c5aff182SThomas Petazzoni } 4374c5aff182SThomas Petazzoni 43754932a918SRussell King static void mvneta_ethtool_get_pauseparam(struct net_device *dev, 43764932a918SRussell King struct ethtool_pauseparam *pause) 43774932a918SRussell King { 43784932a918SRussell King struct mvneta_port *pp = netdev_priv(dev); 43794932a918SRussell King 43804932a918SRussell King phylink_ethtool_get_pauseparam(pp->phylink, pause); 43814932a918SRussell King } 43824932a918SRussell King 43834932a918SRussell King static int mvneta_ethtool_set_pauseparam(struct net_device *dev, 43844932a918SRussell King struct ethtool_pauseparam *pause) 43854932a918SRussell King { 43864932a918SRussell King struct mvneta_port *pp = netdev_priv(dev); 43874932a918SRussell King 43884932a918SRussell King return phylink_ethtool_set_pauseparam(pp->phylink, pause); 43894932a918SRussell King } 43904932a918SRussell King 43919b0cdefaSRussell King static void mvneta_ethtool_get_strings(struct net_device *netdev, u32 sset, 43929b0cdefaSRussell King u8 *data) 43939b0cdefaSRussell King { 43949b0cdefaSRussell King if (sset == ETH_SS_STATS) { 43959b0cdefaSRussell King int i; 43969b0cdefaSRussell King 43979b0cdefaSRussell King for (i = 0; i < ARRAY_SIZE(mvneta_statistics); i++) 43989b0cdefaSRussell King memcpy(data + i * ETH_GSTRING_LEN, 43999b0cdefaSRussell King mvneta_statistics[i].name, ETH_GSTRING_LEN); 44009b0cdefaSRussell King } 44019b0cdefaSRussell King } 44029b0cdefaSRussell King 44039b0cdefaSRussell King static void mvneta_ethtool_update_stats(struct mvneta_port *pp) 44049b0cdefaSRussell King { 44059b0cdefaSRussell King const struct mvneta_statistic *s; 44069b0cdefaSRussell King void __iomem *base = pp->base; 44076d81f451SRussell King u32 high, low; 44086d81f451SRussell King u64 val; 44099b0cdefaSRussell King int i; 44109b0cdefaSRussell King 44119b0cdefaSRussell King for (i = 0, s = mvneta_statistics; 44129b0cdefaSRussell King s < mvneta_statistics + ARRAY_SIZE(mvneta_statistics); 44139b0cdefaSRussell King s++, i++) { 44146d81f451SRussell King val = 0; 44156d81f451SRussell King 44169b0cdefaSRussell King switch (s->type) { 44179b0cdefaSRussell King case T_REG_32: 44189b0cdefaSRussell King val = readl_relaxed(base + s->offset); 44199b0cdefaSRussell King break; 44209b0cdefaSRussell King case T_REG_64: 44219b0cdefaSRussell King /* Docs say to read low 32-bit then high */ 44229b0cdefaSRussell King low = readl_relaxed(base + s->offset); 44239b0cdefaSRussell King high = readl_relaxed(base + s->offset + 4); 44246d81f451SRussell King val = (u64)high << 32 | low; 44256d81f451SRussell King break; 44266d81f451SRussell King case T_SW: 44276d81f451SRussell King switch (s->offset) { 44286d81f451SRussell King case ETHTOOL_STAT_EEE_WAKEUP: 44296d81f451SRussell King val = phylink_get_eee_err(pp->phylink); 44309b0cdefaSRussell King break; 443117a96da6SGregory CLEMENT case ETHTOOL_STAT_SKB_ALLOC_ERR: 443217a96da6SGregory CLEMENT val = pp->rxqs[0].skb_alloc_err; 443317a96da6SGregory CLEMENT break; 443417a96da6SGregory CLEMENT case ETHTOOL_STAT_REFILL_ERR: 443517a96da6SGregory CLEMENT val = pp->rxqs[0].refill_err; 443617a96da6SGregory CLEMENT break; 44379b0cdefaSRussell King } 44386d81f451SRussell King break; 44396d81f451SRussell King } 44406d81f451SRussell King 44416d81f451SRussell King pp->ethtool_stats[i] += val; 44429b0cdefaSRussell King } 44439b0cdefaSRussell King } 44449b0cdefaSRussell King 44459b0cdefaSRussell King static void mvneta_ethtool_get_stats(struct net_device *dev, 44469b0cdefaSRussell King struct ethtool_stats *stats, u64 *data) 44479b0cdefaSRussell King { 44489b0cdefaSRussell King struct mvneta_port *pp = netdev_priv(dev); 44499b0cdefaSRussell King int i; 44509b0cdefaSRussell King 44519b0cdefaSRussell King mvneta_ethtool_update_stats(pp); 44529b0cdefaSRussell King 44539b0cdefaSRussell King for (i = 0; i < ARRAY_SIZE(mvneta_statistics); i++) 44549b0cdefaSRussell King *data++ = pp->ethtool_stats[i]; 44559b0cdefaSRussell King } 44569b0cdefaSRussell King 44579b0cdefaSRussell King static int mvneta_ethtool_get_sset_count(struct net_device *dev, int sset) 44589b0cdefaSRussell King { 44599b0cdefaSRussell King if (sset == ETH_SS_STATS) 44609b0cdefaSRussell King return ARRAY_SIZE(mvneta_statistics); 44619b0cdefaSRussell King return -EOPNOTSUPP; 44629b0cdefaSRussell King } 44639b0cdefaSRussell King 44649a401deaSGregory CLEMENT static u32 mvneta_ethtool_get_rxfh_indir_size(struct net_device *dev) 44659a401deaSGregory CLEMENT { 44669a401deaSGregory CLEMENT return MVNETA_RSS_LU_TABLE_SIZE; 44679a401deaSGregory CLEMENT } 44689a401deaSGregory CLEMENT 44699a401deaSGregory CLEMENT static int mvneta_ethtool_get_rxnfc(struct net_device *dev, 44709a401deaSGregory CLEMENT struct ethtool_rxnfc *info, 44719a401deaSGregory CLEMENT u32 *rules __always_unused) 44729a401deaSGregory CLEMENT { 44739a401deaSGregory CLEMENT switch (info->cmd) { 44749a401deaSGregory CLEMENT case ETHTOOL_GRXRINGS: 44759a401deaSGregory CLEMENT info->data = rxq_number; 44769a401deaSGregory CLEMENT return 0; 44779a401deaSGregory CLEMENT case ETHTOOL_GRXFH: 44789a401deaSGregory CLEMENT return -EOPNOTSUPP; 44799a401deaSGregory CLEMENT default: 44809a401deaSGregory CLEMENT return -EOPNOTSUPP; 44819a401deaSGregory CLEMENT } 44829a401deaSGregory CLEMENT } 44839a401deaSGregory CLEMENT 44849a401deaSGregory CLEMENT static int mvneta_config_rss(struct mvneta_port *pp) 44859a401deaSGregory CLEMENT { 44869a401deaSGregory CLEMENT int cpu; 44879a401deaSGregory CLEMENT u32 val; 44889a401deaSGregory CLEMENT 44899a401deaSGregory CLEMENT netif_tx_stop_all_queues(pp->dev); 44909a401deaSGregory CLEMENT 44916b125d63SGregory CLEMENT on_each_cpu(mvneta_percpu_mask_interrupt, pp, true); 44929a401deaSGregory CLEMENT 44930f5c6c30SJisheng Zhang if (!pp->neta_armada3700) { 44949a401deaSGregory CLEMENT /* We have to synchronise on the napi of each CPU */ 44959a401deaSGregory CLEMENT for_each_online_cpu(cpu) { 44969a401deaSGregory CLEMENT struct mvneta_pcpu_port *pcpu_port = 44979a401deaSGregory CLEMENT per_cpu_ptr(pp->ports, cpu); 44989a401deaSGregory CLEMENT 44999a401deaSGregory CLEMENT napi_synchronize(&pcpu_port->napi); 45009a401deaSGregory CLEMENT napi_disable(&pcpu_port->napi); 45019a401deaSGregory CLEMENT } 45020f5c6c30SJisheng Zhang } else { 45030f5c6c30SJisheng Zhang napi_synchronize(&pp->napi); 45040f5c6c30SJisheng Zhang napi_disable(&pp->napi); 45050f5c6c30SJisheng Zhang } 45069a401deaSGregory CLEMENT 45079a401deaSGregory CLEMENT pp->rxq_def = pp->indir[0]; 45089a401deaSGregory CLEMENT 45099a401deaSGregory CLEMENT /* Update unicast mapping */ 45109a401deaSGregory CLEMENT mvneta_set_rx_mode(pp->dev); 45119a401deaSGregory CLEMENT 45129a401deaSGregory CLEMENT /* Update val of portCfg register accordingly with all RxQueue types */ 45139a401deaSGregory CLEMENT val = MVNETA_PORT_CONFIG_DEFL_VALUE(pp->rxq_def); 45149a401deaSGregory CLEMENT mvreg_write(pp, MVNETA_PORT_CONFIG, val); 45159a401deaSGregory CLEMENT 45169a401deaSGregory CLEMENT /* Update the elected CPU matching the new rxq_def */ 4517120cfa50SGregory CLEMENT spin_lock(&pp->lock); 45189a401deaSGregory CLEMENT mvneta_percpu_elect(pp); 4519120cfa50SGregory CLEMENT spin_unlock(&pp->lock); 45209a401deaSGregory CLEMENT 45210f5c6c30SJisheng Zhang if (!pp->neta_armada3700) { 45229a401deaSGregory CLEMENT /* We have to synchronise on the napi of each CPU */ 45239a401deaSGregory CLEMENT for_each_online_cpu(cpu) { 45249a401deaSGregory CLEMENT struct mvneta_pcpu_port *pcpu_port = 45259a401deaSGregory CLEMENT per_cpu_ptr(pp->ports, cpu); 45269a401deaSGregory CLEMENT 45279a401deaSGregory CLEMENT napi_enable(&pcpu_port->napi); 45289a401deaSGregory CLEMENT } 45290f5c6c30SJisheng Zhang } else { 45300f5c6c30SJisheng Zhang napi_enable(&pp->napi); 45310f5c6c30SJisheng Zhang } 45329a401deaSGregory CLEMENT 45339a401deaSGregory CLEMENT netif_tx_start_all_queues(pp->dev); 45349a401deaSGregory CLEMENT 45359a401deaSGregory CLEMENT return 0; 45369a401deaSGregory CLEMENT } 45379a401deaSGregory CLEMENT 45389a401deaSGregory CLEMENT static int mvneta_ethtool_set_rxfh(struct net_device *dev, const u32 *indir, 45399a401deaSGregory CLEMENT const u8 *key, const u8 hfunc) 45409a401deaSGregory CLEMENT { 45419a401deaSGregory CLEMENT struct mvneta_port *pp = netdev_priv(dev); 45422636ac3cSMarcin Wojtas 45432636ac3cSMarcin Wojtas /* Current code for Armada 3700 doesn't support RSS features yet */ 45442636ac3cSMarcin Wojtas if (pp->neta_armada3700) 45452636ac3cSMarcin Wojtas return -EOPNOTSUPP; 45462636ac3cSMarcin Wojtas 45479a401deaSGregory CLEMENT /* We require at least one supported parameter to be changed 45489a401deaSGregory CLEMENT * and no change in any of the unsupported parameters 45499a401deaSGregory CLEMENT */ 45509a401deaSGregory CLEMENT if (key || 45519a401deaSGregory CLEMENT (hfunc != ETH_RSS_HASH_NO_CHANGE && hfunc != ETH_RSS_HASH_TOP)) 45529a401deaSGregory CLEMENT return -EOPNOTSUPP; 45539a401deaSGregory CLEMENT 45549a401deaSGregory CLEMENT if (!indir) 45559a401deaSGregory CLEMENT return 0; 45569a401deaSGregory CLEMENT 45579a401deaSGregory CLEMENT memcpy(pp->indir, indir, MVNETA_RSS_LU_TABLE_SIZE); 45589a401deaSGregory CLEMENT 45599a401deaSGregory CLEMENT return mvneta_config_rss(pp); 45609a401deaSGregory CLEMENT } 45619a401deaSGregory CLEMENT 45629a401deaSGregory CLEMENT static int mvneta_ethtool_get_rxfh(struct net_device *dev, u32 *indir, u8 *key, 45639a401deaSGregory CLEMENT u8 *hfunc) 45649a401deaSGregory CLEMENT { 45659a401deaSGregory CLEMENT struct mvneta_port *pp = netdev_priv(dev); 45669a401deaSGregory CLEMENT 45672636ac3cSMarcin Wojtas /* Current code for Armada 3700 doesn't support RSS features yet */ 45682636ac3cSMarcin Wojtas if (pp->neta_armada3700) 45692636ac3cSMarcin Wojtas return -EOPNOTSUPP; 45702636ac3cSMarcin Wojtas 45719a401deaSGregory CLEMENT if (hfunc) 45729a401deaSGregory CLEMENT *hfunc = ETH_RSS_HASH_TOP; 45739a401deaSGregory CLEMENT 45749a401deaSGregory CLEMENT if (!indir) 45759a401deaSGregory CLEMENT return 0; 45769a401deaSGregory CLEMENT 45779a401deaSGregory CLEMENT memcpy(indir, pp->indir, MVNETA_RSS_LU_TABLE_SIZE); 45789a401deaSGregory CLEMENT 45799a401deaSGregory CLEMENT return 0; 45809a401deaSGregory CLEMENT } 45819a401deaSGregory CLEMENT 4582b60a00f9SJingju Hou static void mvneta_ethtool_get_wol(struct net_device *dev, 4583b60a00f9SJingju Hou struct ethtool_wolinfo *wol) 4584b60a00f9SJingju Hou { 4585503f9aa9SRussell King struct mvneta_port *pp = netdev_priv(dev); 4586b60a00f9SJingju Hou 4587503f9aa9SRussell King phylink_ethtool_get_wol(pp->phylink, wol); 4588b60a00f9SJingju Hou } 4589b60a00f9SJingju Hou 4590b60a00f9SJingju Hou static int mvneta_ethtool_set_wol(struct net_device *dev, 4591b60a00f9SJingju Hou struct ethtool_wolinfo *wol) 4592b60a00f9SJingju Hou { 4593503f9aa9SRussell King struct mvneta_port *pp = netdev_priv(dev); 459482960fffSJisheng Zhang int ret; 459582960fffSJisheng Zhang 4596503f9aa9SRussell King ret = phylink_ethtool_set_wol(pp->phylink, wol); 459782960fffSJisheng Zhang if (!ret) 459882960fffSJisheng Zhang device_set_wakeup_enable(&dev->dev, !!wol->wolopts); 459982960fffSJisheng Zhang 460082960fffSJisheng Zhang return ret; 4601b60a00f9SJingju Hou } 4602b60a00f9SJingju Hou 46036d81f451SRussell King static int mvneta_ethtool_get_eee(struct net_device *dev, 46046d81f451SRussell King struct ethtool_eee *eee) 46056d81f451SRussell King { 46066d81f451SRussell King struct mvneta_port *pp = netdev_priv(dev); 46076d81f451SRussell King u32 lpi_ctl0; 46086d81f451SRussell King 46096d81f451SRussell King lpi_ctl0 = mvreg_read(pp, MVNETA_LPI_CTRL_0); 46106d81f451SRussell King 46116d81f451SRussell King eee->eee_enabled = pp->eee_enabled; 46126d81f451SRussell King eee->eee_active = pp->eee_active; 46136d81f451SRussell King eee->tx_lpi_enabled = pp->tx_lpi_enabled; 46146d81f451SRussell King eee->tx_lpi_timer = (lpi_ctl0) >> 8; // * scale; 46156d81f451SRussell King 46166d81f451SRussell King return phylink_ethtool_get_eee(pp->phylink, eee); 46176d81f451SRussell King } 46186d81f451SRussell King 46196d81f451SRussell King static int mvneta_ethtool_set_eee(struct net_device *dev, 46206d81f451SRussell King struct ethtool_eee *eee) 46216d81f451SRussell King { 46226d81f451SRussell King struct mvneta_port *pp = netdev_priv(dev); 46236d81f451SRussell King u32 lpi_ctl0; 46246d81f451SRussell King 46256d81f451SRussell King /* The Armada 37x documents do not give limits for this other than 46266d81f451SRussell King * it being an 8-bit register. */ 4627e4a3e9ffSYueHaibing if (eee->tx_lpi_enabled && eee->tx_lpi_timer > 255) 46286d81f451SRussell King return -EINVAL; 46296d81f451SRussell King 46306d81f451SRussell King lpi_ctl0 = mvreg_read(pp, MVNETA_LPI_CTRL_0); 46316d81f451SRussell King lpi_ctl0 &= ~(0xff << 8); 46326d81f451SRussell King lpi_ctl0 |= eee->tx_lpi_timer << 8; 46336d81f451SRussell King mvreg_write(pp, MVNETA_LPI_CTRL_0, lpi_ctl0); 46346d81f451SRussell King 46356d81f451SRussell King pp->eee_enabled = eee->eee_enabled; 46366d81f451SRussell King pp->tx_lpi_enabled = eee->tx_lpi_enabled; 46376d81f451SRussell King 46386d81f451SRussell King mvneta_set_eee(pp, eee->tx_lpi_enabled && eee->eee_enabled); 46396d81f451SRussell King 46406d81f451SRussell King return phylink_ethtool_set_eee(pp->phylink, eee); 46416d81f451SRussell King } 46426d81f451SRussell King 4643c5aff182SThomas Petazzoni static const struct net_device_ops mvneta_netdev_ops = { 4644c5aff182SThomas Petazzoni .ndo_open = mvneta_open, 4645c5aff182SThomas Petazzoni .ndo_stop = mvneta_stop, 4646c5aff182SThomas Petazzoni .ndo_start_xmit = mvneta_tx, 4647c5aff182SThomas Petazzoni .ndo_set_rx_mode = mvneta_set_rx_mode, 4648c5aff182SThomas Petazzoni .ndo_set_mac_address = mvneta_set_mac_addr, 4649c5aff182SThomas Petazzoni .ndo_change_mtu = mvneta_change_mtu, 4650b65657fcSSimon Guinot .ndo_fix_features = mvneta_fix_features, 4651c5aff182SThomas Petazzoni .ndo_get_stats64 = mvneta_get_stats64, 465215f59456SThomas Petazzoni .ndo_do_ioctl = mvneta_ioctl, 46530db51da7SLorenzo Bianconi .ndo_bpf = mvneta_xdp, 4654b0a43db9SLorenzo Bianconi .ndo_xdp_xmit = mvneta_xdp_xmit, 4655c5aff182SThomas Petazzoni }; 4656c5aff182SThomas Petazzoni 46574581be42SJisheng Zhang static const struct ethtool_ops mvneta_eth_tool_ops = { 4658503f9aa9SRussell King .nway_reset = mvneta_ethtool_nway_reset, 4659c5aff182SThomas Petazzoni .get_link = ethtool_op_get_link, 4660c5aff182SThomas Petazzoni .set_coalesce = mvneta_ethtool_set_coalesce, 4661c5aff182SThomas Petazzoni .get_coalesce = mvneta_ethtool_get_coalesce, 4662c5aff182SThomas Petazzoni .get_drvinfo = mvneta_ethtool_get_drvinfo, 4663c5aff182SThomas Petazzoni .get_ringparam = mvneta_ethtool_get_ringparam, 4664c5aff182SThomas Petazzoni .set_ringparam = mvneta_ethtool_set_ringparam, 46654932a918SRussell King .get_pauseparam = mvneta_ethtool_get_pauseparam, 46664932a918SRussell King .set_pauseparam = mvneta_ethtool_set_pauseparam, 46679b0cdefaSRussell King .get_strings = mvneta_ethtool_get_strings, 46689b0cdefaSRussell King .get_ethtool_stats = mvneta_ethtool_get_stats, 46699b0cdefaSRussell King .get_sset_count = mvneta_ethtool_get_sset_count, 46709a401deaSGregory CLEMENT .get_rxfh_indir_size = mvneta_ethtool_get_rxfh_indir_size, 46719a401deaSGregory CLEMENT .get_rxnfc = mvneta_ethtool_get_rxnfc, 46729a401deaSGregory CLEMENT .get_rxfh = mvneta_ethtool_get_rxfh, 46739a401deaSGregory CLEMENT .set_rxfh = mvneta_ethtool_set_rxfh, 4674503f9aa9SRussell King .get_link_ksettings = mvneta_ethtool_get_link_ksettings, 4675013ad40dSPhilippe Reynes .set_link_ksettings = mvneta_ethtool_set_link_ksettings, 4676b60a00f9SJingju Hou .get_wol = mvneta_ethtool_get_wol, 4677b60a00f9SJingju Hou .set_wol = mvneta_ethtool_set_wol, 46786d81f451SRussell King .get_eee = mvneta_ethtool_get_eee, 46796d81f451SRussell King .set_eee = mvneta_ethtool_set_eee, 4680c5aff182SThomas Petazzoni }; 4681c5aff182SThomas Petazzoni 4682c5aff182SThomas Petazzoni /* Initialize hw */ 46839672850bSEzequiel Garcia static int mvneta_init(struct device *dev, struct mvneta_port *pp) 4684c5aff182SThomas Petazzoni { 4685c5aff182SThomas Petazzoni int queue; 4686c5aff182SThomas Petazzoni 4687c5aff182SThomas Petazzoni /* Disable port */ 4688c5aff182SThomas Petazzoni mvneta_port_disable(pp); 4689c5aff182SThomas Petazzoni 4690c5aff182SThomas Petazzoni /* Set port default values */ 4691c5aff182SThomas Petazzoni mvneta_defaults_set(pp); 4692c5aff182SThomas Petazzoni 46935d6312edSMarkus Elfring pp->txqs = devm_kcalloc(dev, txq_number, sizeof(*pp->txqs), GFP_KERNEL); 4694c5aff182SThomas Petazzoni if (!pp->txqs) 4695c5aff182SThomas Petazzoni return -ENOMEM; 4696c5aff182SThomas Petazzoni 4697c5aff182SThomas Petazzoni /* Initialize TX descriptor rings */ 4698c5aff182SThomas Petazzoni for (queue = 0; queue < txq_number; queue++) { 4699c5aff182SThomas Petazzoni struct mvneta_tx_queue *txq = &pp->txqs[queue]; 4700c5aff182SThomas Petazzoni txq->id = queue; 4701c5aff182SThomas Petazzoni txq->size = pp->tx_ring_size; 4702c5aff182SThomas Petazzoni txq->done_pkts_coal = MVNETA_TXDONE_COAL_PKTS; 4703c5aff182SThomas Petazzoni } 4704c5aff182SThomas Petazzoni 47055d6312edSMarkus Elfring pp->rxqs = devm_kcalloc(dev, rxq_number, sizeof(*pp->rxqs), GFP_KERNEL); 47069672850bSEzequiel Garcia if (!pp->rxqs) 4707c5aff182SThomas Petazzoni return -ENOMEM; 4708c5aff182SThomas Petazzoni 4709c5aff182SThomas Petazzoni /* Create Rx descriptor rings */ 4710c5aff182SThomas Petazzoni for (queue = 0; queue < rxq_number; queue++) { 4711c5aff182SThomas Petazzoni struct mvneta_rx_queue *rxq = &pp->rxqs[queue]; 4712c5aff182SThomas Petazzoni rxq->id = queue; 4713c5aff182SThomas Petazzoni rxq->size = pp->rx_ring_size; 4714c5aff182SThomas Petazzoni rxq->pkts_coal = MVNETA_RX_COAL_PKTS; 4715c5aff182SThomas Petazzoni rxq->time_coal = MVNETA_RX_COAL_USEC; 471629110630SMarkus Elfring rxq->buf_virt_addr 471729110630SMarkus Elfring = devm_kmalloc_array(pp->dev->dev.parent, 471829110630SMarkus Elfring rxq->size, 471929110630SMarkus Elfring sizeof(*rxq->buf_virt_addr), 4720f88bee1cSGregory CLEMENT GFP_KERNEL); 4721f88bee1cSGregory CLEMENT if (!rxq->buf_virt_addr) 4722f88bee1cSGregory CLEMENT return -ENOMEM; 4723c5aff182SThomas Petazzoni } 4724c5aff182SThomas Petazzoni 4725c5aff182SThomas Petazzoni return 0; 4726c5aff182SThomas Petazzoni } 4727c5aff182SThomas Petazzoni 4728c5aff182SThomas Petazzoni /* platform glue : initialize decoding windows */ 472903ce758eSGreg KH static void mvneta_conf_mbus_windows(struct mvneta_port *pp, 4730c5aff182SThomas Petazzoni const struct mbus_dram_target_info *dram) 4731c5aff182SThomas Petazzoni { 4732c5aff182SThomas Petazzoni u32 win_enable; 4733c5aff182SThomas Petazzoni u32 win_protect; 4734c5aff182SThomas Petazzoni int i; 4735c5aff182SThomas Petazzoni 4736c5aff182SThomas Petazzoni for (i = 0; i < 6; i++) { 4737c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_WIN_BASE(i), 0); 4738c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_WIN_SIZE(i), 0); 4739c5aff182SThomas Petazzoni 4740c5aff182SThomas Petazzoni if (i < 4) 4741c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_WIN_REMAP(i), 0); 4742c5aff182SThomas Petazzoni } 4743c5aff182SThomas Petazzoni 4744c5aff182SThomas Petazzoni win_enable = 0x3f; 4745c5aff182SThomas Petazzoni win_protect = 0; 4746c5aff182SThomas Petazzoni 47472636ac3cSMarcin Wojtas if (dram) { 4748c5aff182SThomas Petazzoni for (i = 0; i < dram->num_cs; i++) { 4749c5aff182SThomas Petazzoni const struct mbus_dram_window *cs = dram->cs + i; 47502636ac3cSMarcin Wojtas 47512636ac3cSMarcin Wojtas mvreg_write(pp, MVNETA_WIN_BASE(i), 47522636ac3cSMarcin Wojtas (cs->base & 0xffff0000) | 47532636ac3cSMarcin Wojtas (cs->mbus_attr << 8) | 47542636ac3cSMarcin Wojtas dram->mbus_dram_target_id); 4755c5aff182SThomas Petazzoni 4756c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_WIN_SIZE(i), 4757c5aff182SThomas Petazzoni (cs->size - 1) & 0xffff0000); 4758c5aff182SThomas Petazzoni 4759c5aff182SThomas Petazzoni win_enable &= ~(1 << i); 4760c5aff182SThomas Petazzoni win_protect |= 3 << (2 * i); 4761c5aff182SThomas Petazzoni } 47622636ac3cSMarcin Wojtas } else { 47632636ac3cSMarcin Wojtas /* For Armada3700 open default 4GB Mbus window, leaving 47642636ac3cSMarcin Wojtas * arbitration of target/attribute to a different layer 47652636ac3cSMarcin Wojtas * of configuration. 47662636ac3cSMarcin Wojtas */ 47672636ac3cSMarcin Wojtas mvreg_write(pp, MVNETA_WIN_SIZE(0), 0xffff0000); 47682636ac3cSMarcin Wojtas win_enable &= ~BIT(0); 47692636ac3cSMarcin Wojtas win_protect = 3; 47702636ac3cSMarcin Wojtas } 4771c5aff182SThomas Petazzoni 4772c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_BASE_ADDR_ENABLE, win_enable); 4773db6ba9a5SMarcin Wojtas mvreg_write(pp, MVNETA_ACCESS_PROTECT_ENABLE, win_protect); 4774c5aff182SThomas Petazzoni } 4775c5aff182SThomas Petazzoni 4776c5aff182SThomas Petazzoni /* Power up the port */ 47773f1dd4bcSThomas Petazzoni static int mvneta_port_power_up(struct mvneta_port *pp, int phy_mode) 4778c5aff182SThomas Petazzoni { 4779c5aff182SThomas Petazzoni /* MAC Cause register should be cleared */ 4780c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_UNIT_INTR_CAUSE, 0); 4781c5aff182SThomas Petazzoni 478232699954SRussell King if (phy_mode == PHY_INTERFACE_MODE_QSGMII) 47833f1dd4bcSThomas Petazzoni mvreg_write(pp, MVNETA_SERDES_CFG, MVNETA_QSGMII_SERDES_PROTO); 478422f4bf8aSRussell King else if (phy_mode == PHY_INTERFACE_MODE_SGMII || 4785a10c1c81SRussell King phy_interface_mode_is_8023z(phy_mode)) 47863f1dd4bcSThomas Petazzoni mvreg_write(pp, MVNETA_SERDES_CFG, MVNETA_SGMII_SERDES_PROTO); 478732699954SRussell King else if (!phy_interface_mode_is_rgmii(phy_mode)) 47883f1dd4bcSThomas Petazzoni return -EINVAL; 47893f1dd4bcSThomas Petazzoni 47903f1dd4bcSThomas Petazzoni return 0; 4791c5aff182SThomas Petazzoni } 4792c5aff182SThomas Petazzoni 4793c5aff182SThomas Petazzoni /* Device initialization routine */ 479403ce758eSGreg KH static int mvneta_probe(struct platform_device *pdev) 4795c5aff182SThomas Petazzoni { 4796c5aff182SThomas Petazzoni struct device_node *dn = pdev->dev.of_node; 4797dc35a10fSMarcin Wojtas struct device_node *bm_node; 4798c5aff182SThomas Petazzoni struct mvneta_port *pp; 4799c5aff182SThomas Petazzoni struct net_device *dev; 4800503f9aa9SRussell King struct phylink *phylink; 4801a10c1c81SRussell King struct phy *comphy; 48028cc3e439SThomas Petazzoni const char *dt_mac_addr; 48038cc3e439SThomas Petazzoni char hw_mac_addr[ETH_ALEN]; 48040c65b2b9SAndrew Lunn phy_interface_t phy_mode; 48058cc3e439SThomas Petazzoni const char *mac_from; 48069110ee07SMarcin Wojtas int tx_csum_limit; 4807c5aff182SThomas Petazzoni int err; 480812bb03b4SMaxime Ripard int cpu; 4809c5aff182SThomas Petazzoni 4810a3ddd94fSRosen Penev dev = devm_alloc_etherdev_mqs(&pdev->dev, sizeof(struct mvneta_port), 4811a3ddd94fSRosen Penev txq_number, rxq_number); 4812c5aff182SThomas Petazzoni if (!dev) 4813c5aff182SThomas Petazzoni return -ENOMEM; 4814c5aff182SThomas Petazzoni 4815c5aff182SThomas Petazzoni dev->irq = irq_of_parse_and_map(dn, 0); 4816a3ddd94fSRosen Penev if (dev->irq == 0) 4817a3ddd94fSRosen Penev return -EINVAL; 4818c5aff182SThomas Petazzoni 48190c65b2b9SAndrew Lunn err = of_get_phy_mode(dn, &phy_mode); 48200c65b2b9SAndrew Lunn if (err) { 4821c5aff182SThomas Petazzoni dev_err(&pdev->dev, "incorrect phy-mode\n"); 4822503f9aa9SRussell King goto err_free_irq; 4823503f9aa9SRussell King } 4824503f9aa9SRussell King 4825a10c1c81SRussell King comphy = devm_of_phy_get(&pdev->dev, dn, NULL); 4826a10c1c81SRussell King if (comphy == ERR_PTR(-EPROBE_DEFER)) { 4827a10c1c81SRussell King err = -EPROBE_DEFER; 4828a10c1c81SRussell King goto err_free_irq; 4829a10c1c81SRussell King } else if (IS_ERR(comphy)) { 4830a10c1c81SRussell King comphy = NULL; 4831a10c1c81SRussell King } 4832a10c1c81SRussell King 483344cc27e4SIoana Ciornei pp = netdev_priv(dev); 483444cc27e4SIoana Ciornei spin_lock_init(&pp->lock); 483544cc27e4SIoana Ciornei 483644cc27e4SIoana Ciornei pp->phylink_config.dev = &dev->dev; 483744cc27e4SIoana Ciornei pp->phylink_config.type = PHYLINK_NETDEV; 483844cc27e4SIoana Ciornei 483944cc27e4SIoana Ciornei phylink = phylink_create(&pp->phylink_config, pdev->dev.fwnode, 484044cc27e4SIoana Ciornei phy_mode, &mvneta_phylink_ops); 4841503f9aa9SRussell King if (IS_ERR(phylink)) { 4842503f9aa9SRussell King err = PTR_ERR(phylink); 4843503f9aa9SRussell King goto err_free_irq; 4844c5aff182SThomas Petazzoni } 4845c5aff182SThomas Petazzoni 4846c5aff182SThomas Petazzoni dev->tx_queue_len = MVNETA_MAX_TXD; 4847c5aff182SThomas Petazzoni dev->watchdog_timeo = 5 * HZ; 4848c5aff182SThomas Petazzoni dev->netdev_ops = &mvneta_netdev_ops; 4849c5aff182SThomas Petazzoni 48507ad24ea4SWilfried Klaebe dev->ethtool_ops = &mvneta_eth_tool_ops; 4851c5aff182SThomas Petazzoni 4852503f9aa9SRussell King pp->phylink = phylink; 4853a10c1c81SRussell King pp->comphy = comphy; 4854c5aff182SThomas Petazzoni pp->phy_interface = phy_mode; 4855503f9aa9SRussell King pp->dn = dn; 4856c5aff182SThomas Petazzoni 485790b74c01SGregory CLEMENT pp->rxq_def = rxq_def; 48589a401deaSGregory CLEMENT pp->indir[0] = rxq_def; 48599a401deaSGregory CLEMENT 48602636ac3cSMarcin Wojtas /* Get special SoC configurations */ 48612636ac3cSMarcin Wojtas if (of_device_is_compatible(dn, "marvell,armada-3700-neta")) 48622636ac3cSMarcin Wojtas pp->neta_armada3700 = true; 48632636ac3cSMarcin Wojtas 48642804ba4eSJisheng Zhang pp->clk = devm_clk_get(&pdev->dev, "core"); 48652804ba4eSJisheng Zhang if (IS_ERR(pp->clk)) 4866189dd626SThomas Petazzoni pp->clk = devm_clk_get(&pdev->dev, NULL); 4867189dd626SThomas Petazzoni if (IS_ERR(pp->clk)) { 4868189dd626SThomas Petazzoni err = PTR_ERR(pp->clk); 4869503f9aa9SRussell King goto err_free_phylink; 4870189dd626SThomas Petazzoni } 4871189dd626SThomas Petazzoni 4872189dd626SThomas Petazzoni clk_prepare_enable(pp->clk); 4873189dd626SThomas Petazzoni 487415cc4a4aSJisheng Zhang pp->clk_bus = devm_clk_get(&pdev->dev, "bus"); 487515cc4a4aSJisheng Zhang if (!IS_ERR(pp->clk_bus)) 487615cc4a4aSJisheng Zhang clk_prepare_enable(pp->clk_bus); 487715cc4a4aSJisheng Zhang 487800c33afbSJisheng Zhang pp->base = devm_platform_ioremap_resource(pdev, 0); 4879c3f0dd38SThomas Petazzoni if (IS_ERR(pp->base)) { 4880c3f0dd38SThomas Petazzoni err = PTR_ERR(pp->base); 48815445eaf3SArnaud Patard \(Rtp\) goto err_clk; 48825445eaf3SArnaud Patard \(Rtp\) } 48835445eaf3SArnaud Patard \(Rtp\) 488412bb03b4SMaxime Ripard /* Alloc per-cpu port structure */ 488512bb03b4SMaxime Ripard pp->ports = alloc_percpu(struct mvneta_pcpu_port); 488612bb03b4SMaxime Ripard if (!pp->ports) { 488712bb03b4SMaxime Ripard err = -ENOMEM; 488812bb03b4SMaxime Ripard goto err_clk; 488912bb03b4SMaxime Ripard } 489012bb03b4SMaxime Ripard 489174c41b04Swilly tarreau /* Alloc per-cpu stats */ 48921c213bd2SWANG Cong pp->stats = netdev_alloc_pcpu_stats(struct mvneta_pcpu_stats); 489374c41b04Swilly tarreau if (!pp->stats) { 489474c41b04Swilly tarreau err = -ENOMEM; 489512bb03b4SMaxime Ripard goto err_free_ports; 489674c41b04Swilly tarreau } 489774c41b04Swilly tarreau 48988cc3e439SThomas Petazzoni dt_mac_addr = of_get_mac_address(dn); 4899a51645f7SPetr Štetiar if (!IS_ERR(dt_mac_addr)) { 49008cc3e439SThomas Petazzoni mac_from = "device tree"; 49012d2924afSPetr Štetiar ether_addr_copy(dev->dev_addr, dt_mac_addr); 49028cc3e439SThomas Petazzoni } else { 49038cc3e439SThomas Petazzoni mvneta_get_mac_addr(pp, hw_mac_addr); 49048cc3e439SThomas Petazzoni if (is_valid_ether_addr(hw_mac_addr)) { 49058cc3e439SThomas Petazzoni mac_from = "hardware"; 49068cc3e439SThomas Petazzoni memcpy(dev->dev_addr, hw_mac_addr, ETH_ALEN); 49078cc3e439SThomas Petazzoni } else { 49088cc3e439SThomas Petazzoni mac_from = "random"; 49098cc3e439SThomas Petazzoni eth_hw_addr_random(dev); 49108cc3e439SThomas Petazzoni } 49118cc3e439SThomas Petazzoni } 49128cc3e439SThomas Petazzoni 49139110ee07SMarcin Wojtas if (!of_property_read_u32(dn, "tx-csum-limit", &tx_csum_limit)) { 49149110ee07SMarcin Wojtas if (tx_csum_limit < 0 || 49159110ee07SMarcin Wojtas tx_csum_limit > MVNETA_TX_CSUM_MAX_SIZE) { 49169110ee07SMarcin Wojtas tx_csum_limit = MVNETA_TX_CSUM_DEF_SIZE; 49179110ee07SMarcin Wojtas dev_info(&pdev->dev, 49189110ee07SMarcin Wojtas "Wrong TX csum limit in DT, set to %dB\n", 49199110ee07SMarcin Wojtas MVNETA_TX_CSUM_DEF_SIZE); 49209110ee07SMarcin Wojtas } 49219110ee07SMarcin Wojtas } else if (of_device_is_compatible(dn, "marvell,armada-370-neta")) { 49229110ee07SMarcin Wojtas tx_csum_limit = MVNETA_TX_CSUM_DEF_SIZE; 49239110ee07SMarcin Wojtas } else { 49249110ee07SMarcin Wojtas tx_csum_limit = MVNETA_TX_CSUM_MAX_SIZE; 49259110ee07SMarcin Wojtas } 49269110ee07SMarcin Wojtas 49279110ee07SMarcin Wojtas pp->tx_csum_limit = tx_csum_limit; 4928b65657fcSSimon Guinot 49299768b45cSJane Li pp->dram_target_info = mv_mbus_dram_info(); 49302636ac3cSMarcin Wojtas /* Armada3700 requires setting default configuration of Mbus 49312636ac3cSMarcin Wojtas * windows, however without using filled mbus_dram_target_info 49322636ac3cSMarcin Wojtas * structure. 49332636ac3cSMarcin Wojtas */ 49349768b45cSJane Li if (pp->dram_target_info || pp->neta_armada3700) 49359768b45cSJane Li mvneta_conf_mbus_windows(pp, pp->dram_target_info); 4936dc35a10fSMarcin Wojtas 4937c5aff182SThomas Petazzoni pp->tx_ring_size = MVNETA_MAX_TXD; 4938c5aff182SThomas Petazzoni pp->rx_ring_size = MVNETA_MAX_RXD; 4939c5aff182SThomas Petazzoni 4940c5aff182SThomas Petazzoni pp->dev = dev; 4941c5aff182SThomas Petazzoni SET_NETDEV_DEV(dev, &pdev->dev); 4942c5aff182SThomas Petazzoni 4943dc35a10fSMarcin Wojtas pp->id = global_port_id++; 49440db51da7SLorenzo Bianconi pp->rx_offset_correction = MVNETA_SKB_HEADROOM; 4945dc35a10fSMarcin Wojtas 4946dc35a10fSMarcin Wojtas /* Obtain access to BM resources if enabled and already initialized */ 4947dc35a10fSMarcin Wojtas bm_node = of_parse_phandle(dn, "buffer-manager", 0); 4948965cbbecSGregory CLEMENT if (bm_node) { 4949965cbbecSGregory CLEMENT pp->bm_priv = mvneta_bm_get(bm_node); 4950965cbbecSGregory CLEMENT if (pp->bm_priv) { 4951dc35a10fSMarcin Wojtas err = mvneta_bm_port_init(pdev, pp); 4952dc35a10fSMarcin Wojtas if (err < 0) { 4953965cbbecSGregory CLEMENT dev_info(&pdev->dev, 4954965cbbecSGregory CLEMENT "use SW buffer management\n"); 4955965cbbecSGregory CLEMENT mvneta_bm_put(pp->bm_priv); 4956dc35a10fSMarcin Wojtas pp->bm_priv = NULL; 4957dc35a10fSMarcin Wojtas } 4958dc35a10fSMarcin Wojtas } 4959562e2f46SYelena Krivosheev /* Set RX packet offset correction for platforms, whose 4960562e2f46SYelena Krivosheev * NET_SKB_PAD, exceeds 64B. It should be 64B for 64-bit 4961562e2f46SYelena Krivosheev * platforms and 0B for 32-bit ones. 4962562e2f46SYelena Krivosheev */ 4963562e2f46SYelena Krivosheev pp->rx_offset_correction = max(0, 4964562e2f46SYelena Krivosheev NET_SKB_PAD - 4965562e2f46SYelena Krivosheev MVNETA_RX_PKT_OFFSET_CORRECTION); 4966965cbbecSGregory CLEMENT } 4967d4e4da00SPeter Chen of_node_put(bm_node); 4968dc35a10fSMarcin Wojtas 49699672850bSEzequiel Garcia err = mvneta_init(&pdev->dev, pp); 49709672850bSEzequiel Garcia if (err < 0) 4971dc35a10fSMarcin Wojtas goto err_netdev; 49723f1dd4bcSThomas Petazzoni 49733f1dd4bcSThomas Petazzoni err = mvneta_port_power_up(pp, phy_mode); 49743f1dd4bcSThomas Petazzoni if (err < 0) { 49753f1dd4bcSThomas Petazzoni dev_err(&pdev->dev, "can't power up port\n"); 4976dc35a10fSMarcin Wojtas goto err_netdev; 49773f1dd4bcSThomas Petazzoni } 4978c5aff182SThomas Petazzoni 49792636ac3cSMarcin Wojtas /* Armada3700 network controller does not support per-cpu 49802636ac3cSMarcin Wojtas * operation, so only single NAPI should be initialized. 49812636ac3cSMarcin Wojtas */ 49822636ac3cSMarcin Wojtas if (pp->neta_armada3700) { 49832636ac3cSMarcin Wojtas netif_napi_add(dev, &pp->napi, mvneta_poll, NAPI_POLL_WEIGHT); 49842636ac3cSMarcin Wojtas } else { 498512bb03b4SMaxime Ripard for_each_present_cpu(cpu) { 49862636ac3cSMarcin Wojtas struct mvneta_pcpu_port *port = 49872636ac3cSMarcin Wojtas per_cpu_ptr(pp->ports, cpu); 498812bb03b4SMaxime Ripard 49892636ac3cSMarcin Wojtas netif_napi_add(dev, &port->napi, mvneta_poll, 49902636ac3cSMarcin Wojtas NAPI_POLL_WEIGHT); 499112bb03b4SMaxime Ripard port->pp = pp; 499212bb03b4SMaxime Ripard } 49932636ac3cSMarcin Wojtas } 4994c5aff182SThomas Petazzoni 49957772988aSJisheng Zhang dev->features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | 49967772988aSJisheng Zhang NETIF_F_TSO | NETIF_F_RXCSUM; 499701ef26caSEzequiel Garcia dev->hw_features |= dev->features; 499801ef26caSEzequiel Garcia dev->vlan_features |= dev->features; 499997db8afaSAndrew Lunn dev->priv_flags |= IFF_LIVE_ADDR_CHANGE; 50008eef5f97SEzequiel Garcia dev->gso_max_segs = MVNETA_MAX_TSO_SEGS; 5001b50b72deSwilly tarreau 50025777987eSJarod Wilson /* MTU range: 68 - 9676 */ 50035777987eSJarod Wilson dev->min_mtu = ETH_MIN_MTU; 50045777987eSJarod Wilson /* 9676 == 9700 - 20 and rounding to 8 */ 50055777987eSJarod Wilson dev->max_mtu = 9676; 50065777987eSJarod Wilson 5007c5aff182SThomas Petazzoni err = register_netdev(dev); 5008c5aff182SThomas Petazzoni if (err < 0) { 5009c5aff182SThomas Petazzoni dev_err(&pdev->dev, "failed to register\n"); 5010d484e06eSJisheng Zhang goto err_netdev; 5011c5aff182SThomas Petazzoni } 5012c5aff182SThomas Petazzoni 50138cc3e439SThomas Petazzoni netdev_info(dev, "Using %s mac address %pM\n", mac_from, 50148cc3e439SThomas Petazzoni dev->dev_addr); 5015c5aff182SThomas Petazzoni 5016c5aff182SThomas Petazzoni platform_set_drvdata(pdev, pp->dev); 5017c5aff182SThomas Petazzoni 5018c5aff182SThomas Petazzoni return 0; 5019c5aff182SThomas Petazzoni 5020dc35a10fSMarcin Wojtas err_netdev: 5021dc35a10fSMarcin Wojtas if (pp->bm_priv) { 5022dc35a10fSMarcin Wojtas mvneta_bm_pool_destroy(pp->bm_priv, pp->pool_long, 1 << pp->id); 5023dc35a10fSMarcin Wojtas mvneta_bm_pool_destroy(pp->bm_priv, pp->pool_short, 5024dc35a10fSMarcin Wojtas 1 << pp->id); 5025965cbbecSGregory CLEMENT mvneta_bm_put(pp->bm_priv); 5026dc35a10fSMarcin Wojtas } 502774c41b04Swilly tarreau free_percpu(pp->stats); 502812bb03b4SMaxime Ripard err_free_ports: 502912bb03b4SMaxime Ripard free_percpu(pp->ports); 50305445eaf3SArnaud Patard \(Rtp\) err_clk: 503115cc4a4aSJisheng Zhang clk_disable_unprepare(pp->clk_bus); 50325445eaf3SArnaud Patard \(Rtp\) clk_disable_unprepare(pp->clk); 5033503f9aa9SRussell King err_free_phylink: 5034503f9aa9SRussell King if (pp->phylink) 5035503f9aa9SRussell King phylink_destroy(pp->phylink); 5036c5aff182SThomas Petazzoni err_free_irq: 5037c5aff182SThomas Petazzoni irq_dispose_mapping(dev->irq); 5038c5aff182SThomas Petazzoni return err; 5039c5aff182SThomas Petazzoni } 5040c5aff182SThomas Petazzoni 5041c5aff182SThomas Petazzoni /* Device removal routine */ 504203ce758eSGreg KH static int mvneta_remove(struct platform_device *pdev) 5043c5aff182SThomas Petazzoni { 5044c5aff182SThomas Petazzoni struct net_device *dev = platform_get_drvdata(pdev); 5045c5aff182SThomas Petazzoni struct mvneta_port *pp = netdev_priv(dev); 5046c5aff182SThomas Petazzoni 5047c5aff182SThomas Petazzoni unregister_netdev(dev); 504815cc4a4aSJisheng Zhang clk_disable_unprepare(pp->clk_bus); 5049189dd626SThomas Petazzoni clk_disable_unprepare(pp->clk); 505012bb03b4SMaxime Ripard free_percpu(pp->ports); 505174c41b04Swilly tarreau free_percpu(pp->stats); 5052c5aff182SThomas Petazzoni irq_dispose_mapping(dev->irq); 5053503f9aa9SRussell King phylink_destroy(pp->phylink); 5054c5aff182SThomas Petazzoni 5055dc35a10fSMarcin Wojtas if (pp->bm_priv) { 5056dc35a10fSMarcin Wojtas mvneta_bm_pool_destroy(pp->bm_priv, pp->pool_long, 1 << pp->id); 5057dc35a10fSMarcin Wojtas mvneta_bm_pool_destroy(pp->bm_priv, pp->pool_short, 5058dc35a10fSMarcin Wojtas 1 << pp->id); 5059965cbbecSGregory CLEMENT mvneta_bm_put(pp->bm_priv); 5060dc35a10fSMarcin Wojtas } 5061dc35a10fSMarcin Wojtas 5062c5aff182SThomas Petazzoni return 0; 5063c5aff182SThomas Petazzoni } 5064c5aff182SThomas Petazzoni 50659768b45cSJane Li #ifdef CONFIG_PM_SLEEP 50669768b45cSJane Li static int mvneta_suspend(struct device *device) 50679768b45cSJane Li { 50681799cdd2SJisheng Zhang int queue; 50699768b45cSJane Li struct net_device *dev = dev_get_drvdata(device); 50709768b45cSJane Li struct mvneta_port *pp = netdev_priv(dev); 50719768b45cSJane Li 50721799cdd2SJisheng Zhang if (!netif_running(dev)) 50731799cdd2SJisheng Zhang goto clean_exit; 50741799cdd2SJisheng Zhang 50751799cdd2SJisheng Zhang if (!pp->neta_armada3700) { 50761799cdd2SJisheng Zhang spin_lock(&pp->lock); 50771799cdd2SJisheng Zhang pp->is_stopped = true; 50781799cdd2SJisheng Zhang spin_unlock(&pp->lock); 50791799cdd2SJisheng Zhang 50801799cdd2SJisheng Zhang cpuhp_state_remove_instance_nocalls(online_hpstate, 50811799cdd2SJisheng Zhang &pp->node_online); 50821799cdd2SJisheng Zhang cpuhp_state_remove_instance_nocalls(CPUHP_NET_MVNETA_DEAD, 50831799cdd2SJisheng Zhang &pp->node_dead); 50841799cdd2SJisheng Zhang } 50851799cdd2SJisheng Zhang 50863b8bc674SRussell King rtnl_lock(); 50871799cdd2SJisheng Zhang mvneta_stop_dev(pp); 50883b8bc674SRussell King rtnl_unlock(); 50891799cdd2SJisheng Zhang 50901799cdd2SJisheng Zhang for (queue = 0; queue < rxq_number; queue++) { 50911799cdd2SJisheng Zhang struct mvneta_rx_queue *rxq = &pp->rxqs[queue]; 50921799cdd2SJisheng Zhang 50931799cdd2SJisheng Zhang mvneta_rxq_drop_pkts(pp, rxq); 50941799cdd2SJisheng Zhang } 50951799cdd2SJisheng Zhang 50961799cdd2SJisheng Zhang for (queue = 0; queue < txq_number; queue++) { 50971799cdd2SJisheng Zhang struct mvneta_tx_queue *txq = &pp->txqs[queue]; 50981799cdd2SJisheng Zhang 50991799cdd2SJisheng Zhang mvneta_txq_hw_deinit(pp, txq); 51001799cdd2SJisheng Zhang } 51011799cdd2SJisheng Zhang 51021799cdd2SJisheng Zhang clean_exit: 51039768b45cSJane Li netif_device_detach(dev); 51049768b45cSJane Li clk_disable_unprepare(pp->clk_bus); 51059768b45cSJane Li clk_disable_unprepare(pp->clk); 51061799cdd2SJisheng Zhang 51079768b45cSJane Li return 0; 51089768b45cSJane Li } 51099768b45cSJane Li 51109768b45cSJane Li static int mvneta_resume(struct device *device) 51119768b45cSJane Li { 51129768b45cSJane Li struct platform_device *pdev = to_platform_device(device); 51139768b45cSJane Li struct net_device *dev = dev_get_drvdata(device); 51149768b45cSJane Li struct mvneta_port *pp = netdev_priv(dev); 51151799cdd2SJisheng Zhang int err, queue; 51169768b45cSJane Li 51179768b45cSJane Li clk_prepare_enable(pp->clk); 51189768b45cSJane Li if (!IS_ERR(pp->clk_bus)) 51199768b45cSJane Li clk_prepare_enable(pp->clk_bus); 51209768b45cSJane Li if (pp->dram_target_info || pp->neta_armada3700) 51219768b45cSJane Li mvneta_conf_mbus_windows(pp, pp->dram_target_info); 51229768b45cSJane Li if (pp->bm_priv) { 51239768b45cSJane Li err = mvneta_bm_port_init(pdev, pp); 51249768b45cSJane Li if (err < 0) { 51259768b45cSJane Li dev_info(&pdev->dev, "use SW buffer management\n"); 51269768b45cSJane Li pp->bm_priv = NULL; 51279768b45cSJane Li } 51289768b45cSJane Li } 51299768b45cSJane Li mvneta_defaults_set(pp); 51309768b45cSJane Li err = mvneta_port_power_up(pp, pp->phy_interface); 51319768b45cSJane Li if (err < 0) { 51329768b45cSJane Li dev_err(device, "can't power up port\n"); 51339768b45cSJane Li return err; 51349768b45cSJane Li } 51359768b45cSJane Li 51369768b45cSJane Li netif_device_attach(dev); 51371799cdd2SJisheng Zhang 51381799cdd2SJisheng Zhang if (!netif_running(dev)) 51391799cdd2SJisheng Zhang return 0; 51401799cdd2SJisheng Zhang 51411799cdd2SJisheng Zhang for (queue = 0; queue < rxq_number; queue++) { 51421799cdd2SJisheng Zhang struct mvneta_rx_queue *rxq = &pp->rxqs[queue]; 51431799cdd2SJisheng Zhang 51441799cdd2SJisheng Zhang rxq->next_desc_to_proc = 0; 51451799cdd2SJisheng Zhang mvneta_rxq_hw_init(pp, rxq); 5146d6956ac8SJisheng Zhang } 51471799cdd2SJisheng Zhang 51481799cdd2SJisheng Zhang for (queue = 0; queue < txq_number; queue++) { 51491799cdd2SJisheng Zhang struct mvneta_tx_queue *txq = &pp->txqs[queue]; 51501799cdd2SJisheng Zhang 51511799cdd2SJisheng Zhang txq->next_desc_to_proc = 0; 51521799cdd2SJisheng Zhang mvneta_txq_hw_init(pp, txq); 51531799cdd2SJisheng Zhang } 51541799cdd2SJisheng Zhang 51551799cdd2SJisheng Zhang if (!pp->neta_armada3700) { 51561799cdd2SJisheng Zhang spin_lock(&pp->lock); 51571799cdd2SJisheng Zhang pp->is_stopped = false; 51581799cdd2SJisheng Zhang spin_unlock(&pp->lock); 51591799cdd2SJisheng Zhang cpuhp_state_add_instance_nocalls(online_hpstate, 51601799cdd2SJisheng Zhang &pp->node_online); 51611799cdd2SJisheng Zhang cpuhp_state_add_instance_nocalls(CPUHP_NET_MVNETA_DEAD, 51621799cdd2SJisheng Zhang &pp->node_dead); 51631799cdd2SJisheng Zhang } 51641799cdd2SJisheng Zhang 51651799cdd2SJisheng Zhang rtnl_lock(); 51661799cdd2SJisheng Zhang mvneta_start_dev(pp); 51673b8bc674SRussell King rtnl_unlock(); 51681799cdd2SJisheng Zhang mvneta_set_rx_mode(dev); 5169d6956ac8SJisheng Zhang 51709768b45cSJane Li return 0; 51719768b45cSJane Li } 51729768b45cSJane Li #endif 51739768b45cSJane Li 51749768b45cSJane Li static SIMPLE_DEV_PM_OPS(mvneta_pm_ops, mvneta_suspend, mvneta_resume); 51759768b45cSJane Li 5176c5aff182SThomas Petazzoni static const struct of_device_id mvneta_match[] = { 5177c5aff182SThomas Petazzoni { .compatible = "marvell,armada-370-neta" }, 5178f522a975SSimon Guinot { .compatible = "marvell,armada-xp-neta" }, 51792636ac3cSMarcin Wojtas { .compatible = "marvell,armada-3700-neta" }, 5180c5aff182SThomas Petazzoni { } 5181c5aff182SThomas Petazzoni }; 5182c5aff182SThomas Petazzoni MODULE_DEVICE_TABLE(of, mvneta_match); 5183c5aff182SThomas Petazzoni 5184c5aff182SThomas Petazzoni static struct platform_driver mvneta_driver = { 5185c5aff182SThomas Petazzoni .probe = mvneta_probe, 518603ce758eSGreg KH .remove = mvneta_remove, 5187c5aff182SThomas Petazzoni .driver = { 5188c5aff182SThomas Petazzoni .name = MVNETA_DRIVER_NAME, 5189c5aff182SThomas Petazzoni .of_match_table = mvneta_match, 51909768b45cSJane Li .pm = &mvneta_pm_ops, 5191c5aff182SThomas Petazzoni }, 5192c5aff182SThomas Petazzoni }; 5193c5aff182SThomas Petazzoni 519484a3f4dbSSebastian Andrzej Siewior static int __init mvneta_driver_init(void) 519584a3f4dbSSebastian Andrzej Siewior { 519684a3f4dbSSebastian Andrzej Siewior int ret; 519784a3f4dbSSebastian Andrzej Siewior 519884a3f4dbSSebastian Andrzej Siewior ret = cpuhp_setup_state_multi(CPUHP_AP_ONLINE_DYN, "net/mvmeta:online", 519984a3f4dbSSebastian Andrzej Siewior mvneta_cpu_online, 520084a3f4dbSSebastian Andrzej Siewior mvneta_cpu_down_prepare); 520184a3f4dbSSebastian Andrzej Siewior if (ret < 0) 520284a3f4dbSSebastian Andrzej Siewior goto out; 520384a3f4dbSSebastian Andrzej Siewior online_hpstate = ret; 520484a3f4dbSSebastian Andrzej Siewior ret = cpuhp_setup_state_multi(CPUHP_NET_MVNETA_DEAD, "net/mvneta:dead", 520584a3f4dbSSebastian Andrzej Siewior NULL, mvneta_cpu_dead); 520684a3f4dbSSebastian Andrzej Siewior if (ret) 520784a3f4dbSSebastian Andrzej Siewior goto err_dead; 520884a3f4dbSSebastian Andrzej Siewior 520984a3f4dbSSebastian Andrzej Siewior ret = platform_driver_register(&mvneta_driver); 521084a3f4dbSSebastian Andrzej Siewior if (ret) 521184a3f4dbSSebastian Andrzej Siewior goto err; 521284a3f4dbSSebastian Andrzej Siewior return 0; 521384a3f4dbSSebastian Andrzej Siewior 521484a3f4dbSSebastian Andrzej Siewior err: 521584a3f4dbSSebastian Andrzej Siewior cpuhp_remove_multi_state(CPUHP_NET_MVNETA_DEAD); 521684a3f4dbSSebastian Andrzej Siewior err_dead: 521784a3f4dbSSebastian Andrzej Siewior cpuhp_remove_multi_state(online_hpstate); 521884a3f4dbSSebastian Andrzej Siewior out: 521984a3f4dbSSebastian Andrzej Siewior return ret; 522084a3f4dbSSebastian Andrzej Siewior } 522184a3f4dbSSebastian Andrzej Siewior module_init(mvneta_driver_init); 522284a3f4dbSSebastian Andrzej Siewior 522384a3f4dbSSebastian Andrzej Siewior static void __exit mvneta_driver_exit(void) 522484a3f4dbSSebastian Andrzej Siewior { 522584a3f4dbSSebastian Andrzej Siewior platform_driver_unregister(&mvneta_driver); 522684a3f4dbSSebastian Andrzej Siewior cpuhp_remove_multi_state(CPUHP_NET_MVNETA_DEAD); 522784a3f4dbSSebastian Andrzej Siewior cpuhp_remove_multi_state(online_hpstate); 522884a3f4dbSSebastian Andrzej Siewior } 522984a3f4dbSSebastian Andrzej Siewior module_exit(mvneta_driver_exit); 5230c5aff182SThomas Petazzoni 5231c5aff182SThomas Petazzoni MODULE_DESCRIPTION("Marvell NETA Ethernet Driver - www.marvell.com"); 5232c5aff182SThomas Petazzoni MODULE_AUTHOR("Rami Rosen <rosenr@marvell.com>, Thomas Petazzoni <thomas.petazzoni@free-electrons.com>"); 5233c5aff182SThomas Petazzoni MODULE_LICENSE("GPL"); 5234c5aff182SThomas Petazzoni 5235d3757ba4SJoe Perches module_param(rxq_number, int, 0444); 5236d3757ba4SJoe Perches module_param(txq_number, int, 0444); 5237c5aff182SThomas Petazzoni 5238d3757ba4SJoe Perches module_param(rxq_def, int, 0444); 5239d3757ba4SJoe Perches module_param(rx_copybreak, int, 0644); 5240