1c5aff182SThomas Petazzoni /* 2c5aff182SThomas Petazzoni * Driver for Marvell NETA network card for Armada XP and Armada 370 SoCs. 3c5aff182SThomas Petazzoni * 4c5aff182SThomas Petazzoni * Copyright (C) 2012 Marvell 5c5aff182SThomas Petazzoni * 6c5aff182SThomas Petazzoni * Rami Rosen <rosenr@marvell.com> 7c5aff182SThomas Petazzoni * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> 8c5aff182SThomas Petazzoni * 9c5aff182SThomas Petazzoni * This file is licensed under the terms of the GNU General Public 10c5aff182SThomas Petazzoni * License version 2. This program is licensed "as is" without any 11c5aff182SThomas Petazzoni * warranty of any kind, whether express or implied. 12c5aff182SThomas Petazzoni */ 13c5aff182SThomas Petazzoni 140e03f563SJisheng Zhang #include <linux/clk.h> 150e03f563SJisheng Zhang #include <linux/cpu.h> 16c5aff182SThomas Petazzoni #include <linux/etherdevice.h> 170e03f563SJisheng Zhang #include <linux/if_vlan.h> 18c5aff182SThomas Petazzoni #include <linux/inetdevice.h> 190e03f563SJisheng Zhang #include <linux/interrupt.h> 200e03f563SJisheng Zhang #include <linux/io.h> 210e03f563SJisheng Zhang #include <linux/kernel.h> 22c5aff182SThomas Petazzoni #include <linux/mbus.h> 23c5aff182SThomas Petazzoni #include <linux/module.h> 240e03f563SJisheng Zhang #include <linux/netdevice.h> 25c5aff182SThomas Petazzoni #include <linux/of.h> 260e03f563SJisheng Zhang #include <linux/of_address.h> 27c5aff182SThomas Petazzoni #include <linux/of_irq.h> 28c5aff182SThomas Petazzoni #include <linux/of_mdio.h> 29c5aff182SThomas Petazzoni #include <linux/of_net.h> 30c5aff182SThomas Petazzoni #include <linux/phy.h> 310e03f563SJisheng Zhang #include <linux/platform_device.h> 320e03f563SJisheng Zhang #include <linux/skbuff.h> 330e03f563SJisheng Zhang #include <net/ip.h> 340e03f563SJisheng Zhang #include <net/ipv6.h> 350e03f563SJisheng Zhang #include <net/tso.h> 36c5aff182SThomas Petazzoni 37c5aff182SThomas Petazzoni /* Registers */ 38c5aff182SThomas Petazzoni #define MVNETA_RXQ_CONFIG_REG(q) (0x1400 + ((q) << 2)) 39e5bdf689SMarcin Wojtas #define MVNETA_RXQ_HW_BUF_ALLOC BIT(0) 40c5aff182SThomas Petazzoni #define MVNETA_RXQ_PKT_OFFSET_ALL_MASK (0xf << 8) 41c5aff182SThomas Petazzoni #define MVNETA_RXQ_PKT_OFFSET_MASK(offs) ((offs) << 8) 42c5aff182SThomas Petazzoni #define MVNETA_RXQ_THRESHOLD_REG(q) (0x14c0 + ((q) << 2)) 43c5aff182SThomas Petazzoni #define MVNETA_RXQ_NON_OCCUPIED(v) ((v) << 16) 44c5aff182SThomas Petazzoni #define MVNETA_RXQ_BASE_ADDR_REG(q) (0x1480 + ((q) << 2)) 45c5aff182SThomas Petazzoni #define MVNETA_RXQ_SIZE_REG(q) (0x14a0 + ((q) << 2)) 46c5aff182SThomas Petazzoni #define MVNETA_RXQ_BUF_SIZE_SHIFT 19 47c5aff182SThomas Petazzoni #define MVNETA_RXQ_BUF_SIZE_MASK (0x1fff << 19) 48c5aff182SThomas Petazzoni #define MVNETA_RXQ_STATUS_REG(q) (0x14e0 + ((q) << 2)) 49c5aff182SThomas Petazzoni #define MVNETA_RXQ_OCCUPIED_ALL_MASK 0x3fff 50c5aff182SThomas Petazzoni #define MVNETA_RXQ_STATUS_UPDATE_REG(q) (0x1500 + ((q) << 2)) 51c5aff182SThomas Petazzoni #define MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT 16 52c5aff182SThomas Petazzoni #define MVNETA_RXQ_ADD_NON_OCCUPIED_MAX 255 53c5aff182SThomas Petazzoni #define MVNETA_PORT_RX_RESET 0x1cc0 54c5aff182SThomas Petazzoni #define MVNETA_PORT_RX_DMA_RESET BIT(0) 55c5aff182SThomas Petazzoni #define MVNETA_PHY_ADDR 0x2000 56c5aff182SThomas Petazzoni #define MVNETA_PHY_ADDR_MASK 0x1f 57c5aff182SThomas Petazzoni #define MVNETA_MBUS_RETRY 0x2010 58c5aff182SThomas Petazzoni #define MVNETA_UNIT_INTR_CAUSE 0x2080 59c5aff182SThomas Petazzoni #define MVNETA_UNIT_CONTROL 0x20B0 60c5aff182SThomas Petazzoni #define MVNETA_PHY_POLLING_ENABLE BIT(1) 61c5aff182SThomas Petazzoni #define MVNETA_WIN_BASE(w) (0x2200 + ((w) << 3)) 62c5aff182SThomas Petazzoni #define MVNETA_WIN_SIZE(w) (0x2204 + ((w) << 3)) 63c5aff182SThomas Petazzoni #define MVNETA_WIN_REMAP(w) (0x2280 + ((w) << 2)) 64c5aff182SThomas Petazzoni #define MVNETA_BASE_ADDR_ENABLE 0x2290 65db6ba9a5SMarcin Wojtas #define MVNETA_ACCESS_PROTECT_ENABLE 0x2294 66c5aff182SThomas Petazzoni #define MVNETA_PORT_CONFIG 0x2400 67c5aff182SThomas Petazzoni #define MVNETA_UNI_PROMISC_MODE BIT(0) 68c5aff182SThomas Petazzoni #define MVNETA_DEF_RXQ(q) ((q) << 1) 69c5aff182SThomas Petazzoni #define MVNETA_DEF_RXQ_ARP(q) ((q) << 4) 70c5aff182SThomas Petazzoni #define MVNETA_TX_UNSET_ERR_SUM BIT(12) 71c5aff182SThomas Petazzoni #define MVNETA_DEF_RXQ_TCP(q) ((q) << 16) 72c5aff182SThomas Petazzoni #define MVNETA_DEF_RXQ_UDP(q) ((q) << 19) 73c5aff182SThomas Petazzoni #define MVNETA_DEF_RXQ_BPDU(q) ((q) << 22) 74c5aff182SThomas Petazzoni #define MVNETA_RX_CSUM_WITH_PSEUDO_HDR BIT(25) 75c5aff182SThomas Petazzoni #define MVNETA_PORT_CONFIG_DEFL_VALUE(q) (MVNETA_DEF_RXQ(q) | \ 76c5aff182SThomas Petazzoni MVNETA_DEF_RXQ_ARP(q) | \ 77c5aff182SThomas Petazzoni MVNETA_DEF_RXQ_TCP(q) | \ 78c5aff182SThomas Petazzoni MVNETA_DEF_RXQ_UDP(q) | \ 79c5aff182SThomas Petazzoni MVNETA_DEF_RXQ_BPDU(q) | \ 80c5aff182SThomas Petazzoni MVNETA_TX_UNSET_ERR_SUM | \ 81c5aff182SThomas Petazzoni MVNETA_RX_CSUM_WITH_PSEUDO_HDR) 82c5aff182SThomas Petazzoni #define MVNETA_PORT_CONFIG_EXTEND 0x2404 83c5aff182SThomas Petazzoni #define MVNETA_MAC_ADDR_LOW 0x2414 84c5aff182SThomas Petazzoni #define MVNETA_MAC_ADDR_HIGH 0x2418 85c5aff182SThomas Petazzoni #define MVNETA_SDMA_CONFIG 0x241c 86c5aff182SThomas Petazzoni #define MVNETA_SDMA_BRST_SIZE_16 4 87c5aff182SThomas Petazzoni #define MVNETA_RX_BRST_SZ_MASK(burst) ((burst) << 1) 88c5aff182SThomas Petazzoni #define MVNETA_RX_NO_DATA_SWAP BIT(4) 89c5aff182SThomas Petazzoni #define MVNETA_TX_NO_DATA_SWAP BIT(5) 909ad8fef6SThomas Petazzoni #define MVNETA_DESC_SWAP BIT(6) 91c5aff182SThomas Petazzoni #define MVNETA_TX_BRST_SZ_MASK(burst) ((burst) << 22) 92c5aff182SThomas Petazzoni #define MVNETA_PORT_STATUS 0x2444 93c5aff182SThomas Petazzoni #define MVNETA_TX_IN_PRGRS BIT(1) 94c5aff182SThomas Petazzoni #define MVNETA_TX_FIFO_EMPTY BIT(8) 95c5aff182SThomas Petazzoni #define MVNETA_RX_MIN_FRAME_SIZE 0x247c 963f1dd4bcSThomas Petazzoni #define MVNETA_SERDES_CFG 0x24A0 975445eaf3SArnaud Patard \(Rtp\) #define MVNETA_SGMII_SERDES_PROTO 0x0cc7 983f1dd4bcSThomas Petazzoni #define MVNETA_QSGMII_SERDES_PROTO 0x0667 99c5aff182SThomas Petazzoni #define MVNETA_TYPE_PRIO 0x24bc 100c5aff182SThomas Petazzoni #define MVNETA_FORCE_UNI BIT(21) 101c5aff182SThomas Petazzoni #define MVNETA_TXQ_CMD_1 0x24e4 102c5aff182SThomas Petazzoni #define MVNETA_TXQ_CMD 0x2448 103c5aff182SThomas Petazzoni #define MVNETA_TXQ_DISABLE_SHIFT 8 104c5aff182SThomas Petazzoni #define MVNETA_TXQ_ENABLE_MASK 0x000000ff 105e483911fSAndrew Lunn #define MVNETA_RX_DISCARD_FRAME_COUNT 0x2484 106e483911fSAndrew Lunn #define MVNETA_OVERRUN_FRAME_COUNT 0x2488 107898b2970SStas Sergeev #define MVNETA_GMAC_CLOCK_DIVIDER 0x24f4 108898b2970SStas Sergeev #define MVNETA_GMAC_1MS_CLOCK_ENABLE BIT(31) 109c5aff182SThomas Petazzoni #define MVNETA_ACC_MODE 0x2500 110c5aff182SThomas Petazzoni #define MVNETA_CPU_MAP(cpu) (0x2540 + ((cpu) << 2)) 111c5aff182SThomas Petazzoni #define MVNETA_CPU_RXQ_ACCESS_ALL_MASK 0x000000ff 112c5aff182SThomas Petazzoni #define MVNETA_CPU_TXQ_ACCESS_ALL_MASK 0x0000ff00 1132dcf75e2SGregory CLEMENT #define MVNETA_CPU_RXQ_ACCESS(rxq) BIT(rxq) 11450bf8cb6SGregory CLEMENT #define MVNETA_CPU_TXQ_ACCESS(txq) BIT(txq + 8) 115c5aff182SThomas Petazzoni #define MVNETA_RXQ_TIME_COAL_REG(q) (0x2580 + ((q) << 2)) 11640ba35e7Swilly tarreau 1172dcf75e2SGregory CLEMENT /* Exception Interrupt Port/Queue Cause register 1182dcf75e2SGregory CLEMENT * 1192dcf75e2SGregory CLEMENT * Their behavior depend of the mapping done using the PCPX2Q 1202dcf75e2SGregory CLEMENT * registers. For a given CPU if the bit associated to a queue is not 1212dcf75e2SGregory CLEMENT * set, then for the register a read from this CPU will always return 1222dcf75e2SGregory CLEMENT * 0 and a write won't do anything 1232dcf75e2SGregory CLEMENT */ 12440ba35e7Swilly tarreau 125c5aff182SThomas Petazzoni #define MVNETA_INTR_NEW_CAUSE 0x25a0 126c5aff182SThomas Petazzoni #define MVNETA_INTR_NEW_MASK 0x25a4 12740ba35e7Swilly tarreau 12840ba35e7Swilly tarreau /* bits 0..7 = TXQ SENT, one bit per queue. 12940ba35e7Swilly tarreau * bits 8..15 = RXQ OCCUP, one bit per queue. 13040ba35e7Swilly tarreau * bits 16..23 = RXQ FREE, one bit per queue. 13140ba35e7Swilly tarreau * bit 29 = OLD_REG_SUM, see old reg ? 13240ba35e7Swilly tarreau * bit 30 = TX_ERR_SUM, one bit for 4 ports 13340ba35e7Swilly tarreau * bit 31 = MISC_SUM, one bit for 4 ports 13440ba35e7Swilly tarreau */ 13540ba35e7Swilly tarreau #define MVNETA_TX_INTR_MASK(nr_txqs) (((1 << nr_txqs) - 1) << 0) 13640ba35e7Swilly tarreau #define MVNETA_TX_INTR_MASK_ALL (0xff << 0) 13740ba35e7Swilly tarreau #define MVNETA_RX_INTR_MASK(nr_rxqs) (((1 << nr_rxqs) - 1) << 8) 13840ba35e7Swilly tarreau #define MVNETA_RX_INTR_MASK_ALL (0xff << 8) 139898b2970SStas Sergeev #define MVNETA_MISCINTR_INTR_MASK BIT(31) 14040ba35e7Swilly tarreau 141c5aff182SThomas Petazzoni #define MVNETA_INTR_OLD_CAUSE 0x25a8 142c5aff182SThomas Petazzoni #define MVNETA_INTR_OLD_MASK 0x25ac 14340ba35e7Swilly tarreau 14440ba35e7Swilly tarreau /* Data Path Port/Queue Cause Register */ 145c5aff182SThomas Petazzoni #define MVNETA_INTR_MISC_CAUSE 0x25b0 146c5aff182SThomas Petazzoni #define MVNETA_INTR_MISC_MASK 0x25b4 14740ba35e7Swilly tarreau 14840ba35e7Swilly tarreau #define MVNETA_CAUSE_PHY_STATUS_CHANGE BIT(0) 14940ba35e7Swilly tarreau #define MVNETA_CAUSE_LINK_CHANGE BIT(1) 15040ba35e7Swilly tarreau #define MVNETA_CAUSE_PTP BIT(4) 15140ba35e7Swilly tarreau 15240ba35e7Swilly tarreau #define MVNETA_CAUSE_INTERNAL_ADDR_ERR BIT(7) 15340ba35e7Swilly tarreau #define MVNETA_CAUSE_RX_OVERRUN BIT(8) 15440ba35e7Swilly tarreau #define MVNETA_CAUSE_RX_CRC_ERROR BIT(9) 15540ba35e7Swilly tarreau #define MVNETA_CAUSE_RX_LARGE_PKT BIT(10) 15640ba35e7Swilly tarreau #define MVNETA_CAUSE_TX_UNDERUN BIT(11) 15740ba35e7Swilly tarreau #define MVNETA_CAUSE_PRBS_ERR BIT(12) 15840ba35e7Swilly tarreau #define MVNETA_CAUSE_PSC_SYNC_CHANGE BIT(13) 15940ba35e7Swilly tarreau #define MVNETA_CAUSE_SERDES_SYNC_ERR BIT(14) 16040ba35e7Swilly tarreau 16140ba35e7Swilly tarreau #define MVNETA_CAUSE_BMU_ALLOC_ERR_SHIFT 16 16240ba35e7Swilly tarreau #define MVNETA_CAUSE_BMU_ALLOC_ERR_ALL_MASK (0xF << MVNETA_CAUSE_BMU_ALLOC_ERR_SHIFT) 16340ba35e7Swilly tarreau #define MVNETA_CAUSE_BMU_ALLOC_ERR_MASK(pool) (1 << (MVNETA_CAUSE_BMU_ALLOC_ERR_SHIFT + (pool))) 16440ba35e7Swilly tarreau 16540ba35e7Swilly tarreau #define MVNETA_CAUSE_TXQ_ERROR_SHIFT 24 16640ba35e7Swilly tarreau #define MVNETA_CAUSE_TXQ_ERROR_ALL_MASK (0xFF << MVNETA_CAUSE_TXQ_ERROR_SHIFT) 16740ba35e7Swilly tarreau #define MVNETA_CAUSE_TXQ_ERROR_MASK(q) (1 << (MVNETA_CAUSE_TXQ_ERROR_SHIFT + (q))) 16840ba35e7Swilly tarreau 169c5aff182SThomas Petazzoni #define MVNETA_INTR_ENABLE 0x25b8 170c5aff182SThomas Petazzoni #define MVNETA_TXQ_INTR_ENABLE_ALL_MASK 0x0000ff00 171dc1aadf6SMarcin Wojtas #define MVNETA_RXQ_INTR_ENABLE_ALL_MASK 0x000000ff 17240ba35e7Swilly tarreau 173c5aff182SThomas Petazzoni #define MVNETA_RXQ_CMD 0x2680 174c5aff182SThomas Petazzoni #define MVNETA_RXQ_DISABLE_SHIFT 8 175c5aff182SThomas Petazzoni #define MVNETA_RXQ_ENABLE_MASK 0x000000ff 176c5aff182SThomas Petazzoni #define MVETH_TXQ_TOKEN_COUNT_REG(q) (0x2700 + ((q) << 4)) 177c5aff182SThomas Petazzoni #define MVETH_TXQ_TOKEN_CFG_REG(q) (0x2704 + ((q) << 4)) 178c5aff182SThomas Petazzoni #define MVNETA_GMAC_CTRL_0 0x2c00 179c5aff182SThomas Petazzoni #define MVNETA_GMAC_MAX_RX_SIZE_SHIFT 2 180c5aff182SThomas Petazzoni #define MVNETA_GMAC_MAX_RX_SIZE_MASK 0x7ffc 181c5aff182SThomas Petazzoni #define MVNETA_GMAC0_PORT_ENABLE BIT(0) 182c5aff182SThomas Petazzoni #define MVNETA_GMAC_CTRL_2 0x2c08 183898b2970SStas Sergeev #define MVNETA_GMAC2_INBAND_AN_ENABLE BIT(0) 184a79121d3SThomas Petazzoni #define MVNETA_GMAC2_PCS_ENABLE BIT(3) 185c5aff182SThomas Petazzoni #define MVNETA_GMAC2_PORT_RGMII BIT(4) 186c5aff182SThomas Petazzoni #define MVNETA_GMAC2_PORT_RESET BIT(6) 187c5aff182SThomas Petazzoni #define MVNETA_GMAC_STATUS 0x2c10 188c5aff182SThomas Petazzoni #define MVNETA_GMAC_LINK_UP BIT(0) 189c5aff182SThomas Petazzoni #define MVNETA_GMAC_SPEED_1000 BIT(1) 190c5aff182SThomas Petazzoni #define MVNETA_GMAC_SPEED_100 BIT(2) 191c5aff182SThomas Petazzoni #define MVNETA_GMAC_FULL_DUPLEX BIT(3) 192c5aff182SThomas Petazzoni #define MVNETA_GMAC_RX_FLOW_CTRL_ENABLE BIT(4) 193c5aff182SThomas Petazzoni #define MVNETA_GMAC_TX_FLOW_CTRL_ENABLE BIT(5) 194c5aff182SThomas Petazzoni #define MVNETA_GMAC_RX_FLOW_CTRL_ACTIVE BIT(6) 195c5aff182SThomas Petazzoni #define MVNETA_GMAC_TX_FLOW_CTRL_ACTIVE BIT(7) 196c5aff182SThomas Petazzoni #define MVNETA_GMAC_AUTONEG_CONFIG 0x2c0c 197c5aff182SThomas Petazzoni #define MVNETA_GMAC_FORCE_LINK_DOWN BIT(0) 198c5aff182SThomas Petazzoni #define MVNETA_GMAC_FORCE_LINK_PASS BIT(1) 199898b2970SStas Sergeev #define MVNETA_GMAC_INBAND_AN_ENABLE BIT(2) 200c5aff182SThomas Petazzoni #define MVNETA_GMAC_CONFIG_MII_SPEED BIT(5) 201c5aff182SThomas Petazzoni #define MVNETA_GMAC_CONFIG_GMII_SPEED BIT(6) 20271408602SThomas Petazzoni #define MVNETA_GMAC_AN_SPEED_EN BIT(7) 203898b2970SStas Sergeev #define MVNETA_GMAC_AN_FLOW_CTRL_EN BIT(11) 204c5aff182SThomas Petazzoni #define MVNETA_GMAC_CONFIG_FULL_DUPLEX BIT(12) 20571408602SThomas Petazzoni #define MVNETA_GMAC_AN_DUPLEX_EN BIT(13) 206e483911fSAndrew Lunn #define MVNETA_MIB_COUNTERS_BASE 0x3000 207c5aff182SThomas Petazzoni #define MVNETA_MIB_LATE_COLLISION 0x7c 208c5aff182SThomas Petazzoni #define MVNETA_DA_FILT_SPEC_MCAST 0x3400 209c5aff182SThomas Petazzoni #define MVNETA_DA_FILT_OTH_MCAST 0x3500 210c5aff182SThomas Petazzoni #define MVNETA_DA_FILT_UCAST_BASE 0x3600 211c5aff182SThomas Petazzoni #define MVNETA_TXQ_BASE_ADDR_REG(q) (0x3c00 + ((q) << 2)) 212c5aff182SThomas Petazzoni #define MVNETA_TXQ_SIZE_REG(q) (0x3c20 + ((q) << 2)) 213c5aff182SThomas Petazzoni #define MVNETA_TXQ_SENT_THRESH_ALL_MASK 0x3fff0000 214c5aff182SThomas Petazzoni #define MVNETA_TXQ_SENT_THRESH_MASK(coal) ((coal) << 16) 215c5aff182SThomas Petazzoni #define MVNETA_TXQ_UPDATE_REG(q) (0x3c60 + ((q) << 2)) 216c5aff182SThomas Petazzoni #define MVNETA_TXQ_DEC_SENT_SHIFT 16 217c5aff182SThomas Petazzoni #define MVNETA_TXQ_STATUS_REG(q) (0x3c40 + ((q) << 2)) 218c5aff182SThomas Petazzoni #define MVNETA_TXQ_SENT_DESC_SHIFT 16 219c5aff182SThomas Petazzoni #define MVNETA_TXQ_SENT_DESC_MASK 0x3fff0000 220c5aff182SThomas Petazzoni #define MVNETA_PORT_TX_RESET 0x3cf0 221c5aff182SThomas Petazzoni #define MVNETA_PORT_TX_DMA_RESET BIT(0) 222c5aff182SThomas Petazzoni #define MVNETA_TX_MTU 0x3e0c 223c5aff182SThomas Petazzoni #define MVNETA_TX_TOKEN_SIZE 0x3e14 224c5aff182SThomas Petazzoni #define MVNETA_TX_TOKEN_SIZE_MAX 0xffffffff 225c5aff182SThomas Petazzoni #define MVNETA_TXQ_TOKEN_SIZE_REG(q) (0x3e40 + ((q) << 2)) 226c5aff182SThomas Petazzoni #define MVNETA_TXQ_TOKEN_SIZE_MAX 0x7fffffff 227c5aff182SThomas Petazzoni 228c5aff182SThomas Petazzoni #define MVNETA_CAUSE_TXQ_SENT_DESC_ALL_MASK 0xff 229c5aff182SThomas Petazzoni 230c5aff182SThomas Petazzoni /* Descriptor ring Macros */ 231c5aff182SThomas Petazzoni #define MVNETA_QUEUE_NEXT_DESC(q, index) \ 232c5aff182SThomas Petazzoni (((index) < (q)->last_desc) ? ((index) + 1) : 0) 233c5aff182SThomas Petazzoni 234c5aff182SThomas Petazzoni /* Various constants */ 235c5aff182SThomas Petazzoni 236c5aff182SThomas Petazzoni /* Coalescing */ 237aebea2baSwilly tarreau #define MVNETA_TXDONE_COAL_PKTS 1 238c5aff182SThomas Petazzoni #define MVNETA_RX_COAL_PKTS 32 239c5aff182SThomas Petazzoni #define MVNETA_RX_COAL_USEC 100 240c5aff182SThomas Petazzoni 2416a20c175SThomas Petazzoni /* The two bytes Marvell header. Either contains a special value used 242c5aff182SThomas Petazzoni * by Marvell switches when a specific hardware mode is enabled (not 243c5aff182SThomas Petazzoni * supported by this driver) or is filled automatically by zeroes on 244c5aff182SThomas Petazzoni * the RX side. Those two bytes being at the front of the Ethernet 245c5aff182SThomas Petazzoni * header, they allow to have the IP header aligned on a 4 bytes 246c5aff182SThomas Petazzoni * boundary automatically: the hardware skips those two bytes on its 247c5aff182SThomas Petazzoni * own. 248c5aff182SThomas Petazzoni */ 249c5aff182SThomas Petazzoni #define MVNETA_MH_SIZE 2 250c5aff182SThomas Petazzoni 251c5aff182SThomas Petazzoni #define MVNETA_VLAN_TAG_LEN 4 252c5aff182SThomas Petazzoni 253c5aff182SThomas Petazzoni #define MVNETA_CPU_D_CACHE_LINE_SIZE 32 2549110ee07SMarcin Wojtas #define MVNETA_TX_CSUM_DEF_SIZE 1600 255c5aff182SThomas Petazzoni #define MVNETA_TX_CSUM_MAX_SIZE 9800 256c5aff182SThomas Petazzoni #define MVNETA_ACC_MODE_EXT 1 257c5aff182SThomas Petazzoni 258c5aff182SThomas Petazzoni /* Timeout constants */ 259c5aff182SThomas Petazzoni #define MVNETA_TX_DISABLE_TIMEOUT_MSEC 1000 260c5aff182SThomas Petazzoni #define MVNETA_RX_DISABLE_TIMEOUT_MSEC 1000 261c5aff182SThomas Petazzoni #define MVNETA_TX_FIFO_EMPTY_TIMEOUT 10000 262c5aff182SThomas Petazzoni 263c5aff182SThomas Petazzoni #define MVNETA_TX_MTU_MAX 0x3ffff 264c5aff182SThomas Petazzoni 2659a401deaSGregory CLEMENT /* The RSS lookup table actually has 256 entries but we do not use 2669a401deaSGregory CLEMENT * them yet 2679a401deaSGregory CLEMENT */ 2689a401deaSGregory CLEMENT #define MVNETA_RSS_LU_TABLE_SIZE 1 2699a401deaSGregory CLEMENT 2702adb719dSEzequiel Garcia /* TSO header size */ 2712adb719dSEzequiel Garcia #define TSO_HEADER_SIZE 128 2722adb719dSEzequiel Garcia 273c5aff182SThomas Petazzoni /* Max number of Rx descriptors */ 274c5aff182SThomas Petazzoni #define MVNETA_MAX_RXD 128 275c5aff182SThomas Petazzoni 276c5aff182SThomas Petazzoni /* Max number of Tx descriptors */ 277c5aff182SThomas Petazzoni #define MVNETA_MAX_TXD 532 278c5aff182SThomas Petazzoni 2798eef5f97SEzequiel Garcia /* Max number of allowed TCP segments for software TSO */ 2808eef5f97SEzequiel Garcia #define MVNETA_MAX_TSO_SEGS 100 2818eef5f97SEzequiel Garcia 2828eef5f97SEzequiel Garcia #define MVNETA_MAX_SKB_DESCS (MVNETA_MAX_TSO_SEGS * 2 + MAX_SKB_FRAGS) 2838eef5f97SEzequiel Garcia 284c5aff182SThomas Petazzoni /* descriptor aligned size */ 285c5aff182SThomas Petazzoni #define MVNETA_DESC_ALIGNED_SIZE 32 286c5aff182SThomas Petazzoni 287c5aff182SThomas Petazzoni #define MVNETA_RX_PKT_SIZE(mtu) \ 288c5aff182SThomas Petazzoni ALIGN((mtu) + MVNETA_MH_SIZE + MVNETA_VLAN_TAG_LEN + \ 289c5aff182SThomas Petazzoni ETH_HLEN + ETH_FCS_LEN, \ 290c5aff182SThomas Petazzoni MVNETA_CPU_D_CACHE_LINE_SIZE) 291c5aff182SThomas Petazzoni 2922e3173a3SEzequiel Garcia #define IS_TSO_HEADER(txq, addr) \ 2932e3173a3SEzequiel Garcia ((addr >= txq->tso_hdrs_phys) && \ 2942e3173a3SEzequiel Garcia (addr < txq->tso_hdrs_phys + txq->size * TSO_HEADER_SIZE)) 2952e3173a3SEzequiel Garcia 296c5aff182SThomas Petazzoni #define MVNETA_RX_BUF_SIZE(pkt_size) ((pkt_size) + NET_SKB_PAD) 297c5aff182SThomas Petazzoni 2989b0cdefaSRussell King struct mvneta_statistic { 2999b0cdefaSRussell King unsigned short offset; 3009b0cdefaSRussell King unsigned short type; 3019b0cdefaSRussell King const char name[ETH_GSTRING_LEN]; 3029b0cdefaSRussell King }; 3039b0cdefaSRussell King 3049b0cdefaSRussell King #define T_REG_32 32 3059b0cdefaSRussell King #define T_REG_64 64 3069b0cdefaSRussell King 3079b0cdefaSRussell King static const struct mvneta_statistic mvneta_statistics[] = { 3089b0cdefaSRussell King { 0x3000, T_REG_64, "good_octets_received", }, 3099b0cdefaSRussell King { 0x3010, T_REG_32, "good_frames_received", }, 3109b0cdefaSRussell King { 0x3008, T_REG_32, "bad_octets_received", }, 3119b0cdefaSRussell King { 0x3014, T_REG_32, "bad_frames_received", }, 3129b0cdefaSRussell King { 0x3018, T_REG_32, "broadcast_frames_received", }, 3139b0cdefaSRussell King { 0x301c, T_REG_32, "multicast_frames_received", }, 3149b0cdefaSRussell King { 0x3050, T_REG_32, "unrec_mac_control_received", }, 3159b0cdefaSRussell King { 0x3058, T_REG_32, "good_fc_received", }, 3169b0cdefaSRussell King { 0x305c, T_REG_32, "bad_fc_received", }, 3179b0cdefaSRussell King { 0x3060, T_REG_32, "undersize_received", }, 3189b0cdefaSRussell King { 0x3064, T_REG_32, "fragments_received", }, 3199b0cdefaSRussell King { 0x3068, T_REG_32, "oversize_received", }, 3209b0cdefaSRussell King { 0x306c, T_REG_32, "jabber_received", }, 3219b0cdefaSRussell King { 0x3070, T_REG_32, "mac_receive_error", }, 3229b0cdefaSRussell King { 0x3074, T_REG_32, "bad_crc_event", }, 3239b0cdefaSRussell King { 0x3078, T_REG_32, "collision", }, 3249b0cdefaSRussell King { 0x307c, T_REG_32, "late_collision", }, 3259b0cdefaSRussell King { 0x2484, T_REG_32, "rx_discard", }, 3269b0cdefaSRussell King { 0x2488, T_REG_32, "rx_overrun", }, 3279b0cdefaSRussell King { 0x3020, T_REG_32, "frames_64_octets", }, 3289b0cdefaSRussell King { 0x3024, T_REG_32, "frames_65_to_127_octets", }, 3299b0cdefaSRussell King { 0x3028, T_REG_32, "frames_128_to_255_octets", }, 3309b0cdefaSRussell King { 0x302c, T_REG_32, "frames_256_to_511_octets", }, 3319b0cdefaSRussell King { 0x3030, T_REG_32, "frames_512_to_1023_octets", }, 3329b0cdefaSRussell King { 0x3034, T_REG_32, "frames_1024_to_max_octets", }, 3339b0cdefaSRussell King { 0x3038, T_REG_64, "good_octets_sent", }, 3349b0cdefaSRussell King { 0x3040, T_REG_32, "good_frames_sent", }, 3359b0cdefaSRussell King { 0x3044, T_REG_32, "excessive_collision", }, 3369b0cdefaSRussell King { 0x3048, T_REG_32, "multicast_frames_sent", }, 3379b0cdefaSRussell King { 0x304c, T_REG_32, "broadcast_frames_sent", }, 3389b0cdefaSRussell King { 0x3054, T_REG_32, "fc_sent", }, 3399b0cdefaSRussell King { 0x300c, T_REG_32, "internal_mac_transmit_err", }, 3409b0cdefaSRussell King }; 3419b0cdefaSRussell King 34274c41b04Swilly tarreau struct mvneta_pcpu_stats { 343c5aff182SThomas Petazzoni struct u64_stats_sync syncp; 34474c41b04Swilly tarreau u64 rx_packets; 34574c41b04Swilly tarreau u64 rx_bytes; 34674c41b04Swilly tarreau u64 tx_packets; 34774c41b04Swilly tarreau u64 tx_bytes; 348c5aff182SThomas Petazzoni }; 349c5aff182SThomas Petazzoni 35012bb03b4SMaxime Ripard struct mvneta_pcpu_port { 35112bb03b4SMaxime Ripard /* Pointer to the shared port */ 35212bb03b4SMaxime Ripard struct mvneta_port *pp; 35312bb03b4SMaxime Ripard 35412bb03b4SMaxime Ripard /* Pointer to the CPU-local NAPI struct */ 35512bb03b4SMaxime Ripard struct napi_struct napi; 35612bb03b4SMaxime Ripard 35712bb03b4SMaxime Ripard /* Cause of the previous interrupt */ 35812bb03b4SMaxime Ripard u32 cause_rx_tx; 35912bb03b4SMaxime Ripard }; 36012bb03b4SMaxime Ripard 361c5aff182SThomas Petazzoni struct mvneta_port { 36212bb03b4SMaxime Ripard struct mvneta_pcpu_port __percpu *ports; 36312bb03b4SMaxime Ripard struct mvneta_pcpu_stats __percpu *stats; 36412bb03b4SMaxime Ripard 365c5aff182SThomas Petazzoni int pkt_size; 3668ec2cd48Swilly tarreau unsigned int frag_size; 367c5aff182SThomas Petazzoni void __iomem *base; 368c5aff182SThomas Petazzoni struct mvneta_rx_queue *rxqs; 369c5aff182SThomas Petazzoni struct mvneta_tx_queue *txqs; 370c5aff182SThomas Petazzoni struct net_device *dev; 371f8642885SMaxime Ripard struct notifier_block cpu_notifier; 37290b74c01SGregory CLEMENT int rxq_def; 373c5aff182SThomas Petazzoni 374c5aff182SThomas Petazzoni /* Core clock */ 375189dd626SThomas Petazzoni struct clk *clk; 37615cc4a4aSJisheng Zhang /* AXI clock */ 37715cc4a4aSJisheng Zhang struct clk *clk_bus; 378c5aff182SThomas Petazzoni u8 mcast_count[256]; 379c5aff182SThomas Petazzoni u16 tx_ring_size; 380c5aff182SThomas Petazzoni u16 rx_ring_size; 381c5aff182SThomas Petazzoni 382c5aff182SThomas Petazzoni struct mii_bus *mii_bus; 383c5aff182SThomas Petazzoni struct phy_device *phy_dev; 384c5aff182SThomas Petazzoni phy_interface_t phy_interface; 385c5aff182SThomas Petazzoni struct device_node *phy_node; 386c5aff182SThomas Petazzoni unsigned int link; 387c5aff182SThomas Petazzoni unsigned int duplex; 388c5aff182SThomas Petazzoni unsigned int speed; 389b65657fcSSimon Guinot unsigned int tx_csum_limit; 3900c0744fcSStas Sergeev unsigned int use_inband_status:1; 3919b0cdefaSRussell King 3929b0cdefaSRussell King u64 ethtool_stats[ARRAY_SIZE(mvneta_statistics)]; 3939a401deaSGregory CLEMENT 3949a401deaSGregory CLEMENT u32 indir[MVNETA_RSS_LU_TABLE_SIZE]; 395c5aff182SThomas Petazzoni }; 396c5aff182SThomas Petazzoni 3976a20c175SThomas Petazzoni /* The mvneta_tx_desc and mvneta_rx_desc structures describe the 398c5aff182SThomas Petazzoni * layout of the transmit and reception DMA descriptors, and their 399c5aff182SThomas Petazzoni * layout is therefore defined by the hardware design 400c5aff182SThomas Petazzoni */ 4016083ed44SThomas Petazzoni 402c5aff182SThomas Petazzoni #define MVNETA_TX_L3_OFF_SHIFT 0 403c5aff182SThomas Petazzoni #define MVNETA_TX_IP_HLEN_SHIFT 8 404c5aff182SThomas Petazzoni #define MVNETA_TX_L4_UDP BIT(16) 405c5aff182SThomas Petazzoni #define MVNETA_TX_L3_IP6 BIT(17) 406c5aff182SThomas Petazzoni #define MVNETA_TXD_IP_CSUM BIT(18) 407c5aff182SThomas Petazzoni #define MVNETA_TXD_Z_PAD BIT(19) 408c5aff182SThomas Petazzoni #define MVNETA_TXD_L_DESC BIT(20) 409c5aff182SThomas Petazzoni #define MVNETA_TXD_F_DESC BIT(21) 410c5aff182SThomas Petazzoni #define MVNETA_TXD_FLZ_DESC (MVNETA_TXD_Z_PAD | \ 411c5aff182SThomas Petazzoni MVNETA_TXD_L_DESC | \ 412c5aff182SThomas Petazzoni MVNETA_TXD_F_DESC) 413c5aff182SThomas Petazzoni #define MVNETA_TX_L4_CSUM_FULL BIT(30) 414c5aff182SThomas Petazzoni #define MVNETA_TX_L4_CSUM_NOT BIT(31) 415c5aff182SThomas Petazzoni 416c5aff182SThomas Petazzoni #define MVNETA_RXD_ERR_CRC 0x0 417c5aff182SThomas Petazzoni #define MVNETA_RXD_ERR_SUMMARY BIT(16) 418c5aff182SThomas Petazzoni #define MVNETA_RXD_ERR_OVERRUN BIT(17) 419c5aff182SThomas Petazzoni #define MVNETA_RXD_ERR_LEN BIT(18) 420c5aff182SThomas Petazzoni #define MVNETA_RXD_ERR_RESOURCE (BIT(17) | BIT(18)) 421c5aff182SThomas Petazzoni #define MVNETA_RXD_ERR_CODE_MASK (BIT(17) | BIT(18)) 422c5aff182SThomas Petazzoni #define MVNETA_RXD_L3_IP4 BIT(25) 423c5aff182SThomas Petazzoni #define MVNETA_RXD_FIRST_LAST_DESC (BIT(26) | BIT(27)) 424c5aff182SThomas Petazzoni #define MVNETA_RXD_L4_CSUM_OK BIT(30) 425c5aff182SThomas Petazzoni 4269ad8fef6SThomas Petazzoni #if defined(__LITTLE_ENDIAN) 4276083ed44SThomas Petazzoni struct mvneta_tx_desc { 4286083ed44SThomas Petazzoni u32 command; /* Options used by HW for packet transmitting.*/ 4296083ed44SThomas Petazzoni u16 reserverd1; /* csum_l4 (for future use) */ 4306083ed44SThomas Petazzoni u16 data_size; /* Data size of transmitted packet in bytes */ 4316083ed44SThomas Petazzoni u32 buf_phys_addr; /* Physical addr of transmitted buffer */ 4326083ed44SThomas Petazzoni u32 reserved2; /* hw_cmd - (for future use, PMT) */ 4336083ed44SThomas Petazzoni u32 reserved3[4]; /* Reserved - (for future use) */ 4346083ed44SThomas Petazzoni }; 4356083ed44SThomas Petazzoni 4366083ed44SThomas Petazzoni struct mvneta_rx_desc { 4376083ed44SThomas Petazzoni u32 status; /* Info about received packet */ 438c5aff182SThomas Petazzoni u16 reserved1; /* pnc_info - (for future use, PnC) */ 439c5aff182SThomas Petazzoni u16 data_size; /* Size of received packet in bytes */ 4406083ed44SThomas Petazzoni 441c5aff182SThomas Petazzoni u32 buf_phys_addr; /* Physical address of the buffer */ 442c5aff182SThomas Petazzoni u32 reserved2; /* pnc_flow_id (for future use, PnC) */ 4436083ed44SThomas Petazzoni 444c5aff182SThomas Petazzoni u32 buf_cookie; /* cookie for access to RX buffer in rx path */ 445c5aff182SThomas Petazzoni u16 reserved3; /* prefetch_cmd, for future use */ 446c5aff182SThomas Petazzoni u16 reserved4; /* csum_l4 - (for future use, PnC) */ 4476083ed44SThomas Petazzoni 448c5aff182SThomas Petazzoni u32 reserved5; /* pnc_extra PnC (for future use, PnC) */ 449c5aff182SThomas Petazzoni u32 reserved6; /* hw_cmd (for future use, PnC and HWF) */ 450c5aff182SThomas Petazzoni }; 4519ad8fef6SThomas Petazzoni #else 4529ad8fef6SThomas Petazzoni struct mvneta_tx_desc { 4539ad8fef6SThomas Petazzoni u16 data_size; /* Data size of transmitted packet in bytes */ 4549ad8fef6SThomas Petazzoni u16 reserverd1; /* csum_l4 (for future use) */ 4559ad8fef6SThomas Petazzoni u32 command; /* Options used by HW for packet transmitting.*/ 4569ad8fef6SThomas Petazzoni u32 reserved2; /* hw_cmd - (for future use, PMT) */ 4579ad8fef6SThomas Petazzoni u32 buf_phys_addr; /* Physical addr of transmitted buffer */ 4589ad8fef6SThomas Petazzoni u32 reserved3[4]; /* Reserved - (for future use) */ 4599ad8fef6SThomas Petazzoni }; 4609ad8fef6SThomas Petazzoni 4619ad8fef6SThomas Petazzoni struct mvneta_rx_desc { 4629ad8fef6SThomas Petazzoni u16 data_size; /* Size of received packet in bytes */ 4639ad8fef6SThomas Petazzoni u16 reserved1; /* pnc_info - (for future use, PnC) */ 4649ad8fef6SThomas Petazzoni u32 status; /* Info about received packet */ 4659ad8fef6SThomas Petazzoni 4669ad8fef6SThomas Petazzoni u32 reserved2; /* pnc_flow_id (for future use, PnC) */ 4679ad8fef6SThomas Petazzoni u32 buf_phys_addr; /* Physical address of the buffer */ 4689ad8fef6SThomas Petazzoni 4699ad8fef6SThomas Petazzoni u16 reserved4; /* csum_l4 - (for future use, PnC) */ 4709ad8fef6SThomas Petazzoni u16 reserved3; /* prefetch_cmd, for future use */ 4719ad8fef6SThomas Petazzoni u32 buf_cookie; /* cookie for access to RX buffer in rx path */ 4729ad8fef6SThomas Petazzoni 4739ad8fef6SThomas Petazzoni u32 reserved5; /* pnc_extra PnC (for future use, PnC) */ 4749ad8fef6SThomas Petazzoni u32 reserved6; /* hw_cmd (for future use, PnC and HWF) */ 4759ad8fef6SThomas Petazzoni }; 4769ad8fef6SThomas Petazzoni #endif 477c5aff182SThomas Petazzoni 478c5aff182SThomas Petazzoni struct mvneta_tx_queue { 479c5aff182SThomas Petazzoni /* Number of this TX queue, in the range 0-7 */ 480c5aff182SThomas Petazzoni u8 id; 481c5aff182SThomas Petazzoni 482c5aff182SThomas Petazzoni /* Number of TX DMA descriptors in the descriptor ring */ 483c5aff182SThomas Petazzoni int size; 484c5aff182SThomas Petazzoni 485c5aff182SThomas Petazzoni /* Number of currently used TX DMA descriptor in the 4866a20c175SThomas Petazzoni * descriptor ring 4876a20c175SThomas Petazzoni */ 488c5aff182SThomas Petazzoni int count; 4898eef5f97SEzequiel Garcia int tx_stop_threshold; 4908eef5f97SEzequiel Garcia int tx_wake_threshold; 491c5aff182SThomas Petazzoni 492c5aff182SThomas Petazzoni /* Array of transmitted skb */ 493c5aff182SThomas Petazzoni struct sk_buff **tx_skb; 494c5aff182SThomas Petazzoni 495c5aff182SThomas Petazzoni /* Index of last TX DMA descriptor that was inserted */ 496c5aff182SThomas Petazzoni int txq_put_index; 497c5aff182SThomas Petazzoni 498c5aff182SThomas Petazzoni /* Index of the TX DMA descriptor to be cleaned up */ 499c5aff182SThomas Petazzoni int txq_get_index; 500c5aff182SThomas Petazzoni 501c5aff182SThomas Petazzoni u32 done_pkts_coal; 502c5aff182SThomas Petazzoni 503c5aff182SThomas Petazzoni /* Virtual address of the TX DMA descriptors array */ 504c5aff182SThomas Petazzoni struct mvneta_tx_desc *descs; 505c5aff182SThomas Petazzoni 506c5aff182SThomas Petazzoni /* DMA address of the TX DMA descriptors array */ 507c5aff182SThomas Petazzoni dma_addr_t descs_phys; 508c5aff182SThomas Petazzoni 509c5aff182SThomas Petazzoni /* Index of the last TX DMA descriptor */ 510c5aff182SThomas Petazzoni int last_desc; 511c5aff182SThomas Petazzoni 512c5aff182SThomas Petazzoni /* Index of the next TX DMA descriptor to process */ 513c5aff182SThomas Petazzoni int next_desc_to_proc; 5142adb719dSEzequiel Garcia 5152adb719dSEzequiel Garcia /* DMA buffers for TSO headers */ 5162adb719dSEzequiel Garcia char *tso_hdrs; 5172adb719dSEzequiel Garcia 5182adb719dSEzequiel Garcia /* DMA address of TSO headers */ 5192adb719dSEzequiel Garcia dma_addr_t tso_hdrs_phys; 52050bf8cb6SGregory CLEMENT 52150bf8cb6SGregory CLEMENT /* Affinity mask for CPUs*/ 52250bf8cb6SGregory CLEMENT cpumask_t affinity_mask; 523c5aff182SThomas Petazzoni }; 524c5aff182SThomas Petazzoni 525c5aff182SThomas Petazzoni struct mvneta_rx_queue { 526c5aff182SThomas Petazzoni /* rx queue number, in the range 0-7 */ 527c5aff182SThomas Petazzoni u8 id; 528c5aff182SThomas Petazzoni 529c5aff182SThomas Petazzoni /* num of rx descriptors in the rx descriptor ring */ 530c5aff182SThomas Petazzoni int size; 531c5aff182SThomas Petazzoni 532c5aff182SThomas Petazzoni /* counter of times when mvneta_refill() failed */ 533c5aff182SThomas Petazzoni int missed; 534c5aff182SThomas Petazzoni 535c5aff182SThomas Petazzoni u32 pkts_coal; 536c5aff182SThomas Petazzoni u32 time_coal; 537c5aff182SThomas Petazzoni 538c5aff182SThomas Petazzoni /* Virtual address of the RX DMA descriptors array */ 539c5aff182SThomas Petazzoni struct mvneta_rx_desc *descs; 540c5aff182SThomas Petazzoni 541c5aff182SThomas Petazzoni /* DMA address of the RX DMA descriptors array */ 542c5aff182SThomas Petazzoni dma_addr_t descs_phys; 543c5aff182SThomas Petazzoni 544c5aff182SThomas Petazzoni /* Index of the last RX DMA descriptor */ 545c5aff182SThomas Petazzoni int last_desc; 546c5aff182SThomas Petazzoni 547c5aff182SThomas Petazzoni /* Index of the next RX DMA descriptor to process */ 548c5aff182SThomas Petazzoni int next_desc_to_proc; 549c5aff182SThomas Petazzoni }; 550c5aff182SThomas Petazzoni 551edadb7faSEzequiel Garcia /* The hardware supports eight (8) rx queues, but we are only allowing 552edadb7faSEzequiel Garcia * the first one to be used. Therefore, let's just allocate one queue. 553edadb7faSEzequiel Garcia */ 554d8936657SMaxime Ripard static int rxq_number = 8; 555c5aff182SThomas Petazzoni static int txq_number = 8; 556c5aff182SThomas Petazzoni 557c5aff182SThomas Petazzoni static int rxq_def; 558c5aff182SThomas Petazzoni 559f19fadfcSwilly tarreau static int rx_copybreak __read_mostly = 256; 560f19fadfcSwilly tarreau 561c5aff182SThomas Petazzoni #define MVNETA_DRIVER_NAME "mvneta" 562c5aff182SThomas Petazzoni #define MVNETA_DRIVER_VERSION "1.0" 563c5aff182SThomas Petazzoni 564c5aff182SThomas Petazzoni /* Utility/helper methods */ 565c5aff182SThomas Petazzoni 566c5aff182SThomas Petazzoni /* Write helper method */ 567c5aff182SThomas Petazzoni static void mvreg_write(struct mvneta_port *pp, u32 offset, u32 data) 568c5aff182SThomas Petazzoni { 569c5aff182SThomas Petazzoni writel(data, pp->base + offset); 570c5aff182SThomas Petazzoni } 571c5aff182SThomas Petazzoni 572c5aff182SThomas Petazzoni /* Read helper method */ 573c5aff182SThomas Petazzoni static u32 mvreg_read(struct mvneta_port *pp, u32 offset) 574c5aff182SThomas Petazzoni { 575c5aff182SThomas Petazzoni return readl(pp->base + offset); 576c5aff182SThomas Petazzoni } 577c5aff182SThomas Petazzoni 578c5aff182SThomas Petazzoni /* Increment txq get counter */ 579c5aff182SThomas Petazzoni static void mvneta_txq_inc_get(struct mvneta_tx_queue *txq) 580c5aff182SThomas Petazzoni { 581c5aff182SThomas Petazzoni txq->txq_get_index++; 582c5aff182SThomas Petazzoni if (txq->txq_get_index == txq->size) 583c5aff182SThomas Petazzoni txq->txq_get_index = 0; 584c5aff182SThomas Petazzoni } 585c5aff182SThomas Petazzoni 586c5aff182SThomas Petazzoni /* Increment txq put counter */ 587c5aff182SThomas Petazzoni static void mvneta_txq_inc_put(struct mvneta_tx_queue *txq) 588c5aff182SThomas Petazzoni { 589c5aff182SThomas Petazzoni txq->txq_put_index++; 590c5aff182SThomas Petazzoni if (txq->txq_put_index == txq->size) 591c5aff182SThomas Petazzoni txq->txq_put_index = 0; 592c5aff182SThomas Petazzoni } 593c5aff182SThomas Petazzoni 594c5aff182SThomas Petazzoni 595c5aff182SThomas Petazzoni /* Clear all MIB counters */ 596c5aff182SThomas Petazzoni static void mvneta_mib_counters_clear(struct mvneta_port *pp) 597c5aff182SThomas Petazzoni { 598c5aff182SThomas Petazzoni int i; 599c5aff182SThomas Petazzoni u32 dummy; 600c5aff182SThomas Petazzoni 601c5aff182SThomas Petazzoni /* Perform dummy reads from MIB counters */ 602c5aff182SThomas Petazzoni for (i = 0; i < MVNETA_MIB_LATE_COLLISION; i += 4) 603c5aff182SThomas Petazzoni dummy = mvreg_read(pp, (MVNETA_MIB_COUNTERS_BASE + i)); 604e483911fSAndrew Lunn dummy = mvreg_read(pp, MVNETA_RX_DISCARD_FRAME_COUNT); 605e483911fSAndrew Lunn dummy = mvreg_read(pp, MVNETA_OVERRUN_FRAME_COUNT); 606c5aff182SThomas Petazzoni } 607c5aff182SThomas Petazzoni 608c5aff182SThomas Petazzoni /* Get System Network Statistics */ 609c5aff182SThomas Petazzoni struct rtnl_link_stats64 *mvneta_get_stats64(struct net_device *dev, 610c5aff182SThomas Petazzoni struct rtnl_link_stats64 *stats) 611c5aff182SThomas Petazzoni { 612c5aff182SThomas Petazzoni struct mvneta_port *pp = netdev_priv(dev); 613c5aff182SThomas Petazzoni unsigned int start; 61474c41b04Swilly tarreau int cpu; 615c5aff182SThomas Petazzoni 61674c41b04Swilly tarreau for_each_possible_cpu(cpu) { 61774c41b04Swilly tarreau struct mvneta_pcpu_stats *cpu_stats; 61874c41b04Swilly tarreau u64 rx_packets; 61974c41b04Swilly tarreau u64 rx_bytes; 62074c41b04Swilly tarreau u64 tx_packets; 62174c41b04Swilly tarreau u64 tx_bytes; 622c5aff182SThomas Petazzoni 62374c41b04Swilly tarreau cpu_stats = per_cpu_ptr(pp->stats, cpu); 624c5aff182SThomas Petazzoni do { 62557a7744eSEric W. Biederman start = u64_stats_fetch_begin_irq(&cpu_stats->syncp); 62674c41b04Swilly tarreau rx_packets = cpu_stats->rx_packets; 62774c41b04Swilly tarreau rx_bytes = cpu_stats->rx_bytes; 62874c41b04Swilly tarreau tx_packets = cpu_stats->tx_packets; 62974c41b04Swilly tarreau tx_bytes = cpu_stats->tx_bytes; 63057a7744eSEric W. Biederman } while (u64_stats_fetch_retry_irq(&cpu_stats->syncp, start)); 631c5aff182SThomas Petazzoni 63274c41b04Swilly tarreau stats->rx_packets += rx_packets; 63374c41b04Swilly tarreau stats->rx_bytes += rx_bytes; 63474c41b04Swilly tarreau stats->tx_packets += tx_packets; 63574c41b04Swilly tarreau stats->tx_bytes += tx_bytes; 63674c41b04Swilly tarreau } 637c5aff182SThomas Petazzoni 638c5aff182SThomas Petazzoni stats->rx_errors = dev->stats.rx_errors; 639c5aff182SThomas Petazzoni stats->rx_dropped = dev->stats.rx_dropped; 640c5aff182SThomas Petazzoni 641c5aff182SThomas Petazzoni stats->tx_dropped = dev->stats.tx_dropped; 642c5aff182SThomas Petazzoni 643c5aff182SThomas Petazzoni return stats; 644c5aff182SThomas Petazzoni } 645c5aff182SThomas Petazzoni 646c5aff182SThomas Petazzoni /* Rx descriptors helper methods */ 647c5aff182SThomas Petazzoni 6485428213cSwilly tarreau /* Checks whether the RX descriptor having this status is both the first 6495428213cSwilly tarreau * and the last descriptor for the RX packet. Each RX packet is currently 650c5aff182SThomas Petazzoni * received through a single RX descriptor, so not having each RX 651c5aff182SThomas Petazzoni * descriptor with its first and last bits set is an error 652c5aff182SThomas Petazzoni */ 6535428213cSwilly tarreau static int mvneta_rxq_desc_is_first_last(u32 status) 654c5aff182SThomas Petazzoni { 6555428213cSwilly tarreau return (status & MVNETA_RXD_FIRST_LAST_DESC) == 656c5aff182SThomas Petazzoni MVNETA_RXD_FIRST_LAST_DESC; 657c5aff182SThomas Petazzoni } 658c5aff182SThomas Petazzoni 659c5aff182SThomas Petazzoni /* Add number of descriptors ready to receive new packets */ 660c5aff182SThomas Petazzoni static void mvneta_rxq_non_occup_desc_add(struct mvneta_port *pp, 661c5aff182SThomas Petazzoni struct mvneta_rx_queue *rxq, 662c5aff182SThomas Petazzoni int ndescs) 663c5aff182SThomas Petazzoni { 664c5aff182SThomas Petazzoni /* Only MVNETA_RXQ_ADD_NON_OCCUPIED_MAX (255) descriptors can 6656a20c175SThomas Petazzoni * be added at once 6666a20c175SThomas Petazzoni */ 667c5aff182SThomas Petazzoni while (ndescs > MVNETA_RXQ_ADD_NON_OCCUPIED_MAX) { 668c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id), 669c5aff182SThomas Petazzoni (MVNETA_RXQ_ADD_NON_OCCUPIED_MAX << 670c5aff182SThomas Petazzoni MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT)); 671c5aff182SThomas Petazzoni ndescs -= MVNETA_RXQ_ADD_NON_OCCUPIED_MAX; 672c5aff182SThomas Petazzoni } 673c5aff182SThomas Petazzoni 674c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id), 675c5aff182SThomas Petazzoni (ndescs << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT)); 676c5aff182SThomas Petazzoni } 677c5aff182SThomas Petazzoni 678c5aff182SThomas Petazzoni /* Get number of RX descriptors occupied by received packets */ 679c5aff182SThomas Petazzoni static int mvneta_rxq_busy_desc_num_get(struct mvneta_port *pp, 680c5aff182SThomas Petazzoni struct mvneta_rx_queue *rxq) 681c5aff182SThomas Petazzoni { 682c5aff182SThomas Petazzoni u32 val; 683c5aff182SThomas Petazzoni 684c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_RXQ_STATUS_REG(rxq->id)); 685c5aff182SThomas Petazzoni return val & MVNETA_RXQ_OCCUPIED_ALL_MASK; 686c5aff182SThomas Petazzoni } 687c5aff182SThomas Petazzoni 6886a20c175SThomas Petazzoni /* Update num of rx desc called upon return from rx path or 689c5aff182SThomas Petazzoni * from mvneta_rxq_drop_pkts(). 690c5aff182SThomas Petazzoni */ 691c5aff182SThomas Petazzoni static void mvneta_rxq_desc_num_update(struct mvneta_port *pp, 692c5aff182SThomas Petazzoni struct mvneta_rx_queue *rxq, 693c5aff182SThomas Petazzoni int rx_done, int rx_filled) 694c5aff182SThomas Petazzoni { 695c5aff182SThomas Petazzoni u32 val; 696c5aff182SThomas Petazzoni 697c5aff182SThomas Petazzoni if ((rx_done <= 0xff) && (rx_filled <= 0xff)) { 698c5aff182SThomas Petazzoni val = rx_done | 699c5aff182SThomas Petazzoni (rx_filled << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT); 700c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id), val); 701c5aff182SThomas Petazzoni return; 702c5aff182SThomas Petazzoni } 703c5aff182SThomas Petazzoni 704c5aff182SThomas Petazzoni /* Only 255 descriptors can be added at once */ 705c5aff182SThomas Petazzoni while ((rx_done > 0) || (rx_filled > 0)) { 706c5aff182SThomas Petazzoni if (rx_done <= 0xff) { 707c5aff182SThomas Petazzoni val = rx_done; 708c5aff182SThomas Petazzoni rx_done = 0; 709c5aff182SThomas Petazzoni } else { 710c5aff182SThomas Petazzoni val = 0xff; 711c5aff182SThomas Petazzoni rx_done -= 0xff; 712c5aff182SThomas Petazzoni } 713c5aff182SThomas Petazzoni if (rx_filled <= 0xff) { 714c5aff182SThomas Petazzoni val |= rx_filled << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT; 715c5aff182SThomas Petazzoni rx_filled = 0; 716c5aff182SThomas Petazzoni } else { 717c5aff182SThomas Petazzoni val |= 0xff << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT; 718c5aff182SThomas Petazzoni rx_filled -= 0xff; 719c5aff182SThomas Petazzoni } 720c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id), val); 721c5aff182SThomas Petazzoni } 722c5aff182SThomas Petazzoni } 723c5aff182SThomas Petazzoni 724c5aff182SThomas Petazzoni /* Get pointer to next RX descriptor to be processed by SW */ 725c5aff182SThomas Petazzoni static struct mvneta_rx_desc * 726c5aff182SThomas Petazzoni mvneta_rxq_next_desc_get(struct mvneta_rx_queue *rxq) 727c5aff182SThomas Petazzoni { 728c5aff182SThomas Petazzoni int rx_desc = rxq->next_desc_to_proc; 729c5aff182SThomas Petazzoni 730c5aff182SThomas Petazzoni rxq->next_desc_to_proc = MVNETA_QUEUE_NEXT_DESC(rxq, rx_desc); 73134e4179dSwilly tarreau prefetch(rxq->descs + rxq->next_desc_to_proc); 732c5aff182SThomas Petazzoni return rxq->descs + rx_desc; 733c5aff182SThomas Petazzoni } 734c5aff182SThomas Petazzoni 735c5aff182SThomas Petazzoni /* Change maximum receive size of the port. */ 736c5aff182SThomas Petazzoni static void mvneta_max_rx_size_set(struct mvneta_port *pp, int max_rx_size) 737c5aff182SThomas Petazzoni { 738c5aff182SThomas Petazzoni u32 val; 739c5aff182SThomas Petazzoni 740c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_GMAC_CTRL_0); 741c5aff182SThomas Petazzoni val &= ~MVNETA_GMAC_MAX_RX_SIZE_MASK; 742c5aff182SThomas Petazzoni val |= ((max_rx_size - MVNETA_MH_SIZE) / 2) << 743c5aff182SThomas Petazzoni MVNETA_GMAC_MAX_RX_SIZE_SHIFT; 744c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_GMAC_CTRL_0, val); 745c5aff182SThomas Petazzoni } 746c5aff182SThomas Petazzoni 747c5aff182SThomas Petazzoni 748c5aff182SThomas Petazzoni /* Set rx queue offset */ 749c5aff182SThomas Petazzoni static void mvneta_rxq_offset_set(struct mvneta_port *pp, 750c5aff182SThomas Petazzoni struct mvneta_rx_queue *rxq, 751c5aff182SThomas Petazzoni int offset) 752c5aff182SThomas Petazzoni { 753c5aff182SThomas Petazzoni u32 val; 754c5aff182SThomas Petazzoni 755c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_RXQ_CONFIG_REG(rxq->id)); 756c5aff182SThomas Petazzoni val &= ~MVNETA_RXQ_PKT_OFFSET_ALL_MASK; 757c5aff182SThomas Petazzoni 758c5aff182SThomas Petazzoni /* Offset is in */ 759c5aff182SThomas Petazzoni val |= MVNETA_RXQ_PKT_OFFSET_MASK(offset >> 3); 760c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_RXQ_CONFIG_REG(rxq->id), val); 761c5aff182SThomas Petazzoni } 762c5aff182SThomas Petazzoni 763c5aff182SThomas Petazzoni 764c5aff182SThomas Petazzoni /* Tx descriptors helper methods */ 765c5aff182SThomas Petazzoni 766c5aff182SThomas Petazzoni /* Update HW with number of TX descriptors to be sent */ 767c5aff182SThomas Petazzoni static void mvneta_txq_pend_desc_add(struct mvneta_port *pp, 768c5aff182SThomas Petazzoni struct mvneta_tx_queue *txq, 769c5aff182SThomas Petazzoni int pend_desc) 770c5aff182SThomas Petazzoni { 771c5aff182SThomas Petazzoni u32 val; 772c5aff182SThomas Petazzoni 773c5aff182SThomas Petazzoni /* Only 255 descriptors can be added at once ; Assume caller 7746a20c175SThomas Petazzoni * process TX desriptors in quanta less than 256 7756a20c175SThomas Petazzoni */ 776c5aff182SThomas Petazzoni val = pend_desc; 777c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val); 778c5aff182SThomas Petazzoni } 779c5aff182SThomas Petazzoni 780c5aff182SThomas Petazzoni /* Get pointer to next TX descriptor to be processed (send) by HW */ 781c5aff182SThomas Petazzoni static struct mvneta_tx_desc * 782c5aff182SThomas Petazzoni mvneta_txq_next_desc_get(struct mvneta_tx_queue *txq) 783c5aff182SThomas Petazzoni { 784c5aff182SThomas Petazzoni int tx_desc = txq->next_desc_to_proc; 785c5aff182SThomas Petazzoni 786c5aff182SThomas Petazzoni txq->next_desc_to_proc = MVNETA_QUEUE_NEXT_DESC(txq, tx_desc); 787c5aff182SThomas Petazzoni return txq->descs + tx_desc; 788c5aff182SThomas Petazzoni } 789c5aff182SThomas Petazzoni 790c5aff182SThomas Petazzoni /* Release the last allocated TX descriptor. Useful to handle DMA 7916a20c175SThomas Petazzoni * mapping failures in the TX path. 7926a20c175SThomas Petazzoni */ 793c5aff182SThomas Petazzoni static void mvneta_txq_desc_put(struct mvneta_tx_queue *txq) 794c5aff182SThomas Petazzoni { 795c5aff182SThomas Petazzoni if (txq->next_desc_to_proc == 0) 796c5aff182SThomas Petazzoni txq->next_desc_to_proc = txq->last_desc - 1; 797c5aff182SThomas Petazzoni else 798c5aff182SThomas Petazzoni txq->next_desc_to_proc--; 799c5aff182SThomas Petazzoni } 800c5aff182SThomas Petazzoni 801c5aff182SThomas Petazzoni /* Set rxq buf size */ 802c5aff182SThomas Petazzoni static void mvneta_rxq_buf_size_set(struct mvneta_port *pp, 803c5aff182SThomas Petazzoni struct mvneta_rx_queue *rxq, 804c5aff182SThomas Petazzoni int buf_size) 805c5aff182SThomas Petazzoni { 806c5aff182SThomas Petazzoni u32 val; 807c5aff182SThomas Petazzoni 808c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_RXQ_SIZE_REG(rxq->id)); 809c5aff182SThomas Petazzoni 810c5aff182SThomas Petazzoni val &= ~MVNETA_RXQ_BUF_SIZE_MASK; 811c5aff182SThomas Petazzoni val |= ((buf_size >> 3) << MVNETA_RXQ_BUF_SIZE_SHIFT); 812c5aff182SThomas Petazzoni 813c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_RXQ_SIZE_REG(rxq->id), val); 814c5aff182SThomas Petazzoni } 815c5aff182SThomas Petazzoni 816c5aff182SThomas Petazzoni /* Disable buffer management (BM) */ 817c5aff182SThomas Petazzoni static void mvneta_rxq_bm_disable(struct mvneta_port *pp, 818c5aff182SThomas Petazzoni struct mvneta_rx_queue *rxq) 819c5aff182SThomas Petazzoni { 820c5aff182SThomas Petazzoni u32 val; 821c5aff182SThomas Petazzoni 822c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_RXQ_CONFIG_REG(rxq->id)); 823c5aff182SThomas Petazzoni val &= ~MVNETA_RXQ_HW_BUF_ALLOC; 824c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_RXQ_CONFIG_REG(rxq->id), val); 825c5aff182SThomas Petazzoni } 826c5aff182SThomas Petazzoni 827c5aff182SThomas Petazzoni /* Start the Ethernet port RX and TX activity */ 828c5aff182SThomas Petazzoni static void mvneta_port_up(struct mvneta_port *pp) 829c5aff182SThomas Petazzoni { 830c5aff182SThomas Petazzoni int queue; 831c5aff182SThomas Petazzoni u32 q_map; 832c5aff182SThomas Petazzoni 833c5aff182SThomas Petazzoni /* Enable all initialized TXs. */ 834c5aff182SThomas Petazzoni q_map = 0; 835c5aff182SThomas Petazzoni for (queue = 0; queue < txq_number; queue++) { 836c5aff182SThomas Petazzoni struct mvneta_tx_queue *txq = &pp->txqs[queue]; 837c5aff182SThomas Petazzoni if (txq->descs != NULL) 838c5aff182SThomas Petazzoni q_map |= (1 << queue); 839c5aff182SThomas Petazzoni } 840c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_TXQ_CMD, q_map); 841c5aff182SThomas Petazzoni 842c5aff182SThomas Petazzoni /* Enable all initialized RXQs. */ 8432dcf75e2SGregory CLEMENT for (queue = 0; queue < rxq_number; queue++) { 8442dcf75e2SGregory CLEMENT struct mvneta_rx_queue *rxq = &pp->rxqs[queue]; 8452dcf75e2SGregory CLEMENT 8462dcf75e2SGregory CLEMENT if (rxq->descs != NULL) 8472dcf75e2SGregory CLEMENT q_map |= (1 << queue); 8482dcf75e2SGregory CLEMENT } 8492dcf75e2SGregory CLEMENT mvreg_write(pp, MVNETA_RXQ_CMD, q_map); 850c5aff182SThomas Petazzoni } 851c5aff182SThomas Petazzoni 852c5aff182SThomas Petazzoni /* Stop the Ethernet port activity */ 853c5aff182SThomas Petazzoni static void mvneta_port_down(struct mvneta_port *pp) 854c5aff182SThomas Petazzoni { 855c5aff182SThomas Petazzoni u32 val; 856c5aff182SThomas Petazzoni int count; 857c5aff182SThomas Petazzoni 858c5aff182SThomas Petazzoni /* Stop Rx port activity. Check port Rx activity. */ 859c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_RXQ_CMD) & MVNETA_RXQ_ENABLE_MASK; 860c5aff182SThomas Petazzoni 861c5aff182SThomas Petazzoni /* Issue stop command for active channels only */ 862c5aff182SThomas Petazzoni if (val != 0) 863c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_RXQ_CMD, 864c5aff182SThomas Petazzoni val << MVNETA_RXQ_DISABLE_SHIFT); 865c5aff182SThomas Petazzoni 866c5aff182SThomas Petazzoni /* Wait for all Rx activity to terminate. */ 867c5aff182SThomas Petazzoni count = 0; 868c5aff182SThomas Petazzoni do { 869c5aff182SThomas Petazzoni if (count++ >= MVNETA_RX_DISABLE_TIMEOUT_MSEC) { 870c5aff182SThomas Petazzoni netdev_warn(pp->dev, 871c5aff182SThomas Petazzoni "TIMEOUT for RX stopped ! rx_queue_cmd: 0x08%x\n", 872c5aff182SThomas Petazzoni val); 873c5aff182SThomas Petazzoni break; 874c5aff182SThomas Petazzoni } 875c5aff182SThomas Petazzoni mdelay(1); 876c5aff182SThomas Petazzoni 877c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_RXQ_CMD); 878c5aff182SThomas Petazzoni } while (val & 0xff); 879c5aff182SThomas Petazzoni 880c5aff182SThomas Petazzoni /* Stop Tx port activity. Check port Tx activity. Issue stop 8816a20c175SThomas Petazzoni * command for active channels only 8826a20c175SThomas Petazzoni */ 883c5aff182SThomas Petazzoni val = (mvreg_read(pp, MVNETA_TXQ_CMD)) & MVNETA_TXQ_ENABLE_MASK; 884c5aff182SThomas Petazzoni 885c5aff182SThomas Petazzoni if (val != 0) 886c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_TXQ_CMD, 887c5aff182SThomas Petazzoni (val << MVNETA_TXQ_DISABLE_SHIFT)); 888c5aff182SThomas Petazzoni 889c5aff182SThomas Petazzoni /* Wait for all Tx activity to terminate. */ 890c5aff182SThomas Petazzoni count = 0; 891c5aff182SThomas Petazzoni do { 892c5aff182SThomas Petazzoni if (count++ >= MVNETA_TX_DISABLE_TIMEOUT_MSEC) { 893c5aff182SThomas Petazzoni netdev_warn(pp->dev, 894c5aff182SThomas Petazzoni "TIMEOUT for TX stopped status=0x%08x\n", 895c5aff182SThomas Petazzoni val); 896c5aff182SThomas Petazzoni break; 897c5aff182SThomas Petazzoni } 898c5aff182SThomas Petazzoni mdelay(1); 899c5aff182SThomas Petazzoni 900c5aff182SThomas Petazzoni /* Check TX Command reg that all Txqs are stopped */ 901c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_TXQ_CMD); 902c5aff182SThomas Petazzoni 903c5aff182SThomas Petazzoni } while (val & 0xff); 904c5aff182SThomas Petazzoni 905c5aff182SThomas Petazzoni /* Double check to verify that TX FIFO is empty */ 906c5aff182SThomas Petazzoni count = 0; 907c5aff182SThomas Petazzoni do { 908c5aff182SThomas Petazzoni if (count++ >= MVNETA_TX_FIFO_EMPTY_TIMEOUT) { 909c5aff182SThomas Petazzoni netdev_warn(pp->dev, 910c5aff182SThomas Petazzoni "TX FIFO empty timeout status=0x08%x\n", 911c5aff182SThomas Petazzoni val); 912c5aff182SThomas Petazzoni break; 913c5aff182SThomas Petazzoni } 914c5aff182SThomas Petazzoni mdelay(1); 915c5aff182SThomas Petazzoni 916c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_PORT_STATUS); 917c5aff182SThomas Petazzoni } while (!(val & MVNETA_TX_FIFO_EMPTY) && 918c5aff182SThomas Petazzoni (val & MVNETA_TX_IN_PRGRS)); 919c5aff182SThomas Petazzoni 920c5aff182SThomas Petazzoni udelay(200); 921c5aff182SThomas Petazzoni } 922c5aff182SThomas Petazzoni 923c5aff182SThomas Petazzoni /* Enable the port by setting the port enable bit of the MAC control register */ 924c5aff182SThomas Petazzoni static void mvneta_port_enable(struct mvneta_port *pp) 925c5aff182SThomas Petazzoni { 926c5aff182SThomas Petazzoni u32 val; 927c5aff182SThomas Petazzoni 928c5aff182SThomas Petazzoni /* Enable port */ 929c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_GMAC_CTRL_0); 930c5aff182SThomas Petazzoni val |= MVNETA_GMAC0_PORT_ENABLE; 931c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_GMAC_CTRL_0, val); 932c5aff182SThomas Petazzoni } 933c5aff182SThomas Petazzoni 934c5aff182SThomas Petazzoni /* Disable the port and wait for about 200 usec before retuning */ 935c5aff182SThomas Petazzoni static void mvneta_port_disable(struct mvneta_port *pp) 936c5aff182SThomas Petazzoni { 937c5aff182SThomas Petazzoni u32 val; 938c5aff182SThomas Petazzoni 939c5aff182SThomas Petazzoni /* Reset the Enable bit in the Serial Control Register */ 940c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_GMAC_CTRL_0); 941c5aff182SThomas Petazzoni val &= ~MVNETA_GMAC0_PORT_ENABLE; 942c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_GMAC_CTRL_0, val); 943c5aff182SThomas Petazzoni 944c5aff182SThomas Petazzoni udelay(200); 945c5aff182SThomas Petazzoni } 946c5aff182SThomas Petazzoni 947c5aff182SThomas Petazzoni /* Multicast tables methods */ 948c5aff182SThomas Petazzoni 949c5aff182SThomas Petazzoni /* Set all entries in Unicast MAC Table; queue==-1 means reject all */ 950c5aff182SThomas Petazzoni static void mvneta_set_ucast_table(struct mvneta_port *pp, int queue) 951c5aff182SThomas Petazzoni { 952c5aff182SThomas Petazzoni int offset; 953c5aff182SThomas Petazzoni u32 val; 954c5aff182SThomas Petazzoni 955c5aff182SThomas Petazzoni if (queue == -1) { 956c5aff182SThomas Petazzoni val = 0; 957c5aff182SThomas Petazzoni } else { 958c5aff182SThomas Petazzoni val = 0x1 | (queue << 1); 959c5aff182SThomas Petazzoni val |= (val << 24) | (val << 16) | (val << 8); 960c5aff182SThomas Petazzoni } 961c5aff182SThomas Petazzoni 962c5aff182SThomas Petazzoni for (offset = 0; offset <= 0xc; offset += 4) 963c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_DA_FILT_UCAST_BASE + offset, val); 964c5aff182SThomas Petazzoni } 965c5aff182SThomas Petazzoni 966c5aff182SThomas Petazzoni /* Set all entries in Special Multicast MAC Table; queue==-1 means reject all */ 967c5aff182SThomas Petazzoni static void mvneta_set_special_mcast_table(struct mvneta_port *pp, int queue) 968c5aff182SThomas Petazzoni { 969c5aff182SThomas Petazzoni int offset; 970c5aff182SThomas Petazzoni u32 val; 971c5aff182SThomas Petazzoni 972c5aff182SThomas Petazzoni if (queue == -1) { 973c5aff182SThomas Petazzoni val = 0; 974c5aff182SThomas Petazzoni } else { 975c5aff182SThomas Petazzoni val = 0x1 | (queue << 1); 976c5aff182SThomas Petazzoni val |= (val << 24) | (val << 16) | (val << 8); 977c5aff182SThomas Petazzoni } 978c5aff182SThomas Petazzoni 979c5aff182SThomas Petazzoni for (offset = 0; offset <= 0xfc; offset += 4) 980c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_DA_FILT_SPEC_MCAST + offset, val); 981c5aff182SThomas Petazzoni 982c5aff182SThomas Petazzoni } 983c5aff182SThomas Petazzoni 984c5aff182SThomas Petazzoni /* Set all entries in Other Multicast MAC Table. queue==-1 means reject all */ 985c5aff182SThomas Petazzoni static void mvneta_set_other_mcast_table(struct mvneta_port *pp, int queue) 986c5aff182SThomas Petazzoni { 987c5aff182SThomas Petazzoni int offset; 988c5aff182SThomas Petazzoni u32 val; 989c5aff182SThomas Petazzoni 990c5aff182SThomas Petazzoni if (queue == -1) { 991c5aff182SThomas Petazzoni memset(pp->mcast_count, 0, sizeof(pp->mcast_count)); 992c5aff182SThomas Petazzoni val = 0; 993c5aff182SThomas Petazzoni } else { 994c5aff182SThomas Petazzoni memset(pp->mcast_count, 1, sizeof(pp->mcast_count)); 995c5aff182SThomas Petazzoni val = 0x1 | (queue << 1); 996c5aff182SThomas Petazzoni val |= (val << 24) | (val << 16) | (val << 8); 997c5aff182SThomas Petazzoni } 998c5aff182SThomas Petazzoni 999c5aff182SThomas Petazzoni for (offset = 0; offset <= 0xfc; offset += 4) 1000c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_DA_FILT_OTH_MCAST + offset, val); 1001c5aff182SThomas Petazzoni } 1002c5aff182SThomas Petazzoni 10030c0744fcSStas Sergeev static void mvneta_set_autoneg(struct mvneta_port *pp, int enable) 10040c0744fcSStas Sergeev { 10050c0744fcSStas Sergeev u32 val; 10060c0744fcSStas Sergeev 10070c0744fcSStas Sergeev if (enable) { 10080c0744fcSStas Sergeev val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG); 10090c0744fcSStas Sergeev val &= ~(MVNETA_GMAC_FORCE_LINK_PASS | 10100c0744fcSStas Sergeev MVNETA_GMAC_FORCE_LINK_DOWN | 10110c0744fcSStas Sergeev MVNETA_GMAC_AN_FLOW_CTRL_EN); 10120c0744fcSStas Sergeev val |= MVNETA_GMAC_INBAND_AN_ENABLE | 10130c0744fcSStas Sergeev MVNETA_GMAC_AN_SPEED_EN | 10140c0744fcSStas Sergeev MVNETA_GMAC_AN_DUPLEX_EN; 10150c0744fcSStas Sergeev mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val); 10160c0744fcSStas Sergeev 10170c0744fcSStas Sergeev val = mvreg_read(pp, MVNETA_GMAC_CLOCK_DIVIDER); 10180c0744fcSStas Sergeev val |= MVNETA_GMAC_1MS_CLOCK_ENABLE; 10190c0744fcSStas Sergeev mvreg_write(pp, MVNETA_GMAC_CLOCK_DIVIDER, val); 10200c0744fcSStas Sergeev 10210c0744fcSStas Sergeev val = mvreg_read(pp, MVNETA_GMAC_CTRL_2); 10220c0744fcSStas Sergeev val |= MVNETA_GMAC2_INBAND_AN_ENABLE; 10230c0744fcSStas Sergeev mvreg_write(pp, MVNETA_GMAC_CTRL_2, val); 10240c0744fcSStas Sergeev } else { 10250c0744fcSStas Sergeev val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG); 10260c0744fcSStas Sergeev val &= ~(MVNETA_GMAC_INBAND_AN_ENABLE | 10270c0744fcSStas Sergeev MVNETA_GMAC_AN_SPEED_EN | 10280c0744fcSStas Sergeev MVNETA_GMAC_AN_DUPLEX_EN); 10290c0744fcSStas Sergeev mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val); 10300c0744fcSStas Sergeev 10310c0744fcSStas Sergeev val = mvreg_read(pp, MVNETA_GMAC_CLOCK_DIVIDER); 10320c0744fcSStas Sergeev val &= ~MVNETA_GMAC_1MS_CLOCK_ENABLE; 10330c0744fcSStas Sergeev mvreg_write(pp, MVNETA_GMAC_CLOCK_DIVIDER, val); 10340c0744fcSStas Sergeev 10350c0744fcSStas Sergeev val = mvreg_read(pp, MVNETA_GMAC_CTRL_2); 10360c0744fcSStas Sergeev val &= ~MVNETA_GMAC2_INBAND_AN_ENABLE; 10370c0744fcSStas Sergeev mvreg_write(pp, MVNETA_GMAC_CTRL_2, val); 10380c0744fcSStas Sergeev } 10390c0744fcSStas Sergeev } 10400c0744fcSStas Sergeev 1041c5aff182SThomas Petazzoni /* This method sets defaults to the NETA port: 1042c5aff182SThomas Petazzoni * Clears interrupt Cause and Mask registers. 1043c5aff182SThomas Petazzoni * Clears all MAC tables. 1044c5aff182SThomas Petazzoni * Sets defaults to all registers. 1045c5aff182SThomas Petazzoni * Resets RX and TX descriptor rings. 1046c5aff182SThomas Petazzoni * Resets PHY. 1047c5aff182SThomas Petazzoni * This method can be called after mvneta_port_down() to return the port 1048c5aff182SThomas Petazzoni * settings to defaults. 1049c5aff182SThomas Petazzoni */ 1050c5aff182SThomas Petazzoni static void mvneta_defaults_set(struct mvneta_port *pp) 1051c5aff182SThomas Petazzoni { 1052c5aff182SThomas Petazzoni int cpu; 1053c5aff182SThomas Petazzoni int queue; 1054c5aff182SThomas Petazzoni u32 val; 10552dcf75e2SGregory CLEMENT int max_cpu = num_present_cpus(); 1056c5aff182SThomas Petazzoni 1057c5aff182SThomas Petazzoni /* Clear all Cause registers */ 1058c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_INTR_NEW_CAUSE, 0); 1059c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_INTR_OLD_CAUSE, 0); 1060c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_INTR_MISC_CAUSE, 0); 1061c5aff182SThomas Petazzoni 1062c5aff182SThomas Petazzoni /* Mask all interrupts */ 1063c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_INTR_NEW_MASK, 0); 1064c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_INTR_OLD_MASK, 0); 1065c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_INTR_MISC_MASK, 0); 1066c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_INTR_ENABLE, 0); 1067c5aff182SThomas Petazzoni 1068c5aff182SThomas Petazzoni /* Enable MBUS Retry bit16 */ 1069c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_MBUS_RETRY, 0x20); 1070c5aff182SThomas Petazzoni 107150bf8cb6SGregory CLEMENT /* Set CPU queue access map. CPUs are assigned to the RX and 107250bf8cb6SGregory CLEMENT * TX queues modulo their number. If there is only one TX 107350bf8cb6SGregory CLEMENT * queue then it is assigned to the CPU associated to the 107450bf8cb6SGregory CLEMENT * default RX queue. 10756a20c175SThomas Petazzoni */ 10762dcf75e2SGregory CLEMENT for_each_present_cpu(cpu) { 10772dcf75e2SGregory CLEMENT int rxq_map = 0, txq_map = 0; 107850bf8cb6SGregory CLEMENT int rxq, txq; 10792dcf75e2SGregory CLEMENT 10802dcf75e2SGregory CLEMENT for (rxq = 0; rxq < rxq_number; rxq++) 10812dcf75e2SGregory CLEMENT if ((rxq % max_cpu) == cpu) 10822dcf75e2SGregory CLEMENT rxq_map |= MVNETA_CPU_RXQ_ACCESS(rxq); 10832dcf75e2SGregory CLEMENT 108450bf8cb6SGregory CLEMENT for (txq = 0; txq < txq_number; txq++) 108550bf8cb6SGregory CLEMENT if ((txq % max_cpu) == cpu) 108650bf8cb6SGregory CLEMENT txq_map |= MVNETA_CPU_TXQ_ACCESS(txq); 108750bf8cb6SGregory CLEMENT 108850bf8cb6SGregory CLEMENT /* With only one TX queue we configure a special case 108950bf8cb6SGregory CLEMENT * which will allow to get all the irq on a single 109050bf8cb6SGregory CLEMENT * CPU 109150bf8cb6SGregory CLEMENT */ 109250bf8cb6SGregory CLEMENT if (txq_number == 1) 109350bf8cb6SGregory CLEMENT txq_map = (cpu == pp->rxq_def) ? 109450bf8cb6SGregory CLEMENT MVNETA_CPU_TXQ_ACCESS(1) : 0; 10952dcf75e2SGregory CLEMENT 10962dcf75e2SGregory CLEMENT mvreg_write(pp, MVNETA_CPU_MAP(cpu), rxq_map | txq_map); 10972dcf75e2SGregory CLEMENT } 1098c5aff182SThomas Petazzoni 1099c5aff182SThomas Petazzoni /* Reset RX and TX DMAs */ 1100c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_PORT_RX_RESET, MVNETA_PORT_RX_DMA_RESET); 1101c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_PORT_TX_RESET, MVNETA_PORT_TX_DMA_RESET); 1102c5aff182SThomas Petazzoni 1103c5aff182SThomas Petazzoni /* Disable Legacy WRR, Disable EJP, Release from reset */ 1104c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_TXQ_CMD_1, 0); 1105c5aff182SThomas Petazzoni for (queue = 0; queue < txq_number; queue++) { 1106c5aff182SThomas Petazzoni mvreg_write(pp, MVETH_TXQ_TOKEN_COUNT_REG(queue), 0); 1107c5aff182SThomas Petazzoni mvreg_write(pp, MVETH_TXQ_TOKEN_CFG_REG(queue), 0); 1108c5aff182SThomas Petazzoni } 1109c5aff182SThomas Petazzoni 1110c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_PORT_TX_RESET, 0); 1111c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_PORT_RX_RESET, 0); 1112c5aff182SThomas Petazzoni 1113c5aff182SThomas Petazzoni /* Set Port Acceleration Mode */ 1114c5aff182SThomas Petazzoni val = MVNETA_ACC_MODE_EXT; 1115c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_ACC_MODE, val); 1116c5aff182SThomas Petazzoni 1117c5aff182SThomas Petazzoni /* Update val of portCfg register accordingly with all RxQueue types */ 111890b74c01SGregory CLEMENT val = MVNETA_PORT_CONFIG_DEFL_VALUE(pp->rxq_def); 1119c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_PORT_CONFIG, val); 1120c5aff182SThomas Petazzoni 1121c5aff182SThomas Petazzoni val = 0; 1122c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_PORT_CONFIG_EXTEND, val); 1123c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_RX_MIN_FRAME_SIZE, 64); 1124c5aff182SThomas Petazzoni 1125c5aff182SThomas Petazzoni /* Build PORT_SDMA_CONFIG_REG */ 1126c5aff182SThomas Petazzoni val = 0; 1127c5aff182SThomas Petazzoni 1128c5aff182SThomas Petazzoni /* Default burst size */ 1129c5aff182SThomas Petazzoni val |= MVNETA_TX_BRST_SZ_MASK(MVNETA_SDMA_BRST_SIZE_16); 1130c5aff182SThomas Petazzoni val |= MVNETA_RX_BRST_SZ_MASK(MVNETA_SDMA_BRST_SIZE_16); 11319ad8fef6SThomas Petazzoni val |= MVNETA_RX_NO_DATA_SWAP | MVNETA_TX_NO_DATA_SWAP; 1132c5aff182SThomas Petazzoni 11339ad8fef6SThomas Petazzoni #if defined(__BIG_ENDIAN) 11349ad8fef6SThomas Petazzoni val |= MVNETA_DESC_SWAP; 11359ad8fef6SThomas Petazzoni #endif 1136c5aff182SThomas Petazzoni 1137c5aff182SThomas Petazzoni /* Assign port SDMA configuration */ 1138c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_SDMA_CONFIG, val); 1139c5aff182SThomas Petazzoni 114071408602SThomas Petazzoni /* Disable PHY polling in hardware, since we're using the 114171408602SThomas Petazzoni * kernel phylib to do this. 114271408602SThomas Petazzoni */ 114371408602SThomas Petazzoni val = mvreg_read(pp, MVNETA_UNIT_CONTROL); 114471408602SThomas Petazzoni val &= ~MVNETA_PHY_POLLING_ENABLE; 114571408602SThomas Petazzoni mvreg_write(pp, MVNETA_UNIT_CONTROL, val); 114671408602SThomas Petazzoni 11470c0744fcSStas Sergeev mvneta_set_autoneg(pp, pp->use_inband_status); 1148c5aff182SThomas Petazzoni mvneta_set_ucast_table(pp, -1); 1149c5aff182SThomas Petazzoni mvneta_set_special_mcast_table(pp, -1); 1150c5aff182SThomas Petazzoni mvneta_set_other_mcast_table(pp, -1); 1151c5aff182SThomas Petazzoni 1152c5aff182SThomas Petazzoni /* Set port interrupt enable register - default enable all */ 1153c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_INTR_ENABLE, 1154c5aff182SThomas Petazzoni (MVNETA_RXQ_INTR_ENABLE_ALL_MASK 1155c5aff182SThomas Petazzoni | MVNETA_TXQ_INTR_ENABLE_ALL_MASK)); 1156e483911fSAndrew Lunn 1157e483911fSAndrew Lunn mvneta_mib_counters_clear(pp); 1158c5aff182SThomas Petazzoni } 1159c5aff182SThomas Petazzoni 1160c5aff182SThomas Petazzoni /* Set max sizes for tx queues */ 1161c5aff182SThomas Petazzoni static void mvneta_txq_max_tx_size_set(struct mvneta_port *pp, int max_tx_size) 1162c5aff182SThomas Petazzoni 1163c5aff182SThomas Petazzoni { 1164c5aff182SThomas Petazzoni u32 val, size, mtu; 1165c5aff182SThomas Petazzoni int queue; 1166c5aff182SThomas Petazzoni 1167c5aff182SThomas Petazzoni mtu = max_tx_size * 8; 1168c5aff182SThomas Petazzoni if (mtu > MVNETA_TX_MTU_MAX) 1169c5aff182SThomas Petazzoni mtu = MVNETA_TX_MTU_MAX; 1170c5aff182SThomas Petazzoni 1171c5aff182SThomas Petazzoni /* Set MTU */ 1172c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_TX_MTU); 1173c5aff182SThomas Petazzoni val &= ~MVNETA_TX_MTU_MAX; 1174c5aff182SThomas Petazzoni val |= mtu; 1175c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_TX_MTU, val); 1176c5aff182SThomas Petazzoni 1177c5aff182SThomas Petazzoni /* TX token size and all TXQs token size must be larger that MTU */ 1178c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_TX_TOKEN_SIZE); 1179c5aff182SThomas Petazzoni 1180c5aff182SThomas Petazzoni size = val & MVNETA_TX_TOKEN_SIZE_MAX; 1181c5aff182SThomas Petazzoni if (size < mtu) { 1182c5aff182SThomas Petazzoni size = mtu; 1183c5aff182SThomas Petazzoni val &= ~MVNETA_TX_TOKEN_SIZE_MAX; 1184c5aff182SThomas Petazzoni val |= size; 1185c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_TX_TOKEN_SIZE, val); 1186c5aff182SThomas Petazzoni } 1187c5aff182SThomas Petazzoni for (queue = 0; queue < txq_number; queue++) { 1188c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_TXQ_TOKEN_SIZE_REG(queue)); 1189c5aff182SThomas Petazzoni 1190c5aff182SThomas Petazzoni size = val & MVNETA_TXQ_TOKEN_SIZE_MAX; 1191c5aff182SThomas Petazzoni if (size < mtu) { 1192c5aff182SThomas Petazzoni size = mtu; 1193c5aff182SThomas Petazzoni val &= ~MVNETA_TXQ_TOKEN_SIZE_MAX; 1194c5aff182SThomas Petazzoni val |= size; 1195c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_TXQ_TOKEN_SIZE_REG(queue), val); 1196c5aff182SThomas Petazzoni } 1197c5aff182SThomas Petazzoni } 1198c5aff182SThomas Petazzoni } 1199c5aff182SThomas Petazzoni 1200c5aff182SThomas Petazzoni /* Set unicast address */ 1201c5aff182SThomas Petazzoni static void mvneta_set_ucast_addr(struct mvneta_port *pp, u8 last_nibble, 1202c5aff182SThomas Petazzoni int queue) 1203c5aff182SThomas Petazzoni { 1204c5aff182SThomas Petazzoni unsigned int unicast_reg; 1205c5aff182SThomas Petazzoni unsigned int tbl_offset; 1206c5aff182SThomas Petazzoni unsigned int reg_offset; 1207c5aff182SThomas Petazzoni 1208c5aff182SThomas Petazzoni /* Locate the Unicast table entry */ 1209c5aff182SThomas Petazzoni last_nibble = (0xf & last_nibble); 1210c5aff182SThomas Petazzoni 1211c5aff182SThomas Petazzoni /* offset from unicast tbl base */ 1212c5aff182SThomas Petazzoni tbl_offset = (last_nibble / 4) * 4; 1213c5aff182SThomas Petazzoni 1214c5aff182SThomas Petazzoni /* offset within the above reg */ 1215c5aff182SThomas Petazzoni reg_offset = last_nibble % 4; 1216c5aff182SThomas Petazzoni 1217c5aff182SThomas Petazzoni unicast_reg = mvreg_read(pp, (MVNETA_DA_FILT_UCAST_BASE + tbl_offset)); 1218c5aff182SThomas Petazzoni 1219c5aff182SThomas Petazzoni if (queue == -1) { 1220c5aff182SThomas Petazzoni /* Clear accepts frame bit at specified unicast DA tbl entry */ 1221c5aff182SThomas Petazzoni unicast_reg &= ~(0xff << (8 * reg_offset)); 1222c5aff182SThomas Petazzoni } else { 1223c5aff182SThomas Petazzoni unicast_reg &= ~(0xff << (8 * reg_offset)); 1224c5aff182SThomas Petazzoni unicast_reg |= ((0x01 | (queue << 1)) << (8 * reg_offset)); 1225c5aff182SThomas Petazzoni } 1226c5aff182SThomas Petazzoni 1227c5aff182SThomas Petazzoni mvreg_write(pp, (MVNETA_DA_FILT_UCAST_BASE + tbl_offset), unicast_reg); 1228c5aff182SThomas Petazzoni } 1229c5aff182SThomas Petazzoni 1230c5aff182SThomas Petazzoni /* Set mac address */ 1231c5aff182SThomas Petazzoni static void mvneta_mac_addr_set(struct mvneta_port *pp, unsigned char *addr, 1232c5aff182SThomas Petazzoni int queue) 1233c5aff182SThomas Petazzoni { 1234c5aff182SThomas Petazzoni unsigned int mac_h; 1235c5aff182SThomas Petazzoni unsigned int mac_l; 1236c5aff182SThomas Petazzoni 1237c5aff182SThomas Petazzoni if (queue != -1) { 1238c5aff182SThomas Petazzoni mac_l = (addr[4] << 8) | (addr[5]); 1239c5aff182SThomas Petazzoni mac_h = (addr[0] << 24) | (addr[1] << 16) | 1240c5aff182SThomas Petazzoni (addr[2] << 8) | (addr[3] << 0); 1241c5aff182SThomas Petazzoni 1242c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_MAC_ADDR_LOW, mac_l); 1243c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_MAC_ADDR_HIGH, mac_h); 1244c5aff182SThomas Petazzoni } 1245c5aff182SThomas Petazzoni 1246c5aff182SThomas Petazzoni /* Accept frames of this address */ 1247c5aff182SThomas Petazzoni mvneta_set_ucast_addr(pp, addr[5], queue); 1248c5aff182SThomas Petazzoni } 1249c5aff182SThomas Petazzoni 12506a20c175SThomas Petazzoni /* Set the number of packets that will be received before RX interrupt 12516a20c175SThomas Petazzoni * will be generated by HW. 1252c5aff182SThomas Petazzoni */ 1253c5aff182SThomas Petazzoni static void mvneta_rx_pkts_coal_set(struct mvneta_port *pp, 1254c5aff182SThomas Petazzoni struct mvneta_rx_queue *rxq, u32 value) 1255c5aff182SThomas Petazzoni { 1256c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_RXQ_THRESHOLD_REG(rxq->id), 1257c5aff182SThomas Petazzoni value | MVNETA_RXQ_NON_OCCUPIED(0)); 1258c5aff182SThomas Petazzoni rxq->pkts_coal = value; 1259c5aff182SThomas Petazzoni } 1260c5aff182SThomas Petazzoni 12616a20c175SThomas Petazzoni /* Set the time delay in usec before RX interrupt will be generated by 12626a20c175SThomas Petazzoni * HW. 1263c5aff182SThomas Petazzoni */ 1264c5aff182SThomas Petazzoni static void mvneta_rx_time_coal_set(struct mvneta_port *pp, 1265c5aff182SThomas Petazzoni struct mvneta_rx_queue *rxq, u32 value) 1266c5aff182SThomas Petazzoni { 1267189dd626SThomas Petazzoni u32 val; 1268189dd626SThomas Petazzoni unsigned long clk_rate; 1269189dd626SThomas Petazzoni 1270189dd626SThomas Petazzoni clk_rate = clk_get_rate(pp->clk); 1271189dd626SThomas Petazzoni val = (clk_rate / 1000000) * value; 1272c5aff182SThomas Petazzoni 1273c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_RXQ_TIME_COAL_REG(rxq->id), val); 1274c5aff182SThomas Petazzoni rxq->time_coal = value; 1275c5aff182SThomas Petazzoni } 1276c5aff182SThomas Petazzoni 1277c5aff182SThomas Petazzoni /* Set threshold for TX_DONE pkts coalescing */ 1278c5aff182SThomas Petazzoni static void mvneta_tx_done_pkts_coal_set(struct mvneta_port *pp, 1279c5aff182SThomas Petazzoni struct mvneta_tx_queue *txq, u32 value) 1280c5aff182SThomas Petazzoni { 1281c5aff182SThomas Petazzoni u32 val; 1282c5aff182SThomas Petazzoni 1283c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_TXQ_SIZE_REG(txq->id)); 1284c5aff182SThomas Petazzoni 1285c5aff182SThomas Petazzoni val &= ~MVNETA_TXQ_SENT_THRESH_ALL_MASK; 1286c5aff182SThomas Petazzoni val |= MVNETA_TXQ_SENT_THRESH_MASK(value); 1287c5aff182SThomas Petazzoni 1288c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_TXQ_SIZE_REG(txq->id), val); 1289c5aff182SThomas Petazzoni 1290c5aff182SThomas Petazzoni txq->done_pkts_coal = value; 1291c5aff182SThomas Petazzoni } 1292c5aff182SThomas Petazzoni 1293c5aff182SThomas Petazzoni /* Handle rx descriptor fill by setting buf_cookie and buf_phys_addr */ 1294c5aff182SThomas Petazzoni static void mvneta_rx_desc_fill(struct mvneta_rx_desc *rx_desc, 1295c5aff182SThomas Petazzoni u32 phys_addr, u32 cookie) 1296c5aff182SThomas Petazzoni { 1297c5aff182SThomas Petazzoni rx_desc->buf_cookie = cookie; 1298c5aff182SThomas Petazzoni rx_desc->buf_phys_addr = phys_addr; 1299c5aff182SThomas Petazzoni } 1300c5aff182SThomas Petazzoni 1301c5aff182SThomas Petazzoni /* Decrement sent descriptors counter */ 1302c5aff182SThomas Petazzoni static void mvneta_txq_sent_desc_dec(struct mvneta_port *pp, 1303c5aff182SThomas Petazzoni struct mvneta_tx_queue *txq, 1304c5aff182SThomas Petazzoni int sent_desc) 1305c5aff182SThomas Petazzoni { 1306c5aff182SThomas Petazzoni u32 val; 1307c5aff182SThomas Petazzoni 1308c5aff182SThomas Petazzoni /* Only 255 TX descriptors can be updated at once */ 1309c5aff182SThomas Petazzoni while (sent_desc > 0xff) { 1310c5aff182SThomas Petazzoni val = 0xff << MVNETA_TXQ_DEC_SENT_SHIFT; 1311c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val); 1312c5aff182SThomas Petazzoni sent_desc = sent_desc - 0xff; 1313c5aff182SThomas Petazzoni } 1314c5aff182SThomas Petazzoni 1315c5aff182SThomas Petazzoni val = sent_desc << MVNETA_TXQ_DEC_SENT_SHIFT; 1316c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val); 1317c5aff182SThomas Petazzoni } 1318c5aff182SThomas Petazzoni 1319c5aff182SThomas Petazzoni /* Get number of TX descriptors already sent by HW */ 1320c5aff182SThomas Petazzoni static int mvneta_txq_sent_desc_num_get(struct mvneta_port *pp, 1321c5aff182SThomas Petazzoni struct mvneta_tx_queue *txq) 1322c5aff182SThomas Petazzoni { 1323c5aff182SThomas Petazzoni u32 val; 1324c5aff182SThomas Petazzoni int sent_desc; 1325c5aff182SThomas Petazzoni 1326c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_TXQ_STATUS_REG(txq->id)); 1327c5aff182SThomas Petazzoni sent_desc = (val & MVNETA_TXQ_SENT_DESC_MASK) >> 1328c5aff182SThomas Petazzoni MVNETA_TXQ_SENT_DESC_SHIFT; 1329c5aff182SThomas Petazzoni 1330c5aff182SThomas Petazzoni return sent_desc; 1331c5aff182SThomas Petazzoni } 1332c5aff182SThomas Petazzoni 13336a20c175SThomas Petazzoni /* Get number of sent descriptors and decrement counter. 1334c5aff182SThomas Petazzoni * The number of sent descriptors is returned. 1335c5aff182SThomas Petazzoni */ 1336c5aff182SThomas Petazzoni static int mvneta_txq_sent_desc_proc(struct mvneta_port *pp, 1337c5aff182SThomas Petazzoni struct mvneta_tx_queue *txq) 1338c5aff182SThomas Petazzoni { 1339c5aff182SThomas Petazzoni int sent_desc; 1340c5aff182SThomas Petazzoni 1341c5aff182SThomas Petazzoni /* Get number of sent descriptors */ 1342c5aff182SThomas Petazzoni sent_desc = mvneta_txq_sent_desc_num_get(pp, txq); 1343c5aff182SThomas Petazzoni 1344c5aff182SThomas Petazzoni /* Decrement sent descriptors counter */ 1345c5aff182SThomas Petazzoni if (sent_desc) 1346c5aff182SThomas Petazzoni mvneta_txq_sent_desc_dec(pp, txq, sent_desc); 1347c5aff182SThomas Petazzoni 1348c5aff182SThomas Petazzoni return sent_desc; 1349c5aff182SThomas Petazzoni } 1350c5aff182SThomas Petazzoni 1351c5aff182SThomas Petazzoni /* Set TXQ descriptors fields relevant for CSUM calculation */ 1352c5aff182SThomas Petazzoni static u32 mvneta_txq_desc_csum(int l3_offs, int l3_proto, 1353c5aff182SThomas Petazzoni int ip_hdr_len, int l4_proto) 1354c5aff182SThomas Petazzoni { 1355c5aff182SThomas Petazzoni u32 command; 1356c5aff182SThomas Petazzoni 1357c5aff182SThomas Petazzoni /* Fields: L3_offset, IP_hdrlen, L3_type, G_IPv4_chk, 13586a20c175SThomas Petazzoni * G_L4_chk, L4_type; required only for checksum 13596a20c175SThomas Petazzoni * calculation 13606a20c175SThomas Petazzoni */ 1361c5aff182SThomas Petazzoni command = l3_offs << MVNETA_TX_L3_OFF_SHIFT; 1362c5aff182SThomas Petazzoni command |= ip_hdr_len << MVNETA_TX_IP_HLEN_SHIFT; 1363c5aff182SThomas Petazzoni 13640a198587SThomas Fitzsimmons if (l3_proto == htons(ETH_P_IP)) 1365c5aff182SThomas Petazzoni command |= MVNETA_TXD_IP_CSUM; 1366c5aff182SThomas Petazzoni else 1367c5aff182SThomas Petazzoni command |= MVNETA_TX_L3_IP6; 1368c5aff182SThomas Petazzoni 1369c5aff182SThomas Petazzoni if (l4_proto == IPPROTO_TCP) 1370c5aff182SThomas Petazzoni command |= MVNETA_TX_L4_CSUM_FULL; 1371c5aff182SThomas Petazzoni else if (l4_proto == IPPROTO_UDP) 1372c5aff182SThomas Petazzoni command |= MVNETA_TX_L4_UDP | MVNETA_TX_L4_CSUM_FULL; 1373c5aff182SThomas Petazzoni else 1374c5aff182SThomas Petazzoni command |= MVNETA_TX_L4_CSUM_NOT; 1375c5aff182SThomas Petazzoni 1376c5aff182SThomas Petazzoni return command; 1377c5aff182SThomas Petazzoni } 1378c5aff182SThomas Petazzoni 1379c5aff182SThomas Petazzoni 1380c5aff182SThomas Petazzoni /* Display more error info */ 1381c5aff182SThomas Petazzoni static void mvneta_rx_error(struct mvneta_port *pp, 1382c5aff182SThomas Petazzoni struct mvneta_rx_desc *rx_desc) 1383c5aff182SThomas Petazzoni { 1384c5aff182SThomas Petazzoni u32 status = rx_desc->status; 1385c5aff182SThomas Petazzoni 13865428213cSwilly tarreau if (!mvneta_rxq_desc_is_first_last(status)) { 1387c5aff182SThomas Petazzoni netdev_err(pp->dev, 1388c5aff182SThomas Petazzoni "bad rx status %08x (buffer oversize), size=%d\n", 13895428213cSwilly tarreau status, rx_desc->data_size); 1390c5aff182SThomas Petazzoni return; 1391c5aff182SThomas Petazzoni } 1392c5aff182SThomas Petazzoni 1393c5aff182SThomas Petazzoni switch (status & MVNETA_RXD_ERR_CODE_MASK) { 1394c5aff182SThomas Petazzoni case MVNETA_RXD_ERR_CRC: 1395c5aff182SThomas Petazzoni netdev_err(pp->dev, "bad rx status %08x (crc error), size=%d\n", 1396c5aff182SThomas Petazzoni status, rx_desc->data_size); 1397c5aff182SThomas Petazzoni break; 1398c5aff182SThomas Petazzoni case MVNETA_RXD_ERR_OVERRUN: 1399c5aff182SThomas Petazzoni netdev_err(pp->dev, "bad rx status %08x (overrun error), size=%d\n", 1400c5aff182SThomas Petazzoni status, rx_desc->data_size); 1401c5aff182SThomas Petazzoni break; 1402c5aff182SThomas Petazzoni case MVNETA_RXD_ERR_LEN: 1403c5aff182SThomas Petazzoni netdev_err(pp->dev, "bad rx status %08x (max frame length error), size=%d\n", 1404c5aff182SThomas Petazzoni status, rx_desc->data_size); 1405c5aff182SThomas Petazzoni break; 1406c5aff182SThomas Petazzoni case MVNETA_RXD_ERR_RESOURCE: 1407c5aff182SThomas Petazzoni netdev_err(pp->dev, "bad rx status %08x (resource error), size=%d\n", 1408c5aff182SThomas Petazzoni status, rx_desc->data_size); 1409c5aff182SThomas Petazzoni break; 1410c5aff182SThomas Petazzoni } 1411c5aff182SThomas Petazzoni } 1412c5aff182SThomas Petazzoni 14135428213cSwilly tarreau /* Handle RX checksum offload based on the descriptor's status */ 14145428213cSwilly tarreau static void mvneta_rx_csum(struct mvneta_port *pp, u32 status, 1415c5aff182SThomas Petazzoni struct sk_buff *skb) 1416c5aff182SThomas Petazzoni { 14175428213cSwilly tarreau if ((status & MVNETA_RXD_L3_IP4) && 14185428213cSwilly tarreau (status & MVNETA_RXD_L4_CSUM_OK)) { 1419c5aff182SThomas Petazzoni skb->csum = 0; 1420c5aff182SThomas Petazzoni skb->ip_summed = CHECKSUM_UNNECESSARY; 1421c5aff182SThomas Petazzoni return; 1422c5aff182SThomas Petazzoni } 1423c5aff182SThomas Petazzoni 1424c5aff182SThomas Petazzoni skb->ip_summed = CHECKSUM_NONE; 1425c5aff182SThomas Petazzoni } 1426c5aff182SThomas Petazzoni 14276c498974Swilly tarreau /* Return tx queue pointer (find last set bit) according to <cause> returned 14286c498974Swilly tarreau * form tx_done reg. <cause> must not be null. The return value is always a 14296c498974Swilly tarreau * valid queue for matching the first one found in <cause>. 14306c498974Swilly tarreau */ 1431c5aff182SThomas Petazzoni static struct mvneta_tx_queue *mvneta_tx_done_policy(struct mvneta_port *pp, 1432c5aff182SThomas Petazzoni u32 cause) 1433c5aff182SThomas Petazzoni { 1434c5aff182SThomas Petazzoni int queue = fls(cause) - 1; 1435c5aff182SThomas Petazzoni 14366c498974Swilly tarreau return &pp->txqs[queue]; 1437c5aff182SThomas Petazzoni } 1438c5aff182SThomas Petazzoni 1439c5aff182SThomas Petazzoni /* Free tx queue skbuffs */ 1440c5aff182SThomas Petazzoni static void mvneta_txq_bufs_free(struct mvneta_port *pp, 1441c5aff182SThomas Petazzoni struct mvneta_tx_queue *txq, int num) 1442c5aff182SThomas Petazzoni { 1443c5aff182SThomas Petazzoni int i; 1444c5aff182SThomas Petazzoni 1445c5aff182SThomas Petazzoni for (i = 0; i < num; i++) { 1446c5aff182SThomas Petazzoni struct mvneta_tx_desc *tx_desc = txq->descs + 1447c5aff182SThomas Petazzoni txq->txq_get_index; 1448c5aff182SThomas Petazzoni struct sk_buff *skb = txq->tx_skb[txq->txq_get_index]; 1449c5aff182SThomas Petazzoni 1450c5aff182SThomas Petazzoni mvneta_txq_inc_get(txq); 1451c5aff182SThomas Petazzoni 14522e3173a3SEzequiel Garcia if (!IS_TSO_HEADER(txq, tx_desc->buf_phys_addr)) 14532e3173a3SEzequiel Garcia dma_unmap_single(pp->dev->dev.parent, 14542e3173a3SEzequiel Garcia tx_desc->buf_phys_addr, 1455c5aff182SThomas Petazzoni tx_desc->data_size, DMA_TO_DEVICE); 1456ba7e46efSEzequiel Garcia if (!skb) 1457ba7e46efSEzequiel Garcia continue; 1458c5aff182SThomas Petazzoni dev_kfree_skb_any(skb); 1459c5aff182SThomas Petazzoni } 1460c5aff182SThomas Petazzoni } 1461c5aff182SThomas Petazzoni 1462c5aff182SThomas Petazzoni /* Handle end of transmission */ 1463cd713199SArnaud Ebalard static void mvneta_txq_done(struct mvneta_port *pp, 1464c5aff182SThomas Petazzoni struct mvneta_tx_queue *txq) 1465c5aff182SThomas Petazzoni { 1466c5aff182SThomas Petazzoni struct netdev_queue *nq = netdev_get_tx_queue(pp->dev, txq->id); 1467c5aff182SThomas Petazzoni int tx_done; 1468c5aff182SThomas Petazzoni 1469c5aff182SThomas Petazzoni tx_done = mvneta_txq_sent_desc_proc(pp, txq); 1470cd713199SArnaud Ebalard if (!tx_done) 1471cd713199SArnaud Ebalard return; 1472cd713199SArnaud Ebalard 1473c5aff182SThomas Petazzoni mvneta_txq_bufs_free(pp, txq, tx_done); 1474c5aff182SThomas Petazzoni 1475c5aff182SThomas Petazzoni txq->count -= tx_done; 1476c5aff182SThomas Petazzoni 1477c5aff182SThomas Petazzoni if (netif_tx_queue_stopped(nq)) { 14788eef5f97SEzequiel Garcia if (txq->count <= txq->tx_wake_threshold) 1479c5aff182SThomas Petazzoni netif_tx_wake_queue(nq); 1480c5aff182SThomas Petazzoni } 1481c5aff182SThomas Petazzoni } 1482c5aff182SThomas Petazzoni 14838ec2cd48Swilly tarreau static void *mvneta_frag_alloc(const struct mvneta_port *pp) 14848ec2cd48Swilly tarreau { 14858ec2cd48Swilly tarreau if (likely(pp->frag_size <= PAGE_SIZE)) 14868ec2cd48Swilly tarreau return netdev_alloc_frag(pp->frag_size); 14878ec2cd48Swilly tarreau else 14888ec2cd48Swilly tarreau return kmalloc(pp->frag_size, GFP_ATOMIC); 14898ec2cd48Swilly tarreau } 14908ec2cd48Swilly tarreau 14918ec2cd48Swilly tarreau static void mvneta_frag_free(const struct mvneta_port *pp, void *data) 14928ec2cd48Swilly tarreau { 14938ec2cd48Swilly tarreau if (likely(pp->frag_size <= PAGE_SIZE)) 149413dc0d2bSAlexander Duyck skb_free_frag(data); 14958ec2cd48Swilly tarreau else 14968ec2cd48Swilly tarreau kfree(data); 14978ec2cd48Swilly tarreau } 14988ec2cd48Swilly tarreau 1499c5aff182SThomas Petazzoni /* Refill processing */ 1500c5aff182SThomas Petazzoni static int mvneta_rx_refill(struct mvneta_port *pp, 1501c5aff182SThomas Petazzoni struct mvneta_rx_desc *rx_desc) 1502c5aff182SThomas Petazzoni 1503c5aff182SThomas Petazzoni { 1504c5aff182SThomas Petazzoni dma_addr_t phys_addr; 15058ec2cd48Swilly tarreau void *data; 1506c5aff182SThomas Petazzoni 15078ec2cd48Swilly tarreau data = mvneta_frag_alloc(pp); 15088ec2cd48Swilly tarreau if (!data) 1509c5aff182SThomas Petazzoni return -ENOMEM; 1510c5aff182SThomas Petazzoni 15118ec2cd48Swilly tarreau phys_addr = dma_map_single(pp->dev->dev.parent, data, 1512c5aff182SThomas Petazzoni MVNETA_RX_BUF_SIZE(pp->pkt_size), 1513c5aff182SThomas Petazzoni DMA_FROM_DEVICE); 1514c5aff182SThomas Petazzoni if (unlikely(dma_mapping_error(pp->dev->dev.parent, phys_addr))) { 15158ec2cd48Swilly tarreau mvneta_frag_free(pp, data); 1516c5aff182SThomas Petazzoni return -ENOMEM; 1517c5aff182SThomas Petazzoni } 1518c5aff182SThomas Petazzoni 15198ec2cd48Swilly tarreau mvneta_rx_desc_fill(rx_desc, phys_addr, (u32)data); 1520c5aff182SThomas Petazzoni return 0; 1521c5aff182SThomas Petazzoni } 1522c5aff182SThomas Petazzoni 1523c5aff182SThomas Petazzoni /* Handle tx checksum */ 1524c5aff182SThomas Petazzoni static u32 mvneta_skb_tx_csum(struct mvneta_port *pp, struct sk_buff *skb) 1525c5aff182SThomas Petazzoni { 1526c5aff182SThomas Petazzoni if (skb->ip_summed == CHECKSUM_PARTIAL) { 1527c5aff182SThomas Petazzoni int ip_hdr_len = 0; 1528817dbfa5SVlad Yasevich __be16 l3_proto = vlan_get_protocol(skb); 1529c5aff182SThomas Petazzoni u8 l4_proto; 1530c5aff182SThomas Petazzoni 1531817dbfa5SVlad Yasevich if (l3_proto == htons(ETH_P_IP)) { 1532c5aff182SThomas Petazzoni struct iphdr *ip4h = ip_hdr(skb); 1533c5aff182SThomas Petazzoni 1534c5aff182SThomas Petazzoni /* Calculate IPv4 checksum and L4 checksum */ 1535c5aff182SThomas Petazzoni ip_hdr_len = ip4h->ihl; 1536c5aff182SThomas Petazzoni l4_proto = ip4h->protocol; 1537817dbfa5SVlad Yasevich } else if (l3_proto == htons(ETH_P_IPV6)) { 1538c5aff182SThomas Petazzoni struct ipv6hdr *ip6h = ipv6_hdr(skb); 1539c5aff182SThomas Petazzoni 1540c5aff182SThomas Petazzoni /* Read l4_protocol from one of IPv6 extra headers */ 1541c5aff182SThomas Petazzoni if (skb_network_header_len(skb) > 0) 1542c5aff182SThomas Petazzoni ip_hdr_len = (skb_network_header_len(skb) >> 2); 1543c5aff182SThomas Petazzoni l4_proto = ip6h->nexthdr; 1544c5aff182SThomas Petazzoni } else 1545c5aff182SThomas Petazzoni return MVNETA_TX_L4_CSUM_NOT; 1546c5aff182SThomas Petazzoni 1547c5aff182SThomas Petazzoni return mvneta_txq_desc_csum(skb_network_offset(skb), 1548817dbfa5SVlad Yasevich l3_proto, ip_hdr_len, l4_proto); 1549c5aff182SThomas Petazzoni } 1550c5aff182SThomas Petazzoni 1551c5aff182SThomas Petazzoni return MVNETA_TX_L4_CSUM_NOT; 1552c5aff182SThomas Petazzoni } 1553c5aff182SThomas Petazzoni 1554c5aff182SThomas Petazzoni /* Drop packets received by the RXQ and free buffers */ 1555c5aff182SThomas Petazzoni static void mvneta_rxq_drop_pkts(struct mvneta_port *pp, 1556c5aff182SThomas Petazzoni struct mvneta_rx_queue *rxq) 1557c5aff182SThomas Petazzoni { 1558c5aff182SThomas Petazzoni int rx_done, i; 1559c5aff182SThomas Petazzoni 1560c5aff182SThomas Petazzoni rx_done = mvneta_rxq_busy_desc_num_get(pp, rxq); 1561c5aff182SThomas Petazzoni for (i = 0; i < rxq->size; i++) { 1562c5aff182SThomas Petazzoni struct mvneta_rx_desc *rx_desc = rxq->descs + i; 15638ec2cd48Swilly tarreau void *data = (void *)rx_desc->buf_cookie; 1564c5aff182SThomas Petazzoni 1565c5aff182SThomas Petazzoni dma_unmap_single(pp->dev->dev.parent, rx_desc->buf_phys_addr, 1566a328f3a0SEzequiel Garcia MVNETA_RX_BUF_SIZE(pp->pkt_size), DMA_FROM_DEVICE); 15678c94ddbcSJustin Maggard mvneta_frag_free(pp, data); 1568c5aff182SThomas Petazzoni } 1569c5aff182SThomas Petazzoni 1570c5aff182SThomas Petazzoni if (rx_done) 1571c5aff182SThomas Petazzoni mvneta_rxq_desc_num_update(pp, rxq, rx_done, rx_done); 1572c5aff182SThomas Petazzoni } 1573c5aff182SThomas Petazzoni 1574c5aff182SThomas Petazzoni /* Main rx processing */ 1575c5aff182SThomas Petazzoni static int mvneta_rx(struct mvneta_port *pp, int rx_todo, 1576c5aff182SThomas Petazzoni struct mvneta_rx_queue *rxq) 1577c5aff182SThomas Petazzoni { 157812bb03b4SMaxime Ripard struct mvneta_pcpu_port *port = this_cpu_ptr(pp->ports); 1579c5aff182SThomas Petazzoni struct net_device *dev = pp->dev; 1580a84e3289SSimon Guinot int rx_done; 1581dc4277ddSwilly tarreau u32 rcvd_pkts = 0; 1582dc4277ddSwilly tarreau u32 rcvd_bytes = 0; 1583c5aff182SThomas Petazzoni 1584c5aff182SThomas Petazzoni /* Get number of received packets */ 1585c5aff182SThomas Petazzoni rx_done = mvneta_rxq_busy_desc_num_get(pp, rxq); 1586c5aff182SThomas Petazzoni 1587c5aff182SThomas Petazzoni if (rx_todo > rx_done) 1588c5aff182SThomas Petazzoni rx_todo = rx_done; 1589c5aff182SThomas Petazzoni 1590c5aff182SThomas Petazzoni rx_done = 0; 1591c5aff182SThomas Petazzoni 1592c5aff182SThomas Petazzoni /* Fairness NAPI loop */ 1593c5aff182SThomas Petazzoni while (rx_done < rx_todo) { 1594c5aff182SThomas Petazzoni struct mvneta_rx_desc *rx_desc = mvneta_rxq_next_desc_get(rxq); 1595c5aff182SThomas Petazzoni struct sk_buff *skb; 15968ec2cd48Swilly tarreau unsigned char *data; 1597daf158d0SSimon Guinot dma_addr_t phys_addr; 1598c5aff182SThomas Petazzoni u32 rx_status; 1599c5aff182SThomas Petazzoni int rx_bytes, err; 1600c5aff182SThomas Petazzoni 1601c5aff182SThomas Petazzoni rx_done++; 1602c5aff182SThomas Petazzoni rx_status = rx_desc->status; 1603f19fadfcSwilly tarreau rx_bytes = rx_desc->data_size - (ETH_FCS_LEN + MVNETA_MH_SIZE); 16048ec2cd48Swilly tarreau data = (unsigned char *)rx_desc->buf_cookie; 1605daf158d0SSimon Guinot phys_addr = rx_desc->buf_phys_addr; 1606c5aff182SThomas Petazzoni 16075428213cSwilly tarreau if (!mvneta_rxq_desc_is_first_last(rx_status) || 1608f19fadfcSwilly tarreau (rx_status & MVNETA_RXD_ERR_SUMMARY)) { 1609f19fadfcSwilly tarreau err_drop_frame: 1610c5aff182SThomas Petazzoni dev->stats.rx_errors++; 1611c5aff182SThomas Petazzoni mvneta_rx_error(pp, rx_desc); 16128ec2cd48Swilly tarreau /* leave the descriptor untouched */ 1613c5aff182SThomas Petazzoni continue; 1614c5aff182SThomas Petazzoni } 1615c5aff182SThomas Petazzoni 1616f19fadfcSwilly tarreau if (rx_bytes <= rx_copybreak) { 1617f19fadfcSwilly tarreau /* better copy a small frame and not unmap the DMA region */ 1618f19fadfcSwilly tarreau skb = netdev_alloc_skb_ip_align(dev, rx_bytes); 1619f19fadfcSwilly tarreau if (unlikely(!skb)) 1620f19fadfcSwilly tarreau goto err_drop_frame; 1621f19fadfcSwilly tarreau 1622f19fadfcSwilly tarreau dma_sync_single_range_for_cpu(dev->dev.parent, 1623f19fadfcSwilly tarreau rx_desc->buf_phys_addr, 1624f19fadfcSwilly tarreau MVNETA_MH_SIZE + NET_SKB_PAD, 1625f19fadfcSwilly tarreau rx_bytes, 1626f19fadfcSwilly tarreau DMA_FROM_DEVICE); 1627f19fadfcSwilly tarreau memcpy(skb_put(skb, rx_bytes), 1628f19fadfcSwilly tarreau data + MVNETA_MH_SIZE + NET_SKB_PAD, 1629f19fadfcSwilly tarreau rx_bytes); 1630f19fadfcSwilly tarreau 1631f19fadfcSwilly tarreau skb->protocol = eth_type_trans(skb, dev); 1632f19fadfcSwilly tarreau mvneta_rx_csum(pp, rx_status, skb); 163312bb03b4SMaxime Ripard napi_gro_receive(&port->napi, skb); 1634f19fadfcSwilly tarreau 1635f19fadfcSwilly tarreau rcvd_pkts++; 1636f19fadfcSwilly tarreau rcvd_bytes += rx_bytes; 1637f19fadfcSwilly tarreau 1638f19fadfcSwilly tarreau /* leave the descriptor and buffer untouched */ 1639f19fadfcSwilly tarreau continue; 1640f19fadfcSwilly tarreau } 1641f19fadfcSwilly tarreau 1642a84e3289SSimon Guinot /* Refill processing */ 1643a84e3289SSimon Guinot err = mvneta_rx_refill(pp, rx_desc); 1644a84e3289SSimon Guinot if (err) { 1645a84e3289SSimon Guinot netdev_err(dev, "Linux processing - Can't refill\n"); 1646a84e3289SSimon Guinot rxq->missed++; 1647a84e3289SSimon Guinot goto err_drop_frame; 1648a84e3289SSimon Guinot } 1649a84e3289SSimon Guinot 1650f19fadfcSwilly tarreau skb = build_skb(data, pp->frag_size > PAGE_SIZE ? 0 : pp->frag_size); 1651f19fadfcSwilly tarreau 165226c17a17SMarcin Wojtas /* After refill old buffer has to be unmapped regardless 165326c17a17SMarcin Wojtas * the skb is successfully built or not. 165426c17a17SMarcin Wojtas */ 1655daf158d0SSimon Guinot dma_unmap_single(dev->dev.parent, phys_addr, 1656a328f3a0SEzequiel Garcia MVNETA_RX_BUF_SIZE(pp->pkt_size), DMA_FROM_DEVICE); 1657c5aff182SThomas Petazzoni 165826c17a17SMarcin Wojtas if (!skb) 165926c17a17SMarcin Wojtas goto err_drop_frame; 166026c17a17SMarcin Wojtas 1661dc4277ddSwilly tarreau rcvd_pkts++; 1662dc4277ddSwilly tarreau rcvd_bytes += rx_bytes; 1663c5aff182SThomas Petazzoni 1664c5aff182SThomas Petazzoni /* Linux processing */ 16658ec2cd48Swilly tarreau skb_reserve(skb, MVNETA_MH_SIZE + NET_SKB_PAD); 1666c5aff182SThomas Petazzoni skb_put(skb, rx_bytes); 1667c5aff182SThomas Petazzoni 1668c5aff182SThomas Petazzoni skb->protocol = eth_type_trans(skb, dev); 1669c5aff182SThomas Petazzoni 16705428213cSwilly tarreau mvneta_rx_csum(pp, rx_status, skb); 1671c5aff182SThomas Petazzoni 167212bb03b4SMaxime Ripard napi_gro_receive(&port->napi, skb); 1673c5aff182SThomas Petazzoni } 1674c5aff182SThomas Petazzoni 1675dc4277ddSwilly tarreau if (rcvd_pkts) { 167674c41b04Swilly tarreau struct mvneta_pcpu_stats *stats = this_cpu_ptr(pp->stats); 167774c41b04Swilly tarreau 167874c41b04Swilly tarreau u64_stats_update_begin(&stats->syncp); 167974c41b04Swilly tarreau stats->rx_packets += rcvd_pkts; 168074c41b04Swilly tarreau stats->rx_bytes += rcvd_bytes; 168174c41b04Swilly tarreau u64_stats_update_end(&stats->syncp); 1682dc4277ddSwilly tarreau } 1683dc4277ddSwilly tarreau 1684c5aff182SThomas Petazzoni /* Update rxq management counters */ 1685a84e3289SSimon Guinot mvneta_rxq_desc_num_update(pp, rxq, rx_done, rx_done); 1686c5aff182SThomas Petazzoni 1687c5aff182SThomas Petazzoni return rx_done; 1688c5aff182SThomas Petazzoni } 1689c5aff182SThomas Petazzoni 16902adb719dSEzequiel Garcia static inline void 16912adb719dSEzequiel Garcia mvneta_tso_put_hdr(struct sk_buff *skb, 16922adb719dSEzequiel Garcia struct mvneta_port *pp, struct mvneta_tx_queue *txq) 16932adb719dSEzequiel Garcia { 16942adb719dSEzequiel Garcia struct mvneta_tx_desc *tx_desc; 16952adb719dSEzequiel Garcia int hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb); 16962adb719dSEzequiel Garcia 16972adb719dSEzequiel Garcia txq->tx_skb[txq->txq_put_index] = NULL; 16982adb719dSEzequiel Garcia tx_desc = mvneta_txq_next_desc_get(txq); 16992adb719dSEzequiel Garcia tx_desc->data_size = hdr_len; 17002adb719dSEzequiel Garcia tx_desc->command = mvneta_skb_tx_csum(pp, skb); 17012adb719dSEzequiel Garcia tx_desc->command |= MVNETA_TXD_F_DESC; 17022adb719dSEzequiel Garcia tx_desc->buf_phys_addr = txq->tso_hdrs_phys + 17032adb719dSEzequiel Garcia txq->txq_put_index * TSO_HEADER_SIZE; 17042adb719dSEzequiel Garcia mvneta_txq_inc_put(txq); 17052adb719dSEzequiel Garcia } 17062adb719dSEzequiel Garcia 17072adb719dSEzequiel Garcia static inline int 17082adb719dSEzequiel Garcia mvneta_tso_put_data(struct net_device *dev, struct mvneta_tx_queue *txq, 17092adb719dSEzequiel Garcia struct sk_buff *skb, char *data, int size, 17102adb719dSEzequiel Garcia bool last_tcp, bool is_last) 17112adb719dSEzequiel Garcia { 17122adb719dSEzequiel Garcia struct mvneta_tx_desc *tx_desc; 17132adb719dSEzequiel Garcia 17142adb719dSEzequiel Garcia tx_desc = mvneta_txq_next_desc_get(txq); 17152adb719dSEzequiel Garcia tx_desc->data_size = size; 17162adb719dSEzequiel Garcia tx_desc->buf_phys_addr = dma_map_single(dev->dev.parent, data, 17172adb719dSEzequiel Garcia size, DMA_TO_DEVICE); 17182adb719dSEzequiel Garcia if (unlikely(dma_mapping_error(dev->dev.parent, 17192adb719dSEzequiel Garcia tx_desc->buf_phys_addr))) { 17202adb719dSEzequiel Garcia mvneta_txq_desc_put(txq); 17212adb719dSEzequiel Garcia return -ENOMEM; 17222adb719dSEzequiel Garcia } 17232adb719dSEzequiel Garcia 17242adb719dSEzequiel Garcia tx_desc->command = 0; 17252adb719dSEzequiel Garcia txq->tx_skb[txq->txq_put_index] = NULL; 17262adb719dSEzequiel Garcia 17272adb719dSEzequiel Garcia if (last_tcp) { 17282adb719dSEzequiel Garcia /* last descriptor in the TCP packet */ 17292adb719dSEzequiel Garcia tx_desc->command = MVNETA_TXD_L_DESC; 17302adb719dSEzequiel Garcia 17312adb719dSEzequiel Garcia /* last descriptor in SKB */ 17322adb719dSEzequiel Garcia if (is_last) 17332adb719dSEzequiel Garcia txq->tx_skb[txq->txq_put_index] = skb; 17342adb719dSEzequiel Garcia } 17352adb719dSEzequiel Garcia mvneta_txq_inc_put(txq); 17362adb719dSEzequiel Garcia return 0; 17372adb719dSEzequiel Garcia } 17382adb719dSEzequiel Garcia 17392adb719dSEzequiel Garcia static int mvneta_tx_tso(struct sk_buff *skb, struct net_device *dev, 17402adb719dSEzequiel Garcia struct mvneta_tx_queue *txq) 17412adb719dSEzequiel Garcia { 17422adb719dSEzequiel Garcia int total_len, data_left; 17432adb719dSEzequiel Garcia int desc_count = 0; 17442adb719dSEzequiel Garcia struct mvneta_port *pp = netdev_priv(dev); 17452adb719dSEzequiel Garcia struct tso_t tso; 17462adb719dSEzequiel Garcia int hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb); 17472adb719dSEzequiel Garcia int i; 17482adb719dSEzequiel Garcia 17492adb719dSEzequiel Garcia /* Count needed descriptors */ 17502adb719dSEzequiel Garcia if ((txq->count + tso_count_descs(skb)) >= txq->size) 17512adb719dSEzequiel Garcia return 0; 17522adb719dSEzequiel Garcia 17532adb719dSEzequiel Garcia if (skb_headlen(skb) < (skb_transport_offset(skb) + tcp_hdrlen(skb))) { 17542adb719dSEzequiel Garcia pr_info("*** Is this even possible???!?!?\n"); 17552adb719dSEzequiel Garcia return 0; 17562adb719dSEzequiel Garcia } 17572adb719dSEzequiel Garcia 17582adb719dSEzequiel Garcia /* Initialize the TSO handler, and prepare the first payload */ 17592adb719dSEzequiel Garcia tso_start(skb, &tso); 17602adb719dSEzequiel Garcia 17612adb719dSEzequiel Garcia total_len = skb->len - hdr_len; 17622adb719dSEzequiel Garcia while (total_len > 0) { 17632adb719dSEzequiel Garcia char *hdr; 17642adb719dSEzequiel Garcia 17652adb719dSEzequiel Garcia data_left = min_t(int, skb_shinfo(skb)->gso_size, total_len); 17662adb719dSEzequiel Garcia total_len -= data_left; 17672adb719dSEzequiel Garcia desc_count++; 17682adb719dSEzequiel Garcia 17692adb719dSEzequiel Garcia /* prepare packet headers: MAC + IP + TCP */ 17702adb719dSEzequiel Garcia hdr = txq->tso_hdrs + txq->txq_put_index * TSO_HEADER_SIZE; 17712adb719dSEzequiel Garcia tso_build_hdr(skb, hdr, &tso, data_left, total_len == 0); 17722adb719dSEzequiel Garcia 17732adb719dSEzequiel Garcia mvneta_tso_put_hdr(skb, pp, txq); 17742adb719dSEzequiel Garcia 17752adb719dSEzequiel Garcia while (data_left > 0) { 17762adb719dSEzequiel Garcia int size; 17772adb719dSEzequiel Garcia desc_count++; 17782adb719dSEzequiel Garcia 17792adb719dSEzequiel Garcia size = min_t(int, tso.size, data_left); 17802adb719dSEzequiel Garcia 17812adb719dSEzequiel Garcia if (mvneta_tso_put_data(dev, txq, skb, 17822adb719dSEzequiel Garcia tso.data, size, 17832adb719dSEzequiel Garcia size == data_left, 17842adb719dSEzequiel Garcia total_len == 0)) 17852adb719dSEzequiel Garcia goto err_release; 17862adb719dSEzequiel Garcia data_left -= size; 17872adb719dSEzequiel Garcia 17882adb719dSEzequiel Garcia tso_build_data(skb, &tso, size); 17892adb719dSEzequiel Garcia } 17902adb719dSEzequiel Garcia } 17912adb719dSEzequiel Garcia 17922adb719dSEzequiel Garcia return desc_count; 17932adb719dSEzequiel Garcia 17942adb719dSEzequiel Garcia err_release: 17952adb719dSEzequiel Garcia /* Release all used data descriptors; header descriptors must not 17962adb719dSEzequiel Garcia * be DMA-unmapped. 17972adb719dSEzequiel Garcia */ 17982adb719dSEzequiel Garcia for (i = desc_count - 1; i >= 0; i--) { 17992adb719dSEzequiel Garcia struct mvneta_tx_desc *tx_desc = txq->descs + i; 18002e3173a3SEzequiel Garcia if (!IS_TSO_HEADER(txq, tx_desc->buf_phys_addr)) 18012adb719dSEzequiel Garcia dma_unmap_single(pp->dev->dev.parent, 18022adb719dSEzequiel Garcia tx_desc->buf_phys_addr, 18032adb719dSEzequiel Garcia tx_desc->data_size, 18042adb719dSEzequiel Garcia DMA_TO_DEVICE); 18052adb719dSEzequiel Garcia mvneta_txq_desc_put(txq); 18062adb719dSEzequiel Garcia } 18072adb719dSEzequiel Garcia return 0; 18082adb719dSEzequiel Garcia } 18092adb719dSEzequiel Garcia 1810c5aff182SThomas Petazzoni /* Handle tx fragmentation processing */ 1811c5aff182SThomas Petazzoni static int mvneta_tx_frag_process(struct mvneta_port *pp, struct sk_buff *skb, 1812c5aff182SThomas Petazzoni struct mvneta_tx_queue *txq) 1813c5aff182SThomas Petazzoni { 1814c5aff182SThomas Petazzoni struct mvneta_tx_desc *tx_desc; 18153d4ea02fSEzequiel Garcia int i, nr_frags = skb_shinfo(skb)->nr_frags; 1816c5aff182SThomas Petazzoni 18173d4ea02fSEzequiel Garcia for (i = 0; i < nr_frags; i++) { 1818c5aff182SThomas Petazzoni skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 1819c5aff182SThomas Petazzoni void *addr = page_address(frag->page.p) + frag->page_offset; 1820c5aff182SThomas Petazzoni 1821c5aff182SThomas Petazzoni tx_desc = mvneta_txq_next_desc_get(txq); 1822c5aff182SThomas Petazzoni tx_desc->data_size = frag->size; 1823c5aff182SThomas Petazzoni 1824c5aff182SThomas Petazzoni tx_desc->buf_phys_addr = 1825c5aff182SThomas Petazzoni dma_map_single(pp->dev->dev.parent, addr, 1826c5aff182SThomas Petazzoni tx_desc->data_size, DMA_TO_DEVICE); 1827c5aff182SThomas Petazzoni 1828c5aff182SThomas Petazzoni if (dma_mapping_error(pp->dev->dev.parent, 1829c5aff182SThomas Petazzoni tx_desc->buf_phys_addr)) { 1830c5aff182SThomas Petazzoni mvneta_txq_desc_put(txq); 1831c5aff182SThomas Petazzoni goto error; 1832c5aff182SThomas Petazzoni } 1833c5aff182SThomas Petazzoni 18343d4ea02fSEzequiel Garcia if (i == nr_frags - 1) { 1835c5aff182SThomas Petazzoni /* Last descriptor */ 1836c5aff182SThomas Petazzoni tx_desc->command = MVNETA_TXD_L_DESC | MVNETA_TXD_Z_PAD; 1837c5aff182SThomas Petazzoni txq->tx_skb[txq->txq_put_index] = skb; 1838c5aff182SThomas Petazzoni } else { 1839c5aff182SThomas Petazzoni /* Descriptor in the middle: Not First, Not Last */ 1840c5aff182SThomas Petazzoni tx_desc->command = 0; 1841c5aff182SThomas Petazzoni txq->tx_skb[txq->txq_put_index] = NULL; 1842c5aff182SThomas Petazzoni } 18433d4ea02fSEzequiel Garcia mvneta_txq_inc_put(txq); 1844c5aff182SThomas Petazzoni } 1845c5aff182SThomas Petazzoni 1846c5aff182SThomas Petazzoni return 0; 1847c5aff182SThomas Petazzoni 1848c5aff182SThomas Petazzoni error: 1849c5aff182SThomas Petazzoni /* Release all descriptors that were used to map fragments of 18506a20c175SThomas Petazzoni * this packet, as well as the corresponding DMA mappings 18516a20c175SThomas Petazzoni */ 1852c5aff182SThomas Petazzoni for (i = i - 1; i >= 0; i--) { 1853c5aff182SThomas Petazzoni tx_desc = txq->descs + i; 1854c5aff182SThomas Petazzoni dma_unmap_single(pp->dev->dev.parent, 1855c5aff182SThomas Petazzoni tx_desc->buf_phys_addr, 1856c5aff182SThomas Petazzoni tx_desc->data_size, 1857c5aff182SThomas Petazzoni DMA_TO_DEVICE); 1858c5aff182SThomas Petazzoni mvneta_txq_desc_put(txq); 1859c5aff182SThomas Petazzoni } 1860c5aff182SThomas Petazzoni 1861c5aff182SThomas Petazzoni return -ENOMEM; 1862c5aff182SThomas Petazzoni } 1863c5aff182SThomas Petazzoni 1864c5aff182SThomas Petazzoni /* Main tx processing */ 1865c5aff182SThomas Petazzoni static int mvneta_tx(struct sk_buff *skb, struct net_device *dev) 1866c5aff182SThomas Petazzoni { 1867c5aff182SThomas Petazzoni struct mvneta_port *pp = netdev_priv(dev); 1868ee40a116SWilly Tarreau u16 txq_id = skb_get_queue_mapping(skb); 1869ee40a116SWilly Tarreau struct mvneta_tx_queue *txq = &pp->txqs[txq_id]; 1870c5aff182SThomas Petazzoni struct mvneta_tx_desc *tx_desc; 18715f478b41SEric Dumazet int len = skb->len; 1872c5aff182SThomas Petazzoni int frags = 0; 1873c5aff182SThomas Petazzoni u32 tx_cmd; 1874c5aff182SThomas Petazzoni 1875c5aff182SThomas Petazzoni if (!netif_running(dev)) 1876c5aff182SThomas Petazzoni goto out; 1877c5aff182SThomas Petazzoni 18782adb719dSEzequiel Garcia if (skb_is_gso(skb)) { 18792adb719dSEzequiel Garcia frags = mvneta_tx_tso(skb, dev, txq); 18802adb719dSEzequiel Garcia goto out; 18812adb719dSEzequiel Garcia } 18822adb719dSEzequiel Garcia 1883c5aff182SThomas Petazzoni frags = skb_shinfo(skb)->nr_frags + 1; 1884c5aff182SThomas Petazzoni 1885c5aff182SThomas Petazzoni /* Get a descriptor for the first part of the packet */ 1886c5aff182SThomas Petazzoni tx_desc = mvneta_txq_next_desc_get(txq); 1887c5aff182SThomas Petazzoni 1888c5aff182SThomas Petazzoni tx_cmd = mvneta_skb_tx_csum(pp, skb); 1889c5aff182SThomas Petazzoni 1890c5aff182SThomas Petazzoni tx_desc->data_size = skb_headlen(skb); 1891c5aff182SThomas Petazzoni 1892c5aff182SThomas Petazzoni tx_desc->buf_phys_addr = dma_map_single(dev->dev.parent, skb->data, 1893c5aff182SThomas Petazzoni tx_desc->data_size, 1894c5aff182SThomas Petazzoni DMA_TO_DEVICE); 1895c5aff182SThomas Petazzoni if (unlikely(dma_mapping_error(dev->dev.parent, 1896c5aff182SThomas Petazzoni tx_desc->buf_phys_addr))) { 1897c5aff182SThomas Petazzoni mvneta_txq_desc_put(txq); 1898c5aff182SThomas Petazzoni frags = 0; 1899c5aff182SThomas Petazzoni goto out; 1900c5aff182SThomas Petazzoni } 1901c5aff182SThomas Petazzoni 1902c5aff182SThomas Petazzoni if (frags == 1) { 1903c5aff182SThomas Petazzoni /* First and Last descriptor */ 1904c5aff182SThomas Petazzoni tx_cmd |= MVNETA_TXD_FLZ_DESC; 1905c5aff182SThomas Petazzoni tx_desc->command = tx_cmd; 1906c5aff182SThomas Petazzoni txq->tx_skb[txq->txq_put_index] = skb; 1907c5aff182SThomas Petazzoni mvneta_txq_inc_put(txq); 1908c5aff182SThomas Petazzoni } else { 1909c5aff182SThomas Petazzoni /* First but not Last */ 1910c5aff182SThomas Petazzoni tx_cmd |= MVNETA_TXD_F_DESC; 1911c5aff182SThomas Petazzoni txq->tx_skb[txq->txq_put_index] = NULL; 1912c5aff182SThomas Petazzoni mvneta_txq_inc_put(txq); 1913c5aff182SThomas Petazzoni tx_desc->command = tx_cmd; 1914c5aff182SThomas Petazzoni /* Continue with other skb fragments */ 1915c5aff182SThomas Petazzoni if (mvneta_tx_frag_process(pp, skb, txq)) { 1916c5aff182SThomas Petazzoni dma_unmap_single(dev->dev.parent, 1917c5aff182SThomas Petazzoni tx_desc->buf_phys_addr, 1918c5aff182SThomas Petazzoni tx_desc->data_size, 1919c5aff182SThomas Petazzoni DMA_TO_DEVICE); 1920c5aff182SThomas Petazzoni mvneta_txq_desc_put(txq); 1921c5aff182SThomas Petazzoni frags = 0; 1922c5aff182SThomas Petazzoni goto out; 1923c5aff182SThomas Petazzoni } 1924c5aff182SThomas Petazzoni } 1925c5aff182SThomas Petazzoni 1926e19d2ddaSEzequiel Garcia out: 1927e19d2ddaSEzequiel Garcia if (frags > 0) { 1928e19d2ddaSEzequiel Garcia struct mvneta_pcpu_stats *stats = this_cpu_ptr(pp->stats); 1929e19d2ddaSEzequiel Garcia struct netdev_queue *nq = netdev_get_tx_queue(dev, txq_id); 1930e19d2ddaSEzequiel Garcia 1931c5aff182SThomas Petazzoni txq->count += frags; 1932c5aff182SThomas Petazzoni mvneta_txq_pend_desc_add(pp, txq, frags); 1933c5aff182SThomas Petazzoni 19348eef5f97SEzequiel Garcia if (txq->count >= txq->tx_stop_threshold) 1935c5aff182SThomas Petazzoni netif_tx_stop_queue(nq); 1936c5aff182SThomas Petazzoni 193774c41b04Swilly tarreau u64_stats_update_begin(&stats->syncp); 193874c41b04Swilly tarreau stats->tx_packets++; 19395f478b41SEric Dumazet stats->tx_bytes += len; 194074c41b04Swilly tarreau u64_stats_update_end(&stats->syncp); 1941c5aff182SThomas Petazzoni } else { 1942c5aff182SThomas Petazzoni dev->stats.tx_dropped++; 1943c5aff182SThomas Petazzoni dev_kfree_skb_any(skb); 1944c5aff182SThomas Petazzoni } 1945c5aff182SThomas Petazzoni 1946c5aff182SThomas Petazzoni return NETDEV_TX_OK; 1947c5aff182SThomas Petazzoni } 1948c5aff182SThomas Petazzoni 1949c5aff182SThomas Petazzoni 1950c5aff182SThomas Petazzoni /* Free tx resources, when resetting a port */ 1951c5aff182SThomas Petazzoni static void mvneta_txq_done_force(struct mvneta_port *pp, 1952c5aff182SThomas Petazzoni struct mvneta_tx_queue *txq) 1953c5aff182SThomas Petazzoni 1954c5aff182SThomas Petazzoni { 1955c5aff182SThomas Petazzoni int tx_done = txq->count; 1956c5aff182SThomas Petazzoni 1957c5aff182SThomas Petazzoni mvneta_txq_bufs_free(pp, txq, tx_done); 1958c5aff182SThomas Petazzoni 1959c5aff182SThomas Petazzoni /* reset txq */ 1960c5aff182SThomas Petazzoni txq->count = 0; 1961c5aff182SThomas Petazzoni txq->txq_put_index = 0; 1962c5aff182SThomas Petazzoni txq->txq_get_index = 0; 1963c5aff182SThomas Petazzoni } 1964c5aff182SThomas Petazzoni 19656c498974Swilly tarreau /* Handle tx done - called in softirq context. The <cause_tx_done> argument 19666c498974Swilly tarreau * must be a valid cause according to MVNETA_TXQ_INTR_MASK_ALL. 19676c498974Swilly tarreau */ 19680713a86aSArnaud Ebalard static void mvneta_tx_done_gbe(struct mvneta_port *pp, u32 cause_tx_done) 1969c5aff182SThomas Petazzoni { 1970c5aff182SThomas Petazzoni struct mvneta_tx_queue *txq; 1971c5aff182SThomas Petazzoni struct netdev_queue *nq; 1972c5aff182SThomas Petazzoni 19736c498974Swilly tarreau while (cause_tx_done) { 1974c5aff182SThomas Petazzoni txq = mvneta_tx_done_policy(pp, cause_tx_done); 1975c5aff182SThomas Petazzoni 1976c5aff182SThomas Petazzoni nq = netdev_get_tx_queue(pp->dev, txq->id); 1977c5aff182SThomas Petazzoni __netif_tx_lock(nq, smp_processor_id()); 1978c5aff182SThomas Petazzoni 19790713a86aSArnaud Ebalard if (txq->count) 19800713a86aSArnaud Ebalard mvneta_txq_done(pp, txq); 1981c5aff182SThomas Petazzoni 1982c5aff182SThomas Petazzoni __netif_tx_unlock(nq); 1983c5aff182SThomas Petazzoni cause_tx_done &= ~((1 << txq->id)); 1984c5aff182SThomas Petazzoni } 1985c5aff182SThomas Petazzoni } 1986c5aff182SThomas Petazzoni 19876a20c175SThomas Petazzoni /* Compute crc8 of the specified address, using a unique algorithm , 1988c5aff182SThomas Petazzoni * according to hw spec, different than generic crc8 algorithm 1989c5aff182SThomas Petazzoni */ 1990c5aff182SThomas Petazzoni static int mvneta_addr_crc(unsigned char *addr) 1991c5aff182SThomas Petazzoni { 1992c5aff182SThomas Petazzoni int crc = 0; 1993c5aff182SThomas Petazzoni int i; 1994c5aff182SThomas Petazzoni 1995c5aff182SThomas Petazzoni for (i = 0; i < ETH_ALEN; i++) { 1996c5aff182SThomas Petazzoni int j; 1997c5aff182SThomas Petazzoni 1998c5aff182SThomas Petazzoni crc = (crc ^ addr[i]) << 8; 1999c5aff182SThomas Petazzoni for (j = 7; j >= 0; j--) { 2000c5aff182SThomas Petazzoni if (crc & (0x100 << j)) 2001c5aff182SThomas Petazzoni crc ^= 0x107 << j; 2002c5aff182SThomas Petazzoni } 2003c5aff182SThomas Petazzoni } 2004c5aff182SThomas Petazzoni 2005c5aff182SThomas Petazzoni return crc; 2006c5aff182SThomas Petazzoni } 2007c5aff182SThomas Petazzoni 2008c5aff182SThomas Petazzoni /* This method controls the net device special MAC multicast support. 2009c5aff182SThomas Petazzoni * The Special Multicast Table for MAC addresses supports MAC of the form 2010c5aff182SThomas Petazzoni * 0x01-00-5E-00-00-XX (where XX is between 0x00 and 0xFF). 2011c5aff182SThomas Petazzoni * The MAC DA[7:0] bits are used as a pointer to the Special Multicast 2012c5aff182SThomas Petazzoni * Table entries in the DA-Filter table. This method set the Special 2013c5aff182SThomas Petazzoni * Multicast Table appropriate entry. 2014c5aff182SThomas Petazzoni */ 2015c5aff182SThomas Petazzoni static void mvneta_set_special_mcast_addr(struct mvneta_port *pp, 2016c5aff182SThomas Petazzoni unsigned char last_byte, 2017c5aff182SThomas Petazzoni int queue) 2018c5aff182SThomas Petazzoni { 2019c5aff182SThomas Petazzoni unsigned int smc_table_reg; 2020c5aff182SThomas Petazzoni unsigned int tbl_offset; 2021c5aff182SThomas Petazzoni unsigned int reg_offset; 2022c5aff182SThomas Petazzoni 2023c5aff182SThomas Petazzoni /* Register offset from SMC table base */ 2024c5aff182SThomas Petazzoni tbl_offset = (last_byte / 4); 2025c5aff182SThomas Petazzoni /* Entry offset within the above reg */ 2026c5aff182SThomas Petazzoni reg_offset = last_byte % 4; 2027c5aff182SThomas Petazzoni 2028c5aff182SThomas Petazzoni smc_table_reg = mvreg_read(pp, (MVNETA_DA_FILT_SPEC_MCAST 2029c5aff182SThomas Petazzoni + tbl_offset * 4)); 2030c5aff182SThomas Petazzoni 2031c5aff182SThomas Petazzoni if (queue == -1) 2032c5aff182SThomas Petazzoni smc_table_reg &= ~(0xff << (8 * reg_offset)); 2033c5aff182SThomas Petazzoni else { 2034c5aff182SThomas Petazzoni smc_table_reg &= ~(0xff << (8 * reg_offset)); 2035c5aff182SThomas Petazzoni smc_table_reg |= ((0x01 | (queue << 1)) << (8 * reg_offset)); 2036c5aff182SThomas Petazzoni } 2037c5aff182SThomas Petazzoni 2038c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_DA_FILT_SPEC_MCAST + tbl_offset * 4, 2039c5aff182SThomas Petazzoni smc_table_reg); 2040c5aff182SThomas Petazzoni } 2041c5aff182SThomas Petazzoni 2042c5aff182SThomas Petazzoni /* This method controls the network device Other MAC multicast support. 2043c5aff182SThomas Petazzoni * The Other Multicast Table is used for multicast of another type. 2044c5aff182SThomas Petazzoni * A CRC-8 is used as an index to the Other Multicast Table entries 2045c5aff182SThomas Petazzoni * in the DA-Filter table. 2046c5aff182SThomas Petazzoni * The method gets the CRC-8 value from the calling routine and 2047c5aff182SThomas Petazzoni * sets the Other Multicast Table appropriate entry according to the 2048c5aff182SThomas Petazzoni * specified CRC-8 . 2049c5aff182SThomas Petazzoni */ 2050c5aff182SThomas Petazzoni static void mvneta_set_other_mcast_addr(struct mvneta_port *pp, 2051c5aff182SThomas Petazzoni unsigned char crc8, 2052c5aff182SThomas Petazzoni int queue) 2053c5aff182SThomas Petazzoni { 2054c5aff182SThomas Petazzoni unsigned int omc_table_reg; 2055c5aff182SThomas Petazzoni unsigned int tbl_offset; 2056c5aff182SThomas Petazzoni unsigned int reg_offset; 2057c5aff182SThomas Petazzoni 2058c5aff182SThomas Petazzoni tbl_offset = (crc8 / 4) * 4; /* Register offset from OMC table base */ 2059c5aff182SThomas Petazzoni reg_offset = crc8 % 4; /* Entry offset within the above reg */ 2060c5aff182SThomas Petazzoni 2061c5aff182SThomas Petazzoni omc_table_reg = mvreg_read(pp, MVNETA_DA_FILT_OTH_MCAST + tbl_offset); 2062c5aff182SThomas Petazzoni 2063c5aff182SThomas Petazzoni if (queue == -1) { 2064c5aff182SThomas Petazzoni /* Clear accepts frame bit at specified Other DA table entry */ 2065c5aff182SThomas Petazzoni omc_table_reg &= ~(0xff << (8 * reg_offset)); 2066c5aff182SThomas Petazzoni } else { 2067c5aff182SThomas Petazzoni omc_table_reg &= ~(0xff << (8 * reg_offset)); 2068c5aff182SThomas Petazzoni omc_table_reg |= ((0x01 | (queue << 1)) << (8 * reg_offset)); 2069c5aff182SThomas Petazzoni } 2070c5aff182SThomas Petazzoni 2071c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_DA_FILT_OTH_MCAST + tbl_offset, omc_table_reg); 2072c5aff182SThomas Petazzoni } 2073c5aff182SThomas Petazzoni 2074c5aff182SThomas Petazzoni /* The network device supports multicast using two tables: 2075c5aff182SThomas Petazzoni * 1) Special Multicast Table for MAC addresses of the form 2076c5aff182SThomas Petazzoni * 0x01-00-5E-00-00-XX (where XX is between 0x00 and 0xFF). 2077c5aff182SThomas Petazzoni * The MAC DA[7:0] bits are used as a pointer to the Special Multicast 2078c5aff182SThomas Petazzoni * Table entries in the DA-Filter table. 2079c5aff182SThomas Petazzoni * 2) Other Multicast Table for multicast of another type. A CRC-8 value 2080c5aff182SThomas Petazzoni * is used as an index to the Other Multicast Table entries in the 2081c5aff182SThomas Petazzoni * DA-Filter table. 2082c5aff182SThomas Petazzoni */ 2083c5aff182SThomas Petazzoni static int mvneta_mcast_addr_set(struct mvneta_port *pp, unsigned char *p_addr, 2084c5aff182SThomas Petazzoni int queue) 2085c5aff182SThomas Petazzoni { 2086c5aff182SThomas Petazzoni unsigned char crc_result = 0; 2087c5aff182SThomas Petazzoni 2088c5aff182SThomas Petazzoni if (memcmp(p_addr, "\x01\x00\x5e\x00\x00", 5) == 0) { 2089c5aff182SThomas Petazzoni mvneta_set_special_mcast_addr(pp, p_addr[5], queue); 2090c5aff182SThomas Petazzoni return 0; 2091c5aff182SThomas Petazzoni } 2092c5aff182SThomas Petazzoni 2093c5aff182SThomas Petazzoni crc_result = mvneta_addr_crc(p_addr); 2094c5aff182SThomas Petazzoni if (queue == -1) { 2095c5aff182SThomas Petazzoni if (pp->mcast_count[crc_result] == 0) { 2096c5aff182SThomas Petazzoni netdev_info(pp->dev, "No valid Mcast for crc8=0x%02x\n", 2097c5aff182SThomas Petazzoni crc_result); 2098c5aff182SThomas Petazzoni return -EINVAL; 2099c5aff182SThomas Petazzoni } 2100c5aff182SThomas Petazzoni 2101c5aff182SThomas Petazzoni pp->mcast_count[crc_result]--; 2102c5aff182SThomas Petazzoni if (pp->mcast_count[crc_result] != 0) { 2103c5aff182SThomas Petazzoni netdev_info(pp->dev, 2104c5aff182SThomas Petazzoni "After delete there are %d valid Mcast for crc8=0x%02x\n", 2105c5aff182SThomas Petazzoni pp->mcast_count[crc_result], crc_result); 2106c5aff182SThomas Petazzoni return -EINVAL; 2107c5aff182SThomas Petazzoni } 2108c5aff182SThomas Petazzoni } else 2109c5aff182SThomas Petazzoni pp->mcast_count[crc_result]++; 2110c5aff182SThomas Petazzoni 2111c5aff182SThomas Petazzoni mvneta_set_other_mcast_addr(pp, crc_result, queue); 2112c5aff182SThomas Petazzoni 2113c5aff182SThomas Petazzoni return 0; 2114c5aff182SThomas Petazzoni } 2115c5aff182SThomas Petazzoni 2116c5aff182SThomas Petazzoni /* Configure Fitering mode of Ethernet port */ 2117c5aff182SThomas Petazzoni static void mvneta_rx_unicast_promisc_set(struct mvneta_port *pp, 2118c5aff182SThomas Petazzoni int is_promisc) 2119c5aff182SThomas Petazzoni { 2120c5aff182SThomas Petazzoni u32 port_cfg_reg, val; 2121c5aff182SThomas Petazzoni 2122c5aff182SThomas Petazzoni port_cfg_reg = mvreg_read(pp, MVNETA_PORT_CONFIG); 2123c5aff182SThomas Petazzoni 2124c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_TYPE_PRIO); 2125c5aff182SThomas Petazzoni 2126c5aff182SThomas Petazzoni /* Set / Clear UPM bit in port configuration register */ 2127c5aff182SThomas Petazzoni if (is_promisc) { 2128c5aff182SThomas Petazzoni /* Accept all Unicast addresses */ 2129c5aff182SThomas Petazzoni port_cfg_reg |= MVNETA_UNI_PROMISC_MODE; 2130c5aff182SThomas Petazzoni val |= MVNETA_FORCE_UNI; 2131c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_MAC_ADDR_LOW, 0xffff); 2132c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_MAC_ADDR_HIGH, 0xffffffff); 2133c5aff182SThomas Petazzoni } else { 2134c5aff182SThomas Petazzoni /* Reject all Unicast addresses */ 2135c5aff182SThomas Petazzoni port_cfg_reg &= ~MVNETA_UNI_PROMISC_MODE; 2136c5aff182SThomas Petazzoni val &= ~MVNETA_FORCE_UNI; 2137c5aff182SThomas Petazzoni } 2138c5aff182SThomas Petazzoni 2139c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_PORT_CONFIG, port_cfg_reg); 2140c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_TYPE_PRIO, val); 2141c5aff182SThomas Petazzoni } 2142c5aff182SThomas Petazzoni 2143c5aff182SThomas Petazzoni /* register unicast and multicast addresses */ 2144c5aff182SThomas Petazzoni static void mvneta_set_rx_mode(struct net_device *dev) 2145c5aff182SThomas Petazzoni { 2146c5aff182SThomas Petazzoni struct mvneta_port *pp = netdev_priv(dev); 2147c5aff182SThomas Petazzoni struct netdev_hw_addr *ha; 2148c5aff182SThomas Petazzoni 2149c5aff182SThomas Petazzoni if (dev->flags & IFF_PROMISC) { 2150c5aff182SThomas Petazzoni /* Accept all: Multicast + Unicast */ 2151c5aff182SThomas Petazzoni mvneta_rx_unicast_promisc_set(pp, 1); 215290b74c01SGregory CLEMENT mvneta_set_ucast_table(pp, pp->rxq_def); 215390b74c01SGregory CLEMENT mvneta_set_special_mcast_table(pp, pp->rxq_def); 215490b74c01SGregory CLEMENT mvneta_set_other_mcast_table(pp, pp->rxq_def); 2155c5aff182SThomas Petazzoni } else { 2156c5aff182SThomas Petazzoni /* Accept single Unicast */ 2157c5aff182SThomas Petazzoni mvneta_rx_unicast_promisc_set(pp, 0); 2158c5aff182SThomas Petazzoni mvneta_set_ucast_table(pp, -1); 215990b74c01SGregory CLEMENT mvneta_mac_addr_set(pp, dev->dev_addr, pp->rxq_def); 2160c5aff182SThomas Petazzoni 2161c5aff182SThomas Petazzoni if (dev->flags & IFF_ALLMULTI) { 2162c5aff182SThomas Petazzoni /* Accept all multicast */ 216390b74c01SGregory CLEMENT mvneta_set_special_mcast_table(pp, pp->rxq_def); 216490b74c01SGregory CLEMENT mvneta_set_other_mcast_table(pp, pp->rxq_def); 2165c5aff182SThomas Petazzoni } else { 2166c5aff182SThomas Petazzoni /* Accept only initialized multicast */ 2167c5aff182SThomas Petazzoni mvneta_set_special_mcast_table(pp, -1); 2168c5aff182SThomas Petazzoni mvneta_set_other_mcast_table(pp, -1); 2169c5aff182SThomas Petazzoni 2170c5aff182SThomas Petazzoni if (!netdev_mc_empty(dev)) { 2171c5aff182SThomas Petazzoni netdev_for_each_mc_addr(ha, dev) { 2172c5aff182SThomas Petazzoni mvneta_mcast_addr_set(pp, ha->addr, 217390b74c01SGregory CLEMENT pp->rxq_def); 2174c5aff182SThomas Petazzoni } 2175c5aff182SThomas Petazzoni } 2176c5aff182SThomas Petazzoni } 2177c5aff182SThomas Petazzoni } 2178c5aff182SThomas Petazzoni } 2179c5aff182SThomas Petazzoni 2180c5aff182SThomas Petazzoni /* Interrupt handling - the callback for request_irq() */ 2181c5aff182SThomas Petazzoni static irqreturn_t mvneta_isr(int irq, void *dev_id) 2182c5aff182SThomas Petazzoni { 218312bb03b4SMaxime Ripard struct mvneta_pcpu_port *port = (struct mvneta_pcpu_port *)dev_id; 2184c5aff182SThomas Petazzoni 218512bb03b4SMaxime Ripard disable_percpu_irq(port->pp->dev->irq); 218612bb03b4SMaxime Ripard napi_schedule(&port->napi); 2187c5aff182SThomas Petazzoni 2188c5aff182SThomas Petazzoni return IRQ_HANDLED; 2189c5aff182SThomas Petazzoni } 2190c5aff182SThomas Petazzoni 2191898b2970SStas Sergeev static int mvneta_fixed_link_update(struct mvneta_port *pp, 2192898b2970SStas Sergeev struct phy_device *phy) 2193898b2970SStas Sergeev { 2194898b2970SStas Sergeev struct fixed_phy_status status; 2195898b2970SStas Sergeev struct fixed_phy_status changed = {}; 2196898b2970SStas Sergeev u32 gmac_stat = mvreg_read(pp, MVNETA_GMAC_STATUS); 2197898b2970SStas Sergeev 2198898b2970SStas Sergeev status.link = !!(gmac_stat & MVNETA_GMAC_LINK_UP); 2199898b2970SStas Sergeev if (gmac_stat & MVNETA_GMAC_SPEED_1000) 2200898b2970SStas Sergeev status.speed = SPEED_1000; 2201898b2970SStas Sergeev else if (gmac_stat & MVNETA_GMAC_SPEED_100) 2202898b2970SStas Sergeev status.speed = SPEED_100; 2203898b2970SStas Sergeev else 2204898b2970SStas Sergeev status.speed = SPEED_10; 2205898b2970SStas Sergeev status.duplex = !!(gmac_stat & MVNETA_GMAC_FULL_DUPLEX); 2206898b2970SStas Sergeev changed.link = 1; 2207898b2970SStas Sergeev changed.speed = 1; 2208898b2970SStas Sergeev changed.duplex = 1; 2209898b2970SStas Sergeev fixed_phy_update_state(phy, &status, &changed); 2210898b2970SStas Sergeev return 0; 2211898b2970SStas Sergeev } 2212898b2970SStas Sergeev 2213c5aff182SThomas Petazzoni /* NAPI handler 2214c5aff182SThomas Petazzoni * Bits 0 - 7 of the causeRxTx register indicate that are transmitted 2215c5aff182SThomas Petazzoni * packets on the corresponding TXQ (Bit 0 is for TX queue 1). 2216c5aff182SThomas Petazzoni * Bits 8 -15 of the cause Rx Tx register indicate that are received 2217c5aff182SThomas Petazzoni * packets on the corresponding RXQ (Bit 8 is for RX queue 0). 2218c5aff182SThomas Petazzoni * Each CPU has its own causeRxTx register 2219c5aff182SThomas Petazzoni */ 2220c5aff182SThomas Petazzoni static int mvneta_poll(struct napi_struct *napi, int budget) 2221c5aff182SThomas Petazzoni { 2222c5aff182SThomas Petazzoni int rx_done = 0; 2223c5aff182SThomas Petazzoni u32 cause_rx_tx; 22242dcf75e2SGregory CLEMENT int rx_queue; 2225c5aff182SThomas Petazzoni struct mvneta_port *pp = netdev_priv(napi->dev); 222612bb03b4SMaxime Ripard struct mvneta_pcpu_port *port = this_cpu_ptr(pp->ports); 2227c5aff182SThomas Petazzoni 2228c5aff182SThomas Petazzoni if (!netif_running(pp->dev)) { 222912bb03b4SMaxime Ripard napi_complete(&port->napi); 2230c5aff182SThomas Petazzoni return rx_done; 2231c5aff182SThomas Petazzoni } 2232c5aff182SThomas Petazzoni 2233c5aff182SThomas Petazzoni /* Read cause register */ 2234898b2970SStas Sergeev cause_rx_tx = mvreg_read(pp, MVNETA_INTR_NEW_CAUSE); 2235898b2970SStas Sergeev if (cause_rx_tx & MVNETA_MISCINTR_INTR_MASK) { 2236898b2970SStas Sergeev u32 cause_misc = mvreg_read(pp, MVNETA_INTR_MISC_CAUSE); 2237898b2970SStas Sergeev 2238898b2970SStas Sergeev mvreg_write(pp, MVNETA_INTR_MISC_CAUSE, 0); 2239898b2970SStas Sergeev if (pp->use_inband_status && (cause_misc & 2240898b2970SStas Sergeev (MVNETA_CAUSE_PHY_STATUS_CHANGE | 2241898b2970SStas Sergeev MVNETA_CAUSE_LINK_CHANGE | 2242898b2970SStas Sergeev MVNETA_CAUSE_PSC_SYNC_CHANGE))) { 2243898b2970SStas Sergeev mvneta_fixed_link_update(pp, pp->phy_dev); 2244898b2970SStas Sergeev } 2245898b2970SStas Sergeev } 224671f6d1b3Swilly tarreau 224771f6d1b3Swilly tarreau /* Release Tx descriptors */ 224871f6d1b3Swilly tarreau if (cause_rx_tx & MVNETA_TX_INTR_MASK_ALL) { 22490713a86aSArnaud Ebalard mvneta_tx_done_gbe(pp, (cause_rx_tx & MVNETA_TX_INTR_MASK_ALL)); 225071f6d1b3Swilly tarreau cause_rx_tx &= ~MVNETA_TX_INTR_MASK_ALL; 225171f6d1b3Swilly tarreau } 2252c5aff182SThomas Petazzoni 22536a20c175SThomas Petazzoni /* For the case where the last mvneta_poll did not process all 2254c5aff182SThomas Petazzoni * RX packets 2255c5aff182SThomas Petazzoni */ 22562dcf75e2SGregory CLEMENT rx_queue = fls(((cause_rx_tx >> 8) & 0xff)); 22572dcf75e2SGregory CLEMENT 225812bb03b4SMaxime Ripard cause_rx_tx |= port->cause_rx_tx; 22592dcf75e2SGregory CLEMENT 22602dcf75e2SGregory CLEMENT if (rx_queue) { 22612dcf75e2SGregory CLEMENT rx_queue = rx_queue - 1; 22622dcf75e2SGregory CLEMENT rx_done = mvneta_rx(pp, budget, &pp->rxqs[rx_queue]); 22632dcf75e2SGregory CLEMENT } 22642dcf75e2SGregory CLEMENT 2265c5aff182SThomas Petazzoni budget -= rx_done; 2266c5aff182SThomas Petazzoni 2267c5aff182SThomas Petazzoni if (budget > 0) { 2268c5aff182SThomas Petazzoni cause_rx_tx = 0; 226912bb03b4SMaxime Ripard napi_complete(&port->napi); 227012bb03b4SMaxime Ripard enable_percpu_irq(pp->dev->irq, 0); 2271c5aff182SThomas Petazzoni } 2272c5aff182SThomas Petazzoni 227312bb03b4SMaxime Ripard port->cause_rx_tx = cause_rx_tx; 2274c5aff182SThomas Petazzoni return rx_done; 2275c5aff182SThomas Petazzoni } 2276c5aff182SThomas Petazzoni 2277c5aff182SThomas Petazzoni /* Handle rxq fill: allocates rxq skbs; called when initializing a port */ 2278c5aff182SThomas Petazzoni static int mvneta_rxq_fill(struct mvneta_port *pp, struct mvneta_rx_queue *rxq, 2279c5aff182SThomas Petazzoni int num) 2280c5aff182SThomas Petazzoni { 2281c5aff182SThomas Petazzoni int i; 2282c5aff182SThomas Petazzoni 2283c5aff182SThomas Petazzoni for (i = 0; i < num; i++) { 2284a1a65ab1Swilly tarreau memset(rxq->descs + i, 0, sizeof(struct mvneta_rx_desc)); 2285a1a65ab1Swilly tarreau if (mvneta_rx_refill(pp, rxq->descs + i) != 0) { 2286a1a65ab1Swilly tarreau netdev_err(pp->dev, "%s:rxq %d, %d of %d buffs filled\n", 2287c5aff182SThomas Petazzoni __func__, rxq->id, i, num); 2288c5aff182SThomas Petazzoni break; 2289c5aff182SThomas Petazzoni } 2290c5aff182SThomas Petazzoni } 2291c5aff182SThomas Petazzoni 2292c5aff182SThomas Petazzoni /* Add this number of RX descriptors as non occupied (ready to 22936a20c175SThomas Petazzoni * get packets) 22946a20c175SThomas Petazzoni */ 2295c5aff182SThomas Petazzoni mvneta_rxq_non_occup_desc_add(pp, rxq, i); 2296c5aff182SThomas Petazzoni 2297c5aff182SThomas Petazzoni return i; 2298c5aff182SThomas Petazzoni } 2299c5aff182SThomas Petazzoni 2300c5aff182SThomas Petazzoni /* Free all packets pending transmit from all TXQs and reset TX port */ 2301c5aff182SThomas Petazzoni static void mvneta_tx_reset(struct mvneta_port *pp) 2302c5aff182SThomas Petazzoni { 2303c5aff182SThomas Petazzoni int queue; 2304c5aff182SThomas Petazzoni 23059672850bSEzequiel Garcia /* free the skb's in the tx ring */ 2306c5aff182SThomas Petazzoni for (queue = 0; queue < txq_number; queue++) 2307c5aff182SThomas Petazzoni mvneta_txq_done_force(pp, &pp->txqs[queue]); 2308c5aff182SThomas Petazzoni 2309c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_PORT_TX_RESET, MVNETA_PORT_TX_DMA_RESET); 2310c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_PORT_TX_RESET, 0); 2311c5aff182SThomas Petazzoni } 2312c5aff182SThomas Petazzoni 2313c5aff182SThomas Petazzoni static void mvneta_rx_reset(struct mvneta_port *pp) 2314c5aff182SThomas Petazzoni { 2315c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_PORT_RX_RESET, MVNETA_PORT_RX_DMA_RESET); 2316c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_PORT_RX_RESET, 0); 2317c5aff182SThomas Petazzoni } 2318c5aff182SThomas Petazzoni 2319c5aff182SThomas Petazzoni /* Rx/Tx queue initialization/cleanup methods */ 2320c5aff182SThomas Petazzoni 2321c5aff182SThomas Petazzoni /* Create a specified RX queue */ 2322c5aff182SThomas Petazzoni static int mvneta_rxq_init(struct mvneta_port *pp, 2323c5aff182SThomas Petazzoni struct mvneta_rx_queue *rxq) 2324c5aff182SThomas Petazzoni 2325c5aff182SThomas Petazzoni { 2326c5aff182SThomas Petazzoni rxq->size = pp->rx_ring_size; 2327c5aff182SThomas Petazzoni 2328c5aff182SThomas Petazzoni /* Allocate memory for RX descriptors */ 2329c5aff182SThomas Petazzoni rxq->descs = dma_alloc_coherent(pp->dev->dev.parent, 2330c5aff182SThomas Petazzoni rxq->size * MVNETA_DESC_ALIGNED_SIZE, 2331c5aff182SThomas Petazzoni &rxq->descs_phys, GFP_KERNEL); 2332d0320f75SJoe Perches if (rxq->descs == NULL) 2333c5aff182SThomas Petazzoni return -ENOMEM; 2334c5aff182SThomas Petazzoni 2335c5aff182SThomas Petazzoni BUG_ON(rxq->descs != 2336c5aff182SThomas Petazzoni PTR_ALIGN(rxq->descs, MVNETA_CPU_D_CACHE_LINE_SIZE)); 2337c5aff182SThomas Petazzoni 2338c5aff182SThomas Petazzoni rxq->last_desc = rxq->size - 1; 2339c5aff182SThomas Petazzoni 2340c5aff182SThomas Petazzoni /* Set Rx descriptors queue starting address */ 2341c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_RXQ_BASE_ADDR_REG(rxq->id), rxq->descs_phys); 2342c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_RXQ_SIZE_REG(rxq->id), rxq->size); 2343c5aff182SThomas Petazzoni 2344c5aff182SThomas Petazzoni /* Set Offset */ 2345c5aff182SThomas Petazzoni mvneta_rxq_offset_set(pp, rxq, NET_SKB_PAD); 2346c5aff182SThomas Petazzoni 2347c5aff182SThomas Petazzoni /* Set coalescing pkts and time */ 2348c5aff182SThomas Petazzoni mvneta_rx_pkts_coal_set(pp, rxq, rxq->pkts_coal); 2349c5aff182SThomas Petazzoni mvneta_rx_time_coal_set(pp, rxq, rxq->time_coal); 2350c5aff182SThomas Petazzoni 2351c5aff182SThomas Petazzoni /* Fill RXQ with buffers from RX pool */ 2352c5aff182SThomas Petazzoni mvneta_rxq_buf_size_set(pp, rxq, MVNETA_RX_BUF_SIZE(pp->pkt_size)); 2353c5aff182SThomas Petazzoni mvneta_rxq_bm_disable(pp, rxq); 2354c5aff182SThomas Petazzoni mvneta_rxq_fill(pp, rxq, rxq->size); 2355c5aff182SThomas Petazzoni 2356c5aff182SThomas Petazzoni return 0; 2357c5aff182SThomas Petazzoni } 2358c5aff182SThomas Petazzoni 2359c5aff182SThomas Petazzoni /* Cleanup Rx queue */ 2360c5aff182SThomas Petazzoni static void mvneta_rxq_deinit(struct mvneta_port *pp, 2361c5aff182SThomas Petazzoni struct mvneta_rx_queue *rxq) 2362c5aff182SThomas Petazzoni { 2363c5aff182SThomas Petazzoni mvneta_rxq_drop_pkts(pp, rxq); 2364c5aff182SThomas Petazzoni 2365c5aff182SThomas Petazzoni if (rxq->descs) 2366c5aff182SThomas Petazzoni dma_free_coherent(pp->dev->dev.parent, 2367c5aff182SThomas Petazzoni rxq->size * MVNETA_DESC_ALIGNED_SIZE, 2368c5aff182SThomas Petazzoni rxq->descs, 2369c5aff182SThomas Petazzoni rxq->descs_phys); 2370c5aff182SThomas Petazzoni 2371c5aff182SThomas Petazzoni rxq->descs = NULL; 2372c5aff182SThomas Petazzoni rxq->last_desc = 0; 2373c5aff182SThomas Petazzoni rxq->next_desc_to_proc = 0; 2374c5aff182SThomas Petazzoni rxq->descs_phys = 0; 2375c5aff182SThomas Petazzoni } 2376c5aff182SThomas Petazzoni 2377c5aff182SThomas Petazzoni /* Create and initialize a tx queue */ 2378c5aff182SThomas Petazzoni static int mvneta_txq_init(struct mvneta_port *pp, 2379c5aff182SThomas Petazzoni struct mvneta_tx_queue *txq) 2380c5aff182SThomas Petazzoni { 238150bf8cb6SGregory CLEMENT int cpu; 238250bf8cb6SGregory CLEMENT 2383c5aff182SThomas Petazzoni txq->size = pp->tx_ring_size; 2384c5aff182SThomas Petazzoni 23858eef5f97SEzequiel Garcia /* A queue must always have room for at least one skb. 23868eef5f97SEzequiel Garcia * Therefore, stop the queue when the free entries reaches 23878eef5f97SEzequiel Garcia * the maximum number of descriptors per skb. 23888eef5f97SEzequiel Garcia */ 23898eef5f97SEzequiel Garcia txq->tx_stop_threshold = txq->size - MVNETA_MAX_SKB_DESCS; 23908eef5f97SEzequiel Garcia txq->tx_wake_threshold = txq->tx_stop_threshold / 2; 23918eef5f97SEzequiel Garcia 23928eef5f97SEzequiel Garcia 2393c5aff182SThomas Petazzoni /* Allocate memory for TX descriptors */ 2394c5aff182SThomas Petazzoni txq->descs = dma_alloc_coherent(pp->dev->dev.parent, 2395c5aff182SThomas Petazzoni txq->size * MVNETA_DESC_ALIGNED_SIZE, 2396c5aff182SThomas Petazzoni &txq->descs_phys, GFP_KERNEL); 2397d0320f75SJoe Perches if (txq->descs == NULL) 2398c5aff182SThomas Petazzoni return -ENOMEM; 2399c5aff182SThomas Petazzoni 2400c5aff182SThomas Petazzoni /* Make sure descriptor address is cache line size aligned */ 2401c5aff182SThomas Petazzoni BUG_ON(txq->descs != 2402c5aff182SThomas Petazzoni PTR_ALIGN(txq->descs, MVNETA_CPU_D_CACHE_LINE_SIZE)); 2403c5aff182SThomas Petazzoni 2404c5aff182SThomas Petazzoni txq->last_desc = txq->size - 1; 2405c5aff182SThomas Petazzoni 2406c5aff182SThomas Petazzoni /* Set maximum bandwidth for enabled TXQs */ 2407c5aff182SThomas Petazzoni mvreg_write(pp, MVETH_TXQ_TOKEN_CFG_REG(txq->id), 0x03ffffff); 2408c5aff182SThomas Petazzoni mvreg_write(pp, MVETH_TXQ_TOKEN_COUNT_REG(txq->id), 0x3fffffff); 2409c5aff182SThomas Petazzoni 2410c5aff182SThomas Petazzoni /* Set Tx descriptors queue starting address */ 2411c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_TXQ_BASE_ADDR_REG(txq->id), txq->descs_phys); 2412c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_TXQ_SIZE_REG(txq->id), txq->size); 2413c5aff182SThomas Petazzoni 2414c5aff182SThomas Petazzoni txq->tx_skb = kmalloc(txq->size * sizeof(*txq->tx_skb), GFP_KERNEL); 2415c5aff182SThomas Petazzoni if (txq->tx_skb == NULL) { 2416c5aff182SThomas Petazzoni dma_free_coherent(pp->dev->dev.parent, 2417c5aff182SThomas Petazzoni txq->size * MVNETA_DESC_ALIGNED_SIZE, 2418c5aff182SThomas Petazzoni txq->descs, txq->descs_phys); 2419c5aff182SThomas Petazzoni return -ENOMEM; 2420c5aff182SThomas Petazzoni } 24212adb719dSEzequiel Garcia 24222adb719dSEzequiel Garcia /* Allocate DMA buffers for TSO MAC/IP/TCP headers */ 24232adb719dSEzequiel Garcia txq->tso_hdrs = dma_alloc_coherent(pp->dev->dev.parent, 24242adb719dSEzequiel Garcia txq->size * TSO_HEADER_SIZE, 24252adb719dSEzequiel Garcia &txq->tso_hdrs_phys, GFP_KERNEL); 24262adb719dSEzequiel Garcia if (txq->tso_hdrs == NULL) { 24272adb719dSEzequiel Garcia kfree(txq->tx_skb); 24282adb719dSEzequiel Garcia dma_free_coherent(pp->dev->dev.parent, 24292adb719dSEzequiel Garcia txq->size * MVNETA_DESC_ALIGNED_SIZE, 24302adb719dSEzequiel Garcia txq->descs, txq->descs_phys); 24312adb719dSEzequiel Garcia return -ENOMEM; 24322adb719dSEzequiel Garcia } 2433c5aff182SThomas Petazzoni mvneta_tx_done_pkts_coal_set(pp, txq, txq->done_pkts_coal); 2434c5aff182SThomas Petazzoni 243550bf8cb6SGregory CLEMENT /* Setup XPS mapping */ 243650bf8cb6SGregory CLEMENT if (txq_number > 1) 243750bf8cb6SGregory CLEMENT cpu = txq->id % num_present_cpus(); 243850bf8cb6SGregory CLEMENT else 243950bf8cb6SGregory CLEMENT cpu = pp->rxq_def % num_present_cpus(); 244050bf8cb6SGregory CLEMENT cpumask_set_cpu(cpu, &txq->affinity_mask); 244150bf8cb6SGregory CLEMENT netif_set_xps_queue(pp->dev, &txq->affinity_mask, txq->id); 244250bf8cb6SGregory CLEMENT 2443c5aff182SThomas Petazzoni return 0; 2444c5aff182SThomas Petazzoni } 2445c5aff182SThomas Petazzoni 2446c5aff182SThomas Petazzoni /* Free allocated resources when mvneta_txq_init() fails to allocate memory*/ 2447c5aff182SThomas Petazzoni static void mvneta_txq_deinit(struct mvneta_port *pp, 2448c5aff182SThomas Petazzoni struct mvneta_tx_queue *txq) 2449c5aff182SThomas Petazzoni { 2450c5aff182SThomas Petazzoni kfree(txq->tx_skb); 2451c5aff182SThomas Petazzoni 24522adb719dSEzequiel Garcia if (txq->tso_hdrs) 24532adb719dSEzequiel Garcia dma_free_coherent(pp->dev->dev.parent, 24542adb719dSEzequiel Garcia txq->size * TSO_HEADER_SIZE, 24552adb719dSEzequiel Garcia txq->tso_hdrs, txq->tso_hdrs_phys); 2456c5aff182SThomas Petazzoni if (txq->descs) 2457c5aff182SThomas Petazzoni dma_free_coherent(pp->dev->dev.parent, 2458c5aff182SThomas Petazzoni txq->size * MVNETA_DESC_ALIGNED_SIZE, 2459c5aff182SThomas Petazzoni txq->descs, txq->descs_phys); 2460c5aff182SThomas Petazzoni 2461c5aff182SThomas Petazzoni txq->descs = NULL; 2462c5aff182SThomas Petazzoni txq->last_desc = 0; 2463c5aff182SThomas Petazzoni txq->next_desc_to_proc = 0; 2464c5aff182SThomas Petazzoni txq->descs_phys = 0; 2465c5aff182SThomas Petazzoni 2466c5aff182SThomas Petazzoni /* Set minimum bandwidth for disabled TXQs */ 2467c5aff182SThomas Petazzoni mvreg_write(pp, MVETH_TXQ_TOKEN_CFG_REG(txq->id), 0); 2468c5aff182SThomas Petazzoni mvreg_write(pp, MVETH_TXQ_TOKEN_COUNT_REG(txq->id), 0); 2469c5aff182SThomas Petazzoni 2470c5aff182SThomas Petazzoni /* Set Tx descriptors queue starting address and size */ 2471c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_TXQ_BASE_ADDR_REG(txq->id), 0); 2472c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_TXQ_SIZE_REG(txq->id), 0); 2473c5aff182SThomas Petazzoni } 2474c5aff182SThomas Petazzoni 2475c5aff182SThomas Petazzoni /* Cleanup all Tx queues */ 2476c5aff182SThomas Petazzoni static void mvneta_cleanup_txqs(struct mvneta_port *pp) 2477c5aff182SThomas Petazzoni { 2478c5aff182SThomas Petazzoni int queue; 2479c5aff182SThomas Petazzoni 2480c5aff182SThomas Petazzoni for (queue = 0; queue < txq_number; queue++) 2481c5aff182SThomas Petazzoni mvneta_txq_deinit(pp, &pp->txqs[queue]); 2482c5aff182SThomas Petazzoni } 2483c5aff182SThomas Petazzoni 2484c5aff182SThomas Petazzoni /* Cleanup all Rx queues */ 2485c5aff182SThomas Petazzoni static void mvneta_cleanup_rxqs(struct mvneta_port *pp) 2486c5aff182SThomas Petazzoni { 24872dcf75e2SGregory CLEMENT int queue; 24882dcf75e2SGregory CLEMENT 24892dcf75e2SGregory CLEMENT for (queue = 0; queue < txq_number; queue++) 24902dcf75e2SGregory CLEMENT mvneta_rxq_deinit(pp, &pp->rxqs[queue]); 2491c5aff182SThomas Petazzoni } 2492c5aff182SThomas Petazzoni 2493c5aff182SThomas Petazzoni 2494c5aff182SThomas Petazzoni /* Init all Rx queues */ 2495c5aff182SThomas Petazzoni static int mvneta_setup_rxqs(struct mvneta_port *pp) 2496c5aff182SThomas Petazzoni { 24972dcf75e2SGregory CLEMENT int queue; 24982dcf75e2SGregory CLEMENT 24992dcf75e2SGregory CLEMENT for (queue = 0; queue < rxq_number; queue++) { 25002dcf75e2SGregory CLEMENT int err = mvneta_rxq_init(pp, &pp->rxqs[queue]); 25012dcf75e2SGregory CLEMENT 2502c5aff182SThomas Petazzoni if (err) { 2503c5aff182SThomas Petazzoni netdev_err(pp->dev, "%s: can't create rxq=%d\n", 25042dcf75e2SGregory CLEMENT __func__, queue); 2505c5aff182SThomas Petazzoni mvneta_cleanup_rxqs(pp); 2506c5aff182SThomas Petazzoni return err; 2507c5aff182SThomas Petazzoni } 25082dcf75e2SGregory CLEMENT } 2509c5aff182SThomas Petazzoni 2510c5aff182SThomas Petazzoni return 0; 2511c5aff182SThomas Petazzoni } 2512c5aff182SThomas Petazzoni 2513c5aff182SThomas Petazzoni /* Init all tx queues */ 2514c5aff182SThomas Petazzoni static int mvneta_setup_txqs(struct mvneta_port *pp) 2515c5aff182SThomas Petazzoni { 2516c5aff182SThomas Petazzoni int queue; 2517c5aff182SThomas Petazzoni 2518c5aff182SThomas Petazzoni for (queue = 0; queue < txq_number; queue++) { 2519c5aff182SThomas Petazzoni int err = mvneta_txq_init(pp, &pp->txqs[queue]); 2520c5aff182SThomas Petazzoni if (err) { 2521c5aff182SThomas Petazzoni netdev_err(pp->dev, "%s: can't create txq=%d\n", 2522c5aff182SThomas Petazzoni __func__, queue); 2523c5aff182SThomas Petazzoni mvneta_cleanup_txqs(pp); 2524c5aff182SThomas Petazzoni return err; 2525c5aff182SThomas Petazzoni } 2526c5aff182SThomas Petazzoni } 2527c5aff182SThomas Petazzoni 2528c5aff182SThomas Petazzoni return 0; 2529c5aff182SThomas Petazzoni } 2530c5aff182SThomas Petazzoni 25312dcf75e2SGregory CLEMENT static void mvneta_percpu_unmask_interrupt(void *arg) 25322dcf75e2SGregory CLEMENT { 25332dcf75e2SGregory CLEMENT struct mvneta_port *pp = arg; 25342dcf75e2SGregory CLEMENT 25352dcf75e2SGregory CLEMENT /* All the queue are unmasked, but actually only the ones 25362dcf75e2SGregory CLEMENT * maped to this CPU will be unmasked 25372dcf75e2SGregory CLEMENT */ 25382dcf75e2SGregory CLEMENT mvreg_write(pp, MVNETA_INTR_NEW_MASK, 25392dcf75e2SGregory CLEMENT MVNETA_RX_INTR_MASK_ALL | 25402dcf75e2SGregory CLEMENT MVNETA_TX_INTR_MASK_ALL | 25412dcf75e2SGregory CLEMENT MVNETA_MISCINTR_INTR_MASK); 25422dcf75e2SGregory CLEMENT } 25432dcf75e2SGregory CLEMENT 25449a401deaSGregory CLEMENT static void mvneta_percpu_mask_interrupt(void *arg) 25459a401deaSGregory CLEMENT { 25469a401deaSGregory CLEMENT struct mvneta_port *pp = arg; 25479a401deaSGregory CLEMENT 25489a401deaSGregory CLEMENT /* All the queue are masked, but actually only the ones 25499a401deaSGregory CLEMENT * maped to this CPU will be masked 25509a401deaSGregory CLEMENT */ 25519a401deaSGregory CLEMENT mvreg_write(pp, MVNETA_INTR_NEW_MASK, 0); 25529a401deaSGregory CLEMENT mvreg_write(pp, MVNETA_INTR_OLD_MASK, 0); 25539a401deaSGregory CLEMENT mvreg_write(pp, MVNETA_INTR_MISC_MASK, 0); 25549a401deaSGregory CLEMENT } 25559a401deaSGregory CLEMENT 2556c5aff182SThomas Petazzoni static void mvneta_start_dev(struct mvneta_port *pp) 2557c5aff182SThomas Petazzoni { 255812bb03b4SMaxime Ripard unsigned int cpu; 255912bb03b4SMaxime Ripard 2560c5aff182SThomas Petazzoni mvneta_max_rx_size_set(pp, pp->pkt_size); 2561c5aff182SThomas Petazzoni mvneta_txq_max_tx_size_set(pp, pp->pkt_size); 2562c5aff182SThomas Petazzoni 2563c5aff182SThomas Petazzoni /* start the Rx/Tx activity */ 2564c5aff182SThomas Petazzoni mvneta_port_enable(pp); 2565c5aff182SThomas Petazzoni 2566c5aff182SThomas Petazzoni /* Enable polling on the port */ 2567129219e4SGregory CLEMENT for_each_online_cpu(cpu) { 256812bb03b4SMaxime Ripard struct mvneta_pcpu_port *port = per_cpu_ptr(pp->ports, cpu); 256912bb03b4SMaxime Ripard 257012bb03b4SMaxime Ripard napi_enable(&port->napi); 257112bb03b4SMaxime Ripard } 2572c5aff182SThomas Petazzoni 25732dcf75e2SGregory CLEMENT /* Unmask interrupts. It has to be done from each CPU */ 25742dcf75e2SGregory CLEMENT for_each_online_cpu(cpu) 25752dcf75e2SGregory CLEMENT smp_call_function_single(cpu, mvneta_percpu_unmask_interrupt, 25762dcf75e2SGregory CLEMENT pp, true); 2577898b2970SStas Sergeev mvreg_write(pp, MVNETA_INTR_MISC_MASK, 2578898b2970SStas Sergeev MVNETA_CAUSE_PHY_STATUS_CHANGE | 2579898b2970SStas Sergeev MVNETA_CAUSE_LINK_CHANGE | 2580898b2970SStas Sergeev MVNETA_CAUSE_PSC_SYNC_CHANGE); 2581c5aff182SThomas Petazzoni 2582c5aff182SThomas Petazzoni phy_start(pp->phy_dev); 2583c5aff182SThomas Petazzoni netif_tx_start_all_queues(pp->dev); 2584c5aff182SThomas Petazzoni } 2585c5aff182SThomas Petazzoni 2586c5aff182SThomas Petazzoni static void mvneta_stop_dev(struct mvneta_port *pp) 2587c5aff182SThomas Petazzoni { 258812bb03b4SMaxime Ripard unsigned int cpu; 258912bb03b4SMaxime Ripard 2590c5aff182SThomas Petazzoni phy_stop(pp->phy_dev); 2591c5aff182SThomas Petazzoni 2592129219e4SGregory CLEMENT for_each_online_cpu(cpu) { 259312bb03b4SMaxime Ripard struct mvneta_pcpu_port *port = per_cpu_ptr(pp->ports, cpu); 259412bb03b4SMaxime Ripard 259512bb03b4SMaxime Ripard napi_disable(&port->napi); 259612bb03b4SMaxime Ripard } 2597c5aff182SThomas Petazzoni 2598c5aff182SThomas Petazzoni netif_carrier_off(pp->dev); 2599c5aff182SThomas Petazzoni 2600c5aff182SThomas Petazzoni mvneta_port_down(pp); 2601c5aff182SThomas Petazzoni netif_tx_stop_all_queues(pp->dev); 2602c5aff182SThomas Petazzoni 2603c5aff182SThomas Petazzoni /* Stop the port activity */ 2604c5aff182SThomas Petazzoni mvneta_port_disable(pp); 2605c5aff182SThomas Petazzoni 2606c5aff182SThomas Petazzoni /* Clear all ethernet port interrupts */ 2607c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_INTR_MISC_CAUSE, 0); 2608c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_INTR_OLD_CAUSE, 0); 2609c5aff182SThomas Petazzoni 2610c5aff182SThomas Petazzoni /* Mask all ethernet port interrupts */ 2611c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_INTR_NEW_MASK, 0); 2612c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_INTR_OLD_MASK, 0); 2613c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_INTR_MISC_MASK, 0); 2614c5aff182SThomas Petazzoni 2615c5aff182SThomas Petazzoni mvneta_tx_reset(pp); 2616c5aff182SThomas Petazzoni mvneta_rx_reset(pp); 2617c5aff182SThomas Petazzoni } 2618c5aff182SThomas Petazzoni 2619c5aff182SThomas Petazzoni /* Return positive if MTU is valid */ 2620c5aff182SThomas Petazzoni static int mvneta_check_mtu_valid(struct net_device *dev, int mtu) 2621c5aff182SThomas Petazzoni { 2622c5aff182SThomas Petazzoni if (mtu < 68) { 2623c5aff182SThomas Petazzoni netdev_err(dev, "cannot change mtu to less than 68\n"); 2624c5aff182SThomas Petazzoni return -EINVAL; 2625c5aff182SThomas Petazzoni } 2626c5aff182SThomas Petazzoni 2627c5aff182SThomas Petazzoni /* 9676 == 9700 - 20 and rounding to 8 */ 2628c5aff182SThomas Petazzoni if (mtu > 9676) { 2629c5aff182SThomas Petazzoni netdev_info(dev, "Illegal MTU value %d, round to 9676\n", mtu); 2630c5aff182SThomas Petazzoni mtu = 9676; 2631c5aff182SThomas Petazzoni } 2632c5aff182SThomas Petazzoni 2633c5aff182SThomas Petazzoni if (!IS_ALIGNED(MVNETA_RX_PKT_SIZE(mtu), 8)) { 2634c5aff182SThomas Petazzoni netdev_info(dev, "Illegal MTU value %d, rounding to %d\n", 2635c5aff182SThomas Petazzoni mtu, ALIGN(MVNETA_RX_PKT_SIZE(mtu), 8)); 2636c5aff182SThomas Petazzoni mtu = ALIGN(MVNETA_RX_PKT_SIZE(mtu), 8); 2637c5aff182SThomas Petazzoni } 2638c5aff182SThomas Petazzoni 2639c5aff182SThomas Petazzoni return mtu; 2640c5aff182SThomas Petazzoni } 2641c5aff182SThomas Petazzoni 2642c5aff182SThomas Petazzoni /* Change the device mtu */ 2643c5aff182SThomas Petazzoni static int mvneta_change_mtu(struct net_device *dev, int mtu) 2644c5aff182SThomas Petazzoni { 2645c5aff182SThomas Petazzoni struct mvneta_port *pp = netdev_priv(dev); 2646c5aff182SThomas Petazzoni int ret; 2647c5aff182SThomas Petazzoni 2648c5aff182SThomas Petazzoni mtu = mvneta_check_mtu_valid(dev, mtu); 2649c5aff182SThomas Petazzoni if (mtu < 0) 2650c5aff182SThomas Petazzoni return -EINVAL; 2651c5aff182SThomas Petazzoni 2652c5aff182SThomas Petazzoni dev->mtu = mtu; 2653c5aff182SThomas Petazzoni 2654b65657fcSSimon Guinot if (!netif_running(dev)) { 2655b65657fcSSimon Guinot netdev_update_features(dev); 2656c5aff182SThomas Petazzoni return 0; 2657b65657fcSSimon Guinot } 2658c5aff182SThomas Petazzoni 26596a20c175SThomas Petazzoni /* The interface is running, so we have to force a 2660a92dbd96SEzequiel Garcia * reallocation of the queues 2661c5aff182SThomas Petazzoni */ 2662c5aff182SThomas Petazzoni mvneta_stop_dev(pp); 2663c5aff182SThomas Petazzoni 2664c5aff182SThomas Petazzoni mvneta_cleanup_txqs(pp); 2665c5aff182SThomas Petazzoni mvneta_cleanup_rxqs(pp); 2666c5aff182SThomas Petazzoni 2667a92dbd96SEzequiel Garcia pp->pkt_size = MVNETA_RX_PKT_SIZE(dev->mtu); 26688ec2cd48Swilly tarreau pp->frag_size = SKB_DATA_ALIGN(MVNETA_RX_BUF_SIZE(pp->pkt_size)) + 26698ec2cd48Swilly tarreau SKB_DATA_ALIGN(sizeof(struct skb_shared_info)); 2670c5aff182SThomas Petazzoni 2671c5aff182SThomas Petazzoni ret = mvneta_setup_rxqs(pp); 2672c5aff182SThomas Petazzoni if (ret) { 2673a92dbd96SEzequiel Garcia netdev_err(dev, "unable to setup rxqs after MTU change\n"); 2674c5aff182SThomas Petazzoni return ret; 2675c5aff182SThomas Petazzoni } 2676c5aff182SThomas Petazzoni 2677a92dbd96SEzequiel Garcia ret = mvneta_setup_txqs(pp); 2678a92dbd96SEzequiel Garcia if (ret) { 2679a92dbd96SEzequiel Garcia netdev_err(dev, "unable to setup txqs after MTU change\n"); 2680a92dbd96SEzequiel Garcia return ret; 2681a92dbd96SEzequiel Garcia } 2682c5aff182SThomas Petazzoni 2683c5aff182SThomas Petazzoni mvneta_start_dev(pp); 2684c5aff182SThomas Petazzoni mvneta_port_up(pp); 2685c5aff182SThomas Petazzoni 2686b65657fcSSimon Guinot netdev_update_features(dev); 2687b65657fcSSimon Guinot 2688c5aff182SThomas Petazzoni return 0; 2689c5aff182SThomas Petazzoni } 2690c5aff182SThomas Petazzoni 2691b65657fcSSimon Guinot static netdev_features_t mvneta_fix_features(struct net_device *dev, 2692b65657fcSSimon Guinot netdev_features_t features) 2693b65657fcSSimon Guinot { 2694b65657fcSSimon Guinot struct mvneta_port *pp = netdev_priv(dev); 2695b65657fcSSimon Guinot 2696b65657fcSSimon Guinot if (pp->tx_csum_limit && dev->mtu > pp->tx_csum_limit) { 2697b65657fcSSimon Guinot features &= ~(NETIF_F_IP_CSUM | NETIF_F_TSO); 2698b65657fcSSimon Guinot netdev_info(dev, 2699b65657fcSSimon Guinot "Disable IP checksum for MTU greater than %dB\n", 2700b65657fcSSimon Guinot pp->tx_csum_limit); 2701b65657fcSSimon Guinot } 2702b65657fcSSimon Guinot 2703b65657fcSSimon Guinot return features; 2704b65657fcSSimon Guinot } 2705b65657fcSSimon Guinot 27068cc3e439SThomas Petazzoni /* Get mac address */ 27078cc3e439SThomas Petazzoni static void mvneta_get_mac_addr(struct mvneta_port *pp, unsigned char *addr) 27088cc3e439SThomas Petazzoni { 27098cc3e439SThomas Petazzoni u32 mac_addr_l, mac_addr_h; 27108cc3e439SThomas Petazzoni 27118cc3e439SThomas Petazzoni mac_addr_l = mvreg_read(pp, MVNETA_MAC_ADDR_LOW); 27128cc3e439SThomas Petazzoni mac_addr_h = mvreg_read(pp, MVNETA_MAC_ADDR_HIGH); 27138cc3e439SThomas Petazzoni addr[0] = (mac_addr_h >> 24) & 0xFF; 27148cc3e439SThomas Petazzoni addr[1] = (mac_addr_h >> 16) & 0xFF; 27158cc3e439SThomas Petazzoni addr[2] = (mac_addr_h >> 8) & 0xFF; 27168cc3e439SThomas Petazzoni addr[3] = mac_addr_h & 0xFF; 27178cc3e439SThomas Petazzoni addr[4] = (mac_addr_l >> 8) & 0xFF; 27188cc3e439SThomas Petazzoni addr[5] = mac_addr_l & 0xFF; 27198cc3e439SThomas Petazzoni } 27208cc3e439SThomas Petazzoni 2721c5aff182SThomas Petazzoni /* Handle setting mac address */ 2722c5aff182SThomas Petazzoni static int mvneta_set_mac_addr(struct net_device *dev, void *addr) 2723c5aff182SThomas Petazzoni { 2724c5aff182SThomas Petazzoni struct mvneta_port *pp = netdev_priv(dev); 2725e68de360SEzequiel Garcia struct sockaddr *sockaddr = addr; 2726e68de360SEzequiel Garcia int ret; 2727c5aff182SThomas Petazzoni 2728e68de360SEzequiel Garcia ret = eth_prepare_mac_addr_change(dev, addr); 2729e68de360SEzequiel Garcia if (ret < 0) 2730e68de360SEzequiel Garcia return ret; 2731c5aff182SThomas Petazzoni /* Remove previous address table entry */ 2732c5aff182SThomas Petazzoni mvneta_mac_addr_set(pp, dev->dev_addr, -1); 2733c5aff182SThomas Petazzoni 2734c5aff182SThomas Petazzoni /* Set new addr in hw */ 273590b74c01SGregory CLEMENT mvneta_mac_addr_set(pp, sockaddr->sa_data, pp->rxq_def); 2736c5aff182SThomas Petazzoni 2737e68de360SEzequiel Garcia eth_commit_mac_addr_change(dev, addr); 2738c5aff182SThomas Petazzoni return 0; 2739c5aff182SThomas Petazzoni } 2740c5aff182SThomas Petazzoni 2741c5aff182SThomas Petazzoni static void mvneta_adjust_link(struct net_device *ndev) 2742c5aff182SThomas Petazzoni { 2743c5aff182SThomas Petazzoni struct mvneta_port *pp = netdev_priv(ndev); 2744c5aff182SThomas Petazzoni struct phy_device *phydev = pp->phy_dev; 2745c5aff182SThomas Petazzoni int status_change = 0; 2746c5aff182SThomas Petazzoni 2747c5aff182SThomas Petazzoni if (phydev->link) { 2748c5aff182SThomas Petazzoni if ((pp->speed != phydev->speed) || 2749c5aff182SThomas Petazzoni (pp->duplex != phydev->duplex)) { 2750c5aff182SThomas Petazzoni u32 val; 2751c5aff182SThomas Petazzoni 2752c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG); 2753c5aff182SThomas Petazzoni val &= ~(MVNETA_GMAC_CONFIG_MII_SPEED | 2754c5aff182SThomas Petazzoni MVNETA_GMAC_CONFIG_GMII_SPEED | 2755898b2970SStas Sergeev MVNETA_GMAC_CONFIG_FULL_DUPLEX); 2756c5aff182SThomas Petazzoni 2757c5aff182SThomas Petazzoni if (phydev->duplex) 2758c5aff182SThomas Petazzoni val |= MVNETA_GMAC_CONFIG_FULL_DUPLEX; 2759c5aff182SThomas Petazzoni 2760c5aff182SThomas Petazzoni if (phydev->speed == SPEED_1000) 2761c5aff182SThomas Petazzoni val |= MVNETA_GMAC_CONFIG_GMII_SPEED; 27624d12bc63SThomas Petazzoni else if (phydev->speed == SPEED_100) 2763c5aff182SThomas Petazzoni val |= MVNETA_GMAC_CONFIG_MII_SPEED; 2764c5aff182SThomas Petazzoni 2765c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val); 2766c5aff182SThomas Petazzoni 2767c5aff182SThomas Petazzoni pp->duplex = phydev->duplex; 2768c5aff182SThomas Petazzoni pp->speed = phydev->speed; 2769c5aff182SThomas Petazzoni } 2770c5aff182SThomas Petazzoni } 2771c5aff182SThomas Petazzoni 2772c5aff182SThomas Petazzoni if (phydev->link != pp->link) { 2773c5aff182SThomas Petazzoni if (!phydev->link) { 2774c5aff182SThomas Petazzoni pp->duplex = -1; 2775c5aff182SThomas Petazzoni pp->speed = 0; 2776c5aff182SThomas Petazzoni } 2777c5aff182SThomas Petazzoni 2778c5aff182SThomas Petazzoni pp->link = phydev->link; 2779c5aff182SThomas Petazzoni status_change = 1; 2780c5aff182SThomas Petazzoni } 2781c5aff182SThomas Petazzoni 2782c5aff182SThomas Petazzoni if (status_change) { 2783c5aff182SThomas Petazzoni if (phydev->link) { 2784898b2970SStas Sergeev if (!pp->use_inband_status) { 2785898b2970SStas Sergeev u32 val = mvreg_read(pp, 2786898b2970SStas Sergeev MVNETA_GMAC_AUTONEG_CONFIG); 2787898b2970SStas Sergeev val &= ~MVNETA_GMAC_FORCE_LINK_DOWN; 2788898b2970SStas Sergeev val |= MVNETA_GMAC_FORCE_LINK_PASS; 2789898b2970SStas Sergeev mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, 2790898b2970SStas Sergeev val); 2791898b2970SStas Sergeev } 2792c5aff182SThomas Petazzoni mvneta_port_up(pp); 2793c5aff182SThomas Petazzoni } else { 2794898b2970SStas Sergeev if (!pp->use_inband_status) { 2795898b2970SStas Sergeev u32 val = mvreg_read(pp, 2796898b2970SStas Sergeev MVNETA_GMAC_AUTONEG_CONFIG); 2797898b2970SStas Sergeev val &= ~MVNETA_GMAC_FORCE_LINK_PASS; 2798898b2970SStas Sergeev val |= MVNETA_GMAC_FORCE_LINK_DOWN; 2799898b2970SStas Sergeev mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, 2800898b2970SStas Sergeev val); 2801898b2970SStas Sergeev } 2802c5aff182SThomas Petazzoni mvneta_port_down(pp); 2803c5aff182SThomas Petazzoni } 28040089b745SEzequiel Garcia phy_print_status(phydev); 2805c5aff182SThomas Petazzoni } 2806c5aff182SThomas Petazzoni } 2807c5aff182SThomas Petazzoni 2808c5aff182SThomas Petazzoni static int mvneta_mdio_probe(struct mvneta_port *pp) 2809c5aff182SThomas Petazzoni { 2810c5aff182SThomas Petazzoni struct phy_device *phy_dev; 2811c5aff182SThomas Petazzoni 2812c5aff182SThomas Petazzoni phy_dev = of_phy_connect(pp->dev, pp->phy_node, mvneta_adjust_link, 0, 2813c5aff182SThomas Petazzoni pp->phy_interface); 2814c5aff182SThomas Petazzoni if (!phy_dev) { 2815c5aff182SThomas Petazzoni netdev_err(pp->dev, "could not find the PHY\n"); 2816c5aff182SThomas Petazzoni return -ENODEV; 2817c5aff182SThomas Petazzoni } 2818c5aff182SThomas Petazzoni 2819c5aff182SThomas Petazzoni phy_dev->supported &= PHY_GBIT_FEATURES; 2820c5aff182SThomas Petazzoni phy_dev->advertising = phy_dev->supported; 2821c5aff182SThomas Petazzoni 2822c5aff182SThomas Petazzoni pp->phy_dev = phy_dev; 2823c5aff182SThomas Petazzoni pp->link = 0; 2824c5aff182SThomas Petazzoni pp->duplex = 0; 2825c5aff182SThomas Petazzoni pp->speed = 0; 2826c5aff182SThomas Petazzoni 2827c5aff182SThomas Petazzoni return 0; 2828c5aff182SThomas Petazzoni } 2829c5aff182SThomas Petazzoni 2830c5aff182SThomas Petazzoni static void mvneta_mdio_remove(struct mvneta_port *pp) 2831c5aff182SThomas Petazzoni { 2832c5aff182SThomas Petazzoni phy_disconnect(pp->phy_dev); 2833c5aff182SThomas Petazzoni pp->phy_dev = NULL; 2834c5aff182SThomas Petazzoni } 2835c5aff182SThomas Petazzoni 2836f8642885SMaxime Ripard static void mvneta_percpu_enable(void *arg) 2837f8642885SMaxime Ripard { 2838f8642885SMaxime Ripard struct mvneta_port *pp = arg; 2839f8642885SMaxime Ripard 2840f8642885SMaxime Ripard enable_percpu_irq(pp->dev->irq, IRQ_TYPE_NONE); 2841f8642885SMaxime Ripard } 2842f8642885SMaxime Ripard 2843f8642885SMaxime Ripard static void mvneta_percpu_disable(void *arg) 2844f8642885SMaxime Ripard { 2845f8642885SMaxime Ripard struct mvneta_port *pp = arg; 2846f8642885SMaxime Ripard 2847f8642885SMaxime Ripard disable_percpu_irq(pp->dev->irq); 2848f8642885SMaxime Ripard } 2849f8642885SMaxime Ripard 2850f8642885SMaxime Ripard static void mvneta_percpu_elect(struct mvneta_port *pp) 2851f8642885SMaxime Ripard { 2852cad5d847SGregory CLEMENT int elected_cpu = 0, max_cpu, cpu, i = 0; 2853f8642885SMaxime Ripard 2854cad5d847SGregory CLEMENT /* Use the cpu associated to the rxq when it is online, in all 2855cad5d847SGregory CLEMENT * the other cases, use the cpu 0 which can't be offline. 2856cad5d847SGregory CLEMENT */ 2857cad5d847SGregory CLEMENT if (cpu_online(pp->rxq_def)) 2858cad5d847SGregory CLEMENT elected_cpu = pp->rxq_def; 2859cad5d847SGregory CLEMENT 28602dcf75e2SGregory CLEMENT max_cpu = num_present_cpus(); 2861f8642885SMaxime Ripard 2862f8642885SMaxime Ripard for_each_online_cpu(cpu) { 28632dcf75e2SGregory CLEMENT int rxq_map = 0, txq_map = 0; 28642dcf75e2SGregory CLEMENT int rxq; 28652dcf75e2SGregory CLEMENT 28662dcf75e2SGregory CLEMENT for (rxq = 0; rxq < rxq_number; rxq++) 28672dcf75e2SGregory CLEMENT if ((rxq % max_cpu) == cpu) 28682dcf75e2SGregory CLEMENT rxq_map |= MVNETA_CPU_RXQ_ACCESS(rxq); 28692dcf75e2SGregory CLEMENT 2870cad5d847SGregory CLEMENT if (cpu == elected_cpu) 287150bf8cb6SGregory CLEMENT /* Map the default receive queue queue to the 287250bf8cb6SGregory CLEMENT * elected CPU 2873f8642885SMaxime Ripard */ 28742dcf75e2SGregory CLEMENT rxq_map |= MVNETA_CPU_RXQ_ACCESS(pp->rxq_def); 287550bf8cb6SGregory CLEMENT 287650bf8cb6SGregory CLEMENT /* We update the TX queue map only if we have one 287750bf8cb6SGregory CLEMENT * queue. In this case we associate the TX queue to 287850bf8cb6SGregory CLEMENT * the CPU bound to the default RX queue 287950bf8cb6SGregory CLEMENT */ 288050bf8cb6SGregory CLEMENT if (txq_number == 1) 2881cad5d847SGregory CLEMENT txq_map = (cpu == elected_cpu) ? 288250bf8cb6SGregory CLEMENT MVNETA_CPU_TXQ_ACCESS(1) : 0; 288350bf8cb6SGregory CLEMENT else 288450bf8cb6SGregory CLEMENT txq_map = mvreg_read(pp, MVNETA_CPU_MAP(cpu)) & 288550bf8cb6SGregory CLEMENT MVNETA_CPU_TXQ_ACCESS_ALL_MASK; 288650bf8cb6SGregory CLEMENT 28872dcf75e2SGregory CLEMENT mvreg_write(pp, MVNETA_CPU_MAP(cpu), rxq_map | txq_map); 28882dcf75e2SGregory CLEMENT 28892dcf75e2SGregory CLEMENT /* Update the interrupt mask on each CPU according the 28902dcf75e2SGregory CLEMENT * new mapping 28912dcf75e2SGregory CLEMENT */ 28922dcf75e2SGregory CLEMENT smp_call_function_single(cpu, mvneta_percpu_unmask_interrupt, 2893f8642885SMaxime Ripard pp, true); 2894f8642885SMaxime Ripard i++; 28952dcf75e2SGregory CLEMENT 2896f8642885SMaxime Ripard } 2897f8642885SMaxime Ripard }; 2898f8642885SMaxime Ripard 2899f8642885SMaxime Ripard static int mvneta_percpu_notifier(struct notifier_block *nfb, 2900f8642885SMaxime Ripard unsigned long action, void *hcpu) 2901f8642885SMaxime Ripard { 2902f8642885SMaxime Ripard struct mvneta_port *pp = container_of(nfb, struct mvneta_port, 2903f8642885SMaxime Ripard cpu_notifier); 2904f8642885SMaxime Ripard int cpu = (unsigned long)hcpu, other_cpu; 2905f8642885SMaxime Ripard struct mvneta_pcpu_port *port = per_cpu_ptr(pp->ports, cpu); 2906f8642885SMaxime Ripard 2907f8642885SMaxime Ripard switch (action) { 2908f8642885SMaxime Ripard case CPU_ONLINE: 2909f8642885SMaxime Ripard case CPU_ONLINE_FROZEN: 2910f8642885SMaxime Ripard netif_tx_stop_all_queues(pp->dev); 2911f8642885SMaxime Ripard 2912f8642885SMaxime Ripard /* We have to synchronise on tha napi of each CPU 2913f8642885SMaxime Ripard * except the one just being waked up 2914f8642885SMaxime Ripard */ 2915f8642885SMaxime Ripard for_each_online_cpu(other_cpu) { 2916f8642885SMaxime Ripard if (other_cpu != cpu) { 2917f8642885SMaxime Ripard struct mvneta_pcpu_port *other_port = 2918f8642885SMaxime Ripard per_cpu_ptr(pp->ports, other_cpu); 2919f8642885SMaxime Ripard 2920f8642885SMaxime Ripard napi_synchronize(&other_port->napi); 2921f8642885SMaxime Ripard } 2922f8642885SMaxime Ripard } 2923f8642885SMaxime Ripard 2924f8642885SMaxime Ripard /* Mask all ethernet port interrupts */ 2925f8642885SMaxime Ripard mvreg_write(pp, MVNETA_INTR_NEW_MASK, 0); 2926f8642885SMaxime Ripard mvreg_write(pp, MVNETA_INTR_OLD_MASK, 0); 2927f8642885SMaxime Ripard mvreg_write(pp, MVNETA_INTR_MISC_MASK, 0); 2928f8642885SMaxime Ripard napi_enable(&port->napi); 2929f8642885SMaxime Ripard 29302dcf75e2SGregory CLEMENT 29312dcf75e2SGregory CLEMENT /* Enable per-CPU interrupts on the CPU that is 29322dcf75e2SGregory CLEMENT * brought up. 29332dcf75e2SGregory CLEMENT */ 29342dcf75e2SGregory CLEMENT smp_call_function_single(cpu, mvneta_percpu_enable, 29352dcf75e2SGregory CLEMENT pp, true); 29362dcf75e2SGregory CLEMENT 2937f8642885SMaxime Ripard /* Enable per-CPU interrupt on the one CPU we care 2938f8642885SMaxime Ripard * about. 2939f8642885SMaxime Ripard */ 2940f8642885SMaxime Ripard mvneta_percpu_elect(pp); 2941f8642885SMaxime Ripard 29422dcf75e2SGregory CLEMENT /* Unmask all ethernet port interrupts, as this 29432dcf75e2SGregory CLEMENT * notifier is called for each CPU then the CPU to 29442dcf75e2SGregory CLEMENT * Queue mapping is applied 29452dcf75e2SGregory CLEMENT */ 2946f8642885SMaxime Ripard mvreg_write(pp, MVNETA_INTR_NEW_MASK, 2947f8642885SMaxime Ripard MVNETA_RX_INTR_MASK(rxq_number) | 2948f8642885SMaxime Ripard MVNETA_TX_INTR_MASK(txq_number) | 2949f8642885SMaxime Ripard MVNETA_MISCINTR_INTR_MASK); 2950f8642885SMaxime Ripard mvreg_write(pp, MVNETA_INTR_MISC_MASK, 2951f8642885SMaxime Ripard MVNETA_CAUSE_PHY_STATUS_CHANGE | 2952f8642885SMaxime Ripard MVNETA_CAUSE_LINK_CHANGE | 2953f8642885SMaxime Ripard MVNETA_CAUSE_PSC_SYNC_CHANGE); 2954f8642885SMaxime Ripard netif_tx_start_all_queues(pp->dev); 2955f8642885SMaxime Ripard break; 2956f8642885SMaxime Ripard case CPU_DOWN_PREPARE: 2957f8642885SMaxime Ripard case CPU_DOWN_PREPARE_FROZEN: 2958f8642885SMaxime Ripard netif_tx_stop_all_queues(pp->dev); 2959f8642885SMaxime Ripard /* Mask all ethernet port interrupts */ 2960f8642885SMaxime Ripard mvreg_write(pp, MVNETA_INTR_NEW_MASK, 0); 2961f8642885SMaxime Ripard mvreg_write(pp, MVNETA_INTR_OLD_MASK, 0); 2962f8642885SMaxime Ripard mvreg_write(pp, MVNETA_INTR_MISC_MASK, 0); 2963f8642885SMaxime Ripard 2964f8642885SMaxime Ripard napi_synchronize(&port->napi); 2965f8642885SMaxime Ripard napi_disable(&port->napi); 2966f8642885SMaxime Ripard /* Disable per-CPU interrupts on the CPU that is 2967f8642885SMaxime Ripard * brought down. 2968f8642885SMaxime Ripard */ 2969f8642885SMaxime Ripard smp_call_function_single(cpu, mvneta_percpu_disable, 2970f8642885SMaxime Ripard pp, true); 2971f8642885SMaxime Ripard 2972f8642885SMaxime Ripard break; 2973f8642885SMaxime Ripard case CPU_DEAD: 2974f8642885SMaxime Ripard case CPU_DEAD_FROZEN: 2975f8642885SMaxime Ripard /* Check if a new CPU must be elected now this on is down */ 2976f8642885SMaxime Ripard mvneta_percpu_elect(pp); 2977f8642885SMaxime Ripard /* Unmask all ethernet port interrupts */ 2978f8642885SMaxime Ripard mvreg_write(pp, MVNETA_INTR_NEW_MASK, 2979f8642885SMaxime Ripard MVNETA_RX_INTR_MASK(rxq_number) | 2980f8642885SMaxime Ripard MVNETA_TX_INTR_MASK(txq_number) | 2981f8642885SMaxime Ripard MVNETA_MISCINTR_INTR_MASK); 2982f8642885SMaxime Ripard mvreg_write(pp, MVNETA_INTR_MISC_MASK, 2983f8642885SMaxime Ripard MVNETA_CAUSE_PHY_STATUS_CHANGE | 2984f8642885SMaxime Ripard MVNETA_CAUSE_LINK_CHANGE | 2985f8642885SMaxime Ripard MVNETA_CAUSE_PSC_SYNC_CHANGE); 2986f8642885SMaxime Ripard netif_tx_start_all_queues(pp->dev); 2987f8642885SMaxime Ripard break; 2988f8642885SMaxime Ripard } 2989f8642885SMaxime Ripard 2990f8642885SMaxime Ripard return NOTIFY_OK; 2991f8642885SMaxime Ripard } 2992f8642885SMaxime Ripard 2993c5aff182SThomas Petazzoni static int mvneta_open(struct net_device *dev) 2994c5aff182SThomas Petazzoni { 2995c5aff182SThomas Petazzoni struct mvneta_port *pp = netdev_priv(dev); 29962dcf75e2SGregory CLEMENT int ret, cpu; 2997c5aff182SThomas Petazzoni 2998c5aff182SThomas Petazzoni pp->pkt_size = MVNETA_RX_PKT_SIZE(pp->dev->mtu); 29998ec2cd48Swilly tarreau pp->frag_size = SKB_DATA_ALIGN(MVNETA_RX_BUF_SIZE(pp->pkt_size)) + 30008ec2cd48Swilly tarreau SKB_DATA_ALIGN(sizeof(struct skb_shared_info)); 3001c5aff182SThomas Petazzoni 3002c5aff182SThomas Petazzoni ret = mvneta_setup_rxqs(pp); 3003c5aff182SThomas Petazzoni if (ret) 3004c5aff182SThomas Petazzoni return ret; 3005c5aff182SThomas Petazzoni 3006c5aff182SThomas Petazzoni ret = mvneta_setup_txqs(pp); 3007c5aff182SThomas Petazzoni if (ret) 3008c5aff182SThomas Petazzoni goto err_cleanup_rxqs; 3009c5aff182SThomas Petazzoni 3010c5aff182SThomas Petazzoni /* Connect to port interrupt line */ 301112bb03b4SMaxime Ripard ret = request_percpu_irq(pp->dev->irq, mvneta_isr, 301212bb03b4SMaxime Ripard MVNETA_DRIVER_NAME, pp->ports); 3013c5aff182SThomas Petazzoni if (ret) { 3014c5aff182SThomas Petazzoni netdev_err(pp->dev, "cannot request irq %d\n", pp->dev->irq); 3015c5aff182SThomas Petazzoni goto err_cleanup_txqs; 3016c5aff182SThomas Petazzoni } 3017c5aff182SThomas Petazzoni 3018f8642885SMaxime Ripard /* Even though the documentation says that request_percpu_irq 3019f8642885SMaxime Ripard * doesn't enable the interrupts automatically, it actually 3020f8642885SMaxime Ripard * does so on the local CPU. 3021f8642885SMaxime Ripard * 3022f8642885SMaxime Ripard * Make sure it's disabled. 3023f8642885SMaxime Ripard */ 3024f8642885SMaxime Ripard mvneta_percpu_disable(pp); 3025f8642885SMaxime Ripard 30262dcf75e2SGregory CLEMENT /* Enable per-CPU interrupt on all the CPU to handle our RX 30272dcf75e2SGregory CLEMENT * queue interrupts 30282dcf75e2SGregory CLEMENT */ 30292dcf75e2SGregory CLEMENT for_each_online_cpu(cpu) 30302dcf75e2SGregory CLEMENT smp_call_function_single(cpu, mvneta_percpu_enable, 30312dcf75e2SGregory CLEMENT pp, true); 30322dcf75e2SGregory CLEMENT 3033f8642885SMaxime Ripard 3034f8642885SMaxime Ripard /* Register a CPU notifier to handle the case where our CPU 3035f8642885SMaxime Ripard * might be taken offline. 3036f8642885SMaxime Ripard */ 3037f8642885SMaxime Ripard register_cpu_notifier(&pp->cpu_notifier); 3038f8642885SMaxime Ripard 3039c5aff182SThomas Petazzoni /* In default link is down */ 3040c5aff182SThomas Petazzoni netif_carrier_off(pp->dev); 3041c5aff182SThomas Petazzoni 3042c5aff182SThomas Petazzoni ret = mvneta_mdio_probe(pp); 3043c5aff182SThomas Petazzoni if (ret < 0) { 3044c5aff182SThomas Petazzoni netdev_err(dev, "cannot probe MDIO bus\n"); 3045c5aff182SThomas Petazzoni goto err_free_irq; 3046c5aff182SThomas Petazzoni } 3047c5aff182SThomas Petazzoni 3048c5aff182SThomas Petazzoni mvneta_start_dev(pp); 3049c5aff182SThomas Petazzoni 3050c5aff182SThomas Petazzoni return 0; 3051c5aff182SThomas Petazzoni 3052c5aff182SThomas Petazzoni err_free_irq: 305312bb03b4SMaxime Ripard free_percpu_irq(pp->dev->irq, pp->ports); 3054c5aff182SThomas Petazzoni err_cleanup_txqs: 3055c5aff182SThomas Petazzoni mvneta_cleanup_txqs(pp); 3056c5aff182SThomas Petazzoni err_cleanup_rxqs: 3057c5aff182SThomas Petazzoni mvneta_cleanup_rxqs(pp); 3058c5aff182SThomas Petazzoni return ret; 3059c5aff182SThomas Petazzoni } 3060c5aff182SThomas Petazzoni 3061c5aff182SThomas Petazzoni /* Stop the port, free port interrupt line */ 3062c5aff182SThomas Petazzoni static int mvneta_stop(struct net_device *dev) 3063c5aff182SThomas Petazzoni { 3064c5aff182SThomas Petazzoni struct mvneta_port *pp = netdev_priv(dev); 3065c5aff182SThomas Petazzoni 3066c5aff182SThomas Petazzoni mvneta_stop_dev(pp); 3067c5aff182SThomas Petazzoni mvneta_mdio_remove(pp); 3068f8642885SMaxime Ripard unregister_cpu_notifier(&pp->cpu_notifier); 3069129219e4SGregory CLEMENT on_each_cpu(mvneta_percpu_disable, pp, true); 307012bb03b4SMaxime Ripard free_percpu_irq(dev->irq, pp->ports); 3071c5aff182SThomas Petazzoni mvneta_cleanup_rxqs(pp); 3072c5aff182SThomas Petazzoni mvneta_cleanup_txqs(pp); 3073c5aff182SThomas Petazzoni 3074c5aff182SThomas Petazzoni return 0; 3075c5aff182SThomas Petazzoni } 3076c5aff182SThomas Petazzoni 307715f59456SThomas Petazzoni static int mvneta_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) 307815f59456SThomas Petazzoni { 307915f59456SThomas Petazzoni struct mvneta_port *pp = netdev_priv(dev); 308015f59456SThomas Petazzoni 308115f59456SThomas Petazzoni if (!pp->phy_dev) 308215f59456SThomas Petazzoni return -ENOTSUPP; 308315f59456SThomas Petazzoni 3084ecf7b361SStas Sergeev return phy_mii_ioctl(pp->phy_dev, ifr, cmd); 308515f59456SThomas Petazzoni } 308615f59456SThomas Petazzoni 3087c5aff182SThomas Petazzoni /* Ethtool methods */ 3088c5aff182SThomas Petazzoni 3089c5aff182SThomas Petazzoni /* Get settings (phy address, speed) for ethtools */ 3090c5aff182SThomas Petazzoni int mvneta_ethtool_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) 3091c5aff182SThomas Petazzoni { 3092c5aff182SThomas Petazzoni struct mvneta_port *pp = netdev_priv(dev); 3093c5aff182SThomas Petazzoni 3094c5aff182SThomas Petazzoni if (!pp->phy_dev) 3095c5aff182SThomas Petazzoni return -ENODEV; 3096c5aff182SThomas Petazzoni 3097c5aff182SThomas Petazzoni return phy_ethtool_gset(pp->phy_dev, cmd); 3098c5aff182SThomas Petazzoni } 3099c5aff182SThomas Petazzoni 3100c5aff182SThomas Petazzoni /* Set settings (phy address, speed) for ethtools */ 3101c5aff182SThomas Petazzoni int mvneta_ethtool_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) 3102c5aff182SThomas Petazzoni { 3103c5aff182SThomas Petazzoni struct mvneta_port *pp = netdev_priv(dev); 31040c0744fcSStas Sergeev struct phy_device *phydev = pp->phy_dev; 3105c5aff182SThomas Petazzoni 31060c0744fcSStas Sergeev if (!phydev) 3107c5aff182SThomas Petazzoni return -ENODEV; 3108c5aff182SThomas Petazzoni 31090c0744fcSStas Sergeev if ((cmd->autoneg == AUTONEG_ENABLE) != pp->use_inband_status) { 31100c0744fcSStas Sergeev u32 val; 31110c0744fcSStas Sergeev 31120c0744fcSStas Sergeev mvneta_set_autoneg(pp, cmd->autoneg == AUTONEG_ENABLE); 31130c0744fcSStas Sergeev 31140c0744fcSStas Sergeev if (cmd->autoneg == AUTONEG_DISABLE) { 31150c0744fcSStas Sergeev val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG); 31160c0744fcSStas Sergeev val &= ~(MVNETA_GMAC_CONFIG_MII_SPEED | 31170c0744fcSStas Sergeev MVNETA_GMAC_CONFIG_GMII_SPEED | 31180c0744fcSStas Sergeev MVNETA_GMAC_CONFIG_FULL_DUPLEX); 31190c0744fcSStas Sergeev 31200c0744fcSStas Sergeev if (phydev->duplex) 31210c0744fcSStas Sergeev val |= MVNETA_GMAC_CONFIG_FULL_DUPLEX; 31220c0744fcSStas Sergeev 31230c0744fcSStas Sergeev if (phydev->speed == SPEED_1000) 31240c0744fcSStas Sergeev val |= MVNETA_GMAC_CONFIG_GMII_SPEED; 31250c0744fcSStas Sergeev else if (phydev->speed == SPEED_100) 31260c0744fcSStas Sergeev val |= MVNETA_GMAC_CONFIG_MII_SPEED; 31270c0744fcSStas Sergeev 31280c0744fcSStas Sergeev mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val); 31290c0744fcSStas Sergeev } 31300c0744fcSStas Sergeev 31310c0744fcSStas Sergeev pp->use_inband_status = (cmd->autoneg == AUTONEG_ENABLE); 31320c0744fcSStas Sergeev netdev_info(pp->dev, "autoneg status set to %i\n", 31330c0744fcSStas Sergeev pp->use_inband_status); 31340c0744fcSStas Sergeev 31350c0744fcSStas Sergeev if (netif_running(dev)) { 31360c0744fcSStas Sergeev mvneta_port_down(pp); 31370c0744fcSStas Sergeev mvneta_port_up(pp); 31380c0744fcSStas Sergeev } 31390c0744fcSStas Sergeev } 31400c0744fcSStas Sergeev 3141c5aff182SThomas Petazzoni return phy_ethtool_sset(pp->phy_dev, cmd); 3142c5aff182SThomas Petazzoni } 3143c5aff182SThomas Petazzoni 3144c5aff182SThomas Petazzoni /* Set interrupt coalescing for ethtools */ 3145c5aff182SThomas Petazzoni static int mvneta_ethtool_set_coalesce(struct net_device *dev, 3146c5aff182SThomas Petazzoni struct ethtool_coalesce *c) 3147c5aff182SThomas Petazzoni { 3148c5aff182SThomas Petazzoni struct mvneta_port *pp = netdev_priv(dev); 3149c5aff182SThomas Petazzoni int queue; 3150c5aff182SThomas Petazzoni 3151c5aff182SThomas Petazzoni for (queue = 0; queue < rxq_number; queue++) { 3152c5aff182SThomas Petazzoni struct mvneta_rx_queue *rxq = &pp->rxqs[queue]; 3153c5aff182SThomas Petazzoni rxq->time_coal = c->rx_coalesce_usecs; 3154c5aff182SThomas Petazzoni rxq->pkts_coal = c->rx_max_coalesced_frames; 3155c5aff182SThomas Petazzoni mvneta_rx_pkts_coal_set(pp, rxq, rxq->pkts_coal); 3156c5aff182SThomas Petazzoni mvneta_rx_time_coal_set(pp, rxq, rxq->time_coal); 3157c5aff182SThomas Petazzoni } 3158c5aff182SThomas Petazzoni 3159c5aff182SThomas Petazzoni for (queue = 0; queue < txq_number; queue++) { 3160c5aff182SThomas Petazzoni struct mvneta_tx_queue *txq = &pp->txqs[queue]; 3161c5aff182SThomas Petazzoni txq->done_pkts_coal = c->tx_max_coalesced_frames; 3162c5aff182SThomas Petazzoni mvneta_tx_done_pkts_coal_set(pp, txq, txq->done_pkts_coal); 3163c5aff182SThomas Petazzoni } 3164c5aff182SThomas Petazzoni 3165c5aff182SThomas Petazzoni return 0; 3166c5aff182SThomas Petazzoni } 3167c5aff182SThomas Petazzoni 3168c5aff182SThomas Petazzoni /* get coalescing for ethtools */ 3169c5aff182SThomas Petazzoni static int mvneta_ethtool_get_coalesce(struct net_device *dev, 3170c5aff182SThomas Petazzoni struct ethtool_coalesce *c) 3171c5aff182SThomas Petazzoni { 3172c5aff182SThomas Petazzoni struct mvneta_port *pp = netdev_priv(dev); 3173c5aff182SThomas Petazzoni 3174c5aff182SThomas Petazzoni c->rx_coalesce_usecs = pp->rxqs[0].time_coal; 3175c5aff182SThomas Petazzoni c->rx_max_coalesced_frames = pp->rxqs[0].pkts_coal; 3176c5aff182SThomas Petazzoni 3177c5aff182SThomas Petazzoni c->tx_max_coalesced_frames = pp->txqs[0].done_pkts_coal; 3178c5aff182SThomas Petazzoni return 0; 3179c5aff182SThomas Petazzoni } 3180c5aff182SThomas Petazzoni 3181c5aff182SThomas Petazzoni 3182c5aff182SThomas Petazzoni static void mvneta_ethtool_get_drvinfo(struct net_device *dev, 3183c5aff182SThomas Petazzoni struct ethtool_drvinfo *drvinfo) 3184c5aff182SThomas Petazzoni { 3185c5aff182SThomas Petazzoni strlcpy(drvinfo->driver, MVNETA_DRIVER_NAME, 3186c5aff182SThomas Petazzoni sizeof(drvinfo->driver)); 3187c5aff182SThomas Petazzoni strlcpy(drvinfo->version, MVNETA_DRIVER_VERSION, 3188c5aff182SThomas Petazzoni sizeof(drvinfo->version)); 3189c5aff182SThomas Petazzoni strlcpy(drvinfo->bus_info, dev_name(&dev->dev), 3190c5aff182SThomas Petazzoni sizeof(drvinfo->bus_info)); 3191c5aff182SThomas Petazzoni } 3192c5aff182SThomas Petazzoni 3193c5aff182SThomas Petazzoni 3194c5aff182SThomas Petazzoni static void mvneta_ethtool_get_ringparam(struct net_device *netdev, 3195c5aff182SThomas Petazzoni struct ethtool_ringparam *ring) 3196c5aff182SThomas Petazzoni { 3197c5aff182SThomas Petazzoni struct mvneta_port *pp = netdev_priv(netdev); 3198c5aff182SThomas Petazzoni 3199c5aff182SThomas Petazzoni ring->rx_max_pending = MVNETA_MAX_RXD; 3200c5aff182SThomas Petazzoni ring->tx_max_pending = MVNETA_MAX_TXD; 3201c5aff182SThomas Petazzoni ring->rx_pending = pp->rx_ring_size; 3202c5aff182SThomas Petazzoni ring->tx_pending = pp->tx_ring_size; 3203c5aff182SThomas Petazzoni } 3204c5aff182SThomas Petazzoni 3205c5aff182SThomas Petazzoni static int mvneta_ethtool_set_ringparam(struct net_device *dev, 3206c5aff182SThomas Petazzoni struct ethtool_ringparam *ring) 3207c5aff182SThomas Petazzoni { 3208c5aff182SThomas Petazzoni struct mvneta_port *pp = netdev_priv(dev); 3209c5aff182SThomas Petazzoni 3210c5aff182SThomas Petazzoni if ((ring->rx_pending == 0) || (ring->tx_pending == 0)) 3211c5aff182SThomas Petazzoni return -EINVAL; 3212c5aff182SThomas Petazzoni pp->rx_ring_size = ring->rx_pending < MVNETA_MAX_RXD ? 3213c5aff182SThomas Petazzoni ring->rx_pending : MVNETA_MAX_RXD; 32148eef5f97SEzequiel Garcia 32158eef5f97SEzequiel Garcia pp->tx_ring_size = clamp_t(u16, ring->tx_pending, 32168eef5f97SEzequiel Garcia MVNETA_MAX_SKB_DESCS * 2, MVNETA_MAX_TXD); 32178eef5f97SEzequiel Garcia if (pp->tx_ring_size != ring->tx_pending) 32188eef5f97SEzequiel Garcia netdev_warn(dev, "TX queue size set to %u (requested %u)\n", 32198eef5f97SEzequiel Garcia pp->tx_ring_size, ring->tx_pending); 3220c5aff182SThomas Petazzoni 3221c5aff182SThomas Petazzoni if (netif_running(dev)) { 3222c5aff182SThomas Petazzoni mvneta_stop(dev); 3223c5aff182SThomas Petazzoni if (mvneta_open(dev)) { 3224c5aff182SThomas Petazzoni netdev_err(dev, 3225c5aff182SThomas Petazzoni "error on opening device after ring param change\n"); 3226c5aff182SThomas Petazzoni return -ENOMEM; 3227c5aff182SThomas Petazzoni } 3228c5aff182SThomas Petazzoni } 3229c5aff182SThomas Petazzoni 3230c5aff182SThomas Petazzoni return 0; 3231c5aff182SThomas Petazzoni } 3232c5aff182SThomas Petazzoni 32339b0cdefaSRussell King static void mvneta_ethtool_get_strings(struct net_device *netdev, u32 sset, 32349b0cdefaSRussell King u8 *data) 32359b0cdefaSRussell King { 32369b0cdefaSRussell King if (sset == ETH_SS_STATS) { 32379b0cdefaSRussell King int i; 32389b0cdefaSRussell King 32399b0cdefaSRussell King for (i = 0; i < ARRAY_SIZE(mvneta_statistics); i++) 32409b0cdefaSRussell King memcpy(data + i * ETH_GSTRING_LEN, 32419b0cdefaSRussell King mvneta_statistics[i].name, ETH_GSTRING_LEN); 32429b0cdefaSRussell King } 32439b0cdefaSRussell King } 32449b0cdefaSRussell King 32459b0cdefaSRussell King static void mvneta_ethtool_update_stats(struct mvneta_port *pp) 32469b0cdefaSRussell King { 32479b0cdefaSRussell King const struct mvneta_statistic *s; 32489b0cdefaSRussell King void __iomem *base = pp->base; 32499b0cdefaSRussell King u32 high, low, val; 32502c832293SJisheng Zhang u64 val64; 32519b0cdefaSRussell King int i; 32529b0cdefaSRussell King 32539b0cdefaSRussell King for (i = 0, s = mvneta_statistics; 32549b0cdefaSRussell King s < mvneta_statistics + ARRAY_SIZE(mvneta_statistics); 32559b0cdefaSRussell King s++, i++) { 32569b0cdefaSRussell King switch (s->type) { 32579b0cdefaSRussell King case T_REG_32: 32589b0cdefaSRussell King val = readl_relaxed(base + s->offset); 32592c832293SJisheng Zhang pp->ethtool_stats[i] += val; 32609b0cdefaSRussell King break; 32619b0cdefaSRussell King case T_REG_64: 32629b0cdefaSRussell King /* Docs say to read low 32-bit then high */ 32639b0cdefaSRussell King low = readl_relaxed(base + s->offset); 32649b0cdefaSRussell King high = readl_relaxed(base + s->offset + 4); 32652c832293SJisheng Zhang val64 = (u64)high << 32 | low; 32662c832293SJisheng Zhang pp->ethtool_stats[i] += val64; 32679b0cdefaSRussell King break; 32689b0cdefaSRussell King } 32699b0cdefaSRussell King } 32709b0cdefaSRussell King } 32719b0cdefaSRussell King 32729b0cdefaSRussell King static void mvneta_ethtool_get_stats(struct net_device *dev, 32739b0cdefaSRussell King struct ethtool_stats *stats, u64 *data) 32749b0cdefaSRussell King { 32759b0cdefaSRussell King struct mvneta_port *pp = netdev_priv(dev); 32769b0cdefaSRussell King int i; 32779b0cdefaSRussell King 32789b0cdefaSRussell King mvneta_ethtool_update_stats(pp); 32799b0cdefaSRussell King 32809b0cdefaSRussell King for (i = 0; i < ARRAY_SIZE(mvneta_statistics); i++) 32819b0cdefaSRussell King *data++ = pp->ethtool_stats[i]; 32829b0cdefaSRussell King } 32839b0cdefaSRussell King 32849b0cdefaSRussell King static int mvneta_ethtool_get_sset_count(struct net_device *dev, int sset) 32859b0cdefaSRussell King { 32869b0cdefaSRussell King if (sset == ETH_SS_STATS) 32879b0cdefaSRussell King return ARRAY_SIZE(mvneta_statistics); 32889b0cdefaSRussell King return -EOPNOTSUPP; 32899b0cdefaSRussell King } 32909b0cdefaSRussell King 32919a401deaSGregory CLEMENT static u32 mvneta_ethtool_get_rxfh_indir_size(struct net_device *dev) 32929a401deaSGregory CLEMENT { 32939a401deaSGregory CLEMENT return MVNETA_RSS_LU_TABLE_SIZE; 32949a401deaSGregory CLEMENT } 32959a401deaSGregory CLEMENT 32969a401deaSGregory CLEMENT static int mvneta_ethtool_get_rxnfc(struct net_device *dev, 32979a401deaSGregory CLEMENT struct ethtool_rxnfc *info, 32989a401deaSGregory CLEMENT u32 *rules __always_unused) 32999a401deaSGregory CLEMENT { 33009a401deaSGregory CLEMENT switch (info->cmd) { 33019a401deaSGregory CLEMENT case ETHTOOL_GRXRINGS: 33029a401deaSGregory CLEMENT info->data = rxq_number; 33039a401deaSGregory CLEMENT return 0; 33049a401deaSGregory CLEMENT case ETHTOOL_GRXFH: 33059a401deaSGregory CLEMENT return -EOPNOTSUPP; 33069a401deaSGregory CLEMENT default: 33079a401deaSGregory CLEMENT return -EOPNOTSUPP; 33089a401deaSGregory CLEMENT } 33099a401deaSGregory CLEMENT } 33109a401deaSGregory CLEMENT 33119a401deaSGregory CLEMENT static int mvneta_config_rss(struct mvneta_port *pp) 33129a401deaSGregory CLEMENT { 33139a401deaSGregory CLEMENT int cpu; 33149a401deaSGregory CLEMENT u32 val; 33159a401deaSGregory CLEMENT 33169a401deaSGregory CLEMENT netif_tx_stop_all_queues(pp->dev); 33179a401deaSGregory CLEMENT 33189a401deaSGregory CLEMENT for_each_online_cpu(cpu) 33199a401deaSGregory CLEMENT smp_call_function_single(cpu, mvneta_percpu_mask_interrupt, 33209a401deaSGregory CLEMENT pp, true); 33219a401deaSGregory CLEMENT 33229a401deaSGregory CLEMENT /* We have to synchronise on the napi of each CPU */ 33239a401deaSGregory CLEMENT for_each_online_cpu(cpu) { 33249a401deaSGregory CLEMENT struct mvneta_pcpu_port *pcpu_port = 33259a401deaSGregory CLEMENT per_cpu_ptr(pp->ports, cpu); 33269a401deaSGregory CLEMENT 33279a401deaSGregory CLEMENT napi_synchronize(&pcpu_port->napi); 33289a401deaSGregory CLEMENT napi_disable(&pcpu_port->napi); 33299a401deaSGregory CLEMENT } 33309a401deaSGregory CLEMENT 33319a401deaSGregory CLEMENT pp->rxq_def = pp->indir[0]; 33329a401deaSGregory CLEMENT 33339a401deaSGregory CLEMENT /* Update unicast mapping */ 33349a401deaSGregory CLEMENT mvneta_set_rx_mode(pp->dev); 33359a401deaSGregory CLEMENT 33369a401deaSGregory CLEMENT /* Update val of portCfg register accordingly with all RxQueue types */ 33379a401deaSGregory CLEMENT val = MVNETA_PORT_CONFIG_DEFL_VALUE(pp->rxq_def); 33389a401deaSGregory CLEMENT mvreg_write(pp, MVNETA_PORT_CONFIG, val); 33399a401deaSGregory CLEMENT 33409a401deaSGregory CLEMENT /* Update the elected CPU matching the new rxq_def */ 33419a401deaSGregory CLEMENT mvneta_percpu_elect(pp); 33429a401deaSGregory CLEMENT 33439a401deaSGregory CLEMENT /* We have to synchronise on the napi of each CPU */ 33449a401deaSGregory CLEMENT for_each_online_cpu(cpu) { 33459a401deaSGregory CLEMENT struct mvneta_pcpu_port *pcpu_port = 33469a401deaSGregory CLEMENT per_cpu_ptr(pp->ports, cpu); 33479a401deaSGregory CLEMENT 33489a401deaSGregory CLEMENT napi_enable(&pcpu_port->napi); 33499a401deaSGregory CLEMENT } 33509a401deaSGregory CLEMENT 33519a401deaSGregory CLEMENT netif_tx_start_all_queues(pp->dev); 33529a401deaSGregory CLEMENT 33539a401deaSGregory CLEMENT return 0; 33549a401deaSGregory CLEMENT } 33559a401deaSGregory CLEMENT 33569a401deaSGregory CLEMENT static int mvneta_ethtool_set_rxfh(struct net_device *dev, const u32 *indir, 33579a401deaSGregory CLEMENT const u8 *key, const u8 hfunc) 33589a401deaSGregory CLEMENT { 33599a401deaSGregory CLEMENT struct mvneta_port *pp = netdev_priv(dev); 33609a401deaSGregory CLEMENT /* We require at least one supported parameter to be changed 33619a401deaSGregory CLEMENT * and no change in any of the unsupported parameters 33629a401deaSGregory CLEMENT */ 33639a401deaSGregory CLEMENT if (key || 33649a401deaSGregory CLEMENT (hfunc != ETH_RSS_HASH_NO_CHANGE && hfunc != ETH_RSS_HASH_TOP)) 33659a401deaSGregory CLEMENT return -EOPNOTSUPP; 33669a401deaSGregory CLEMENT 33679a401deaSGregory CLEMENT if (!indir) 33689a401deaSGregory CLEMENT return 0; 33699a401deaSGregory CLEMENT 33709a401deaSGregory CLEMENT memcpy(pp->indir, indir, MVNETA_RSS_LU_TABLE_SIZE); 33719a401deaSGregory CLEMENT 33729a401deaSGregory CLEMENT return mvneta_config_rss(pp); 33739a401deaSGregory CLEMENT } 33749a401deaSGregory CLEMENT 33759a401deaSGregory CLEMENT static int mvneta_ethtool_get_rxfh(struct net_device *dev, u32 *indir, u8 *key, 33769a401deaSGregory CLEMENT u8 *hfunc) 33779a401deaSGregory CLEMENT { 33789a401deaSGregory CLEMENT struct mvneta_port *pp = netdev_priv(dev); 33799a401deaSGregory CLEMENT 33809a401deaSGregory CLEMENT if (hfunc) 33819a401deaSGregory CLEMENT *hfunc = ETH_RSS_HASH_TOP; 33829a401deaSGregory CLEMENT 33839a401deaSGregory CLEMENT if (!indir) 33849a401deaSGregory CLEMENT return 0; 33859a401deaSGregory CLEMENT 33869a401deaSGregory CLEMENT memcpy(indir, pp->indir, MVNETA_RSS_LU_TABLE_SIZE); 33879a401deaSGregory CLEMENT 33889a401deaSGregory CLEMENT return 0; 33899a401deaSGregory CLEMENT } 33909a401deaSGregory CLEMENT 3391c5aff182SThomas Petazzoni static const struct net_device_ops mvneta_netdev_ops = { 3392c5aff182SThomas Petazzoni .ndo_open = mvneta_open, 3393c5aff182SThomas Petazzoni .ndo_stop = mvneta_stop, 3394c5aff182SThomas Petazzoni .ndo_start_xmit = mvneta_tx, 3395c5aff182SThomas Petazzoni .ndo_set_rx_mode = mvneta_set_rx_mode, 3396c5aff182SThomas Petazzoni .ndo_set_mac_address = mvneta_set_mac_addr, 3397c5aff182SThomas Petazzoni .ndo_change_mtu = mvneta_change_mtu, 3398b65657fcSSimon Guinot .ndo_fix_features = mvneta_fix_features, 3399c5aff182SThomas Petazzoni .ndo_get_stats64 = mvneta_get_stats64, 340015f59456SThomas Petazzoni .ndo_do_ioctl = mvneta_ioctl, 3401c5aff182SThomas Petazzoni }; 3402c5aff182SThomas Petazzoni 3403c5aff182SThomas Petazzoni const struct ethtool_ops mvneta_eth_tool_ops = { 3404c5aff182SThomas Petazzoni .get_link = ethtool_op_get_link, 3405c5aff182SThomas Petazzoni .get_settings = mvneta_ethtool_get_settings, 3406c5aff182SThomas Petazzoni .set_settings = mvneta_ethtool_set_settings, 3407c5aff182SThomas Petazzoni .set_coalesce = mvneta_ethtool_set_coalesce, 3408c5aff182SThomas Petazzoni .get_coalesce = mvneta_ethtool_get_coalesce, 3409c5aff182SThomas Petazzoni .get_drvinfo = mvneta_ethtool_get_drvinfo, 3410c5aff182SThomas Petazzoni .get_ringparam = mvneta_ethtool_get_ringparam, 3411c5aff182SThomas Petazzoni .set_ringparam = mvneta_ethtool_set_ringparam, 34129b0cdefaSRussell King .get_strings = mvneta_ethtool_get_strings, 34139b0cdefaSRussell King .get_ethtool_stats = mvneta_ethtool_get_stats, 34149b0cdefaSRussell King .get_sset_count = mvneta_ethtool_get_sset_count, 34159a401deaSGregory CLEMENT .get_rxfh_indir_size = mvneta_ethtool_get_rxfh_indir_size, 34169a401deaSGregory CLEMENT .get_rxnfc = mvneta_ethtool_get_rxnfc, 34179a401deaSGregory CLEMENT .get_rxfh = mvneta_ethtool_get_rxfh, 34189a401deaSGregory CLEMENT .set_rxfh = mvneta_ethtool_set_rxfh, 3419c5aff182SThomas Petazzoni }; 3420c5aff182SThomas Petazzoni 3421c5aff182SThomas Petazzoni /* Initialize hw */ 34229672850bSEzequiel Garcia static int mvneta_init(struct device *dev, struct mvneta_port *pp) 3423c5aff182SThomas Petazzoni { 3424c5aff182SThomas Petazzoni int queue; 3425c5aff182SThomas Petazzoni 3426c5aff182SThomas Petazzoni /* Disable port */ 3427c5aff182SThomas Petazzoni mvneta_port_disable(pp); 3428c5aff182SThomas Petazzoni 3429c5aff182SThomas Petazzoni /* Set port default values */ 3430c5aff182SThomas Petazzoni mvneta_defaults_set(pp); 3431c5aff182SThomas Petazzoni 34329672850bSEzequiel Garcia pp->txqs = devm_kcalloc(dev, txq_number, sizeof(struct mvneta_tx_queue), 3433c5aff182SThomas Petazzoni GFP_KERNEL); 3434c5aff182SThomas Petazzoni if (!pp->txqs) 3435c5aff182SThomas Petazzoni return -ENOMEM; 3436c5aff182SThomas Petazzoni 3437c5aff182SThomas Petazzoni /* Initialize TX descriptor rings */ 3438c5aff182SThomas Petazzoni for (queue = 0; queue < txq_number; queue++) { 3439c5aff182SThomas Petazzoni struct mvneta_tx_queue *txq = &pp->txqs[queue]; 3440c5aff182SThomas Petazzoni txq->id = queue; 3441c5aff182SThomas Petazzoni txq->size = pp->tx_ring_size; 3442c5aff182SThomas Petazzoni txq->done_pkts_coal = MVNETA_TXDONE_COAL_PKTS; 3443c5aff182SThomas Petazzoni } 3444c5aff182SThomas Petazzoni 34459672850bSEzequiel Garcia pp->rxqs = devm_kcalloc(dev, rxq_number, sizeof(struct mvneta_rx_queue), 3446c5aff182SThomas Petazzoni GFP_KERNEL); 34479672850bSEzequiel Garcia if (!pp->rxqs) 3448c5aff182SThomas Petazzoni return -ENOMEM; 3449c5aff182SThomas Petazzoni 3450c5aff182SThomas Petazzoni /* Create Rx descriptor rings */ 3451c5aff182SThomas Petazzoni for (queue = 0; queue < rxq_number; queue++) { 3452c5aff182SThomas Petazzoni struct mvneta_rx_queue *rxq = &pp->rxqs[queue]; 3453c5aff182SThomas Petazzoni rxq->id = queue; 3454c5aff182SThomas Petazzoni rxq->size = pp->rx_ring_size; 3455c5aff182SThomas Petazzoni rxq->pkts_coal = MVNETA_RX_COAL_PKTS; 3456c5aff182SThomas Petazzoni rxq->time_coal = MVNETA_RX_COAL_USEC; 3457c5aff182SThomas Petazzoni } 3458c5aff182SThomas Petazzoni 3459c5aff182SThomas Petazzoni return 0; 3460c5aff182SThomas Petazzoni } 3461c5aff182SThomas Petazzoni 3462c5aff182SThomas Petazzoni /* platform glue : initialize decoding windows */ 346303ce758eSGreg KH static void mvneta_conf_mbus_windows(struct mvneta_port *pp, 3464c5aff182SThomas Petazzoni const struct mbus_dram_target_info *dram) 3465c5aff182SThomas Petazzoni { 3466c5aff182SThomas Petazzoni u32 win_enable; 3467c5aff182SThomas Petazzoni u32 win_protect; 3468c5aff182SThomas Petazzoni int i; 3469c5aff182SThomas Petazzoni 3470c5aff182SThomas Petazzoni for (i = 0; i < 6; i++) { 3471c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_WIN_BASE(i), 0); 3472c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_WIN_SIZE(i), 0); 3473c5aff182SThomas Petazzoni 3474c5aff182SThomas Petazzoni if (i < 4) 3475c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_WIN_REMAP(i), 0); 3476c5aff182SThomas Petazzoni } 3477c5aff182SThomas Petazzoni 3478c5aff182SThomas Petazzoni win_enable = 0x3f; 3479c5aff182SThomas Petazzoni win_protect = 0; 3480c5aff182SThomas Petazzoni 3481c5aff182SThomas Petazzoni for (i = 0; i < dram->num_cs; i++) { 3482c5aff182SThomas Petazzoni const struct mbus_dram_window *cs = dram->cs + i; 3483c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_WIN_BASE(i), (cs->base & 0xffff0000) | 3484c5aff182SThomas Petazzoni (cs->mbus_attr << 8) | dram->mbus_dram_target_id); 3485c5aff182SThomas Petazzoni 3486c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_WIN_SIZE(i), 3487c5aff182SThomas Petazzoni (cs->size - 1) & 0xffff0000); 3488c5aff182SThomas Petazzoni 3489c5aff182SThomas Petazzoni win_enable &= ~(1 << i); 3490c5aff182SThomas Petazzoni win_protect |= 3 << (2 * i); 3491c5aff182SThomas Petazzoni } 3492c5aff182SThomas Petazzoni 3493c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_BASE_ADDR_ENABLE, win_enable); 3494db6ba9a5SMarcin Wojtas mvreg_write(pp, MVNETA_ACCESS_PROTECT_ENABLE, win_protect); 3495c5aff182SThomas Petazzoni } 3496c5aff182SThomas Petazzoni 3497c5aff182SThomas Petazzoni /* Power up the port */ 34983f1dd4bcSThomas Petazzoni static int mvneta_port_power_up(struct mvneta_port *pp, int phy_mode) 3499c5aff182SThomas Petazzoni { 35003f1dd4bcSThomas Petazzoni u32 ctrl; 3501c5aff182SThomas Petazzoni 3502c5aff182SThomas Petazzoni /* MAC Cause register should be cleared */ 3503c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_UNIT_INTR_CAUSE, 0); 3504c5aff182SThomas Petazzoni 35053f1dd4bcSThomas Petazzoni ctrl = mvreg_read(pp, MVNETA_GMAC_CTRL_2); 3506c5aff182SThomas Petazzoni 35073f1dd4bcSThomas Petazzoni /* Even though it might look weird, when we're configured in 35083f1dd4bcSThomas Petazzoni * SGMII or QSGMII mode, the RGMII bit needs to be set. 35093f1dd4bcSThomas Petazzoni */ 35103f1dd4bcSThomas Petazzoni switch(phy_mode) { 35113f1dd4bcSThomas Petazzoni case PHY_INTERFACE_MODE_QSGMII: 35123f1dd4bcSThomas Petazzoni mvreg_write(pp, MVNETA_SERDES_CFG, MVNETA_QSGMII_SERDES_PROTO); 35133f1dd4bcSThomas Petazzoni ctrl |= MVNETA_GMAC2_PCS_ENABLE | MVNETA_GMAC2_PORT_RGMII; 35143f1dd4bcSThomas Petazzoni break; 35153f1dd4bcSThomas Petazzoni case PHY_INTERFACE_MODE_SGMII: 35163f1dd4bcSThomas Petazzoni mvreg_write(pp, MVNETA_SERDES_CFG, MVNETA_SGMII_SERDES_PROTO); 35173f1dd4bcSThomas Petazzoni ctrl |= MVNETA_GMAC2_PCS_ENABLE | MVNETA_GMAC2_PORT_RGMII; 35183f1dd4bcSThomas Petazzoni break; 35193f1dd4bcSThomas Petazzoni case PHY_INTERFACE_MODE_RGMII: 35203f1dd4bcSThomas Petazzoni case PHY_INTERFACE_MODE_RGMII_ID: 35213f1dd4bcSThomas Petazzoni ctrl |= MVNETA_GMAC2_PORT_RGMII; 35223f1dd4bcSThomas Petazzoni break; 35233f1dd4bcSThomas Petazzoni default: 35243f1dd4bcSThomas Petazzoni return -EINVAL; 35253f1dd4bcSThomas Petazzoni } 3526c5aff182SThomas Petazzoni 3527c5aff182SThomas Petazzoni /* Cancel Port Reset */ 35283f1dd4bcSThomas Petazzoni ctrl &= ~MVNETA_GMAC2_PORT_RESET; 35293f1dd4bcSThomas Petazzoni mvreg_write(pp, MVNETA_GMAC_CTRL_2, ctrl); 3530c5aff182SThomas Petazzoni 3531c5aff182SThomas Petazzoni while ((mvreg_read(pp, MVNETA_GMAC_CTRL_2) & 3532c5aff182SThomas Petazzoni MVNETA_GMAC2_PORT_RESET) != 0) 3533c5aff182SThomas Petazzoni continue; 35343f1dd4bcSThomas Petazzoni 35353f1dd4bcSThomas Petazzoni return 0; 3536c5aff182SThomas Petazzoni } 3537c5aff182SThomas Petazzoni 3538c5aff182SThomas Petazzoni /* Device initialization routine */ 353903ce758eSGreg KH static int mvneta_probe(struct platform_device *pdev) 3540c5aff182SThomas Petazzoni { 3541c5aff182SThomas Petazzoni const struct mbus_dram_target_info *dram_target_info; 3542c3f0dd38SThomas Petazzoni struct resource *res; 3543c5aff182SThomas Petazzoni struct device_node *dn = pdev->dev.of_node; 3544c5aff182SThomas Petazzoni struct device_node *phy_node; 3545c5aff182SThomas Petazzoni struct mvneta_port *pp; 3546c5aff182SThomas Petazzoni struct net_device *dev; 35478cc3e439SThomas Petazzoni const char *dt_mac_addr; 35488cc3e439SThomas Petazzoni char hw_mac_addr[ETH_ALEN]; 35498cc3e439SThomas Petazzoni const char *mac_from; 3550f8af8e6eSStas Sergeev const char *managed; 35519110ee07SMarcin Wojtas int tx_csum_limit; 3552c5aff182SThomas Petazzoni int phy_mode; 3553c5aff182SThomas Petazzoni int err; 355412bb03b4SMaxime Ripard int cpu; 3555c5aff182SThomas Petazzoni 3556ee40a116SWilly Tarreau dev = alloc_etherdev_mqs(sizeof(struct mvneta_port), txq_number, rxq_number); 3557c5aff182SThomas Petazzoni if (!dev) 3558c5aff182SThomas Petazzoni return -ENOMEM; 3559c5aff182SThomas Petazzoni 3560c5aff182SThomas Petazzoni dev->irq = irq_of_parse_and_map(dn, 0); 3561c5aff182SThomas Petazzoni if (dev->irq == 0) { 3562c5aff182SThomas Petazzoni err = -EINVAL; 3563c5aff182SThomas Petazzoni goto err_free_netdev; 3564c5aff182SThomas Petazzoni } 3565c5aff182SThomas Petazzoni 3566c5aff182SThomas Petazzoni phy_node = of_parse_phandle(dn, "phy", 0); 3567c5aff182SThomas Petazzoni if (!phy_node) { 356883895bedSThomas Petazzoni if (!of_phy_is_fixed_link(dn)) { 356983895bedSThomas Petazzoni dev_err(&pdev->dev, "no PHY specified\n"); 3570c5aff182SThomas Petazzoni err = -ENODEV; 3571c5aff182SThomas Petazzoni goto err_free_irq; 3572c5aff182SThomas Petazzoni } 3573c5aff182SThomas Petazzoni 357483895bedSThomas Petazzoni err = of_phy_register_fixed_link(dn); 357583895bedSThomas Petazzoni if (err < 0) { 357683895bedSThomas Petazzoni dev_err(&pdev->dev, "cannot register fixed PHY\n"); 357783895bedSThomas Petazzoni goto err_free_irq; 357883895bedSThomas Petazzoni } 357983895bedSThomas Petazzoni 358083895bedSThomas Petazzoni /* In the case of a fixed PHY, the DT node associated 358183895bedSThomas Petazzoni * to the PHY is the Ethernet MAC DT node. 358283895bedSThomas Petazzoni */ 3583c891c24cSUwe Kleine-König phy_node = of_node_get(dn); 358483895bedSThomas Petazzoni } 358583895bedSThomas Petazzoni 3586c5aff182SThomas Petazzoni phy_mode = of_get_phy_mode(dn); 3587c5aff182SThomas Petazzoni if (phy_mode < 0) { 3588c5aff182SThomas Petazzoni dev_err(&pdev->dev, "incorrect phy-mode\n"); 3589c5aff182SThomas Petazzoni err = -EINVAL; 3590c891c24cSUwe Kleine-König goto err_put_phy_node; 3591c5aff182SThomas Petazzoni } 3592c5aff182SThomas Petazzoni 3593c5aff182SThomas Petazzoni dev->tx_queue_len = MVNETA_MAX_TXD; 3594c5aff182SThomas Petazzoni dev->watchdog_timeo = 5 * HZ; 3595c5aff182SThomas Petazzoni dev->netdev_ops = &mvneta_netdev_ops; 3596c5aff182SThomas Petazzoni 35977ad24ea4SWilfried Klaebe dev->ethtool_ops = &mvneta_eth_tool_ops; 3598c5aff182SThomas Petazzoni 3599c5aff182SThomas Petazzoni pp = netdev_priv(dev); 3600c5aff182SThomas Petazzoni pp->phy_node = phy_node; 3601c5aff182SThomas Petazzoni pp->phy_interface = phy_mode; 3602f8af8e6eSStas Sergeev 3603f8af8e6eSStas Sergeev err = of_property_read_string(dn, "managed", &managed); 3604f8af8e6eSStas Sergeev pp->use_inband_status = (err == 0 && 3605f8af8e6eSStas Sergeev strcmp(managed, "in-band-status") == 0); 3606f8642885SMaxime Ripard pp->cpu_notifier.notifier_call = mvneta_percpu_notifier; 3607c5aff182SThomas Petazzoni 360890b74c01SGregory CLEMENT pp->rxq_def = rxq_def; 360990b74c01SGregory CLEMENT 36109a401deaSGregory CLEMENT pp->indir[0] = rxq_def; 36119a401deaSGregory CLEMENT 36122804ba4eSJisheng Zhang pp->clk = devm_clk_get(&pdev->dev, "core"); 36132804ba4eSJisheng Zhang if (IS_ERR(pp->clk)) 3614189dd626SThomas Petazzoni pp->clk = devm_clk_get(&pdev->dev, NULL); 3615189dd626SThomas Petazzoni if (IS_ERR(pp->clk)) { 3616189dd626SThomas Petazzoni err = PTR_ERR(pp->clk); 3617c891c24cSUwe Kleine-König goto err_put_phy_node; 3618189dd626SThomas Petazzoni } 3619189dd626SThomas Petazzoni 3620189dd626SThomas Petazzoni clk_prepare_enable(pp->clk); 3621189dd626SThomas Petazzoni 362215cc4a4aSJisheng Zhang pp->clk_bus = devm_clk_get(&pdev->dev, "bus"); 362315cc4a4aSJisheng Zhang if (!IS_ERR(pp->clk_bus)) 362415cc4a4aSJisheng Zhang clk_prepare_enable(pp->clk_bus); 362515cc4a4aSJisheng Zhang 3626c3f0dd38SThomas Petazzoni res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 3627c3f0dd38SThomas Petazzoni pp->base = devm_ioremap_resource(&pdev->dev, res); 3628c3f0dd38SThomas Petazzoni if (IS_ERR(pp->base)) { 3629c3f0dd38SThomas Petazzoni err = PTR_ERR(pp->base); 36305445eaf3SArnaud Patard \(Rtp\) goto err_clk; 36315445eaf3SArnaud Patard \(Rtp\) } 36325445eaf3SArnaud Patard \(Rtp\) 363312bb03b4SMaxime Ripard /* Alloc per-cpu port structure */ 363412bb03b4SMaxime Ripard pp->ports = alloc_percpu(struct mvneta_pcpu_port); 363512bb03b4SMaxime Ripard if (!pp->ports) { 363612bb03b4SMaxime Ripard err = -ENOMEM; 363712bb03b4SMaxime Ripard goto err_clk; 363812bb03b4SMaxime Ripard } 363912bb03b4SMaxime Ripard 364074c41b04Swilly tarreau /* Alloc per-cpu stats */ 36411c213bd2SWANG Cong pp->stats = netdev_alloc_pcpu_stats(struct mvneta_pcpu_stats); 364274c41b04Swilly tarreau if (!pp->stats) { 364374c41b04Swilly tarreau err = -ENOMEM; 364412bb03b4SMaxime Ripard goto err_free_ports; 364574c41b04Swilly tarreau } 364674c41b04Swilly tarreau 36478cc3e439SThomas Petazzoni dt_mac_addr = of_get_mac_address(dn); 36486c7a9a3cSLuka Perkov if (dt_mac_addr) { 36498cc3e439SThomas Petazzoni mac_from = "device tree"; 36508cc3e439SThomas Petazzoni memcpy(dev->dev_addr, dt_mac_addr, ETH_ALEN); 36518cc3e439SThomas Petazzoni } else { 36528cc3e439SThomas Petazzoni mvneta_get_mac_addr(pp, hw_mac_addr); 36538cc3e439SThomas Petazzoni if (is_valid_ether_addr(hw_mac_addr)) { 36548cc3e439SThomas Petazzoni mac_from = "hardware"; 36558cc3e439SThomas Petazzoni memcpy(dev->dev_addr, hw_mac_addr, ETH_ALEN); 36568cc3e439SThomas Petazzoni } else { 36578cc3e439SThomas Petazzoni mac_from = "random"; 36588cc3e439SThomas Petazzoni eth_hw_addr_random(dev); 36598cc3e439SThomas Petazzoni } 36608cc3e439SThomas Petazzoni } 36618cc3e439SThomas Petazzoni 36629110ee07SMarcin Wojtas if (!of_property_read_u32(dn, "tx-csum-limit", &tx_csum_limit)) { 36639110ee07SMarcin Wojtas if (tx_csum_limit < 0 || 36649110ee07SMarcin Wojtas tx_csum_limit > MVNETA_TX_CSUM_MAX_SIZE) { 36659110ee07SMarcin Wojtas tx_csum_limit = MVNETA_TX_CSUM_DEF_SIZE; 36669110ee07SMarcin Wojtas dev_info(&pdev->dev, 36679110ee07SMarcin Wojtas "Wrong TX csum limit in DT, set to %dB\n", 36689110ee07SMarcin Wojtas MVNETA_TX_CSUM_DEF_SIZE); 36699110ee07SMarcin Wojtas } 36709110ee07SMarcin Wojtas } else if (of_device_is_compatible(dn, "marvell,armada-370-neta")) { 36719110ee07SMarcin Wojtas tx_csum_limit = MVNETA_TX_CSUM_DEF_SIZE; 36729110ee07SMarcin Wojtas } else { 36739110ee07SMarcin Wojtas tx_csum_limit = MVNETA_TX_CSUM_MAX_SIZE; 36749110ee07SMarcin Wojtas } 36759110ee07SMarcin Wojtas 36769110ee07SMarcin Wojtas pp->tx_csum_limit = tx_csum_limit; 3677b65657fcSSimon Guinot 3678c5aff182SThomas Petazzoni pp->tx_ring_size = MVNETA_MAX_TXD; 3679c5aff182SThomas Petazzoni pp->rx_ring_size = MVNETA_MAX_RXD; 3680c5aff182SThomas Petazzoni 3681c5aff182SThomas Petazzoni pp->dev = dev; 3682c5aff182SThomas Petazzoni SET_NETDEV_DEV(dev, &pdev->dev); 3683c5aff182SThomas Petazzoni 36849672850bSEzequiel Garcia err = mvneta_init(&pdev->dev, pp); 36859672850bSEzequiel Garcia if (err < 0) 368674c41b04Swilly tarreau goto err_free_stats; 36873f1dd4bcSThomas Petazzoni 36883f1dd4bcSThomas Petazzoni err = mvneta_port_power_up(pp, phy_mode); 36893f1dd4bcSThomas Petazzoni if (err < 0) { 36903f1dd4bcSThomas Petazzoni dev_err(&pdev->dev, "can't power up port\n"); 36919672850bSEzequiel Garcia goto err_free_stats; 36923f1dd4bcSThomas Petazzoni } 3693c5aff182SThomas Petazzoni 3694c5aff182SThomas Petazzoni dram_target_info = mv_mbus_dram_info(); 3695c5aff182SThomas Petazzoni if (dram_target_info) 3696c5aff182SThomas Petazzoni mvneta_conf_mbus_windows(pp, dram_target_info); 3697c5aff182SThomas Petazzoni 369812bb03b4SMaxime Ripard for_each_present_cpu(cpu) { 369912bb03b4SMaxime Ripard struct mvneta_pcpu_port *port = per_cpu_ptr(pp->ports, cpu); 370012bb03b4SMaxime Ripard 370112bb03b4SMaxime Ripard netif_napi_add(dev, &port->napi, mvneta_poll, NAPI_POLL_WEIGHT); 370212bb03b4SMaxime Ripard port->pp = pp; 370312bb03b4SMaxime Ripard } 3704c5aff182SThomas Petazzoni 37052adb719dSEzequiel Garcia dev->features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO; 370601ef26caSEzequiel Garcia dev->hw_features |= dev->features; 370701ef26caSEzequiel Garcia dev->vlan_features |= dev->features; 3708b50b72deSwilly tarreau dev->priv_flags |= IFF_UNICAST_FLT; 37098eef5f97SEzequiel Garcia dev->gso_max_segs = MVNETA_MAX_TSO_SEGS; 3710b50b72deSwilly tarreau 3711c5aff182SThomas Petazzoni err = register_netdev(dev); 3712c5aff182SThomas Petazzoni if (err < 0) { 3713c5aff182SThomas Petazzoni dev_err(&pdev->dev, "failed to register\n"); 37149672850bSEzequiel Garcia goto err_free_stats; 3715c5aff182SThomas Petazzoni } 3716c5aff182SThomas Petazzoni 37178cc3e439SThomas Petazzoni netdev_info(dev, "Using %s mac address %pM\n", mac_from, 37188cc3e439SThomas Petazzoni dev->dev_addr); 3719c5aff182SThomas Petazzoni 3720c5aff182SThomas Petazzoni platform_set_drvdata(pdev, pp->dev); 3721c5aff182SThomas Petazzoni 3722898b2970SStas Sergeev if (pp->use_inband_status) { 3723898b2970SStas Sergeev struct phy_device *phy = of_phy_find_device(dn); 3724898b2970SStas Sergeev 3725898b2970SStas Sergeev mvneta_fixed_link_update(pp, phy); 372604d53b20SRussell King 3727e5a03bfdSAndrew Lunn put_device(&phy->mdio.dev); 3728898b2970SStas Sergeev } 3729898b2970SStas Sergeev 3730c5aff182SThomas Petazzoni return 0; 3731c5aff182SThomas Petazzoni 373274c41b04Swilly tarreau err_free_stats: 373374c41b04Swilly tarreau free_percpu(pp->stats); 373412bb03b4SMaxime Ripard err_free_ports: 373512bb03b4SMaxime Ripard free_percpu(pp->ports); 37365445eaf3SArnaud Patard \(Rtp\) err_clk: 373715cc4a4aSJisheng Zhang clk_disable_unprepare(pp->clk_bus); 37385445eaf3SArnaud Patard \(Rtp\) clk_disable_unprepare(pp->clk); 3739c891c24cSUwe Kleine-König err_put_phy_node: 3740c891c24cSUwe Kleine-König of_node_put(phy_node); 3741c5aff182SThomas Petazzoni err_free_irq: 3742c5aff182SThomas Petazzoni irq_dispose_mapping(dev->irq); 3743c5aff182SThomas Petazzoni err_free_netdev: 3744c5aff182SThomas Petazzoni free_netdev(dev); 3745c5aff182SThomas Petazzoni return err; 3746c5aff182SThomas Petazzoni } 3747c5aff182SThomas Petazzoni 3748c5aff182SThomas Petazzoni /* Device removal routine */ 374903ce758eSGreg KH static int mvneta_remove(struct platform_device *pdev) 3750c5aff182SThomas Petazzoni { 3751c5aff182SThomas Petazzoni struct net_device *dev = platform_get_drvdata(pdev); 3752c5aff182SThomas Petazzoni struct mvneta_port *pp = netdev_priv(dev); 3753c5aff182SThomas Petazzoni 3754c5aff182SThomas Petazzoni unregister_netdev(dev); 375515cc4a4aSJisheng Zhang clk_disable_unprepare(pp->clk_bus); 3756189dd626SThomas Petazzoni clk_disable_unprepare(pp->clk); 375712bb03b4SMaxime Ripard free_percpu(pp->ports); 375874c41b04Swilly tarreau free_percpu(pp->stats); 3759c5aff182SThomas Petazzoni irq_dispose_mapping(dev->irq); 3760c891c24cSUwe Kleine-König of_node_put(pp->phy_node); 3761c5aff182SThomas Petazzoni free_netdev(dev); 3762c5aff182SThomas Petazzoni 3763c5aff182SThomas Petazzoni return 0; 3764c5aff182SThomas Petazzoni } 3765c5aff182SThomas Petazzoni 3766c5aff182SThomas Petazzoni static const struct of_device_id mvneta_match[] = { 3767c5aff182SThomas Petazzoni { .compatible = "marvell,armada-370-neta" }, 3768f522a975SSimon Guinot { .compatible = "marvell,armada-xp-neta" }, 3769c5aff182SThomas Petazzoni { } 3770c5aff182SThomas Petazzoni }; 3771c5aff182SThomas Petazzoni MODULE_DEVICE_TABLE(of, mvneta_match); 3772c5aff182SThomas Petazzoni 3773c5aff182SThomas Petazzoni static struct platform_driver mvneta_driver = { 3774c5aff182SThomas Petazzoni .probe = mvneta_probe, 377503ce758eSGreg KH .remove = mvneta_remove, 3776c5aff182SThomas Petazzoni .driver = { 3777c5aff182SThomas Petazzoni .name = MVNETA_DRIVER_NAME, 3778c5aff182SThomas Petazzoni .of_match_table = mvneta_match, 3779c5aff182SThomas Petazzoni }, 3780c5aff182SThomas Petazzoni }; 3781c5aff182SThomas Petazzoni 3782c5aff182SThomas Petazzoni module_platform_driver(mvneta_driver); 3783c5aff182SThomas Petazzoni 3784c5aff182SThomas Petazzoni MODULE_DESCRIPTION("Marvell NETA Ethernet Driver - www.marvell.com"); 3785c5aff182SThomas Petazzoni MODULE_AUTHOR("Rami Rosen <rosenr@marvell.com>, Thomas Petazzoni <thomas.petazzoni@free-electrons.com>"); 3786c5aff182SThomas Petazzoni MODULE_LICENSE("GPL"); 3787c5aff182SThomas Petazzoni 3788c5aff182SThomas Petazzoni module_param(rxq_number, int, S_IRUGO); 3789c5aff182SThomas Petazzoni module_param(txq_number, int, S_IRUGO); 3790c5aff182SThomas Petazzoni 3791c5aff182SThomas Petazzoni module_param(rxq_def, int, S_IRUGO); 3792f19fadfcSwilly tarreau module_param(rx_copybreak, int, S_IRUGO | S_IWUSR); 3793