1c5aff182SThomas Petazzoni /* 2c5aff182SThomas Petazzoni * Driver for Marvell NETA network card for Armada XP and Armada 370 SoCs. 3c5aff182SThomas Petazzoni * 4c5aff182SThomas Petazzoni * Copyright (C) 2012 Marvell 5c5aff182SThomas Petazzoni * 6c5aff182SThomas Petazzoni * Rami Rosen <rosenr@marvell.com> 7c5aff182SThomas Petazzoni * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> 8c5aff182SThomas Petazzoni * 9c5aff182SThomas Petazzoni * This file is licensed under the terms of the GNU General Public 10c5aff182SThomas Petazzoni * License version 2. This program is licensed "as is" without any 11c5aff182SThomas Petazzoni * warranty of any kind, whether express or implied. 12c5aff182SThomas Petazzoni */ 13c5aff182SThomas Petazzoni 14c5aff182SThomas Petazzoni #include <linux/kernel.h> 15c5aff182SThomas Petazzoni #include <linux/netdevice.h> 16c5aff182SThomas Petazzoni #include <linux/etherdevice.h> 17c5aff182SThomas Petazzoni #include <linux/platform_device.h> 18c5aff182SThomas Petazzoni #include <linux/skbuff.h> 19c5aff182SThomas Petazzoni #include <linux/inetdevice.h> 20c5aff182SThomas Petazzoni #include <linux/mbus.h> 21c5aff182SThomas Petazzoni #include <linux/module.h> 22c5aff182SThomas Petazzoni #include <linux/interrupt.h> 232d39d120SDavid S. Miller #include <linux/if_vlan.h> 24c5aff182SThomas Petazzoni #include <net/ip.h> 25c5aff182SThomas Petazzoni #include <net/ipv6.h> 26c3f0dd38SThomas Petazzoni #include <linux/io.h> 272adb719dSEzequiel Garcia #include <net/tso.h> 28c5aff182SThomas Petazzoni #include <linux/of.h> 29c5aff182SThomas Petazzoni #include <linux/of_irq.h> 30c5aff182SThomas Petazzoni #include <linux/of_mdio.h> 31c5aff182SThomas Petazzoni #include <linux/of_net.h> 32c5aff182SThomas Petazzoni #include <linux/of_address.h> 33c5aff182SThomas Petazzoni #include <linux/phy.h> 34189dd626SThomas Petazzoni #include <linux/clk.h> 35c5aff182SThomas Petazzoni 36c5aff182SThomas Petazzoni /* Registers */ 37c5aff182SThomas Petazzoni #define MVNETA_RXQ_CONFIG_REG(q) (0x1400 + ((q) << 2)) 38c5aff182SThomas Petazzoni #define MVNETA_RXQ_HW_BUF_ALLOC BIT(1) 39c5aff182SThomas Petazzoni #define MVNETA_RXQ_PKT_OFFSET_ALL_MASK (0xf << 8) 40c5aff182SThomas Petazzoni #define MVNETA_RXQ_PKT_OFFSET_MASK(offs) ((offs) << 8) 41c5aff182SThomas Petazzoni #define MVNETA_RXQ_THRESHOLD_REG(q) (0x14c0 + ((q) << 2)) 42c5aff182SThomas Petazzoni #define MVNETA_RXQ_NON_OCCUPIED(v) ((v) << 16) 43c5aff182SThomas Petazzoni #define MVNETA_RXQ_BASE_ADDR_REG(q) (0x1480 + ((q) << 2)) 44c5aff182SThomas Petazzoni #define MVNETA_RXQ_SIZE_REG(q) (0x14a0 + ((q) << 2)) 45c5aff182SThomas Petazzoni #define MVNETA_RXQ_BUF_SIZE_SHIFT 19 46c5aff182SThomas Petazzoni #define MVNETA_RXQ_BUF_SIZE_MASK (0x1fff << 19) 47c5aff182SThomas Petazzoni #define MVNETA_RXQ_STATUS_REG(q) (0x14e0 + ((q) << 2)) 48c5aff182SThomas Petazzoni #define MVNETA_RXQ_OCCUPIED_ALL_MASK 0x3fff 49c5aff182SThomas Petazzoni #define MVNETA_RXQ_STATUS_UPDATE_REG(q) (0x1500 + ((q) << 2)) 50c5aff182SThomas Petazzoni #define MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT 16 51c5aff182SThomas Petazzoni #define MVNETA_RXQ_ADD_NON_OCCUPIED_MAX 255 52c5aff182SThomas Petazzoni #define MVNETA_PORT_RX_RESET 0x1cc0 53c5aff182SThomas Petazzoni #define MVNETA_PORT_RX_DMA_RESET BIT(0) 54c5aff182SThomas Petazzoni #define MVNETA_PHY_ADDR 0x2000 55c5aff182SThomas Petazzoni #define MVNETA_PHY_ADDR_MASK 0x1f 56c5aff182SThomas Petazzoni #define MVNETA_MBUS_RETRY 0x2010 57c5aff182SThomas Petazzoni #define MVNETA_UNIT_INTR_CAUSE 0x2080 58c5aff182SThomas Petazzoni #define MVNETA_UNIT_CONTROL 0x20B0 59c5aff182SThomas Petazzoni #define MVNETA_PHY_POLLING_ENABLE BIT(1) 60c5aff182SThomas Petazzoni #define MVNETA_WIN_BASE(w) (0x2200 + ((w) << 3)) 61c5aff182SThomas Petazzoni #define MVNETA_WIN_SIZE(w) (0x2204 + ((w) << 3)) 62c5aff182SThomas Petazzoni #define MVNETA_WIN_REMAP(w) (0x2280 + ((w) << 2)) 63c5aff182SThomas Petazzoni #define MVNETA_BASE_ADDR_ENABLE 0x2290 64c5aff182SThomas Petazzoni #define MVNETA_PORT_CONFIG 0x2400 65c5aff182SThomas Petazzoni #define MVNETA_UNI_PROMISC_MODE BIT(0) 66c5aff182SThomas Petazzoni #define MVNETA_DEF_RXQ(q) ((q) << 1) 67c5aff182SThomas Petazzoni #define MVNETA_DEF_RXQ_ARP(q) ((q) << 4) 68c5aff182SThomas Petazzoni #define MVNETA_TX_UNSET_ERR_SUM BIT(12) 69c5aff182SThomas Petazzoni #define MVNETA_DEF_RXQ_TCP(q) ((q) << 16) 70c5aff182SThomas Petazzoni #define MVNETA_DEF_RXQ_UDP(q) ((q) << 19) 71c5aff182SThomas Petazzoni #define MVNETA_DEF_RXQ_BPDU(q) ((q) << 22) 72c5aff182SThomas Petazzoni #define MVNETA_RX_CSUM_WITH_PSEUDO_HDR BIT(25) 73c5aff182SThomas Petazzoni #define MVNETA_PORT_CONFIG_DEFL_VALUE(q) (MVNETA_DEF_RXQ(q) | \ 74c5aff182SThomas Petazzoni MVNETA_DEF_RXQ_ARP(q) | \ 75c5aff182SThomas Petazzoni MVNETA_DEF_RXQ_TCP(q) | \ 76c5aff182SThomas Petazzoni MVNETA_DEF_RXQ_UDP(q) | \ 77c5aff182SThomas Petazzoni MVNETA_DEF_RXQ_BPDU(q) | \ 78c5aff182SThomas Petazzoni MVNETA_TX_UNSET_ERR_SUM | \ 79c5aff182SThomas Petazzoni MVNETA_RX_CSUM_WITH_PSEUDO_HDR) 80c5aff182SThomas Petazzoni #define MVNETA_PORT_CONFIG_EXTEND 0x2404 81c5aff182SThomas Petazzoni #define MVNETA_MAC_ADDR_LOW 0x2414 82c5aff182SThomas Petazzoni #define MVNETA_MAC_ADDR_HIGH 0x2418 83c5aff182SThomas Petazzoni #define MVNETA_SDMA_CONFIG 0x241c 84c5aff182SThomas Petazzoni #define MVNETA_SDMA_BRST_SIZE_16 4 85c5aff182SThomas Petazzoni #define MVNETA_RX_BRST_SZ_MASK(burst) ((burst) << 1) 86c5aff182SThomas Petazzoni #define MVNETA_RX_NO_DATA_SWAP BIT(4) 87c5aff182SThomas Petazzoni #define MVNETA_TX_NO_DATA_SWAP BIT(5) 889ad8fef6SThomas Petazzoni #define MVNETA_DESC_SWAP BIT(6) 89c5aff182SThomas Petazzoni #define MVNETA_TX_BRST_SZ_MASK(burst) ((burst) << 22) 90c5aff182SThomas Petazzoni #define MVNETA_PORT_STATUS 0x2444 91c5aff182SThomas Petazzoni #define MVNETA_TX_IN_PRGRS BIT(1) 92c5aff182SThomas Petazzoni #define MVNETA_TX_FIFO_EMPTY BIT(8) 93c5aff182SThomas Petazzoni #define MVNETA_RX_MIN_FRAME_SIZE 0x247c 943f1dd4bcSThomas Petazzoni #define MVNETA_SERDES_CFG 0x24A0 955445eaf3SArnaud Patard \(Rtp\) #define MVNETA_SGMII_SERDES_PROTO 0x0cc7 963f1dd4bcSThomas Petazzoni #define MVNETA_QSGMII_SERDES_PROTO 0x0667 97c5aff182SThomas Petazzoni #define MVNETA_TYPE_PRIO 0x24bc 98c5aff182SThomas Petazzoni #define MVNETA_FORCE_UNI BIT(21) 99c5aff182SThomas Petazzoni #define MVNETA_TXQ_CMD_1 0x24e4 100c5aff182SThomas Petazzoni #define MVNETA_TXQ_CMD 0x2448 101c5aff182SThomas Petazzoni #define MVNETA_TXQ_DISABLE_SHIFT 8 102c5aff182SThomas Petazzoni #define MVNETA_TXQ_ENABLE_MASK 0x000000ff 103898b2970SStas Sergeev #define MVNETA_GMAC_CLOCK_DIVIDER 0x24f4 104898b2970SStas Sergeev #define MVNETA_GMAC_1MS_CLOCK_ENABLE BIT(31) 105c5aff182SThomas Petazzoni #define MVNETA_ACC_MODE 0x2500 106c5aff182SThomas Petazzoni #define MVNETA_CPU_MAP(cpu) (0x2540 + ((cpu) << 2)) 107c5aff182SThomas Petazzoni #define MVNETA_CPU_RXQ_ACCESS_ALL_MASK 0x000000ff 108c5aff182SThomas Petazzoni #define MVNETA_CPU_TXQ_ACCESS_ALL_MASK 0x0000ff00 109c5aff182SThomas Petazzoni #define MVNETA_RXQ_TIME_COAL_REG(q) (0x2580 + ((q) << 2)) 11040ba35e7Swilly tarreau 11140ba35e7Swilly tarreau /* Exception Interrupt Port/Queue Cause register */ 11240ba35e7Swilly tarreau 113c5aff182SThomas Petazzoni #define MVNETA_INTR_NEW_CAUSE 0x25a0 114c5aff182SThomas Petazzoni #define MVNETA_INTR_NEW_MASK 0x25a4 11540ba35e7Swilly tarreau 11640ba35e7Swilly tarreau /* bits 0..7 = TXQ SENT, one bit per queue. 11740ba35e7Swilly tarreau * bits 8..15 = RXQ OCCUP, one bit per queue. 11840ba35e7Swilly tarreau * bits 16..23 = RXQ FREE, one bit per queue. 11940ba35e7Swilly tarreau * bit 29 = OLD_REG_SUM, see old reg ? 12040ba35e7Swilly tarreau * bit 30 = TX_ERR_SUM, one bit for 4 ports 12140ba35e7Swilly tarreau * bit 31 = MISC_SUM, one bit for 4 ports 12240ba35e7Swilly tarreau */ 12340ba35e7Swilly tarreau #define MVNETA_TX_INTR_MASK(nr_txqs) (((1 << nr_txqs) - 1) << 0) 12440ba35e7Swilly tarreau #define MVNETA_TX_INTR_MASK_ALL (0xff << 0) 12540ba35e7Swilly tarreau #define MVNETA_RX_INTR_MASK(nr_rxqs) (((1 << nr_rxqs) - 1) << 8) 12640ba35e7Swilly tarreau #define MVNETA_RX_INTR_MASK_ALL (0xff << 8) 127898b2970SStas Sergeev #define MVNETA_MISCINTR_INTR_MASK BIT(31) 12840ba35e7Swilly tarreau 129c5aff182SThomas Petazzoni #define MVNETA_INTR_OLD_CAUSE 0x25a8 130c5aff182SThomas Petazzoni #define MVNETA_INTR_OLD_MASK 0x25ac 13140ba35e7Swilly tarreau 13240ba35e7Swilly tarreau /* Data Path Port/Queue Cause Register */ 133c5aff182SThomas Petazzoni #define MVNETA_INTR_MISC_CAUSE 0x25b0 134c5aff182SThomas Petazzoni #define MVNETA_INTR_MISC_MASK 0x25b4 13540ba35e7Swilly tarreau 13640ba35e7Swilly tarreau #define MVNETA_CAUSE_PHY_STATUS_CHANGE BIT(0) 13740ba35e7Swilly tarreau #define MVNETA_CAUSE_LINK_CHANGE BIT(1) 13840ba35e7Swilly tarreau #define MVNETA_CAUSE_PTP BIT(4) 13940ba35e7Swilly tarreau 14040ba35e7Swilly tarreau #define MVNETA_CAUSE_INTERNAL_ADDR_ERR BIT(7) 14140ba35e7Swilly tarreau #define MVNETA_CAUSE_RX_OVERRUN BIT(8) 14240ba35e7Swilly tarreau #define MVNETA_CAUSE_RX_CRC_ERROR BIT(9) 14340ba35e7Swilly tarreau #define MVNETA_CAUSE_RX_LARGE_PKT BIT(10) 14440ba35e7Swilly tarreau #define MVNETA_CAUSE_TX_UNDERUN BIT(11) 14540ba35e7Swilly tarreau #define MVNETA_CAUSE_PRBS_ERR BIT(12) 14640ba35e7Swilly tarreau #define MVNETA_CAUSE_PSC_SYNC_CHANGE BIT(13) 14740ba35e7Swilly tarreau #define MVNETA_CAUSE_SERDES_SYNC_ERR BIT(14) 14840ba35e7Swilly tarreau 14940ba35e7Swilly tarreau #define MVNETA_CAUSE_BMU_ALLOC_ERR_SHIFT 16 15040ba35e7Swilly tarreau #define MVNETA_CAUSE_BMU_ALLOC_ERR_ALL_MASK (0xF << MVNETA_CAUSE_BMU_ALLOC_ERR_SHIFT) 15140ba35e7Swilly tarreau #define MVNETA_CAUSE_BMU_ALLOC_ERR_MASK(pool) (1 << (MVNETA_CAUSE_BMU_ALLOC_ERR_SHIFT + (pool))) 15240ba35e7Swilly tarreau 15340ba35e7Swilly tarreau #define MVNETA_CAUSE_TXQ_ERROR_SHIFT 24 15440ba35e7Swilly tarreau #define MVNETA_CAUSE_TXQ_ERROR_ALL_MASK (0xFF << MVNETA_CAUSE_TXQ_ERROR_SHIFT) 15540ba35e7Swilly tarreau #define MVNETA_CAUSE_TXQ_ERROR_MASK(q) (1 << (MVNETA_CAUSE_TXQ_ERROR_SHIFT + (q))) 15640ba35e7Swilly tarreau 157c5aff182SThomas Petazzoni #define MVNETA_INTR_ENABLE 0x25b8 158c5aff182SThomas Petazzoni #define MVNETA_TXQ_INTR_ENABLE_ALL_MASK 0x0000ff00 15940ba35e7Swilly tarreau #define MVNETA_RXQ_INTR_ENABLE_ALL_MASK 0xff000000 // note: neta says it's 0x000000FF 16040ba35e7Swilly tarreau 161c5aff182SThomas Petazzoni #define MVNETA_RXQ_CMD 0x2680 162c5aff182SThomas Petazzoni #define MVNETA_RXQ_DISABLE_SHIFT 8 163c5aff182SThomas Petazzoni #define MVNETA_RXQ_ENABLE_MASK 0x000000ff 164c5aff182SThomas Petazzoni #define MVETH_TXQ_TOKEN_COUNT_REG(q) (0x2700 + ((q) << 4)) 165c5aff182SThomas Petazzoni #define MVETH_TXQ_TOKEN_CFG_REG(q) (0x2704 + ((q) << 4)) 166c5aff182SThomas Petazzoni #define MVNETA_GMAC_CTRL_0 0x2c00 167c5aff182SThomas Petazzoni #define MVNETA_GMAC_MAX_RX_SIZE_SHIFT 2 168c5aff182SThomas Petazzoni #define MVNETA_GMAC_MAX_RX_SIZE_MASK 0x7ffc 169c5aff182SThomas Petazzoni #define MVNETA_GMAC0_PORT_ENABLE BIT(0) 170c5aff182SThomas Petazzoni #define MVNETA_GMAC_CTRL_2 0x2c08 171898b2970SStas Sergeev #define MVNETA_GMAC2_INBAND_AN_ENABLE BIT(0) 172a79121d3SThomas Petazzoni #define MVNETA_GMAC2_PCS_ENABLE BIT(3) 173c5aff182SThomas Petazzoni #define MVNETA_GMAC2_PORT_RGMII BIT(4) 174c5aff182SThomas Petazzoni #define MVNETA_GMAC2_PORT_RESET BIT(6) 175c5aff182SThomas Petazzoni #define MVNETA_GMAC_STATUS 0x2c10 176c5aff182SThomas Petazzoni #define MVNETA_GMAC_LINK_UP BIT(0) 177c5aff182SThomas Petazzoni #define MVNETA_GMAC_SPEED_1000 BIT(1) 178c5aff182SThomas Petazzoni #define MVNETA_GMAC_SPEED_100 BIT(2) 179c5aff182SThomas Petazzoni #define MVNETA_GMAC_FULL_DUPLEX BIT(3) 180c5aff182SThomas Petazzoni #define MVNETA_GMAC_RX_FLOW_CTRL_ENABLE BIT(4) 181c5aff182SThomas Petazzoni #define MVNETA_GMAC_TX_FLOW_CTRL_ENABLE BIT(5) 182c5aff182SThomas Petazzoni #define MVNETA_GMAC_RX_FLOW_CTRL_ACTIVE BIT(6) 183c5aff182SThomas Petazzoni #define MVNETA_GMAC_TX_FLOW_CTRL_ACTIVE BIT(7) 184c5aff182SThomas Petazzoni #define MVNETA_GMAC_AUTONEG_CONFIG 0x2c0c 185c5aff182SThomas Petazzoni #define MVNETA_GMAC_FORCE_LINK_DOWN BIT(0) 186c5aff182SThomas Petazzoni #define MVNETA_GMAC_FORCE_LINK_PASS BIT(1) 187898b2970SStas Sergeev #define MVNETA_GMAC_INBAND_AN_ENABLE BIT(2) 188c5aff182SThomas Petazzoni #define MVNETA_GMAC_CONFIG_MII_SPEED BIT(5) 189c5aff182SThomas Petazzoni #define MVNETA_GMAC_CONFIG_GMII_SPEED BIT(6) 19071408602SThomas Petazzoni #define MVNETA_GMAC_AN_SPEED_EN BIT(7) 191898b2970SStas Sergeev #define MVNETA_GMAC_AN_FLOW_CTRL_EN BIT(11) 192c5aff182SThomas Petazzoni #define MVNETA_GMAC_CONFIG_FULL_DUPLEX BIT(12) 19371408602SThomas Petazzoni #define MVNETA_GMAC_AN_DUPLEX_EN BIT(13) 194c5aff182SThomas Petazzoni #define MVNETA_MIB_COUNTERS_BASE 0x3080 195c5aff182SThomas Petazzoni #define MVNETA_MIB_LATE_COLLISION 0x7c 196c5aff182SThomas Petazzoni #define MVNETA_DA_FILT_SPEC_MCAST 0x3400 197c5aff182SThomas Petazzoni #define MVNETA_DA_FILT_OTH_MCAST 0x3500 198c5aff182SThomas Petazzoni #define MVNETA_DA_FILT_UCAST_BASE 0x3600 199c5aff182SThomas Petazzoni #define MVNETA_TXQ_BASE_ADDR_REG(q) (0x3c00 + ((q) << 2)) 200c5aff182SThomas Petazzoni #define MVNETA_TXQ_SIZE_REG(q) (0x3c20 + ((q) << 2)) 201c5aff182SThomas Petazzoni #define MVNETA_TXQ_SENT_THRESH_ALL_MASK 0x3fff0000 202c5aff182SThomas Petazzoni #define MVNETA_TXQ_SENT_THRESH_MASK(coal) ((coal) << 16) 203c5aff182SThomas Petazzoni #define MVNETA_TXQ_UPDATE_REG(q) (0x3c60 + ((q) << 2)) 204c5aff182SThomas Petazzoni #define MVNETA_TXQ_DEC_SENT_SHIFT 16 205c5aff182SThomas Petazzoni #define MVNETA_TXQ_STATUS_REG(q) (0x3c40 + ((q) << 2)) 206c5aff182SThomas Petazzoni #define MVNETA_TXQ_SENT_DESC_SHIFT 16 207c5aff182SThomas Petazzoni #define MVNETA_TXQ_SENT_DESC_MASK 0x3fff0000 208c5aff182SThomas Petazzoni #define MVNETA_PORT_TX_RESET 0x3cf0 209c5aff182SThomas Petazzoni #define MVNETA_PORT_TX_DMA_RESET BIT(0) 210c5aff182SThomas Petazzoni #define MVNETA_TX_MTU 0x3e0c 211c5aff182SThomas Petazzoni #define MVNETA_TX_TOKEN_SIZE 0x3e14 212c5aff182SThomas Petazzoni #define MVNETA_TX_TOKEN_SIZE_MAX 0xffffffff 213c5aff182SThomas Petazzoni #define MVNETA_TXQ_TOKEN_SIZE_REG(q) (0x3e40 + ((q) << 2)) 214c5aff182SThomas Petazzoni #define MVNETA_TXQ_TOKEN_SIZE_MAX 0x7fffffff 215c5aff182SThomas Petazzoni 216c5aff182SThomas Petazzoni #define MVNETA_CAUSE_TXQ_SENT_DESC_ALL_MASK 0xff 217c5aff182SThomas Petazzoni 218c5aff182SThomas Petazzoni /* Descriptor ring Macros */ 219c5aff182SThomas Petazzoni #define MVNETA_QUEUE_NEXT_DESC(q, index) \ 220c5aff182SThomas Petazzoni (((index) < (q)->last_desc) ? ((index) + 1) : 0) 221c5aff182SThomas Petazzoni 222c5aff182SThomas Petazzoni /* Various constants */ 223c5aff182SThomas Petazzoni 224c5aff182SThomas Petazzoni /* Coalescing */ 225aebea2baSwilly tarreau #define MVNETA_TXDONE_COAL_PKTS 1 226c5aff182SThomas Petazzoni #define MVNETA_RX_COAL_PKTS 32 227c5aff182SThomas Petazzoni #define MVNETA_RX_COAL_USEC 100 228c5aff182SThomas Petazzoni 2296a20c175SThomas Petazzoni /* The two bytes Marvell header. Either contains a special value used 230c5aff182SThomas Petazzoni * by Marvell switches when a specific hardware mode is enabled (not 231c5aff182SThomas Petazzoni * supported by this driver) or is filled automatically by zeroes on 232c5aff182SThomas Petazzoni * the RX side. Those two bytes being at the front of the Ethernet 233c5aff182SThomas Petazzoni * header, they allow to have the IP header aligned on a 4 bytes 234c5aff182SThomas Petazzoni * boundary automatically: the hardware skips those two bytes on its 235c5aff182SThomas Petazzoni * own. 236c5aff182SThomas Petazzoni */ 237c5aff182SThomas Petazzoni #define MVNETA_MH_SIZE 2 238c5aff182SThomas Petazzoni 239c5aff182SThomas Petazzoni #define MVNETA_VLAN_TAG_LEN 4 240c5aff182SThomas Petazzoni 241c5aff182SThomas Petazzoni #define MVNETA_CPU_D_CACHE_LINE_SIZE 32 242c5aff182SThomas Petazzoni #define MVNETA_TX_CSUM_MAX_SIZE 9800 243c5aff182SThomas Petazzoni #define MVNETA_ACC_MODE_EXT 1 244c5aff182SThomas Petazzoni 245c5aff182SThomas Petazzoni /* Timeout constants */ 246c5aff182SThomas Petazzoni #define MVNETA_TX_DISABLE_TIMEOUT_MSEC 1000 247c5aff182SThomas Petazzoni #define MVNETA_RX_DISABLE_TIMEOUT_MSEC 1000 248c5aff182SThomas Petazzoni #define MVNETA_TX_FIFO_EMPTY_TIMEOUT 10000 249c5aff182SThomas Petazzoni 250c5aff182SThomas Petazzoni #define MVNETA_TX_MTU_MAX 0x3ffff 251c5aff182SThomas Petazzoni 2522adb719dSEzequiel Garcia /* TSO header size */ 2532adb719dSEzequiel Garcia #define TSO_HEADER_SIZE 128 2542adb719dSEzequiel Garcia 255c5aff182SThomas Petazzoni /* Max number of Rx descriptors */ 256c5aff182SThomas Petazzoni #define MVNETA_MAX_RXD 128 257c5aff182SThomas Petazzoni 258c5aff182SThomas Petazzoni /* Max number of Tx descriptors */ 259c5aff182SThomas Petazzoni #define MVNETA_MAX_TXD 532 260c5aff182SThomas Petazzoni 2618eef5f97SEzequiel Garcia /* Max number of allowed TCP segments for software TSO */ 2628eef5f97SEzequiel Garcia #define MVNETA_MAX_TSO_SEGS 100 2638eef5f97SEzequiel Garcia 2648eef5f97SEzequiel Garcia #define MVNETA_MAX_SKB_DESCS (MVNETA_MAX_TSO_SEGS * 2 + MAX_SKB_FRAGS) 2658eef5f97SEzequiel Garcia 266c5aff182SThomas Petazzoni /* descriptor aligned size */ 267c5aff182SThomas Petazzoni #define MVNETA_DESC_ALIGNED_SIZE 32 268c5aff182SThomas Petazzoni 269c5aff182SThomas Petazzoni #define MVNETA_RX_PKT_SIZE(mtu) \ 270c5aff182SThomas Petazzoni ALIGN((mtu) + MVNETA_MH_SIZE + MVNETA_VLAN_TAG_LEN + \ 271c5aff182SThomas Petazzoni ETH_HLEN + ETH_FCS_LEN, \ 272c5aff182SThomas Petazzoni MVNETA_CPU_D_CACHE_LINE_SIZE) 273c5aff182SThomas Petazzoni 2742e3173a3SEzequiel Garcia #define IS_TSO_HEADER(txq, addr) \ 2752e3173a3SEzequiel Garcia ((addr >= txq->tso_hdrs_phys) && \ 2762e3173a3SEzequiel Garcia (addr < txq->tso_hdrs_phys + txq->size * TSO_HEADER_SIZE)) 2772e3173a3SEzequiel Garcia 278c5aff182SThomas Petazzoni #define MVNETA_RX_BUF_SIZE(pkt_size) ((pkt_size) + NET_SKB_PAD) 279c5aff182SThomas Petazzoni 28074c41b04Swilly tarreau struct mvneta_pcpu_stats { 281c5aff182SThomas Petazzoni struct u64_stats_sync syncp; 28274c41b04Swilly tarreau u64 rx_packets; 28374c41b04Swilly tarreau u64 rx_bytes; 28474c41b04Swilly tarreau u64 tx_packets; 28574c41b04Swilly tarreau u64 tx_bytes; 286c5aff182SThomas Petazzoni }; 287c5aff182SThomas Petazzoni 288c5aff182SThomas Petazzoni struct mvneta_port { 289c5aff182SThomas Petazzoni int pkt_size; 2908ec2cd48Swilly tarreau unsigned int frag_size; 291c5aff182SThomas Petazzoni void __iomem *base; 292c5aff182SThomas Petazzoni struct mvneta_rx_queue *rxqs; 293c5aff182SThomas Petazzoni struct mvneta_tx_queue *txqs; 294c5aff182SThomas Petazzoni struct net_device *dev; 295c5aff182SThomas Petazzoni 296c5aff182SThomas Petazzoni u32 cause_rx_tx; 297c5aff182SThomas Petazzoni struct napi_struct napi; 298c5aff182SThomas Petazzoni 299c5aff182SThomas Petazzoni /* Core clock */ 300189dd626SThomas Petazzoni struct clk *clk; 301c5aff182SThomas Petazzoni u8 mcast_count[256]; 302c5aff182SThomas Petazzoni u16 tx_ring_size; 303c5aff182SThomas Petazzoni u16 rx_ring_size; 30474c41b04Swilly tarreau struct mvneta_pcpu_stats *stats; 305c5aff182SThomas Petazzoni 306c5aff182SThomas Petazzoni struct mii_bus *mii_bus; 307c5aff182SThomas Petazzoni struct phy_device *phy_dev; 308c5aff182SThomas Petazzoni phy_interface_t phy_interface; 309c5aff182SThomas Petazzoni struct device_node *phy_node; 310c5aff182SThomas Petazzoni unsigned int link; 311c5aff182SThomas Petazzoni unsigned int duplex; 312c5aff182SThomas Petazzoni unsigned int speed; 313b65657fcSSimon Guinot unsigned int tx_csum_limit; 314898b2970SStas Sergeev int use_inband_status:1; 315c5aff182SThomas Petazzoni }; 316c5aff182SThomas Petazzoni 3176a20c175SThomas Petazzoni /* The mvneta_tx_desc and mvneta_rx_desc structures describe the 318c5aff182SThomas Petazzoni * layout of the transmit and reception DMA descriptors, and their 319c5aff182SThomas Petazzoni * layout is therefore defined by the hardware design 320c5aff182SThomas Petazzoni */ 3216083ed44SThomas Petazzoni 322c5aff182SThomas Petazzoni #define MVNETA_TX_L3_OFF_SHIFT 0 323c5aff182SThomas Petazzoni #define MVNETA_TX_IP_HLEN_SHIFT 8 324c5aff182SThomas Petazzoni #define MVNETA_TX_L4_UDP BIT(16) 325c5aff182SThomas Petazzoni #define MVNETA_TX_L3_IP6 BIT(17) 326c5aff182SThomas Petazzoni #define MVNETA_TXD_IP_CSUM BIT(18) 327c5aff182SThomas Petazzoni #define MVNETA_TXD_Z_PAD BIT(19) 328c5aff182SThomas Petazzoni #define MVNETA_TXD_L_DESC BIT(20) 329c5aff182SThomas Petazzoni #define MVNETA_TXD_F_DESC BIT(21) 330c5aff182SThomas Petazzoni #define MVNETA_TXD_FLZ_DESC (MVNETA_TXD_Z_PAD | \ 331c5aff182SThomas Petazzoni MVNETA_TXD_L_DESC | \ 332c5aff182SThomas Petazzoni MVNETA_TXD_F_DESC) 333c5aff182SThomas Petazzoni #define MVNETA_TX_L4_CSUM_FULL BIT(30) 334c5aff182SThomas Petazzoni #define MVNETA_TX_L4_CSUM_NOT BIT(31) 335c5aff182SThomas Petazzoni 336c5aff182SThomas Petazzoni #define MVNETA_RXD_ERR_CRC 0x0 337c5aff182SThomas Petazzoni #define MVNETA_RXD_ERR_SUMMARY BIT(16) 338c5aff182SThomas Petazzoni #define MVNETA_RXD_ERR_OVERRUN BIT(17) 339c5aff182SThomas Petazzoni #define MVNETA_RXD_ERR_LEN BIT(18) 340c5aff182SThomas Petazzoni #define MVNETA_RXD_ERR_RESOURCE (BIT(17) | BIT(18)) 341c5aff182SThomas Petazzoni #define MVNETA_RXD_ERR_CODE_MASK (BIT(17) | BIT(18)) 342c5aff182SThomas Petazzoni #define MVNETA_RXD_L3_IP4 BIT(25) 343c5aff182SThomas Petazzoni #define MVNETA_RXD_FIRST_LAST_DESC (BIT(26) | BIT(27)) 344c5aff182SThomas Petazzoni #define MVNETA_RXD_L4_CSUM_OK BIT(30) 345c5aff182SThomas Petazzoni 3469ad8fef6SThomas Petazzoni #if defined(__LITTLE_ENDIAN) 3476083ed44SThomas Petazzoni struct mvneta_tx_desc { 3486083ed44SThomas Petazzoni u32 command; /* Options used by HW for packet transmitting.*/ 3496083ed44SThomas Petazzoni u16 reserverd1; /* csum_l4 (for future use) */ 3506083ed44SThomas Petazzoni u16 data_size; /* Data size of transmitted packet in bytes */ 3516083ed44SThomas Petazzoni u32 buf_phys_addr; /* Physical addr of transmitted buffer */ 3526083ed44SThomas Petazzoni u32 reserved2; /* hw_cmd - (for future use, PMT) */ 3536083ed44SThomas Petazzoni u32 reserved3[4]; /* Reserved - (for future use) */ 3546083ed44SThomas Petazzoni }; 3556083ed44SThomas Petazzoni 3566083ed44SThomas Petazzoni struct mvneta_rx_desc { 3576083ed44SThomas Petazzoni u32 status; /* Info about received packet */ 358c5aff182SThomas Petazzoni u16 reserved1; /* pnc_info - (for future use, PnC) */ 359c5aff182SThomas Petazzoni u16 data_size; /* Size of received packet in bytes */ 3606083ed44SThomas Petazzoni 361c5aff182SThomas Petazzoni u32 buf_phys_addr; /* Physical address of the buffer */ 362c5aff182SThomas Petazzoni u32 reserved2; /* pnc_flow_id (for future use, PnC) */ 3636083ed44SThomas Petazzoni 364c5aff182SThomas Petazzoni u32 buf_cookie; /* cookie for access to RX buffer in rx path */ 365c5aff182SThomas Petazzoni u16 reserved3; /* prefetch_cmd, for future use */ 366c5aff182SThomas Petazzoni u16 reserved4; /* csum_l4 - (for future use, PnC) */ 3676083ed44SThomas Petazzoni 368c5aff182SThomas Petazzoni u32 reserved5; /* pnc_extra PnC (for future use, PnC) */ 369c5aff182SThomas Petazzoni u32 reserved6; /* hw_cmd (for future use, PnC and HWF) */ 370c5aff182SThomas Petazzoni }; 3719ad8fef6SThomas Petazzoni #else 3729ad8fef6SThomas Petazzoni struct mvneta_tx_desc { 3739ad8fef6SThomas Petazzoni u16 data_size; /* Data size of transmitted packet in bytes */ 3749ad8fef6SThomas Petazzoni u16 reserverd1; /* csum_l4 (for future use) */ 3759ad8fef6SThomas Petazzoni u32 command; /* Options used by HW for packet transmitting.*/ 3769ad8fef6SThomas Petazzoni u32 reserved2; /* hw_cmd - (for future use, PMT) */ 3779ad8fef6SThomas Petazzoni u32 buf_phys_addr; /* Physical addr of transmitted buffer */ 3789ad8fef6SThomas Petazzoni u32 reserved3[4]; /* Reserved - (for future use) */ 3799ad8fef6SThomas Petazzoni }; 3809ad8fef6SThomas Petazzoni 3819ad8fef6SThomas Petazzoni struct mvneta_rx_desc { 3829ad8fef6SThomas Petazzoni u16 data_size; /* Size of received packet in bytes */ 3839ad8fef6SThomas Petazzoni u16 reserved1; /* pnc_info - (for future use, PnC) */ 3849ad8fef6SThomas Petazzoni u32 status; /* Info about received packet */ 3859ad8fef6SThomas Petazzoni 3869ad8fef6SThomas Petazzoni u32 reserved2; /* pnc_flow_id (for future use, PnC) */ 3879ad8fef6SThomas Petazzoni u32 buf_phys_addr; /* Physical address of the buffer */ 3889ad8fef6SThomas Petazzoni 3899ad8fef6SThomas Petazzoni u16 reserved4; /* csum_l4 - (for future use, PnC) */ 3909ad8fef6SThomas Petazzoni u16 reserved3; /* prefetch_cmd, for future use */ 3919ad8fef6SThomas Petazzoni u32 buf_cookie; /* cookie for access to RX buffer in rx path */ 3929ad8fef6SThomas Petazzoni 3939ad8fef6SThomas Petazzoni u32 reserved5; /* pnc_extra PnC (for future use, PnC) */ 3949ad8fef6SThomas Petazzoni u32 reserved6; /* hw_cmd (for future use, PnC and HWF) */ 3959ad8fef6SThomas Petazzoni }; 3969ad8fef6SThomas Petazzoni #endif 397c5aff182SThomas Petazzoni 398c5aff182SThomas Petazzoni struct mvneta_tx_queue { 399c5aff182SThomas Petazzoni /* Number of this TX queue, in the range 0-7 */ 400c5aff182SThomas Petazzoni u8 id; 401c5aff182SThomas Petazzoni 402c5aff182SThomas Petazzoni /* Number of TX DMA descriptors in the descriptor ring */ 403c5aff182SThomas Petazzoni int size; 404c5aff182SThomas Petazzoni 405c5aff182SThomas Petazzoni /* Number of currently used TX DMA descriptor in the 4066a20c175SThomas Petazzoni * descriptor ring 4076a20c175SThomas Petazzoni */ 408c5aff182SThomas Petazzoni int count; 4098eef5f97SEzequiel Garcia int tx_stop_threshold; 4108eef5f97SEzequiel Garcia int tx_wake_threshold; 411c5aff182SThomas Petazzoni 412c5aff182SThomas Petazzoni /* Array of transmitted skb */ 413c5aff182SThomas Petazzoni struct sk_buff **tx_skb; 414c5aff182SThomas Petazzoni 415c5aff182SThomas Petazzoni /* Index of last TX DMA descriptor that was inserted */ 416c5aff182SThomas Petazzoni int txq_put_index; 417c5aff182SThomas Petazzoni 418c5aff182SThomas Petazzoni /* Index of the TX DMA descriptor to be cleaned up */ 419c5aff182SThomas Petazzoni int txq_get_index; 420c5aff182SThomas Petazzoni 421c5aff182SThomas Petazzoni u32 done_pkts_coal; 422c5aff182SThomas Petazzoni 423c5aff182SThomas Petazzoni /* Virtual address of the TX DMA descriptors array */ 424c5aff182SThomas Petazzoni struct mvneta_tx_desc *descs; 425c5aff182SThomas Petazzoni 426c5aff182SThomas Petazzoni /* DMA address of the TX DMA descriptors array */ 427c5aff182SThomas Petazzoni dma_addr_t descs_phys; 428c5aff182SThomas Petazzoni 429c5aff182SThomas Petazzoni /* Index of the last TX DMA descriptor */ 430c5aff182SThomas Petazzoni int last_desc; 431c5aff182SThomas Petazzoni 432c5aff182SThomas Petazzoni /* Index of the next TX DMA descriptor to process */ 433c5aff182SThomas Petazzoni int next_desc_to_proc; 4342adb719dSEzequiel Garcia 4352adb719dSEzequiel Garcia /* DMA buffers for TSO headers */ 4362adb719dSEzequiel Garcia char *tso_hdrs; 4372adb719dSEzequiel Garcia 4382adb719dSEzequiel Garcia /* DMA address of TSO headers */ 4392adb719dSEzequiel Garcia dma_addr_t tso_hdrs_phys; 440c5aff182SThomas Petazzoni }; 441c5aff182SThomas Petazzoni 442c5aff182SThomas Petazzoni struct mvneta_rx_queue { 443c5aff182SThomas Petazzoni /* rx queue number, in the range 0-7 */ 444c5aff182SThomas Petazzoni u8 id; 445c5aff182SThomas Petazzoni 446c5aff182SThomas Petazzoni /* num of rx descriptors in the rx descriptor ring */ 447c5aff182SThomas Petazzoni int size; 448c5aff182SThomas Petazzoni 449c5aff182SThomas Petazzoni /* counter of times when mvneta_refill() failed */ 450c5aff182SThomas Petazzoni int missed; 451c5aff182SThomas Petazzoni 452c5aff182SThomas Petazzoni u32 pkts_coal; 453c5aff182SThomas Petazzoni u32 time_coal; 454c5aff182SThomas Petazzoni 455c5aff182SThomas Petazzoni /* Virtual address of the RX DMA descriptors array */ 456c5aff182SThomas Petazzoni struct mvneta_rx_desc *descs; 457c5aff182SThomas Petazzoni 458c5aff182SThomas Petazzoni /* DMA address of the RX DMA descriptors array */ 459c5aff182SThomas Petazzoni dma_addr_t descs_phys; 460c5aff182SThomas Petazzoni 461c5aff182SThomas Petazzoni /* Index of the last RX DMA descriptor */ 462c5aff182SThomas Petazzoni int last_desc; 463c5aff182SThomas Petazzoni 464c5aff182SThomas Petazzoni /* Index of the next RX DMA descriptor to process */ 465c5aff182SThomas Petazzoni int next_desc_to_proc; 466c5aff182SThomas Petazzoni }; 467c5aff182SThomas Petazzoni 468edadb7faSEzequiel Garcia /* The hardware supports eight (8) rx queues, but we are only allowing 469edadb7faSEzequiel Garcia * the first one to be used. Therefore, let's just allocate one queue. 470edadb7faSEzequiel Garcia */ 471edadb7faSEzequiel Garcia static int rxq_number = 1; 472c5aff182SThomas Petazzoni static int txq_number = 8; 473c5aff182SThomas Petazzoni 474c5aff182SThomas Petazzoni static int rxq_def; 475c5aff182SThomas Petazzoni 476f19fadfcSwilly tarreau static int rx_copybreak __read_mostly = 256; 477f19fadfcSwilly tarreau 478c5aff182SThomas Petazzoni #define MVNETA_DRIVER_NAME "mvneta" 479c5aff182SThomas Petazzoni #define MVNETA_DRIVER_VERSION "1.0" 480c5aff182SThomas Petazzoni 481c5aff182SThomas Petazzoni /* Utility/helper methods */ 482c5aff182SThomas Petazzoni 483c5aff182SThomas Petazzoni /* Write helper method */ 484c5aff182SThomas Petazzoni static void mvreg_write(struct mvneta_port *pp, u32 offset, u32 data) 485c5aff182SThomas Petazzoni { 486c5aff182SThomas Petazzoni writel(data, pp->base + offset); 487c5aff182SThomas Petazzoni } 488c5aff182SThomas Petazzoni 489c5aff182SThomas Petazzoni /* Read helper method */ 490c5aff182SThomas Petazzoni static u32 mvreg_read(struct mvneta_port *pp, u32 offset) 491c5aff182SThomas Petazzoni { 492c5aff182SThomas Petazzoni return readl(pp->base + offset); 493c5aff182SThomas Petazzoni } 494c5aff182SThomas Petazzoni 495c5aff182SThomas Petazzoni /* Increment txq get counter */ 496c5aff182SThomas Petazzoni static void mvneta_txq_inc_get(struct mvneta_tx_queue *txq) 497c5aff182SThomas Petazzoni { 498c5aff182SThomas Petazzoni txq->txq_get_index++; 499c5aff182SThomas Petazzoni if (txq->txq_get_index == txq->size) 500c5aff182SThomas Petazzoni txq->txq_get_index = 0; 501c5aff182SThomas Petazzoni } 502c5aff182SThomas Petazzoni 503c5aff182SThomas Petazzoni /* Increment txq put counter */ 504c5aff182SThomas Petazzoni static void mvneta_txq_inc_put(struct mvneta_tx_queue *txq) 505c5aff182SThomas Petazzoni { 506c5aff182SThomas Petazzoni txq->txq_put_index++; 507c5aff182SThomas Petazzoni if (txq->txq_put_index == txq->size) 508c5aff182SThomas Petazzoni txq->txq_put_index = 0; 509c5aff182SThomas Petazzoni } 510c5aff182SThomas Petazzoni 511c5aff182SThomas Petazzoni 512c5aff182SThomas Petazzoni /* Clear all MIB counters */ 513c5aff182SThomas Petazzoni static void mvneta_mib_counters_clear(struct mvneta_port *pp) 514c5aff182SThomas Petazzoni { 515c5aff182SThomas Petazzoni int i; 516c5aff182SThomas Petazzoni u32 dummy; 517c5aff182SThomas Petazzoni 518c5aff182SThomas Petazzoni /* Perform dummy reads from MIB counters */ 519c5aff182SThomas Petazzoni for (i = 0; i < MVNETA_MIB_LATE_COLLISION; i += 4) 520c5aff182SThomas Petazzoni dummy = mvreg_read(pp, (MVNETA_MIB_COUNTERS_BASE + i)); 521c5aff182SThomas Petazzoni } 522c5aff182SThomas Petazzoni 523c5aff182SThomas Petazzoni /* Get System Network Statistics */ 524c5aff182SThomas Petazzoni struct rtnl_link_stats64 *mvneta_get_stats64(struct net_device *dev, 525c5aff182SThomas Petazzoni struct rtnl_link_stats64 *stats) 526c5aff182SThomas Petazzoni { 527c5aff182SThomas Petazzoni struct mvneta_port *pp = netdev_priv(dev); 528c5aff182SThomas Petazzoni unsigned int start; 52974c41b04Swilly tarreau int cpu; 530c5aff182SThomas Petazzoni 53174c41b04Swilly tarreau for_each_possible_cpu(cpu) { 53274c41b04Swilly tarreau struct mvneta_pcpu_stats *cpu_stats; 53374c41b04Swilly tarreau u64 rx_packets; 53474c41b04Swilly tarreau u64 rx_bytes; 53574c41b04Swilly tarreau u64 tx_packets; 53674c41b04Swilly tarreau u64 tx_bytes; 537c5aff182SThomas Petazzoni 53874c41b04Swilly tarreau cpu_stats = per_cpu_ptr(pp->stats, cpu); 539c5aff182SThomas Petazzoni do { 54057a7744eSEric W. Biederman start = u64_stats_fetch_begin_irq(&cpu_stats->syncp); 54174c41b04Swilly tarreau rx_packets = cpu_stats->rx_packets; 54274c41b04Swilly tarreau rx_bytes = cpu_stats->rx_bytes; 54374c41b04Swilly tarreau tx_packets = cpu_stats->tx_packets; 54474c41b04Swilly tarreau tx_bytes = cpu_stats->tx_bytes; 54557a7744eSEric W. Biederman } while (u64_stats_fetch_retry_irq(&cpu_stats->syncp, start)); 546c5aff182SThomas Petazzoni 54774c41b04Swilly tarreau stats->rx_packets += rx_packets; 54874c41b04Swilly tarreau stats->rx_bytes += rx_bytes; 54974c41b04Swilly tarreau stats->tx_packets += tx_packets; 55074c41b04Swilly tarreau stats->tx_bytes += tx_bytes; 55174c41b04Swilly tarreau } 552c5aff182SThomas Petazzoni 553c5aff182SThomas Petazzoni stats->rx_errors = dev->stats.rx_errors; 554c5aff182SThomas Petazzoni stats->rx_dropped = dev->stats.rx_dropped; 555c5aff182SThomas Petazzoni 556c5aff182SThomas Petazzoni stats->tx_dropped = dev->stats.tx_dropped; 557c5aff182SThomas Petazzoni 558c5aff182SThomas Petazzoni return stats; 559c5aff182SThomas Petazzoni } 560c5aff182SThomas Petazzoni 561c5aff182SThomas Petazzoni /* Rx descriptors helper methods */ 562c5aff182SThomas Petazzoni 5635428213cSwilly tarreau /* Checks whether the RX descriptor having this status is both the first 5645428213cSwilly tarreau * and the last descriptor for the RX packet. Each RX packet is currently 565c5aff182SThomas Petazzoni * received through a single RX descriptor, so not having each RX 566c5aff182SThomas Petazzoni * descriptor with its first and last bits set is an error 567c5aff182SThomas Petazzoni */ 5685428213cSwilly tarreau static int mvneta_rxq_desc_is_first_last(u32 status) 569c5aff182SThomas Petazzoni { 5705428213cSwilly tarreau return (status & MVNETA_RXD_FIRST_LAST_DESC) == 571c5aff182SThomas Petazzoni MVNETA_RXD_FIRST_LAST_DESC; 572c5aff182SThomas Petazzoni } 573c5aff182SThomas Petazzoni 574c5aff182SThomas Petazzoni /* Add number of descriptors ready to receive new packets */ 575c5aff182SThomas Petazzoni static void mvneta_rxq_non_occup_desc_add(struct mvneta_port *pp, 576c5aff182SThomas Petazzoni struct mvneta_rx_queue *rxq, 577c5aff182SThomas Petazzoni int ndescs) 578c5aff182SThomas Petazzoni { 579c5aff182SThomas Petazzoni /* Only MVNETA_RXQ_ADD_NON_OCCUPIED_MAX (255) descriptors can 5806a20c175SThomas Petazzoni * be added at once 5816a20c175SThomas Petazzoni */ 582c5aff182SThomas Petazzoni while (ndescs > MVNETA_RXQ_ADD_NON_OCCUPIED_MAX) { 583c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id), 584c5aff182SThomas Petazzoni (MVNETA_RXQ_ADD_NON_OCCUPIED_MAX << 585c5aff182SThomas Petazzoni MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT)); 586c5aff182SThomas Petazzoni ndescs -= MVNETA_RXQ_ADD_NON_OCCUPIED_MAX; 587c5aff182SThomas Petazzoni } 588c5aff182SThomas Petazzoni 589c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id), 590c5aff182SThomas Petazzoni (ndescs << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT)); 591c5aff182SThomas Petazzoni } 592c5aff182SThomas Petazzoni 593c5aff182SThomas Petazzoni /* Get number of RX descriptors occupied by received packets */ 594c5aff182SThomas Petazzoni static int mvneta_rxq_busy_desc_num_get(struct mvneta_port *pp, 595c5aff182SThomas Petazzoni struct mvneta_rx_queue *rxq) 596c5aff182SThomas Petazzoni { 597c5aff182SThomas Petazzoni u32 val; 598c5aff182SThomas Petazzoni 599c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_RXQ_STATUS_REG(rxq->id)); 600c5aff182SThomas Petazzoni return val & MVNETA_RXQ_OCCUPIED_ALL_MASK; 601c5aff182SThomas Petazzoni } 602c5aff182SThomas Petazzoni 6036a20c175SThomas Petazzoni /* Update num of rx desc called upon return from rx path or 604c5aff182SThomas Petazzoni * from mvneta_rxq_drop_pkts(). 605c5aff182SThomas Petazzoni */ 606c5aff182SThomas Petazzoni static void mvneta_rxq_desc_num_update(struct mvneta_port *pp, 607c5aff182SThomas Petazzoni struct mvneta_rx_queue *rxq, 608c5aff182SThomas Petazzoni int rx_done, int rx_filled) 609c5aff182SThomas Petazzoni { 610c5aff182SThomas Petazzoni u32 val; 611c5aff182SThomas Petazzoni 612c5aff182SThomas Petazzoni if ((rx_done <= 0xff) && (rx_filled <= 0xff)) { 613c5aff182SThomas Petazzoni val = rx_done | 614c5aff182SThomas Petazzoni (rx_filled << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT); 615c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id), val); 616c5aff182SThomas Petazzoni return; 617c5aff182SThomas Petazzoni } 618c5aff182SThomas Petazzoni 619c5aff182SThomas Petazzoni /* Only 255 descriptors can be added at once */ 620c5aff182SThomas Petazzoni while ((rx_done > 0) || (rx_filled > 0)) { 621c5aff182SThomas Petazzoni if (rx_done <= 0xff) { 622c5aff182SThomas Petazzoni val = rx_done; 623c5aff182SThomas Petazzoni rx_done = 0; 624c5aff182SThomas Petazzoni } else { 625c5aff182SThomas Petazzoni val = 0xff; 626c5aff182SThomas Petazzoni rx_done -= 0xff; 627c5aff182SThomas Petazzoni } 628c5aff182SThomas Petazzoni if (rx_filled <= 0xff) { 629c5aff182SThomas Petazzoni val |= rx_filled << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT; 630c5aff182SThomas Petazzoni rx_filled = 0; 631c5aff182SThomas Petazzoni } else { 632c5aff182SThomas Petazzoni val |= 0xff << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT; 633c5aff182SThomas Petazzoni rx_filled -= 0xff; 634c5aff182SThomas Petazzoni } 635c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id), val); 636c5aff182SThomas Petazzoni } 637c5aff182SThomas Petazzoni } 638c5aff182SThomas Petazzoni 639c5aff182SThomas Petazzoni /* Get pointer to next RX descriptor to be processed by SW */ 640c5aff182SThomas Petazzoni static struct mvneta_rx_desc * 641c5aff182SThomas Petazzoni mvneta_rxq_next_desc_get(struct mvneta_rx_queue *rxq) 642c5aff182SThomas Petazzoni { 643c5aff182SThomas Petazzoni int rx_desc = rxq->next_desc_to_proc; 644c5aff182SThomas Petazzoni 645c5aff182SThomas Petazzoni rxq->next_desc_to_proc = MVNETA_QUEUE_NEXT_DESC(rxq, rx_desc); 64634e4179dSwilly tarreau prefetch(rxq->descs + rxq->next_desc_to_proc); 647c5aff182SThomas Petazzoni return rxq->descs + rx_desc; 648c5aff182SThomas Petazzoni } 649c5aff182SThomas Petazzoni 650c5aff182SThomas Petazzoni /* Change maximum receive size of the port. */ 651c5aff182SThomas Petazzoni static void mvneta_max_rx_size_set(struct mvneta_port *pp, int max_rx_size) 652c5aff182SThomas Petazzoni { 653c5aff182SThomas Petazzoni u32 val; 654c5aff182SThomas Petazzoni 655c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_GMAC_CTRL_0); 656c5aff182SThomas Petazzoni val &= ~MVNETA_GMAC_MAX_RX_SIZE_MASK; 657c5aff182SThomas Petazzoni val |= ((max_rx_size - MVNETA_MH_SIZE) / 2) << 658c5aff182SThomas Petazzoni MVNETA_GMAC_MAX_RX_SIZE_SHIFT; 659c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_GMAC_CTRL_0, val); 660c5aff182SThomas Petazzoni } 661c5aff182SThomas Petazzoni 662c5aff182SThomas Petazzoni 663c5aff182SThomas Petazzoni /* Set rx queue offset */ 664c5aff182SThomas Petazzoni static void mvneta_rxq_offset_set(struct mvneta_port *pp, 665c5aff182SThomas Petazzoni struct mvneta_rx_queue *rxq, 666c5aff182SThomas Petazzoni int offset) 667c5aff182SThomas Petazzoni { 668c5aff182SThomas Petazzoni u32 val; 669c5aff182SThomas Petazzoni 670c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_RXQ_CONFIG_REG(rxq->id)); 671c5aff182SThomas Petazzoni val &= ~MVNETA_RXQ_PKT_OFFSET_ALL_MASK; 672c5aff182SThomas Petazzoni 673c5aff182SThomas Petazzoni /* Offset is in */ 674c5aff182SThomas Petazzoni val |= MVNETA_RXQ_PKT_OFFSET_MASK(offset >> 3); 675c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_RXQ_CONFIG_REG(rxq->id), val); 676c5aff182SThomas Petazzoni } 677c5aff182SThomas Petazzoni 678c5aff182SThomas Petazzoni 679c5aff182SThomas Petazzoni /* Tx descriptors helper methods */ 680c5aff182SThomas Petazzoni 681c5aff182SThomas Petazzoni /* Update HW with number of TX descriptors to be sent */ 682c5aff182SThomas Petazzoni static void mvneta_txq_pend_desc_add(struct mvneta_port *pp, 683c5aff182SThomas Petazzoni struct mvneta_tx_queue *txq, 684c5aff182SThomas Petazzoni int pend_desc) 685c5aff182SThomas Petazzoni { 686c5aff182SThomas Petazzoni u32 val; 687c5aff182SThomas Petazzoni 688c5aff182SThomas Petazzoni /* Only 255 descriptors can be added at once ; Assume caller 6896a20c175SThomas Petazzoni * process TX desriptors in quanta less than 256 6906a20c175SThomas Petazzoni */ 691c5aff182SThomas Petazzoni val = pend_desc; 692c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val); 693c5aff182SThomas Petazzoni } 694c5aff182SThomas Petazzoni 695c5aff182SThomas Petazzoni /* Get pointer to next TX descriptor to be processed (send) by HW */ 696c5aff182SThomas Petazzoni static struct mvneta_tx_desc * 697c5aff182SThomas Petazzoni mvneta_txq_next_desc_get(struct mvneta_tx_queue *txq) 698c5aff182SThomas Petazzoni { 699c5aff182SThomas Petazzoni int tx_desc = txq->next_desc_to_proc; 700c5aff182SThomas Petazzoni 701c5aff182SThomas Petazzoni txq->next_desc_to_proc = MVNETA_QUEUE_NEXT_DESC(txq, tx_desc); 702c5aff182SThomas Petazzoni return txq->descs + tx_desc; 703c5aff182SThomas Petazzoni } 704c5aff182SThomas Petazzoni 705c5aff182SThomas Petazzoni /* Release the last allocated TX descriptor. Useful to handle DMA 7066a20c175SThomas Petazzoni * mapping failures in the TX path. 7076a20c175SThomas Petazzoni */ 708c5aff182SThomas Petazzoni static void mvneta_txq_desc_put(struct mvneta_tx_queue *txq) 709c5aff182SThomas Petazzoni { 710c5aff182SThomas Petazzoni if (txq->next_desc_to_proc == 0) 711c5aff182SThomas Petazzoni txq->next_desc_to_proc = txq->last_desc - 1; 712c5aff182SThomas Petazzoni else 713c5aff182SThomas Petazzoni txq->next_desc_to_proc--; 714c5aff182SThomas Petazzoni } 715c5aff182SThomas Petazzoni 716c5aff182SThomas Petazzoni /* Set rxq buf size */ 717c5aff182SThomas Petazzoni static void mvneta_rxq_buf_size_set(struct mvneta_port *pp, 718c5aff182SThomas Petazzoni struct mvneta_rx_queue *rxq, 719c5aff182SThomas Petazzoni int buf_size) 720c5aff182SThomas Petazzoni { 721c5aff182SThomas Petazzoni u32 val; 722c5aff182SThomas Petazzoni 723c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_RXQ_SIZE_REG(rxq->id)); 724c5aff182SThomas Petazzoni 725c5aff182SThomas Petazzoni val &= ~MVNETA_RXQ_BUF_SIZE_MASK; 726c5aff182SThomas Petazzoni val |= ((buf_size >> 3) << MVNETA_RXQ_BUF_SIZE_SHIFT); 727c5aff182SThomas Petazzoni 728c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_RXQ_SIZE_REG(rxq->id), val); 729c5aff182SThomas Petazzoni } 730c5aff182SThomas Petazzoni 731c5aff182SThomas Petazzoni /* Disable buffer management (BM) */ 732c5aff182SThomas Petazzoni static void mvneta_rxq_bm_disable(struct mvneta_port *pp, 733c5aff182SThomas Petazzoni struct mvneta_rx_queue *rxq) 734c5aff182SThomas Petazzoni { 735c5aff182SThomas Petazzoni u32 val; 736c5aff182SThomas Petazzoni 737c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_RXQ_CONFIG_REG(rxq->id)); 738c5aff182SThomas Petazzoni val &= ~MVNETA_RXQ_HW_BUF_ALLOC; 739c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_RXQ_CONFIG_REG(rxq->id), val); 740c5aff182SThomas Petazzoni } 741c5aff182SThomas Petazzoni 742c5aff182SThomas Petazzoni /* Start the Ethernet port RX and TX activity */ 743c5aff182SThomas Petazzoni static void mvneta_port_up(struct mvneta_port *pp) 744c5aff182SThomas Petazzoni { 745c5aff182SThomas Petazzoni int queue; 746c5aff182SThomas Petazzoni u32 q_map; 747c5aff182SThomas Petazzoni 748c5aff182SThomas Petazzoni /* Enable all initialized TXs. */ 749c5aff182SThomas Petazzoni mvneta_mib_counters_clear(pp); 750c5aff182SThomas Petazzoni q_map = 0; 751c5aff182SThomas Petazzoni for (queue = 0; queue < txq_number; queue++) { 752c5aff182SThomas Petazzoni struct mvneta_tx_queue *txq = &pp->txqs[queue]; 753c5aff182SThomas Petazzoni if (txq->descs != NULL) 754c5aff182SThomas Petazzoni q_map |= (1 << queue); 755c5aff182SThomas Petazzoni } 756c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_TXQ_CMD, q_map); 757c5aff182SThomas Petazzoni 758c5aff182SThomas Petazzoni /* Enable all initialized RXQs. */ 759c5aff182SThomas Petazzoni q_map = 0; 760c5aff182SThomas Petazzoni for (queue = 0; queue < rxq_number; queue++) { 761c5aff182SThomas Petazzoni struct mvneta_rx_queue *rxq = &pp->rxqs[queue]; 762c5aff182SThomas Petazzoni if (rxq->descs != NULL) 763c5aff182SThomas Petazzoni q_map |= (1 << queue); 764c5aff182SThomas Petazzoni } 765c5aff182SThomas Petazzoni 766c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_RXQ_CMD, q_map); 767c5aff182SThomas Petazzoni } 768c5aff182SThomas Petazzoni 769c5aff182SThomas Petazzoni /* Stop the Ethernet port activity */ 770c5aff182SThomas Petazzoni static void mvneta_port_down(struct mvneta_port *pp) 771c5aff182SThomas Petazzoni { 772c5aff182SThomas Petazzoni u32 val; 773c5aff182SThomas Petazzoni int count; 774c5aff182SThomas Petazzoni 775c5aff182SThomas Petazzoni /* Stop Rx port activity. Check port Rx activity. */ 776c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_RXQ_CMD) & MVNETA_RXQ_ENABLE_MASK; 777c5aff182SThomas Petazzoni 778c5aff182SThomas Petazzoni /* Issue stop command for active channels only */ 779c5aff182SThomas Petazzoni if (val != 0) 780c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_RXQ_CMD, 781c5aff182SThomas Petazzoni val << MVNETA_RXQ_DISABLE_SHIFT); 782c5aff182SThomas Petazzoni 783c5aff182SThomas Petazzoni /* Wait for all Rx activity to terminate. */ 784c5aff182SThomas Petazzoni count = 0; 785c5aff182SThomas Petazzoni do { 786c5aff182SThomas Petazzoni if (count++ >= MVNETA_RX_DISABLE_TIMEOUT_MSEC) { 787c5aff182SThomas Petazzoni netdev_warn(pp->dev, 788c5aff182SThomas Petazzoni "TIMEOUT for RX stopped ! rx_queue_cmd: 0x08%x\n", 789c5aff182SThomas Petazzoni val); 790c5aff182SThomas Petazzoni break; 791c5aff182SThomas Petazzoni } 792c5aff182SThomas Petazzoni mdelay(1); 793c5aff182SThomas Petazzoni 794c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_RXQ_CMD); 795c5aff182SThomas Petazzoni } while (val & 0xff); 796c5aff182SThomas Petazzoni 797c5aff182SThomas Petazzoni /* Stop Tx port activity. Check port Tx activity. Issue stop 7986a20c175SThomas Petazzoni * command for active channels only 7996a20c175SThomas Petazzoni */ 800c5aff182SThomas Petazzoni val = (mvreg_read(pp, MVNETA_TXQ_CMD)) & MVNETA_TXQ_ENABLE_MASK; 801c5aff182SThomas Petazzoni 802c5aff182SThomas Petazzoni if (val != 0) 803c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_TXQ_CMD, 804c5aff182SThomas Petazzoni (val << MVNETA_TXQ_DISABLE_SHIFT)); 805c5aff182SThomas Petazzoni 806c5aff182SThomas Petazzoni /* Wait for all Tx activity to terminate. */ 807c5aff182SThomas Petazzoni count = 0; 808c5aff182SThomas Petazzoni do { 809c5aff182SThomas Petazzoni if (count++ >= MVNETA_TX_DISABLE_TIMEOUT_MSEC) { 810c5aff182SThomas Petazzoni netdev_warn(pp->dev, 811c5aff182SThomas Petazzoni "TIMEOUT for TX stopped status=0x%08x\n", 812c5aff182SThomas Petazzoni val); 813c5aff182SThomas Petazzoni break; 814c5aff182SThomas Petazzoni } 815c5aff182SThomas Petazzoni mdelay(1); 816c5aff182SThomas Petazzoni 817c5aff182SThomas Petazzoni /* Check TX Command reg that all Txqs are stopped */ 818c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_TXQ_CMD); 819c5aff182SThomas Petazzoni 820c5aff182SThomas Petazzoni } while (val & 0xff); 821c5aff182SThomas Petazzoni 822c5aff182SThomas Petazzoni /* Double check to verify that TX FIFO is empty */ 823c5aff182SThomas Petazzoni count = 0; 824c5aff182SThomas Petazzoni do { 825c5aff182SThomas Petazzoni if (count++ >= MVNETA_TX_FIFO_EMPTY_TIMEOUT) { 826c5aff182SThomas Petazzoni netdev_warn(pp->dev, 827c5aff182SThomas Petazzoni "TX FIFO empty timeout status=0x08%x\n", 828c5aff182SThomas Petazzoni val); 829c5aff182SThomas Petazzoni break; 830c5aff182SThomas Petazzoni } 831c5aff182SThomas Petazzoni mdelay(1); 832c5aff182SThomas Petazzoni 833c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_PORT_STATUS); 834c5aff182SThomas Petazzoni } while (!(val & MVNETA_TX_FIFO_EMPTY) && 835c5aff182SThomas Petazzoni (val & MVNETA_TX_IN_PRGRS)); 836c5aff182SThomas Petazzoni 837c5aff182SThomas Petazzoni udelay(200); 838c5aff182SThomas Petazzoni } 839c5aff182SThomas Petazzoni 840c5aff182SThomas Petazzoni /* Enable the port by setting the port enable bit of the MAC control register */ 841c5aff182SThomas Petazzoni static void mvneta_port_enable(struct mvneta_port *pp) 842c5aff182SThomas Petazzoni { 843c5aff182SThomas Petazzoni u32 val; 844c5aff182SThomas Petazzoni 845c5aff182SThomas Petazzoni /* Enable port */ 846c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_GMAC_CTRL_0); 847c5aff182SThomas Petazzoni val |= MVNETA_GMAC0_PORT_ENABLE; 848c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_GMAC_CTRL_0, val); 849c5aff182SThomas Petazzoni } 850c5aff182SThomas Petazzoni 851c5aff182SThomas Petazzoni /* Disable the port and wait for about 200 usec before retuning */ 852c5aff182SThomas Petazzoni static void mvneta_port_disable(struct mvneta_port *pp) 853c5aff182SThomas Petazzoni { 854c5aff182SThomas Petazzoni u32 val; 855c5aff182SThomas Petazzoni 856c5aff182SThomas Petazzoni /* Reset the Enable bit in the Serial Control Register */ 857c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_GMAC_CTRL_0); 858c5aff182SThomas Petazzoni val &= ~MVNETA_GMAC0_PORT_ENABLE; 859c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_GMAC_CTRL_0, val); 860c5aff182SThomas Petazzoni 861c5aff182SThomas Petazzoni udelay(200); 862c5aff182SThomas Petazzoni } 863c5aff182SThomas Petazzoni 864c5aff182SThomas Petazzoni /* Multicast tables methods */ 865c5aff182SThomas Petazzoni 866c5aff182SThomas Petazzoni /* Set all entries in Unicast MAC Table; queue==-1 means reject all */ 867c5aff182SThomas Petazzoni static void mvneta_set_ucast_table(struct mvneta_port *pp, int queue) 868c5aff182SThomas Petazzoni { 869c5aff182SThomas Petazzoni int offset; 870c5aff182SThomas Petazzoni u32 val; 871c5aff182SThomas Petazzoni 872c5aff182SThomas Petazzoni if (queue == -1) { 873c5aff182SThomas Petazzoni val = 0; 874c5aff182SThomas Petazzoni } else { 875c5aff182SThomas Petazzoni val = 0x1 | (queue << 1); 876c5aff182SThomas Petazzoni val |= (val << 24) | (val << 16) | (val << 8); 877c5aff182SThomas Petazzoni } 878c5aff182SThomas Petazzoni 879c5aff182SThomas Petazzoni for (offset = 0; offset <= 0xc; offset += 4) 880c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_DA_FILT_UCAST_BASE + offset, val); 881c5aff182SThomas Petazzoni } 882c5aff182SThomas Petazzoni 883c5aff182SThomas Petazzoni /* Set all entries in Special Multicast MAC Table; queue==-1 means reject all */ 884c5aff182SThomas Petazzoni static void mvneta_set_special_mcast_table(struct mvneta_port *pp, int queue) 885c5aff182SThomas Petazzoni { 886c5aff182SThomas Petazzoni int offset; 887c5aff182SThomas Petazzoni u32 val; 888c5aff182SThomas Petazzoni 889c5aff182SThomas Petazzoni if (queue == -1) { 890c5aff182SThomas Petazzoni val = 0; 891c5aff182SThomas Petazzoni } else { 892c5aff182SThomas Petazzoni val = 0x1 | (queue << 1); 893c5aff182SThomas Petazzoni val |= (val << 24) | (val << 16) | (val << 8); 894c5aff182SThomas Petazzoni } 895c5aff182SThomas Petazzoni 896c5aff182SThomas Petazzoni for (offset = 0; offset <= 0xfc; offset += 4) 897c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_DA_FILT_SPEC_MCAST + offset, val); 898c5aff182SThomas Petazzoni 899c5aff182SThomas Petazzoni } 900c5aff182SThomas Petazzoni 901c5aff182SThomas Petazzoni /* Set all entries in Other Multicast MAC Table. queue==-1 means reject all */ 902c5aff182SThomas Petazzoni static void mvneta_set_other_mcast_table(struct mvneta_port *pp, int queue) 903c5aff182SThomas Petazzoni { 904c5aff182SThomas Petazzoni int offset; 905c5aff182SThomas Petazzoni u32 val; 906c5aff182SThomas Petazzoni 907c5aff182SThomas Petazzoni if (queue == -1) { 908c5aff182SThomas Petazzoni memset(pp->mcast_count, 0, sizeof(pp->mcast_count)); 909c5aff182SThomas Petazzoni val = 0; 910c5aff182SThomas Petazzoni } else { 911c5aff182SThomas Petazzoni memset(pp->mcast_count, 1, sizeof(pp->mcast_count)); 912c5aff182SThomas Petazzoni val = 0x1 | (queue << 1); 913c5aff182SThomas Petazzoni val |= (val << 24) | (val << 16) | (val << 8); 914c5aff182SThomas Petazzoni } 915c5aff182SThomas Petazzoni 916c5aff182SThomas Petazzoni for (offset = 0; offset <= 0xfc; offset += 4) 917c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_DA_FILT_OTH_MCAST + offset, val); 918c5aff182SThomas Petazzoni } 919c5aff182SThomas Petazzoni 920c5aff182SThomas Petazzoni /* This method sets defaults to the NETA port: 921c5aff182SThomas Petazzoni * Clears interrupt Cause and Mask registers. 922c5aff182SThomas Petazzoni * Clears all MAC tables. 923c5aff182SThomas Petazzoni * Sets defaults to all registers. 924c5aff182SThomas Petazzoni * Resets RX and TX descriptor rings. 925c5aff182SThomas Petazzoni * Resets PHY. 926c5aff182SThomas Petazzoni * This method can be called after mvneta_port_down() to return the port 927c5aff182SThomas Petazzoni * settings to defaults. 928c5aff182SThomas Petazzoni */ 929c5aff182SThomas Petazzoni static void mvneta_defaults_set(struct mvneta_port *pp) 930c5aff182SThomas Petazzoni { 931c5aff182SThomas Petazzoni int cpu; 932c5aff182SThomas Petazzoni int queue; 933c5aff182SThomas Petazzoni u32 val; 934c5aff182SThomas Petazzoni 935c5aff182SThomas Petazzoni /* Clear all Cause registers */ 936c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_INTR_NEW_CAUSE, 0); 937c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_INTR_OLD_CAUSE, 0); 938c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_INTR_MISC_CAUSE, 0); 939c5aff182SThomas Petazzoni 940c5aff182SThomas Petazzoni /* Mask all interrupts */ 941c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_INTR_NEW_MASK, 0); 942c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_INTR_OLD_MASK, 0); 943c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_INTR_MISC_MASK, 0); 944c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_INTR_ENABLE, 0); 945c5aff182SThomas Petazzoni 946c5aff182SThomas Petazzoni /* Enable MBUS Retry bit16 */ 947c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_MBUS_RETRY, 0x20); 948c5aff182SThomas Petazzoni 949c5aff182SThomas Petazzoni /* Set CPU queue access map - all CPUs have access to all RX 9506a20c175SThomas Petazzoni * queues and to all TX queues 9516a20c175SThomas Petazzoni */ 952c5aff182SThomas Petazzoni for (cpu = 0; cpu < CONFIG_NR_CPUS; cpu++) 953c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_CPU_MAP(cpu), 954c5aff182SThomas Petazzoni (MVNETA_CPU_RXQ_ACCESS_ALL_MASK | 955c5aff182SThomas Petazzoni MVNETA_CPU_TXQ_ACCESS_ALL_MASK)); 956c5aff182SThomas Petazzoni 957c5aff182SThomas Petazzoni /* Reset RX and TX DMAs */ 958c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_PORT_RX_RESET, MVNETA_PORT_RX_DMA_RESET); 959c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_PORT_TX_RESET, MVNETA_PORT_TX_DMA_RESET); 960c5aff182SThomas Petazzoni 961c5aff182SThomas Petazzoni /* Disable Legacy WRR, Disable EJP, Release from reset */ 962c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_TXQ_CMD_1, 0); 963c5aff182SThomas Petazzoni for (queue = 0; queue < txq_number; queue++) { 964c5aff182SThomas Petazzoni mvreg_write(pp, MVETH_TXQ_TOKEN_COUNT_REG(queue), 0); 965c5aff182SThomas Petazzoni mvreg_write(pp, MVETH_TXQ_TOKEN_CFG_REG(queue), 0); 966c5aff182SThomas Petazzoni } 967c5aff182SThomas Petazzoni 968c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_PORT_TX_RESET, 0); 969c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_PORT_RX_RESET, 0); 970c5aff182SThomas Petazzoni 971c5aff182SThomas Petazzoni /* Set Port Acceleration Mode */ 972c5aff182SThomas Petazzoni val = MVNETA_ACC_MODE_EXT; 973c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_ACC_MODE, val); 974c5aff182SThomas Petazzoni 975c5aff182SThomas Petazzoni /* Update val of portCfg register accordingly with all RxQueue types */ 976c5aff182SThomas Petazzoni val = MVNETA_PORT_CONFIG_DEFL_VALUE(rxq_def); 977c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_PORT_CONFIG, val); 978c5aff182SThomas Petazzoni 979c5aff182SThomas Petazzoni val = 0; 980c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_PORT_CONFIG_EXTEND, val); 981c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_RX_MIN_FRAME_SIZE, 64); 982c5aff182SThomas Petazzoni 983c5aff182SThomas Petazzoni /* Build PORT_SDMA_CONFIG_REG */ 984c5aff182SThomas Petazzoni val = 0; 985c5aff182SThomas Petazzoni 986c5aff182SThomas Petazzoni /* Default burst size */ 987c5aff182SThomas Petazzoni val |= MVNETA_TX_BRST_SZ_MASK(MVNETA_SDMA_BRST_SIZE_16); 988c5aff182SThomas Petazzoni val |= MVNETA_RX_BRST_SZ_MASK(MVNETA_SDMA_BRST_SIZE_16); 9899ad8fef6SThomas Petazzoni val |= MVNETA_RX_NO_DATA_SWAP | MVNETA_TX_NO_DATA_SWAP; 990c5aff182SThomas Petazzoni 9919ad8fef6SThomas Petazzoni #if defined(__BIG_ENDIAN) 9929ad8fef6SThomas Petazzoni val |= MVNETA_DESC_SWAP; 9939ad8fef6SThomas Petazzoni #endif 994c5aff182SThomas Petazzoni 995c5aff182SThomas Petazzoni /* Assign port SDMA configuration */ 996c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_SDMA_CONFIG, val); 997c5aff182SThomas Petazzoni 99871408602SThomas Petazzoni /* Disable PHY polling in hardware, since we're using the 99971408602SThomas Petazzoni * kernel phylib to do this. 100071408602SThomas Petazzoni */ 100171408602SThomas Petazzoni val = mvreg_read(pp, MVNETA_UNIT_CONTROL); 100271408602SThomas Petazzoni val &= ~MVNETA_PHY_POLLING_ENABLE; 100371408602SThomas Petazzoni mvreg_write(pp, MVNETA_UNIT_CONTROL, val); 100471408602SThomas Petazzoni 1005898b2970SStas Sergeev if (pp->use_inband_status) { 1006898b2970SStas Sergeev val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG); 1007898b2970SStas Sergeev val &= ~(MVNETA_GMAC_FORCE_LINK_PASS | 1008898b2970SStas Sergeev MVNETA_GMAC_FORCE_LINK_DOWN | 1009898b2970SStas Sergeev MVNETA_GMAC_AN_FLOW_CTRL_EN); 1010898b2970SStas Sergeev val |= MVNETA_GMAC_INBAND_AN_ENABLE | 1011898b2970SStas Sergeev MVNETA_GMAC_AN_SPEED_EN | 1012898b2970SStas Sergeev MVNETA_GMAC_AN_DUPLEX_EN; 1013898b2970SStas Sergeev mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val); 1014898b2970SStas Sergeev val = mvreg_read(pp, MVNETA_GMAC_CLOCK_DIVIDER); 1015898b2970SStas Sergeev val |= MVNETA_GMAC_1MS_CLOCK_ENABLE; 1016898b2970SStas Sergeev mvreg_write(pp, MVNETA_GMAC_CLOCK_DIVIDER, val); 1017538761b7SStas Sergeev } else { 1018538761b7SStas Sergeev val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG); 1019538761b7SStas Sergeev val &= ~(MVNETA_GMAC_INBAND_AN_ENABLE | 1020538761b7SStas Sergeev MVNETA_GMAC_AN_SPEED_EN | 1021538761b7SStas Sergeev MVNETA_GMAC_AN_DUPLEX_EN); 1022538761b7SStas Sergeev mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val); 1023898b2970SStas Sergeev } 1024898b2970SStas Sergeev 1025c5aff182SThomas Petazzoni mvneta_set_ucast_table(pp, -1); 1026c5aff182SThomas Petazzoni mvneta_set_special_mcast_table(pp, -1); 1027c5aff182SThomas Petazzoni mvneta_set_other_mcast_table(pp, -1); 1028c5aff182SThomas Petazzoni 1029c5aff182SThomas Petazzoni /* Set port interrupt enable register - default enable all */ 1030c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_INTR_ENABLE, 1031c5aff182SThomas Petazzoni (MVNETA_RXQ_INTR_ENABLE_ALL_MASK 1032c5aff182SThomas Petazzoni | MVNETA_TXQ_INTR_ENABLE_ALL_MASK)); 1033c5aff182SThomas Petazzoni } 1034c5aff182SThomas Petazzoni 1035c5aff182SThomas Petazzoni /* Set max sizes for tx queues */ 1036c5aff182SThomas Petazzoni static void mvneta_txq_max_tx_size_set(struct mvneta_port *pp, int max_tx_size) 1037c5aff182SThomas Petazzoni 1038c5aff182SThomas Petazzoni { 1039c5aff182SThomas Petazzoni u32 val, size, mtu; 1040c5aff182SThomas Petazzoni int queue; 1041c5aff182SThomas Petazzoni 1042c5aff182SThomas Petazzoni mtu = max_tx_size * 8; 1043c5aff182SThomas Petazzoni if (mtu > MVNETA_TX_MTU_MAX) 1044c5aff182SThomas Petazzoni mtu = MVNETA_TX_MTU_MAX; 1045c5aff182SThomas Petazzoni 1046c5aff182SThomas Petazzoni /* Set MTU */ 1047c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_TX_MTU); 1048c5aff182SThomas Petazzoni val &= ~MVNETA_TX_MTU_MAX; 1049c5aff182SThomas Petazzoni val |= mtu; 1050c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_TX_MTU, val); 1051c5aff182SThomas Petazzoni 1052c5aff182SThomas Petazzoni /* TX token size and all TXQs token size must be larger that MTU */ 1053c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_TX_TOKEN_SIZE); 1054c5aff182SThomas Petazzoni 1055c5aff182SThomas Petazzoni size = val & MVNETA_TX_TOKEN_SIZE_MAX; 1056c5aff182SThomas Petazzoni if (size < mtu) { 1057c5aff182SThomas Petazzoni size = mtu; 1058c5aff182SThomas Petazzoni val &= ~MVNETA_TX_TOKEN_SIZE_MAX; 1059c5aff182SThomas Petazzoni val |= size; 1060c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_TX_TOKEN_SIZE, val); 1061c5aff182SThomas Petazzoni } 1062c5aff182SThomas Petazzoni for (queue = 0; queue < txq_number; queue++) { 1063c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_TXQ_TOKEN_SIZE_REG(queue)); 1064c5aff182SThomas Petazzoni 1065c5aff182SThomas Petazzoni size = val & MVNETA_TXQ_TOKEN_SIZE_MAX; 1066c5aff182SThomas Petazzoni if (size < mtu) { 1067c5aff182SThomas Petazzoni size = mtu; 1068c5aff182SThomas Petazzoni val &= ~MVNETA_TXQ_TOKEN_SIZE_MAX; 1069c5aff182SThomas Petazzoni val |= size; 1070c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_TXQ_TOKEN_SIZE_REG(queue), val); 1071c5aff182SThomas Petazzoni } 1072c5aff182SThomas Petazzoni } 1073c5aff182SThomas Petazzoni } 1074c5aff182SThomas Petazzoni 1075c5aff182SThomas Petazzoni /* Set unicast address */ 1076c5aff182SThomas Petazzoni static void mvneta_set_ucast_addr(struct mvneta_port *pp, u8 last_nibble, 1077c5aff182SThomas Petazzoni int queue) 1078c5aff182SThomas Petazzoni { 1079c5aff182SThomas Petazzoni unsigned int unicast_reg; 1080c5aff182SThomas Petazzoni unsigned int tbl_offset; 1081c5aff182SThomas Petazzoni unsigned int reg_offset; 1082c5aff182SThomas Petazzoni 1083c5aff182SThomas Petazzoni /* Locate the Unicast table entry */ 1084c5aff182SThomas Petazzoni last_nibble = (0xf & last_nibble); 1085c5aff182SThomas Petazzoni 1086c5aff182SThomas Petazzoni /* offset from unicast tbl base */ 1087c5aff182SThomas Petazzoni tbl_offset = (last_nibble / 4) * 4; 1088c5aff182SThomas Petazzoni 1089c5aff182SThomas Petazzoni /* offset within the above reg */ 1090c5aff182SThomas Petazzoni reg_offset = last_nibble % 4; 1091c5aff182SThomas Petazzoni 1092c5aff182SThomas Petazzoni unicast_reg = mvreg_read(pp, (MVNETA_DA_FILT_UCAST_BASE + tbl_offset)); 1093c5aff182SThomas Petazzoni 1094c5aff182SThomas Petazzoni if (queue == -1) { 1095c5aff182SThomas Petazzoni /* Clear accepts frame bit at specified unicast DA tbl entry */ 1096c5aff182SThomas Petazzoni unicast_reg &= ~(0xff << (8 * reg_offset)); 1097c5aff182SThomas Petazzoni } else { 1098c5aff182SThomas Petazzoni unicast_reg &= ~(0xff << (8 * reg_offset)); 1099c5aff182SThomas Petazzoni unicast_reg |= ((0x01 | (queue << 1)) << (8 * reg_offset)); 1100c5aff182SThomas Petazzoni } 1101c5aff182SThomas Petazzoni 1102c5aff182SThomas Petazzoni mvreg_write(pp, (MVNETA_DA_FILT_UCAST_BASE + tbl_offset), unicast_reg); 1103c5aff182SThomas Petazzoni } 1104c5aff182SThomas Petazzoni 1105c5aff182SThomas Petazzoni /* Set mac address */ 1106c5aff182SThomas Petazzoni static void mvneta_mac_addr_set(struct mvneta_port *pp, unsigned char *addr, 1107c5aff182SThomas Petazzoni int queue) 1108c5aff182SThomas Petazzoni { 1109c5aff182SThomas Petazzoni unsigned int mac_h; 1110c5aff182SThomas Petazzoni unsigned int mac_l; 1111c5aff182SThomas Petazzoni 1112c5aff182SThomas Petazzoni if (queue != -1) { 1113c5aff182SThomas Petazzoni mac_l = (addr[4] << 8) | (addr[5]); 1114c5aff182SThomas Petazzoni mac_h = (addr[0] << 24) | (addr[1] << 16) | 1115c5aff182SThomas Petazzoni (addr[2] << 8) | (addr[3] << 0); 1116c5aff182SThomas Petazzoni 1117c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_MAC_ADDR_LOW, mac_l); 1118c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_MAC_ADDR_HIGH, mac_h); 1119c5aff182SThomas Petazzoni } 1120c5aff182SThomas Petazzoni 1121c5aff182SThomas Petazzoni /* Accept frames of this address */ 1122c5aff182SThomas Petazzoni mvneta_set_ucast_addr(pp, addr[5], queue); 1123c5aff182SThomas Petazzoni } 1124c5aff182SThomas Petazzoni 11256a20c175SThomas Petazzoni /* Set the number of packets that will be received before RX interrupt 11266a20c175SThomas Petazzoni * will be generated by HW. 1127c5aff182SThomas Petazzoni */ 1128c5aff182SThomas Petazzoni static void mvneta_rx_pkts_coal_set(struct mvneta_port *pp, 1129c5aff182SThomas Petazzoni struct mvneta_rx_queue *rxq, u32 value) 1130c5aff182SThomas Petazzoni { 1131c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_RXQ_THRESHOLD_REG(rxq->id), 1132c5aff182SThomas Petazzoni value | MVNETA_RXQ_NON_OCCUPIED(0)); 1133c5aff182SThomas Petazzoni rxq->pkts_coal = value; 1134c5aff182SThomas Petazzoni } 1135c5aff182SThomas Petazzoni 11366a20c175SThomas Petazzoni /* Set the time delay in usec before RX interrupt will be generated by 11376a20c175SThomas Petazzoni * HW. 1138c5aff182SThomas Petazzoni */ 1139c5aff182SThomas Petazzoni static void mvneta_rx_time_coal_set(struct mvneta_port *pp, 1140c5aff182SThomas Petazzoni struct mvneta_rx_queue *rxq, u32 value) 1141c5aff182SThomas Petazzoni { 1142189dd626SThomas Petazzoni u32 val; 1143189dd626SThomas Petazzoni unsigned long clk_rate; 1144189dd626SThomas Petazzoni 1145189dd626SThomas Petazzoni clk_rate = clk_get_rate(pp->clk); 1146189dd626SThomas Petazzoni val = (clk_rate / 1000000) * value; 1147c5aff182SThomas Petazzoni 1148c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_RXQ_TIME_COAL_REG(rxq->id), val); 1149c5aff182SThomas Petazzoni rxq->time_coal = value; 1150c5aff182SThomas Petazzoni } 1151c5aff182SThomas Petazzoni 1152c5aff182SThomas Petazzoni /* Set threshold for TX_DONE pkts coalescing */ 1153c5aff182SThomas Petazzoni static void mvneta_tx_done_pkts_coal_set(struct mvneta_port *pp, 1154c5aff182SThomas Petazzoni struct mvneta_tx_queue *txq, u32 value) 1155c5aff182SThomas Petazzoni { 1156c5aff182SThomas Petazzoni u32 val; 1157c5aff182SThomas Petazzoni 1158c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_TXQ_SIZE_REG(txq->id)); 1159c5aff182SThomas Petazzoni 1160c5aff182SThomas Petazzoni val &= ~MVNETA_TXQ_SENT_THRESH_ALL_MASK; 1161c5aff182SThomas Petazzoni val |= MVNETA_TXQ_SENT_THRESH_MASK(value); 1162c5aff182SThomas Petazzoni 1163c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_TXQ_SIZE_REG(txq->id), val); 1164c5aff182SThomas Petazzoni 1165c5aff182SThomas Petazzoni txq->done_pkts_coal = value; 1166c5aff182SThomas Petazzoni } 1167c5aff182SThomas Petazzoni 1168c5aff182SThomas Petazzoni /* Handle rx descriptor fill by setting buf_cookie and buf_phys_addr */ 1169c5aff182SThomas Petazzoni static void mvneta_rx_desc_fill(struct mvneta_rx_desc *rx_desc, 1170c5aff182SThomas Petazzoni u32 phys_addr, u32 cookie) 1171c5aff182SThomas Petazzoni { 1172c5aff182SThomas Petazzoni rx_desc->buf_cookie = cookie; 1173c5aff182SThomas Petazzoni rx_desc->buf_phys_addr = phys_addr; 1174c5aff182SThomas Petazzoni } 1175c5aff182SThomas Petazzoni 1176c5aff182SThomas Petazzoni /* Decrement sent descriptors counter */ 1177c5aff182SThomas Petazzoni static void mvneta_txq_sent_desc_dec(struct mvneta_port *pp, 1178c5aff182SThomas Petazzoni struct mvneta_tx_queue *txq, 1179c5aff182SThomas Petazzoni int sent_desc) 1180c5aff182SThomas Petazzoni { 1181c5aff182SThomas Petazzoni u32 val; 1182c5aff182SThomas Petazzoni 1183c5aff182SThomas Petazzoni /* Only 255 TX descriptors can be updated at once */ 1184c5aff182SThomas Petazzoni while (sent_desc > 0xff) { 1185c5aff182SThomas Petazzoni val = 0xff << MVNETA_TXQ_DEC_SENT_SHIFT; 1186c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val); 1187c5aff182SThomas Petazzoni sent_desc = sent_desc - 0xff; 1188c5aff182SThomas Petazzoni } 1189c5aff182SThomas Petazzoni 1190c5aff182SThomas Petazzoni val = sent_desc << MVNETA_TXQ_DEC_SENT_SHIFT; 1191c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val); 1192c5aff182SThomas Petazzoni } 1193c5aff182SThomas Petazzoni 1194c5aff182SThomas Petazzoni /* Get number of TX descriptors already sent by HW */ 1195c5aff182SThomas Petazzoni static int mvneta_txq_sent_desc_num_get(struct mvneta_port *pp, 1196c5aff182SThomas Petazzoni struct mvneta_tx_queue *txq) 1197c5aff182SThomas Petazzoni { 1198c5aff182SThomas Petazzoni u32 val; 1199c5aff182SThomas Petazzoni int sent_desc; 1200c5aff182SThomas Petazzoni 1201c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_TXQ_STATUS_REG(txq->id)); 1202c5aff182SThomas Petazzoni sent_desc = (val & MVNETA_TXQ_SENT_DESC_MASK) >> 1203c5aff182SThomas Petazzoni MVNETA_TXQ_SENT_DESC_SHIFT; 1204c5aff182SThomas Petazzoni 1205c5aff182SThomas Petazzoni return sent_desc; 1206c5aff182SThomas Petazzoni } 1207c5aff182SThomas Petazzoni 12086a20c175SThomas Petazzoni /* Get number of sent descriptors and decrement counter. 1209c5aff182SThomas Petazzoni * The number of sent descriptors is returned. 1210c5aff182SThomas Petazzoni */ 1211c5aff182SThomas Petazzoni static int mvneta_txq_sent_desc_proc(struct mvneta_port *pp, 1212c5aff182SThomas Petazzoni struct mvneta_tx_queue *txq) 1213c5aff182SThomas Petazzoni { 1214c5aff182SThomas Petazzoni int sent_desc; 1215c5aff182SThomas Petazzoni 1216c5aff182SThomas Petazzoni /* Get number of sent descriptors */ 1217c5aff182SThomas Petazzoni sent_desc = mvneta_txq_sent_desc_num_get(pp, txq); 1218c5aff182SThomas Petazzoni 1219c5aff182SThomas Petazzoni /* Decrement sent descriptors counter */ 1220c5aff182SThomas Petazzoni if (sent_desc) 1221c5aff182SThomas Petazzoni mvneta_txq_sent_desc_dec(pp, txq, sent_desc); 1222c5aff182SThomas Petazzoni 1223c5aff182SThomas Petazzoni return sent_desc; 1224c5aff182SThomas Petazzoni } 1225c5aff182SThomas Petazzoni 1226c5aff182SThomas Petazzoni /* Set TXQ descriptors fields relevant for CSUM calculation */ 1227c5aff182SThomas Petazzoni static u32 mvneta_txq_desc_csum(int l3_offs, int l3_proto, 1228c5aff182SThomas Petazzoni int ip_hdr_len, int l4_proto) 1229c5aff182SThomas Petazzoni { 1230c5aff182SThomas Petazzoni u32 command; 1231c5aff182SThomas Petazzoni 1232c5aff182SThomas Petazzoni /* Fields: L3_offset, IP_hdrlen, L3_type, G_IPv4_chk, 12336a20c175SThomas Petazzoni * G_L4_chk, L4_type; required only for checksum 12346a20c175SThomas Petazzoni * calculation 12356a20c175SThomas Petazzoni */ 1236c5aff182SThomas Petazzoni command = l3_offs << MVNETA_TX_L3_OFF_SHIFT; 1237c5aff182SThomas Petazzoni command |= ip_hdr_len << MVNETA_TX_IP_HLEN_SHIFT; 1238c5aff182SThomas Petazzoni 12390a198587SThomas Fitzsimmons if (l3_proto == htons(ETH_P_IP)) 1240c5aff182SThomas Petazzoni command |= MVNETA_TXD_IP_CSUM; 1241c5aff182SThomas Petazzoni else 1242c5aff182SThomas Petazzoni command |= MVNETA_TX_L3_IP6; 1243c5aff182SThomas Petazzoni 1244c5aff182SThomas Petazzoni if (l4_proto == IPPROTO_TCP) 1245c5aff182SThomas Petazzoni command |= MVNETA_TX_L4_CSUM_FULL; 1246c5aff182SThomas Petazzoni else if (l4_proto == IPPROTO_UDP) 1247c5aff182SThomas Petazzoni command |= MVNETA_TX_L4_UDP | MVNETA_TX_L4_CSUM_FULL; 1248c5aff182SThomas Petazzoni else 1249c5aff182SThomas Petazzoni command |= MVNETA_TX_L4_CSUM_NOT; 1250c5aff182SThomas Petazzoni 1251c5aff182SThomas Petazzoni return command; 1252c5aff182SThomas Petazzoni } 1253c5aff182SThomas Petazzoni 1254c5aff182SThomas Petazzoni 1255c5aff182SThomas Petazzoni /* Display more error info */ 1256c5aff182SThomas Petazzoni static void mvneta_rx_error(struct mvneta_port *pp, 1257c5aff182SThomas Petazzoni struct mvneta_rx_desc *rx_desc) 1258c5aff182SThomas Petazzoni { 1259c5aff182SThomas Petazzoni u32 status = rx_desc->status; 1260c5aff182SThomas Petazzoni 12615428213cSwilly tarreau if (!mvneta_rxq_desc_is_first_last(status)) { 1262c5aff182SThomas Petazzoni netdev_err(pp->dev, 1263c5aff182SThomas Petazzoni "bad rx status %08x (buffer oversize), size=%d\n", 12645428213cSwilly tarreau status, rx_desc->data_size); 1265c5aff182SThomas Petazzoni return; 1266c5aff182SThomas Petazzoni } 1267c5aff182SThomas Petazzoni 1268c5aff182SThomas Petazzoni switch (status & MVNETA_RXD_ERR_CODE_MASK) { 1269c5aff182SThomas Petazzoni case MVNETA_RXD_ERR_CRC: 1270c5aff182SThomas Petazzoni netdev_err(pp->dev, "bad rx status %08x (crc error), size=%d\n", 1271c5aff182SThomas Petazzoni status, rx_desc->data_size); 1272c5aff182SThomas Petazzoni break; 1273c5aff182SThomas Petazzoni case MVNETA_RXD_ERR_OVERRUN: 1274c5aff182SThomas Petazzoni netdev_err(pp->dev, "bad rx status %08x (overrun error), size=%d\n", 1275c5aff182SThomas Petazzoni status, rx_desc->data_size); 1276c5aff182SThomas Petazzoni break; 1277c5aff182SThomas Petazzoni case MVNETA_RXD_ERR_LEN: 1278c5aff182SThomas Petazzoni netdev_err(pp->dev, "bad rx status %08x (max frame length error), size=%d\n", 1279c5aff182SThomas Petazzoni status, rx_desc->data_size); 1280c5aff182SThomas Petazzoni break; 1281c5aff182SThomas Petazzoni case MVNETA_RXD_ERR_RESOURCE: 1282c5aff182SThomas Petazzoni netdev_err(pp->dev, "bad rx status %08x (resource error), size=%d\n", 1283c5aff182SThomas Petazzoni status, rx_desc->data_size); 1284c5aff182SThomas Petazzoni break; 1285c5aff182SThomas Petazzoni } 1286c5aff182SThomas Petazzoni } 1287c5aff182SThomas Petazzoni 12885428213cSwilly tarreau /* Handle RX checksum offload based on the descriptor's status */ 12895428213cSwilly tarreau static void mvneta_rx_csum(struct mvneta_port *pp, u32 status, 1290c5aff182SThomas Petazzoni struct sk_buff *skb) 1291c5aff182SThomas Petazzoni { 12925428213cSwilly tarreau if ((status & MVNETA_RXD_L3_IP4) && 12935428213cSwilly tarreau (status & MVNETA_RXD_L4_CSUM_OK)) { 1294c5aff182SThomas Petazzoni skb->csum = 0; 1295c5aff182SThomas Petazzoni skb->ip_summed = CHECKSUM_UNNECESSARY; 1296c5aff182SThomas Petazzoni return; 1297c5aff182SThomas Petazzoni } 1298c5aff182SThomas Petazzoni 1299c5aff182SThomas Petazzoni skb->ip_summed = CHECKSUM_NONE; 1300c5aff182SThomas Petazzoni } 1301c5aff182SThomas Petazzoni 13026c498974Swilly tarreau /* Return tx queue pointer (find last set bit) according to <cause> returned 13036c498974Swilly tarreau * form tx_done reg. <cause> must not be null. The return value is always a 13046c498974Swilly tarreau * valid queue for matching the first one found in <cause>. 13056c498974Swilly tarreau */ 1306c5aff182SThomas Petazzoni static struct mvneta_tx_queue *mvneta_tx_done_policy(struct mvneta_port *pp, 1307c5aff182SThomas Petazzoni u32 cause) 1308c5aff182SThomas Petazzoni { 1309c5aff182SThomas Petazzoni int queue = fls(cause) - 1; 1310c5aff182SThomas Petazzoni 13116c498974Swilly tarreau return &pp->txqs[queue]; 1312c5aff182SThomas Petazzoni } 1313c5aff182SThomas Petazzoni 1314c5aff182SThomas Petazzoni /* Free tx queue skbuffs */ 1315c5aff182SThomas Petazzoni static void mvneta_txq_bufs_free(struct mvneta_port *pp, 1316c5aff182SThomas Petazzoni struct mvneta_tx_queue *txq, int num) 1317c5aff182SThomas Petazzoni { 1318c5aff182SThomas Petazzoni int i; 1319c5aff182SThomas Petazzoni 1320c5aff182SThomas Petazzoni for (i = 0; i < num; i++) { 1321c5aff182SThomas Petazzoni struct mvneta_tx_desc *tx_desc = txq->descs + 1322c5aff182SThomas Petazzoni txq->txq_get_index; 1323c5aff182SThomas Petazzoni struct sk_buff *skb = txq->tx_skb[txq->txq_get_index]; 1324c5aff182SThomas Petazzoni 1325c5aff182SThomas Petazzoni mvneta_txq_inc_get(txq); 1326c5aff182SThomas Petazzoni 13272e3173a3SEzequiel Garcia if (!IS_TSO_HEADER(txq, tx_desc->buf_phys_addr)) 13282e3173a3SEzequiel Garcia dma_unmap_single(pp->dev->dev.parent, 13292e3173a3SEzequiel Garcia tx_desc->buf_phys_addr, 1330c5aff182SThomas Petazzoni tx_desc->data_size, DMA_TO_DEVICE); 1331ba7e46efSEzequiel Garcia if (!skb) 1332ba7e46efSEzequiel Garcia continue; 1333c5aff182SThomas Petazzoni dev_kfree_skb_any(skb); 1334c5aff182SThomas Petazzoni } 1335c5aff182SThomas Petazzoni } 1336c5aff182SThomas Petazzoni 1337c5aff182SThomas Petazzoni /* Handle end of transmission */ 1338cd713199SArnaud Ebalard static void mvneta_txq_done(struct mvneta_port *pp, 1339c5aff182SThomas Petazzoni struct mvneta_tx_queue *txq) 1340c5aff182SThomas Petazzoni { 1341c5aff182SThomas Petazzoni struct netdev_queue *nq = netdev_get_tx_queue(pp->dev, txq->id); 1342c5aff182SThomas Petazzoni int tx_done; 1343c5aff182SThomas Petazzoni 1344c5aff182SThomas Petazzoni tx_done = mvneta_txq_sent_desc_proc(pp, txq); 1345cd713199SArnaud Ebalard if (!tx_done) 1346cd713199SArnaud Ebalard return; 1347cd713199SArnaud Ebalard 1348c5aff182SThomas Petazzoni mvneta_txq_bufs_free(pp, txq, tx_done); 1349c5aff182SThomas Petazzoni 1350c5aff182SThomas Petazzoni txq->count -= tx_done; 1351c5aff182SThomas Petazzoni 1352c5aff182SThomas Petazzoni if (netif_tx_queue_stopped(nq)) { 13538eef5f97SEzequiel Garcia if (txq->count <= txq->tx_wake_threshold) 1354c5aff182SThomas Petazzoni netif_tx_wake_queue(nq); 1355c5aff182SThomas Petazzoni } 1356c5aff182SThomas Petazzoni } 1357c5aff182SThomas Petazzoni 13588ec2cd48Swilly tarreau static void *mvneta_frag_alloc(const struct mvneta_port *pp) 13598ec2cd48Swilly tarreau { 13608ec2cd48Swilly tarreau if (likely(pp->frag_size <= PAGE_SIZE)) 13618ec2cd48Swilly tarreau return netdev_alloc_frag(pp->frag_size); 13628ec2cd48Swilly tarreau else 13638ec2cd48Swilly tarreau return kmalloc(pp->frag_size, GFP_ATOMIC); 13648ec2cd48Swilly tarreau } 13658ec2cd48Swilly tarreau 13668ec2cd48Swilly tarreau static void mvneta_frag_free(const struct mvneta_port *pp, void *data) 13678ec2cd48Swilly tarreau { 13688ec2cd48Swilly tarreau if (likely(pp->frag_size <= PAGE_SIZE)) 136913dc0d2bSAlexander Duyck skb_free_frag(data); 13708ec2cd48Swilly tarreau else 13718ec2cd48Swilly tarreau kfree(data); 13728ec2cd48Swilly tarreau } 13738ec2cd48Swilly tarreau 1374c5aff182SThomas Petazzoni /* Refill processing */ 1375c5aff182SThomas Petazzoni static int mvneta_rx_refill(struct mvneta_port *pp, 1376c5aff182SThomas Petazzoni struct mvneta_rx_desc *rx_desc) 1377c5aff182SThomas Petazzoni 1378c5aff182SThomas Petazzoni { 1379c5aff182SThomas Petazzoni dma_addr_t phys_addr; 13808ec2cd48Swilly tarreau void *data; 1381c5aff182SThomas Petazzoni 13828ec2cd48Swilly tarreau data = mvneta_frag_alloc(pp); 13838ec2cd48Swilly tarreau if (!data) 1384c5aff182SThomas Petazzoni return -ENOMEM; 1385c5aff182SThomas Petazzoni 13868ec2cd48Swilly tarreau phys_addr = dma_map_single(pp->dev->dev.parent, data, 1387c5aff182SThomas Petazzoni MVNETA_RX_BUF_SIZE(pp->pkt_size), 1388c5aff182SThomas Petazzoni DMA_FROM_DEVICE); 1389c5aff182SThomas Petazzoni if (unlikely(dma_mapping_error(pp->dev->dev.parent, phys_addr))) { 13908ec2cd48Swilly tarreau mvneta_frag_free(pp, data); 1391c5aff182SThomas Petazzoni return -ENOMEM; 1392c5aff182SThomas Petazzoni } 1393c5aff182SThomas Petazzoni 13948ec2cd48Swilly tarreau mvneta_rx_desc_fill(rx_desc, phys_addr, (u32)data); 1395c5aff182SThomas Petazzoni return 0; 1396c5aff182SThomas Petazzoni } 1397c5aff182SThomas Petazzoni 1398c5aff182SThomas Petazzoni /* Handle tx checksum */ 1399c5aff182SThomas Petazzoni static u32 mvneta_skb_tx_csum(struct mvneta_port *pp, struct sk_buff *skb) 1400c5aff182SThomas Petazzoni { 1401c5aff182SThomas Petazzoni if (skb->ip_summed == CHECKSUM_PARTIAL) { 1402c5aff182SThomas Petazzoni int ip_hdr_len = 0; 1403817dbfa5SVlad Yasevich __be16 l3_proto = vlan_get_protocol(skb); 1404c5aff182SThomas Petazzoni u8 l4_proto; 1405c5aff182SThomas Petazzoni 1406817dbfa5SVlad Yasevich if (l3_proto == htons(ETH_P_IP)) { 1407c5aff182SThomas Petazzoni struct iphdr *ip4h = ip_hdr(skb); 1408c5aff182SThomas Petazzoni 1409c5aff182SThomas Petazzoni /* Calculate IPv4 checksum and L4 checksum */ 1410c5aff182SThomas Petazzoni ip_hdr_len = ip4h->ihl; 1411c5aff182SThomas Petazzoni l4_proto = ip4h->protocol; 1412817dbfa5SVlad Yasevich } else if (l3_proto == htons(ETH_P_IPV6)) { 1413c5aff182SThomas Petazzoni struct ipv6hdr *ip6h = ipv6_hdr(skb); 1414c5aff182SThomas Petazzoni 1415c5aff182SThomas Petazzoni /* Read l4_protocol from one of IPv6 extra headers */ 1416c5aff182SThomas Petazzoni if (skb_network_header_len(skb) > 0) 1417c5aff182SThomas Petazzoni ip_hdr_len = (skb_network_header_len(skb) >> 2); 1418c5aff182SThomas Petazzoni l4_proto = ip6h->nexthdr; 1419c5aff182SThomas Petazzoni } else 1420c5aff182SThomas Petazzoni return MVNETA_TX_L4_CSUM_NOT; 1421c5aff182SThomas Petazzoni 1422c5aff182SThomas Petazzoni return mvneta_txq_desc_csum(skb_network_offset(skb), 1423817dbfa5SVlad Yasevich l3_proto, ip_hdr_len, l4_proto); 1424c5aff182SThomas Petazzoni } 1425c5aff182SThomas Petazzoni 1426c5aff182SThomas Petazzoni return MVNETA_TX_L4_CSUM_NOT; 1427c5aff182SThomas Petazzoni } 1428c5aff182SThomas Petazzoni 14296a20c175SThomas Petazzoni /* Returns rx queue pointer (find last set bit) according to causeRxTx 1430c5aff182SThomas Petazzoni * value 1431c5aff182SThomas Petazzoni */ 1432c5aff182SThomas Petazzoni static struct mvneta_rx_queue *mvneta_rx_policy(struct mvneta_port *pp, 1433c5aff182SThomas Petazzoni u32 cause) 1434c5aff182SThomas Petazzoni { 1435c5aff182SThomas Petazzoni int queue = fls(cause >> 8) - 1; 1436c5aff182SThomas Petazzoni 1437c5aff182SThomas Petazzoni return (queue < 0 || queue >= rxq_number) ? NULL : &pp->rxqs[queue]; 1438c5aff182SThomas Petazzoni } 1439c5aff182SThomas Petazzoni 1440c5aff182SThomas Petazzoni /* Drop packets received by the RXQ and free buffers */ 1441c5aff182SThomas Petazzoni static void mvneta_rxq_drop_pkts(struct mvneta_port *pp, 1442c5aff182SThomas Petazzoni struct mvneta_rx_queue *rxq) 1443c5aff182SThomas Petazzoni { 1444c5aff182SThomas Petazzoni int rx_done, i; 1445c5aff182SThomas Petazzoni 1446c5aff182SThomas Petazzoni rx_done = mvneta_rxq_busy_desc_num_get(pp, rxq); 1447c5aff182SThomas Petazzoni for (i = 0; i < rxq->size; i++) { 1448c5aff182SThomas Petazzoni struct mvneta_rx_desc *rx_desc = rxq->descs + i; 14498ec2cd48Swilly tarreau void *data = (void *)rx_desc->buf_cookie; 1450c5aff182SThomas Petazzoni 14518ec2cd48Swilly tarreau mvneta_frag_free(pp, data); 1452c5aff182SThomas Petazzoni dma_unmap_single(pp->dev->dev.parent, rx_desc->buf_phys_addr, 1453a328f3a0SEzequiel Garcia MVNETA_RX_BUF_SIZE(pp->pkt_size), DMA_FROM_DEVICE); 1454c5aff182SThomas Petazzoni } 1455c5aff182SThomas Petazzoni 1456c5aff182SThomas Petazzoni if (rx_done) 1457c5aff182SThomas Petazzoni mvneta_rxq_desc_num_update(pp, rxq, rx_done, rx_done); 1458c5aff182SThomas Petazzoni } 1459c5aff182SThomas Petazzoni 1460c5aff182SThomas Petazzoni /* Main rx processing */ 1461c5aff182SThomas Petazzoni static int mvneta_rx(struct mvneta_port *pp, int rx_todo, 1462c5aff182SThomas Petazzoni struct mvneta_rx_queue *rxq) 1463c5aff182SThomas Petazzoni { 1464c5aff182SThomas Petazzoni struct net_device *dev = pp->dev; 1465a84e3289SSimon Guinot int rx_done; 1466dc4277ddSwilly tarreau u32 rcvd_pkts = 0; 1467dc4277ddSwilly tarreau u32 rcvd_bytes = 0; 1468c5aff182SThomas Petazzoni 1469c5aff182SThomas Petazzoni /* Get number of received packets */ 1470c5aff182SThomas Petazzoni rx_done = mvneta_rxq_busy_desc_num_get(pp, rxq); 1471c5aff182SThomas Petazzoni 1472c5aff182SThomas Petazzoni if (rx_todo > rx_done) 1473c5aff182SThomas Petazzoni rx_todo = rx_done; 1474c5aff182SThomas Petazzoni 1475c5aff182SThomas Petazzoni rx_done = 0; 1476c5aff182SThomas Petazzoni 1477c5aff182SThomas Petazzoni /* Fairness NAPI loop */ 1478c5aff182SThomas Petazzoni while (rx_done < rx_todo) { 1479c5aff182SThomas Petazzoni struct mvneta_rx_desc *rx_desc = mvneta_rxq_next_desc_get(rxq); 1480c5aff182SThomas Petazzoni struct sk_buff *skb; 14818ec2cd48Swilly tarreau unsigned char *data; 1482c5aff182SThomas Petazzoni u32 rx_status; 1483c5aff182SThomas Petazzoni int rx_bytes, err; 1484c5aff182SThomas Petazzoni 1485c5aff182SThomas Petazzoni rx_done++; 1486c5aff182SThomas Petazzoni rx_status = rx_desc->status; 1487f19fadfcSwilly tarreau rx_bytes = rx_desc->data_size - (ETH_FCS_LEN + MVNETA_MH_SIZE); 14888ec2cd48Swilly tarreau data = (unsigned char *)rx_desc->buf_cookie; 1489c5aff182SThomas Petazzoni 14905428213cSwilly tarreau if (!mvneta_rxq_desc_is_first_last(rx_status) || 1491f19fadfcSwilly tarreau (rx_status & MVNETA_RXD_ERR_SUMMARY)) { 1492f19fadfcSwilly tarreau err_drop_frame: 1493c5aff182SThomas Petazzoni dev->stats.rx_errors++; 1494c5aff182SThomas Petazzoni mvneta_rx_error(pp, rx_desc); 14958ec2cd48Swilly tarreau /* leave the descriptor untouched */ 1496c5aff182SThomas Petazzoni continue; 1497c5aff182SThomas Petazzoni } 1498c5aff182SThomas Petazzoni 1499f19fadfcSwilly tarreau if (rx_bytes <= rx_copybreak) { 1500f19fadfcSwilly tarreau /* better copy a small frame and not unmap the DMA region */ 1501f19fadfcSwilly tarreau skb = netdev_alloc_skb_ip_align(dev, rx_bytes); 1502f19fadfcSwilly tarreau if (unlikely(!skb)) 1503f19fadfcSwilly tarreau goto err_drop_frame; 1504f19fadfcSwilly tarreau 1505f19fadfcSwilly tarreau dma_sync_single_range_for_cpu(dev->dev.parent, 1506f19fadfcSwilly tarreau rx_desc->buf_phys_addr, 1507f19fadfcSwilly tarreau MVNETA_MH_SIZE + NET_SKB_PAD, 1508f19fadfcSwilly tarreau rx_bytes, 1509f19fadfcSwilly tarreau DMA_FROM_DEVICE); 1510f19fadfcSwilly tarreau memcpy(skb_put(skb, rx_bytes), 1511f19fadfcSwilly tarreau data + MVNETA_MH_SIZE + NET_SKB_PAD, 1512f19fadfcSwilly tarreau rx_bytes); 1513f19fadfcSwilly tarreau 1514f19fadfcSwilly tarreau skb->protocol = eth_type_trans(skb, dev); 1515f19fadfcSwilly tarreau mvneta_rx_csum(pp, rx_status, skb); 1516f19fadfcSwilly tarreau napi_gro_receive(&pp->napi, skb); 1517f19fadfcSwilly tarreau 1518f19fadfcSwilly tarreau rcvd_pkts++; 1519f19fadfcSwilly tarreau rcvd_bytes += rx_bytes; 1520f19fadfcSwilly tarreau 1521f19fadfcSwilly tarreau /* leave the descriptor and buffer untouched */ 1522f19fadfcSwilly tarreau continue; 1523f19fadfcSwilly tarreau } 1524f19fadfcSwilly tarreau 1525a84e3289SSimon Guinot /* Refill processing */ 1526a84e3289SSimon Guinot err = mvneta_rx_refill(pp, rx_desc); 1527a84e3289SSimon Guinot if (err) { 1528a84e3289SSimon Guinot netdev_err(dev, "Linux processing - Can't refill\n"); 1529a84e3289SSimon Guinot rxq->missed++; 1530a84e3289SSimon Guinot goto err_drop_frame; 1531a84e3289SSimon Guinot } 1532a84e3289SSimon Guinot 1533f19fadfcSwilly tarreau skb = build_skb(data, pp->frag_size > PAGE_SIZE ? 0 : pp->frag_size); 1534f19fadfcSwilly tarreau if (!skb) 1535f19fadfcSwilly tarreau goto err_drop_frame; 1536f19fadfcSwilly tarreau 1537f19fadfcSwilly tarreau dma_unmap_single(dev->dev.parent, rx_desc->buf_phys_addr, 1538a328f3a0SEzequiel Garcia MVNETA_RX_BUF_SIZE(pp->pkt_size), DMA_FROM_DEVICE); 1539c5aff182SThomas Petazzoni 1540dc4277ddSwilly tarreau rcvd_pkts++; 1541dc4277ddSwilly tarreau rcvd_bytes += rx_bytes; 1542c5aff182SThomas Petazzoni 1543c5aff182SThomas Petazzoni /* Linux processing */ 15448ec2cd48Swilly tarreau skb_reserve(skb, MVNETA_MH_SIZE + NET_SKB_PAD); 1545c5aff182SThomas Petazzoni skb_put(skb, rx_bytes); 1546c5aff182SThomas Petazzoni 1547c5aff182SThomas Petazzoni skb->protocol = eth_type_trans(skb, dev); 1548c5aff182SThomas Petazzoni 15495428213cSwilly tarreau mvneta_rx_csum(pp, rx_status, skb); 1550c5aff182SThomas Petazzoni 1551c5aff182SThomas Petazzoni napi_gro_receive(&pp->napi, skb); 1552c5aff182SThomas Petazzoni } 1553c5aff182SThomas Petazzoni 1554dc4277ddSwilly tarreau if (rcvd_pkts) { 155574c41b04Swilly tarreau struct mvneta_pcpu_stats *stats = this_cpu_ptr(pp->stats); 155674c41b04Swilly tarreau 155774c41b04Swilly tarreau u64_stats_update_begin(&stats->syncp); 155874c41b04Swilly tarreau stats->rx_packets += rcvd_pkts; 155974c41b04Swilly tarreau stats->rx_bytes += rcvd_bytes; 156074c41b04Swilly tarreau u64_stats_update_end(&stats->syncp); 1561dc4277ddSwilly tarreau } 1562dc4277ddSwilly tarreau 1563c5aff182SThomas Petazzoni /* Update rxq management counters */ 1564a84e3289SSimon Guinot mvneta_rxq_desc_num_update(pp, rxq, rx_done, rx_done); 1565c5aff182SThomas Petazzoni 1566c5aff182SThomas Petazzoni return rx_done; 1567c5aff182SThomas Petazzoni } 1568c5aff182SThomas Petazzoni 15692adb719dSEzequiel Garcia static inline void 15702adb719dSEzequiel Garcia mvneta_tso_put_hdr(struct sk_buff *skb, 15712adb719dSEzequiel Garcia struct mvneta_port *pp, struct mvneta_tx_queue *txq) 15722adb719dSEzequiel Garcia { 15732adb719dSEzequiel Garcia struct mvneta_tx_desc *tx_desc; 15742adb719dSEzequiel Garcia int hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb); 15752adb719dSEzequiel Garcia 15762adb719dSEzequiel Garcia txq->tx_skb[txq->txq_put_index] = NULL; 15772adb719dSEzequiel Garcia tx_desc = mvneta_txq_next_desc_get(txq); 15782adb719dSEzequiel Garcia tx_desc->data_size = hdr_len; 15792adb719dSEzequiel Garcia tx_desc->command = mvneta_skb_tx_csum(pp, skb); 15802adb719dSEzequiel Garcia tx_desc->command |= MVNETA_TXD_F_DESC; 15812adb719dSEzequiel Garcia tx_desc->buf_phys_addr = txq->tso_hdrs_phys + 15822adb719dSEzequiel Garcia txq->txq_put_index * TSO_HEADER_SIZE; 15832adb719dSEzequiel Garcia mvneta_txq_inc_put(txq); 15842adb719dSEzequiel Garcia } 15852adb719dSEzequiel Garcia 15862adb719dSEzequiel Garcia static inline int 15872adb719dSEzequiel Garcia mvneta_tso_put_data(struct net_device *dev, struct mvneta_tx_queue *txq, 15882adb719dSEzequiel Garcia struct sk_buff *skb, char *data, int size, 15892adb719dSEzequiel Garcia bool last_tcp, bool is_last) 15902adb719dSEzequiel Garcia { 15912adb719dSEzequiel Garcia struct mvneta_tx_desc *tx_desc; 15922adb719dSEzequiel Garcia 15932adb719dSEzequiel Garcia tx_desc = mvneta_txq_next_desc_get(txq); 15942adb719dSEzequiel Garcia tx_desc->data_size = size; 15952adb719dSEzequiel Garcia tx_desc->buf_phys_addr = dma_map_single(dev->dev.parent, data, 15962adb719dSEzequiel Garcia size, DMA_TO_DEVICE); 15972adb719dSEzequiel Garcia if (unlikely(dma_mapping_error(dev->dev.parent, 15982adb719dSEzequiel Garcia tx_desc->buf_phys_addr))) { 15992adb719dSEzequiel Garcia mvneta_txq_desc_put(txq); 16002adb719dSEzequiel Garcia return -ENOMEM; 16012adb719dSEzequiel Garcia } 16022adb719dSEzequiel Garcia 16032adb719dSEzequiel Garcia tx_desc->command = 0; 16042adb719dSEzequiel Garcia txq->tx_skb[txq->txq_put_index] = NULL; 16052adb719dSEzequiel Garcia 16062adb719dSEzequiel Garcia if (last_tcp) { 16072adb719dSEzequiel Garcia /* last descriptor in the TCP packet */ 16082adb719dSEzequiel Garcia tx_desc->command = MVNETA_TXD_L_DESC; 16092adb719dSEzequiel Garcia 16102adb719dSEzequiel Garcia /* last descriptor in SKB */ 16112adb719dSEzequiel Garcia if (is_last) 16122adb719dSEzequiel Garcia txq->tx_skb[txq->txq_put_index] = skb; 16132adb719dSEzequiel Garcia } 16142adb719dSEzequiel Garcia mvneta_txq_inc_put(txq); 16152adb719dSEzequiel Garcia return 0; 16162adb719dSEzequiel Garcia } 16172adb719dSEzequiel Garcia 16182adb719dSEzequiel Garcia static int mvneta_tx_tso(struct sk_buff *skb, struct net_device *dev, 16192adb719dSEzequiel Garcia struct mvneta_tx_queue *txq) 16202adb719dSEzequiel Garcia { 16212adb719dSEzequiel Garcia int total_len, data_left; 16222adb719dSEzequiel Garcia int desc_count = 0; 16232adb719dSEzequiel Garcia struct mvneta_port *pp = netdev_priv(dev); 16242adb719dSEzequiel Garcia struct tso_t tso; 16252adb719dSEzequiel Garcia int hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb); 16262adb719dSEzequiel Garcia int i; 16272adb719dSEzequiel Garcia 16282adb719dSEzequiel Garcia /* Count needed descriptors */ 16292adb719dSEzequiel Garcia if ((txq->count + tso_count_descs(skb)) >= txq->size) 16302adb719dSEzequiel Garcia return 0; 16312adb719dSEzequiel Garcia 16322adb719dSEzequiel Garcia if (skb_headlen(skb) < (skb_transport_offset(skb) + tcp_hdrlen(skb))) { 16332adb719dSEzequiel Garcia pr_info("*** Is this even possible???!?!?\n"); 16342adb719dSEzequiel Garcia return 0; 16352adb719dSEzequiel Garcia } 16362adb719dSEzequiel Garcia 16372adb719dSEzequiel Garcia /* Initialize the TSO handler, and prepare the first payload */ 16382adb719dSEzequiel Garcia tso_start(skb, &tso); 16392adb719dSEzequiel Garcia 16402adb719dSEzequiel Garcia total_len = skb->len - hdr_len; 16412adb719dSEzequiel Garcia while (total_len > 0) { 16422adb719dSEzequiel Garcia char *hdr; 16432adb719dSEzequiel Garcia 16442adb719dSEzequiel Garcia data_left = min_t(int, skb_shinfo(skb)->gso_size, total_len); 16452adb719dSEzequiel Garcia total_len -= data_left; 16462adb719dSEzequiel Garcia desc_count++; 16472adb719dSEzequiel Garcia 16482adb719dSEzequiel Garcia /* prepare packet headers: MAC + IP + TCP */ 16492adb719dSEzequiel Garcia hdr = txq->tso_hdrs + txq->txq_put_index * TSO_HEADER_SIZE; 16502adb719dSEzequiel Garcia tso_build_hdr(skb, hdr, &tso, data_left, total_len == 0); 16512adb719dSEzequiel Garcia 16522adb719dSEzequiel Garcia mvneta_tso_put_hdr(skb, pp, txq); 16532adb719dSEzequiel Garcia 16542adb719dSEzequiel Garcia while (data_left > 0) { 16552adb719dSEzequiel Garcia int size; 16562adb719dSEzequiel Garcia desc_count++; 16572adb719dSEzequiel Garcia 16582adb719dSEzequiel Garcia size = min_t(int, tso.size, data_left); 16592adb719dSEzequiel Garcia 16602adb719dSEzequiel Garcia if (mvneta_tso_put_data(dev, txq, skb, 16612adb719dSEzequiel Garcia tso.data, size, 16622adb719dSEzequiel Garcia size == data_left, 16632adb719dSEzequiel Garcia total_len == 0)) 16642adb719dSEzequiel Garcia goto err_release; 16652adb719dSEzequiel Garcia data_left -= size; 16662adb719dSEzequiel Garcia 16672adb719dSEzequiel Garcia tso_build_data(skb, &tso, size); 16682adb719dSEzequiel Garcia } 16692adb719dSEzequiel Garcia } 16702adb719dSEzequiel Garcia 16712adb719dSEzequiel Garcia return desc_count; 16722adb719dSEzequiel Garcia 16732adb719dSEzequiel Garcia err_release: 16742adb719dSEzequiel Garcia /* Release all used data descriptors; header descriptors must not 16752adb719dSEzequiel Garcia * be DMA-unmapped. 16762adb719dSEzequiel Garcia */ 16772adb719dSEzequiel Garcia for (i = desc_count - 1; i >= 0; i--) { 16782adb719dSEzequiel Garcia struct mvneta_tx_desc *tx_desc = txq->descs + i; 16792e3173a3SEzequiel Garcia if (!IS_TSO_HEADER(txq, tx_desc->buf_phys_addr)) 16802adb719dSEzequiel Garcia dma_unmap_single(pp->dev->dev.parent, 16812adb719dSEzequiel Garcia tx_desc->buf_phys_addr, 16822adb719dSEzequiel Garcia tx_desc->data_size, 16832adb719dSEzequiel Garcia DMA_TO_DEVICE); 16842adb719dSEzequiel Garcia mvneta_txq_desc_put(txq); 16852adb719dSEzequiel Garcia } 16862adb719dSEzequiel Garcia return 0; 16872adb719dSEzequiel Garcia } 16882adb719dSEzequiel Garcia 1689c5aff182SThomas Petazzoni /* Handle tx fragmentation processing */ 1690c5aff182SThomas Petazzoni static int mvneta_tx_frag_process(struct mvneta_port *pp, struct sk_buff *skb, 1691c5aff182SThomas Petazzoni struct mvneta_tx_queue *txq) 1692c5aff182SThomas Petazzoni { 1693c5aff182SThomas Petazzoni struct mvneta_tx_desc *tx_desc; 16943d4ea02fSEzequiel Garcia int i, nr_frags = skb_shinfo(skb)->nr_frags; 1695c5aff182SThomas Petazzoni 16963d4ea02fSEzequiel Garcia for (i = 0; i < nr_frags; i++) { 1697c5aff182SThomas Petazzoni skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 1698c5aff182SThomas Petazzoni void *addr = page_address(frag->page.p) + frag->page_offset; 1699c5aff182SThomas Petazzoni 1700c5aff182SThomas Petazzoni tx_desc = mvneta_txq_next_desc_get(txq); 1701c5aff182SThomas Petazzoni tx_desc->data_size = frag->size; 1702c5aff182SThomas Petazzoni 1703c5aff182SThomas Petazzoni tx_desc->buf_phys_addr = 1704c5aff182SThomas Petazzoni dma_map_single(pp->dev->dev.parent, addr, 1705c5aff182SThomas Petazzoni tx_desc->data_size, DMA_TO_DEVICE); 1706c5aff182SThomas Petazzoni 1707c5aff182SThomas Petazzoni if (dma_mapping_error(pp->dev->dev.parent, 1708c5aff182SThomas Petazzoni tx_desc->buf_phys_addr)) { 1709c5aff182SThomas Petazzoni mvneta_txq_desc_put(txq); 1710c5aff182SThomas Petazzoni goto error; 1711c5aff182SThomas Petazzoni } 1712c5aff182SThomas Petazzoni 17133d4ea02fSEzequiel Garcia if (i == nr_frags - 1) { 1714c5aff182SThomas Petazzoni /* Last descriptor */ 1715c5aff182SThomas Petazzoni tx_desc->command = MVNETA_TXD_L_DESC | MVNETA_TXD_Z_PAD; 1716c5aff182SThomas Petazzoni txq->tx_skb[txq->txq_put_index] = skb; 1717c5aff182SThomas Petazzoni } else { 1718c5aff182SThomas Petazzoni /* Descriptor in the middle: Not First, Not Last */ 1719c5aff182SThomas Petazzoni tx_desc->command = 0; 1720c5aff182SThomas Petazzoni txq->tx_skb[txq->txq_put_index] = NULL; 1721c5aff182SThomas Petazzoni } 17223d4ea02fSEzequiel Garcia mvneta_txq_inc_put(txq); 1723c5aff182SThomas Petazzoni } 1724c5aff182SThomas Petazzoni 1725c5aff182SThomas Petazzoni return 0; 1726c5aff182SThomas Petazzoni 1727c5aff182SThomas Petazzoni error: 1728c5aff182SThomas Petazzoni /* Release all descriptors that were used to map fragments of 17296a20c175SThomas Petazzoni * this packet, as well as the corresponding DMA mappings 17306a20c175SThomas Petazzoni */ 1731c5aff182SThomas Petazzoni for (i = i - 1; i >= 0; i--) { 1732c5aff182SThomas Petazzoni tx_desc = txq->descs + i; 1733c5aff182SThomas Petazzoni dma_unmap_single(pp->dev->dev.parent, 1734c5aff182SThomas Petazzoni tx_desc->buf_phys_addr, 1735c5aff182SThomas Petazzoni tx_desc->data_size, 1736c5aff182SThomas Petazzoni DMA_TO_DEVICE); 1737c5aff182SThomas Petazzoni mvneta_txq_desc_put(txq); 1738c5aff182SThomas Petazzoni } 1739c5aff182SThomas Petazzoni 1740c5aff182SThomas Petazzoni return -ENOMEM; 1741c5aff182SThomas Petazzoni } 1742c5aff182SThomas Petazzoni 1743c5aff182SThomas Petazzoni /* Main tx processing */ 1744c5aff182SThomas Petazzoni static int mvneta_tx(struct sk_buff *skb, struct net_device *dev) 1745c5aff182SThomas Petazzoni { 1746c5aff182SThomas Petazzoni struct mvneta_port *pp = netdev_priv(dev); 1747ee40a116SWilly Tarreau u16 txq_id = skb_get_queue_mapping(skb); 1748ee40a116SWilly Tarreau struct mvneta_tx_queue *txq = &pp->txqs[txq_id]; 1749c5aff182SThomas Petazzoni struct mvneta_tx_desc *tx_desc; 17505f478b41SEric Dumazet int len = skb->len; 1751c5aff182SThomas Petazzoni int frags = 0; 1752c5aff182SThomas Petazzoni u32 tx_cmd; 1753c5aff182SThomas Petazzoni 1754c5aff182SThomas Petazzoni if (!netif_running(dev)) 1755c5aff182SThomas Petazzoni goto out; 1756c5aff182SThomas Petazzoni 17572adb719dSEzequiel Garcia if (skb_is_gso(skb)) { 17582adb719dSEzequiel Garcia frags = mvneta_tx_tso(skb, dev, txq); 17592adb719dSEzequiel Garcia goto out; 17602adb719dSEzequiel Garcia } 17612adb719dSEzequiel Garcia 1762c5aff182SThomas Petazzoni frags = skb_shinfo(skb)->nr_frags + 1; 1763c5aff182SThomas Petazzoni 1764c5aff182SThomas Petazzoni /* Get a descriptor for the first part of the packet */ 1765c5aff182SThomas Petazzoni tx_desc = mvneta_txq_next_desc_get(txq); 1766c5aff182SThomas Petazzoni 1767c5aff182SThomas Petazzoni tx_cmd = mvneta_skb_tx_csum(pp, skb); 1768c5aff182SThomas Petazzoni 1769c5aff182SThomas Petazzoni tx_desc->data_size = skb_headlen(skb); 1770c5aff182SThomas Petazzoni 1771c5aff182SThomas Petazzoni tx_desc->buf_phys_addr = dma_map_single(dev->dev.parent, skb->data, 1772c5aff182SThomas Petazzoni tx_desc->data_size, 1773c5aff182SThomas Petazzoni DMA_TO_DEVICE); 1774c5aff182SThomas Petazzoni if (unlikely(dma_mapping_error(dev->dev.parent, 1775c5aff182SThomas Petazzoni tx_desc->buf_phys_addr))) { 1776c5aff182SThomas Petazzoni mvneta_txq_desc_put(txq); 1777c5aff182SThomas Petazzoni frags = 0; 1778c5aff182SThomas Petazzoni goto out; 1779c5aff182SThomas Petazzoni } 1780c5aff182SThomas Petazzoni 1781c5aff182SThomas Petazzoni if (frags == 1) { 1782c5aff182SThomas Petazzoni /* First and Last descriptor */ 1783c5aff182SThomas Petazzoni tx_cmd |= MVNETA_TXD_FLZ_DESC; 1784c5aff182SThomas Petazzoni tx_desc->command = tx_cmd; 1785c5aff182SThomas Petazzoni txq->tx_skb[txq->txq_put_index] = skb; 1786c5aff182SThomas Petazzoni mvneta_txq_inc_put(txq); 1787c5aff182SThomas Petazzoni } else { 1788c5aff182SThomas Petazzoni /* First but not Last */ 1789c5aff182SThomas Petazzoni tx_cmd |= MVNETA_TXD_F_DESC; 1790c5aff182SThomas Petazzoni txq->tx_skb[txq->txq_put_index] = NULL; 1791c5aff182SThomas Petazzoni mvneta_txq_inc_put(txq); 1792c5aff182SThomas Petazzoni tx_desc->command = tx_cmd; 1793c5aff182SThomas Petazzoni /* Continue with other skb fragments */ 1794c5aff182SThomas Petazzoni if (mvneta_tx_frag_process(pp, skb, txq)) { 1795c5aff182SThomas Petazzoni dma_unmap_single(dev->dev.parent, 1796c5aff182SThomas Petazzoni tx_desc->buf_phys_addr, 1797c5aff182SThomas Petazzoni tx_desc->data_size, 1798c5aff182SThomas Petazzoni DMA_TO_DEVICE); 1799c5aff182SThomas Petazzoni mvneta_txq_desc_put(txq); 1800c5aff182SThomas Petazzoni frags = 0; 1801c5aff182SThomas Petazzoni goto out; 1802c5aff182SThomas Petazzoni } 1803c5aff182SThomas Petazzoni } 1804c5aff182SThomas Petazzoni 1805e19d2ddaSEzequiel Garcia out: 1806e19d2ddaSEzequiel Garcia if (frags > 0) { 1807e19d2ddaSEzequiel Garcia struct mvneta_pcpu_stats *stats = this_cpu_ptr(pp->stats); 1808e19d2ddaSEzequiel Garcia struct netdev_queue *nq = netdev_get_tx_queue(dev, txq_id); 1809e19d2ddaSEzequiel Garcia 1810c5aff182SThomas Petazzoni txq->count += frags; 1811c5aff182SThomas Petazzoni mvneta_txq_pend_desc_add(pp, txq, frags); 1812c5aff182SThomas Petazzoni 18138eef5f97SEzequiel Garcia if (txq->count >= txq->tx_stop_threshold) 1814c5aff182SThomas Petazzoni netif_tx_stop_queue(nq); 1815c5aff182SThomas Petazzoni 181674c41b04Swilly tarreau u64_stats_update_begin(&stats->syncp); 181774c41b04Swilly tarreau stats->tx_packets++; 18185f478b41SEric Dumazet stats->tx_bytes += len; 181974c41b04Swilly tarreau u64_stats_update_end(&stats->syncp); 1820c5aff182SThomas Petazzoni } else { 1821c5aff182SThomas Petazzoni dev->stats.tx_dropped++; 1822c5aff182SThomas Petazzoni dev_kfree_skb_any(skb); 1823c5aff182SThomas Petazzoni } 1824c5aff182SThomas Petazzoni 1825c5aff182SThomas Petazzoni return NETDEV_TX_OK; 1826c5aff182SThomas Petazzoni } 1827c5aff182SThomas Petazzoni 1828c5aff182SThomas Petazzoni 1829c5aff182SThomas Petazzoni /* Free tx resources, when resetting a port */ 1830c5aff182SThomas Petazzoni static void mvneta_txq_done_force(struct mvneta_port *pp, 1831c5aff182SThomas Petazzoni struct mvneta_tx_queue *txq) 1832c5aff182SThomas Petazzoni 1833c5aff182SThomas Petazzoni { 1834c5aff182SThomas Petazzoni int tx_done = txq->count; 1835c5aff182SThomas Petazzoni 1836c5aff182SThomas Petazzoni mvneta_txq_bufs_free(pp, txq, tx_done); 1837c5aff182SThomas Petazzoni 1838c5aff182SThomas Petazzoni /* reset txq */ 1839c5aff182SThomas Petazzoni txq->count = 0; 1840c5aff182SThomas Petazzoni txq->txq_put_index = 0; 1841c5aff182SThomas Petazzoni txq->txq_get_index = 0; 1842c5aff182SThomas Petazzoni } 1843c5aff182SThomas Petazzoni 18446c498974Swilly tarreau /* Handle tx done - called in softirq context. The <cause_tx_done> argument 18456c498974Swilly tarreau * must be a valid cause according to MVNETA_TXQ_INTR_MASK_ALL. 18466c498974Swilly tarreau */ 18470713a86aSArnaud Ebalard static void mvneta_tx_done_gbe(struct mvneta_port *pp, u32 cause_tx_done) 1848c5aff182SThomas Petazzoni { 1849c5aff182SThomas Petazzoni struct mvneta_tx_queue *txq; 1850c5aff182SThomas Petazzoni struct netdev_queue *nq; 1851c5aff182SThomas Petazzoni 18526c498974Swilly tarreau while (cause_tx_done) { 1853c5aff182SThomas Petazzoni txq = mvneta_tx_done_policy(pp, cause_tx_done); 1854c5aff182SThomas Petazzoni 1855c5aff182SThomas Petazzoni nq = netdev_get_tx_queue(pp->dev, txq->id); 1856c5aff182SThomas Petazzoni __netif_tx_lock(nq, smp_processor_id()); 1857c5aff182SThomas Petazzoni 18580713a86aSArnaud Ebalard if (txq->count) 18590713a86aSArnaud Ebalard mvneta_txq_done(pp, txq); 1860c5aff182SThomas Petazzoni 1861c5aff182SThomas Petazzoni __netif_tx_unlock(nq); 1862c5aff182SThomas Petazzoni cause_tx_done &= ~((1 << txq->id)); 1863c5aff182SThomas Petazzoni } 1864c5aff182SThomas Petazzoni } 1865c5aff182SThomas Petazzoni 18666a20c175SThomas Petazzoni /* Compute crc8 of the specified address, using a unique algorithm , 1867c5aff182SThomas Petazzoni * according to hw spec, different than generic crc8 algorithm 1868c5aff182SThomas Petazzoni */ 1869c5aff182SThomas Petazzoni static int mvneta_addr_crc(unsigned char *addr) 1870c5aff182SThomas Petazzoni { 1871c5aff182SThomas Petazzoni int crc = 0; 1872c5aff182SThomas Petazzoni int i; 1873c5aff182SThomas Petazzoni 1874c5aff182SThomas Petazzoni for (i = 0; i < ETH_ALEN; i++) { 1875c5aff182SThomas Petazzoni int j; 1876c5aff182SThomas Petazzoni 1877c5aff182SThomas Petazzoni crc = (crc ^ addr[i]) << 8; 1878c5aff182SThomas Petazzoni for (j = 7; j >= 0; j--) { 1879c5aff182SThomas Petazzoni if (crc & (0x100 << j)) 1880c5aff182SThomas Petazzoni crc ^= 0x107 << j; 1881c5aff182SThomas Petazzoni } 1882c5aff182SThomas Petazzoni } 1883c5aff182SThomas Petazzoni 1884c5aff182SThomas Petazzoni return crc; 1885c5aff182SThomas Petazzoni } 1886c5aff182SThomas Petazzoni 1887c5aff182SThomas Petazzoni /* This method controls the net device special MAC multicast support. 1888c5aff182SThomas Petazzoni * The Special Multicast Table for MAC addresses supports MAC of the form 1889c5aff182SThomas Petazzoni * 0x01-00-5E-00-00-XX (where XX is between 0x00 and 0xFF). 1890c5aff182SThomas Petazzoni * The MAC DA[7:0] bits are used as a pointer to the Special Multicast 1891c5aff182SThomas Petazzoni * Table entries in the DA-Filter table. This method set the Special 1892c5aff182SThomas Petazzoni * Multicast Table appropriate entry. 1893c5aff182SThomas Petazzoni */ 1894c5aff182SThomas Petazzoni static void mvneta_set_special_mcast_addr(struct mvneta_port *pp, 1895c5aff182SThomas Petazzoni unsigned char last_byte, 1896c5aff182SThomas Petazzoni int queue) 1897c5aff182SThomas Petazzoni { 1898c5aff182SThomas Petazzoni unsigned int smc_table_reg; 1899c5aff182SThomas Petazzoni unsigned int tbl_offset; 1900c5aff182SThomas Petazzoni unsigned int reg_offset; 1901c5aff182SThomas Petazzoni 1902c5aff182SThomas Petazzoni /* Register offset from SMC table base */ 1903c5aff182SThomas Petazzoni tbl_offset = (last_byte / 4); 1904c5aff182SThomas Petazzoni /* Entry offset within the above reg */ 1905c5aff182SThomas Petazzoni reg_offset = last_byte % 4; 1906c5aff182SThomas Petazzoni 1907c5aff182SThomas Petazzoni smc_table_reg = mvreg_read(pp, (MVNETA_DA_FILT_SPEC_MCAST 1908c5aff182SThomas Petazzoni + tbl_offset * 4)); 1909c5aff182SThomas Petazzoni 1910c5aff182SThomas Petazzoni if (queue == -1) 1911c5aff182SThomas Petazzoni smc_table_reg &= ~(0xff << (8 * reg_offset)); 1912c5aff182SThomas Petazzoni else { 1913c5aff182SThomas Petazzoni smc_table_reg &= ~(0xff << (8 * reg_offset)); 1914c5aff182SThomas Petazzoni smc_table_reg |= ((0x01 | (queue << 1)) << (8 * reg_offset)); 1915c5aff182SThomas Petazzoni } 1916c5aff182SThomas Petazzoni 1917c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_DA_FILT_SPEC_MCAST + tbl_offset * 4, 1918c5aff182SThomas Petazzoni smc_table_reg); 1919c5aff182SThomas Petazzoni } 1920c5aff182SThomas Petazzoni 1921c5aff182SThomas Petazzoni /* This method controls the network device Other MAC multicast support. 1922c5aff182SThomas Petazzoni * The Other Multicast Table is used for multicast of another type. 1923c5aff182SThomas Petazzoni * A CRC-8 is used as an index to the Other Multicast Table entries 1924c5aff182SThomas Petazzoni * in the DA-Filter table. 1925c5aff182SThomas Petazzoni * The method gets the CRC-8 value from the calling routine and 1926c5aff182SThomas Petazzoni * sets the Other Multicast Table appropriate entry according to the 1927c5aff182SThomas Petazzoni * specified CRC-8 . 1928c5aff182SThomas Petazzoni */ 1929c5aff182SThomas Petazzoni static void mvneta_set_other_mcast_addr(struct mvneta_port *pp, 1930c5aff182SThomas Petazzoni unsigned char crc8, 1931c5aff182SThomas Petazzoni int queue) 1932c5aff182SThomas Petazzoni { 1933c5aff182SThomas Petazzoni unsigned int omc_table_reg; 1934c5aff182SThomas Petazzoni unsigned int tbl_offset; 1935c5aff182SThomas Petazzoni unsigned int reg_offset; 1936c5aff182SThomas Petazzoni 1937c5aff182SThomas Petazzoni tbl_offset = (crc8 / 4) * 4; /* Register offset from OMC table base */ 1938c5aff182SThomas Petazzoni reg_offset = crc8 % 4; /* Entry offset within the above reg */ 1939c5aff182SThomas Petazzoni 1940c5aff182SThomas Petazzoni omc_table_reg = mvreg_read(pp, MVNETA_DA_FILT_OTH_MCAST + tbl_offset); 1941c5aff182SThomas Petazzoni 1942c5aff182SThomas Petazzoni if (queue == -1) { 1943c5aff182SThomas Petazzoni /* Clear accepts frame bit at specified Other DA table entry */ 1944c5aff182SThomas Petazzoni omc_table_reg &= ~(0xff << (8 * reg_offset)); 1945c5aff182SThomas Petazzoni } else { 1946c5aff182SThomas Petazzoni omc_table_reg &= ~(0xff << (8 * reg_offset)); 1947c5aff182SThomas Petazzoni omc_table_reg |= ((0x01 | (queue << 1)) << (8 * reg_offset)); 1948c5aff182SThomas Petazzoni } 1949c5aff182SThomas Petazzoni 1950c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_DA_FILT_OTH_MCAST + tbl_offset, omc_table_reg); 1951c5aff182SThomas Petazzoni } 1952c5aff182SThomas Petazzoni 1953c5aff182SThomas Petazzoni /* The network device supports multicast using two tables: 1954c5aff182SThomas Petazzoni * 1) Special Multicast Table for MAC addresses of the form 1955c5aff182SThomas Petazzoni * 0x01-00-5E-00-00-XX (where XX is between 0x00 and 0xFF). 1956c5aff182SThomas Petazzoni * The MAC DA[7:0] bits are used as a pointer to the Special Multicast 1957c5aff182SThomas Petazzoni * Table entries in the DA-Filter table. 1958c5aff182SThomas Petazzoni * 2) Other Multicast Table for multicast of another type. A CRC-8 value 1959c5aff182SThomas Petazzoni * is used as an index to the Other Multicast Table entries in the 1960c5aff182SThomas Petazzoni * DA-Filter table. 1961c5aff182SThomas Petazzoni */ 1962c5aff182SThomas Petazzoni static int mvneta_mcast_addr_set(struct mvneta_port *pp, unsigned char *p_addr, 1963c5aff182SThomas Petazzoni int queue) 1964c5aff182SThomas Petazzoni { 1965c5aff182SThomas Petazzoni unsigned char crc_result = 0; 1966c5aff182SThomas Petazzoni 1967c5aff182SThomas Petazzoni if (memcmp(p_addr, "\x01\x00\x5e\x00\x00", 5) == 0) { 1968c5aff182SThomas Petazzoni mvneta_set_special_mcast_addr(pp, p_addr[5], queue); 1969c5aff182SThomas Petazzoni return 0; 1970c5aff182SThomas Petazzoni } 1971c5aff182SThomas Petazzoni 1972c5aff182SThomas Petazzoni crc_result = mvneta_addr_crc(p_addr); 1973c5aff182SThomas Petazzoni if (queue == -1) { 1974c5aff182SThomas Petazzoni if (pp->mcast_count[crc_result] == 0) { 1975c5aff182SThomas Petazzoni netdev_info(pp->dev, "No valid Mcast for crc8=0x%02x\n", 1976c5aff182SThomas Petazzoni crc_result); 1977c5aff182SThomas Petazzoni return -EINVAL; 1978c5aff182SThomas Petazzoni } 1979c5aff182SThomas Petazzoni 1980c5aff182SThomas Petazzoni pp->mcast_count[crc_result]--; 1981c5aff182SThomas Petazzoni if (pp->mcast_count[crc_result] != 0) { 1982c5aff182SThomas Petazzoni netdev_info(pp->dev, 1983c5aff182SThomas Petazzoni "After delete there are %d valid Mcast for crc8=0x%02x\n", 1984c5aff182SThomas Petazzoni pp->mcast_count[crc_result], crc_result); 1985c5aff182SThomas Petazzoni return -EINVAL; 1986c5aff182SThomas Petazzoni } 1987c5aff182SThomas Petazzoni } else 1988c5aff182SThomas Petazzoni pp->mcast_count[crc_result]++; 1989c5aff182SThomas Petazzoni 1990c5aff182SThomas Petazzoni mvneta_set_other_mcast_addr(pp, crc_result, queue); 1991c5aff182SThomas Petazzoni 1992c5aff182SThomas Petazzoni return 0; 1993c5aff182SThomas Petazzoni } 1994c5aff182SThomas Petazzoni 1995c5aff182SThomas Petazzoni /* Configure Fitering mode of Ethernet port */ 1996c5aff182SThomas Petazzoni static void mvneta_rx_unicast_promisc_set(struct mvneta_port *pp, 1997c5aff182SThomas Petazzoni int is_promisc) 1998c5aff182SThomas Petazzoni { 1999c5aff182SThomas Petazzoni u32 port_cfg_reg, val; 2000c5aff182SThomas Petazzoni 2001c5aff182SThomas Petazzoni port_cfg_reg = mvreg_read(pp, MVNETA_PORT_CONFIG); 2002c5aff182SThomas Petazzoni 2003c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_TYPE_PRIO); 2004c5aff182SThomas Petazzoni 2005c5aff182SThomas Petazzoni /* Set / Clear UPM bit in port configuration register */ 2006c5aff182SThomas Petazzoni if (is_promisc) { 2007c5aff182SThomas Petazzoni /* Accept all Unicast addresses */ 2008c5aff182SThomas Petazzoni port_cfg_reg |= MVNETA_UNI_PROMISC_MODE; 2009c5aff182SThomas Petazzoni val |= MVNETA_FORCE_UNI; 2010c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_MAC_ADDR_LOW, 0xffff); 2011c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_MAC_ADDR_HIGH, 0xffffffff); 2012c5aff182SThomas Petazzoni } else { 2013c5aff182SThomas Petazzoni /* Reject all Unicast addresses */ 2014c5aff182SThomas Petazzoni port_cfg_reg &= ~MVNETA_UNI_PROMISC_MODE; 2015c5aff182SThomas Petazzoni val &= ~MVNETA_FORCE_UNI; 2016c5aff182SThomas Petazzoni } 2017c5aff182SThomas Petazzoni 2018c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_PORT_CONFIG, port_cfg_reg); 2019c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_TYPE_PRIO, val); 2020c5aff182SThomas Petazzoni } 2021c5aff182SThomas Petazzoni 2022c5aff182SThomas Petazzoni /* register unicast and multicast addresses */ 2023c5aff182SThomas Petazzoni static void mvneta_set_rx_mode(struct net_device *dev) 2024c5aff182SThomas Petazzoni { 2025c5aff182SThomas Petazzoni struct mvneta_port *pp = netdev_priv(dev); 2026c5aff182SThomas Petazzoni struct netdev_hw_addr *ha; 2027c5aff182SThomas Petazzoni 2028c5aff182SThomas Petazzoni if (dev->flags & IFF_PROMISC) { 2029c5aff182SThomas Petazzoni /* Accept all: Multicast + Unicast */ 2030c5aff182SThomas Petazzoni mvneta_rx_unicast_promisc_set(pp, 1); 2031c5aff182SThomas Petazzoni mvneta_set_ucast_table(pp, rxq_def); 2032c5aff182SThomas Petazzoni mvneta_set_special_mcast_table(pp, rxq_def); 2033c5aff182SThomas Petazzoni mvneta_set_other_mcast_table(pp, rxq_def); 2034c5aff182SThomas Petazzoni } else { 2035c5aff182SThomas Petazzoni /* Accept single Unicast */ 2036c5aff182SThomas Petazzoni mvneta_rx_unicast_promisc_set(pp, 0); 2037c5aff182SThomas Petazzoni mvneta_set_ucast_table(pp, -1); 2038c5aff182SThomas Petazzoni mvneta_mac_addr_set(pp, dev->dev_addr, rxq_def); 2039c5aff182SThomas Petazzoni 2040c5aff182SThomas Petazzoni if (dev->flags & IFF_ALLMULTI) { 2041c5aff182SThomas Petazzoni /* Accept all multicast */ 2042c5aff182SThomas Petazzoni mvneta_set_special_mcast_table(pp, rxq_def); 2043c5aff182SThomas Petazzoni mvneta_set_other_mcast_table(pp, rxq_def); 2044c5aff182SThomas Petazzoni } else { 2045c5aff182SThomas Petazzoni /* Accept only initialized multicast */ 2046c5aff182SThomas Petazzoni mvneta_set_special_mcast_table(pp, -1); 2047c5aff182SThomas Petazzoni mvneta_set_other_mcast_table(pp, -1); 2048c5aff182SThomas Petazzoni 2049c5aff182SThomas Petazzoni if (!netdev_mc_empty(dev)) { 2050c5aff182SThomas Petazzoni netdev_for_each_mc_addr(ha, dev) { 2051c5aff182SThomas Petazzoni mvneta_mcast_addr_set(pp, ha->addr, 2052c5aff182SThomas Petazzoni rxq_def); 2053c5aff182SThomas Petazzoni } 2054c5aff182SThomas Petazzoni } 2055c5aff182SThomas Petazzoni } 2056c5aff182SThomas Petazzoni } 2057c5aff182SThomas Petazzoni } 2058c5aff182SThomas Petazzoni 2059c5aff182SThomas Petazzoni /* Interrupt handling - the callback for request_irq() */ 2060c5aff182SThomas Petazzoni static irqreturn_t mvneta_isr(int irq, void *dev_id) 2061c5aff182SThomas Petazzoni { 2062c5aff182SThomas Petazzoni struct mvneta_port *pp = (struct mvneta_port *)dev_id; 2063c5aff182SThomas Petazzoni 2064c5aff182SThomas Petazzoni /* Mask all interrupts */ 2065c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_INTR_NEW_MASK, 0); 2066c5aff182SThomas Petazzoni 2067c5aff182SThomas Petazzoni napi_schedule(&pp->napi); 2068c5aff182SThomas Petazzoni 2069c5aff182SThomas Petazzoni return IRQ_HANDLED; 2070c5aff182SThomas Petazzoni } 2071c5aff182SThomas Petazzoni 2072898b2970SStas Sergeev static int mvneta_fixed_link_update(struct mvneta_port *pp, 2073898b2970SStas Sergeev struct phy_device *phy) 2074898b2970SStas Sergeev { 2075898b2970SStas Sergeev struct fixed_phy_status status; 2076898b2970SStas Sergeev struct fixed_phy_status changed = {}; 2077898b2970SStas Sergeev u32 gmac_stat = mvreg_read(pp, MVNETA_GMAC_STATUS); 2078898b2970SStas Sergeev 2079898b2970SStas Sergeev status.link = !!(gmac_stat & MVNETA_GMAC_LINK_UP); 2080898b2970SStas Sergeev if (gmac_stat & MVNETA_GMAC_SPEED_1000) 2081898b2970SStas Sergeev status.speed = SPEED_1000; 2082898b2970SStas Sergeev else if (gmac_stat & MVNETA_GMAC_SPEED_100) 2083898b2970SStas Sergeev status.speed = SPEED_100; 2084898b2970SStas Sergeev else 2085898b2970SStas Sergeev status.speed = SPEED_10; 2086898b2970SStas Sergeev status.duplex = !!(gmac_stat & MVNETA_GMAC_FULL_DUPLEX); 2087898b2970SStas Sergeev changed.link = 1; 2088898b2970SStas Sergeev changed.speed = 1; 2089898b2970SStas Sergeev changed.duplex = 1; 2090898b2970SStas Sergeev fixed_phy_update_state(phy, &status, &changed); 2091898b2970SStas Sergeev return 0; 2092898b2970SStas Sergeev } 2093898b2970SStas Sergeev 2094c5aff182SThomas Petazzoni /* NAPI handler 2095c5aff182SThomas Petazzoni * Bits 0 - 7 of the causeRxTx register indicate that are transmitted 2096c5aff182SThomas Petazzoni * packets on the corresponding TXQ (Bit 0 is for TX queue 1). 2097c5aff182SThomas Petazzoni * Bits 8 -15 of the cause Rx Tx register indicate that are received 2098c5aff182SThomas Petazzoni * packets on the corresponding RXQ (Bit 8 is for RX queue 0). 2099c5aff182SThomas Petazzoni * Each CPU has its own causeRxTx register 2100c5aff182SThomas Petazzoni */ 2101c5aff182SThomas Petazzoni static int mvneta_poll(struct napi_struct *napi, int budget) 2102c5aff182SThomas Petazzoni { 2103c5aff182SThomas Petazzoni int rx_done = 0; 2104c5aff182SThomas Petazzoni u32 cause_rx_tx; 2105c5aff182SThomas Petazzoni unsigned long flags; 2106c5aff182SThomas Petazzoni struct mvneta_port *pp = netdev_priv(napi->dev); 2107c5aff182SThomas Petazzoni 2108c5aff182SThomas Petazzoni if (!netif_running(pp->dev)) { 2109c5aff182SThomas Petazzoni napi_complete(napi); 2110c5aff182SThomas Petazzoni return rx_done; 2111c5aff182SThomas Petazzoni } 2112c5aff182SThomas Petazzoni 2113c5aff182SThomas Petazzoni /* Read cause register */ 2114898b2970SStas Sergeev cause_rx_tx = mvreg_read(pp, MVNETA_INTR_NEW_CAUSE); 2115898b2970SStas Sergeev if (cause_rx_tx & MVNETA_MISCINTR_INTR_MASK) { 2116898b2970SStas Sergeev u32 cause_misc = mvreg_read(pp, MVNETA_INTR_MISC_CAUSE); 2117898b2970SStas Sergeev 2118898b2970SStas Sergeev mvreg_write(pp, MVNETA_INTR_MISC_CAUSE, 0); 2119898b2970SStas Sergeev if (pp->use_inband_status && (cause_misc & 2120898b2970SStas Sergeev (MVNETA_CAUSE_PHY_STATUS_CHANGE | 2121898b2970SStas Sergeev MVNETA_CAUSE_LINK_CHANGE | 2122898b2970SStas Sergeev MVNETA_CAUSE_PSC_SYNC_CHANGE))) { 2123898b2970SStas Sergeev mvneta_fixed_link_update(pp, pp->phy_dev); 2124898b2970SStas Sergeev } 2125898b2970SStas Sergeev } 212671f6d1b3Swilly tarreau 212771f6d1b3Swilly tarreau /* Release Tx descriptors */ 212871f6d1b3Swilly tarreau if (cause_rx_tx & MVNETA_TX_INTR_MASK_ALL) { 21290713a86aSArnaud Ebalard mvneta_tx_done_gbe(pp, (cause_rx_tx & MVNETA_TX_INTR_MASK_ALL)); 213071f6d1b3Swilly tarreau cause_rx_tx &= ~MVNETA_TX_INTR_MASK_ALL; 213171f6d1b3Swilly tarreau } 2132c5aff182SThomas Petazzoni 21336a20c175SThomas Petazzoni /* For the case where the last mvneta_poll did not process all 2134c5aff182SThomas Petazzoni * RX packets 2135c5aff182SThomas Petazzoni */ 2136c5aff182SThomas Petazzoni cause_rx_tx |= pp->cause_rx_tx; 2137c5aff182SThomas Petazzoni if (rxq_number > 1) { 213871f6d1b3Swilly tarreau while ((cause_rx_tx & MVNETA_RX_INTR_MASK_ALL) && (budget > 0)) { 2139c5aff182SThomas Petazzoni int count; 2140c5aff182SThomas Petazzoni struct mvneta_rx_queue *rxq; 2141c5aff182SThomas Petazzoni /* get rx queue number from cause_rx_tx */ 2142c5aff182SThomas Petazzoni rxq = mvneta_rx_policy(pp, cause_rx_tx); 2143c5aff182SThomas Petazzoni if (!rxq) 2144c5aff182SThomas Petazzoni break; 2145c5aff182SThomas Petazzoni 2146c5aff182SThomas Petazzoni /* process the packet in that rx queue */ 2147c5aff182SThomas Petazzoni count = mvneta_rx(pp, budget, rxq); 2148c5aff182SThomas Petazzoni rx_done += count; 2149c5aff182SThomas Petazzoni budget -= count; 2150c5aff182SThomas Petazzoni if (budget > 0) { 21516a20c175SThomas Petazzoni /* set off the rx bit of the 21526a20c175SThomas Petazzoni * corresponding bit in the cause rx 21536a20c175SThomas Petazzoni * tx register, so that next iteration 21546a20c175SThomas Petazzoni * will find the next rx queue where 21556a20c175SThomas Petazzoni * packets are received on 21566a20c175SThomas Petazzoni */ 2157c5aff182SThomas Petazzoni cause_rx_tx &= ~((1 << rxq->id) << 8); 2158c5aff182SThomas Petazzoni } 2159c5aff182SThomas Petazzoni } 2160c5aff182SThomas Petazzoni } else { 2161c5aff182SThomas Petazzoni rx_done = mvneta_rx(pp, budget, &pp->rxqs[rxq_def]); 2162c5aff182SThomas Petazzoni budget -= rx_done; 2163c5aff182SThomas Petazzoni } 2164c5aff182SThomas Petazzoni 2165c5aff182SThomas Petazzoni if (budget > 0) { 2166c5aff182SThomas Petazzoni cause_rx_tx = 0; 2167c5aff182SThomas Petazzoni napi_complete(napi); 2168c5aff182SThomas Petazzoni local_irq_save(flags); 2169c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_INTR_NEW_MASK, 2170898b2970SStas Sergeev MVNETA_RX_INTR_MASK(rxq_number) | 2171898b2970SStas Sergeev MVNETA_TX_INTR_MASK(txq_number) | 2172898b2970SStas Sergeev MVNETA_MISCINTR_INTR_MASK); 2173c5aff182SThomas Petazzoni local_irq_restore(flags); 2174c5aff182SThomas Petazzoni } 2175c5aff182SThomas Petazzoni 2176c5aff182SThomas Petazzoni pp->cause_rx_tx = cause_rx_tx; 2177c5aff182SThomas Petazzoni return rx_done; 2178c5aff182SThomas Petazzoni } 2179c5aff182SThomas Petazzoni 2180c5aff182SThomas Petazzoni /* Handle rxq fill: allocates rxq skbs; called when initializing a port */ 2181c5aff182SThomas Petazzoni static int mvneta_rxq_fill(struct mvneta_port *pp, struct mvneta_rx_queue *rxq, 2182c5aff182SThomas Petazzoni int num) 2183c5aff182SThomas Petazzoni { 2184c5aff182SThomas Petazzoni int i; 2185c5aff182SThomas Petazzoni 2186c5aff182SThomas Petazzoni for (i = 0; i < num; i++) { 2187a1a65ab1Swilly tarreau memset(rxq->descs + i, 0, sizeof(struct mvneta_rx_desc)); 2188a1a65ab1Swilly tarreau if (mvneta_rx_refill(pp, rxq->descs + i) != 0) { 2189a1a65ab1Swilly tarreau netdev_err(pp->dev, "%s:rxq %d, %d of %d buffs filled\n", 2190c5aff182SThomas Petazzoni __func__, rxq->id, i, num); 2191c5aff182SThomas Petazzoni break; 2192c5aff182SThomas Petazzoni } 2193c5aff182SThomas Petazzoni } 2194c5aff182SThomas Petazzoni 2195c5aff182SThomas Petazzoni /* Add this number of RX descriptors as non occupied (ready to 21966a20c175SThomas Petazzoni * get packets) 21976a20c175SThomas Petazzoni */ 2198c5aff182SThomas Petazzoni mvneta_rxq_non_occup_desc_add(pp, rxq, i); 2199c5aff182SThomas Petazzoni 2200c5aff182SThomas Petazzoni return i; 2201c5aff182SThomas Petazzoni } 2202c5aff182SThomas Petazzoni 2203c5aff182SThomas Petazzoni /* Free all packets pending transmit from all TXQs and reset TX port */ 2204c5aff182SThomas Petazzoni static void mvneta_tx_reset(struct mvneta_port *pp) 2205c5aff182SThomas Petazzoni { 2206c5aff182SThomas Petazzoni int queue; 2207c5aff182SThomas Petazzoni 22089672850bSEzequiel Garcia /* free the skb's in the tx ring */ 2209c5aff182SThomas Petazzoni for (queue = 0; queue < txq_number; queue++) 2210c5aff182SThomas Petazzoni mvneta_txq_done_force(pp, &pp->txqs[queue]); 2211c5aff182SThomas Petazzoni 2212c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_PORT_TX_RESET, MVNETA_PORT_TX_DMA_RESET); 2213c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_PORT_TX_RESET, 0); 2214c5aff182SThomas Petazzoni } 2215c5aff182SThomas Petazzoni 2216c5aff182SThomas Petazzoni static void mvneta_rx_reset(struct mvneta_port *pp) 2217c5aff182SThomas Petazzoni { 2218c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_PORT_RX_RESET, MVNETA_PORT_RX_DMA_RESET); 2219c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_PORT_RX_RESET, 0); 2220c5aff182SThomas Petazzoni } 2221c5aff182SThomas Petazzoni 2222c5aff182SThomas Petazzoni /* Rx/Tx queue initialization/cleanup methods */ 2223c5aff182SThomas Petazzoni 2224c5aff182SThomas Petazzoni /* Create a specified RX queue */ 2225c5aff182SThomas Petazzoni static int mvneta_rxq_init(struct mvneta_port *pp, 2226c5aff182SThomas Petazzoni struct mvneta_rx_queue *rxq) 2227c5aff182SThomas Petazzoni 2228c5aff182SThomas Petazzoni { 2229c5aff182SThomas Petazzoni rxq->size = pp->rx_ring_size; 2230c5aff182SThomas Petazzoni 2231c5aff182SThomas Petazzoni /* Allocate memory for RX descriptors */ 2232c5aff182SThomas Petazzoni rxq->descs = dma_alloc_coherent(pp->dev->dev.parent, 2233c5aff182SThomas Petazzoni rxq->size * MVNETA_DESC_ALIGNED_SIZE, 2234c5aff182SThomas Petazzoni &rxq->descs_phys, GFP_KERNEL); 2235d0320f75SJoe Perches if (rxq->descs == NULL) 2236c5aff182SThomas Petazzoni return -ENOMEM; 2237c5aff182SThomas Petazzoni 2238c5aff182SThomas Petazzoni BUG_ON(rxq->descs != 2239c5aff182SThomas Petazzoni PTR_ALIGN(rxq->descs, MVNETA_CPU_D_CACHE_LINE_SIZE)); 2240c5aff182SThomas Petazzoni 2241c5aff182SThomas Petazzoni rxq->last_desc = rxq->size - 1; 2242c5aff182SThomas Petazzoni 2243c5aff182SThomas Petazzoni /* Set Rx descriptors queue starting address */ 2244c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_RXQ_BASE_ADDR_REG(rxq->id), rxq->descs_phys); 2245c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_RXQ_SIZE_REG(rxq->id), rxq->size); 2246c5aff182SThomas Petazzoni 2247c5aff182SThomas Petazzoni /* Set Offset */ 2248c5aff182SThomas Petazzoni mvneta_rxq_offset_set(pp, rxq, NET_SKB_PAD); 2249c5aff182SThomas Petazzoni 2250c5aff182SThomas Petazzoni /* Set coalescing pkts and time */ 2251c5aff182SThomas Petazzoni mvneta_rx_pkts_coal_set(pp, rxq, rxq->pkts_coal); 2252c5aff182SThomas Petazzoni mvneta_rx_time_coal_set(pp, rxq, rxq->time_coal); 2253c5aff182SThomas Petazzoni 2254c5aff182SThomas Petazzoni /* Fill RXQ with buffers from RX pool */ 2255c5aff182SThomas Petazzoni mvneta_rxq_buf_size_set(pp, rxq, MVNETA_RX_BUF_SIZE(pp->pkt_size)); 2256c5aff182SThomas Petazzoni mvneta_rxq_bm_disable(pp, rxq); 2257c5aff182SThomas Petazzoni mvneta_rxq_fill(pp, rxq, rxq->size); 2258c5aff182SThomas Petazzoni 2259c5aff182SThomas Petazzoni return 0; 2260c5aff182SThomas Petazzoni } 2261c5aff182SThomas Petazzoni 2262c5aff182SThomas Petazzoni /* Cleanup Rx queue */ 2263c5aff182SThomas Petazzoni static void mvneta_rxq_deinit(struct mvneta_port *pp, 2264c5aff182SThomas Petazzoni struct mvneta_rx_queue *rxq) 2265c5aff182SThomas Petazzoni { 2266c5aff182SThomas Petazzoni mvneta_rxq_drop_pkts(pp, rxq); 2267c5aff182SThomas Petazzoni 2268c5aff182SThomas Petazzoni if (rxq->descs) 2269c5aff182SThomas Petazzoni dma_free_coherent(pp->dev->dev.parent, 2270c5aff182SThomas Petazzoni rxq->size * MVNETA_DESC_ALIGNED_SIZE, 2271c5aff182SThomas Petazzoni rxq->descs, 2272c5aff182SThomas Petazzoni rxq->descs_phys); 2273c5aff182SThomas Petazzoni 2274c5aff182SThomas Petazzoni rxq->descs = NULL; 2275c5aff182SThomas Petazzoni rxq->last_desc = 0; 2276c5aff182SThomas Petazzoni rxq->next_desc_to_proc = 0; 2277c5aff182SThomas Petazzoni rxq->descs_phys = 0; 2278c5aff182SThomas Petazzoni } 2279c5aff182SThomas Petazzoni 2280c5aff182SThomas Petazzoni /* Create and initialize a tx queue */ 2281c5aff182SThomas Petazzoni static int mvneta_txq_init(struct mvneta_port *pp, 2282c5aff182SThomas Petazzoni struct mvneta_tx_queue *txq) 2283c5aff182SThomas Petazzoni { 2284c5aff182SThomas Petazzoni txq->size = pp->tx_ring_size; 2285c5aff182SThomas Petazzoni 22868eef5f97SEzequiel Garcia /* A queue must always have room for at least one skb. 22878eef5f97SEzequiel Garcia * Therefore, stop the queue when the free entries reaches 22888eef5f97SEzequiel Garcia * the maximum number of descriptors per skb. 22898eef5f97SEzequiel Garcia */ 22908eef5f97SEzequiel Garcia txq->tx_stop_threshold = txq->size - MVNETA_MAX_SKB_DESCS; 22918eef5f97SEzequiel Garcia txq->tx_wake_threshold = txq->tx_stop_threshold / 2; 22928eef5f97SEzequiel Garcia 22938eef5f97SEzequiel Garcia 2294c5aff182SThomas Petazzoni /* Allocate memory for TX descriptors */ 2295c5aff182SThomas Petazzoni txq->descs = dma_alloc_coherent(pp->dev->dev.parent, 2296c5aff182SThomas Petazzoni txq->size * MVNETA_DESC_ALIGNED_SIZE, 2297c5aff182SThomas Petazzoni &txq->descs_phys, GFP_KERNEL); 2298d0320f75SJoe Perches if (txq->descs == NULL) 2299c5aff182SThomas Petazzoni return -ENOMEM; 2300c5aff182SThomas Petazzoni 2301c5aff182SThomas Petazzoni /* Make sure descriptor address is cache line size aligned */ 2302c5aff182SThomas Petazzoni BUG_ON(txq->descs != 2303c5aff182SThomas Petazzoni PTR_ALIGN(txq->descs, MVNETA_CPU_D_CACHE_LINE_SIZE)); 2304c5aff182SThomas Petazzoni 2305c5aff182SThomas Petazzoni txq->last_desc = txq->size - 1; 2306c5aff182SThomas Petazzoni 2307c5aff182SThomas Petazzoni /* Set maximum bandwidth for enabled TXQs */ 2308c5aff182SThomas Petazzoni mvreg_write(pp, MVETH_TXQ_TOKEN_CFG_REG(txq->id), 0x03ffffff); 2309c5aff182SThomas Petazzoni mvreg_write(pp, MVETH_TXQ_TOKEN_COUNT_REG(txq->id), 0x3fffffff); 2310c5aff182SThomas Petazzoni 2311c5aff182SThomas Petazzoni /* Set Tx descriptors queue starting address */ 2312c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_TXQ_BASE_ADDR_REG(txq->id), txq->descs_phys); 2313c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_TXQ_SIZE_REG(txq->id), txq->size); 2314c5aff182SThomas Petazzoni 2315c5aff182SThomas Petazzoni txq->tx_skb = kmalloc(txq->size * sizeof(*txq->tx_skb), GFP_KERNEL); 2316c5aff182SThomas Petazzoni if (txq->tx_skb == NULL) { 2317c5aff182SThomas Petazzoni dma_free_coherent(pp->dev->dev.parent, 2318c5aff182SThomas Petazzoni txq->size * MVNETA_DESC_ALIGNED_SIZE, 2319c5aff182SThomas Petazzoni txq->descs, txq->descs_phys); 2320c5aff182SThomas Petazzoni return -ENOMEM; 2321c5aff182SThomas Petazzoni } 23222adb719dSEzequiel Garcia 23232adb719dSEzequiel Garcia /* Allocate DMA buffers for TSO MAC/IP/TCP headers */ 23242adb719dSEzequiel Garcia txq->tso_hdrs = dma_alloc_coherent(pp->dev->dev.parent, 23252adb719dSEzequiel Garcia txq->size * TSO_HEADER_SIZE, 23262adb719dSEzequiel Garcia &txq->tso_hdrs_phys, GFP_KERNEL); 23272adb719dSEzequiel Garcia if (txq->tso_hdrs == NULL) { 23282adb719dSEzequiel Garcia kfree(txq->tx_skb); 23292adb719dSEzequiel Garcia dma_free_coherent(pp->dev->dev.parent, 23302adb719dSEzequiel Garcia txq->size * MVNETA_DESC_ALIGNED_SIZE, 23312adb719dSEzequiel Garcia txq->descs, txq->descs_phys); 23322adb719dSEzequiel Garcia return -ENOMEM; 23332adb719dSEzequiel Garcia } 2334c5aff182SThomas Petazzoni mvneta_tx_done_pkts_coal_set(pp, txq, txq->done_pkts_coal); 2335c5aff182SThomas Petazzoni 2336c5aff182SThomas Petazzoni return 0; 2337c5aff182SThomas Petazzoni } 2338c5aff182SThomas Petazzoni 2339c5aff182SThomas Petazzoni /* Free allocated resources when mvneta_txq_init() fails to allocate memory*/ 2340c5aff182SThomas Petazzoni static void mvneta_txq_deinit(struct mvneta_port *pp, 2341c5aff182SThomas Petazzoni struct mvneta_tx_queue *txq) 2342c5aff182SThomas Petazzoni { 2343c5aff182SThomas Petazzoni kfree(txq->tx_skb); 2344c5aff182SThomas Petazzoni 23452adb719dSEzequiel Garcia if (txq->tso_hdrs) 23462adb719dSEzequiel Garcia dma_free_coherent(pp->dev->dev.parent, 23472adb719dSEzequiel Garcia txq->size * TSO_HEADER_SIZE, 23482adb719dSEzequiel Garcia txq->tso_hdrs, txq->tso_hdrs_phys); 2349c5aff182SThomas Petazzoni if (txq->descs) 2350c5aff182SThomas Petazzoni dma_free_coherent(pp->dev->dev.parent, 2351c5aff182SThomas Petazzoni txq->size * MVNETA_DESC_ALIGNED_SIZE, 2352c5aff182SThomas Petazzoni txq->descs, txq->descs_phys); 2353c5aff182SThomas Petazzoni 2354c5aff182SThomas Petazzoni txq->descs = NULL; 2355c5aff182SThomas Petazzoni txq->last_desc = 0; 2356c5aff182SThomas Petazzoni txq->next_desc_to_proc = 0; 2357c5aff182SThomas Petazzoni txq->descs_phys = 0; 2358c5aff182SThomas Petazzoni 2359c5aff182SThomas Petazzoni /* Set minimum bandwidth for disabled TXQs */ 2360c5aff182SThomas Petazzoni mvreg_write(pp, MVETH_TXQ_TOKEN_CFG_REG(txq->id), 0); 2361c5aff182SThomas Petazzoni mvreg_write(pp, MVETH_TXQ_TOKEN_COUNT_REG(txq->id), 0); 2362c5aff182SThomas Petazzoni 2363c5aff182SThomas Petazzoni /* Set Tx descriptors queue starting address and size */ 2364c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_TXQ_BASE_ADDR_REG(txq->id), 0); 2365c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_TXQ_SIZE_REG(txq->id), 0); 2366c5aff182SThomas Petazzoni } 2367c5aff182SThomas Petazzoni 2368c5aff182SThomas Petazzoni /* Cleanup all Tx queues */ 2369c5aff182SThomas Petazzoni static void mvneta_cleanup_txqs(struct mvneta_port *pp) 2370c5aff182SThomas Petazzoni { 2371c5aff182SThomas Petazzoni int queue; 2372c5aff182SThomas Petazzoni 2373c5aff182SThomas Petazzoni for (queue = 0; queue < txq_number; queue++) 2374c5aff182SThomas Petazzoni mvneta_txq_deinit(pp, &pp->txqs[queue]); 2375c5aff182SThomas Petazzoni } 2376c5aff182SThomas Petazzoni 2377c5aff182SThomas Petazzoni /* Cleanup all Rx queues */ 2378c5aff182SThomas Petazzoni static void mvneta_cleanup_rxqs(struct mvneta_port *pp) 2379c5aff182SThomas Petazzoni { 2380c5aff182SThomas Petazzoni int queue; 2381c5aff182SThomas Petazzoni 2382c5aff182SThomas Petazzoni for (queue = 0; queue < rxq_number; queue++) 2383c5aff182SThomas Petazzoni mvneta_rxq_deinit(pp, &pp->rxqs[queue]); 2384c5aff182SThomas Petazzoni } 2385c5aff182SThomas Petazzoni 2386c5aff182SThomas Petazzoni 2387c5aff182SThomas Petazzoni /* Init all Rx queues */ 2388c5aff182SThomas Petazzoni static int mvneta_setup_rxqs(struct mvneta_port *pp) 2389c5aff182SThomas Petazzoni { 2390c5aff182SThomas Petazzoni int queue; 2391c5aff182SThomas Petazzoni 2392c5aff182SThomas Petazzoni for (queue = 0; queue < rxq_number; queue++) { 2393c5aff182SThomas Petazzoni int err = mvneta_rxq_init(pp, &pp->rxqs[queue]); 2394c5aff182SThomas Petazzoni if (err) { 2395c5aff182SThomas Petazzoni netdev_err(pp->dev, "%s: can't create rxq=%d\n", 2396c5aff182SThomas Petazzoni __func__, queue); 2397c5aff182SThomas Petazzoni mvneta_cleanup_rxqs(pp); 2398c5aff182SThomas Petazzoni return err; 2399c5aff182SThomas Petazzoni } 2400c5aff182SThomas Petazzoni } 2401c5aff182SThomas Petazzoni 2402c5aff182SThomas Petazzoni return 0; 2403c5aff182SThomas Petazzoni } 2404c5aff182SThomas Petazzoni 2405c5aff182SThomas Petazzoni /* Init all tx queues */ 2406c5aff182SThomas Petazzoni static int mvneta_setup_txqs(struct mvneta_port *pp) 2407c5aff182SThomas Petazzoni { 2408c5aff182SThomas Petazzoni int queue; 2409c5aff182SThomas Petazzoni 2410c5aff182SThomas Petazzoni for (queue = 0; queue < txq_number; queue++) { 2411c5aff182SThomas Petazzoni int err = mvneta_txq_init(pp, &pp->txqs[queue]); 2412c5aff182SThomas Petazzoni if (err) { 2413c5aff182SThomas Petazzoni netdev_err(pp->dev, "%s: can't create txq=%d\n", 2414c5aff182SThomas Petazzoni __func__, queue); 2415c5aff182SThomas Petazzoni mvneta_cleanup_txqs(pp); 2416c5aff182SThomas Petazzoni return err; 2417c5aff182SThomas Petazzoni } 2418c5aff182SThomas Petazzoni } 2419c5aff182SThomas Petazzoni 2420c5aff182SThomas Petazzoni return 0; 2421c5aff182SThomas Petazzoni } 2422c5aff182SThomas Petazzoni 2423c5aff182SThomas Petazzoni static void mvneta_start_dev(struct mvneta_port *pp) 2424c5aff182SThomas Petazzoni { 2425c5aff182SThomas Petazzoni mvneta_max_rx_size_set(pp, pp->pkt_size); 2426c5aff182SThomas Petazzoni mvneta_txq_max_tx_size_set(pp, pp->pkt_size); 2427c5aff182SThomas Petazzoni 2428c5aff182SThomas Petazzoni /* start the Rx/Tx activity */ 2429c5aff182SThomas Petazzoni mvneta_port_enable(pp); 2430c5aff182SThomas Petazzoni 2431c5aff182SThomas Petazzoni /* Enable polling on the port */ 2432c5aff182SThomas Petazzoni napi_enable(&pp->napi); 2433c5aff182SThomas Petazzoni 2434c5aff182SThomas Petazzoni /* Unmask interrupts */ 2435c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_INTR_NEW_MASK, 2436898b2970SStas Sergeev MVNETA_RX_INTR_MASK(rxq_number) | 2437898b2970SStas Sergeev MVNETA_TX_INTR_MASK(txq_number) | 2438898b2970SStas Sergeev MVNETA_MISCINTR_INTR_MASK); 2439898b2970SStas Sergeev mvreg_write(pp, MVNETA_INTR_MISC_MASK, 2440898b2970SStas Sergeev MVNETA_CAUSE_PHY_STATUS_CHANGE | 2441898b2970SStas Sergeev MVNETA_CAUSE_LINK_CHANGE | 2442898b2970SStas Sergeev MVNETA_CAUSE_PSC_SYNC_CHANGE); 2443c5aff182SThomas Petazzoni 2444c5aff182SThomas Petazzoni phy_start(pp->phy_dev); 2445c5aff182SThomas Petazzoni netif_tx_start_all_queues(pp->dev); 2446c5aff182SThomas Petazzoni } 2447c5aff182SThomas Petazzoni 2448c5aff182SThomas Petazzoni static void mvneta_stop_dev(struct mvneta_port *pp) 2449c5aff182SThomas Petazzoni { 2450c5aff182SThomas Petazzoni phy_stop(pp->phy_dev); 2451c5aff182SThomas Petazzoni 2452c5aff182SThomas Petazzoni napi_disable(&pp->napi); 2453c5aff182SThomas Petazzoni 2454c5aff182SThomas Petazzoni netif_carrier_off(pp->dev); 2455c5aff182SThomas Petazzoni 2456c5aff182SThomas Petazzoni mvneta_port_down(pp); 2457c5aff182SThomas Petazzoni netif_tx_stop_all_queues(pp->dev); 2458c5aff182SThomas Petazzoni 2459c5aff182SThomas Petazzoni /* Stop the port activity */ 2460c5aff182SThomas Petazzoni mvneta_port_disable(pp); 2461c5aff182SThomas Petazzoni 2462c5aff182SThomas Petazzoni /* Clear all ethernet port interrupts */ 2463c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_INTR_MISC_CAUSE, 0); 2464c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_INTR_OLD_CAUSE, 0); 2465c5aff182SThomas Petazzoni 2466c5aff182SThomas Petazzoni /* Mask all ethernet port interrupts */ 2467c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_INTR_NEW_MASK, 0); 2468c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_INTR_OLD_MASK, 0); 2469c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_INTR_MISC_MASK, 0); 2470c5aff182SThomas Petazzoni 2471c5aff182SThomas Petazzoni mvneta_tx_reset(pp); 2472c5aff182SThomas Petazzoni mvneta_rx_reset(pp); 2473c5aff182SThomas Petazzoni } 2474c5aff182SThomas Petazzoni 2475c5aff182SThomas Petazzoni /* Return positive if MTU is valid */ 2476c5aff182SThomas Petazzoni static int mvneta_check_mtu_valid(struct net_device *dev, int mtu) 2477c5aff182SThomas Petazzoni { 2478c5aff182SThomas Petazzoni if (mtu < 68) { 2479c5aff182SThomas Petazzoni netdev_err(dev, "cannot change mtu to less than 68\n"); 2480c5aff182SThomas Petazzoni return -EINVAL; 2481c5aff182SThomas Petazzoni } 2482c5aff182SThomas Petazzoni 2483c5aff182SThomas Petazzoni /* 9676 == 9700 - 20 and rounding to 8 */ 2484c5aff182SThomas Petazzoni if (mtu > 9676) { 2485c5aff182SThomas Petazzoni netdev_info(dev, "Illegal MTU value %d, round to 9676\n", mtu); 2486c5aff182SThomas Petazzoni mtu = 9676; 2487c5aff182SThomas Petazzoni } 2488c5aff182SThomas Petazzoni 2489c5aff182SThomas Petazzoni if (!IS_ALIGNED(MVNETA_RX_PKT_SIZE(mtu), 8)) { 2490c5aff182SThomas Petazzoni netdev_info(dev, "Illegal MTU value %d, rounding to %d\n", 2491c5aff182SThomas Petazzoni mtu, ALIGN(MVNETA_RX_PKT_SIZE(mtu), 8)); 2492c5aff182SThomas Petazzoni mtu = ALIGN(MVNETA_RX_PKT_SIZE(mtu), 8); 2493c5aff182SThomas Petazzoni } 2494c5aff182SThomas Petazzoni 2495c5aff182SThomas Petazzoni return mtu; 2496c5aff182SThomas Petazzoni } 2497c5aff182SThomas Petazzoni 2498c5aff182SThomas Petazzoni /* Change the device mtu */ 2499c5aff182SThomas Petazzoni static int mvneta_change_mtu(struct net_device *dev, int mtu) 2500c5aff182SThomas Petazzoni { 2501c5aff182SThomas Petazzoni struct mvneta_port *pp = netdev_priv(dev); 2502c5aff182SThomas Petazzoni int ret; 2503c5aff182SThomas Petazzoni 2504c5aff182SThomas Petazzoni mtu = mvneta_check_mtu_valid(dev, mtu); 2505c5aff182SThomas Petazzoni if (mtu < 0) 2506c5aff182SThomas Petazzoni return -EINVAL; 2507c5aff182SThomas Petazzoni 2508c5aff182SThomas Petazzoni dev->mtu = mtu; 2509c5aff182SThomas Petazzoni 2510b65657fcSSimon Guinot if (!netif_running(dev)) { 2511b65657fcSSimon Guinot netdev_update_features(dev); 2512c5aff182SThomas Petazzoni return 0; 2513b65657fcSSimon Guinot } 2514c5aff182SThomas Petazzoni 25156a20c175SThomas Petazzoni /* The interface is running, so we have to force a 2516a92dbd96SEzequiel Garcia * reallocation of the queues 2517c5aff182SThomas Petazzoni */ 2518c5aff182SThomas Petazzoni mvneta_stop_dev(pp); 2519c5aff182SThomas Petazzoni 2520c5aff182SThomas Petazzoni mvneta_cleanup_txqs(pp); 2521c5aff182SThomas Petazzoni mvneta_cleanup_rxqs(pp); 2522c5aff182SThomas Petazzoni 2523a92dbd96SEzequiel Garcia pp->pkt_size = MVNETA_RX_PKT_SIZE(dev->mtu); 25248ec2cd48Swilly tarreau pp->frag_size = SKB_DATA_ALIGN(MVNETA_RX_BUF_SIZE(pp->pkt_size)) + 25258ec2cd48Swilly tarreau SKB_DATA_ALIGN(sizeof(struct skb_shared_info)); 2526c5aff182SThomas Petazzoni 2527c5aff182SThomas Petazzoni ret = mvneta_setup_rxqs(pp); 2528c5aff182SThomas Petazzoni if (ret) { 2529a92dbd96SEzequiel Garcia netdev_err(dev, "unable to setup rxqs after MTU change\n"); 2530c5aff182SThomas Petazzoni return ret; 2531c5aff182SThomas Petazzoni } 2532c5aff182SThomas Petazzoni 2533a92dbd96SEzequiel Garcia ret = mvneta_setup_txqs(pp); 2534a92dbd96SEzequiel Garcia if (ret) { 2535a92dbd96SEzequiel Garcia netdev_err(dev, "unable to setup txqs after MTU change\n"); 2536a92dbd96SEzequiel Garcia return ret; 2537a92dbd96SEzequiel Garcia } 2538c5aff182SThomas Petazzoni 2539c5aff182SThomas Petazzoni mvneta_start_dev(pp); 2540c5aff182SThomas Petazzoni mvneta_port_up(pp); 2541c5aff182SThomas Petazzoni 2542b65657fcSSimon Guinot netdev_update_features(dev); 2543b65657fcSSimon Guinot 2544c5aff182SThomas Petazzoni return 0; 2545c5aff182SThomas Petazzoni } 2546c5aff182SThomas Petazzoni 2547b65657fcSSimon Guinot static netdev_features_t mvneta_fix_features(struct net_device *dev, 2548b65657fcSSimon Guinot netdev_features_t features) 2549b65657fcSSimon Guinot { 2550b65657fcSSimon Guinot struct mvneta_port *pp = netdev_priv(dev); 2551b65657fcSSimon Guinot 2552b65657fcSSimon Guinot if (pp->tx_csum_limit && dev->mtu > pp->tx_csum_limit) { 2553b65657fcSSimon Guinot features &= ~(NETIF_F_IP_CSUM | NETIF_F_TSO); 2554b65657fcSSimon Guinot netdev_info(dev, 2555b65657fcSSimon Guinot "Disable IP checksum for MTU greater than %dB\n", 2556b65657fcSSimon Guinot pp->tx_csum_limit); 2557b65657fcSSimon Guinot } 2558b65657fcSSimon Guinot 2559b65657fcSSimon Guinot return features; 2560b65657fcSSimon Guinot } 2561b65657fcSSimon Guinot 25628cc3e439SThomas Petazzoni /* Get mac address */ 25638cc3e439SThomas Petazzoni static void mvneta_get_mac_addr(struct mvneta_port *pp, unsigned char *addr) 25648cc3e439SThomas Petazzoni { 25658cc3e439SThomas Petazzoni u32 mac_addr_l, mac_addr_h; 25668cc3e439SThomas Petazzoni 25678cc3e439SThomas Petazzoni mac_addr_l = mvreg_read(pp, MVNETA_MAC_ADDR_LOW); 25688cc3e439SThomas Petazzoni mac_addr_h = mvreg_read(pp, MVNETA_MAC_ADDR_HIGH); 25698cc3e439SThomas Petazzoni addr[0] = (mac_addr_h >> 24) & 0xFF; 25708cc3e439SThomas Petazzoni addr[1] = (mac_addr_h >> 16) & 0xFF; 25718cc3e439SThomas Petazzoni addr[2] = (mac_addr_h >> 8) & 0xFF; 25728cc3e439SThomas Petazzoni addr[3] = mac_addr_h & 0xFF; 25738cc3e439SThomas Petazzoni addr[4] = (mac_addr_l >> 8) & 0xFF; 25748cc3e439SThomas Petazzoni addr[5] = mac_addr_l & 0xFF; 25758cc3e439SThomas Petazzoni } 25768cc3e439SThomas Petazzoni 2577c5aff182SThomas Petazzoni /* Handle setting mac address */ 2578c5aff182SThomas Petazzoni static int mvneta_set_mac_addr(struct net_device *dev, void *addr) 2579c5aff182SThomas Petazzoni { 2580c5aff182SThomas Petazzoni struct mvneta_port *pp = netdev_priv(dev); 2581e68de360SEzequiel Garcia struct sockaddr *sockaddr = addr; 2582e68de360SEzequiel Garcia int ret; 2583c5aff182SThomas Petazzoni 2584e68de360SEzequiel Garcia ret = eth_prepare_mac_addr_change(dev, addr); 2585e68de360SEzequiel Garcia if (ret < 0) 2586e68de360SEzequiel Garcia return ret; 2587c5aff182SThomas Petazzoni /* Remove previous address table entry */ 2588c5aff182SThomas Petazzoni mvneta_mac_addr_set(pp, dev->dev_addr, -1); 2589c5aff182SThomas Petazzoni 2590c5aff182SThomas Petazzoni /* Set new addr in hw */ 2591e68de360SEzequiel Garcia mvneta_mac_addr_set(pp, sockaddr->sa_data, rxq_def); 2592c5aff182SThomas Petazzoni 2593e68de360SEzequiel Garcia eth_commit_mac_addr_change(dev, addr); 2594c5aff182SThomas Petazzoni return 0; 2595c5aff182SThomas Petazzoni } 2596c5aff182SThomas Petazzoni 2597c5aff182SThomas Petazzoni static void mvneta_adjust_link(struct net_device *ndev) 2598c5aff182SThomas Petazzoni { 2599c5aff182SThomas Petazzoni struct mvneta_port *pp = netdev_priv(ndev); 2600c5aff182SThomas Petazzoni struct phy_device *phydev = pp->phy_dev; 2601c5aff182SThomas Petazzoni int status_change = 0; 2602c5aff182SThomas Petazzoni 2603c5aff182SThomas Petazzoni if (phydev->link) { 2604c5aff182SThomas Petazzoni if ((pp->speed != phydev->speed) || 2605c5aff182SThomas Petazzoni (pp->duplex != phydev->duplex)) { 2606c5aff182SThomas Petazzoni u32 val; 2607c5aff182SThomas Petazzoni 2608c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG); 2609c5aff182SThomas Petazzoni val &= ~(MVNETA_GMAC_CONFIG_MII_SPEED | 2610c5aff182SThomas Petazzoni MVNETA_GMAC_CONFIG_GMII_SPEED | 2611898b2970SStas Sergeev MVNETA_GMAC_CONFIG_FULL_DUPLEX); 2612c5aff182SThomas Petazzoni 2613c5aff182SThomas Petazzoni if (phydev->duplex) 2614c5aff182SThomas Petazzoni val |= MVNETA_GMAC_CONFIG_FULL_DUPLEX; 2615c5aff182SThomas Petazzoni 2616c5aff182SThomas Petazzoni if (phydev->speed == SPEED_1000) 2617c5aff182SThomas Petazzoni val |= MVNETA_GMAC_CONFIG_GMII_SPEED; 26184d12bc63SThomas Petazzoni else if (phydev->speed == SPEED_100) 2619c5aff182SThomas Petazzoni val |= MVNETA_GMAC_CONFIG_MII_SPEED; 2620c5aff182SThomas Petazzoni 2621c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val); 2622c5aff182SThomas Petazzoni 2623c5aff182SThomas Petazzoni pp->duplex = phydev->duplex; 2624c5aff182SThomas Petazzoni pp->speed = phydev->speed; 2625c5aff182SThomas Petazzoni } 2626c5aff182SThomas Petazzoni } 2627c5aff182SThomas Petazzoni 2628c5aff182SThomas Petazzoni if (phydev->link != pp->link) { 2629c5aff182SThomas Petazzoni if (!phydev->link) { 2630c5aff182SThomas Petazzoni pp->duplex = -1; 2631c5aff182SThomas Petazzoni pp->speed = 0; 2632c5aff182SThomas Petazzoni } 2633c5aff182SThomas Petazzoni 2634c5aff182SThomas Petazzoni pp->link = phydev->link; 2635c5aff182SThomas Petazzoni status_change = 1; 2636c5aff182SThomas Petazzoni } 2637c5aff182SThomas Petazzoni 2638c5aff182SThomas Petazzoni if (status_change) { 2639c5aff182SThomas Petazzoni if (phydev->link) { 2640898b2970SStas Sergeev if (!pp->use_inband_status) { 2641898b2970SStas Sergeev u32 val = mvreg_read(pp, 2642898b2970SStas Sergeev MVNETA_GMAC_AUTONEG_CONFIG); 2643898b2970SStas Sergeev val &= ~MVNETA_GMAC_FORCE_LINK_DOWN; 2644898b2970SStas Sergeev val |= MVNETA_GMAC_FORCE_LINK_PASS; 2645898b2970SStas Sergeev mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, 2646898b2970SStas Sergeev val); 2647898b2970SStas Sergeev } 2648c5aff182SThomas Petazzoni mvneta_port_up(pp); 2649c5aff182SThomas Petazzoni } else { 2650898b2970SStas Sergeev if (!pp->use_inband_status) { 2651898b2970SStas Sergeev u32 val = mvreg_read(pp, 2652898b2970SStas Sergeev MVNETA_GMAC_AUTONEG_CONFIG); 2653898b2970SStas Sergeev val &= ~MVNETA_GMAC_FORCE_LINK_PASS; 2654898b2970SStas Sergeev val |= MVNETA_GMAC_FORCE_LINK_DOWN; 2655898b2970SStas Sergeev mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, 2656898b2970SStas Sergeev val); 2657898b2970SStas Sergeev } 2658c5aff182SThomas Petazzoni mvneta_port_down(pp); 2659c5aff182SThomas Petazzoni } 26600089b745SEzequiel Garcia phy_print_status(phydev); 2661c5aff182SThomas Petazzoni } 2662c5aff182SThomas Petazzoni } 2663c5aff182SThomas Petazzoni 2664c5aff182SThomas Petazzoni static int mvneta_mdio_probe(struct mvneta_port *pp) 2665c5aff182SThomas Petazzoni { 2666c5aff182SThomas Petazzoni struct phy_device *phy_dev; 2667c5aff182SThomas Petazzoni 2668c5aff182SThomas Petazzoni phy_dev = of_phy_connect(pp->dev, pp->phy_node, mvneta_adjust_link, 0, 2669c5aff182SThomas Petazzoni pp->phy_interface); 2670c5aff182SThomas Petazzoni if (!phy_dev) { 2671c5aff182SThomas Petazzoni netdev_err(pp->dev, "could not find the PHY\n"); 2672c5aff182SThomas Petazzoni return -ENODEV; 2673c5aff182SThomas Petazzoni } 2674c5aff182SThomas Petazzoni 2675c5aff182SThomas Petazzoni phy_dev->supported &= PHY_GBIT_FEATURES; 2676c5aff182SThomas Petazzoni phy_dev->advertising = phy_dev->supported; 2677c5aff182SThomas Petazzoni 2678c5aff182SThomas Petazzoni pp->phy_dev = phy_dev; 2679c5aff182SThomas Petazzoni pp->link = 0; 2680c5aff182SThomas Petazzoni pp->duplex = 0; 2681c5aff182SThomas Petazzoni pp->speed = 0; 2682c5aff182SThomas Petazzoni 2683c5aff182SThomas Petazzoni return 0; 2684c5aff182SThomas Petazzoni } 2685c5aff182SThomas Petazzoni 2686c5aff182SThomas Petazzoni static void mvneta_mdio_remove(struct mvneta_port *pp) 2687c5aff182SThomas Petazzoni { 2688c5aff182SThomas Petazzoni phy_disconnect(pp->phy_dev); 2689c5aff182SThomas Petazzoni pp->phy_dev = NULL; 2690c5aff182SThomas Petazzoni } 2691c5aff182SThomas Petazzoni 2692c5aff182SThomas Petazzoni static int mvneta_open(struct net_device *dev) 2693c5aff182SThomas Petazzoni { 2694c5aff182SThomas Petazzoni struct mvneta_port *pp = netdev_priv(dev); 2695c5aff182SThomas Petazzoni int ret; 2696c5aff182SThomas Petazzoni 2697c5aff182SThomas Petazzoni pp->pkt_size = MVNETA_RX_PKT_SIZE(pp->dev->mtu); 26988ec2cd48Swilly tarreau pp->frag_size = SKB_DATA_ALIGN(MVNETA_RX_BUF_SIZE(pp->pkt_size)) + 26998ec2cd48Swilly tarreau SKB_DATA_ALIGN(sizeof(struct skb_shared_info)); 2700c5aff182SThomas Petazzoni 2701c5aff182SThomas Petazzoni ret = mvneta_setup_rxqs(pp); 2702c5aff182SThomas Petazzoni if (ret) 2703c5aff182SThomas Petazzoni return ret; 2704c5aff182SThomas Petazzoni 2705c5aff182SThomas Petazzoni ret = mvneta_setup_txqs(pp); 2706c5aff182SThomas Petazzoni if (ret) 2707c5aff182SThomas Petazzoni goto err_cleanup_rxqs; 2708c5aff182SThomas Petazzoni 2709c5aff182SThomas Petazzoni /* Connect to port interrupt line */ 2710c5aff182SThomas Petazzoni ret = request_irq(pp->dev->irq, mvneta_isr, 0, 2711c5aff182SThomas Petazzoni MVNETA_DRIVER_NAME, pp); 2712c5aff182SThomas Petazzoni if (ret) { 2713c5aff182SThomas Petazzoni netdev_err(pp->dev, "cannot request irq %d\n", pp->dev->irq); 2714c5aff182SThomas Petazzoni goto err_cleanup_txqs; 2715c5aff182SThomas Petazzoni } 2716c5aff182SThomas Petazzoni 2717c5aff182SThomas Petazzoni /* In default link is down */ 2718c5aff182SThomas Petazzoni netif_carrier_off(pp->dev); 2719c5aff182SThomas Petazzoni 2720c5aff182SThomas Petazzoni ret = mvneta_mdio_probe(pp); 2721c5aff182SThomas Petazzoni if (ret < 0) { 2722c5aff182SThomas Petazzoni netdev_err(dev, "cannot probe MDIO bus\n"); 2723c5aff182SThomas Petazzoni goto err_free_irq; 2724c5aff182SThomas Petazzoni } 2725c5aff182SThomas Petazzoni 2726c5aff182SThomas Petazzoni mvneta_start_dev(pp); 2727c5aff182SThomas Petazzoni 2728c5aff182SThomas Petazzoni return 0; 2729c5aff182SThomas Petazzoni 2730c5aff182SThomas Petazzoni err_free_irq: 2731c5aff182SThomas Petazzoni free_irq(pp->dev->irq, pp); 2732c5aff182SThomas Petazzoni err_cleanup_txqs: 2733c5aff182SThomas Petazzoni mvneta_cleanup_txqs(pp); 2734c5aff182SThomas Petazzoni err_cleanup_rxqs: 2735c5aff182SThomas Petazzoni mvneta_cleanup_rxqs(pp); 2736c5aff182SThomas Petazzoni return ret; 2737c5aff182SThomas Petazzoni } 2738c5aff182SThomas Petazzoni 2739c5aff182SThomas Petazzoni /* Stop the port, free port interrupt line */ 2740c5aff182SThomas Petazzoni static int mvneta_stop(struct net_device *dev) 2741c5aff182SThomas Petazzoni { 2742c5aff182SThomas Petazzoni struct mvneta_port *pp = netdev_priv(dev); 2743c5aff182SThomas Petazzoni 2744c5aff182SThomas Petazzoni mvneta_stop_dev(pp); 2745c5aff182SThomas Petazzoni mvneta_mdio_remove(pp); 2746c5aff182SThomas Petazzoni free_irq(dev->irq, pp); 2747c5aff182SThomas Petazzoni mvneta_cleanup_rxqs(pp); 2748c5aff182SThomas Petazzoni mvneta_cleanup_txqs(pp); 2749c5aff182SThomas Petazzoni 2750c5aff182SThomas Petazzoni return 0; 2751c5aff182SThomas Petazzoni } 2752c5aff182SThomas Petazzoni 275315f59456SThomas Petazzoni static int mvneta_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) 275415f59456SThomas Petazzoni { 275515f59456SThomas Petazzoni struct mvneta_port *pp = netdev_priv(dev); 275615f59456SThomas Petazzoni 275715f59456SThomas Petazzoni if (!pp->phy_dev) 275815f59456SThomas Petazzoni return -ENOTSUPP; 275915f59456SThomas Petazzoni 2760ecf7b361SStas Sergeev return phy_mii_ioctl(pp->phy_dev, ifr, cmd); 276115f59456SThomas Petazzoni } 276215f59456SThomas Petazzoni 2763c5aff182SThomas Petazzoni /* Ethtool methods */ 2764c5aff182SThomas Petazzoni 2765c5aff182SThomas Petazzoni /* Get settings (phy address, speed) for ethtools */ 2766c5aff182SThomas Petazzoni int mvneta_ethtool_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) 2767c5aff182SThomas Petazzoni { 2768c5aff182SThomas Petazzoni struct mvneta_port *pp = netdev_priv(dev); 2769c5aff182SThomas Petazzoni 2770c5aff182SThomas Petazzoni if (!pp->phy_dev) 2771c5aff182SThomas Petazzoni return -ENODEV; 2772c5aff182SThomas Petazzoni 2773c5aff182SThomas Petazzoni return phy_ethtool_gset(pp->phy_dev, cmd); 2774c5aff182SThomas Petazzoni } 2775c5aff182SThomas Petazzoni 2776c5aff182SThomas Petazzoni /* Set settings (phy address, speed) for ethtools */ 2777c5aff182SThomas Petazzoni int mvneta_ethtool_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) 2778c5aff182SThomas Petazzoni { 2779c5aff182SThomas Petazzoni struct mvneta_port *pp = netdev_priv(dev); 2780c5aff182SThomas Petazzoni 2781c5aff182SThomas Petazzoni if (!pp->phy_dev) 2782c5aff182SThomas Petazzoni return -ENODEV; 2783c5aff182SThomas Petazzoni 2784c5aff182SThomas Petazzoni return phy_ethtool_sset(pp->phy_dev, cmd); 2785c5aff182SThomas Petazzoni } 2786c5aff182SThomas Petazzoni 2787c5aff182SThomas Petazzoni /* Set interrupt coalescing for ethtools */ 2788c5aff182SThomas Petazzoni static int mvneta_ethtool_set_coalesce(struct net_device *dev, 2789c5aff182SThomas Petazzoni struct ethtool_coalesce *c) 2790c5aff182SThomas Petazzoni { 2791c5aff182SThomas Petazzoni struct mvneta_port *pp = netdev_priv(dev); 2792c5aff182SThomas Petazzoni int queue; 2793c5aff182SThomas Petazzoni 2794c5aff182SThomas Petazzoni for (queue = 0; queue < rxq_number; queue++) { 2795c5aff182SThomas Petazzoni struct mvneta_rx_queue *rxq = &pp->rxqs[queue]; 2796c5aff182SThomas Petazzoni rxq->time_coal = c->rx_coalesce_usecs; 2797c5aff182SThomas Petazzoni rxq->pkts_coal = c->rx_max_coalesced_frames; 2798c5aff182SThomas Petazzoni mvneta_rx_pkts_coal_set(pp, rxq, rxq->pkts_coal); 2799c5aff182SThomas Petazzoni mvneta_rx_time_coal_set(pp, rxq, rxq->time_coal); 2800c5aff182SThomas Petazzoni } 2801c5aff182SThomas Petazzoni 2802c5aff182SThomas Petazzoni for (queue = 0; queue < txq_number; queue++) { 2803c5aff182SThomas Petazzoni struct mvneta_tx_queue *txq = &pp->txqs[queue]; 2804c5aff182SThomas Petazzoni txq->done_pkts_coal = c->tx_max_coalesced_frames; 2805c5aff182SThomas Petazzoni mvneta_tx_done_pkts_coal_set(pp, txq, txq->done_pkts_coal); 2806c5aff182SThomas Petazzoni } 2807c5aff182SThomas Petazzoni 2808c5aff182SThomas Petazzoni return 0; 2809c5aff182SThomas Petazzoni } 2810c5aff182SThomas Petazzoni 2811c5aff182SThomas Petazzoni /* get coalescing for ethtools */ 2812c5aff182SThomas Petazzoni static int mvneta_ethtool_get_coalesce(struct net_device *dev, 2813c5aff182SThomas Petazzoni struct ethtool_coalesce *c) 2814c5aff182SThomas Petazzoni { 2815c5aff182SThomas Petazzoni struct mvneta_port *pp = netdev_priv(dev); 2816c5aff182SThomas Petazzoni 2817c5aff182SThomas Petazzoni c->rx_coalesce_usecs = pp->rxqs[0].time_coal; 2818c5aff182SThomas Petazzoni c->rx_max_coalesced_frames = pp->rxqs[0].pkts_coal; 2819c5aff182SThomas Petazzoni 2820c5aff182SThomas Petazzoni c->tx_max_coalesced_frames = pp->txqs[0].done_pkts_coal; 2821c5aff182SThomas Petazzoni return 0; 2822c5aff182SThomas Petazzoni } 2823c5aff182SThomas Petazzoni 2824c5aff182SThomas Petazzoni 2825c5aff182SThomas Petazzoni static void mvneta_ethtool_get_drvinfo(struct net_device *dev, 2826c5aff182SThomas Petazzoni struct ethtool_drvinfo *drvinfo) 2827c5aff182SThomas Petazzoni { 2828c5aff182SThomas Petazzoni strlcpy(drvinfo->driver, MVNETA_DRIVER_NAME, 2829c5aff182SThomas Petazzoni sizeof(drvinfo->driver)); 2830c5aff182SThomas Petazzoni strlcpy(drvinfo->version, MVNETA_DRIVER_VERSION, 2831c5aff182SThomas Petazzoni sizeof(drvinfo->version)); 2832c5aff182SThomas Petazzoni strlcpy(drvinfo->bus_info, dev_name(&dev->dev), 2833c5aff182SThomas Petazzoni sizeof(drvinfo->bus_info)); 2834c5aff182SThomas Petazzoni } 2835c5aff182SThomas Petazzoni 2836c5aff182SThomas Petazzoni 2837c5aff182SThomas Petazzoni static void mvneta_ethtool_get_ringparam(struct net_device *netdev, 2838c5aff182SThomas Petazzoni struct ethtool_ringparam *ring) 2839c5aff182SThomas Petazzoni { 2840c5aff182SThomas Petazzoni struct mvneta_port *pp = netdev_priv(netdev); 2841c5aff182SThomas Petazzoni 2842c5aff182SThomas Petazzoni ring->rx_max_pending = MVNETA_MAX_RXD; 2843c5aff182SThomas Petazzoni ring->tx_max_pending = MVNETA_MAX_TXD; 2844c5aff182SThomas Petazzoni ring->rx_pending = pp->rx_ring_size; 2845c5aff182SThomas Petazzoni ring->tx_pending = pp->tx_ring_size; 2846c5aff182SThomas Petazzoni } 2847c5aff182SThomas Petazzoni 2848c5aff182SThomas Petazzoni static int mvneta_ethtool_set_ringparam(struct net_device *dev, 2849c5aff182SThomas Petazzoni struct ethtool_ringparam *ring) 2850c5aff182SThomas Petazzoni { 2851c5aff182SThomas Petazzoni struct mvneta_port *pp = netdev_priv(dev); 2852c5aff182SThomas Petazzoni 2853c5aff182SThomas Petazzoni if ((ring->rx_pending == 0) || (ring->tx_pending == 0)) 2854c5aff182SThomas Petazzoni return -EINVAL; 2855c5aff182SThomas Petazzoni pp->rx_ring_size = ring->rx_pending < MVNETA_MAX_RXD ? 2856c5aff182SThomas Petazzoni ring->rx_pending : MVNETA_MAX_RXD; 28578eef5f97SEzequiel Garcia 28588eef5f97SEzequiel Garcia pp->tx_ring_size = clamp_t(u16, ring->tx_pending, 28598eef5f97SEzequiel Garcia MVNETA_MAX_SKB_DESCS * 2, MVNETA_MAX_TXD); 28608eef5f97SEzequiel Garcia if (pp->tx_ring_size != ring->tx_pending) 28618eef5f97SEzequiel Garcia netdev_warn(dev, "TX queue size set to %u (requested %u)\n", 28628eef5f97SEzequiel Garcia pp->tx_ring_size, ring->tx_pending); 2863c5aff182SThomas Petazzoni 2864c5aff182SThomas Petazzoni if (netif_running(dev)) { 2865c5aff182SThomas Petazzoni mvneta_stop(dev); 2866c5aff182SThomas Petazzoni if (mvneta_open(dev)) { 2867c5aff182SThomas Petazzoni netdev_err(dev, 2868c5aff182SThomas Petazzoni "error on opening device after ring param change\n"); 2869c5aff182SThomas Petazzoni return -ENOMEM; 2870c5aff182SThomas Petazzoni } 2871c5aff182SThomas Petazzoni } 2872c5aff182SThomas Petazzoni 2873c5aff182SThomas Petazzoni return 0; 2874c5aff182SThomas Petazzoni } 2875c5aff182SThomas Petazzoni 2876c5aff182SThomas Petazzoni static const struct net_device_ops mvneta_netdev_ops = { 2877c5aff182SThomas Petazzoni .ndo_open = mvneta_open, 2878c5aff182SThomas Petazzoni .ndo_stop = mvneta_stop, 2879c5aff182SThomas Petazzoni .ndo_start_xmit = mvneta_tx, 2880c5aff182SThomas Petazzoni .ndo_set_rx_mode = mvneta_set_rx_mode, 2881c5aff182SThomas Petazzoni .ndo_set_mac_address = mvneta_set_mac_addr, 2882c5aff182SThomas Petazzoni .ndo_change_mtu = mvneta_change_mtu, 2883b65657fcSSimon Guinot .ndo_fix_features = mvneta_fix_features, 2884c5aff182SThomas Petazzoni .ndo_get_stats64 = mvneta_get_stats64, 288515f59456SThomas Petazzoni .ndo_do_ioctl = mvneta_ioctl, 2886c5aff182SThomas Petazzoni }; 2887c5aff182SThomas Petazzoni 2888c5aff182SThomas Petazzoni const struct ethtool_ops mvneta_eth_tool_ops = { 2889c5aff182SThomas Petazzoni .get_link = ethtool_op_get_link, 2890c5aff182SThomas Petazzoni .get_settings = mvneta_ethtool_get_settings, 2891c5aff182SThomas Petazzoni .set_settings = mvneta_ethtool_set_settings, 2892c5aff182SThomas Petazzoni .set_coalesce = mvneta_ethtool_set_coalesce, 2893c5aff182SThomas Petazzoni .get_coalesce = mvneta_ethtool_get_coalesce, 2894c5aff182SThomas Petazzoni .get_drvinfo = mvneta_ethtool_get_drvinfo, 2895c5aff182SThomas Petazzoni .get_ringparam = mvneta_ethtool_get_ringparam, 2896c5aff182SThomas Petazzoni .set_ringparam = mvneta_ethtool_set_ringparam, 2897c5aff182SThomas Petazzoni }; 2898c5aff182SThomas Petazzoni 2899c5aff182SThomas Petazzoni /* Initialize hw */ 29009672850bSEzequiel Garcia static int mvneta_init(struct device *dev, struct mvneta_port *pp) 2901c5aff182SThomas Petazzoni { 2902c5aff182SThomas Petazzoni int queue; 2903c5aff182SThomas Petazzoni 2904c5aff182SThomas Petazzoni /* Disable port */ 2905c5aff182SThomas Petazzoni mvneta_port_disable(pp); 2906c5aff182SThomas Petazzoni 2907c5aff182SThomas Petazzoni /* Set port default values */ 2908c5aff182SThomas Petazzoni mvneta_defaults_set(pp); 2909c5aff182SThomas Petazzoni 29109672850bSEzequiel Garcia pp->txqs = devm_kcalloc(dev, txq_number, sizeof(struct mvneta_tx_queue), 2911c5aff182SThomas Petazzoni GFP_KERNEL); 2912c5aff182SThomas Petazzoni if (!pp->txqs) 2913c5aff182SThomas Petazzoni return -ENOMEM; 2914c5aff182SThomas Petazzoni 2915c5aff182SThomas Petazzoni /* Initialize TX descriptor rings */ 2916c5aff182SThomas Petazzoni for (queue = 0; queue < txq_number; queue++) { 2917c5aff182SThomas Petazzoni struct mvneta_tx_queue *txq = &pp->txqs[queue]; 2918c5aff182SThomas Petazzoni txq->id = queue; 2919c5aff182SThomas Petazzoni txq->size = pp->tx_ring_size; 2920c5aff182SThomas Petazzoni txq->done_pkts_coal = MVNETA_TXDONE_COAL_PKTS; 2921c5aff182SThomas Petazzoni } 2922c5aff182SThomas Petazzoni 29239672850bSEzequiel Garcia pp->rxqs = devm_kcalloc(dev, rxq_number, sizeof(struct mvneta_rx_queue), 2924c5aff182SThomas Petazzoni GFP_KERNEL); 29259672850bSEzequiel Garcia if (!pp->rxqs) 2926c5aff182SThomas Petazzoni return -ENOMEM; 2927c5aff182SThomas Petazzoni 2928c5aff182SThomas Petazzoni /* Create Rx descriptor rings */ 2929c5aff182SThomas Petazzoni for (queue = 0; queue < rxq_number; queue++) { 2930c5aff182SThomas Petazzoni struct mvneta_rx_queue *rxq = &pp->rxqs[queue]; 2931c5aff182SThomas Petazzoni rxq->id = queue; 2932c5aff182SThomas Petazzoni rxq->size = pp->rx_ring_size; 2933c5aff182SThomas Petazzoni rxq->pkts_coal = MVNETA_RX_COAL_PKTS; 2934c5aff182SThomas Petazzoni rxq->time_coal = MVNETA_RX_COAL_USEC; 2935c5aff182SThomas Petazzoni } 2936c5aff182SThomas Petazzoni 2937c5aff182SThomas Petazzoni return 0; 2938c5aff182SThomas Petazzoni } 2939c5aff182SThomas Petazzoni 2940c5aff182SThomas Petazzoni /* platform glue : initialize decoding windows */ 294103ce758eSGreg KH static void mvneta_conf_mbus_windows(struct mvneta_port *pp, 2942c5aff182SThomas Petazzoni const struct mbus_dram_target_info *dram) 2943c5aff182SThomas Petazzoni { 2944c5aff182SThomas Petazzoni u32 win_enable; 2945c5aff182SThomas Petazzoni u32 win_protect; 2946c5aff182SThomas Petazzoni int i; 2947c5aff182SThomas Petazzoni 2948c5aff182SThomas Petazzoni for (i = 0; i < 6; i++) { 2949c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_WIN_BASE(i), 0); 2950c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_WIN_SIZE(i), 0); 2951c5aff182SThomas Petazzoni 2952c5aff182SThomas Petazzoni if (i < 4) 2953c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_WIN_REMAP(i), 0); 2954c5aff182SThomas Petazzoni } 2955c5aff182SThomas Petazzoni 2956c5aff182SThomas Petazzoni win_enable = 0x3f; 2957c5aff182SThomas Petazzoni win_protect = 0; 2958c5aff182SThomas Petazzoni 2959c5aff182SThomas Petazzoni for (i = 0; i < dram->num_cs; i++) { 2960c5aff182SThomas Petazzoni const struct mbus_dram_window *cs = dram->cs + i; 2961c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_WIN_BASE(i), (cs->base & 0xffff0000) | 2962c5aff182SThomas Petazzoni (cs->mbus_attr << 8) | dram->mbus_dram_target_id); 2963c5aff182SThomas Petazzoni 2964c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_WIN_SIZE(i), 2965c5aff182SThomas Petazzoni (cs->size - 1) & 0xffff0000); 2966c5aff182SThomas Petazzoni 2967c5aff182SThomas Petazzoni win_enable &= ~(1 << i); 2968c5aff182SThomas Petazzoni win_protect |= 3 << (2 * i); 2969c5aff182SThomas Petazzoni } 2970c5aff182SThomas Petazzoni 2971c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_BASE_ADDR_ENABLE, win_enable); 2972c5aff182SThomas Petazzoni } 2973c5aff182SThomas Petazzoni 2974c5aff182SThomas Petazzoni /* Power up the port */ 29753f1dd4bcSThomas Petazzoni static int mvneta_port_power_up(struct mvneta_port *pp, int phy_mode) 2976c5aff182SThomas Petazzoni { 29773f1dd4bcSThomas Petazzoni u32 ctrl; 2978c5aff182SThomas Petazzoni 2979c5aff182SThomas Petazzoni /* MAC Cause register should be cleared */ 2980c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_UNIT_INTR_CAUSE, 0); 2981c5aff182SThomas Petazzoni 29823f1dd4bcSThomas Petazzoni ctrl = mvreg_read(pp, MVNETA_GMAC_CTRL_2); 2983c5aff182SThomas Petazzoni 29843f1dd4bcSThomas Petazzoni /* Even though it might look weird, when we're configured in 29853f1dd4bcSThomas Petazzoni * SGMII or QSGMII mode, the RGMII bit needs to be set. 29863f1dd4bcSThomas Petazzoni */ 29873f1dd4bcSThomas Petazzoni switch(phy_mode) { 29883f1dd4bcSThomas Petazzoni case PHY_INTERFACE_MODE_QSGMII: 29893f1dd4bcSThomas Petazzoni mvreg_write(pp, MVNETA_SERDES_CFG, MVNETA_QSGMII_SERDES_PROTO); 29903f1dd4bcSThomas Petazzoni ctrl |= MVNETA_GMAC2_PCS_ENABLE | MVNETA_GMAC2_PORT_RGMII; 29913f1dd4bcSThomas Petazzoni break; 29923f1dd4bcSThomas Petazzoni case PHY_INTERFACE_MODE_SGMII: 29933f1dd4bcSThomas Petazzoni mvreg_write(pp, MVNETA_SERDES_CFG, MVNETA_SGMII_SERDES_PROTO); 29943f1dd4bcSThomas Petazzoni ctrl |= MVNETA_GMAC2_PCS_ENABLE | MVNETA_GMAC2_PORT_RGMII; 29953f1dd4bcSThomas Petazzoni break; 29963f1dd4bcSThomas Petazzoni case PHY_INTERFACE_MODE_RGMII: 29973f1dd4bcSThomas Petazzoni case PHY_INTERFACE_MODE_RGMII_ID: 29983f1dd4bcSThomas Petazzoni ctrl |= MVNETA_GMAC2_PORT_RGMII; 29993f1dd4bcSThomas Petazzoni break; 30003f1dd4bcSThomas Petazzoni default: 30013f1dd4bcSThomas Petazzoni return -EINVAL; 30023f1dd4bcSThomas Petazzoni } 3003c5aff182SThomas Petazzoni 3004898b2970SStas Sergeev if (pp->use_inband_status) 3005898b2970SStas Sergeev ctrl |= MVNETA_GMAC2_INBAND_AN_ENABLE; 3006898b2970SStas Sergeev 3007c5aff182SThomas Petazzoni /* Cancel Port Reset */ 30083f1dd4bcSThomas Petazzoni ctrl &= ~MVNETA_GMAC2_PORT_RESET; 30093f1dd4bcSThomas Petazzoni mvreg_write(pp, MVNETA_GMAC_CTRL_2, ctrl); 3010c5aff182SThomas Petazzoni 3011c5aff182SThomas Petazzoni while ((mvreg_read(pp, MVNETA_GMAC_CTRL_2) & 3012c5aff182SThomas Petazzoni MVNETA_GMAC2_PORT_RESET) != 0) 3013c5aff182SThomas Petazzoni continue; 30143f1dd4bcSThomas Petazzoni 30153f1dd4bcSThomas Petazzoni return 0; 3016c5aff182SThomas Petazzoni } 3017c5aff182SThomas Petazzoni 3018c5aff182SThomas Petazzoni /* Device initialization routine */ 301903ce758eSGreg KH static int mvneta_probe(struct platform_device *pdev) 3020c5aff182SThomas Petazzoni { 3021c5aff182SThomas Petazzoni const struct mbus_dram_target_info *dram_target_info; 3022c3f0dd38SThomas Petazzoni struct resource *res; 3023c5aff182SThomas Petazzoni struct device_node *dn = pdev->dev.of_node; 3024c5aff182SThomas Petazzoni struct device_node *phy_node; 3025c5aff182SThomas Petazzoni struct mvneta_port *pp; 3026c5aff182SThomas Petazzoni struct net_device *dev; 30278cc3e439SThomas Petazzoni const char *dt_mac_addr; 30288cc3e439SThomas Petazzoni char hw_mac_addr[ETH_ALEN]; 30298cc3e439SThomas Petazzoni const char *mac_from; 3030c5aff182SThomas Petazzoni int phy_mode; 3031898b2970SStas Sergeev int fixed_phy = 0; 3032c5aff182SThomas Petazzoni int err; 3033c5aff182SThomas Petazzoni 30346a20c175SThomas Petazzoni /* Our multiqueue support is not complete, so for now, only 3035c5aff182SThomas Petazzoni * allow the usage of the first RX queue 3036c5aff182SThomas Petazzoni */ 3037c5aff182SThomas Petazzoni if (rxq_def != 0) { 3038c5aff182SThomas Petazzoni dev_err(&pdev->dev, "Invalid rxq_def argument: %d\n", rxq_def); 3039c5aff182SThomas Petazzoni return -EINVAL; 3040c5aff182SThomas Petazzoni } 3041c5aff182SThomas Petazzoni 3042ee40a116SWilly Tarreau dev = alloc_etherdev_mqs(sizeof(struct mvneta_port), txq_number, rxq_number); 3043c5aff182SThomas Petazzoni if (!dev) 3044c5aff182SThomas Petazzoni return -ENOMEM; 3045c5aff182SThomas Petazzoni 3046c5aff182SThomas Petazzoni dev->irq = irq_of_parse_and_map(dn, 0); 3047c5aff182SThomas Petazzoni if (dev->irq == 0) { 3048c5aff182SThomas Petazzoni err = -EINVAL; 3049c5aff182SThomas Petazzoni goto err_free_netdev; 3050c5aff182SThomas Petazzoni } 3051c5aff182SThomas Petazzoni 3052c5aff182SThomas Petazzoni phy_node = of_parse_phandle(dn, "phy", 0); 3053c5aff182SThomas Petazzoni if (!phy_node) { 305483895bedSThomas Petazzoni if (!of_phy_is_fixed_link(dn)) { 305583895bedSThomas Petazzoni dev_err(&pdev->dev, "no PHY specified\n"); 3056c5aff182SThomas Petazzoni err = -ENODEV; 3057c5aff182SThomas Petazzoni goto err_free_irq; 3058c5aff182SThomas Petazzoni } 3059c5aff182SThomas Petazzoni 306083895bedSThomas Petazzoni err = of_phy_register_fixed_link(dn); 306183895bedSThomas Petazzoni if (err < 0) { 306283895bedSThomas Petazzoni dev_err(&pdev->dev, "cannot register fixed PHY\n"); 306383895bedSThomas Petazzoni goto err_free_irq; 306483895bedSThomas Petazzoni } 3065898b2970SStas Sergeev fixed_phy = 1; 306683895bedSThomas Petazzoni 306783895bedSThomas Petazzoni /* In the case of a fixed PHY, the DT node associated 306883895bedSThomas Petazzoni * to the PHY is the Ethernet MAC DT node. 306983895bedSThomas Petazzoni */ 3070c891c24cSUwe Kleine-König phy_node = of_node_get(dn); 307183895bedSThomas Petazzoni } 307283895bedSThomas Petazzoni 3073c5aff182SThomas Petazzoni phy_mode = of_get_phy_mode(dn); 3074c5aff182SThomas Petazzoni if (phy_mode < 0) { 3075c5aff182SThomas Petazzoni dev_err(&pdev->dev, "incorrect phy-mode\n"); 3076c5aff182SThomas Petazzoni err = -EINVAL; 3077c891c24cSUwe Kleine-König goto err_put_phy_node; 3078c5aff182SThomas Petazzoni } 3079c5aff182SThomas Petazzoni 3080c5aff182SThomas Petazzoni dev->tx_queue_len = MVNETA_MAX_TXD; 3081c5aff182SThomas Petazzoni dev->watchdog_timeo = 5 * HZ; 3082c5aff182SThomas Petazzoni dev->netdev_ops = &mvneta_netdev_ops; 3083c5aff182SThomas Petazzoni 30847ad24ea4SWilfried Klaebe dev->ethtool_ops = &mvneta_eth_tool_ops; 3085c5aff182SThomas Petazzoni 3086c5aff182SThomas Petazzoni pp = netdev_priv(dev); 3087c5aff182SThomas Petazzoni pp->phy_node = phy_node; 3088c5aff182SThomas Petazzoni pp->phy_interface = phy_mode; 3089898b2970SStas Sergeev pp->use_inband_status = (phy_mode == PHY_INTERFACE_MODE_SGMII) && 3090898b2970SStas Sergeev fixed_phy; 3091c5aff182SThomas Petazzoni 3092189dd626SThomas Petazzoni pp->clk = devm_clk_get(&pdev->dev, NULL); 3093189dd626SThomas Petazzoni if (IS_ERR(pp->clk)) { 3094189dd626SThomas Petazzoni err = PTR_ERR(pp->clk); 3095c891c24cSUwe Kleine-König goto err_put_phy_node; 3096189dd626SThomas Petazzoni } 3097189dd626SThomas Petazzoni 3098189dd626SThomas Petazzoni clk_prepare_enable(pp->clk); 3099189dd626SThomas Petazzoni 3100c3f0dd38SThomas Petazzoni res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 3101c3f0dd38SThomas Petazzoni pp->base = devm_ioremap_resource(&pdev->dev, res); 3102c3f0dd38SThomas Petazzoni if (IS_ERR(pp->base)) { 3103c3f0dd38SThomas Petazzoni err = PTR_ERR(pp->base); 31045445eaf3SArnaud Patard \(Rtp\) goto err_clk; 31055445eaf3SArnaud Patard \(Rtp\) } 31065445eaf3SArnaud Patard \(Rtp\) 310774c41b04Swilly tarreau /* Alloc per-cpu stats */ 31081c213bd2SWANG Cong pp->stats = netdev_alloc_pcpu_stats(struct mvneta_pcpu_stats); 310974c41b04Swilly tarreau if (!pp->stats) { 311074c41b04Swilly tarreau err = -ENOMEM; 3111c3f0dd38SThomas Petazzoni goto err_clk; 311274c41b04Swilly tarreau } 311374c41b04Swilly tarreau 31148cc3e439SThomas Petazzoni dt_mac_addr = of_get_mac_address(dn); 31156c7a9a3cSLuka Perkov if (dt_mac_addr) { 31168cc3e439SThomas Petazzoni mac_from = "device tree"; 31178cc3e439SThomas Petazzoni memcpy(dev->dev_addr, dt_mac_addr, ETH_ALEN); 31188cc3e439SThomas Petazzoni } else { 31198cc3e439SThomas Petazzoni mvneta_get_mac_addr(pp, hw_mac_addr); 31208cc3e439SThomas Petazzoni if (is_valid_ether_addr(hw_mac_addr)) { 31218cc3e439SThomas Petazzoni mac_from = "hardware"; 31228cc3e439SThomas Petazzoni memcpy(dev->dev_addr, hw_mac_addr, ETH_ALEN); 31238cc3e439SThomas Petazzoni } else { 31248cc3e439SThomas Petazzoni mac_from = "random"; 31258cc3e439SThomas Petazzoni eth_hw_addr_random(dev); 31268cc3e439SThomas Petazzoni } 31278cc3e439SThomas Petazzoni } 31288cc3e439SThomas Petazzoni 3129b65657fcSSimon Guinot if (of_device_is_compatible(dn, "marvell,armada-370-neta")) 3130b65657fcSSimon Guinot pp->tx_csum_limit = 1600; 3131b65657fcSSimon Guinot 3132c5aff182SThomas Petazzoni pp->tx_ring_size = MVNETA_MAX_TXD; 3133c5aff182SThomas Petazzoni pp->rx_ring_size = MVNETA_MAX_RXD; 3134c5aff182SThomas Petazzoni 3135c5aff182SThomas Petazzoni pp->dev = dev; 3136c5aff182SThomas Petazzoni SET_NETDEV_DEV(dev, &pdev->dev); 3137c5aff182SThomas Petazzoni 31389672850bSEzequiel Garcia err = mvneta_init(&pdev->dev, pp); 31399672850bSEzequiel Garcia if (err < 0) 314074c41b04Swilly tarreau goto err_free_stats; 31413f1dd4bcSThomas Petazzoni 31423f1dd4bcSThomas Petazzoni err = mvneta_port_power_up(pp, phy_mode); 31433f1dd4bcSThomas Petazzoni if (err < 0) { 31443f1dd4bcSThomas Petazzoni dev_err(&pdev->dev, "can't power up port\n"); 31459672850bSEzequiel Garcia goto err_free_stats; 31463f1dd4bcSThomas Petazzoni } 3147c5aff182SThomas Petazzoni 3148c5aff182SThomas Petazzoni dram_target_info = mv_mbus_dram_info(); 3149c5aff182SThomas Petazzoni if (dram_target_info) 3150c5aff182SThomas Petazzoni mvneta_conf_mbus_windows(pp, dram_target_info); 3151c5aff182SThomas Petazzoni 31529fa9379dSEzequiel Garcia netif_napi_add(dev, &pp->napi, mvneta_poll, NAPI_POLL_WEIGHT); 3153c5aff182SThomas Petazzoni 31542adb719dSEzequiel Garcia dev->features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO; 315501ef26caSEzequiel Garcia dev->hw_features |= dev->features; 315601ef26caSEzequiel Garcia dev->vlan_features |= dev->features; 3157b50b72deSwilly tarreau dev->priv_flags |= IFF_UNICAST_FLT; 31588eef5f97SEzequiel Garcia dev->gso_max_segs = MVNETA_MAX_TSO_SEGS; 3159b50b72deSwilly tarreau 3160c5aff182SThomas Petazzoni err = register_netdev(dev); 3161c5aff182SThomas Petazzoni if (err < 0) { 3162c5aff182SThomas Petazzoni dev_err(&pdev->dev, "failed to register\n"); 31639672850bSEzequiel Garcia goto err_free_stats; 3164c5aff182SThomas Petazzoni } 3165c5aff182SThomas Petazzoni 31668cc3e439SThomas Petazzoni netdev_info(dev, "Using %s mac address %pM\n", mac_from, 31678cc3e439SThomas Petazzoni dev->dev_addr); 3168c5aff182SThomas Petazzoni 3169c5aff182SThomas Petazzoni platform_set_drvdata(pdev, pp->dev); 3170c5aff182SThomas Petazzoni 3171898b2970SStas Sergeev if (pp->use_inband_status) { 3172898b2970SStas Sergeev struct phy_device *phy = of_phy_find_device(dn); 3173898b2970SStas Sergeev 3174898b2970SStas Sergeev mvneta_fixed_link_update(pp, phy); 3175898b2970SStas Sergeev } 3176898b2970SStas Sergeev 3177c5aff182SThomas Petazzoni return 0; 3178c5aff182SThomas Petazzoni 317974c41b04Swilly tarreau err_free_stats: 318074c41b04Swilly tarreau free_percpu(pp->stats); 31815445eaf3SArnaud Patard \(Rtp\) err_clk: 31825445eaf3SArnaud Patard \(Rtp\) clk_disable_unprepare(pp->clk); 3183c891c24cSUwe Kleine-König err_put_phy_node: 3184c891c24cSUwe Kleine-König of_node_put(phy_node); 3185c5aff182SThomas Petazzoni err_free_irq: 3186c5aff182SThomas Petazzoni irq_dispose_mapping(dev->irq); 3187c5aff182SThomas Petazzoni err_free_netdev: 3188c5aff182SThomas Petazzoni free_netdev(dev); 3189c5aff182SThomas Petazzoni return err; 3190c5aff182SThomas Petazzoni } 3191c5aff182SThomas Petazzoni 3192c5aff182SThomas Petazzoni /* Device removal routine */ 319303ce758eSGreg KH static int mvneta_remove(struct platform_device *pdev) 3194c5aff182SThomas Petazzoni { 3195c5aff182SThomas Petazzoni struct net_device *dev = platform_get_drvdata(pdev); 3196c5aff182SThomas Petazzoni struct mvneta_port *pp = netdev_priv(dev); 3197c5aff182SThomas Petazzoni 3198c5aff182SThomas Petazzoni unregister_netdev(dev); 3199189dd626SThomas Petazzoni clk_disable_unprepare(pp->clk); 320074c41b04Swilly tarreau free_percpu(pp->stats); 3201c5aff182SThomas Petazzoni irq_dispose_mapping(dev->irq); 3202c891c24cSUwe Kleine-König of_node_put(pp->phy_node); 3203c5aff182SThomas Petazzoni free_netdev(dev); 3204c5aff182SThomas Petazzoni 3205c5aff182SThomas Petazzoni return 0; 3206c5aff182SThomas Petazzoni } 3207c5aff182SThomas Petazzoni 3208c5aff182SThomas Petazzoni static const struct of_device_id mvneta_match[] = { 3209c5aff182SThomas Petazzoni { .compatible = "marvell,armada-370-neta" }, 3210f522a975SSimon Guinot { .compatible = "marvell,armada-xp-neta" }, 3211c5aff182SThomas Petazzoni { } 3212c5aff182SThomas Petazzoni }; 3213c5aff182SThomas Petazzoni MODULE_DEVICE_TABLE(of, mvneta_match); 3214c5aff182SThomas Petazzoni 3215c5aff182SThomas Petazzoni static struct platform_driver mvneta_driver = { 3216c5aff182SThomas Petazzoni .probe = mvneta_probe, 321703ce758eSGreg KH .remove = mvneta_remove, 3218c5aff182SThomas Petazzoni .driver = { 3219c5aff182SThomas Petazzoni .name = MVNETA_DRIVER_NAME, 3220c5aff182SThomas Petazzoni .of_match_table = mvneta_match, 3221c5aff182SThomas Petazzoni }, 3222c5aff182SThomas Petazzoni }; 3223c5aff182SThomas Petazzoni 3224c5aff182SThomas Petazzoni module_platform_driver(mvneta_driver); 3225c5aff182SThomas Petazzoni 3226c5aff182SThomas Petazzoni MODULE_DESCRIPTION("Marvell NETA Ethernet Driver - www.marvell.com"); 3227c5aff182SThomas Petazzoni MODULE_AUTHOR("Rami Rosen <rosenr@marvell.com>, Thomas Petazzoni <thomas.petazzoni@free-electrons.com>"); 3228c5aff182SThomas Petazzoni MODULE_LICENSE("GPL"); 3229c5aff182SThomas Petazzoni 3230c5aff182SThomas Petazzoni module_param(rxq_number, int, S_IRUGO); 3231c5aff182SThomas Petazzoni module_param(txq_number, int, S_IRUGO); 3232c5aff182SThomas Petazzoni 3233c5aff182SThomas Petazzoni module_param(rxq_def, int, S_IRUGO); 3234f19fadfcSwilly tarreau module_param(rx_copybreak, int, S_IRUGO | S_IWUSR); 3235