1c5aff182SThomas Petazzoni /* 2c5aff182SThomas Petazzoni * Driver for Marvell NETA network card for Armada XP and Armada 370 SoCs. 3c5aff182SThomas Petazzoni * 4c5aff182SThomas Petazzoni * Copyright (C) 2012 Marvell 5c5aff182SThomas Petazzoni * 6c5aff182SThomas Petazzoni * Rami Rosen <rosenr@marvell.com> 7c5aff182SThomas Petazzoni * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> 8c5aff182SThomas Petazzoni * 9c5aff182SThomas Petazzoni * This file is licensed under the terms of the GNU General Public 10c5aff182SThomas Petazzoni * License version 2. This program is licensed "as is" without any 11c5aff182SThomas Petazzoni * warranty of any kind, whether express or implied. 12c5aff182SThomas Petazzoni */ 13c5aff182SThomas Petazzoni 140e03f563SJisheng Zhang #include <linux/clk.h> 150e03f563SJisheng Zhang #include <linux/cpu.h> 16c5aff182SThomas Petazzoni #include <linux/etherdevice.h> 170e03f563SJisheng Zhang #include <linux/if_vlan.h> 18c5aff182SThomas Petazzoni #include <linux/inetdevice.h> 190e03f563SJisheng Zhang #include <linux/interrupt.h> 200e03f563SJisheng Zhang #include <linux/io.h> 210e03f563SJisheng Zhang #include <linux/kernel.h> 22c5aff182SThomas Petazzoni #include <linux/mbus.h> 23c5aff182SThomas Petazzoni #include <linux/module.h> 240e03f563SJisheng Zhang #include <linux/netdevice.h> 25c5aff182SThomas Petazzoni #include <linux/of.h> 260e03f563SJisheng Zhang #include <linux/of_address.h> 27c5aff182SThomas Petazzoni #include <linux/of_irq.h> 28c5aff182SThomas Petazzoni #include <linux/of_mdio.h> 29c5aff182SThomas Petazzoni #include <linux/of_net.h> 30a10c1c81SRussell King #include <linux/phy/phy.h> 31c5aff182SThomas Petazzoni #include <linux/phy.h> 32503f9aa9SRussell King #include <linux/phylink.h> 330e03f563SJisheng Zhang #include <linux/platform_device.h> 340e03f563SJisheng Zhang #include <linux/skbuff.h> 35baa11ebcSGregory CLEMENT #include <net/hwbm.h> 36dc35a10fSMarcin Wojtas #include "mvneta_bm.h" 370e03f563SJisheng Zhang #include <net/ip.h> 380e03f563SJisheng Zhang #include <net/ipv6.h> 390e03f563SJisheng Zhang #include <net/tso.h> 40c5aff182SThomas Petazzoni 41c5aff182SThomas Petazzoni /* Registers */ 42c5aff182SThomas Petazzoni #define MVNETA_RXQ_CONFIG_REG(q) (0x1400 + ((q) << 2)) 43e5bdf689SMarcin Wojtas #define MVNETA_RXQ_HW_BUF_ALLOC BIT(0) 44dc35a10fSMarcin Wojtas #define MVNETA_RXQ_SHORT_POOL_ID_SHIFT 4 45dc35a10fSMarcin Wojtas #define MVNETA_RXQ_SHORT_POOL_ID_MASK 0x30 46dc35a10fSMarcin Wojtas #define MVNETA_RXQ_LONG_POOL_ID_SHIFT 6 47dc35a10fSMarcin Wojtas #define MVNETA_RXQ_LONG_POOL_ID_MASK 0xc0 48c5aff182SThomas Petazzoni #define MVNETA_RXQ_PKT_OFFSET_ALL_MASK (0xf << 8) 49c5aff182SThomas Petazzoni #define MVNETA_RXQ_PKT_OFFSET_MASK(offs) ((offs) << 8) 50c5aff182SThomas Petazzoni #define MVNETA_RXQ_THRESHOLD_REG(q) (0x14c0 + ((q) << 2)) 51c5aff182SThomas Petazzoni #define MVNETA_RXQ_NON_OCCUPIED(v) ((v) << 16) 52c5aff182SThomas Petazzoni #define MVNETA_RXQ_BASE_ADDR_REG(q) (0x1480 + ((q) << 2)) 53c5aff182SThomas Petazzoni #define MVNETA_RXQ_SIZE_REG(q) (0x14a0 + ((q) << 2)) 54c5aff182SThomas Petazzoni #define MVNETA_RXQ_BUF_SIZE_SHIFT 19 55c5aff182SThomas Petazzoni #define MVNETA_RXQ_BUF_SIZE_MASK (0x1fff << 19) 56c5aff182SThomas Petazzoni #define MVNETA_RXQ_STATUS_REG(q) (0x14e0 + ((q) << 2)) 57c5aff182SThomas Petazzoni #define MVNETA_RXQ_OCCUPIED_ALL_MASK 0x3fff 58c5aff182SThomas Petazzoni #define MVNETA_RXQ_STATUS_UPDATE_REG(q) (0x1500 + ((q) << 2)) 59c5aff182SThomas Petazzoni #define MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT 16 60c5aff182SThomas Petazzoni #define MVNETA_RXQ_ADD_NON_OCCUPIED_MAX 255 61dc35a10fSMarcin Wojtas #define MVNETA_PORT_POOL_BUFFER_SZ_REG(pool) (0x1700 + ((pool) << 2)) 62dc35a10fSMarcin Wojtas #define MVNETA_PORT_POOL_BUFFER_SZ_SHIFT 3 63dc35a10fSMarcin Wojtas #define MVNETA_PORT_POOL_BUFFER_SZ_MASK 0xfff8 64c5aff182SThomas Petazzoni #define MVNETA_PORT_RX_RESET 0x1cc0 65c5aff182SThomas Petazzoni #define MVNETA_PORT_RX_DMA_RESET BIT(0) 66c5aff182SThomas Petazzoni #define MVNETA_PHY_ADDR 0x2000 67c5aff182SThomas Petazzoni #define MVNETA_PHY_ADDR_MASK 0x1f 68c5aff182SThomas Petazzoni #define MVNETA_MBUS_RETRY 0x2010 69c5aff182SThomas Petazzoni #define MVNETA_UNIT_INTR_CAUSE 0x2080 70c5aff182SThomas Petazzoni #define MVNETA_UNIT_CONTROL 0x20B0 71c5aff182SThomas Petazzoni #define MVNETA_PHY_POLLING_ENABLE BIT(1) 72c5aff182SThomas Petazzoni #define MVNETA_WIN_BASE(w) (0x2200 + ((w) << 3)) 73c5aff182SThomas Petazzoni #define MVNETA_WIN_SIZE(w) (0x2204 + ((w) << 3)) 74c5aff182SThomas Petazzoni #define MVNETA_WIN_REMAP(w) (0x2280 + ((w) << 2)) 75c5aff182SThomas Petazzoni #define MVNETA_BASE_ADDR_ENABLE 0x2290 76db6ba9a5SMarcin Wojtas #define MVNETA_ACCESS_PROTECT_ENABLE 0x2294 77c5aff182SThomas Petazzoni #define MVNETA_PORT_CONFIG 0x2400 78c5aff182SThomas Petazzoni #define MVNETA_UNI_PROMISC_MODE BIT(0) 79c5aff182SThomas Petazzoni #define MVNETA_DEF_RXQ(q) ((q) << 1) 80c5aff182SThomas Petazzoni #define MVNETA_DEF_RXQ_ARP(q) ((q) << 4) 81c5aff182SThomas Petazzoni #define MVNETA_TX_UNSET_ERR_SUM BIT(12) 82c5aff182SThomas Petazzoni #define MVNETA_DEF_RXQ_TCP(q) ((q) << 16) 83c5aff182SThomas Petazzoni #define MVNETA_DEF_RXQ_UDP(q) ((q) << 19) 84c5aff182SThomas Petazzoni #define MVNETA_DEF_RXQ_BPDU(q) ((q) << 22) 85c5aff182SThomas Petazzoni #define MVNETA_RX_CSUM_WITH_PSEUDO_HDR BIT(25) 86c5aff182SThomas Petazzoni #define MVNETA_PORT_CONFIG_DEFL_VALUE(q) (MVNETA_DEF_RXQ(q) | \ 87c5aff182SThomas Petazzoni MVNETA_DEF_RXQ_ARP(q) | \ 88c5aff182SThomas Petazzoni MVNETA_DEF_RXQ_TCP(q) | \ 89c5aff182SThomas Petazzoni MVNETA_DEF_RXQ_UDP(q) | \ 90c5aff182SThomas Petazzoni MVNETA_DEF_RXQ_BPDU(q) | \ 91c5aff182SThomas Petazzoni MVNETA_TX_UNSET_ERR_SUM | \ 92c5aff182SThomas Petazzoni MVNETA_RX_CSUM_WITH_PSEUDO_HDR) 93c5aff182SThomas Petazzoni #define MVNETA_PORT_CONFIG_EXTEND 0x2404 94c5aff182SThomas Petazzoni #define MVNETA_MAC_ADDR_LOW 0x2414 95c5aff182SThomas Petazzoni #define MVNETA_MAC_ADDR_HIGH 0x2418 96c5aff182SThomas Petazzoni #define MVNETA_SDMA_CONFIG 0x241c 97c5aff182SThomas Petazzoni #define MVNETA_SDMA_BRST_SIZE_16 4 98c5aff182SThomas Petazzoni #define MVNETA_RX_BRST_SZ_MASK(burst) ((burst) << 1) 99c5aff182SThomas Petazzoni #define MVNETA_RX_NO_DATA_SWAP BIT(4) 100c5aff182SThomas Petazzoni #define MVNETA_TX_NO_DATA_SWAP BIT(5) 1019ad8fef6SThomas Petazzoni #define MVNETA_DESC_SWAP BIT(6) 102c5aff182SThomas Petazzoni #define MVNETA_TX_BRST_SZ_MASK(burst) ((burst) << 22) 103c5aff182SThomas Petazzoni #define MVNETA_PORT_STATUS 0x2444 104c5aff182SThomas Petazzoni #define MVNETA_TX_IN_PRGRS BIT(1) 105c5aff182SThomas Petazzoni #define MVNETA_TX_FIFO_EMPTY BIT(8) 106c5aff182SThomas Petazzoni #define MVNETA_RX_MIN_FRAME_SIZE 0x247c 1073f1dd4bcSThomas Petazzoni #define MVNETA_SERDES_CFG 0x24A0 1085445eaf3SArnaud Patard \(Rtp\) #define MVNETA_SGMII_SERDES_PROTO 0x0cc7 1093f1dd4bcSThomas Petazzoni #define MVNETA_QSGMII_SERDES_PROTO 0x0667 110c5aff182SThomas Petazzoni #define MVNETA_TYPE_PRIO 0x24bc 111c5aff182SThomas Petazzoni #define MVNETA_FORCE_UNI BIT(21) 112c5aff182SThomas Petazzoni #define MVNETA_TXQ_CMD_1 0x24e4 113c5aff182SThomas Petazzoni #define MVNETA_TXQ_CMD 0x2448 114c5aff182SThomas Petazzoni #define MVNETA_TXQ_DISABLE_SHIFT 8 115c5aff182SThomas Petazzoni #define MVNETA_TXQ_ENABLE_MASK 0x000000ff 116e483911fSAndrew Lunn #define MVNETA_RX_DISCARD_FRAME_COUNT 0x2484 117e483911fSAndrew Lunn #define MVNETA_OVERRUN_FRAME_COUNT 0x2488 118898b2970SStas Sergeev #define MVNETA_GMAC_CLOCK_DIVIDER 0x24f4 119898b2970SStas Sergeev #define MVNETA_GMAC_1MS_CLOCK_ENABLE BIT(31) 120c5aff182SThomas Petazzoni #define MVNETA_ACC_MODE 0x2500 121dc35a10fSMarcin Wojtas #define MVNETA_BM_ADDRESS 0x2504 122c5aff182SThomas Petazzoni #define MVNETA_CPU_MAP(cpu) (0x2540 + ((cpu) << 2)) 123c5aff182SThomas Petazzoni #define MVNETA_CPU_RXQ_ACCESS_ALL_MASK 0x000000ff 124c5aff182SThomas Petazzoni #define MVNETA_CPU_TXQ_ACCESS_ALL_MASK 0x0000ff00 1252dcf75e2SGregory CLEMENT #define MVNETA_CPU_RXQ_ACCESS(rxq) BIT(rxq) 12650bf8cb6SGregory CLEMENT #define MVNETA_CPU_TXQ_ACCESS(txq) BIT(txq + 8) 127c5aff182SThomas Petazzoni #define MVNETA_RXQ_TIME_COAL_REG(q) (0x2580 + ((q) << 2)) 12840ba35e7Swilly tarreau 1292dcf75e2SGregory CLEMENT /* Exception Interrupt Port/Queue Cause register 1302dcf75e2SGregory CLEMENT * 1312dcf75e2SGregory CLEMENT * Their behavior depend of the mapping done using the PCPX2Q 1322dcf75e2SGregory CLEMENT * registers. For a given CPU if the bit associated to a queue is not 1332dcf75e2SGregory CLEMENT * set, then for the register a read from this CPU will always return 1342dcf75e2SGregory CLEMENT * 0 and a write won't do anything 1352dcf75e2SGregory CLEMENT */ 13640ba35e7Swilly tarreau 137c5aff182SThomas Petazzoni #define MVNETA_INTR_NEW_CAUSE 0x25a0 138c5aff182SThomas Petazzoni #define MVNETA_INTR_NEW_MASK 0x25a4 13940ba35e7Swilly tarreau 14040ba35e7Swilly tarreau /* bits 0..7 = TXQ SENT, one bit per queue. 14140ba35e7Swilly tarreau * bits 8..15 = RXQ OCCUP, one bit per queue. 14240ba35e7Swilly tarreau * bits 16..23 = RXQ FREE, one bit per queue. 14340ba35e7Swilly tarreau * bit 29 = OLD_REG_SUM, see old reg ? 14440ba35e7Swilly tarreau * bit 30 = TX_ERR_SUM, one bit for 4 ports 14540ba35e7Swilly tarreau * bit 31 = MISC_SUM, one bit for 4 ports 14640ba35e7Swilly tarreau */ 14740ba35e7Swilly tarreau #define MVNETA_TX_INTR_MASK(nr_txqs) (((1 << nr_txqs) - 1) << 0) 14840ba35e7Swilly tarreau #define MVNETA_TX_INTR_MASK_ALL (0xff << 0) 14940ba35e7Swilly tarreau #define MVNETA_RX_INTR_MASK(nr_rxqs) (((1 << nr_rxqs) - 1) << 8) 15040ba35e7Swilly tarreau #define MVNETA_RX_INTR_MASK_ALL (0xff << 8) 151898b2970SStas Sergeev #define MVNETA_MISCINTR_INTR_MASK BIT(31) 15240ba35e7Swilly tarreau 153c5aff182SThomas Petazzoni #define MVNETA_INTR_OLD_CAUSE 0x25a8 154c5aff182SThomas Petazzoni #define MVNETA_INTR_OLD_MASK 0x25ac 15540ba35e7Swilly tarreau 15640ba35e7Swilly tarreau /* Data Path Port/Queue Cause Register */ 157c5aff182SThomas Petazzoni #define MVNETA_INTR_MISC_CAUSE 0x25b0 158c5aff182SThomas Petazzoni #define MVNETA_INTR_MISC_MASK 0x25b4 15940ba35e7Swilly tarreau 16040ba35e7Swilly tarreau #define MVNETA_CAUSE_PHY_STATUS_CHANGE BIT(0) 16140ba35e7Swilly tarreau #define MVNETA_CAUSE_LINK_CHANGE BIT(1) 16240ba35e7Swilly tarreau #define MVNETA_CAUSE_PTP BIT(4) 16340ba35e7Swilly tarreau 16440ba35e7Swilly tarreau #define MVNETA_CAUSE_INTERNAL_ADDR_ERR BIT(7) 16540ba35e7Swilly tarreau #define MVNETA_CAUSE_RX_OVERRUN BIT(8) 16640ba35e7Swilly tarreau #define MVNETA_CAUSE_RX_CRC_ERROR BIT(9) 16740ba35e7Swilly tarreau #define MVNETA_CAUSE_RX_LARGE_PKT BIT(10) 16840ba35e7Swilly tarreau #define MVNETA_CAUSE_TX_UNDERUN BIT(11) 16940ba35e7Swilly tarreau #define MVNETA_CAUSE_PRBS_ERR BIT(12) 17040ba35e7Swilly tarreau #define MVNETA_CAUSE_PSC_SYNC_CHANGE BIT(13) 17140ba35e7Swilly tarreau #define MVNETA_CAUSE_SERDES_SYNC_ERR BIT(14) 17240ba35e7Swilly tarreau 17340ba35e7Swilly tarreau #define MVNETA_CAUSE_BMU_ALLOC_ERR_SHIFT 16 17440ba35e7Swilly tarreau #define MVNETA_CAUSE_BMU_ALLOC_ERR_ALL_MASK (0xF << MVNETA_CAUSE_BMU_ALLOC_ERR_SHIFT) 17540ba35e7Swilly tarreau #define MVNETA_CAUSE_BMU_ALLOC_ERR_MASK(pool) (1 << (MVNETA_CAUSE_BMU_ALLOC_ERR_SHIFT + (pool))) 17640ba35e7Swilly tarreau 17740ba35e7Swilly tarreau #define MVNETA_CAUSE_TXQ_ERROR_SHIFT 24 17840ba35e7Swilly tarreau #define MVNETA_CAUSE_TXQ_ERROR_ALL_MASK (0xFF << MVNETA_CAUSE_TXQ_ERROR_SHIFT) 17940ba35e7Swilly tarreau #define MVNETA_CAUSE_TXQ_ERROR_MASK(q) (1 << (MVNETA_CAUSE_TXQ_ERROR_SHIFT + (q))) 18040ba35e7Swilly tarreau 181c5aff182SThomas Petazzoni #define MVNETA_INTR_ENABLE 0x25b8 182c5aff182SThomas Petazzoni #define MVNETA_TXQ_INTR_ENABLE_ALL_MASK 0x0000ff00 183dc1aadf6SMarcin Wojtas #define MVNETA_RXQ_INTR_ENABLE_ALL_MASK 0x000000ff 18440ba35e7Swilly tarreau 185c5aff182SThomas Petazzoni #define MVNETA_RXQ_CMD 0x2680 186c5aff182SThomas Petazzoni #define MVNETA_RXQ_DISABLE_SHIFT 8 187c5aff182SThomas Petazzoni #define MVNETA_RXQ_ENABLE_MASK 0x000000ff 188c5aff182SThomas Petazzoni #define MVETH_TXQ_TOKEN_COUNT_REG(q) (0x2700 + ((q) << 4)) 189c5aff182SThomas Petazzoni #define MVETH_TXQ_TOKEN_CFG_REG(q) (0x2704 + ((q) << 4)) 190c5aff182SThomas Petazzoni #define MVNETA_GMAC_CTRL_0 0x2c00 191c5aff182SThomas Petazzoni #define MVNETA_GMAC_MAX_RX_SIZE_SHIFT 2 192c5aff182SThomas Petazzoni #define MVNETA_GMAC_MAX_RX_SIZE_MASK 0x7ffc 19322f4bf8aSRussell King #define MVNETA_GMAC0_PORT_1000BASE_X BIT(1) 194c5aff182SThomas Petazzoni #define MVNETA_GMAC0_PORT_ENABLE BIT(0) 195c5aff182SThomas Petazzoni #define MVNETA_GMAC_CTRL_2 0x2c08 196898b2970SStas Sergeev #define MVNETA_GMAC2_INBAND_AN_ENABLE BIT(0) 197a79121d3SThomas Petazzoni #define MVNETA_GMAC2_PCS_ENABLE BIT(3) 198c5aff182SThomas Petazzoni #define MVNETA_GMAC2_PORT_RGMII BIT(4) 199c5aff182SThomas Petazzoni #define MVNETA_GMAC2_PORT_RESET BIT(6) 200c5aff182SThomas Petazzoni #define MVNETA_GMAC_STATUS 0x2c10 201c5aff182SThomas Petazzoni #define MVNETA_GMAC_LINK_UP BIT(0) 202c5aff182SThomas Petazzoni #define MVNETA_GMAC_SPEED_1000 BIT(1) 203c5aff182SThomas Petazzoni #define MVNETA_GMAC_SPEED_100 BIT(2) 204c5aff182SThomas Petazzoni #define MVNETA_GMAC_FULL_DUPLEX BIT(3) 205c5aff182SThomas Petazzoni #define MVNETA_GMAC_RX_FLOW_CTRL_ENABLE BIT(4) 206c5aff182SThomas Petazzoni #define MVNETA_GMAC_TX_FLOW_CTRL_ENABLE BIT(5) 207c5aff182SThomas Petazzoni #define MVNETA_GMAC_RX_FLOW_CTRL_ACTIVE BIT(6) 208c5aff182SThomas Petazzoni #define MVNETA_GMAC_TX_FLOW_CTRL_ACTIVE BIT(7) 209503f9aa9SRussell King #define MVNETA_GMAC_AN_COMPLETE BIT(11) 210503f9aa9SRussell King #define MVNETA_GMAC_SYNC_OK BIT(14) 211c5aff182SThomas Petazzoni #define MVNETA_GMAC_AUTONEG_CONFIG 0x2c0c 212c5aff182SThomas Petazzoni #define MVNETA_GMAC_FORCE_LINK_DOWN BIT(0) 213c5aff182SThomas Petazzoni #define MVNETA_GMAC_FORCE_LINK_PASS BIT(1) 214898b2970SStas Sergeev #define MVNETA_GMAC_INBAND_AN_ENABLE BIT(2) 21522f4bf8aSRussell King #define MVNETA_GMAC_AN_BYPASS_ENABLE BIT(3) 21622f4bf8aSRussell King #define MVNETA_GMAC_INBAND_RESTART_AN BIT(4) 217c5aff182SThomas Petazzoni #define MVNETA_GMAC_CONFIG_MII_SPEED BIT(5) 218c5aff182SThomas Petazzoni #define MVNETA_GMAC_CONFIG_GMII_SPEED BIT(6) 21971408602SThomas Petazzoni #define MVNETA_GMAC_AN_SPEED_EN BIT(7) 22022f4bf8aSRussell King #define MVNETA_GMAC_CONFIG_FLOW_CTRL BIT(8) 22122f4bf8aSRussell King #define MVNETA_GMAC_ADVERT_SYM_FLOW_CTRL BIT(9) 222898b2970SStas Sergeev #define MVNETA_GMAC_AN_FLOW_CTRL_EN BIT(11) 223c5aff182SThomas Petazzoni #define MVNETA_GMAC_CONFIG_FULL_DUPLEX BIT(12) 22471408602SThomas Petazzoni #define MVNETA_GMAC_AN_DUPLEX_EN BIT(13) 225da58a931SMaxime Chevallier #define MVNETA_GMAC_CTRL_4 0x2c90 226da58a931SMaxime Chevallier #define MVNETA_GMAC4_SHORT_PREAMBLE_ENABLE BIT(1) 227e483911fSAndrew Lunn #define MVNETA_MIB_COUNTERS_BASE 0x3000 228c5aff182SThomas Petazzoni #define MVNETA_MIB_LATE_COLLISION 0x7c 229c5aff182SThomas Petazzoni #define MVNETA_DA_FILT_SPEC_MCAST 0x3400 230c5aff182SThomas Petazzoni #define MVNETA_DA_FILT_OTH_MCAST 0x3500 231c5aff182SThomas Petazzoni #define MVNETA_DA_FILT_UCAST_BASE 0x3600 232c5aff182SThomas Petazzoni #define MVNETA_TXQ_BASE_ADDR_REG(q) (0x3c00 + ((q) << 2)) 233c5aff182SThomas Petazzoni #define MVNETA_TXQ_SIZE_REG(q) (0x3c20 + ((q) << 2)) 234c5aff182SThomas Petazzoni #define MVNETA_TXQ_SENT_THRESH_ALL_MASK 0x3fff0000 235c5aff182SThomas Petazzoni #define MVNETA_TXQ_SENT_THRESH_MASK(coal) ((coal) << 16) 236c5aff182SThomas Petazzoni #define MVNETA_TXQ_UPDATE_REG(q) (0x3c60 + ((q) << 2)) 237c5aff182SThomas Petazzoni #define MVNETA_TXQ_DEC_SENT_SHIFT 16 2382a90f7e1SSimon Guinot #define MVNETA_TXQ_DEC_SENT_MASK 0xff 239c5aff182SThomas Petazzoni #define MVNETA_TXQ_STATUS_REG(q) (0x3c40 + ((q) << 2)) 240c5aff182SThomas Petazzoni #define MVNETA_TXQ_SENT_DESC_SHIFT 16 241c5aff182SThomas Petazzoni #define MVNETA_TXQ_SENT_DESC_MASK 0x3fff0000 242c5aff182SThomas Petazzoni #define MVNETA_PORT_TX_RESET 0x3cf0 243c5aff182SThomas Petazzoni #define MVNETA_PORT_TX_DMA_RESET BIT(0) 244c5aff182SThomas Petazzoni #define MVNETA_TX_MTU 0x3e0c 245c5aff182SThomas Petazzoni #define MVNETA_TX_TOKEN_SIZE 0x3e14 246c5aff182SThomas Petazzoni #define MVNETA_TX_TOKEN_SIZE_MAX 0xffffffff 247c5aff182SThomas Petazzoni #define MVNETA_TXQ_TOKEN_SIZE_REG(q) (0x3e40 + ((q) << 2)) 248c5aff182SThomas Petazzoni #define MVNETA_TXQ_TOKEN_SIZE_MAX 0x7fffffff 249c5aff182SThomas Petazzoni 2506d81f451SRussell King #define MVNETA_LPI_CTRL_0 0x2cc0 2516d81f451SRussell King #define MVNETA_LPI_CTRL_1 0x2cc4 2526d81f451SRussell King #define MVNETA_LPI_REQUEST_ENABLE BIT(0) 2536d81f451SRussell King #define MVNETA_LPI_CTRL_2 0x2cc8 2546d81f451SRussell King #define MVNETA_LPI_STATUS 0x2ccc 2556d81f451SRussell King 256c5aff182SThomas Petazzoni #define MVNETA_CAUSE_TXQ_SENT_DESC_ALL_MASK 0xff 257c5aff182SThomas Petazzoni 258c5aff182SThomas Petazzoni /* Descriptor ring Macros */ 259c5aff182SThomas Petazzoni #define MVNETA_QUEUE_NEXT_DESC(q, index) \ 260c5aff182SThomas Petazzoni (((index) < (q)->last_desc) ? ((index) + 1) : 0) 261c5aff182SThomas Petazzoni 262c5aff182SThomas Petazzoni /* Various constants */ 263c5aff182SThomas Petazzoni 264c5aff182SThomas Petazzoni /* Coalescing */ 26506708f81SDmitri Epshtein #define MVNETA_TXDONE_COAL_PKTS 0 /* interrupt per packet */ 266c5aff182SThomas Petazzoni #define MVNETA_RX_COAL_PKTS 32 267c5aff182SThomas Petazzoni #define MVNETA_RX_COAL_USEC 100 268c5aff182SThomas Petazzoni 2696a20c175SThomas Petazzoni /* The two bytes Marvell header. Either contains a special value used 270c5aff182SThomas Petazzoni * by Marvell switches when a specific hardware mode is enabled (not 271c5aff182SThomas Petazzoni * supported by this driver) or is filled automatically by zeroes on 272c5aff182SThomas Petazzoni * the RX side. Those two bytes being at the front of the Ethernet 273c5aff182SThomas Petazzoni * header, they allow to have the IP header aligned on a 4 bytes 274c5aff182SThomas Petazzoni * boundary automatically: the hardware skips those two bytes on its 275c5aff182SThomas Petazzoni * own. 276c5aff182SThomas Petazzoni */ 277c5aff182SThomas Petazzoni #define MVNETA_MH_SIZE 2 278c5aff182SThomas Petazzoni 279c5aff182SThomas Petazzoni #define MVNETA_VLAN_TAG_LEN 4 280c5aff182SThomas Petazzoni 2819110ee07SMarcin Wojtas #define MVNETA_TX_CSUM_DEF_SIZE 1600 282c5aff182SThomas Petazzoni #define MVNETA_TX_CSUM_MAX_SIZE 9800 283dc35a10fSMarcin Wojtas #define MVNETA_ACC_MODE_EXT1 1 284dc35a10fSMarcin Wojtas #define MVNETA_ACC_MODE_EXT2 2 285dc35a10fSMarcin Wojtas 286dc35a10fSMarcin Wojtas #define MVNETA_MAX_DECODE_WIN 6 287c5aff182SThomas Petazzoni 288c5aff182SThomas Petazzoni /* Timeout constants */ 289c5aff182SThomas Petazzoni #define MVNETA_TX_DISABLE_TIMEOUT_MSEC 1000 290c5aff182SThomas Petazzoni #define MVNETA_RX_DISABLE_TIMEOUT_MSEC 1000 291c5aff182SThomas Petazzoni #define MVNETA_TX_FIFO_EMPTY_TIMEOUT 10000 292c5aff182SThomas Petazzoni 293c5aff182SThomas Petazzoni #define MVNETA_TX_MTU_MAX 0x3ffff 294c5aff182SThomas Petazzoni 2959a401deaSGregory CLEMENT /* The RSS lookup table actually has 256 entries but we do not use 2969a401deaSGregory CLEMENT * them yet 2979a401deaSGregory CLEMENT */ 2989a401deaSGregory CLEMENT #define MVNETA_RSS_LU_TABLE_SIZE 1 2999a401deaSGregory CLEMENT 300c5aff182SThomas Petazzoni /* Max number of Rx descriptors */ 301c307e2a8SYelena Krivosheev #define MVNETA_MAX_RXD 512 302c5aff182SThomas Petazzoni 303c5aff182SThomas Petazzoni /* Max number of Tx descriptors */ 304c307e2a8SYelena Krivosheev #define MVNETA_MAX_TXD 1024 305c5aff182SThomas Petazzoni 3068eef5f97SEzequiel Garcia /* Max number of allowed TCP segments for software TSO */ 3078eef5f97SEzequiel Garcia #define MVNETA_MAX_TSO_SEGS 100 3088eef5f97SEzequiel Garcia 3098eef5f97SEzequiel Garcia #define MVNETA_MAX_SKB_DESCS (MVNETA_MAX_TSO_SEGS * 2 + MAX_SKB_FRAGS) 3108eef5f97SEzequiel Garcia 311c5aff182SThomas Petazzoni /* descriptor aligned size */ 312c5aff182SThomas Petazzoni #define MVNETA_DESC_ALIGNED_SIZE 32 313c5aff182SThomas Petazzoni 3148d5047cfSMarcin Wojtas /* Number of bytes to be taken into account by HW when putting incoming data 3158d5047cfSMarcin Wojtas * to the buffers. It is needed in case NET_SKB_PAD exceeds maximum packet 3168d5047cfSMarcin Wojtas * offset supported in MVNETA_RXQ_CONFIG_REG(q) registers. 3178d5047cfSMarcin Wojtas */ 3188d5047cfSMarcin Wojtas #define MVNETA_RX_PKT_OFFSET_CORRECTION 64 3198d5047cfSMarcin Wojtas 320c5aff182SThomas Petazzoni #define MVNETA_RX_PKT_SIZE(mtu) \ 321c5aff182SThomas Petazzoni ALIGN((mtu) + MVNETA_MH_SIZE + MVNETA_VLAN_TAG_LEN + \ 322c5aff182SThomas Petazzoni ETH_HLEN + ETH_FCS_LEN, \ 323c66e98c9SJisheng Zhang cache_line_size()) 324c5aff182SThomas Petazzoni 3252e3173a3SEzequiel Garcia #define IS_TSO_HEADER(txq, addr) \ 3262e3173a3SEzequiel Garcia ((addr >= txq->tso_hdrs_phys) && \ 3272e3173a3SEzequiel Garcia (addr < txq->tso_hdrs_phys + txq->size * TSO_HEADER_SIZE)) 3282e3173a3SEzequiel Garcia 329dc35a10fSMarcin Wojtas #define MVNETA_RX_GET_BM_POOL_ID(rxd) \ 330dc35a10fSMarcin Wojtas (((rxd)->status & MVNETA_RXD_BM_POOL_MASK) >> MVNETA_RXD_BM_POOL_SHIFT) 331c5aff182SThomas Petazzoni 3326d81f451SRussell King enum { 3336d81f451SRussell King ETHTOOL_STAT_EEE_WAKEUP, 33417a96da6SGregory CLEMENT ETHTOOL_STAT_SKB_ALLOC_ERR, 33517a96da6SGregory CLEMENT ETHTOOL_STAT_REFILL_ERR, 3366d81f451SRussell King ETHTOOL_MAX_STATS, 3376d81f451SRussell King }; 3386d81f451SRussell King 3399b0cdefaSRussell King struct mvneta_statistic { 3409b0cdefaSRussell King unsigned short offset; 3419b0cdefaSRussell King unsigned short type; 3429b0cdefaSRussell King const char name[ETH_GSTRING_LEN]; 3439b0cdefaSRussell King }; 3449b0cdefaSRussell King 3459b0cdefaSRussell King #define T_REG_32 32 3469b0cdefaSRussell King #define T_REG_64 64 3476d81f451SRussell King #define T_SW 1 3489b0cdefaSRussell King 3499b0cdefaSRussell King static const struct mvneta_statistic mvneta_statistics[] = { 3509b0cdefaSRussell King { 0x3000, T_REG_64, "good_octets_received", }, 3519b0cdefaSRussell King { 0x3010, T_REG_32, "good_frames_received", }, 3529b0cdefaSRussell King { 0x3008, T_REG_32, "bad_octets_received", }, 3539b0cdefaSRussell King { 0x3014, T_REG_32, "bad_frames_received", }, 3549b0cdefaSRussell King { 0x3018, T_REG_32, "broadcast_frames_received", }, 3559b0cdefaSRussell King { 0x301c, T_REG_32, "multicast_frames_received", }, 3569b0cdefaSRussell King { 0x3050, T_REG_32, "unrec_mac_control_received", }, 3579b0cdefaSRussell King { 0x3058, T_REG_32, "good_fc_received", }, 3589b0cdefaSRussell King { 0x305c, T_REG_32, "bad_fc_received", }, 3599b0cdefaSRussell King { 0x3060, T_REG_32, "undersize_received", }, 3609b0cdefaSRussell King { 0x3064, T_REG_32, "fragments_received", }, 3619b0cdefaSRussell King { 0x3068, T_REG_32, "oversize_received", }, 3629b0cdefaSRussell King { 0x306c, T_REG_32, "jabber_received", }, 3639b0cdefaSRussell King { 0x3070, T_REG_32, "mac_receive_error", }, 3649b0cdefaSRussell King { 0x3074, T_REG_32, "bad_crc_event", }, 3659b0cdefaSRussell King { 0x3078, T_REG_32, "collision", }, 3669b0cdefaSRussell King { 0x307c, T_REG_32, "late_collision", }, 3679b0cdefaSRussell King { 0x2484, T_REG_32, "rx_discard", }, 3689b0cdefaSRussell King { 0x2488, T_REG_32, "rx_overrun", }, 3699b0cdefaSRussell King { 0x3020, T_REG_32, "frames_64_octets", }, 3709b0cdefaSRussell King { 0x3024, T_REG_32, "frames_65_to_127_octets", }, 3719b0cdefaSRussell King { 0x3028, T_REG_32, "frames_128_to_255_octets", }, 3729b0cdefaSRussell King { 0x302c, T_REG_32, "frames_256_to_511_octets", }, 3739b0cdefaSRussell King { 0x3030, T_REG_32, "frames_512_to_1023_octets", }, 3749b0cdefaSRussell King { 0x3034, T_REG_32, "frames_1024_to_max_octets", }, 3759b0cdefaSRussell King { 0x3038, T_REG_64, "good_octets_sent", }, 3769b0cdefaSRussell King { 0x3040, T_REG_32, "good_frames_sent", }, 3779b0cdefaSRussell King { 0x3044, T_REG_32, "excessive_collision", }, 3789b0cdefaSRussell King { 0x3048, T_REG_32, "multicast_frames_sent", }, 3799b0cdefaSRussell King { 0x304c, T_REG_32, "broadcast_frames_sent", }, 3809b0cdefaSRussell King { 0x3054, T_REG_32, "fc_sent", }, 3819b0cdefaSRussell King { 0x300c, T_REG_32, "internal_mac_transmit_err", }, 3826d81f451SRussell King { ETHTOOL_STAT_EEE_WAKEUP, T_SW, "eee_wakeup_errors", }, 38317a96da6SGregory CLEMENT { ETHTOOL_STAT_SKB_ALLOC_ERR, T_SW, "skb_alloc_errors", }, 38417a96da6SGregory CLEMENT { ETHTOOL_STAT_REFILL_ERR, T_SW, "refill_errors", }, 3859b0cdefaSRussell King }; 3869b0cdefaSRussell King 38774c41b04Swilly tarreau struct mvneta_pcpu_stats { 388c5aff182SThomas Petazzoni struct u64_stats_sync syncp; 38974c41b04Swilly tarreau u64 rx_packets; 39074c41b04Swilly tarreau u64 rx_bytes; 39174c41b04Swilly tarreau u64 tx_packets; 39274c41b04Swilly tarreau u64 tx_bytes; 393c5aff182SThomas Petazzoni }; 394c5aff182SThomas Petazzoni 39512bb03b4SMaxime Ripard struct mvneta_pcpu_port { 39612bb03b4SMaxime Ripard /* Pointer to the shared port */ 39712bb03b4SMaxime Ripard struct mvneta_port *pp; 39812bb03b4SMaxime Ripard 39912bb03b4SMaxime Ripard /* Pointer to the CPU-local NAPI struct */ 40012bb03b4SMaxime Ripard struct napi_struct napi; 40112bb03b4SMaxime Ripard 40212bb03b4SMaxime Ripard /* Cause of the previous interrupt */ 40312bb03b4SMaxime Ripard u32 cause_rx_tx; 40412bb03b4SMaxime Ripard }; 40512bb03b4SMaxime Ripard 406c5aff182SThomas Petazzoni struct mvneta_port { 407dc35a10fSMarcin Wojtas u8 id; 40812bb03b4SMaxime Ripard struct mvneta_pcpu_port __percpu *ports; 40912bb03b4SMaxime Ripard struct mvneta_pcpu_stats __percpu *stats; 41012bb03b4SMaxime Ripard 411c5aff182SThomas Petazzoni int pkt_size; 412c5aff182SThomas Petazzoni void __iomem *base; 413c5aff182SThomas Petazzoni struct mvneta_rx_queue *rxqs; 414c5aff182SThomas Petazzoni struct mvneta_tx_queue *txqs; 415c5aff182SThomas Petazzoni struct net_device *dev; 41684a3f4dbSSebastian Andrzej Siewior struct hlist_node node_online; 41784a3f4dbSSebastian Andrzej Siewior struct hlist_node node_dead; 41890b74c01SGregory CLEMENT int rxq_def; 4195888511eSGregory CLEMENT /* Protect the access to the percpu interrupt registers, 4205888511eSGregory CLEMENT * ensuring that the configuration remains coherent. 4215888511eSGregory CLEMENT */ 4225888511eSGregory CLEMENT spinlock_t lock; 423120cfa50SGregory CLEMENT bool is_stopped; 424c5aff182SThomas Petazzoni 4252636ac3cSMarcin Wojtas u32 cause_rx_tx; 4262636ac3cSMarcin Wojtas struct napi_struct napi; 4272636ac3cSMarcin Wojtas 428c5aff182SThomas Petazzoni /* Core clock */ 429189dd626SThomas Petazzoni struct clk *clk; 43015cc4a4aSJisheng Zhang /* AXI clock */ 43115cc4a4aSJisheng Zhang struct clk *clk_bus; 432c5aff182SThomas Petazzoni u8 mcast_count[256]; 433c5aff182SThomas Petazzoni u16 tx_ring_size; 434c5aff182SThomas Petazzoni u16 rx_ring_size; 435c5aff182SThomas Petazzoni 436c5aff182SThomas Petazzoni phy_interface_t phy_interface; 437503f9aa9SRussell King struct device_node *dn; 438b65657fcSSimon Guinot unsigned int tx_csum_limit; 439503f9aa9SRussell King struct phylink *phylink; 440a10c1c81SRussell King struct phy *comphy; 4419b0cdefaSRussell King 442dc35a10fSMarcin Wojtas struct mvneta_bm *bm_priv; 443dc35a10fSMarcin Wojtas struct mvneta_bm_pool *pool_long; 444dc35a10fSMarcin Wojtas struct mvneta_bm_pool *pool_short; 445dc35a10fSMarcin Wojtas int bm_win_id; 446dc35a10fSMarcin Wojtas 4476d81f451SRussell King bool eee_enabled; 4486d81f451SRussell King bool eee_active; 4496d81f451SRussell King bool tx_lpi_enabled; 4506d81f451SRussell King 4519b0cdefaSRussell King u64 ethtool_stats[ARRAY_SIZE(mvneta_statistics)]; 4529a401deaSGregory CLEMENT 4539a401deaSGregory CLEMENT u32 indir[MVNETA_RSS_LU_TABLE_SIZE]; 4542636ac3cSMarcin Wojtas 4552636ac3cSMarcin Wojtas /* Flags for special SoC configurations */ 4562636ac3cSMarcin Wojtas bool neta_armada3700; 4578d5047cfSMarcin Wojtas u16 rx_offset_correction; 4589768b45cSJane Li const struct mbus_dram_target_info *dram_target_info; 459c5aff182SThomas Petazzoni }; 460c5aff182SThomas Petazzoni 4616a20c175SThomas Petazzoni /* The mvneta_tx_desc and mvneta_rx_desc structures describe the 462c5aff182SThomas Petazzoni * layout of the transmit and reception DMA descriptors, and their 463c5aff182SThomas Petazzoni * layout is therefore defined by the hardware design 464c5aff182SThomas Petazzoni */ 4656083ed44SThomas Petazzoni 466c5aff182SThomas Petazzoni #define MVNETA_TX_L3_OFF_SHIFT 0 467c5aff182SThomas Petazzoni #define MVNETA_TX_IP_HLEN_SHIFT 8 468c5aff182SThomas Petazzoni #define MVNETA_TX_L4_UDP BIT(16) 469c5aff182SThomas Petazzoni #define MVNETA_TX_L3_IP6 BIT(17) 470c5aff182SThomas Petazzoni #define MVNETA_TXD_IP_CSUM BIT(18) 471c5aff182SThomas Petazzoni #define MVNETA_TXD_Z_PAD BIT(19) 472c5aff182SThomas Petazzoni #define MVNETA_TXD_L_DESC BIT(20) 473c5aff182SThomas Petazzoni #define MVNETA_TXD_F_DESC BIT(21) 474c5aff182SThomas Petazzoni #define MVNETA_TXD_FLZ_DESC (MVNETA_TXD_Z_PAD | \ 475c5aff182SThomas Petazzoni MVNETA_TXD_L_DESC | \ 476c5aff182SThomas Petazzoni MVNETA_TXD_F_DESC) 477c5aff182SThomas Petazzoni #define MVNETA_TX_L4_CSUM_FULL BIT(30) 478c5aff182SThomas Petazzoni #define MVNETA_TX_L4_CSUM_NOT BIT(31) 479c5aff182SThomas Petazzoni 480c5aff182SThomas Petazzoni #define MVNETA_RXD_ERR_CRC 0x0 481dc35a10fSMarcin Wojtas #define MVNETA_RXD_BM_POOL_SHIFT 13 482dc35a10fSMarcin Wojtas #define MVNETA_RXD_BM_POOL_MASK (BIT(13) | BIT(14)) 483c5aff182SThomas Petazzoni #define MVNETA_RXD_ERR_SUMMARY BIT(16) 484c5aff182SThomas Petazzoni #define MVNETA_RXD_ERR_OVERRUN BIT(17) 485c5aff182SThomas Petazzoni #define MVNETA_RXD_ERR_LEN BIT(18) 486c5aff182SThomas Petazzoni #define MVNETA_RXD_ERR_RESOURCE (BIT(17) | BIT(18)) 487c5aff182SThomas Petazzoni #define MVNETA_RXD_ERR_CODE_MASK (BIT(17) | BIT(18)) 488c5aff182SThomas Petazzoni #define MVNETA_RXD_L3_IP4 BIT(25) 489562e2f46SYelena Krivosheev #define MVNETA_RXD_LAST_DESC BIT(26) 490562e2f46SYelena Krivosheev #define MVNETA_RXD_FIRST_DESC BIT(27) 491562e2f46SYelena Krivosheev #define MVNETA_RXD_FIRST_LAST_DESC (MVNETA_RXD_FIRST_DESC | \ 492562e2f46SYelena Krivosheev MVNETA_RXD_LAST_DESC) 493c5aff182SThomas Petazzoni #define MVNETA_RXD_L4_CSUM_OK BIT(30) 494c5aff182SThomas Petazzoni 4959ad8fef6SThomas Petazzoni #if defined(__LITTLE_ENDIAN) 4966083ed44SThomas Petazzoni struct mvneta_tx_desc { 4976083ed44SThomas Petazzoni u32 command; /* Options used by HW for packet transmitting.*/ 498fbd1d524SAlexandre Belloni u16 reserved1; /* csum_l4 (for future use) */ 4996083ed44SThomas Petazzoni u16 data_size; /* Data size of transmitted packet in bytes */ 5006083ed44SThomas Petazzoni u32 buf_phys_addr; /* Physical addr of transmitted buffer */ 5016083ed44SThomas Petazzoni u32 reserved2; /* hw_cmd - (for future use, PMT) */ 5026083ed44SThomas Petazzoni u32 reserved3[4]; /* Reserved - (for future use) */ 5036083ed44SThomas Petazzoni }; 5046083ed44SThomas Petazzoni 5056083ed44SThomas Petazzoni struct mvneta_rx_desc { 5066083ed44SThomas Petazzoni u32 status; /* Info about received packet */ 507c5aff182SThomas Petazzoni u16 reserved1; /* pnc_info - (for future use, PnC) */ 508c5aff182SThomas Petazzoni u16 data_size; /* Size of received packet in bytes */ 5096083ed44SThomas Petazzoni 510c5aff182SThomas Petazzoni u32 buf_phys_addr; /* Physical address of the buffer */ 511c5aff182SThomas Petazzoni u32 reserved2; /* pnc_flow_id (for future use, PnC) */ 5126083ed44SThomas Petazzoni 513c5aff182SThomas Petazzoni u32 buf_cookie; /* cookie for access to RX buffer in rx path */ 514c5aff182SThomas Petazzoni u16 reserved3; /* prefetch_cmd, for future use */ 515c5aff182SThomas Petazzoni u16 reserved4; /* csum_l4 - (for future use, PnC) */ 5166083ed44SThomas Petazzoni 517c5aff182SThomas Petazzoni u32 reserved5; /* pnc_extra PnC (for future use, PnC) */ 518c5aff182SThomas Petazzoni u32 reserved6; /* hw_cmd (for future use, PnC and HWF) */ 519c5aff182SThomas Petazzoni }; 5209ad8fef6SThomas Petazzoni #else 5219ad8fef6SThomas Petazzoni struct mvneta_tx_desc { 5229ad8fef6SThomas Petazzoni u16 data_size; /* Data size of transmitted packet in bytes */ 523fbd1d524SAlexandre Belloni u16 reserved1; /* csum_l4 (for future use) */ 5249ad8fef6SThomas Petazzoni u32 command; /* Options used by HW for packet transmitting.*/ 5259ad8fef6SThomas Petazzoni u32 reserved2; /* hw_cmd - (for future use, PMT) */ 5269ad8fef6SThomas Petazzoni u32 buf_phys_addr; /* Physical addr of transmitted buffer */ 5279ad8fef6SThomas Petazzoni u32 reserved3[4]; /* Reserved - (for future use) */ 5289ad8fef6SThomas Petazzoni }; 5299ad8fef6SThomas Petazzoni 5309ad8fef6SThomas Petazzoni struct mvneta_rx_desc { 5319ad8fef6SThomas Petazzoni u16 data_size; /* Size of received packet in bytes */ 5329ad8fef6SThomas Petazzoni u16 reserved1; /* pnc_info - (for future use, PnC) */ 5339ad8fef6SThomas Petazzoni u32 status; /* Info about received packet */ 5349ad8fef6SThomas Petazzoni 5359ad8fef6SThomas Petazzoni u32 reserved2; /* pnc_flow_id (for future use, PnC) */ 5369ad8fef6SThomas Petazzoni u32 buf_phys_addr; /* Physical address of the buffer */ 5379ad8fef6SThomas Petazzoni 5389ad8fef6SThomas Petazzoni u16 reserved4; /* csum_l4 - (for future use, PnC) */ 5399ad8fef6SThomas Petazzoni u16 reserved3; /* prefetch_cmd, for future use */ 5409ad8fef6SThomas Petazzoni u32 buf_cookie; /* cookie for access to RX buffer in rx path */ 5419ad8fef6SThomas Petazzoni 5429ad8fef6SThomas Petazzoni u32 reserved5; /* pnc_extra PnC (for future use, PnC) */ 5439ad8fef6SThomas Petazzoni u32 reserved6; /* hw_cmd (for future use, PnC and HWF) */ 5449ad8fef6SThomas Petazzoni }; 5459ad8fef6SThomas Petazzoni #endif 546c5aff182SThomas Petazzoni 547c5aff182SThomas Petazzoni struct mvneta_tx_queue { 548c5aff182SThomas Petazzoni /* Number of this TX queue, in the range 0-7 */ 549c5aff182SThomas Petazzoni u8 id; 550c5aff182SThomas Petazzoni 551c5aff182SThomas Petazzoni /* Number of TX DMA descriptors in the descriptor ring */ 552c5aff182SThomas Petazzoni int size; 553c5aff182SThomas Petazzoni 554c5aff182SThomas Petazzoni /* Number of currently used TX DMA descriptor in the 5556a20c175SThomas Petazzoni * descriptor ring 5566a20c175SThomas Petazzoni */ 557c5aff182SThomas Petazzoni int count; 5582a90f7e1SSimon Guinot int pending; 5598eef5f97SEzequiel Garcia int tx_stop_threshold; 5608eef5f97SEzequiel Garcia int tx_wake_threshold; 561c5aff182SThomas Petazzoni 562c5aff182SThomas Petazzoni /* Array of transmitted skb */ 563c5aff182SThomas Petazzoni struct sk_buff **tx_skb; 564c5aff182SThomas Petazzoni 565c5aff182SThomas Petazzoni /* Index of last TX DMA descriptor that was inserted */ 566c5aff182SThomas Petazzoni int txq_put_index; 567c5aff182SThomas Petazzoni 568c5aff182SThomas Petazzoni /* Index of the TX DMA descriptor to be cleaned up */ 569c5aff182SThomas Petazzoni int txq_get_index; 570c5aff182SThomas Petazzoni 571c5aff182SThomas Petazzoni u32 done_pkts_coal; 572c5aff182SThomas Petazzoni 573c5aff182SThomas Petazzoni /* Virtual address of the TX DMA descriptors array */ 574c5aff182SThomas Petazzoni struct mvneta_tx_desc *descs; 575c5aff182SThomas Petazzoni 576c5aff182SThomas Petazzoni /* DMA address of the TX DMA descriptors array */ 577c5aff182SThomas Petazzoni dma_addr_t descs_phys; 578c5aff182SThomas Petazzoni 579c5aff182SThomas Petazzoni /* Index of the last TX DMA descriptor */ 580c5aff182SThomas Petazzoni int last_desc; 581c5aff182SThomas Petazzoni 582c5aff182SThomas Petazzoni /* Index of the next TX DMA descriptor to process */ 583c5aff182SThomas Petazzoni int next_desc_to_proc; 5842adb719dSEzequiel Garcia 5852adb719dSEzequiel Garcia /* DMA buffers for TSO headers */ 5862adb719dSEzequiel Garcia char *tso_hdrs; 5872adb719dSEzequiel Garcia 5882adb719dSEzequiel Garcia /* DMA address of TSO headers */ 5892adb719dSEzequiel Garcia dma_addr_t tso_hdrs_phys; 59050bf8cb6SGregory CLEMENT 59150bf8cb6SGregory CLEMENT /* Affinity mask for CPUs*/ 59250bf8cb6SGregory CLEMENT cpumask_t affinity_mask; 593c5aff182SThomas Petazzoni }; 594c5aff182SThomas Petazzoni 595c5aff182SThomas Petazzoni struct mvneta_rx_queue { 596c5aff182SThomas Petazzoni /* rx queue number, in the range 0-7 */ 597c5aff182SThomas Petazzoni u8 id; 598c5aff182SThomas Petazzoni 599c5aff182SThomas Petazzoni /* num of rx descriptors in the rx descriptor ring */ 600c5aff182SThomas Petazzoni int size; 601c5aff182SThomas Petazzoni 602c5aff182SThomas Petazzoni u32 pkts_coal; 603c5aff182SThomas Petazzoni u32 time_coal; 604c5aff182SThomas Petazzoni 605f88bee1cSGregory CLEMENT /* Virtual address of the RX buffer */ 606f88bee1cSGregory CLEMENT void **buf_virt_addr; 607f88bee1cSGregory CLEMENT 608c5aff182SThomas Petazzoni /* Virtual address of the RX DMA descriptors array */ 609c5aff182SThomas Petazzoni struct mvneta_rx_desc *descs; 610c5aff182SThomas Petazzoni 611c5aff182SThomas Petazzoni /* DMA address of the RX DMA descriptors array */ 612c5aff182SThomas Petazzoni dma_addr_t descs_phys; 613c5aff182SThomas Petazzoni 614c5aff182SThomas Petazzoni /* Index of the last RX DMA descriptor */ 615c5aff182SThomas Petazzoni int last_desc; 616c5aff182SThomas Petazzoni 617c5aff182SThomas Petazzoni /* Index of the next RX DMA descriptor to process */ 618c5aff182SThomas Petazzoni int next_desc_to_proc; 61917a96da6SGregory CLEMENT 620562e2f46SYelena Krivosheev /* Index of first RX DMA descriptor to refill */ 621562e2f46SYelena Krivosheev int first_to_refill; 622562e2f46SYelena Krivosheev u32 refill_num; 623562e2f46SYelena Krivosheev 624562e2f46SYelena Krivosheev /* pointer to uncomplete skb buffer */ 625562e2f46SYelena Krivosheev struct sk_buff *skb; 626562e2f46SYelena Krivosheev int left_size; 627562e2f46SYelena Krivosheev 62817a96da6SGregory CLEMENT /* error counters */ 62917a96da6SGregory CLEMENT u32 skb_alloc_err; 63017a96da6SGregory CLEMENT u32 refill_err; 631c5aff182SThomas Petazzoni }; 632c5aff182SThomas Petazzoni 63384a3f4dbSSebastian Andrzej Siewior static enum cpuhp_state online_hpstate; 634edadb7faSEzequiel Garcia /* The hardware supports eight (8) rx queues, but we are only allowing 635edadb7faSEzequiel Garcia * the first one to be used. Therefore, let's just allocate one queue. 636edadb7faSEzequiel Garcia */ 637d8936657SMaxime Ripard static int rxq_number = 8; 638c5aff182SThomas Petazzoni static int txq_number = 8; 639c5aff182SThomas Petazzoni 640c5aff182SThomas Petazzoni static int rxq_def; 641c5aff182SThomas Petazzoni 642f19fadfcSwilly tarreau static int rx_copybreak __read_mostly = 256; 643562e2f46SYelena Krivosheev static int rx_header_size __read_mostly = 128; 644f19fadfcSwilly tarreau 645dc35a10fSMarcin Wojtas /* HW BM need that each port be identify by a unique ID */ 646dc35a10fSMarcin Wojtas static int global_port_id; 647dc35a10fSMarcin Wojtas 648c5aff182SThomas Petazzoni #define MVNETA_DRIVER_NAME "mvneta" 649c5aff182SThomas Petazzoni #define MVNETA_DRIVER_VERSION "1.0" 650c5aff182SThomas Petazzoni 651c5aff182SThomas Petazzoni /* Utility/helper methods */ 652c5aff182SThomas Petazzoni 653c5aff182SThomas Petazzoni /* Write helper method */ 654c5aff182SThomas Petazzoni static void mvreg_write(struct mvneta_port *pp, u32 offset, u32 data) 655c5aff182SThomas Petazzoni { 656c5aff182SThomas Petazzoni writel(data, pp->base + offset); 657c5aff182SThomas Petazzoni } 658c5aff182SThomas Petazzoni 659c5aff182SThomas Petazzoni /* Read helper method */ 660c5aff182SThomas Petazzoni static u32 mvreg_read(struct mvneta_port *pp, u32 offset) 661c5aff182SThomas Petazzoni { 662c5aff182SThomas Petazzoni return readl(pp->base + offset); 663c5aff182SThomas Petazzoni } 664c5aff182SThomas Petazzoni 665c5aff182SThomas Petazzoni /* Increment txq get counter */ 666c5aff182SThomas Petazzoni static void mvneta_txq_inc_get(struct mvneta_tx_queue *txq) 667c5aff182SThomas Petazzoni { 668c5aff182SThomas Petazzoni txq->txq_get_index++; 669c5aff182SThomas Petazzoni if (txq->txq_get_index == txq->size) 670c5aff182SThomas Petazzoni txq->txq_get_index = 0; 671c5aff182SThomas Petazzoni } 672c5aff182SThomas Petazzoni 673c5aff182SThomas Petazzoni /* Increment txq put counter */ 674c5aff182SThomas Petazzoni static void mvneta_txq_inc_put(struct mvneta_tx_queue *txq) 675c5aff182SThomas Petazzoni { 676c5aff182SThomas Petazzoni txq->txq_put_index++; 677c5aff182SThomas Petazzoni if (txq->txq_put_index == txq->size) 678c5aff182SThomas Petazzoni txq->txq_put_index = 0; 679c5aff182SThomas Petazzoni } 680c5aff182SThomas Petazzoni 681c5aff182SThomas Petazzoni 682c5aff182SThomas Petazzoni /* Clear all MIB counters */ 683c5aff182SThomas Petazzoni static void mvneta_mib_counters_clear(struct mvneta_port *pp) 684c5aff182SThomas Petazzoni { 685c5aff182SThomas Petazzoni int i; 686c5aff182SThomas Petazzoni u32 dummy; 687c5aff182SThomas Petazzoni 688c5aff182SThomas Petazzoni /* Perform dummy reads from MIB counters */ 689c5aff182SThomas Petazzoni for (i = 0; i < MVNETA_MIB_LATE_COLLISION; i += 4) 690c5aff182SThomas Petazzoni dummy = mvreg_read(pp, (MVNETA_MIB_COUNTERS_BASE + i)); 691e483911fSAndrew Lunn dummy = mvreg_read(pp, MVNETA_RX_DISCARD_FRAME_COUNT); 692e483911fSAndrew Lunn dummy = mvreg_read(pp, MVNETA_OVERRUN_FRAME_COUNT); 693c5aff182SThomas Petazzoni } 694c5aff182SThomas Petazzoni 695c5aff182SThomas Petazzoni /* Get System Network Statistics */ 696bc1f4470Sstephen hemminger static void 6972dc0d2b4SBaoyou Xie mvneta_get_stats64(struct net_device *dev, 698c5aff182SThomas Petazzoni struct rtnl_link_stats64 *stats) 699c5aff182SThomas Petazzoni { 700c5aff182SThomas Petazzoni struct mvneta_port *pp = netdev_priv(dev); 701c5aff182SThomas Petazzoni unsigned int start; 70274c41b04Swilly tarreau int cpu; 703c5aff182SThomas Petazzoni 70474c41b04Swilly tarreau for_each_possible_cpu(cpu) { 70574c41b04Swilly tarreau struct mvneta_pcpu_stats *cpu_stats; 70674c41b04Swilly tarreau u64 rx_packets; 70774c41b04Swilly tarreau u64 rx_bytes; 70874c41b04Swilly tarreau u64 tx_packets; 70974c41b04Swilly tarreau u64 tx_bytes; 710c5aff182SThomas Petazzoni 71174c41b04Swilly tarreau cpu_stats = per_cpu_ptr(pp->stats, cpu); 712c5aff182SThomas Petazzoni do { 71357a7744eSEric W. Biederman start = u64_stats_fetch_begin_irq(&cpu_stats->syncp); 71474c41b04Swilly tarreau rx_packets = cpu_stats->rx_packets; 71574c41b04Swilly tarreau rx_bytes = cpu_stats->rx_bytes; 71674c41b04Swilly tarreau tx_packets = cpu_stats->tx_packets; 71774c41b04Swilly tarreau tx_bytes = cpu_stats->tx_bytes; 71857a7744eSEric W. Biederman } while (u64_stats_fetch_retry_irq(&cpu_stats->syncp, start)); 719c5aff182SThomas Petazzoni 72074c41b04Swilly tarreau stats->rx_packets += rx_packets; 72174c41b04Swilly tarreau stats->rx_bytes += rx_bytes; 72274c41b04Swilly tarreau stats->tx_packets += tx_packets; 72374c41b04Swilly tarreau stats->tx_bytes += tx_bytes; 72474c41b04Swilly tarreau } 725c5aff182SThomas Petazzoni 726c5aff182SThomas Petazzoni stats->rx_errors = dev->stats.rx_errors; 727c5aff182SThomas Petazzoni stats->rx_dropped = dev->stats.rx_dropped; 728c5aff182SThomas Petazzoni 729c5aff182SThomas Petazzoni stats->tx_dropped = dev->stats.tx_dropped; 730c5aff182SThomas Petazzoni } 731c5aff182SThomas Petazzoni 732c5aff182SThomas Petazzoni /* Rx descriptors helper methods */ 733c5aff182SThomas Petazzoni 7345428213cSwilly tarreau /* Checks whether the RX descriptor having this status is both the first 7355428213cSwilly tarreau * and the last descriptor for the RX packet. Each RX packet is currently 736c5aff182SThomas Petazzoni * received through a single RX descriptor, so not having each RX 737c5aff182SThomas Petazzoni * descriptor with its first and last bits set is an error 738c5aff182SThomas Petazzoni */ 7395428213cSwilly tarreau static int mvneta_rxq_desc_is_first_last(u32 status) 740c5aff182SThomas Petazzoni { 7415428213cSwilly tarreau return (status & MVNETA_RXD_FIRST_LAST_DESC) == 742c5aff182SThomas Petazzoni MVNETA_RXD_FIRST_LAST_DESC; 743c5aff182SThomas Petazzoni } 744c5aff182SThomas Petazzoni 745c5aff182SThomas Petazzoni /* Add number of descriptors ready to receive new packets */ 746c5aff182SThomas Petazzoni static void mvneta_rxq_non_occup_desc_add(struct mvneta_port *pp, 747c5aff182SThomas Petazzoni struct mvneta_rx_queue *rxq, 748c5aff182SThomas Petazzoni int ndescs) 749c5aff182SThomas Petazzoni { 750c5aff182SThomas Petazzoni /* Only MVNETA_RXQ_ADD_NON_OCCUPIED_MAX (255) descriptors can 7516a20c175SThomas Petazzoni * be added at once 7526a20c175SThomas Petazzoni */ 753c5aff182SThomas Petazzoni while (ndescs > MVNETA_RXQ_ADD_NON_OCCUPIED_MAX) { 754c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id), 755c5aff182SThomas Petazzoni (MVNETA_RXQ_ADD_NON_OCCUPIED_MAX << 756c5aff182SThomas Petazzoni MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT)); 757c5aff182SThomas Petazzoni ndescs -= MVNETA_RXQ_ADD_NON_OCCUPIED_MAX; 758c5aff182SThomas Petazzoni } 759c5aff182SThomas Petazzoni 760c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id), 761c5aff182SThomas Petazzoni (ndescs << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT)); 762c5aff182SThomas Petazzoni } 763c5aff182SThomas Petazzoni 764c5aff182SThomas Petazzoni /* Get number of RX descriptors occupied by received packets */ 765c5aff182SThomas Petazzoni static int mvneta_rxq_busy_desc_num_get(struct mvneta_port *pp, 766c5aff182SThomas Petazzoni struct mvneta_rx_queue *rxq) 767c5aff182SThomas Petazzoni { 768c5aff182SThomas Petazzoni u32 val; 769c5aff182SThomas Petazzoni 770c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_RXQ_STATUS_REG(rxq->id)); 771c5aff182SThomas Petazzoni return val & MVNETA_RXQ_OCCUPIED_ALL_MASK; 772c5aff182SThomas Petazzoni } 773c5aff182SThomas Petazzoni 7746a20c175SThomas Petazzoni /* Update num of rx desc called upon return from rx path or 775c5aff182SThomas Petazzoni * from mvneta_rxq_drop_pkts(). 776c5aff182SThomas Petazzoni */ 777c5aff182SThomas Petazzoni static void mvneta_rxq_desc_num_update(struct mvneta_port *pp, 778c5aff182SThomas Petazzoni struct mvneta_rx_queue *rxq, 779c5aff182SThomas Petazzoni int rx_done, int rx_filled) 780c5aff182SThomas Petazzoni { 781c5aff182SThomas Petazzoni u32 val; 782c5aff182SThomas Petazzoni 783c5aff182SThomas Petazzoni if ((rx_done <= 0xff) && (rx_filled <= 0xff)) { 784c5aff182SThomas Petazzoni val = rx_done | 785c5aff182SThomas Petazzoni (rx_filled << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT); 786c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id), val); 787c5aff182SThomas Petazzoni return; 788c5aff182SThomas Petazzoni } 789c5aff182SThomas Petazzoni 790c5aff182SThomas Petazzoni /* Only 255 descriptors can be added at once */ 791c5aff182SThomas Petazzoni while ((rx_done > 0) || (rx_filled > 0)) { 792c5aff182SThomas Petazzoni if (rx_done <= 0xff) { 793c5aff182SThomas Petazzoni val = rx_done; 794c5aff182SThomas Petazzoni rx_done = 0; 795c5aff182SThomas Petazzoni } else { 796c5aff182SThomas Petazzoni val = 0xff; 797c5aff182SThomas Petazzoni rx_done -= 0xff; 798c5aff182SThomas Petazzoni } 799c5aff182SThomas Petazzoni if (rx_filled <= 0xff) { 800c5aff182SThomas Petazzoni val |= rx_filled << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT; 801c5aff182SThomas Petazzoni rx_filled = 0; 802c5aff182SThomas Petazzoni } else { 803c5aff182SThomas Petazzoni val |= 0xff << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT; 804c5aff182SThomas Petazzoni rx_filled -= 0xff; 805c5aff182SThomas Petazzoni } 806c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id), val); 807c5aff182SThomas Petazzoni } 808c5aff182SThomas Petazzoni } 809c5aff182SThomas Petazzoni 810c5aff182SThomas Petazzoni /* Get pointer to next RX descriptor to be processed by SW */ 811c5aff182SThomas Petazzoni static struct mvneta_rx_desc * 812c5aff182SThomas Petazzoni mvneta_rxq_next_desc_get(struct mvneta_rx_queue *rxq) 813c5aff182SThomas Petazzoni { 814c5aff182SThomas Petazzoni int rx_desc = rxq->next_desc_to_proc; 815c5aff182SThomas Petazzoni 816c5aff182SThomas Petazzoni rxq->next_desc_to_proc = MVNETA_QUEUE_NEXT_DESC(rxq, rx_desc); 81734e4179dSwilly tarreau prefetch(rxq->descs + rxq->next_desc_to_proc); 818c5aff182SThomas Petazzoni return rxq->descs + rx_desc; 819c5aff182SThomas Petazzoni } 820c5aff182SThomas Petazzoni 821c5aff182SThomas Petazzoni /* Change maximum receive size of the port. */ 822c5aff182SThomas Petazzoni static void mvneta_max_rx_size_set(struct mvneta_port *pp, int max_rx_size) 823c5aff182SThomas Petazzoni { 824c5aff182SThomas Petazzoni u32 val; 825c5aff182SThomas Petazzoni 826c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_GMAC_CTRL_0); 827c5aff182SThomas Petazzoni val &= ~MVNETA_GMAC_MAX_RX_SIZE_MASK; 828c5aff182SThomas Petazzoni val |= ((max_rx_size - MVNETA_MH_SIZE) / 2) << 829c5aff182SThomas Petazzoni MVNETA_GMAC_MAX_RX_SIZE_SHIFT; 830c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_GMAC_CTRL_0, val); 831c5aff182SThomas Petazzoni } 832c5aff182SThomas Petazzoni 833c5aff182SThomas Petazzoni 834c5aff182SThomas Petazzoni /* Set rx queue offset */ 835c5aff182SThomas Petazzoni static void mvneta_rxq_offset_set(struct mvneta_port *pp, 836c5aff182SThomas Petazzoni struct mvneta_rx_queue *rxq, 837c5aff182SThomas Petazzoni int offset) 838c5aff182SThomas Petazzoni { 839c5aff182SThomas Petazzoni u32 val; 840c5aff182SThomas Petazzoni 841c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_RXQ_CONFIG_REG(rxq->id)); 842c5aff182SThomas Petazzoni val &= ~MVNETA_RXQ_PKT_OFFSET_ALL_MASK; 843c5aff182SThomas Petazzoni 844c5aff182SThomas Petazzoni /* Offset is in */ 845c5aff182SThomas Petazzoni val |= MVNETA_RXQ_PKT_OFFSET_MASK(offset >> 3); 846c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_RXQ_CONFIG_REG(rxq->id), val); 847c5aff182SThomas Petazzoni } 848c5aff182SThomas Petazzoni 849c5aff182SThomas Petazzoni 850c5aff182SThomas Petazzoni /* Tx descriptors helper methods */ 851c5aff182SThomas Petazzoni 852c5aff182SThomas Petazzoni /* Update HW with number of TX descriptors to be sent */ 853c5aff182SThomas Petazzoni static void mvneta_txq_pend_desc_add(struct mvneta_port *pp, 854c5aff182SThomas Petazzoni struct mvneta_tx_queue *txq, 855c5aff182SThomas Petazzoni int pend_desc) 856c5aff182SThomas Petazzoni { 857c5aff182SThomas Petazzoni u32 val; 858c5aff182SThomas Petazzoni 8590d63785cSSimon Guinot pend_desc += txq->pending; 8600d63785cSSimon Guinot 8610d63785cSSimon Guinot /* Only 255 Tx descriptors can be added at once */ 8620d63785cSSimon Guinot do { 8630d63785cSSimon Guinot val = min(pend_desc, 255); 864c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val); 8650d63785cSSimon Guinot pend_desc -= val; 8660d63785cSSimon Guinot } while (pend_desc > 0); 8672a90f7e1SSimon Guinot txq->pending = 0; 868c5aff182SThomas Petazzoni } 869c5aff182SThomas Petazzoni 870c5aff182SThomas Petazzoni /* Get pointer to next TX descriptor to be processed (send) by HW */ 871c5aff182SThomas Petazzoni static struct mvneta_tx_desc * 872c5aff182SThomas Petazzoni mvneta_txq_next_desc_get(struct mvneta_tx_queue *txq) 873c5aff182SThomas Petazzoni { 874c5aff182SThomas Petazzoni int tx_desc = txq->next_desc_to_proc; 875c5aff182SThomas Petazzoni 876c5aff182SThomas Petazzoni txq->next_desc_to_proc = MVNETA_QUEUE_NEXT_DESC(txq, tx_desc); 877c5aff182SThomas Petazzoni return txq->descs + tx_desc; 878c5aff182SThomas Petazzoni } 879c5aff182SThomas Petazzoni 880c5aff182SThomas Petazzoni /* Release the last allocated TX descriptor. Useful to handle DMA 8816a20c175SThomas Petazzoni * mapping failures in the TX path. 8826a20c175SThomas Petazzoni */ 883c5aff182SThomas Petazzoni static void mvneta_txq_desc_put(struct mvneta_tx_queue *txq) 884c5aff182SThomas Petazzoni { 885c5aff182SThomas Petazzoni if (txq->next_desc_to_proc == 0) 886c5aff182SThomas Petazzoni txq->next_desc_to_proc = txq->last_desc - 1; 887c5aff182SThomas Petazzoni else 888c5aff182SThomas Petazzoni txq->next_desc_to_proc--; 889c5aff182SThomas Petazzoni } 890c5aff182SThomas Petazzoni 891c5aff182SThomas Petazzoni /* Set rxq buf size */ 892c5aff182SThomas Petazzoni static void mvneta_rxq_buf_size_set(struct mvneta_port *pp, 893c5aff182SThomas Petazzoni struct mvneta_rx_queue *rxq, 894c5aff182SThomas Petazzoni int buf_size) 895c5aff182SThomas Petazzoni { 896c5aff182SThomas Petazzoni u32 val; 897c5aff182SThomas Petazzoni 898c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_RXQ_SIZE_REG(rxq->id)); 899c5aff182SThomas Petazzoni 900c5aff182SThomas Petazzoni val &= ~MVNETA_RXQ_BUF_SIZE_MASK; 901c5aff182SThomas Petazzoni val |= ((buf_size >> 3) << MVNETA_RXQ_BUF_SIZE_SHIFT); 902c5aff182SThomas Petazzoni 903c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_RXQ_SIZE_REG(rxq->id), val); 904c5aff182SThomas Petazzoni } 905c5aff182SThomas Petazzoni 906c5aff182SThomas Petazzoni /* Disable buffer management (BM) */ 907c5aff182SThomas Petazzoni static void mvneta_rxq_bm_disable(struct mvneta_port *pp, 908c5aff182SThomas Petazzoni struct mvneta_rx_queue *rxq) 909c5aff182SThomas Petazzoni { 910c5aff182SThomas Petazzoni u32 val; 911c5aff182SThomas Petazzoni 912c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_RXQ_CONFIG_REG(rxq->id)); 913c5aff182SThomas Petazzoni val &= ~MVNETA_RXQ_HW_BUF_ALLOC; 914c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_RXQ_CONFIG_REG(rxq->id), val); 915c5aff182SThomas Petazzoni } 916c5aff182SThomas Petazzoni 917dc35a10fSMarcin Wojtas /* Enable buffer management (BM) */ 918dc35a10fSMarcin Wojtas static void mvneta_rxq_bm_enable(struct mvneta_port *pp, 919dc35a10fSMarcin Wojtas struct mvneta_rx_queue *rxq) 920dc35a10fSMarcin Wojtas { 921dc35a10fSMarcin Wojtas u32 val; 922dc35a10fSMarcin Wojtas 923dc35a10fSMarcin Wojtas val = mvreg_read(pp, MVNETA_RXQ_CONFIG_REG(rxq->id)); 924dc35a10fSMarcin Wojtas val |= MVNETA_RXQ_HW_BUF_ALLOC; 925dc35a10fSMarcin Wojtas mvreg_write(pp, MVNETA_RXQ_CONFIG_REG(rxq->id), val); 926dc35a10fSMarcin Wojtas } 927dc35a10fSMarcin Wojtas 928dc35a10fSMarcin Wojtas /* Notify HW about port's assignment of pool for bigger packets */ 929dc35a10fSMarcin Wojtas static void mvneta_rxq_long_pool_set(struct mvneta_port *pp, 930dc35a10fSMarcin Wojtas struct mvneta_rx_queue *rxq) 931dc35a10fSMarcin Wojtas { 932dc35a10fSMarcin Wojtas u32 val; 933dc35a10fSMarcin Wojtas 934dc35a10fSMarcin Wojtas val = mvreg_read(pp, MVNETA_RXQ_CONFIG_REG(rxq->id)); 935dc35a10fSMarcin Wojtas val &= ~MVNETA_RXQ_LONG_POOL_ID_MASK; 936dc35a10fSMarcin Wojtas val |= (pp->pool_long->id << MVNETA_RXQ_LONG_POOL_ID_SHIFT); 937dc35a10fSMarcin Wojtas 938dc35a10fSMarcin Wojtas mvreg_write(pp, MVNETA_RXQ_CONFIG_REG(rxq->id), val); 939dc35a10fSMarcin Wojtas } 940dc35a10fSMarcin Wojtas 941dc35a10fSMarcin Wojtas /* Notify HW about port's assignment of pool for smaller packets */ 942dc35a10fSMarcin Wojtas static void mvneta_rxq_short_pool_set(struct mvneta_port *pp, 943dc35a10fSMarcin Wojtas struct mvneta_rx_queue *rxq) 944dc35a10fSMarcin Wojtas { 945dc35a10fSMarcin Wojtas u32 val; 946dc35a10fSMarcin Wojtas 947dc35a10fSMarcin Wojtas val = mvreg_read(pp, MVNETA_RXQ_CONFIG_REG(rxq->id)); 948dc35a10fSMarcin Wojtas val &= ~MVNETA_RXQ_SHORT_POOL_ID_MASK; 949dc35a10fSMarcin Wojtas val |= (pp->pool_short->id << MVNETA_RXQ_SHORT_POOL_ID_SHIFT); 950dc35a10fSMarcin Wojtas 951dc35a10fSMarcin Wojtas mvreg_write(pp, MVNETA_RXQ_CONFIG_REG(rxq->id), val); 952dc35a10fSMarcin Wojtas } 953dc35a10fSMarcin Wojtas 954dc35a10fSMarcin Wojtas /* Set port's receive buffer size for assigned BM pool */ 955dc35a10fSMarcin Wojtas static inline void mvneta_bm_pool_bufsize_set(struct mvneta_port *pp, 956dc35a10fSMarcin Wojtas int buf_size, 957dc35a10fSMarcin Wojtas u8 pool_id) 958dc35a10fSMarcin Wojtas { 959dc35a10fSMarcin Wojtas u32 val; 960dc35a10fSMarcin Wojtas 961dc35a10fSMarcin Wojtas if (!IS_ALIGNED(buf_size, 8)) { 962dc35a10fSMarcin Wojtas dev_warn(pp->dev->dev.parent, 963dc35a10fSMarcin Wojtas "illegal buf_size value %d, round to %d\n", 964dc35a10fSMarcin Wojtas buf_size, ALIGN(buf_size, 8)); 965dc35a10fSMarcin Wojtas buf_size = ALIGN(buf_size, 8); 966dc35a10fSMarcin Wojtas } 967dc35a10fSMarcin Wojtas 968dc35a10fSMarcin Wojtas val = mvreg_read(pp, MVNETA_PORT_POOL_BUFFER_SZ_REG(pool_id)); 969dc35a10fSMarcin Wojtas val |= buf_size & MVNETA_PORT_POOL_BUFFER_SZ_MASK; 970dc35a10fSMarcin Wojtas mvreg_write(pp, MVNETA_PORT_POOL_BUFFER_SZ_REG(pool_id), val); 971dc35a10fSMarcin Wojtas } 972dc35a10fSMarcin Wojtas 973dc35a10fSMarcin Wojtas /* Configure MBUS window in order to enable access BM internal SRAM */ 974dc35a10fSMarcin Wojtas static int mvneta_mbus_io_win_set(struct mvneta_port *pp, u32 base, u32 wsize, 975dc35a10fSMarcin Wojtas u8 target, u8 attr) 976dc35a10fSMarcin Wojtas { 977dc35a10fSMarcin Wojtas u32 win_enable, win_protect; 978dc35a10fSMarcin Wojtas int i; 979dc35a10fSMarcin Wojtas 980dc35a10fSMarcin Wojtas win_enable = mvreg_read(pp, MVNETA_BASE_ADDR_ENABLE); 981dc35a10fSMarcin Wojtas 982dc35a10fSMarcin Wojtas if (pp->bm_win_id < 0) { 983dc35a10fSMarcin Wojtas /* Find first not occupied window */ 984dc35a10fSMarcin Wojtas for (i = 0; i < MVNETA_MAX_DECODE_WIN; i++) { 985dc35a10fSMarcin Wojtas if (win_enable & (1 << i)) { 986dc35a10fSMarcin Wojtas pp->bm_win_id = i; 987dc35a10fSMarcin Wojtas break; 988dc35a10fSMarcin Wojtas } 989dc35a10fSMarcin Wojtas } 990dc35a10fSMarcin Wojtas if (i == MVNETA_MAX_DECODE_WIN) 991dc35a10fSMarcin Wojtas return -ENOMEM; 992dc35a10fSMarcin Wojtas } else { 993dc35a10fSMarcin Wojtas i = pp->bm_win_id; 994dc35a10fSMarcin Wojtas } 995dc35a10fSMarcin Wojtas 996dc35a10fSMarcin Wojtas mvreg_write(pp, MVNETA_WIN_BASE(i), 0); 997dc35a10fSMarcin Wojtas mvreg_write(pp, MVNETA_WIN_SIZE(i), 0); 998dc35a10fSMarcin Wojtas 999dc35a10fSMarcin Wojtas if (i < 4) 1000dc35a10fSMarcin Wojtas mvreg_write(pp, MVNETA_WIN_REMAP(i), 0); 1001dc35a10fSMarcin Wojtas 1002dc35a10fSMarcin Wojtas mvreg_write(pp, MVNETA_WIN_BASE(i), (base & 0xffff0000) | 1003dc35a10fSMarcin Wojtas (attr << 8) | target); 1004dc35a10fSMarcin Wojtas 1005dc35a10fSMarcin Wojtas mvreg_write(pp, MVNETA_WIN_SIZE(i), (wsize - 1) & 0xffff0000); 1006dc35a10fSMarcin Wojtas 1007dc35a10fSMarcin Wojtas win_protect = mvreg_read(pp, MVNETA_ACCESS_PROTECT_ENABLE); 1008dc35a10fSMarcin Wojtas win_protect |= 3 << (2 * i); 1009dc35a10fSMarcin Wojtas mvreg_write(pp, MVNETA_ACCESS_PROTECT_ENABLE, win_protect); 1010dc35a10fSMarcin Wojtas 1011dc35a10fSMarcin Wojtas win_enable &= ~(1 << i); 1012dc35a10fSMarcin Wojtas mvreg_write(pp, MVNETA_BASE_ADDR_ENABLE, win_enable); 1013dc35a10fSMarcin Wojtas 1014dc35a10fSMarcin Wojtas return 0; 1015dc35a10fSMarcin Wojtas } 1016dc35a10fSMarcin Wojtas 10172636ac3cSMarcin Wojtas static int mvneta_bm_port_mbus_init(struct mvneta_port *pp) 1018dc35a10fSMarcin Wojtas { 10192636ac3cSMarcin Wojtas u32 wsize; 1020dc35a10fSMarcin Wojtas u8 target, attr; 1021dc35a10fSMarcin Wojtas int err; 1022dc35a10fSMarcin Wojtas 1023dc35a10fSMarcin Wojtas /* Get BM window information */ 1024dc35a10fSMarcin Wojtas err = mvebu_mbus_get_io_win_info(pp->bm_priv->bppi_phys_addr, &wsize, 1025dc35a10fSMarcin Wojtas &target, &attr); 1026dc35a10fSMarcin Wojtas if (err < 0) 1027dc35a10fSMarcin Wojtas return err; 1028dc35a10fSMarcin Wojtas 1029dc35a10fSMarcin Wojtas pp->bm_win_id = -1; 1030dc35a10fSMarcin Wojtas 1031dc35a10fSMarcin Wojtas /* Open NETA -> BM window */ 1032dc35a10fSMarcin Wojtas err = mvneta_mbus_io_win_set(pp, pp->bm_priv->bppi_phys_addr, wsize, 1033dc35a10fSMarcin Wojtas target, attr); 1034dc35a10fSMarcin Wojtas if (err < 0) { 1035dc35a10fSMarcin Wojtas netdev_info(pp->dev, "fail to configure mbus window to BM\n"); 1036dc35a10fSMarcin Wojtas return err; 1037dc35a10fSMarcin Wojtas } 10382636ac3cSMarcin Wojtas return 0; 10392636ac3cSMarcin Wojtas } 10402636ac3cSMarcin Wojtas 10412636ac3cSMarcin Wojtas /* Assign and initialize pools for port. In case of fail 10422636ac3cSMarcin Wojtas * buffer manager will remain disabled for current port. 10432636ac3cSMarcin Wojtas */ 10442636ac3cSMarcin Wojtas static int mvneta_bm_port_init(struct platform_device *pdev, 10452636ac3cSMarcin Wojtas struct mvneta_port *pp) 10462636ac3cSMarcin Wojtas { 10472636ac3cSMarcin Wojtas struct device_node *dn = pdev->dev.of_node; 10482636ac3cSMarcin Wojtas u32 long_pool_id, short_pool_id; 10492636ac3cSMarcin Wojtas 10502636ac3cSMarcin Wojtas if (!pp->neta_armada3700) { 10512636ac3cSMarcin Wojtas int ret; 10522636ac3cSMarcin Wojtas 10532636ac3cSMarcin Wojtas ret = mvneta_bm_port_mbus_init(pp); 10542636ac3cSMarcin Wojtas if (ret) 10552636ac3cSMarcin Wojtas return ret; 10562636ac3cSMarcin Wojtas } 1057dc35a10fSMarcin Wojtas 1058dc35a10fSMarcin Wojtas if (of_property_read_u32(dn, "bm,pool-long", &long_pool_id)) { 1059dc35a10fSMarcin Wojtas netdev_info(pp->dev, "missing long pool id\n"); 1060dc35a10fSMarcin Wojtas return -EINVAL; 1061dc35a10fSMarcin Wojtas } 1062dc35a10fSMarcin Wojtas 1063dc35a10fSMarcin Wojtas /* Create port's long pool depending on mtu */ 1064dc35a10fSMarcin Wojtas pp->pool_long = mvneta_bm_pool_use(pp->bm_priv, long_pool_id, 1065dc35a10fSMarcin Wojtas MVNETA_BM_LONG, pp->id, 1066dc35a10fSMarcin Wojtas MVNETA_RX_PKT_SIZE(pp->dev->mtu)); 1067dc35a10fSMarcin Wojtas if (!pp->pool_long) { 1068dc35a10fSMarcin Wojtas netdev_info(pp->dev, "fail to obtain long pool for port\n"); 1069dc35a10fSMarcin Wojtas return -ENOMEM; 1070dc35a10fSMarcin Wojtas } 1071dc35a10fSMarcin Wojtas 1072dc35a10fSMarcin Wojtas pp->pool_long->port_map |= 1 << pp->id; 1073dc35a10fSMarcin Wojtas 1074dc35a10fSMarcin Wojtas mvneta_bm_pool_bufsize_set(pp, pp->pool_long->buf_size, 1075dc35a10fSMarcin Wojtas pp->pool_long->id); 1076dc35a10fSMarcin Wojtas 1077dc35a10fSMarcin Wojtas /* If short pool id is not defined, assume using single pool */ 1078dc35a10fSMarcin Wojtas if (of_property_read_u32(dn, "bm,pool-short", &short_pool_id)) 1079dc35a10fSMarcin Wojtas short_pool_id = long_pool_id; 1080dc35a10fSMarcin Wojtas 1081dc35a10fSMarcin Wojtas /* Create port's short pool */ 1082dc35a10fSMarcin Wojtas pp->pool_short = mvneta_bm_pool_use(pp->bm_priv, short_pool_id, 1083dc35a10fSMarcin Wojtas MVNETA_BM_SHORT, pp->id, 1084dc35a10fSMarcin Wojtas MVNETA_BM_SHORT_PKT_SIZE); 1085dc35a10fSMarcin Wojtas if (!pp->pool_short) { 1086dc35a10fSMarcin Wojtas netdev_info(pp->dev, "fail to obtain short pool for port\n"); 1087dc35a10fSMarcin Wojtas mvneta_bm_pool_destroy(pp->bm_priv, pp->pool_long, 1 << pp->id); 1088dc35a10fSMarcin Wojtas return -ENOMEM; 1089dc35a10fSMarcin Wojtas } 1090dc35a10fSMarcin Wojtas 1091dc35a10fSMarcin Wojtas if (short_pool_id != long_pool_id) { 1092dc35a10fSMarcin Wojtas pp->pool_short->port_map |= 1 << pp->id; 1093dc35a10fSMarcin Wojtas mvneta_bm_pool_bufsize_set(pp, pp->pool_short->buf_size, 1094dc35a10fSMarcin Wojtas pp->pool_short->id); 1095dc35a10fSMarcin Wojtas } 1096dc35a10fSMarcin Wojtas 1097dc35a10fSMarcin Wojtas return 0; 1098dc35a10fSMarcin Wojtas } 1099dc35a10fSMarcin Wojtas 1100dc35a10fSMarcin Wojtas /* Update settings of a pool for bigger packets */ 1101dc35a10fSMarcin Wojtas static void mvneta_bm_update_mtu(struct mvneta_port *pp, int mtu) 1102dc35a10fSMarcin Wojtas { 1103dc35a10fSMarcin Wojtas struct mvneta_bm_pool *bm_pool = pp->pool_long; 1104baa11ebcSGregory CLEMENT struct hwbm_pool *hwbm_pool = &bm_pool->hwbm_pool; 1105dc35a10fSMarcin Wojtas int num; 1106dc35a10fSMarcin Wojtas 1107dc35a10fSMarcin Wojtas /* Release all buffers from long pool */ 1108dc35a10fSMarcin Wojtas mvneta_bm_bufs_free(pp->bm_priv, bm_pool, 1 << pp->id); 1109baa11ebcSGregory CLEMENT if (hwbm_pool->buf_num) { 1110dc35a10fSMarcin Wojtas WARN(1, "cannot free all buffers in pool %d\n", 1111dc35a10fSMarcin Wojtas bm_pool->id); 1112dc35a10fSMarcin Wojtas goto bm_mtu_err; 1113dc35a10fSMarcin Wojtas } 1114dc35a10fSMarcin Wojtas 1115dc35a10fSMarcin Wojtas bm_pool->pkt_size = MVNETA_RX_PKT_SIZE(mtu); 1116dc35a10fSMarcin Wojtas bm_pool->buf_size = MVNETA_RX_BUF_SIZE(bm_pool->pkt_size); 1117baa11ebcSGregory CLEMENT hwbm_pool->frag_size = SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) + 1118dc35a10fSMarcin Wojtas SKB_DATA_ALIGN(MVNETA_RX_BUF_SIZE(bm_pool->pkt_size)); 1119dc35a10fSMarcin Wojtas 1120dc35a10fSMarcin Wojtas /* Fill entire long pool */ 1121baa11ebcSGregory CLEMENT num = hwbm_pool_add(hwbm_pool, hwbm_pool->size, GFP_ATOMIC); 1122baa11ebcSGregory CLEMENT if (num != hwbm_pool->size) { 1123dc35a10fSMarcin Wojtas WARN(1, "pool %d: %d of %d allocated\n", 1124baa11ebcSGregory CLEMENT bm_pool->id, num, hwbm_pool->size); 1125dc35a10fSMarcin Wojtas goto bm_mtu_err; 1126dc35a10fSMarcin Wojtas } 1127dc35a10fSMarcin Wojtas mvneta_bm_pool_bufsize_set(pp, bm_pool->buf_size, bm_pool->id); 1128dc35a10fSMarcin Wojtas 1129dc35a10fSMarcin Wojtas return; 1130dc35a10fSMarcin Wojtas 1131dc35a10fSMarcin Wojtas bm_mtu_err: 1132dc35a10fSMarcin Wojtas mvneta_bm_pool_destroy(pp->bm_priv, pp->pool_long, 1 << pp->id); 1133dc35a10fSMarcin Wojtas mvneta_bm_pool_destroy(pp->bm_priv, pp->pool_short, 1 << pp->id); 1134dc35a10fSMarcin Wojtas 1135dc35a10fSMarcin Wojtas pp->bm_priv = NULL; 1136dc35a10fSMarcin Wojtas mvreg_write(pp, MVNETA_ACC_MODE, MVNETA_ACC_MODE_EXT1); 1137dc35a10fSMarcin Wojtas netdev_info(pp->dev, "fail to update MTU, fall back to software BM\n"); 1138dc35a10fSMarcin Wojtas } 1139dc35a10fSMarcin Wojtas 1140c5aff182SThomas Petazzoni /* Start the Ethernet port RX and TX activity */ 1141c5aff182SThomas Petazzoni static void mvneta_port_up(struct mvneta_port *pp) 1142c5aff182SThomas Petazzoni { 1143c5aff182SThomas Petazzoni int queue; 1144c5aff182SThomas Petazzoni u32 q_map; 1145c5aff182SThomas Petazzoni 1146c5aff182SThomas Petazzoni /* Enable all initialized TXs. */ 1147c5aff182SThomas Petazzoni q_map = 0; 1148c5aff182SThomas Petazzoni for (queue = 0; queue < txq_number; queue++) { 1149c5aff182SThomas Petazzoni struct mvneta_tx_queue *txq = &pp->txqs[queue]; 1150f95936ccSMarkus Elfring if (txq->descs) 1151c5aff182SThomas Petazzoni q_map |= (1 << queue); 1152c5aff182SThomas Petazzoni } 1153c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_TXQ_CMD, q_map); 1154c5aff182SThomas Petazzoni 1155e81b5e01SYelena Krivosheev q_map = 0; 1156c5aff182SThomas Petazzoni /* Enable all initialized RXQs. */ 11572dcf75e2SGregory CLEMENT for (queue = 0; queue < rxq_number; queue++) { 11582dcf75e2SGregory CLEMENT struct mvneta_rx_queue *rxq = &pp->rxqs[queue]; 11592dcf75e2SGregory CLEMENT 1160f95936ccSMarkus Elfring if (rxq->descs) 11612dcf75e2SGregory CLEMENT q_map |= (1 << queue); 11622dcf75e2SGregory CLEMENT } 11632dcf75e2SGregory CLEMENT mvreg_write(pp, MVNETA_RXQ_CMD, q_map); 1164c5aff182SThomas Petazzoni } 1165c5aff182SThomas Petazzoni 1166c5aff182SThomas Petazzoni /* Stop the Ethernet port activity */ 1167c5aff182SThomas Petazzoni static void mvneta_port_down(struct mvneta_port *pp) 1168c5aff182SThomas Petazzoni { 1169c5aff182SThomas Petazzoni u32 val; 1170c5aff182SThomas Petazzoni int count; 1171c5aff182SThomas Petazzoni 1172c5aff182SThomas Petazzoni /* Stop Rx port activity. Check port Rx activity. */ 1173c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_RXQ_CMD) & MVNETA_RXQ_ENABLE_MASK; 1174c5aff182SThomas Petazzoni 1175c5aff182SThomas Petazzoni /* Issue stop command for active channels only */ 1176c5aff182SThomas Petazzoni if (val != 0) 1177c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_RXQ_CMD, 1178c5aff182SThomas Petazzoni val << MVNETA_RXQ_DISABLE_SHIFT); 1179c5aff182SThomas Petazzoni 1180c5aff182SThomas Petazzoni /* Wait for all Rx activity to terminate. */ 1181c5aff182SThomas Petazzoni count = 0; 1182c5aff182SThomas Petazzoni do { 1183c5aff182SThomas Petazzoni if (count++ >= MVNETA_RX_DISABLE_TIMEOUT_MSEC) { 1184c5aff182SThomas Petazzoni netdev_warn(pp->dev, 11850838abb3SDmitri Epshtein "TIMEOUT for RX stopped ! rx_queue_cmd: 0x%08x\n", 1186c5aff182SThomas Petazzoni val); 1187c5aff182SThomas Petazzoni break; 1188c5aff182SThomas Petazzoni } 1189c5aff182SThomas Petazzoni mdelay(1); 1190c5aff182SThomas Petazzoni 1191c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_RXQ_CMD); 1192a3703fb3SDmitri Epshtein } while (val & MVNETA_RXQ_ENABLE_MASK); 1193c5aff182SThomas Petazzoni 1194c5aff182SThomas Petazzoni /* Stop Tx port activity. Check port Tx activity. Issue stop 11956a20c175SThomas Petazzoni * command for active channels only 11966a20c175SThomas Petazzoni */ 1197c5aff182SThomas Petazzoni val = (mvreg_read(pp, MVNETA_TXQ_CMD)) & MVNETA_TXQ_ENABLE_MASK; 1198c5aff182SThomas Petazzoni 1199c5aff182SThomas Petazzoni if (val != 0) 1200c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_TXQ_CMD, 1201c5aff182SThomas Petazzoni (val << MVNETA_TXQ_DISABLE_SHIFT)); 1202c5aff182SThomas Petazzoni 1203c5aff182SThomas Petazzoni /* Wait for all Tx activity to terminate. */ 1204c5aff182SThomas Petazzoni count = 0; 1205c5aff182SThomas Petazzoni do { 1206c5aff182SThomas Petazzoni if (count++ >= MVNETA_TX_DISABLE_TIMEOUT_MSEC) { 1207c5aff182SThomas Petazzoni netdev_warn(pp->dev, 1208c5aff182SThomas Petazzoni "TIMEOUT for TX stopped status=0x%08x\n", 1209c5aff182SThomas Petazzoni val); 1210c5aff182SThomas Petazzoni break; 1211c5aff182SThomas Petazzoni } 1212c5aff182SThomas Petazzoni mdelay(1); 1213c5aff182SThomas Petazzoni 1214c5aff182SThomas Petazzoni /* Check TX Command reg that all Txqs are stopped */ 1215c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_TXQ_CMD); 1216c5aff182SThomas Petazzoni 1217a3703fb3SDmitri Epshtein } while (val & MVNETA_TXQ_ENABLE_MASK); 1218c5aff182SThomas Petazzoni 1219c5aff182SThomas Petazzoni /* Double check to verify that TX FIFO is empty */ 1220c5aff182SThomas Petazzoni count = 0; 1221c5aff182SThomas Petazzoni do { 1222c5aff182SThomas Petazzoni if (count++ >= MVNETA_TX_FIFO_EMPTY_TIMEOUT) { 1223c5aff182SThomas Petazzoni netdev_warn(pp->dev, 12240838abb3SDmitri Epshtein "TX FIFO empty timeout status=0x%08x\n", 1225c5aff182SThomas Petazzoni val); 1226c5aff182SThomas Petazzoni break; 1227c5aff182SThomas Petazzoni } 1228c5aff182SThomas Petazzoni mdelay(1); 1229c5aff182SThomas Petazzoni 1230c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_PORT_STATUS); 1231c5aff182SThomas Petazzoni } while (!(val & MVNETA_TX_FIFO_EMPTY) && 1232c5aff182SThomas Petazzoni (val & MVNETA_TX_IN_PRGRS)); 1233c5aff182SThomas Petazzoni 1234c5aff182SThomas Petazzoni udelay(200); 1235c5aff182SThomas Petazzoni } 1236c5aff182SThomas Petazzoni 1237c5aff182SThomas Petazzoni /* Enable the port by setting the port enable bit of the MAC control register */ 1238c5aff182SThomas Petazzoni static void mvneta_port_enable(struct mvneta_port *pp) 1239c5aff182SThomas Petazzoni { 1240c5aff182SThomas Petazzoni u32 val; 1241c5aff182SThomas Petazzoni 1242c5aff182SThomas Petazzoni /* Enable port */ 1243c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_GMAC_CTRL_0); 1244c5aff182SThomas Petazzoni val |= MVNETA_GMAC0_PORT_ENABLE; 1245c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_GMAC_CTRL_0, val); 1246c5aff182SThomas Petazzoni } 1247c5aff182SThomas Petazzoni 1248c5aff182SThomas Petazzoni /* Disable the port and wait for about 200 usec before retuning */ 1249c5aff182SThomas Petazzoni static void mvneta_port_disable(struct mvneta_port *pp) 1250c5aff182SThomas Petazzoni { 1251c5aff182SThomas Petazzoni u32 val; 1252c5aff182SThomas Petazzoni 1253c5aff182SThomas Petazzoni /* Reset the Enable bit in the Serial Control Register */ 1254c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_GMAC_CTRL_0); 1255c5aff182SThomas Petazzoni val &= ~MVNETA_GMAC0_PORT_ENABLE; 1256c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_GMAC_CTRL_0, val); 1257c5aff182SThomas Petazzoni 1258c5aff182SThomas Petazzoni udelay(200); 1259c5aff182SThomas Petazzoni } 1260c5aff182SThomas Petazzoni 1261c5aff182SThomas Petazzoni /* Multicast tables methods */ 1262c5aff182SThomas Petazzoni 1263c5aff182SThomas Petazzoni /* Set all entries in Unicast MAC Table; queue==-1 means reject all */ 1264c5aff182SThomas Petazzoni static void mvneta_set_ucast_table(struct mvneta_port *pp, int queue) 1265c5aff182SThomas Petazzoni { 1266c5aff182SThomas Petazzoni int offset; 1267c5aff182SThomas Petazzoni u32 val; 1268c5aff182SThomas Petazzoni 1269c5aff182SThomas Petazzoni if (queue == -1) { 1270c5aff182SThomas Petazzoni val = 0; 1271c5aff182SThomas Petazzoni } else { 1272c5aff182SThomas Petazzoni val = 0x1 | (queue << 1); 1273c5aff182SThomas Petazzoni val |= (val << 24) | (val << 16) | (val << 8); 1274c5aff182SThomas Petazzoni } 1275c5aff182SThomas Petazzoni 1276c5aff182SThomas Petazzoni for (offset = 0; offset <= 0xc; offset += 4) 1277c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_DA_FILT_UCAST_BASE + offset, val); 1278c5aff182SThomas Petazzoni } 1279c5aff182SThomas Petazzoni 1280c5aff182SThomas Petazzoni /* Set all entries in Special Multicast MAC Table; queue==-1 means reject all */ 1281c5aff182SThomas Petazzoni static void mvneta_set_special_mcast_table(struct mvneta_port *pp, int queue) 1282c5aff182SThomas Petazzoni { 1283c5aff182SThomas Petazzoni int offset; 1284c5aff182SThomas Petazzoni u32 val; 1285c5aff182SThomas Petazzoni 1286c5aff182SThomas Petazzoni if (queue == -1) { 1287c5aff182SThomas Petazzoni val = 0; 1288c5aff182SThomas Petazzoni } else { 1289c5aff182SThomas Petazzoni val = 0x1 | (queue << 1); 1290c5aff182SThomas Petazzoni val |= (val << 24) | (val << 16) | (val << 8); 1291c5aff182SThomas Petazzoni } 1292c5aff182SThomas Petazzoni 1293c5aff182SThomas Petazzoni for (offset = 0; offset <= 0xfc; offset += 4) 1294c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_DA_FILT_SPEC_MCAST + offset, val); 1295c5aff182SThomas Petazzoni 1296c5aff182SThomas Petazzoni } 1297c5aff182SThomas Petazzoni 1298c5aff182SThomas Petazzoni /* Set all entries in Other Multicast MAC Table. queue==-1 means reject all */ 1299c5aff182SThomas Petazzoni static void mvneta_set_other_mcast_table(struct mvneta_port *pp, int queue) 1300c5aff182SThomas Petazzoni { 1301c5aff182SThomas Petazzoni int offset; 1302c5aff182SThomas Petazzoni u32 val; 1303c5aff182SThomas Petazzoni 1304c5aff182SThomas Petazzoni if (queue == -1) { 1305c5aff182SThomas Petazzoni memset(pp->mcast_count, 0, sizeof(pp->mcast_count)); 1306c5aff182SThomas Petazzoni val = 0; 1307c5aff182SThomas Petazzoni } else { 1308c5aff182SThomas Petazzoni memset(pp->mcast_count, 1, sizeof(pp->mcast_count)); 1309c5aff182SThomas Petazzoni val = 0x1 | (queue << 1); 1310c5aff182SThomas Petazzoni val |= (val << 24) | (val << 16) | (val << 8); 1311c5aff182SThomas Petazzoni } 1312c5aff182SThomas Petazzoni 1313c5aff182SThomas Petazzoni for (offset = 0; offset <= 0xfc; offset += 4) 1314c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_DA_FILT_OTH_MCAST + offset, val); 1315c5aff182SThomas Petazzoni } 1316c5aff182SThomas Petazzoni 1317db488c10SGregory CLEMENT static void mvneta_percpu_unmask_interrupt(void *arg) 1318db488c10SGregory CLEMENT { 1319db488c10SGregory CLEMENT struct mvneta_port *pp = arg; 1320db488c10SGregory CLEMENT 1321db488c10SGregory CLEMENT /* All the queue are unmasked, but actually only the ones 1322db488c10SGregory CLEMENT * mapped to this CPU will be unmasked 1323db488c10SGregory CLEMENT */ 1324db488c10SGregory CLEMENT mvreg_write(pp, MVNETA_INTR_NEW_MASK, 1325db488c10SGregory CLEMENT MVNETA_RX_INTR_MASK_ALL | 1326db488c10SGregory CLEMENT MVNETA_TX_INTR_MASK_ALL | 1327db488c10SGregory CLEMENT MVNETA_MISCINTR_INTR_MASK); 1328db488c10SGregory CLEMENT } 1329db488c10SGregory CLEMENT 1330db488c10SGregory CLEMENT static void mvneta_percpu_mask_interrupt(void *arg) 1331db488c10SGregory CLEMENT { 1332db488c10SGregory CLEMENT struct mvneta_port *pp = arg; 1333db488c10SGregory CLEMENT 1334db488c10SGregory CLEMENT /* All the queue are masked, but actually only the ones 1335db488c10SGregory CLEMENT * mapped to this CPU will be masked 1336db488c10SGregory CLEMENT */ 1337db488c10SGregory CLEMENT mvreg_write(pp, MVNETA_INTR_NEW_MASK, 0); 1338db488c10SGregory CLEMENT mvreg_write(pp, MVNETA_INTR_OLD_MASK, 0); 1339db488c10SGregory CLEMENT mvreg_write(pp, MVNETA_INTR_MISC_MASK, 0); 1340db488c10SGregory CLEMENT } 1341db488c10SGregory CLEMENT 1342db488c10SGregory CLEMENT static void mvneta_percpu_clear_intr_cause(void *arg) 1343db488c10SGregory CLEMENT { 1344db488c10SGregory CLEMENT struct mvneta_port *pp = arg; 1345db488c10SGregory CLEMENT 1346db488c10SGregory CLEMENT /* All the queue are cleared, but actually only the ones 1347db488c10SGregory CLEMENT * mapped to this CPU will be cleared 1348db488c10SGregory CLEMENT */ 1349db488c10SGregory CLEMENT mvreg_write(pp, MVNETA_INTR_NEW_CAUSE, 0); 1350db488c10SGregory CLEMENT mvreg_write(pp, MVNETA_INTR_MISC_CAUSE, 0); 1351db488c10SGregory CLEMENT mvreg_write(pp, MVNETA_INTR_OLD_CAUSE, 0); 1352db488c10SGregory CLEMENT } 1353db488c10SGregory CLEMENT 1354c5aff182SThomas Petazzoni /* This method sets defaults to the NETA port: 1355c5aff182SThomas Petazzoni * Clears interrupt Cause and Mask registers. 1356c5aff182SThomas Petazzoni * Clears all MAC tables. 1357c5aff182SThomas Petazzoni * Sets defaults to all registers. 1358c5aff182SThomas Petazzoni * Resets RX and TX descriptor rings. 1359c5aff182SThomas Petazzoni * Resets PHY. 1360c5aff182SThomas Petazzoni * This method can be called after mvneta_port_down() to return the port 1361c5aff182SThomas Petazzoni * settings to defaults. 1362c5aff182SThomas Petazzoni */ 1363c5aff182SThomas Petazzoni static void mvneta_defaults_set(struct mvneta_port *pp) 1364c5aff182SThomas Petazzoni { 1365c5aff182SThomas Petazzoni int cpu; 1366c5aff182SThomas Petazzoni int queue; 1367c5aff182SThomas Petazzoni u32 val; 13682dcf75e2SGregory CLEMENT int max_cpu = num_present_cpus(); 1369c5aff182SThomas Petazzoni 1370c5aff182SThomas Petazzoni /* Clear all Cause registers */ 1371db488c10SGregory CLEMENT on_each_cpu(mvneta_percpu_clear_intr_cause, pp, true); 1372c5aff182SThomas Petazzoni 1373c5aff182SThomas Petazzoni /* Mask all interrupts */ 1374db488c10SGregory CLEMENT on_each_cpu(mvneta_percpu_mask_interrupt, pp, true); 1375c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_INTR_ENABLE, 0); 1376c5aff182SThomas Petazzoni 1377c5aff182SThomas Petazzoni /* Enable MBUS Retry bit16 */ 1378c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_MBUS_RETRY, 0x20); 1379c5aff182SThomas Petazzoni 138050bf8cb6SGregory CLEMENT /* Set CPU queue access map. CPUs are assigned to the RX and 138150bf8cb6SGregory CLEMENT * TX queues modulo their number. If there is only one TX 138250bf8cb6SGregory CLEMENT * queue then it is assigned to the CPU associated to the 138350bf8cb6SGregory CLEMENT * default RX queue. 13846a20c175SThomas Petazzoni */ 13852dcf75e2SGregory CLEMENT for_each_present_cpu(cpu) { 13862dcf75e2SGregory CLEMENT int rxq_map = 0, txq_map = 0; 138750bf8cb6SGregory CLEMENT int rxq, txq; 13882636ac3cSMarcin Wojtas if (!pp->neta_armada3700) { 13892dcf75e2SGregory CLEMENT for (rxq = 0; rxq < rxq_number; rxq++) 13902dcf75e2SGregory CLEMENT if ((rxq % max_cpu) == cpu) 13912dcf75e2SGregory CLEMENT rxq_map |= MVNETA_CPU_RXQ_ACCESS(rxq); 13922dcf75e2SGregory CLEMENT 139350bf8cb6SGregory CLEMENT for (txq = 0; txq < txq_number; txq++) 139450bf8cb6SGregory CLEMENT if ((txq % max_cpu) == cpu) 139550bf8cb6SGregory CLEMENT txq_map |= MVNETA_CPU_TXQ_ACCESS(txq); 139650bf8cb6SGregory CLEMENT 139750bf8cb6SGregory CLEMENT /* With only one TX queue we configure a special case 139850bf8cb6SGregory CLEMENT * which will allow to get all the irq on a single 139950bf8cb6SGregory CLEMENT * CPU 140050bf8cb6SGregory CLEMENT */ 140150bf8cb6SGregory CLEMENT if (txq_number == 1) 140250bf8cb6SGregory CLEMENT txq_map = (cpu == pp->rxq_def) ? 140350bf8cb6SGregory CLEMENT MVNETA_CPU_TXQ_ACCESS(1) : 0; 14042dcf75e2SGregory CLEMENT 14052636ac3cSMarcin Wojtas } else { 14062636ac3cSMarcin Wojtas txq_map = MVNETA_CPU_TXQ_ACCESS_ALL_MASK; 14072636ac3cSMarcin Wojtas rxq_map = MVNETA_CPU_RXQ_ACCESS_ALL_MASK; 14082636ac3cSMarcin Wojtas } 14092636ac3cSMarcin Wojtas 14102dcf75e2SGregory CLEMENT mvreg_write(pp, MVNETA_CPU_MAP(cpu), rxq_map | txq_map); 14112dcf75e2SGregory CLEMENT } 1412c5aff182SThomas Petazzoni 1413c5aff182SThomas Petazzoni /* Reset RX and TX DMAs */ 1414c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_PORT_RX_RESET, MVNETA_PORT_RX_DMA_RESET); 1415c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_PORT_TX_RESET, MVNETA_PORT_TX_DMA_RESET); 1416c5aff182SThomas Petazzoni 1417c5aff182SThomas Petazzoni /* Disable Legacy WRR, Disable EJP, Release from reset */ 1418c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_TXQ_CMD_1, 0); 1419c5aff182SThomas Petazzoni for (queue = 0; queue < txq_number; queue++) { 1420c5aff182SThomas Petazzoni mvreg_write(pp, MVETH_TXQ_TOKEN_COUNT_REG(queue), 0); 1421c5aff182SThomas Petazzoni mvreg_write(pp, MVETH_TXQ_TOKEN_CFG_REG(queue), 0); 1422c5aff182SThomas Petazzoni } 1423c5aff182SThomas Petazzoni 1424c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_PORT_TX_RESET, 0); 1425c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_PORT_RX_RESET, 0); 1426c5aff182SThomas Petazzoni 1427c5aff182SThomas Petazzoni /* Set Port Acceleration Mode */ 1428dc35a10fSMarcin Wojtas if (pp->bm_priv) 1429dc35a10fSMarcin Wojtas /* HW buffer management + legacy parser */ 1430dc35a10fSMarcin Wojtas val = MVNETA_ACC_MODE_EXT2; 1431dc35a10fSMarcin Wojtas else 1432dc35a10fSMarcin Wojtas /* SW buffer management + legacy parser */ 1433dc35a10fSMarcin Wojtas val = MVNETA_ACC_MODE_EXT1; 1434c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_ACC_MODE, val); 1435c5aff182SThomas Petazzoni 1436dc35a10fSMarcin Wojtas if (pp->bm_priv) 1437dc35a10fSMarcin Wojtas mvreg_write(pp, MVNETA_BM_ADDRESS, pp->bm_priv->bppi_phys_addr); 1438dc35a10fSMarcin Wojtas 1439c5aff182SThomas Petazzoni /* Update val of portCfg register accordingly with all RxQueue types */ 144090b74c01SGregory CLEMENT val = MVNETA_PORT_CONFIG_DEFL_VALUE(pp->rxq_def); 1441c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_PORT_CONFIG, val); 1442c5aff182SThomas Petazzoni 1443c5aff182SThomas Petazzoni val = 0; 1444c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_PORT_CONFIG_EXTEND, val); 1445c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_RX_MIN_FRAME_SIZE, 64); 1446c5aff182SThomas Petazzoni 1447c5aff182SThomas Petazzoni /* Build PORT_SDMA_CONFIG_REG */ 1448c5aff182SThomas Petazzoni val = 0; 1449c5aff182SThomas Petazzoni 1450c5aff182SThomas Petazzoni /* Default burst size */ 1451c5aff182SThomas Petazzoni val |= MVNETA_TX_BRST_SZ_MASK(MVNETA_SDMA_BRST_SIZE_16); 1452c5aff182SThomas Petazzoni val |= MVNETA_RX_BRST_SZ_MASK(MVNETA_SDMA_BRST_SIZE_16); 14539ad8fef6SThomas Petazzoni val |= MVNETA_RX_NO_DATA_SWAP | MVNETA_TX_NO_DATA_SWAP; 1454c5aff182SThomas Petazzoni 14559ad8fef6SThomas Petazzoni #if defined(__BIG_ENDIAN) 14569ad8fef6SThomas Petazzoni val |= MVNETA_DESC_SWAP; 14579ad8fef6SThomas Petazzoni #endif 1458c5aff182SThomas Petazzoni 1459c5aff182SThomas Petazzoni /* Assign port SDMA configuration */ 1460c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_SDMA_CONFIG, val); 1461c5aff182SThomas Petazzoni 146271408602SThomas Petazzoni /* Disable PHY polling in hardware, since we're using the 146371408602SThomas Petazzoni * kernel phylib to do this. 146471408602SThomas Petazzoni */ 146571408602SThomas Petazzoni val = mvreg_read(pp, MVNETA_UNIT_CONTROL); 146671408602SThomas Petazzoni val &= ~MVNETA_PHY_POLLING_ENABLE; 146771408602SThomas Petazzoni mvreg_write(pp, MVNETA_UNIT_CONTROL, val); 146871408602SThomas Petazzoni 1469c5aff182SThomas Petazzoni mvneta_set_ucast_table(pp, -1); 1470c5aff182SThomas Petazzoni mvneta_set_special_mcast_table(pp, -1); 1471c5aff182SThomas Petazzoni mvneta_set_other_mcast_table(pp, -1); 1472c5aff182SThomas Petazzoni 1473c5aff182SThomas Petazzoni /* Set port interrupt enable register - default enable all */ 1474c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_INTR_ENABLE, 1475c5aff182SThomas Petazzoni (MVNETA_RXQ_INTR_ENABLE_ALL_MASK 1476c5aff182SThomas Petazzoni | MVNETA_TXQ_INTR_ENABLE_ALL_MASK)); 1477e483911fSAndrew Lunn 1478e483911fSAndrew Lunn mvneta_mib_counters_clear(pp); 1479c5aff182SThomas Petazzoni } 1480c5aff182SThomas Petazzoni 1481c5aff182SThomas Petazzoni /* Set max sizes for tx queues */ 1482c5aff182SThomas Petazzoni static void mvneta_txq_max_tx_size_set(struct mvneta_port *pp, int max_tx_size) 1483c5aff182SThomas Petazzoni 1484c5aff182SThomas Petazzoni { 1485c5aff182SThomas Petazzoni u32 val, size, mtu; 1486c5aff182SThomas Petazzoni int queue; 1487c5aff182SThomas Petazzoni 1488c5aff182SThomas Petazzoni mtu = max_tx_size * 8; 1489c5aff182SThomas Petazzoni if (mtu > MVNETA_TX_MTU_MAX) 1490c5aff182SThomas Petazzoni mtu = MVNETA_TX_MTU_MAX; 1491c5aff182SThomas Petazzoni 1492c5aff182SThomas Petazzoni /* Set MTU */ 1493c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_TX_MTU); 1494c5aff182SThomas Petazzoni val &= ~MVNETA_TX_MTU_MAX; 1495c5aff182SThomas Petazzoni val |= mtu; 1496c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_TX_MTU, val); 1497c5aff182SThomas Petazzoni 1498c5aff182SThomas Petazzoni /* TX token size and all TXQs token size must be larger that MTU */ 1499c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_TX_TOKEN_SIZE); 1500c5aff182SThomas Petazzoni 1501c5aff182SThomas Petazzoni size = val & MVNETA_TX_TOKEN_SIZE_MAX; 1502c5aff182SThomas Petazzoni if (size < mtu) { 1503c5aff182SThomas Petazzoni size = mtu; 1504c5aff182SThomas Petazzoni val &= ~MVNETA_TX_TOKEN_SIZE_MAX; 1505c5aff182SThomas Petazzoni val |= size; 1506c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_TX_TOKEN_SIZE, val); 1507c5aff182SThomas Petazzoni } 1508c5aff182SThomas Petazzoni for (queue = 0; queue < txq_number; queue++) { 1509c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_TXQ_TOKEN_SIZE_REG(queue)); 1510c5aff182SThomas Petazzoni 1511c5aff182SThomas Petazzoni size = val & MVNETA_TXQ_TOKEN_SIZE_MAX; 1512c5aff182SThomas Petazzoni if (size < mtu) { 1513c5aff182SThomas Petazzoni size = mtu; 1514c5aff182SThomas Petazzoni val &= ~MVNETA_TXQ_TOKEN_SIZE_MAX; 1515c5aff182SThomas Petazzoni val |= size; 1516c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_TXQ_TOKEN_SIZE_REG(queue), val); 1517c5aff182SThomas Petazzoni } 1518c5aff182SThomas Petazzoni } 1519c5aff182SThomas Petazzoni } 1520c5aff182SThomas Petazzoni 1521c5aff182SThomas Petazzoni /* Set unicast address */ 1522c5aff182SThomas Petazzoni static void mvneta_set_ucast_addr(struct mvneta_port *pp, u8 last_nibble, 1523c5aff182SThomas Petazzoni int queue) 1524c5aff182SThomas Petazzoni { 1525c5aff182SThomas Petazzoni unsigned int unicast_reg; 1526c5aff182SThomas Petazzoni unsigned int tbl_offset; 1527c5aff182SThomas Petazzoni unsigned int reg_offset; 1528c5aff182SThomas Petazzoni 1529c5aff182SThomas Petazzoni /* Locate the Unicast table entry */ 1530c5aff182SThomas Petazzoni last_nibble = (0xf & last_nibble); 1531c5aff182SThomas Petazzoni 1532c5aff182SThomas Petazzoni /* offset from unicast tbl base */ 1533c5aff182SThomas Petazzoni tbl_offset = (last_nibble / 4) * 4; 1534c5aff182SThomas Petazzoni 1535c5aff182SThomas Petazzoni /* offset within the above reg */ 1536c5aff182SThomas Petazzoni reg_offset = last_nibble % 4; 1537c5aff182SThomas Petazzoni 1538c5aff182SThomas Petazzoni unicast_reg = mvreg_read(pp, (MVNETA_DA_FILT_UCAST_BASE + tbl_offset)); 1539c5aff182SThomas Petazzoni 1540c5aff182SThomas Petazzoni if (queue == -1) { 1541c5aff182SThomas Petazzoni /* Clear accepts frame bit at specified unicast DA tbl entry */ 1542c5aff182SThomas Petazzoni unicast_reg &= ~(0xff << (8 * reg_offset)); 1543c5aff182SThomas Petazzoni } else { 1544c5aff182SThomas Petazzoni unicast_reg &= ~(0xff << (8 * reg_offset)); 1545c5aff182SThomas Petazzoni unicast_reg |= ((0x01 | (queue << 1)) << (8 * reg_offset)); 1546c5aff182SThomas Petazzoni } 1547c5aff182SThomas Petazzoni 1548c5aff182SThomas Petazzoni mvreg_write(pp, (MVNETA_DA_FILT_UCAST_BASE + tbl_offset), unicast_reg); 1549c5aff182SThomas Petazzoni } 1550c5aff182SThomas Petazzoni 1551c5aff182SThomas Petazzoni /* Set mac address */ 1552c5aff182SThomas Petazzoni static void mvneta_mac_addr_set(struct mvneta_port *pp, unsigned char *addr, 1553c5aff182SThomas Petazzoni int queue) 1554c5aff182SThomas Petazzoni { 1555c5aff182SThomas Petazzoni unsigned int mac_h; 1556c5aff182SThomas Petazzoni unsigned int mac_l; 1557c5aff182SThomas Petazzoni 1558c5aff182SThomas Petazzoni if (queue != -1) { 1559c5aff182SThomas Petazzoni mac_l = (addr[4] << 8) | (addr[5]); 1560c5aff182SThomas Petazzoni mac_h = (addr[0] << 24) | (addr[1] << 16) | 1561c5aff182SThomas Petazzoni (addr[2] << 8) | (addr[3] << 0); 1562c5aff182SThomas Petazzoni 1563c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_MAC_ADDR_LOW, mac_l); 1564c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_MAC_ADDR_HIGH, mac_h); 1565c5aff182SThomas Petazzoni } 1566c5aff182SThomas Petazzoni 1567c5aff182SThomas Petazzoni /* Accept frames of this address */ 1568c5aff182SThomas Petazzoni mvneta_set_ucast_addr(pp, addr[5], queue); 1569c5aff182SThomas Petazzoni } 1570c5aff182SThomas Petazzoni 15716a20c175SThomas Petazzoni /* Set the number of packets that will be received before RX interrupt 15726a20c175SThomas Petazzoni * will be generated by HW. 1573c5aff182SThomas Petazzoni */ 1574c5aff182SThomas Petazzoni static void mvneta_rx_pkts_coal_set(struct mvneta_port *pp, 1575c5aff182SThomas Petazzoni struct mvneta_rx_queue *rxq, u32 value) 1576c5aff182SThomas Petazzoni { 1577c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_RXQ_THRESHOLD_REG(rxq->id), 1578c5aff182SThomas Petazzoni value | MVNETA_RXQ_NON_OCCUPIED(0)); 1579c5aff182SThomas Petazzoni } 1580c5aff182SThomas Petazzoni 15816a20c175SThomas Petazzoni /* Set the time delay in usec before RX interrupt will be generated by 15826a20c175SThomas Petazzoni * HW. 1583c5aff182SThomas Petazzoni */ 1584c5aff182SThomas Petazzoni static void mvneta_rx_time_coal_set(struct mvneta_port *pp, 1585c5aff182SThomas Petazzoni struct mvneta_rx_queue *rxq, u32 value) 1586c5aff182SThomas Petazzoni { 1587189dd626SThomas Petazzoni u32 val; 1588189dd626SThomas Petazzoni unsigned long clk_rate; 1589189dd626SThomas Petazzoni 1590189dd626SThomas Petazzoni clk_rate = clk_get_rate(pp->clk); 1591189dd626SThomas Petazzoni val = (clk_rate / 1000000) * value; 1592c5aff182SThomas Petazzoni 1593c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_RXQ_TIME_COAL_REG(rxq->id), val); 1594c5aff182SThomas Petazzoni } 1595c5aff182SThomas Petazzoni 1596c5aff182SThomas Petazzoni /* Set threshold for TX_DONE pkts coalescing */ 1597c5aff182SThomas Petazzoni static void mvneta_tx_done_pkts_coal_set(struct mvneta_port *pp, 1598c5aff182SThomas Petazzoni struct mvneta_tx_queue *txq, u32 value) 1599c5aff182SThomas Petazzoni { 1600c5aff182SThomas Petazzoni u32 val; 1601c5aff182SThomas Petazzoni 1602c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_TXQ_SIZE_REG(txq->id)); 1603c5aff182SThomas Petazzoni 1604c5aff182SThomas Petazzoni val &= ~MVNETA_TXQ_SENT_THRESH_ALL_MASK; 1605c5aff182SThomas Petazzoni val |= MVNETA_TXQ_SENT_THRESH_MASK(value); 1606c5aff182SThomas Petazzoni 1607c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_TXQ_SIZE_REG(txq->id), val); 1608c5aff182SThomas Petazzoni } 1609c5aff182SThomas Petazzoni 1610c5aff182SThomas Petazzoni /* Handle rx descriptor fill by setting buf_cookie and buf_phys_addr */ 1611c5aff182SThomas Petazzoni static void mvneta_rx_desc_fill(struct mvneta_rx_desc *rx_desc, 1612f88bee1cSGregory CLEMENT u32 phys_addr, void *virt_addr, 1613f88bee1cSGregory CLEMENT struct mvneta_rx_queue *rxq) 1614c5aff182SThomas Petazzoni { 1615f88bee1cSGregory CLEMENT int i; 1616f88bee1cSGregory CLEMENT 1617c5aff182SThomas Petazzoni rx_desc->buf_phys_addr = phys_addr; 1618f88bee1cSGregory CLEMENT i = rx_desc - rxq->descs; 1619f88bee1cSGregory CLEMENT rxq->buf_virt_addr[i] = virt_addr; 1620c5aff182SThomas Petazzoni } 1621c5aff182SThomas Petazzoni 1622c5aff182SThomas Petazzoni /* Decrement sent descriptors counter */ 1623c5aff182SThomas Petazzoni static void mvneta_txq_sent_desc_dec(struct mvneta_port *pp, 1624c5aff182SThomas Petazzoni struct mvneta_tx_queue *txq, 1625c5aff182SThomas Petazzoni int sent_desc) 1626c5aff182SThomas Petazzoni { 1627c5aff182SThomas Petazzoni u32 val; 1628c5aff182SThomas Petazzoni 1629c5aff182SThomas Petazzoni /* Only 255 TX descriptors can be updated at once */ 1630c5aff182SThomas Petazzoni while (sent_desc > 0xff) { 1631c5aff182SThomas Petazzoni val = 0xff << MVNETA_TXQ_DEC_SENT_SHIFT; 1632c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val); 1633c5aff182SThomas Petazzoni sent_desc = sent_desc - 0xff; 1634c5aff182SThomas Petazzoni } 1635c5aff182SThomas Petazzoni 1636c5aff182SThomas Petazzoni val = sent_desc << MVNETA_TXQ_DEC_SENT_SHIFT; 1637c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val); 1638c5aff182SThomas Petazzoni } 1639c5aff182SThomas Petazzoni 1640c5aff182SThomas Petazzoni /* Get number of TX descriptors already sent by HW */ 1641c5aff182SThomas Petazzoni static int mvneta_txq_sent_desc_num_get(struct mvneta_port *pp, 1642c5aff182SThomas Petazzoni struct mvneta_tx_queue *txq) 1643c5aff182SThomas Petazzoni { 1644c5aff182SThomas Petazzoni u32 val; 1645c5aff182SThomas Petazzoni int sent_desc; 1646c5aff182SThomas Petazzoni 1647c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_TXQ_STATUS_REG(txq->id)); 1648c5aff182SThomas Petazzoni sent_desc = (val & MVNETA_TXQ_SENT_DESC_MASK) >> 1649c5aff182SThomas Petazzoni MVNETA_TXQ_SENT_DESC_SHIFT; 1650c5aff182SThomas Petazzoni 1651c5aff182SThomas Petazzoni return sent_desc; 1652c5aff182SThomas Petazzoni } 1653c5aff182SThomas Petazzoni 16546a20c175SThomas Petazzoni /* Get number of sent descriptors and decrement counter. 1655c5aff182SThomas Petazzoni * The number of sent descriptors is returned. 1656c5aff182SThomas Petazzoni */ 1657c5aff182SThomas Petazzoni static int mvneta_txq_sent_desc_proc(struct mvneta_port *pp, 1658c5aff182SThomas Petazzoni struct mvneta_tx_queue *txq) 1659c5aff182SThomas Petazzoni { 1660c5aff182SThomas Petazzoni int sent_desc; 1661c5aff182SThomas Petazzoni 1662c5aff182SThomas Petazzoni /* Get number of sent descriptors */ 1663c5aff182SThomas Petazzoni sent_desc = mvneta_txq_sent_desc_num_get(pp, txq); 1664c5aff182SThomas Petazzoni 1665c5aff182SThomas Petazzoni /* Decrement sent descriptors counter */ 1666c5aff182SThomas Petazzoni if (sent_desc) 1667c5aff182SThomas Petazzoni mvneta_txq_sent_desc_dec(pp, txq, sent_desc); 1668c5aff182SThomas Petazzoni 1669c5aff182SThomas Petazzoni return sent_desc; 1670c5aff182SThomas Petazzoni } 1671c5aff182SThomas Petazzoni 1672c5aff182SThomas Petazzoni /* Set TXQ descriptors fields relevant for CSUM calculation */ 1673c5aff182SThomas Petazzoni static u32 mvneta_txq_desc_csum(int l3_offs, int l3_proto, 1674c5aff182SThomas Petazzoni int ip_hdr_len, int l4_proto) 1675c5aff182SThomas Petazzoni { 1676c5aff182SThomas Petazzoni u32 command; 1677c5aff182SThomas Petazzoni 1678c5aff182SThomas Petazzoni /* Fields: L3_offset, IP_hdrlen, L3_type, G_IPv4_chk, 16796a20c175SThomas Petazzoni * G_L4_chk, L4_type; required only for checksum 16806a20c175SThomas Petazzoni * calculation 16816a20c175SThomas Petazzoni */ 1682c5aff182SThomas Petazzoni command = l3_offs << MVNETA_TX_L3_OFF_SHIFT; 1683c5aff182SThomas Petazzoni command |= ip_hdr_len << MVNETA_TX_IP_HLEN_SHIFT; 1684c5aff182SThomas Petazzoni 16850a198587SThomas Fitzsimmons if (l3_proto == htons(ETH_P_IP)) 1686c5aff182SThomas Petazzoni command |= MVNETA_TXD_IP_CSUM; 1687c5aff182SThomas Petazzoni else 1688c5aff182SThomas Petazzoni command |= MVNETA_TX_L3_IP6; 1689c5aff182SThomas Petazzoni 1690c5aff182SThomas Petazzoni if (l4_proto == IPPROTO_TCP) 1691c5aff182SThomas Petazzoni command |= MVNETA_TX_L4_CSUM_FULL; 1692c5aff182SThomas Petazzoni else if (l4_proto == IPPROTO_UDP) 1693c5aff182SThomas Petazzoni command |= MVNETA_TX_L4_UDP | MVNETA_TX_L4_CSUM_FULL; 1694c5aff182SThomas Petazzoni else 1695c5aff182SThomas Petazzoni command |= MVNETA_TX_L4_CSUM_NOT; 1696c5aff182SThomas Petazzoni 1697c5aff182SThomas Petazzoni return command; 1698c5aff182SThomas Petazzoni } 1699c5aff182SThomas Petazzoni 1700c5aff182SThomas Petazzoni 1701c5aff182SThomas Petazzoni /* Display more error info */ 1702c5aff182SThomas Petazzoni static void mvneta_rx_error(struct mvneta_port *pp, 1703c5aff182SThomas Petazzoni struct mvneta_rx_desc *rx_desc) 1704c5aff182SThomas Petazzoni { 1705c5aff182SThomas Petazzoni u32 status = rx_desc->status; 1706c5aff182SThomas Petazzoni 1707c5aff182SThomas Petazzoni switch (status & MVNETA_RXD_ERR_CODE_MASK) { 1708c5aff182SThomas Petazzoni case MVNETA_RXD_ERR_CRC: 1709c5aff182SThomas Petazzoni netdev_err(pp->dev, "bad rx status %08x (crc error), size=%d\n", 1710c5aff182SThomas Petazzoni status, rx_desc->data_size); 1711c5aff182SThomas Petazzoni break; 1712c5aff182SThomas Petazzoni case MVNETA_RXD_ERR_OVERRUN: 1713c5aff182SThomas Petazzoni netdev_err(pp->dev, "bad rx status %08x (overrun error), size=%d\n", 1714c5aff182SThomas Petazzoni status, rx_desc->data_size); 1715c5aff182SThomas Petazzoni break; 1716c5aff182SThomas Petazzoni case MVNETA_RXD_ERR_LEN: 1717c5aff182SThomas Petazzoni netdev_err(pp->dev, "bad rx status %08x (max frame length error), size=%d\n", 1718c5aff182SThomas Petazzoni status, rx_desc->data_size); 1719c5aff182SThomas Petazzoni break; 1720c5aff182SThomas Petazzoni case MVNETA_RXD_ERR_RESOURCE: 1721c5aff182SThomas Petazzoni netdev_err(pp->dev, "bad rx status %08x (resource error), size=%d\n", 1722c5aff182SThomas Petazzoni status, rx_desc->data_size); 1723c5aff182SThomas Petazzoni break; 1724c5aff182SThomas Petazzoni } 1725c5aff182SThomas Petazzoni } 1726c5aff182SThomas Petazzoni 17275428213cSwilly tarreau /* Handle RX checksum offload based on the descriptor's status */ 17285428213cSwilly tarreau static void mvneta_rx_csum(struct mvneta_port *pp, u32 status, 1729c5aff182SThomas Petazzoni struct sk_buff *skb) 1730c5aff182SThomas Petazzoni { 1731f945cec8SYelena Krivosheev if ((pp->dev->features & NETIF_F_RXCSUM) && 1732f945cec8SYelena Krivosheev (status & MVNETA_RXD_L3_IP4) && 17335428213cSwilly tarreau (status & MVNETA_RXD_L4_CSUM_OK)) { 1734c5aff182SThomas Petazzoni skb->csum = 0; 1735c5aff182SThomas Petazzoni skb->ip_summed = CHECKSUM_UNNECESSARY; 1736c5aff182SThomas Petazzoni return; 1737c5aff182SThomas Petazzoni } 1738c5aff182SThomas Petazzoni 1739c5aff182SThomas Petazzoni skb->ip_summed = CHECKSUM_NONE; 1740c5aff182SThomas Petazzoni } 1741c5aff182SThomas Petazzoni 17426c498974Swilly tarreau /* Return tx queue pointer (find last set bit) according to <cause> returned 17436c498974Swilly tarreau * form tx_done reg. <cause> must not be null. The return value is always a 17446c498974Swilly tarreau * valid queue for matching the first one found in <cause>. 17456c498974Swilly tarreau */ 1746c5aff182SThomas Petazzoni static struct mvneta_tx_queue *mvneta_tx_done_policy(struct mvneta_port *pp, 1747c5aff182SThomas Petazzoni u32 cause) 1748c5aff182SThomas Petazzoni { 1749c5aff182SThomas Petazzoni int queue = fls(cause) - 1; 1750c5aff182SThomas Petazzoni 17516c498974Swilly tarreau return &pp->txqs[queue]; 1752c5aff182SThomas Petazzoni } 1753c5aff182SThomas Petazzoni 1754c5aff182SThomas Petazzoni /* Free tx queue skbuffs */ 1755c5aff182SThomas Petazzoni static void mvneta_txq_bufs_free(struct mvneta_port *pp, 1756a29b6235SMarcin Wojtas struct mvneta_tx_queue *txq, int num, 1757a29b6235SMarcin Wojtas struct netdev_queue *nq) 1758c5aff182SThomas Petazzoni { 1759a29b6235SMarcin Wojtas unsigned int bytes_compl = 0, pkts_compl = 0; 1760c5aff182SThomas Petazzoni int i; 1761c5aff182SThomas Petazzoni 1762c5aff182SThomas Petazzoni for (i = 0; i < num; i++) { 1763c5aff182SThomas Petazzoni struct mvneta_tx_desc *tx_desc = txq->descs + 1764c5aff182SThomas Petazzoni txq->txq_get_index; 1765c5aff182SThomas Petazzoni struct sk_buff *skb = txq->tx_skb[txq->txq_get_index]; 1766c5aff182SThomas Petazzoni 1767a29b6235SMarcin Wojtas if (skb) { 1768a29b6235SMarcin Wojtas bytes_compl += skb->len; 1769a29b6235SMarcin Wojtas pkts_compl++; 1770a29b6235SMarcin Wojtas } 1771a29b6235SMarcin Wojtas 1772c5aff182SThomas Petazzoni mvneta_txq_inc_get(txq); 1773c5aff182SThomas Petazzoni 17742e3173a3SEzequiel Garcia if (!IS_TSO_HEADER(txq, tx_desc->buf_phys_addr)) 17752e3173a3SEzequiel Garcia dma_unmap_single(pp->dev->dev.parent, 17762e3173a3SEzequiel Garcia tx_desc->buf_phys_addr, 1777c5aff182SThomas Petazzoni tx_desc->data_size, DMA_TO_DEVICE); 1778ba7e46efSEzequiel Garcia if (!skb) 1779ba7e46efSEzequiel Garcia continue; 1780c5aff182SThomas Petazzoni dev_kfree_skb_any(skb); 1781c5aff182SThomas Petazzoni } 1782a29b6235SMarcin Wojtas 1783a29b6235SMarcin Wojtas netdev_tx_completed_queue(nq, pkts_compl, bytes_compl); 1784c5aff182SThomas Petazzoni } 1785c5aff182SThomas Petazzoni 1786c5aff182SThomas Petazzoni /* Handle end of transmission */ 1787cd713199SArnaud Ebalard static void mvneta_txq_done(struct mvneta_port *pp, 1788c5aff182SThomas Petazzoni struct mvneta_tx_queue *txq) 1789c5aff182SThomas Petazzoni { 1790c5aff182SThomas Petazzoni struct netdev_queue *nq = netdev_get_tx_queue(pp->dev, txq->id); 1791c5aff182SThomas Petazzoni int tx_done; 1792c5aff182SThomas Petazzoni 1793c5aff182SThomas Petazzoni tx_done = mvneta_txq_sent_desc_proc(pp, txq); 1794cd713199SArnaud Ebalard if (!tx_done) 1795cd713199SArnaud Ebalard return; 1796cd713199SArnaud Ebalard 1797a29b6235SMarcin Wojtas mvneta_txq_bufs_free(pp, txq, tx_done, nq); 1798c5aff182SThomas Petazzoni 1799c5aff182SThomas Petazzoni txq->count -= tx_done; 1800c5aff182SThomas Petazzoni 1801c5aff182SThomas Petazzoni if (netif_tx_queue_stopped(nq)) { 18028eef5f97SEzequiel Garcia if (txq->count <= txq->tx_wake_threshold) 1803c5aff182SThomas Petazzoni netif_tx_wake_queue(nq); 1804c5aff182SThomas Petazzoni } 1805c5aff182SThomas Petazzoni } 1806c5aff182SThomas Petazzoni 1807dc35a10fSMarcin Wojtas /* Refill processing for SW buffer management */ 18087e47fd84SGregory CLEMENT /* Allocate page per descriptor */ 1809c5aff182SThomas Petazzoni static int mvneta_rx_refill(struct mvneta_port *pp, 1810f88bee1cSGregory CLEMENT struct mvneta_rx_desc *rx_desc, 18117e47fd84SGregory CLEMENT struct mvneta_rx_queue *rxq, 18127e47fd84SGregory CLEMENT gfp_t gfp_mask) 1813c5aff182SThomas Petazzoni { 1814c5aff182SThomas Petazzoni dma_addr_t phys_addr; 18157e47fd84SGregory CLEMENT struct page *page; 1816c5aff182SThomas Petazzoni 18177e47fd84SGregory CLEMENT page = __dev_alloc_page(gfp_mask); 18187e47fd84SGregory CLEMENT if (!page) 1819c5aff182SThomas Petazzoni return -ENOMEM; 1820c5aff182SThomas Petazzoni 18217e47fd84SGregory CLEMENT /* map page for use */ 18227e47fd84SGregory CLEMENT phys_addr = dma_map_page(pp->dev->dev.parent, page, 0, PAGE_SIZE, 1823c5aff182SThomas Petazzoni DMA_FROM_DEVICE); 1824c5aff182SThomas Petazzoni if (unlikely(dma_mapping_error(pp->dev->dev.parent, phys_addr))) { 18257e47fd84SGregory CLEMENT __free_page(page); 1826c5aff182SThomas Petazzoni return -ENOMEM; 1827c5aff182SThomas Petazzoni } 1828c5aff182SThomas Petazzoni 18298d5047cfSMarcin Wojtas phys_addr += pp->rx_offset_correction; 18307e47fd84SGregory CLEMENT mvneta_rx_desc_fill(rx_desc, phys_addr, page, rxq); 1831c5aff182SThomas Petazzoni return 0; 1832c5aff182SThomas Petazzoni } 1833c5aff182SThomas Petazzoni 1834c5aff182SThomas Petazzoni /* Handle tx checksum */ 1835c5aff182SThomas Petazzoni static u32 mvneta_skb_tx_csum(struct mvneta_port *pp, struct sk_buff *skb) 1836c5aff182SThomas Petazzoni { 1837c5aff182SThomas Petazzoni if (skb->ip_summed == CHECKSUM_PARTIAL) { 1838c5aff182SThomas Petazzoni int ip_hdr_len = 0; 1839817dbfa5SVlad Yasevich __be16 l3_proto = vlan_get_protocol(skb); 1840c5aff182SThomas Petazzoni u8 l4_proto; 1841c5aff182SThomas Petazzoni 1842817dbfa5SVlad Yasevich if (l3_proto == htons(ETH_P_IP)) { 1843c5aff182SThomas Petazzoni struct iphdr *ip4h = ip_hdr(skb); 1844c5aff182SThomas Petazzoni 1845c5aff182SThomas Petazzoni /* Calculate IPv4 checksum and L4 checksum */ 1846c5aff182SThomas Petazzoni ip_hdr_len = ip4h->ihl; 1847c5aff182SThomas Petazzoni l4_proto = ip4h->protocol; 1848817dbfa5SVlad Yasevich } else if (l3_proto == htons(ETH_P_IPV6)) { 1849c5aff182SThomas Petazzoni struct ipv6hdr *ip6h = ipv6_hdr(skb); 1850c5aff182SThomas Petazzoni 1851c5aff182SThomas Petazzoni /* Read l4_protocol from one of IPv6 extra headers */ 1852c5aff182SThomas Petazzoni if (skb_network_header_len(skb) > 0) 1853c5aff182SThomas Petazzoni ip_hdr_len = (skb_network_header_len(skb) >> 2); 1854c5aff182SThomas Petazzoni l4_proto = ip6h->nexthdr; 1855c5aff182SThomas Petazzoni } else 1856c5aff182SThomas Petazzoni return MVNETA_TX_L4_CSUM_NOT; 1857c5aff182SThomas Petazzoni 1858c5aff182SThomas Petazzoni return mvneta_txq_desc_csum(skb_network_offset(skb), 1859817dbfa5SVlad Yasevich l3_proto, ip_hdr_len, l4_proto); 1860c5aff182SThomas Petazzoni } 1861c5aff182SThomas Petazzoni 1862c5aff182SThomas Petazzoni return MVNETA_TX_L4_CSUM_NOT; 1863c5aff182SThomas Petazzoni } 1864c5aff182SThomas Petazzoni 1865c5aff182SThomas Petazzoni /* Drop packets received by the RXQ and free buffers */ 1866c5aff182SThomas Petazzoni static void mvneta_rxq_drop_pkts(struct mvneta_port *pp, 1867c5aff182SThomas Petazzoni struct mvneta_rx_queue *rxq) 1868c5aff182SThomas Petazzoni { 1869c5aff182SThomas Petazzoni int rx_done, i; 1870c5aff182SThomas Petazzoni 1871c5aff182SThomas Petazzoni rx_done = mvneta_rxq_busy_desc_num_get(pp, rxq); 1872dc35a10fSMarcin Wojtas if (rx_done) 1873dc35a10fSMarcin Wojtas mvneta_rxq_desc_num_update(pp, rxq, rx_done, rx_done); 1874dc35a10fSMarcin Wojtas 1875dc35a10fSMarcin Wojtas if (pp->bm_priv) { 1876dc35a10fSMarcin Wojtas for (i = 0; i < rx_done; i++) { 1877dc35a10fSMarcin Wojtas struct mvneta_rx_desc *rx_desc = 1878dc35a10fSMarcin Wojtas mvneta_rxq_next_desc_get(rxq); 1879dc35a10fSMarcin Wojtas u8 pool_id = MVNETA_RX_GET_BM_POOL_ID(rx_desc); 1880dc35a10fSMarcin Wojtas struct mvneta_bm_pool *bm_pool; 1881dc35a10fSMarcin Wojtas 1882dc35a10fSMarcin Wojtas bm_pool = &pp->bm_priv->bm_pools[pool_id]; 1883dc35a10fSMarcin Wojtas /* Return dropped buffer to the pool */ 1884dc35a10fSMarcin Wojtas mvneta_bm_pool_put_bp(pp->bm_priv, bm_pool, 1885dc35a10fSMarcin Wojtas rx_desc->buf_phys_addr); 1886dc35a10fSMarcin Wojtas } 1887dc35a10fSMarcin Wojtas return; 1888dc35a10fSMarcin Wojtas } 1889dc35a10fSMarcin Wojtas 1890c5aff182SThomas Petazzoni for (i = 0; i < rxq->size; i++) { 1891c5aff182SThomas Petazzoni struct mvneta_rx_desc *rx_desc = rxq->descs + i; 1892f88bee1cSGregory CLEMENT void *data = rxq->buf_virt_addr[i]; 1893562e2f46SYelena Krivosheev if (!data || !(rx_desc->buf_phys_addr)) 1894562e2f46SYelena Krivosheev continue; 1895c5aff182SThomas Petazzoni 1896f4a51879SAntoine Tenart dma_unmap_page(pp->dev->dev.parent, rx_desc->buf_phys_addr, 1897f4a51879SAntoine Tenart PAGE_SIZE, DMA_FROM_DEVICE); 18987e47fd84SGregory CLEMENT __free_page(data); 1899dc35a10fSMarcin Wojtas } 1900c5aff182SThomas Petazzoni } 1901c5aff182SThomas Petazzoni 1902562e2f46SYelena Krivosheev static inline 1903562e2f46SYelena Krivosheev int mvneta_rx_refill_queue(struct mvneta_port *pp, struct mvneta_rx_queue *rxq) 1904562e2f46SYelena Krivosheev { 1905562e2f46SYelena Krivosheev struct mvneta_rx_desc *rx_desc; 1906562e2f46SYelena Krivosheev int curr_desc = rxq->first_to_refill; 1907562e2f46SYelena Krivosheev int i; 1908562e2f46SYelena Krivosheev 1909562e2f46SYelena Krivosheev for (i = 0; (i < rxq->refill_num) && (i < 64); i++) { 1910562e2f46SYelena Krivosheev rx_desc = rxq->descs + curr_desc; 1911562e2f46SYelena Krivosheev if (!(rx_desc->buf_phys_addr)) { 1912562e2f46SYelena Krivosheev if (mvneta_rx_refill(pp, rx_desc, rxq, GFP_ATOMIC)) { 1913562e2f46SYelena Krivosheev pr_err("Can't refill queue %d. Done %d from %d\n", 1914562e2f46SYelena Krivosheev rxq->id, i, rxq->refill_num); 1915562e2f46SYelena Krivosheev rxq->refill_err++; 1916562e2f46SYelena Krivosheev break; 1917562e2f46SYelena Krivosheev } 1918562e2f46SYelena Krivosheev } 1919562e2f46SYelena Krivosheev curr_desc = MVNETA_QUEUE_NEXT_DESC(rxq, curr_desc); 1920562e2f46SYelena Krivosheev } 1921562e2f46SYelena Krivosheev rxq->refill_num -= i; 1922562e2f46SYelena Krivosheev rxq->first_to_refill = curr_desc; 1923562e2f46SYelena Krivosheev 1924562e2f46SYelena Krivosheev return i; 1925562e2f46SYelena Krivosheev } 1926562e2f46SYelena Krivosheev 1927dc35a10fSMarcin Wojtas /* Main rx processing when using software buffer management */ 19287a86f05fSAndrew Lunn static int mvneta_rx_swbm(struct napi_struct *napi, 1929562e2f46SYelena Krivosheev struct mvneta_port *pp, int budget, 1930c5aff182SThomas Petazzoni struct mvneta_rx_queue *rxq) 1931c5aff182SThomas Petazzoni { 1932c5aff182SThomas Petazzoni struct net_device *dev = pp->dev; 1933562e2f46SYelena Krivosheev int rx_todo, rx_proc; 1934562e2f46SYelena Krivosheev int refill = 0; 1935dc4277ddSwilly tarreau u32 rcvd_pkts = 0; 1936dc4277ddSwilly tarreau u32 rcvd_bytes = 0; 1937c5aff182SThomas Petazzoni 1938c5aff182SThomas Petazzoni /* Get number of received packets */ 1939562e2f46SYelena Krivosheev rx_todo = mvneta_rxq_busy_desc_num_get(pp, rxq); 1940562e2f46SYelena Krivosheev rx_proc = 0; 1941c5aff182SThomas Petazzoni 1942c5aff182SThomas Petazzoni /* Fairness NAPI loop */ 1943562e2f46SYelena Krivosheev while ((rcvd_pkts < budget) && (rx_proc < rx_todo)) { 1944c5aff182SThomas Petazzoni struct mvneta_rx_desc *rx_desc = mvneta_rxq_next_desc_get(rxq); 19458ec2cd48Swilly tarreau unsigned char *data; 19467e47fd84SGregory CLEMENT struct page *page; 1947daf158d0SSimon Guinot dma_addr_t phys_addr; 1948562e2f46SYelena Krivosheev u32 rx_status, index; 1949562e2f46SYelena Krivosheev int rx_bytes, skb_size, copy_size; 1950562e2f46SYelena Krivosheev int frag_num, frag_size, frag_offset; 1951c5aff182SThomas Petazzoni 1952f88bee1cSGregory CLEMENT index = rx_desc - rxq->descs; 19537e47fd84SGregory CLEMENT page = (struct page *)rxq->buf_virt_addr[index]; 19547e47fd84SGregory CLEMENT data = page_address(page); 19557e47fd84SGregory CLEMENT /* Prefetch header */ 19567e47fd84SGregory CLEMENT prefetch(data); 1957c5aff182SThomas Petazzoni 1958562e2f46SYelena Krivosheev phys_addr = rx_desc->buf_phys_addr; 1959562e2f46SYelena Krivosheev rx_status = rx_desc->status; 1960562e2f46SYelena Krivosheev rx_proc++; 1961562e2f46SYelena Krivosheev rxq->refill_num++; 1962562e2f46SYelena Krivosheev 1963562e2f46SYelena Krivosheev if (rx_status & MVNETA_RXD_FIRST_DESC) { 1964562e2f46SYelena Krivosheev /* Check errors only for FIRST descriptor */ 1965562e2f46SYelena Krivosheev if (rx_status & MVNETA_RXD_ERR_SUMMARY) { 19662eecb2e0SYelena Krivosheev mvneta_rx_error(pp, rx_desc); 1967c5aff182SThomas Petazzoni dev->stats.rx_errors++; 19688ec2cd48Swilly tarreau /* leave the descriptor untouched */ 1969c5aff182SThomas Petazzoni continue; 1970c5aff182SThomas Petazzoni } 1971562e2f46SYelena Krivosheev rx_bytes = rx_desc->data_size - 1972562e2f46SYelena Krivosheev (ETH_FCS_LEN + MVNETA_MH_SIZE); 1973c5aff182SThomas Petazzoni 1974562e2f46SYelena Krivosheev /* Allocate small skb for each new packet */ 1975562e2f46SYelena Krivosheev skb_size = max(rx_copybreak, rx_header_size); 1976562e2f46SYelena Krivosheev rxq->skb = netdev_alloc_skb_ip_align(dev, skb_size); 1977562e2f46SYelena Krivosheev if (unlikely(!rxq->skb)) { 197817a96da6SGregory CLEMENT netdev_err(dev, 197917a96da6SGregory CLEMENT "Can't allocate skb on queue %d\n", 198017a96da6SGregory CLEMENT rxq->id); 1981562e2f46SYelena Krivosheev dev->stats.rx_dropped++; 198217a96da6SGregory CLEMENT rxq->skb_alloc_err++; 1983f19fadfcSwilly tarreau continue; 1984f19fadfcSwilly tarreau } 1985562e2f46SYelena Krivosheev copy_size = min(skb_size, rx_bytes); 1986f19fadfcSwilly tarreau 1987562e2f46SYelena Krivosheev /* Copy data from buffer to SKB, skip Marvell header */ 1988562e2f46SYelena Krivosheev memcpy(rxq->skb->data, data + MVNETA_MH_SIZE, 1989562e2f46SYelena Krivosheev copy_size); 1990562e2f46SYelena Krivosheev skb_put(rxq->skb, copy_size); 1991562e2f46SYelena Krivosheev rxq->left_size = rx_bytes - copy_size; 1992a84e3289SSimon Guinot 1993562e2f46SYelena Krivosheev mvneta_rx_csum(pp, rx_status, rxq->skb); 1994562e2f46SYelena Krivosheev if (rxq->left_size == 0) { 1995562e2f46SYelena Krivosheev int size = copy_size + MVNETA_MH_SIZE; 1996dc35a10fSMarcin Wojtas 1997562e2f46SYelena Krivosheev dma_sync_single_range_for_cpu(dev->dev.parent, 1998562e2f46SYelena Krivosheev phys_addr, 0, 1999562e2f46SYelena Krivosheev size, 2000dc35a10fSMarcin Wojtas DMA_FROM_DEVICE); 2001c5aff182SThomas Petazzoni 2002562e2f46SYelena Krivosheev /* leave the descriptor and buffer untouched */ 2003562e2f46SYelena Krivosheev } else { 2004562e2f46SYelena Krivosheev /* refill descriptor with new buffer later */ 2005562e2f46SYelena Krivosheev rx_desc->buf_phys_addr = 0; 200626c17a17SMarcin Wojtas 2007562e2f46SYelena Krivosheev frag_num = 0; 2008562e2f46SYelena Krivosheev frag_offset = copy_size + MVNETA_MH_SIZE; 2009562e2f46SYelena Krivosheev frag_size = min(rxq->left_size, 2010562e2f46SYelena Krivosheev (int)(PAGE_SIZE - frag_offset)); 2011562e2f46SYelena Krivosheev skb_add_rx_frag(rxq->skb, frag_num, page, 2012562e2f46SYelena Krivosheev frag_offset, frag_size, 2013562e2f46SYelena Krivosheev PAGE_SIZE); 2014cf5cca6eSAntoine Tenart dma_unmap_page(dev->dev.parent, phys_addr, 2015562e2f46SYelena Krivosheev PAGE_SIZE, DMA_FROM_DEVICE); 2016562e2f46SYelena Krivosheev rxq->left_size -= frag_size; 2017562e2f46SYelena Krivosheev } 2018562e2f46SYelena Krivosheev } else { 2019562e2f46SYelena Krivosheev /* Middle or Last descriptor */ 2020562e2f46SYelena Krivosheev if (unlikely(!rxq->skb)) { 2021562e2f46SYelena Krivosheev pr_debug("no skb for rx_status 0x%x\n", 2022562e2f46SYelena Krivosheev rx_status); 2023562e2f46SYelena Krivosheev continue; 2024562e2f46SYelena Krivosheev } 2025562e2f46SYelena Krivosheev if (!rxq->left_size) { 2026562e2f46SYelena Krivosheev /* last descriptor has only FCS */ 2027562e2f46SYelena Krivosheev /* and can be discarded */ 2028562e2f46SYelena Krivosheev dma_sync_single_range_for_cpu(dev->dev.parent, 2029562e2f46SYelena Krivosheev phys_addr, 0, 2030562e2f46SYelena Krivosheev ETH_FCS_LEN, 2031562e2f46SYelena Krivosheev DMA_FROM_DEVICE); 2032562e2f46SYelena Krivosheev /* leave the descriptor and buffer untouched */ 2033562e2f46SYelena Krivosheev } else { 2034562e2f46SYelena Krivosheev /* refill descriptor with new buffer later */ 2035562e2f46SYelena Krivosheev rx_desc->buf_phys_addr = 0; 2036562e2f46SYelena Krivosheev 2037562e2f46SYelena Krivosheev frag_num = skb_shinfo(rxq->skb)->nr_frags; 2038562e2f46SYelena Krivosheev frag_offset = 0; 2039562e2f46SYelena Krivosheev frag_size = min(rxq->left_size, 2040562e2f46SYelena Krivosheev (int)(PAGE_SIZE - frag_offset)); 2041562e2f46SYelena Krivosheev skb_add_rx_frag(rxq->skb, frag_num, page, 2042562e2f46SYelena Krivosheev frag_offset, frag_size, 2043562e2f46SYelena Krivosheev PAGE_SIZE); 2044562e2f46SYelena Krivosheev 2045f4a51879SAntoine Tenart dma_unmap_page(dev->dev.parent, phys_addr, 2046f4a51879SAntoine Tenart PAGE_SIZE, DMA_FROM_DEVICE); 2047562e2f46SYelena Krivosheev 2048562e2f46SYelena Krivosheev rxq->left_size -= frag_size; 2049562e2f46SYelena Krivosheev } 2050562e2f46SYelena Krivosheev } /* Middle or Last descriptor */ 2051562e2f46SYelena Krivosheev 2052562e2f46SYelena Krivosheev if (!(rx_status & MVNETA_RXD_LAST_DESC)) 2053562e2f46SYelena Krivosheev /* no last descriptor this time */ 2054562e2f46SYelena Krivosheev continue; 2055562e2f46SYelena Krivosheev 2056562e2f46SYelena Krivosheev if (rxq->left_size) { 2057562e2f46SYelena Krivosheev pr_err("get last desc, but left_size (%d) != 0\n", 2058562e2f46SYelena Krivosheev rxq->left_size); 2059562e2f46SYelena Krivosheev dev_kfree_skb_any(rxq->skb); 2060562e2f46SYelena Krivosheev rxq->left_size = 0; 2061562e2f46SYelena Krivosheev rxq->skb = NULL; 2062562e2f46SYelena Krivosheev continue; 2063562e2f46SYelena Krivosheev } 2064dc4277ddSwilly tarreau rcvd_pkts++; 2065562e2f46SYelena Krivosheev rcvd_bytes += rxq->skb->len; 2066c5aff182SThomas Petazzoni 2067c5aff182SThomas Petazzoni /* Linux processing */ 2068562e2f46SYelena Krivosheev rxq->skb->protocol = eth_type_trans(rxq->skb, dev); 2069c5aff182SThomas Petazzoni 2070562e2f46SYelena Krivosheev napi_gro_receive(napi, rxq->skb); 2071c5aff182SThomas Petazzoni 2072562e2f46SYelena Krivosheev /* clean uncomplete skb pointer in queue */ 2073562e2f46SYelena Krivosheev rxq->skb = NULL; 2074562e2f46SYelena Krivosheev rxq->left_size = 0; 2075c5aff182SThomas Petazzoni } 2076c5aff182SThomas Petazzoni 2077dc4277ddSwilly tarreau if (rcvd_pkts) { 207874c41b04Swilly tarreau struct mvneta_pcpu_stats *stats = this_cpu_ptr(pp->stats); 207974c41b04Swilly tarreau 208074c41b04Swilly tarreau u64_stats_update_begin(&stats->syncp); 208174c41b04Swilly tarreau stats->rx_packets += rcvd_pkts; 208274c41b04Swilly tarreau stats->rx_bytes += rcvd_bytes; 208374c41b04Swilly tarreau u64_stats_update_end(&stats->syncp); 2084dc4277ddSwilly tarreau } 2085dc4277ddSwilly tarreau 2086562e2f46SYelena Krivosheev /* return some buffers to hardware queue, one at a time is too slow */ 2087562e2f46SYelena Krivosheev refill = mvneta_rx_refill_queue(pp, rxq); 2088c5aff182SThomas Petazzoni 2089562e2f46SYelena Krivosheev /* Update rxq management counters */ 2090562e2f46SYelena Krivosheev mvneta_rxq_desc_num_update(pp, rxq, rx_proc, refill); 2091562e2f46SYelena Krivosheev 2092562e2f46SYelena Krivosheev return rcvd_pkts; 2093c5aff182SThomas Petazzoni } 2094c5aff182SThomas Petazzoni 2095dc35a10fSMarcin Wojtas /* Main rx processing when using hardware buffer management */ 20967a86f05fSAndrew Lunn static int mvneta_rx_hwbm(struct napi_struct *napi, 20977a86f05fSAndrew Lunn struct mvneta_port *pp, int rx_todo, 2098dc35a10fSMarcin Wojtas struct mvneta_rx_queue *rxq) 2099dc35a10fSMarcin Wojtas { 2100dc35a10fSMarcin Wojtas struct net_device *dev = pp->dev; 2101dc35a10fSMarcin Wojtas int rx_done; 2102dc35a10fSMarcin Wojtas u32 rcvd_pkts = 0; 2103dc35a10fSMarcin Wojtas u32 rcvd_bytes = 0; 2104dc35a10fSMarcin Wojtas 2105dc35a10fSMarcin Wojtas /* Get number of received packets */ 2106dc35a10fSMarcin Wojtas rx_done = mvneta_rxq_busy_desc_num_get(pp, rxq); 2107dc35a10fSMarcin Wojtas 2108dc35a10fSMarcin Wojtas if (rx_todo > rx_done) 2109dc35a10fSMarcin Wojtas rx_todo = rx_done; 2110dc35a10fSMarcin Wojtas 2111dc35a10fSMarcin Wojtas rx_done = 0; 2112dc35a10fSMarcin Wojtas 2113dc35a10fSMarcin Wojtas /* Fairness NAPI loop */ 2114dc35a10fSMarcin Wojtas while (rx_done < rx_todo) { 2115dc35a10fSMarcin Wojtas struct mvneta_rx_desc *rx_desc = mvneta_rxq_next_desc_get(rxq); 2116dc35a10fSMarcin Wojtas struct mvneta_bm_pool *bm_pool = NULL; 2117dc35a10fSMarcin Wojtas struct sk_buff *skb; 2118dc35a10fSMarcin Wojtas unsigned char *data; 2119dc35a10fSMarcin Wojtas dma_addr_t phys_addr; 2120dc35a10fSMarcin Wojtas u32 rx_status, frag_size; 2121dc35a10fSMarcin Wojtas int rx_bytes, err; 2122dc35a10fSMarcin Wojtas u8 pool_id; 2123dc35a10fSMarcin Wojtas 2124dc35a10fSMarcin Wojtas rx_done++; 2125dc35a10fSMarcin Wojtas rx_status = rx_desc->status; 2126dc35a10fSMarcin Wojtas rx_bytes = rx_desc->data_size - (ETH_FCS_LEN + MVNETA_MH_SIZE); 2127f88bee1cSGregory CLEMENT data = (u8 *)(uintptr_t)rx_desc->buf_cookie; 2128dc35a10fSMarcin Wojtas phys_addr = rx_desc->buf_phys_addr; 2129dc35a10fSMarcin Wojtas pool_id = MVNETA_RX_GET_BM_POOL_ID(rx_desc); 2130dc35a10fSMarcin Wojtas bm_pool = &pp->bm_priv->bm_pools[pool_id]; 2131dc35a10fSMarcin Wojtas 2132dc35a10fSMarcin Wojtas if (!mvneta_rxq_desc_is_first_last(rx_status) || 2133dc35a10fSMarcin Wojtas (rx_status & MVNETA_RXD_ERR_SUMMARY)) { 2134dc35a10fSMarcin Wojtas err_drop_frame_ret_pool: 2135dc35a10fSMarcin Wojtas /* Return the buffer to the pool */ 2136dc35a10fSMarcin Wojtas mvneta_bm_pool_put_bp(pp->bm_priv, bm_pool, 2137dc35a10fSMarcin Wojtas rx_desc->buf_phys_addr); 2138dc35a10fSMarcin Wojtas err_drop_frame: 2139dc35a10fSMarcin Wojtas dev->stats.rx_errors++; 2140dc35a10fSMarcin Wojtas mvneta_rx_error(pp, rx_desc); 2141dc35a10fSMarcin Wojtas /* leave the descriptor untouched */ 2142dc35a10fSMarcin Wojtas continue; 2143dc35a10fSMarcin Wojtas } 2144dc35a10fSMarcin Wojtas 2145dc35a10fSMarcin Wojtas if (rx_bytes <= rx_copybreak) { 2146dc35a10fSMarcin Wojtas /* better copy a small frame and not unmap the DMA region */ 2147dc35a10fSMarcin Wojtas skb = netdev_alloc_skb_ip_align(dev, rx_bytes); 2148dc35a10fSMarcin Wojtas if (unlikely(!skb)) 2149dc35a10fSMarcin Wojtas goto err_drop_frame_ret_pool; 2150dc35a10fSMarcin Wojtas 2151a8fef9baSRussell King dma_sync_single_range_for_cpu(&pp->bm_priv->pdev->dev, 2152dc35a10fSMarcin Wojtas rx_desc->buf_phys_addr, 2153dc35a10fSMarcin Wojtas MVNETA_MH_SIZE + NET_SKB_PAD, 2154dc35a10fSMarcin Wojtas rx_bytes, 2155dc35a10fSMarcin Wojtas DMA_FROM_DEVICE); 215659ae1d12SJohannes Berg skb_put_data(skb, data + MVNETA_MH_SIZE + NET_SKB_PAD, 2157dc35a10fSMarcin Wojtas rx_bytes); 2158dc35a10fSMarcin Wojtas 2159dc35a10fSMarcin Wojtas skb->protocol = eth_type_trans(skb, dev); 2160dc35a10fSMarcin Wojtas mvneta_rx_csum(pp, rx_status, skb); 21617a86f05fSAndrew Lunn napi_gro_receive(napi, skb); 2162dc35a10fSMarcin Wojtas 2163dc35a10fSMarcin Wojtas rcvd_pkts++; 2164dc35a10fSMarcin Wojtas rcvd_bytes += rx_bytes; 2165dc35a10fSMarcin Wojtas 2166dc35a10fSMarcin Wojtas /* Return the buffer to the pool */ 2167dc35a10fSMarcin Wojtas mvneta_bm_pool_put_bp(pp->bm_priv, bm_pool, 2168dc35a10fSMarcin Wojtas rx_desc->buf_phys_addr); 2169dc35a10fSMarcin Wojtas 2170dc35a10fSMarcin Wojtas /* leave the descriptor and buffer untouched */ 2171dc35a10fSMarcin Wojtas continue; 2172dc35a10fSMarcin Wojtas } 2173dc35a10fSMarcin Wojtas 2174dc35a10fSMarcin Wojtas /* Refill processing */ 2175baa11ebcSGregory CLEMENT err = hwbm_pool_refill(&bm_pool->hwbm_pool, GFP_ATOMIC); 2176dc35a10fSMarcin Wojtas if (err) { 2177dc35a10fSMarcin Wojtas netdev_err(dev, "Linux processing - Can't refill\n"); 217817a96da6SGregory CLEMENT rxq->refill_err++; 2179dc35a10fSMarcin Wojtas goto err_drop_frame_ret_pool; 2180dc35a10fSMarcin Wojtas } 2181dc35a10fSMarcin Wojtas 2182baa11ebcSGregory CLEMENT frag_size = bm_pool->hwbm_pool.frag_size; 2183dc35a10fSMarcin Wojtas 2184dc35a10fSMarcin Wojtas skb = build_skb(data, frag_size > PAGE_SIZE ? 0 : frag_size); 2185dc35a10fSMarcin Wojtas 2186dc35a10fSMarcin Wojtas /* After refill old buffer has to be unmapped regardless 2187dc35a10fSMarcin Wojtas * the skb is successfully built or not. 2188dc35a10fSMarcin Wojtas */ 2189dc35a10fSMarcin Wojtas dma_unmap_single(&pp->bm_priv->pdev->dev, phys_addr, 2190dc35a10fSMarcin Wojtas bm_pool->buf_size, DMA_FROM_DEVICE); 2191dc35a10fSMarcin Wojtas if (!skb) 2192dc35a10fSMarcin Wojtas goto err_drop_frame; 2193dc35a10fSMarcin Wojtas 2194dc35a10fSMarcin Wojtas rcvd_pkts++; 2195dc35a10fSMarcin Wojtas rcvd_bytes += rx_bytes; 2196dc35a10fSMarcin Wojtas 2197dc35a10fSMarcin Wojtas /* Linux processing */ 2198dc35a10fSMarcin Wojtas skb_reserve(skb, MVNETA_MH_SIZE + NET_SKB_PAD); 2199dc35a10fSMarcin Wojtas skb_put(skb, rx_bytes); 2200dc35a10fSMarcin Wojtas 2201dc35a10fSMarcin Wojtas skb->protocol = eth_type_trans(skb, dev); 2202dc35a10fSMarcin Wojtas 2203dc35a10fSMarcin Wojtas mvneta_rx_csum(pp, rx_status, skb); 2204dc35a10fSMarcin Wojtas 22057a86f05fSAndrew Lunn napi_gro_receive(napi, skb); 2206dc35a10fSMarcin Wojtas } 2207dc35a10fSMarcin Wojtas 2208dc35a10fSMarcin Wojtas if (rcvd_pkts) { 2209dc35a10fSMarcin Wojtas struct mvneta_pcpu_stats *stats = this_cpu_ptr(pp->stats); 2210dc35a10fSMarcin Wojtas 2211dc35a10fSMarcin Wojtas u64_stats_update_begin(&stats->syncp); 2212dc35a10fSMarcin Wojtas stats->rx_packets += rcvd_pkts; 2213dc35a10fSMarcin Wojtas stats->rx_bytes += rcvd_bytes; 2214dc35a10fSMarcin Wojtas u64_stats_update_end(&stats->syncp); 2215dc35a10fSMarcin Wojtas } 2216dc35a10fSMarcin Wojtas 2217dc35a10fSMarcin Wojtas /* Update rxq management counters */ 2218dc35a10fSMarcin Wojtas mvneta_rxq_desc_num_update(pp, rxq, rx_done, rx_done); 2219dc35a10fSMarcin Wojtas 2220dc35a10fSMarcin Wojtas return rx_done; 2221dc35a10fSMarcin Wojtas } 2222dc35a10fSMarcin Wojtas 22232adb719dSEzequiel Garcia static inline void 22242adb719dSEzequiel Garcia mvneta_tso_put_hdr(struct sk_buff *skb, 22252adb719dSEzequiel Garcia struct mvneta_port *pp, struct mvneta_tx_queue *txq) 22262adb719dSEzequiel Garcia { 22272adb719dSEzequiel Garcia struct mvneta_tx_desc *tx_desc; 22282adb719dSEzequiel Garcia int hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb); 22292adb719dSEzequiel Garcia 22302adb719dSEzequiel Garcia txq->tx_skb[txq->txq_put_index] = NULL; 22312adb719dSEzequiel Garcia tx_desc = mvneta_txq_next_desc_get(txq); 22322adb719dSEzequiel Garcia tx_desc->data_size = hdr_len; 22332adb719dSEzequiel Garcia tx_desc->command = mvneta_skb_tx_csum(pp, skb); 22342adb719dSEzequiel Garcia tx_desc->command |= MVNETA_TXD_F_DESC; 22352adb719dSEzequiel Garcia tx_desc->buf_phys_addr = txq->tso_hdrs_phys + 22362adb719dSEzequiel Garcia txq->txq_put_index * TSO_HEADER_SIZE; 22372adb719dSEzequiel Garcia mvneta_txq_inc_put(txq); 22382adb719dSEzequiel Garcia } 22392adb719dSEzequiel Garcia 22402adb719dSEzequiel Garcia static inline int 22412adb719dSEzequiel Garcia mvneta_tso_put_data(struct net_device *dev, struct mvneta_tx_queue *txq, 22422adb719dSEzequiel Garcia struct sk_buff *skb, char *data, int size, 22432adb719dSEzequiel Garcia bool last_tcp, bool is_last) 22442adb719dSEzequiel Garcia { 22452adb719dSEzequiel Garcia struct mvneta_tx_desc *tx_desc; 22462adb719dSEzequiel Garcia 22472adb719dSEzequiel Garcia tx_desc = mvneta_txq_next_desc_get(txq); 22482adb719dSEzequiel Garcia tx_desc->data_size = size; 22492adb719dSEzequiel Garcia tx_desc->buf_phys_addr = dma_map_single(dev->dev.parent, data, 22502adb719dSEzequiel Garcia size, DMA_TO_DEVICE); 22512adb719dSEzequiel Garcia if (unlikely(dma_mapping_error(dev->dev.parent, 22522adb719dSEzequiel Garcia tx_desc->buf_phys_addr))) { 22532adb719dSEzequiel Garcia mvneta_txq_desc_put(txq); 22542adb719dSEzequiel Garcia return -ENOMEM; 22552adb719dSEzequiel Garcia } 22562adb719dSEzequiel Garcia 22572adb719dSEzequiel Garcia tx_desc->command = 0; 22582adb719dSEzequiel Garcia txq->tx_skb[txq->txq_put_index] = NULL; 22592adb719dSEzequiel Garcia 22602adb719dSEzequiel Garcia if (last_tcp) { 22612adb719dSEzequiel Garcia /* last descriptor in the TCP packet */ 22622adb719dSEzequiel Garcia tx_desc->command = MVNETA_TXD_L_DESC; 22632adb719dSEzequiel Garcia 22642adb719dSEzequiel Garcia /* last descriptor in SKB */ 22652adb719dSEzequiel Garcia if (is_last) 22662adb719dSEzequiel Garcia txq->tx_skb[txq->txq_put_index] = skb; 22672adb719dSEzequiel Garcia } 22682adb719dSEzequiel Garcia mvneta_txq_inc_put(txq); 22692adb719dSEzequiel Garcia return 0; 22702adb719dSEzequiel Garcia } 22712adb719dSEzequiel Garcia 22722adb719dSEzequiel Garcia static int mvneta_tx_tso(struct sk_buff *skb, struct net_device *dev, 22732adb719dSEzequiel Garcia struct mvneta_tx_queue *txq) 22742adb719dSEzequiel Garcia { 22752adb719dSEzequiel Garcia int total_len, data_left; 22762adb719dSEzequiel Garcia int desc_count = 0; 22772adb719dSEzequiel Garcia struct mvneta_port *pp = netdev_priv(dev); 22782adb719dSEzequiel Garcia struct tso_t tso; 22792adb719dSEzequiel Garcia int hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb); 22802adb719dSEzequiel Garcia int i; 22812adb719dSEzequiel Garcia 22822adb719dSEzequiel Garcia /* Count needed descriptors */ 22832adb719dSEzequiel Garcia if ((txq->count + tso_count_descs(skb)) >= txq->size) 22842adb719dSEzequiel Garcia return 0; 22852adb719dSEzequiel Garcia 22862adb719dSEzequiel Garcia if (skb_headlen(skb) < (skb_transport_offset(skb) + tcp_hdrlen(skb))) { 22872adb719dSEzequiel Garcia pr_info("*** Is this even possible???!?!?\n"); 22882adb719dSEzequiel Garcia return 0; 22892adb719dSEzequiel Garcia } 22902adb719dSEzequiel Garcia 22912adb719dSEzequiel Garcia /* Initialize the TSO handler, and prepare the first payload */ 22922adb719dSEzequiel Garcia tso_start(skb, &tso); 22932adb719dSEzequiel Garcia 22942adb719dSEzequiel Garcia total_len = skb->len - hdr_len; 22952adb719dSEzequiel Garcia while (total_len > 0) { 22962adb719dSEzequiel Garcia char *hdr; 22972adb719dSEzequiel Garcia 22982adb719dSEzequiel Garcia data_left = min_t(int, skb_shinfo(skb)->gso_size, total_len); 22992adb719dSEzequiel Garcia total_len -= data_left; 23002adb719dSEzequiel Garcia desc_count++; 23012adb719dSEzequiel Garcia 23022adb719dSEzequiel Garcia /* prepare packet headers: MAC + IP + TCP */ 23032adb719dSEzequiel Garcia hdr = txq->tso_hdrs + txq->txq_put_index * TSO_HEADER_SIZE; 23042adb719dSEzequiel Garcia tso_build_hdr(skb, hdr, &tso, data_left, total_len == 0); 23052adb719dSEzequiel Garcia 23062adb719dSEzequiel Garcia mvneta_tso_put_hdr(skb, pp, txq); 23072adb719dSEzequiel Garcia 23082adb719dSEzequiel Garcia while (data_left > 0) { 23092adb719dSEzequiel Garcia int size; 23102adb719dSEzequiel Garcia desc_count++; 23112adb719dSEzequiel Garcia 23122adb719dSEzequiel Garcia size = min_t(int, tso.size, data_left); 23132adb719dSEzequiel Garcia 23142adb719dSEzequiel Garcia if (mvneta_tso_put_data(dev, txq, skb, 23152adb719dSEzequiel Garcia tso.data, size, 23162adb719dSEzequiel Garcia size == data_left, 23172adb719dSEzequiel Garcia total_len == 0)) 23182adb719dSEzequiel Garcia goto err_release; 23192adb719dSEzequiel Garcia data_left -= size; 23202adb719dSEzequiel Garcia 23212adb719dSEzequiel Garcia tso_build_data(skb, &tso, size); 23222adb719dSEzequiel Garcia } 23232adb719dSEzequiel Garcia } 23242adb719dSEzequiel Garcia 23252adb719dSEzequiel Garcia return desc_count; 23262adb719dSEzequiel Garcia 23272adb719dSEzequiel Garcia err_release: 23282adb719dSEzequiel Garcia /* Release all used data descriptors; header descriptors must not 23292adb719dSEzequiel Garcia * be DMA-unmapped. 23302adb719dSEzequiel Garcia */ 23312adb719dSEzequiel Garcia for (i = desc_count - 1; i >= 0; i--) { 23322adb719dSEzequiel Garcia struct mvneta_tx_desc *tx_desc = txq->descs + i; 23332e3173a3SEzequiel Garcia if (!IS_TSO_HEADER(txq, tx_desc->buf_phys_addr)) 23342adb719dSEzequiel Garcia dma_unmap_single(pp->dev->dev.parent, 23352adb719dSEzequiel Garcia tx_desc->buf_phys_addr, 23362adb719dSEzequiel Garcia tx_desc->data_size, 23372adb719dSEzequiel Garcia DMA_TO_DEVICE); 23382adb719dSEzequiel Garcia mvneta_txq_desc_put(txq); 23392adb719dSEzequiel Garcia } 23402adb719dSEzequiel Garcia return 0; 23412adb719dSEzequiel Garcia } 23422adb719dSEzequiel Garcia 2343c5aff182SThomas Petazzoni /* Handle tx fragmentation processing */ 2344c5aff182SThomas Petazzoni static int mvneta_tx_frag_process(struct mvneta_port *pp, struct sk_buff *skb, 2345c5aff182SThomas Petazzoni struct mvneta_tx_queue *txq) 2346c5aff182SThomas Petazzoni { 2347c5aff182SThomas Petazzoni struct mvneta_tx_desc *tx_desc; 23483d4ea02fSEzequiel Garcia int i, nr_frags = skb_shinfo(skb)->nr_frags; 2349c5aff182SThomas Petazzoni 23503d4ea02fSEzequiel Garcia for (i = 0; i < nr_frags; i++) { 2351c5aff182SThomas Petazzoni skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 2352c5aff182SThomas Petazzoni void *addr = page_address(frag->page.p) + frag->page_offset; 2353c5aff182SThomas Petazzoni 2354c5aff182SThomas Petazzoni tx_desc = mvneta_txq_next_desc_get(txq); 2355c5aff182SThomas Petazzoni tx_desc->data_size = frag->size; 2356c5aff182SThomas Petazzoni 2357c5aff182SThomas Petazzoni tx_desc->buf_phys_addr = 2358c5aff182SThomas Petazzoni dma_map_single(pp->dev->dev.parent, addr, 2359c5aff182SThomas Petazzoni tx_desc->data_size, DMA_TO_DEVICE); 2360c5aff182SThomas Petazzoni 2361c5aff182SThomas Petazzoni if (dma_mapping_error(pp->dev->dev.parent, 2362c5aff182SThomas Petazzoni tx_desc->buf_phys_addr)) { 2363c5aff182SThomas Petazzoni mvneta_txq_desc_put(txq); 2364c5aff182SThomas Petazzoni goto error; 2365c5aff182SThomas Petazzoni } 2366c5aff182SThomas Petazzoni 23673d4ea02fSEzequiel Garcia if (i == nr_frags - 1) { 2368c5aff182SThomas Petazzoni /* Last descriptor */ 2369c5aff182SThomas Petazzoni tx_desc->command = MVNETA_TXD_L_DESC | MVNETA_TXD_Z_PAD; 2370c5aff182SThomas Petazzoni txq->tx_skb[txq->txq_put_index] = skb; 2371c5aff182SThomas Petazzoni } else { 2372c5aff182SThomas Petazzoni /* Descriptor in the middle: Not First, Not Last */ 2373c5aff182SThomas Petazzoni tx_desc->command = 0; 2374c5aff182SThomas Petazzoni txq->tx_skb[txq->txq_put_index] = NULL; 2375c5aff182SThomas Petazzoni } 23763d4ea02fSEzequiel Garcia mvneta_txq_inc_put(txq); 2377c5aff182SThomas Petazzoni } 2378c5aff182SThomas Petazzoni 2379c5aff182SThomas Petazzoni return 0; 2380c5aff182SThomas Petazzoni 2381c5aff182SThomas Petazzoni error: 2382c5aff182SThomas Petazzoni /* Release all descriptors that were used to map fragments of 23836a20c175SThomas Petazzoni * this packet, as well as the corresponding DMA mappings 23846a20c175SThomas Petazzoni */ 2385c5aff182SThomas Petazzoni for (i = i - 1; i >= 0; i--) { 2386c5aff182SThomas Petazzoni tx_desc = txq->descs + i; 2387c5aff182SThomas Petazzoni dma_unmap_single(pp->dev->dev.parent, 2388c5aff182SThomas Petazzoni tx_desc->buf_phys_addr, 2389c5aff182SThomas Petazzoni tx_desc->data_size, 2390c5aff182SThomas Petazzoni DMA_TO_DEVICE); 2391c5aff182SThomas Petazzoni mvneta_txq_desc_put(txq); 2392c5aff182SThomas Petazzoni } 2393c5aff182SThomas Petazzoni 2394c5aff182SThomas Petazzoni return -ENOMEM; 2395c5aff182SThomas Petazzoni } 2396c5aff182SThomas Petazzoni 2397c5aff182SThomas Petazzoni /* Main tx processing */ 2398f03508ceSYueHaibing static netdev_tx_t mvneta_tx(struct sk_buff *skb, struct net_device *dev) 2399c5aff182SThomas Petazzoni { 2400c5aff182SThomas Petazzoni struct mvneta_port *pp = netdev_priv(dev); 2401ee40a116SWilly Tarreau u16 txq_id = skb_get_queue_mapping(skb); 2402ee40a116SWilly Tarreau struct mvneta_tx_queue *txq = &pp->txqs[txq_id]; 2403c5aff182SThomas Petazzoni struct mvneta_tx_desc *tx_desc; 24045f478b41SEric Dumazet int len = skb->len; 2405c5aff182SThomas Petazzoni int frags = 0; 2406c5aff182SThomas Petazzoni u32 tx_cmd; 2407c5aff182SThomas Petazzoni 2408c5aff182SThomas Petazzoni if (!netif_running(dev)) 2409c5aff182SThomas Petazzoni goto out; 2410c5aff182SThomas Petazzoni 24112adb719dSEzequiel Garcia if (skb_is_gso(skb)) { 24122adb719dSEzequiel Garcia frags = mvneta_tx_tso(skb, dev, txq); 24132adb719dSEzequiel Garcia goto out; 24142adb719dSEzequiel Garcia } 24152adb719dSEzequiel Garcia 2416c5aff182SThomas Petazzoni frags = skb_shinfo(skb)->nr_frags + 1; 2417c5aff182SThomas Petazzoni 2418c5aff182SThomas Petazzoni /* Get a descriptor for the first part of the packet */ 2419c5aff182SThomas Petazzoni tx_desc = mvneta_txq_next_desc_get(txq); 2420c5aff182SThomas Petazzoni 2421c5aff182SThomas Petazzoni tx_cmd = mvneta_skb_tx_csum(pp, skb); 2422c5aff182SThomas Petazzoni 2423c5aff182SThomas Petazzoni tx_desc->data_size = skb_headlen(skb); 2424c5aff182SThomas Petazzoni 2425c5aff182SThomas Petazzoni tx_desc->buf_phys_addr = dma_map_single(dev->dev.parent, skb->data, 2426c5aff182SThomas Petazzoni tx_desc->data_size, 2427c5aff182SThomas Petazzoni DMA_TO_DEVICE); 2428c5aff182SThomas Petazzoni if (unlikely(dma_mapping_error(dev->dev.parent, 2429c5aff182SThomas Petazzoni tx_desc->buf_phys_addr))) { 2430c5aff182SThomas Petazzoni mvneta_txq_desc_put(txq); 2431c5aff182SThomas Petazzoni frags = 0; 2432c5aff182SThomas Petazzoni goto out; 2433c5aff182SThomas Petazzoni } 2434c5aff182SThomas Petazzoni 2435c5aff182SThomas Petazzoni if (frags == 1) { 2436c5aff182SThomas Petazzoni /* First and Last descriptor */ 2437c5aff182SThomas Petazzoni tx_cmd |= MVNETA_TXD_FLZ_DESC; 2438c5aff182SThomas Petazzoni tx_desc->command = tx_cmd; 2439c5aff182SThomas Petazzoni txq->tx_skb[txq->txq_put_index] = skb; 2440c5aff182SThomas Petazzoni mvneta_txq_inc_put(txq); 2441c5aff182SThomas Petazzoni } else { 2442c5aff182SThomas Petazzoni /* First but not Last */ 2443c5aff182SThomas Petazzoni tx_cmd |= MVNETA_TXD_F_DESC; 2444c5aff182SThomas Petazzoni txq->tx_skb[txq->txq_put_index] = NULL; 2445c5aff182SThomas Petazzoni mvneta_txq_inc_put(txq); 2446c5aff182SThomas Petazzoni tx_desc->command = tx_cmd; 2447c5aff182SThomas Petazzoni /* Continue with other skb fragments */ 2448c5aff182SThomas Petazzoni if (mvneta_tx_frag_process(pp, skb, txq)) { 2449c5aff182SThomas Petazzoni dma_unmap_single(dev->dev.parent, 2450c5aff182SThomas Petazzoni tx_desc->buf_phys_addr, 2451c5aff182SThomas Petazzoni tx_desc->data_size, 2452c5aff182SThomas Petazzoni DMA_TO_DEVICE); 2453c5aff182SThomas Petazzoni mvneta_txq_desc_put(txq); 2454c5aff182SThomas Petazzoni frags = 0; 2455c5aff182SThomas Petazzoni goto out; 2456c5aff182SThomas Petazzoni } 2457c5aff182SThomas Petazzoni } 2458c5aff182SThomas Petazzoni 2459e19d2ddaSEzequiel Garcia out: 2460e19d2ddaSEzequiel Garcia if (frags > 0) { 2461e19d2ddaSEzequiel Garcia struct mvneta_pcpu_stats *stats = this_cpu_ptr(pp->stats); 2462e19d2ddaSEzequiel Garcia struct netdev_queue *nq = netdev_get_tx_queue(dev, txq_id); 2463e19d2ddaSEzequiel Garcia 2464a29b6235SMarcin Wojtas netdev_tx_sent_queue(nq, len); 2465a29b6235SMarcin Wojtas 2466c5aff182SThomas Petazzoni txq->count += frags; 24678eef5f97SEzequiel Garcia if (txq->count >= txq->tx_stop_threshold) 2468c5aff182SThomas Petazzoni netif_tx_stop_queue(nq); 2469c5aff182SThomas Petazzoni 24706b16f9eeSFlorian Westphal if (!netdev_xmit_more() || netif_xmit_stopped(nq) || 24712a90f7e1SSimon Guinot txq->pending + frags > MVNETA_TXQ_DEC_SENT_MASK) 24722a90f7e1SSimon Guinot mvneta_txq_pend_desc_add(pp, txq, frags); 24732a90f7e1SSimon Guinot else 24742a90f7e1SSimon Guinot txq->pending += frags; 24752a90f7e1SSimon Guinot 247674c41b04Swilly tarreau u64_stats_update_begin(&stats->syncp); 247774c41b04Swilly tarreau stats->tx_packets++; 24785f478b41SEric Dumazet stats->tx_bytes += len; 247974c41b04Swilly tarreau u64_stats_update_end(&stats->syncp); 2480c5aff182SThomas Petazzoni } else { 2481c5aff182SThomas Petazzoni dev->stats.tx_dropped++; 2482c5aff182SThomas Petazzoni dev_kfree_skb_any(skb); 2483c5aff182SThomas Petazzoni } 2484c5aff182SThomas Petazzoni 2485c5aff182SThomas Petazzoni return NETDEV_TX_OK; 2486c5aff182SThomas Petazzoni } 2487c5aff182SThomas Petazzoni 2488c5aff182SThomas Petazzoni 2489c5aff182SThomas Petazzoni /* Free tx resources, when resetting a port */ 2490c5aff182SThomas Petazzoni static void mvneta_txq_done_force(struct mvneta_port *pp, 2491c5aff182SThomas Petazzoni struct mvneta_tx_queue *txq) 2492c5aff182SThomas Petazzoni 2493c5aff182SThomas Petazzoni { 2494a29b6235SMarcin Wojtas struct netdev_queue *nq = netdev_get_tx_queue(pp->dev, txq->id); 2495c5aff182SThomas Petazzoni int tx_done = txq->count; 2496c5aff182SThomas Petazzoni 2497a29b6235SMarcin Wojtas mvneta_txq_bufs_free(pp, txq, tx_done, nq); 2498c5aff182SThomas Petazzoni 2499c5aff182SThomas Petazzoni /* reset txq */ 2500c5aff182SThomas Petazzoni txq->count = 0; 2501c5aff182SThomas Petazzoni txq->txq_put_index = 0; 2502c5aff182SThomas Petazzoni txq->txq_get_index = 0; 2503c5aff182SThomas Petazzoni } 2504c5aff182SThomas Petazzoni 25056c498974Swilly tarreau /* Handle tx done - called in softirq context. The <cause_tx_done> argument 25066c498974Swilly tarreau * must be a valid cause according to MVNETA_TXQ_INTR_MASK_ALL. 25076c498974Swilly tarreau */ 25080713a86aSArnaud Ebalard static void mvneta_tx_done_gbe(struct mvneta_port *pp, u32 cause_tx_done) 2509c5aff182SThomas Petazzoni { 2510c5aff182SThomas Petazzoni struct mvneta_tx_queue *txq; 2511c5aff182SThomas Petazzoni struct netdev_queue *nq; 2512bd9f1ee3SJisheng Zhang int cpu = smp_processor_id(); 2513c5aff182SThomas Petazzoni 25146c498974Swilly tarreau while (cause_tx_done) { 2515c5aff182SThomas Petazzoni txq = mvneta_tx_done_policy(pp, cause_tx_done); 2516c5aff182SThomas Petazzoni 2517c5aff182SThomas Petazzoni nq = netdev_get_tx_queue(pp->dev, txq->id); 2518bd9f1ee3SJisheng Zhang __netif_tx_lock(nq, cpu); 2519c5aff182SThomas Petazzoni 25200713a86aSArnaud Ebalard if (txq->count) 25210713a86aSArnaud Ebalard mvneta_txq_done(pp, txq); 2522c5aff182SThomas Petazzoni 2523c5aff182SThomas Petazzoni __netif_tx_unlock(nq); 2524c5aff182SThomas Petazzoni cause_tx_done &= ~((1 << txq->id)); 2525c5aff182SThomas Petazzoni } 2526c5aff182SThomas Petazzoni } 2527c5aff182SThomas Petazzoni 25286a20c175SThomas Petazzoni /* Compute crc8 of the specified address, using a unique algorithm , 2529c5aff182SThomas Petazzoni * according to hw spec, different than generic crc8 algorithm 2530c5aff182SThomas Petazzoni */ 2531c5aff182SThomas Petazzoni static int mvneta_addr_crc(unsigned char *addr) 2532c5aff182SThomas Petazzoni { 2533c5aff182SThomas Petazzoni int crc = 0; 2534c5aff182SThomas Petazzoni int i; 2535c5aff182SThomas Petazzoni 2536c5aff182SThomas Petazzoni for (i = 0; i < ETH_ALEN; i++) { 2537c5aff182SThomas Petazzoni int j; 2538c5aff182SThomas Petazzoni 2539c5aff182SThomas Petazzoni crc = (crc ^ addr[i]) << 8; 2540c5aff182SThomas Petazzoni for (j = 7; j >= 0; j--) { 2541c5aff182SThomas Petazzoni if (crc & (0x100 << j)) 2542c5aff182SThomas Petazzoni crc ^= 0x107 << j; 2543c5aff182SThomas Petazzoni } 2544c5aff182SThomas Petazzoni } 2545c5aff182SThomas Petazzoni 2546c5aff182SThomas Petazzoni return crc; 2547c5aff182SThomas Petazzoni } 2548c5aff182SThomas Petazzoni 2549c5aff182SThomas Petazzoni /* This method controls the net device special MAC multicast support. 2550c5aff182SThomas Petazzoni * The Special Multicast Table for MAC addresses supports MAC of the form 2551c5aff182SThomas Petazzoni * 0x01-00-5E-00-00-XX (where XX is between 0x00 and 0xFF). 2552c5aff182SThomas Petazzoni * The MAC DA[7:0] bits are used as a pointer to the Special Multicast 2553c5aff182SThomas Petazzoni * Table entries in the DA-Filter table. This method set the Special 2554c5aff182SThomas Petazzoni * Multicast Table appropriate entry. 2555c5aff182SThomas Petazzoni */ 2556c5aff182SThomas Petazzoni static void mvneta_set_special_mcast_addr(struct mvneta_port *pp, 2557c5aff182SThomas Petazzoni unsigned char last_byte, 2558c5aff182SThomas Petazzoni int queue) 2559c5aff182SThomas Petazzoni { 2560c5aff182SThomas Petazzoni unsigned int smc_table_reg; 2561c5aff182SThomas Petazzoni unsigned int tbl_offset; 2562c5aff182SThomas Petazzoni unsigned int reg_offset; 2563c5aff182SThomas Petazzoni 2564c5aff182SThomas Petazzoni /* Register offset from SMC table base */ 2565c5aff182SThomas Petazzoni tbl_offset = (last_byte / 4); 2566c5aff182SThomas Petazzoni /* Entry offset within the above reg */ 2567c5aff182SThomas Petazzoni reg_offset = last_byte % 4; 2568c5aff182SThomas Petazzoni 2569c5aff182SThomas Petazzoni smc_table_reg = mvreg_read(pp, (MVNETA_DA_FILT_SPEC_MCAST 2570c5aff182SThomas Petazzoni + tbl_offset * 4)); 2571c5aff182SThomas Petazzoni 2572c5aff182SThomas Petazzoni if (queue == -1) 2573c5aff182SThomas Petazzoni smc_table_reg &= ~(0xff << (8 * reg_offset)); 2574c5aff182SThomas Petazzoni else { 2575c5aff182SThomas Petazzoni smc_table_reg &= ~(0xff << (8 * reg_offset)); 2576c5aff182SThomas Petazzoni smc_table_reg |= ((0x01 | (queue << 1)) << (8 * reg_offset)); 2577c5aff182SThomas Petazzoni } 2578c5aff182SThomas Petazzoni 2579c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_DA_FILT_SPEC_MCAST + tbl_offset * 4, 2580c5aff182SThomas Petazzoni smc_table_reg); 2581c5aff182SThomas Petazzoni } 2582c5aff182SThomas Petazzoni 2583c5aff182SThomas Petazzoni /* This method controls the network device Other MAC multicast support. 2584c5aff182SThomas Petazzoni * The Other Multicast Table is used for multicast of another type. 2585c5aff182SThomas Petazzoni * A CRC-8 is used as an index to the Other Multicast Table entries 2586c5aff182SThomas Petazzoni * in the DA-Filter table. 2587c5aff182SThomas Petazzoni * The method gets the CRC-8 value from the calling routine and 2588c5aff182SThomas Petazzoni * sets the Other Multicast Table appropriate entry according to the 2589c5aff182SThomas Petazzoni * specified CRC-8 . 2590c5aff182SThomas Petazzoni */ 2591c5aff182SThomas Petazzoni static void mvneta_set_other_mcast_addr(struct mvneta_port *pp, 2592c5aff182SThomas Petazzoni unsigned char crc8, 2593c5aff182SThomas Petazzoni int queue) 2594c5aff182SThomas Petazzoni { 2595c5aff182SThomas Petazzoni unsigned int omc_table_reg; 2596c5aff182SThomas Petazzoni unsigned int tbl_offset; 2597c5aff182SThomas Petazzoni unsigned int reg_offset; 2598c5aff182SThomas Petazzoni 2599c5aff182SThomas Petazzoni tbl_offset = (crc8 / 4) * 4; /* Register offset from OMC table base */ 2600c5aff182SThomas Petazzoni reg_offset = crc8 % 4; /* Entry offset within the above reg */ 2601c5aff182SThomas Petazzoni 2602c5aff182SThomas Petazzoni omc_table_reg = mvreg_read(pp, MVNETA_DA_FILT_OTH_MCAST + tbl_offset); 2603c5aff182SThomas Petazzoni 2604c5aff182SThomas Petazzoni if (queue == -1) { 2605c5aff182SThomas Petazzoni /* Clear accepts frame bit at specified Other DA table entry */ 2606c5aff182SThomas Petazzoni omc_table_reg &= ~(0xff << (8 * reg_offset)); 2607c5aff182SThomas Petazzoni } else { 2608c5aff182SThomas Petazzoni omc_table_reg &= ~(0xff << (8 * reg_offset)); 2609c5aff182SThomas Petazzoni omc_table_reg |= ((0x01 | (queue << 1)) << (8 * reg_offset)); 2610c5aff182SThomas Petazzoni } 2611c5aff182SThomas Petazzoni 2612c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_DA_FILT_OTH_MCAST + tbl_offset, omc_table_reg); 2613c5aff182SThomas Petazzoni } 2614c5aff182SThomas Petazzoni 2615c5aff182SThomas Petazzoni /* The network device supports multicast using two tables: 2616c5aff182SThomas Petazzoni * 1) Special Multicast Table for MAC addresses of the form 2617c5aff182SThomas Petazzoni * 0x01-00-5E-00-00-XX (where XX is between 0x00 and 0xFF). 2618c5aff182SThomas Petazzoni * The MAC DA[7:0] bits are used as a pointer to the Special Multicast 2619c5aff182SThomas Petazzoni * Table entries in the DA-Filter table. 2620c5aff182SThomas Petazzoni * 2) Other Multicast Table for multicast of another type. A CRC-8 value 2621c5aff182SThomas Petazzoni * is used as an index to the Other Multicast Table entries in the 2622c5aff182SThomas Petazzoni * DA-Filter table. 2623c5aff182SThomas Petazzoni */ 2624c5aff182SThomas Petazzoni static int mvneta_mcast_addr_set(struct mvneta_port *pp, unsigned char *p_addr, 2625c5aff182SThomas Petazzoni int queue) 2626c5aff182SThomas Petazzoni { 2627c5aff182SThomas Petazzoni unsigned char crc_result = 0; 2628c5aff182SThomas Petazzoni 2629c5aff182SThomas Petazzoni if (memcmp(p_addr, "\x01\x00\x5e\x00\x00", 5) == 0) { 2630c5aff182SThomas Petazzoni mvneta_set_special_mcast_addr(pp, p_addr[5], queue); 2631c5aff182SThomas Petazzoni return 0; 2632c5aff182SThomas Petazzoni } 2633c5aff182SThomas Petazzoni 2634c5aff182SThomas Petazzoni crc_result = mvneta_addr_crc(p_addr); 2635c5aff182SThomas Petazzoni if (queue == -1) { 2636c5aff182SThomas Petazzoni if (pp->mcast_count[crc_result] == 0) { 2637c5aff182SThomas Petazzoni netdev_info(pp->dev, "No valid Mcast for crc8=0x%02x\n", 2638c5aff182SThomas Petazzoni crc_result); 2639c5aff182SThomas Petazzoni return -EINVAL; 2640c5aff182SThomas Petazzoni } 2641c5aff182SThomas Petazzoni 2642c5aff182SThomas Petazzoni pp->mcast_count[crc_result]--; 2643c5aff182SThomas Petazzoni if (pp->mcast_count[crc_result] != 0) { 2644c5aff182SThomas Petazzoni netdev_info(pp->dev, 2645c5aff182SThomas Petazzoni "After delete there are %d valid Mcast for crc8=0x%02x\n", 2646c5aff182SThomas Petazzoni pp->mcast_count[crc_result], crc_result); 2647c5aff182SThomas Petazzoni return -EINVAL; 2648c5aff182SThomas Petazzoni } 2649c5aff182SThomas Petazzoni } else 2650c5aff182SThomas Petazzoni pp->mcast_count[crc_result]++; 2651c5aff182SThomas Petazzoni 2652c5aff182SThomas Petazzoni mvneta_set_other_mcast_addr(pp, crc_result, queue); 2653c5aff182SThomas Petazzoni 2654c5aff182SThomas Petazzoni return 0; 2655c5aff182SThomas Petazzoni } 2656c5aff182SThomas Petazzoni 2657c5aff182SThomas Petazzoni /* Configure Fitering mode of Ethernet port */ 2658c5aff182SThomas Petazzoni static void mvneta_rx_unicast_promisc_set(struct mvneta_port *pp, 2659c5aff182SThomas Petazzoni int is_promisc) 2660c5aff182SThomas Petazzoni { 2661c5aff182SThomas Petazzoni u32 port_cfg_reg, val; 2662c5aff182SThomas Petazzoni 2663c5aff182SThomas Petazzoni port_cfg_reg = mvreg_read(pp, MVNETA_PORT_CONFIG); 2664c5aff182SThomas Petazzoni 2665c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_TYPE_PRIO); 2666c5aff182SThomas Petazzoni 2667c5aff182SThomas Petazzoni /* Set / Clear UPM bit in port configuration register */ 2668c5aff182SThomas Petazzoni if (is_promisc) { 2669c5aff182SThomas Petazzoni /* Accept all Unicast addresses */ 2670c5aff182SThomas Petazzoni port_cfg_reg |= MVNETA_UNI_PROMISC_MODE; 2671c5aff182SThomas Petazzoni val |= MVNETA_FORCE_UNI; 2672c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_MAC_ADDR_LOW, 0xffff); 2673c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_MAC_ADDR_HIGH, 0xffffffff); 2674c5aff182SThomas Petazzoni } else { 2675c5aff182SThomas Petazzoni /* Reject all Unicast addresses */ 2676c5aff182SThomas Petazzoni port_cfg_reg &= ~MVNETA_UNI_PROMISC_MODE; 2677c5aff182SThomas Petazzoni val &= ~MVNETA_FORCE_UNI; 2678c5aff182SThomas Petazzoni } 2679c5aff182SThomas Petazzoni 2680c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_PORT_CONFIG, port_cfg_reg); 2681c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_TYPE_PRIO, val); 2682c5aff182SThomas Petazzoni } 2683c5aff182SThomas Petazzoni 2684c5aff182SThomas Petazzoni /* register unicast and multicast addresses */ 2685c5aff182SThomas Petazzoni static void mvneta_set_rx_mode(struct net_device *dev) 2686c5aff182SThomas Petazzoni { 2687c5aff182SThomas Petazzoni struct mvneta_port *pp = netdev_priv(dev); 2688c5aff182SThomas Petazzoni struct netdev_hw_addr *ha; 2689c5aff182SThomas Petazzoni 2690c5aff182SThomas Petazzoni if (dev->flags & IFF_PROMISC) { 2691c5aff182SThomas Petazzoni /* Accept all: Multicast + Unicast */ 2692c5aff182SThomas Petazzoni mvneta_rx_unicast_promisc_set(pp, 1); 269390b74c01SGregory CLEMENT mvneta_set_ucast_table(pp, pp->rxq_def); 269490b74c01SGregory CLEMENT mvneta_set_special_mcast_table(pp, pp->rxq_def); 269590b74c01SGregory CLEMENT mvneta_set_other_mcast_table(pp, pp->rxq_def); 2696c5aff182SThomas Petazzoni } else { 2697c5aff182SThomas Petazzoni /* Accept single Unicast */ 2698c5aff182SThomas Petazzoni mvneta_rx_unicast_promisc_set(pp, 0); 2699c5aff182SThomas Petazzoni mvneta_set_ucast_table(pp, -1); 270090b74c01SGregory CLEMENT mvneta_mac_addr_set(pp, dev->dev_addr, pp->rxq_def); 2701c5aff182SThomas Petazzoni 2702c5aff182SThomas Petazzoni if (dev->flags & IFF_ALLMULTI) { 2703c5aff182SThomas Petazzoni /* Accept all multicast */ 270490b74c01SGregory CLEMENT mvneta_set_special_mcast_table(pp, pp->rxq_def); 270590b74c01SGregory CLEMENT mvneta_set_other_mcast_table(pp, pp->rxq_def); 2706c5aff182SThomas Petazzoni } else { 2707c5aff182SThomas Petazzoni /* Accept only initialized multicast */ 2708c5aff182SThomas Petazzoni mvneta_set_special_mcast_table(pp, -1); 2709c5aff182SThomas Petazzoni mvneta_set_other_mcast_table(pp, -1); 2710c5aff182SThomas Petazzoni 2711c5aff182SThomas Petazzoni if (!netdev_mc_empty(dev)) { 2712c5aff182SThomas Petazzoni netdev_for_each_mc_addr(ha, dev) { 2713c5aff182SThomas Petazzoni mvneta_mcast_addr_set(pp, ha->addr, 271490b74c01SGregory CLEMENT pp->rxq_def); 2715c5aff182SThomas Petazzoni } 2716c5aff182SThomas Petazzoni } 2717c5aff182SThomas Petazzoni } 2718c5aff182SThomas Petazzoni } 2719c5aff182SThomas Petazzoni } 2720c5aff182SThomas Petazzoni 2721c5aff182SThomas Petazzoni /* Interrupt handling - the callback for request_irq() */ 2722c5aff182SThomas Petazzoni static irqreturn_t mvneta_isr(int irq, void *dev_id) 2723c5aff182SThomas Petazzoni { 27242636ac3cSMarcin Wojtas struct mvneta_port *pp = (struct mvneta_port *)dev_id; 27252636ac3cSMarcin Wojtas 27262636ac3cSMarcin Wojtas mvreg_write(pp, MVNETA_INTR_NEW_MASK, 0); 27272636ac3cSMarcin Wojtas napi_schedule(&pp->napi); 27282636ac3cSMarcin Wojtas 27292636ac3cSMarcin Wojtas return IRQ_HANDLED; 27302636ac3cSMarcin Wojtas } 27312636ac3cSMarcin Wojtas 27322636ac3cSMarcin Wojtas /* Interrupt handling - the callback for request_percpu_irq() */ 27332636ac3cSMarcin Wojtas static irqreturn_t mvneta_percpu_isr(int irq, void *dev_id) 27342636ac3cSMarcin Wojtas { 273512bb03b4SMaxime Ripard struct mvneta_pcpu_port *port = (struct mvneta_pcpu_port *)dev_id; 2736c5aff182SThomas Petazzoni 273712bb03b4SMaxime Ripard disable_percpu_irq(port->pp->dev->irq); 273812bb03b4SMaxime Ripard napi_schedule(&port->napi); 2739c5aff182SThomas Petazzoni 2740c5aff182SThomas Petazzoni return IRQ_HANDLED; 2741c5aff182SThomas Petazzoni } 2742c5aff182SThomas Petazzoni 2743503f9aa9SRussell King static void mvneta_link_change(struct mvneta_port *pp) 2744898b2970SStas Sergeev { 2745898b2970SStas Sergeev u32 gmac_stat = mvreg_read(pp, MVNETA_GMAC_STATUS); 2746898b2970SStas Sergeev 2747503f9aa9SRussell King phylink_mac_change(pp->phylink, !!(gmac_stat & MVNETA_GMAC_LINK_UP)); 2748898b2970SStas Sergeev } 2749898b2970SStas Sergeev 2750c5aff182SThomas Petazzoni /* NAPI handler 2751c5aff182SThomas Petazzoni * Bits 0 - 7 of the causeRxTx register indicate that are transmitted 2752c5aff182SThomas Petazzoni * packets on the corresponding TXQ (Bit 0 is for TX queue 1). 2753c5aff182SThomas Petazzoni * Bits 8 -15 of the cause Rx Tx register indicate that are received 2754c5aff182SThomas Petazzoni * packets on the corresponding RXQ (Bit 8 is for RX queue 0). 2755c5aff182SThomas Petazzoni * Each CPU has its own causeRxTx register 2756c5aff182SThomas Petazzoni */ 2757c5aff182SThomas Petazzoni static int mvneta_poll(struct napi_struct *napi, int budget) 2758c5aff182SThomas Petazzoni { 2759c5aff182SThomas Petazzoni int rx_done = 0; 2760c5aff182SThomas Petazzoni u32 cause_rx_tx; 27612dcf75e2SGregory CLEMENT int rx_queue; 2762c5aff182SThomas Petazzoni struct mvneta_port *pp = netdev_priv(napi->dev); 276312bb03b4SMaxime Ripard struct mvneta_pcpu_port *port = this_cpu_ptr(pp->ports); 2764c5aff182SThomas Petazzoni 2765c5aff182SThomas Petazzoni if (!netif_running(pp->dev)) { 27662636ac3cSMarcin Wojtas napi_complete(napi); 2767c5aff182SThomas Petazzoni return rx_done; 2768c5aff182SThomas Petazzoni } 2769c5aff182SThomas Petazzoni 2770c5aff182SThomas Petazzoni /* Read cause register */ 2771898b2970SStas Sergeev cause_rx_tx = mvreg_read(pp, MVNETA_INTR_NEW_CAUSE); 2772898b2970SStas Sergeev if (cause_rx_tx & MVNETA_MISCINTR_INTR_MASK) { 2773898b2970SStas Sergeev u32 cause_misc = mvreg_read(pp, MVNETA_INTR_MISC_CAUSE); 2774898b2970SStas Sergeev 2775898b2970SStas Sergeev mvreg_write(pp, MVNETA_INTR_MISC_CAUSE, 0); 2776503f9aa9SRussell King 2777503f9aa9SRussell King if (cause_misc & (MVNETA_CAUSE_PHY_STATUS_CHANGE | 2778856b2cc5SRussell King MVNETA_CAUSE_LINK_CHANGE)) 2779503f9aa9SRussell King mvneta_link_change(pp); 2780898b2970SStas Sergeev } 278171f6d1b3Swilly tarreau 278271f6d1b3Swilly tarreau /* Release Tx descriptors */ 278371f6d1b3Swilly tarreau if (cause_rx_tx & MVNETA_TX_INTR_MASK_ALL) { 27840713a86aSArnaud Ebalard mvneta_tx_done_gbe(pp, (cause_rx_tx & MVNETA_TX_INTR_MASK_ALL)); 278571f6d1b3Swilly tarreau cause_rx_tx &= ~MVNETA_TX_INTR_MASK_ALL; 278671f6d1b3Swilly tarreau } 2787c5aff182SThomas Petazzoni 27886a20c175SThomas Petazzoni /* For the case where the last mvneta_poll did not process all 2789c5aff182SThomas Petazzoni * RX packets 2790c5aff182SThomas Petazzoni */ 27912dcf75e2SGregory CLEMENT rx_queue = fls(((cause_rx_tx >> 8) & 0xff)); 27922dcf75e2SGregory CLEMENT 27932636ac3cSMarcin Wojtas cause_rx_tx |= pp->neta_armada3700 ? pp->cause_rx_tx : 27942636ac3cSMarcin Wojtas port->cause_rx_tx; 27952dcf75e2SGregory CLEMENT 27962dcf75e2SGregory CLEMENT if (rx_queue) { 27972dcf75e2SGregory CLEMENT rx_queue = rx_queue - 1; 2798dc35a10fSMarcin Wojtas if (pp->bm_priv) 27997a86f05fSAndrew Lunn rx_done = mvneta_rx_hwbm(napi, pp, budget, 28007a86f05fSAndrew Lunn &pp->rxqs[rx_queue]); 2801dc35a10fSMarcin Wojtas else 28027a86f05fSAndrew Lunn rx_done = mvneta_rx_swbm(napi, pp, budget, 28037a86f05fSAndrew Lunn &pp->rxqs[rx_queue]); 28042dcf75e2SGregory CLEMENT } 28052dcf75e2SGregory CLEMENT 28066ad20165SEric Dumazet if (rx_done < budget) { 2807c5aff182SThomas Petazzoni cause_rx_tx = 0; 28086ad20165SEric Dumazet napi_complete_done(napi, rx_done); 28092636ac3cSMarcin Wojtas 28102636ac3cSMarcin Wojtas if (pp->neta_armada3700) { 28112636ac3cSMarcin Wojtas unsigned long flags; 28122636ac3cSMarcin Wojtas 28132636ac3cSMarcin Wojtas local_irq_save(flags); 28142636ac3cSMarcin Wojtas mvreg_write(pp, MVNETA_INTR_NEW_MASK, 28152636ac3cSMarcin Wojtas MVNETA_RX_INTR_MASK(rxq_number) | 28162636ac3cSMarcin Wojtas MVNETA_TX_INTR_MASK(txq_number) | 28172636ac3cSMarcin Wojtas MVNETA_MISCINTR_INTR_MASK); 28182636ac3cSMarcin Wojtas local_irq_restore(flags); 28192636ac3cSMarcin Wojtas } else { 282012bb03b4SMaxime Ripard enable_percpu_irq(pp->dev->irq, 0); 2821c5aff182SThomas Petazzoni } 28222636ac3cSMarcin Wojtas } 2823c5aff182SThomas Petazzoni 28242636ac3cSMarcin Wojtas if (pp->neta_armada3700) 28252636ac3cSMarcin Wojtas pp->cause_rx_tx = cause_rx_tx; 28262636ac3cSMarcin Wojtas else 282712bb03b4SMaxime Ripard port->cause_rx_tx = cause_rx_tx; 28282636ac3cSMarcin Wojtas 2829c5aff182SThomas Petazzoni return rx_done; 2830c5aff182SThomas Petazzoni } 2831c5aff182SThomas Petazzoni 2832c5aff182SThomas Petazzoni /* Handle rxq fill: allocates rxq skbs; called when initializing a port */ 2833c5aff182SThomas Petazzoni static int mvneta_rxq_fill(struct mvneta_port *pp, struct mvneta_rx_queue *rxq, 2834c5aff182SThomas Petazzoni int num) 2835c5aff182SThomas Petazzoni { 2836c5aff182SThomas Petazzoni int i; 2837c5aff182SThomas Petazzoni 2838c5aff182SThomas Petazzoni for (i = 0; i < num; i++) { 2839a1a65ab1Swilly tarreau memset(rxq->descs + i, 0, sizeof(struct mvneta_rx_desc)); 28407e47fd84SGregory CLEMENT if (mvneta_rx_refill(pp, rxq->descs + i, rxq, 28417e47fd84SGregory CLEMENT GFP_KERNEL) != 0) { 28427e47fd84SGregory CLEMENT netdev_err(pp->dev, 28437e47fd84SGregory CLEMENT "%s:rxq %d, %d of %d buffs filled\n", 2844c5aff182SThomas Petazzoni __func__, rxq->id, i, num); 2845c5aff182SThomas Petazzoni break; 2846c5aff182SThomas Petazzoni } 2847c5aff182SThomas Petazzoni } 2848c5aff182SThomas Petazzoni 2849c5aff182SThomas Petazzoni /* Add this number of RX descriptors as non occupied (ready to 28506a20c175SThomas Petazzoni * get packets) 28516a20c175SThomas Petazzoni */ 2852c5aff182SThomas Petazzoni mvneta_rxq_non_occup_desc_add(pp, rxq, i); 2853c5aff182SThomas Petazzoni 2854c5aff182SThomas Petazzoni return i; 2855c5aff182SThomas Petazzoni } 2856c5aff182SThomas Petazzoni 2857c5aff182SThomas Petazzoni /* Free all packets pending transmit from all TXQs and reset TX port */ 2858c5aff182SThomas Petazzoni static void mvneta_tx_reset(struct mvneta_port *pp) 2859c5aff182SThomas Petazzoni { 2860c5aff182SThomas Petazzoni int queue; 2861c5aff182SThomas Petazzoni 28629672850bSEzequiel Garcia /* free the skb's in the tx ring */ 2863c5aff182SThomas Petazzoni for (queue = 0; queue < txq_number; queue++) 2864c5aff182SThomas Petazzoni mvneta_txq_done_force(pp, &pp->txqs[queue]); 2865c5aff182SThomas Petazzoni 2866c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_PORT_TX_RESET, MVNETA_PORT_TX_DMA_RESET); 2867c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_PORT_TX_RESET, 0); 2868c5aff182SThomas Petazzoni } 2869c5aff182SThomas Petazzoni 2870c5aff182SThomas Petazzoni static void mvneta_rx_reset(struct mvneta_port *pp) 2871c5aff182SThomas Petazzoni { 2872c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_PORT_RX_RESET, MVNETA_PORT_RX_DMA_RESET); 2873c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_PORT_RX_RESET, 0); 2874c5aff182SThomas Petazzoni } 2875c5aff182SThomas Petazzoni 2876c5aff182SThomas Petazzoni /* Rx/Tx queue initialization/cleanup methods */ 2877c5aff182SThomas Petazzoni 28784a188a63SJisheng Zhang static int mvneta_rxq_sw_init(struct mvneta_port *pp, 2879c5aff182SThomas Petazzoni struct mvneta_rx_queue *rxq) 2880c5aff182SThomas Petazzoni { 2881c5aff182SThomas Petazzoni rxq->size = pp->rx_ring_size; 2882c5aff182SThomas Petazzoni 2883c5aff182SThomas Petazzoni /* Allocate memory for RX descriptors */ 2884c5aff182SThomas Petazzoni rxq->descs = dma_alloc_coherent(pp->dev->dev.parent, 2885c5aff182SThomas Petazzoni rxq->size * MVNETA_DESC_ALIGNED_SIZE, 2886c5aff182SThomas Petazzoni &rxq->descs_phys, GFP_KERNEL); 2887f95936ccSMarkus Elfring if (!rxq->descs) 2888c5aff182SThomas Petazzoni return -ENOMEM; 2889c5aff182SThomas Petazzoni 2890c5aff182SThomas Petazzoni rxq->last_desc = rxq->size - 1; 2891c5aff182SThomas Petazzoni 28924a188a63SJisheng Zhang return 0; 28934a188a63SJisheng Zhang } 28944a188a63SJisheng Zhang 28954a188a63SJisheng Zhang static void mvneta_rxq_hw_init(struct mvneta_port *pp, 28964a188a63SJisheng Zhang struct mvneta_rx_queue *rxq) 28974a188a63SJisheng Zhang { 2898c5aff182SThomas Petazzoni /* Set Rx descriptors queue starting address */ 2899c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_RXQ_BASE_ADDR_REG(rxq->id), rxq->descs_phys); 2900c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_RXQ_SIZE_REG(rxq->id), rxq->size); 2901c5aff182SThomas Petazzoni 2902c5aff182SThomas Petazzoni /* Set coalescing pkts and time */ 2903c5aff182SThomas Petazzoni mvneta_rx_pkts_coal_set(pp, rxq, rxq->pkts_coal); 2904c5aff182SThomas Petazzoni mvneta_rx_time_coal_set(pp, rxq, rxq->time_coal); 2905c5aff182SThomas Petazzoni 2906dc35a10fSMarcin Wojtas if (!pp->bm_priv) { 2907562e2f46SYelena Krivosheev /* Set Offset */ 2908562e2f46SYelena Krivosheev mvneta_rxq_offset_set(pp, rxq, 0); 2909e735fd55SMarcin Wojtas mvneta_rxq_buf_size_set(pp, rxq, PAGE_SIZE < SZ_64K ? 2910e735fd55SMarcin Wojtas PAGE_SIZE : 2911e735fd55SMarcin Wojtas MVNETA_RX_BUF_SIZE(pp->pkt_size)); 2912c5aff182SThomas Petazzoni mvneta_rxq_bm_disable(pp, rxq); 2913e9f64999SGregory CLEMENT mvneta_rxq_fill(pp, rxq, rxq->size); 2914dc35a10fSMarcin Wojtas } else { 2915562e2f46SYelena Krivosheev /* Set Offset */ 2916562e2f46SYelena Krivosheev mvneta_rxq_offset_set(pp, rxq, 2917562e2f46SYelena Krivosheev NET_SKB_PAD - pp->rx_offset_correction); 2918562e2f46SYelena Krivosheev 2919dc35a10fSMarcin Wojtas mvneta_rxq_bm_enable(pp, rxq); 2920562e2f46SYelena Krivosheev /* Fill RXQ with buffers from RX pool */ 2921dc35a10fSMarcin Wojtas mvneta_rxq_long_pool_set(pp, rxq); 2922dc35a10fSMarcin Wojtas mvneta_rxq_short_pool_set(pp, rxq); 2923e9f64999SGregory CLEMENT mvneta_rxq_non_occup_desc_add(pp, rxq, rxq->size); 2924dc35a10fSMarcin Wojtas } 29254a188a63SJisheng Zhang } 29264a188a63SJisheng Zhang 29274a188a63SJisheng Zhang /* Create a specified RX queue */ 29284a188a63SJisheng Zhang static int mvneta_rxq_init(struct mvneta_port *pp, 29294a188a63SJisheng Zhang struct mvneta_rx_queue *rxq) 29304a188a63SJisheng Zhang 29314a188a63SJisheng Zhang { 29324a188a63SJisheng Zhang int ret; 29334a188a63SJisheng Zhang 29344a188a63SJisheng Zhang ret = mvneta_rxq_sw_init(pp, rxq); 29354a188a63SJisheng Zhang if (ret < 0) 29364a188a63SJisheng Zhang return ret; 29374a188a63SJisheng Zhang 29384a188a63SJisheng Zhang mvneta_rxq_hw_init(pp, rxq); 2939dc35a10fSMarcin Wojtas 2940c5aff182SThomas Petazzoni return 0; 2941c5aff182SThomas Petazzoni } 2942c5aff182SThomas Petazzoni 2943c5aff182SThomas Petazzoni /* Cleanup Rx queue */ 2944c5aff182SThomas Petazzoni static void mvneta_rxq_deinit(struct mvneta_port *pp, 2945c5aff182SThomas Petazzoni struct mvneta_rx_queue *rxq) 2946c5aff182SThomas Petazzoni { 2947c5aff182SThomas Petazzoni mvneta_rxq_drop_pkts(pp, rxq); 2948c5aff182SThomas Petazzoni 2949562e2f46SYelena Krivosheev if (rxq->skb) 2950562e2f46SYelena Krivosheev dev_kfree_skb_any(rxq->skb); 2951562e2f46SYelena Krivosheev 2952c5aff182SThomas Petazzoni if (rxq->descs) 2953c5aff182SThomas Petazzoni dma_free_coherent(pp->dev->dev.parent, 2954c5aff182SThomas Petazzoni rxq->size * MVNETA_DESC_ALIGNED_SIZE, 2955c5aff182SThomas Petazzoni rxq->descs, 2956c5aff182SThomas Petazzoni rxq->descs_phys); 2957c5aff182SThomas Petazzoni 2958c5aff182SThomas Petazzoni rxq->descs = NULL; 2959c5aff182SThomas Petazzoni rxq->last_desc = 0; 2960c5aff182SThomas Petazzoni rxq->next_desc_to_proc = 0; 2961c5aff182SThomas Petazzoni rxq->descs_phys = 0; 2962562e2f46SYelena Krivosheev rxq->first_to_refill = 0; 2963562e2f46SYelena Krivosheev rxq->refill_num = 0; 2964562e2f46SYelena Krivosheev rxq->skb = NULL; 2965562e2f46SYelena Krivosheev rxq->left_size = 0; 2966c5aff182SThomas Petazzoni } 2967c5aff182SThomas Petazzoni 29684a188a63SJisheng Zhang static int mvneta_txq_sw_init(struct mvneta_port *pp, 2969c5aff182SThomas Petazzoni struct mvneta_tx_queue *txq) 2970c5aff182SThomas Petazzoni { 297150bf8cb6SGregory CLEMENT int cpu; 297250bf8cb6SGregory CLEMENT 2973c5aff182SThomas Petazzoni txq->size = pp->tx_ring_size; 2974c5aff182SThomas Petazzoni 29758eef5f97SEzequiel Garcia /* A queue must always have room for at least one skb. 29768eef5f97SEzequiel Garcia * Therefore, stop the queue when the free entries reaches 29778eef5f97SEzequiel Garcia * the maximum number of descriptors per skb. 29788eef5f97SEzequiel Garcia */ 29798eef5f97SEzequiel Garcia txq->tx_stop_threshold = txq->size - MVNETA_MAX_SKB_DESCS; 29808eef5f97SEzequiel Garcia txq->tx_wake_threshold = txq->tx_stop_threshold / 2; 29818eef5f97SEzequiel Garcia 2982c5aff182SThomas Petazzoni /* Allocate memory for TX descriptors */ 2983c5aff182SThomas Petazzoni txq->descs = dma_alloc_coherent(pp->dev->dev.parent, 2984c5aff182SThomas Petazzoni txq->size * MVNETA_DESC_ALIGNED_SIZE, 2985c5aff182SThomas Petazzoni &txq->descs_phys, GFP_KERNEL); 2986f95936ccSMarkus Elfring if (!txq->descs) 2987c5aff182SThomas Petazzoni return -ENOMEM; 2988c5aff182SThomas Petazzoni 2989c5aff182SThomas Petazzoni txq->last_desc = txq->size - 1; 2990c5aff182SThomas Petazzoni 2991d441b688SMarkus Elfring txq->tx_skb = kmalloc_array(txq->size, sizeof(*txq->tx_skb), 2992d441b688SMarkus Elfring GFP_KERNEL); 2993f95936ccSMarkus Elfring if (!txq->tx_skb) { 2994c5aff182SThomas Petazzoni dma_free_coherent(pp->dev->dev.parent, 2995c5aff182SThomas Petazzoni txq->size * MVNETA_DESC_ALIGNED_SIZE, 2996c5aff182SThomas Petazzoni txq->descs, txq->descs_phys); 2997c5aff182SThomas Petazzoni return -ENOMEM; 2998c5aff182SThomas Petazzoni } 29992adb719dSEzequiel Garcia 30002adb719dSEzequiel Garcia /* Allocate DMA buffers for TSO MAC/IP/TCP headers */ 30012adb719dSEzequiel Garcia txq->tso_hdrs = dma_alloc_coherent(pp->dev->dev.parent, 30022adb719dSEzequiel Garcia txq->size * TSO_HEADER_SIZE, 30032adb719dSEzequiel Garcia &txq->tso_hdrs_phys, GFP_KERNEL); 3004f95936ccSMarkus Elfring if (!txq->tso_hdrs) { 30052adb719dSEzequiel Garcia kfree(txq->tx_skb); 30062adb719dSEzequiel Garcia dma_free_coherent(pp->dev->dev.parent, 30072adb719dSEzequiel Garcia txq->size * MVNETA_DESC_ALIGNED_SIZE, 30082adb719dSEzequiel Garcia txq->descs, txq->descs_phys); 30092adb719dSEzequiel Garcia return -ENOMEM; 30102adb719dSEzequiel Garcia } 3011c5aff182SThomas Petazzoni 301250bf8cb6SGregory CLEMENT /* Setup XPS mapping */ 301350bf8cb6SGregory CLEMENT if (txq_number > 1) 301450bf8cb6SGregory CLEMENT cpu = txq->id % num_present_cpus(); 301550bf8cb6SGregory CLEMENT else 301650bf8cb6SGregory CLEMENT cpu = pp->rxq_def % num_present_cpus(); 301750bf8cb6SGregory CLEMENT cpumask_set_cpu(cpu, &txq->affinity_mask); 301850bf8cb6SGregory CLEMENT netif_set_xps_queue(pp->dev, &txq->affinity_mask, txq->id); 301950bf8cb6SGregory CLEMENT 3020c5aff182SThomas Petazzoni return 0; 3021c5aff182SThomas Petazzoni } 3022c5aff182SThomas Petazzoni 30234a188a63SJisheng Zhang static void mvneta_txq_hw_init(struct mvneta_port *pp, 30244a188a63SJisheng Zhang struct mvneta_tx_queue *txq) 30254a188a63SJisheng Zhang { 30264a188a63SJisheng Zhang /* Set maximum bandwidth for enabled TXQs */ 30274a188a63SJisheng Zhang mvreg_write(pp, MVETH_TXQ_TOKEN_CFG_REG(txq->id), 0x03ffffff); 30284a188a63SJisheng Zhang mvreg_write(pp, MVETH_TXQ_TOKEN_COUNT_REG(txq->id), 0x3fffffff); 30294a188a63SJisheng Zhang 30304a188a63SJisheng Zhang /* Set Tx descriptors queue starting address */ 30314a188a63SJisheng Zhang mvreg_write(pp, MVNETA_TXQ_BASE_ADDR_REG(txq->id), txq->descs_phys); 30324a188a63SJisheng Zhang mvreg_write(pp, MVNETA_TXQ_SIZE_REG(txq->id), txq->size); 30334a188a63SJisheng Zhang 30344a188a63SJisheng Zhang mvneta_tx_done_pkts_coal_set(pp, txq, txq->done_pkts_coal); 30354a188a63SJisheng Zhang } 30364a188a63SJisheng Zhang 30374a188a63SJisheng Zhang /* Create and initialize a tx queue */ 30384a188a63SJisheng Zhang static int mvneta_txq_init(struct mvneta_port *pp, 30394a188a63SJisheng Zhang struct mvneta_tx_queue *txq) 30404a188a63SJisheng Zhang { 30414a188a63SJisheng Zhang int ret; 30424a188a63SJisheng Zhang 30434a188a63SJisheng Zhang ret = mvneta_txq_sw_init(pp, txq); 30444a188a63SJisheng Zhang if (ret < 0) 30454a188a63SJisheng Zhang return ret; 30464a188a63SJisheng Zhang 30474a188a63SJisheng Zhang mvneta_txq_hw_init(pp, txq); 30484a188a63SJisheng Zhang 30494a188a63SJisheng Zhang return 0; 30504a188a63SJisheng Zhang } 30514a188a63SJisheng Zhang 3052c5aff182SThomas Petazzoni /* Free allocated resources when mvneta_txq_init() fails to allocate memory*/ 30534a188a63SJisheng Zhang static void mvneta_txq_sw_deinit(struct mvneta_port *pp, 3054c5aff182SThomas Petazzoni struct mvneta_tx_queue *txq) 3055c5aff182SThomas Petazzoni { 3056a29b6235SMarcin Wojtas struct netdev_queue *nq = netdev_get_tx_queue(pp->dev, txq->id); 3057a29b6235SMarcin Wojtas 3058c5aff182SThomas Petazzoni kfree(txq->tx_skb); 3059c5aff182SThomas Petazzoni 30602adb719dSEzequiel Garcia if (txq->tso_hdrs) 30612adb719dSEzequiel Garcia dma_free_coherent(pp->dev->dev.parent, 30622adb719dSEzequiel Garcia txq->size * TSO_HEADER_SIZE, 30632adb719dSEzequiel Garcia txq->tso_hdrs, txq->tso_hdrs_phys); 3064c5aff182SThomas Petazzoni if (txq->descs) 3065c5aff182SThomas Petazzoni dma_free_coherent(pp->dev->dev.parent, 3066c5aff182SThomas Petazzoni txq->size * MVNETA_DESC_ALIGNED_SIZE, 3067c5aff182SThomas Petazzoni txq->descs, txq->descs_phys); 3068c5aff182SThomas Petazzoni 3069a29b6235SMarcin Wojtas netdev_tx_reset_queue(nq); 3070a29b6235SMarcin Wojtas 3071c5aff182SThomas Petazzoni txq->descs = NULL; 3072c5aff182SThomas Petazzoni txq->last_desc = 0; 3073c5aff182SThomas Petazzoni txq->next_desc_to_proc = 0; 3074c5aff182SThomas Petazzoni txq->descs_phys = 0; 30754a188a63SJisheng Zhang } 3076c5aff182SThomas Petazzoni 30774a188a63SJisheng Zhang static void mvneta_txq_hw_deinit(struct mvneta_port *pp, 30784a188a63SJisheng Zhang struct mvneta_tx_queue *txq) 30794a188a63SJisheng Zhang { 3080c5aff182SThomas Petazzoni /* Set minimum bandwidth for disabled TXQs */ 3081c5aff182SThomas Petazzoni mvreg_write(pp, MVETH_TXQ_TOKEN_CFG_REG(txq->id), 0); 3082c5aff182SThomas Petazzoni mvreg_write(pp, MVETH_TXQ_TOKEN_COUNT_REG(txq->id), 0); 3083c5aff182SThomas Petazzoni 3084c5aff182SThomas Petazzoni /* Set Tx descriptors queue starting address and size */ 3085c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_TXQ_BASE_ADDR_REG(txq->id), 0); 3086c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_TXQ_SIZE_REG(txq->id), 0); 3087c5aff182SThomas Petazzoni } 3088c5aff182SThomas Petazzoni 30894a188a63SJisheng Zhang static void mvneta_txq_deinit(struct mvneta_port *pp, 30904a188a63SJisheng Zhang struct mvneta_tx_queue *txq) 30914a188a63SJisheng Zhang { 30924a188a63SJisheng Zhang mvneta_txq_sw_deinit(pp, txq); 30934a188a63SJisheng Zhang mvneta_txq_hw_deinit(pp, txq); 30944a188a63SJisheng Zhang } 30954a188a63SJisheng Zhang 3096c5aff182SThomas Petazzoni /* Cleanup all Tx queues */ 3097c5aff182SThomas Petazzoni static void mvneta_cleanup_txqs(struct mvneta_port *pp) 3098c5aff182SThomas Petazzoni { 3099c5aff182SThomas Petazzoni int queue; 3100c5aff182SThomas Petazzoni 3101c5aff182SThomas Petazzoni for (queue = 0; queue < txq_number; queue++) 3102c5aff182SThomas Petazzoni mvneta_txq_deinit(pp, &pp->txqs[queue]); 3103c5aff182SThomas Petazzoni } 3104c5aff182SThomas Petazzoni 3105c5aff182SThomas Petazzoni /* Cleanup all Rx queues */ 3106c5aff182SThomas Petazzoni static void mvneta_cleanup_rxqs(struct mvneta_port *pp) 3107c5aff182SThomas Petazzoni { 31082dcf75e2SGregory CLEMENT int queue; 31092dcf75e2SGregory CLEMENT 3110ca5902a6SYelena Krivosheev for (queue = 0; queue < rxq_number; queue++) 31112dcf75e2SGregory CLEMENT mvneta_rxq_deinit(pp, &pp->rxqs[queue]); 3112c5aff182SThomas Petazzoni } 3113c5aff182SThomas Petazzoni 3114c5aff182SThomas Petazzoni 3115c5aff182SThomas Petazzoni /* Init all Rx queues */ 3116c5aff182SThomas Petazzoni static int mvneta_setup_rxqs(struct mvneta_port *pp) 3117c5aff182SThomas Petazzoni { 31182dcf75e2SGregory CLEMENT int queue; 31192dcf75e2SGregory CLEMENT 31202dcf75e2SGregory CLEMENT for (queue = 0; queue < rxq_number; queue++) { 31212dcf75e2SGregory CLEMENT int err = mvneta_rxq_init(pp, &pp->rxqs[queue]); 31222dcf75e2SGregory CLEMENT 3123c5aff182SThomas Petazzoni if (err) { 3124c5aff182SThomas Petazzoni netdev_err(pp->dev, "%s: can't create rxq=%d\n", 31252dcf75e2SGregory CLEMENT __func__, queue); 3126c5aff182SThomas Petazzoni mvneta_cleanup_rxqs(pp); 3127c5aff182SThomas Petazzoni return err; 3128c5aff182SThomas Petazzoni } 31292dcf75e2SGregory CLEMENT } 3130c5aff182SThomas Petazzoni 3131c5aff182SThomas Petazzoni return 0; 3132c5aff182SThomas Petazzoni } 3133c5aff182SThomas Petazzoni 3134c5aff182SThomas Petazzoni /* Init all tx queues */ 3135c5aff182SThomas Petazzoni static int mvneta_setup_txqs(struct mvneta_port *pp) 3136c5aff182SThomas Petazzoni { 3137c5aff182SThomas Petazzoni int queue; 3138c5aff182SThomas Petazzoni 3139c5aff182SThomas Petazzoni for (queue = 0; queue < txq_number; queue++) { 3140c5aff182SThomas Petazzoni int err = mvneta_txq_init(pp, &pp->txqs[queue]); 3141c5aff182SThomas Petazzoni if (err) { 3142c5aff182SThomas Petazzoni netdev_err(pp->dev, "%s: can't create txq=%d\n", 3143c5aff182SThomas Petazzoni __func__, queue); 3144c5aff182SThomas Petazzoni mvneta_cleanup_txqs(pp); 3145c5aff182SThomas Petazzoni return err; 3146c5aff182SThomas Petazzoni } 3147c5aff182SThomas Petazzoni } 3148c5aff182SThomas Petazzoni 3149c5aff182SThomas Petazzoni return 0; 3150c5aff182SThomas Petazzoni } 3151c5aff182SThomas Petazzoni 3152031b922bSMarek Behún static int mvneta_comphy_init(struct mvneta_port *pp) 3153031b922bSMarek Behún { 3154031b922bSMarek Behún int ret; 3155031b922bSMarek Behún 3156031b922bSMarek Behún if (!pp->comphy) 3157031b922bSMarek Behún return 0; 3158031b922bSMarek Behún 3159031b922bSMarek Behún ret = phy_set_mode_ext(pp->comphy, PHY_MODE_ETHERNET, 3160031b922bSMarek Behún pp->phy_interface); 3161031b922bSMarek Behún if (ret) 3162031b922bSMarek Behún return ret; 3163031b922bSMarek Behún 3164031b922bSMarek Behún return phy_power_on(pp->comphy); 3165031b922bSMarek Behún } 3166031b922bSMarek Behún 3167c5aff182SThomas Petazzoni static void mvneta_start_dev(struct mvneta_port *pp) 3168c5aff182SThomas Petazzoni { 31696b125d63SGregory CLEMENT int cpu; 317012bb03b4SMaxime Ripard 3171031b922bSMarek Behún WARN_ON(mvneta_comphy_init(pp)); 3172a10c1c81SRussell King 3173c5aff182SThomas Petazzoni mvneta_max_rx_size_set(pp, pp->pkt_size); 3174c5aff182SThomas Petazzoni mvneta_txq_max_tx_size_set(pp, pp->pkt_size); 3175c5aff182SThomas Petazzoni 3176c5aff182SThomas Petazzoni /* start the Rx/Tx activity */ 3177c5aff182SThomas Petazzoni mvneta_port_enable(pp); 3178c5aff182SThomas Petazzoni 31792636ac3cSMarcin Wojtas if (!pp->neta_armada3700) { 3180c5aff182SThomas Petazzoni /* Enable polling on the port */ 3181129219e4SGregory CLEMENT for_each_online_cpu(cpu) { 31822636ac3cSMarcin Wojtas struct mvneta_pcpu_port *port = 31832636ac3cSMarcin Wojtas per_cpu_ptr(pp->ports, cpu); 318412bb03b4SMaxime Ripard 318512bb03b4SMaxime Ripard napi_enable(&port->napi); 318612bb03b4SMaxime Ripard } 31872636ac3cSMarcin Wojtas } else { 31882636ac3cSMarcin Wojtas napi_enable(&pp->napi); 31892636ac3cSMarcin Wojtas } 3190c5aff182SThomas Petazzoni 31912dcf75e2SGregory CLEMENT /* Unmask interrupts. It has to be done from each CPU */ 31926b125d63SGregory CLEMENT on_each_cpu(mvneta_percpu_unmask_interrupt, pp, true); 31936b125d63SGregory CLEMENT 3194898b2970SStas Sergeev mvreg_write(pp, MVNETA_INTR_MISC_MASK, 3195898b2970SStas Sergeev MVNETA_CAUSE_PHY_STATUS_CHANGE | 3196856b2cc5SRussell King MVNETA_CAUSE_LINK_CHANGE); 3197c5aff182SThomas Petazzoni 3198503f9aa9SRussell King phylink_start(pp->phylink); 3199c5aff182SThomas Petazzoni netif_tx_start_all_queues(pp->dev); 3200c5aff182SThomas Petazzoni } 3201c5aff182SThomas Petazzoni 3202c5aff182SThomas Petazzoni static void mvneta_stop_dev(struct mvneta_port *pp) 3203c5aff182SThomas Petazzoni { 320412bb03b4SMaxime Ripard unsigned int cpu; 320512bb03b4SMaxime Ripard 3206503f9aa9SRussell King phylink_stop(pp->phylink); 3207c5aff182SThomas Petazzoni 32082636ac3cSMarcin Wojtas if (!pp->neta_armada3700) { 3209129219e4SGregory CLEMENT for_each_online_cpu(cpu) { 32102636ac3cSMarcin Wojtas struct mvneta_pcpu_port *port = 32112636ac3cSMarcin Wojtas per_cpu_ptr(pp->ports, cpu); 321212bb03b4SMaxime Ripard 321312bb03b4SMaxime Ripard napi_disable(&port->napi); 321412bb03b4SMaxime Ripard } 32152636ac3cSMarcin Wojtas } else { 32162636ac3cSMarcin Wojtas napi_disable(&pp->napi); 32172636ac3cSMarcin Wojtas } 3218c5aff182SThomas Petazzoni 3219c5aff182SThomas Petazzoni netif_carrier_off(pp->dev); 3220c5aff182SThomas Petazzoni 3221c5aff182SThomas Petazzoni mvneta_port_down(pp); 3222c5aff182SThomas Petazzoni netif_tx_stop_all_queues(pp->dev); 3223c5aff182SThomas Petazzoni 3224c5aff182SThomas Petazzoni /* Stop the port activity */ 3225c5aff182SThomas Petazzoni mvneta_port_disable(pp); 3226c5aff182SThomas Petazzoni 3227c5aff182SThomas Petazzoni /* Clear all ethernet port interrupts */ 3228db488c10SGregory CLEMENT on_each_cpu(mvneta_percpu_clear_intr_cause, pp, true); 3229c5aff182SThomas Petazzoni 3230c5aff182SThomas Petazzoni /* Mask all ethernet port interrupts */ 3231db488c10SGregory CLEMENT on_each_cpu(mvneta_percpu_mask_interrupt, pp, true); 3232c5aff182SThomas Petazzoni 3233c5aff182SThomas Petazzoni mvneta_tx_reset(pp); 3234c5aff182SThomas Petazzoni mvneta_rx_reset(pp); 3235a10c1c81SRussell King 3236a10c1c81SRussell King WARN_ON(phy_power_off(pp->comphy)); 3237c5aff182SThomas Petazzoni } 3238c5aff182SThomas Petazzoni 3239db5dd0dbSMarcin Wojtas static void mvneta_percpu_enable(void *arg) 3240db5dd0dbSMarcin Wojtas { 3241db5dd0dbSMarcin Wojtas struct mvneta_port *pp = arg; 3242db5dd0dbSMarcin Wojtas 3243db5dd0dbSMarcin Wojtas enable_percpu_irq(pp->dev->irq, IRQ_TYPE_NONE); 3244db5dd0dbSMarcin Wojtas } 3245db5dd0dbSMarcin Wojtas 3246db5dd0dbSMarcin Wojtas static void mvneta_percpu_disable(void *arg) 3247db5dd0dbSMarcin Wojtas { 3248db5dd0dbSMarcin Wojtas struct mvneta_port *pp = arg; 3249db5dd0dbSMarcin Wojtas 3250db5dd0dbSMarcin Wojtas disable_percpu_irq(pp->dev->irq); 3251db5dd0dbSMarcin Wojtas } 3252db5dd0dbSMarcin Wojtas 3253c5aff182SThomas Petazzoni /* Change the device mtu */ 3254c5aff182SThomas Petazzoni static int mvneta_change_mtu(struct net_device *dev, int mtu) 3255c5aff182SThomas Petazzoni { 3256c5aff182SThomas Petazzoni struct mvneta_port *pp = netdev_priv(dev); 3257c5aff182SThomas Petazzoni int ret; 3258c5aff182SThomas Petazzoni 32595777987eSJarod Wilson if (!IS_ALIGNED(MVNETA_RX_PKT_SIZE(mtu), 8)) { 32605777987eSJarod Wilson netdev_info(dev, "Illegal MTU value %d, rounding to %d\n", 32615777987eSJarod Wilson mtu, ALIGN(MVNETA_RX_PKT_SIZE(mtu), 8)); 32625777987eSJarod Wilson mtu = ALIGN(MVNETA_RX_PKT_SIZE(mtu), 8); 32635777987eSJarod Wilson } 3264c5aff182SThomas Petazzoni 3265c5aff182SThomas Petazzoni dev->mtu = mtu; 3266c5aff182SThomas Petazzoni 3267b65657fcSSimon Guinot if (!netif_running(dev)) { 3268dc35a10fSMarcin Wojtas if (pp->bm_priv) 3269dc35a10fSMarcin Wojtas mvneta_bm_update_mtu(pp, mtu); 3270dc35a10fSMarcin Wojtas 3271b65657fcSSimon Guinot netdev_update_features(dev); 3272c5aff182SThomas Petazzoni return 0; 3273b65657fcSSimon Guinot } 3274c5aff182SThomas Petazzoni 32756a20c175SThomas Petazzoni /* The interface is running, so we have to force a 3276a92dbd96SEzequiel Garcia * reallocation of the queues 3277c5aff182SThomas Petazzoni */ 3278c5aff182SThomas Petazzoni mvneta_stop_dev(pp); 3279db5dd0dbSMarcin Wojtas on_each_cpu(mvneta_percpu_disable, pp, true); 3280c5aff182SThomas Petazzoni 3281c5aff182SThomas Petazzoni mvneta_cleanup_txqs(pp); 3282c5aff182SThomas Petazzoni mvneta_cleanup_rxqs(pp); 3283c5aff182SThomas Petazzoni 3284dc35a10fSMarcin Wojtas if (pp->bm_priv) 3285dc35a10fSMarcin Wojtas mvneta_bm_update_mtu(pp, mtu); 3286dc35a10fSMarcin Wojtas 3287a92dbd96SEzequiel Garcia pp->pkt_size = MVNETA_RX_PKT_SIZE(dev->mtu); 3288c5aff182SThomas Petazzoni 3289c5aff182SThomas Petazzoni ret = mvneta_setup_rxqs(pp); 3290c5aff182SThomas Petazzoni if (ret) { 3291a92dbd96SEzequiel Garcia netdev_err(dev, "unable to setup rxqs after MTU change\n"); 3292c5aff182SThomas Petazzoni return ret; 3293c5aff182SThomas Petazzoni } 3294c5aff182SThomas Petazzoni 3295a92dbd96SEzequiel Garcia ret = mvneta_setup_txqs(pp); 3296a92dbd96SEzequiel Garcia if (ret) { 3297a92dbd96SEzequiel Garcia netdev_err(dev, "unable to setup txqs after MTU change\n"); 3298a92dbd96SEzequiel Garcia return ret; 3299a92dbd96SEzequiel Garcia } 3300c5aff182SThomas Petazzoni 3301db5dd0dbSMarcin Wojtas on_each_cpu(mvneta_percpu_enable, pp, true); 3302c5aff182SThomas Petazzoni mvneta_start_dev(pp); 3303c5aff182SThomas Petazzoni 3304b65657fcSSimon Guinot netdev_update_features(dev); 3305b65657fcSSimon Guinot 3306c5aff182SThomas Petazzoni return 0; 3307c5aff182SThomas Petazzoni } 3308c5aff182SThomas Petazzoni 3309b65657fcSSimon Guinot static netdev_features_t mvneta_fix_features(struct net_device *dev, 3310b65657fcSSimon Guinot netdev_features_t features) 3311b65657fcSSimon Guinot { 3312b65657fcSSimon Guinot struct mvneta_port *pp = netdev_priv(dev); 3313b65657fcSSimon Guinot 3314b65657fcSSimon Guinot if (pp->tx_csum_limit && dev->mtu > pp->tx_csum_limit) { 3315b65657fcSSimon Guinot features &= ~(NETIF_F_IP_CSUM | NETIF_F_TSO); 3316b65657fcSSimon Guinot netdev_info(dev, 3317b65657fcSSimon Guinot "Disable IP checksum for MTU greater than %dB\n", 3318b65657fcSSimon Guinot pp->tx_csum_limit); 3319b65657fcSSimon Guinot } 3320b65657fcSSimon Guinot 3321b65657fcSSimon Guinot return features; 3322b65657fcSSimon Guinot } 3323b65657fcSSimon Guinot 33248cc3e439SThomas Petazzoni /* Get mac address */ 33258cc3e439SThomas Petazzoni static void mvneta_get_mac_addr(struct mvneta_port *pp, unsigned char *addr) 33268cc3e439SThomas Petazzoni { 33278cc3e439SThomas Petazzoni u32 mac_addr_l, mac_addr_h; 33288cc3e439SThomas Petazzoni 33298cc3e439SThomas Petazzoni mac_addr_l = mvreg_read(pp, MVNETA_MAC_ADDR_LOW); 33308cc3e439SThomas Petazzoni mac_addr_h = mvreg_read(pp, MVNETA_MAC_ADDR_HIGH); 33318cc3e439SThomas Petazzoni addr[0] = (mac_addr_h >> 24) & 0xFF; 33328cc3e439SThomas Petazzoni addr[1] = (mac_addr_h >> 16) & 0xFF; 33338cc3e439SThomas Petazzoni addr[2] = (mac_addr_h >> 8) & 0xFF; 33348cc3e439SThomas Petazzoni addr[3] = mac_addr_h & 0xFF; 33358cc3e439SThomas Petazzoni addr[4] = (mac_addr_l >> 8) & 0xFF; 33368cc3e439SThomas Petazzoni addr[5] = mac_addr_l & 0xFF; 33378cc3e439SThomas Petazzoni } 33388cc3e439SThomas Petazzoni 3339c5aff182SThomas Petazzoni /* Handle setting mac address */ 3340c5aff182SThomas Petazzoni static int mvneta_set_mac_addr(struct net_device *dev, void *addr) 3341c5aff182SThomas Petazzoni { 3342c5aff182SThomas Petazzoni struct mvneta_port *pp = netdev_priv(dev); 3343e68de360SEzequiel Garcia struct sockaddr *sockaddr = addr; 3344e68de360SEzequiel Garcia int ret; 3345c5aff182SThomas Petazzoni 3346e68de360SEzequiel Garcia ret = eth_prepare_mac_addr_change(dev, addr); 3347e68de360SEzequiel Garcia if (ret < 0) 3348e68de360SEzequiel Garcia return ret; 3349c5aff182SThomas Petazzoni /* Remove previous address table entry */ 3350c5aff182SThomas Petazzoni mvneta_mac_addr_set(pp, dev->dev_addr, -1); 3351c5aff182SThomas Petazzoni 3352c5aff182SThomas Petazzoni /* Set new addr in hw */ 335390b74c01SGregory CLEMENT mvneta_mac_addr_set(pp, sockaddr->sa_data, pp->rxq_def); 3354c5aff182SThomas Petazzoni 3355e68de360SEzequiel Garcia eth_commit_mac_addr_change(dev, addr); 3356c5aff182SThomas Petazzoni return 0; 3357c5aff182SThomas Petazzoni } 3358c5aff182SThomas Petazzoni 3359503f9aa9SRussell King static void mvneta_validate(struct net_device *ndev, unsigned long *supported, 3360503f9aa9SRussell King struct phylink_link_state *state) 3361503f9aa9SRussell King { 3362a10c1c81SRussell King struct mvneta_port *pp = netdev_priv(ndev); 3363503f9aa9SRussell King __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, }; 3364503f9aa9SRussell King 336522f4bf8aSRussell King /* We only support QSGMII, SGMII, 802.3z and RGMII modes */ 3366503f9aa9SRussell King if (state->interface != PHY_INTERFACE_MODE_NA && 3367503f9aa9SRussell King state->interface != PHY_INTERFACE_MODE_QSGMII && 3368503f9aa9SRussell King state->interface != PHY_INTERFACE_MODE_SGMII && 336922f4bf8aSRussell King !phy_interface_mode_is_8023z(state->interface) && 3370503f9aa9SRussell King !phy_interface_mode_is_rgmii(state->interface)) { 3371503f9aa9SRussell King bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS); 3372503f9aa9SRussell King return; 3373503f9aa9SRussell King } 3374503f9aa9SRussell King 3375503f9aa9SRussell King /* Allow all the expected bits */ 3376503f9aa9SRussell King phylink_set(mask, Autoneg); 3377503f9aa9SRussell King phylink_set_port_modes(mask); 3378503f9aa9SRussell King 33794932a918SRussell King /* Asymmetric pause is unsupported */ 33804932a918SRussell King phylink_set(mask, Pause); 3381da58a931SMaxime Chevallier 338283e65df6SMaxime Chevallier /* Half-duplex at speeds higher than 100Mbit is unsupported */ 3383a10c1c81SRussell King if (pp->comphy || state->interface != PHY_INTERFACE_MODE_2500BASEX) { 3384503f9aa9SRussell King phylink_set(mask, 1000baseT_Full); 3385503f9aa9SRussell King phylink_set(mask, 1000baseX_Full); 3386a10c1c81SRussell King } 3387a10c1c81SRussell King if (pp->comphy || state->interface == PHY_INTERFACE_MODE_2500BASEX) { 3388eda3d1b0SMaxime Chevallier phylink_set(mask, 2500baseT_Full); 3389a10c1c81SRussell King phylink_set(mask, 2500baseX_Full); 3390a10c1c81SRussell King } 339122f4bf8aSRussell King 339222f4bf8aSRussell King if (!phy_interface_mode_is_8023z(state->interface)) { 339322f4bf8aSRussell King /* 10M and 100M are only supported in non-802.3z mode */ 3394503f9aa9SRussell King phylink_set(mask, 10baseT_Half); 3395503f9aa9SRussell King phylink_set(mask, 10baseT_Full); 3396503f9aa9SRussell King phylink_set(mask, 100baseT_Half); 3397503f9aa9SRussell King phylink_set(mask, 100baseT_Full); 339822f4bf8aSRussell King } 3399503f9aa9SRussell King 3400503f9aa9SRussell King bitmap_and(supported, supported, mask, 3401503f9aa9SRussell King __ETHTOOL_LINK_MODE_MASK_NBITS); 3402503f9aa9SRussell King bitmap_and(state->advertising, state->advertising, mask, 3403503f9aa9SRussell King __ETHTOOL_LINK_MODE_MASK_NBITS); 3404a10c1c81SRussell King 3405a10c1c81SRussell King /* We can only operate at 2500BaseX or 1000BaseX. If requested 3406a10c1c81SRussell King * to advertise both, only report advertising at 2500BaseX. 3407a10c1c81SRussell King */ 3408a10c1c81SRussell King phylink_helper_basex_speed(state); 3409503f9aa9SRussell King } 3410503f9aa9SRussell King 3411503f9aa9SRussell King static int mvneta_mac_link_state(struct net_device *ndev, 3412503f9aa9SRussell King struct phylink_link_state *state) 3413c5aff182SThomas Petazzoni { 3414c5aff182SThomas Petazzoni struct mvneta_port *pp = netdev_priv(ndev); 3415503f9aa9SRussell King u32 gmac_stat; 3416c5aff182SThomas Petazzoni 3417503f9aa9SRussell King gmac_stat = mvreg_read(pp, MVNETA_GMAC_STATUS); 3418503f9aa9SRussell King 3419503f9aa9SRussell King if (gmac_stat & MVNETA_GMAC_SPEED_1000) 3420a10c1c81SRussell King state->speed = 3421a10c1c81SRussell King state->interface == PHY_INTERFACE_MODE_2500BASEX ? 3422a10c1c81SRussell King SPEED_2500 : SPEED_1000; 3423503f9aa9SRussell King else if (gmac_stat & MVNETA_GMAC_SPEED_100) 3424503f9aa9SRussell King state->speed = SPEED_100; 3425503f9aa9SRussell King else 3426503f9aa9SRussell King state->speed = SPEED_10; 3427503f9aa9SRussell King 3428503f9aa9SRussell King state->an_complete = !!(gmac_stat & MVNETA_GMAC_AN_COMPLETE); 3429503f9aa9SRussell King state->link = !!(gmac_stat & MVNETA_GMAC_LINK_UP); 3430503f9aa9SRussell King state->duplex = !!(gmac_stat & MVNETA_GMAC_FULL_DUPLEX); 3431503f9aa9SRussell King 3432503f9aa9SRussell King state->pause = 0; 34334932a918SRussell King if (gmac_stat & MVNETA_GMAC_RX_FLOW_CTRL_ENABLE) 34344932a918SRussell King state->pause |= MLO_PAUSE_RX; 34354932a918SRussell King if (gmac_stat & MVNETA_GMAC_TX_FLOW_CTRL_ENABLE) 34364932a918SRussell King state->pause |= MLO_PAUSE_TX; 3437503f9aa9SRussell King 3438503f9aa9SRussell King return 1; 3439503f9aa9SRussell King } 3440503f9aa9SRussell King 344122f4bf8aSRussell King static void mvneta_mac_an_restart(struct net_device *ndev) 344222f4bf8aSRussell King { 344322f4bf8aSRussell King struct mvneta_port *pp = netdev_priv(ndev); 344422f4bf8aSRussell King u32 gmac_an = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG); 344522f4bf8aSRussell King 344622f4bf8aSRussell King mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, 344722f4bf8aSRussell King gmac_an | MVNETA_GMAC_INBAND_RESTART_AN); 344822f4bf8aSRussell King mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, 344922f4bf8aSRussell King gmac_an & ~MVNETA_GMAC_INBAND_RESTART_AN); 345022f4bf8aSRussell King } 345122f4bf8aSRussell King 3452503f9aa9SRussell King static void mvneta_mac_config(struct net_device *ndev, unsigned int mode, 3453503f9aa9SRussell King const struct phylink_link_state *state) 3454503f9aa9SRussell King { 3455503f9aa9SRussell King struct mvneta_port *pp = netdev_priv(ndev); 345622f4bf8aSRussell King u32 new_ctrl0, gmac_ctrl0 = mvreg_read(pp, MVNETA_GMAC_CTRL_0); 3457503f9aa9SRussell King u32 new_ctrl2, gmac_ctrl2 = mvreg_read(pp, MVNETA_GMAC_CTRL_2); 3458da58a931SMaxime Chevallier u32 new_ctrl4, gmac_ctrl4 = mvreg_read(pp, MVNETA_GMAC_CTRL_4); 3459503f9aa9SRussell King u32 new_clk, gmac_clk = mvreg_read(pp, MVNETA_GMAC_CLOCK_DIVIDER); 3460503f9aa9SRussell King u32 new_an, gmac_an = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG); 3461503f9aa9SRussell King 346222f4bf8aSRussell King new_ctrl0 = gmac_ctrl0 & ~MVNETA_GMAC0_PORT_1000BASE_X; 346332699954SRussell King new_ctrl2 = gmac_ctrl2 & ~(MVNETA_GMAC2_INBAND_AN_ENABLE | 346432699954SRussell King MVNETA_GMAC2_PORT_RESET); 3465da58a931SMaxime Chevallier new_ctrl4 = gmac_ctrl4 & ~(MVNETA_GMAC4_SHORT_PREAMBLE_ENABLE); 3466503f9aa9SRussell King new_clk = gmac_clk & ~MVNETA_GMAC_1MS_CLOCK_ENABLE; 3467503f9aa9SRussell King new_an = gmac_an & ~(MVNETA_GMAC_INBAND_AN_ENABLE | 3468503f9aa9SRussell King MVNETA_GMAC_INBAND_RESTART_AN | 3469503f9aa9SRussell King MVNETA_GMAC_CONFIG_MII_SPEED | 3470c5aff182SThomas Petazzoni MVNETA_GMAC_CONFIG_GMII_SPEED | 3471503f9aa9SRussell King MVNETA_GMAC_AN_SPEED_EN | 347222f4bf8aSRussell King MVNETA_GMAC_ADVERT_SYM_FLOW_CTRL | 347322f4bf8aSRussell King MVNETA_GMAC_CONFIG_FLOW_CTRL | 3474503f9aa9SRussell King MVNETA_GMAC_AN_FLOW_CTRL_EN | 3475503f9aa9SRussell King MVNETA_GMAC_CONFIG_FULL_DUPLEX | 3476503f9aa9SRussell King MVNETA_GMAC_AN_DUPLEX_EN); 3477c5aff182SThomas Petazzoni 347832699954SRussell King /* Even though it might look weird, when we're configured in 347932699954SRussell King * SGMII or QSGMII mode, the RGMII bit needs to be set. 348032699954SRussell King */ 348132699954SRussell King new_ctrl2 |= MVNETA_GMAC2_PORT_RGMII; 348232699954SRussell King 348332699954SRussell King if (state->interface == PHY_INTERFACE_MODE_QSGMII || 348422f4bf8aSRussell King state->interface == PHY_INTERFACE_MODE_SGMII || 348522f4bf8aSRussell King phy_interface_mode_is_8023z(state->interface)) 348632699954SRussell King new_ctrl2 |= MVNETA_GMAC2_PCS_ENABLE; 348732699954SRussell King 34884932a918SRussell King if (phylink_test(state->advertising, Pause)) 34894932a918SRussell King new_an |= MVNETA_GMAC_ADVERT_SYM_FLOW_CTRL; 34904932a918SRussell King if (state->pause & MLO_PAUSE_TXRX_MASK) 34914932a918SRussell King new_an |= MVNETA_GMAC_CONFIG_FLOW_CTRL; 34924932a918SRussell King 3493503f9aa9SRussell King if (!phylink_autoneg_inband(mode)) { 3494503f9aa9SRussell King /* Phy or fixed speed */ 3495503f9aa9SRussell King if (state->duplex) 3496503f9aa9SRussell King new_an |= MVNETA_GMAC_CONFIG_FULL_DUPLEX; 3497c5aff182SThomas Petazzoni 3498da58a931SMaxime Chevallier if (state->speed == SPEED_1000 || state->speed == SPEED_2500) 3499503f9aa9SRussell King new_an |= MVNETA_GMAC_CONFIG_GMII_SPEED; 3500503f9aa9SRussell King else if (state->speed == SPEED_100) 3501503f9aa9SRussell King new_an |= MVNETA_GMAC_CONFIG_MII_SPEED; 350222f4bf8aSRussell King } else if (state->interface == PHY_INTERFACE_MODE_SGMII) { 3503503f9aa9SRussell King /* SGMII mode receives the state from the PHY */ 3504503f9aa9SRussell King new_ctrl2 |= MVNETA_GMAC2_INBAND_AN_ENABLE; 3505503f9aa9SRussell King new_clk |= MVNETA_GMAC_1MS_CLOCK_ENABLE; 3506503f9aa9SRussell King new_an = (new_an & ~(MVNETA_GMAC_FORCE_LINK_DOWN | 3507503f9aa9SRussell King MVNETA_GMAC_FORCE_LINK_PASS)) | 3508503f9aa9SRussell King MVNETA_GMAC_INBAND_AN_ENABLE | 3509503f9aa9SRussell King MVNETA_GMAC_AN_SPEED_EN | 3510503f9aa9SRussell King MVNETA_GMAC_AN_DUPLEX_EN; 351122f4bf8aSRussell King } else { 351222f4bf8aSRussell King /* 802.3z negotiation - only 1000base-X */ 351322f4bf8aSRussell King new_ctrl0 |= MVNETA_GMAC0_PORT_1000BASE_X; 351422f4bf8aSRussell King new_clk |= MVNETA_GMAC_1MS_CLOCK_ENABLE; 351522f4bf8aSRussell King new_an = (new_an & ~(MVNETA_GMAC_FORCE_LINK_DOWN | 351622f4bf8aSRussell King MVNETA_GMAC_FORCE_LINK_PASS)) | 351722f4bf8aSRussell King MVNETA_GMAC_INBAND_AN_ENABLE | 351822f4bf8aSRussell King MVNETA_GMAC_CONFIG_GMII_SPEED | 351922f4bf8aSRussell King /* The MAC only supports FD mode */ 352022f4bf8aSRussell King MVNETA_GMAC_CONFIG_FULL_DUPLEX; 35214932a918SRussell King 35224932a918SRussell King if (state->pause & MLO_PAUSE_AN && state->an_enabled) 35234932a918SRussell King new_an |= MVNETA_GMAC_AN_FLOW_CTRL_EN; 3524c5aff182SThomas Petazzoni } 3525c5aff182SThomas Petazzoni 3526503f9aa9SRussell King /* Armada 370 documentation says we can only change the port mode 3527503f9aa9SRussell King * and in-band enable when the link is down, so force it down 3528503f9aa9SRussell King * while making these changes. We also do this for GMAC_CTRL2 */ 352922f4bf8aSRussell King if ((new_ctrl0 ^ gmac_ctrl0) & MVNETA_GMAC0_PORT_1000BASE_X || 353022f4bf8aSRussell King (new_ctrl2 ^ gmac_ctrl2) & MVNETA_GMAC2_INBAND_AN_ENABLE || 3531503f9aa9SRussell King (new_an ^ gmac_an) & MVNETA_GMAC_INBAND_AN_ENABLE) { 3532503f9aa9SRussell King mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, 3533503f9aa9SRussell King (gmac_an & ~MVNETA_GMAC_FORCE_LINK_PASS) | 3534503f9aa9SRussell King MVNETA_GMAC_FORCE_LINK_DOWN); 3535503f9aa9SRussell King } 3536503f9aa9SRussell King 3537a10c1c81SRussell King 3538da58a931SMaxime Chevallier /* When at 2.5G, the link partner can send frames with shortened 3539da58a931SMaxime Chevallier * preambles. 3540da58a931SMaxime Chevallier */ 3541da58a931SMaxime Chevallier if (state->speed == SPEED_2500) 3542da58a931SMaxime Chevallier new_ctrl4 |= MVNETA_GMAC4_SHORT_PREAMBLE_ENABLE; 3543da58a931SMaxime Chevallier 3544031b922bSMarek Behún if (pp->comphy && pp->phy_interface != state->interface && 3545a10c1c81SRussell King (state->interface == PHY_INTERFACE_MODE_SGMII || 3546a10c1c81SRussell King state->interface == PHY_INTERFACE_MODE_1000BASEX || 3547031b922bSMarek Behún state->interface == PHY_INTERFACE_MODE_2500BASEX)) { 3548031b922bSMarek Behún pp->phy_interface = state->interface; 3549031b922bSMarek Behún 3550031b922bSMarek Behún WARN_ON(phy_power_off(pp->comphy)); 3551031b922bSMarek Behún WARN_ON(mvneta_comphy_init(pp)); 3552031b922bSMarek Behún } 3553a10c1c81SRussell King 355422f4bf8aSRussell King if (new_ctrl0 != gmac_ctrl0) 355522f4bf8aSRussell King mvreg_write(pp, MVNETA_GMAC_CTRL_0, new_ctrl0); 3556503f9aa9SRussell King if (new_ctrl2 != gmac_ctrl2) 3557503f9aa9SRussell King mvreg_write(pp, MVNETA_GMAC_CTRL_2, new_ctrl2); 3558da58a931SMaxime Chevallier if (new_ctrl4 != gmac_ctrl4) 3559da58a931SMaxime Chevallier mvreg_write(pp, MVNETA_GMAC_CTRL_4, new_ctrl4); 3560503f9aa9SRussell King if (new_clk != gmac_clk) 3561503f9aa9SRussell King mvreg_write(pp, MVNETA_GMAC_CLOCK_DIVIDER, new_clk); 3562503f9aa9SRussell King if (new_an != gmac_an) 3563503f9aa9SRussell King mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, new_an); 356432699954SRussell King 356532699954SRussell King if (gmac_ctrl2 & MVNETA_GMAC2_PORT_RESET) { 356632699954SRussell King while ((mvreg_read(pp, MVNETA_GMAC_CTRL_2) & 356732699954SRussell King MVNETA_GMAC2_PORT_RESET) != 0) 356832699954SRussell King continue; 356932699954SRussell King } 3570503f9aa9SRussell King } 3571503f9aa9SRussell King 35726d81f451SRussell King static void mvneta_set_eee(struct mvneta_port *pp, bool enable) 35736d81f451SRussell King { 35746d81f451SRussell King u32 lpi_ctl1; 35756d81f451SRussell King 35766d81f451SRussell King lpi_ctl1 = mvreg_read(pp, MVNETA_LPI_CTRL_1); 35776d81f451SRussell King if (enable) 35786d81f451SRussell King lpi_ctl1 |= MVNETA_LPI_REQUEST_ENABLE; 35796d81f451SRussell King else 35806d81f451SRussell King lpi_ctl1 &= ~MVNETA_LPI_REQUEST_ENABLE; 35816d81f451SRussell King mvreg_write(pp, MVNETA_LPI_CTRL_1, lpi_ctl1); 35826d81f451SRussell King } 35836d81f451SRussell King 3584c6ab3008SFlorian Fainelli static void mvneta_mac_link_down(struct net_device *ndev, unsigned int mode, 3585c6ab3008SFlorian Fainelli phy_interface_t interface) 3586fc548b99SRussell King { 3587fc548b99SRussell King struct mvneta_port *pp = netdev_priv(ndev); 3588fc548b99SRussell King u32 val; 3589fc548b99SRussell King 3590503f9aa9SRussell King mvneta_port_down(pp); 3591503f9aa9SRussell King 3592503f9aa9SRussell King if (!phylink_autoneg_inband(mode)) { 3593fc548b99SRussell King val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG); 3594fc548b99SRussell King val &= ~MVNETA_GMAC_FORCE_LINK_PASS; 3595fc548b99SRussell King val |= MVNETA_GMAC_FORCE_LINK_DOWN; 3596fc548b99SRussell King mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val); 3597fc548b99SRussell King } 35986d81f451SRussell King 35996d81f451SRussell King pp->eee_active = false; 36006d81f451SRussell King mvneta_set_eee(pp, false); 3601fc548b99SRussell King } 3602fc548b99SRussell King 3603503f9aa9SRussell King static void mvneta_mac_link_up(struct net_device *ndev, unsigned int mode, 3604c6ab3008SFlorian Fainelli phy_interface_t interface, 3605503f9aa9SRussell King struct phy_device *phy) 3606fc548b99SRussell King { 3607fc548b99SRussell King struct mvneta_port *pp = netdev_priv(ndev); 3608fc548b99SRussell King u32 val; 3609fc548b99SRussell King 3610503f9aa9SRussell King if (!phylink_autoneg_inband(mode)) { 3611fc548b99SRussell King val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG); 3612fc548b99SRussell King val &= ~MVNETA_GMAC_FORCE_LINK_DOWN; 3613fc548b99SRussell King val |= MVNETA_GMAC_FORCE_LINK_PASS; 3614fc548b99SRussell King mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val); 3615fc548b99SRussell King } 3616fc548b99SRussell King 3617fc548b99SRussell King mvneta_port_up(pp); 36186d81f451SRussell King 36196d81f451SRussell King if (phy && pp->eee_enabled) { 36206d81f451SRussell King pp->eee_active = phy_init_eee(phy, 0) >= 0; 36216d81f451SRussell King mvneta_set_eee(pp, pp->eee_active && pp->tx_lpi_enabled); 36226d81f451SRussell King } 3623fc548b99SRussell King } 3624fc548b99SRussell King 3625503f9aa9SRussell King static const struct phylink_mac_ops mvneta_phylink_ops = { 3626503f9aa9SRussell King .validate = mvneta_validate, 3627503f9aa9SRussell King .mac_link_state = mvneta_mac_link_state, 362822f4bf8aSRussell King .mac_an_restart = mvneta_mac_an_restart, 3629503f9aa9SRussell King .mac_config = mvneta_mac_config, 3630503f9aa9SRussell King .mac_link_down = mvneta_mac_link_down, 3631503f9aa9SRussell King .mac_link_up = mvneta_mac_link_up, 3632503f9aa9SRussell King }; 3633c5aff182SThomas Petazzoni 3634c5aff182SThomas Petazzoni static int mvneta_mdio_probe(struct mvneta_port *pp) 3635c5aff182SThomas Petazzoni { 363682960fffSJisheng Zhang struct ethtool_wolinfo wol = { .cmd = ETHTOOL_GWOL }; 3637503f9aa9SRussell King int err = phylink_of_phy_connect(pp->phylink, pp->dn, 0); 3638c5aff182SThomas Petazzoni 3639503f9aa9SRussell King if (err) 3640503f9aa9SRussell King netdev_err(pp->dev, "could not attach PHY: %d\n", err); 3641c5aff182SThomas Petazzoni 3642503f9aa9SRussell King phylink_ethtool_get_wol(pp->phylink, &wol); 364382960fffSJisheng Zhang device_set_wakeup_capable(&pp->dev->dev, !!wol.supported); 364482960fffSJisheng Zhang 3645503f9aa9SRussell King return err; 3646c5aff182SThomas Petazzoni } 3647c5aff182SThomas Petazzoni 3648c5aff182SThomas Petazzoni static void mvneta_mdio_remove(struct mvneta_port *pp) 3649c5aff182SThomas Petazzoni { 3650503f9aa9SRussell King phylink_disconnect_phy(pp->phylink); 3651c5aff182SThomas Petazzoni } 3652c5aff182SThomas Petazzoni 3653120cfa50SGregory CLEMENT /* Electing a CPU must be done in an atomic way: it should be done 3654120cfa50SGregory CLEMENT * after or before the removal/insertion of a CPU and this function is 3655120cfa50SGregory CLEMENT * not reentrant. 3656120cfa50SGregory CLEMENT */ 3657f8642885SMaxime Ripard static void mvneta_percpu_elect(struct mvneta_port *pp) 3658f8642885SMaxime Ripard { 3659cad5d847SGregory CLEMENT int elected_cpu = 0, max_cpu, cpu, i = 0; 3660f8642885SMaxime Ripard 3661cad5d847SGregory CLEMENT /* Use the cpu associated to the rxq when it is online, in all 3662cad5d847SGregory CLEMENT * the other cases, use the cpu 0 which can't be offline. 3663cad5d847SGregory CLEMENT */ 3664cad5d847SGregory CLEMENT if (cpu_online(pp->rxq_def)) 3665cad5d847SGregory CLEMENT elected_cpu = pp->rxq_def; 3666cad5d847SGregory CLEMENT 36672dcf75e2SGregory CLEMENT max_cpu = num_present_cpus(); 3668f8642885SMaxime Ripard 3669f8642885SMaxime Ripard for_each_online_cpu(cpu) { 36702dcf75e2SGregory CLEMENT int rxq_map = 0, txq_map = 0; 36712dcf75e2SGregory CLEMENT int rxq; 36722dcf75e2SGregory CLEMENT 36732dcf75e2SGregory CLEMENT for (rxq = 0; rxq < rxq_number; rxq++) 36742dcf75e2SGregory CLEMENT if ((rxq % max_cpu) == cpu) 36752dcf75e2SGregory CLEMENT rxq_map |= MVNETA_CPU_RXQ_ACCESS(rxq); 36762dcf75e2SGregory CLEMENT 3677cad5d847SGregory CLEMENT if (cpu == elected_cpu) 367850bf8cb6SGregory CLEMENT /* Map the default receive queue queue to the 367950bf8cb6SGregory CLEMENT * elected CPU 3680f8642885SMaxime Ripard */ 36812dcf75e2SGregory CLEMENT rxq_map |= MVNETA_CPU_RXQ_ACCESS(pp->rxq_def); 368250bf8cb6SGregory CLEMENT 368350bf8cb6SGregory CLEMENT /* We update the TX queue map only if we have one 368450bf8cb6SGregory CLEMENT * queue. In this case we associate the TX queue to 368550bf8cb6SGregory CLEMENT * the CPU bound to the default RX queue 368650bf8cb6SGregory CLEMENT */ 368750bf8cb6SGregory CLEMENT if (txq_number == 1) 3688cad5d847SGregory CLEMENT txq_map = (cpu == elected_cpu) ? 368950bf8cb6SGregory CLEMENT MVNETA_CPU_TXQ_ACCESS(1) : 0; 369050bf8cb6SGregory CLEMENT else 369150bf8cb6SGregory CLEMENT txq_map = mvreg_read(pp, MVNETA_CPU_MAP(cpu)) & 369250bf8cb6SGregory CLEMENT MVNETA_CPU_TXQ_ACCESS_ALL_MASK; 369350bf8cb6SGregory CLEMENT 36942dcf75e2SGregory CLEMENT mvreg_write(pp, MVNETA_CPU_MAP(cpu), rxq_map | txq_map); 36952dcf75e2SGregory CLEMENT 36962dcf75e2SGregory CLEMENT /* Update the interrupt mask on each CPU according the 36972dcf75e2SGregory CLEMENT * new mapping 36982dcf75e2SGregory CLEMENT */ 36992dcf75e2SGregory CLEMENT smp_call_function_single(cpu, mvneta_percpu_unmask_interrupt, 3700f8642885SMaxime Ripard pp, true); 3701f8642885SMaxime Ripard i++; 37022dcf75e2SGregory CLEMENT 3703f8642885SMaxime Ripard } 3704f8642885SMaxime Ripard }; 3705f8642885SMaxime Ripard 370684a3f4dbSSebastian Andrzej Siewior static int mvneta_cpu_online(unsigned int cpu, struct hlist_node *node) 3707f8642885SMaxime Ripard { 370884a3f4dbSSebastian Andrzej Siewior int other_cpu; 370984a3f4dbSSebastian Andrzej Siewior struct mvneta_port *pp = hlist_entry_safe(node, struct mvneta_port, 371084a3f4dbSSebastian Andrzej Siewior node_online); 3711f8642885SMaxime Ripard struct mvneta_pcpu_port *port = per_cpu_ptr(pp->ports, cpu); 3712f8642885SMaxime Ripard 371384a3f4dbSSebastian Andrzej Siewior 3714120cfa50SGregory CLEMENT spin_lock(&pp->lock); 371584a3f4dbSSebastian Andrzej Siewior /* 371684a3f4dbSSebastian Andrzej Siewior * Configuring the driver for a new CPU while the driver is 371784a3f4dbSSebastian Andrzej Siewior * stopping is racy, so just avoid it. 3718120cfa50SGregory CLEMENT */ 3719120cfa50SGregory CLEMENT if (pp->is_stopped) { 3720120cfa50SGregory CLEMENT spin_unlock(&pp->lock); 372184a3f4dbSSebastian Andrzej Siewior return 0; 3722120cfa50SGregory CLEMENT } 3723f8642885SMaxime Ripard netif_tx_stop_all_queues(pp->dev); 3724f8642885SMaxime Ripard 372584a3f4dbSSebastian Andrzej Siewior /* 372684a3f4dbSSebastian Andrzej Siewior * We have to synchronise on tha napi of each CPU except the one 372784a3f4dbSSebastian Andrzej Siewior * just being woken up 3728f8642885SMaxime Ripard */ 3729f8642885SMaxime Ripard for_each_online_cpu(other_cpu) { 3730f8642885SMaxime Ripard if (other_cpu != cpu) { 3731f8642885SMaxime Ripard struct mvneta_pcpu_port *other_port = 3732f8642885SMaxime Ripard per_cpu_ptr(pp->ports, other_cpu); 3733f8642885SMaxime Ripard 3734f8642885SMaxime Ripard napi_synchronize(&other_port->napi); 3735f8642885SMaxime Ripard } 3736f8642885SMaxime Ripard } 3737f8642885SMaxime Ripard 3738f8642885SMaxime Ripard /* Mask all ethernet port interrupts */ 3739db488c10SGregory CLEMENT on_each_cpu(mvneta_percpu_mask_interrupt, pp, true); 3740f8642885SMaxime Ripard napi_enable(&port->napi); 3741f8642885SMaxime Ripard 374284a3f4dbSSebastian Andrzej Siewior /* 374384a3f4dbSSebastian Andrzej Siewior * Enable per-CPU interrupts on the CPU that is 37442dcf75e2SGregory CLEMENT * brought up. 37452dcf75e2SGregory CLEMENT */ 37460e28bf93SAnna-Maria Gleixner mvneta_percpu_enable(pp); 37472dcf75e2SGregory CLEMENT 374884a3f4dbSSebastian Andrzej Siewior /* 374984a3f4dbSSebastian Andrzej Siewior * Enable per-CPU interrupt on the one CPU we care 3750f8642885SMaxime Ripard * about. 3751f8642885SMaxime Ripard */ 3752f8642885SMaxime Ripard mvneta_percpu_elect(pp); 3753f8642885SMaxime Ripard 3754db488c10SGregory CLEMENT /* Unmask all ethernet port interrupts */ 3755db488c10SGregory CLEMENT on_each_cpu(mvneta_percpu_unmask_interrupt, pp, true); 3756f8642885SMaxime Ripard mvreg_write(pp, MVNETA_INTR_MISC_MASK, 3757f8642885SMaxime Ripard MVNETA_CAUSE_PHY_STATUS_CHANGE | 3758856b2cc5SRussell King MVNETA_CAUSE_LINK_CHANGE); 3759f8642885SMaxime Ripard netif_tx_start_all_queues(pp->dev); 3760120cfa50SGregory CLEMENT spin_unlock(&pp->lock); 376184a3f4dbSSebastian Andrzej Siewior return 0; 376284a3f4dbSSebastian Andrzej Siewior } 376384a3f4dbSSebastian Andrzej Siewior 376484a3f4dbSSebastian Andrzej Siewior static int mvneta_cpu_down_prepare(unsigned int cpu, struct hlist_node *node) 376584a3f4dbSSebastian Andrzej Siewior { 376684a3f4dbSSebastian Andrzej Siewior struct mvneta_port *pp = hlist_entry_safe(node, struct mvneta_port, 376784a3f4dbSSebastian Andrzej Siewior node_online); 376884a3f4dbSSebastian Andrzej Siewior struct mvneta_pcpu_port *port = per_cpu_ptr(pp->ports, cpu); 376984a3f4dbSSebastian Andrzej Siewior 377084a3f4dbSSebastian Andrzej Siewior /* 377184a3f4dbSSebastian Andrzej Siewior * Thanks to this lock we are sure that any pending cpu election is 377284a3f4dbSSebastian Andrzej Siewior * done. 37735888511eSGregory CLEMENT */ 37745888511eSGregory CLEMENT spin_lock(&pp->lock); 3775f8642885SMaxime Ripard /* Mask all ethernet port interrupts */ 3776db488c10SGregory CLEMENT on_each_cpu(mvneta_percpu_mask_interrupt, pp, true); 37775888511eSGregory CLEMENT spin_unlock(&pp->lock); 3778f8642885SMaxime Ripard 3779f8642885SMaxime Ripard napi_synchronize(&port->napi); 3780f8642885SMaxime Ripard napi_disable(&port->napi); 378184a3f4dbSSebastian Andrzej Siewior /* Disable per-CPU interrupts on the CPU that is brought down. */ 37820e28bf93SAnna-Maria Gleixner mvneta_percpu_disable(pp); 378384a3f4dbSSebastian Andrzej Siewior return 0; 378484a3f4dbSSebastian Andrzej Siewior } 3785f8642885SMaxime Ripard 378684a3f4dbSSebastian Andrzej Siewior static int mvneta_cpu_dead(unsigned int cpu, struct hlist_node *node) 378784a3f4dbSSebastian Andrzej Siewior { 378884a3f4dbSSebastian Andrzej Siewior struct mvneta_port *pp = hlist_entry_safe(node, struct mvneta_port, 378984a3f4dbSSebastian Andrzej Siewior node_dead); 379084a3f4dbSSebastian Andrzej Siewior 3791f8642885SMaxime Ripard /* Check if a new CPU must be elected now this on is down */ 3792120cfa50SGregory CLEMENT spin_lock(&pp->lock); 3793f8642885SMaxime Ripard mvneta_percpu_elect(pp); 3794120cfa50SGregory CLEMENT spin_unlock(&pp->lock); 3795f8642885SMaxime Ripard /* Unmask all ethernet port interrupts */ 3796db488c10SGregory CLEMENT on_each_cpu(mvneta_percpu_unmask_interrupt, pp, true); 3797f8642885SMaxime Ripard mvreg_write(pp, MVNETA_INTR_MISC_MASK, 3798f8642885SMaxime Ripard MVNETA_CAUSE_PHY_STATUS_CHANGE | 3799856b2cc5SRussell King MVNETA_CAUSE_LINK_CHANGE); 3800f8642885SMaxime Ripard netif_tx_start_all_queues(pp->dev); 380184a3f4dbSSebastian Andrzej Siewior return 0; 3802f8642885SMaxime Ripard } 3803f8642885SMaxime Ripard 3804c5aff182SThomas Petazzoni static int mvneta_open(struct net_device *dev) 3805c5aff182SThomas Petazzoni { 3806c5aff182SThomas Petazzoni struct mvneta_port *pp = netdev_priv(dev); 38076b125d63SGregory CLEMENT int ret; 3808c5aff182SThomas Petazzoni 3809c5aff182SThomas Petazzoni pp->pkt_size = MVNETA_RX_PKT_SIZE(pp->dev->mtu); 3810c5aff182SThomas Petazzoni 3811c5aff182SThomas Petazzoni ret = mvneta_setup_rxqs(pp); 3812c5aff182SThomas Petazzoni if (ret) 3813c5aff182SThomas Petazzoni return ret; 3814c5aff182SThomas Petazzoni 3815c5aff182SThomas Petazzoni ret = mvneta_setup_txqs(pp); 3816c5aff182SThomas Petazzoni if (ret) 3817c5aff182SThomas Petazzoni goto err_cleanup_rxqs; 3818c5aff182SThomas Petazzoni 3819c5aff182SThomas Petazzoni /* Connect to port interrupt line */ 38202636ac3cSMarcin Wojtas if (pp->neta_armada3700) 38212636ac3cSMarcin Wojtas ret = request_irq(pp->dev->irq, mvneta_isr, 0, 38222636ac3cSMarcin Wojtas dev->name, pp); 38232636ac3cSMarcin Wojtas else 38242636ac3cSMarcin Wojtas ret = request_percpu_irq(pp->dev->irq, mvneta_percpu_isr, 38252636ac3cSMarcin Wojtas dev->name, pp->ports); 3826c5aff182SThomas Petazzoni if (ret) { 3827c5aff182SThomas Petazzoni netdev_err(pp->dev, "cannot request irq %d\n", pp->dev->irq); 3828c5aff182SThomas Petazzoni goto err_cleanup_txqs; 3829c5aff182SThomas Petazzoni } 3830c5aff182SThomas Petazzoni 38312636ac3cSMarcin Wojtas if (!pp->neta_armada3700) { 38322dcf75e2SGregory CLEMENT /* Enable per-CPU interrupt on all the CPU to handle our RX 38332dcf75e2SGregory CLEMENT * queue interrupts 38342dcf75e2SGregory CLEMENT */ 38356b125d63SGregory CLEMENT on_each_cpu(mvneta_percpu_enable, pp, true); 38362dcf75e2SGregory CLEMENT 3837120cfa50SGregory CLEMENT pp->is_stopped = false; 3838f8642885SMaxime Ripard /* Register a CPU notifier to handle the case where our CPU 3839f8642885SMaxime Ripard * might be taken offline. 3840f8642885SMaxime Ripard */ 384184a3f4dbSSebastian Andrzej Siewior ret = cpuhp_state_add_instance_nocalls(online_hpstate, 384284a3f4dbSSebastian Andrzej Siewior &pp->node_online); 384384a3f4dbSSebastian Andrzej Siewior if (ret) 384484a3f4dbSSebastian Andrzej Siewior goto err_free_irq; 384584a3f4dbSSebastian Andrzej Siewior 384684a3f4dbSSebastian Andrzej Siewior ret = cpuhp_state_add_instance_nocalls(CPUHP_NET_MVNETA_DEAD, 384784a3f4dbSSebastian Andrzej Siewior &pp->node_dead); 384884a3f4dbSSebastian Andrzej Siewior if (ret) 384984a3f4dbSSebastian Andrzej Siewior goto err_free_online_hp; 38502636ac3cSMarcin Wojtas } 3851f8642885SMaxime Ripard 3852c5aff182SThomas Petazzoni ret = mvneta_mdio_probe(pp); 3853c5aff182SThomas Petazzoni if (ret < 0) { 3854c5aff182SThomas Petazzoni netdev_err(dev, "cannot probe MDIO bus\n"); 385584a3f4dbSSebastian Andrzej Siewior goto err_free_dead_hp; 3856c5aff182SThomas Petazzoni } 3857c5aff182SThomas Petazzoni 3858c5aff182SThomas Petazzoni mvneta_start_dev(pp); 3859c5aff182SThomas Petazzoni 3860c5aff182SThomas Petazzoni return 0; 3861c5aff182SThomas Petazzoni 386284a3f4dbSSebastian Andrzej Siewior err_free_dead_hp: 38632636ac3cSMarcin Wojtas if (!pp->neta_armada3700) 386484a3f4dbSSebastian Andrzej Siewior cpuhp_state_remove_instance_nocalls(CPUHP_NET_MVNETA_DEAD, 386584a3f4dbSSebastian Andrzej Siewior &pp->node_dead); 386684a3f4dbSSebastian Andrzej Siewior err_free_online_hp: 38672636ac3cSMarcin Wojtas if (!pp->neta_armada3700) 38682636ac3cSMarcin Wojtas cpuhp_state_remove_instance_nocalls(online_hpstate, 38692636ac3cSMarcin Wojtas &pp->node_online); 3870c5aff182SThomas Petazzoni err_free_irq: 38712636ac3cSMarcin Wojtas if (pp->neta_armada3700) { 38722636ac3cSMarcin Wojtas free_irq(pp->dev->irq, pp); 38732636ac3cSMarcin Wojtas } else { 38743d8c4530SRussell King - ARM Linux on_each_cpu(mvneta_percpu_disable, pp, true); 387512bb03b4SMaxime Ripard free_percpu_irq(pp->dev->irq, pp->ports); 38762636ac3cSMarcin Wojtas } 3877c5aff182SThomas Petazzoni err_cleanup_txqs: 3878c5aff182SThomas Petazzoni mvneta_cleanup_txqs(pp); 3879c5aff182SThomas Petazzoni err_cleanup_rxqs: 3880c5aff182SThomas Petazzoni mvneta_cleanup_rxqs(pp); 3881c5aff182SThomas Petazzoni return ret; 3882c5aff182SThomas Petazzoni } 3883c5aff182SThomas Petazzoni 3884c5aff182SThomas Petazzoni /* Stop the port, free port interrupt line */ 3885c5aff182SThomas Petazzoni static int mvneta_stop(struct net_device *dev) 3886c5aff182SThomas Petazzoni { 3887c5aff182SThomas Petazzoni struct mvneta_port *pp = netdev_priv(dev); 3888c5aff182SThomas Petazzoni 38892636ac3cSMarcin Wojtas if (!pp->neta_armada3700) { 3890120cfa50SGregory CLEMENT /* Inform that we are stopping so we don't want to setup the 38911c2722a9SGregory CLEMENT * driver for new CPUs in the notifiers. The code of the 38921c2722a9SGregory CLEMENT * notifier for CPU online is protected by the same spinlock, 38931c2722a9SGregory CLEMENT * so when we get the lock, the notifer work is done. 3894120cfa50SGregory CLEMENT */ 3895120cfa50SGregory CLEMENT spin_lock(&pp->lock); 3896120cfa50SGregory CLEMENT pp->is_stopped = true; 38971c2722a9SGregory CLEMENT spin_unlock(&pp->lock); 38981c2722a9SGregory CLEMENT 3899c5aff182SThomas Petazzoni mvneta_stop_dev(pp); 3900c5aff182SThomas Petazzoni mvneta_mdio_remove(pp); 390184a3f4dbSSebastian Andrzej Siewior 3902d26aac2dSDan Carpenter cpuhp_state_remove_instance_nocalls(online_hpstate, 3903d26aac2dSDan Carpenter &pp->node_online); 390484a3f4dbSSebastian Andrzej Siewior cpuhp_state_remove_instance_nocalls(CPUHP_NET_MVNETA_DEAD, 390584a3f4dbSSebastian Andrzej Siewior &pp->node_dead); 3906129219e4SGregory CLEMENT on_each_cpu(mvneta_percpu_disable, pp, true); 390712bb03b4SMaxime Ripard free_percpu_irq(dev->irq, pp->ports); 39082636ac3cSMarcin Wojtas } else { 39092636ac3cSMarcin Wojtas mvneta_stop_dev(pp); 39102636ac3cSMarcin Wojtas mvneta_mdio_remove(pp); 39112636ac3cSMarcin Wojtas free_irq(dev->irq, pp); 39122636ac3cSMarcin Wojtas } 39132636ac3cSMarcin Wojtas 3914c5aff182SThomas Petazzoni mvneta_cleanup_rxqs(pp); 3915c5aff182SThomas Petazzoni mvneta_cleanup_txqs(pp); 3916c5aff182SThomas Petazzoni 3917c5aff182SThomas Petazzoni return 0; 3918c5aff182SThomas Petazzoni } 3919c5aff182SThomas Petazzoni 392015f59456SThomas Petazzoni static int mvneta_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) 392115f59456SThomas Petazzoni { 3922503f9aa9SRussell King struct mvneta_port *pp = netdev_priv(dev); 392315f59456SThomas Petazzoni 3924503f9aa9SRussell King return phylink_mii_ioctl(pp->phylink, ifr, cmd); 392515f59456SThomas Petazzoni } 392615f59456SThomas Petazzoni 3927c5aff182SThomas Petazzoni /* Ethtool methods */ 3928c5aff182SThomas Petazzoni 3929013ad40dSPhilippe Reynes /* Set link ksettings (phy address, speed) for ethtools */ 39302dc0d2b4SBaoyou Xie static int 39312dc0d2b4SBaoyou Xie mvneta_ethtool_set_link_ksettings(struct net_device *ndev, 3932013ad40dSPhilippe Reynes const struct ethtool_link_ksettings *cmd) 3933c5aff182SThomas Petazzoni { 3934013ad40dSPhilippe Reynes struct mvneta_port *pp = netdev_priv(ndev); 3935c5aff182SThomas Petazzoni 3936503f9aa9SRussell King return phylink_ethtool_ksettings_set(pp->phylink, cmd); 39370c0744fcSStas Sergeev } 39380c0744fcSStas Sergeev 3939503f9aa9SRussell King /* Get link ksettings for ethtools */ 3940503f9aa9SRussell King static int 3941503f9aa9SRussell King mvneta_ethtool_get_link_ksettings(struct net_device *ndev, 3942503f9aa9SRussell King struct ethtool_link_ksettings *cmd) 3943503f9aa9SRussell King { 3944503f9aa9SRussell King struct mvneta_port *pp = netdev_priv(ndev); 39450c0744fcSStas Sergeev 3946503f9aa9SRussell King return phylink_ethtool_ksettings_get(pp->phylink, cmd); 39470c0744fcSStas Sergeev } 39480c0744fcSStas Sergeev 3949503f9aa9SRussell King static int mvneta_ethtool_nway_reset(struct net_device *dev) 3950503f9aa9SRussell King { 3951503f9aa9SRussell King struct mvneta_port *pp = netdev_priv(dev); 3952503f9aa9SRussell King 3953503f9aa9SRussell King return phylink_ethtool_nway_reset(pp->phylink); 3954c5aff182SThomas Petazzoni } 3955c5aff182SThomas Petazzoni 3956c5aff182SThomas Petazzoni /* Set interrupt coalescing for ethtools */ 3957c5aff182SThomas Petazzoni static int mvneta_ethtool_set_coalesce(struct net_device *dev, 3958c5aff182SThomas Petazzoni struct ethtool_coalesce *c) 3959c5aff182SThomas Petazzoni { 3960c5aff182SThomas Petazzoni struct mvneta_port *pp = netdev_priv(dev); 3961c5aff182SThomas Petazzoni int queue; 3962c5aff182SThomas Petazzoni 3963c5aff182SThomas Petazzoni for (queue = 0; queue < rxq_number; queue++) { 3964c5aff182SThomas Petazzoni struct mvneta_rx_queue *rxq = &pp->rxqs[queue]; 3965c5aff182SThomas Petazzoni rxq->time_coal = c->rx_coalesce_usecs; 3966c5aff182SThomas Petazzoni rxq->pkts_coal = c->rx_max_coalesced_frames; 3967c5aff182SThomas Petazzoni mvneta_rx_pkts_coal_set(pp, rxq, rxq->pkts_coal); 3968c5aff182SThomas Petazzoni mvneta_rx_time_coal_set(pp, rxq, rxq->time_coal); 3969c5aff182SThomas Petazzoni } 3970c5aff182SThomas Petazzoni 3971c5aff182SThomas Petazzoni for (queue = 0; queue < txq_number; queue++) { 3972c5aff182SThomas Petazzoni struct mvneta_tx_queue *txq = &pp->txqs[queue]; 3973c5aff182SThomas Petazzoni txq->done_pkts_coal = c->tx_max_coalesced_frames; 3974c5aff182SThomas Petazzoni mvneta_tx_done_pkts_coal_set(pp, txq, txq->done_pkts_coal); 3975c5aff182SThomas Petazzoni } 3976c5aff182SThomas Petazzoni 3977c5aff182SThomas Petazzoni return 0; 3978c5aff182SThomas Petazzoni } 3979c5aff182SThomas Petazzoni 3980c5aff182SThomas Petazzoni /* get coalescing for ethtools */ 3981c5aff182SThomas Petazzoni static int mvneta_ethtool_get_coalesce(struct net_device *dev, 3982c5aff182SThomas Petazzoni struct ethtool_coalesce *c) 3983c5aff182SThomas Petazzoni { 3984c5aff182SThomas Petazzoni struct mvneta_port *pp = netdev_priv(dev); 3985c5aff182SThomas Petazzoni 3986c5aff182SThomas Petazzoni c->rx_coalesce_usecs = pp->rxqs[0].time_coal; 3987c5aff182SThomas Petazzoni c->rx_max_coalesced_frames = pp->rxqs[0].pkts_coal; 3988c5aff182SThomas Petazzoni 3989c5aff182SThomas Petazzoni c->tx_max_coalesced_frames = pp->txqs[0].done_pkts_coal; 3990c5aff182SThomas Petazzoni return 0; 3991c5aff182SThomas Petazzoni } 3992c5aff182SThomas Petazzoni 3993c5aff182SThomas Petazzoni 3994c5aff182SThomas Petazzoni static void mvneta_ethtool_get_drvinfo(struct net_device *dev, 3995c5aff182SThomas Petazzoni struct ethtool_drvinfo *drvinfo) 3996c5aff182SThomas Petazzoni { 3997c5aff182SThomas Petazzoni strlcpy(drvinfo->driver, MVNETA_DRIVER_NAME, 3998c5aff182SThomas Petazzoni sizeof(drvinfo->driver)); 3999c5aff182SThomas Petazzoni strlcpy(drvinfo->version, MVNETA_DRIVER_VERSION, 4000c5aff182SThomas Petazzoni sizeof(drvinfo->version)); 4001c5aff182SThomas Petazzoni strlcpy(drvinfo->bus_info, dev_name(&dev->dev), 4002c5aff182SThomas Petazzoni sizeof(drvinfo->bus_info)); 4003c5aff182SThomas Petazzoni } 4004c5aff182SThomas Petazzoni 4005c5aff182SThomas Petazzoni 4006c5aff182SThomas Petazzoni static void mvneta_ethtool_get_ringparam(struct net_device *netdev, 4007c5aff182SThomas Petazzoni struct ethtool_ringparam *ring) 4008c5aff182SThomas Petazzoni { 4009c5aff182SThomas Petazzoni struct mvneta_port *pp = netdev_priv(netdev); 4010c5aff182SThomas Petazzoni 4011c5aff182SThomas Petazzoni ring->rx_max_pending = MVNETA_MAX_RXD; 4012c5aff182SThomas Petazzoni ring->tx_max_pending = MVNETA_MAX_TXD; 4013c5aff182SThomas Petazzoni ring->rx_pending = pp->rx_ring_size; 4014c5aff182SThomas Petazzoni ring->tx_pending = pp->tx_ring_size; 4015c5aff182SThomas Petazzoni } 4016c5aff182SThomas Petazzoni 4017c5aff182SThomas Petazzoni static int mvneta_ethtool_set_ringparam(struct net_device *dev, 4018c5aff182SThomas Petazzoni struct ethtool_ringparam *ring) 4019c5aff182SThomas Petazzoni { 4020c5aff182SThomas Petazzoni struct mvneta_port *pp = netdev_priv(dev); 4021c5aff182SThomas Petazzoni 4022c5aff182SThomas Petazzoni if ((ring->rx_pending == 0) || (ring->tx_pending == 0)) 4023c5aff182SThomas Petazzoni return -EINVAL; 4024c5aff182SThomas Petazzoni pp->rx_ring_size = ring->rx_pending < MVNETA_MAX_RXD ? 4025c5aff182SThomas Petazzoni ring->rx_pending : MVNETA_MAX_RXD; 40268eef5f97SEzequiel Garcia 40278eef5f97SEzequiel Garcia pp->tx_ring_size = clamp_t(u16, ring->tx_pending, 40288eef5f97SEzequiel Garcia MVNETA_MAX_SKB_DESCS * 2, MVNETA_MAX_TXD); 40298eef5f97SEzequiel Garcia if (pp->tx_ring_size != ring->tx_pending) 40308eef5f97SEzequiel Garcia netdev_warn(dev, "TX queue size set to %u (requested %u)\n", 40318eef5f97SEzequiel Garcia pp->tx_ring_size, ring->tx_pending); 4032c5aff182SThomas Petazzoni 4033c5aff182SThomas Petazzoni if (netif_running(dev)) { 4034c5aff182SThomas Petazzoni mvneta_stop(dev); 4035c5aff182SThomas Petazzoni if (mvneta_open(dev)) { 4036c5aff182SThomas Petazzoni netdev_err(dev, 4037c5aff182SThomas Petazzoni "error on opening device after ring param change\n"); 4038c5aff182SThomas Petazzoni return -ENOMEM; 4039c5aff182SThomas Petazzoni } 4040c5aff182SThomas Petazzoni } 4041c5aff182SThomas Petazzoni 4042c5aff182SThomas Petazzoni return 0; 4043c5aff182SThomas Petazzoni } 4044c5aff182SThomas Petazzoni 40454932a918SRussell King static void mvneta_ethtool_get_pauseparam(struct net_device *dev, 40464932a918SRussell King struct ethtool_pauseparam *pause) 40474932a918SRussell King { 40484932a918SRussell King struct mvneta_port *pp = netdev_priv(dev); 40494932a918SRussell King 40504932a918SRussell King phylink_ethtool_get_pauseparam(pp->phylink, pause); 40514932a918SRussell King } 40524932a918SRussell King 40534932a918SRussell King static int mvneta_ethtool_set_pauseparam(struct net_device *dev, 40544932a918SRussell King struct ethtool_pauseparam *pause) 40554932a918SRussell King { 40564932a918SRussell King struct mvneta_port *pp = netdev_priv(dev); 40574932a918SRussell King 40584932a918SRussell King return phylink_ethtool_set_pauseparam(pp->phylink, pause); 40594932a918SRussell King } 40604932a918SRussell King 40619b0cdefaSRussell King static void mvneta_ethtool_get_strings(struct net_device *netdev, u32 sset, 40629b0cdefaSRussell King u8 *data) 40639b0cdefaSRussell King { 40649b0cdefaSRussell King if (sset == ETH_SS_STATS) { 40659b0cdefaSRussell King int i; 40669b0cdefaSRussell King 40679b0cdefaSRussell King for (i = 0; i < ARRAY_SIZE(mvneta_statistics); i++) 40689b0cdefaSRussell King memcpy(data + i * ETH_GSTRING_LEN, 40699b0cdefaSRussell King mvneta_statistics[i].name, ETH_GSTRING_LEN); 40709b0cdefaSRussell King } 40719b0cdefaSRussell King } 40729b0cdefaSRussell King 40739b0cdefaSRussell King static void mvneta_ethtool_update_stats(struct mvneta_port *pp) 40749b0cdefaSRussell King { 40759b0cdefaSRussell King const struct mvneta_statistic *s; 40769b0cdefaSRussell King void __iomem *base = pp->base; 40776d81f451SRussell King u32 high, low; 40786d81f451SRussell King u64 val; 40799b0cdefaSRussell King int i; 40809b0cdefaSRussell King 40819b0cdefaSRussell King for (i = 0, s = mvneta_statistics; 40829b0cdefaSRussell King s < mvneta_statistics + ARRAY_SIZE(mvneta_statistics); 40839b0cdefaSRussell King s++, i++) { 40846d81f451SRussell King val = 0; 40856d81f451SRussell King 40869b0cdefaSRussell King switch (s->type) { 40879b0cdefaSRussell King case T_REG_32: 40889b0cdefaSRussell King val = readl_relaxed(base + s->offset); 40899b0cdefaSRussell King break; 40909b0cdefaSRussell King case T_REG_64: 40919b0cdefaSRussell King /* Docs say to read low 32-bit then high */ 40929b0cdefaSRussell King low = readl_relaxed(base + s->offset); 40939b0cdefaSRussell King high = readl_relaxed(base + s->offset + 4); 40946d81f451SRussell King val = (u64)high << 32 | low; 40956d81f451SRussell King break; 40966d81f451SRussell King case T_SW: 40976d81f451SRussell King switch (s->offset) { 40986d81f451SRussell King case ETHTOOL_STAT_EEE_WAKEUP: 40996d81f451SRussell King val = phylink_get_eee_err(pp->phylink); 41009b0cdefaSRussell King break; 410117a96da6SGregory CLEMENT case ETHTOOL_STAT_SKB_ALLOC_ERR: 410217a96da6SGregory CLEMENT val = pp->rxqs[0].skb_alloc_err; 410317a96da6SGregory CLEMENT break; 410417a96da6SGregory CLEMENT case ETHTOOL_STAT_REFILL_ERR: 410517a96da6SGregory CLEMENT val = pp->rxqs[0].refill_err; 410617a96da6SGregory CLEMENT break; 41079b0cdefaSRussell King } 41086d81f451SRussell King break; 41096d81f451SRussell King } 41106d81f451SRussell King 41116d81f451SRussell King pp->ethtool_stats[i] += val; 41129b0cdefaSRussell King } 41139b0cdefaSRussell King } 41149b0cdefaSRussell King 41159b0cdefaSRussell King static void mvneta_ethtool_get_stats(struct net_device *dev, 41169b0cdefaSRussell King struct ethtool_stats *stats, u64 *data) 41179b0cdefaSRussell King { 41189b0cdefaSRussell King struct mvneta_port *pp = netdev_priv(dev); 41199b0cdefaSRussell King int i; 41209b0cdefaSRussell King 41219b0cdefaSRussell King mvneta_ethtool_update_stats(pp); 41229b0cdefaSRussell King 41239b0cdefaSRussell King for (i = 0; i < ARRAY_SIZE(mvneta_statistics); i++) 41249b0cdefaSRussell King *data++ = pp->ethtool_stats[i]; 41259b0cdefaSRussell King } 41269b0cdefaSRussell King 41279b0cdefaSRussell King static int mvneta_ethtool_get_sset_count(struct net_device *dev, int sset) 41289b0cdefaSRussell King { 41299b0cdefaSRussell King if (sset == ETH_SS_STATS) 41309b0cdefaSRussell King return ARRAY_SIZE(mvneta_statistics); 41319b0cdefaSRussell King return -EOPNOTSUPP; 41329b0cdefaSRussell King } 41339b0cdefaSRussell King 41349a401deaSGregory CLEMENT static u32 mvneta_ethtool_get_rxfh_indir_size(struct net_device *dev) 41359a401deaSGregory CLEMENT { 41369a401deaSGregory CLEMENT return MVNETA_RSS_LU_TABLE_SIZE; 41379a401deaSGregory CLEMENT } 41389a401deaSGregory CLEMENT 41399a401deaSGregory CLEMENT static int mvneta_ethtool_get_rxnfc(struct net_device *dev, 41409a401deaSGregory CLEMENT struct ethtool_rxnfc *info, 41419a401deaSGregory CLEMENT u32 *rules __always_unused) 41429a401deaSGregory CLEMENT { 41439a401deaSGregory CLEMENT switch (info->cmd) { 41449a401deaSGregory CLEMENT case ETHTOOL_GRXRINGS: 41459a401deaSGregory CLEMENT info->data = rxq_number; 41469a401deaSGregory CLEMENT return 0; 41479a401deaSGregory CLEMENT case ETHTOOL_GRXFH: 41489a401deaSGregory CLEMENT return -EOPNOTSUPP; 41499a401deaSGregory CLEMENT default: 41509a401deaSGregory CLEMENT return -EOPNOTSUPP; 41519a401deaSGregory CLEMENT } 41529a401deaSGregory CLEMENT } 41539a401deaSGregory CLEMENT 41549a401deaSGregory CLEMENT static int mvneta_config_rss(struct mvneta_port *pp) 41559a401deaSGregory CLEMENT { 41569a401deaSGregory CLEMENT int cpu; 41579a401deaSGregory CLEMENT u32 val; 41589a401deaSGregory CLEMENT 41599a401deaSGregory CLEMENT netif_tx_stop_all_queues(pp->dev); 41609a401deaSGregory CLEMENT 41616b125d63SGregory CLEMENT on_each_cpu(mvneta_percpu_mask_interrupt, pp, true); 41629a401deaSGregory CLEMENT 41630f5c6c30SJisheng Zhang if (!pp->neta_armada3700) { 41649a401deaSGregory CLEMENT /* We have to synchronise on the napi of each CPU */ 41659a401deaSGregory CLEMENT for_each_online_cpu(cpu) { 41669a401deaSGregory CLEMENT struct mvneta_pcpu_port *pcpu_port = 41679a401deaSGregory CLEMENT per_cpu_ptr(pp->ports, cpu); 41689a401deaSGregory CLEMENT 41699a401deaSGregory CLEMENT napi_synchronize(&pcpu_port->napi); 41709a401deaSGregory CLEMENT napi_disable(&pcpu_port->napi); 41719a401deaSGregory CLEMENT } 41720f5c6c30SJisheng Zhang } else { 41730f5c6c30SJisheng Zhang napi_synchronize(&pp->napi); 41740f5c6c30SJisheng Zhang napi_disable(&pp->napi); 41750f5c6c30SJisheng Zhang } 41769a401deaSGregory CLEMENT 41779a401deaSGregory CLEMENT pp->rxq_def = pp->indir[0]; 41789a401deaSGregory CLEMENT 41799a401deaSGregory CLEMENT /* Update unicast mapping */ 41809a401deaSGregory CLEMENT mvneta_set_rx_mode(pp->dev); 41819a401deaSGregory CLEMENT 41829a401deaSGregory CLEMENT /* Update val of portCfg register accordingly with all RxQueue types */ 41839a401deaSGregory CLEMENT val = MVNETA_PORT_CONFIG_DEFL_VALUE(pp->rxq_def); 41849a401deaSGregory CLEMENT mvreg_write(pp, MVNETA_PORT_CONFIG, val); 41859a401deaSGregory CLEMENT 41869a401deaSGregory CLEMENT /* Update the elected CPU matching the new rxq_def */ 4187120cfa50SGregory CLEMENT spin_lock(&pp->lock); 41889a401deaSGregory CLEMENT mvneta_percpu_elect(pp); 4189120cfa50SGregory CLEMENT spin_unlock(&pp->lock); 41909a401deaSGregory CLEMENT 41910f5c6c30SJisheng Zhang if (!pp->neta_armada3700) { 41929a401deaSGregory CLEMENT /* We have to synchronise on the napi of each CPU */ 41939a401deaSGregory CLEMENT for_each_online_cpu(cpu) { 41949a401deaSGregory CLEMENT struct mvneta_pcpu_port *pcpu_port = 41959a401deaSGregory CLEMENT per_cpu_ptr(pp->ports, cpu); 41969a401deaSGregory CLEMENT 41979a401deaSGregory CLEMENT napi_enable(&pcpu_port->napi); 41989a401deaSGregory CLEMENT } 41990f5c6c30SJisheng Zhang } else { 42000f5c6c30SJisheng Zhang napi_enable(&pp->napi); 42010f5c6c30SJisheng Zhang } 42029a401deaSGregory CLEMENT 42039a401deaSGregory CLEMENT netif_tx_start_all_queues(pp->dev); 42049a401deaSGregory CLEMENT 42059a401deaSGregory CLEMENT return 0; 42069a401deaSGregory CLEMENT } 42079a401deaSGregory CLEMENT 42089a401deaSGregory CLEMENT static int mvneta_ethtool_set_rxfh(struct net_device *dev, const u32 *indir, 42099a401deaSGregory CLEMENT const u8 *key, const u8 hfunc) 42109a401deaSGregory CLEMENT { 42119a401deaSGregory CLEMENT struct mvneta_port *pp = netdev_priv(dev); 42122636ac3cSMarcin Wojtas 42132636ac3cSMarcin Wojtas /* Current code for Armada 3700 doesn't support RSS features yet */ 42142636ac3cSMarcin Wojtas if (pp->neta_armada3700) 42152636ac3cSMarcin Wojtas return -EOPNOTSUPP; 42162636ac3cSMarcin Wojtas 42179a401deaSGregory CLEMENT /* We require at least one supported parameter to be changed 42189a401deaSGregory CLEMENT * and no change in any of the unsupported parameters 42199a401deaSGregory CLEMENT */ 42209a401deaSGregory CLEMENT if (key || 42219a401deaSGregory CLEMENT (hfunc != ETH_RSS_HASH_NO_CHANGE && hfunc != ETH_RSS_HASH_TOP)) 42229a401deaSGregory CLEMENT return -EOPNOTSUPP; 42239a401deaSGregory CLEMENT 42249a401deaSGregory CLEMENT if (!indir) 42259a401deaSGregory CLEMENT return 0; 42269a401deaSGregory CLEMENT 42279a401deaSGregory CLEMENT memcpy(pp->indir, indir, MVNETA_RSS_LU_TABLE_SIZE); 42289a401deaSGregory CLEMENT 42299a401deaSGregory CLEMENT return mvneta_config_rss(pp); 42309a401deaSGregory CLEMENT } 42319a401deaSGregory CLEMENT 42329a401deaSGregory CLEMENT static int mvneta_ethtool_get_rxfh(struct net_device *dev, u32 *indir, u8 *key, 42339a401deaSGregory CLEMENT u8 *hfunc) 42349a401deaSGregory CLEMENT { 42359a401deaSGregory CLEMENT struct mvneta_port *pp = netdev_priv(dev); 42369a401deaSGregory CLEMENT 42372636ac3cSMarcin Wojtas /* Current code for Armada 3700 doesn't support RSS features yet */ 42382636ac3cSMarcin Wojtas if (pp->neta_armada3700) 42392636ac3cSMarcin Wojtas return -EOPNOTSUPP; 42402636ac3cSMarcin Wojtas 42419a401deaSGregory CLEMENT if (hfunc) 42429a401deaSGregory CLEMENT *hfunc = ETH_RSS_HASH_TOP; 42439a401deaSGregory CLEMENT 42449a401deaSGregory CLEMENT if (!indir) 42459a401deaSGregory CLEMENT return 0; 42469a401deaSGregory CLEMENT 42479a401deaSGregory CLEMENT memcpy(indir, pp->indir, MVNETA_RSS_LU_TABLE_SIZE); 42489a401deaSGregory CLEMENT 42499a401deaSGregory CLEMENT return 0; 42509a401deaSGregory CLEMENT } 42519a401deaSGregory CLEMENT 4252b60a00f9SJingju Hou static void mvneta_ethtool_get_wol(struct net_device *dev, 4253b60a00f9SJingju Hou struct ethtool_wolinfo *wol) 4254b60a00f9SJingju Hou { 4255503f9aa9SRussell King struct mvneta_port *pp = netdev_priv(dev); 4256b60a00f9SJingju Hou 4257503f9aa9SRussell King phylink_ethtool_get_wol(pp->phylink, wol); 4258b60a00f9SJingju Hou } 4259b60a00f9SJingju Hou 4260b60a00f9SJingju Hou static int mvneta_ethtool_set_wol(struct net_device *dev, 4261b60a00f9SJingju Hou struct ethtool_wolinfo *wol) 4262b60a00f9SJingju Hou { 4263503f9aa9SRussell King struct mvneta_port *pp = netdev_priv(dev); 426482960fffSJisheng Zhang int ret; 426582960fffSJisheng Zhang 4266503f9aa9SRussell King ret = phylink_ethtool_set_wol(pp->phylink, wol); 426782960fffSJisheng Zhang if (!ret) 426882960fffSJisheng Zhang device_set_wakeup_enable(&dev->dev, !!wol->wolopts); 426982960fffSJisheng Zhang 427082960fffSJisheng Zhang return ret; 4271b60a00f9SJingju Hou } 4272b60a00f9SJingju Hou 42736d81f451SRussell King static int mvneta_ethtool_get_eee(struct net_device *dev, 42746d81f451SRussell King struct ethtool_eee *eee) 42756d81f451SRussell King { 42766d81f451SRussell King struct mvneta_port *pp = netdev_priv(dev); 42776d81f451SRussell King u32 lpi_ctl0; 42786d81f451SRussell King 42796d81f451SRussell King lpi_ctl0 = mvreg_read(pp, MVNETA_LPI_CTRL_0); 42806d81f451SRussell King 42816d81f451SRussell King eee->eee_enabled = pp->eee_enabled; 42826d81f451SRussell King eee->eee_active = pp->eee_active; 42836d81f451SRussell King eee->tx_lpi_enabled = pp->tx_lpi_enabled; 42846d81f451SRussell King eee->tx_lpi_timer = (lpi_ctl0) >> 8; // * scale; 42856d81f451SRussell King 42866d81f451SRussell King return phylink_ethtool_get_eee(pp->phylink, eee); 42876d81f451SRussell King } 42886d81f451SRussell King 42896d81f451SRussell King static int mvneta_ethtool_set_eee(struct net_device *dev, 42906d81f451SRussell King struct ethtool_eee *eee) 42916d81f451SRussell King { 42926d81f451SRussell King struct mvneta_port *pp = netdev_priv(dev); 42936d81f451SRussell King u32 lpi_ctl0; 42946d81f451SRussell King 42956d81f451SRussell King /* The Armada 37x documents do not give limits for this other than 42966d81f451SRussell King * it being an 8-bit register. */ 4297e4a3e9ffSYueHaibing if (eee->tx_lpi_enabled && eee->tx_lpi_timer > 255) 42986d81f451SRussell King return -EINVAL; 42996d81f451SRussell King 43006d81f451SRussell King lpi_ctl0 = mvreg_read(pp, MVNETA_LPI_CTRL_0); 43016d81f451SRussell King lpi_ctl0 &= ~(0xff << 8); 43026d81f451SRussell King lpi_ctl0 |= eee->tx_lpi_timer << 8; 43036d81f451SRussell King mvreg_write(pp, MVNETA_LPI_CTRL_0, lpi_ctl0); 43046d81f451SRussell King 43056d81f451SRussell King pp->eee_enabled = eee->eee_enabled; 43066d81f451SRussell King pp->tx_lpi_enabled = eee->tx_lpi_enabled; 43076d81f451SRussell King 43086d81f451SRussell King mvneta_set_eee(pp, eee->tx_lpi_enabled && eee->eee_enabled); 43096d81f451SRussell King 43106d81f451SRussell King return phylink_ethtool_set_eee(pp->phylink, eee); 43116d81f451SRussell King } 43126d81f451SRussell King 4313c5aff182SThomas Petazzoni static const struct net_device_ops mvneta_netdev_ops = { 4314c5aff182SThomas Petazzoni .ndo_open = mvneta_open, 4315c5aff182SThomas Petazzoni .ndo_stop = mvneta_stop, 4316c5aff182SThomas Petazzoni .ndo_start_xmit = mvneta_tx, 4317c5aff182SThomas Petazzoni .ndo_set_rx_mode = mvneta_set_rx_mode, 4318c5aff182SThomas Petazzoni .ndo_set_mac_address = mvneta_set_mac_addr, 4319c5aff182SThomas Petazzoni .ndo_change_mtu = mvneta_change_mtu, 4320b65657fcSSimon Guinot .ndo_fix_features = mvneta_fix_features, 4321c5aff182SThomas Petazzoni .ndo_get_stats64 = mvneta_get_stats64, 432215f59456SThomas Petazzoni .ndo_do_ioctl = mvneta_ioctl, 4323c5aff182SThomas Petazzoni }; 4324c5aff182SThomas Petazzoni 43254581be42SJisheng Zhang static const struct ethtool_ops mvneta_eth_tool_ops = { 4326503f9aa9SRussell King .nway_reset = mvneta_ethtool_nway_reset, 4327c5aff182SThomas Petazzoni .get_link = ethtool_op_get_link, 4328c5aff182SThomas Petazzoni .set_coalesce = mvneta_ethtool_set_coalesce, 4329c5aff182SThomas Petazzoni .get_coalesce = mvneta_ethtool_get_coalesce, 4330c5aff182SThomas Petazzoni .get_drvinfo = mvneta_ethtool_get_drvinfo, 4331c5aff182SThomas Petazzoni .get_ringparam = mvneta_ethtool_get_ringparam, 4332c5aff182SThomas Petazzoni .set_ringparam = mvneta_ethtool_set_ringparam, 43334932a918SRussell King .get_pauseparam = mvneta_ethtool_get_pauseparam, 43344932a918SRussell King .set_pauseparam = mvneta_ethtool_set_pauseparam, 43359b0cdefaSRussell King .get_strings = mvneta_ethtool_get_strings, 43369b0cdefaSRussell King .get_ethtool_stats = mvneta_ethtool_get_stats, 43379b0cdefaSRussell King .get_sset_count = mvneta_ethtool_get_sset_count, 43389a401deaSGregory CLEMENT .get_rxfh_indir_size = mvneta_ethtool_get_rxfh_indir_size, 43399a401deaSGregory CLEMENT .get_rxnfc = mvneta_ethtool_get_rxnfc, 43409a401deaSGregory CLEMENT .get_rxfh = mvneta_ethtool_get_rxfh, 43419a401deaSGregory CLEMENT .set_rxfh = mvneta_ethtool_set_rxfh, 4342503f9aa9SRussell King .get_link_ksettings = mvneta_ethtool_get_link_ksettings, 4343013ad40dSPhilippe Reynes .set_link_ksettings = mvneta_ethtool_set_link_ksettings, 4344b60a00f9SJingju Hou .get_wol = mvneta_ethtool_get_wol, 4345b60a00f9SJingju Hou .set_wol = mvneta_ethtool_set_wol, 43466d81f451SRussell King .get_eee = mvneta_ethtool_get_eee, 43476d81f451SRussell King .set_eee = mvneta_ethtool_set_eee, 4348c5aff182SThomas Petazzoni }; 4349c5aff182SThomas Petazzoni 4350c5aff182SThomas Petazzoni /* Initialize hw */ 43519672850bSEzequiel Garcia static int mvneta_init(struct device *dev, struct mvneta_port *pp) 4352c5aff182SThomas Petazzoni { 4353c5aff182SThomas Petazzoni int queue; 4354c5aff182SThomas Petazzoni 4355c5aff182SThomas Petazzoni /* Disable port */ 4356c5aff182SThomas Petazzoni mvneta_port_disable(pp); 4357c5aff182SThomas Petazzoni 4358c5aff182SThomas Petazzoni /* Set port default values */ 4359c5aff182SThomas Petazzoni mvneta_defaults_set(pp); 4360c5aff182SThomas Petazzoni 43615d6312edSMarkus Elfring pp->txqs = devm_kcalloc(dev, txq_number, sizeof(*pp->txqs), GFP_KERNEL); 4362c5aff182SThomas Petazzoni if (!pp->txqs) 4363c5aff182SThomas Petazzoni return -ENOMEM; 4364c5aff182SThomas Petazzoni 4365c5aff182SThomas Petazzoni /* Initialize TX descriptor rings */ 4366c5aff182SThomas Petazzoni for (queue = 0; queue < txq_number; queue++) { 4367c5aff182SThomas Petazzoni struct mvneta_tx_queue *txq = &pp->txqs[queue]; 4368c5aff182SThomas Petazzoni txq->id = queue; 4369c5aff182SThomas Petazzoni txq->size = pp->tx_ring_size; 4370c5aff182SThomas Petazzoni txq->done_pkts_coal = MVNETA_TXDONE_COAL_PKTS; 4371c5aff182SThomas Petazzoni } 4372c5aff182SThomas Petazzoni 43735d6312edSMarkus Elfring pp->rxqs = devm_kcalloc(dev, rxq_number, sizeof(*pp->rxqs), GFP_KERNEL); 43749672850bSEzequiel Garcia if (!pp->rxqs) 4375c5aff182SThomas Petazzoni return -ENOMEM; 4376c5aff182SThomas Petazzoni 4377c5aff182SThomas Petazzoni /* Create Rx descriptor rings */ 4378c5aff182SThomas Petazzoni for (queue = 0; queue < rxq_number; queue++) { 4379c5aff182SThomas Petazzoni struct mvneta_rx_queue *rxq = &pp->rxqs[queue]; 4380c5aff182SThomas Petazzoni rxq->id = queue; 4381c5aff182SThomas Petazzoni rxq->size = pp->rx_ring_size; 4382c5aff182SThomas Petazzoni rxq->pkts_coal = MVNETA_RX_COAL_PKTS; 4383c5aff182SThomas Petazzoni rxq->time_coal = MVNETA_RX_COAL_USEC; 438429110630SMarkus Elfring rxq->buf_virt_addr 438529110630SMarkus Elfring = devm_kmalloc_array(pp->dev->dev.parent, 438629110630SMarkus Elfring rxq->size, 438729110630SMarkus Elfring sizeof(*rxq->buf_virt_addr), 4388f88bee1cSGregory CLEMENT GFP_KERNEL); 4389f88bee1cSGregory CLEMENT if (!rxq->buf_virt_addr) 4390f88bee1cSGregory CLEMENT return -ENOMEM; 4391c5aff182SThomas Petazzoni } 4392c5aff182SThomas Petazzoni 4393c5aff182SThomas Petazzoni return 0; 4394c5aff182SThomas Petazzoni } 4395c5aff182SThomas Petazzoni 4396c5aff182SThomas Petazzoni /* platform glue : initialize decoding windows */ 439703ce758eSGreg KH static void mvneta_conf_mbus_windows(struct mvneta_port *pp, 4398c5aff182SThomas Petazzoni const struct mbus_dram_target_info *dram) 4399c5aff182SThomas Petazzoni { 4400c5aff182SThomas Petazzoni u32 win_enable; 4401c5aff182SThomas Petazzoni u32 win_protect; 4402c5aff182SThomas Petazzoni int i; 4403c5aff182SThomas Petazzoni 4404c5aff182SThomas Petazzoni for (i = 0; i < 6; i++) { 4405c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_WIN_BASE(i), 0); 4406c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_WIN_SIZE(i), 0); 4407c5aff182SThomas Petazzoni 4408c5aff182SThomas Petazzoni if (i < 4) 4409c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_WIN_REMAP(i), 0); 4410c5aff182SThomas Petazzoni } 4411c5aff182SThomas Petazzoni 4412c5aff182SThomas Petazzoni win_enable = 0x3f; 4413c5aff182SThomas Petazzoni win_protect = 0; 4414c5aff182SThomas Petazzoni 44152636ac3cSMarcin Wojtas if (dram) { 4416c5aff182SThomas Petazzoni for (i = 0; i < dram->num_cs; i++) { 4417c5aff182SThomas Petazzoni const struct mbus_dram_window *cs = dram->cs + i; 44182636ac3cSMarcin Wojtas 44192636ac3cSMarcin Wojtas mvreg_write(pp, MVNETA_WIN_BASE(i), 44202636ac3cSMarcin Wojtas (cs->base & 0xffff0000) | 44212636ac3cSMarcin Wojtas (cs->mbus_attr << 8) | 44222636ac3cSMarcin Wojtas dram->mbus_dram_target_id); 4423c5aff182SThomas Petazzoni 4424c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_WIN_SIZE(i), 4425c5aff182SThomas Petazzoni (cs->size - 1) & 0xffff0000); 4426c5aff182SThomas Petazzoni 4427c5aff182SThomas Petazzoni win_enable &= ~(1 << i); 4428c5aff182SThomas Petazzoni win_protect |= 3 << (2 * i); 4429c5aff182SThomas Petazzoni } 44302636ac3cSMarcin Wojtas } else { 44312636ac3cSMarcin Wojtas /* For Armada3700 open default 4GB Mbus window, leaving 44322636ac3cSMarcin Wojtas * arbitration of target/attribute to a different layer 44332636ac3cSMarcin Wojtas * of configuration. 44342636ac3cSMarcin Wojtas */ 44352636ac3cSMarcin Wojtas mvreg_write(pp, MVNETA_WIN_SIZE(0), 0xffff0000); 44362636ac3cSMarcin Wojtas win_enable &= ~BIT(0); 44372636ac3cSMarcin Wojtas win_protect = 3; 44382636ac3cSMarcin Wojtas } 4439c5aff182SThomas Petazzoni 4440c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_BASE_ADDR_ENABLE, win_enable); 4441db6ba9a5SMarcin Wojtas mvreg_write(pp, MVNETA_ACCESS_PROTECT_ENABLE, win_protect); 4442c5aff182SThomas Petazzoni } 4443c5aff182SThomas Petazzoni 4444c5aff182SThomas Petazzoni /* Power up the port */ 44453f1dd4bcSThomas Petazzoni static int mvneta_port_power_up(struct mvneta_port *pp, int phy_mode) 4446c5aff182SThomas Petazzoni { 4447c5aff182SThomas Petazzoni /* MAC Cause register should be cleared */ 4448c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_UNIT_INTR_CAUSE, 0); 4449c5aff182SThomas Petazzoni 445032699954SRussell King if (phy_mode == PHY_INTERFACE_MODE_QSGMII) 44513f1dd4bcSThomas Petazzoni mvreg_write(pp, MVNETA_SERDES_CFG, MVNETA_QSGMII_SERDES_PROTO); 445222f4bf8aSRussell King else if (phy_mode == PHY_INTERFACE_MODE_SGMII || 4453a10c1c81SRussell King phy_interface_mode_is_8023z(phy_mode)) 44543f1dd4bcSThomas Petazzoni mvreg_write(pp, MVNETA_SERDES_CFG, MVNETA_SGMII_SERDES_PROTO); 445532699954SRussell King else if (!phy_interface_mode_is_rgmii(phy_mode)) 44563f1dd4bcSThomas Petazzoni return -EINVAL; 44573f1dd4bcSThomas Petazzoni 44583f1dd4bcSThomas Petazzoni return 0; 4459c5aff182SThomas Petazzoni } 4460c5aff182SThomas Petazzoni 4461c5aff182SThomas Petazzoni /* Device initialization routine */ 446203ce758eSGreg KH static int mvneta_probe(struct platform_device *pdev) 4463c5aff182SThomas Petazzoni { 4464c3f0dd38SThomas Petazzoni struct resource *res; 4465c5aff182SThomas Petazzoni struct device_node *dn = pdev->dev.of_node; 4466dc35a10fSMarcin Wojtas struct device_node *bm_node; 4467c5aff182SThomas Petazzoni struct mvneta_port *pp; 4468c5aff182SThomas Petazzoni struct net_device *dev; 4469503f9aa9SRussell King struct phylink *phylink; 4470a10c1c81SRussell King struct phy *comphy; 44718cc3e439SThomas Petazzoni const char *dt_mac_addr; 44728cc3e439SThomas Petazzoni char hw_mac_addr[ETH_ALEN]; 44738cc3e439SThomas Petazzoni const char *mac_from; 44749110ee07SMarcin Wojtas int tx_csum_limit; 4475c5aff182SThomas Petazzoni int phy_mode; 4476c5aff182SThomas Petazzoni int err; 447712bb03b4SMaxime Ripard int cpu; 4478c5aff182SThomas Petazzoni 4479a3ddd94fSRosen Penev dev = devm_alloc_etherdev_mqs(&pdev->dev, sizeof(struct mvneta_port), 4480a3ddd94fSRosen Penev txq_number, rxq_number); 4481c5aff182SThomas Petazzoni if (!dev) 4482c5aff182SThomas Petazzoni return -ENOMEM; 4483c5aff182SThomas Petazzoni 4484c5aff182SThomas Petazzoni dev->irq = irq_of_parse_and_map(dn, 0); 4485a3ddd94fSRosen Penev if (dev->irq == 0) 4486a3ddd94fSRosen Penev return -EINVAL; 4487c5aff182SThomas Petazzoni 4488c5aff182SThomas Petazzoni phy_mode = of_get_phy_mode(dn); 4489c5aff182SThomas Petazzoni if (phy_mode < 0) { 4490c5aff182SThomas Petazzoni dev_err(&pdev->dev, "incorrect phy-mode\n"); 4491c5aff182SThomas Petazzoni err = -EINVAL; 4492503f9aa9SRussell King goto err_free_irq; 4493503f9aa9SRussell King } 4494503f9aa9SRussell King 4495a10c1c81SRussell King comphy = devm_of_phy_get(&pdev->dev, dn, NULL); 4496a10c1c81SRussell King if (comphy == ERR_PTR(-EPROBE_DEFER)) { 4497a10c1c81SRussell King err = -EPROBE_DEFER; 4498a10c1c81SRussell King goto err_free_irq; 4499a10c1c81SRussell King } else if (IS_ERR(comphy)) { 4500a10c1c81SRussell King comphy = NULL; 4501a10c1c81SRussell King } 4502a10c1c81SRussell King 4503503f9aa9SRussell King phylink = phylink_create(dev, pdev->dev.fwnode, phy_mode, 4504503f9aa9SRussell King &mvneta_phylink_ops); 4505503f9aa9SRussell King if (IS_ERR(phylink)) { 4506503f9aa9SRussell King err = PTR_ERR(phylink); 4507503f9aa9SRussell King goto err_free_irq; 4508c5aff182SThomas Petazzoni } 4509c5aff182SThomas Petazzoni 4510c5aff182SThomas Petazzoni dev->tx_queue_len = MVNETA_MAX_TXD; 4511c5aff182SThomas Petazzoni dev->watchdog_timeo = 5 * HZ; 4512c5aff182SThomas Petazzoni dev->netdev_ops = &mvneta_netdev_ops; 4513c5aff182SThomas Petazzoni 45147ad24ea4SWilfried Klaebe dev->ethtool_ops = &mvneta_eth_tool_ops; 4515c5aff182SThomas Petazzoni 4516c5aff182SThomas Petazzoni pp = netdev_priv(dev); 45171c2722a9SGregory CLEMENT spin_lock_init(&pp->lock); 4518503f9aa9SRussell King pp->phylink = phylink; 4519a10c1c81SRussell King pp->comphy = comphy; 4520c5aff182SThomas Petazzoni pp->phy_interface = phy_mode; 4521503f9aa9SRussell King pp->dn = dn; 4522c5aff182SThomas Petazzoni 452390b74c01SGregory CLEMENT pp->rxq_def = rxq_def; 45249a401deaSGregory CLEMENT pp->indir[0] = rxq_def; 45259a401deaSGregory CLEMENT 45262636ac3cSMarcin Wojtas /* Get special SoC configurations */ 45272636ac3cSMarcin Wojtas if (of_device_is_compatible(dn, "marvell,armada-3700-neta")) 45282636ac3cSMarcin Wojtas pp->neta_armada3700 = true; 45292636ac3cSMarcin Wojtas 45302804ba4eSJisheng Zhang pp->clk = devm_clk_get(&pdev->dev, "core"); 45312804ba4eSJisheng Zhang if (IS_ERR(pp->clk)) 4532189dd626SThomas Petazzoni pp->clk = devm_clk_get(&pdev->dev, NULL); 4533189dd626SThomas Petazzoni if (IS_ERR(pp->clk)) { 4534189dd626SThomas Petazzoni err = PTR_ERR(pp->clk); 4535503f9aa9SRussell King goto err_free_phylink; 4536189dd626SThomas Petazzoni } 4537189dd626SThomas Petazzoni 4538189dd626SThomas Petazzoni clk_prepare_enable(pp->clk); 4539189dd626SThomas Petazzoni 454015cc4a4aSJisheng Zhang pp->clk_bus = devm_clk_get(&pdev->dev, "bus"); 454115cc4a4aSJisheng Zhang if (!IS_ERR(pp->clk_bus)) 454215cc4a4aSJisheng Zhang clk_prepare_enable(pp->clk_bus); 454315cc4a4aSJisheng Zhang 4544c3f0dd38SThomas Petazzoni res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 4545c3f0dd38SThomas Petazzoni pp->base = devm_ioremap_resource(&pdev->dev, res); 4546c3f0dd38SThomas Petazzoni if (IS_ERR(pp->base)) { 4547c3f0dd38SThomas Petazzoni err = PTR_ERR(pp->base); 45485445eaf3SArnaud Patard \(Rtp\) goto err_clk; 45495445eaf3SArnaud Patard \(Rtp\) } 45505445eaf3SArnaud Patard \(Rtp\) 455112bb03b4SMaxime Ripard /* Alloc per-cpu port structure */ 455212bb03b4SMaxime Ripard pp->ports = alloc_percpu(struct mvneta_pcpu_port); 455312bb03b4SMaxime Ripard if (!pp->ports) { 455412bb03b4SMaxime Ripard err = -ENOMEM; 455512bb03b4SMaxime Ripard goto err_clk; 455612bb03b4SMaxime Ripard } 455712bb03b4SMaxime Ripard 455874c41b04Swilly tarreau /* Alloc per-cpu stats */ 45591c213bd2SWANG Cong pp->stats = netdev_alloc_pcpu_stats(struct mvneta_pcpu_stats); 456074c41b04Swilly tarreau if (!pp->stats) { 456174c41b04Swilly tarreau err = -ENOMEM; 456212bb03b4SMaxime Ripard goto err_free_ports; 456374c41b04Swilly tarreau } 456474c41b04Swilly tarreau 45658cc3e439SThomas Petazzoni dt_mac_addr = of_get_mac_address(dn); 4566a51645f7SPetr Štetiar if (!IS_ERR(dt_mac_addr)) { 45678cc3e439SThomas Petazzoni mac_from = "device tree"; 45688cc3e439SThomas Petazzoni memcpy(dev->dev_addr, dt_mac_addr, ETH_ALEN); 45698cc3e439SThomas Petazzoni } else { 45708cc3e439SThomas Petazzoni mvneta_get_mac_addr(pp, hw_mac_addr); 45718cc3e439SThomas Petazzoni if (is_valid_ether_addr(hw_mac_addr)) { 45728cc3e439SThomas Petazzoni mac_from = "hardware"; 45738cc3e439SThomas Petazzoni memcpy(dev->dev_addr, hw_mac_addr, ETH_ALEN); 45748cc3e439SThomas Petazzoni } else { 45758cc3e439SThomas Petazzoni mac_from = "random"; 45768cc3e439SThomas Petazzoni eth_hw_addr_random(dev); 45778cc3e439SThomas Petazzoni } 45788cc3e439SThomas Petazzoni } 45798cc3e439SThomas Petazzoni 45809110ee07SMarcin Wojtas if (!of_property_read_u32(dn, "tx-csum-limit", &tx_csum_limit)) { 45819110ee07SMarcin Wojtas if (tx_csum_limit < 0 || 45829110ee07SMarcin Wojtas tx_csum_limit > MVNETA_TX_CSUM_MAX_SIZE) { 45839110ee07SMarcin Wojtas tx_csum_limit = MVNETA_TX_CSUM_DEF_SIZE; 45849110ee07SMarcin Wojtas dev_info(&pdev->dev, 45859110ee07SMarcin Wojtas "Wrong TX csum limit in DT, set to %dB\n", 45869110ee07SMarcin Wojtas MVNETA_TX_CSUM_DEF_SIZE); 45879110ee07SMarcin Wojtas } 45889110ee07SMarcin Wojtas } else if (of_device_is_compatible(dn, "marvell,armada-370-neta")) { 45899110ee07SMarcin Wojtas tx_csum_limit = MVNETA_TX_CSUM_DEF_SIZE; 45909110ee07SMarcin Wojtas } else { 45919110ee07SMarcin Wojtas tx_csum_limit = MVNETA_TX_CSUM_MAX_SIZE; 45929110ee07SMarcin Wojtas } 45939110ee07SMarcin Wojtas 45949110ee07SMarcin Wojtas pp->tx_csum_limit = tx_csum_limit; 4595b65657fcSSimon Guinot 45969768b45cSJane Li pp->dram_target_info = mv_mbus_dram_info(); 45972636ac3cSMarcin Wojtas /* Armada3700 requires setting default configuration of Mbus 45982636ac3cSMarcin Wojtas * windows, however without using filled mbus_dram_target_info 45992636ac3cSMarcin Wojtas * structure. 46002636ac3cSMarcin Wojtas */ 46019768b45cSJane Li if (pp->dram_target_info || pp->neta_armada3700) 46029768b45cSJane Li mvneta_conf_mbus_windows(pp, pp->dram_target_info); 4603dc35a10fSMarcin Wojtas 4604c5aff182SThomas Petazzoni pp->tx_ring_size = MVNETA_MAX_TXD; 4605c5aff182SThomas Petazzoni pp->rx_ring_size = MVNETA_MAX_RXD; 4606c5aff182SThomas Petazzoni 4607c5aff182SThomas Petazzoni pp->dev = dev; 4608c5aff182SThomas Petazzoni SET_NETDEV_DEV(dev, &pdev->dev); 4609c5aff182SThomas Petazzoni 4610dc35a10fSMarcin Wojtas pp->id = global_port_id++; 4611562e2f46SYelena Krivosheev pp->rx_offset_correction = 0; /* not relevant for SW BM */ 4612dc35a10fSMarcin Wojtas 4613dc35a10fSMarcin Wojtas /* Obtain access to BM resources if enabled and already initialized */ 4614dc35a10fSMarcin Wojtas bm_node = of_parse_phandle(dn, "buffer-manager", 0); 4615965cbbecSGregory CLEMENT if (bm_node) { 4616965cbbecSGregory CLEMENT pp->bm_priv = mvneta_bm_get(bm_node); 4617965cbbecSGregory CLEMENT if (pp->bm_priv) { 4618dc35a10fSMarcin Wojtas err = mvneta_bm_port_init(pdev, pp); 4619dc35a10fSMarcin Wojtas if (err < 0) { 4620965cbbecSGregory CLEMENT dev_info(&pdev->dev, 4621965cbbecSGregory CLEMENT "use SW buffer management\n"); 4622965cbbecSGregory CLEMENT mvneta_bm_put(pp->bm_priv); 4623dc35a10fSMarcin Wojtas pp->bm_priv = NULL; 4624dc35a10fSMarcin Wojtas } 4625dc35a10fSMarcin Wojtas } 4626562e2f46SYelena Krivosheev /* Set RX packet offset correction for platforms, whose 4627562e2f46SYelena Krivosheev * NET_SKB_PAD, exceeds 64B. It should be 64B for 64-bit 4628562e2f46SYelena Krivosheev * platforms and 0B for 32-bit ones. 4629562e2f46SYelena Krivosheev */ 4630562e2f46SYelena Krivosheev pp->rx_offset_correction = max(0, 4631562e2f46SYelena Krivosheev NET_SKB_PAD - 4632562e2f46SYelena Krivosheev MVNETA_RX_PKT_OFFSET_CORRECTION); 4633965cbbecSGregory CLEMENT } 4634d4e4da00SPeter Chen of_node_put(bm_node); 4635dc35a10fSMarcin Wojtas 46369672850bSEzequiel Garcia err = mvneta_init(&pdev->dev, pp); 46379672850bSEzequiel Garcia if (err < 0) 4638dc35a10fSMarcin Wojtas goto err_netdev; 46393f1dd4bcSThomas Petazzoni 46403f1dd4bcSThomas Petazzoni err = mvneta_port_power_up(pp, phy_mode); 46413f1dd4bcSThomas Petazzoni if (err < 0) { 46423f1dd4bcSThomas Petazzoni dev_err(&pdev->dev, "can't power up port\n"); 4643dc35a10fSMarcin Wojtas goto err_netdev; 46443f1dd4bcSThomas Petazzoni } 4645c5aff182SThomas Petazzoni 46462636ac3cSMarcin Wojtas /* Armada3700 network controller does not support per-cpu 46472636ac3cSMarcin Wojtas * operation, so only single NAPI should be initialized. 46482636ac3cSMarcin Wojtas */ 46492636ac3cSMarcin Wojtas if (pp->neta_armada3700) { 46502636ac3cSMarcin Wojtas netif_napi_add(dev, &pp->napi, mvneta_poll, NAPI_POLL_WEIGHT); 46512636ac3cSMarcin Wojtas } else { 465212bb03b4SMaxime Ripard for_each_present_cpu(cpu) { 46532636ac3cSMarcin Wojtas struct mvneta_pcpu_port *port = 46542636ac3cSMarcin Wojtas per_cpu_ptr(pp->ports, cpu); 465512bb03b4SMaxime Ripard 46562636ac3cSMarcin Wojtas netif_napi_add(dev, &port->napi, mvneta_poll, 46572636ac3cSMarcin Wojtas NAPI_POLL_WEIGHT); 465812bb03b4SMaxime Ripard port->pp = pp; 465912bb03b4SMaxime Ripard } 46602636ac3cSMarcin Wojtas } 4661c5aff182SThomas Petazzoni 46627772988aSJisheng Zhang dev->features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | 46637772988aSJisheng Zhang NETIF_F_TSO | NETIF_F_RXCSUM; 466401ef26caSEzequiel Garcia dev->hw_features |= dev->features; 466501ef26caSEzequiel Garcia dev->vlan_features |= dev->features; 466697db8afaSAndrew Lunn dev->priv_flags |= IFF_LIVE_ADDR_CHANGE; 46678eef5f97SEzequiel Garcia dev->gso_max_segs = MVNETA_MAX_TSO_SEGS; 4668b50b72deSwilly tarreau 46695777987eSJarod Wilson /* MTU range: 68 - 9676 */ 46705777987eSJarod Wilson dev->min_mtu = ETH_MIN_MTU; 46715777987eSJarod Wilson /* 9676 == 9700 - 20 and rounding to 8 */ 46725777987eSJarod Wilson dev->max_mtu = 9676; 46735777987eSJarod Wilson 4674c5aff182SThomas Petazzoni err = register_netdev(dev); 4675c5aff182SThomas Petazzoni if (err < 0) { 4676c5aff182SThomas Petazzoni dev_err(&pdev->dev, "failed to register\n"); 46779672850bSEzequiel Garcia goto err_free_stats; 4678c5aff182SThomas Petazzoni } 4679c5aff182SThomas Petazzoni 46808cc3e439SThomas Petazzoni netdev_info(dev, "Using %s mac address %pM\n", mac_from, 46818cc3e439SThomas Petazzoni dev->dev_addr); 4682c5aff182SThomas Petazzoni 4683c5aff182SThomas Petazzoni platform_set_drvdata(pdev, pp->dev); 4684c5aff182SThomas Petazzoni 4685c5aff182SThomas Petazzoni return 0; 4686c5aff182SThomas Petazzoni 4687dc35a10fSMarcin Wojtas err_netdev: 4688dc35a10fSMarcin Wojtas unregister_netdev(dev); 4689dc35a10fSMarcin Wojtas if (pp->bm_priv) { 4690dc35a10fSMarcin Wojtas mvneta_bm_pool_destroy(pp->bm_priv, pp->pool_long, 1 << pp->id); 4691dc35a10fSMarcin Wojtas mvneta_bm_pool_destroy(pp->bm_priv, pp->pool_short, 4692dc35a10fSMarcin Wojtas 1 << pp->id); 4693965cbbecSGregory CLEMENT mvneta_bm_put(pp->bm_priv); 4694dc35a10fSMarcin Wojtas } 469574c41b04Swilly tarreau err_free_stats: 469674c41b04Swilly tarreau free_percpu(pp->stats); 469712bb03b4SMaxime Ripard err_free_ports: 469812bb03b4SMaxime Ripard free_percpu(pp->ports); 46995445eaf3SArnaud Patard \(Rtp\) err_clk: 470015cc4a4aSJisheng Zhang clk_disable_unprepare(pp->clk_bus); 47015445eaf3SArnaud Patard \(Rtp\) clk_disable_unprepare(pp->clk); 4702503f9aa9SRussell King err_free_phylink: 4703503f9aa9SRussell King if (pp->phylink) 4704503f9aa9SRussell King phylink_destroy(pp->phylink); 4705c5aff182SThomas Petazzoni err_free_irq: 4706c5aff182SThomas Petazzoni irq_dispose_mapping(dev->irq); 4707c5aff182SThomas Petazzoni return err; 4708c5aff182SThomas Petazzoni } 4709c5aff182SThomas Petazzoni 4710c5aff182SThomas Petazzoni /* Device removal routine */ 471103ce758eSGreg KH static int mvneta_remove(struct platform_device *pdev) 4712c5aff182SThomas Petazzoni { 4713c5aff182SThomas Petazzoni struct net_device *dev = platform_get_drvdata(pdev); 4714c5aff182SThomas Petazzoni struct mvneta_port *pp = netdev_priv(dev); 4715c5aff182SThomas Petazzoni 4716c5aff182SThomas Petazzoni unregister_netdev(dev); 471715cc4a4aSJisheng Zhang clk_disable_unprepare(pp->clk_bus); 4718189dd626SThomas Petazzoni clk_disable_unprepare(pp->clk); 471912bb03b4SMaxime Ripard free_percpu(pp->ports); 472074c41b04Swilly tarreau free_percpu(pp->stats); 4721c5aff182SThomas Petazzoni irq_dispose_mapping(dev->irq); 4722503f9aa9SRussell King phylink_destroy(pp->phylink); 4723c5aff182SThomas Petazzoni 4724dc35a10fSMarcin Wojtas if (pp->bm_priv) { 4725dc35a10fSMarcin Wojtas mvneta_bm_pool_destroy(pp->bm_priv, pp->pool_long, 1 << pp->id); 4726dc35a10fSMarcin Wojtas mvneta_bm_pool_destroy(pp->bm_priv, pp->pool_short, 4727dc35a10fSMarcin Wojtas 1 << pp->id); 4728965cbbecSGregory CLEMENT mvneta_bm_put(pp->bm_priv); 4729dc35a10fSMarcin Wojtas } 4730dc35a10fSMarcin Wojtas 4731c5aff182SThomas Petazzoni return 0; 4732c5aff182SThomas Petazzoni } 4733c5aff182SThomas Petazzoni 47349768b45cSJane Li #ifdef CONFIG_PM_SLEEP 47359768b45cSJane Li static int mvneta_suspend(struct device *device) 47369768b45cSJane Li { 47371799cdd2SJisheng Zhang int queue; 47389768b45cSJane Li struct net_device *dev = dev_get_drvdata(device); 47399768b45cSJane Li struct mvneta_port *pp = netdev_priv(dev); 47409768b45cSJane Li 47411799cdd2SJisheng Zhang if (!netif_running(dev)) 47421799cdd2SJisheng Zhang goto clean_exit; 47431799cdd2SJisheng Zhang 47441799cdd2SJisheng Zhang if (!pp->neta_armada3700) { 47451799cdd2SJisheng Zhang spin_lock(&pp->lock); 47461799cdd2SJisheng Zhang pp->is_stopped = true; 47471799cdd2SJisheng Zhang spin_unlock(&pp->lock); 47481799cdd2SJisheng Zhang 47491799cdd2SJisheng Zhang cpuhp_state_remove_instance_nocalls(online_hpstate, 47501799cdd2SJisheng Zhang &pp->node_online); 47511799cdd2SJisheng Zhang cpuhp_state_remove_instance_nocalls(CPUHP_NET_MVNETA_DEAD, 47521799cdd2SJisheng Zhang &pp->node_dead); 47531799cdd2SJisheng Zhang } 47541799cdd2SJisheng Zhang 47553b8bc674SRussell King rtnl_lock(); 47561799cdd2SJisheng Zhang mvneta_stop_dev(pp); 47573b8bc674SRussell King rtnl_unlock(); 47581799cdd2SJisheng Zhang 47591799cdd2SJisheng Zhang for (queue = 0; queue < rxq_number; queue++) { 47601799cdd2SJisheng Zhang struct mvneta_rx_queue *rxq = &pp->rxqs[queue]; 47611799cdd2SJisheng Zhang 47621799cdd2SJisheng Zhang mvneta_rxq_drop_pkts(pp, rxq); 47631799cdd2SJisheng Zhang } 47641799cdd2SJisheng Zhang 47651799cdd2SJisheng Zhang for (queue = 0; queue < txq_number; queue++) { 47661799cdd2SJisheng Zhang struct mvneta_tx_queue *txq = &pp->txqs[queue]; 47671799cdd2SJisheng Zhang 47681799cdd2SJisheng Zhang mvneta_txq_hw_deinit(pp, txq); 47691799cdd2SJisheng Zhang } 47701799cdd2SJisheng Zhang 47711799cdd2SJisheng Zhang clean_exit: 47729768b45cSJane Li netif_device_detach(dev); 47739768b45cSJane Li clk_disable_unprepare(pp->clk_bus); 47749768b45cSJane Li clk_disable_unprepare(pp->clk); 47751799cdd2SJisheng Zhang 47769768b45cSJane Li return 0; 47779768b45cSJane Li } 47789768b45cSJane Li 47799768b45cSJane Li static int mvneta_resume(struct device *device) 47809768b45cSJane Li { 47819768b45cSJane Li struct platform_device *pdev = to_platform_device(device); 47829768b45cSJane Li struct net_device *dev = dev_get_drvdata(device); 47839768b45cSJane Li struct mvneta_port *pp = netdev_priv(dev); 47841799cdd2SJisheng Zhang int err, queue; 47859768b45cSJane Li 47869768b45cSJane Li clk_prepare_enable(pp->clk); 47879768b45cSJane Li if (!IS_ERR(pp->clk_bus)) 47889768b45cSJane Li clk_prepare_enable(pp->clk_bus); 47899768b45cSJane Li if (pp->dram_target_info || pp->neta_armada3700) 47909768b45cSJane Li mvneta_conf_mbus_windows(pp, pp->dram_target_info); 47919768b45cSJane Li if (pp->bm_priv) { 47929768b45cSJane Li err = mvneta_bm_port_init(pdev, pp); 47939768b45cSJane Li if (err < 0) { 47949768b45cSJane Li dev_info(&pdev->dev, "use SW buffer management\n"); 47959768b45cSJane Li pp->bm_priv = NULL; 47969768b45cSJane Li } 47979768b45cSJane Li } 47989768b45cSJane Li mvneta_defaults_set(pp); 47999768b45cSJane Li err = mvneta_port_power_up(pp, pp->phy_interface); 48009768b45cSJane Li if (err < 0) { 48019768b45cSJane Li dev_err(device, "can't power up port\n"); 48029768b45cSJane Li return err; 48039768b45cSJane Li } 48049768b45cSJane Li 48059768b45cSJane Li netif_device_attach(dev); 48061799cdd2SJisheng Zhang 48071799cdd2SJisheng Zhang if (!netif_running(dev)) 48081799cdd2SJisheng Zhang return 0; 48091799cdd2SJisheng Zhang 48101799cdd2SJisheng Zhang for (queue = 0; queue < rxq_number; queue++) { 48111799cdd2SJisheng Zhang struct mvneta_rx_queue *rxq = &pp->rxqs[queue]; 48121799cdd2SJisheng Zhang 48131799cdd2SJisheng Zhang rxq->next_desc_to_proc = 0; 48141799cdd2SJisheng Zhang mvneta_rxq_hw_init(pp, rxq); 4815d6956ac8SJisheng Zhang } 48161799cdd2SJisheng Zhang 48171799cdd2SJisheng Zhang for (queue = 0; queue < txq_number; queue++) { 48181799cdd2SJisheng Zhang struct mvneta_tx_queue *txq = &pp->txqs[queue]; 48191799cdd2SJisheng Zhang 48201799cdd2SJisheng Zhang txq->next_desc_to_proc = 0; 48211799cdd2SJisheng Zhang mvneta_txq_hw_init(pp, txq); 48221799cdd2SJisheng Zhang } 48231799cdd2SJisheng Zhang 48241799cdd2SJisheng Zhang if (!pp->neta_armada3700) { 48251799cdd2SJisheng Zhang spin_lock(&pp->lock); 48261799cdd2SJisheng Zhang pp->is_stopped = false; 48271799cdd2SJisheng Zhang spin_unlock(&pp->lock); 48281799cdd2SJisheng Zhang cpuhp_state_add_instance_nocalls(online_hpstate, 48291799cdd2SJisheng Zhang &pp->node_online); 48301799cdd2SJisheng Zhang cpuhp_state_add_instance_nocalls(CPUHP_NET_MVNETA_DEAD, 48311799cdd2SJisheng Zhang &pp->node_dead); 48321799cdd2SJisheng Zhang } 48331799cdd2SJisheng Zhang 48341799cdd2SJisheng Zhang rtnl_lock(); 48351799cdd2SJisheng Zhang mvneta_start_dev(pp); 48363b8bc674SRussell King rtnl_unlock(); 48371799cdd2SJisheng Zhang mvneta_set_rx_mode(dev); 4838d6956ac8SJisheng Zhang 48399768b45cSJane Li return 0; 48409768b45cSJane Li } 48419768b45cSJane Li #endif 48429768b45cSJane Li 48439768b45cSJane Li static SIMPLE_DEV_PM_OPS(mvneta_pm_ops, mvneta_suspend, mvneta_resume); 48449768b45cSJane Li 4845c5aff182SThomas Petazzoni static const struct of_device_id mvneta_match[] = { 4846c5aff182SThomas Petazzoni { .compatible = "marvell,armada-370-neta" }, 4847f522a975SSimon Guinot { .compatible = "marvell,armada-xp-neta" }, 48482636ac3cSMarcin Wojtas { .compatible = "marvell,armada-3700-neta" }, 4849c5aff182SThomas Petazzoni { } 4850c5aff182SThomas Petazzoni }; 4851c5aff182SThomas Petazzoni MODULE_DEVICE_TABLE(of, mvneta_match); 4852c5aff182SThomas Petazzoni 4853c5aff182SThomas Petazzoni static struct platform_driver mvneta_driver = { 4854c5aff182SThomas Petazzoni .probe = mvneta_probe, 485503ce758eSGreg KH .remove = mvneta_remove, 4856c5aff182SThomas Petazzoni .driver = { 4857c5aff182SThomas Petazzoni .name = MVNETA_DRIVER_NAME, 4858c5aff182SThomas Petazzoni .of_match_table = mvneta_match, 48599768b45cSJane Li .pm = &mvneta_pm_ops, 4860c5aff182SThomas Petazzoni }, 4861c5aff182SThomas Petazzoni }; 4862c5aff182SThomas Petazzoni 486384a3f4dbSSebastian Andrzej Siewior static int __init mvneta_driver_init(void) 486484a3f4dbSSebastian Andrzej Siewior { 486584a3f4dbSSebastian Andrzej Siewior int ret; 486684a3f4dbSSebastian Andrzej Siewior 486784a3f4dbSSebastian Andrzej Siewior ret = cpuhp_setup_state_multi(CPUHP_AP_ONLINE_DYN, "net/mvmeta:online", 486884a3f4dbSSebastian Andrzej Siewior mvneta_cpu_online, 486984a3f4dbSSebastian Andrzej Siewior mvneta_cpu_down_prepare); 487084a3f4dbSSebastian Andrzej Siewior if (ret < 0) 487184a3f4dbSSebastian Andrzej Siewior goto out; 487284a3f4dbSSebastian Andrzej Siewior online_hpstate = ret; 487384a3f4dbSSebastian Andrzej Siewior ret = cpuhp_setup_state_multi(CPUHP_NET_MVNETA_DEAD, "net/mvneta:dead", 487484a3f4dbSSebastian Andrzej Siewior NULL, mvneta_cpu_dead); 487584a3f4dbSSebastian Andrzej Siewior if (ret) 487684a3f4dbSSebastian Andrzej Siewior goto err_dead; 487784a3f4dbSSebastian Andrzej Siewior 487884a3f4dbSSebastian Andrzej Siewior ret = platform_driver_register(&mvneta_driver); 487984a3f4dbSSebastian Andrzej Siewior if (ret) 488084a3f4dbSSebastian Andrzej Siewior goto err; 488184a3f4dbSSebastian Andrzej Siewior return 0; 488284a3f4dbSSebastian Andrzej Siewior 488384a3f4dbSSebastian Andrzej Siewior err: 488484a3f4dbSSebastian Andrzej Siewior cpuhp_remove_multi_state(CPUHP_NET_MVNETA_DEAD); 488584a3f4dbSSebastian Andrzej Siewior err_dead: 488684a3f4dbSSebastian Andrzej Siewior cpuhp_remove_multi_state(online_hpstate); 488784a3f4dbSSebastian Andrzej Siewior out: 488884a3f4dbSSebastian Andrzej Siewior return ret; 488984a3f4dbSSebastian Andrzej Siewior } 489084a3f4dbSSebastian Andrzej Siewior module_init(mvneta_driver_init); 489184a3f4dbSSebastian Andrzej Siewior 489284a3f4dbSSebastian Andrzej Siewior static void __exit mvneta_driver_exit(void) 489384a3f4dbSSebastian Andrzej Siewior { 489484a3f4dbSSebastian Andrzej Siewior platform_driver_unregister(&mvneta_driver); 489584a3f4dbSSebastian Andrzej Siewior cpuhp_remove_multi_state(CPUHP_NET_MVNETA_DEAD); 489684a3f4dbSSebastian Andrzej Siewior cpuhp_remove_multi_state(online_hpstate); 489784a3f4dbSSebastian Andrzej Siewior } 489884a3f4dbSSebastian Andrzej Siewior module_exit(mvneta_driver_exit); 4899c5aff182SThomas Petazzoni 4900c5aff182SThomas Petazzoni MODULE_DESCRIPTION("Marvell NETA Ethernet Driver - www.marvell.com"); 4901c5aff182SThomas Petazzoni MODULE_AUTHOR("Rami Rosen <rosenr@marvell.com>, Thomas Petazzoni <thomas.petazzoni@free-electrons.com>"); 4902c5aff182SThomas Petazzoni MODULE_LICENSE("GPL"); 4903c5aff182SThomas Petazzoni 4904d3757ba4SJoe Perches module_param(rxq_number, int, 0444); 4905d3757ba4SJoe Perches module_param(txq_number, int, 0444); 4906c5aff182SThomas Petazzoni 4907d3757ba4SJoe Perches module_param(rxq_def, int, 0444); 4908d3757ba4SJoe Perches module_param(rx_copybreak, int, 0644); 4909