1c5aff182SThomas Petazzoni /* 2c5aff182SThomas Petazzoni * Driver for Marvell NETA network card for Armada XP and Armada 370 SoCs. 3c5aff182SThomas Petazzoni * 4c5aff182SThomas Petazzoni * Copyright (C) 2012 Marvell 5c5aff182SThomas Petazzoni * 6c5aff182SThomas Petazzoni * Rami Rosen <rosenr@marvell.com> 7c5aff182SThomas Petazzoni * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> 8c5aff182SThomas Petazzoni * 9c5aff182SThomas Petazzoni * This file is licensed under the terms of the GNU General Public 10c5aff182SThomas Petazzoni * License version 2. This program is licensed "as is" without any 11c5aff182SThomas Petazzoni * warranty of any kind, whether express or implied. 12c5aff182SThomas Petazzoni */ 13c5aff182SThomas Petazzoni 140e03f563SJisheng Zhang #include <linux/clk.h> 150e03f563SJisheng Zhang #include <linux/cpu.h> 16c5aff182SThomas Petazzoni #include <linux/etherdevice.h> 170e03f563SJisheng Zhang #include <linux/if_vlan.h> 18c5aff182SThomas Petazzoni #include <linux/inetdevice.h> 190e03f563SJisheng Zhang #include <linux/interrupt.h> 200e03f563SJisheng Zhang #include <linux/io.h> 210e03f563SJisheng Zhang #include <linux/kernel.h> 22c5aff182SThomas Petazzoni #include <linux/mbus.h> 23c5aff182SThomas Petazzoni #include <linux/module.h> 240e03f563SJisheng Zhang #include <linux/netdevice.h> 25c5aff182SThomas Petazzoni #include <linux/of.h> 260e03f563SJisheng Zhang #include <linux/of_address.h> 27c5aff182SThomas Petazzoni #include <linux/of_irq.h> 28c5aff182SThomas Petazzoni #include <linux/of_mdio.h> 29c5aff182SThomas Petazzoni #include <linux/of_net.h> 30a10c1c81SRussell King #include <linux/phy/phy.h> 31c5aff182SThomas Petazzoni #include <linux/phy.h> 32503f9aa9SRussell King #include <linux/phylink.h> 330e03f563SJisheng Zhang #include <linux/platform_device.h> 340e03f563SJisheng Zhang #include <linux/skbuff.h> 35baa11ebcSGregory CLEMENT #include <net/hwbm.h> 36dc35a10fSMarcin Wojtas #include "mvneta_bm.h" 370e03f563SJisheng Zhang #include <net/ip.h> 380e03f563SJisheng Zhang #include <net/ipv6.h> 390e03f563SJisheng Zhang #include <net/tso.h> 40568a3fa2SLorenzo Bianconi #include <net/page_pool.h> 410db51da7SLorenzo Bianconi #include <linux/bpf_trace.h> 42c5aff182SThomas Petazzoni 43c5aff182SThomas Petazzoni /* Registers */ 44c5aff182SThomas Petazzoni #define MVNETA_RXQ_CONFIG_REG(q) (0x1400 + ((q) << 2)) 45e5bdf689SMarcin Wojtas #define MVNETA_RXQ_HW_BUF_ALLOC BIT(0) 46dc35a10fSMarcin Wojtas #define MVNETA_RXQ_SHORT_POOL_ID_SHIFT 4 47dc35a10fSMarcin Wojtas #define MVNETA_RXQ_SHORT_POOL_ID_MASK 0x30 48dc35a10fSMarcin Wojtas #define MVNETA_RXQ_LONG_POOL_ID_SHIFT 6 49dc35a10fSMarcin Wojtas #define MVNETA_RXQ_LONG_POOL_ID_MASK 0xc0 50c5aff182SThomas Petazzoni #define MVNETA_RXQ_PKT_OFFSET_ALL_MASK (0xf << 8) 51c5aff182SThomas Petazzoni #define MVNETA_RXQ_PKT_OFFSET_MASK(offs) ((offs) << 8) 52c5aff182SThomas Petazzoni #define MVNETA_RXQ_THRESHOLD_REG(q) (0x14c0 + ((q) << 2)) 53c5aff182SThomas Petazzoni #define MVNETA_RXQ_NON_OCCUPIED(v) ((v) << 16) 54c5aff182SThomas Petazzoni #define MVNETA_RXQ_BASE_ADDR_REG(q) (0x1480 + ((q) << 2)) 55c5aff182SThomas Petazzoni #define MVNETA_RXQ_SIZE_REG(q) (0x14a0 + ((q) << 2)) 56c5aff182SThomas Petazzoni #define MVNETA_RXQ_BUF_SIZE_SHIFT 19 57c5aff182SThomas Petazzoni #define MVNETA_RXQ_BUF_SIZE_MASK (0x1fff << 19) 58c5aff182SThomas Petazzoni #define MVNETA_RXQ_STATUS_REG(q) (0x14e0 + ((q) << 2)) 59c5aff182SThomas Petazzoni #define MVNETA_RXQ_OCCUPIED_ALL_MASK 0x3fff 60c5aff182SThomas Petazzoni #define MVNETA_RXQ_STATUS_UPDATE_REG(q) (0x1500 + ((q) << 2)) 61c5aff182SThomas Petazzoni #define MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT 16 62c5aff182SThomas Petazzoni #define MVNETA_RXQ_ADD_NON_OCCUPIED_MAX 255 63dc35a10fSMarcin Wojtas #define MVNETA_PORT_POOL_BUFFER_SZ_REG(pool) (0x1700 + ((pool) << 2)) 64dc35a10fSMarcin Wojtas #define MVNETA_PORT_POOL_BUFFER_SZ_SHIFT 3 65dc35a10fSMarcin Wojtas #define MVNETA_PORT_POOL_BUFFER_SZ_MASK 0xfff8 66c5aff182SThomas Petazzoni #define MVNETA_PORT_RX_RESET 0x1cc0 67c5aff182SThomas Petazzoni #define MVNETA_PORT_RX_DMA_RESET BIT(0) 68c5aff182SThomas Petazzoni #define MVNETA_PHY_ADDR 0x2000 69c5aff182SThomas Petazzoni #define MVNETA_PHY_ADDR_MASK 0x1f 70c5aff182SThomas Petazzoni #define MVNETA_MBUS_RETRY 0x2010 71c5aff182SThomas Petazzoni #define MVNETA_UNIT_INTR_CAUSE 0x2080 72c5aff182SThomas Petazzoni #define MVNETA_UNIT_CONTROL 0x20B0 73c5aff182SThomas Petazzoni #define MVNETA_PHY_POLLING_ENABLE BIT(1) 74c5aff182SThomas Petazzoni #define MVNETA_WIN_BASE(w) (0x2200 + ((w) << 3)) 75c5aff182SThomas Petazzoni #define MVNETA_WIN_SIZE(w) (0x2204 + ((w) << 3)) 76c5aff182SThomas Petazzoni #define MVNETA_WIN_REMAP(w) (0x2280 + ((w) << 2)) 77c5aff182SThomas Petazzoni #define MVNETA_BASE_ADDR_ENABLE 0x2290 78db6ba9a5SMarcin Wojtas #define MVNETA_ACCESS_PROTECT_ENABLE 0x2294 79c5aff182SThomas Petazzoni #define MVNETA_PORT_CONFIG 0x2400 80c5aff182SThomas Petazzoni #define MVNETA_UNI_PROMISC_MODE BIT(0) 81c5aff182SThomas Petazzoni #define MVNETA_DEF_RXQ(q) ((q) << 1) 82c5aff182SThomas Petazzoni #define MVNETA_DEF_RXQ_ARP(q) ((q) << 4) 83c5aff182SThomas Petazzoni #define MVNETA_TX_UNSET_ERR_SUM BIT(12) 84c5aff182SThomas Petazzoni #define MVNETA_DEF_RXQ_TCP(q) ((q) << 16) 85c5aff182SThomas Petazzoni #define MVNETA_DEF_RXQ_UDP(q) ((q) << 19) 86c5aff182SThomas Petazzoni #define MVNETA_DEF_RXQ_BPDU(q) ((q) << 22) 87c5aff182SThomas Petazzoni #define MVNETA_RX_CSUM_WITH_PSEUDO_HDR BIT(25) 88c5aff182SThomas Petazzoni #define MVNETA_PORT_CONFIG_DEFL_VALUE(q) (MVNETA_DEF_RXQ(q) | \ 89c5aff182SThomas Petazzoni MVNETA_DEF_RXQ_ARP(q) | \ 90c5aff182SThomas Petazzoni MVNETA_DEF_RXQ_TCP(q) | \ 91c5aff182SThomas Petazzoni MVNETA_DEF_RXQ_UDP(q) | \ 92c5aff182SThomas Petazzoni MVNETA_DEF_RXQ_BPDU(q) | \ 93c5aff182SThomas Petazzoni MVNETA_TX_UNSET_ERR_SUM | \ 94c5aff182SThomas Petazzoni MVNETA_RX_CSUM_WITH_PSEUDO_HDR) 95c5aff182SThomas Petazzoni #define MVNETA_PORT_CONFIG_EXTEND 0x2404 96c5aff182SThomas Petazzoni #define MVNETA_MAC_ADDR_LOW 0x2414 97c5aff182SThomas Petazzoni #define MVNETA_MAC_ADDR_HIGH 0x2418 98c5aff182SThomas Petazzoni #define MVNETA_SDMA_CONFIG 0x241c 99c5aff182SThomas Petazzoni #define MVNETA_SDMA_BRST_SIZE_16 4 100c5aff182SThomas Petazzoni #define MVNETA_RX_BRST_SZ_MASK(burst) ((burst) << 1) 101c5aff182SThomas Petazzoni #define MVNETA_RX_NO_DATA_SWAP BIT(4) 102c5aff182SThomas Petazzoni #define MVNETA_TX_NO_DATA_SWAP BIT(5) 1039ad8fef6SThomas Petazzoni #define MVNETA_DESC_SWAP BIT(6) 104c5aff182SThomas Petazzoni #define MVNETA_TX_BRST_SZ_MASK(burst) ((burst) << 22) 105c5aff182SThomas Petazzoni #define MVNETA_PORT_STATUS 0x2444 106c5aff182SThomas Petazzoni #define MVNETA_TX_IN_PRGRS BIT(1) 107c5aff182SThomas Petazzoni #define MVNETA_TX_FIFO_EMPTY BIT(8) 108c5aff182SThomas Petazzoni #define MVNETA_RX_MIN_FRAME_SIZE 0x247c 109b4748553SSascha Hauer /* Only exists on Armada XP and Armada 370 */ 1103f1dd4bcSThomas Petazzoni #define MVNETA_SERDES_CFG 0x24A0 1115445eaf3SArnaud Patard \(Rtp\) #define MVNETA_SGMII_SERDES_PROTO 0x0cc7 1123f1dd4bcSThomas Petazzoni #define MVNETA_QSGMII_SERDES_PROTO 0x0667 1131a642ca7SSascha Hauer #define MVNETA_HSGMII_SERDES_PROTO 0x1107 114c5aff182SThomas Petazzoni #define MVNETA_TYPE_PRIO 0x24bc 115c5aff182SThomas Petazzoni #define MVNETA_FORCE_UNI BIT(21) 116c5aff182SThomas Petazzoni #define MVNETA_TXQ_CMD_1 0x24e4 117c5aff182SThomas Petazzoni #define MVNETA_TXQ_CMD 0x2448 118c5aff182SThomas Petazzoni #define MVNETA_TXQ_DISABLE_SHIFT 8 119c5aff182SThomas Petazzoni #define MVNETA_TXQ_ENABLE_MASK 0x000000ff 120e483911fSAndrew Lunn #define MVNETA_RX_DISCARD_FRAME_COUNT 0x2484 121e483911fSAndrew Lunn #define MVNETA_OVERRUN_FRAME_COUNT 0x2488 122898b2970SStas Sergeev #define MVNETA_GMAC_CLOCK_DIVIDER 0x24f4 123898b2970SStas Sergeev #define MVNETA_GMAC_1MS_CLOCK_ENABLE BIT(31) 124c5aff182SThomas Petazzoni #define MVNETA_ACC_MODE 0x2500 125dc35a10fSMarcin Wojtas #define MVNETA_BM_ADDRESS 0x2504 126c5aff182SThomas Petazzoni #define MVNETA_CPU_MAP(cpu) (0x2540 + ((cpu) << 2)) 127c5aff182SThomas Petazzoni #define MVNETA_CPU_RXQ_ACCESS_ALL_MASK 0x000000ff 128c5aff182SThomas Petazzoni #define MVNETA_CPU_TXQ_ACCESS_ALL_MASK 0x0000ff00 1292dcf75e2SGregory CLEMENT #define MVNETA_CPU_RXQ_ACCESS(rxq) BIT(rxq) 13050bf8cb6SGregory CLEMENT #define MVNETA_CPU_TXQ_ACCESS(txq) BIT(txq + 8) 131c5aff182SThomas Petazzoni #define MVNETA_RXQ_TIME_COAL_REG(q) (0x2580 + ((q) << 2)) 13240ba35e7Swilly tarreau 1332dcf75e2SGregory CLEMENT /* Exception Interrupt Port/Queue Cause register 1342dcf75e2SGregory CLEMENT * 1352dcf75e2SGregory CLEMENT * Their behavior depend of the mapping done using the PCPX2Q 1362dcf75e2SGregory CLEMENT * registers. For a given CPU if the bit associated to a queue is not 1372dcf75e2SGregory CLEMENT * set, then for the register a read from this CPU will always return 1382dcf75e2SGregory CLEMENT * 0 and a write won't do anything 1392dcf75e2SGregory CLEMENT */ 14040ba35e7Swilly tarreau 141c5aff182SThomas Petazzoni #define MVNETA_INTR_NEW_CAUSE 0x25a0 142c5aff182SThomas Petazzoni #define MVNETA_INTR_NEW_MASK 0x25a4 14340ba35e7Swilly tarreau 14440ba35e7Swilly tarreau /* bits 0..7 = TXQ SENT, one bit per queue. 14540ba35e7Swilly tarreau * bits 8..15 = RXQ OCCUP, one bit per queue. 14640ba35e7Swilly tarreau * bits 16..23 = RXQ FREE, one bit per queue. 14740ba35e7Swilly tarreau * bit 29 = OLD_REG_SUM, see old reg ? 14840ba35e7Swilly tarreau * bit 30 = TX_ERR_SUM, one bit for 4 ports 14940ba35e7Swilly tarreau * bit 31 = MISC_SUM, one bit for 4 ports 15040ba35e7Swilly tarreau */ 15140ba35e7Swilly tarreau #define MVNETA_TX_INTR_MASK(nr_txqs) (((1 << nr_txqs) - 1) << 0) 15240ba35e7Swilly tarreau #define MVNETA_TX_INTR_MASK_ALL (0xff << 0) 15340ba35e7Swilly tarreau #define MVNETA_RX_INTR_MASK(nr_rxqs) (((1 << nr_rxqs) - 1) << 8) 15440ba35e7Swilly tarreau #define MVNETA_RX_INTR_MASK_ALL (0xff << 8) 155898b2970SStas Sergeev #define MVNETA_MISCINTR_INTR_MASK BIT(31) 15640ba35e7Swilly tarreau 157c5aff182SThomas Petazzoni #define MVNETA_INTR_OLD_CAUSE 0x25a8 158c5aff182SThomas Petazzoni #define MVNETA_INTR_OLD_MASK 0x25ac 15940ba35e7Swilly tarreau 16040ba35e7Swilly tarreau /* Data Path Port/Queue Cause Register */ 161c5aff182SThomas Petazzoni #define MVNETA_INTR_MISC_CAUSE 0x25b0 162c5aff182SThomas Petazzoni #define MVNETA_INTR_MISC_MASK 0x25b4 16340ba35e7Swilly tarreau 16440ba35e7Swilly tarreau #define MVNETA_CAUSE_PHY_STATUS_CHANGE BIT(0) 16540ba35e7Swilly tarreau #define MVNETA_CAUSE_LINK_CHANGE BIT(1) 16640ba35e7Swilly tarreau #define MVNETA_CAUSE_PTP BIT(4) 16740ba35e7Swilly tarreau 16840ba35e7Swilly tarreau #define MVNETA_CAUSE_INTERNAL_ADDR_ERR BIT(7) 16940ba35e7Swilly tarreau #define MVNETA_CAUSE_RX_OVERRUN BIT(8) 17040ba35e7Swilly tarreau #define MVNETA_CAUSE_RX_CRC_ERROR BIT(9) 17140ba35e7Swilly tarreau #define MVNETA_CAUSE_RX_LARGE_PKT BIT(10) 17240ba35e7Swilly tarreau #define MVNETA_CAUSE_TX_UNDERUN BIT(11) 17340ba35e7Swilly tarreau #define MVNETA_CAUSE_PRBS_ERR BIT(12) 17440ba35e7Swilly tarreau #define MVNETA_CAUSE_PSC_SYNC_CHANGE BIT(13) 17540ba35e7Swilly tarreau #define MVNETA_CAUSE_SERDES_SYNC_ERR BIT(14) 17640ba35e7Swilly tarreau 17740ba35e7Swilly tarreau #define MVNETA_CAUSE_BMU_ALLOC_ERR_SHIFT 16 17840ba35e7Swilly tarreau #define MVNETA_CAUSE_BMU_ALLOC_ERR_ALL_MASK (0xF << MVNETA_CAUSE_BMU_ALLOC_ERR_SHIFT) 17940ba35e7Swilly tarreau #define MVNETA_CAUSE_BMU_ALLOC_ERR_MASK(pool) (1 << (MVNETA_CAUSE_BMU_ALLOC_ERR_SHIFT + (pool))) 18040ba35e7Swilly tarreau 18140ba35e7Swilly tarreau #define MVNETA_CAUSE_TXQ_ERROR_SHIFT 24 18240ba35e7Swilly tarreau #define MVNETA_CAUSE_TXQ_ERROR_ALL_MASK (0xFF << MVNETA_CAUSE_TXQ_ERROR_SHIFT) 18340ba35e7Swilly tarreau #define MVNETA_CAUSE_TXQ_ERROR_MASK(q) (1 << (MVNETA_CAUSE_TXQ_ERROR_SHIFT + (q))) 18440ba35e7Swilly tarreau 185c5aff182SThomas Petazzoni #define MVNETA_INTR_ENABLE 0x25b8 186c5aff182SThomas Petazzoni #define MVNETA_TXQ_INTR_ENABLE_ALL_MASK 0x0000ff00 187dc1aadf6SMarcin Wojtas #define MVNETA_RXQ_INTR_ENABLE_ALL_MASK 0x000000ff 18840ba35e7Swilly tarreau 189c5aff182SThomas Petazzoni #define MVNETA_RXQ_CMD 0x2680 190c5aff182SThomas Petazzoni #define MVNETA_RXQ_DISABLE_SHIFT 8 191c5aff182SThomas Petazzoni #define MVNETA_RXQ_ENABLE_MASK 0x000000ff 192c5aff182SThomas Petazzoni #define MVETH_TXQ_TOKEN_COUNT_REG(q) (0x2700 + ((q) << 4)) 193c5aff182SThomas Petazzoni #define MVETH_TXQ_TOKEN_CFG_REG(q) (0x2704 + ((q) << 4)) 194c5aff182SThomas Petazzoni #define MVNETA_GMAC_CTRL_0 0x2c00 195c5aff182SThomas Petazzoni #define MVNETA_GMAC_MAX_RX_SIZE_SHIFT 2 196c5aff182SThomas Petazzoni #define MVNETA_GMAC_MAX_RX_SIZE_MASK 0x7ffc 19722f4bf8aSRussell King #define MVNETA_GMAC0_PORT_1000BASE_X BIT(1) 198c5aff182SThomas Petazzoni #define MVNETA_GMAC0_PORT_ENABLE BIT(0) 199c5aff182SThomas Petazzoni #define MVNETA_GMAC_CTRL_2 0x2c08 200898b2970SStas Sergeev #define MVNETA_GMAC2_INBAND_AN_ENABLE BIT(0) 201a79121d3SThomas Petazzoni #define MVNETA_GMAC2_PCS_ENABLE BIT(3) 202c5aff182SThomas Petazzoni #define MVNETA_GMAC2_PORT_RGMII BIT(4) 203c5aff182SThomas Petazzoni #define MVNETA_GMAC2_PORT_RESET BIT(6) 204c5aff182SThomas Petazzoni #define MVNETA_GMAC_STATUS 0x2c10 205c5aff182SThomas Petazzoni #define MVNETA_GMAC_LINK_UP BIT(0) 206c5aff182SThomas Petazzoni #define MVNETA_GMAC_SPEED_1000 BIT(1) 207c5aff182SThomas Petazzoni #define MVNETA_GMAC_SPEED_100 BIT(2) 208c5aff182SThomas Petazzoni #define MVNETA_GMAC_FULL_DUPLEX BIT(3) 209c5aff182SThomas Petazzoni #define MVNETA_GMAC_RX_FLOW_CTRL_ENABLE BIT(4) 210c5aff182SThomas Petazzoni #define MVNETA_GMAC_TX_FLOW_CTRL_ENABLE BIT(5) 211c5aff182SThomas Petazzoni #define MVNETA_GMAC_RX_FLOW_CTRL_ACTIVE BIT(6) 212c5aff182SThomas Petazzoni #define MVNETA_GMAC_TX_FLOW_CTRL_ACTIVE BIT(7) 213503f9aa9SRussell King #define MVNETA_GMAC_AN_COMPLETE BIT(11) 214503f9aa9SRussell King #define MVNETA_GMAC_SYNC_OK BIT(14) 215c5aff182SThomas Petazzoni #define MVNETA_GMAC_AUTONEG_CONFIG 0x2c0c 216c5aff182SThomas Petazzoni #define MVNETA_GMAC_FORCE_LINK_DOWN BIT(0) 217c5aff182SThomas Petazzoni #define MVNETA_GMAC_FORCE_LINK_PASS BIT(1) 218898b2970SStas Sergeev #define MVNETA_GMAC_INBAND_AN_ENABLE BIT(2) 21922f4bf8aSRussell King #define MVNETA_GMAC_AN_BYPASS_ENABLE BIT(3) 22022f4bf8aSRussell King #define MVNETA_GMAC_INBAND_RESTART_AN BIT(4) 221c5aff182SThomas Petazzoni #define MVNETA_GMAC_CONFIG_MII_SPEED BIT(5) 222c5aff182SThomas Petazzoni #define MVNETA_GMAC_CONFIG_GMII_SPEED BIT(6) 22371408602SThomas Petazzoni #define MVNETA_GMAC_AN_SPEED_EN BIT(7) 22422f4bf8aSRussell King #define MVNETA_GMAC_CONFIG_FLOW_CTRL BIT(8) 22522f4bf8aSRussell King #define MVNETA_GMAC_ADVERT_SYM_FLOW_CTRL BIT(9) 226898b2970SStas Sergeev #define MVNETA_GMAC_AN_FLOW_CTRL_EN BIT(11) 227c5aff182SThomas Petazzoni #define MVNETA_GMAC_CONFIG_FULL_DUPLEX BIT(12) 22871408602SThomas Petazzoni #define MVNETA_GMAC_AN_DUPLEX_EN BIT(13) 229da58a931SMaxime Chevallier #define MVNETA_GMAC_CTRL_4 0x2c90 230da58a931SMaxime Chevallier #define MVNETA_GMAC4_SHORT_PREAMBLE_ENABLE BIT(1) 231e483911fSAndrew Lunn #define MVNETA_MIB_COUNTERS_BASE 0x3000 232c5aff182SThomas Petazzoni #define MVNETA_MIB_LATE_COLLISION 0x7c 233c5aff182SThomas Petazzoni #define MVNETA_DA_FILT_SPEC_MCAST 0x3400 234c5aff182SThomas Petazzoni #define MVNETA_DA_FILT_OTH_MCAST 0x3500 235c5aff182SThomas Petazzoni #define MVNETA_DA_FILT_UCAST_BASE 0x3600 236c5aff182SThomas Petazzoni #define MVNETA_TXQ_BASE_ADDR_REG(q) (0x3c00 + ((q) << 2)) 237c5aff182SThomas Petazzoni #define MVNETA_TXQ_SIZE_REG(q) (0x3c20 + ((q) << 2)) 238c5aff182SThomas Petazzoni #define MVNETA_TXQ_SENT_THRESH_ALL_MASK 0x3fff0000 239c5aff182SThomas Petazzoni #define MVNETA_TXQ_SENT_THRESH_MASK(coal) ((coal) << 16) 240c5aff182SThomas Petazzoni #define MVNETA_TXQ_UPDATE_REG(q) (0x3c60 + ((q) << 2)) 241c5aff182SThomas Petazzoni #define MVNETA_TXQ_DEC_SENT_SHIFT 16 2422a90f7e1SSimon Guinot #define MVNETA_TXQ_DEC_SENT_MASK 0xff 243c5aff182SThomas Petazzoni #define MVNETA_TXQ_STATUS_REG(q) (0x3c40 + ((q) << 2)) 244c5aff182SThomas Petazzoni #define MVNETA_TXQ_SENT_DESC_SHIFT 16 245c5aff182SThomas Petazzoni #define MVNETA_TXQ_SENT_DESC_MASK 0x3fff0000 246c5aff182SThomas Petazzoni #define MVNETA_PORT_TX_RESET 0x3cf0 247c5aff182SThomas Petazzoni #define MVNETA_PORT_TX_DMA_RESET BIT(0) 248c5aff182SThomas Petazzoni #define MVNETA_TX_MTU 0x3e0c 249c5aff182SThomas Petazzoni #define MVNETA_TX_TOKEN_SIZE 0x3e14 250c5aff182SThomas Petazzoni #define MVNETA_TX_TOKEN_SIZE_MAX 0xffffffff 251c5aff182SThomas Petazzoni #define MVNETA_TXQ_TOKEN_SIZE_REG(q) (0x3e40 + ((q) << 2)) 252c5aff182SThomas Petazzoni #define MVNETA_TXQ_TOKEN_SIZE_MAX 0x7fffffff 253c5aff182SThomas Petazzoni 2546d81f451SRussell King #define MVNETA_LPI_CTRL_0 0x2cc0 2556d81f451SRussell King #define MVNETA_LPI_CTRL_1 0x2cc4 2566d81f451SRussell King #define MVNETA_LPI_REQUEST_ENABLE BIT(0) 2576d81f451SRussell King #define MVNETA_LPI_CTRL_2 0x2cc8 2586d81f451SRussell King #define MVNETA_LPI_STATUS 0x2ccc 2596d81f451SRussell King 260c5aff182SThomas Petazzoni #define MVNETA_CAUSE_TXQ_SENT_DESC_ALL_MASK 0xff 261c5aff182SThomas Petazzoni 262c5aff182SThomas Petazzoni /* Descriptor ring Macros */ 263c5aff182SThomas Petazzoni #define MVNETA_QUEUE_NEXT_DESC(q, index) \ 264c5aff182SThomas Petazzoni (((index) < (q)->last_desc) ? ((index) + 1) : 0) 265c5aff182SThomas Petazzoni 266c5aff182SThomas Petazzoni /* Various constants */ 267c5aff182SThomas Petazzoni 268c5aff182SThomas Petazzoni /* Coalescing */ 26906708f81SDmitri Epshtein #define MVNETA_TXDONE_COAL_PKTS 0 /* interrupt per packet */ 270c5aff182SThomas Petazzoni #define MVNETA_RX_COAL_PKTS 32 271c5aff182SThomas Petazzoni #define MVNETA_RX_COAL_USEC 100 272c5aff182SThomas Petazzoni 2736a20c175SThomas Petazzoni /* The two bytes Marvell header. Either contains a special value used 274c5aff182SThomas Petazzoni * by Marvell switches when a specific hardware mode is enabled (not 275c5aff182SThomas Petazzoni * supported by this driver) or is filled automatically by zeroes on 276c5aff182SThomas Petazzoni * the RX side. Those two bytes being at the front of the Ethernet 277c5aff182SThomas Petazzoni * header, they allow to have the IP header aligned on a 4 bytes 278c5aff182SThomas Petazzoni * boundary automatically: the hardware skips those two bytes on its 279c5aff182SThomas Petazzoni * own. 280c5aff182SThomas Petazzoni */ 281c5aff182SThomas Petazzoni #define MVNETA_MH_SIZE 2 282c5aff182SThomas Petazzoni 283c5aff182SThomas Petazzoni #define MVNETA_VLAN_TAG_LEN 4 284c5aff182SThomas Petazzoni 2859110ee07SMarcin Wojtas #define MVNETA_TX_CSUM_DEF_SIZE 1600 286c5aff182SThomas Petazzoni #define MVNETA_TX_CSUM_MAX_SIZE 9800 287dc35a10fSMarcin Wojtas #define MVNETA_ACC_MODE_EXT1 1 288dc35a10fSMarcin Wojtas #define MVNETA_ACC_MODE_EXT2 2 289dc35a10fSMarcin Wojtas 290dc35a10fSMarcin Wojtas #define MVNETA_MAX_DECODE_WIN 6 291c5aff182SThomas Petazzoni 292c5aff182SThomas Petazzoni /* Timeout constants */ 293c5aff182SThomas Petazzoni #define MVNETA_TX_DISABLE_TIMEOUT_MSEC 1000 294c5aff182SThomas Petazzoni #define MVNETA_RX_DISABLE_TIMEOUT_MSEC 1000 295c5aff182SThomas Petazzoni #define MVNETA_TX_FIFO_EMPTY_TIMEOUT 10000 296c5aff182SThomas Petazzoni 297c5aff182SThomas Petazzoni #define MVNETA_TX_MTU_MAX 0x3ffff 298c5aff182SThomas Petazzoni 2999a401deaSGregory CLEMENT /* The RSS lookup table actually has 256 entries but we do not use 3009a401deaSGregory CLEMENT * them yet 3019a401deaSGregory CLEMENT */ 3029a401deaSGregory CLEMENT #define MVNETA_RSS_LU_TABLE_SIZE 1 3039a401deaSGregory CLEMENT 304c5aff182SThomas Petazzoni /* Max number of Rx descriptors */ 305c307e2a8SYelena Krivosheev #define MVNETA_MAX_RXD 512 306c5aff182SThomas Petazzoni 307c5aff182SThomas Petazzoni /* Max number of Tx descriptors */ 308c307e2a8SYelena Krivosheev #define MVNETA_MAX_TXD 1024 309c5aff182SThomas Petazzoni 3108eef5f97SEzequiel Garcia /* Max number of allowed TCP segments for software TSO */ 3118eef5f97SEzequiel Garcia #define MVNETA_MAX_TSO_SEGS 100 3128eef5f97SEzequiel Garcia 3138eef5f97SEzequiel Garcia #define MVNETA_MAX_SKB_DESCS (MVNETA_MAX_TSO_SEGS * 2 + MAX_SKB_FRAGS) 3148eef5f97SEzequiel Garcia 315c5aff182SThomas Petazzoni /* descriptor aligned size */ 316c5aff182SThomas Petazzoni #define MVNETA_DESC_ALIGNED_SIZE 32 317c5aff182SThomas Petazzoni 3188d5047cfSMarcin Wojtas /* Number of bytes to be taken into account by HW when putting incoming data 3198d5047cfSMarcin Wojtas * to the buffers. It is needed in case NET_SKB_PAD exceeds maximum packet 3208d5047cfSMarcin Wojtas * offset supported in MVNETA_RXQ_CONFIG_REG(q) registers. 3218d5047cfSMarcin Wojtas */ 3228d5047cfSMarcin Wojtas #define MVNETA_RX_PKT_OFFSET_CORRECTION 64 3238d5047cfSMarcin Wojtas 324c5aff182SThomas Petazzoni #define MVNETA_RX_PKT_SIZE(mtu) \ 325c5aff182SThomas Petazzoni ALIGN((mtu) + MVNETA_MH_SIZE + MVNETA_VLAN_TAG_LEN + \ 326c5aff182SThomas Petazzoni ETH_HLEN + ETH_FCS_LEN, \ 327c66e98c9SJisheng Zhang cache_line_size()) 328c5aff182SThomas Petazzoni 329ca23cb0bSSven Auhagen /* Driver assumes that the last 3 bits are 0 */ 330e2243720SAlexander Lobakin #define MVNETA_SKB_HEADROOM ALIGN(max(NET_SKB_PAD, XDP_PACKET_HEADROOM), 8) 3318dc9a088SLorenzo Bianconi #define MVNETA_SKB_PAD (SKB_DATA_ALIGN(sizeof(struct skb_shared_info) + \ 3320db51da7SLorenzo Bianconi MVNETA_SKB_HEADROOM)) 3338dc9a088SLorenzo Bianconi #define MVNETA_MAX_RX_BUF_SIZE (PAGE_SIZE - MVNETA_SKB_PAD) 3348dc9a088SLorenzo Bianconi 3352e3173a3SEzequiel Garcia #define IS_TSO_HEADER(txq, addr) \ 3362e3173a3SEzequiel Garcia ((addr >= txq->tso_hdrs_phys) && \ 3372e3173a3SEzequiel Garcia (addr < txq->tso_hdrs_phys + txq->size * TSO_HEADER_SIZE)) 3382e3173a3SEzequiel Garcia 339dc35a10fSMarcin Wojtas #define MVNETA_RX_GET_BM_POOL_ID(rxd) \ 340dc35a10fSMarcin Wojtas (((rxd)->status & MVNETA_RXD_BM_POOL_MASK) >> MVNETA_RXD_BM_POOL_SHIFT) 341c5aff182SThomas Petazzoni 3426d81f451SRussell King enum { 3436d81f451SRussell King ETHTOOL_STAT_EEE_WAKEUP, 34417a96da6SGregory CLEMENT ETHTOOL_STAT_SKB_ALLOC_ERR, 34517a96da6SGregory CLEMENT ETHTOOL_STAT_REFILL_ERR, 3463d866523SLorenzo Bianconi ETHTOOL_XDP_REDIRECT, 3473d866523SLorenzo Bianconi ETHTOOL_XDP_PASS, 3483d866523SLorenzo Bianconi ETHTOOL_XDP_DROP, 3493d866523SLorenzo Bianconi ETHTOOL_XDP_TX, 35015070919SJesper Dangaard Brouer ETHTOOL_XDP_TX_ERR, 35115070919SJesper Dangaard Brouer ETHTOOL_XDP_XMIT, 35215070919SJesper Dangaard Brouer ETHTOOL_XDP_XMIT_ERR, 3536d81f451SRussell King ETHTOOL_MAX_STATS, 3546d81f451SRussell King }; 3556d81f451SRussell King 3569b0cdefaSRussell King struct mvneta_statistic { 3579b0cdefaSRussell King unsigned short offset; 3589b0cdefaSRussell King unsigned short type; 3599b0cdefaSRussell King const char name[ETH_GSTRING_LEN]; 3609b0cdefaSRussell King }; 3619b0cdefaSRussell King 3629b0cdefaSRussell King #define T_REG_32 32 3639b0cdefaSRussell King #define T_REG_64 64 3646d81f451SRussell King #define T_SW 1 3659b0cdefaSRussell King 3666c8a8cfdSLorenzo Bianconi #define MVNETA_XDP_PASS 0 3676c8a8cfdSLorenzo Bianconi #define MVNETA_XDP_DROPPED BIT(0) 3686c8a8cfdSLorenzo Bianconi #define MVNETA_XDP_TX BIT(1) 3696c8a8cfdSLorenzo Bianconi #define MVNETA_XDP_REDIR BIT(2) 3700db51da7SLorenzo Bianconi 3719b0cdefaSRussell King static const struct mvneta_statistic mvneta_statistics[] = { 3729b0cdefaSRussell King { 0x3000, T_REG_64, "good_octets_received", }, 3739b0cdefaSRussell King { 0x3010, T_REG_32, "good_frames_received", }, 3749b0cdefaSRussell King { 0x3008, T_REG_32, "bad_octets_received", }, 3759b0cdefaSRussell King { 0x3014, T_REG_32, "bad_frames_received", }, 3769b0cdefaSRussell King { 0x3018, T_REG_32, "broadcast_frames_received", }, 3779b0cdefaSRussell King { 0x301c, T_REG_32, "multicast_frames_received", }, 3789b0cdefaSRussell King { 0x3050, T_REG_32, "unrec_mac_control_received", }, 3799b0cdefaSRussell King { 0x3058, T_REG_32, "good_fc_received", }, 3809b0cdefaSRussell King { 0x305c, T_REG_32, "bad_fc_received", }, 3819b0cdefaSRussell King { 0x3060, T_REG_32, "undersize_received", }, 3829b0cdefaSRussell King { 0x3064, T_REG_32, "fragments_received", }, 3839b0cdefaSRussell King { 0x3068, T_REG_32, "oversize_received", }, 3849b0cdefaSRussell King { 0x306c, T_REG_32, "jabber_received", }, 3859b0cdefaSRussell King { 0x3070, T_REG_32, "mac_receive_error", }, 3869b0cdefaSRussell King { 0x3074, T_REG_32, "bad_crc_event", }, 3879b0cdefaSRussell King { 0x3078, T_REG_32, "collision", }, 3889b0cdefaSRussell King { 0x307c, T_REG_32, "late_collision", }, 3899b0cdefaSRussell King { 0x2484, T_REG_32, "rx_discard", }, 3909b0cdefaSRussell King { 0x2488, T_REG_32, "rx_overrun", }, 3919b0cdefaSRussell King { 0x3020, T_REG_32, "frames_64_octets", }, 3929b0cdefaSRussell King { 0x3024, T_REG_32, "frames_65_to_127_octets", }, 3939b0cdefaSRussell King { 0x3028, T_REG_32, "frames_128_to_255_octets", }, 3949b0cdefaSRussell King { 0x302c, T_REG_32, "frames_256_to_511_octets", }, 3959b0cdefaSRussell King { 0x3030, T_REG_32, "frames_512_to_1023_octets", }, 3969b0cdefaSRussell King { 0x3034, T_REG_32, "frames_1024_to_max_octets", }, 3979b0cdefaSRussell King { 0x3038, T_REG_64, "good_octets_sent", }, 3989b0cdefaSRussell King { 0x3040, T_REG_32, "good_frames_sent", }, 3999b0cdefaSRussell King { 0x3044, T_REG_32, "excessive_collision", }, 4009b0cdefaSRussell King { 0x3048, T_REG_32, "multicast_frames_sent", }, 4019b0cdefaSRussell King { 0x304c, T_REG_32, "broadcast_frames_sent", }, 4029b0cdefaSRussell King { 0x3054, T_REG_32, "fc_sent", }, 4039b0cdefaSRussell King { 0x300c, T_REG_32, "internal_mac_transmit_err", }, 4046d81f451SRussell King { ETHTOOL_STAT_EEE_WAKEUP, T_SW, "eee_wakeup_errors", }, 40517a96da6SGregory CLEMENT { ETHTOOL_STAT_SKB_ALLOC_ERR, T_SW, "skb_alloc_errors", }, 40617a96da6SGregory CLEMENT { ETHTOOL_STAT_REFILL_ERR, T_SW, "refill_errors", }, 4077d51a015SLorenzo Bianconi { ETHTOOL_XDP_REDIRECT, T_SW, "rx_xdp_redirect", }, 4087d51a015SLorenzo Bianconi { ETHTOOL_XDP_PASS, T_SW, "rx_xdp_pass", }, 4097d51a015SLorenzo Bianconi { ETHTOOL_XDP_DROP, T_SW, "rx_xdp_drop", }, 4107d51a015SLorenzo Bianconi { ETHTOOL_XDP_TX, T_SW, "rx_xdp_tx", }, 41115070919SJesper Dangaard Brouer { ETHTOOL_XDP_TX_ERR, T_SW, "rx_xdp_tx_errors", }, 4127d51a015SLorenzo Bianconi { ETHTOOL_XDP_XMIT, T_SW, "tx_xdp_xmit", }, 41315070919SJesper Dangaard Brouer { ETHTOOL_XDP_XMIT_ERR, T_SW, "tx_xdp_xmit_errors", }, 4149b0cdefaSRussell King }; 4159b0cdefaSRussell King 416320d5441SLorenzo Bianconi struct mvneta_stats { 417320d5441SLorenzo Bianconi u64 rx_packets; 418320d5441SLorenzo Bianconi u64 rx_bytes; 419320d5441SLorenzo Bianconi u64 tx_packets; 420320d5441SLorenzo Bianconi u64 tx_bytes; 4213d866523SLorenzo Bianconi /* xdp */ 4223d866523SLorenzo Bianconi u64 xdp_redirect; 4233d866523SLorenzo Bianconi u64 xdp_pass; 4243d866523SLorenzo Bianconi u64 xdp_drop; 4257d51a015SLorenzo Bianconi u64 xdp_xmit; 42615070919SJesper Dangaard Brouer u64 xdp_xmit_err; 4273d866523SLorenzo Bianconi u64 xdp_tx; 42815070919SJesper Dangaard Brouer u64 xdp_tx_err; 429320d5441SLorenzo Bianconi }; 430320d5441SLorenzo Bianconi 4319ac41f3cSLorenzo Bianconi struct mvneta_ethtool_stats { 432320d5441SLorenzo Bianconi struct mvneta_stats ps; 4339ac41f3cSLorenzo Bianconi u64 skb_alloc_error; 4349ac41f3cSLorenzo Bianconi u64 refill_error; 4359ac41f3cSLorenzo Bianconi }; 4369ac41f3cSLorenzo Bianconi 43774c41b04Swilly tarreau struct mvneta_pcpu_stats { 438c5aff182SThomas Petazzoni struct u64_stats_sync syncp; 4399ac41f3cSLorenzo Bianconi 4409ac41f3cSLorenzo Bianconi struct mvneta_ethtool_stats es; 441c35947b8SLorenzo Bianconi u64 rx_dropped; 442c35947b8SLorenzo Bianconi u64 rx_errors; 443c5aff182SThomas Petazzoni }; 444c5aff182SThomas Petazzoni 44512bb03b4SMaxime Ripard struct mvneta_pcpu_port { 44612bb03b4SMaxime Ripard /* Pointer to the shared port */ 44712bb03b4SMaxime Ripard struct mvneta_port *pp; 44812bb03b4SMaxime Ripard 44912bb03b4SMaxime Ripard /* Pointer to the CPU-local NAPI struct */ 45012bb03b4SMaxime Ripard struct napi_struct napi; 45112bb03b4SMaxime Ripard 45212bb03b4SMaxime Ripard /* Cause of the previous interrupt */ 45312bb03b4SMaxime Ripard u32 cause_rx_tx; 45412bb03b4SMaxime Ripard }; 45512bb03b4SMaxime Ripard 45662a502ccSLorenzo Bianconi enum { 45762a502ccSLorenzo Bianconi __MVNETA_DOWN, 45862a502ccSLorenzo Bianconi }; 45962a502ccSLorenzo Bianconi 460c5aff182SThomas Petazzoni struct mvneta_port { 461dc35a10fSMarcin Wojtas u8 id; 46212bb03b4SMaxime Ripard struct mvneta_pcpu_port __percpu *ports; 46312bb03b4SMaxime Ripard struct mvneta_pcpu_stats __percpu *stats; 46412bb03b4SMaxime Ripard 46562a502ccSLorenzo Bianconi unsigned long state; 46662a502ccSLorenzo Bianconi 467c5aff182SThomas Petazzoni int pkt_size; 468c5aff182SThomas Petazzoni void __iomem *base; 469c5aff182SThomas Petazzoni struct mvneta_rx_queue *rxqs; 470c5aff182SThomas Petazzoni struct mvneta_tx_queue *txqs; 471c5aff182SThomas Petazzoni struct net_device *dev; 47284a3f4dbSSebastian Andrzej Siewior struct hlist_node node_online; 47384a3f4dbSSebastian Andrzej Siewior struct hlist_node node_dead; 47490b74c01SGregory CLEMENT int rxq_def; 4755888511eSGregory CLEMENT /* Protect the access to the percpu interrupt registers, 4765888511eSGregory CLEMENT * ensuring that the configuration remains coherent. 4775888511eSGregory CLEMENT */ 4785888511eSGregory CLEMENT spinlock_t lock; 479120cfa50SGregory CLEMENT bool is_stopped; 480c5aff182SThomas Petazzoni 4812636ac3cSMarcin Wojtas u32 cause_rx_tx; 4822636ac3cSMarcin Wojtas struct napi_struct napi; 4832636ac3cSMarcin Wojtas 4840db51da7SLorenzo Bianconi struct bpf_prog *xdp_prog; 4850db51da7SLorenzo Bianconi 486c5aff182SThomas Petazzoni /* Core clock */ 487189dd626SThomas Petazzoni struct clk *clk; 48815cc4a4aSJisheng Zhang /* AXI clock */ 48915cc4a4aSJisheng Zhang struct clk *clk_bus; 490c5aff182SThomas Petazzoni u8 mcast_count[256]; 491c5aff182SThomas Petazzoni u16 tx_ring_size; 492c5aff182SThomas Petazzoni u16 rx_ring_size; 493c5aff182SThomas Petazzoni 494c5aff182SThomas Petazzoni phy_interface_t phy_interface; 495503f9aa9SRussell King struct device_node *dn; 496b65657fcSSimon Guinot unsigned int tx_csum_limit; 497503f9aa9SRussell King struct phylink *phylink; 49844cc27e4SIoana Ciornei struct phylink_config phylink_config; 499a10c1c81SRussell King struct phy *comphy; 5009b0cdefaSRussell King 501dc35a10fSMarcin Wojtas struct mvneta_bm *bm_priv; 502dc35a10fSMarcin Wojtas struct mvneta_bm_pool *pool_long; 503dc35a10fSMarcin Wojtas struct mvneta_bm_pool *pool_short; 504dc35a10fSMarcin Wojtas int bm_win_id; 505dc35a10fSMarcin Wojtas 5066d81f451SRussell King bool eee_enabled; 5076d81f451SRussell King bool eee_active; 5086d81f451SRussell King bool tx_lpi_enabled; 5096d81f451SRussell King 5109b0cdefaSRussell King u64 ethtool_stats[ARRAY_SIZE(mvneta_statistics)]; 5119a401deaSGregory CLEMENT 5129a401deaSGregory CLEMENT u32 indir[MVNETA_RSS_LU_TABLE_SIZE]; 5132636ac3cSMarcin Wojtas 5142636ac3cSMarcin Wojtas /* Flags for special SoC configurations */ 5152636ac3cSMarcin Wojtas bool neta_armada3700; 5168d5047cfSMarcin Wojtas u16 rx_offset_correction; 5179768b45cSJane Li const struct mbus_dram_target_info *dram_target_info; 518c5aff182SThomas Petazzoni }; 519c5aff182SThomas Petazzoni 5206a20c175SThomas Petazzoni /* The mvneta_tx_desc and mvneta_rx_desc structures describe the 521c5aff182SThomas Petazzoni * layout of the transmit and reception DMA descriptors, and their 522c5aff182SThomas Petazzoni * layout is therefore defined by the hardware design 523c5aff182SThomas Petazzoni */ 5246083ed44SThomas Petazzoni 525c5aff182SThomas Petazzoni #define MVNETA_TX_L3_OFF_SHIFT 0 526c5aff182SThomas Petazzoni #define MVNETA_TX_IP_HLEN_SHIFT 8 527c5aff182SThomas Petazzoni #define MVNETA_TX_L4_UDP BIT(16) 528c5aff182SThomas Petazzoni #define MVNETA_TX_L3_IP6 BIT(17) 529c5aff182SThomas Petazzoni #define MVNETA_TXD_IP_CSUM BIT(18) 530c5aff182SThomas Petazzoni #define MVNETA_TXD_Z_PAD BIT(19) 531c5aff182SThomas Petazzoni #define MVNETA_TXD_L_DESC BIT(20) 532c5aff182SThomas Petazzoni #define MVNETA_TXD_F_DESC BIT(21) 533c5aff182SThomas Petazzoni #define MVNETA_TXD_FLZ_DESC (MVNETA_TXD_Z_PAD | \ 534c5aff182SThomas Petazzoni MVNETA_TXD_L_DESC | \ 535c5aff182SThomas Petazzoni MVNETA_TXD_F_DESC) 536c5aff182SThomas Petazzoni #define MVNETA_TX_L4_CSUM_FULL BIT(30) 537c5aff182SThomas Petazzoni #define MVNETA_TX_L4_CSUM_NOT BIT(31) 538c5aff182SThomas Petazzoni 539c5aff182SThomas Petazzoni #define MVNETA_RXD_ERR_CRC 0x0 540dc35a10fSMarcin Wojtas #define MVNETA_RXD_BM_POOL_SHIFT 13 541dc35a10fSMarcin Wojtas #define MVNETA_RXD_BM_POOL_MASK (BIT(13) | BIT(14)) 542c5aff182SThomas Petazzoni #define MVNETA_RXD_ERR_SUMMARY BIT(16) 543c5aff182SThomas Petazzoni #define MVNETA_RXD_ERR_OVERRUN BIT(17) 544c5aff182SThomas Petazzoni #define MVNETA_RXD_ERR_LEN BIT(18) 545c5aff182SThomas Petazzoni #define MVNETA_RXD_ERR_RESOURCE (BIT(17) | BIT(18)) 546c5aff182SThomas Petazzoni #define MVNETA_RXD_ERR_CODE_MASK (BIT(17) | BIT(18)) 547c5aff182SThomas Petazzoni #define MVNETA_RXD_L3_IP4 BIT(25) 548562e2f46SYelena Krivosheev #define MVNETA_RXD_LAST_DESC BIT(26) 549562e2f46SYelena Krivosheev #define MVNETA_RXD_FIRST_DESC BIT(27) 550562e2f46SYelena Krivosheev #define MVNETA_RXD_FIRST_LAST_DESC (MVNETA_RXD_FIRST_DESC | \ 551562e2f46SYelena Krivosheev MVNETA_RXD_LAST_DESC) 552c5aff182SThomas Petazzoni #define MVNETA_RXD_L4_CSUM_OK BIT(30) 553c5aff182SThomas Petazzoni 5549ad8fef6SThomas Petazzoni #if defined(__LITTLE_ENDIAN) 5556083ed44SThomas Petazzoni struct mvneta_tx_desc { 5566083ed44SThomas Petazzoni u32 command; /* Options used by HW for packet transmitting.*/ 557fbd1d524SAlexandre Belloni u16 reserved1; /* csum_l4 (for future use) */ 5586083ed44SThomas Petazzoni u16 data_size; /* Data size of transmitted packet in bytes */ 5596083ed44SThomas Petazzoni u32 buf_phys_addr; /* Physical addr of transmitted buffer */ 5606083ed44SThomas Petazzoni u32 reserved2; /* hw_cmd - (for future use, PMT) */ 5616083ed44SThomas Petazzoni u32 reserved3[4]; /* Reserved - (for future use) */ 5626083ed44SThomas Petazzoni }; 5636083ed44SThomas Petazzoni 5646083ed44SThomas Petazzoni struct mvneta_rx_desc { 5656083ed44SThomas Petazzoni u32 status; /* Info about received packet */ 566c5aff182SThomas Petazzoni u16 reserved1; /* pnc_info - (for future use, PnC) */ 567c5aff182SThomas Petazzoni u16 data_size; /* Size of received packet in bytes */ 5686083ed44SThomas Petazzoni 569c5aff182SThomas Petazzoni u32 buf_phys_addr; /* Physical address of the buffer */ 570c5aff182SThomas Petazzoni u32 reserved2; /* pnc_flow_id (for future use, PnC) */ 5716083ed44SThomas Petazzoni 572c5aff182SThomas Petazzoni u32 buf_cookie; /* cookie for access to RX buffer in rx path */ 573c5aff182SThomas Petazzoni u16 reserved3; /* prefetch_cmd, for future use */ 574c5aff182SThomas Petazzoni u16 reserved4; /* csum_l4 - (for future use, PnC) */ 5756083ed44SThomas Petazzoni 576c5aff182SThomas Petazzoni u32 reserved5; /* pnc_extra PnC (for future use, PnC) */ 577c5aff182SThomas Petazzoni u32 reserved6; /* hw_cmd (for future use, PnC and HWF) */ 578c5aff182SThomas Petazzoni }; 5799ad8fef6SThomas Petazzoni #else 5809ad8fef6SThomas Petazzoni struct mvneta_tx_desc { 5819ad8fef6SThomas Petazzoni u16 data_size; /* Data size of transmitted packet in bytes */ 582fbd1d524SAlexandre Belloni u16 reserved1; /* csum_l4 (for future use) */ 5839ad8fef6SThomas Petazzoni u32 command; /* Options used by HW for packet transmitting.*/ 5849ad8fef6SThomas Petazzoni u32 reserved2; /* hw_cmd - (for future use, PMT) */ 5859ad8fef6SThomas Petazzoni u32 buf_phys_addr; /* Physical addr of transmitted buffer */ 5869ad8fef6SThomas Petazzoni u32 reserved3[4]; /* Reserved - (for future use) */ 5879ad8fef6SThomas Petazzoni }; 5889ad8fef6SThomas Petazzoni 5899ad8fef6SThomas Petazzoni struct mvneta_rx_desc { 5909ad8fef6SThomas Petazzoni u16 data_size; /* Size of received packet in bytes */ 5919ad8fef6SThomas Petazzoni u16 reserved1; /* pnc_info - (for future use, PnC) */ 5929ad8fef6SThomas Petazzoni u32 status; /* Info about received packet */ 5939ad8fef6SThomas Petazzoni 5949ad8fef6SThomas Petazzoni u32 reserved2; /* pnc_flow_id (for future use, PnC) */ 5959ad8fef6SThomas Petazzoni u32 buf_phys_addr; /* Physical address of the buffer */ 5969ad8fef6SThomas Petazzoni 5979ad8fef6SThomas Petazzoni u16 reserved4; /* csum_l4 - (for future use, PnC) */ 5989ad8fef6SThomas Petazzoni u16 reserved3; /* prefetch_cmd, for future use */ 5999ad8fef6SThomas Petazzoni u32 buf_cookie; /* cookie for access to RX buffer in rx path */ 6009ad8fef6SThomas Petazzoni 6019ad8fef6SThomas Petazzoni u32 reserved5; /* pnc_extra PnC (for future use, PnC) */ 6029ad8fef6SThomas Petazzoni u32 reserved6; /* hw_cmd (for future use, PnC and HWF) */ 6039ad8fef6SThomas Petazzoni }; 6049ad8fef6SThomas Petazzoni #endif 605c5aff182SThomas Petazzoni 6069e58c8b4SLorenzo Bianconi enum mvneta_tx_buf_type { 6079e58c8b4SLorenzo Bianconi MVNETA_TYPE_SKB, 6089e58c8b4SLorenzo Bianconi MVNETA_TYPE_XDP_TX, 6099e58c8b4SLorenzo Bianconi MVNETA_TYPE_XDP_NDO, 6109e58c8b4SLorenzo Bianconi }; 6119e58c8b4SLorenzo Bianconi 6129e58c8b4SLorenzo Bianconi struct mvneta_tx_buf { 6139e58c8b4SLorenzo Bianconi enum mvneta_tx_buf_type type; 6149e58c8b4SLorenzo Bianconi union { 6159e58c8b4SLorenzo Bianconi struct xdp_frame *xdpf; 6169e58c8b4SLorenzo Bianconi struct sk_buff *skb; 6179e58c8b4SLorenzo Bianconi }; 6189e58c8b4SLorenzo Bianconi }; 6199e58c8b4SLorenzo Bianconi 620c5aff182SThomas Petazzoni struct mvneta_tx_queue { 621c5aff182SThomas Petazzoni /* Number of this TX queue, in the range 0-7 */ 622c5aff182SThomas Petazzoni u8 id; 623c5aff182SThomas Petazzoni 624c5aff182SThomas Petazzoni /* Number of TX DMA descriptors in the descriptor ring */ 625c5aff182SThomas Petazzoni int size; 626c5aff182SThomas Petazzoni 627c5aff182SThomas Petazzoni /* Number of currently used TX DMA descriptor in the 6286a20c175SThomas Petazzoni * descriptor ring 6296a20c175SThomas Petazzoni */ 630c5aff182SThomas Petazzoni int count; 6312a90f7e1SSimon Guinot int pending; 6328eef5f97SEzequiel Garcia int tx_stop_threshold; 6338eef5f97SEzequiel Garcia int tx_wake_threshold; 634c5aff182SThomas Petazzoni 6359e58c8b4SLorenzo Bianconi /* Array of transmitted buffers */ 6369e58c8b4SLorenzo Bianconi struct mvneta_tx_buf *buf; 637c5aff182SThomas Petazzoni 638c5aff182SThomas Petazzoni /* Index of last TX DMA descriptor that was inserted */ 639c5aff182SThomas Petazzoni int txq_put_index; 640c5aff182SThomas Petazzoni 641c5aff182SThomas Petazzoni /* Index of the TX DMA descriptor to be cleaned up */ 642c5aff182SThomas Petazzoni int txq_get_index; 643c5aff182SThomas Petazzoni 644c5aff182SThomas Petazzoni u32 done_pkts_coal; 645c5aff182SThomas Petazzoni 646c5aff182SThomas Petazzoni /* Virtual address of the TX DMA descriptors array */ 647c5aff182SThomas Petazzoni struct mvneta_tx_desc *descs; 648c5aff182SThomas Petazzoni 649c5aff182SThomas Petazzoni /* DMA address of the TX DMA descriptors array */ 650c5aff182SThomas Petazzoni dma_addr_t descs_phys; 651c5aff182SThomas Petazzoni 652c5aff182SThomas Petazzoni /* Index of the last TX DMA descriptor */ 653c5aff182SThomas Petazzoni int last_desc; 654c5aff182SThomas Petazzoni 655c5aff182SThomas Petazzoni /* Index of the next TX DMA descriptor to process */ 656c5aff182SThomas Petazzoni int next_desc_to_proc; 6572adb719dSEzequiel Garcia 6582adb719dSEzequiel Garcia /* DMA buffers for TSO headers */ 6592adb719dSEzequiel Garcia char *tso_hdrs; 6602adb719dSEzequiel Garcia 6612adb719dSEzequiel Garcia /* DMA address of TSO headers */ 6622adb719dSEzequiel Garcia dma_addr_t tso_hdrs_phys; 66350bf8cb6SGregory CLEMENT 66450bf8cb6SGregory CLEMENT /* Affinity mask for CPUs*/ 66550bf8cb6SGregory CLEMENT cpumask_t affinity_mask; 666c5aff182SThomas Petazzoni }; 667c5aff182SThomas Petazzoni 668c5aff182SThomas Petazzoni struct mvneta_rx_queue { 669c5aff182SThomas Petazzoni /* rx queue number, in the range 0-7 */ 670c5aff182SThomas Petazzoni u8 id; 671c5aff182SThomas Petazzoni 672c5aff182SThomas Petazzoni /* num of rx descriptors in the rx descriptor ring */ 673c5aff182SThomas Petazzoni int size; 674c5aff182SThomas Petazzoni 675c5aff182SThomas Petazzoni u32 pkts_coal; 676c5aff182SThomas Petazzoni u32 time_coal; 677c5aff182SThomas Petazzoni 678568a3fa2SLorenzo Bianconi /* page_pool */ 679568a3fa2SLorenzo Bianconi struct page_pool *page_pool; 680568a3fa2SLorenzo Bianconi struct xdp_rxq_info xdp_rxq; 681568a3fa2SLorenzo Bianconi 682f88bee1cSGregory CLEMENT /* Virtual address of the RX buffer */ 683f88bee1cSGregory CLEMENT void **buf_virt_addr; 684f88bee1cSGregory CLEMENT 685c5aff182SThomas Petazzoni /* Virtual address of the RX DMA descriptors array */ 686c5aff182SThomas Petazzoni struct mvneta_rx_desc *descs; 687c5aff182SThomas Petazzoni 688c5aff182SThomas Petazzoni /* DMA address of the RX DMA descriptors array */ 689c5aff182SThomas Petazzoni dma_addr_t descs_phys; 690c5aff182SThomas Petazzoni 691c5aff182SThomas Petazzoni /* Index of the last RX DMA descriptor */ 692c5aff182SThomas Petazzoni int last_desc; 693c5aff182SThomas Petazzoni 694c5aff182SThomas Petazzoni /* Index of the next RX DMA descriptor to process */ 695c5aff182SThomas Petazzoni int next_desc_to_proc; 69617a96da6SGregory CLEMENT 697562e2f46SYelena Krivosheev /* Index of first RX DMA descriptor to refill */ 698562e2f46SYelena Krivosheev int first_to_refill; 699562e2f46SYelena Krivosheev u32 refill_num; 700c5aff182SThomas Petazzoni }; 701c5aff182SThomas Petazzoni 70284a3f4dbSSebastian Andrzej Siewior static enum cpuhp_state online_hpstate; 703edadb7faSEzequiel Garcia /* The hardware supports eight (8) rx queues, but we are only allowing 704edadb7faSEzequiel Garcia * the first one to be used. Therefore, let's just allocate one queue. 705edadb7faSEzequiel Garcia */ 706d8936657SMaxime Ripard static int rxq_number = 8; 707c5aff182SThomas Petazzoni static int txq_number = 8; 708c5aff182SThomas Petazzoni 709c5aff182SThomas Petazzoni static int rxq_def; 710c5aff182SThomas Petazzoni 711f19fadfcSwilly tarreau static int rx_copybreak __read_mostly = 256; 712f19fadfcSwilly tarreau 713dc35a10fSMarcin Wojtas /* HW BM need that each port be identify by a unique ID */ 714dc35a10fSMarcin Wojtas static int global_port_id; 715dc35a10fSMarcin Wojtas 716c5aff182SThomas Petazzoni #define MVNETA_DRIVER_NAME "mvneta" 717c5aff182SThomas Petazzoni #define MVNETA_DRIVER_VERSION "1.0" 718c5aff182SThomas Petazzoni 719c5aff182SThomas Petazzoni /* Utility/helper methods */ 720c5aff182SThomas Petazzoni 721c5aff182SThomas Petazzoni /* Write helper method */ 722c5aff182SThomas Petazzoni static void mvreg_write(struct mvneta_port *pp, u32 offset, u32 data) 723c5aff182SThomas Petazzoni { 724c5aff182SThomas Petazzoni writel(data, pp->base + offset); 725c5aff182SThomas Petazzoni } 726c5aff182SThomas Petazzoni 727c5aff182SThomas Petazzoni /* Read helper method */ 728c5aff182SThomas Petazzoni static u32 mvreg_read(struct mvneta_port *pp, u32 offset) 729c5aff182SThomas Petazzoni { 730c5aff182SThomas Petazzoni return readl(pp->base + offset); 731c5aff182SThomas Petazzoni } 732c5aff182SThomas Petazzoni 733c5aff182SThomas Petazzoni /* Increment txq get counter */ 734c5aff182SThomas Petazzoni static void mvneta_txq_inc_get(struct mvneta_tx_queue *txq) 735c5aff182SThomas Petazzoni { 736c5aff182SThomas Petazzoni txq->txq_get_index++; 737c5aff182SThomas Petazzoni if (txq->txq_get_index == txq->size) 738c5aff182SThomas Petazzoni txq->txq_get_index = 0; 739c5aff182SThomas Petazzoni } 740c5aff182SThomas Petazzoni 741c5aff182SThomas Petazzoni /* Increment txq put counter */ 742c5aff182SThomas Petazzoni static void mvneta_txq_inc_put(struct mvneta_tx_queue *txq) 743c5aff182SThomas Petazzoni { 744c5aff182SThomas Petazzoni txq->txq_put_index++; 745c5aff182SThomas Petazzoni if (txq->txq_put_index == txq->size) 746c5aff182SThomas Petazzoni txq->txq_put_index = 0; 747c5aff182SThomas Petazzoni } 748c5aff182SThomas Petazzoni 749c5aff182SThomas Petazzoni 750c5aff182SThomas Petazzoni /* Clear all MIB counters */ 751c5aff182SThomas Petazzoni static void mvneta_mib_counters_clear(struct mvneta_port *pp) 752c5aff182SThomas Petazzoni { 753c5aff182SThomas Petazzoni int i; 754c5aff182SThomas Petazzoni 755c5aff182SThomas Petazzoni /* Perform dummy reads from MIB counters */ 756c5aff182SThomas Petazzoni for (i = 0; i < MVNETA_MIB_LATE_COLLISION; i += 4) 757098c2fc6SZhang Changzhong mvreg_read(pp, (MVNETA_MIB_COUNTERS_BASE + i)); 758098c2fc6SZhang Changzhong mvreg_read(pp, MVNETA_RX_DISCARD_FRAME_COUNT); 759098c2fc6SZhang Changzhong mvreg_read(pp, MVNETA_OVERRUN_FRAME_COUNT); 760c5aff182SThomas Petazzoni } 761c5aff182SThomas Petazzoni 762c5aff182SThomas Petazzoni /* Get System Network Statistics */ 763bc1f4470Sstephen hemminger static void 7642dc0d2b4SBaoyou Xie mvneta_get_stats64(struct net_device *dev, 765c5aff182SThomas Petazzoni struct rtnl_link_stats64 *stats) 766c5aff182SThomas Petazzoni { 767c5aff182SThomas Petazzoni struct mvneta_port *pp = netdev_priv(dev); 768c5aff182SThomas Petazzoni unsigned int start; 76974c41b04Swilly tarreau int cpu; 770c5aff182SThomas Petazzoni 77174c41b04Swilly tarreau for_each_possible_cpu(cpu) { 77274c41b04Swilly tarreau struct mvneta_pcpu_stats *cpu_stats; 77374c41b04Swilly tarreau u64 rx_packets; 77474c41b04Swilly tarreau u64 rx_bytes; 775c35947b8SLorenzo Bianconi u64 rx_dropped; 776c35947b8SLorenzo Bianconi u64 rx_errors; 77774c41b04Swilly tarreau u64 tx_packets; 77874c41b04Swilly tarreau u64 tx_bytes; 779c5aff182SThomas Petazzoni 78074c41b04Swilly tarreau cpu_stats = per_cpu_ptr(pp->stats, cpu); 781c5aff182SThomas Petazzoni do { 78257a7744eSEric W. Biederman start = u64_stats_fetch_begin_irq(&cpu_stats->syncp); 783320d5441SLorenzo Bianconi rx_packets = cpu_stats->es.ps.rx_packets; 784320d5441SLorenzo Bianconi rx_bytes = cpu_stats->es.ps.rx_bytes; 785c35947b8SLorenzo Bianconi rx_dropped = cpu_stats->rx_dropped; 786c35947b8SLorenzo Bianconi rx_errors = cpu_stats->rx_errors; 787320d5441SLorenzo Bianconi tx_packets = cpu_stats->es.ps.tx_packets; 788320d5441SLorenzo Bianconi tx_bytes = cpu_stats->es.ps.tx_bytes; 78957a7744eSEric W. Biederman } while (u64_stats_fetch_retry_irq(&cpu_stats->syncp, start)); 790c5aff182SThomas Petazzoni 79174c41b04Swilly tarreau stats->rx_packets += rx_packets; 79274c41b04Swilly tarreau stats->rx_bytes += rx_bytes; 793c35947b8SLorenzo Bianconi stats->rx_dropped += rx_dropped; 794c35947b8SLorenzo Bianconi stats->rx_errors += rx_errors; 79574c41b04Swilly tarreau stats->tx_packets += tx_packets; 79674c41b04Swilly tarreau stats->tx_bytes += tx_bytes; 79774c41b04Swilly tarreau } 798c5aff182SThomas Petazzoni 799c5aff182SThomas Petazzoni stats->tx_dropped = dev->stats.tx_dropped; 800c5aff182SThomas Petazzoni } 801c5aff182SThomas Petazzoni 802c5aff182SThomas Petazzoni /* Rx descriptors helper methods */ 803c5aff182SThomas Petazzoni 8045428213cSwilly tarreau /* Checks whether the RX descriptor having this status is both the first 8055428213cSwilly tarreau * and the last descriptor for the RX packet. Each RX packet is currently 806c5aff182SThomas Petazzoni * received through a single RX descriptor, so not having each RX 807c5aff182SThomas Petazzoni * descriptor with its first and last bits set is an error 808c5aff182SThomas Petazzoni */ 8095428213cSwilly tarreau static int mvneta_rxq_desc_is_first_last(u32 status) 810c5aff182SThomas Petazzoni { 8115428213cSwilly tarreau return (status & MVNETA_RXD_FIRST_LAST_DESC) == 812c5aff182SThomas Petazzoni MVNETA_RXD_FIRST_LAST_DESC; 813c5aff182SThomas Petazzoni } 814c5aff182SThomas Petazzoni 815c5aff182SThomas Petazzoni /* Add number of descriptors ready to receive new packets */ 816c5aff182SThomas Petazzoni static void mvneta_rxq_non_occup_desc_add(struct mvneta_port *pp, 817c5aff182SThomas Petazzoni struct mvneta_rx_queue *rxq, 818c5aff182SThomas Petazzoni int ndescs) 819c5aff182SThomas Petazzoni { 820c5aff182SThomas Petazzoni /* Only MVNETA_RXQ_ADD_NON_OCCUPIED_MAX (255) descriptors can 8216a20c175SThomas Petazzoni * be added at once 8226a20c175SThomas Petazzoni */ 823c5aff182SThomas Petazzoni while (ndescs > MVNETA_RXQ_ADD_NON_OCCUPIED_MAX) { 824c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id), 825c5aff182SThomas Petazzoni (MVNETA_RXQ_ADD_NON_OCCUPIED_MAX << 826c5aff182SThomas Petazzoni MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT)); 827c5aff182SThomas Petazzoni ndescs -= MVNETA_RXQ_ADD_NON_OCCUPIED_MAX; 828c5aff182SThomas Petazzoni } 829c5aff182SThomas Petazzoni 830c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id), 831c5aff182SThomas Petazzoni (ndescs << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT)); 832c5aff182SThomas Petazzoni } 833c5aff182SThomas Petazzoni 834c5aff182SThomas Petazzoni /* Get number of RX descriptors occupied by received packets */ 835c5aff182SThomas Petazzoni static int mvneta_rxq_busy_desc_num_get(struct mvneta_port *pp, 836c5aff182SThomas Petazzoni struct mvneta_rx_queue *rxq) 837c5aff182SThomas Petazzoni { 838c5aff182SThomas Petazzoni u32 val; 839c5aff182SThomas Petazzoni 840c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_RXQ_STATUS_REG(rxq->id)); 841c5aff182SThomas Petazzoni return val & MVNETA_RXQ_OCCUPIED_ALL_MASK; 842c5aff182SThomas Petazzoni } 843c5aff182SThomas Petazzoni 8446a20c175SThomas Petazzoni /* Update num of rx desc called upon return from rx path or 845c5aff182SThomas Petazzoni * from mvneta_rxq_drop_pkts(). 846c5aff182SThomas Petazzoni */ 847c5aff182SThomas Petazzoni static void mvneta_rxq_desc_num_update(struct mvneta_port *pp, 848c5aff182SThomas Petazzoni struct mvneta_rx_queue *rxq, 849c5aff182SThomas Petazzoni int rx_done, int rx_filled) 850c5aff182SThomas Petazzoni { 851c5aff182SThomas Petazzoni u32 val; 852c5aff182SThomas Petazzoni 853c5aff182SThomas Petazzoni if ((rx_done <= 0xff) && (rx_filled <= 0xff)) { 854c5aff182SThomas Petazzoni val = rx_done | 855c5aff182SThomas Petazzoni (rx_filled << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT); 856c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id), val); 857c5aff182SThomas Petazzoni return; 858c5aff182SThomas Petazzoni } 859c5aff182SThomas Petazzoni 860c5aff182SThomas Petazzoni /* Only 255 descriptors can be added at once */ 861c5aff182SThomas Petazzoni while ((rx_done > 0) || (rx_filled > 0)) { 862c5aff182SThomas Petazzoni if (rx_done <= 0xff) { 863c5aff182SThomas Petazzoni val = rx_done; 864c5aff182SThomas Petazzoni rx_done = 0; 865c5aff182SThomas Petazzoni } else { 866c5aff182SThomas Petazzoni val = 0xff; 867c5aff182SThomas Petazzoni rx_done -= 0xff; 868c5aff182SThomas Petazzoni } 869c5aff182SThomas Petazzoni if (rx_filled <= 0xff) { 870c5aff182SThomas Petazzoni val |= rx_filled << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT; 871c5aff182SThomas Petazzoni rx_filled = 0; 872c5aff182SThomas Petazzoni } else { 873c5aff182SThomas Petazzoni val |= 0xff << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT; 874c5aff182SThomas Petazzoni rx_filled -= 0xff; 875c5aff182SThomas Petazzoni } 876c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id), val); 877c5aff182SThomas Petazzoni } 878c5aff182SThomas Petazzoni } 879c5aff182SThomas Petazzoni 880c5aff182SThomas Petazzoni /* Get pointer to next RX descriptor to be processed by SW */ 881c5aff182SThomas Petazzoni static struct mvneta_rx_desc * 882c5aff182SThomas Petazzoni mvneta_rxq_next_desc_get(struct mvneta_rx_queue *rxq) 883c5aff182SThomas Petazzoni { 884c5aff182SThomas Petazzoni int rx_desc = rxq->next_desc_to_proc; 885c5aff182SThomas Petazzoni 886c5aff182SThomas Petazzoni rxq->next_desc_to_proc = MVNETA_QUEUE_NEXT_DESC(rxq, rx_desc); 88734e4179dSwilly tarreau prefetch(rxq->descs + rxq->next_desc_to_proc); 888c5aff182SThomas Petazzoni return rxq->descs + rx_desc; 889c5aff182SThomas Petazzoni } 890c5aff182SThomas Petazzoni 891c5aff182SThomas Petazzoni /* Change maximum receive size of the port. */ 892c5aff182SThomas Petazzoni static void mvneta_max_rx_size_set(struct mvneta_port *pp, int max_rx_size) 893c5aff182SThomas Petazzoni { 894c5aff182SThomas Petazzoni u32 val; 895c5aff182SThomas Petazzoni 896c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_GMAC_CTRL_0); 897c5aff182SThomas Petazzoni val &= ~MVNETA_GMAC_MAX_RX_SIZE_MASK; 898c5aff182SThomas Petazzoni val |= ((max_rx_size - MVNETA_MH_SIZE) / 2) << 899c5aff182SThomas Petazzoni MVNETA_GMAC_MAX_RX_SIZE_SHIFT; 900c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_GMAC_CTRL_0, val); 901c5aff182SThomas Petazzoni } 902c5aff182SThomas Petazzoni 903c5aff182SThomas Petazzoni 904c5aff182SThomas Petazzoni /* Set rx queue offset */ 905c5aff182SThomas Petazzoni static void mvneta_rxq_offset_set(struct mvneta_port *pp, 906c5aff182SThomas Petazzoni struct mvneta_rx_queue *rxq, 907c5aff182SThomas Petazzoni int offset) 908c5aff182SThomas Petazzoni { 909c5aff182SThomas Petazzoni u32 val; 910c5aff182SThomas Petazzoni 911c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_RXQ_CONFIG_REG(rxq->id)); 912c5aff182SThomas Petazzoni val &= ~MVNETA_RXQ_PKT_OFFSET_ALL_MASK; 913c5aff182SThomas Petazzoni 914c5aff182SThomas Petazzoni /* Offset is in */ 915c5aff182SThomas Petazzoni val |= MVNETA_RXQ_PKT_OFFSET_MASK(offset >> 3); 916c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_RXQ_CONFIG_REG(rxq->id), val); 917c5aff182SThomas Petazzoni } 918c5aff182SThomas Petazzoni 919c5aff182SThomas Petazzoni 920c5aff182SThomas Petazzoni /* Tx descriptors helper methods */ 921c5aff182SThomas Petazzoni 922c5aff182SThomas Petazzoni /* Update HW with number of TX descriptors to be sent */ 923c5aff182SThomas Petazzoni static void mvneta_txq_pend_desc_add(struct mvneta_port *pp, 924c5aff182SThomas Petazzoni struct mvneta_tx_queue *txq, 925c5aff182SThomas Petazzoni int pend_desc) 926c5aff182SThomas Petazzoni { 927c5aff182SThomas Petazzoni u32 val; 928c5aff182SThomas Petazzoni 9290d63785cSSimon Guinot pend_desc += txq->pending; 9300d63785cSSimon Guinot 9310d63785cSSimon Guinot /* Only 255 Tx descriptors can be added at once */ 9320d63785cSSimon Guinot do { 9330d63785cSSimon Guinot val = min(pend_desc, 255); 934c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val); 9350d63785cSSimon Guinot pend_desc -= val; 9360d63785cSSimon Guinot } while (pend_desc > 0); 9372a90f7e1SSimon Guinot txq->pending = 0; 938c5aff182SThomas Petazzoni } 939c5aff182SThomas Petazzoni 940c5aff182SThomas Petazzoni /* Get pointer to next TX descriptor to be processed (send) by HW */ 941c5aff182SThomas Petazzoni static struct mvneta_tx_desc * 942c5aff182SThomas Petazzoni mvneta_txq_next_desc_get(struct mvneta_tx_queue *txq) 943c5aff182SThomas Petazzoni { 944c5aff182SThomas Petazzoni int tx_desc = txq->next_desc_to_proc; 945c5aff182SThomas Petazzoni 946c5aff182SThomas Petazzoni txq->next_desc_to_proc = MVNETA_QUEUE_NEXT_DESC(txq, tx_desc); 947c5aff182SThomas Petazzoni return txq->descs + tx_desc; 948c5aff182SThomas Petazzoni } 949c5aff182SThomas Petazzoni 950c5aff182SThomas Petazzoni /* Release the last allocated TX descriptor. Useful to handle DMA 9516a20c175SThomas Petazzoni * mapping failures in the TX path. 9526a20c175SThomas Petazzoni */ 953c5aff182SThomas Petazzoni static void mvneta_txq_desc_put(struct mvneta_tx_queue *txq) 954c5aff182SThomas Petazzoni { 955c5aff182SThomas Petazzoni if (txq->next_desc_to_proc == 0) 956c5aff182SThomas Petazzoni txq->next_desc_to_proc = txq->last_desc - 1; 957c5aff182SThomas Petazzoni else 958c5aff182SThomas Petazzoni txq->next_desc_to_proc--; 959c5aff182SThomas Petazzoni } 960c5aff182SThomas Petazzoni 961c5aff182SThomas Petazzoni /* Set rxq buf size */ 962c5aff182SThomas Petazzoni static void mvneta_rxq_buf_size_set(struct mvneta_port *pp, 963c5aff182SThomas Petazzoni struct mvneta_rx_queue *rxq, 964c5aff182SThomas Petazzoni int buf_size) 965c5aff182SThomas Petazzoni { 966c5aff182SThomas Petazzoni u32 val; 967c5aff182SThomas Petazzoni 968c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_RXQ_SIZE_REG(rxq->id)); 969c5aff182SThomas Petazzoni 970c5aff182SThomas Petazzoni val &= ~MVNETA_RXQ_BUF_SIZE_MASK; 971c5aff182SThomas Petazzoni val |= ((buf_size >> 3) << MVNETA_RXQ_BUF_SIZE_SHIFT); 972c5aff182SThomas Petazzoni 973c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_RXQ_SIZE_REG(rxq->id), val); 974c5aff182SThomas Petazzoni } 975c5aff182SThomas Petazzoni 976c5aff182SThomas Petazzoni /* Disable buffer management (BM) */ 977c5aff182SThomas Petazzoni static void mvneta_rxq_bm_disable(struct mvneta_port *pp, 978c5aff182SThomas Petazzoni struct mvneta_rx_queue *rxq) 979c5aff182SThomas Petazzoni { 980c5aff182SThomas Petazzoni u32 val; 981c5aff182SThomas Petazzoni 982c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_RXQ_CONFIG_REG(rxq->id)); 983c5aff182SThomas Petazzoni val &= ~MVNETA_RXQ_HW_BUF_ALLOC; 984c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_RXQ_CONFIG_REG(rxq->id), val); 985c5aff182SThomas Petazzoni } 986c5aff182SThomas Petazzoni 987dc35a10fSMarcin Wojtas /* Enable buffer management (BM) */ 988dc35a10fSMarcin Wojtas static void mvneta_rxq_bm_enable(struct mvneta_port *pp, 989dc35a10fSMarcin Wojtas struct mvneta_rx_queue *rxq) 990dc35a10fSMarcin Wojtas { 991dc35a10fSMarcin Wojtas u32 val; 992dc35a10fSMarcin Wojtas 993dc35a10fSMarcin Wojtas val = mvreg_read(pp, MVNETA_RXQ_CONFIG_REG(rxq->id)); 994dc35a10fSMarcin Wojtas val |= MVNETA_RXQ_HW_BUF_ALLOC; 995dc35a10fSMarcin Wojtas mvreg_write(pp, MVNETA_RXQ_CONFIG_REG(rxq->id), val); 996dc35a10fSMarcin Wojtas } 997dc35a10fSMarcin Wojtas 998dc35a10fSMarcin Wojtas /* Notify HW about port's assignment of pool for bigger packets */ 999dc35a10fSMarcin Wojtas static void mvneta_rxq_long_pool_set(struct mvneta_port *pp, 1000dc35a10fSMarcin Wojtas struct mvneta_rx_queue *rxq) 1001dc35a10fSMarcin Wojtas { 1002dc35a10fSMarcin Wojtas u32 val; 1003dc35a10fSMarcin Wojtas 1004dc35a10fSMarcin Wojtas val = mvreg_read(pp, MVNETA_RXQ_CONFIG_REG(rxq->id)); 1005dc35a10fSMarcin Wojtas val &= ~MVNETA_RXQ_LONG_POOL_ID_MASK; 1006dc35a10fSMarcin Wojtas val |= (pp->pool_long->id << MVNETA_RXQ_LONG_POOL_ID_SHIFT); 1007dc35a10fSMarcin Wojtas 1008dc35a10fSMarcin Wojtas mvreg_write(pp, MVNETA_RXQ_CONFIG_REG(rxq->id), val); 1009dc35a10fSMarcin Wojtas } 1010dc35a10fSMarcin Wojtas 1011dc35a10fSMarcin Wojtas /* Notify HW about port's assignment of pool for smaller packets */ 1012dc35a10fSMarcin Wojtas static void mvneta_rxq_short_pool_set(struct mvneta_port *pp, 1013dc35a10fSMarcin Wojtas struct mvneta_rx_queue *rxq) 1014dc35a10fSMarcin Wojtas { 1015dc35a10fSMarcin Wojtas u32 val; 1016dc35a10fSMarcin Wojtas 1017dc35a10fSMarcin Wojtas val = mvreg_read(pp, MVNETA_RXQ_CONFIG_REG(rxq->id)); 1018dc35a10fSMarcin Wojtas val &= ~MVNETA_RXQ_SHORT_POOL_ID_MASK; 1019dc35a10fSMarcin Wojtas val |= (pp->pool_short->id << MVNETA_RXQ_SHORT_POOL_ID_SHIFT); 1020dc35a10fSMarcin Wojtas 1021dc35a10fSMarcin Wojtas mvreg_write(pp, MVNETA_RXQ_CONFIG_REG(rxq->id), val); 1022dc35a10fSMarcin Wojtas } 1023dc35a10fSMarcin Wojtas 1024dc35a10fSMarcin Wojtas /* Set port's receive buffer size for assigned BM pool */ 1025dc35a10fSMarcin Wojtas static inline void mvneta_bm_pool_bufsize_set(struct mvneta_port *pp, 1026dc35a10fSMarcin Wojtas int buf_size, 1027dc35a10fSMarcin Wojtas u8 pool_id) 1028dc35a10fSMarcin Wojtas { 1029dc35a10fSMarcin Wojtas u32 val; 1030dc35a10fSMarcin Wojtas 1031dc35a10fSMarcin Wojtas if (!IS_ALIGNED(buf_size, 8)) { 1032dc35a10fSMarcin Wojtas dev_warn(pp->dev->dev.parent, 1033dc35a10fSMarcin Wojtas "illegal buf_size value %d, round to %d\n", 1034dc35a10fSMarcin Wojtas buf_size, ALIGN(buf_size, 8)); 1035dc35a10fSMarcin Wojtas buf_size = ALIGN(buf_size, 8); 1036dc35a10fSMarcin Wojtas } 1037dc35a10fSMarcin Wojtas 1038dc35a10fSMarcin Wojtas val = mvreg_read(pp, MVNETA_PORT_POOL_BUFFER_SZ_REG(pool_id)); 1039dc35a10fSMarcin Wojtas val |= buf_size & MVNETA_PORT_POOL_BUFFER_SZ_MASK; 1040dc35a10fSMarcin Wojtas mvreg_write(pp, MVNETA_PORT_POOL_BUFFER_SZ_REG(pool_id), val); 1041dc35a10fSMarcin Wojtas } 1042dc35a10fSMarcin Wojtas 1043dc35a10fSMarcin Wojtas /* Configure MBUS window in order to enable access BM internal SRAM */ 1044dc35a10fSMarcin Wojtas static int mvneta_mbus_io_win_set(struct mvneta_port *pp, u32 base, u32 wsize, 1045dc35a10fSMarcin Wojtas u8 target, u8 attr) 1046dc35a10fSMarcin Wojtas { 1047dc35a10fSMarcin Wojtas u32 win_enable, win_protect; 1048dc35a10fSMarcin Wojtas int i; 1049dc35a10fSMarcin Wojtas 1050dc35a10fSMarcin Wojtas win_enable = mvreg_read(pp, MVNETA_BASE_ADDR_ENABLE); 1051dc35a10fSMarcin Wojtas 1052dc35a10fSMarcin Wojtas if (pp->bm_win_id < 0) { 1053dc35a10fSMarcin Wojtas /* Find first not occupied window */ 1054dc35a10fSMarcin Wojtas for (i = 0; i < MVNETA_MAX_DECODE_WIN; i++) { 1055dc35a10fSMarcin Wojtas if (win_enable & (1 << i)) { 1056dc35a10fSMarcin Wojtas pp->bm_win_id = i; 1057dc35a10fSMarcin Wojtas break; 1058dc35a10fSMarcin Wojtas } 1059dc35a10fSMarcin Wojtas } 1060dc35a10fSMarcin Wojtas if (i == MVNETA_MAX_DECODE_WIN) 1061dc35a10fSMarcin Wojtas return -ENOMEM; 1062dc35a10fSMarcin Wojtas } else { 1063dc35a10fSMarcin Wojtas i = pp->bm_win_id; 1064dc35a10fSMarcin Wojtas } 1065dc35a10fSMarcin Wojtas 1066dc35a10fSMarcin Wojtas mvreg_write(pp, MVNETA_WIN_BASE(i), 0); 1067dc35a10fSMarcin Wojtas mvreg_write(pp, MVNETA_WIN_SIZE(i), 0); 1068dc35a10fSMarcin Wojtas 1069dc35a10fSMarcin Wojtas if (i < 4) 1070dc35a10fSMarcin Wojtas mvreg_write(pp, MVNETA_WIN_REMAP(i), 0); 1071dc35a10fSMarcin Wojtas 1072dc35a10fSMarcin Wojtas mvreg_write(pp, MVNETA_WIN_BASE(i), (base & 0xffff0000) | 1073dc35a10fSMarcin Wojtas (attr << 8) | target); 1074dc35a10fSMarcin Wojtas 1075dc35a10fSMarcin Wojtas mvreg_write(pp, MVNETA_WIN_SIZE(i), (wsize - 1) & 0xffff0000); 1076dc35a10fSMarcin Wojtas 1077dc35a10fSMarcin Wojtas win_protect = mvreg_read(pp, MVNETA_ACCESS_PROTECT_ENABLE); 1078dc35a10fSMarcin Wojtas win_protect |= 3 << (2 * i); 1079dc35a10fSMarcin Wojtas mvreg_write(pp, MVNETA_ACCESS_PROTECT_ENABLE, win_protect); 1080dc35a10fSMarcin Wojtas 1081dc35a10fSMarcin Wojtas win_enable &= ~(1 << i); 1082dc35a10fSMarcin Wojtas mvreg_write(pp, MVNETA_BASE_ADDR_ENABLE, win_enable); 1083dc35a10fSMarcin Wojtas 1084dc35a10fSMarcin Wojtas return 0; 1085dc35a10fSMarcin Wojtas } 1086dc35a10fSMarcin Wojtas 10872636ac3cSMarcin Wojtas static int mvneta_bm_port_mbus_init(struct mvneta_port *pp) 1088dc35a10fSMarcin Wojtas { 10892636ac3cSMarcin Wojtas u32 wsize; 1090dc35a10fSMarcin Wojtas u8 target, attr; 1091dc35a10fSMarcin Wojtas int err; 1092dc35a10fSMarcin Wojtas 1093dc35a10fSMarcin Wojtas /* Get BM window information */ 1094dc35a10fSMarcin Wojtas err = mvebu_mbus_get_io_win_info(pp->bm_priv->bppi_phys_addr, &wsize, 1095dc35a10fSMarcin Wojtas &target, &attr); 1096dc35a10fSMarcin Wojtas if (err < 0) 1097dc35a10fSMarcin Wojtas return err; 1098dc35a10fSMarcin Wojtas 1099dc35a10fSMarcin Wojtas pp->bm_win_id = -1; 1100dc35a10fSMarcin Wojtas 1101dc35a10fSMarcin Wojtas /* Open NETA -> BM window */ 1102dc35a10fSMarcin Wojtas err = mvneta_mbus_io_win_set(pp, pp->bm_priv->bppi_phys_addr, wsize, 1103dc35a10fSMarcin Wojtas target, attr); 1104dc35a10fSMarcin Wojtas if (err < 0) { 1105dc35a10fSMarcin Wojtas netdev_info(pp->dev, "fail to configure mbus window to BM\n"); 1106dc35a10fSMarcin Wojtas return err; 1107dc35a10fSMarcin Wojtas } 11082636ac3cSMarcin Wojtas return 0; 11092636ac3cSMarcin Wojtas } 11102636ac3cSMarcin Wojtas 11112636ac3cSMarcin Wojtas /* Assign and initialize pools for port. In case of fail 11122636ac3cSMarcin Wojtas * buffer manager will remain disabled for current port. 11132636ac3cSMarcin Wojtas */ 11142636ac3cSMarcin Wojtas static int mvneta_bm_port_init(struct platform_device *pdev, 11152636ac3cSMarcin Wojtas struct mvneta_port *pp) 11162636ac3cSMarcin Wojtas { 11172636ac3cSMarcin Wojtas struct device_node *dn = pdev->dev.of_node; 11182636ac3cSMarcin Wojtas u32 long_pool_id, short_pool_id; 11192636ac3cSMarcin Wojtas 11202636ac3cSMarcin Wojtas if (!pp->neta_armada3700) { 11212636ac3cSMarcin Wojtas int ret; 11222636ac3cSMarcin Wojtas 11232636ac3cSMarcin Wojtas ret = mvneta_bm_port_mbus_init(pp); 11242636ac3cSMarcin Wojtas if (ret) 11252636ac3cSMarcin Wojtas return ret; 11262636ac3cSMarcin Wojtas } 1127dc35a10fSMarcin Wojtas 1128dc35a10fSMarcin Wojtas if (of_property_read_u32(dn, "bm,pool-long", &long_pool_id)) { 1129dc35a10fSMarcin Wojtas netdev_info(pp->dev, "missing long pool id\n"); 1130dc35a10fSMarcin Wojtas return -EINVAL; 1131dc35a10fSMarcin Wojtas } 1132dc35a10fSMarcin Wojtas 1133dc35a10fSMarcin Wojtas /* Create port's long pool depending on mtu */ 1134dc35a10fSMarcin Wojtas pp->pool_long = mvneta_bm_pool_use(pp->bm_priv, long_pool_id, 1135dc35a10fSMarcin Wojtas MVNETA_BM_LONG, pp->id, 1136dc35a10fSMarcin Wojtas MVNETA_RX_PKT_SIZE(pp->dev->mtu)); 1137dc35a10fSMarcin Wojtas if (!pp->pool_long) { 1138dc35a10fSMarcin Wojtas netdev_info(pp->dev, "fail to obtain long pool for port\n"); 1139dc35a10fSMarcin Wojtas return -ENOMEM; 1140dc35a10fSMarcin Wojtas } 1141dc35a10fSMarcin Wojtas 1142dc35a10fSMarcin Wojtas pp->pool_long->port_map |= 1 << pp->id; 1143dc35a10fSMarcin Wojtas 1144dc35a10fSMarcin Wojtas mvneta_bm_pool_bufsize_set(pp, pp->pool_long->buf_size, 1145dc35a10fSMarcin Wojtas pp->pool_long->id); 1146dc35a10fSMarcin Wojtas 1147dc35a10fSMarcin Wojtas /* If short pool id is not defined, assume using single pool */ 1148dc35a10fSMarcin Wojtas if (of_property_read_u32(dn, "bm,pool-short", &short_pool_id)) 1149dc35a10fSMarcin Wojtas short_pool_id = long_pool_id; 1150dc35a10fSMarcin Wojtas 1151dc35a10fSMarcin Wojtas /* Create port's short pool */ 1152dc35a10fSMarcin Wojtas pp->pool_short = mvneta_bm_pool_use(pp->bm_priv, short_pool_id, 1153dc35a10fSMarcin Wojtas MVNETA_BM_SHORT, pp->id, 1154dc35a10fSMarcin Wojtas MVNETA_BM_SHORT_PKT_SIZE); 1155dc35a10fSMarcin Wojtas if (!pp->pool_short) { 1156dc35a10fSMarcin Wojtas netdev_info(pp->dev, "fail to obtain short pool for port\n"); 1157dc35a10fSMarcin Wojtas mvneta_bm_pool_destroy(pp->bm_priv, pp->pool_long, 1 << pp->id); 1158dc35a10fSMarcin Wojtas return -ENOMEM; 1159dc35a10fSMarcin Wojtas } 1160dc35a10fSMarcin Wojtas 1161dc35a10fSMarcin Wojtas if (short_pool_id != long_pool_id) { 1162dc35a10fSMarcin Wojtas pp->pool_short->port_map |= 1 << pp->id; 1163dc35a10fSMarcin Wojtas mvneta_bm_pool_bufsize_set(pp, pp->pool_short->buf_size, 1164dc35a10fSMarcin Wojtas pp->pool_short->id); 1165dc35a10fSMarcin Wojtas } 1166dc35a10fSMarcin Wojtas 1167dc35a10fSMarcin Wojtas return 0; 1168dc35a10fSMarcin Wojtas } 1169dc35a10fSMarcin Wojtas 1170dc35a10fSMarcin Wojtas /* Update settings of a pool for bigger packets */ 1171dc35a10fSMarcin Wojtas static void mvneta_bm_update_mtu(struct mvneta_port *pp, int mtu) 1172dc35a10fSMarcin Wojtas { 1173dc35a10fSMarcin Wojtas struct mvneta_bm_pool *bm_pool = pp->pool_long; 1174baa11ebcSGregory CLEMENT struct hwbm_pool *hwbm_pool = &bm_pool->hwbm_pool; 1175dc35a10fSMarcin Wojtas int num; 1176dc35a10fSMarcin Wojtas 1177dc35a10fSMarcin Wojtas /* Release all buffers from long pool */ 1178dc35a10fSMarcin Wojtas mvneta_bm_bufs_free(pp->bm_priv, bm_pool, 1 << pp->id); 1179baa11ebcSGregory CLEMENT if (hwbm_pool->buf_num) { 1180dc35a10fSMarcin Wojtas WARN(1, "cannot free all buffers in pool %d\n", 1181dc35a10fSMarcin Wojtas bm_pool->id); 1182dc35a10fSMarcin Wojtas goto bm_mtu_err; 1183dc35a10fSMarcin Wojtas } 1184dc35a10fSMarcin Wojtas 1185dc35a10fSMarcin Wojtas bm_pool->pkt_size = MVNETA_RX_PKT_SIZE(mtu); 1186dc35a10fSMarcin Wojtas bm_pool->buf_size = MVNETA_RX_BUF_SIZE(bm_pool->pkt_size); 1187baa11ebcSGregory CLEMENT hwbm_pool->frag_size = SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) + 1188dc35a10fSMarcin Wojtas SKB_DATA_ALIGN(MVNETA_RX_BUF_SIZE(bm_pool->pkt_size)); 1189dc35a10fSMarcin Wojtas 1190dc35a10fSMarcin Wojtas /* Fill entire long pool */ 11916dcdd884SSebastian Andrzej Siewior num = hwbm_pool_add(hwbm_pool, hwbm_pool->size); 1192baa11ebcSGregory CLEMENT if (num != hwbm_pool->size) { 1193dc35a10fSMarcin Wojtas WARN(1, "pool %d: %d of %d allocated\n", 1194baa11ebcSGregory CLEMENT bm_pool->id, num, hwbm_pool->size); 1195dc35a10fSMarcin Wojtas goto bm_mtu_err; 1196dc35a10fSMarcin Wojtas } 1197dc35a10fSMarcin Wojtas mvneta_bm_pool_bufsize_set(pp, bm_pool->buf_size, bm_pool->id); 1198dc35a10fSMarcin Wojtas 1199dc35a10fSMarcin Wojtas return; 1200dc35a10fSMarcin Wojtas 1201dc35a10fSMarcin Wojtas bm_mtu_err: 1202dc35a10fSMarcin Wojtas mvneta_bm_pool_destroy(pp->bm_priv, pp->pool_long, 1 << pp->id); 1203dc35a10fSMarcin Wojtas mvneta_bm_pool_destroy(pp->bm_priv, pp->pool_short, 1 << pp->id); 1204dc35a10fSMarcin Wojtas 1205dc35a10fSMarcin Wojtas pp->bm_priv = NULL; 120644efc78dSLorenzo Bianconi pp->rx_offset_correction = MVNETA_SKB_HEADROOM; 1207dc35a10fSMarcin Wojtas mvreg_write(pp, MVNETA_ACC_MODE, MVNETA_ACC_MODE_EXT1); 1208dc35a10fSMarcin Wojtas netdev_info(pp->dev, "fail to update MTU, fall back to software BM\n"); 1209dc35a10fSMarcin Wojtas } 1210dc35a10fSMarcin Wojtas 1211c5aff182SThomas Petazzoni /* Start the Ethernet port RX and TX activity */ 1212c5aff182SThomas Petazzoni static void mvneta_port_up(struct mvneta_port *pp) 1213c5aff182SThomas Petazzoni { 1214c5aff182SThomas Petazzoni int queue; 1215c5aff182SThomas Petazzoni u32 q_map; 1216c5aff182SThomas Petazzoni 1217c5aff182SThomas Petazzoni /* Enable all initialized TXs. */ 1218c5aff182SThomas Petazzoni q_map = 0; 1219c5aff182SThomas Petazzoni for (queue = 0; queue < txq_number; queue++) { 1220c5aff182SThomas Petazzoni struct mvneta_tx_queue *txq = &pp->txqs[queue]; 1221f95936ccSMarkus Elfring if (txq->descs) 1222c5aff182SThomas Petazzoni q_map |= (1 << queue); 1223c5aff182SThomas Petazzoni } 1224c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_TXQ_CMD, q_map); 1225c5aff182SThomas Petazzoni 1226e81b5e01SYelena Krivosheev q_map = 0; 1227c5aff182SThomas Petazzoni /* Enable all initialized RXQs. */ 12282dcf75e2SGregory CLEMENT for (queue = 0; queue < rxq_number; queue++) { 12292dcf75e2SGregory CLEMENT struct mvneta_rx_queue *rxq = &pp->rxqs[queue]; 12302dcf75e2SGregory CLEMENT 1231f95936ccSMarkus Elfring if (rxq->descs) 12322dcf75e2SGregory CLEMENT q_map |= (1 << queue); 12332dcf75e2SGregory CLEMENT } 12342dcf75e2SGregory CLEMENT mvreg_write(pp, MVNETA_RXQ_CMD, q_map); 1235c5aff182SThomas Petazzoni } 1236c5aff182SThomas Petazzoni 1237c5aff182SThomas Petazzoni /* Stop the Ethernet port activity */ 1238c5aff182SThomas Petazzoni static void mvneta_port_down(struct mvneta_port *pp) 1239c5aff182SThomas Petazzoni { 1240c5aff182SThomas Petazzoni u32 val; 1241c5aff182SThomas Petazzoni int count; 1242c5aff182SThomas Petazzoni 1243c5aff182SThomas Petazzoni /* Stop Rx port activity. Check port Rx activity. */ 1244c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_RXQ_CMD) & MVNETA_RXQ_ENABLE_MASK; 1245c5aff182SThomas Petazzoni 1246c5aff182SThomas Petazzoni /* Issue stop command for active channels only */ 1247c5aff182SThomas Petazzoni if (val != 0) 1248c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_RXQ_CMD, 1249c5aff182SThomas Petazzoni val << MVNETA_RXQ_DISABLE_SHIFT); 1250c5aff182SThomas Petazzoni 1251c5aff182SThomas Petazzoni /* Wait for all Rx activity to terminate. */ 1252c5aff182SThomas Petazzoni count = 0; 1253c5aff182SThomas Petazzoni do { 1254c5aff182SThomas Petazzoni if (count++ >= MVNETA_RX_DISABLE_TIMEOUT_MSEC) { 1255c5aff182SThomas Petazzoni netdev_warn(pp->dev, 12560838abb3SDmitri Epshtein "TIMEOUT for RX stopped ! rx_queue_cmd: 0x%08x\n", 1257c5aff182SThomas Petazzoni val); 1258c5aff182SThomas Petazzoni break; 1259c5aff182SThomas Petazzoni } 1260c5aff182SThomas Petazzoni mdelay(1); 1261c5aff182SThomas Petazzoni 1262c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_RXQ_CMD); 1263a3703fb3SDmitri Epshtein } while (val & MVNETA_RXQ_ENABLE_MASK); 1264c5aff182SThomas Petazzoni 1265c5aff182SThomas Petazzoni /* Stop Tx port activity. Check port Tx activity. Issue stop 12666a20c175SThomas Petazzoni * command for active channels only 12676a20c175SThomas Petazzoni */ 1268c5aff182SThomas Petazzoni val = (mvreg_read(pp, MVNETA_TXQ_CMD)) & MVNETA_TXQ_ENABLE_MASK; 1269c5aff182SThomas Petazzoni 1270c5aff182SThomas Petazzoni if (val != 0) 1271c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_TXQ_CMD, 1272c5aff182SThomas Petazzoni (val << MVNETA_TXQ_DISABLE_SHIFT)); 1273c5aff182SThomas Petazzoni 1274c5aff182SThomas Petazzoni /* Wait for all Tx activity to terminate. */ 1275c5aff182SThomas Petazzoni count = 0; 1276c5aff182SThomas Petazzoni do { 1277c5aff182SThomas Petazzoni if (count++ >= MVNETA_TX_DISABLE_TIMEOUT_MSEC) { 1278c5aff182SThomas Petazzoni netdev_warn(pp->dev, 1279c5aff182SThomas Petazzoni "TIMEOUT for TX stopped status=0x%08x\n", 1280c5aff182SThomas Petazzoni val); 1281c5aff182SThomas Petazzoni break; 1282c5aff182SThomas Petazzoni } 1283c5aff182SThomas Petazzoni mdelay(1); 1284c5aff182SThomas Petazzoni 1285c5aff182SThomas Petazzoni /* Check TX Command reg that all Txqs are stopped */ 1286c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_TXQ_CMD); 1287c5aff182SThomas Petazzoni 1288a3703fb3SDmitri Epshtein } while (val & MVNETA_TXQ_ENABLE_MASK); 1289c5aff182SThomas Petazzoni 1290c5aff182SThomas Petazzoni /* Double check to verify that TX FIFO is empty */ 1291c5aff182SThomas Petazzoni count = 0; 1292c5aff182SThomas Petazzoni do { 1293c5aff182SThomas Petazzoni if (count++ >= MVNETA_TX_FIFO_EMPTY_TIMEOUT) { 1294c5aff182SThomas Petazzoni netdev_warn(pp->dev, 12950838abb3SDmitri Epshtein "TX FIFO empty timeout status=0x%08x\n", 1296c5aff182SThomas Petazzoni val); 1297c5aff182SThomas Petazzoni break; 1298c5aff182SThomas Petazzoni } 1299c5aff182SThomas Petazzoni mdelay(1); 1300c5aff182SThomas Petazzoni 1301c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_PORT_STATUS); 1302c5aff182SThomas Petazzoni } while (!(val & MVNETA_TX_FIFO_EMPTY) && 1303c5aff182SThomas Petazzoni (val & MVNETA_TX_IN_PRGRS)); 1304c5aff182SThomas Petazzoni 1305c5aff182SThomas Petazzoni udelay(200); 1306c5aff182SThomas Petazzoni } 1307c5aff182SThomas Petazzoni 1308c5aff182SThomas Petazzoni /* Enable the port by setting the port enable bit of the MAC control register */ 1309c5aff182SThomas Petazzoni static void mvneta_port_enable(struct mvneta_port *pp) 1310c5aff182SThomas Petazzoni { 1311c5aff182SThomas Petazzoni u32 val; 1312c5aff182SThomas Petazzoni 1313c5aff182SThomas Petazzoni /* Enable port */ 1314c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_GMAC_CTRL_0); 1315c5aff182SThomas Petazzoni val |= MVNETA_GMAC0_PORT_ENABLE; 1316c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_GMAC_CTRL_0, val); 1317c5aff182SThomas Petazzoni } 1318c5aff182SThomas Petazzoni 1319c5aff182SThomas Petazzoni /* Disable the port and wait for about 200 usec before retuning */ 1320c5aff182SThomas Petazzoni static void mvneta_port_disable(struct mvneta_port *pp) 1321c5aff182SThomas Petazzoni { 1322c5aff182SThomas Petazzoni u32 val; 1323c5aff182SThomas Petazzoni 1324c5aff182SThomas Petazzoni /* Reset the Enable bit in the Serial Control Register */ 1325c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_GMAC_CTRL_0); 1326c5aff182SThomas Petazzoni val &= ~MVNETA_GMAC0_PORT_ENABLE; 1327c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_GMAC_CTRL_0, val); 1328c5aff182SThomas Petazzoni 1329c5aff182SThomas Petazzoni udelay(200); 1330c5aff182SThomas Petazzoni } 1331c5aff182SThomas Petazzoni 1332c5aff182SThomas Petazzoni /* Multicast tables methods */ 1333c5aff182SThomas Petazzoni 1334c5aff182SThomas Petazzoni /* Set all entries in Unicast MAC Table; queue==-1 means reject all */ 1335c5aff182SThomas Petazzoni static void mvneta_set_ucast_table(struct mvneta_port *pp, int queue) 1336c5aff182SThomas Petazzoni { 1337c5aff182SThomas Petazzoni int offset; 1338c5aff182SThomas Petazzoni u32 val; 1339c5aff182SThomas Petazzoni 1340c5aff182SThomas Petazzoni if (queue == -1) { 1341c5aff182SThomas Petazzoni val = 0; 1342c5aff182SThomas Petazzoni } else { 1343c5aff182SThomas Petazzoni val = 0x1 | (queue << 1); 1344c5aff182SThomas Petazzoni val |= (val << 24) | (val << 16) | (val << 8); 1345c5aff182SThomas Petazzoni } 1346c5aff182SThomas Petazzoni 1347c5aff182SThomas Petazzoni for (offset = 0; offset <= 0xc; offset += 4) 1348c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_DA_FILT_UCAST_BASE + offset, val); 1349c5aff182SThomas Petazzoni } 1350c5aff182SThomas Petazzoni 1351c5aff182SThomas Petazzoni /* Set all entries in Special Multicast MAC Table; queue==-1 means reject all */ 1352c5aff182SThomas Petazzoni static void mvneta_set_special_mcast_table(struct mvneta_port *pp, int queue) 1353c5aff182SThomas Petazzoni { 1354c5aff182SThomas Petazzoni int offset; 1355c5aff182SThomas Petazzoni u32 val; 1356c5aff182SThomas Petazzoni 1357c5aff182SThomas Petazzoni if (queue == -1) { 1358c5aff182SThomas Petazzoni val = 0; 1359c5aff182SThomas Petazzoni } else { 1360c5aff182SThomas Petazzoni val = 0x1 | (queue << 1); 1361c5aff182SThomas Petazzoni val |= (val << 24) | (val << 16) | (val << 8); 1362c5aff182SThomas Petazzoni } 1363c5aff182SThomas Petazzoni 1364c5aff182SThomas Petazzoni for (offset = 0; offset <= 0xfc; offset += 4) 1365c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_DA_FILT_SPEC_MCAST + offset, val); 1366c5aff182SThomas Petazzoni 1367c5aff182SThomas Petazzoni } 1368c5aff182SThomas Petazzoni 1369c5aff182SThomas Petazzoni /* Set all entries in Other Multicast MAC Table. queue==-1 means reject all */ 1370c5aff182SThomas Petazzoni static void mvneta_set_other_mcast_table(struct mvneta_port *pp, int queue) 1371c5aff182SThomas Petazzoni { 1372c5aff182SThomas Petazzoni int offset; 1373c5aff182SThomas Petazzoni u32 val; 1374c5aff182SThomas Petazzoni 1375c5aff182SThomas Petazzoni if (queue == -1) { 1376c5aff182SThomas Petazzoni memset(pp->mcast_count, 0, sizeof(pp->mcast_count)); 1377c5aff182SThomas Petazzoni val = 0; 1378c5aff182SThomas Petazzoni } else { 1379c5aff182SThomas Petazzoni memset(pp->mcast_count, 1, sizeof(pp->mcast_count)); 1380c5aff182SThomas Petazzoni val = 0x1 | (queue << 1); 1381c5aff182SThomas Petazzoni val |= (val << 24) | (val << 16) | (val << 8); 1382c5aff182SThomas Petazzoni } 1383c5aff182SThomas Petazzoni 1384c5aff182SThomas Petazzoni for (offset = 0; offset <= 0xfc; offset += 4) 1385c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_DA_FILT_OTH_MCAST + offset, val); 1386c5aff182SThomas Petazzoni } 1387c5aff182SThomas Petazzoni 1388db488c10SGregory CLEMENT static void mvneta_percpu_unmask_interrupt(void *arg) 1389db488c10SGregory CLEMENT { 1390db488c10SGregory CLEMENT struct mvneta_port *pp = arg; 1391db488c10SGregory CLEMENT 1392db488c10SGregory CLEMENT /* All the queue are unmasked, but actually only the ones 1393db488c10SGregory CLEMENT * mapped to this CPU will be unmasked 1394db488c10SGregory CLEMENT */ 1395db488c10SGregory CLEMENT mvreg_write(pp, MVNETA_INTR_NEW_MASK, 1396db488c10SGregory CLEMENT MVNETA_RX_INTR_MASK_ALL | 1397db488c10SGregory CLEMENT MVNETA_TX_INTR_MASK_ALL | 1398db488c10SGregory CLEMENT MVNETA_MISCINTR_INTR_MASK); 1399db488c10SGregory CLEMENT } 1400db488c10SGregory CLEMENT 1401db488c10SGregory CLEMENT static void mvneta_percpu_mask_interrupt(void *arg) 1402db488c10SGregory CLEMENT { 1403db488c10SGregory CLEMENT struct mvneta_port *pp = arg; 1404db488c10SGregory CLEMENT 1405db488c10SGregory CLEMENT /* All the queue are masked, but actually only the ones 1406db488c10SGregory CLEMENT * mapped to this CPU will be masked 1407db488c10SGregory CLEMENT */ 1408db488c10SGregory CLEMENT mvreg_write(pp, MVNETA_INTR_NEW_MASK, 0); 1409db488c10SGregory CLEMENT mvreg_write(pp, MVNETA_INTR_OLD_MASK, 0); 1410db488c10SGregory CLEMENT mvreg_write(pp, MVNETA_INTR_MISC_MASK, 0); 1411db488c10SGregory CLEMENT } 1412db488c10SGregory CLEMENT 1413db488c10SGregory CLEMENT static void mvneta_percpu_clear_intr_cause(void *arg) 1414db488c10SGregory CLEMENT { 1415db488c10SGregory CLEMENT struct mvneta_port *pp = arg; 1416db488c10SGregory CLEMENT 1417db488c10SGregory CLEMENT /* All the queue are cleared, but actually only the ones 1418db488c10SGregory CLEMENT * mapped to this CPU will be cleared 1419db488c10SGregory CLEMENT */ 1420db488c10SGregory CLEMENT mvreg_write(pp, MVNETA_INTR_NEW_CAUSE, 0); 1421db488c10SGregory CLEMENT mvreg_write(pp, MVNETA_INTR_MISC_CAUSE, 0); 1422db488c10SGregory CLEMENT mvreg_write(pp, MVNETA_INTR_OLD_CAUSE, 0); 1423db488c10SGregory CLEMENT } 1424db488c10SGregory CLEMENT 1425c5aff182SThomas Petazzoni /* This method sets defaults to the NETA port: 1426c5aff182SThomas Petazzoni * Clears interrupt Cause and Mask registers. 1427c5aff182SThomas Petazzoni * Clears all MAC tables. 1428c5aff182SThomas Petazzoni * Sets defaults to all registers. 1429c5aff182SThomas Petazzoni * Resets RX and TX descriptor rings. 1430c5aff182SThomas Petazzoni * Resets PHY. 1431c5aff182SThomas Petazzoni * This method can be called after mvneta_port_down() to return the port 1432c5aff182SThomas Petazzoni * settings to defaults. 1433c5aff182SThomas Petazzoni */ 1434c5aff182SThomas Petazzoni static void mvneta_defaults_set(struct mvneta_port *pp) 1435c5aff182SThomas Petazzoni { 1436c5aff182SThomas Petazzoni int cpu; 1437c5aff182SThomas Petazzoni int queue; 1438c5aff182SThomas Petazzoni u32 val; 14392dcf75e2SGregory CLEMENT int max_cpu = num_present_cpus(); 1440c5aff182SThomas Petazzoni 1441c5aff182SThomas Petazzoni /* Clear all Cause registers */ 1442db488c10SGregory CLEMENT on_each_cpu(mvneta_percpu_clear_intr_cause, pp, true); 1443c5aff182SThomas Petazzoni 1444c5aff182SThomas Petazzoni /* Mask all interrupts */ 1445db488c10SGregory CLEMENT on_each_cpu(mvneta_percpu_mask_interrupt, pp, true); 1446c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_INTR_ENABLE, 0); 1447c5aff182SThomas Petazzoni 1448c5aff182SThomas Petazzoni /* Enable MBUS Retry bit16 */ 1449c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_MBUS_RETRY, 0x20); 1450c5aff182SThomas Petazzoni 145150bf8cb6SGregory CLEMENT /* Set CPU queue access map. CPUs are assigned to the RX and 145250bf8cb6SGregory CLEMENT * TX queues modulo their number. If there is only one TX 145350bf8cb6SGregory CLEMENT * queue then it is assigned to the CPU associated to the 145450bf8cb6SGregory CLEMENT * default RX queue. 14556a20c175SThomas Petazzoni */ 14562dcf75e2SGregory CLEMENT for_each_present_cpu(cpu) { 14572dcf75e2SGregory CLEMENT int rxq_map = 0, txq_map = 0; 145850bf8cb6SGregory CLEMENT int rxq, txq; 14592636ac3cSMarcin Wojtas if (!pp->neta_armada3700) { 14602dcf75e2SGregory CLEMENT for (rxq = 0; rxq < rxq_number; rxq++) 14612dcf75e2SGregory CLEMENT if ((rxq % max_cpu) == cpu) 14622dcf75e2SGregory CLEMENT rxq_map |= MVNETA_CPU_RXQ_ACCESS(rxq); 14632dcf75e2SGregory CLEMENT 146450bf8cb6SGregory CLEMENT for (txq = 0; txq < txq_number; txq++) 146550bf8cb6SGregory CLEMENT if ((txq % max_cpu) == cpu) 146650bf8cb6SGregory CLEMENT txq_map |= MVNETA_CPU_TXQ_ACCESS(txq); 146750bf8cb6SGregory CLEMENT 146850bf8cb6SGregory CLEMENT /* With only one TX queue we configure a special case 146950bf8cb6SGregory CLEMENT * which will allow to get all the irq on a single 147050bf8cb6SGregory CLEMENT * CPU 147150bf8cb6SGregory CLEMENT */ 147250bf8cb6SGregory CLEMENT if (txq_number == 1) 147350bf8cb6SGregory CLEMENT txq_map = (cpu == pp->rxq_def) ? 147450bf8cb6SGregory CLEMENT MVNETA_CPU_TXQ_ACCESS(1) : 0; 14752dcf75e2SGregory CLEMENT 14762636ac3cSMarcin Wojtas } else { 14772636ac3cSMarcin Wojtas txq_map = MVNETA_CPU_TXQ_ACCESS_ALL_MASK; 14782636ac3cSMarcin Wojtas rxq_map = MVNETA_CPU_RXQ_ACCESS_ALL_MASK; 14792636ac3cSMarcin Wojtas } 14802636ac3cSMarcin Wojtas 14812dcf75e2SGregory CLEMENT mvreg_write(pp, MVNETA_CPU_MAP(cpu), rxq_map | txq_map); 14822dcf75e2SGregory CLEMENT } 1483c5aff182SThomas Petazzoni 1484c5aff182SThomas Petazzoni /* Reset RX and TX DMAs */ 1485c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_PORT_RX_RESET, MVNETA_PORT_RX_DMA_RESET); 1486c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_PORT_TX_RESET, MVNETA_PORT_TX_DMA_RESET); 1487c5aff182SThomas Petazzoni 1488c5aff182SThomas Petazzoni /* Disable Legacy WRR, Disable EJP, Release from reset */ 1489c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_TXQ_CMD_1, 0); 1490c5aff182SThomas Petazzoni for (queue = 0; queue < txq_number; queue++) { 1491c5aff182SThomas Petazzoni mvreg_write(pp, MVETH_TXQ_TOKEN_COUNT_REG(queue), 0); 1492c5aff182SThomas Petazzoni mvreg_write(pp, MVETH_TXQ_TOKEN_CFG_REG(queue), 0); 1493c5aff182SThomas Petazzoni } 1494c5aff182SThomas Petazzoni 1495c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_PORT_TX_RESET, 0); 1496c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_PORT_RX_RESET, 0); 1497c5aff182SThomas Petazzoni 1498c5aff182SThomas Petazzoni /* Set Port Acceleration Mode */ 1499dc35a10fSMarcin Wojtas if (pp->bm_priv) 1500dc35a10fSMarcin Wojtas /* HW buffer management + legacy parser */ 1501dc35a10fSMarcin Wojtas val = MVNETA_ACC_MODE_EXT2; 1502dc35a10fSMarcin Wojtas else 1503dc35a10fSMarcin Wojtas /* SW buffer management + legacy parser */ 1504dc35a10fSMarcin Wojtas val = MVNETA_ACC_MODE_EXT1; 1505c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_ACC_MODE, val); 1506c5aff182SThomas Petazzoni 1507dc35a10fSMarcin Wojtas if (pp->bm_priv) 1508dc35a10fSMarcin Wojtas mvreg_write(pp, MVNETA_BM_ADDRESS, pp->bm_priv->bppi_phys_addr); 1509dc35a10fSMarcin Wojtas 1510c5aff182SThomas Petazzoni /* Update val of portCfg register accordingly with all RxQueue types */ 151190b74c01SGregory CLEMENT val = MVNETA_PORT_CONFIG_DEFL_VALUE(pp->rxq_def); 1512c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_PORT_CONFIG, val); 1513c5aff182SThomas Petazzoni 1514c5aff182SThomas Petazzoni val = 0; 1515c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_PORT_CONFIG_EXTEND, val); 1516c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_RX_MIN_FRAME_SIZE, 64); 1517c5aff182SThomas Petazzoni 1518c5aff182SThomas Petazzoni /* Build PORT_SDMA_CONFIG_REG */ 1519c5aff182SThomas Petazzoni val = 0; 1520c5aff182SThomas Petazzoni 1521c5aff182SThomas Petazzoni /* Default burst size */ 1522c5aff182SThomas Petazzoni val |= MVNETA_TX_BRST_SZ_MASK(MVNETA_SDMA_BRST_SIZE_16); 1523c5aff182SThomas Petazzoni val |= MVNETA_RX_BRST_SZ_MASK(MVNETA_SDMA_BRST_SIZE_16); 15249ad8fef6SThomas Petazzoni val |= MVNETA_RX_NO_DATA_SWAP | MVNETA_TX_NO_DATA_SWAP; 1525c5aff182SThomas Petazzoni 15269ad8fef6SThomas Petazzoni #if defined(__BIG_ENDIAN) 15279ad8fef6SThomas Petazzoni val |= MVNETA_DESC_SWAP; 15289ad8fef6SThomas Petazzoni #endif 1529c5aff182SThomas Petazzoni 1530c5aff182SThomas Petazzoni /* Assign port SDMA configuration */ 1531c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_SDMA_CONFIG, val); 1532c5aff182SThomas Petazzoni 153371408602SThomas Petazzoni /* Disable PHY polling in hardware, since we're using the 153471408602SThomas Petazzoni * kernel phylib to do this. 153571408602SThomas Petazzoni */ 153671408602SThomas Petazzoni val = mvreg_read(pp, MVNETA_UNIT_CONTROL); 153771408602SThomas Petazzoni val &= ~MVNETA_PHY_POLLING_ENABLE; 153871408602SThomas Petazzoni mvreg_write(pp, MVNETA_UNIT_CONTROL, val); 153971408602SThomas Petazzoni 1540c5aff182SThomas Petazzoni mvneta_set_ucast_table(pp, -1); 1541c5aff182SThomas Petazzoni mvneta_set_special_mcast_table(pp, -1); 1542c5aff182SThomas Petazzoni mvneta_set_other_mcast_table(pp, -1); 1543c5aff182SThomas Petazzoni 1544c5aff182SThomas Petazzoni /* Set port interrupt enable register - default enable all */ 1545c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_INTR_ENABLE, 1546c5aff182SThomas Petazzoni (MVNETA_RXQ_INTR_ENABLE_ALL_MASK 1547c5aff182SThomas Petazzoni | MVNETA_TXQ_INTR_ENABLE_ALL_MASK)); 1548e483911fSAndrew Lunn 1549e483911fSAndrew Lunn mvneta_mib_counters_clear(pp); 1550c5aff182SThomas Petazzoni } 1551c5aff182SThomas Petazzoni 1552c5aff182SThomas Petazzoni /* Set max sizes for tx queues */ 1553c5aff182SThomas Petazzoni static void mvneta_txq_max_tx_size_set(struct mvneta_port *pp, int max_tx_size) 1554c5aff182SThomas Petazzoni 1555c5aff182SThomas Petazzoni { 1556c5aff182SThomas Petazzoni u32 val, size, mtu; 1557c5aff182SThomas Petazzoni int queue; 1558c5aff182SThomas Petazzoni 1559c5aff182SThomas Petazzoni mtu = max_tx_size * 8; 1560c5aff182SThomas Petazzoni if (mtu > MVNETA_TX_MTU_MAX) 1561c5aff182SThomas Petazzoni mtu = MVNETA_TX_MTU_MAX; 1562c5aff182SThomas Petazzoni 1563c5aff182SThomas Petazzoni /* Set MTU */ 1564c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_TX_MTU); 1565c5aff182SThomas Petazzoni val &= ~MVNETA_TX_MTU_MAX; 1566c5aff182SThomas Petazzoni val |= mtu; 1567c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_TX_MTU, val); 1568c5aff182SThomas Petazzoni 1569c5aff182SThomas Petazzoni /* TX token size and all TXQs token size must be larger that MTU */ 1570c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_TX_TOKEN_SIZE); 1571c5aff182SThomas Petazzoni 1572c5aff182SThomas Petazzoni size = val & MVNETA_TX_TOKEN_SIZE_MAX; 1573c5aff182SThomas Petazzoni if (size < mtu) { 1574c5aff182SThomas Petazzoni size = mtu; 1575c5aff182SThomas Petazzoni val &= ~MVNETA_TX_TOKEN_SIZE_MAX; 1576c5aff182SThomas Petazzoni val |= size; 1577c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_TX_TOKEN_SIZE, val); 1578c5aff182SThomas Petazzoni } 1579c5aff182SThomas Petazzoni for (queue = 0; queue < txq_number; queue++) { 1580c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_TXQ_TOKEN_SIZE_REG(queue)); 1581c5aff182SThomas Petazzoni 1582c5aff182SThomas Petazzoni size = val & MVNETA_TXQ_TOKEN_SIZE_MAX; 1583c5aff182SThomas Petazzoni if (size < mtu) { 1584c5aff182SThomas Petazzoni size = mtu; 1585c5aff182SThomas Petazzoni val &= ~MVNETA_TXQ_TOKEN_SIZE_MAX; 1586c5aff182SThomas Petazzoni val |= size; 1587c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_TXQ_TOKEN_SIZE_REG(queue), val); 1588c5aff182SThomas Petazzoni } 1589c5aff182SThomas Petazzoni } 1590c5aff182SThomas Petazzoni } 1591c5aff182SThomas Petazzoni 1592c5aff182SThomas Petazzoni /* Set unicast address */ 1593c5aff182SThomas Petazzoni static void mvneta_set_ucast_addr(struct mvneta_port *pp, u8 last_nibble, 1594c5aff182SThomas Petazzoni int queue) 1595c5aff182SThomas Petazzoni { 1596c5aff182SThomas Petazzoni unsigned int unicast_reg; 1597c5aff182SThomas Petazzoni unsigned int tbl_offset; 1598c5aff182SThomas Petazzoni unsigned int reg_offset; 1599c5aff182SThomas Petazzoni 1600c5aff182SThomas Petazzoni /* Locate the Unicast table entry */ 1601c5aff182SThomas Petazzoni last_nibble = (0xf & last_nibble); 1602c5aff182SThomas Petazzoni 1603c5aff182SThomas Petazzoni /* offset from unicast tbl base */ 1604c5aff182SThomas Petazzoni tbl_offset = (last_nibble / 4) * 4; 1605c5aff182SThomas Petazzoni 1606c5aff182SThomas Petazzoni /* offset within the above reg */ 1607c5aff182SThomas Petazzoni reg_offset = last_nibble % 4; 1608c5aff182SThomas Petazzoni 1609c5aff182SThomas Petazzoni unicast_reg = mvreg_read(pp, (MVNETA_DA_FILT_UCAST_BASE + tbl_offset)); 1610c5aff182SThomas Petazzoni 1611c5aff182SThomas Petazzoni if (queue == -1) { 1612c5aff182SThomas Petazzoni /* Clear accepts frame bit at specified unicast DA tbl entry */ 1613c5aff182SThomas Petazzoni unicast_reg &= ~(0xff << (8 * reg_offset)); 1614c5aff182SThomas Petazzoni } else { 1615c5aff182SThomas Petazzoni unicast_reg &= ~(0xff << (8 * reg_offset)); 1616c5aff182SThomas Petazzoni unicast_reg |= ((0x01 | (queue << 1)) << (8 * reg_offset)); 1617c5aff182SThomas Petazzoni } 1618c5aff182SThomas Petazzoni 1619c5aff182SThomas Petazzoni mvreg_write(pp, (MVNETA_DA_FILT_UCAST_BASE + tbl_offset), unicast_reg); 1620c5aff182SThomas Petazzoni } 1621c5aff182SThomas Petazzoni 1622c5aff182SThomas Petazzoni /* Set mac address */ 1623c5aff182SThomas Petazzoni static void mvneta_mac_addr_set(struct mvneta_port *pp, unsigned char *addr, 1624c5aff182SThomas Petazzoni int queue) 1625c5aff182SThomas Petazzoni { 1626c5aff182SThomas Petazzoni unsigned int mac_h; 1627c5aff182SThomas Petazzoni unsigned int mac_l; 1628c5aff182SThomas Petazzoni 1629c5aff182SThomas Petazzoni if (queue != -1) { 1630c5aff182SThomas Petazzoni mac_l = (addr[4] << 8) | (addr[5]); 1631c5aff182SThomas Petazzoni mac_h = (addr[0] << 24) | (addr[1] << 16) | 1632c5aff182SThomas Petazzoni (addr[2] << 8) | (addr[3] << 0); 1633c5aff182SThomas Petazzoni 1634c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_MAC_ADDR_LOW, mac_l); 1635c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_MAC_ADDR_HIGH, mac_h); 1636c5aff182SThomas Petazzoni } 1637c5aff182SThomas Petazzoni 1638c5aff182SThomas Petazzoni /* Accept frames of this address */ 1639c5aff182SThomas Petazzoni mvneta_set_ucast_addr(pp, addr[5], queue); 1640c5aff182SThomas Petazzoni } 1641c5aff182SThomas Petazzoni 16426a20c175SThomas Petazzoni /* Set the number of packets that will be received before RX interrupt 16436a20c175SThomas Petazzoni * will be generated by HW. 1644c5aff182SThomas Petazzoni */ 1645c5aff182SThomas Petazzoni static void mvneta_rx_pkts_coal_set(struct mvneta_port *pp, 1646c5aff182SThomas Petazzoni struct mvneta_rx_queue *rxq, u32 value) 1647c5aff182SThomas Petazzoni { 1648c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_RXQ_THRESHOLD_REG(rxq->id), 1649c5aff182SThomas Petazzoni value | MVNETA_RXQ_NON_OCCUPIED(0)); 1650c5aff182SThomas Petazzoni } 1651c5aff182SThomas Petazzoni 16526a20c175SThomas Petazzoni /* Set the time delay in usec before RX interrupt will be generated by 16536a20c175SThomas Petazzoni * HW. 1654c5aff182SThomas Petazzoni */ 1655c5aff182SThomas Petazzoni static void mvneta_rx_time_coal_set(struct mvneta_port *pp, 1656c5aff182SThomas Petazzoni struct mvneta_rx_queue *rxq, u32 value) 1657c5aff182SThomas Petazzoni { 1658189dd626SThomas Petazzoni u32 val; 1659189dd626SThomas Petazzoni unsigned long clk_rate; 1660189dd626SThomas Petazzoni 1661189dd626SThomas Petazzoni clk_rate = clk_get_rate(pp->clk); 1662189dd626SThomas Petazzoni val = (clk_rate / 1000000) * value; 1663c5aff182SThomas Petazzoni 1664c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_RXQ_TIME_COAL_REG(rxq->id), val); 1665c5aff182SThomas Petazzoni } 1666c5aff182SThomas Petazzoni 1667c5aff182SThomas Petazzoni /* Set threshold for TX_DONE pkts coalescing */ 1668c5aff182SThomas Petazzoni static void mvneta_tx_done_pkts_coal_set(struct mvneta_port *pp, 1669c5aff182SThomas Petazzoni struct mvneta_tx_queue *txq, u32 value) 1670c5aff182SThomas Petazzoni { 1671c5aff182SThomas Petazzoni u32 val; 1672c5aff182SThomas Petazzoni 1673c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_TXQ_SIZE_REG(txq->id)); 1674c5aff182SThomas Petazzoni 1675c5aff182SThomas Petazzoni val &= ~MVNETA_TXQ_SENT_THRESH_ALL_MASK; 1676c5aff182SThomas Petazzoni val |= MVNETA_TXQ_SENT_THRESH_MASK(value); 1677c5aff182SThomas Petazzoni 1678c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_TXQ_SIZE_REG(txq->id), val); 1679c5aff182SThomas Petazzoni } 1680c5aff182SThomas Petazzoni 1681c5aff182SThomas Petazzoni /* Handle rx descriptor fill by setting buf_cookie and buf_phys_addr */ 1682c5aff182SThomas Petazzoni static void mvneta_rx_desc_fill(struct mvneta_rx_desc *rx_desc, 1683f88bee1cSGregory CLEMENT u32 phys_addr, void *virt_addr, 1684f88bee1cSGregory CLEMENT struct mvneta_rx_queue *rxq) 1685c5aff182SThomas Petazzoni { 1686f88bee1cSGregory CLEMENT int i; 1687f88bee1cSGregory CLEMENT 1688c5aff182SThomas Petazzoni rx_desc->buf_phys_addr = phys_addr; 1689f88bee1cSGregory CLEMENT i = rx_desc - rxq->descs; 1690f88bee1cSGregory CLEMENT rxq->buf_virt_addr[i] = virt_addr; 1691c5aff182SThomas Petazzoni } 1692c5aff182SThomas Petazzoni 1693c5aff182SThomas Petazzoni /* Decrement sent descriptors counter */ 1694c5aff182SThomas Petazzoni static void mvneta_txq_sent_desc_dec(struct mvneta_port *pp, 1695c5aff182SThomas Petazzoni struct mvneta_tx_queue *txq, 1696c5aff182SThomas Petazzoni int sent_desc) 1697c5aff182SThomas Petazzoni { 1698c5aff182SThomas Petazzoni u32 val; 1699c5aff182SThomas Petazzoni 1700c5aff182SThomas Petazzoni /* Only 255 TX descriptors can be updated at once */ 1701c5aff182SThomas Petazzoni while (sent_desc > 0xff) { 1702c5aff182SThomas Petazzoni val = 0xff << MVNETA_TXQ_DEC_SENT_SHIFT; 1703c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val); 1704c5aff182SThomas Petazzoni sent_desc = sent_desc - 0xff; 1705c5aff182SThomas Petazzoni } 1706c5aff182SThomas Petazzoni 1707c5aff182SThomas Petazzoni val = sent_desc << MVNETA_TXQ_DEC_SENT_SHIFT; 1708c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val); 1709c5aff182SThomas Petazzoni } 1710c5aff182SThomas Petazzoni 1711c5aff182SThomas Petazzoni /* Get number of TX descriptors already sent by HW */ 1712c5aff182SThomas Petazzoni static int mvneta_txq_sent_desc_num_get(struct mvneta_port *pp, 1713c5aff182SThomas Petazzoni struct mvneta_tx_queue *txq) 1714c5aff182SThomas Petazzoni { 1715c5aff182SThomas Petazzoni u32 val; 1716c5aff182SThomas Petazzoni int sent_desc; 1717c5aff182SThomas Petazzoni 1718c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_TXQ_STATUS_REG(txq->id)); 1719c5aff182SThomas Petazzoni sent_desc = (val & MVNETA_TXQ_SENT_DESC_MASK) >> 1720c5aff182SThomas Petazzoni MVNETA_TXQ_SENT_DESC_SHIFT; 1721c5aff182SThomas Petazzoni 1722c5aff182SThomas Petazzoni return sent_desc; 1723c5aff182SThomas Petazzoni } 1724c5aff182SThomas Petazzoni 17256a20c175SThomas Petazzoni /* Get number of sent descriptors and decrement counter. 1726c5aff182SThomas Petazzoni * The number of sent descriptors is returned. 1727c5aff182SThomas Petazzoni */ 1728c5aff182SThomas Petazzoni static int mvneta_txq_sent_desc_proc(struct mvneta_port *pp, 1729c5aff182SThomas Petazzoni struct mvneta_tx_queue *txq) 1730c5aff182SThomas Petazzoni { 1731c5aff182SThomas Petazzoni int sent_desc; 1732c5aff182SThomas Petazzoni 1733c5aff182SThomas Petazzoni /* Get number of sent descriptors */ 1734c5aff182SThomas Petazzoni sent_desc = mvneta_txq_sent_desc_num_get(pp, txq); 1735c5aff182SThomas Petazzoni 1736c5aff182SThomas Petazzoni /* Decrement sent descriptors counter */ 1737c5aff182SThomas Petazzoni if (sent_desc) 1738c5aff182SThomas Petazzoni mvneta_txq_sent_desc_dec(pp, txq, sent_desc); 1739c5aff182SThomas Petazzoni 1740c5aff182SThomas Petazzoni return sent_desc; 1741c5aff182SThomas Petazzoni } 1742c5aff182SThomas Petazzoni 1743c5aff182SThomas Petazzoni /* Set TXQ descriptors fields relevant for CSUM calculation */ 1744c5aff182SThomas Petazzoni static u32 mvneta_txq_desc_csum(int l3_offs, int l3_proto, 1745c5aff182SThomas Petazzoni int ip_hdr_len, int l4_proto) 1746c5aff182SThomas Petazzoni { 1747c5aff182SThomas Petazzoni u32 command; 1748c5aff182SThomas Petazzoni 1749c5aff182SThomas Petazzoni /* Fields: L3_offset, IP_hdrlen, L3_type, G_IPv4_chk, 17506a20c175SThomas Petazzoni * G_L4_chk, L4_type; required only for checksum 17516a20c175SThomas Petazzoni * calculation 17526a20c175SThomas Petazzoni */ 1753c5aff182SThomas Petazzoni command = l3_offs << MVNETA_TX_L3_OFF_SHIFT; 1754c5aff182SThomas Petazzoni command |= ip_hdr_len << MVNETA_TX_IP_HLEN_SHIFT; 1755c5aff182SThomas Petazzoni 17560a198587SThomas Fitzsimmons if (l3_proto == htons(ETH_P_IP)) 1757c5aff182SThomas Petazzoni command |= MVNETA_TXD_IP_CSUM; 1758c5aff182SThomas Petazzoni else 1759c5aff182SThomas Petazzoni command |= MVNETA_TX_L3_IP6; 1760c5aff182SThomas Petazzoni 1761c5aff182SThomas Petazzoni if (l4_proto == IPPROTO_TCP) 1762c5aff182SThomas Petazzoni command |= MVNETA_TX_L4_CSUM_FULL; 1763c5aff182SThomas Petazzoni else if (l4_proto == IPPROTO_UDP) 1764c5aff182SThomas Petazzoni command |= MVNETA_TX_L4_UDP | MVNETA_TX_L4_CSUM_FULL; 1765c5aff182SThomas Petazzoni else 1766c5aff182SThomas Petazzoni command |= MVNETA_TX_L4_CSUM_NOT; 1767c5aff182SThomas Petazzoni 1768c5aff182SThomas Petazzoni return command; 1769c5aff182SThomas Petazzoni } 1770c5aff182SThomas Petazzoni 1771c5aff182SThomas Petazzoni 1772c5aff182SThomas Petazzoni /* Display more error info */ 1773c5aff182SThomas Petazzoni static void mvneta_rx_error(struct mvneta_port *pp, 1774c5aff182SThomas Petazzoni struct mvneta_rx_desc *rx_desc) 1775c5aff182SThomas Petazzoni { 1776c35947b8SLorenzo Bianconi struct mvneta_pcpu_stats *stats = this_cpu_ptr(pp->stats); 1777c5aff182SThomas Petazzoni u32 status = rx_desc->status; 1778c5aff182SThomas Petazzoni 1779c35947b8SLorenzo Bianconi /* update per-cpu counter */ 1780c35947b8SLorenzo Bianconi u64_stats_update_begin(&stats->syncp); 1781c35947b8SLorenzo Bianconi stats->rx_errors++; 1782c35947b8SLorenzo Bianconi u64_stats_update_end(&stats->syncp); 1783c35947b8SLorenzo Bianconi 1784c5aff182SThomas Petazzoni switch (status & MVNETA_RXD_ERR_CODE_MASK) { 1785c5aff182SThomas Petazzoni case MVNETA_RXD_ERR_CRC: 1786c5aff182SThomas Petazzoni netdev_err(pp->dev, "bad rx status %08x (crc error), size=%d\n", 1787c5aff182SThomas Petazzoni status, rx_desc->data_size); 1788c5aff182SThomas Petazzoni break; 1789c5aff182SThomas Petazzoni case MVNETA_RXD_ERR_OVERRUN: 1790c5aff182SThomas Petazzoni netdev_err(pp->dev, "bad rx status %08x (overrun error), size=%d\n", 1791c5aff182SThomas Petazzoni status, rx_desc->data_size); 1792c5aff182SThomas Petazzoni break; 1793c5aff182SThomas Petazzoni case MVNETA_RXD_ERR_LEN: 1794c5aff182SThomas Petazzoni netdev_err(pp->dev, "bad rx status %08x (max frame length error), size=%d\n", 1795c5aff182SThomas Petazzoni status, rx_desc->data_size); 1796c5aff182SThomas Petazzoni break; 1797c5aff182SThomas Petazzoni case MVNETA_RXD_ERR_RESOURCE: 1798c5aff182SThomas Petazzoni netdev_err(pp->dev, "bad rx status %08x (resource error), size=%d\n", 1799c5aff182SThomas Petazzoni status, rx_desc->data_size); 1800c5aff182SThomas Petazzoni break; 1801c5aff182SThomas Petazzoni } 1802c5aff182SThomas Petazzoni } 1803c5aff182SThomas Petazzoni 18045428213cSwilly tarreau /* Handle RX checksum offload based on the descriptor's status */ 18055428213cSwilly tarreau static void mvneta_rx_csum(struct mvneta_port *pp, u32 status, 1806c5aff182SThomas Petazzoni struct sk_buff *skb) 1807c5aff182SThomas Petazzoni { 1808f945cec8SYelena Krivosheev if ((pp->dev->features & NETIF_F_RXCSUM) && 1809f945cec8SYelena Krivosheev (status & MVNETA_RXD_L3_IP4) && 18105428213cSwilly tarreau (status & MVNETA_RXD_L4_CSUM_OK)) { 1811c5aff182SThomas Petazzoni skb->csum = 0; 1812c5aff182SThomas Petazzoni skb->ip_summed = CHECKSUM_UNNECESSARY; 1813c5aff182SThomas Petazzoni return; 1814c5aff182SThomas Petazzoni } 1815c5aff182SThomas Petazzoni 1816c5aff182SThomas Petazzoni skb->ip_summed = CHECKSUM_NONE; 1817c5aff182SThomas Petazzoni } 1818c5aff182SThomas Petazzoni 18196c498974Swilly tarreau /* Return tx queue pointer (find last set bit) according to <cause> returned 18206c498974Swilly tarreau * form tx_done reg. <cause> must not be null. The return value is always a 18216c498974Swilly tarreau * valid queue for matching the first one found in <cause>. 18226c498974Swilly tarreau */ 1823c5aff182SThomas Petazzoni static struct mvneta_tx_queue *mvneta_tx_done_policy(struct mvneta_port *pp, 1824c5aff182SThomas Petazzoni u32 cause) 1825c5aff182SThomas Petazzoni { 1826c5aff182SThomas Petazzoni int queue = fls(cause) - 1; 1827c5aff182SThomas Petazzoni 18286c498974Swilly tarreau return &pp->txqs[queue]; 1829c5aff182SThomas Petazzoni } 1830c5aff182SThomas Petazzoni 1831c5aff182SThomas Petazzoni /* Free tx queue skbuffs */ 1832c5aff182SThomas Petazzoni static void mvneta_txq_bufs_free(struct mvneta_port *pp, 1833a29b6235SMarcin Wojtas struct mvneta_tx_queue *txq, int num, 1834632bb64fSLorenzo Bianconi struct netdev_queue *nq, bool napi) 1835c5aff182SThomas Petazzoni { 1836a29b6235SMarcin Wojtas unsigned int bytes_compl = 0, pkts_compl = 0; 1837c5aff182SThomas Petazzoni int i; 1838c5aff182SThomas Petazzoni 1839c5aff182SThomas Petazzoni for (i = 0; i < num; i++) { 18409e58c8b4SLorenzo Bianconi struct mvneta_tx_buf *buf = &txq->buf[txq->txq_get_index]; 1841c5aff182SThomas Petazzoni struct mvneta_tx_desc *tx_desc = txq->descs + 1842c5aff182SThomas Petazzoni txq->txq_get_index; 1843a29b6235SMarcin Wojtas 1844c5aff182SThomas Petazzoni mvneta_txq_inc_get(txq); 1845c5aff182SThomas Petazzoni 1846b0a43db9SLorenzo Bianconi if (!IS_TSO_HEADER(txq, tx_desc->buf_phys_addr) && 1847b0a43db9SLorenzo Bianconi buf->type != MVNETA_TYPE_XDP_TX) 18482e3173a3SEzequiel Garcia dma_unmap_single(pp->dev->dev.parent, 18492e3173a3SEzequiel Garcia tx_desc->buf_phys_addr, 1850c5aff182SThomas Petazzoni tx_desc->data_size, DMA_TO_DEVICE); 1851b0a43db9SLorenzo Bianconi if (buf->type == MVNETA_TYPE_SKB && buf->skb) { 18529e58c8b4SLorenzo Bianconi bytes_compl += buf->skb->len; 18539e58c8b4SLorenzo Bianconi pkts_compl++; 18549e58c8b4SLorenzo Bianconi dev_kfree_skb_any(buf->skb); 1855b0a43db9SLorenzo Bianconi } else if (buf->type == MVNETA_TYPE_XDP_TX || 1856b0a43db9SLorenzo Bianconi buf->type == MVNETA_TYPE_XDP_NDO) { 1857632bb64fSLorenzo Bianconi if (napi && buf->type == MVNETA_TYPE_XDP_TX) 1858632bb64fSLorenzo Bianconi xdp_return_frame_rx_napi(buf->xdpf); 1859632bb64fSLorenzo Bianconi else 1860b0a43db9SLorenzo Bianconi xdp_return_frame(buf->xdpf); 1861b0a43db9SLorenzo Bianconi } 1862c5aff182SThomas Petazzoni } 1863a29b6235SMarcin Wojtas 1864a29b6235SMarcin Wojtas netdev_tx_completed_queue(nq, pkts_compl, bytes_compl); 1865c5aff182SThomas Petazzoni } 1866c5aff182SThomas Petazzoni 1867c5aff182SThomas Petazzoni /* Handle end of transmission */ 1868cd713199SArnaud Ebalard static void mvneta_txq_done(struct mvneta_port *pp, 1869c5aff182SThomas Petazzoni struct mvneta_tx_queue *txq) 1870c5aff182SThomas Petazzoni { 1871c5aff182SThomas Petazzoni struct netdev_queue *nq = netdev_get_tx_queue(pp->dev, txq->id); 1872c5aff182SThomas Petazzoni int tx_done; 1873c5aff182SThomas Petazzoni 1874c5aff182SThomas Petazzoni tx_done = mvneta_txq_sent_desc_proc(pp, txq); 1875cd713199SArnaud Ebalard if (!tx_done) 1876cd713199SArnaud Ebalard return; 1877cd713199SArnaud Ebalard 1878632bb64fSLorenzo Bianconi mvneta_txq_bufs_free(pp, txq, tx_done, nq, true); 1879c5aff182SThomas Petazzoni 1880c5aff182SThomas Petazzoni txq->count -= tx_done; 1881c5aff182SThomas Petazzoni 1882c5aff182SThomas Petazzoni if (netif_tx_queue_stopped(nq)) { 18838eef5f97SEzequiel Garcia if (txq->count <= txq->tx_wake_threshold) 1884c5aff182SThomas Petazzoni netif_tx_wake_queue(nq); 1885c5aff182SThomas Petazzoni } 1886c5aff182SThomas Petazzoni } 1887c5aff182SThomas Petazzoni 1888dc35a10fSMarcin Wojtas /* Refill processing for SW buffer management */ 18897e47fd84SGregory CLEMENT /* Allocate page per descriptor */ 1890c5aff182SThomas Petazzoni static int mvneta_rx_refill(struct mvneta_port *pp, 1891f88bee1cSGregory CLEMENT struct mvneta_rx_desc *rx_desc, 18927e47fd84SGregory CLEMENT struct mvneta_rx_queue *rxq, 18937e47fd84SGregory CLEMENT gfp_t gfp_mask) 1894c5aff182SThomas Petazzoni { 1895c5aff182SThomas Petazzoni dma_addr_t phys_addr; 18967e47fd84SGregory CLEMENT struct page *page; 1897c5aff182SThomas Petazzoni 1898568a3fa2SLorenzo Bianconi page = page_pool_alloc_pages(rxq->page_pool, 1899568a3fa2SLorenzo Bianconi gfp_mask | __GFP_NOWARN); 19007e47fd84SGregory CLEMENT if (!page) 1901c5aff182SThomas Petazzoni return -ENOMEM; 1902c5aff182SThomas Petazzoni 1903568a3fa2SLorenzo Bianconi phys_addr = page_pool_get_dma_addr(page) + pp->rx_offset_correction; 19047e47fd84SGregory CLEMENT mvneta_rx_desc_fill(rx_desc, phys_addr, page, rxq); 1905568a3fa2SLorenzo Bianconi 1906c5aff182SThomas Petazzoni return 0; 1907c5aff182SThomas Petazzoni } 1908c5aff182SThomas Petazzoni 1909c5aff182SThomas Petazzoni /* Handle tx checksum */ 1910c5aff182SThomas Petazzoni static u32 mvneta_skb_tx_csum(struct mvneta_port *pp, struct sk_buff *skb) 1911c5aff182SThomas Petazzoni { 1912c5aff182SThomas Petazzoni if (skb->ip_summed == CHECKSUM_PARTIAL) { 1913c5aff182SThomas Petazzoni int ip_hdr_len = 0; 1914817dbfa5SVlad Yasevich __be16 l3_proto = vlan_get_protocol(skb); 1915c5aff182SThomas Petazzoni u8 l4_proto; 1916c5aff182SThomas Petazzoni 1917817dbfa5SVlad Yasevich if (l3_proto == htons(ETH_P_IP)) { 1918c5aff182SThomas Petazzoni struct iphdr *ip4h = ip_hdr(skb); 1919c5aff182SThomas Petazzoni 1920c5aff182SThomas Petazzoni /* Calculate IPv4 checksum and L4 checksum */ 1921c5aff182SThomas Petazzoni ip_hdr_len = ip4h->ihl; 1922c5aff182SThomas Petazzoni l4_proto = ip4h->protocol; 1923817dbfa5SVlad Yasevich } else if (l3_proto == htons(ETH_P_IPV6)) { 1924c5aff182SThomas Petazzoni struct ipv6hdr *ip6h = ipv6_hdr(skb); 1925c5aff182SThomas Petazzoni 1926c5aff182SThomas Petazzoni /* Read l4_protocol from one of IPv6 extra headers */ 1927c5aff182SThomas Petazzoni if (skb_network_header_len(skb) > 0) 1928c5aff182SThomas Petazzoni ip_hdr_len = (skb_network_header_len(skb) >> 2); 1929c5aff182SThomas Petazzoni l4_proto = ip6h->nexthdr; 1930c5aff182SThomas Petazzoni } else 1931c5aff182SThomas Petazzoni return MVNETA_TX_L4_CSUM_NOT; 1932c5aff182SThomas Petazzoni 1933c5aff182SThomas Petazzoni return mvneta_txq_desc_csum(skb_network_offset(skb), 1934817dbfa5SVlad Yasevich l3_proto, ip_hdr_len, l4_proto); 1935c5aff182SThomas Petazzoni } 1936c5aff182SThomas Petazzoni 1937c5aff182SThomas Petazzoni return MVNETA_TX_L4_CSUM_NOT; 1938c5aff182SThomas Petazzoni } 1939c5aff182SThomas Petazzoni 1940c5aff182SThomas Petazzoni /* Drop packets received by the RXQ and free buffers */ 1941c5aff182SThomas Petazzoni static void mvneta_rxq_drop_pkts(struct mvneta_port *pp, 1942c5aff182SThomas Petazzoni struct mvneta_rx_queue *rxq) 1943c5aff182SThomas Petazzoni { 1944c5aff182SThomas Petazzoni int rx_done, i; 1945c5aff182SThomas Petazzoni 1946c5aff182SThomas Petazzoni rx_done = mvneta_rxq_busy_desc_num_get(pp, rxq); 1947dc35a10fSMarcin Wojtas if (rx_done) 1948dc35a10fSMarcin Wojtas mvneta_rxq_desc_num_update(pp, rxq, rx_done, rx_done); 1949dc35a10fSMarcin Wojtas 1950dc35a10fSMarcin Wojtas if (pp->bm_priv) { 1951dc35a10fSMarcin Wojtas for (i = 0; i < rx_done; i++) { 1952dc35a10fSMarcin Wojtas struct mvneta_rx_desc *rx_desc = 1953dc35a10fSMarcin Wojtas mvneta_rxq_next_desc_get(rxq); 1954dc35a10fSMarcin Wojtas u8 pool_id = MVNETA_RX_GET_BM_POOL_ID(rx_desc); 1955dc35a10fSMarcin Wojtas struct mvneta_bm_pool *bm_pool; 1956dc35a10fSMarcin Wojtas 1957dc35a10fSMarcin Wojtas bm_pool = &pp->bm_priv->bm_pools[pool_id]; 1958dc35a10fSMarcin Wojtas /* Return dropped buffer to the pool */ 1959dc35a10fSMarcin Wojtas mvneta_bm_pool_put_bp(pp->bm_priv, bm_pool, 1960dc35a10fSMarcin Wojtas rx_desc->buf_phys_addr); 1961dc35a10fSMarcin Wojtas } 1962dc35a10fSMarcin Wojtas return; 1963dc35a10fSMarcin Wojtas } 1964dc35a10fSMarcin Wojtas 1965c5aff182SThomas Petazzoni for (i = 0; i < rxq->size; i++) { 1966c5aff182SThomas Petazzoni struct mvneta_rx_desc *rx_desc = rxq->descs + i; 1967f88bee1cSGregory CLEMENT void *data = rxq->buf_virt_addr[i]; 1968562e2f46SYelena Krivosheev if (!data || !(rx_desc->buf_phys_addr)) 1969562e2f46SYelena Krivosheev continue; 1970c5aff182SThomas Petazzoni 1971458de8a9SIlias Apalodimas page_pool_put_full_page(rxq->page_pool, data, false); 1972dc35a10fSMarcin Wojtas } 1973568a3fa2SLorenzo Bianconi if (xdp_rxq_info_is_reg(&rxq->xdp_rxq)) 1974568a3fa2SLorenzo Bianconi xdp_rxq_info_unreg(&rxq->xdp_rxq); 1975568a3fa2SLorenzo Bianconi page_pool_destroy(rxq->page_pool); 1976568a3fa2SLorenzo Bianconi rxq->page_pool = NULL; 1977c5aff182SThomas Petazzoni } 1978c5aff182SThomas Petazzoni 1979ff519e2aSLorenzo Bianconi static void 1980320d5441SLorenzo Bianconi mvneta_update_stats(struct mvneta_port *pp, 1981320d5441SLorenzo Bianconi struct mvneta_stats *ps) 1982ff519e2aSLorenzo Bianconi { 1983ff519e2aSLorenzo Bianconi struct mvneta_pcpu_stats *stats = this_cpu_ptr(pp->stats); 1984ff519e2aSLorenzo Bianconi 1985ff519e2aSLorenzo Bianconi u64_stats_update_begin(&stats->syncp); 1986320d5441SLorenzo Bianconi stats->es.ps.rx_packets += ps->rx_packets; 1987320d5441SLorenzo Bianconi stats->es.ps.rx_bytes += ps->rx_bytes; 19883d866523SLorenzo Bianconi /* xdp */ 19893d866523SLorenzo Bianconi stats->es.ps.xdp_redirect += ps->xdp_redirect; 19903d866523SLorenzo Bianconi stats->es.ps.xdp_pass += ps->xdp_pass; 19913d866523SLorenzo Bianconi stats->es.ps.xdp_drop += ps->xdp_drop; 1992ff519e2aSLorenzo Bianconi u64_stats_update_end(&stats->syncp); 1993ff519e2aSLorenzo Bianconi } 1994ff519e2aSLorenzo Bianconi 1995562e2f46SYelena Krivosheev static inline 1996562e2f46SYelena Krivosheev int mvneta_rx_refill_queue(struct mvneta_port *pp, struct mvneta_rx_queue *rxq) 1997562e2f46SYelena Krivosheev { 1998562e2f46SYelena Krivosheev struct mvneta_rx_desc *rx_desc; 1999562e2f46SYelena Krivosheev int curr_desc = rxq->first_to_refill; 2000562e2f46SYelena Krivosheev int i; 2001562e2f46SYelena Krivosheev 2002562e2f46SYelena Krivosheev for (i = 0; (i < rxq->refill_num) && (i < 64); i++) { 2003562e2f46SYelena Krivosheev rx_desc = rxq->descs + curr_desc; 2004562e2f46SYelena Krivosheev if (!(rx_desc->buf_phys_addr)) { 2005562e2f46SYelena Krivosheev if (mvneta_rx_refill(pp, rx_desc, rxq, GFP_ATOMIC)) { 20069ac41f3cSLorenzo Bianconi struct mvneta_pcpu_stats *stats; 20079ac41f3cSLorenzo Bianconi 2008562e2f46SYelena Krivosheev pr_err("Can't refill queue %d. Done %d from %d\n", 2009562e2f46SYelena Krivosheev rxq->id, i, rxq->refill_num); 20109ac41f3cSLorenzo Bianconi 20119ac41f3cSLorenzo Bianconi stats = this_cpu_ptr(pp->stats); 20129ac41f3cSLorenzo Bianconi u64_stats_update_begin(&stats->syncp); 20139ac41f3cSLorenzo Bianconi stats->es.refill_error++; 20149ac41f3cSLorenzo Bianconi u64_stats_update_end(&stats->syncp); 2015562e2f46SYelena Krivosheev break; 2016562e2f46SYelena Krivosheev } 2017562e2f46SYelena Krivosheev } 2018562e2f46SYelena Krivosheev curr_desc = MVNETA_QUEUE_NEXT_DESC(rxq, curr_desc); 2019562e2f46SYelena Krivosheev } 2020562e2f46SYelena Krivosheev rxq->refill_num -= i; 2021562e2f46SYelena Krivosheev rxq->first_to_refill = curr_desc; 2022562e2f46SYelena Krivosheev 2023562e2f46SYelena Krivosheev return i; 2024562e2f46SYelena Krivosheev } 2025562e2f46SYelena Krivosheev 2026ca0e0146SLorenzo Bianconi static void 2027ca0e0146SLorenzo Bianconi mvneta_xdp_put_buff(struct mvneta_port *pp, struct mvneta_rx_queue *rxq, 2028ca0e0146SLorenzo Bianconi struct xdp_buff *xdp, int sync_len, bool napi) 2029ca0e0146SLorenzo Bianconi { 2030ca0e0146SLorenzo Bianconi struct skb_shared_info *sinfo = xdp_get_shared_info_from_buff(xdp); 2031ca0e0146SLorenzo Bianconi int i; 2032ca0e0146SLorenzo Bianconi 2033ca0e0146SLorenzo Bianconi for (i = 0; i < sinfo->nr_frags; i++) 2034ca0e0146SLorenzo Bianconi page_pool_put_full_page(rxq->page_pool, 2035ca0e0146SLorenzo Bianconi skb_frag_page(&sinfo->frags[i]), napi); 20369d3b2d3eSLorenzo Bianconi page_pool_put_page(rxq->page_pool, virt_to_head_page(xdp->data), 20379d3b2d3eSLorenzo Bianconi sync_len, napi); 2038ca0e0146SLorenzo Bianconi } 2039ca0e0146SLorenzo Bianconi 20408dc9a088SLorenzo Bianconi static int 2041b0a43db9SLorenzo Bianconi mvneta_xdp_submit_frame(struct mvneta_port *pp, struct mvneta_tx_queue *txq, 2042b0a43db9SLorenzo Bianconi struct xdp_frame *xdpf, bool dma_map) 2043b0a43db9SLorenzo Bianconi { 2044b0a43db9SLorenzo Bianconi struct mvneta_tx_desc *tx_desc; 2045b0a43db9SLorenzo Bianconi struct mvneta_tx_buf *buf; 2046b0a43db9SLorenzo Bianconi dma_addr_t dma_addr; 2047b0a43db9SLorenzo Bianconi 2048b0a43db9SLorenzo Bianconi if (txq->count >= txq->tx_stop_threshold) 2049b0a43db9SLorenzo Bianconi return MVNETA_XDP_DROPPED; 2050b0a43db9SLorenzo Bianconi 2051b0a43db9SLorenzo Bianconi tx_desc = mvneta_txq_next_desc_get(txq); 2052b0a43db9SLorenzo Bianconi 2053b0a43db9SLorenzo Bianconi buf = &txq->buf[txq->txq_put_index]; 2054b0a43db9SLorenzo Bianconi if (dma_map) { 2055b0a43db9SLorenzo Bianconi /* ndo_xdp_xmit */ 2056b0a43db9SLorenzo Bianconi dma_addr = dma_map_single(pp->dev->dev.parent, xdpf->data, 2057b0a43db9SLorenzo Bianconi xdpf->len, DMA_TO_DEVICE); 2058b0a43db9SLorenzo Bianconi if (dma_mapping_error(pp->dev->dev.parent, dma_addr)) { 2059b0a43db9SLorenzo Bianconi mvneta_txq_desc_put(txq); 2060b0a43db9SLorenzo Bianconi return MVNETA_XDP_DROPPED; 2061b0a43db9SLorenzo Bianconi } 2062b0a43db9SLorenzo Bianconi buf->type = MVNETA_TYPE_XDP_NDO; 2063b0a43db9SLorenzo Bianconi } else { 2064b0a43db9SLorenzo Bianconi struct page *page = virt_to_page(xdpf->data); 2065b0a43db9SLorenzo Bianconi 2066b0a43db9SLorenzo Bianconi dma_addr = page_pool_get_dma_addr(page) + 2067b0a43db9SLorenzo Bianconi sizeof(*xdpf) + xdpf->headroom; 2068b0a43db9SLorenzo Bianconi dma_sync_single_for_device(pp->dev->dev.parent, dma_addr, 2069b0a43db9SLorenzo Bianconi xdpf->len, DMA_BIDIRECTIONAL); 2070b0a43db9SLorenzo Bianconi buf->type = MVNETA_TYPE_XDP_TX; 2071b0a43db9SLorenzo Bianconi } 2072b0a43db9SLorenzo Bianconi buf->xdpf = xdpf; 2073b0a43db9SLorenzo Bianconi 2074b0a43db9SLorenzo Bianconi tx_desc->command = MVNETA_TXD_FLZ_DESC; 2075b0a43db9SLorenzo Bianconi tx_desc->buf_phys_addr = dma_addr; 2076b0a43db9SLorenzo Bianconi tx_desc->data_size = xdpf->len; 2077b0a43db9SLorenzo Bianconi 2078b0a43db9SLorenzo Bianconi mvneta_txq_inc_put(txq); 2079b0a43db9SLorenzo Bianconi txq->pending++; 2080b0a43db9SLorenzo Bianconi txq->count++; 2081b0a43db9SLorenzo Bianconi 2082b0a43db9SLorenzo Bianconi return MVNETA_XDP_TX; 2083b0a43db9SLorenzo Bianconi } 2084b0a43db9SLorenzo Bianconi 2085b0a43db9SLorenzo Bianconi static int 2086b0a43db9SLorenzo Bianconi mvneta_xdp_xmit_back(struct mvneta_port *pp, struct xdp_buff *xdp) 2087b0a43db9SLorenzo Bianconi { 208815070919SJesper Dangaard Brouer struct mvneta_pcpu_stats *stats = this_cpu_ptr(pp->stats); 2089b0a43db9SLorenzo Bianconi struct mvneta_tx_queue *txq; 2090b0a43db9SLorenzo Bianconi struct netdev_queue *nq; 2091b0a43db9SLorenzo Bianconi struct xdp_frame *xdpf; 2092b0a43db9SLorenzo Bianconi int cpu; 2093b0a43db9SLorenzo Bianconi u32 ret; 2094b0a43db9SLorenzo Bianconi 20951b698fa5SLorenzo Bianconi xdpf = xdp_convert_buff_to_frame(xdp); 2096b0a43db9SLorenzo Bianconi if (unlikely(!xdpf)) 2097b0a43db9SLorenzo Bianconi return MVNETA_XDP_DROPPED; 2098b0a43db9SLorenzo Bianconi 2099b0a43db9SLorenzo Bianconi cpu = smp_processor_id(); 2100b0a43db9SLorenzo Bianconi txq = &pp->txqs[cpu % txq_number]; 2101b0a43db9SLorenzo Bianconi nq = netdev_get_tx_queue(pp->dev, txq->id); 2102b0a43db9SLorenzo Bianconi 2103b0a43db9SLorenzo Bianconi __netif_tx_lock(nq, cpu); 2104b0a43db9SLorenzo Bianconi ret = mvneta_xdp_submit_frame(pp, txq, xdpf, false); 21057d51a015SLorenzo Bianconi if (ret == MVNETA_XDP_TX) { 21067d51a015SLorenzo Bianconi u64_stats_update_begin(&stats->syncp); 21077d51a015SLorenzo Bianconi stats->es.ps.tx_bytes += xdpf->len; 21087d51a015SLorenzo Bianconi stats->es.ps.tx_packets++; 21097d51a015SLorenzo Bianconi stats->es.ps.xdp_tx++; 21107d51a015SLorenzo Bianconi u64_stats_update_end(&stats->syncp); 21117d51a015SLorenzo Bianconi 2112b0a43db9SLorenzo Bianconi mvneta_txq_pend_desc_add(pp, txq, 0); 211315070919SJesper Dangaard Brouer } else { 211415070919SJesper Dangaard Brouer u64_stats_update_begin(&stats->syncp); 211515070919SJesper Dangaard Brouer stats->es.ps.xdp_tx_err++; 211615070919SJesper Dangaard Brouer u64_stats_update_end(&stats->syncp); 21177d51a015SLorenzo Bianconi } 2118b0a43db9SLorenzo Bianconi __netif_tx_unlock(nq); 2119b0a43db9SLorenzo Bianconi 2120b0a43db9SLorenzo Bianconi return ret; 2121b0a43db9SLorenzo Bianconi } 2122b0a43db9SLorenzo Bianconi 2123b0a43db9SLorenzo Bianconi static int 2124b0a43db9SLorenzo Bianconi mvneta_xdp_xmit(struct net_device *dev, int num_frame, 2125b0a43db9SLorenzo Bianconi struct xdp_frame **frames, u32 flags) 2126b0a43db9SLorenzo Bianconi { 2127b0a43db9SLorenzo Bianconi struct mvneta_port *pp = netdev_priv(dev); 21287d51a015SLorenzo Bianconi struct mvneta_pcpu_stats *stats = this_cpu_ptr(pp->stats); 21297d51a015SLorenzo Bianconi int i, nxmit_byte = 0, nxmit = num_frame; 2130b0a43db9SLorenzo Bianconi int cpu = smp_processor_id(); 2131b0a43db9SLorenzo Bianconi struct mvneta_tx_queue *txq; 2132b0a43db9SLorenzo Bianconi struct netdev_queue *nq; 2133b0a43db9SLorenzo Bianconi u32 ret; 2134b0a43db9SLorenzo Bianconi 213562a502ccSLorenzo Bianconi if (unlikely(test_bit(__MVNETA_DOWN, &pp->state))) 213662a502ccSLorenzo Bianconi return -ENETDOWN; 213762a502ccSLorenzo Bianconi 2138b0a43db9SLorenzo Bianconi if (unlikely(flags & ~XDP_XMIT_FLAGS_MASK)) 2139b0a43db9SLorenzo Bianconi return -EINVAL; 2140b0a43db9SLorenzo Bianconi 2141b0a43db9SLorenzo Bianconi txq = &pp->txqs[cpu % txq_number]; 2142b0a43db9SLorenzo Bianconi nq = netdev_get_tx_queue(pp->dev, txq->id); 2143b0a43db9SLorenzo Bianconi 2144b0a43db9SLorenzo Bianconi __netif_tx_lock(nq, cpu); 2145b0a43db9SLorenzo Bianconi for (i = 0; i < num_frame; i++) { 2146b0a43db9SLorenzo Bianconi ret = mvneta_xdp_submit_frame(pp, txq, frames[i], true); 21477d51a015SLorenzo Bianconi if (ret == MVNETA_XDP_TX) { 21487d51a015SLorenzo Bianconi nxmit_byte += frames[i]->len; 21497d51a015SLorenzo Bianconi } else { 2150b0a43db9SLorenzo Bianconi xdp_return_frame_rx_napi(frames[i]); 21517d51a015SLorenzo Bianconi nxmit--; 2152b0a43db9SLorenzo Bianconi } 2153b0a43db9SLorenzo Bianconi } 2154b0a43db9SLorenzo Bianconi 2155b0a43db9SLorenzo Bianconi if (unlikely(flags & XDP_XMIT_FLUSH)) 2156b0a43db9SLorenzo Bianconi mvneta_txq_pend_desc_add(pp, txq, 0); 2157b0a43db9SLorenzo Bianconi __netif_tx_unlock(nq); 2158b0a43db9SLorenzo Bianconi 21597d51a015SLorenzo Bianconi u64_stats_update_begin(&stats->syncp); 21607d51a015SLorenzo Bianconi stats->es.ps.tx_bytes += nxmit_byte; 21617d51a015SLorenzo Bianconi stats->es.ps.tx_packets += nxmit; 21627d51a015SLorenzo Bianconi stats->es.ps.xdp_xmit += nxmit; 216315070919SJesper Dangaard Brouer stats->es.ps.xdp_xmit_err += num_frame - nxmit; 21647d51a015SLorenzo Bianconi u64_stats_update_end(&stats->syncp); 21657d51a015SLorenzo Bianconi 21667d51a015SLorenzo Bianconi return nxmit; 2167b0a43db9SLorenzo Bianconi } 2168b0a43db9SLorenzo Bianconi 2169b0a43db9SLorenzo Bianconi static int 21700db51da7SLorenzo Bianconi mvneta_run_xdp(struct mvneta_port *pp, struct mvneta_rx_queue *rxq, 2171320d5441SLorenzo Bianconi struct bpf_prog *prog, struct xdp_buff *xdp, 21727d1643ebSLorenzo Bianconi u32 frame_sz, struct mvneta_stats *stats) 21730db51da7SLorenzo Bianconi { 21747d1643ebSLorenzo Bianconi unsigned int len, data_len, sync; 21758c4df83fSLorenzo Bianconi u32 ret, act; 21768c4df83fSLorenzo Bianconi 21778c4df83fSLorenzo Bianconi len = xdp->data_end - xdp->data_hard_start - pp->rx_offset_correction; 21787d1643ebSLorenzo Bianconi data_len = xdp->data_end - xdp->data; 21798c4df83fSLorenzo Bianconi act = bpf_prog_run_xdp(prog, xdp); 21800db51da7SLorenzo Bianconi 2181494f44d5SJesper Dangaard Brouer /* Due xdp_adjust_tail: DMA sync for_device cover max len CPU touch */ 2182494f44d5SJesper Dangaard Brouer sync = xdp->data_end - xdp->data_hard_start - pp->rx_offset_correction; 2183494f44d5SJesper Dangaard Brouer sync = max(sync, len); 2184494f44d5SJesper Dangaard Brouer 21850db51da7SLorenzo Bianconi switch (act) { 21860db51da7SLorenzo Bianconi case XDP_PASS: 21873d866523SLorenzo Bianconi stats->xdp_pass++; 2188320d5441SLorenzo Bianconi return MVNETA_XDP_PASS; 21890db51da7SLorenzo Bianconi case XDP_REDIRECT: { 21900db51da7SLorenzo Bianconi int err; 21910db51da7SLorenzo Bianconi 21920db51da7SLorenzo Bianconi err = xdp_do_redirect(pp->dev, xdp, prog); 219315070919SJesper Dangaard Brouer if (unlikely(err)) { 21947d1643ebSLorenzo Bianconi mvneta_xdp_put_buff(pp, rxq, xdp, sync, true); 21950db51da7SLorenzo Bianconi ret = MVNETA_XDP_DROPPED; 21960db51da7SLorenzo Bianconi } else { 21970db51da7SLorenzo Bianconi ret = MVNETA_XDP_REDIR; 21983d866523SLorenzo Bianconi stats->xdp_redirect++; 21990db51da7SLorenzo Bianconi } 22000db51da7SLorenzo Bianconi break; 22010db51da7SLorenzo Bianconi } 2202b0a43db9SLorenzo Bianconi case XDP_TX: 2203b0a43db9SLorenzo Bianconi ret = mvneta_xdp_xmit_back(pp, xdp); 22047d1643ebSLorenzo Bianconi if (ret != MVNETA_XDP_TX) 22057d1643ebSLorenzo Bianconi mvneta_xdp_put_buff(pp, rxq, xdp, sync, true); 2206b0a43db9SLorenzo Bianconi break; 22070db51da7SLorenzo Bianconi default: 22080db51da7SLorenzo Bianconi bpf_warn_invalid_xdp_action(act); 2209df561f66SGustavo A. R. Silva fallthrough; 22100db51da7SLorenzo Bianconi case XDP_ABORTED: 22110db51da7SLorenzo Bianconi trace_xdp_exception(pp->dev, prog, act); 2212df561f66SGustavo A. R. Silva fallthrough; 22130db51da7SLorenzo Bianconi case XDP_DROP: 22147d1643ebSLorenzo Bianconi mvneta_xdp_put_buff(pp, rxq, xdp, sync, true); 22150db51da7SLorenzo Bianconi ret = MVNETA_XDP_DROPPED; 22163d866523SLorenzo Bianconi stats->xdp_drop++; 22170db51da7SLorenzo Bianconi break; 22180db51da7SLorenzo Bianconi } 22190db51da7SLorenzo Bianconi 22207d1643ebSLorenzo Bianconi stats->rx_bytes += frame_sz + xdp->data_end - xdp->data - data_len; 2221320d5441SLorenzo Bianconi stats->rx_packets++; 2222320d5441SLorenzo Bianconi 22230db51da7SLorenzo Bianconi return ret; 22240db51da7SLorenzo Bianconi } 22250db51da7SLorenzo Bianconi 2226afda408bSLorenzo Bianconi static void 22278dc9a088SLorenzo Bianconi mvneta_swbm_rx_frame(struct mvneta_port *pp, 22288dc9a088SLorenzo Bianconi struct mvneta_rx_desc *rx_desc, 22298dc9a088SLorenzo Bianconi struct mvneta_rx_queue *rxq, 2230c7a3a8cdSLorenzo Bianconi struct xdp_buff *xdp, int *size, 22313a8c4ad1SLorenzo Bianconi struct page *page) 22328dc9a088SLorenzo Bianconi { 22338dc9a088SLorenzo Bianconi unsigned char *data = page_address(page); 22348dc9a088SLorenzo Bianconi int data_len = -MVNETA_MH_SIZE, len; 22358dc9a088SLorenzo Bianconi struct net_device *dev = pp->dev; 22368dc9a088SLorenzo Bianconi enum dma_data_direction dma_dir; 2237ca0e0146SLorenzo Bianconi struct skb_shared_info *sinfo; 22388dc9a088SLorenzo Bianconi 2239879456beSLorenzo Bianconi if (*size > MVNETA_MAX_RX_BUF_SIZE) { 22408dc9a088SLorenzo Bianconi len = MVNETA_MAX_RX_BUF_SIZE; 22418dc9a088SLorenzo Bianconi data_len += len; 22428dc9a088SLorenzo Bianconi } else { 2243879456beSLorenzo Bianconi len = *size; 22448dc9a088SLorenzo Bianconi data_len += len - ETH_FCS_LEN; 22458dc9a088SLorenzo Bianconi } 2246879456beSLorenzo Bianconi *size = *size - len; 22478dc9a088SLorenzo Bianconi 22488dc9a088SLorenzo Bianconi dma_dir = page_pool_get_dma_dir(rxq->page_pool); 22498dc9a088SLorenzo Bianconi dma_sync_single_for_cpu(dev->dev.parent, 22508dc9a088SLorenzo Bianconi rx_desc->buf_phys_addr, 22518dc9a088SLorenzo Bianconi len, dma_dir); 22528dc9a088SLorenzo Bianconi 2253879456beSLorenzo Bianconi rx_desc->buf_phys_addr = 0; 2254879456beSLorenzo Bianconi 2255fa383f6bSLorenzo Bianconi /* Prefetch header */ 2256fa383f6bSLorenzo Bianconi prefetch(data); 2257fa383f6bSLorenzo Bianconi 22580db51da7SLorenzo Bianconi xdp->data_hard_start = data; 2259b37fa92eSLorenzo Bianconi xdp->data = data + pp->rx_offset_correction + MVNETA_MH_SIZE; 22600db51da7SLorenzo Bianconi xdp->data_end = xdp->data + data_len; 22610db51da7SLorenzo Bianconi xdp_set_data_meta_invalid(xdp); 22620db51da7SLorenzo Bianconi 2263ca0e0146SLorenzo Bianconi sinfo = xdp_get_shared_info_from_buff(xdp); 2264ca0e0146SLorenzo Bianconi sinfo->nr_frags = 0; 22658dc9a088SLorenzo Bianconi } 22668dc9a088SLorenzo Bianconi 22678dc9a088SLorenzo Bianconi static void 22688dc9a088SLorenzo Bianconi mvneta_swbm_add_rx_fragment(struct mvneta_port *pp, 22698dc9a088SLorenzo Bianconi struct mvneta_rx_desc *rx_desc, 22708dc9a088SLorenzo Bianconi struct mvneta_rx_queue *rxq, 2271c7a3a8cdSLorenzo Bianconi struct xdp_buff *xdp, int *size, 22728dc9a088SLorenzo Bianconi struct page *page) 22738dc9a088SLorenzo Bianconi { 2274ca0e0146SLorenzo Bianconi struct skb_shared_info *sinfo = xdp_get_shared_info_from_buff(xdp); 22758dc9a088SLorenzo Bianconi struct net_device *dev = pp->dev; 22768dc9a088SLorenzo Bianconi enum dma_data_direction dma_dir; 22778dc9a088SLorenzo Bianconi int data_len, len; 22788dc9a088SLorenzo Bianconi 2279c7a3a8cdSLorenzo Bianconi if (*size > MVNETA_MAX_RX_BUF_SIZE) { 22808dc9a088SLorenzo Bianconi len = MVNETA_MAX_RX_BUF_SIZE; 22818dc9a088SLorenzo Bianconi data_len = len; 22828dc9a088SLorenzo Bianconi } else { 2283c7a3a8cdSLorenzo Bianconi len = *size; 22848dc9a088SLorenzo Bianconi data_len = len - ETH_FCS_LEN; 22858dc9a088SLorenzo Bianconi } 22868dc9a088SLorenzo Bianconi dma_dir = page_pool_get_dma_dir(rxq->page_pool); 22878dc9a088SLorenzo Bianconi dma_sync_single_for_cpu(dev->dev.parent, 22888dc9a088SLorenzo Bianconi rx_desc->buf_phys_addr, 22898dc9a088SLorenzo Bianconi len, dma_dir); 22909c79a8abSLorenzo Bianconi rx_desc->buf_phys_addr = 0; 2291ca0e0146SLorenzo Bianconi 2292ca0e0146SLorenzo Bianconi if (data_len > 0 && sinfo->nr_frags < MAX_SKB_FRAGS) { 2293ca0e0146SLorenzo Bianconi skb_frag_t *frag = &sinfo->frags[sinfo->nr_frags]; 2294ca0e0146SLorenzo Bianconi 2295ca0e0146SLorenzo Bianconi skb_frag_off_set(frag, pp->rx_offset_correction); 2296ca0e0146SLorenzo Bianconi skb_frag_size_set(frag, data_len); 2297ca0e0146SLorenzo Bianconi __skb_frag_set_page(frag, page); 2298ca0e0146SLorenzo Bianconi sinfo->nr_frags++; 22999c79a8abSLorenzo Bianconi } else { 23009c79a8abSLorenzo Bianconi page_pool_put_full_page(rxq->page_pool, page, true); 2301ca0e0146SLorenzo Bianconi } 2302c7a3a8cdSLorenzo Bianconi *size -= len; 23038dc9a088SLorenzo Bianconi } 23048dc9a088SLorenzo Bianconi 2305ca0e0146SLorenzo Bianconi static struct sk_buff * 2306ca0e0146SLorenzo Bianconi mvneta_swbm_build_skb(struct mvneta_port *pp, struct mvneta_rx_queue *rxq, 2307ca0e0146SLorenzo Bianconi struct xdp_buff *xdp, u32 desc_status) 2308ca0e0146SLorenzo Bianconi { 2309ca0e0146SLorenzo Bianconi struct skb_shared_info *sinfo = xdp_get_shared_info_from_buff(xdp); 2310ca0e0146SLorenzo Bianconi int i, num_frags = sinfo->nr_frags; 2311ca0e0146SLorenzo Bianconi struct sk_buff *skb; 2312ca0e0146SLorenzo Bianconi 2313ca0e0146SLorenzo Bianconi skb = build_skb(xdp->data_hard_start, PAGE_SIZE); 2314ca0e0146SLorenzo Bianconi if (!skb) 2315ca0e0146SLorenzo Bianconi return ERR_PTR(-ENOMEM); 2316ca0e0146SLorenzo Bianconi 2317ca0e0146SLorenzo Bianconi page_pool_release_page(rxq->page_pool, virt_to_page(xdp->data)); 2318ca0e0146SLorenzo Bianconi 2319ca0e0146SLorenzo Bianconi skb_reserve(skb, xdp->data - xdp->data_hard_start); 2320ca0e0146SLorenzo Bianconi skb_put(skb, xdp->data_end - xdp->data); 2321ca0e0146SLorenzo Bianconi mvneta_rx_csum(pp, desc_status, skb); 2322ca0e0146SLorenzo Bianconi 2323ca0e0146SLorenzo Bianconi for (i = 0; i < num_frags; i++) { 232452731441SLorenzo Bianconi skb_frag_t *frag = &sinfo->frags[i]; 2325ca0e0146SLorenzo Bianconi 2326ca0e0146SLorenzo Bianconi skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, 232752731441SLorenzo Bianconi skb_frag_page(frag), skb_frag_off(frag), 232852731441SLorenzo Bianconi skb_frag_size(frag), PAGE_SIZE); 232952731441SLorenzo Bianconi page_pool_release_page(rxq->page_pool, skb_frag_page(frag)); 2330ca0e0146SLorenzo Bianconi } 2331ca0e0146SLorenzo Bianconi 2332ca0e0146SLorenzo Bianconi return skb; 2333ca0e0146SLorenzo Bianconi } 2334ca0e0146SLorenzo Bianconi 2335dc35a10fSMarcin Wojtas /* Main rx processing when using software buffer management */ 23367a86f05fSAndrew Lunn static int mvneta_rx_swbm(struct napi_struct *napi, 2337562e2f46SYelena Krivosheev struct mvneta_port *pp, int budget, 2338c5aff182SThomas Petazzoni struct mvneta_rx_queue *rxq) 2339c5aff182SThomas Petazzoni { 2340c7a3a8cdSLorenzo Bianconi int rx_proc = 0, rx_todo, refill, size = 0; 2341c5aff182SThomas Petazzoni struct net_device *dev = pp->dev; 2342ca0e0146SLorenzo Bianconi struct xdp_buff xdp_buf = { 2343ca0e0146SLorenzo Bianconi .frame_sz = PAGE_SIZE, 2344ca0e0146SLorenzo Bianconi .rxq = &rxq->xdp_rxq, 2345ca0e0146SLorenzo Bianconi }; 2346320d5441SLorenzo Bianconi struct mvneta_stats ps = {}; 23470db51da7SLorenzo Bianconi struct bpf_prog *xdp_prog; 23487d1643ebSLorenzo Bianconi u32 desc_status, frame_sz; 2349c5aff182SThomas Petazzoni 2350c5aff182SThomas Petazzoni /* Get number of received packets */ 2351562e2f46SYelena Krivosheev rx_todo = mvneta_rxq_busy_desc_num_get(pp, rxq); 2352c5aff182SThomas Petazzoni 23530db51da7SLorenzo Bianconi rcu_read_lock(); 23540db51da7SLorenzo Bianconi xdp_prog = READ_ONCE(pp->xdp_prog); 23550db51da7SLorenzo Bianconi 2356c5aff182SThomas Petazzoni /* Fairness NAPI loop */ 23578dc9a088SLorenzo Bianconi while (rx_proc < budget && rx_proc < rx_todo) { 2358c5aff182SThomas Petazzoni struct mvneta_rx_desc *rx_desc = mvneta_rxq_next_desc_get(rxq); 23598dc9a088SLorenzo Bianconi u32 rx_status, index; 2360ca0e0146SLorenzo Bianconi struct sk_buff *skb; 23617e47fd84SGregory CLEMENT struct page *page; 2362c5aff182SThomas Petazzoni 2363f88bee1cSGregory CLEMENT index = rx_desc - rxq->descs; 23647e47fd84SGregory CLEMENT page = (struct page *)rxq->buf_virt_addr[index]; 2365c5aff182SThomas Petazzoni 2366562e2f46SYelena Krivosheev rx_status = rx_desc->status; 2367562e2f46SYelena Krivosheev rx_proc++; 2368562e2f46SYelena Krivosheev rxq->refill_num++; 2369562e2f46SYelena Krivosheev 2370562e2f46SYelena Krivosheev if (rx_status & MVNETA_RXD_FIRST_DESC) { 2371562e2f46SYelena Krivosheev /* Check errors only for FIRST descriptor */ 2372562e2f46SYelena Krivosheev if (rx_status & MVNETA_RXD_ERR_SUMMARY) { 23732eecb2e0SYelena Krivosheev mvneta_rx_error(pp, rx_desc); 2374ca0e0146SLorenzo Bianconi goto next; 2375c5aff182SThomas Petazzoni } 2376c5aff182SThomas Petazzoni 2377c7a3a8cdSLorenzo Bianconi size = rx_desc->data_size; 2378c7a3a8cdSLorenzo Bianconi frame_sz = size - ETH_FCS_LEN; 2379879456beSLorenzo Bianconi desc_status = rx_status; 23807d1643ebSLorenzo Bianconi 2381c7a3a8cdSLorenzo Bianconi mvneta_swbm_rx_frame(pp, rx_desc, rxq, &xdp_buf, 23823a8c4ad1SLorenzo Bianconi &size, page); 2383562e2f46SYelena Krivosheev } else { 2384b6e11785SLorenzo Bianconi if (unlikely(!xdp_buf.data_hard_start)) { 2385b6e11785SLorenzo Bianconi rx_desc->buf_phys_addr = 0; 2386b6e11785SLorenzo Bianconi page_pool_put_full_page(rxq->page_pool, page, 2387b6e11785SLorenzo Bianconi true); 2388562e2f46SYelena Krivosheev continue; 2389b6e11785SLorenzo Bianconi } 2390ca0e0146SLorenzo Bianconi 2391ca0e0146SLorenzo Bianconi mvneta_swbm_add_rx_fragment(pp, rx_desc, rxq, &xdp_buf, 2392c7a3a8cdSLorenzo Bianconi &size, page); 2393562e2f46SYelena Krivosheev } /* Middle or Last descriptor */ 2394562e2f46SYelena Krivosheev 2395562e2f46SYelena Krivosheev if (!(rx_status & MVNETA_RXD_LAST_DESC)) 2396562e2f46SYelena Krivosheev /* no last descriptor this time */ 2397562e2f46SYelena Krivosheev continue; 2398562e2f46SYelena Krivosheev 2399c7a3a8cdSLorenzo Bianconi if (size) { 2400ca0e0146SLorenzo Bianconi mvneta_xdp_put_buff(pp, rxq, &xdp_buf, -1, true); 2401ca0e0146SLorenzo Bianconi goto next; 2402562e2f46SYelena Krivosheev } 2403320d5441SLorenzo Bianconi 2404afda408bSLorenzo Bianconi if (xdp_prog && 24057d1643ebSLorenzo Bianconi mvneta_run_xdp(pp, rxq, xdp_prog, &xdp_buf, frame_sz, &ps)) 2406afda408bSLorenzo Bianconi goto next; 2407afda408bSLorenzo Bianconi 2408ca0e0146SLorenzo Bianconi skb = mvneta_swbm_build_skb(pp, rxq, &xdp_buf, desc_status); 2409ca0e0146SLorenzo Bianconi if (IS_ERR(skb)) { 2410ca0e0146SLorenzo Bianconi struct mvneta_pcpu_stats *stats = this_cpu_ptr(pp->stats); 2411ca0e0146SLorenzo Bianconi 2412ca0e0146SLorenzo Bianconi mvneta_xdp_put_buff(pp, rxq, &xdp_buf, -1, true); 2413ca0e0146SLorenzo Bianconi 2414ca0e0146SLorenzo Bianconi u64_stats_update_begin(&stats->syncp); 2415ca0e0146SLorenzo Bianconi stats->es.skb_alloc_error++; 2416ca0e0146SLorenzo Bianconi stats->rx_dropped++; 2417ca0e0146SLorenzo Bianconi u64_stats_update_end(&stats->syncp); 2418ca0e0146SLorenzo Bianconi 2419ca0e0146SLorenzo Bianconi goto next; 2420ca0e0146SLorenzo Bianconi } 2421ca0e0146SLorenzo Bianconi 2422ca0e0146SLorenzo Bianconi ps.rx_bytes += skb->len; 2423320d5441SLorenzo Bianconi ps.rx_packets++; 2424c5aff182SThomas Petazzoni 2425ca0e0146SLorenzo Bianconi skb->protocol = eth_type_trans(skb, dev); 2426ca0e0146SLorenzo Bianconi napi_gro_receive(napi, skb); 2427ca0e0146SLorenzo Bianconi next: 2428ca0e0146SLorenzo Bianconi xdp_buf.data_hard_start = NULL; 2429c5aff182SThomas Petazzoni } 24300db51da7SLorenzo Bianconi rcu_read_unlock(); 24310db51da7SLorenzo Bianconi 2432ca0e0146SLorenzo Bianconi if (xdp_buf.data_hard_start) 2433ca0e0146SLorenzo Bianconi mvneta_xdp_put_buff(pp, rxq, &xdp_buf, -1, true); 2434ca0e0146SLorenzo Bianconi 24356c8a8cfdSLorenzo Bianconi if (ps.xdp_redirect) 24360db51da7SLorenzo Bianconi xdp_do_flush_map(); 2437c5aff182SThomas Petazzoni 2438320d5441SLorenzo Bianconi if (ps.rx_packets) 2439320d5441SLorenzo Bianconi mvneta_update_stats(pp, &ps); 2440dc4277ddSwilly tarreau 2441562e2f46SYelena Krivosheev /* return some buffers to hardware queue, one at a time is too slow */ 2442562e2f46SYelena Krivosheev refill = mvneta_rx_refill_queue(pp, rxq); 2443c5aff182SThomas Petazzoni 2444562e2f46SYelena Krivosheev /* Update rxq management counters */ 2445562e2f46SYelena Krivosheev mvneta_rxq_desc_num_update(pp, rxq, rx_proc, refill); 2446562e2f46SYelena Krivosheev 2447320d5441SLorenzo Bianconi return ps.rx_packets; 2448c5aff182SThomas Petazzoni } 2449c5aff182SThomas Petazzoni 2450dc35a10fSMarcin Wojtas /* Main rx processing when using hardware buffer management */ 24517a86f05fSAndrew Lunn static int mvneta_rx_hwbm(struct napi_struct *napi, 24527a86f05fSAndrew Lunn struct mvneta_port *pp, int rx_todo, 2453dc35a10fSMarcin Wojtas struct mvneta_rx_queue *rxq) 2454dc35a10fSMarcin Wojtas { 2455dc35a10fSMarcin Wojtas struct net_device *dev = pp->dev; 2456dc35a10fSMarcin Wojtas int rx_done; 2457dc35a10fSMarcin Wojtas u32 rcvd_pkts = 0; 2458dc35a10fSMarcin Wojtas u32 rcvd_bytes = 0; 2459dc35a10fSMarcin Wojtas 2460dc35a10fSMarcin Wojtas /* Get number of received packets */ 2461dc35a10fSMarcin Wojtas rx_done = mvneta_rxq_busy_desc_num_get(pp, rxq); 2462dc35a10fSMarcin Wojtas 2463dc35a10fSMarcin Wojtas if (rx_todo > rx_done) 2464dc35a10fSMarcin Wojtas rx_todo = rx_done; 2465dc35a10fSMarcin Wojtas 2466dc35a10fSMarcin Wojtas rx_done = 0; 2467dc35a10fSMarcin Wojtas 2468dc35a10fSMarcin Wojtas /* Fairness NAPI loop */ 2469dc35a10fSMarcin Wojtas while (rx_done < rx_todo) { 2470dc35a10fSMarcin Wojtas struct mvneta_rx_desc *rx_desc = mvneta_rxq_next_desc_get(rxq); 2471dc35a10fSMarcin Wojtas struct mvneta_bm_pool *bm_pool = NULL; 2472dc35a10fSMarcin Wojtas struct sk_buff *skb; 2473dc35a10fSMarcin Wojtas unsigned char *data; 2474dc35a10fSMarcin Wojtas dma_addr_t phys_addr; 2475dc35a10fSMarcin Wojtas u32 rx_status, frag_size; 2476dc35a10fSMarcin Wojtas int rx_bytes, err; 2477dc35a10fSMarcin Wojtas u8 pool_id; 2478dc35a10fSMarcin Wojtas 2479dc35a10fSMarcin Wojtas rx_done++; 2480dc35a10fSMarcin Wojtas rx_status = rx_desc->status; 2481dc35a10fSMarcin Wojtas rx_bytes = rx_desc->data_size - (ETH_FCS_LEN + MVNETA_MH_SIZE); 2482f88bee1cSGregory CLEMENT data = (u8 *)(uintptr_t)rx_desc->buf_cookie; 2483dc35a10fSMarcin Wojtas phys_addr = rx_desc->buf_phys_addr; 2484dc35a10fSMarcin Wojtas pool_id = MVNETA_RX_GET_BM_POOL_ID(rx_desc); 2485dc35a10fSMarcin Wojtas bm_pool = &pp->bm_priv->bm_pools[pool_id]; 2486dc35a10fSMarcin Wojtas 2487dc35a10fSMarcin Wojtas if (!mvneta_rxq_desc_is_first_last(rx_status) || 2488dc35a10fSMarcin Wojtas (rx_status & MVNETA_RXD_ERR_SUMMARY)) { 2489dc35a10fSMarcin Wojtas err_drop_frame_ret_pool: 2490dc35a10fSMarcin Wojtas /* Return the buffer to the pool */ 2491dc35a10fSMarcin Wojtas mvneta_bm_pool_put_bp(pp->bm_priv, bm_pool, 2492dc35a10fSMarcin Wojtas rx_desc->buf_phys_addr); 2493dc35a10fSMarcin Wojtas err_drop_frame: 2494dc35a10fSMarcin Wojtas mvneta_rx_error(pp, rx_desc); 2495dc35a10fSMarcin Wojtas /* leave the descriptor untouched */ 2496dc35a10fSMarcin Wojtas continue; 2497dc35a10fSMarcin Wojtas } 2498dc35a10fSMarcin Wojtas 2499dc35a10fSMarcin Wojtas if (rx_bytes <= rx_copybreak) { 2500dc35a10fSMarcin Wojtas /* better copy a small frame and not unmap the DMA region */ 2501dc35a10fSMarcin Wojtas skb = netdev_alloc_skb_ip_align(dev, rx_bytes); 2502dc35a10fSMarcin Wojtas if (unlikely(!skb)) 2503dc35a10fSMarcin Wojtas goto err_drop_frame_ret_pool; 2504dc35a10fSMarcin Wojtas 2505a8fef9baSRussell King dma_sync_single_range_for_cpu(&pp->bm_priv->pdev->dev, 2506dc35a10fSMarcin Wojtas rx_desc->buf_phys_addr, 2507dc35a10fSMarcin Wojtas MVNETA_MH_SIZE + NET_SKB_PAD, 2508dc35a10fSMarcin Wojtas rx_bytes, 2509dc35a10fSMarcin Wojtas DMA_FROM_DEVICE); 251059ae1d12SJohannes Berg skb_put_data(skb, data + MVNETA_MH_SIZE + NET_SKB_PAD, 2511dc35a10fSMarcin Wojtas rx_bytes); 2512dc35a10fSMarcin Wojtas 2513dc35a10fSMarcin Wojtas skb->protocol = eth_type_trans(skb, dev); 2514dc35a10fSMarcin Wojtas mvneta_rx_csum(pp, rx_status, skb); 25157a86f05fSAndrew Lunn napi_gro_receive(napi, skb); 2516dc35a10fSMarcin Wojtas 2517dc35a10fSMarcin Wojtas rcvd_pkts++; 2518dc35a10fSMarcin Wojtas rcvd_bytes += rx_bytes; 2519dc35a10fSMarcin Wojtas 2520dc35a10fSMarcin Wojtas /* Return the buffer to the pool */ 2521dc35a10fSMarcin Wojtas mvneta_bm_pool_put_bp(pp->bm_priv, bm_pool, 2522dc35a10fSMarcin Wojtas rx_desc->buf_phys_addr); 2523dc35a10fSMarcin Wojtas 2524dc35a10fSMarcin Wojtas /* leave the descriptor and buffer untouched */ 2525dc35a10fSMarcin Wojtas continue; 2526dc35a10fSMarcin Wojtas } 2527dc35a10fSMarcin Wojtas 2528dc35a10fSMarcin Wojtas /* Refill processing */ 2529baa11ebcSGregory CLEMENT err = hwbm_pool_refill(&bm_pool->hwbm_pool, GFP_ATOMIC); 2530dc35a10fSMarcin Wojtas if (err) { 25319ac41f3cSLorenzo Bianconi struct mvneta_pcpu_stats *stats; 25329ac41f3cSLorenzo Bianconi 2533dc35a10fSMarcin Wojtas netdev_err(dev, "Linux processing - Can't refill\n"); 25349ac41f3cSLorenzo Bianconi 25359ac41f3cSLorenzo Bianconi stats = this_cpu_ptr(pp->stats); 25369ac41f3cSLorenzo Bianconi u64_stats_update_begin(&stats->syncp); 25379ac41f3cSLorenzo Bianconi stats->es.refill_error++; 25389ac41f3cSLorenzo Bianconi u64_stats_update_end(&stats->syncp); 25399ac41f3cSLorenzo Bianconi 2540dc35a10fSMarcin Wojtas goto err_drop_frame_ret_pool; 2541dc35a10fSMarcin Wojtas } 2542dc35a10fSMarcin Wojtas 2543baa11ebcSGregory CLEMENT frag_size = bm_pool->hwbm_pool.frag_size; 2544dc35a10fSMarcin Wojtas 2545dc35a10fSMarcin Wojtas skb = build_skb(data, frag_size > PAGE_SIZE ? 0 : frag_size); 2546dc35a10fSMarcin Wojtas 2547dc35a10fSMarcin Wojtas /* After refill old buffer has to be unmapped regardless 2548dc35a10fSMarcin Wojtas * the skb is successfully built or not. 2549dc35a10fSMarcin Wojtas */ 2550dc35a10fSMarcin Wojtas dma_unmap_single(&pp->bm_priv->pdev->dev, phys_addr, 2551dc35a10fSMarcin Wojtas bm_pool->buf_size, DMA_FROM_DEVICE); 2552dc35a10fSMarcin Wojtas if (!skb) 2553dc35a10fSMarcin Wojtas goto err_drop_frame; 2554dc35a10fSMarcin Wojtas 2555dc35a10fSMarcin Wojtas rcvd_pkts++; 2556dc35a10fSMarcin Wojtas rcvd_bytes += rx_bytes; 2557dc35a10fSMarcin Wojtas 2558dc35a10fSMarcin Wojtas /* Linux processing */ 2559dc35a10fSMarcin Wojtas skb_reserve(skb, MVNETA_MH_SIZE + NET_SKB_PAD); 2560dc35a10fSMarcin Wojtas skb_put(skb, rx_bytes); 2561dc35a10fSMarcin Wojtas 2562dc35a10fSMarcin Wojtas skb->protocol = eth_type_trans(skb, dev); 2563dc35a10fSMarcin Wojtas 2564dc35a10fSMarcin Wojtas mvneta_rx_csum(pp, rx_status, skb); 2565dc35a10fSMarcin Wojtas 25667a86f05fSAndrew Lunn napi_gro_receive(napi, skb); 2567dc35a10fSMarcin Wojtas } 2568dc35a10fSMarcin Wojtas 256969de66fcSLorenzo Bianconi if (rcvd_pkts) { 257069de66fcSLorenzo Bianconi struct mvneta_pcpu_stats *stats = this_cpu_ptr(pp->stats); 257169de66fcSLorenzo Bianconi 257269de66fcSLorenzo Bianconi u64_stats_update_begin(&stats->syncp); 2573320d5441SLorenzo Bianconi stats->es.ps.rx_packets += rcvd_pkts; 2574320d5441SLorenzo Bianconi stats->es.ps.rx_bytes += rcvd_bytes; 257569de66fcSLorenzo Bianconi u64_stats_update_end(&stats->syncp); 257669de66fcSLorenzo Bianconi } 2577dc35a10fSMarcin Wojtas 2578dc35a10fSMarcin Wojtas /* Update rxq management counters */ 2579dc35a10fSMarcin Wojtas mvneta_rxq_desc_num_update(pp, rxq, rx_done, rx_done); 2580dc35a10fSMarcin Wojtas 2581dc35a10fSMarcin Wojtas return rx_done; 2582dc35a10fSMarcin Wojtas } 2583dc35a10fSMarcin Wojtas 25842adb719dSEzequiel Garcia static inline void 25852adb719dSEzequiel Garcia mvneta_tso_put_hdr(struct sk_buff *skb, 25862adb719dSEzequiel Garcia struct mvneta_port *pp, struct mvneta_tx_queue *txq) 25872adb719dSEzequiel Garcia { 25882adb719dSEzequiel Garcia int hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb); 25899e58c8b4SLorenzo Bianconi struct mvneta_tx_buf *buf = &txq->buf[txq->txq_put_index]; 25909e58c8b4SLorenzo Bianconi struct mvneta_tx_desc *tx_desc; 25912adb719dSEzequiel Garcia 25922adb719dSEzequiel Garcia tx_desc = mvneta_txq_next_desc_get(txq); 25932adb719dSEzequiel Garcia tx_desc->data_size = hdr_len; 25942adb719dSEzequiel Garcia tx_desc->command = mvneta_skb_tx_csum(pp, skb); 25952adb719dSEzequiel Garcia tx_desc->command |= MVNETA_TXD_F_DESC; 25962adb719dSEzequiel Garcia tx_desc->buf_phys_addr = txq->tso_hdrs_phys + 25972adb719dSEzequiel Garcia txq->txq_put_index * TSO_HEADER_SIZE; 25989e58c8b4SLorenzo Bianconi buf->type = MVNETA_TYPE_SKB; 25999e58c8b4SLorenzo Bianconi buf->skb = NULL; 26009e58c8b4SLorenzo Bianconi 26012adb719dSEzequiel Garcia mvneta_txq_inc_put(txq); 26022adb719dSEzequiel Garcia } 26032adb719dSEzequiel Garcia 26042adb719dSEzequiel Garcia static inline int 26052adb719dSEzequiel Garcia mvneta_tso_put_data(struct net_device *dev, struct mvneta_tx_queue *txq, 26062adb719dSEzequiel Garcia struct sk_buff *skb, char *data, int size, 26072adb719dSEzequiel Garcia bool last_tcp, bool is_last) 26082adb719dSEzequiel Garcia { 26099e58c8b4SLorenzo Bianconi struct mvneta_tx_buf *buf = &txq->buf[txq->txq_put_index]; 26102adb719dSEzequiel Garcia struct mvneta_tx_desc *tx_desc; 26112adb719dSEzequiel Garcia 26122adb719dSEzequiel Garcia tx_desc = mvneta_txq_next_desc_get(txq); 26132adb719dSEzequiel Garcia tx_desc->data_size = size; 26142adb719dSEzequiel Garcia tx_desc->buf_phys_addr = dma_map_single(dev->dev.parent, data, 26152adb719dSEzequiel Garcia size, DMA_TO_DEVICE); 26162adb719dSEzequiel Garcia if (unlikely(dma_mapping_error(dev->dev.parent, 26172adb719dSEzequiel Garcia tx_desc->buf_phys_addr))) { 26182adb719dSEzequiel Garcia mvneta_txq_desc_put(txq); 26192adb719dSEzequiel Garcia return -ENOMEM; 26202adb719dSEzequiel Garcia } 26212adb719dSEzequiel Garcia 26222adb719dSEzequiel Garcia tx_desc->command = 0; 26239e58c8b4SLorenzo Bianconi buf->type = MVNETA_TYPE_SKB; 26249e58c8b4SLorenzo Bianconi buf->skb = NULL; 26252adb719dSEzequiel Garcia 26262adb719dSEzequiel Garcia if (last_tcp) { 26272adb719dSEzequiel Garcia /* last descriptor in the TCP packet */ 26282adb719dSEzequiel Garcia tx_desc->command = MVNETA_TXD_L_DESC; 26292adb719dSEzequiel Garcia 26302adb719dSEzequiel Garcia /* last descriptor in SKB */ 26312adb719dSEzequiel Garcia if (is_last) 26329e58c8b4SLorenzo Bianconi buf->skb = skb; 26332adb719dSEzequiel Garcia } 26342adb719dSEzequiel Garcia mvneta_txq_inc_put(txq); 26352adb719dSEzequiel Garcia return 0; 26362adb719dSEzequiel Garcia } 26372adb719dSEzequiel Garcia 26382adb719dSEzequiel Garcia static int mvneta_tx_tso(struct sk_buff *skb, struct net_device *dev, 26392adb719dSEzequiel Garcia struct mvneta_tx_queue *txq) 26402adb719dSEzequiel Garcia { 2641761b331cSEric Dumazet int hdr_len, total_len, data_left; 26422adb719dSEzequiel Garcia int desc_count = 0; 26432adb719dSEzequiel Garcia struct mvneta_port *pp = netdev_priv(dev); 26442adb719dSEzequiel Garcia struct tso_t tso; 26452adb719dSEzequiel Garcia int i; 26462adb719dSEzequiel Garcia 26472adb719dSEzequiel Garcia /* Count needed descriptors */ 26482adb719dSEzequiel Garcia if ((txq->count + tso_count_descs(skb)) >= txq->size) 26492adb719dSEzequiel Garcia return 0; 26502adb719dSEzequiel Garcia 26512adb719dSEzequiel Garcia if (skb_headlen(skb) < (skb_transport_offset(skb) + tcp_hdrlen(skb))) { 26522adb719dSEzequiel Garcia pr_info("*** Is this even possible???!?!?\n"); 26532adb719dSEzequiel Garcia return 0; 26542adb719dSEzequiel Garcia } 26552adb719dSEzequiel Garcia 26562adb719dSEzequiel Garcia /* Initialize the TSO handler, and prepare the first payload */ 2657761b331cSEric Dumazet hdr_len = tso_start(skb, &tso); 26582adb719dSEzequiel Garcia 26592adb719dSEzequiel Garcia total_len = skb->len - hdr_len; 26602adb719dSEzequiel Garcia while (total_len > 0) { 26612adb719dSEzequiel Garcia char *hdr; 26622adb719dSEzequiel Garcia 26632adb719dSEzequiel Garcia data_left = min_t(int, skb_shinfo(skb)->gso_size, total_len); 26642adb719dSEzequiel Garcia total_len -= data_left; 26652adb719dSEzequiel Garcia desc_count++; 26662adb719dSEzequiel Garcia 26672adb719dSEzequiel Garcia /* prepare packet headers: MAC + IP + TCP */ 26682adb719dSEzequiel Garcia hdr = txq->tso_hdrs + txq->txq_put_index * TSO_HEADER_SIZE; 26692adb719dSEzequiel Garcia tso_build_hdr(skb, hdr, &tso, data_left, total_len == 0); 26702adb719dSEzequiel Garcia 26712adb719dSEzequiel Garcia mvneta_tso_put_hdr(skb, pp, txq); 26722adb719dSEzequiel Garcia 26732adb719dSEzequiel Garcia while (data_left > 0) { 26742adb719dSEzequiel Garcia int size; 26752adb719dSEzequiel Garcia desc_count++; 26762adb719dSEzequiel Garcia 26772adb719dSEzequiel Garcia size = min_t(int, tso.size, data_left); 26782adb719dSEzequiel Garcia 26792adb719dSEzequiel Garcia if (mvneta_tso_put_data(dev, txq, skb, 26802adb719dSEzequiel Garcia tso.data, size, 26812adb719dSEzequiel Garcia size == data_left, 26822adb719dSEzequiel Garcia total_len == 0)) 26832adb719dSEzequiel Garcia goto err_release; 26842adb719dSEzequiel Garcia data_left -= size; 26852adb719dSEzequiel Garcia 26862adb719dSEzequiel Garcia tso_build_data(skb, &tso, size); 26872adb719dSEzequiel Garcia } 26882adb719dSEzequiel Garcia } 26892adb719dSEzequiel Garcia 26902adb719dSEzequiel Garcia return desc_count; 26912adb719dSEzequiel Garcia 26922adb719dSEzequiel Garcia err_release: 26932adb719dSEzequiel Garcia /* Release all used data descriptors; header descriptors must not 26942adb719dSEzequiel Garcia * be DMA-unmapped. 26952adb719dSEzequiel Garcia */ 26962adb719dSEzequiel Garcia for (i = desc_count - 1; i >= 0; i--) { 26972adb719dSEzequiel Garcia struct mvneta_tx_desc *tx_desc = txq->descs + i; 26982e3173a3SEzequiel Garcia if (!IS_TSO_HEADER(txq, tx_desc->buf_phys_addr)) 26992adb719dSEzequiel Garcia dma_unmap_single(pp->dev->dev.parent, 27002adb719dSEzequiel Garcia tx_desc->buf_phys_addr, 27012adb719dSEzequiel Garcia tx_desc->data_size, 27022adb719dSEzequiel Garcia DMA_TO_DEVICE); 27032adb719dSEzequiel Garcia mvneta_txq_desc_put(txq); 27042adb719dSEzequiel Garcia } 27052adb719dSEzequiel Garcia return 0; 27062adb719dSEzequiel Garcia } 27072adb719dSEzequiel Garcia 2708c5aff182SThomas Petazzoni /* Handle tx fragmentation processing */ 2709c5aff182SThomas Petazzoni static int mvneta_tx_frag_process(struct mvneta_port *pp, struct sk_buff *skb, 2710c5aff182SThomas Petazzoni struct mvneta_tx_queue *txq) 2711c5aff182SThomas Petazzoni { 2712c5aff182SThomas Petazzoni struct mvneta_tx_desc *tx_desc; 27133d4ea02fSEzequiel Garcia int i, nr_frags = skb_shinfo(skb)->nr_frags; 2714c5aff182SThomas Petazzoni 27153d4ea02fSEzequiel Garcia for (i = 0; i < nr_frags; i++) { 27169e58c8b4SLorenzo Bianconi struct mvneta_tx_buf *buf = &txq->buf[txq->txq_put_index]; 2717c5aff182SThomas Petazzoni skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 2718d7840976SMatthew Wilcox (Oracle) void *addr = skb_frag_address(frag); 2719c5aff182SThomas Petazzoni 2720c5aff182SThomas Petazzoni tx_desc = mvneta_txq_next_desc_get(txq); 2721d7840976SMatthew Wilcox (Oracle) tx_desc->data_size = skb_frag_size(frag); 2722c5aff182SThomas Petazzoni 2723c5aff182SThomas Petazzoni tx_desc->buf_phys_addr = 2724c5aff182SThomas Petazzoni dma_map_single(pp->dev->dev.parent, addr, 2725c5aff182SThomas Petazzoni tx_desc->data_size, DMA_TO_DEVICE); 2726c5aff182SThomas Petazzoni 2727c5aff182SThomas Petazzoni if (dma_mapping_error(pp->dev->dev.parent, 2728c5aff182SThomas Petazzoni tx_desc->buf_phys_addr)) { 2729c5aff182SThomas Petazzoni mvneta_txq_desc_put(txq); 2730c5aff182SThomas Petazzoni goto error; 2731c5aff182SThomas Petazzoni } 2732c5aff182SThomas Petazzoni 27333d4ea02fSEzequiel Garcia if (i == nr_frags - 1) { 2734c5aff182SThomas Petazzoni /* Last descriptor */ 2735c5aff182SThomas Petazzoni tx_desc->command = MVNETA_TXD_L_DESC | MVNETA_TXD_Z_PAD; 27369e58c8b4SLorenzo Bianconi buf->skb = skb; 2737c5aff182SThomas Petazzoni } else { 2738c5aff182SThomas Petazzoni /* Descriptor in the middle: Not First, Not Last */ 2739c5aff182SThomas Petazzoni tx_desc->command = 0; 27409e58c8b4SLorenzo Bianconi buf->skb = NULL; 2741c5aff182SThomas Petazzoni } 27429e58c8b4SLorenzo Bianconi buf->type = MVNETA_TYPE_SKB; 27433d4ea02fSEzequiel Garcia mvneta_txq_inc_put(txq); 2744c5aff182SThomas Petazzoni } 2745c5aff182SThomas Petazzoni 2746c5aff182SThomas Petazzoni return 0; 2747c5aff182SThomas Petazzoni 2748c5aff182SThomas Petazzoni error: 2749c5aff182SThomas Petazzoni /* Release all descriptors that were used to map fragments of 27506a20c175SThomas Petazzoni * this packet, as well as the corresponding DMA mappings 27516a20c175SThomas Petazzoni */ 2752c5aff182SThomas Petazzoni for (i = i - 1; i >= 0; i--) { 2753c5aff182SThomas Petazzoni tx_desc = txq->descs + i; 2754c5aff182SThomas Petazzoni dma_unmap_single(pp->dev->dev.parent, 2755c5aff182SThomas Petazzoni tx_desc->buf_phys_addr, 2756c5aff182SThomas Petazzoni tx_desc->data_size, 2757c5aff182SThomas Petazzoni DMA_TO_DEVICE); 2758c5aff182SThomas Petazzoni mvneta_txq_desc_put(txq); 2759c5aff182SThomas Petazzoni } 2760c5aff182SThomas Petazzoni 2761c5aff182SThomas Petazzoni return -ENOMEM; 2762c5aff182SThomas Petazzoni } 2763c5aff182SThomas Petazzoni 2764c5aff182SThomas Petazzoni /* Main tx processing */ 2765f03508ceSYueHaibing static netdev_tx_t mvneta_tx(struct sk_buff *skb, struct net_device *dev) 2766c5aff182SThomas Petazzoni { 2767c5aff182SThomas Petazzoni struct mvneta_port *pp = netdev_priv(dev); 2768ee40a116SWilly Tarreau u16 txq_id = skb_get_queue_mapping(skb); 2769ee40a116SWilly Tarreau struct mvneta_tx_queue *txq = &pp->txqs[txq_id]; 27709e58c8b4SLorenzo Bianconi struct mvneta_tx_buf *buf = &txq->buf[txq->txq_put_index]; 2771c5aff182SThomas Petazzoni struct mvneta_tx_desc *tx_desc; 27725f478b41SEric Dumazet int len = skb->len; 2773c5aff182SThomas Petazzoni int frags = 0; 2774c5aff182SThomas Petazzoni u32 tx_cmd; 2775c5aff182SThomas Petazzoni 2776c5aff182SThomas Petazzoni if (!netif_running(dev)) 2777c5aff182SThomas Petazzoni goto out; 2778c5aff182SThomas Petazzoni 27792adb719dSEzequiel Garcia if (skb_is_gso(skb)) { 27802adb719dSEzequiel Garcia frags = mvneta_tx_tso(skb, dev, txq); 27812adb719dSEzequiel Garcia goto out; 27822adb719dSEzequiel Garcia } 27832adb719dSEzequiel Garcia 2784c5aff182SThomas Petazzoni frags = skb_shinfo(skb)->nr_frags + 1; 2785c5aff182SThomas Petazzoni 2786c5aff182SThomas Petazzoni /* Get a descriptor for the first part of the packet */ 2787c5aff182SThomas Petazzoni tx_desc = mvneta_txq_next_desc_get(txq); 2788c5aff182SThomas Petazzoni 2789c5aff182SThomas Petazzoni tx_cmd = mvneta_skb_tx_csum(pp, skb); 2790c5aff182SThomas Petazzoni 2791c5aff182SThomas Petazzoni tx_desc->data_size = skb_headlen(skb); 2792c5aff182SThomas Petazzoni 2793c5aff182SThomas Petazzoni tx_desc->buf_phys_addr = dma_map_single(dev->dev.parent, skb->data, 2794c5aff182SThomas Petazzoni tx_desc->data_size, 2795c5aff182SThomas Petazzoni DMA_TO_DEVICE); 2796c5aff182SThomas Petazzoni if (unlikely(dma_mapping_error(dev->dev.parent, 2797c5aff182SThomas Petazzoni tx_desc->buf_phys_addr))) { 2798c5aff182SThomas Petazzoni mvneta_txq_desc_put(txq); 2799c5aff182SThomas Petazzoni frags = 0; 2800c5aff182SThomas Petazzoni goto out; 2801c5aff182SThomas Petazzoni } 2802c5aff182SThomas Petazzoni 28039e58c8b4SLorenzo Bianconi buf->type = MVNETA_TYPE_SKB; 2804c5aff182SThomas Petazzoni if (frags == 1) { 2805c5aff182SThomas Petazzoni /* First and Last descriptor */ 2806c5aff182SThomas Petazzoni tx_cmd |= MVNETA_TXD_FLZ_DESC; 2807c5aff182SThomas Petazzoni tx_desc->command = tx_cmd; 28089e58c8b4SLorenzo Bianconi buf->skb = skb; 2809c5aff182SThomas Petazzoni mvneta_txq_inc_put(txq); 2810c5aff182SThomas Petazzoni } else { 2811c5aff182SThomas Petazzoni /* First but not Last */ 2812c5aff182SThomas Petazzoni tx_cmd |= MVNETA_TXD_F_DESC; 28139e58c8b4SLorenzo Bianconi buf->skb = NULL; 2814c5aff182SThomas Petazzoni mvneta_txq_inc_put(txq); 2815c5aff182SThomas Petazzoni tx_desc->command = tx_cmd; 2816c5aff182SThomas Petazzoni /* Continue with other skb fragments */ 2817c5aff182SThomas Petazzoni if (mvneta_tx_frag_process(pp, skb, txq)) { 2818c5aff182SThomas Petazzoni dma_unmap_single(dev->dev.parent, 2819c5aff182SThomas Petazzoni tx_desc->buf_phys_addr, 2820c5aff182SThomas Petazzoni tx_desc->data_size, 2821c5aff182SThomas Petazzoni DMA_TO_DEVICE); 2822c5aff182SThomas Petazzoni mvneta_txq_desc_put(txq); 2823c5aff182SThomas Petazzoni frags = 0; 2824c5aff182SThomas Petazzoni goto out; 2825c5aff182SThomas Petazzoni } 2826c5aff182SThomas Petazzoni } 2827c5aff182SThomas Petazzoni 2828e19d2ddaSEzequiel Garcia out: 2829e19d2ddaSEzequiel Garcia if (frags > 0) { 2830e19d2ddaSEzequiel Garcia struct netdev_queue *nq = netdev_get_tx_queue(dev, txq_id); 283169de66fcSLorenzo Bianconi struct mvneta_pcpu_stats *stats = this_cpu_ptr(pp->stats); 2832e19d2ddaSEzequiel Garcia 2833a29b6235SMarcin Wojtas netdev_tx_sent_queue(nq, len); 2834a29b6235SMarcin Wojtas 2835c5aff182SThomas Petazzoni txq->count += frags; 28368eef5f97SEzequiel Garcia if (txq->count >= txq->tx_stop_threshold) 2837c5aff182SThomas Petazzoni netif_tx_stop_queue(nq); 2838c5aff182SThomas Petazzoni 28396b16f9eeSFlorian Westphal if (!netdev_xmit_more() || netif_xmit_stopped(nq) || 28402a90f7e1SSimon Guinot txq->pending + frags > MVNETA_TXQ_DEC_SENT_MASK) 28412a90f7e1SSimon Guinot mvneta_txq_pend_desc_add(pp, txq, frags); 28422a90f7e1SSimon Guinot else 28432a90f7e1SSimon Guinot txq->pending += frags; 28442a90f7e1SSimon Guinot 284569de66fcSLorenzo Bianconi u64_stats_update_begin(&stats->syncp); 2846320d5441SLorenzo Bianconi stats->es.ps.tx_bytes += len; 2847320d5441SLorenzo Bianconi stats->es.ps.tx_packets++; 284869de66fcSLorenzo Bianconi u64_stats_update_end(&stats->syncp); 2849c5aff182SThomas Petazzoni } else { 2850c5aff182SThomas Petazzoni dev->stats.tx_dropped++; 2851c5aff182SThomas Petazzoni dev_kfree_skb_any(skb); 2852c5aff182SThomas Petazzoni } 2853c5aff182SThomas Petazzoni 2854c5aff182SThomas Petazzoni return NETDEV_TX_OK; 2855c5aff182SThomas Petazzoni } 2856c5aff182SThomas Petazzoni 2857c5aff182SThomas Petazzoni 2858c5aff182SThomas Petazzoni /* Free tx resources, when resetting a port */ 2859c5aff182SThomas Petazzoni static void mvneta_txq_done_force(struct mvneta_port *pp, 2860c5aff182SThomas Petazzoni struct mvneta_tx_queue *txq) 2861c5aff182SThomas Petazzoni 2862c5aff182SThomas Petazzoni { 2863a29b6235SMarcin Wojtas struct netdev_queue *nq = netdev_get_tx_queue(pp->dev, txq->id); 2864c5aff182SThomas Petazzoni int tx_done = txq->count; 2865c5aff182SThomas Petazzoni 2866632bb64fSLorenzo Bianconi mvneta_txq_bufs_free(pp, txq, tx_done, nq, false); 2867c5aff182SThomas Petazzoni 2868c5aff182SThomas Petazzoni /* reset txq */ 2869c5aff182SThomas Petazzoni txq->count = 0; 2870c5aff182SThomas Petazzoni txq->txq_put_index = 0; 2871c5aff182SThomas Petazzoni txq->txq_get_index = 0; 2872c5aff182SThomas Petazzoni } 2873c5aff182SThomas Petazzoni 28746c498974Swilly tarreau /* Handle tx done - called in softirq context. The <cause_tx_done> argument 28756c498974Swilly tarreau * must be a valid cause according to MVNETA_TXQ_INTR_MASK_ALL. 28766c498974Swilly tarreau */ 28770713a86aSArnaud Ebalard static void mvneta_tx_done_gbe(struct mvneta_port *pp, u32 cause_tx_done) 2878c5aff182SThomas Petazzoni { 2879c5aff182SThomas Petazzoni struct mvneta_tx_queue *txq; 2880c5aff182SThomas Petazzoni struct netdev_queue *nq; 2881bd9f1ee3SJisheng Zhang int cpu = smp_processor_id(); 2882c5aff182SThomas Petazzoni 28836c498974Swilly tarreau while (cause_tx_done) { 2884c5aff182SThomas Petazzoni txq = mvneta_tx_done_policy(pp, cause_tx_done); 2885c5aff182SThomas Petazzoni 2886c5aff182SThomas Petazzoni nq = netdev_get_tx_queue(pp->dev, txq->id); 2887bd9f1ee3SJisheng Zhang __netif_tx_lock(nq, cpu); 2888c5aff182SThomas Petazzoni 28890713a86aSArnaud Ebalard if (txq->count) 28900713a86aSArnaud Ebalard mvneta_txq_done(pp, txq); 2891c5aff182SThomas Petazzoni 2892c5aff182SThomas Petazzoni __netif_tx_unlock(nq); 2893c5aff182SThomas Petazzoni cause_tx_done &= ~((1 << txq->id)); 2894c5aff182SThomas Petazzoni } 2895c5aff182SThomas Petazzoni } 2896c5aff182SThomas Petazzoni 28976a20c175SThomas Petazzoni /* Compute crc8 of the specified address, using a unique algorithm , 2898c5aff182SThomas Petazzoni * according to hw spec, different than generic crc8 algorithm 2899c5aff182SThomas Petazzoni */ 2900c5aff182SThomas Petazzoni static int mvneta_addr_crc(unsigned char *addr) 2901c5aff182SThomas Petazzoni { 2902c5aff182SThomas Petazzoni int crc = 0; 2903c5aff182SThomas Petazzoni int i; 2904c5aff182SThomas Petazzoni 2905c5aff182SThomas Petazzoni for (i = 0; i < ETH_ALEN; i++) { 2906c5aff182SThomas Petazzoni int j; 2907c5aff182SThomas Petazzoni 2908c5aff182SThomas Petazzoni crc = (crc ^ addr[i]) << 8; 2909c5aff182SThomas Petazzoni for (j = 7; j >= 0; j--) { 2910c5aff182SThomas Petazzoni if (crc & (0x100 << j)) 2911c5aff182SThomas Petazzoni crc ^= 0x107 << j; 2912c5aff182SThomas Petazzoni } 2913c5aff182SThomas Petazzoni } 2914c5aff182SThomas Petazzoni 2915c5aff182SThomas Petazzoni return crc; 2916c5aff182SThomas Petazzoni } 2917c5aff182SThomas Petazzoni 2918c5aff182SThomas Petazzoni /* This method controls the net device special MAC multicast support. 2919c5aff182SThomas Petazzoni * The Special Multicast Table for MAC addresses supports MAC of the form 2920c5aff182SThomas Petazzoni * 0x01-00-5E-00-00-XX (where XX is between 0x00 and 0xFF). 2921c5aff182SThomas Petazzoni * The MAC DA[7:0] bits are used as a pointer to the Special Multicast 2922c5aff182SThomas Petazzoni * Table entries in the DA-Filter table. This method set the Special 2923c5aff182SThomas Petazzoni * Multicast Table appropriate entry. 2924c5aff182SThomas Petazzoni */ 2925c5aff182SThomas Petazzoni static void mvneta_set_special_mcast_addr(struct mvneta_port *pp, 2926c5aff182SThomas Petazzoni unsigned char last_byte, 2927c5aff182SThomas Petazzoni int queue) 2928c5aff182SThomas Petazzoni { 2929c5aff182SThomas Petazzoni unsigned int smc_table_reg; 2930c5aff182SThomas Petazzoni unsigned int tbl_offset; 2931c5aff182SThomas Petazzoni unsigned int reg_offset; 2932c5aff182SThomas Petazzoni 2933c5aff182SThomas Petazzoni /* Register offset from SMC table base */ 2934c5aff182SThomas Petazzoni tbl_offset = (last_byte / 4); 2935c5aff182SThomas Petazzoni /* Entry offset within the above reg */ 2936c5aff182SThomas Petazzoni reg_offset = last_byte % 4; 2937c5aff182SThomas Petazzoni 2938c5aff182SThomas Petazzoni smc_table_reg = mvreg_read(pp, (MVNETA_DA_FILT_SPEC_MCAST 2939c5aff182SThomas Petazzoni + tbl_offset * 4)); 2940c5aff182SThomas Petazzoni 2941c5aff182SThomas Petazzoni if (queue == -1) 2942c5aff182SThomas Petazzoni smc_table_reg &= ~(0xff << (8 * reg_offset)); 2943c5aff182SThomas Petazzoni else { 2944c5aff182SThomas Petazzoni smc_table_reg &= ~(0xff << (8 * reg_offset)); 2945c5aff182SThomas Petazzoni smc_table_reg |= ((0x01 | (queue << 1)) << (8 * reg_offset)); 2946c5aff182SThomas Petazzoni } 2947c5aff182SThomas Petazzoni 2948c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_DA_FILT_SPEC_MCAST + tbl_offset * 4, 2949c5aff182SThomas Petazzoni smc_table_reg); 2950c5aff182SThomas Petazzoni } 2951c5aff182SThomas Petazzoni 2952c5aff182SThomas Petazzoni /* This method controls the network device Other MAC multicast support. 2953c5aff182SThomas Petazzoni * The Other Multicast Table is used for multicast of another type. 2954c5aff182SThomas Petazzoni * A CRC-8 is used as an index to the Other Multicast Table entries 2955c5aff182SThomas Petazzoni * in the DA-Filter table. 2956c5aff182SThomas Petazzoni * The method gets the CRC-8 value from the calling routine and 2957c5aff182SThomas Petazzoni * sets the Other Multicast Table appropriate entry according to the 2958c5aff182SThomas Petazzoni * specified CRC-8 . 2959c5aff182SThomas Petazzoni */ 2960c5aff182SThomas Petazzoni static void mvneta_set_other_mcast_addr(struct mvneta_port *pp, 2961c5aff182SThomas Petazzoni unsigned char crc8, 2962c5aff182SThomas Petazzoni int queue) 2963c5aff182SThomas Petazzoni { 2964c5aff182SThomas Petazzoni unsigned int omc_table_reg; 2965c5aff182SThomas Petazzoni unsigned int tbl_offset; 2966c5aff182SThomas Petazzoni unsigned int reg_offset; 2967c5aff182SThomas Petazzoni 2968c5aff182SThomas Petazzoni tbl_offset = (crc8 / 4) * 4; /* Register offset from OMC table base */ 2969c5aff182SThomas Petazzoni reg_offset = crc8 % 4; /* Entry offset within the above reg */ 2970c5aff182SThomas Petazzoni 2971c5aff182SThomas Petazzoni omc_table_reg = mvreg_read(pp, MVNETA_DA_FILT_OTH_MCAST + tbl_offset); 2972c5aff182SThomas Petazzoni 2973c5aff182SThomas Petazzoni if (queue == -1) { 2974c5aff182SThomas Petazzoni /* Clear accepts frame bit at specified Other DA table entry */ 2975c5aff182SThomas Petazzoni omc_table_reg &= ~(0xff << (8 * reg_offset)); 2976c5aff182SThomas Petazzoni } else { 2977c5aff182SThomas Petazzoni omc_table_reg &= ~(0xff << (8 * reg_offset)); 2978c5aff182SThomas Petazzoni omc_table_reg |= ((0x01 | (queue << 1)) << (8 * reg_offset)); 2979c5aff182SThomas Petazzoni } 2980c5aff182SThomas Petazzoni 2981c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_DA_FILT_OTH_MCAST + tbl_offset, omc_table_reg); 2982c5aff182SThomas Petazzoni } 2983c5aff182SThomas Petazzoni 2984c5aff182SThomas Petazzoni /* The network device supports multicast using two tables: 2985c5aff182SThomas Petazzoni * 1) Special Multicast Table for MAC addresses of the form 2986c5aff182SThomas Petazzoni * 0x01-00-5E-00-00-XX (where XX is between 0x00 and 0xFF). 2987c5aff182SThomas Petazzoni * The MAC DA[7:0] bits are used as a pointer to the Special Multicast 2988c5aff182SThomas Petazzoni * Table entries in the DA-Filter table. 2989c5aff182SThomas Petazzoni * 2) Other Multicast Table for multicast of another type. A CRC-8 value 2990c5aff182SThomas Petazzoni * is used as an index to the Other Multicast Table entries in the 2991c5aff182SThomas Petazzoni * DA-Filter table. 2992c5aff182SThomas Petazzoni */ 2993c5aff182SThomas Petazzoni static int mvneta_mcast_addr_set(struct mvneta_port *pp, unsigned char *p_addr, 2994c5aff182SThomas Petazzoni int queue) 2995c5aff182SThomas Petazzoni { 2996c5aff182SThomas Petazzoni unsigned char crc_result = 0; 2997c5aff182SThomas Petazzoni 2998c5aff182SThomas Petazzoni if (memcmp(p_addr, "\x01\x00\x5e\x00\x00", 5) == 0) { 2999c5aff182SThomas Petazzoni mvneta_set_special_mcast_addr(pp, p_addr[5], queue); 3000c5aff182SThomas Petazzoni return 0; 3001c5aff182SThomas Petazzoni } 3002c5aff182SThomas Petazzoni 3003c5aff182SThomas Petazzoni crc_result = mvneta_addr_crc(p_addr); 3004c5aff182SThomas Petazzoni if (queue == -1) { 3005c5aff182SThomas Petazzoni if (pp->mcast_count[crc_result] == 0) { 3006c5aff182SThomas Petazzoni netdev_info(pp->dev, "No valid Mcast for crc8=0x%02x\n", 3007c5aff182SThomas Petazzoni crc_result); 3008c5aff182SThomas Petazzoni return -EINVAL; 3009c5aff182SThomas Petazzoni } 3010c5aff182SThomas Petazzoni 3011c5aff182SThomas Petazzoni pp->mcast_count[crc_result]--; 3012c5aff182SThomas Petazzoni if (pp->mcast_count[crc_result] != 0) { 3013c5aff182SThomas Petazzoni netdev_info(pp->dev, 3014c5aff182SThomas Petazzoni "After delete there are %d valid Mcast for crc8=0x%02x\n", 3015c5aff182SThomas Petazzoni pp->mcast_count[crc_result], crc_result); 3016c5aff182SThomas Petazzoni return -EINVAL; 3017c5aff182SThomas Petazzoni } 3018c5aff182SThomas Petazzoni } else 3019c5aff182SThomas Petazzoni pp->mcast_count[crc_result]++; 3020c5aff182SThomas Petazzoni 3021c5aff182SThomas Petazzoni mvneta_set_other_mcast_addr(pp, crc_result, queue); 3022c5aff182SThomas Petazzoni 3023c5aff182SThomas Petazzoni return 0; 3024c5aff182SThomas Petazzoni } 3025c5aff182SThomas Petazzoni 3026c5aff182SThomas Petazzoni /* Configure Fitering mode of Ethernet port */ 3027c5aff182SThomas Petazzoni static void mvneta_rx_unicast_promisc_set(struct mvneta_port *pp, 3028c5aff182SThomas Petazzoni int is_promisc) 3029c5aff182SThomas Petazzoni { 3030c5aff182SThomas Petazzoni u32 port_cfg_reg, val; 3031c5aff182SThomas Petazzoni 3032c5aff182SThomas Petazzoni port_cfg_reg = mvreg_read(pp, MVNETA_PORT_CONFIG); 3033c5aff182SThomas Petazzoni 3034c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_TYPE_PRIO); 3035c5aff182SThomas Petazzoni 3036c5aff182SThomas Petazzoni /* Set / Clear UPM bit in port configuration register */ 3037c5aff182SThomas Petazzoni if (is_promisc) { 3038c5aff182SThomas Petazzoni /* Accept all Unicast addresses */ 3039c5aff182SThomas Petazzoni port_cfg_reg |= MVNETA_UNI_PROMISC_MODE; 3040c5aff182SThomas Petazzoni val |= MVNETA_FORCE_UNI; 3041c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_MAC_ADDR_LOW, 0xffff); 3042c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_MAC_ADDR_HIGH, 0xffffffff); 3043c5aff182SThomas Petazzoni } else { 3044c5aff182SThomas Petazzoni /* Reject all Unicast addresses */ 3045c5aff182SThomas Petazzoni port_cfg_reg &= ~MVNETA_UNI_PROMISC_MODE; 3046c5aff182SThomas Petazzoni val &= ~MVNETA_FORCE_UNI; 3047c5aff182SThomas Petazzoni } 3048c5aff182SThomas Petazzoni 3049c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_PORT_CONFIG, port_cfg_reg); 3050c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_TYPE_PRIO, val); 3051c5aff182SThomas Petazzoni } 3052c5aff182SThomas Petazzoni 3053c5aff182SThomas Petazzoni /* register unicast and multicast addresses */ 3054c5aff182SThomas Petazzoni static void mvneta_set_rx_mode(struct net_device *dev) 3055c5aff182SThomas Petazzoni { 3056c5aff182SThomas Petazzoni struct mvneta_port *pp = netdev_priv(dev); 3057c5aff182SThomas Petazzoni struct netdev_hw_addr *ha; 3058c5aff182SThomas Petazzoni 3059c5aff182SThomas Petazzoni if (dev->flags & IFF_PROMISC) { 3060c5aff182SThomas Petazzoni /* Accept all: Multicast + Unicast */ 3061c5aff182SThomas Petazzoni mvneta_rx_unicast_promisc_set(pp, 1); 306290b74c01SGregory CLEMENT mvneta_set_ucast_table(pp, pp->rxq_def); 306390b74c01SGregory CLEMENT mvneta_set_special_mcast_table(pp, pp->rxq_def); 306490b74c01SGregory CLEMENT mvneta_set_other_mcast_table(pp, pp->rxq_def); 3065c5aff182SThomas Petazzoni } else { 3066c5aff182SThomas Petazzoni /* Accept single Unicast */ 3067c5aff182SThomas Petazzoni mvneta_rx_unicast_promisc_set(pp, 0); 3068c5aff182SThomas Petazzoni mvneta_set_ucast_table(pp, -1); 306990b74c01SGregory CLEMENT mvneta_mac_addr_set(pp, dev->dev_addr, pp->rxq_def); 3070c5aff182SThomas Petazzoni 3071c5aff182SThomas Petazzoni if (dev->flags & IFF_ALLMULTI) { 3072c5aff182SThomas Petazzoni /* Accept all multicast */ 307390b74c01SGregory CLEMENT mvneta_set_special_mcast_table(pp, pp->rxq_def); 307490b74c01SGregory CLEMENT mvneta_set_other_mcast_table(pp, pp->rxq_def); 3075c5aff182SThomas Petazzoni } else { 3076c5aff182SThomas Petazzoni /* Accept only initialized multicast */ 3077c5aff182SThomas Petazzoni mvneta_set_special_mcast_table(pp, -1); 3078c5aff182SThomas Petazzoni mvneta_set_other_mcast_table(pp, -1); 3079c5aff182SThomas Petazzoni 3080c5aff182SThomas Petazzoni if (!netdev_mc_empty(dev)) { 3081c5aff182SThomas Petazzoni netdev_for_each_mc_addr(ha, dev) { 3082c5aff182SThomas Petazzoni mvneta_mcast_addr_set(pp, ha->addr, 308390b74c01SGregory CLEMENT pp->rxq_def); 3084c5aff182SThomas Petazzoni } 3085c5aff182SThomas Petazzoni } 3086c5aff182SThomas Petazzoni } 3087c5aff182SThomas Petazzoni } 3088c5aff182SThomas Petazzoni } 3089c5aff182SThomas Petazzoni 3090c5aff182SThomas Petazzoni /* Interrupt handling - the callback for request_irq() */ 3091c5aff182SThomas Petazzoni static irqreturn_t mvneta_isr(int irq, void *dev_id) 3092c5aff182SThomas Petazzoni { 30932636ac3cSMarcin Wojtas struct mvneta_port *pp = (struct mvneta_port *)dev_id; 30942636ac3cSMarcin Wojtas 30952636ac3cSMarcin Wojtas mvreg_write(pp, MVNETA_INTR_NEW_MASK, 0); 30962636ac3cSMarcin Wojtas napi_schedule(&pp->napi); 30972636ac3cSMarcin Wojtas 30982636ac3cSMarcin Wojtas return IRQ_HANDLED; 30992636ac3cSMarcin Wojtas } 31002636ac3cSMarcin Wojtas 31012636ac3cSMarcin Wojtas /* Interrupt handling - the callback for request_percpu_irq() */ 31022636ac3cSMarcin Wojtas static irqreturn_t mvneta_percpu_isr(int irq, void *dev_id) 31032636ac3cSMarcin Wojtas { 310412bb03b4SMaxime Ripard struct mvneta_pcpu_port *port = (struct mvneta_pcpu_port *)dev_id; 3105c5aff182SThomas Petazzoni 310612bb03b4SMaxime Ripard disable_percpu_irq(port->pp->dev->irq); 310712bb03b4SMaxime Ripard napi_schedule(&port->napi); 3108c5aff182SThomas Petazzoni 3109c5aff182SThomas Petazzoni return IRQ_HANDLED; 3110c5aff182SThomas Petazzoni } 3111c5aff182SThomas Petazzoni 3112503f9aa9SRussell King static void mvneta_link_change(struct mvneta_port *pp) 3113898b2970SStas Sergeev { 3114898b2970SStas Sergeev u32 gmac_stat = mvreg_read(pp, MVNETA_GMAC_STATUS); 3115898b2970SStas Sergeev 3116503f9aa9SRussell King phylink_mac_change(pp->phylink, !!(gmac_stat & MVNETA_GMAC_LINK_UP)); 3117898b2970SStas Sergeev } 3118898b2970SStas Sergeev 3119c5aff182SThomas Petazzoni /* NAPI handler 3120c5aff182SThomas Petazzoni * Bits 0 - 7 of the causeRxTx register indicate that are transmitted 3121c5aff182SThomas Petazzoni * packets on the corresponding TXQ (Bit 0 is for TX queue 1). 3122c5aff182SThomas Petazzoni * Bits 8 -15 of the cause Rx Tx register indicate that are received 3123c5aff182SThomas Petazzoni * packets on the corresponding RXQ (Bit 8 is for RX queue 0). 3124c5aff182SThomas Petazzoni * Each CPU has its own causeRxTx register 3125c5aff182SThomas Petazzoni */ 3126c5aff182SThomas Petazzoni static int mvneta_poll(struct napi_struct *napi, int budget) 3127c5aff182SThomas Petazzoni { 3128c5aff182SThomas Petazzoni int rx_done = 0; 3129c5aff182SThomas Petazzoni u32 cause_rx_tx; 31302dcf75e2SGregory CLEMENT int rx_queue; 3131c5aff182SThomas Petazzoni struct mvneta_port *pp = netdev_priv(napi->dev); 313212bb03b4SMaxime Ripard struct mvneta_pcpu_port *port = this_cpu_ptr(pp->ports); 3133c5aff182SThomas Petazzoni 3134c5aff182SThomas Petazzoni if (!netif_running(pp->dev)) { 31352636ac3cSMarcin Wojtas napi_complete(napi); 3136c5aff182SThomas Petazzoni return rx_done; 3137c5aff182SThomas Petazzoni } 3138c5aff182SThomas Petazzoni 3139c5aff182SThomas Petazzoni /* Read cause register */ 3140898b2970SStas Sergeev cause_rx_tx = mvreg_read(pp, MVNETA_INTR_NEW_CAUSE); 3141898b2970SStas Sergeev if (cause_rx_tx & MVNETA_MISCINTR_INTR_MASK) { 3142898b2970SStas Sergeev u32 cause_misc = mvreg_read(pp, MVNETA_INTR_MISC_CAUSE); 3143898b2970SStas Sergeev 3144898b2970SStas Sergeev mvreg_write(pp, MVNETA_INTR_MISC_CAUSE, 0); 3145503f9aa9SRussell King 3146503f9aa9SRussell King if (cause_misc & (MVNETA_CAUSE_PHY_STATUS_CHANGE | 3147856b2cc5SRussell King MVNETA_CAUSE_LINK_CHANGE)) 3148503f9aa9SRussell King mvneta_link_change(pp); 3149898b2970SStas Sergeev } 315071f6d1b3Swilly tarreau 315171f6d1b3Swilly tarreau /* Release Tx descriptors */ 315271f6d1b3Swilly tarreau if (cause_rx_tx & MVNETA_TX_INTR_MASK_ALL) { 31530713a86aSArnaud Ebalard mvneta_tx_done_gbe(pp, (cause_rx_tx & MVNETA_TX_INTR_MASK_ALL)); 315471f6d1b3Swilly tarreau cause_rx_tx &= ~MVNETA_TX_INTR_MASK_ALL; 315571f6d1b3Swilly tarreau } 3156c5aff182SThomas Petazzoni 31576a20c175SThomas Petazzoni /* For the case where the last mvneta_poll did not process all 3158c5aff182SThomas Petazzoni * RX packets 3159c5aff182SThomas Petazzoni */ 31602636ac3cSMarcin Wojtas cause_rx_tx |= pp->neta_armada3700 ? pp->cause_rx_tx : 31612636ac3cSMarcin Wojtas port->cause_rx_tx; 31622dcf75e2SGregory CLEMENT 3163065fd83eSJisheng Zhang rx_queue = fls(((cause_rx_tx >> 8) & 0xff)); 31642dcf75e2SGregory CLEMENT if (rx_queue) { 31652dcf75e2SGregory CLEMENT rx_queue = rx_queue - 1; 3166dc35a10fSMarcin Wojtas if (pp->bm_priv) 31677a86f05fSAndrew Lunn rx_done = mvneta_rx_hwbm(napi, pp, budget, 31687a86f05fSAndrew Lunn &pp->rxqs[rx_queue]); 3169dc35a10fSMarcin Wojtas else 31707a86f05fSAndrew Lunn rx_done = mvneta_rx_swbm(napi, pp, budget, 31717a86f05fSAndrew Lunn &pp->rxqs[rx_queue]); 31722dcf75e2SGregory CLEMENT } 31732dcf75e2SGregory CLEMENT 31746ad20165SEric Dumazet if (rx_done < budget) { 3175c5aff182SThomas Petazzoni cause_rx_tx = 0; 31766ad20165SEric Dumazet napi_complete_done(napi, rx_done); 31772636ac3cSMarcin Wojtas 31782636ac3cSMarcin Wojtas if (pp->neta_armada3700) { 31792636ac3cSMarcin Wojtas unsigned long flags; 31802636ac3cSMarcin Wojtas 31812636ac3cSMarcin Wojtas local_irq_save(flags); 31822636ac3cSMarcin Wojtas mvreg_write(pp, MVNETA_INTR_NEW_MASK, 31832636ac3cSMarcin Wojtas MVNETA_RX_INTR_MASK(rxq_number) | 31842636ac3cSMarcin Wojtas MVNETA_TX_INTR_MASK(txq_number) | 31852636ac3cSMarcin Wojtas MVNETA_MISCINTR_INTR_MASK); 31862636ac3cSMarcin Wojtas local_irq_restore(flags); 31872636ac3cSMarcin Wojtas } else { 318812bb03b4SMaxime Ripard enable_percpu_irq(pp->dev->irq, 0); 3189c5aff182SThomas Petazzoni } 31902636ac3cSMarcin Wojtas } 3191c5aff182SThomas Petazzoni 31922636ac3cSMarcin Wojtas if (pp->neta_armada3700) 31932636ac3cSMarcin Wojtas pp->cause_rx_tx = cause_rx_tx; 31942636ac3cSMarcin Wojtas else 319512bb03b4SMaxime Ripard port->cause_rx_tx = cause_rx_tx; 31962636ac3cSMarcin Wojtas 3197c5aff182SThomas Petazzoni return rx_done; 3198c5aff182SThomas Petazzoni } 3199c5aff182SThomas Petazzoni 3200568a3fa2SLorenzo Bianconi static int mvneta_create_page_pool(struct mvneta_port *pp, 3201568a3fa2SLorenzo Bianconi struct mvneta_rx_queue *rxq, int size) 3202568a3fa2SLorenzo Bianconi { 32030db51da7SLorenzo Bianconi struct bpf_prog *xdp_prog = READ_ONCE(pp->xdp_prog); 3204568a3fa2SLorenzo Bianconi struct page_pool_params pp_params = { 3205568a3fa2SLorenzo Bianconi .order = 0, 320607e13edbSLorenzo Bianconi .flags = PP_FLAG_DMA_MAP | PP_FLAG_DMA_SYNC_DEV, 3207568a3fa2SLorenzo Bianconi .pool_size = size, 32081657adccSLorenzo Bianconi .nid = NUMA_NO_NODE, 3209568a3fa2SLorenzo Bianconi .dev = pp->dev->dev.parent, 32100db51da7SLorenzo Bianconi .dma_dir = xdp_prog ? DMA_BIDIRECTIONAL : DMA_FROM_DEVICE, 321107e13edbSLorenzo Bianconi .offset = pp->rx_offset_correction, 321207e13edbSLorenzo Bianconi .max_len = MVNETA_MAX_RX_BUF_SIZE, 3213568a3fa2SLorenzo Bianconi }; 3214568a3fa2SLorenzo Bianconi int err; 3215568a3fa2SLorenzo Bianconi 3216568a3fa2SLorenzo Bianconi rxq->page_pool = page_pool_create(&pp_params); 3217568a3fa2SLorenzo Bianconi if (IS_ERR(rxq->page_pool)) { 3218568a3fa2SLorenzo Bianconi err = PTR_ERR(rxq->page_pool); 3219568a3fa2SLorenzo Bianconi rxq->page_pool = NULL; 3220568a3fa2SLorenzo Bianconi return err; 3221568a3fa2SLorenzo Bianconi } 3222568a3fa2SLorenzo Bianconi 3223568a3fa2SLorenzo Bianconi err = xdp_rxq_info_reg(&rxq->xdp_rxq, pp->dev, rxq->id); 3224568a3fa2SLorenzo Bianconi if (err < 0) 3225568a3fa2SLorenzo Bianconi goto err_free_pp; 3226568a3fa2SLorenzo Bianconi 3227568a3fa2SLorenzo Bianconi err = xdp_rxq_info_reg_mem_model(&rxq->xdp_rxq, MEM_TYPE_PAGE_POOL, 3228568a3fa2SLorenzo Bianconi rxq->page_pool); 3229568a3fa2SLorenzo Bianconi if (err) 3230568a3fa2SLorenzo Bianconi goto err_unregister_rxq; 3231568a3fa2SLorenzo Bianconi 3232568a3fa2SLorenzo Bianconi return 0; 3233568a3fa2SLorenzo Bianconi 3234568a3fa2SLorenzo Bianconi err_unregister_rxq: 3235568a3fa2SLorenzo Bianconi xdp_rxq_info_unreg(&rxq->xdp_rxq); 3236568a3fa2SLorenzo Bianconi err_free_pp: 3237568a3fa2SLorenzo Bianconi page_pool_destroy(rxq->page_pool); 3238568a3fa2SLorenzo Bianconi rxq->page_pool = NULL; 3239568a3fa2SLorenzo Bianconi return err; 3240568a3fa2SLorenzo Bianconi } 3241568a3fa2SLorenzo Bianconi 3242c5aff182SThomas Petazzoni /* Handle rxq fill: allocates rxq skbs; called when initializing a port */ 3243c5aff182SThomas Petazzoni static int mvneta_rxq_fill(struct mvneta_port *pp, struct mvneta_rx_queue *rxq, 3244c5aff182SThomas Petazzoni int num) 3245c5aff182SThomas Petazzoni { 3246568a3fa2SLorenzo Bianconi int i, err; 3247568a3fa2SLorenzo Bianconi 3248568a3fa2SLorenzo Bianconi err = mvneta_create_page_pool(pp, rxq, num); 3249568a3fa2SLorenzo Bianconi if (err < 0) 3250568a3fa2SLorenzo Bianconi return err; 3251c5aff182SThomas Petazzoni 3252c5aff182SThomas Petazzoni for (i = 0; i < num; i++) { 3253a1a65ab1Swilly tarreau memset(rxq->descs + i, 0, sizeof(struct mvneta_rx_desc)); 32547e47fd84SGregory CLEMENT if (mvneta_rx_refill(pp, rxq->descs + i, rxq, 32557e47fd84SGregory CLEMENT GFP_KERNEL) != 0) { 32567e47fd84SGregory CLEMENT netdev_err(pp->dev, 32577e47fd84SGregory CLEMENT "%s:rxq %d, %d of %d buffs filled\n", 3258c5aff182SThomas Petazzoni __func__, rxq->id, i, num); 3259c5aff182SThomas Petazzoni break; 3260c5aff182SThomas Petazzoni } 3261c5aff182SThomas Petazzoni } 3262c5aff182SThomas Petazzoni 3263c5aff182SThomas Petazzoni /* Add this number of RX descriptors as non occupied (ready to 32646a20c175SThomas Petazzoni * get packets) 32656a20c175SThomas Petazzoni */ 3266c5aff182SThomas Petazzoni mvneta_rxq_non_occup_desc_add(pp, rxq, i); 3267c5aff182SThomas Petazzoni 3268c5aff182SThomas Petazzoni return i; 3269c5aff182SThomas Petazzoni } 3270c5aff182SThomas Petazzoni 3271c5aff182SThomas Petazzoni /* Free all packets pending transmit from all TXQs and reset TX port */ 3272c5aff182SThomas Petazzoni static void mvneta_tx_reset(struct mvneta_port *pp) 3273c5aff182SThomas Petazzoni { 3274c5aff182SThomas Petazzoni int queue; 3275c5aff182SThomas Petazzoni 32769672850bSEzequiel Garcia /* free the skb's in the tx ring */ 3277c5aff182SThomas Petazzoni for (queue = 0; queue < txq_number; queue++) 3278c5aff182SThomas Petazzoni mvneta_txq_done_force(pp, &pp->txqs[queue]); 3279c5aff182SThomas Petazzoni 3280c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_PORT_TX_RESET, MVNETA_PORT_TX_DMA_RESET); 3281c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_PORT_TX_RESET, 0); 3282c5aff182SThomas Petazzoni } 3283c5aff182SThomas Petazzoni 3284c5aff182SThomas Petazzoni static void mvneta_rx_reset(struct mvneta_port *pp) 3285c5aff182SThomas Petazzoni { 3286c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_PORT_RX_RESET, MVNETA_PORT_RX_DMA_RESET); 3287c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_PORT_RX_RESET, 0); 3288c5aff182SThomas Petazzoni } 3289c5aff182SThomas Petazzoni 3290c5aff182SThomas Petazzoni /* Rx/Tx queue initialization/cleanup methods */ 3291c5aff182SThomas Petazzoni 32924a188a63SJisheng Zhang static int mvneta_rxq_sw_init(struct mvneta_port *pp, 3293c5aff182SThomas Petazzoni struct mvneta_rx_queue *rxq) 3294c5aff182SThomas Petazzoni { 3295c5aff182SThomas Petazzoni rxq->size = pp->rx_ring_size; 3296c5aff182SThomas Petazzoni 3297c5aff182SThomas Petazzoni /* Allocate memory for RX descriptors */ 3298c5aff182SThomas Petazzoni rxq->descs = dma_alloc_coherent(pp->dev->dev.parent, 3299c5aff182SThomas Petazzoni rxq->size * MVNETA_DESC_ALIGNED_SIZE, 3300c5aff182SThomas Petazzoni &rxq->descs_phys, GFP_KERNEL); 3301f95936ccSMarkus Elfring if (!rxq->descs) 3302c5aff182SThomas Petazzoni return -ENOMEM; 3303c5aff182SThomas Petazzoni 3304c5aff182SThomas Petazzoni rxq->last_desc = rxq->size - 1; 3305c5aff182SThomas Petazzoni 33064a188a63SJisheng Zhang return 0; 33074a188a63SJisheng Zhang } 33084a188a63SJisheng Zhang 33094a188a63SJisheng Zhang static void mvneta_rxq_hw_init(struct mvneta_port *pp, 33104a188a63SJisheng Zhang struct mvneta_rx_queue *rxq) 33114a188a63SJisheng Zhang { 3312c5aff182SThomas Petazzoni /* Set Rx descriptors queue starting address */ 3313c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_RXQ_BASE_ADDR_REG(rxq->id), rxq->descs_phys); 3314c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_RXQ_SIZE_REG(rxq->id), rxq->size); 3315c5aff182SThomas Petazzoni 3316c5aff182SThomas Petazzoni /* Set coalescing pkts and time */ 3317c5aff182SThomas Petazzoni mvneta_rx_pkts_coal_set(pp, rxq, rxq->pkts_coal); 3318c5aff182SThomas Petazzoni mvneta_rx_time_coal_set(pp, rxq, rxq->time_coal); 3319c5aff182SThomas Petazzoni 3320dc35a10fSMarcin Wojtas if (!pp->bm_priv) { 3321562e2f46SYelena Krivosheev /* Set Offset */ 3322562e2f46SYelena Krivosheev mvneta_rxq_offset_set(pp, rxq, 0); 3323e735fd55SMarcin Wojtas mvneta_rxq_buf_size_set(pp, rxq, PAGE_SIZE < SZ_64K ? 33248dc9a088SLorenzo Bianconi MVNETA_MAX_RX_BUF_SIZE : 3325e735fd55SMarcin Wojtas MVNETA_RX_BUF_SIZE(pp->pkt_size)); 3326c5aff182SThomas Petazzoni mvneta_rxq_bm_disable(pp, rxq); 3327e9f64999SGregory CLEMENT mvneta_rxq_fill(pp, rxq, rxq->size); 3328dc35a10fSMarcin Wojtas } else { 3329562e2f46SYelena Krivosheev /* Set Offset */ 3330562e2f46SYelena Krivosheev mvneta_rxq_offset_set(pp, rxq, 3331562e2f46SYelena Krivosheev NET_SKB_PAD - pp->rx_offset_correction); 3332562e2f46SYelena Krivosheev 3333dc35a10fSMarcin Wojtas mvneta_rxq_bm_enable(pp, rxq); 3334562e2f46SYelena Krivosheev /* Fill RXQ with buffers from RX pool */ 3335dc35a10fSMarcin Wojtas mvneta_rxq_long_pool_set(pp, rxq); 3336dc35a10fSMarcin Wojtas mvneta_rxq_short_pool_set(pp, rxq); 3337e9f64999SGregory CLEMENT mvneta_rxq_non_occup_desc_add(pp, rxq, rxq->size); 3338dc35a10fSMarcin Wojtas } 33394a188a63SJisheng Zhang } 33404a188a63SJisheng Zhang 33414a188a63SJisheng Zhang /* Create a specified RX queue */ 33424a188a63SJisheng Zhang static int mvneta_rxq_init(struct mvneta_port *pp, 33434a188a63SJisheng Zhang struct mvneta_rx_queue *rxq) 33444a188a63SJisheng Zhang 33454a188a63SJisheng Zhang { 33464a188a63SJisheng Zhang int ret; 33474a188a63SJisheng Zhang 33484a188a63SJisheng Zhang ret = mvneta_rxq_sw_init(pp, rxq); 33494a188a63SJisheng Zhang if (ret < 0) 33504a188a63SJisheng Zhang return ret; 33514a188a63SJisheng Zhang 33524a188a63SJisheng Zhang mvneta_rxq_hw_init(pp, rxq); 3353dc35a10fSMarcin Wojtas 3354c5aff182SThomas Petazzoni return 0; 3355c5aff182SThomas Petazzoni } 3356c5aff182SThomas Petazzoni 3357c5aff182SThomas Petazzoni /* Cleanup Rx queue */ 3358c5aff182SThomas Petazzoni static void mvneta_rxq_deinit(struct mvneta_port *pp, 3359c5aff182SThomas Petazzoni struct mvneta_rx_queue *rxq) 3360c5aff182SThomas Petazzoni { 3361c5aff182SThomas Petazzoni mvneta_rxq_drop_pkts(pp, rxq); 3362c5aff182SThomas Petazzoni 3363c5aff182SThomas Petazzoni if (rxq->descs) 3364c5aff182SThomas Petazzoni dma_free_coherent(pp->dev->dev.parent, 3365c5aff182SThomas Petazzoni rxq->size * MVNETA_DESC_ALIGNED_SIZE, 3366c5aff182SThomas Petazzoni rxq->descs, 3367c5aff182SThomas Petazzoni rxq->descs_phys); 3368c5aff182SThomas Petazzoni 3369c5aff182SThomas Petazzoni rxq->descs = NULL; 3370c5aff182SThomas Petazzoni rxq->last_desc = 0; 3371c5aff182SThomas Petazzoni rxq->next_desc_to_proc = 0; 3372c5aff182SThomas Petazzoni rxq->descs_phys = 0; 3373562e2f46SYelena Krivosheev rxq->first_to_refill = 0; 3374562e2f46SYelena Krivosheev rxq->refill_num = 0; 3375c5aff182SThomas Petazzoni } 3376c5aff182SThomas Petazzoni 33774a188a63SJisheng Zhang static int mvneta_txq_sw_init(struct mvneta_port *pp, 3378c5aff182SThomas Petazzoni struct mvneta_tx_queue *txq) 3379c5aff182SThomas Petazzoni { 338050bf8cb6SGregory CLEMENT int cpu; 338150bf8cb6SGregory CLEMENT 3382c5aff182SThomas Petazzoni txq->size = pp->tx_ring_size; 3383c5aff182SThomas Petazzoni 33848eef5f97SEzequiel Garcia /* A queue must always have room for at least one skb. 33858eef5f97SEzequiel Garcia * Therefore, stop the queue when the free entries reaches 33868eef5f97SEzequiel Garcia * the maximum number of descriptors per skb. 33878eef5f97SEzequiel Garcia */ 33888eef5f97SEzequiel Garcia txq->tx_stop_threshold = txq->size - MVNETA_MAX_SKB_DESCS; 33898eef5f97SEzequiel Garcia txq->tx_wake_threshold = txq->tx_stop_threshold / 2; 33908eef5f97SEzequiel Garcia 3391c5aff182SThomas Petazzoni /* Allocate memory for TX descriptors */ 3392c5aff182SThomas Petazzoni txq->descs = dma_alloc_coherent(pp->dev->dev.parent, 3393c5aff182SThomas Petazzoni txq->size * MVNETA_DESC_ALIGNED_SIZE, 3394c5aff182SThomas Petazzoni &txq->descs_phys, GFP_KERNEL); 3395f95936ccSMarkus Elfring if (!txq->descs) 3396c5aff182SThomas Petazzoni return -ENOMEM; 3397c5aff182SThomas Petazzoni 3398c5aff182SThomas Petazzoni txq->last_desc = txq->size - 1; 3399c5aff182SThomas Petazzoni 34009e58c8b4SLorenzo Bianconi txq->buf = kmalloc_array(txq->size, sizeof(*txq->buf), GFP_KERNEL); 3401f4544e53STom Rix if (!txq->buf) 3402c5aff182SThomas Petazzoni return -ENOMEM; 34032adb719dSEzequiel Garcia 34042adb719dSEzequiel Garcia /* Allocate DMA buffers for TSO MAC/IP/TCP headers */ 34052adb719dSEzequiel Garcia txq->tso_hdrs = dma_alloc_coherent(pp->dev->dev.parent, 34062adb719dSEzequiel Garcia txq->size * TSO_HEADER_SIZE, 34072adb719dSEzequiel Garcia &txq->tso_hdrs_phys, GFP_KERNEL); 3408f4544e53STom Rix if (!txq->tso_hdrs) 34092adb719dSEzequiel Garcia return -ENOMEM; 3410c5aff182SThomas Petazzoni 341150bf8cb6SGregory CLEMENT /* Setup XPS mapping */ 341250bf8cb6SGregory CLEMENT if (txq_number > 1) 341350bf8cb6SGregory CLEMENT cpu = txq->id % num_present_cpus(); 341450bf8cb6SGregory CLEMENT else 341550bf8cb6SGregory CLEMENT cpu = pp->rxq_def % num_present_cpus(); 341650bf8cb6SGregory CLEMENT cpumask_set_cpu(cpu, &txq->affinity_mask); 341750bf8cb6SGregory CLEMENT netif_set_xps_queue(pp->dev, &txq->affinity_mask, txq->id); 341850bf8cb6SGregory CLEMENT 3419c5aff182SThomas Petazzoni return 0; 3420c5aff182SThomas Petazzoni } 3421c5aff182SThomas Petazzoni 34224a188a63SJisheng Zhang static void mvneta_txq_hw_init(struct mvneta_port *pp, 34234a188a63SJisheng Zhang struct mvneta_tx_queue *txq) 34244a188a63SJisheng Zhang { 34254a188a63SJisheng Zhang /* Set maximum bandwidth for enabled TXQs */ 34264a188a63SJisheng Zhang mvreg_write(pp, MVETH_TXQ_TOKEN_CFG_REG(txq->id), 0x03ffffff); 34274a188a63SJisheng Zhang mvreg_write(pp, MVETH_TXQ_TOKEN_COUNT_REG(txq->id), 0x3fffffff); 34284a188a63SJisheng Zhang 34294a188a63SJisheng Zhang /* Set Tx descriptors queue starting address */ 34304a188a63SJisheng Zhang mvreg_write(pp, MVNETA_TXQ_BASE_ADDR_REG(txq->id), txq->descs_phys); 34314a188a63SJisheng Zhang mvreg_write(pp, MVNETA_TXQ_SIZE_REG(txq->id), txq->size); 34324a188a63SJisheng Zhang 34334a188a63SJisheng Zhang mvneta_tx_done_pkts_coal_set(pp, txq, txq->done_pkts_coal); 34344a188a63SJisheng Zhang } 34354a188a63SJisheng Zhang 34364a188a63SJisheng Zhang /* Create and initialize a tx queue */ 34374a188a63SJisheng Zhang static int mvneta_txq_init(struct mvneta_port *pp, 34384a188a63SJisheng Zhang struct mvneta_tx_queue *txq) 34394a188a63SJisheng Zhang { 34404a188a63SJisheng Zhang int ret; 34414a188a63SJisheng Zhang 34424a188a63SJisheng Zhang ret = mvneta_txq_sw_init(pp, txq); 34434a188a63SJisheng Zhang if (ret < 0) 34444a188a63SJisheng Zhang return ret; 34454a188a63SJisheng Zhang 34464a188a63SJisheng Zhang mvneta_txq_hw_init(pp, txq); 34474a188a63SJisheng Zhang 34484a188a63SJisheng Zhang return 0; 34494a188a63SJisheng Zhang } 34504a188a63SJisheng Zhang 3451c5aff182SThomas Petazzoni /* Free allocated resources when mvneta_txq_init() fails to allocate memory*/ 34524a188a63SJisheng Zhang static void mvneta_txq_sw_deinit(struct mvneta_port *pp, 3453c5aff182SThomas Petazzoni struct mvneta_tx_queue *txq) 3454c5aff182SThomas Petazzoni { 3455a29b6235SMarcin Wojtas struct netdev_queue *nq = netdev_get_tx_queue(pp->dev, txq->id); 3456a29b6235SMarcin Wojtas 34579e58c8b4SLorenzo Bianconi kfree(txq->buf); 3458c5aff182SThomas Petazzoni 34592adb719dSEzequiel Garcia if (txq->tso_hdrs) 34602adb719dSEzequiel Garcia dma_free_coherent(pp->dev->dev.parent, 34612adb719dSEzequiel Garcia txq->size * TSO_HEADER_SIZE, 34622adb719dSEzequiel Garcia txq->tso_hdrs, txq->tso_hdrs_phys); 3463c5aff182SThomas Petazzoni if (txq->descs) 3464c5aff182SThomas Petazzoni dma_free_coherent(pp->dev->dev.parent, 3465c5aff182SThomas Petazzoni txq->size * MVNETA_DESC_ALIGNED_SIZE, 3466c5aff182SThomas Petazzoni txq->descs, txq->descs_phys); 3467c5aff182SThomas Petazzoni 3468a29b6235SMarcin Wojtas netdev_tx_reset_queue(nq); 3469a29b6235SMarcin Wojtas 3470c5aff182SThomas Petazzoni txq->descs = NULL; 3471c5aff182SThomas Petazzoni txq->last_desc = 0; 3472c5aff182SThomas Petazzoni txq->next_desc_to_proc = 0; 3473c5aff182SThomas Petazzoni txq->descs_phys = 0; 34744a188a63SJisheng Zhang } 3475c5aff182SThomas Petazzoni 34764a188a63SJisheng Zhang static void mvneta_txq_hw_deinit(struct mvneta_port *pp, 34774a188a63SJisheng Zhang struct mvneta_tx_queue *txq) 34784a188a63SJisheng Zhang { 3479c5aff182SThomas Petazzoni /* Set minimum bandwidth for disabled TXQs */ 3480c5aff182SThomas Petazzoni mvreg_write(pp, MVETH_TXQ_TOKEN_CFG_REG(txq->id), 0); 3481c5aff182SThomas Petazzoni mvreg_write(pp, MVETH_TXQ_TOKEN_COUNT_REG(txq->id), 0); 3482c5aff182SThomas Petazzoni 3483c5aff182SThomas Petazzoni /* Set Tx descriptors queue starting address and size */ 3484c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_TXQ_BASE_ADDR_REG(txq->id), 0); 3485c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_TXQ_SIZE_REG(txq->id), 0); 3486c5aff182SThomas Petazzoni } 3487c5aff182SThomas Petazzoni 34884a188a63SJisheng Zhang static void mvneta_txq_deinit(struct mvneta_port *pp, 34894a188a63SJisheng Zhang struct mvneta_tx_queue *txq) 34904a188a63SJisheng Zhang { 34914a188a63SJisheng Zhang mvneta_txq_sw_deinit(pp, txq); 34924a188a63SJisheng Zhang mvneta_txq_hw_deinit(pp, txq); 34934a188a63SJisheng Zhang } 34944a188a63SJisheng Zhang 3495c5aff182SThomas Petazzoni /* Cleanup all Tx queues */ 3496c5aff182SThomas Petazzoni static void mvneta_cleanup_txqs(struct mvneta_port *pp) 3497c5aff182SThomas Petazzoni { 3498c5aff182SThomas Petazzoni int queue; 3499c5aff182SThomas Petazzoni 3500c5aff182SThomas Petazzoni for (queue = 0; queue < txq_number; queue++) 3501c5aff182SThomas Petazzoni mvneta_txq_deinit(pp, &pp->txqs[queue]); 3502c5aff182SThomas Petazzoni } 3503c5aff182SThomas Petazzoni 3504c5aff182SThomas Petazzoni /* Cleanup all Rx queues */ 3505c5aff182SThomas Petazzoni static void mvneta_cleanup_rxqs(struct mvneta_port *pp) 3506c5aff182SThomas Petazzoni { 35072dcf75e2SGregory CLEMENT int queue; 35082dcf75e2SGregory CLEMENT 3509ca5902a6SYelena Krivosheev for (queue = 0; queue < rxq_number; queue++) 35102dcf75e2SGregory CLEMENT mvneta_rxq_deinit(pp, &pp->rxqs[queue]); 3511c5aff182SThomas Petazzoni } 3512c5aff182SThomas Petazzoni 3513c5aff182SThomas Petazzoni 3514c5aff182SThomas Petazzoni /* Init all Rx queues */ 3515c5aff182SThomas Petazzoni static int mvneta_setup_rxqs(struct mvneta_port *pp) 3516c5aff182SThomas Petazzoni { 35172dcf75e2SGregory CLEMENT int queue; 35182dcf75e2SGregory CLEMENT 35192dcf75e2SGregory CLEMENT for (queue = 0; queue < rxq_number; queue++) { 35202dcf75e2SGregory CLEMENT int err = mvneta_rxq_init(pp, &pp->rxqs[queue]); 35212dcf75e2SGregory CLEMENT 3522c5aff182SThomas Petazzoni if (err) { 3523c5aff182SThomas Petazzoni netdev_err(pp->dev, "%s: can't create rxq=%d\n", 35242dcf75e2SGregory CLEMENT __func__, queue); 3525c5aff182SThomas Petazzoni mvneta_cleanup_rxqs(pp); 3526c5aff182SThomas Petazzoni return err; 3527c5aff182SThomas Petazzoni } 35282dcf75e2SGregory CLEMENT } 3529c5aff182SThomas Petazzoni 3530c5aff182SThomas Petazzoni return 0; 3531c5aff182SThomas Petazzoni } 3532c5aff182SThomas Petazzoni 3533c5aff182SThomas Petazzoni /* Init all tx queues */ 3534c5aff182SThomas Petazzoni static int mvneta_setup_txqs(struct mvneta_port *pp) 3535c5aff182SThomas Petazzoni { 3536c5aff182SThomas Petazzoni int queue; 3537c5aff182SThomas Petazzoni 3538c5aff182SThomas Petazzoni for (queue = 0; queue < txq_number; queue++) { 3539c5aff182SThomas Petazzoni int err = mvneta_txq_init(pp, &pp->txqs[queue]); 3540c5aff182SThomas Petazzoni if (err) { 3541c5aff182SThomas Petazzoni netdev_err(pp->dev, "%s: can't create txq=%d\n", 3542c5aff182SThomas Petazzoni __func__, queue); 3543c5aff182SThomas Petazzoni mvneta_cleanup_txqs(pp); 3544c5aff182SThomas Petazzoni return err; 3545c5aff182SThomas Petazzoni } 3546c5aff182SThomas Petazzoni } 3547c5aff182SThomas Petazzoni 3548c5aff182SThomas Petazzoni return 0; 3549c5aff182SThomas Petazzoni } 3550c5aff182SThomas Petazzoni 3551b4748553SSascha Hauer static int mvneta_comphy_init(struct mvneta_port *pp, phy_interface_t interface) 3552031b922bSMarek Behún { 3553031b922bSMarek Behún int ret; 3554031b922bSMarek Behún 3555b4748553SSascha Hauer ret = phy_set_mode_ext(pp->comphy, PHY_MODE_ETHERNET, interface); 3556031b922bSMarek Behún if (ret) 3557031b922bSMarek Behún return ret; 3558031b922bSMarek Behún 3559031b922bSMarek Behún return phy_power_on(pp->comphy); 3560031b922bSMarek Behún } 3561031b922bSMarek Behún 3562b4748553SSascha Hauer static int mvneta_config_interface(struct mvneta_port *pp, 3563b4748553SSascha Hauer phy_interface_t interface) 3564b4748553SSascha Hauer { 3565b4748553SSascha Hauer int ret = 0; 3566b4748553SSascha Hauer 3567b4748553SSascha Hauer if (pp->comphy) { 3568b4748553SSascha Hauer if (interface == PHY_INTERFACE_MODE_SGMII || 3569b4748553SSascha Hauer interface == PHY_INTERFACE_MODE_1000BASEX || 3570b4748553SSascha Hauer interface == PHY_INTERFACE_MODE_2500BASEX) { 3571b4748553SSascha Hauer ret = mvneta_comphy_init(pp, interface); 3572b4748553SSascha Hauer } 3573b4748553SSascha Hauer } else { 3574b4748553SSascha Hauer switch (interface) { 3575b4748553SSascha Hauer case PHY_INTERFACE_MODE_QSGMII: 3576b4748553SSascha Hauer mvreg_write(pp, MVNETA_SERDES_CFG, 3577b4748553SSascha Hauer MVNETA_QSGMII_SERDES_PROTO); 3578b4748553SSascha Hauer break; 3579b4748553SSascha Hauer 3580b4748553SSascha Hauer case PHY_INTERFACE_MODE_SGMII: 3581b4748553SSascha Hauer case PHY_INTERFACE_MODE_1000BASEX: 3582b4748553SSascha Hauer mvreg_write(pp, MVNETA_SERDES_CFG, 3583b4748553SSascha Hauer MVNETA_SGMII_SERDES_PROTO); 3584b4748553SSascha Hauer break; 35851a642ca7SSascha Hauer 35861a642ca7SSascha Hauer case PHY_INTERFACE_MODE_2500BASEX: 35871a642ca7SSascha Hauer mvreg_write(pp, MVNETA_SERDES_CFG, 35881a642ca7SSascha Hauer MVNETA_HSGMII_SERDES_PROTO); 35891a642ca7SSascha Hauer break; 3590b4748553SSascha Hauer default: 3591d3d239dcSSascha Hauer break; 3592b4748553SSascha Hauer } 3593b4748553SSascha Hauer } 3594b4748553SSascha Hauer 3595b4748553SSascha Hauer pp->phy_interface = interface; 3596b4748553SSascha Hauer 3597b4748553SSascha Hauer return ret; 3598b4748553SSascha Hauer } 3599b4748553SSascha Hauer 3600c5aff182SThomas Petazzoni static void mvneta_start_dev(struct mvneta_port *pp) 3601c5aff182SThomas Petazzoni { 36026b125d63SGregory CLEMENT int cpu; 360312bb03b4SMaxime Ripard 3604b4748553SSascha Hauer WARN_ON(mvneta_config_interface(pp, pp->phy_interface)); 3605a10c1c81SRussell King 3606c5aff182SThomas Petazzoni mvneta_max_rx_size_set(pp, pp->pkt_size); 3607c5aff182SThomas Petazzoni mvneta_txq_max_tx_size_set(pp, pp->pkt_size); 3608c5aff182SThomas Petazzoni 3609c5aff182SThomas Petazzoni /* start the Rx/Tx activity */ 3610c5aff182SThomas Petazzoni mvneta_port_enable(pp); 3611c5aff182SThomas Petazzoni 36122636ac3cSMarcin Wojtas if (!pp->neta_armada3700) { 3613c5aff182SThomas Petazzoni /* Enable polling on the port */ 3614129219e4SGregory CLEMENT for_each_online_cpu(cpu) { 36152636ac3cSMarcin Wojtas struct mvneta_pcpu_port *port = 36162636ac3cSMarcin Wojtas per_cpu_ptr(pp->ports, cpu); 361712bb03b4SMaxime Ripard 361812bb03b4SMaxime Ripard napi_enable(&port->napi); 361912bb03b4SMaxime Ripard } 36202636ac3cSMarcin Wojtas } else { 36212636ac3cSMarcin Wojtas napi_enable(&pp->napi); 36222636ac3cSMarcin Wojtas } 3623c5aff182SThomas Petazzoni 36242dcf75e2SGregory CLEMENT /* Unmask interrupts. It has to be done from each CPU */ 36256b125d63SGregory CLEMENT on_each_cpu(mvneta_percpu_unmask_interrupt, pp, true); 36266b125d63SGregory CLEMENT 3627898b2970SStas Sergeev mvreg_write(pp, MVNETA_INTR_MISC_MASK, 3628898b2970SStas Sergeev MVNETA_CAUSE_PHY_STATUS_CHANGE | 3629856b2cc5SRussell King MVNETA_CAUSE_LINK_CHANGE); 3630c5aff182SThomas Petazzoni 3631503f9aa9SRussell King phylink_start(pp->phylink); 363261b5cc20SDaniel González Cabanelas 36335ba2254bSJisheng Zhang /* We may have called phylink_speed_down before */ 363461b5cc20SDaniel González Cabanelas phylink_speed_up(pp->phylink); 363561b5cc20SDaniel González Cabanelas 3636c5aff182SThomas Petazzoni netif_tx_start_all_queues(pp->dev); 363762a502ccSLorenzo Bianconi 363862a502ccSLorenzo Bianconi clear_bit(__MVNETA_DOWN, &pp->state); 3639c5aff182SThomas Petazzoni } 3640c5aff182SThomas Petazzoni 3641c5aff182SThomas Petazzoni static void mvneta_stop_dev(struct mvneta_port *pp) 3642c5aff182SThomas Petazzoni { 364312bb03b4SMaxime Ripard unsigned int cpu; 364412bb03b4SMaxime Ripard 364562a502ccSLorenzo Bianconi set_bit(__MVNETA_DOWN, &pp->state); 364662a502ccSLorenzo Bianconi 364761b5cc20SDaniel González Cabanelas if (device_may_wakeup(&pp->dev->dev)) 364861b5cc20SDaniel González Cabanelas phylink_speed_down(pp->phylink, false); 364961b5cc20SDaniel González Cabanelas 3650503f9aa9SRussell King phylink_stop(pp->phylink); 3651c5aff182SThomas Petazzoni 36522636ac3cSMarcin Wojtas if (!pp->neta_armada3700) { 3653129219e4SGregory CLEMENT for_each_online_cpu(cpu) { 36542636ac3cSMarcin Wojtas struct mvneta_pcpu_port *port = 36552636ac3cSMarcin Wojtas per_cpu_ptr(pp->ports, cpu); 365612bb03b4SMaxime Ripard 365712bb03b4SMaxime Ripard napi_disable(&port->napi); 365812bb03b4SMaxime Ripard } 36592636ac3cSMarcin Wojtas } else { 36602636ac3cSMarcin Wojtas napi_disable(&pp->napi); 36612636ac3cSMarcin Wojtas } 3662c5aff182SThomas Petazzoni 3663c5aff182SThomas Petazzoni netif_carrier_off(pp->dev); 3664c5aff182SThomas Petazzoni 3665c5aff182SThomas Petazzoni mvneta_port_down(pp); 3666c5aff182SThomas Petazzoni netif_tx_stop_all_queues(pp->dev); 3667c5aff182SThomas Petazzoni 3668c5aff182SThomas Petazzoni /* Stop the port activity */ 3669c5aff182SThomas Petazzoni mvneta_port_disable(pp); 3670c5aff182SThomas Petazzoni 3671c5aff182SThomas Petazzoni /* Clear all ethernet port interrupts */ 3672db488c10SGregory CLEMENT on_each_cpu(mvneta_percpu_clear_intr_cause, pp, true); 3673c5aff182SThomas Petazzoni 3674c5aff182SThomas Petazzoni /* Mask all ethernet port interrupts */ 3675db488c10SGregory CLEMENT on_each_cpu(mvneta_percpu_mask_interrupt, pp, true); 3676c5aff182SThomas Petazzoni 3677c5aff182SThomas Petazzoni mvneta_tx_reset(pp); 3678c5aff182SThomas Petazzoni mvneta_rx_reset(pp); 3679a10c1c81SRussell King 3680a10c1c81SRussell King WARN_ON(phy_power_off(pp->comphy)); 3681c5aff182SThomas Petazzoni } 3682c5aff182SThomas Petazzoni 3683db5dd0dbSMarcin Wojtas static void mvneta_percpu_enable(void *arg) 3684db5dd0dbSMarcin Wojtas { 3685db5dd0dbSMarcin Wojtas struct mvneta_port *pp = arg; 3686db5dd0dbSMarcin Wojtas 3687db5dd0dbSMarcin Wojtas enable_percpu_irq(pp->dev->irq, IRQ_TYPE_NONE); 3688db5dd0dbSMarcin Wojtas } 3689db5dd0dbSMarcin Wojtas 3690db5dd0dbSMarcin Wojtas static void mvneta_percpu_disable(void *arg) 3691db5dd0dbSMarcin Wojtas { 3692db5dd0dbSMarcin Wojtas struct mvneta_port *pp = arg; 3693db5dd0dbSMarcin Wojtas 3694db5dd0dbSMarcin Wojtas disable_percpu_irq(pp->dev->irq); 3695db5dd0dbSMarcin Wojtas } 3696db5dd0dbSMarcin Wojtas 3697c5aff182SThomas Petazzoni /* Change the device mtu */ 3698c5aff182SThomas Petazzoni static int mvneta_change_mtu(struct net_device *dev, int mtu) 3699c5aff182SThomas Petazzoni { 3700c5aff182SThomas Petazzoni struct mvneta_port *pp = netdev_priv(dev); 3701c5aff182SThomas Petazzoni int ret; 3702c5aff182SThomas Petazzoni 37035777987eSJarod Wilson if (!IS_ALIGNED(MVNETA_RX_PKT_SIZE(mtu), 8)) { 37045777987eSJarod Wilson netdev_info(dev, "Illegal MTU value %d, rounding to %d\n", 37055777987eSJarod Wilson mtu, ALIGN(MVNETA_RX_PKT_SIZE(mtu), 8)); 37065777987eSJarod Wilson mtu = ALIGN(MVNETA_RX_PKT_SIZE(mtu), 8); 37075777987eSJarod Wilson } 3708c5aff182SThomas Petazzoni 37090db51da7SLorenzo Bianconi if (pp->xdp_prog && mtu > MVNETA_MAX_RX_BUF_SIZE) { 37100db51da7SLorenzo Bianconi netdev_info(dev, "Illegal MTU value %d for XDP mode\n", mtu); 37110db51da7SLorenzo Bianconi return -EINVAL; 37120db51da7SLorenzo Bianconi } 37130db51da7SLorenzo Bianconi 3714c5aff182SThomas Petazzoni dev->mtu = mtu; 3715c5aff182SThomas Petazzoni 3716b65657fcSSimon Guinot if (!netif_running(dev)) { 3717dc35a10fSMarcin Wojtas if (pp->bm_priv) 3718dc35a10fSMarcin Wojtas mvneta_bm_update_mtu(pp, mtu); 3719dc35a10fSMarcin Wojtas 3720b65657fcSSimon Guinot netdev_update_features(dev); 3721c5aff182SThomas Petazzoni return 0; 3722b65657fcSSimon Guinot } 3723c5aff182SThomas Petazzoni 37246a20c175SThomas Petazzoni /* The interface is running, so we have to force a 3725a92dbd96SEzequiel Garcia * reallocation of the queues 3726c5aff182SThomas Petazzoni */ 3727c5aff182SThomas Petazzoni mvneta_stop_dev(pp); 3728db5dd0dbSMarcin Wojtas on_each_cpu(mvneta_percpu_disable, pp, true); 3729c5aff182SThomas Petazzoni 3730c5aff182SThomas Petazzoni mvneta_cleanup_txqs(pp); 3731c5aff182SThomas Petazzoni mvneta_cleanup_rxqs(pp); 3732c5aff182SThomas Petazzoni 3733dc35a10fSMarcin Wojtas if (pp->bm_priv) 3734dc35a10fSMarcin Wojtas mvneta_bm_update_mtu(pp, mtu); 3735dc35a10fSMarcin Wojtas 3736a92dbd96SEzequiel Garcia pp->pkt_size = MVNETA_RX_PKT_SIZE(dev->mtu); 3737c5aff182SThomas Petazzoni 3738c5aff182SThomas Petazzoni ret = mvneta_setup_rxqs(pp); 3739c5aff182SThomas Petazzoni if (ret) { 3740a92dbd96SEzequiel Garcia netdev_err(dev, "unable to setup rxqs after MTU change\n"); 3741c5aff182SThomas Petazzoni return ret; 3742c5aff182SThomas Petazzoni } 3743c5aff182SThomas Petazzoni 3744a92dbd96SEzequiel Garcia ret = mvneta_setup_txqs(pp); 3745a92dbd96SEzequiel Garcia if (ret) { 3746a92dbd96SEzequiel Garcia netdev_err(dev, "unable to setup txqs after MTU change\n"); 3747a92dbd96SEzequiel Garcia return ret; 3748a92dbd96SEzequiel Garcia } 3749c5aff182SThomas Petazzoni 3750db5dd0dbSMarcin Wojtas on_each_cpu(mvneta_percpu_enable, pp, true); 3751c5aff182SThomas Petazzoni mvneta_start_dev(pp); 3752c5aff182SThomas Petazzoni 3753b65657fcSSimon Guinot netdev_update_features(dev); 3754b65657fcSSimon Guinot 3755c5aff182SThomas Petazzoni return 0; 3756c5aff182SThomas Petazzoni } 3757c5aff182SThomas Petazzoni 3758b65657fcSSimon Guinot static netdev_features_t mvneta_fix_features(struct net_device *dev, 3759b65657fcSSimon Guinot netdev_features_t features) 3760b65657fcSSimon Guinot { 3761b65657fcSSimon Guinot struct mvneta_port *pp = netdev_priv(dev); 3762b65657fcSSimon Guinot 3763b65657fcSSimon Guinot if (pp->tx_csum_limit && dev->mtu > pp->tx_csum_limit) { 3764b65657fcSSimon Guinot features &= ~(NETIF_F_IP_CSUM | NETIF_F_TSO); 3765b65657fcSSimon Guinot netdev_info(dev, 3766b65657fcSSimon Guinot "Disable IP checksum for MTU greater than %dB\n", 3767b65657fcSSimon Guinot pp->tx_csum_limit); 3768b65657fcSSimon Guinot } 3769b65657fcSSimon Guinot 3770b65657fcSSimon Guinot return features; 3771b65657fcSSimon Guinot } 3772b65657fcSSimon Guinot 37738cc3e439SThomas Petazzoni /* Get mac address */ 37748cc3e439SThomas Petazzoni static void mvneta_get_mac_addr(struct mvneta_port *pp, unsigned char *addr) 37758cc3e439SThomas Petazzoni { 37768cc3e439SThomas Petazzoni u32 mac_addr_l, mac_addr_h; 37778cc3e439SThomas Petazzoni 37788cc3e439SThomas Petazzoni mac_addr_l = mvreg_read(pp, MVNETA_MAC_ADDR_LOW); 37798cc3e439SThomas Petazzoni mac_addr_h = mvreg_read(pp, MVNETA_MAC_ADDR_HIGH); 37808cc3e439SThomas Petazzoni addr[0] = (mac_addr_h >> 24) & 0xFF; 37818cc3e439SThomas Petazzoni addr[1] = (mac_addr_h >> 16) & 0xFF; 37828cc3e439SThomas Petazzoni addr[2] = (mac_addr_h >> 8) & 0xFF; 37838cc3e439SThomas Petazzoni addr[3] = mac_addr_h & 0xFF; 37848cc3e439SThomas Petazzoni addr[4] = (mac_addr_l >> 8) & 0xFF; 37858cc3e439SThomas Petazzoni addr[5] = mac_addr_l & 0xFF; 37868cc3e439SThomas Petazzoni } 37878cc3e439SThomas Petazzoni 3788c5aff182SThomas Petazzoni /* Handle setting mac address */ 3789c5aff182SThomas Petazzoni static int mvneta_set_mac_addr(struct net_device *dev, void *addr) 3790c5aff182SThomas Petazzoni { 3791c5aff182SThomas Petazzoni struct mvneta_port *pp = netdev_priv(dev); 3792e68de360SEzequiel Garcia struct sockaddr *sockaddr = addr; 3793e68de360SEzequiel Garcia int ret; 3794c5aff182SThomas Petazzoni 3795e68de360SEzequiel Garcia ret = eth_prepare_mac_addr_change(dev, addr); 3796e68de360SEzequiel Garcia if (ret < 0) 3797e68de360SEzequiel Garcia return ret; 3798c5aff182SThomas Petazzoni /* Remove previous address table entry */ 3799c5aff182SThomas Petazzoni mvneta_mac_addr_set(pp, dev->dev_addr, -1); 3800c5aff182SThomas Petazzoni 3801c5aff182SThomas Petazzoni /* Set new addr in hw */ 380290b74c01SGregory CLEMENT mvneta_mac_addr_set(pp, sockaddr->sa_data, pp->rxq_def); 3803c5aff182SThomas Petazzoni 3804e68de360SEzequiel Garcia eth_commit_mac_addr_change(dev, addr); 3805c5aff182SThomas Petazzoni return 0; 3806c5aff182SThomas Petazzoni } 3807c5aff182SThomas Petazzoni 380844cc27e4SIoana Ciornei static void mvneta_validate(struct phylink_config *config, 380944cc27e4SIoana Ciornei unsigned long *supported, 3810503f9aa9SRussell King struct phylink_link_state *state) 3811503f9aa9SRussell King { 381244cc27e4SIoana Ciornei struct net_device *ndev = to_net_dev(config->dev); 3813a10c1c81SRussell King struct mvneta_port *pp = netdev_priv(ndev); 3814503f9aa9SRussell King __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, }; 3815503f9aa9SRussell King 381622f4bf8aSRussell King /* We only support QSGMII, SGMII, 802.3z and RGMII modes */ 3817503f9aa9SRussell King if (state->interface != PHY_INTERFACE_MODE_NA && 3818503f9aa9SRussell King state->interface != PHY_INTERFACE_MODE_QSGMII && 3819503f9aa9SRussell King state->interface != PHY_INTERFACE_MODE_SGMII && 382022f4bf8aSRussell King !phy_interface_mode_is_8023z(state->interface) && 3821503f9aa9SRussell King !phy_interface_mode_is_rgmii(state->interface)) { 3822503f9aa9SRussell King bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS); 3823503f9aa9SRussell King return; 3824503f9aa9SRussell King } 3825503f9aa9SRussell King 3826503f9aa9SRussell King /* Allow all the expected bits */ 3827503f9aa9SRussell King phylink_set(mask, Autoneg); 3828503f9aa9SRussell King phylink_set_port_modes(mask); 3829503f9aa9SRussell King 38304932a918SRussell King /* Asymmetric pause is unsupported */ 38314932a918SRussell King phylink_set(mask, Pause); 3832da58a931SMaxime Chevallier 383383e65df6SMaxime Chevallier /* Half-duplex at speeds higher than 100Mbit is unsupported */ 3834a10c1c81SRussell King if (pp->comphy || state->interface != PHY_INTERFACE_MODE_2500BASEX) { 3835503f9aa9SRussell King phylink_set(mask, 1000baseT_Full); 3836503f9aa9SRussell King phylink_set(mask, 1000baseX_Full); 3837a10c1c81SRussell King } 3838a10c1c81SRussell King if (pp->comphy || state->interface == PHY_INTERFACE_MODE_2500BASEX) { 3839eda3d1b0SMaxime Chevallier phylink_set(mask, 2500baseT_Full); 3840a10c1c81SRussell King phylink_set(mask, 2500baseX_Full); 3841a10c1c81SRussell King } 384222f4bf8aSRussell King 384322f4bf8aSRussell King if (!phy_interface_mode_is_8023z(state->interface)) { 384422f4bf8aSRussell King /* 10M and 100M are only supported in non-802.3z mode */ 3845503f9aa9SRussell King phylink_set(mask, 10baseT_Half); 3846503f9aa9SRussell King phylink_set(mask, 10baseT_Full); 3847503f9aa9SRussell King phylink_set(mask, 100baseT_Half); 3848503f9aa9SRussell King phylink_set(mask, 100baseT_Full); 384922f4bf8aSRussell King } 3850503f9aa9SRussell King 3851503f9aa9SRussell King bitmap_and(supported, supported, mask, 3852503f9aa9SRussell King __ETHTOOL_LINK_MODE_MASK_NBITS); 3853503f9aa9SRussell King bitmap_and(state->advertising, state->advertising, mask, 3854503f9aa9SRussell King __ETHTOOL_LINK_MODE_MASK_NBITS); 3855a10c1c81SRussell King 3856a10c1c81SRussell King /* We can only operate at 2500BaseX or 1000BaseX. If requested 3857a10c1c81SRussell King * to advertise both, only report advertising at 2500BaseX. 3858a10c1c81SRussell King */ 3859a10c1c81SRussell King phylink_helper_basex_speed(state); 3860503f9aa9SRussell King } 3861503f9aa9SRussell King 3862d46b7e4fSRussell King static void mvneta_mac_pcs_get_state(struct phylink_config *config, 3863503f9aa9SRussell King struct phylink_link_state *state) 3864c5aff182SThomas Petazzoni { 386544cc27e4SIoana Ciornei struct net_device *ndev = to_net_dev(config->dev); 3866c5aff182SThomas Petazzoni struct mvneta_port *pp = netdev_priv(ndev); 3867503f9aa9SRussell King u32 gmac_stat; 3868c5aff182SThomas Petazzoni 3869503f9aa9SRussell King gmac_stat = mvreg_read(pp, MVNETA_GMAC_STATUS); 3870503f9aa9SRussell King 3871503f9aa9SRussell King if (gmac_stat & MVNETA_GMAC_SPEED_1000) 3872a10c1c81SRussell King state->speed = 3873a10c1c81SRussell King state->interface == PHY_INTERFACE_MODE_2500BASEX ? 3874a10c1c81SRussell King SPEED_2500 : SPEED_1000; 3875503f9aa9SRussell King else if (gmac_stat & MVNETA_GMAC_SPEED_100) 3876503f9aa9SRussell King state->speed = SPEED_100; 3877503f9aa9SRussell King else 3878503f9aa9SRussell King state->speed = SPEED_10; 3879503f9aa9SRussell King 3880503f9aa9SRussell King state->an_complete = !!(gmac_stat & MVNETA_GMAC_AN_COMPLETE); 3881503f9aa9SRussell King state->link = !!(gmac_stat & MVNETA_GMAC_LINK_UP); 3882503f9aa9SRussell King state->duplex = !!(gmac_stat & MVNETA_GMAC_FULL_DUPLEX); 3883503f9aa9SRussell King 3884503f9aa9SRussell King state->pause = 0; 38854932a918SRussell King if (gmac_stat & MVNETA_GMAC_RX_FLOW_CTRL_ENABLE) 38864932a918SRussell King state->pause |= MLO_PAUSE_RX; 38874932a918SRussell King if (gmac_stat & MVNETA_GMAC_TX_FLOW_CTRL_ENABLE) 38884932a918SRussell King state->pause |= MLO_PAUSE_TX; 3889503f9aa9SRussell King } 3890503f9aa9SRussell King 389144cc27e4SIoana Ciornei static void mvneta_mac_an_restart(struct phylink_config *config) 389222f4bf8aSRussell King { 389344cc27e4SIoana Ciornei struct net_device *ndev = to_net_dev(config->dev); 389422f4bf8aSRussell King struct mvneta_port *pp = netdev_priv(ndev); 389522f4bf8aSRussell King u32 gmac_an = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG); 389622f4bf8aSRussell King 389722f4bf8aSRussell King mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, 389822f4bf8aSRussell King gmac_an | MVNETA_GMAC_INBAND_RESTART_AN); 389922f4bf8aSRussell King mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, 390022f4bf8aSRussell King gmac_an & ~MVNETA_GMAC_INBAND_RESTART_AN); 390122f4bf8aSRussell King } 390222f4bf8aSRussell King 390344cc27e4SIoana Ciornei static void mvneta_mac_config(struct phylink_config *config, unsigned int mode, 3904503f9aa9SRussell King const struct phylink_link_state *state) 3905503f9aa9SRussell King { 390644cc27e4SIoana Ciornei struct net_device *ndev = to_net_dev(config->dev); 3907503f9aa9SRussell King struct mvneta_port *pp = netdev_priv(ndev); 390822f4bf8aSRussell King u32 new_ctrl0, gmac_ctrl0 = mvreg_read(pp, MVNETA_GMAC_CTRL_0); 3909503f9aa9SRussell King u32 new_ctrl2, gmac_ctrl2 = mvreg_read(pp, MVNETA_GMAC_CTRL_2); 3910da58a931SMaxime Chevallier u32 new_ctrl4, gmac_ctrl4 = mvreg_read(pp, MVNETA_GMAC_CTRL_4); 3911503f9aa9SRussell King u32 new_clk, gmac_clk = mvreg_read(pp, MVNETA_GMAC_CLOCK_DIVIDER); 3912503f9aa9SRussell King u32 new_an, gmac_an = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG); 3913503f9aa9SRussell King 391422f4bf8aSRussell King new_ctrl0 = gmac_ctrl0 & ~MVNETA_GMAC0_PORT_1000BASE_X; 391532699954SRussell King new_ctrl2 = gmac_ctrl2 & ~(MVNETA_GMAC2_INBAND_AN_ENABLE | 391632699954SRussell King MVNETA_GMAC2_PORT_RESET); 3917da58a931SMaxime Chevallier new_ctrl4 = gmac_ctrl4 & ~(MVNETA_GMAC4_SHORT_PREAMBLE_ENABLE); 3918503f9aa9SRussell King new_clk = gmac_clk & ~MVNETA_GMAC_1MS_CLOCK_ENABLE; 3919503f9aa9SRussell King new_an = gmac_an & ~(MVNETA_GMAC_INBAND_AN_ENABLE | 3920503f9aa9SRussell King MVNETA_GMAC_INBAND_RESTART_AN | 3921503f9aa9SRussell King MVNETA_GMAC_AN_SPEED_EN | 392222f4bf8aSRussell King MVNETA_GMAC_ADVERT_SYM_FLOW_CTRL | 3923503f9aa9SRussell King MVNETA_GMAC_AN_FLOW_CTRL_EN | 3924503f9aa9SRussell King MVNETA_GMAC_AN_DUPLEX_EN); 3925c5aff182SThomas Petazzoni 392632699954SRussell King /* Even though it might look weird, when we're configured in 392732699954SRussell King * SGMII or QSGMII mode, the RGMII bit needs to be set. 392832699954SRussell King */ 392932699954SRussell King new_ctrl2 |= MVNETA_GMAC2_PORT_RGMII; 393032699954SRussell King 393132699954SRussell King if (state->interface == PHY_INTERFACE_MODE_QSGMII || 393222f4bf8aSRussell King state->interface == PHY_INTERFACE_MODE_SGMII || 393322f4bf8aSRussell King phy_interface_mode_is_8023z(state->interface)) 393432699954SRussell King new_ctrl2 |= MVNETA_GMAC2_PCS_ENABLE; 393532699954SRussell King 39364932a918SRussell King if (phylink_test(state->advertising, Pause)) 39374932a918SRussell King new_an |= MVNETA_GMAC_ADVERT_SYM_FLOW_CTRL; 39384932a918SRussell King 3939503f9aa9SRussell King if (!phylink_autoneg_inband(mode)) { 3940ff03f0b1SRussell King /* Phy or fixed speed - nothing to do, leave the 3941ff03f0b1SRussell King * configured speed, duplex and flow control as-is. 3942ff03f0b1SRussell King */ 394322f4bf8aSRussell King } else if (state->interface == PHY_INTERFACE_MODE_SGMII) { 3944503f9aa9SRussell King /* SGMII mode receives the state from the PHY */ 3945503f9aa9SRussell King new_ctrl2 |= MVNETA_GMAC2_INBAND_AN_ENABLE; 3946503f9aa9SRussell King new_clk |= MVNETA_GMAC_1MS_CLOCK_ENABLE; 3947503f9aa9SRussell King new_an = (new_an & ~(MVNETA_GMAC_FORCE_LINK_DOWN | 3948ff03f0b1SRussell King MVNETA_GMAC_FORCE_LINK_PASS | 3949ff03f0b1SRussell King MVNETA_GMAC_CONFIG_MII_SPEED | 3950ff03f0b1SRussell King MVNETA_GMAC_CONFIG_GMII_SPEED | 3951ff03f0b1SRussell King MVNETA_GMAC_CONFIG_FULL_DUPLEX)) | 3952503f9aa9SRussell King MVNETA_GMAC_INBAND_AN_ENABLE | 3953503f9aa9SRussell King MVNETA_GMAC_AN_SPEED_EN | 3954503f9aa9SRussell King MVNETA_GMAC_AN_DUPLEX_EN; 395522f4bf8aSRussell King } else { 395622f4bf8aSRussell King /* 802.3z negotiation - only 1000base-X */ 395722f4bf8aSRussell King new_ctrl0 |= MVNETA_GMAC0_PORT_1000BASE_X; 395822f4bf8aSRussell King new_clk |= MVNETA_GMAC_1MS_CLOCK_ENABLE; 395922f4bf8aSRussell King new_an = (new_an & ~(MVNETA_GMAC_FORCE_LINK_DOWN | 3960ff03f0b1SRussell King MVNETA_GMAC_FORCE_LINK_PASS | 3961ff03f0b1SRussell King MVNETA_GMAC_CONFIG_MII_SPEED)) | 396222f4bf8aSRussell King MVNETA_GMAC_INBAND_AN_ENABLE | 396322f4bf8aSRussell King MVNETA_GMAC_CONFIG_GMII_SPEED | 396422f4bf8aSRussell King /* The MAC only supports FD mode */ 396522f4bf8aSRussell King MVNETA_GMAC_CONFIG_FULL_DUPLEX; 39664932a918SRussell King 39674932a918SRussell King if (state->pause & MLO_PAUSE_AN && state->an_enabled) 39684932a918SRussell King new_an |= MVNETA_GMAC_AN_FLOW_CTRL_EN; 3969c5aff182SThomas Petazzoni } 3970c5aff182SThomas Petazzoni 3971503f9aa9SRussell King /* Armada 370 documentation says we can only change the port mode 3972503f9aa9SRussell King * and in-band enable when the link is down, so force it down 3973503f9aa9SRussell King * while making these changes. We also do this for GMAC_CTRL2 */ 397422f4bf8aSRussell King if ((new_ctrl0 ^ gmac_ctrl0) & MVNETA_GMAC0_PORT_1000BASE_X || 397522f4bf8aSRussell King (new_ctrl2 ^ gmac_ctrl2) & MVNETA_GMAC2_INBAND_AN_ENABLE || 3976503f9aa9SRussell King (new_an ^ gmac_an) & MVNETA_GMAC_INBAND_AN_ENABLE) { 3977503f9aa9SRussell King mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, 3978503f9aa9SRussell King (gmac_an & ~MVNETA_GMAC_FORCE_LINK_PASS) | 3979503f9aa9SRussell King MVNETA_GMAC_FORCE_LINK_DOWN); 3980503f9aa9SRussell King } 3981503f9aa9SRussell King 3982a10c1c81SRussell King 3983da58a931SMaxime Chevallier /* When at 2.5G, the link partner can send frames with shortened 3984da58a931SMaxime Chevallier * preambles. 3985da58a931SMaxime Chevallier */ 3986f2ca673dSRussell King if (state->interface == PHY_INTERFACE_MODE_2500BASEX) 3987da58a931SMaxime Chevallier new_ctrl4 |= MVNETA_GMAC4_SHORT_PREAMBLE_ENABLE; 3988da58a931SMaxime Chevallier 3989b4748553SSascha Hauer if (pp->phy_interface != state->interface) { 3990b4748553SSascha Hauer if (pp->comphy) 3991031b922bSMarek Behún WARN_ON(phy_power_off(pp->comphy)); 3992b4748553SSascha Hauer WARN_ON(mvneta_config_interface(pp, state->interface)); 3993031b922bSMarek Behún } 3994a10c1c81SRussell King 399522f4bf8aSRussell King if (new_ctrl0 != gmac_ctrl0) 399622f4bf8aSRussell King mvreg_write(pp, MVNETA_GMAC_CTRL_0, new_ctrl0); 3997503f9aa9SRussell King if (new_ctrl2 != gmac_ctrl2) 3998503f9aa9SRussell King mvreg_write(pp, MVNETA_GMAC_CTRL_2, new_ctrl2); 3999da58a931SMaxime Chevallier if (new_ctrl4 != gmac_ctrl4) 4000da58a931SMaxime Chevallier mvreg_write(pp, MVNETA_GMAC_CTRL_4, new_ctrl4); 4001503f9aa9SRussell King if (new_clk != gmac_clk) 4002503f9aa9SRussell King mvreg_write(pp, MVNETA_GMAC_CLOCK_DIVIDER, new_clk); 4003503f9aa9SRussell King if (new_an != gmac_an) 4004503f9aa9SRussell King mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, new_an); 400532699954SRussell King 400632699954SRussell King if (gmac_ctrl2 & MVNETA_GMAC2_PORT_RESET) { 400732699954SRussell King while ((mvreg_read(pp, MVNETA_GMAC_CTRL_2) & 400832699954SRussell King MVNETA_GMAC2_PORT_RESET) != 0) 400932699954SRussell King continue; 401032699954SRussell King } 4011503f9aa9SRussell King } 4012503f9aa9SRussell King 40136d81f451SRussell King static void mvneta_set_eee(struct mvneta_port *pp, bool enable) 40146d81f451SRussell King { 40156d81f451SRussell King u32 lpi_ctl1; 40166d81f451SRussell King 40176d81f451SRussell King lpi_ctl1 = mvreg_read(pp, MVNETA_LPI_CTRL_1); 40186d81f451SRussell King if (enable) 40196d81f451SRussell King lpi_ctl1 |= MVNETA_LPI_REQUEST_ENABLE; 40206d81f451SRussell King else 40216d81f451SRussell King lpi_ctl1 &= ~MVNETA_LPI_REQUEST_ENABLE; 40226d81f451SRussell King mvreg_write(pp, MVNETA_LPI_CTRL_1, lpi_ctl1); 40236d81f451SRussell King } 40246d81f451SRussell King 402544cc27e4SIoana Ciornei static void mvneta_mac_link_down(struct phylink_config *config, 402644cc27e4SIoana Ciornei unsigned int mode, phy_interface_t interface) 4027fc548b99SRussell King { 402844cc27e4SIoana Ciornei struct net_device *ndev = to_net_dev(config->dev); 4029fc548b99SRussell King struct mvneta_port *pp = netdev_priv(ndev); 4030fc548b99SRussell King u32 val; 4031fc548b99SRussell King 4032503f9aa9SRussell King mvneta_port_down(pp); 4033503f9aa9SRussell King 4034503f9aa9SRussell King if (!phylink_autoneg_inband(mode)) { 4035fc548b99SRussell King val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG); 4036fc548b99SRussell King val &= ~MVNETA_GMAC_FORCE_LINK_PASS; 4037fc548b99SRussell King val |= MVNETA_GMAC_FORCE_LINK_DOWN; 4038fc548b99SRussell King mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val); 4039fc548b99SRussell King } 40406d81f451SRussell King 40416d81f451SRussell King pp->eee_active = false; 40426d81f451SRussell King mvneta_set_eee(pp, false); 4043fc548b99SRussell King } 4044fc548b99SRussell King 404591a208f2SRussell King static void mvneta_mac_link_up(struct phylink_config *config, 404691a208f2SRussell King struct phy_device *phy, 404791a208f2SRussell King unsigned int mode, phy_interface_t interface, 404891a208f2SRussell King int speed, int duplex, 404991a208f2SRussell King bool tx_pause, bool rx_pause) 4050fc548b99SRussell King { 405144cc27e4SIoana Ciornei struct net_device *ndev = to_net_dev(config->dev); 4052fc548b99SRussell King struct mvneta_port *pp = netdev_priv(ndev); 4053fc548b99SRussell King u32 val; 4054fc548b99SRussell King 4055503f9aa9SRussell King if (!phylink_autoneg_inband(mode)) { 4056fc548b99SRussell King val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG); 4057ff03f0b1SRussell King val &= ~(MVNETA_GMAC_FORCE_LINK_DOWN | 4058ff03f0b1SRussell King MVNETA_GMAC_CONFIG_MII_SPEED | 4059ff03f0b1SRussell King MVNETA_GMAC_CONFIG_GMII_SPEED | 4060ff03f0b1SRussell King MVNETA_GMAC_CONFIG_FLOW_CTRL | 4061ff03f0b1SRussell King MVNETA_GMAC_CONFIG_FULL_DUPLEX); 4062fc548b99SRussell King val |= MVNETA_GMAC_FORCE_LINK_PASS; 4063ff03f0b1SRussell King 4064ff03f0b1SRussell King if (speed == SPEED_1000 || speed == SPEED_2500) 4065ff03f0b1SRussell King val |= MVNETA_GMAC_CONFIG_GMII_SPEED; 4066ff03f0b1SRussell King else if (speed == SPEED_100) 4067ff03f0b1SRussell King val |= MVNETA_GMAC_CONFIG_MII_SPEED; 4068ff03f0b1SRussell King 4069ff03f0b1SRussell King if (duplex == DUPLEX_FULL) 4070ff03f0b1SRussell King val |= MVNETA_GMAC_CONFIG_FULL_DUPLEX; 4071ff03f0b1SRussell King 4072ff03f0b1SRussell King if (tx_pause || rx_pause) 4073ff03f0b1SRussell King val |= MVNETA_GMAC_CONFIG_FLOW_CTRL; 4074ff03f0b1SRussell King 4075ff03f0b1SRussell King mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val); 4076ff03f0b1SRussell King } else { 4077ff03f0b1SRussell King /* When inband doesn't cover flow control or flow control is 4078ff03f0b1SRussell King * disabled, we need to manually configure it. This bit will 4079ff03f0b1SRussell King * only have effect if MVNETA_GMAC_AN_FLOW_CTRL_EN is unset. 4080ff03f0b1SRussell King */ 4081ff03f0b1SRussell King val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG); 4082ff03f0b1SRussell King val &= ~MVNETA_GMAC_CONFIG_FLOW_CTRL; 4083ff03f0b1SRussell King 4084ff03f0b1SRussell King if (tx_pause || rx_pause) 4085ff03f0b1SRussell King val |= MVNETA_GMAC_CONFIG_FLOW_CTRL; 4086ff03f0b1SRussell King 4087fc548b99SRussell King mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val); 4088fc548b99SRussell King } 4089fc548b99SRussell King 4090fc548b99SRussell King mvneta_port_up(pp); 40916d81f451SRussell King 40926d81f451SRussell King if (phy && pp->eee_enabled) { 40936d81f451SRussell King pp->eee_active = phy_init_eee(phy, 0) >= 0; 40946d81f451SRussell King mvneta_set_eee(pp, pp->eee_active && pp->tx_lpi_enabled); 40956d81f451SRussell King } 4096fc548b99SRussell King } 4097fc548b99SRussell King 4098503f9aa9SRussell King static const struct phylink_mac_ops mvneta_phylink_ops = { 4099503f9aa9SRussell King .validate = mvneta_validate, 4100d46b7e4fSRussell King .mac_pcs_get_state = mvneta_mac_pcs_get_state, 410122f4bf8aSRussell King .mac_an_restart = mvneta_mac_an_restart, 4102503f9aa9SRussell King .mac_config = mvneta_mac_config, 4103503f9aa9SRussell King .mac_link_down = mvneta_mac_link_down, 4104503f9aa9SRussell King .mac_link_up = mvneta_mac_link_up, 4105503f9aa9SRussell King }; 4106c5aff182SThomas Petazzoni 4107c5aff182SThomas Petazzoni static int mvneta_mdio_probe(struct mvneta_port *pp) 4108c5aff182SThomas Petazzoni { 410982960fffSJisheng Zhang struct ethtool_wolinfo wol = { .cmd = ETHTOOL_GWOL }; 4110503f9aa9SRussell King int err = phylink_of_phy_connect(pp->phylink, pp->dn, 0); 4111c5aff182SThomas Petazzoni 4112503f9aa9SRussell King if (err) 4113503f9aa9SRussell King netdev_err(pp->dev, "could not attach PHY: %d\n", err); 4114c5aff182SThomas Petazzoni 4115503f9aa9SRussell King phylink_ethtool_get_wol(pp->phylink, &wol); 411682960fffSJisheng Zhang device_set_wakeup_capable(&pp->dev->dev, !!wol.supported); 411782960fffSJisheng Zhang 411861b5cc20SDaniel González Cabanelas /* PHY WoL may be enabled but device wakeup disabled */ 411961b5cc20SDaniel González Cabanelas if (wol.supported) 412061b5cc20SDaniel González Cabanelas device_set_wakeup_enable(&pp->dev->dev, !!wol.wolopts); 412161b5cc20SDaniel González Cabanelas 4122503f9aa9SRussell King return err; 4123c5aff182SThomas Petazzoni } 4124c5aff182SThomas Petazzoni 4125c5aff182SThomas Petazzoni static void mvneta_mdio_remove(struct mvneta_port *pp) 4126c5aff182SThomas Petazzoni { 4127503f9aa9SRussell King phylink_disconnect_phy(pp->phylink); 4128c5aff182SThomas Petazzoni } 4129c5aff182SThomas Petazzoni 4130120cfa50SGregory CLEMENT /* Electing a CPU must be done in an atomic way: it should be done 4131120cfa50SGregory CLEMENT * after or before the removal/insertion of a CPU and this function is 4132120cfa50SGregory CLEMENT * not reentrant. 4133120cfa50SGregory CLEMENT */ 4134f8642885SMaxime Ripard static void mvneta_percpu_elect(struct mvneta_port *pp) 4135f8642885SMaxime Ripard { 4136cad5d847SGregory CLEMENT int elected_cpu = 0, max_cpu, cpu, i = 0; 4137f8642885SMaxime Ripard 4138cad5d847SGregory CLEMENT /* Use the cpu associated to the rxq when it is online, in all 4139cad5d847SGregory CLEMENT * the other cases, use the cpu 0 which can't be offline. 4140cad5d847SGregory CLEMENT */ 4141cad5d847SGregory CLEMENT if (cpu_online(pp->rxq_def)) 4142cad5d847SGregory CLEMENT elected_cpu = pp->rxq_def; 4143cad5d847SGregory CLEMENT 41442dcf75e2SGregory CLEMENT max_cpu = num_present_cpus(); 4145f8642885SMaxime Ripard 4146f8642885SMaxime Ripard for_each_online_cpu(cpu) { 41472dcf75e2SGregory CLEMENT int rxq_map = 0, txq_map = 0; 41482dcf75e2SGregory CLEMENT int rxq; 41492dcf75e2SGregory CLEMENT 41502dcf75e2SGregory CLEMENT for (rxq = 0; rxq < rxq_number; rxq++) 41512dcf75e2SGregory CLEMENT if ((rxq % max_cpu) == cpu) 41522dcf75e2SGregory CLEMENT rxq_map |= MVNETA_CPU_RXQ_ACCESS(rxq); 41532dcf75e2SGregory CLEMENT 4154cad5d847SGregory CLEMENT if (cpu == elected_cpu) 415550bf8cb6SGregory CLEMENT /* Map the default receive queue queue to the 415650bf8cb6SGregory CLEMENT * elected CPU 4157f8642885SMaxime Ripard */ 41582dcf75e2SGregory CLEMENT rxq_map |= MVNETA_CPU_RXQ_ACCESS(pp->rxq_def); 415950bf8cb6SGregory CLEMENT 416050bf8cb6SGregory CLEMENT /* We update the TX queue map only if we have one 416150bf8cb6SGregory CLEMENT * queue. In this case we associate the TX queue to 416250bf8cb6SGregory CLEMENT * the CPU bound to the default RX queue 416350bf8cb6SGregory CLEMENT */ 416450bf8cb6SGregory CLEMENT if (txq_number == 1) 4165cad5d847SGregory CLEMENT txq_map = (cpu == elected_cpu) ? 416650bf8cb6SGregory CLEMENT MVNETA_CPU_TXQ_ACCESS(1) : 0; 416750bf8cb6SGregory CLEMENT else 416850bf8cb6SGregory CLEMENT txq_map = mvreg_read(pp, MVNETA_CPU_MAP(cpu)) & 416950bf8cb6SGregory CLEMENT MVNETA_CPU_TXQ_ACCESS_ALL_MASK; 417050bf8cb6SGregory CLEMENT 41712dcf75e2SGregory CLEMENT mvreg_write(pp, MVNETA_CPU_MAP(cpu), rxq_map | txq_map); 41722dcf75e2SGregory CLEMENT 41732dcf75e2SGregory CLEMENT /* Update the interrupt mask on each CPU according the 41742dcf75e2SGregory CLEMENT * new mapping 41752dcf75e2SGregory CLEMENT */ 41762dcf75e2SGregory CLEMENT smp_call_function_single(cpu, mvneta_percpu_unmask_interrupt, 4177f8642885SMaxime Ripard pp, true); 4178f8642885SMaxime Ripard i++; 41792dcf75e2SGregory CLEMENT 4180f8642885SMaxime Ripard } 4181f8642885SMaxime Ripard }; 4182f8642885SMaxime Ripard 418384a3f4dbSSebastian Andrzej Siewior static int mvneta_cpu_online(unsigned int cpu, struct hlist_node *node) 4184f8642885SMaxime Ripard { 418584a3f4dbSSebastian Andrzej Siewior int other_cpu; 418684a3f4dbSSebastian Andrzej Siewior struct mvneta_port *pp = hlist_entry_safe(node, struct mvneta_port, 418784a3f4dbSSebastian Andrzej Siewior node_online); 4188f8642885SMaxime Ripard struct mvneta_pcpu_port *port = per_cpu_ptr(pp->ports, cpu); 4189f8642885SMaxime Ripard 419084a3f4dbSSebastian Andrzej Siewior 4191120cfa50SGregory CLEMENT spin_lock(&pp->lock); 419284a3f4dbSSebastian Andrzej Siewior /* 419384a3f4dbSSebastian Andrzej Siewior * Configuring the driver for a new CPU while the driver is 419484a3f4dbSSebastian Andrzej Siewior * stopping is racy, so just avoid it. 4195120cfa50SGregory CLEMENT */ 4196120cfa50SGregory CLEMENT if (pp->is_stopped) { 4197120cfa50SGregory CLEMENT spin_unlock(&pp->lock); 419884a3f4dbSSebastian Andrzej Siewior return 0; 4199120cfa50SGregory CLEMENT } 4200f8642885SMaxime Ripard netif_tx_stop_all_queues(pp->dev); 4201f8642885SMaxime Ripard 420284a3f4dbSSebastian Andrzej Siewior /* 420384a3f4dbSSebastian Andrzej Siewior * We have to synchronise on tha napi of each CPU except the one 420484a3f4dbSSebastian Andrzej Siewior * just being woken up 4205f8642885SMaxime Ripard */ 4206f8642885SMaxime Ripard for_each_online_cpu(other_cpu) { 4207f8642885SMaxime Ripard if (other_cpu != cpu) { 4208f8642885SMaxime Ripard struct mvneta_pcpu_port *other_port = 4209f8642885SMaxime Ripard per_cpu_ptr(pp->ports, other_cpu); 4210f8642885SMaxime Ripard 4211f8642885SMaxime Ripard napi_synchronize(&other_port->napi); 4212f8642885SMaxime Ripard } 4213f8642885SMaxime Ripard } 4214f8642885SMaxime Ripard 4215f8642885SMaxime Ripard /* Mask all ethernet port interrupts */ 4216db488c10SGregory CLEMENT on_each_cpu(mvneta_percpu_mask_interrupt, pp, true); 4217f8642885SMaxime Ripard napi_enable(&port->napi); 4218f8642885SMaxime Ripard 421984a3f4dbSSebastian Andrzej Siewior /* 422084a3f4dbSSebastian Andrzej Siewior * Enable per-CPU interrupts on the CPU that is 42212dcf75e2SGregory CLEMENT * brought up. 42222dcf75e2SGregory CLEMENT */ 42230e28bf93SAnna-Maria Gleixner mvneta_percpu_enable(pp); 42242dcf75e2SGregory CLEMENT 422584a3f4dbSSebastian Andrzej Siewior /* 422684a3f4dbSSebastian Andrzej Siewior * Enable per-CPU interrupt on the one CPU we care 4227f8642885SMaxime Ripard * about. 4228f8642885SMaxime Ripard */ 4229f8642885SMaxime Ripard mvneta_percpu_elect(pp); 4230f8642885SMaxime Ripard 4231db488c10SGregory CLEMENT /* Unmask all ethernet port interrupts */ 4232db488c10SGregory CLEMENT on_each_cpu(mvneta_percpu_unmask_interrupt, pp, true); 4233f8642885SMaxime Ripard mvreg_write(pp, MVNETA_INTR_MISC_MASK, 4234f8642885SMaxime Ripard MVNETA_CAUSE_PHY_STATUS_CHANGE | 4235856b2cc5SRussell King MVNETA_CAUSE_LINK_CHANGE); 4236f8642885SMaxime Ripard netif_tx_start_all_queues(pp->dev); 4237120cfa50SGregory CLEMENT spin_unlock(&pp->lock); 423884a3f4dbSSebastian Andrzej Siewior return 0; 423984a3f4dbSSebastian Andrzej Siewior } 424084a3f4dbSSebastian Andrzej Siewior 424184a3f4dbSSebastian Andrzej Siewior static int mvneta_cpu_down_prepare(unsigned int cpu, struct hlist_node *node) 424284a3f4dbSSebastian Andrzej Siewior { 424384a3f4dbSSebastian Andrzej Siewior struct mvneta_port *pp = hlist_entry_safe(node, struct mvneta_port, 424484a3f4dbSSebastian Andrzej Siewior node_online); 424584a3f4dbSSebastian Andrzej Siewior struct mvneta_pcpu_port *port = per_cpu_ptr(pp->ports, cpu); 424684a3f4dbSSebastian Andrzej Siewior 424784a3f4dbSSebastian Andrzej Siewior /* 424884a3f4dbSSebastian Andrzej Siewior * Thanks to this lock we are sure that any pending cpu election is 424984a3f4dbSSebastian Andrzej Siewior * done. 42505888511eSGregory CLEMENT */ 42515888511eSGregory CLEMENT spin_lock(&pp->lock); 4252f8642885SMaxime Ripard /* Mask all ethernet port interrupts */ 4253db488c10SGregory CLEMENT on_each_cpu(mvneta_percpu_mask_interrupt, pp, true); 42545888511eSGregory CLEMENT spin_unlock(&pp->lock); 4255f8642885SMaxime Ripard 4256f8642885SMaxime Ripard napi_synchronize(&port->napi); 4257f8642885SMaxime Ripard napi_disable(&port->napi); 425884a3f4dbSSebastian Andrzej Siewior /* Disable per-CPU interrupts on the CPU that is brought down. */ 42590e28bf93SAnna-Maria Gleixner mvneta_percpu_disable(pp); 426084a3f4dbSSebastian Andrzej Siewior return 0; 426184a3f4dbSSebastian Andrzej Siewior } 4262f8642885SMaxime Ripard 426384a3f4dbSSebastian Andrzej Siewior static int mvneta_cpu_dead(unsigned int cpu, struct hlist_node *node) 426484a3f4dbSSebastian Andrzej Siewior { 426584a3f4dbSSebastian Andrzej Siewior struct mvneta_port *pp = hlist_entry_safe(node, struct mvneta_port, 426684a3f4dbSSebastian Andrzej Siewior node_dead); 426784a3f4dbSSebastian Andrzej Siewior 4268f8642885SMaxime Ripard /* Check if a new CPU must be elected now this on is down */ 4269120cfa50SGregory CLEMENT spin_lock(&pp->lock); 4270f8642885SMaxime Ripard mvneta_percpu_elect(pp); 4271120cfa50SGregory CLEMENT spin_unlock(&pp->lock); 4272f8642885SMaxime Ripard /* Unmask all ethernet port interrupts */ 4273db488c10SGregory CLEMENT on_each_cpu(mvneta_percpu_unmask_interrupt, pp, true); 4274f8642885SMaxime Ripard mvreg_write(pp, MVNETA_INTR_MISC_MASK, 4275f8642885SMaxime Ripard MVNETA_CAUSE_PHY_STATUS_CHANGE | 4276856b2cc5SRussell King MVNETA_CAUSE_LINK_CHANGE); 4277f8642885SMaxime Ripard netif_tx_start_all_queues(pp->dev); 427884a3f4dbSSebastian Andrzej Siewior return 0; 4279f8642885SMaxime Ripard } 4280f8642885SMaxime Ripard 4281c5aff182SThomas Petazzoni static int mvneta_open(struct net_device *dev) 4282c5aff182SThomas Petazzoni { 4283c5aff182SThomas Petazzoni struct mvneta_port *pp = netdev_priv(dev); 42846b125d63SGregory CLEMENT int ret; 4285c5aff182SThomas Petazzoni 4286c5aff182SThomas Petazzoni pp->pkt_size = MVNETA_RX_PKT_SIZE(pp->dev->mtu); 4287c5aff182SThomas Petazzoni 4288c5aff182SThomas Petazzoni ret = mvneta_setup_rxqs(pp); 4289c5aff182SThomas Petazzoni if (ret) 4290c5aff182SThomas Petazzoni return ret; 4291c5aff182SThomas Petazzoni 4292c5aff182SThomas Petazzoni ret = mvneta_setup_txqs(pp); 4293c5aff182SThomas Petazzoni if (ret) 4294c5aff182SThomas Petazzoni goto err_cleanup_rxqs; 4295c5aff182SThomas Petazzoni 4296c5aff182SThomas Petazzoni /* Connect to port interrupt line */ 42972636ac3cSMarcin Wojtas if (pp->neta_armada3700) 42982636ac3cSMarcin Wojtas ret = request_irq(pp->dev->irq, mvneta_isr, 0, 42992636ac3cSMarcin Wojtas dev->name, pp); 43002636ac3cSMarcin Wojtas else 43012636ac3cSMarcin Wojtas ret = request_percpu_irq(pp->dev->irq, mvneta_percpu_isr, 43022636ac3cSMarcin Wojtas dev->name, pp->ports); 4303c5aff182SThomas Petazzoni if (ret) { 4304c5aff182SThomas Petazzoni netdev_err(pp->dev, "cannot request irq %d\n", pp->dev->irq); 4305c5aff182SThomas Petazzoni goto err_cleanup_txqs; 4306c5aff182SThomas Petazzoni } 4307c5aff182SThomas Petazzoni 43082636ac3cSMarcin Wojtas if (!pp->neta_armada3700) { 43092dcf75e2SGregory CLEMENT /* Enable per-CPU interrupt on all the CPU to handle our RX 43102dcf75e2SGregory CLEMENT * queue interrupts 43112dcf75e2SGregory CLEMENT */ 43126b125d63SGregory CLEMENT on_each_cpu(mvneta_percpu_enable, pp, true); 43132dcf75e2SGregory CLEMENT 4314120cfa50SGregory CLEMENT pp->is_stopped = false; 4315f8642885SMaxime Ripard /* Register a CPU notifier to handle the case where our CPU 4316f8642885SMaxime Ripard * might be taken offline. 4317f8642885SMaxime Ripard */ 431884a3f4dbSSebastian Andrzej Siewior ret = cpuhp_state_add_instance_nocalls(online_hpstate, 431984a3f4dbSSebastian Andrzej Siewior &pp->node_online); 432084a3f4dbSSebastian Andrzej Siewior if (ret) 432184a3f4dbSSebastian Andrzej Siewior goto err_free_irq; 432284a3f4dbSSebastian Andrzej Siewior 432384a3f4dbSSebastian Andrzej Siewior ret = cpuhp_state_add_instance_nocalls(CPUHP_NET_MVNETA_DEAD, 432484a3f4dbSSebastian Andrzej Siewior &pp->node_dead); 432584a3f4dbSSebastian Andrzej Siewior if (ret) 432684a3f4dbSSebastian Andrzej Siewior goto err_free_online_hp; 43272636ac3cSMarcin Wojtas } 4328f8642885SMaxime Ripard 4329c5aff182SThomas Petazzoni ret = mvneta_mdio_probe(pp); 4330c5aff182SThomas Petazzoni if (ret < 0) { 4331c5aff182SThomas Petazzoni netdev_err(dev, "cannot probe MDIO bus\n"); 433284a3f4dbSSebastian Andrzej Siewior goto err_free_dead_hp; 4333c5aff182SThomas Petazzoni } 4334c5aff182SThomas Petazzoni 4335c5aff182SThomas Petazzoni mvneta_start_dev(pp); 4336c5aff182SThomas Petazzoni 4337c5aff182SThomas Petazzoni return 0; 4338c5aff182SThomas Petazzoni 433984a3f4dbSSebastian Andrzej Siewior err_free_dead_hp: 43402636ac3cSMarcin Wojtas if (!pp->neta_armada3700) 434184a3f4dbSSebastian Andrzej Siewior cpuhp_state_remove_instance_nocalls(CPUHP_NET_MVNETA_DEAD, 434284a3f4dbSSebastian Andrzej Siewior &pp->node_dead); 434384a3f4dbSSebastian Andrzej Siewior err_free_online_hp: 43442636ac3cSMarcin Wojtas if (!pp->neta_armada3700) 43452636ac3cSMarcin Wojtas cpuhp_state_remove_instance_nocalls(online_hpstate, 43462636ac3cSMarcin Wojtas &pp->node_online); 4347c5aff182SThomas Petazzoni err_free_irq: 43482636ac3cSMarcin Wojtas if (pp->neta_armada3700) { 43492636ac3cSMarcin Wojtas free_irq(pp->dev->irq, pp); 43502636ac3cSMarcin Wojtas } else { 43513d8c4530SRussell King - ARM Linux on_each_cpu(mvneta_percpu_disable, pp, true); 435212bb03b4SMaxime Ripard free_percpu_irq(pp->dev->irq, pp->ports); 43532636ac3cSMarcin Wojtas } 4354c5aff182SThomas Petazzoni err_cleanup_txqs: 4355c5aff182SThomas Petazzoni mvneta_cleanup_txqs(pp); 4356c5aff182SThomas Petazzoni err_cleanup_rxqs: 4357c5aff182SThomas Petazzoni mvneta_cleanup_rxqs(pp); 4358c5aff182SThomas Petazzoni return ret; 4359c5aff182SThomas Petazzoni } 4360c5aff182SThomas Petazzoni 4361c5aff182SThomas Petazzoni /* Stop the port, free port interrupt line */ 4362c5aff182SThomas Petazzoni static int mvneta_stop(struct net_device *dev) 4363c5aff182SThomas Petazzoni { 4364c5aff182SThomas Petazzoni struct mvneta_port *pp = netdev_priv(dev); 4365c5aff182SThomas Petazzoni 43662636ac3cSMarcin Wojtas if (!pp->neta_armada3700) { 4367120cfa50SGregory CLEMENT /* Inform that we are stopping so we don't want to setup the 43681c2722a9SGregory CLEMENT * driver for new CPUs in the notifiers. The code of the 43691c2722a9SGregory CLEMENT * notifier for CPU online is protected by the same spinlock, 43701c2722a9SGregory CLEMENT * so when we get the lock, the notifer work is done. 4371120cfa50SGregory CLEMENT */ 4372120cfa50SGregory CLEMENT spin_lock(&pp->lock); 4373120cfa50SGregory CLEMENT pp->is_stopped = true; 43741c2722a9SGregory CLEMENT spin_unlock(&pp->lock); 43751c2722a9SGregory CLEMENT 4376c5aff182SThomas Petazzoni mvneta_stop_dev(pp); 4377c5aff182SThomas Petazzoni mvneta_mdio_remove(pp); 437884a3f4dbSSebastian Andrzej Siewior 4379d26aac2dSDan Carpenter cpuhp_state_remove_instance_nocalls(online_hpstate, 4380d26aac2dSDan Carpenter &pp->node_online); 438184a3f4dbSSebastian Andrzej Siewior cpuhp_state_remove_instance_nocalls(CPUHP_NET_MVNETA_DEAD, 438284a3f4dbSSebastian Andrzej Siewior &pp->node_dead); 4383129219e4SGregory CLEMENT on_each_cpu(mvneta_percpu_disable, pp, true); 438412bb03b4SMaxime Ripard free_percpu_irq(dev->irq, pp->ports); 43852636ac3cSMarcin Wojtas } else { 43862636ac3cSMarcin Wojtas mvneta_stop_dev(pp); 43872636ac3cSMarcin Wojtas mvneta_mdio_remove(pp); 43882636ac3cSMarcin Wojtas free_irq(dev->irq, pp); 43892636ac3cSMarcin Wojtas } 43902636ac3cSMarcin Wojtas 4391c5aff182SThomas Petazzoni mvneta_cleanup_rxqs(pp); 4392c5aff182SThomas Petazzoni mvneta_cleanup_txqs(pp); 4393c5aff182SThomas Petazzoni 4394c5aff182SThomas Petazzoni return 0; 4395c5aff182SThomas Petazzoni } 4396c5aff182SThomas Petazzoni 439715f59456SThomas Petazzoni static int mvneta_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) 439815f59456SThomas Petazzoni { 4399503f9aa9SRussell King struct mvneta_port *pp = netdev_priv(dev); 440015f59456SThomas Petazzoni 4401503f9aa9SRussell King return phylink_mii_ioctl(pp->phylink, ifr, cmd); 440215f59456SThomas Petazzoni } 440315f59456SThomas Petazzoni 44040db51da7SLorenzo Bianconi static int mvneta_xdp_setup(struct net_device *dev, struct bpf_prog *prog, 44050db51da7SLorenzo Bianconi struct netlink_ext_ack *extack) 44060db51da7SLorenzo Bianconi { 44070db51da7SLorenzo Bianconi bool need_update, running = netif_running(dev); 44080db51da7SLorenzo Bianconi struct mvneta_port *pp = netdev_priv(dev); 44090db51da7SLorenzo Bianconi struct bpf_prog *old_prog; 44100db51da7SLorenzo Bianconi 44110db51da7SLorenzo Bianconi if (prog && dev->mtu > MVNETA_MAX_RX_BUF_SIZE) { 44120db51da7SLorenzo Bianconi NL_SET_ERR_MSG_MOD(extack, "Jumbo frames not supported on XDP"); 44130db51da7SLorenzo Bianconi return -EOPNOTSUPP; 44140db51da7SLorenzo Bianconi } 44150db51da7SLorenzo Bianconi 441679572c98SSven Auhagen if (pp->bm_priv) { 441779572c98SSven Auhagen NL_SET_ERR_MSG_MOD(extack, 441879572c98SSven Auhagen "Hardware Buffer Management not supported on XDP"); 441979572c98SSven Auhagen return -EOPNOTSUPP; 442079572c98SSven Auhagen } 442179572c98SSven Auhagen 44220db51da7SLorenzo Bianconi need_update = !!pp->xdp_prog != !!prog; 44230db51da7SLorenzo Bianconi if (running && need_update) 44240db51da7SLorenzo Bianconi mvneta_stop(dev); 44250db51da7SLorenzo Bianconi 44260db51da7SLorenzo Bianconi old_prog = xchg(&pp->xdp_prog, prog); 44270db51da7SLorenzo Bianconi if (old_prog) 44280db51da7SLorenzo Bianconi bpf_prog_put(old_prog); 44290db51da7SLorenzo Bianconi 44300db51da7SLorenzo Bianconi if (running && need_update) 44310db51da7SLorenzo Bianconi return mvneta_open(dev); 44320db51da7SLorenzo Bianconi 44330db51da7SLorenzo Bianconi return 0; 44340db51da7SLorenzo Bianconi } 44350db51da7SLorenzo Bianconi 44360db51da7SLorenzo Bianconi static int mvneta_xdp(struct net_device *dev, struct netdev_bpf *xdp) 44370db51da7SLorenzo Bianconi { 44380db51da7SLorenzo Bianconi switch (xdp->command) { 44390db51da7SLorenzo Bianconi case XDP_SETUP_PROG: 44400db51da7SLorenzo Bianconi return mvneta_xdp_setup(dev, xdp->prog, xdp->extack); 44410db51da7SLorenzo Bianconi default: 44420db51da7SLorenzo Bianconi return -EINVAL; 44430db51da7SLorenzo Bianconi } 44440db51da7SLorenzo Bianconi } 44450db51da7SLorenzo Bianconi 4446c5aff182SThomas Petazzoni /* Ethtool methods */ 4447c5aff182SThomas Petazzoni 4448013ad40dSPhilippe Reynes /* Set link ksettings (phy address, speed) for ethtools */ 44492dc0d2b4SBaoyou Xie static int 44502dc0d2b4SBaoyou Xie mvneta_ethtool_set_link_ksettings(struct net_device *ndev, 4451013ad40dSPhilippe Reynes const struct ethtool_link_ksettings *cmd) 4452c5aff182SThomas Petazzoni { 4453013ad40dSPhilippe Reynes struct mvneta_port *pp = netdev_priv(ndev); 4454c5aff182SThomas Petazzoni 4455503f9aa9SRussell King return phylink_ethtool_ksettings_set(pp->phylink, cmd); 44560c0744fcSStas Sergeev } 44570c0744fcSStas Sergeev 4458503f9aa9SRussell King /* Get link ksettings for ethtools */ 4459503f9aa9SRussell King static int 4460503f9aa9SRussell King mvneta_ethtool_get_link_ksettings(struct net_device *ndev, 4461503f9aa9SRussell King struct ethtool_link_ksettings *cmd) 4462503f9aa9SRussell King { 4463503f9aa9SRussell King struct mvneta_port *pp = netdev_priv(ndev); 44640c0744fcSStas Sergeev 4465503f9aa9SRussell King return phylink_ethtool_ksettings_get(pp->phylink, cmd); 44660c0744fcSStas Sergeev } 44670c0744fcSStas Sergeev 4468503f9aa9SRussell King static int mvneta_ethtool_nway_reset(struct net_device *dev) 4469503f9aa9SRussell King { 4470503f9aa9SRussell King struct mvneta_port *pp = netdev_priv(dev); 4471503f9aa9SRussell King 4472503f9aa9SRussell King return phylink_ethtool_nway_reset(pp->phylink); 4473c5aff182SThomas Petazzoni } 4474c5aff182SThomas Petazzoni 4475c5aff182SThomas Petazzoni /* Set interrupt coalescing for ethtools */ 4476c5aff182SThomas Petazzoni static int mvneta_ethtool_set_coalesce(struct net_device *dev, 4477c5aff182SThomas Petazzoni struct ethtool_coalesce *c) 4478c5aff182SThomas Petazzoni { 4479c5aff182SThomas Petazzoni struct mvneta_port *pp = netdev_priv(dev); 4480c5aff182SThomas Petazzoni int queue; 4481c5aff182SThomas Petazzoni 4482c5aff182SThomas Petazzoni for (queue = 0; queue < rxq_number; queue++) { 4483c5aff182SThomas Petazzoni struct mvneta_rx_queue *rxq = &pp->rxqs[queue]; 4484c5aff182SThomas Petazzoni rxq->time_coal = c->rx_coalesce_usecs; 4485c5aff182SThomas Petazzoni rxq->pkts_coal = c->rx_max_coalesced_frames; 4486c5aff182SThomas Petazzoni mvneta_rx_pkts_coal_set(pp, rxq, rxq->pkts_coal); 4487c5aff182SThomas Petazzoni mvneta_rx_time_coal_set(pp, rxq, rxq->time_coal); 4488c5aff182SThomas Petazzoni } 4489c5aff182SThomas Petazzoni 4490c5aff182SThomas Petazzoni for (queue = 0; queue < txq_number; queue++) { 4491c5aff182SThomas Petazzoni struct mvneta_tx_queue *txq = &pp->txqs[queue]; 4492c5aff182SThomas Petazzoni txq->done_pkts_coal = c->tx_max_coalesced_frames; 4493c5aff182SThomas Petazzoni mvneta_tx_done_pkts_coal_set(pp, txq, txq->done_pkts_coal); 4494c5aff182SThomas Petazzoni } 4495c5aff182SThomas Petazzoni 4496c5aff182SThomas Petazzoni return 0; 4497c5aff182SThomas Petazzoni } 4498c5aff182SThomas Petazzoni 4499c5aff182SThomas Petazzoni /* get coalescing for ethtools */ 4500c5aff182SThomas Petazzoni static int mvneta_ethtool_get_coalesce(struct net_device *dev, 4501c5aff182SThomas Petazzoni struct ethtool_coalesce *c) 4502c5aff182SThomas Petazzoni { 4503c5aff182SThomas Petazzoni struct mvneta_port *pp = netdev_priv(dev); 4504c5aff182SThomas Petazzoni 4505c5aff182SThomas Petazzoni c->rx_coalesce_usecs = pp->rxqs[0].time_coal; 4506c5aff182SThomas Petazzoni c->rx_max_coalesced_frames = pp->rxqs[0].pkts_coal; 4507c5aff182SThomas Petazzoni 4508c5aff182SThomas Petazzoni c->tx_max_coalesced_frames = pp->txqs[0].done_pkts_coal; 4509c5aff182SThomas Petazzoni return 0; 4510c5aff182SThomas Petazzoni } 4511c5aff182SThomas Petazzoni 4512c5aff182SThomas Petazzoni 4513c5aff182SThomas Petazzoni static void mvneta_ethtool_get_drvinfo(struct net_device *dev, 4514c5aff182SThomas Petazzoni struct ethtool_drvinfo *drvinfo) 4515c5aff182SThomas Petazzoni { 4516c5aff182SThomas Petazzoni strlcpy(drvinfo->driver, MVNETA_DRIVER_NAME, 4517c5aff182SThomas Petazzoni sizeof(drvinfo->driver)); 4518c5aff182SThomas Petazzoni strlcpy(drvinfo->version, MVNETA_DRIVER_VERSION, 4519c5aff182SThomas Petazzoni sizeof(drvinfo->version)); 4520c5aff182SThomas Petazzoni strlcpy(drvinfo->bus_info, dev_name(&dev->dev), 4521c5aff182SThomas Petazzoni sizeof(drvinfo->bus_info)); 4522c5aff182SThomas Petazzoni } 4523c5aff182SThomas Petazzoni 4524c5aff182SThomas Petazzoni 4525c5aff182SThomas Petazzoni static void mvneta_ethtool_get_ringparam(struct net_device *netdev, 4526c5aff182SThomas Petazzoni struct ethtool_ringparam *ring) 4527c5aff182SThomas Petazzoni { 4528c5aff182SThomas Petazzoni struct mvneta_port *pp = netdev_priv(netdev); 4529c5aff182SThomas Petazzoni 4530c5aff182SThomas Petazzoni ring->rx_max_pending = MVNETA_MAX_RXD; 4531c5aff182SThomas Petazzoni ring->tx_max_pending = MVNETA_MAX_TXD; 4532c5aff182SThomas Petazzoni ring->rx_pending = pp->rx_ring_size; 4533c5aff182SThomas Petazzoni ring->tx_pending = pp->tx_ring_size; 4534c5aff182SThomas Petazzoni } 4535c5aff182SThomas Petazzoni 4536c5aff182SThomas Petazzoni static int mvneta_ethtool_set_ringparam(struct net_device *dev, 4537c5aff182SThomas Petazzoni struct ethtool_ringparam *ring) 4538c5aff182SThomas Petazzoni { 4539c5aff182SThomas Petazzoni struct mvneta_port *pp = netdev_priv(dev); 4540c5aff182SThomas Petazzoni 4541c5aff182SThomas Petazzoni if ((ring->rx_pending == 0) || (ring->tx_pending == 0)) 4542c5aff182SThomas Petazzoni return -EINVAL; 4543c5aff182SThomas Petazzoni pp->rx_ring_size = ring->rx_pending < MVNETA_MAX_RXD ? 4544c5aff182SThomas Petazzoni ring->rx_pending : MVNETA_MAX_RXD; 45458eef5f97SEzequiel Garcia 45468eef5f97SEzequiel Garcia pp->tx_ring_size = clamp_t(u16, ring->tx_pending, 45478eef5f97SEzequiel Garcia MVNETA_MAX_SKB_DESCS * 2, MVNETA_MAX_TXD); 45488eef5f97SEzequiel Garcia if (pp->tx_ring_size != ring->tx_pending) 45498eef5f97SEzequiel Garcia netdev_warn(dev, "TX queue size set to %u (requested %u)\n", 45508eef5f97SEzequiel Garcia pp->tx_ring_size, ring->tx_pending); 4551c5aff182SThomas Petazzoni 4552c5aff182SThomas Petazzoni if (netif_running(dev)) { 4553c5aff182SThomas Petazzoni mvneta_stop(dev); 4554c5aff182SThomas Petazzoni if (mvneta_open(dev)) { 4555c5aff182SThomas Petazzoni netdev_err(dev, 4556c5aff182SThomas Petazzoni "error on opening device after ring param change\n"); 4557c5aff182SThomas Petazzoni return -ENOMEM; 4558c5aff182SThomas Petazzoni } 4559c5aff182SThomas Petazzoni } 4560c5aff182SThomas Petazzoni 4561c5aff182SThomas Petazzoni return 0; 4562c5aff182SThomas Petazzoni } 4563c5aff182SThomas Petazzoni 45644932a918SRussell King static void mvneta_ethtool_get_pauseparam(struct net_device *dev, 45654932a918SRussell King struct ethtool_pauseparam *pause) 45664932a918SRussell King { 45674932a918SRussell King struct mvneta_port *pp = netdev_priv(dev); 45684932a918SRussell King 45694932a918SRussell King phylink_ethtool_get_pauseparam(pp->phylink, pause); 45704932a918SRussell King } 45714932a918SRussell King 45724932a918SRussell King static int mvneta_ethtool_set_pauseparam(struct net_device *dev, 45734932a918SRussell King struct ethtool_pauseparam *pause) 45744932a918SRussell King { 45754932a918SRussell King struct mvneta_port *pp = netdev_priv(dev); 45764932a918SRussell King 45774932a918SRussell King return phylink_ethtool_set_pauseparam(pp->phylink, pause); 45784932a918SRussell King } 45794932a918SRussell King 45809b0cdefaSRussell King static void mvneta_ethtool_get_strings(struct net_device *netdev, u32 sset, 45819b0cdefaSRussell King u8 *data) 45829b0cdefaSRussell King { 45839b0cdefaSRussell King if (sset == ETH_SS_STATS) { 45849b0cdefaSRussell King int i; 45859b0cdefaSRussell King 45869b0cdefaSRussell King for (i = 0; i < ARRAY_SIZE(mvneta_statistics); i++) 45879b0cdefaSRussell King memcpy(data + i * ETH_GSTRING_LEN, 45889b0cdefaSRussell King mvneta_statistics[i].name, ETH_GSTRING_LEN); 45899b0cdefaSRussell King } 45909b0cdefaSRussell King } 45919b0cdefaSRussell King 45929ac41f3cSLorenzo Bianconi static void 45939ac41f3cSLorenzo Bianconi mvneta_ethtool_update_pcpu_stats(struct mvneta_port *pp, 45949ac41f3cSLorenzo Bianconi struct mvneta_ethtool_stats *es) 45959ac41f3cSLorenzo Bianconi { 45969ac41f3cSLorenzo Bianconi unsigned int start; 45979ac41f3cSLorenzo Bianconi int cpu; 45989ac41f3cSLorenzo Bianconi 45999ac41f3cSLorenzo Bianconi for_each_possible_cpu(cpu) { 46009ac41f3cSLorenzo Bianconi struct mvneta_pcpu_stats *stats; 46019ac41f3cSLorenzo Bianconi u64 skb_alloc_error; 46029ac41f3cSLorenzo Bianconi u64 refill_error; 46033d866523SLorenzo Bianconi u64 xdp_redirect; 460415070919SJesper Dangaard Brouer u64 xdp_xmit_err; 460515070919SJesper Dangaard Brouer u64 xdp_tx_err; 46063d866523SLorenzo Bianconi u64 xdp_pass; 46073d866523SLorenzo Bianconi u64 xdp_drop; 46087d51a015SLorenzo Bianconi u64 xdp_xmit; 46093d866523SLorenzo Bianconi u64 xdp_tx; 46109ac41f3cSLorenzo Bianconi 46119ac41f3cSLorenzo Bianconi stats = per_cpu_ptr(pp->stats, cpu); 46129ac41f3cSLorenzo Bianconi do { 46139ac41f3cSLorenzo Bianconi start = u64_stats_fetch_begin_irq(&stats->syncp); 46149ac41f3cSLorenzo Bianconi skb_alloc_error = stats->es.skb_alloc_error; 46159ac41f3cSLorenzo Bianconi refill_error = stats->es.refill_error; 46163d866523SLorenzo Bianconi xdp_redirect = stats->es.ps.xdp_redirect; 46173d866523SLorenzo Bianconi xdp_pass = stats->es.ps.xdp_pass; 46183d866523SLorenzo Bianconi xdp_drop = stats->es.ps.xdp_drop; 46197d51a015SLorenzo Bianconi xdp_xmit = stats->es.ps.xdp_xmit; 462015070919SJesper Dangaard Brouer xdp_xmit_err = stats->es.ps.xdp_xmit_err; 46213d866523SLorenzo Bianconi xdp_tx = stats->es.ps.xdp_tx; 462215070919SJesper Dangaard Brouer xdp_tx_err = stats->es.ps.xdp_tx_err; 46239ac41f3cSLorenzo Bianconi } while (u64_stats_fetch_retry_irq(&stats->syncp, start)); 46249ac41f3cSLorenzo Bianconi 46259ac41f3cSLorenzo Bianconi es->skb_alloc_error += skb_alloc_error; 46269ac41f3cSLorenzo Bianconi es->refill_error += refill_error; 46273d866523SLorenzo Bianconi es->ps.xdp_redirect += xdp_redirect; 46283d866523SLorenzo Bianconi es->ps.xdp_pass += xdp_pass; 46293d866523SLorenzo Bianconi es->ps.xdp_drop += xdp_drop; 46307d51a015SLorenzo Bianconi es->ps.xdp_xmit += xdp_xmit; 463115070919SJesper Dangaard Brouer es->ps.xdp_xmit_err += xdp_xmit_err; 46323d866523SLorenzo Bianconi es->ps.xdp_tx += xdp_tx; 463315070919SJesper Dangaard Brouer es->ps.xdp_tx_err += xdp_tx_err; 46349ac41f3cSLorenzo Bianconi } 46359ac41f3cSLorenzo Bianconi } 46369ac41f3cSLorenzo Bianconi 46379b0cdefaSRussell King static void mvneta_ethtool_update_stats(struct mvneta_port *pp) 46389b0cdefaSRussell King { 46399ac41f3cSLorenzo Bianconi struct mvneta_ethtool_stats stats = {}; 46409b0cdefaSRussell King const struct mvneta_statistic *s; 46419b0cdefaSRussell King void __iomem *base = pp->base; 46426d81f451SRussell King u32 high, low; 46436d81f451SRussell King u64 val; 46449b0cdefaSRussell King int i; 46459b0cdefaSRussell King 46469ac41f3cSLorenzo Bianconi mvneta_ethtool_update_pcpu_stats(pp, &stats); 46479b0cdefaSRussell King for (i = 0, s = mvneta_statistics; 46489b0cdefaSRussell King s < mvneta_statistics + ARRAY_SIZE(mvneta_statistics); 46499b0cdefaSRussell King s++, i++) { 46509b0cdefaSRussell King switch (s->type) { 46519b0cdefaSRussell King case T_REG_32: 46529b0cdefaSRussell King val = readl_relaxed(base + s->offset); 46539ac41f3cSLorenzo Bianconi pp->ethtool_stats[i] += val; 46549b0cdefaSRussell King break; 46559b0cdefaSRussell King case T_REG_64: 46569b0cdefaSRussell King /* Docs say to read low 32-bit then high */ 46579b0cdefaSRussell King low = readl_relaxed(base + s->offset); 46589b0cdefaSRussell King high = readl_relaxed(base + s->offset + 4); 46596d81f451SRussell King val = (u64)high << 32 | low; 46609ac41f3cSLorenzo Bianconi pp->ethtool_stats[i] += val; 46616d81f451SRussell King break; 46626d81f451SRussell King case T_SW: 46636d81f451SRussell King switch (s->offset) { 46646d81f451SRussell King case ETHTOOL_STAT_EEE_WAKEUP: 46656d81f451SRussell King val = phylink_get_eee_err(pp->phylink); 46669ac41f3cSLorenzo Bianconi pp->ethtool_stats[i] += val; 46679b0cdefaSRussell King break; 466817a96da6SGregory CLEMENT case ETHTOOL_STAT_SKB_ALLOC_ERR: 46699ac41f3cSLorenzo Bianconi pp->ethtool_stats[i] = stats.skb_alloc_error; 467017a96da6SGregory CLEMENT break; 467117a96da6SGregory CLEMENT case ETHTOOL_STAT_REFILL_ERR: 46729ac41f3cSLorenzo Bianconi pp->ethtool_stats[i] = stats.refill_error; 467317a96da6SGregory CLEMENT break; 46743d866523SLorenzo Bianconi case ETHTOOL_XDP_REDIRECT: 46753d866523SLorenzo Bianconi pp->ethtool_stats[i] = stats.ps.xdp_redirect; 46763d866523SLorenzo Bianconi break; 46773d866523SLorenzo Bianconi case ETHTOOL_XDP_PASS: 46783d866523SLorenzo Bianconi pp->ethtool_stats[i] = stats.ps.xdp_pass; 46793d866523SLorenzo Bianconi break; 46803d866523SLorenzo Bianconi case ETHTOOL_XDP_DROP: 46813d866523SLorenzo Bianconi pp->ethtool_stats[i] = stats.ps.xdp_drop; 46823d866523SLorenzo Bianconi break; 46833d866523SLorenzo Bianconi case ETHTOOL_XDP_TX: 46843d866523SLorenzo Bianconi pp->ethtool_stats[i] = stats.ps.xdp_tx; 46853d866523SLorenzo Bianconi break; 468615070919SJesper Dangaard Brouer case ETHTOOL_XDP_TX_ERR: 468715070919SJesper Dangaard Brouer pp->ethtool_stats[i] = stats.ps.xdp_tx_err; 468815070919SJesper Dangaard Brouer break; 46897d51a015SLorenzo Bianconi case ETHTOOL_XDP_XMIT: 46907d51a015SLorenzo Bianconi pp->ethtool_stats[i] = stats.ps.xdp_xmit; 46917d51a015SLorenzo Bianconi break; 469215070919SJesper Dangaard Brouer case ETHTOOL_XDP_XMIT_ERR: 469315070919SJesper Dangaard Brouer pp->ethtool_stats[i] = stats.ps.xdp_xmit_err; 469415070919SJesper Dangaard Brouer break; 46959b0cdefaSRussell King } 46966d81f451SRussell King break; 46976d81f451SRussell King } 46989b0cdefaSRussell King } 46999b0cdefaSRussell King } 47009b0cdefaSRussell King 47019b0cdefaSRussell King static void mvneta_ethtool_get_stats(struct net_device *dev, 47029b0cdefaSRussell King struct ethtool_stats *stats, u64 *data) 47039b0cdefaSRussell King { 47049b0cdefaSRussell King struct mvneta_port *pp = netdev_priv(dev); 47059b0cdefaSRussell King int i; 47069b0cdefaSRussell King 47079b0cdefaSRussell King mvneta_ethtool_update_stats(pp); 47089b0cdefaSRussell King 47099b0cdefaSRussell King for (i = 0; i < ARRAY_SIZE(mvneta_statistics); i++) 47109b0cdefaSRussell King *data++ = pp->ethtool_stats[i]; 47119b0cdefaSRussell King } 47129b0cdefaSRussell King 47139b0cdefaSRussell King static int mvneta_ethtool_get_sset_count(struct net_device *dev, int sset) 47149b0cdefaSRussell King { 47159b0cdefaSRussell King if (sset == ETH_SS_STATS) 47169b0cdefaSRussell King return ARRAY_SIZE(mvneta_statistics); 47179b0cdefaSRussell King return -EOPNOTSUPP; 47189b0cdefaSRussell King } 47199b0cdefaSRussell King 47209a401deaSGregory CLEMENT static u32 mvneta_ethtool_get_rxfh_indir_size(struct net_device *dev) 47219a401deaSGregory CLEMENT { 47229a401deaSGregory CLEMENT return MVNETA_RSS_LU_TABLE_SIZE; 47239a401deaSGregory CLEMENT } 47249a401deaSGregory CLEMENT 47259a401deaSGregory CLEMENT static int mvneta_ethtool_get_rxnfc(struct net_device *dev, 47269a401deaSGregory CLEMENT struct ethtool_rxnfc *info, 47279a401deaSGregory CLEMENT u32 *rules __always_unused) 47289a401deaSGregory CLEMENT { 47299a401deaSGregory CLEMENT switch (info->cmd) { 47309a401deaSGregory CLEMENT case ETHTOOL_GRXRINGS: 47319a401deaSGregory CLEMENT info->data = rxq_number; 47329a401deaSGregory CLEMENT return 0; 47339a401deaSGregory CLEMENT case ETHTOOL_GRXFH: 47349a401deaSGregory CLEMENT return -EOPNOTSUPP; 47359a401deaSGregory CLEMENT default: 47369a401deaSGregory CLEMENT return -EOPNOTSUPP; 47379a401deaSGregory CLEMENT } 47389a401deaSGregory CLEMENT } 47399a401deaSGregory CLEMENT 47409a401deaSGregory CLEMENT static int mvneta_config_rss(struct mvneta_port *pp) 47419a401deaSGregory CLEMENT { 47429a401deaSGregory CLEMENT int cpu; 47439a401deaSGregory CLEMENT u32 val; 47449a401deaSGregory CLEMENT 47459a401deaSGregory CLEMENT netif_tx_stop_all_queues(pp->dev); 47469a401deaSGregory CLEMENT 47476b125d63SGregory CLEMENT on_each_cpu(mvneta_percpu_mask_interrupt, pp, true); 47489a401deaSGregory CLEMENT 47490f5c6c30SJisheng Zhang if (!pp->neta_armada3700) { 47509a401deaSGregory CLEMENT /* We have to synchronise on the napi of each CPU */ 47519a401deaSGregory CLEMENT for_each_online_cpu(cpu) { 47529a401deaSGregory CLEMENT struct mvneta_pcpu_port *pcpu_port = 47539a401deaSGregory CLEMENT per_cpu_ptr(pp->ports, cpu); 47549a401deaSGregory CLEMENT 47559a401deaSGregory CLEMENT napi_synchronize(&pcpu_port->napi); 47569a401deaSGregory CLEMENT napi_disable(&pcpu_port->napi); 47579a401deaSGregory CLEMENT } 47580f5c6c30SJisheng Zhang } else { 47590f5c6c30SJisheng Zhang napi_synchronize(&pp->napi); 47600f5c6c30SJisheng Zhang napi_disable(&pp->napi); 47610f5c6c30SJisheng Zhang } 47629a401deaSGregory CLEMENT 47639a401deaSGregory CLEMENT pp->rxq_def = pp->indir[0]; 47649a401deaSGregory CLEMENT 47659a401deaSGregory CLEMENT /* Update unicast mapping */ 47669a401deaSGregory CLEMENT mvneta_set_rx_mode(pp->dev); 47679a401deaSGregory CLEMENT 47689a401deaSGregory CLEMENT /* Update val of portCfg register accordingly with all RxQueue types */ 47699a401deaSGregory CLEMENT val = MVNETA_PORT_CONFIG_DEFL_VALUE(pp->rxq_def); 47709a401deaSGregory CLEMENT mvreg_write(pp, MVNETA_PORT_CONFIG, val); 47719a401deaSGregory CLEMENT 47729a401deaSGregory CLEMENT /* Update the elected CPU matching the new rxq_def */ 4773120cfa50SGregory CLEMENT spin_lock(&pp->lock); 47749a401deaSGregory CLEMENT mvneta_percpu_elect(pp); 4775120cfa50SGregory CLEMENT spin_unlock(&pp->lock); 47769a401deaSGregory CLEMENT 47770f5c6c30SJisheng Zhang if (!pp->neta_armada3700) { 47789a401deaSGregory CLEMENT /* We have to synchronise on the napi of each CPU */ 47799a401deaSGregory CLEMENT for_each_online_cpu(cpu) { 47809a401deaSGregory CLEMENT struct mvneta_pcpu_port *pcpu_port = 47819a401deaSGregory CLEMENT per_cpu_ptr(pp->ports, cpu); 47829a401deaSGregory CLEMENT 47839a401deaSGregory CLEMENT napi_enable(&pcpu_port->napi); 47849a401deaSGregory CLEMENT } 47850f5c6c30SJisheng Zhang } else { 47860f5c6c30SJisheng Zhang napi_enable(&pp->napi); 47870f5c6c30SJisheng Zhang } 47889a401deaSGregory CLEMENT 47899a401deaSGregory CLEMENT netif_tx_start_all_queues(pp->dev); 47909a401deaSGregory CLEMENT 47919a401deaSGregory CLEMENT return 0; 47929a401deaSGregory CLEMENT } 47939a401deaSGregory CLEMENT 47949a401deaSGregory CLEMENT static int mvneta_ethtool_set_rxfh(struct net_device *dev, const u32 *indir, 47959a401deaSGregory CLEMENT const u8 *key, const u8 hfunc) 47969a401deaSGregory CLEMENT { 47979a401deaSGregory CLEMENT struct mvneta_port *pp = netdev_priv(dev); 47982636ac3cSMarcin Wojtas 47992636ac3cSMarcin Wojtas /* Current code for Armada 3700 doesn't support RSS features yet */ 48002636ac3cSMarcin Wojtas if (pp->neta_armada3700) 48012636ac3cSMarcin Wojtas return -EOPNOTSUPP; 48022636ac3cSMarcin Wojtas 48039a401deaSGregory CLEMENT /* We require at least one supported parameter to be changed 48049a401deaSGregory CLEMENT * and no change in any of the unsupported parameters 48059a401deaSGregory CLEMENT */ 48069a401deaSGregory CLEMENT if (key || 48079a401deaSGregory CLEMENT (hfunc != ETH_RSS_HASH_NO_CHANGE && hfunc != ETH_RSS_HASH_TOP)) 48089a401deaSGregory CLEMENT return -EOPNOTSUPP; 48099a401deaSGregory CLEMENT 48109a401deaSGregory CLEMENT if (!indir) 48119a401deaSGregory CLEMENT return 0; 48129a401deaSGregory CLEMENT 48139a401deaSGregory CLEMENT memcpy(pp->indir, indir, MVNETA_RSS_LU_TABLE_SIZE); 48149a401deaSGregory CLEMENT 48159a401deaSGregory CLEMENT return mvneta_config_rss(pp); 48169a401deaSGregory CLEMENT } 48179a401deaSGregory CLEMENT 48189a401deaSGregory CLEMENT static int mvneta_ethtool_get_rxfh(struct net_device *dev, u32 *indir, u8 *key, 48199a401deaSGregory CLEMENT u8 *hfunc) 48209a401deaSGregory CLEMENT { 48219a401deaSGregory CLEMENT struct mvneta_port *pp = netdev_priv(dev); 48229a401deaSGregory CLEMENT 48232636ac3cSMarcin Wojtas /* Current code for Armada 3700 doesn't support RSS features yet */ 48242636ac3cSMarcin Wojtas if (pp->neta_armada3700) 48252636ac3cSMarcin Wojtas return -EOPNOTSUPP; 48262636ac3cSMarcin Wojtas 48279a401deaSGregory CLEMENT if (hfunc) 48289a401deaSGregory CLEMENT *hfunc = ETH_RSS_HASH_TOP; 48299a401deaSGregory CLEMENT 48309a401deaSGregory CLEMENT if (!indir) 48319a401deaSGregory CLEMENT return 0; 48329a401deaSGregory CLEMENT 48339a401deaSGregory CLEMENT memcpy(indir, pp->indir, MVNETA_RSS_LU_TABLE_SIZE); 48349a401deaSGregory CLEMENT 48359a401deaSGregory CLEMENT return 0; 48369a401deaSGregory CLEMENT } 48379a401deaSGregory CLEMENT 4838b60a00f9SJingju Hou static void mvneta_ethtool_get_wol(struct net_device *dev, 4839b60a00f9SJingju Hou struct ethtool_wolinfo *wol) 4840b60a00f9SJingju Hou { 4841503f9aa9SRussell King struct mvneta_port *pp = netdev_priv(dev); 4842b60a00f9SJingju Hou 4843503f9aa9SRussell King phylink_ethtool_get_wol(pp->phylink, wol); 4844b60a00f9SJingju Hou } 4845b60a00f9SJingju Hou 4846b60a00f9SJingju Hou static int mvneta_ethtool_set_wol(struct net_device *dev, 4847b60a00f9SJingju Hou struct ethtool_wolinfo *wol) 4848b60a00f9SJingju Hou { 4849503f9aa9SRussell King struct mvneta_port *pp = netdev_priv(dev); 485082960fffSJisheng Zhang int ret; 485182960fffSJisheng Zhang 4852503f9aa9SRussell King ret = phylink_ethtool_set_wol(pp->phylink, wol); 485382960fffSJisheng Zhang if (!ret) 485482960fffSJisheng Zhang device_set_wakeup_enable(&dev->dev, !!wol->wolopts); 485582960fffSJisheng Zhang 485682960fffSJisheng Zhang return ret; 4857b60a00f9SJingju Hou } 4858b60a00f9SJingju Hou 48596d81f451SRussell King static int mvneta_ethtool_get_eee(struct net_device *dev, 48606d81f451SRussell King struct ethtool_eee *eee) 48616d81f451SRussell King { 48626d81f451SRussell King struct mvneta_port *pp = netdev_priv(dev); 48636d81f451SRussell King u32 lpi_ctl0; 48646d81f451SRussell King 48656d81f451SRussell King lpi_ctl0 = mvreg_read(pp, MVNETA_LPI_CTRL_0); 48666d81f451SRussell King 48676d81f451SRussell King eee->eee_enabled = pp->eee_enabled; 48686d81f451SRussell King eee->eee_active = pp->eee_active; 48696d81f451SRussell King eee->tx_lpi_enabled = pp->tx_lpi_enabled; 48706d81f451SRussell King eee->tx_lpi_timer = (lpi_ctl0) >> 8; // * scale; 48716d81f451SRussell King 48726d81f451SRussell King return phylink_ethtool_get_eee(pp->phylink, eee); 48736d81f451SRussell King } 48746d81f451SRussell King 48756d81f451SRussell King static int mvneta_ethtool_set_eee(struct net_device *dev, 48766d81f451SRussell King struct ethtool_eee *eee) 48776d81f451SRussell King { 48786d81f451SRussell King struct mvneta_port *pp = netdev_priv(dev); 48796d81f451SRussell King u32 lpi_ctl0; 48806d81f451SRussell King 48816d81f451SRussell King /* The Armada 37x documents do not give limits for this other than 48826d81f451SRussell King * it being an 8-bit register. */ 4883e4a3e9ffSYueHaibing if (eee->tx_lpi_enabled && eee->tx_lpi_timer > 255) 48846d81f451SRussell King return -EINVAL; 48856d81f451SRussell King 48866d81f451SRussell King lpi_ctl0 = mvreg_read(pp, MVNETA_LPI_CTRL_0); 48876d81f451SRussell King lpi_ctl0 &= ~(0xff << 8); 48886d81f451SRussell King lpi_ctl0 |= eee->tx_lpi_timer << 8; 48896d81f451SRussell King mvreg_write(pp, MVNETA_LPI_CTRL_0, lpi_ctl0); 48906d81f451SRussell King 48916d81f451SRussell King pp->eee_enabled = eee->eee_enabled; 48926d81f451SRussell King pp->tx_lpi_enabled = eee->tx_lpi_enabled; 48936d81f451SRussell King 48946d81f451SRussell King mvneta_set_eee(pp, eee->tx_lpi_enabled && eee->eee_enabled); 48956d81f451SRussell King 48966d81f451SRussell King return phylink_ethtool_set_eee(pp->phylink, eee); 48976d81f451SRussell King } 48986d81f451SRussell King 4899c5aff182SThomas Petazzoni static const struct net_device_ops mvneta_netdev_ops = { 4900c5aff182SThomas Petazzoni .ndo_open = mvneta_open, 4901c5aff182SThomas Petazzoni .ndo_stop = mvneta_stop, 4902c5aff182SThomas Petazzoni .ndo_start_xmit = mvneta_tx, 4903c5aff182SThomas Petazzoni .ndo_set_rx_mode = mvneta_set_rx_mode, 4904c5aff182SThomas Petazzoni .ndo_set_mac_address = mvneta_set_mac_addr, 4905c5aff182SThomas Petazzoni .ndo_change_mtu = mvneta_change_mtu, 4906b65657fcSSimon Guinot .ndo_fix_features = mvneta_fix_features, 4907c5aff182SThomas Petazzoni .ndo_get_stats64 = mvneta_get_stats64, 490815f59456SThomas Petazzoni .ndo_do_ioctl = mvneta_ioctl, 49090db51da7SLorenzo Bianconi .ndo_bpf = mvneta_xdp, 4910b0a43db9SLorenzo Bianconi .ndo_xdp_xmit = mvneta_xdp_xmit, 4911c5aff182SThomas Petazzoni }; 4912c5aff182SThomas Petazzoni 49134581be42SJisheng Zhang static const struct ethtool_ops mvneta_eth_tool_ops = { 491416e8d8b3SJakub Kicinski .supported_coalesce_params = ETHTOOL_COALESCE_RX_USECS | 491516e8d8b3SJakub Kicinski ETHTOOL_COALESCE_MAX_FRAMES, 4916503f9aa9SRussell King .nway_reset = mvneta_ethtool_nway_reset, 4917c5aff182SThomas Petazzoni .get_link = ethtool_op_get_link, 4918c5aff182SThomas Petazzoni .set_coalesce = mvneta_ethtool_set_coalesce, 4919c5aff182SThomas Petazzoni .get_coalesce = mvneta_ethtool_get_coalesce, 4920c5aff182SThomas Petazzoni .get_drvinfo = mvneta_ethtool_get_drvinfo, 4921c5aff182SThomas Petazzoni .get_ringparam = mvneta_ethtool_get_ringparam, 4922c5aff182SThomas Petazzoni .set_ringparam = mvneta_ethtool_set_ringparam, 49234932a918SRussell King .get_pauseparam = mvneta_ethtool_get_pauseparam, 49244932a918SRussell King .set_pauseparam = mvneta_ethtool_set_pauseparam, 49259b0cdefaSRussell King .get_strings = mvneta_ethtool_get_strings, 49269b0cdefaSRussell King .get_ethtool_stats = mvneta_ethtool_get_stats, 49279b0cdefaSRussell King .get_sset_count = mvneta_ethtool_get_sset_count, 49289a401deaSGregory CLEMENT .get_rxfh_indir_size = mvneta_ethtool_get_rxfh_indir_size, 49299a401deaSGregory CLEMENT .get_rxnfc = mvneta_ethtool_get_rxnfc, 49309a401deaSGregory CLEMENT .get_rxfh = mvneta_ethtool_get_rxfh, 49319a401deaSGregory CLEMENT .set_rxfh = mvneta_ethtool_set_rxfh, 4932503f9aa9SRussell King .get_link_ksettings = mvneta_ethtool_get_link_ksettings, 4933013ad40dSPhilippe Reynes .set_link_ksettings = mvneta_ethtool_set_link_ksettings, 4934b60a00f9SJingju Hou .get_wol = mvneta_ethtool_get_wol, 4935b60a00f9SJingju Hou .set_wol = mvneta_ethtool_set_wol, 49366d81f451SRussell King .get_eee = mvneta_ethtool_get_eee, 49376d81f451SRussell King .set_eee = mvneta_ethtool_set_eee, 4938c5aff182SThomas Petazzoni }; 4939c5aff182SThomas Petazzoni 4940c5aff182SThomas Petazzoni /* Initialize hw */ 49419672850bSEzequiel Garcia static int mvneta_init(struct device *dev, struct mvneta_port *pp) 4942c5aff182SThomas Petazzoni { 4943c5aff182SThomas Petazzoni int queue; 4944c5aff182SThomas Petazzoni 4945c5aff182SThomas Petazzoni /* Disable port */ 4946c5aff182SThomas Petazzoni mvneta_port_disable(pp); 4947c5aff182SThomas Petazzoni 4948c5aff182SThomas Petazzoni /* Set port default values */ 4949c5aff182SThomas Petazzoni mvneta_defaults_set(pp); 4950c5aff182SThomas Petazzoni 49515d6312edSMarkus Elfring pp->txqs = devm_kcalloc(dev, txq_number, sizeof(*pp->txqs), GFP_KERNEL); 4952c5aff182SThomas Petazzoni if (!pp->txqs) 4953c5aff182SThomas Petazzoni return -ENOMEM; 4954c5aff182SThomas Petazzoni 4955c5aff182SThomas Petazzoni /* Initialize TX descriptor rings */ 4956c5aff182SThomas Petazzoni for (queue = 0; queue < txq_number; queue++) { 4957c5aff182SThomas Petazzoni struct mvneta_tx_queue *txq = &pp->txqs[queue]; 4958c5aff182SThomas Petazzoni txq->id = queue; 4959c5aff182SThomas Petazzoni txq->size = pp->tx_ring_size; 4960c5aff182SThomas Petazzoni txq->done_pkts_coal = MVNETA_TXDONE_COAL_PKTS; 4961c5aff182SThomas Petazzoni } 4962c5aff182SThomas Petazzoni 49635d6312edSMarkus Elfring pp->rxqs = devm_kcalloc(dev, rxq_number, sizeof(*pp->rxqs), GFP_KERNEL); 49649672850bSEzequiel Garcia if (!pp->rxqs) 4965c5aff182SThomas Petazzoni return -ENOMEM; 4966c5aff182SThomas Petazzoni 4967c5aff182SThomas Petazzoni /* Create Rx descriptor rings */ 4968c5aff182SThomas Petazzoni for (queue = 0; queue < rxq_number; queue++) { 4969c5aff182SThomas Petazzoni struct mvneta_rx_queue *rxq = &pp->rxqs[queue]; 4970c5aff182SThomas Petazzoni rxq->id = queue; 4971c5aff182SThomas Petazzoni rxq->size = pp->rx_ring_size; 4972c5aff182SThomas Petazzoni rxq->pkts_coal = MVNETA_RX_COAL_PKTS; 4973c5aff182SThomas Petazzoni rxq->time_coal = MVNETA_RX_COAL_USEC; 497429110630SMarkus Elfring rxq->buf_virt_addr 497529110630SMarkus Elfring = devm_kmalloc_array(pp->dev->dev.parent, 497629110630SMarkus Elfring rxq->size, 497729110630SMarkus Elfring sizeof(*rxq->buf_virt_addr), 4978f88bee1cSGregory CLEMENT GFP_KERNEL); 4979f88bee1cSGregory CLEMENT if (!rxq->buf_virt_addr) 4980f88bee1cSGregory CLEMENT return -ENOMEM; 4981c5aff182SThomas Petazzoni } 4982c5aff182SThomas Petazzoni 4983c5aff182SThomas Petazzoni return 0; 4984c5aff182SThomas Petazzoni } 4985c5aff182SThomas Petazzoni 4986c5aff182SThomas Petazzoni /* platform glue : initialize decoding windows */ 498703ce758eSGreg KH static void mvneta_conf_mbus_windows(struct mvneta_port *pp, 4988c5aff182SThomas Petazzoni const struct mbus_dram_target_info *dram) 4989c5aff182SThomas Petazzoni { 4990c5aff182SThomas Petazzoni u32 win_enable; 4991c5aff182SThomas Petazzoni u32 win_protect; 4992c5aff182SThomas Petazzoni int i; 4993c5aff182SThomas Petazzoni 4994c5aff182SThomas Petazzoni for (i = 0; i < 6; i++) { 4995c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_WIN_BASE(i), 0); 4996c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_WIN_SIZE(i), 0); 4997c5aff182SThomas Petazzoni 4998c5aff182SThomas Petazzoni if (i < 4) 4999c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_WIN_REMAP(i), 0); 5000c5aff182SThomas Petazzoni } 5001c5aff182SThomas Petazzoni 5002c5aff182SThomas Petazzoni win_enable = 0x3f; 5003c5aff182SThomas Petazzoni win_protect = 0; 5004c5aff182SThomas Petazzoni 50052636ac3cSMarcin Wojtas if (dram) { 5006c5aff182SThomas Petazzoni for (i = 0; i < dram->num_cs; i++) { 5007c5aff182SThomas Petazzoni const struct mbus_dram_window *cs = dram->cs + i; 50082636ac3cSMarcin Wojtas 50092636ac3cSMarcin Wojtas mvreg_write(pp, MVNETA_WIN_BASE(i), 50102636ac3cSMarcin Wojtas (cs->base & 0xffff0000) | 50112636ac3cSMarcin Wojtas (cs->mbus_attr << 8) | 50122636ac3cSMarcin Wojtas dram->mbus_dram_target_id); 5013c5aff182SThomas Petazzoni 5014c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_WIN_SIZE(i), 5015c5aff182SThomas Petazzoni (cs->size - 1) & 0xffff0000); 5016c5aff182SThomas Petazzoni 5017c5aff182SThomas Petazzoni win_enable &= ~(1 << i); 5018c5aff182SThomas Petazzoni win_protect |= 3 << (2 * i); 5019c5aff182SThomas Petazzoni } 50202636ac3cSMarcin Wojtas } else { 50212636ac3cSMarcin Wojtas /* For Armada3700 open default 4GB Mbus window, leaving 50222636ac3cSMarcin Wojtas * arbitration of target/attribute to a different layer 50232636ac3cSMarcin Wojtas * of configuration. 50242636ac3cSMarcin Wojtas */ 50252636ac3cSMarcin Wojtas mvreg_write(pp, MVNETA_WIN_SIZE(0), 0xffff0000); 50262636ac3cSMarcin Wojtas win_enable &= ~BIT(0); 50272636ac3cSMarcin Wojtas win_protect = 3; 50282636ac3cSMarcin Wojtas } 5029c5aff182SThomas Petazzoni 5030c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_BASE_ADDR_ENABLE, win_enable); 5031db6ba9a5SMarcin Wojtas mvreg_write(pp, MVNETA_ACCESS_PROTECT_ENABLE, win_protect); 5032c5aff182SThomas Petazzoni } 5033c5aff182SThomas Petazzoni 5034c5aff182SThomas Petazzoni /* Power up the port */ 50353f1dd4bcSThomas Petazzoni static int mvneta_port_power_up(struct mvneta_port *pp, int phy_mode) 5036c5aff182SThomas Petazzoni { 5037c5aff182SThomas Petazzoni /* MAC Cause register should be cleared */ 5038c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_UNIT_INTR_CAUSE, 0); 5039c5aff182SThomas Petazzoni 504041c2b6b4SSascha Hauer if (phy_mode != PHY_INTERFACE_MODE_QSGMII && 504141c2b6b4SSascha Hauer phy_mode != PHY_INTERFACE_MODE_SGMII && 504241c2b6b4SSascha Hauer !phy_interface_mode_is_8023z(phy_mode) && 504341c2b6b4SSascha Hauer !phy_interface_mode_is_rgmii(phy_mode)) 50443f1dd4bcSThomas Petazzoni return -EINVAL; 50453f1dd4bcSThomas Petazzoni 50463f1dd4bcSThomas Petazzoni return 0; 5047c5aff182SThomas Petazzoni } 5048c5aff182SThomas Petazzoni 5049c5aff182SThomas Petazzoni /* Device initialization routine */ 505003ce758eSGreg KH static int mvneta_probe(struct platform_device *pdev) 5051c5aff182SThomas Petazzoni { 5052c5aff182SThomas Petazzoni struct device_node *dn = pdev->dev.of_node; 5053dc35a10fSMarcin Wojtas struct device_node *bm_node; 5054c5aff182SThomas Petazzoni struct mvneta_port *pp; 5055c5aff182SThomas Petazzoni struct net_device *dev; 5056503f9aa9SRussell King struct phylink *phylink; 5057a10c1c81SRussell King struct phy *comphy; 50588cc3e439SThomas Petazzoni const char *dt_mac_addr; 50598cc3e439SThomas Petazzoni char hw_mac_addr[ETH_ALEN]; 50600c65b2b9SAndrew Lunn phy_interface_t phy_mode; 50618cc3e439SThomas Petazzoni const char *mac_from; 50629110ee07SMarcin Wojtas int tx_csum_limit; 5063c5aff182SThomas Petazzoni int err; 506412bb03b4SMaxime Ripard int cpu; 5065c5aff182SThomas Petazzoni 5066a3ddd94fSRosen Penev dev = devm_alloc_etherdev_mqs(&pdev->dev, sizeof(struct mvneta_port), 5067a3ddd94fSRosen Penev txq_number, rxq_number); 5068c5aff182SThomas Petazzoni if (!dev) 5069c5aff182SThomas Petazzoni return -ENOMEM; 5070c5aff182SThomas Petazzoni 5071c5aff182SThomas Petazzoni dev->irq = irq_of_parse_and_map(dn, 0); 5072a3ddd94fSRosen Penev if (dev->irq == 0) 5073a3ddd94fSRosen Penev return -EINVAL; 5074c5aff182SThomas Petazzoni 50750c65b2b9SAndrew Lunn err = of_get_phy_mode(dn, &phy_mode); 50760c65b2b9SAndrew Lunn if (err) { 5077c5aff182SThomas Petazzoni dev_err(&pdev->dev, "incorrect phy-mode\n"); 5078503f9aa9SRussell King goto err_free_irq; 5079503f9aa9SRussell King } 5080503f9aa9SRussell King 5081a10c1c81SRussell King comphy = devm_of_phy_get(&pdev->dev, dn, NULL); 5082a10c1c81SRussell King if (comphy == ERR_PTR(-EPROBE_DEFER)) { 5083a10c1c81SRussell King err = -EPROBE_DEFER; 5084a10c1c81SRussell King goto err_free_irq; 5085a10c1c81SRussell King } else if (IS_ERR(comphy)) { 5086a10c1c81SRussell King comphy = NULL; 5087a10c1c81SRussell King } 5088a10c1c81SRussell King 508944cc27e4SIoana Ciornei pp = netdev_priv(dev); 509044cc27e4SIoana Ciornei spin_lock_init(&pp->lock); 509144cc27e4SIoana Ciornei 509244cc27e4SIoana Ciornei pp->phylink_config.dev = &dev->dev; 509344cc27e4SIoana Ciornei pp->phylink_config.type = PHYLINK_NETDEV; 509444cc27e4SIoana Ciornei 509544cc27e4SIoana Ciornei phylink = phylink_create(&pp->phylink_config, pdev->dev.fwnode, 509644cc27e4SIoana Ciornei phy_mode, &mvneta_phylink_ops); 5097503f9aa9SRussell King if (IS_ERR(phylink)) { 5098503f9aa9SRussell King err = PTR_ERR(phylink); 5099503f9aa9SRussell King goto err_free_irq; 5100c5aff182SThomas Petazzoni } 5101c5aff182SThomas Petazzoni 5102c5aff182SThomas Petazzoni dev->tx_queue_len = MVNETA_MAX_TXD; 5103c5aff182SThomas Petazzoni dev->watchdog_timeo = 5 * HZ; 5104c5aff182SThomas Petazzoni dev->netdev_ops = &mvneta_netdev_ops; 5105c5aff182SThomas Petazzoni 51067ad24ea4SWilfried Klaebe dev->ethtool_ops = &mvneta_eth_tool_ops; 5107c5aff182SThomas Petazzoni 5108503f9aa9SRussell King pp->phylink = phylink; 5109a10c1c81SRussell King pp->comphy = comphy; 5110c5aff182SThomas Petazzoni pp->phy_interface = phy_mode; 5111503f9aa9SRussell King pp->dn = dn; 5112c5aff182SThomas Petazzoni 511390b74c01SGregory CLEMENT pp->rxq_def = rxq_def; 51149a401deaSGregory CLEMENT pp->indir[0] = rxq_def; 51159a401deaSGregory CLEMENT 51162636ac3cSMarcin Wojtas /* Get special SoC configurations */ 51172636ac3cSMarcin Wojtas if (of_device_is_compatible(dn, "marvell,armada-3700-neta")) 51182636ac3cSMarcin Wojtas pp->neta_armada3700 = true; 51192636ac3cSMarcin Wojtas 51202804ba4eSJisheng Zhang pp->clk = devm_clk_get(&pdev->dev, "core"); 51212804ba4eSJisheng Zhang if (IS_ERR(pp->clk)) 5122189dd626SThomas Petazzoni pp->clk = devm_clk_get(&pdev->dev, NULL); 5123189dd626SThomas Petazzoni if (IS_ERR(pp->clk)) { 5124189dd626SThomas Petazzoni err = PTR_ERR(pp->clk); 5125503f9aa9SRussell King goto err_free_phylink; 5126189dd626SThomas Petazzoni } 5127189dd626SThomas Petazzoni 5128189dd626SThomas Petazzoni clk_prepare_enable(pp->clk); 5129189dd626SThomas Petazzoni 513015cc4a4aSJisheng Zhang pp->clk_bus = devm_clk_get(&pdev->dev, "bus"); 513115cc4a4aSJisheng Zhang if (!IS_ERR(pp->clk_bus)) 513215cc4a4aSJisheng Zhang clk_prepare_enable(pp->clk_bus); 513315cc4a4aSJisheng Zhang 513400c33afbSJisheng Zhang pp->base = devm_platform_ioremap_resource(pdev, 0); 5135c3f0dd38SThomas Petazzoni if (IS_ERR(pp->base)) { 5136c3f0dd38SThomas Petazzoni err = PTR_ERR(pp->base); 51375445eaf3SArnaud Patard \(Rtp\) goto err_clk; 51385445eaf3SArnaud Patard \(Rtp\) } 51395445eaf3SArnaud Patard \(Rtp\) 514012bb03b4SMaxime Ripard /* Alloc per-cpu port structure */ 514112bb03b4SMaxime Ripard pp->ports = alloc_percpu(struct mvneta_pcpu_port); 514212bb03b4SMaxime Ripard if (!pp->ports) { 514312bb03b4SMaxime Ripard err = -ENOMEM; 514412bb03b4SMaxime Ripard goto err_clk; 514512bb03b4SMaxime Ripard } 514612bb03b4SMaxime Ripard 514774c41b04Swilly tarreau /* Alloc per-cpu stats */ 51481c213bd2SWANG Cong pp->stats = netdev_alloc_pcpu_stats(struct mvneta_pcpu_stats); 514974c41b04Swilly tarreau if (!pp->stats) { 515074c41b04Swilly tarreau err = -ENOMEM; 515112bb03b4SMaxime Ripard goto err_free_ports; 515274c41b04Swilly tarreau } 515374c41b04Swilly tarreau 51548cc3e439SThomas Petazzoni dt_mac_addr = of_get_mac_address(dn); 5155a51645f7SPetr Štetiar if (!IS_ERR(dt_mac_addr)) { 51568cc3e439SThomas Petazzoni mac_from = "device tree"; 51572d2924afSPetr Štetiar ether_addr_copy(dev->dev_addr, dt_mac_addr); 51588cc3e439SThomas Petazzoni } else { 51598cc3e439SThomas Petazzoni mvneta_get_mac_addr(pp, hw_mac_addr); 51608cc3e439SThomas Petazzoni if (is_valid_ether_addr(hw_mac_addr)) { 51618cc3e439SThomas Petazzoni mac_from = "hardware"; 51628cc3e439SThomas Petazzoni memcpy(dev->dev_addr, hw_mac_addr, ETH_ALEN); 51638cc3e439SThomas Petazzoni } else { 51648cc3e439SThomas Petazzoni mac_from = "random"; 51658cc3e439SThomas Petazzoni eth_hw_addr_random(dev); 51668cc3e439SThomas Petazzoni } 51678cc3e439SThomas Petazzoni } 51688cc3e439SThomas Petazzoni 51699110ee07SMarcin Wojtas if (!of_property_read_u32(dn, "tx-csum-limit", &tx_csum_limit)) { 51709110ee07SMarcin Wojtas if (tx_csum_limit < 0 || 51719110ee07SMarcin Wojtas tx_csum_limit > MVNETA_TX_CSUM_MAX_SIZE) { 51729110ee07SMarcin Wojtas tx_csum_limit = MVNETA_TX_CSUM_DEF_SIZE; 51739110ee07SMarcin Wojtas dev_info(&pdev->dev, 51749110ee07SMarcin Wojtas "Wrong TX csum limit in DT, set to %dB\n", 51759110ee07SMarcin Wojtas MVNETA_TX_CSUM_DEF_SIZE); 51769110ee07SMarcin Wojtas } 51779110ee07SMarcin Wojtas } else if (of_device_is_compatible(dn, "marvell,armada-370-neta")) { 51789110ee07SMarcin Wojtas tx_csum_limit = MVNETA_TX_CSUM_DEF_SIZE; 51799110ee07SMarcin Wojtas } else { 51809110ee07SMarcin Wojtas tx_csum_limit = MVNETA_TX_CSUM_MAX_SIZE; 51819110ee07SMarcin Wojtas } 51829110ee07SMarcin Wojtas 51839110ee07SMarcin Wojtas pp->tx_csum_limit = tx_csum_limit; 5184b65657fcSSimon Guinot 51859768b45cSJane Li pp->dram_target_info = mv_mbus_dram_info(); 51862636ac3cSMarcin Wojtas /* Armada3700 requires setting default configuration of Mbus 51872636ac3cSMarcin Wojtas * windows, however without using filled mbus_dram_target_info 51882636ac3cSMarcin Wojtas * structure. 51892636ac3cSMarcin Wojtas */ 51909768b45cSJane Li if (pp->dram_target_info || pp->neta_armada3700) 51919768b45cSJane Li mvneta_conf_mbus_windows(pp, pp->dram_target_info); 5192dc35a10fSMarcin Wojtas 5193c5aff182SThomas Petazzoni pp->tx_ring_size = MVNETA_MAX_TXD; 5194c5aff182SThomas Petazzoni pp->rx_ring_size = MVNETA_MAX_RXD; 5195c5aff182SThomas Petazzoni 5196c5aff182SThomas Petazzoni pp->dev = dev; 5197c5aff182SThomas Petazzoni SET_NETDEV_DEV(dev, &pdev->dev); 5198c5aff182SThomas Petazzoni 5199dc35a10fSMarcin Wojtas pp->id = global_port_id++; 5200dc35a10fSMarcin Wojtas 5201dc35a10fSMarcin Wojtas /* Obtain access to BM resources if enabled and already initialized */ 5202dc35a10fSMarcin Wojtas bm_node = of_parse_phandle(dn, "buffer-manager", 0); 5203965cbbecSGregory CLEMENT if (bm_node) { 5204965cbbecSGregory CLEMENT pp->bm_priv = mvneta_bm_get(bm_node); 5205965cbbecSGregory CLEMENT if (pp->bm_priv) { 5206dc35a10fSMarcin Wojtas err = mvneta_bm_port_init(pdev, pp); 5207dc35a10fSMarcin Wojtas if (err < 0) { 5208965cbbecSGregory CLEMENT dev_info(&pdev->dev, 5209965cbbecSGregory CLEMENT "use SW buffer management\n"); 5210965cbbecSGregory CLEMENT mvneta_bm_put(pp->bm_priv); 5211dc35a10fSMarcin Wojtas pp->bm_priv = NULL; 5212dc35a10fSMarcin Wojtas } 5213dc35a10fSMarcin Wojtas } 5214562e2f46SYelena Krivosheev /* Set RX packet offset correction for platforms, whose 5215562e2f46SYelena Krivosheev * NET_SKB_PAD, exceeds 64B. It should be 64B for 64-bit 5216562e2f46SYelena Krivosheev * platforms and 0B for 32-bit ones. 5217562e2f46SYelena Krivosheev */ 5218562e2f46SYelena Krivosheev pp->rx_offset_correction = max(0, 5219562e2f46SYelena Krivosheev NET_SKB_PAD - 5220562e2f46SYelena Krivosheev MVNETA_RX_PKT_OFFSET_CORRECTION); 5221965cbbecSGregory CLEMENT } 5222d4e4da00SPeter Chen of_node_put(bm_node); 5223dc35a10fSMarcin Wojtas 522444efc78dSLorenzo Bianconi /* sw buffer management */ 522544efc78dSLorenzo Bianconi if (!pp->bm_priv) 522644efc78dSLorenzo Bianconi pp->rx_offset_correction = MVNETA_SKB_HEADROOM; 522744efc78dSLorenzo Bianconi 52289672850bSEzequiel Garcia err = mvneta_init(&pdev->dev, pp); 52299672850bSEzequiel Garcia if (err < 0) 5230dc35a10fSMarcin Wojtas goto err_netdev; 52313f1dd4bcSThomas Petazzoni 523241c2b6b4SSascha Hauer err = mvneta_port_power_up(pp, pp->phy_interface); 52333f1dd4bcSThomas Petazzoni if (err < 0) { 52343f1dd4bcSThomas Petazzoni dev_err(&pdev->dev, "can't power up port\n"); 523541c2b6b4SSascha Hauer return err; 52363f1dd4bcSThomas Petazzoni } 5237c5aff182SThomas Petazzoni 52382636ac3cSMarcin Wojtas /* Armada3700 network controller does not support per-cpu 52392636ac3cSMarcin Wojtas * operation, so only single NAPI should be initialized. 52402636ac3cSMarcin Wojtas */ 52412636ac3cSMarcin Wojtas if (pp->neta_armada3700) { 52422636ac3cSMarcin Wojtas netif_napi_add(dev, &pp->napi, mvneta_poll, NAPI_POLL_WEIGHT); 52432636ac3cSMarcin Wojtas } else { 524412bb03b4SMaxime Ripard for_each_present_cpu(cpu) { 52452636ac3cSMarcin Wojtas struct mvneta_pcpu_port *port = 52462636ac3cSMarcin Wojtas per_cpu_ptr(pp->ports, cpu); 524712bb03b4SMaxime Ripard 52482636ac3cSMarcin Wojtas netif_napi_add(dev, &port->napi, mvneta_poll, 52492636ac3cSMarcin Wojtas NAPI_POLL_WEIGHT); 525012bb03b4SMaxime Ripard port->pp = pp; 525112bb03b4SMaxime Ripard } 52522636ac3cSMarcin Wojtas } 5253c5aff182SThomas Petazzoni 52547772988aSJisheng Zhang dev->features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | 52557772988aSJisheng Zhang NETIF_F_TSO | NETIF_F_RXCSUM; 525601ef26caSEzequiel Garcia dev->hw_features |= dev->features; 525701ef26caSEzequiel Garcia dev->vlan_features |= dev->features; 525897db8afaSAndrew Lunn dev->priv_flags |= IFF_LIVE_ADDR_CHANGE; 52598eef5f97SEzequiel Garcia dev->gso_max_segs = MVNETA_MAX_TSO_SEGS; 5260b50b72deSwilly tarreau 52615777987eSJarod Wilson /* MTU range: 68 - 9676 */ 52625777987eSJarod Wilson dev->min_mtu = ETH_MIN_MTU; 52635777987eSJarod Wilson /* 9676 == 9700 - 20 and rounding to 8 */ 52645777987eSJarod Wilson dev->max_mtu = 9676; 52655777987eSJarod Wilson 5266c5aff182SThomas Petazzoni err = register_netdev(dev); 5267c5aff182SThomas Petazzoni if (err < 0) { 5268c5aff182SThomas Petazzoni dev_err(&pdev->dev, "failed to register\n"); 5269d484e06eSJisheng Zhang goto err_netdev; 5270c5aff182SThomas Petazzoni } 5271c5aff182SThomas Petazzoni 52728cc3e439SThomas Petazzoni netdev_info(dev, "Using %s mac address %pM\n", mac_from, 52738cc3e439SThomas Petazzoni dev->dev_addr); 5274c5aff182SThomas Petazzoni 5275c5aff182SThomas Petazzoni platform_set_drvdata(pdev, pp->dev); 5276c5aff182SThomas Petazzoni 5277c5aff182SThomas Petazzoni return 0; 5278c5aff182SThomas Petazzoni 5279dc35a10fSMarcin Wojtas err_netdev: 5280dc35a10fSMarcin Wojtas if (pp->bm_priv) { 5281dc35a10fSMarcin Wojtas mvneta_bm_pool_destroy(pp->bm_priv, pp->pool_long, 1 << pp->id); 5282dc35a10fSMarcin Wojtas mvneta_bm_pool_destroy(pp->bm_priv, pp->pool_short, 5283dc35a10fSMarcin Wojtas 1 << pp->id); 5284965cbbecSGregory CLEMENT mvneta_bm_put(pp->bm_priv); 5285dc35a10fSMarcin Wojtas } 528674c41b04Swilly tarreau free_percpu(pp->stats); 528712bb03b4SMaxime Ripard err_free_ports: 528812bb03b4SMaxime Ripard free_percpu(pp->ports); 52895445eaf3SArnaud Patard \(Rtp\) err_clk: 529015cc4a4aSJisheng Zhang clk_disable_unprepare(pp->clk_bus); 52915445eaf3SArnaud Patard \(Rtp\) clk_disable_unprepare(pp->clk); 5292503f9aa9SRussell King err_free_phylink: 5293503f9aa9SRussell King if (pp->phylink) 5294503f9aa9SRussell King phylink_destroy(pp->phylink); 5295c5aff182SThomas Petazzoni err_free_irq: 5296c5aff182SThomas Petazzoni irq_dispose_mapping(dev->irq); 5297c5aff182SThomas Petazzoni return err; 5298c5aff182SThomas Petazzoni } 5299c5aff182SThomas Petazzoni 5300c5aff182SThomas Petazzoni /* Device removal routine */ 530103ce758eSGreg KH static int mvneta_remove(struct platform_device *pdev) 5302c5aff182SThomas Petazzoni { 5303c5aff182SThomas Petazzoni struct net_device *dev = platform_get_drvdata(pdev); 5304c5aff182SThomas Petazzoni struct mvneta_port *pp = netdev_priv(dev); 5305c5aff182SThomas Petazzoni 5306c5aff182SThomas Petazzoni unregister_netdev(dev); 530715cc4a4aSJisheng Zhang clk_disable_unprepare(pp->clk_bus); 5308189dd626SThomas Petazzoni clk_disable_unprepare(pp->clk); 530912bb03b4SMaxime Ripard free_percpu(pp->ports); 531074c41b04Swilly tarreau free_percpu(pp->stats); 5311c5aff182SThomas Petazzoni irq_dispose_mapping(dev->irq); 5312503f9aa9SRussell King phylink_destroy(pp->phylink); 5313c5aff182SThomas Petazzoni 5314dc35a10fSMarcin Wojtas if (pp->bm_priv) { 5315dc35a10fSMarcin Wojtas mvneta_bm_pool_destroy(pp->bm_priv, pp->pool_long, 1 << pp->id); 5316dc35a10fSMarcin Wojtas mvneta_bm_pool_destroy(pp->bm_priv, pp->pool_short, 5317dc35a10fSMarcin Wojtas 1 << pp->id); 5318965cbbecSGregory CLEMENT mvneta_bm_put(pp->bm_priv); 5319dc35a10fSMarcin Wojtas } 5320dc35a10fSMarcin Wojtas 5321c5aff182SThomas Petazzoni return 0; 5322c5aff182SThomas Petazzoni } 5323c5aff182SThomas Petazzoni 53249768b45cSJane Li #ifdef CONFIG_PM_SLEEP 53259768b45cSJane Li static int mvneta_suspend(struct device *device) 53269768b45cSJane Li { 53271799cdd2SJisheng Zhang int queue; 53289768b45cSJane Li struct net_device *dev = dev_get_drvdata(device); 53299768b45cSJane Li struct mvneta_port *pp = netdev_priv(dev); 53309768b45cSJane Li 53311799cdd2SJisheng Zhang if (!netif_running(dev)) 53321799cdd2SJisheng Zhang goto clean_exit; 53331799cdd2SJisheng Zhang 53341799cdd2SJisheng Zhang if (!pp->neta_armada3700) { 53351799cdd2SJisheng Zhang spin_lock(&pp->lock); 53361799cdd2SJisheng Zhang pp->is_stopped = true; 53371799cdd2SJisheng Zhang spin_unlock(&pp->lock); 53381799cdd2SJisheng Zhang 53391799cdd2SJisheng Zhang cpuhp_state_remove_instance_nocalls(online_hpstate, 53401799cdd2SJisheng Zhang &pp->node_online); 53411799cdd2SJisheng Zhang cpuhp_state_remove_instance_nocalls(CPUHP_NET_MVNETA_DEAD, 53421799cdd2SJisheng Zhang &pp->node_dead); 53431799cdd2SJisheng Zhang } 53441799cdd2SJisheng Zhang 53453b8bc674SRussell King rtnl_lock(); 53461799cdd2SJisheng Zhang mvneta_stop_dev(pp); 53473b8bc674SRussell King rtnl_unlock(); 53481799cdd2SJisheng Zhang 53491799cdd2SJisheng Zhang for (queue = 0; queue < rxq_number; queue++) { 53501799cdd2SJisheng Zhang struct mvneta_rx_queue *rxq = &pp->rxqs[queue]; 53511799cdd2SJisheng Zhang 53521799cdd2SJisheng Zhang mvneta_rxq_drop_pkts(pp, rxq); 53531799cdd2SJisheng Zhang } 53541799cdd2SJisheng Zhang 53551799cdd2SJisheng Zhang for (queue = 0; queue < txq_number; queue++) { 53561799cdd2SJisheng Zhang struct mvneta_tx_queue *txq = &pp->txqs[queue]; 53571799cdd2SJisheng Zhang 53581799cdd2SJisheng Zhang mvneta_txq_hw_deinit(pp, txq); 53591799cdd2SJisheng Zhang } 53601799cdd2SJisheng Zhang 53611799cdd2SJisheng Zhang clean_exit: 53629768b45cSJane Li netif_device_detach(dev); 53639768b45cSJane Li clk_disable_unprepare(pp->clk_bus); 53649768b45cSJane Li clk_disable_unprepare(pp->clk); 53651799cdd2SJisheng Zhang 53669768b45cSJane Li return 0; 53679768b45cSJane Li } 53689768b45cSJane Li 53699768b45cSJane Li static int mvneta_resume(struct device *device) 53709768b45cSJane Li { 53719768b45cSJane Li struct platform_device *pdev = to_platform_device(device); 53729768b45cSJane Li struct net_device *dev = dev_get_drvdata(device); 53739768b45cSJane Li struct mvneta_port *pp = netdev_priv(dev); 53741799cdd2SJisheng Zhang int err, queue; 53759768b45cSJane Li 53769768b45cSJane Li clk_prepare_enable(pp->clk); 53779768b45cSJane Li if (!IS_ERR(pp->clk_bus)) 53789768b45cSJane Li clk_prepare_enable(pp->clk_bus); 53799768b45cSJane Li if (pp->dram_target_info || pp->neta_armada3700) 53809768b45cSJane Li mvneta_conf_mbus_windows(pp, pp->dram_target_info); 53819768b45cSJane Li if (pp->bm_priv) { 53829768b45cSJane Li err = mvneta_bm_port_init(pdev, pp); 53839768b45cSJane Li if (err < 0) { 53849768b45cSJane Li dev_info(&pdev->dev, "use SW buffer management\n"); 538544efc78dSLorenzo Bianconi pp->rx_offset_correction = MVNETA_SKB_HEADROOM; 53869768b45cSJane Li pp->bm_priv = NULL; 53879768b45cSJane Li } 53889768b45cSJane Li } 53899768b45cSJane Li mvneta_defaults_set(pp); 53909768b45cSJane Li err = mvneta_port_power_up(pp, pp->phy_interface); 53919768b45cSJane Li if (err < 0) { 53929768b45cSJane Li dev_err(device, "can't power up port\n"); 53939768b45cSJane Li return err; 53949768b45cSJane Li } 53959768b45cSJane Li 53969768b45cSJane Li netif_device_attach(dev); 53971799cdd2SJisheng Zhang 53981799cdd2SJisheng Zhang if (!netif_running(dev)) 53991799cdd2SJisheng Zhang return 0; 54001799cdd2SJisheng Zhang 54011799cdd2SJisheng Zhang for (queue = 0; queue < rxq_number; queue++) { 54021799cdd2SJisheng Zhang struct mvneta_rx_queue *rxq = &pp->rxqs[queue]; 54031799cdd2SJisheng Zhang 54041799cdd2SJisheng Zhang rxq->next_desc_to_proc = 0; 54051799cdd2SJisheng Zhang mvneta_rxq_hw_init(pp, rxq); 5406d6956ac8SJisheng Zhang } 54071799cdd2SJisheng Zhang 54081799cdd2SJisheng Zhang for (queue = 0; queue < txq_number; queue++) { 54091799cdd2SJisheng Zhang struct mvneta_tx_queue *txq = &pp->txqs[queue]; 54101799cdd2SJisheng Zhang 54111799cdd2SJisheng Zhang txq->next_desc_to_proc = 0; 54121799cdd2SJisheng Zhang mvneta_txq_hw_init(pp, txq); 54131799cdd2SJisheng Zhang } 54141799cdd2SJisheng Zhang 54151799cdd2SJisheng Zhang if (!pp->neta_armada3700) { 54161799cdd2SJisheng Zhang spin_lock(&pp->lock); 54171799cdd2SJisheng Zhang pp->is_stopped = false; 54181799cdd2SJisheng Zhang spin_unlock(&pp->lock); 54191799cdd2SJisheng Zhang cpuhp_state_add_instance_nocalls(online_hpstate, 54201799cdd2SJisheng Zhang &pp->node_online); 54211799cdd2SJisheng Zhang cpuhp_state_add_instance_nocalls(CPUHP_NET_MVNETA_DEAD, 54221799cdd2SJisheng Zhang &pp->node_dead); 54231799cdd2SJisheng Zhang } 54241799cdd2SJisheng Zhang 54251799cdd2SJisheng Zhang rtnl_lock(); 54261799cdd2SJisheng Zhang mvneta_start_dev(pp); 54273b8bc674SRussell King rtnl_unlock(); 54281799cdd2SJisheng Zhang mvneta_set_rx_mode(dev); 5429d6956ac8SJisheng Zhang 54309768b45cSJane Li return 0; 54319768b45cSJane Li } 54329768b45cSJane Li #endif 54339768b45cSJane Li 54349768b45cSJane Li static SIMPLE_DEV_PM_OPS(mvneta_pm_ops, mvneta_suspend, mvneta_resume); 54359768b45cSJane Li 5436c5aff182SThomas Petazzoni static const struct of_device_id mvneta_match[] = { 5437c5aff182SThomas Petazzoni { .compatible = "marvell,armada-370-neta" }, 5438f522a975SSimon Guinot { .compatible = "marvell,armada-xp-neta" }, 54392636ac3cSMarcin Wojtas { .compatible = "marvell,armada-3700-neta" }, 5440c5aff182SThomas Petazzoni { } 5441c5aff182SThomas Petazzoni }; 5442c5aff182SThomas Petazzoni MODULE_DEVICE_TABLE(of, mvneta_match); 5443c5aff182SThomas Petazzoni 5444c5aff182SThomas Petazzoni static struct platform_driver mvneta_driver = { 5445c5aff182SThomas Petazzoni .probe = mvneta_probe, 544603ce758eSGreg KH .remove = mvneta_remove, 5447c5aff182SThomas Petazzoni .driver = { 5448c5aff182SThomas Petazzoni .name = MVNETA_DRIVER_NAME, 5449c5aff182SThomas Petazzoni .of_match_table = mvneta_match, 54509768b45cSJane Li .pm = &mvneta_pm_ops, 5451c5aff182SThomas Petazzoni }, 5452c5aff182SThomas Petazzoni }; 5453c5aff182SThomas Petazzoni 545484a3f4dbSSebastian Andrzej Siewior static int __init mvneta_driver_init(void) 545584a3f4dbSSebastian Andrzej Siewior { 545684a3f4dbSSebastian Andrzej Siewior int ret; 545784a3f4dbSSebastian Andrzej Siewior 5458664d035cSChristophe JAILLET ret = cpuhp_setup_state_multi(CPUHP_AP_ONLINE_DYN, "net/mvneta:online", 545984a3f4dbSSebastian Andrzej Siewior mvneta_cpu_online, 546084a3f4dbSSebastian Andrzej Siewior mvneta_cpu_down_prepare); 546184a3f4dbSSebastian Andrzej Siewior if (ret < 0) 546284a3f4dbSSebastian Andrzej Siewior goto out; 546384a3f4dbSSebastian Andrzej Siewior online_hpstate = ret; 546484a3f4dbSSebastian Andrzej Siewior ret = cpuhp_setup_state_multi(CPUHP_NET_MVNETA_DEAD, "net/mvneta:dead", 546584a3f4dbSSebastian Andrzej Siewior NULL, mvneta_cpu_dead); 546684a3f4dbSSebastian Andrzej Siewior if (ret) 546784a3f4dbSSebastian Andrzej Siewior goto err_dead; 546884a3f4dbSSebastian Andrzej Siewior 546984a3f4dbSSebastian Andrzej Siewior ret = platform_driver_register(&mvneta_driver); 547084a3f4dbSSebastian Andrzej Siewior if (ret) 547184a3f4dbSSebastian Andrzej Siewior goto err; 547284a3f4dbSSebastian Andrzej Siewior return 0; 547384a3f4dbSSebastian Andrzej Siewior 547484a3f4dbSSebastian Andrzej Siewior err: 547584a3f4dbSSebastian Andrzej Siewior cpuhp_remove_multi_state(CPUHP_NET_MVNETA_DEAD); 547684a3f4dbSSebastian Andrzej Siewior err_dead: 547784a3f4dbSSebastian Andrzej Siewior cpuhp_remove_multi_state(online_hpstate); 547884a3f4dbSSebastian Andrzej Siewior out: 547984a3f4dbSSebastian Andrzej Siewior return ret; 548084a3f4dbSSebastian Andrzej Siewior } 548184a3f4dbSSebastian Andrzej Siewior module_init(mvneta_driver_init); 548284a3f4dbSSebastian Andrzej Siewior 548384a3f4dbSSebastian Andrzej Siewior static void __exit mvneta_driver_exit(void) 548484a3f4dbSSebastian Andrzej Siewior { 548584a3f4dbSSebastian Andrzej Siewior platform_driver_unregister(&mvneta_driver); 548684a3f4dbSSebastian Andrzej Siewior cpuhp_remove_multi_state(CPUHP_NET_MVNETA_DEAD); 548784a3f4dbSSebastian Andrzej Siewior cpuhp_remove_multi_state(online_hpstate); 548884a3f4dbSSebastian Andrzej Siewior } 548984a3f4dbSSebastian Andrzej Siewior module_exit(mvneta_driver_exit); 5490c5aff182SThomas Petazzoni 5491c5aff182SThomas Petazzoni MODULE_DESCRIPTION("Marvell NETA Ethernet Driver - www.marvell.com"); 5492c5aff182SThomas Petazzoni MODULE_AUTHOR("Rami Rosen <rosenr@marvell.com>, Thomas Petazzoni <thomas.petazzoni@free-electrons.com>"); 5493c5aff182SThomas Petazzoni MODULE_LICENSE("GPL"); 5494c5aff182SThomas Petazzoni 5495d3757ba4SJoe Perches module_param(rxq_number, int, 0444); 5496d3757ba4SJoe Perches module_param(txq_number, int, 0444); 5497c5aff182SThomas Petazzoni 5498d3757ba4SJoe Perches module_param(rxq_def, int, 0444); 5499d3757ba4SJoe Perches module_param(rx_copybreak, int, 0644); 5500