1c5aff182SThomas Petazzoni /* 2c5aff182SThomas Petazzoni * Driver for Marvell NETA network card for Armada XP and Armada 370 SoCs. 3c5aff182SThomas Petazzoni * 4c5aff182SThomas Petazzoni * Copyright (C) 2012 Marvell 5c5aff182SThomas Petazzoni * 6c5aff182SThomas Petazzoni * Rami Rosen <rosenr@marvell.com> 7c5aff182SThomas Petazzoni * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> 8c5aff182SThomas Petazzoni * 9c5aff182SThomas Petazzoni * This file is licensed under the terms of the GNU General Public 10c5aff182SThomas Petazzoni * License version 2. This program is licensed "as is" without any 11c5aff182SThomas Petazzoni * warranty of any kind, whether express or implied. 12c5aff182SThomas Petazzoni */ 13c5aff182SThomas Petazzoni 140e03f563SJisheng Zhang #include <linux/clk.h> 150e03f563SJisheng Zhang #include <linux/cpu.h> 16c5aff182SThomas Petazzoni #include <linux/etherdevice.h> 170e03f563SJisheng Zhang #include <linux/if_vlan.h> 18c5aff182SThomas Petazzoni #include <linux/inetdevice.h> 190e03f563SJisheng Zhang #include <linux/interrupt.h> 200e03f563SJisheng Zhang #include <linux/io.h> 210e03f563SJisheng Zhang #include <linux/kernel.h> 22c5aff182SThomas Petazzoni #include <linux/mbus.h> 23c5aff182SThomas Petazzoni #include <linux/module.h> 240e03f563SJisheng Zhang #include <linux/netdevice.h> 25c5aff182SThomas Petazzoni #include <linux/of.h> 260e03f563SJisheng Zhang #include <linux/of_address.h> 27c5aff182SThomas Petazzoni #include <linux/of_irq.h> 28c5aff182SThomas Petazzoni #include <linux/of_mdio.h> 29c5aff182SThomas Petazzoni #include <linux/of_net.h> 30c5aff182SThomas Petazzoni #include <linux/phy.h> 31503f9aa9SRussell King #include <linux/phylink.h> 320e03f563SJisheng Zhang #include <linux/platform_device.h> 330e03f563SJisheng Zhang #include <linux/skbuff.h> 34baa11ebcSGregory CLEMENT #include <net/hwbm.h> 35dc35a10fSMarcin Wojtas #include "mvneta_bm.h" 360e03f563SJisheng Zhang #include <net/ip.h> 370e03f563SJisheng Zhang #include <net/ipv6.h> 380e03f563SJisheng Zhang #include <net/tso.h> 39c5aff182SThomas Petazzoni 40c5aff182SThomas Petazzoni /* Registers */ 41c5aff182SThomas Petazzoni #define MVNETA_RXQ_CONFIG_REG(q) (0x1400 + ((q) << 2)) 42e5bdf689SMarcin Wojtas #define MVNETA_RXQ_HW_BUF_ALLOC BIT(0) 43dc35a10fSMarcin Wojtas #define MVNETA_RXQ_SHORT_POOL_ID_SHIFT 4 44dc35a10fSMarcin Wojtas #define MVNETA_RXQ_SHORT_POOL_ID_MASK 0x30 45dc35a10fSMarcin Wojtas #define MVNETA_RXQ_LONG_POOL_ID_SHIFT 6 46dc35a10fSMarcin Wojtas #define MVNETA_RXQ_LONG_POOL_ID_MASK 0xc0 47c5aff182SThomas Petazzoni #define MVNETA_RXQ_PKT_OFFSET_ALL_MASK (0xf << 8) 48c5aff182SThomas Petazzoni #define MVNETA_RXQ_PKT_OFFSET_MASK(offs) ((offs) << 8) 49c5aff182SThomas Petazzoni #define MVNETA_RXQ_THRESHOLD_REG(q) (0x14c0 + ((q) << 2)) 50c5aff182SThomas Petazzoni #define MVNETA_RXQ_NON_OCCUPIED(v) ((v) << 16) 51c5aff182SThomas Petazzoni #define MVNETA_RXQ_BASE_ADDR_REG(q) (0x1480 + ((q) << 2)) 52c5aff182SThomas Petazzoni #define MVNETA_RXQ_SIZE_REG(q) (0x14a0 + ((q) << 2)) 53c5aff182SThomas Petazzoni #define MVNETA_RXQ_BUF_SIZE_SHIFT 19 54c5aff182SThomas Petazzoni #define MVNETA_RXQ_BUF_SIZE_MASK (0x1fff << 19) 55c5aff182SThomas Petazzoni #define MVNETA_RXQ_STATUS_REG(q) (0x14e0 + ((q) << 2)) 56c5aff182SThomas Petazzoni #define MVNETA_RXQ_OCCUPIED_ALL_MASK 0x3fff 57c5aff182SThomas Petazzoni #define MVNETA_RXQ_STATUS_UPDATE_REG(q) (0x1500 + ((q) << 2)) 58c5aff182SThomas Petazzoni #define MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT 16 59c5aff182SThomas Petazzoni #define MVNETA_RXQ_ADD_NON_OCCUPIED_MAX 255 60dc35a10fSMarcin Wojtas #define MVNETA_PORT_POOL_BUFFER_SZ_REG(pool) (0x1700 + ((pool) << 2)) 61dc35a10fSMarcin Wojtas #define MVNETA_PORT_POOL_BUFFER_SZ_SHIFT 3 62dc35a10fSMarcin Wojtas #define MVNETA_PORT_POOL_BUFFER_SZ_MASK 0xfff8 63c5aff182SThomas Petazzoni #define MVNETA_PORT_RX_RESET 0x1cc0 64c5aff182SThomas Petazzoni #define MVNETA_PORT_RX_DMA_RESET BIT(0) 65c5aff182SThomas Petazzoni #define MVNETA_PHY_ADDR 0x2000 66c5aff182SThomas Petazzoni #define MVNETA_PHY_ADDR_MASK 0x1f 67c5aff182SThomas Petazzoni #define MVNETA_MBUS_RETRY 0x2010 68c5aff182SThomas Petazzoni #define MVNETA_UNIT_INTR_CAUSE 0x2080 69c5aff182SThomas Petazzoni #define MVNETA_UNIT_CONTROL 0x20B0 70c5aff182SThomas Petazzoni #define MVNETA_PHY_POLLING_ENABLE BIT(1) 71c5aff182SThomas Petazzoni #define MVNETA_WIN_BASE(w) (0x2200 + ((w) << 3)) 72c5aff182SThomas Petazzoni #define MVNETA_WIN_SIZE(w) (0x2204 + ((w) << 3)) 73c5aff182SThomas Petazzoni #define MVNETA_WIN_REMAP(w) (0x2280 + ((w) << 2)) 74c5aff182SThomas Petazzoni #define MVNETA_BASE_ADDR_ENABLE 0x2290 75db6ba9a5SMarcin Wojtas #define MVNETA_ACCESS_PROTECT_ENABLE 0x2294 76c5aff182SThomas Petazzoni #define MVNETA_PORT_CONFIG 0x2400 77c5aff182SThomas Petazzoni #define MVNETA_UNI_PROMISC_MODE BIT(0) 78c5aff182SThomas Petazzoni #define MVNETA_DEF_RXQ(q) ((q) << 1) 79c5aff182SThomas Petazzoni #define MVNETA_DEF_RXQ_ARP(q) ((q) << 4) 80c5aff182SThomas Petazzoni #define MVNETA_TX_UNSET_ERR_SUM BIT(12) 81c5aff182SThomas Petazzoni #define MVNETA_DEF_RXQ_TCP(q) ((q) << 16) 82c5aff182SThomas Petazzoni #define MVNETA_DEF_RXQ_UDP(q) ((q) << 19) 83c5aff182SThomas Petazzoni #define MVNETA_DEF_RXQ_BPDU(q) ((q) << 22) 84c5aff182SThomas Petazzoni #define MVNETA_RX_CSUM_WITH_PSEUDO_HDR BIT(25) 85c5aff182SThomas Petazzoni #define MVNETA_PORT_CONFIG_DEFL_VALUE(q) (MVNETA_DEF_RXQ(q) | \ 86c5aff182SThomas Petazzoni MVNETA_DEF_RXQ_ARP(q) | \ 87c5aff182SThomas Petazzoni MVNETA_DEF_RXQ_TCP(q) | \ 88c5aff182SThomas Petazzoni MVNETA_DEF_RXQ_UDP(q) | \ 89c5aff182SThomas Petazzoni MVNETA_DEF_RXQ_BPDU(q) | \ 90c5aff182SThomas Petazzoni MVNETA_TX_UNSET_ERR_SUM | \ 91c5aff182SThomas Petazzoni MVNETA_RX_CSUM_WITH_PSEUDO_HDR) 92c5aff182SThomas Petazzoni #define MVNETA_PORT_CONFIG_EXTEND 0x2404 93c5aff182SThomas Petazzoni #define MVNETA_MAC_ADDR_LOW 0x2414 94c5aff182SThomas Petazzoni #define MVNETA_MAC_ADDR_HIGH 0x2418 95c5aff182SThomas Petazzoni #define MVNETA_SDMA_CONFIG 0x241c 96c5aff182SThomas Petazzoni #define MVNETA_SDMA_BRST_SIZE_16 4 97c5aff182SThomas Petazzoni #define MVNETA_RX_BRST_SZ_MASK(burst) ((burst) << 1) 98c5aff182SThomas Petazzoni #define MVNETA_RX_NO_DATA_SWAP BIT(4) 99c5aff182SThomas Petazzoni #define MVNETA_TX_NO_DATA_SWAP BIT(5) 1009ad8fef6SThomas Petazzoni #define MVNETA_DESC_SWAP BIT(6) 101c5aff182SThomas Petazzoni #define MVNETA_TX_BRST_SZ_MASK(burst) ((burst) << 22) 102c5aff182SThomas Petazzoni #define MVNETA_PORT_STATUS 0x2444 103c5aff182SThomas Petazzoni #define MVNETA_TX_IN_PRGRS BIT(1) 104c5aff182SThomas Petazzoni #define MVNETA_TX_FIFO_EMPTY BIT(8) 105c5aff182SThomas Petazzoni #define MVNETA_RX_MIN_FRAME_SIZE 0x247c 1063f1dd4bcSThomas Petazzoni #define MVNETA_SERDES_CFG 0x24A0 1075445eaf3SArnaud Patard \(Rtp\) #define MVNETA_SGMII_SERDES_PROTO 0x0cc7 1083f1dd4bcSThomas Petazzoni #define MVNETA_QSGMII_SERDES_PROTO 0x0667 109c5aff182SThomas Petazzoni #define MVNETA_TYPE_PRIO 0x24bc 110c5aff182SThomas Petazzoni #define MVNETA_FORCE_UNI BIT(21) 111c5aff182SThomas Petazzoni #define MVNETA_TXQ_CMD_1 0x24e4 112c5aff182SThomas Petazzoni #define MVNETA_TXQ_CMD 0x2448 113c5aff182SThomas Petazzoni #define MVNETA_TXQ_DISABLE_SHIFT 8 114c5aff182SThomas Petazzoni #define MVNETA_TXQ_ENABLE_MASK 0x000000ff 115e483911fSAndrew Lunn #define MVNETA_RX_DISCARD_FRAME_COUNT 0x2484 116e483911fSAndrew Lunn #define MVNETA_OVERRUN_FRAME_COUNT 0x2488 117898b2970SStas Sergeev #define MVNETA_GMAC_CLOCK_DIVIDER 0x24f4 118898b2970SStas Sergeev #define MVNETA_GMAC_1MS_CLOCK_ENABLE BIT(31) 119c5aff182SThomas Petazzoni #define MVNETA_ACC_MODE 0x2500 120dc35a10fSMarcin Wojtas #define MVNETA_BM_ADDRESS 0x2504 121c5aff182SThomas Petazzoni #define MVNETA_CPU_MAP(cpu) (0x2540 + ((cpu) << 2)) 122c5aff182SThomas Petazzoni #define MVNETA_CPU_RXQ_ACCESS_ALL_MASK 0x000000ff 123c5aff182SThomas Petazzoni #define MVNETA_CPU_TXQ_ACCESS_ALL_MASK 0x0000ff00 1242dcf75e2SGregory CLEMENT #define MVNETA_CPU_RXQ_ACCESS(rxq) BIT(rxq) 12550bf8cb6SGregory CLEMENT #define MVNETA_CPU_TXQ_ACCESS(txq) BIT(txq + 8) 126c5aff182SThomas Petazzoni #define MVNETA_RXQ_TIME_COAL_REG(q) (0x2580 + ((q) << 2)) 12740ba35e7Swilly tarreau 1282dcf75e2SGregory CLEMENT /* Exception Interrupt Port/Queue Cause register 1292dcf75e2SGregory CLEMENT * 1302dcf75e2SGregory CLEMENT * Their behavior depend of the mapping done using the PCPX2Q 1312dcf75e2SGregory CLEMENT * registers. For a given CPU if the bit associated to a queue is not 1322dcf75e2SGregory CLEMENT * set, then for the register a read from this CPU will always return 1332dcf75e2SGregory CLEMENT * 0 and a write won't do anything 1342dcf75e2SGregory CLEMENT */ 13540ba35e7Swilly tarreau 136c5aff182SThomas Petazzoni #define MVNETA_INTR_NEW_CAUSE 0x25a0 137c5aff182SThomas Petazzoni #define MVNETA_INTR_NEW_MASK 0x25a4 13840ba35e7Swilly tarreau 13940ba35e7Swilly tarreau /* bits 0..7 = TXQ SENT, one bit per queue. 14040ba35e7Swilly tarreau * bits 8..15 = RXQ OCCUP, one bit per queue. 14140ba35e7Swilly tarreau * bits 16..23 = RXQ FREE, one bit per queue. 14240ba35e7Swilly tarreau * bit 29 = OLD_REG_SUM, see old reg ? 14340ba35e7Swilly tarreau * bit 30 = TX_ERR_SUM, one bit for 4 ports 14440ba35e7Swilly tarreau * bit 31 = MISC_SUM, one bit for 4 ports 14540ba35e7Swilly tarreau */ 14640ba35e7Swilly tarreau #define MVNETA_TX_INTR_MASK(nr_txqs) (((1 << nr_txqs) - 1) << 0) 14740ba35e7Swilly tarreau #define MVNETA_TX_INTR_MASK_ALL (0xff << 0) 14840ba35e7Swilly tarreau #define MVNETA_RX_INTR_MASK(nr_rxqs) (((1 << nr_rxqs) - 1) << 8) 14940ba35e7Swilly tarreau #define MVNETA_RX_INTR_MASK_ALL (0xff << 8) 150898b2970SStas Sergeev #define MVNETA_MISCINTR_INTR_MASK BIT(31) 15140ba35e7Swilly tarreau 152c5aff182SThomas Petazzoni #define MVNETA_INTR_OLD_CAUSE 0x25a8 153c5aff182SThomas Petazzoni #define MVNETA_INTR_OLD_MASK 0x25ac 15440ba35e7Swilly tarreau 15540ba35e7Swilly tarreau /* Data Path Port/Queue Cause Register */ 156c5aff182SThomas Petazzoni #define MVNETA_INTR_MISC_CAUSE 0x25b0 157c5aff182SThomas Petazzoni #define MVNETA_INTR_MISC_MASK 0x25b4 15840ba35e7Swilly tarreau 15940ba35e7Swilly tarreau #define MVNETA_CAUSE_PHY_STATUS_CHANGE BIT(0) 16040ba35e7Swilly tarreau #define MVNETA_CAUSE_LINK_CHANGE BIT(1) 16140ba35e7Swilly tarreau #define MVNETA_CAUSE_PTP BIT(4) 16240ba35e7Swilly tarreau 16340ba35e7Swilly tarreau #define MVNETA_CAUSE_INTERNAL_ADDR_ERR BIT(7) 16440ba35e7Swilly tarreau #define MVNETA_CAUSE_RX_OVERRUN BIT(8) 16540ba35e7Swilly tarreau #define MVNETA_CAUSE_RX_CRC_ERROR BIT(9) 16640ba35e7Swilly tarreau #define MVNETA_CAUSE_RX_LARGE_PKT BIT(10) 16740ba35e7Swilly tarreau #define MVNETA_CAUSE_TX_UNDERUN BIT(11) 16840ba35e7Swilly tarreau #define MVNETA_CAUSE_PRBS_ERR BIT(12) 16940ba35e7Swilly tarreau #define MVNETA_CAUSE_PSC_SYNC_CHANGE BIT(13) 17040ba35e7Swilly tarreau #define MVNETA_CAUSE_SERDES_SYNC_ERR BIT(14) 17140ba35e7Swilly tarreau 17240ba35e7Swilly tarreau #define MVNETA_CAUSE_BMU_ALLOC_ERR_SHIFT 16 17340ba35e7Swilly tarreau #define MVNETA_CAUSE_BMU_ALLOC_ERR_ALL_MASK (0xF << MVNETA_CAUSE_BMU_ALLOC_ERR_SHIFT) 17440ba35e7Swilly tarreau #define MVNETA_CAUSE_BMU_ALLOC_ERR_MASK(pool) (1 << (MVNETA_CAUSE_BMU_ALLOC_ERR_SHIFT + (pool))) 17540ba35e7Swilly tarreau 17640ba35e7Swilly tarreau #define MVNETA_CAUSE_TXQ_ERROR_SHIFT 24 17740ba35e7Swilly tarreau #define MVNETA_CAUSE_TXQ_ERROR_ALL_MASK (0xFF << MVNETA_CAUSE_TXQ_ERROR_SHIFT) 17840ba35e7Swilly tarreau #define MVNETA_CAUSE_TXQ_ERROR_MASK(q) (1 << (MVNETA_CAUSE_TXQ_ERROR_SHIFT + (q))) 17940ba35e7Swilly tarreau 180c5aff182SThomas Petazzoni #define MVNETA_INTR_ENABLE 0x25b8 181c5aff182SThomas Petazzoni #define MVNETA_TXQ_INTR_ENABLE_ALL_MASK 0x0000ff00 182dc1aadf6SMarcin Wojtas #define MVNETA_RXQ_INTR_ENABLE_ALL_MASK 0x000000ff 18340ba35e7Swilly tarreau 184c5aff182SThomas Petazzoni #define MVNETA_RXQ_CMD 0x2680 185c5aff182SThomas Petazzoni #define MVNETA_RXQ_DISABLE_SHIFT 8 186c5aff182SThomas Petazzoni #define MVNETA_RXQ_ENABLE_MASK 0x000000ff 187c5aff182SThomas Petazzoni #define MVETH_TXQ_TOKEN_COUNT_REG(q) (0x2700 + ((q) << 4)) 188c5aff182SThomas Petazzoni #define MVETH_TXQ_TOKEN_CFG_REG(q) (0x2704 + ((q) << 4)) 189c5aff182SThomas Petazzoni #define MVNETA_GMAC_CTRL_0 0x2c00 190c5aff182SThomas Petazzoni #define MVNETA_GMAC_MAX_RX_SIZE_SHIFT 2 191c5aff182SThomas Petazzoni #define MVNETA_GMAC_MAX_RX_SIZE_MASK 0x7ffc 19222f4bf8aSRussell King #define MVNETA_GMAC0_PORT_1000BASE_X BIT(1) 193c5aff182SThomas Petazzoni #define MVNETA_GMAC0_PORT_ENABLE BIT(0) 194c5aff182SThomas Petazzoni #define MVNETA_GMAC_CTRL_2 0x2c08 195898b2970SStas Sergeev #define MVNETA_GMAC2_INBAND_AN_ENABLE BIT(0) 196a79121d3SThomas Petazzoni #define MVNETA_GMAC2_PCS_ENABLE BIT(3) 197c5aff182SThomas Petazzoni #define MVNETA_GMAC2_PORT_RGMII BIT(4) 198c5aff182SThomas Petazzoni #define MVNETA_GMAC2_PORT_RESET BIT(6) 199c5aff182SThomas Petazzoni #define MVNETA_GMAC_STATUS 0x2c10 200c5aff182SThomas Petazzoni #define MVNETA_GMAC_LINK_UP BIT(0) 201c5aff182SThomas Petazzoni #define MVNETA_GMAC_SPEED_1000 BIT(1) 202c5aff182SThomas Petazzoni #define MVNETA_GMAC_SPEED_100 BIT(2) 203c5aff182SThomas Petazzoni #define MVNETA_GMAC_FULL_DUPLEX BIT(3) 204c5aff182SThomas Petazzoni #define MVNETA_GMAC_RX_FLOW_CTRL_ENABLE BIT(4) 205c5aff182SThomas Petazzoni #define MVNETA_GMAC_TX_FLOW_CTRL_ENABLE BIT(5) 206c5aff182SThomas Petazzoni #define MVNETA_GMAC_RX_FLOW_CTRL_ACTIVE BIT(6) 207c5aff182SThomas Petazzoni #define MVNETA_GMAC_TX_FLOW_CTRL_ACTIVE BIT(7) 208503f9aa9SRussell King #define MVNETA_GMAC_AN_COMPLETE BIT(11) 209503f9aa9SRussell King #define MVNETA_GMAC_SYNC_OK BIT(14) 210c5aff182SThomas Petazzoni #define MVNETA_GMAC_AUTONEG_CONFIG 0x2c0c 211c5aff182SThomas Petazzoni #define MVNETA_GMAC_FORCE_LINK_DOWN BIT(0) 212c5aff182SThomas Petazzoni #define MVNETA_GMAC_FORCE_LINK_PASS BIT(1) 213898b2970SStas Sergeev #define MVNETA_GMAC_INBAND_AN_ENABLE BIT(2) 21422f4bf8aSRussell King #define MVNETA_GMAC_AN_BYPASS_ENABLE BIT(3) 21522f4bf8aSRussell King #define MVNETA_GMAC_INBAND_RESTART_AN BIT(4) 216c5aff182SThomas Petazzoni #define MVNETA_GMAC_CONFIG_MII_SPEED BIT(5) 217c5aff182SThomas Petazzoni #define MVNETA_GMAC_CONFIG_GMII_SPEED BIT(6) 21871408602SThomas Petazzoni #define MVNETA_GMAC_AN_SPEED_EN BIT(7) 21922f4bf8aSRussell King #define MVNETA_GMAC_CONFIG_FLOW_CTRL BIT(8) 22022f4bf8aSRussell King #define MVNETA_GMAC_ADVERT_SYM_FLOW_CTRL BIT(9) 221898b2970SStas Sergeev #define MVNETA_GMAC_AN_FLOW_CTRL_EN BIT(11) 222c5aff182SThomas Petazzoni #define MVNETA_GMAC_CONFIG_FULL_DUPLEX BIT(12) 22371408602SThomas Petazzoni #define MVNETA_GMAC_AN_DUPLEX_EN BIT(13) 224da58a931SMaxime Chevallier #define MVNETA_GMAC_CTRL_4 0x2c90 225da58a931SMaxime Chevallier #define MVNETA_GMAC4_SHORT_PREAMBLE_ENABLE BIT(1) 226e483911fSAndrew Lunn #define MVNETA_MIB_COUNTERS_BASE 0x3000 227c5aff182SThomas Petazzoni #define MVNETA_MIB_LATE_COLLISION 0x7c 228c5aff182SThomas Petazzoni #define MVNETA_DA_FILT_SPEC_MCAST 0x3400 229c5aff182SThomas Petazzoni #define MVNETA_DA_FILT_OTH_MCAST 0x3500 230c5aff182SThomas Petazzoni #define MVNETA_DA_FILT_UCAST_BASE 0x3600 231c5aff182SThomas Petazzoni #define MVNETA_TXQ_BASE_ADDR_REG(q) (0x3c00 + ((q) << 2)) 232c5aff182SThomas Petazzoni #define MVNETA_TXQ_SIZE_REG(q) (0x3c20 + ((q) << 2)) 233c5aff182SThomas Petazzoni #define MVNETA_TXQ_SENT_THRESH_ALL_MASK 0x3fff0000 234c5aff182SThomas Petazzoni #define MVNETA_TXQ_SENT_THRESH_MASK(coal) ((coal) << 16) 235c5aff182SThomas Petazzoni #define MVNETA_TXQ_UPDATE_REG(q) (0x3c60 + ((q) << 2)) 236c5aff182SThomas Petazzoni #define MVNETA_TXQ_DEC_SENT_SHIFT 16 2372a90f7e1SSimon Guinot #define MVNETA_TXQ_DEC_SENT_MASK 0xff 238c5aff182SThomas Petazzoni #define MVNETA_TXQ_STATUS_REG(q) (0x3c40 + ((q) << 2)) 239c5aff182SThomas Petazzoni #define MVNETA_TXQ_SENT_DESC_SHIFT 16 240c5aff182SThomas Petazzoni #define MVNETA_TXQ_SENT_DESC_MASK 0x3fff0000 241c5aff182SThomas Petazzoni #define MVNETA_PORT_TX_RESET 0x3cf0 242c5aff182SThomas Petazzoni #define MVNETA_PORT_TX_DMA_RESET BIT(0) 243c5aff182SThomas Petazzoni #define MVNETA_TX_MTU 0x3e0c 244c5aff182SThomas Petazzoni #define MVNETA_TX_TOKEN_SIZE 0x3e14 245c5aff182SThomas Petazzoni #define MVNETA_TX_TOKEN_SIZE_MAX 0xffffffff 246c5aff182SThomas Petazzoni #define MVNETA_TXQ_TOKEN_SIZE_REG(q) (0x3e40 + ((q) << 2)) 247c5aff182SThomas Petazzoni #define MVNETA_TXQ_TOKEN_SIZE_MAX 0x7fffffff 248c5aff182SThomas Petazzoni 2496d81f451SRussell King #define MVNETA_LPI_CTRL_0 0x2cc0 2506d81f451SRussell King #define MVNETA_LPI_CTRL_1 0x2cc4 2516d81f451SRussell King #define MVNETA_LPI_REQUEST_ENABLE BIT(0) 2526d81f451SRussell King #define MVNETA_LPI_CTRL_2 0x2cc8 2536d81f451SRussell King #define MVNETA_LPI_STATUS 0x2ccc 2546d81f451SRussell King 255c5aff182SThomas Petazzoni #define MVNETA_CAUSE_TXQ_SENT_DESC_ALL_MASK 0xff 256c5aff182SThomas Petazzoni 257c5aff182SThomas Petazzoni /* Descriptor ring Macros */ 258c5aff182SThomas Petazzoni #define MVNETA_QUEUE_NEXT_DESC(q, index) \ 259c5aff182SThomas Petazzoni (((index) < (q)->last_desc) ? ((index) + 1) : 0) 260c5aff182SThomas Petazzoni 261c5aff182SThomas Petazzoni /* Various constants */ 262c5aff182SThomas Petazzoni 263c5aff182SThomas Petazzoni /* Coalescing */ 26406708f81SDmitri Epshtein #define MVNETA_TXDONE_COAL_PKTS 0 /* interrupt per packet */ 265c5aff182SThomas Petazzoni #define MVNETA_RX_COAL_PKTS 32 266c5aff182SThomas Petazzoni #define MVNETA_RX_COAL_USEC 100 267c5aff182SThomas Petazzoni 2686a20c175SThomas Petazzoni /* The two bytes Marvell header. Either contains a special value used 269c5aff182SThomas Petazzoni * by Marvell switches when a specific hardware mode is enabled (not 270c5aff182SThomas Petazzoni * supported by this driver) or is filled automatically by zeroes on 271c5aff182SThomas Petazzoni * the RX side. Those two bytes being at the front of the Ethernet 272c5aff182SThomas Petazzoni * header, they allow to have the IP header aligned on a 4 bytes 273c5aff182SThomas Petazzoni * boundary automatically: the hardware skips those two bytes on its 274c5aff182SThomas Petazzoni * own. 275c5aff182SThomas Petazzoni */ 276c5aff182SThomas Petazzoni #define MVNETA_MH_SIZE 2 277c5aff182SThomas Petazzoni 278c5aff182SThomas Petazzoni #define MVNETA_VLAN_TAG_LEN 4 279c5aff182SThomas Petazzoni 2809110ee07SMarcin Wojtas #define MVNETA_TX_CSUM_DEF_SIZE 1600 281c5aff182SThomas Petazzoni #define MVNETA_TX_CSUM_MAX_SIZE 9800 282dc35a10fSMarcin Wojtas #define MVNETA_ACC_MODE_EXT1 1 283dc35a10fSMarcin Wojtas #define MVNETA_ACC_MODE_EXT2 2 284dc35a10fSMarcin Wojtas 285dc35a10fSMarcin Wojtas #define MVNETA_MAX_DECODE_WIN 6 286c5aff182SThomas Petazzoni 287c5aff182SThomas Petazzoni /* Timeout constants */ 288c5aff182SThomas Petazzoni #define MVNETA_TX_DISABLE_TIMEOUT_MSEC 1000 289c5aff182SThomas Petazzoni #define MVNETA_RX_DISABLE_TIMEOUT_MSEC 1000 290c5aff182SThomas Petazzoni #define MVNETA_TX_FIFO_EMPTY_TIMEOUT 10000 291c5aff182SThomas Petazzoni 292c5aff182SThomas Petazzoni #define MVNETA_TX_MTU_MAX 0x3ffff 293c5aff182SThomas Petazzoni 2949a401deaSGregory CLEMENT /* The RSS lookup table actually has 256 entries but we do not use 2959a401deaSGregory CLEMENT * them yet 2969a401deaSGregory CLEMENT */ 2979a401deaSGregory CLEMENT #define MVNETA_RSS_LU_TABLE_SIZE 1 2989a401deaSGregory CLEMENT 299c5aff182SThomas Petazzoni /* Max number of Rx descriptors */ 300c307e2a8SYelena Krivosheev #define MVNETA_MAX_RXD 512 301c5aff182SThomas Petazzoni 302c5aff182SThomas Petazzoni /* Max number of Tx descriptors */ 303c307e2a8SYelena Krivosheev #define MVNETA_MAX_TXD 1024 304c5aff182SThomas Petazzoni 3058eef5f97SEzequiel Garcia /* Max number of allowed TCP segments for software TSO */ 3068eef5f97SEzequiel Garcia #define MVNETA_MAX_TSO_SEGS 100 3078eef5f97SEzequiel Garcia 3088eef5f97SEzequiel Garcia #define MVNETA_MAX_SKB_DESCS (MVNETA_MAX_TSO_SEGS * 2 + MAX_SKB_FRAGS) 3098eef5f97SEzequiel Garcia 310c5aff182SThomas Petazzoni /* descriptor aligned size */ 311c5aff182SThomas Petazzoni #define MVNETA_DESC_ALIGNED_SIZE 32 312c5aff182SThomas Petazzoni 3138d5047cfSMarcin Wojtas /* Number of bytes to be taken into account by HW when putting incoming data 3148d5047cfSMarcin Wojtas * to the buffers. It is needed in case NET_SKB_PAD exceeds maximum packet 3158d5047cfSMarcin Wojtas * offset supported in MVNETA_RXQ_CONFIG_REG(q) registers. 3168d5047cfSMarcin Wojtas */ 3178d5047cfSMarcin Wojtas #define MVNETA_RX_PKT_OFFSET_CORRECTION 64 3188d5047cfSMarcin Wojtas 319c5aff182SThomas Petazzoni #define MVNETA_RX_PKT_SIZE(mtu) \ 320c5aff182SThomas Petazzoni ALIGN((mtu) + MVNETA_MH_SIZE + MVNETA_VLAN_TAG_LEN + \ 321c5aff182SThomas Petazzoni ETH_HLEN + ETH_FCS_LEN, \ 322c66e98c9SJisheng Zhang cache_line_size()) 323c5aff182SThomas Petazzoni 3242e3173a3SEzequiel Garcia #define IS_TSO_HEADER(txq, addr) \ 3252e3173a3SEzequiel Garcia ((addr >= txq->tso_hdrs_phys) && \ 3262e3173a3SEzequiel Garcia (addr < txq->tso_hdrs_phys + txq->size * TSO_HEADER_SIZE)) 3272e3173a3SEzequiel Garcia 328dc35a10fSMarcin Wojtas #define MVNETA_RX_GET_BM_POOL_ID(rxd) \ 329dc35a10fSMarcin Wojtas (((rxd)->status & MVNETA_RXD_BM_POOL_MASK) >> MVNETA_RXD_BM_POOL_SHIFT) 330c5aff182SThomas Petazzoni 3316d81f451SRussell King enum { 3326d81f451SRussell King ETHTOOL_STAT_EEE_WAKEUP, 33317a96da6SGregory CLEMENT ETHTOOL_STAT_SKB_ALLOC_ERR, 33417a96da6SGregory CLEMENT ETHTOOL_STAT_REFILL_ERR, 3356d81f451SRussell King ETHTOOL_MAX_STATS, 3366d81f451SRussell King }; 3376d81f451SRussell King 3389b0cdefaSRussell King struct mvneta_statistic { 3399b0cdefaSRussell King unsigned short offset; 3409b0cdefaSRussell King unsigned short type; 3419b0cdefaSRussell King const char name[ETH_GSTRING_LEN]; 3429b0cdefaSRussell King }; 3439b0cdefaSRussell King 3449b0cdefaSRussell King #define T_REG_32 32 3459b0cdefaSRussell King #define T_REG_64 64 3466d81f451SRussell King #define T_SW 1 3479b0cdefaSRussell King 3489b0cdefaSRussell King static const struct mvneta_statistic mvneta_statistics[] = { 3499b0cdefaSRussell King { 0x3000, T_REG_64, "good_octets_received", }, 3509b0cdefaSRussell King { 0x3010, T_REG_32, "good_frames_received", }, 3519b0cdefaSRussell King { 0x3008, T_REG_32, "bad_octets_received", }, 3529b0cdefaSRussell King { 0x3014, T_REG_32, "bad_frames_received", }, 3539b0cdefaSRussell King { 0x3018, T_REG_32, "broadcast_frames_received", }, 3549b0cdefaSRussell King { 0x301c, T_REG_32, "multicast_frames_received", }, 3559b0cdefaSRussell King { 0x3050, T_REG_32, "unrec_mac_control_received", }, 3569b0cdefaSRussell King { 0x3058, T_REG_32, "good_fc_received", }, 3579b0cdefaSRussell King { 0x305c, T_REG_32, "bad_fc_received", }, 3589b0cdefaSRussell King { 0x3060, T_REG_32, "undersize_received", }, 3599b0cdefaSRussell King { 0x3064, T_REG_32, "fragments_received", }, 3609b0cdefaSRussell King { 0x3068, T_REG_32, "oversize_received", }, 3619b0cdefaSRussell King { 0x306c, T_REG_32, "jabber_received", }, 3629b0cdefaSRussell King { 0x3070, T_REG_32, "mac_receive_error", }, 3639b0cdefaSRussell King { 0x3074, T_REG_32, "bad_crc_event", }, 3649b0cdefaSRussell King { 0x3078, T_REG_32, "collision", }, 3659b0cdefaSRussell King { 0x307c, T_REG_32, "late_collision", }, 3669b0cdefaSRussell King { 0x2484, T_REG_32, "rx_discard", }, 3679b0cdefaSRussell King { 0x2488, T_REG_32, "rx_overrun", }, 3689b0cdefaSRussell King { 0x3020, T_REG_32, "frames_64_octets", }, 3699b0cdefaSRussell King { 0x3024, T_REG_32, "frames_65_to_127_octets", }, 3709b0cdefaSRussell King { 0x3028, T_REG_32, "frames_128_to_255_octets", }, 3719b0cdefaSRussell King { 0x302c, T_REG_32, "frames_256_to_511_octets", }, 3729b0cdefaSRussell King { 0x3030, T_REG_32, "frames_512_to_1023_octets", }, 3739b0cdefaSRussell King { 0x3034, T_REG_32, "frames_1024_to_max_octets", }, 3749b0cdefaSRussell King { 0x3038, T_REG_64, "good_octets_sent", }, 3759b0cdefaSRussell King { 0x3040, T_REG_32, "good_frames_sent", }, 3769b0cdefaSRussell King { 0x3044, T_REG_32, "excessive_collision", }, 3779b0cdefaSRussell King { 0x3048, T_REG_32, "multicast_frames_sent", }, 3789b0cdefaSRussell King { 0x304c, T_REG_32, "broadcast_frames_sent", }, 3799b0cdefaSRussell King { 0x3054, T_REG_32, "fc_sent", }, 3809b0cdefaSRussell King { 0x300c, T_REG_32, "internal_mac_transmit_err", }, 3816d81f451SRussell King { ETHTOOL_STAT_EEE_WAKEUP, T_SW, "eee_wakeup_errors", }, 38217a96da6SGregory CLEMENT { ETHTOOL_STAT_SKB_ALLOC_ERR, T_SW, "skb_alloc_errors", }, 38317a96da6SGregory CLEMENT { ETHTOOL_STAT_REFILL_ERR, T_SW, "refill_errors", }, 3849b0cdefaSRussell King }; 3859b0cdefaSRussell King 38674c41b04Swilly tarreau struct mvneta_pcpu_stats { 387c5aff182SThomas Petazzoni struct u64_stats_sync syncp; 38874c41b04Swilly tarreau u64 rx_packets; 38974c41b04Swilly tarreau u64 rx_bytes; 39074c41b04Swilly tarreau u64 tx_packets; 39174c41b04Swilly tarreau u64 tx_bytes; 392c5aff182SThomas Petazzoni }; 393c5aff182SThomas Petazzoni 39412bb03b4SMaxime Ripard struct mvneta_pcpu_port { 39512bb03b4SMaxime Ripard /* Pointer to the shared port */ 39612bb03b4SMaxime Ripard struct mvneta_port *pp; 39712bb03b4SMaxime Ripard 39812bb03b4SMaxime Ripard /* Pointer to the CPU-local NAPI struct */ 39912bb03b4SMaxime Ripard struct napi_struct napi; 40012bb03b4SMaxime Ripard 40112bb03b4SMaxime Ripard /* Cause of the previous interrupt */ 40212bb03b4SMaxime Ripard u32 cause_rx_tx; 40312bb03b4SMaxime Ripard }; 40412bb03b4SMaxime Ripard 405c5aff182SThomas Petazzoni struct mvneta_port { 406dc35a10fSMarcin Wojtas u8 id; 40712bb03b4SMaxime Ripard struct mvneta_pcpu_port __percpu *ports; 40812bb03b4SMaxime Ripard struct mvneta_pcpu_stats __percpu *stats; 40912bb03b4SMaxime Ripard 410c5aff182SThomas Petazzoni int pkt_size; 4118ec2cd48Swilly tarreau unsigned int frag_size; 412c5aff182SThomas Petazzoni void __iomem *base; 413c5aff182SThomas Petazzoni struct mvneta_rx_queue *rxqs; 414c5aff182SThomas Petazzoni struct mvneta_tx_queue *txqs; 415c5aff182SThomas Petazzoni struct net_device *dev; 41684a3f4dbSSebastian Andrzej Siewior struct hlist_node node_online; 41784a3f4dbSSebastian Andrzej Siewior struct hlist_node node_dead; 41890b74c01SGregory CLEMENT int rxq_def; 4195888511eSGregory CLEMENT /* Protect the access to the percpu interrupt registers, 4205888511eSGregory CLEMENT * ensuring that the configuration remains coherent. 4215888511eSGregory CLEMENT */ 4225888511eSGregory CLEMENT spinlock_t lock; 423120cfa50SGregory CLEMENT bool is_stopped; 424c5aff182SThomas Petazzoni 4252636ac3cSMarcin Wojtas u32 cause_rx_tx; 4262636ac3cSMarcin Wojtas struct napi_struct napi; 4272636ac3cSMarcin Wojtas 428c5aff182SThomas Petazzoni /* Core clock */ 429189dd626SThomas Petazzoni struct clk *clk; 43015cc4a4aSJisheng Zhang /* AXI clock */ 43115cc4a4aSJisheng Zhang struct clk *clk_bus; 432c5aff182SThomas Petazzoni u8 mcast_count[256]; 433c5aff182SThomas Petazzoni u16 tx_ring_size; 434c5aff182SThomas Petazzoni u16 rx_ring_size; 435c5aff182SThomas Petazzoni 436c5aff182SThomas Petazzoni phy_interface_t phy_interface; 437503f9aa9SRussell King struct device_node *dn; 438b65657fcSSimon Guinot unsigned int tx_csum_limit; 439503f9aa9SRussell King struct phylink *phylink; 4409b0cdefaSRussell King 441dc35a10fSMarcin Wojtas struct mvneta_bm *bm_priv; 442dc35a10fSMarcin Wojtas struct mvneta_bm_pool *pool_long; 443dc35a10fSMarcin Wojtas struct mvneta_bm_pool *pool_short; 444dc35a10fSMarcin Wojtas int bm_win_id; 445dc35a10fSMarcin Wojtas 4466d81f451SRussell King bool eee_enabled; 4476d81f451SRussell King bool eee_active; 4486d81f451SRussell King bool tx_lpi_enabled; 4496d81f451SRussell King 4509b0cdefaSRussell King u64 ethtool_stats[ARRAY_SIZE(mvneta_statistics)]; 4519a401deaSGregory CLEMENT 4529a401deaSGregory CLEMENT u32 indir[MVNETA_RSS_LU_TABLE_SIZE]; 4532636ac3cSMarcin Wojtas 4542636ac3cSMarcin Wojtas /* Flags for special SoC configurations */ 4552636ac3cSMarcin Wojtas bool neta_armada3700; 4568d5047cfSMarcin Wojtas u16 rx_offset_correction; 4579768b45cSJane Li const struct mbus_dram_target_info *dram_target_info; 458c5aff182SThomas Petazzoni }; 459c5aff182SThomas Petazzoni 4606a20c175SThomas Petazzoni /* The mvneta_tx_desc and mvneta_rx_desc structures describe the 461c5aff182SThomas Petazzoni * layout of the transmit and reception DMA descriptors, and their 462c5aff182SThomas Petazzoni * layout is therefore defined by the hardware design 463c5aff182SThomas Petazzoni */ 4646083ed44SThomas Petazzoni 465c5aff182SThomas Petazzoni #define MVNETA_TX_L3_OFF_SHIFT 0 466c5aff182SThomas Petazzoni #define MVNETA_TX_IP_HLEN_SHIFT 8 467c5aff182SThomas Petazzoni #define MVNETA_TX_L4_UDP BIT(16) 468c5aff182SThomas Petazzoni #define MVNETA_TX_L3_IP6 BIT(17) 469c5aff182SThomas Petazzoni #define MVNETA_TXD_IP_CSUM BIT(18) 470c5aff182SThomas Petazzoni #define MVNETA_TXD_Z_PAD BIT(19) 471c5aff182SThomas Petazzoni #define MVNETA_TXD_L_DESC BIT(20) 472c5aff182SThomas Petazzoni #define MVNETA_TXD_F_DESC BIT(21) 473c5aff182SThomas Petazzoni #define MVNETA_TXD_FLZ_DESC (MVNETA_TXD_Z_PAD | \ 474c5aff182SThomas Petazzoni MVNETA_TXD_L_DESC | \ 475c5aff182SThomas Petazzoni MVNETA_TXD_F_DESC) 476c5aff182SThomas Petazzoni #define MVNETA_TX_L4_CSUM_FULL BIT(30) 477c5aff182SThomas Petazzoni #define MVNETA_TX_L4_CSUM_NOT BIT(31) 478c5aff182SThomas Petazzoni 479c5aff182SThomas Petazzoni #define MVNETA_RXD_ERR_CRC 0x0 480dc35a10fSMarcin Wojtas #define MVNETA_RXD_BM_POOL_SHIFT 13 481dc35a10fSMarcin Wojtas #define MVNETA_RXD_BM_POOL_MASK (BIT(13) | BIT(14)) 482c5aff182SThomas Petazzoni #define MVNETA_RXD_ERR_SUMMARY BIT(16) 483c5aff182SThomas Petazzoni #define MVNETA_RXD_ERR_OVERRUN BIT(17) 484c5aff182SThomas Petazzoni #define MVNETA_RXD_ERR_LEN BIT(18) 485c5aff182SThomas Petazzoni #define MVNETA_RXD_ERR_RESOURCE (BIT(17) | BIT(18)) 486c5aff182SThomas Petazzoni #define MVNETA_RXD_ERR_CODE_MASK (BIT(17) | BIT(18)) 487c5aff182SThomas Petazzoni #define MVNETA_RXD_L3_IP4 BIT(25) 488562e2f46SYelena Krivosheev #define MVNETA_RXD_LAST_DESC BIT(26) 489562e2f46SYelena Krivosheev #define MVNETA_RXD_FIRST_DESC BIT(27) 490562e2f46SYelena Krivosheev #define MVNETA_RXD_FIRST_LAST_DESC (MVNETA_RXD_FIRST_DESC | \ 491562e2f46SYelena Krivosheev MVNETA_RXD_LAST_DESC) 492c5aff182SThomas Petazzoni #define MVNETA_RXD_L4_CSUM_OK BIT(30) 493c5aff182SThomas Petazzoni 4949ad8fef6SThomas Petazzoni #if defined(__LITTLE_ENDIAN) 4956083ed44SThomas Petazzoni struct mvneta_tx_desc { 4966083ed44SThomas Petazzoni u32 command; /* Options used by HW for packet transmitting.*/ 497fbd1d524SAlexandre Belloni u16 reserved1; /* csum_l4 (for future use) */ 4986083ed44SThomas Petazzoni u16 data_size; /* Data size of transmitted packet in bytes */ 4996083ed44SThomas Petazzoni u32 buf_phys_addr; /* Physical addr of transmitted buffer */ 5006083ed44SThomas Petazzoni u32 reserved2; /* hw_cmd - (for future use, PMT) */ 5016083ed44SThomas Petazzoni u32 reserved3[4]; /* Reserved - (for future use) */ 5026083ed44SThomas Petazzoni }; 5036083ed44SThomas Petazzoni 5046083ed44SThomas Petazzoni struct mvneta_rx_desc { 5056083ed44SThomas Petazzoni u32 status; /* Info about received packet */ 506c5aff182SThomas Petazzoni u16 reserved1; /* pnc_info - (for future use, PnC) */ 507c5aff182SThomas Petazzoni u16 data_size; /* Size of received packet in bytes */ 5086083ed44SThomas Petazzoni 509c5aff182SThomas Petazzoni u32 buf_phys_addr; /* Physical address of the buffer */ 510c5aff182SThomas Petazzoni u32 reserved2; /* pnc_flow_id (for future use, PnC) */ 5116083ed44SThomas Petazzoni 512c5aff182SThomas Petazzoni u32 buf_cookie; /* cookie for access to RX buffer in rx path */ 513c5aff182SThomas Petazzoni u16 reserved3; /* prefetch_cmd, for future use */ 514c5aff182SThomas Petazzoni u16 reserved4; /* csum_l4 - (for future use, PnC) */ 5156083ed44SThomas Petazzoni 516c5aff182SThomas Petazzoni u32 reserved5; /* pnc_extra PnC (for future use, PnC) */ 517c5aff182SThomas Petazzoni u32 reserved6; /* hw_cmd (for future use, PnC and HWF) */ 518c5aff182SThomas Petazzoni }; 5199ad8fef6SThomas Petazzoni #else 5209ad8fef6SThomas Petazzoni struct mvneta_tx_desc { 5219ad8fef6SThomas Petazzoni u16 data_size; /* Data size of transmitted packet in bytes */ 522fbd1d524SAlexandre Belloni u16 reserved1; /* csum_l4 (for future use) */ 5239ad8fef6SThomas Petazzoni u32 command; /* Options used by HW for packet transmitting.*/ 5249ad8fef6SThomas Petazzoni u32 reserved2; /* hw_cmd - (for future use, PMT) */ 5259ad8fef6SThomas Petazzoni u32 buf_phys_addr; /* Physical addr of transmitted buffer */ 5269ad8fef6SThomas Petazzoni u32 reserved3[4]; /* Reserved - (for future use) */ 5279ad8fef6SThomas Petazzoni }; 5289ad8fef6SThomas Petazzoni 5299ad8fef6SThomas Petazzoni struct mvneta_rx_desc { 5309ad8fef6SThomas Petazzoni u16 data_size; /* Size of received packet in bytes */ 5319ad8fef6SThomas Petazzoni u16 reserved1; /* pnc_info - (for future use, PnC) */ 5329ad8fef6SThomas Petazzoni u32 status; /* Info about received packet */ 5339ad8fef6SThomas Petazzoni 5349ad8fef6SThomas Petazzoni u32 reserved2; /* pnc_flow_id (for future use, PnC) */ 5359ad8fef6SThomas Petazzoni u32 buf_phys_addr; /* Physical address of the buffer */ 5369ad8fef6SThomas Petazzoni 5379ad8fef6SThomas Petazzoni u16 reserved4; /* csum_l4 - (for future use, PnC) */ 5389ad8fef6SThomas Petazzoni u16 reserved3; /* prefetch_cmd, for future use */ 5399ad8fef6SThomas Petazzoni u32 buf_cookie; /* cookie for access to RX buffer in rx path */ 5409ad8fef6SThomas Petazzoni 5419ad8fef6SThomas Petazzoni u32 reserved5; /* pnc_extra PnC (for future use, PnC) */ 5429ad8fef6SThomas Petazzoni u32 reserved6; /* hw_cmd (for future use, PnC and HWF) */ 5439ad8fef6SThomas Petazzoni }; 5449ad8fef6SThomas Petazzoni #endif 545c5aff182SThomas Petazzoni 546c5aff182SThomas Petazzoni struct mvneta_tx_queue { 547c5aff182SThomas Petazzoni /* Number of this TX queue, in the range 0-7 */ 548c5aff182SThomas Petazzoni u8 id; 549c5aff182SThomas Petazzoni 550c5aff182SThomas Petazzoni /* Number of TX DMA descriptors in the descriptor ring */ 551c5aff182SThomas Petazzoni int size; 552c5aff182SThomas Petazzoni 553c5aff182SThomas Petazzoni /* Number of currently used TX DMA descriptor in the 5546a20c175SThomas Petazzoni * descriptor ring 5556a20c175SThomas Petazzoni */ 556c5aff182SThomas Petazzoni int count; 5572a90f7e1SSimon Guinot int pending; 5588eef5f97SEzequiel Garcia int tx_stop_threshold; 5598eef5f97SEzequiel Garcia int tx_wake_threshold; 560c5aff182SThomas Petazzoni 561c5aff182SThomas Petazzoni /* Array of transmitted skb */ 562c5aff182SThomas Petazzoni struct sk_buff **tx_skb; 563c5aff182SThomas Petazzoni 564c5aff182SThomas Petazzoni /* Index of last TX DMA descriptor that was inserted */ 565c5aff182SThomas Petazzoni int txq_put_index; 566c5aff182SThomas Petazzoni 567c5aff182SThomas Petazzoni /* Index of the TX DMA descriptor to be cleaned up */ 568c5aff182SThomas Petazzoni int txq_get_index; 569c5aff182SThomas Petazzoni 570c5aff182SThomas Petazzoni u32 done_pkts_coal; 571c5aff182SThomas Petazzoni 572c5aff182SThomas Petazzoni /* Virtual address of the TX DMA descriptors array */ 573c5aff182SThomas Petazzoni struct mvneta_tx_desc *descs; 574c5aff182SThomas Petazzoni 575c5aff182SThomas Petazzoni /* DMA address of the TX DMA descriptors array */ 576c5aff182SThomas Petazzoni dma_addr_t descs_phys; 577c5aff182SThomas Petazzoni 578c5aff182SThomas Petazzoni /* Index of the last TX DMA descriptor */ 579c5aff182SThomas Petazzoni int last_desc; 580c5aff182SThomas Petazzoni 581c5aff182SThomas Petazzoni /* Index of the next TX DMA descriptor to process */ 582c5aff182SThomas Petazzoni int next_desc_to_proc; 5832adb719dSEzequiel Garcia 5842adb719dSEzequiel Garcia /* DMA buffers for TSO headers */ 5852adb719dSEzequiel Garcia char *tso_hdrs; 5862adb719dSEzequiel Garcia 5872adb719dSEzequiel Garcia /* DMA address of TSO headers */ 5882adb719dSEzequiel Garcia dma_addr_t tso_hdrs_phys; 58950bf8cb6SGregory CLEMENT 59050bf8cb6SGregory CLEMENT /* Affinity mask for CPUs*/ 59150bf8cb6SGregory CLEMENT cpumask_t affinity_mask; 592c5aff182SThomas Petazzoni }; 593c5aff182SThomas Petazzoni 594c5aff182SThomas Petazzoni struct mvneta_rx_queue { 595c5aff182SThomas Petazzoni /* rx queue number, in the range 0-7 */ 596c5aff182SThomas Petazzoni u8 id; 597c5aff182SThomas Petazzoni 598c5aff182SThomas Petazzoni /* num of rx descriptors in the rx descriptor ring */ 599c5aff182SThomas Petazzoni int size; 600c5aff182SThomas Petazzoni 601c5aff182SThomas Petazzoni u32 pkts_coal; 602c5aff182SThomas Petazzoni u32 time_coal; 603c5aff182SThomas Petazzoni 604f88bee1cSGregory CLEMENT /* Virtual address of the RX buffer */ 605f88bee1cSGregory CLEMENT void **buf_virt_addr; 606f88bee1cSGregory CLEMENT 607c5aff182SThomas Petazzoni /* Virtual address of the RX DMA descriptors array */ 608c5aff182SThomas Petazzoni struct mvneta_rx_desc *descs; 609c5aff182SThomas Petazzoni 610c5aff182SThomas Petazzoni /* DMA address of the RX DMA descriptors array */ 611c5aff182SThomas Petazzoni dma_addr_t descs_phys; 612c5aff182SThomas Petazzoni 613c5aff182SThomas Petazzoni /* Index of the last RX DMA descriptor */ 614c5aff182SThomas Petazzoni int last_desc; 615c5aff182SThomas Petazzoni 616c5aff182SThomas Petazzoni /* Index of the next RX DMA descriptor to process */ 617c5aff182SThomas Petazzoni int next_desc_to_proc; 61817a96da6SGregory CLEMENT 619562e2f46SYelena Krivosheev /* Index of first RX DMA descriptor to refill */ 620562e2f46SYelena Krivosheev int first_to_refill; 621562e2f46SYelena Krivosheev u32 refill_num; 622562e2f46SYelena Krivosheev 623562e2f46SYelena Krivosheev /* pointer to uncomplete skb buffer */ 624562e2f46SYelena Krivosheev struct sk_buff *skb; 625562e2f46SYelena Krivosheev int left_size; 626562e2f46SYelena Krivosheev 62717a96da6SGregory CLEMENT /* error counters */ 62817a96da6SGregory CLEMENT u32 skb_alloc_err; 62917a96da6SGregory CLEMENT u32 refill_err; 630c5aff182SThomas Petazzoni }; 631c5aff182SThomas Petazzoni 63284a3f4dbSSebastian Andrzej Siewior static enum cpuhp_state online_hpstate; 633edadb7faSEzequiel Garcia /* The hardware supports eight (8) rx queues, but we are only allowing 634edadb7faSEzequiel Garcia * the first one to be used. Therefore, let's just allocate one queue. 635edadb7faSEzequiel Garcia */ 636d8936657SMaxime Ripard static int rxq_number = 8; 637c5aff182SThomas Petazzoni static int txq_number = 8; 638c5aff182SThomas Petazzoni 639c5aff182SThomas Petazzoni static int rxq_def; 640c5aff182SThomas Petazzoni 641f19fadfcSwilly tarreau static int rx_copybreak __read_mostly = 256; 642562e2f46SYelena Krivosheev static int rx_header_size __read_mostly = 128; 643f19fadfcSwilly tarreau 644dc35a10fSMarcin Wojtas /* HW BM need that each port be identify by a unique ID */ 645dc35a10fSMarcin Wojtas static int global_port_id; 646dc35a10fSMarcin Wojtas 647c5aff182SThomas Petazzoni #define MVNETA_DRIVER_NAME "mvneta" 648c5aff182SThomas Petazzoni #define MVNETA_DRIVER_VERSION "1.0" 649c5aff182SThomas Petazzoni 650c5aff182SThomas Petazzoni /* Utility/helper methods */ 651c5aff182SThomas Petazzoni 652c5aff182SThomas Petazzoni /* Write helper method */ 653c5aff182SThomas Petazzoni static void mvreg_write(struct mvneta_port *pp, u32 offset, u32 data) 654c5aff182SThomas Petazzoni { 655c5aff182SThomas Petazzoni writel(data, pp->base + offset); 656c5aff182SThomas Petazzoni } 657c5aff182SThomas Petazzoni 658c5aff182SThomas Petazzoni /* Read helper method */ 659c5aff182SThomas Petazzoni static u32 mvreg_read(struct mvneta_port *pp, u32 offset) 660c5aff182SThomas Petazzoni { 661c5aff182SThomas Petazzoni return readl(pp->base + offset); 662c5aff182SThomas Petazzoni } 663c5aff182SThomas Petazzoni 664c5aff182SThomas Petazzoni /* Increment txq get counter */ 665c5aff182SThomas Petazzoni static void mvneta_txq_inc_get(struct mvneta_tx_queue *txq) 666c5aff182SThomas Petazzoni { 667c5aff182SThomas Petazzoni txq->txq_get_index++; 668c5aff182SThomas Petazzoni if (txq->txq_get_index == txq->size) 669c5aff182SThomas Petazzoni txq->txq_get_index = 0; 670c5aff182SThomas Petazzoni } 671c5aff182SThomas Petazzoni 672c5aff182SThomas Petazzoni /* Increment txq put counter */ 673c5aff182SThomas Petazzoni static void mvneta_txq_inc_put(struct mvneta_tx_queue *txq) 674c5aff182SThomas Petazzoni { 675c5aff182SThomas Petazzoni txq->txq_put_index++; 676c5aff182SThomas Petazzoni if (txq->txq_put_index == txq->size) 677c5aff182SThomas Petazzoni txq->txq_put_index = 0; 678c5aff182SThomas Petazzoni } 679c5aff182SThomas Petazzoni 680c5aff182SThomas Petazzoni 681c5aff182SThomas Petazzoni /* Clear all MIB counters */ 682c5aff182SThomas Petazzoni static void mvneta_mib_counters_clear(struct mvneta_port *pp) 683c5aff182SThomas Petazzoni { 684c5aff182SThomas Petazzoni int i; 685c5aff182SThomas Petazzoni u32 dummy; 686c5aff182SThomas Petazzoni 687c5aff182SThomas Petazzoni /* Perform dummy reads from MIB counters */ 688c5aff182SThomas Petazzoni for (i = 0; i < MVNETA_MIB_LATE_COLLISION; i += 4) 689c5aff182SThomas Petazzoni dummy = mvreg_read(pp, (MVNETA_MIB_COUNTERS_BASE + i)); 690e483911fSAndrew Lunn dummy = mvreg_read(pp, MVNETA_RX_DISCARD_FRAME_COUNT); 691e483911fSAndrew Lunn dummy = mvreg_read(pp, MVNETA_OVERRUN_FRAME_COUNT); 692c5aff182SThomas Petazzoni } 693c5aff182SThomas Petazzoni 694c5aff182SThomas Petazzoni /* Get System Network Statistics */ 695bc1f4470Sstephen hemminger static void 6962dc0d2b4SBaoyou Xie mvneta_get_stats64(struct net_device *dev, 697c5aff182SThomas Petazzoni struct rtnl_link_stats64 *stats) 698c5aff182SThomas Petazzoni { 699c5aff182SThomas Petazzoni struct mvneta_port *pp = netdev_priv(dev); 700c5aff182SThomas Petazzoni unsigned int start; 70174c41b04Swilly tarreau int cpu; 702c5aff182SThomas Petazzoni 70374c41b04Swilly tarreau for_each_possible_cpu(cpu) { 70474c41b04Swilly tarreau struct mvneta_pcpu_stats *cpu_stats; 70574c41b04Swilly tarreau u64 rx_packets; 70674c41b04Swilly tarreau u64 rx_bytes; 70774c41b04Swilly tarreau u64 tx_packets; 70874c41b04Swilly tarreau u64 tx_bytes; 709c5aff182SThomas Petazzoni 71074c41b04Swilly tarreau cpu_stats = per_cpu_ptr(pp->stats, cpu); 711c5aff182SThomas Petazzoni do { 71257a7744eSEric W. Biederman start = u64_stats_fetch_begin_irq(&cpu_stats->syncp); 71374c41b04Swilly tarreau rx_packets = cpu_stats->rx_packets; 71474c41b04Swilly tarreau rx_bytes = cpu_stats->rx_bytes; 71574c41b04Swilly tarreau tx_packets = cpu_stats->tx_packets; 71674c41b04Swilly tarreau tx_bytes = cpu_stats->tx_bytes; 71757a7744eSEric W. Biederman } while (u64_stats_fetch_retry_irq(&cpu_stats->syncp, start)); 718c5aff182SThomas Petazzoni 71974c41b04Swilly tarreau stats->rx_packets += rx_packets; 72074c41b04Swilly tarreau stats->rx_bytes += rx_bytes; 72174c41b04Swilly tarreau stats->tx_packets += tx_packets; 72274c41b04Swilly tarreau stats->tx_bytes += tx_bytes; 72374c41b04Swilly tarreau } 724c5aff182SThomas Petazzoni 725c5aff182SThomas Petazzoni stats->rx_errors = dev->stats.rx_errors; 726c5aff182SThomas Petazzoni stats->rx_dropped = dev->stats.rx_dropped; 727c5aff182SThomas Petazzoni 728c5aff182SThomas Petazzoni stats->tx_dropped = dev->stats.tx_dropped; 729c5aff182SThomas Petazzoni } 730c5aff182SThomas Petazzoni 731c5aff182SThomas Petazzoni /* Rx descriptors helper methods */ 732c5aff182SThomas Petazzoni 7335428213cSwilly tarreau /* Checks whether the RX descriptor having this status is both the first 7345428213cSwilly tarreau * and the last descriptor for the RX packet. Each RX packet is currently 735c5aff182SThomas Petazzoni * received through a single RX descriptor, so not having each RX 736c5aff182SThomas Petazzoni * descriptor with its first and last bits set is an error 737c5aff182SThomas Petazzoni */ 7385428213cSwilly tarreau static int mvneta_rxq_desc_is_first_last(u32 status) 739c5aff182SThomas Petazzoni { 7405428213cSwilly tarreau return (status & MVNETA_RXD_FIRST_LAST_DESC) == 741c5aff182SThomas Petazzoni MVNETA_RXD_FIRST_LAST_DESC; 742c5aff182SThomas Petazzoni } 743c5aff182SThomas Petazzoni 744c5aff182SThomas Petazzoni /* Add number of descriptors ready to receive new packets */ 745c5aff182SThomas Petazzoni static void mvneta_rxq_non_occup_desc_add(struct mvneta_port *pp, 746c5aff182SThomas Petazzoni struct mvneta_rx_queue *rxq, 747c5aff182SThomas Petazzoni int ndescs) 748c5aff182SThomas Petazzoni { 749c5aff182SThomas Petazzoni /* Only MVNETA_RXQ_ADD_NON_OCCUPIED_MAX (255) descriptors can 7506a20c175SThomas Petazzoni * be added at once 7516a20c175SThomas Petazzoni */ 752c5aff182SThomas Petazzoni while (ndescs > MVNETA_RXQ_ADD_NON_OCCUPIED_MAX) { 753c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id), 754c5aff182SThomas Petazzoni (MVNETA_RXQ_ADD_NON_OCCUPIED_MAX << 755c5aff182SThomas Petazzoni MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT)); 756c5aff182SThomas Petazzoni ndescs -= MVNETA_RXQ_ADD_NON_OCCUPIED_MAX; 757c5aff182SThomas Petazzoni } 758c5aff182SThomas Petazzoni 759c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id), 760c5aff182SThomas Petazzoni (ndescs << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT)); 761c5aff182SThomas Petazzoni } 762c5aff182SThomas Petazzoni 763c5aff182SThomas Petazzoni /* Get number of RX descriptors occupied by received packets */ 764c5aff182SThomas Petazzoni static int mvneta_rxq_busy_desc_num_get(struct mvneta_port *pp, 765c5aff182SThomas Petazzoni struct mvneta_rx_queue *rxq) 766c5aff182SThomas Petazzoni { 767c5aff182SThomas Petazzoni u32 val; 768c5aff182SThomas Petazzoni 769c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_RXQ_STATUS_REG(rxq->id)); 770c5aff182SThomas Petazzoni return val & MVNETA_RXQ_OCCUPIED_ALL_MASK; 771c5aff182SThomas Petazzoni } 772c5aff182SThomas Petazzoni 7736a20c175SThomas Petazzoni /* Update num of rx desc called upon return from rx path or 774c5aff182SThomas Petazzoni * from mvneta_rxq_drop_pkts(). 775c5aff182SThomas Petazzoni */ 776c5aff182SThomas Petazzoni static void mvneta_rxq_desc_num_update(struct mvneta_port *pp, 777c5aff182SThomas Petazzoni struct mvneta_rx_queue *rxq, 778c5aff182SThomas Petazzoni int rx_done, int rx_filled) 779c5aff182SThomas Petazzoni { 780c5aff182SThomas Petazzoni u32 val; 781c5aff182SThomas Petazzoni 782c5aff182SThomas Petazzoni if ((rx_done <= 0xff) && (rx_filled <= 0xff)) { 783c5aff182SThomas Petazzoni val = rx_done | 784c5aff182SThomas Petazzoni (rx_filled << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT); 785c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id), val); 786c5aff182SThomas Petazzoni return; 787c5aff182SThomas Petazzoni } 788c5aff182SThomas Petazzoni 789c5aff182SThomas Petazzoni /* Only 255 descriptors can be added at once */ 790c5aff182SThomas Petazzoni while ((rx_done > 0) || (rx_filled > 0)) { 791c5aff182SThomas Petazzoni if (rx_done <= 0xff) { 792c5aff182SThomas Petazzoni val = rx_done; 793c5aff182SThomas Petazzoni rx_done = 0; 794c5aff182SThomas Petazzoni } else { 795c5aff182SThomas Petazzoni val = 0xff; 796c5aff182SThomas Petazzoni rx_done -= 0xff; 797c5aff182SThomas Petazzoni } 798c5aff182SThomas Petazzoni if (rx_filled <= 0xff) { 799c5aff182SThomas Petazzoni val |= rx_filled << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT; 800c5aff182SThomas Petazzoni rx_filled = 0; 801c5aff182SThomas Petazzoni } else { 802c5aff182SThomas Petazzoni val |= 0xff << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT; 803c5aff182SThomas Petazzoni rx_filled -= 0xff; 804c5aff182SThomas Petazzoni } 805c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id), val); 806c5aff182SThomas Petazzoni } 807c5aff182SThomas Petazzoni } 808c5aff182SThomas Petazzoni 809c5aff182SThomas Petazzoni /* Get pointer to next RX descriptor to be processed by SW */ 810c5aff182SThomas Petazzoni static struct mvneta_rx_desc * 811c5aff182SThomas Petazzoni mvneta_rxq_next_desc_get(struct mvneta_rx_queue *rxq) 812c5aff182SThomas Petazzoni { 813c5aff182SThomas Petazzoni int rx_desc = rxq->next_desc_to_proc; 814c5aff182SThomas Petazzoni 815c5aff182SThomas Petazzoni rxq->next_desc_to_proc = MVNETA_QUEUE_NEXT_DESC(rxq, rx_desc); 81634e4179dSwilly tarreau prefetch(rxq->descs + rxq->next_desc_to_proc); 817c5aff182SThomas Petazzoni return rxq->descs + rx_desc; 818c5aff182SThomas Petazzoni } 819c5aff182SThomas Petazzoni 820c5aff182SThomas Petazzoni /* Change maximum receive size of the port. */ 821c5aff182SThomas Petazzoni static void mvneta_max_rx_size_set(struct mvneta_port *pp, int max_rx_size) 822c5aff182SThomas Petazzoni { 823c5aff182SThomas Petazzoni u32 val; 824c5aff182SThomas Petazzoni 825c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_GMAC_CTRL_0); 826c5aff182SThomas Petazzoni val &= ~MVNETA_GMAC_MAX_RX_SIZE_MASK; 827c5aff182SThomas Petazzoni val |= ((max_rx_size - MVNETA_MH_SIZE) / 2) << 828c5aff182SThomas Petazzoni MVNETA_GMAC_MAX_RX_SIZE_SHIFT; 829c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_GMAC_CTRL_0, val); 830c5aff182SThomas Petazzoni } 831c5aff182SThomas Petazzoni 832c5aff182SThomas Petazzoni 833c5aff182SThomas Petazzoni /* Set rx queue offset */ 834c5aff182SThomas Petazzoni static void mvneta_rxq_offset_set(struct mvneta_port *pp, 835c5aff182SThomas Petazzoni struct mvneta_rx_queue *rxq, 836c5aff182SThomas Petazzoni int offset) 837c5aff182SThomas Petazzoni { 838c5aff182SThomas Petazzoni u32 val; 839c5aff182SThomas Petazzoni 840c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_RXQ_CONFIG_REG(rxq->id)); 841c5aff182SThomas Petazzoni val &= ~MVNETA_RXQ_PKT_OFFSET_ALL_MASK; 842c5aff182SThomas Petazzoni 843c5aff182SThomas Petazzoni /* Offset is in */ 844c5aff182SThomas Petazzoni val |= MVNETA_RXQ_PKT_OFFSET_MASK(offset >> 3); 845c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_RXQ_CONFIG_REG(rxq->id), val); 846c5aff182SThomas Petazzoni } 847c5aff182SThomas Petazzoni 848c5aff182SThomas Petazzoni 849c5aff182SThomas Petazzoni /* Tx descriptors helper methods */ 850c5aff182SThomas Petazzoni 851c5aff182SThomas Petazzoni /* Update HW with number of TX descriptors to be sent */ 852c5aff182SThomas Petazzoni static void mvneta_txq_pend_desc_add(struct mvneta_port *pp, 853c5aff182SThomas Petazzoni struct mvneta_tx_queue *txq, 854c5aff182SThomas Petazzoni int pend_desc) 855c5aff182SThomas Petazzoni { 856c5aff182SThomas Petazzoni u32 val; 857c5aff182SThomas Petazzoni 8580d63785cSSimon Guinot pend_desc += txq->pending; 8590d63785cSSimon Guinot 8600d63785cSSimon Guinot /* Only 255 Tx descriptors can be added at once */ 8610d63785cSSimon Guinot do { 8620d63785cSSimon Guinot val = min(pend_desc, 255); 863c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val); 8640d63785cSSimon Guinot pend_desc -= val; 8650d63785cSSimon Guinot } while (pend_desc > 0); 8662a90f7e1SSimon Guinot txq->pending = 0; 867c5aff182SThomas Petazzoni } 868c5aff182SThomas Petazzoni 869c5aff182SThomas Petazzoni /* Get pointer to next TX descriptor to be processed (send) by HW */ 870c5aff182SThomas Petazzoni static struct mvneta_tx_desc * 871c5aff182SThomas Petazzoni mvneta_txq_next_desc_get(struct mvneta_tx_queue *txq) 872c5aff182SThomas Petazzoni { 873c5aff182SThomas Petazzoni int tx_desc = txq->next_desc_to_proc; 874c5aff182SThomas Petazzoni 875c5aff182SThomas Petazzoni txq->next_desc_to_proc = MVNETA_QUEUE_NEXT_DESC(txq, tx_desc); 876c5aff182SThomas Petazzoni return txq->descs + tx_desc; 877c5aff182SThomas Petazzoni } 878c5aff182SThomas Petazzoni 879c5aff182SThomas Petazzoni /* Release the last allocated TX descriptor. Useful to handle DMA 8806a20c175SThomas Petazzoni * mapping failures in the TX path. 8816a20c175SThomas Petazzoni */ 882c5aff182SThomas Petazzoni static void mvneta_txq_desc_put(struct mvneta_tx_queue *txq) 883c5aff182SThomas Petazzoni { 884c5aff182SThomas Petazzoni if (txq->next_desc_to_proc == 0) 885c5aff182SThomas Petazzoni txq->next_desc_to_proc = txq->last_desc - 1; 886c5aff182SThomas Petazzoni else 887c5aff182SThomas Petazzoni txq->next_desc_to_proc--; 888c5aff182SThomas Petazzoni } 889c5aff182SThomas Petazzoni 890c5aff182SThomas Petazzoni /* Set rxq buf size */ 891c5aff182SThomas Petazzoni static void mvneta_rxq_buf_size_set(struct mvneta_port *pp, 892c5aff182SThomas Petazzoni struct mvneta_rx_queue *rxq, 893c5aff182SThomas Petazzoni int buf_size) 894c5aff182SThomas Petazzoni { 895c5aff182SThomas Petazzoni u32 val; 896c5aff182SThomas Petazzoni 897c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_RXQ_SIZE_REG(rxq->id)); 898c5aff182SThomas Petazzoni 899c5aff182SThomas Petazzoni val &= ~MVNETA_RXQ_BUF_SIZE_MASK; 900c5aff182SThomas Petazzoni val |= ((buf_size >> 3) << MVNETA_RXQ_BUF_SIZE_SHIFT); 901c5aff182SThomas Petazzoni 902c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_RXQ_SIZE_REG(rxq->id), val); 903c5aff182SThomas Petazzoni } 904c5aff182SThomas Petazzoni 905c5aff182SThomas Petazzoni /* Disable buffer management (BM) */ 906c5aff182SThomas Petazzoni static void mvneta_rxq_bm_disable(struct mvneta_port *pp, 907c5aff182SThomas Petazzoni struct mvneta_rx_queue *rxq) 908c5aff182SThomas Petazzoni { 909c5aff182SThomas Petazzoni u32 val; 910c5aff182SThomas Petazzoni 911c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_RXQ_CONFIG_REG(rxq->id)); 912c5aff182SThomas Petazzoni val &= ~MVNETA_RXQ_HW_BUF_ALLOC; 913c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_RXQ_CONFIG_REG(rxq->id), val); 914c5aff182SThomas Petazzoni } 915c5aff182SThomas Petazzoni 916dc35a10fSMarcin Wojtas /* Enable buffer management (BM) */ 917dc35a10fSMarcin Wojtas static void mvneta_rxq_bm_enable(struct mvneta_port *pp, 918dc35a10fSMarcin Wojtas struct mvneta_rx_queue *rxq) 919dc35a10fSMarcin Wojtas { 920dc35a10fSMarcin Wojtas u32 val; 921dc35a10fSMarcin Wojtas 922dc35a10fSMarcin Wojtas val = mvreg_read(pp, MVNETA_RXQ_CONFIG_REG(rxq->id)); 923dc35a10fSMarcin Wojtas val |= MVNETA_RXQ_HW_BUF_ALLOC; 924dc35a10fSMarcin Wojtas mvreg_write(pp, MVNETA_RXQ_CONFIG_REG(rxq->id), val); 925dc35a10fSMarcin Wojtas } 926dc35a10fSMarcin Wojtas 927dc35a10fSMarcin Wojtas /* Notify HW about port's assignment of pool for bigger packets */ 928dc35a10fSMarcin Wojtas static void mvneta_rxq_long_pool_set(struct mvneta_port *pp, 929dc35a10fSMarcin Wojtas struct mvneta_rx_queue *rxq) 930dc35a10fSMarcin Wojtas { 931dc35a10fSMarcin Wojtas u32 val; 932dc35a10fSMarcin Wojtas 933dc35a10fSMarcin Wojtas val = mvreg_read(pp, MVNETA_RXQ_CONFIG_REG(rxq->id)); 934dc35a10fSMarcin Wojtas val &= ~MVNETA_RXQ_LONG_POOL_ID_MASK; 935dc35a10fSMarcin Wojtas val |= (pp->pool_long->id << MVNETA_RXQ_LONG_POOL_ID_SHIFT); 936dc35a10fSMarcin Wojtas 937dc35a10fSMarcin Wojtas mvreg_write(pp, MVNETA_RXQ_CONFIG_REG(rxq->id), val); 938dc35a10fSMarcin Wojtas } 939dc35a10fSMarcin Wojtas 940dc35a10fSMarcin Wojtas /* Notify HW about port's assignment of pool for smaller packets */ 941dc35a10fSMarcin Wojtas static void mvneta_rxq_short_pool_set(struct mvneta_port *pp, 942dc35a10fSMarcin Wojtas struct mvneta_rx_queue *rxq) 943dc35a10fSMarcin Wojtas { 944dc35a10fSMarcin Wojtas u32 val; 945dc35a10fSMarcin Wojtas 946dc35a10fSMarcin Wojtas val = mvreg_read(pp, MVNETA_RXQ_CONFIG_REG(rxq->id)); 947dc35a10fSMarcin Wojtas val &= ~MVNETA_RXQ_SHORT_POOL_ID_MASK; 948dc35a10fSMarcin Wojtas val |= (pp->pool_short->id << MVNETA_RXQ_SHORT_POOL_ID_SHIFT); 949dc35a10fSMarcin Wojtas 950dc35a10fSMarcin Wojtas mvreg_write(pp, MVNETA_RXQ_CONFIG_REG(rxq->id), val); 951dc35a10fSMarcin Wojtas } 952dc35a10fSMarcin Wojtas 953dc35a10fSMarcin Wojtas /* Set port's receive buffer size for assigned BM pool */ 954dc35a10fSMarcin Wojtas static inline void mvneta_bm_pool_bufsize_set(struct mvneta_port *pp, 955dc35a10fSMarcin Wojtas int buf_size, 956dc35a10fSMarcin Wojtas u8 pool_id) 957dc35a10fSMarcin Wojtas { 958dc35a10fSMarcin Wojtas u32 val; 959dc35a10fSMarcin Wojtas 960dc35a10fSMarcin Wojtas if (!IS_ALIGNED(buf_size, 8)) { 961dc35a10fSMarcin Wojtas dev_warn(pp->dev->dev.parent, 962dc35a10fSMarcin Wojtas "illegal buf_size value %d, round to %d\n", 963dc35a10fSMarcin Wojtas buf_size, ALIGN(buf_size, 8)); 964dc35a10fSMarcin Wojtas buf_size = ALIGN(buf_size, 8); 965dc35a10fSMarcin Wojtas } 966dc35a10fSMarcin Wojtas 967dc35a10fSMarcin Wojtas val = mvreg_read(pp, MVNETA_PORT_POOL_BUFFER_SZ_REG(pool_id)); 968dc35a10fSMarcin Wojtas val |= buf_size & MVNETA_PORT_POOL_BUFFER_SZ_MASK; 969dc35a10fSMarcin Wojtas mvreg_write(pp, MVNETA_PORT_POOL_BUFFER_SZ_REG(pool_id), val); 970dc35a10fSMarcin Wojtas } 971dc35a10fSMarcin Wojtas 972dc35a10fSMarcin Wojtas /* Configure MBUS window in order to enable access BM internal SRAM */ 973dc35a10fSMarcin Wojtas static int mvneta_mbus_io_win_set(struct mvneta_port *pp, u32 base, u32 wsize, 974dc35a10fSMarcin Wojtas u8 target, u8 attr) 975dc35a10fSMarcin Wojtas { 976dc35a10fSMarcin Wojtas u32 win_enable, win_protect; 977dc35a10fSMarcin Wojtas int i; 978dc35a10fSMarcin Wojtas 979dc35a10fSMarcin Wojtas win_enable = mvreg_read(pp, MVNETA_BASE_ADDR_ENABLE); 980dc35a10fSMarcin Wojtas 981dc35a10fSMarcin Wojtas if (pp->bm_win_id < 0) { 982dc35a10fSMarcin Wojtas /* Find first not occupied window */ 983dc35a10fSMarcin Wojtas for (i = 0; i < MVNETA_MAX_DECODE_WIN; i++) { 984dc35a10fSMarcin Wojtas if (win_enable & (1 << i)) { 985dc35a10fSMarcin Wojtas pp->bm_win_id = i; 986dc35a10fSMarcin Wojtas break; 987dc35a10fSMarcin Wojtas } 988dc35a10fSMarcin Wojtas } 989dc35a10fSMarcin Wojtas if (i == MVNETA_MAX_DECODE_WIN) 990dc35a10fSMarcin Wojtas return -ENOMEM; 991dc35a10fSMarcin Wojtas } else { 992dc35a10fSMarcin Wojtas i = pp->bm_win_id; 993dc35a10fSMarcin Wojtas } 994dc35a10fSMarcin Wojtas 995dc35a10fSMarcin Wojtas mvreg_write(pp, MVNETA_WIN_BASE(i), 0); 996dc35a10fSMarcin Wojtas mvreg_write(pp, MVNETA_WIN_SIZE(i), 0); 997dc35a10fSMarcin Wojtas 998dc35a10fSMarcin Wojtas if (i < 4) 999dc35a10fSMarcin Wojtas mvreg_write(pp, MVNETA_WIN_REMAP(i), 0); 1000dc35a10fSMarcin Wojtas 1001dc35a10fSMarcin Wojtas mvreg_write(pp, MVNETA_WIN_BASE(i), (base & 0xffff0000) | 1002dc35a10fSMarcin Wojtas (attr << 8) | target); 1003dc35a10fSMarcin Wojtas 1004dc35a10fSMarcin Wojtas mvreg_write(pp, MVNETA_WIN_SIZE(i), (wsize - 1) & 0xffff0000); 1005dc35a10fSMarcin Wojtas 1006dc35a10fSMarcin Wojtas win_protect = mvreg_read(pp, MVNETA_ACCESS_PROTECT_ENABLE); 1007dc35a10fSMarcin Wojtas win_protect |= 3 << (2 * i); 1008dc35a10fSMarcin Wojtas mvreg_write(pp, MVNETA_ACCESS_PROTECT_ENABLE, win_protect); 1009dc35a10fSMarcin Wojtas 1010dc35a10fSMarcin Wojtas win_enable &= ~(1 << i); 1011dc35a10fSMarcin Wojtas mvreg_write(pp, MVNETA_BASE_ADDR_ENABLE, win_enable); 1012dc35a10fSMarcin Wojtas 1013dc35a10fSMarcin Wojtas return 0; 1014dc35a10fSMarcin Wojtas } 1015dc35a10fSMarcin Wojtas 10162636ac3cSMarcin Wojtas static int mvneta_bm_port_mbus_init(struct mvneta_port *pp) 1017dc35a10fSMarcin Wojtas { 10182636ac3cSMarcin Wojtas u32 wsize; 1019dc35a10fSMarcin Wojtas u8 target, attr; 1020dc35a10fSMarcin Wojtas int err; 1021dc35a10fSMarcin Wojtas 1022dc35a10fSMarcin Wojtas /* Get BM window information */ 1023dc35a10fSMarcin Wojtas err = mvebu_mbus_get_io_win_info(pp->bm_priv->bppi_phys_addr, &wsize, 1024dc35a10fSMarcin Wojtas &target, &attr); 1025dc35a10fSMarcin Wojtas if (err < 0) 1026dc35a10fSMarcin Wojtas return err; 1027dc35a10fSMarcin Wojtas 1028dc35a10fSMarcin Wojtas pp->bm_win_id = -1; 1029dc35a10fSMarcin Wojtas 1030dc35a10fSMarcin Wojtas /* Open NETA -> BM window */ 1031dc35a10fSMarcin Wojtas err = mvneta_mbus_io_win_set(pp, pp->bm_priv->bppi_phys_addr, wsize, 1032dc35a10fSMarcin Wojtas target, attr); 1033dc35a10fSMarcin Wojtas if (err < 0) { 1034dc35a10fSMarcin Wojtas netdev_info(pp->dev, "fail to configure mbus window to BM\n"); 1035dc35a10fSMarcin Wojtas return err; 1036dc35a10fSMarcin Wojtas } 10372636ac3cSMarcin Wojtas return 0; 10382636ac3cSMarcin Wojtas } 10392636ac3cSMarcin Wojtas 10402636ac3cSMarcin Wojtas /* Assign and initialize pools for port. In case of fail 10412636ac3cSMarcin Wojtas * buffer manager will remain disabled for current port. 10422636ac3cSMarcin Wojtas */ 10432636ac3cSMarcin Wojtas static int mvneta_bm_port_init(struct platform_device *pdev, 10442636ac3cSMarcin Wojtas struct mvneta_port *pp) 10452636ac3cSMarcin Wojtas { 10462636ac3cSMarcin Wojtas struct device_node *dn = pdev->dev.of_node; 10472636ac3cSMarcin Wojtas u32 long_pool_id, short_pool_id; 10482636ac3cSMarcin Wojtas 10492636ac3cSMarcin Wojtas if (!pp->neta_armada3700) { 10502636ac3cSMarcin Wojtas int ret; 10512636ac3cSMarcin Wojtas 10522636ac3cSMarcin Wojtas ret = mvneta_bm_port_mbus_init(pp); 10532636ac3cSMarcin Wojtas if (ret) 10542636ac3cSMarcin Wojtas return ret; 10552636ac3cSMarcin Wojtas } 1056dc35a10fSMarcin Wojtas 1057dc35a10fSMarcin Wojtas if (of_property_read_u32(dn, "bm,pool-long", &long_pool_id)) { 1058dc35a10fSMarcin Wojtas netdev_info(pp->dev, "missing long pool id\n"); 1059dc35a10fSMarcin Wojtas return -EINVAL; 1060dc35a10fSMarcin Wojtas } 1061dc35a10fSMarcin Wojtas 1062dc35a10fSMarcin Wojtas /* Create port's long pool depending on mtu */ 1063dc35a10fSMarcin Wojtas pp->pool_long = mvneta_bm_pool_use(pp->bm_priv, long_pool_id, 1064dc35a10fSMarcin Wojtas MVNETA_BM_LONG, pp->id, 1065dc35a10fSMarcin Wojtas MVNETA_RX_PKT_SIZE(pp->dev->mtu)); 1066dc35a10fSMarcin Wojtas if (!pp->pool_long) { 1067dc35a10fSMarcin Wojtas netdev_info(pp->dev, "fail to obtain long pool for port\n"); 1068dc35a10fSMarcin Wojtas return -ENOMEM; 1069dc35a10fSMarcin Wojtas } 1070dc35a10fSMarcin Wojtas 1071dc35a10fSMarcin Wojtas pp->pool_long->port_map |= 1 << pp->id; 1072dc35a10fSMarcin Wojtas 1073dc35a10fSMarcin Wojtas mvneta_bm_pool_bufsize_set(pp, pp->pool_long->buf_size, 1074dc35a10fSMarcin Wojtas pp->pool_long->id); 1075dc35a10fSMarcin Wojtas 1076dc35a10fSMarcin Wojtas /* If short pool id is not defined, assume using single pool */ 1077dc35a10fSMarcin Wojtas if (of_property_read_u32(dn, "bm,pool-short", &short_pool_id)) 1078dc35a10fSMarcin Wojtas short_pool_id = long_pool_id; 1079dc35a10fSMarcin Wojtas 1080dc35a10fSMarcin Wojtas /* Create port's short pool */ 1081dc35a10fSMarcin Wojtas pp->pool_short = mvneta_bm_pool_use(pp->bm_priv, short_pool_id, 1082dc35a10fSMarcin Wojtas MVNETA_BM_SHORT, pp->id, 1083dc35a10fSMarcin Wojtas MVNETA_BM_SHORT_PKT_SIZE); 1084dc35a10fSMarcin Wojtas if (!pp->pool_short) { 1085dc35a10fSMarcin Wojtas netdev_info(pp->dev, "fail to obtain short pool for port\n"); 1086dc35a10fSMarcin Wojtas mvneta_bm_pool_destroy(pp->bm_priv, pp->pool_long, 1 << pp->id); 1087dc35a10fSMarcin Wojtas return -ENOMEM; 1088dc35a10fSMarcin Wojtas } 1089dc35a10fSMarcin Wojtas 1090dc35a10fSMarcin Wojtas if (short_pool_id != long_pool_id) { 1091dc35a10fSMarcin Wojtas pp->pool_short->port_map |= 1 << pp->id; 1092dc35a10fSMarcin Wojtas mvneta_bm_pool_bufsize_set(pp, pp->pool_short->buf_size, 1093dc35a10fSMarcin Wojtas pp->pool_short->id); 1094dc35a10fSMarcin Wojtas } 1095dc35a10fSMarcin Wojtas 1096dc35a10fSMarcin Wojtas return 0; 1097dc35a10fSMarcin Wojtas } 1098dc35a10fSMarcin Wojtas 1099dc35a10fSMarcin Wojtas /* Update settings of a pool for bigger packets */ 1100dc35a10fSMarcin Wojtas static void mvneta_bm_update_mtu(struct mvneta_port *pp, int mtu) 1101dc35a10fSMarcin Wojtas { 1102dc35a10fSMarcin Wojtas struct mvneta_bm_pool *bm_pool = pp->pool_long; 1103baa11ebcSGregory CLEMENT struct hwbm_pool *hwbm_pool = &bm_pool->hwbm_pool; 1104dc35a10fSMarcin Wojtas int num; 1105dc35a10fSMarcin Wojtas 1106dc35a10fSMarcin Wojtas /* Release all buffers from long pool */ 1107dc35a10fSMarcin Wojtas mvneta_bm_bufs_free(pp->bm_priv, bm_pool, 1 << pp->id); 1108baa11ebcSGregory CLEMENT if (hwbm_pool->buf_num) { 1109dc35a10fSMarcin Wojtas WARN(1, "cannot free all buffers in pool %d\n", 1110dc35a10fSMarcin Wojtas bm_pool->id); 1111dc35a10fSMarcin Wojtas goto bm_mtu_err; 1112dc35a10fSMarcin Wojtas } 1113dc35a10fSMarcin Wojtas 1114dc35a10fSMarcin Wojtas bm_pool->pkt_size = MVNETA_RX_PKT_SIZE(mtu); 1115dc35a10fSMarcin Wojtas bm_pool->buf_size = MVNETA_RX_BUF_SIZE(bm_pool->pkt_size); 1116baa11ebcSGregory CLEMENT hwbm_pool->frag_size = SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) + 1117dc35a10fSMarcin Wojtas SKB_DATA_ALIGN(MVNETA_RX_BUF_SIZE(bm_pool->pkt_size)); 1118dc35a10fSMarcin Wojtas 1119dc35a10fSMarcin Wojtas /* Fill entire long pool */ 1120baa11ebcSGregory CLEMENT num = hwbm_pool_add(hwbm_pool, hwbm_pool->size, GFP_ATOMIC); 1121baa11ebcSGregory CLEMENT if (num != hwbm_pool->size) { 1122dc35a10fSMarcin Wojtas WARN(1, "pool %d: %d of %d allocated\n", 1123baa11ebcSGregory CLEMENT bm_pool->id, num, hwbm_pool->size); 1124dc35a10fSMarcin Wojtas goto bm_mtu_err; 1125dc35a10fSMarcin Wojtas } 1126dc35a10fSMarcin Wojtas mvneta_bm_pool_bufsize_set(pp, bm_pool->buf_size, bm_pool->id); 1127dc35a10fSMarcin Wojtas 1128dc35a10fSMarcin Wojtas return; 1129dc35a10fSMarcin Wojtas 1130dc35a10fSMarcin Wojtas bm_mtu_err: 1131dc35a10fSMarcin Wojtas mvneta_bm_pool_destroy(pp->bm_priv, pp->pool_long, 1 << pp->id); 1132dc35a10fSMarcin Wojtas mvneta_bm_pool_destroy(pp->bm_priv, pp->pool_short, 1 << pp->id); 1133dc35a10fSMarcin Wojtas 1134dc35a10fSMarcin Wojtas pp->bm_priv = NULL; 1135dc35a10fSMarcin Wojtas mvreg_write(pp, MVNETA_ACC_MODE, MVNETA_ACC_MODE_EXT1); 1136dc35a10fSMarcin Wojtas netdev_info(pp->dev, "fail to update MTU, fall back to software BM\n"); 1137dc35a10fSMarcin Wojtas } 1138dc35a10fSMarcin Wojtas 1139c5aff182SThomas Petazzoni /* Start the Ethernet port RX and TX activity */ 1140c5aff182SThomas Petazzoni static void mvneta_port_up(struct mvneta_port *pp) 1141c5aff182SThomas Petazzoni { 1142c5aff182SThomas Petazzoni int queue; 1143c5aff182SThomas Petazzoni u32 q_map; 1144c5aff182SThomas Petazzoni 1145c5aff182SThomas Petazzoni /* Enable all initialized TXs. */ 1146c5aff182SThomas Petazzoni q_map = 0; 1147c5aff182SThomas Petazzoni for (queue = 0; queue < txq_number; queue++) { 1148c5aff182SThomas Petazzoni struct mvneta_tx_queue *txq = &pp->txqs[queue]; 1149f95936ccSMarkus Elfring if (txq->descs) 1150c5aff182SThomas Petazzoni q_map |= (1 << queue); 1151c5aff182SThomas Petazzoni } 1152c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_TXQ_CMD, q_map); 1153c5aff182SThomas Petazzoni 1154e81b5e01SYelena Krivosheev q_map = 0; 1155c5aff182SThomas Petazzoni /* Enable all initialized RXQs. */ 11562dcf75e2SGregory CLEMENT for (queue = 0; queue < rxq_number; queue++) { 11572dcf75e2SGregory CLEMENT struct mvneta_rx_queue *rxq = &pp->rxqs[queue]; 11582dcf75e2SGregory CLEMENT 1159f95936ccSMarkus Elfring if (rxq->descs) 11602dcf75e2SGregory CLEMENT q_map |= (1 << queue); 11612dcf75e2SGregory CLEMENT } 11622dcf75e2SGregory CLEMENT mvreg_write(pp, MVNETA_RXQ_CMD, q_map); 1163c5aff182SThomas Petazzoni } 1164c5aff182SThomas Petazzoni 1165c5aff182SThomas Petazzoni /* Stop the Ethernet port activity */ 1166c5aff182SThomas Petazzoni static void mvneta_port_down(struct mvneta_port *pp) 1167c5aff182SThomas Petazzoni { 1168c5aff182SThomas Petazzoni u32 val; 1169c5aff182SThomas Petazzoni int count; 1170c5aff182SThomas Petazzoni 1171c5aff182SThomas Petazzoni /* Stop Rx port activity. Check port Rx activity. */ 1172c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_RXQ_CMD) & MVNETA_RXQ_ENABLE_MASK; 1173c5aff182SThomas Petazzoni 1174c5aff182SThomas Petazzoni /* Issue stop command for active channels only */ 1175c5aff182SThomas Petazzoni if (val != 0) 1176c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_RXQ_CMD, 1177c5aff182SThomas Petazzoni val << MVNETA_RXQ_DISABLE_SHIFT); 1178c5aff182SThomas Petazzoni 1179c5aff182SThomas Petazzoni /* Wait for all Rx activity to terminate. */ 1180c5aff182SThomas Petazzoni count = 0; 1181c5aff182SThomas Petazzoni do { 1182c5aff182SThomas Petazzoni if (count++ >= MVNETA_RX_DISABLE_TIMEOUT_MSEC) { 1183c5aff182SThomas Petazzoni netdev_warn(pp->dev, 11840838abb3SDmitri Epshtein "TIMEOUT for RX stopped ! rx_queue_cmd: 0x%08x\n", 1185c5aff182SThomas Petazzoni val); 1186c5aff182SThomas Petazzoni break; 1187c5aff182SThomas Petazzoni } 1188c5aff182SThomas Petazzoni mdelay(1); 1189c5aff182SThomas Petazzoni 1190c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_RXQ_CMD); 1191a3703fb3SDmitri Epshtein } while (val & MVNETA_RXQ_ENABLE_MASK); 1192c5aff182SThomas Petazzoni 1193c5aff182SThomas Petazzoni /* Stop Tx port activity. Check port Tx activity. Issue stop 11946a20c175SThomas Petazzoni * command for active channels only 11956a20c175SThomas Petazzoni */ 1196c5aff182SThomas Petazzoni val = (mvreg_read(pp, MVNETA_TXQ_CMD)) & MVNETA_TXQ_ENABLE_MASK; 1197c5aff182SThomas Petazzoni 1198c5aff182SThomas Petazzoni if (val != 0) 1199c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_TXQ_CMD, 1200c5aff182SThomas Petazzoni (val << MVNETA_TXQ_DISABLE_SHIFT)); 1201c5aff182SThomas Petazzoni 1202c5aff182SThomas Petazzoni /* Wait for all Tx activity to terminate. */ 1203c5aff182SThomas Petazzoni count = 0; 1204c5aff182SThomas Petazzoni do { 1205c5aff182SThomas Petazzoni if (count++ >= MVNETA_TX_DISABLE_TIMEOUT_MSEC) { 1206c5aff182SThomas Petazzoni netdev_warn(pp->dev, 1207c5aff182SThomas Petazzoni "TIMEOUT for TX stopped status=0x%08x\n", 1208c5aff182SThomas Petazzoni val); 1209c5aff182SThomas Petazzoni break; 1210c5aff182SThomas Petazzoni } 1211c5aff182SThomas Petazzoni mdelay(1); 1212c5aff182SThomas Petazzoni 1213c5aff182SThomas Petazzoni /* Check TX Command reg that all Txqs are stopped */ 1214c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_TXQ_CMD); 1215c5aff182SThomas Petazzoni 1216a3703fb3SDmitri Epshtein } while (val & MVNETA_TXQ_ENABLE_MASK); 1217c5aff182SThomas Petazzoni 1218c5aff182SThomas Petazzoni /* Double check to verify that TX FIFO is empty */ 1219c5aff182SThomas Petazzoni count = 0; 1220c5aff182SThomas Petazzoni do { 1221c5aff182SThomas Petazzoni if (count++ >= MVNETA_TX_FIFO_EMPTY_TIMEOUT) { 1222c5aff182SThomas Petazzoni netdev_warn(pp->dev, 12230838abb3SDmitri Epshtein "TX FIFO empty timeout status=0x%08x\n", 1224c5aff182SThomas Petazzoni val); 1225c5aff182SThomas Petazzoni break; 1226c5aff182SThomas Petazzoni } 1227c5aff182SThomas Petazzoni mdelay(1); 1228c5aff182SThomas Petazzoni 1229c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_PORT_STATUS); 1230c5aff182SThomas Petazzoni } while (!(val & MVNETA_TX_FIFO_EMPTY) && 1231c5aff182SThomas Petazzoni (val & MVNETA_TX_IN_PRGRS)); 1232c5aff182SThomas Petazzoni 1233c5aff182SThomas Petazzoni udelay(200); 1234c5aff182SThomas Petazzoni } 1235c5aff182SThomas Petazzoni 1236c5aff182SThomas Petazzoni /* Enable the port by setting the port enable bit of the MAC control register */ 1237c5aff182SThomas Petazzoni static void mvneta_port_enable(struct mvneta_port *pp) 1238c5aff182SThomas Petazzoni { 1239c5aff182SThomas Petazzoni u32 val; 1240c5aff182SThomas Petazzoni 1241c5aff182SThomas Petazzoni /* Enable port */ 1242c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_GMAC_CTRL_0); 1243c5aff182SThomas Petazzoni val |= MVNETA_GMAC0_PORT_ENABLE; 1244c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_GMAC_CTRL_0, val); 1245c5aff182SThomas Petazzoni } 1246c5aff182SThomas Petazzoni 1247c5aff182SThomas Petazzoni /* Disable the port and wait for about 200 usec before retuning */ 1248c5aff182SThomas Petazzoni static void mvneta_port_disable(struct mvneta_port *pp) 1249c5aff182SThomas Petazzoni { 1250c5aff182SThomas Petazzoni u32 val; 1251c5aff182SThomas Petazzoni 1252c5aff182SThomas Petazzoni /* Reset the Enable bit in the Serial Control Register */ 1253c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_GMAC_CTRL_0); 1254c5aff182SThomas Petazzoni val &= ~MVNETA_GMAC0_PORT_ENABLE; 1255c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_GMAC_CTRL_0, val); 1256c5aff182SThomas Petazzoni 1257c5aff182SThomas Petazzoni udelay(200); 1258c5aff182SThomas Petazzoni } 1259c5aff182SThomas Petazzoni 1260c5aff182SThomas Petazzoni /* Multicast tables methods */ 1261c5aff182SThomas Petazzoni 1262c5aff182SThomas Petazzoni /* Set all entries in Unicast MAC Table; queue==-1 means reject all */ 1263c5aff182SThomas Petazzoni static void mvneta_set_ucast_table(struct mvneta_port *pp, int queue) 1264c5aff182SThomas Petazzoni { 1265c5aff182SThomas Petazzoni int offset; 1266c5aff182SThomas Petazzoni u32 val; 1267c5aff182SThomas Petazzoni 1268c5aff182SThomas Petazzoni if (queue == -1) { 1269c5aff182SThomas Petazzoni val = 0; 1270c5aff182SThomas Petazzoni } else { 1271c5aff182SThomas Petazzoni val = 0x1 | (queue << 1); 1272c5aff182SThomas Petazzoni val |= (val << 24) | (val << 16) | (val << 8); 1273c5aff182SThomas Petazzoni } 1274c5aff182SThomas Petazzoni 1275c5aff182SThomas Petazzoni for (offset = 0; offset <= 0xc; offset += 4) 1276c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_DA_FILT_UCAST_BASE + offset, val); 1277c5aff182SThomas Petazzoni } 1278c5aff182SThomas Petazzoni 1279c5aff182SThomas Petazzoni /* Set all entries in Special Multicast MAC Table; queue==-1 means reject all */ 1280c5aff182SThomas Petazzoni static void mvneta_set_special_mcast_table(struct mvneta_port *pp, int queue) 1281c5aff182SThomas Petazzoni { 1282c5aff182SThomas Petazzoni int offset; 1283c5aff182SThomas Petazzoni u32 val; 1284c5aff182SThomas Petazzoni 1285c5aff182SThomas Petazzoni if (queue == -1) { 1286c5aff182SThomas Petazzoni val = 0; 1287c5aff182SThomas Petazzoni } else { 1288c5aff182SThomas Petazzoni val = 0x1 | (queue << 1); 1289c5aff182SThomas Petazzoni val |= (val << 24) | (val << 16) | (val << 8); 1290c5aff182SThomas Petazzoni } 1291c5aff182SThomas Petazzoni 1292c5aff182SThomas Petazzoni for (offset = 0; offset <= 0xfc; offset += 4) 1293c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_DA_FILT_SPEC_MCAST + offset, val); 1294c5aff182SThomas Petazzoni 1295c5aff182SThomas Petazzoni } 1296c5aff182SThomas Petazzoni 1297c5aff182SThomas Petazzoni /* Set all entries in Other Multicast MAC Table. queue==-1 means reject all */ 1298c5aff182SThomas Petazzoni static void mvneta_set_other_mcast_table(struct mvneta_port *pp, int queue) 1299c5aff182SThomas Petazzoni { 1300c5aff182SThomas Petazzoni int offset; 1301c5aff182SThomas Petazzoni u32 val; 1302c5aff182SThomas Petazzoni 1303c5aff182SThomas Petazzoni if (queue == -1) { 1304c5aff182SThomas Petazzoni memset(pp->mcast_count, 0, sizeof(pp->mcast_count)); 1305c5aff182SThomas Petazzoni val = 0; 1306c5aff182SThomas Petazzoni } else { 1307c5aff182SThomas Petazzoni memset(pp->mcast_count, 1, sizeof(pp->mcast_count)); 1308c5aff182SThomas Petazzoni val = 0x1 | (queue << 1); 1309c5aff182SThomas Petazzoni val |= (val << 24) | (val << 16) | (val << 8); 1310c5aff182SThomas Petazzoni } 1311c5aff182SThomas Petazzoni 1312c5aff182SThomas Petazzoni for (offset = 0; offset <= 0xfc; offset += 4) 1313c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_DA_FILT_OTH_MCAST + offset, val); 1314c5aff182SThomas Petazzoni } 1315c5aff182SThomas Petazzoni 1316db488c10SGregory CLEMENT static void mvneta_percpu_unmask_interrupt(void *arg) 1317db488c10SGregory CLEMENT { 1318db488c10SGregory CLEMENT struct mvneta_port *pp = arg; 1319db488c10SGregory CLEMENT 1320db488c10SGregory CLEMENT /* All the queue are unmasked, but actually only the ones 1321db488c10SGregory CLEMENT * mapped to this CPU will be unmasked 1322db488c10SGregory CLEMENT */ 1323db488c10SGregory CLEMENT mvreg_write(pp, MVNETA_INTR_NEW_MASK, 1324db488c10SGregory CLEMENT MVNETA_RX_INTR_MASK_ALL | 1325db488c10SGregory CLEMENT MVNETA_TX_INTR_MASK_ALL | 1326db488c10SGregory CLEMENT MVNETA_MISCINTR_INTR_MASK); 1327db488c10SGregory CLEMENT } 1328db488c10SGregory CLEMENT 1329db488c10SGregory CLEMENT static void mvneta_percpu_mask_interrupt(void *arg) 1330db488c10SGregory CLEMENT { 1331db488c10SGregory CLEMENT struct mvneta_port *pp = arg; 1332db488c10SGregory CLEMENT 1333db488c10SGregory CLEMENT /* All the queue are masked, but actually only the ones 1334db488c10SGregory CLEMENT * mapped to this CPU will be masked 1335db488c10SGregory CLEMENT */ 1336db488c10SGregory CLEMENT mvreg_write(pp, MVNETA_INTR_NEW_MASK, 0); 1337db488c10SGregory CLEMENT mvreg_write(pp, MVNETA_INTR_OLD_MASK, 0); 1338db488c10SGregory CLEMENT mvreg_write(pp, MVNETA_INTR_MISC_MASK, 0); 1339db488c10SGregory CLEMENT } 1340db488c10SGregory CLEMENT 1341db488c10SGregory CLEMENT static void mvneta_percpu_clear_intr_cause(void *arg) 1342db488c10SGregory CLEMENT { 1343db488c10SGregory CLEMENT struct mvneta_port *pp = arg; 1344db488c10SGregory CLEMENT 1345db488c10SGregory CLEMENT /* All the queue are cleared, but actually only the ones 1346db488c10SGregory CLEMENT * mapped to this CPU will be cleared 1347db488c10SGregory CLEMENT */ 1348db488c10SGregory CLEMENT mvreg_write(pp, MVNETA_INTR_NEW_CAUSE, 0); 1349db488c10SGregory CLEMENT mvreg_write(pp, MVNETA_INTR_MISC_CAUSE, 0); 1350db488c10SGregory CLEMENT mvreg_write(pp, MVNETA_INTR_OLD_CAUSE, 0); 1351db488c10SGregory CLEMENT } 1352db488c10SGregory CLEMENT 1353c5aff182SThomas Petazzoni /* This method sets defaults to the NETA port: 1354c5aff182SThomas Petazzoni * Clears interrupt Cause and Mask registers. 1355c5aff182SThomas Petazzoni * Clears all MAC tables. 1356c5aff182SThomas Petazzoni * Sets defaults to all registers. 1357c5aff182SThomas Petazzoni * Resets RX and TX descriptor rings. 1358c5aff182SThomas Petazzoni * Resets PHY. 1359c5aff182SThomas Petazzoni * This method can be called after mvneta_port_down() to return the port 1360c5aff182SThomas Petazzoni * settings to defaults. 1361c5aff182SThomas Petazzoni */ 1362c5aff182SThomas Petazzoni static void mvneta_defaults_set(struct mvneta_port *pp) 1363c5aff182SThomas Petazzoni { 1364c5aff182SThomas Petazzoni int cpu; 1365c5aff182SThomas Petazzoni int queue; 1366c5aff182SThomas Petazzoni u32 val; 13672dcf75e2SGregory CLEMENT int max_cpu = num_present_cpus(); 1368c5aff182SThomas Petazzoni 1369c5aff182SThomas Petazzoni /* Clear all Cause registers */ 1370db488c10SGregory CLEMENT on_each_cpu(mvneta_percpu_clear_intr_cause, pp, true); 1371c5aff182SThomas Petazzoni 1372c5aff182SThomas Petazzoni /* Mask all interrupts */ 1373db488c10SGregory CLEMENT on_each_cpu(mvneta_percpu_mask_interrupt, pp, true); 1374c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_INTR_ENABLE, 0); 1375c5aff182SThomas Petazzoni 1376c5aff182SThomas Petazzoni /* Enable MBUS Retry bit16 */ 1377c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_MBUS_RETRY, 0x20); 1378c5aff182SThomas Petazzoni 137950bf8cb6SGregory CLEMENT /* Set CPU queue access map. CPUs are assigned to the RX and 138050bf8cb6SGregory CLEMENT * TX queues modulo their number. If there is only one TX 138150bf8cb6SGregory CLEMENT * queue then it is assigned to the CPU associated to the 138250bf8cb6SGregory CLEMENT * default RX queue. 13836a20c175SThomas Petazzoni */ 13842dcf75e2SGregory CLEMENT for_each_present_cpu(cpu) { 13852dcf75e2SGregory CLEMENT int rxq_map = 0, txq_map = 0; 138650bf8cb6SGregory CLEMENT int rxq, txq; 13872636ac3cSMarcin Wojtas if (!pp->neta_armada3700) { 13882dcf75e2SGregory CLEMENT for (rxq = 0; rxq < rxq_number; rxq++) 13892dcf75e2SGregory CLEMENT if ((rxq % max_cpu) == cpu) 13902dcf75e2SGregory CLEMENT rxq_map |= MVNETA_CPU_RXQ_ACCESS(rxq); 13912dcf75e2SGregory CLEMENT 139250bf8cb6SGregory CLEMENT for (txq = 0; txq < txq_number; txq++) 139350bf8cb6SGregory CLEMENT if ((txq % max_cpu) == cpu) 139450bf8cb6SGregory CLEMENT txq_map |= MVNETA_CPU_TXQ_ACCESS(txq); 139550bf8cb6SGregory CLEMENT 139650bf8cb6SGregory CLEMENT /* With only one TX queue we configure a special case 139750bf8cb6SGregory CLEMENT * which will allow to get all the irq on a single 139850bf8cb6SGregory CLEMENT * CPU 139950bf8cb6SGregory CLEMENT */ 140050bf8cb6SGregory CLEMENT if (txq_number == 1) 140150bf8cb6SGregory CLEMENT txq_map = (cpu == pp->rxq_def) ? 140250bf8cb6SGregory CLEMENT MVNETA_CPU_TXQ_ACCESS(1) : 0; 14032dcf75e2SGregory CLEMENT 14042636ac3cSMarcin Wojtas } else { 14052636ac3cSMarcin Wojtas txq_map = MVNETA_CPU_TXQ_ACCESS_ALL_MASK; 14062636ac3cSMarcin Wojtas rxq_map = MVNETA_CPU_RXQ_ACCESS_ALL_MASK; 14072636ac3cSMarcin Wojtas } 14082636ac3cSMarcin Wojtas 14092dcf75e2SGregory CLEMENT mvreg_write(pp, MVNETA_CPU_MAP(cpu), rxq_map | txq_map); 14102dcf75e2SGregory CLEMENT } 1411c5aff182SThomas Petazzoni 1412c5aff182SThomas Petazzoni /* Reset RX and TX DMAs */ 1413c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_PORT_RX_RESET, MVNETA_PORT_RX_DMA_RESET); 1414c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_PORT_TX_RESET, MVNETA_PORT_TX_DMA_RESET); 1415c5aff182SThomas Petazzoni 1416c5aff182SThomas Petazzoni /* Disable Legacy WRR, Disable EJP, Release from reset */ 1417c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_TXQ_CMD_1, 0); 1418c5aff182SThomas Petazzoni for (queue = 0; queue < txq_number; queue++) { 1419c5aff182SThomas Petazzoni mvreg_write(pp, MVETH_TXQ_TOKEN_COUNT_REG(queue), 0); 1420c5aff182SThomas Petazzoni mvreg_write(pp, MVETH_TXQ_TOKEN_CFG_REG(queue), 0); 1421c5aff182SThomas Petazzoni } 1422c5aff182SThomas Petazzoni 1423c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_PORT_TX_RESET, 0); 1424c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_PORT_RX_RESET, 0); 1425c5aff182SThomas Petazzoni 1426c5aff182SThomas Petazzoni /* Set Port Acceleration Mode */ 1427dc35a10fSMarcin Wojtas if (pp->bm_priv) 1428dc35a10fSMarcin Wojtas /* HW buffer management + legacy parser */ 1429dc35a10fSMarcin Wojtas val = MVNETA_ACC_MODE_EXT2; 1430dc35a10fSMarcin Wojtas else 1431dc35a10fSMarcin Wojtas /* SW buffer management + legacy parser */ 1432dc35a10fSMarcin Wojtas val = MVNETA_ACC_MODE_EXT1; 1433c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_ACC_MODE, val); 1434c5aff182SThomas Petazzoni 1435dc35a10fSMarcin Wojtas if (pp->bm_priv) 1436dc35a10fSMarcin Wojtas mvreg_write(pp, MVNETA_BM_ADDRESS, pp->bm_priv->bppi_phys_addr); 1437dc35a10fSMarcin Wojtas 1438c5aff182SThomas Petazzoni /* Update val of portCfg register accordingly with all RxQueue types */ 143990b74c01SGregory CLEMENT val = MVNETA_PORT_CONFIG_DEFL_VALUE(pp->rxq_def); 1440c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_PORT_CONFIG, val); 1441c5aff182SThomas Petazzoni 1442c5aff182SThomas Petazzoni val = 0; 1443c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_PORT_CONFIG_EXTEND, val); 1444c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_RX_MIN_FRAME_SIZE, 64); 1445c5aff182SThomas Petazzoni 1446c5aff182SThomas Petazzoni /* Build PORT_SDMA_CONFIG_REG */ 1447c5aff182SThomas Petazzoni val = 0; 1448c5aff182SThomas Petazzoni 1449c5aff182SThomas Petazzoni /* Default burst size */ 1450c5aff182SThomas Petazzoni val |= MVNETA_TX_BRST_SZ_MASK(MVNETA_SDMA_BRST_SIZE_16); 1451c5aff182SThomas Petazzoni val |= MVNETA_RX_BRST_SZ_MASK(MVNETA_SDMA_BRST_SIZE_16); 14529ad8fef6SThomas Petazzoni val |= MVNETA_RX_NO_DATA_SWAP | MVNETA_TX_NO_DATA_SWAP; 1453c5aff182SThomas Petazzoni 14549ad8fef6SThomas Petazzoni #if defined(__BIG_ENDIAN) 14559ad8fef6SThomas Petazzoni val |= MVNETA_DESC_SWAP; 14569ad8fef6SThomas Petazzoni #endif 1457c5aff182SThomas Petazzoni 1458c5aff182SThomas Petazzoni /* Assign port SDMA configuration */ 1459c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_SDMA_CONFIG, val); 1460c5aff182SThomas Petazzoni 146171408602SThomas Petazzoni /* Disable PHY polling in hardware, since we're using the 146271408602SThomas Petazzoni * kernel phylib to do this. 146371408602SThomas Petazzoni */ 146471408602SThomas Petazzoni val = mvreg_read(pp, MVNETA_UNIT_CONTROL); 146571408602SThomas Petazzoni val &= ~MVNETA_PHY_POLLING_ENABLE; 146671408602SThomas Petazzoni mvreg_write(pp, MVNETA_UNIT_CONTROL, val); 146771408602SThomas Petazzoni 1468c5aff182SThomas Petazzoni mvneta_set_ucast_table(pp, -1); 1469c5aff182SThomas Petazzoni mvneta_set_special_mcast_table(pp, -1); 1470c5aff182SThomas Petazzoni mvneta_set_other_mcast_table(pp, -1); 1471c5aff182SThomas Petazzoni 1472c5aff182SThomas Petazzoni /* Set port interrupt enable register - default enable all */ 1473c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_INTR_ENABLE, 1474c5aff182SThomas Petazzoni (MVNETA_RXQ_INTR_ENABLE_ALL_MASK 1475c5aff182SThomas Petazzoni | MVNETA_TXQ_INTR_ENABLE_ALL_MASK)); 1476e483911fSAndrew Lunn 1477e483911fSAndrew Lunn mvneta_mib_counters_clear(pp); 1478c5aff182SThomas Petazzoni } 1479c5aff182SThomas Petazzoni 1480c5aff182SThomas Petazzoni /* Set max sizes for tx queues */ 1481c5aff182SThomas Petazzoni static void mvneta_txq_max_tx_size_set(struct mvneta_port *pp, int max_tx_size) 1482c5aff182SThomas Petazzoni 1483c5aff182SThomas Petazzoni { 1484c5aff182SThomas Petazzoni u32 val, size, mtu; 1485c5aff182SThomas Petazzoni int queue; 1486c5aff182SThomas Petazzoni 1487c5aff182SThomas Petazzoni mtu = max_tx_size * 8; 1488c5aff182SThomas Petazzoni if (mtu > MVNETA_TX_MTU_MAX) 1489c5aff182SThomas Petazzoni mtu = MVNETA_TX_MTU_MAX; 1490c5aff182SThomas Petazzoni 1491c5aff182SThomas Petazzoni /* Set MTU */ 1492c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_TX_MTU); 1493c5aff182SThomas Petazzoni val &= ~MVNETA_TX_MTU_MAX; 1494c5aff182SThomas Petazzoni val |= mtu; 1495c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_TX_MTU, val); 1496c5aff182SThomas Petazzoni 1497c5aff182SThomas Petazzoni /* TX token size and all TXQs token size must be larger that MTU */ 1498c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_TX_TOKEN_SIZE); 1499c5aff182SThomas Petazzoni 1500c5aff182SThomas Petazzoni size = val & MVNETA_TX_TOKEN_SIZE_MAX; 1501c5aff182SThomas Petazzoni if (size < mtu) { 1502c5aff182SThomas Petazzoni size = mtu; 1503c5aff182SThomas Petazzoni val &= ~MVNETA_TX_TOKEN_SIZE_MAX; 1504c5aff182SThomas Petazzoni val |= size; 1505c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_TX_TOKEN_SIZE, val); 1506c5aff182SThomas Petazzoni } 1507c5aff182SThomas Petazzoni for (queue = 0; queue < txq_number; queue++) { 1508c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_TXQ_TOKEN_SIZE_REG(queue)); 1509c5aff182SThomas Petazzoni 1510c5aff182SThomas Petazzoni size = val & MVNETA_TXQ_TOKEN_SIZE_MAX; 1511c5aff182SThomas Petazzoni if (size < mtu) { 1512c5aff182SThomas Petazzoni size = mtu; 1513c5aff182SThomas Petazzoni val &= ~MVNETA_TXQ_TOKEN_SIZE_MAX; 1514c5aff182SThomas Petazzoni val |= size; 1515c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_TXQ_TOKEN_SIZE_REG(queue), val); 1516c5aff182SThomas Petazzoni } 1517c5aff182SThomas Petazzoni } 1518c5aff182SThomas Petazzoni } 1519c5aff182SThomas Petazzoni 1520c5aff182SThomas Petazzoni /* Set unicast address */ 1521c5aff182SThomas Petazzoni static void mvneta_set_ucast_addr(struct mvneta_port *pp, u8 last_nibble, 1522c5aff182SThomas Petazzoni int queue) 1523c5aff182SThomas Petazzoni { 1524c5aff182SThomas Petazzoni unsigned int unicast_reg; 1525c5aff182SThomas Petazzoni unsigned int tbl_offset; 1526c5aff182SThomas Petazzoni unsigned int reg_offset; 1527c5aff182SThomas Petazzoni 1528c5aff182SThomas Petazzoni /* Locate the Unicast table entry */ 1529c5aff182SThomas Petazzoni last_nibble = (0xf & last_nibble); 1530c5aff182SThomas Petazzoni 1531c5aff182SThomas Petazzoni /* offset from unicast tbl base */ 1532c5aff182SThomas Petazzoni tbl_offset = (last_nibble / 4) * 4; 1533c5aff182SThomas Petazzoni 1534c5aff182SThomas Petazzoni /* offset within the above reg */ 1535c5aff182SThomas Petazzoni reg_offset = last_nibble % 4; 1536c5aff182SThomas Petazzoni 1537c5aff182SThomas Petazzoni unicast_reg = mvreg_read(pp, (MVNETA_DA_FILT_UCAST_BASE + tbl_offset)); 1538c5aff182SThomas Petazzoni 1539c5aff182SThomas Petazzoni if (queue == -1) { 1540c5aff182SThomas Petazzoni /* Clear accepts frame bit at specified unicast DA tbl entry */ 1541c5aff182SThomas Petazzoni unicast_reg &= ~(0xff << (8 * reg_offset)); 1542c5aff182SThomas Petazzoni } else { 1543c5aff182SThomas Petazzoni unicast_reg &= ~(0xff << (8 * reg_offset)); 1544c5aff182SThomas Petazzoni unicast_reg |= ((0x01 | (queue << 1)) << (8 * reg_offset)); 1545c5aff182SThomas Petazzoni } 1546c5aff182SThomas Petazzoni 1547c5aff182SThomas Petazzoni mvreg_write(pp, (MVNETA_DA_FILT_UCAST_BASE + tbl_offset), unicast_reg); 1548c5aff182SThomas Petazzoni } 1549c5aff182SThomas Petazzoni 1550c5aff182SThomas Petazzoni /* Set mac address */ 1551c5aff182SThomas Petazzoni static void mvneta_mac_addr_set(struct mvneta_port *pp, unsigned char *addr, 1552c5aff182SThomas Petazzoni int queue) 1553c5aff182SThomas Petazzoni { 1554c5aff182SThomas Petazzoni unsigned int mac_h; 1555c5aff182SThomas Petazzoni unsigned int mac_l; 1556c5aff182SThomas Petazzoni 1557c5aff182SThomas Petazzoni if (queue != -1) { 1558c5aff182SThomas Petazzoni mac_l = (addr[4] << 8) | (addr[5]); 1559c5aff182SThomas Petazzoni mac_h = (addr[0] << 24) | (addr[1] << 16) | 1560c5aff182SThomas Petazzoni (addr[2] << 8) | (addr[3] << 0); 1561c5aff182SThomas Petazzoni 1562c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_MAC_ADDR_LOW, mac_l); 1563c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_MAC_ADDR_HIGH, mac_h); 1564c5aff182SThomas Petazzoni } 1565c5aff182SThomas Petazzoni 1566c5aff182SThomas Petazzoni /* Accept frames of this address */ 1567c5aff182SThomas Petazzoni mvneta_set_ucast_addr(pp, addr[5], queue); 1568c5aff182SThomas Petazzoni } 1569c5aff182SThomas Petazzoni 15706a20c175SThomas Petazzoni /* Set the number of packets that will be received before RX interrupt 15716a20c175SThomas Petazzoni * will be generated by HW. 1572c5aff182SThomas Petazzoni */ 1573c5aff182SThomas Petazzoni static void mvneta_rx_pkts_coal_set(struct mvneta_port *pp, 1574c5aff182SThomas Petazzoni struct mvneta_rx_queue *rxq, u32 value) 1575c5aff182SThomas Petazzoni { 1576c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_RXQ_THRESHOLD_REG(rxq->id), 1577c5aff182SThomas Petazzoni value | MVNETA_RXQ_NON_OCCUPIED(0)); 1578c5aff182SThomas Petazzoni } 1579c5aff182SThomas Petazzoni 15806a20c175SThomas Petazzoni /* Set the time delay in usec before RX interrupt will be generated by 15816a20c175SThomas Petazzoni * HW. 1582c5aff182SThomas Petazzoni */ 1583c5aff182SThomas Petazzoni static void mvneta_rx_time_coal_set(struct mvneta_port *pp, 1584c5aff182SThomas Petazzoni struct mvneta_rx_queue *rxq, u32 value) 1585c5aff182SThomas Petazzoni { 1586189dd626SThomas Petazzoni u32 val; 1587189dd626SThomas Petazzoni unsigned long clk_rate; 1588189dd626SThomas Petazzoni 1589189dd626SThomas Petazzoni clk_rate = clk_get_rate(pp->clk); 1590189dd626SThomas Petazzoni val = (clk_rate / 1000000) * value; 1591c5aff182SThomas Petazzoni 1592c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_RXQ_TIME_COAL_REG(rxq->id), val); 1593c5aff182SThomas Petazzoni } 1594c5aff182SThomas Petazzoni 1595c5aff182SThomas Petazzoni /* Set threshold for TX_DONE pkts coalescing */ 1596c5aff182SThomas Petazzoni static void mvneta_tx_done_pkts_coal_set(struct mvneta_port *pp, 1597c5aff182SThomas Petazzoni struct mvneta_tx_queue *txq, u32 value) 1598c5aff182SThomas Petazzoni { 1599c5aff182SThomas Petazzoni u32 val; 1600c5aff182SThomas Petazzoni 1601c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_TXQ_SIZE_REG(txq->id)); 1602c5aff182SThomas Petazzoni 1603c5aff182SThomas Petazzoni val &= ~MVNETA_TXQ_SENT_THRESH_ALL_MASK; 1604c5aff182SThomas Petazzoni val |= MVNETA_TXQ_SENT_THRESH_MASK(value); 1605c5aff182SThomas Petazzoni 1606c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_TXQ_SIZE_REG(txq->id), val); 1607c5aff182SThomas Petazzoni } 1608c5aff182SThomas Petazzoni 1609c5aff182SThomas Petazzoni /* Handle rx descriptor fill by setting buf_cookie and buf_phys_addr */ 1610c5aff182SThomas Petazzoni static void mvneta_rx_desc_fill(struct mvneta_rx_desc *rx_desc, 1611f88bee1cSGregory CLEMENT u32 phys_addr, void *virt_addr, 1612f88bee1cSGregory CLEMENT struct mvneta_rx_queue *rxq) 1613c5aff182SThomas Petazzoni { 1614f88bee1cSGregory CLEMENT int i; 1615f88bee1cSGregory CLEMENT 1616c5aff182SThomas Petazzoni rx_desc->buf_phys_addr = phys_addr; 1617f88bee1cSGregory CLEMENT i = rx_desc - rxq->descs; 1618f88bee1cSGregory CLEMENT rxq->buf_virt_addr[i] = virt_addr; 1619c5aff182SThomas Petazzoni } 1620c5aff182SThomas Petazzoni 1621c5aff182SThomas Petazzoni /* Decrement sent descriptors counter */ 1622c5aff182SThomas Petazzoni static void mvneta_txq_sent_desc_dec(struct mvneta_port *pp, 1623c5aff182SThomas Petazzoni struct mvneta_tx_queue *txq, 1624c5aff182SThomas Petazzoni int sent_desc) 1625c5aff182SThomas Petazzoni { 1626c5aff182SThomas Petazzoni u32 val; 1627c5aff182SThomas Petazzoni 1628c5aff182SThomas Petazzoni /* Only 255 TX descriptors can be updated at once */ 1629c5aff182SThomas Petazzoni while (sent_desc > 0xff) { 1630c5aff182SThomas Petazzoni val = 0xff << MVNETA_TXQ_DEC_SENT_SHIFT; 1631c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val); 1632c5aff182SThomas Petazzoni sent_desc = sent_desc - 0xff; 1633c5aff182SThomas Petazzoni } 1634c5aff182SThomas Petazzoni 1635c5aff182SThomas Petazzoni val = sent_desc << MVNETA_TXQ_DEC_SENT_SHIFT; 1636c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val); 1637c5aff182SThomas Petazzoni } 1638c5aff182SThomas Petazzoni 1639c5aff182SThomas Petazzoni /* Get number of TX descriptors already sent by HW */ 1640c5aff182SThomas Petazzoni static int mvneta_txq_sent_desc_num_get(struct mvneta_port *pp, 1641c5aff182SThomas Petazzoni struct mvneta_tx_queue *txq) 1642c5aff182SThomas Petazzoni { 1643c5aff182SThomas Petazzoni u32 val; 1644c5aff182SThomas Petazzoni int sent_desc; 1645c5aff182SThomas Petazzoni 1646c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_TXQ_STATUS_REG(txq->id)); 1647c5aff182SThomas Petazzoni sent_desc = (val & MVNETA_TXQ_SENT_DESC_MASK) >> 1648c5aff182SThomas Petazzoni MVNETA_TXQ_SENT_DESC_SHIFT; 1649c5aff182SThomas Petazzoni 1650c5aff182SThomas Petazzoni return sent_desc; 1651c5aff182SThomas Petazzoni } 1652c5aff182SThomas Petazzoni 16536a20c175SThomas Petazzoni /* Get number of sent descriptors and decrement counter. 1654c5aff182SThomas Petazzoni * The number of sent descriptors is returned. 1655c5aff182SThomas Petazzoni */ 1656c5aff182SThomas Petazzoni static int mvneta_txq_sent_desc_proc(struct mvneta_port *pp, 1657c5aff182SThomas Petazzoni struct mvneta_tx_queue *txq) 1658c5aff182SThomas Petazzoni { 1659c5aff182SThomas Petazzoni int sent_desc; 1660c5aff182SThomas Petazzoni 1661c5aff182SThomas Petazzoni /* Get number of sent descriptors */ 1662c5aff182SThomas Petazzoni sent_desc = mvneta_txq_sent_desc_num_get(pp, txq); 1663c5aff182SThomas Petazzoni 1664c5aff182SThomas Petazzoni /* Decrement sent descriptors counter */ 1665c5aff182SThomas Petazzoni if (sent_desc) 1666c5aff182SThomas Petazzoni mvneta_txq_sent_desc_dec(pp, txq, sent_desc); 1667c5aff182SThomas Petazzoni 1668c5aff182SThomas Petazzoni return sent_desc; 1669c5aff182SThomas Petazzoni } 1670c5aff182SThomas Petazzoni 1671c5aff182SThomas Petazzoni /* Set TXQ descriptors fields relevant for CSUM calculation */ 1672c5aff182SThomas Petazzoni static u32 mvneta_txq_desc_csum(int l3_offs, int l3_proto, 1673c5aff182SThomas Petazzoni int ip_hdr_len, int l4_proto) 1674c5aff182SThomas Petazzoni { 1675c5aff182SThomas Petazzoni u32 command; 1676c5aff182SThomas Petazzoni 1677c5aff182SThomas Petazzoni /* Fields: L3_offset, IP_hdrlen, L3_type, G_IPv4_chk, 16786a20c175SThomas Petazzoni * G_L4_chk, L4_type; required only for checksum 16796a20c175SThomas Petazzoni * calculation 16806a20c175SThomas Petazzoni */ 1681c5aff182SThomas Petazzoni command = l3_offs << MVNETA_TX_L3_OFF_SHIFT; 1682c5aff182SThomas Petazzoni command |= ip_hdr_len << MVNETA_TX_IP_HLEN_SHIFT; 1683c5aff182SThomas Petazzoni 16840a198587SThomas Fitzsimmons if (l3_proto == htons(ETH_P_IP)) 1685c5aff182SThomas Petazzoni command |= MVNETA_TXD_IP_CSUM; 1686c5aff182SThomas Petazzoni else 1687c5aff182SThomas Petazzoni command |= MVNETA_TX_L3_IP6; 1688c5aff182SThomas Petazzoni 1689c5aff182SThomas Petazzoni if (l4_proto == IPPROTO_TCP) 1690c5aff182SThomas Petazzoni command |= MVNETA_TX_L4_CSUM_FULL; 1691c5aff182SThomas Petazzoni else if (l4_proto == IPPROTO_UDP) 1692c5aff182SThomas Petazzoni command |= MVNETA_TX_L4_UDP | MVNETA_TX_L4_CSUM_FULL; 1693c5aff182SThomas Petazzoni else 1694c5aff182SThomas Petazzoni command |= MVNETA_TX_L4_CSUM_NOT; 1695c5aff182SThomas Petazzoni 1696c5aff182SThomas Petazzoni return command; 1697c5aff182SThomas Petazzoni } 1698c5aff182SThomas Petazzoni 1699c5aff182SThomas Petazzoni 1700c5aff182SThomas Petazzoni /* Display more error info */ 1701c5aff182SThomas Petazzoni static void mvneta_rx_error(struct mvneta_port *pp, 1702c5aff182SThomas Petazzoni struct mvneta_rx_desc *rx_desc) 1703c5aff182SThomas Petazzoni { 1704c5aff182SThomas Petazzoni u32 status = rx_desc->status; 1705c5aff182SThomas Petazzoni 1706c5aff182SThomas Petazzoni switch (status & MVNETA_RXD_ERR_CODE_MASK) { 1707c5aff182SThomas Petazzoni case MVNETA_RXD_ERR_CRC: 1708c5aff182SThomas Petazzoni netdev_err(pp->dev, "bad rx status %08x (crc error), size=%d\n", 1709c5aff182SThomas Petazzoni status, rx_desc->data_size); 1710c5aff182SThomas Petazzoni break; 1711c5aff182SThomas Petazzoni case MVNETA_RXD_ERR_OVERRUN: 1712c5aff182SThomas Petazzoni netdev_err(pp->dev, "bad rx status %08x (overrun error), size=%d\n", 1713c5aff182SThomas Petazzoni status, rx_desc->data_size); 1714c5aff182SThomas Petazzoni break; 1715c5aff182SThomas Petazzoni case MVNETA_RXD_ERR_LEN: 1716c5aff182SThomas Petazzoni netdev_err(pp->dev, "bad rx status %08x (max frame length error), size=%d\n", 1717c5aff182SThomas Petazzoni status, rx_desc->data_size); 1718c5aff182SThomas Petazzoni break; 1719c5aff182SThomas Petazzoni case MVNETA_RXD_ERR_RESOURCE: 1720c5aff182SThomas Petazzoni netdev_err(pp->dev, "bad rx status %08x (resource error), size=%d\n", 1721c5aff182SThomas Petazzoni status, rx_desc->data_size); 1722c5aff182SThomas Petazzoni break; 1723c5aff182SThomas Petazzoni } 1724c5aff182SThomas Petazzoni } 1725c5aff182SThomas Petazzoni 17265428213cSwilly tarreau /* Handle RX checksum offload based on the descriptor's status */ 17275428213cSwilly tarreau static void mvneta_rx_csum(struct mvneta_port *pp, u32 status, 1728c5aff182SThomas Petazzoni struct sk_buff *skb) 1729c5aff182SThomas Petazzoni { 1730f945cec8SYelena Krivosheev if ((pp->dev->features & NETIF_F_RXCSUM) && 1731f945cec8SYelena Krivosheev (status & MVNETA_RXD_L3_IP4) && 17325428213cSwilly tarreau (status & MVNETA_RXD_L4_CSUM_OK)) { 1733c5aff182SThomas Petazzoni skb->csum = 0; 1734c5aff182SThomas Petazzoni skb->ip_summed = CHECKSUM_UNNECESSARY; 1735c5aff182SThomas Petazzoni return; 1736c5aff182SThomas Petazzoni } 1737c5aff182SThomas Petazzoni 1738c5aff182SThomas Petazzoni skb->ip_summed = CHECKSUM_NONE; 1739c5aff182SThomas Petazzoni } 1740c5aff182SThomas Petazzoni 17416c498974Swilly tarreau /* Return tx queue pointer (find last set bit) according to <cause> returned 17426c498974Swilly tarreau * form tx_done reg. <cause> must not be null. The return value is always a 17436c498974Swilly tarreau * valid queue for matching the first one found in <cause>. 17446c498974Swilly tarreau */ 1745c5aff182SThomas Petazzoni static struct mvneta_tx_queue *mvneta_tx_done_policy(struct mvneta_port *pp, 1746c5aff182SThomas Petazzoni u32 cause) 1747c5aff182SThomas Petazzoni { 1748c5aff182SThomas Petazzoni int queue = fls(cause) - 1; 1749c5aff182SThomas Petazzoni 17506c498974Swilly tarreau return &pp->txqs[queue]; 1751c5aff182SThomas Petazzoni } 1752c5aff182SThomas Petazzoni 1753c5aff182SThomas Petazzoni /* Free tx queue skbuffs */ 1754c5aff182SThomas Petazzoni static void mvneta_txq_bufs_free(struct mvneta_port *pp, 1755a29b6235SMarcin Wojtas struct mvneta_tx_queue *txq, int num, 1756a29b6235SMarcin Wojtas struct netdev_queue *nq) 1757c5aff182SThomas Petazzoni { 1758a29b6235SMarcin Wojtas unsigned int bytes_compl = 0, pkts_compl = 0; 1759c5aff182SThomas Petazzoni int i; 1760c5aff182SThomas Petazzoni 1761c5aff182SThomas Petazzoni for (i = 0; i < num; i++) { 1762c5aff182SThomas Petazzoni struct mvneta_tx_desc *tx_desc = txq->descs + 1763c5aff182SThomas Petazzoni txq->txq_get_index; 1764c5aff182SThomas Petazzoni struct sk_buff *skb = txq->tx_skb[txq->txq_get_index]; 1765c5aff182SThomas Petazzoni 1766a29b6235SMarcin Wojtas if (skb) { 1767a29b6235SMarcin Wojtas bytes_compl += skb->len; 1768a29b6235SMarcin Wojtas pkts_compl++; 1769a29b6235SMarcin Wojtas } 1770a29b6235SMarcin Wojtas 1771c5aff182SThomas Petazzoni mvneta_txq_inc_get(txq); 1772c5aff182SThomas Petazzoni 17732e3173a3SEzequiel Garcia if (!IS_TSO_HEADER(txq, tx_desc->buf_phys_addr)) 17742e3173a3SEzequiel Garcia dma_unmap_single(pp->dev->dev.parent, 17752e3173a3SEzequiel Garcia tx_desc->buf_phys_addr, 1776c5aff182SThomas Petazzoni tx_desc->data_size, DMA_TO_DEVICE); 1777ba7e46efSEzequiel Garcia if (!skb) 1778ba7e46efSEzequiel Garcia continue; 1779c5aff182SThomas Petazzoni dev_kfree_skb_any(skb); 1780c5aff182SThomas Petazzoni } 1781a29b6235SMarcin Wojtas 1782a29b6235SMarcin Wojtas netdev_tx_completed_queue(nq, pkts_compl, bytes_compl); 1783c5aff182SThomas Petazzoni } 1784c5aff182SThomas Petazzoni 1785c5aff182SThomas Petazzoni /* Handle end of transmission */ 1786cd713199SArnaud Ebalard static void mvneta_txq_done(struct mvneta_port *pp, 1787c5aff182SThomas Petazzoni struct mvneta_tx_queue *txq) 1788c5aff182SThomas Petazzoni { 1789c5aff182SThomas Petazzoni struct netdev_queue *nq = netdev_get_tx_queue(pp->dev, txq->id); 1790c5aff182SThomas Petazzoni int tx_done; 1791c5aff182SThomas Petazzoni 1792c5aff182SThomas Petazzoni tx_done = mvneta_txq_sent_desc_proc(pp, txq); 1793cd713199SArnaud Ebalard if (!tx_done) 1794cd713199SArnaud Ebalard return; 1795cd713199SArnaud Ebalard 1796a29b6235SMarcin Wojtas mvneta_txq_bufs_free(pp, txq, tx_done, nq); 1797c5aff182SThomas Petazzoni 1798c5aff182SThomas Petazzoni txq->count -= tx_done; 1799c5aff182SThomas Petazzoni 1800c5aff182SThomas Petazzoni if (netif_tx_queue_stopped(nq)) { 18018eef5f97SEzequiel Garcia if (txq->count <= txq->tx_wake_threshold) 1802c5aff182SThomas Petazzoni netif_tx_wake_queue(nq); 1803c5aff182SThomas Petazzoni } 1804c5aff182SThomas Petazzoni } 1805c5aff182SThomas Petazzoni 1806dc35a10fSMarcin Wojtas /* Refill processing for SW buffer management */ 18077e47fd84SGregory CLEMENT /* Allocate page per descriptor */ 1808c5aff182SThomas Petazzoni static int mvneta_rx_refill(struct mvneta_port *pp, 1809f88bee1cSGregory CLEMENT struct mvneta_rx_desc *rx_desc, 18107e47fd84SGregory CLEMENT struct mvneta_rx_queue *rxq, 18117e47fd84SGregory CLEMENT gfp_t gfp_mask) 1812c5aff182SThomas Petazzoni { 1813c5aff182SThomas Petazzoni dma_addr_t phys_addr; 18147e47fd84SGregory CLEMENT struct page *page; 1815c5aff182SThomas Petazzoni 18167e47fd84SGregory CLEMENT page = __dev_alloc_page(gfp_mask); 18177e47fd84SGregory CLEMENT if (!page) 1818c5aff182SThomas Petazzoni return -ENOMEM; 1819c5aff182SThomas Petazzoni 18207e47fd84SGregory CLEMENT /* map page for use */ 18217e47fd84SGregory CLEMENT phys_addr = dma_map_page(pp->dev->dev.parent, page, 0, PAGE_SIZE, 1822c5aff182SThomas Petazzoni DMA_FROM_DEVICE); 1823c5aff182SThomas Petazzoni if (unlikely(dma_mapping_error(pp->dev->dev.parent, phys_addr))) { 18247e47fd84SGregory CLEMENT __free_page(page); 1825c5aff182SThomas Petazzoni return -ENOMEM; 1826c5aff182SThomas Petazzoni } 1827c5aff182SThomas Petazzoni 18288d5047cfSMarcin Wojtas phys_addr += pp->rx_offset_correction; 18297e47fd84SGregory CLEMENT mvneta_rx_desc_fill(rx_desc, phys_addr, page, rxq); 1830c5aff182SThomas Petazzoni return 0; 1831c5aff182SThomas Petazzoni } 1832c5aff182SThomas Petazzoni 1833c5aff182SThomas Petazzoni /* Handle tx checksum */ 1834c5aff182SThomas Petazzoni static u32 mvneta_skb_tx_csum(struct mvneta_port *pp, struct sk_buff *skb) 1835c5aff182SThomas Petazzoni { 1836c5aff182SThomas Petazzoni if (skb->ip_summed == CHECKSUM_PARTIAL) { 1837c5aff182SThomas Petazzoni int ip_hdr_len = 0; 1838817dbfa5SVlad Yasevich __be16 l3_proto = vlan_get_protocol(skb); 1839c5aff182SThomas Petazzoni u8 l4_proto; 1840c5aff182SThomas Petazzoni 1841817dbfa5SVlad Yasevich if (l3_proto == htons(ETH_P_IP)) { 1842c5aff182SThomas Petazzoni struct iphdr *ip4h = ip_hdr(skb); 1843c5aff182SThomas Petazzoni 1844c5aff182SThomas Petazzoni /* Calculate IPv4 checksum and L4 checksum */ 1845c5aff182SThomas Petazzoni ip_hdr_len = ip4h->ihl; 1846c5aff182SThomas Petazzoni l4_proto = ip4h->protocol; 1847817dbfa5SVlad Yasevich } else if (l3_proto == htons(ETH_P_IPV6)) { 1848c5aff182SThomas Petazzoni struct ipv6hdr *ip6h = ipv6_hdr(skb); 1849c5aff182SThomas Petazzoni 1850c5aff182SThomas Petazzoni /* Read l4_protocol from one of IPv6 extra headers */ 1851c5aff182SThomas Petazzoni if (skb_network_header_len(skb) > 0) 1852c5aff182SThomas Petazzoni ip_hdr_len = (skb_network_header_len(skb) >> 2); 1853c5aff182SThomas Petazzoni l4_proto = ip6h->nexthdr; 1854c5aff182SThomas Petazzoni } else 1855c5aff182SThomas Petazzoni return MVNETA_TX_L4_CSUM_NOT; 1856c5aff182SThomas Petazzoni 1857c5aff182SThomas Petazzoni return mvneta_txq_desc_csum(skb_network_offset(skb), 1858817dbfa5SVlad Yasevich l3_proto, ip_hdr_len, l4_proto); 1859c5aff182SThomas Petazzoni } 1860c5aff182SThomas Petazzoni 1861c5aff182SThomas Petazzoni return MVNETA_TX_L4_CSUM_NOT; 1862c5aff182SThomas Petazzoni } 1863c5aff182SThomas Petazzoni 1864c5aff182SThomas Petazzoni /* Drop packets received by the RXQ and free buffers */ 1865c5aff182SThomas Petazzoni static void mvneta_rxq_drop_pkts(struct mvneta_port *pp, 1866c5aff182SThomas Petazzoni struct mvneta_rx_queue *rxq) 1867c5aff182SThomas Petazzoni { 1868c5aff182SThomas Petazzoni int rx_done, i; 1869c5aff182SThomas Petazzoni 1870c5aff182SThomas Petazzoni rx_done = mvneta_rxq_busy_desc_num_get(pp, rxq); 1871dc35a10fSMarcin Wojtas if (rx_done) 1872dc35a10fSMarcin Wojtas mvneta_rxq_desc_num_update(pp, rxq, rx_done, rx_done); 1873dc35a10fSMarcin Wojtas 1874dc35a10fSMarcin Wojtas if (pp->bm_priv) { 1875dc35a10fSMarcin Wojtas for (i = 0; i < rx_done; i++) { 1876dc35a10fSMarcin Wojtas struct mvneta_rx_desc *rx_desc = 1877dc35a10fSMarcin Wojtas mvneta_rxq_next_desc_get(rxq); 1878dc35a10fSMarcin Wojtas u8 pool_id = MVNETA_RX_GET_BM_POOL_ID(rx_desc); 1879dc35a10fSMarcin Wojtas struct mvneta_bm_pool *bm_pool; 1880dc35a10fSMarcin Wojtas 1881dc35a10fSMarcin Wojtas bm_pool = &pp->bm_priv->bm_pools[pool_id]; 1882dc35a10fSMarcin Wojtas /* Return dropped buffer to the pool */ 1883dc35a10fSMarcin Wojtas mvneta_bm_pool_put_bp(pp->bm_priv, bm_pool, 1884dc35a10fSMarcin Wojtas rx_desc->buf_phys_addr); 1885dc35a10fSMarcin Wojtas } 1886dc35a10fSMarcin Wojtas return; 1887dc35a10fSMarcin Wojtas } 1888dc35a10fSMarcin Wojtas 1889c5aff182SThomas Petazzoni for (i = 0; i < rxq->size; i++) { 1890c5aff182SThomas Petazzoni struct mvneta_rx_desc *rx_desc = rxq->descs + i; 1891f88bee1cSGregory CLEMENT void *data = rxq->buf_virt_addr[i]; 1892562e2f46SYelena Krivosheev if (!data || !(rx_desc->buf_phys_addr)) 1893562e2f46SYelena Krivosheev continue; 1894c5aff182SThomas Petazzoni 1895f4a51879SAntoine Tenart dma_unmap_page(pp->dev->dev.parent, rx_desc->buf_phys_addr, 1896f4a51879SAntoine Tenart PAGE_SIZE, DMA_FROM_DEVICE); 18977e47fd84SGregory CLEMENT __free_page(data); 1898dc35a10fSMarcin Wojtas } 1899c5aff182SThomas Petazzoni } 1900c5aff182SThomas Petazzoni 1901562e2f46SYelena Krivosheev static inline 1902562e2f46SYelena Krivosheev int mvneta_rx_refill_queue(struct mvneta_port *pp, struct mvneta_rx_queue *rxq) 1903562e2f46SYelena Krivosheev { 1904562e2f46SYelena Krivosheev struct mvneta_rx_desc *rx_desc; 1905562e2f46SYelena Krivosheev int curr_desc = rxq->first_to_refill; 1906562e2f46SYelena Krivosheev int i; 1907562e2f46SYelena Krivosheev 1908562e2f46SYelena Krivosheev for (i = 0; (i < rxq->refill_num) && (i < 64); i++) { 1909562e2f46SYelena Krivosheev rx_desc = rxq->descs + curr_desc; 1910562e2f46SYelena Krivosheev if (!(rx_desc->buf_phys_addr)) { 1911562e2f46SYelena Krivosheev if (mvneta_rx_refill(pp, rx_desc, rxq, GFP_ATOMIC)) { 1912562e2f46SYelena Krivosheev pr_err("Can't refill queue %d. Done %d from %d\n", 1913562e2f46SYelena Krivosheev rxq->id, i, rxq->refill_num); 1914562e2f46SYelena Krivosheev rxq->refill_err++; 1915562e2f46SYelena Krivosheev break; 1916562e2f46SYelena Krivosheev } 1917562e2f46SYelena Krivosheev } 1918562e2f46SYelena Krivosheev curr_desc = MVNETA_QUEUE_NEXT_DESC(rxq, curr_desc); 1919562e2f46SYelena Krivosheev } 1920562e2f46SYelena Krivosheev rxq->refill_num -= i; 1921562e2f46SYelena Krivosheev rxq->first_to_refill = curr_desc; 1922562e2f46SYelena Krivosheev 1923562e2f46SYelena Krivosheev return i; 1924562e2f46SYelena Krivosheev } 1925562e2f46SYelena Krivosheev 1926dc35a10fSMarcin Wojtas /* Main rx processing when using software buffer management */ 19277a86f05fSAndrew Lunn static int mvneta_rx_swbm(struct napi_struct *napi, 1928562e2f46SYelena Krivosheev struct mvneta_port *pp, int budget, 1929c5aff182SThomas Petazzoni struct mvneta_rx_queue *rxq) 1930c5aff182SThomas Petazzoni { 1931c5aff182SThomas Petazzoni struct net_device *dev = pp->dev; 1932562e2f46SYelena Krivosheev int rx_todo, rx_proc; 1933562e2f46SYelena Krivosheev int refill = 0; 1934dc4277ddSwilly tarreau u32 rcvd_pkts = 0; 1935dc4277ddSwilly tarreau u32 rcvd_bytes = 0; 1936c5aff182SThomas Petazzoni 1937c5aff182SThomas Petazzoni /* Get number of received packets */ 1938562e2f46SYelena Krivosheev rx_todo = mvneta_rxq_busy_desc_num_get(pp, rxq); 1939562e2f46SYelena Krivosheev rx_proc = 0; 1940c5aff182SThomas Petazzoni 1941c5aff182SThomas Petazzoni /* Fairness NAPI loop */ 1942562e2f46SYelena Krivosheev while ((rcvd_pkts < budget) && (rx_proc < rx_todo)) { 1943c5aff182SThomas Petazzoni struct mvneta_rx_desc *rx_desc = mvneta_rxq_next_desc_get(rxq); 19448ec2cd48Swilly tarreau unsigned char *data; 19457e47fd84SGregory CLEMENT struct page *page; 1946daf158d0SSimon Guinot dma_addr_t phys_addr; 1947562e2f46SYelena Krivosheev u32 rx_status, index; 1948562e2f46SYelena Krivosheev int rx_bytes, skb_size, copy_size; 1949562e2f46SYelena Krivosheev int frag_num, frag_size, frag_offset; 1950c5aff182SThomas Petazzoni 1951f88bee1cSGregory CLEMENT index = rx_desc - rxq->descs; 19527e47fd84SGregory CLEMENT page = (struct page *)rxq->buf_virt_addr[index]; 19537e47fd84SGregory CLEMENT data = page_address(page); 19547e47fd84SGregory CLEMENT /* Prefetch header */ 19557e47fd84SGregory CLEMENT prefetch(data); 1956c5aff182SThomas Petazzoni 1957562e2f46SYelena Krivosheev phys_addr = rx_desc->buf_phys_addr; 1958562e2f46SYelena Krivosheev rx_status = rx_desc->status; 1959562e2f46SYelena Krivosheev rx_proc++; 1960562e2f46SYelena Krivosheev rxq->refill_num++; 1961562e2f46SYelena Krivosheev 1962562e2f46SYelena Krivosheev if (rx_status & MVNETA_RXD_FIRST_DESC) { 1963562e2f46SYelena Krivosheev /* Check errors only for FIRST descriptor */ 1964562e2f46SYelena Krivosheev if (rx_status & MVNETA_RXD_ERR_SUMMARY) { 19652eecb2e0SYelena Krivosheev mvneta_rx_error(pp, rx_desc); 1966c5aff182SThomas Petazzoni dev->stats.rx_errors++; 19678ec2cd48Swilly tarreau /* leave the descriptor untouched */ 1968c5aff182SThomas Petazzoni continue; 1969c5aff182SThomas Petazzoni } 1970562e2f46SYelena Krivosheev rx_bytes = rx_desc->data_size - 1971562e2f46SYelena Krivosheev (ETH_FCS_LEN + MVNETA_MH_SIZE); 1972c5aff182SThomas Petazzoni 1973562e2f46SYelena Krivosheev /* Allocate small skb for each new packet */ 1974562e2f46SYelena Krivosheev skb_size = max(rx_copybreak, rx_header_size); 1975562e2f46SYelena Krivosheev rxq->skb = netdev_alloc_skb_ip_align(dev, skb_size); 1976562e2f46SYelena Krivosheev if (unlikely(!rxq->skb)) { 197717a96da6SGregory CLEMENT netdev_err(dev, 197817a96da6SGregory CLEMENT "Can't allocate skb on queue %d\n", 197917a96da6SGregory CLEMENT rxq->id); 1980562e2f46SYelena Krivosheev dev->stats.rx_dropped++; 198117a96da6SGregory CLEMENT rxq->skb_alloc_err++; 1982f19fadfcSwilly tarreau continue; 1983f19fadfcSwilly tarreau } 1984562e2f46SYelena Krivosheev copy_size = min(skb_size, rx_bytes); 1985f19fadfcSwilly tarreau 1986562e2f46SYelena Krivosheev /* Copy data from buffer to SKB, skip Marvell header */ 1987562e2f46SYelena Krivosheev memcpy(rxq->skb->data, data + MVNETA_MH_SIZE, 1988562e2f46SYelena Krivosheev copy_size); 1989562e2f46SYelena Krivosheev skb_put(rxq->skb, copy_size); 1990562e2f46SYelena Krivosheev rxq->left_size = rx_bytes - copy_size; 1991a84e3289SSimon Guinot 1992562e2f46SYelena Krivosheev mvneta_rx_csum(pp, rx_status, rxq->skb); 1993562e2f46SYelena Krivosheev if (rxq->left_size == 0) { 1994562e2f46SYelena Krivosheev int size = copy_size + MVNETA_MH_SIZE; 1995dc35a10fSMarcin Wojtas 1996562e2f46SYelena Krivosheev dma_sync_single_range_for_cpu(dev->dev.parent, 1997562e2f46SYelena Krivosheev phys_addr, 0, 1998562e2f46SYelena Krivosheev size, 1999dc35a10fSMarcin Wojtas DMA_FROM_DEVICE); 2000c5aff182SThomas Petazzoni 2001562e2f46SYelena Krivosheev /* leave the descriptor and buffer untouched */ 2002562e2f46SYelena Krivosheev } else { 2003562e2f46SYelena Krivosheev /* refill descriptor with new buffer later */ 2004562e2f46SYelena Krivosheev rx_desc->buf_phys_addr = 0; 200526c17a17SMarcin Wojtas 2006562e2f46SYelena Krivosheev frag_num = 0; 2007562e2f46SYelena Krivosheev frag_offset = copy_size + MVNETA_MH_SIZE; 2008562e2f46SYelena Krivosheev frag_size = min(rxq->left_size, 2009562e2f46SYelena Krivosheev (int)(PAGE_SIZE - frag_offset)); 2010562e2f46SYelena Krivosheev skb_add_rx_frag(rxq->skb, frag_num, page, 2011562e2f46SYelena Krivosheev frag_offset, frag_size, 2012562e2f46SYelena Krivosheev PAGE_SIZE); 2013cf5cca6eSAntoine Tenart dma_unmap_page(dev->dev.parent, phys_addr, 2014562e2f46SYelena Krivosheev PAGE_SIZE, DMA_FROM_DEVICE); 2015562e2f46SYelena Krivosheev rxq->left_size -= frag_size; 2016562e2f46SYelena Krivosheev } 2017562e2f46SYelena Krivosheev } else { 2018562e2f46SYelena Krivosheev /* Middle or Last descriptor */ 2019562e2f46SYelena Krivosheev if (unlikely(!rxq->skb)) { 2020562e2f46SYelena Krivosheev pr_debug("no skb for rx_status 0x%x\n", 2021562e2f46SYelena Krivosheev rx_status); 2022562e2f46SYelena Krivosheev continue; 2023562e2f46SYelena Krivosheev } 2024562e2f46SYelena Krivosheev if (!rxq->left_size) { 2025562e2f46SYelena Krivosheev /* last descriptor has only FCS */ 2026562e2f46SYelena Krivosheev /* and can be discarded */ 2027562e2f46SYelena Krivosheev dma_sync_single_range_for_cpu(dev->dev.parent, 2028562e2f46SYelena Krivosheev phys_addr, 0, 2029562e2f46SYelena Krivosheev ETH_FCS_LEN, 2030562e2f46SYelena Krivosheev DMA_FROM_DEVICE); 2031562e2f46SYelena Krivosheev /* leave the descriptor and buffer untouched */ 2032562e2f46SYelena Krivosheev } else { 2033562e2f46SYelena Krivosheev /* refill descriptor with new buffer later */ 2034562e2f46SYelena Krivosheev rx_desc->buf_phys_addr = 0; 2035562e2f46SYelena Krivosheev 2036562e2f46SYelena Krivosheev frag_num = skb_shinfo(rxq->skb)->nr_frags; 2037562e2f46SYelena Krivosheev frag_offset = 0; 2038562e2f46SYelena Krivosheev frag_size = min(rxq->left_size, 2039562e2f46SYelena Krivosheev (int)(PAGE_SIZE - frag_offset)); 2040562e2f46SYelena Krivosheev skb_add_rx_frag(rxq->skb, frag_num, page, 2041562e2f46SYelena Krivosheev frag_offset, frag_size, 2042562e2f46SYelena Krivosheev PAGE_SIZE); 2043562e2f46SYelena Krivosheev 2044f4a51879SAntoine Tenart dma_unmap_page(dev->dev.parent, phys_addr, 2045f4a51879SAntoine Tenart PAGE_SIZE, DMA_FROM_DEVICE); 2046562e2f46SYelena Krivosheev 2047562e2f46SYelena Krivosheev rxq->left_size -= frag_size; 2048562e2f46SYelena Krivosheev } 2049562e2f46SYelena Krivosheev } /* Middle or Last descriptor */ 2050562e2f46SYelena Krivosheev 2051562e2f46SYelena Krivosheev if (!(rx_status & MVNETA_RXD_LAST_DESC)) 2052562e2f46SYelena Krivosheev /* no last descriptor this time */ 2053562e2f46SYelena Krivosheev continue; 2054562e2f46SYelena Krivosheev 2055562e2f46SYelena Krivosheev if (rxq->left_size) { 2056562e2f46SYelena Krivosheev pr_err("get last desc, but left_size (%d) != 0\n", 2057562e2f46SYelena Krivosheev rxq->left_size); 2058562e2f46SYelena Krivosheev dev_kfree_skb_any(rxq->skb); 2059562e2f46SYelena Krivosheev rxq->left_size = 0; 2060562e2f46SYelena Krivosheev rxq->skb = NULL; 2061562e2f46SYelena Krivosheev continue; 2062562e2f46SYelena Krivosheev } 2063dc4277ddSwilly tarreau rcvd_pkts++; 2064562e2f46SYelena Krivosheev rcvd_bytes += rxq->skb->len; 2065c5aff182SThomas Petazzoni 2066c5aff182SThomas Petazzoni /* Linux processing */ 2067562e2f46SYelena Krivosheev rxq->skb->protocol = eth_type_trans(rxq->skb, dev); 2068c5aff182SThomas Petazzoni 2069562e2f46SYelena Krivosheev napi_gro_receive(napi, rxq->skb); 2070c5aff182SThomas Petazzoni 2071562e2f46SYelena Krivosheev /* clean uncomplete skb pointer in queue */ 2072562e2f46SYelena Krivosheev rxq->skb = NULL; 2073562e2f46SYelena Krivosheev rxq->left_size = 0; 2074c5aff182SThomas Petazzoni } 2075c5aff182SThomas Petazzoni 2076dc4277ddSwilly tarreau if (rcvd_pkts) { 207774c41b04Swilly tarreau struct mvneta_pcpu_stats *stats = this_cpu_ptr(pp->stats); 207874c41b04Swilly tarreau 207974c41b04Swilly tarreau u64_stats_update_begin(&stats->syncp); 208074c41b04Swilly tarreau stats->rx_packets += rcvd_pkts; 208174c41b04Swilly tarreau stats->rx_bytes += rcvd_bytes; 208274c41b04Swilly tarreau u64_stats_update_end(&stats->syncp); 2083dc4277ddSwilly tarreau } 2084dc4277ddSwilly tarreau 2085562e2f46SYelena Krivosheev /* return some buffers to hardware queue, one at a time is too slow */ 2086562e2f46SYelena Krivosheev refill = mvneta_rx_refill_queue(pp, rxq); 2087c5aff182SThomas Petazzoni 2088562e2f46SYelena Krivosheev /* Update rxq management counters */ 2089562e2f46SYelena Krivosheev mvneta_rxq_desc_num_update(pp, rxq, rx_proc, refill); 2090562e2f46SYelena Krivosheev 2091562e2f46SYelena Krivosheev return rcvd_pkts; 2092c5aff182SThomas Petazzoni } 2093c5aff182SThomas Petazzoni 2094dc35a10fSMarcin Wojtas /* Main rx processing when using hardware buffer management */ 20957a86f05fSAndrew Lunn static int mvneta_rx_hwbm(struct napi_struct *napi, 20967a86f05fSAndrew Lunn struct mvneta_port *pp, int rx_todo, 2097dc35a10fSMarcin Wojtas struct mvneta_rx_queue *rxq) 2098dc35a10fSMarcin Wojtas { 2099dc35a10fSMarcin Wojtas struct net_device *dev = pp->dev; 2100dc35a10fSMarcin Wojtas int rx_done; 2101dc35a10fSMarcin Wojtas u32 rcvd_pkts = 0; 2102dc35a10fSMarcin Wojtas u32 rcvd_bytes = 0; 2103dc35a10fSMarcin Wojtas 2104dc35a10fSMarcin Wojtas /* Get number of received packets */ 2105dc35a10fSMarcin Wojtas rx_done = mvneta_rxq_busy_desc_num_get(pp, rxq); 2106dc35a10fSMarcin Wojtas 2107dc35a10fSMarcin Wojtas if (rx_todo > rx_done) 2108dc35a10fSMarcin Wojtas rx_todo = rx_done; 2109dc35a10fSMarcin Wojtas 2110dc35a10fSMarcin Wojtas rx_done = 0; 2111dc35a10fSMarcin Wojtas 2112dc35a10fSMarcin Wojtas /* Fairness NAPI loop */ 2113dc35a10fSMarcin Wojtas while (rx_done < rx_todo) { 2114dc35a10fSMarcin Wojtas struct mvneta_rx_desc *rx_desc = mvneta_rxq_next_desc_get(rxq); 2115dc35a10fSMarcin Wojtas struct mvneta_bm_pool *bm_pool = NULL; 2116dc35a10fSMarcin Wojtas struct sk_buff *skb; 2117dc35a10fSMarcin Wojtas unsigned char *data; 2118dc35a10fSMarcin Wojtas dma_addr_t phys_addr; 2119dc35a10fSMarcin Wojtas u32 rx_status, frag_size; 2120dc35a10fSMarcin Wojtas int rx_bytes, err; 2121dc35a10fSMarcin Wojtas u8 pool_id; 2122dc35a10fSMarcin Wojtas 2123dc35a10fSMarcin Wojtas rx_done++; 2124dc35a10fSMarcin Wojtas rx_status = rx_desc->status; 2125dc35a10fSMarcin Wojtas rx_bytes = rx_desc->data_size - (ETH_FCS_LEN + MVNETA_MH_SIZE); 2126f88bee1cSGregory CLEMENT data = (u8 *)(uintptr_t)rx_desc->buf_cookie; 2127dc35a10fSMarcin Wojtas phys_addr = rx_desc->buf_phys_addr; 2128dc35a10fSMarcin Wojtas pool_id = MVNETA_RX_GET_BM_POOL_ID(rx_desc); 2129dc35a10fSMarcin Wojtas bm_pool = &pp->bm_priv->bm_pools[pool_id]; 2130dc35a10fSMarcin Wojtas 2131dc35a10fSMarcin Wojtas if (!mvneta_rxq_desc_is_first_last(rx_status) || 2132dc35a10fSMarcin Wojtas (rx_status & MVNETA_RXD_ERR_SUMMARY)) { 2133dc35a10fSMarcin Wojtas err_drop_frame_ret_pool: 2134dc35a10fSMarcin Wojtas /* Return the buffer to the pool */ 2135dc35a10fSMarcin Wojtas mvneta_bm_pool_put_bp(pp->bm_priv, bm_pool, 2136dc35a10fSMarcin Wojtas rx_desc->buf_phys_addr); 2137dc35a10fSMarcin Wojtas err_drop_frame: 2138dc35a10fSMarcin Wojtas dev->stats.rx_errors++; 2139dc35a10fSMarcin Wojtas mvneta_rx_error(pp, rx_desc); 2140dc35a10fSMarcin Wojtas /* leave the descriptor untouched */ 2141dc35a10fSMarcin Wojtas continue; 2142dc35a10fSMarcin Wojtas } 2143dc35a10fSMarcin Wojtas 2144dc35a10fSMarcin Wojtas if (rx_bytes <= rx_copybreak) { 2145dc35a10fSMarcin Wojtas /* better copy a small frame and not unmap the DMA region */ 2146dc35a10fSMarcin Wojtas skb = netdev_alloc_skb_ip_align(dev, rx_bytes); 2147dc35a10fSMarcin Wojtas if (unlikely(!skb)) 2148dc35a10fSMarcin Wojtas goto err_drop_frame_ret_pool; 2149dc35a10fSMarcin Wojtas 2150dc35a10fSMarcin Wojtas dma_sync_single_range_for_cpu(dev->dev.parent, 2151dc35a10fSMarcin Wojtas rx_desc->buf_phys_addr, 2152dc35a10fSMarcin Wojtas MVNETA_MH_SIZE + NET_SKB_PAD, 2153dc35a10fSMarcin Wojtas rx_bytes, 2154dc35a10fSMarcin Wojtas DMA_FROM_DEVICE); 215559ae1d12SJohannes Berg skb_put_data(skb, data + MVNETA_MH_SIZE + NET_SKB_PAD, 2156dc35a10fSMarcin Wojtas rx_bytes); 2157dc35a10fSMarcin Wojtas 2158dc35a10fSMarcin Wojtas skb->protocol = eth_type_trans(skb, dev); 2159dc35a10fSMarcin Wojtas mvneta_rx_csum(pp, rx_status, skb); 21607a86f05fSAndrew Lunn napi_gro_receive(napi, skb); 2161dc35a10fSMarcin Wojtas 2162dc35a10fSMarcin Wojtas rcvd_pkts++; 2163dc35a10fSMarcin Wojtas rcvd_bytes += rx_bytes; 2164dc35a10fSMarcin Wojtas 2165dc35a10fSMarcin Wojtas /* Return the buffer to the pool */ 2166dc35a10fSMarcin Wojtas mvneta_bm_pool_put_bp(pp->bm_priv, bm_pool, 2167dc35a10fSMarcin Wojtas rx_desc->buf_phys_addr); 2168dc35a10fSMarcin Wojtas 2169dc35a10fSMarcin Wojtas /* leave the descriptor and buffer untouched */ 2170dc35a10fSMarcin Wojtas continue; 2171dc35a10fSMarcin Wojtas } 2172dc35a10fSMarcin Wojtas 2173dc35a10fSMarcin Wojtas /* Refill processing */ 2174baa11ebcSGregory CLEMENT err = hwbm_pool_refill(&bm_pool->hwbm_pool, GFP_ATOMIC); 2175dc35a10fSMarcin Wojtas if (err) { 2176dc35a10fSMarcin Wojtas netdev_err(dev, "Linux processing - Can't refill\n"); 217717a96da6SGregory CLEMENT rxq->refill_err++; 2178dc35a10fSMarcin Wojtas goto err_drop_frame_ret_pool; 2179dc35a10fSMarcin Wojtas } 2180dc35a10fSMarcin Wojtas 2181baa11ebcSGregory CLEMENT frag_size = bm_pool->hwbm_pool.frag_size; 2182dc35a10fSMarcin Wojtas 2183dc35a10fSMarcin Wojtas skb = build_skb(data, frag_size > PAGE_SIZE ? 0 : frag_size); 2184dc35a10fSMarcin Wojtas 2185dc35a10fSMarcin Wojtas /* After refill old buffer has to be unmapped regardless 2186dc35a10fSMarcin Wojtas * the skb is successfully built or not. 2187dc35a10fSMarcin Wojtas */ 2188dc35a10fSMarcin Wojtas dma_unmap_single(&pp->bm_priv->pdev->dev, phys_addr, 2189dc35a10fSMarcin Wojtas bm_pool->buf_size, DMA_FROM_DEVICE); 2190dc35a10fSMarcin Wojtas if (!skb) 2191dc35a10fSMarcin Wojtas goto err_drop_frame; 2192dc35a10fSMarcin Wojtas 2193dc35a10fSMarcin Wojtas rcvd_pkts++; 2194dc35a10fSMarcin Wojtas rcvd_bytes += rx_bytes; 2195dc35a10fSMarcin Wojtas 2196dc35a10fSMarcin Wojtas /* Linux processing */ 2197dc35a10fSMarcin Wojtas skb_reserve(skb, MVNETA_MH_SIZE + NET_SKB_PAD); 2198dc35a10fSMarcin Wojtas skb_put(skb, rx_bytes); 2199dc35a10fSMarcin Wojtas 2200dc35a10fSMarcin Wojtas skb->protocol = eth_type_trans(skb, dev); 2201dc35a10fSMarcin Wojtas 2202dc35a10fSMarcin Wojtas mvneta_rx_csum(pp, rx_status, skb); 2203dc35a10fSMarcin Wojtas 22047a86f05fSAndrew Lunn napi_gro_receive(napi, skb); 2205dc35a10fSMarcin Wojtas } 2206dc35a10fSMarcin Wojtas 2207dc35a10fSMarcin Wojtas if (rcvd_pkts) { 2208dc35a10fSMarcin Wojtas struct mvneta_pcpu_stats *stats = this_cpu_ptr(pp->stats); 2209dc35a10fSMarcin Wojtas 2210dc35a10fSMarcin Wojtas u64_stats_update_begin(&stats->syncp); 2211dc35a10fSMarcin Wojtas stats->rx_packets += rcvd_pkts; 2212dc35a10fSMarcin Wojtas stats->rx_bytes += rcvd_bytes; 2213dc35a10fSMarcin Wojtas u64_stats_update_end(&stats->syncp); 2214dc35a10fSMarcin Wojtas } 2215dc35a10fSMarcin Wojtas 2216dc35a10fSMarcin Wojtas /* Update rxq management counters */ 2217dc35a10fSMarcin Wojtas mvneta_rxq_desc_num_update(pp, rxq, rx_done, rx_done); 2218dc35a10fSMarcin Wojtas 2219dc35a10fSMarcin Wojtas return rx_done; 2220dc35a10fSMarcin Wojtas } 2221dc35a10fSMarcin Wojtas 22222adb719dSEzequiel Garcia static inline void 22232adb719dSEzequiel Garcia mvneta_tso_put_hdr(struct sk_buff *skb, 22242adb719dSEzequiel Garcia struct mvneta_port *pp, struct mvneta_tx_queue *txq) 22252adb719dSEzequiel Garcia { 22262adb719dSEzequiel Garcia struct mvneta_tx_desc *tx_desc; 22272adb719dSEzequiel Garcia int hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb); 22282adb719dSEzequiel Garcia 22292adb719dSEzequiel Garcia txq->tx_skb[txq->txq_put_index] = NULL; 22302adb719dSEzequiel Garcia tx_desc = mvneta_txq_next_desc_get(txq); 22312adb719dSEzequiel Garcia tx_desc->data_size = hdr_len; 22322adb719dSEzequiel Garcia tx_desc->command = mvneta_skb_tx_csum(pp, skb); 22332adb719dSEzequiel Garcia tx_desc->command |= MVNETA_TXD_F_DESC; 22342adb719dSEzequiel Garcia tx_desc->buf_phys_addr = txq->tso_hdrs_phys + 22352adb719dSEzequiel Garcia txq->txq_put_index * TSO_HEADER_SIZE; 22362adb719dSEzequiel Garcia mvneta_txq_inc_put(txq); 22372adb719dSEzequiel Garcia } 22382adb719dSEzequiel Garcia 22392adb719dSEzequiel Garcia static inline int 22402adb719dSEzequiel Garcia mvneta_tso_put_data(struct net_device *dev, struct mvneta_tx_queue *txq, 22412adb719dSEzequiel Garcia struct sk_buff *skb, char *data, int size, 22422adb719dSEzequiel Garcia bool last_tcp, bool is_last) 22432adb719dSEzequiel Garcia { 22442adb719dSEzequiel Garcia struct mvneta_tx_desc *tx_desc; 22452adb719dSEzequiel Garcia 22462adb719dSEzequiel Garcia tx_desc = mvneta_txq_next_desc_get(txq); 22472adb719dSEzequiel Garcia tx_desc->data_size = size; 22482adb719dSEzequiel Garcia tx_desc->buf_phys_addr = dma_map_single(dev->dev.parent, data, 22492adb719dSEzequiel Garcia size, DMA_TO_DEVICE); 22502adb719dSEzequiel Garcia if (unlikely(dma_mapping_error(dev->dev.parent, 22512adb719dSEzequiel Garcia tx_desc->buf_phys_addr))) { 22522adb719dSEzequiel Garcia mvneta_txq_desc_put(txq); 22532adb719dSEzequiel Garcia return -ENOMEM; 22542adb719dSEzequiel Garcia } 22552adb719dSEzequiel Garcia 22562adb719dSEzequiel Garcia tx_desc->command = 0; 22572adb719dSEzequiel Garcia txq->tx_skb[txq->txq_put_index] = NULL; 22582adb719dSEzequiel Garcia 22592adb719dSEzequiel Garcia if (last_tcp) { 22602adb719dSEzequiel Garcia /* last descriptor in the TCP packet */ 22612adb719dSEzequiel Garcia tx_desc->command = MVNETA_TXD_L_DESC; 22622adb719dSEzequiel Garcia 22632adb719dSEzequiel Garcia /* last descriptor in SKB */ 22642adb719dSEzequiel Garcia if (is_last) 22652adb719dSEzequiel Garcia txq->tx_skb[txq->txq_put_index] = skb; 22662adb719dSEzequiel Garcia } 22672adb719dSEzequiel Garcia mvneta_txq_inc_put(txq); 22682adb719dSEzequiel Garcia return 0; 22692adb719dSEzequiel Garcia } 22702adb719dSEzequiel Garcia 22712adb719dSEzequiel Garcia static int mvneta_tx_tso(struct sk_buff *skb, struct net_device *dev, 22722adb719dSEzequiel Garcia struct mvneta_tx_queue *txq) 22732adb719dSEzequiel Garcia { 22742adb719dSEzequiel Garcia int total_len, data_left; 22752adb719dSEzequiel Garcia int desc_count = 0; 22762adb719dSEzequiel Garcia struct mvneta_port *pp = netdev_priv(dev); 22772adb719dSEzequiel Garcia struct tso_t tso; 22782adb719dSEzequiel Garcia int hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb); 22792adb719dSEzequiel Garcia int i; 22802adb719dSEzequiel Garcia 22812adb719dSEzequiel Garcia /* Count needed descriptors */ 22822adb719dSEzequiel Garcia if ((txq->count + tso_count_descs(skb)) >= txq->size) 22832adb719dSEzequiel Garcia return 0; 22842adb719dSEzequiel Garcia 22852adb719dSEzequiel Garcia if (skb_headlen(skb) < (skb_transport_offset(skb) + tcp_hdrlen(skb))) { 22862adb719dSEzequiel Garcia pr_info("*** Is this even possible???!?!?\n"); 22872adb719dSEzequiel Garcia return 0; 22882adb719dSEzequiel Garcia } 22892adb719dSEzequiel Garcia 22902adb719dSEzequiel Garcia /* Initialize the TSO handler, and prepare the first payload */ 22912adb719dSEzequiel Garcia tso_start(skb, &tso); 22922adb719dSEzequiel Garcia 22932adb719dSEzequiel Garcia total_len = skb->len - hdr_len; 22942adb719dSEzequiel Garcia while (total_len > 0) { 22952adb719dSEzequiel Garcia char *hdr; 22962adb719dSEzequiel Garcia 22972adb719dSEzequiel Garcia data_left = min_t(int, skb_shinfo(skb)->gso_size, total_len); 22982adb719dSEzequiel Garcia total_len -= data_left; 22992adb719dSEzequiel Garcia desc_count++; 23002adb719dSEzequiel Garcia 23012adb719dSEzequiel Garcia /* prepare packet headers: MAC + IP + TCP */ 23022adb719dSEzequiel Garcia hdr = txq->tso_hdrs + txq->txq_put_index * TSO_HEADER_SIZE; 23032adb719dSEzequiel Garcia tso_build_hdr(skb, hdr, &tso, data_left, total_len == 0); 23042adb719dSEzequiel Garcia 23052adb719dSEzequiel Garcia mvneta_tso_put_hdr(skb, pp, txq); 23062adb719dSEzequiel Garcia 23072adb719dSEzequiel Garcia while (data_left > 0) { 23082adb719dSEzequiel Garcia int size; 23092adb719dSEzequiel Garcia desc_count++; 23102adb719dSEzequiel Garcia 23112adb719dSEzequiel Garcia size = min_t(int, tso.size, data_left); 23122adb719dSEzequiel Garcia 23132adb719dSEzequiel Garcia if (mvneta_tso_put_data(dev, txq, skb, 23142adb719dSEzequiel Garcia tso.data, size, 23152adb719dSEzequiel Garcia size == data_left, 23162adb719dSEzequiel Garcia total_len == 0)) 23172adb719dSEzequiel Garcia goto err_release; 23182adb719dSEzequiel Garcia data_left -= size; 23192adb719dSEzequiel Garcia 23202adb719dSEzequiel Garcia tso_build_data(skb, &tso, size); 23212adb719dSEzequiel Garcia } 23222adb719dSEzequiel Garcia } 23232adb719dSEzequiel Garcia 23242adb719dSEzequiel Garcia return desc_count; 23252adb719dSEzequiel Garcia 23262adb719dSEzequiel Garcia err_release: 23272adb719dSEzequiel Garcia /* Release all used data descriptors; header descriptors must not 23282adb719dSEzequiel Garcia * be DMA-unmapped. 23292adb719dSEzequiel Garcia */ 23302adb719dSEzequiel Garcia for (i = desc_count - 1; i >= 0; i--) { 23312adb719dSEzequiel Garcia struct mvneta_tx_desc *tx_desc = txq->descs + i; 23322e3173a3SEzequiel Garcia if (!IS_TSO_HEADER(txq, tx_desc->buf_phys_addr)) 23332adb719dSEzequiel Garcia dma_unmap_single(pp->dev->dev.parent, 23342adb719dSEzequiel Garcia tx_desc->buf_phys_addr, 23352adb719dSEzequiel Garcia tx_desc->data_size, 23362adb719dSEzequiel Garcia DMA_TO_DEVICE); 23372adb719dSEzequiel Garcia mvneta_txq_desc_put(txq); 23382adb719dSEzequiel Garcia } 23392adb719dSEzequiel Garcia return 0; 23402adb719dSEzequiel Garcia } 23412adb719dSEzequiel Garcia 2342c5aff182SThomas Petazzoni /* Handle tx fragmentation processing */ 2343c5aff182SThomas Petazzoni static int mvneta_tx_frag_process(struct mvneta_port *pp, struct sk_buff *skb, 2344c5aff182SThomas Petazzoni struct mvneta_tx_queue *txq) 2345c5aff182SThomas Petazzoni { 2346c5aff182SThomas Petazzoni struct mvneta_tx_desc *tx_desc; 23473d4ea02fSEzequiel Garcia int i, nr_frags = skb_shinfo(skb)->nr_frags; 2348c5aff182SThomas Petazzoni 23493d4ea02fSEzequiel Garcia for (i = 0; i < nr_frags; i++) { 2350c5aff182SThomas Petazzoni skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 2351c5aff182SThomas Petazzoni void *addr = page_address(frag->page.p) + frag->page_offset; 2352c5aff182SThomas Petazzoni 2353c5aff182SThomas Petazzoni tx_desc = mvneta_txq_next_desc_get(txq); 2354c5aff182SThomas Petazzoni tx_desc->data_size = frag->size; 2355c5aff182SThomas Petazzoni 2356c5aff182SThomas Petazzoni tx_desc->buf_phys_addr = 2357c5aff182SThomas Petazzoni dma_map_single(pp->dev->dev.parent, addr, 2358c5aff182SThomas Petazzoni tx_desc->data_size, DMA_TO_DEVICE); 2359c5aff182SThomas Petazzoni 2360c5aff182SThomas Petazzoni if (dma_mapping_error(pp->dev->dev.parent, 2361c5aff182SThomas Petazzoni tx_desc->buf_phys_addr)) { 2362c5aff182SThomas Petazzoni mvneta_txq_desc_put(txq); 2363c5aff182SThomas Petazzoni goto error; 2364c5aff182SThomas Petazzoni } 2365c5aff182SThomas Petazzoni 23663d4ea02fSEzequiel Garcia if (i == nr_frags - 1) { 2367c5aff182SThomas Petazzoni /* Last descriptor */ 2368c5aff182SThomas Petazzoni tx_desc->command = MVNETA_TXD_L_DESC | MVNETA_TXD_Z_PAD; 2369c5aff182SThomas Petazzoni txq->tx_skb[txq->txq_put_index] = skb; 2370c5aff182SThomas Petazzoni } else { 2371c5aff182SThomas Petazzoni /* Descriptor in the middle: Not First, Not Last */ 2372c5aff182SThomas Petazzoni tx_desc->command = 0; 2373c5aff182SThomas Petazzoni txq->tx_skb[txq->txq_put_index] = NULL; 2374c5aff182SThomas Petazzoni } 23753d4ea02fSEzequiel Garcia mvneta_txq_inc_put(txq); 2376c5aff182SThomas Petazzoni } 2377c5aff182SThomas Petazzoni 2378c5aff182SThomas Petazzoni return 0; 2379c5aff182SThomas Petazzoni 2380c5aff182SThomas Petazzoni error: 2381c5aff182SThomas Petazzoni /* Release all descriptors that were used to map fragments of 23826a20c175SThomas Petazzoni * this packet, as well as the corresponding DMA mappings 23836a20c175SThomas Petazzoni */ 2384c5aff182SThomas Petazzoni for (i = i - 1; i >= 0; i--) { 2385c5aff182SThomas Petazzoni tx_desc = txq->descs + i; 2386c5aff182SThomas Petazzoni dma_unmap_single(pp->dev->dev.parent, 2387c5aff182SThomas Petazzoni tx_desc->buf_phys_addr, 2388c5aff182SThomas Petazzoni tx_desc->data_size, 2389c5aff182SThomas Petazzoni DMA_TO_DEVICE); 2390c5aff182SThomas Petazzoni mvneta_txq_desc_put(txq); 2391c5aff182SThomas Petazzoni } 2392c5aff182SThomas Petazzoni 2393c5aff182SThomas Petazzoni return -ENOMEM; 2394c5aff182SThomas Petazzoni } 2395c5aff182SThomas Petazzoni 2396c5aff182SThomas Petazzoni /* Main tx processing */ 2397f03508ceSYueHaibing static netdev_tx_t mvneta_tx(struct sk_buff *skb, struct net_device *dev) 2398c5aff182SThomas Petazzoni { 2399c5aff182SThomas Petazzoni struct mvneta_port *pp = netdev_priv(dev); 2400ee40a116SWilly Tarreau u16 txq_id = skb_get_queue_mapping(skb); 2401ee40a116SWilly Tarreau struct mvneta_tx_queue *txq = &pp->txqs[txq_id]; 2402c5aff182SThomas Petazzoni struct mvneta_tx_desc *tx_desc; 24035f478b41SEric Dumazet int len = skb->len; 2404c5aff182SThomas Petazzoni int frags = 0; 2405c5aff182SThomas Petazzoni u32 tx_cmd; 2406c5aff182SThomas Petazzoni 2407c5aff182SThomas Petazzoni if (!netif_running(dev)) 2408c5aff182SThomas Petazzoni goto out; 2409c5aff182SThomas Petazzoni 24102adb719dSEzequiel Garcia if (skb_is_gso(skb)) { 24112adb719dSEzequiel Garcia frags = mvneta_tx_tso(skb, dev, txq); 24122adb719dSEzequiel Garcia goto out; 24132adb719dSEzequiel Garcia } 24142adb719dSEzequiel Garcia 2415c5aff182SThomas Petazzoni frags = skb_shinfo(skb)->nr_frags + 1; 2416c5aff182SThomas Petazzoni 2417c5aff182SThomas Petazzoni /* Get a descriptor for the first part of the packet */ 2418c5aff182SThomas Petazzoni tx_desc = mvneta_txq_next_desc_get(txq); 2419c5aff182SThomas Petazzoni 2420c5aff182SThomas Petazzoni tx_cmd = mvneta_skb_tx_csum(pp, skb); 2421c5aff182SThomas Petazzoni 2422c5aff182SThomas Petazzoni tx_desc->data_size = skb_headlen(skb); 2423c5aff182SThomas Petazzoni 2424c5aff182SThomas Petazzoni tx_desc->buf_phys_addr = dma_map_single(dev->dev.parent, skb->data, 2425c5aff182SThomas Petazzoni tx_desc->data_size, 2426c5aff182SThomas Petazzoni DMA_TO_DEVICE); 2427c5aff182SThomas Petazzoni if (unlikely(dma_mapping_error(dev->dev.parent, 2428c5aff182SThomas Petazzoni tx_desc->buf_phys_addr))) { 2429c5aff182SThomas Petazzoni mvneta_txq_desc_put(txq); 2430c5aff182SThomas Petazzoni frags = 0; 2431c5aff182SThomas Petazzoni goto out; 2432c5aff182SThomas Petazzoni } 2433c5aff182SThomas Petazzoni 2434c5aff182SThomas Petazzoni if (frags == 1) { 2435c5aff182SThomas Petazzoni /* First and Last descriptor */ 2436c5aff182SThomas Petazzoni tx_cmd |= MVNETA_TXD_FLZ_DESC; 2437c5aff182SThomas Petazzoni tx_desc->command = tx_cmd; 2438c5aff182SThomas Petazzoni txq->tx_skb[txq->txq_put_index] = skb; 2439c5aff182SThomas Petazzoni mvneta_txq_inc_put(txq); 2440c5aff182SThomas Petazzoni } else { 2441c5aff182SThomas Petazzoni /* First but not Last */ 2442c5aff182SThomas Petazzoni tx_cmd |= MVNETA_TXD_F_DESC; 2443c5aff182SThomas Petazzoni txq->tx_skb[txq->txq_put_index] = NULL; 2444c5aff182SThomas Petazzoni mvneta_txq_inc_put(txq); 2445c5aff182SThomas Petazzoni tx_desc->command = tx_cmd; 2446c5aff182SThomas Petazzoni /* Continue with other skb fragments */ 2447c5aff182SThomas Petazzoni if (mvneta_tx_frag_process(pp, skb, txq)) { 2448c5aff182SThomas Petazzoni dma_unmap_single(dev->dev.parent, 2449c5aff182SThomas Petazzoni tx_desc->buf_phys_addr, 2450c5aff182SThomas Petazzoni tx_desc->data_size, 2451c5aff182SThomas Petazzoni DMA_TO_DEVICE); 2452c5aff182SThomas Petazzoni mvneta_txq_desc_put(txq); 2453c5aff182SThomas Petazzoni frags = 0; 2454c5aff182SThomas Petazzoni goto out; 2455c5aff182SThomas Petazzoni } 2456c5aff182SThomas Petazzoni } 2457c5aff182SThomas Petazzoni 2458e19d2ddaSEzequiel Garcia out: 2459e19d2ddaSEzequiel Garcia if (frags > 0) { 2460e19d2ddaSEzequiel Garcia struct mvneta_pcpu_stats *stats = this_cpu_ptr(pp->stats); 2461e19d2ddaSEzequiel Garcia struct netdev_queue *nq = netdev_get_tx_queue(dev, txq_id); 2462e19d2ddaSEzequiel Garcia 2463a29b6235SMarcin Wojtas netdev_tx_sent_queue(nq, len); 2464a29b6235SMarcin Wojtas 2465c5aff182SThomas Petazzoni txq->count += frags; 24668eef5f97SEzequiel Garcia if (txq->count >= txq->tx_stop_threshold) 2467c5aff182SThomas Petazzoni netif_tx_stop_queue(nq); 2468c5aff182SThomas Petazzoni 24692a90f7e1SSimon Guinot if (!skb->xmit_more || netif_xmit_stopped(nq) || 24702a90f7e1SSimon Guinot txq->pending + frags > MVNETA_TXQ_DEC_SENT_MASK) 24712a90f7e1SSimon Guinot mvneta_txq_pend_desc_add(pp, txq, frags); 24722a90f7e1SSimon Guinot else 24732a90f7e1SSimon Guinot txq->pending += frags; 24742a90f7e1SSimon Guinot 247574c41b04Swilly tarreau u64_stats_update_begin(&stats->syncp); 247674c41b04Swilly tarreau stats->tx_packets++; 24775f478b41SEric Dumazet stats->tx_bytes += len; 247874c41b04Swilly tarreau u64_stats_update_end(&stats->syncp); 2479c5aff182SThomas Petazzoni } else { 2480c5aff182SThomas Petazzoni dev->stats.tx_dropped++; 2481c5aff182SThomas Petazzoni dev_kfree_skb_any(skb); 2482c5aff182SThomas Petazzoni } 2483c5aff182SThomas Petazzoni 2484c5aff182SThomas Petazzoni return NETDEV_TX_OK; 2485c5aff182SThomas Petazzoni } 2486c5aff182SThomas Petazzoni 2487c5aff182SThomas Petazzoni 2488c5aff182SThomas Petazzoni /* Free tx resources, when resetting a port */ 2489c5aff182SThomas Petazzoni static void mvneta_txq_done_force(struct mvneta_port *pp, 2490c5aff182SThomas Petazzoni struct mvneta_tx_queue *txq) 2491c5aff182SThomas Petazzoni 2492c5aff182SThomas Petazzoni { 2493a29b6235SMarcin Wojtas struct netdev_queue *nq = netdev_get_tx_queue(pp->dev, txq->id); 2494c5aff182SThomas Petazzoni int tx_done = txq->count; 2495c5aff182SThomas Petazzoni 2496a29b6235SMarcin Wojtas mvneta_txq_bufs_free(pp, txq, tx_done, nq); 2497c5aff182SThomas Petazzoni 2498c5aff182SThomas Petazzoni /* reset txq */ 2499c5aff182SThomas Petazzoni txq->count = 0; 2500c5aff182SThomas Petazzoni txq->txq_put_index = 0; 2501c5aff182SThomas Petazzoni txq->txq_get_index = 0; 2502c5aff182SThomas Petazzoni } 2503c5aff182SThomas Petazzoni 25046c498974Swilly tarreau /* Handle tx done - called in softirq context. The <cause_tx_done> argument 25056c498974Swilly tarreau * must be a valid cause according to MVNETA_TXQ_INTR_MASK_ALL. 25066c498974Swilly tarreau */ 25070713a86aSArnaud Ebalard static void mvneta_tx_done_gbe(struct mvneta_port *pp, u32 cause_tx_done) 2508c5aff182SThomas Petazzoni { 2509c5aff182SThomas Petazzoni struct mvneta_tx_queue *txq; 2510c5aff182SThomas Petazzoni struct netdev_queue *nq; 2511bd9f1ee3SJisheng Zhang int cpu = smp_processor_id(); 2512c5aff182SThomas Petazzoni 25136c498974Swilly tarreau while (cause_tx_done) { 2514c5aff182SThomas Petazzoni txq = mvneta_tx_done_policy(pp, cause_tx_done); 2515c5aff182SThomas Petazzoni 2516c5aff182SThomas Petazzoni nq = netdev_get_tx_queue(pp->dev, txq->id); 2517bd9f1ee3SJisheng Zhang __netif_tx_lock(nq, cpu); 2518c5aff182SThomas Petazzoni 25190713a86aSArnaud Ebalard if (txq->count) 25200713a86aSArnaud Ebalard mvneta_txq_done(pp, txq); 2521c5aff182SThomas Petazzoni 2522c5aff182SThomas Petazzoni __netif_tx_unlock(nq); 2523c5aff182SThomas Petazzoni cause_tx_done &= ~((1 << txq->id)); 2524c5aff182SThomas Petazzoni } 2525c5aff182SThomas Petazzoni } 2526c5aff182SThomas Petazzoni 25276a20c175SThomas Petazzoni /* Compute crc8 of the specified address, using a unique algorithm , 2528c5aff182SThomas Petazzoni * according to hw spec, different than generic crc8 algorithm 2529c5aff182SThomas Petazzoni */ 2530c5aff182SThomas Petazzoni static int mvneta_addr_crc(unsigned char *addr) 2531c5aff182SThomas Petazzoni { 2532c5aff182SThomas Petazzoni int crc = 0; 2533c5aff182SThomas Petazzoni int i; 2534c5aff182SThomas Petazzoni 2535c5aff182SThomas Petazzoni for (i = 0; i < ETH_ALEN; i++) { 2536c5aff182SThomas Petazzoni int j; 2537c5aff182SThomas Petazzoni 2538c5aff182SThomas Petazzoni crc = (crc ^ addr[i]) << 8; 2539c5aff182SThomas Petazzoni for (j = 7; j >= 0; j--) { 2540c5aff182SThomas Petazzoni if (crc & (0x100 << j)) 2541c5aff182SThomas Petazzoni crc ^= 0x107 << j; 2542c5aff182SThomas Petazzoni } 2543c5aff182SThomas Petazzoni } 2544c5aff182SThomas Petazzoni 2545c5aff182SThomas Petazzoni return crc; 2546c5aff182SThomas Petazzoni } 2547c5aff182SThomas Petazzoni 2548c5aff182SThomas Petazzoni /* This method controls the net device special MAC multicast support. 2549c5aff182SThomas Petazzoni * The Special Multicast Table for MAC addresses supports MAC of the form 2550c5aff182SThomas Petazzoni * 0x01-00-5E-00-00-XX (where XX is between 0x00 and 0xFF). 2551c5aff182SThomas Petazzoni * The MAC DA[7:0] bits are used as a pointer to the Special Multicast 2552c5aff182SThomas Petazzoni * Table entries in the DA-Filter table. This method set the Special 2553c5aff182SThomas Petazzoni * Multicast Table appropriate entry. 2554c5aff182SThomas Petazzoni */ 2555c5aff182SThomas Petazzoni static void mvneta_set_special_mcast_addr(struct mvneta_port *pp, 2556c5aff182SThomas Petazzoni unsigned char last_byte, 2557c5aff182SThomas Petazzoni int queue) 2558c5aff182SThomas Petazzoni { 2559c5aff182SThomas Petazzoni unsigned int smc_table_reg; 2560c5aff182SThomas Petazzoni unsigned int tbl_offset; 2561c5aff182SThomas Petazzoni unsigned int reg_offset; 2562c5aff182SThomas Petazzoni 2563c5aff182SThomas Petazzoni /* Register offset from SMC table base */ 2564c5aff182SThomas Petazzoni tbl_offset = (last_byte / 4); 2565c5aff182SThomas Petazzoni /* Entry offset within the above reg */ 2566c5aff182SThomas Petazzoni reg_offset = last_byte % 4; 2567c5aff182SThomas Petazzoni 2568c5aff182SThomas Petazzoni smc_table_reg = mvreg_read(pp, (MVNETA_DA_FILT_SPEC_MCAST 2569c5aff182SThomas Petazzoni + tbl_offset * 4)); 2570c5aff182SThomas Petazzoni 2571c5aff182SThomas Petazzoni if (queue == -1) 2572c5aff182SThomas Petazzoni smc_table_reg &= ~(0xff << (8 * reg_offset)); 2573c5aff182SThomas Petazzoni else { 2574c5aff182SThomas Petazzoni smc_table_reg &= ~(0xff << (8 * reg_offset)); 2575c5aff182SThomas Petazzoni smc_table_reg |= ((0x01 | (queue << 1)) << (8 * reg_offset)); 2576c5aff182SThomas Petazzoni } 2577c5aff182SThomas Petazzoni 2578c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_DA_FILT_SPEC_MCAST + tbl_offset * 4, 2579c5aff182SThomas Petazzoni smc_table_reg); 2580c5aff182SThomas Petazzoni } 2581c5aff182SThomas Petazzoni 2582c5aff182SThomas Petazzoni /* This method controls the network device Other MAC multicast support. 2583c5aff182SThomas Petazzoni * The Other Multicast Table is used for multicast of another type. 2584c5aff182SThomas Petazzoni * A CRC-8 is used as an index to the Other Multicast Table entries 2585c5aff182SThomas Petazzoni * in the DA-Filter table. 2586c5aff182SThomas Petazzoni * The method gets the CRC-8 value from the calling routine and 2587c5aff182SThomas Petazzoni * sets the Other Multicast Table appropriate entry according to the 2588c5aff182SThomas Petazzoni * specified CRC-8 . 2589c5aff182SThomas Petazzoni */ 2590c5aff182SThomas Petazzoni static void mvneta_set_other_mcast_addr(struct mvneta_port *pp, 2591c5aff182SThomas Petazzoni unsigned char crc8, 2592c5aff182SThomas Petazzoni int queue) 2593c5aff182SThomas Petazzoni { 2594c5aff182SThomas Petazzoni unsigned int omc_table_reg; 2595c5aff182SThomas Petazzoni unsigned int tbl_offset; 2596c5aff182SThomas Petazzoni unsigned int reg_offset; 2597c5aff182SThomas Petazzoni 2598c5aff182SThomas Petazzoni tbl_offset = (crc8 / 4) * 4; /* Register offset from OMC table base */ 2599c5aff182SThomas Petazzoni reg_offset = crc8 % 4; /* Entry offset within the above reg */ 2600c5aff182SThomas Petazzoni 2601c5aff182SThomas Petazzoni omc_table_reg = mvreg_read(pp, MVNETA_DA_FILT_OTH_MCAST + tbl_offset); 2602c5aff182SThomas Petazzoni 2603c5aff182SThomas Petazzoni if (queue == -1) { 2604c5aff182SThomas Petazzoni /* Clear accepts frame bit at specified Other DA table entry */ 2605c5aff182SThomas Petazzoni omc_table_reg &= ~(0xff << (8 * reg_offset)); 2606c5aff182SThomas Petazzoni } else { 2607c5aff182SThomas Petazzoni omc_table_reg &= ~(0xff << (8 * reg_offset)); 2608c5aff182SThomas Petazzoni omc_table_reg |= ((0x01 | (queue << 1)) << (8 * reg_offset)); 2609c5aff182SThomas Petazzoni } 2610c5aff182SThomas Petazzoni 2611c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_DA_FILT_OTH_MCAST + tbl_offset, omc_table_reg); 2612c5aff182SThomas Petazzoni } 2613c5aff182SThomas Petazzoni 2614c5aff182SThomas Petazzoni /* The network device supports multicast using two tables: 2615c5aff182SThomas Petazzoni * 1) Special Multicast Table for MAC addresses of the form 2616c5aff182SThomas Petazzoni * 0x01-00-5E-00-00-XX (where XX is between 0x00 and 0xFF). 2617c5aff182SThomas Petazzoni * The MAC DA[7:0] bits are used as a pointer to the Special Multicast 2618c5aff182SThomas Petazzoni * Table entries in the DA-Filter table. 2619c5aff182SThomas Petazzoni * 2) Other Multicast Table for multicast of another type. A CRC-8 value 2620c5aff182SThomas Petazzoni * is used as an index to the Other Multicast Table entries in the 2621c5aff182SThomas Petazzoni * DA-Filter table. 2622c5aff182SThomas Petazzoni */ 2623c5aff182SThomas Petazzoni static int mvneta_mcast_addr_set(struct mvneta_port *pp, unsigned char *p_addr, 2624c5aff182SThomas Petazzoni int queue) 2625c5aff182SThomas Petazzoni { 2626c5aff182SThomas Petazzoni unsigned char crc_result = 0; 2627c5aff182SThomas Petazzoni 2628c5aff182SThomas Petazzoni if (memcmp(p_addr, "\x01\x00\x5e\x00\x00", 5) == 0) { 2629c5aff182SThomas Petazzoni mvneta_set_special_mcast_addr(pp, p_addr[5], queue); 2630c5aff182SThomas Petazzoni return 0; 2631c5aff182SThomas Petazzoni } 2632c5aff182SThomas Petazzoni 2633c5aff182SThomas Petazzoni crc_result = mvneta_addr_crc(p_addr); 2634c5aff182SThomas Petazzoni if (queue == -1) { 2635c5aff182SThomas Petazzoni if (pp->mcast_count[crc_result] == 0) { 2636c5aff182SThomas Petazzoni netdev_info(pp->dev, "No valid Mcast for crc8=0x%02x\n", 2637c5aff182SThomas Petazzoni crc_result); 2638c5aff182SThomas Petazzoni return -EINVAL; 2639c5aff182SThomas Petazzoni } 2640c5aff182SThomas Petazzoni 2641c5aff182SThomas Petazzoni pp->mcast_count[crc_result]--; 2642c5aff182SThomas Petazzoni if (pp->mcast_count[crc_result] != 0) { 2643c5aff182SThomas Petazzoni netdev_info(pp->dev, 2644c5aff182SThomas Petazzoni "After delete there are %d valid Mcast for crc8=0x%02x\n", 2645c5aff182SThomas Petazzoni pp->mcast_count[crc_result], crc_result); 2646c5aff182SThomas Petazzoni return -EINVAL; 2647c5aff182SThomas Petazzoni } 2648c5aff182SThomas Petazzoni } else 2649c5aff182SThomas Petazzoni pp->mcast_count[crc_result]++; 2650c5aff182SThomas Petazzoni 2651c5aff182SThomas Petazzoni mvneta_set_other_mcast_addr(pp, crc_result, queue); 2652c5aff182SThomas Petazzoni 2653c5aff182SThomas Petazzoni return 0; 2654c5aff182SThomas Petazzoni } 2655c5aff182SThomas Petazzoni 2656c5aff182SThomas Petazzoni /* Configure Fitering mode of Ethernet port */ 2657c5aff182SThomas Petazzoni static void mvneta_rx_unicast_promisc_set(struct mvneta_port *pp, 2658c5aff182SThomas Petazzoni int is_promisc) 2659c5aff182SThomas Petazzoni { 2660c5aff182SThomas Petazzoni u32 port_cfg_reg, val; 2661c5aff182SThomas Petazzoni 2662c5aff182SThomas Petazzoni port_cfg_reg = mvreg_read(pp, MVNETA_PORT_CONFIG); 2663c5aff182SThomas Petazzoni 2664c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_TYPE_PRIO); 2665c5aff182SThomas Petazzoni 2666c5aff182SThomas Petazzoni /* Set / Clear UPM bit in port configuration register */ 2667c5aff182SThomas Petazzoni if (is_promisc) { 2668c5aff182SThomas Petazzoni /* Accept all Unicast addresses */ 2669c5aff182SThomas Petazzoni port_cfg_reg |= MVNETA_UNI_PROMISC_MODE; 2670c5aff182SThomas Petazzoni val |= MVNETA_FORCE_UNI; 2671c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_MAC_ADDR_LOW, 0xffff); 2672c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_MAC_ADDR_HIGH, 0xffffffff); 2673c5aff182SThomas Petazzoni } else { 2674c5aff182SThomas Petazzoni /* Reject all Unicast addresses */ 2675c5aff182SThomas Petazzoni port_cfg_reg &= ~MVNETA_UNI_PROMISC_MODE; 2676c5aff182SThomas Petazzoni val &= ~MVNETA_FORCE_UNI; 2677c5aff182SThomas Petazzoni } 2678c5aff182SThomas Petazzoni 2679c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_PORT_CONFIG, port_cfg_reg); 2680c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_TYPE_PRIO, val); 2681c5aff182SThomas Petazzoni } 2682c5aff182SThomas Petazzoni 2683c5aff182SThomas Petazzoni /* register unicast and multicast addresses */ 2684c5aff182SThomas Petazzoni static void mvneta_set_rx_mode(struct net_device *dev) 2685c5aff182SThomas Petazzoni { 2686c5aff182SThomas Petazzoni struct mvneta_port *pp = netdev_priv(dev); 2687c5aff182SThomas Petazzoni struct netdev_hw_addr *ha; 2688c5aff182SThomas Petazzoni 2689c5aff182SThomas Petazzoni if (dev->flags & IFF_PROMISC) { 2690c5aff182SThomas Petazzoni /* Accept all: Multicast + Unicast */ 2691c5aff182SThomas Petazzoni mvneta_rx_unicast_promisc_set(pp, 1); 269290b74c01SGregory CLEMENT mvneta_set_ucast_table(pp, pp->rxq_def); 269390b74c01SGregory CLEMENT mvneta_set_special_mcast_table(pp, pp->rxq_def); 269490b74c01SGregory CLEMENT mvneta_set_other_mcast_table(pp, pp->rxq_def); 2695c5aff182SThomas Petazzoni } else { 2696c5aff182SThomas Petazzoni /* Accept single Unicast */ 2697c5aff182SThomas Petazzoni mvneta_rx_unicast_promisc_set(pp, 0); 2698c5aff182SThomas Petazzoni mvneta_set_ucast_table(pp, -1); 269990b74c01SGregory CLEMENT mvneta_mac_addr_set(pp, dev->dev_addr, pp->rxq_def); 2700c5aff182SThomas Petazzoni 2701c5aff182SThomas Petazzoni if (dev->flags & IFF_ALLMULTI) { 2702c5aff182SThomas Petazzoni /* Accept all multicast */ 270390b74c01SGregory CLEMENT mvneta_set_special_mcast_table(pp, pp->rxq_def); 270490b74c01SGregory CLEMENT mvneta_set_other_mcast_table(pp, pp->rxq_def); 2705c5aff182SThomas Petazzoni } else { 2706c5aff182SThomas Petazzoni /* Accept only initialized multicast */ 2707c5aff182SThomas Petazzoni mvneta_set_special_mcast_table(pp, -1); 2708c5aff182SThomas Petazzoni mvneta_set_other_mcast_table(pp, -1); 2709c5aff182SThomas Petazzoni 2710c5aff182SThomas Petazzoni if (!netdev_mc_empty(dev)) { 2711c5aff182SThomas Petazzoni netdev_for_each_mc_addr(ha, dev) { 2712c5aff182SThomas Petazzoni mvneta_mcast_addr_set(pp, ha->addr, 271390b74c01SGregory CLEMENT pp->rxq_def); 2714c5aff182SThomas Petazzoni } 2715c5aff182SThomas Petazzoni } 2716c5aff182SThomas Petazzoni } 2717c5aff182SThomas Petazzoni } 2718c5aff182SThomas Petazzoni } 2719c5aff182SThomas Petazzoni 2720c5aff182SThomas Petazzoni /* Interrupt handling - the callback for request_irq() */ 2721c5aff182SThomas Petazzoni static irqreturn_t mvneta_isr(int irq, void *dev_id) 2722c5aff182SThomas Petazzoni { 27232636ac3cSMarcin Wojtas struct mvneta_port *pp = (struct mvneta_port *)dev_id; 27242636ac3cSMarcin Wojtas 27252636ac3cSMarcin Wojtas mvreg_write(pp, MVNETA_INTR_NEW_MASK, 0); 27262636ac3cSMarcin Wojtas napi_schedule(&pp->napi); 27272636ac3cSMarcin Wojtas 27282636ac3cSMarcin Wojtas return IRQ_HANDLED; 27292636ac3cSMarcin Wojtas } 27302636ac3cSMarcin Wojtas 27312636ac3cSMarcin Wojtas /* Interrupt handling - the callback for request_percpu_irq() */ 27322636ac3cSMarcin Wojtas static irqreturn_t mvneta_percpu_isr(int irq, void *dev_id) 27332636ac3cSMarcin Wojtas { 273412bb03b4SMaxime Ripard struct mvneta_pcpu_port *port = (struct mvneta_pcpu_port *)dev_id; 2735c5aff182SThomas Petazzoni 273612bb03b4SMaxime Ripard disable_percpu_irq(port->pp->dev->irq); 273712bb03b4SMaxime Ripard napi_schedule(&port->napi); 2738c5aff182SThomas Petazzoni 2739c5aff182SThomas Petazzoni return IRQ_HANDLED; 2740c5aff182SThomas Petazzoni } 2741c5aff182SThomas Petazzoni 2742503f9aa9SRussell King static void mvneta_link_change(struct mvneta_port *pp) 2743898b2970SStas Sergeev { 2744898b2970SStas Sergeev u32 gmac_stat = mvreg_read(pp, MVNETA_GMAC_STATUS); 2745898b2970SStas Sergeev 2746503f9aa9SRussell King phylink_mac_change(pp->phylink, !!(gmac_stat & MVNETA_GMAC_LINK_UP)); 2747898b2970SStas Sergeev } 2748898b2970SStas Sergeev 2749c5aff182SThomas Petazzoni /* NAPI handler 2750c5aff182SThomas Petazzoni * Bits 0 - 7 of the causeRxTx register indicate that are transmitted 2751c5aff182SThomas Petazzoni * packets on the corresponding TXQ (Bit 0 is for TX queue 1). 2752c5aff182SThomas Petazzoni * Bits 8 -15 of the cause Rx Tx register indicate that are received 2753c5aff182SThomas Petazzoni * packets on the corresponding RXQ (Bit 8 is for RX queue 0). 2754c5aff182SThomas Petazzoni * Each CPU has its own causeRxTx register 2755c5aff182SThomas Petazzoni */ 2756c5aff182SThomas Petazzoni static int mvneta_poll(struct napi_struct *napi, int budget) 2757c5aff182SThomas Petazzoni { 2758c5aff182SThomas Petazzoni int rx_done = 0; 2759c5aff182SThomas Petazzoni u32 cause_rx_tx; 27602dcf75e2SGregory CLEMENT int rx_queue; 2761c5aff182SThomas Petazzoni struct mvneta_port *pp = netdev_priv(napi->dev); 276212bb03b4SMaxime Ripard struct mvneta_pcpu_port *port = this_cpu_ptr(pp->ports); 2763c5aff182SThomas Petazzoni 2764c5aff182SThomas Petazzoni if (!netif_running(pp->dev)) { 27652636ac3cSMarcin Wojtas napi_complete(napi); 2766c5aff182SThomas Petazzoni return rx_done; 2767c5aff182SThomas Petazzoni } 2768c5aff182SThomas Petazzoni 2769c5aff182SThomas Petazzoni /* Read cause register */ 2770898b2970SStas Sergeev cause_rx_tx = mvreg_read(pp, MVNETA_INTR_NEW_CAUSE); 2771898b2970SStas Sergeev if (cause_rx_tx & MVNETA_MISCINTR_INTR_MASK) { 2772898b2970SStas Sergeev u32 cause_misc = mvreg_read(pp, MVNETA_INTR_MISC_CAUSE); 2773898b2970SStas Sergeev 2774898b2970SStas Sergeev mvreg_write(pp, MVNETA_INTR_MISC_CAUSE, 0); 2775503f9aa9SRussell King 2776503f9aa9SRussell King if (cause_misc & (MVNETA_CAUSE_PHY_STATUS_CHANGE | 2777856b2cc5SRussell King MVNETA_CAUSE_LINK_CHANGE)) 2778503f9aa9SRussell King mvneta_link_change(pp); 2779898b2970SStas Sergeev } 278071f6d1b3Swilly tarreau 278171f6d1b3Swilly tarreau /* Release Tx descriptors */ 278271f6d1b3Swilly tarreau if (cause_rx_tx & MVNETA_TX_INTR_MASK_ALL) { 27830713a86aSArnaud Ebalard mvneta_tx_done_gbe(pp, (cause_rx_tx & MVNETA_TX_INTR_MASK_ALL)); 278471f6d1b3Swilly tarreau cause_rx_tx &= ~MVNETA_TX_INTR_MASK_ALL; 278571f6d1b3Swilly tarreau } 2786c5aff182SThomas Petazzoni 27876a20c175SThomas Petazzoni /* For the case where the last mvneta_poll did not process all 2788c5aff182SThomas Petazzoni * RX packets 2789c5aff182SThomas Petazzoni */ 27902dcf75e2SGregory CLEMENT rx_queue = fls(((cause_rx_tx >> 8) & 0xff)); 27912dcf75e2SGregory CLEMENT 27922636ac3cSMarcin Wojtas cause_rx_tx |= pp->neta_armada3700 ? pp->cause_rx_tx : 27932636ac3cSMarcin Wojtas port->cause_rx_tx; 27942dcf75e2SGregory CLEMENT 27952dcf75e2SGregory CLEMENT if (rx_queue) { 27962dcf75e2SGregory CLEMENT rx_queue = rx_queue - 1; 2797dc35a10fSMarcin Wojtas if (pp->bm_priv) 27987a86f05fSAndrew Lunn rx_done = mvneta_rx_hwbm(napi, pp, budget, 27997a86f05fSAndrew Lunn &pp->rxqs[rx_queue]); 2800dc35a10fSMarcin Wojtas else 28017a86f05fSAndrew Lunn rx_done = mvneta_rx_swbm(napi, pp, budget, 28027a86f05fSAndrew Lunn &pp->rxqs[rx_queue]); 28032dcf75e2SGregory CLEMENT } 28042dcf75e2SGregory CLEMENT 28056ad20165SEric Dumazet if (rx_done < budget) { 2806c5aff182SThomas Petazzoni cause_rx_tx = 0; 28076ad20165SEric Dumazet napi_complete_done(napi, rx_done); 28082636ac3cSMarcin Wojtas 28092636ac3cSMarcin Wojtas if (pp->neta_armada3700) { 28102636ac3cSMarcin Wojtas unsigned long flags; 28112636ac3cSMarcin Wojtas 28122636ac3cSMarcin Wojtas local_irq_save(flags); 28132636ac3cSMarcin Wojtas mvreg_write(pp, MVNETA_INTR_NEW_MASK, 28142636ac3cSMarcin Wojtas MVNETA_RX_INTR_MASK(rxq_number) | 28152636ac3cSMarcin Wojtas MVNETA_TX_INTR_MASK(txq_number) | 28162636ac3cSMarcin Wojtas MVNETA_MISCINTR_INTR_MASK); 28172636ac3cSMarcin Wojtas local_irq_restore(flags); 28182636ac3cSMarcin Wojtas } else { 281912bb03b4SMaxime Ripard enable_percpu_irq(pp->dev->irq, 0); 2820c5aff182SThomas Petazzoni } 28212636ac3cSMarcin Wojtas } 2822c5aff182SThomas Petazzoni 28232636ac3cSMarcin Wojtas if (pp->neta_armada3700) 28242636ac3cSMarcin Wojtas pp->cause_rx_tx = cause_rx_tx; 28252636ac3cSMarcin Wojtas else 282612bb03b4SMaxime Ripard port->cause_rx_tx = cause_rx_tx; 28272636ac3cSMarcin Wojtas 2828c5aff182SThomas Petazzoni return rx_done; 2829c5aff182SThomas Petazzoni } 2830c5aff182SThomas Petazzoni 2831c5aff182SThomas Petazzoni /* Handle rxq fill: allocates rxq skbs; called when initializing a port */ 2832c5aff182SThomas Petazzoni static int mvneta_rxq_fill(struct mvneta_port *pp, struct mvneta_rx_queue *rxq, 2833c5aff182SThomas Petazzoni int num) 2834c5aff182SThomas Petazzoni { 2835c5aff182SThomas Petazzoni int i; 2836c5aff182SThomas Petazzoni 2837c5aff182SThomas Petazzoni for (i = 0; i < num; i++) { 2838a1a65ab1Swilly tarreau memset(rxq->descs + i, 0, sizeof(struct mvneta_rx_desc)); 28397e47fd84SGregory CLEMENT if (mvneta_rx_refill(pp, rxq->descs + i, rxq, 28407e47fd84SGregory CLEMENT GFP_KERNEL) != 0) { 28417e47fd84SGregory CLEMENT netdev_err(pp->dev, 28427e47fd84SGregory CLEMENT "%s:rxq %d, %d of %d buffs filled\n", 2843c5aff182SThomas Petazzoni __func__, rxq->id, i, num); 2844c5aff182SThomas Petazzoni break; 2845c5aff182SThomas Petazzoni } 2846c5aff182SThomas Petazzoni } 2847c5aff182SThomas Petazzoni 2848c5aff182SThomas Petazzoni /* Add this number of RX descriptors as non occupied (ready to 28496a20c175SThomas Petazzoni * get packets) 28506a20c175SThomas Petazzoni */ 2851c5aff182SThomas Petazzoni mvneta_rxq_non_occup_desc_add(pp, rxq, i); 2852c5aff182SThomas Petazzoni 2853c5aff182SThomas Petazzoni return i; 2854c5aff182SThomas Petazzoni } 2855c5aff182SThomas Petazzoni 2856c5aff182SThomas Petazzoni /* Free all packets pending transmit from all TXQs and reset TX port */ 2857c5aff182SThomas Petazzoni static void mvneta_tx_reset(struct mvneta_port *pp) 2858c5aff182SThomas Petazzoni { 2859c5aff182SThomas Petazzoni int queue; 2860c5aff182SThomas Petazzoni 28619672850bSEzequiel Garcia /* free the skb's in the tx ring */ 2862c5aff182SThomas Petazzoni for (queue = 0; queue < txq_number; queue++) 2863c5aff182SThomas Petazzoni mvneta_txq_done_force(pp, &pp->txqs[queue]); 2864c5aff182SThomas Petazzoni 2865c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_PORT_TX_RESET, MVNETA_PORT_TX_DMA_RESET); 2866c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_PORT_TX_RESET, 0); 2867c5aff182SThomas Petazzoni } 2868c5aff182SThomas Petazzoni 2869c5aff182SThomas Petazzoni static void mvneta_rx_reset(struct mvneta_port *pp) 2870c5aff182SThomas Petazzoni { 2871c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_PORT_RX_RESET, MVNETA_PORT_RX_DMA_RESET); 2872c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_PORT_RX_RESET, 0); 2873c5aff182SThomas Petazzoni } 2874c5aff182SThomas Petazzoni 2875c5aff182SThomas Petazzoni /* Rx/Tx queue initialization/cleanup methods */ 2876c5aff182SThomas Petazzoni 28774a188a63SJisheng Zhang static int mvneta_rxq_sw_init(struct mvneta_port *pp, 2878c5aff182SThomas Petazzoni struct mvneta_rx_queue *rxq) 2879c5aff182SThomas Petazzoni { 2880c5aff182SThomas Petazzoni rxq->size = pp->rx_ring_size; 2881c5aff182SThomas Petazzoni 2882c5aff182SThomas Petazzoni /* Allocate memory for RX descriptors */ 2883c5aff182SThomas Petazzoni rxq->descs = dma_alloc_coherent(pp->dev->dev.parent, 2884c5aff182SThomas Petazzoni rxq->size * MVNETA_DESC_ALIGNED_SIZE, 2885c5aff182SThomas Petazzoni &rxq->descs_phys, GFP_KERNEL); 2886f95936ccSMarkus Elfring if (!rxq->descs) 2887c5aff182SThomas Petazzoni return -ENOMEM; 2888c5aff182SThomas Petazzoni 2889c5aff182SThomas Petazzoni rxq->last_desc = rxq->size - 1; 2890c5aff182SThomas Petazzoni 28914a188a63SJisheng Zhang return 0; 28924a188a63SJisheng Zhang } 28934a188a63SJisheng Zhang 28944a188a63SJisheng Zhang static void mvneta_rxq_hw_init(struct mvneta_port *pp, 28954a188a63SJisheng Zhang struct mvneta_rx_queue *rxq) 28964a188a63SJisheng Zhang { 2897c5aff182SThomas Petazzoni /* Set Rx descriptors queue starting address */ 2898c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_RXQ_BASE_ADDR_REG(rxq->id), rxq->descs_phys); 2899c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_RXQ_SIZE_REG(rxq->id), rxq->size); 2900c5aff182SThomas Petazzoni 2901c5aff182SThomas Petazzoni /* Set coalescing pkts and time */ 2902c5aff182SThomas Petazzoni mvneta_rx_pkts_coal_set(pp, rxq, rxq->pkts_coal); 2903c5aff182SThomas Petazzoni mvneta_rx_time_coal_set(pp, rxq, rxq->time_coal); 2904c5aff182SThomas Petazzoni 2905dc35a10fSMarcin Wojtas if (!pp->bm_priv) { 2906562e2f46SYelena Krivosheev /* Set Offset */ 2907562e2f46SYelena Krivosheev mvneta_rxq_offset_set(pp, rxq, 0); 2908562e2f46SYelena Krivosheev mvneta_rxq_buf_size_set(pp, rxq, pp->frag_size); 2909c5aff182SThomas Petazzoni mvneta_rxq_bm_disable(pp, rxq); 2910e9f64999SGregory CLEMENT mvneta_rxq_fill(pp, rxq, rxq->size); 2911dc35a10fSMarcin Wojtas } else { 2912562e2f46SYelena Krivosheev /* Set Offset */ 2913562e2f46SYelena Krivosheev mvneta_rxq_offset_set(pp, rxq, 2914562e2f46SYelena Krivosheev NET_SKB_PAD - pp->rx_offset_correction); 2915562e2f46SYelena Krivosheev 2916dc35a10fSMarcin Wojtas mvneta_rxq_bm_enable(pp, rxq); 2917562e2f46SYelena Krivosheev /* Fill RXQ with buffers from RX pool */ 2918dc35a10fSMarcin Wojtas mvneta_rxq_long_pool_set(pp, rxq); 2919dc35a10fSMarcin Wojtas mvneta_rxq_short_pool_set(pp, rxq); 2920e9f64999SGregory CLEMENT mvneta_rxq_non_occup_desc_add(pp, rxq, rxq->size); 2921dc35a10fSMarcin Wojtas } 29224a188a63SJisheng Zhang } 29234a188a63SJisheng Zhang 29244a188a63SJisheng Zhang /* Create a specified RX queue */ 29254a188a63SJisheng Zhang static int mvneta_rxq_init(struct mvneta_port *pp, 29264a188a63SJisheng Zhang struct mvneta_rx_queue *rxq) 29274a188a63SJisheng Zhang 29284a188a63SJisheng Zhang { 29294a188a63SJisheng Zhang int ret; 29304a188a63SJisheng Zhang 29314a188a63SJisheng Zhang ret = mvneta_rxq_sw_init(pp, rxq); 29324a188a63SJisheng Zhang if (ret < 0) 29334a188a63SJisheng Zhang return ret; 29344a188a63SJisheng Zhang 29354a188a63SJisheng Zhang mvneta_rxq_hw_init(pp, rxq); 2936dc35a10fSMarcin Wojtas 2937c5aff182SThomas Petazzoni return 0; 2938c5aff182SThomas Petazzoni } 2939c5aff182SThomas Petazzoni 2940c5aff182SThomas Petazzoni /* Cleanup Rx queue */ 2941c5aff182SThomas Petazzoni static void mvneta_rxq_deinit(struct mvneta_port *pp, 2942c5aff182SThomas Petazzoni struct mvneta_rx_queue *rxq) 2943c5aff182SThomas Petazzoni { 2944c5aff182SThomas Petazzoni mvneta_rxq_drop_pkts(pp, rxq); 2945c5aff182SThomas Petazzoni 2946562e2f46SYelena Krivosheev if (rxq->skb) 2947562e2f46SYelena Krivosheev dev_kfree_skb_any(rxq->skb); 2948562e2f46SYelena Krivosheev 2949c5aff182SThomas Petazzoni if (rxq->descs) 2950c5aff182SThomas Petazzoni dma_free_coherent(pp->dev->dev.parent, 2951c5aff182SThomas Petazzoni rxq->size * MVNETA_DESC_ALIGNED_SIZE, 2952c5aff182SThomas Petazzoni rxq->descs, 2953c5aff182SThomas Petazzoni rxq->descs_phys); 2954c5aff182SThomas Petazzoni 2955c5aff182SThomas Petazzoni rxq->descs = NULL; 2956c5aff182SThomas Petazzoni rxq->last_desc = 0; 2957c5aff182SThomas Petazzoni rxq->next_desc_to_proc = 0; 2958c5aff182SThomas Petazzoni rxq->descs_phys = 0; 2959562e2f46SYelena Krivosheev rxq->first_to_refill = 0; 2960562e2f46SYelena Krivosheev rxq->refill_num = 0; 2961562e2f46SYelena Krivosheev rxq->skb = NULL; 2962562e2f46SYelena Krivosheev rxq->left_size = 0; 2963c5aff182SThomas Petazzoni } 2964c5aff182SThomas Petazzoni 29654a188a63SJisheng Zhang static int mvneta_txq_sw_init(struct mvneta_port *pp, 2966c5aff182SThomas Petazzoni struct mvneta_tx_queue *txq) 2967c5aff182SThomas Petazzoni { 296850bf8cb6SGregory CLEMENT int cpu; 296950bf8cb6SGregory CLEMENT 2970c5aff182SThomas Petazzoni txq->size = pp->tx_ring_size; 2971c5aff182SThomas Petazzoni 29728eef5f97SEzequiel Garcia /* A queue must always have room for at least one skb. 29738eef5f97SEzequiel Garcia * Therefore, stop the queue when the free entries reaches 29748eef5f97SEzequiel Garcia * the maximum number of descriptors per skb. 29758eef5f97SEzequiel Garcia */ 29768eef5f97SEzequiel Garcia txq->tx_stop_threshold = txq->size - MVNETA_MAX_SKB_DESCS; 29778eef5f97SEzequiel Garcia txq->tx_wake_threshold = txq->tx_stop_threshold / 2; 29788eef5f97SEzequiel Garcia 2979c5aff182SThomas Petazzoni /* Allocate memory for TX descriptors */ 2980c5aff182SThomas Petazzoni txq->descs = dma_alloc_coherent(pp->dev->dev.parent, 2981c5aff182SThomas Petazzoni txq->size * MVNETA_DESC_ALIGNED_SIZE, 2982c5aff182SThomas Petazzoni &txq->descs_phys, GFP_KERNEL); 2983f95936ccSMarkus Elfring if (!txq->descs) 2984c5aff182SThomas Petazzoni return -ENOMEM; 2985c5aff182SThomas Petazzoni 2986c5aff182SThomas Petazzoni txq->last_desc = txq->size - 1; 2987c5aff182SThomas Petazzoni 2988d441b688SMarkus Elfring txq->tx_skb = kmalloc_array(txq->size, sizeof(*txq->tx_skb), 2989d441b688SMarkus Elfring GFP_KERNEL); 2990f95936ccSMarkus Elfring if (!txq->tx_skb) { 2991c5aff182SThomas Petazzoni dma_free_coherent(pp->dev->dev.parent, 2992c5aff182SThomas Petazzoni txq->size * MVNETA_DESC_ALIGNED_SIZE, 2993c5aff182SThomas Petazzoni txq->descs, txq->descs_phys); 2994c5aff182SThomas Petazzoni return -ENOMEM; 2995c5aff182SThomas Petazzoni } 29962adb719dSEzequiel Garcia 29972adb719dSEzequiel Garcia /* Allocate DMA buffers for TSO MAC/IP/TCP headers */ 29982adb719dSEzequiel Garcia txq->tso_hdrs = dma_alloc_coherent(pp->dev->dev.parent, 29992adb719dSEzequiel Garcia txq->size * TSO_HEADER_SIZE, 30002adb719dSEzequiel Garcia &txq->tso_hdrs_phys, GFP_KERNEL); 3001f95936ccSMarkus Elfring if (!txq->tso_hdrs) { 30022adb719dSEzequiel Garcia kfree(txq->tx_skb); 30032adb719dSEzequiel Garcia dma_free_coherent(pp->dev->dev.parent, 30042adb719dSEzequiel Garcia txq->size * MVNETA_DESC_ALIGNED_SIZE, 30052adb719dSEzequiel Garcia txq->descs, txq->descs_phys); 30062adb719dSEzequiel Garcia return -ENOMEM; 30072adb719dSEzequiel Garcia } 3008c5aff182SThomas Petazzoni 300950bf8cb6SGregory CLEMENT /* Setup XPS mapping */ 301050bf8cb6SGregory CLEMENT if (txq_number > 1) 301150bf8cb6SGregory CLEMENT cpu = txq->id % num_present_cpus(); 301250bf8cb6SGregory CLEMENT else 301350bf8cb6SGregory CLEMENT cpu = pp->rxq_def % num_present_cpus(); 301450bf8cb6SGregory CLEMENT cpumask_set_cpu(cpu, &txq->affinity_mask); 301550bf8cb6SGregory CLEMENT netif_set_xps_queue(pp->dev, &txq->affinity_mask, txq->id); 301650bf8cb6SGregory CLEMENT 3017c5aff182SThomas Petazzoni return 0; 3018c5aff182SThomas Petazzoni } 3019c5aff182SThomas Petazzoni 30204a188a63SJisheng Zhang static void mvneta_txq_hw_init(struct mvneta_port *pp, 30214a188a63SJisheng Zhang struct mvneta_tx_queue *txq) 30224a188a63SJisheng Zhang { 30234a188a63SJisheng Zhang /* Set maximum bandwidth for enabled TXQs */ 30244a188a63SJisheng Zhang mvreg_write(pp, MVETH_TXQ_TOKEN_CFG_REG(txq->id), 0x03ffffff); 30254a188a63SJisheng Zhang mvreg_write(pp, MVETH_TXQ_TOKEN_COUNT_REG(txq->id), 0x3fffffff); 30264a188a63SJisheng Zhang 30274a188a63SJisheng Zhang /* Set Tx descriptors queue starting address */ 30284a188a63SJisheng Zhang mvreg_write(pp, MVNETA_TXQ_BASE_ADDR_REG(txq->id), txq->descs_phys); 30294a188a63SJisheng Zhang mvreg_write(pp, MVNETA_TXQ_SIZE_REG(txq->id), txq->size); 30304a188a63SJisheng Zhang 30314a188a63SJisheng Zhang mvneta_tx_done_pkts_coal_set(pp, txq, txq->done_pkts_coal); 30324a188a63SJisheng Zhang } 30334a188a63SJisheng Zhang 30344a188a63SJisheng Zhang /* Create and initialize a tx queue */ 30354a188a63SJisheng Zhang static int mvneta_txq_init(struct mvneta_port *pp, 30364a188a63SJisheng Zhang struct mvneta_tx_queue *txq) 30374a188a63SJisheng Zhang { 30384a188a63SJisheng Zhang int ret; 30394a188a63SJisheng Zhang 30404a188a63SJisheng Zhang ret = mvneta_txq_sw_init(pp, txq); 30414a188a63SJisheng Zhang if (ret < 0) 30424a188a63SJisheng Zhang return ret; 30434a188a63SJisheng Zhang 30444a188a63SJisheng Zhang mvneta_txq_hw_init(pp, txq); 30454a188a63SJisheng Zhang 30464a188a63SJisheng Zhang return 0; 30474a188a63SJisheng Zhang } 30484a188a63SJisheng Zhang 3049c5aff182SThomas Petazzoni /* Free allocated resources when mvneta_txq_init() fails to allocate memory*/ 30504a188a63SJisheng Zhang static void mvneta_txq_sw_deinit(struct mvneta_port *pp, 3051c5aff182SThomas Petazzoni struct mvneta_tx_queue *txq) 3052c5aff182SThomas Petazzoni { 3053a29b6235SMarcin Wojtas struct netdev_queue *nq = netdev_get_tx_queue(pp->dev, txq->id); 3054a29b6235SMarcin Wojtas 3055c5aff182SThomas Petazzoni kfree(txq->tx_skb); 3056c5aff182SThomas Petazzoni 30572adb719dSEzequiel Garcia if (txq->tso_hdrs) 30582adb719dSEzequiel Garcia dma_free_coherent(pp->dev->dev.parent, 30592adb719dSEzequiel Garcia txq->size * TSO_HEADER_SIZE, 30602adb719dSEzequiel Garcia txq->tso_hdrs, txq->tso_hdrs_phys); 3061c5aff182SThomas Petazzoni if (txq->descs) 3062c5aff182SThomas Petazzoni dma_free_coherent(pp->dev->dev.parent, 3063c5aff182SThomas Petazzoni txq->size * MVNETA_DESC_ALIGNED_SIZE, 3064c5aff182SThomas Petazzoni txq->descs, txq->descs_phys); 3065c5aff182SThomas Petazzoni 3066a29b6235SMarcin Wojtas netdev_tx_reset_queue(nq); 3067a29b6235SMarcin Wojtas 3068c5aff182SThomas Petazzoni txq->descs = NULL; 3069c5aff182SThomas Petazzoni txq->last_desc = 0; 3070c5aff182SThomas Petazzoni txq->next_desc_to_proc = 0; 3071c5aff182SThomas Petazzoni txq->descs_phys = 0; 30724a188a63SJisheng Zhang } 3073c5aff182SThomas Petazzoni 30744a188a63SJisheng Zhang static void mvneta_txq_hw_deinit(struct mvneta_port *pp, 30754a188a63SJisheng Zhang struct mvneta_tx_queue *txq) 30764a188a63SJisheng Zhang { 3077c5aff182SThomas Petazzoni /* Set minimum bandwidth for disabled TXQs */ 3078c5aff182SThomas Petazzoni mvreg_write(pp, MVETH_TXQ_TOKEN_CFG_REG(txq->id), 0); 3079c5aff182SThomas Petazzoni mvreg_write(pp, MVETH_TXQ_TOKEN_COUNT_REG(txq->id), 0); 3080c5aff182SThomas Petazzoni 3081c5aff182SThomas Petazzoni /* Set Tx descriptors queue starting address and size */ 3082c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_TXQ_BASE_ADDR_REG(txq->id), 0); 3083c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_TXQ_SIZE_REG(txq->id), 0); 3084c5aff182SThomas Petazzoni } 3085c5aff182SThomas Petazzoni 30864a188a63SJisheng Zhang static void mvneta_txq_deinit(struct mvneta_port *pp, 30874a188a63SJisheng Zhang struct mvneta_tx_queue *txq) 30884a188a63SJisheng Zhang { 30894a188a63SJisheng Zhang mvneta_txq_sw_deinit(pp, txq); 30904a188a63SJisheng Zhang mvneta_txq_hw_deinit(pp, txq); 30914a188a63SJisheng Zhang } 30924a188a63SJisheng Zhang 3093c5aff182SThomas Petazzoni /* Cleanup all Tx queues */ 3094c5aff182SThomas Petazzoni static void mvneta_cleanup_txqs(struct mvneta_port *pp) 3095c5aff182SThomas Petazzoni { 3096c5aff182SThomas Petazzoni int queue; 3097c5aff182SThomas Petazzoni 3098c5aff182SThomas Petazzoni for (queue = 0; queue < txq_number; queue++) 3099c5aff182SThomas Petazzoni mvneta_txq_deinit(pp, &pp->txqs[queue]); 3100c5aff182SThomas Petazzoni } 3101c5aff182SThomas Petazzoni 3102c5aff182SThomas Petazzoni /* Cleanup all Rx queues */ 3103c5aff182SThomas Petazzoni static void mvneta_cleanup_rxqs(struct mvneta_port *pp) 3104c5aff182SThomas Petazzoni { 31052dcf75e2SGregory CLEMENT int queue; 31062dcf75e2SGregory CLEMENT 3107ca5902a6SYelena Krivosheev for (queue = 0; queue < rxq_number; queue++) 31082dcf75e2SGregory CLEMENT mvneta_rxq_deinit(pp, &pp->rxqs[queue]); 3109c5aff182SThomas Petazzoni } 3110c5aff182SThomas Petazzoni 3111c5aff182SThomas Petazzoni 3112c5aff182SThomas Petazzoni /* Init all Rx queues */ 3113c5aff182SThomas Petazzoni static int mvneta_setup_rxqs(struct mvneta_port *pp) 3114c5aff182SThomas Petazzoni { 31152dcf75e2SGregory CLEMENT int queue; 31162dcf75e2SGregory CLEMENT 31172dcf75e2SGregory CLEMENT for (queue = 0; queue < rxq_number; queue++) { 31182dcf75e2SGregory CLEMENT int err = mvneta_rxq_init(pp, &pp->rxqs[queue]); 31192dcf75e2SGregory CLEMENT 3120c5aff182SThomas Petazzoni if (err) { 3121c5aff182SThomas Petazzoni netdev_err(pp->dev, "%s: can't create rxq=%d\n", 31222dcf75e2SGregory CLEMENT __func__, queue); 3123c5aff182SThomas Petazzoni mvneta_cleanup_rxqs(pp); 3124c5aff182SThomas Petazzoni return err; 3125c5aff182SThomas Petazzoni } 31262dcf75e2SGregory CLEMENT } 3127c5aff182SThomas Petazzoni 3128c5aff182SThomas Petazzoni return 0; 3129c5aff182SThomas Petazzoni } 3130c5aff182SThomas Petazzoni 3131c5aff182SThomas Petazzoni /* Init all tx queues */ 3132c5aff182SThomas Petazzoni static int mvneta_setup_txqs(struct mvneta_port *pp) 3133c5aff182SThomas Petazzoni { 3134c5aff182SThomas Petazzoni int queue; 3135c5aff182SThomas Petazzoni 3136c5aff182SThomas Petazzoni for (queue = 0; queue < txq_number; queue++) { 3137c5aff182SThomas Petazzoni int err = mvneta_txq_init(pp, &pp->txqs[queue]); 3138c5aff182SThomas Petazzoni if (err) { 3139c5aff182SThomas Petazzoni netdev_err(pp->dev, "%s: can't create txq=%d\n", 3140c5aff182SThomas Petazzoni __func__, queue); 3141c5aff182SThomas Petazzoni mvneta_cleanup_txqs(pp); 3142c5aff182SThomas Petazzoni return err; 3143c5aff182SThomas Petazzoni } 3144c5aff182SThomas Petazzoni } 3145c5aff182SThomas Petazzoni 3146c5aff182SThomas Petazzoni return 0; 3147c5aff182SThomas Petazzoni } 3148c5aff182SThomas Petazzoni 3149c5aff182SThomas Petazzoni static void mvneta_start_dev(struct mvneta_port *pp) 3150c5aff182SThomas Petazzoni { 31516b125d63SGregory CLEMENT int cpu; 315212bb03b4SMaxime Ripard 3153c5aff182SThomas Petazzoni mvneta_max_rx_size_set(pp, pp->pkt_size); 3154c5aff182SThomas Petazzoni mvneta_txq_max_tx_size_set(pp, pp->pkt_size); 3155c5aff182SThomas Petazzoni 3156c5aff182SThomas Petazzoni /* start the Rx/Tx activity */ 3157c5aff182SThomas Petazzoni mvneta_port_enable(pp); 3158c5aff182SThomas Petazzoni 31592636ac3cSMarcin Wojtas if (!pp->neta_armada3700) { 3160c5aff182SThomas Petazzoni /* Enable polling on the port */ 3161129219e4SGregory CLEMENT for_each_online_cpu(cpu) { 31622636ac3cSMarcin Wojtas struct mvneta_pcpu_port *port = 31632636ac3cSMarcin Wojtas per_cpu_ptr(pp->ports, cpu); 316412bb03b4SMaxime Ripard 316512bb03b4SMaxime Ripard napi_enable(&port->napi); 316612bb03b4SMaxime Ripard } 31672636ac3cSMarcin Wojtas } else { 31682636ac3cSMarcin Wojtas napi_enable(&pp->napi); 31692636ac3cSMarcin Wojtas } 3170c5aff182SThomas Petazzoni 31712dcf75e2SGregory CLEMENT /* Unmask interrupts. It has to be done from each CPU */ 31726b125d63SGregory CLEMENT on_each_cpu(mvneta_percpu_unmask_interrupt, pp, true); 31736b125d63SGregory CLEMENT 3174898b2970SStas Sergeev mvreg_write(pp, MVNETA_INTR_MISC_MASK, 3175898b2970SStas Sergeev MVNETA_CAUSE_PHY_STATUS_CHANGE | 3176856b2cc5SRussell King MVNETA_CAUSE_LINK_CHANGE); 3177c5aff182SThomas Petazzoni 3178503f9aa9SRussell King phylink_start(pp->phylink); 3179c5aff182SThomas Petazzoni netif_tx_start_all_queues(pp->dev); 3180c5aff182SThomas Petazzoni } 3181c5aff182SThomas Petazzoni 3182c5aff182SThomas Petazzoni static void mvneta_stop_dev(struct mvneta_port *pp) 3183c5aff182SThomas Petazzoni { 318412bb03b4SMaxime Ripard unsigned int cpu; 318512bb03b4SMaxime Ripard 3186503f9aa9SRussell King phylink_stop(pp->phylink); 3187c5aff182SThomas Petazzoni 31882636ac3cSMarcin Wojtas if (!pp->neta_armada3700) { 3189129219e4SGregory CLEMENT for_each_online_cpu(cpu) { 31902636ac3cSMarcin Wojtas struct mvneta_pcpu_port *port = 31912636ac3cSMarcin Wojtas per_cpu_ptr(pp->ports, cpu); 319212bb03b4SMaxime Ripard 319312bb03b4SMaxime Ripard napi_disable(&port->napi); 319412bb03b4SMaxime Ripard } 31952636ac3cSMarcin Wojtas } else { 31962636ac3cSMarcin Wojtas napi_disable(&pp->napi); 31972636ac3cSMarcin Wojtas } 3198c5aff182SThomas Petazzoni 3199c5aff182SThomas Petazzoni netif_carrier_off(pp->dev); 3200c5aff182SThomas Petazzoni 3201c5aff182SThomas Petazzoni mvneta_port_down(pp); 3202c5aff182SThomas Petazzoni netif_tx_stop_all_queues(pp->dev); 3203c5aff182SThomas Petazzoni 3204c5aff182SThomas Petazzoni /* Stop the port activity */ 3205c5aff182SThomas Petazzoni mvneta_port_disable(pp); 3206c5aff182SThomas Petazzoni 3207c5aff182SThomas Petazzoni /* Clear all ethernet port interrupts */ 3208db488c10SGregory CLEMENT on_each_cpu(mvneta_percpu_clear_intr_cause, pp, true); 3209c5aff182SThomas Petazzoni 3210c5aff182SThomas Petazzoni /* Mask all ethernet port interrupts */ 3211db488c10SGregory CLEMENT on_each_cpu(mvneta_percpu_mask_interrupt, pp, true); 3212c5aff182SThomas Petazzoni 3213c5aff182SThomas Petazzoni mvneta_tx_reset(pp); 3214c5aff182SThomas Petazzoni mvneta_rx_reset(pp); 3215c5aff182SThomas Petazzoni } 3216c5aff182SThomas Petazzoni 3217db5dd0dbSMarcin Wojtas static void mvneta_percpu_enable(void *arg) 3218db5dd0dbSMarcin Wojtas { 3219db5dd0dbSMarcin Wojtas struct mvneta_port *pp = arg; 3220db5dd0dbSMarcin Wojtas 3221db5dd0dbSMarcin Wojtas enable_percpu_irq(pp->dev->irq, IRQ_TYPE_NONE); 3222db5dd0dbSMarcin Wojtas } 3223db5dd0dbSMarcin Wojtas 3224db5dd0dbSMarcin Wojtas static void mvneta_percpu_disable(void *arg) 3225db5dd0dbSMarcin Wojtas { 3226db5dd0dbSMarcin Wojtas struct mvneta_port *pp = arg; 3227db5dd0dbSMarcin Wojtas 3228db5dd0dbSMarcin Wojtas disable_percpu_irq(pp->dev->irq); 3229db5dd0dbSMarcin Wojtas } 3230db5dd0dbSMarcin Wojtas 3231c5aff182SThomas Petazzoni /* Change the device mtu */ 3232c5aff182SThomas Petazzoni static int mvneta_change_mtu(struct net_device *dev, int mtu) 3233c5aff182SThomas Petazzoni { 3234c5aff182SThomas Petazzoni struct mvneta_port *pp = netdev_priv(dev); 3235c5aff182SThomas Petazzoni int ret; 3236c5aff182SThomas Petazzoni 32375777987eSJarod Wilson if (!IS_ALIGNED(MVNETA_RX_PKT_SIZE(mtu), 8)) { 32385777987eSJarod Wilson netdev_info(dev, "Illegal MTU value %d, rounding to %d\n", 32395777987eSJarod Wilson mtu, ALIGN(MVNETA_RX_PKT_SIZE(mtu), 8)); 32405777987eSJarod Wilson mtu = ALIGN(MVNETA_RX_PKT_SIZE(mtu), 8); 32415777987eSJarod Wilson } 3242c5aff182SThomas Petazzoni 3243c5aff182SThomas Petazzoni dev->mtu = mtu; 3244c5aff182SThomas Petazzoni 3245b65657fcSSimon Guinot if (!netif_running(dev)) { 3246dc35a10fSMarcin Wojtas if (pp->bm_priv) 3247dc35a10fSMarcin Wojtas mvneta_bm_update_mtu(pp, mtu); 3248dc35a10fSMarcin Wojtas 3249b65657fcSSimon Guinot netdev_update_features(dev); 3250c5aff182SThomas Petazzoni return 0; 3251b65657fcSSimon Guinot } 3252c5aff182SThomas Petazzoni 32536a20c175SThomas Petazzoni /* The interface is running, so we have to force a 3254a92dbd96SEzequiel Garcia * reallocation of the queues 3255c5aff182SThomas Petazzoni */ 3256c5aff182SThomas Petazzoni mvneta_stop_dev(pp); 3257db5dd0dbSMarcin Wojtas on_each_cpu(mvneta_percpu_disable, pp, true); 3258c5aff182SThomas Petazzoni 3259c5aff182SThomas Petazzoni mvneta_cleanup_txqs(pp); 3260c5aff182SThomas Petazzoni mvneta_cleanup_rxqs(pp); 3261c5aff182SThomas Petazzoni 3262dc35a10fSMarcin Wojtas if (pp->bm_priv) 3263dc35a10fSMarcin Wojtas mvneta_bm_update_mtu(pp, mtu); 3264dc35a10fSMarcin Wojtas 3265a92dbd96SEzequiel Garcia pp->pkt_size = MVNETA_RX_PKT_SIZE(dev->mtu); 3266c5aff182SThomas Petazzoni 3267c5aff182SThomas Petazzoni ret = mvneta_setup_rxqs(pp); 3268c5aff182SThomas Petazzoni if (ret) { 3269a92dbd96SEzequiel Garcia netdev_err(dev, "unable to setup rxqs after MTU change\n"); 3270c5aff182SThomas Petazzoni return ret; 3271c5aff182SThomas Petazzoni } 3272c5aff182SThomas Petazzoni 3273a92dbd96SEzequiel Garcia ret = mvneta_setup_txqs(pp); 3274a92dbd96SEzequiel Garcia if (ret) { 3275a92dbd96SEzequiel Garcia netdev_err(dev, "unable to setup txqs after MTU change\n"); 3276a92dbd96SEzequiel Garcia return ret; 3277a92dbd96SEzequiel Garcia } 3278c5aff182SThomas Petazzoni 3279db5dd0dbSMarcin Wojtas on_each_cpu(mvneta_percpu_enable, pp, true); 3280c5aff182SThomas Petazzoni mvneta_start_dev(pp); 3281c5aff182SThomas Petazzoni 3282b65657fcSSimon Guinot netdev_update_features(dev); 3283b65657fcSSimon Guinot 3284c5aff182SThomas Petazzoni return 0; 3285c5aff182SThomas Petazzoni } 3286c5aff182SThomas Petazzoni 3287b65657fcSSimon Guinot static netdev_features_t mvneta_fix_features(struct net_device *dev, 3288b65657fcSSimon Guinot netdev_features_t features) 3289b65657fcSSimon Guinot { 3290b65657fcSSimon Guinot struct mvneta_port *pp = netdev_priv(dev); 3291b65657fcSSimon Guinot 3292b65657fcSSimon Guinot if (pp->tx_csum_limit && dev->mtu > pp->tx_csum_limit) { 3293b65657fcSSimon Guinot features &= ~(NETIF_F_IP_CSUM | NETIF_F_TSO); 3294b65657fcSSimon Guinot netdev_info(dev, 3295b65657fcSSimon Guinot "Disable IP checksum for MTU greater than %dB\n", 3296b65657fcSSimon Guinot pp->tx_csum_limit); 3297b65657fcSSimon Guinot } 3298b65657fcSSimon Guinot 3299b65657fcSSimon Guinot return features; 3300b65657fcSSimon Guinot } 3301b65657fcSSimon Guinot 33028cc3e439SThomas Petazzoni /* Get mac address */ 33038cc3e439SThomas Petazzoni static void mvneta_get_mac_addr(struct mvneta_port *pp, unsigned char *addr) 33048cc3e439SThomas Petazzoni { 33058cc3e439SThomas Petazzoni u32 mac_addr_l, mac_addr_h; 33068cc3e439SThomas Petazzoni 33078cc3e439SThomas Petazzoni mac_addr_l = mvreg_read(pp, MVNETA_MAC_ADDR_LOW); 33088cc3e439SThomas Petazzoni mac_addr_h = mvreg_read(pp, MVNETA_MAC_ADDR_HIGH); 33098cc3e439SThomas Petazzoni addr[0] = (mac_addr_h >> 24) & 0xFF; 33108cc3e439SThomas Petazzoni addr[1] = (mac_addr_h >> 16) & 0xFF; 33118cc3e439SThomas Petazzoni addr[2] = (mac_addr_h >> 8) & 0xFF; 33128cc3e439SThomas Petazzoni addr[3] = mac_addr_h & 0xFF; 33138cc3e439SThomas Petazzoni addr[4] = (mac_addr_l >> 8) & 0xFF; 33148cc3e439SThomas Petazzoni addr[5] = mac_addr_l & 0xFF; 33158cc3e439SThomas Petazzoni } 33168cc3e439SThomas Petazzoni 3317c5aff182SThomas Petazzoni /* Handle setting mac address */ 3318c5aff182SThomas Petazzoni static int mvneta_set_mac_addr(struct net_device *dev, void *addr) 3319c5aff182SThomas Petazzoni { 3320c5aff182SThomas Petazzoni struct mvneta_port *pp = netdev_priv(dev); 3321e68de360SEzequiel Garcia struct sockaddr *sockaddr = addr; 3322e68de360SEzequiel Garcia int ret; 3323c5aff182SThomas Petazzoni 3324e68de360SEzequiel Garcia ret = eth_prepare_mac_addr_change(dev, addr); 3325e68de360SEzequiel Garcia if (ret < 0) 3326e68de360SEzequiel Garcia return ret; 3327c5aff182SThomas Petazzoni /* Remove previous address table entry */ 3328c5aff182SThomas Petazzoni mvneta_mac_addr_set(pp, dev->dev_addr, -1); 3329c5aff182SThomas Petazzoni 3330c5aff182SThomas Petazzoni /* Set new addr in hw */ 333190b74c01SGregory CLEMENT mvneta_mac_addr_set(pp, sockaddr->sa_data, pp->rxq_def); 3332c5aff182SThomas Petazzoni 3333e68de360SEzequiel Garcia eth_commit_mac_addr_change(dev, addr); 3334c5aff182SThomas Petazzoni return 0; 3335c5aff182SThomas Petazzoni } 3336c5aff182SThomas Petazzoni 3337503f9aa9SRussell King static void mvneta_validate(struct net_device *ndev, unsigned long *supported, 3338503f9aa9SRussell King struct phylink_link_state *state) 3339503f9aa9SRussell King { 3340503f9aa9SRussell King __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, }; 3341503f9aa9SRussell King 334222f4bf8aSRussell King /* We only support QSGMII, SGMII, 802.3z and RGMII modes */ 3343503f9aa9SRussell King if (state->interface != PHY_INTERFACE_MODE_NA && 3344503f9aa9SRussell King state->interface != PHY_INTERFACE_MODE_QSGMII && 3345503f9aa9SRussell King state->interface != PHY_INTERFACE_MODE_SGMII && 334622f4bf8aSRussell King !phy_interface_mode_is_8023z(state->interface) && 3347503f9aa9SRussell King !phy_interface_mode_is_rgmii(state->interface)) { 3348503f9aa9SRussell King bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS); 3349503f9aa9SRussell King return; 3350503f9aa9SRussell King } 3351503f9aa9SRussell King 3352503f9aa9SRussell King /* Allow all the expected bits */ 3353503f9aa9SRussell King phylink_set(mask, Autoneg); 3354503f9aa9SRussell King phylink_set_port_modes(mask); 3355503f9aa9SRussell King 33564932a918SRussell King /* Asymmetric pause is unsupported */ 33574932a918SRussell King phylink_set(mask, Pause); 3358da58a931SMaxime Chevallier 335983e65df6SMaxime Chevallier /* Half-duplex at speeds higher than 100Mbit is unsupported */ 3360503f9aa9SRussell King phylink_set(mask, 1000baseT_Full); 3361503f9aa9SRussell King phylink_set(mask, 1000baseX_Full); 336222f4bf8aSRussell King 336322f4bf8aSRussell King if (!phy_interface_mode_is_8023z(state->interface)) { 336422f4bf8aSRussell King /* 10M and 100M are only supported in non-802.3z mode */ 3365503f9aa9SRussell King phylink_set(mask, 10baseT_Half); 3366503f9aa9SRussell King phylink_set(mask, 10baseT_Full); 3367503f9aa9SRussell King phylink_set(mask, 100baseT_Half); 3368503f9aa9SRussell King phylink_set(mask, 100baseT_Full); 336922f4bf8aSRussell King } 3370503f9aa9SRussell King 3371503f9aa9SRussell King bitmap_and(supported, supported, mask, 3372503f9aa9SRussell King __ETHTOOL_LINK_MODE_MASK_NBITS); 3373503f9aa9SRussell King bitmap_and(state->advertising, state->advertising, mask, 3374503f9aa9SRussell King __ETHTOOL_LINK_MODE_MASK_NBITS); 3375503f9aa9SRussell King } 3376503f9aa9SRussell King 3377503f9aa9SRussell King static int mvneta_mac_link_state(struct net_device *ndev, 3378503f9aa9SRussell King struct phylink_link_state *state) 3379c5aff182SThomas Petazzoni { 3380c5aff182SThomas Petazzoni struct mvneta_port *pp = netdev_priv(ndev); 3381503f9aa9SRussell King u32 gmac_stat; 3382c5aff182SThomas Petazzoni 3383503f9aa9SRussell King gmac_stat = mvreg_read(pp, MVNETA_GMAC_STATUS); 3384503f9aa9SRussell King 3385503f9aa9SRussell King if (gmac_stat & MVNETA_GMAC_SPEED_1000) 3386503f9aa9SRussell King state->speed = SPEED_1000; 3387503f9aa9SRussell King else if (gmac_stat & MVNETA_GMAC_SPEED_100) 3388503f9aa9SRussell King state->speed = SPEED_100; 3389503f9aa9SRussell King else 3390503f9aa9SRussell King state->speed = SPEED_10; 3391503f9aa9SRussell King 3392503f9aa9SRussell King state->an_complete = !!(gmac_stat & MVNETA_GMAC_AN_COMPLETE); 3393503f9aa9SRussell King state->link = !!(gmac_stat & MVNETA_GMAC_LINK_UP); 3394503f9aa9SRussell King state->duplex = !!(gmac_stat & MVNETA_GMAC_FULL_DUPLEX); 3395503f9aa9SRussell King 3396503f9aa9SRussell King state->pause = 0; 33974932a918SRussell King if (gmac_stat & MVNETA_GMAC_RX_FLOW_CTRL_ENABLE) 33984932a918SRussell King state->pause |= MLO_PAUSE_RX; 33994932a918SRussell King if (gmac_stat & MVNETA_GMAC_TX_FLOW_CTRL_ENABLE) 34004932a918SRussell King state->pause |= MLO_PAUSE_TX; 3401503f9aa9SRussell King 3402503f9aa9SRussell King return 1; 3403503f9aa9SRussell King } 3404503f9aa9SRussell King 340522f4bf8aSRussell King static void mvneta_mac_an_restart(struct net_device *ndev) 340622f4bf8aSRussell King { 340722f4bf8aSRussell King struct mvneta_port *pp = netdev_priv(ndev); 340822f4bf8aSRussell King u32 gmac_an = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG); 340922f4bf8aSRussell King 341022f4bf8aSRussell King mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, 341122f4bf8aSRussell King gmac_an | MVNETA_GMAC_INBAND_RESTART_AN); 341222f4bf8aSRussell King mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, 341322f4bf8aSRussell King gmac_an & ~MVNETA_GMAC_INBAND_RESTART_AN); 341422f4bf8aSRussell King } 341522f4bf8aSRussell King 3416503f9aa9SRussell King static void mvneta_mac_config(struct net_device *ndev, unsigned int mode, 3417503f9aa9SRussell King const struct phylink_link_state *state) 3418503f9aa9SRussell King { 3419503f9aa9SRussell King struct mvneta_port *pp = netdev_priv(ndev); 342022f4bf8aSRussell King u32 new_ctrl0, gmac_ctrl0 = mvreg_read(pp, MVNETA_GMAC_CTRL_0); 3421503f9aa9SRussell King u32 new_ctrl2, gmac_ctrl2 = mvreg_read(pp, MVNETA_GMAC_CTRL_2); 3422da58a931SMaxime Chevallier u32 new_ctrl4, gmac_ctrl4 = mvreg_read(pp, MVNETA_GMAC_CTRL_4); 3423503f9aa9SRussell King u32 new_clk, gmac_clk = mvreg_read(pp, MVNETA_GMAC_CLOCK_DIVIDER); 3424503f9aa9SRussell King u32 new_an, gmac_an = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG); 3425503f9aa9SRussell King 342622f4bf8aSRussell King new_ctrl0 = gmac_ctrl0 & ~MVNETA_GMAC0_PORT_1000BASE_X; 342732699954SRussell King new_ctrl2 = gmac_ctrl2 & ~(MVNETA_GMAC2_INBAND_AN_ENABLE | 342832699954SRussell King MVNETA_GMAC2_PORT_RESET); 3429da58a931SMaxime Chevallier new_ctrl4 = gmac_ctrl4 & ~(MVNETA_GMAC4_SHORT_PREAMBLE_ENABLE); 3430503f9aa9SRussell King new_clk = gmac_clk & ~MVNETA_GMAC_1MS_CLOCK_ENABLE; 3431503f9aa9SRussell King new_an = gmac_an & ~(MVNETA_GMAC_INBAND_AN_ENABLE | 3432503f9aa9SRussell King MVNETA_GMAC_INBAND_RESTART_AN | 3433503f9aa9SRussell King MVNETA_GMAC_CONFIG_MII_SPEED | 3434c5aff182SThomas Petazzoni MVNETA_GMAC_CONFIG_GMII_SPEED | 3435503f9aa9SRussell King MVNETA_GMAC_AN_SPEED_EN | 343622f4bf8aSRussell King MVNETA_GMAC_ADVERT_SYM_FLOW_CTRL | 343722f4bf8aSRussell King MVNETA_GMAC_CONFIG_FLOW_CTRL | 3438503f9aa9SRussell King MVNETA_GMAC_AN_FLOW_CTRL_EN | 3439503f9aa9SRussell King MVNETA_GMAC_CONFIG_FULL_DUPLEX | 3440503f9aa9SRussell King MVNETA_GMAC_AN_DUPLEX_EN); 3441c5aff182SThomas Petazzoni 344232699954SRussell King /* Even though it might look weird, when we're configured in 344332699954SRussell King * SGMII or QSGMII mode, the RGMII bit needs to be set. 344432699954SRussell King */ 344532699954SRussell King new_ctrl2 |= MVNETA_GMAC2_PORT_RGMII; 344632699954SRussell King 344732699954SRussell King if (state->interface == PHY_INTERFACE_MODE_QSGMII || 344822f4bf8aSRussell King state->interface == PHY_INTERFACE_MODE_SGMII || 344922f4bf8aSRussell King phy_interface_mode_is_8023z(state->interface)) 345032699954SRussell King new_ctrl2 |= MVNETA_GMAC2_PCS_ENABLE; 345132699954SRussell King 34524932a918SRussell King if (phylink_test(state->advertising, Pause)) 34534932a918SRussell King new_an |= MVNETA_GMAC_ADVERT_SYM_FLOW_CTRL; 34544932a918SRussell King if (state->pause & MLO_PAUSE_TXRX_MASK) 34554932a918SRussell King new_an |= MVNETA_GMAC_CONFIG_FLOW_CTRL; 34564932a918SRussell King 3457503f9aa9SRussell King if (!phylink_autoneg_inband(mode)) { 3458503f9aa9SRussell King /* Phy or fixed speed */ 3459503f9aa9SRussell King if (state->duplex) 3460503f9aa9SRussell King new_an |= MVNETA_GMAC_CONFIG_FULL_DUPLEX; 3461c5aff182SThomas Petazzoni 3462da58a931SMaxime Chevallier if (state->speed == SPEED_1000 || state->speed == SPEED_2500) 3463503f9aa9SRussell King new_an |= MVNETA_GMAC_CONFIG_GMII_SPEED; 3464503f9aa9SRussell King else if (state->speed == SPEED_100) 3465503f9aa9SRussell King new_an |= MVNETA_GMAC_CONFIG_MII_SPEED; 346622f4bf8aSRussell King } else if (state->interface == PHY_INTERFACE_MODE_SGMII) { 3467503f9aa9SRussell King /* SGMII mode receives the state from the PHY */ 3468503f9aa9SRussell King new_ctrl2 |= MVNETA_GMAC2_INBAND_AN_ENABLE; 3469503f9aa9SRussell King new_clk |= MVNETA_GMAC_1MS_CLOCK_ENABLE; 3470503f9aa9SRussell King new_an = (new_an & ~(MVNETA_GMAC_FORCE_LINK_DOWN | 3471503f9aa9SRussell King MVNETA_GMAC_FORCE_LINK_PASS)) | 3472503f9aa9SRussell King MVNETA_GMAC_INBAND_AN_ENABLE | 3473503f9aa9SRussell King MVNETA_GMAC_AN_SPEED_EN | 3474503f9aa9SRussell King MVNETA_GMAC_AN_DUPLEX_EN; 347522f4bf8aSRussell King } else { 347622f4bf8aSRussell King /* 802.3z negotiation - only 1000base-X */ 347722f4bf8aSRussell King new_ctrl0 |= MVNETA_GMAC0_PORT_1000BASE_X; 347822f4bf8aSRussell King new_clk |= MVNETA_GMAC_1MS_CLOCK_ENABLE; 347922f4bf8aSRussell King new_an = (new_an & ~(MVNETA_GMAC_FORCE_LINK_DOWN | 348022f4bf8aSRussell King MVNETA_GMAC_FORCE_LINK_PASS)) | 348122f4bf8aSRussell King MVNETA_GMAC_INBAND_AN_ENABLE | 348222f4bf8aSRussell King MVNETA_GMAC_CONFIG_GMII_SPEED | 348322f4bf8aSRussell King /* The MAC only supports FD mode */ 348422f4bf8aSRussell King MVNETA_GMAC_CONFIG_FULL_DUPLEX; 34854932a918SRussell King 34864932a918SRussell King if (state->pause & MLO_PAUSE_AN && state->an_enabled) 34874932a918SRussell King new_an |= MVNETA_GMAC_AN_FLOW_CTRL_EN; 3488c5aff182SThomas Petazzoni } 3489c5aff182SThomas Petazzoni 3490503f9aa9SRussell King /* Armada 370 documentation says we can only change the port mode 3491503f9aa9SRussell King * and in-band enable when the link is down, so force it down 3492503f9aa9SRussell King * while making these changes. We also do this for GMAC_CTRL2 */ 349322f4bf8aSRussell King if ((new_ctrl0 ^ gmac_ctrl0) & MVNETA_GMAC0_PORT_1000BASE_X || 349422f4bf8aSRussell King (new_ctrl2 ^ gmac_ctrl2) & MVNETA_GMAC2_INBAND_AN_ENABLE || 3495503f9aa9SRussell King (new_an ^ gmac_an) & MVNETA_GMAC_INBAND_AN_ENABLE) { 3496503f9aa9SRussell King mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, 3497503f9aa9SRussell King (gmac_an & ~MVNETA_GMAC_FORCE_LINK_PASS) | 3498503f9aa9SRussell King MVNETA_GMAC_FORCE_LINK_DOWN); 3499503f9aa9SRussell King } 3500503f9aa9SRussell King 3501da58a931SMaxime Chevallier /* When at 2.5G, the link partner can send frames with shortened 3502da58a931SMaxime Chevallier * preambles. 3503da58a931SMaxime Chevallier */ 3504da58a931SMaxime Chevallier if (state->speed == SPEED_2500) 3505da58a931SMaxime Chevallier new_ctrl4 |= MVNETA_GMAC4_SHORT_PREAMBLE_ENABLE; 3506da58a931SMaxime Chevallier 350722f4bf8aSRussell King if (new_ctrl0 != gmac_ctrl0) 350822f4bf8aSRussell King mvreg_write(pp, MVNETA_GMAC_CTRL_0, new_ctrl0); 3509503f9aa9SRussell King if (new_ctrl2 != gmac_ctrl2) 3510503f9aa9SRussell King mvreg_write(pp, MVNETA_GMAC_CTRL_2, new_ctrl2); 3511da58a931SMaxime Chevallier if (new_ctrl4 != gmac_ctrl4) 3512da58a931SMaxime Chevallier mvreg_write(pp, MVNETA_GMAC_CTRL_4, new_ctrl4); 3513503f9aa9SRussell King if (new_clk != gmac_clk) 3514503f9aa9SRussell King mvreg_write(pp, MVNETA_GMAC_CLOCK_DIVIDER, new_clk); 3515503f9aa9SRussell King if (new_an != gmac_an) 3516503f9aa9SRussell King mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, new_an); 351732699954SRussell King 351832699954SRussell King if (gmac_ctrl2 & MVNETA_GMAC2_PORT_RESET) { 351932699954SRussell King while ((mvreg_read(pp, MVNETA_GMAC_CTRL_2) & 352032699954SRussell King MVNETA_GMAC2_PORT_RESET) != 0) 352132699954SRussell King continue; 352232699954SRussell King } 3523503f9aa9SRussell King } 3524503f9aa9SRussell King 35256d81f451SRussell King static void mvneta_set_eee(struct mvneta_port *pp, bool enable) 35266d81f451SRussell King { 35276d81f451SRussell King u32 lpi_ctl1; 35286d81f451SRussell King 35296d81f451SRussell King lpi_ctl1 = mvreg_read(pp, MVNETA_LPI_CTRL_1); 35306d81f451SRussell King if (enable) 35316d81f451SRussell King lpi_ctl1 |= MVNETA_LPI_REQUEST_ENABLE; 35326d81f451SRussell King else 35336d81f451SRussell King lpi_ctl1 &= ~MVNETA_LPI_REQUEST_ENABLE; 35346d81f451SRussell King mvreg_write(pp, MVNETA_LPI_CTRL_1, lpi_ctl1); 35356d81f451SRussell King } 35366d81f451SRussell King 3537c6ab3008SFlorian Fainelli static void mvneta_mac_link_down(struct net_device *ndev, unsigned int mode, 3538c6ab3008SFlorian Fainelli phy_interface_t interface) 3539fc548b99SRussell King { 3540fc548b99SRussell King struct mvneta_port *pp = netdev_priv(ndev); 3541fc548b99SRussell King u32 val; 3542fc548b99SRussell King 3543503f9aa9SRussell King mvneta_port_down(pp); 3544503f9aa9SRussell King 3545503f9aa9SRussell King if (!phylink_autoneg_inband(mode)) { 3546fc548b99SRussell King val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG); 3547fc548b99SRussell King val &= ~MVNETA_GMAC_FORCE_LINK_PASS; 3548fc548b99SRussell King val |= MVNETA_GMAC_FORCE_LINK_DOWN; 3549fc548b99SRussell King mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val); 3550fc548b99SRussell King } 35516d81f451SRussell King 35526d81f451SRussell King pp->eee_active = false; 35536d81f451SRussell King mvneta_set_eee(pp, false); 3554fc548b99SRussell King } 3555fc548b99SRussell King 3556503f9aa9SRussell King static void mvneta_mac_link_up(struct net_device *ndev, unsigned int mode, 3557c6ab3008SFlorian Fainelli phy_interface_t interface, 3558503f9aa9SRussell King struct phy_device *phy) 3559fc548b99SRussell King { 3560fc548b99SRussell King struct mvneta_port *pp = netdev_priv(ndev); 3561fc548b99SRussell King u32 val; 3562fc548b99SRussell King 3563503f9aa9SRussell King if (!phylink_autoneg_inband(mode)) { 3564fc548b99SRussell King val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG); 3565fc548b99SRussell King val &= ~MVNETA_GMAC_FORCE_LINK_DOWN; 3566fc548b99SRussell King val |= MVNETA_GMAC_FORCE_LINK_PASS; 3567fc548b99SRussell King mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val); 3568fc548b99SRussell King } 3569fc548b99SRussell King 3570fc548b99SRussell King mvneta_port_up(pp); 35716d81f451SRussell King 35726d81f451SRussell King if (phy && pp->eee_enabled) { 35736d81f451SRussell King pp->eee_active = phy_init_eee(phy, 0) >= 0; 35746d81f451SRussell King mvneta_set_eee(pp, pp->eee_active && pp->tx_lpi_enabled); 35756d81f451SRussell King } 3576fc548b99SRussell King } 3577fc548b99SRussell King 3578503f9aa9SRussell King static const struct phylink_mac_ops mvneta_phylink_ops = { 3579503f9aa9SRussell King .validate = mvneta_validate, 3580503f9aa9SRussell King .mac_link_state = mvneta_mac_link_state, 358122f4bf8aSRussell King .mac_an_restart = mvneta_mac_an_restart, 3582503f9aa9SRussell King .mac_config = mvneta_mac_config, 3583503f9aa9SRussell King .mac_link_down = mvneta_mac_link_down, 3584503f9aa9SRussell King .mac_link_up = mvneta_mac_link_up, 3585503f9aa9SRussell King }; 3586c5aff182SThomas Petazzoni 3587c5aff182SThomas Petazzoni static int mvneta_mdio_probe(struct mvneta_port *pp) 3588c5aff182SThomas Petazzoni { 358982960fffSJisheng Zhang struct ethtool_wolinfo wol = { .cmd = ETHTOOL_GWOL }; 3590503f9aa9SRussell King int err = phylink_of_phy_connect(pp->phylink, pp->dn, 0); 3591c5aff182SThomas Petazzoni 3592503f9aa9SRussell King if (err) 3593503f9aa9SRussell King netdev_err(pp->dev, "could not attach PHY: %d\n", err); 3594c5aff182SThomas Petazzoni 3595503f9aa9SRussell King phylink_ethtool_get_wol(pp->phylink, &wol); 359682960fffSJisheng Zhang device_set_wakeup_capable(&pp->dev->dev, !!wol.supported); 359782960fffSJisheng Zhang 3598503f9aa9SRussell King return err; 3599c5aff182SThomas Petazzoni } 3600c5aff182SThomas Petazzoni 3601c5aff182SThomas Petazzoni static void mvneta_mdio_remove(struct mvneta_port *pp) 3602c5aff182SThomas Petazzoni { 3603503f9aa9SRussell King phylink_disconnect_phy(pp->phylink); 3604c5aff182SThomas Petazzoni } 3605c5aff182SThomas Petazzoni 3606120cfa50SGregory CLEMENT /* Electing a CPU must be done in an atomic way: it should be done 3607120cfa50SGregory CLEMENT * after or before the removal/insertion of a CPU and this function is 3608120cfa50SGregory CLEMENT * not reentrant. 3609120cfa50SGregory CLEMENT */ 3610f8642885SMaxime Ripard static void mvneta_percpu_elect(struct mvneta_port *pp) 3611f8642885SMaxime Ripard { 3612cad5d847SGregory CLEMENT int elected_cpu = 0, max_cpu, cpu, i = 0; 3613f8642885SMaxime Ripard 3614cad5d847SGregory CLEMENT /* Use the cpu associated to the rxq when it is online, in all 3615cad5d847SGregory CLEMENT * the other cases, use the cpu 0 which can't be offline. 3616cad5d847SGregory CLEMENT */ 3617cad5d847SGregory CLEMENT if (cpu_online(pp->rxq_def)) 3618cad5d847SGregory CLEMENT elected_cpu = pp->rxq_def; 3619cad5d847SGregory CLEMENT 36202dcf75e2SGregory CLEMENT max_cpu = num_present_cpus(); 3621f8642885SMaxime Ripard 3622f8642885SMaxime Ripard for_each_online_cpu(cpu) { 36232dcf75e2SGregory CLEMENT int rxq_map = 0, txq_map = 0; 36242dcf75e2SGregory CLEMENT int rxq; 36252dcf75e2SGregory CLEMENT 36262dcf75e2SGregory CLEMENT for (rxq = 0; rxq < rxq_number; rxq++) 36272dcf75e2SGregory CLEMENT if ((rxq % max_cpu) == cpu) 36282dcf75e2SGregory CLEMENT rxq_map |= MVNETA_CPU_RXQ_ACCESS(rxq); 36292dcf75e2SGregory CLEMENT 3630cad5d847SGregory CLEMENT if (cpu == elected_cpu) 363150bf8cb6SGregory CLEMENT /* Map the default receive queue queue to the 363250bf8cb6SGregory CLEMENT * elected CPU 3633f8642885SMaxime Ripard */ 36342dcf75e2SGregory CLEMENT rxq_map |= MVNETA_CPU_RXQ_ACCESS(pp->rxq_def); 363550bf8cb6SGregory CLEMENT 363650bf8cb6SGregory CLEMENT /* We update the TX queue map only if we have one 363750bf8cb6SGregory CLEMENT * queue. In this case we associate the TX queue to 363850bf8cb6SGregory CLEMENT * the CPU bound to the default RX queue 363950bf8cb6SGregory CLEMENT */ 364050bf8cb6SGregory CLEMENT if (txq_number == 1) 3641cad5d847SGregory CLEMENT txq_map = (cpu == elected_cpu) ? 364250bf8cb6SGregory CLEMENT MVNETA_CPU_TXQ_ACCESS(1) : 0; 364350bf8cb6SGregory CLEMENT else 364450bf8cb6SGregory CLEMENT txq_map = mvreg_read(pp, MVNETA_CPU_MAP(cpu)) & 364550bf8cb6SGregory CLEMENT MVNETA_CPU_TXQ_ACCESS_ALL_MASK; 364650bf8cb6SGregory CLEMENT 36472dcf75e2SGregory CLEMENT mvreg_write(pp, MVNETA_CPU_MAP(cpu), rxq_map | txq_map); 36482dcf75e2SGregory CLEMENT 36492dcf75e2SGregory CLEMENT /* Update the interrupt mask on each CPU according the 36502dcf75e2SGregory CLEMENT * new mapping 36512dcf75e2SGregory CLEMENT */ 36522dcf75e2SGregory CLEMENT smp_call_function_single(cpu, mvneta_percpu_unmask_interrupt, 3653f8642885SMaxime Ripard pp, true); 3654f8642885SMaxime Ripard i++; 36552dcf75e2SGregory CLEMENT 3656f8642885SMaxime Ripard } 3657f8642885SMaxime Ripard }; 3658f8642885SMaxime Ripard 365984a3f4dbSSebastian Andrzej Siewior static int mvneta_cpu_online(unsigned int cpu, struct hlist_node *node) 3660f8642885SMaxime Ripard { 366184a3f4dbSSebastian Andrzej Siewior int other_cpu; 366284a3f4dbSSebastian Andrzej Siewior struct mvneta_port *pp = hlist_entry_safe(node, struct mvneta_port, 366384a3f4dbSSebastian Andrzej Siewior node_online); 3664f8642885SMaxime Ripard struct mvneta_pcpu_port *port = per_cpu_ptr(pp->ports, cpu); 3665f8642885SMaxime Ripard 366684a3f4dbSSebastian Andrzej Siewior 3667120cfa50SGregory CLEMENT spin_lock(&pp->lock); 366884a3f4dbSSebastian Andrzej Siewior /* 366984a3f4dbSSebastian Andrzej Siewior * Configuring the driver for a new CPU while the driver is 367084a3f4dbSSebastian Andrzej Siewior * stopping is racy, so just avoid it. 3671120cfa50SGregory CLEMENT */ 3672120cfa50SGregory CLEMENT if (pp->is_stopped) { 3673120cfa50SGregory CLEMENT spin_unlock(&pp->lock); 367484a3f4dbSSebastian Andrzej Siewior return 0; 3675120cfa50SGregory CLEMENT } 3676f8642885SMaxime Ripard netif_tx_stop_all_queues(pp->dev); 3677f8642885SMaxime Ripard 367884a3f4dbSSebastian Andrzej Siewior /* 367984a3f4dbSSebastian Andrzej Siewior * We have to synchronise on tha napi of each CPU except the one 368084a3f4dbSSebastian Andrzej Siewior * just being woken up 3681f8642885SMaxime Ripard */ 3682f8642885SMaxime Ripard for_each_online_cpu(other_cpu) { 3683f8642885SMaxime Ripard if (other_cpu != cpu) { 3684f8642885SMaxime Ripard struct mvneta_pcpu_port *other_port = 3685f8642885SMaxime Ripard per_cpu_ptr(pp->ports, other_cpu); 3686f8642885SMaxime Ripard 3687f8642885SMaxime Ripard napi_synchronize(&other_port->napi); 3688f8642885SMaxime Ripard } 3689f8642885SMaxime Ripard } 3690f8642885SMaxime Ripard 3691f8642885SMaxime Ripard /* Mask all ethernet port interrupts */ 3692db488c10SGregory CLEMENT on_each_cpu(mvneta_percpu_mask_interrupt, pp, true); 3693f8642885SMaxime Ripard napi_enable(&port->napi); 3694f8642885SMaxime Ripard 369584a3f4dbSSebastian Andrzej Siewior /* 369684a3f4dbSSebastian Andrzej Siewior * Enable per-CPU interrupts on the CPU that is 36972dcf75e2SGregory CLEMENT * brought up. 36982dcf75e2SGregory CLEMENT */ 36990e28bf93SAnna-Maria Gleixner mvneta_percpu_enable(pp); 37002dcf75e2SGregory CLEMENT 370184a3f4dbSSebastian Andrzej Siewior /* 370284a3f4dbSSebastian Andrzej Siewior * Enable per-CPU interrupt on the one CPU we care 3703f8642885SMaxime Ripard * about. 3704f8642885SMaxime Ripard */ 3705f8642885SMaxime Ripard mvneta_percpu_elect(pp); 3706f8642885SMaxime Ripard 3707db488c10SGregory CLEMENT /* Unmask all ethernet port interrupts */ 3708db488c10SGregory CLEMENT on_each_cpu(mvneta_percpu_unmask_interrupt, pp, true); 3709f8642885SMaxime Ripard mvreg_write(pp, MVNETA_INTR_MISC_MASK, 3710f8642885SMaxime Ripard MVNETA_CAUSE_PHY_STATUS_CHANGE | 3711856b2cc5SRussell King MVNETA_CAUSE_LINK_CHANGE); 3712f8642885SMaxime Ripard netif_tx_start_all_queues(pp->dev); 3713120cfa50SGregory CLEMENT spin_unlock(&pp->lock); 371484a3f4dbSSebastian Andrzej Siewior return 0; 371584a3f4dbSSebastian Andrzej Siewior } 371684a3f4dbSSebastian Andrzej Siewior 371784a3f4dbSSebastian Andrzej Siewior static int mvneta_cpu_down_prepare(unsigned int cpu, struct hlist_node *node) 371884a3f4dbSSebastian Andrzej Siewior { 371984a3f4dbSSebastian Andrzej Siewior struct mvneta_port *pp = hlist_entry_safe(node, struct mvneta_port, 372084a3f4dbSSebastian Andrzej Siewior node_online); 372184a3f4dbSSebastian Andrzej Siewior struct mvneta_pcpu_port *port = per_cpu_ptr(pp->ports, cpu); 372284a3f4dbSSebastian Andrzej Siewior 372384a3f4dbSSebastian Andrzej Siewior /* 372484a3f4dbSSebastian Andrzej Siewior * Thanks to this lock we are sure that any pending cpu election is 372584a3f4dbSSebastian Andrzej Siewior * done. 37265888511eSGregory CLEMENT */ 37275888511eSGregory CLEMENT spin_lock(&pp->lock); 3728f8642885SMaxime Ripard /* Mask all ethernet port interrupts */ 3729db488c10SGregory CLEMENT on_each_cpu(mvneta_percpu_mask_interrupt, pp, true); 37305888511eSGregory CLEMENT spin_unlock(&pp->lock); 3731f8642885SMaxime Ripard 3732f8642885SMaxime Ripard napi_synchronize(&port->napi); 3733f8642885SMaxime Ripard napi_disable(&port->napi); 373484a3f4dbSSebastian Andrzej Siewior /* Disable per-CPU interrupts on the CPU that is brought down. */ 37350e28bf93SAnna-Maria Gleixner mvneta_percpu_disable(pp); 373684a3f4dbSSebastian Andrzej Siewior return 0; 373784a3f4dbSSebastian Andrzej Siewior } 3738f8642885SMaxime Ripard 373984a3f4dbSSebastian Andrzej Siewior static int mvneta_cpu_dead(unsigned int cpu, struct hlist_node *node) 374084a3f4dbSSebastian Andrzej Siewior { 374184a3f4dbSSebastian Andrzej Siewior struct mvneta_port *pp = hlist_entry_safe(node, struct mvneta_port, 374284a3f4dbSSebastian Andrzej Siewior node_dead); 374384a3f4dbSSebastian Andrzej Siewior 3744f8642885SMaxime Ripard /* Check if a new CPU must be elected now this on is down */ 3745120cfa50SGregory CLEMENT spin_lock(&pp->lock); 3746f8642885SMaxime Ripard mvneta_percpu_elect(pp); 3747120cfa50SGregory CLEMENT spin_unlock(&pp->lock); 3748f8642885SMaxime Ripard /* Unmask all ethernet port interrupts */ 3749db488c10SGregory CLEMENT on_each_cpu(mvneta_percpu_unmask_interrupt, pp, true); 3750f8642885SMaxime Ripard mvreg_write(pp, MVNETA_INTR_MISC_MASK, 3751f8642885SMaxime Ripard MVNETA_CAUSE_PHY_STATUS_CHANGE | 3752856b2cc5SRussell King MVNETA_CAUSE_LINK_CHANGE); 3753f8642885SMaxime Ripard netif_tx_start_all_queues(pp->dev); 375484a3f4dbSSebastian Andrzej Siewior return 0; 3755f8642885SMaxime Ripard } 3756f8642885SMaxime Ripard 3757c5aff182SThomas Petazzoni static int mvneta_open(struct net_device *dev) 3758c5aff182SThomas Petazzoni { 3759c5aff182SThomas Petazzoni struct mvneta_port *pp = netdev_priv(dev); 37606b125d63SGregory CLEMENT int ret; 3761c5aff182SThomas Petazzoni 3762c5aff182SThomas Petazzoni pp->pkt_size = MVNETA_RX_PKT_SIZE(pp->dev->mtu); 37637e47fd84SGregory CLEMENT pp->frag_size = PAGE_SIZE; 3764c5aff182SThomas Petazzoni 3765c5aff182SThomas Petazzoni ret = mvneta_setup_rxqs(pp); 3766c5aff182SThomas Petazzoni if (ret) 3767c5aff182SThomas Petazzoni return ret; 3768c5aff182SThomas Petazzoni 3769c5aff182SThomas Petazzoni ret = mvneta_setup_txqs(pp); 3770c5aff182SThomas Petazzoni if (ret) 3771c5aff182SThomas Petazzoni goto err_cleanup_rxqs; 3772c5aff182SThomas Petazzoni 3773c5aff182SThomas Petazzoni /* Connect to port interrupt line */ 37742636ac3cSMarcin Wojtas if (pp->neta_armada3700) 37752636ac3cSMarcin Wojtas ret = request_irq(pp->dev->irq, mvneta_isr, 0, 37762636ac3cSMarcin Wojtas dev->name, pp); 37772636ac3cSMarcin Wojtas else 37782636ac3cSMarcin Wojtas ret = request_percpu_irq(pp->dev->irq, mvneta_percpu_isr, 37792636ac3cSMarcin Wojtas dev->name, pp->ports); 3780c5aff182SThomas Petazzoni if (ret) { 3781c5aff182SThomas Petazzoni netdev_err(pp->dev, "cannot request irq %d\n", pp->dev->irq); 3782c5aff182SThomas Petazzoni goto err_cleanup_txqs; 3783c5aff182SThomas Petazzoni } 3784c5aff182SThomas Petazzoni 37852636ac3cSMarcin Wojtas if (!pp->neta_armada3700) { 37862dcf75e2SGregory CLEMENT /* Enable per-CPU interrupt on all the CPU to handle our RX 37872dcf75e2SGregory CLEMENT * queue interrupts 37882dcf75e2SGregory CLEMENT */ 37896b125d63SGregory CLEMENT on_each_cpu(mvneta_percpu_enable, pp, true); 37902dcf75e2SGregory CLEMENT 3791120cfa50SGregory CLEMENT pp->is_stopped = false; 3792f8642885SMaxime Ripard /* Register a CPU notifier to handle the case where our CPU 3793f8642885SMaxime Ripard * might be taken offline. 3794f8642885SMaxime Ripard */ 379584a3f4dbSSebastian Andrzej Siewior ret = cpuhp_state_add_instance_nocalls(online_hpstate, 379684a3f4dbSSebastian Andrzej Siewior &pp->node_online); 379784a3f4dbSSebastian Andrzej Siewior if (ret) 379884a3f4dbSSebastian Andrzej Siewior goto err_free_irq; 379984a3f4dbSSebastian Andrzej Siewior 380084a3f4dbSSebastian Andrzej Siewior ret = cpuhp_state_add_instance_nocalls(CPUHP_NET_MVNETA_DEAD, 380184a3f4dbSSebastian Andrzej Siewior &pp->node_dead); 380284a3f4dbSSebastian Andrzej Siewior if (ret) 380384a3f4dbSSebastian Andrzej Siewior goto err_free_online_hp; 38042636ac3cSMarcin Wojtas } 3805f8642885SMaxime Ripard 3806c5aff182SThomas Petazzoni ret = mvneta_mdio_probe(pp); 3807c5aff182SThomas Petazzoni if (ret < 0) { 3808c5aff182SThomas Petazzoni netdev_err(dev, "cannot probe MDIO bus\n"); 380984a3f4dbSSebastian Andrzej Siewior goto err_free_dead_hp; 3810c5aff182SThomas Petazzoni } 3811c5aff182SThomas Petazzoni 3812c5aff182SThomas Petazzoni mvneta_start_dev(pp); 3813c5aff182SThomas Petazzoni 3814c5aff182SThomas Petazzoni return 0; 3815c5aff182SThomas Petazzoni 381684a3f4dbSSebastian Andrzej Siewior err_free_dead_hp: 38172636ac3cSMarcin Wojtas if (!pp->neta_armada3700) 381884a3f4dbSSebastian Andrzej Siewior cpuhp_state_remove_instance_nocalls(CPUHP_NET_MVNETA_DEAD, 381984a3f4dbSSebastian Andrzej Siewior &pp->node_dead); 382084a3f4dbSSebastian Andrzej Siewior err_free_online_hp: 38212636ac3cSMarcin Wojtas if (!pp->neta_armada3700) 38222636ac3cSMarcin Wojtas cpuhp_state_remove_instance_nocalls(online_hpstate, 38232636ac3cSMarcin Wojtas &pp->node_online); 3824c5aff182SThomas Petazzoni err_free_irq: 38252636ac3cSMarcin Wojtas if (pp->neta_armada3700) { 38262636ac3cSMarcin Wojtas free_irq(pp->dev->irq, pp); 38272636ac3cSMarcin Wojtas } else { 38283d8c4530SRussell King - ARM Linux on_each_cpu(mvneta_percpu_disable, pp, true); 382912bb03b4SMaxime Ripard free_percpu_irq(pp->dev->irq, pp->ports); 38302636ac3cSMarcin Wojtas } 3831c5aff182SThomas Petazzoni err_cleanup_txqs: 3832c5aff182SThomas Petazzoni mvneta_cleanup_txqs(pp); 3833c5aff182SThomas Petazzoni err_cleanup_rxqs: 3834c5aff182SThomas Petazzoni mvneta_cleanup_rxqs(pp); 3835c5aff182SThomas Petazzoni return ret; 3836c5aff182SThomas Petazzoni } 3837c5aff182SThomas Petazzoni 3838c5aff182SThomas Petazzoni /* Stop the port, free port interrupt line */ 3839c5aff182SThomas Petazzoni static int mvneta_stop(struct net_device *dev) 3840c5aff182SThomas Petazzoni { 3841c5aff182SThomas Petazzoni struct mvneta_port *pp = netdev_priv(dev); 3842c5aff182SThomas Petazzoni 38432636ac3cSMarcin Wojtas if (!pp->neta_armada3700) { 3844120cfa50SGregory CLEMENT /* Inform that we are stopping so we don't want to setup the 38451c2722a9SGregory CLEMENT * driver for new CPUs in the notifiers. The code of the 38461c2722a9SGregory CLEMENT * notifier for CPU online is protected by the same spinlock, 38471c2722a9SGregory CLEMENT * so when we get the lock, the notifer work is done. 3848120cfa50SGregory CLEMENT */ 3849120cfa50SGregory CLEMENT spin_lock(&pp->lock); 3850120cfa50SGregory CLEMENT pp->is_stopped = true; 38511c2722a9SGregory CLEMENT spin_unlock(&pp->lock); 38521c2722a9SGregory CLEMENT 3853c5aff182SThomas Petazzoni mvneta_stop_dev(pp); 3854c5aff182SThomas Petazzoni mvneta_mdio_remove(pp); 385584a3f4dbSSebastian Andrzej Siewior 3856d26aac2dSDan Carpenter cpuhp_state_remove_instance_nocalls(online_hpstate, 3857d26aac2dSDan Carpenter &pp->node_online); 385884a3f4dbSSebastian Andrzej Siewior cpuhp_state_remove_instance_nocalls(CPUHP_NET_MVNETA_DEAD, 385984a3f4dbSSebastian Andrzej Siewior &pp->node_dead); 3860129219e4SGregory CLEMENT on_each_cpu(mvneta_percpu_disable, pp, true); 386112bb03b4SMaxime Ripard free_percpu_irq(dev->irq, pp->ports); 38622636ac3cSMarcin Wojtas } else { 38632636ac3cSMarcin Wojtas mvneta_stop_dev(pp); 38642636ac3cSMarcin Wojtas mvneta_mdio_remove(pp); 38652636ac3cSMarcin Wojtas free_irq(dev->irq, pp); 38662636ac3cSMarcin Wojtas } 38672636ac3cSMarcin Wojtas 3868c5aff182SThomas Petazzoni mvneta_cleanup_rxqs(pp); 3869c5aff182SThomas Petazzoni mvneta_cleanup_txqs(pp); 3870c5aff182SThomas Petazzoni 3871c5aff182SThomas Petazzoni return 0; 3872c5aff182SThomas Petazzoni } 3873c5aff182SThomas Petazzoni 387415f59456SThomas Petazzoni static int mvneta_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) 387515f59456SThomas Petazzoni { 3876503f9aa9SRussell King struct mvneta_port *pp = netdev_priv(dev); 387715f59456SThomas Petazzoni 3878503f9aa9SRussell King return phylink_mii_ioctl(pp->phylink, ifr, cmd); 387915f59456SThomas Petazzoni } 388015f59456SThomas Petazzoni 3881c5aff182SThomas Petazzoni /* Ethtool methods */ 3882c5aff182SThomas Petazzoni 3883013ad40dSPhilippe Reynes /* Set link ksettings (phy address, speed) for ethtools */ 38842dc0d2b4SBaoyou Xie static int 38852dc0d2b4SBaoyou Xie mvneta_ethtool_set_link_ksettings(struct net_device *ndev, 3886013ad40dSPhilippe Reynes const struct ethtool_link_ksettings *cmd) 3887c5aff182SThomas Petazzoni { 3888013ad40dSPhilippe Reynes struct mvneta_port *pp = netdev_priv(ndev); 3889c5aff182SThomas Petazzoni 3890503f9aa9SRussell King return phylink_ethtool_ksettings_set(pp->phylink, cmd); 38910c0744fcSStas Sergeev } 38920c0744fcSStas Sergeev 3893503f9aa9SRussell King /* Get link ksettings for ethtools */ 3894503f9aa9SRussell King static int 3895503f9aa9SRussell King mvneta_ethtool_get_link_ksettings(struct net_device *ndev, 3896503f9aa9SRussell King struct ethtool_link_ksettings *cmd) 3897503f9aa9SRussell King { 3898503f9aa9SRussell King struct mvneta_port *pp = netdev_priv(ndev); 38990c0744fcSStas Sergeev 3900503f9aa9SRussell King return phylink_ethtool_ksettings_get(pp->phylink, cmd); 39010c0744fcSStas Sergeev } 39020c0744fcSStas Sergeev 3903503f9aa9SRussell King static int mvneta_ethtool_nway_reset(struct net_device *dev) 3904503f9aa9SRussell King { 3905503f9aa9SRussell King struct mvneta_port *pp = netdev_priv(dev); 3906503f9aa9SRussell King 3907503f9aa9SRussell King return phylink_ethtool_nway_reset(pp->phylink); 3908c5aff182SThomas Petazzoni } 3909c5aff182SThomas Petazzoni 3910c5aff182SThomas Petazzoni /* Set interrupt coalescing for ethtools */ 3911c5aff182SThomas Petazzoni static int mvneta_ethtool_set_coalesce(struct net_device *dev, 3912c5aff182SThomas Petazzoni struct ethtool_coalesce *c) 3913c5aff182SThomas Petazzoni { 3914c5aff182SThomas Petazzoni struct mvneta_port *pp = netdev_priv(dev); 3915c5aff182SThomas Petazzoni int queue; 3916c5aff182SThomas Petazzoni 3917c5aff182SThomas Petazzoni for (queue = 0; queue < rxq_number; queue++) { 3918c5aff182SThomas Petazzoni struct mvneta_rx_queue *rxq = &pp->rxqs[queue]; 3919c5aff182SThomas Petazzoni rxq->time_coal = c->rx_coalesce_usecs; 3920c5aff182SThomas Petazzoni rxq->pkts_coal = c->rx_max_coalesced_frames; 3921c5aff182SThomas Petazzoni mvneta_rx_pkts_coal_set(pp, rxq, rxq->pkts_coal); 3922c5aff182SThomas Petazzoni mvneta_rx_time_coal_set(pp, rxq, rxq->time_coal); 3923c5aff182SThomas Petazzoni } 3924c5aff182SThomas Petazzoni 3925c5aff182SThomas Petazzoni for (queue = 0; queue < txq_number; queue++) { 3926c5aff182SThomas Petazzoni struct mvneta_tx_queue *txq = &pp->txqs[queue]; 3927c5aff182SThomas Petazzoni txq->done_pkts_coal = c->tx_max_coalesced_frames; 3928c5aff182SThomas Petazzoni mvneta_tx_done_pkts_coal_set(pp, txq, txq->done_pkts_coal); 3929c5aff182SThomas Petazzoni } 3930c5aff182SThomas Petazzoni 3931c5aff182SThomas Petazzoni return 0; 3932c5aff182SThomas Petazzoni } 3933c5aff182SThomas Petazzoni 3934c5aff182SThomas Petazzoni /* get coalescing for ethtools */ 3935c5aff182SThomas Petazzoni static int mvneta_ethtool_get_coalesce(struct net_device *dev, 3936c5aff182SThomas Petazzoni struct ethtool_coalesce *c) 3937c5aff182SThomas Petazzoni { 3938c5aff182SThomas Petazzoni struct mvneta_port *pp = netdev_priv(dev); 3939c5aff182SThomas Petazzoni 3940c5aff182SThomas Petazzoni c->rx_coalesce_usecs = pp->rxqs[0].time_coal; 3941c5aff182SThomas Petazzoni c->rx_max_coalesced_frames = pp->rxqs[0].pkts_coal; 3942c5aff182SThomas Petazzoni 3943c5aff182SThomas Petazzoni c->tx_max_coalesced_frames = pp->txqs[0].done_pkts_coal; 3944c5aff182SThomas Petazzoni return 0; 3945c5aff182SThomas Petazzoni } 3946c5aff182SThomas Petazzoni 3947c5aff182SThomas Petazzoni 3948c5aff182SThomas Petazzoni static void mvneta_ethtool_get_drvinfo(struct net_device *dev, 3949c5aff182SThomas Petazzoni struct ethtool_drvinfo *drvinfo) 3950c5aff182SThomas Petazzoni { 3951c5aff182SThomas Petazzoni strlcpy(drvinfo->driver, MVNETA_DRIVER_NAME, 3952c5aff182SThomas Petazzoni sizeof(drvinfo->driver)); 3953c5aff182SThomas Petazzoni strlcpy(drvinfo->version, MVNETA_DRIVER_VERSION, 3954c5aff182SThomas Petazzoni sizeof(drvinfo->version)); 3955c5aff182SThomas Petazzoni strlcpy(drvinfo->bus_info, dev_name(&dev->dev), 3956c5aff182SThomas Petazzoni sizeof(drvinfo->bus_info)); 3957c5aff182SThomas Petazzoni } 3958c5aff182SThomas Petazzoni 3959c5aff182SThomas Petazzoni 3960c5aff182SThomas Petazzoni static void mvneta_ethtool_get_ringparam(struct net_device *netdev, 3961c5aff182SThomas Petazzoni struct ethtool_ringparam *ring) 3962c5aff182SThomas Petazzoni { 3963c5aff182SThomas Petazzoni struct mvneta_port *pp = netdev_priv(netdev); 3964c5aff182SThomas Petazzoni 3965c5aff182SThomas Petazzoni ring->rx_max_pending = MVNETA_MAX_RXD; 3966c5aff182SThomas Petazzoni ring->tx_max_pending = MVNETA_MAX_TXD; 3967c5aff182SThomas Petazzoni ring->rx_pending = pp->rx_ring_size; 3968c5aff182SThomas Petazzoni ring->tx_pending = pp->tx_ring_size; 3969c5aff182SThomas Petazzoni } 3970c5aff182SThomas Petazzoni 3971c5aff182SThomas Petazzoni static int mvneta_ethtool_set_ringparam(struct net_device *dev, 3972c5aff182SThomas Petazzoni struct ethtool_ringparam *ring) 3973c5aff182SThomas Petazzoni { 3974c5aff182SThomas Petazzoni struct mvneta_port *pp = netdev_priv(dev); 3975c5aff182SThomas Petazzoni 3976c5aff182SThomas Petazzoni if ((ring->rx_pending == 0) || (ring->tx_pending == 0)) 3977c5aff182SThomas Petazzoni return -EINVAL; 3978c5aff182SThomas Petazzoni pp->rx_ring_size = ring->rx_pending < MVNETA_MAX_RXD ? 3979c5aff182SThomas Petazzoni ring->rx_pending : MVNETA_MAX_RXD; 39808eef5f97SEzequiel Garcia 39818eef5f97SEzequiel Garcia pp->tx_ring_size = clamp_t(u16, ring->tx_pending, 39828eef5f97SEzequiel Garcia MVNETA_MAX_SKB_DESCS * 2, MVNETA_MAX_TXD); 39838eef5f97SEzequiel Garcia if (pp->tx_ring_size != ring->tx_pending) 39848eef5f97SEzequiel Garcia netdev_warn(dev, "TX queue size set to %u (requested %u)\n", 39858eef5f97SEzequiel Garcia pp->tx_ring_size, ring->tx_pending); 3986c5aff182SThomas Petazzoni 3987c5aff182SThomas Petazzoni if (netif_running(dev)) { 3988c5aff182SThomas Petazzoni mvneta_stop(dev); 3989c5aff182SThomas Petazzoni if (mvneta_open(dev)) { 3990c5aff182SThomas Petazzoni netdev_err(dev, 3991c5aff182SThomas Petazzoni "error on opening device after ring param change\n"); 3992c5aff182SThomas Petazzoni return -ENOMEM; 3993c5aff182SThomas Petazzoni } 3994c5aff182SThomas Petazzoni } 3995c5aff182SThomas Petazzoni 3996c5aff182SThomas Petazzoni return 0; 3997c5aff182SThomas Petazzoni } 3998c5aff182SThomas Petazzoni 39994932a918SRussell King static void mvneta_ethtool_get_pauseparam(struct net_device *dev, 40004932a918SRussell King struct ethtool_pauseparam *pause) 40014932a918SRussell King { 40024932a918SRussell King struct mvneta_port *pp = netdev_priv(dev); 40034932a918SRussell King 40044932a918SRussell King phylink_ethtool_get_pauseparam(pp->phylink, pause); 40054932a918SRussell King } 40064932a918SRussell King 40074932a918SRussell King static int mvneta_ethtool_set_pauseparam(struct net_device *dev, 40084932a918SRussell King struct ethtool_pauseparam *pause) 40094932a918SRussell King { 40104932a918SRussell King struct mvneta_port *pp = netdev_priv(dev); 40114932a918SRussell King 40124932a918SRussell King return phylink_ethtool_set_pauseparam(pp->phylink, pause); 40134932a918SRussell King } 40144932a918SRussell King 40159b0cdefaSRussell King static void mvneta_ethtool_get_strings(struct net_device *netdev, u32 sset, 40169b0cdefaSRussell King u8 *data) 40179b0cdefaSRussell King { 40189b0cdefaSRussell King if (sset == ETH_SS_STATS) { 40199b0cdefaSRussell King int i; 40209b0cdefaSRussell King 40219b0cdefaSRussell King for (i = 0; i < ARRAY_SIZE(mvneta_statistics); i++) 40229b0cdefaSRussell King memcpy(data + i * ETH_GSTRING_LEN, 40239b0cdefaSRussell King mvneta_statistics[i].name, ETH_GSTRING_LEN); 40249b0cdefaSRussell King } 40259b0cdefaSRussell King } 40269b0cdefaSRussell King 40279b0cdefaSRussell King static void mvneta_ethtool_update_stats(struct mvneta_port *pp) 40289b0cdefaSRussell King { 40299b0cdefaSRussell King const struct mvneta_statistic *s; 40309b0cdefaSRussell King void __iomem *base = pp->base; 40316d81f451SRussell King u32 high, low; 40326d81f451SRussell King u64 val; 40339b0cdefaSRussell King int i; 40349b0cdefaSRussell King 40359b0cdefaSRussell King for (i = 0, s = mvneta_statistics; 40369b0cdefaSRussell King s < mvneta_statistics + ARRAY_SIZE(mvneta_statistics); 40379b0cdefaSRussell King s++, i++) { 40386d81f451SRussell King val = 0; 40396d81f451SRussell King 40409b0cdefaSRussell King switch (s->type) { 40419b0cdefaSRussell King case T_REG_32: 40429b0cdefaSRussell King val = readl_relaxed(base + s->offset); 40439b0cdefaSRussell King break; 40449b0cdefaSRussell King case T_REG_64: 40459b0cdefaSRussell King /* Docs say to read low 32-bit then high */ 40469b0cdefaSRussell King low = readl_relaxed(base + s->offset); 40479b0cdefaSRussell King high = readl_relaxed(base + s->offset + 4); 40486d81f451SRussell King val = (u64)high << 32 | low; 40496d81f451SRussell King break; 40506d81f451SRussell King case T_SW: 40516d81f451SRussell King switch (s->offset) { 40526d81f451SRussell King case ETHTOOL_STAT_EEE_WAKEUP: 40536d81f451SRussell King val = phylink_get_eee_err(pp->phylink); 40549b0cdefaSRussell King break; 405517a96da6SGregory CLEMENT case ETHTOOL_STAT_SKB_ALLOC_ERR: 405617a96da6SGregory CLEMENT val = pp->rxqs[0].skb_alloc_err; 405717a96da6SGregory CLEMENT break; 405817a96da6SGregory CLEMENT case ETHTOOL_STAT_REFILL_ERR: 405917a96da6SGregory CLEMENT val = pp->rxqs[0].refill_err; 406017a96da6SGregory CLEMENT break; 40619b0cdefaSRussell King } 40626d81f451SRussell King break; 40636d81f451SRussell King } 40646d81f451SRussell King 40656d81f451SRussell King pp->ethtool_stats[i] += val; 40669b0cdefaSRussell King } 40679b0cdefaSRussell King } 40689b0cdefaSRussell King 40699b0cdefaSRussell King static void mvneta_ethtool_get_stats(struct net_device *dev, 40709b0cdefaSRussell King struct ethtool_stats *stats, u64 *data) 40719b0cdefaSRussell King { 40729b0cdefaSRussell King struct mvneta_port *pp = netdev_priv(dev); 40739b0cdefaSRussell King int i; 40749b0cdefaSRussell King 40759b0cdefaSRussell King mvneta_ethtool_update_stats(pp); 40769b0cdefaSRussell King 40779b0cdefaSRussell King for (i = 0; i < ARRAY_SIZE(mvneta_statistics); i++) 40789b0cdefaSRussell King *data++ = pp->ethtool_stats[i]; 40799b0cdefaSRussell King } 40809b0cdefaSRussell King 40819b0cdefaSRussell King static int mvneta_ethtool_get_sset_count(struct net_device *dev, int sset) 40829b0cdefaSRussell King { 40839b0cdefaSRussell King if (sset == ETH_SS_STATS) 40849b0cdefaSRussell King return ARRAY_SIZE(mvneta_statistics); 40859b0cdefaSRussell King return -EOPNOTSUPP; 40869b0cdefaSRussell King } 40879b0cdefaSRussell King 40889a401deaSGregory CLEMENT static u32 mvneta_ethtool_get_rxfh_indir_size(struct net_device *dev) 40899a401deaSGregory CLEMENT { 40909a401deaSGregory CLEMENT return MVNETA_RSS_LU_TABLE_SIZE; 40919a401deaSGregory CLEMENT } 40929a401deaSGregory CLEMENT 40939a401deaSGregory CLEMENT static int mvneta_ethtool_get_rxnfc(struct net_device *dev, 40949a401deaSGregory CLEMENT struct ethtool_rxnfc *info, 40959a401deaSGregory CLEMENT u32 *rules __always_unused) 40969a401deaSGregory CLEMENT { 40979a401deaSGregory CLEMENT switch (info->cmd) { 40989a401deaSGregory CLEMENT case ETHTOOL_GRXRINGS: 40999a401deaSGregory CLEMENT info->data = rxq_number; 41009a401deaSGregory CLEMENT return 0; 41019a401deaSGregory CLEMENT case ETHTOOL_GRXFH: 41029a401deaSGregory CLEMENT return -EOPNOTSUPP; 41039a401deaSGregory CLEMENT default: 41049a401deaSGregory CLEMENT return -EOPNOTSUPP; 41059a401deaSGregory CLEMENT } 41069a401deaSGregory CLEMENT } 41079a401deaSGregory CLEMENT 41089a401deaSGregory CLEMENT static int mvneta_config_rss(struct mvneta_port *pp) 41099a401deaSGregory CLEMENT { 41109a401deaSGregory CLEMENT int cpu; 41119a401deaSGregory CLEMENT u32 val; 41129a401deaSGregory CLEMENT 41139a401deaSGregory CLEMENT netif_tx_stop_all_queues(pp->dev); 41149a401deaSGregory CLEMENT 41156b125d63SGregory CLEMENT on_each_cpu(mvneta_percpu_mask_interrupt, pp, true); 41169a401deaSGregory CLEMENT 41170f5c6c30SJisheng Zhang if (!pp->neta_armada3700) { 41189a401deaSGregory CLEMENT /* We have to synchronise on the napi of each CPU */ 41199a401deaSGregory CLEMENT for_each_online_cpu(cpu) { 41209a401deaSGregory CLEMENT struct mvneta_pcpu_port *pcpu_port = 41219a401deaSGregory CLEMENT per_cpu_ptr(pp->ports, cpu); 41229a401deaSGregory CLEMENT 41239a401deaSGregory CLEMENT napi_synchronize(&pcpu_port->napi); 41249a401deaSGregory CLEMENT napi_disable(&pcpu_port->napi); 41259a401deaSGregory CLEMENT } 41260f5c6c30SJisheng Zhang } else { 41270f5c6c30SJisheng Zhang napi_synchronize(&pp->napi); 41280f5c6c30SJisheng Zhang napi_disable(&pp->napi); 41290f5c6c30SJisheng Zhang } 41309a401deaSGregory CLEMENT 41319a401deaSGregory CLEMENT pp->rxq_def = pp->indir[0]; 41329a401deaSGregory CLEMENT 41339a401deaSGregory CLEMENT /* Update unicast mapping */ 41349a401deaSGregory CLEMENT mvneta_set_rx_mode(pp->dev); 41359a401deaSGregory CLEMENT 41369a401deaSGregory CLEMENT /* Update val of portCfg register accordingly with all RxQueue types */ 41379a401deaSGregory CLEMENT val = MVNETA_PORT_CONFIG_DEFL_VALUE(pp->rxq_def); 41389a401deaSGregory CLEMENT mvreg_write(pp, MVNETA_PORT_CONFIG, val); 41399a401deaSGregory CLEMENT 41409a401deaSGregory CLEMENT /* Update the elected CPU matching the new rxq_def */ 4141120cfa50SGregory CLEMENT spin_lock(&pp->lock); 41429a401deaSGregory CLEMENT mvneta_percpu_elect(pp); 4143120cfa50SGregory CLEMENT spin_unlock(&pp->lock); 41449a401deaSGregory CLEMENT 41450f5c6c30SJisheng Zhang if (!pp->neta_armada3700) { 41469a401deaSGregory CLEMENT /* We have to synchronise on the napi of each CPU */ 41479a401deaSGregory CLEMENT for_each_online_cpu(cpu) { 41489a401deaSGregory CLEMENT struct mvneta_pcpu_port *pcpu_port = 41499a401deaSGregory CLEMENT per_cpu_ptr(pp->ports, cpu); 41509a401deaSGregory CLEMENT 41519a401deaSGregory CLEMENT napi_enable(&pcpu_port->napi); 41529a401deaSGregory CLEMENT } 41530f5c6c30SJisheng Zhang } else { 41540f5c6c30SJisheng Zhang napi_enable(&pp->napi); 41550f5c6c30SJisheng Zhang } 41569a401deaSGregory CLEMENT 41579a401deaSGregory CLEMENT netif_tx_start_all_queues(pp->dev); 41589a401deaSGregory CLEMENT 41599a401deaSGregory CLEMENT return 0; 41609a401deaSGregory CLEMENT } 41619a401deaSGregory CLEMENT 41629a401deaSGregory CLEMENT static int mvneta_ethtool_set_rxfh(struct net_device *dev, const u32 *indir, 41639a401deaSGregory CLEMENT const u8 *key, const u8 hfunc) 41649a401deaSGregory CLEMENT { 41659a401deaSGregory CLEMENT struct mvneta_port *pp = netdev_priv(dev); 41662636ac3cSMarcin Wojtas 41672636ac3cSMarcin Wojtas /* Current code for Armada 3700 doesn't support RSS features yet */ 41682636ac3cSMarcin Wojtas if (pp->neta_armada3700) 41692636ac3cSMarcin Wojtas return -EOPNOTSUPP; 41702636ac3cSMarcin Wojtas 41719a401deaSGregory CLEMENT /* We require at least one supported parameter to be changed 41729a401deaSGregory CLEMENT * and no change in any of the unsupported parameters 41739a401deaSGregory CLEMENT */ 41749a401deaSGregory CLEMENT if (key || 41759a401deaSGregory CLEMENT (hfunc != ETH_RSS_HASH_NO_CHANGE && hfunc != ETH_RSS_HASH_TOP)) 41769a401deaSGregory CLEMENT return -EOPNOTSUPP; 41779a401deaSGregory CLEMENT 41789a401deaSGregory CLEMENT if (!indir) 41799a401deaSGregory CLEMENT return 0; 41809a401deaSGregory CLEMENT 41819a401deaSGregory CLEMENT memcpy(pp->indir, indir, MVNETA_RSS_LU_TABLE_SIZE); 41829a401deaSGregory CLEMENT 41839a401deaSGregory CLEMENT return mvneta_config_rss(pp); 41849a401deaSGregory CLEMENT } 41859a401deaSGregory CLEMENT 41869a401deaSGregory CLEMENT static int mvneta_ethtool_get_rxfh(struct net_device *dev, u32 *indir, u8 *key, 41879a401deaSGregory CLEMENT u8 *hfunc) 41889a401deaSGregory CLEMENT { 41899a401deaSGregory CLEMENT struct mvneta_port *pp = netdev_priv(dev); 41909a401deaSGregory CLEMENT 41912636ac3cSMarcin Wojtas /* Current code for Armada 3700 doesn't support RSS features yet */ 41922636ac3cSMarcin Wojtas if (pp->neta_armada3700) 41932636ac3cSMarcin Wojtas return -EOPNOTSUPP; 41942636ac3cSMarcin Wojtas 41959a401deaSGregory CLEMENT if (hfunc) 41969a401deaSGregory CLEMENT *hfunc = ETH_RSS_HASH_TOP; 41979a401deaSGregory CLEMENT 41989a401deaSGregory CLEMENT if (!indir) 41999a401deaSGregory CLEMENT return 0; 42009a401deaSGregory CLEMENT 42019a401deaSGregory CLEMENT memcpy(indir, pp->indir, MVNETA_RSS_LU_TABLE_SIZE); 42029a401deaSGregory CLEMENT 42039a401deaSGregory CLEMENT return 0; 42049a401deaSGregory CLEMENT } 42059a401deaSGregory CLEMENT 4206b60a00f9SJingju Hou static void mvneta_ethtool_get_wol(struct net_device *dev, 4207b60a00f9SJingju Hou struct ethtool_wolinfo *wol) 4208b60a00f9SJingju Hou { 4209503f9aa9SRussell King struct mvneta_port *pp = netdev_priv(dev); 4210b60a00f9SJingju Hou 4211503f9aa9SRussell King phylink_ethtool_get_wol(pp->phylink, wol); 4212b60a00f9SJingju Hou } 4213b60a00f9SJingju Hou 4214b60a00f9SJingju Hou static int mvneta_ethtool_set_wol(struct net_device *dev, 4215b60a00f9SJingju Hou struct ethtool_wolinfo *wol) 4216b60a00f9SJingju Hou { 4217503f9aa9SRussell King struct mvneta_port *pp = netdev_priv(dev); 421882960fffSJisheng Zhang int ret; 421982960fffSJisheng Zhang 4220503f9aa9SRussell King ret = phylink_ethtool_set_wol(pp->phylink, wol); 422182960fffSJisheng Zhang if (!ret) 422282960fffSJisheng Zhang device_set_wakeup_enable(&dev->dev, !!wol->wolopts); 422382960fffSJisheng Zhang 422482960fffSJisheng Zhang return ret; 4225b60a00f9SJingju Hou } 4226b60a00f9SJingju Hou 42276d81f451SRussell King static int mvneta_ethtool_get_eee(struct net_device *dev, 42286d81f451SRussell King struct ethtool_eee *eee) 42296d81f451SRussell King { 42306d81f451SRussell King struct mvneta_port *pp = netdev_priv(dev); 42316d81f451SRussell King u32 lpi_ctl0; 42326d81f451SRussell King 42336d81f451SRussell King lpi_ctl0 = mvreg_read(pp, MVNETA_LPI_CTRL_0); 42346d81f451SRussell King 42356d81f451SRussell King eee->eee_enabled = pp->eee_enabled; 42366d81f451SRussell King eee->eee_active = pp->eee_active; 42376d81f451SRussell King eee->tx_lpi_enabled = pp->tx_lpi_enabled; 42386d81f451SRussell King eee->tx_lpi_timer = (lpi_ctl0) >> 8; // * scale; 42396d81f451SRussell King 42406d81f451SRussell King return phylink_ethtool_get_eee(pp->phylink, eee); 42416d81f451SRussell King } 42426d81f451SRussell King 42436d81f451SRussell King static int mvneta_ethtool_set_eee(struct net_device *dev, 42446d81f451SRussell King struct ethtool_eee *eee) 42456d81f451SRussell King { 42466d81f451SRussell King struct mvneta_port *pp = netdev_priv(dev); 42476d81f451SRussell King u32 lpi_ctl0; 42486d81f451SRussell King 42496d81f451SRussell King /* The Armada 37x documents do not give limits for this other than 42506d81f451SRussell King * it being an 8-bit register. */ 42516d81f451SRussell King if (eee->tx_lpi_enabled && 42526d81f451SRussell King (eee->tx_lpi_timer < 0 || eee->tx_lpi_timer > 255)) 42536d81f451SRussell King return -EINVAL; 42546d81f451SRussell King 42556d81f451SRussell King lpi_ctl0 = mvreg_read(pp, MVNETA_LPI_CTRL_0); 42566d81f451SRussell King lpi_ctl0 &= ~(0xff << 8); 42576d81f451SRussell King lpi_ctl0 |= eee->tx_lpi_timer << 8; 42586d81f451SRussell King mvreg_write(pp, MVNETA_LPI_CTRL_0, lpi_ctl0); 42596d81f451SRussell King 42606d81f451SRussell King pp->eee_enabled = eee->eee_enabled; 42616d81f451SRussell King pp->tx_lpi_enabled = eee->tx_lpi_enabled; 42626d81f451SRussell King 42636d81f451SRussell King mvneta_set_eee(pp, eee->tx_lpi_enabled && eee->eee_enabled); 42646d81f451SRussell King 42656d81f451SRussell King return phylink_ethtool_set_eee(pp->phylink, eee); 42666d81f451SRussell King } 42676d81f451SRussell King 4268c5aff182SThomas Petazzoni static const struct net_device_ops mvneta_netdev_ops = { 4269c5aff182SThomas Petazzoni .ndo_open = mvneta_open, 4270c5aff182SThomas Petazzoni .ndo_stop = mvneta_stop, 4271c5aff182SThomas Petazzoni .ndo_start_xmit = mvneta_tx, 4272c5aff182SThomas Petazzoni .ndo_set_rx_mode = mvneta_set_rx_mode, 4273c5aff182SThomas Petazzoni .ndo_set_mac_address = mvneta_set_mac_addr, 4274c5aff182SThomas Petazzoni .ndo_change_mtu = mvneta_change_mtu, 4275b65657fcSSimon Guinot .ndo_fix_features = mvneta_fix_features, 4276c5aff182SThomas Petazzoni .ndo_get_stats64 = mvneta_get_stats64, 427715f59456SThomas Petazzoni .ndo_do_ioctl = mvneta_ioctl, 4278c5aff182SThomas Petazzoni }; 4279c5aff182SThomas Petazzoni 42804581be42SJisheng Zhang static const struct ethtool_ops mvneta_eth_tool_ops = { 4281503f9aa9SRussell King .nway_reset = mvneta_ethtool_nway_reset, 4282c5aff182SThomas Petazzoni .get_link = ethtool_op_get_link, 4283c5aff182SThomas Petazzoni .set_coalesce = mvneta_ethtool_set_coalesce, 4284c5aff182SThomas Petazzoni .get_coalesce = mvneta_ethtool_get_coalesce, 4285c5aff182SThomas Petazzoni .get_drvinfo = mvneta_ethtool_get_drvinfo, 4286c5aff182SThomas Petazzoni .get_ringparam = mvneta_ethtool_get_ringparam, 4287c5aff182SThomas Petazzoni .set_ringparam = mvneta_ethtool_set_ringparam, 42884932a918SRussell King .get_pauseparam = mvneta_ethtool_get_pauseparam, 42894932a918SRussell King .set_pauseparam = mvneta_ethtool_set_pauseparam, 42909b0cdefaSRussell King .get_strings = mvneta_ethtool_get_strings, 42919b0cdefaSRussell King .get_ethtool_stats = mvneta_ethtool_get_stats, 42929b0cdefaSRussell King .get_sset_count = mvneta_ethtool_get_sset_count, 42939a401deaSGregory CLEMENT .get_rxfh_indir_size = mvneta_ethtool_get_rxfh_indir_size, 42949a401deaSGregory CLEMENT .get_rxnfc = mvneta_ethtool_get_rxnfc, 42959a401deaSGregory CLEMENT .get_rxfh = mvneta_ethtool_get_rxfh, 42969a401deaSGregory CLEMENT .set_rxfh = mvneta_ethtool_set_rxfh, 4297503f9aa9SRussell King .get_link_ksettings = mvneta_ethtool_get_link_ksettings, 4298013ad40dSPhilippe Reynes .set_link_ksettings = mvneta_ethtool_set_link_ksettings, 4299b60a00f9SJingju Hou .get_wol = mvneta_ethtool_get_wol, 4300b60a00f9SJingju Hou .set_wol = mvneta_ethtool_set_wol, 43016d81f451SRussell King .get_eee = mvneta_ethtool_get_eee, 43026d81f451SRussell King .set_eee = mvneta_ethtool_set_eee, 4303c5aff182SThomas Petazzoni }; 4304c5aff182SThomas Petazzoni 4305c5aff182SThomas Petazzoni /* Initialize hw */ 43069672850bSEzequiel Garcia static int mvneta_init(struct device *dev, struct mvneta_port *pp) 4307c5aff182SThomas Petazzoni { 4308c5aff182SThomas Petazzoni int queue; 4309c5aff182SThomas Petazzoni 4310c5aff182SThomas Petazzoni /* Disable port */ 4311c5aff182SThomas Petazzoni mvneta_port_disable(pp); 4312c5aff182SThomas Petazzoni 4313c5aff182SThomas Petazzoni /* Set port default values */ 4314c5aff182SThomas Petazzoni mvneta_defaults_set(pp); 4315c5aff182SThomas Petazzoni 43165d6312edSMarkus Elfring pp->txqs = devm_kcalloc(dev, txq_number, sizeof(*pp->txqs), GFP_KERNEL); 4317c5aff182SThomas Petazzoni if (!pp->txqs) 4318c5aff182SThomas Petazzoni return -ENOMEM; 4319c5aff182SThomas Petazzoni 4320c5aff182SThomas Petazzoni /* Initialize TX descriptor rings */ 4321c5aff182SThomas Petazzoni for (queue = 0; queue < txq_number; queue++) { 4322c5aff182SThomas Petazzoni struct mvneta_tx_queue *txq = &pp->txqs[queue]; 4323c5aff182SThomas Petazzoni txq->id = queue; 4324c5aff182SThomas Petazzoni txq->size = pp->tx_ring_size; 4325c5aff182SThomas Petazzoni txq->done_pkts_coal = MVNETA_TXDONE_COAL_PKTS; 4326c5aff182SThomas Petazzoni } 4327c5aff182SThomas Petazzoni 43285d6312edSMarkus Elfring pp->rxqs = devm_kcalloc(dev, rxq_number, sizeof(*pp->rxqs), GFP_KERNEL); 43299672850bSEzequiel Garcia if (!pp->rxqs) 4330c5aff182SThomas Petazzoni return -ENOMEM; 4331c5aff182SThomas Petazzoni 4332c5aff182SThomas Petazzoni /* Create Rx descriptor rings */ 4333c5aff182SThomas Petazzoni for (queue = 0; queue < rxq_number; queue++) { 4334c5aff182SThomas Petazzoni struct mvneta_rx_queue *rxq = &pp->rxqs[queue]; 4335c5aff182SThomas Petazzoni rxq->id = queue; 4336c5aff182SThomas Petazzoni rxq->size = pp->rx_ring_size; 4337c5aff182SThomas Petazzoni rxq->pkts_coal = MVNETA_RX_COAL_PKTS; 4338c5aff182SThomas Petazzoni rxq->time_coal = MVNETA_RX_COAL_USEC; 433929110630SMarkus Elfring rxq->buf_virt_addr 434029110630SMarkus Elfring = devm_kmalloc_array(pp->dev->dev.parent, 434129110630SMarkus Elfring rxq->size, 434229110630SMarkus Elfring sizeof(*rxq->buf_virt_addr), 4343f88bee1cSGregory CLEMENT GFP_KERNEL); 4344f88bee1cSGregory CLEMENT if (!rxq->buf_virt_addr) 4345f88bee1cSGregory CLEMENT return -ENOMEM; 4346c5aff182SThomas Petazzoni } 4347c5aff182SThomas Petazzoni 4348c5aff182SThomas Petazzoni return 0; 4349c5aff182SThomas Petazzoni } 4350c5aff182SThomas Petazzoni 4351c5aff182SThomas Petazzoni /* platform glue : initialize decoding windows */ 435203ce758eSGreg KH static void mvneta_conf_mbus_windows(struct mvneta_port *pp, 4353c5aff182SThomas Petazzoni const struct mbus_dram_target_info *dram) 4354c5aff182SThomas Petazzoni { 4355c5aff182SThomas Petazzoni u32 win_enable; 4356c5aff182SThomas Petazzoni u32 win_protect; 4357c5aff182SThomas Petazzoni int i; 4358c5aff182SThomas Petazzoni 4359c5aff182SThomas Petazzoni for (i = 0; i < 6; i++) { 4360c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_WIN_BASE(i), 0); 4361c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_WIN_SIZE(i), 0); 4362c5aff182SThomas Petazzoni 4363c5aff182SThomas Petazzoni if (i < 4) 4364c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_WIN_REMAP(i), 0); 4365c5aff182SThomas Petazzoni } 4366c5aff182SThomas Petazzoni 4367c5aff182SThomas Petazzoni win_enable = 0x3f; 4368c5aff182SThomas Petazzoni win_protect = 0; 4369c5aff182SThomas Petazzoni 43702636ac3cSMarcin Wojtas if (dram) { 4371c5aff182SThomas Petazzoni for (i = 0; i < dram->num_cs; i++) { 4372c5aff182SThomas Petazzoni const struct mbus_dram_window *cs = dram->cs + i; 43732636ac3cSMarcin Wojtas 43742636ac3cSMarcin Wojtas mvreg_write(pp, MVNETA_WIN_BASE(i), 43752636ac3cSMarcin Wojtas (cs->base & 0xffff0000) | 43762636ac3cSMarcin Wojtas (cs->mbus_attr << 8) | 43772636ac3cSMarcin Wojtas dram->mbus_dram_target_id); 4378c5aff182SThomas Petazzoni 4379c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_WIN_SIZE(i), 4380c5aff182SThomas Petazzoni (cs->size - 1) & 0xffff0000); 4381c5aff182SThomas Petazzoni 4382c5aff182SThomas Petazzoni win_enable &= ~(1 << i); 4383c5aff182SThomas Petazzoni win_protect |= 3 << (2 * i); 4384c5aff182SThomas Petazzoni } 43852636ac3cSMarcin Wojtas } else { 43862636ac3cSMarcin Wojtas /* For Armada3700 open default 4GB Mbus window, leaving 43872636ac3cSMarcin Wojtas * arbitration of target/attribute to a different layer 43882636ac3cSMarcin Wojtas * of configuration. 43892636ac3cSMarcin Wojtas */ 43902636ac3cSMarcin Wojtas mvreg_write(pp, MVNETA_WIN_SIZE(0), 0xffff0000); 43912636ac3cSMarcin Wojtas win_enable &= ~BIT(0); 43922636ac3cSMarcin Wojtas win_protect = 3; 43932636ac3cSMarcin Wojtas } 4394c5aff182SThomas Petazzoni 4395c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_BASE_ADDR_ENABLE, win_enable); 4396db6ba9a5SMarcin Wojtas mvreg_write(pp, MVNETA_ACCESS_PROTECT_ENABLE, win_protect); 4397c5aff182SThomas Petazzoni } 4398c5aff182SThomas Petazzoni 4399c5aff182SThomas Petazzoni /* Power up the port */ 44003f1dd4bcSThomas Petazzoni static int mvneta_port_power_up(struct mvneta_port *pp, int phy_mode) 4401c5aff182SThomas Petazzoni { 4402c5aff182SThomas Petazzoni /* MAC Cause register should be cleared */ 4403c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_UNIT_INTR_CAUSE, 0); 4404c5aff182SThomas Petazzoni 440532699954SRussell King if (phy_mode == PHY_INTERFACE_MODE_QSGMII) 44063f1dd4bcSThomas Petazzoni mvreg_write(pp, MVNETA_SERDES_CFG, MVNETA_QSGMII_SERDES_PROTO); 440722f4bf8aSRussell King else if (phy_mode == PHY_INTERFACE_MODE_SGMII || 440822f4bf8aSRussell King phy_mode == PHY_INTERFACE_MODE_1000BASEX) 44093f1dd4bcSThomas Petazzoni mvreg_write(pp, MVNETA_SERDES_CFG, MVNETA_SGMII_SERDES_PROTO); 441032699954SRussell King else if (!phy_interface_mode_is_rgmii(phy_mode)) 44113f1dd4bcSThomas Petazzoni return -EINVAL; 44123f1dd4bcSThomas Petazzoni 44133f1dd4bcSThomas Petazzoni return 0; 4414c5aff182SThomas Petazzoni } 4415c5aff182SThomas Petazzoni 4416c5aff182SThomas Petazzoni /* Device initialization routine */ 441703ce758eSGreg KH static int mvneta_probe(struct platform_device *pdev) 4418c5aff182SThomas Petazzoni { 4419c3f0dd38SThomas Petazzoni struct resource *res; 4420c5aff182SThomas Petazzoni struct device_node *dn = pdev->dev.of_node; 4421dc35a10fSMarcin Wojtas struct device_node *bm_node; 4422c5aff182SThomas Petazzoni struct mvneta_port *pp; 4423c5aff182SThomas Petazzoni struct net_device *dev; 4424503f9aa9SRussell King struct phylink *phylink; 44258cc3e439SThomas Petazzoni const char *dt_mac_addr; 44268cc3e439SThomas Petazzoni char hw_mac_addr[ETH_ALEN]; 44278cc3e439SThomas Petazzoni const char *mac_from; 44289110ee07SMarcin Wojtas int tx_csum_limit; 4429c5aff182SThomas Petazzoni int phy_mode; 4430c5aff182SThomas Petazzoni int err; 443112bb03b4SMaxime Ripard int cpu; 4432c5aff182SThomas Petazzoni 4433ee40a116SWilly Tarreau dev = alloc_etherdev_mqs(sizeof(struct mvneta_port), txq_number, rxq_number); 4434c5aff182SThomas Petazzoni if (!dev) 4435c5aff182SThomas Petazzoni return -ENOMEM; 4436c5aff182SThomas Petazzoni 4437c5aff182SThomas Petazzoni dev->irq = irq_of_parse_and_map(dn, 0); 4438c5aff182SThomas Petazzoni if (dev->irq == 0) { 4439c5aff182SThomas Petazzoni err = -EINVAL; 4440c5aff182SThomas Petazzoni goto err_free_netdev; 4441c5aff182SThomas Petazzoni } 4442c5aff182SThomas Petazzoni 4443c5aff182SThomas Petazzoni phy_mode = of_get_phy_mode(dn); 4444c5aff182SThomas Petazzoni if (phy_mode < 0) { 4445c5aff182SThomas Petazzoni dev_err(&pdev->dev, "incorrect phy-mode\n"); 4446c5aff182SThomas Petazzoni err = -EINVAL; 4447503f9aa9SRussell King goto err_free_irq; 4448503f9aa9SRussell King } 4449503f9aa9SRussell King 4450503f9aa9SRussell King phylink = phylink_create(dev, pdev->dev.fwnode, phy_mode, 4451503f9aa9SRussell King &mvneta_phylink_ops); 4452503f9aa9SRussell King if (IS_ERR(phylink)) { 4453503f9aa9SRussell King err = PTR_ERR(phylink); 4454503f9aa9SRussell King goto err_free_irq; 4455c5aff182SThomas Petazzoni } 4456c5aff182SThomas Petazzoni 4457c5aff182SThomas Petazzoni dev->tx_queue_len = MVNETA_MAX_TXD; 4458c5aff182SThomas Petazzoni dev->watchdog_timeo = 5 * HZ; 4459c5aff182SThomas Petazzoni dev->netdev_ops = &mvneta_netdev_ops; 4460c5aff182SThomas Petazzoni 44617ad24ea4SWilfried Klaebe dev->ethtool_ops = &mvneta_eth_tool_ops; 4462c5aff182SThomas Petazzoni 4463c5aff182SThomas Petazzoni pp = netdev_priv(dev); 44641c2722a9SGregory CLEMENT spin_lock_init(&pp->lock); 4465503f9aa9SRussell King pp->phylink = phylink; 4466c5aff182SThomas Petazzoni pp->phy_interface = phy_mode; 4467503f9aa9SRussell King pp->dn = dn; 4468c5aff182SThomas Petazzoni 446990b74c01SGregory CLEMENT pp->rxq_def = rxq_def; 44709a401deaSGregory CLEMENT pp->indir[0] = rxq_def; 44719a401deaSGregory CLEMENT 44722636ac3cSMarcin Wojtas /* Get special SoC configurations */ 44732636ac3cSMarcin Wojtas if (of_device_is_compatible(dn, "marvell,armada-3700-neta")) 44742636ac3cSMarcin Wojtas pp->neta_armada3700 = true; 44752636ac3cSMarcin Wojtas 44762804ba4eSJisheng Zhang pp->clk = devm_clk_get(&pdev->dev, "core"); 44772804ba4eSJisheng Zhang if (IS_ERR(pp->clk)) 4478189dd626SThomas Petazzoni pp->clk = devm_clk_get(&pdev->dev, NULL); 4479189dd626SThomas Petazzoni if (IS_ERR(pp->clk)) { 4480189dd626SThomas Petazzoni err = PTR_ERR(pp->clk); 4481503f9aa9SRussell King goto err_free_phylink; 4482189dd626SThomas Petazzoni } 4483189dd626SThomas Petazzoni 4484189dd626SThomas Petazzoni clk_prepare_enable(pp->clk); 4485189dd626SThomas Petazzoni 448615cc4a4aSJisheng Zhang pp->clk_bus = devm_clk_get(&pdev->dev, "bus"); 448715cc4a4aSJisheng Zhang if (!IS_ERR(pp->clk_bus)) 448815cc4a4aSJisheng Zhang clk_prepare_enable(pp->clk_bus); 448915cc4a4aSJisheng Zhang 4490c3f0dd38SThomas Petazzoni res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 4491c3f0dd38SThomas Petazzoni pp->base = devm_ioremap_resource(&pdev->dev, res); 4492c3f0dd38SThomas Petazzoni if (IS_ERR(pp->base)) { 4493c3f0dd38SThomas Petazzoni err = PTR_ERR(pp->base); 44945445eaf3SArnaud Patard \(Rtp\) goto err_clk; 44955445eaf3SArnaud Patard \(Rtp\) } 44965445eaf3SArnaud Patard \(Rtp\) 449712bb03b4SMaxime Ripard /* Alloc per-cpu port structure */ 449812bb03b4SMaxime Ripard pp->ports = alloc_percpu(struct mvneta_pcpu_port); 449912bb03b4SMaxime Ripard if (!pp->ports) { 450012bb03b4SMaxime Ripard err = -ENOMEM; 450112bb03b4SMaxime Ripard goto err_clk; 450212bb03b4SMaxime Ripard } 450312bb03b4SMaxime Ripard 450474c41b04Swilly tarreau /* Alloc per-cpu stats */ 45051c213bd2SWANG Cong pp->stats = netdev_alloc_pcpu_stats(struct mvneta_pcpu_stats); 450674c41b04Swilly tarreau if (!pp->stats) { 450774c41b04Swilly tarreau err = -ENOMEM; 450812bb03b4SMaxime Ripard goto err_free_ports; 450974c41b04Swilly tarreau } 451074c41b04Swilly tarreau 45118cc3e439SThomas Petazzoni dt_mac_addr = of_get_mac_address(dn); 45126c7a9a3cSLuka Perkov if (dt_mac_addr) { 45138cc3e439SThomas Petazzoni mac_from = "device tree"; 45148cc3e439SThomas Petazzoni memcpy(dev->dev_addr, dt_mac_addr, ETH_ALEN); 45158cc3e439SThomas Petazzoni } else { 45168cc3e439SThomas Petazzoni mvneta_get_mac_addr(pp, hw_mac_addr); 45178cc3e439SThomas Petazzoni if (is_valid_ether_addr(hw_mac_addr)) { 45188cc3e439SThomas Petazzoni mac_from = "hardware"; 45198cc3e439SThomas Petazzoni memcpy(dev->dev_addr, hw_mac_addr, ETH_ALEN); 45208cc3e439SThomas Petazzoni } else { 45218cc3e439SThomas Petazzoni mac_from = "random"; 45228cc3e439SThomas Petazzoni eth_hw_addr_random(dev); 45238cc3e439SThomas Petazzoni } 45248cc3e439SThomas Petazzoni } 45258cc3e439SThomas Petazzoni 45269110ee07SMarcin Wojtas if (!of_property_read_u32(dn, "tx-csum-limit", &tx_csum_limit)) { 45279110ee07SMarcin Wojtas if (tx_csum_limit < 0 || 45289110ee07SMarcin Wojtas tx_csum_limit > MVNETA_TX_CSUM_MAX_SIZE) { 45299110ee07SMarcin Wojtas tx_csum_limit = MVNETA_TX_CSUM_DEF_SIZE; 45309110ee07SMarcin Wojtas dev_info(&pdev->dev, 45319110ee07SMarcin Wojtas "Wrong TX csum limit in DT, set to %dB\n", 45329110ee07SMarcin Wojtas MVNETA_TX_CSUM_DEF_SIZE); 45339110ee07SMarcin Wojtas } 45349110ee07SMarcin Wojtas } else if (of_device_is_compatible(dn, "marvell,armada-370-neta")) { 45359110ee07SMarcin Wojtas tx_csum_limit = MVNETA_TX_CSUM_DEF_SIZE; 45369110ee07SMarcin Wojtas } else { 45379110ee07SMarcin Wojtas tx_csum_limit = MVNETA_TX_CSUM_MAX_SIZE; 45389110ee07SMarcin Wojtas } 45399110ee07SMarcin Wojtas 45409110ee07SMarcin Wojtas pp->tx_csum_limit = tx_csum_limit; 4541b65657fcSSimon Guinot 45429768b45cSJane Li pp->dram_target_info = mv_mbus_dram_info(); 45432636ac3cSMarcin Wojtas /* Armada3700 requires setting default configuration of Mbus 45442636ac3cSMarcin Wojtas * windows, however without using filled mbus_dram_target_info 45452636ac3cSMarcin Wojtas * structure. 45462636ac3cSMarcin Wojtas */ 45479768b45cSJane Li if (pp->dram_target_info || pp->neta_armada3700) 45489768b45cSJane Li mvneta_conf_mbus_windows(pp, pp->dram_target_info); 4549dc35a10fSMarcin Wojtas 4550c5aff182SThomas Petazzoni pp->tx_ring_size = MVNETA_MAX_TXD; 4551c5aff182SThomas Petazzoni pp->rx_ring_size = MVNETA_MAX_RXD; 4552c5aff182SThomas Petazzoni 4553c5aff182SThomas Petazzoni pp->dev = dev; 4554c5aff182SThomas Petazzoni SET_NETDEV_DEV(dev, &pdev->dev); 4555c5aff182SThomas Petazzoni 4556dc35a10fSMarcin Wojtas pp->id = global_port_id++; 4557562e2f46SYelena Krivosheev pp->rx_offset_correction = 0; /* not relevant for SW BM */ 4558dc35a10fSMarcin Wojtas 4559dc35a10fSMarcin Wojtas /* Obtain access to BM resources if enabled and already initialized */ 4560dc35a10fSMarcin Wojtas bm_node = of_parse_phandle(dn, "buffer-manager", 0); 4561965cbbecSGregory CLEMENT if (bm_node) { 4562965cbbecSGregory CLEMENT pp->bm_priv = mvneta_bm_get(bm_node); 4563965cbbecSGregory CLEMENT if (pp->bm_priv) { 4564dc35a10fSMarcin Wojtas err = mvneta_bm_port_init(pdev, pp); 4565dc35a10fSMarcin Wojtas if (err < 0) { 4566965cbbecSGregory CLEMENT dev_info(&pdev->dev, 4567965cbbecSGregory CLEMENT "use SW buffer management\n"); 4568965cbbecSGregory CLEMENT mvneta_bm_put(pp->bm_priv); 4569dc35a10fSMarcin Wojtas pp->bm_priv = NULL; 4570dc35a10fSMarcin Wojtas } 4571dc35a10fSMarcin Wojtas } 4572562e2f46SYelena Krivosheev /* Set RX packet offset correction for platforms, whose 4573562e2f46SYelena Krivosheev * NET_SKB_PAD, exceeds 64B. It should be 64B for 64-bit 4574562e2f46SYelena Krivosheev * platforms and 0B for 32-bit ones. 4575562e2f46SYelena Krivosheev */ 4576562e2f46SYelena Krivosheev pp->rx_offset_correction = max(0, 4577562e2f46SYelena Krivosheev NET_SKB_PAD - 4578562e2f46SYelena Krivosheev MVNETA_RX_PKT_OFFSET_CORRECTION); 4579965cbbecSGregory CLEMENT } 4580d4e4da00SPeter Chen of_node_put(bm_node); 4581dc35a10fSMarcin Wojtas 45829672850bSEzequiel Garcia err = mvneta_init(&pdev->dev, pp); 45839672850bSEzequiel Garcia if (err < 0) 4584dc35a10fSMarcin Wojtas goto err_netdev; 45853f1dd4bcSThomas Petazzoni 45863f1dd4bcSThomas Petazzoni err = mvneta_port_power_up(pp, phy_mode); 45873f1dd4bcSThomas Petazzoni if (err < 0) { 45883f1dd4bcSThomas Petazzoni dev_err(&pdev->dev, "can't power up port\n"); 4589dc35a10fSMarcin Wojtas goto err_netdev; 45903f1dd4bcSThomas Petazzoni } 4591c5aff182SThomas Petazzoni 45922636ac3cSMarcin Wojtas /* Armada3700 network controller does not support per-cpu 45932636ac3cSMarcin Wojtas * operation, so only single NAPI should be initialized. 45942636ac3cSMarcin Wojtas */ 45952636ac3cSMarcin Wojtas if (pp->neta_armada3700) { 45962636ac3cSMarcin Wojtas netif_napi_add(dev, &pp->napi, mvneta_poll, NAPI_POLL_WEIGHT); 45972636ac3cSMarcin Wojtas } else { 459812bb03b4SMaxime Ripard for_each_present_cpu(cpu) { 45992636ac3cSMarcin Wojtas struct mvneta_pcpu_port *port = 46002636ac3cSMarcin Wojtas per_cpu_ptr(pp->ports, cpu); 460112bb03b4SMaxime Ripard 46022636ac3cSMarcin Wojtas netif_napi_add(dev, &port->napi, mvneta_poll, 46032636ac3cSMarcin Wojtas NAPI_POLL_WEIGHT); 460412bb03b4SMaxime Ripard port->pp = pp; 460512bb03b4SMaxime Ripard } 46062636ac3cSMarcin Wojtas } 4607c5aff182SThomas Petazzoni 46087772988aSJisheng Zhang dev->features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | 46097772988aSJisheng Zhang NETIF_F_TSO | NETIF_F_RXCSUM; 461001ef26caSEzequiel Garcia dev->hw_features |= dev->features; 461101ef26caSEzequiel Garcia dev->vlan_features |= dev->features; 461297db8afaSAndrew Lunn dev->priv_flags |= IFF_LIVE_ADDR_CHANGE; 46138eef5f97SEzequiel Garcia dev->gso_max_segs = MVNETA_MAX_TSO_SEGS; 4614b50b72deSwilly tarreau 46155777987eSJarod Wilson /* MTU range: 68 - 9676 */ 46165777987eSJarod Wilson dev->min_mtu = ETH_MIN_MTU; 46175777987eSJarod Wilson /* 9676 == 9700 - 20 and rounding to 8 */ 46185777987eSJarod Wilson dev->max_mtu = 9676; 46195777987eSJarod Wilson 4620c5aff182SThomas Petazzoni err = register_netdev(dev); 4621c5aff182SThomas Petazzoni if (err < 0) { 4622c5aff182SThomas Petazzoni dev_err(&pdev->dev, "failed to register\n"); 46239672850bSEzequiel Garcia goto err_free_stats; 4624c5aff182SThomas Petazzoni } 4625c5aff182SThomas Petazzoni 46268cc3e439SThomas Petazzoni netdev_info(dev, "Using %s mac address %pM\n", mac_from, 46278cc3e439SThomas Petazzoni dev->dev_addr); 4628c5aff182SThomas Petazzoni 4629c5aff182SThomas Petazzoni platform_set_drvdata(pdev, pp->dev); 4630c5aff182SThomas Petazzoni 4631c5aff182SThomas Petazzoni return 0; 4632c5aff182SThomas Petazzoni 4633dc35a10fSMarcin Wojtas err_netdev: 4634dc35a10fSMarcin Wojtas unregister_netdev(dev); 4635dc35a10fSMarcin Wojtas if (pp->bm_priv) { 4636dc35a10fSMarcin Wojtas mvneta_bm_pool_destroy(pp->bm_priv, pp->pool_long, 1 << pp->id); 4637dc35a10fSMarcin Wojtas mvneta_bm_pool_destroy(pp->bm_priv, pp->pool_short, 4638dc35a10fSMarcin Wojtas 1 << pp->id); 4639965cbbecSGregory CLEMENT mvneta_bm_put(pp->bm_priv); 4640dc35a10fSMarcin Wojtas } 464174c41b04Swilly tarreau err_free_stats: 464274c41b04Swilly tarreau free_percpu(pp->stats); 464312bb03b4SMaxime Ripard err_free_ports: 464412bb03b4SMaxime Ripard free_percpu(pp->ports); 46455445eaf3SArnaud Patard \(Rtp\) err_clk: 464615cc4a4aSJisheng Zhang clk_disable_unprepare(pp->clk_bus); 46475445eaf3SArnaud Patard \(Rtp\) clk_disable_unprepare(pp->clk); 4648503f9aa9SRussell King err_free_phylink: 4649503f9aa9SRussell King if (pp->phylink) 4650503f9aa9SRussell King phylink_destroy(pp->phylink); 4651c5aff182SThomas Petazzoni err_free_irq: 4652c5aff182SThomas Petazzoni irq_dispose_mapping(dev->irq); 4653c5aff182SThomas Petazzoni err_free_netdev: 4654c5aff182SThomas Petazzoni free_netdev(dev); 4655c5aff182SThomas Petazzoni return err; 4656c5aff182SThomas Petazzoni } 4657c5aff182SThomas Petazzoni 4658c5aff182SThomas Petazzoni /* Device removal routine */ 465903ce758eSGreg KH static int mvneta_remove(struct platform_device *pdev) 4660c5aff182SThomas Petazzoni { 4661c5aff182SThomas Petazzoni struct net_device *dev = platform_get_drvdata(pdev); 4662c5aff182SThomas Petazzoni struct mvneta_port *pp = netdev_priv(dev); 4663c5aff182SThomas Petazzoni 4664c5aff182SThomas Petazzoni unregister_netdev(dev); 466515cc4a4aSJisheng Zhang clk_disable_unprepare(pp->clk_bus); 4666189dd626SThomas Petazzoni clk_disable_unprepare(pp->clk); 466712bb03b4SMaxime Ripard free_percpu(pp->ports); 466874c41b04Swilly tarreau free_percpu(pp->stats); 4669c5aff182SThomas Petazzoni irq_dispose_mapping(dev->irq); 4670503f9aa9SRussell King phylink_destroy(pp->phylink); 4671c5aff182SThomas Petazzoni free_netdev(dev); 4672c5aff182SThomas Petazzoni 4673dc35a10fSMarcin Wojtas if (pp->bm_priv) { 4674dc35a10fSMarcin Wojtas mvneta_bm_pool_destroy(pp->bm_priv, pp->pool_long, 1 << pp->id); 4675dc35a10fSMarcin Wojtas mvneta_bm_pool_destroy(pp->bm_priv, pp->pool_short, 4676dc35a10fSMarcin Wojtas 1 << pp->id); 4677965cbbecSGregory CLEMENT mvneta_bm_put(pp->bm_priv); 4678dc35a10fSMarcin Wojtas } 4679dc35a10fSMarcin Wojtas 4680c5aff182SThomas Petazzoni return 0; 4681c5aff182SThomas Petazzoni } 4682c5aff182SThomas Petazzoni 46839768b45cSJane Li #ifdef CONFIG_PM_SLEEP 46849768b45cSJane Li static int mvneta_suspend(struct device *device) 46859768b45cSJane Li { 46861799cdd2SJisheng Zhang int queue; 46879768b45cSJane Li struct net_device *dev = dev_get_drvdata(device); 46889768b45cSJane Li struct mvneta_port *pp = netdev_priv(dev); 46899768b45cSJane Li 46901799cdd2SJisheng Zhang if (!netif_running(dev)) 46911799cdd2SJisheng Zhang goto clean_exit; 46921799cdd2SJisheng Zhang 46931799cdd2SJisheng Zhang if (!pp->neta_armada3700) { 46941799cdd2SJisheng Zhang spin_lock(&pp->lock); 46951799cdd2SJisheng Zhang pp->is_stopped = true; 46961799cdd2SJisheng Zhang spin_unlock(&pp->lock); 46971799cdd2SJisheng Zhang 46981799cdd2SJisheng Zhang cpuhp_state_remove_instance_nocalls(online_hpstate, 46991799cdd2SJisheng Zhang &pp->node_online); 47001799cdd2SJisheng Zhang cpuhp_state_remove_instance_nocalls(CPUHP_NET_MVNETA_DEAD, 47011799cdd2SJisheng Zhang &pp->node_dead); 47021799cdd2SJisheng Zhang } 47031799cdd2SJisheng Zhang 47043b8bc674SRussell King rtnl_lock(); 47051799cdd2SJisheng Zhang mvneta_stop_dev(pp); 47063b8bc674SRussell King rtnl_unlock(); 47071799cdd2SJisheng Zhang 47081799cdd2SJisheng Zhang for (queue = 0; queue < rxq_number; queue++) { 47091799cdd2SJisheng Zhang struct mvneta_rx_queue *rxq = &pp->rxqs[queue]; 47101799cdd2SJisheng Zhang 47111799cdd2SJisheng Zhang mvneta_rxq_drop_pkts(pp, rxq); 47121799cdd2SJisheng Zhang } 47131799cdd2SJisheng Zhang 47141799cdd2SJisheng Zhang for (queue = 0; queue < txq_number; queue++) { 47151799cdd2SJisheng Zhang struct mvneta_tx_queue *txq = &pp->txqs[queue]; 47161799cdd2SJisheng Zhang 47171799cdd2SJisheng Zhang mvneta_txq_hw_deinit(pp, txq); 47181799cdd2SJisheng Zhang } 47191799cdd2SJisheng Zhang 47201799cdd2SJisheng Zhang clean_exit: 47219768b45cSJane Li netif_device_detach(dev); 47229768b45cSJane Li clk_disable_unprepare(pp->clk_bus); 47239768b45cSJane Li clk_disable_unprepare(pp->clk); 47241799cdd2SJisheng Zhang 47259768b45cSJane Li return 0; 47269768b45cSJane Li } 47279768b45cSJane Li 47289768b45cSJane Li static int mvneta_resume(struct device *device) 47299768b45cSJane Li { 47309768b45cSJane Li struct platform_device *pdev = to_platform_device(device); 47319768b45cSJane Li struct net_device *dev = dev_get_drvdata(device); 47329768b45cSJane Li struct mvneta_port *pp = netdev_priv(dev); 47331799cdd2SJisheng Zhang int err, queue; 47349768b45cSJane Li 47359768b45cSJane Li clk_prepare_enable(pp->clk); 47369768b45cSJane Li if (!IS_ERR(pp->clk_bus)) 47379768b45cSJane Li clk_prepare_enable(pp->clk_bus); 47389768b45cSJane Li if (pp->dram_target_info || pp->neta_armada3700) 47399768b45cSJane Li mvneta_conf_mbus_windows(pp, pp->dram_target_info); 47409768b45cSJane Li if (pp->bm_priv) { 47419768b45cSJane Li err = mvneta_bm_port_init(pdev, pp); 47429768b45cSJane Li if (err < 0) { 47439768b45cSJane Li dev_info(&pdev->dev, "use SW buffer management\n"); 47449768b45cSJane Li pp->bm_priv = NULL; 47459768b45cSJane Li } 47469768b45cSJane Li } 47479768b45cSJane Li mvneta_defaults_set(pp); 47489768b45cSJane Li err = mvneta_port_power_up(pp, pp->phy_interface); 47499768b45cSJane Li if (err < 0) { 47509768b45cSJane Li dev_err(device, "can't power up port\n"); 47519768b45cSJane Li return err; 47529768b45cSJane Li } 47539768b45cSJane Li 47549768b45cSJane Li netif_device_attach(dev); 47551799cdd2SJisheng Zhang 47561799cdd2SJisheng Zhang if (!netif_running(dev)) 47571799cdd2SJisheng Zhang return 0; 47581799cdd2SJisheng Zhang 47591799cdd2SJisheng Zhang for (queue = 0; queue < rxq_number; queue++) { 47601799cdd2SJisheng Zhang struct mvneta_rx_queue *rxq = &pp->rxqs[queue]; 47611799cdd2SJisheng Zhang 47621799cdd2SJisheng Zhang rxq->next_desc_to_proc = 0; 47631799cdd2SJisheng Zhang mvneta_rxq_hw_init(pp, rxq); 4764d6956ac8SJisheng Zhang } 47651799cdd2SJisheng Zhang 47661799cdd2SJisheng Zhang for (queue = 0; queue < txq_number; queue++) { 47671799cdd2SJisheng Zhang struct mvneta_tx_queue *txq = &pp->txqs[queue]; 47681799cdd2SJisheng Zhang 47691799cdd2SJisheng Zhang txq->next_desc_to_proc = 0; 47701799cdd2SJisheng Zhang mvneta_txq_hw_init(pp, txq); 47711799cdd2SJisheng Zhang } 47721799cdd2SJisheng Zhang 47731799cdd2SJisheng Zhang if (!pp->neta_armada3700) { 47741799cdd2SJisheng Zhang spin_lock(&pp->lock); 47751799cdd2SJisheng Zhang pp->is_stopped = false; 47761799cdd2SJisheng Zhang spin_unlock(&pp->lock); 47771799cdd2SJisheng Zhang cpuhp_state_add_instance_nocalls(online_hpstate, 47781799cdd2SJisheng Zhang &pp->node_online); 47791799cdd2SJisheng Zhang cpuhp_state_add_instance_nocalls(CPUHP_NET_MVNETA_DEAD, 47801799cdd2SJisheng Zhang &pp->node_dead); 47811799cdd2SJisheng Zhang } 47821799cdd2SJisheng Zhang 47831799cdd2SJisheng Zhang rtnl_lock(); 47841799cdd2SJisheng Zhang mvneta_start_dev(pp); 47853b8bc674SRussell King rtnl_unlock(); 47861799cdd2SJisheng Zhang mvneta_set_rx_mode(dev); 4787d6956ac8SJisheng Zhang 47889768b45cSJane Li return 0; 47899768b45cSJane Li } 47909768b45cSJane Li #endif 47919768b45cSJane Li 47929768b45cSJane Li static SIMPLE_DEV_PM_OPS(mvneta_pm_ops, mvneta_suspend, mvneta_resume); 47939768b45cSJane Li 4794c5aff182SThomas Petazzoni static const struct of_device_id mvneta_match[] = { 4795c5aff182SThomas Petazzoni { .compatible = "marvell,armada-370-neta" }, 4796f522a975SSimon Guinot { .compatible = "marvell,armada-xp-neta" }, 47972636ac3cSMarcin Wojtas { .compatible = "marvell,armada-3700-neta" }, 4798c5aff182SThomas Petazzoni { } 4799c5aff182SThomas Petazzoni }; 4800c5aff182SThomas Petazzoni MODULE_DEVICE_TABLE(of, mvneta_match); 4801c5aff182SThomas Petazzoni 4802c5aff182SThomas Petazzoni static struct platform_driver mvneta_driver = { 4803c5aff182SThomas Petazzoni .probe = mvneta_probe, 480403ce758eSGreg KH .remove = mvneta_remove, 4805c5aff182SThomas Petazzoni .driver = { 4806c5aff182SThomas Petazzoni .name = MVNETA_DRIVER_NAME, 4807c5aff182SThomas Petazzoni .of_match_table = mvneta_match, 48089768b45cSJane Li .pm = &mvneta_pm_ops, 4809c5aff182SThomas Petazzoni }, 4810c5aff182SThomas Petazzoni }; 4811c5aff182SThomas Petazzoni 481284a3f4dbSSebastian Andrzej Siewior static int __init mvneta_driver_init(void) 481384a3f4dbSSebastian Andrzej Siewior { 481484a3f4dbSSebastian Andrzej Siewior int ret; 481584a3f4dbSSebastian Andrzej Siewior 481684a3f4dbSSebastian Andrzej Siewior ret = cpuhp_setup_state_multi(CPUHP_AP_ONLINE_DYN, "net/mvmeta:online", 481784a3f4dbSSebastian Andrzej Siewior mvneta_cpu_online, 481884a3f4dbSSebastian Andrzej Siewior mvneta_cpu_down_prepare); 481984a3f4dbSSebastian Andrzej Siewior if (ret < 0) 482084a3f4dbSSebastian Andrzej Siewior goto out; 482184a3f4dbSSebastian Andrzej Siewior online_hpstate = ret; 482284a3f4dbSSebastian Andrzej Siewior ret = cpuhp_setup_state_multi(CPUHP_NET_MVNETA_DEAD, "net/mvneta:dead", 482384a3f4dbSSebastian Andrzej Siewior NULL, mvneta_cpu_dead); 482484a3f4dbSSebastian Andrzej Siewior if (ret) 482584a3f4dbSSebastian Andrzej Siewior goto err_dead; 482684a3f4dbSSebastian Andrzej Siewior 482784a3f4dbSSebastian Andrzej Siewior ret = platform_driver_register(&mvneta_driver); 482884a3f4dbSSebastian Andrzej Siewior if (ret) 482984a3f4dbSSebastian Andrzej Siewior goto err; 483084a3f4dbSSebastian Andrzej Siewior return 0; 483184a3f4dbSSebastian Andrzej Siewior 483284a3f4dbSSebastian Andrzej Siewior err: 483384a3f4dbSSebastian Andrzej Siewior cpuhp_remove_multi_state(CPUHP_NET_MVNETA_DEAD); 483484a3f4dbSSebastian Andrzej Siewior err_dead: 483584a3f4dbSSebastian Andrzej Siewior cpuhp_remove_multi_state(online_hpstate); 483684a3f4dbSSebastian Andrzej Siewior out: 483784a3f4dbSSebastian Andrzej Siewior return ret; 483884a3f4dbSSebastian Andrzej Siewior } 483984a3f4dbSSebastian Andrzej Siewior module_init(mvneta_driver_init); 484084a3f4dbSSebastian Andrzej Siewior 484184a3f4dbSSebastian Andrzej Siewior static void __exit mvneta_driver_exit(void) 484284a3f4dbSSebastian Andrzej Siewior { 484384a3f4dbSSebastian Andrzej Siewior platform_driver_unregister(&mvneta_driver); 484484a3f4dbSSebastian Andrzej Siewior cpuhp_remove_multi_state(CPUHP_NET_MVNETA_DEAD); 484584a3f4dbSSebastian Andrzej Siewior cpuhp_remove_multi_state(online_hpstate); 484684a3f4dbSSebastian Andrzej Siewior } 484784a3f4dbSSebastian Andrzej Siewior module_exit(mvneta_driver_exit); 4848c5aff182SThomas Petazzoni 4849c5aff182SThomas Petazzoni MODULE_DESCRIPTION("Marvell NETA Ethernet Driver - www.marvell.com"); 4850c5aff182SThomas Petazzoni MODULE_AUTHOR("Rami Rosen <rosenr@marvell.com>, Thomas Petazzoni <thomas.petazzoni@free-electrons.com>"); 4851c5aff182SThomas Petazzoni MODULE_LICENSE("GPL"); 4852c5aff182SThomas Petazzoni 4853d3757ba4SJoe Perches module_param(rxq_number, int, 0444); 4854d3757ba4SJoe Perches module_param(txq_number, int, 0444); 4855c5aff182SThomas Petazzoni 4856d3757ba4SJoe Perches module_param(rxq_def, int, 0444); 4857d3757ba4SJoe Perches module_param(rx_copybreak, int, 0644); 4858