1c5aff182SThomas Petazzoni /* 2c5aff182SThomas Petazzoni * Driver for Marvell NETA network card for Armada XP and Armada 370 SoCs. 3c5aff182SThomas Petazzoni * 4c5aff182SThomas Petazzoni * Copyright (C) 2012 Marvell 5c5aff182SThomas Petazzoni * 6c5aff182SThomas Petazzoni * Rami Rosen <rosenr@marvell.com> 7c5aff182SThomas Petazzoni * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> 8c5aff182SThomas Petazzoni * 9c5aff182SThomas Petazzoni * This file is licensed under the terms of the GNU General Public 10c5aff182SThomas Petazzoni * License version 2. This program is licensed "as is" without any 11c5aff182SThomas Petazzoni * warranty of any kind, whether express or implied. 12c5aff182SThomas Petazzoni */ 13c5aff182SThomas Petazzoni 140e03f563SJisheng Zhang #include <linux/clk.h> 150e03f563SJisheng Zhang #include <linux/cpu.h> 16c5aff182SThomas Petazzoni #include <linux/etherdevice.h> 170e03f563SJisheng Zhang #include <linux/if_vlan.h> 18c5aff182SThomas Petazzoni #include <linux/inetdevice.h> 190e03f563SJisheng Zhang #include <linux/interrupt.h> 200e03f563SJisheng Zhang #include <linux/io.h> 210e03f563SJisheng Zhang #include <linux/kernel.h> 22c5aff182SThomas Petazzoni #include <linux/mbus.h> 23c5aff182SThomas Petazzoni #include <linux/module.h> 240e03f563SJisheng Zhang #include <linux/netdevice.h> 25c5aff182SThomas Petazzoni #include <linux/of.h> 260e03f563SJisheng Zhang #include <linux/of_address.h> 27c5aff182SThomas Petazzoni #include <linux/of_irq.h> 28c5aff182SThomas Petazzoni #include <linux/of_mdio.h> 29c5aff182SThomas Petazzoni #include <linux/of_net.h> 30a10c1c81SRussell King #include <linux/phy/phy.h> 31c5aff182SThomas Petazzoni #include <linux/phy.h> 32503f9aa9SRussell King #include <linux/phylink.h> 330e03f563SJisheng Zhang #include <linux/platform_device.h> 340e03f563SJisheng Zhang #include <linux/skbuff.h> 35baa11ebcSGregory CLEMENT #include <net/hwbm.h> 36dc35a10fSMarcin Wojtas #include "mvneta_bm.h" 370e03f563SJisheng Zhang #include <net/ip.h> 380e03f563SJisheng Zhang #include <net/ipv6.h> 390e03f563SJisheng Zhang #include <net/tso.h> 40568a3fa2SLorenzo Bianconi #include <net/page_pool.h> 410db51da7SLorenzo Bianconi #include <linux/bpf_trace.h> 42c5aff182SThomas Petazzoni 43c5aff182SThomas Petazzoni /* Registers */ 44c5aff182SThomas Petazzoni #define MVNETA_RXQ_CONFIG_REG(q) (0x1400 + ((q) << 2)) 45e5bdf689SMarcin Wojtas #define MVNETA_RXQ_HW_BUF_ALLOC BIT(0) 46dc35a10fSMarcin Wojtas #define MVNETA_RXQ_SHORT_POOL_ID_SHIFT 4 47dc35a10fSMarcin Wojtas #define MVNETA_RXQ_SHORT_POOL_ID_MASK 0x30 48dc35a10fSMarcin Wojtas #define MVNETA_RXQ_LONG_POOL_ID_SHIFT 6 49dc35a10fSMarcin Wojtas #define MVNETA_RXQ_LONG_POOL_ID_MASK 0xc0 50c5aff182SThomas Petazzoni #define MVNETA_RXQ_PKT_OFFSET_ALL_MASK (0xf << 8) 51c5aff182SThomas Petazzoni #define MVNETA_RXQ_PKT_OFFSET_MASK(offs) ((offs) << 8) 52c5aff182SThomas Petazzoni #define MVNETA_RXQ_THRESHOLD_REG(q) (0x14c0 + ((q) << 2)) 53c5aff182SThomas Petazzoni #define MVNETA_RXQ_NON_OCCUPIED(v) ((v) << 16) 54c5aff182SThomas Petazzoni #define MVNETA_RXQ_BASE_ADDR_REG(q) (0x1480 + ((q) << 2)) 55c5aff182SThomas Petazzoni #define MVNETA_RXQ_SIZE_REG(q) (0x14a0 + ((q) << 2)) 56c5aff182SThomas Petazzoni #define MVNETA_RXQ_BUF_SIZE_SHIFT 19 57c5aff182SThomas Petazzoni #define MVNETA_RXQ_BUF_SIZE_MASK (0x1fff << 19) 58c5aff182SThomas Petazzoni #define MVNETA_RXQ_STATUS_REG(q) (0x14e0 + ((q) << 2)) 59c5aff182SThomas Petazzoni #define MVNETA_RXQ_OCCUPIED_ALL_MASK 0x3fff 60c5aff182SThomas Petazzoni #define MVNETA_RXQ_STATUS_UPDATE_REG(q) (0x1500 + ((q) << 2)) 61c5aff182SThomas Petazzoni #define MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT 16 62c5aff182SThomas Petazzoni #define MVNETA_RXQ_ADD_NON_OCCUPIED_MAX 255 63dc35a10fSMarcin Wojtas #define MVNETA_PORT_POOL_BUFFER_SZ_REG(pool) (0x1700 + ((pool) << 2)) 64dc35a10fSMarcin Wojtas #define MVNETA_PORT_POOL_BUFFER_SZ_SHIFT 3 65dc35a10fSMarcin Wojtas #define MVNETA_PORT_POOL_BUFFER_SZ_MASK 0xfff8 66c5aff182SThomas Petazzoni #define MVNETA_PORT_RX_RESET 0x1cc0 67c5aff182SThomas Petazzoni #define MVNETA_PORT_RX_DMA_RESET BIT(0) 68c5aff182SThomas Petazzoni #define MVNETA_PHY_ADDR 0x2000 69c5aff182SThomas Petazzoni #define MVNETA_PHY_ADDR_MASK 0x1f 70c5aff182SThomas Petazzoni #define MVNETA_MBUS_RETRY 0x2010 71c5aff182SThomas Petazzoni #define MVNETA_UNIT_INTR_CAUSE 0x2080 72c5aff182SThomas Petazzoni #define MVNETA_UNIT_CONTROL 0x20B0 73c5aff182SThomas Petazzoni #define MVNETA_PHY_POLLING_ENABLE BIT(1) 74c5aff182SThomas Petazzoni #define MVNETA_WIN_BASE(w) (0x2200 + ((w) << 3)) 75c5aff182SThomas Petazzoni #define MVNETA_WIN_SIZE(w) (0x2204 + ((w) << 3)) 76c5aff182SThomas Petazzoni #define MVNETA_WIN_REMAP(w) (0x2280 + ((w) << 2)) 77c5aff182SThomas Petazzoni #define MVNETA_BASE_ADDR_ENABLE 0x2290 78db6ba9a5SMarcin Wojtas #define MVNETA_ACCESS_PROTECT_ENABLE 0x2294 79c5aff182SThomas Petazzoni #define MVNETA_PORT_CONFIG 0x2400 80c5aff182SThomas Petazzoni #define MVNETA_UNI_PROMISC_MODE BIT(0) 81c5aff182SThomas Petazzoni #define MVNETA_DEF_RXQ(q) ((q) << 1) 82c5aff182SThomas Petazzoni #define MVNETA_DEF_RXQ_ARP(q) ((q) << 4) 83c5aff182SThomas Petazzoni #define MVNETA_TX_UNSET_ERR_SUM BIT(12) 84c5aff182SThomas Petazzoni #define MVNETA_DEF_RXQ_TCP(q) ((q) << 16) 85c5aff182SThomas Petazzoni #define MVNETA_DEF_RXQ_UDP(q) ((q) << 19) 86c5aff182SThomas Petazzoni #define MVNETA_DEF_RXQ_BPDU(q) ((q) << 22) 87c5aff182SThomas Petazzoni #define MVNETA_RX_CSUM_WITH_PSEUDO_HDR BIT(25) 88c5aff182SThomas Petazzoni #define MVNETA_PORT_CONFIG_DEFL_VALUE(q) (MVNETA_DEF_RXQ(q) | \ 89c5aff182SThomas Petazzoni MVNETA_DEF_RXQ_ARP(q) | \ 90c5aff182SThomas Petazzoni MVNETA_DEF_RXQ_TCP(q) | \ 91c5aff182SThomas Petazzoni MVNETA_DEF_RXQ_UDP(q) | \ 92c5aff182SThomas Petazzoni MVNETA_DEF_RXQ_BPDU(q) | \ 93c5aff182SThomas Petazzoni MVNETA_TX_UNSET_ERR_SUM | \ 94c5aff182SThomas Petazzoni MVNETA_RX_CSUM_WITH_PSEUDO_HDR) 95c5aff182SThomas Petazzoni #define MVNETA_PORT_CONFIG_EXTEND 0x2404 96c5aff182SThomas Petazzoni #define MVNETA_MAC_ADDR_LOW 0x2414 97c5aff182SThomas Petazzoni #define MVNETA_MAC_ADDR_HIGH 0x2418 98c5aff182SThomas Petazzoni #define MVNETA_SDMA_CONFIG 0x241c 99c5aff182SThomas Petazzoni #define MVNETA_SDMA_BRST_SIZE_16 4 100c5aff182SThomas Petazzoni #define MVNETA_RX_BRST_SZ_MASK(burst) ((burst) << 1) 101c5aff182SThomas Petazzoni #define MVNETA_RX_NO_DATA_SWAP BIT(4) 102c5aff182SThomas Petazzoni #define MVNETA_TX_NO_DATA_SWAP BIT(5) 1039ad8fef6SThomas Petazzoni #define MVNETA_DESC_SWAP BIT(6) 104c5aff182SThomas Petazzoni #define MVNETA_TX_BRST_SZ_MASK(burst) ((burst) << 22) 1054906887aSMaxime Chevallier #define MVNETA_VLAN_PRIO_TO_RXQ 0x2440 1064906887aSMaxime Chevallier #define MVNETA_VLAN_PRIO_RXQ_MAP(prio, rxq) ((rxq) << ((prio) * 3)) 107c5aff182SThomas Petazzoni #define MVNETA_PORT_STATUS 0x2444 108359f4cddSMaxim Kiselev #define MVNETA_TX_IN_PRGRS BIT(0) 109c5aff182SThomas Petazzoni #define MVNETA_TX_FIFO_EMPTY BIT(8) 110c5aff182SThomas Petazzoni #define MVNETA_RX_MIN_FRAME_SIZE 0x247c 111b4748553SSascha Hauer /* Only exists on Armada XP and Armada 370 */ 1123f1dd4bcSThomas Petazzoni #define MVNETA_SERDES_CFG 0x24A0 1135445eaf3SArnaud Patard \(Rtp\) #define MVNETA_SGMII_SERDES_PROTO 0x0cc7 1143f1dd4bcSThomas Petazzoni #define MVNETA_QSGMII_SERDES_PROTO 0x0667 1151a642ca7SSascha Hauer #define MVNETA_HSGMII_SERDES_PROTO 0x1107 116c5aff182SThomas Petazzoni #define MVNETA_TYPE_PRIO 0x24bc 117c5aff182SThomas Petazzoni #define MVNETA_FORCE_UNI BIT(21) 118c5aff182SThomas Petazzoni #define MVNETA_TXQ_CMD_1 0x24e4 119c5aff182SThomas Petazzoni #define MVNETA_TXQ_CMD 0x2448 120c5aff182SThomas Petazzoni #define MVNETA_TXQ_DISABLE_SHIFT 8 121c5aff182SThomas Petazzoni #define MVNETA_TXQ_ENABLE_MASK 0x000000ff 122e483911fSAndrew Lunn #define MVNETA_RX_DISCARD_FRAME_COUNT 0x2484 123e483911fSAndrew Lunn #define MVNETA_OVERRUN_FRAME_COUNT 0x2488 124898b2970SStas Sergeev #define MVNETA_GMAC_CLOCK_DIVIDER 0x24f4 125898b2970SStas Sergeev #define MVNETA_GMAC_1MS_CLOCK_ENABLE BIT(31) 126c5aff182SThomas Petazzoni #define MVNETA_ACC_MODE 0x2500 127dc35a10fSMarcin Wojtas #define MVNETA_BM_ADDRESS 0x2504 128c5aff182SThomas Petazzoni #define MVNETA_CPU_MAP(cpu) (0x2540 + ((cpu) << 2)) 129c5aff182SThomas Petazzoni #define MVNETA_CPU_RXQ_ACCESS_ALL_MASK 0x000000ff 130c5aff182SThomas Petazzoni #define MVNETA_CPU_TXQ_ACCESS_ALL_MASK 0x0000ff00 1312dcf75e2SGregory CLEMENT #define MVNETA_CPU_RXQ_ACCESS(rxq) BIT(rxq) 13250bf8cb6SGregory CLEMENT #define MVNETA_CPU_TXQ_ACCESS(txq) BIT(txq + 8) 133c5aff182SThomas Petazzoni #define MVNETA_RXQ_TIME_COAL_REG(q) (0x2580 + ((q) << 2)) 13440ba35e7Swilly tarreau 1352dcf75e2SGregory CLEMENT /* Exception Interrupt Port/Queue Cause register 1362dcf75e2SGregory CLEMENT * 1372dcf75e2SGregory CLEMENT * Their behavior depend of the mapping done using the PCPX2Q 1382dcf75e2SGregory CLEMENT * registers. For a given CPU if the bit associated to a queue is not 1392dcf75e2SGregory CLEMENT * set, then for the register a read from this CPU will always return 1402dcf75e2SGregory CLEMENT * 0 and a write won't do anything 1412dcf75e2SGregory CLEMENT */ 14240ba35e7Swilly tarreau 143c5aff182SThomas Petazzoni #define MVNETA_INTR_NEW_CAUSE 0x25a0 144c5aff182SThomas Petazzoni #define MVNETA_INTR_NEW_MASK 0x25a4 14540ba35e7Swilly tarreau 14640ba35e7Swilly tarreau /* bits 0..7 = TXQ SENT, one bit per queue. 14740ba35e7Swilly tarreau * bits 8..15 = RXQ OCCUP, one bit per queue. 14840ba35e7Swilly tarreau * bits 16..23 = RXQ FREE, one bit per queue. 14940ba35e7Swilly tarreau * bit 29 = OLD_REG_SUM, see old reg ? 15040ba35e7Swilly tarreau * bit 30 = TX_ERR_SUM, one bit for 4 ports 15140ba35e7Swilly tarreau * bit 31 = MISC_SUM, one bit for 4 ports 15240ba35e7Swilly tarreau */ 15340ba35e7Swilly tarreau #define MVNETA_TX_INTR_MASK(nr_txqs) (((1 << nr_txqs) - 1) << 0) 15440ba35e7Swilly tarreau #define MVNETA_TX_INTR_MASK_ALL (0xff << 0) 15540ba35e7Swilly tarreau #define MVNETA_RX_INTR_MASK(nr_rxqs) (((1 << nr_rxqs) - 1) << 8) 15640ba35e7Swilly tarreau #define MVNETA_RX_INTR_MASK_ALL (0xff << 8) 157898b2970SStas Sergeev #define MVNETA_MISCINTR_INTR_MASK BIT(31) 15840ba35e7Swilly tarreau 159c5aff182SThomas Petazzoni #define MVNETA_INTR_OLD_CAUSE 0x25a8 160c5aff182SThomas Petazzoni #define MVNETA_INTR_OLD_MASK 0x25ac 16140ba35e7Swilly tarreau 16240ba35e7Swilly tarreau /* Data Path Port/Queue Cause Register */ 163c5aff182SThomas Petazzoni #define MVNETA_INTR_MISC_CAUSE 0x25b0 164c5aff182SThomas Petazzoni #define MVNETA_INTR_MISC_MASK 0x25b4 16540ba35e7Swilly tarreau 16640ba35e7Swilly tarreau #define MVNETA_CAUSE_PHY_STATUS_CHANGE BIT(0) 16740ba35e7Swilly tarreau #define MVNETA_CAUSE_LINK_CHANGE BIT(1) 16840ba35e7Swilly tarreau #define MVNETA_CAUSE_PTP BIT(4) 16940ba35e7Swilly tarreau 17040ba35e7Swilly tarreau #define MVNETA_CAUSE_INTERNAL_ADDR_ERR BIT(7) 17140ba35e7Swilly tarreau #define MVNETA_CAUSE_RX_OVERRUN BIT(8) 17240ba35e7Swilly tarreau #define MVNETA_CAUSE_RX_CRC_ERROR BIT(9) 17340ba35e7Swilly tarreau #define MVNETA_CAUSE_RX_LARGE_PKT BIT(10) 17440ba35e7Swilly tarreau #define MVNETA_CAUSE_TX_UNDERUN BIT(11) 17540ba35e7Swilly tarreau #define MVNETA_CAUSE_PRBS_ERR BIT(12) 17640ba35e7Swilly tarreau #define MVNETA_CAUSE_PSC_SYNC_CHANGE BIT(13) 17740ba35e7Swilly tarreau #define MVNETA_CAUSE_SERDES_SYNC_ERR BIT(14) 17840ba35e7Swilly tarreau 17940ba35e7Swilly tarreau #define MVNETA_CAUSE_BMU_ALLOC_ERR_SHIFT 16 18040ba35e7Swilly tarreau #define MVNETA_CAUSE_BMU_ALLOC_ERR_ALL_MASK (0xF << MVNETA_CAUSE_BMU_ALLOC_ERR_SHIFT) 18140ba35e7Swilly tarreau #define MVNETA_CAUSE_BMU_ALLOC_ERR_MASK(pool) (1 << (MVNETA_CAUSE_BMU_ALLOC_ERR_SHIFT + (pool))) 18240ba35e7Swilly tarreau 18340ba35e7Swilly tarreau #define MVNETA_CAUSE_TXQ_ERROR_SHIFT 24 18440ba35e7Swilly tarreau #define MVNETA_CAUSE_TXQ_ERROR_ALL_MASK (0xFF << MVNETA_CAUSE_TXQ_ERROR_SHIFT) 18540ba35e7Swilly tarreau #define MVNETA_CAUSE_TXQ_ERROR_MASK(q) (1 << (MVNETA_CAUSE_TXQ_ERROR_SHIFT + (q))) 18640ba35e7Swilly tarreau 187c5aff182SThomas Petazzoni #define MVNETA_INTR_ENABLE 0x25b8 188c5aff182SThomas Petazzoni #define MVNETA_TXQ_INTR_ENABLE_ALL_MASK 0x0000ff00 189dc1aadf6SMarcin Wojtas #define MVNETA_RXQ_INTR_ENABLE_ALL_MASK 0x000000ff 19040ba35e7Swilly tarreau 191c5aff182SThomas Petazzoni #define MVNETA_RXQ_CMD 0x2680 192c5aff182SThomas Petazzoni #define MVNETA_RXQ_DISABLE_SHIFT 8 193c5aff182SThomas Petazzoni #define MVNETA_RXQ_ENABLE_MASK 0x000000ff 194c5aff182SThomas Petazzoni #define MVETH_TXQ_TOKEN_COUNT_REG(q) (0x2700 + ((q) << 4)) 195c5aff182SThomas Petazzoni #define MVETH_TXQ_TOKEN_CFG_REG(q) (0x2704 + ((q) << 4)) 196c5aff182SThomas Petazzoni #define MVNETA_GMAC_CTRL_0 0x2c00 197c5aff182SThomas Petazzoni #define MVNETA_GMAC_MAX_RX_SIZE_SHIFT 2 198c5aff182SThomas Petazzoni #define MVNETA_GMAC_MAX_RX_SIZE_MASK 0x7ffc 19922f4bf8aSRussell King #define MVNETA_GMAC0_PORT_1000BASE_X BIT(1) 200c5aff182SThomas Petazzoni #define MVNETA_GMAC0_PORT_ENABLE BIT(0) 201c5aff182SThomas Petazzoni #define MVNETA_GMAC_CTRL_2 0x2c08 202898b2970SStas Sergeev #define MVNETA_GMAC2_INBAND_AN_ENABLE BIT(0) 203a79121d3SThomas Petazzoni #define MVNETA_GMAC2_PCS_ENABLE BIT(3) 204c5aff182SThomas Petazzoni #define MVNETA_GMAC2_PORT_RGMII BIT(4) 205c5aff182SThomas Petazzoni #define MVNETA_GMAC2_PORT_RESET BIT(6) 206c5aff182SThomas Petazzoni #define MVNETA_GMAC_STATUS 0x2c10 207c5aff182SThomas Petazzoni #define MVNETA_GMAC_LINK_UP BIT(0) 208c5aff182SThomas Petazzoni #define MVNETA_GMAC_SPEED_1000 BIT(1) 209c5aff182SThomas Petazzoni #define MVNETA_GMAC_SPEED_100 BIT(2) 210c5aff182SThomas Petazzoni #define MVNETA_GMAC_FULL_DUPLEX BIT(3) 211c5aff182SThomas Petazzoni #define MVNETA_GMAC_RX_FLOW_CTRL_ENABLE BIT(4) 212c5aff182SThomas Petazzoni #define MVNETA_GMAC_TX_FLOW_CTRL_ENABLE BIT(5) 213c5aff182SThomas Petazzoni #define MVNETA_GMAC_RX_FLOW_CTRL_ACTIVE BIT(6) 214c5aff182SThomas Petazzoni #define MVNETA_GMAC_TX_FLOW_CTRL_ACTIVE BIT(7) 215503f9aa9SRussell King #define MVNETA_GMAC_AN_COMPLETE BIT(11) 216503f9aa9SRussell King #define MVNETA_GMAC_SYNC_OK BIT(14) 217c5aff182SThomas Petazzoni #define MVNETA_GMAC_AUTONEG_CONFIG 0x2c0c 218c5aff182SThomas Petazzoni #define MVNETA_GMAC_FORCE_LINK_DOWN BIT(0) 219c5aff182SThomas Petazzoni #define MVNETA_GMAC_FORCE_LINK_PASS BIT(1) 220898b2970SStas Sergeev #define MVNETA_GMAC_INBAND_AN_ENABLE BIT(2) 22122f4bf8aSRussell King #define MVNETA_GMAC_AN_BYPASS_ENABLE BIT(3) 22222f4bf8aSRussell King #define MVNETA_GMAC_INBAND_RESTART_AN BIT(4) 223c5aff182SThomas Petazzoni #define MVNETA_GMAC_CONFIG_MII_SPEED BIT(5) 224c5aff182SThomas Petazzoni #define MVNETA_GMAC_CONFIG_GMII_SPEED BIT(6) 22571408602SThomas Petazzoni #define MVNETA_GMAC_AN_SPEED_EN BIT(7) 22622f4bf8aSRussell King #define MVNETA_GMAC_CONFIG_FLOW_CTRL BIT(8) 22722f4bf8aSRussell King #define MVNETA_GMAC_ADVERT_SYM_FLOW_CTRL BIT(9) 228898b2970SStas Sergeev #define MVNETA_GMAC_AN_FLOW_CTRL_EN BIT(11) 229c5aff182SThomas Petazzoni #define MVNETA_GMAC_CONFIG_FULL_DUPLEX BIT(12) 23071408602SThomas Petazzoni #define MVNETA_GMAC_AN_DUPLEX_EN BIT(13) 231da58a931SMaxime Chevallier #define MVNETA_GMAC_CTRL_4 0x2c90 232da58a931SMaxime Chevallier #define MVNETA_GMAC4_SHORT_PREAMBLE_ENABLE BIT(1) 233e483911fSAndrew Lunn #define MVNETA_MIB_COUNTERS_BASE 0x3000 234c5aff182SThomas Petazzoni #define MVNETA_MIB_LATE_COLLISION 0x7c 235c5aff182SThomas Petazzoni #define MVNETA_DA_FILT_SPEC_MCAST 0x3400 236c5aff182SThomas Petazzoni #define MVNETA_DA_FILT_OTH_MCAST 0x3500 237c5aff182SThomas Petazzoni #define MVNETA_DA_FILT_UCAST_BASE 0x3600 238c5aff182SThomas Petazzoni #define MVNETA_TXQ_BASE_ADDR_REG(q) (0x3c00 + ((q) << 2)) 239c5aff182SThomas Petazzoni #define MVNETA_TXQ_SIZE_REG(q) (0x3c20 + ((q) << 2)) 240c5aff182SThomas Petazzoni #define MVNETA_TXQ_SENT_THRESH_ALL_MASK 0x3fff0000 241c5aff182SThomas Petazzoni #define MVNETA_TXQ_SENT_THRESH_MASK(coal) ((coal) << 16) 242c5aff182SThomas Petazzoni #define MVNETA_TXQ_UPDATE_REG(q) (0x3c60 + ((q) << 2)) 243c5aff182SThomas Petazzoni #define MVNETA_TXQ_DEC_SENT_SHIFT 16 2442a90f7e1SSimon Guinot #define MVNETA_TXQ_DEC_SENT_MASK 0xff 245c5aff182SThomas Petazzoni #define MVNETA_TXQ_STATUS_REG(q) (0x3c40 + ((q) << 2)) 246c5aff182SThomas Petazzoni #define MVNETA_TXQ_SENT_DESC_SHIFT 16 247c5aff182SThomas Petazzoni #define MVNETA_TXQ_SENT_DESC_MASK 0x3fff0000 248c5aff182SThomas Petazzoni #define MVNETA_PORT_TX_RESET 0x3cf0 249c5aff182SThomas Petazzoni #define MVNETA_PORT_TX_DMA_RESET BIT(0) 250c5aff182SThomas Petazzoni #define MVNETA_TX_MTU 0x3e0c 251c5aff182SThomas Petazzoni #define MVNETA_TX_TOKEN_SIZE 0x3e14 252c5aff182SThomas Petazzoni #define MVNETA_TX_TOKEN_SIZE_MAX 0xffffffff 253c5aff182SThomas Petazzoni #define MVNETA_TXQ_TOKEN_SIZE_REG(q) (0x3e40 + ((q) << 2)) 254c5aff182SThomas Petazzoni #define MVNETA_TXQ_TOKEN_SIZE_MAX 0x7fffffff 255c5aff182SThomas Petazzoni 2566d81f451SRussell King #define MVNETA_LPI_CTRL_0 0x2cc0 2576d81f451SRussell King #define MVNETA_LPI_CTRL_1 0x2cc4 2586d81f451SRussell King #define MVNETA_LPI_REQUEST_ENABLE BIT(0) 2596d81f451SRussell King #define MVNETA_LPI_CTRL_2 0x2cc8 2606d81f451SRussell King #define MVNETA_LPI_STATUS 0x2ccc 2616d81f451SRussell King 262c5aff182SThomas Petazzoni #define MVNETA_CAUSE_TXQ_SENT_DESC_ALL_MASK 0xff 263c5aff182SThomas Petazzoni 264c5aff182SThomas Petazzoni /* Descriptor ring Macros */ 265c5aff182SThomas Petazzoni #define MVNETA_QUEUE_NEXT_DESC(q, index) \ 266c5aff182SThomas Petazzoni (((index) < (q)->last_desc) ? ((index) + 1) : 0) 267c5aff182SThomas Petazzoni 268c5aff182SThomas Petazzoni /* Various constants */ 269c5aff182SThomas Petazzoni 270c5aff182SThomas Petazzoni /* Coalescing */ 27106708f81SDmitri Epshtein #define MVNETA_TXDONE_COAL_PKTS 0 /* interrupt per packet */ 272c5aff182SThomas Petazzoni #define MVNETA_RX_COAL_PKTS 32 273c5aff182SThomas Petazzoni #define MVNETA_RX_COAL_USEC 100 274c5aff182SThomas Petazzoni 2756a20c175SThomas Petazzoni /* The two bytes Marvell header. Either contains a special value used 276c5aff182SThomas Petazzoni * by Marvell switches when a specific hardware mode is enabled (not 277c5aff182SThomas Petazzoni * supported by this driver) or is filled automatically by zeroes on 278c5aff182SThomas Petazzoni * the RX side. Those two bytes being at the front of the Ethernet 279c5aff182SThomas Petazzoni * header, they allow to have the IP header aligned on a 4 bytes 280c5aff182SThomas Petazzoni * boundary automatically: the hardware skips those two bytes on its 281c5aff182SThomas Petazzoni * own. 282c5aff182SThomas Petazzoni */ 283c5aff182SThomas Petazzoni #define MVNETA_MH_SIZE 2 284c5aff182SThomas Petazzoni 285c5aff182SThomas Petazzoni #define MVNETA_VLAN_TAG_LEN 4 286c5aff182SThomas Petazzoni 2879110ee07SMarcin Wojtas #define MVNETA_TX_CSUM_DEF_SIZE 1600 288c5aff182SThomas Petazzoni #define MVNETA_TX_CSUM_MAX_SIZE 9800 289dc35a10fSMarcin Wojtas #define MVNETA_ACC_MODE_EXT1 1 290dc35a10fSMarcin Wojtas #define MVNETA_ACC_MODE_EXT2 2 291dc35a10fSMarcin Wojtas 292dc35a10fSMarcin Wojtas #define MVNETA_MAX_DECODE_WIN 6 293c5aff182SThomas Petazzoni 294c5aff182SThomas Petazzoni /* Timeout constants */ 295c5aff182SThomas Petazzoni #define MVNETA_TX_DISABLE_TIMEOUT_MSEC 1000 296c5aff182SThomas Petazzoni #define MVNETA_RX_DISABLE_TIMEOUT_MSEC 1000 297c5aff182SThomas Petazzoni #define MVNETA_TX_FIFO_EMPTY_TIMEOUT 10000 298c5aff182SThomas Petazzoni 299c5aff182SThomas Petazzoni #define MVNETA_TX_MTU_MAX 0x3ffff 300c5aff182SThomas Petazzoni 3019a401deaSGregory CLEMENT /* The RSS lookup table actually has 256 entries but we do not use 3029a401deaSGregory CLEMENT * them yet 3039a401deaSGregory CLEMENT */ 3049a401deaSGregory CLEMENT #define MVNETA_RSS_LU_TABLE_SIZE 1 3059a401deaSGregory CLEMENT 306c5aff182SThomas Petazzoni /* Max number of Rx descriptors */ 307c307e2a8SYelena Krivosheev #define MVNETA_MAX_RXD 512 308c5aff182SThomas Petazzoni 309c5aff182SThomas Petazzoni /* Max number of Tx descriptors */ 310c307e2a8SYelena Krivosheev #define MVNETA_MAX_TXD 1024 311c5aff182SThomas Petazzoni 3128eef5f97SEzequiel Garcia /* Max number of allowed TCP segments for software TSO */ 3138eef5f97SEzequiel Garcia #define MVNETA_MAX_TSO_SEGS 100 3148eef5f97SEzequiel Garcia 3158eef5f97SEzequiel Garcia #define MVNETA_MAX_SKB_DESCS (MVNETA_MAX_TSO_SEGS * 2 + MAX_SKB_FRAGS) 3168eef5f97SEzequiel Garcia 317c5aff182SThomas Petazzoni /* descriptor aligned size */ 318c5aff182SThomas Petazzoni #define MVNETA_DESC_ALIGNED_SIZE 32 319c5aff182SThomas Petazzoni 3208d5047cfSMarcin Wojtas /* Number of bytes to be taken into account by HW when putting incoming data 3218d5047cfSMarcin Wojtas * to the buffers. It is needed in case NET_SKB_PAD exceeds maximum packet 3228d5047cfSMarcin Wojtas * offset supported in MVNETA_RXQ_CONFIG_REG(q) registers. 3238d5047cfSMarcin Wojtas */ 3248d5047cfSMarcin Wojtas #define MVNETA_RX_PKT_OFFSET_CORRECTION 64 3258d5047cfSMarcin Wojtas 326c5aff182SThomas Petazzoni #define MVNETA_RX_PKT_SIZE(mtu) \ 327c5aff182SThomas Petazzoni ALIGN((mtu) + MVNETA_MH_SIZE + MVNETA_VLAN_TAG_LEN + \ 328c5aff182SThomas Petazzoni ETH_HLEN + ETH_FCS_LEN, \ 329c66e98c9SJisheng Zhang cache_line_size()) 330c5aff182SThomas Petazzoni 331ca23cb0bSSven Auhagen /* Driver assumes that the last 3 bits are 0 */ 332e2243720SAlexander Lobakin #define MVNETA_SKB_HEADROOM ALIGN(max(NET_SKB_PAD, XDP_PACKET_HEADROOM), 8) 3338dc9a088SLorenzo Bianconi #define MVNETA_SKB_PAD (SKB_DATA_ALIGN(sizeof(struct skb_shared_info) + \ 3340db51da7SLorenzo Bianconi MVNETA_SKB_HEADROOM)) 3358dc9a088SLorenzo Bianconi #define MVNETA_MAX_RX_BUF_SIZE (PAGE_SIZE - MVNETA_SKB_PAD) 3368dc9a088SLorenzo Bianconi 3372e3173a3SEzequiel Garcia #define IS_TSO_HEADER(txq, addr) \ 3382e3173a3SEzequiel Garcia ((addr >= txq->tso_hdrs_phys) && \ 3392e3173a3SEzequiel Garcia (addr < txq->tso_hdrs_phys + txq->size * TSO_HEADER_SIZE)) 3402e3173a3SEzequiel Garcia 341dc35a10fSMarcin Wojtas #define MVNETA_RX_GET_BM_POOL_ID(rxd) \ 342dc35a10fSMarcin Wojtas (((rxd)->status & MVNETA_RXD_BM_POOL_MASK) >> MVNETA_RXD_BM_POOL_SHIFT) 343c5aff182SThomas Petazzoni 3446d81f451SRussell King enum { 3456d81f451SRussell King ETHTOOL_STAT_EEE_WAKEUP, 34617a96da6SGregory CLEMENT ETHTOOL_STAT_SKB_ALLOC_ERR, 34717a96da6SGregory CLEMENT ETHTOOL_STAT_REFILL_ERR, 3483d866523SLorenzo Bianconi ETHTOOL_XDP_REDIRECT, 3493d866523SLorenzo Bianconi ETHTOOL_XDP_PASS, 3503d866523SLorenzo Bianconi ETHTOOL_XDP_DROP, 3513d866523SLorenzo Bianconi ETHTOOL_XDP_TX, 35215070919SJesper Dangaard Brouer ETHTOOL_XDP_TX_ERR, 35315070919SJesper Dangaard Brouer ETHTOOL_XDP_XMIT, 35415070919SJesper Dangaard Brouer ETHTOOL_XDP_XMIT_ERR, 3556d81f451SRussell King ETHTOOL_MAX_STATS, 3566d81f451SRussell King }; 3576d81f451SRussell King 3589b0cdefaSRussell King struct mvneta_statistic { 3599b0cdefaSRussell King unsigned short offset; 3609b0cdefaSRussell King unsigned short type; 3619b0cdefaSRussell King const char name[ETH_GSTRING_LEN]; 3629b0cdefaSRussell King }; 3639b0cdefaSRussell King 3649b0cdefaSRussell King #define T_REG_32 32 3659b0cdefaSRussell King #define T_REG_64 64 3666d81f451SRussell King #define T_SW 1 3679b0cdefaSRussell King 3686c8a8cfdSLorenzo Bianconi #define MVNETA_XDP_PASS 0 3696c8a8cfdSLorenzo Bianconi #define MVNETA_XDP_DROPPED BIT(0) 3706c8a8cfdSLorenzo Bianconi #define MVNETA_XDP_TX BIT(1) 3716c8a8cfdSLorenzo Bianconi #define MVNETA_XDP_REDIR BIT(2) 3720db51da7SLorenzo Bianconi 3739b0cdefaSRussell King static const struct mvneta_statistic mvneta_statistics[] = { 3749b0cdefaSRussell King { 0x3000, T_REG_64, "good_octets_received", }, 3759b0cdefaSRussell King { 0x3010, T_REG_32, "good_frames_received", }, 3769b0cdefaSRussell King { 0x3008, T_REG_32, "bad_octets_received", }, 3779b0cdefaSRussell King { 0x3014, T_REG_32, "bad_frames_received", }, 3789b0cdefaSRussell King { 0x3018, T_REG_32, "broadcast_frames_received", }, 3799b0cdefaSRussell King { 0x301c, T_REG_32, "multicast_frames_received", }, 3809b0cdefaSRussell King { 0x3050, T_REG_32, "unrec_mac_control_received", }, 3819b0cdefaSRussell King { 0x3058, T_REG_32, "good_fc_received", }, 3829b0cdefaSRussell King { 0x305c, T_REG_32, "bad_fc_received", }, 3839b0cdefaSRussell King { 0x3060, T_REG_32, "undersize_received", }, 3849b0cdefaSRussell King { 0x3064, T_REG_32, "fragments_received", }, 3859b0cdefaSRussell King { 0x3068, T_REG_32, "oversize_received", }, 3869b0cdefaSRussell King { 0x306c, T_REG_32, "jabber_received", }, 3879b0cdefaSRussell King { 0x3070, T_REG_32, "mac_receive_error", }, 3889b0cdefaSRussell King { 0x3074, T_REG_32, "bad_crc_event", }, 3899b0cdefaSRussell King { 0x3078, T_REG_32, "collision", }, 3909b0cdefaSRussell King { 0x307c, T_REG_32, "late_collision", }, 3919b0cdefaSRussell King { 0x2484, T_REG_32, "rx_discard", }, 3929b0cdefaSRussell King { 0x2488, T_REG_32, "rx_overrun", }, 3939b0cdefaSRussell King { 0x3020, T_REG_32, "frames_64_octets", }, 3949b0cdefaSRussell King { 0x3024, T_REG_32, "frames_65_to_127_octets", }, 3959b0cdefaSRussell King { 0x3028, T_REG_32, "frames_128_to_255_octets", }, 3969b0cdefaSRussell King { 0x302c, T_REG_32, "frames_256_to_511_octets", }, 3979b0cdefaSRussell King { 0x3030, T_REG_32, "frames_512_to_1023_octets", }, 3989b0cdefaSRussell King { 0x3034, T_REG_32, "frames_1024_to_max_octets", }, 3999b0cdefaSRussell King { 0x3038, T_REG_64, "good_octets_sent", }, 4009b0cdefaSRussell King { 0x3040, T_REG_32, "good_frames_sent", }, 4019b0cdefaSRussell King { 0x3044, T_REG_32, "excessive_collision", }, 4029b0cdefaSRussell King { 0x3048, T_REG_32, "multicast_frames_sent", }, 4039b0cdefaSRussell King { 0x304c, T_REG_32, "broadcast_frames_sent", }, 4049b0cdefaSRussell King { 0x3054, T_REG_32, "fc_sent", }, 4059b0cdefaSRussell King { 0x300c, T_REG_32, "internal_mac_transmit_err", }, 4066d81f451SRussell King { ETHTOOL_STAT_EEE_WAKEUP, T_SW, "eee_wakeup_errors", }, 40717a96da6SGregory CLEMENT { ETHTOOL_STAT_SKB_ALLOC_ERR, T_SW, "skb_alloc_errors", }, 40817a96da6SGregory CLEMENT { ETHTOOL_STAT_REFILL_ERR, T_SW, "refill_errors", }, 4097d51a015SLorenzo Bianconi { ETHTOOL_XDP_REDIRECT, T_SW, "rx_xdp_redirect", }, 4107d51a015SLorenzo Bianconi { ETHTOOL_XDP_PASS, T_SW, "rx_xdp_pass", }, 4117d51a015SLorenzo Bianconi { ETHTOOL_XDP_DROP, T_SW, "rx_xdp_drop", }, 4127d51a015SLorenzo Bianconi { ETHTOOL_XDP_TX, T_SW, "rx_xdp_tx", }, 41315070919SJesper Dangaard Brouer { ETHTOOL_XDP_TX_ERR, T_SW, "rx_xdp_tx_errors", }, 4147d51a015SLorenzo Bianconi { ETHTOOL_XDP_XMIT, T_SW, "tx_xdp_xmit", }, 41515070919SJesper Dangaard Brouer { ETHTOOL_XDP_XMIT_ERR, T_SW, "tx_xdp_xmit_errors", }, 4169b0cdefaSRussell King }; 4179b0cdefaSRussell King 418320d5441SLorenzo Bianconi struct mvneta_stats { 419320d5441SLorenzo Bianconi u64 rx_packets; 420320d5441SLorenzo Bianconi u64 rx_bytes; 421320d5441SLorenzo Bianconi u64 tx_packets; 422320d5441SLorenzo Bianconi u64 tx_bytes; 4233d866523SLorenzo Bianconi /* xdp */ 4243d866523SLorenzo Bianconi u64 xdp_redirect; 4253d866523SLorenzo Bianconi u64 xdp_pass; 4263d866523SLorenzo Bianconi u64 xdp_drop; 4277d51a015SLorenzo Bianconi u64 xdp_xmit; 42815070919SJesper Dangaard Brouer u64 xdp_xmit_err; 4293d866523SLorenzo Bianconi u64 xdp_tx; 43015070919SJesper Dangaard Brouer u64 xdp_tx_err; 431320d5441SLorenzo Bianconi }; 432320d5441SLorenzo Bianconi 4339ac41f3cSLorenzo Bianconi struct mvneta_ethtool_stats { 434320d5441SLorenzo Bianconi struct mvneta_stats ps; 4359ac41f3cSLorenzo Bianconi u64 skb_alloc_error; 4369ac41f3cSLorenzo Bianconi u64 refill_error; 4379ac41f3cSLorenzo Bianconi }; 4389ac41f3cSLorenzo Bianconi 43974c41b04Swilly tarreau struct mvneta_pcpu_stats { 440c5aff182SThomas Petazzoni struct u64_stats_sync syncp; 4419ac41f3cSLorenzo Bianconi 4429ac41f3cSLorenzo Bianconi struct mvneta_ethtool_stats es; 443c35947b8SLorenzo Bianconi u64 rx_dropped; 444c35947b8SLorenzo Bianconi u64 rx_errors; 445c5aff182SThomas Petazzoni }; 446c5aff182SThomas Petazzoni 44712bb03b4SMaxime Ripard struct mvneta_pcpu_port { 44812bb03b4SMaxime Ripard /* Pointer to the shared port */ 44912bb03b4SMaxime Ripard struct mvneta_port *pp; 45012bb03b4SMaxime Ripard 45112bb03b4SMaxime Ripard /* Pointer to the CPU-local NAPI struct */ 45212bb03b4SMaxime Ripard struct napi_struct napi; 45312bb03b4SMaxime Ripard 45412bb03b4SMaxime Ripard /* Cause of the previous interrupt */ 45512bb03b4SMaxime Ripard u32 cause_rx_tx; 45612bb03b4SMaxime Ripard }; 45712bb03b4SMaxime Ripard 45862a502ccSLorenzo Bianconi enum { 45962a502ccSLorenzo Bianconi __MVNETA_DOWN, 46062a502ccSLorenzo Bianconi }; 46162a502ccSLorenzo Bianconi 462c5aff182SThomas Petazzoni struct mvneta_port { 463dc35a10fSMarcin Wojtas u8 id; 46412bb03b4SMaxime Ripard struct mvneta_pcpu_port __percpu *ports; 46512bb03b4SMaxime Ripard struct mvneta_pcpu_stats __percpu *stats; 46612bb03b4SMaxime Ripard 46762a502ccSLorenzo Bianconi unsigned long state; 46862a502ccSLorenzo Bianconi 469c5aff182SThomas Petazzoni int pkt_size; 470c5aff182SThomas Petazzoni void __iomem *base; 471c5aff182SThomas Petazzoni struct mvneta_rx_queue *rxqs; 472c5aff182SThomas Petazzoni struct mvneta_tx_queue *txqs; 473c5aff182SThomas Petazzoni struct net_device *dev; 47484a3f4dbSSebastian Andrzej Siewior struct hlist_node node_online; 47584a3f4dbSSebastian Andrzej Siewior struct hlist_node node_dead; 47690b74c01SGregory CLEMENT int rxq_def; 4775888511eSGregory CLEMENT /* Protect the access to the percpu interrupt registers, 4785888511eSGregory CLEMENT * ensuring that the configuration remains coherent. 4795888511eSGregory CLEMENT */ 4805888511eSGregory CLEMENT spinlock_t lock; 481120cfa50SGregory CLEMENT bool is_stopped; 482c5aff182SThomas Petazzoni 4832636ac3cSMarcin Wojtas u32 cause_rx_tx; 4842636ac3cSMarcin Wojtas struct napi_struct napi; 4852636ac3cSMarcin Wojtas 4860db51da7SLorenzo Bianconi struct bpf_prog *xdp_prog; 4870db51da7SLorenzo Bianconi 488c5aff182SThomas Petazzoni /* Core clock */ 489189dd626SThomas Petazzoni struct clk *clk; 49015cc4a4aSJisheng Zhang /* AXI clock */ 49115cc4a4aSJisheng Zhang struct clk *clk_bus; 492c5aff182SThomas Petazzoni u8 mcast_count[256]; 493c5aff182SThomas Petazzoni u16 tx_ring_size; 494c5aff182SThomas Petazzoni u16 rx_ring_size; 4954906887aSMaxime Chevallier u8 prio_tc_map[8]; 496c5aff182SThomas Petazzoni 497c5aff182SThomas Petazzoni phy_interface_t phy_interface; 498503f9aa9SRussell King struct device_node *dn; 499b65657fcSSimon Guinot unsigned int tx_csum_limit; 500503f9aa9SRussell King struct phylink *phylink; 50144cc27e4SIoana Ciornei struct phylink_config phylink_config; 502a10c1c81SRussell King struct phy *comphy; 5039b0cdefaSRussell King 504dc35a10fSMarcin Wojtas struct mvneta_bm *bm_priv; 505dc35a10fSMarcin Wojtas struct mvneta_bm_pool *pool_long; 506dc35a10fSMarcin Wojtas struct mvneta_bm_pool *pool_short; 507dc35a10fSMarcin Wojtas int bm_win_id; 508dc35a10fSMarcin Wojtas 5096d81f451SRussell King bool eee_enabled; 5106d81f451SRussell King bool eee_active; 5116d81f451SRussell King bool tx_lpi_enabled; 5126d81f451SRussell King 5139b0cdefaSRussell King u64 ethtool_stats[ARRAY_SIZE(mvneta_statistics)]; 5149a401deaSGregory CLEMENT 5159a401deaSGregory CLEMENT u32 indir[MVNETA_RSS_LU_TABLE_SIZE]; 5162636ac3cSMarcin Wojtas 5172636ac3cSMarcin Wojtas /* Flags for special SoC configurations */ 5182636ac3cSMarcin Wojtas bool neta_armada3700; 5198d5047cfSMarcin Wojtas u16 rx_offset_correction; 5209768b45cSJane Li const struct mbus_dram_target_info *dram_target_info; 521c5aff182SThomas Petazzoni }; 522c5aff182SThomas Petazzoni 5236a20c175SThomas Petazzoni /* The mvneta_tx_desc and mvneta_rx_desc structures describe the 524c5aff182SThomas Petazzoni * layout of the transmit and reception DMA descriptors, and their 525c5aff182SThomas Petazzoni * layout is therefore defined by the hardware design 526c5aff182SThomas Petazzoni */ 5276083ed44SThomas Petazzoni 528c5aff182SThomas Petazzoni #define MVNETA_TX_L3_OFF_SHIFT 0 529c5aff182SThomas Petazzoni #define MVNETA_TX_IP_HLEN_SHIFT 8 530c5aff182SThomas Petazzoni #define MVNETA_TX_L4_UDP BIT(16) 531c5aff182SThomas Petazzoni #define MVNETA_TX_L3_IP6 BIT(17) 532c5aff182SThomas Petazzoni #define MVNETA_TXD_IP_CSUM BIT(18) 533c5aff182SThomas Petazzoni #define MVNETA_TXD_Z_PAD BIT(19) 534c5aff182SThomas Petazzoni #define MVNETA_TXD_L_DESC BIT(20) 535c5aff182SThomas Petazzoni #define MVNETA_TXD_F_DESC BIT(21) 536c5aff182SThomas Petazzoni #define MVNETA_TXD_FLZ_DESC (MVNETA_TXD_Z_PAD | \ 537c5aff182SThomas Petazzoni MVNETA_TXD_L_DESC | \ 538c5aff182SThomas Petazzoni MVNETA_TXD_F_DESC) 539c5aff182SThomas Petazzoni #define MVNETA_TX_L4_CSUM_FULL BIT(30) 540c5aff182SThomas Petazzoni #define MVNETA_TX_L4_CSUM_NOT BIT(31) 541c5aff182SThomas Petazzoni 542c5aff182SThomas Petazzoni #define MVNETA_RXD_ERR_CRC 0x0 543dc35a10fSMarcin Wojtas #define MVNETA_RXD_BM_POOL_SHIFT 13 544dc35a10fSMarcin Wojtas #define MVNETA_RXD_BM_POOL_MASK (BIT(13) | BIT(14)) 545c5aff182SThomas Petazzoni #define MVNETA_RXD_ERR_SUMMARY BIT(16) 546c5aff182SThomas Petazzoni #define MVNETA_RXD_ERR_OVERRUN BIT(17) 547c5aff182SThomas Petazzoni #define MVNETA_RXD_ERR_LEN BIT(18) 548c5aff182SThomas Petazzoni #define MVNETA_RXD_ERR_RESOURCE (BIT(17) | BIT(18)) 549c5aff182SThomas Petazzoni #define MVNETA_RXD_ERR_CODE_MASK (BIT(17) | BIT(18)) 550c5aff182SThomas Petazzoni #define MVNETA_RXD_L3_IP4 BIT(25) 551562e2f46SYelena Krivosheev #define MVNETA_RXD_LAST_DESC BIT(26) 552562e2f46SYelena Krivosheev #define MVNETA_RXD_FIRST_DESC BIT(27) 553562e2f46SYelena Krivosheev #define MVNETA_RXD_FIRST_LAST_DESC (MVNETA_RXD_FIRST_DESC | \ 554562e2f46SYelena Krivosheev MVNETA_RXD_LAST_DESC) 555c5aff182SThomas Petazzoni #define MVNETA_RXD_L4_CSUM_OK BIT(30) 556c5aff182SThomas Petazzoni 5579ad8fef6SThomas Petazzoni #if defined(__LITTLE_ENDIAN) 5586083ed44SThomas Petazzoni struct mvneta_tx_desc { 5596083ed44SThomas Petazzoni u32 command; /* Options used by HW for packet transmitting.*/ 560fbd1d524SAlexandre Belloni u16 reserved1; /* csum_l4 (for future use) */ 5616083ed44SThomas Petazzoni u16 data_size; /* Data size of transmitted packet in bytes */ 5626083ed44SThomas Petazzoni u32 buf_phys_addr; /* Physical addr of transmitted buffer */ 5636083ed44SThomas Petazzoni u32 reserved2; /* hw_cmd - (for future use, PMT) */ 5646083ed44SThomas Petazzoni u32 reserved3[4]; /* Reserved - (for future use) */ 5656083ed44SThomas Petazzoni }; 5666083ed44SThomas Petazzoni 5676083ed44SThomas Petazzoni struct mvneta_rx_desc { 5686083ed44SThomas Petazzoni u32 status; /* Info about received packet */ 569c5aff182SThomas Petazzoni u16 reserved1; /* pnc_info - (for future use, PnC) */ 570c5aff182SThomas Petazzoni u16 data_size; /* Size of received packet in bytes */ 5716083ed44SThomas Petazzoni 572c5aff182SThomas Petazzoni u32 buf_phys_addr; /* Physical address of the buffer */ 573c5aff182SThomas Petazzoni u32 reserved2; /* pnc_flow_id (for future use, PnC) */ 5746083ed44SThomas Petazzoni 575c5aff182SThomas Petazzoni u32 buf_cookie; /* cookie for access to RX buffer in rx path */ 576c5aff182SThomas Petazzoni u16 reserved3; /* prefetch_cmd, for future use */ 577c5aff182SThomas Petazzoni u16 reserved4; /* csum_l4 - (for future use, PnC) */ 5786083ed44SThomas Petazzoni 579c5aff182SThomas Petazzoni u32 reserved5; /* pnc_extra PnC (for future use, PnC) */ 580c5aff182SThomas Petazzoni u32 reserved6; /* hw_cmd (for future use, PnC and HWF) */ 581c5aff182SThomas Petazzoni }; 5829ad8fef6SThomas Petazzoni #else 5839ad8fef6SThomas Petazzoni struct mvneta_tx_desc { 5849ad8fef6SThomas Petazzoni u16 data_size; /* Data size of transmitted packet in bytes */ 585fbd1d524SAlexandre Belloni u16 reserved1; /* csum_l4 (for future use) */ 5869ad8fef6SThomas Petazzoni u32 command; /* Options used by HW for packet transmitting.*/ 5879ad8fef6SThomas Petazzoni u32 reserved2; /* hw_cmd - (for future use, PMT) */ 5889ad8fef6SThomas Petazzoni u32 buf_phys_addr; /* Physical addr of transmitted buffer */ 5899ad8fef6SThomas Petazzoni u32 reserved3[4]; /* Reserved - (for future use) */ 5909ad8fef6SThomas Petazzoni }; 5919ad8fef6SThomas Petazzoni 5929ad8fef6SThomas Petazzoni struct mvneta_rx_desc { 5939ad8fef6SThomas Petazzoni u16 data_size; /* Size of received packet in bytes */ 5949ad8fef6SThomas Petazzoni u16 reserved1; /* pnc_info - (for future use, PnC) */ 5959ad8fef6SThomas Petazzoni u32 status; /* Info about received packet */ 5969ad8fef6SThomas Petazzoni 5979ad8fef6SThomas Petazzoni u32 reserved2; /* pnc_flow_id (for future use, PnC) */ 5989ad8fef6SThomas Petazzoni u32 buf_phys_addr; /* Physical address of the buffer */ 5999ad8fef6SThomas Petazzoni 6009ad8fef6SThomas Petazzoni u16 reserved4; /* csum_l4 - (for future use, PnC) */ 6019ad8fef6SThomas Petazzoni u16 reserved3; /* prefetch_cmd, for future use */ 6029ad8fef6SThomas Petazzoni u32 buf_cookie; /* cookie for access to RX buffer in rx path */ 6039ad8fef6SThomas Petazzoni 6049ad8fef6SThomas Petazzoni u32 reserved5; /* pnc_extra PnC (for future use, PnC) */ 6059ad8fef6SThomas Petazzoni u32 reserved6; /* hw_cmd (for future use, PnC and HWF) */ 6069ad8fef6SThomas Petazzoni }; 6079ad8fef6SThomas Petazzoni #endif 608c5aff182SThomas Petazzoni 6099e58c8b4SLorenzo Bianconi enum mvneta_tx_buf_type { 6109e58c8b4SLorenzo Bianconi MVNETA_TYPE_SKB, 6119e58c8b4SLorenzo Bianconi MVNETA_TYPE_XDP_TX, 6129e58c8b4SLorenzo Bianconi MVNETA_TYPE_XDP_NDO, 6139e58c8b4SLorenzo Bianconi }; 6149e58c8b4SLorenzo Bianconi 6159e58c8b4SLorenzo Bianconi struct mvneta_tx_buf { 6169e58c8b4SLorenzo Bianconi enum mvneta_tx_buf_type type; 6179e58c8b4SLorenzo Bianconi union { 6189e58c8b4SLorenzo Bianconi struct xdp_frame *xdpf; 6199e58c8b4SLorenzo Bianconi struct sk_buff *skb; 6209e58c8b4SLorenzo Bianconi }; 6219e58c8b4SLorenzo Bianconi }; 6229e58c8b4SLorenzo Bianconi 623c5aff182SThomas Petazzoni struct mvneta_tx_queue { 624c5aff182SThomas Petazzoni /* Number of this TX queue, in the range 0-7 */ 625c5aff182SThomas Petazzoni u8 id; 626c5aff182SThomas Petazzoni 627c5aff182SThomas Petazzoni /* Number of TX DMA descriptors in the descriptor ring */ 628c5aff182SThomas Petazzoni int size; 629c5aff182SThomas Petazzoni 630c5aff182SThomas Petazzoni /* Number of currently used TX DMA descriptor in the 6316a20c175SThomas Petazzoni * descriptor ring 6326a20c175SThomas Petazzoni */ 633c5aff182SThomas Petazzoni int count; 6342a90f7e1SSimon Guinot int pending; 6358eef5f97SEzequiel Garcia int tx_stop_threshold; 6368eef5f97SEzequiel Garcia int tx_wake_threshold; 637c5aff182SThomas Petazzoni 6389e58c8b4SLorenzo Bianconi /* Array of transmitted buffers */ 6399e58c8b4SLorenzo Bianconi struct mvneta_tx_buf *buf; 640c5aff182SThomas Petazzoni 641c5aff182SThomas Petazzoni /* Index of last TX DMA descriptor that was inserted */ 642c5aff182SThomas Petazzoni int txq_put_index; 643c5aff182SThomas Petazzoni 644c5aff182SThomas Petazzoni /* Index of the TX DMA descriptor to be cleaned up */ 645c5aff182SThomas Petazzoni int txq_get_index; 646c5aff182SThomas Petazzoni 647c5aff182SThomas Petazzoni u32 done_pkts_coal; 648c5aff182SThomas Petazzoni 649c5aff182SThomas Petazzoni /* Virtual address of the TX DMA descriptors array */ 650c5aff182SThomas Petazzoni struct mvneta_tx_desc *descs; 651c5aff182SThomas Petazzoni 652c5aff182SThomas Petazzoni /* DMA address of the TX DMA descriptors array */ 653c5aff182SThomas Petazzoni dma_addr_t descs_phys; 654c5aff182SThomas Petazzoni 655c5aff182SThomas Petazzoni /* Index of the last TX DMA descriptor */ 656c5aff182SThomas Petazzoni int last_desc; 657c5aff182SThomas Petazzoni 658c5aff182SThomas Petazzoni /* Index of the next TX DMA descriptor to process */ 659c5aff182SThomas Petazzoni int next_desc_to_proc; 6602adb719dSEzequiel Garcia 6612adb719dSEzequiel Garcia /* DMA buffers for TSO headers */ 6622adb719dSEzequiel Garcia char *tso_hdrs; 6632adb719dSEzequiel Garcia 6642adb719dSEzequiel Garcia /* DMA address of TSO headers */ 6652adb719dSEzequiel Garcia dma_addr_t tso_hdrs_phys; 66650bf8cb6SGregory CLEMENT 66750bf8cb6SGregory CLEMENT /* Affinity mask for CPUs*/ 66850bf8cb6SGregory CLEMENT cpumask_t affinity_mask; 669c5aff182SThomas Petazzoni }; 670c5aff182SThomas Petazzoni 671c5aff182SThomas Petazzoni struct mvneta_rx_queue { 672c5aff182SThomas Petazzoni /* rx queue number, in the range 0-7 */ 673c5aff182SThomas Petazzoni u8 id; 674c5aff182SThomas Petazzoni 675c5aff182SThomas Petazzoni /* num of rx descriptors in the rx descriptor ring */ 676c5aff182SThomas Petazzoni int size; 677c5aff182SThomas Petazzoni 678c5aff182SThomas Petazzoni u32 pkts_coal; 679c5aff182SThomas Petazzoni u32 time_coal; 680c5aff182SThomas Petazzoni 681568a3fa2SLorenzo Bianconi /* page_pool */ 682568a3fa2SLorenzo Bianconi struct page_pool *page_pool; 683568a3fa2SLorenzo Bianconi struct xdp_rxq_info xdp_rxq; 684568a3fa2SLorenzo Bianconi 685f88bee1cSGregory CLEMENT /* Virtual address of the RX buffer */ 686f88bee1cSGregory CLEMENT void **buf_virt_addr; 687f88bee1cSGregory CLEMENT 688c5aff182SThomas Petazzoni /* Virtual address of the RX DMA descriptors array */ 689c5aff182SThomas Petazzoni struct mvneta_rx_desc *descs; 690c5aff182SThomas Petazzoni 691c5aff182SThomas Petazzoni /* DMA address of the RX DMA descriptors array */ 692c5aff182SThomas Petazzoni dma_addr_t descs_phys; 693c5aff182SThomas Petazzoni 694c5aff182SThomas Petazzoni /* Index of the last RX DMA descriptor */ 695c5aff182SThomas Petazzoni int last_desc; 696c5aff182SThomas Petazzoni 697c5aff182SThomas Petazzoni /* Index of the next RX DMA descriptor to process */ 698c5aff182SThomas Petazzoni int next_desc_to_proc; 69917a96da6SGregory CLEMENT 700562e2f46SYelena Krivosheev /* Index of first RX DMA descriptor to refill */ 701562e2f46SYelena Krivosheev int first_to_refill; 702562e2f46SYelena Krivosheev u32 refill_num; 703c5aff182SThomas Petazzoni }; 704c5aff182SThomas Petazzoni 70584a3f4dbSSebastian Andrzej Siewior static enum cpuhp_state online_hpstate; 706edadb7faSEzequiel Garcia /* The hardware supports eight (8) rx queues, but we are only allowing 707edadb7faSEzequiel Garcia * the first one to be used. Therefore, let's just allocate one queue. 708edadb7faSEzequiel Garcia */ 709d8936657SMaxime Ripard static int rxq_number = 8; 710c5aff182SThomas Petazzoni static int txq_number = 8; 711c5aff182SThomas Petazzoni 712c5aff182SThomas Petazzoni static int rxq_def; 713c5aff182SThomas Petazzoni 714f19fadfcSwilly tarreau static int rx_copybreak __read_mostly = 256; 715f19fadfcSwilly tarreau 716dc35a10fSMarcin Wojtas /* HW BM need that each port be identify by a unique ID */ 717dc35a10fSMarcin Wojtas static int global_port_id; 718dc35a10fSMarcin Wojtas 719c5aff182SThomas Petazzoni #define MVNETA_DRIVER_NAME "mvneta" 720c5aff182SThomas Petazzoni #define MVNETA_DRIVER_VERSION "1.0" 721c5aff182SThomas Petazzoni 722c5aff182SThomas Petazzoni /* Utility/helper methods */ 723c5aff182SThomas Petazzoni 724c5aff182SThomas Petazzoni /* Write helper method */ 725c5aff182SThomas Petazzoni static void mvreg_write(struct mvneta_port *pp, u32 offset, u32 data) 726c5aff182SThomas Petazzoni { 727c5aff182SThomas Petazzoni writel(data, pp->base + offset); 728c5aff182SThomas Petazzoni } 729c5aff182SThomas Petazzoni 730c5aff182SThomas Petazzoni /* Read helper method */ 731c5aff182SThomas Petazzoni static u32 mvreg_read(struct mvneta_port *pp, u32 offset) 732c5aff182SThomas Petazzoni { 733c5aff182SThomas Petazzoni return readl(pp->base + offset); 734c5aff182SThomas Petazzoni } 735c5aff182SThomas Petazzoni 736c5aff182SThomas Petazzoni /* Increment txq get counter */ 737c5aff182SThomas Petazzoni static void mvneta_txq_inc_get(struct mvneta_tx_queue *txq) 738c5aff182SThomas Petazzoni { 739c5aff182SThomas Petazzoni txq->txq_get_index++; 740c5aff182SThomas Petazzoni if (txq->txq_get_index == txq->size) 741c5aff182SThomas Petazzoni txq->txq_get_index = 0; 742c5aff182SThomas Petazzoni } 743c5aff182SThomas Petazzoni 744c5aff182SThomas Petazzoni /* Increment txq put counter */ 745c5aff182SThomas Petazzoni static void mvneta_txq_inc_put(struct mvneta_tx_queue *txq) 746c5aff182SThomas Petazzoni { 747c5aff182SThomas Petazzoni txq->txq_put_index++; 748c5aff182SThomas Petazzoni if (txq->txq_put_index == txq->size) 749c5aff182SThomas Petazzoni txq->txq_put_index = 0; 750c5aff182SThomas Petazzoni } 751c5aff182SThomas Petazzoni 752c5aff182SThomas Petazzoni 753c5aff182SThomas Petazzoni /* Clear all MIB counters */ 754c5aff182SThomas Petazzoni static void mvneta_mib_counters_clear(struct mvneta_port *pp) 755c5aff182SThomas Petazzoni { 756c5aff182SThomas Petazzoni int i; 757c5aff182SThomas Petazzoni 758c5aff182SThomas Petazzoni /* Perform dummy reads from MIB counters */ 759c5aff182SThomas Petazzoni for (i = 0; i < MVNETA_MIB_LATE_COLLISION; i += 4) 760098c2fc6SZhang Changzhong mvreg_read(pp, (MVNETA_MIB_COUNTERS_BASE + i)); 761098c2fc6SZhang Changzhong mvreg_read(pp, MVNETA_RX_DISCARD_FRAME_COUNT); 762098c2fc6SZhang Changzhong mvreg_read(pp, MVNETA_OVERRUN_FRAME_COUNT); 763c5aff182SThomas Petazzoni } 764c5aff182SThomas Petazzoni 765c5aff182SThomas Petazzoni /* Get System Network Statistics */ 766bc1f4470Sstephen hemminger static void 7672dc0d2b4SBaoyou Xie mvneta_get_stats64(struct net_device *dev, 768c5aff182SThomas Petazzoni struct rtnl_link_stats64 *stats) 769c5aff182SThomas Petazzoni { 770c5aff182SThomas Petazzoni struct mvneta_port *pp = netdev_priv(dev); 771c5aff182SThomas Petazzoni unsigned int start; 77274c41b04Swilly tarreau int cpu; 773c5aff182SThomas Petazzoni 77474c41b04Swilly tarreau for_each_possible_cpu(cpu) { 77574c41b04Swilly tarreau struct mvneta_pcpu_stats *cpu_stats; 77674c41b04Swilly tarreau u64 rx_packets; 77774c41b04Swilly tarreau u64 rx_bytes; 778c35947b8SLorenzo Bianconi u64 rx_dropped; 779c35947b8SLorenzo Bianconi u64 rx_errors; 78074c41b04Swilly tarreau u64 tx_packets; 78174c41b04Swilly tarreau u64 tx_bytes; 782c5aff182SThomas Petazzoni 78374c41b04Swilly tarreau cpu_stats = per_cpu_ptr(pp->stats, cpu); 784c5aff182SThomas Petazzoni do { 78557a7744eSEric W. Biederman start = u64_stats_fetch_begin_irq(&cpu_stats->syncp); 786320d5441SLorenzo Bianconi rx_packets = cpu_stats->es.ps.rx_packets; 787320d5441SLorenzo Bianconi rx_bytes = cpu_stats->es.ps.rx_bytes; 788c35947b8SLorenzo Bianconi rx_dropped = cpu_stats->rx_dropped; 789c35947b8SLorenzo Bianconi rx_errors = cpu_stats->rx_errors; 790320d5441SLorenzo Bianconi tx_packets = cpu_stats->es.ps.tx_packets; 791320d5441SLorenzo Bianconi tx_bytes = cpu_stats->es.ps.tx_bytes; 79257a7744eSEric W. Biederman } while (u64_stats_fetch_retry_irq(&cpu_stats->syncp, start)); 793c5aff182SThomas Petazzoni 79474c41b04Swilly tarreau stats->rx_packets += rx_packets; 79574c41b04Swilly tarreau stats->rx_bytes += rx_bytes; 796c35947b8SLorenzo Bianconi stats->rx_dropped += rx_dropped; 797c35947b8SLorenzo Bianconi stats->rx_errors += rx_errors; 79874c41b04Swilly tarreau stats->tx_packets += tx_packets; 79974c41b04Swilly tarreau stats->tx_bytes += tx_bytes; 80074c41b04Swilly tarreau } 801c5aff182SThomas Petazzoni 802c5aff182SThomas Petazzoni stats->tx_dropped = dev->stats.tx_dropped; 803c5aff182SThomas Petazzoni } 804c5aff182SThomas Petazzoni 805c5aff182SThomas Petazzoni /* Rx descriptors helper methods */ 806c5aff182SThomas Petazzoni 8075428213cSwilly tarreau /* Checks whether the RX descriptor having this status is both the first 8085428213cSwilly tarreau * and the last descriptor for the RX packet. Each RX packet is currently 809c5aff182SThomas Petazzoni * received through a single RX descriptor, so not having each RX 810c5aff182SThomas Petazzoni * descriptor with its first and last bits set is an error 811c5aff182SThomas Petazzoni */ 8125428213cSwilly tarreau static int mvneta_rxq_desc_is_first_last(u32 status) 813c5aff182SThomas Petazzoni { 8145428213cSwilly tarreau return (status & MVNETA_RXD_FIRST_LAST_DESC) == 815c5aff182SThomas Petazzoni MVNETA_RXD_FIRST_LAST_DESC; 816c5aff182SThomas Petazzoni } 817c5aff182SThomas Petazzoni 818c5aff182SThomas Petazzoni /* Add number of descriptors ready to receive new packets */ 819c5aff182SThomas Petazzoni static void mvneta_rxq_non_occup_desc_add(struct mvneta_port *pp, 820c5aff182SThomas Petazzoni struct mvneta_rx_queue *rxq, 821c5aff182SThomas Petazzoni int ndescs) 822c5aff182SThomas Petazzoni { 823c5aff182SThomas Petazzoni /* Only MVNETA_RXQ_ADD_NON_OCCUPIED_MAX (255) descriptors can 8246a20c175SThomas Petazzoni * be added at once 8256a20c175SThomas Petazzoni */ 826c5aff182SThomas Petazzoni while (ndescs > MVNETA_RXQ_ADD_NON_OCCUPIED_MAX) { 827c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id), 828c5aff182SThomas Petazzoni (MVNETA_RXQ_ADD_NON_OCCUPIED_MAX << 829c5aff182SThomas Petazzoni MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT)); 830c5aff182SThomas Petazzoni ndescs -= MVNETA_RXQ_ADD_NON_OCCUPIED_MAX; 831c5aff182SThomas Petazzoni } 832c5aff182SThomas Petazzoni 833c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id), 834c5aff182SThomas Petazzoni (ndescs << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT)); 835c5aff182SThomas Petazzoni } 836c5aff182SThomas Petazzoni 837c5aff182SThomas Petazzoni /* Get number of RX descriptors occupied by received packets */ 838c5aff182SThomas Petazzoni static int mvneta_rxq_busy_desc_num_get(struct mvneta_port *pp, 839c5aff182SThomas Petazzoni struct mvneta_rx_queue *rxq) 840c5aff182SThomas Petazzoni { 841c5aff182SThomas Petazzoni u32 val; 842c5aff182SThomas Petazzoni 843c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_RXQ_STATUS_REG(rxq->id)); 844c5aff182SThomas Petazzoni return val & MVNETA_RXQ_OCCUPIED_ALL_MASK; 845c5aff182SThomas Petazzoni } 846c5aff182SThomas Petazzoni 8476a20c175SThomas Petazzoni /* Update num of rx desc called upon return from rx path or 848c5aff182SThomas Petazzoni * from mvneta_rxq_drop_pkts(). 849c5aff182SThomas Petazzoni */ 850c5aff182SThomas Petazzoni static void mvneta_rxq_desc_num_update(struct mvneta_port *pp, 851c5aff182SThomas Petazzoni struct mvneta_rx_queue *rxq, 852c5aff182SThomas Petazzoni int rx_done, int rx_filled) 853c5aff182SThomas Petazzoni { 854c5aff182SThomas Petazzoni u32 val; 855c5aff182SThomas Petazzoni 856c5aff182SThomas Petazzoni if ((rx_done <= 0xff) && (rx_filled <= 0xff)) { 857c5aff182SThomas Petazzoni val = rx_done | 858c5aff182SThomas Petazzoni (rx_filled << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT); 859c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id), val); 860c5aff182SThomas Petazzoni return; 861c5aff182SThomas Petazzoni } 862c5aff182SThomas Petazzoni 863c5aff182SThomas Petazzoni /* Only 255 descriptors can be added at once */ 864c5aff182SThomas Petazzoni while ((rx_done > 0) || (rx_filled > 0)) { 865c5aff182SThomas Petazzoni if (rx_done <= 0xff) { 866c5aff182SThomas Petazzoni val = rx_done; 867c5aff182SThomas Petazzoni rx_done = 0; 868c5aff182SThomas Petazzoni } else { 869c5aff182SThomas Petazzoni val = 0xff; 870c5aff182SThomas Petazzoni rx_done -= 0xff; 871c5aff182SThomas Petazzoni } 872c5aff182SThomas Petazzoni if (rx_filled <= 0xff) { 873c5aff182SThomas Petazzoni val |= rx_filled << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT; 874c5aff182SThomas Petazzoni rx_filled = 0; 875c5aff182SThomas Petazzoni } else { 876c5aff182SThomas Petazzoni val |= 0xff << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT; 877c5aff182SThomas Petazzoni rx_filled -= 0xff; 878c5aff182SThomas Petazzoni } 879c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id), val); 880c5aff182SThomas Petazzoni } 881c5aff182SThomas Petazzoni } 882c5aff182SThomas Petazzoni 883c5aff182SThomas Petazzoni /* Get pointer to next RX descriptor to be processed by SW */ 884c5aff182SThomas Petazzoni static struct mvneta_rx_desc * 885c5aff182SThomas Petazzoni mvneta_rxq_next_desc_get(struct mvneta_rx_queue *rxq) 886c5aff182SThomas Petazzoni { 887c5aff182SThomas Petazzoni int rx_desc = rxq->next_desc_to_proc; 888c5aff182SThomas Petazzoni 889c5aff182SThomas Petazzoni rxq->next_desc_to_proc = MVNETA_QUEUE_NEXT_DESC(rxq, rx_desc); 89034e4179dSwilly tarreau prefetch(rxq->descs + rxq->next_desc_to_proc); 891c5aff182SThomas Petazzoni return rxq->descs + rx_desc; 892c5aff182SThomas Petazzoni } 893c5aff182SThomas Petazzoni 894c5aff182SThomas Petazzoni /* Change maximum receive size of the port. */ 895c5aff182SThomas Petazzoni static void mvneta_max_rx_size_set(struct mvneta_port *pp, int max_rx_size) 896c5aff182SThomas Petazzoni { 897c5aff182SThomas Petazzoni u32 val; 898c5aff182SThomas Petazzoni 899c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_GMAC_CTRL_0); 900c5aff182SThomas Petazzoni val &= ~MVNETA_GMAC_MAX_RX_SIZE_MASK; 901c5aff182SThomas Petazzoni val |= ((max_rx_size - MVNETA_MH_SIZE) / 2) << 902c5aff182SThomas Petazzoni MVNETA_GMAC_MAX_RX_SIZE_SHIFT; 903c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_GMAC_CTRL_0, val); 904c5aff182SThomas Petazzoni } 905c5aff182SThomas Petazzoni 906c5aff182SThomas Petazzoni 907c5aff182SThomas Petazzoni /* Set rx queue offset */ 908c5aff182SThomas Petazzoni static void mvneta_rxq_offset_set(struct mvneta_port *pp, 909c5aff182SThomas Petazzoni struct mvneta_rx_queue *rxq, 910c5aff182SThomas Petazzoni int offset) 911c5aff182SThomas Petazzoni { 912c5aff182SThomas Petazzoni u32 val; 913c5aff182SThomas Petazzoni 914c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_RXQ_CONFIG_REG(rxq->id)); 915c5aff182SThomas Petazzoni val &= ~MVNETA_RXQ_PKT_OFFSET_ALL_MASK; 916c5aff182SThomas Petazzoni 917c5aff182SThomas Petazzoni /* Offset is in */ 918c5aff182SThomas Petazzoni val |= MVNETA_RXQ_PKT_OFFSET_MASK(offset >> 3); 919c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_RXQ_CONFIG_REG(rxq->id), val); 920c5aff182SThomas Petazzoni } 921c5aff182SThomas Petazzoni 922c5aff182SThomas Petazzoni 923c5aff182SThomas Petazzoni /* Tx descriptors helper methods */ 924c5aff182SThomas Petazzoni 925c5aff182SThomas Petazzoni /* Update HW with number of TX descriptors to be sent */ 926c5aff182SThomas Petazzoni static void mvneta_txq_pend_desc_add(struct mvneta_port *pp, 927c5aff182SThomas Petazzoni struct mvneta_tx_queue *txq, 928c5aff182SThomas Petazzoni int pend_desc) 929c5aff182SThomas Petazzoni { 930c5aff182SThomas Petazzoni u32 val; 931c5aff182SThomas Petazzoni 9320d63785cSSimon Guinot pend_desc += txq->pending; 9330d63785cSSimon Guinot 9340d63785cSSimon Guinot /* Only 255 Tx descriptors can be added at once */ 9350d63785cSSimon Guinot do { 9360d63785cSSimon Guinot val = min(pend_desc, 255); 937c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val); 9380d63785cSSimon Guinot pend_desc -= val; 9390d63785cSSimon Guinot } while (pend_desc > 0); 9402a90f7e1SSimon Guinot txq->pending = 0; 941c5aff182SThomas Petazzoni } 942c5aff182SThomas Petazzoni 943c5aff182SThomas Petazzoni /* Get pointer to next TX descriptor to be processed (send) by HW */ 944c5aff182SThomas Petazzoni static struct mvneta_tx_desc * 945c5aff182SThomas Petazzoni mvneta_txq_next_desc_get(struct mvneta_tx_queue *txq) 946c5aff182SThomas Petazzoni { 947c5aff182SThomas Petazzoni int tx_desc = txq->next_desc_to_proc; 948c5aff182SThomas Petazzoni 949c5aff182SThomas Petazzoni txq->next_desc_to_proc = MVNETA_QUEUE_NEXT_DESC(txq, tx_desc); 950c5aff182SThomas Petazzoni return txq->descs + tx_desc; 951c5aff182SThomas Petazzoni } 952c5aff182SThomas Petazzoni 953c5aff182SThomas Petazzoni /* Release the last allocated TX descriptor. Useful to handle DMA 9546a20c175SThomas Petazzoni * mapping failures in the TX path. 9556a20c175SThomas Petazzoni */ 956c5aff182SThomas Petazzoni static void mvneta_txq_desc_put(struct mvneta_tx_queue *txq) 957c5aff182SThomas Petazzoni { 958c5aff182SThomas Petazzoni if (txq->next_desc_to_proc == 0) 959c5aff182SThomas Petazzoni txq->next_desc_to_proc = txq->last_desc - 1; 960c5aff182SThomas Petazzoni else 961c5aff182SThomas Petazzoni txq->next_desc_to_proc--; 962c5aff182SThomas Petazzoni } 963c5aff182SThomas Petazzoni 964c5aff182SThomas Petazzoni /* Set rxq buf size */ 965c5aff182SThomas Petazzoni static void mvneta_rxq_buf_size_set(struct mvneta_port *pp, 966c5aff182SThomas Petazzoni struct mvneta_rx_queue *rxq, 967c5aff182SThomas Petazzoni int buf_size) 968c5aff182SThomas Petazzoni { 969c5aff182SThomas Petazzoni u32 val; 970c5aff182SThomas Petazzoni 971c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_RXQ_SIZE_REG(rxq->id)); 972c5aff182SThomas Petazzoni 973c5aff182SThomas Petazzoni val &= ~MVNETA_RXQ_BUF_SIZE_MASK; 974c5aff182SThomas Petazzoni val |= ((buf_size >> 3) << MVNETA_RXQ_BUF_SIZE_SHIFT); 975c5aff182SThomas Petazzoni 976c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_RXQ_SIZE_REG(rxq->id), val); 977c5aff182SThomas Petazzoni } 978c5aff182SThomas Petazzoni 979c5aff182SThomas Petazzoni /* Disable buffer management (BM) */ 980c5aff182SThomas Petazzoni static void mvneta_rxq_bm_disable(struct mvneta_port *pp, 981c5aff182SThomas Petazzoni struct mvneta_rx_queue *rxq) 982c5aff182SThomas Petazzoni { 983c5aff182SThomas Petazzoni u32 val; 984c5aff182SThomas Petazzoni 985c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_RXQ_CONFIG_REG(rxq->id)); 986c5aff182SThomas Petazzoni val &= ~MVNETA_RXQ_HW_BUF_ALLOC; 987c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_RXQ_CONFIG_REG(rxq->id), val); 988c5aff182SThomas Petazzoni } 989c5aff182SThomas Petazzoni 990dc35a10fSMarcin Wojtas /* Enable buffer management (BM) */ 991dc35a10fSMarcin Wojtas static void mvneta_rxq_bm_enable(struct mvneta_port *pp, 992dc35a10fSMarcin Wojtas struct mvneta_rx_queue *rxq) 993dc35a10fSMarcin Wojtas { 994dc35a10fSMarcin Wojtas u32 val; 995dc35a10fSMarcin Wojtas 996dc35a10fSMarcin Wojtas val = mvreg_read(pp, MVNETA_RXQ_CONFIG_REG(rxq->id)); 997dc35a10fSMarcin Wojtas val |= MVNETA_RXQ_HW_BUF_ALLOC; 998dc35a10fSMarcin Wojtas mvreg_write(pp, MVNETA_RXQ_CONFIG_REG(rxq->id), val); 999dc35a10fSMarcin Wojtas } 1000dc35a10fSMarcin Wojtas 1001dc35a10fSMarcin Wojtas /* Notify HW about port's assignment of pool for bigger packets */ 1002dc35a10fSMarcin Wojtas static void mvneta_rxq_long_pool_set(struct mvneta_port *pp, 1003dc35a10fSMarcin Wojtas struct mvneta_rx_queue *rxq) 1004dc35a10fSMarcin Wojtas { 1005dc35a10fSMarcin Wojtas u32 val; 1006dc35a10fSMarcin Wojtas 1007dc35a10fSMarcin Wojtas val = mvreg_read(pp, MVNETA_RXQ_CONFIG_REG(rxq->id)); 1008dc35a10fSMarcin Wojtas val &= ~MVNETA_RXQ_LONG_POOL_ID_MASK; 1009dc35a10fSMarcin Wojtas val |= (pp->pool_long->id << MVNETA_RXQ_LONG_POOL_ID_SHIFT); 1010dc35a10fSMarcin Wojtas 1011dc35a10fSMarcin Wojtas mvreg_write(pp, MVNETA_RXQ_CONFIG_REG(rxq->id), val); 1012dc35a10fSMarcin Wojtas } 1013dc35a10fSMarcin Wojtas 1014dc35a10fSMarcin Wojtas /* Notify HW about port's assignment of pool for smaller packets */ 1015dc35a10fSMarcin Wojtas static void mvneta_rxq_short_pool_set(struct mvneta_port *pp, 1016dc35a10fSMarcin Wojtas struct mvneta_rx_queue *rxq) 1017dc35a10fSMarcin Wojtas { 1018dc35a10fSMarcin Wojtas u32 val; 1019dc35a10fSMarcin Wojtas 1020dc35a10fSMarcin Wojtas val = mvreg_read(pp, MVNETA_RXQ_CONFIG_REG(rxq->id)); 1021dc35a10fSMarcin Wojtas val &= ~MVNETA_RXQ_SHORT_POOL_ID_MASK; 1022dc35a10fSMarcin Wojtas val |= (pp->pool_short->id << MVNETA_RXQ_SHORT_POOL_ID_SHIFT); 1023dc35a10fSMarcin Wojtas 1024dc35a10fSMarcin Wojtas mvreg_write(pp, MVNETA_RXQ_CONFIG_REG(rxq->id), val); 1025dc35a10fSMarcin Wojtas } 1026dc35a10fSMarcin Wojtas 1027dc35a10fSMarcin Wojtas /* Set port's receive buffer size for assigned BM pool */ 1028dc35a10fSMarcin Wojtas static inline void mvneta_bm_pool_bufsize_set(struct mvneta_port *pp, 1029dc35a10fSMarcin Wojtas int buf_size, 1030dc35a10fSMarcin Wojtas u8 pool_id) 1031dc35a10fSMarcin Wojtas { 1032dc35a10fSMarcin Wojtas u32 val; 1033dc35a10fSMarcin Wojtas 1034dc35a10fSMarcin Wojtas if (!IS_ALIGNED(buf_size, 8)) { 1035dc35a10fSMarcin Wojtas dev_warn(pp->dev->dev.parent, 1036dc35a10fSMarcin Wojtas "illegal buf_size value %d, round to %d\n", 1037dc35a10fSMarcin Wojtas buf_size, ALIGN(buf_size, 8)); 1038dc35a10fSMarcin Wojtas buf_size = ALIGN(buf_size, 8); 1039dc35a10fSMarcin Wojtas } 1040dc35a10fSMarcin Wojtas 1041dc35a10fSMarcin Wojtas val = mvreg_read(pp, MVNETA_PORT_POOL_BUFFER_SZ_REG(pool_id)); 1042dc35a10fSMarcin Wojtas val |= buf_size & MVNETA_PORT_POOL_BUFFER_SZ_MASK; 1043dc35a10fSMarcin Wojtas mvreg_write(pp, MVNETA_PORT_POOL_BUFFER_SZ_REG(pool_id), val); 1044dc35a10fSMarcin Wojtas } 1045dc35a10fSMarcin Wojtas 1046dc35a10fSMarcin Wojtas /* Configure MBUS window in order to enable access BM internal SRAM */ 1047dc35a10fSMarcin Wojtas static int mvneta_mbus_io_win_set(struct mvneta_port *pp, u32 base, u32 wsize, 1048dc35a10fSMarcin Wojtas u8 target, u8 attr) 1049dc35a10fSMarcin Wojtas { 1050dc35a10fSMarcin Wojtas u32 win_enable, win_protect; 1051dc35a10fSMarcin Wojtas int i; 1052dc35a10fSMarcin Wojtas 1053dc35a10fSMarcin Wojtas win_enable = mvreg_read(pp, MVNETA_BASE_ADDR_ENABLE); 1054dc35a10fSMarcin Wojtas 1055dc35a10fSMarcin Wojtas if (pp->bm_win_id < 0) { 1056dc35a10fSMarcin Wojtas /* Find first not occupied window */ 1057dc35a10fSMarcin Wojtas for (i = 0; i < MVNETA_MAX_DECODE_WIN; i++) { 1058dc35a10fSMarcin Wojtas if (win_enable & (1 << i)) { 1059dc35a10fSMarcin Wojtas pp->bm_win_id = i; 1060dc35a10fSMarcin Wojtas break; 1061dc35a10fSMarcin Wojtas } 1062dc35a10fSMarcin Wojtas } 1063dc35a10fSMarcin Wojtas if (i == MVNETA_MAX_DECODE_WIN) 1064dc35a10fSMarcin Wojtas return -ENOMEM; 1065dc35a10fSMarcin Wojtas } else { 1066dc35a10fSMarcin Wojtas i = pp->bm_win_id; 1067dc35a10fSMarcin Wojtas } 1068dc35a10fSMarcin Wojtas 1069dc35a10fSMarcin Wojtas mvreg_write(pp, MVNETA_WIN_BASE(i), 0); 1070dc35a10fSMarcin Wojtas mvreg_write(pp, MVNETA_WIN_SIZE(i), 0); 1071dc35a10fSMarcin Wojtas 1072dc35a10fSMarcin Wojtas if (i < 4) 1073dc35a10fSMarcin Wojtas mvreg_write(pp, MVNETA_WIN_REMAP(i), 0); 1074dc35a10fSMarcin Wojtas 1075dc35a10fSMarcin Wojtas mvreg_write(pp, MVNETA_WIN_BASE(i), (base & 0xffff0000) | 1076dc35a10fSMarcin Wojtas (attr << 8) | target); 1077dc35a10fSMarcin Wojtas 1078dc35a10fSMarcin Wojtas mvreg_write(pp, MVNETA_WIN_SIZE(i), (wsize - 1) & 0xffff0000); 1079dc35a10fSMarcin Wojtas 1080dc35a10fSMarcin Wojtas win_protect = mvreg_read(pp, MVNETA_ACCESS_PROTECT_ENABLE); 1081dc35a10fSMarcin Wojtas win_protect |= 3 << (2 * i); 1082dc35a10fSMarcin Wojtas mvreg_write(pp, MVNETA_ACCESS_PROTECT_ENABLE, win_protect); 1083dc35a10fSMarcin Wojtas 1084dc35a10fSMarcin Wojtas win_enable &= ~(1 << i); 1085dc35a10fSMarcin Wojtas mvreg_write(pp, MVNETA_BASE_ADDR_ENABLE, win_enable); 1086dc35a10fSMarcin Wojtas 1087dc35a10fSMarcin Wojtas return 0; 1088dc35a10fSMarcin Wojtas } 1089dc35a10fSMarcin Wojtas 10902636ac3cSMarcin Wojtas static int mvneta_bm_port_mbus_init(struct mvneta_port *pp) 1091dc35a10fSMarcin Wojtas { 10922636ac3cSMarcin Wojtas u32 wsize; 1093dc35a10fSMarcin Wojtas u8 target, attr; 1094dc35a10fSMarcin Wojtas int err; 1095dc35a10fSMarcin Wojtas 1096dc35a10fSMarcin Wojtas /* Get BM window information */ 1097dc35a10fSMarcin Wojtas err = mvebu_mbus_get_io_win_info(pp->bm_priv->bppi_phys_addr, &wsize, 1098dc35a10fSMarcin Wojtas &target, &attr); 1099dc35a10fSMarcin Wojtas if (err < 0) 1100dc35a10fSMarcin Wojtas return err; 1101dc35a10fSMarcin Wojtas 1102dc35a10fSMarcin Wojtas pp->bm_win_id = -1; 1103dc35a10fSMarcin Wojtas 1104dc35a10fSMarcin Wojtas /* Open NETA -> BM window */ 1105dc35a10fSMarcin Wojtas err = mvneta_mbus_io_win_set(pp, pp->bm_priv->bppi_phys_addr, wsize, 1106dc35a10fSMarcin Wojtas target, attr); 1107dc35a10fSMarcin Wojtas if (err < 0) { 1108dc35a10fSMarcin Wojtas netdev_info(pp->dev, "fail to configure mbus window to BM\n"); 1109dc35a10fSMarcin Wojtas return err; 1110dc35a10fSMarcin Wojtas } 11112636ac3cSMarcin Wojtas return 0; 11122636ac3cSMarcin Wojtas } 11132636ac3cSMarcin Wojtas 11142636ac3cSMarcin Wojtas /* Assign and initialize pools for port. In case of fail 11152636ac3cSMarcin Wojtas * buffer manager will remain disabled for current port. 11162636ac3cSMarcin Wojtas */ 11172636ac3cSMarcin Wojtas static int mvneta_bm_port_init(struct platform_device *pdev, 11182636ac3cSMarcin Wojtas struct mvneta_port *pp) 11192636ac3cSMarcin Wojtas { 11202636ac3cSMarcin Wojtas struct device_node *dn = pdev->dev.of_node; 11212636ac3cSMarcin Wojtas u32 long_pool_id, short_pool_id; 11222636ac3cSMarcin Wojtas 11232636ac3cSMarcin Wojtas if (!pp->neta_armada3700) { 11242636ac3cSMarcin Wojtas int ret; 11252636ac3cSMarcin Wojtas 11262636ac3cSMarcin Wojtas ret = mvneta_bm_port_mbus_init(pp); 11272636ac3cSMarcin Wojtas if (ret) 11282636ac3cSMarcin Wojtas return ret; 11292636ac3cSMarcin Wojtas } 1130dc35a10fSMarcin Wojtas 1131dc35a10fSMarcin Wojtas if (of_property_read_u32(dn, "bm,pool-long", &long_pool_id)) { 1132dc35a10fSMarcin Wojtas netdev_info(pp->dev, "missing long pool id\n"); 1133dc35a10fSMarcin Wojtas return -EINVAL; 1134dc35a10fSMarcin Wojtas } 1135dc35a10fSMarcin Wojtas 1136dc35a10fSMarcin Wojtas /* Create port's long pool depending on mtu */ 1137dc35a10fSMarcin Wojtas pp->pool_long = mvneta_bm_pool_use(pp->bm_priv, long_pool_id, 1138dc35a10fSMarcin Wojtas MVNETA_BM_LONG, pp->id, 1139dc35a10fSMarcin Wojtas MVNETA_RX_PKT_SIZE(pp->dev->mtu)); 1140dc35a10fSMarcin Wojtas if (!pp->pool_long) { 1141dc35a10fSMarcin Wojtas netdev_info(pp->dev, "fail to obtain long pool for port\n"); 1142dc35a10fSMarcin Wojtas return -ENOMEM; 1143dc35a10fSMarcin Wojtas } 1144dc35a10fSMarcin Wojtas 1145dc35a10fSMarcin Wojtas pp->pool_long->port_map |= 1 << pp->id; 1146dc35a10fSMarcin Wojtas 1147dc35a10fSMarcin Wojtas mvneta_bm_pool_bufsize_set(pp, pp->pool_long->buf_size, 1148dc35a10fSMarcin Wojtas pp->pool_long->id); 1149dc35a10fSMarcin Wojtas 1150dc35a10fSMarcin Wojtas /* If short pool id is not defined, assume using single pool */ 1151dc35a10fSMarcin Wojtas if (of_property_read_u32(dn, "bm,pool-short", &short_pool_id)) 1152dc35a10fSMarcin Wojtas short_pool_id = long_pool_id; 1153dc35a10fSMarcin Wojtas 1154dc35a10fSMarcin Wojtas /* Create port's short pool */ 1155dc35a10fSMarcin Wojtas pp->pool_short = mvneta_bm_pool_use(pp->bm_priv, short_pool_id, 1156dc35a10fSMarcin Wojtas MVNETA_BM_SHORT, pp->id, 1157dc35a10fSMarcin Wojtas MVNETA_BM_SHORT_PKT_SIZE); 1158dc35a10fSMarcin Wojtas if (!pp->pool_short) { 1159dc35a10fSMarcin Wojtas netdev_info(pp->dev, "fail to obtain short pool for port\n"); 1160dc35a10fSMarcin Wojtas mvneta_bm_pool_destroy(pp->bm_priv, pp->pool_long, 1 << pp->id); 1161dc35a10fSMarcin Wojtas return -ENOMEM; 1162dc35a10fSMarcin Wojtas } 1163dc35a10fSMarcin Wojtas 1164dc35a10fSMarcin Wojtas if (short_pool_id != long_pool_id) { 1165dc35a10fSMarcin Wojtas pp->pool_short->port_map |= 1 << pp->id; 1166dc35a10fSMarcin Wojtas mvneta_bm_pool_bufsize_set(pp, pp->pool_short->buf_size, 1167dc35a10fSMarcin Wojtas pp->pool_short->id); 1168dc35a10fSMarcin Wojtas } 1169dc35a10fSMarcin Wojtas 1170dc35a10fSMarcin Wojtas return 0; 1171dc35a10fSMarcin Wojtas } 1172dc35a10fSMarcin Wojtas 1173dc35a10fSMarcin Wojtas /* Update settings of a pool for bigger packets */ 1174dc35a10fSMarcin Wojtas static void mvneta_bm_update_mtu(struct mvneta_port *pp, int mtu) 1175dc35a10fSMarcin Wojtas { 1176dc35a10fSMarcin Wojtas struct mvneta_bm_pool *bm_pool = pp->pool_long; 1177baa11ebcSGregory CLEMENT struct hwbm_pool *hwbm_pool = &bm_pool->hwbm_pool; 1178dc35a10fSMarcin Wojtas int num; 1179dc35a10fSMarcin Wojtas 1180dc35a10fSMarcin Wojtas /* Release all buffers from long pool */ 1181dc35a10fSMarcin Wojtas mvneta_bm_bufs_free(pp->bm_priv, bm_pool, 1 << pp->id); 1182baa11ebcSGregory CLEMENT if (hwbm_pool->buf_num) { 1183dc35a10fSMarcin Wojtas WARN(1, "cannot free all buffers in pool %d\n", 1184dc35a10fSMarcin Wojtas bm_pool->id); 1185dc35a10fSMarcin Wojtas goto bm_mtu_err; 1186dc35a10fSMarcin Wojtas } 1187dc35a10fSMarcin Wojtas 1188dc35a10fSMarcin Wojtas bm_pool->pkt_size = MVNETA_RX_PKT_SIZE(mtu); 1189dc35a10fSMarcin Wojtas bm_pool->buf_size = MVNETA_RX_BUF_SIZE(bm_pool->pkt_size); 1190baa11ebcSGregory CLEMENT hwbm_pool->frag_size = SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) + 1191dc35a10fSMarcin Wojtas SKB_DATA_ALIGN(MVNETA_RX_BUF_SIZE(bm_pool->pkt_size)); 1192dc35a10fSMarcin Wojtas 1193dc35a10fSMarcin Wojtas /* Fill entire long pool */ 11946dcdd884SSebastian Andrzej Siewior num = hwbm_pool_add(hwbm_pool, hwbm_pool->size); 1195baa11ebcSGregory CLEMENT if (num != hwbm_pool->size) { 1196dc35a10fSMarcin Wojtas WARN(1, "pool %d: %d of %d allocated\n", 1197baa11ebcSGregory CLEMENT bm_pool->id, num, hwbm_pool->size); 1198dc35a10fSMarcin Wojtas goto bm_mtu_err; 1199dc35a10fSMarcin Wojtas } 1200dc35a10fSMarcin Wojtas mvneta_bm_pool_bufsize_set(pp, bm_pool->buf_size, bm_pool->id); 1201dc35a10fSMarcin Wojtas 1202dc35a10fSMarcin Wojtas return; 1203dc35a10fSMarcin Wojtas 1204dc35a10fSMarcin Wojtas bm_mtu_err: 1205dc35a10fSMarcin Wojtas mvneta_bm_pool_destroy(pp->bm_priv, pp->pool_long, 1 << pp->id); 1206dc35a10fSMarcin Wojtas mvneta_bm_pool_destroy(pp->bm_priv, pp->pool_short, 1 << pp->id); 1207dc35a10fSMarcin Wojtas 1208dc35a10fSMarcin Wojtas pp->bm_priv = NULL; 120944efc78dSLorenzo Bianconi pp->rx_offset_correction = MVNETA_SKB_HEADROOM; 1210dc35a10fSMarcin Wojtas mvreg_write(pp, MVNETA_ACC_MODE, MVNETA_ACC_MODE_EXT1); 1211dc35a10fSMarcin Wojtas netdev_info(pp->dev, "fail to update MTU, fall back to software BM\n"); 1212dc35a10fSMarcin Wojtas } 1213dc35a10fSMarcin Wojtas 1214c5aff182SThomas Petazzoni /* Start the Ethernet port RX and TX activity */ 1215c5aff182SThomas Petazzoni static void mvneta_port_up(struct mvneta_port *pp) 1216c5aff182SThomas Petazzoni { 1217c5aff182SThomas Petazzoni int queue; 1218c5aff182SThomas Petazzoni u32 q_map; 1219c5aff182SThomas Petazzoni 1220c5aff182SThomas Petazzoni /* Enable all initialized TXs. */ 1221c5aff182SThomas Petazzoni q_map = 0; 1222c5aff182SThomas Petazzoni for (queue = 0; queue < txq_number; queue++) { 1223c5aff182SThomas Petazzoni struct mvneta_tx_queue *txq = &pp->txqs[queue]; 1224f95936ccSMarkus Elfring if (txq->descs) 1225c5aff182SThomas Petazzoni q_map |= (1 << queue); 1226c5aff182SThomas Petazzoni } 1227c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_TXQ_CMD, q_map); 1228c5aff182SThomas Petazzoni 1229e81b5e01SYelena Krivosheev q_map = 0; 1230c5aff182SThomas Petazzoni /* Enable all initialized RXQs. */ 12312dcf75e2SGregory CLEMENT for (queue = 0; queue < rxq_number; queue++) { 12322dcf75e2SGregory CLEMENT struct mvneta_rx_queue *rxq = &pp->rxqs[queue]; 12332dcf75e2SGregory CLEMENT 1234f95936ccSMarkus Elfring if (rxq->descs) 12352dcf75e2SGregory CLEMENT q_map |= (1 << queue); 12362dcf75e2SGregory CLEMENT } 12372dcf75e2SGregory CLEMENT mvreg_write(pp, MVNETA_RXQ_CMD, q_map); 1238c5aff182SThomas Petazzoni } 1239c5aff182SThomas Petazzoni 1240c5aff182SThomas Petazzoni /* Stop the Ethernet port activity */ 1241c5aff182SThomas Petazzoni static void mvneta_port_down(struct mvneta_port *pp) 1242c5aff182SThomas Petazzoni { 1243c5aff182SThomas Petazzoni u32 val; 1244c5aff182SThomas Petazzoni int count; 1245c5aff182SThomas Petazzoni 1246c5aff182SThomas Petazzoni /* Stop Rx port activity. Check port Rx activity. */ 1247c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_RXQ_CMD) & MVNETA_RXQ_ENABLE_MASK; 1248c5aff182SThomas Petazzoni 1249c5aff182SThomas Petazzoni /* Issue stop command for active channels only */ 1250c5aff182SThomas Petazzoni if (val != 0) 1251c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_RXQ_CMD, 1252c5aff182SThomas Petazzoni val << MVNETA_RXQ_DISABLE_SHIFT); 1253c5aff182SThomas Petazzoni 1254c5aff182SThomas Petazzoni /* Wait for all Rx activity to terminate. */ 1255c5aff182SThomas Petazzoni count = 0; 1256c5aff182SThomas Petazzoni do { 1257c5aff182SThomas Petazzoni if (count++ >= MVNETA_RX_DISABLE_TIMEOUT_MSEC) { 1258c5aff182SThomas Petazzoni netdev_warn(pp->dev, 12590838abb3SDmitri Epshtein "TIMEOUT for RX stopped ! rx_queue_cmd: 0x%08x\n", 1260c5aff182SThomas Petazzoni val); 1261c5aff182SThomas Petazzoni break; 1262c5aff182SThomas Petazzoni } 1263c5aff182SThomas Petazzoni mdelay(1); 1264c5aff182SThomas Petazzoni 1265c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_RXQ_CMD); 1266a3703fb3SDmitri Epshtein } while (val & MVNETA_RXQ_ENABLE_MASK); 1267c5aff182SThomas Petazzoni 1268c5aff182SThomas Petazzoni /* Stop Tx port activity. Check port Tx activity. Issue stop 12696a20c175SThomas Petazzoni * command for active channels only 12706a20c175SThomas Petazzoni */ 1271c5aff182SThomas Petazzoni val = (mvreg_read(pp, MVNETA_TXQ_CMD)) & MVNETA_TXQ_ENABLE_MASK; 1272c5aff182SThomas Petazzoni 1273c5aff182SThomas Petazzoni if (val != 0) 1274c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_TXQ_CMD, 1275c5aff182SThomas Petazzoni (val << MVNETA_TXQ_DISABLE_SHIFT)); 1276c5aff182SThomas Petazzoni 1277c5aff182SThomas Petazzoni /* Wait for all Tx activity to terminate. */ 1278c5aff182SThomas Petazzoni count = 0; 1279c5aff182SThomas Petazzoni do { 1280c5aff182SThomas Petazzoni if (count++ >= MVNETA_TX_DISABLE_TIMEOUT_MSEC) { 1281c5aff182SThomas Petazzoni netdev_warn(pp->dev, 1282c5aff182SThomas Petazzoni "TIMEOUT for TX stopped status=0x%08x\n", 1283c5aff182SThomas Petazzoni val); 1284c5aff182SThomas Petazzoni break; 1285c5aff182SThomas Petazzoni } 1286c5aff182SThomas Petazzoni mdelay(1); 1287c5aff182SThomas Petazzoni 1288c5aff182SThomas Petazzoni /* Check TX Command reg that all Txqs are stopped */ 1289c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_TXQ_CMD); 1290c5aff182SThomas Petazzoni 1291a3703fb3SDmitri Epshtein } while (val & MVNETA_TXQ_ENABLE_MASK); 1292c5aff182SThomas Petazzoni 1293c5aff182SThomas Petazzoni /* Double check to verify that TX FIFO is empty */ 1294c5aff182SThomas Petazzoni count = 0; 1295c5aff182SThomas Petazzoni do { 1296c5aff182SThomas Petazzoni if (count++ >= MVNETA_TX_FIFO_EMPTY_TIMEOUT) { 1297c5aff182SThomas Petazzoni netdev_warn(pp->dev, 12980838abb3SDmitri Epshtein "TX FIFO empty timeout status=0x%08x\n", 1299c5aff182SThomas Petazzoni val); 1300c5aff182SThomas Petazzoni break; 1301c5aff182SThomas Petazzoni } 1302c5aff182SThomas Petazzoni mdelay(1); 1303c5aff182SThomas Petazzoni 1304c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_PORT_STATUS); 1305c5aff182SThomas Petazzoni } while (!(val & MVNETA_TX_FIFO_EMPTY) && 1306c5aff182SThomas Petazzoni (val & MVNETA_TX_IN_PRGRS)); 1307c5aff182SThomas Petazzoni 1308c5aff182SThomas Petazzoni udelay(200); 1309c5aff182SThomas Petazzoni } 1310c5aff182SThomas Petazzoni 1311c5aff182SThomas Petazzoni /* Enable the port by setting the port enable bit of the MAC control register */ 1312c5aff182SThomas Petazzoni static void mvneta_port_enable(struct mvneta_port *pp) 1313c5aff182SThomas Petazzoni { 1314c5aff182SThomas Petazzoni u32 val; 1315c5aff182SThomas Petazzoni 1316c5aff182SThomas Petazzoni /* Enable port */ 1317c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_GMAC_CTRL_0); 1318c5aff182SThomas Petazzoni val |= MVNETA_GMAC0_PORT_ENABLE; 1319c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_GMAC_CTRL_0, val); 1320c5aff182SThomas Petazzoni } 1321c5aff182SThomas Petazzoni 1322c5aff182SThomas Petazzoni /* Disable the port and wait for about 200 usec before retuning */ 1323c5aff182SThomas Petazzoni static void mvneta_port_disable(struct mvneta_port *pp) 1324c5aff182SThomas Petazzoni { 1325c5aff182SThomas Petazzoni u32 val; 1326c5aff182SThomas Petazzoni 1327c5aff182SThomas Petazzoni /* Reset the Enable bit in the Serial Control Register */ 1328c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_GMAC_CTRL_0); 1329c5aff182SThomas Petazzoni val &= ~MVNETA_GMAC0_PORT_ENABLE; 1330c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_GMAC_CTRL_0, val); 1331c5aff182SThomas Petazzoni 1332c5aff182SThomas Petazzoni udelay(200); 1333c5aff182SThomas Petazzoni } 1334c5aff182SThomas Petazzoni 1335c5aff182SThomas Petazzoni /* Multicast tables methods */ 1336c5aff182SThomas Petazzoni 1337c5aff182SThomas Petazzoni /* Set all entries in Unicast MAC Table; queue==-1 means reject all */ 1338c5aff182SThomas Petazzoni static void mvneta_set_ucast_table(struct mvneta_port *pp, int queue) 1339c5aff182SThomas Petazzoni { 1340c5aff182SThomas Petazzoni int offset; 1341c5aff182SThomas Petazzoni u32 val; 1342c5aff182SThomas Petazzoni 1343c5aff182SThomas Petazzoni if (queue == -1) { 1344c5aff182SThomas Petazzoni val = 0; 1345c5aff182SThomas Petazzoni } else { 1346c5aff182SThomas Petazzoni val = 0x1 | (queue << 1); 1347c5aff182SThomas Petazzoni val |= (val << 24) | (val << 16) | (val << 8); 1348c5aff182SThomas Petazzoni } 1349c5aff182SThomas Petazzoni 1350c5aff182SThomas Petazzoni for (offset = 0; offset <= 0xc; offset += 4) 1351c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_DA_FILT_UCAST_BASE + offset, val); 1352c5aff182SThomas Petazzoni } 1353c5aff182SThomas Petazzoni 1354c5aff182SThomas Petazzoni /* Set all entries in Special Multicast MAC Table; queue==-1 means reject all */ 1355c5aff182SThomas Petazzoni static void mvneta_set_special_mcast_table(struct mvneta_port *pp, int queue) 1356c5aff182SThomas Petazzoni { 1357c5aff182SThomas Petazzoni int offset; 1358c5aff182SThomas Petazzoni u32 val; 1359c5aff182SThomas Petazzoni 1360c5aff182SThomas Petazzoni if (queue == -1) { 1361c5aff182SThomas Petazzoni val = 0; 1362c5aff182SThomas Petazzoni } else { 1363c5aff182SThomas Petazzoni val = 0x1 | (queue << 1); 1364c5aff182SThomas Petazzoni val |= (val << 24) | (val << 16) | (val << 8); 1365c5aff182SThomas Petazzoni } 1366c5aff182SThomas Petazzoni 1367c5aff182SThomas Petazzoni for (offset = 0; offset <= 0xfc; offset += 4) 1368c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_DA_FILT_SPEC_MCAST + offset, val); 1369c5aff182SThomas Petazzoni 1370c5aff182SThomas Petazzoni } 1371c5aff182SThomas Petazzoni 1372c5aff182SThomas Petazzoni /* Set all entries in Other Multicast MAC Table. queue==-1 means reject all */ 1373c5aff182SThomas Petazzoni static void mvneta_set_other_mcast_table(struct mvneta_port *pp, int queue) 1374c5aff182SThomas Petazzoni { 1375c5aff182SThomas Petazzoni int offset; 1376c5aff182SThomas Petazzoni u32 val; 1377c5aff182SThomas Petazzoni 1378c5aff182SThomas Petazzoni if (queue == -1) { 1379c5aff182SThomas Petazzoni memset(pp->mcast_count, 0, sizeof(pp->mcast_count)); 1380c5aff182SThomas Petazzoni val = 0; 1381c5aff182SThomas Petazzoni } else { 1382c5aff182SThomas Petazzoni memset(pp->mcast_count, 1, sizeof(pp->mcast_count)); 1383c5aff182SThomas Petazzoni val = 0x1 | (queue << 1); 1384c5aff182SThomas Petazzoni val |= (val << 24) | (val << 16) | (val << 8); 1385c5aff182SThomas Petazzoni } 1386c5aff182SThomas Petazzoni 1387c5aff182SThomas Petazzoni for (offset = 0; offset <= 0xfc; offset += 4) 1388c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_DA_FILT_OTH_MCAST + offset, val); 1389c5aff182SThomas Petazzoni } 1390c5aff182SThomas Petazzoni 1391db488c10SGregory CLEMENT static void mvneta_percpu_unmask_interrupt(void *arg) 1392db488c10SGregory CLEMENT { 1393db488c10SGregory CLEMENT struct mvneta_port *pp = arg; 1394db488c10SGregory CLEMENT 1395db488c10SGregory CLEMENT /* All the queue are unmasked, but actually only the ones 1396db488c10SGregory CLEMENT * mapped to this CPU will be unmasked 1397db488c10SGregory CLEMENT */ 1398db488c10SGregory CLEMENT mvreg_write(pp, MVNETA_INTR_NEW_MASK, 1399db488c10SGregory CLEMENT MVNETA_RX_INTR_MASK_ALL | 1400db488c10SGregory CLEMENT MVNETA_TX_INTR_MASK_ALL | 1401db488c10SGregory CLEMENT MVNETA_MISCINTR_INTR_MASK); 1402db488c10SGregory CLEMENT } 1403db488c10SGregory CLEMENT 1404db488c10SGregory CLEMENT static void mvneta_percpu_mask_interrupt(void *arg) 1405db488c10SGregory CLEMENT { 1406db488c10SGregory CLEMENT struct mvneta_port *pp = arg; 1407db488c10SGregory CLEMENT 1408db488c10SGregory CLEMENT /* All the queue are masked, but actually only the ones 1409db488c10SGregory CLEMENT * mapped to this CPU will be masked 1410db488c10SGregory CLEMENT */ 1411db488c10SGregory CLEMENT mvreg_write(pp, MVNETA_INTR_NEW_MASK, 0); 1412db488c10SGregory CLEMENT mvreg_write(pp, MVNETA_INTR_OLD_MASK, 0); 1413db488c10SGregory CLEMENT mvreg_write(pp, MVNETA_INTR_MISC_MASK, 0); 1414db488c10SGregory CLEMENT } 1415db488c10SGregory CLEMENT 1416db488c10SGregory CLEMENT static void mvneta_percpu_clear_intr_cause(void *arg) 1417db488c10SGregory CLEMENT { 1418db488c10SGregory CLEMENT struct mvneta_port *pp = arg; 1419db488c10SGregory CLEMENT 1420db488c10SGregory CLEMENT /* All the queue are cleared, but actually only the ones 1421db488c10SGregory CLEMENT * mapped to this CPU will be cleared 1422db488c10SGregory CLEMENT */ 1423db488c10SGregory CLEMENT mvreg_write(pp, MVNETA_INTR_NEW_CAUSE, 0); 1424db488c10SGregory CLEMENT mvreg_write(pp, MVNETA_INTR_MISC_CAUSE, 0); 1425db488c10SGregory CLEMENT mvreg_write(pp, MVNETA_INTR_OLD_CAUSE, 0); 1426db488c10SGregory CLEMENT } 1427db488c10SGregory CLEMENT 1428c5aff182SThomas Petazzoni /* This method sets defaults to the NETA port: 1429c5aff182SThomas Petazzoni * Clears interrupt Cause and Mask registers. 1430c5aff182SThomas Petazzoni * Clears all MAC tables. 1431c5aff182SThomas Petazzoni * Sets defaults to all registers. 1432c5aff182SThomas Petazzoni * Resets RX and TX descriptor rings. 1433c5aff182SThomas Petazzoni * Resets PHY. 1434c5aff182SThomas Petazzoni * This method can be called after mvneta_port_down() to return the port 1435c5aff182SThomas Petazzoni * settings to defaults. 1436c5aff182SThomas Petazzoni */ 1437c5aff182SThomas Petazzoni static void mvneta_defaults_set(struct mvneta_port *pp) 1438c5aff182SThomas Petazzoni { 1439c5aff182SThomas Petazzoni int cpu; 1440c5aff182SThomas Petazzoni int queue; 1441c5aff182SThomas Petazzoni u32 val; 14422dcf75e2SGregory CLEMENT int max_cpu = num_present_cpus(); 1443c5aff182SThomas Petazzoni 1444c5aff182SThomas Petazzoni /* Clear all Cause registers */ 1445db488c10SGregory CLEMENT on_each_cpu(mvneta_percpu_clear_intr_cause, pp, true); 1446c5aff182SThomas Petazzoni 1447c5aff182SThomas Petazzoni /* Mask all interrupts */ 1448db488c10SGregory CLEMENT on_each_cpu(mvneta_percpu_mask_interrupt, pp, true); 1449c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_INTR_ENABLE, 0); 1450c5aff182SThomas Petazzoni 1451c5aff182SThomas Petazzoni /* Enable MBUS Retry bit16 */ 1452c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_MBUS_RETRY, 0x20); 1453c5aff182SThomas Petazzoni 145450bf8cb6SGregory CLEMENT /* Set CPU queue access map. CPUs are assigned to the RX and 145550bf8cb6SGregory CLEMENT * TX queues modulo their number. If there is only one TX 145650bf8cb6SGregory CLEMENT * queue then it is assigned to the CPU associated to the 145750bf8cb6SGregory CLEMENT * default RX queue. 14586a20c175SThomas Petazzoni */ 14592dcf75e2SGregory CLEMENT for_each_present_cpu(cpu) { 14602dcf75e2SGregory CLEMENT int rxq_map = 0, txq_map = 0; 146150bf8cb6SGregory CLEMENT int rxq, txq; 14622636ac3cSMarcin Wojtas if (!pp->neta_armada3700) { 14632dcf75e2SGregory CLEMENT for (rxq = 0; rxq < rxq_number; rxq++) 14642dcf75e2SGregory CLEMENT if ((rxq % max_cpu) == cpu) 14652dcf75e2SGregory CLEMENT rxq_map |= MVNETA_CPU_RXQ_ACCESS(rxq); 14662dcf75e2SGregory CLEMENT 146750bf8cb6SGregory CLEMENT for (txq = 0; txq < txq_number; txq++) 146850bf8cb6SGregory CLEMENT if ((txq % max_cpu) == cpu) 146950bf8cb6SGregory CLEMENT txq_map |= MVNETA_CPU_TXQ_ACCESS(txq); 147050bf8cb6SGregory CLEMENT 147150bf8cb6SGregory CLEMENT /* With only one TX queue we configure a special case 147250bf8cb6SGregory CLEMENT * which will allow to get all the irq on a single 147350bf8cb6SGregory CLEMENT * CPU 147450bf8cb6SGregory CLEMENT */ 147550bf8cb6SGregory CLEMENT if (txq_number == 1) 147650bf8cb6SGregory CLEMENT txq_map = (cpu == pp->rxq_def) ? 147750bf8cb6SGregory CLEMENT MVNETA_CPU_TXQ_ACCESS(1) : 0; 14782dcf75e2SGregory CLEMENT 14792636ac3cSMarcin Wojtas } else { 14802636ac3cSMarcin Wojtas txq_map = MVNETA_CPU_TXQ_ACCESS_ALL_MASK; 14812636ac3cSMarcin Wojtas rxq_map = MVNETA_CPU_RXQ_ACCESS_ALL_MASK; 14822636ac3cSMarcin Wojtas } 14832636ac3cSMarcin Wojtas 14842dcf75e2SGregory CLEMENT mvreg_write(pp, MVNETA_CPU_MAP(cpu), rxq_map | txq_map); 14852dcf75e2SGregory CLEMENT } 1486c5aff182SThomas Petazzoni 1487c5aff182SThomas Petazzoni /* Reset RX and TX DMAs */ 1488c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_PORT_RX_RESET, MVNETA_PORT_RX_DMA_RESET); 1489c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_PORT_TX_RESET, MVNETA_PORT_TX_DMA_RESET); 1490c5aff182SThomas Petazzoni 1491c5aff182SThomas Petazzoni /* Disable Legacy WRR, Disable EJP, Release from reset */ 1492c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_TXQ_CMD_1, 0); 1493c5aff182SThomas Petazzoni for (queue = 0; queue < txq_number; queue++) { 1494c5aff182SThomas Petazzoni mvreg_write(pp, MVETH_TXQ_TOKEN_COUNT_REG(queue), 0); 1495c5aff182SThomas Petazzoni mvreg_write(pp, MVETH_TXQ_TOKEN_CFG_REG(queue), 0); 1496c5aff182SThomas Petazzoni } 1497c5aff182SThomas Petazzoni 1498c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_PORT_TX_RESET, 0); 1499c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_PORT_RX_RESET, 0); 1500c5aff182SThomas Petazzoni 1501c5aff182SThomas Petazzoni /* Set Port Acceleration Mode */ 1502dc35a10fSMarcin Wojtas if (pp->bm_priv) 1503dc35a10fSMarcin Wojtas /* HW buffer management + legacy parser */ 1504dc35a10fSMarcin Wojtas val = MVNETA_ACC_MODE_EXT2; 1505dc35a10fSMarcin Wojtas else 1506dc35a10fSMarcin Wojtas /* SW buffer management + legacy parser */ 1507dc35a10fSMarcin Wojtas val = MVNETA_ACC_MODE_EXT1; 1508c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_ACC_MODE, val); 1509c5aff182SThomas Petazzoni 1510dc35a10fSMarcin Wojtas if (pp->bm_priv) 1511dc35a10fSMarcin Wojtas mvreg_write(pp, MVNETA_BM_ADDRESS, pp->bm_priv->bppi_phys_addr); 1512dc35a10fSMarcin Wojtas 1513c5aff182SThomas Petazzoni /* Update val of portCfg register accordingly with all RxQueue types */ 151490b74c01SGregory CLEMENT val = MVNETA_PORT_CONFIG_DEFL_VALUE(pp->rxq_def); 1515c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_PORT_CONFIG, val); 1516c5aff182SThomas Petazzoni 1517c5aff182SThomas Petazzoni val = 0; 1518c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_PORT_CONFIG_EXTEND, val); 1519c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_RX_MIN_FRAME_SIZE, 64); 1520c5aff182SThomas Petazzoni 1521c5aff182SThomas Petazzoni /* Build PORT_SDMA_CONFIG_REG */ 1522c5aff182SThomas Petazzoni val = 0; 1523c5aff182SThomas Petazzoni 1524c5aff182SThomas Petazzoni /* Default burst size */ 1525c5aff182SThomas Petazzoni val |= MVNETA_TX_BRST_SZ_MASK(MVNETA_SDMA_BRST_SIZE_16); 1526c5aff182SThomas Petazzoni val |= MVNETA_RX_BRST_SZ_MASK(MVNETA_SDMA_BRST_SIZE_16); 15279ad8fef6SThomas Petazzoni val |= MVNETA_RX_NO_DATA_SWAP | MVNETA_TX_NO_DATA_SWAP; 1528c5aff182SThomas Petazzoni 15299ad8fef6SThomas Petazzoni #if defined(__BIG_ENDIAN) 15309ad8fef6SThomas Petazzoni val |= MVNETA_DESC_SWAP; 15319ad8fef6SThomas Petazzoni #endif 1532c5aff182SThomas Petazzoni 1533c5aff182SThomas Petazzoni /* Assign port SDMA configuration */ 1534c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_SDMA_CONFIG, val); 1535c5aff182SThomas Petazzoni 153671408602SThomas Petazzoni /* Disable PHY polling in hardware, since we're using the 153771408602SThomas Petazzoni * kernel phylib to do this. 153871408602SThomas Petazzoni */ 153971408602SThomas Petazzoni val = mvreg_read(pp, MVNETA_UNIT_CONTROL); 154071408602SThomas Petazzoni val &= ~MVNETA_PHY_POLLING_ENABLE; 154171408602SThomas Petazzoni mvreg_write(pp, MVNETA_UNIT_CONTROL, val); 154271408602SThomas Petazzoni 1543c5aff182SThomas Petazzoni mvneta_set_ucast_table(pp, -1); 1544c5aff182SThomas Petazzoni mvneta_set_special_mcast_table(pp, -1); 1545c5aff182SThomas Petazzoni mvneta_set_other_mcast_table(pp, -1); 1546c5aff182SThomas Petazzoni 1547c5aff182SThomas Petazzoni /* Set port interrupt enable register - default enable all */ 1548c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_INTR_ENABLE, 1549c5aff182SThomas Petazzoni (MVNETA_RXQ_INTR_ENABLE_ALL_MASK 1550c5aff182SThomas Petazzoni | MVNETA_TXQ_INTR_ENABLE_ALL_MASK)); 1551e483911fSAndrew Lunn 1552e483911fSAndrew Lunn mvneta_mib_counters_clear(pp); 1553c5aff182SThomas Petazzoni } 1554c5aff182SThomas Petazzoni 1555c5aff182SThomas Petazzoni /* Set max sizes for tx queues */ 1556c5aff182SThomas Petazzoni static void mvneta_txq_max_tx_size_set(struct mvneta_port *pp, int max_tx_size) 1557c5aff182SThomas Petazzoni 1558c5aff182SThomas Petazzoni { 1559c5aff182SThomas Petazzoni u32 val, size, mtu; 1560c5aff182SThomas Petazzoni int queue; 1561c5aff182SThomas Petazzoni 1562c5aff182SThomas Petazzoni mtu = max_tx_size * 8; 1563c5aff182SThomas Petazzoni if (mtu > MVNETA_TX_MTU_MAX) 1564c5aff182SThomas Petazzoni mtu = MVNETA_TX_MTU_MAX; 1565c5aff182SThomas Petazzoni 1566c5aff182SThomas Petazzoni /* Set MTU */ 1567c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_TX_MTU); 1568c5aff182SThomas Petazzoni val &= ~MVNETA_TX_MTU_MAX; 1569c5aff182SThomas Petazzoni val |= mtu; 1570c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_TX_MTU, val); 1571c5aff182SThomas Petazzoni 1572c5aff182SThomas Petazzoni /* TX token size and all TXQs token size must be larger that MTU */ 1573c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_TX_TOKEN_SIZE); 1574c5aff182SThomas Petazzoni 1575c5aff182SThomas Petazzoni size = val & MVNETA_TX_TOKEN_SIZE_MAX; 1576c5aff182SThomas Petazzoni if (size < mtu) { 1577c5aff182SThomas Petazzoni size = mtu; 1578c5aff182SThomas Petazzoni val &= ~MVNETA_TX_TOKEN_SIZE_MAX; 1579c5aff182SThomas Petazzoni val |= size; 1580c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_TX_TOKEN_SIZE, val); 1581c5aff182SThomas Petazzoni } 1582c5aff182SThomas Petazzoni for (queue = 0; queue < txq_number; queue++) { 1583c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_TXQ_TOKEN_SIZE_REG(queue)); 1584c5aff182SThomas Petazzoni 1585c5aff182SThomas Petazzoni size = val & MVNETA_TXQ_TOKEN_SIZE_MAX; 1586c5aff182SThomas Petazzoni if (size < mtu) { 1587c5aff182SThomas Petazzoni size = mtu; 1588c5aff182SThomas Petazzoni val &= ~MVNETA_TXQ_TOKEN_SIZE_MAX; 1589c5aff182SThomas Petazzoni val |= size; 1590c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_TXQ_TOKEN_SIZE_REG(queue), val); 1591c5aff182SThomas Petazzoni } 1592c5aff182SThomas Petazzoni } 1593c5aff182SThomas Petazzoni } 1594c5aff182SThomas Petazzoni 1595c5aff182SThomas Petazzoni /* Set unicast address */ 1596c5aff182SThomas Petazzoni static void mvneta_set_ucast_addr(struct mvneta_port *pp, u8 last_nibble, 1597c5aff182SThomas Petazzoni int queue) 1598c5aff182SThomas Petazzoni { 1599c5aff182SThomas Petazzoni unsigned int unicast_reg; 1600c5aff182SThomas Petazzoni unsigned int tbl_offset; 1601c5aff182SThomas Petazzoni unsigned int reg_offset; 1602c5aff182SThomas Petazzoni 1603c5aff182SThomas Petazzoni /* Locate the Unicast table entry */ 1604c5aff182SThomas Petazzoni last_nibble = (0xf & last_nibble); 1605c5aff182SThomas Petazzoni 1606c5aff182SThomas Petazzoni /* offset from unicast tbl base */ 1607c5aff182SThomas Petazzoni tbl_offset = (last_nibble / 4) * 4; 1608c5aff182SThomas Petazzoni 1609c5aff182SThomas Petazzoni /* offset within the above reg */ 1610c5aff182SThomas Petazzoni reg_offset = last_nibble % 4; 1611c5aff182SThomas Petazzoni 1612c5aff182SThomas Petazzoni unicast_reg = mvreg_read(pp, (MVNETA_DA_FILT_UCAST_BASE + tbl_offset)); 1613c5aff182SThomas Petazzoni 1614c5aff182SThomas Petazzoni if (queue == -1) { 1615c5aff182SThomas Petazzoni /* Clear accepts frame bit at specified unicast DA tbl entry */ 1616c5aff182SThomas Petazzoni unicast_reg &= ~(0xff << (8 * reg_offset)); 1617c5aff182SThomas Petazzoni } else { 1618c5aff182SThomas Petazzoni unicast_reg &= ~(0xff << (8 * reg_offset)); 1619c5aff182SThomas Petazzoni unicast_reg |= ((0x01 | (queue << 1)) << (8 * reg_offset)); 1620c5aff182SThomas Petazzoni } 1621c5aff182SThomas Petazzoni 1622c5aff182SThomas Petazzoni mvreg_write(pp, (MVNETA_DA_FILT_UCAST_BASE + tbl_offset), unicast_reg); 1623c5aff182SThomas Petazzoni } 1624c5aff182SThomas Petazzoni 1625c5aff182SThomas Petazzoni /* Set mac address */ 162676660757SJakub Kicinski static void mvneta_mac_addr_set(struct mvneta_port *pp, 162776660757SJakub Kicinski const unsigned char *addr, int queue) 1628c5aff182SThomas Petazzoni { 1629c5aff182SThomas Petazzoni unsigned int mac_h; 1630c5aff182SThomas Petazzoni unsigned int mac_l; 1631c5aff182SThomas Petazzoni 1632c5aff182SThomas Petazzoni if (queue != -1) { 1633c5aff182SThomas Petazzoni mac_l = (addr[4] << 8) | (addr[5]); 1634c5aff182SThomas Petazzoni mac_h = (addr[0] << 24) | (addr[1] << 16) | 1635c5aff182SThomas Petazzoni (addr[2] << 8) | (addr[3] << 0); 1636c5aff182SThomas Petazzoni 1637c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_MAC_ADDR_LOW, mac_l); 1638c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_MAC_ADDR_HIGH, mac_h); 1639c5aff182SThomas Petazzoni } 1640c5aff182SThomas Petazzoni 1641c5aff182SThomas Petazzoni /* Accept frames of this address */ 1642c5aff182SThomas Petazzoni mvneta_set_ucast_addr(pp, addr[5], queue); 1643c5aff182SThomas Petazzoni } 1644c5aff182SThomas Petazzoni 16456a20c175SThomas Petazzoni /* Set the number of packets that will be received before RX interrupt 16466a20c175SThomas Petazzoni * will be generated by HW. 1647c5aff182SThomas Petazzoni */ 1648c5aff182SThomas Petazzoni static void mvneta_rx_pkts_coal_set(struct mvneta_port *pp, 1649c5aff182SThomas Petazzoni struct mvneta_rx_queue *rxq, u32 value) 1650c5aff182SThomas Petazzoni { 1651c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_RXQ_THRESHOLD_REG(rxq->id), 1652c5aff182SThomas Petazzoni value | MVNETA_RXQ_NON_OCCUPIED(0)); 1653c5aff182SThomas Petazzoni } 1654c5aff182SThomas Petazzoni 16556a20c175SThomas Petazzoni /* Set the time delay in usec before RX interrupt will be generated by 16566a20c175SThomas Petazzoni * HW. 1657c5aff182SThomas Petazzoni */ 1658c5aff182SThomas Petazzoni static void mvneta_rx_time_coal_set(struct mvneta_port *pp, 1659c5aff182SThomas Petazzoni struct mvneta_rx_queue *rxq, u32 value) 1660c5aff182SThomas Petazzoni { 1661189dd626SThomas Petazzoni u32 val; 1662189dd626SThomas Petazzoni unsigned long clk_rate; 1663189dd626SThomas Petazzoni 1664189dd626SThomas Petazzoni clk_rate = clk_get_rate(pp->clk); 1665189dd626SThomas Petazzoni val = (clk_rate / 1000000) * value; 1666c5aff182SThomas Petazzoni 1667c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_RXQ_TIME_COAL_REG(rxq->id), val); 1668c5aff182SThomas Petazzoni } 1669c5aff182SThomas Petazzoni 1670c5aff182SThomas Petazzoni /* Set threshold for TX_DONE pkts coalescing */ 1671c5aff182SThomas Petazzoni static void mvneta_tx_done_pkts_coal_set(struct mvneta_port *pp, 1672c5aff182SThomas Petazzoni struct mvneta_tx_queue *txq, u32 value) 1673c5aff182SThomas Petazzoni { 1674c5aff182SThomas Petazzoni u32 val; 1675c5aff182SThomas Petazzoni 1676c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_TXQ_SIZE_REG(txq->id)); 1677c5aff182SThomas Petazzoni 1678c5aff182SThomas Petazzoni val &= ~MVNETA_TXQ_SENT_THRESH_ALL_MASK; 1679c5aff182SThomas Petazzoni val |= MVNETA_TXQ_SENT_THRESH_MASK(value); 1680c5aff182SThomas Petazzoni 1681c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_TXQ_SIZE_REG(txq->id), val); 1682c5aff182SThomas Petazzoni } 1683c5aff182SThomas Petazzoni 1684c5aff182SThomas Petazzoni /* Handle rx descriptor fill by setting buf_cookie and buf_phys_addr */ 1685c5aff182SThomas Petazzoni static void mvneta_rx_desc_fill(struct mvneta_rx_desc *rx_desc, 1686f88bee1cSGregory CLEMENT u32 phys_addr, void *virt_addr, 1687f88bee1cSGregory CLEMENT struct mvneta_rx_queue *rxq) 1688c5aff182SThomas Petazzoni { 1689f88bee1cSGregory CLEMENT int i; 1690f88bee1cSGregory CLEMENT 1691c5aff182SThomas Petazzoni rx_desc->buf_phys_addr = phys_addr; 1692f88bee1cSGregory CLEMENT i = rx_desc - rxq->descs; 1693f88bee1cSGregory CLEMENT rxq->buf_virt_addr[i] = virt_addr; 1694c5aff182SThomas Petazzoni } 1695c5aff182SThomas Petazzoni 1696c5aff182SThomas Petazzoni /* Decrement sent descriptors counter */ 1697c5aff182SThomas Petazzoni static void mvneta_txq_sent_desc_dec(struct mvneta_port *pp, 1698c5aff182SThomas Petazzoni struct mvneta_tx_queue *txq, 1699c5aff182SThomas Petazzoni int sent_desc) 1700c5aff182SThomas Petazzoni { 1701c5aff182SThomas Petazzoni u32 val; 1702c5aff182SThomas Petazzoni 1703c5aff182SThomas Petazzoni /* Only 255 TX descriptors can be updated at once */ 1704c5aff182SThomas Petazzoni while (sent_desc > 0xff) { 1705c5aff182SThomas Petazzoni val = 0xff << MVNETA_TXQ_DEC_SENT_SHIFT; 1706c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val); 1707c5aff182SThomas Petazzoni sent_desc = sent_desc - 0xff; 1708c5aff182SThomas Petazzoni } 1709c5aff182SThomas Petazzoni 1710c5aff182SThomas Petazzoni val = sent_desc << MVNETA_TXQ_DEC_SENT_SHIFT; 1711c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val); 1712c5aff182SThomas Petazzoni } 1713c5aff182SThomas Petazzoni 1714c5aff182SThomas Petazzoni /* Get number of TX descriptors already sent by HW */ 1715c5aff182SThomas Petazzoni static int mvneta_txq_sent_desc_num_get(struct mvneta_port *pp, 1716c5aff182SThomas Petazzoni struct mvneta_tx_queue *txq) 1717c5aff182SThomas Petazzoni { 1718c5aff182SThomas Petazzoni u32 val; 1719c5aff182SThomas Petazzoni int sent_desc; 1720c5aff182SThomas Petazzoni 1721c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_TXQ_STATUS_REG(txq->id)); 1722c5aff182SThomas Petazzoni sent_desc = (val & MVNETA_TXQ_SENT_DESC_MASK) >> 1723c5aff182SThomas Petazzoni MVNETA_TXQ_SENT_DESC_SHIFT; 1724c5aff182SThomas Petazzoni 1725c5aff182SThomas Petazzoni return sent_desc; 1726c5aff182SThomas Petazzoni } 1727c5aff182SThomas Petazzoni 17286a20c175SThomas Petazzoni /* Get number of sent descriptors and decrement counter. 1729c5aff182SThomas Petazzoni * The number of sent descriptors is returned. 1730c5aff182SThomas Petazzoni */ 1731c5aff182SThomas Petazzoni static int mvneta_txq_sent_desc_proc(struct mvneta_port *pp, 1732c5aff182SThomas Petazzoni struct mvneta_tx_queue *txq) 1733c5aff182SThomas Petazzoni { 1734c5aff182SThomas Petazzoni int sent_desc; 1735c5aff182SThomas Petazzoni 1736c5aff182SThomas Petazzoni /* Get number of sent descriptors */ 1737c5aff182SThomas Petazzoni sent_desc = mvneta_txq_sent_desc_num_get(pp, txq); 1738c5aff182SThomas Petazzoni 1739c5aff182SThomas Petazzoni /* Decrement sent descriptors counter */ 1740c5aff182SThomas Petazzoni if (sent_desc) 1741c5aff182SThomas Petazzoni mvneta_txq_sent_desc_dec(pp, txq, sent_desc); 1742c5aff182SThomas Petazzoni 1743c5aff182SThomas Petazzoni return sent_desc; 1744c5aff182SThomas Petazzoni } 1745c5aff182SThomas Petazzoni 1746c5aff182SThomas Petazzoni /* Set TXQ descriptors fields relevant for CSUM calculation */ 1747c5aff182SThomas Petazzoni static u32 mvneta_txq_desc_csum(int l3_offs, int l3_proto, 1748c5aff182SThomas Petazzoni int ip_hdr_len, int l4_proto) 1749c5aff182SThomas Petazzoni { 1750c5aff182SThomas Petazzoni u32 command; 1751c5aff182SThomas Petazzoni 1752c5aff182SThomas Petazzoni /* Fields: L3_offset, IP_hdrlen, L3_type, G_IPv4_chk, 17536a20c175SThomas Petazzoni * G_L4_chk, L4_type; required only for checksum 17546a20c175SThomas Petazzoni * calculation 17556a20c175SThomas Petazzoni */ 1756c5aff182SThomas Petazzoni command = l3_offs << MVNETA_TX_L3_OFF_SHIFT; 1757c5aff182SThomas Petazzoni command |= ip_hdr_len << MVNETA_TX_IP_HLEN_SHIFT; 1758c5aff182SThomas Petazzoni 17590a198587SThomas Fitzsimmons if (l3_proto == htons(ETH_P_IP)) 1760c5aff182SThomas Petazzoni command |= MVNETA_TXD_IP_CSUM; 1761c5aff182SThomas Petazzoni else 1762c5aff182SThomas Petazzoni command |= MVNETA_TX_L3_IP6; 1763c5aff182SThomas Petazzoni 1764c5aff182SThomas Petazzoni if (l4_proto == IPPROTO_TCP) 1765c5aff182SThomas Petazzoni command |= MVNETA_TX_L4_CSUM_FULL; 1766c5aff182SThomas Petazzoni else if (l4_proto == IPPROTO_UDP) 1767c5aff182SThomas Petazzoni command |= MVNETA_TX_L4_UDP | MVNETA_TX_L4_CSUM_FULL; 1768c5aff182SThomas Petazzoni else 1769c5aff182SThomas Petazzoni command |= MVNETA_TX_L4_CSUM_NOT; 1770c5aff182SThomas Petazzoni 1771c5aff182SThomas Petazzoni return command; 1772c5aff182SThomas Petazzoni } 1773c5aff182SThomas Petazzoni 1774c5aff182SThomas Petazzoni 1775c5aff182SThomas Petazzoni /* Display more error info */ 1776c5aff182SThomas Petazzoni static void mvneta_rx_error(struct mvneta_port *pp, 1777c5aff182SThomas Petazzoni struct mvneta_rx_desc *rx_desc) 1778c5aff182SThomas Petazzoni { 1779c35947b8SLorenzo Bianconi struct mvneta_pcpu_stats *stats = this_cpu_ptr(pp->stats); 1780c5aff182SThomas Petazzoni u32 status = rx_desc->status; 1781c5aff182SThomas Petazzoni 1782c35947b8SLorenzo Bianconi /* update per-cpu counter */ 1783c35947b8SLorenzo Bianconi u64_stats_update_begin(&stats->syncp); 1784c35947b8SLorenzo Bianconi stats->rx_errors++; 1785c35947b8SLorenzo Bianconi u64_stats_update_end(&stats->syncp); 1786c35947b8SLorenzo Bianconi 1787c5aff182SThomas Petazzoni switch (status & MVNETA_RXD_ERR_CODE_MASK) { 1788c5aff182SThomas Petazzoni case MVNETA_RXD_ERR_CRC: 1789c5aff182SThomas Petazzoni netdev_err(pp->dev, "bad rx status %08x (crc error), size=%d\n", 1790c5aff182SThomas Petazzoni status, rx_desc->data_size); 1791c5aff182SThomas Petazzoni break; 1792c5aff182SThomas Petazzoni case MVNETA_RXD_ERR_OVERRUN: 1793c5aff182SThomas Petazzoni netdev_err(pp->dev, "bad rx status %08x (overrun error), size=%d\n", 1794c5aff182SThomas Petazzoni status, rx_desc->data_size); 1795c5aff182SThomas Petazzoni break; 1796c5aff182SThomas Petazzoni case MVNETA_RXD_ERR_LEN: 1797c5aff182SThomas Petazzoni netdev_err(pp->dev, "bad rx status %08x (max frame length error), size=%d\n", 1798c5aff182SThomas Petazzoni status, rx_desc->data_size); 1799c5aff182SThomas Petazzoni break; 1800c5aff182SThomas Petazzoni case MVNETA_RXD_ERR_RESOURCE: 1801c5aff182SThomas Petazzoni netdev_err(pp->dev, "bad rx status %08x (resource error), size=%d\n", 1802c5aff182SThomas Petazzoni status, rx_desc->data_size); 1803c5aff182SThomas Petazzoni break; 1804c5aff182SThomas Petazzoni } 1805c5aff182SThomas Petazzoni } 1806c5aff182SThomas Petazzoni 18075428213cSwilly tarreau /* Handle RX checksum offload based on the descriptor's status */ 1808aff0824dSLorenzo Bianconi static int mvneta_rx_csum(struct mvneta_port *pp, u32 status) 1809c5aff182SThomas Petazzoni { 1810f945cec8SYelena Krivosheev if ((pp->dev->features & NETIF_F_RXCSUM) && 1811f945cec8SYelena Krivosheev (status & MVNETA_RXD_L3_IP4) && 1812aff0824dSLorenzo Bianconi (status & MVNETA_RXD_L4_CSUM_OK)) 1813aff0824dSLorenzo Bianconi return CHECKSUM_UNNECESSARY; 1814c5aff182SThomas Petazzoni 1815aff0824dSLorenzo Bianconi return CHECKSUM_NONE; 1816c5aff182SThomas Petazzoni } 1817c5aff182SThomas Petazzoni 18186c498974Swilly tarreau /* Return tx queue pointer (find last set bit) according to <cause> returned 18196c498974Swilly tarreau * form tx_done reg. <cause> must not be null. The return value is always a 18206c498974Swilly tarreau * valid queue for matching the first one found in <cause>. 18216c498974Swilly tarreau */ 1822c5aff182SThomas Petazzoni static struct mvneta_tx_queue *mvneta_tx_done_policy(struct mvneta_port *pp, 1823c5aff182SThomas Petazzoni u32 cause) 1824c5aff182SThomas Petazzoni { 1825c5aff182SThomas Petazzoni int queue = fls(cause) - 1; 1826c5aff182SThomas Petazzoni 18276c498974Swilly tarreau return &pp->txqs[queue]; 1828c5aff182SThomas Petazzoni } 1829c5aff182SThomas Petazzoni 1830c5aff182SThomas Petazzoni /* Free tx queue skbuffs */ 1831c5aff182SThomas Petazzoni static void mvneta_txq_bufs_free(struct mvneta_port *pp, 1832a29b6235SMarcin Wojtas struct mvneta_tx_queue *txq, int num, 1833632bb64fSLorenzo Bianconi struct netdev_queue *nq, bool napi) 1834c5aff182SThomas Petazzoni { 1835a29b6235SMarcin Wojtas unsigned int bytes_compl = 0, pkts_compl = 0; 18362f9d0939SLorenzo Bianconi struct xdp_frame_bulk bq; 1837c5aff182SThomas Petazzoni int i; 1838c5aff182SThomas Petazzoni 18392f9d0939SLorenzo Bianconi xdp_frame_bulk_init(&bq); 18402f9d0939SLorenzo Bianconi 18412f9d0939SLorenzo Bianconi rcu_read_lock(); /* need for xdp_return_frame_bulk */ 18422f9d0939SLorenzo Bianconi 1843c5aff182SThomas Petazzoni for (i = 0; i < num; i++) { 18449e58c8b4SLorenzo Bianconi struct mvneta_tx_buf *buf = &txq->buf[txq->txq_get_index]; 1845c5aff182SThomas Petazzoni struct mvneta_tx_desc *tx_desc = txq->descs + 1846c5aff182SThomas Petazzoni txq->txq_get_index; 1847a29b6235SMarcin Wojtas 1848c5aff182SThomas Petazzoni mvneta_txq_inc_get(txq); 1849c5aff182SThomas Petazzoni 1850b0a43db9SLorenzo Bianconi if (!IS_TSO_HEADER(txq, tx_desc->buf_phys_addr) && 1851b0a43db9SLorenzo Bianconi buf->type != MVNETA_TYPE_XDP_TX) 18522e3173a3SEzequiel Garcia dma_unmap_single(pp->dev->dev.parent, 18532e3173a3SEzequiel Garcia tx_desc->buf_phys_addr, 1854c5aff182SThomas Petazzoni tx_desc->data_size, DMA_TO_DEVICE); 1855b0a43db9SLorenzo Bianconi if (buf->type == MVNETA_TYPE_SKB && buf->skb) { 18569e58c8b4SLorenzo Bianconi bytes_compl += buf->skb->len; 18579e58c8b4SLorenzo Bianconi pkts_compl++; 18589e58c8b4SLorenzo Bianconi dev_kfree_skb_any(buf->skb); 1859b0a43db9SLorenzo Bianconi } else if (buf->type == MVNETA_TYPE_XDP_TX || 1860b0a43db9SLorenzo Bianconi buf->type == MVNETA_TYPE_XDP_NDO) { 1861632bb64fSLorenzo Bianconi if (napi && buf->type == MVNETA_TYPE_XDP_TX) 1862632bb64fSLorenzo Bianconi xdp_return_frame_rx_napi(buf->xdpf); 1863632bb64fSLorenzo Bianconi else 18642f9d0939SLorenzo Bianconi xdp_return_frame_bulk(buf->xdpf, &bq); 1865b0a43db9SLorenzo Bianconi } 1866c5aff182SThomas Petazzoni } 18672f9d0939SLorenzo Bianconi xdp_flush_frame_bulk(&bq); 18682f9d0939SLorenzo Bianconi 18692f9d0939SLorenzo Bianconi rcu_read_unlock(); 1870a29b6235SMarcin Wojtas 1871a29b6235SMarcin Wojtas netdev_tx_completed_queue(nq, pkts_compl, bytes_compl); 1872c5aff182SThomas Petazzoni } 1873c5aff182SThomas Petazzoni 1874c5aff182SThomas Petazzoni /* Handle end of transmission */ 1875cd713199SArnaud Ebalard static void mvneta_txq_done(struct mvneta_port *pp, 1876c5aff182SThomas Petazzoni struct mvneta_tx_queue *txq) 1877c5aff182SThomas Petazzoni { 1878c5aff182SThomas Petazzoni struct netdev_queue *nq = netdev_get_tx_queue(pp->dev, txq->id); 1879c5aff182SThomas Petazzoni int tx_done; 1880c5aff182SThomas Petazzoni 1881c5aff182SThomas Petazzoni tx_done = mvneta_txq_sent_desc_proc(pp, txq); 1882cd713199SArnaud Ebalard if (!tx_done) 1883cd713199SArnaud Ebalard return; 1884cd713199SArnaud Ebalard 1885632bb64fSLorenzo Bianconi mvneta_txq_bufs_free(pp, txq, tx_done, nq, true); 1886c5aff182SThomas Petazzoni 1887c5aff182SThomas Petazzoni txq->count -= tx_done; 1888c5aff182SThomas Petazzoni 1889c5aff182SThomas Petazzoni if (netif_tx_queue_stopped(nq)) { 18908eef5f97SEzequiel Garcia if (txq->count <= txq->tx_wake_threshold) 1891c5aff182SThomas Petazzoni netif_tx_wake_queue(nq); 1892c5aff182SThomas Petazzoni } 1893c5aff182SThomas Petazzoni } 1894c5aff182SThomas Petazzoni 1895dc35a10fSMarcin Wojtas /* Refill processing for SW buffer management */ 18967e47fd84SGregory CLEMENT /* Allocate page per descriptor */ 1897c5aff182SThomas Petazzoni static int mvneta_rx_refill(struct mvneta_port *pp, 1898f88bee1cSGregory CLEMENT struct mvneta_rx_desc *rx_desc, 18997e47fd84SGregory CLEMENT struct mvneta_rx_queue *rxq, 19007e47fd84SGregory CLEMENT gfp_t gfp_mask) 1901c5aff182SThomas Petazzoni { 1902c5aff182SThomas Petazzoni dma_addr_t phys_addr; 19037e47fd84SGregory CLEMENT struct page *page; 1904c5aff182SThomas Petazzoni 1905568a3fa2SLorenzo Bianconi page = page_pool_alloc_pages(rxq->page_pool, 1906568a3fa2SLorenzo Bianconi gfp_mask | __GFP_NOWARN); 19077e47fd84SGregory CLEMENT if (!page) 1908c5aff182SThomas Petazzoni return -ENOMEM; 1909c5aff182SThomas Petazzoni 1910568a3fa2SLorenzo Bianconi phys_addr = page_pool_get_dma_addr(page) + pp->rx_offset_correction; 19117e47fd84SGregory CLEMENT mvneta_rx_desc_fill(rx_desc, phys_addr, page, rxq); 1912568a3fa2SLorenzo Bianconi 1913c5aff182SThomas Petazzoni return 0; 1914c5aff182SThomas Petazzoni } 1915c5aff182SThomas Petazzoni 1916c5aff182SThomas Petazzoni /* Handle tx checksum */ 191720d446f2SYuval Shaia static u32 mvneta_skb_tx_csum(struct sk_buff *skb) 1918c5aff182SThomas Petazzoni { 1919c5aff182SThomas Petazzoni if (skb->ip_summed == CHECKSUM_PARTIAL) { 1920c5aff182SThomas Petazzoni int ip_hdr_len = 0; 1921817dbfa5SVlad Yasevich __be16 l3_proto = vlan_get_protocol(skb); 1922c5aff182SThomas Petazzoni u8 l4_proto; 1923c5aff182SThomas Petazzoni 1924817dbfa5SVlad Yasevich if (l3_proto == htons(ETH_P_IP)) { 1925c5aff182SThomas Petazzoni struct iphdr *ip4h = ip_hdr(skb); 1926c5aff182SThomas Petazzoni 1927c5aff182SThomas Petazzoni /* Calculate IPv4 checksum and L4 checksum */ 1928c5aff182SThomas Petazzoni ip_hdr_len = ip4h->ihl; 1929c5aff182SThomas Petazzoni l4_proto = ip4h->protocol; 1930817dbfa5SVlad Yasevich } else if (l3_proto == htons(ETH_P_IPV6)) { 1931c5aff182SThomas Petazzoni struct ipv6hdr *ip6h = ipv6_hdr(skb); 1932c5aff182SThomas Petazzoni 1933c5aff182SThomas Petazzoni /* Read l4_protocol from one of IPv6 extra headers */ 1934c5aff182SThomas Petazzoni if (skb_network_header_len(skb) > 0) 1935c5aff182SThomas Petazzoni ip_hdr_len = (skb_network_header_len(skb) >> 2); 1936c5aff182SThomas Petazzoni l4_proto = ip6h->nexthdr; 1937c5aff182SThomas Petazzoni } else 1938c5aff182SThomas Petazzoni return MVNETA_TX_L4_CSUM_NOT; 1939c5aff182SThomas Petazzoni 1940c5aff182SThomas Petazzoni return mvneta_txq_desc_csum(skb_network_offset(skb), 1941817dbfa5SVlad Yasevich l3_proto, ip_hdr_len, l4_proto); 1942c5aff182SThomas Petazzoni } 1943c5aff182SThomas Petazzoni 1944c5aff182SThomas Petazzoni return MVNETA_TX_L4_CSUM_NOT; 1945c5aff182SThomas Petazzoni } 1946c5aff182SThomas Petazzoni 1947c5aff182SThomas Petazzoni /* Drop packets received by the RXQ and free buffers */ 1948c5aff182SThomas Petazzoni static void mvneta_rxq_drop_pkts(struct mvneta_port *pp, 1949c5aff182SThomas Petazzoni struct mvneta_rx_queue *rxq) 1950c5aff182SThomas Petazzoni { 1951c5aff182SThomas Petazzoni int rx_done, i; 1952c5aff182SThomas Petazzoni 1953c5aff182SThomas Petazzoni rx_done = mvneta_rxq_busy_desc_num_get(pp, rxq); 1954dc35a10fSMarcin Wojtas if (rx_done) 1955dc35a10fSMarcin Wojtas mvneta_rxq_desc_num_update(pp, rxq, rx_done, rx_done); 1956dc35a10fSMarcin Wojtas 1957dc35a10fSMarcin Wojtas if (pp->bm_priv) { 1958dc35a10fSMarcin Wojtas for (i = 0; i < rx_done; i++) { 1959dc35a10fSMarcin Wojtas struct mvneta_rx_desc *rx_desc = 1960dc35a10fSMarcin Wojtas mvneta_rxq_next_desc_get(rxq); 1961dc35a10fSMarcin Wojtas u8 pool_id = MVNETA_RX_GET_BM_POOL_ID(rx_desc); 1962dc35a10fSMarcin Wojtas struct mvneta_bm_pool *bm_pool; 1963dc35a10fSMarcin Wojtas 1964dc35a10fSMarcin Wojtas bm_pool = &pp->bm_priv->bm_pools[pool_id]; 1965dc35a10fSMarcin Wojtas /* Return dropped buffer to the pool */ 1966dc35a10fSMarcin Wojtas mvneta_bm_pool_put_bp(pp->bm_priv, bm_pool, 1967dc35a10fSMarcin Wojtas rx_desc->buf_phys_addr); 1968dc35a10fSMarcin Wojtas } 1969dc35a10fSMarcin Wojtas return; 1970dc35a10fSMarcin Wojtas } 1971dc35a10fSMarcin Wojtas 1972c5aff182SThomas Petazzoni for (i = 0; i < rxq->size; i++) { 1973c5aff182SThomas Petazzoni struct mvneta_rx_desc *rx_desc = rxq->descs + i; 1974f88bee1cSGregory CLEMENT void *data = rxq->buf_virt_addr[i]; 1975562e2f46SYelena Krivosheev if (!data || !(rx_desc->buf_phys_addr)) 1976562e2f46SYelena Krivosheev continue; 1977c5aff182SThomas Petazzoni 1978458de8a9SIlias Apalodimas page_pool_put_full_page(rxq->page_pool, data, false); 1979dc35a10fSMarcin Wojtas } 1980568a3fa2SLorenzo Bianconi if (xdp_rxq_info_is_reg(&rxq->xdp_rxq)) 1981568a3fa2SLorenzo Bianconi xdp_rxq_info_unreg(&rxq->xdp_rxq); 1982568a3fa2SLorenzo Bianconi page_pool_destroy(rxq->page_pool); 1983568a3fa2SLorenzo Bianconi rxq->page_pool = NULL; 1984c5aff182SThomas Petazzoni } 1985c5aff182SThomas Petazzoni 1986ff519e2aSLorenzo Bianconi static void 1987320d5441SLorenzo Bianconi mvneta_update_stats(struct mvneta_port *pp, 1988320d5441SLorenzo Bianconi struct mvneta_stats *ps) 1989ff519e2aSLorenzo Bianconi { 1990ff519e2aSLorenzo Bianconi struct mvneta_pcpu_stats *stats = this_cpu_ptr(pp->stats); 1991ff519e2aSLorenzo Bianconi 1992ff519e2aSLorenzo Bianconi u64_stats_update_begin(&stats->syncp); 1993320d5441SLorenzo Bianconi stats->es.ps.rx_packets += ps->rx_packets; 1994320d5441SLorenzo Bianconi stats->es.ps.rx_bytes += ps->rx_bytes; 19953d866523SLorenzo Bianconi /* xdp */ 19963d866523SLorenzo Bianconi stats->es.ps.xdp_redirect += ps->xdp_redirect; 19973d866523SLorenzo Bianconi stats->es.ps.xdp_pass += ps->xdp_pass; 19983d866523SLorenzo Bianconi stats->es.ps.xdp_drop += ps->xdp_drop; 1999ff519e2aSLorenzo Bianconi u64_stats_update_end(&stats->syncp); 2000ff519e2aSLorenzo Bianconi } 2001ff519e2aSLorenzo Bianconi 2002562e2f46SYelena Krivosheev static inline 2003562e2f46SYelena Krivosheev int mvneta_rx_refill_queue(struct mvneta_port *pp, struct mvneta_rx_queue *rxq) 2004562e2f46SYelena Krivosheev { 2005562e2f46SYelena Krivosheev struct mvneta_rx_desc *rx_desc; 2006562e2f46SYelena Krivosheev int curr_desc = rxq->first_to_refill; 2007562e2f46SYelena Krivosheev int i; 2008562e2f46SYelena Krivosheev 2009562e2f46SYelena Krivosheev for (i = 0; (i < rxq->refill_num) && (i < 64); i++) { 2010562e2f46SYelena Krivosheev rx_desc = rxq->descs + curr_desc; 2011562e2f46SYelena Krivosheev if (!(rx_desc->buf_phys_addr)) { 2012562e2f46SYelena Krivosheev if (mvneta_rx_refill(pp, rx_desc, rxq, GFP_ATOMIC)) { 20139ac41f3cSLorenzo Bianconi struct mvneta_pcpu_stats *stats; 20149ac41f3cSLorenzo Bianconi 2015562e2f46SYelena Krivosheev pr_err("Can't refill queue %d. Done %d from %d\n", 2016562e2f46SYelena Krivosheev rxq->id, i, rxq->refill_num); 20179ac41f3cSLorenzo Bianconi 20189ac41f3cSLorenzo Bianconi stats = this_cpu_ptr(pp->stats); 20199ac41f3cSLorenzo Bianconi u64_stats_update_begin(&stats->syncp); 20209ac41f3cSLorenzo Bianconi stats->es.refill_error++; 20219ac41f3cSLorenzo Bianconi u64_stats_update_end(&stats->syncp); 2022562e2f46SYelena Krivosheev break; 2023562e2f46SYelena Krivosheev } 2024562e2f46SYelena Krivosheev } 2025562e2f46SYelena Krivosheev curr_desc = MVNETA_QUEUE_NEXT_DESC(rxq, curr_desc); 2026562e2f46SYelena Krivosheev } 2027562e2f46SYelena Krivosheev rxq->refill_num -= i; 2028562e2f46SYelena Krivosheev rxq->first_to_refill = curr_desc; 2029562e2f46SYelena Krivosheev 2030562e2f46SYelena Krivosheev return i; 2031562e2f46SYelena Krivosheev } 2032562e2f46SYelena Krivosheev 2033ca0e0146SLorenzo Bianconi static void 2034ca0e0146SLorenzo Bianconi mvneta_xdp_put_buff(struct mvneta_port *pp, struct mvneta_rx_queue *rxq, 2035eb33f118SLorenzo Bianconi struct xdp_buff *xdp, struct skb_shared_info *sinfo, 2036eb33f118SLorenzo Bianconi int sync_len) 2037ca0e0146SLorenzo Bianconi { 2038ca0e0146SLorenzo Bianconi int i; 2039ca0e0146SLorenzo Bianconi 2040ca0e0146SLorenzo Bianconi for (i = 0; i < sinfo->nr_frags; i++) 2041ca0e0146SLorenzo Bianconi page_pool_put_full_page(rxq->page_pool, 2042eb33f118SLorenzo Bianconi skb_frag_page(&sinfo->frags[i]), true); 20439d3b2d3eSLorenzo Bianconi page_pool_put_page(rxq->page_pool, virt_to_head_page(xdp->data), 2044eb33f118SLorenzo Bianconi sync_len, true); 2045ca0e0146SLorenzo Bianconi } 2046ca0e0146SLorenzo Bianconi 20478dc9a088SLorenzo Bianconi static int 2048b0a43db9SLorenzo Bianconi mvneta_xdp_submit_frame(struct mvneta_port *pp, struct mvneta_tx_queue *txq, 2049b0a43db9SLorenzo Bianconi struct xdp_frame *xdpf, bool dma_map) 2050b0a43db9SLorenzo Bianconi { 2051b0a43db9SLorenzo Bianconi struct mvneta_tx_desc *tx_desc; 2052b0a43db9SLorenzo Bianconi struct mvneta_tx_buf *buf; 2053b0a43db9SLorenzo Bianconi dma_addr_t dma_addr; 2054b0a43db9SLorenzo Bianconi 2055b0a43db9SLorenzo Bianconi if (txq->count >= txq->tx_stop_threshold) 2056b0a43db9SLorenzo Bianconi return MVNETA_XDP_DROPPED; 2057b0a43db9SLorenzo Bianconi 2058b0a43db9SLorenzo Bianconi tx_desc = mvneta_txq_next_desc_get(txq); 2059b0a43db9SLorenzo Bianconi 2060b0a43db9SLorenzo Bianconi buf = &txq->buf[txq->txq_put_index]; 2061b0a43db9SLorenzo Bianconi if (dma_map) { 2062b0a43db9SLorenzo Bianconi /* ndo_xdp_xmit */ 2063b0a43db9SLorenzo Bianconi dma_addr = dma_map_single(pp->dev->dev.parent, xdpf->data, 2064b0a43db9SLorenzo Bianconi xdpf->len, DMA_TO_DEVICE); 2065b0a43db9SLorenzo Bianconi if (dma_mapping_error(pp->dev->dev.parent, dma_addr)) { 2066b0a43db9SLorenzo Bianconi mvneta_txq_desc_put(txq); 2067b0a43db9SLorenzo Bianconi return MVNETA_XDP_DROPPED; 2068b0a43db9SLorenzo Bianconi } 2069b0a43db9SLorenzo Bianconi buf->type = MVNETA_TYPE_XDP_NDO; 2070b0a43db9SLorenzo Bianconi } else { 2071b0a43db9SLorenzo Bianconi struct page *page = virt_to_page(xdpf->data); 2072b0a43db9SLorenzo Bianconi 2073b0a43db9SLorenzo Bianconi dma_addr = page_pool_get_dma_addr(page) + 2074b0a43db9SLorenzo Bianconi sizeof(*xdpf) + xdpf->headroom; 2075b0a43db9SLorenzo Bianconi dma_sync_single_for_device(pp->dev->dev.parent, dma_addr, 2076b0a43db9SLorenzo Bianconi xdpf->len, DMA_BIDIRECTIONAL); 2077b0a43db9SLorenzo Bianconi buf->type = MVNETA_TYPE_XDP_TX; 2078b0a43db9SLorenzo Bianconi } 2079b0a43db9SLorenzo Bianconi buf->xdpf = xdpf; 2080b0a43db9SLorenzo Bianconi 2081b0a43db9SLorenzo Bianconi tx_desc->command = MVNETA_TXD_FLZ_DESC; 2082b0a43db9SLorenzo Bianconi tx_desc->buf_phys_addr = dma_addr; 2083b0a43db9SLorenzo Bianconi tx_desc->data_size = xdpf->len; 2084b0a43db9SLorenzo Bianconi 2085b0a43db9SLorenzo Bianconi mvneta_txq_inc_put(txq); 2086b0a43db9SLorenzo Bianconi txq->pending++; 2087b0a43db9SLorenzo Bianconi txq->count++; 2088b0a43db9SLorenzo Bianconi 2089b0a43db9SLorenzo Bianconi return MVNETA_XDP_TX; 2090b0a43db9SLorenzo Bianconi } 2091b0a43db9SLorenzo Bianconi 2092b0a43db9SLorenzo Bianconi static int 2093b0a43db9SLorenzo Bianconi mvneta_xdp_xmit_back(struct mvneta_port *pp, struct xdp_buff *xdp) 2094b0a43db9SLorenzo Bianconi { 209515070919SJesper Dangaard Brouer struct mvneta_pcpu_stats *stats = this_cpu_ptr(pp->stats); 2096b0a43db9SLorenzo Bianconi struct mvneta_tx_queue *txq; 2097b0a43db9SLorenzo Bianconi struct netdev_queue *nq; 2098b0a43db9SLorenzo Bianconi struct xdp_frame *xdpf; 2099b0a43db9SLorenzo Bianconi int cpu; 2100b0a43db9SLorenzo Bianconi u32 ret; 2101b0a43db9SLorenzo Bianconi 21021b698fa5SLorenzo Bianconi xdpf = xdp_convert_buff_to_frame(xdp); 2103b0a43db9SLorenzo Bianconi if (unlikely(!xdpf)) 2104b0a43db9SLorenzo Bianconi return MVNETA_XDP_DROPPED; 2105b0a43db9SLorenzo Bianconi 2106b0a43db9SLorenzo Bianconi cpu = smp_processor_id(); 2107b0a43db9SLorenzo Bianconi txq = &pp->txqs[cpu % txq_number]; 2108b0a43db9SLorenzo Bianconi nq = netdev_get_tx_queue(pp->dev, txq->id); 2109b0a43db9SLorenzo Bianconi 2110b0a43db9SLorenzo Bianconi __netif_tx_lock(nq, cpu); 2111b0a43db9SLorenzo Bianconi ret = mvneta_xdp_submit_frame(pp, txq, xdpf, false); 21127d51a015SLorenzo Bianconi if (ret == MVNETA_XDP_TX) { 21137d51a015SLorenzo Bianconi u64_stats_update_begin(&stats->syncp); 21147d51a015SLorenzo Bianconi stats->es.ps.tx_bytes += xdpf->len; 21157d51a015SLorenzo Bianconi stats->es.ps.tx_packets++; 21167d51a015SLorenzo Bianconi stats->es.ps.xdp_tx++; 21177d51a015SLorenzo Bianconi u64_stats_update_end(&stats->syncp); 21187d51a015SLorenzo Bianconi 2119b0a43db9SLorenzo Bianconi mvneta_txq_pend_desc_add(pp, txq, 0); 212015070919SJesper Dangaard Brouer } else { 212115070919SJesper Dangaard Brouer u64_stats_update_begin(&stats->syncp); 212215070919SJesper Dangaard Brouer stats->es.ps.xdp_tx_err++; 212315070919SJesper Dangaard Brouer u64_stats_update_end(&stats->syncp); 21247d51a015SLorenzo Bianconi } 2125b0a43db9SLorenzo Bianconi __netif_tx_unlock(nq); 2126b0a43db9SLorenzo Bianconi 2127b0a43db9SLorenzo Bianconi return ret; 2128b0a43db9SLorenzo Bianconi } 2129b0a43db9SLorenzo Bianconi 2130b0a43db9SLorenzo Bianconi static int 2131b0a43db9SLorenzo Bianconi mvneta_xdp_xmit(struct net_device *dev, int num_frame, 2132b0a43db9SLorenzo Bianconi struct xdp_frame **frames, u32 flags) 2133b0a43db9SLorenzo Bianconi { 2134b0a43db9SLorenzo Bianconi struct mvneta_port *pp = netdev_priv(dev); 21357d51a015SLorenzo Bianconi struct mvneta_pcpu_stats *stats = this_cpu_ptr(pp->stats); 2136fdc13979SLorenzo Bianconi int i, nxmit_byte = 0, nxmit = 0; 2137b0a43db9SLorenzo Bianconi int cpu = smp_processor_id(); 2138b0a43db9SLorenzo Bianconi struct mvneta_tx_queue *txq; 2139b0a43db9SLorenzo Bianconi struct netdev_queue *nq; 2140b0a43db9SLorenzo Bianconi u32 ret; 2141b0a43db9SLorenzo Bianconi 214262a502ccSLorenzo Bianconi if (unlikely(test_bit(__MVNETA_DOWN, &pp->state))) 214362a502ccSLorenzo Bianconi return -ENETDOWN; 214462a502ccSLorenzo Bianconi 2145b0a43db9SLorenzo Bianconi if (unlikely(flags & ~XDP_XMIT_FLAGS_MASK)) 2146b0a43db9SLorenzo Bianconi return -EINVAL; 2147b0a43db9SLorenzo Bianconi 2148b0a43db9SLorenzo Bianconi txq = &pp->txqs[cpu % txq_number]; 2149b0a43db9SLorenzo Bianconi nq = netdev_get_tx_queue(pp->dev, txq->id); 2150b0a43db9SLorenzo Bianconi 2151b0a43db9SLorenzo Bianconi __netif_tx_lock(nq, cpu); 2152b0a43db9SLorenzo Bianconi for (i = 0; i < num_frame; i++) { 2153b0a43db9SLorenzo Bianconi ret = mvneta_xdp_submit_frame(pp, txq, frames[i], true); 2154fdc13979SLorenzo Bianconi if (ret != MVNETA_XDP_TX) 2155fdc13979SLorenzo Bianconi break; 2156fdc13979SLorenzo Bianconi 21577d51a015SLorenzo Bianconi nxmit_byte += frames[i]->len; 2158fdc13979SLorenzo Bianconi nxmit++; 2159b0a43db9SLorenzo Bianconi } 2160b0a43db9SLorenzo Bianconi 2161b0a43db9SLorenzo Bianconi if (unlikely(flags & XDP_XMIT_FLUSH)) 2162b0a43db9SLorenzo Bianconi mvneta_txq_pend_desc_add(pp, txq, 0); 2163b0a43db9SLorenzo Bianconi __netif_tx_unlock(nq); 2164b0a43db9SLorenzo Bianconi 21657d51a015SLorenzo Bianconi u64_stats_update_begin(&stats->syncp); 21667d51a015SLorenzo Bianconi stats->es.ps.tx_bytes += nxmit_byte; 21677d51a015SLorenzo Bianconi stats->es.ps.tx_packets += nxmit; 21687d51a015SLorenzo Bianconi stats->es.ps.xdp_xmit += nxmit; 216915070919SJesper Dangaard Brouer stats->es.ps.xdp_xmit_err += num_frame - nxmit; 21707d51a015SLorenzo Bianconi u64_stats_update_end(&stats->syncp); 21717d51a015SLorenzo Bianconi 21727d51a015SLorenzo Bianconi return nxmit; 2173b0a43db9SLorenzo Bianconi } 2174b0a43db9SLorenzo Bianconi 2175b0a43db9SLorenzo Bianconi static int 21760db51da7SLorenzo Bianconi mvneta_run_xdp(struct mvneta_port *pp, struct mvneta_rx_queue *rxq, 2177320d5441SLorenzo Bianconi struct bpf_prog *prog, struct xdp_buff *xdp, 21787d1643ebSLorenzo Bianconi u32 frame_sz, struct mvneta_stats *stats) 21790db51da7SLorenzo Bianconi { 2180eb33f118SLorenzo Bianconi struct skb_shared_info *sinfo = xdp_get_shared_info_from_buff(xdp); 21817d1643ebSLorenzo Bianconi unsigned int len, data_len, sync; 21828c4df83fSLorenzo Bianconi u32 ret, act; 21838c4df83fSLorenzo Bianconi 21848c4df83fSLorenzo Bianconi len = xdp->data_end - xdp->data_hard_start - pp->rx_offset_correction; 21857d1643ebSLorenzo Bianconi data_len = xdp->data_end - xdp->data; 21868c4df83fSLorenzo Bianconi act = bpf_prog_run_xdp(prog, xdp); 21870db51da7SLorenzo Bianconi 2188494f44d5SJesper Dangaard Brouer /* Due xdp_adjust_tail: DMA sync for_device cover max len CPU touch */ 2189494f44d5SJesper Dangaard Brouer sync = xdp->data_end - xdp->data_hard_start - pp->rx_offset_correction; 2190494f44d5SJesper Dangaard Brouer sync = max(sync, len); 2191494f44d5SJesper Dangaard Brouer 21920db51da7SLorenzo Bianconi switch (act) { 21930db51da7SLorenzo Bianconi case XDP_PASS: 21943d866523SLorenzo Bianconi stats->xdp_pass++; 2195320d5441SLorenzo Bianconi return MVNETA_XDP_PASS; 21960db51da7SLorenzo Bianconi case XDP_REDIRECT: { 21970db51da7SLorenzo Bianconi int err; 21980db51da7SLorenzo Bianconi 21990db51da7SLorenzo Bianconi err = xdp_do_redirect(pp->dev, xdp, prog); 220015070919SJesper Dangaard Brouer if (unlikely(err)) { 2201eb33f118SLorenzo Bianconi mvneta_xdp_put_buff(pp, rxq, xdp, sinfo, sync); 22020db51da7SLorenzo Bianconi ret = MVNETA_XDP_DROPPED; 22030db51da7SLorenzo Bianconi } else { 22040db51da7SLorenzo Bianconi ret = MVNETA_XDP_REDIR; 22053d866523SLorenzo Bianconi stats->xdp_redirect++; 22060db51da7SLorenzo Bianconi } 22070db51da7SLorenzo Bianconi break; 22080db51da7SLorenzo Bianconi } 2209b0a43db9SLorenzo Bianconi case XDP_TX: 2210b0a43db9SLorenzo Bianconi ret = mvneta_xdp_xmit_back(pp, xdp); 22117d1643ebSLorenzo Bianconi if (ret != MVNETA_XDP_TX) 2212eb33f118SLorenzo Bianconi mvneta_xdp_put_buff(pp, rxq, xdp, sinfo, sync); 2213b0a43db9SLorenzo Bianconi break; 22140db51da7SLorenzo Bianconi default: 22150db51da7SLorenzo Bianconi bpf_warn_invalid_xdp_action(act); 2216df561f66SGustavo A. R. Silva fallthrough; 22170db51da7SLorenzo Bianconi case XDP_ABORTED: 22180db51da7SLorenzo Bianconi trace_xdp_exception(pp->dev, prog, act); 2219df561f66SGustavo A. R. Silva fallthrough; 22200db51da7SLorenzo Bianconi case XDP_DROP: 2221eb33f118SLorenzo Bianconi mvneta_xdp_put_buff(pp, rxq, xdp, sinfo, sync); 22220db51da7SLorenzo Bianconi ret = MVNETA_XDP_DROPPED; 22233d866523SLorenzo Bianconi stats->xdp_drop++; 22240db51da7SLorenzo Bianconi break; 22250db51da7SLorenzo Bianconi } 22260db51da7SLorenzo Bianconi 22277d1643ebSLorenzo Bianconi stats->rx_bytes += frame_sz + xdp->data_end - xdp->data - data_len; 2228320d5441SLorenzo Bianconi stats->rx_packets++; 2229320d5441SLorenzo Bianconi 22300db51da7SLorenzo Bianconi return ret; 22310db51da7SLorenzo Bianconi } 22320db51da7SLorenzo Bianconi 2233afda408bSLorenzo Bianconi static void 22348dc9a088SLorenzo Bianconi mvneta_swbm_rx_frame(struct mvneta_port *pp, 22358dc9a088SLorenzo Bianconi struct mvneta_rx_desc *rx_desc, 22368dc9a088SLorenzo Bianconi struct mvneta_rx_queue *rxq, 2237c7a3a8cdSLorenzo Bianconi struct xdp_buff *xdp, int *size, 22383a8c4ad1SLorenzo Bianconi struct page *page) 22398dc9a088SLorenzo Bianconi { 22408dc9a088SLorenzo Bianconi unsigned char *data = page_address(page); 22418dc9a088SLorenzo Bianconi int data_len = -MVNETA_MH_SIZE, len; 22428dc9a088SLorenzo Bianconi struct net_device *dev = pp->dev; 22438dc9a088SLorenzo Bianconi enum dma_data_direction dma_dir; 2244ca0e0146SLorenzo Bianconi struct skb_shared_info *sinfo; 22458dc9a088SLorenzo Bianconi 2246879456beSLorenzo Bianconi if (*size > MVNETA_MAX_RX_BUF_SIZE) { 22478dc9a088SLorenzo Bianconi len = MVNETA_MAX_RX_BUF_SIZE; 22488dc9a088SLorenzo Bianconi data_len += len; 22498dc9a088SLorenzo Bianconi } else { 2250879456beSLorenzo Bianconi len = *size; 22518dc9a088SLorenzo Bianconi data_len += len - ETH_FCS_LEN; 22528dc9a088SLorenzo Bianconi } 2253879456beSLorenzo Bianconi *size = *size - len; 22548dc9a088SLorenzo Bianconi 22558dc9a088SLorenzo Bianconi dma_dir = page_pool_get_dma_dir(rxq->page_pool); 22568dc9a088SLorenzo Bianconi dma_sync_single_for_cpu(dev->dev.parent, 22578dc9a088SLorenzo Bianconi rx_desc->buf_phys_addr, 22588dc9a088SLorenzo Bianconi len, dma_dir); 22598dc9a088SLorenzo Bianconi 2260879456beSLorenzo Bianconi rx_desc->buf_phys_addr = 0; 2261879456beSLorenzo Bianconi 2262fa383f6bSLorenzo Bianconi /* Prefetch header */ 2263fa383f6bSLorenzo Bianconi prefetch(data); 2264be9df4afSLorenzo Bianconi xdp_prepare_buff(xdp, data, pp->rx_offset_correction + MVNETA_MH_SIZE, 2265be9df4afSLorenzo Bianconi data_len, false); 22660db51da7SLorenzo Bianconi 2267ca0e0146SLorenzo Bianconi sinfo = xdp_get_shared_info_from_buff(xdp); 2268ca0e0146SLorenzo Bianconi sinfo->nr_frags = 0; 22698dc9a088SLorenzo Bianconi } 22708dc9a088SLorenzo Bianconi 22718dc9a088SLorenzo Bianconi static void 22728dc9a088SLorenzo Bianconi mvneta_swbm_add_rx_fragment(struct mvneta_port *pp, 22738dc9a088SLorenzo Bianconi struct mvneta_rx_desc *rx_desc, 22748dc9a088SLorenzo Bianconi struct mvneta_rx_queue *rxq, 2275c7a3a8cdSLorenzo Bianconi struct xdp_buff *xdp, int *size, 2276039fbc47SLorenzo Bianconi struct skb_shared_info *xdp_sinfo, 22778dc9a088SLorenzo Bianconi struct page *page) 22788dc9a088SLorenzo Bianconi { 22798dc9a088SLorenzo Bianconi struct net_device *dev = pp->dev; 22808dc9a088SLorenzo Bianconi enum dma_data_direction dma_dir; 22818dc9a088SLorenzo Bianconi int data_len, len; 22828dc9a088SLorenzo Bianconi 2283c7a3a8cdSLorenzo Bianconi if (*size > MVNETA_MAX_RX_BUF_SIZE) { 22848dc9a088SLorenzo Bianconi len = MVNETA_MAX_RX_BUF_SIZE; 22858dc9a088SLorenzo Bianconi data_len = len; 22868dc9a088SLorenzo Bianconi } else { 2287c7a3a8cdSLorenzo Bianconi len = *size; 22888dc9a088SLorenzo Bianconi data_len = len - ETH_FCS_LEN; 22898dc9a088SLorenzo Bianconi } 22908dc9a088SLorenzo Bianconi dma_dir = page_pool_get_dma_dir(rxq->page_pool); 22918dc9a088SLorenzo Bianconi dma_sync_single_for_cpu(dev->dev.parent, 22928dc9a088SLorenzo Bianconi rx_desc->buf_phys_addr, 22938dc9a088SLorenzo Bianconi len, dma_dir); 22949c79a8abSLorenzo Bianconi rx_desc->buf_phys_addr = 0; 2295ca0e0146SLorenzo Bianconi 2296039fbc47SLorenzo Bianconi if (data_len > 0 && xdp_sinfo->nr_frags < MAX_SKB_FRAGS) { 2297039fbc47SLorenzo Bianconi skb_frag_t *frag = &xdp_sinfo->frags[xdp_sinfo->nr_frags++]; 2298ca0e0146SLorenzo Bianconi 2299ca0e0146SLorenzo Bianconi skb_frag_off_set(frag, pp->rx_offset_correction); 2300ca0e0146SLorenzo Bianconi skb_frag_size_set(frag, data_len); 2301ca0e0146SLorenzo Bianconi __skb_frag_set_page(frag, page); 23026ff63a15SLorenzo Bianconi } else { 23036ff63a15SLorenzo Bianconi page_pool_put_full_page(rxq->page_pool, page, true); 23046ff63a15SLorenzo Bianconi } 2305039fbc47SLorenzo Bianconi 2306039fbc47SLorenzo Bianconi /* last fragment */ 2307039fbc47SLorenzo Bianconi if (len == *size) { 2308039fbc47SLorenzo Bianconi struct skb_shared_info *sinfo; 2309039fbc47SLorenzo Bianconi 2310039fbc47SLorenzo Bianconi sinfo = xdp_get_shared_info_from_buff(xdp); 2311039fbc47SLorenzo Bianconi sinfo->nr_frags = xdp_sinfo->nr_frags; 2312039fbc47SLorenzo Bianconi memcpy(sinfo->frags, xdp_sinfo->frags, 2313039fbc47SLorenzo Bianconi sinfo->nr_frags * sizeof(skb_frag_t)); 2314039fbc47SLorenzo Bianconi } 2315c7a3a8cdSLorenzo Bianconi *size -= len; 23168dc9a088SLorenzo Bianconi } 23178dc9a088SLorenzo Bianconi 2318ca0e0146SLorenzo Bianconi static struct sk_buff * 2319e4017570SMatteo Croce mvneta_swbm_build_skb(struct mvneta_port *pp, struct page_pool *pool, 2320ca0e0146SLorenzo Bianconi struct xdp_buff *xdp, u32 desc_status) 2321ca0e0146SLorenzo Bianconi { 2322ca0e0146SLorenzo Bianconi struct skb_shared_info *sinfo = xdp_get_shared_info_from_buff(xdp); 2323ca0e0146SLorenzo Bianconi int i, num_frags = sinfo->nr_frags; 2324ca0e0146SLorenzo Bianconi struct sk_buff *skb; 2325ca0e0146SLorenzo Bianconi 2326ca0e0146SLorenzo Bianconi skb = build_skb(xdp->data_hard_start, PAGE_SIZE); 2327ca0e0146SLorenzo Bianconi if (!skb) 2328ca0e0146SLorenzo Bianconi return ERR_PTR(-ENOMEM); 2329ca0e0146SLorenzo Bianconi 233057f05bc2SYunsheng Lin skb_mark_for_recycle(skb); 2331ca0e0146SLorenzo Bianconi 2332ca0e0146SLorenzo Bianconi skb_reserve(skb, xdp->data - xdp->data_hard_start); 2333ca0e0146SLorenzo Bianconi skb_put(skb, xdp->data_end - xdp->data); 2334aff0824dSLorenzo Bianconi skb->ip_summed = mvneta_rx_csum(pp, desc_status); 2335ca0e0146SLorenzo Bianconi 2336ca0e0146SLorenzo Bianconi for (i = 0; i < num_frags; i++) { 233752731441SLorenzo Bianconi skb_frag_t *frag = &sinfo->frags[i]; 2338ca0e0146SLorenzo Bianconi 2339ca0e0146SLorenzo Bianconi skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, 234052731441SLorenzo Bianconi skb_frag_page(frag), skb_frag_off(frag), 234152731441SLorenzo Bianconi skb_frag_size(frag), PAGE_SIZE); 2342ca0e0146SLorenzo Bianconi } 2343ca0e0146SLorenzo Bianconi 2344ca0e0146SLorenzo Bianconi return skb; 2345ca0e0146SLorenzo Bianconi } 2346ca0e0146SLorenzo Bianconi 2347dc35a10fSMarcin Wojtas /* Main rx processing when using software buffer management */ 23487a86f05fSAndrew Lunn static int mvneta_rx_swbm(struct napi_struct *napi, 2349562e2f46SYelena Krivosheev struct mvneta_port *pp, int budget, 2350c5aff182SThomas Petazzoni struct mvneta_rx_queue *rxq) 2351c5aff182SThomas Petazzoni { 2352c7a3a8cdSLorenzo Bianconi int rx_proc = 0, rx_todo, refill, size = 0; 2353c5aff182SThomas Petazzoni struct net_device *dev = pp->dev; 2354039fbc47SLorenzo Bianconi struct skb_shared_info sinfo; 2355320d5441SLorenzo Bianconi struct mvneta_stats ps = {}; 23560db51da7SLorenzo Bianconi struct bpf_prog *xdp_prog; 23577d1643ebSLorenzo Bianconi u32 desc_status, frame_sz; 235805c748f7SLorenzo Bianconi struct xdp_buff xdp_buf; 235905c748f7SLorenzo Bianconi 236043b5169dSLorenzo Bianconi xdp_init_buff(&xdp_buf, PAGE_SIZE, &rxq->xdp_rxq); 236105c748f7SLorenzo Bianconi xdp_buf.data_hard_start = NULL; 2362c5aff182SThomas Petazzoni 2363039fbc47SLorenzo Bianconi sinfo.nr_frags = 0; 2364039fbc47SLorenzo Bianconi 2365c5aff182SThomas Petazzoni /* Get number of received packets */ 2366562e2f46SYelena Krivosheev rx_todo = mvneta_rxq_busy_desc_num_get(pp, rxq); 2367c5aff182SThomas Petazzoni 23680db51da7SLorenzo Bianconi xdp_prog = READ_ONCE(pp->xdp_prog); 23690db51da7SLorenzo Bianconi 2370c5aff182SThomas Petazzoni /* Fairness NAPI loop */ 23718dc9a088SLorenzo Bianconi while (rx_proc < budget && rx_proc < rx_todo) { 2372c5aff182SThomas Petazzoni struct mvneta_rx_desc *rx_desc = mvneta_rxq_next_desc_get(rxq); 23738dc9a088SLorenzo Bianconi u32 rx_status, index; 2374ca0e0146SLorenzo Bianconi struct sk_buff *skb; 23757e47fd84SGregory CLEMENT struct page *page; 2376c5aff182SThomas Petazzoni 2377f88bee1cSGregory CLEMENT index = rx_desc - rxq->descs; 23787e47fd84SGregory CLEMENT page = (struct page *)rxq->buf_virt_addr[index]; 2379c5aff182SThomas Petazzoni 2380562e2f46SYelena Krivosheev rx_status = rx_desc->status; 2381562e2f46SYelena Krivosheev rx_proc++; 2382562e2f46SYelena Krivosheev rxq->refill_num++; 2383562e2f46SYelena Krivosheev 2384562e2f46SYelena Krivosheev if (rx_status & MVNETA_RXD_FIRST_DESC) { 2385562e2f46SYelena Krivosheev /* Check errors only for FIRST descriptor */ 2386562e2f46SYelena Krivosheev if (rx_status & MVNETA_RXD_ERR_SUMMARY) { 23872eecb2e0SYelena Krivosheev mvneta_rx_error(pp, rx_desc); 2388ca0e0146SLorenzo Bianconi goto next; 2389c5aff182SThomas Petazzoni } 2390c5aff182SThomas Petazzoni 2391c7a3a8cdSLorenzo Bianconi size = rx_desc->data_size; 2392c7a3a8cdSLorenzo Bianconi frame_sz = size - ETH_FCS_LEN; 2393879456beSLorenzo Bianconi desc_status = rx_status; 23947d1643ebSLorenzo Bianconi 2395c7a3a8cdSLorenzo Bianconi mvneta_swbm_rx_frame(pp, rx_desc, rxq, &xdp_buf, 23963a8c4ad1SLorenzo Bianconi &size, page); 2397562e2f46SYelena Krivosheev } else { 2398b6e11785SLorenzo Bianconi if (unlikely(!xdp_buf.data_hard_start)) { 2399b6e11785SLorenzo Bianconi rx_desc->buf_phys_addr = 0; 2400b6e11785SLorenzo Bianconi page_pool_put_full_page(rxq->page_pool, page, 2401b6e11785SLorenzo Bianconi true); 2402039fbc47SLorenzo Bianconi goto next; 2403b6e11785SLorenzo Bianconi } 2404ca0e0146SLorenzo Bianconi 2405ca0e0146SLorenzo Bianconi mvneta_swbm_add_rx_fragment(pp, rx_desc, rxq, &xdp_buf, 2406039fbc47SLorenzo Bianconi &size, &sinfo, page); 2407562e2f46SYelena Krivosheev } /* Middle or Last descriptor */ 2408562e2f46SYelena Krivosheev 2409562e2f46SYelena Krivosheev if (!(rx_status & MVNETA_RXD_LAST_DESC)) 2410562e2f46SYelena Krivosheev /* no last descriptor this time */ 2411562e2f46SYelena Krivosheev continue; 2412562e2f46SYelena Krivosheev 2413c7a3a8cdSLorenzo Bianconi if (size) { 2414039fbc47SLorenzo Bianconi mvneta_xdp_put_buff(pp, rxq, &xdp_buf, &sinfo, -1); 2415ca0e0146SLorenzo Bianconi goto next; 2416562e2f46SYelena Krivosheev } 2417320d5441SLorenzo Bianconi 2418afda408bSLorenzo Bianconi if (xdp_prog && 24197d1643ebSLorenzo Bianconi mvneta_run_xdp(pp, rxq, xdp_prog, &xdp_buf, frame_sz, &ps)) 2420afda408bSLorenzo Bianconi goto next; 2421afda408bSLorenzo Bianconi 2422e4017570SMatteo Croce skb = mvneta_swbm_build_skb(pp, rxq->page_pool, &xdp_buf, desc_status); 2423ca0e0146SLorenzo Bianconi if (IS_ERR(skb)) { 2424ca0e0146SLorenzo Bianconi struct mvneta_pcpu_stats *stats = this_cpu_ptr(pp->stats); 2425ca0e0146SLorenzo Bianconi 2426039fbc47SLorenzo Bianconi mvneta_xdp_put_buff(pp, rxq, &xdp_buf, &sinfo, -1); 2427ca0e0146SLorenzo Bianconi 2428ca0e0146SLorenzo Bianconi u64_stats_update_begin(&stats->syncp); 2429ca0e0146SLorenzo Bianconi stats->es.skb_alloc_error++; 2430ca0e0146SLorenzo Bianconi stats->rx_dropped++; 2431ca0e0146SLorenzo Bianconi u64_stats_update_end(&stats->syncp); 2432ca0e0146SLorenzo Bianconi 2433ca0e0146SLorenzo Bianconi goto next; 2434ca0e0146SLorenzo Bianconi } 2435ca0e0146SLorenzo Bianconi 2436ca0e0146SLorenzo Bianconi ps.rx_bytes += skb->len; 2437320d5441SLorenzo Bianconi ps.rx_packets++; 2438c5aff182SThomas Petazzoni 2439ca0e0146SLorenzo Bianconi skb->protocol = eth_type_trans(skb, dev); 2440ca0e0146SLorenzo Bianconi napi_gro_receive(napi, skb); 2441ca0e0146SLorenzo Bianconi next: 2442ca0e0146SLorenzo Bianconi xdp_buf.data_hard_start = NULL; 2443039fbc47SLorenzo Bianconi sinfo.nr_frags = 0; 2444c5aff182SThomas Petazzoni } 24450db51da7SLorenzo Bianconi 2446039fbc47SLorenzo Bianconi if (xdp_buf.data_hard_start) 2447039fbc47SLorenzo Bianconi mvneta_xdp_put_buff(pp, rxq, &xdp_buf, &sinfo, -1); 2448ca0e0146SLorenzo Bianconi 24496c8a8cfdSLorenzo Bianconi if (ps.xdp_redirect) 24500db51da7SLorenzo Bianconi xdp_do_flush_map(); 2451c5aff182SThomas Petazzoni 2452320d5441SLorenzo Bianconi if (ps.rx_packets) 2453320d5441SLorenzo Bianconi mvneta_update_stats(pp, &ps); 2454dc4277ddSwilly tarreau 2455562e2f46SYelena Krivosheev /* return some buffers to hardware queue, one at a time is too slow */ 2456562e2f46SYelena Krivosheev refill = mvneta_rx_refill_queue(pp, rxq); 2457c5aff182SThomas Petazzoni 2458562e2f46SYelena Krivosheev /* Update rxq management counters */ 2459562e2f46SYelena Krivosheev mvneta_rxq_desc_num_update(pp, rxq, rx_proc, refill); 2460562e2f46SYelena Krivosheev 2461320d5441SLorenzo Bianconi return ps.rx_packets; 2462c5aff182SThomas Petazzoni } 2463c5aff182SThomas Petazzoni 2464dc35a10fSMarcin Wojtas /* Main rx processing when using hardware buffer management */ 24657a86f05fSAndrew Lunn static int mvneta_rx_hwbm(struct napi_struct *napi, 24667a86f05fSAndrew Lunn struct mvneta_port *pp, int rx_todo, 2467dc35a10fSMarcin Wojtas struct mvneta_rx_queue *rxq) 2468dc35a10fSMarcin Wojtas { 2469dc35a10fSMarcin Wojtas struct net_device *dev = pp->dev; 2470dc35a10fSMarcin Wojtas int rx_done; 2471dc35a10fSMarcin Wojtas u32 rcvd_pkts = 0; 2472dc35a10fSMarcin Wojtas u32 rcvd_bytes = 0; 2473dc35a10fSMarcin Wojtas 2474dc35a10fSMarcin Wojtas /* Get number of received packets */ 2475dc35a10fSMarcin Wojtas rx_done = mvneta_rxq_busy_desc_num_get(pp, rxq); 2476dc35a10fSMarcin Wojtas 2477dc35a10fSMarcin Wojtas if (rx_todo > rx_done) 2478dc35a10fSMarcin Wojtas rx_todo = rx_done; 2479dc35a10fSMarcin Wojtas 2480dc35a10fSMarcin Wojtas rx_done = 0; 2481dc35a10fSMarcin Wojtas 2482dc35a10fSMarcin Wojtas /* Fairness NAPI loop */ 2483dc35a10fSMarcin Wojtas while (rx_done < rx_todo) { 2484dc35a10fSMarcin Wojtas struct mvneta_rx_desc *rx_desc = mvneta_rxq_next_desc_get(rxq); 2485dc35a10fSMarcin Wojtas struct mvneta_bm_pool *bm_pool = NULL; 2486dc35a10fSMarcin Wojtas struct sk_buff *skb; 2487dc35a10fSMarcin Wojtas unsigned char *data; 2488dc35a10fSMarcin Wojtas dma_addr_t phys_addr; 2489dc35a10fSMarcin Wojtas u32 rx_status, frag_size; 2490dc35a10fSMarcin Wojtas int rx_bytes, err; 2491dc35a10fSMarcin Wojtas u8 pool_id; 2492dc35a10fSMarcin Wojtas 2493dc35a10fSMarcin Wojtas rx_done++; 2494dc35a10fSMarcin Wojtas rx_status = rx_desc->status; 2495dc35a10fSMarcin Wojtas rx_bytes = rx_desc->data_size - (ETH_FCS_LEN + MVNETA_MH_SIZE); 2496f88bee1cSGregory CLEMENT data = (u8 *)(uintptr_t)rx_desc->buf_cookie; 2497dc35a10fSMarcin Wojtas phys_addr = rx_desc->buf_phys_addr; 2498dc35a10fSMarcin Wojtas pool_id = MVNETA_RX_GET_BM_POOL_ID(rx_desc); 2499dc35a10fSMarcin Wojtas bm_pool = &pp->bm_priv->bm_pools[pool_id]; 2500dc35a10fSMarcin Wojtas 2501dc35a10fSMarcin Wojtas if (!mvneta_rxq_desc_is_first_last(rx_status) || 2502dc35a10fSMarcin Wojtas (rx_status & MVNETA_RXD_ERR_SUMMARY)) { 2503dc35a10fSMarcin Wojtas err_drop_frame_ret_pool: 2504dc35a10fSMarcin Wojtas /* Return the buffer to the pool */ 2505dc35a10fSMarcin Wojtas mvneta_bm_pool_put_bp(pp->bm_priv, bm_pool, 2506dc35a10fSMarcin Wojtas rx_desc->buf_phys_addr); 2507dc35a10fSMarcin Wojtas err_drop_frame: 2508dc35a10fSMarcin Wojtas mvneta_rx_error(pp, rx_desc); 2509dc35a10fSMarcin Wojtas /* leave the descriptor untouched */ 2510dc35a10fSMarcin Wojtas continue; 2511dc35a10fSMarcin Wojtas } 2512dc35a10fSMarcin Wojtas 2513dc35a10fSMarcin Wojtas if (rx_bytes <= rx_copybreak) { 2514dc35a10fSMarcin Wojtas /* better copy a small frame and not unmap the DMA region */ 2515dc35a10fSMarcin Wojtas skb = netdev_alloc_skb_ip_align(dev, rx_bytes); 2516dc35a10fSMarcin Wojtas if (unlikely(!skb)) 2517dc35a10fSMarcin Wojtas goto err_drop_frame_ret_pool; 2518dc35a10fSMarcin Wojtas 2519a8fef9baSRussell King dma_sync_single_range_for_cpu(&pp->bm_priv->pdev->dev, 2520dc35a10fSMarcin Wojtas rx_desc->buf_phys_addr, 2521dc35a10fSMarcin Wojtas MVNETA_MH_SIZE + NET_SKB_PAD, 2522dc35a10fSMarcin Wojtas rx_bytes, 2523dc35a10fSMarcin Wojtas DMA_FROM_DEVICE); 252459ae1d12SJohannes Berg skb_put_data(skb, data + MVNETA_MH_SIZE + NET_SKB_PAD, 2525dc35a10fSMarcin Wojtas rx_bytes); 2526dc35a10fSMarcin Wojtas 2527dc35a10fSMarcin Wojtas skb->protocol = eth_type_trans(skb, dev); 2528aff0824dSLorenzo Bianconi skb->ip_summed = mvneta_rx_csum(pp, rx_status); 25297a86f05fSAndrew Lunn napi_gro_receive(napi, skb); 2530dc35a10fSMarcin Wojtas 2531dc35a10fSMarcin Wojtas rcvd_pkts++; 2532dc35a10fSMarcin Wojtas rcvd_bytes += rx_bytes; 2533dc35a10fSMarcin Wojtas 2534dc35a10fSMarcin Wojtas /* Return the buffer to the pool */ 2535dc35a10fSMarcin Wojtas mvneta_bm_pool_put_bp(pp->bm_priv, bm_pool, 2536dc35a10fSMarcin Wojtas rx_desc->buf_phys_addr); 2537dc35a10fSMarcin Wojtas 2538dc35a10fSMarcin Wojtas /* leave the descriptor and buffer untouched */ 2539dc35a10fSMarcin Wojtas continue; 2540dc35a10fSMarcin Wojtas } 2541dc35a10fSMarcin Wojtas 2542dc35a10fSMarcin Wojtas /* Refill processing */ 2543baa11ebcSGregory CLEMENT err = hwbm_pool_refill(&bm_pool->hwbm_pool, GFP_ATOMIC); 2544dc35a10fSMarcin Wojtas if (err) { 25459ac41f3cSLorenzo Bianconi struct mvneta_pcpu_stats *stats; 25469ac41f3cSLorenzo Bianconi 2547dc35a10fSMarcin Wojtas netdev_err(dev, "Linux processing - Can't refill\n"); 25489ac41f3cSLorenzo Bianconi 25499ac41f3cSLorenzo Bianconi stats = this_cpu_ptr(pp->stats); 25509ac41f3cSLorenzo Bianconi u64_stats_update_begin(&stats->syncp); 25519ac41f3cSLorenzo Bianconi stats->es.refill_error++; 25529ac41f3cSLorenzo Bianconi u64_stats_update_end(&stats->syncp); 25539ac41f3cSLorenzo Bianconi 2554dc35a10fSMarcin Wojtas goto err_drop_frame_ret_pool; 2555dc35a10fSMarcin Wojtas } 2556dc35a10fSMarcin Wojtas 2557baa11ebcSGregory CLEMENT frag_size = bm_pool->hwbm_pool.frag_size; 2558dc35a10fSMarcin Wojtas 2559dc35a10fSMarcin Wojtas skb = build_skb(data, frag_size > PAGE_SIZE ? 0 : frag_size); 2560dc35a10fSMarcin Wojtas 2561dc35a10fSMarcin Wojtas /* After refill old buffer has to be unmapped regardless 2562dc35a10fSMarcin Wojtas * the skb is successfully built or not. 2563dc35a10fSMarcin Wojtas */ 2564dc35a10fSMarcin Wojtas dma_unmap_single(&pp->bm_priv->pdev->dev, phys_addr, 2565dc35a10fSMarcin Wojtas bm_pool->buf_size, DMA_FROM_DEVICE); 2566dc35a10fSMarcin Wojtas if (!skb) 2567dc35a10fSMarcin Wojtas goto err_drop_frame; 2568dc35a10fSMarcin Wojtas 2569dc35a10fSMarcin Wojtas rcvd_pkts++; 2570dc35a10fSMarcin Wojtas rcvd_bytes += rx_bytes; 2571dc35a10fSMarcin Wojtas 2572dc35a10fSMarcin Wojtas /* Linux processing */ 2573dc35a10fSMarcin Wojtas skb_reserve(skb, MVNETA_MH_SIZE + NET_SKB_PAD); 2574dc35a10fSMarcin Wojtas skb_put(skb, rx_bytes); 2575dc35a10fSMarcin Wojtas 2576dc35a10fSMarcin Wojtas skb->protocol = eth_type_trans(skb, dev); 2577aff0824dSLorenzo Bianconi skb->ip_summed = mvneta_rx_csum(pp, rx_status); 2578dc35a10fSMarcin Wojtas 25797a86f05fSAndrew Lunn napi_gro_receive(napi, skb); 2580dc35a10fSMarcin Wojtas } 2581dc35a10fSMarcin Wojtas 258269de66fcSLorenzo Bianconi if (rcvd_pkts) { 258369de66fcSLorenzo Bianconi struct mvneta_pcpu_stats *stats = this_cpu_ptr(pp->stats); 258469de66fcSLorenzo Bianconi 258569de66fcSLorenzo Bianconi u64_stats_update_begin(&stats->syncp); 2586320d5441SLorenzo Bianconi stats->es.ps.rx_packets += rcvd_pkts; 2587320d5441SLorenzo Bianconi stats->es.ps.rx_bytes += rcvd_bytes; 258869de66fcSLorenzo Bianconi u64_stats_update_end(&stats->syncp); 258969de66fcSLorenzo Bianconi } 2590dc35a10fSMarcin Wojtas 2591dc35a10fSMarcin Wojtas /* Update rxq management counters */ 2592dc35a10fSMarcin Wojtas mvneta_rxq_desc_num_update(pp, rxq, rx_done, rx_done); 2593dc35a10fSMarcin Wojtas 2594dc35a10fSMarcin Wojtas return rx_done; 2595dc35a10fSMarcin Wojtas } 2596dc35a10fSMarcin Wojtas 25972adb719dSEzequiel Garcia static inline void 259820d446f2SYuval Shaia mvneta_tso_put_hdr(struct sk_buff *skb, struct mvneta_tx_queue *txq) 25992adb719dSEzequiel Garcia { 26002adb719dSEzequiel Garcia int hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb); 26019e58c8b4SLorenzo Bianconi struct mvneta_tx_buf *buf = &txq->buf[txq->txq_put_index]; 26029e58c8b4SLorenzo Bianconi struct mvneta_tx_desc *tx_desc; 26032adb719dSEzequiel Garcia 26042adb719dSEzequiel Garcia tx_desc = mvneta_txq_next_desc_get(txq); 26052adb719dSEzequiel Garcia tx_desc->data_size = hdr_len; 260620d446f2SYuval Shaia tx_desc->command = mvneta_skb_tx_csum(skb); 26072adb719dSEzequiel Garcia tx_desc->command |= MVNETA_TXD_F_DESC; 26082adb719dSEzequiel Garcia tx_desc->buf_phys_addr = txq->tso_hdrs_phys + 26092adb719dSEzequiel Garcia txq->txq_put_index * TSO_HEADER_SIZE; 26109e58c8b4SLorenzo Bianconi buf->type = MVNETA_TYPE_SKB; 26119e58c8b4SLorenzo Bianconi buf->skb = NULL; 26129e58c8b4SLorenzo Bianconi 26132adb719dSEzequiel Garcia mvneta_txq_inc_put(txq); 26142adb719dSEzequiel Garcia } 26152adb719dSEzequiel Garcia 26162adb719dSEzequiel Garcia static inline int 26172adb719dSEzequiel Garcia mvneta_tso_put_data(struct net_device *dev, struct mvneta_tx_queue *txq, 26182adb719dSEzequiel Garcia struct sk_buff *skb, char *data, int size, 26192adb719dSEzequiel Garcia bool last_tcp, bool is_last) 26202adb719dSEzequiel Garcia { 26219e58c8b4SLorenzo Bianconi struct mvneta_tx_buf *buf = &txq->buf[txq->txq_put_index]; 26222adb719dSEzequiel Garcia struct mvneta_tx_desc *tx_desc; 26232adb719dSEzequiel Garcia 26242adb719dSEzequiel Garcia tx_desc = mvneta_txq_next_desc_get(txq); 26252adb719dSEzequiel Garcia tx_desc->data_size = size; 26262adb719dSEzequiel Garcia tx_desc->buf_phys_addr = dma_map_single(dev->dev.parent, data, 26272adb719dSEzequiel Garcia size, DMA_TO_DEVICE); 26282adb719dSEzequiel Garcia if (unlikely(dma_mapping_error(dev->dev.parent, 26292adb719dSEzequiel Garcia tx_desc->buf_phys_addr))) { 26302adb719dSEzequiel Garcia mvneta_txq_desc_put(txq); 26312adb719dSEzequiel Garcia return -ENOMEM; 26322adb719dSEzequiel Garcia } 26332adb719dSEzequiel Garcia 26342adb719dSEzequiel Garcia tx_desc->command = 0; 26359e58c8b4SLorenzo Bianconi buf->type = MVNETA_TYPE_SKB; 26369e58c8b4SLorenzo Bianconi buf->skb = NULL; 26372adb719dSEzequiel Garcia 26382adb719dSEzequiel Garcia if (last_tcp) { 26392adb719dSEzequiel Garcia /* last descriptor in the TCP packet */ 26402adb719dSEzequiel Garcia tx_desc->command = MVNETA_TXD_L_DESC; 26412adb719dSEzequiel Garcia 26422adb719dSEzequiel Garcia /* last descriptor in SKB */ 26432adb719dSEzequiel Garcia if (is_last) 26449e58c8b4SLorenzo Bianconi buf->skb = skb; 26452adb719dSEzequiel Garcia } 26462adb719dSEzequiel Garcia mvneta_txq_inc_put(txq); 26472adb719dSEzequiel Garcia return 0; 26482adb719dSEzequiel Garcia } 26492adb719dSEzequiel Garcia 26502adb719dSEzequiel Garcia static int mvneta_tx_tso(struct sk_buff *skb, struct net_device *dev, 26512adb719dSEzequiel Garcia struct mvneta_tx_queue *txq) 26522adb719dSEzequiel Garcia { 2653761b331cSEric Dumazet int hdr_len, total_len, data_left; 26542adb719dSEzequiel Garcia int desc_count = 0; 26552adb719dSEzequiel Garcia struct mvneta_port *pp = netdev_priv(dev); 26562adb719dSEzequiel Garcia struct tso_t tso; 26572adb719dSEzequiel Garcia int i; 26582adb719dSEzequiel Garcia 26592adb719dSEzequiel Garcia /* Count needed descriptors */ 26602adb719dSEzequiel Garcia if ((txq->count + tso_count_descs(skb)) >= txq->size) 26612adb719dSEzequiel Garcia return 0; 26622adb719dSEzequiel Garcia 26632adb719dSEzequiel Garcia if (skb_headlen(skb) < (skb_transport_offset(skb) + tcp_hdrlen(skb))) { 2664fa660684SColin Ian King pr_info("*** Is this even possible?\n"); 26652adb719dSEzequiel Garcia return 0; 26662adb719dSEzequiel Garcia } 26672adb719dSEzequiel Garcia 26682adb719dSEzequiel Garcia /* Initialize the TSO handler, and prepare the first payload */ 2669761b331cSEric Dumazet hdr_len = tso_start(skb, &tso); 26702adb719dSEzequiel Garcia 26712adb719dSEzequiel Garcia total_len = skb->len - hdr_len; 26722adb719dSEzequiel Garcia while (total_len > 0) { 26732adb719dSEzequiel Garcia char *hdr; 26742adb719dSEzequiel Garcia 26752adb719dSEzequiel Garcia data_left = min_t(int, skb_shinfo(skb)->gso_size, total_len); 26762adb719dSEzequiel Garcia total_len -= data_left; 26772adb719dSEzequiel Garcia desc_count++; 26782adb719dSEzequiel Garcia 26792adb719dSEzequiel Garcia /* prepare packet headers: MAC + IP + TCP */ 26802adb719dSEzequiel Garcia hdr = txq->tso_hdrs + txq->txq_put_index * TSO_HEADER_SIZE; 26812adb719dSEzequiel Garcia tso_build_hdr(skb, hdr, &tso, data_left, total_len == 0); 26822adb719dSEzequiel Garcia 268320d446f2SYuval Shaia mvneta_tso_put_hdr(skb, txq); 26842adb719dSEzequiel Garcia 26852adb719dSEzequiel Garcia while (data_left > 0) { 26862adb719dSEzequiel Garcia int size; 26872adb719dSEzequiel Garcia desc_count++; 26882adb719dSEzequiel Garcia 26892adb719dSEzequiel Garcia size = min_t(int, tso.size, data_left); 26902adb719dSEzequiel Garcia 26912adb719dSEzequiel Garcia if (mvneta_tso_put_data(dev, txq, skb, 26922adb719dSEzequiel Garcia tso.data, size, 26932adb719dSEzequiel Garcia size == data_left, 26942adb719dSEzequiel Garcia total_len == 0)) 26952adb719dSEzequiel Garcia goto err_release; 26962adb719dSEzequiel Garcia data_left -= size; 26972adb719dSEzequiel Garcia 26982adb719dSEzequiel Garcia tso_build_data(skb, &tso, size); 26992adb719dSEzequiel Garcia } 27002adb719dSEzequiel Garcia } 27012adb719dSEzequiel Garcia 27022adb719dSEzequiel Garcia return desc_count; 27032adb719dSEzequiel Garcia 27042adb719dSEzequiel Garcia err_release: 27052adb719dSEzequiel Garcia /* Release all used data descriptors; header descriptors must not 27062adb719dSEzequiel Garcia * be DMA-unmapped. 27072adb719dSEzequiel Garcia */ 27082adb719dSEzequiel Garcia for (i = desc_count - 1; i >= 0; i--) { 27092adb719dSEzequiel Garcia struct mvneta_tx_desc *tx_desc = txq->descs + i; 27102e3173a3SEzequiel Garcia if (!IS_TSO_HEADER(txq, tx_desc->buf_phys_addr)) 27112adb719dSEzequiel Garcia dma_unmap_single(pp->dev->dev.parent, 27122adb719dSEzequiel Garcia tx_desc->buf_phys_addr, 27132adb719dSEzequiel Garcia tx_desc->data_size, 27142adb719dSEzequiel Garcia DMA_TO_DEVICE); 27152adb719dSEzequiel Garcia mvneta_txq_desc_put(txq); 27162adb719dSEzequiel Garcia } 27172adb719dSEzequiel Garcia return 0; 27182adb719dSEzequiel Garcia } 27192adb719dSEzequiel Garcia 2720c5aff182SThomas Petazzoni /* Handle tx fragmentation processing */ 2721c5aff182SThomas Petazzoni static int mvneta_tx_frag_process(struct mvneta_port *pp, struct sk_buff *skb, 2722c5aff182SThomas Petazzoni struct mvneta_tx_queue *txq) 2723c5aff182SThomas Petazzoni { 2724c5aff182SThomas Petazzoni struct mvneta_tx_desc *tx_desc; 27253d4ea02fSEzequiel Garcia int i, nr_frags = skb_shinfo(skb)->nr_frags; 2726c5aff182SThomas Petazzoni 27273d4ea02fSEzequiel Garcia for (i = 0; i < nr_frags; i++) { 27289e58c8b4SLorenzo Bianconi struct mvneta_tx_buf *buf = &txq->buf[txq->txq_put_index]; 2729c5aff182SThomas Petazzoni skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 2730d7840976SMatthew Wilcox (Oracle) void *addr = skb_frag_address(frag); 2731c5aff182SThomas Petazzoni 2732c5aff182SThomas Petazzoni tx_desc = mvneta_txq_next_desc_get(txq); 2733d7840976SMatthew Wilcox (Oracle) tx_desc->data_size = skb_frag_size(frag); 2734c5aff182SThomas Petazzoni 2735c5aff182SThomas Petazzoni tx_desc->buf_phys_addr = 2736c5aff182SThomas Petazzoni dma_map_single(pp->dev->dev.parent, addr, 2737c5aff182SThomas Petazzoni tx_desc->data_size, DMA_TO_DEVICE); 2738c5aff182SThomas Petazzoni 2739c5aff182SThomas Petazzoni if (dma_mapping_error(pp->dev->dev.parent, 2740c5aff182SThomas Petazzoni tx_desc->buf_phys_addr)) { 2741c5aff182SThomas Petazzoni mvneta_txq_desc_put(txq); 2742c5aff182SThomas Petazzoni goto error; 2743c5aff182SThomas Petazzoni } 2744c5aff182SThomas Petazzoni 27453d4ea02fSEzequiel Garcia if (i == nr_frags - 1) { 2746c5aff182SThomas Petazzoni /* Last descriptor */ 2747c5aff182SThomas Petazzoni tx_desc->command = MVNETA_TXD_L_DESC | MVNETA_TXD_Z_PAD; 27489e58c8b4SLorenzo Bianconi buf->skb = skb; 2749c5aff182SThomas Petazzoni } else { 2750c5aff182SThomas Petazzoni /* Descriptor in the middle: Not First, Not Last */ 2751c5aff182SThomas Petazzoni tx_desc->command = 0; 27529e58c8b4SLorenzo Bianconi buf->skb = NULL; 2753c5aff182SThomas Petazzoni } 27549e58c8b4SLorenzo Bianconi buf->type = MVNETA_TYPE_SKB; 27553d4ea02fSEzequiel Garcia mvneta_txq_inc_put(txq); 2756c5aff182SThomas Petazzoni } 2757c5aff182SThomas Petazzoni 2758c5aff182SThomas Petazzoni return 0; 2759c5aff182SThomas Petazzoni 2760c5aff182SThomas Petazzoni error: 2761c5aff182SThomas Petazzoni /* Release all descriptors that were used to map fragments of 27626a20c175SThomas Petazzoni * this packet, as well as the corresponding DMA mappings 27636a20c175SThomas Petazzoni */ 2764c5aff182SThomas Petazzoni for (i = i - 1; i >= 0; i--) { 2765c5aff182SThomas Petazzoni tx_desc = txq->descs + i; 2766c5aff182SThomas Petazzoni dma_unmap_single(pp->dev->dev.parent, 2767c5aff182SThomas Petazzoni tx_desc->buf_phys_addr, 2768c5aff182SThomas Petazzoni tx_desc->data_size, 2769c5aff182SThomas Petazzoni DMA_TO_DEVICE); 2770c5aff182SThomas Petazzoni mvneta_txq_desc_put(txq); 2771c5aff182SThomas Petazzoni } 2772c5aff182SThomas Petazzoni 2773c5aff182SThomas Petazzoni return -ENOMEM; 2774c5aff182SThomas Petazzoni } 2775c5aff182SThomas Petazzoni 2776c5aff182SThomas Petazzoni /* Main tx processing */ 2777f03508ceSYueHaibing static netdev_tx_t mvneta_tx(struct sk_buff *skb, struct net_device *dev) 2778c5aff182SThomas Petazzoni { 2779c5aff182SThomas Petazzoni struct mvneta_port *pp = netdev_priv(dev); 2780ee40a116SWilly Tarreau u16 txq_id = skb_get_queue_mapping(skb); 2781ee40a116SWilly Tarreau struct mvneta_tx_queue *txq = &pp->txqs[txq_id]; 27829e58c8b4SLorenzo Bianconi struct mvneta_tx_buf *buf = &txq->buf[txq->txq_put_index]; 2783c5aff182SThomas Petazzoni struct mvneta_tx_desc *tx_desc; 27845f478b41SEric Dumazet int len = skb->len; 2785c5aff182SThomas Petazzoni int frags = 0; 2786c5aff182SThomas Petazzoni u32 tx_cmd; 2787c5aff182SThomas Petazzoni 2788c5aff182SThomas Petazzoni if (!netif_running(dev)) 2789c5aff182SThomas Petazzoni goto out; 2790c5aff182SThomas Petazzoni 27912adb719dSEzequiel Garcia if (skb_is_gso(skb)) { 27922adb719dSEzequiel Garcia frags = mvneta_tx_tso(skb, dev, txq); 27932adb719dSEzequiel Garcia goto out; 27942adb719dSEzequiel Garcia } 27952adb719dSEzequiel Garcia 2796c5aff182SThomas Petazzoni frags = skb_shinfo(skb)->nr_frags + 1; 2797c5aff182SThomas Petazzoni 2798c5aff182SThomas Petazzoni /* Get a descriptor for the first part of the packet */ 2799c5aff182SThomas Petazzoni tx_desc = mvneta_txq_next_desc_get(txq); 2800c5aff182SThomas Petazzoni 280120d446f2SYuval Shaia tx_cmd = mvneta_skb_tx_csum(skb); 2802c5aff182SThomas Petazzoni 2803c5aff182SThomas Petazzoni tx_desc->data_size = skb_headlen(skb); 2804c5aff182SThomas Petazzoni 2805c5aff182SThomas Petazzoni tx_desc->buf_phys_addr = dma_map_single(dev->dev.parent, skb->data, 2806c5aff182SThomas Petazzoni tx_desc->data_size, 2807c5aff182SThomas Petazzoni DMA_TO_DEVICE); 2808c5aff182SThomas Petazzoni if (unlikely(dma_mapping_error(dev->dev.parent, 2809c5aff182SThomas Petazzoni tx_desc->buf_phys_addr))) { 2810c5aff182SThomas Petazzoni mvneta_txq_desc_put(txq); 2811c5aff182SThomas Petazzoni frags = 0; 2812c5aff182SThomas Petazzoni goto out; 2813c5aff182SThomas Petazzoni } 2814c5aff182SThomas Petazzoni 28159e58c8b4SLorenzo Bianconi buf->type = MVNETA_TYPE_SKB; 2816c5aff182SThomas Petazzoni if (frags == 1) { 2817c5aff182SThomas Petazzoni /* First and Last descriptor */ 2818c5aff182SThomas Petazzoni tx_cmd |= MVNETA_TXD_FLZ_DESC; 2819c5aff182SThomas Petazzoni tx_desc->command = tx_cmd; 28209e58c8b4SLorenzo Bianconi buf->skb = skb; 2821c5aff182SThomas Petazzoni mvneta_txq_inc_put(txq); 2822c5aff182SThomas Petazzoni } else { 2823c5aff182SThomas Petazzoni /* First but not Last */ 2824c5aff182SThomas Petazzoni tx_cmd |= MVNETA_TXD_F_DESC; 28259e58c8b4SLorenzo Bianconi buf->skb = NULL; 2826c5aff182SThomas Petazzoni mvneta_txq_inc_put(txq); 2827c5aff182SThomas Petazzoni tx_desc->command = tx_cmd; 2828c5aff182SThomas Petazzoni /* Continue with other skb fragments */ 2829c5aff182SThomas Petazzoni if (mvneta_tx_frag_process(pp, skb, txq)) { 2830c5aff182SThomas Petazzoni dma_unmap_single(dev->dev.parent, 2831c5aff182SThomas Petazzoni tx_desc->buf_phys_addr, 2832c5aff182SThomas Petazzoni tx_desc->data_size, 2833c5aff182SThomas Petazzoni DMA_TO_DEVICE); 2834c5aff182SThomas Petazzoni mvneta_txq_desc_put(txq); 2835c5aff182SThomas Petazzoni frags = 0; 2836c5aff182SThomas Petazzoni goto out; 2837c5aff182SThomas Petazzoni } 2838c5aff182SThomas Petazzoni } 2839c5aff182SThomas Petazzoni 2840e19d2ddaSEzequiel Garcia out: 2841e19d2ddaSEzequiel Garcia if (frags > 0) { 2842e19d2ddaSEzequiel Garcia struct netdev_queue *nq = netdev_get_tx_queue(dev, txq_id); 284369de66fcSLorenzo Bianconi struct mvneta_pcpu_stats *stats = this_cpu_ptr(pp->stats); 2844e19d2ddaSEzequiel Garcia 2845a29b6235SMarcin Wojtas netdev_tx_sent_queue(nq, len); 2846a29b6235SMarcin Wojtas 2847c5aff182SThomas Petazzoni txq->count += frags; 28488eef5f97SEzequiel Garcia if (txq->count >= txq->tx_stop_threshold) 2849c5aff182SThomas Petazzoni netif_tx_stop_queue(nq); 2850c5aff182SThomas Petazzoni 28516b16f9eeSFlorian Westphal if (!netdev_xmit_more() || netif_xmit_stopped(nq) || 28522a90f7e1SSimon Guinot txq->pending + frags > MVNETA_TXQ_DEC_SENT_MASK) 28532a90f7e1SSimon Guinot mvneta_txq_pend_desc_add(pp, txq, frags); 28542a90f7e1SSimon Guinot else 28552a90f7e1SSimon Guinot txq->pending += frags; 28562a90f7e1SSimon Guinot 285769de66fcSLorenzo Bianconi u64_stats_update_begin(&stats->syncp); 2858320d5441SLorenzo Bianconi stats->es.ps.tx_bytes += len; 2859320d5441SLorenzo Bianconi stats->es.ps.tx_packets++; 286069de66fcSLorenzo Bianconi u64_stats_update_end(&stats->syncp); 2861c5aff182SThomas Petazzoni } else { 2862c5aff182SThomas Petazzoni dev->stats.tx_dropped++; 2863c5aff182SThomas Petazzoni dev_kfree_skb_any(skb); 2864c5aff182SThomas Petazzoni } 2865c5aff182SThomas Petazzoni 2866c5aff182SThomas Petazzoni return NETDEV_TX_OK; 2867c5aff182SThomas Petazzoni } 2868c5aff182SThomas Petazzoni 2869c5aff182SThomas Petazzoni 2870c5aff182SThomas Petazzoni /* Free tx resources, when resetting a port */ 2871c5aff182SThomas Petazzoni static void mvneta_txq_done_force(struct mvneta_port *pp, 2872c5aff182SThomas Petazzoni struct mvneta_tx_queue *txq) 2873c5aff182SThomas Petazzoni 2874c5aff182SThomas Petazzoni { 2875a29b6235SMarcin Wojtas struct netdev_queue *nq = netdev_get_tx_queue(pp->dev, txq->id); 2876c5aff182SThomas Petazzoni int tx_done = txq->count; 2877c5aff182SThomas Petazzoni 2878632bb64fSLorenzo Bianconi mvneta_txq_bufs_free(pp, txq, tx_done, nq, false); 2879c5aff182SThomas Petazzoni 2880c5aff182SThomas Petazzoni /* reset txq */ 2881c5aff182SThomas Petazzoni txq->count = 0; 2882c5aff182SThomas Petazzoni txq->txq_put_index = 0; 2883c5aff182SThomas Petazzoni txq->txq_get_index = 0; 2884c5aff182SThomas Petazzoni } 2885c5aff182SThomas Petazzoni 28866c498974Swilly tarreau /* Handle tx done - called in softirq context. The <cause_tx_done> argument 28876c498974Swilly tarreau * must be a valid cause according to MVNETA_TXQ_INTR_MASK_ALL. 28886c498974Swilly tarreau */ 28890713a86aSArnaud Ebalard static void mvneta_tx_done_gbe(struct mvneta_port *pp, u32 cause_tx_done) 2890c5aff182SThomas Petazzoni { 2891c5aff182SThomas Petazzoni struct mvneta_tx_queue *txq; 2892c5aff182SThomas Petazzoni struct netdev_queue *nq; 2893bd9f1ee3SJisheng Zhang int cpu = smp_processor_id(); 2894c5aff182SThomas Petazzoni 28956c498974Swilly tarreau while (cause_tx_done) { 2896c5aff182SThomas Petazzoni txq = mvneta_tx_done_policy(pp, cause_tx_done); 2897c5aff182SThomas Petazzoni 2898c5aff182SThomas Petazzoni nq = netdev_get_tx_queue(pp->dev, txq->id); 2899bd9f1ee3SJisheng Zhang __netif_tx_lock(nq, cpu); 2900c5aff182SThomas Petazzoni 29010713a86aSArnaud Ebalard if (txq->count) 29020713a86aSArnaud Ebalard mvneta_txq_done(pp, txq); 2903c5aff182SThomas Petazzoni 2904c5aff182SThomas Petazzoni __netif_tx_unlock(nq); 2905c5aff182SThomas Petazzoni cause_tx_done &= ~((1 << txq->id)); 2906c5aff182SThomas Petazzoni } 2907c5aff182SThomas Petazzoni } 2908c5aff182SThomas Petazzoni 29096a20c175SThomas Petazzoni /* Compute crc8 of the specified address, using a unique algorithm , 2910c5aff182SThomas Petazzoni * according to hw spec, different than generic crc8 algorithm 2911c5aff182SThomas Petazzoni */ 2912c5aff182SThomas Petazzoni static int mvneta_addr_crc(unsigned char *addr) 2913c5aff182SThomas Petazzoni { 2914c5aff182SThomas Petazzoni int crc = 0; 2915c5aff182SThomas Petazzoni int i; 2916c5aff182SThomas Petazzoni 2917c5aff182SThomas Petazzoni for (i = 0; i < ETH_ALEN; i++) { 2918c5aff182SThomas Petazzoni int j; 2919c5aff182SThomas Petazzoni 2920c5aff182SThomas Petazzoni crc = (crc ^ addr[i]) << 8; 2921c5aff182SThomas Petazzoni for (j = 7; j >= 0; j--) { 2922c5aff182SThomas Petazzoni if (crc & (0x100 << j)) 2923c5aff182SThomas Petazzoni crc ^= 0x107 << j; 2924c5aff182SThomas Petazzoni } 2925c5aff182SThomas Petazzoni } 2926c5aff182SThomas Petazzoni 2927c5aff182SThomas Petazzoni return crc; 2928c5aff182SThomas Petazzoni } 2929c5aff182SThomas Petazzoni 2930c5aff182SThomas Petazzoni /* This method controls the net device special MAC multicast support. 2931c5aff182SThomas Petazzoni * The Special Multicast Table for MAC addresses supports MAC of the form 2932c5aff182SThomas Petazzoni * 0x01-00-5E-00-00-XX (where XX is between 0x00 and 0xFF). 2933c5aff182SThomas Petazzoni * The MAC DA[7:0] bits are used as a pointer to the Special Multicast 2934c5aff182SThomas Petazzoni * Table entries in the DA-Filter table. This method set the Special 2935c5aff182SThomas Petazzoni * Multicast Table appropriate entry. 2936c5aff182SThomas Petazzoni */ 2937c5aff182SThomas Petazzoni static void mvneta_set_special_mcast_addr(struct mvneta_port *pp, 2938c5aff182SThomas Petazzoni unsigned char last_byte, 2939c5aff182SThomas Petazzoni int queue) 2940c5aff182SThomas Petazzoni { 2941c5aff182SThomas Petazzoni unsigned int smc_table_reg; 2942c5aff182SThomas Petazzoni unsigned int tbl_offset; 2943c5aff182SThomas Petazzoni unsigned int reg_offset; 2944c5aff182SThomas Petazzoni 2945c5aff182SThomas Petazzoni /* Register offset from SMC table base */ 2946c5aff182SThomas Petazzoni tbl_offset = (last_byte / 4); 2947c5aff182SThomas Petazzoni /* Entry offset within the above reg */ 2948c5aff182SThomas Petazzoni reg_offset = last_byte % 4; 2949c5aff182SThomas Petazzoni 2950c5aff182SThomas Petazzoni smc_table_reg = mvreg_read(pp, (MVNETA_DA_FILT_SPEC_MCAST 2951c5aff182SThomas Petazzoni + tbl_offset * 4)); 2952c5aff182SThomas Petazzoni 2953c5aff182SThomas Petazzoni if (queue == -1) 2954c5aff182SThomas Petazzoni smc_table_reg &= ~(0xff << (8 * reg_offset)); 2955c5aff182SThomas Petazzoni else { 2956c5aff182SThomas Petazzoni smc_table_reg &= ~(0xff << (8 * reg_offset)); 2957c5aff182SThomas Petazzoni smc_table_reg |= ((0x01 | (queue << 1)) << (8 * reg_offset)); 2958c5aff182SThomas Petazzoni } 2959c5aff182SThomas Petazzoni 2960c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_DA_FILT_SPEC_MCAST + tbl_offset * 4, 2961c5aff182SThomas Petazzoni smc_table_reg); 2962c5aff182SThomas Petazzoni } 2963c5aff182SThomas Petazzoni 2964c5aff182SThomas Petazzoni /* This method controls the network device Other MAC multicast support. 2965c5aff182SThomas Petazzoni * The Other Multicast Table is used for multicast of another type. 2966c5aff182SThomas Petazzoni * A CRC-8 is used as an index to the Other Multicast Table entries 2967c5aff182SThomas Petazzoni * in the DA-Filter table. 2968c5aff182SThomas Petazzoni * The method gets the CRC-8 value from the calling routine and 2969c5aff182SThomas Petazzoni * sets the Other Multicast Table appropriate entry according to the 2970c5aff182SThomas Petazzoni * specified CRC-8 . 2971c5aff182SThomas Petazzoni */ 2972c5aff182SThomas Petazzoni static void mvneta_set_other_mcast_addr(struct mvneta_port *pp, 2973c5aff182SThomas Petazzoni unsigned char crc8, 2974c5aff182SThomas Petazzoni int queue) 2975c5aff182SThomas Petazzoni { 2976c5aff182SThomas Petazzoni unsigned int omc_table_reg; 2977c5aff182SThomas Petazzoni unsigned int tbl_offset; 2978c5aff182SThomas Petazzoni unsigned int reg_offset; 2979c5aff182SThomas Petazzoni 2980c5aff182SThomas Petazzoni tbl_offset = (crc8 / 4) * 4; /* Register offset from OMC table base */ 2981c5aff182SThomas Petazzoni reg_offset = crc8 % 4; /* Entry offset within the above reg */ 2982c5aff182SThomas Petazzoni 2983c5aff182SThomas Petazzoni omc_table_reg = mvreg_read(pp, MVNETA_DA_FILT_OTH_MCAST + tbl_offset); 2984c5aff182SThomas Petazzoni 2985c5aff182SThomas Petazzoni if (queue == -1) { 2986c5aff182SThomas Petazzoni /* Clear accepts frame bit at specified Other DA table entry */ 2987c5aff182SThomas Petazzoni omc_table_reg &= ~(0xff << (8 * reg_offset)); 2988c5aff182SThomas Petazzoni } else { 2989c5aff182SThomas Petazzoni omc_table_reg &= ~(0xff << (8 * reg_offset)); 2990c5aff182SThomas Petazzoni omc_table_reg |= ((0x01 | (queue << 1)) << (8 * reg_offset)); 2991c5aff182SThomas Petazzoni } 2992c5aff182SThomas Petazzoni 2993c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_DA_FILT_OTH_MCAST + tbl_offset, omc_table_reg); 2994c5aff182SThomas Petazzoni } 2995c5aff182SThomas Petazzoni 2996c5aff182SThomas Petazzoni /* The network device supports multicast using two tables: 2997c5aff182SThomas Petazzoni * 1) Special Multicast Table for MAC addresses of the form 2998c5aff182SThomas Petazzoni * 0x01-00-5E-00-00-XX (where XX is between 0x00 and 0xFF). 2999c5aff182SThomas Petazzoni * The MAC DA[7:0] bits are used as a pointer to the Special Multicast 3000c5aff182SThomas Petazzoni * Table entries in the DA-Filter table. 3001c5aff182SThomas Petazzoni * 2) Other Multicast Table for multicast of another type. A CRC-8 value 3002c5aff182SThomas Petazzoni * is used as an index to the Other Multicast Table entries in the 3003c5aff182SThomas Petazzoni * DA-Filter table. 3004c5aff182SThomas Petazzoni */ 3005c5aff182SThomas Petazzoni static int mvneta_mcast_addr_set(struct mvneta_port *pp, unsigned char *p_addr, 3006c5aff182SThomas Petazzoni int queue) 3007c5aff182SThomas Petazzoni { 3008c5aff182SThomas Petazzoni unsigned char crc_result = 0; 3009c5aff182SThomas Petazzoni 3010c5aff182SThomas Petazzoni if (memcmp(p_addr, "\x01\x00\x5e\x00\x00", 5) == 0) { 3011c5aff182SThomas Petazzoni mvneta_set_special_mcast_addr(pp, p_addr[5], queue); 3012c5aff182SThomas Petazzoni return 0; 3013c5aff182SThomas Petazzoni } 3014c5aff182SThomas Petazzoni 3015c5aff182SThomas Petazzoni crc_result = mvneta_addr_crc(p_addr); 3016c5aff182SThomas Petazzoni if (queue == -1) { 3017c5aff182SThomas Petazzoni if (pp->mcast_count[crc_result] == 0) { 3018c5aff182SThomas Petazzoni netdev_info(pp->dev, "No valid Mcast for crc8=0x%02x\n", 3019c5aff182SThomas Petazzoni crc_result); 3020c5aff182SThomas Petazzoni return -EINVAL; 3021c5aff182SThomas Petazzoni } 3022c5aff182SThomas Petazzoni 3023c5aff182SThomas Petazzoni pp->mcast_count[crc_result]--; 3024c5aff182SThomas Petazzoni if (pp->mcast_count[crc_result] != 0) { 3025c5aff182SThomas Petazzoni netdev_info(pp->dev, 3026c5aff182SThomas Petazzoni "After delete there are %d valid Mcast for crc8=0x%02x\n", 3027c5aff182SThomas Petazzoni pp->mcast_count[crc_result], crc_result); 3028c5aff182SThomas Petazzoni return -EINVAL; 3029c5aff182SThomas Petazzoni } 3030c5aff182SThomas Petazzoni } else 3031c5aff182SThomas Petazzoni pp->mcast_count[crc_result]++; 3032c5aff182SThomas Petazzoni 3033c5aff182SThomas Petazzoni mvneta_set_other_mcast_addr(pp, crc_result, queue); 3034c5aff182SThomas Petazzoni 3035c5aff182SThomas Petazzoni return 0; 3036c5aff182SThomas Petazzoni } 3037c5aff182SThomas Petazzoni 3038c5aff182SThomas Petazzoni /* Configure Fitering mode of Ethernet port */ 3039c5aff182SThomas Petazzoni static void mvneta_rx_unicast_promisc_set(struct mvneta_port *pp, 3040c5aff182SThomas Petazzoni int is_promisc) 3041c5aff182SThomas Petazzoni { 3042c5aff182SThomas Petazzoni u32 port_cfg_reg, val; 3043c5aff182SThomas Petazzoni 3044c5aff182SThomas Petazzoni port_cfg_reg = mvreg_read(pp, MVNETA_PORT_CONFIG); 3045c5aff182SThomas Petazzoni 3046c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_TYPE_PRIO); 3047c5aff182SThomas Petazzoni 3048c5aff182SThomas Petazzoni /* Set / Clear UPM bit in port configuration register */ 3049c5aff182SThomas Petazzoni if (is_promisc) { 3050c5aff182SThomas Petazzoni /* Accept all Unicast addresses */ 3051c5aff182SThomas Petazzoni port_cfg_reg |= MVNETA_UNI_PROMISC_MODE; 3052c5aff182SThomas Petazzoni val |= MVNETA_FORCE_UNI; 3053c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_MAC_ADDR_LOW, 0xffff); 3054c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_MAC_ADDR_HIGH, 0xffffffff); 3055c5aff182SThomas Petazzoni } else { 3056c5aff182SThomas Petazzoni /* Reject all Unicast addresses */ 3057c5aff182SThomas Petazzoni port_cfg_reg &= ~MVNETA_UNI_PROMISC_MODE; 3058c5aff182SThomas Petazzoni val &= ~MVNETA_FORCE_UNI; 3059c5aff182SThomas Petazzoni } 3060c5aff182SThomas Petazzoni 3061c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_PORT_CONFIG, port_cfg_reg); 3062c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_TYPE_PRIO, val); 3063c5aff182SThomas Petazzoni } 3064c5aff182SThomas Petazzoni 3065c5aff182SThomas Petazzoni /* register unicast and multicast addresses */ 3066c5aff182SThomas Petazzoni static void mvneta_set_rx_mode(struct net_device *dev) 3067c5aff182SThomas Petazzoni { 3068c5aff182SThomas Petazzoni struct mvneta_port *pp = netdev_priv(dev); 3069c5aff182SThomas Petazzoni struct netdev_hw_addr *ha; 3070c5aff182SThomas Petazzoni 3071c5aff182SThomas Petazzoni if (dev->flags & IFF_PROMISC) { 3072c5aff182SThomas Petazzoni /* Accept all: Multicast + Unicast */ 3073c5aff182SThomas Petazzoni mvneta_rx_unicast_promisc_set(pp, 1); 307490b74c01SGregory CLEMENT mvneta_set_ucast_table(pp, pp->rxq_def); 307590b74c01SGregory CLEMENT mvneta_set_special_mcast_table(pp, pp->rxq_def); 307690b74c01SGregory CLEMENT mvneta_set_other_mcast_table(pp, pp->rxq_def); 3077c5aff182SThomas Petazzoni } else { 3078c5aff182SThomas Petazzoni /* Accept single Unicast */ 3079c5aff182SThomas Petazzoni mvneta_rx_unicast_promisc_set(pp, 0); 3080c5aff182SThomas Petazzoni mvneta_set_ucast_table(pp, -1); 308190b74c01SGregory CLEMENT mvneta_mac_addr_set(pp, dev->dev_addr, pp->rxq_def); 3082c5aff182SThomas Petazzoni 3083c5aff182SThomas Petazzoni if (dev->flags & IFF_ALLMULTI) { 3084c5aff182SThomas Petazzoni /* Accept all multicast */ 308590b74c01SGregory CLEMENT mvneta_set_special_mcast_table(pp, pp->rxq_def); 308690b74c01SGregory CLEMENT mvneta_set_other_mcast_table(pp, pp->rxq_def); 3087c5aff182SThomas Petazzoni } else { 3088c5aff182SThomas Petazzoni /* Accept only initialized multicast */ 3089c5aff182SThomas Petazzoni mvneta_set_special_mcast_table(pp, -1); 3090c5aff182SThomas Petazzoni mvneta_set_other_mcast_table(pp, -1); 3091c5aff182SThomas Petazzoni 3092c5aff182SThomas Petazzoni if (!netdev_mc_empty(dev)) { 3093c5aff182SThomas Petazzoni netdev_for_each_mc_addr(ha, dev) { 3094c5aff182SThomas Petazzoni mvneta_mcast_addr_set(pp, ha->addr, 309590b74c01SGregory CLEMENT pp->rxq_def); 3096c5aff182SThomas Petazzoni } 3097c5aff182SThomas Petazzoni } 3098c5aff182SThomas Petazzoni } 3099c5aff182SThomas Petazzoni } 3100c5aff182SThomas Petazzoni } 3101c5aff182SThomas Petazzoni 3102c5aff182SThomas Petazzoni /* Interrupt handling - the callback for request_irq() */ 3103c5aff182SThomas Petazzoni static irqreturn_t mvneta_isr(int irq, void *dev_id) 3104c5aff182SThomas Petazzoni { 31052636ac3cSMarcin Wojtas struct mvneta_port *pp = (struct mvneta_port *)dev_id; 31062636ac3cSMarcin Wojtas 31072636ac3cSMarcin Wojtas mvreg_write(pp, MVNETA_INTR_NEW_MASK, 0); 31082636ac3cSMarcin Wojtas napi_schedule(&pp->napi); 31092636ac3cSMarcin Wojtas 31102636ac3cSMarcin Wojtas return IRQ_HANDLED; 31112636ac3cSMarcin Wojtas } 31122636ac3cSMarcin Wojtas 31132636ac3cSMarcin Wojtas /* Interrupt handling - the callback for request_percpu_irq() */ 31142636ac3cSMarcin Wojtas static irqreturn_t mvneta_percpu_isr(int irq, void *dev_id) 31152636ac3cSMarcin Wojtas { 311612bb03b4SMaxime Ripard struct mvneta_pcpu_port *port = (struct mvneta_pcpu_port *)dev_id; 3117c5aff182SThomas Petazzoni 311812bb03b4SMaxime Ripard disable_percpu_irq(port->pp->dev->irq); 311912bb03b4SMaxime Ripard napi_schedule(&port->napi); 3120c5aff182SThomas Petazzoni 3121c5aff182SThomas Petazzoni return IRQ_HANDLED; 3122c5aff182SThomas Petazzoni } 3123c5aff182SThomas Petazzoni 3124503f9aa9SRussell King static void mvneta_link_change(struct mvneta_port *pp) 3125898b2970SStas Sergeev { 3126898b2970SStas Sergeev u32 gmac_stat = mvreg_read(pp, MVNETA_GMAC_STATUS); 3127898b2970SStas Sergeev 3128503f9aa9SRussell King phylink_mac_change(pp->phylink, !!(gmac_stat & MVNETA_GMAC_LINK_UP)); 3129898b2970SStas Sergeev } 3130898b2970SStas Sergeev 3131c5aff182SThomas Petazzoni /* NAPI handler 3132c5aff182SThomas Petazzoni * Bits 0 - 7 of the causeRxTx register indicate that are transmitted 3133c5aff182SThomas Petazzoni * packets on the corresponding TXQ (Bit 0 is for TX queue 1). 3134c5aff182SThomas Petazzoni * Bits 8 -15 of the cause Rx Tx register indicate that are received 3135c5aff182SThomas Petazzoni * packets on the corresponding RXQ (Bit 8 is for RX queue 0). 3136c5aff182SThomas Petazzoni * Each CPU has its own causeRxTx register 3137c5aff182SThomas Petazzoni */ 3138c5aff182SThomas Petazzoni static int mvneta_poll(struct napi_struct *napi, int budget) 3139c5aff182SThomas Petazzoni { 3140c5aff182SThomas Petazzoni int rx_done = 0; 3141c5aff182SThomas Petazzoni u32 cause_rx_tx; 31422dcf75e2SGregory CLEMENT int rx_queue; 3143c5aff182SThomas Petazzoni struct mvneta_port *pp = netdev_priv(napi->dev); 314412bb03b4SMaxime Ripard struct mvneta_pcpu_port *port = this_cpu_ptr(pp->ports); 3145c5aff182SThomas Petazzoni 3146c5aff182SThomas Petazzoni if (!netif_running(pp->dev)) { 31472636ac3cSMarcin Wojtas napi_complete(napi); 3148c5aff182SThomas Petazzoni return rx_done; 3149c5aff182SThomas Petazzoni } 3150c5aff182SThomas Petazzoni 3151c5aff182SThomas Petazzoni /* Read cause register */ 3152898b2970SStas Sergeev cause_rx_tx = mvreg_read(pp, MVNETA_INTR_NEW_CAUSE); 3153898b2970SStas Sergeev if (cause_rx_tx & MVNETA_MISCINTR_INTR_MASK) { 3154898b2970SStas Sergeev u32 cause_misc = mvreg_read(pp, MVNETA_INTR_MISC_CAUSE); 3155898b2970SStas Sergeev 3156898b2970SStas Sergeev mvreg_write(pp, MVNETA_INTR_MISC_CAUSE, 0); 3157503f9aa9SRussell King 3158503f9aa9SRussell King if (cause_misc & (MVNETA_CAUSE_PHY_STATUS_CHANGE | 3159856b2cc5SRussell King MVNETA_CAUSE_LINK_CHANGE)) 3160503f9aa9SRussell King mvneta_link_change(pp); 3161898b2970SStas Sergeev } 316271f6d1b3Swilly tarreau 316371f6d1b3Swilly tarreau /* Release Tx descriptors */ 316471f6d1b3Swilly tarreau if (cause_rx_tx & MVNETA_TX_INTR_MASK_ALL) { 31650713a86aSArnaud Ebalard mvneta_tx_done_gbe(pp, (cause_rx_tx & MVNETA_TX_INTR_MASK_ALL)); 316671f6d1b3Swilly tarreau cause_rx_tx &= ~MVNETA_TX_INTR_MASK_ALL; 316771f6d1b3Swilly tarreau } 3168c5aff182SThomas Petazzoni 31696a20c175SThomas Petazzoni /* For the case where the last mvneta_poll did not process all 3170c5aff182SThomas Petazzoni * RX packets 3171c5aff182SThomas Petazzoni */ 31722636ac3cSMarcin Wojtas cause_rx_tx |= pp->neta_armada3700 ? pp->cause_rx_tx : 31732636ac3cSMarcin Wojtas port->cause_rx_tx; 31742dcf75e2SGregory CLEMENT 3175065fd83eSJisheng Zhang rx_queue = fls(((cause_rx_tx >> 8) & 0xff)); 31762dcf75e2SGregory CLEMENT if (rx_queue) { 31772dcf75e2SGregory CLEMENT rx_queue = rx_queue - 1; 3178dc35a10fSMarcin Wojtas if (pp->bm_priv) 31797a86f05fSAndrew Lunn rx_done = mvneta_rx_hwbm(napi, pp, budget, 31807a86f05fSAndrew Lunn &pp->rxqs[rx_queue]); 3181dc35a10fSMarcin Wojtas else 31827a86f05fSAndrew Lunn rx_done = mvneta_rx_swbm(napi, pp, budget, 31837a86f05fSAndrew Lunn &pp->rxqs[rx_queue]); 31842dcf75e2SGregory CLEMENT } 31852dcf75e2SGregory CLEMENT 31866ad20165SEric Dumazet if (rx_done < budget) { 3187c5aff182SThomas Petazzoni cause_rx_tx = 0; 31886ad20165SEric Dumazet napi_complete_done(napi, rx_done); 31892636ac3cSMarcin Wojtas 31902636ac3cSMarcin Wojtas if (pp->neta_armada3700) { 31912636ac3cSMarcin Wojtas unsigned long flags; 31922636ac3cSMarcin Wojtas 31932636ac3cSMarcin Wojtas local_irq_save(flags); 31942636ac3cSMarcin Wojtas mvreg_write(pp, MVNETA_INTR_NEW_MASK, 31952636ac3cSMarcin Wojtas MVNETA_RX_INTR_MASK(rxq_number) | 31962636ac3cSMarcin Wojtas MVNETA_TX_INTR_MASK(txq_number) | 31972636ac3cSMarcin Wojtas MVNETA_MISCINTR_INTR_MASK); 31982636ac3cSMarcin Wojtas local_irq_restore(flags); 31992636ac3cSMarcin Wojtas } else { 320012bb03b4SMaxime Ripard enable_percpu_irq(pp->dev->irq, 0); 3201c5aff182SThomas Petazzoni } 32022636ac3cSMarcin Wojtas } 3203c5aff182SThomas Petazzoni 32042636ac3cSMarcin Wojtas if (pp->neta_armada3700) 32052636ac3cSMarcin Wojtas pp->cause_rx_tx = cause_rx_tx; 32062636ac3cSMarcin Wojtas else 320712bb03b4SMaxime Ripard port->cause_rx_tx = cause_rx_tx; 32082636ac3cSMarcin Wojtas 3209c5aff182SThomas Petazzoni return rx_done; 3210c5aff182SThomas Petazzoni } 3211c5aff182SThomas Petazzoni 3212568a3fa2SLorenzo Bianconi static int mvneta_create_page_pool(struct mvneta_port *pp, 3213568a3fa2SLorenzo Bianconi struct mvneta_rx_queue *rxq, int size) 3214568a3fa2SLorenzo Bianconi { 32150db51da7SLorenzo Bianconi struct bpf_prog *xdp_prog = READ_ONCE(pp->xdp_prog); 3216568a3fa2SLorenzo Bianconi struct page_pool_params pp_params = { 3217568a3fa2SLorenzo Bianconi .order = 0, 321807e13edbSLorenzo Bianconi .flags = PP_FLAG_DMA_MAP | PP_FLAG_DMA_SYNC_DEV, 3219568a3fa2SLorenzo Bianconi .pool_size = size, 32201657adccSLorenzo Bianconi .nid = NUMA_NO_NODE, 3221568a3fa2SLorenzo Bianconi .dev = pp->dev->dev.parent, 32220db51da7SLorenzo Bianconi .dma_dir = xdp_prog ? DMA_BIDIRECTIONAL : DMA_FROM_DEVICE, 322307e13edbSLorenzo Bianconi .offset = pp->rx_offset_correction, 322407e13edbSLorenzo Bianconi .max_len = MVNETA_MAX_RX_BUF_SIZE, 3225568a3fa2SLorenzo Bianconi }; 3226568a3fa2SLorenzo Bianconi int err; 3227568a3fa2SLorenzo Bianconi 3228568a3fa2SLorenzo Bianconi rxq->page_pool = page_pool_create(&pp_params); 3229568a3fa2SLorenzo Bianconi if (IS_ERR(rxq->page_pool)) { 3230568a3fa2SLorenzo Bianconi err = PTR_ERR(rxq->page_pool); 3231568a3fa2SLorenzo Bianconi rxq->page_pool = NULL; 3232568a3fa2SLorenzo Bianconi return err; 3233568a3fa2SLorenzo Bianconi } 3234568a3fa2SLorenzo Bianconi 3235b02e5a0eSBjörn Töpel err = xdp_rxq_info_reg(&rxq->xdp_rxq, pp->dev, rxq->id, 0); 3236568a3fa2SLorenzo Bianconi if (err < 0) 3237568a3fa2SLorenzo Bianconi goto err_free_pp; 3238568a3fa2SLorenzo Bianconi 3239568a3fa2SLorenzo Bianconi err = xdp_rxq_info_reg_mem_model(&rxq->xdp_rxq, MEM_TYPE_PAGE_POOL, 3240568a3fa2SLorenzo Bianconi rxq->page_pool); 3241568a3fa2SLorenzo Bianconi if (err) 3242568a3fa2SLorenzo Bianconi goto err_unregister_rxq; 3243568a3fa2SLorenzo Bianconi 3244568a3fa2SLorenzo Bianconi return 0; 3245568a3fa2SLorenzo Bianconi 3246568a3fa2SLorenzo Bianconi err_unregister_rxq: 3247568a3fa2SLorenzo Bianconi xdp_rxq_info_unreg(&rxq->xdp_rxq); 3248568a3fa2SLorenzo Bianconi err_free_pp: 3249568a3fa2SLorenzo Bianconi page_pool_destroy(rxq->page_pool); 3250568a3fa2SLorenzo Bianconi rxq->page_pool = NULL; 3251568a3fa2SLorenzo Bianconi return err; 3252568a3fa2SLorenzo Bianconi } 3253568a3fa2SLorenzo Bianconi 3254c5aff182SThomas Petazzoni /* Handle rxq fill: allocates rxq skbs; called when initializing a port */ 3255c5aff182SThomas Petazzoni static int mvneta_rxq_fill(struct mvneta_port *pp, struct mvneta_rx_queue *rxq, 3256c5aff182SThomas Petazzoni int num) 3257c5aff182SThomas Petazzoni { 3258568a3fa2SLorenzo Bianconi int i, err; 3259568a3fa2SLorenzo Bianconi 3260568a3fa2SLorenzo Bianconi err = mvneta_create_page_pool(pp, rxq, num); 3261568a3fa2SLorenzo Bianconi if (err < 0) 3262568a3fa2SLorenzo Bianconi return err; 3263c5aff182SThomas Petazzoni 3264c5aff182SThomas Petazzoni for (i = 0; i < num; i++) { 3265a1a65ab1Swilly tarreau memset(rxq->descs + i, 0, sizeof(struct mvneta_rx_desc)); 32667e47fd84SGregory CLEMENT if (mvneta_rx_refill(pp, rxq->descs + i, rxq, 32677e47fd84SGregory CLEMENT GFP_KERNEL) != 0) { 32687e47fd84SGregory CLEMENT netdev_err(pp->dev, 32697e47fd84SGregory CLEMENT "%s:rxq %d, %d of %d buffs filled\n", 3270c5aff182SThomas Petazzoni __func__, rxq->id, i, num); 3271c5aff182SThomas Petazzoni break; 3272c5aff182SThomas Petazzoni } 3273c5aff182SThomas Petazzoni } 3274c5aff182SThomas Petazzoni 3275c5aff182SThomas Petazzoni /* Add this number of RX descriptors as non occupied (ready to 32766a20c175SThomas Petazzoni * get packets) 32776a20c175SThomas Petazzoni */ 3278c5aff182SThomas Petazzoni mvneta_rxq_non_occup_desc_add(pp, rxq, i); 3279c5aff182SThomas Petazzoni 3280c5aff182SThomas Petazzoni return i; 3281c5aff182SThomas Petazzoni } 3282c5aff182SThomas Petazzoni 3283c5aff182SThomas Petazzoni /* Free all packets pending transmit from all TXQs and reset TX port */ 3284c5aff182SThomas Petazzoni static void mvneta_tx_reset(struct mvneta_port *pp) 3285c5aff182SThomas Petazzoni { 3286c5aff182SThomas Petazzoni int queue; 3287c5aff182SThomas Petazzoni 32889672850bSEzequiel Garcia /* free the skb's in the tx ring */ 3289c5aff182SThomas Petazzoni for (queue = 0; queue < txq_number; queue++) 3290c5aff182SThomas Petazzoni mvneta_txq_done_force(pp, &pp->txqs[queue]); 3291c5aff182SThomas Petazzoni 3292c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_PORT_TX_RESET, MVNETA_PORT_TX_DMA_RESET); 3293c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_PORT_TX_RESET, 0); 3294c5aff182SThomas Petazzoni } 3295c5aff182SThomas Petazzoni 3296c5aff182SThomas Petazzoni static void mvneta_rx_reset(struct mvneta_port *pp) 3297c5aff182SThomas Petazzoni { 3298c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_PORT_RX_RESET, MVNETA_PORT_RX_DMA_RESET); 3299c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_PORT_RX_RESET, 0); 3300c5aff182SThomas Petazzoni } 3301c5aff182SThomas Petazzoni 3302c5aff182SThomas Petazzoni /* Rx/Tx queue initialization/cleanup methods */ 3303c5aff182SThomas Petazzoni 33044a188a63SJisheng Zhang static int mvneta_rxq_sw_init(struct mvneta_port *pp, 3305c5aff182SThomas Petazzoni struct mvneta_rx_queue *rxq) 3306c5aff182SThomas Petazzoni { 3307c5aff182SThomas Petazzoni rxq->size = pp->rx_ring_size; 3308c5aff182SThomas Petazzoni 3309c5aff182SThomas Petazzoni /* Allocate memory for RX descriptors */ 3310c5aff182SThomas Petazzoni rxq->descs = dma_alloc_coherent(pp->dev->dev.parent, 3311c5aff182SThomas Petazzoni rxq->size * MVNETA_DESC_ALIGNED_SIZE, 3312c5aff182SThomas Petazzoni &rxq->descs_phys, GFP_KERNEL); 3313f95936ccSMarkus Elfring if (!rxq->descs) 3314c5aff182SThomas Petazzoni return -ENOMEM; 3315c5aff182SThomas Petazzoni 3316c5aff182SThomas Petazzoni rxq->last_desc = rxq->size - 1; 3317c5aff182SThomas Petazzoni 33184a188a63SJisheng Zhang return 0; 33194a188a63SJisheng Zhang } 33204a188a63SJisheng Zhang 33214a188a63SJisheng Zhang static void mvneta_rxq_hw_init(struct mvneta_port *pp, 33224a188a63SJisheng Zhang struct mvneta_rx_queue *rxq) 33234a188a63SJisheng Zhang { 3324c5aff182SThomas Petazzoni /* Set Rx descriptors queue starting address */ 3325c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_RXQ_BASE_ADDR_REG(rxq->id), rxq->descs_phys); 3326c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_RXQ_SIZE_REG(rxq->id), rxq->size); 3327c5aff182SThomas Petazzoni 3328c5aff182SThomas Petazzoni /* Set coalescing pkts and time */ 3329c5aff182SThomas Petazzoni mvneta_rx_pkts_coal_set(pp, rxq, rxq->pkts_coal); 3330c5aff182SThomas Petazzoni mvneta_rx_time_coal_set(pp, rxq, rxq->time_coal); 3331c5aff182SThomas Petazzoni 3332dc35a10fSMarcin Wojtas if (!pp->bm_priv) { 3333562e2f46SYelena Krivosheev /* Set Offset */ 3334562e2f46SYelena Krivosheev mvneta_rxq_offset_set(pp, rxq, 0); 3335e735fd55SMarcin Wojtas mvneta_rxq_buf_size_set(pp, rxq, PAGE_SIZE < SZ_64K ? 33368dc9a088SLorenzo Bianconi MVNETA_MAX_RX_BUF_SIZE : 3337e735fd55SMarcin Wojtas MVNETA_RX_BUF_SIZE(pp->pkt_size)); 3338c5aff182SThomas Petazzoni mvneta_rxq_bm_disable(pp, rxq); 3339e9f64999SGregory CLEMENT mvneta_rxq_fill(pp, rxq, rxq->size); 3340dc35a10fSMarcin Wojtas } else { 3341562e2f46SYelena Krivosheev /* Set Offset */ 3342562e2f46SYelena Krivosheev mvneta_rxq_offset_set(pp, rxq, 3343562e2f46SYelena Krivosheev NET_SKB_PAD - pp->rx_offset_correction); 3344562e2f46SYelena Krivosheev 3345dc35a10fSMarcin Wojtas mvneta_rxq_bm_enable(pp, rxq); 3346562e2f46SYelena Krivosheev /* Fill RXQ with buffers from RX pool */ 3347dc35a10fSMarcin Wojtas mvneta_rxq_long_pool_set(pp, rxq); 3348dc35a10fSMarcin Wojtas mvneta_rxq_short_pool_set(pp, rxq); 3349e9f64999SGregory CLEMENT mvneta_rxq_non_occup_desc_add(pp, rxq, rxq->size); 3350dc35a10fSMarcin Wojtas } 33514a188a63SJisheng Zhang } 33524a188a63SJisheng Zhang 33534a188a63SJisheng Zhang /* Create a specified RX queue */ 33544a188a63SJisheng Zhang static int mvneta_rxq_init(struct mvneta_port *pp, 33554a188a63SJisheng Zhang struct mvneta_rx_queue *rxq) 33564a188a63SJisheng Zhang 33574a188a63SJisheng Zhang { 33584a188a63SJisheng Zhang int ret; 33594a188a63SJisheng Zhang 33604a188a63SJisheng Zhang ret = mvneta_rxq_sw_init(pp, rxq); 33614a188a63SJisheng Zhang if (ret < 0) 33624a188a63SJisheng Zhang return ret; 33634a188a63SJisheng Zhang 33644a188a63SJisheng Zhang mvneta_rxq_hw_init(pp, rxq); 3365dc35a10fSMarcin Wojtas 3366c5aff182SThomas Petazzoni return 0; 3367c5aff182SThomas Petazzoni } 3368c5aff182SThomas Petazzoni 3369c5aff182SThomas Petazzoni /* Cleanup Rx queue */ 3370c5aff182SThomas Petazzoni static void mvneta_rxq_deinit(struct mvneta_port *pp, 3371c5aff182SThomas Petazzoni struct mvneta_rx_queue *rxq) 3372c5aff182SThomas Petazzoni { 3373c5aff182SThomas Petazzoni mvneta_rxq_drop_pkts(pp, rxq); 3374c5aff182SThomas Petazzoni 3375c5aff182SThomas Petazzoni if (rxq->descs) 3376c5aff182SThomas Petazzoni dma_free_coherent(pp->dev->dev.parent, 3377c5aff182SThomas Petazzoni rxq->size * MVNETA_DESC_ALIGNED_SIZE, 3378c5aff182SThomas Petazzoni rxq->descs, 3379c5aff182SThomas Petazzoni rxq->descs_phys); 3380c5aff182SThomas Petazzoni 3381c5aff182SThomas Petazzoni rxq->descs = NULL; 3382c5aff182SThomas Petazzoni rxq->last_desc = 0; 3383c5aff182SThomas Petazzoni rxq->next_desc_to_proc = 0; 3384c5aff182SThomas Petazzoni rxq->descs_phys = 0; 3385562e2f46SYelena Krivosheev rxq->first_to_refill = 0; 3386562e2f46SYelena Krivosheev rxq->refill_num = 0; 3387c5aff182SThomas Petazzoni } 3388c5aff182SThomas Petazzoni 33894a188a63SJisheng Zhang static int mvneta_txq_sw_init(struct mvneta_port *pp, 3390c5aff182SThomas Petazzoni struct mvneta_tx_queue *txq) 3391c5aff182SThomas Petazzoni { 339250bf8cb6SGregory CLEMENT int cpu; 339350bf8cb6SGregory CLEMENT 3394c5aff182SThomas Petazzoni txq->size = pp->tx_ring_size; 3395c5aff182SThomas Petazzoni 33968eef5f97SEzequiel Garcia /* A queue must always have room for at least one skb. 33978eef5f97SEzequiel Garcia * Therefore, stop the queue when the free entries reaches 33988eef5f97SEzequiel Garcia * the maximum number of descriptors per skb. 33998eef5f97SEzequiel Garcia */ 34008eef5f97SEzequiel Garcia txq->tx_stop_threshold = txq->size - MVNETA_MAX_SKB_DESCS; 34018eef5f97SEzequiel Garcia txq->tx_wake_threshold = txq->tx_stop_threshold / 2; 34028eef5f97SEzequiel Garcia 3403c5aff182SThomas Petazzoni /* Allocate memory for TX descriptors */ 3404c5aff182SThomas Petazzoni txq->descs = dma_alloc_coherent(pp->dev->dev.parent, 3405c5aff182SThomas Petazzoni txq->size * MVNETA_DESC_ALIGNED_SIZE, 3406c5aff182SThomas Petazzoni &txq->descs_phys, GFP_KERNEL); 3407f95936ccSMarkus Elfring if (!txq->descs) 3408c5aff182SThomas Petazzoni return -ENOMEM; 3409c5aff182SThomas Petazzoni 3410c5aff182SThomas Petazzoni txq->last_desc = txq->size - 1; 3411c5aff182SThomas Petazzoni 34129e58c8b4SLorenzo Bianconi txq->buf = kmalloc_array(txq->size, sizeof(*txq->buf), GFP_KERNEL); 3413f4544e53STom Rix if (!txq->buf) 3414c5aff182SThomas Petazzoni return -ENOMEM; 34152adb719dSEzequiel Garcia 34162adb719dSEzequiel Garcia /* Allocate DMA buffers for TSO MAC/IP/TCP headers */ 34172adb719dSEzequiel Garcia txq->tso_hdrs = dma_alloc_coherent(pp->dev->dev.parent, 34182adb719dSEzequiel Garcia txq->size * TSO_HEADER_SIZE, 34192adb719dSEzequiel Garcia &txq->tso_hdrs_phys, GFP_KERNEL); 3420f4544e53STom Rix if (!txq->tso_hdrs) 34212adb719dSEzequiel Garcia return -ENOMEM; 3422c5aff182SThomas Petazzoni 342350bf8cb6SGregory CLEMENT /* Setup XPS mapping */ 3424cf9bf871SMaxime Chevallier if (pp->neta_armada3700) 3425cf9bf871SMaxime Chevallier cpu = 0; 3426cf9bf871SMaxime Chevallier else if (txq_number > 1) 342750bf8cb6SGregory CLEMENT cpu = txq->id % num_present_cpus(); 342850bf8cb6SGregory CLEMENT else 342950bf8cb6SGregory CLEMENT cpu = pp->rxq_def % num_present_cpus(); 343050bf8cb6SGregory CLEMENT cpumask_set_cpu(cpu, &txq->affinity_mask); 343150bf8cb6SGregory CLEMENT netif_set_xps_queue(pp->dev, &txq->affinity_mask, txq->id); 343250bf8cb6SGregory CLEMENT 3433c5aff182SThomas Petazzoni return 0; 3434c5aff182SThomas Petazzoni } 3435c5aff182SThomas Petazzoni 34364a188a63SJisheng Zhang static void mvneta_txq_hw_init(struct mvneta_port *pp, 34374a188a63SJisheng Zhang struct mvneta_tx_queue *txq) 34384a188a63SJisheng Zhang { 34394a188a63SJisheng Zhang /* Set maximum bandwidth for enabled TXQs */ 34404a188a63SJisheng Zhang mvreg_write(pp, MVETH_TXQ_TOKEN_CFG_REG(txq->id), 0x03ffffff); 34414a188a63SJisheng Zhang mvreg_write(pp, MVETH_TXQ_TOKEN_COUNT_REG(txq->id), 0x3fffffff); 34424a188a63SJisheng Zhang 34434a188a63SJisheng Zhang /* Set Tx descriptors queue starting address */ 34444a188a63SJisheng Zhang mvreg_write(pp, MVNETA_TXQ_BASE_ADDR_REG(txq->id), txq->descs_phys); 34454a188a63SJisheng Zhang mvreg_write(pp, MVNETA_TXQ_SIZE_REG(txq->id), txq->size); 34464a188a63SJisheng Zhang 34474a188a63SJisheng Zhang mvneta_tx_done_pkts_coal_set(pp, txq, txq->done_pkts_coal); 34484a188a63SJisheng Zhang } 34494a188a63SJisheng Zhang 34504a188a63SJisheng Zhang /* Create and initialize a tx queue */ 34514a188a63SJisheng Zhang static int mvneta_txq_init(struct mvneta_port *pp, 34524a188a63SJisheng Zhang struct mvneta_tx_queue *txq) 34534a188a63SJisheng Zhang { 34544a188a63SJisheng Zhang int ret; 34554a188a63SJisheng Zhang 34564a188a63SJisheng Zhang ret = mvneta_txq_sw_init(pp, txq); 34574a188a63SJisheng Zhang if (ret < 0) 34584a188a63SJisheng Zhang return ret; 34594a188a63SJisheng Zhang 34604a188a63SJisheng Zhang mvneta_txq_hw_init(pp, txq); 34614a188a63SJisheng Zhang 34624a188a63SJisheng Zhang return 0; 34634a188a63SJisheng Zhang } 34644a188a63SJisheng Zhang 3465c5aff182SThomas Petazzoni /* Free allocated resources when mvneta_txq_init() fails to allocate memory*/ 34664a188a63SJisheng Zhang static void mvneta_txq_sw_deinit(struct mvneta_port *pp, 3467c5aff182SThomas Petazzoni struct mvneta_tx_queue *txq) 3468c5aff182SThomas Petazzoni { 3469a29b6235SMarcin Wojtas struct netdev_queue *nq = netdev_get_tx_queue(pp->dev, txq->id); 3470a29b6235SMarcin Wojtas 34719e58c8b4SLorenzo Bianconi kfree(txq->buf); 3472c5aff182SThomas Petazzoni 34732adb719dSEzequiel Garcia if (txq->tso_hdrs) 34742adb719dSEzequiel Garcia dma_free_coherent(pp->dev->dev.parent, 34752adb719dSEzequiel Garcia txq->size * TSO_HEADER_SIZE, 34762adb719dSEzequiel Garcia txq->tso_hdrs, txq->tso_hdrs_phys); 3477c5aff182SThomas Petazzoni if (txq->descs) 3478c5aff182SThomas Petazzoni dma_free_coherent(pp->dev->dev.parent, 3479c5aff182SThomas Petazzoni txq->size * MVNETA_DESC_ALIGNED_SIZE, 3480c5aff182SThomas Petazzoni txq->descs, txq->descs_phys); 3481c5aff182SThomas Petazzoni 3482a29b6235SMarcin Wojtas netdev_tx_reset_queue(nq); 3483a29b6235SMarcin Wojtas 3484c5aff182SThomas Petazzoni txq->descs = NULL; 3485c5aff182SThomas Petazzoni txq->last_desc = 0; 3486c5aff182SThomas Petazzoni txq->next_desc_to_proc = 0; 3487c5aff182SThomas Petazzoni txq->descs_phys = 0; 34884a188a63SJisheng Zhang } 3489c5aff182SThomas Petazzoni 34904a188a63SJisheng Zhang static void mvneta_txq_hw_deinit(struct mvneta_port *pp, 34914a188a63SJisheng Zhang struct mvneta_tx_queue *txq) 34924a188a63SJisheng Zhang { 3493c5aff182SThomas Petazzoni /* Set minimum bandwidth for disabled TXQs */ 3494c5aff182SThomas Petazzoni mvreg_write(pp, MVETH_TXQ_TOKEN_CFG_REG(txq->id), 0); 3495c5aff182SThomas Petazzoni mvreg_write(pp, MVETH_TXQ_TOKEN_COUNT_REG(txq->id), 0); 3496c5aff182SThomas Petazzoni 3497c5aff182SThomas Petazzoni /* Set Tx descriptors queue starting address and size */ 3498c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_TXQ_BASE_ADDR_REG(txq->id), 0); 3499c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_TXQ_SIZE_REG(txq->id), 0); 3500c5aff182SThomas Petazzoni } 3501c5aff182SThomas Petazzoni 35024a188a63SJisheng Zhang static void mvneta_txq_deinit(struct mvneta_port *pp, 35034a188a63SJisheng Zhang struct mvneta_tx_queue *txq) 35044a188a63SJisheng Zhang { 35054a188a63SJisheng Zhang mvneta_txq_sw_deinit(pp, txq); 35064a188a63SJisheng Zhang mvneta_txq_hw_deinit(pp, txq); 35074a188a63SJisheng Zhang } 35084a188a63SJisheng Zhang 3509c5aff182SThomas Petazzoni /* Cleanup all Tx queues */ 3510c5aff182SThomas Petazzoni static void mvneta_cleanup_txqs(struct mvneta_port *pp) 3511c5aff182SThomas Petazzoni { 3512c5aff182SThomas Petazzoni int queue; 3513c5aff182SThomas Petazzoni 3514c5aff182SThomas Petazzoni for (queue = 0; queue < txq_number; queue++) 3515c5aff182SThomas Petazzoni mvneta_txq_deinit(pp, &pp->txqs[queue]); 3516c5aff182SThomas Petazzoni } 3517c5aff182SThomas Petazzoni 3518c5aff182SThomas Petazzoni /* Cleanup all Rx queues */ 3519c5aff182SThomas Petazzoni static void mvneta_cleanup_rxqs(struct mvneta_port *pp) 3520c5aff182SThomas Petazzoni { 35212dcf75e2SGregory CLEMENT int queue; 35222dcf75e2SGregory CLEMENT 3523ca5902a6SYelena Krivosheev for (queue = 0; queue < rxq_number; queue++) 35242dcf75e2SGregory CLEMENT mvneta_rxq_deinit(pp, &pp->rxqs[queue]); 3525c5aff182SThomas Petazzoni } 3526c5aff182SThomas Petazzoni 3527c5aff182SThomas Petazzoni 3528c5aff182SThomas Petazzoni /* Init all Rx queues */ 3529c5aff182SThomas Petazzoni static int mvneta_setup_rxqs(struct mvneta_port *pp) 3530c5aff182SThomas Petazzoni { 35312dcf75e2SGregory CLEMENT int queue; 35322dcf75e2SGregory CLEMENT 35332dcf75e2SGregory CLEMENT for (queue = 0; queue < rxq_number; queue++) { 35342dcf75e2SGregory CLEMENT int err = mvneta_rxq_init(pp, &pp->rxqs[queue]); 35352dcf75e2SGregory CLEMENT 3536c5aff182SThomas Petazzoni if (err) { 3537c5aff182SThomas Petazzoni netdev_err(pp->dev, "%s: can't create rxq=%d\n", 35382dcf75e2SGregory CLEMENT __func__, queue); 3539c5aff182SThomas Petazzoni mvneta_cleanup_rxqs(pp); 3540c5aff182SThomas Petazzoni return err; 3541c5aff182SThomas Petazzoni } 35422dcf75e2SGregory CLEMENT } 3543c5aff182SThomas Petazzoni 3544c5aff182SThomas Petazzoni return 0; 3545c5aff182SThomas Petazzoni } 3546c5aff182SThomas Petazzoni 3547c5aff182SThomas Petazzoni /* Init all tx queues */ 3548c5aff182SThomas Petazzoni static int mvneta_setup_txqs(struct mvneta_port *pp) 3549c5aff182SThomas Petazzoni { 3550c5aff182SThomas Petazzoni int queue; 3551c5aff182SThomas Petazzoni 3552c5aff182SThomas Petazzoni for (queue = 0; queue < txq_number; queue++) { 3553c5aff182SThomas Petazzoni int err = mvneta_txq_init(pp, &pp->txqs[queue]); 3554c5aff182SThomas Petazzoni if (err) { 3555c5aff182SThomas Petazzoni netdev_err(pp->dev, "%s: can't create txq=%d\n", 3556c5aff182SThomas Petazzoni __func__, queue); 3557c5aff182SThomas Petazzoni mvneta_cleanup_txqs(pp); 3558c5aff182SThomas Petazzoni return err; 3559c5aff182SThomas Petazzoni } 3560c5aff182SThomas Petazzoni } 3561c5aff182SThomas Petazzoni 3562c5aff182SThomas Petazzoni return 0; 3563c5aff182SThomas Petazzoni } 3564c5aff182SThomas Petazzoni 3565b4748553SSascha Hauer static int mvneta_comphy_init(struct mvneta_port *pp, phy_interface_t interface) 3566031b922bSMarek Behún { 3567031b922bSMarek Behún int ret; 3568031b922bSMarek Behún 3569b4748553SSascha Hauer ret = phy_set_mode_ext(pp->comphy, PHY_MODE_ETHERNET, interface); 3570031b922bSMarek Behún if (ret) 3571031b922bSMarek Behún return ret; 3572031b922bSMarek Behún 3573031b922bSMarek Behún return phy_power_on(pp->comphy); 3574031b922bSMarek Behún } 3575031b922bSMarek Behún 3576b4748553SSascha Hauer static int mvneta_config_interface(struct mvneta_port *pp, 3577b4748553SSascha Hauer phy_interface_t interface) 3578b4748553SSascha Hauer { 3579b4748553SSascha Hauer int ret = 0; 3580b4748553SSascha Hauer 3581b4748553SSascha Hauer if (pp->comphy) { 3582b4748553SSascha Hauer if (interface == PHY_INTERFACE_MODE_SGMII || 3583b4748553SSascha Hauer interface == PHY_INTERFACE_MODE_1000BASEX || 3584b4748553SSascha Hauer interface == PHY_INTERFACE_MODE_2500BASEX) { 3585b4748553SSascha Hauer ret = mvneta_comphy_init(pp, interface); 3586b4748553SSascha Hauer } 3587b4748553SSascha Hauer } else { 3588b4748553SSascha Hauer switch (interface) { 3589b4748553SSascha Hauer case PHY_INTERFACE_MODE_QSGMII: 3590b4748553SSascha Hauer mvreg_write(pp, MVNETA_SERDES_CFG, 3591b4748553SSascha Hauer MVNETA_QSGMII_SERDES_PROTO); 3592b4748553SSascha Hauer break; 3593b4748553SSascha Hauer 3594b4748553SSascha Hauer case PHY_INTERFACE_MODE_SGMII: 3595b4748553SSascha Hauer case PHY_INTERFACE_MODE_1000BASEX: 3596b4748553SSascha Hauer mvreg_write(pp, MVNETA_SERDES_CFG, 3597b4748553SSascha Hauer MVNETA_SGMII_SERDES_PROTO); 3598b4748553SSascha Hauer break; 35991a642ca7SSascha Hauer 36001a642ca7SSascha Hauer case PHY_INTERFACE_MODE_2500BASEX: 36011a642ca7SSascha Hauer mvreg_write(pp, MVNETA_SERDES_CFG, 36021a642ca7SSascha Hauer MVNETA_HSGMII_SERDES_PROTO); 36031a642ca7SSascha Hauer break; 3604b4748553SSascha Hauer default: 3605d3d239dcSSascha Hauer break; 3606b4748553SSascha Hauer } 3607b4748553SSascha Hauer } 3608b4748553SSascha Hauer 3609b4748553SSascha Hauer pp->phy_interface = interface; 3610b4748553SSascha Hauer 3611b4748553SSascha Hauer return ret; 3612b4748553SSascha Hauer } 3613b4748553SSascha Hauer 3614c5aff182SThomas Petazzoni static void mvneta_start_dev(struct mvneta_port *pp) 3615c5aff182SThomas Petazzoni { 36166b125d63SGregory CLEMENT int cpu; 361712bb03b4SMaxime Ripard 3618b4748553SSascha Hauer WARN_ON(mvneta_config_interface(pp, pp->phy_interface)); 3619a10c1c81SRussell King 3620c5aff182SThomas Petazzoni mvneta_max_rx_size_set(pp, pp->pkt_size); 3621c5aff182SThomas Petazzoni mvneta_txq_max_tx_size_set(pp, pp->pkt_size); 3622c5aff182SThomas Petazzoni 3623c5aff182SThomas Petazzoni /* start the Rx/Tx activity */ 3624c5aff182SThomas Petazzoni mvneta_port_enable(pp); 3625c5aff182SThomas Petazzoni 36262636ac3cSMarcin Wojtas if (!pp->neta_armada3700) { 3627c5aff182SThomas Petazzoni /* Enable polling on the port */ 3628129219e4SGregory CLEMENT for_each_online_cpu(cpu) { 36292636ac3cSMarcin Wojtas struct mvneta_pcpu_port *port = 36302636ac3cSMarcin Wojtas per_cpu_ptr(pp->ports, cpu); 363112bb03b4SMaxime Ripard 363212bb03b4SMaxime Ripard napi_enable(&port->napi); 363312bb03b4SMaxime Ripard } 36342636ac3cSMarcin Wojtas } else { 36352636ac3cSMarcin Wojtas napi_enable(&pp->napi); 36362636ac3cSMarcin Wojtas } 3637c5aff182SThomas Petazzoni 36382dcf75e2SGregory CLEMENT /* Unmask interrupts. It has to be done from each CPU */ 36396b125d63SGregory CLEMENT on_each_cpu(mvneta_percpu_unmask_interrupt, pp, true); 36406b125d63SGregory CLEMENT 3641898b2970SStas Sergeev mvreg_write(pp, MVNETA_INTR_MISC_MASK, 3642898b2970SStas Sergeev MVNETA_CAUSE_PHY_STATUS_CHANGE | 3643856b2cc5SRussell King MVNETA_CAUSE_LINK_CHANGE); 3644c5aff182SThomas Petazzoni 3645503f9aa9SRussell King phylink_start(pp->phylink); 364661b5cc20SDaniel González Cabanelas 36475ba2254bSJisheng Zhang /* We may have called phylink_speed_down before */ 364861b5cc20SDaniel González Cabanelas phylink_speed_up(pp->phylink); 364961b5cc20SDaniel González Cabanelas 3650c5aff182SThomas Petazzoni netif_tx_start_all_queues(pp->dev); 365162a502ccSLorenzo Bianconi 365262a502ccSLorenzo Bianconi clear_bit(__MVNETA_DOWN, &pp->state); 3653c5aff182SThomas Petazzoni } 3654c5aff182SThomas Petazzoni 3655c5aff182SThomas Petazzoni static void mvneta_stop_dev(struct mvneta_port *pp) 3656c5aff182SThomas Petazzoni { 365712bb03b4SMaxime Ripard unsigned int cpu; 365812bb03b4SMaxime Ripard 365962a502ccSLorenzo Bianconi set_bit(__MVNETA_DOWN, &pp->state); 366062a502ccSLorenzo Bianconi 366161b5cc20SDaniel González Cabanelas if (device_may_wakeup(&pp->dev->dev)) 366261b5cc20SDaniel González Cabanelas phylink_speed_down(pp->phylink, false); 366361b5cc20SDaniel González Cabanelas 3664503f9aa9SRussell King phylink_stop(pp->phylink); 3665c5aff182SThomas Petazzoni 36662636ac3cSMarcin Wojtas if (!pp->neta_armada3700) { 3667129219e4SGregory CLEMENT for_each_online_cpu(cpu) { 36682636ac3cSMarcin Wojtas struct mvneta_pcpu_port *port = 36692636ac3cSMarcin Wojtas per_cpu_ptr(pp->ports, cpu); 367012bb03b4SMaxime Ripard 367112bb03b4SMaxime Ripard napi_disable(&port->napi); 367212bb03b4SMaxime Ripard } 36732636ac3cSMarcin Wojtas } else { 36742636ac3cSMarcin Wojtas napi_disable(&pp->napi); 36752636ac3cSMarcin Wojtas } 3676c5aff182SThomas Petazzoni 3677c5aff182SThomas Petazzoni netif_carrier_off(pp->dev); 3678c5aff182SThomas Petazzoni 3679c5aff182SThomas Petazzoni mvneta_port_down(pp); 3680c5aff182SThomas Petazzoni netif_tx_stop_all_queues(pp->dev); 3681c5aff182SThomas Petazzoni 3682c5aff182SThomas Petazzoni /* Stop the port activity */ 3683c5aff182SThomas Petazzoni mvneta_port_disable(pp); 3684c5aff182SThomas Petazzoni 3685c5aff182SThomas Petazzoni /* Clear all ethernet port interrupts */ 3686db488c10SGregory CLEMENT on_each_cpu(mvneta_percpu_clear_intr_cause, pp, true); 3687c5aff182SThomas Petazzoni 3688c5aff182SThomas Petazzoni /* Mask all ethernet port interrupts */ 3689db488c10SGregory CLEMENT on_each_cpu(mvneta_percpu_mask_interrupt, pp, true); 3690c5aff182SThomas Petazzoni 3691c5aff182SThomas Petazzoni mvneta_tx_reset(pp); 3692c5aff182SThomas Petazzoni mvneta_rx_reset(pp); 3693a10c1c81SRussell King 3694a10c1c81SRussell King WARN_ON(phy_power_off(pp->comphy)); 3695c5aff182SThomas Petazzoni } 3696c5aff182SThomas Petazzoni 3697db5dd0dbSMarcin Wojtas static void mvneta_percpu_enable(void *arg) 3698db5dd0dbSMarcin Wojtas { 3699db5dd0dbSMarcin Wojtas struct mvneta_port *pp = arg; 3700db5dd0dbSMarcin Wojtas 3701db5dd0dbSMarcin Wojtas enable_percpu_irq(pp->dev->irq, IRQ_TYPE_NONE); 3702db5dd0dbSMarcin Wojtas } 3703db5dd0dbSMarcin Wojtas 3704db5dd0dbSMarcin Wojtas static void mvneta_percpu_disable(void *arg) 3705db5dd0dbSMarcin Wojtas { 3706db5dd0dbSMarcin Wojtas struct mvneta_port *pp = arg; 3707db5dd0dbSMarcin Wojtas 3708db5dd0dbSMarcin Wojtas disable_percpu_irq(pp->dev->irq); 3709db5dd0dbSMarcin Wojtas } 3710db5dd0dbSMarcin Wojtas 3711c5aff182SThomas Petazzoni /* Change the device mtu */ 3712c5aff182SThomas Petazzoni static int mvneta_change_mtu(struct net_device *dev, int mtu) 3713c5aff182SThomas Petazzoni { 3714c5aff182SThomas Petazzoni struct mvneta_port *pp = netdev_priv(dev); 3715c5aff182SThomas Petazzoni int ret; 3716c5aff182SThomas Petazzoni 37175777987eSJarod Wilson if (!IS_ALIGNED(MVNETA_RX_PKT_SIZE(mtu), 8)) { 37185777987eSJarod Wilson netdev_info(dev, "Illegal MTU value %d, rounding to %d\n", 37195777987eSJarod Wilson mtu, ALIGN(MVNETA_RX_PKT_SIZE(mtu), 8)); 37205777987eSJarod Wilson mtu = ALIGN(MVNETA_RX_PKT_SIZE(mtu), 8); 37215777987eSJarod Wilson } 3722c5aff182SThomas Petazzoni 37230db51da7SLorenzo Bianconi if (pp->xdp_prog && mtu > MVNETA_MAX_RX_BUF_SIZE) { 37240db51da7SLorenzo Bianconi netdev_info(dev, "Illegal MTU value %d for XDP mode\n", mtu); 37250db51da7SLorenzo Bianconi return -EINVAL; 37260db51da7SLorenzo Bianconi } 37270db51da7SLorenzo Bianconi 3728c5aff182SThomas Petazzoni dev->mtu = mtu; 3729c5aff182SThomas Petazzoni 3730b65657fcSSimon Guinot if (!netif_running(dev)) { 3731dc35a10fSMarcin Wojtas if (pp->bm_priv) 3732dc35a10fSMarcin Wojtas mvneta_bm_update_mtu(pp, mtu); 3733dc35a10fSMarcin Wojtas 3734b65657fcSSimon Guinot netdev_update_features(dev); 3735c5aff182SThomas Petazzoni return 0; 3736b65657fcSSimon Guinot } 3737c5aff182SThomas Petazzoni 37386a20c175SThomas Petazzoni /* The interface is running, so we have to force a 3739a92dbd96SEzequiel Garcia * reallocation of the queues 3740c5aff182SThomas Petazzoni */ 3741c5aff182SThomas Petazzoni mvneta_stop_dev(pp); 3742db5dd0dbSMarcin Wojtas on_each_cpu(mvneta_percpu_disable, pp, true); 3743c5aff182SThomas Petazzoni 3744c5aff182SThomas Petazzoni mvneta_cleanup_txqs(pp); 3745c5aff182SThomas Petazzoni mvneta_cleanup_rxqs(pp); 3746c5aff182SThomas Petazzoni 3747dc35a10fSMarcin Wojtas if (pp->bm_priv) 3748dc35a10fSMarcin Wojtas mvneta_bm_update_mtu(pp, mtu); 3749dc35a10fSMarcin Wojtas 3750a92dbd96SEzequiel Garcia pp->pkt_size = MVNETA_RX_PKT_SIZE(dev->mtu); 3751c5aff182SThomas Petazzoni 3752c5aff182SThomas Petazzoni ret = mvneta_setup_rxqs(pp); 3753c5aff182SThomas Petazzoni if (ret) { 3754a92dbd96SEzequiel Garcia netdev_err(dev, "unable to setup rxqs after MTU change\n"); 3755c5aff182SThomas Petazzoni return ret; 3756c5aff182SThomas Petazzoni } 3757c5aff182SThomas Petazzoni 3758a92dbd96SEzequiel Garcia ret = mvneta_setup_txqs(pp); 3759a92dbd96SEzequiel Garcia if (ret) { 3760a92dbd96SEzequiel Garcia netdev_err(dev, "unable to setup txqs after MTU change\n"); 3761a92dbd96SEzequiel Garcia return ret; 3762a92dbd96SEzequiel Garcia } 3763c5aff182SThomas Petazzoni 3764db5dd0dbSMarcin Wojtas on_each_cpu(mvneta_percpu_enable, pp, true); 3765c5aff182SThomas Petazzoni mvneta_start_dev(pp); 3766c5aff182SThomas Petazzoni 3767b65657fcSSimon Guinot netdev_update_features(dev); 3768b65657fcSSimon Guinot 3769c5aff182SThomas Petazzoni return 0; 3770c5aff182SThomas Petazzoni } 3771c5aff182SThomas Petazzoni 3772b65657fcSSimon Guinot static netdev_features_t mvneta_fix_features(struct net_device *dev, 3773b65657fcSSimon Guinot netdev_features_t features) 3774b65657fcSSimon Guinot { 3775b65657fcSSimon Guinot struct mvneta_port *pp = netdev_priv(dev); 3776b65657fcSSimon Guinot 3777b65657fcSSimon Guinot if (pp->tx_csum_limit && dev->mtu > pp->tx_csum_limit) { 3778b65657fcSSimon Guinot features &= ~(NETIF_F_IP_CSUM | NETIF_F_TSO); 3779b65657fcSSimon Guinot netdev_info(dev, 3780b65657fcSSimon Guinot "Disable IP checksum for MTU greater than %dB\n", 3781b65657fcSSimon Guinot pp->tx_csum_limit); 3782b65657fcSSimon Guinot } 3783b65657fcSSimon Guinot 3784b65657fcSSimon Guinot return features; 3785b65657fcSSimon Guinot } 3786b65657fcSSimon Guinot 37878cc3e439SThomas Petazzoni /* Get mac address */ 37888cc3e439SThomas Petazzoni static void mvneta_get_mac_addr(struct mvneta_port *pp, unsigned char *addr) 37898cc3e439SThomas Petazzoni { 37908cc3e439SThomas Petazzoni u32 mac_addr_l, mac_addr_h; 37918cc3e439SThomas Petazzoni 37928cc3e439SThomas Petazzoni mac_addr_l = mvreg_read(pp, MVNETA_MAC_ADDR_LOW); 37938cc3e439SThomas Petazzoni mac_addr_h = mvreg_read(pp, MVNETA_MAC_ADDR_HIGH); 37948cc3e439SThomas Petazzoni addr[0] = (mac_addr_h >> 24) & 0xFF; 37958cc3e439SThomas Petazzoni addr[1] = (mac_addr_h >> 16) & 0xFF; 37968cc3e439SThomas Petazzoni addr[2] = (mac_addr_h >> 8) & 0xFF; 37978cc3e439SThomas Petazzoni addr[3] = mac_addr_h & 0xFF; 37988cc3e439SThomas Petazzoni addr[4] = (mac_addr_l >> 8) & 0xFF; 37998cc3e439SThomas Petazzoni addr[5] = mac_addr_l & 0xFF; 38008cc3e439SThomas Petazzoni } 38018cc3e439SThomas Petazzoni 3802c5aff182SThomas Petazzoni /* Handle setting mac address */ 3803c5aff182SThomas Petazzoni static int mvneta_set_mac_addr(struct net_device *dev, void *addr) 3804c5aff182SThomas Petazzoni { 3805c5aff182SThomas Petazzoni struct mvneta_port *pp = netdev_priv(dev); 3806e68de360SEzequiel Garcia struct sockaddr *sockaddr = addr; 3807e68de360SEzequiel Garcia int ret; 3808c5aff182SThomas Petazzoni 3809e68de360SEzequiel Garcia ret = eth_prepare_mac_addr_change(dev, addr); 3810e68de360SEzequiel Garcia if (ret < 0) 3811e68de360SEzequiel Garcia return ret; 3812c5aff182SThomas Petazzoni /* Remove previous address table entry */ 3813c5aff182SThomas Petazzoni mvneta_mac_addr_set(pp, dev->dev_addr, -1); 3814c5aff182SThomas Petazzoni 3815c5aff182SThomas Petazzoni /* Set new addr in hw */ 381690b74c01SGregory CLEMENT mvneta_mac_addr_set(pp, sockaddr->sa_data, pp->rxq_def); 3817c5aff182SThomas Petazzoni 3818e68de360SEzequiel Garcia eth_commit_mac_addr_change(dev, addr); 3819c5aff182SThomas Petazzoni return 0; 3820c5aff182SThomas Petazzoni } 3821c5aff182SThomas Petazzoni 382244cc27e4SIoana Ciornei static void mvneta_validate(struct phylink_config *config, 382344cc27e4SIoana Ciornei unsigned long *supported, 3824503f9aa9SRussell King struct phylink_link_state *state) 3825503f9aa9SRussell King { 3826c762b7faSRussell King (Oracle) /* We only support QSGMII, SGMII, 802.3z and RGMII modes. 3827c762b7faSRussell King (Oracle) * When in 802.3z mode, we must have AN enabled: 3828c762b7faSRussell King (Oracle) * "Bit 2 Field InBandAnEn In-band Auto-Negotiation enable. ... 3829c762b7faSRussell King (Oracle) * When <PortType> = 1 (1000BASE-X) this field must be set to 1." 3830c762b7faSRussell King (Oracle) */ 3831d9ca7280SRussell King (Oracle) if (phy_interface_mode_is_8023z(state->interface) && 3832d9ca7280SRussell King (Oracle) !phylink_test(state->advertising, Autoneg)) { 38334973056cSSean Anderson linkmode_zero(supported); 3834503f9aa9SRussell King return; 3835503f9aa9SRussell King } 3836503f9aa9SRussell King 383702a0988bSRussell King (Oracle) phylink_generic_validate(config, supported, state); 3838503f9aa9SRussell King } 3839503f9aa9SRussell King 3840d46b7e4fSRussell King static void mvneta_mac_pcs_get_state(struct phylink_config *config, 3841503f9aa9SRussell King struct phylink_link_state *state) 3842c5aff182SThomas Petazzoni { 384344cc27e4SIoana Ciornei struct net_device *ndev = to_net_dev(config->dev); 3844c5aff182SThomas Petazzoni struct mvneta_port *pp = netdev_priv(ndev); 3845503f9aa9SRussell King u32 gmac_stat; 3846c5aff182SThomas Petazzoni 3847503f9aa9SRussell King gmac_stat = mvreg_read(pp, MVNETA_GMAC_STATUS); 3848503f9aa9SRussell King 3849503f9aa9SRussell King if (gmac_stat & MVNETA_GMAC_SPEED_1000) 3850a10c1c81SRussell King state->speed = 3851a10c1c81SRussell King state->interface == PHY_INTERFACE_MODE_2500BASEX ? 3852a10c1c81SRussell King SPEED_2500 : SPEED_1000; 3853503f9aa9SRussell King else if (gmac_stat & MVNETA_GMAC_SPEED_100) 3854503f9aa9SRussell King state->speed = SPEED_100; 3855503f9aa9SRussell King else 3856503f9aa9SRussell King state->speed = SPEED_10; 3857503f9aa9SRussell King 3858503f9aa9SRussell King state->an_complete = !!(gmac_stat & MVNETA_GMAC_AN_COMPLETE); 3859503f9aa9SRussell King state->link = !!(gmac_stat & MVNETA_GMAC_LINK_UP); 3860503f9aa9SRussell King state->duplex = !!(gmac_stat & MVNETA_GMAC_FULL_DUPLEX); 3861503f9aa9SRussell King 3862503f9aa9SRussell King state->pause = 0; 38634932a918SRussell King if (gmac_stat & MVNETA_GMAC_RX_FLOW_CTRL_ENABLE) 38644932a918SRussell King state->pause |= MLO_PAUSE_RX; 38654932a918SRussell King if (gmac_stat & MVNETA_GMAC_TX_FLOW_CTRL_ENABLE) 38664932a918SRussell King state->pause |= MLO_PAUSE_TX; 3867503f9aa9SRussell King } 3868503f9aa9SRussell King 386944cc27e4SIoana Ciornei static void mvneta_mac_an_restart(struct phylink_config *config) 387022f4bf8aSRussell King { 387144cc27e4SIoana Ciornei struct net_device *ndev = to_net_dev(config->dev); 387222f4bf8aSRussell King struct mvneta_port *pp = netdev_priv(ndev); 387322f4bf8aSRussell King u32 gmac_an = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG); 387422f4bf8aSRussell King 387522f4bf8aSRussell King mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, 387622f4bf8aSRussell King gmac_an | MVNETA_GMAC_INBAND_RESTART_AN); 387722f4bf8aSRussell King mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, 387822f4bf8aSRussell King gmac_an & ~MVNETA_GMAC_INBAND_RESTART_AN); 387922f4bf8aSRussell King } 388022f4bf8aSRussell King 388144cc27e4SIoana Ciornei static void mvneta_mac_config(struct phylink_config *config, unsigned int mode, 3882503f9aa9SRussell King const struct phylink_link_state *state) 3883503f9aa9SRussell King { 388444cc27e4SIoana Ciornei struct net_device *ndev = to_net_dev(config->dev); 3885503f9aa9SRussell King struct mvneta_port *pp = netdev_priv(ndev); 388622f4bf8aSRussell King u32 new_ctrl0, gmac_ctrl0 = mvreg_read(pp, MVNETA_GMAC_CTRL_0); 3887503f9aa9SRussell King u32 new_ctrl2, gmac_ctrl2 = mvreg_read(pp, MVNETA_GMAC_CTRL_2); 3888da58a931SMaxime Chevallier u32 new_ctrl4, gmac_ctrl4 = mvreg_read(pp, MVNETA_GMAC_CTRL_4); 3889503f9aa9SRussell King u32 new_clk, gmac_clk = mvreg_read(pp, MVNETA_GMAC_CLOCK_DIVIDER); 3890503f9aa9SRussell King u32 new_an, gmac_an = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG); 3891503f9aa9SRussell King 389222f4bf8aSRussell King new_ctrl0 = gmac_ctrl0 & ~MVNETA_GMAC0_PORT_1000BASE_X; 389332699954SRussell King new_ctrl2 = gmac_ctrl2 & ~(MVNETA_GMAC2_INBAND_AN_ENABLE | 389432699954SRussell King MVNETA_GMAC2_PORT_RESET); 3895da58a931SMaxime Chevallier new_ctrl4 = gmac_ctrl4 & ~(MVNETA_GMAC4_SHORT_PREAMBLE_ENABLE); 3896503f9aa9SRussell King new_clk = gmac_clk & ~MVNETA_GMAC_1MS_CLOCK_ENABLE; 3897503f9aa9SRussell King new_an = gmac_an & ~(MVNETA_GMAC_INBAND_AN_ENABLE | 3898503f9aa9SRussell King MVNETA_GMAC_INBAND_RESTART_AN | 3899503f9aa9SRussell King MVNETA_GMAC_AN_SPEED_EN | 390022f4bf8aSRussell King MVNETA_GMAC_ADVERT_SYM_FLOW_CTRL | 3901503f9aa9SRussell King MVNETA_GMAC_AN_FLOW_CTRL_EN | 3902503f9aa9SRussell King MVNETA_GMAC_AN_DUPLEX_EN); 3903c5aff182SThomas Petazzoni 390432699954SRussell King /* Even though it might look weird, when we're configured in 390532699954SRussell King * SGMII or QSGMII mode, the RGMII bit needs to be set. 390632699954SRussell King */ 390732699954SRussell King new_ctrl2 |= MVNETA_GMAC2_PORT_RGMII; 390832699954SRussell King 390932699954SRussell King if (state->interface == PHY_INTERFACE_MODE_QSGMII || 391022f4bf8aSRussell King state->interface == PHY_INTERFACE_MODE_SGMII || 391122f4bf8aSRussell King phy_interface_mode_is_8023z(state->interface)) 391232699954SRussell King new_ctrl2 |= MVNETA_GMAC2_PCS_ENABLE; 391332699954SRussell King 39144932a918SRussell King if (phylink_test(state->advertising, Pause)) 39154932a918SRussell King new_an |= MVNETA_GMAC_ADVERT_SYM_FLOW_CTRL; 39164932a918SRussell King 3917503f9aa9SRussell King if (!phylink_autoneg_inband(mode)) { 3918ff03f0b1SRussell King /* Phy or fixed speed - nothing to do, leave the 3919ff03f0b1SRussell King * configured speed, duplex and flow control as-is. 3920ff03f0b1SRussell King */ 392122f4bf8aSRussell King } else if (state->interface == PHY_INTERFACE_MODE_SGMII) { 3922503f9aa9SRussell King /* SGMII mode receives the state from the PHY */ 3923503f9aa9SRussell King new_ctrl2 |= MVNETA_GMAC2_INBAND_AN_ENABLE; 3924503f9aa9SRussell King new_clk |= MVNETA_GMAC_1MS_CLOCK_ENABLE; 3925503f9aa9SRussell King new_an = (new_an & ~(MVNETA_GMAC_FORCE_LINK_DOWN | 3926ff03f0b1SRussell King MVNETA_GMAC_FORCE_LINK_PASS | 3927ff03f0b1SRussell King MVNETA_GMAC_CONFIG_MII_SPEED | 3928ff03f0b1SRussell King MVNETA_GMAC_CONFIG_GMII_SPEED | 3929ff03f0b1SRussell King MVNETA_GMAC_CONFIG_FULL_DUPLEX)) | 3930503f9aa9SRussell King MVNETA_GMAC_INBAND_AN_ENABLE | 3931503f9aa9SRussell King MVNETA_GMAC_AN_SPEED_EN | 3932503f9aa9SRussell King MVNETA_GMAC_AN_DUPLEX_EN; 393322f4bf8aSRussell King } else { 393422f4bf8aSRussell King /* 802.3z negotiation - only 1000base-X */ 393522f4bf8aSRussell King new_ctrl0 |= MVNETA_GMAC0_PORT_1000BASE_X; 393622f4bf8aSRussell King new_clk |= MVNETA_GMAC_1MS_CLOCK_ENABLE; 393722f4bf8aSRussell King new_an = (new_an & ~(MVNETA_GMAC_FORCE_LINK_DOWN | 3938ff03f0b1SRussell King MVNETA_GMAC_FORCE_LINK_PASS | 3939ff03f0b1SRussell King MVNETA_GMAC_CONFIG_MII_SPEED)) | 394022f4bf8aSRussell King MVNETA_GMAC_INBAND_AN_ENABLE | 394122f4bf8aSRussell King MVNETA_GMAC_CONFIG_GMII_SPEED | 394222f4bf8aSRussell King /* The MAC only supports FD mode */ 394322f4bf8aSRussell King MVNETA_GMAC_CONFIG_FULL_DUPLEX; 39444932a918SRussell King 39454932a918SRussell King if (state->pause & MLO_PAUSE_AN && state->an_enabled) 39464932a918SRussell King new_an |= MVNETA_GMAC_AN_FLOW_CTRL_EN; 3947c5aff182SThomas Petazzoni } 3948c5aff182SThomas Petazzoni 3949503f9aa9SRussell King /* Armada 370 documentation says we can only change the port mode 3950503f9aa9SRussell King * and in-band enable when the link is down, so force it down 3951df4a17a9SYangyang Li * while making these changes. We also do this for GMAC_CTRL2 3952df4a17a9SYangyang Li */ 395322f4bf8aSRussell King if ((new_ctrl0 ^ gmac_ctrl0) & MVNETA_GMAC0_PORT_1000BASE_X || 395422f4bf8aSRussell King (new_ctrl2 ^ gmac_ctrl2) & MVNETA_GMAC2_INBAND_AN_ENABLE || 3955503f9aa9SRussell King (new_an ^ gmac_an) & MVNETA_GMAC_INBAND_AN_ENABLE) { 3956503f9aa9SRussell King mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, 3957503f9aa9SRussell King (gmac_an & ~MVNETA_GMAC_FORCE_LINK_PASS) | 3958503f9aa9SRussell King MVNETA_GMAC_FORCE_LINK_DOWN); 3959503f9aa9SRussell King } 3960503f9aa9SRussell King 3961a10c1c81SRussell King 3962da58a931SMaxime Chevallier /* When at 2.5G, the link partner can send frames with shortened 3963da58a931SMaxime Chevallier * preambles. 3964da58a931SMaxime Chevallier */ 3965f2ca673dSRussell King if (state->interface == PHY_INTERFACE_MODE_2500BASEX) 3966da58a931SMaxime Chevallier new_ctrl4 |= MVNETA_GMAC4_SHORT_PREAMBLE_ENABLE; 3967da58a931SMaxime Chevallier 3968b4748553SSascha Hauer if (pp->phy_interface != state->interface) { 3969b4748553SSascha Hauer if (pp->comphy) 3970031b922bSMarek Behún WARN_ON(phy_power_off(pp->comphy)); 3971b4748553SSascha Hauer WARN_ON(mvneta_config_interface(pp, state->interface)); 3972031b922bSMarek Behún } 3973a10c1c81SRussell King 397422f4bf8aSRussell King if (new_ctrl0 != gmac_ctrl0) 397522f4bf8aSRussell King mvreg_write(pp, MVNETA_GMAC_CTRL_0, new_ctrl0); 3976503f9aa9SRussell King if (new_ctrl2 != gmac_ctrl2) 3977503f9aa9SRussell King mvreg_write(pp, MVNETA_GMAC_CTRL_2, new_ctrl2); 3978da58a931SMaxime Chevallier if (new_ctrl4 != gmac_ctrl4) 3979da58a931SMaxime Chevallier mvreg_write(pp, MVNETA_GMAC_CTRL_4, new_ctrl4); 3980503f9aa9SRussell King if (new_clk != gmac_clk) 3981503f9aa9SRussell King mvreg_write(pp, MVNETA_GMAC_CLOCK_DIVIDER, new_clk); 3982503f9aa9SRussell King if (new_an != gmac_an) 3983503f9aa9SRussell King mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, new_an); 398432699954SRussell King 398532699954SRussell King if (gmac_ctrl2 & MVNETA_GMAC2_PORT_RESET) { 398632699954SRussell King while ((mvreg_read(pp, MVNETA_GMAC_CTRL_2) & 398732699954SRussell King MVNETA_GMAC2_PORT_RESET) != 0) 398832699954SRussell King continue; 398932699954SRussell King } 3990503f9aa9SRussell King } 3991503f9aa9SRussell King 39926d81f451SRussell King static void mvneta_set_eee(struct mvneta_port *pp, bool enable) 39936d81f451SRussell King { 39946d81f451SRussell King u32 lpi_ctl1; 39956d81f451SRussell King 39966d81f451SRussell King lpi_ctl1 = mvreg_read(pp, MVNETA_LPI_CTRL_1); 39976d81f451SRussell King if (enable) 39986d81f451SRussell King lpi_ctl1 |= MVNETA_LPI_REQUEST_ENABLE; 39996d81f451SRussell King else 40006d81f451SRussell King lpi_ctl1 &= ~MVNETA_LPI_REQUEST_ENABLE; 40016d81f451SRussell King mvreg_write(pp, MVNETA_LPI_CTRL_1, lpi_ctl1); 40026d81f451SRussell King } 40036d81f451SRussell King 400444cc27e4SIoana Ciornei static void mvneta_mac_link_down(struct phylink_config *config, 400544cc27e4SIoana Ciornei unsigned int mode, phy_interface_t interface) 4006fc548b99SRussell King { 400744cc27e4SIoana Ciornei struct net_device *ndev = to_net_dev(config->dev); 4008fc548b99SRussell King struct mvneta_port *pp = netdev_priv(ndev); 4009fc548b99SRussell King u32 val; 4010fc548b99SRussell King 4011503f9aa9SRussell King mvneta_port_down(pp); 4012503f9aa9SRussell King 4013503f9aa9SRussell King if (!phylink_autoneg_inband(mode)) { 4014fc548b99SRussell King val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG); 4015fc548b99SRussell King val &= ~MVNETA_GMAC_FORCE_LINK_PASS; 4016fc548b99SRussell King val |= MVNETA_GMAC_FORCE_LINK_DOWN; 4017fc548b99SRussell King mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val); 4018fc548b99SRussell King } 40196d81f451SRussell King 40206d81f451SRussell King pp->eee_active = false; 40216d81f451SRussell King mvneta_set_eee(pp, false); 4022fc548b99SRussell King } 4023fc548b99SRussell King 402491a208f2SRussell King static void mvneta_mac_link_up(struct phylink_config *config, 402591a208f2SRussell King struct phy_device *phy, 402691a208f2SRussell King unsigned int mode, phy_interface_t interface, 402791a208f2SRussell King int speed, int duplex, 402891a208f2SRussell King bool tx_pause, bool rx_pause) 4029fc548b99SRussell King { 403044cc27e4SIoana Ciornei struct net_device *ndev = to_net_dev(config->dev); 4031fc548b99SRussell King struct mvneta_port *pp = netdev_priv(ndev); 4032fc548b99SRussell King u32 val; 4033fc548b99SRussell King 4034503f9aa9SRussell King if (!phylink_autoneg_inband(mode)) { 4035fc548b99SRussell King val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG); 4036ff03f0b1SRussell King val &= ~(MVNETA_GMAC_FORCE_LINK_DOWN | 4037ff03f0b1SRussell King MVNETA_GMAC_CONFIG_MII_SPEED | 4038ff03f0b1SRussell King MVNETA_GMAC_CONFIG_GMII_SPEED | 4039ff03f0b1SRussell King MVNETA_GMAC_CONFIG_FLOW_CTRL | 4040ff03f0b1SRussell King MVNETA_GMAC_CONFIG_FULL_DUPLEX); 4041fc548b99SRussell King val |= MVNETA_GMAC_FORCE_LINK_PASS; 4042ff03f0b1SRussell King 4043ff03f0b1SRussell King if (speed == SPEED_1000 || speed == SPEED_2500) 4044ff03f0b1SRussell King val |= MVNETA_GMAC_CONFIG_GMII_SPEED; 4045ff03f0b1SRussell King else if (speed == SPEED_100) 4046ff03f0b1SRussell King val |= MVNETA_GMAC_CONFIG_MII_SPEED; 4047ff03f0b1SRussell King 4048ff03f0b1SRussell King if (duplex == DUPLEX_FULL) 4049ff03f0b1SRussell King val |= MVNETA_GMAC_CONFIG_FULL_DUPLEX; 4050ff03f0b1SRussell King 4051ff03f0b1SRussell King if (tx_pause || rx_pause) 4052ff03f0b1SRussell King val |= MVNETA_GMAC_CONFIG_FLOW_CTRL; 4053ff03f0b1SRussell King 4054ff03f0b1SRussell King mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val); 4055ff03f0b1SRussell King } else { 4056ff03f0b1SRussell King /* When inband doesn't cover flow control or flow control is 4057ff03f0b1SRussell King * disabled, we need to manually configure it. This bit will 4058ff03f0b1SRussell King * only have effect if MVNETA_GMAC_AN_FLOW_CTRL_EN is unset. 4059ff03f0b1SRussell King */ 4060ff03f0b1SRussell King val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG); 4061ff03f0b1SRussell King val &= ~MVNETA_GMAC_CONFIG_FLOW_CTRL; 4062ff03f0b1SRussell King 4063ff03f0b1SRussell King if (tx_pause || rx_pause) 4064ff03f0b1SRussell King val |= MVNETA_GMAC_CONFIG_FLOW_CTRL; 4065ff03f0b1SRussell King 4066fc548b99SRussell King mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val); 4067fc548b99SRussell King } 4068fc548b99SRussell King 4069fc548b99SRussell King mvneta_port_up(pp); 40706d81f451SRussell King 40716d81f451SRussell King if (phy && pp->eee_enabled) { 40726d81f451SRussell King pp->eee_active = phy_init_eee(phy, 0) >= 0; 40736d81f451SRussell King mvneta_set_eee(pp, pp->eee_active && pp->tx_lpi_enabled); 40746d81f451SRussell King } 4075fc548b99SRussell King } 4076fc548b99SRussell King 4077503f9aa9SRussell King static const struct phylink_mac_ops mvneta_phylink_ops = { 4078503f9aa9SRussell King .validate = mvneta_validate, 4079d46b7e4fSRussell King .mac_pcs_get_state = mvneta_mac_pcs_get_state, 408022f4bf8aSRussell King .mac_an_restart = mvneta_mac_an_restart, 4081503f9aa9SRussell King .mac_config = mvneta_mac_config, 4082503f9aa9SRussell King .mac_link_down = mvneta_mac_link_down, 4083503f9aa9SRussell King .mac_link_up = mvneta_mac_link_up, 4084503f9aa9SRussell King }; 4085c5aff182SThomas Petazzoni 4086c5aff182SThomas Petazzoni static int mvneta_mdio_probe(struct mvneta_port *pp) 4087c5aff182SThomas Petazzoni { 408882960fffSJisheng Zhang struct ethtool_wolinfo wol = { .cmd = ETHTOOL_GWOL }; 4089503f9aa9SRussell King int err = phylink_of_phy_connect(pp->phylink, pp->dn, 0); 4090c5aff182SThomas Petazzoni 4091503f9aa9SRussell King if (err) 4092503f9aa9SRussell King netdev_err(pp->dev, "could not attach PHY: %d\n", err); 4093c5aff182SThomas Petazzoni 4094503f9aa9SRussell King phylink_ethtool_get_wol(pp->phylink, &wol); 409582960fffSJisheng Zhang device_set_wakeup_capable(&pp->dev->dev, !!wol.supported); 409682960fffSJisheng Zhang 409761b5cc20SDaniel González Cabanelas /* PHY WoL may be enabled but device wakeup disabled */ 409861b5cc20SDaniel González Cabanelas if (wol.supported) 409961b5cc20SDaniel González Cabanelas device_set_wakeup_enable(&pp->dev->dev, !!wol.wolopts); 410061b5cc20SDaniel González Cabanelas 4101503f9aa9SRussell King return err; 4102c5aff182SThomas Petazzoni } 4103c5aff182SThomas Petazzoni 4104c5aff182SThomas Petazzoni static void mvneta_mdio_remove(struct mvneta_port *pp) 4105c5aff182SThomas Petazzoni { 4106503f9aa9SRussell King phylink_disconnect_phy(pp->phylink); 4107c5aff182SThomas Petazzoni } 4108c5aff182SThomas Petazzoni 4109120cfa50SGregory CLEMENT /* Electing a CPU must be done in an atomic way: it should be done 4110120cfa50SGregory CLEMENT * after or before the removal/insertion of a CPU and this function is 4111120cfa50SGregory CLEMENT * not reentrant. 4112120cfa50SGregory CLEMENT */ 4113f8642885SMaxime Ripard static void mvneta_percpu_elect(struct mvneta_port *pp) 4114f8642885SMaxime Ripard { 4115cad5d847SGregory CLEMENT int elected_cpu = 0, max_cpu, cpu, i = 0; 4116f8642885SMaxime Ripard 4117cad5d847SGregory CLEMENT /* Use the cpu associated to the rxq when it is online, in all 4118cad5d847SGregory CLEMENT * the other cases, use the cpu 0 which can't be offline. 4119cad5d847SGregory CLEMENT */ 4120cad5d847SGregory CLEMENT if (cpu_online(pp->rxq_def)) 4121cad5d847SGregory CLEMENT elected_cpu = pp->rxq_def; 4122cad5d847SGregory CLEMENT 41232dcf75e2SGregory CLEMENT max_cpu = num_present_cpus(); 4124f8642885SMaxime Ripard 4125f8642885SMaxime Ripard for_each_online_cpu(cpu) { 41262dcf75e2SGregory CLEMENT int rxq_map = 0, txq_map = 0; 41272dcf75e2SGregory CLEMENT int rxq; 41282dcf75e2SGregory CLEMENT 41292dcf75e2SGregory CLEMENT for (rxq = 0; rxq < rxq_number; rxq++) 41302dcf75e2SGregory CLEMENT if ((rxq % max_cpu) == cpu) 41312dcf75e2SGregory CLEMENT rxq_map |= MVNETA_CPU_RXQ_ACCESS(rxq); 41322dcf75e2SGregory CLEMENT 4133cad5d847SGregory CLEMENT if (cpu == elected_cpu) 4134b52f6425SYangyang Li /* Map the default receive queue to the elected CPU */ 41352dcf75e2SGregory CLEMENT rxq_map |= MVNETA_CPU_RXQ_ACCESS(pp->rxq_def); 413650bf8cb6SGregory CLEMENT 413750bf8cb6SGregory CLEMENT /* We update the TX queue map only if we have one 413850bf8cb6SGregory CLEMENT * queue. In this case we associate the TX queue to 413950bf8cb6SGregory CLEMENT * the CPU bound to the default RX queue 414050bf8cb6SGregory CLEMENT */ 414150bf8cb6SGregory CLEMENT if (txq_number == 1) 4142cad5d847SGregory CLEMENT txq_map = (cpu == elected_cpu) ? 414350bf8cb6SGregory CLEMENT MVNETA_CPU_TXQ_ACCESS(1) : 0; 414450bf8cb6SGregory CLEMENT else 414550bf8cb6SGregory CLEMENT txq_map = mvreg_read(pp, MVNETA_CPU_MAP(cpu)) & 414650bf8cb6SGregory CLEMENT MVNETA_CPU_TXQ_ACCESS_ALL_MASK; 414750bf8cb6SGregory CLEMENT 41482dcf75e2SGregory CLEMENT mvreg_write(pp, MVNETA_CPU_MAP(cpu), rxq_map | txq_map); 41492dcf75e2SGregory CLEMENT 41502dcf75e2SGregory CLEMENT /* Update the interrupt mask on each CPU according the 41512dcf75e2SGregory CLEMENT * new mapping 41522dcf75e2SGregory CLEMENT */ 41532dcf75e2SGregory CLEMENT smp_call_function_single(cpu, mvneta_percpu_unmask_interrupt, 4154f8642885SMaxime Ripard pp, true); 4155f8642885SMaxime Ripard i++; 41562dcf75e2SGregory CLEMENT 4157f8642885SMaxime Ripard } 4158f8642885SMaxime Ripard }; 4159f8642885SMaxime Ripard 416084a3f4dbSSebastian Andrzej Siewior static int mvneta_cpu_online(unsigned int cpu, struct hlist_node *node) 4161f8642885SMaxime Ripard { 416284a3f4dbSSebastian Andrzej Siewior int other_cpu; 416384a3f4dbSSebastian Andrzej Siewior struct mvneta_port *pp = hlist_entry_safe(node, struct mvneta_port, 416484a3f4dbSSebastian Andrzej Siewior node_online); 4165f8642885SMaxime Ripard struct mvneta_pcpu_port *port = per_cpu_ptr(pp->ports, cpu); 4166f8642885SMaxime Ripard 4167cf9bf871SMaxime Chevallier /* Armada 3700's per-cpu interrupt for mvneta is broken, all interrupts 4168cf9bf871SMaxime Chevallier * are routed to CPU 0, so we don't need all the cpu-hotplug support 4169cf9bf871SMaxime Chevallier */ 4170cf9bf871SMaxime Chevallier if (pp->neta_armada3700) 4171cf9bf871SMaxime Chevallier return 0; 417284a3f4dbSSebastian Andrzej Siewior 4173120cfa50SGregory CLEMENT spin_lock(&pp->lock); 417484a3f4dbSSebastian Andrzej Siewior /* 417584a3f4dbSSebastian Andrzej Siewior * Configuring the driver for a new CPU while the driver is 417684a3f4dbSSebastian Andrzej Siewior * stopping is racy, so just avoid it. 4177120cfa50SGregory CLEMENT */ 4178120cfa50SGregory CLEMENT if (pp->is_stopped) { 4179120cfa50SGregory CLEMENT spin_unlock(&pp->lock); 418084a3f4dbSSebastian Andrzej Siewior return 0; 4181120cfa50SGregory CLEMENT } 4182f8642885SMaxime Ripard netif_tx_stop_all_queues(pp->dev); 4183f8642885SMaxime Ripard 418484a3f4dbSSebastian Andrzej Siewior /* 418584a3f4dbSSebastian Andrzej Siewior * We have to synchronise on tha napi of each CPU except the one 418684a3f4dbSSebastian Andrzej Siewior * just being woken up 4187f8642885SMaxime Ripard */ 4188f8642885SMaxime Ripard for_each_online_cpu(other_cpu) { 4189f8642885SMaxime Ripard if (other_cpu != cpu) { 4190f8642885SMaxime Ripard struct mvneta_pcpu_port *other_port = 4191f8642885SMaxime Ripard per_cpu_ptr(pp->ports, other_cpu); 4192f8642885SMaxime Ripard 4193f8642885SMaxime Ripard napi_synchronize(&other_port->napi); 4194f8642885SMaxime Ripard } 4195f8642885SMaxime Ripard } 4196f8642885SMaxime Ripard 4197f8642885SMaxime Ripard /* Mask all ethernet port interrupts */ 4198db488c10SGregory CLEMENT on_each_cpu(mvneta_percpu_mask_interrupt, pp, true); 4199f8642885SMaxime Ripard napi_enable(&port->napi); 4200f8642885SMaxime Ripard 420184a3f4dbSSebastian Andrzej Siewior /* 420284a3f4dbSSebastian Andrzej Siewior * Enable per-CPU interrupts on the CPU that is 42032dcf75e2SGregory CLEMENT * brought up. 42042dcf75e2SGregory CLEMENT */ 42050e28bf93SAnna-Maria Gleixner mvneta_percpu_enable(pp); 42062dcf75e2SGregory CLEMENT 420784a3f4dbSSebastian Andrzej Siewior /* 420884a3f4dbSSebastian Andrzej Siewior * Enable per-CPU interrupt on the one CPU we care 4209f8642885SMaxime Ripard * about. 4210f8642885SMaxime Ripard */ 4211f8642885SMaxime Ripard mvneta_percpu_elect(pp); 4212f8642885SMaxime Ripard 4213db488c10SGregory CLEMENT /* Unmask all ethernet port interrupts */ 4214db488c10SGregory CLEMENT on_each_cpu(mvneta_percpu_unmask_interrupt, pp, true); 4215f8642885SMaxime Ripard mvreg_write(pp, MVNETA_INTR_MISC_MASK, 4216f8642885SMaxime Ripard MVNETA_CAUSE_PHY_STATUS_CHANGE | 4217856b2cc5SRussell King MVNETA_CAUSE_LINK_CHANGE); 4218f8642885SMaxime Ripard netif_tx_start_all_queues(pp->dev); 4219120cfa50SGregory CLEMENT spin_unlock(&pp->lock); 422084a3f4dbSSebastian Andrzej Siewior return 0; 422184a3f4dbSSebastian Andrzej Siewior } 422284a3f4dbSSebastian Andrzej Siewior 422384a3f4dbSSebastian Andrzej Siewior static int mvneta_cpu_down_prepare(unsigned int cpu, struct hlist_node *node) 422484a3f4dbSSebastian Andrzej Siewior { 422584a3f4dbSSebastian Andrzej Siewior struct mvneta_port *pp = hlist_entry_safe(node, struct mvneta_port, 422684a3f4dbSSebastian Andrzej Siewior node_online); 422784a3f4dbSSebastian Andrzej Siewior struct mvneta_pcpu_port *port = per_cpu_ptr(pp->ports, cpu); 422884a3f4dbSSebastian Andrzej Siewior 422984a3f4dbSSebastian Andrzej Siewior /* 423084a3f4dbSSebastian Andrzej Siewior * Thanks to this lock we are sure that any pending cpu election is 423184a3f4dbSSebastian Andrzej Siewior * done. 42325888511eSGregory CLEMENT */ 42335888511eSGregory CLEMENT spin_lock(&pp->lock); 4234f8642885SMaxime Ripard /* Mask all ethernet port interrupts */ 4235db488c10SGregory CLEMENT on_each_cpu(mvneta_percpu_mask_interrupt, pp, true); 42365888511eSGregory CLEMENT spin_unlock(&pp->lock); 4237f8642885SMaxime Ripard 4238f8642885SMaxime Ripard napi_synchronize(&port->napi); 4239f8642885SMaxime Ripard napi_disable(&port->napi); 424084a3f4dbSSebastian Andrzej Siewior /* Disable per-CPU interrupts on the CPU that is brought down. */ 42410e28bf93SAnna-Maria Gleixner mvneta_percpu_disable(pp); 424284a3f4dbSSebastian Andrzej Siewior return 0; 424384a3f4dbSSebastian Andrzej Siewior } 4244f8642885SMaxime Ripard 424584a3f4dbSSebastian Andrzej Siewior static int mvneta_cpu_dead(unsigned int cpu, struct hlist_node *node) 424684a3f4dbSSebastian Andrzej Siewior { 424784a3f4dbSSebastian Andrzej Siewior struct mvneta_port *pp = hlist_entry_safe(node, struct mvneta_port, 424884a3f4dbSSebastian Andrzej Siewior node_dead); 424984a3f4dbSSebastian Andrzej Siewior 4250f8642885SMaxime Ripard /* Check if a new CPU must be elected now this on is down */ 4251120cfa50SGregory CLEMENT spin_lock(&pp->lock); 4252f8642885SMaxime Ripard mvneta_percpu_elect(pp); 4253120cfa50SGregory CLEMENT spin_unlock(&pp->lock); 4254f8642885SMaxime Ripard /* Unmask all ethernet port interrupts */ 4255db488c10SGregory CLEMENT on_each_cpu(mvneta_percpu_unmask_interrupt, pp, true); 4256f8642885SMaxime Ripard mvreg_write(pp, MVNETA_INTR_MISC_MASK, 4257f8642885SMaxime Ripard MVNETA_CAUSE_PHY_STATUS_CHANGE | 4258856b2cc5SRussell King MVNETA_CAUSE_LINK_CHANGE); 4259f8642885SMaxime Ripard netif_tx_start_all_queues(pp->dev); 426084a3f4dbSSebastian Andrzej Siewior return 0; 4261f8642885SMaxime Ripard } 4262f8642885SMaxime Ripard 4263c5aff182SThomas Petazzoni static int mvneta_open(struct net_device *dev) 4264c5aff182SThomas Petazzoni { 4265c5aff182SThomas Petazzoni struct mvneta_port *pp = netdev_priv(dev); 42666b125d63SGregory CLEMENT int ret; 4267c5aff182SThomas Petazzoni 4268c5aff182SThomas Petazzoni pp->pkt_size = MVNETA_RX_PKT_SIZE(pp->dev->mtu); 4269c5aff182SThomas Petazzoni 4270c5aff182SThomas Petazzoni ret = mvneta_setup_rxqs(pp); 4271c5aff182SThomas Petazzoni if (ret) 4272c5aff182SThomas Petazzoni return ret; 4273c5aff182SThomas Petazzoni 4274c5aff182SThomas Petazzoni ret = mvneta_setup_txqs(pp); 4275c5aff182SThomas Petazzoni if (ret) 4276c5aff182SThomas Petazzoni goto err_cleanup_rxqs; 4277c5aff182SThomas Petazzoni 4278c5aff182SThomas Petazzoni /* Connect to port interrupt line */ 42792636ac3cSMarcin Wojtas if (pp->neta_armada3700) 42802636ac3cSMarcin Wojtas ret = request_irq(pp->dev->irq, mvneta_isr, 0, 42812636ac3cSMarcin Wojtas dev->name, pp); 42822636ac3cSMarcin Wojtas else 42832636ac3cSMarcin Wojtas ret = request_percpu_irq(pp->dev->irq, mvneta_percpu_isr, 42842636ac3cSMarcin Wojtas dev->name, pp->ports); 4285c5aff182SThomas Petazzoni if (ret) { 4286c5aff182SThomas Petazzoni netdev_err(pp->dev, "cannot request irq %d\n", pp->dev->irq); 4287c5aff182SThomas Petazzoni goto err_cleanup_txqs; 4288c5aff182SThomas Petazzoni } 4289c5aff182SThomas Petazzoni 42902636ac3cSMarcin Wojtas if (!pp->neta_armada3700) { 42912dcf75e2SGregory CLEMENT /* Enable per-CPU interrupt on all the CPU to handle our RX 42922dcf75e2SGregory CLEMENT * queue interrupts 42932dcf75e2SGregory CLEMENT */ 42946b125d63SGregory CLEMENT on_each_cpu(mvneta_percpu_enable, pp, true); 42952dcf75e2SGregory CLEMENT 4296120cfa50SGregory CLEMENT pp->is_stopped = false; 4297f8642885SMaxime Ripard /* Register a CPU notifier to handle the case where our CPU 4298f8642885SMaxime Ripard * might be taken offline. 4299f8642885SMaxime Ripard */ 430084a3f4dbSSebastian Andrzej Siewior ret = cpuhp_state_add_instance_nocalls(online_hpstate, 430184a3f4dbSSebastian Andrzej Siewior &pp->node_online); 430284a3f4dbSSebastian Andrzej Siewior if (ret) 430384a3f4dbSSebastian Andrzej Siewior goto err_free_irq; 430484a3f4dbSSebastian Andrzej Siewior 430584a3f4dbSSebastian Andrzej Siewior ret = cpuhp_state_add_instance_nocalls(CPUHP_NET_MVNETA_DEAD, 430684a3f4dbSSebastian Andrzej Siewior &pp->node_dead); 430784a3f4dbSSebastian Andrzej Siewior if (ret) 430884a3f4dbSSebastian Andrzej Siewior goto err_free_online_hp; 43092636ac3cSMarcin Wojtas } 4310f8642885SMaxime Ripard 4311c5aff182SThomas Petazzoni ret = mvneta_mdio_probe(pp); 4312c5aff182SThomas Petazzoni if (ret < 0) { 4313c5aff182SThomas Petazzoni netdev_err(dev, "cannot probe MDIO bus\n"); 431484a3f4dbSSebastian Andrzej Siewior goto err_free_dead_hp; 4315c5aff182SThomas Petazzoni } 4316c5aff182SThomas Petazzoni 4317c5aff182SThomas Petazzoni mvneta_start_dev(pp); 4318c5aff182SThomas Petazzoni 4319c5aff182SThomas Petazzoni return 0; 4320c5aff182SThomas Petazzoni 432184a3f4dbSSebastian Andrzej Siewior err_free_dead_hp: 43222636ac3cSMarcin Wojtas if (!pp->neta_armada3700) 432384a3f4dbSSebastian Andrzej Siewior cpuhp_state_remove_instance_nocalls(CPUHP_NET_MVNETA_DEAD, 432484a3f4dbSSebastian Andrzej Siewior &pp->node_dead); 432584a3f4dbSSebastian Andrzej Siewior err_free_online_hp: 43262636ac3cSMarcin Wojtas if (!pp->neta_armada3700) 43272636ac3cSMarcin Wojtas cpuhp_state_remove_instance_nocalls(online_hpstate, 43282636ac3cSMarcin Wojtas &pp->node_online); 4329c5aff182SThomas Petazzoni err_free_irq: 43302636ac3cSMarcin Wojtas if (pp->neta_armada3700) { 43312636ac3cSMarcin Wojtas free_irq(pp->dev->irq, pp); 43322636ac3cSMarcin Wojtas } else { 43333d8c4530SRussell King - ARM Linux on_each_cpu(mvneta_percpu_disable, pp, true); 433412bb03b4SMaxime Ripard free_percpu_irq(pp->dev->irq, pp->ports); 43352636ac3cSMarcin Wojtas } 4336c5aff182SThomas Petazzoni err_cleanup_txqs: 4337c5aff182SThomas Petazzoni mvneta_cleanup_txqs(pp); 4338c5aff182SThomas Petazzoni err_cleanup_rxqs: 4339c5aff182SThomas Petazzoni mvneta_cleanup_rxqs(pp); 4340c5aff182SThomas Petazzoni return ret; 4341c5aff182SThomas Petazzoni } 4342c5aff182SThomas Petazzoni 4343c5aff182SThomas Petazzoni /* Stop the port, free port interrupt line */ 4344c5aff182SThomas Petazzoni static int mvneta_stop(struct net_device *dev) 4345c5aff182SThomas Petazzoni { 4346c5aff182SThomas Petazzoni struct mvneta_port *pp = netdev_priv(dev); 4347c5aff182SThomas Petazzoni 43482636ac3cSMarcin Wojtas if (!pp->neta_armada3700) { 4349120cfa50SGregory CLEMENT /* Inform that we are stopping so we don't want to setup the 43501c2722a9SGregory CLEMENT * driver for new CPUs in the notifiers. The code of the 43511c2722a9SGregory CLEMENT * notifier for CPU online is protected by the same spinlock, 43521c2722a9SGregory CLEMENT * so when we get the lock, the notifer work is done. 4353120cfa50SGregory CLEMENT */ 4354120cfa50SGregory CLEMENT spin_lock(&pp->lock); 4355120cfa50SGregory CLEMENT pp->is_stopped = true; 43561c2722a9SGregory CLEMENT spin_unlock(&pp->lock); 43571c2722a9SGregory CLEMENT 4358c5aff182SThomas Petazzoni mvneta_stop_dev(pp); 4359c5aff182SThomas Petazzoni mvneta_mdio_remove(pp); 436084a3f4dbSSebastian Andrzej Siewior 4361d26aac2dSDan Carpenter cpuhp_state_remove_instance_nocalls(online_hpstate, 4362d26aac2dSDan Carpenter &pp->node_online); 436384a3f4dbSSebastian Andrzej Siewior cpuhp_state_remove_instance_nocalls(CPUHP_NET_MVNETA_DEAD, 436484a3f4dbSSebastian Andrzej Siewior &pp->node_dead); 4365129219e4SGregory CLEMENT on_each_cpu(mvneta_percpu_disable, pp, true); 436612bb03b4SMaxime Ripard free_percpu_irq(dev->irq, pp->ports); 43672636ac3cSMarcin Wojtas } else { 43682636ac3cSMarcin Wojtas mvneta_stop_dev(pp); 43692636ac3cSMarcin Wojtas mvneta_mdio_remove(pp); 43702636ac3cSMarcin Wojtas free_irq(dev->irq, pp); 43712636ac3cSMarcin Wojtas } 43722636ac3cSMarcin Wojtas 4373c5aff182SThomas Petazzoni mvneta_cleanup_rxqs(pp); 4374c5aff182SThomas Petazzoni mvneta_cleanup_txqs(pp); 4375c5aff182SThomas Petazzoni 4376c5aff182SThomas Petazzoni return 0; 4377c5aff182SThomas Petazzoni } 4378c5aff182SThomas Petazzoni 437915f59456SThomas Petazzoni static int mvneta_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) 438015f59456SThomas Petazzoni { 4381503f9aa9SRussell King struct mvneta_port *pp = netdev_priv(dev); 438215f59456SThomas Petazzoni 4383503f9aa9SRussell King return phylink_mii_ioctl(pp->phylink, ifr, cmd); 438415f59456SThomas Petazzoni } 438515f59456SThomas Petazzoni 43860db51da7SLorenzo Bianconi static int mvneta_xdp_setup(struct net_device *dev, struct bpf_prog *prog, 43870db51da7SLorenzo Bianconi struct netlink_ext_ack *extack) 43880db51da7SLorenzo Bianconi { 43890db51da7SLorenzo Bianconi bool need_update, running = netif_running(dev); 43900db51da7SLorenzo Bianconi struct mvneta_port *pp = netdev_priv(dev); 43910db51da7SLorenzo Bianconi struct bpf_prog *old_prog; 43920db51da7SLorenzo Bianconi 43930db51da7SLorenzo Bianconi if (prog && dev->mtu > MVNETA_MAX_RX_BUF_SIZE) { 43940d136f5cSMarek Behún NL_SET_ERR_MSG_MOD(extack, "MTU too large for XDP"); 43950db51da7SLorenzo Bianconi return -EOPNOTSUPP; 43960db51da7SLorenzo Bianconi } 43970db51da7SLorenzo Bianconi 439879572c98SSven Auhagen if (pp->bm_priv) { 439979572c98SSven Auhagen NL_SET_ERR_MSG_MOD(extack, 440079572c98SSven Auhagen "Hardware Buffer Management not supported on XDP"); 440179572c98SSven Auhagen return -EOPNOTSUPP; 440279572c98SSven Auhagen } 440379572c98SSven Auhagen 44040db51da7SLorenzo Bianconi need_update = !!pp->xdp_prog != !!prog; 44050db51da7SLorenzo Bianconi if (running && need_update) 44060db51da7SLorenzo Bianconi mvneta_stop(dev); 44070db51da7SLorenzo Bianconi 44080db51da7SLorenzo Bianconi old_prog = xchg(&pp->xdp_prog, prog); 44090db51da7SLorenzo Bianconi if (old_prog) 44100db51da7SLorenzo Bianconi bpf_prog_put(old_prog); 44110db51da7SLorenzo Bianconi 44120db51da7SLorenzo Bianconi if (running && need_update) 44130db51da7SLorenzo Bianconi return mvneta_open(dev); 44140db51da7SLorenzo Bianconi 44150db51da7SLorenzo Bianconi return 0; 44160db51da7SLorenzo Bianconi } 44170db51da7SLorenzo Bianconi 44180db51da7SLorenzo Bianconi static int mvneta_xdp(struct net_device *dev, struct netdev_bpf *xdp) 44190db51da7SLorenzo Bianconi { 44200db51da7SLorenzo Bianconi switch (xdp->command) { 44210db51da7SLorenzo Bianconi case XDP_SETUP_PROG: 44220db51da7SLorenzo Bianconi return mvneta_xdp_setup(dev, xdp->prog, xdp->extack); 44230db51da7SLorenzo Bianconi default: 44240db51da7SLorenzo Bianconi return -EINVAL; 44250db51da7SLorenzo Bianconi } 44260db51da7SLorenzo Bianconi } 44270db51da7SLorenzo Bianconi 4428c5aff182SThomas Petazzoni /* Ethtool methods */ 4429c5aff182SThomas Petazzoni 4430013ad40dSPhilippe Reynes /* Set link ksettings (phy address, speed) for ethtools */ 44312dc0d2b4SBaoyou Xie static int 44322dc0d2b4SBaoyou Xie mvneta_ethtool_set_link_ksettings(struct net_device *ndev, 4433013ad40dSPhilippe Reynes const struct ethtool_link_ksettings *cmd) 4434c5aff182SThomas Petazzoni { 4435013ad40dSPhilippe Reynes struct mvneta_port *pp = netdev_priv(ndev); 4436c5aff182SThomas Petazzoni 4437503f9aa9SRussell King return phylink_ethtool_ksettings_set(pp->phylink, cmd); 44380c0744fcSStas Sergeev } 44390c0744fcSStas Sergeev 4440503f9aa9SRussell King /* Get link ksettings for ethtools */ 4441503f9aa9SRussell King static int 4442503f9aa9SRussell King mvneta_ethtool_get_link_ksettings(struct net_device *ndev, 4443503f9aa9SRussell King struct ethtool_link_ksettings *cmd) 4444503f9aa9SRussell King { 4445503f9aa9SRussell King struct mvneta_port *pp = netdev_priv(ndev); 44460c0744fcSStas Sergeev 4447503f9aa9SRussell King return phylink_ethtool_ksettings_get(pp->phylink, cmd); 44480c0744fcSStas Sergeev } 44490c0744fcSStas Sergeev 4450503f9aa9SRussell King static int mvneta_ethtool_nway_reset(struct net_device *dev) 4451503f9aa9SRussell King { 4452503f9aa9SRussell King struct mvneta_port *pp = netdev_priv(dev); 4453503f9aa9SRussell King 4454503f9aa9SRussell King return phylink_ethtool_nway_reset(pp->phylink); 4455c5aff182SThomas Petazzoni } 4456c5aff182SThomas Petazzoni 4457c5aff182SThomas Petazzoni /* Set interrupt coalescing for ethtools */ 4458f3ccfda1SYufeng Mo static int 4459f3ccfda1SYufeng Mo mvneta_ethtool_set_coalesce(struct net_device *dev, 4460f3ccfda1SYufeng Mo struct ethtool_coalesce *c, 4461f3ccfda1SYufeng Mo struct kernel_ethtool_coalesce *kernel_coal, 4462f3ccfda1SYufeng Mo struct netlink_ext_ack *extack) 4463c5aff182SThomas Petazzoni { 4464c5aff182SThomas Petazzoni struct mvneta_port *pp = netdev_priv(dev); 4465c5aff182SThomas Petazzoni int queue; 4466c5aff182SThomas Petazzoni 4467c5aff182SThomas Petazzoni for (queue = 0; queue < rxq_number; queue++) { 4468c5aff182SThomas Petazzoni struct mvneta_rx_queue *rxq = &pp->rxqs[queue]; 4469c5aff182SThomas Petazzoni rxq->time_coal = c->rx_coalesce_usecs; 4470c5aff182SThomas Petazzoni rxq->pkts_coal = c->rx_max_coalesced_frames; 4471c5aff182SThomas Petazzoni mvneta_rx_pkts_coal_set(pp, rxq, rxq->pkts_coal); 4472c5aff182SThomas Petazzoni mvneta_rx_time_coal_set(pp, rxq, rxq->time_coal); 4473c5aff182SThomas Petazzoni } 4474c5aff182SThomas Petazzoni 4475c5aff182SThomas Petazzoni for (queue = 0; queue < txq_number; queue++) { 4476c5aff182SThomas Petazzoni struct mvneta_tx_queue *txq = &pp->txqs[queue]; 4477c5aff182SThomas Petazzoni txq->done_pkts_coal = c->tx_max_coalesced_frames; 4478c5aff182SThomas Petazzoni mvneta_tx_done_pkts_coal_set(pp, txq, txq->done_pkts_coal); 4479c5aff182SThomas Petazzoni } 4480c5aff182SThomas Petazzoni 4481c5aff182SThomas Petazzoni return 0; 4482c5aff182SThomas Petazzoni } 4483c5aff182SThomas Petazzoni 4484c5aff182SThomas Petazzoni /* get coalescing for ethtools */ 4485f3ccfda1SYufeng Mo static int 4486f3ccfda1SYufeng Mo mvneta_ethtool_get_coalesce(struct net_device *dev, 4487f3ccfda1SYufeng Mo struct ethtool_coalesce *c, 4488f3ccfda1SYufeng Mo struct kernel_ethtool_coalesce *kernel_coal, 4489f3ccfda1SYufeng Mo struct netlink_ext_ack *extack) 4490c5aff182SThomas Petazzoni { 4491c5aff182SThomas Petazzoni struct mvneta_port *pp = netdev_priv(dev); 4492c5aff182SThomas Petazzoni 4493c5aff182SThomas Petazzoni c->rx_coalesce_usecs = pp->rxqs[0].time_coal; 4494c5aff182SThomas Petazzoni c->rx_max_coalesced_frames = pp->rxqs[0].pkts_coal; 4495c5aff182SThomas Petazzoni 4496c5aff182SThomas Petazzoni c->tx_max_coalesced_frames = pp->txqs[0].done_pkts_coal; 4497c5aff182SThomas Petazzoni return 0; 4498c5aff182SThomas Petazzoni } 4499c5aff182SThomas Petazzoni 4500c5aff182SThomas Petazzoni 4501c5aff182SThomas Petazzoni static void mvneta_ethtool_get_drvinfo(struct net_device *dev, 4502c5aff182SThomas Petazzoni struct ethtool_drvinfo *drvinfo) 4503c5aff182SThomas Petazzoni { 4504c5aff182SThomas Petazzoni strlcpy(drvinfo->driver, MVNETA_DRIVER_NAME, 4505c5aff182SThomas Petazzoni sizeof(drvinfo->driver)); 4506c5aff182SThomas Petazzoni strlcpy(drvinfo->version, MVNETA_DRIVER_VERSION, 4507c5aff182SThomas Petazzoni sizeof(drvinfo->version)); 4508c5aff182SThomas Petazzoni strlcpy(drvinfo->bus_info, dev_name(&dev->dev), 4509c5aff182SThomas Petazzoni sizeof(drvinfo->bus_info)); 4510c5aff182SThomas Petazzoni } 4511c5aff182SThomas Petazzoni 4512c5aff182SThomas Petazzoni 4513*74624944SHao Chen static void 4514*74624944SHao Chen mvneta_ethtool_get_ringparam(struct net_device *netdev, 4515*74624944SHao Chen struct ethtool_ringparam *ring, 4516*74624944SHao Chen struct kernel_ethtool_ringparam *kernel_ring, 4517*74624944SHao Chen struct netlink_ext_ack *extack) 4518c5aff182SThomas Petazzoni { 4519c5aff182SThomas Petazzoni struct mvneta_port *pp = netdev_priv(netdev); 4520c5aff182SThomas Petazzoni 4521c5aff182SThomas Petazzoni ring->rx_max_pending = MVNETA_MAX_RXD; 4522c5aff182SThomas Petazzoni ring->tx_max_pending = MVNETA_MAX_TXD; 4523c5aff182SThomas Petazzoni ring->rx_pending = pp->rx_ring_size; 4524c5aff182SThomas Petazzoni ring->tx_pending = pp->tx_ring_size; 4525c5aff182SThomas Petazzoni } 4526c5aff182SThomas Petazzoni 4527*74624944SHao Chen static int 4528*74624944SHao Chen mvneta_ethtool_set_ringparam(struct net_device *dev, 4529*74624944SHao Chen struct ethtool_ringparam *ring, 4530*74624944SHao Chen struct kernel_ethtool_ringparam *kernel_ring, 4531*74624944SHao Chen struct netlink_ext_ack *extack) 4532c5aff182SThomas Petazzoni { 4533c5aff182SThomas Petazzoni struct mvneta_port *pp = netdev_priv(dev); 4534c5aff182SThomas Petazzoni 4535c5aff182SThomas Petazzoni if ((ring->rx_pending == 0) || (ring->tx_pending == 0)) 4536c5aff182SThomas Petazzoni return -EINVAL; 4537c5aff182SThomas Petazzoni pp->rx_ring_size = ring->rx_pending < MVNETA_MAX_RXD ? 4538c5aff182SThomas Petazzoni ring->rx_pending : MVNETA_MAX_RXD; 45398eef5f97SEzequiel Garcia 45408eef5f97SEzequiel Garcia pp->tx_ring_size = clamp_t(u16, ring->tx_pending, 45418eef5f97SEzequiel Garcia MVNETA_MAX_SKB_DESCS * 2, MVNETA_MAX_TXD); 45428eef5f97SEzequiel Garcia if (pp->tx_ring_size != ring->tx_pending) 45438eef5f97SEzequiel Garcia netdev_warn(dev, "TX queue size set to %u (requested %u)\n", 45448eef5f97SEzequiel Garcia pp->tx_ring_size, ring->tx_pending); 4545c5aff182SThomas Petazzoni 4546c5aff182SThomas Petazzoni if (netif_running(dev)) { 4547c5aff182SThomas Petazzoni mvneta_stop(dev); 4548c5aff182SThomas Petazzoni if (mvneta_open(dev)) { 4549c5aff182SThomas Petazzoni netdev_err(dev, 4550c5aff182SThomas Petazzoni "error on opening device after ring param change\n"); 4551c5aff182SThomas Petazzoni return -ENOMEM; 4552c5aff182SThomas Petazzoni } 4553c5aff182SThomas Petazzoni } 4554c5aff182SThomas Petazzoni 4555c5aff182SThomas Petazzoni return 0; 4556c5aff182SThomas Petazzoni } 4557c5aff182SThomas Petazzoni 45584932a918SRussell King static void mvneta_ethtool_get_pauseparam(struct net_device *dev, 45594932a918SRussell King struct ethtool_pauseparam *pause) 45604932a918SRussell King { 45614932a918SRussell King struct mvneta_port *pp = netdev_priv(dev); 45624932a918SRussell King 45634932a918SRussell King phylink_ethtool_get_pauseparam(pp->phylink, pause); 45644932a918SRussell King } 45654932a918SRussell King 45664932a918SRussell King static int mvneta_ethtool_set_pauseparam(struct net_device *dev, 45674932a918SRussell King struct ethtool_pauseparam *pause) 45684932a918SRussell King { 45694932a918SRussell King struct mvneta_port *pp = netdev_priv(dev); 45704932a918SRussell King 45714932a918SRussell King return phylink_ethtool_set_pauseparam(pp->phylink, pause); 45724932a918SRussell King } 45734932a918SRussell King 45749b0cdefaSRussell King static void mvneta_ethtool_get_strings(struct net_device *netdev, u32 sset, 45759b0cdefaSRussell King u8 *data) 45769b0cdefaSRussell King { 45779b0cdefaSRussell King if (sset == ETH_SS_STATS) { 45789b0cdefaSRussell King int i; 45799b0cdefaSRussell King 45809b0cdefaSRussell King for (i = 0; i < ARRAY_SIZE(mvneta_statistics); i++) 45819b0cdefaSRussell King memcpy(data + i * ETH_GSTRING_LEN, 45829b0cdefaSRussell King mvneta_statistics[i].name, ETH_GSTRING_LEN); 45839b0cdefaSRussell King } 45849b0cdefaSRussell King } 45859b0cdefaSRussell King 45869ac41f3cSLorenzo Bianconi static void 45879ac41f3cSLorenzo Bianconi mvneta_ethtool_update_pcpu_stats(struct mvneta_port *pp, 45889ac41f3cSLorenzo Bianconi struct mvneta_ethtool_stats *es) 45899ac41f3cSLorenzo Bianconi { 45909ac41f3cSLorenzo Bianconi unsigned int start; 45919ac41f3cSLorenzo Bianconi int cpu; 45929ac41f3cSLorenzo Bianconi 45939ac41f3cSLorenzo Bianconi for_each_possible_cpu(cpu) { 45949ac41f3cSLorenzo Bianconi struct mvneta_pcpu_stats *stats; 45959ac41f3cSLorenzo Bianconi u64 skb_alloc_error; 45969ac41f3cSLorenzo Bianconi u64 refill_error; 45973d866523SLorenzo Bianconi u64 xdp_redirect; 459815070919SJesper Dangaard Brouer u64 xdp_xmit_err; 459915070919SJesper Dangaard Brouer u64 xdp_tx_err; 46003d866523SLorenzo Bianconi u64 xdp_pass; 46013d866523SLorenzo Bianconi u64 xdp_drop; 46027d51a015SLorenzo Bianconi u64 xdp_xmit; 46033d866523SLorenzo Bianconi u64 xdp_tx; 46049ac41f3cSLorenzo Bianconi 46059ac41f3cSLorenzo Bianconi stats = per_cpu_ptr(pp->stats, cpu); 46069ac41f3cSLorenzo Bianconi do { 46079ac41f3cSLorenzo Bianconi start = u64_stats_fetch_begin_irq(&stats->syncp); 46089ac41f3cSLorenzo Bianconi skb_alloc_error = stats->es.skb_alloc_error; 46099ac41f3cSLorenzo Bianconi refill_error = stats->es.refill_error; 46103d866523SLorenzo Bianconi xdp_redirect = stats->es.ps.xdp_redirect; 46113d866523SLorenzo Bianconi xdp_pass = stats->es.ps.xdp_pass; 46123d866523SLorenzo Bianconi xdp_drop = stats->es.ps.xdp_drop; 46137d51a015SLorenzo Bianconi xdp_xmit = stats->es.ps.xdp_xmit; 461415070919SJesper Dangaard Brouer xdp_xmit_err = stats->es.ps.xdp_xmit_err; 46153d866523SLorenzo Bianconi xdp_tx = stats->es.ps.xdp_tx; 461615070919SJesper Dangaard Brouer xdp_tx_err = stats->es.ps.xdp_tx_err; 46179ac41f3cSLorenzo Bianconi } while (u64_stats_fetch_retry_irq(&stats->syncp, start)); 46189ac41f3cSLorenzo Bianconi 46199ac41f3cSLorenzo Bianconi es->skb_alloc_error += skb_alloc_error; 46209ac41f3cSLorenzo Bianconi es->refill_error += refill_error; 46213d866523SLorenzo Bianconi es->ps.xdp_redirect += xdp_redirect; 46223d866523SLorenzo Bianconi es->ps.xdp_pass += xdp_pass; 46233d866523SLorenzo Bianconi es->ps.xdp_drop += xdp_drop; 46247d51a015SLorenzo Bianconi es->ps.xdp_xmit += xdp_xmit; 462515070919SJesper Dangaard Brouer es->ps.xdp_xmit_err += xdp_xmit_err; 46263d866523SLorenzo Bianconi es->ps.xdp_tx += xdp_tx; 462715070919SJesper Dangaard Brouer es->ps.xdp_tx_err += xdp_tx_err; 46289ac41f3cSLorenzo Bianconi } 46299ac41f3cSLorenzo Bianconi } 46309ac41f3cSLorenzo Bianconi 46319b0cdefaSRussell King static void mvneta_ethtool_update_stats(struct mvneta_port *pp) 46329b0cdefaSRussell King { 46339ac41f3cSLorenzo Bianconi struct mvneta_ethtool_stats stats = {}; 46349b0cdefaSRussell King const struct mvneta_statistic *s; 46359b0cdefaSRussell King void __iomem *base = pp->base; 46366d81f451SRussell King u32 high, low; 46376d81f451SRussell King u64 val; 46389b0cdefaSRussell King int i; 46399b0cdefaSRussell King 46409ac41f3cSLorenzo Bianconi mvneta_ethtool_update_pcpu_stats(pp, &stats); 46419b0cdefaSRussell King for (i = 0, s = mvneta_statistics; 46429b0cdefaSRussell King s < mvneta_statistics + ARRAY_SIZE(mvneta_statistics); 46439b0cdefaSRussell King s++, i++) { 46449b0cdefaSRussell King switch (s->type) { 46459b0cdefaSRussell King case T_REG_32: 46469b0cdefaSRussell King val = readl_relaxed(base + s->offset); 46479ac41f3cSLorenzo Bianconi pp->ethtool_stats[i] += val; 46489b0cdefaSRussell King break; 46499b0cdefaSRussell King case T_REG_64: 46509b0cdefaSRussell King /* Docs say to read low 32-bit then high */ 46519b0cdefaSRussell King low = readl_relaxed(base + s->offset); 46529b0cdefaSRussell King high = readl_relaxed(base + s->offset + 4); 46536d81f451SRussell King val = (u64)high << 32 | low; 46549ac41f3cSLorenzo Bianconi pp->ethtool_stats[i] += val; 46556d81f451SRussell King break; 46566d81f451SRussell King case T_SW: 46576d81f451SRussell King switch (s->offset) { 46586d81f451SRussell King case ETHTOOL_STAT_EEE_WAKEUP: 46596d81f451SRussell King val = phylink_get_eee_err(pp->phylink); 46609ac41f3cSLorenzo Bianconi pp->ethtool_stats[i] += val; 46619b0cdefaSRussell King break; 466217a96da6SGregory CLEMENT case ETHTOOL_STAT_SKB_ALLOC_ERR: 46639ac41f3cSLorenzo Bianconi pp->ethtool_stats[i] = stats.skb_alloc_error; 466417a96da6SGregory CLEMENT break; 466517a96da6SGregory CLEMENT case ETHTOOL_STAT_REFILL_ERR: 46669ac41f3cSLorenzo Bianconi pp->ethtool_stats[i] = stats.refill_error; 466717a96da6SGregory CLEMENT break; 46683d866523SLorenzo Bianconi case ETHTOOL_XDP_REDIRECT: 46693d866523SLorenzo Bianconi pp->ethtool_stats[i] = stats.ps.xdp_redirect; 46703d866523SLorenzo Bianconi break; 46713d866523SLorenzo Bianconi case ETHTOOL_XDP_PASS: 46723d866523SLorenzo Bianconi pp->ethtool_stats[i] = stats.ps.xdp_pass; 46733d866523SLorenzo Bianconi break; 46743d866523SLorenzo Bianconi case ETHTOOL_XDP_DROP: 46753d866523SLorenzo Bianconi pp->ethtool_stats[i] = stats.ps.xdp_drop; 46763d866523SLorenzo Bianconi break; 46773d866523SLorenzo Bianconi case ETHTOOL_XDP_TX: 46783d866523SLorenzo Bianconi pp->ethtool_stats[i] = stats.ps.xdp_tx; 46793d866523SLorenzo Bianconi break; 468015070919SJesper Dangaard Brouer case ETHTOOL_XDP_TX_ERR: 468115070919SJesper Dangaard Brouer pp->ethtool_stats[i] = stats.ps.xdp_tx_err; 468215070919SJesper Dangaard Brouer break; 46837d51a015SLorenzo Bianconi case ETHTOOL_XDP_XMIT: 46847d51a015SLorenzo Bianconi pp->ethtool_stats[i] = stats.ps.xdp_xmit; 46857d51a015SLorenzo Bianconi break; 468615070919SJesper Dangaard Brouer case ETHTOOL_XDP_XMIT_ERR: 468715070919SJesper Dangaard Brouer pp->ethtool_stats[i] = stats.ps.xdp_xmit_err; 468815070919SJesper Dangaard Brouer break; 46899b0cdefaSRussell King } 46906d81f451SRussell King break; 46916d81f451SRussell King } 46929b0cdefaSRussell King } 46939b0cdefaSRussell King } 46949b0cdefaSRussell King 46959b0cdefaSRussell King static void mvneta_ethtool_get_stats(struct net_device *dev, 46969b0cdefaSRussell King struct ethtool_stats *stats, u64 *data) 46979b0cdefaSRussell King { 46989b0cdefaSRussell King struct mvneta_port *pp = netdev_priv(dev); 46999b0cdefaSRussell King int i; 47009b0cdefaSRussell King 47019b0cdefaSRussell King mvneta_ethtool_update_stats(pp); 47029b0cdefaSRussell King 47039b0cdefaSRussell King for (i = 0; i < ARRAY_SIZE(mvneta_statistics); i++) 47049b0cdefaSRussell King *data++ = pp->ethtool_stats[i]; 47059b0cdefaSRussell King } 47069b0cdefaSRussell King 47079b0cdefaSRussell King static int mvneta_ethtool_get_sset_count(struct net_device *dev, int sset) 47089b0cdefaSRussell King { 47099b0cdefaSRussell King if (sset == ETH_SS_STATS) 47109b0cdefaSRussell King return ARRAY_SIZE(mvneta_statistics); 47119b0cdefaSRussell King return -EOPNOTSUPP; 47129b0cdefaSRussell King } 47139b0cdefaSRussell King 47149a401deaSGregory CLEMENT static u32 mvneta_ethtool_get_rxfh_indir_size(struct net_device *dev) 47159a401deaSGregory CLEMENT { 47169a401deaSGregory CLEMENT return MVNETA_RSS_LU_TABLE_SIZE; 47179a401deaSGregory CLEMENT } 47189a401deaSGregory CLEMENT 47199a401deaSGregory CLEMENT static int mvneta_ethtool_get_rxnfc(struct net_device *dev, 47209a401deaSGregory CLEMENT struct ethtool_rxnfc *info, 47219a401deaSGregory CLEMENT u32 *rules __always_unused) 47229a401deaSGregory CLEMENT { 47239a401deaSGregory CLEMENT switch (info->cmd) { 47249a401deaSGregory CLEMENT case ETHTOOL_GRXRINGS: 47259a401deaSGregory CLEMENT info->data = rxq_number; 47269a401deaSGregory CLEMENT return 0; 47279a401deaSGregory CLEMENT case ETHTOOL_GRXFH: 47289a401deaSGregory CLEMENT return -EOPNOTSUPP; 47299a401deaSGregory CLEMENT default: 47309a401deaSGregory CLEMENT return -EOPNOTSUPP; 47319a401deaSGregory CLEMENT } 47329a401deaSGregory CLEMENT } 47339a401deaSGregory CLEMENT 47349a401deaSGregory CLEMENT static int mvneta_config_rss(struct mvneta_port *pp) 47359a401deaSGregory CLEMENT { 47369a401deaSGregory CLEMENT int cpu; 47379a401deaSGregory CLEMENT u32 val; 47389a401deaSGregory CLEMENT 47399a401deaSGregory CLEMENT netif_tx_stop_all_queues(pp->dev); 47409a401deaSGregory CLEMENT 47416b125d63SGregory CLEMENT on_each_cpu(mvneta_percpu_mask_interrupt, pp, true); 47429a401deaSGregory CLEMENT 47430f5c6c30SJisheng Zhang if (!pp->neta_armada3700) { 47449a401deaSGregory CLEMENT /* We have to synchronise on the napi of each CPU */ 47459a401deaSGregory CLEMENT for_each_online_cpu(cpu) { 47469a401deaSGregory CLEMENT struct mvneta_pcpu_port *pcpu_port = 47479a401deaSGregory CLEMENT per_cpu_ptr(pp->ports, cpu); 47489a401deaSGregory CLEMENT 47499a401deaSGregory CLEMENT napi_synchronize(&pcpu_port->napi); 47509a401deaSGregory CLEMENT napi_disable(&pcpu_port->napi); 47519a401deaSGregory CLEMENT } 47520f5c6c30SJisheng Zhang } else { 47530f5c6c30SJisheng Zhang napi_synchronize(&pp->napi); 47540f5c6c30SJisheng Zhang napi_disable(&pp->napi); 47550f5c6c30SJisheng Zhang } 47569a401deaSGregory CLEMENT 47579a401deaSGregory CLEMENT pp->rxq_def = pp->indir[0]; 47589a401deaSGregory CLEMENT 47599a401deaSGregory CLEMENT /* Update unicast mapping */ 47609a401deaSGregory CLEMENT mvneta_set_rx_mode(pp->dev); 47619a401deaSGregory CLEMENT 47629a401deaSGregory CLEMENT /* Update val of portCfg register accordingly with all RxQueue types */ 47639a401deaSGregory CLEMENT val = MVNETA_PORT_CONFIG_DEFL_VALUE(pp->rxq_def); 47649a401deaSGregory CLEMENT mvreg_write(pp, MVNETA_PORT_CONFIG, val); 47659a401deaSGregory CLEMENT 47669a401deaSGregory CLEMENT /* Update the elected CPU matching the new rxq_def */ 4767120cfa50SGregory CLEMENT spin_lock(&pp->lock); 47689a401deaSGregory CLEMENT mvneta_percpu_elect(pp); 4769120cfa50SGregory CLEMENT spin_unlock(&pp->lock); 47709a401deaSGregory CLEMENT 47710f5c6c30SJisheng Zhang if (!pp->neta_armada3700) { 47729a401deaSGregory CLEMENT /* We have to synchronise on the napi of each CPU */ 47739a401deaSGregory CLEMENT for_each_online_cpu(cpu) { 47749a401deaSGregory CLEMENT struct mvneta_pcpu_port *pcpu_port = 47759a401deaSGregory CLEMENT per_cpu_ptr(pp->ports, cpu); 47769a401deaSGregory CLEMENT 47779a401deaSGregory CLEMENT napi_enable(&pcpu_port->napi); 47789a401deaSGregory CLEMENT } 47790f5c6c30SJisheng Zhang } else { 47800f5c6c30SJisheng Zhang napi_enable(&pp->napi); 47810f5c6c30SJisheng Zhang } 47829a401deaSGregory CLEMENT 47839a401deaSGregory CLEMENT netif_tx_start_all_queues(pp->dev); 47849a401deaSGregory CLEMENT 47859a401deaSGregory CLEMENT return 0; 47869a401deaSGregory CLEMENT } 47879a401deaSGregory CLEMENT 47889a401deaSGregory CLEMENT static int mvneta_ethtool_set_rxfh(struct net_device *dev, const u32 *indir, 47899a401deaSGregory CLEMENT const u8 *key, const u8 hfunc) 47909a401deaSGregory CLEMENT { 47919a401deaSGregory CLEMENT struct mvneta_port *pp = netdev_priv(dev); 47922636ac3cSMarcin Wojtas 47932636ac3cSMarcin Wojtas /* Current code for Armada 3700 doesn't support RSS features yet */ 47942636ac3cSMarcin Wojtas if (pp->neta_armada3700) 47952636ac3cSMarcin Wojtas return -EOPNOTSUPP; 47962636ac3cSMarcin Wojtas 47979a401deaSGregory CLEMENT /* We require at least one supported parameter to be changed 47989a401deaSGregory CLEMENT * and no change in any of the unsupported parameters 47999a401deaSGregory CLEMENT */ 48009a401deaSGregory CLEMENT if (key || 48019a401deaSGregory CLEMENT (hfunc != ETH_RSS_HASH_NO_CHANGE && hfunc != ETH_RSS_HASH_TOP)) 48029a401deaSGregory CLEMENT return -EOPNOTSUPP; 48039a401deaSGregory CLEMENT 48049a401deaSGregory CLEMENT if (!indir) 48059a401deaSGregory CLEMENT return 0; 48069a401deaSGregory CLEMENT 48079a401deaSGregory CLEMENT memcpy(pp->indir, indir, MVNETA_RSS_LU_TABLE_SIZE); 48089a401deaSGregory CLEMENT 48099a401deaSGregory CLEMENT return mvneta_config_rss(pp); 48109a401deaSGregory CLEMENT } 48119a401deaSGregory CLEMENT 48129a401deaSGregory CLEMENT static int mvneta_ethtool_get_rxfh(struct net_device *dev, u32 *indir, u8 *key, 48139a401deaSGregory CLEMENT u8 *hfunc) 48149a401deaSGregory CLEMENT { 48159a401deaSGregory CLEMENT struct mvneta_port *pp = netdev_priv(dev); 48169a401deaSGregory CLEMENT 48172636ac3cSMarcin Wojtas /* Current code for Armada 3700 doesn't support RSS features yet */ 48182636ac3cSMarcin Wojtas if (pp->neta_armada3700) 48192636ac3cSMarcin Wojtas return -EOPNOTSUPP; 48202636ac3cSMarcin Wojtas 48219a401deaSGregory CLEMENT if (hfunc) 48229a401deaSGregory CLEMENT *hfunc = ETH_RSS_HASH_TOP; 48239a401deaSGregory CLEMENT 48249a401deaSGregory CLEMENT if (!indir) 48259a401deaSGregory CLEMENT return 0; 48269a401deaSGregory CLEMENT 48279a401deaSGregory CLEMENT memcpy(indir, pp->indir, MVNETA_RSS_LU_TABLE_SIZE); 48289a401deaSGregory CLEMENT 48299a401deaSGregory CLEMENT return 0; 48309a401deaSGregory CLEMENT } 48319a401deaSGregory CLEMENT 4832b60a00f9SJingju Hou static void mvneta_ethtool_get_wol(struct net_device *dev, 4833b60a00f9SJingju Hou struct ethtool_wolinfo *wol) 4834b60a00f9SJingju Hou { 4835503f9aa9SRussell King struct mvneta_port *pp = netdev_priv(dev); 4836b60a00f9SJingju Hou 4837503f9aa9SRussell King phylink_ethtool_get_wol(pp->phylink, wol); 4838b60a00f9SJingju Hou } 4839b60a00f9SJingju Hou 4840b60a00f9SJingju Hou static int mvneta_ethtool_set_wol(struct net_device *dev, 4841b60a00f9SJingju Hou struct ethtool_wolinfo *wol) 4842b60a00f9SJingju Hou { 4843503f9aa9SRussell King struct mvneta_port *pp = netdev_priv(dev); 484482960fffSJisheng Zhang int ret; 484582960fffSJisheng Zhang 4846503f9aa9SRussell King ret = phylink_ethtool_set_wol(pp->phylink, wol); 484782960fffSJisheng Zhang if (!ret) 484882960fffSJisheng Zhang device_set_wakeup_enable(&dev->dev, !!wol->wolopts); 484982960fffSJisheng Zhang 485082960fffSJisheng Zhang return ret; 4851b60a00f9SJingju Hou } 4852b60a00f9SJingju Hou 48536d81f451SRussell King static int mvneta_ethtool_get_eee(struct net_device *dev, 48546d81f451SRussell King struct ethtool_eee *eee) 48556d81f451SRussell King { 48566d81f451SRussell King struct mvneta_port *pp = netdev_priv(dev); 48576d81f451SRussell King u32 lpi_ctl0; 48586d81f451SRussell King 48596d81f451SRussell King lpi_ctl0 = mvreg_read(pp, MVNETA_LPI_CTRL_0); 48606d81f451SRussell King 48616d81f451SRussell King eee->eee_enabled = pp->eee_enabled; 48626d81f451SRussell King eee->eee_active = pp->eee_active; 48636d81f451SRussell King eee->tx_lpi_enabled = pp->tx_lpi_enabled; 48646d81f451SRussell King eee->tx_lpi_timer = (lpi_ctl0) >> 8; // * scale; 48656d81f451SRussell King 48666d81f451SRussell King return phylink_ethtool_get_eee(pp->phylink, eee); 48676d81f451SRussell King } 48686d81f451SRussell King 48696d81f451SRussell King static int mvneta_ethtool_set_eee(struct net_device *dev, 48706d81f451SRussell King struct ethtool_eee *eee) 48716d81f451SRussell King { 48726d81f451SRussell King struct mvneta_port *pp = netdev_priv(dev); 48736d81f451SRussell King u32 lpi_ctl0; 48746d81f451SRussell King 48756d81f451SRussell King /* The Armada 37x documents do not give limits for this other than 4876df4a17a9SYangyang Li * it being an 8-bit register. 4877df4a17a9SYangyang Li */ 4878e4a3e9ffSYueHaibing if (eee->tx_lpi_enabled && eee->tx_lpi_timer > 255) 48796d81f451SRussell King return -EINVAL; 48806d81f451SRussell King 48816d81f451SRussell King lpi_ctl0 = mvreg_read(pp, MVNETA_LPI_CTRL_0); 48826d81f451SRussell King lpi_ctl0 &= ~(0xff << 8); 48836d81f451SRussell King lpi_ctl0 |= eee->tx_lpi_timer << 8; 48846d81f451SRussell King mvreg_write(pp, MVNETA_LPI_CTRL_0, lpi_ctl0); 48856d81f451SRussell King 48866d81f451SRussell King pp->eee_enabled = eee->eee_enabled; 48876d81f451SRussell King pp->tx_lpi_enabled = eee->tx_lpi_enabled; 48886d81f451SRussell King 48896d81f451SRussell King mvneta_set_eee(pp, eee->tx_lpi_enabled && eee->eee_enabled); 48906d81f451SRussell King 48916d81f451SRussell King return phylink_ethtool_set_eee(pp->phylink, eee); 48926d81f451SRussell King } 48936d81f451SRussell King 48944906887aSMaxime Chevallier static void mvneta_clear_rx_prio_map(struct mvneta_port *pp) 48954906887aSMaxime Chevallier { 48964906887aSMaxime Chevallier mvreg_write(pp, MVNETA_VLAN_PRIO_TO_RXQ, 0); 48974906887aSMaxime Chevallier } 48984906887aSMaxime Chevallier 48994906887aSMaxime Chevallier static void mvneta_setup_rx_prio_map(struct mvneta_port *pp) 49004906887aSMaxime Chevallier { 49014906887aSMaxime Chevallier u32 val = 0; 49024906887aSMaxime Chevallier int i; 49034906887aSMaxime Chevallier 49044906887aSMaxime Chevallier for (i = 0; i < rxq_number; i++) 49054906887aSMaxime Chevallier val |= MVNETA_VLAN_PRIO_RXQ_MAP(i, pp->prio_tc_map[i]); 49064906887aSMaxime Chevallier 49074906887aSMaxime Chevallier mvreg_write(pp, MVNETA_VLAN_PRIO_TO_RXQ, val); 49084906887aSMaxime Chevallier } 49094906887aSMaxime Chevallier 49104906887aSMaxime Chevallier static int mvneta_setup_mqprio(struct net_device *dev, 49114906887aSMaxime Chevallier struct tc_mqprio_qopt *qopt) 49124906887aSMaxime Chevallier { 49134906887aSMaxime Chevallier struct mvneta_port *pp = netdev_priv(dev); 49144906887aSMaxime Chevallier u8 num_tc; 49154906887aSMaxime Chevallier int i; 49164906887aSMaxime Chevallier 49174906887aSMaxime Chevallier qopt->hw = TC_MQPRIO_HW_OFFLOAD_TCS; 49184906887aSMaxime Chevallier num_tc = qopt->num_tc; 49194906887aSMaxime Chevallier 49204906887aSMaxime Chevallier if (num_tc > rxq_number) 49214906887aSMaxime Chevallier return -EINVAL; 49224906887aSMaxime Chevallier 49234906887aSMaxime Chevallier if (!num_tc) { 49244906887aSMaxime Chevallier mvneta_clear_rx_prio_map(pp); 49254906887aSMaxime Chevallier netdev_reset_tc(dev); 49264906887aSMaxime Chevallier return 0; 49274906887aSMaxime Chevallier } 49284906887aSMaxime Chevallier 49294906887aSMaxime Chevallier memcpy(pp->prio_tc_map, qopt->prio_tc_map, sizeof(pp->prio_tc_map)); 49304906887aSMaxime Chevallier 49314906887aSMaxime Chevallier mvneta_setup_rx_prio_map(pp); 49324906887aSMaxime Chevallier 49334906887aSMaxime Chevallier netdev_set_num_tc(dev, qopt->num_tc); 49344906887aSMaxime Chevallier for (i = 0; i < qopt->num_tc; i++) 49354906887aSMaxime Chevallier netdev_set_tc_queue(dev, i, qopt->count[i], qopt->offset[i]); 49364906887aSMaxime Chevallier 49374906887aSMaxime Chevallier return 0; 49384906887aSMaxime Chevallier } 49394906887aSMaxime Chevallier 49404906887aSMaxime Chevallier static int mvneta_setup_tc(struct net_device *dev, enum tc_setup_type type, 49414906887aSMaxime Chevallier void *type_data) 49424906887aSMaxime Chevallier { 49434906887aSMaxime Chevallier switch (type) { 49444906887aSMaxime Chevallier case TC_SETUP_QDISC_MQPRIO: 49454906887aSMaxime Chevallier return mvneta_setup_mqprio(dev, type_data); 49464906887aSMaxime Chevallier default: 49474906887aSMaxime Chevallier return -EOPNOTSUPP; 49484906887aSMaxime Chevallier } 49494906887aSMaxime Chevallier } 49504906887aSMaxime Chevallier 4951c5aff182SThomas Petazzoni static const struct net_device_ops mvneta_netdev_ops = { 4952c5aff182SThomas Petazzoni .ndo_open = mvneta_open, 4953c5aff182SThomas Petazzoni .ndo_stop = mvneta_stop, 4954c5aff182SThomas Petazzoni .ndo_start_xmit = mvneta_tx, 4955c5aff182SThomas Petazzoni .ndo_set_rx_mode = mvneta_set_rx_mode, 4956c5aff182SThomas Petazzoni .ndo_set_mac_address = mvneta_set_mac_addr, 4957c5aff182SThomas Petazzoni .ndo_change_mtu = mvneta_change_mtu, 4958b65657fcSSimon Guinot .ndo_fix_features = mvneta_fix_features, 4959c5aff182SThomas Petazzoni .ndo_get_stats64 = mvneta_get_stats64, 4960a7605370SArnd Bergmann .ndo_eth_ioctl = mvneta_ioctl, 49610db51da7SLorenzo Bianconi .ndo_bpf = mvneta_xdp, 4962b0a43db9SLorenzo Bianconi .ndo_xdp_xmit = mvneta_xdp_xmit, 49634906887aSMaxime Chevallier .ndo_setup_tc = mvneta_setup_tc, 4964c5aff182SThomas Petazzoni }; 4965c5aff182SThomas Petazzoni 49664581be42SJisheng Zhang static const struct ethtool_ops mvneta_eth_tool_ops = { 496716e8d8b3SJakub Kicinski .supported_coalesce_params = ETHTOOL_COALESCE_RX_USECS | 496816e8d8b3SJakub Kicinski ETHTOOL_COALESCE_MAX_FRAMES, 4969503f9aa9SRussell King .nway_reset = mvneta_ethtool_nway_reset, 4970c5aff182SThomas Petazzoni .get_link = ethtool_op_get_link, 4971c5aff182SThomas Petazzoni .set_coalesce = mvneta_ethtool_set_coalesce, 4972c5aff182SThomas Petazzoni .get_coalesce = mvneta_ethtool_get_coalesce, 4973c5aff182SThomas Petazzoni .get_drvinfo = mvneta_ethtool_get_drvinfo, 4974c5aff182SThomas Petazzoni .get_ringparam = mvneta_ethtool_get_ringparam, 4975c5aff182SThomas Petazzoni .set_ringparam = mvneta_ethtool_set_ringparam, 49764932a918SRussell King .get_pauseparam = mvneta_ethtool_get_pauseparam, 49774932a918SRussell King .set_pauseparam = mvneta_ethtool_set_pauseparam, 49789b0cdefaSRussell King .get_strings = mvneta_ethtool_get_strings, 49799b0cdefaSRussell King .get_ethtool_stats = mvneta_ethtool_get_stats, 49809b0cdefaSRussell King .get_sset_count = mvneta_ethtool_get_sset_count, 49819a401deaSGregory CLEMENT .get_rxfh_indir_size = mvneta_ethtool_get_rxfh_indir_size, 49829a401deaSGregory CLEMENT .get_rxnfc = mvneta_ethtool_get_rxnfc, 49839a401deaSGregory CLEMENT .get_rxfh = mvneta_ethtool_get_rxfh, 49849a401deaSGregory CLEMENT .set_rxfh = mvneta_ethtool_set_rxfh, 4985503f9aa9SRussell King .get_link_ksettings = mvneta_ethtool_get_link_ksettings, 4986013ad40dSPhilippe Reynes .set_link_ksettings = mvneta_ethtool_set_link_ksettings, 4987b60a00f9SJingju Hou .get_wol = mvneta_ethtool_get_wol, 4988b60a00f9SJingju Hou .set_wol = mvneta_ethtool_set_wol, 49896d81f451SRussell King .get_eee = mvneta_ethtool_get_eee, 49906d81f451SRussell King .set_eee = mvneta_ethtool_set_eee, 4991c5aff182SThomas Petazzoni }; 4992c5aff182SThomas Petazzoni 4993c5aff182SThomas Petazzoni /* Initialize hw */ 49949672850bSEzequiel Garcia static int mvneta_init(struct device *dev, struct mvneta_port *pp) 4995c5aff182SThomas Petazzoni { 4996c5aff182SThomas Petazzoni int queue; 4997c5aff182SThomas Petazzoni 4998c5aff182SThomas Petazzoni /* Disable port */ 4999c5aff182SThomas Petazzoni mvneta_port_disable(pp); 5000c5aff182SThomas Petazzoni 5001c5aff182SThomas Petazzoni /* Set port default values */ 5002c5aff182SThomas Petazzoni mvneta_defaults_set(pp); 5003c5aff182SThomas Petazzoni 50045d6312edSMarkus Elfring pp->txqs = devm_kcalloc(dev, txq_number, sizeof(*pp->txqs), GFP_KERNEL); 5005c5aff182SThomas Petazzoni if (!pp->txqs) 5006c5aff182SThomas Petazzoni return -ENOMEM; 5007c5aff182SThomas Petazzoni 5008c5aff182SThomas Petazzoni /* Initialize TX descriptor rings */ 5009c5aff182SThomas Petazzoni for (queue = 0; queue < txq_number; queue++) { 5010c5aff182SThomas Petazzoni struct mvneta_tx_queue *txq = &pp->txqs[queue]; 5011c5aff182SThomas Petazzoni txq->id = queue; 5012c5aff182SThomas Petazzoni txq->size = pp->tx_ring_size; 5013c5aff182SThomas Petazzoni txq->done_pkts_coal = MVNETA_TXDONE_COAL_PKTS; 5014c5aff182SThomas Petazzoni } 5015c5aff182SThomas Petazzoni 50165d6312edSMarkus Elfring pp->rxqs = devm_kcalloc(dev, rxq_number, sizeof(*pp->rxqs), GFP_KERNEL); 50179672850bSEzequiel Garcia if (!pp->rxqs) 5018c5aff182SThomas Petazzoni return -ENOMEM; 5019c5aff182SThomas Petazzoni 5020c5aff182SThomas Petazzoni /* Create Rx descriptor rings */ 5021c5aff182SThomas Petazzoni for (queue = 0; queue < rxq_number; queue++) { 5022c5aff182SThomas Petazzoni struct mvneta_rx_queue *rxq = &pp->rxqs[queue]; 5023c5aff182SThomas Petazzoni rxq->id = queue; 5024c5aff182SThomas Petazzoni rxq->size = pp->rx_ring_size; 5025c5aff182SThomas Petazzoni rxq->pkts_coal = MVNETA_RX_COAL_PKTS; 5026c5aff182SThomas Petazzoni rxq->time_coal = MVNETA_RX_COAL_USEC; 502729110630SMarkus Elfring rxq->buf_virt_addr 502829110630SMarkus Elfring = devm_kmalloc_array(pp->dev->dev.parent, 502929110630SMarkus Elfring rxq->size, 503029110630SMarkus Elfring sizeof(*rxq->buf_virt_addr), 5031f88bee1cSGregory CLEMENT GFP_KERNEL); 5032f88bee1cSGregory CLEMENT if (!rxq->buf_virt_addr) 5033f88bee1cSGregory CLEMENT return -ENOMEM; 5034c5aff182SThomas Petazzoni } 5035c5aff182SThomas Petazzoni 5036c5aff182SThomas Petazzoni return 0; 5037c5aff182SThomas Petazzoni } 5038c5aff182SThomas Petazzoni 5039c5aff182SThomas Petazzoni /* platform glue : initialize decoding windows */ 504003ce758eSGreg KH static void mvneta_conf_mbus_windows(struct mvneta_port *pp, 5041c5aff182SThomas Petazzoni const struct mbus_dram_target_info *dram) 5042c5aff182SThomas Petazzoni { 5043c5aff182SThomas Petazzoni u32 win_enable; 5044c5aff182SThomas Petazzoni u32 win_protect; 5045c5aff182SThomas Petazzoni int i; 5046c5aff182SThomas Petazzoni 5047c5aff182SThomas Petazzoni for (i = 0; i < 6; i++) { 5048c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_WIN_BASE(i), 0); 5049c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_WIN_SIZE(i), 0); 5050c5aff182SThomas Petazzoni 5051c5aff182SThomas Petazzoni if (i < 4) 5052c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_WIN_REMAP(i), 0); 5053c5aff182SThomas Petazzoni } 5054c5aff182SThomas Petazzoni 5055c5aff182SThomas Petazzoni win_enable = 0x3f; 5056c5aff182SThomas Petazzoni win_protect = 0; 5057c5aff182SThomas Petazzoni 50582636ac3cSMarcin Wojtas if (dram) { 5059c5aff182SThomas Petazzoni for (i = 0; i < dram->num_cs; i++) { 5060c5aff182SThomas Petazzoni const struct mbus_dram_window *cs = dram->cs + i; 50612636ac3cSMarcin Wojtas 50622636ac3cSMarcin Wojtas mvreg_write(pp, MVNETA_WIN_BASE(i), 50632636ac3cSMarcin Wojtas (cs->base & 0xffff0000) | 50642636ac3cSMarcin Wojtas (cs->mbus_attr << 8) | 50652636ac3cSMarcin Wojtas dram->mbus_dram_target_id); 5066c5aff182SThomas Petazzoni 5067c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_WIN_SIZE(i), 5068c5aff182SThomas Petazzoni (cs->size - 1) & 0xffff0000); 5069c5aff182SThomas Petazzoni 5070c5aff182SThomas Petazzoni win_enable &= ~(1 << i); 5071c5aff182SThomas Petazzoni win_protect |= 3 << (2 * i); 5072c5aff182SThomas Petazzoni } 50732636ac3cSMarcin Wojtas } else { 50742636ac3cSMarcin Wojtas /* For Armada3700 open default 4GB Mbus window, leaving 50752636ac3cSMarcin Wojtas * arbitration of target/attribute to a different layer 50762636ac3cSMarcin Wojtas * of configuration. 50772636ac3cSMarcin Wojtas */ 50782636ac3cSMarcin Wojtas mvreg_write(pp, MVNETA_WIN_SIZE(0), 0xffff0000); 50792636ac3cSMarcin Wojtas win_enable &= ~BIT(0); 50802636ac3cSMarcin Wojtas win_protect = 3; 50812636ac3cSMarcin Wojtas } 5082c5aff182SThomas Petazzoni 5083c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_BASE_ADDR_ENABLE, win_enable); 5084db6ba9a5SMarcin Wojtas mvreg_write(pp, MVNETA_ACCESS_PROTECT_ENABLE, win_protect); 5085c5aff182SThomas Petazzoni } 5086c5aff182SThomas Petazzoni 5087c5aff182SThomas Petazzoni /* Power up the port */ 50883f1dd4bcSThomas Petazzoni static int mvneta_port_power_up(struct mvneta_port *pp, int phy_mode) 5089c5aff182SThomas Petazzoni { 5090c5aff182SThomas Petazzoni /* MAC Cause register should be cleared */ 5091c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_UNIT_INTR_CAUSE, 0); 5092c5aff182SThomas Petazzoni 509341c2b6b4SSascha Hauer if (phy_mode != PHY_INTERFACE_MODE_QSGMII && 509441c2b6b4SSascha Hauer phy_mode != PHY_INTERFACE_MODE_SGMII && 509541c2b6b4SSascha Hauer !phy_interface_mode_is_8023z(phy_mode) && 509641c2b6b4SSascha Hauer !phy_interface_mode_is_rgmii(phy_mode)) 50973f1dd4bcSThomas Petazzoni return -EINVAL; 50983f1dd4bcSThomas Petazzoni 50993f1dd4bcSThomas Petazzoni return 0; 5100c5aff182SThomas Petazzoni } 5101c5aff182SThomas Petazzoni 5102c5aff182SThomas Petazzoni /* Device initialization routine */ 510303ce758eSGreg KH static int mvneta_probe(struct platform_device *pdev) 5104c5aff182SThomas Petazzoni { 5105c5aff182SThomas Petazzoni struct device_node *dn = pdev->dev.of_node; 5106dc35a10fSMarcin Wojtas struct device_node *bm_node; 5107c5aff182SThomas Petazzoni struct mvneta_port *pp; 5108c5aff182SThomas Petazzoni struct net_device *dev; 5109503f9aa9SRussell King struct phylink *phylink; 5110a10c1c81SRussell King struct phy *comphy; 51118cc3e439SThomas Petazzoni char hw_mac_addr[ETH_ALEN]; 51120c65b2b9SAndrew Lunn phy_interface_t phy_mode; 51138cc3e439SThomas Petazzoni const char *mac_from; 51149110ee07SMarcin Wojtas int tx_csum_limit; 5115c5aff182SThomas Petazzoni int err; 511612bb03b4SMaxime Ripard int cpu; 5117c5aff182SThomas Petazzoni 5118a3ddd94fSRosen Penev dev = devm_alloc_etherdev_mqs(&pdev->dev, sizeof(struct mvneta_port), 5119a3ddd94fSRosen Penev txq_number, rxq_number); 5120c5aff182SThomas Petazzoni if (!dev) 5121c5aff182SThomas Petazzoni return -ENOMEM; 5122c5aff182SThomas Petazzoni 5123c5aff182SThomas Petazzoni dev->irq = irq_of_parse_and_map(dn, 0); 5124a3ddd94fSRosen Penev if (dev->irq == 0) 5125a3ddd94fSRosen Penev return -EINVAL; 5126c5aff182SThomas Petazzoni 51270c65b2b9SAndrew Lunn err = of_get_phy_mode(dn, &phy_mode); 51280c65b2b9SAndrew Lunn if (err) { 5129c5aff182SThomas Petazzoni dev_err(&pdev->dev, "incorrect phy-mode\n"); 5130503f9aa9SRussell King goto err_free_irq; 5131503f9aa9SRussell King } 5132503f9aa9SRussell King 5133a10c1c81SRussell King comphy = devm_of_phy_get(&pdev->dev, dn, NULL); 5134a10c1c81SRussell King if (comphy == ERR_PTR(-EPROBE_DEFER)) { 5135a10c1c81SRussell King err = -EPROBE_DEFER; 5136a10c1c81SRussell King goto err_free_irq; 5137a10c1c81SRussell King } else if (IS_ERR(comphy)) { 5138a10c1c81SRussell King comphy = NULL; 5139a10c1c81SRussell King } 5140a10c1c81SRussell King 514144cc27e4SIoana Ciornei pp = netdev_priv(dev); 514244cc27e4SIoana Ciornei spin_lock_init(&pp->lock); 514344cc27e4SIoana Ciornei 514444cc27e4SIoana Ciornei pp->phylink_config.dev = &dev->dev; 514544cc27e4SIoana Ciornei pp->phylink_config.type = PHYLINK_NETDEV; 514602a0988bSRussell King (Oracle) pp->phylink_config.mac_capabilities = MAC_SYM_PAUSE | MAC_10 | 514702a0988bSRussell King (Oracle) MAC_100 | MAC_1000FD | MAC_2500FD; 514802a0988bSRussell King (Oracle) 5149fdedb695SRussell King phy_interface_set_rgmii(pp->phylink_config.supported_interfaces); 5150fdedb695SRussell King __set_bit(PHY_INTERFACE_MODE_QSGMII, 5151fdedb695SRussell King pp->phylink_config.supported_interfaces); 5152fdedb695SRussell King if (comphy) { 5153fdedb695SRussell King /* If a COMPHY is present, we can support any of the serdes 5154fdedb695SRussell King * modes and switch between them. 5155fdedb695SRussell King */ 5156fdedb695SRussell King __set_bit(PHY_INTERFACE_MODE_SGMII, 5157fdedb695SRussell King pp->phylink_config.supported_interfaces); 5158fdedb695SRussell King __set_bit(PHY_INTERFACE_MODE_1000BASEX, 5159fdedb695SRussell King pp->phylink_config.supported_interfaces); 5160fdedb695SRussell King __set_bit(PHY_INTERFACE_MODE_2500BASEX, 5161fdedb695SRussell King pp->phylink_config.supported_interfaces); 5162fdedb695SRussell King } else if (phy_mode == PHY_INTERFACE_MODE_2500BASEX) { 5163fdedb695SRussell King /* No COMPHY, with only 2500BASE-X mode supported */ 5164fdedb695SRussell King __set_bit(PHY_INTERFACE_MODE_2500BASEX, 5165fdedb695SRussell King pp->phylink_config.supported_interfaces); 5166fdedb695SRussell King } else if (phy_mode == PHY_INTERFACE_MODE_1000BASEX || 5167fdedb695SRussell King phy_mode == PHY_INTERFACE_MODE_SGMII) { 5168fdedb695SRussell King /* No COMPHY, we can switch between 1000BASE-X and SGMII */ 5169fdedb695SRussell King __set_bit(PHY_INTERFACE_MODE_1000BASEX, 5170fdedb695SRussell King pp->phylink_config.supported_interfaces); 5171fdedb695SRussell King __set_bit(PHY_INTERFACE_MODE_SGMII, 5172fdedb695SRussell King pp->phylink_config.supported_interfaces); 5173fdedb695SRussell King } 517444cc27e4SIoana Ciornei 517544cc27e4SIoana Ciornei phylink = phylink_create(&pp->phylink_config, pdev->dev.fwnode, 517644cc27e4SIoana Ciornei phy_mode, &mvneta_phylink_ops); 5177503f9aa9SRussell King if (IS_ERR(phylink)) { 5178503f9aa9SRussell King err = PTR_ERR(phylink); 5179503f9aa9SRussell King goto err_free_irq; 5180c5aff182SThomas Petazzoni } 5181c5aff182SThomas Petazzoni 5182c5aff182SThomas Petazzoni dev->tx_queue_len = MVNETA_MAX_TXD; 5183c5aff182SThomas Petazzoni dev->watchdog_timeo = 5 * HZ; 5184c5aff182SThomas Petazzoni dev->netdev_ops = &mvneta_netdev_ops; 5185c5aff182SThomas Petazzoni 51867ad24ea4SWilfried Klaebe dev->ethtool_ops = &mvneta_eth_tool_ops; 5187c5aff182SThomas Petazzoni 5188503f9aa9SRussell King pp->phylink = phylink; 5189a10c1c81SRussell King pp->comphy = comphy; 5190c5aff182SThomas Petazzoni pp->phy_interface = phy_mode; 5191503f9aa9SRussell King pp->dn = dn; 5192c5aff182SThomas Petazzoni 519390b74c01SGregory CLEMENT pp->rxq_def = rxq_def; 51949a401deaSGregory CLEMENT pp->indir[0] = rxq_def; 51959a401deaSGregory CLEMENT 51962636ac3cSMarcin Wojtas /* Get special SoC configurations */ 51972636ac3cSMarcin Wojtas if (of_device_is_compatible(dn, "marvell,armada-3700-neta")) 51982636ac3cSMarcin Wojtas pp->neta_armada3700 = true; 51992636ac3cSMarcin Wojtas 52002804ba4eSJisheng Zhang pp->clk = devm_clk_get(&pdev->dev, "core"); 52012804ba4eSJisheng Zhang if (IS_ERR(pp->clk)) 5202189dd626SThomas Petazzoni pp->clk = devm_clk_get(&pdev->dev, NULL); 5203189dd626SThomas Petazzoni if (IS_ERR(pp->clk)) { 5204189dd626SThomas Petazzoni err = PTR_ERR(pp->clk); 5205503f9aa9SRussell King goto err_free_phylink; 5206189dd626SThomas Petazzoni } 5207189dd626SThomas Petazzoni 5208189dd626SThomas Petazzoni clk_prepare_enable(pp->clk); 5209189dd626SThomas Petazzoni 521015cc4a4aSJisheng Zhang pp->clk_bus = devm_clk_get(&pdev->dev, "bus"); 521115cc4a4aSJisheng Zhang if (!IS_ERR(pp->clk_bus)) 521215cc4a4aSJisheng Zhang clk_prepare_enable(pp->clk_bus); 521315cc4a4aSJisheng Zhang 521400c33afbSJisheng Zhang pp->base = devm_platform_ioremap_resource(pdev, 0); 5215c3f0dd38SThomas Petazzoni if (IS_ERR(pp->base)) { 5216c3f0dd38SThomas Petazzoni err = PTR_ERR(pp->base); 52175445eaf3SArnaud Patard \(Rtp\) goto err_clk; 52185445eaf3SArnaud Patard \(Rtp\) } 52195445eaf3SArnaud Patard \(Rtp\) 522012bb03b4SMaxime Ripard /* Alloc per-cpu port structure */ 522112bb03b4SMaxime Ripard pp->ports = alloc_percpu(struct mvneta_pcpu_port); 522212bb03b4SMaxime Ripard if (!pp->ports) { 522312bb03b4SMaxime Ripard err = -ENOMEM; 522412bb03b4SMaxime Ripard goto err_clk; 522512bb03b4SMaxime Ripard } 522612bb03b4SMaxime Ripard 522774c41b04Swilly tarreau /* Alloc per-cpu stats */ 52281c213bd2SWANG Cong pp->stats = netdev_alloc_pcpu_stats(struct mvneta_pcpu_stats); 522974c41b04Swilly tarreau if (!pp->stats) { 523074c41b04Swilly tarreau err = -ENOMEM; 523112bb03b4SMaxime Ripard goto err_free_ports; 523274c41b04Swilly tarreau } 523374c41b04Swilly tarreau 52349ca01b25SJakub Kicinski err = of_get_ethdev_address(dn, dev); 523583216e39SMichael Walle if (!err) { 52368cc3e439SThomas Petazzoni mac_from = "device tree"; 52378cc3e439SThomas Petazzoni } else { 52388cc3e439SThomas Petazzoni mvneta_get_mac_addr(pp, hw_mac_addr); 52398cc3e439SThomas Petazzoni if (is_valid_ether_addr(hw_mac_addr)) { 52408cc3e439SThomas Petazzoni mac_from = "hardware"; 5241a96d317fSJakub Kicinski eth_hw_addr_set(dev, hw_mac_addr); 52428cc3e439SThomas Petazzoni } else { 52438cc3e439SThomas Petazzoni mac_from = "random"; 52448cc3e439SThomas Petazzoni eth_hw_addr_random(dev); 52458cc3e439SThomas Petazzoni } 52468cc3e439SThomas Petazzoni } 52478cc3e439SThomas Petazzoni 52489110ee07SMarcin Wojtas if (!of_property_read_u32(dn, "tx-csum-limit", &tx_csum_limit)) { 52499110ee07SMarcin Wojtas if (tx_csum_limit < 0 || 52509110ee07SMarcin Wojtas tx_csum_limit > MVNETA_TX_CSUM_MAX_SIZE) { 52519110ee07SMarcin Wojtas tx_csum_limit = MVNETA_TX_CSUM_DEF_SIZE; 52529110ee07SMarcin Wojtas dev_info(&pdev->dev, 52539110ee07SMarcin Wojtas "Wrong TX csum limit in DT, set to %dB\n", 52549110ee07SMarcin Wojtas MVNETA_TX_CSUM_DEF_SIZE); 52559110ee07SMarcin Wojtas } 52569110ee07SMarcin Wojtas } else if (of_device_is_compatible(dn, "marvell,armada-370-neta")) { 52579110ee07SMarcin Wojtas tx_csum_limit = MVNETA_TX_CSUM_DEF_SIZE; 52589110ee07SMarcin Wojtas } else { 52599110ee07SMarcin Wojtas tx_csum_limit = MVNETA_TX_CSUM_MAX_SIZE; 52609110ee07SMarcin Wojtas } 52619110ee07SMarcin Wojtas 52629110ee07SMarcin Wojtas pp->tx_csum_limit = tx_csum_limit; 5263b65657fcSSimon Guinot 52649768b45cSJane Li pp->dram_target_info = mv_mbus_dram_info(); 52652636ac3cSMarcin Wojtas /* Armada3700 requires setting default configuration of Mbus 52662636ac3cSMarcin Wojtas * windows, however without using filled mbus_dram_target_info 52672636ac3cSMarcin Wojtas * structure. 52682636ac3cSMarcin Wojtas */ 52699768b45cSJane Li if (pp->dram_target_info || pp->neta_armada3700) 52709768b45cSJane Li mvneta_conf_mbus_windows(pp, pp->dram_target_info); 5271dc35a10fSMarcin Wojtas 5272c5aff182SThomas Petazzoni pp->tx_ring_size = MVNETA_MAX_TXD; 5273c5aff182SThomas Petazzoni pp->rx_ring_size = MVNETA_MAX_RXD; 5274c5aff182SThomas Petazzoni 5275c5aff182SThomas Petazzoni pp->dev = dev; 5276c5aff182SThomas Petazzoni SET_NETDEV_DEV(dev, &pdev->dev); 5277c5aff182SThomas Petazzoni 5278dc35a10fSMarcin Wojtas pp->id = global_port_id++; 5279dc35a10fSMarcin Wojtas 5280dc35a10fSMarcin Wojtas /* Obtain access to BM resources if enabled and already initialized */ 5281dc35a10fSMarcin Wojtas bm_node = of_parse_phandle(dn, "buffer-manager", 0); 5282965cbbecSGregory CLEMENT if (bm_node) { 5283965cbbecSGregory CLEMENT pp->bm_priv = mvneta_bm_get(bm_node); 5284965cbbecSGregory CLEMENT if (pp->bm_priv) { 5285dc35a10fSMarcin Wojtas err = mvneta_bm_port_init(pdev, pp); 5286dc35a10fSMarcin Wojtas if (err < 0) { 5287965cbbecSGregory CLEMENT dev_info(&pdev->dev, 5288965cbbecSGregory CLEMENT "use SW buffer management\n"); 5289965cbbecSGregory CLEMENT mvneta_bm_put(pp->bm_priv); 5290dc35a10fSMarcin Wojtas pp->bm_priv = NULL; 5291dc35a10fSMarcin Wojtas } 5292dc35a10fSMarcin Wojtas } 5293562e2f46SYelena Krivosheev /* Set RX packet offset correction for platforms, whose 5294562e2f46SYelena Krivosheev * NET_SKB_PAD, exceeds 64B. It should be 64B for 64-bit 5295562e2f46SYelena Krivosheev * platforms and 0B for 32-bit ones. 5296562e2f46SYelena Krivosheev */ 5297562e2f46SYelena Krivosheev pp->rx_offset_correction = max(0, 5298562e2f46SYelena Krivosheev NET_SKB_PAD - 5299562e2f46SYelena Krivosheev MVNETA_RX_PKT_OFFSET_CORRECTION); 5300965cbbecSGregory CLEMENT } 5301d4e4da00SPeter Chen of_node_put(bm_node); 5302dc35a10fSMarcin Wojtas 530344efc78dSLorenzo Bianconi /* sw buffer management */ 530444efc78dSLorenzo Bianconi if (!pp->bm_priv) 530544efc78dSLorenzo Bianconi pp->rx_offset_correction = MVNETA_SKB_HEADROOM; 530644efc78dSLorenzo Bianconi 53079672850bSEzequiel Garcia err = mvneta_init(&pdev->dev, pp); 53089672850bSEzequiel Garcia if (err < 0) 5309dc35a10fSMarcin Wojtas goto err_netdev; 53103f1dd4bcSThomas Petazzoni 531141c2b6b4SSascha Hauer err = mvneta_port_power_up(pp, pp->phy_interface); 53123f1dd4bcSThomas Petazzoni if (err < 0) { 53133f1dd4bcSThomas Petazzoni dev_err(&pdev->dev, "can't power up port\n"); 531458f60329SDinghao Liu goto err_netdev; 53153f1dd4bcSThomas Petazzoni } 5316c5aff182SThomas Petazzoni 53172636ac3cSMarcin Wojtas /* Armada3700 network controller does not support per-cpu 53182636ac3cSMarcin Wojtas * operation, so only single NAPI should be initialized. 53192636ac3cSMarcin Wojtas */ 53202636ac3cSMarcin Wojtas if (pp->neta_armada3700) { 53212636ac3cSMarcin Wojtas netif_napi_add(dev, &pp->napi, mvneta_poll, NAPI_POLL_WEIGHT); 53222636ac3cSMarcin Wojtas } else { 532312bb03b4SMaxime Ripard for_each_present_cpu(cpu) { 53242636ac3cSMarcin Wojtas struct mvneta_pcpu_port *port = 53252636ac3cSMarcin Wojtas per_cpu_ptr(pp->ports, cpu); 532612bb03b4SMaxime Ripard 53272636ac3cSMarcin Wojtas netif_napi_add(dev, &port->napi, mvneta_poll, 53282636ac3cSMarcin Wojtas NAPI_POLL_WEIGHT); 532912bb03b4SMaxime Ripard port->pp = pp; 533012bb03b4SMaxime Ripard } 53312636ac3cSMarcin Wojtas } 5332c5aff182SThomas Petazzoni 53337772988aSJisheng Zhang dev->features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | 53347772988aSJisheng Zhang NETIF_F_TSO | NETIF_F_RXCSUM; 533501ef26caSEzequiel Garcia dev->hw_features |= dev->features; 533601ef26caSEzequiel Garcia dev->vlan_features |= dev->features; 533797db8afaSAndrew Lunn dev->priv_flags |= IFF_LIVE_ADDR_CHANGE; 53388eef5f97SEzequiel Garcia dev->gso_max_segs = MVNETA_MAX_TSO_SEGS; 5339b50b72deSwilly tarreau 53405777987eSJarod Wilson /* MTU range: 68 - 9676 */ 53415777987eSJarod Wilson dev->min_mtu = ETH_MIN_MTU; 53425777987eSJarod Wilson /* 9676 == 9700 - 20 and rounding to 8 */ 53435777987eSJarod Wilson dev->max_mtu = 9676; 53445777987eSJarod Wilson 5345c5aff182SThomas Petazzoni err = register_netdev(dev); 5346c5aff182SThomas Petazzoni if (err < 0) { 5347c5aff182SThomas Petazzoni dev_err(&pdev->dev, "failed to register\n"); 5348d484e06eSJisheng Zhang goto err_netdev; 5349c5aff182SThomas Petazzoni } 5350c5aff182SThomas Petazzoni 53518cc3e439SThomas Petazzoni netdev_info(dev, "Using %s mac address %pM\n", mac_from, 53528cc3e439SThomas Petazzoni dev->dev_addr); 5353c5aff182SThomas Petazzoni 5354c5aff182SThomas Petazzoni platform_set_drvdata(pdev, pp->dev); 5355c5aff182SThomas Petazzoni 5356c5aff182SThomas Petazzoni return 0; 5357c5aff182SThomas Petazzoni 5358dc35a10fSMarcin Wojtas err_netdev: 5359dc35a10fSMarcin Wojtas if (pp->bm_priv) { 5360dc35a10fSMarcin Wojtas mvneta_bm_pool_destroy(pp->bm_priv, pp->pool_long, 1 << pp->id); 5361dc35a10fSMarcin Wojtas mvneta_bm_pool_destroy(pp->bm_priv, pp->pool_short, 5362dc35a10fSMarcin Wojtas 1 << pp->id); 5363965cbbecSGregory CLEMENT mvneta_bm_put(pp->bm_priv); 5364dc35a10fSMarcin Wojtas } 536574c41b04Swilly tarreau free_percpu(pp->stats); 536612bb03b4SMaxime Ripard err_free_ports: 536712bb03b4SMaxime Ripard free_percpu(pp->ports); 53685445eaf3SArnaud Patard \(Rtp\) err_clk: 536915cc4a4aSJisheng Zhang clk_disable_unprepare(pp->clk_bus); 53705445eaf3SArnaud Patard \(Rtp\) clk_disable_unprepare(pp->clk); 5371503f9aa9SRussell King err_free_phylink: 5372503f9aa9SRussell King if (pp->phylink) 5373503f9aa9SRussell King phylink_destroy(pp->phylink); 5374c5aff182SThomas Petazzoni err_free_irq: 5375c5aff182SThomas Petazzoni irq_dispose_mapping(dev->irq); 5376c5aff182SThomas Petazzoni return err; 5377c5aff182SThomas Petazzoni } 5378c5aff182SThomas Petazzoni 5379c5aff182SThomas Petazzoni /* Device removal routine */ 538003ce758eSGreg KH static int mvneta_remove(struct platform_device *pdev) 5381c5aff182SThomas Petazzoni { 5382c5aff182SThomas Petazzoni struct net_device *dev = platform_get_drvdata(pdev); 5383c5aff182SThomas Petazzoni struct mvneta_port *pp = netdev_priv(dev); 5384c5aff182SThomas Petazzoni 5385c5aff182SThomas Petazzoni unregister_netdev(dev); 538615cc4a4aSJisheng Zhang clk_disable_unprepare(pp->clk_bus); 5387189dd626SThomas Petazzoni clk_disable_unprepare(pp->clk); 538812bb03b4SMaxime Ripard free_percpu(pp->ports); 538974c41b04Swilly tarreau free_percpu(pp->stats); 5390c5aff182SThomas Petazzoni irq_dispose_mapping(dev->irq); 5391503f9aa9SRussell King phylink_destroy(pp->phylink); 5392c5aff182SThomas Petazzoni 5393dc35a10fSMarcin Wojtas if (pp->bm_priv) { 5394dc35a10fSMarcin Wojtas mvneta_bm_pool_destroy(pp->bm_priv, pp->pool_long, 1 << pp->id); 5395dc35a10fSMarcin Wojtas mvneta_bm_pool_destroy(pp->bm_priv, pp->pool_short, 5396dc35a10fSMarcin Wojtas 1 << pp->id); 5397965cbbecSGregory CLEMENT mvneta_bm_put(pp->bm_priv); 5398dc35a10fSMarcin Wojtas } 5399dc35a10fSMarcin Wojtas 5400c5aff182SThomas Petazzoni return 0; 5401c5aff182SThomas Petazzoni } 5402c5aff182SThomas Petazzoni 54039768b45cSJane Li #ifdef CONFIG_PM_SLEEP 54049768b45cSJane Li static int mvneta_suspend(struct device *device) 54059768b45cSJane Li { 54061799cdd2SJisheng Zhang int queue; 54079768b45cSJane Li struct net_device *dev = dev_get_drvdata(device); 54089768b45cSJane Li struct mvneta_port *pp = netdev_priv(dev); 54099768b45cSJane Li 54101799cdd2SJisheng Zhang if (!netif_running(dev)) 54111799cdd2SJisheng Zhang goto clean_exit; 54121799cdd2SJisheng Zhang 54131799cdd2SJisheng Zhang if (!pp->neta_armada3700) { 54141799cdd2SJisheng Zhang spin_lock(&pp->lock); 54151799cdd2SJisheng Zhang pp->is_stopped = true; 54161799cdd2SJisheng Zhang spin_unlock(&pp->lock); 54171799cdd2SJisheng Zhang 54181799cdd2SJisheng Zhang cpuhp_state_remove_instance_nocalls(online_hpstate, 54191799cdd2SJisheng Zhang &pp->node_online); 54201799cdd2SJisheng Zhang cpuhp_state_remove_instance_nocalls(CPUHP_NET_MVNETA_DEAD, 54211799cdd2SJisheng Zhang &pp->node_dead); 54221799cdd2SJisheng Zhang } 54231799cdd2SJisheng Zhang 54243b8bc674SRussell King rtnl_lock(); 54251799cdd2SJisheng Zhang mvneta_stop_dev(pp); 54263b8bc674SRussell King rtnl_unlock(); 54271799cdd2SJisheng Zhang 54281799cdd2SJisheng Zhang for (queue = 0; queue < rxq_number; queue++) { 54291799cdd2SJisheng Zhang struct mvneta_rx_queue *rxq = &pp->rxqs[queue]; 54301799cdd2SJisheng Zhang 54311799cdd2SJisheng Zhang mvneta_rxq_drop_pkts(pp, rxq); 54321799cdd2SJisheng Zhang } 54331799cdd2SJisheng Zhang 54341799cdd2SJisheng Zhang for (queue = 0; queue < txq_number; queue++) { 54351799cdd2SJisheng Zhang struct mvneta_tx_queue *txq = &pp->txqs[queue]; 54361799cdd2SJisheng Zhang 54371799cdd2SJisheng Zhang mvneta_txq_hw_deinit(pp, txq); 54381799cdd2SJisheng Zhang } 54391799cdd2SJisheng Zhang 54401799cdd2SJisheng Zhang clean_exit: 54419768b45cSJane Li netif_device_detach(dev); 54429768b45cSJane Li clk_disable_unprepare(pp->clk_bus); 54439768b45cSJane Li clk_disable_unprepare(pp->clk); 54441799cdd2SJisheng Zhang 54459768b45cSJane Li return 0; 54469768b45cSJane Li } 54479768b45cSJane Li 54489768b45cSJane Li static int mvneta_resume(struct device *device) 54499768b45cSJane Li { 54509768b45cSJane Li struct platform_device *pdev = to_platform_device(device); 54519768b45cSJane Li struct net_device *dev = dev_get_drvdata(device); 54529768b45cSJane Li struct mvneta_port *pp = netdev_priv(dev); 54531799cdd2SJisheng Zhang int err, queue; 54549768b45cSJane Li 54559768b45cSJane Li clk_prepare_enable(pp->clk); 54569768b45cSJane Li if (!IS_ERR(pp->clk_bus)) 54579768b45cSJane Li clk_prepare_enable(pp->clk_bus); 54589768b45cSJane Li if (pp->dram_target_info || pp->neta_armada3700) 54599768b45cSJane Li mvneta_conf_mbus_windows(pp, pp->dram_target_info); 54609768b45cSJane Li if (pp->bm_priv) { 54619768b45cSJane Li err = mvneta_bm_port_init(pdev, pp); 54629768b45cSJane Li if (err < 0) { 54639768b45cSJane Li dev_info(&pdev->dev, "use SW buffer management\n"); 546444efc78dSLorenzo Bianconi pp->rx_offset_correction = MVNETA_SKB_HEADROOM; 54659768b45cSJane Li pp->bm_priv = NULL; 54669768b45cSJane Li } 54679768b45cSJane Li } 54689768b45cSJane Li mvneta_defaults_set(pp); 54699768b45cSJane Li err = mvneta_port_power_up(pp, pp->phy_interface); 54709768b45cSJane Li if (err < 0) { 54719768b45cSJane Li dev_err(device, "can't power up port\n"); 54729768b45cSJane Li return err; 54739768b45cSJane Li } 54749768b45cSJane Li 54759768b45cSJane Li netif_device_attach(dev); 54761799cdd2SJisheng Zhang 54771799cdd2SJisheng Zhang if (!netif_running(dev)) 54781799cdd2SJisheng Zhang return 0; 54791799cdd2SJisheng Zhang 54801799cdd2SJisheng Zhang for (queue = 0; queue < rxq_number; queue++) { 54811799cdd2SJisheng Zhang struct mvneta_rx_queue *rxq = &pp->rxqs[queue]; 54821799cdd2SJisheng Zhang 54831799cdd2SJisheng Zhang rxq->next_desc_to_proc = 0; 54841799cdd2SJisheng Zhang mvneta_rxq_hw_init(pp, rxq); 5485d6956ac8SJisheng Zhang } 54861799cdd2SJisheng Zhang 54871799cdd2SJisheng Zhang for (queue = 0; queue < txq_number; queue++) { 54881799cdd2SJisheng Zhang struct mvneta_tx_queue *txq = &pp->txqs[queue]; 54891799cdd2SJisheng Zhang 54901799cdd2SJisheng Zhang txq->next_desc_to_proc = 0; 54911799cdd2SJisheng Zhang mvneta_txq_hw_init(pp, txq); 54921799cdd2SJisheng Zhang } 54931799cdd2SJisheng Zhang 54941799cdd2SJisheng Zhang if (!pp->neta_armada3700) { 54951799cdd2SJisheng Zhang spin_lock(&pp->lock); 54961799cdd2SJisheng Zhang pp->is_stopped = false; 54971799cdd2SJisheng Zhang spin_unlock(&pp->lock); 54981799cdd2SJisheng Zhang cpuhp_state_add_instance_nocalls(online_hpstate, 54991799cdd2SJisheng Zhang &pp->node_online); 55001799cdd2SJisheng Zhang cpuhp_state_add_instance_nocalls(CPUHP_NET_MVNETA_DEAD, 55011799cdd2SJisheng Zhang &pp->node_dead); 55021799cdd2SJisheng Zhang } 55031799cdd2SJisheng Zhang 55041799cdd2SJisheng Zhang rtnl_lock(); 55051799cdd2SJisheng Zhang mvneta_start_dev(pp); 55063b8bc674SRussell King rtnl_unlock(); 55071799cdd2SJisheng Zhang mvneta_set_rx_mode(dev); 5508d6956ac8SJisheng Zhang 55099768b45cSJane Li return 0; 55109768b45cSJane Li } 55119768b45cSJane Li #endif 55129768b45cSJane Li 55139768b45cSJane Li static SIMPLE_DEV_PM_OPS(mvneta_pm_ops, mvneta_suspend, mvneta_resume); 55149768b45cSJane Li 5515c5aff182SThomas Petazzoni static const struct of_device_id mvneta_match[] = { 5516c5aff182SThomas Petazzoni { .compatible = "marvell,armada-370-neta" }, 5517f522a975SSimon Guinot { .compatible = "marvell,armada-xp-neta" }, 55182636ac3cSMarcin Wojtas { .compatible = "marvell,armada-3700-neta" }, 5519c5aff182SThomas Petazzoni { } 5520c5aff182SThomas Petazzoni }; 5521c5aff182SThomas Petazzoni MODULE_DEVICE_TABLE(of, mvneta_match); 5522c5aff182SThomas Petazzoni 5523c5aff182SThomas Petazzoni static struct platform_driver mvneta_driver = { 5524c5aff182SThomas Petazzoni .probe = mvneta_probe, 552503ce758eSGreg KH .remove = mvneta_remove, 5526c5aff182SThomas Petazzoni .driver = { 5527c5aff182SThomas Petazzoni .name = MVNETA_DRIVER_NAME, 5528c5aff182SThomas Petazzoni .of_match_table = mvneta_match, 55299768b45cSJane Li .pm = &mvneta_pm_ops, 5530c5aff182SThomas Petazzoni }, 5531c5aff182SThomas Petazzoni }; 5532c5aff182SThomas Petazzoni 553384a3f4dbSSebastian Andrzej Siewior static int __init mvneta_driver_init(void) 553484a3f4dbSSebastian Andrzej Siewior { 553584a3f4dbSSebastian Andrzej Siewior int ret; 553684a3f4dbSSebastian Andrzej Siewior 5537664d035cSChristophe JAILLET ret = cpuhp_setup_state_multi(CPUHP_AP_ONLINE_DYN, "net/mvneta:online", 553884a3f4dbSSebastian Andrzej Siewior mvneta_cpu_online, 553984a3f4dbSSebastian Andrzej Siewior mvneta_cpu_down_prepare); 554084a3f4dbSSebastian Andrzej Siewior if (ret < 0) 554184a3f4dbSSebastian Andrzej Siewior goto out; 554284a3f4dbSSebastian Andrzej Siewior online_hpstate = ret; 554384a3f4dbSSebastian Andrzej Siewior ret = cpuhp_setup_state_multi(CPUHP_NET_MVNETA_DEAD, "net/mvneta:dead", 554484a3f4dbSSebastian Andrzej Siewior NULL, mvneta_cpu_dead); 554584a3f4dbSSebastian Andrzej Siewior if (ret) 554684a3f4dbSSebastian Andrzej Siewior goto err_dead; 554784a3f4dbSSebastian Andrzej Siewior 554884a3f4dbSSebastian Andrzej Siewior ret = platform_driver_register(&mvneta_driver); 554984a3f4dbSSebastian Andrzej Siewior if (ret) 555084a3f4dbSSebastian Andrzej Siewior goto err; 555184a3f4dbSSebastian Andrzej Siewior return 0; 555284a3f4dbSSebastian Andrzej Siewior 555384a3f4dbSSebastian Andrzej Siewior err: 555484a3f4dbSSebastian Andrzej Siewior cpuhp_remove_multi_state(CPUHP_NET_MVNETA_DEAD); 555584a3f4dbSSebastian Andrzej Siewior err_dead: 555684a3f4dbSSebastian Andrzej Siewior cpuhp_remove_multi_state(online_hpstate); 555784a3f4dbSSebastian Andrzej Siewior out: 555884a3f4dbSSebastian Andrzej Siewior return ret; 555984a3f4dbSSebastian Andrzej Siewior } 556084a3f4dbSSebastian Andrzej Siewior module_init(mvneta_driver_init); 556184a3f4dbSSebastian Andrzej Siewior 556284a3f4dbSSebastian Andrzej Siewior static void __exit mvneta_driver_exit(void) 556384a3f4dbSSebastian Andrzej Siewior { 556484a3f4dbSSebastian Andrzej Siewior platform_driver_unregister(&mvneta_driver); 556584a3f4dbSSebastian Andrzej Siewior cpuhp_remove_multi_state(CPUHP_NET_MVNETA_DEAD); 556684a3f4dbSSebastian Andrzej Siewior cpuhp_remove_multi_state(online_hpstate); 556784a3f4dbSSebastian Andrzej Siewior } 556884a3f4dbSSebastian Andrzej Siewior module_exit(mvneta_driver_exit); 5569c5aff182SThomas Petazzoni 5570c5aff182SThomas Petazzoni MODULE_DESCRIPTION("Marvell NETA Ethernet Driver - www.marvell.com"); 5571c5aff182SThomas Petazzoni MODULE_AUTHOR("Rami Rosen <rosenr@marvell.com>, Thomas Petazzoni <thomas.petazzoni@free-electrons.com>"); 5572c5aff182SThomas Petazzoni MODULE_LICENSE("GPL"); 5573c5aff182SThomas Petazzoni 5574d3757ba4SJoe Perches module_param(rxq_number, int, 0444); 5575d3757ba4SJoe Perches module_param(txq_number, int, 0444); 5576c5aff182SThomas Petazzoni 5577d3757ba4SJoe Perches module_param(rxq_def, int, 0444); 5578d3757ba4SJoe Perches module_param(rx_copybreak, int, 0644); 5579