1c5aff182SThomas Petazzoni /* 2c5aff182SThomas Petazzoni * Driver for Marvell NETA network card for Armada XP and Armada 370 SoCs. 3c5aff182SThomas Petazzoni * 4c5aff182SThomas Petazzoni * Copyright (C) 2012 Marvell 5c5aff182SThomas Petazzoni * 6c5aff182SThomas Petazzoni * Rami Rosen <rosenr@marvell.com> 7c5aff182SThomas Petazzoni * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> 8c5aff182SThomas Petazzoni * 9c5aff182SThomas Petazzoni * This file is licensed under the terms of the GNU General Public 10c5aff182SThomas Petazzoni * License version 2. This program is licensed "as is" without any 11c5aff182SThomas Petazzoni * warranty of any kind, whether express or implied. 12c5aff182SThomas Petazzoni */ 13c5aff182SThomas Petazzoni 140e03f563SJisheng Zhang #include <linux/clk.h> 150e03f563SJisheng Zhang #include <linux/cpu.h> 16c5aff182SThomas Petazzoni #include <linux/etherdevice.h> 170e03f563SJisheng Zhang #include <linux/if_vlan.h> 18c5aff182SThomas Petazzoni #include <linux/inetdevice.h> 190e03f563SJisheng Zhang #include <linux/interrupt.h> 200e03f563SJisheng Zhang #include <linux/io.h> 210e03f563SJisheng Zhang #include <linux/kernel.h> 22c5aff182SThomas Petazzoni #include <linux/mbus.h> 23c5aff182SThomas Petazzoni #include <linux/module.h> 240e03f563SJisheng Zhang #include <linux/netdevice.h> 25c5aff182SThomas Petazzoni #include <linux/of.h> 260e03f563SJisheng Zhang #include <linux/of_address.h> 27c5aff182SThomas Petazzoni #include <linux/of_irq.h> 28c5aff182SThomas Petazzoni #include <linux/of_mdio.h> 29c5aff182SThomas Petazzoni #include <linux/of_net.h> 30a10c1c81SRussell King #include <linux/phy/phy.h> 31c5aff182SThomas Petazzoni #include <linux/phy.h> 32503f9aa9SRussell King #include <linux/phylink.h> 330e03f563SJisheng Zhang #include <linux/platform_device.h> 340e03f563SJisheng Zhang #include <linux/skbuff.h> 35baa11ebcSGregory CLEMENT #include <net/hwbm.h> 36dc35a10fSMarcin Wojtas #include "mvneta_bm.h" 370e03f563SJisheng Zhang #include <net/ip.h> 380e03f563SJisheng Zhang #include <net/ipv6.h> 390e03f563SJisheng Zhang #include <net/tso.h> 40568a3fa2SLorenzo Bianconi #include <net/page_pool.h> 410db51da7SLorenzo Bianconi #include <linux/bpf_trace.h> 42c5aff182SThomas Petazzoni 43c5aff182SThomas Petazzoni /* Registers */ 44c5aff182SThomas Petazzoni #define MVNETA_RXQ_CONFIG_REG(q) (0x1400 + ((q) << 2)) 45e5bdf689SMarcin Wojtas #define MVNETA_RXQ_HW_BUF_ALLOC BIT(0) 46dc35a10fSMarcin Wojtas #define MVNETA_RXQ_SHORT_POOL_ID_SHIFT 4 47dc35a10fSMarcin Wojtas #define MVNETA_RXQ_SHORT_POOL_ID_MASK 0x30 48dc35a10fSMarcin Wojtas #define MVNETA_RXQ_LONG_POOL_ID_SHIFT 6 49dc35a10fSMarcin Wojtas #define MVNETA_RXQ_LONG_POOL_ID_MASK 0xc0 50c5aff182SThomas Petazzoni #define MVNETA_RXQ_PKT_OFFSET_ALL_MASK (0xf << 8) 51c5aff182SThomas Petazzoni #define MVNETA_RXQ_PKT_OFFSET_MASK(offs) ((offs) << 8) 52c5aff182SThomas Petazzoni #define MVNETA_RXQ_THRESHOLD_REG(q) (0x14c0 + ((q) << 2)) 53c5aff182SThomas Petazzoni #define MVNETA_RXQ_NON_OCCUPIED(v) ((v) << 16) 54c5aff182SThomas Petazzoni #define MVNETA_RXQ_BASE_ADDR_REG(q) (0x1480 + ((q) << 2)) 55c5aff182SThomas Petazzoni #define MVNETA_RXQ_SIZE_REG(q) (0x14a0 + ((q) << 2)) 56c5aff182SThomas Petazzoni #define MVNETA_RXQ_BUF_SIZE_SHIFT 19 57c5aff182SThomas Petazzoni #define MVNETA_RXQ_BUF_SIZE_MASK (0x1fff << 19) 58c5aff182SThomas Petazzoni #define MVNETA_RXQ_STATUS_REG(q) (0x14e0 + ((q) << 2)) 59c5aff182SThomas Petazzoni #define MVNETA_RXQ_OCCUPIED_ALL_MASK 0x3fff 60c5aff182SThomas Petazzoni #define MVNETA_RXQ_STATUS_UPDATE_REG(q) (0x1500 + ((q) << 2)) 61c5aff182SThomas Petazzoni #define MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT 16 62c5aff182SThomas Petazzoni #define MVNETA_RXQ_ADD_NON_OCCUPIED_MAX 255 63dc35a10fSMarcin Wojtas #define MVNETA_PORT_POOL_BUFFER_SZ_REG(pool) (0x1700 + ((pool) << 2)) 64dc35a10fSMarcin Wojtas #define MVNETA_PORT_POOL_BUFFER_SZ_SHIFT 3 65dc35a10fSMarcin Wojtas #define MVNETA_PORT_POOL_BUFFER_SZ_MASK 0xfff8 66c5aff182SThomas Petazzoni #define MVNETA_PORT_RX_RESET 0x1cc0 67c5aff182SThomas Petazzoni #define MVNETA_PORT_RX_DMA_RESET BIT(0) 68c5aff182SThomas Petazzoni #define MVNETA_PHY_ADDR 0x2000 69c5aff182SThomas Petazzoni #define MVNETA_PHY_ADDR_MASK 0x1f 70c5aff182SThomas Petazzoni #define MVNETA_MBUS_RETRY 0x2010 71c5aff182SThomas Petazzoni #define MVNETA_UNIT_INTR_CAUSE 0x2080 72c5aff182SThomas Petazzoni #define MVNETA_UNIT_CONTROL 0x20B0 73c5aff182SThomas Petazzoni #define MVNETA_PHY_POLLING_ENABLE BIT(1) 74c5aff182SThomas Petazzoni #define MVNETA_WIN_BASE(w) (0x2200 + ((w) << 3)) 75c5aff182SThomas Petazzoni #define MVNETA_WIN_SIZE(w) (0x2204 + ((w) << 3)) 76c5aff182SThomas Petazzoni #define MVNETA_WIN_REMAP(w) (0x2280 + ((w) << 2)) 77c5aff182SThomas Petazzoni #define MVNETA_BASE_ADDR_ENABLE 0x2290 78db6ba9a5SMarcin Wojtas #define MVNETA_ACCESS_PROTECT_ENABLE 0x2294 79c5aff182SThomas Petazzoni #define MVNETA_PORT_CONFIG 0x2400 80c5aff182SThomas Petazzoni #define MVNETA_UNI_PROMISC_MODE BIT(0) 81c5aff182SThomas Petazzoni #define MVNETA_DEF_RXQ(q) ((q) << 1) 82c5aff182SThomas Petazzoni #define MVNETA_DEF_RXQ_ARP(q) ((q) << 4) 83c5aff182SThomas Petazzoni #define MVNETA_TX_UNSET_ERR_SUM BIT(12) 84c5aff182SThomas Petazzoni #define MVNETA_DEF_RXQ_TCP(q) ((q) << 16) 85c5aff182SThomas Petazzoni #define MVNETA_DEF_RXQ_UDP(q) ((q) << 19) 86c5aff182SThomas Petazzoni #define MVNETA_DEF_RXQ_BPDU(q) ((q) << 22) 87c5aff182SThomas Petazzoni #define MVNETA_RX_CSUM_WITH_PSEUDO_HDR BIT(25) 88c5aff182SThomas Petazzoni #define MVNETA_PORT_CONFIG_DEFL_VALUE(q) (MVNETA_DEF_RXQ(q) | \ 89c5aff182SThomas Petazzoni MVNETA_DEF_RXQ_ARP(q) | \ 90c5aff182SThomas Petazzoni MVNETA_DEF_RXQ_TCP(q) | \ 91c5aff182SThomas Petazzoni MVNETA_DEF_RXQ_UDP(q) | \ 92c5aff182SThomas Petazzoni MVNETA_DEF_RXQ_BPDU(q) | \ 93c5aff182SThomas Petazzoni MVNETA_TX_UNSET_ERR_SUM | \ 94c5aff182SThomas Petazzoni MVNETA_RX_CSUM_WITH_PSEUDO_HDR) 95c5aff182SThomas Petazzoni #define MVNETA_PORT_CONFIG_EXTEND 0x2404 96c5aff182SThomas Petazzoni #define MVNETA_MAC_ADDR_LOW 0x2414 97c5aff182SThomas Petazzoni #define MVNETA_MAC_ADDR_HIGH 0x2418 98c5aff182SThomas Petazzoni #define MVNETA_SDMA_CONFIG 0x241c 99c5aff182SThomas Petazzoni #define MVNETA_SDMA_BRST_SIZE_16 4 100c5aff182SThomas Petazzoni #define MVNETA_RX_BRST_SZ_MASK(burst) ((burst) << 1) 101c5aff182SThomas Petazzoni #define MVNETA_RX_NO_DATA_SWAP BIT(4) 102c5aff182SThomas Petazzoni #define MVNETA_TX_NO_DATA_SWAP BIT(5) 1039ad8fef6SThomas Petazzoni #define MVNETA_DESC_SWAP BIT(6) 104c5aff182SThomas Petazzoni #define MVNETA_TX_BRST_SZ_MASK(burst) ((burst) << 22) 105c5aff182SThomas Petazzoni #define MVNETA_PORT_STATUS 0x2444 106c5aff182SThomas Petazzoni #define MVNETA_TX_IN_PRGRS BIT(1) 107c5aff182SThomas Petazzoni #define MVNETA_TX_FIFO_EMPTY BIT(8) 108c5aff182SThomas Petazzoni #define MVNETA_RX_MIN_FRAME_SIZE 0x247c 1093f1dd4bcSThomas Petazzoni #define MVNETA_SERDES_CFG 0x24A0 1105445eaf3SArnaud Patard \(Rtp\) #define MVNETA_SGMII_SERDES_PROTO 0x0cc7 1113f1dd4bcSThomas Petazzoni #define MVNETA_QSGMII_SERDES_PROTO 0x0667 112c5aff182SThomas Petazzoni #define MVNETA_TYPE_PRIO 0x24bc 113c5aff182SThomas Petazzoni #define MVNETA_FORCE_UNI BIT(21) 114c5aff182SThomas Petazzoni #define MVNETA_TXQ_CMD_1 0x24e4 115c5aff182SThomas Petazzoni #define MVNETA_TXQ_CMD 0x2448 116c5aff182SThomas Petazzoni #define MVNETA_TXQ_DISABLE_SHIFT 8 117c5aff182SThomas Petazzoni #define MVNETA_TXQ_ENABLE_MASK 0x000000ff 118e483911fSAndrew Lunn #define MVNETA_RX_DISCARD_FRAME_COUNT 0x2484 119e483911fSAndrew Lunn #define MVNETA_OVERRUN_FRAME_COUNT 0x2488 120898b2970SStas Sergeev #define MVNETA_GMAC_CLOCK_DIVIDER 0x24f4 121898b2970SStas Sergeev #define MVNETA_GMAC_1MS_CLOCK_ENABLE BIT(31) 122c5aff182SThomas Petazzoni #define MVNETA_ACC_MODE 0x2500 123dc35a10fSMarcin Wojtas #define MVNETA_BM_ADDRESS 0x2504 124c5aff182SThomas Petazzoni #define MVNETA_CPU_MAP(cpu) (0x2540 + ((cpu) << 2)) 125c5aff182SThomas Petazzoni #define MVNETA_CPU_RXQ_ACCESS_ALL_MASK 0x000000ff 126c5aff182SThomas Petazzoni #define MVNETA_CPU_TXQ_ACCESS_ALL_MASK 0x0000ff00 1272dcf75e2SGregory CLEMENT #define MVNETA_CPU_RXQ_ACCESS(rxq) BIT(rxq) 12850bf8cb6SGregory CLEMENT #define MVNETA_CPU_TXQ_ACCESS(txq) BIT(txq + 8) 129c5aff182SThomas Petazzoni #define MVNETA_RXQ_TIME_COAL_REG(q) (0x2580 + ((q) << 2)) 13040ba35e7Swilly tarreau 1312dcf75e2SGregory CLEMENT /* Exception Interrupt Port/Queue Cause register 1322dcf75e2SGregory CLEMENT * 1332dcf75e2SGregory CLEMENT * Their behavior depend of the mapping done using the PCPX2Q 1342dcf75e2SGregory CLEMENT * registers. For a given CPU if the bit associated to a queue is not 1352dcf75e2SGregory CLEMENT * set, then for the register a read from this CPU will always return 1362dcf75e2SGregory CLEMENT * 0 and a write won't do anything 1372dcf75e2SGregory CLEMENT */ 13840ba35e7Swilly tarreau 139c5aff182SThomas Petazzoni #define MVNETA_INTR_NEW_CAUSE 0x25a0 140c5aff182SThomas Petazzoni #define MVNETA_INTR_NEW_MASK 0x25a4 14140ba35e7Swilly tarreau 14240ba35e7Swilly tarreau /* bits 0..7 = TXQ SENT, one bit per queue. 14340ba35e7Swilly tarreau * bits 8..15 = RXQ OCCUP, one bit per queue. 14440ba35e7Swilly tarreau * bits 16..23 = RXQ FREE, one bit per queue. 14540ba35e7Swilly tarreau * bit 29 = OLD_REG_SUM, see old reg ? 14640ba35e7Swilly tarreau * bit 30 = TX_ERR_SUM, one bit for 4 ports 14740ba35e7Swilly tarreau * bit 31 = MISC_SUM, one bit for 4 ports 14840ba35e7Swilly tarreau */ 14940ba35e7Swilly tarreau #define MVNETA_TX_INTR_MASK(nr_txqs) (((1 << nr_txqs) - 1) << 0) 15040ba35e7Swilly tarreau #define MVNETA_TX_INTR_MASK_ALL (0xff << 0) 15140ba35e7Swilly tarreau #define MVNETA_RX_INTR_MASK(nr_rxqs) (((1 << nr_rxqs) - 1) << 8) 15240ba35e7Swilly tarreau #define MVNETA_RX_INTR_MASK_ALL (0xff << 8) 153898b2970SStas Sergeev #define MVNETA_MISCINTR_INTR_MASK BIT(31) 15440ba35e7Swilly tarreau 155c5aff182SThomas Petazzoni #define MVNETA_INTR_OLD_CAUSE 0x25a8 156c5aff182SThomas Petazzoni #define MVNETA_INTR_OLD_MASK 0x25ac 15740ba35e7Swilly tarreau 15840ba35e7Swilly tarreau /* Data Path Port/Queue Cause Register */ 159c5aff182SThomas Petazzoni #define MVNETA_INTR_MISC_CAUSE 0x25b0 160c5aff182SThomas Petazzoni #define MVNETA_INTR_MISC_MASK 0x25b4 16140ba35e7Swilly tarreau 16240ba35e7Swilly tarreau #define MVNETA_CAUSE_PHY_STATUS_CHANGE BIT(0) 16340ba35e7Swilly tarreau #define MVNETA_CAUSE_LINK_CHANGE BIT(1) 16440ba35e7Swilly tarreau #define MVNETA_CAUSE_PTP BIT(4) 16540ba35e7Swilly tarreau 16640ba35e7Swilly tarreau #define MVNETA_CAUSE_INTERNAL_ADDR_ERR BIT(7) 16740ba35e7Swilly tarreau #define MVNETA_CAUSE_RX_OVERRUN BIT(8) 16840ba35e7Swilly tarreau #define MVNETA_CAUSE_RX_CRC_ERROR BIT(9) 16940ba35e7Swilly tarreau #define MVNETA_CAUSE_RX_LARGE_PKT BIT(10) 17040ba35e7Swilly tarreau #define MVNETA_CAUSE_TX_UNDERUN BIT(11) 17140ba35e7Swilly tarreau #define MVNETA_CAUSE_PRBS_ERR BIT(12) 17240ba35e7Swilly tarreau #define MVNETA_CAUSE_PSC_SYNC_CHANGE BIT(13) 17340ba35e7Swilly tarreau #define MVNETA_CAUSE_SERDES_SYNC_ERR BIT(14) 17440ba35e7Swilly tarreau 17540ba35e7Swilly tarreau #define MVNETA_CAUSE_BMU_ALLOC_ERR_SHIFT 16 17640ba35e7Swilly tarreau #define MVNETA_CAUSE_BMU_ALLOC_ERR_ALL_MASK (0xF << MVNETA_CAUSE_BMU_ALLOC_ERR_SHIFT) 17740ba35e7Swilly tarreau #define MVNETA_CAUSE_BMU_ALLOC_ERR_MASK(pool) (1 << (MVNETA_CAUSE_BMU_ALLOC_ERR_SHIFT + (pool))) 17840ba35e7Swilly tarreau 17940ba35e7Swilly tarreau #define MVNETA_CAUSE_TXQ_ERROR_SHIFT 24 18040ba35e7Swilly tarreau #define MVNETA_CAUSE_TXQ_ERROR_ALL_MASK (0xFF << MVNETA_CAUSE_TXQ_ERROR_SHIFT) 18140ba35e7Swilly tarreau #define MVNETA_CAUSE_TXQ_ERROR_MASK(q) (1 << (MVNETA_CAUSE_TXQ_ERROR_SHIFT + (q))) 18240ba35e7Swilly tarreau 183c5aff182SThomas Petazzoni #define MVNETA_INTR_ENABLE 0x25b8 184c5aff182SThomas Petazzoni #define MVNETA_TXQ_INTR_ENABLE_ALL_MASK 0x0000ff00 185dc1aadf6SMarcin Wojtas #define MVNETA_RXQ_INTR_ENABLE_ALL_MASK 0x000000ff 18640ba35e7Swilly tarreau 187c5aff182SThomas Petazzoni #define MVNETA_RXQ_CMD 0x2680 188c5aff182SThomas Petazzoni #define MVNETA_RXQ_DISABLE_SHIFT 8 189c5aff182SThomas Petazzoni #define MVNETA_RXQ_ENABLE_MASK 0x000000ff 190c5aff182SThomas Petazzoni #define MVETH_TXQ_TOKEN_COUNT_REG(q) (0x2700 + ((q) << 4)) 191c5aff182SThomas Petazzoni #define MVETH_TXQ_TOKEN_CFG_REG(q) (0x2704 + ((q) << 4)) 192c5aff182SThomas Petazzoni #define MVNETA_GMAC_CTRL_0 0x2c00 193c5aff182SThomas Petazzoni #define MVNETA_GMAC_MAX_RX_SIZE_SHIFT 2 194c5aff182SThomas Petazzoni #define MVNETA_GMAC_MAX_RX_SIZE_MASK 0x7ffc 19522f4bf8aSRussell King #define MVNETA_GMAC0_PORT_1000BASE_X BIT(1) 196c5aff182SThomas Petazzoni #define MVNETA_GMAC0_PORT_ENABLE BIT(0) 197c5aff182SThomas Petazzoni #define MVNETA_GMAC_CTRL_2 0x2c08 198898b2970SStas Sergeev #define MVNETA_GMAC2_INBAND_AN_ENABLE BIT(0) 199a79121d3SThomas Petazzoni #define MVNETA_GMAC2_PCS_ENABLE BIT(3) 200c5aff182SThomas Petazzoni #define MVNETA_GMAC2_PORT_RGMII BIT(4) 201c5aff182SThomas Petazzoni #define MVNETA_GMAC2_PORT_RESET BIT(6) 202c5aff182SThomas Petazzoni #define MVNETA_GMAC_STATUS 0x2c10 203c5aff182SThomas Petazzoni #define MVNETA_GMAC_LINK_UP BIT(0) 204c5aff182SThomas Petazzoni #define MVNETA_GMAC_SPEED_1000 BIT(1) 205c5aff182SThomas Petazzoni #define MVNETA_GMAC_SPEED_100 BIT(2) 206c5aff182SThomas Petazzoni #define MVNETA_GMAC_FULL_DUPLEX BIT(3) 207c5aff182SThomas Petazzoni #define MVNETA_GMAC_RX_FLOW_CTRL_ENABLE BIT(4) 208c5aff182SThomas Petazzoni #define MVNETA_GMAC_TX_FLOW_CTRL_ENABLE BIT(5) 209c5aff182SThomas Petazzoni #define MVNETA_GMAC_RX_FLOW_CTRL_ACTIVE BIT(6) 210c5aff182SThomas Petazzoni #define MVNETA_GMAC_TX_FLOW_CTRL_ACTIVE BIT(7) 211503f9aa9SRussell King #define MVNETA_GMAC_AN_COMPLETE BIT(11) 212503f9aa9SRussell King #define MVNETA_GMAC_SYNC_OK BIT(14) 213c5aff182SThomas Petazzoni #define MVNETA_GMAC_AUTONEG_CONFIG 0x2c0c 214c5aff182SThomas Petazzoni #define MVNETA_GMAC_FORCE_LINK_DOWN BIT(0) 215c5aff182SThomas Petazzoni #define MVNETA_GMAC_FORCE_LINK_PASS BIT(1) 216898b2970SStas Sergeev #define MVNETA_GMAC_INBAND_AN_ENABLE BIT(2) 21722f4bf8aSRussell King #define MVNETA_GMAC_AN_BYPASS_ENABLE BIT(3) 21822f4bf8aSRussell King #define MVNETA_GMAC_INBAND_RESTART_AN BIT(4) 219c5aff182SThomas Petazzoni #define MVNETA_GMAC_CONFIG_MII_SPEED BIT(5) 220c5aff182SThomas Petazzoni #define MVNETA_GMAC_CONFIG_GMII_SPEED BIT(6) 22171408602SThomas Petazzoni #define MVNETA_GMAC_AN_SPEED_EN BIT(7) 22222f4bf8aSRussell King #define MVNETA_GMAC_CONFIG_FLOW_CTRL BIT(8) 22322f4bf8aSRussell King #define MVNETA_GMAC_ADVERT_SYM_FLOW_CTRL BIT(9) 224898b2970SStas Sergeev #define MVNETA_GMAC_AN_FLOW_CTRL_EN BIT(11) 225c5aff182SThomas Petazzoni #define MVNETA_GMAC_CONFIG_FULL_DUPLEX BIT(12) 22671408602SThomas Petazzoni #define MVNETA_GMAC_AN_DUPLEX_EN BIT(13) 227da58a931SMaxime Chevallier #define MVNETA_GMAC_CTRL_4 0x2c90 228da58a931SMaxime Chevallier #define MVNETA_GMAC4_SHORT_PREAMBLE_ENABLE BIT(1) 229e483911fSAndrew Lunn #define MVNETA_MIB_COUNTERS_BASE 0x3000 230c5aff182SThomas Petazzoni #define MVNETA_MIB_LATE_COLLISION 0x7c 231c5aff182SThomas Petazzoni #define MVNETA_DA_FILT_SPEC_MCAST 0x3400 232c5aff182SThomas Petazzoni #define MVNETA_DA_FILT_OTH_MCAST 0x3500 233c5aff182SThomas Petazzoni #define MVNETA_DA_FILT_UCAST_BASE 0x3600 234c5aff182SThomas Petazzoni #define MVNETA_TXQ_BASE_ADDR_REG(q) (0x3c00 + ((q) << 2)) 235c5aff182SThomas Petazzoni #define MVNETA_TXQ_SIZE_REG(q) (0x3c20 + ((q) << 2)) 236c5aff182SThomas Petazzoni #define MVNETA_TXQ_SENT_THRESH_ALL_MASK 0x3fff0000 237c5aff182SThomas Petazzoni #define MVNETA_TXQ_SENT_THRESH_MASK(coal) ((coal) << 16) 238c5aff182SThomas Petazzoni #define MVNETA_TXQ_UPDATE_REG(q) (0x3c60 + ((q) << 2)) 239c5aff182SThomas Petazzoni #define MVNETA_TXQ_DEC_SENT_SHIFT 16 2402a90f7e1SSimon Guinot #define MVNETA_TXQ_DEC_SENT_MASK 0xff 241c5aff182SThomas Petazzoni #define MVNETA_TXQ_STATUS_REG(q) (0x3c40 + ((q) << 2)) 242c5aff182SThomas Petazzoni #define MVNETA_TXQ_SENT_DESC_SHIFT 16 243c5aff182SThomas Petazzoni #define MVNETA_TXQ_SENT_DESC_MASK 0x3fff0000 244c5aff182SThomas Petazzoni #define MVNETA_PORT_TX_RESET 0x3cf0 245c5aff182SThomas Petazzoni #define MVNETA_PORT_TX_DMA_RESET BIT(0) 246c5aff182SThomas Petazzoni #define MVNETA_TX_MTU 0x3e0c 247c5aff182SThomas Petazzoni #define MVNETA_TX_TOKEN_SIZE 0x3e14 248c5aff182SThomas Petazzoni #define MVNETA_TX_TOKEN_SIZE_MAX 0xffffffff 249c5aff182SThomas Petazzoni #define MVNETA_TXQ_TOKEN_SIZE_REG(q) (0x3e40 + ((q) << 2)) 250c5aff182SThomas Petazzoni #define MVNETA_TXQ_TOKEN_SIZE_MAX 0x7fffffff 251c5aff182SThomas Petazzoni 2526d81f451SRussell King #define MVNETA_LPI_CTRL_0 0x2cc0 2536d81f451SRussell King #define MVNETA_LPI_CTRL_1 0x2cc4 2546d81f451SRussell King #define MVNETA_LPI_REQUEST_ENABLE BIT(0) 2556d81f451SRussell King #define MVNETA_LPI_CTRL_2 0x2cc8 2566d81f451SRussell King #define MVNETA_LPI_STATUS 0x2ccc 2576d81f451SRussell King 258c5aff182SThomas Petazzoni #define MVNETA_CAUSE_TXQ_SENT_DESC_ALL_MASK 0xff 259c5aff182SThomas Petazzoni 260c5aff182SThomas Petazzoni /* Descriptor ring Macros */ 261c5aff182SThomas Petazzoni #define MVNETA_QUEUE_NEXT_DESC(q, index) \ 262c5aff182SThomas Petazzoni (((index) < (q)->last_desc) ? ((index) + 1) : 0) 263c5aff182SThomas Petazzoni 264c5aff182SThomas Petazzoni /* Various constants */ 265c5aff182SThomas Petazzoni 266c5aff182SThomas Petazzoni /* Coalescing */ 26706708f81SDmitri Epshtein #define MVNETA_TXDONE_COAL_PKTS 0 /* interrupt per packet */ 268c5aff182SThomas Petazzoni #define MVNETA_RX_COAL_PKTS 32 269c5aff182SThomas Petazzoni #define MVNETA_RX_COAL_USEC 100 270c5aff182SThomas Petazzoni 2716a20c175SThomas Petazzoni /* The two bytes Marvell header. Either contains a special value used 272c5aff182SThomas Petazzoni * by Marvell switches when a specific hardware mode is enabled (not 273c5aff182SThomas Petazzoni * supported by this driver) or is filled automatically by zeroes on 274c5aff182SThomas Petazzoni * the RX side. Those two bytes being at the front of the Ethernet 275c5aff182SThomas Petazzoni * header, they allow to have the IP header aligned on a 4 bytes 276c5aff182SThomas Petazzoni * boundary automatically: the hardware skips those two bytes on its 277c5aff182SThomas Petazzoni * own. 278c5aff182SThomas Petazzoni */ 279c5aff182SThomas Petazzoni #define MVNETA_MH_SIZE 2 280c5aff182SThomas Petazzoni 281c5aff182SThomas Petazzoni #define MVNETA_VLAN_TAG_LEN 4 282c5aff182SThomas Petazzoni 2839110ee07SMarcin Wojtas #define MVNETA_TX_CSUM_DEF_SIZE 1600 284c5aff182SThomas Petazzoni #define MVNETA_TX_CSUM_MAX_SIZE 9800 285dc35a10fSMarcin Wojtas #define MVNETA_ACC_MODE_EXT1 1 286dc35a10fSMarcin Wojtas #define MVNETA_ACC_MODE_EXT2 2 287dc35a10fSMarcin Wojtas 288dc35a10fSMarcin Wojtas #define MVNETA_MAX_DECODE_WIN 6 289c5aff182SThomas Petazzoni 290c5aff182SThomas Petazzoni /* Timeout constants */ 291c5aff182SThomas Petazzoni #define MVNETA_TX_DISABLE_TIMEOUT_MSEC 1000 292c5aff182SThomas Petazzoni #define MVNETA_RX_DISABLE_TIMEOUT_MSEC 1000 293c5aff182SThomas Petazzoni #define MVNETA_TX_FIFO_EMPTY_TIMEOUT 10000 294c5aff182SThomas Petazzoni 295c5aff182SThomas Petazzoni #define MVNETA_TX_MTU_MAX 0x3ffff 296c5aff182SThomas Petazzoni 2979a401deaSGregory CLEMENT /* The RSS lookup table actually has 256 entries but we do not use 2989a401deaSGregory CLEMENT * them yet 2999a401deaSGregory CLEMENT */ 3009a401deaSGregory CLEMENT #define MVNETA_RSS_LU_TABLE_SIZE 1 3019a401deaSGregory CLEMENT 302c5aff182SThomas Petazzoni /* Max number of Rx descriptors */ 303c307e2a8SYelena Krivosheev #define MVNETA_MAX_RXD 512 304c5aff182SThomas Petazzoni 305c5aff182SThomas Petazzoni /* Max number of Tx descriptors */ 306c307e2a8SYelena Krivosheev #define MVNETA_MAX_TXD 1024 307c5aff182SThomas Petazzoni 3088eef5f97SEzequiel Garcia /* Max number of allowed TCP segments for software TSO */ 3098eef5f97SEzequiel Garcia #define MVNETA_MAX_TSO_SEGS 100 3108eef5f97SEzequiel Garcia 3118eef5f97SEzequiel Garcia #define MVNETA_MAX_SKB_DESCS (MVNETA_MAX_TSO_SEGS * 2 + MAX_SKB_FRAGS) 3128eef5f97SEzequiel Garcia 313c5aff182SThomas Petazzoni /* descriptor aligned size */ 314c5aff182SThomas Petazzoni #define MVNETA_DESC_ALIGNED_SIZE 32 315c5aff182SThomas Petazzoni 3168d5047cfSMarcin Wojtas /* Number of bytes to be taken into account by HW when putting incoming data 3178d5047cfSMarcin Wojtas * to the buffers. It is needed in case NET_SKB_PAD exceeds maximum packet 3188d5047cfSMarcin Wojtas * offset supported in MVNETA_RXQ_CONFIG_REG(q) registers. 3198d5047cfSMarcin Wojtas */ 3208d5047cfSMarcin Wojtas #define MVNETA_RX_PKT_OFFSET_CORRECTION 64 3218d5047cfSMarcin Wojtas 322c5aff182SThomas Petazzoni #define MVNETA_RX_PKT_SIZE(mtu) \ 323c5aff182SThomas Petazzoni ALIGN((mtu) + MVNETA_MH_SIZE + MVNETA_VLAN_TAG_LEN + \ 324c5aff182SThomas Petazzoni ETH_HLEN + ETH_FCS_LEN, \ 325c66e98c9SJisheng Zhang cache_line_size()) 326c5aff182SThomas Petazzoni 32744efc78dSLorenzo Bianconi #define MVNETA_SKB_HEADROOM max(XDP_PACKET_HEADROOM, NET_SKB_PAD) 3288dc9a088SLorenzo Bianconi #define MVNETA_SKB_PAD (SKB_DATA_ALIGN(sizeof(struct skb_shared_info) + \ 3290db51da7SLorenzo Bianconi MVNETA_SKB_HEADROOM)) 3308dc9a088SLorenzo Bianconi #define MVNETA_SKB_SIZE(len) (SKB_DATA_ALIGN(len) + MVNETA_SKB_PAD) 3318dc9a088SLorenzo Bianconi #define MVNETA_MAX_RX_BUF_SIZE (PAGE_SIZE - MVNETA_SKB_PAD) 3328dc9a088SLorenzo Bianconi 3332e3173a3SEzequiel Garcia #define IS_TSO_HEADER(txq, addr) \ 3342e3173a3SEzequiel Garcia ((addr >= txq->tso_hdrs_phys) && \ 3352e3173a3SEzequiel Garcia (addr < txq->tso_hdrs_phys + txq->size * TSO_HEADER_SIZE)) 3362e3173a3SEzequiel Garcia 337dc35a10fSMarcin Wojtas #define MVNETA_RX_GET_BM_POOL_ID(rxd) \ 338dc35a10fSMarcin Wojtas (((rxd)->status & MVNETA_RXD_BM_POOL_MASK) >> MVNETA_RXD_BM_POOL_SHIFT) 339c5aff182SThomas Petazzoni 3406d81f451SRussell King enum { 3416d81f451SRussell King ETHTOOL_STAT_EEE_WAKEUP, 34217a96da6SGregory CLEMENT ETHTOOL_STAT_SKB_ALLOC_ERR, 34317a96da6SGregory CLEMENT ETHTOOL_STAT_REFILL_ERR, 3446d81f451SRussell King ETHTOOL_MAX_STATS, 3456d81f451SRussell King }; 3466d81f451SRussell King 3479b0cdefaSRussell King struct mvneta_statistic { 3489b0cdefaSRussell King unsigned short offset; 3499b0cdefaSRussell King unsigned short type; 3509b0cdefaSRussell King const char name[ETH_GSTRING_LEN]; 3519b0cdefaSRussell King }; 3529b0cdefaSRussell King 3539b0cdefaSRussell King #define T_REG_32 32 3549b0cdefaSRussell King #define T_REG_64 64 3556d81f451SRussell King #define T_SW 1 3569b0cdefaSRussell King 3570db51da7SLorenzo Bianconi #define MVNETA_XDP_PASS BIT(0) 3580db51da7SLorenzo Bianconi #define MVNETA_XDP_DROPPED BIT(1) 3590db51da7SLorenzo Bianconi #define MVNETA_XDP_TX BIT(2) 3600db51da7SLorenzo Bianconi #define MVNETA_XDP_REDIR BIT(3) 3610db51da7SLorenzo Bianconi 3629b0cdefaSRussell King static const struct mvneta_statistic mvneta_statistics[] = { 3639b0cdefaSRussell King { 0x3000, T_REG_64, "good_octets_received", }, 3649b0cdefaSRussell King { 0x3010, T_REG_32, "good_frames_received", }, 3659b0cdefaSRussell King { 0x3008, T_REG_32, "bad_octets_received", }, 3669b0cdefaSRussell King { 0x3014, T_REG_32, "bad_frames_received", }, 3679b0cdefaSRussell King { 0x3018, T_REG_32, "broadcast_frames_received", }, 3689b0cdefaSRussell King { 0x301c, T_REG_32, "multicast_frames_received", }, 3699b0cdefaSRussell King { 0x3050, T_REG_32, "unrec_mac_control_received", }, 3709b0cdefaSRussell King { 0x3058, T_REG_32, "good_fc_received", }, 3719b0cdefaSRussell King { 0x305c, T_REG_32, "bad_fc_received", }, 3729b0cdefaSRussell King { 0x3060, T_REG_32, "undersize_received", }, 3739b0cdefaSRussell King { 0x3064, T_REG_32, "fragments_received", }, 3749b0cdefaSRussell King { 0x3068, T_REG_32, "oversize_received", }, 3759b0cdefaSRussell King { 0x306c, T_REG_32, "jabber_received", }, 3769b0cdefaSRussell King { 0x3070, T_REG_32, "mac_receive_error", }, 3779b0cdefaSRussell King { 0x3074, T_REG_32, "bad_crc_event", }, 3789b0cdefaSRussell King { 0x3078, T_REG_32, "collision", }, 3799b0cdefaSRussell King { 0x307c, T_REG_32, "late_collision", }, 3809b0cdefaSRussell King { 0x2484, T_REG_32, "rx_discard", }, 3819b0cdefaSRussell King { 0x2488, T_REG_32, "rx_overrun", }, 3829b0cdefaSRussell King { 0x3020, T_REG_32, "frames_64_octets", }, 3839b0cdefaSRussell King { 0x3024, T_REG_32, "frames_65_to_127_octets", }, 3849b0cdefaSRussell King { 0x3028, T_REG_32, "frames_128_to_255_octets", }, 3859b0cdefaSRussell King { 0x302c, T_REG_32, "frames_256_to_511_octets", }, 3869b0cdefaSRussell King { 0x3030, T_REG_32, "frames_512_to_1023_octets", }, 3879b0cdefaSRussell King { 0x3034, T_REG_32, "frames_1024_to_max_octets", }, 3889b0cdefaSRussell King { 0x3038, T_REG_64, "good_octets_sent", }, 3899b0cdefaSRussell King { 0x3040, T_REG_32, "good_frames_sent", }, 3909b0cdefaSRussell King { 0x3044, T_REG_32, "excessive_collision", }, 3919b0cdefaSRussell King { 0x3048, T_REG_32, "multicast_frames_sent", }, 3929b0cdefaSRussell King { 0x304c, T_REG_32, "broadcast_frames_sent", }, 3939b0cdefaSRussell King { 0x3054, T_REG_32, "fc_sent", }, 3949b0cdefaSRussell King { 0x300c, T_REG_32, "internal_mac_transmit_err", }, 3956d81f451SRussell King { ETHTOOL_STAT_EEE_WAKEUP, T_SW, "eee_wakeup_errors", }, 39617a96da6SGregory CLEMENT { ETHTOOL_STAT_SKB_ALLOC_ERR, T_SW, "skb_alloc_errors", }, 39717a96da6SGregory CLEMENT { ETHTOOL_STAT_REFILL_ERR, T_SW, "refill_errors", }, 3989b0cdefaSRussell King }; 3999b0cdefaSRussell King 4009ac41f3cSLorenzo Bianconi struct mvneta_ethtool_stats { 4019ac41f3cSLorenzo Bianconi u64 skb_alloc_error; 4029ac41f3cSLorenzo Bianconi u64 refill_error; 4039ac41f3cSLorenzo Bianconi }; 4049ac41f3cSLorenzo Bianconi 40574c41b04Swilly tarreau struct mvneta_pcpu_stats { 406c5aff182SThomas Petazzoni struct u64_stats_sync syncp; 4079ac41f3cSLorenzo Bianconi 4089ac41f3cSLorenzo Bianconi struct mvneta_ethtool_stats es; 40974c41b04Swilly tarreau u64 rx_packets; 41074c41b04Swilly tarreau u64 rx_bytes; 411c35947b8SLorenzo Bianconi u64 rx_dropped; 412c35947b8SLorenzo Bianconi u64 rx_errors; 41374c41b04Swilly tarreau u64 tx_packets; 41474c41b04Swilly tarreau u64 tx_bytes; 415c5aff182SThomas Petazzoni }; 416c5aff182SThomas Petazzoni 41712bb03b4SMaxime Ripard struct mvneta_pcpu_port { 41812bb03b4SMaxime Ripard /* Pointer to the shared port */ 41912bb03b4SMaxime Ripard struct mvneta_port *pp; 42012bb03b4SMaxime Ripard 42112bb03b4SMaxime Ripard /* Pointer to the CPU-local NAPI struct */ 42212bb03b4SMaxime Ripard struct napi_struct napi; 42312bb03b4SMaxime Ripard 42412bb03b4SMaxime Ripard /* Cause of the previous interrupt */ 42512bb03b4SMaxime Ripard u32 cause_rx_tx; 42612bb03b4SMaxime Ripard }; 42712bb03b4SMaxime Ripard 428c5aff182SThomas Petazzoni struct mvneta_port { 429dc35a10fSMarcin Wojtas u8 id; 43012bb03b4SMaxime Ripard struct mvneta_pcpu_port __percpu *ports; 43112bb03b4SMaxime Ripard struct mvneta_pcpu_stats __percpu *stats; 43212bb03b4SMaxime Ripard 433c5aff182SThomas Petazzoni int pkt_size; 434c5aff182SThomas Petazzoni void __iomem *base; 435c5aff182SThomas Petazzoni struct mvneta_rx_queue *rxqs; 436c5aff182SThomas Petazzoni struct mvneta_tx_queue *txqs; 437c5aff182SThomas Petazzoni struct net_device *dev; 43884a3f4dbSSebastian Andrzej Siewior struct hlist_node node_online; 43984a3f4dbSSebastian Andrzej Siewior struct hlist_node node_dead; 44090b74c01SGregory CLEMENT int rxq_def; 4415888511eSGregory CLEMENT /* Protect the access to the percpu interrupt registers, 4425888511eSGregory CLEMENT * ensuring that the configuration remains coherent. 4435888511eSGregory CLEMENT */ 4445888511eSGregory CLEMENT spinlock_t lock; 445120cfa50SGregory CLEMENT bool is_stopped; 446c5aff182SThomas Petazzoni 4472636ac3cSMarcin Wojtas u32 cause_rx_tx; 4482636ac3cSMarcin Wojtas struct napi_struct napi; 4492636ac3cSMarcin Wojtas 4500db51da7SLorenzo Bianconi struct bpf_prog *xdp_prog; 4510db51da7SLorenzo Bianconi 452c5aff182SThomas Petazzoni /* Core clock */ 453189dd626SThomas Petazzoni struct clk *clk; 45415cc4a4aSJisheng Zhang /* AXI clock */ 45515cc4a4aSJisheng Zhang struct clk *clk_bus; 456c5aff182SThomas Petazzoni u8 mcast_count[256]; 457c5aff182SThomas Petazzoni u16 tx_ring_size; 458c5aff182SThomas Petazzoni u16 rx_ring_size; 459c5aff182SThomas Petazzoni 460c5aff182SThomas Petazzoni phy_interface_t phy_interface; 461503f9aa9SRussell King struct device_node *dn; 462b65657fcSSimon Guinot unsigned int tx_csum_limit; 463503f9aa9SRussell King struct phylink *phylink; 46444cc27e4SIoana Ciornei struct phylink_config phylink_config; 465a10c1c81SRussell King struct phy *comphy; 4669b0cdefaSRussell King 467dc35a10fSMarcin Wojtas struct mvneta_bm *bm_priv; 468dc35a10fSMarcin Wojtas struct mvneta_bm_pool *pool_long; 469dc35a10fSMarcin Wojtas struct mvneta_bm_pool *pool_short; 470dc35a10fSMarcin Wojtas int bm_win_id; 471dc35a10fSMarcin Wojtas 4726d81f451SRussell King bool eee_enabled; 4736d81f451SRussell King bool eee_active; 4746d81f451SRussell King bool tx_lpi_enabled; 4756d81f451SRussell King 4769b0cdefaSRussell King u64 ethtool_stats[ARRAY_SIZE(mvneta_statistics)]; 4779a401deaSGregory CLEMENT 4789a401deaSGregory CLEMENT u32 indir[MVNETA_RSS_LU_TABLE_SIZE]; 4792636ac3cSMarcin Wojtas 4802636ac3cSMarcin Wojtas /* Flags for special SoC configurations */ 4812636ac3cSMarcin Wojtas bool neta_armada3700; 4828d5047cfSMarcin Wojtas u16 rx_offset_correction; 4839768b45cSJane Li const struct mbus_dram_target_info *dram_target_info; 484c5aff182SThomas Petazzoni }; 485c5aff182SThomas Petazzoni 4866a20c175SThomas Petazzoni /* The mvneta_tx_desc and mvneta_rx_desc structures describe the 487c5aff182SThomas Petazzoni * layout of the transmit and reception DMA descriptors, and their 488c5aff182SThomas Petazzoni * layout is therefore defined by the hardware design 489c5aff182SThomas Petazzoni */ 4906083ed44SThomas Petazzoni 491c5aff182SThomas Petazzoni #define MVNETA_TX_L3_OFF_SHIFT 0 492c5aff182SThomas Petazzoni #define MVNETA_TX_IP_HLEN_SHIFT 8 493c5aff182SThomas Petazzoni #define MVNETA_TX_L4_UDP BIT(16) 494c5aff182SThomas Petazzoni #define MVNETA_TX_L3_IP6 BIT(17) 495c5aff182SThomas Petazzoni #define MVNETA_TXD_IP_CSUM BIT(18) 496c5aff182SThomas Petazzoni #define MVNETA_TXD_Z_PAD BIT(19) 497c5aff182SThomas Petazzoni #define MVNETA_TXD_L_DESC BIT(20) 498c5aff182SThomas Petazzoni #define MVNETA_TXD_F_DESC BIT(21) 499c5aff182SThomas Petazzoni #define MVNETA_TXD_FLZ_DESC (MVNETA_TXD_Z_PAD | \ 500c5aff182SThomas Petazzoni MVNETA_TXD_L_DESC | \ 501c5aff182SThomas Petazzoni MVNETA_TXD_F_DESC) 502c5aff182SThomas Petazzoni #define MVNETA_TX_L4_CSUM_FULL BIT(30) 503c5aff182SThomas Petazzoni #define MVNETA_TX_L4_CSUM_NOT BIT(31) 504c5aff182SThomas Petazzoni 505c5aff182SThomas Petazzoni #define MVNETA_RXD_ERR_CRC 0x0 506dc35a10fSMarcin Wojtas #define MVNETA_RXD_BM_POOL_SHIFT 13 507dc35a10fSMarcin Wojtas #define MVNETA_RXD_BM_POOL_MASK (BIT(13) | BIT(14)) 508c5aff182SThomas Petazzoni #define MVNETA_RXD_ERR_SUMMARY BIT(16) 509c5aff182SThomas Petazzoni #define MVNETA_RXD_ERR_OVERRUN BIT(17) 510c5aff182SThomas Petazzoni #define MVNETA_RXD_ERR_LEN BIT(18) 511c5aff182SThomas Petazzoni #define MVNETA_RXD_ERR_RESOURCE (BIT(17) | BIT(18)) 512c5aff182SThomas Petazzoni #define MVNETA_RXD_ERR_CODE_MASK (BIT(17) | BIT(18)) 513c5aff182SThomas Petazzoni #define MVNETA_RXD_L3_IP4 BIT(25) 514562e2f46SYelena Krivosheev #define MVNETA_RXD_LAST_DESC BIT(26) 515562e2f46SYelena Krivosheev #define MVNETA_RXD_FIRST_DESC BIT(27) 516562e2f46SYelena Krivosheev #define MVNETA_RXD_FIRST_LAST_DESC (MVNETA_RXD_FIRST_DESC | \ 517562e2f46SYelena Krivosheev MVNETA_RXD_LAST_DESC) 518c5aff182SThomas Petazzoni #define MVNETA_RXD_L4_CSUM_OK BIT(30) 519c5aff182SThomas Petazzoni 5209ad8fef6SThomas Petazzoni #if defined(__LITTLE_ENDIAN) 5216083ed44SThomas Petazzoni struct mvneta_tx_desc { 5226083ed44SThomas Petazzoni u32 command; /* Options used by HW for packet transmitting.*/ 523fbd1d524SAlexandre Belloni u16 reserved1; /* csum_l4 (for future use) */ 5246083ed44SThomas Petazzoni u16 data_size; /* Data size of transmitted packet in bytes */ 5256083ed44SThomas Petazzoni u32 buf_phys_addr; /* Physical addr of transmitted buffer */ 5266083ed44SThomas Petazzoni u32 reserved2; /* hw_cmd - (for future use, PMT) */ 5276083ed44SThomas Petazzoni u32 reserved3[4]; /* Reserved - (for future use) */ 5286083ed44SThomas Petazzoni }; 5296083ed44SThomas Petazzoni 5306083ed44SThomas Petazzoni struct mvneta_rx_desc { 5316083ed44SThomas Petazzoni u32 status; /* Info about received packet */ 532c5aff182SThomas Petazzoni u16 reserved1; /* pnc_info - (for future use, PnC) */ 533c5aff182SThomas Petazzoni u16 data_size; /* Size of received packet in bytes */ 5346083ed44SThomas Petazzoni 535c5aff182SThomas Petazzoni u32 buf_phys_addr; /* Physical address of the buffer */ 536c5aff182SThomas Petazzoni u32 reserved2; /* pnc_flow_id (for future use, PnC) */ 5376083ed44SThomas Petazzoni 538c5aff182SThomas Petazzoni u32 buf_cookie; /* cookie for access to RX buffer in rx path */ 539c5aff182SThomas Petazzoni u16 reserved3; /* prefetch_cmd, for future use */ 540c5aff182SThomas Petazzoni u16 reserved4; /* csum_l4 - (for future use, PnC) */ 5416083ed44SThomas Petazzoni 542c5aff182SThomas Petazzoni u32 reserved5; /* pnc_extra PnC (for future use, PnC) */ 543c5aff182SThomas Petazzoni u32 reserved6; /* hw_cmd (for future use, PnC and HWF) */ 544c5aff182SThomas Petazzoni }; 5459ad8fef6SThomas Petazzoni #else 5469ad8fef6SThomas Petazzoni struct mvneta_tx_desc { 5479ad8fef6SThomas Petazzoni u16 data_size; /* Data size of transmitted packet in bytes */ 548fbd1d524SAlexandre Belloni u16 reserved1; /* csum_l4 (for future use) */ 5499ad8fef6SThomas Petazzoni u32 command; /* Options used by HW for packet transmitting.*/ 5509ad8fef6SThomas Petazzoni u32 reserved2; /* hw_cmd - (for future use, PMT) */ 5519ad8fef6SThomas Petazzoni u32 buf_phys_addr; /* Physical addr of transmitted buffer */ 5529ad8fef6SThomas Petazzoni u32 reserved3[4]; /* Reserved - (for future use) */ 5539ad8fef6SThomas Petazzoni }; 5549ad8fef6SThomas Petazzoni 5559ad8fef6SThomas Petazzoni struct mvneta_rx_desc { 5569ad8fef6SThomas Petazzoni u16 data_size; /* Size of received packet in bytes */ 5579ad8fef6SThomas Petazzoni u16 reserved1; /* pnc_info - (for future use, PnC) */ 5589ad8fef6SThomas Petazzoni u32 status; /* Info about received packet */ 5599ad8fef6SThomas Petazzoni 5609ad8fef6SThomas Petazzoni u32 reserved2; /* pnc_flow_id (for future use, PnC) */ 5619ad8fef6SThomas Petazzoni u32 buf_phys_addr; /* Physical address of the buffer */ 5629ad8fef6SThomas Petazzoni 5639ad8fef6SThomas Petazzoni u16 reserved4; /* csum_l4 - (for future use, PnC) */ 5649ad8fef6SThomas Petazzoni u16 reserved3; /* prefetch_cmd, for future use */ 5659ad8fef6SThomas Petazzoni u32 buf_cookie; /* cookie for access to RX buffer in rx path */ 5669ad8fef6SThomas Petazzoni 5679ad8fef6SThomas Petazzoni u32 reserved5; /* pnc_extra PnC (for future use, PnC) */ 5689ad8fef6SThomas Petazzoni u32 reserved6; /* hw_cmd (for future use, PnC and HWF) */ 5699ad8fef6SThomas Petazzoni }; 5709ad8fef6SThomas Petazzoni #endif 571c5aff182SThomas Petazzoni 5729e58c8b4SLorenzo Bianconi enum mvneta_tx_buf_type { 5739e58c8b4SLorenzo Bianconi MVNETA_TYPE_SKB, 5749e58c8b4SLorenzo Bianconi MVNETA_TYPE_XDP_TX, 5759e58c8b4SLorenzo Bianconi MVNETA_TYPE_XDP_NDO, 5769e58c8b4SLorenzo Bianconi }; 5779e58c8b4SLorenzo Bianconi 5789e58c8b4SLorenzo Bianconi struct mvneta_tx_buf { 5799e58c8b4SLorenzo Bianconi enum mvneta_tx_buf_type type; 5809e58c8b4SLorenzo Bianconi union { 5819e58c8b4SLorenzo Bianconi struct xdp_frame *xdpf; 5829e58c8b4SLorenzo Bianconi struct sk_buff *skb; 5839e58c8b4SLorenzo Bianconi }; 5849e58c8b4SLorenzo Bianconi }; 5859e58c8b4SLorenzo Bianconi 586c5aff182SThomas Petazzoni struct mvneta_tx_queue { 587c5aff182SThomas Petazzoni /* Number of this TX queue, in the range 0-7 */ 588c5aff182SThomas Petazzoni u8 id; 589c5aff182SThomas Petazzoni 590c5aff182SThomas Petazzoni /* Number of TX DMA descriptors in the descriptor ring */ 591c5aff182SThomas Petazzoni int size; 592c5aff182SThomas Petazzoni 593c5aff182SThomas Petazzoni /* Number of currently used TX DMA descriptor in the 5946a20c175SThomas Petazzoni * descriptor ring 5956a20c175SThomas Petazzoni */ 596c5aff182SThomas Petazzoni int count; 5972a90f7e1SSimon Guinot int pending; 5988eef5f97SEzequiel Garcia int tx_stop_threshold; 5998eef5f97SEzequiel Garcia int tx_wake_threshold; 600c5aff182SThomas Petazzoni 6019e58c8b4SLorenzo Bianconi /* Array of transmitted buffers */ 6029e58c8b4SLorenzo Bianconi struct mvneta_tx_buf *buf; 603c5aff182SThomas Petazzoni 604c5aff182SThomas Petazzoni /* Index of last TX DMA descriptor that was inserted */ 605c5aff182SThomas Petazzoni int txq_put_index; 606c5aff182SThomas Petazzoni 607c5aff182SThomas Petazzoni /* Index of the TX DMA descriptor to be cleaned up */ 608c5aff182SThomas Petazzoni int txq_get_index; 609c5aff182SThomas Petazzoni 610c5aff182SThomas Petazzoni u32 done_pkts_coal; 611c5aff182SThomas Petazzoni 612c5aff182SThomas Petazzoni /* Virtual address of the TX DMA descriptors array */ 613c5aff182SThomas Petazzoni struct mvneta_tx_desc *descs; 614c5aff182SThomas Petazzoni 615c5aff182SThomas Petazzoni /* DMA address of the TX DMA descriptors array */ 616c5aff182SThomas Petazzoni dma_addr_t descs_phys; 617c5aff182SThomas Petazzoni 618c5aff182SThomas Petazzoni /* Index of the last TX DMA descriptor */ 619c5aff182SThomas Petazzoni int last_desc; 620c5aff182SThomas Petazzoni 621c5aff182SThomas Petazzoni /* Index of the next TX DMA descriptor to process */ 622c5aff182SThomas Petazzoni int next_desc_to_proc; 6232adb719dSEzequiel Garcia 6242adb719dSEzequiel Garcia /* DMA buffers for TSO headers */ 6252adb719dSEzequiel Garcia char *tso_hdrs; 6262adb719dSEzequiel Garcia 6272adb719dSEzequiel Garcia /* DMA address of TSO headers */ 6282adb719dSEzequiel Garcia dma_addr_t tso_hdrs_phys; 62950bf8cb6SGregory CLEMENT 63050bf8cb6SGregory CLEMENT /* Affinity mask for CPUs*/ 63150bf8cb6SGregory CLEMENT cpumask_t affinity_mask; 632c5aff182SThomas Petazzoni }; 633c5aff182SThomas Petazzoni 634c5aff182SThomas Petazzoni struct mvneta_rx_queue { 635c5aff182SThomas Petazzoni /* rx queue number, in the range 0-7 */ 636c5aff182SThomas Petazzoni u8 id; 637c5aff182SThomas Petazzoni 638c5aff182SThomas Petazzoni /* num of rx descriptors in the rx descriptor ring */ 639c5aff182SThomas Petazzoni int size; 640c5aff182SThomas Petazzoni 641c5aff182SThomas Petazzoni u32 pkts_coal; 642c5aff182SThomas Petazzoni u32 time_coal; 643c5aff182SThomas Petazzoni 644568a3fa2SLorenzo Bianconi /* page_pool */ 645568a3fa2SLorenzo Bianconi struct page_pool *page_pool; 646568a3fa2SLorenzo Bianconi struct xdp_rxq_info xdp_rxq; 647568a3fa2SLorenzo Bianconi 648f88bee1cSGregory CLEMENT /* Virtual address of the RX buffer */ 649f88bee1cSGregory CLEMENT void **buf_virt_addr; 650f88bee1cSGregory CLEMENT 651c5aff182SThomas Petazzoni /* Virtual address of the RX DMA descriptors array */ 652c5aff182SThomas Petazzoni struct mvneta_rx_desc *descs; 653c5aff182SThomas Petazzoni 654c5aff182SThomas Petazzoni /* DMA address of the RX DMA descriptors array */ 655c5aff182SThomas Petazzoni dma_addr_t descs_phys; 656c5aff182SThomas Petazzoni 657c5aff182SThomas Petazzoni /* Index of the last RX DMA descriptor */ 658c5aff182SThomas Petazzoni int last_desc; 659c5aff182SThomas Petazzoni 660c5aff182SThomas Petazzoni /* Index of the next RX DMA descriptor to process */ 661c5aff182SThomas Petazzoni int next_desc_to_proc; 66217a96da6SGregory CLEMENT 663562e2f46SYelena Krivosheev /* Index of first RX DMA descriptor to refill */ 664562e2f46SYelena Krivosheev int first_to_refill; 665562e2f46SYelena Krivosheev u32 refill_num; 666562e2f46SYelena Krivosheev 667562e2f46SYelena Krivosheev /* pointer to uncomplete skb buffer */ 668562e2f46SYelena Krivosheev struct sk_buff *skb; 669562e2f46SYelena Krivosheev int left_size; 670c5aff182SThomas Petazzoni }; 671c5aff182SThomas Petazzoni 67284a3f4dbSSebastian Andrzej Siewior static enum cpuhp_state online_hpstate; 673edadb7faSEzequiel Garcia /* The hardware supports eight (8) rx queues, but we are only allowing 674edadb7faSEzequiel Garcia * the first one to be used. Therefore, let's just allocate one queue. 675edadb7faSEzequiel Garcia */ 676d8936657SMaxime Ripard static int rxq_number = 8; 677c5aff182SThomas Petazzoni static int txq_number = 8; 678c5aff182SThomas Petazzoni 679c5aff182SThomas Petazzoni static int rxq_def; 680c5aff182SThomas Petazzoni 681f19fadfcSwilly tarreau static int rx_copybreak __read_mostly = 256; 682f19fadfcSwilly tarreau 683dc35a10fSMarcin Wojtas /* HW BM need that each port be identify by a unique ID */ 684dc35a10fSMarcin Wojtas static int global_port_id; 685dc35a10fSMarcin Wojtas 686c5aff182SThomas Petazzoni #define MVNETA_DRIVER_NAME "mvneta" 687c5aff182SThomas Petazzoni #define MVNETA_DRIVER_VERSION "1.0" 688c5aff182SThomas Petazzoni 689c5aff182SThomas Petazzoni /* Utility/helper methods */ 690c5aff182SThomas Petazzoni 691c5aff182SThomas Petazzoni /* Write helper method */ 692c5aff182SThomas Petazzoni static void mvreg_write(struct mvneta_port *pp, u32 offset, u32 data) 693c5aff182SThomas Petazzoni { 694c5aff182SThomas Petazzoni writel(data, pp->base + offset); 695c5aff182SThomas Petazzoni } 696c5aff182SThomas Petazzoni 697c5aff182SThomas Petazzoni /* Read helper method */ 698c5aff182SThomas Petazzoni static u32 mvreg_read(struct mvneta_port *pp, u32 offset) 699c5aff182SThomas Petazzoni { 700c5aff182SThomas Petazzoni return readl(pp->base + offset); 701c5aff182SThomas Petazzoni } 702c5aff182SThomas Petazzoni 703c5aff182SThomas Petazzoni /* Increment txq get counter */ 704c5aff182SThomas Petazzoni static void mvneta_txq_inc_get(struct mvneta_tx_queue *txq) 705c5aff182SThomas Petazzoni { 706c5aff182SThomas Petazzoni txq->txq_get_index++; 707c5aff182SThomas Petazzoni if (txq->txq_get_index == txq->size) 708c5aff182SThomas Petazzoni txq->txq_get_index = 0; 709c5aff182SThomas Petazzoni } 710c5aff182SThomas Petazzoni 711c5aff182SThomas Petazzoni /* Increment txq put counter */ 712c5aff182SThomas Petazzoni static void mvneta_txq_inc_put(struct mvneta_tx_queue *txq) 713c5aff182SThomas Petazzoni { 714c5aff182SThomas Petazzoni txq->txq_put_index++; 715c5aff182SThomas Petazzoni if (txq->txq_put_index == txq->size) 716c5aff182SThomas Petazzoni txq->txq_put_index = 0; 717c5aff182SThomas Petazzoni } 718c5aff182SThomas Petazzoni 719c5aff182SThomas Petazzoni 720c5aff182SThomas Petazzoni /* Clear all MIB counters */ 721c5aff182SThomas Petazzoni static void mvneta_mib_counters_clear(struct mvneta_port *pp) 722c5aff182SThomas Petazzoni { 723c5aff182SThomas Petazzoni int i; 724c5aff182SThomas Petazzoni u32 dummy; 725c5aff182SThomas Petazzoni 726c5aff182SThomas Petazzoni /* Perform dummy reads from MIB counters */ 727c5aff182SThomas Petazzoni for (i = 0; i < MVNETA_MIB_LATE_COLLISION; i += 4) 728c5aff182SThomas Petazzoni dummy = mvreg_read(pp, (MVNETA_MIB_COUNTERS_BASE + i)); 729e483911fSAndrew Lunn dummy = mvreg_read(pp, MVNETA_RX_DISCARD_FRAME_COUNT); 730e483911fSAndrew Lunn dummy = mvreg_read(pp, MVNETA_OVERRUN_FRAME_COUNT); 731c5aff182SThomas Petazzoni } 732c5aff182SThomas Petazzoni 733c5aff182SThomas Petazzoni /* Get System Network Statistics */ 734bc1f4470Sstephen hemminger static void 7352dc0d2b4SBaoyou Xie mvneta_get_stats64(struct net_device *dev, 736c5aff182SThomas Petazzoni struct rtnl_link_stats64 *stats) 737c5aff182SThomas Petazzoni { 738c5aff182SThomas Petazzoni struct mvneta_port *pp = netdev_priv(dev); 739c5aff182SThomas Petazzoni unsigned int start; 74074c41b04Swilly tarreau int cpu; 741c5aff182SThomas Petazzoni 74274c41b04Swilly tarreau for_each_possible_cpu(cpu) { 74374c41b04Swilly tarreau struct mvneta_pcpu_stats *cpu_stats; 74474c41b04Swilly tarreau u64 rx_packets; 74574c41b04Swilly tarreau u64 rx_bytes; 746c35947b8SLorenzo Bianconi u64 rx_dropped; 747c35947b8SLorenzo Bianconi u64 rx_errors; 74874c41b04Swilly tarreau u64 tx_packets; 74974c41b04Swilly tarreau u64 tx_bytes; 750c5aff182SThomas Petazzoni 75174c41b04Swilly tarreau cpu_stats = per_cpu_ptr(pp->stats, cpu); 752c5aff182SThomas Petazzoni do { 75357a7744eSEric W. Biederman start = u64_stats_fetch_begin_irq(&cpu_stats->syncp); 75474c41b04Swilly tarreau rx_packets = cpu_stats->rx_packets; 75574c41b04Swilly tarreau rx_bytes = cpu_stats->rx_bytes; 756c35947b8SLorenzo Bianconi rx_dropped = cpu_stats->rx_dropped; 757c35947b8SLorenzo Bianconi rx_errors = cpu_stats->rx_errors; 75874c41b04Swilly tarreau tx_packets = cpu_stats->tx_packets; 75974c41b04Swilly tarreau tx_bytes = cpu_stats->tx_bytes; 76057a7744eSEric W. Biederman } while (u64_stats_fetch_retry_irq(&cpu_stats->syncp, start)); 761c5aff182SThomas Petazzoni 76274c41b04Swilly tarreau stats->rx_packets += rx_packets; 76374c41b04Swilly tarreau stats->rx_bytes += rx_bytes; 764c35947b8SLorenzo Bianconi stats->rx_dropped += rx_dropped; 765c35947b8SLorenzo Bianconi stats->rx_errors += rx_errors; 76674c41b04Swilly tarreau stats->tx_packets += tx_packets; 76774c41b04Swilly tarreau stats->tx_bytes += tx_bytes; 76874c41b04Swilly tarreau } 769c5aff182SThomas Petazzoni 770c5aff182SThomas Petazzoni stats->tx_dropped = dev->stats.tx_dropped; 771c5aff182SThomas Petazzoni } 772c5aff182SThomas Petazzoni 773c5aff182SThomas Petazzoni /* Rx descriptors helper methods */ 774c5aff182SThomas Petazzoni 7755428213cSwilly tarreau /* Checks whether the RX descriptor having this status is both the first 7765428213cSwilly tarreau * and the last descriptor for the RX packet. Each RX packet is currently 777c5aff182SThomas Petazzoni * received through a single RX descriptor, so not having each RX 778c5aff182SThomas Petazzoni * descriptor with its first and last bits set is an error 779c5aff182SThomas Petazzoni */ 7805428213cSwilly tarreau static int mvneta_rxq_desc_is_first_last(u32 status) 781c5aff182SThomas Petazzoni { 7825428213cSwilly tarreau return (status & MVNETA_RXD_FIRST_LAST_DESC) == 783c5aff182SThomas Petazzoni MVNETA_RXD_FIRST_LAST_DESC; 784c5aff182SThomas Petazzoni } 785c5aff182SThomas Petazzoni 786c5aff182SThomas Petazzoni /* Add number of descriptors ready to receive new packets */ 787c5aff182SThomas Petazzoni static void mvneta_rxq_non_occup_desc_add(struct mvneta_port *pp, 788c5aff182SThomas Petazzoni struct mvneta_rx_queue *rxq, 789c5aff182SThomas Petazzoni int ndescs) 790c5aff182SThomas Petazzoni { 791c5aff182SThomas Petazzoni /* Only MVNETA_RXQ_ADD_NON_OCCUPIED_MAX (255) descriptors can 7926a20c175SThomas Petazzoni * be added at once 7936a20c175SThomas Petazzoni */ 794c5aff182SThomas Petazzoni while (ndescs > MVNETA_RXQ_ADD_NON_OCCUPIED_MAX) { 795c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id), 796c5aff182SThomas Petazzoni (MVNETA_RXQ_ADD_NON_OCCUPIED_MAX << 797c5aff182SThomas Petazzoni MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT)); 798c5aff182SThomas Petazzoni ndescs -= MVNETA_RXQ_ADD_NON_OCCUPIED_MAX; 799c5aff182SThomas Petazzoni } 800c5aff182SThomas Petazzoni 801c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id), 802c5aff182SThomas Petazzoni (ndescs << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT)); 803c5aff182SThomas Petazzoni } 804c5aff182SThomas Petazzoni 805c5aff182SThomas Petazzoni /* Get number of RX descriptors occupied by received packets */ 806c5aff182SThomas Petazzoni static int mvneta_rxq_busy_desc_num_get(struct mvneta_port *pp, 807c5aff182SThomas Petazzoni struct mvneta_rx_queue *rxq) 808c5aff182SThomas Petazzoni { 809c5aff182SThomas Petazzoni u32 val; 810c5aff182SThomas Petazzoni 811c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_RXQ_STATUS_REG(rxq->id)); 812c5aff182SThomas Petazzoni return val & MVNETA_RXQ_OCCUPIED_ALL_MASK; 813c5aff182SThomas Petazzoni } 814c5aff182SThomas Petazzoni 8156a20c175SThomas Petazzoni /* Update num of rx desc called upon return from rx path or 816c5aff182SThomas Petazzoni * from mvneta_rxq_drop_pkts(). 817c5aff182SThomas Petazzoni */ 818c5aff182SThomas Petazzoni static void mvneta_rxq_desc_num_update(struct mvneta_port *pp, 819c5aff182SThomas Petazzoni struct mvneta_rx_queue *rxq, 820c5aff182SThomas Petazzoni int rx_done, int rx_filled) 821c5aff182SThomas Petazzoni { 822c5aff182SThomas Petazzoni u32 val; 823c5aff182SThomas Petazzoni 824c5aff182SThomas Petazzoni if ((rx_done <= 0xff) && (rx_filled <= 0xff)) { 825c5aff182SThomas Petazzoni val = rx_done | 826c5aff182SThomas Petazzoni (rx_filled << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT); 827c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id), val); 828c5aff182SThomas Petazzoni return; 829c5aff182SThomas Petazzoni } 830c5aff182SThomas Petazzoni 831c5aff182SThomas Petazzoni /* Only 255 descriptors can be added at once */ 832c5aff182SThomas Petazzoni while ((rx_done > 0) || (rx_filled > 0)) { 833c5aff182SThomas Petazzoni if (rx_done <= 0xff) { 834c5aff182SThomas Petazzoni val = rx_done; 835c5aff182SThomas Petazzoni rx_done = 0; 836c5aff182SThomas Petazzoni } else { 837c5aff182SThomas Petazzoni val = 0xff; 838c5aff182SThomas Petazzoni rx_done -= 0xff; 839c5aff182SThomas Petazzoni } 840c5aff182SThomas Petazzoni if (rx_filled <= 0xff) { 841c5aff182SThomas Petazzoni val |= rx_filled << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT; 842c5aff182SThomas Petazzoni rx_filled = 0; 843c5aff182SThomas Petazzoni } else { 844c5aff182SThomas Petazzoni val |= 0xff << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT; 845c5aff182SThomas Petazzoni rx_filled -= 0xff; 846c5aff182SThomas Petazzoni } 847c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id), val); 848c5aff182SThomas Petazzoni } 849c5aff182SThomas Petazzoni } 850c5aff182SThomas Petazzoni 851c5aff182SThomas Petazzoni /* Get pointer to next RX descriptor to be processed by SW */ 852c5aff182SThomas Petazzoni static struct mvneta_rx_desc * 853c5aff182SThomas Petazzoni mvneta_rxq_next_desc_get(struct mvneta_rx_queue *rxq) 854c5aff182SThomas Petazzoni { 855c5aff182SThomas Petazzoni int rx_desc = rxq->next_desc_to_proc; 856c5aff182SThomas Petazzoni 857c5aff182SThomas Petazzoni rxq->next_desc_to_proc = MVNETA_QUEUE_NEXT_DESC(rxq, rx_desc); 85834e4179dSwilly tarreau prefetch(rxq->descs + rxq->next_desc_to_proc); 859c5aff182SThomas Petazzoni return rxq->descs + rx_desc; 860c5aff182SThomas Petazzoni } 861c5aff182SThomas Petazzoni 862c5aff182SThomas Petazzoni /* Change maximum receive size of the port. */ 863c5aff182SThomas Petazzoni static void mvneta_max_rx_size_set(struct mvneta_port *pp, int max_rx_size) 864c5aff182SThomas Petazzoni { 865c5aff182SThomas Petazzoni u32 val; 866c5aff182SThomas Petazzoni 867c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_GMAC_CTRL_0); 868c5aff182SThomas Petazzoni val &= ~MVNETA_GMAC_MAX_RX_SIZE_MASK; 869c5aff182SThomas Petazzoni val |= ((max_rx_size - MVNETA_MH_SIZE) / 2) << 870c5aff182SThomas Petazzoni MVNETA_GMAC_MAX_RX_SIZE_SHIFT; 871c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_GMAC_CTRL_0, val); 872c5aff182SThomas Petazzoni } 873c5aff182SThomas Petazzoni 874c5aff182SThomas Petazzoni 875c5aff182SThomas Petazzoni /* Set rx queue offset */ 876c5aff182SThomas Petazzoni static void mvneta_rxq_offset_set(struct mvneta_port *pp, 877c5aff182SThomas Petazzoni struct mvneta_rx_queue *rxq, 878c5aff182SThomas Petazzoni int offset) 879c5aff182SThomas Petazzoni { 880c5aff182SThomas Petazzoni u32 val; 881c5aff182SThomas Petazzoni 882c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_RXQ_CONFIG_REG(rxq->id)); 883c5aff182SThomas Petazzoni val &= ~MVNETA_RXQ_PKT_OFFSET_ALL_MASK; 884c5aff182SThomas Petazzoni 885c5aff182SThomas Petazzoni /* Offset is in */ 886c5aff182SThomas Petazzoni val |= MVNETA_RXQ_PKT_OFFSET_MASK(offset >> 3); 887c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_RXQ_CONFIG_REG(rxq->id), val); 888c5aff182SThomas Petazzoni } 889c5aff182SThomas Petazzoni 890c5aff182SThomas Petazzoni 891c5aff182SThomas Petazzoni /* Tx descriptors helper methods */ 892c5aff182SThomas Petazzoni 893c5aff182SThomas Petazzoni /* Update HW with number of TX descriptors to be sent */ 894c5aff182SThomas Petazzoni static void mvneta_txq_pend_desc_add(struct mvneta_port *pp, 895c5aff182SThomas Petazzoni struct mvneta_tx_queue *txq, 896c5aff182SThomas Petazzoni int pend_desc) 897c5aff182SThomas Petazzoni { 898c5aff182SThomas Petazzoni u32 val; 899c5aff182SThomas Petazzoni 9000d63785cSSimon Guinot pend_desc += txq->pending; 9010d63785cSSimon Guinot 9020d63785cSSimon Guinot /* Only 255 Tx descriptors can be added at once */ 9030d63785cSSimon Guinot do { 9040d63785cSSimon Guinot val = min(pend_desc, 255); 905c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val); 9060d63785cSSimon Guinot pend_desc -= val; 9070d63785cSSimon Guinot } while (pend_desc > 0); 9082a90f7e1SSimon Guinot txq->pending = 0; 909c5aff182SThomas Petazzoni } 910c5aff182SThomas Petazzoni 911c5aff182SThomas Petazzoni /* Get pointer to next TX descriptor to be processed (send) by HW */ 912c5aff182SThomas Petazzoni static struct mvneta_tx_desc * 913c5aff182SThomas Petazzoni mvneta_txq_next_desc_get(struct mvneta_tx_queue *txq) 914c5aff182SThomas Petazzoni { 915c5aff182SThomas Petazzoni int tx_desc = txq->next_desc_to_proc; 916c5aff182SThomas Petazzoni 917c5aff182SThomas Petazzoni txq->next_desc_to_proc = MVNETA_QUEUE_NEXT_DESC(txq, tx_desc); 918c5aff182SThomas Petazzoni return txq->descs + tx_desc; 919c5aff182SThomas Petazzoni } 920c5aff182SThomas Petazzoni 921c5aff182SThomas Petazzoni /* Release the last allocated TX descriptor. Useful to handle DMA 9226a20c175SThomas Petazzoni * mapping failures in the TX path. 9236a20c175SThomas Petazzoni */ 924c5aff182SThomas Petazzoni static void mvneta_txq_desc_put(struct mvneta_tx_queue *txq) 925c5aff182SThomas Petazzoni { 926c5aff182SThomas Petazzoni if (txq->next_desc_to_proc == 0) 927c5aff182SThomas Petazzoni txq->next_desc_to_proc = txq->last_desc - 1; 928c5aff182SThomas Petazzoni else 929c5aff182SThomas Petazzoni txq->next_desc_to_proc--; 930c5aff182SThomas Petazzoni } 931c5aff182SThomas Petazzoni 932c5aff182SThomas Petazzoni /* Set rxq buf size */ 933c5aff182SThomas Petazzoni static void mvneta_rxq_buf_size_set(struct mvneta_port *pp, 934c5aff182SThomas Petazzoni struct mvneta_rx_queue *rxq, 935c5aff182SThomas Petazzoni int buf_size) 936c5aff182SThomas Petazzoni { 937c5aff182SThomas Petazzoni u32 val; 938c5aff182SThomas Petazzoni 939c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_RXQ_SIZE_REG(rxq->id)); 940c5aff182SThomas Petazzoni 941c5aff182SThomas Petazzoni val &= ~MVNETA_RXQ_BUF_SIZE_MASK; 942c5aff182SThomas Petazzoni val |= ((buf_size >> 3) << MVNETA_RXQ_BUF_SIZE_SHIFT); 943c5aff182SThomas Petazzoni 944c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_RXQ_SIZE_REG(rxq->id), val); 945c5aff182SThomas Petazzoni } 946c5aff182SThomas Petazzoni 947c5aff182SThomas Petazzoni /* Disable buffer management (BM) */ 948c5aff182SThomas Petazzoni static void mvneta_rxq_bm_disable(struct mvneta_port *pp, 949c5aff182SThomas Petazzoni struct mvneta_rx_queue *rxq) 950c5aff182SThomas Petazzoni { 951c5aff182SThomas Petazzoni u32 val; 952c5aff182SThomas Petazzoni 953c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_RXQ_CONFIG_REG(rxq->id)); 954c5aff182SThomas Petazzoni val &= ~MVNETA_RXQ_HW_BUF_ALLOC; 955c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_RXQ_CONFIG_REG(rxq->id), val); 956c5aff182SThomas Petazzoni } 957c5aff182SThomas Petazzoni 958dc35a10fSMarcin Wojtas /* Enable buffer management (BM) */ 959dc35a10fSMarcin Wojtas static void mvneta_rxq_bm_enable(struct mvneta_port *pp, 960dc35a10fSMarcin Wojtas struct mvneta_rx_queue *rxq) 961dc35a10fSMarcin Wojtas { 962dc35a10fSMarcin Wojtas u32 val; 963dc35a10fSMarcin Wojtas 964dc35a10fSMarcin Wojtas val = mvreg_read(pp, MVNETA_RXQ_CONFIG_REG(rxq->id)); 965dc35a10fSMarcin Wojtas val |= MVNETA_RXQ_HW_BUF_ALLOC; 966dc35a10fSMarcin Wojtas mvreg_write(pp, MVNETA_RXQ_CONFIG_REG(rxq->id), val); 967dc35a10fSMarcin Wojtas } 968dc35a10fSMarcin Wojtas 969dc35a10fSMarcin Wojtas /* Notify HW about port's assignment of pool for bigger packets */ 970dc35a10fSMarcin Wojtas static void mvneta_rxq_long_pool_set(struct mvneta_port *pp, 971dc35a10fSMarcin Wojtas struct mvneta_rx_queue *rxq) 972dc35a10fSMarcin Wojtas { 973dc35a10fSMarcin Wojtas u32 val; 974dc35a10fSMarcin Wojtas 975dc35a10fSMarcin Wojtas val = mvreg_read(pp, MVNETA_RXQ_CONFIG_REG(rxq->id)); 976dc35a10fSMarcin Wojtas val &= ~MVNETA_RXQ_LONG_POOL_ID_MASK; 977dc35a10fSMarcin Wojtas val |= (pp->pool_long->id << MVNETA_RXQ_LONG_POOL_ID_SHIFT); 978dc35a10fSMarcin Wojtas 979dc35a10fSMarcin Wojtas mvreg_write(pp, MVNETA_RXQ_CONFIG_REG(rxq->id), val); 980dc35a10fSMarcin Wojtas } 981dc35a10fSMarcin Wojtas 982dc35a10fSMarcin Wojtas /* Notify HW about port's assignment of pool for smaller packets */ 983dc35a10fSMarcin Wojtas static void mvneta_rxq_short_pool_set(struct mvneta_port *pp, 984dc35a10fSMarcin Wojtas struct mvneta_rx_queue *rxq) 985dc35a10fSMarcin Wojtas { 986dc35a10fSMarcin Wojtas u32 val; 987dc35a10fSMarcin Wojtas 988dc35a10fSMarcin Wojtas val = mvreg_read(pp, MVNETA_RXQ_CONFIG_REG(rxq->id)); 989dc35a10fSMarcin Wojtas val &= ~MVNETA_RXQ_SHORT_POOL_ID_MASK; 990dc35a10fSMarcin Wojtas val |= (pp->pool_short->id << MVNETA_RXQ_SHORT_POOL_ID_SHIFT); 991dc35a10fSMarcin Wojtas 992dc35a10fSMarcin Wojtas mvreg_write(pp, MVNETA_RXQ_CONFIG_REG(rxq->id), val); 993dc35a10fSMarcin Wojtas } 994dc35a10fSMarcin Wojtas 995dc35a10fSMarcin Wojtas /* Set port's receive buffer size for assigned BM pool */ 996dc35a10fSMarcin Wojtas static inline void mvneta_bm_pool_bufsize_set(struct mvneta_port *pp, 997dc35a10fSMarcin Wojtas int buf_size, 998dc35a10fSMarcin Wojtas u8 pool_id) 999dc35a10fSMarcin Wojtas { 1000dc35a10fSMarcin Wojtas u32 val; 1001dc35a10fSMarcin Wojtas 1002dc35a10fSMarcin Wojtas if (!IS_ALIGNED(buf_size, 8)) { 1003dc35a10fSMarcin Wojtas dev_warn(pp->dev->dev.parent, 1004dc35a10fSMarcin Wojtas "illegal buf_size value %d, round to %d\n", 1005dc35a10fSMarcin Wojtas buf_size, ALIGN(buf_size, 8)); 1006dc35a10fSMarcin Wojtas buf_size = ALIGN(buf_size, 8); 1007dc35a10fSMarcin Wojtas } 1008dc35a10fSMarcin Wojtas 1009dc35a10fSMarcin Wojtas val = mvreg_read(pp, MVNETA_PORT_POOL_BUFFER_SZ_REG(pool_id)); 1010dc35a10fSMarcin Wojtas val |= buf_size & MVNETA_PORT_POOL_BUFFER_SZ_MASK; 1011dc35a10fSMarcin Wojtas mvreg_write(pp, MVNETA_PORT_POOL_BUFFER_SZ_REG(pool_id), val); 1012dc35a10fSMarcin Wojtas } 1013dc35a10fSMarcin Wojtas 1014dc35a10fSMarcin Wojtas /* Configure MBUS window in order to enable access BM internal SRAM */ 1015dc35a10fSMarcin Wojtas static int mvneta_mbus_io_win_set(struct mvneta_port *pp, u32 base, u32 wsize, 1016dc35a10fSMarcin Wojtas u8 target, u8 attr) 1017dc35a10fSMarcin Wojtas { 1018dc35a10fSMarcin Wojtas u32 win_enable, win_protect; 1019dc35a10fSMarcin Wojtas int i; 1020dc35a10fSMarcin Wojtas 1021dc35a10fSMarcin Wojtas win_enable = mvreg_read(pp, MVNETA_BASE_ADDR_ENABLE); 1022dc35a10fSMarcin Wojtas 1023dc35a10fSMarcin Wojtas if (pp->bm_win_id < 0) { 1024dc35a10fSMarcin Wojtas /* Find first not occupied window */ 1025dc35a10fSMarcin Wojtas for (i = 0; i < MVNETA_MAX_DECODE_WIN; i++) { 1026dc35a10fSMarcin Wojtas if (win_enable & (1 << i)) { 1027dc35a10fSMarcin Wojtas pp->bm_win_id = i; 1028dc35a10fSMarcin Wojtas break; 1029dc35a10fSMarcin Wojtas } 1030dc35a10fSMarcin Wojtas } 1031dc35a10fSMarcin Wojtas if (i == MVNETA_MAX_DECODE_WIN) 1032dc35a10fSMarcin Wojtas return -ENOMEM; 1033dc35a10fSMarcin Wojtas } else { 1034dc35a10fSMarcin Wojtas i = pp->bm_win_id; 1035dc35a10fSMarcin Wojtas } 1036dc35a10fSMarcin Wojtas 1037dc35a10fSMarcin Wojtas mvreg_write(pp, MVNETA_WIN_BASE(i), 0); 1038dc35a10fSMarcin Wojtas mvreg_write(pp, MVNETA_WIN_SIZE(i), 0); 1039dc35a10fSMarcin Wojtas 1040dc35a10fSMarcin Wojtas if (i < 4) 1041dc35a10fSMarcin Wojtas mvreg_write(pp, MVNETA_WIN_REMAP(i), 0); 1042dc35a10fSMarcin Wojtas 1043dc35a10fSMarcin Wojtas mvreg_write(pp, MVNETA_WIN_BASE(i), (base & 0xffff0000) | 1044dc35a10fSMarcin Wojtas (attr << 8) | target); 1045dc35a10fSMarcin Wojtas 1046dc35a10fSMarcin Wojtas mvreg_write(pp, MVNETA_WIN_SIZE(i), (wsize - 1) & 0xffff0000); 1047dc35a10fSMarcin Wojtas 1048dc35a10fSMarcin Wojtas win_protect = mvreg_read(pp, MVNETA_ACCESS_PROTECT_ENABLE); 1049dc35a10fSMarcin Wojtas win_protect |= 3 << (2 * i); 1050dc35a10fSMarcin Wojtas mvreg_write(pp, MVNETA_ACCESS_PROTECT_ENABLE, win_protect); 1051dc35a10fSMarcin Wojtas 1052dc35a10fSMarcin Wojtas win_enable &= ~(1 << i); 1053dc35a10fSMarcin Wojtas mvreg_write(pp, MVNETA_BASE_ADDR_ENABLE, win_enable); 1054dc35a10fSMarcin Wojtas 1055dc35a10fSMarcin Wojtas return 0; 1056dc35a10fSMarcin Wojtas } 1057dc35a10fSMarcin Wojtas 10582636ac3cSMarcin Wojtas static int mvneta_bm_port_mbus_init(struct mvneta_port *pp) 1059dc35a10fSMarcin Wojtas { 10602636ac3cSMarcin Wojtas u32 wsize; 1061dc35a10fSMarcin Wojtas u8 target, attr; 1062dc35a10fSMarcin Wojtas int err; 1063dc35a10fSMarcin Wojtas 1064dc35a10fSMarcin Wojtas /* Get BM window information */ 1065dc35a10fSMarcin Wojtas err = mvebu_mbus_get_io_win_info(pp->bm_priv->bppi_phys_addr, &wsize, 1066dc35a10fSMarcin Wojtas &target, &attr); 1067dc35a10fSMarcin Wojtas if (err < 0) 1068dc35a10fSMarcin Wojtas return err; 1069dc35a10fSMarcin Wojtas 1070dc35a10fSMarcin Wojtas pp->bm_win_id = -1; 1071dc35a10fSMarcin Wojtas 1072dc35a10fSMarcin Wojtas /* Open NETA -> BM window */ 1073dc35a10fSMarcin Wojtas err = mvneta_mbus_io_win_set(pp, pp->bm_priv->bppi_phys_addr, wsize, 1074dc35a10fSMarcin Wojtas target, attr); 1075dc35a10fSMarcin Wojtas if (err < 0) { 1076dc35a10fSMarcin Wojtas netdev_info(pp->dev, "fail to configure mbus window to BM\n"); 1077dc35a10fSMarcin Wojtas return err; 1078dc35a10fSMarcin Wojtas } 10792636ac3cSMarcin Wojtas return 0; 10802636ac3cSMarcin Wojtas } 10812636ac3cSMarcin Wojtas 10822636ac3cSMarcin Wojtas /* Assign and initialize pools for port. In case of fail 10832636ac3cSMarcin Wojtas * buffer manager will remain disabled for current port. 10842636ac3cSMarcin Wojtas */ 10852636ac3cSMarcin Wojtas static int mvneta_bm_port_init(struct platform_device *pdev, 10862636ac3cSMarcin Wojtas struct mvneta_port *pp) 10872636ac3cSMarcin Wojtas { 10882636ac3cSMarcin Wojtas struct device_node *dn = pdev->dev.of_node; 10892636ac3cSMarcin Wojtas u32 long_pool_id, short_pool_id; 10902636ac3cSMarcin Wojtas 10912636ac3cSMarcin Wojtas if (!pp->neta_armada3700) { 10922636ac3cSMarcin Wojtas int ret; 10932636ac3cSMarcin Wojtas 10942636ac3cSMarcin Wojtas ret = mvneta_bm_port_mbus_init(pp); 10952636ac3cSMarcin Wojtas if (ret) 10962636ac3cSMarcin Wojtas return ret; 10972636ac3cSMarcin Wojtas } 1098dc35a10fSMarcin Wojtas 1099dc35a10fSMarcin Wojtas if (of_property_read_u32(dn, "bm,pool-long", &long_pool_id)) { 1100dc35a10fSMarcin Wojtas netdev_info(pp->dev, "missing long pool id\n"); 1101dc35a10fSMarcin Wojtas return -EINVAL; 1102dc35a10fSMarcin Wojtas } 1103dc35a10fSMarcin Wojtas 1104dc35a10fSMarcin Wojtas /* Create port's long pool depending on mtu */ 1105dc35a10fSMarcin Wojtas pp->pool_long = mvneta_bm_pool_use(pp->bm_priv, long_pool_id, 1106dc35a10fSMarcin Wojtas MVNETA_BM_LONG, pp->id, 1107dc35a10fSMarcin Wojtas MVNETA_RX_PKT_SIZE(pp->dev->mtu)); 1108dc35a10fSMarcin Wojtas if (!pp->pool_long) { 1109dc35a10fSMarcin Wojtas netdev_info(pp->dev, "fail to obtain long pool for port\n"); 1110dc35a10fSMarcin Wojtas return -ENOMEM; 1111dc35a10fSMarcin Wojtas } 1112dc35a10fSMarcin Wojtas 1113dc35a10fSMarcin Wojtas pp->pool_long->port_map |= 1 << pp->id; 1114dc35a10fSMarcin Wojtas 1115dc35a10fSMarcin Wojtas mvneta_bm_pool_bufsize_set(pp, pp->pool_long->buf_size, 1116dc35a10fSMarcin Wojtas pp->pool_long->id); 1117dc35a10fSMarcin Wojtas 1118dc35a10fSMarcin Wojtas /* If short pool id is not defined, assume using single pool */ 1119dc35a10fSMarcin Wojtas if (of_property_read_u32(dn, "bm,pool-short", &short_pool_id)) 1120dc35a10fSMarcin Wojtas short_pool_id = long_pool_id; 1121dc35a10fSMarcin Wojtas 1122dc35a10fSMarcin Wojtas /* Create port's short pool */ 1123dc35a10fSMarcin Wojtas pp->pool_short = mvneta_bm_pool_use(pp->bm_priv, short_pool_id, 1124dc35a10fSMarcin Wojtas MVNETA_BM_SHORT, pp->id, 1125dc35a10fSMarcin Wojtas MVNETA_BM_SHORT_PKT_SIZE); 1126dc35a10fSMarcin Wojtas if (!pp->pool_short) { 1127dc35a10fSMarcin Wojtas netdev_info(pp->dev, "fail to obtain short pool for port\n"); 1128dc35a10fSMarcin Wojtas mvneta_bm_pool_destroy(pp->bm_priv, pp->pool_long, 1 << pp->id); 1129dc35a10fSMarcin Wojtas return -ENOMEM; 1130dc35a10fSMarcin Wojtas } 1131dc35a10fSMarcin Wojtas 1132dc35a10fSMarcin Wojtas if (short_pool_id != long_pool_id) { 1133dc35a10fSMarcin Wojtas pp->pool_short->port_map |= 1 << pp->id; 1134dc35a10fSMarcin Wojtas mvneta_bm_pool_bufsize_set(pp, pp->pool_short->buf_size, 1135dc35a10fSMarcin Wojtas pp->pool_short->id); 1136dc35a10fSMarcin Wojtas } 1137dc35a10fSMarcin Wojtas 1138dc35a10fSMarcin Wojtas return 0; 1139dc35a10fSMarcin Wojtas } 1140dc35a10fSMarcin Wojtas 1141dc35a10fSMarcin Wojtas /* Update settings of a pool for bigger packets */ 1142dc35a10fSMarcin Wojtas static void mvneta_bm_update_mtu(struct mvneta_port *pp, int mtu) 1143dc35a10fSMarcin Wojtas { 1144dc35a10fSMarcin Wojtas struct mvneta_bm_pool *bm_pool = pp->pool_long; 1145baa11ebcSGregory CLEMENT struct hwbm_pool *hwbm_pool = &bm_pool->hwbm_pool; 1146dc35a10fSMarcin Wojtas int num; 1147dc35a10fSMarcin Wojtas 1148dc35a10fSMarcin Wojtas /* Release all buffers from long pool */ 1149dc35a10fSMarcin Wojtas mvneta_bm_bufs_free(pp->bm_priv, bm_pool, 1 << pp->id); 1150baa11ebcSGregory CLEMENT if (hwbm_pool->buf_num) { 1151dc35a10fSMarcin Wojtas WARN(1, "cannot free all buffers in pool %d\n", 1152dc35a10fSMarcin Wojtas bm_pool->id); 1153dc35a10fSMarcin Wojtas goto bm_mtu_err; 1154dc35a10fSMarcin Wojtas } 1155dc35a10fSMarcin Wojtas 1156dc35a10fSMarcin Wojtas bm_pool->pkt_size = MVNETA_RX_PKT_SIZE(mtu); 1157dc35a10fSMarcin Wojtas bm_pool->buf_size = MVNETA_RX_BUF_SIZE(bm_pool->pkt_size); 1158baa11ebcSGregory CLEMENT hwbm_pool->frag_size = SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) + 1159dc35a10fSMarcin Wojtas SKB_DATA_ALIGN(MVNETA_RX_BUF_SIZE(bm_pool->pkt_size)); 1160dc35a10fSMarcin Wojtas 1161dc35a10fSMarcin Wojtas /* Fill entire long pool */ 11626dcdd884SSebastian Andrzej Siewior num = hwbm_pool_add(hwbm_pool, hwbm_pool->size); 1163baa11ebcSGregory CLEMENT if (num != hwbm_pool->size) { 1164dc35a10fSMarcin Wojtas WARN(1, "pool %d: %d of %d allocated\n", 1165baa11ebcSGregory CLEMENT bm_pool->id, num, hwbm_pool->size); 1166dc35a10fSMarcin Wojtas goto bm_mtu_err; 1167dc35a10fSMarcin Wojtas } 1168dc35a10fSMarcin Wojtas mvneta_bm_pool_bufsize_set(pp, bm_pool->buf_size, bm_pool->id); 1169dc35a10fSMarcin Wojtas 1170dc35a10fSMarcin Wojtas return; 1171dc35a10fSMarcin Wojtas 1172dc35a10fSMarcin Wojtas bm_mtu_err: 1173dc35a10fSMarcin Wojtas mvneta_bm_pool_destroy(pp->bm_priv, pp->pool_long, 1 << pp->id); 1174dc35a10fSMarcin Wojtas mvneta_bm_pool_destroy(pp->bm_priv, pp->pool_short, 1 << pp->id); 1175dc35a10fSMarcin Wojtas 1176dc35a10fSMarcin Wojtas pp->bm_priv = NULL; 117744efc78dSLorenzo Bianconi pp->rx_offset_correction = MVNETA_SKB_HEADROOM; 1178dc35a10fSMarcin Wojtas mvreg_write(pp, MVNETA_ACC_MODE, MVNETA_ACC_MODE_EXT1); 1179dc35a10fSMarcin Wojtas netdev_info(pp->dev, "fail to update MTU, fall back to software BM\n"); 1180dc35a10fSMarcin Wojtas } 1181dc35a10fSMarcin Wojtas 1182c5aff182SThomas Petazzoni /* Start the Ethernet port RX and TX activity */ 1183c5aff182SThomas Petazzoni static void mvneta_port_up(struct mvneta_port *pp) 1184c5aff182SThomas Petazzoni { 1185c5aff182SThomas Petazzoni int queue; 1186c5aff182SThomas Petazzoni u32 q_map; 1187c5aff182SThomas Petazzoni 1188c5aff182SThomas Petazzoni /* Enable all initialized TXs. */ 1189c5aff182SThomas Petazzoni q_map = 0; 1190c5aff182SThomas Petazzoni for (queue = 0; queue < txq_number; queue++) { 1191c5aff182SThomas Petazzoni struct mvneta_tx_queue *txq = &pp->txqs[queue]; 1192f95936ccSMarkus Elfring if (txq->descs) 1193c5aff182SThomas Petazzoni q_map |= (1 << queue); 1194c5aff182SThomas Petazzoni } 1195c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_TXQ_CMD, q_map); 1196c5aff182SThomas Petazzoni 1197e81b5e01SYelena Krivosheev q_map = 0; 1198c5aff182SThomas Petazzoni /* Enable all initialized RXQs. */ 11992dcf75e2SGregory CLEMENT for (queue = 0; queue < rxq_number; queue++) { 12002dcf75e2SGregory CLEMENT struct mvneta_rx_queue *rxq = &pp->rxqs[queue]; 12012dcf75e2SGregory CLEMENT 1202f95936ccSMarkus Elfring if (rxq->descs) 12032dcf75e2SGregory CLEMENT q_map |= (1 << queue); 12042dcf75e2SGregory CLEMENT } 12052dcf75e2SGregory CLEMENT mvreg_write(pp, MVNETA_RXQ_CMD, q_map); 1206c5aff182SThomas Petazzoni } 1207c5aff182SThomas Petazzoni 1208c5aff182SThomas Petazzoni /* Stop the Ethernet port activity */ 1209c5aff182SThomas Petazzoni static void mvneta_port_down(struct mvneta_port *pp) 1210c5aff182SThomas Petazzoni { 1211c5aff182SThomas Petazzoni u32 val; 1212c5aff182SThomas Petazzoni int count; 1213c5aff182SThomas Petazzoni 1214c5aff182SThomas Petazzoni /* Stop Rx port activity. Check port Rx activity. */ 1215c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_RXQ_CMD) & MVNETA_RXQ_ENABLE_MASK; 1216c5aff182SThomas Petazzoni 1217c5aff182SThomas Petazzoni /* Issue stop command for active channels only */ 1218c5aff182SThomas Petazzoni if (val != 0) 1219c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_RXQ_CMD, 1220c5aff182SThomas Petazzoni val << MVNETA_RXQ_DISABLE_SHIFT); 1221c5aff182SThomas Petazzoni 1222c5aff182SThomas Petazzoni /* Wait for all Rx activity to terminate. */ 1223c5aff182SThomas Petazzoni count = 0; 1224c5aff182SThomas Petazzoni do { 1225c5aff182SThomas Petazzoni if (count++ >= MVNETA_RX_DISABLE_TIMEOUT_MSEC) { 1226c5aff182SThomas Petazzoni netdev_warn(pp->dev, 12270838abb3SDmitri Epshtein "TIMEOUT for RX stopped ! rx_queue_cmd: 0x%08x\n", 1228c5aff182SThomas Petazzoni val); 1229c5aff182SThomas Petazzoni break; 1230c5aff182SThomas Petazzoni } 1231c5aff182SThomas Petazzoni mdelay(1); 1232c5aff182SThomas Petazzoni 1233c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_RXQ_CMD); 1234a3703fb3SDmitri Epshtein } while (val & MVNETA_RXQ_ENABLE_MASK); 1235c5aff182SThomas Petazzoni 1236c5aff182SThomas Petazzoni /* Stop Tx port activity. Check port Tx activity. Issue stop 12376a20c175SThomas Petazzoni * command for active channels only 12386a20c175SThomas Petazzoni */ 1239c5aff182SThomas Petazzoni val = (mvreg_read(pp, MVNETA_TXQ_CMD)) & MVNETA_TXQ_ENABLE_MASK; 1240c5aff182SThomas Petazzoni 1241c5aff182SThomas Petazzoni if (val != 0) 1242c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_TXQ_CMD, 1243c5aff182SThomas Petazzoni (val << MVNETA_TXQ_DISABLE_SHIFT)); 1244c5aff182SThomas Petazzoni 1245c5aff182SThomas Petazzoni /* Wait for all Tx activity to terminate. */ 1246c5aff182SThomas Petazzoni count = 0; 1247c5aff182SThomas Petazzoni do { 1248c5aff182SThomas Petazzoni if (count++ >= MVNETA_TX_DISABLE_TIMEOUT_MSEC) { 1249c5aff182SThomas Petazzoni netdev_warn(pp->dev, 1250c5aff182SThomas Petazzoni "TIMEOUT for TX stopped status=0x%08x\n", 1251c5aff182SThomas Petazzoni val); 1252c5aff182SThomas Petazzoni break; 1253c5aff182SThomas Petazzoni } 1254c5aff182SThomas Petazzoni mdelay(1); 1255c5aff182SThomas Petazzoni 1256c5aff182SThomas Petazzoni /* Check TX Command reg that all Txqs are stopped */ 1257c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_TXQ_CMD); 1258c5aff182SThomas Petazzoni 1259a3703fb3SDmitri Epshtein } while (val & MVNETA_TXQ_ENABLE_MASK); 1260c5aff182SThomas Petazzoni 1261c5aff182SThomas Petazzoni /* Double check to verify that TX FIFO is empty */ 1262c5aff182SThomas Petazzoni count = 0; 1263c5aff182SThomas Petazzoni do { 1264c5aff182SThomas Petazzoni if (count++ >= MVNETA_TX_FIFO_EMPTY_TIMEOUT) { 1265c5aff182SThomas Petazzoni netdev_warn(pp->dev, 12660838abb3SDmitri Epshtein "TX FIFO empty timeout status=0x%08x\n", 1267c5aff182SThomas Petazzoni val); 1268c5aff182SThomas Petazzoni break; 1269c5aff182SThomas Petazzoni } 1270c5aff182SThomas Petazzoni mdelay(1); 1271c5aff182SThomas Petazzoni 1272c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_PORT_STATUS); 1273c5aff182SThomas Petazzoni } while (!(val & MVNETA_TX_FIFO_EMPTY) && 1274c5aff182SThomas Petazzoni (val & MVNETA_TX_IN_PRGRS)); 1275c5aff182SThomas Petazzoni 1276c5aff182SThomas Petazzoni udelay(200); 1277c5aff182SThomas Petazzoni } 1278c5aff182SThomas Petazzoni 1279c5aff182SThomas Petazzoni /* Enable the port by setting the port enable bit of the MAC control register */ 1280c5aff182SThomas Petazzoni static void mvneta_port_enable(struct mvneta_port *pp) 1281c5aff182SThomas Petazzoni { 1282c5aff182SThomas Petazzoni u32 val; 1283c5aff182SThomas Petazzoni 1284c5aff182SThomas Petazzoni /* Enable port */ 1285c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_GMAC_CTRL_0); 1286c5aff182SThomas Petazzoni val |= MVNETA_GMAC0_PORT_ENABLE; 1287c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_GMAC_CTRL_0, val); 1288c5aff182SThomas Petazzoni } 1289c5aff182SThomas Petazzoni 1290c5aff182SThomas Petazzoni /* Disable the port and wait for about 200 usec before retuning */ 1291c5aff182SThomas Petazzoni static void mvneta_port_disable(struct mvneta_port *pp) 1292c5aff182SThomas Petazzoni { 1293c5aff182SThomas Petazzoni u32 val; 1294c5aff182SThomas Petazzoni 1295c5aff182SThomas Petazzoni /* Reset the Enable bit in the Serial Control Register */ 1296c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_GMAC_CTRL_0); 1297c5aff182SThomas Petazzoni val &= ~MVNETA_GMAC0_PORT_ENABLE; 1298c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_GMAC_CTRL_0, val); 1299c5aff182SThomas Petazzoni 1300c5aff182SThomas Petazzoni udelay(200); 1301c5aff182SThomas Petazzoni } 1302c5aff182SThomas Petazzoni 1303c5aff182SThomas Petazzoni /* Multicast tables methods */ 1304c5aff182SThomas Petazzoni 1305c5aff182SThomas Petazzoni /* Set all entries in Unicast MAC Table; queue==-1 means reject all */ 1306c5aff182SThomas Petazzoni static void mvneta_set_ucast_table(struct mvneta_port *pp, int queue) 1307c5aff182SThomas Petazzoni { 1308c5aff182SThomas Petazzoni int offset; 1309c5aff182SThomas Petazzoni u32 val; 1310c5aff182SThomas Petazzoni 1311c5aff182SThomas Petazzoni if (queue == -1) { 1312c5aff182SThomas Petazzoni val = 0; 1313c5aff182SThomas Petazzoni } else { 1314c5aff182SThomas Petazzoni val = 0x1 | (queue << 1); 1315c5aff182SThomas Petazzoni val |= (val << 24) | (val << 16) | (val << 8); 1316c5aff182SThomas Petazzoni } 1317c5aff182SThomas Petazzoni 1318c5aff182SThomas Petazzoni for (offset = 0; offset <= 0xc; offset += 4) 1319c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_DA_FILT_UCAST_BASE + offset, val); 1320c5aff182SThomas Petazzoni } 1321c5aff182SThomas Petazzoni 1322c5aff182SThomas Petazzoni /* Set all entries in Special Multicast MAC Table; queue==-1 means reject all */ 1323c5aff182SThomas Petazzoni static void mvneta_set_special_mcast_table(struct mvneta_port *pp, int queue) 1324c5aff182SThomas Petazzoni { 1325c5aff182SThomas Petazzoni int offset; 1326c5aff182SThomas Petazzoni u32 val; 1327c5aff182SThomas Petazzoni 1328c5aff182SThomas Petazzoni if (queue == -1) { 1329c5aff182SThomas Petazzoni val = 0; 1330c5aff182SThomas Petazzoni } else { 1331c5aff182SThomas Petazzoni val = 0x1 | (queue << 1); 1332c5aff182SThomas Petazzoni val |= (val << 24) | (val << 16) | (val << 8); 1333c5aff182SThomas Petazzoni } 1334c5aff182SThomas Petazzoni 1335c5aff182SThomas Petazzoni for (offset = 0; offset <= 0xfc; offset += 4) 1336c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_DA_FILT_SPEC_MCAST + offset, val); 1337c5aff182SThomas Petazzoni 1338c5aff182SThomas Petazzoni } 1339c5aff182SThomas Petazzoni 1340c5aff182SThomas Petazzoni /* Set all entries in Other Multicast MAC Table. queue==-1 means reject all */ 1341c5aff182SThomas Petazzoni static void mvneta_set_other_mcast_table(struct mvneta_port *pp, int queue) 1342c5aff182SThomas Petazzoni { 1343c5aff182SThomas Petazzoni int offset; 1344c5aff182SThomas Petazzoni u32 val; 1345c5aff182SThomas Petazzoni 1346c5aff182SThomas Petazzoni if (queue == -1) { 1347c5aff182SThomas Petazzoni memset(pp->mcast_count, 0, sizeof(pp->mcast_count)); 1348c5aff182SThomas Petazzoni val = 0; 1349c5aff182SThomas Petazzoni } else { 1350c5aff182SThomas Petazzoni memset(pp->mcast_count, 1, sizeof(pp->mcast_count)); 1351c5aff182SThomas Petazzoni val = 0x1 | (queue << 1); 1352c5aff182SThomas Petazzoni val |= (val << 24) | (val << 16) | (val << 8); 1353c5aff182SThomas Petazzoni } 1354c5aff182SThomas Petazzoni 1355c5aff182SThomas Petazzoni for (offset = 0; offset <= 0xfc; offset += 4) 1356c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_DA_FILT_OTH_MCAST + offset, val); 1357c5aff182SThomas Petazzoni } 1358c5aff182SThomas Petazzoni 1359db488c10SGregory CLEMENT static void mvneta_percpu_unmask_interrupt(void *arg) 1360db488c10SGregory CLEMENT { 1361db488c10SGregory CLEMENT struct mvneta_port *pp = arg; 1362db488c10SGregory CLEMENT 1363db488c10SGregory CLEMENT /* All the queue are unmasked, but actually only the ones 1364db488c10SGregory CLEMENT * mapped to this CPU will be unmasked 1365db488c10SGregory CLEMENT */ 1366db488c10SGregory CLEMENT mvreg_write(pp, MVNETA_INTR_NEW_MASK, 1367db488c10SGregory CLEMENT MVNETA_RX_INTR_MASK_ALL | 1368db488c10SGregory CLEMENT MVNETA_TX_INTR_MASK_ALL | 1369db488c10SGregory CLEMENT MVNETA_MISCINTR_INTR_MASK); 1370db488c10SGregory CLEMENT } 1371db488c10SGregory CLEMENT 1372db488c10SGregory CLEMENT static void mvneta_percpu_mask_interrupt(void *arg) 1373db488c10SGregory CLEMENT { 1374db488c10SGregory CLEMENT struct mvneta_port *pp = arg; 1375db488c10SGregory CLEMENT 1376db488c10SGregory CLEMENT /* All the queue are masked, but actually only the ones 1377db488c10SGregory CLEMENT * mapped to this CPU will be masked 1378db488c10SGregory CLEMENT */ 1379db488c10SGregory CLEMENT mvreg_write(pp, MVNETA_INTR_NEW_MASK, 0); 1380db488c10SGregory CLEMENT mvreg_write(pp, MVNETA_INTR_OLD_MASK, 0); 1381db488c10SGregory CLEMENT mvreg_write(pp, MVNETA_INTR_MISC_MASK, 0); 1382db488c10SGregory CLEMENT } 1383db488c10SGregory CLEMENT 1384db488c10SGregory CLEMENT static void mvneta_percpu_clear_intr_cause(void *arg) 1385db488c10SGregory CLEMENT { 1386db488c10SGregory CLEMENT struct mvneta_port *pp = arg; 1387db488c10SGregory CLEMENT 1388db488c10SGregory CLEMENT /* All the queue are cleared, but actually only the ones 1389db488c10SGregory CLEMENT * mapped to this CPU will be cleared 1390db488c10SGregory CLEMENT */ 1391db488c10SGregory CLEMENT mvreg_write(pp, MVNETA_INTR_NEW_CAUSE, 0); 1392db488c10SGregory CLEMENT mvreg_write(pp, MVNETA_INTR_MISC_CAUSE, 0); 1393db488c10SGregory CLEMENT mvreg_write(pp, MVNETA_INTR_OLD_CAUSE, 0); 1394db488c10SGregory CLEMENT } 1395db488c10SGregory CLEMENT 1396c5aff182SThomas Petazzoni /* This method sets defaults to the NETA port: 1397c5aff182SThomas Petazzoni * Clears interrupt Cause and Mask registers. 1398c5aff182SThomas Petazzoni * Clears all MAC tables. 1399c5aff182SThomas Petazzoni * Sets defaults to all registers. 1400c5aff182SThomas Petazzoni * Resets RX and TX descriptor rings. 1401c5aff182SThomas Petazzoni * Resets PHY. 1402c5aff182SThomas Petazzoni * This method can be called after mvneta_port_down() to return the port 1403c5aff182SThomas Petazzoni * settings to defaults. 1404c5aff182SThomas Petazzoni */ 1405c5aff182SThomas Petazzoni static void mvneta_defaults_set(struct mvneta_port *pp) 1406c5aff182SThomas Petazzoni { 1407c5aff182SThomas Petazzoni int cpu; 1408c5aff182SThomas Petazzoni int queue; 1409c5aff182SThomas Petazzoni u32 val; 14102dcf75e2SGregory CLEMENT int max_cpu = num_present_cpus(); 1411c5aff182SThomas Petazzoni 1412c5aff182SThomas Petazzoni /* Clear all Cause registers */ 1413db488c10SGregory CLEMENT on_each_cpu(mvneta_percpu_clear_intr_cause, pp, true); 1414c5aff182SThomas Petazzoni 1415c5aff182SThomas Petazzoni /* Mask all interrupts */ 1416db488c10SGregory CLEMENT on_each_cpu(mvneta_percpu_mask_interrupt, pp, true); 1417c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_INTR_ENABLE, 0); 1418c5aff182SThomas Petazzoni 1419c5aff182SThomas Petazzoni /* Enable MBUS Retry bit16 */ 1420c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_MBUS_RETRY, 0x20); 1421c5aff182SThomas Petazzoni 142250bf8cb6SGregory CLEMENT /* Set CPU queue access map. CPUs are assigned to the RX and 142350bf8cb6SGregory CLEMENT * TX queues modulo their number. If there is only one TX 142450bf8cb6SGregory CLEMENT * queue then it is assigned to the CPU associated to the 142550bf8cb6SGregory CLEMENT * default RX queue. 14266a20c175SThomas Petazzoni */ 14272dcf75e2SGregory CLEMENT for_each_present_cpu(cpu) { 14282dcf75e2SGregory CLEMENT int rxq_map = 0, txq_map = 0; 142950bf8cb6SGregory CLEMENT int rxq, txq; 14302636ac3cSMarcin Wojtas if (!pp->neta_armada3700) { 14312dcf75e2SGregory CLEMENT for (rxq = 0; rxq < rxq_number; rxq++) 14322dcf75e2SGregory CLEMENT if ((rxq % max_cpu) == cpu) 14332dcf75e2SGregory CLEMENT rxq_map |= MVNETA_CPU_RXQ_ACCESS(rxq); 14342dcf75e2SGregory CLEMENT 143550bf8cb6SGregory CLEMENT for (txq = 0; txq < txq_number; txq++) 143650bf8cb6SGregory CLEMENT if ((txq % max_cpu) == cpu) 143750bf8cb6SGregory CLEMENT txq_map |= MVNETA_CPU_TXQ_ACCESS(txq); 143850bf8cb6SGregory CLEMENT 143950bf8cb6SGregory CLEMENT /* With only one TX queue we configure a special case 144050bf8cb6SGregory CLEMENT * which will allow to get all the irq on a single 144150bf8cb6SGregory CLEMENT * CPU 144250bf8cb6SGregory CLEMENT */ 144350bf8cb6SGregory CLEMENT if (txq_number == 1) 144450bf8cb6SGregory CLEMENT txq_map = (cpu == pp->rxq_def) ? 144550bf8cb6SGregory CLEMENT MVNETA_CPU_TXQ_ACCESS(1) : 0; 14462dcf75e2SGregory CLEMENT 14472636ac3cSMarcin Wojtas } else { 14482636ac3cSMarcin Wojtas txq_map = MVNETA_CPU_TXQ_ACCESS_ALL_MASK; 14492636ac3cSMarcin Wojtas rxq_map = MVNETA_CPU_RXQ_ACCESS_ALL_MASK; 14502636ac3cSMarcin Wojtas } 14512636ac3cSMarcin Wojtas 14522dcf75e2SGregory CLEMENT mvreg_write(pp, MVNETA_CPU_MAP(cpu), rxq_map | txq_map); 14532dcf75e2SGregory CLEMENT } 1454c5aff182SThomas Petazzoni 1455c5aff182SThomas Petazzoni /* Reset RX and TX DMAs */ 1456c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_PORT_RX_RESET, MVNETA_PORT_RX_DMA_RESET); 1457c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_PORT_TX_RESET, MVNETA_PORT_TX_DMA_RESET); 1458c5aff182SThomas Petazzoni 1459c5aff182SThomas Petazzoni /* Disable Legacy WRR, Disable EJP, Release from reset */ 1460c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_TXQ_CMD_1, 0); 1461c5aff182SThomas Petazzoni for (queue = 0; queue < txq_number; queue++) { 1462c5aff182SThomas Petazzoni mvreg_write(pp, MVETH_TXQ_TOKEN_COUNT_REG(queue), 0); 1463c5aff182SThomas Petazzoni mvreg_write(pp, MVETH_TXQ_TOKEN_CFG_REG(queue), 0); 1464c5aff182SThomas Petazzoni } 1465c5aff182SThomas Petazzoni 1466c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_PORT_TX_RESET, 0); 1467c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_PORT_RX_RESET, 0); 1468c5aff182SThomas Petazzoni 1469c5aff182SThomas Petazzoni /* Set Port Acceleration Mode */ 1470dc35a10fSMarcin Wojtas if (pp->bm_priv) 1471dc35a10fSMarcin Wojtas /* HW buffer management + legacy parser */ 1472dc35a10fSMarcin Wojtas val = MVNETA_ACC_MODE_EXT2; 1473dc35a10fSMarcin Wojtas else 1474dc35a10fSMarcin Wojtas /* SW buffer management + legacy parser */ 1475dc35a10fSMarcin Wojtas val = MVNETA_ACC_MODE_EXT1; 1476c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_ACC_MODE, val); 1477c5aff182SThomas Petazzoni 1478dc35a10fSMarcin Wojtas if (pp->bm_priv) 1479dc35a10fSMarcin Wojtas mvreg_write(pp, MVNETA_BM_ADDRESS, pp->bm_priv->bppi_phys_addr); 1480dc35a10fSMarcin Wojtas 1481c5aff182SThomas Petazzoni /* Update val of portCfg register accordingly with all RxQueue types */ 148290b74c01SGregory CLEMENT val = MVNETA_PORT_CONFIG_DEFL_VALUE(pp->rxq_def); 1483c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_PORT_CONFIG, val); 1484c5aff182SThomas Petazzoni 1485c5aff182SThomas Petazzoni val = 0; 1486c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_PORT_CONFIG_EXTEND, val); 1487c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_RX_MIN_FRAME_SIZE, 64); 1488c5aff182SThomas Petazzoni 1489c5aff182SThomas Petazzoni /* Build PORT_SDMA_CONFIG_REG */ 1490c5aff182SThomas Petazzoni val = 0; 1491c5aff182SThomas Petazzoni 1492c5aff182SThomas Petazzoni /* Default burst size */ 1493c5aff182SThomas Petazzoni val |= MVNETA_TX_BRST_SZ_MASK(MVNETA_SDMA_BRST_SIZE_16); 1494c5aff182SThomas Petazzoni val |= MVNETA_RX_BRST_SZ_MASK(MVNETA_SDMA_BRST_SIZE_16); 14959ad8fef6SThomas Petazzoni val |= MVNETA_RX_NO_DATA_SWAP | MVNETA_TX_NO_DATA_SWAP; 1496c5aff182SThomas Petazzoni 14979ad8fef6SThomas Petazzoni #if defined(__BIG_ENDIAN) 14989ad8fef6SThomas Petazzoni val |= MVNETA_DESC_SWAP; 14999ad8fef6SThomas Petazzoni #endif 1500c5aff182SThomas Petazzoni 1501c5aff182SThomas Petazzoni /* Assign port SDMA configuration */ 1502c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_SDMA_CONFIG, val); 1503c5aff182SThomas Petazzoni 150471408602SThomas Petazzoni /* Disable PHY polling in hardware, since we're using the 150571408602SThomas Petazzoni * kernel phylib to do this. 150671408602SThomas Petazzoni */ 150771408602SThomas Petazzoni val = mvreg_read(pp, MVNETA_UNIT_CONTROL); 150871408602SThomas Petazzoni val &= ~MVNETA_PHY_POLLING_ENABLE; 150971408602SThomas Petazzoni mvreg_write(pp, MVNETA_UNIT_CONTROL, val); 151071408602SThomas Petazzoni 1511c5aff182SThomas Petazzoni mvneta_set_ucast_table(pp, -1); 1512c5aff182SThomas Petazzoni mvneta_set_special_mcast_table(pp, -1); 1513c5aff182SThomas Petazzoni mvneta_set_other_mcast_table(pp, -1); 1514c5aff182SThomas Petazzoni 1515c5aff182SThomas Petazzoni /* Set port interrupt enable register - default enable all */ 1516c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_INTR_ENABLE, 1517c5aff182SThomas Petazzoni (MVNETA_RXQ_INTR_ENABLE_ALL_MASK 1518c5aff182SThomas Petazzoni | MVNETA_TXQ_INTR_ENABLE_ALL_MASK)); 1519e483911fSAndrew Lunn 1520e483911fSAndrew Lunn mvneta_mib_counters_clear(pp); 1521c5aff182SThomas Petazzoni } 1522c5aff182SThomas Petazzoni 1523c5aff182SThomas Petazzoni /* Set max sizes for tx queues */ 1524c5aff182SThomas Petazzoni static void mvneta_txq_max_tx_size_set(struct mvneta_port *pp, int max_tx_size) 1525c5aff182SThomas Petazzoni 1526c5aff182SThomas Petazzoni { 1527c5aff182SThomas Petazzoni u32 val, size, mtu; 1528c5aff182SThomas Petazzoni int queue; 1529c5aff182SThomas Petazzoni 1530c5aff182SThomas Petazzoni mtu = max_tx_size * 8; 1531c5aff182SThomas Petazzoni if (mtu > MVNETA_TX_MTU_MAX) 1532c5aff182SThomas Petazzoni mtu = MVNETA_TX_MTU_MAX; 1533c5aff182SThomas Petazzoni 1534c5aff182SThomas Petazzoni /* Set MTU */ 1535c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_TX_MTU); 1536c5aff182SThomas Petazzoni val &= ~MVNETA_TX_MTU_MAX; 1537c5aff182SThomas Petazzoni val |= mtu; 1538c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_TX_MTU, val); 1539c5aff182SThomas Petazzoni 1540c5aff182SThomas Petazzoni /* TX token size and all TXQs token size must be larger that MTU */ 1541c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_TX_TOKEN_SIZE); 1542c5aff182SThomas Petazzoni 1543c5aff182SThomas Petazzoni size = val & MVNETA_TX_TOKEN_SIZE_MAX; 1544c5aff182SThomas Petazzoni if (size < mtu) { 1545c5aff182SThomas Petazzoni size = mtu; 1546c5aff182SThomas Petazzoni val &= ~MVNETA_TX_TOKEN_SIZE_MAX; 1547c5aff182SThomas Petazzoni val |= size; 1548c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_TX_TOKEN_SIZE, val); 1549c5aff182SThomas Petazzoni } 1550c5aff182SThomas Petazzoni for (queue = 0; queue < txq_number; queue++) { 1551c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_TXQ_TOKEN_SIZE_REG(queue)); 1552c5aff182SThomas Petazzoni 1553c5aff182SThomas Petazzoni size = val & MVNETA_TXQ_TOKEN_SIZE_MAX; 1554c5aff182SThomas Petazzoni if (size < mtu) { 1555c5aff182SThomas Petazzoni size = mtu; 1556c5aff182SThomas Petazzoni val &= ~MVNETA_TXQ_TOKEN_SIZE_MAX; 1557c5aff182SThomas Petazzoni val |= size; 1558c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_TXQ_TOKEN_SIZE_REG(queue), val); 1559c5aff182SThomas Petazzoni } 1560c5aff182SThomas Petazzoni } 1561c5aff182SThomas Petazzoni } 1562c5aff182SThomas Petazzoni 1563c5aff182SThomas Petazzoni /* Set unicast address */ 1564c5aff182SThomas Petazzoni static void mvneta_set_ucast_addr(struct mvneta_port *pp, u8 last_nibble, 1565c5aff182SThomas Petazzoni int queue) 1566c5aff182SThomas Petazzoni { 1567c5aff182SThomas Petazzoni unsigned int unicast_reg; 1568c5aff182SThomas Petazzoni unsigned int tbl_offset; 1569c5aff182SThomas Petazzoni unsigned int reg_offset; 1570c5aff182SThomas Petazzoni 1571c5aff182SThomas Petazzoni /* Locate the Unicast table entry */ 1572c5aff182SThomas Petazzoni last_nibble = (0xf & last_nibble); 1573c5aff182SThomas Petazzoni 1574c5aff182SThomas Petazzoni /* offset from unicast tbl base */ 1575c5aff182SThomas Petazzoni tbl_offset = (last_nibble / 4) * 4; 1576c5aff182SThomas Petazzoni 1577c5aff182SThomas Petazzoni /* offset within the above reg */ 1578c5aff182SThomas Petazzoni reg_offset = last_nibble % 4; 1579c5aff182SThomas Petazzoni 1580c5aff182SThomas Petazzoni unicast_reg = mvreg_read(pp, (MVNETA_DA_FILT_UCAST_BASE + tbl_offset)); 1581c5aff182SThomas Petazzoni 1582c5aff182SThomas Petazzoni if (queue == -1) { 1583c5aff182SThomas Petazzoni /* Clear accepts frame bit at specified unicast DA tbl entry */ 1584c5aff182SThomas Petazzoni unicast_reg &= ~(0xff << (8 * reg_offset)); 1585c5aff182SThomas Petazzoni } else { 1586c5aff182SThomas Petazzoni unicast_reg &= ~(0xff << (8 * reg_offset)); 1587c5aff182SThomas Petazzoni unicast_reg |= ((0x01 | (queue << 1)) << (8 * reg_offset)); 1588c5aff182SThomas Petazzoni } 1589c5aff182SThomas Petazzoni 1590c5aff182SThomas Petazzoni mvreg_write(pp, (MVNETA_DA_FILT_UCAST_BASE + tbl_offset), unicast_reg); 1591c5aff182SThomas Petazzoni } 1592c5aff182SThomas Petazzoni 1593c5aff182SThomas Petazzoni /* Set mac address */ 1594c5aff182SThomas Petazzoni static void mvneta_mac_addr_set(struct mvneta_port *pp, unsigned char *addr, 1595c5aff182SThomas Petazzoni int queue) 1596c5aff182SThomas Petazzoni { 1597c5aff182SThomas Petazzoni unsigned int mac_h; 1598c5aff182SThomas Petazzoni unsigned int mac_l; 1599c5aff182SThomas Petazzoni 1600c5aff182SThomas Petazzoni if (queue != -1) { 1601c5aff182SThomas Petazzoni mac_l = (addr[4] << 8) | (addr[5]); 1602c5aff182SThomas Petazzoni mac_h = (addr[0] << 24) | (addr[1] << 16) | 1603c5aff182SThomas Petazzoni (addr[2] << 8) | (addr[3] << 0); 1604c5aff182SThomas Petazzoni 1605c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_MAC_ADDR_LOW, mac_l); 1606c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_MAC_ADDR_HIGH, mac_h); 1607c5aff182SThomas Petazzoni } 1608c5aff182SThomas Petazzoni 1609c5aff182SThomas Petazzoni /* Accept frames of this address */ 1610c5aff182SThomas Petazzoni mvneta_set_ucast_addr(pp, addr[5], queue); 1611c5aff182SThomas Petazzoni } 1612c5aff182SThomas Petazzoni 16136a20c175SThomas Petazzoni /* Set the number of packets that will be received before RX interrupt 16146a20c175SThomas Petazzoni * will be generated by HW. 1615c5aff182SThomas Petazzoni */ 1616c5aff182SThomas Petazzoni static void mvneta_rx_pkts_coal_set(struct mvneta_port *pp, 1617c5aff182SThomas Petazzoni struct mvneta_rx_queue *rxq, u32 value) 1618c5aff182SThomas Petazzoni { 1619c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_RXQ_THRESHOLD_REG(rxq->id), 1620c5aff182SThomas Petazzoni value | MVNETA_RXQ_NON_OCCUPIED(0)); 1621c5aff182SThomas Petazzoni } 1622c5aff182SThomas Petazzoni 16236a20c175SThomas Petazzoni /* Set the time delay in usec before RX interrupt will be generated by 16246a20c175SThomas Petazzoni * HW. 1625c5aff182SThomas Petazzoni */ 1626c5aff182SThomas Petazzoni static void mvneta_rx_time_coal_set(struct mvneta_port *pp, 1627c5aff182SThomas Petazzoni struct mvneta_rx_queue *rxq, u32 value) 1628c5aff182SThomas Petazzoni { 1629189dd626SThomas Petazzoni u32 val; 1630189dd626SThomas Petazzoni unsigned long clk_rate; 1631189dd626SThomas Petazzoni 1632189dd626SThomas Petazzoni clk_rate = clk_get_rate(pp->clk); 1633189dd626SThomas Petazzoni val = (clk_rate / 1000000) * value; 1634c5aff182SThomas Petazzoni 1635c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_RXQ_TIME_COAL_REG(rxq->id), val); 1636c5aff182SThomas Petazzoni } 1637c5aff182SThomas Petazzoni 1638c5aff182SThomas Petazzoni /* Set threshold for TX_DONE pkts coalescing */ 1639c5aff182SThomas Petazzoni static void mvneta_tx_done_pkts_coal_set(struct mvneta_port *pp, 1640c5aff182SThomas Petazzoni struct mvneta_tx_queue *txq, u32 value) 1641c5aff182SThomas Petazzoni { 1642c5aff182SThomas Petazzoni u32 val; 1643c5aff182SThomas Petazzoni 1644c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_TXQ_SIZE_REG(txq->id)); 1645c5aff182SThomas Petazzoni 1646c5aff182SThomas Petazzoni val &= ~MVNETA_TXQ_SENT_THRESH_ALL_MASK; 1647c5aff182SThomas Petazzoni val |= MVNETA_TXQ_SENT_THRESH_MASK(value); 1648c5aff182SThomas Petazzoni 1649c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_TXQ_SIZE_REG(txq->id), val); 1650c5aff182SThomas Petazzoni } 1651c5aff182SThomas Petazzoni 1652c5aff182SThomas Petazzoni /* Handle rx descriptor fill by setting buf_cookie and buf_phys_addr */ 1653c5aff182SThomas Petazzoni static void mvneta_rx_desc_fill(struct mvneta_rx_desc *rx_desc, 1654f88bee1cSGregory CLEMENT u32 phys_addr, void *virt_addr, 1655f88bee1cSGregory CLEMENT struct mvneta_rx_queue *rxq) 1656c5aff182SThomas Petazzoni { 1657f88bee1cSGregory CLEMENT int i; 1658f88bee1cSGregory CLEMENT 1659c5aff182SThomas Petazzoni rx_desc->buf_phys_addr = phys_addr; 1660f88bee1cSGregory CLEMENT i = rx_desc - rxq->descs; 1661f88bee1cSGregory CLEMENT rxq->buf_virt_addr[i] = virt_addr; 1662c5aff182SThomas Petazzoni } 1663c5aff182SThomas Petazzoni 1664c5aff182SThomas Petazzoni /* Decrement sent descriptors counter */ 1665c5aff182SThomas Petazzoni static void mvneta_txq_sent_desc_dec(struct mvneta_port *pp, 1666c5aff182SThomas Petazzoni struct mvneta_tx_queue *txq, 1667c5aff182SThomas Petazzoni int sent_desc) 1668c5aff182SThomas Petazzoni { 1669c5aff182SThomas Petazzoni u32 val; 1670c5aff182SThomas Petazzoni 1671c5aff182SThomas Petazzoni /* Only 255 TX descriptors can be updated at once */ 1672c5aff182SThomas Petazzoni while (sent_desc > 0xff) { 1673c5aff182SThomas Petazzoni val = 0xff << MVNETA_TXQ_DEC_SENT_SHIFT; 1674c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val); 1675c5aff182SThomas Petazzoni sent_desc = sent_desc - 0xff; 1676c5aff182SThomas Petazzoni } 1677c5aff182SThomas Petazzoni 1678c5aff182SThomas Petazzoni val = sent_desc << MVNETA_TXQ_DEC_SENT_SHIFT; 1679c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val); 1680c5aff182SThomas Petazzoni } 1681c5aff182SThomas Petazzoni 1682c5aff182SThomas Petazzoni /* Get number of TX descriptors already sent by HW */ 1683c5aff182SThomas Petazzoni static int mvneta_txq_sent_desc_num_get(struct mvneta_port *pp, 1684c5aff182SThomas Petazzoni struct mvneta_tx_queue *txq) 1685c5aff182SThomas Petazzoni { 1686c5aff182SThomas Petazzoni u32 val; 1687c5aff182SThomas Petazzoni int sent_desc; 1688c5aff182SThomas Petazzoni 1689c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_TXQ_STATUS_REG(txq->id)); 1690c5aff182SThomas Petazzoni sent_desc = (val & MVNETA_TXQ_SENT_DESC_MASK) >> 1691c5aff182SThomas Petazzoni MVNETA_TXQ_SENT_DESC_SHIFT; 1692c5aff182SThomas Petazzoni 1693c5aff182SThomas Petazzoni return sent_desc; 1694c5aff182SThomas Petazzoni } 1695c5aff182SThomas Petazzoni 16966a20c175SThomas Petazzoni /* Get number of sent descriptors and decrement counter. 1697c5aff182SThomas Petazzoni * The number of sent descriptors is returned. 1698c5aff182SThomas Petazzoni */ 1699c5aff182SThomas Petazzoni static int mvneta_txq_sent_desc_proc(struct mvneta_port *pp, 1700c5aff182SThomas Petazzoni struct mvneta_tx_queue *txq) 1701c5aff182SThomas Petazzoni { 1702c5aff182SThomas Petazzoni int sent_desc; 1703c5aff182SThomas Petazzoni 1704c5aff182SThomas Petazzoni /* Get number of sent descriptors */ 1705c5aff182SThomas Petazzoni sent_desc = mvneta_txq_sent_desc_num_get(pp, txq); 1706c5aff182SThomas Petazzoni 1707c5aff182SThomas Petazzoni /* Decrement sent descriptors counter */ 1708c5aff182SThomas Petazzoni if (sent_desc) 1709c5aff182SThomas Petazzoni mvneta_txq_sent_desc_dec(pp, txq, sent_desc); 1710c5aff182SThomas Petazzoni 1711c5aff182SThomas Petazzoni return sent_desc; 1712c5aff182SThomas Petazzoni } 1713c5aff182SThomas Petazzoni 1714c5aff182SThomas Petazzoni /* Set TXQ descriptors fields relevant for CSUM calculation */ 1715c5aff182SThomas Petazzoni static u32 mvneta_txq_desc_csum(int l3_offs, int l3_proto, 1716c5aff182SThomas Petazzoni int ip_hdr_len, int l4_proto) 1717c5aff182SThomas Petazzoni { 1718c5aff182SThomas Petazzoni u32 command; 1719c5aff182SThomas Petazzoni 1720c5aff182SThomas Petazzoni /* Fields: L3_offset, IP_hdrlen, L3_type, G_IPv4_chk, 17216a20c175SThomas Petazzoni * G_L4_chk, L4_type; required only for checksum 17226a20c175SThomas Petazzoni * calculation 17236a20c175SThomas Petazzoni */ 1724c5aff182SThomas Petazzoni command = l3_offs << MVNETA_TX_L3_OFF_SHIFT; 1725c5aff182SThomas Petazzoni command |= ip_hdr_len << MVNETA_TX_IP_HLEN_SHIFT; 1726c5aff182SThomas Petazzoni 17270a198587SThomas Fitzsimmons if (l3_proto == htons(ETH_P_IP)) 1728c5aff182SThomas Petazzoni command |= MVNETA_TXD_IP_CSUM; 1729c5aff182SThomas Petazzoni else 1730c5aff182SThomas Petazzoni command |= MVNETA_TX_L3_IP6; 1731c5aff182SThomas Petazzoni 1732c5aff182SThomas Petazzoni if (l4_proto == IPPROTO_TCP) 1733c5aff182SThomas Petazzoni command |= MVNETA_TX_L4_CSUM_FULL; 1734c5aff182SThomas Petazzoni else if (l4_proto == IPPROTO_UDP) 1735c5aff182SThomas Petazzoni command |= MVNETA_TX_L4_UDP | MVNETA_TX_L4_CSUM_FULL; 1736c5aff182SThomas Petazzoni else 1737c5aff182SThomas Petazzoni command |= MVNETA_TX_L4_CSUM_NOT; 1738c5aff182SThomas Petazzoni 1739c5aff182SThomas Petazzoni return command; 1740c5aff182SThomas Petazzoni } 1741c5aff182SThomas Petazzoni 1742c5aff182SThomas Petazzoni 1743c5aff182SThomas Petazzoni /* Display more error info */ 1744c5aff182SThomas Petazzoni static void mvneta_rx_error(struct mvneta_port *pp, 1745c5aff182SThomas Petazzoni struct mvneta_rx_desc *rx_desc) 1746c5aff182SThomas Petazzoni { 1747c35947b8SLorenzo Bianconi struct mvneta_pcpu_stats *stats = this_cpu_ptr(pp->stats); 1748c5aff182SThomas Petazzoni u32 status = rx_desc->status; 1749c5aff182SThomas Petazzoni 1750c35947b8SLorenzo Bianconi /* update per-cpu counter */ 1751c35947b8SLorenzo Bianconi u64_stats_update_begin(&stats->syncp); 1752c35947b8SLorenzo Bianconi stats->rx_errors++; 1753c35947b8SLorenzo Bianconi u64_stats_update_end(&stats->syncp); 1754c35947b8SLorenzo Bianconi 1755c5aff182SThomas Petazzoni switch (status & MVNETA_RXD_ERR_CODE_MASK) { 1756c5aff182SThomas Petazzoni case MVNETA_RXD_ERR_CRC: 1757c5aff182SThomas Petazzoni netdev_err(pp->dev, "bad rx status %08x (crc error), size=%d\n", 1758c5aff182SThomas Petazzoni status, rx_desc->data_size); 1759c5aff182SThomas Petazzoni break; 1760c5aff182SThomas Petazzoni case MVNETA_RXD_ERR_OVERRUN: 1761c5aff182SThomas Petazzoni netdev_err(pp->dev, "bad rx status %08x (overrun error), size=%d\n", 1762c5aff182SThomas Petazzoni status, rx_desc->data_size); 1763c5aff182SThomas Petazzoni break; 1764c5aff182SThomas Petazzoni case MVNETA_RXD_ERR_LEN: 1765c5aff182SThomas Petazzoni netdev_err(pp->dev, "bad rx status %08x (max frame length error), size=%d\n", 1766c5aff182SThomas Petazzoni status, rx_desc->data_size); 1767c5aff182SThomas Petazzoni break; 1768c5aff182SThomas Petazzoni case MVNETA_RXD_ERR_RESOURCE: 1769c5aff182SThomas Petazzoni netdev_err(pp->dev, "bad rx status %08x (resource error), size=%d\n", 1770c5aff182SThomas Petazzoni status, rx_desc->data_size); 1771c5aff182SThomas Petazzoni break; 1772c5aff182SThomas Petazzoni } 1773c5aff182SThomas Petazzoni } 1774c5aff182SThomas Petazzoni 17755428213cSwilly tarreau /* Handle RX checksum offload based on the descriptor's status */ 17765428213cSwilly tarreau static void mvneta_rx_csum(struct mvneta_port *pp, u32 status, 1777c5aff182SThomas Petazzoni struct sk_buff *skb) 1778c5aff182SThomas Petazzoni { 1779f945cec8SYelena Krivosheev if ((pp->dev->features & NETIF_F_RXCSUM) && 1780f945cec8SYelena Krivosheev (status & MVNETA_RXD_L3_IP4) && 17815428213cSwilly tarreau (status & MVNETA_RXD_L4_CSUM_OK)) { 1782c5aff182SThomas Petazzoni skb->csum = 0; 1783c5aff182SThomas Petazzoni skb->ip_summed = CHECKSUM_UNNECESSARY; 1784c5aff182SThomas Petazzoni return; 1785c5aff182SThomas Petazzoni } 1786c5aff182SThomas Petazzoni 1787c5aff182SThomas Petazzoni skb->ip_summed = CHECKSUM_NONE; 1788c5aff182SThomas Petazzoni } 1789c5aff182SThomas Petazzoni 17906c498974Swilly tarreau /* Return tx queue pointer (find last set bit) according to <cause> returned 17916c498974Swilly tarreau * form tx_done reg. <cause> must not be null. The return value is always a 17926c498974Swilly tarreau * valid queue for matching the first one found in <cause>. 17936c498974Swilly tarreau */ 1794c5aff182SThomas Petazzoni static struct mvneta_tx_queue *mvneta_tx_done_policy(struct mvneta_port *pp, 1795c5aff182SThomas Petazzoni u32 cause) 1796c5aff182SThomas Petazzoni { 1797c5aff182SThomas Petazzoni int queue = fls(cause) - 1; 1798c5aff182SThomas Petazzoni 17996c498974Swilly tarreau return &pp->txqs[queue]; 1800c5aff182SThomas Petazzoni } 1801c5aff182SThomas Petazzoni 1802c5aff182SThomas Petazzoni /* Free tx queue skbuffs */ 1803c5aff182SThomas Petazzoni static void mvneta_txq_bufs_free(struct mvneta_port *pp, 1804a29b6235SMarcin Wojtas struct mvneta_tx_queue *txq, int num, 1805a29b6235SMarcin Wojtas struct netdev_queue *nq) 1806c5aff182SThomas Petazzoni { 1807a29b6235SMarcin Wojtas unsigned int bytes_compl = 0, pkts_compl = 0; 1808c5aff182SThomas Petazzoni int i; 1809c5aff182SThomas Petazzoni 1810c5aff182SThomas Petazzoni for (i = 0; i < num; i++) { 18119e58c8b4SLorenzo Bianconi struct mvneta_tx_buf *buf = &txq->buf[txq->txq_get_index]; 1812c5aff182SThomas Petazzoni struct mvneta_tx_desc *tx_desc = txq->descs + 1813c5aff182SThomas Petazzoni txq->txq_get_index; 1814a29b6235SMarcin Wojtas 1815c5aff182SThomas Petazzoni mvneta_txq_inc_get(txq); 1816c5aff182SThomas Petazzoni 1817b0a43db9SLorenzo Bianconi if (!IS_TSO_HEADER(txq, tx_desc->buf_phys_addr) && 1818b0a43db9SLorenzo Bianconi buf->type != MVNETA_TYPE_XDP_TX) 18192e3173a3SEzequiel Garcia dma_unmap_single(pp->dev->dev.parent, 18202e3173a3SEzequiel Garcia tx_desc->buf_phys_addr, 1821c5aff182SThomas Petazzoni tx_desc->data_size, DMA_TO_DEVICE); 1822b0a43db9SLorenzo Bianconi if (buf->type == MVNETA_TYPE_SKB && buf->skb) { 18239e58c8b4SLorenzo Bianconi bytes_compl += buf->skb->len; 18249e58c8b4SLorenzo Bianconi pkts_compl++; 18259e58c8b4SLorenzo Bianconi dev_kfree_skb_any(buf->skb); 1826b0a43db9SLorenzo Bianconi } else if (buf->type == MVNETA_TYPE_XDP_TX || 1827b0a43db9SLorenzo Bianconi buf->type == MVNETA_TYPE_XDP_NDO) { 1828b0a43db9SLorenzo Bianconi xdp_return_frame(buf->xdpf); 1829b0a43db9SLorenzo Bianconi } 1830c5aff182SThomas Petazzoni } 1831a29b6235SMarcin Wojtas 1832a29b6235SMarcin Wojtas netdev_tx_completed_queue(nq, pkts_compl, bytes_compl); 1833c5aff182SThomas Petazzoni } 1834c5aff182SThomas Petazzoni 1835c5aff182SThomas Petazzoni /* Handle end of transmission */ 1836cd713199SArnaud Ebalard static void mvneta_txq_done(struct mvneta_port *pp, 1837c5aff182SThomas Petazzoni struct mvneta_tx_queue *txq) 1838c5aff182SThomas Petazzoni { 1839c5aff182SThomas Petazzoni struct netdev_queue *nq = netdev_get_tx_queue(pp->dev, txq->id); 1840c5aff182SThomas Petazzoni int tx_done; 1841c5aff182SThomas Petazzoni 1842c5aff182SThomas Petazzoni tx_done = mvneta_txq_sent_desc_proc(pp, txq); 1843cd713199SArnaud Ebalard if (!tx_done) 1844cd713199SArnaud Ebalard return; 1845cd713199SArnaud Ebalard 1846a29b6235SMarcin Wojtas mvneta_txq_bufs_free(pp, txq, tx_done, nq); 1847c5aff182SThomas Petazzoni 1848c5aff182SThomas Petazzoni txq->count -= tx_done; 1849c5aff182SThomas Petazzoni 1850c5aff182SThomas Petazzoni if (netif_tx_queue_stopped(nq)) { 18518eef5f97SEzequiel Garcia if (txq->count <= txq->tx_wake_threshold) 1852c5aff182SThomas Petazzoni netif_tx_wake_queue(nq); 1853c5aff182SThomas Petazzoni } 1854c5aff182SThomas Petazzoni } 1855c5aff182SThomas Petazzoni 1856dc35a10fSMarcin Wojtas /* Refill processing for SW buffer management */ 18577e47fd84SGregory CLEMENT /* Allocate page per descriptor */ 1858c5aff182SThomas Petazzoni static int mvneta_rx_refill(struct mvneta_port *pp, 1859f88bee1cSGregory CLEMENT struct mvneta_rx_desc *rx_desc, 18607e47fd84SGregory CLEMENT struct mvneta_rx_queue *rxq, 18617e47fd84SGregory CLEMENT gfp_t gfp_mask) 1862c5aff182SThomas Petazzoni { 1863c5aff182SThomas Petazzoni dma_addr_t phys_addr; 18647e47fd84SGregory CLEMENT struct page *page; 1865c5aff182SThomas Petazzoni 1866568a3fa2SLorenzo Bianconi page = page_pool_alloc_pages(rxq->page_pool, 1867568a3fa2SLorenzo Bianconi gfp_mask | __GFP_NOWARN); 18687e47fd84SGregory CLEMENT if (!page) 1869c5aff182SThomas Petazzoni return -ENOMEM; 1870c5aff182SThomas Petazzoni 1871568a3fa2SLorenzo Bianconi phys_addr = page_pool_get_dma_addr(page) + pp->rx_offset_correction; 18727e47fd84SGregory CLEMENT mvneta_rx_desc_fill(rx_desc, phys_addr, page, rxq); 1873568a3fa2SLorenzo Bianconi 1874c5aff182SThomas Petazzoni return 0; 1875c5aff182SThomas Petazzoni } 1876c5aff182SThomas Petazzoni 1877c5aff182SThomas Petazzoni /* Handle tx checksum */ 1878c5aff182SThomas Petazzoni static u32 mvneta_skb_tx_csum(struct mvneta_port *pp, struct sk_buff *skb) 1879c5aff182SThomas Petazzoni { 1880c5aff182SThomas Petazzoni if (skb->ip_summed == CHECKSUM_PARTIAL) { 1881c5aff182SThomas Petazzoni int ip_hdr_len = 0; 1882817dbfa5SVlad Yasevich __be16 l3_proto = vlan_get_protocol(skb); 1883c5aff182SThomas Petazzoni u8 l4_proto; 1884c5aff182SThomas Petazzoni 1885817dbfa5SVlad Yasevich if (l3_proto == htons(ETH_P_IP)) { 1886c5aff182SThomas Petazzoni struct iphdr *ip4h = ip_hdr(skb); 1887c5aff182SThomas Petazzoni 1888c5aff182SThomas Petazzoni /* Calculate IPv4 checksum and L4 checksum */ 1889c5aff182SThomas Petazzoni ip_hdr_len = ip4h->ihl; 1890c5aff182SThomas Petazzoni l4_proto = ip4h->protocol; 1891817dbfa5SVlad Yasevich } else if (l3_proto == htons(ETH_P_IPV6)) { 1892c5aff182SThomas Petazzoni struct ipv6hdr *ip6h = ipv6_hdr(skb); 1893c5aff182SThomas Petazzoni 1894c5aff182SThomas Petazzoni /* Read l4_protocol from one of IPv6 extra headers */ 1895c5aff182SThomas Petazzoni if (skb_network_header_len(skb) > 0) 1896c5aff182SThomas Petazzoni ip_hdr_len = (skb_network_header_len(skb) >> 2); 1897c5aff182SThomas Petazzoni l4_proto = ip6h->nexthdr; 1898c5aff182SThomas Petazzoni } else 1899c5aff182SThomas Petazzoni return MVNETA_TX_L4_CSUM_NOT; 1900c5aff182SThomas Petazzoni 1901c5aff182SThomas Petazzoni return mvneta_txq_desc_csum(skb_network_offset(skb), 1902817dbfa5SVlad Yasevich l3_proto, ip_hdr_len, l4_proto); 1903c5aff182SThomas Petazzoni } 1904c5aff182SThomas Petazzoni 1905c5aff182SThomas Petazzoni return MVNETA_TX_L4_CSUM_NOT; 1906c5aff182SThomas Petazzoni } 1907c5aff182SThomas Petazzoni 1908c5aff182SThomas Petazzoni /* Drop packets received by the RXQ and free buffers */ 1909c5aff182SThomas Petazzoni static void mvneta_rxq_drop_pkts(struct mvneta_port *pp, 1910c5aff182SThomas Petazzoni struct mvneta_rx_queue *rxq) 1911c5aff182SThomas Petazzoni { 1912c5aff182SThomas Petazzoni int rx_done, i; 1913c5aff182SThomas Petazzoni 1914c5aff182SThomas Petazzoni rx_done = mvneta_rxq_busy_desc_num_get(pp, rxq); 1915dc35a10fSMarcin Wojtas if (rx_done) 1916dc35a10fSMarcin Wojtas mvneta_rxq_desc_num_update(pp, rxq, rx_done, rx_done); 1917dc35a10fSMarcin Wojtas 1918dc35a10fSMarcin Wojtas if (pp->bm_priv) { 1919dc35a10fSMarcin Wojtas for (i = 0; i < rx_done; i++) { 1920dc35a10fSMarcin Wojtas struct mvneta_rx_desc *rx_desc = 1921dc35a10fSMarcin Wojtas mvneta_rxq_next_desc_get(rxq); 1922dc35a10fSMarcin Wojtas u8 pool_id = MVNETA_RX_GET_BM_POOL_ID(rx_desc); 1923dc35a10fSMarcin Wojtas struct mvneta_bm_pool *bm_pool; 1924dc35a10fSMarcin Wojtas 1925dc35a10fSMarcin Wojtas bm_pool = &pp->bm_priv->bm_pools[pool_id]; 1926dc35a10fSMarcin Wojtas /* Return dropped buffer to the pool */ 1927dc35a10fSMarcin Wojtas mvneta_bm_pool_put_bp(pp->bm_priv, bm_pool, 1928dc35a10fSMarcin Wojtas rx_desc->buf_phys_addr); 1929dc35a10fSMarcin Wojtas } 1930dc35a10fSMarcin Wojtas return; 1931dc35a10fSMarcin Wojtas } 1932dc35a10fSMarcin Wojtas 1933c5aff182SThomas Petazzoni for (i = 0; i < rxq->size; i++) { 1934c5aff182SThomas Petazzoni struct mvneta_rx_desc *rx_desc = rxq->descs + i; 1935f88bee1cSGregory CLEMENT void *data = rxq->buf_virt_addr[i]; 1936562e2f46SYelena Krivosheev if (!data || !(rx_desc->buf_phys_addr)) 1937562e2f46SYelena Krivosheev continue; 1938c5aff182SThomas Petazzoni 1939568a3fa2SLorenzo Bianconi page_pool_put_page(rxq->page_pool, data, false); 1940dc35a10fSMarcin Wojtas } 1941568a3fa2SLorenzo Bianconi if (xdp_rxq_info_is_reg(&rxq->xdp_rxq)) 1942568a3fa2SLorenzo Bianconi xdp_rxq_info_unreg(&rxq->xdp_rxq); 1943568a3fa2SLorenzo Bianconi page_pool_destroy(rxq->page_pool); 1944568a3fa2SLorenzo Bianconi rxq->page_pool = NULL; 1945c5aff182SThomas Petazzoni } 1946c5aff182SThomas Petazzoni 1947ff519e2aSLorenzo Bianconi static void 194869de66fcSLorenzo Bianconi mvneta_update_stats(struct mvneta_port *pp, u32 pkts, u32 len) 1949ff519e2aSLorenzo Bianconi { 1950ff519e2aSLorenzo Bianconi struct mvneta_pcpu_stats *stats = this_cpu_ptr(pp->stats); 1951ff519e2aSLorenzo Bianconi 1952ff519e2aSLorenzo Bianconi u64_stats_update_begin(&stats->syncp); 1953ff519e2aSLorenzo Bianconi stats->rx_packets += pkts; 1954ff519e2aSLorenzo Bianconi stats->rx_bytes += len; 1955ff519e2aSLorenzo Bianconi u64_stats_update_end(&stats->syncp); 1956ff519e2aSLorenzo Bianconi } 1957ff519e2aSLorenzo Bianconi 1958562e2f46SYelena Krivosheev static inline 1959562e2f46SYelena Krivosheev int mvneta_rx_refill_queue(struct mvneta_port *pp, struct mvneta_rx_queue *rxq) 1960562e2f46SYelena Krivosheev { 1961562e2f46SYelena Krivosheev struct mvneta_rx_desc *rx_desc; 1962562e2f46SYelena Krivosheev int curr_desc = rxq->first_to_refill; 1963562e2f46SYelena Krivosheev int i; 1964562e2f46SYelena Krivosheev 1965562e2f46SYelena Krivosheev for (i = 0; (i < rxq->refill_num) && (i < 64); i++) { 1966562e2f46SYelena Krivosheev rx_desc = rxq->descs + curr_desc; 1967562e2f46SYelena Krivosheev if (!(rx_desc->buf_phys_addr)) { 1968562e2f46SYelena Krivosheev if (mvneta_rx_refill(pp, rx_desc, rxq, GFP_ATOMIC)) { 19699ac41f3cSLorenzo Bianconi struct mvneta_pcpu_stats *stats; 19709ac41f3cSLorenzo Bianconi 1971562e2f46SYelena Krivosheev pr_err("Can't refill queue %d. Done %d from %d\n", 1972562e2f46SYelena Krivosheev rxq->id, i, rxq->refill_num); 19739ac41f3cSLorenzo Bianconi 19749ac41f3cSLorenzo Bianconi stats = this_cpu_ptr(pp->stats); 19759ac41f3cSLorenzo Bianconi u64_stats_update_begin(&stats->syncp); 19769ac41f3cSLorenzo Bianconi stats->es.refill_error++; 19779ac41f3cSLorenzo Bianconi u64_stats_update_end(&stats->syncp); 1978562e2f46SYelena Krivosheev break; 1979562e2f46SYelena Krivosheev } 1980562e2f46SYelena Krivosheev } 1981562e2f46SYelena Krivosheev curr_desc = MVNETA_QUEUE_NEXT_DESC(rxq, curr_desc); 1982562e2f46SYelena Krivosheev } 1983562e2f46SYelena Krivosheev rxq->refill_num -= i; 1984562e2f46SYelena Krivosheev rxq->first_to_refill = curr_desc; 1985562e2f46SYelena Krivosheev 1986562e2f46SYelena Krivosheev return i; 1987562e2f46SYelena Krivosheev } 1988562e2f46SYelena Krivosheev 19898dc9a088SLorenzo Bianconi static int 1990b0a43db9SLorenzo Bianconi mvneta_xdp_submit_frame(struct mvneta_port *pp, struct mvneta_tx_queue *txq, 1991b0a43db9SLorenzo Bianconi struct xdp_frame *xdpf, bool dma_map) 1992b0a43db9SLorenzo Bianconi { 199369de66fcSLorenzo Bianconi struct mvneta_pcpu_stats *stats = this_cpu_ptr(pp->stats); 1994b0a43db9SLorenzo Bianconi struct mvneta_tx_desc *tx_desc; 1995b0a43db9SLorenzo Bianconi struct mvneta_tx_buf *buf; 1996b0a43db9SLorenzo Bianconi dma_addr_t dma_addr; 1997b0a43db9SLorenzo Bianconi 1998b0a43db9SLorenzo Bianconi if (txq->count >= txq->tx_stop_threshold) 1999b0a43db9SLorenzo Bianconi return MVNETA_XDP_DROPPED; 2000b0a43db9SLorenzo Bianconi 2001b0a43db9SLorenzo Bianconi tx_desc = mvneta_txq_next_desc_get(txq); 2002b0a43db9SLorenzo Bianconi 2003b0a43db9SLorenzo Bianconi buf = &txq->buf[txq->txq_put_index]; 2004b0a43db9SLorenzo Bianconi if (dma_map) { 2005b0a43db9SLorenzo Bianconi /* ndo_xdp_xmit */ 2006b0a43db9SLorenzo Bianconi dma_addr = dma_map_single(pp->dev->dev.parent, xdpf->data, 2007b0a43db9SLorenzo Bianconi xdpf->len, DMA_TO_DEVICE); 2008b0a43db9SLorenzo Bianconi if (dma_mapping_error(pp->dev->dev.parent, dma_addr)) { 2009b0a43db9SLorenzo Bianconi mvneta_txq_desc_put(txq); 2010b0a43db9SLorenzo Bianconi return MVNETA_XDP_DROPPED; 2011b0a43db9SLorenzo Bianconi } 2012b0a43db9SLorenzo Bianconi buf->type = MVNETA_TYPE_XDP_NDO; 2013b0a43db9SLorenzo Bianconi } else { 2014b0a43db9SLorenzo Bianconi struct page *page = virt_to_page(xdpf->data); 2015b0a43db9SLorenzo Bianconi 2016b0a43db9SLorenzo Bianconi dma_addr = page_pool_get_dma_addr(page) + 2017b0a43db9SLorenzo Bianconi sizeof(*xdpf) + xdpf->headroom; 2018b0a43db9SLorenzo Bianconi dma_sync_single_for_device(pp->dev->dev.parent, dma_addr, 2019b0a43db9SLorenzo Bianconi xdpf->len, DMA_BIDIRECTIONAL); 2020b0a43db9SLorenzo Bianconi buf->type = MVNETA_TYPE_XDP_TX; 2021b0a43db9SLorenzo Bianconi } 2022b0a43db9SLorenzo Bianconi buf->xdpf = xdpf; 2023b0a43db9SLorenzo Bianconi 2024b0a43db9SLorenzo Bianconi tx_desc->command = MVNETA_TXD_FLZ_DESC; 2025b0a43db9SLorenzo Bianconi tx_desc->buf_phys_addr = dma_addr; 2026b0a43db9SLorenzo Bianconi tx_desc->data_size = xdpf->len; 2027b0a43db9SLorenzo Bianconi 202869de66fcSLorenzo Bianconi u64_stats_update_begin(&stats->syncp); 202969de66fcSLorenzo Bianconi stats->tx_bytes += xdpf->len; 203069de66fcSLorenzo Bianconi stats->tx_packets++; 203169de66fcSLorenzo Bianconi u64_stats_update_end(&stats->syncp); 203269de66fcSLorenzo Bianconi 2033b0a43db9SLorenzo Bianconi mvneta_txq_inc_put(txq); 2034b0a43db9SLorenzo Bianconi txq->pending++; 2035b0a43db9SLorenzo Bianconi txq->count++; 2036b0a43db9SLorenzo Bianconi 2037b0a43db9SLorenzo Bianconi return MVNETA_XDP_TX; 2038b0a43db9SLorenzo Bianconi } 2039b0a43db9SLorenzo Bianconi 2040b0a43db9SLorenzo Bianconi static int 2041b0a43db9SLorenzo Bianconi mvneta_xdp_xmit_back(struct mvneta_port *pp, struct xdp_buff *xdp) 2042b0a43db9SLorenzo Bianconi { 2043b0a43db9SLorenzo Bianconi struct mvneta_tx_queue *txq; 2044b0a43db9SLorenzo Bianconi struct netdev_queue *nq; 2045b0a43db9SLorenzo Bianconi struct xdp_frame *xdpf; 2046b0a43db9SLorenzo Bianconi int cpu; 2047b0a43db9SLorenzo Bianconi u32 ret; 2048b0a43db9SLorenzo Bianconi 2049b0a43db9SLorenzo Bianconi xdpf = convert_to_xdp_frame(xdp); 2050b0a43db9SLorenzo Bianconi if (unlikely(!xdpf)) 2051b0a43db9SLorenzo Bianconi return MVNETA_XDP_DROPPED; 2052b0a43db9SLorenzo Bianconi 2053b0a43db9SLorenzo Bianconi cpu = smp_processor_id(); 2054b0a43db9SLorenzo Bianconi txq = &pp->txqs[cpu % txq_number]; 2055b0a43db9SLorenzo Bianconi nq = netdev_get_tx_queue(pp->dev, txq->id); 2056b0a43db9SLorenzo Bianconi 2057b0a43db9SLorenzo Bianconi __netif_tx_lock(nq, cpu); 2058b0a43db9SLorenzo Bianconi ret = mvneta_xdp_submit_frame(pp, txq, xdpf, false); 2059b0a43db9SLorenzo Bianconi if (ret == MVNETA_XDP_TX) 2060b0a43db9SLorenzo Bianconi mvneta_txq_pend_desc_add(pp, txq, 0); 2061b0a43db9SLorenzo Bianconi __netif_tx_unlock(nq); 2062b0a43db9SLorenzo Bianconi 2063b0a43db9SLorenzo Bianconi return ret; 2064b0a43db9SLorenzo Bianconi } 2065b0a43db9SLorenzo Bianconi 2066b0a43db9SLorenzo Bianconi static int 2067b0a43db9SLorenzo Bianconi mvneta_xdp_xmit(struct net_device *dev, int num_frame, 2068b0a43db9SLorenzo Bianconi struct xdp_frame **frames, u32 flags) 2069b0a43db9SLorenzo Bianconi { 2070b0a43db9SLorenzo Bianconi struct mvneta_port *pp = netdev_priv(dev); 2071b0a43db9SLorenzo Bianconi int cpu = smp_processor_id(); 2072b0a43db9SLorenzo Bianconi struct mvneta_tx_queue *txq; 2073b0a43db9SLorenzo Bianconi struct netdev_queue *nq; 2074b0a43db9SLorenzo Bianconi int i, drops = 0; 2075b0a43db9SLorenzo Bianconi u32 ret; 2076b0a43db9SLorenzo Bianconi 2077b0a43db9SLorenzo Bianconi if (unlikely(flags & ~XDP_XMIT_FLAGS_MASK)) 2078b0a43db9SLorenzo Bianconi return -EINVAL; 2079b0a43db9SLorenzo Bianconi 2080b0a43db9SLorenzo Bianconi txq = &pp->txqs[cpu % txq_number]; 2081b0a43db9SLorenzo Bianconi nq = netdev_get_tx_queue(pp->dev, txq->id); 2082b0a43db9SLorenzo Bianconi 2083b0a43db9SLorenzo Bianconi __netif_tx_lock(nq, cpu); 2084b0a43db9SLorenzo Bianconi for (i = 0; i < num_frame; i++) { 2085b0a43db9SLorenzo Bianconi ret = mvneta_xdp_submit_frame(pp, txq, frames[i], true); 2086b0a43db9SLorenzo Bianconi if (ret != MVNETA_XDP_TX) { 2087b0a43db9SLorenzo Bianconi xdp_return_frame_rx_napi(frames[i]); 2088b0a43db9SLorenzo Bianconi drops++; 2089b0a43db9SLorenzo Bianconi } 2090b0a43db9SLorenzo Bianconi } 2091b0a43db9SLorenzo Bianconi 2092b0a43db9SLorenzo Bianconi if (unlikely(flags & XDP_XMIT_FLUSH)) 2093b0a43db9SLorenzo Bianconi mvneta_txq_pend_desc_add(pp, txq, 0); 2094b0a43db9SLorenzo Bianconi __netif_tx_unlock(nq); 2095b0a43db9SLorenzo Bianconi 2096b0a43db9SLorenzo Bianconi return num_frame - drops; 2097b0a43db9SLorenzo Bianconi } 2098b0a43db9SLorenzo Bianconi 2099b0a43db9SLorenzo Bianconi static int 21000db51da7SLorenzo Bianconi mvneta_run_xdp(struct mvneta_port *pp, struct mvneta_rx_queue *rxq, 21010db51da7SLorenzo Bianconi struct bpf_prog *prog, struct xdp_buff *xdp) 21020db51da7SLorenzo Bianconi { 21038c4df83fSLorenzo Bianconi unsigned int len; 21048c4df83fSLorenzo Bianconi u32 ret, act; 21058c4df83fSLorenzo Bianconi 21068c4df83fSLorenzo Bianconi len = xdp->data_end - xdp->data_hard_start - pp->rx_offset_correction; 21078c4df83fSLorenzo Bianconi act = bpf_prog_run_xdp(prog, xdp); 21080db51da7SLorenzo Bianconi 21090db51da7SLorenzo Bianconi switch (act) { 21100db51da7SLorenzo Bianconi case XDP_PASS: 21110db51da7SLorenzo Bianconi ret = MVNETA_XDP_PASS; 21120db51da7SLorenzo Bianconi break; 21130db51da7SLorenzo Bianconi case XDP_REDIRECT: { 21140db51da7SLorenzo Bianconi int err; 21150db51da7SLorenzo Bianconi 21160db51da7SLorenzo Bianconi err = xdp_do_redirect(pp->dev, xdp, prog); 21170db51da7SLorenzo Bianconi if (err) { 21180db51da7SLorenzo Bianconi ret = MVNETA_XDP_DROPPED; 211907e13edbSLorenzo Bianconi __page_pool_put_page(rxq->page_pool, 212007e13edbSLorenzo Bianconi virt_to_head_page(xdp->data), 21218c4df83fSLorenzo Bianconi len, true); 21220db51da7SLorenzo Bianconi } else { 21230db51da7SLorenzo Bianconi ret = MVNETA_XDP_REDIR; 21240db51da7SLorenzo Bianconi } 21250db51da7SLorenzo Bianconi break; 21260db51da7SLorenzo Bianconi } 2127b0a43db9SLorenzo Bianconi case XDP_TX: 2128b0a43db9SLorenzo Bianconi ret = mvneta_xdp_xmit_back(pp, xdp); 2129b0a43db9SLorenzo Bianconi if (ret != MVNETA_XDP_TX) 213007e13edbSLorenzo Bianconi __page_pool_put_page(rxq->page_pool, 213107e13edbSLorenzo Bianconi virt_to_head_page(xdp->data), 21328c4df83fSLorenzo Bianconi len, true); 2133b0a43db9SLorenzo Bianconi break; 21340db51da7SLorenzo Bianconi default: 21350db51da7SLorenzo Bianconi bpf_warn_invalid_xdp_action(act); 21360db51da7SLorenzo Bianconi /* fall through */ 21370db51da7SLorenzo Bianconi case XDP_ABORTED: 21380db51da7SLorenzo Bianconi trace_xdp_exception(pp->dev, prog, act); 21390db51da7SLorenzo Bianconi /* fall through */ 21400db51da7SLorenzo Bianconi case XDP_DROP: 214107e13edbSLorenzo Bianconi __page_pool_put_page(rxq->page_pool, 214207e13edbSLorenzo Bianconi virt_to_head_page(xdp->data), 21438c4df83fSLorenzo Bianconi len, true); 21440db51da7SLorenzo Bianconi ret = MVNETA_XDP_DROPPED; 21450db51da7SLorenzo Bianconi break; 21460db51da7SLorenzo Bianconi } 21470db51da7SLorenzo Bianconi 21480db51da7SLorenzo Bianconi return ret; 21490db51da7SLorenzo Bianconi } 21500db51da7SLorenzo Bianconi 21510db51da7SLorenzo Bianconi static int 21528dc9a088SLorenzo Bianconi mvneta_swbm_rx_frame(struct mvneta_port *pp, 21538dc9a088SLorenzo Bianconi struct mvneta_rx_desc *rx_desc, 21548dc9a088SLorenzo Bianconi struct mvneta_rx_queue *rxq, 21550db51da7SLorenzo Bianconi struct xdp_buff *xdp, 21560db51da7SLorenzo Bianconi struct bpf_prog *xdp_prog, 21570db51da7SLorenzo Bianconi struct page *page, u32 *xdp_ret) 21588dc9a088SLorenzo Bianconi { 21598dc9a088SLorenzo Bianconi unsigned char *data = page_address(page); 21608dc9a088SLorenzo Bianconi int data_len = -MVNETA_MH_SIZE, len; 21618dc9a088SLorenzo Bianconi struct net_device *dev = pp->dev; 21628dc9a088SLorenzo Bianconi enum dma_data_direction dma_dir; 21638dc9a088SLorenzo Bianconi 21648dc9a088SLorenzo Bianconi if (MVNETA_SKB_SIZE(rx_desc->data_size) > PAGE_SIZE) { 21658dc9a088SLorenzo Bianconi len = MVNETA_MAX_RX_BUF_SIZE; 21668dc9a088SLorenzo Bianconi data_len += len; 21678dc9a088SLorenzo Bianconi } else { 21688dc9a088SLorenzo Bianconi len = rx_desc->data_size; 21698dc9a088SLorenzo Bianconi data_len += len - ETH_FCS_LEN; 21708dc9a088SLorenzo Bianconi } 21718dc9a088SLorenzo Bianconi 21728dc9a088SLorenzo Bianconi dma_dir = page_pool_get_dma_dir(rxq->page_pool); 21738dc9a088SLorenzo Bianconi dma_sync_single_for_cpu(dev->dev.parent, 21748dc9a088SLorenzo Bianconi rx_desc->buf_phys_addr, 21758dc9a088SLorenzo Bianconi len, dma_dir); 21768dc9a088SLorenzo Bianconi 2177fa383f6bSLorenzo Bianconi /* Prefetch header */ 2178fa383f6bSLorenzo Bianconi prefetch(data); 2179fa383f6bSLorenzo Bianconi 21800db51da7SLorenzo Bianconi xdp->data_hard_start = data; 2181b37fa92eSLorenzo Bianconi xdp->data = data + pp->rx_offset_correction + MVNETA_MH_SIZE; 21820db51da7SLorenzo Bianconi xdp->data_end = xdp->data + data_len; 21830db51da7SLorenzo Bianconi xdp_set_data_meta_invalid(xdp); 21840db51da7SLorenzo Bianconi 21850db51da7SLorenzo Bianconi if (xdp_prog) { 21860db51da7SLorenzo Bianconi u32 ret; 21870db51da7SLorenzo Bianconi 21880db51da7SLorenzo Bianconi ret = mvneta_run_xdp(pp, rxq, xdp_prog, xdp); 21890db51da7SLorenzo Bianconi if (ret != MVNETA_XDP_PASS) { 21900db51da7SLorenzo Bianconi mvneta_update_stats(pp, 1, 219169de66fcSLorenzo Bianconi xdp->data_end - xdp->data); 21920db51da7SLorenzo Bianconi rx_desc->buf_phys_addr = 0; 21930db51da7SLorenzo Bianconi *xdp_ret |= ret; 21940db51da7SLorenzo Bianconi return ret; 21950db51da7SLorenzo Bianconi } 21960db51da7SLorenzo Bianconi } 21970db51da7SLorenzo Bianconi 21980db51da7SLorenzo Bianconi rxq->skb = build_skb(xdp->data_hard_start, PAGE_SIZE); 21998dc9a088SLorenzo Bianconi if (unlikely(!rxq->skb)) { 2200c35947b8SLorenzo Bianconi struct mvneta_pcpu_stats *stats = this_cpu_ptr(pp->stats); 2201c35947b8SLorenzo Bianconi 2202c35947b8SLorenzo Bianconi netdev_err(dev, "Can't allocate skb on queue %d\n", rxq->id); 2203c35947b8SLorenzo Bianconi 2204c35947b8SLorenzo Bianconi u64_stats_update_begin(&stats->syncp); 22059ac41f3cSLorenzo Bianconi stats->es.skb_alloc_error++; 2206c35947b8SLorenzo Bianconi stats->rx_dropped++; 2207c35947b8SLorenzo Bianconi u64_stats_update_end(&stats->syncp); 2208c35947b8SLorenzo Bianconi 22098dc9a088SLorenzo Bianconi return -ENOMEM; 22108dc9a088SLorenzo Bianconi } 22118dc9a088SLorenzo Bianconi page_pool_release_page(rxq->page_pool, page); 22128dc9a088SLorenzo Bianconi 22130db51da7SLorenzo Bianconi skb_reserve(rxq->skb, 22140db51da7SLorenzo Bianconi xdp->data - xdp->data_hard_start); 22150db51da7SLorenzo Bianconi skb_put(rxq->skb, xdp->data_end - xdp->data); 22168dc9a088SLorenzo Bianconi mvneta_rx_csum(pp, rx_desc->status, rxq->skb); 22178dc9a088SLorenzo Bianconi 22188dc9a088SLorenzo Bianconi rxq->left_size = rx_desc->data_size - len; 22198dc9a088SLorenzo Bianconi rx_desc->buf_phys_addr = 0; 22208dc9a088SLorenzo Bianconi 22218dc9a088SLorenzo Bianconi return 0; 22228dc9a088SLorenzo Bianconi } 22238dc9a088SLorenzo Bianconi 22248dc9a088SLorenzo Bianconi static void 22258dc9a088SLorenzo Bianconi mvneta_swbm_add_rx_fragment(struct mvneta_port *pp, 22268dc9a088SLorenzo Bianconi struct mvneta_rx_desc *rx_desc, 22278dc9a088SLorenzo Bianconi struct mvneta_rx_queue *rxq, 22288dc9a088SLorenzo Bianconi struct page *page) 22298dc9a088SLorenzo Bianconi { 22308dc9a088SLorenzo Bianconi struct net_device *dev = pp->dev; 22318dc9a088SLorenzo Bianconi enum dma_data_direction dma_dir; 22328dc9a088SLorenzo Bianconi int data_len, len; 22338dc9a088SLorenzo Bianconi 22348dc9a088SLorenzo Bianconi if (rxq->left_size > MVNETA_MAX_RX_BUF_SIZE) { 22358dc9a088SLorenzo Bianconi len = MVNETA_MAX_RX_BUF_SIZE; 22368dc9a088SLorenzo Bianconi data_len = len; 22378dc9a088SLorenzo Bianconi } else { 22388dc9a088SLorenzo Bianconi len = rxq->left_size; 22398dc9a088SLorenzo Bianconi data_len = len - ETH_FCS_LEN; 22408dc9a088SLorenzo Bianconi } 22418dc9a088SLorenzo Bianconi dma_dir = page_pool_get_dma_dir(rxq->page_pool); 22428dc9a088SLorenzo Bianconi dma_sync_single_for_cpu(dev->dev.parent, 22438dc9a088SLorenzo Bianconi rx_desc->buf_phys_addr, 22448dc9a088SLorenzo Bianconi len, dma_dir); 22458dc9a088SLorenzo Bianconi if (data_len > 0) { 22468dc9a088SLorenzo Bianconi /* refill descriptor with new buffer later */ 22478dc9a088SLorenzo Bianconi skb_add_rx_frag(rxq->skb, 22488dc9a088SLorenzo Bianconi skb_shinfo(rxq->skb)->nr_frags, 2249b37fa92eSLorenzo Bianconi page, pp->rx_offset_correction, data_len, 22508dc9a088SLorenzo Bianconi PAGE_SIZE); 22518dc9a088SLorenzo Bianconi } 22528dc9a088SLorenzo Bianconi page_pool_release_page(rxq->page_pool, page); 22538dc9a088SLorenzo Bianconi rx_desc->buf_phys_addr = 0; 22548dc9a088SLorenzo Bianconi rxq->left_size -= len; 22558dc9a088SLorenzo Bianconi } 22568dc9a088SLorenzo Bianconi 2257dc35a10fSMarcin Wojtas /* Main rx processing when using software buffer management */ 22587a86f05fSAndrew Lunn static int mvneta_rx_swbm(struct napi_struct *napi, 2259562e2f46SYelena Krivosheev struct mvneta_port *pp, int budget, 2260c5aff182SThomas Petazzoni struct mvneta_rx_queue *rxq) 2261c5aff182SThomas Petazzoni { 22628dc9a088SLorenzo Bianconi int rcvd_pkts = 0, rcvd_bytes = 0, rx_proc = 0; 2263c5aff182SThomas Petazzoni struct net_device *dev = pp->dev; 22640db51da7SLorenzo Bianconi struct bpf_prog *xdp_prog; 22650db51da7SLorenzo Bianconi struct xdp_buff xdp_buf; 22668dc9a088SLorenzo Bianconi int rx_todo, refill; 22670db51da7SLorenzo Bianconi u32 xdp_ret = 0; 2268c5aff182SThomas Petazzoni 2269c5aff182SThomas Petazzoni /* Get number of received packets */ 2270562e2f46SYelena Krivosheev rx_todo = mvneta_rxq_busy_desc_num_get(pp, rxq); 2271c5aff182SThomas Petazzoni 22720db51da7SLorenzo Bianconi rcu_read_lock(); 22730db51da7SLorenzo Bianconi xdp_prog = READ_ONCE(pp->xdp_prog); 22740db51da7SLorenzo Bianconi xdp_buf.rxq = &rxq->xdp_rxq; 22750db51da7SLorenzo Bianconi 2276c5aff182SThomas Petazzoni /* Fairness NAPI loop */ 22778dc9a088SLorenzo Bianconi while (rx_proc < budget && rx_proc < rx_todo) { 2278c5aff182SThomas Petazzoni struct mvneta_rx_desc *rx_desc = mvneta_rxq_next_desc_get(rxq); 22798dc9a088SLorenzo Bianconi u32 rx_status, index; 22807e47fd84SGregory CLEMENT struct page *page; 2281c5aff182SThomas Petazzoni 2282f88bee1cSGregory CLEMENT index = rx_desc - rxq->descs; 22837e47fd84SGregory CLEMENT page = (struct page *)rxq->buf_virt_addr[index]; 2284c5aff182SThomas Petazzoni 2285562e2f46SYelena Krivosheev rx_status = rx_desc->status; 2286562e2f46SYelena Krivosheev rx_proc++; 2287562e2f46SYelena Krivosheev rxq->refill_num++; 2288562e2f46SYelena Krivosheev 2289562e2f46SYelena Krivosheev if (rx_status & MVNETA_RXD_FIRST_DESC) { 22908dc9a088SLorenzo Bianconi int err; 22918dc9a088SLorenzo Bianconi 2292562e2f46SYelena Krivosheev /* Check errors only for FIRST descriptor */ 2293562e2f46SYelena Krivosheev if (rx_status & MVNETA_RXD_ERR_SUMMARY) { 22942eecb2e0SYelena Krivosheev mvneta_rx_error(pp, rx_desc); 22958ec2cd48Swilly tarreau /* leave the descriptor untouched */ 2296c5aff182SThomas Petazzoni continue; 2297c5aff182SThomas Petazzoni } 2298c5aff182SThomas Petazzoni 22990db51da7SLorenzo Bianconi err = mvneta_swbm_rx_frame(pp, rx_desc, rxq, &xdp_buf, 23000db51da7SLorenzo Bianconi xdp_prog, page, &xdp_ret); 23018dc9a088SLorenzo Bianconi if (err) 2302f19fadfcSwilly tarreau continue; 2303562e2f46SYelena Krivosheev } else { 2304562e2f46SYelena Krivosheev if (unlikely(!rxq->skb)) { 2305562e2f46SYelena Krivosheev pr_debug("no skb for rx_status 0x%x\n", 2306562e2f46SYelena Krivosheev rx_status); 2307562e2f46SYelena Krivosheev continue; 2308562e2f46SYelena Krivosheev } 23098dc9a088SLorenzo Bianconi mvneta_swbm_add_rx_fragment(pp, rx_desc, rxq, page); 2310562e2f46SYelena Krivosheev } /* Middle or Last descriptor */ 2311562e2f46SYelena Krivosheev 2312562e2f46SYelena Krivosheev if (!(rx_status & MVNETA_RXD_LAST_DESC)) 2313562e2f46SYelena Krivosheev /* no last descriptor this time */ 2314562e2f46SYelena Krivosheev continue; 2315562e2f46SYelena Krivosheev 2316562e2f46SYelena Krivosheev if (rxq->left_size) { 2317562e2f46SYelena Krivosheev pr_err("get last desc, but left_size (%d) != 0\n", 2318562e2f46SYelena Krivosheev rxq->left_size); 2319562e2f46SYelena Krivosheev dev_kfree_skb_any(rxq->skb); 2320562e2f46SYelena Krivosheev rxq->left_size = 0; 2321562e2f46SYelena Krivosheev rxq->skb = NULL; 2322562e2f46SYelena Krivosheev continue; 2323562e2f46SYelena Krivosheev } 2324dc4277ddSwilly tarreau rcvd_pkts++; 2325562e2f46SYelena Krivosheev rcvd_bytes += rxq->skb->len; 2326c5aff182SThomas Petazzoni 2327c5aff182SThomas Petazzoni /* Linux processing */ 2328562e2f46SYelena Krivosheev rxq->skb->protocol = eth_type_trans(rxq->skb, dev); 2329c5aff182SThomas Petazzoni 2330562e2f46SYelena Krivosheev napi_gro_receive(napi, rxq->skb); 2331c5aff182SThomas Petazzoni 2332562e2f46SYelena Krivosheev /* clean uncomplete skb pointer in queue */ 2333562e2f46SYelena Krivosheev rxq->skb = NULL; 2334c5aff182SThomas Petazzoni } 23350db51da7SLorenzo Bianconi rcu_read_unlock(); 23360db51da7SLorenzo Bianconi 23370db51da7SLorenzo Bianconi if (xdp_ret & MVNETA_XDP_REDIR) 23380db51da7SLorenzo Bianconi xdp_do_flush_map(); 2339c5aff182SThomas Petazzoni 2340ff519e2aSLorenzo Bianconi if (rcvd_pkts) 234169de66fcSLorenzo Bianconi mvneta_update_stats(pp, rcvd_pkts, rcvd_bytes); 2342dc4277ddSwilly tarreau 2343562e2f46SYelena Krivosheev /* return some buffers to hardware queue, one at a time is too slow */ 2344562e2f46SYelena Krivosheev refill = mvneta_rx_refill_queue(pp, rxq); 2345c5aff182SThomas Petazzoni 2346562e2f46SYelena Krivosheev /* Update rxq management counters */ 2347562e2f46SYelena Krivosheev mvneta_rxq_desc_num_update(pp, rxq, rx_proc, refill); 2348562e2f46SYelena Krivosheev 2349562e2f46SYelena Krivosheev return rcvd_pkts; 2350c5aff182SThomas Petazzoni } 2351c5aff182SThomas Petazzoni 2352dc35a10fSMarcin Wojtas /* Main rx processing when using hardware buffer management */ 23537a86f05fSAndrew Lunn static int mvneta_rx_hwbm(struct napi_struct *napi, 23547a86f05fSAndrew Lunn struct mvneta_port *pp, int rx_todo, 2355dc35a10fSMarcin Wojtas struct mvneta_rx_queue *rxq) 2356dc35a10fSMarcin Wojtas { 2357dc35a10fSMarcin Wojtas struct net_device *dev = pp->dev; 2358dc35a10fSMarcin Wojtas int rx_done; 2359dc35a10fSMarcin Wojtas u32 rcvd_pkts = 0; 2360dc35a10fSMarcin Wojtas u32 rcvd_bytes = 0; 2361dc35a10fSMarcin Wojtas 2362dc35a10fSMarcin Wojtas /* Get number of received packets */ 2363dc35a10fSMarcin Wojtas rx_done = mvneta_rxq_busy_desc_num_get(pp, rxq); 2364dc35a10fSMarcin Wojtas 2365dc35a10fSMarcin Wojtas if (rx_todo > rx_done) 2366dc35a10fSMarcin Wojtas rx_todo = rx_done; 2367dc35a10fSMarcin Wojtas 2368dc35a10fSMarcin Wojtas rx_done = 0; 2369dc35a10fSMarcin Wojtas 2370dc35a10fSMarcin Wojtas /* Fairness NAPI loop */ 2371dc35a10fSMarcin Wojtas while (rx_done < rx_todo) { 2372dc35a10fSMarcin Wojtas struct mvneta_rx_desc *rx_desc = mvneta_rxq_next_desc_get(rxq); 2373dc35a10fSMarcin Wojtas struct mvneta_bm_pool *bm_pool = NULL; 2374dc35a10fSMarcin Wojtas struct sk_buff *skb; 2375dc35a10fSMarcin Wojtas unsigned char *data; 2376dc35a10fSMarcin Wojtas dma_addr_t phys_addr; 2377dc35a10fSMarcin Wojtas u32 rx_status, frag_size; 2378dc35a10fSMarcin Wojtas int rx_bytes, err; 2379dc35a10fSMarcin Wojtas u8 pool_id; 2380dc35a10fSMarcin Wojtas 2381dc35a10fSMarcin Wojtas rx_done++; 2382dc35a10fSMarcin Wojtas rx_status = rx_desc->status; 2383dc35a10fSMarcin Wojtas rx_bytes = rx_desc->data_size - (ETH_FCS_LEN + MVNETA_MH_SIZE); 2384f88bee1cSGregory CLEMENT data = (u8 *)(uintptr_t)rx_desc->buf_cookie; 2385dc35a10fSMarcin Wojtas phys_addr = rx_desc->buf_phys_addr; 2386dc35a10fSMarcin Wojtas pool_id = MVNETA_RX_GET_BM_POOL_ID(rx_desc); 2387dc35a10fSMarcin Wojtas bm_pool = &pp->bm_priv->bm_pools[pool_id]; 2388dc35a10fSMarcin Wojtas 2389dc35a10fSMarcin Wojtas if (!mvneta_rxq_desc_is_first_last(rx_status) || 2390dc35a10fSMarcin Wojtas (rx_status & MVNETA_RXD_ERR_SUMMARY)) { 2391dc35a10fSMarcin Wojtas err_drop_frame_ret_pool: 2392dc35a10fSMarcin Wojtas /* Return the buffer to the pool */ 2393dc35a10fSMarcin Wojtas mvneta_bm_pool_put_bp(pp->bm_priv, bm_pool, 2394dc35a10fSMarcin Wojtas rx_desc->buf_phys_addr); 2395dc35a10fSMarcin Wojtas err_drop_frame: 2396dc35a10fSMarcin Wojtas mvneta_rx_error(pp, rx_desc); 2397dc35a10fSMarcin Wojtas /* leave the descriptor untouched */ 2398dc35a10fSMarcin Wojtas continue; 2399dc35a10fSMarcin Wojtas } 2400dc35a10fSMarcin Wojtas 2401dc35a10fSMarcin Wojtas if (rx_bytes <= rx_copybreak) { 2402dc35a10fSMarcin Wojtas /* better copy a small frame and not unmap the DMA region */ 2403dc35a10fSMarcin Wojtas skb = netdev_alloc_skb_ip_align(dev, rx_bytes); 2404dc35a10fSMarcin Wojtas if (unlikely(!skb)) 2405dc35a10fSMarcin Wojtas goto err_drop_frame_ret_pool; 2406dc35a10fSMarcin Wojtas 2407a8fef9baSRussell King dma_sync_single_range_for_cpu(&pp->bm_priv->pdev->dev, 2408dc35a10fSMarcin Wojtas rx_desc->buf_phys_addr, 2409dc35a10fSMarcin Wojtas MVNETA_MH_SIZE + NET_SKB_PAD, 2410dc35a10fSMarcin Wojtas rx_bytes, 2411dc35a10fSMarcin Wojtas DMA_FROM_DEVICE); 241259ae1d12SJohannes Berg skb_put_data(skb, data + MVNETA_MH_SIZE + NET_SKB_PAD, 2413dc35a10fSMarcin Wojtas rx_bytes); 2414dc35a10fSMarcin Wojtas 2415dc35a10fSMarcin Wojtas skb->protocol = eth_type_trans(skb, dev); 2416dc35a10fSMarcin Wojtas mvneta_rx_csum(pp, rx_status, skb); 24177a86f05fSAndrew Lunn napi_gro_receive(napi, skb); 2418dc35a10fSMarcin Wojtas 2419dc35a10fSMarcin Wojtas rcvd_pkts++; 2420dc35a10fSMarcin Wojtas rcvd_bytes += rx_bytes; 2421dc35a10fSMarcin Wojtas 2422dc35a10fSMarcin Wojtas /* Return the buffer to the pool */ 2423dc35a10fSMarcin Wojtas mvneta_bm_pool_put_bp(pp->bm_priv, bm_pool, 2424dc35a10fSMarcin Wojtas rx_desc->buf_phys_addr); 2425dc35a10fSMarcin Wojtas 2426dc35a10fSMarcin Wojtas /* leave the descriptor and buffer untouched */ 2427dc35a10fSMarcin Wojtas continue; 2428dc35a10fSMarcin Wojtas } 2429dc35a10fSMarcin Wojtas 2430dc35a10fSMarcin Wojtas /* Refill processing */ 2431baa11ebcSGregory CLEMENT err = hwbm_pool_refill(&bm_pool->hwbm_pool, GFP_ATOMIC); 2432dc35a10fSMarcin Wojtas if (err) { 24339ac41f3cSLorenzo Bianconi struct mvneta_pcpu_stats *stats; 24349ac41f3cSLorenzo Bianconi 2435dc35a10fSMarcin Wojtas netdev_err(dev, "Linux processing - Can't refill\n"); 24369ac41f3cSLorenzo Bianconi 24379ac41f3cSLorenzo Bianconi stats = this_cpu_ptr(pp->stats); 24389ac41f3cSLorenzo Bianconi u64_stats_update_begin(&stats->syncp); 24399ac41f3cSLorenzo Bianconi stats->es.refill_error++; 24409ac41f3cSLorenzo Bianconi u64_stats_update_end(&stats->syncp); 24419ac41f3cSLorenzo Bianconi 2442dc35a10fSMarcin Wojtas goto err_drop_frame_ret_pool; 2443dc35a10fSMarcin Wojtas } 2444dc35a10fSMarcin Wojtas 2445baa11ebcSGregory CLEMENT frag_size = bm_pool->hwbm_pool.frag_size; 2446dc35a10fSMarcin Wojtas 2447dc35a10fSMarcin Wojtas skb = build_skb(data, frag_size > PAGE_SIZE ? 0 : frag_size); 2448dc35a10fSMarcin Wojtas 2449dc35a10fSMarcin Wojtas /* After refill old buffer has to be unmapped regardless 2450dc35a10fSMarcin Wojtas * the skb is successfully built or not. 2451dc35a10fSMarcin Wojtas */ 2452dc35a10fSMarcin Wojtas dma_unmap_single(&pp->bm_priv->pdev->dev, phys_addr, 2453dc35a10fSMarcin Wojtas bm_pool->buf_size, DMA_FROM_DEVICE); 2454dc35a10fSMarcin Wojtas if (!skb) 2455dc35a10fSMarcin Wojtas goto err_drop_frame; 2456dc35a10fSMarcin Wojtas 2457dc35a10fSMarcin Wojtas rcvd_pkts++; 2458dc35a10fSMarcin Wojtas rcvd_bytes += rx_bytes; 2459dc35a10fSMarcin Wojtas 2460dc35a10fSMarcin Wojtas /* Linux processing */ 2461dc35a10fSMarcin Wojtas skb_reserve(skb, MVNETA_MH_SIZE + NET_SKB_PAD); 2462dc35a10fSMarcin Wojtas skb_put(skb, rx_bytes); 2463dc35a10fSMarcin Wojtas 2464dc35a10fSMarcin Wojtas skb->protocol = eth_type_trans(skb, dev); 2465dc35a10fSMarcin Wojtas 2466dc35a10fSMarcin Wojtas mvneta_rx_csum(pp, rx_status, skb); 2467dc35a10fSMarcin Wojtas 24687a86f05fSAndrew Lunn napi_gro_receive(napi, skb); 2469dc35a10fSMarcin Wojtas } 2470dc35a10fSMarcin Wojtas 247169de66fcSLorenzo Bianconi if (rcvd_pkts) { 247269de66fcSLorenzo Bianconi struct mvneta_pcpu_stats *stats = this_cpu_ptr(pp->stats); 247369de66fcSLorenzo Bianconi 247469de66fcSLorenzo Bianconi u64_stats_update_begin(&stats->syncp); 247569de66fcSLorenzo Bianconi stats->rx_packets += rcvd_pkts; 247669de66fcSLorenzo Bianconi stats->rx_bytes += rcvd_bytes; 247769de66fcSLorenzo Bianconi u64_stats_update_end(&stats->syncp); 247869de66fcSLorenzo Bianconi } 2479dc35a10fSMarcin Wojtas 2480dc35a10fSMarcin Wojtas /* Update rxq management counters */ 2481dc35a10fSMarcin Wojtas mvneta_rxq_desc_num_update(pp, rxq, rx_done, rx_done); 2482dc35a10fSMarcin Wojtas 2483dc35a10fSMarcin Wojtas return rx_done; 2484dc35a10fSMarcin Wojtas } 2485dc35a10fSMarcin Wojtas 24862adb719dSEzequiel Garcia static inline void 24872adb719dSEzequiel Garcia mvneta_tso_put_hdr(struct sk_buff *skb, 24882adb719dSEzequiel Garcia struct mvneta_port *pp, struct mvneta_tx_queue *txq) 24892adb719dSEzequiel Garcia { 24902adb719dSEzequiel Garcia int hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb); 24919e58c8b4SLorenzo Bianconi struct mvneta_tx_buf *buf = &txq->buf[txq->txq_put_index]; 24929e58c8b4SLorenzo Bianconi struct mvneta_tx_desc *tx_desc; 24932adb719dSEzequiel Garcia 24942adb719dSEzequiel Garcia tx_desc = mvneta_txq_next_desc_get(txq); 24952adb719dSEzequiel Garcia tx_desc->data_size = hdr_len; 24962adb719dSEzequiel Garcia tx_desc->command = mvneta_skb_tx_csum(pp, skb); 24972adb719dSEzequiel Garcia tx_desc->command |= MVNETA_TXD_F_DESC; 24982adb719dSEzequiel Garcia tx_desc->buf_phys_addr = txq->tso_hdrs_phys + 24992adb719dSEzequiel Garcia txq->txq_put_index * TSO_HEADER_SIZE; 25009e58c8b4SLorenzo Bianconi buf->type = MVNETA_TYPE_SKB; 25019e58c8b4SLorenzo Bianconi buf->skb = NULL; 25029e58c8b4SLorenzo Bianconi 25032adb719dSEzequiel Garcia mvneta_txq_inc_put(txq); 25042adb719dSEzequiel Garcia } 25052adb719dSEzequiel Garcia 25062adb719dSEzequiel Garcia static inline int 25072adb719dSEzequiel Garcia mvneta_tso_put_data(struct net_device *dev, struct mvneta_tx_queue *txq, 25082adb719dSEzequiel Garcia struct sk_buff *skb, char *data, int size, 25092adb719dSEzequiel Garcia bool last_tcp, bool is_last) 25102adb719dSEzequiel Garcia { 25119e58c8b4SLorenzo Bianconi struct mvneta_tx_buf *buf = &txq->buf[txq->txq_put_index]; 25122adb719dSEzequiel Garcia struct mvneta_tx_desc *tx_desc; 25132adb719dSEzequiel Garcia 25142adb719dSEzequiel Garcia tx_desc = mvneta_txq_next_desc_get(txq); 25152adb719dSEzequiel Garcia tx_desc->data_size = size; 25162adb719dSEzequiel Garcia tx_desc->buf_phys_addr = dma_map_single(dev->dev.parent, data, 25172adb719dSEzequiel Garcia size, DMA_TO_DEVICE); 25182adb719dSEzequiel Garcia if (unlikely(dma_mapping_error(dev->dev.parent, 25192adb719dSEzequiel Garcia tx_desc->buf_phys_addr))) { 25202adb719dSEzequiel Garcia mvneta_txq_desc_put(txq); 25212adb719dSEzequiel Garcia return -ENOMEM; 25222adb719dSEzequiel Garcia } 25232adb719dSEzequiel Garcia 25242adb719dSEzequiel Garcia tx_desc->command = 0; 25259e58c8b4SLorenzo Bianconi buf->type = MVNETA_TYPE_SKB; 25269e58c8b4SLorenzo Bianconi buf->skb = NULL; 25272adb719dSEzequiel Garcia 25282adb719dSEzequiel Garcia if (last_tcp) { 25292adb719dSEzequiel Garcia /* last descriptor in the TCP packet */ 25302adb719dSEzequiel Garcia tx_desc->command = MVNETA_TXD_L_DESC; 25312adb719dSEzequiel Garcia 25322adb719dSEzequiel Garcia /* last descriptor in SKB */ 25332adb719dSEzequiel Garcia if (is_last) 25349e58c8b4SLorenzo Bianconi buf->skb = skb; 25352adb719dSEzequiel Garcia } 25362adb719dSEzequiel Garcia mvneta_txq_inc_put(txq); 25372adb719dSEzequiel Garcia return 0; 25382adb719dSEzequiel Garcia } 25392adb719dSEzequiel Garcia 25402adb719dSEzequiel Garcia static int mvneta_tx_tso(struct sk_buff *skb, struct net_device *dev, 25412adb719dSEzequiel Garcia struct mvneta_tx_queue *txq) 25422adb719dSEzequiel Garcia { 25432adb719dSEzequiel Garcia int total_len, data_left; 25442adb719dSEzequiel Garcia int desc_count = 0; 25452adb719dSEzequiel Garcia struct mvneta_port *pp = netdev_priv(dev); 25462adb719dSEzequiel Garcia struct tso_t tso; 25472adb719dSEzequiel Garcia int hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb); 25482adb719dSEzequiel Garcia int i; 25492adb719dSEzequiel Garcia 25502adb719dSEzequiel Garcia /* Count needed descriptors */ 25512adb719dSEzequiel Garcia if ((txq->count + tso_count_descs(skb)) >= txq->size) 25522adb719dSEzequiel Garcia return 0; 25532adb719dSEzequiel Garcia 25542adb719dSEzequiel Garcia if (skb_headlen(skb) < (skb_transport_offset(skb) + tcp_hdrlen(skb))) { 25552adb719dSEzequiel Garcia pr_info("*** Is this even possible???!?!?\n"); 25562adb719dSEzequiel Garcia return 0; 25572adb719dSEzequiel Garcia } 25582adb719dSEzequiel Garcia 25592adb719dSEzequiel Garcia /* Initialize the TSO handler, and prepare the first payload */ 25602adb719dSEzequiel Garcia tso_start(skb, &tso); 25612adb719dSEzequiel Garcia 25622adb719dSEzequiel Garcia total_len = skb->len - hdr_len; 25632adb719dSEzequiel Garcia while (total_len > 0) { 25642adb719dSEzequiel Garcia char *hdr; 25652adb719dSEzequiel Garcia 25662adb719dSEzequiel Garcia data_left = min_t(int, skb_shinfo(skb)->gso_size, total_len); 25672adb719dSEzequiel Garcia total_len -= data_left; 25682adb719dSEzequiel Garcia desc_count++; 25692adb719dSEzequiel Garcia 25702adb719dSEzequiel Garcia /* prepare packet headers: MAC + IP + TCP */ 25712adb719dSEzequiel Garcia hdr = txq->tso_hdrs + txq->txq_put_index * TSO_HEADER_SIZE; 25722adb719dSEzequiel Garcia tso_build_hdr(skb, hdr, &tso, data_left, total_len == 0); 25732adb719dSEzequiel Garcia 25742adb719dSEzequiel Garcia mvneta_tso_put_hdr(skb, pp, txq); 25752adb719dSEzequiel Garcia 25762adb719dSEzequiel Garcia while (data_left > 0) { 25772adb719dSEzequiel Garcia int size; 25782adb719dSEzequiel Garcia desc_count++; 25792adb719dSEzequiel Garcia 25802adb719dSEzequiel Garcia size = min_t(int, tso.size, data_left); 25812adb719dSEzequiel Garcia 25822adb719dSEzequiel Garcia if (mvneta_tso_put_data(dev, txq, skb, 25832adb719dSEzequiel Garcia tso.data, size, 25842adb719dSEzequiel Garcia size == data_left, 25852adb719dSEzequiel Garcia total_len == 0)) 25862adb719dSEzequiel Garcia goto err_release; 25872adb719dSEzequiel Garcia data_left -= size; 25882adb719dSEzequiel Garcia 25892adb719dSEzequiel Garcia tso_build_data(skb, &tso, size); 25902adb719dSEzequiel Garcia } 25912adb719dSEzequiel Garcia } 25922adb719dSEzequiel Garcia 25932adb719dSEzequiel Garcia return desc_count; 25942adb719dSEzequiel Garcia 25952adb719dSEzequiel Garcia err_release: 25962adb719dSEzequiel Garcia /* Release all used data descriptors; header descriptors must not 25972adb719dSEzequiel Garcia * be DMA-unmapped. 25982adb719dSEzequiel Garcia */ 25992adb719dSEzequiel Garcia for (i = desc_count - 1; i >= 0; i--) { 26002adb719dSEzequiel Garcia struct mvneta_tx_desc *tx_desc = txq->descs + i; 26012e3173a3SEzequiel Garcia if (!IS_TSO_HEADER(txq, tx_desc->buf_phys_addr)) 26022adb719dSEzequiel Garcia dma_unmap_single(pp->dev->dev.parent, 26032adb719dSEzequiel Garcia tx_desc->buf_phys_addr, 26042adb719dSEzequiel Garcia tx_desc->data_size, 26052adb719dSEzequiel Garcia DMA_TO_DEVICE); 26062adb719dSEzequiel Garcia mvneta_txq_desc_put(txq); 26072adb719dSEzequiel Garcia } 26082adb719dSEzequiel Garcia return 0; 26092adb719dSEzequiel Garcia } 26102adb719dSEzequiel Garcia 2611c5aff182SThomas Petazzoni /* Handle tx fragmentation processing */ 2612c5aff182SThomas Petazzoni static int mvneta_tx_frag_process(struct mvneta_port *pp, struct sk_buff *skb, 2613c5aff182SThomas Petazzoni struct mvneta_tx_queue *txq) 2614c5aff182SThomas Petazzoni { 2615c5aff182SThomas Petazzoni struct mvneta_tx_desc *tx_desc; 26163d4ea02fSEzequiel Garcia int i, nr_frags = skb_shinfo(skb)->nr_frags; 2617c5aff182SThomas Petazzoni 26183d4ea02fSEzequiel Garcia for (i = 0; i < nr_frags; i++) { 26199e58c8b4SLorenzo Bianconi struct mvneta_tx_buf *buf = &txq->buf[txq->txq_put_index]; 2620c5aff182SThomas Petazzoni skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 2621d7840976SMatthew Wilcox (Oracle) void *addr = skb_frag_address(frag); 2622c5aff182SThomas Petazzoni 2623c5aff182SThomas Petazzoni tx_desc = mvneta_txq_next_desc_get(txq); 2624d7840976SMatthew Wilcox (Oracle) tx_desc->data_size = skb_frag_size(frag); 2625c5aff182SThomas Petazzoni 2626c5aff182SThomas Petazzoni tx_desc->buf_phys_addr = 2627c5aff182SThomas Petazzoni dma_map_single(pp->dev->dev.parent, addr, 2628c5aff182SThomas Petazzoni tx_desc->data_size, DMA_TO_DEVICE); 2629c5aff182SThomas Petazzoni 2630c5aff182SThomas Petazzoni if (dma_mapping_error(pp->dev->dev.parent, 2631c5aff182SThomas Petazzoni tx_desc->buf_phys_addr)) { 2632c5aff182SThomas Petazzoni mvneta_txq_desc_put(txq); 2633c5aff182SThomas Petazzoni goto error; 2634c5aff182SThomas Petazzoni } 2635c5aff182SThomas Petazzoni 26363d4ea02fSEzequiel Garcia if (i == nr_frags - 1) { 2637c5aff182SThomas Petazzoni /* Last descriptor */ 2638c5aff182SThomas Petazzoni tx_desc->command = MVNETA_TXD_L_DESC | MVNETA_TXD_Z_PAD; 26399e58c8b4SLorenzo Bianconi buf->skb = skb; 2640c5aff182SThomas Petazzoni } else { 2641c5aff182SThomas Petazzoni /* Descriptor in the middle: Not First, Not Last */ 2642c5aff182SThomas Petazzoni tx_desc->command = 0; 26439e58c8b4SLorenzo Bianconi buf->skb = NULL; 2644c5aff182SThomas Petazzoni } 26459e58c8b4SLorenzo Bianconi buf->type = MVNETA_TYPE_SKB; 26463d4ea02fSEzequiel Garcia mvneta_txq_inc_put(txq); 2647c5aff182SThomas Petazzoni } 2648c5aff182SThomas Petazzoni 2649c5aff182SThomas Petazzoni return 0; 2650c5aff182SThomas Petazzoni 2651c5aff182SThomas Petazzoni error: 2652c5aff182SThomas Petazzoni /* Release all descriptors that were used to map fragments of 26536a20c175SThomas Petazzoni * this packet, as well as the corresponding DMA mappings 26546a20c175SThomas Petazzoni */ 2655c5aff182SThomas Petazzoni for (i = i - 1; i >= 0; i--) { 2656c5aff182SThomas Petazzoni tx_desc = txq->descs + i; 2657c5aff182SThomas Petazzoni dma_unmap_single(pp->dev->dev.parent, 2658c5aff182SThomas Petazzoni tx_desc->buf_phys_addr, 2659c5aff182SThomas Petazzoni tx_desc->data_size, 2660c5aff182SThomas Petazzoni DMA_TO_DEVICE); 2661c5aff182SThomas Petazzoni mvneta_txq_desc_put(txq); 2662c5aff182SThomas Petazzoni } 2663c5aff182SThomas Petazzoni 2664c5aff182SThomas Petazzoni return -ENOMEM; 2665c5aff182SThomas Petazzoni } 2666c5aff182SThomas Petazzoni 2667c5aff182SThomas Petazzoni /* Main tx processing */ 2668f03508ceSYueHaibing static netdev_tx_t mvneta_tx(struct sk_buff *skb, struct net_device *dev) 2669c5aff182SThomas Petazzoni { 2670c5aff182SThomas Petazzoni struct mvneta_port *pp = netdev_priv(dev); 2671ee40a116SWilly Tarreau u16 txq_id = skb_get_queue_mapping(skb); 2672ee40a116SWilly Tarreau struct mvneta_tx_queue *txq = &pp->txqs[txq_id]; 26739e58c8b4SLorenzo Bianconi struct mvneta_tx_buf *buf = &txq->buf[txq->txq_put_index]; 2674c5aff182SThomas Petazzoni struct mvneta_tx_desc *tx_desc; 26755f478b41SEric Dumazet int len = skb->len; 2676c5aff182SThomas Petazzoni int frags = 0; 2677c5aff182SThomas Petazzoni u32 tx_cmd; 2678c5aff182SThomas Petazzoni 2679c5aff182SThomas Petazzoni if (!netif_running(dev)) 2680c5aff182SThomas Petazzoni goto out; 2681c5aff182SThomas Petazzoni 26822adb719dSEzequiel Garcia if (skb_is_gso(skb)) { 26832adb719dSEzequiel Garcia frags = mvneta_tx_tso(skb, dev, txq); 26842adb719dSEzequiel Garcia goto out; 26852adb719dSEzequiel Garcia } 26862adb719dSEzequiel Garcia 2687c5aff182SThomas Petazzoni frags = skb_shinfo(skb)->nr_frags + 1; 2688c5aff182SThomas Petazzoni 2689c5aff182SThomas Petazzoni /* Get a descriptor for the first part of the packet */ 2690c5aff182SThomas Petazzoni tx_desc = mvneta_txq_next_desc_get(txq); 2691c5aff182SThomas Petazzoni 2692c5aff182SThomas Petazzoni tx_cmd = mvneta_skb_tx_csum(pp, skb); 2693c5aff182SThomas Petazzoni 2694c5aff182SThomas Petazzoni tx_desc->data_size = skb_headlen(skb); 2695c5aff182SThomas Petazzoni 2696c5aff182SThomas Petazzoni tx_desc->buf_phys_addr = dma_map_single(dev->dev.parent, skb->data, 2697c5aff182SThomas Petazzoni tx_desc->data_size, 2698c5aff182SThomas Petazzoni DMA_TO_DEVICE); 2699c5aff182SThomas Petazzoni if (unlikely(dma_mapping_error(dev->dev.parent, 2700c5aff182SThomas Petazzoni tx_desc->buf_phys_addr))) { 2701c5aff182SThomas Petazzoni mvneta_txq_desc_put(txq); 2702c5aff182SThomas Petazzoni frags = 0; 2703c5aff182SThomas Petazzoni goto out; 2704c5aff182SThomas Petazzoni } 2705c5aff182SThomas Petazzoni 27069e58c8b4SLorenzo Bianconi buf->type = MVNETA_TYPE_SKB; 2707c5aff182SThomas Petazzoni if (frags == 1) { 2708c5aff182SThomas Petazzoni /* First and Last descriptor */ 2709c5aff182SThomas Petazzoni tx_cmd |= MVNETA_TXD_FLZ_DESC; 2710c5aff182SThomas Petazzoni tx_desc->command = tx_cmd; 27119e58c8b4SLorenzo Bianconi buf->skb = skb; 2712c5aff182SThomas Petazzoni mvneta_txq_inc_put(txq); 2713c5aff182SThomas Petazzoni } else { 2714c5aff182SThomas Petazzoni /* First but not Last */ 2715c5aff182SThomas Petazzoni tx_cmd |= MVNETA_TXD_F_DESC; 27169e58c8b4SLorenzo Bianconi buf->skb = NULL; 2717c5aff182SThomas Petazzoni mvneta_txq_inc_put(txq); 2718c5aff182SThomas Petazzoni tx_desc->command = tx_cmd; 2719c5aff182SThomas Petazzoni /* Continue with other skb fragments */ 2720c5aff182SThomas Petazzoni if (mvneta_tx_frag_process(pp, skb, txq)) { 2721c5aff182SThomas Petazzoni dma_unmap_single(dev->dev.parent, 2722c5aff182SThomas Petazzoni tx_desc->buf_phys_addr, 2723c5aff182SThomas Petazzoni tx_desc->data_size, 2724c5aff182SThomas Petazzoni DMA_TO_DEVICE); 2725c5aff182SThomas Petazzoni mvneta_txq_desc_put(txq); 2726c5aff182SThomas Petazzoni frags = 0; 2727c5aff182SThomas Petazzoni goto out; 2728c5aff182SThomas Petazzoni } 2729c5aff182SThomas Petazzoni } 2730c5aff182SThomas Petazzoni 2731e19d2ddaSEzequiel Garcia out: 2732e19d2ddaSEzequiel Garcia if (frags > 0) { 2733e19d2ddaSEzequiel Garcia struct netdev_queue *nq = netdev_get_tx_queue(dev, txq_id); 273469de66fcSLorenzo Bianconi struct mvneta_pcpu_stats *stats = this_cpu_ptr(pp->stats); 2735e19d2ddaSEzequiel Garcia 2736a29b6235SMarcin Wojtas netdev_tx_sent_queue(nq, len); 2737a29b6235SMarcin Wojtas 2738c5aff182SThomas Petazzoni txq->count += frags; 27398eef5f97SEzequiel Garcia if (txq->count >= txq->tx_stop_threshold) 2740c5aff182SThomas Petazzoni netif_tx_stop_queue(nq); 2741c5aff182SThomas Petazzoni 27426b16f9eeSFlorian Westphal if (!netdev_xmit_more() || netif_xmit_stopped(nq) || 27432a90f7e1SSimon Guinot txq->pending + frags > MVNETA_TXQ_DEC_SENT_MASK) 27442a90f7e1SSimon Guinot mvneta_txq_pend_desc_add(pp, txq, frags); 27452a90f7e1SSimon Guinot else 27462a90f7e1SSimon Guinot txq->pending += frags; 27472a90f7e1SSimon Guinot 274869de66fcSLorenzo Bianconi u64_stats_update_begin(&stats->syncp); 274969de66fcSLorenzo Bianconi stats->tx_bytes += len; 275069de66fcSLorenzo Bianconi stats->tx_packets++; 275169de66fcSLorenzo Bianconi u64_stats_update_end(&stats->syncp); 2752c5aff182SThomas Petazzoni } else { 2753c5aff182SThomas Petazzoni dev->stats.tx_dropped++; 2754c5aff182SThomas Petazzoni dev_kfree_skb_any(skb); 2755c5aff182SThomas Petazzoni } 2756c5aff182SThomas Petazzoni 2757c5aff182SThomas Petazzoni return NETDEV_TX_OK; 2758c5aff182SThomas Petazzoni } 2759c5aff182SThomas Petazzoni 2760c5aff182SThomas Petazzoni 2761c5aff182SThomas Petazzoni /* Free tx resources, when resetting a port */ 2762c5aff182SThomas Petazzoni static void mvneta_txq_done_force(struct mvneta_port *pp, 2763c5aff182SThomas Petazzoni struct mvneta_tx_queue *txq) 2764c5aff182SThomas Petazzoni 2765c5aff182SThomas Petazzoni { 2766a29b6235SMarcin Wojtas struct netdev_queue *nq = netdev_get_tx_queue(pp->dev, txq->id); 2767c5aff182SThomas Petazzoni int tx_done = txq->count; 2768c5aff182SThomas Petazzoni 2769a29b6235SMarcin Wojtas mvneta_txq_bufs_free(pp, txq, tx_done, nq); 2770c5aff182SThomas Petazzoni 2771c5aff182SThomas Petazzoni /* reset txq */ 2772c5aff182SThomas Petazzoni txq->count = 0; 2773c5aff182SThomas Petazzoni txq->txq_put_index = 0; 2774c5aff182SThomas Petazzoni txq->txq_get_index = 0; 2775c5aff182SThomas Petazzoni } 2776c5aff182SThomas Petazzoni 27776c498974Swilly tarreau /* Handle tx done - called in softirq context. The <cause_tx_done> argument 27786c498974Swilly tarreau * must be a valid cause according to MVNETA_TXQ_INTR_MASK_ALL. 27796c498974Swilly tarreau */ 27800713a86aSArnaud Ebalard static void mvneta_tx_done_gbe(struct mvneta_port *pp, u32 cause_tx_done) 2781c5aff182SThomas Petazzoni { 2782c5aff182SThomas Petazzoni struct mvneta_tx_queue *txq; 2783c5aff182SThomas Petazzoni struct netdev_queue *nq; 2784bd9f1ee3SJisheng Zhang int cpu = smp_processor_id(); 2785c5aff182SThomas Petazzoni 27866c498974Swilly tarreau while (cause_tx_done) { 2787c5aff182SThomas Petazzoni txq = mvneta_tx_done_policy(pp, cause_tx_done); 2788c5aff182SThomas Petazzoni 2789c5aff182SThomas Petazzoni nq = netdev_get_tx_queue(pp->dev, txq->id); 2790bd9f1ee3SJisheng Zhang __netif_tx_lock(nq, cpu); 2791c5aff182SThomas Petazzoni 27920713a86aSArnaud Ebalard if (txq->count) 27930713a86aSArnaud Ebalard mvneta_txq_done(pp, txq); 2794c5aff182SThomas Petazzoni 2795c5aff182SThomas Petazzoni __netif_tx_unlock(nq); 2796c5aff182SThomas Petazzoni cause_tx_done &= ~((1 << txq->id)); 2797c5aff182SThomas Petazzoni } 2798c5aff182SThomas Petazzoni } 2799c5aff182SThomas Petazzoni 28006a20c175SThomas Petazzoni /* Compute crc8 of the specified address, using a unique algorithm , 2801c5aff182SThomas Petazzoni * according to hw spec, different than generic crc8 algorithm 2802c5aff182SThomas Petazzoni */ 2803c5aff182SThomas Petazzoni static int mvneta_addr_crc(unsigned char *addr) 2804c5aff182SThomas Petazzoni { 2805c5aff182SThomas Petazzoni int crc = 0; 2806c5aff182SThomas Petazzoni int i; 2807c5aff182SThomas Petazzoni 2808c5aff182SThomas Petazzoni for (i = 0; i < ETH_ALEN; i++) { 2809c5aff182SThomas Petazzoni int j; 2810c5aff182SThomas Petazzoni 2811c5aff182SThomas Petazzoni crc = (crc ^ addr[i]) << 8; 2812c5aff182SThomas Petazzoni for (j = 7; j >= 0; j--) { 2813c5aff182SThomas Petazzoni if (crc & (0x100 << j)) 2814c5aff182SThomas Petazzoni crc ^= 0x107 << j; 2815c5aff182SThomas Petazzoni } 2816c5aff182SThomas Petazzoni } 2817c5aff182SThomas Petazzoni 2818c5aff182SThomas Petazzoni return crc; 2819c5aff182SThomas Petazzoni } 2820c5aff182SThomas Petazzoni 2821c5aff182SThomas Petazzoni /* This method controls the net device special MAC multicast support. 2822c5aff182SThomas Petazzoni * The Special Multicast Table for MAC addresses supports MAC of the form 2823c5aff182SThomas Petazzoni * 0x01-00-5E-00-00-XX (where XX is between 0x00 and 0xFF). 2824c5aff182SThomas Petazzoni * The MAC DA[7:0] bits are used as a pointer to the Special Multicast 2825c5aff182SThomas Petazzoni * Table entries in the DA-Filter table. This method set the Special 2826c5aff182SThomas Petazzoni * Multicast Table appropriate entry. 2827c5aff182SThomas Petazzoni */ 2828c5aff182SThomas Petazzoni static void mvneta_set_special_mcast_addr(struct mvneta_port *pp, 2829c5aff182SThomas Petazzoni unsigned char last_byte, 2830c5aff182SThomas Petazzoni int queue) 2831c5aff182SThomas Petazzoni { 2832c5aff182SThomas Petazzoni unsigned int smc_table_reg; 2833c5aff182SThomas Petazzoni unsigned int tbl_offset; 2834c5aff182SThomas Petazzoni unsigned int reg_offset; 2835c5aff182SThomas Petazzoni 2836c5aff182SThomas Petazzoni /* Register offset from SMC table base */ 2837c5aff182SThomas Petazzoni tbl_offset = (last_byte / 4); 2838c5aff182SThomas Petazzoni /* Entry offset within the above reg */ 2839c5aff182SThomas Petazzoni reg_offset = last_byte % 4; 2840c5aff182SThomas Petazzoni 2841c5aff182SThomas Petazzoni smc_table_reg = mvreg_read(pp, (MVNETA_DA_FILT_SPEC_MCAST 2842c5aff182SThomas Petazzoni + tbl_offset * 4)); 2843c5aff182SThomas Petazzoni 2844c5aff182SThomas Petazzoni if (queue == -1) 2845c5aff182SThomas Petazzoni smc_table_reg &= ~(0xff << (8 * reg_offset)); 2846c5aff182SThomas Petazzoni else { 2847c5aff182SThomas Petazzoni smc_table_reg &= ~(0xff << (8 * reg_offset)); 2848c5aff182SThomas Petazzoni smc_table_reg |= ((0x01 | (queue << 1)) << (8 * reg_offset)); 2849c5aff182SThomas Petazzoni } 2850c5aff182SThomas Petazzoni 2851c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_DA_FILT_SPEC_MCAST + tbl_offset * 4, 2852c5aff182SThomas Petazzoni smc_table_reg); 2853c5aff182SThomas Petazzoni } 2854c5aff182SThomas Petazzoni 2855c5aff182SThomas Petazzoni /* This method controls the network device Other MAC multicast support. 2856c5aff182SThomas Petazzoni * The Other Multicast Table is used for multicast of another type. 2857c5aff182SThomas Petazzoni * A CRC-8 is used as an index to the Other Multicast Table entries 2858c5aff182SThomas Petazzoni * in the DA-Filter table. 2859c5aff182SThomas Petazzoni * The method gets the CRC-8 value from the calling routine and 2860c5aff182SThomas Petazzoni * sets the Other Multicast Table appropriate entry according to the 2861c5aff182SThomas Petazzoni * specified CRC-8 . 2862c5aff182SThomas Petazzoni */ 2863c5aff182SThomas Petazzoni static void mvneta_set_other_mcast_addr(struct mvneta_port *pp, 2864c5aff182SThomas Petazzoni unsigned char crc8, 2865c5aff182SThomas Petazzoni int queue) 2866c5aff182SThomas Petazzoni { 2867c5aff182SThomas Petazzoni unsigned int omc_table_reg; 2868c5aff182SThomas Petazzoni unsigned int tbl_offset; 2869c5aff182SThomas Petazzoni unsigned int reg_offset; 2870c5aff182SThomas Petazzoni 2871c5aff182SThomas Petazzoni tbl_offset = (crc8 / 4) * 4; /* Register offset from OMC table base */ 2872c5aff182SThomas Petazzoni reg_offset = crc8 % 4; /* Entry offset within the above reg */ 2873c5aff182SThomas Petazzoni 2874c5aff182SThomas Petazzoni omc_table_reg = mvreg_read(pp, MVNETA_DA_FILT_OTH_MCAST + tbl_offset); 2875c5aff182SThomas Petazzoni 2876c5aff182SThomas Petazzoni if (queue == -1) { 2877c5aff182SThomas Petazzoni /* Clear accepts frame bit at specified Other DA table entry */ 2878c5aff182SThomas Petazzoni omc_table_reg &= ~(0xff << (8 * reg_offset)); 2879c5aff182SThomas Petazzoni } else { 2880c5aff182SThomas Petazzoni omc_table_reg &= ~(0xff << (8 * reg_offset)); 2881c5aff182SThomas Petazzoni omc_table_reg |= ((0x01 | (queue << 1)) << (8 * reg_offset)); 2882c5aff182SThomas Petazzoni } 2883c5aff182SThomas Petazzoni 2884c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_DA_FILT_OTH_MCAST + tbl_offset, omc_table_reg); 2885c5aff182SThomas Petazzoni } 2886c5aff182SThomas Petazzoni 2887c5aff182SThomas Petazzoni /* The network device supports multicast using two tables: 2888c5aff182SThomas Petazzoni * 1) Special Multicast Table for MAC addresses of the form 2889c5aff182SThomas Petazzoni * 0x01-00-5E-00-00-XX (where XX is between 0x00 and 0xFF). 2890c5aff182SThomas Petazzoni * The MAC DA[7:0] bits are used as a pointer to the Special Multicast 2891c5aff182SThomas Petazzoni * Table entries in the DA-Filter table. 2892c5aff182SThomas Petazzoni * 2) Other Multicast Table for multicast of another type. A CRC-8 value 2893c5aff182SThomas Petazzoni * is used as an index to the Other Multicast Table entries in the 2894c5aff182SThomas Petazzoni * DA-Filter table. 2895c5aff182SThomas Petazzoni */ 2896c5aff182SThomas Petazzoni static int mvneta_mcast_addr_set(struct mvneta_port *pp, unsigned char *p_addr, 2897c5aff182SThomas Petazzoni int queue) 2898c5aff182SThomas Petazzoni { 2899c5aff182SThomas Petazzoni unsigned char crc_result = 0; 2900c5aff182SThomas Petazzoni 2901c5aff182SThomas Petazzoni if (memcmp(p_addr, "\x01\x00\x5e\x00\x00", 5) == 0) { 2902c5aff182SThomas Petazzoni mvneta_set_special_mcast_addr(pp, p_addr[5], queue); 2903c5aff182SThomas Petazzoni return 0; 2904c5aff182SThomas Petazzoni } 2905c5aff182SThomas Petazzoni 2906c5aff182SThomas Petazzoni crc_result = mvneta_addr_crc(p_addr); 2907c5aff182SThomas Petazzoni if (queue == -1) { 2908c5aff182SThomas Petazzoni if (pp->mcast_count[crc_result] == 0) { 2909c5aff182SThomas Petazzoni netdev_info(pp->dev, "No valid Mcast for crc8=0x%02x\n", 2910c5aff182SThomas Petazzoni crc_result); 2911c5aff182SThomas Petazzoni return -EINVAL; 2912c5aff182SThomas Petazzoni } 2913c5aff182SThomas Petazzoni 2914c5aff182SThomas Petazzoni pp->mcast_count[crc_result]--; 2915c5aff182SThomas Petazzoni if (pp->mcast_count[crc_result] != 0) { 2916c5aff182SThomas Petazzoni netdev_info(pp->dev, 2917c5aff182SThomas Petazzoni "After delete there are %d valid Mcast for crc8=0x%02x\n", 2918c5aff182SThomas Petazzoni pp->mcast_count[crc_result], crc_result); 2919c5aff182SThomas Petazzoni return -EINVAL; 2920c5aff182SThomas Petazzoni } 2921c5aff182SThomas Petazzoni } else 2922c5aff182SThomas Petazzoni pp->mcast_count[crc_result]++; 2923c5aff182SThomas Petazzoni 2924c5aff182SThomas Petazzoni mvneta_set_other_mcast_addr(pp, crc_result, queue); 2925c5aff182SThomas Petazzoni 2926c5aff182SThomas Petazzoni return 0; 2927c5aff182SThomas Petazzoni } 2928c5aff182SThomas Petazzoni 2929c5aff182SThomas Petazzoni /* Configure Fitering mode of Ethernet port */ 2930c5aff182SThomas Petazzoni static void mvneta_rx_unicast_promisc_set(struct mvneta_port *pp, 2931c5aff182SThomas Petazzoni int is_promisc) 2932c5aff182SThomas Petazzoni { 2933c5aff182SThomas Petazzoni u32 port_cfg_reg, val; 2934c5aff182SThomas Petazzoni 2935c5aff182SThomas Petazzoni port_cfg_reg = mvreg_read(pp, MVNETA_PORT_CONFIG); 2936c5aff182SThomas Petazzoni 2937c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_TYPE_PRIO); 2938c5aff182SThomas Petazzoni 2939c5aff182SThomas Petazzoni /* Set / Clear UPM bit in port configuration register */ 2940c5aff182SThomas Petazzoni if (is_promisc) { 2941c5aff182SThomas Petazzoni /* Accept all Unicast addresses */ 2942c5aff182SThomas Petazzoni port_cfg_reg |= MVNETA_UNI_PROMISC_MODE; 2943c5aff182SThomas Petazzoni val |= MVNETA_FORCE_UNI; 2944c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_MAC_ADDR_LOW, 0xffff); 2945c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_MAC_ADDR_HIGH, 0xffffffff); 2946c5aff182SThomas Petazzoni } else { 2947c5aff182SThomas Petazzoni /* Reject all Unicast addresses */ 2948c5aff182SThomas Petazzoni port_cfg_reg &= ~MVNETA_UNI_PROMISC_MODE; 2949c5aff182SThomas Petazzoni val &= ~MVNETA_FORCE_UNI; 2950c5aff182SThomas Petazzoni } 2951c5aff182SThomas Petazzoni 2952c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_PORT_CONFIG, port_cfg_reg); 2953c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_TYPE_PRIO, val); 2954c5aff182SThomas Petazzoni } 2955c5aff182SThomas Petazzoni 2956c5aff182SThomas Petazzoni /* register unicast and multicast addresses */ 2957c5aff182SThomas Petazzoni static void mvneta_set_rx_mode(struct net_device *dev) 2958c5aff182SThomas Petazzoni { 2959c5aff182SThomas Petazzoni struct mvneta_port *pp = netdev_priv(dev); 2960c5aff182SThomas Petazzoni struct netdev_hw_addr *ha; 2961c5aff182SThomas Petazzoni 2962c5aff182SThomas Petazzoni if (dev->flags & IFF_PROMISC) { 2963c5aff182SThomas Petazzoni /* Accept all: Multicast + Unicast */ 2964c5aff182SThomas Petazzoni mvneta_rx_unicast_promisc_set(pp, 1); 296590b74c01SGregory CLEMENT mvneta_set_ucast_table(pp, pp->rxq_def); 296690b74c01SGregory CLEMENT mvneta_set_special_mcast_table(pp, pp->rxq_def); 296790b74c01SGregory CLEMENT mvneta_set_other_mcast_table(pp, pp->rxq_def); 2968c5aff182SThomas Petazzoni } else { 2969c5aff182SThomas Petazzoni /* Accept single Unicast */ 2970c5aff182SThomas Petazzoni mvneta_rx_unicast_promisc_set(pp, 0); 2971c5aff182SThomas Petazzoni mvneta_set_ucast_table(pp, -1); 297290b74c01SGregory CLEMENT mvneta_mac_addr_set(pp, dev->dev_addr, pp->rxq_def); 2973c5aff182SThomas Petazzoni 2974c5aff182SThomas Petazzoni if (dev->flags & IFF_ALLMULTI) { 2975c5aff182SThomas Petazzoni /* Accept all multicast */ 297690b74c01SGregory CLEMENT mvneta_set_special_mcast_table(pp, pp->rxq_def); 297790b74c01SGregory CLEMENT mvneta_set_other_mcast_table(pp, pp->rxq_def); 2978c5aff182SThomas Petazzoni } else { 2979c5aff182SThomas Petazzoni /* Accept only initialized multicast */ 2980c5aff182SThomas Petazzoni mvneta_set_special_mcast_table(pp, -1); 2981c5aff182SThomas Petazzoni mvneta_set_other_mcast_table(pp, -1); 2982c5aff182SThomas Petazzoni 2983c5aff182SThomas Petazzoni if (!netdev_mc_empty(dev)) { 2984c5aff182SThomas Petazzoni netdev_for_each_mc_addr(ha, dev) { 2985c5aff182SThomas Petazzoni mvneta_mcast_addr_set(pp, ha->addr, 298690b74c01SGregory CLEMENT pp->rxq_def); 2987c5aff182SThomas Petazzoni } 2988c5aff182SThomas Petazzoni } 2989c5aff182SThomas Petazzoni } 2990c5aff182SThomas Petazzoni } 2991c5aff182SThomas Petazzoni } 2992c5aff182SThomas Petazzoni 2993c5aff182SThomas Petazzoni /* Interrupt handling - the callback for request_irq() */ 2994c5aff182SThomas Petazzoni static irqreturn_t mvneta_isr(int irq, void *dev_id) 2995c5aff182SThomas Petazzoni { 29962636ac3cSMarcin Wojtas struct mvneta_port *pp = (struct mvneta_port *)dev_id; 29972636ac3cSMarcin Wojtas 29982636ac3cSMarcin Wojtas mvreg_write(pp, MVNETA_INTR_NEW_MASK, 0); 29992636ac3cSMarcin Wojtas napi_schedule(&pp->napi); 30002636ac3cSMarcin Wojtas 30012636ac3cSMarcin Wojtas return IRQ_HANDLED; 30022636ac3cSMarcin Wojtas } 30032636ac3cSMarcin Wojtas 30042636ac3cSMarcin Wojtas /* Interrupt handling - the callback for request_percpu_irq() */ 30052636ac3cSMarcin Wojtas static irqreturn_t mvneta_percpu_isr(int irq, void *dev_id) 30062636ac3cSMarcin Wojtas { 300712bb03b4SMaxime Ripard struct mvneta_pcpu_port *port = (struct mvneta_pcpu_port *)dev_id; 3008c5aff182SThomas Petazzoni 300912bb03b4SMaxime Ripard disable_percpu_irq(port->pp->dev->irq); 301012bb03b4SMaxime Ripard napi_schedule(&port->napi); 3011c5aff182SThomas Petazzoni 3012c5aff182SThomas Petazzoni return IRQ_HANDLED; 3013c5aff182SThomas Petazzoni } 3014c5aff182SThomas Petazzoni 3015503f9aa9SRussell King static void mvneta_link_change(struct mvneta_port *pp) 3016898b2970SStas Sergeev { 3017898b2970SStas Sergeev u32 gmac_stat = mvreg_read(pp, MVNETA_GMAC_STATUS); 3018898b2970SStas Sergeev 3019503f9aa9SRussell King phylink_mac_change(pp->phylink, !!(gmac_stat & MVNETA_GMAC_LINK_UP)); 3020898b2970SStas Sergeev } 3021898b2970SStas Sergeev 3022c5aff182SThomas Petazzoni /* NAPI handler 3023c5aff182SThomas Petazzoni * Bits 0 - 7 of the causeRxTx register indicate that are transmitted 3024c5aff182SThomas Petazzoni * packets on the corresponding TXQ (Bit 0 is for TX queue 1). 3025c5aff182SThomas Petazzoni * Bits 8 -15 of the cause Rx Tx register indicate that are received 3026c5aff182SThomas Petazzoni * packets on the corresponding RXQ (Bit 8 is for RX queue 0). 3027c5aff182SThomas Petazzoni * Each CPU has its own causeRxTx register 3028c5aff182SThomas Petazzoni */ 3029c5aff182SThomas Petazzoni static int mvneta_poll(struct napi_struct *napi, int budget) 3030c5aff182SThomas Petazzoni { 3031c5aff182SThomas Petazzoni int rx_done = 0; 3032c5aff182SThomas Petazzoni u32 cause_rx_tx; 30332dcf75e2SGregory CLEMENT int rx_queue; 3034c5aff182SThomas Petazzoni struct mvneta_port *pp = netdev_priv(napi->dev); 303512bb03b4SMaxime Ripard struct mvneta_pcpu_port *port = this_cpu_ptr(pp->ports); 3036c5aff182SThomas Petazzoni 3037c5aff182SThomas Petazzoni if (!netif_running(pp->dev)) { 30382636ac3cSMarcin Wojtas napi_complete(napi); 3039c5aff182SThomas Petazzoni return rx_done; 3040c5aff182SThomas Petazzoni } 3041c5aff182SThomas Petazzoni 3042c5aff182SThomas Petazzoni /* Read cause register */ 3043898b2970SStas Sergeev cause_rx_tx = mvreg_read(pp, MVNETA_INTR_NEW_CAUSE); 3044898b2970SStas Sergeev if (cause_rx_tx & MVNETA_MISCINTR_INTR_MASK) { 3045898b2970SStas Sergeev u32 cause_misc = mvreg_read(pp, MVNETA_INTR_MISC_CAUSE); 3046898b2970SStas Sergeev 3047898b2970SStas Sergeev mvreg_write(pp, MVNETA_INTR_MISC_CAUSE, 0); 3048503f9aa9SRussell King 3049503f9aa9SRussell King if (cause_misc & (MVNETA_CAUSE_PHY_STATUS_CHANGE | 3050856b2cc5SRussell King MVNETA_CAUSE_LINK_CHANGE)) 3051503f9aa9SRussell King mvneta_link_change(pp); 3052898b2970SStas Sergeev } 305371f6d1b3Swilly tarreau 305471f6d1b3Swilly tarreau /* Release Tx descriptors */ 305571f6d1b3Swilly tarreau if (cause_rx_tx & MVNETA_TX_INTR_MASK_ALL) { 30560713a86aSArnaud Ebalard mvneta_tx_done_gbe(pp, (cause_rx_tx & MVNETA_TX_INTR_MASK_ALL)); 305771f6d1b3Swilly tarreau cause_rx_tx &= ~MVNETA_TX_INTR_MASK_ALL; 305871f6d1b3Swilly tarreau } 3059c5aff182SThomas Petazzoni 30606a20c175SThomas Petazzoni /* For the case where the last mvneta_poll did not process all 3061c5aff182SThomas Petazzoni * RX packets 3062c5aff182SThomas Petazzoni */ 30632dcf75e2SGregory CLEMENT rx_queue = fls(((cause_rx_tx >> 8) & 0xff)); 30642dcf75e2SGregory CLEMENT 30652636ac3cSMarcin Wojtas cause_rx_tx |= pp->neta_armada3700 ? pp->cause_rx_tx : 30662636ac3cSMarcin Wojtas port->cause_rx_tx; 30672dcf75e2SGregory CLEMENT 30682dcf75e2SGregory CLEMENT if (rx_queue) { 30692dcf75e2SGregory CLEMENT rx_queue = rx_queue - 1; 3070dc35a10fSMarcin Wojtas if (pp->bm_priv) 30717a86f05fSAndrew Lunn rx_done = mvneta_rx_hwbm(napi, pp, budget, 30727a86f05fSAndrew Lunn &pp->rxqs[rx_queue]); 3073dc35a10fSMarcin Wojtas else 30747a86f05fSAndrew Lunn rx_done = mvneta_rx_swbm(napi, pp, budget, 30757a86f05fSAndrew Lunn &pp->rxqs[rx_queue]); 30762dcf75e2SGregory CLEMENT } 30772dcf75e2SGregory CLEMENT 30786ad20165SEric Dumazet if (rx_done < budget) { 3079c5aff182SThomas Petazzoni cause_rx_tx = 0; 30806ad20165SEric Dumazet napi_complete_done(napi, rx_done); 30812636ac3cSMarcin Wojtas 30822636ac3cSMarcin Wojtas if (pp->neta_armada3700) { 30832636ac3cSMarcin Wojtas unsigned long flags; 30842636ac3cSMarcin Wojtas 30852636ac3cSMarcin Wojtas local_irq_save(flags); 30862636ac3cSMarcin Wojtas mvreg_write(pp, MVNETA_INTR_NEW_MASK, 30872636ac3cSMarcin Wojtas MVNETA_RX_INTR_MASK(rxq_number) | 30882636ac3cSMarcin Wojtas MVNETA_TX_INTR_MASK(txq_number) | 30892636ac3cSMarcin Wojtas MVNETA_MISCINTR_INTR_MASK); 30902636ac3cSMarcin Wojtas local_irq_restore(flags); 30912636ac3cSMarcin Wojtas } else { 309212bb03b4SMaxime Ripard enable_percpu_irq(pp->dev->irq, 0); 3093c5aff182SThomas Petazzoni } 30942636ac3cSMarcin Wojtas } 3095c5aff182SThomas Petazzoni 30962636ac3cSMarcin Wojtas if (pp->neta_armada3700) 30972636ac3cSMarcin Wojtas pp->cause_rx_tx = cause_rx_tx; 30982636ac3cSMarcin Wojtas else 309912bb03b4SMaxime Ripard port->cause_rx_tx = cause_rx_tx; 31002636ac3cSMarcin Wojtas 3101c5aff182SThomas Petazzoni return rx_done; 3102c5aff182SThomas Petazzoni } 3103c5aff182SThomas Petazzoni 3104568a3fa2SLorenzo Bianconi static int mvneta_create_page_pool(struct mvneta_port *pp, 3105568a3fa2SLorenzo Bianconi struct mvneta_rx_queue *rxq, int size) 3106568a3fa2SLorenzo Bianconi { 31070db51da7SLorenzo Bianconi struct bpf_prog *xdp_prog = READ_ONCE(pp->xdp_prog); 3108568a3fa2SLorenzo Bianconi struct page_pool_params pp_params = { 3109568a3fa2SLorenzo Bianconi .order = 0, 311007e13edbSLorenzo Bianconi .flags = PP_FLAG_DMA_MAP | PP_FLAG_DMA_SYNC_DEV, 3111568a3fa2SLorenzo Bianconi .pool_size = size, 31121657adccSLorenzo Bianconi .nid = NUMA_NO_NODE, 3113568a3fa2SLorenzo Bianconi .dev = pp->dev->dev.parent, 31140db51da7SLorenzo Bianconi .dma_dir = xdp_prog ? DMA_BIDIRECTIONAL : DMA_FROM_DEVICE, 311507e13edbSLorenzo Bianconi .offset = pp->rx_offset_correction, 311607e13edbSLorenzo Bianconi .max_len = MVNETA_MAX_RX_BUF_SIZE, 3117568a3fa2SLorenzo Bianconi }; 3118568a3fa2SLorenzo Bianconi int err; 3119568a3fa2SLorenzo Bianconi 3120568a3fa2SLorenzo Bianconi rxq->page_pool = page_pool_create(&pp_params); 3121568a3fa2SLorenzo Bianconi if (IS_ERR(rxq->page_pool)) { 3122568a3fa2SLorenzo Bianconi err = PTR_ERR(rxq->page_pool); 3123568a3fa2SLorenzo Bianconi rxq->page_pool = NULL; 3124568a3fa2SLorenzo Bianconi return err; 3125568a3fa2SLorenzo Bianconi } 3126568a3fa2SLorenzo Bianconi 3127568a3fa2SLorenzo Bianconi err = xdp_rxq_info_reg(&rxq->xdp_rxq, pp->dev, rxq->id); 3128568a3fa2SLorenzo Bianconi if (err < 0) 3129568a3fa2SLorenzo Bianconi goto err_free_pp; 3130568a3fa2SLorenzo Bianconi 3131568a3fa2SLorenzo Bianconi err = xdp_rxq_info_reg_mem_model(&rxq->xdp_rxq, MEM_TYPE_PAGE_POOL, 3132568a3fa2SLorenzo Bianconi rxq->page_pool); 3133568a3fa2SLorenzo Bianconi if (err) 3134568a3fa2SLorenzo Bianconi goto err_unregister_rxq; 3135568a3fa2SLorenzo Bianconi 3136568a3fa2SLorenzo Bianconi return 0; 3137568a3fa2SLorenzo Bianconi 3138568a3fa2SLorenzo Bianconi err_unregister_rxq: 3139568a3fa2SLorenzo Bianconi xdp_rxq_info_unreg(&rxq->xdp_rxq); 3140568a3fa2SLorenzo Bianconi err_free_pp: 3141568a3fa2SLorenzo Bianconi page_pool_destroy(rxq->page_pool); 3142568a3fa2SLorenzo Bianconi rxq->page_pool = NULL; 3143568a3fa2SLorenzo Bianconi return err; 3144568a3fa2SLorenzo Bianconi } 3145568a3fa2SLorenzo Bianconi 3146c5aff182SThomas Petazzoni /* Handle rxq fill: allocates rxq skbs; called when initializing a port */ 3147c5aff182SThomas Petazzoni static int mvneta_rxq_fill(struct mvneta_port *pp, struct mvneta_rx_queue *rxq, 3148c5aff182SThomas Petazzoni int num) 3149c5aff182SThomas Petazzoni { 3150568a3fa2SLorenzo Bianconi int i, err; 3151568a3fa2SLorenzo Bianconi 3152568a3fa2SLorenzo Bianconi err = mvneta_create_page_pool(pp, rxq, num); 3153568a3fa2SLorenzo Bianconi if (err < 0) 3154568a3fa2SLorenzo Bianconi return err; 3155c5aff182SThomas Petazzoni 3156c5aff182SThomas Petazzoni for (i = 0; i < num; i++) { 3157a1a65ab1Swilly tarreau memset(rxq->descs + i, 0, sizeof(struct mvneta_rx_desc)); 31587e47fd84SGregory CLEMENT if (mvneta_rx_refill(pp, rxq->descs + i, rxq, 31597e47fd84SGregory CLEMENT GFP_KERNEL) != 0) { 31607e47fd84SGregory CLEMENT netdev_err(pp->dev, 31617e47fd84SGregory CLEMENT "%s:rxq %d, %d of %d buffs filled\n", 3162c5aff182SThomas Petazzoni __func__, rxq->id, i, num); 3163c5aff182SThomas Petazzoni break; 3164c5aff182SThomas Petazzoni } 3165c5aff182SThomas Petazzoni } 3166c5aff182SThomas Petazzoni 3167c5aff182SThomas Petazzoni /* Add this number of RX descriptors as non occupied (ready to 31686a20c175SThomas Petazzoni * get packets) 31696a20c175SThomas Petazzoni */ 3170c5aff182SThomas Petazzoni mvneta_rxq_non_occup_desc_add(pp, rxq, i); 3171c5aff182SThomas Petazzoni 3172c5aff182SThomas Petazzoni return i; 3173c5aff182SThomas Petazzoni } 3174c5aff182SThomas Petazzoni 3175c5aff182SThomas Petazzoni /* Free all packets pending transmit from all TXQs and reset TX port */ 3176c5aff182SThomas Petazzoni static void mvneta_tx_reset(struct mvneta_port *pp) 3177c5aff182SThomas Petazzoni { 3178c5aff182SThomas Petazzoni int queue; 3179c5aff182SThomas Petazzoni 31809672850bSEzequiel Garcia /* free the skb's in the tx ring */ 3181c5aff182SThomas Petazzoni for (queue = 0; queue < txq_number; queue++) 3182c5aff182SThomas Petazzoni mvneta_txq_done_force(pp, &pp->txqs[queue]); 3183c5aff182SThomas Petazzoni 3184c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_PORT_TX_RESET, MVNETA_PORT_TX_DMA_RESET); 3185c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_PORT_TX_RESET, 0); 3186c5aff182SThomas Petazzoni } 3187c5aff182SThomas Petazzoni 3188c5aff182SThomas Petazzoni static void mvneta_rx_reset(struct mvneta_port *pp) 3189c5aff182SThomas Petazzoni { 3190c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_PORT_RX_RESET, MVNETA_PORT_RX_DMA_RESET); 3191c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_PORT_RX_RESET, 0); 3192c5aff182SThomas Petazzoni } 3193c5aff182SThomas Petazzoni 3194c5aff182SThomas Petazzoni /* Rx/Tx queue initialization/cleanup methods */ 3195c5aff182SThomas Petazzoni 31964a188a63SJisheng Zhang static int mvneta_rxq_sw_init(struct mvneta_port *pp, 3197c5aff182SThomas Petazzoni struct mvneta_rx_queue *rxq) 3198c5aff182SThomas Petazzoni { 3199c5aff182SThomas Petazzoni rxq->size = pp->rx_ring_size; 3200c5aff182SThomas Petazzoni 3201c5aff182SThomas Petazzoni /* Allocate memory for RX descriptors */ 3202c5aff182SThomas Petazzoni rxq->descs = dma_alloc_coherent(pp->dev->dev.parent, 3203c5aff182SThomas Petazzoni rxq->size * MVNETA_DESC_ALIGNED_SIZE, 3204c5aff182SThomas Petazzoni &rxq->descs_phys, GFP_KERNEL); 3205f95936ccSMarkus Elfring if (!rxq->descs) 3206c5aff182SThomas Petazzoni return -ENOMEM; 3207c5aff182SThomas Petazzoni 3208c5aff182SThomas Petazzoni rxq->last_desc = rxq->size - 1; 3209c5aff182SThomas Petazzoni 32104a188a63SJisheng Zhang return 0; 32114a188a63SJisheng Zhang } 32124a188a63SJisheng Zhang 32134a188a63SJisheng Zhang static void mvneta_rxq_hw_init(struct mvneta_port *pp, 32144a188a63SJisheng Zhang struct mvneta_rx_queue *rxq) 32154a188a63SJisheng Zhang { 3216c5aff182SThomas Petazzoni /* Set Rx descriptors queue starting address */ 3217c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_RXQ_BASE_ADDR_REG(rxq->id), rxq->descs_phys); 3218c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_RXQ_SIZE_REG(rxq->id), rxq->size); 3219c5aff182SThomas Petazzoni 3220c5aff182SThomas Petazzoni /* Set coalescing pkts and time */ 3221c5aff182SThomas Petazzoni mvneta_rx_pkts_coal_set(pp, rxq, rxq->pkts_coal); 3222c5aff182SThomas Petazzoni mvneta_rx_time_coal_set(pp, rxq, rxq->time_coal); 3223c5aff182SThomas Petazzoni 3224dc35a10fSMarcin Wojtas if (!pp->bm_priv) { 3225562e2f46SYelena Krivosheev /* Set Offset */ 3226562e2f46SYelena Krivosheev mvneta_rxq_offset_set(pp, rxq, 0); 3227e735fd55SMarcin Wojtas mvneta_rxq_buf_size_set(pp, rxq, PAGE_SIZE < SZ_64K ? 32288dc9a088SLorenzo Bianconi MVNETA_MAX_RX_BUF_SIZE : 3229e735fd55SMarcin Wojtas MVNETA_RX_BUF_SIZE(pp->pkt_size)); 3230c5aff182SThomas Petazzoni mvneta_rxq_bm_disable(pp, rxq); 3231e9f64999SGregory CLEMENT mvneta_rxq_fill(pp, rxq, rxq->size); 3232dc35a10fSMarcin Wojtas } else { 3233562e2f46SYelena Krivosheev /* Set Offset */ 3234562e2f46SYelena Krivosheev mvneta_rxq_offset_set(pp, rxq, 3235562e2f46SYelena Krivosheev NET_SKB_PAD - pp->rx_offset_correction); 3236562e2f46SYelena Krivosheev 3237dc35a10fSMarcin Wojtas mvneta_rxq_bm_enable(pp, rxq); 3238562e2f46SYelena Krivosheev /* Fill RXQ with buffers from RX pool */ 3239dc35a10fSMarcin Wojtas mvneta_rxq_long_pool_set(pp, rxq); 3240dc35a10fSMarcin Wojtas mvneta_rxq_short_pool_set(pp, rxq); 3241e9f64999SGregory CLEMENT mvneta_rxq_non_occup_desc_add(pp, rxq, rxq->size); 3242dc35a10fSMarcin Wojtas } 32434a188a63SJisheng Zhang } 32444a188a63SJisheng Zhang 32454a188a63SJisheng Zhang /* Create a specified RX queue */ 32464a188a63SJisheng Zhang static int mvneta_rxq_init(struct mvneta_port *pp, 32474a188a63SJisheng Zhang struct mvneta_rx_queue *rxq) 32484a188a63SJisheng Zhang 32494a188a63SJisheng Zhang { 32504a188a63SJisheng Zhang int ret; 32514a188a63SJisheng Zhang 32524a188a63SJisheng Zhang ret = mvneta_rxq_sw_init(pp, rxq); 32534a188a63SJisheng Zhang if (ret < 0) 32544a188a63SJisheng Zhang return ret; 32554a188a63SJisheng Zhang 32564a188a63SJisheng Zhang mvneta_rxq_hw_init(pp, rxq); 3257dc35a10fSMarcin Wojtas 3258c5aff182SThomas Petazzoni return 0; 3259c5aff182SThomas Petazzoni } 3260c5aff182SThomas Petazzoni 3261c5aff182SThomas Petazzoni /* Cleanup Rx queue */ 3262c5aff182SThomas Petazzoni static void mvneta_rxq_deinit(struct mvneta_port *pp, 3263c5aff182SThomas Petazzoni struct mvneta_rx_queue *rxq) 3264c5aff182SThomas Petazzoni { 3265c5aff182SThomas Petazzoni mvneta_rxq_drop_pkts(pp, rxq); 3266c5aff182SThomas Petazzoni 3267562e2f46SYelena Krivosheev if (rxq->skb) 3268562e2f46SYelena Krivosheev dev_kfree_skb_any(rxq->skb); 3269562e2f46SYelena Krivosheev 3270c5aff182SThomas Petazzoni if (rxq->descs) 3271c5aff182SThomas Petazzoni dma_free_coherent(pp->dev->dev.parent, 3272c5aff182SThomas Petazzoni rxq->size * MVNETA_DESC_ALIGNED_SIZE, 3273c5aff182SThomas Petazzoni rxq->descs, 3274c5aff182SThomas Petazzoni rxq->descs_phys); 3275c5aff182SThomas Petazzoni 3276c5aff182SThomas Petazzoni rxq->descs = NULL; 3277c5aff182SThomas Petazzoni rxq->last_desc = 0; 3278c5aff182SThomas Petazzoni rxq->next_desc_to_proc = 0; 3279c5aff182SThomas Petazzoni rxq->descs_phys = 0; 3280562e2f46SYelena Krivosheev rxq->first_to_refill = 0; 3281562e2f46SYelena Krivosheev rxq->refill_num = 0; 3282562e2f46SYelena Krivosheev rxq->skb = NULL; 3283562e2f46SYelena Krivosheev rxq->left_size = 0; 3284c5aff182SThomas Petazzoni } 3285c5aff182SThomas Petazzoni 32864a188a63SJisheng Zhang static int mvneta_txq_sw_init(struct mvneta_port *pp, 3287c5aff182SThomas Petazzoni struct mvneta_tx_queue *txq) 3288c5aff182SThomas Petazzoni { 328950bf8cb6SGregory CLEMENT int cpu; 329050bf8cb6SGregory CLEMENT 3291c5aff182SThomas Petazzoni txq->size = pp->tx_ring_size; 3292c5aff182SThomas Petazzoni 32938eef5f97SEzequiel Garcia /* A queue must always have room for at least one skb. 32948eef5f97SEzequiel Garcia * Therefore, stop the queue when the free entries reaches 32958eef5f97SEzequiel Garcia * the maximum number of descriptors per skb. 32968eef5f97SEzequiel Garcia */ 32978eef5f97SEzequiel Garcia txq->tx_stop_threshold = txq->size - MVNETA_MAX_SKB_DESCS; 32988eef5f97SEzequiel Garcia txq->tx_wake_threshold = txq->tx_stop_threshold / 2; 32998eef5f97SEzequiel Garcia 3300c5aff182SThomas Petazzoni /* Allocate memory for TX descriptors */ 3301c5aff182SThomas Petazzoni txq->descs = dma_alloc_coherent(pp->dev->dev.parent, 3302c5aff182SThomas Petazzoni txq->size * MVNETA_DESC_ALIGNED_SIZE, 3303c5aff182SThomas Petazzoni &txq->descs_phys, GFP_KERNEL); 3304f95936ccSMarkus Elfring if (!txq->descs) 3305c5aff182SThomas Petazzoni return -ENOMEM; 3306c5aff182SThomas Petazzoni 3307c5aff182SThomas Petazzoni txq->last_desc = txq->size - 1; 3308c5aff182SThomas Petazzoni 33099e58c8b4SLorenzo Bianconi txq->buf = kmalloc_array(txq->size, sizeof(*txq->buf), GFP_KERNEL); 33109e58c8b4SLorenzo Bianconi if (!txq->buf) { 3311c5aff182SThomas Petazzoni dma_free_coherent(pp->dev->dev.parent, 3312c5aff182SThomas Petazzoni txq->size * MVNETA_DESC_ALIGNED_SIZE, 3313c5aff182SThomas Petazzoni txq->descs, txq->descs_phys); 3314c5aff182SThomas Petazzoni return -ENOMEM; 3315c5aff182SThomas Petazzoni } 33162adb719dSEzequiel Garcia 33172adb719dSEzequiel Garcia /* Allocate DMA buffers for TSO MAC/IP/TCP headers */ 33182adb719dSEzequiel Garcia txq->tso_hdrs = dma_alloc_coherent(pp->dev->dev.parent, 33192adb719dSEzequiel Garcia txq->size * TSO_HEADER_SIZE, 33202adb719dSEzequiel Garcia &txq->tso_hdrs_phys, GFP_KERNEL); 3321f95936ccSMarkus Elfring if (!txq->tso_hdrs) { 33229e58c8b4SLorenzo Bianconi kfree(txq->buf); 33232adb719dSEzequiel Garcia dma_free_coherent(pp->dev->dev.parent, 33242adb719dSEzequiel Garcia txq->size * MVNETA_DESC_ALIGNED_SIZE, 33252adb719dSEzequiel Garcia txq->descs, txq->descs_phys); 33262adb719dSEzequiel Garcia return -ENOMEM; 33272adb719dSEzequiel Garcia } 3328c5aff182SThomas Petazzoni 332950bf8cb6SGregory CLEMENT /* Setup XPS mapping */ 333050bf8cb6SGregory CLEMENT if (txq_number > 1) 333150bf8cb6SGregory CLEMENT cpu = txq->id % num_present_cpus(); 333250bf8cb6SGregory CLEMENT else 333350bf8cb6SGregory CLEMENT cpu = pp->rxq_def % num_present_cpus(); 333450bf8cb6SGregory CLEMENT cpumask_set_cpu(cpu, &txq->affinity_mask); 333550bf8cb6SGregory CLEMENT netif_set_xps_queue(pp->dev, &txq->affinity_mask, txq->id); 333650bf8cb6SGregory CLEMENT 3337c5aff182SThomas Petazzoni return 0; 3338c5aff182SThomas Petazzoni } 3339c5aff182SThomas Petazzoni 33404a188a63SJisheng Zhang static void mvneta_txq_hw_init(struct mvneta_port *pp, 33414a188a63SJisheng Zhang struct mvneta_tx_queue *txq) 33424a188a63SJisheng Zhang { 33434a188a63SJisheng Zhang /* Set maximum bandwidth for enabled TXQs */ 33444a188a63SJisheng Zhang mvreg_write(pp, MVETH_TXQ_TOKEN_CFG_REG(txq->id), 0x03ffffff); 33454a188a63SJisheng Zhang mvreg_write(pp, MVETH_TXQ_TOKEN_COUNT_REG(txq->id), 0x3fffffff); 33464a188a63SJisheng Zhang 33474a188a63SJisheng Zhang /* Set Tx descriptors queue starting address */ 33484a188a63SJisheng Zhang mvreg_write(pp, MVNETA_TXQ_BASE_ADDR_REG(txq->id), txq->descs_phys); 33494a188a63SJisheng Zhang mvreg_write(pp, MVNETA_TXQ_SIZE_REG(txq->id), txq->size); 33504a188a63SJisheng Zhang 33514a188a63SJisheng Zhang mvneta_tx_done_pkts_coal_set(pp, txq, txq->done_pkts_coal); 33524a188a63SJisheng Zhang } 33534a188a63SJisheng Zhang 33544a188a63SJisheng Zhang /* Create and initialize a tx queue */ 33554a188a63SJisheng Zhang static int mvneta_txq_init(struct mvneta_port *pp, 33564a188a63SJisheng Zhang struct mvneta_tx_queue *txq) 33574a188a63SJisheng Zhang { 33584a188a63SJisheng Zhang int ret; 33594a188a63SJisheng Zhang 33604a188a63SJisheng Zhang ret = mvneta_txq_sw_init(pp, txq); 33614a188a63SJisheng Zhang if (ret < 0) 33624a188a63SJisheng Zhang return ret; 33634a188a63SJisheng Zhang 33644a188a63SJisheng Zhang mvneta_txq_hw_init(pp, txq); 33654a188a63SJisheng Zhang 33664a188a63SJisheng Zhang return 0; 33674a188a63SJisheng Zhang } 33684a188a63SJisheng Zhang 3369c5aff182SThomas Petazzoni /* Free allocated resources when mvneta_txq_init() fails to allocate memory*/ 33704a188a63SJisheng Zhang static void mvneta_txq_sw_deinit(struct mvneta_port *pp, 3371c5aff182SThomas Petazzoni struct mvneta_tx_queue *txq) 3372c5aff182SThomas Petazzoni { 3373a29b6235SMarcin Wojtas struct netdev_queue *nq = netdev_get_tx_queue(pp->dev, txq->id); 3374a29b6235SMarcin Wojtas 33759e58c8b4SLorenzo Bianconi kfree(txq->buf); 3376c5aff182SThomas Petazzoni 33772adb719dSEzequiel Garcia if (txq->tso_hdrs) 33782adb719dSEzequiel Garcia dma_free_coherent(pp->dev->dev.parent, 33792adb719dSEzequiel Garcia txq->size * TSO_HEADER_SIZE, 33802adb719dSEzequiel Garcia txq->tso_hdrs, txq->tso_hdrs_phys); 3381c5aff182SThomas Petazzoni if (txq->descs) 3382c5aff182SThomas Petazzoni dma_free_coherent(pp->dev->dev.parent, 3383c5aff182SThomas Petazzoni txq->size * MVNETA_DESC_ALIGNED_SIZE, 3384c5aff182SThomas Petazzoni txq->descs, txq->descs_phys); 3385c5aff182SThomas Petazzoni 3386a29b6235SMarcin Wojtas netdev_tx_reset_queue(nq); 3387a29b6235SMarcin Wojtas 3388c5aff182SThomas Petazzoni txq->descs = NULL; 3389c5aff182SThomas Petazzoni txq->last_desc = 0; 3390c5aff182SThomas Petazzoni txq->next_desc_to_proc = 0; 3391c5aff182SThomas Petazzoni txq->descs_phys = 0; 33924a188a63SJisheng Zhang } 3393c5aff182SThomas Petazzoni 33944a188a63SJisheng Zhang static void mvneta_txq_hw_deinit(struct mvneta_port *pp, 33954a188a63SJisheng Zhang struct mvneta_tx_queue *txq) 33964a188a63SJisheng Zhang { 3397c5aff182SThomas Petazzoni /* Set minimum bandwidth for disabled TXQs */ 3398c5aff182SThomas Petazzoni mvreg_write(pp, MVETH_TXQ_TOKEN_CFG_REG(txq->id), 0); 3399c5aff182SThomas Petazzoni mvreg_write(pp, MVETH_TXQ_TOKEN_COUNT_REG(txq->id), 0); 3400c5aff182SThomas Petazzoni 3401c5aff182SThomas Petazzoni /* Set Tx descriptors queue starting address and size */ 3402c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_TXQ_BASE_ADDR_REG(txq->id), 0); 3403c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_TXQ_SIZE_REG(txq->id), 0); 3404c5aff182SThomas Petazzoni } 3405c5aff182SThomas Petazzoni 34064a188a63SJisheng Zhang static void mvneta_txq_deinit(struct mvneta_port *pp, 34074a188a63SJisheng Zhang struct mvneta_tx_queue *txq) 34084a188a63SJisheng Zhang { 34094a188a63SJisheng Zhang mvneta_txq_sw_deinit(pp, txq); 34104a188a63SJisheng Zhang mvneta_txq_hw_deinit(pp, txq); 34114a188a63SJisheng Zhang } 34124a188a63SJisheng Zhang 3413c5aff182SThomas Petazzoni /* Cleanup all Tx queues */ 3414c5aff182SThomas Petazzoni static void mvneta_cleanup_txqs(struct mvneta_port *pp) 3415c5aff182SThomas Petazzoni { 3416c5aff182SThomas Petazzoni int queue; 3417c5aff182SThomas Petazzoni 3418c5aff182SThomas Petazzoni for (queue = 0; queue < txq_number; queue++) 3419c5aff182SThomas Petazzoni mvneta_txq_deinit(pp, &pp->txqs[queue]); 3420c5aff182SThomas Petazzoni } 3421c5aff182SThomas Petazzoni 3422c5aff182SThomas Petazzoni /* Cleanup all Rx queues */ 3423c5aff182SThomas Petazzoni static void mvneta_cleanup_rxqs(struct mvneta_port *pp) 3424c5aff182SThomas Petazzoni { 34252dcf75e2SGregory CLEMENT int queue; 34262dcf75e2SGregory CLEMENT 3427ca5902a6SYelena Krivosheev for (queue = 0; queue < rxq_number; queue++) 34282dcf75e2SGregory CLEMENT mvneta_rxq_deinit(pp, &pp->rxqs[queue]); 3429c5aff182SThomas Petazzoni } 3430c5aff182SThomas Petazzoni 3431c5aff182SThomas Petazzoni 3432c5aff182SThomas Petazzoni /* Init all Rx queues */ 3433c5aff182SThomas Petazzoni static int mvneta_setup_rxqs(struct mvneta_port *pp) 3434c5aff182SThomas Petazzoni { 34352dcf75e2SGregory CLEMENT int queue; 34362dcf75e2SGregory CLEMENT 34372dcf75e2SGregory CLEMENT for (queue = 0; queue < rxq_number; queue++) { 34382dcf75e2SGregory CLEMENT int err = mvneta_rxq_init(pp, &pp->rxqs[queue]); 34392dcf75e2SGregory CLEMENT 3440c5aff182SThomas Petazzoni if (err) { 3441c5aff182SThomas Petazzoni netdev_err(pp->dev, "%s: can't create rxq=%d\n", 34422dcf75e2SGregory CLEMENT __func__, queue); 3443c5aff182SThomas Petazzoni mvneta_cleanup_rxqs(pp); 3444c5aff182SThomas Petazzoni return err; 3445c5aff182SThomas Petazzoni } 34462dcf75e2SGregory CLEMENT } 3447c5aff182SThomas Petazzoni 3448c5aff182SThomas Petazzoni return 0; 3449c5aff182SThomas Petazzoni } 3450c5aff182SThomas Petazzoni 3451c5aff182SThomas Petazzoni /* Init all tx queues */ 3452c5aff182SThomas Petazzoni static int mvneta_setup_txqs(struct mvneta_port *pp) 3453c5aff182SThomas Petazzoni { 3454c5aff182SThomas Petazzoni int queue; 3455c5aff182SThomas Petazzoni 3456c5aff182SThomas Petazzoni for (queue = 0; queue < txq_number; queue++) { 3457c5aff182SThomas Petazzoni int err = mvneta_txq_init(pp, &pp->txqs[queue]); 3458c5aff182SThomas Petazzoni if (err) { 3459c5aff182SThomas Petazzoni netdev_err(pp->dev, "%s: can't create txq=%d\n", 3460c5aff182SThomas Petazzoni __func__, queue); 3461c5aff182SThomas Petazzoni mvneta_cleanup_txqs(pp); 3462c5aff182SThomas Petazzoni return err; 3463c5aff182SThomas Petazzoni } 3464c5aff182SThomas Petazzoni } 3465c5aff182SThomas Petazzoni 3466c5aff182SThomas Petazzoni return 0; 3467c5aff182SThomas Petazzoni } 3468c5aff182SThomas Petazzoni 3469031b922bSMarek Behún static int mvneta_comphy_init(struct mvneta_port *pp) 3470031b922bSMarek Behún { 3471031b922bSMarek Behún int ret; 3472031b922bSMarek Behún 3473031b922bSMarek Behún if (!pp->comphy) 3474031b922bSMarek Behún return 0; 3475031b922bSMarek Behún 3476031b922bSMarek Behún ret = phy_set_mode_ext(pp->comphy, PHY_MODE_ETHERNET, 3477031b922bSMarek Behún pp->phy_interface); 3478031b922bSMarek Behún if (ret) 3479031b922bSMarek Behún return ret; 3480031b922bSMarek Behún 3481031b922bSMarek Behún return phy_power_on(pp->comphy); 3482031b922bSMarek Behún } 3483031b922bSMarek Behún 3484c5aff182SThomas Petazzoni static void mvneta_start_dev(struct mvneta_port *pp) 3485c5aff182SThomas Petazzoni { 34866b125d63SGregory CLEMENT int cpu; 348712bb03b4SMaxime Ripard 3488031b922bSMarek Behún WARN_ON(mvneta_comphy_init(pp)); 3489a10c1c81SRussell King 3490c5aff182SThomas Petazzoni mvneta_max_rx_size_set(pp, pp->pkt_size); 3491c5aff182SThomas Petazzoni mvneta_txq_max_tx_size_set(pp, pp->pkt_size); 3492c5aff182SThomas Petazzoni 3493c5aff182SThomas Petazzoni /* start the Rx/Tx activity */ 3494c5aff182SThomas Petazzoni mvneta_port_enable(pp); 3495c5aff182SThomas Petazzoni 34962636ac3cSMarcin Wojtas if (!pp->neta_armada3700) { 3497c5aff182SThomas Petazzoni /* Enable polling on the port */ 3498129219e4SGregory CLEMENT for_each_online_cpu(cpu) { 34992636ac3cSMarcin Wojtas struct mvneta_pcpu_port *port = 35002636ac3cSMarcin Wojtas per_cpu_ptr(pp->ports, cpu); 350112bb03b4SMaxime Ripard 350212bb03b4SMaxime Ripard napi_enable(&port->napi); 350312bb03b4SMaxime Ripard } 35042636ac3cSMarcin Wojtas } else { 35052636ac3cSMarcin Wojtas napi_enable(&pp->napi); 35062636ac3cSMarcin Wojtas } 3507c5aff182SThomas Petazzoni 35082dcf75e2SGregory CLEMENT /* Unmask interrupts. It has to be done from each CPU */ 35096b125d63SGregory CLEMENT on_each_cpu(mvneta_percpu_unmask_interrupt, pp, true); 35106b125d63SGregory CLEMENT 3511898b2970SStas Sergeev mvreg_write(pp, MVNETA_INTR_MISC_MASK, 3512898b2970SStas Sergeev MVNETA_CAUSE_PHY_STATUS_CHANGE | 3513856b2cc5SRussell King MVNETA_CAUSE_LINK_CHANGE); 3514c5aff182SThomas Petazzoni 3515503f9aa9SRussell King phylink_start(pp->phylink); 3516c5aff182SThomas Petazzoni netif_tx_start_all_queues(pp->dev); 3517c5aff182SThomas Petazzoni } 3518c5aff182SThomas Petazzoni 3519c5aff182SThomas Petazzoni static void mvneta_stop_dev(struct mvneta_port *pp) 3520c5aff182SThomas Petazzoni { 352112bb03b4SMaxime Ripard unsigned int cpu; 352212bb03b4SMaxime Ripard 3523503f9aa9SRussell King phylink_stop(pp->phylink); 3524c5aff182SThomas Petazzoni 35252636ac3cSMarcin Wojtas if (!pp->neta_armada3700) { 3526129219e4SGregory CLEMENT for_each_online_cpu(cpu) { 35272636ac3cSMarcin Wojtas struct mvneta_pcpu_port *port = 35282636ac3cSMarcin Wojtas per_cpu_ptr(pp->ports, cpu); 352912bb03b4SMaxime Ripard 353012bb03b4SMaxime Ripard napi_disable(&port->napi); 353112bb03b4SMaxime Ripard } 35322636ac3cSMarcin Wojtas } else { 35332636ac3cSMarcin Wojtas napi_disable(&pp->napi); 35342636ac3cSMarcin Wojtas } 3535c5aff182SThomas Petazzoni 3536c5aff182SThomas Petazzoni netif_carrier_off(pp->dev); 3537c5aff182SThomas Petazzoni 3538c5aff182SThomas Petazzoni mvneta_port_down(pp); 3539c5aff182SThomas Petazzoni netif_tx_stop_all_queues(pp->dev); 3540c5aff182SThomas Petazzoni 3541c5aff182SThomas Petazzoni /* Stop the port activity */ 3542c5aff182SThomas Petazzoni mvneta_port_disable(pp); 3543c5aff182SThomas Petazzoni 3544c5aff182SThomas Petazzoni /* Clear all ethernet port interrupts */ 3545db488c10SGregory CLEMENT on_each_cpu(mvneta_percpu_clear_intr_cause, pp, true); 3546c5aff182SThomas Petazzoni 3547c5aff182SThomas Petazzoni /* Mask all ethernet port interrupts */ 3548db488c10SGregory CLEMENT on_each_cpu(mvneta_percpu_mask_interrupt, pp, true); 3549c5aff182SThomas Petazzoni 3550c5aff182SThomas Petazzoni mvneta_tx_reset(pp); 3551c5aff182SThomas Petazzoni mvneta_rx_reset(pp); 3552a10c1c81SRussell King 3553a10c1c81SRussell King WARN_ON(phy_power_off(pp->comphy)); 3554c5aff182SThomas Petazzoni } 3555c5aff182SThomas Petazzoni 3556db5dd0dbSMarcin Wojtas static void mvneta_percpu_enable(void *arg) 3557db5dd0dbSMarcin Wojtas { 3558db5dd0dbSMarcin Wojtas struct mvneta_port *pp = arg; 3559db5dd0dbSMarcin Wojtas 3560db5dd0dbSMarcin Wojtas enable_percpu_irq(pp->dev->irq, IRQ_TYPE_NONE); 3561db5dd0dbSMarcin Wojtas } 3562db5dd0dbSMarcin Wojtas 3563db5dd0dbSMarcin Wojtas static void mvneta_percpu_disable(void *arg) 3564db5dd0dbSMarcin Wojtas { 3565db5dd0dbSMarcin Wojtas struct mvneta_port *pp = arg; 3566db5dd0dbSMarcin Wojtas 3567db5dd0dbSMarcin Wojtas disable_percpu_irq(pp->dev->irq); 3568db5dd0dbSMarcin Wojtas } 3569db5dd0dbSMarcin Wojtas 3570c5aff182SThomas Petazzoni /* Change the device mtu */ 3571c5aff182SThomas Petazzoni static int mvneta_change_mtu(struct net_device *dev, int mtu) 3572c5aff182SThomas Petazzoni { 3573c5aff182SThomas Petazzoni struct mvneta_port *pp = netdev_priv(dev); 3574c5aff182SThomas Petazzoni int ret; 3575c5aff182SThomas Petazzoni 35765777987eSJarod Wilson if (!IS_ALIGNED(MVNETA_RX_PKT_SIZE(mtu), 8)) { 35775777987eSJarod Wilson netdev_info(dev, "Illegal MTU value %d, rounding to %d\n", 35785777987eSJarod Wilson mtu, ALIGN(MVNETA_RX_PKT_SIZE(mtu), 8)); 35795777987eSJarod Wilson mtu = ALIGN(MVNETA_RX_PKT_SIZE(mtu), 8); 35805777987eSJarod Wilson } 3581c5aff182SThomas Petazzoni 35820db51da7SLorenzo Bianconi if (pp->xdp_prog && mtu > MVNETA_MAX_RX_BUF_SIZE) { 35830db51da7SLorenzo Bianconi netdev_info(dev, "Illegal MTU value %d for XDP mode\n", mtu); 35840db51da7SLorenzo Bianconi return -EINVAL; 35850db51da7SLorenzo Bianconi } 35860db51da7SLorenzo Bianconi 3587c5aff182SThomas Petazzoni dev->mtu = mtu; 3588c5aff182SThomas Petazzoni 3589b65657fcSSimon Guinot if (!netif_running(dev)) { 3590dc35a10fSMarcin Wojtas if (pp->bm_priv) 3591dc35a10fSMarcin Wojtas mvneta_bm_update_mtu(pp, mtu); 3592dc35a10fSMarcin Wojtas 3593b65657fcSSimon Guinot netdev_update_features(dev); 3594c5aff182SThomas Petazzoni return 0; 3595b65657fcSSimon Guinot } 3596c5aff182SThomas Petazzoni 35976a20c175SThomas Petazzoni /* The interface is running, so we have to force a 3598a92dbd96SEzequiel Garcia * reallocation of the queues 3599c5aff182SThomas Petazzoni */ 3600c5aff182SThomas Petazzoni mvneta_stop_dev(pp); 3601db5dd0dbSMarcin Wojtas on_each_cpu(mvneta_percpu_disable, pp, true); 3602c5aff182SThomas Petazzoni 3603c5aff182SThomas Petazzoni mvneta_cleanup_txqs(pp); 3604c5aff182SThomas Petazzoni mvneta_cleanup_rxqs(pp); 3605c5aff182SThomas Petazzoni 3606dc35a10fSMarcin Wojtas if (pp->bm_priv) 3607dc35a10fSMarcin Wojtas mvneta_bm_update_mtu(pp, mtu); 3608dc35a10fSMarcin Wojtas 3609a92dbd96SEzequiel Garcia pp->pkt_size = MVNETA_RX_PKT_SIZE(dev->mtu); 3610c5aff182SThomas Petazzoni 3611c5aff182SThomas Petazzoni ret = mvneta_setup_rxqs(pp); 3612c5aff182SThomas Petazzoni if (ret) { 3613a92dbd96SEzequiel Garcia netdev_err(dev, "unable to setup rxqs after MTU change\n"); 3614c5aff182SThomas Petazzoni return ret; 3615c5aff182SThomas Petazzoni } 3616c5aff182SThomas Petazzoni 3617a92dbd96SEzequiel Garcia ret = mvneta_setup_txqs(pp); 3618a92dbd96SEzequiel Garcia if (ret) { 3619a92dbd96SEzequiel Garcia netdev_err(dev, "unable to setup txqs after MTU change\n"); 3620a92dbd96SEzequiel Garcia return ret; 3621a92dbd96SEzequiel Garcia } 3622c5aff182SThomas Petazzoni 3623db5dd0dbSMarcin Wojtas on_each_cpu(mvneta_percpu_enable, pp, true); 3624c5aff182SThomas Petazzoni mvneta_start_dev(pp); 3625c5aff182SThomas Petazzoni 3626b65657fcSSimon Guinot netdev_update_features(dev); 3627b65657fcSSimon Guinot 3628c5aff182SThomas Petazzoni return 0; 3629c5aff182SThomas Petazzoni } 3630c5aff182SThomas Petazzoni 3631b65657fcSSimon Guinot static netdev_features_t mvneta_fix_features(struct net_device *dev, 3632b65657fcSSimon Guinot netdev_features_t features) 3633b65657fcSSimon Guinot { 3634b65657fcSSimon Guinot struct mvneta_port *pp = netdev_priv(dev); 3635b65657fcSSimon Guinot 3636b65657fcSSimon Guinot if (pp->tx_csum_limit && dev->mtu > pp->tx_csum_limit) { 3637b65657fcSSimon Guinot features &= ~(NETIF_F_IP_CSUM | NETIF_F_TSO); 3638b65657fcSSimon Guinot netdev_info(dev, 3639b65657fcSSimon Guinot "Disable IP checksum for MTU greater than %dB\n", 3640b65657fcSSimon Guinot pp->tx_csum_limit); 3641b65657fcSSimon Guinot } 3642b65657fcSSimon Guinot 3643b65657fcSSimon Guinot return features; 3644b65657fcSSimon Guinot } 3645b65657fcSSimon Guinot 36468cc3e439SThomas Petazzoni /* Get mac address */ 36478cc3e439SThomas Petazzoni static void mvneta_get_mac_addr(struct mvneta_port *pp, unsigned char *addr) 36488cc3e439SThomas Petazzoni { 36498cc3e439SThomas Petazzoni u32 mac_addr_l, mac_addr_h; 36508cc3e439SThomas Petazzoni 36518cc3e439SThomas Petazzoni mac_addr_l = mvreg_read(pp, MVNETA_MAC_ADDR_LOW); 36528cc3e439SThomas Petazzoni mac_addr_h = mvreg_read(pp, MVNETA_MAC_ADDR_HIGH); 36538cc3e439SThomas Petazzoni addr[0] = (mac_addr_h >> 24) & 0xFF; 36548cc3e439SThomas Petazzoni addr[1] = (mac_addr_h >> 16) & 0xFF; 36558cc3e439SThomas Petazzoni addr[2] = (mac_addr_h >> 8) & 0xFF; 36568cc3e439SThomas Petazzoni addr[3] = mac_addr_h & 0xFF; 36578cc3e439SThomas Petazzoni addr[4] = (mac_addr_l >> 8) & 0xFF; 36588cc3e439SThomas Petazzoni addr[5] = mac_addr_l & 0xFF; 36598cc3e439SThomas Petazzoni } 36608cc3e439SThomas Petazzoni 3661c5aff182SThomas Petazzoni /* Handle setting mac address */ 3662c5aff182SThomas Petazzoni static int mvneta_set_mac_addr(struct net_device *dev, void *addr) 3663c5aff182SThomas Petazzoni { 3664c5aff182SThomas Petazzoni struct mvneta_port *pp = netdev_priv(dev); 3665e68de360SEzequiel Garcia struct sockaddr *sockaddr = addr; 3666e68de360SEzequiel Garcia int ret; 3667c5aff182SThomas Petazzoni 3668e68de360SEzequiel Garcia ret = eth_prepare_mac_addr_change(dev, addr); 3669e68de360SEzequiel Garcia if (ret < 0) 3670e68de360SEzequiel Garcia return ret; 3671c5aff182SThomas Petazzoni /* Remove previous address table entry */ 3672c5aff182SThomas Petazzoni mvneta_mac_addr_set(pp, dev->dev_addr, -1); 3673c5aff182SThomas Petazzoni 3674c5aff182SThomas Petazzoni /* Set new addr in hw */ 367590b74c01SGregory CLEMENT mvneta_mac_addr_set(pp, sockaddr->sa_data, pp->rxq_def); 3676c5aff182SThomas Petazzoni 3677e68de360SEzequiel Garcia eth_commit_mac_addr_change(dev, addr); 3678c5aff182SThomas Petazzoni return 0; 3679c5aff182SThomas Petazzoni } 3680c5aff182SThomas Petazzoni 368144cc27e4SIoana Ciornei static void mvneta_validate(struct phylink_config *config, 368244cc27e4SIoana Ciornei unsigned long *supported, 3683503f9aa9SRussell King struct phylink_link_state *state) 3684503f9aa9SRussell King { 368544cc27e4SIoana Ciornei struct net_device *ndev = to_net_dev(config->dev); 3686a10c1c81SRussell King struct mvneta_port *pp = netdev_priv(ndev); 3687503f9aa9SRussell King __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, }; 3688503f9aa9SRussell King 368922f4bf8aSRussell King /* We only support QSGMII, SGMII, 802.3z and RGMII modes */ 3690503f9aa9SRussell King if (state->interface != PHY_INTERFACE_MODE_NA && 3691503f9aa9SRussell King state->interface != PHY_INTERFACE_MODE_QSGMII && 3692503f9aa9SRussell King state->interface != PHY_INTERFACE_MODE_SGMII && 369322f4bf8aSRussell King !phy_interface_mode_is_8023z(state->interface) && 3694503f9aa9SRussell King !phy_interface_mode_is_rgmii(state->interface)) { 3695503f9aa9SRussell King bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS); 3696503f9aa9SRussell King return; 3697503f9aa9SRussell King } 3698503f9aa9SRussell King 3699503f9aa9SRussell King /* Allow all the expected bits */ 3700503f9aa9SRussell King phylink_set(mask, Autoneg); 3701503f9aa9SRussell King phylink_set_port_modes(mask); 3702503f9aa9SRussell King 37034932a918SRussell King /* Asymmetric pause is unsupported */ 37044932a918SRussell King phylink_set(mask, Pause); 3705da58a931SMaxime Chevallier 370683e65df6SMaxime Chevallier /* Half-duplex at speeds higher than 100Mbit is unsupported */ 3707a10c1c81SRussell King if (pp->comphy || state->interface != PHY_INTERFACE_MODE_2500BASEX) { 3708503f9aa9SRussell King phylink_set(mask, 1000baseT_Full); 3709503f9aa9SRussell King phylink_set(mask, 1000baseX_Full); 3710a10c1c81SRussell King } 3711a10c1c81SRussell King if (pp->comphy || state->interface == PHY_INTERFACE_MODE_2500BASEX) { 3712eda3d1b0SMaxime Chevallier phylink_set(mask, 2500baseT_Full); 3713a10c1c81SRussell King phylink_set(mask, 2500baseX_Full); 3714a10c1c81SRussell King } 371522f4bf8aSRussell King 371622f4bf8aSRussell King if (!phy_interface_mode_is_8023z(state->interface)) { 371722f4bf8aSRussell King /* 10M and 100M are only supported in non-802.3z mode */ 3718503f9aa9SRussell King phylink_set(mask, 10baseT_Half); 3719503f9aa9SRussell King phylink_set(mask, 10baseT_Full); 3720503f9aa9SRussell King phylink_set(mask, 100baseT_Half); 3721503f9aa9SRussell King phylink_set(mask, 100baseT_Full); 372222f4bf8aSRussell King } 3723503f9aa9SRussell King 3724503f9aa9SRussell King bitmap_and(supported, supported, mask, 3725503f9aa9SRussell King __ETHTOOL_LINK_MODE_MASK_NBITS); 3726503f9aa9SRussell King bitmap_and(state->advertising, state->advertising, mask, 3727503f9aa9SRussell King __ETHTOOL_LINK_MODE_MASK_NBITS); 3728a10c1c81SRussell King 3729a10c1c81SRussell King /* We can only operate at 2500BaseX or 1000BaseX. If requested 3730a10c1c81SRussell King * to advertise both, only report advertising at 2500BaseX. 3731a10c1c81SRussell King */ 3732a10c1c81SRussell King phylink_helper_basex_speed(state); 3733503f9aa9SRussell King } 3734503f9aa9SRussell King 3735d46b7e4fSRussell King static void mvneta_mac_pcs_get_state(struct phylink_config *config, 3736503f9aa9SRussell King struct phylink_link_state *state) 3737c5aff182SThomas Petazzoni { 373844cc27e4SIoana Ciornei struct net_device *ndev = to_net_dev(config->dev); 3739c5aff182SThomas Petazzoni struct mvneta_port *pp = netdev_priv(ndev); 3740503f9aa9SRussell King u32 gmac_stat; 3741c5aff182SThomas Petazzoni 3742503f9aa9SRussell King gmac_stat = mvreg_read(pp, MVNETA_GMAC_STATUS); 3743503f9aa9SRussell King 3744503f9aa9SRussell King if (gmac_stat & MVNETA_GMAC_SPEED_1000) 3745a10c1c81SRussell King state->speed = 3746a10c1c81SRussell King state->interface == PHY_INTERFACE_MODE_2500BASEX ? 3747a10c1c81SRussell King SPEED_2500 : SPEED_1000; 3748503f9aa9SRussell King else if (gmac_stat & MVNETA_GMAC_SPEED_100) 3749503f9aa9SRussell King state->speed = SPEED_100; 3750503f9aa9SRussell King else 3751503f9aa9SRussell King state->speed = SPEED_10; 3752503f9aa9SRussell King 3753503f9aa9SRussell King state->an_complete = !!(gmac_stat & MVNETA_GMAC_AN_COMPLETE); 3754503f9aa9SRussell King state->link = !!(gmac_stat & MVNETA_GMAC_LINK_UP); 3755503f9aa9SRussell King state->duplex = !!(gmac_stat & MVNETA_GMAC_FULL_DUPLEX); 3756503f9aa9SRussell King 3757503f9aa9SRussell King state->pause = 0; 37584932a918SRussell King if (gmac_stat & MVNETA_GMAC_RX_FLOW_CTRL_ENABLE) 37594932a918SRussell King state->pause |= MLO_PAUSE_RX; 37604932a918SRussell King if (gmac_stat & MVNETA_GMAC_TX_FLOW_CTRL_ENABLE) 37614932a918SRussell King state->pause |= MLO_PAUSE_TX; 3762503f9aa9SRussell King } 3763503f9aa9SRussell King 376444cc27e4SIoana Ciornei static void mvneta_mac_an_restart(struct phylink_config *config) 376522f4bf8aSRussell King { 376644cc27e4SIoana Ciornei struct net_device *ndev = to_net_dev(config->dev); 376722f4bf8aSRussell King struct mvneta_port *pp = netdev_priv(ndev); 376822f4bf8aSRussell King u32 gmac_an = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG); 376922f4bf8aSRussell King 377022f4bf8aSRussell King mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, 377122f4bf8aSRussell King gmac_an | MVNETA_GMAC_INBAND_RESTART_AN); 377222f4bf8aSRussell King mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, 377322f4bf8aSRussell King gmac_an & ~MVNETA_GMAC_INBAND_RESTART_AN); 377422f4bf8aSRussell King } 377522f4bf8aSRussell King 377644cc27e4SIoana Ciornei static void mvneta_mac_config(struct phylink_config *config, unsigned int mode, 3777503f9aa9SRussell King const struct phylink_link_state *state) 3778503f9aa9SRussell King { 377944cc27e4SIoana Ciornei struct net_device *ndev = to_net_dev(config->dev); 3780503f9aa9SRussell King struct mvneta_port *pp = netdev_priv(ndev); 378122f4bf8aSRussell King u32 new_ctrl0, gmac_ctrl0 = mvreg_read(pp, MVNETA_GMAC_CTRL_0); 3782503f9aa9SRussell King u32 new_ctrl2, gmac_ctrl2 = mvreg_read(pp, MVNETA_GMAC_CTRL_2); 3783da58a931SMaxime Chevallier u32 new_ctrl4, gmac_ctrl4 = mvreg_read(pp, MVNETA_GMAC_CTRL_4); 3784503f9aa9SRussell King u32 new_clk, gmac_clk = mvreg_read(pp, MVNETA_GMAC_CLOCK_DIVIDER); 3785503f9aa9SRussell King u32 new_an, gmac_an = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG); 3786503f9aa9SRussell King 378722f4bf8aSRussell King new_ctrl0 = gmac_ctrl0 & ~MVNETA_GMAC0_PORT_1000BASE_X; 378832699954SRussell King new_ctrl2 = gmac_ctrl2 & ~(MVNETA_GMAC2_INBAND_AN_ENABLE | 378932699954SRussell King MVNETA_GMAC2_PORT_RESET); 3790da58a931SMaxime Chevallier new_ctrl4 = gmac_ctrl4 & ~(MVNETA_GMAC4_SHORT_PREAMBLE_ENABLE); 3791503f9aa9SRussell King new_clk = gmac_clk & ~MVNETA_GMAC_1MS_CLOCK_ENABLE; 3792503f9aa9SRussell King new_an = gmac_an & ~(MVNETA_GMAC_INBAND_AN_ENABLE | 3793503f9aa9SRussell King MVNETA_GMAC_INBAND_RESTART_AN | 3794503f9aa9SRussell King MVNETA_GMAC_CONFIG_MII_SPEED | 3795c5aff182SThomas Petazzoni MVNETA_GMAC_CONFIG_GMII_SPEED | 3796503f9aa9SRussell King MVNETA_GMAC_AN_SPEED_EN | 379722f4bf8aSRussell King MVNETA_GMAC_ADVERT_SYM_FLOW_CTRL | 379822f4bf8aSRussell King MVNETA_GMAC_CONFIG_FLOW_CTRL | 3799503f9aa9SRussell King MVNETA_GMAC_AN_FLOW_CTRL_EN | 3800503f9aa9SRussell King MVNETA_GMAC_CONFIG_FULL_DUPLEX | 3801503f9aa9SRussell King MVNETA_GMAC_AN_DUPLEX_EN); 3802c5aff182SThomas Petazzoni 380332699954SRussell King /* Even though it might look weird, when we're configured in 380432699954SRussell King * SGMII or QSGMII mode, the RGMII bit needs to be set. 380532699954SRussell King */ 380632699954SRussell King new_ctrl2 |= MVNETA_GMAC2_PORT_RGMII; 380732699954SRussell King 380832699954SRussell King if (state->interface == PHY_INTERFACE_MODE_QSGMII || 380922f4bf8aSRussell King state->interface == PHY_INTERFACE_MODE_SGMII || 381022f4bf8aSRussell King phy_interface_mode_is_8023z(state->interface)) 381132699954SRussell King new_ctrl2 |= MVNETA_GMAC2_PCS_ENABLE; 381232699954SRussell King 38134932a918SRussell King if (phylink_test(state->advertising, Pause)) 38144932a918SRussell King new_an |= MVNETA_GMAC_ADVERT_SYM_FLOW_CTRL; 38154932a918SRussell King if (state->pause & MLO_PAUSE_TXRX_MASK) 38164932a918SRussell King new_an |= MVNETA_GMAC_CONFIG_FLOW_CTRL; 38174932a918SRussell King 3818503f9aa9SRussell King if (!phylink_autoneg_inband(mode)) { 3819503f9aa9SRussell King /* Phy or fixed speed */ 3820503f9aa9SRussell King if (state->duplex) 3821503f9aa9SRussell King new_an |= MVNETA_GMAC_CONFIG_FULL_DUPLEX; 3822c5aff182SThomas Petazzoni 3823da58a931SMaxime Chevallier if (state->speed == SPEED_1000 || state->speed == SPEED_2500) 3824503f9aa9SRussell King new_an |= MVNETA_GMAC_CONFIG_GMII_SPEED; 3825503f9aa9SRussell King else if (state->speed == SPEED_100) 3826503f9aa9SRussell King new_an |= MVNETA_GMAC_CONFIG_MII_SPEED; 382722f4bf8aSRussell King } else if (state->interface == PHY_INTERFACE_MODE_SGMII) { 3828503f9aa9SRussell King /* SGMII mode receives the state from the PHY */ 3829503f9aa9SRussell King new_ctrl2 |= MVNETA_GMAC2_INBAND_AN_ENABLE; 3830503f9aa9SRussell King new_clk |= MVNETA_GMAC_1MS_CLOCK_ENABLE; 3831503f9aa9SRussell King new_an = (new_an & ~(MVNETA_GMAC_FORCE_LINK_DOWN | 3832503f9aa9SRussell King MVNETA_GMAC_FORCE_LINK_PASS)) | 3833503f9aa9SRussell King MVNETA_GMAC_INBAND_AN_ENABLE | 3834503f9aa9SRussell King MVNETA_GMAC_AN_SPEED_EN | 3835503f9aa9SRussell King MVNETA_GMAC_AN_DUPLEX_EN; 383622f4bf8aSRussell King } else { 383722f4bf8aSRussell King /* 802.3z negotiation - only 1000base-X */ 383822f4bf8aSRussell King new_ctrl0 |= MVNETA_GMAC0_PORT_1000BASE_X; 383922f4bf8aSRussell King new_clk |= MVNETA_GMAC_1MS_CLOCK_ENABLE; 384022f4bf8aSRussell King new_an = (new_an & ~(MVNETA_GMAC_FORCE_LINK_DOWN | 384122f4bf8aSRussell King MVNETA_GMAC_FORCE_LINK_PASS)) | 384222f4bf8aSRussell King MVNETA_GMAC_INBAND_AN_ENABLE | 384322f4bf8aSRussell King MVNETA_GMAC_CONFIG_GMII_SPEED | 384422f4bf8aSRussell King /* The MAC only supports FD mode */ 384522f4bf8aSRussell King MVNETA_GMAC_CONFIG_FULL_DUPLEX; 38464932a918SRussell King 38474932a918SRussell King if (state->pause & MLO_PAUSE_AN && state->an_enabled) 38484932a918SRussell King new_an |= MVNETA_GMAC_AN_FLOW_CTRL_EN; 3849c5aff182SThomas Petazzoni } 3850c5aff182SThomas Petazzoni 3851503f9aa9SRussell King /* Armada 370 documentation says we can only change the port mode 3852503f9aa9SRussell King * and in-band enable when the link is down, so force it down 3853503f9aa9SRussell King * while making these changes. We also do this for GMAC_CTRL2 */ 385422f4bf8aSRussell King if ((new_ctrl0 ^ gmac_ctrl0) & MVNETA_GMAC0_PORT_1000BASE_X || 385522f4bf8aSRussell King (new_ctrl2 ^ gmac_ctrl2) & MVNETA_GMAC2_INBAND_AN_ENABLE || 3856503f9aa9SRussell King (new_an ^ gmac_an) & MVNETA_GMAC_INBAND_AN_ENABLE) { 3857503f9aa9SRussell King mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, 3858503f9aa9SRussell King (gmac_an & ~MVNETA_GMAC_FORCE_LINK_PASS) | 3859503f9aa9SRussell King MVNETA_GMAC_FORCE_LINK_DOWN); 3860503f9aa9SRussell King } 3861503f9aa9SRussell King 3862a10c1c81SRussell King 3863da58a931SMaxime Chevallier /* When at 2.5G, the link partner can send frames with shortened 3864da58a931SMaxime Chevallier * preambles. 3865da58a931SMaxime Chevallier */ 3866da58a931SMaxime Chevallier if (state->speed == SPEED_2500) 3867da58a931SMaxime Chevallier new_ctrl4 |= MVNETA_GMAC4_SHORT_PREAMBLE_ENABLE; 3868da58a931SMaxime Chevallier 3869031b922bSMarek Behún if (pp->comphy && pp->phy_interface != state->interface && 3870a10c1c81SRussell King (state->interface == PHY_INTERFACE_MODE_SGMII || 3871a10c1c81SRussell King state->interface == PHY_INTERFACE_MODE_1000BASEX || 3872031b922bSMarek Behún state->interface == PHY_INTERFACE_MODE_2500BASEX)) { 3873031b922bSMarek Behún pp->phy_interface = state->interface; 3874031b922bSMarek Behún 3875031b922bSMarek Behún WARN_ON(phy_power_off(pp->comphy)); 3876031b922bSMarek Behún WARN_ON(mvneta_comphy_init(pp)); 3877031b922bSMarek Behún } 3878a10c1c81SRussell King 387922f4bf8aSRussell King if (new_ctrl0 != gmac_ctrl0) 388022f4bf8aSRussell King mvreg_write(pp, MVNETA_GMAC_CTRL_0, new_ctrl0); 3881503f9aa9SRussell King if (new_ctrl2 != gmac_ctrl2) 3882503f9aa9SRussell King mvreg_write(pp, MVNETA_GMAC_CTRL_2, new_ctrl2); 3883da58a931SMaxime Chevallier if (new_ctrl4 != gmac_ctrl4) 3884da58a931SMaxime Chevallier mvreg_write(pp, MVNETA_GMAC_CTRL_4, new_ctrl4); 3885503f9aa9SRussell King if (new_clk != gmac_clk) 3886503f9aa9SRussell King mvreg_write(pp, MVNETA_GMAC_CLOCK_DIVIDER, new_clk); 3887503f9aa9SRussell King if (new_an != gmac_an) 3888503f9aa9SRussell King mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, new_an); 388932699954SRussell King 389032699954SRussell King if (gmac_ctrl2 & MVNETA_GMAC2_PORT_RESET) { 389132699954SRussell King while ((mvreg_read(pp, MVNETA_GMAC_CTRL_2) & 389232699954SRussell King MVNETA_GMAC2_PORT_RESET) != 0) 389332699954SRussell King continue; 389432699954SRussell King } 3895503f9aa9SRussell King } 3896503f9aa9SRussell King 38976d81f451SRussell King static void mvneta_set_eee(struct mvneta_port *pp, bool enable) 38986d81f451SRussell King { 38996d81f451SRussell King u32 lpi_ctl1; 39006d81f451SRussell King 39016d81f451SRussell King lpi_ctl1 = mvreg_read(pp, MVNETA_LPI_CTRL_1); 39026d81f451SRussell King if (enable) 39036d81f451SRussell King lpi_ctl1 |= MVNETA_LPI_REQUEST_ENABLE; 39046d81f451SRussell King else 39056d81f451SRussell King lpi_ctl1 &= ~MVNETA_LPI_REQUEST_ENABLE; 39066d81f451SRussell King mvreg_write(pp, MVNETA_LPI_CTRL_1, lpi_ctl1); 39076d81f451SRussell King } 39086d81f451SRussell King 390944cc27e4SIoana Ciornei static void mvneta_mac_link_down(struct phylink_config *config, 391044cc27e4SIoana Ciornei unsigned int mode, phy_interface_t interface) 3911fc548b99SRussell King { 391244cc27e4SIoana Ciornei struct net_device *ndev = to_net_dev(config->dev); 3913fc548b99SRussell King struct mvneta_port *pp = netdev_priv(ndev); 3914fc548b99SRussell King u32 val; 3915fc548b99SRussell King 3916503f9aa9SRussell King mvneta_port_down(pp); 3917503f9aa9SRussell King 3918503f9aa9SRussell King if (!phylink_autoneg_inband(mode)) { 3919fc548b99SRussell King val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG); 3920fc548b99SRussell King val &= ~MVNETA_GMAC_FORCE_LINK_PASS; 3921fc548b99SRussell King val |= MVNETA_GMAC_FORCE_LINK_DOWN; 3922fc548b99SRussell King mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val); 3923fc548b99SRussell King } 39246d81f451SRussell King 39256d81f451SRussell King pp->eee_active = false; 39266d81f451SRussell King mvneta_set_eee(pp, false); 3927fc548b99SRussell King } 3928fc548b99SRussell King 392944cc27e4SIoana Ciornei static void mvneta_mac_link_up(struct phylink_config *config, unsigned int mode, 3930c6ab3008SFlorian Fainelli phy_interface_t interface, 3931503f9aa9SRussell King struct phy_device *phy) 3932fc548b99SRussell King { 393344cc27e4SIoana Ciornei struct net_device *ndev = to_net_dev(config->dev); 3934fc548b99SRussell King struct mvneta_port *pp = netdev_priv(ndev); 3935fc548b99SRussell King u32 val; 3936fc548b99SRussell King 3937503f9aa9SRussell King if (!phylink_autoneg_inband(mode)) { 3938fc548b99SRussell King val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG); 3939fc548b99SRussell King val &= ~MVNETA_GMAC_FORCE_LINK_DOWN; 3940fc548b99SRussell King val |= MVNETA_GMAC_FORCE_LINK_PASS; 3941fc548b99SRussell King mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val); 3942fc548b99SRussell King } 3943fc548b99SRussell King 3944fc548b99SRussell King mvneta_port_up(pp); 39456d81f451SRussell King 39466d81f451SRussell King if (phy && pp->eee_enabled) { 39476d81f451SRussell King pp->eee_active = phy_init_eee(phy, 0) >= 0; 39486d81f451SRussell King mvneta_set_eee(pp, pp->eee_active && pp->tx_lpi_enabled); 39496d81f451SRussell King } 3950fc548b99SRussell King } 3951fc548b99SRussell King 3952503f9aa9SRussell King static const struct phylink_mac_ops mvneta_phylink_ops = { 3953503f9aa9SRussell King .validate = mvneta_validate, 3954d46b7e4fSRussell King .mac_pcs_get_state = mvneta_mac_pcs_get_state, 395522f4bf8aSRussell King .mac_an_restart = mvneta_mac_an_restart, 3956503f9aa9SRussell King .mac_config = mvneta_mac_config, 3957503f9aa9SRussell King .mac_link_down = mvneta_mac_link_down, 3958503f9aa9SRussell King .mac_link_up = mvneta_mac_link_up, 3959503f9aa9SRussell King }; 3960c5aff182SThomas Petazzoni 3961c5aff182SThomas Petazzoni static int mvneta_mdio_probe(struct mvneta_port *pp) 3962c5aff182SThomas Petazzoni { 396382960fffSJisheng Zhang struct ethtool_wolinfo wol = { .cmd = ETHTOOL_GWOL }; 3964503f9aa9SRussell King int err = phylink_of_phy_connect(pp->phylink, pp->dn, 0); 3965c5aff182SThomas Petazzoni 3966503f9aa9SRussell King if (err) 3967503f9aa9SRussell King netdev_err(pp->dev, "could not attach PHY: %d\n", err); 3968c5aff182SThomas Petazzoni 3969503f9aa9SRussell King phylink_ethtool_get_wol(pp->phylink, &wol); 397082960fffSJisheng Zhang device_set_wakeup_capable(&pp->dev->dev, !!wol.supported); 397182960fffSJisheng Zhang 3972503f9aa9SRussell King return err; 3973c5aff182SThomas Petazzoni } 3974c5aff182SThomas Petazzoni 3975c5aff182SThomas Petazzoni static void mvneta_mdio_remove(struct mvneta_port *pp) 3976c5aff182SThomas Petazzoni { 3977503f9aa9SRussell King phylink_disconnect_phy(pp->phylink); 3978c5aff182SThomas Petazzoni } 3979c5aff182SThomas Petazzoni 3980120cfa50SGregory CLEMENT /* Electing a CPU must be done in an atomic way: it should be done 3981120cfa50SGregory CLEMENT * after or before the removal/insertion of a CPU and this function is 3982120cfa50SGregory CLEMENT * not reentrant. 3983120cfa50SGregory CLEMENT */ 3984f8642885SMaxime Ripard static void mvneta_percpu_elect(struct mvneta_port *pp) 3985f8642885SMaxime Ripard { 3986cad5d847SGregory CLEMENT int elected_cpu = 0, max_cpu, cpu, i = 0; 3987f8642885SMaxime Ripard 3988cad5d847SGregory CLEMENT /* Use the cpu associated to the rxq when it is online, in all 3989cad5d847SGregory CLEMENT * the other cases, use the cpu 0 which can't be offline. 3990cad5d847SGregory CLEMENT */ 3991cad5d847SGregory CLEMENT if (cpu_online(pp->rxq_def)) 3992cad5d847SGregory CLEMENT elected_cpu = pp->rxq_def; 3993cad5d847SGregory CLEMENT 39942dcf75e2SGregory CLEMENT max_cpu = num_present_cpus(); 3995f8642885SMaxime Ripard 3996f8642885SMaxime Ripard for_each_online_cpu(cpu) { 39972dcf75e2SGregory CLEMENT int rxq_map = 0, txq_map = 0; 39982dcf75e2SGregory CLEMENT int rxq; 39992dcf75e2SGregory CLEMENT 40002dcf75e2SGregory CLEMENT for (rxq = 0; rxq < rxq_number; rxq++) 40012dcf75e2SGregory CLEMENT if ((rxq % max_cpu) == cpu) 40022dcf75e2SGregory CLEMENT rxq_map |= MVNETA_CPU_RXQ_ACCESS(rxq); 40032dcf75e2SGregory CLEMENT 4004cad5d847SGregory CLEMENT if (cpu == elected_cpu) 400550bf8cb6SGregory CLEMENT /* Map the default receive queue queue to the 400650bf8cb6SGregory CLEMENT * elected CPU 4007f8642885SMaxime Ripard */ 40082dcf75e2SGregory CLEMENT rxq_map |= MVNETA_CPU_RXQ_ACCESS(pp->rxq_def); 400950bf8cb6SGregory CLEMENT 401050bf8cb6SGregory CLEMENT /* We update the TX queue map only if we have one 401150bf8cb6SGregory CLEMENT * queue. In this case we associate the TX queue to 401250bf8cb6SGregory CLEMENT * the CPU bound to the default RX queue 401350bf8cb6SGregory CLEMENT */ 401450bf8cb6SGregory CLEMENT if (txq_number == 1) 4015cad5d847SGregory CLEMENT txq_map = (cpu == elected_cpu) ? 401650bf8cb6SGregory CLEMENT MVNETA_CPU_TXQ_ACCESS(1) : 0; 401750bf8cb6SGregory CLEMENT else 401850bf8cb6SGregory CLEMENT txq_map = mvreg_read(pp, MVNETA_CPU_MAP(cpu)) & 401950bf8cb6SGregory CLEMENT MVNETA_CPU_TXQ_ACCESS_ALL_MASK; 402050bf8cb6SGregory CLEMENT 40212dcf75e2SGregory CLEMENT mvreg_write(pp, MVNETA_CPU_MAP(cpu), rxq_map | txq_map); 40222dcf75e2SGregory CLEMENT 40232dcf75e2SGregory CLEMENT /* Update the interrupt mask on each CPU according the 40242dcf75e2SGregory CLEMENT * new mapping 40252dcf75e2SGregory CLEMENT */ 40262dcf75e2SGregory CLEMENT smp_call_function_single(cpu, mvneta_percpu_unmask_interrupt, 4027f8642885SMaxime Ripard pp, true); 4028f8642885SMaxime Ripard i++; 40292dcf75e2SGregory CLEMENT 4030f8642885SMaxime Ripard } 4031f8642885SMaxime Ripard }; 4032f8642885SMaxime Ripard 403384a3f4dbSSebastian Andrzej Siewior static int mvneta_cpu_online(unsigned int cpu, struct hlist_node *node) 4034f8642885SMaxime Ripard { 403584a3f4dbSSebastian Andrzej Siewior int other_cpu; 403684a3f4dbSSebastian Andrzej Siewior struct mvneta_port *pp = hlist_entry_safe(node, struct mvneta_port, 403784a3f4dbSSebastian Andrzej Siewior node_online); 4038f8642885SMaxime Ripard struct mvneta_pcpu_port *port = per_cpu_ptr(pp->ports, cpu); 4039f8642885SMaxime Ripard 404084a3f4dbSSebastian Andrzej Siewior 4041120cfa50SGregory CLEMENT spin_lock(&pp->lock); 404284a3f4dbSSebastian Andrzej Siewior /* 404384a3f4dbSSebastian Andrzej Siewior * Configuring the driver for a new CPU while the driver is 404484a3f4dbSSebastian Andrzej Siewior * stopping is racy, so just avoid it. 4045120cfa50SGregory CLEMENT */ 4046120cfa50SGregory CLEMENT if (pp->is_stopped) { 4047120cfa50SGregory CLEMENT spin_unlock(&pp->lock); 404884a3f4dbSSebastian Andrzej Siewior return 0; 4049120cfa50SGregory CLEMENT } 4050f8642885SMaxime Ripard netif_tx_stop_all_queues(pp->dev); 4051f8642885SMaxime Ripard 405284a3f4dbSSebastian Andrzej Siewior /* 405384a3f4dbSSebastian Andrzej Siewior * We have to synchronise on tha napi of each CPU except the one 405484a3f4dbSSebastian Andrzej Siewior * just being woken up 4055f8642885SMaxime Ripard */ 4056f8642885SMaxime Ripard for_each_online_cpu(other_cpu) { 4057f8642885SMaxime Ripard if (other_cpu != cpu) { 4058f8642885SMaxime Ripard struct mvneta_pcpu_port *other_port = 4059f8642885SMaxime Ripard per_cpu_ptr(pp->ports, other_cpu); 4060f8642885SMaxime Ripard 4061f8642885SMaxime Ripard napi_synchronize(&other_port->napi); 4062f8642885SMaxime Ripard } 4063f8642885SMaxime Ripard } 4064f8642885SMaxime Ripard 4065f8642885SMaxime Ripard /* Mask all ethernet port interrupts */ 4066db488c10SGregory CLEMENT on_each_cpu(mvneta_percpu_mask_interrupt, pp, true); 4067f8642885SMaxime Ripard napi_enable(&port->napi); 4068f8642885SMaxime Ripard 406984a3f4dbSSebastian Andrzej Siewior /* 407084a3f4dbSSebastian Andrzej Siewior * Enable per-CPU interrupts on the CPU that is 40712dcf75e2SGregory CLEMENT * brought up. 40722dcf75e2SGregory CLEMENT */ 40730e28bf93SAnna-Maria Gleixner mvneta_percpu_enable(pp); 40742dcf75e2SGregory CLEMENT 407584a3f4dbSSebastian Andrzej Siewior /* 407684a3f4dbSSebastian Andrzej Siewior * Enable per-CPU interrupt on the one CPU we care 4077f8642885SMaxime Ripard * about. 4078f8642885SMaxime Ripard */ 4079f8642885SMaxime Ripard mvneta_percpu_elect(pp); 4080f8642885SMaxime Ripard 4081db488c10SGregory CLEMENT /* Unmask all ethernet port interrupts */ 4082db488c10SGregory CLEMENT on_each_cpu(mvneta_percpu_unmask_interrupt, pp, true); 4083f8642885SMaxime Ripard mvreg_write(pp, MVNETA_INTR_MISC_MASK, 4084f8642885SMaxime Ripard MVNETA_CAUSE_PHY_STATUS_CHANGE | 4085856b2cc5SRussell King MVNETA_CAUSE_LINK_CHANGE); 4086f8642885SMaxime Ripard netif_tx_start_all_queues(pp->dev); 4087120cfa50SGregory CLEMENT spin_unlock(&pp->lock); 408884a3f4dbSSebastian Andrzej Siewior return 0; 408984a3f4dbSSebastian Andrzej Siewior } 409084a3f4dbSSebastian Andrzej Siewior 409184a3f4dbSSebastian Andrzej Siewior static int mvneta_cpu_down_prepare(unsigned int cpu, struct hlist_node *node) 409284a3f4dbSSebastian Andrzej Siewior { 409384a3f4dbSSebastian Andrzej Siewior struct mvneta_port *pp = hlist_entry_safe(node, struct mvneta_port, 409484a3f4dbSSebastian Andrzej Siewior node_online); 409584a3f4dbSSebastian Andrzej Siewior struct mvneta_pcpu_port *port = per_cpu_ptr(pp->ports, cpu); 409684a3f4dbSSebastian Andrzej Siewior 409784a3f4dbSSebastian Andrzej Siewior /* 409884a3f4dbSSebastian Andrzej Siewior * Thanks to this lock we are sure that any pending cpu election is 409984a3f4dbSSebastian Andrzej Siewior * done. 41005888511eSGregory CLEMENT */ 41015888511eSGregory CLEMENT spin_lock(&pp->lock); 4102f8642885SMaxime Ripard /* Mask all ethernet port interrupts */ 4103db488c10SGregory CLEMENT on_each_cpu(mvneta_percpu_mask_interrupt, pp, true); 41045888511eSGregory CLEMENT spin_unlock(&pp->lock); 4105f8642885SMaxime Ripard 4106f8642885SMaxime Ripard napi_synchronize(&port->napi); 4107f8642885SMaxime Ripard napi_disable(&port->napi); 410884a3f4dbSSebastian Andrzej Siewior /* Disable per-CPU interrupts on the CPU that is brought down. */ 41090e28bf93SAnna-Maria Gleixner mvneta_percpu_disable(pp); 411084a3f4dbSSebastian Andrzej Siewior return 0; 411184a3f4dbSSebastian Andrzej Siewior } 4112f8642885SMaxime Ripard 411384a3f4dbSSebastian Andrzej Siewior static int mvneta_cpu_dead(unsigned int cpu, struct hlist_node *node) 411484a3f4dbSSebastian Andrzej Siewior { 411584a3f4dbSSebastian Andrzej Siewior struct mvneta_port *pp = hlist_entry_safe(node, struct mvneta_port, 411684a3f4dbSSebastian Andrzej Siewior node_dead); 411784a3f4dbSSebastian Andrzej Siewior 4118f8642885SMaxime Ripard /* Check if a new CPU must be elected now this on is down */ 4119120cfa50SGregory CLEMENT spin_lock(&pp->lock); 4120f8642885SMaxime Ripard mvneta_percpu_elect(pp); 4121120cfa50SGregory CLEMENT spin_unlock(&pp->lock); 4122f8642885SMaxime Ripard /* Unmask all ethernet port interrupts */ 4123db488c10SGregory CLEMENT on_each_cpu(mvneta_percpu_unmask_interrupt, pp, true); 4124f8642885SMaxime Ripard mvreg_write(pp, MVNETA_INTR_MISC_MASK, 4125f8642885SMaxime Ripard MVNETA_CAUSE_PHY_STATUS_CHANGE | 4126856b2cc5SRussell King MVNETA_CAUSE_LINK_CHANGE); 4127f8642885SMaxime Ripard netif_tx_start_all_queues(pp->dev); 412884a3f4dbSSebastian Andrzej Siewior return 0; 4129f8642885SMaxime Ripard } 4130f8642885SMaxime Ripard 4131c5aff182SThomas Petazzoni static int mvneta_open(struct net_device *dev) 4132c5aff182SThomas Petazzoni { 4133c5aff182SThomas Petazzoni struct mvneta_port *pp = netdev_priv(dev); 41346b125d63SGregory CLEMENT int ret; 4135c5aff182SThomas Petazzoni 4136c5aff182SThomas Petazzoni pp->pkt_size = MVNETA_RX_PKT_SIZE(pp->dev->mtu); 4137c5aff182SThomas Petazzoni 4138c5aff182SThomas Petazzoni ret = mvneta_setup_rxqs(pp); 4139c5aff182SThomas Petazzoni if (ret) 4140c5aff182SThomas Petazzoni return ret; 4141c5aff182SThomas Petazzoni 4142c5aff182SThomas Petazzoni ret = mvneta_setup_txqs(pp); 4143c5aff182SThomas Petazzoni if (ret) 4144c5aff182SThomas Petazzoni goto err_cleanup_rxqs; 4145c5aff182SThomas Petazzoni 4146c5aff182SThomas Petazzoni /* Connect to port interrupt line */ 41472636ac3cSMarcin Wojtas if (pp->neta_armada3700) 41482636ac3cSMarcin Wojtas ret = request_irq(pp->dev->irq, mvneta_isr, 0, 41492636ac3cSMarcin Wojtas dev->name, pp); 41502636ac3cSMarcin Wojtas else 41512636ac3cSMarcin Wojtas ret = request_percpu_irq(pp->dev->irq, mvneta_percpu_isr, 41522636ac3cSMarcin Wojtas dev->name, pp->ports); 4153c5aff182SThomas Petazzoni if (ret) { 4154c5aff182SThomas Petazzoni netdev_err(pp->dev, "cannot request irq %d\n", pp->dev->irq); 4155c5aff182SThomas Petazzoni goto err_cleanup_txqs; 4156c5aff182SThomas Petazzoni } 4157c5aff182SThomas Petazzoni 41582636ac3cSMarcin Wojtas if (!pp->neta_armada3700) { 41592dcf75e2SGregory CLEMENT /* Enable per-CPU interrupt on all the CPU to handle our RX 41602dcf75e2SGregory CLEMENT * queue interrupts 41612dcf75e2SGregory CLEMENT */ 41626b125d63SGregory CLEMENT on_each_cpu(mvneta_percpu_enable, pp, true); 41632dcf75e2SGregory CLEMENT 4164120cfa50SGregory CLEMENT pp->is_stopped = false; 4165f8642885SMaxime Ripard /* Register a CPU notifier to handle the case where our CPU 4166f8642885SMaxime Ripard * might be taken offline. 4167f8642885SMaxime Ripard */ 416884a3f4dbSSebastian Andrzej Siewior ret = cpuhp_state_add_instance_nocalls(online_hpstate, 416984a3f4dbSSebastian Andrzej Siewior &pp->node_online); 417084a3f4dbSSebastian Andrzej Siewior if (ret) 417184a3f4dbSSebastian Andrzej Siewior goto err_free_irq; 417284a3f4dbSSebastian Andrzej Siewior 417384a3f4dbSSebastian Andrzej Siewior ret = cpuhp_state_add_instance_nocalls(CPUHP_NET_MVNETA_DEAD, 417484a3f4dbSSebastian Andrzej Siewior &pp->node_dead); 417584a3f4dbSSebastian Andrzej Siewior if (ret) 417684a3f4dbSSebastian Andrzej Siewior goto err_free_online_hp; 41772636ac3cSMarcin Wojtas } 4178f8642885SMaxime Ripard 4179c5aff182SThomas Petazzoni ret = mvneta_mdio_probe(pp); 4180c5aff182SThomas Petazzoni if (ret < 0) { 4181c5aff182SThomas Petazzoni netdev_err(dev, "cannot probe MDIO bus\n"); 418284a3f4dbSSebastian Andrzej Siewior goto err_free_dead_hp; 4183c5aff182SThomas Petazzoni } 4184c5aff182SThomas Petazzoni 4185c5aff182SThomas Petazzoni mvneta_start_dev(pp); 4186c5aff182SThomas Petazzoni 4187c5aff182SThomas Petazzoni return 0; 4188c5aff182SThomas Petazzoni 418984a3f4dbSSebastian Andrzej Siewior err_free_dead_hp: 41902636ac3cSMarcin Wojtas if (!pp->neta_armada3700) 419184a3f4dbSSebastian Andrzej Siewior cpuhp_state_remove_instance_nocalls(CPUHP_NET_MVNETA_DEAD, 419284a3f4dbSSebastian Andrzej Siewior &pp->node_dead); 419384a3f4dbSSebastian Andrzej Siewior err_free_online_hp: 41942636ac3cSMarcin Wojtas if (!pp->neta_armada3700) 41952636ac3cSMarcin Wojtas cpuhp_state_remove_instance_nocalls(online_hpstate, 41962636ac3cSMarcin Wojtas &pp->node_online); 4197c5aff182SThomas Petazzoni err_free_irq: 41982636ac3cSMarcin Wojtas if (pp->neta_armada3700) { 41992636ac3cSMarcin Wojtas free_irq(pp->dev->irq, pp); 42002636ac3cSMarcin Wojtas } else { 42013d8c4530SRussell King - ARM Linux on_each_cpu(mvneta_percpu_disable, pp, true); 420212bb03b4SMaxime Ripard free_percpu_irq(pp->dev->irq, pp->ports); 42032636ac3cSMarcin Wojtas } 4204c5aff182SThomas Petazzoni err_cleanup_txqs: 4205c5aff182SThomas Petazzoni mvneta_cleanup_txqs(pp); 4206c5aff182SThomas Petazzoni err_cleanup_rxqs: 4207c5aff182SThomas Petazzoni mvneta_cleanup_rxqs(pp); 4208c5aff182SThomas Petazzoni return ret; 4209c5aff182SThomas Petazzoni } 4210c5aff182SThomas Petazzoni 4211c5aff182SThomas Petazzoni /* Stop the port, free port interrupt line */ 4212c5aff182SThomas Petazzoni static int mvneta_stop(struct net_device *dev) 4213c5aff182SThomas Petazzoni { 4214c5aff182SThomas Petazzoni struct mvneta_port *pp = netdev_priv(dev); 4215c5aff182SThomas Petazzoni 42162636ac3cSMarcin Wojtas if (!pp->neta_armada3700) { 4217120cfa50SGregory CLEMENT /* Inform that we are stopping so we don't want to setup the 42181c2722a9SGregory CLEMENT * driver for new CPUs in the notifiers. The code of the 42191c2722a9SGregory CLEMENT * notifier for CPU online is protected by the same spinlock, 42201c2722a9SGregory CLEMENT * so when we get the lock, the notifer work is done. 4221120cfa50SGregory CLEMENT */ 4222120cfa50SGregory CLEMENT spin_lock(&pp->lock); 4223120cfa50SGregory CLEMENT pp->is_stopped = true; 42241c2722a9SGregory CLEMENT spin_unlock(&pp->lock); 42251c2722a9SGregory CLEMENT 4226c5aff182SThomas Petazzoni mvneta_stop_dev(pp); 4227c5aff182SThomas Petazzoni mvneta_mdio_remove(pp); 422884a3f4dbSSebastian Andrzej Siewior 4229d26aac2dSDan Carpenter cpuhp_state_remove_instance_nocalls(online_hpstate, 4230d26aac2dSDan Carpenter &pp->node_online); 423184a3f4dbSSebastian Andrzej Siewior cpuhp_state_remove_instance_nocalls(CPUHP_NET_MVNETA_DEAD, 423284a3f4dbSSebastian Andrzej Siewior &pp->node_dead); 4233129219e4SGregory CLEMENT on_each_cpu(mvneta_percpu_disable, pp, true); 423412bb03b4SMaxime Ripard free_percpu_irq(dev->irq, pp->ports); 42352636ac3cSMarcin Wojtas } else { 42362636ac3cSMarcin Wojtas mvneta_stop_dev(pp); 42372636ac3cSMarcin Wojtas mvneta_mdio_remove(pp); 42382636ac3cSMarcin Wojtas free_irq(dev->irq, pp); 42392636ac3cSMarcin Wojtas } 42402636ac3cSMarcin Wojtas 4241c5aff182SThomas Petazzoni mvneta_cleanup_rxqs(pp); 4242c5aff182SThomas Petazzoni mvneta_cleanup_txqs(pp); 4243c5aff182SThomas Petazzoni 4244c5aff182SThomas Petazzoni return 0; 4245c5aff182SThomas Petazzoni } 4246c5aff182SThomas Petazzoni 424715f59456SThomas Petazzoni static int mvneta_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) 424815f59456SThomas Petazzoni { 4249503f9aa9SRussell King struct mvneta_port *pp = netdev_priv(dev); 425015f59456SThomas Petazzoni 4251503f9aa9SRussell King return phylink_mii_ioctl(pp->phylink, ifr, cmd); 425215f59456SThomas Petazzoni } 425315f59456SThomas Petazzoni 42540db51da7SLorenzo Bianconi static int mvneta_xdp_setup(struct net_device *dev, struct bpf_prog *prog, 42550db51da7SLorenzo Bianconi struct netlink_ext_ack *extack) 42560db51da7SLorenzo Bianconi { 42570db51da7SLorenzo Bianconi bool need_update, running = netif_running(dev); 42580db51da7SLorenzo Bianconi struct mvneta_port *pp = netdev_priv(dev); 42590db51da7SLorenzo Bianconi struct bpf_prog *old_prog; 42600db51da7SLorenzo Bianconi 42610db51da7SLorenzo Bianconi if (prog && dev->mtu > MVNETA_MAX_RX_BUF_SIZE) { 42620db51da7SLorenzo Bianconi NL_SET_ERR_MSG_MOD(extack, "Jumbo frames not supported on XDP"); 42630db51da7SLorenzo Bianconi return -EOPNOTSUPP; 42640db51da7SLorenzo Bianconi } 42650db51da7SLorenzo Bianconi 426679572c98SSven Auhagen if (pp->bm_priv) { 426779572c98SSven Auhagen NL_SET_ERR_MSG_MOD(extack, 426879572c98SSven Auhagen "Hardware Buffer Management not supported on XDP"); 426979572c98SSven Auhagen return -EOPNOTSUPP; 427079572c98SSven Auhagen } 427179572c98SSven Auhagen 42720db51da7SLorenzo Bianconi need_update = !!pp->xdp_prog != !!prog; 42730db51da7SLorenzo Bianconi if (running && need_update) 42740db51da7SLorenzo Bianconi mvneta_stop(dev); 42750db51da7SLorenzo Bianconi 42760db51da7SLorenzo Bianconi old_prog = xchg(&pp->xdp_prog, prog); 42770db51da7SLorenzo Bianconi if (old_prog) 42780db51da7SLorenzo Bianconi bpf_prog_put(old_prog); 42790db51da7SLorenzo Bianconi 42800db51da7SLorenzo Bianconi if (running && need_update) 42810db51da7SLorenzo Bianconi return mvneta_open(dev); 42820db51da7SLorenzo Bianconi 42830db51da7SLorenzo Bianconi return 0; 42840db51da7SLorenzo Bianconi } 42850db51da7SLorenzo Bianconi 42860db51da7SLorenzo Bianconi static int mvneta_xdp(struct net_device *dev, struct netdev_bpf *xdp) 42870db51da7SLorenzo Bianconi { 42880db51da7SLorenzo Bianconi struct mvneta_port *pp = netdev_priv(dev); 42890db51da7SLorenzo Bianconi 42900db51da7SLorenzo Bianconi switch (xdp->command) { 42910db51da7SLorenzo Bianconi case XDP_SETUP_PROG: 42920db51da7SLorenzo Bianconi return mvneta_xdp_setup(dev, xdp->prog, xdp->extack); 42930db51da7SLorenzo Bianconi case XDP_QUERY_PROG: 42940db51da7SLorenzo Bianconi xdp->prog_id = pp->xdp_prog ? pp->xdp_prog->aux->id : 0; 42950db51da7SLorenzo Bianconi return 0; 42960db51da7SLorenzo Bianconi default: 42970db51da7SLorenzo Bianconi return -EINVAL; 42980db51da7SLorenzo Bianconi } 42990db51da7SLorenzo Bianconi } 43000db51da7SLorenzo Bianconi 4301c5aff182SThomas Petazzoni /* Ethtool methods */ 4302c5aff182SThomas Petazzoni 4303013ad40dSPhilippe Reynes /* Set link ksettings (phy address, speed) for ethtools */ 43042dc0d2b4SBaoyou Xie static int 43052dc0d2b4SBaoyou Xie mvneta_ethtool_set_link_ksettings(struct net_device *ndev, 4306013ad40dSPhilippe Reynes const struct ethtool_link_ksettings *cmd) 4307c5aff182SThomas Petazzoni { 4308013ad40dSPhilippe Reynes struct mvneta_port *pp = netdev_priv(ndev); 4309c5aff182SThomas Petazzoni 4310503f9aa9SRussell King return phylink_ethtool_ksettings_set(pp->phylink, cmd); 43110c0744fcSStas Sergeev } 43120c0744fcSStas Sergeev 4313503f9aa9SRussell King /* Get link ksettings for ethtools */ 4314503f9aa9SRussell King static int 4315503f9aa9SRussell King mvneta_ethtool_get_link_ksettings(struct net_device *ndev, 4316503f9aa9SRussell King struct ethtool_link_ksettings *cmd) 4317503f9aa9SRussell King { 4318503f9aa9SRussell King struct mvneta_port *pp = netdev_priv(ndev); 43190c0744fcSStas Sergeev 4320503f9aa9SRussell King return phylink_ethtool_ksettings_get(pp->phylink, cmd); 43210c0744fcSStas Sergeev } 43220c0744fcSStas Sergeev 4323503f9aa9SRussell King static int mvneta_ethtool_nway_reset(struct net_device *dev) 4324503f9aa9SRussell King { 4325503f9aa9SRussell King struct mvneta_port *pp = netdev_priv(dev); 4326503f9aa9SRussell King 4327503f9aa9SRussell King return phylink_ethtool_nway_reset(pp->phylink); 4328c5aff182SThomas Petazzoni } 4329c5aff182SThomas Petazzoni 4330c5aff182SThomas Petazzoni /* Set interrupt coalescing for ethtools */ 4331c5aff182SThomas Petazzoni static int mvneta_ethtool_set_coalesce(struct net_device *dev, 4332c5aff182SThomas Petazzoni struct ethtool_coalesce *c) 4333c5aff182SThomas Petazzoni { 4334c5aff182SThomas Petazzoni struct mvneta_port *pp = netdev_priv(dev); 4335c5aff182SThomas Petazzoni int queue; 4336c5aff182SThomas Petazzoni 4337c5aff182SThomas Petazzoni for (queue = 0; queue < rxq_number; queue++) { 4338c5aff182SThomas Petazzoni struct mvneta_rx_queue *rxq = &pp->rxqs[queue]; 4339c5aff182SThomas Petazzoni rxq->time_coal = c->rx_coalesce_usecs; 4340c5aff182SThomas Petazzoni rxq->pkts_coal = c->rx_max_coalesced_frames; 4341c5aff182SThomas Petazzoni mvneta_rx_pkts_coal_set(pp, rxq, rxq->pkts_coal); 4342c5aff182SThomas Petazzoni mvneta_rx_time_coal_set(pp, rxq, rxq->time_coal); 4343c5aff182SThomas Petazzoni } 4344c5aff182SThomas Petazzoni 4345c5aff182SThomas Petazzoni for (queue = 0; queue < txq_number; queue++) { 4346c5aff182SThomas Petazzoni struct mvneta_tx_queue *txq = &pp->txqs[queue]; 4347c5aff182SThomas Petazzoni txq->done_pkts_coal = c->tx_max_coalesced_frames; 4348c5aff182SThomas Petazzoni mvneta_tx_done_pkts_coal_set(pp, txq, txq->done_pkts_coal); 4349c5aff182SThomas Petazzoni } 4350c5aff182SThomas Petazzoni 4351c5aff182SThomas Petazzoni return 0; 4352c5aff182SThomas Petazzoni } 4353c5aff182SThomas Petazzoni 4354c5aff182SThomas Petazzoni /* get coalescing for ethtools */ 4355c5aff182SThomas Petazzoni static int mvneta_ethtool_get_coalesce(struct net_device *dev, 4356c5aff182SThomas Petazzoni struct ethtool_coalesce *c) 4357c5aff182SThomas Petazzoni { 4358c5aff182SThomas Petazzoni struct mvneta_port *pp = netdev_priv(dev); 4359c5aff182SThomas Petazzoni 4360c5aff182SThomas Petazzoni c->rx_coalesce_usecs = pp->rxqs[0].time_coal; 4361c5aff182SThomas Petazzoni c->rx_max_coalesced_frames = pp->rxqs[0].pkts_coal; 4362c5aff182SThomas Petazzoni 4363c5aff182SThomas Petazzoni c->tx_max_coalesced_frames = pp->txqs[0].done_pkts_coal; 4364c5aff182SThomas Petazzoni return 0; 4365c5aff182SThomas Petazzoni } 4366c5aff182SThomas Petazzoni 4367c5aff182SThomas Petazzoni 4368c5aff182SThomas Petazzoni static void mvneta_ethtool_get_drvinfo(struct net_device *dev, 4369c5aff182SThomas Petazzoni struct ethtool_drvinfo *drvinfo) 4370c5aff182SThomas Petazzoni { 4371c5aff182SThomas Petazzoni strlcpy(drvinfo->driver, MVNETA_DRIVER_NAME, 4372c5aff182SThomas Petazzoni sizeof(drvinfo->driver)); 4373c5aff182SThomas Petazzoni strlcpy(drvinfo->version, MVNETA_DRIVER_VERSION, 4374c5aff182SThomas Petazzoni sizeof(drvinfo->version)); 4375c5aff182SThomas Petazzoni strlcpy(drvinfo->bus_info, dev_name(&dev->dev), 4376c5aff182SThomas Petazzoni sizeof(drvinfo->bus_info)); 4377c5aff182SThomas Petazzoni } 4378c5aff182SThomas Petazzoni 4379c5aff182SThomas Petazzoni 4380c5aff182SThomas Petazzoni static void mvneta_ethtool_get_ringparam(struct net_device *netdev, 4381c5aff182SThomas Petazzoni struct ethtool_ringparam *ring) 4382c5aff182SThomas Petazzoni { 4383c5aff182SThomas Petazzoni struct mvneta_port *pp = netdev_priv(netdev); 4384c5aff182SThomas Petazzoni 4385c5aff182SThomas Petazzoni ring->rx_max_pending = MVNETA_MAX_RXD; 4386c5aff182SThomas Petazzoni ring->tx_max_pending = MVNETA_MAX_TXD; 4387c5aff182SThomas Petazzoni ring->rx_pending = pp->rx_ring_size; 4388c5aff182SThomas Petazzoni ring->tx_pending = pp->tx_ring_size; 4389c5aff182SThomas Petazzoni } 4390c5aff182SThomas Petazzoni 4391c5aff182SThomas Petazzoni static int mvneta_ethtool_set_ringparam(struct net_device *dev, 4392c5aff182SThomas Petazzoni struct ethtool_ringparam *ring) 4393c5aff182SThomas Petazzoni { 4394c5aff182SThomas Petazzoni struct mvneta_port *pp = netdev_priv(dev); 4395c5aff182SThomas Petazzoni 4396c5aff182SThomas Petazzoni if ((ring->rx_pending == 0) || (ring->tx_pending == 0)) 4397c5aff182SThomas Petazzoni return -EINVAL; 4398c5aff182SThomas Petazzoni pp->rx_ring_size = ring->rx_pending < MVNETA_MAX_RXD ? 4399c5aff182SThomas Petazzoni ring->rx_pending : MVNETA_MAX_RXD; 44008eef5f97SEzequiel Garcia 44018eef5f97SEzequiel Garcia pp->tx_ring_size = clamp_t(u16, ring->tx_pending, 44028eef5f97SEzequiel Garcia MVNETA_MAX_SKB_DESCS * 2, MVNETA_MAX_TXD); 44038eef5f97SEzequiel Garcia if (pp->tx_ring_size != ring->tx_pending) 44048eef5f97SEzequiel Garcia netdev_warn(dev, "TX queue size set to %u (requested %u)\n", 44058eef5f97SEzequiel Garcia pp->tx_ring_size, ring->tx_pending); 4406c5aff182SThomas Petazzoni 4407c5aff182SThomas Petazzoni if (netif_running(dev)) { 4408c5aff182SThomas Petazzoni mvneta_stop(dev); 4409c5aff182SThomas Petazzoni if (mvneta_open(dev)) { 4410c5aff182SThomas Petazzoni netdev_err(dev, 4411c5aff182SThomas Petazzoni "error on opening device after ring param change\n"); 4412c5aff182SThomas Petazzoni return -ENOMEM; 4413c5aff182SThomas Petazzoni } 4414c5aff182SThomas Petazzoni } 4415c5aff182SThomas Petazzoni 4416c5aff182SThomas Petazzoni return 0; 4417c5aff182SThomas Petazzoni } 4418c5aff182SThomas Petazzoni 44194932a918SRussell King static void mvneta_ethtool_get_pauseparam(struct net_device *dev, 44204932a918SRussell King struct ethtool_pauseparam *pause) 44214932a918SRussell King { 44224932a918SRussell King struct mvneta_port *pp = netdev_priv(dev); 44234932a918SRussell King 44244932a918SRussell King phylink_ethtool_get_pauseparam(pp->phylink, pause); 44254932a918SRussell King } 44264932a918SRussell King 44274932a918SRussell King static int mvneta_ethtool_set_pauseparam(struct net_device *dev, 44284932a918SRussell King struct ethtool_pauseparam *pause) 44294932a918SRussell King { 44304932a918SRussell King struct mvneta_port *pp = netdev_priv(dev); 44314932a918SRussell King 44324932a918SRussell King return phylink_ethtool_set_pauseparam(pp->phylink, pause); 44334932a918SRussell King } 44344932a918SRussell King 44359b0cdefaSRussell King static void mvneta_ethtool_get_strings(struct net_device *netdev, u32 sset, 44369b0cdefaSRussell King u8 *data) 44379b0cdefaSRussell King { 44389b0cdefaSRussell King if (sset == ETH_SS_STATS) { 44399b0cdefaSRussell King int i; 44409b0cdefaSRussell King 44419b0cdefaSRussell King for (i = 0; i < ARRAY_SIZE(mvneta_statistics); i++) 44429b0cdefaSRussell King memcpy(data + i * ETH_GSTRING_LEN, 44439b0cdefaSRussell King mvneta_statistics[i].name, ETH_GSTRING_LEN); 44449b0cdefaSRussell King } 44459b0cdefaSRussell King } 44469b0cdefaSRussell King 44479ac41f3cSLorenzo Bianconi static void 44489ac41f3cSLorenzo Bianconi mvneta_ethtool_update_pcpu_stats(struct mvneta_port *pp, 44499ac41f3cSLorenzo Bianconi struct mvneta_ethtool_stats *es) 44509ac41f3cSLorenzo Bianconi { 44519ac41f3cSLorenzo Bianconi unsigned int start; 44529ac41f3cSLorenzo Bianconi int cpu; 44539ac41f3cSLorenzo Bianconi 44549ac41f3cSLorenzo Bianconi for_each_possible_cpu(cpu) { 44559ac41f3cSLorenzo Bianconi struct mvneta_pcpu_stats *stats; 44569ac41f3cSLorenzo Bianconi u64 skb_alloc_error; 44579ac41f3cSLorenzo Bianconi u64 refill_error; 44589ac41f3cSLorenzo Bianconi 44599ac41f3cSLorenzo Bianconi stats = per_cpu_ptr(pp->stats, cpu); 44609ac41f3cSLorenzo Bianconi do { 44619ac41f3cSLorenzo Bianconi start = u64_stats_fetch_begin_irq(&stats->syncp); 44629ac41f3cSLorenzo Bianconi skb_alloc_error = stats->es.skb_alloc_error; 44639ac41f3cSLorenzo Bianconi refill_error = stats->es.refill_error; 44649ac41f3cSLorenzo Bianconi } while (u64_stats_fetch_retry_irq(&stats->syncp, start)); 44659ac41f3cSLorenzo Bianconi 44669ac41f3cSLorenzo Bianconi es->skb_alloc_error += skb_alloc_error; 44679ac41f3cSLorenzo Bianconi es->refill_error += refill_error; 44689ac41f3cSLorenzo Bianconi } 44699ac41f3cSLorenzo Bianconi } 44709ac41f3cSLorenzo Bianconi 44719b0cdefaSRussell King static void mvneta_ethtool_update_stats(struct mvneta_port *pp) 44729b0cdefaSRussell King { 44739ac41f3cSLorenzo Bianconi struct mvneta_ethtool_stats stats = {}; 44749b0cdefaSRussell King const struct mvneta_statistic *s; 44759b0cdefaSRussell King void __iomem *base = pp->base; 44766d81f451SRussell King u32 high, low; 44776d81f451SRussell King u64 val; 44789b0cdefaSRussell King int i; 44799b0cdefaSRussell King 44809ac41f3cSLorenzo Bianconi mvneta_ethtool_update_pcpu_stats(pp, &stats); 44819b0cdefaSRussell King for (i = 0, s = mvneta_statistics; 44829b0cdefaSRussell King s < mvneta_statistics + ARRAY_SIZE(mvneta_statistics); 44839b0cdefaSRussell King s++, i++) { 44849b0cdefaSRussell King switch (s->type) { 44859b0cdefaSRussell King case T_REG_32: 44869b0cdefaSRussell King val = readl_relaxed(base + s->offset); 44879ac41f3cSLorenzo Bianconi pp->ethtool_stats[i] += val; 44889b0cdefaSRussell King break; 44899b0cdefaSRussell King case T_REG_64: 44909b0cdefaSRussell King /* Docs say to read low 32-bit then high */ 44919b0cdefaSRussell King low = readl_relaxed(base + s->offset); 44929b0cdefaSRussell King high = readl_relaxed(base + s->offset + 4); 44936d81f451SRussell King val = (u64)high << 32 | low; 44949ac41f3cSLorenzo Bianconi pp->ethtool_stats[i] += val; 44956d81f451SRussell King break; 44966d81f451SRussell King case T_SW: 44976d81f451SRussell King switch (s->offset) { 44986d81f451SRussell King case ETHTOOL_STAT_EEE_WAKEUP: 44996d81f451SRussell King val = phylink_get_eee_err(pp->phylink); 45009ac41f3cSLorenzo Bianconi pp->ethtool_stats[i] += val; 45019b0cdefaSRussell King break; 450217a96da6SGregory CLEMENT case ETHTOOL_STAT_SKB_ALLOC_ERR: 45039ac41f3cSLorenzo Bianconi pp->ethtool_stats[i] = stats.skb_alloc_error; 450417a96da6SGregory CLEMENT break; 450517a96da6SGregory CLEMENT case ETHTOOL_STAT_REFILL_ERR: 45069ac41f3cSLorenzo Bianconi pp->ethtool_stats[i] = stats.refill_error; 450717a96da6SGregory CLEMENT break; 45089b0cdefaSRussell King } 45096d81f451SRussell King break; 45106d81f451SRussell King } 45119b0cdefaSRussell King } 45129b0cdefaSRussell King } 45139b0cdefaSRussell King 45149b0cdefaSRussell King static void mvneta_ethtool_get_stats(struct net_device *dev, 45159b0cdefaSRussell King struct ethtool_stats *stats, u64 *data) 45169b0cdefaSRussell King { 45179b0cdefaSRussell King struct mvneta_port *pp = netdev_priv(dev); 45189b0cdefaSRussell King int i; 45199b0cdefaSRussell King 45209b0cdefaSRussell King mvneta_ethtool_update_stats(pp); 45219b0cdefaSRussell King 45229b0cdefaSRussell King for (i = 0; i < ARRAY_SIZE(mvneta_statistics); i++) 45239b0cdefaSRussell King *data++ = pp->ethtool_stats[i]; 45249b0cdefaSRussell King } 45259b0cdefaSRussell King 45269b0cdefaSRussell King static int mvneta_ethtool_get_sset_count(struct net_device *dev, int sset) 45279b0cdefaSRussell King { 45289b0cdefaSRussell King if (sset == ETH_SS_STATS) 45299b0cdefaSRussell King return ARRAY_SIZE(mvneta_statistics); 45309b0cdefaSRussell King return -EOPNOTSUPP; 45319b0cdefaSRussell King } 45329b0cdefaSRussell King 45339a401deaSGregory CLEMENT static u32 mvneta_ethtool_get_rxfh_indir_size(struct net_device *dev) 45349a401deaSGregory CLEMENT { 45359a401deaSGregory CLEMENT return MVNETA_RSS_LU_TABLE_SIZE; 45369a401deaSGregory CLEMENT } 45379a401deaSGregory CLEMENT 45389a401deaSGregory CLEMENT static int mvneta_ethtool_get_rxnfc(struct net_device *dev, 45399a401deaSGregory CLEMENT struct ethtool_rxnfc *info, 45409a401deaSGregory CLEMENT u32 *rules __always_unused) 45419a401deaSGregory CLEMENT { 45429a401deaSGregory CLEMENT switch (info->cmd) { 45439a401deaSGregory CLEMENT case ETHTOOL_GRXRINGS: 45449a401deaSGregory CLEMENT info->data = rxq_number; 45459a401deaSGregory CLEMENT return 0; 45469a401deaSGregory CLEMENT case ETHTOOL_GRXFH: 45479a401deaSGregory CLEMENT return -EOPNOTSUPP; 45489a401deaSGregory CLEMENT default: 45499a401deaSGregory CLEMENT return -EOPNOTSUPP; 45509a401deaSGregory CLEMENT } 45519a401deaSGregory CLEMENT } 45529a401deaSGregory CLEMENT 45539a401deaSGregory CLEMENT static int mvneta_config_rss(struct mvneta_port *pp) 45549a401deaSGregory CLEMENT { 45559a401deaSGregory CLEMENT int cpu; 45569a401deaSGregory CLEMENT u32 val; 45579a401deaSGregory CLEMENT 45589a401deaSGregory CLEMENT netif_tx_stop_all_queues(pp->dev); 45599a401deaSGregory CLEMENT 45606b125d63SGregory CLEMENT on_each_cpu(mvneta_percpu_mask_interrupt, pp, true); 45619a401deaSGregory CLEMENT 45620f5c6c30SJisheng Zhang if (!pp->neta_armada3700) { 45639a401deaSGregory CLEMENT /* We have to synchronise on the napi of each CPU */ 45649a401deaSGregory CLEMENT for_each_online_cpu(cpu) { 45659a401deaSGregory CLEMENT struct mvneta_pcpu_port *pcpu_port = 45669a401deaSGregory CLEMENT per_cpu_ptr(pp->ports, cpu); 45679a401deaSGregory CLEMENT 45689a401deaSGregory CLEMENT napi_synchronize(&pcpu_port->napi); 45699a401deaSGregory CLEMENT napi_disable(&pcpu_port->napi); 45709a401deaSGregory CLEMENT } 45710f5c6c30SJisheng Zhang } else { 45720f5c6c30SJisheng Zhang napi_synchronize(&pp->napi); 45730f5c6c30SJisheng Zhang napi_disable(&pp->napi); 45740f5c6c30SJisheng Zhang } 45759a401deaSGregory CLEMENT 45769a401deaSGregory CLEMENT pp->rxq_def = pp->indir[0]; 45779a401deaSGregory CLEMENT 45789a401deaSGregory CLEMENT /* Update unicast mapping */ 45799a401deaSGregory CLEMENT mvneta_set_rx_mode(pp->dev); 45809a401deaSGregory CLEMENT 45819a401deaSGregory CLEMENT /* Update val of portCfg register accordingly with all RxQueue types */ 45829a401deaSGregory CLEMENT val = MVNETA_PORT_CONFIG_DEFL_VALUE(pp->rxq_def); 45839a401deaSGregory CLEMENT mvreg_write(pp, MVNETA_PORT_CONFIG, val); 45849a401deaSGregory CLEMENT 45859a401deaSGregory CLEMENT /* Update the elected CPU matching the new rxq_def */ 4586120cfa50SGregory CLEMENT spin_lock(&pp->lock); 45879a401deaSGregory CLEMENT mvneta_percpu_elect(pp); 4588120cfa50SGregory CLEMENT spin_unlock(&pp->lock); 45899a401deaSGregory CLEMENT 45900f5c6c30SJisheng Zhang if (!pp->neta_armada3700) { 45919a401deaSGregory CLEMENT /* We have to synchronise on the napi of each CPU */ 45929a401deaSGregory CLEMENT for_each_online_cpu(cpu) { 45939a401deaSGregory CLEMENT struct mvneta_pcpu_port *pcpu_port = 45949a401deaSGregory CLEMENT per_cpu_ptr(pp->ports, cpu); 45959a401deaSGregory CLEMENT 45969a401deaSGregory CLEMENT napi_enable(&pcpu_port->napi); 45979a401deaSGregory CLEMENT } 45980f5c6c30SJisheng Zhang } else { 45990f5c6c30SJisheng Zhang napi_enable(&pp->napi); 46000f5c6c30SJisheng Zhang } 46019a401deaSGregory CLEMENT 46029a401deaSGregory CLEMENT netif_tx_start_all_queues(pp->dev); 46039a401deaSGregory CLEMENT 46049a401deaSGregory CLEMENT return 0; 46059a401deaSGregory CLEMENT } 46069a401deaSGregory CLEMENT 46079a401deaSGregory CLEMENT static int mvneta_ethtool_set_rxfh(struct net_device *dev, const u32 *indir, 46089a401deaSGregory CLEMENT const u8 *key, const u8 hfunc) 46099a401deaSGregory CLEMENT { 46109a401deaSGregory CLEMENT struct mvneta_port *pp = netdev_priv(dev); 46112636ac3cSMarcin Wojtas 46122636ac3cSMarcin Wojtas /* Current code for Armada 3700 doesn't support RSS features yet */ 46132636ac3cSMarcin Wojtas if (pp->neta_armada3700) 46142636ac3cSMarcin Wojtas return -EOPNOTSUPP; 46152636ac3cSMarcin Wojtas 46169a401deaSGregory CLEMENT /* We require at least one supported parameter to be changed 46179a401deaSGregory CLEMENT * and no change in any of the unsupported parameters 46189a401deaSGregory CLEMENT */ 46199a401deaSGregory CLEMENT if (key || 46209a401deaSGregory CLEMENT (hfunc != ETH_RSS_HASH_NO_CHANGE && hfunc != ETH_RSS_HASH_TOP)) 46219a401deaSGregory CLEMENT return -EOPNOTSUPP; 46229a401deaSGregory CLEMENT 46239a401deaSGregory CLEMENT if (!indir) 46249a401deaSGregory CLEMENT return 0; 46259a401deaSGregory CLEMENT 46269a401deaSGregory CLEMENT memcpy(pp->indir, indir, MVNETA_RSS_LU_TABLE_SIZE); 46279a401deaSGregory CLEMENT 46289a401deaSGregory CLEMENT return mvneta_config_rss(pp); 46299a401deaSGregory CLEMENT } 46309a401deaSGregory CLEMENT 46319a401deaSGregory CLEMENT static int mvneta_ethtool_get_rxfh(struct net_device *dev, u32 *indir, u8 *key, 46329a401deaSGregory CLEMENT u8 *hfunc) 46339a401deaSGregory CLEMENT { 46349a401deaSGregory CLEMENT struct mvneta_port *pp = netdev_priv(dev); 46359a401deaSGregory CLEMENT 46362636ac3cSMarcin Wojtas /* Current code for Armada 3700 doesn't support RSS features yet */ 46372636ac3cSMarcin Wojtas if (pp->neta_armada3700) 46382636ac3cSMarcin Wojtas return -EOPNOTSUPP; 46392636ac3cSMarcin Wojtas 46409a401deaSGregory CLEMENT if (hfunc) 46419a401deaSGregory CLEMENT *hfunc = ETH_RSS_HASH_TOP; 46429a401deaSGregory CLEMENT 46439a401deaSGregory CLEMENT if (!indir) 46449a401deaSGregory CLEMENT return 0; 46459a401deaSGregory CLEMENT 46469a401deaSGregory CLEMENT memcpy(indir, pp->indir, MVNETA_RSS_LU_TABLE_SIZE); 46479a401deaSGregory CLEMENT 46489a401deaSGregory CLEMENT return 0; 46499a401deaSGregory CLEMENT } 46509a401deaSGregory CLEMENT 4651b60a00f9SJingju Hou static void mvneta_ethtool_get_wol(struct net_device *dev, 4652b60a00f9SJingju Hou struct ethtool_wolinfo *wol) 4653b60a00f9SJingju Hou { 4654503f9aa9SRussell King struct mvneta_port *pp = netdev_priv(dev); 4655b60a00f9SJingju Hou 4656503f9aa9SRussell King phylink_ethtool_get_wol(pp->phylink, wol); 4657b60a00f9SJingju Hou } 4658b60a00f9SJingju Hou 4659b60a00f9SJingju Hou static int mvneta_ethtool_set_wol(struct net_device *dev, 4660b60a00f9SJingju Hou struct ethtool_wolinfo *wol) 4661b60a00f9SJingju Hou { 4662503f9aa9SRussell King struct mvneta_port *pp = netdev_priv(dev); 466382960fffSJisheng Zhang int ret; 466482960fffSJisheng Zhang 4665503f9aa9SRussell King ret = phylink_ethtool_set_wol(pp->phylink, wol); 466682960fffSJisheng Zhang if (!ret) 466782960fffSJisheng Zhang device_set_wakeup_enable(&dev->dev, !!wol->wolopts); 466882960fffSJisheng Zhang 466982960fffSJisheng Zhang return ret; 4670b60a00f9SJingju Hou } 4671b60a00f9SJingju Hou 46726d81f451SRussell King static int mvneta_ethtool_get_eee(struct net_device *dev, 46736d81f451SRussell King struct ethtool_eee *eee) 46746d81f451SRussell King { 46756d81f451SRussell King struct mvneta_port *pp = netdev_priv(dev); 46766d81f451SRussell King u32 lpi_ctl0; 46776d81f451SRussell King 46786d81f451SRussell King lpi_ctl0 = mvreg_read(pp, MVNETA_LPI_CTRL_0); 46796d81f451SRussell King 46806d81f451SRussell King eee->eee_enabled = pp->eee_enabled; 46816d81f451SRussell King eee->eee_active = pp->eee_active; 46826d81f451SRussell King eee->tx_lpi_enabled = pp->tx_lpi_enabled; 46836d81f451SRussell King eee->tx_lpi_timer = (lpi_ctl0) >> 8; // * scale; 46846d81f451SRussell King 46856d81f451SRussell King return phylink_ethtool_get_eee(pp->phylink, eee); 46866d81f451SRussell King } 46876d81f451SRussell King 46886d81f451SRussell King static int mvneta_ethtool_set_eee(struct net_device *dev, 46896d81f451SRussell King struct ethtool_eee *eee) 46906d81f451SRussell King { 46916d81f451SRussell King struct mvneta_port *pp = netdev_priv(dev); 46926d81f451SRussell King u32 lpi_ctl0; 46936d81f451SRussell King 46946d81f451SRussell King /* The Armada 37x documents do not give limits for this other than 46956d81f451SRussell King * it being an 8-bit register. */ 4696e4a3e9ffSYueHaibing if (eee->tx_lpi_enabled && eee->tx_lpi_timer > 255) 46976d81f451SRussell King return -EINVAL; 46986d81f451SRussell King 46996d81f451SRussell King lpi_ctl0 = mvreg_read(pp, MVNETA_LPI_CTRL_0); 47006d81f451SRussell King lpi_ctl0 &= ~(0xff << 8); 47016d81f451SRussell King lpi_ctl0 |= eee->tx_lpi_timer << 8; 47026d81f451SRussell King mvreg_write(pp, MVNETA_LPI_CTRL_0, lpi_ctl0); 47036d81f451SRussell King 47046d81f451SRussell King pp->eee_enabled = eee->eee_enabled; 47056d81f451SRussell King pp->tx_lpi_enabled = eee->tx_lpi_enabled; 47066d81f451SRussell King 47076d81f451SRussell King mvneta_set_eee(pp, eee->tx_lpi_enabled && eee->eee_enabled); 47086d81f451SRussell King 47096d81f451SRussell King return phylink_ethtool_set_eee(pp->phylink, eee); 47106d81f451SRussell King } 47116d81f451SRussell King 4712c5aff182SThomas Petazzoni static const struct net_device_ops mvneta_netdev_ops = { 4713c5aff182SThomas Petazzoni .ndo_open = mvneta_open, 4714c5aff182SThomas Petazzoni .ndo_stop = mvneta_stop, 4715c5aff182SThomas Petazzoni .ndo_start_xmit = mvneta_tx, 4716c5aff182SThomas Petazzoni .ndo_set_rx_mode = mvneta_set_rx_mode, 4717c5aff182SThomas Petazzoni .ndo_set_mac_address = mvneta_set_mac_addr, 4718c5aff182SThomas Petazzoni .ndo_change_mtu = mvneta_change_mtu, 4719b65657fcSSimon Guinot .ndo_fix_features = mvneta_fix_features, 4720c5aff182SThomas Petazzoni .ndo_get_stats64 = mvneta_get_stats64, 472115f59456SThomas Petazzoni .ndo_do_ioctl = mvneta_ioctl, 47220db51da7SLorenzo Bianconi .ndo_bpf = mvneta_xdp, 4723b0a43db9SLorenzo Bianconi .ndo_xdp_xmit = mvneta_xdp_xmit, 4724c5aff182SThomas Petazzoni }; 4725c5aff182SThomas Petazzoni 47264581be42SJisheng Zhang static const struct ethtool_ops mvneta_eth_tool_ops = { 4727503f9aa9SRussell King .nway_reset = mvneta_ethtool_nway_reset, 4728c5aff182SThomas Petazzoni .get_link = ethtool_op_get_link, 4729c5aff182SThomas Petazzoni .set_coalesce = mvneta_ethtool_set_coalesce, 4730c5aff182SThomas Petazzoni .get_coalesce = mvneta_ethtool_get_coalesce, 4731c5aff182SThomas Petazzoni .get_drvinfo = mvneta_ethtool_get_drvinfo, 4732c5aff182SThomas Petazzoni .get_ringparam = mvneta_ethtool_get_ringparam, 4733c5aff182SThomas Petazzoni .set_ringparam = mvneta_ethtool_set_ringparam, 47344932a918SRussell King .get_pauseparam = mvneta_ethtool_get_pauseparam, 47354932a918SRussell King .set_pauseparam = mvneta_ethtool_set_pauseparam, 47369b0cdefaSRussell King .get_strings = mvneta_ethtool_get_strings, 47379b0cdefaSRussell King .get_ethtool_stats = mvneta_ethtool_get_stats, 47389b0cdefaSRussell King .get_sset_count = mvneta_ethtool_get_sset_count, 47399a401deaSGregory CLEMENT .get_rxfh_indir_size = mvneta_ethtool_get_rxfh_indir_size, 47409a401deaSGregory CLEMENT .get_rxnfc = mvneta_ethtool_get_rxnfc, 47419a401deaSGregory CLEMENT .get_rxfh = mvneta_ethtool_get_rxfh, 47429a401deaSGregory CLEMENT .set_rxfh = mvneta_ethtool_set_rxfh, 4743503f9aa9SRussell King .get_link_ksettings = mvneta_ethtool_get_link_ksettings, 4744013ad40dSPhilippe Reynes .set_link_ksettings = mvneta_ethtool_set_link_ksettings, 4745b60a00f9SJingju Hou .get_wol = mvneta_ethtool_get_wol, 4746b60a00f9SJingju Hou .set_wol = mvneta_ethtool_set_wol, 47476d81f451SRussell King .get_eee = mvneta_ethtool_get_eee, 47486d81f451SRussell King .set_eee = mvneta_ethtool_set_eee, 4749c5aff182SThomas Petazzoni }; 4750c5aff182SThomas Petazzoni 4751c5aff182SThomas Petazzoni /* Initialize hw */ 47529672850bSEzequiel Garcia static int mvneta_init(struct device *dev, struct mvneta_port *pp) 4753c5aff182SThomas Petazzoni { 4754c5aff182SThomas Petazzoni int queue; 4755c5aff182SThomas Petazzoni 4756c5aff182SThomas Petazzoni /* Disable port */ 4757c5aff182SThomas Petazzoni mvneta_port_disable(pp); 4758c5aff182SThomas Petazzoni 4759c5aff182SThomas Petazzoni /* Set port default values */ 4760c5aff182SThomas Petazzoni mvneta_defaults_set(pp); 4761c5aff182SThomas Petazzoni 47625d6312edSMarkus Elfring pp->txqs = devm_kcalloc(dev, txq_number, sizeof(*pp->txqs), GFP_KERNEL); 4763c5aff182SThomas Petazzoni if (!pp->txqs) 4764c5aff182SThomas Petazzoni return -ENOMEM; 4765c5aff182SThomas Petazzoni 4766c5aff182SThomas Petazzoni /* Initialize TX descriptor rings */ 4767c5aff182SThomas Petazzoni for (queue = 0; queue < txq_number; queue++) { 4768c5aff182SThomas Petazzoni struct mvneta_tx_queue *txq = &pp->txqs[queue]; 4769c5aff182SThomas Petazzoni txq->id = queue; 4770c5aff182SThomas Petazzoni txq->size = pp->tx_ring_size; 4771c5aff182SThomas Petazzoni txq->done_pkts_coal = MVNETA_TXDONE_COAL_PKTS; 4772c5aff182SThomas Petazzoni } 4773c5aff182SThomas Petazzoni 47745d6312edSMarkus Elfring pp->rxqs = devm_kcalloc(dev, rxq_number, sizeof(*pp->rxqs), GFP_KERNEL); 47759672850bSEzequiel Garcia if (!pp->rxqs) 4776c5aff182SThomas Petazzoni return -ENOMEM; 4777c5aff182SThomas Petazzoni 4778c5aff182SThomas Petazzoni /* Create Rx descriptor rings */ 4779c5aff182SThomas Petazzoni for (queue = 0; queue < rxq_number; queue++) { 4780c5aff182SThomas Petazzoni struct mvneta_rx_queue *rxq = &pp->rxqs[queue]; 4781c5aff182SThomas Petazzoni rxq->id = queue; 4782c5aff182SThomas Petazzoni rxq->size = pp->rx_ring_size; 4783c5aff182SThomas Petazzoni rxq->pkts_coal = MVNETA_RX_COAL_PKTS; 4784c5aff182SThomas Petazzoni rxq->time_coal = MVNETA_RX_COAL_USEC; 478529110630SMarkus Elfring rxq->buf_virt_addr 478629110630SMarkus Elfring = devm_kmalloc_array(pp->dev->dev.parent, 478729110630SMarkus Elfring rxq->size, 478829110630SMarkus Elfring sizeof(*rxq->buf_virt_addr), 4789f88bee1cSGregory CLEMENT GFP_KERNEL); 4790f88bee1cSGregory CLEMENT if (!rxq->buf_virt_addr) 4791f88bee1cSGregory CLEMENT return -ENOMEM; 4792c5aff182SThomas Petazzoni } 4793c5aff182SThomas Petazzoni 4794c5aff182SThomas Petazzoni return 0; 4795c5aff182SThomas Petazzoni } 4796c5aff182SThomas Petazzoni 4797c5aff182SThomas Petazzoni /* platform glue : initialize decoding windows */ 479803ce758eSGreg KH static void mvneta_conf_mbus_windows(struct mvneta_port *pp, 4799c5aff182SThomas Petazzoni const struct mbus_dram_target_info *dram) 4800c5aff182SThomas Petazzoni { 4801c5aff182SThomas Petazzoni u32 win_enable; 4802c5aff182SThomas Petazzoni u32 win_protect; 4803c5aff182SThomas Petazzoni int i; 4804c5aff182SThomas Petazzoni 4805c5aff182SThomas Petazzoni for (i = 0; i < 6; i++) { 4806c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_WIN_BASE(i), 0); 4807c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_WIN_SIZE(i), 0); 4808c5aff182SThomas Petazzoni 4809c5aff182SThomas Petazzoni if (i < 4) 4810c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_WIN_REMAP(i), 0); 4811c5aff182SThomas Petazzoni } 4812c5aff182SThomas Petazzoni 4813c5aff182SThomas Petazzoni win_enable = 0x3f; 4814c5aff182SThomas Petazzoni win_protect = 0; 4815c5aff182SThomas Petazzoni 48162636ac3cSMarcin Wojtas if (dram) { 4817c5aff182SThomas Petazzoni for (i = 0; i < dram->num_cs; i++) { 4818c5aff182SThomas Petazzoni const struct mbus_dram_window *cs = dram->cs + i; 48192636ac3cSMarcin Wojtas 48202636ac3cSMarcin Wojtas mvreg_write(pp, MVNETA_WIN_BASE(i), 48212636ac3cSMarcin Wojtas (cs->base & 0xffff0000) | 48222636ac3cSMarcin Wojtas (cs->mbus_attr << 8) | 48232636ac3cSMarcin Wojtas dram->mbus_dram_target_id); 4824c5aff182SThomas Petazzoni 4825c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_WIN_SIZE(i), 4826c5aff182SThomas Petazzoni (cs->size - 1) & 0xffff0000); 4827c5aff182SThomas Petazzoni 4828c5aff182SThomas Petazzoni win_enable &= ~(1 << i); 4829c5aff182SThomas Petazzoni win_protect |= 3 << (2 * i); 4830c5aff182SThomas Petazzoni } 48312636ac3cSMarcin Wojtas } else { 48322636ac3cSMarcin Wojtas /* For Armada3700 open default 4GB Mbus window, leaving 48332636ac3cSMarcin Wojtas * arbitration of target/attribute to a different layer 48342636ac3cSMarcin Wojtas * of configuration. 48352636ac3cSMarcin Wojtas */ 48362636ac3cSMarcin Wojtas mvreg_write(pp, MVNETA_WIN_SIZE(0), 0xffff0000); 48372636ac3cSMarcin Wojtas win_enable &= ~BIT(0); 48382636ac3cSMarcin Wojtas win_protect = 3; 48392636ac3cSMarcin Wojtas } 4840c5aff182SThomas Petazzoni 4841c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_BASE_ADDR_ENABLE, win_enable); 4842db6ba9a5SMarcin Wojtas mvreg_write(pp, MVNETA_ACCESS_PROTECT_ENABLE, win_protect); 4843c5aff182SThomas Petazzoni } 4844c5aff182SThomas Petazzoni 4845c5aff182SThomas Petazzoni /* Power up the port */ 48463f1dd4bcSThomas Petazzoni static int mvneta_port_power_up(struct mvneta_port *pp, int phy_mode) 4847c5aff182SThomas Petazzoni { 4848c5aff182SThomas Petazzoni /* MAC Cause register should be cleared */ 4849c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_UNIT_INTR_CAUSE, 0); 4850c5aff182SThomas Petazzoni 485132699954SRussell King if (phy_mode == PHY_INTERFACE_MODE_QSGMII) 48523f1dd4bcSThomas Petazzoni mvreg_write(pp, MVNETA_SERDES_CFG, MVNETA_QSGMII_SERDES_PROTO); 485322f4bf8aSRussell King else if (phy_mode == PHY_INTERFACE_MODE_SGMII || 4854a10c1c81SRussell King phy_interface_mode_is_8023z(phy_mode)) 48553f1dd4bcSThomas Petazzoni mvreg_write(pp, MVNETA_SERDES_CFG, MVNETA_SGMII_SERDES_PROTO); 485632699954SRussell King else if (!phy_interface_mode_is_rgmii(phy_mode)) 48573f1dd4bcSThomas Petazzoni return -EINVAL; 48583f1dd4bcSThomas Petazzoni 48593f1dd4bcSThomas Petazzoni return 0; 4860c5aff182SThomas Petazzoni } 4861c5aff182SThomas Petazzoni 4862c5aff182SThomas Petazzoni /* Device initialization routine */ 486303ce758eSGreg KH static int mvneta_probe(struct platform_device *pdev) 4864c5aff182SThomas Petazzoni { 4865c5aff182SThomas Petazzoni struct device_node *dn = pdev->dev.of_node; 4866dc35a10fSMarcin Wojtas struct device_node *bm_node; 4867c5aff182SThomas Petazzoni struct mvneta_port *pp; 4868c5aff182SThomas Petazzoni struct net_device *dev; 4869503f9aa9SRussell King struct phylink *phylink; 4870a10c1c81SRussell King struct phy *comphy; 48718cc3e439SThomas Petazzoni const char *dt_mac_addr; 48728cc3e439SThomas Petazzoni char hw_mac_addr[ETH_ALEN]; 48730c65b2b9SAndrew Lunn phy_interface_t phy_mode; 48748cc3e439SThomas Petazzoni const char *mac_from; 48759110ee07SMarcin Wojtas int tx_csum_limit; 4876c5aff182SThomas Petazzoni int err; 487712bb03b4SMaxime Ripard int cpu; 4878c5aff182SThomas Petazzoni 4879a3ddd94fSRosen Penev dev = devm_alloc_etherdev_mqs(&pdev->dev, sizeof(struct mvneta_port), 4880a3ddd94fSRosen Penev txq_number, rxq_number); 4881c5aff182SThomas Petazzoni if (!dev) 4882c5aff182SThomas Petazzoni return -ENOMEM; 4883c5aff182SThomas Petazzoni 4884c5aff182SThomas Petazzoni dev->irq = irq_of_parse_and_map(dn, 0); 4885a3ddd94fSRosen Penev if (dev->irq == 0) 4886a3ddd94fSRosen Penev return -EINVAL; 4887c5aff182SThomas Petazzoni 48880c65b2b9SAndrew Lunn err = of_get_phy_mode(dn, &phy_mode); 48890c65b2b9SAndrew Lunn if (err) { 4890c5aff182SThomas Petazzoni dev_err(&pdev->dev, "incorrect phy-mode\n"); 4891503f9aa9SRussell King goto err_free_irq; 4892503f9aa9SRussell King } 4893503f9aa9SRussell King 4894a10c1c81SRussell King comphy = devm_of_phy_get(&pdev->dev, dn, NULL); 4895a10c1c81SRussell King if (comphy == ERR_PTR(-EPROBE_DEFER)) { 4896a10c1c81SRussell King err = -EPROBE_DEFER; 4897a10c1c81SRussell King goto err_free_irq; 4898a10c1c81SRussell King } else if (IS_ERR(comphy)) { 4899a10c1c81SRussell King comphy = NULL; 4900a10c1c81SRussell King } 4901a10c1c81SRussell King 490244cc27e4SIoana Ciornei pp = netdev_priv(dev); 490344cc27e4SIoana Ciornei spin_lock_init(&pp->lock); 490444cc27e4SIoana Ciornei 490544cc27e4SIoana Ciornei pp->phylink_config.dev = &dev->dev; 490644cc27e4SIoana Ciornei pp->phylink_config.type = PHYLINK_NETDEV; 490744cc27e4SIoana Ciornei 490844cc27e4SIoana Ciornei phylink = phylink_create(&pp->phylink_config, pdev->dev.fwnode, 490944cc27e4SIoana Ciornei phy_mode, &mvneta_phylink_ops); 4910503f9aa9SRussell King if (IS_ERR(phylink)) { 4911503f9aa9SRussell King err = PTR_ERR(phylink); 4912503f9aa9SRussell King goto err_free_irq; 4913c5aff182SThomas Petazzoni } 4914c5aff182SThomas Petazzoni 4915c5aff182SThomas Petazzoni dev->tx_queue_len = MVNETA_MAX_TXD; 4916c5aff182SThomas Petazzoni dev->watchdog_timeo = 5 * HZ; 4917c5aff182SThomas Petazzoni dev->netdev_ops = &mvneta_netdev_ops; 4918c5aff182SThomas Petazzoni 49197ad24ea4SWilfried Klaebe dev->ethtool_ops = &mvneta_eth_tool_ops; 4920c5aff182SThomas Petazzoni 4921503f9aa9SRussell King pp->phylink = phylink; 4922a10c1c81SRussell King pp->comphy = comphy; 4923c5aff182SThomas Petazzoni pp->phy_interface = phy_mode; 4924503f9aa9SRussell King pp->dn = dn; 4925c5aff182SThomas Petazzoni 492690b74c01SGregory CLEMENT pp->rxq_def = rxq_def; 49279a401deaSGregory CLEMENT pp->indir[0] = rxq_def; 49289a401deaSGregory CLEMENT 49292636ac3cSMarcin Wojtas /* Get special SoC configurations */ 49302636ac3cSMarcin Wojtas if (of_device_is_compatible(dn, "marvell,armada-3700-neta")) 49312636ac3cSMarcin Wojtas pp->neta_armada3700 = true; 49322636ac3cSMarcin Wojtas 49332804ba4eSJisheng Zhang pp->clk = devm_clk_get(&pdev->dev, "core"); 49342804ba4eSJisheng Zhang if (IS_ERR(pp->clk)) 4935189dd626SThomas Petazzoni pp->clk = devm_clk_get(&pdev->dev, NULL); 4936189dd626SThomas Petazzoni if (IS_ERR(pp->clk)) { 4937189dd626SThomas Petazzoni err = PTR_ERR(pp->clk); 4938503f9aa9SRussell King goto err_free_phylink; 4939189dd626SThomas Petazzoni } 4940189dd626SThomas Petazzoni 4941189dd626SThomas Petazzoni clk_prepare_enable(pp->clk); 4942189dd626SThomas Petazzoni 494315cc4a4aSJisheng Zhang pp->clk_bus = devm_clk_get(&pdev->dev, "bus"); 494415cc4a4aSJisheng Zhang if (!IS_ERR(pp->clk_bus)) 494515cc4a4aSJisheng Zhang clk_prepare_enable(pp->clk_bus); 494615cc4a4aSJisheng Zhang 494700c33afbSJisheng Zhang pp->base = devm_platform_ioremap_resource(pdev, 0); 4948c3f0dd38SThomas Petazzoni if (IS_ERR(pp->base)) { 4949c3f0dd38SThomas Petazzoni err = PTR_ERR(pp->base); 49505445eaf3SArnaud Patard \(Rtp\) goto err_clk; 49515445eaf3SArnaud Patard \(Rtp\) } 49525445eaf3SArnaud Patard \(Rtp\) 495312bb03b4SMaxime Ripard /* Alloc per-cpu port structure */ 495412bb03b4SMaxime Ripard pp->ports = alloc_percpu(struct mvneta_pcpu_port); 495512bb03b4SMaxime Ripard if (!pp->ports) { 495612bb03b4SMaxime Ripard err = -ENOMEM; 495712bb03b4SMaxime Ripard goto err_clk; 495812bb03b4SMaxime Ripard } 495912bb03b4SMaxime Ripard 496074c41b04Swilly tarreau /* Alloc per-cpu stats */ 49611c213bd2SWANG Cong pp->stats = netdev_alloc_pcpu_stats(struct mvneta_pcpu_stats); 496274c41b04Swilly tarreau if (!pp->stats) { 496374c41b04Swilly tarreau err = -ENOMEM; 496412bb03b4SMaxime Ripard goto err_free_ports; 496574c41b04Swilly tarreau } 496674c41b04Swilly tarreau 49678cc3e439SThomas Petazzoni dt_mac_addr = of_get_mac_address(dn); 4968a51645f7SPetr Štetiar if (!IS_ERR(dt_mac_addr)) { 49698cc3e439SThomas Petazzoni mac_from = "device tree"; 49702d2924afSPetr Štetiar ether_addr_copy(dev->dev_addr, dt_mac_addr); 49718cc3e439SThomas Petazzoni } else { 49728cc3e439SThomas Petazzoni mvneta_get_mac_addr(pp, hw_mac_addr); 49738cc3e439SThomas Petazzoni if (is_valid_ether_addr(hw_mac_addr)) { 49748cc3e439SThomas Petazzoni mac_from = "hardware"; 49758cc3e439SThomas Petazzoni memcpy(dev->dev_addr, hw_mac_addr, ETH_ALEN); 49768cc3e439SThomas Petazzoni } else { 49778cc3e439SThomas Petazzoni mac_from = "random"; 49788cc3e439SThomas Petazzoni eth_hw_addr_random(dev); 49798cc3e439SThomas Petazzoni } 49808cc3e439SThomas Petazzoni } 49818cc3e439SThomas Petazzoni 49829110ee07SMarcin Wojtas if (!of_property_read_u32(dn, "tx-csum-limit", &tx_csum_limit)) { 49839110ee07SMarcin Wojtas if (tx_csum_limit < 0 || 49849110ee07SMarcin Wojtas tx_csum_limit > MVNETA_TX_CSUM_MAX_SIZE) { 49859110ee07SMarcin Wojtas tx_csum_limit = MVNETA_TX_CSUM_DEF_SIZE; 49869110ee07SMarcin Wojtas dev_info(&pdev->dev, 49879110ee07SMarcin Wojtas "Wrong TX csum limit in DT, set to %dB\n", 49889110ee07SMarcin Wojtas MVNETA_TX_CSUM_DEF_SIZE); 49899110ee07SMarcin Wojtas } 49909110ee07SMarcin Wojtas } else if (of_device_is_compatible(dn, "marvell,armada-370-neta")) { 49919110ee07SMarcin Wojtas tx_csum_limit = MVNETA_TX_CSUM_DEF_SIZE; 49929110ee07SMarcin Wojtas } else { 49939110ee07SMarcin Wojtas tx_csum_limit = MVNETA_TX_CSUM_MAX_SIZE; 49949110ee07SMarcin Wojtas } 49959110ee07SMarcin Wojtas 49969110ee07SMarcin Wojtas pp->tx_csum_limit = tx_csum_limit; 4997b65657fcSSimon Guinot 49989768b45cSJane Li pp->dram_target_info = mv_mbus_dram_info(); 49992636ac3cSMarcin Wojtas /* Armada3700 requires setting default configuration of Mbus 50002636ac3cSMarcin Wojtas * windows, however without using filled mbus_dram_target_info 50012636ac3cSMarcin Wojtas * structure. 50022636ac3cSMarcin Wojtas */ 50039768b45cSJane Li if (pp->dram_target_info || pp->neta_armada3700) 50049768b45cSJane Li mvneta_conf_mbus_windows(pp, pp->dram_target_info); 5005dc35a10fSMarcin Wojtas 5006c5aff182SThomas Petazzoni pp->tx_ring_size = MVNETA_MAX_TXD; 5007c5aff182SThomas Petazzoni pp->rx_ring_size = MVNETA_MAX_RXD; 5008c5aff182SThomas Petazzoni 5009c5aff182SThomas Petazzoni pp->dev = dev; 5010c5aff182SThomas Petazzoni SET_NETDEV_DEV(dev, &pdev->dev); 5011c5aff182SThomas Petazzoni 5012dc35a10fSMarcin Wojtas pp->id = global_port_id++; 5013dc35a10fSMarcin Wojtas 5014dc35a10fSMarcin Wojtas /* Obtain access to BM resources if enabled and already initialized */ 5015dc35a10fSMarcin Wojtas bm_node = of_parse_phandle(dn, "buffer-manager", 0); 5016965cbbecSGregory CLEMENT if (bm_node) { 5017965cbbecSGregory CLEMENT pp->bm_priv = mvneta_bm_get(bm_node); 5018965cbbecSGregory CLEMENT if (pp->bm_priv) { 5019dc35a10fSMarcin Wojtas err = mvneta_bm_port_init(pdev, pp); 5020dc35a10fSMarcin Wojtas if (err < 0) { 5021965cbbecSGregory CLEMENT dev_info(&pdev->dev, 5022965cbbecSGregory CLEMENT "use SW buffer management\n"); 5023965cbbecSGregory CLEMENT mvneta_bm_put(pp->bm_priv); 5024dc35a10fSMarcin Wojtas pp->bm_priv = NULL; 5025dc35a10fSMarcin Wojtas } 5026dc35a10fSMarcin Wojtas } 5027562e2f46SYelena Krivosheev /* Set RX packet offset correction for platforms, whose 5028562e2f46SYelena Krivosheev * NET_SKB_PAD, exceeds 64B. It should be 64B for 64-bit 5029562e2f46SYelena Krivosheev * platforms and 0B for 32-bit ones. 5030562e2f46SYelena Krivosheev */ 5031562e2f46SYelena Krivosheev pp->rx_offset_correction = max(0, 5032562e2f46SYelena Krivosheev NET_SKB_PAD - 5033562e2f46SYelena Krivosheev MVNETA_RX_PKT_OFFSET_CORRECTION); 5034965cbbecSGregory CLEMENT } 5035d4e4da00SPeter Chen of_node_put(bm_node); 5036dc35a10fSMarcin Wojtas 503744efc78dSLorenzo Bianconi /* sw buffer management */ 503844efc78dSLorenzo Bianconi if (!pp->bm_priv) 503944efc78dSLorenzo Bianconi pp->rx_offset_correction = MVNETA_SKB_HEADROOM; 504044efc78dSLorenzo Bianconi 50419672850bSEzequiel Garcia err = mvneta_init(&pdev->dev, pp); 50429672850bSEzequiel Garcia if (err < 0) 5043dc35a10fSMarcin Wojtas goto err_netdev; 50443f1dd4bcSThomas Petazzoni 50453f1dd4bcSThomas Petazzoni err = mvneta_port_power_up(pp, phy_mode); 50463f1dd4bcSThomas Petazzoni if (err < 0) { 50473f1dd4bcSThomas Petazzoni dev_err(&pdev->dev, "can't power up port\n"); 5048dc35a10fSMarcin Wojtas goto err_netdev; 50493f1dd4bcSThomas Petazzoni } 5050c5aff182SThomas Petazzoni 50512636ac3cSMarcin Wojtas /* Armada3700 network controller does not support per-cpu 50522636ac3cSMarcin Wojtas * operation, so only single NAPI should be initialized. 50532636ac3cSMarcin Wojtas */ 50542636ac3cSMarcin Wojtas if (pp->neta_armada3700) { 50552636ac3cSMarcin Wojtas netif_napi_add(dev, &pp->napi, mvneta_poll, NAPI_POLL_WEIGHT); 50562636ac3cSMarcin Wojtas } else { 505712bb03b4SMaxime Ripard for_each_present_cpu(cpu) { 50582636ac3cSMarcin Wojtas struct mvneta_pcpu_port *port = 50592636ac3cSMarcin Wojtas per_cpu_ptr(pp->ports, cpu); 506012bb03b4SMaxime Ripard 50612636ac3cSMarcin Wojtas netif_napi_add(dev, &port->napi, mvneta_poll, 50622636ac3cSMarcin Wojtas NAPI_POLL_WEIGHT); 506312bb03b4SMaxime Ripard port->pp = pp; 506412bb03b4SMaxime Ripard } 50652636ac3cSMarcin Wojtas } 5066c5aff182SThomas Petazzoni 50677772988aSJisheng Zhang dev->features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | 50687772988aSJisheng Zhang NETIF_F_TSO | NETIF_F_RXCSUM; 506901ef26caSEzequiel Garcia dev->hw_features |= dev->features; 507001ef26caSEzequiel Garcia dev->vlan_features |= dev->features; 507197db8afaSAndrew Lunn dev->priv_flags |= IFF_LIVE_ADDR_CHANGE; 50728eef5f97SEzequiel Garcia dev->gso_max_segs = MVNETA_MAX_TSO_SEGS; 5073b50b72deSwilly tarreau 50745777987eSJarod Wilson /* MTU range: 68 - 9676 */ 50755777987eSJarod Wilson dev->min_mtu = ETH_MIN_MTU; 50765777987eSJarod Wilson /* 9676 == 9700 - 20 and rounding to 8 */ 50775777987eSJarod Wilson dev->max_mtu = 9676; 50785777987eSJarod Wilson 5079c5aff182SThomas Petazzoni err = register_netdev(dev); 5080c5aff182SThomas Petazzoni if (err < 0) { 5081c5aff182SThomas Petazzoni dev_err(&pdev->dev, "failed to register\n"); 5082d484e06eSJisheng Zhang goto err_netdev; 5083c5aff182SThomas Petazzoni } 5084c5aff182SThomas Petazzoni 50858cc3e439SThomas Petazzoni netdev_info(dev, "Using %s mac address %pM\n", mac_from, 50868cc3e439SThomas Petazzoni dev->dev_addr); 5087c5aff182SThomas Petazzoni 5088c5aff182SThomas Petazzoni platform_set_drvdata(pdev, pp->dev); 5089c5aff182SThomas Petazzoni 5090c5aff182SThomas Petazzoni return 0; 5091c5aff182SThomas Petazzoni 5092dc35a10fSMarcin Wojtas err_netdev: 5093dc35a10fSMarcin Wojtas if (pp->bm_priv) { 5094dc35a10fSMarcin Wojtas mvneta_bm_pool_destroy(pp->bm_priv, pp->pool_long, 1 << pp->id); 5095dc35a10fSMarcin Wojtas mvneta_bm_pool_destroy(pp->bm_priv, pp->pool_short, 5096dc35a10fSMarcin Wojtas 1 << pp->id); 5097965cbbecSGregory CLEMENT mvneta_bm_put(pp->bm_priv); 5098dc35a10fSMarcin Wojtas } 509974c41b04Swilly tarreau free_percpu(pp->stats); 510012bb03b4SMaxime Ripard err_free_ports: 510112bb03b4SMaxime Ripard free_percpu(pp->ports); 51025445eaf3SArnaud Patard \(Rtp\) err_clk: 510315cc4a4aSJisheng Zhang clk_disable_unprepare(pp->clk_bus); 51045445eaf3SArnaud Patard \(Rtp\) clk_disable_unprepare(pp->clk); 5105503f9aa9SRussell King err_free_phylink: 5106503f9aa9SRussell King if (pp->phylink) 5107503f9aa9SRussell King phylink_destroy(pp->phylink); 5108c5aff182SThomas Petazzoni err_free_irq: 5109c5aff182SThomas Petazzoni irq_dispose_mapping(dev->irq); 5110c5aff182SThomas Petazzoni return err; 5111c5aff182SThomas Petazzoni } 5112c5aff182SThomas Petazzoni 5113c5aff182SThomas Petazzoni /* Device removal routine */ 511403ce758eSGreg KH static int mvneta_remove(struct platform_device *pdev) 5115c5aff182SThomas Petazzoni { 5116c5aff182SThomas Petazzoni struct net_device *dev = platform_get_drvdata(pdev); 5117c5aff182SThomas Petazzoni struct mvneta_port *pp = netdev_priv(dev); 5118c5aff182SThomas Petazzoni 5119c5aff182SThomas Petazzoni unregister_netdev(dev); 512015cc4a4aSJisheng Zhang clk_disable_unprepare(pp->clk_bus); 5121189dd626SThomas Petazzoni clk_disable_unprepare(pp->clk); 512212bb03b4SMaxime Ripard free_percpu(pp->ports); 512374c41b04Swilly tarreau free_percpu(pp->stats); 5124c5aff182SThomas Petazzoni irq_dispose_mapping(dev->irq); 5125503f9aa9SRussell King phylink_destroy(pp->phylink); 5126c5aff182SThomas Petazzoni 5127dc35a10fSMarcin Wojtas if (pp->bm_priv) { 5128dc35a10fSMarcin Wojtas mvneta_bm_pool_destroy(pp->bm_priv, pp->pool_long, 1 << pp->id); 5129dc35a10fSMarcin Wojtas mvneta_bm_pool_destroy(pp->bm_priv, pp->pool_short, 5130dc35a10fSMarcin Wojtas 1 << pp->id); 5131965cbbecSGregory CLEMENT mvneta_bm_put(pp->bm_priv); 5132dc35a10fSMarcin Wojtas } 5133dc35a10fSMarcin Wojtas 5134c5aff182SThomas Petazzoni return 0; 5135c5aff182SThomas Petazzoni } 5136c5aff182SThomas Petazzoni 51379768b45cSJane Li #ifdef CONFIG_PM_SLEEP 51389768b45cSJane Li static int mvneta_suspend(struct device *device) 51399768b45cSJane Li { 51401799cdd2SJisheng Zhang int queue; 51419768b45cSJane Li struct net_device *dev = dev_get_drvdata(device); 51429768b45cSJane Li struct mvneta_port *pp = netdev_priv(dev); 51439768b45cSJane Li 51441799cdd2SJisheng Zhang if (!netif_running(dev)) 51451799cdd2SJisheng Zhang goto clean_exit; 51461799cdd2SJisheng Zhang 51471799cdd2SJisheng Zhang if (!pp->neta_armada3700) { 51481799cdd2SJisheng Zhang spin_lock(&pp->lock); 51491799cdd2SJisheng Zhang pp->is_stopped = true; 51501799cdd2SJisheng Zhang spin_unlock(&pp->lock); 51511799cdd2SJisheng Zhang 51521799cdd2SJisheng Zhang cpuhp_state_remove_instance_nocalls(online_hpstate, 51531799cdd2SJisheng Zhang &pp->node_online); 51541799cdd2SJisheng Zhang cpuhp_state_remove_instance_nocalls(CPUHP_NET_MVNETA_DEAD, 51551799cdd2SJisheng Zhang &pp->node_dead); 51561799cdd2SJisheng Zhang } 51571799cdd2SJisheng Zhang 51583b8bc674SRussell King rtnl_lock(); 51591799cdd2SJisheng Zhang mvneta_stop_dev(pp); 51603b8bc674SRussell King rtnl_unlock(); 51611799cdd2SJisheng Zhang 51621799cdd2SJisheng Zhang for (queue = 0; queue < rxq_number; queue++) { 51631799cdd2SJisheng Zhang struct mvneta_rx_queue *rxq = &pp->rxqs[queue]; 51641799cdd2SJisheng Zhang 51651799cdd2SJisheng Zhang mvneta_rxq_drop_pkts(pp, rxq); 51661799cdd2SJisheng Zhang } 51671799cdd2SJisheng Zhang 51681799cdd2SJisheng Zhang for (queue = 0; queue < txq_number; queue++) { 51691799cdd2SJisheng Zhang struct mvneta_tx_queue *txq = &pp->txqs[queue]; 51701799cdd2SJisheng Zhang 51711799cdd2SJisheng Zhang mvneta_txq_hw_deinit(pp, txq); 51721799cdd2SJisheng Zhang } 51731799cdd2SJisheng Zhang 51741799cdd2SJisheng Zhang clean_exit: 51759768b45cSJane Li netif_device_detach(dev); 51769768b45cSJane Li clk_disable_unprepare(pp->clk_bus); 51779768b45cSJane Li clk_disable_unprepare(pp->clk); 51781799cdd2SJisheng Zhang 51799768b45cSJane Li return 0; 51809768b45cSJane Li } 51819768b45cSJane Li 51829768b45cSJane Li static int mvneta_resume(struct device *device) 51839768b45cSJane Li { 51849768b45cSJane Li struct platform_device *pdev = to_platform_device(device); 51859768b45cSJane Li struct net_device *dev = dev_get_drvdata(device); 51869768b45cSJane Li struct mvneta_port *pp = netdev_priv(dev); 51871799cdd2SJisheng Zhang int err, queue; 51889768b45cSJane Li 51899768b45cSJane Li clk_prepare_enable(pp->clk); 51909768b45cSJane Li if (!IS_ERR(pp->clk_bus)) 51919768b45cSJane Li clk_prepare_enable(pp->clk_bus); 51929768b45cSJane Li if (pp->dram_target_info || pp->neta_armada3700) 51939768b45cSJane Li mvneta_conf_mbus_windows(pp, pp->dram_target_info); 51949768b45cSJane Li if (pp->bm_priv) { 51959768b45cSJane Li err = mvneta_bm_port_init(pdev, pp); 51969768b45cSJane Li if (err < 0) { 51979768b45cSJane Li dev_info(&pdev->dev, "use SW buffer management\n"); 519844efc78dSLorenzo Bianconi pp->rx_offset_correction = MVNETA_SKB_HEADROOM; 51999768b45cSJane Li pp->bm_priv = NULL; 52009768b45cSJane Li } 52019768b45cSJane Li } 52029768b45cSJane Li mvneta_defaults_set(pp); 52039768b45cSJane Li err = mvneta_port_power_up(pp, pp->phy_interface); 52049768b45cSJane Li if (err < 0) { 52059768b45cSJane Li dev_err(device, "can't power up port\n"); 52069768b45cSJane Li return err; 52079768b45cSJane Li } 52089768b45cSJane Li 52099768b45cSJane Li netif_device_attach(dev); 52101799cdd2SJisheng Zhang 52111799cdd2SJisheng Zhang if (!netif_running(dev)) 52121799cdd2SJisheng Zhang return 0; 52131799cdd2SJisheng Zhang 52141799cdd2SJisheng Zhang for (queue = 0; queue < rxq_number; queue++) { 52151799cdd2SJisheng Zhang struct mvneta_rx_queue *rxq = &pp->rxqs[queue]; 52161799cdd2SJisheng Zhang 52171799cdd2SJisheng Zhang rxq->next_desc_to_proc = 0; 52181799cdd2SJisheng Zhang mvneta_rxq_hw_init(pp, rxq); 5219d6956ac8SJisheng Zhang } 52201799cdd2SJisheng Zhang 52211799cdd2SJisheng Zhang for (queue = 0; queue < txq_number; queue++) { 52221799cdd2SJisheng Zhang struct mvneta_tx_queue *txq = &pp->txqs[queue]; 52231799cdd2SJisheng Zhang 52241799cdd2SJisheng Zhang txq->next_desc_to_proc = 0; 52251799cdd2SJisheng Zhang mvneta_txq_hw_init(pp, txq); 52261799cdd2SJisheng Zhang } 52271799cdd2SJisheng Zhang 52281799cdd2SJisheng Zhang if (!pp->neta_armada3700) { 52291799cdd2SJisheng Zhang spin_lock(&pp->lock); 52301799cdd2SJisheng Zhang pp->is_stopped = false; 52311799cdd2SJisheng Zhang spin_unlock(&pp->lock); 52321799cdd2SJisheng Zhang cpuhp_state_add_instance_nocalls(online_hpstate, 52331799cdd2SJisheng Zhang &pp->node_online); 52341799cdd2SJisheng Zhang cpuhp_state_add_instance_nocalls(CPUHP_NET_MVNETA_DEAD, 52351799cdd2SJisheng Zhang &pp->node_dead); 52361799cdd2SJisheng Zhang } 52371799cdd2SJisheng Zhang 52381799cdd2SJisheng Zhang rtnl_lock(); 52391799cdd2SJisheng Zhang mvneta_start_dev(pp); 52403b8bc674SRussell King rtnl_unlock(); 52411799cdd2SJisheng Zhang mvneta_set_rx_mode(dev); 5242d6956ac8SJisheng Zhang 52439768b45cSJane Li return 0; 52449768b45cSJane Li } 52459768b45cSJane Li #endif 52469768b45cSJane Li 52479768b45cSJane Li static SIMPLE_DEV_PM_OPS(mvneta_pm_ops, mvneta_suspend, mvneta_resume); 52489768b45cSJane Li 5249c5aff182SThomas Petazzoni static const struct of_device_id mvneta_match[] = { 5250c5aff182SThomas Petazzoni { .compatible = "marvell,armada-370-neta" }, 5251f522a975SSimon Guinot { .compatible = "marvell,armada-xp-neta" }, 52522636ac3cSMarcin Wojtas { .compatible = "marvell,armada-3700-neta" }, 5253c5aff182SThomas Petazzoni { } 5254c5aff182SThomas Petazzoni }; 5255c5aff182SThomas Petazzoni MODULE_DEVICE_TABLE(of, mvneta_match); 5256c5aff182SThomas Petazzoni 5257c5aff182SThomas Petazzoni static struct platform_driver mvneta_driver = { 5258c5aff182SThomas Petazzoni .probe = mvneta_probe, 525903ce758eSGreg KH .remove = mvneta_remove, 5260c5aff182SThomas Petazzoni .driver = { 5261c5aff182SThomas Petazzoni .name = MVNETA_DRIVER_NAME, 5262c5aff182SThomas Petazzoni .of_match_table = mvneta_match, 52639768b45cSJane Li .pm = &mvneta_pm_ops, 5264c5aff182SThomas Petazzoni }, 5265c5aff182SThomas Petazzoni }; 5266c5aff182SThomas Petazzoni 526784a3f4dbSSebastian Andrzej Siewior static int __init mvneta_driver_init(void) 526884a3f4dbSSebastian Andrzej Siewior { 526984a3f4dbSSebastian Andrzej Siewior int ret; 527084a3f4dbSSebastian Andrzej Siewior 527184a3f4dbSSebastian Andrzej Siewior ret = cpuhp_setup_state_multi(CPUHP_AP_ONLINE_DYN, "net/mvmeta:online", 527284a3f4dbSSebastian Andrzej Siewior mvneta_cpu_online, 527384a3f4dbSSebastian Andrzej Siewior mvneta_cpu_down_prepare); 527484a3f4dbSSebastian Andrzej Siewior if (ret < 0) 527584a3f4dbSSebastian Andrzej Siewior goto out; 527684a3f4dbSSebastian Andrzej Siewior online_hpstate = ret; 527784a3f4dbSSebastian Andrzej Siewior ret = cpuhp_setup_state_multi(CPUHP_NET_MVNETA_DEAD, "net/mvneta:dead", 527884a3f4dbSSebastian Andrzej Siewior NULL, mvneta_cpu_dead); 527984a3f4dbSSebastian Andrzej Siewior if (ret) 528084a3f4dbSSebastian Andrzej Siewior goto err_dead; 528184a3f4dbSSebastian Andrzej Siewior 528284a3f4dbSSebastian Andrzej Siewior ret = platform_driver_register(&mvneta_driver); 528384a3f4dbSSebastian Andrzej Siewior if (ret) 528484a3f4dbSSebastian Andrzej Siewior goto err; 528584a3f4dbSSebastian Andrzej Siewior return 0; 528684a3f4dbSSebastian Andrzej Siewior 528784a3f4dbSSebastian Andrzej Siewior err: 528884a3f4dbSSebastian Andrzej Siewior cpuhp_remove_multi_state(CPUHP_NET_MVNETA_DEAD); 528984a3f4dbSSebastian Andrzej Siewior err_dead: 529084a3f4dbSSebastian Andrzej Siewior cpuhp_remove_multi_state(online_hpstate); 529184a3f4dbSSebastian Andrzej Siewior out: 529284a3f4dbSSebastian Andrzej Siewior return ret; 529384a3f4dbSSebastian Andrzej Siewior } 529484a3f4dbSSebastian Andrzej Siewior module_init(mvneta_driver_init); 529584a3f4dbSSebastian Andrzej Siewior 529684a3f4dbSSebastian Andrzej Siewior static void __exit mvneta_driver_exit(void) 529784a3f4dbSSebastian Andrzej Siewior { 529884a3f4dbSSebastian Andrzej Siewior platform_driver_unregister(&mvneta_driver); 529984a3f4dbSSebastian Andrzej Siewior cpuhp_remove_multi_state(CPUHP_NET_MVNETA_DEAD); 530084a3f4dbSSebastian Andrzej Siewior cpuhp_remove_multi_state(online_hpstate); 530184a3f4dbSSebastian Andrzej Siewior } 530284a3f4dbSSebastian Andrzej Siewior module_exit(mvneta_driver_exit); 5303c5aff182SThomas Petazzoni 5304c5aff182SThomas Petazzoni MODULE_DESCRIPTION("Marvell NETA Ethernet Driver - www.marvell.com"); 5305c5aff182SThomas Petazzoni MODULE_AUTHOR("Rami Rosen <rosenr@marvell.com>, Thomas Petazzoni <thomas.petazzoni@free-electrons.com>"); 5306c5aff182SThomas Petazzoni MODULE_LICENSE("GPL"); 5307c5aff182SThomas Petazzoni 5308d3757ba4SJoe Perches module_param(rxq_number, int, 0444); 5309d3757ba4SJoe Perches module_param(txq_number, int, 0444); 5310c5aff182SThomas Petazzoni 5311d3757ba4SJoe Perches module_param(rxq_def, int, 0444); 5312d3757ba4SJoe Perches module_param(rx_copybreak, int, 0644); 5313