1c5aff182SThomas Petazzoni /* 2c5aff182SThomas Petazzoni * Driver for Marvell NETA network card for Armada XP and Armada 370 SoCs. 3c5aff182SThomas Petazzoni * 4c5aff182SThomas Petazzoni * Copyright (C) 2012 Marvell 5c5aff182SThomas Petazzoni * 6c5aff182SThomas Petazzoni * Rami Rosen <rosenr@marvell.com> 7c5aff182SThomas Petazzoni * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> 8c5aff182SThomas Petazzoni * 9c5aff182SThomas Petazzoni * This file is licensed under the terms of the GNU General Public 10c5aff182SThomas Petazzoni * License version 2. This program is licensed "as is" without any 11c5aff182SThomas Petazzoni * warranty of any kind, whether express or implied. 12c5aff182SThomas Petazzoni */ 13c5aff182SThomas Petazzoni 14c5aff182SThomas Petazzoni #include <linux/kernel.h> 15c5aff182SThomas Petazzoni #include <linux/netdevice.h> 16c5aff182SThomas Petazzoni #include <linux/etherdevice.h> 17c5aff182SThomas Petazzoni #include <linux/platform_device.h> 18c5aff182SThomas Petazzoni #include <linux/skbuff.h> 19c5aff182SThomas Petazzoni #include <linux/inetdevice.h> 20c5aff182SThomas Petazzoni #include <linux/mbus.h> 21c5aff182SThomas Petazzoni #include <linux/module.h> 22c5aff182SThomas Petazzoni #include <linux/interrupt.h> 23c5aff182SThomas Petazzoni #include <net/ip.h> 24c5aff182SThomas Petazzoni #include <net/ipv6.h> 25c5aff182SThomas Petazzoni #include <linux/of.h> 26c5aff182SThomas Petazzoni #include <linux/of_irq.h> 27c5aff182SThomas Petazzoni #include <linux/of_mdio.h> 28c5aff182SThomas Petazzoni #include <linux/of_net.h> 29c5aff182SThomas Petazzoni #include <linux/of_address.h> 30c5aff182SThomas Petazzoni #include <linux/phy.h> 31189dd626SThomas Petazzoni #include <linux/clk.h> 32c5aff182SThomas Petazzoni 33c5aff182SThomas Petazzoni /* Registers */ 34c5aff182SThomas Petazzoni #define MVNETA_RXQ_CONFIG_REG(q) (0x1400 + ((q) << 2)) 35c5aff182SThomas Petazzoni #define MVNETA_RXQ_HW_BUF_ALLOC BIT(1) 36c5aff182SThomas Petazzoni #define MVNETA_RXQ_PKT_OFFSET_ALL_MASK (0xf << 8) 37c5aff182SThomas Petazzoni #define MVNETA_RXQ_PKT_OFFSET_MASK(offs) ((offs) << 8) 38c5aff182SThomas Petazzoni #define MVNETA_RXQ_THRESHOLD_REG(q) (0x14c0 + ((q) << 2)) 39c5aff182SThomas Petazzoni #define MVNETA_RXQ_NON_OCCUPIED(v) ((v) << 16) 40c5aff182SThomas Petazzoni #define MVNETA_RXQ_BASE_ADDR_REG(q) (0x1480 + ((q) << 2)) 41c5aff182SThomas Petazzoni #define MVNETA_RXQ_SIZE_REG(q) (0x14a0 + ((q) << 2)) 42c5aff182SThomas Petazzoni #define MVNETA_RXQ_BUF_SIZE_SHIFT 19 43c5aff182SThomas Petazzoni #define MVNETA_RXQ_BUF_SIZE_MASK (0x1fff << 19) 44c5aff182SThomas Petazzoni #define MVNETA_RXQ_STATUS_REG(q) (0x14e0 + ((q) << 2)) 45c5aff182SThomas Petazzoni #define MVNETA_RXQ_OCCUPIED_ALL_MASK 0x3fff 46c5aff182SThomas Petazzoni #define MVNETA_RXQ_STATUS_UPDATE_REG(q) (0x1500 + ((q) << 2)) 47c5aff182SThomas Petazzoni #define MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT 16 48c5aff182SThomas Petazzoni #define MVNETA_RXQ_ADD_NON_OCCUPIED_MAX 255 49c5aff182SThomas Petazzoni #define MVNETA_PORT_RX_RESET 0x1cc0 50c5aff182SThomas Petazzoni #define MVNETA_PORT_RX_DMA_RESET BIT(0) 51c5aff182SThomas Petazzoni #define MVNETA_PHY_ADDR 0x2000 52c5aff182SThomas Petazzoni #define MVNETA_PHY_ADDR_MASK 0x1f 53c5aff182SThomas Petazzoni #define MVNETA_MBUS_RETRY 0x2010 54c5aff182SThomas Petazzoni #define MVNETA_UNIT_INTR_CAUSE 0x2080 55c5aff182SThomas Petazzoni #define MVNETA_UNIT_CONTROL 0x20B0 56c5aff182SThomas Petazzoni #define MVNETA_PHY_POLLING_ENABLE BIT(1) 57c5aff182SThomas Petazzoni #define MVNETA_WIN_BASE(w) (0x2200 + ((w) << 3)) 58c5aff182SThomas Petazzoni #define MVNETA_WIN_SIZE(w) (0x2204 + ((w) << 3)) 59c5aff182SThomas Petazzoni #define MVNETA_WIN_REMAP(w) (0x2280 + ((w) << 2)) 60c5aff182SThomas Petazzoni #define MVNETA_BASE_ADDR_ENABLE 0x2290 61c5aff182SThomas Petazzoni #define MVNETA_PORT_CONFIG 0x2400 62c5aff182SThomas Petazzoni #define MVNETA_UNI_PROMISC_MODE BIT(0) 63c5aff182SThomas Petazzoni #define MVNETA_DEF_RXQ(q) ((q) << 1) 64c5aff182SThomas Petazzoni #define MVNETA_DEF_RXQ_ARP(q) ((q) << 4) 65c5aff182SThomas Petazzoni #define MVNETA_TX_UNSET_ERR_SUM BIT(12) 66c5aff182SThomas Petazzoni #define MVNETA_DEF_RXQ_TCP(q) ((q) << 16) 67c5aff182SThomas Petazzoni #define MVNETA_DEF_RXQ_UDP(q) ((q) << 19) 68c5aff182SThomas Petazzoni #define MVNETA_DEF_RXQ_BPDU(q) ((q) << 22) 69c5aff182SThomas Petazzoni #define MVNETA_RX_CSUM_WITH_PSEUDO_HDR BIT(25) 70c5aff182SThomas Petazzoni #define MVNETA_PORT_CONFIG_DEFL_VALUE(q) (MVNETA_DEF_RXQ(q) | \ 71c5aff182SThomas Petazzoni MVNETA_DEF_RXQ_ARP(q) | \ 72c5aff182SThomas Petazzoni MVNETA_DEF_RXQ_TCP(q) | \ 73c5aff182SThomas Petazzoni MVNETA_DEF_RXQ_UDP(q) | \ 74c5aff182SThomas Petazzoni MVNETA_DEF_RXQ_BPDU(q) | \ 75c5aff182SThomas Petazzoni MVNETA_TX_UNSET_ERR_SUM | \ 76c5aff182SThomas Petazzoni MVNETA_RX_CSUM_WITH_PSEUDO_HDR) 77c5aff182SThomas Petazzoni #define MVNETA_PORT_CONFIG_EXTEND 0x2404 78c5aff182SThomas Petazzoni #define MVNETA_MAC_ADDR_LOW 0x2414 79c5aff182SThomas Petazzoni #define MVNETA_MAC_ADDR_HIGH 0x2418 80c5aff182SThomas Petazzoni #define MVNETA_SDMA_CONFIG 0x241c 81c5aff182SThomas Petazzoni #define MVNETA_SDMA_BRST_SIZE_16 4 82c5aff182SThomas Petazzoni #define MVNETA_RX_BRST_SZ_MASK(burst) ((burst) << 1) 83c5aff182SThomas Petazzoni #define MVNETA_RX_NO_DATA_SWAP BIT(4) 84c5aff182SThomas Petazzoni #define MVNETA_TX_NO_DATA_SWAP BIT(5) 859ad8fef6SThomas Petazzoni #define MVNETA_DESC_SWAP BIT(6) 86c5aff182SThomas Petazzoni #define MVNETA_TX_BRST_SZ_MASK(burst) ((burst) << 22) 87c5aff182SThomas Petazzoni #define MVNETA_PORT_STATUS 0x2444 88c5aff182SThomas Petazzoni #define MVNETA_TX_IN_PRGRS BIT(1) 89c5aff182SThomas Petazzoni #define MVNETA_TX_FIFO_EMPTY BIT(8) 90c5aff182SThomas Petazzoni #define MVNETA_RX_MIN_FRAME_SIZE 0x247c 915445eaf3SArnaud Patard \(Rtp\) #define MVNETA_SGMII_SERDES_CFG 0x24A0 925445eaf3SArnaud Patard \(Rtp\) #define MVNETA_SGMII_SERDES_PROTO 0x0cc7 93c5aff182SThomas Petazzoni #define MVNETA_TYPE_PRIO 0x24bc 94c5aff182SThomas Petazzoni #define MVNETA_FORCE_UNI BIT(21) 95c5aff182SThomas Petazzoni #define MVNETA_TXQ_CMD_1 0x24e4 96c5aff182SThomas Petazzoni #define MVNETA_TXQ_CMD 0x2448 97c5aff182SThomas Petazzoni #define MVNETA_TXQ_DISABLE_SHIFT 8 98c5aff182SThomas Petazzoni #define MVNETA_TXQ_ENABLE_MASK 0x000000ff 99c5aff182SThomas Petazzoni #define MVNETA_ACC_MODE 0x2500 100c5aff182SThomas Petazzoni #define MVNETA_CPU_MAP(cpu) (0x2540 + ((cpu) << 2)) 101c5aff182SThomas Petazzoni #define MVNETA_CPU_RXQ_ACCESS_ALL_MASK 0x000000ff 102c5aff182SThomas Petazzoni #define MVNETA_CPU_TXQ_ACCESS_ALL_MASK 0x0000ff00 103c5aff182SThomas Petazzoni #define MVNETA_RXQ_TIME_COAL_REG(q) (0x2580 + ((q) << 2)) 10440ba35e7Swilly tarreau 10540ba35e7Swilly tarreau /* Exception Interrupt Port/Queue Cause register */ 10640ba35e7Swilly tarreau 107c5aff182SThomas Petazzoni #define MVNETA_INTR_NEW_CAUSE 0x25a0 108c5aff182SThomas Petazzoni #define MVNETA_INTR_NEW_MASK 0x25a4 10940ba35e7Swilly tarreau 11040ba35e7Swilly tarreau /* bits 0..7 = TXQ SENT, one bit per queue. 11140ba35e7Swilly tarreau * bits 8..15 = RXQ OCCUP, one bit per queue. 11240ba35e7Swilly tarreau * bits 16..23 = RXQ FREE, one bit per queue. 11340ba35e7Swilly tarreau * bit 29 = OLD_REG_SUM, see old reg ? 11440ba35e7Swilly tarreau * bit 30 = TX_ERR_SUM, one bit for 4 ports 11540ba35e7Swilly tarreau * bit 31 = MISC_SUM, one bit for 4 ports 11640ba35e7Swilly tarreau */ 11740ba35e7Swilly tarreau #define MVNETA_TX_INTR_MASK(nr_txqs) (((1 << nr_txqs) - 1) << 0) 11840ba35e7Swilly tarreau #define MVNETA_TX_INTR_MASK_ALL (0xff << 0) 11940ba35e7Swilly tarreau #define MVNETA_RX_INTR_MASK(nr_rxqs) (((1 << nr_rxqs) - 1) << 8) 12040ba35e7Swilly tarreau #define MVNETA_RX_INTR_MASK_ALL (0xff << 8) 12140ba35e7Swilly tarreau 122c5aff182SThomas Petazzoni #define MVNETA_INTR_OLD_CAUSE 0x25a8 123c5aff182SThomas Petazzoni #define MVNETA_INTR_OLD_MASK 0x25ac 12440ba35e7Swilly tarreau 12540ba35e7Swilly tarreau /* Data Path Port/Queue Cause Register */ 126c5aff182SThomas Petazzoni #define MVNETA_INTR_MISC_CAUSE 0x25b0 127c5aff182SThomas Petazzoni #define MVNETA_INTR_MISC_MASK 0x25b4 12840ba35e7Swilly tarreau 12940ba35e7Swilly tarreau #define MVNETA_CAUSE_PHY_STATUS_CHANGE BIT(0) 13040ba35e7Swilly tarreau #define MVNETA_CAUSE_LINK_CHANGE BIT(1) 13140ba35e7Swilly tarreau #define MVNETA_CAUSE_PTP BIT(4) 13240ba35e7Swilly tarreau 13340ba35e7Swilly tarreau #define MVNETA_CAUSE_INTERNAL_ADDR_ERR BIT(7) 13440ba35e7Swilly tarreau #define MVNETA_CAUSE_RX_OVERRUN BIT(8) 13540ba35e7Swilly tarreau #define MVNETA_CAUSE_RX_CRC_ERROR BIT(9) 13640ba35e7Swilly tarreau #define MVNETA_CAUSE_RX_LARGE_PKT BIT(10) 13740ba35e7Swilly tarreau #define MVNETA_CAUSE_TX_UNDERUN BIT(11) 13840ba35e7Swilly tarreau #define MVNETA_CAUSE_PRBS_ERR BIT(12) 13940ba35e7Swilly tarreau #define MVNETA_CAUSE_PSC_SYNC_CHANGE BIT(13) 14040ba35e7Swilly tarreau #define MVNETA_CAUSE_SERDES_SYNC_ERR BIT(14) 14140ba35e7Swilly tarreau 14240ba35e7Swilly tarreau #define MVNETA_CAUSE_BMU_ALLOC_ERR_SHIFT 16 14340ba35e7Swilly tarreau #define MVNETA_CAUSE_BMU_ALLOC_ERR_ALL_MASK (0xF << MVNETA_CAUSE_BMU_ALLOC_ERR_SHIFT) 14440ba35e7Swilly tarreau #define MVNETA_CAUSE_BMU_ALLOC_ERR_MASK(pool) (1 << (MVNETA_CAUSE_BMU_ALLOC_ERR_SHIFT + (pool))) 14540ba35e7Swilly tarreau 14640ba35e7Swilly tarreau #define MVNETA_CAUSE_TXQ_ERROR_SHIFT 24 14740ba35e7Swilly tarreau #define MVNETA_CAUSE_TXQ_ERROR_ALL_MASK (0xFF << MVNETA_CAUSE_TXQ_ERROR_SHIFT) 14840ba35e7Swilly tarreau #define MVNETA_CAUSE_TXQ_ERROR_MASK(q) (1 << (MVNETA_CAUSE_TXQ_ERROR_SHIFT + (q))) 14940ba35e7Swilly tarreau 150c5aff182SThomas Petazzoni #define MVNETA_INTR_ENABLE 0x25b8 151c5aff182SThomas Petazzoni #define MVNETA_TXQ_INTR_ENABLE_ALL_MASK 0x0000ff00 15240ba35e7Swilly tarreau #define MVNETA_RXQ_INTR_ENABLE_ALL_MASK 0xff000000 // note: neta says it's 0x000000FF 15340ba35e7Swilly tarreau 154c5aff182SThomas Petazzoni #define MVNETA_RXQ_CMD 0x2680 155c5aff182SThomas Petazzoni #define MVNETA_RXQ_DISABLE_SHIFT 8 156c5aff182SThomas Petazzoni #define MVNETA_RXQ_ENABLE_MASK 0x000000ff 157c5aff182SThomas Petazzoni #define MVETH_TXQ_TOKEN_COUNT_REG(q) (0x2700 + ((q) << 4)) 158c5aff182SThomas Petazzoni #define MVETH_TXQ_TOKEN_CFG_REG(q) (0x2704 + ((q) << 4)) 159c5aff182SThomas Petazzoni #define MVNETA_GMAC_CTRL_0 0x2c00 160c5aff182SThomas Petazzoni #define MVNETA_GMAC_MAX_RX_SIZE_SHIFT 2 161c5aff182SThomas Petazzoni #define MVNETA_GMAC_MAX_RX_SIZE_MASK 0x7ffc 162c5aff182SThomas Petazzoni #define MVNETA_GMAC0_PORT_ENABLE BIT(0) 163c5aff182SThomas Petazzoni #define MVNETA_GMAC_CTRL_2 0x2c08 164c5aff182SThomas Petazzoni #define MVNETA_GMAC2_PSC_ENABLE BIT(3) 165c5aff182SThomas Petazzoni #define MVNETA_GMAC2_PORT_RGMII BIT(4) 166c5aff182SThomas Petazzoni #define MVNETA_GMAC2_PORT_RESET BIT(6) 167c5aff182SThomas Petazzoni #define MVNETA_GMAC_STATUS 0x2c10 168c5aff182SThomas Petazzoni #define MVNETA_GMAC_LINK_UP BIT(0) 169c5aff182SThomas Petazzoni #define MVNETA_GMAC_SPEED_1000 BIT(1) 170c5aff182SThomas Petazzoni #define MVNETA_GMAC_SPEED_100 BIT(2) 171c5aff182SThomas Petazzoni #define MVNETA_GMAC_FULL_DUPLEX BIT(3) 172c5aff182SThomas Petazzoni #define MVNETA_GMAC_RX_FLOW_CTRL_ENABLE BIT(4) 173c5aff182SThomas Petazzoni #define MVNETA_GMAC_TX_FLOW_CTRL_ENABLE BIT(5) 174c5aff182SThomas Petazzoni #define MVNETA_GMAC_RX_FLOW_CTRL_ACTIVE BIT(6) 175c5aff182SThomas Petazzoni #define MVNETA_GMAC_TX_FLOW_CTRL_ACTIVE BIT(7) 176c5aff182SThomas Petazzoni #define MVNETA_GMAC_AUTONEG_CONFIG 0x2c0c 177c5aff182SThomas Petazzoni #define MVNETA_GMAC_FORCE_LINK_DOWN BIT(0) 178c5aff182SThomas Petazzoni #define MVNETA_GMAC_FORCE_LINK_PASS BIT(1) 179c5aff182SThomas Petazzoni #define MVNETA_GMAC_CONFIG_MII_SPEED BIT(5) 180c5aff182SThomas Petazzoni #define MVNETA_GMAC_CONFIG_GMII_SPEED BIT(6) 18171408602SThomas Petazzoni #define MVNETA_GMAC_AN_SPEED_EN BIT(7) 182c5aff182SThomas Petazzoni #define MVNETA_GMAC_CONFIG_FULL_DUPLEX BIT(12) 18371408602SThomas Petazzoni #define MVNETA_GMAC_AN_DUPLEX_EN BIT(13) 184c5aff182SThomas Petazzoni #define MVNETA_MIB_COUNTERS_BASE 0x3080 185c5aff182SThomas Petazzoni #define MVNETA_MIB_LATE_COLLISION 0x7c 186c5aff182SThomas Petazzoni #define MVNETA_DA_FILT_SPEC_MCAST 0x3400 187c5aff182SThomas Petazzoni #define MVNETA_DA_FILT_OTH_MCAST 0x3500 188c5aff182SThomas Petazzoni #define MVNETA_DA_FILT_UCAST_BASE 0x3600 189c5aff182SThomas Petazzoni #define MVNETA_TXQ_BASE_ADDR_REG(q) (0x3c00 + ((q) << 2)) 190c5aff182SThomas Petazzoni #define MVNETA_TXQ_SIZE_REG(q) (0x3c20 + ((q) << 2)) 191c5aff182SThomas Petazzoni #define MVNETA_TXQ_SENT_THRESH_ALL_MASK 0x3fff0000 192c5aff182SThomas Petazzoni #define MVNETA_TXQ_SENT_THRESH_MASK(coal) ((coal) << 16) 193c5aff182SThomas Petazzoni #define MVNETA_TXQ_UPDATE_REG(q) (0x3c60 + ((q) << 2)) 194c5aff182SThomas Petazzoni #define MVNETA_TXQ_DEC_SENT_SHIFT 16 195c5aff182SThomas Petazzoni #define MVNETA_TXQ_STATUS_REG(q) (0x3c40 + ((q) << 2)) 196c5aff182SThomas Petazzoni #define MVNETA_TXQ_SENT_DESC_SHIFT 16 197c5aff182SThomas Petazzoni #define MVNETA_TXQ_SENT_DESC_MASK 0x3fff0000 198c5aff182SThomas Petazzoni #define MVNETA_PORT_TX_RESET 0x3cf0 199c5aff182SThomas Petazzoni #define MVNETA_PORT_TX_DMA_RESET BIT(0) 200c5aff182SThomas Petazzoni #define MVNETA_TX_MTU 0x3e0c 201c5aff182SThomas Petazzoni #define MVNETA_TX_TOKEN_SIZE 0x3e14 202c5aff182SThomas Petazzoni #define MVNETA_TX_TOKEN_SIZE_MAX 0xffffffff 203c5aff182SThomas Petazzoni #define MVNETA_TXQ_TOKEN_SIZE_REG(q) (0x3e40 + ((q) << 2)) 204c5aff182SThomas Petazzoni #define MVNETA_TXQ_TOKEN_SIZE_MAX 0x7fffffff 205c5aff182SThomas Petazzoni 206c5aff182SThomas Petazzoni #define MVNETA_CAUSE_TXQ_SENT_DESC_ALL_MASK 0xff 207c5aff182SThomas Petazzoni 208c5aff182SThomas Petazzoni /* Descriptor ring Macros */ 209c5aff182SThomas Petazzoni #define MVNETA_QUEUE_NEXT_DESC(q, index) \ 210c5aff182SThomas Petazzoni (((index) < (q)->last_desc) ? ((index) + 1) : 0) 211c5aff182SThomas Petazzoni 212c5aff182SThomas Petazzoni /* Various constants */ 213c5aff182SThomas Petazzoni 214c5aff182SThomas Petazzoni /* Coalescing */ 215c5aff182SThomas Petazzoni #define MVNETA_TXDONE_COAL_PKTS 16 216c5aff182SThomas Petazzoni #define MVNETA_RX_COAL_PKTS 32 217c5aff182SThomas Petazzoni #define MVNETA_RX_COAL_USEC 100 218c5aff182SThomas Petazzoni 219c5aff182SThomas Petazzoni /* Napi polling weight */ 220c5aff182SThomas Petazzoni #define MVNETA_RX_POLL_WEIGHT 64 221c5aff182SThomas Petazzoni 2226a20c175SThomas Petazzoni /* The two bytes Marvell header. Either contains a special value used 223c5aff182SThomas Petazzoni * by Marvell switches when a specific hardware mode is enabled (not 224c5aff182SThomas Petazzoni * supported by this driver) or is filled automatically by zeroes on 225c5aff182SThomas Petazzoni * the RX side. Those two bytes being at the front of the Ethernet 226c5aff182SThomas Petazzoni * header, they allow to have the IP header aligned on a 4 bytes 227c5aff182SThomas Petazzoni * boundary automatically: the hardware skips those two bytes on its 228c5aff182SThomas Petazzoni * own. 229c5aff182SThomas Petazzoni */ 230c5aff182SThomas Petazzoni #define MVNETA_MH_SIZE 2 231c5aff182SThomas Petazzoni 232c5aff182SThomas Petazzoni #define MVNETA_VLAN_TAG_LEN 4 233c5aff182SThomas Petazzoni 234c5aff182SThomas Petazzoni #define MVNETA_CPU_D_CACHE_LINE_SIZE 32 235c5aff182SThomas Petazzoni #define MVNETA_TX_CSUM_MAX_SIZE 9800 236c5aff182SThomas Petazzoni #define MVNETA_ACC_MODE_EXT 1 237c5aff182SThomas Petazzoni 238c5aff182SThomas Petazzoni /* Timeout constants */ 239c5aff182SThomas Petazzoni #define MVNETA_TX_DISABLE_TIMEOUT_MSEC 1000 240c5aff182SThomas Petazzoni #define MVNETA_RX_DISABLE_TIMEOUT_MSEC 1000 241c5aff182SThomas Petazzoni #define MVNETA_TX_FIFO_EMPTY_TIMEOUT 10000 242c5aff182SThomas Petazzoni 243c5aff182SThomas Petazzoni #define MVNETA_TX_MTU_MAX 0x3ffff 244c5aff182SThomas Petazzoni 245c5aff182SThomas Petazzoni /* Max number of Rx descriptors */ 246c5aff182SThomas Petazzoni #define MVNETA_MAX_RXD 128 247c5aff182SThomas Petazzoni 248c5aff182SThomas Petazzoni /* Max number of Tx descriptors */ 249c5aff182SThomas Petazzoni #define MVNETA_MAX_TXD 532 250c5aff182SThomas Petazzoni 251c5aff182SThomas Petazzoni /* descriptor aligned size */ 252c5aff182SThomas Petazzoni #define MVNETA_DESC_ALIGNED_SIZE 32 253c5aff182SThomas Petazzoni 254c5aff182SThomas Petazzoni #define MVNETA_RX_PKT_SIZE(mtu) \ 255c5aff182SThomas Petazzoni ALIGN((mtu) + MVNETA_MH_SIZE + MVNETA_VLAN_TAG_LEN + \ 256c5aff182SThomas Petazzoni ETH_HLEN + ETH_FCS_LEN, \ 257c5aff182SThomas Petazzoni MVNETA_CPU_D_CACHE_LINE_SIZE) 258c5aff182SThomas Petazzoni 259c5aff182SThomas Petazzoni #define MVNETA_RX_BUF_SIZE(pkt_size) ((pkt_size) + NET_SKB_PAD) 260c5aff182SThomas Petazzoni 26174c41b04Swilly tarreau struct mvneta_pcpu_stats { 262c5aff182SThomas Petazzoni struct u64_stats_sync syncp; 26374c41b04Swilly tarreau u64 rx_packets; 26474c41b04Swilly tarreau u64 rx_bytes; 26574c41b04Swilly tarreau u64 tx_packets; 26674c41b04Swilly tarreau u64 tx_bytes; 267c5aff182SThomas Petazzoni }; 268c5aff182SThomas Petazzoni 269c5aff182SThomas Petazzoni struct mvneta_port { 270c5aff182SThomas Petazzoni int pkt_size; 2718ec2cd48Swilly tarreau unsigned int frag_size; 272c5aff182SThomas Petazzoni void __iomem *base; 273c5aff182SThomas Petazzoni struct mvneta_rx_queue *rxqs; 274c5aff182SThomas Petazzoni struct mvneta_tx_queue *txqs; 275c5aff182SThomas Petazzoni struct net_device *dev; 276c5aff182SThomas Petazzoni 277c5aff182SThomas Petazzoni u32 cause_rx_tx; 278c5aff182SThomas Petazzoni struct napi_struct napi; 279c5aff182SThomas Petazzoni 280c5aff182SThomas Petazzoni /* Napi weight */ 281c5aff182SThomas Petazzoni int weight; 282c5aff182SThomas Petazzoni 283c5aff182SThomas Petazzoni /* Core clock */ 284189dd626SThomas Petazzoni struct clk *clk; 285c5aff182SThomas Petazzoni u8 mcast_count[256]; 286c5aff182SThomas Petazzoni u16 tx_ring_size; 287c5aff182SThomas Petazzoni u16 rx_ring_size; 28874c41b04Swilly tarreau struct mvneta_pcpu_stats *stats; 289c5aff182SThomas Petazzoni 290c5aff182SThomas Petazzoni struct mii_bus *mii_bus; 291c5aff182SThomas Petazzoni struct phy_device *phy_dev; 292c5aff182SThomas Petazzoni phy_interface_t phy_interface; 293c5aff182SThomas Petazzoni struct device_node *phy_node; 294c5aff182SThomas Petazzoni unsigned int link; 295c5aff182SThomas Petazzoni unsigned int duplex; 296c5aff182SThomas Petazzoni unsigned int speed; 297c5aff182SThomas Petazzoni }; 298c5aff182SThomas Petazzoni 2996a20c175SThomas Petazzoni /* The mvneta_tx_desc and mvneta_rx_desc structures describe the 300c5aff182SThomas Petazzoni * layout of the transmit and reception DMA descriptors, and their 301c5aff182SThomas Petazzoni * layout is therefore defined by the hardware design 302c5aff182SThomas Petazzoni */ 3036083ed44SThomas Petazzoni 304c5aff182SThomas Petazzoni #define MVNETA_TX_L3_OFF_SHIFT 0 305c5aff182SThomas Petazzoni #define MVNETA_TX_IP_HLEN_SHIFT 8 306c5aff182SThomas Petazzoni #define MVNETA_TX_L4_UDP BIT(16) 307c5aff182SThomas Petazzoni #define MVNETA_TX_L3_IP6 BIT(17) 308c5aff182SThomas Petazzoni #define MVNETA_TXD_IP_CSUM BIT(18) 309c5aff182SThomas Petazzoni #define MVNETA_TXD_Z_PAD BIT(19) 310c5aff182SThomas Petazzoni #define MVNETA_TXD_L_DESC BIT(20) 311c5aff182SThomas Petazzoni #define MVNETA_TXD_F_DESC BIT(21) 312c5aff182SThomas Petazzoni #define MVNETA_TXD_FLZ_DESC (MVNETA_TXD_Z_PAD | \ 313c5aff182SThomas Petazzoni MVNETA_TXD_L_DESC | \ 314c5aff182SThomas Petazzoni MVNETA_TXD_F_DESC) 315c5aff182SThomas Petazzoni #define MVNETA_TX_L4_CSUM_FULL BIT(30) 316c5aff182SThomas Petazzoni #define MVNETA_TX_L4_CSUM_NOT BIT(31) 317c5aff182SThomas Petazzoni 318c5aff182SThomas Petazzoni #define MVNETA_RXD_ERR_CRC 0x0 319c5aff182SThomas Petazzoni #define MVNETA_RXD_ERR_SUMMARY BIT(16) 320c5aff182SThomas Petazzoni #define MVNETA_RXD_ERR_OVERRUN BIT(17) 321c5aff182SThomas Petazzoni #define MVNETA_RXD_ERR_LEN BIT(18) 322c5aff182SThomas Petazzoni #define MVNETA_RXD_ERR_RESOURCE (BIT(17) | BIT(18)) 323c5aff182SThomas Petazzoni #define MVNETA_RXD_ERR_CODE_MASK (BIT(17) | BIT(18)) 324c5aff182SThomas Petazzoni #define MVNETA_RXD_L3_IP4 BIT(25) 325c5aff182SThomas Petazzoni #define MVNETA_RXD_FIRST_LAST_DESC (BIT(26) | BIT(27)) 326c5aff182SThomas Petazzoni #define MVNETA_RXD_L4_CSUM_OK BIT(30) 327c5aff182SThomas Petazzoni 3289ad8fef6SThomas Petazzoni #if defined(__LITTLE_ENDIAN) 3296083ed44SThomas Petazzoni struct mvneta_tx_desc { 3306083ed44SThomas Petazzoni u32 command; /* Options used by HW for packet transmitting.*/ 3316083ed44SThomas Petazzoni u16 reserverd1; /* csum_l4 (for future use) */ 3326083ed44SThomas Petazzoni u16 data_size; /* Data size of transmitted packet in bytes */ 3336083ed44SThomas Petazzoni u32 buf_phys_addr; /* Physical addr of transmitted buffer */ 3346083ed44SThomas Petazzoni u32 reserved2; /* hw_cmd - (for future use, PMT) */ 3356083ed44SThomas Petazzoni u32 reserved3[4]; /* Reserved - (for future use) */ 3366083ed44SThomas Petazzoni }; 3376083ed44SThomas Petazzoni 3386083ed44SThomas Petazzoni struct mvneta_rx_desc { 3396083ed44SThomas Petazzoni u32 status; /* Info about received packet */ 340c5aff182SThomas Petazzoni u16 reserved1; /* pnc_info - (for future use, PnC) */ 341c5aff182SThomas Petazzoni u16 data_size; /* Size of received packet in bytes */ 3426083ed44SThomas Petazzoni 343c5aff182SThomas Petazzoni u32 buf_phys_addr; /* Physical address of the buffer */ 344c5aff182SThomas Petazzoni u32 reserved2; /* pnc_flow_id (for future use, PnC) */ 3456083ed44SThomas Petazzoni 346c5aff182SThomas Petazzoni u32 buf_cookie; /* cookie for access to RX buffer in rx path */ 347c5aff182SThomas Petazzoni u16 reserved3; /* prefetch_cmd, for future use */ 348c5aff182SThomas Petazzoni u16 reserved4; /* csum_l4 - (for future use, PnC) */ 3496083ed44SThomas Petazzoni 350c5aff182SThomas Petazzoni u32 reserved5; /* pnc_extra PnC (for future use, PnC) */ 351c5aff182SThomas Petazzoni u32 reserved6; /* hw_cmd (for future use, PnC and HWF) */ 352c5aff182SThomas Petazzoni }; 3539ad8fef6SThomas Petazzoni #else 3549ad8fef6SThomas Petazzoni struct mvneta_tx_desc { 3559ad8fef6SThomas Petazzoni u16 data_size; /* Data size of transmitted packet in bytes */ 3569ad8fef6SThomas Petazzoni u16 reserverd1; /* csum_l4 (for future use) */ 3579ad8fef6SThomas Petazzoni u32 command; /* Options used by HW for packet transmitting.*/ 3589ad8fef6SThomas Petazzoni u32 reserved2; /* hw_cmd - (for future use, PMT) */ 3599ad8fef6SThomas Petazzoni u32 buf_phys_addr; /* Physical addr of transmitted buffer */ 3609ad8fef6SThomas Petazzoni u32 reserved3[4]; /* Reserved - (for future use) */ 3619ad8fef6SThomas Petazzoni }; 3629ad8fef6SThomas Petazzoni 3639ad8fef6SThomas Petazzoni struct mvneta_rx_desc { 3649ad8fef6SThomas Petazzoni u16 data_size; /* Size of received packet in bytes */ 3659ad8fef6SThomas Petazzoni u16 reserved1; /* pnc_info - (for future use, PnC) */ 3669ad8fef6SThomas Petazzoni u32 status; /* Info about received packet */ 3679ad8fef6SThomas Petazzoni 3689ad8fef6SThomas Petazzoni u32 reserved2; /* pnc_flow_id (for future use, PnC) */ 3699ad8fef6SThomas Petazzoni u32 buf_phys_addr; /* Physical address of the buffer */ 3709ad8fef6SThomas Petazzoni 3719ad8fef6SThomas Petazzoni u16 reserved4; /* csum_l4 - (for future use, PnC) */ 3729ad8fef6SThomas Petazzoni u16 reserved3; /* prefetch_cmd, for future use */ 3739ad8fef6SThomas Petazzoni u32 buf_cookie; /* cookie for access to RX buffer in rx path */ 3749ad8fef6SThomas Petazzoni 3759ad8fef6SThomas Petazzoni u32 reserved5; /* pnc_extra PnC (for future use, PnC) */ 3769ad8fef6SThomas Petazzoni u32 reserved6; /* hw_cmd (for future use, PnC and HWF) */ 3779ad8fef6SThomas Petazzoni }; 3789ad8fef6SThomas Petazzoni #endif 379c5aff182SThomas Petazzoni 380c5aff182SThomas Petazzoni struct mvneta_tx_queue { 381c5aff182SThomas Petazzoni /* Number of this TX queue, in the range 0-7 */ 382c5aff182SThomas Petazzoni u8 id; 383c5aff182SThomas Petazzoni 384c5aff182SThomas Petazzoni /* Number of TX DMA descriptors in the descriptor ring */ 385c5aff182SThomas Petazzoni int size; 386c5aff182SThomas Petazzoni 387c5aff182SThomas Petazzoni /* Number of currently used TX DMA descriptor in the 3886a20c175SThomas Petazzoni * descriptor ring 3896a20c175SThomas Petazzoni */ 390c5aff182SThomas Petazzoni int count; 391c5aff182SThomas Petazzoni 392c5aff182SThomas Petazzoni /* Array of transmitted skb */ 393c5aff182SThomas Petazzoni struct sk_buff **tx_skb; 394c5aff182SThomas Petazzoni 395c5aff182SThomas Petazzoni /* Index of last TX DMA descriptor that was inserted */ 396c5aff182SThomas Petazzoni int txq_put_index; 397c5aff182SThomas Petazzoni 398c5aff182SThomas Petazzoni /* Index of the TX DMA descriptor to be cleaned up */ 399c5aff182SThomas Petazzoni int txq_get_index; 400c5aff182SThomas Petazzoni 401c5aff182SThomas Petazzoni u32 done_pkts_coal; 402c5aff182SThomas Petazzoni 403c5aff182SThomas Petazzoni /* Virtual address of the TX DMA descriptors array */ 404c5aff182SThomas Petazzoni struct mvneta_tx_desc *descs; 405c5aff182SThomas Petazzoni 406c5aff182SThomas Petazzoni /* DMA address of the TX DMA descriptors array */ 407c5aff182SThomas Petazzoni dma_addr_t descs_phys; 408c5aff182SThomas Petazzoni 409c5aff182SThomas Petazzoni /* Index of the last TX DMA descriptor */ 410c5aff182SThomas Petazzoni int last_desc; 411c5aff182SThomas Petazzoni 412c5aff182SThomas Petazzoni /* Index of the next TX DMA descriptor to process */ 413c5aff182SThomas Petazzoni int next_desc_to_proc; 414c5aff182SThomas Petazzoni }; 415c5aff182SThomas Petazzoni 416c5aff182SThomas Petazzoni struct mvneta_rx_queue { 417c5aff182SThomas Petazzoni /* rx queue number, in the range 0-7 */ 418c5aff182SThomas Petazzoni u8 id; 419c5aff182SThomas Petazzoni 420c5aff182SThomas Petazzoni /* num of rx descriptors in the rx descriptor ring */ 421c5aff182SThomas Petazzoni int size; 422c5aff182SThomas Petazzoni 423c5aff182SThomas Petazzoni /* counter of times when mvneta_refill() failed */ 424c5aff182SThomas Petazzoni int missed; 425c5aff182SThomas Petazzoni 426c5aff182SThomas Petazzoni u32 pkts_coal; 427c5aff182SThomas Petazzoni u32 time_coal; 428c5aff182SThomas Petazzoni 429c5aff182SThomas Petazzoni /* Virtual address of the RX DMA descriptors array */ 430c5aff182SThomas Petazzoni struct mvneta_rx_desc *descs; 431c5aff182SThomas Petazzoni 432c5aff182SThomas Petazzoni /* DMA address of the RX DMA descriptors array */ 433c5aff182SThomas Petazzoni dma_addr_t descs_phys; 434c5aff182SThomas Petazzoni 435c5aff182SThomas Petazzoni /* Index of the last RX DMA descriptor */ 436c5aff182SThomas Petazzoni int last_desc; 437c5aff182SThomas Petazzoni 438c5aff182SThomas Petazzoni /* Index of the next RX DMA descriptor to process */ 439c5aff182SThomas Petazzoni int next_desc_to_proc; 440c5aff182SThomas Petazzoni }; 441c5aff182SThomas Petazzoni 442c5aff182SThomas Petazzoni static int rxq_number = 8; 443c5aff182SThomas Petazzoni static int txq_number = 8; 444c5aff182SThomas Petazzoni 445c5aff182SThomas Petazzoni static int rxq_def; 446c5aff182SThomas Petazzoni 447f19fadfcSwilly tarreau static int rx_copybreak __read_mostly = 256; 448f19fadfcSwilly tarreau 449c5aff182SThomas Petazzoni #define MVNETA_DRIVER_NAME "mvneta" 450c5aff182SThomas Petazzoni #define MVNETA_DRIVER_VERSION "1.0" 451c5aff182SThomas Petazzoni 452c5aff182SThomas Petazzoni /* Utility/helper methods */ 453c5aff182SThomas Petazzoni 454c5aff182SThomas Petazzoni /* Write helper method */ 455c5aff182SThomas Petazzoni static void mvreg_write(struct mvneta_port *pp, u32 offset, u32 data) 456c5aff182SThomas Petazzoni { 457c5aff182SThomas Petazzoni writel(data, pp->base + offset); 458c5aff182SThomas Petazzoni } 459c5aff182SThomas Petazzoni 460c5aff182SThomas Petazzoni /* Read helper method */ 461c5aff182SThomas Petazzoni static u32 mvreg_read(struct mvneta_port *pp, u32 offset) 462c5aff182SThomas Petazzoni { 463c5aff182SThomas Petazzoni return readl(pp->base + offset); 464c5aff182SThomas Petazzoni } 465c5aff182SThomas Petazzoni 466c5aff182SThomas Petazzoni /* Increment txq get counter */ 467c5aff182SThomas Petazzoni static void mvneta_txq_inc_get(struct mvneta_tx_queue *txq) 468c5aff182SThomas Petazzoni { 469c5aff182SThomas Petazzoni txq->txq_get_index++; 470c5aff182SThomas Petazzoni if (txq->txq_get_index == txq->size) 471c5aff182SThomas Petazzoni txq->txq_get_index = 0; 472c5aff182SThomas Petazzoni } 473c5aff182SThomas Petazzoni 474c5aff182SThomas Petazzoni /* Increment txq put counter */ 475c5aff182SThomas Petazzoni static void mvneta_txq_inc_put(struct mvneta_tx_queue *txq) 476c5aff182SThomas Petazzoni { 477c5aff182SThomas Petazzoni txq->txq_put_index++; 478c5aff182SThomas Petazzoni if (txq->txq_put_index == txq->size) 479c5aff182SThomas Petazzoni txq->txq_put_index = 0; 480c5aff182SThomas Petazzoni } 481c5aff182SThomas Petazzoni 482c5aff182SThomas Petazzoni 483c5aff182SThomas Petazzoni /* Clear all MIB counters */ 484c5aff182SThomas Petazzoni static void mvneta_mib_counters_clear(struct mvneta_port *pp) 485c5aff182SThomas Petazzoni { 486c5aff182SThomas Petazzoni int i; 487c5aff182SThomas Petazzoni u32 dummy; 488c5aff182SThomas Petazzoni 489c5aff182SThomas Petazzoni /* Perform dummy reads from MIB counters */ 490c5aff182SThomas Petazzoni for (i = 0; i < MVNETA_MIB_LATE_COLLISION; i += 4) 491c5aff182SThomas Petazzoni dummy = mvreg_read(pp, (MVNETA_MIB_COUNTERS_BASE + i)); 492c5aff182SThomas Petazzoni } 493c5aff182SThomas Petazzoni 494c5aff182SThomas Petazzoni /* Get System Network Statistics */ 495c5aff182SThomas Petazzoni struct rtnl_link_stats64 *mvneta_get_stats64(struct net_device *dev, 496c5aff182SThomas Petazzoni struct rtnl_link_stats64 *stats) 497c5aff182SThomas Petazzoni { 498c5aff182SThomas Petazzoni struct mvneta_port *pp = netdev_priv(dev); 499c5aff182SThomas Petazzoni unsigned int start; 50074c41b04Swilly tarreau int cpu; 501c5aff182SThomas Petazzoni 50274c41b04Swilly tarreau for_each_possible_cpu(cpu) { 50374c41b04Swilly tarreau struct mvneta_pcpu_stats *cpu_stats; 50474c41b04Swilly tarreau u64 rx_packets; 50574c41b04Swilly tarreau u64 rx_bytes; 50674c41b04Swilly tarreau u64 tx_packets; 50774c41b04Swilly tarreau u64 tx_bytes; 508c5aff182SThomas Petazzoni 50974c41b04Swilly tarreau cpu_stats = per_cpu_ptr(pp->stats, cpu); 510c5aff182SThomas Petazzoni do { 51157a7744eSEric W. Biederman start = u64_stats_fetch_begin_irq(&cpu_stats->syncp); 51274c41b04Swilly tarreau rx_packets = cpu_stats->rx_packets; 51374c41b04Swilly tarreau rx_bytes = cpu_stats->rx_bytes; 51474c41b04Swilly tarreau tx_packets = cpu_stats->tx_packets; 51574c41b04Swilly tarreau tx_bytes = cpu_stats->tx_bytes; 51657a7744eSEric W. Biederman } while (u64_stats_fetch_retry_irq(&cpu_stats->syncp, start)); 517c5aff182SThomas Petazzoni 51874c41b04Swilly tarreau stats->rx_packets += rx_packets; 51974c41b04Swilly tarreau stats->rx_bytes += rx_bytes; 52074c41b04Swilly tarreau stats->tx_packets += tx_packets; 52174c41b04Swilly tarreau stats->tx_bytes += tx_bytes; 52274c41b04Swilly tarreau } 523c5aff182SThomas Petazzoni 524c5aff182SThomas Petazzoni stats->rx_errors = dev->stats.rx_errors; 525c5aff182SThomas Petazzoni stats->rx_dropped = dev->stats.rx_dropped; 526c5aff182SThomas Petazzoni 527c5aff182SThomas Petazzoni stats->tx_dropped = dev->stats.tx_dropped; 528c5aff182SThomas Petazzoni 529c5aff182SThomas Petazzoni return stats; 530c5aff182SThomas Petazzoni } 531c5aff182SThomas Petazzoni 532c5aff182SThomas Petazzoni /* Rx descriptors helper methods */ 533c5aff182SThomas Petazzoni 5345428213cSwilly tarreau /* Checks whether the RX descriptor having this status is both the first 5355428213cSwilly tarreau * and the last descriptor for the RX packet. Each RX packet is currently 536c5aff182SThomas Petazzoni * received through a single RX descriptor, so not having each RX 537c5aff182SThomas Petazzoni * descriptor with its first and last bits set is an error 538c5aff182SThomas Petazzoni */ 5395428213cSwilly tarreau static int mvneta_rxq_desc_is_first_last(u32 status) 540c5aff182SThomas Petazzoni { 5415428213cSwilly tarreau return (status & MVNETA_RXD_FIRST_LAST_DESC) == 542c5aff182SThomas Petazzoni MVNETA_RXD_FIRST_LAST_DESC; 543c5aff182SThomas Petazzoni } 544c5aff182SThomas Petazzoni 545c5aff182SThomas Petazzoni /* Add number of descriptors ready to receive new packets */ 546c5aff182SThomas Petazzoni static void mvneta_rxq_non_occup_desc_add(struct mvneta_port *pp, 547c5aff182SThomas Petazzoni struct mvneta_rx_queue *rxq, 548c5aff182SThomas Petazzoni int ndescs) 549c5aff182SThomas Petazzoni { 550c5aff182SThomas Petazzoni /* Only MVNETA_RXQ_ADD_NON_OCCUPIED_MAX (255) descriptors can 5516a20c175SThomas Petazzoni * be added at once 5526a20c175SThomas Petazzoni */ 553c5aff182SThomas Petazzoni while (ndescs > MVNETA_RXQ_ADD_NON_OCCUPIED_MAX) { 554c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id), 555c5aff182SThomas Petazzoni (MVNETA_RXQ_ADD_NON_OCCUPIED_MAX << 556c5aff182SThomas Petazzoni MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT)); 557c5aff182SThomas Petazzoni ndescs -= MVNETA_RXQ_ADD_NON_OCCUPIED_MAX; 558c5aff182SThomas Petazzoni } 559c5aff182SThomas Petazzoni 560c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id), 561c5aff182SThomas Petazzoni (ndescs << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT)); 562c5aff182SThomas Petazzoni } 563c5aff182SThomas Petazzoni 564c5aff182SThomas Petazzoni /* Get number of RX descriptors occupied by received packets */ 565c5aff182SThomas Petazzoni static int mvneta_rxq_busy_desc_num_get(struct mvneta_port *pp, 566c5aff182SThomas Petazzoni struct mvneta_rx_queue *rxq) 567c5aff182SThomas Petazzoni { 568c5aff182SThomas Petazzoni u32 val; 569c5aff182SThomas Petazzoni 570c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_RXQ_STATUS_REG(rxq->id)); 571c5aff182SThomas Petazzoni return val & MVNETA_RXQ_OCCUPIED_ALL_MASK; 572c5aff182SThomas Petazzoni } 573c5aff182SThomas Petazzoni 5746a20c175SThomas Petazzoni /* Update num of rx desc called upon return from rx path or 575c5aff182SThomas Petazzoni * from mvneta_rxq_drop_pkts(). 576c5aff182SThomas Petazzoni */ 577c5aff182SThomas Petazzoni static void mvneta_rxq_desc_num_update(struct mvneta_port *pp, 578c5aff182SThomas Petazzoni struct mvneta_rx_queue *rxq, 579c5aff182SThomas Petazzoni int rx_done, int rx_filled) 580c5aff182SThomas Petazzoni { 581c5aff182SThomas Petazzoni u32 val; 582c5aff182SThomas Petazzoni 583c5aff182SThomas Petazzoni if ((rx_done <= 0xff) && (rx_filled <= 0xff)) { 584c5aff182SThomas Petazzoni val = rx_done | 585c5aff182SThomas Petazzoni (rx_filled << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT); 586c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id), val); 587c5aff182SThomas Petazzoni return; 588c5aff182SThomas Petazzoni } 589c5aff182SThomas Petazzoni 590c5aff182SThomas Petazzoni /* Only 255 descriptors can be added at once */ 591c5aff182SThomas Petazzoni while ((rx_done > 0) || (rx_filled > 0)) { 592c5aff182SThomas Petazzoni if (rx_done <= 0xff) { 593c5aff182SThomas Petazzoni val = rx_done; 594c5aff182SThomas Petazzoni rx_done = 0; 595c5aff182SThomas Petazzoni } else { 596c5aff182SThomas Petazzoni val = 0xff; 597c5aff182SThomas Petazzoni rx_done -= 0xff; 598c5aff182SThomas Petazzoni } 599c5aff182SThomas Petazzoni if (rx_filled <= 0xff) { 600c5aff182SThomas Petazzoni val |= rx_filled << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT; 601c5aff182SThomas Petazzoni rx_filled = 0; 602c5aff182SThomas Petazzoni } else { 603c5aff182SThomas Petazzoni val |= 0xff << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT; 604c5aff182SThomas Petazzoni rx_filled -= 0xff; 605c5aff182SThomas Petazzoni } 606c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id), val); 607c5aff182SThomas Petazzoni } 608c5aff182SThomas Petazzoni } 609c5aff182SThomas Petazzoni 610c5aff182SThomas Petazzoni /* Get pointer to next RX descriptor to be processed by SW */ 611c5aff182SThomas Petazzoni static struct mvneta_rx_desc * 612c5aff182SThomas Petazzoni mvneta_rxq_next_desc_get(struct mvneta_rx_queue *rxq) 613c5aff182SThomas Petazzoni { 614c5aff182SThomas Petazzoni int rx_desc = rxq->next_desc_to_proc; 615c5aff182SThomas Petazzoni 616c5aff182SThomas Petazzoni rxq->next_desc_to_proc = MVNETA_QUEUE_NEXT_DESC(rxq, rx_desc); 61734e4179dSwilly tarreau prefetch(rxq->descs + rxq->next_desc_to_proc); 618c5aff182SThomas Petazzoni return rxq->descs + rx_desc; 619c5aff182SThomas Petazzoni } 620c5aff182SThomas Petazzoni 621c5aff182SThomas Petazzoni /* Change maximum receive size of the port. */ 622c5aff182SThomas Petazzoni static void mvneta_max_rx_size_set(struct mvneta_port *pp, int max_rx_size) 623c5aff182SThomas Petazzoni { 624c5aff182SThomas Petazzoni u32 val; 625c5aff182SThomas Petazzoni 626c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_GMAC_CTRL_0); 627c5aff182SThomas Petazzoni val &= ~MVNETA_GMAC_MAX_RX_SIZE_MASK; 628c5aff182SThomas Petazzoni val |= ((max_rx_size - MVNETA_MH_SIZE) / 2) << 629c5aff182SThomas Petazzoni MVNETA_GMAC_MAX_RX_SIZE_SHIFT; 630c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_GMAC_CTRL_0, val); 631c5aff182SThomas Petazzoni } 632c5aff182SThomas Petazzoni 633c5aff182SThomas Petazzoni 634c5aff182SThomas Petazzoni /* Set rx queue offset */ 635c5aff182SThomas Petazzoni static void mvneta_rxq_offset_set(struct mvneta_port *pp, 636c5aff182SThomas Petazzoni struct mvneta_rx_queue *rxq, 637c5aff182SThomas Petazzoni int offset) 638c5aff182SThomas Petazzoni { 639c5aff182SThomas Petazzoni u32 val; 640c5aff182SThomas Petazzoni 641c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_RXQ_CONFIG_REG(rxq->id)); 642c5aff182SThomas Petazzoni val &= ~MVNETA_RXQ_PKT_OFFSET_ALL_MASK; 643c5aff182SThomas Petazzoni 644c5aff182SThomas Petazzoni /* Offset is in */ 645c5aff182SThomas Petazzoni val |= MVNETA_RXQ_PKT_OFFSET_MASK(offset >> 3); 646c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_RXQ_CONFIG_REG(rxq->id), val); 647c5aff182SThomas Petazzoni } 648c5aff182SThomas Petazzoni 649c5aff182SThomas Petazzoni 650c5aff182SThomas Petazzoni /* Tx descriptors helper methods */ 651c5aff182SThomas Petazzoni 652c5aff182SThomas Petazzoni /* Update HW with number of TX descriptors to be sent */ 653c5aff182SThomas Petazzoni static void mvneta_txq_pend_desc_add(struct mvneta_port *pp, 654c5aff182SThomas Petazzoni struct mvneta_tx_queue *txq, 655c5aff182SThomas Petazzoni int pend_desc) 656c5aff182SThomas Petazzoni { 657c5aff182SThomas Petazzoni u32 val; 658c5aff182SThomas Petazzoni 659c5aff182SThomas Petazzoni /* Only 255 descriptors can be added at once ; Assume caller 6606a20c175SThomas Petazzoni * process TX desriptors in quanta less than 256 6616a20c175SThomas Petazzoni */ 662c5aff182SThomas Petazzoni val = pend_desc; 663c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val); 664c5aff182SThomas Petazzoni } 665c5aff182SThomas Petazzoni 666c5aff182SThomas Petazzoni /* Get pointer to next TX descriptor to be processed (send) by HW */ 667c5aff182SThomas Petazzoni static struct mvneta_tx_desc * 668c5aff182SThomas Petazzoni mvneta_txq_next_desc_get(struct mvneta_tx_queue *txq) 669c5aff182SThomas Petazzoni { 670c5aff182SThomas Petazzoni int tx_desc = txq->next_desc_to_proc; 671c5aff182SThomas Petazzoni 672c5aff182SThomas Petazzoni txq->next_desc_to_proc = MVNETA_QUEUE_NEXT_DESC(txq, tx_desc); 673c5aff182SThomas Petazzoni return txq->descs + tx_desc; 674c5aff182SThomas Petazzoni } 675c5aff182SThomas Petazzoni 676c5aff182SThomas Petazzoni /* Release the last allocated TX descriptor. Useful to handle DMA 6776a20c175SThomas Petazzoni * mapping failures in the TX path. 6786a20c175SThomas Petazzoni */ 679c5aff182SThomas Petazzoni static void mvneta_txq_desc_put(struct mvneta_tx_queue *txq) 680c5aff182SThomas Petazzoni { 681c5aff182SThomas Petazzoni if (txq->next_desc_to_proc == 0) 682c5aff182SThomas Petazzoni txq->next_desc_to_proc = txq->last_desc - 1; 683c5aff182SThomas Petazzoni else 684c5aff182SThomas Petazzoni txq->next_desc_to_proc--; 685c5aff182SThomas Petazzoni } 686c5aff182SThomas Petazzoni 687c5aff182SThomas Petazzoni /* Set rxq buf size */ 688c5aff182SThomas Petazzoni static void mvneta_rxq_buf_size_set(struct mvneta_port *pp, 689c5aff182SThomas Petazzoni struct mvneta_rx_queue *rxq, 690c5aff182SThomas Petazzoni int buf_size) 691c5aff182SThomas Petazzoni { 692c5aff182SThomas Petazzoni u32 val; 693c5aff182SThomas Petazzoni 694c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_RXQ_SIZE_REG(rxq->id)); 695c5aff182SThomas Petazzoni 696c5aff182SThomas Petazzoni val &= ~MVNETA_RXQ_BUF_SIZE_MASK; 697c5aff182SThomas Petazzoni val |= ((buf_size >> 3) << MVNETA_RXQ_BUF_SIZE_SHIFT); 698c5aff182SThomas Petazzoni 699c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_RXQ_SIZE_REG(rxq->id), val); 700c5aff182SThomas Petazzoni } 701c5aff182SThomas Petazzoni 702c5aff182SThomas Petazzoni /* Disable buffer management (BM) */ 703c5aff182SThomas Petazzoni static void mvneta_rxq_bm_disable(struct mvneta_port *pp, 704c5aff182SThomas Petazzoni struct mvneta_rx_queue *rxq) 705c5aff182SThomas Petazzoni { 706c5aff182SThomas Petazzoni u32 val; 707c5aff182SThomas Petazzoni 708c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_RXQ_CONFIG_REG(rxq->id)); 709c5aff182SThomas Petazzoni val &= ~MVNETA_RXQ_HW_BUF_ALLOC; 710c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_RXQ_CONFIG_REG(rxq->id), val); 711c5aff182SThomas Petazzoni } 712c5aff182SThomas Petazzoni 713c5aff182SThomas Petazzoni 714c5aff182SThomas Petazzoni 715c5aff182SThomas Petazzoni /* Sets the RGMII Enable bit (RGMIIEn) in port MAC control register */ 71603ce758eSGreg KH static void mvneta_gmac_rgmii_set(struct mvneta_port *pp, int enable) 717c5aff182SThomas Petazzoni { 718c5aff182SThomas Petazzoni u32 val; 719c5aff182SThomas Petazzoni 720c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_GMAC_CTRL_2); 721c5aff182SThomas Petazzoni 722c5aff182SThomas Petazzoni if (enable) 723c5aff182SThomas Petazzoni val |= MVNETA_GMAC2_PORT_RGMII; 724c5aff182SThomas Petazzoni else 725c5aff182SThomas Petazzoni val &= ~MVNETA_GMAC2_PORT_RGMII; 726c5aff182SThomas Petazzoni 727c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_GMAC_CTRL_2, val); 728c5aff182SThomas Petazzoni } 729c5aff182SThomas Petazzoni 730c5aff182SThomas Petazzoni /* Config SGMII port */ 73103ce758eSGreg KH static void mvneta_port_sgmii_config(struct mvneta_port *pp) 732c5aff182SThomas Petazzoni { 733c5aff182SThomas Petazzoni u32 val; 734c5aff182SThomas Petazzoni 735c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_GMAC_CTRL_2); 736c5aff182SThomas Petazzoni val |= MVNETA_GMAC2_PSC_ENABLE; 737c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_GMAC_CTRL_2, val); 7385445eaf3SArnaud Patard \(Rtp\) 7395445eaf3SArnaud Patard \(Rtp\) mvreg_write(pp, MVNETA_SGMII_SERDES_CFG, MVNETA_SGMII_SERDES_PROTO); 740c5aff182SThomas Petazzoni } 741c5aff182SThomas Petazzoni 742c5aff182SThomas Petazzoni /* Start the Ethernet port RX and TX activity */ 743c5aff182SThomas Petazzoni static void mvneta_port_up(struct mvneta_port *pp) 744c5aff182SThomas Petazzoni { 745c5aff182SThomas Petazzoni int queue; 746c5aff182SThomas Petazzoni u32 q_map; 747c5aff182SThomas Petazzoni 748c5aff182SThomas Petazzoni /* Enable all initialized TXs. */ 749c5aff182SThomas Petazzoni mvneta_mib_counters_clear(pp); 750c5aff182SThomas Petazzoni q_map = 0; 751c5aff182SThomas Petazzoni for (queue = 0; queue < txq_number; queue++) { 752c5aff182SThomas Petazzoni struct mvneta_tx_queue *txq = &pp->txqs[queue]; 753c5aff182SThomas Petazzoni if (txq->descs != NULL) 754c5aff182SThomas Petazzoni q_map |= (1 << queue); 755c5aff182SThomas Petazzoni } 756c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_TXQ_CMD, q_map); 757c5aff182SThomas Petazzoni 758c5aff182SThomas Petazzoni /* Enable all initialized RXQs. */ 759c5aff182SThomas Petazzoni q_map = 0; 760c5aff182SThomas Petazzoni for (queue = 0; queue < rxq_number; queue++) { 761c5aff182SThomas Petazzoni struct mvneta_rx_queue *rxq = &pp->rxqs[queue]; 762c5aff182SThomas Petazzoni if (rxq->descs != NULL) 763c5aff182SThomas Petazzoni q_map |= (1 << queue); 764c5aff182SThomas Petazzoni } 765c5aff182SThomas Petazzoni 766c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_RXQ_CMD, q_map); 767c5aff182SThomas Petazzoni } 768c5aff182SThomas Petazzoni 769c5aff182SThomas Petazzoni /* Stop the Ethernet port activity */ 770c5aff182SThomas Petazzoni static void mvneta_port_down(struct mvneta_port *pp) 771c5aff182SThomas Petazzoni { 772c5aff182SThomas Petazzoni u32 val; 773c5aff182SThomas Petazzoni int count; 774c5aff182SThomas Petazzoni 775c5aff182SThomas Petazzoni /* Stop Rx port activity. Check port Rx activity. */ 776c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_RXQ_CMD) & MVNETA_RXQ_ENABLE_MASK; 777c5aff182SThomas Petazzoni 778c5aff182SThomas Petazzoni /* Issue stop command for active channels only */ 779c5aff182SThomas Petazzoni if (val != 0) 780c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_RXQ_CMD, 781c5aff182SThomas Petazzoni val << MVNETA_RXQ_DISABLE_SHIFT); 782c5aff182SThomas Petazzoni 783c5aff182SThomas Petazzoni /* Wait for all Rx activity to terminate. */ 784c5aff182SThomas Petazzoni count = 0; 785c5aff182SThomas Petazzoni do { 786c5aff182SThomas Petazzoni if (count++ >= MVNETA_RX_DISABLE_TIMEOUT_MSEC) { 787c5aff182SThomas Petazzoni netdev_warn(pp->dev, 788c5aff182SThomas Petazzoni "TIMEOUT for RX stopped ! rx_queue_cmd: 0x08%x\n", 789c5aff182SThomas Petazzoni val); 790c5aff182SThomas Petazzoni break; 791c5aff182SThomas Petazzoni } 792c5aff182SThomas Petazzoni mdelay(1); 793c5aff182SThomas Petazzoni 794c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_RXQ_CMD); 795c5aff182SThomas Petazzoni } while (val & 0xff); 796c5aff182SThomas Petazzoni 797c5aff182SThomas Petazzoni /* Stop Tx port activity. Check port Tx activity. Issue stop 7986a20c175SThomas Petazzoni * command for active channels only 7996a20c175SThomas Petazzoni */ 800c5aff182SThomas Petazzoni val = (mvreg_read(pp, MVNETA_TXQ_CMD)) & MVNETA_TXQ_ENABLE_MASK; 801c5aff182SThomas Petazzoni 802c5aff182SThomas Petazzoni if (val != 0) 803c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_TXQ_CMD, 804c5aff182SThomas Petazzoni (val << MVNETA_TXQ_DISABLE_SHIFT)); 805c5aff182SThomas Petazzoni 806c5aff182SThomas Petazzoni /* Wait for all Tx activity to terminate. */ 807c5aff182SThomas Petazzoni count = 0; 808c5aff182SThomas Petazzoni do { 809c5aff182SThomas Petazzoni if (count++ >= MVNETA_TX_DISABLE_TIMEOUT_MSEC) { 810c5aff182SThomas Petazzoni netdev_warn(pp->dev, 811c5aff182SThomas Petazzoni "TIMEOUT for TX stopped status=0x%08x\n", 812c5aff182SThomas Petazzoni val); 813c5aff182SThomas Petazzoni break; 814c5aff182SThomas Petazzoni } 815c5aff182SThomas Petazzoni mdelay(1); 816c5aff182SThomas Petazzoni 817c5aff182SThomas Petazzoni /* Check TX Command reg that all Txqs are stopped */ 818c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_TXQ_CMD); 819c5aff182SThomas Petazzoni 820c5aff182SThomas Petazzoni } while (val & 0xff); 821c5aff182SThomas Petazzoni 822c5aff182SThomas Petazzoni /* Double check to verify that TX FIFO is empty */ 823c5aff182SThomas Petazzoni count = 0; 824c5aff182SThomas Petazzoni do { 825c5aff182SThomas Petazzoni if (count++ >= MVNETA_TX_FIFO_EMPTY_TIMEOUT) { 826c5aff182SThomas Petazzoni netdev_warn(pp->dev, 827c5aff182SThomas Petazzoni "TX FIFO empty timeout status=0x08%x\n", 828c5aff182SThomas Petazzoni val); 829c5aff182SThomas Petazzoni break; 830c5aff182SThomas Petazzoni } 831c5aff182SThomas Petazzoni mdelay(1); 832c5aff182SThomas Petazzoni 833c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_PORT_STATUS); 834c5aff182SThomas Petazzoni } while (!(val & MVNETA_TX_FIFO_EMPTY) && 835c5aff182SThomas Petazzoni (val & MVNETA_TX_IN_PRGRS)); 836c5aff182SThomas Petazzoni 837c5aff182SThomas Petazzoni udelay(200); 838c5aff182SThomas Petazzoni } 839c5aff182SThomas Petazzoni 840c5aff182SThomas Petazzoni /* Enable the port by setting the port enable bit of the MAC control register */ 841c5aff182SThomas Petazzoni static void mvneta_port_enable(struct mvneta_port *pp) 842c5aff182SThomas Petazzoni { 843c5aff182SThomas Petazzoni u32 val; 844c5aff182SThomas Petazzoni 845c5aff182SThomas Petazzoni /* Enable port */ 846c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_GMAC_CTRL_0); 847c5aff182SThomas Petazzoni val |= MVNETA_GMAC0_PORT_ENABLE; 848c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_GMAC_CTRL_0, val); 849c5aff182SThomas Petazzoni } 850c5aff182SThomas Petazzoni 851c5aff182SThomas Petazzoni /* Disable the port and wait for about 200 usec before retuning */ 852c5aff182SThomas Petazzoni static void mvneta_port_disable(struct mvneta_port *pp) 853c5aff182SThomas Petazzoni { 854c5aff182SThomas Petazzoni u32 val; 855c5aff182SThomas Petazzoni 856c5aff182SThomas Petazzoni /* Reset the Enable bit in the Serial Control Register */ 857c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_GMAC_CTRL_0); 858c5aff182SThomas Petazzoni val &= ~MVNETA_GMAC0_PORT_ENABLE; 859c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_GMAC_CTRL_0, val); 860c5aff182SThomas Petazzoni 861c5aff182SThomas Petazzoni udelay(200); 862c5aff182SThomas Petazzoni } 863c5aff182SThomas Petazzoni 864c5aff182SThomas Petazzoni /* Multicast tables methods */ 865c5aff182SThomas Petazzoni 866c5aff182SThomas Petazzoni /* Set all entries in Unicast MAC Table; queue==-1 means reject all */ 867c5aff182SThomas Petazzoni static void mvneta_set_ucast_table(struct mvneta_port *pp, int queue) 868c5aff182SThomas Petazzoni { 869c5aff182SThomas Petazzoni int offset; 870c5aff182SThomas Petazzoni u32 val; 871c5aff182SThomas Petazzoni 872c5aff182SThomas Petazzoni if (queue == -1) { 873c5aff182SThomas Petazzoni val = 0; 874c5aff182SThomas Petazzoni } else { 875c5aff182SThomas Petazzoni val = 0x1 | (queue << 1); 876c5aff182SThomas Petazzoni val |= (val << 24) | (val << 16) | (val << 8); 877c5aff182SThomas Petazzoni } 878c5aff182SThomas Petazzoni 879c5aff182SThomas Petazzoni for (offset = 0; offset <= 0xc; offset += 4) 880c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_DA_FILT_UCAST_BASE + offset, val); 881c5aff182SThomas Petazzoni } 882c5aff182SThomas Petazzoni 883c5aff182SThomas Petazzoni /* Set all entries in Special Multicast MAC Table; queue==-1 means reject all */ 884c5aff182SThomas Petazzoni static void mvneta_set_special_mcast_table(struct mvneta_port *pp, int queue) 885c5aff182SThomas Petazzoni { 886c5aff182SThomas Petazzoni int offset; 887c5aff182SThomas Petazzoni u32 val; 888c5aff182SThomas Petazzoni 889c5aff182SThomas Petazzoni if (queue == -1) { 890c5aff182SThomas Petazzoni val = 0; 891c5aff182SThomas Petazzoni } else { 892c5aff182SThomas Petazzoni val = 0x1 | (queue << 1); 893c5aff182SThomas Petazzoni val |= (val << 24) | (val << 16) | (val << 8); 894c5aff182SThomas Petazzoni } 895c5aff182SThomas Petazzoni 896c5aff182SThomas Petazzoni for (offset = 0; offset <= 0xfc; offset += 4) 897c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_DA_FILT_SPEC_MCAST + offset, val); 898c5aff182SThomas Petazzoni 899c5aff182SThomas Petazzoni } 900c5aff182SThomas Petazzoni 901c5aff182SThomas Petazzoni /* Set all entries in Other Multicast MAC Table. queue==-1 means reject all */ 902c5aff182SThomas Petazzoni static void mvneta_set_other_mcast_table(struct mvneta_port *pp, int queue) 903c5aff182SThomas Petazzoni { 904c5aff182SThomas Petazzoni int offset; 905c5aff182SThomas Petazzoni u32 val; 906c5aff182SThomas Petazzoni 907c5aff182SThomas Petazzoni if (queue == -1) { 908c5aff182SThomas Petazzoni memset(pp->mcast_count, 0, sizeof(pp->mcast_count)); 909c5aff182SThomas Petazzoni val = 0; 910c5aff182SThomas Petazzoni } else { 911c5aff182SThomas Petazzoni memset(pp->mcast_count, 1, sizeof(pp->mcast_count)); 912c5aff182SThomas Petazzoni val = 0x1 | (queue << 1); 913c5aff182SThomas Petazzoni val |= (val << 24) | (val << 16) | (val << 8); 914c5aff182SThomas Petazzoni } 915c5aff182SThomas Petazzoni 916c5aff182SThomas Petazzoni for (offset = 0; offset <= 0xfc; offset += 4) 917c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_DA_FILT_OTH_MCAST + offset, val); 918c5aff182SThomas Petazzoni } 919c5aff182SThomas Petazzoni 920c5aff182SThomas Petazzoni /* This method sets defaults to the NETA port: 921c5aff182SThomas Petazzoni * Clears interrupt Cause and Mask registers. 922c5aff182SThomas Petazzoni * Clears all MAC tables. 923c5aff182SThomas Petazzoni * Sets defaults to all registers. 924c5aff182SThomas Petazzoni * Resets RX and TX descriptor rings. 925c5aff182SThomas Petazzoni * Resets PHY. 926c5aff182SThomas Petazzoni * This method can be called after mvneta_port_down() to return the port 927c5aff182SThomas Petazzoni * settings to defaults. 928c5aff182SThomas Petazzoni */ 929c5aff182SThomas Petazzoni static void mvneta_defaults_set(struct mvneta_port *pp) 930c5aff182SThomas Petazzoni { 931c5aff182SThomas Petazzoni int cpu; 932c5aff182SThomas Petazzoni int queue; 933c5aff182SThomas Petazzoni u32 val; 934c5aff182SThomas Petazzoni 935c5aff182SThomas Petazzoni /* Clear all Cause registers */ 936c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_INTR_NEW_CAUSE, 0); 937c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_INTR_OLD_CAUSE, 0); 938c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_INTR_MISC_CAUSE, 0); 939c5aff182SThomas Petazzoni 940c5aff182SThomas Petazzoni /* Mask all interrupts */ 941c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_INTR_NEW_MASK, 0); 942c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_INTR_OLD_MASK, 0); 943c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_INTR_MISC_MASK, 0); 944c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_INTR_ENABLE, 0); 945c5aff182SThomas Petazzoni 946c5aff182SThomas Petazzoni /* Enable MBUS Retry bit16 */ 947c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_MBUS_RETRY, 0x20); 948c5aff182SThomas Petazzoni 949c5aff182SThomas Petazzoni /* Set CPU queue access map - all CPUs have access to all RX 9506a20c175SThomas Petazzoni * queues and to all TX queues 9516a20c175SThomas Petazzoni */ 952c5aff182SThomas Petazzoni for (cpu = 0; cpu < CONFIG_NR_CPUS; cpu++) 953c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_CPU_MAP(cpu), 954c5aff182SThomas Petazzoni (MVNETA_CPU_RXQ_ACCESS_ALL_MASK | 955c5aff182SThomas Petazzoni MVNETA_CPU_TXQ_ACCESS_ALL_MASK)); 956c5aff182SThomas Petazzoni 957c5aff182SThomas Petazzoni /* Reset RX and TX DMAs */ 958c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_PORT_RX_RESET, MVNETA_PORT_RX_DMA_RESET); 959c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_PORT_TX_RESET, MVNETA_PORT_TX_DMA_RESET); 960c5aff182SThomas Petazzoni 961c5aff182SThomas Petazzoni /* Disable Legacy WRR, Disable EJP, Release from reset */ 962c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_TXQ_CMD_1, 0); 963c5aff182SThomas Petazzoni for (queue = 0; queue < txq_number; queue++) { 964c5aff182SThomas Petazzoni mvreg_write(pp, MVETH_TXQ_TOKEN_COUNT_REG(queue), 0); 965c5aff182SThomas Petazzoni mvreg_write(pp, MVETH_TXQ_TOKEN_CFG_REG(queue), 0); 966c5aff182SThomas Petazzoni } 967c5aff182SThomas Petazzoni 968c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_PORT_TX_RESET, 0); 969c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_PORT_RX_RESET, 0); 970c5aff182SThomas Petazzoni 971c5aff182SThomas Petazzoni /* Set Port Acceleration Mode */ 972c5aff182SThomas Petazzoni val = MVNETA_ACC_MODE_EXT; 973c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_ACC_MODE, val); 974c5aff182SThomas Petazzoni 975c5aff182SThomas Petazzoni /* Update val of portCfg register accordingly with all RxQueue types */ 976c5aff182SThomas Petazzoni val = MVNETA_PORT_CONFIG_DEFL_VALUE(rxq_def); 977c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_PORT_CONFIG, val); 978c5aff182SThomas Petazzoni 979c5aff182SThomas Petazzoni val = 0; 980c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_PORT_CONFIG_EXTEND, val); 981c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_RX_MIN_FRAME_SIZE, 64); 982c5aff182SThomas Petazzoni 983c5aff182SThomas Petazzoni /* Build PORT_SDMA_CONFIG_REG */ 984c5aff182SThomas Petazzoni val = 0; 985c5aff182SThomas Petazzoni 986c5aff182SThomas Petazzoni /* Default burst size */ 987c5aff182SThomas Petazzoni val |= MVNETA_TX_BRST_SZ_MASK(MVNETA_SDMA_BRST_SIZE_16); 988c5aff182SThomas Petazzoni val |= MVNETA_RX_BRST_SZ_MASK(MVNETA_SDMA_BRST_SIZE_16); 9899ad8fef6SThomas Petazzoni val |= MVNETA_RX_NO_DATA_SWAP | MVNETA_TX_NO_DATA_SWAP; 990c5aff182SThomas Petazzoni 9919ad8fef6SThomas Petazzoni #if defined(__BIG_ENDIAN) 9929ad8fef6SThomas Petazzoni val |= MVNETA_DESC_SWAP; 9939ad8fef6SThomas Petazzoni #endif 994c5aff182SThomas Petazzoni 995c5aff182SThomas Petazzoni /* Assign port SDMA configuration */ 996c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_SDMA_CONFIG, val); 997c5aff182SThomas Petazzoni 99871408602SThomas Petazzoni /* Disable PHY polling in hardware, since we're using the 99971408602SThomas Petazzoni * kernel phylib to do this. 100071408602SThomas Petazzoni */ 100171408602SThomas Petazzoni val = mvreg_read(pp, MVNETA_UNIT_CONTROL); 100271408602SThomas Petazzoni val &= ~MVNETA_PHY_POLLING_ENABLE; 100371408602SThomas Petazzoni mvreg_write(pp, MVNETA_UNIT_CONTROL, val); 100471408602SThomas Petazzoni 1005c5aff182SThomas Petazzoni mvneta_set_ucast_table(pp, -1); 1006c5aff182SThomas Petazzoni mvneta_set_special_mcast_table(pp, -1); 1007c5aff182SThomas Petazzoni mvneta_set_other_mcast_table(pp, -1); 1008c5aff182SThomas Petazzoni 1009c5aff182SThomas Petazzoni /* Set port interrupt enable register - default enable all */ 1010c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_INTR_ENABLE, 1011c5aff182SThomas Petazzoni (MVNETA_RXQ_INTR_ENABLE_ALL_MASK 1012c5aff182SThomas Petazzoni | MVNETA_TXQ_INTR_ENABLE_ALL_MASK)); 1013c5aff182SThomas Petazzoni } 1014c5aff182SThomas Petazzoni 1015c5aff182SThomas Petazzoni /* Set max sizes for tx queues */ 1016c5aff182SThomas Petazzoni static void mvneta_txq_max_tx_size_set(struct mvneta_port *pp, int max_tx_size) 1017c5aff182SThomas Petazzoni 1018c5aff182SThomas Petazzoni { 1019c5aff182SThomas Petazzoni u32 val, size, mtu; 1020c5aff182SThomas Petazzoni int queue; 1021c5aff182SThomas Petazzoni 1022c5aff182SThomas Petazzoni mtu = max_tx_size * 8; 1023c5aff182SThomas Petazzoni if (mtu > MVNETA_TX_MTU_MAX) 1024c5aff182SThomas Petazzoni mtu = MVNETA_TX_MTU_MAX; 1025c5aff182SThomas Petazzoni 1026c5aff182SThomas Petazzoni /* Set MTU */ 1027c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_TX_MTU); 1028c5aff182SThomas Petazzoni val &= ~MVNETA_TX_MTU_MAX; 1029c5aff182SThomas Petazzoni val |= mtu; 1030c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_TX_MTU, val); 1031c5aff182SThomas Petazzoni 1032c5aff182SThomas Petazzoni /* TX token size and all TXQs token size must be larger that MTU */ 1033c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_TX_TOKEN_SIZE); 1034c5aff182SThomas Petazzoni 1035c5aff182SThomas Petazzoni size = val & MVNETA_TX_TOKEN_SIZE_MAX; 1036c5aff182SThomas Petazzoni if (size < mtu) { 1037c5aff182SThomas Petazzoni size = mtu; 1038c5aff182SThomas Petazzoni val &= ~MVNETA_TX_TOKEN_SIZE_MAX; 1039c5aff182SThomas Petazzoni val |= size; 1040c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_TX_TOKEN_SIZE, val); 1041c5aff182SThomas Petazzoni } 1042c5aff182SThomas Petazzoni for (queue = 0; queue < txq_number; queue++) { 1043c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_TXQ_TOKEN_SIZE_REG(queue)); 1044c5aff182SThomas Petazzoni 1045c5aff182SThomas Petazzoni size = val & MVNETA_TXQ_TOKEN_SIZE_MAX; 1046c5aff182SThomas Petazzoni if (size < mtu) { 1047c5aff182SThomas Petazzoni size = mtu; 1048c5aff182SThomas Petazzoni val &= ~MVNETA_TXQ_TOKEN_SIZE_MAX; 1049c5aff182SThomas Petazzoni val |= size; 1050c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_TXQ_TOKEN_SIZE_REG(queue), val); 1051c5aff182SThomas Petazzoni } 1052c5aff182SThomas Petazzoni } 1053c5aff182SThomas Petazzoni } 1054c5aff182SThomas Petazzoni 1055c5aff182SThomas Petazzoni /* Set unicast address */ 1056c5aff182SThomas Petazzoni static void mvneta_set_ucast_addr(struct mvneta_port *pp, u8 last_nibble, 1057c5aff182SThomas Petazzoni int queue) 1058c5aff182SThomas Petazzoni { 1059c5aff182SThomas Petazzoni unsigned int unicast_reg; 1060c5aff182SThomas Petazzoni unsigned int tbl_offset; 1061c5aff182SThomas Petazzoni unsigned int reg_offset; 1062c5aff182SThomas Petazzoni 1063c5aff182SThomas Petazzoni /* Locate the Unicast table entry */ 1064c5aff182SThomas Petazzoni last_nibble = (0xf & last_nibble); 1065c5aff182SThomas Petazzoni 1066c5aff182SThomas Petazzoni /* offset from unicast tbl base */ 1067c5aff182SThomas Petazzoni tbl_offset = (last_nibble / 4) * 4; 1068c5aff182SThomas Petazzoni 1069c5aff182SThomas Petazzoni /* offset within the above reg */ 1070c5aff182SThomas Petazzoni reg_offset = last_nibble % 4; 1071c5aff182SThomas Petazzoni 1072c5aff182SThomas Petazzoni unicast_reg = mvreg_read(pp, (MVNETA_DA_FILT_UCAST_BASE + tbl_offset)); 1073c5aff182SThomas Petazzoni 1074c5aff182SThomas Petazzoni if (queue == -1) { 1075c5aff182SThomas Petazzoni /* Clear accepts frame bit at specified unicast DA tbl entry */ 1076c5aff182SThomas Petazzoni unicast_reg &= ~(0xff << (8 * reg_offset)); 1077c5aff182SThomas Petazzoni } else { 1078c5aff182SThomas Petazzoni unicast_reg &= ~(0xff << (8 * reg_offset)); 1079c5aff182SThomas Petazzoni unicast_reg |= ((0x01 | (queue << 1)) << (8 * reg_offset)); 1080c5aff182SThomas Petazzoni } 1081c5aff182SThomas Petazzoni 1082c5aff182SThomas Petazzoni mvreg_write(pp, (MVNETA_DA_FILT_UCAST_BASE + tbl_offset), unicast_reg); 1083c5aff182SThomas Petazzoni } 1084c5aff182SThomas Petazzoni 1085c5aff182SThomas Petazzoni /* Set mac address */ 1086c5aff182SThomas Petazzoni static void mvneta_mac_addr_set(struct mvneta_port *pp, unsigned char *addr, 1087c5aff182SThomas Petazzoni int queue) 1088c5aff182SThomas Petazzoni { 1089c5aff182SThomas Petazzoni unsigned int mac_h; 1090c5aff182SThomas Petazzoni unsigned int mac_l; 1091c5aff182SThomas Petazzoni 1092c5aff182SThomas Petazzoni if (queue != -1) { 1093c5aff182SThomas Petazzoni mac_l = (addr[4] << 8) | (addr[5]); 1094c5aff182SThomas Petazzoni mac_h = (addr[0] << 24) | (addr[1] << 16) | 1095c5aff182SThomas Petazzoni (addr[2] << 8) | (addr[3] << 0); 1096c5aff182SThomas Petazzoni 1097c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_MAC_ADDR_LOW, mac_l); 1098c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_MAC_ADDR_HIGH, mac_h); 1099c5aff182SThomas Petazzoni } 1100c5aff182SThomas Petazzoni 1101c5aff182SThomas Petazzoni /* Accept frames of this address */ 1102c5aff182SThomas Petazzoni mvneta_set_ucast_addr(pp, addr[5], queue); 1103c5aff182SThomas Petazzoni } 1104c5aff182SThomas Petazzoni 11056a20c175SThomas Petazzoni /* Set the number of packets that will be received before RX interrupt 11066a20c175SThomas Petazzoni * will be generated by HW. 1107c5aff182SThomas Petazzoni */ 1108c5aff182SThomas Petazzoni static void mvneta_rx_pkts_coal_set(struct mvneta_port *pp, 1109c5aff182SThomas Petazzoni struct mvneta_rx_queue *rxq, u32 value) 1110c5aff182SThomas Petazzoni { 1111c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_RXQ_THRESHOLD_REG(rxq->id), 1112c5aff182SThomas Petazzoni value | MVNETA_RXQ_NON_OCCUPIED(0)); 1113c5aff182SThomas Petazzoni rxq->pkts_coal = value; 1114c5aff182SThomas Petazzoni } 1115c5aff182SThomas Petazzoni 11166a20c175SThomas Petazzoni /* Set the time delay in usec before RX interrupt will be generated by 11176a20c175SThomas Petazzoni * HW. 1118c5aff182SThomas Petazzoni */ 1119c5aff182SThomas Petazzoni static void mvneta_rx_time_coal_set(struct mvneta_port *pp, 1120c5aff182SThomas Petazzoni struct mvneta_rx_queue *rxq, u32 value) 1121c5aff182SThomas Petazzoni { 1122189dd626SThomas Petazzoni u32 val; 1123189dd626SThomas Petazzoni unsigned long clk_rate; 1124189dd626SThomas Petazzoni 1125189dd626SThomas Petazzoni clk_rate = clk_get_rate(pp->clk); 1126189dd626SThomas Petazzoni val = (clk_rate / 1000000) * value; 1127c5aff182SThomas Petazzoni 1128c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_RXQ_TIME_COAL_REG(rxq->id), val); 1129c5aff182SThomas Petazzoni rxq->time_coal = value; 1130c5aff182SThomas Petazzoni } 1131c5aff182SThomas Petazzoni 1132c5aff182SThomas Petazzoni /* Set threshold for TX_DONE pkts coalescing */ 1133c5aff182SThomas Petazzoni static void mvneta_tx_done_pkts_coal_set(struct mvneta_port *pp, 1134c5aff182SThomas Petazzoni struct mvneta_tx_queue *txq, u32 value) 1135c5aff182SThomas Petazzoni { 1136c5aff182SThomas Petazzoni u32 val; 1137c5aff182SThomas Petazzoni 1138c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_TXQ_SIZE_REG(txq->id)); 1139c5aff182SThomas Petazzoni 1140c5aff182SThomas Petazzoni val &= ~MVNETA_TXQ_SENT_THRESH_ALL_MASK; 1141c5aff182SThomas Petazzoni val |= MVNETA_TXQ_SENT_THRESH_MASK(value); 1142c5aff182SThomas Petazzoni 1143c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_TXQ_SIZE_REG(txq->id), val); 1144c5aff182SThomas Petazzoni 1145c5aff182SThomas Petazzoni txq->done_pkts_coal = value; 1146c5aff182SThomas Petazzoni } 1147c5aff182SThomas Petazzoni 1148c5aff182SThomas Petazzoni /* Handle rx descriptor fill by setting buf_cookie and buf_phys_addr */ 1149c5aff182SThomas Petazzoni static void mvneta_rx_desc_fill(struct mvneta_rx_desc *rx_desc, 1150c5aff182SThomas Petazzoni u32 phys_addr, u32 cookie) 1151c5aff182SThomas Petazzoni { 1152c5aff182SThomas Petazzoni rx_desc->buf_cookie = cookie; 1153c5aff182SThomas Petazzoni rx_desc->buf_phys_addr = phys_addr; 1154c5aff182SThomas Petazzoni } 1155c5aff182SThomas Petazzoni 1156c5aff182SThomas Petazzoni /* Decrement sent descriptors counter */ 1157c5aff182SThomas Petazzoni static void mvneta_txq_sent_desc_dec(struct mvneta_port *pp, 1158c5aff182SThomas Petazzoni struct mvneta_tx_queue *txq, 1159c5aff182SThomas Petazzoni int sent_desc) 1160c5aff182SThomas Petazzoni { 1161c5aff182SThomas Petazzoni u32 val; 1162c5aff182SThomas Petazzoni 1163c5aff182SThomas Petazzoni /* Only 255 TX descriptors can be updated at once */ 1164c5aff182SThomas Petazzoni while (sent_desc > 0xff) { 1165c5aff182SThomas Petazzoni val = 0xff << MVNETA_TXQ_DEC_SENT_SHIFT; 1166c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val); 1167c5aff182SThomas Petazzoni sent_desc = sent_desc - 0xff; 1168c5aff182SThomas Petazzoni } 1169c5aff182SThomas Petazzoni 1170c5aff182SThomas Petazzoni val = sent_desc << MVNETA_TXQ_DEC_SENT_SHIFT; 1171c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val); 1172c5aff182SThomas Petazzoni } 1173c5aff182SThomas Petazzoni 1174c5aff182SThomas Petazzoni /* Get number of TX descriptors already sent by HW */ 1175c5aff182SThomas Petazzoni static int mvneta_txq_sent_desc_num_get(struct mvneta_port *pp, 1176c5aff182SThomas Petazzoni struct mvneta_tx_queue *txq) 1177c5aff182SThomas Petazzoni { 1178c5aff182SThomas Petazzoni u32 val; 1179c5aff182SThomas Petazzoni int sent_desc; 1180c5aff182SThomas Petazzoni 1181c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_TXQ_STATUS_REG(txq->id)); 1182c5aff182SThomas Petazzoni sent_desc = (val & MVNETA_TXQ_SENT_DESC_MASK) >> 1183c5aff182SThomas Petazzoni MVNETA_TXQ_SENT_DESC_SHIFT; 1184c5aff182SThomas Petazzoni 1185c5aff182SThomas Petazzoni return sent_desc; 1186c5aff182SThomas Petazzoni } 1187c5aff182SThomas Petazzoni 11886a20c175SThomas Petazzoni /* Get number of sent descriptors and decrement counter. 1189c5aff182SThomas Petazzoni * The number of sent descriptors is returned. 1190c5aff182SThomas Petazzoni */ 1191c5aff182SThomas Petazzoni static int mvneta_txq_sent_desc_proc(struct mvneta_port *pp, 1192c5aff182SThomas Petazzoni struct mvneta_tx_queue *txq) 1193c5aff182SThomas Petazzoni { 1194c5aff182SThomas Petazzoni int sent_desc; 1195c5aff182SThomas Petazzoni 1196c5aff182SThomas Petazzoni /* Get number of sent descriptors */ 1197c5aff182SThomas Petazzoni sent_desc = mvneta_txq_sent_desc_num_get(pp, txq); 1198c5aff182SThomas Petazzoni 1199c5aff182SThomas Petazzoni /* Decrement sent descriptors counter */ 1200c5aff182SThomas Petazzoni if (sent_desc) 1201c5aff182SThomas Petazzoni mvneta_txq_sent_desc_dec(pp, txq, sent_desc); 1202c5aff182SThomas Petazzoni 1203c5aff182SThomas Petazzoni return sent_desc; 1204c5aff182SThomas Petazzoni } 1205c5aff182SThomas Petazzoni 1206c5aff182SThomas Petazzoni /* Set TXQ descriptors fields relevant for CSUM calculation */ 1207c5aff182SThomas Petazzoni static u32 mvneta_txq_desc_csum(int l3_offs, int l3_proto, 1208c5aff182SThomas Petazzoni int ip_hdr_len, int l4_proto) 1209c5aff182SThomas Petazzoni { 1210c5aff182SThomas Petazzoni u32 command; 1211c5aff182SThomas Petazzoni 1212c5aff182SThomas Petazzoni /* Fields: L3_offset, IP_hdrlen, L3_type, G_IPv4_chk, 12136a20c175SThomas Petazzoni * G_L4_chk, L4_type; required only for checksum 12146a20c175SThomas Petazzoni * calculation 12156a20c175SThomas Petazzoni */ 1216c5aff182SThomas Petazzoni command = l3_offs << MVNETA_TX_L3_OFF_SHIFT; 1217c5aff182SThomas Petazzoni command |= ip_hdr_len << MVNETA_TX_IP_HLEN_SHIFT; 1218c5aff182SThomas Petazzoni 1219c5aff182SThomas Petazzoni if (l3_proto == swab16(ETH_P_IP)) 1220c5aff182SThomas Petazzoni command |= MVNETA_TXD_IP_CSUM; 1221c5aff182SThomas Petazzoni else 1222c5aff182SThomas Petazzoni command |= MVNETA_TX_L3_IP6; 1223c5aff182SThomas Petazzoni 1224c5aff182SThomas Petazzoni if (l4_proto == IPPROTO_TCP) 1225c5aff182SThomas Petazzoni command |= MVNETA_TX_L4_CSUM_FULL; 1226c5aff182SThomas Petazzoni else if (l4_proto == IPPROTO_UDP) 1227c5aff182SThomas Petazzoni command |= MVNETA_TX_L4_UDP | MVNETA_TX_L4_CSUM_FULL; 1228c5aff182SThomas Petazzoni else 1229c5aff182SThomas Petazzoni command |= MVNETA_TX_L4_CSUM_NOT; 1230c5aff182SThomas Petazzoni 1231c5aff182SThomas Petazzoni return command; 1232c5aff182SThomas Petazzoni } 1233c5aff182SThomas Petazzoni 1234c5aff182SThomas Petazzoni 1235c5aff182SThomas Petazzoni /* Display more error info */ 1236c5aff182SThomas Petazzoni static void mvneta_rx_error(struct mvneta_port *pp, 1237c5aff182SThomas Petazzoni struct mvneta_rx_desc *rx_desc) 1238c5aff182SThomas Petazzoni { 1239c5aff182SThomas Petazzoni u32 status = rx_desc->status; 1240c5aff182SThomas Petazzoni 12415428213cSwilly tarreau if (!mvneta_rxq_desc_is_first_last(status)) { 1242c5aff182SThomas Petazzoni netdev_err(pp->dev, 1243c5aff182SThomas Petazzoni "bad rx status %08x (buffer oversize), size=%d\n", 12445428213cSwilly tarreau status, rx_desc->data_size); 1245c5aff182SThomas Petazzoni return; 1246c5aff182SThomas Petazzoni } 1247c5aff182SThomas Petazzoni 1248c5aff182SThomas Petazzoni switch (status & MVNETA_RXD_ERR_CODE_MASK) { 1249c5aff182SThomas Petazzoni case MVNETA_RXD_ERR_CRC: 1250c5aff182SThomas Petazzoni netdev_err(pp->dev, "bad rx status %08x (crc error), size=%d\n", 1251c5aff182SThomas Petazzoni status, rx_desc->data_size); 1252c5aff182SThomas Petazzoni break; 1253c5aff182SThomas Petazzoni case MVNETA_RXD_ERR_OVERRUN: 1254c5aff182SThomas Petazzoni netdev_err(pp->dev, "bad rx status %08x (overrun error), size=%d\n", 1255c5aff182SThomas Petazzoni status, rx_desc->data_size); 1256c5aff182SThomas Petazzoni break; 1257c5aff182SThomas Petazzoni case MVNETA_RXD_ERR_LEN: 1258c5aff182SThomas Petazzoni netdev_err(pp->dev, "bad rx status %08x (max frame length error), size=%d\n", 1259c5aff182SThomas Petazzoni status, rx_desc->data_size); 1260c5aff182SThomas Petazzoni break; 1261c5aff182SThomas Petazzoni case MVNETA_RXD_ERR_RESOURCE: 1262c5aff182SThomas Petazzoni netdev_err(pp->dev, "bad rx status %08x (resource error), size=%d\n", 1263c5aff182SThomas Petazzoni status, rx_desc->data_size); 1264c5aff182SThomas Petazzoni break; 1265c5aff182SThomas Petazzoni } 1266c5aff182SThomas Petazzoni } 1267c5aff182SThomas Petazzoni 12685428213cSwilly tarreau /* Handle RX checksum offload based on the descriptor's status */ 12695428213cSwilly tarreau static void mvneta_rx_csum(struct mvneta_port *pp, u32 status, 1270c5aff182SThomas Petazzoni struct sk_buff *skb) 1271c5aff182SThomas Petazzoni { 12725428213cSwilly tarreau if ((status & MVNETA_RXD_L3_IP4) && 12735428213cSwilly tarreau (status & MVNETA_RXD_L4_CSUM_OK)) { 1274c5aff182SThomas Petazzoni skb->csum = 0; 1275c5aff182SThomas Petazzoni skb->ip_summed = CHECKSUM_UNNECESSARY; 1276c5aff182SThomas Petazzoni return; 1277c5aff182SThomas Petazzoni } 1278c5aff182SThomas Petazzoni 1279c5aff182SThomas Petazzoni skb->ip_summed = CHECKSUM_NONE; 1280c5aff182SThomas Petazzoni } 1281c5aff182SThomas Petazzoni 12826c498974Swilly tarreau /* Return tx queue pointer (find last set bit) according to <cause> returned 12836c498974Swilly tarreau * form tx_done reg. <cause> must not be null. The return value is always a 12846c498974Swilly tarreau * valid queue for matching the first one found in <cause>. 12856c498974Swilly tarreau */ 1286c5aff182SThomas Petazzoni static struct mvneta_tx_queue *mvneta_tx_done_policy(struct mvneta_port *pp, 1287c5aff182SThomas Petazzoni u32 cause) 1288c5aff182SThomas Petazzoni { 1289c5aff182SThomas Petazzoni int queue = fls(cause) - 1; 1290c5aff182SThomas Petazzoni 12916c498974Swilly tarreau return &pp->txqs[queue]; 1292c5aff182SThomas Petazzoni } 1293c5aff182SThomas Petazzoni 1294c5aff182SThomas Petazzoni /* Free tx queue skbuffs */ 1295c5aff182SThomas Petazzoni static void mvneta_txq_bufs_free(struct mvneta_port *pp, 1296c5aff182SThomas Petazzoni struct mvneta_tx_queue *txq, int num) 1297c5aff182SThomas Petazzoni { 1298c5aff182SThomas Petazzoni int i; 1299c5aff182SThomas Petazzoni 1300c5aff182SThomas Petazzoni for (i = 0; i < num; i++) { 1301c5aff182SThomas Petazzoni struct mvneta_tx_desc *tx_desc = txq->descs + 1302c5aff182SThomas Petazzoni txq->txq_get_index; 1303c5aff182SThomas Petazzoni struct sk_buff *skb = txq->tx_skb[txq->txq_get_index]; 1304c5aff182SThomas Petazzoni 1305c5aff182SThomas Petazzoni mvneta_txq_inc_get(txq); 1306c5aff182SThomas Petazzoni 1307c5aff182SThomas Petazzoni if (!skb) 1308c5aff182SThomas Petazzoni continue; 1309c5aff182SThomas Petazzoni 1310c5aff182SThomas Petazzoni dma_unmap_single(pp->dev->dev.parent, tx_desc->buf_phys_addr, 1311c5aff182SThomas Petazzoni tx_desc->data_size, DMA_TO_DEVICE); 1312c5aff182SThomas Petazzoni dev_kfree_skb_any(skb); 1313c5aff182SThomas Petazzoni } 1314c5aff182SThomas Petazzoni } 1315c5aff182SThomas Petazzoni 1316c5aff182SThomas Petazzoni /* Handle end of transmission */ 1317cd713199SArnaud Ebalard static void mvneta_txq_done(struct mvneta_port *pp, 1318c5aff182SThomas Petazzoni struct mvneta_tx_queue *txq) 1319c5aff182SThomas Petazzoni { 1320c5aff182SThomas Petazzoni struct netdev_queue *nq = netdev_get_tx_queue(pp->dev, txq->id); 1321c5aff182SThomas Petazzoni int tx_done; 1322c5aff182SThomas Petazzoni 1323c5aff182SThomas Petazzoni tx_done = mvneta_txq_sent_desc_proc(pp, txq); 1324cd713199SArnaud Ebalard if (!tx_done) 1325cd713199SArnaud Ebalard return; 1326cd713199SArnaud Ebalard 1327c5aff182SThomas Petazzoni mvneta_txq_bufs_free(pp, txq, tx_done); 1328c5aff182SThomas Petazzoni 1329c5aff182SThomas Petazzoni txq->count -= tx_done; 1330c5aff182SThomas Petazzoni 1331c5aff182SThomas Petazzoni if (netif_tx_queue_stopped(nq)) { 1332c5aff182SThomas Petazzoni if (txq->size - txq->count >= MAX_SKB_FRAGS + 1) 1333c5aff182SThomas Petazzoni netif_tx_wake_queue(nq); 1334c5aff182SThomas Petazzoni } 1335c5aff182SThomas Petazzoni } 1336c5aff182SThomas Petazzoni 13378ec2cd48Swilly tarreau static void *mvneta_frag_alloc(const struct mvneta_port *pp) 13388ec2cd48Swilly tarreau { 13398ec2cd48Swilly tarreau if (likely(pp->frag_size <= PAGE_SIZE)) 13408ec2cd48Swilly tarreau return netdev_alloc_frag(pp->frag_size); 13418ec2cd48Swilly tarreau else 13428ec2cd48Swilly tarreau return kmalloc(pp->frag_size, GFP_ATOMIC); 13438ec2cd48Swilly tarreau } 13448ec2cd48Swilly tarreau 13458ec2cd48Swilly tarreau static void mvneta_frag_free(const struct mvneta_port *pp, void *data) 13468ec2cd48Swilly tarreau { 13478ec2cd48Swilly tarreau if (likely(pp->frag_size <= PAGE_SIZE)) 13488ec2cd48Swilly tarreau put_page(virt_to_head_page(data)); 13498ec2cd48Swilly tarreau else 13508ec2cd48Swilly tarreau kfree(data); 13518ec2cd48Swilly tarreau } 13528ec2cd48Swilly tarreau 1353c5aff182SThomas Petazzoni /* Refill processing */ 1354c5aff182SThomas Petazzoni static int mvneta_rx_refill(struct mvneta_port *pp, 1355c5aff182SThomas Petazzoni struct mvneta_rx_desc *rx_desc) 1356c5aff182SThomas Petazzoni 1357c5aff182SThomas Petazzoni { 1358c5aff182SThomas Petazzoni dma_addr_t phys_addr; 13598ec2cd48Swilly tarreau void *data; 1360c5aff182SThomas Petazzoni 13618ec2cd48Swilly tarreau data = mvneta_frag_alloc(pp); 13628ec2cd48Swilly tarreau if (!data) 1363c5aff182SThomas Petazzoni return -ENOMEM; 1364c5aff182SThomas Petazzoni 13658ec2cd48Swilly tarreau phys_addr = dma_map_single(pp->dev->dev.parent, data, 1366c5aff182SThomas Petazzoni MVNETA_RX_BUF_SIZE(pp->pkt_size), 1367c5aff182SThomas Petazzoni DMA_FROM_DEVICE); 1368c5aff182SThomas Petazzoni if (unlikely(dma_mapping_error(pp->dev->dev.parent, phys_addr))) { 13698ec2cd48Swilly tarreau mvneta_frag_free(pp, data); 1370c5aff182SThomas Petazzoni return -ENOMEM; 1371c5aff182SThomas Petazzoni } 1372c5aff182SThomas Petazzoni 13738ec2cd48Swilly tarreau mvneta_rx_desc_fill(rx_desc, phys_addr, (u32)data); 1374c5aff182SThomas Petazzoni return 0; 1375c5aff182SThomas Petazzoni } 1376c5aff182SThomas Petazzoni 1377c5aff182SThomas Petazzoni /* Handle tx checksum */ 1378c5aff182SThomas Petazzoni static u32 mvneta_skb_tx_csum(struct mvneta_port *pp, struct sk_buff *skb) 1379c5aff182SThomas Petazzoni { 1380c5aff182SThomas Petazzoni if (skb->ip_summed == CHECKSUM_PARTIAL) { 1381c5aff182SThomas Petazzoni int ip_hdr_len = 0; 1382c5aff182SThomas Petazzoni u8 l4_proto; 1383c5aff182SThomas Petazzoni 1384c5aff182SThomas Petazzoni if (skb->protocol == htons(ETH_P_IP)) { 1385c5aff182SThomas Petazzoni struct iphdr *ip4h = ip_hdr(skb); 1386c5aff182SThomas Petazzoni 1387c5aff182SThomas Petazzoni /* Calculate IPv4 checksum and L4 checksum */ 1388c5aff182SThomas Petazzoni ip_hdr_len = ip4h->ihl; 1389c5aff182SThomas Petazzoni l4_proto = ip4h->protocol; 1390c5aff182SThomas Petazzoni } else if (skb->protocol == htons(ETH_P_IPV6)) { 1391c5aff182SThomas Petazzoni struct ipv6hdr *ip6h = ipv6_hdr(skb); 1392c5aff182SThomas Petazzoni 1393c5aff182SThomas Petazzoni /* Read l4_protocol from one of IPv6 extra headers */ 1394c5aff182SThomas Petazzoni if (skb_network_header_len(skb) > 0) 1395c5aff182SThomas Petazzoni ip_hdr_len = (skb_network_header_len(skb) >> 2); 1396c5aff182SThomas Petazzoni l4_proto = ip6h->nexthdr; 1397c5aff182SThomas Petazzoni } else 1398c5aff182SThomas Petazzoni return MVNETA_TX_L4_CSUM_NOT; 1399c5aff182SThomas Petazzoni 1400c5aff182SThomas Petazzoni return mvneta_txq_desc_csum(skb_network_offset(skb), 1401c5aff182SThomas Petazzoni skb->protocol, ip_hdr_len, l4_proto); 1402c5aff182SThomas Petazzoni } 1403c5aff182SThomas Petazzoni 1404c5aff182SThomas Petazzoni return MVNETA_TX_L4_CSUM_NOT; 1405c5aff182SThomas Petazzoni } 1406c5aff182SThomas Petazzoni 14076a20c175SThomas Petazzoni /* Returns rx queue pointer (find last set bit) according to causeRxTx 1408c5aff182SThomas Petazzoni * value 1409c5aff182SThomas Petazzoni */ 1410c5aff182SThomas Petazzoni static struct mvneta_rx_queue *mvneta_rx_policy(struct mvneta_port *pp, 1411c5aff182SThomas Petazzoni u32 cause) 1412c5aff182SThomas Petazzoni { 1413c5aff182SThomas Petazzoni int queue = fls(cause >> 8) - 1; 1414c5aff182SThomas Petazzoni 1415c5aff182SThomas Petazzoni return (queue < 0 || queue >= rxq_number) ? NULL : &pp->rxqs[queue]; 1416c5aff182SThomas Petazzoni } 1417c5aff182SThomas Petazzoni 1418c5aff182SThomas Petazzoni /* Drop packets received by the RXQ and free buffers */ 1419c5aff182SThomas Petazzoni static void mvneta_rxq_drop_pkts(struct mvneta_port *pp, 1420c5aff182SThomas Petazzoni struct mvneta_rx_queue *rxq) 1421c5aff182SThomas Petazzoni { 1422c5aff182SThomas Petazzoni int rx_done, i; 1423c5aff182SThomas Petazzoni 1424c5aff182SThomas Petazzoni rx_done = mvneta_rxq_busy_desc_num_get(pp, rxq); 1425c5aff182SThomas Petazzoni for (i = 0; i < rxq->size; i++) { 1426c5aff182SThomas Petazzoni struct mvneta_rx_desc *rx_desc = rxq->descs + i; 14278ec2cd48Swilly tarreau void *data = (void *)rx_desc->buf_cookie; 1428c5aff182SThomas Petazzoni 14298ec2cd48Swilly tarreau mvneta_frag_free(pp, data); 1430c5aff182SThomas Petazzoni dma_unmap_single(pp->dev->dev.parent, rx_desc->buf_phys_addr, 1431a328f3a0SEzequiel Garcia MVNETA_RX_BUF_SIZE(pp->pkt_size), DMA_FROM_DEVICE); 1432c5aff182SThomas Petazzoni } 1433c5aff182SThomas Petazzoni 1434c5aff182SThomas Petazzoni if (rx_done) 1435c5aff182SThomas Petazzoni mvneta_rxq_desc_num_update(pp, rxq, rx_done, rx_done); 1436c5aff182SThomas Petazzoni } 1437c5aff182SThomas Petazzoni 1438c5aff182SThomas Petazzoni /* Main rx processing */ 1439c5aff182SThomas Petazzoni static int mvneta_rx(struct mvneta_port *pp, int rx_todo, 1440c5aff182SThomas Petazzoni struct mvneta_rx_queue *rxq) 1441c5aff182SThomas Petazzoni { 1442c5aff182SThomas Petazzoni struct net_device *dev = pp->dev; 1443c5aff182SThomas Petazzoni int rx_done, rx_filled; 1444dc4277ddSwilly tarreau u32 rcvd_pkts = 0; 1445dc4277ddSwilly tarreau u32 rcvd_bytes = 0; 1446c5aff182SThomas Petazzoni 1447c5aff182SThomas Petazzoni /* Get number of received packets */ 1448c5aff182SThomas Petazzoni rx_done = mvneta_rxq_busy_desc_num_get(pp, rxq); 1449c5aff182SThomas Petazzoni 1450c5aff182SThomas Petazzoni if (rx_todo > rx_done) 1451c5aff182SThomas Petazzoni rx_todo = rx_done; 1452c5aff182SThomas Petazzoni 1453c5aff182SThomas Petazzoni rx_done = 0; 1454c5aff182SThomas Petazzoni rx_filled = 0; 1455c5aff182SThomas Petazzoni 1456c5aff182SThomas Petazzoni /* Fairness NAPI loop */ 1457c5aff182SThomas Petazzoni while (rx_done < rx_todo) { 1458c5aff182SThomas Petazzoni struct mvneta_rx_desc *rx_desc = mvneta_rxq_next_desc_get(rxq); 1459c5aff182SThomas Petazzoni struct sk_buff *skb; 14608ec2cd48Swilly tarreau unsigned char *data; 1461c5aff182SThomas Petazzoni u32 rx_status; 1462c5aff182SThomas Petazzoni int rx_bytes, err; 1463c5aff182SThomas Petazzoni 1464c5aff182SThomas Petazzoni rx_done++; 1465c5aff182SThomas Petazzoni rx_filled++; 1466c5aff182SThomas Petazzoni rx_status = rx_desc->status; 1467f19fadfcSwilly tarreau rx_bytes = rx_desc->data_size - (ETH_FCS_LEN + MVNETA_MH_SIZE); 14688ec2cd48Swilly tarreau data = (unsigned char *)rx_desc->buf_cookie; 1469c5aff182SThomas Petazzoni 14705428213cSwilly tarreau if (!mvneta_rxq_desc_is_first_last(rx_status) || 1471f19fadfcSwilly tarreau (rx_status & MVNETA_RXD_ERR_SUMMARY)) { 1472f19fadfcSwilly tarreau err_drop_frame: 1473c5aff182SThomas Petazzoni dev->stats.rx_errors++; 1474c5aff182SThomas Petazzoni mvneta_rx_error(pp, rx_desc); 14758ec2cd48Swilly tarreau /* leave the descriptor untouched */ 1476c5aff182SThomas Petazzoni continue; 1477c5aff182SThomas Petazzoni } 1478c5aff182SThomas Petazzoni 1479f19fadfcSwilly tarreau if (rx_bytes <= rx_copybreak) { 1480f19fadfcSwilly tarreau /* better copy a small frame and not unmap the DMA region */ 1481f19fadfcSwilly tarreau skb = netdev_alloc_skb_ip_align(dev, rx_bytes); 1482f19fadfcSwilly tarreau if (unlikely(!skb)) 1483f19fadfcSwilly tarreau goto err_drop_frame; 1484f19fadfcSwilly tarreau 1485f19fadfcSwilly tarreau dma_sync_single_range_for_cpu(dev->dev.parent, 1486f19fadfcSwilly tarreau rx_desc->buf_phys_addr, 1487f19fadfcSwilly tarreau MVNETA_MH_SIZE + NET_SKB_PAD, 1488f19fadfcSwilly tarreau rx_bytes, 1489f19fadfcSwilly tarreau DMA_FROM_DEVICE); 1490f19fadfcSwilly tarreau memcpy(skb_put(skb, rx_bytes), 1491f19fadfcSwilly tarreau data + MVNETA_MH_SIZE + NET_SKB_PAD, 1492f19fadfcSwilly tarreau rx_bytes); 1493f19fadfcSwilly tarreau 1494f19fadfcSwilly tarreau skb->protocol = eth_type_trans(skb, dev); 1495f19fadfcSwilly tarreau mvneta_rx_csum(pp, rx_status, skb); 1496f19fadfcSwilly tarreau napi_gro_receive(&pp->napi, skb); 1497f19fadfcSwilly tarreau 1498f19fadfcSwilly tarreau rcvd_pkts++; 1499f19fadfcSwilly tarreau rcvd_bytes += rx_bytes; 1500f19fadfcSwilly tarreau 1501f19fadfcSwilly tarreau /* leave the descriptor and buffer untouched */ 1502f19fadfcSwilly tarreau continue; 1503f19fadfcSwilly tarreau } 1504f19fadfcSwilly tarreau 1505f19fadfcSwilly tarreau skb = build_skb(data, pp->frag_size > PAGE_SIZE ? 0 : pp->frag_size); 1506f19fadfcSwilly tarreau if (!skb) 1507f19fadfcSwilly tarreau goto err_drop_frame; 1508f19fadfcSwilly tarreau 1509f19fadfcSwilly tarreau dma_unmap_single(dev->dev.parent, rx_desc->buf_phys_addr, 1510a328f3a0SEzequiel Garcia MVNETA_RX_BUF_SIZE(pp->pkt_size), DMA_FROM_DEVICE); 1511c5aff182SThomas Petazzoni 1512dc4277ddSwilly tarreau rcvd_pkts++; 1513dc4277ddSwilly tarreau rcvd_bytes += rx_bytes; 1514c5aff182SThomas Petazzoni 1515c5aff182SThomas Petazzoni /* Linux processing */ 15168ec2cd48Swilly tarreau skb_reserve(skb, MVNETA_MH_SIZE + NET_SKB_PAD); 1517c5aff182SThomas Petazzoni skb_put(skb, rx_bytes); 1518c5aff182SThomas Petazzoni 1519c5aff182SThomas Petazzoni skb->protocol = eth_type_trans(skb, dev); 1520c5aff182SThomas Petazzoni 15215428213cSwilly tarreau mvneta_rx_csum(pp, rx_status, skb); 1522c5aff182SThomas Petazzoni 1523c5aff182SThomas Petazzoni napi_gro_receive(&pp->napi, skb); 1524c5aff182SThomas Petazzoni 1525c5aff182SThomas Petazzoni /* Refill processing */ 1526c5aff182SThomas Petazzoni err = mvneta_rx_refill(pp, rx_desc); 1527c5aff182SThomas Petazzoni if (err) { 1528f19fadfcSwilly tarreau netdev_err(dev, "Linux processing - Can't refill\n"); 1529c5aff182SThomas Petazzoni rxq->missed++; 1530c5aff182SThomas Petazzoni rx_filled--; 1531c5aff182SThomas Petazzoni } 1532c5aff182SThomas Petazzoni } 1533c5aff182SThomas Petazzoni 1534dc4277ddSwilly tarreau if (rcvd_pkts) { 153574c41b04Swilly tarreau struct mvneta_pcpu_stats *stats = this_cpu_ptr(pp->stats); 153674c41b04Swilly tarreau 153774c41b04Swilly tarreau u64_stats_update_begin(&stats->syncp); 153874c41b04Swilly tarreau stats->rx_packets += rcvd_pkts; 153974c41b04Swilly tarreau stats->rx_bytes += rcvd_bytes; 154074c41b04Swilly tarreau u64_stats_update_end(&stats->syncp); 1541dc4277ddSwilly tarreau } 1542dc4277ddSwilly tarreau 1543c5aff182SThomas Petazzoni /* Update rxq management counters */ 1544c5aff182SThomas Petazzoni mvneta_rxq_desc_num_update(pp, rxq, rx_done, rx_filled); 1545c5aff182SThomas Petazzoni 1546c5aff182SThomas Petazzoni return rx_done; 1547c5aff182SThomas Petazzoni } 1548c5aff182SThomas Petazzoni 1549c5aff182SThomas Petazzoni /* Handle tx fragmentation processing */ 1550c5aff182SThomas Petazzoni static int mvneta_tx_frag_process(struct mvneta_port *pp, struct sk_buff *skb, 1551c5aff182SThomas Petazzoni struct mvneta_tx_queue *txq) 1552c5aff182SThomas Petazzoni { 1553c5aff182SThomas Petazzoni struct mvneta_tx_desc *tx_desc; 1554c5aff182SThomas Petazzoni int i; 1555c5aff182SThomas Petazzoni 1556c5aff182SThomas Petazzoni for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { 1557c5aff182SThomas Petazzoni skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 1558c5aff182SThomas Petazzoni void *addr = page_address(frag->page.p) + frag->page_offset; 1559c5aff182SThomas Petazzoni 1560c5aff182SThomas Petazzoni tx_desc = mvneta_txq_next_desc_get(txq); 1561c5aff182SThomas Petazzoni tx_desc->data_size = frag->size; 1562c5aff182SThomas Petazzoni 1563c5aff182SThomas Petazzoni tx_desc->buf_phys_addr = 1564c5aff182SThomas Petazzoni dma_map_single(pp->dev->dev.parent, addr, 1565c5aff182SThomas Petazzoni tx_desc->data_size, DMA_TO_DEVICE); 1566c5aff182SThomas Petazzoni 1567c5aff182SThomas Petazzoni if (dma_mapping_error(pp->dev->dev.parent, 1568c5aff182SThomas Petazzoni tx_desc->buf_phys_addr)) { 1569c5aff182SThomas Petazzoni mvneta_txq_desc_put(txq); 1570c5aff182SThomas Petazzoni goto error; 1571c5aff182SThomas Petazzoni } 1572c5aff182SThomas Petazzoni 1573c5aff182SThomas Petazzoni if (i == (skb_shinfo(skb)->nr_frags - 1)) { 1574c5aff182SThomas Petazzoni /* Last descriptor */ 1575c5aff182SThomas Petazzoni tx_desc->command = MVNETA_TXD_L_DESC | MVNETA_TXD_Z_PAD; 1576c5aff182SThomas Petazzoni 1577c5aff182SThomas Petazzoni txq->tx_skb[txq->txq_put_index] = skb; 1578c5aff182SThomas Petazzoni 1579c5aff182SThomas Petazzoni mvneta_txq_inc_put(txq); 1580c5aff182SThomas Petazzoni } else { 1581c5aff182SThomas Petazzoni /* Descriptor in the middle: Not First, Not Last */ 1582c5aff182SThomas Petazzoni tx_desc->command = 0; 1583c5aff182SThomas Petazzoni 1584c5aff182SThomas Petazzoni txq->tx_skb[txq->txq_put_index] = NULL; 1585c5aff182SThomas Petazzoni mvneta_txq_inc_put(txq); 1586c5aff182SThomas Petazzoni } 1587c5aff182SThomas Petazzoni } 1588c5aff182SThomas Petazzoni 1589c5aff182SThomas Petazzoni return 0; 1590c5aff182SThomas Petazzoni 1591c5aff182SThomas Petazzoni error: 1592c5aff182SThomas Petazzoni /* Release all descriptors that were used to map fragments of 15936a20c175SThomas Petazzoni * this packet, as well as the corresponding DMA mappings 15946a20c175SThomas Petazzoni */ 1595c5aff182SThomas Petazzoni for (i = i - 1; i >= 0; i--) { 1596c5aff182SThomas Petazzoni tx_desc = txq->descs + i; 1597c5aff182SThomas Petazzoni dma_unmap_single(pp->dev->dev.parent, 1598c5aff182SThomas Petazzoni tx_desc->buf_phys_addr, 1599c5aff182SThomas Petazzoni tx_desc->data_size, 1600c5aff182SThomas Petazzoni DMA_TO_DEVICE); 1601c5aff182SThomas Petazzoni mvneta_txq_desc_put(txq); 1602c5aff182SThomas Petazzoni } 1603c5aff182SThomas Petazzoni 1604c5aff182SThomas Petazzoni return -ENOMEM; 1605c5aff182SThomas Petazzoni } 1606c5aff182SThomas Petazzoni 1607c5aff182SThomas Petazzoni /* Main tx processing */ 1608c5aff182SThomas Petazzoni static int mvneta_tx(struct sk_buff *skb, struct net_device *dev) 1609c5aff182SThomas Petazzoni { 1610c5aff182SThomas Petazzoni struct mvneta_port *pp = netdev_priv(dev); 1611ee40a116SWilly Tarreau u16 txq_id = skb_get_queue_mapping(skb); 1612ee40a116SWilly Tarreau struct mvneta_tx_queue *txq = &pp->txqs[txq_id]; 1613c5aff182SThomas Petazzoni struct mvneta_tx_desc *tx_desc; 1614c5aff182SThomas Petazzoni struct netdev_queue *nq; 1615c5aff182SThomas Petazzoni int frags = 0; 1616c5aff182SThomas Petazzoni u32 tx_cmd; 1617c5aff182SThomas Petazzoni 1618c5aff182SThomas Petazzoni if (!netif_running(dev)) 1619c5aff182SThomas Petazzoni goto out; 1620c5aff182SThomas Petazzoni 1621c5aff182SThomas Petazzoni frags = skb_shinfo(skb)->nr_frags + 1; 1622ee40a116SWilly Tarreau nq = netdev_get_tx_queue(dev, txq_id); 1623c5aff182SThomas Petazzoni 1624c5aff182SThomas Petazzoni /* Get a descriptor for the first part of the packet */ 1625c5aff182SThomas Petazzoni tx_desc = mvneta_txq_next_desc_get(txq); 1626c5aff182SThomas Petazzoni 1627c5aff182SThomas Petazzoni tx_cmd = mvneta_skb_tx_csum(pp, skb); 1628c5aff182SThomas Petazzoni 1629c5aff182SThomas Petazzoni tx_desc->data_size = skb_headlen(skb); 1630c5aff182SThomas Petazzoni 1631c5aff182SThomas Petazzoni tx_desc->buf_phys_addr = dma_map_single(dev->dev.parent, skb->data, 1632c5aff182SThomas Petazzoni tx_desc->data_size, 1633c5aff182SThomas Petazzoni DMA_TO_DEVICE); 1634c5aff182SThomas Petazzoni if (unlikely(dma_mapping_error(dev->dev.parent, 1635c5aff182SThomas Petazzoni tx_desc->buf_phys_addr))) { 1636c5aff182SThomas Petazzoni mvneta_txq_desc_put(txq); 1637c5aff182SThomas Petazzoni frags = 0; 1638c5aff182SThomas Petazzoni goto out; 1639c5aff182SThomas Petazzoni } 1640c5aff182SThomas Petazzoni 1641c5aff182SThomas Petazzoni if (frags == 1) { 1642c5aff182SThomas Petazzoni /* First and Last descriptor */ 1643c5aff182SThomas Petazzoni tx_cmd |= MVNETA_TXD_FLZ_DESC; 1644c5aff182SThomas Petazzoni tx_desc->command = tx_cmd; 1645c5aff182SThomas Petazzoni txq->tx_skb[txq->txq_put_index] = skb; 1646c5aff182SThomas Petazzoni mvneta_txq_inc_put(txq); 1647c5aff182SThomas Petazzoni } else { 1648c5aff182SThomas Petazzoni /* First but not Last */ 1649c5aff182SThomas Petazzoni tx_cmd |= MVNETA_TXD_F_DESC; 1650c5aff182SThomas Petazzoni txq->tx_skb[txq->txq_put_index] = NULL; 1651c5aff182SThomas Petazzoni mvneta_txq_inc_put(txq); 1652c5aff182SThomas Petazzoni tx_desc->command = tx_cmd; 1653c5aff182SThomas Petazzoni /* Continue with other skb fragments */ 1654c5aff182SThomas Petazzoni if (mvneta_tx_frag_process(pp, skb, txq)) { 1655c5aff182SThomas Petazzoni dma_unmap_single(dev->dev.parent, 1656c5aff182SThomas Petazzoni tx_desc->buf_phys_addr, 1657c5aff182SThomas Petazzoni tx_desc->data_size, 1658c5aff182SThomas Petazzoni DMA_TO_DEVICE); 1659c5aff182SThomas Petazzoni mvneta_txq_desc_put(txq); 1660c5aff182SThomas Petazzoni frags = 0; 1661c5aff182SThomas Petazzoni goto out; 1662c5aff182SThomas Petazzoni } 1663c5aff182SThomas Petazzoni } 1664c5aff182SThomas Petazzoni 1665c5aff182SThomas Petazzoni txq->count += frags; 1666c5aff182SThomas Petazzoni mvneta_txq_pend_desc_add(pp, txq, frags); 1667c5aff182SThomas Petazzoni 1668c5aff182SThomas Petazzoni if (txq->size - txq->count < MAX_SKB_FRAGS + 1) 1669c5aff182SThomas Petazzoni netif_tx_stop_queue(nq); 1670c5aff182SThomas Petazzoni 1671c5aff182SThomas Petazzoni out: 1672c5aff182SThomas Petazzoni if (frags > 0) { 167374c41b04Swilly tarreau struct mvneta_pcpu_stats *stats = this_cpu_ptr(pp->stats); 1674c5aff182SThomas Petazzoni 167574c41b04Swilly tarreau u64_stats_update_begin(&stats->syncp); 167674c41b04Swilly tarreau stats->tx_packets++; 167774c41b04Swilly tarreau stats->tx_bytes += skb->len; 167874c41b04Swilly tarreau u64_stats_update_end(&stats->syncp); 1679c5aff182SThomas Petazzoni } else { 1680c5aff182SThomas Petazzoni dev->stats.tx_dropped++; 1681c5aff182SThomas Petazzoni dev_kfree_skb_any(skb); 1682c5aff182SThomas Petazzoni } 1683c5aff182SThomas Petazzoni 1684c5aff182SThomas Petazzoni return NETDEV_TX_OK; 1685c5aff182SThomas Petazzoni } 1686c5aff182SThomas Petazzoni 1687c5aff182SThomas Petazzoni 1688c5aff182SThomas Petazzoni /* Free tx resources, when resetting a port */ 1689c5aff182SThomas Petazzoni static void mvneta_txq_done_force(struct mvneta_port *pp, 1690c5aff182SThomas Petazzoni struct mvneta_tx_queue *txq) 1691c5aff182SThomas Petazzoni 1692c5aff182SThomas Petazzoni { 1693c5aff182SThomas Petazzoni int tx_done = txq->count; 1694c5aff182SThomas Petazzoni 1695c5aff182SThomas Petazzoni mvneta_txq_bufs_free(pp, txq, tx_done); 1696c5aff182SThomas Petazzoni 1697c5aff182SThomas Petazzoni /* reset txq */ 1698c5aff182SThomas Petazzoni txq->count = 0; 1699c5aff182SThomas Petazzoni txq->txq_put_index = 0; 1700c5aff182SThomas Petazzoni txq->txq_get_index = 0; 1701c5aff182SThomas Petazzoni } 1702c5aff182SThomas Petazzoni 17036c498974Swilly tarreau /* Handle tx done - called in softirq context. The <cause_tx_done> argument 17046c498974Swilly tarreau * must be a valid cause according to MVNETA_TXQ_INTR_MASK_ALL. 17056c498974Swilly tarreau */ 17060713a86aSArnaud Ebalard static void mvneta_tx_done_gbe(struct mvneta_port *pp, u32 cause_tx_done) 1707c5aff182SThomas Petazzoni { 1708c5aff182SThomas Petazzoni struct mvneta_tx_queue *txq; 1709c5aff182SThomas Petazzoni struct netdev_queue *nq; 1710c5aff182SThomas Petazzoni 17116c498974Swilly tarreau while (cause_tx_done) { 1712c5aff182SThomas Petazzoni txq = mvneta_tx_done_policy(pp, cause_tx_done); 1713c5aff182SThomas Petazzoni 1714c5aff182SThomas Petazzoni nq = netdev_get_tx_queue(pp->dev, txq->id); 1715c5aff182SThomas Petazzoni __netif_tx_lock(nq, smp_processor_id()); 1716c5aff182SThomas Petazzoni 17170713a86aSArnaud Ebalard if (txq->count) 17180713a86aSArnaud Ebalard mvneta_txq_done(pp, txq); 1719c5aff182SThomas Petazzoni 1720c5aff182SThomas Petazzoni __netif_tx_unlock(nq); 1721c5aff182SThomas Petazzoni cause_tx_done &= ~((1 << txq->id)); 1722c5aff182SThomas Petazzoni } 1723c5aff182SThomas Petazzoni } 1724c5aff182SThomas Petazzoni 17256a20c175SThomas Petazzoni /* Compute crc8 of the specified address, using a unique algorithm , 1726c5aff182SThomas Petazzoni * according to hw spec, different than generic crc8 algorithm 1727c5aff182SThomas Petazzoni */ 1728c5aff182SThomas Petazzoni static int mvneta_addr_crc(unsigned char *addr) 1729c5aff182SThomas Petazzoni { 1730c5aff182SThomas Petazzoni int crc = 0; 1731c5aff182SThomas Petazzoni int i; 1732c5aff182SThomas Petazzoni 1733c5aff182SThomas Petazzoni for (i = 0; i < ETH_ALEN; i++) { 1734c5aff182SThomas Petazzoni int j; 1735c5aff182SThomas Petazzoni 1736c5aff182SThomas Petazzoni crc = (crc ^ addr[i]) << 8; 1737c5aff182SThomas Petazzoni for (j = 7; j >= 0; j--) { 1738c5aff182SThomas Petazzoni if (crc & (0x100 << j)) 1739c5aff182SThomas Petazzoni crc ^= 0x107 << j; 1740c5aff182SThomas Petazzoni } 1741c5aff182SThomas Petazzoni } 1742c5aff182SThomas Petazzoni 1743c5aff182SThomas Petazzoni return crc; 1744c5aff182SThomas Petazzoni } 1745c5aff182SThomas Petazzoni 1746c5aff182SThomas Petazzoni /* This method controls the net device special MAC multicast support. 1747c5aff182SThomas Petazzoni * The Special Multicast Table for MAC addresses supports MAC of the form 1748c5aff182SThomas Petazzoni * 0x01-00-5E-00-00-XX (where XX is between 0x00 and 0xFF). 1749c5aff182SThomas Petazzoni * The MAC DA[7:0] bits are used as a pointer to the Special Multicast 1750c5aff182SThomas Petazzoni * Table entries in the DA-Filter table. This method set the Special 1751c5aff182SThomas Petazzoni * Multicast Table appropriate entry. 1752c5aff182SThomas Petazzoni */ 1753c5aff182SThomas Petazzoni static void mvneta_set_special_mcast_addr(struct mvneta_port *pp, 1754c5aff182SThomas Petazzoni unsigned char last_byte, 1755c5aff182SThomas Petazzoni int queue) 1756c5aff182SThomas Petazzoni { 1757c5aff182SThomas Petazzoni unsigned int smc_table_reg; 1758c5aff182SThomas Petazzoni unsigned int tbl_offset; 1759c5aff182SThomas Petazzoni unsigned int reg_offset; 1760c5aff182SThomas Petazzoni 1761c5aff182SThomas Petazzoni /* Register offset from SMC table base */ 1762c5aff182SThomas Petazzoni tbl_offset = (last_byte / 4); 1763c5aff182SThomas Petazzoni /* Entry offset within the above reg */ 1764c5aff182SThomas Petazzoni reg_offset = last_byte % 4; 1765c5aff182SThomas Petazzoni 1766c5aff182SThomas Petazzoni smc_table_reg = mvreg_read(pp, (MVNETA_DA_FILT_SPEC_MCAST 1767c5aff182SThomas Petazzoni + tbl_offset * 4)); 1768c5aff182SThomas Petazzoni 1769c5aff182SThomas Petazzoni if (queue == -1) 1770c5aff182SThomas Petazzoni smc_table_reg &= ~(0xff << (8 * reg_offset)); 1771c5aff182SThomas Petazzoni else { 1772c5aff182SThomas Petazzoni smc_table_reg &= ~(0xff << (8 * reg_offset)); 1773c5aff182SThomas Petazzoni smc_table_reg |= ((0x01 | (queue << 1)) << (8 * reg_offset)); 1774c5aff182SThomas Petazzoni } 1775c5aff182SThomas Petazzoni 1776c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_DA_FILT_SPEC_MCAST + tbl_offset * 4, 1777c5aff182SThomas Petazzoni smc_table_reg); 1778c5aff182SThomas Petazzoni } 1779c5aff182SThomas Petazzoni 1780c5aff182SThomas Petazzoni /* This method controls the network device Other MAC multicast support. 1781c5aff182SThomas Petazzoni * The Other Multicast Table is used for multicast of another type. 1782c5aff182SThomas Petazzoni * A CRC-8 is used as an index to the Other Multicast Table entries 1783c5aff182SThomas Petazzoni * in the DA-Filter table. 1784c5aff182SThomas Petazzoni * The method gets the CRC-8 value from the calling routine and 1785c5aff182SThomas Petazzoni * sets the Other Multicast Table appropriate entry according to the 1786c5aff182SThomas Petazzoni * specified CRC-8 . 1787c5aff182SThomas Petazzoni */ 1788c5aff182SThomas Petazzoni static void mvneta_set_other_mcast_addr(struct mvneta_port *pp, 1789c5aff182SThomas Petazzoni unsigned char crc8, 1790c5aff182SThomas Petazzoni int queue) 1791c5aff182SThomas Petazzoni { 1792c5aff182SThomas Petazzoni unsigned int omc_table_reg; 1793c5aff182SThomas Petazzoni unsigned int tbl_offset; 1794c5aff182SThomas Petazzoni unsigned int reg_offset; 1795c5aff182SThomas Petazzoni 1796c5aff182SThomas Petazzoni tbl_offset = (crc8 / 4) * 4; /* Register offset from OMC table base */ 1797c5aff182SThomas Petazzoni reg_offset = crc8 % 4; /* Entry offset within the above reg */ 1798c5aff182SThomas Petazzoni 1799c5aff182SThomas Petazzoni omc_table_reg = mvreg_read(pp, MVNETA_DA_FILT_OTH_MCAST + tbl_offset); 1800c5aff182SThomas Petazzoni 1801c5aff182SThomas Petazzoni if (queue == -1) { 1802c5aff182SThomas Petazzoni /* Clear accepts frame bit at specified Other DA table entry */ 1803c5aff182SThomas Petazzoni omc_table_reg &= ~(0xff << (8 * reg_offset)); 1804c5aff182SThomas Petazzoni } else { 1805c5aff182SThomas Petazzoni omc_table_reg &= ~(0xff << (8 * reg_offset)); 1806c5aff182SThomas Petazzoni omc_table_reg |= ((0x01 | (queue << 1)) << (8 * reg_offset)); 1807c5aff182SThomas Petazzoni } 1808c5aff182SThomas Petazzoni 1809c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_DA_FILT_OTH_MCAST + tbl_offset, omc_table_reg); 1810c5aff182SThomas Petazzoni } 1811c5aff182SThomas Petazzoni 1812c5aff182SThomas Petazzoni /* The network device supports multicast using two tables: 1813c5aff182SThomas Petazzoni * 1) Special Multicast Table for MAC addresses of the form 1814c5aff182SThomas Petazzoni * 0x01-00-5E-00-00-XX (where XX is between 0x00 and 0xFF). 1815c5aff182SThomas Petazzoni * The MAC DA[7:0] bits are used as a pointer to the Special Multicast 1816c5aff182SThomas Petazzoni * Table entries in the DA-Filter table. 1817c5aff182SThomas Petazzoni * 2) Other Multicast Table for multicast of another type. A CRC-8 value 1818c5aff182SThomas Petazzoni * is used as an index to the Other Multicast Table entries in the 1819c5aff182SThomas Petazzoni * DA-Filter table. 1820c5aff182SThomas Petazzoni */ 1821c5aff182SThomas Petazzoni static int mvneta_mcast_addr_set(struct mvneta_port *pp, unsigned char *p_addr, 1822c5aff182SThomas Petazzoni int queue) 1823c5aff182SThomas Petazzoni { 1824c5aff182SThomas Petazzoni unsigned char crc_result = 0; 1825c5aff182SThomas Petazzoni 1826c5aff182SThomas Petazzoni if (memcmp(p_addr, "\x01\x00\x5e\x00\x00", 5) == 0) { 1827c5aff182SThomas Petazzoni mvneta_set_special_mcast_addr(pp, p_addr[5], queue); 1828c5aff182SThomas Petazzoni return 0; 1829c5aff182SThomas Petazzoni } 1830c5aff182SThomas Petazzoni 1831c5aff182SThomas Petazzoni crc_result = mvneta_addr_crc(p_addr); 1832c5aff182SThomas Petazzoni if (queue == -1) { 1833c5aff182SThomas Petazzoni if (pp->mcast_count[crc_result] == 0) { 1834c5aff182SThomas Petazzoni netdev_info(pp->dev, "No valid Mcast for crc8=0x%02x\n", 1835c5aff182SThomas Petazzoni crc_result); 1836c5aff182SThomas Petazzoni return -EINVAL; 1837c5aff182SThomas Petazzoni } 1838c5aff182SThomas Petazzoni 1839c5aff182SThomas Petazzoni pp->mcast_count[crc_result]--; 1840c5aff182SThomas Petazzoni if (pp->mcast_count[crc_result] != 0) { 1841c5aff182SThomas Petazzoni netdev_info(pp->dev, 1842c5aff182SThomas Petazzoni "After delete there are %d valid Mcast for crc8=0x%02x\n", 1843c5aff182SThomas Petazzoni pp->mcast_count[crc_result], crc_result); 1844c5aff182SThomas Petazzoni return -EINVAL; 1845c5aff182SThomas Petazzoni } 1846c5aff182SThomas Petazzoni } else 1847c5aff182SThomas Petazzoni pp->mcast_count[crc_result]++; 1848c5aff182SThomas Petazzoni 1849c5aff182SThomas Petazzoni mvneta_set_other_mcast_addr(pp, crc_result, queue); 1850c5aff182SThomas Petazzoni 1851c5aff182SThomas Petazzoni return 0; 1852c5aff182SThomas Petazzoni } 1853c5aff182SThomas Petazzoni 1854c5aff182SThomas Petazzoni /* Configure Fitering mode of Ethernet port */ 1855c5aff182SThomas Petazzoni static void mvneta_rx_unicast_promisc_set(struct mvneta_port *pp, 1856c5aff182SThomas Petazzoni int is_promisc) 1857c5aff182SThomas Petazzoni { 1858c5aff182SThomas Petazzoni u32 port_cfg_reg, val; 1859c5aff182SThomas Petazzoni 1860c5aff182SThomas Petazzoni port_cfg_reg = mvreg_read(pp, MVNETA_PORT_CONFIG); 1861c5aff182SThomas Petazzoni 1862c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_TYPE_PRIO); 1863c5aff182SThomas Petazzoni 1864c5aff182SThomas Petazzoni /* Set / Clear UPM bit in port configuration register */ 1865c5aff182SThomas Petazzoni if (is_promisc) { 1866c5aff182SThomas Petazzoni /* Accept all Unicast addresses */ 1867c5aff182SThomas Petazzoni port_cfg_reg |= MVNETA_UNI_PROMISC_MODE; 1868c5aff182SThomas Petazzoni val |= MVNETA_FORCE_UNI; 1869c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_MAC_ADDR_LOW, 0xffff); 1870c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_MAC_ADDR_HIGH, 0xffffffff); 1871c5aff182SThomas Petazzoni } else { 1872c5aff182SThomas Petazzoni /* Reject all Unicast addresses */ 1873c5aff182SThomas Petazzoni port_cfg_reg &= ~MVNETA_UNI_PROMISC_MODE; 1874c5aff182SThomas Petazzoni val &= ~MVNETA_FORCE_UNI; 1875c5aff182SThomas Petazzoni } 1876c5aff182SThomas Petazzoni 1877c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_PORT_CONFIG, port_cfg_reg); 1878c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_TYPE_PRIO, val); 1879c5aff182SThomas Petazzoni } 1880c5aff182SThomas Petazzoni 1881c5aff182SThomas Petazzoni /* register unicast and multicast addresses */ 1882c5aff182SThomas Petazzoni static void mvneta_set_rx_mode(struct net_device *dev) 1883c5aff182SThomas Petazzoni { 1884c5aff182SThomas Petazzoni struct mvneta_port *pp = netdev_priv(dev); 1885c5aff182SThomas Petazzoni struct netdev_hw_addr *ha; 1886c5aff182SThomas Petazzoni 1887c5aff182SThomas Petazzoni if (dev->flags & IFF_PROMISC) { 1888c5aff182SThomas Petazzoni /* Accept all: Multicast + Unicast */ 1889c5aff182SThomas Petazzoni mvneta_rx_unicast_promisc_set(pp, 1); 1890c5aff182SThomas Petazzoni mvneta_set_ucast_table(pp, rxq_def); 1891c5aff182SThomas Petazzoni mvneta_set_special_mcast_table(pp, rxq_def); 1892c5aff182SThomas Petazzoni mvneta_set_other_mcast_table(pp, rxq_def); 1893c5aff182SThomas Petazzoni } else { 1894c5aff182SThomas Petazzoni /* Accept single Unicast */ 1895c5aff182SThomas Petazzoni mvneta_rx_unicast_promisc_set(pp, 0); 1896c5aff182SThomas Petazzoni mvneta_set_ucast_table(pp, -1); 1897c5aff182SThomas Petazzoni mvneta_mac_addr_set(pp, dev->dev_addr, rxq_def); 1898c5aff182SThomas Petazzoni 1899c5aff182SThomas Petazzoni if (dev->flags & IFF_ALLMULTI) { 1900c5aff182SThomas Petazzoni /* Accept all multicast */ 1901c5aff182SThomas Petazzoni mvneta_set_special_mcast_table(pp, rxq_def); 1902c5aff182SThomas Petazzoni mvneta_set_other_mcast_table(pp, rxq_def); 1903c5aff182SThomas Petazzoni } else { 1904c5aff182SThomas Petazzoni /* Accept only initialized multicast */ 1905c5aff182SThomas Petazzoni mvneta_set_special_mcast_table(pp, -1); 1906c5aff182SThomas Petazzoni mvneta_set_other_mcast_table(pp, -1); 1907c5aff182SThomas Petazzoni 1908c5aff182SThomas Petazzoni if (!netdev_mc_empty(dev)) { 1909c5aff182SThomas Petazzoni netdev_for_each_mc_addr(ha, dev) { 1910c5aff182SThomas Petazzoni mvneta_mcast_addr_set(pp, ha->addr, 1911c5aff182SThomas Petazzoni rxq_def); 1912c5aff182SThomas Petazzoni } 1913c5aff182SThomas Petazzoni } 1914c5aff182SThomas Petazzoni } 1915c5aff182SThomas Petazzoni } 1916c5aff182SThomas Petazzoni } 1917c5aff182SThomas Petazzoni 1918c5aff182SThomas Petazzoni /* Interrupt handling - the callback for request_irq() */ 1919c5aff182SThomas Petazzoni static irqreturn_t mvneta_isr(int irq, void *dev_id) 1920c5aff182SThomas Petazzoni { 1921c5aff182SThomas Petazzoni struct mvneta_port *pp = (struct mvneta_port *)dev_id; 1922c5aff182SThomas Petazzoni 1923c5aff182SThomas Petazzoni /* Mask all interrupts */ 1924c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_INTR_NEW_MASK, 0); 1925c5aff182SThomas Petazzoni 1926c5aff182SThomas Petazzoni napi_schedule(&pp->napi); 1927c5aff182SThomas Petazzoni 1928c5aff182SThomas Petazzoni return IRQ_HANDLED; 1929c5aff182SThomas Petazzoni } 1930c5aff182SThomas Petazzoni 1931c5aff182SThomas Petazzoni /* NAPI handler 1932c5aff182SThomas Petazzoni * Bits 0 - 7 of the causeRxTx register indicate that are transmitted 1933c5aff182SThomas Petazzoni * packets on the corresponding TXQ (Bit 0 is for TX queue 1). 1934c5aff182SThomas Petazzoni * Bits 8 -15 of the cause Rx Tx register indicate that are received 1935c5aff182SThomas Petazzoni * packets on the corresponding RXQ (Bit 8 is for RX queue 0). 1936c5aff182SThomas Petazzoni * Each CPU has its own causeRxTx register 1937c5aff182SThomas Petazzoni */ 1938c5aff182SThomas Petazzoni static int mvneta_poll(struct napi_struct *napi, int budget) 1939c5aff182SThomas Petazzoni { 1940c5aff182SThomas Petazzoni int rx_done = 0; 1941c5aff182SThomas Petazzoni u32 cause_rx_tx; 1942c5aff182SThomas Petazzoni unsigned long flags; 1943c5aff182SThomas Petazzoni struct mvneta_port *pp = netdev_priv(napi->dev); 1944c5aff182SThomas Petazzoni 1945c5aff182SThomas Petazzoni if (!netif_running(pp->dev)) { 1946c5aff182SThomas Petazzoni napi_complete(napi); 1947c5aff182SThomas Petazzoni return rx_done; 1948c5aff182SThomas Petazzoni } 1949c5aff182SThomas Petazzoni 1950c5aff182SThomas Petazzoni /* Read cause register */ 1951c5aff182SThomas Petazzoni cause_rx_tx = mvreg_read(pp, MVNETA_INTR_NEW_CAUSE) & 195271f6d1b3Swilly tarreau (MVNETA_RX_INTR_MASK(rxq_number) | MVNETA_TX_INTR_MASK(txq_number)); 195371f6d1b3Swilly tarreau 195471f6d1b3Swilly tarreau /* Release Tx descriptors */ 195571f6d1b3Swilly tarreau if (cause_rx_tx & MVNETA_TX_INTR_MASK_ALL) { 19560713a86aSArnaud Ebalard mvneta_tx_done_gbe(pp, (cause_rx_tx & MVNETA_TX_INTR_MASK_ALL)); 195771f6d1b3Swilly tarreau cause_rx_tx &= ~MVNETA_TX_INTR_MASK_ALL; 195871f6d1b3Swilly tarreau } 1959c5aff182SThomas Petazzoni 19606a20c175SThomas Petazzoni /* For the case where the last mvneta_poll did not process all 1961c5aff182SThomas Petazzoni * RX packets 1962c5aff182SThomas Petazzoni */ 1963c5aff182SThomas Petazzoni cause_rx_tx |= pp->cause_rx_tx; 1964c5aff182SThomas Petazzoni if (rxq_number > 1) { 196571f6d1b3Swilly tarreau while ((cause_rx_tx & MVNETA_RX_INTR_MASK_ALL) && (budget > 0)) { 1966c5aff182SThomas Petazzoni int count; 1967c5aff182SThomas Petazzoni struct mvneta_rx_queue *rxq; 1968c5aff182SThomas Petazzoni /* get rx queue number from cause_rx_tx */ 1969c5aff182SThomas Petazzoni rxq = mvneta_rx_policy(pp, cause_rx_tx); 1970c5aff182SThomas Petazzoni if (!rxq) 1971c5aff182SThomas Petazzoni break; 1972c5aff182SThomas Petazzoni 1973c5aff182SThomas Petazzoni /* process the packet in that rx queue */ 1974c5aff182SThomas Petazzoni count = mvneta_rx(pp, budget, rxq); 1975c5aff182SThomas Petazzoni rx_done += count; 1976c5aff182SThomas Petazzoni budget -= count; 1977c5aff182SThomas Petazzoni if (budget > 0) { 19786a20c175SThomas Petazzoni /* set off the rx bit of the 19796a20c175SThomas Petazzoni * corresponding bit in the cause rx 19806a20c175SThomas Petazzoni * tx register, so that next iteration 19816a20c175SThomas Petazzoni * will find the next rx queue where 19826a20c175SThomas Petazzoni * packets are received on 19836a20c175SThomas Petazzoni */ 1984c5aff182SThomas Petazzoni cause_rx_tx &= ~((1 << rxq->id) << 8); 1985c5aff182SThomas Petazzoni } 1986c5aff182SThomas Petazzoni } 1987c5aff182SThomas Petazzoni } else { 1988c5aff182SThomas Petazzoni rx_done = mvneta_rx(pp, budget, &pp->rxqs[rxq_def]); 1989c5aff182SThomas Petazzoni budget -= rx_done; 1990c5aff182SThomas Petazzoni } 1991c5aff182SThomas Petazzoni 1992c5aff182SThomas Petazzoni if (budget > 0) { 1993c5aff182SThomas Petazzoni cause_rx_tx = 0; 1994c5aff182SThomas Petazzoni napi_complete(napi); 1995c5aff182SThomas Petazzoni local_irq_save(flags); 1996c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_INTR_NEW_MASK, 199771f6d1b3Swilly tarreau MVNETA_RX_INTR_MASK(rxq_number) | MVNETA_TX_INTR_MASK(txq_number)); 1998c5aff182SThomas Petazzoni local_irq_restore(flags); 1999c5aff182SThomas Petazzoni } 2000c5aff182SThomas Petazzoni 2001c5aff182SThomas Petazzoni pp->cause_rx_tx = cause_rx_tx; 2002c5aff182SThomas Petazzoni return rx_done; 2003c5aff182SThomas Petazzoni } 2004c5aff182SThomas Petazzoni 2005c5aff182SThomas Petazzoni /* Handle rxq fill: allocates rxq skbs; called when initializing a port */ 2006c5aff182SThomas Petazzoni static int mvneta_rxq_fill(struct mvneta_port *pp, struct mvneta_rx_queue *rxq, 2007c5aff182SThomas Petazzoni int num) 2008c5aff182SThomas Petazzoni { 2009c5aff182SThomas Petazzoni int i; 2010c5aff182SThomas Petazzoni 2011c5aff182SThomas Petazzoni for (i = 0; i < num; i++) { 2012a1a65ab1Swilly tarreau memset(rxq->descs + i, 0, sizeof(struct mvneta_rx_desc)); 2013a1a65ab1Swilly tarreau if (mvneta_rx_refill(pp, rxq->descs + i) != 0) { 2014a1a65ab1Swilly tarreau netdev_err(pp->dev, "%s:rxq %d, %d of %d buffs filled\n", 2015c5aff182SThomas Petazzoni __func__, rxq->id, i, num); 2016c5aff182SThomas Petazzoni break; 2017c5aff182SThomas Petazzoni } 2018c5aff182SThomas Petazzoni } 2019c5aff182SThomas Petazzoni 2020c5aff182SThomas Petazzoni /* Add this number of RX descriptors as non occupied (ready to 20216a20c175SThomas Petazzoni * get packets) 20226a20c175SThomas Petazzoni */ 2023c5aff182SThomas Petazzoni mvneta_rxq_non_occup_desc_add(pp, rxq, i); 2024c5aff182SThomas Petazzoni 2025c5aff182SThomas Petazzoni return i; 2026c5aff182SThomas Petazzoni } 2027c5aff182SThomas Petazzoni 2028c5aff182SThomas Petazzoni /* Free all packets pending transmit from all TXQs and reset TX port */ 2029c5aff182SThomas Petazzoni static void mvneta_tx_reset(struct mvneta_port *pp) 2030c5aff182SThomas Petazzoni { 2031c5aff182SThomas Petazzoni int queue; 2032c5aff182SThomas Petazzoni 2033c5aff182SThomas Petazzoni /* free the skb's in the hal tx ring */ 2034c5aff182SThomas Petazzoni for (queue = 0; queue < txq_number; queue++) 2035c5aff182SThomas Petazzoni mvneta_txq_done_force(pp, &pp->txqs[queue]); 2036c5aff182SThomas Petazzoni 2037c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_PORT_TX_RESET, MVNETA_PORT_TX_DMA_RESET); 2038c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_PORT_TX_RESET, 0); 2039c5aff182SThomas Petazzoni } 2040c5aff182SThomas Petazzoni 2041c5aff182SThomas Petazzoni static void mvneta_rx_reset(struct mvneta_port *pp) 2042c5aff182SThomas Petazzoni { 2043c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_PORT_RX_RESET, MVNETA_PORT_RX_DMA_RESET); 2044c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_PORT_RX_RESET, 0); 2045c5aff182SThomas Petazzoni } 2046c5aff182SThomas Petazzoni 2047c5aff182SThomas Petazzoni /* Rx/Tx queue initialization/cleanup methods */ 2048c5aff182SThomas Petazzoni 2049c5aff182SThomas Petazzoni /* Create a specified RX queue */ 2050c5aff182SThomas Petazzoni static int mvneta_rxq_init(struct mvneta_port *pp, 2051c5aff182SThomas Petazzoni struct mvneta_rx_queue *rxq) 2052c5aff182SThomas Petazzoni 2053c5aff182SThomas Petazzoni { 2054c5aff182SThomas Petazzoni rxq->size = pp->rx_ring_size; 2055c5aff182SThomas Petazzoni 2056c5aff182SThomas Petazzoni /* Allocate memory for RX descriptors */ 2057c5aff182SThomas Petazzoni rxq->descs = dma_alloc_coherent(pp->dev->dev.parent, 2058c5aff182SThomas Petazzoni rxq->size * MVNETA_DESC_ALIGNED_SIZE, 2059c5aff182SThomas Petazzoni &rxq->descs_phys, GFP_KERNEL); 2060d0320f75SJoe Perches if (rxq->descs == NULL) 2061c5aff182SThomas Petazzoni return -ENOMEM; 2062c5aff182SThomas Petazzoni 2063c5aff182SThomas Petazzoni BUG_ON(rxq->descs != 2064c5aff182SThomas Petazzoni PTR_ALIGN(rxq->descs, MVNETA_CPU_D_CACHE_LINE_SIZE)); 2065c5aff182SThomas Petazzoni 2066c5aff182SThomas Petazzoni rxq->last_desc = rxq->size - 1; 2067c5aff182SThomas Petazzoni 2068c5aff182SThomas Petazzoni /* Set Rx descriptors queue starting address */ 2069c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_RXQ_BASE_ADDR_REG(rxq->id), rxq->descs_phys); 2070c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_RXQ_SIZE_REG(rxq->id), rxq->size); 2071c5aff182SThomas Petazzoni 2072c5aff182SThomas Petazzoni /* Set Offset */ 2073c5aff182SThomas Petazzoni mvneta_rxq_offset_set(pp, rxq, NET_SKB_PAD); 2074c5aff182SThomas Petazzoni 2075c5aff182SThomas Petazzoni /* Set coalescing pkts and time */ 2076c5aff182SThomas Petazzoni mvneta_rx_pkts_coal_set(pp, rxq, rxq->pkts_coal); 2077c5aff182SThomas Petazzoni mvneta_rx_time_coal_set(pp, rxq, rxq->time_coal); 2078c5aff182SThomas Petazzoni 2079c5aff182SThomas Petazzoni /* Fill RXQ with buffers from RX pool */ 2080c5aff182SThomas Petazzoni mvneta_rxq_buf_size_set(pp, rxq, MVNETA_RX_BUF_SIZE(pp->pkt_size)); 2081c5aff182SThomas Petazzoni mvneta_rxq_bm_disable(pp, rxq); 2082c5aff182SThomas Petazzoni mvneta_rxq_fill(pp, rxq, rxq->size); 2083c5aff182SThomas Petazzoni 2084c5aff182SThomas Petazzoni return 0; 2085c5aff182SThomas Petazzoni } 2086c5aff182SThomas Petazzoni 2087c5aff182SThomas Petazzoni /* Cleanup Rx queue */ 2088c5aff182SThomas Petazzoni static void mvneta_rxq_deinit(struct mvneta_port *pp, 2089c5aff182SThomas Petazzoni struct mvneta_rx_queue *rxq) 2090c5aff182SThomas Petazzoni { 2091c5aff182SThomas Petazzoni mvneta_rxq_drop_pkts(pp, rxq); 2092c5aff182SThomas Petazzoni 2093c5aff182SThomas Petazzoni if (rxq->descs) 2094c5aff182SThomas Petazzoni dma_free_coherent(pp->dev->dev.parent, 2095c5aff182SThomas Petazzoni rxq->size * MVNETA_DESC_ALIGNED_SIZE, 2096c5aff182SThomas Petazzoni rxq->descs, 2097c5aff182SThomas Petazzoni rxq->descs_phys); 2098c5aff182SThomas Petazzoni 2099c5aff182SThomas Petazzoni rxq->descs = NULL; 2100c5aff182SThomas Petazzoni rxq->last_desc = 0; 2101c5aff182SThomas Petazzoni rxq->next_desc_to_proc = 0; 2102c5aff182SThomas Petazzoni rxq->descs_phys = 0; 2103c5aff182SThomas Petazzoni } 2104c5aff182SThomas Petazzoni 2105c5aff182SThomas Petazzoni /* Create and initialize a tx queue */ 2106c5aff182SThomas Petazzoni static int mvneta_txq_init(struct mvneta_port *pp, 2107c5aff182SThomas Petazzoni struct mvneta_tx_queue *txq) 2108c5aff182SThomas Petazzoni { 2109c5aff182SThomas Petazzoni txq->size = pp->tx_ring_size; 2110c5aff182SThomas Petazzoni 2111c5aff182SThomas Petazzoni /* Allocate memory for TX descriptors */ 2112c5aff182SThomas Petazzoni txq->descs = dma_alloc_coherent(pp->dev->dev.parent, 2113c5aff182SThomas Petazzoni txq->size * MVNETA_DESC_ALIGNED_SIZE, 2114c5aff182SThomas Petazzoni &txq->descs_phys, GFP_KERNEL); 2115d0320f75SJoe Perches if (txq->descs == NULL) 2116c5aff182SThomas Petazzoni return -ENOMEM; 2117c5aff182SThomas Petazzoni 2118c5aff182SThomas Petazzoni /* Make sure descriptor address is cache line size aligned */ 2119c5aff182SThomas Petazzoni BUG_ON(txq->descs != 2120c5aff182SThomas Petazzoni PTR_ALIGN(txq->descs, MVNETA_CPU_D_CACHE_LINE_SIZE)); 2121c5aff182SThomas Petazzoni 2122c5aff182SThomas Petazzoni txq->last_desc = txq->size - 1; 2123c5aff182SThomas Petazzoni 2124c5aff182SThomas Petazzoni /* Set maximum bandwidth for enabled TXQs */ 2125c5aff182SThomas Petazzoni mvreg_write(pp, MVETH_TXQ_TOKEN_CFG_REG(txq->id), 0x03ffffff); 2126c5aff182SThomas Petazzoni mvreg_write(pp, MVETH_TXQ_TOKEN_COUNT_REG(txq->id), 0x3fffffff); 2127c5aff182SThomas Petazzoni 2128c5aff182SThomas Petazzoni /* Set Tx descriptors queue starting address */ 2129c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_TXQ_BASE_ADDR_REG(txq->id), txq->descs_phys); 2130c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_TXQ_SIZE_REG(txq->id), txq->size); 2131c5aff182SThomas Petazzoni 2132c5aff182SThomas Petazzoni txq->tx_skb = kmalloc(txq->size * sizeof(*txq->tx_skb), GFP_KERNEL); 2133c5aff182SThomas Petazzoni if (txq->tx_skb == NULL) { 2134c5aff182SThomas Petazzoni dma_free_coherent(pp->dev->dev.parent, 2135c5aff182SThomas Petazzoni txq->size * MVNETA_DESC_ALIGNED_SIZE, 2136c5aff182SThomas Petazzoni txq->descs, txq->descs_phys); 2137c5aff182SThomas Petazzoni return -ENOMEM; 2138c5aff182SThomas Petazzoni } 2139c5aff182SThomas Petazzoni mvneta_tx_done_pkts_coal_set(pp, txq, txq->done_pkts_coal); 2140c5aff182SThomas Petazzoni 2141c5aff182SThomas Petazzoni return 0; 2142c5aff182SThomas Petazzoni } 2143c5aff182SThomas Petazzoni 2144c5aff182SThomas Petazzoni /* Free allocated resources when mvneta_txq_init() fails to allocate memory*/ 2145c5aff182SThomas Petazzoni static void mvneta_txq_deinit(struct mvneta_port *pp, 2146c5aff182SThomas Petazzoni struct mvneta_tx_queue *txq) 2147c5aff182SThomas Petazzoni { 2148c5aff182SThomas Petazzoni kfree(txq->tx_skb); 2149c5aff182SThomas Petazzoni 2150c5aff182SThomas Petazzoni if (txq->descs) 2151c5aff182SThomas Petazzoni dma_free_coherent(pp->dev->dev.parent, 2152c5aff182SThomas Petazzoni txq->size * MVNETA_DESC_ALIGNED_SIZE, 2153c5aff182SThomas Petazzoni txq->descs, txq->descs_phys); 2154c5aff182SThomas Petazzoni 2155c5aff182SThomas Petazzoni txq->descs = NULL; 2156c5aff182SThomas Petazzoni txq->last_desc = 0; 2157c5aff182SThomas Petazzoni txq->next_desc_to_proc = 0; 2158c5aff182SThomas Petazzoni txq->descs_phys = 0; 2159c5aff182SThomas Petazzoni 2160c5aff182SThomas Petazzoni /* Set minimum bandwidth for disabled TXQs */ 2161c5aff182SThomas Petazzoni mvreg_write(pp, MVETH_TXQ_TOKEN_CFG_REG(txq->id), 0); 2162c5aff182SThomas Petazzoni mvreg_write(pp, MVETH_TXQ_TOKEN_COUNT_REG(txq->id), 0); 2163c5aff182SThomas Petazzoni 2164c5aff182SThomas Petazzoni /* Set Tx descriptors queue starting address and size */ 2165c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_TXQ_BASE_ADDR_REG(txq->id), 0); 2166c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_TXQ_SIZE_REG(txq->id), 0); 2167c5aff182SThomas Petazzoni } 2168c5aff182SThomas Petazzoni 2169c5aff182SThomas Petazzoni /* Cleanup all Tx queues */ 2170c5aff182SThomas Petazzoni static void mvneta_cleanup_txqs(struct mvneta_port *pp) 2171c5aff182SThomas Petazzoni { 2172c5aff182SThomas Petazzoni int queue; 2173c5aff182SThomas Petazzoni 2174c5aff182SThomas Petazzoni for (queue = 0; queue < txq_number; queue++) 2175c5aff182SThomas Petazzoni mvneta_txq_deinit(pp, &pp->txqs[queue]); 2176c5aff182SThomas Petazzoni } 2177c5aff182SThomas Petazzoni 2178c5aff182SThomas Petazzoni /* Cleanup all Rx queues */ 2179c5aff182SThomas Petazzoni static void mvneta_cleanup_rxqs(struct mvneta_port *pp) 2180c5aff182SThomas Petazzoni { 2181c5aff182SThomas Petazzoni int queue; 2182c5aff182SThomas Petazzoni 2183c5aff182SThomas Petazzoni for (queue = 0; queue < rxq_number; queue++) 2184c5aff182SThomas Petazzoni mvneta_rxq_deinit(pp, &pp->rxqs[queue]); 2185c5aff182SThomas Petazzoni } 2186c5aff182SThomas Petazzoni 2187c5aff182SThomas Petazzoni 2188c5aff182SThomas Petazzoni /* Init all Rx queues */ 2189c5aff182SThomas Petazzoni static int mvneta_setup_rxqs(struct mvneta_port *pp) 2190c5aff182SThomas Petazzoni { 2191c5aff182SThomas Petazzoni int queue; 2192c5aff182SThomas Petazzoni 2193c5aff182SThomas Petazzoni for (queue = 0; queue < rxq_number; queue++) { 2194c5aff182SThomas Petazzoni int err = mvneta_rxq_init(pp, &pp->rxqs[queue]); 2195c5aff182SThomas Petazzoni if (err) { 2196c5aff182SThomas Petazzoni netdev_err(pp->dev, "%s: can't create rxq=%d\n", 2197c5aff182SThomas Petazzoni __func__, queue); 2198c5aff182SThomas Petazzoni mvneta_cleanup_rxqs(pp); 2199c5aff182SThomas Petazzoni return err; 2200c5aff182SThomas Petazzoni } 2201c5aff182SThomas Petazzoni } 2202c5aff182SThomas Petazzoni 2203c5aff182SThomas Petazzoni return 0; 2204c5aff182SThomas Petazzoni } 2205c5aff182SThomas Petazzoni 2206c5aff182SThomas Petazzoni /* Init all tx queues */ 2207c5aff182SThomas Petazzoni static int mvneta_setup_txqs(struct mvneta_port *pp) 2208c5aff182SThomas Petazzoni { 2209c5aff182SThomas Petazzoni int queue; 2210c5aff182SThomas Petazzoni 2211c5aff182SThomas Petazzoni for (queue = 0; queue < txq_number; queue++) { 2212c5aff182SThomas Petazzoni int err = mvneta_txq_init(pp, &pp->txqs[queue]); 2213c5aff182SThomas Petazzoni if (err) { 2214c5aff182SThomas Petazzoni netdev_err(pp->dev, "%s: can't create txq=%d\n", 2215c5aff182SThomas Petazzoni __func__, queue); 2216c5aff182SThomas Petazzoni mvneta_cleanup_txqs(pp); 2217c5aff182SThomas Petazzoni return err; 2218c5aff182SThomas Petazzoni } 2219c5aff182SThomas Petazzoni } 2220c5aff182SThomas Petazzoni 2221c5aff182SThomas Petazzoni return 0; 2222c5aff182SThomas Petazzoni } 2223c5aff182SThomas Petazzoni 2224c5aff182SThomas Petazzoni static void mvneta_start_dev(struct mvneta_port *pp) 2225c5aff182SThomas Petazzoni { 2226c5aff182SThomas Petazzoni mvneta_max_rx_size_set(pp, pp->pkt_size); 2227c5aff182SThomas Petazzoni mvneta_txq_max_tx_size_set(pp, pp->pkt_size); 2228c5aff182SThomas Petazzoni 2229c5aff182SThomas Petazzoni /* start the Rx/Tx activity */ 2230c5aff182SThomas Petazzoni mvneta_port_enable(pp); 2231c5aff182SThomas Petazzoni 2232c5aff182SThomas Petazzoni /* Enable polling on the port */ 2233c5aff182SThomas Petazzoni napi_enable(&pp->napi); 2234c5aff182SThomas Petazzoni 2235c5aff182SThomas Petazzoni /* Unmask interrupts */ 2236c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_INTR_NEW_MASK, 223771f6d1b3Swilly tarreau MVNETA_RX_INTR_MASK(rxq_number) | MVNETA_TX_INTR_MASK(txq_number)); 2238c5aff182SThomas Petazzoni 2239c5aff182SThomas Petazzoni phy_start(pp->phy_dev); 2240c5aff182SThomas Petazzoni netif_tx_start_all_queues(pp->dev); 2241c5aff182SThomas Petazzoni } 2242c5aff182SThomas Petazzoni 2243c5aff182SThomas Petazzoni static void mvneta_stop_dev(struct mvneta_port *pp) 2244c5aff182SThomas Petazzoni { 2245c5aff182SThomas Petazzoni phy_stop(pp->phy_dev); 2246c5aff182SThomas Petazzoni 2247c5aff182SThomas Petazzoni napi_disable(&pp->napi); 2248c5aff182SThomas Petazzoni 2249c5aff182SThomas Petazzoni netif_carrier_off(pp->dev); 2250c5aff182SThomas Petazzoni 2251c5aff182SThomas Petazzoni mvneta_port_down(pp); 2252c5aff182SThomas Petazzoni netif_tx_stop_all_queues(pp->dev); 2253c5aff182SThomas Petazzoni 2254c5aff182SThomas Petazzoni /* Stop the port activity */ 2255c5aff182SThomas Petazzoni mvneta_port_disable(pp); 2256c5aff182SThomas Petazzoni 2257c5aff182SThomas Petazzoni /* Clear all ethernet port interrupts */ 2258c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_INTR_MISC_CAUSE, 0); 2259c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_INTR_OLD_CAUSE, 0); 2260c5aff182SThomas Petazzoni 2261c5aff182SThomas Petazzoni /* Mask all ethernet port interrupts */ 2262c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_INTR_NEW_MASK, 0); 2263c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_INTR_OLD_MASK, 0); 2264c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_INTR_MISC_MASK, 0); 2265c5aff182SThomas Petazzoni 2266c5aff182SThomas Petazzoni mvneta_tx_reset(pp); 2267c5aff182SThomas Petazzoni mvneta_rx_reset(pp); 2268c5aff182SThomas Petazzoni } 2269c5aff182SThomas Petazzoni 2270c5aff182SThomas Petazzoni /* Return positive if MTU is valid */ 2271c5aff182SThomas Petazzoni static int mvneta_check_mtu_valid(struct net_device *dev, int mtu) 2272c5aff182SThomas Petazzoni { 2273c5aff182SThomas Petazzoni if (mtu < 68) { 2274c5aff182SThomas Petazzoni netdev_err(dev, "cannot change mtu to less than 68\n"); 2275c5aff182SThomas Petazzoni return -EINVAL; 2276c5aff182SThomas Petazzoni } 2277c5aff182SThomas Petazzoni 2278c5aff182SThomas Petazzoni /* 9676 == 9700 - 20 and rounding to 8 */ 2279c5aff182SThomas Petazzoni if (mtu > 9676) { 2280c5aff182SThomas Petazzoni netdev_info(dev, "Illegal MTU value %d, round to 9676\n", mtu); 2281c5aff182SThomas Petazzoni mtu = 9676; 2282c5aff182SThomas Petazzoni } 2283c5aff182SThomas Petazzoni 2284c5aff182SThomas Petazzoni if (!IS_ALIGNED(MVNETA_RX_PKT_SIZE(mtu), 8)) { 2285c5aff182SThomas Petazzoni netdev_info(dev, "Illegal MTU value %d, rounding to %d\n", 2286c5aff182SThomas Petazzoni mtu, ALIGN(MVNETA_RX_PKT_SIZE(mtu), 8)); 2287c5aff182SThomas Petazzoni mtu = ALIGN(MVNETA_RX_PKT_SIZE(mtu), 8); 2288c5aff182SThomas Petazzoni } 2289c5aff182SThomas Petazzoni 2290c5aff182SThomas Petazzoni return mtu; 2291c5aff182SThomas Petazzoni } 2292c5aff182SThomas Petazzoni 2293c5aff182SThomas Petazzoni /* Change the device mtu */ 2294c5aff182SThomas Petazzoni static int mvneta_change_mtu(struct net_device *dev, int mtu) 2295c5aff182SThomas Petazzoni { 2296c5aff182SThomas Petazzoni struct mvneta_port *pp = netdev_priv(dev); 2297c5aff182SThomas Petazzoni int ret; 2298c5aff182SThomas Petazzoni 2299c5aff182SThomas Petazzoni mtu = mvneta_check_mtu_valid(dev, mtu); 2300c5aff182SThomas Petazzoni if (mtu < 0) 2301c5aff182SThomas Petazzoni return -EINVAL; 2302c5aff182SThomas Petazzoni 2303c5aff182SThomas Petazzoni dev->mtu = mtu; 2304c5aff182SThomas Petazzoni 2305c5aff182SThomas Petazzoni if (!netif_running(dev)) 2306c5aff182SThomas Petazzoni return 0; 2307c5aff182SThomas Petazzoni 23086a20c175SThomas Petazzoni /* The interface is running, so we have to force a 2309c5aff182SThomas Petazzoni * reallocation of the RXQs 2310c5aff182SThomas Petazzoni */ 2311c5aff182SThomas Petazzoni mvneta_stop_dev(pp); 2312c5aff182SThomas Petazzoni 2313c5aff182SThomas Petazzoni mvneta_cleanup_txqs(pp); 2314c5aff182SThomas Petazzoni mvneta_cleanup_rxqs(pp); 2315c5aff182SThomas Petazzoni 2316c5aff182SThomas Petazzoni pp->pkt_size = MVNETA_RX_PKT_SIZE(pp->dev->mtu); 23178ec2cd48Swilly tarreau pp->frag_size = SKB_DATA_ALIGN(MVNETA_RX_BUF_SIZE(pp->pkt_size)) + 23188ec2cd48Swilly tarreau SKB_DATA_ALIGN(sizeof(struct skb_shared_info)); 2319c5aff182SThomas Petazzoni 2320c5aff182SThomas Petazzoni ret = mvneta_setup_rxqs(pp); 2321c5aff182SThomas Petazzoni if (ret) { 2322c5aff182SThomas Petazzoni netdev_err(pp->dev, "unable to setup rxqs after MTU change\n"); 2323c5aff182SThomas Petazzoni return ret; 2324c5aff182SThomas Petazzoni } 2325c5aff182SThomas Petazzoni 2326c5aff182SThomas Petazzoni mvneta_setup_txqs(pp); 2327c5aff182SThomas Petazzoni 2328c5aff182SThomas Petazzoni mvneta_start_dev(pp); 2329c5aff182SThomas Petazzoni mvneta_port_up(pp); 2330c5aff182SThomas Petazzoni 2331c5aff182SThomas Petazzoni return 0; 2332c5aff182SThomas Petazzoni } 2333c5aff182SThomas Petazzoni 23348cc3e439SThomas Petazzoni /* Get mac address */ 23358cc3e439SThomas Petazzoni static void mvneta_get_mac_addr(struct mvneta_port *pp, unsigned char *addr) 23368cc3e439SThomas Petazzoni { 23378cc3e439SThomas Petazzoni u32 mac_addr_l, mac_addr_h; 23388cc3e439SThomas Petazzoni 23398cc3e439SThomas Petazzoni mac_addr_l = mvreg_read(pp, MVNETA_MAC_ADDR_LOW); 23408cc3e439SThomas Petazzoni mac_addr_h = mvreg_read(pp, MVNETA_MAC_ADDR_HIGH); 23418cc3e439SThomas Petazzoni addr[0] = (mac_addr_h >> 24) & 0xFF; 23428cc3e439SThomas Petazzoni addr[1] = (mac_addr_h >> 16) & 0xFF; 23438cc3e439SThomas Petazzoni addr[2] = (mac_addr_h >> 8) & 0xFF; 23448cc3e439SThomas Petazzoni addr[3] = mac_addr_h & 0xFF; 23458cc3e439SThomas Petazzoni addr[4] = (mac_addr_l >> 8) & 0xFF; 23468cc3e439SThomas Petazzoni addr[5] = mac_addr_l & 0xFF; 23478cc3e439SThomas Petazzoni } 23488cc3e439SThomas Petazzoni 2349c5aff182SThomas Petazzoni /* Handle setting mac address */ 2350c5aff182SThomas Petazzoni static int mvneta_set_mac_addr(struct net_device *dev, void *addr) 2351c5aff182SThomas Petazzoni { 2352c5aff182SThomas Petazzoni struct mvneta_port *pp = netdev_priv(dev); 2353c5aff182SThomas Petazzoni u8 *mac = addr + 2; 2354c5aff182SThomas Petazzoni int i; 2355c5aff182SThomas Petazzoni 2356c5aff182SThomas Petazzoni if (netif_running(dev)) 2357c5aff182SThomas Petazzoni return -EBUSY; 2358c5aff182SThomas Petazzoni 2359c5aff182SThomas Petazzoni /* Remove previous address table entry */ 2360c5aff182SThomas Petazzoni mvneta_mac_addr_set(pp, dev->dev_addr, -1); 2361c5aff182SThomas Petazzoni 2362c5aff182SThomas Petazzoni /* Set new addr in hw */ 2363c5aff182SThomas Petazzoni mvneta_mac_addr_set(pp, mac, rxq_def); 2364c5aff182SThomas Petazzoni 2365c5aff182SThomas Petazzoni /* Set addr in the device */ 2366c5aff182SThomas Petazzoni for (i = 0; i < ETH_ALEN; i++) 2367c5aff182SThomas Petazzoni dev->dev_addr[i] = mac[i]; 2368c5aff182SThomas Petazzoni 2369c5aff182SThomas Petazzoni return 0; 2370c5aff182SThomas Petazzoni } 2371c5aff182SThomas Petazzoni 2372c5aff182SThomas Petazzoni static void mvneta_adjust_link(struct net_device *ndev) 2373c5aff182SThomas Petazzoni { 2374c5aff182SThomas Petazzoni struct mvneta_port *pp = netdev_priv(ndev); 2375c5aff182SThomas Petazzoni struct phy_device *phydev = pp->phy_dev; 2376c5aff182SThomas Petazzoni int status_change = 0; 2377c5aff182SThomas Petazzoni 2378c5aff182SThomas Petazzoni if (phydev->link) { 2379c5aff182SThomas Petazzoni if ((pp->speed != phydev->speed) || 2380c5aff182SThomas Petazzoni (pp->duplex != phydev->duplex)) { 2381c5aff182SThomas Petazzoni u32 val; 2382c5aff182SThomas Petazzoni 2383c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG); 2384c5aff182SThomas Petazzoni val &= ~(MVNETA_GMAC_CONFIG_MII_SPEED | 2385c5aff182SThomas Petazzoni MVNETA_GMAC_CONFIG_GMII_SPEED | 238671408602SThomas Petazzoni MVNETA_GMAC_CONFIG_FULL_DUPLEX | 238771408602SThomas Petazzoni MVNETA_GMAC_AN_SPEED_EN | 238871408602SThomas Petazzoni MVNETA_GMAC_AN_DUPLEX_EN); 2389c5aff182SThomas Petazzoni 2390c5aff182SThomas Petazzoni if (phydev->duplex) 2391c5aff182SThomas Petazzoni val |= MVNETA_GMAC_CONFIG_FULL_DUPLEX; 2392c5aff182SThomas Petazzoni 2393c5aff182SThomas Petazzoni if (phydev->speed == SPEED_1000) 2394c5aff182SThomas Petazzoni val |= MVNETA_GMAC_CONFIG_GMII_SPEED; 2395c5aff182SThomas Petazzoni else 2396c5aff182SThomas Petazzoni val |= MVNETA_GMAC_CONFIG_MII_SPEED; 2397c5aff182SThomas Petazzoni 2398c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val); 2399c5aff182SThomas Petazzoni 2400c5aff182SThomas Petazzoni pp->duplex = phydev->duplex; 2401c5aff182SThomas Petazzoni pp->speed = phydev->speed; 2402c5aff182SThomas Petazzoni } 2403c5aff182SThomas Petazzoni } 2404c5aff182SThomas Petazzoni 2405c5aff182SThomas Petazzoni if (phydev->link != pp->link) { 2406c5aff182SThomas Petazzoni if (!phydev->link) { 2407c5aff182SThomas Petazzoni pp->duplex = -1; 2408c5aff182SThomas Petazzoni pp->speed = 0; 2409c5aff182SThomas Petazzoni } 2410c5aff182SThomas Petazzoni 2411c5aff182SThomas Petazzoni pp->link = phydev->link; 2412c5aff182SThomas Petazzoni status_change = 1; 2413c5aff182SThomas Petazzoni } 2414c5aff182SThomas Petazzoni 2415c5aff182SThomas Petazzoni if (status_change) { 2416c5aff182SThomas Petazzoni if (phydev->link) { 2417c5aff182SThomas Petazzoni u32 val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG); 2418c5aff182SThomas Petazzoni val |= (MVNETA_GMAC_FORCE_LINK_PASS | 2419c5aff182SThomas Petazzoni MVNETA_GMAC_FORCE_LINK_DOWN); 2420c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val); 2421c5aff182SThomas Petazzoni mvneta_port_up(pp); 2422c5aff182SThomas Petazzoni netdev_info(pp->dev, "link up\n"); 2423c5aff182SThomas Petazzoni } else { 2424c5aff182SThomas Petazzoni mvneta_port_down(pp); 2425c5aff182SThomas Petazzoni netdev_info(pp->dev, "link down\n"); 2426c5aff182SThomas Petazzoni } 2427c5aff182SThomas Petazzoni } 2428c5aff182SThomas Petazzoni } 2429c5aff182SThomas Petazzoni 2430c5aff182SThomas Petazzoni static int mvneta_mdio_probe(struct mvneta_port *pp) 2431c5aff182SThomas Petazzoni { 2432c5aff182SThomas Petazzoni struct phy_device *phy_dev; 2433c5aff182SThomas Petazzoni 2434c5aff182SThomas Petazzoni phy_dev = of_phy_connect(pp->dev, pp->phy_node, mvneta_adjust_link, 0, 2435c5aff182SThomas Petazzoni pp->phy_interface); 2436c5aff182SThomas Petazzoni if (!phy_dev) { 2437c5aff182SThomas Petazzoni netdev_err(pp->dev, "could not find the PHY\n"); 2438c5aff182SThomas Petazzoni return -ENODEV; 2439c5aff182SThomas Petazzoni } 2440c5aff182SThomas Petazzoni 2441c5aff182SThomas Petazzoni phy_dev->supported &= PHY_GBIT_FEATURES; 2442c5aff182SThomas Petazzoni phy_dev->advertising = phy_dev->supported; 2443c5aff182SThomas Petazzoni 2444c5aff182SThomas Petazzoni pp->phy_dev = phy_dev; 2445c5aff182SThomas Petazzoni pp->link = 0; 2446c5aff182SThomas Petazzoni pp->duplex = 0; 2447c5aff182SThomas Petazzoni pp->speed = 0; 2448c5aff182SThomas Petazzoni 2449c5aff182SThomas Petazzoni return 0; 2450c5aff182SThomas Petazzoni } 2451c5aff182SThomas Petazzoni 2452c5aff182SThomas Petazzoni static void mvneta_mdio_remove(struct mvneta_port *pp) 2453c5aff182SThomas Petazzoni { 2454c5aff182SThomas Petazzoni phy_disconnect(pp->phy_dev); 2455c5aff182SThomas Petazzoni pp->phy_dev = NULL; 2456c5aff182SThomas Petazzoni } 2457c5aff182SThomas Petazzoni 2458c5aff182SThomas Petazzoni static int mvneta_open(struct net_device *dev) 2459c5aff182SThomas Petazzoni { 2460c5aff182SThomas Petazzoni struct mvneta_port *pp = netdev_priv(dev); 2461c5aff182SThomas Petazzoni int ret; 2462c5aff182SThomas Petazzoni 2463c5aff182SThomas Petazzoni mvneta_mac_addr_set(pp, dev->dev_addr, rxq_def); 2464c5aff182SThomas Petazzoni 2465c5aff182SThomas Petazzoni pp->pkt_size = MVNETA_RX_PKT_SIZE(pp->dev->mtu); 24668ec2cd48Swilly tarreau pp->frag_size = SKB_DATA_ALIGN(MVNETA_RX_BUF_SIZE(pp->pkt_size)) + 24678ec2cd48Swilly tarreau SKB_DATA_ALIGN(sizeof(struct skb_shared_info)); 2468c5aff182SThomas Petazzoni 2469c5aff182SThomas Petazzoni ret = mvneta_setup_rxqs(pp); 2470c5aff182SThomas Petazzoni if (ret) 2471c5aff182SThomas Petazzoni return ret; 2472c5aff182SThomas Petazzoni 2473c5aff182SThomas Petazzoni ret = mvneta_setup_txqs(pp); 2474c5aff182SThomas Petazzoni if (ret) 2475c5aff182SThomas Petazzoni goto err_cleanup_rxqs; 2476c5aff182SThomas Petazzoni 2477c5aff182SThomas Petazzoni /* Connect to port interrupt line */ 2478c5aff182SThomas Petazzoni ret = request_irq(pp->dev->irq, mvneta_isr, 0, 2479c5aff182SThomas Petazzoni MVNETA_DRIVER_NAME, pp); 2480c5aff182SThomas Petazzoni if (ret) { 2481c5aff182SThomas Petazzoni netdev_err(pp->dev, "cannot request irq %d\n", pp->dev->irq); 2482c5aff182SThomas Petazzoni goto err_cleanup_txqs; 2483c5aff182SThomas Petazzoni } 2484c5aff182SThomas Petazzoni 2485c5aff182SThomas Petazzoni /* In default link is down */ 2486c5aff182SThomas Petazzoni netif_carrier_off(pp->dev); 2487c5aff182SThomas Petazzoni 2488c5aff182SThomas Petazzoni ret = mvneta_mdio_probe(pp); 2489c5aff182SThomas Petazzoni if (ret < 0) { 2490c5aff182SThomas Petazzoni netdev_err(dev, "cannot probe MDIO bus\n"); 2491c5aff182SThomas Petazzoni goto err_free_irq; 2492c5aff182SThomas Petazzoni } 2493c5aff182SThomas Petazzoni 2494c5aff182SThomas Petazzoni mvneta_start_dev(pp); 2495c5aff182SThomas Petazzoni 2496c5aff182SThomas Petazzoni return 0; 2497c5aff182SThomas Petazzoni 2498c5aff182SThomas Petazzoni err_free_irq: 2499c5aff182SThomas Petazzoni free_irq(pp->dev->irq, pp); 2500c5aff182SThomas Petazzoni err_cleanup_txqs: 2501c5aff182SThomas Petazzoni mvneta_cleanup_txqs(pp); 2502c5aff182SThomas Petazzoni err_cleanup_rxqs: 2503c5aff182SThomas Petazzoni mvneta_cleanup_rxqs(pp); 2504c5aff182SThomas Petazzoni return ret; 2505c5aff182SThomas Petazzoni } 2506c5aff182SThomas Petazzoni 2507c5aff182SThomas Petazzoni /* Stop the port, free port interrupt line */ 2508c5aff182SThomas Petazzoni static int mvneta_stop(struct net_device *dev) 2509c5aff182SThomas Petazzoni { 2510c5aff182SThomas Petazzoni struct mvneta_port *pp = netdev_priv(dev); 2511c5aff182SThomas Petazzoni 2512c5aff182SThomas Petazzoni mvneta_stop_dev(pp); 2513c5aff182SThomas Petazzoni mvneta_mdio_remove(pp); 2514c5aff182SThomas Petazzoni free_irq(dev->irq, pp); 2515c5aff182SThomas Petazzoni mvneta_cleanup_rxqs(pp); 2516c5aff182SThomas Petazzoni mvneta_cleanup_txqs(pp); 2517c5aff182SThomas Petazzoni 2518c5aff182SThomas Petazzoni return 0; 2519c5aff182SThomas Petazzoni } 2520c5aff182SThomas Petazzoni 252115f59456SThomas Petazzoni static int mvneta_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) 252215f59456SThomas Petazzoni { 252315f59456SThomas Petazzoni struct mvneta_port *pp = netdev_priv(dev); 252415f59456SThomas Petazzoni int ret; 252515f59456SThomas Petazzoni 252615f59456SThomas Petazzoni if (!pp->phy_dev) 252715f59456SThomas Petazzoni return -ENOTSUPP; 252815f59456SThomas Petazzoni 252915f59456SThomas Petazzoni ret = phy_mii_ioctl(pp->phy_dev, ifr, cmd); 253015f59456SThomas Petazzoni if (!ret) 253115f59456SThomas Petazzoni mvneta_adjust_link(dev); 253215f59456SThomas Petazzoni 253315f59456SThomas Petazzoni return ret; 253415f59456SThomas Petazzoni } 253515f59456SThomas Petazzoni 2536c5aff182SThomas Petazzoni /* Ethtool methods */ 2537c5aff182SThomas Petazzoni 2538c5aff182SThomas Petazzoni /* Get settings (phy address, speed) for ethtools */ 2539c5aff182SThomas Petazzoni int mvneta_ethtool_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) 2540c5aff182SThomas Petazzoni { 2541c5aff182SThomas Petazzoni struct mvneta_port *pp = netdev_priv(dev); 2542c5aff182SThomas Petazzoni 2543c5aff182SThomas Petazzoni if (!pp->phy_dev) 2544c5aff182SThomas Petazzoni return -ENODEV; 2545c5aff182SThomas Petazzoni 2546c5aff182SThomas Petazzoni return phy_ethtool_gset(pp->phy_dev, cmd); 2547c5aff182SThomas Petazzoni } 2548c5aff182SThomas Petazzoni 2549c5aff182SThomas Petazzoni /* Set settings (phy address, speed) for ethtools */ 2550c5aff182SThomas Petazzoni int mvneta_ethtool_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) 2551c5aff182SThomas Petazzoni { 2552c5aff182SThomas Petazzoni struct mvneta_port *pp = netdev_priv(dev); 2553c5aff182SThomas Petazzoni 2554c5aff182SThomas Petazzoni if (!pp->phy_dev) 2555c5aff182SThomas Petazzoni return -ENODEV; 2556c5aff182SThomas Petazzoni 2557c5aff182SThomas Petazzoni return phy_ethtool_sset(pp->phy_dev, cmd); 2558c5aff182SThomas Petazzoni } 2559c5aff182SThomas Petazzoni 2560c5aff182SThomas Petazzoni /* Set interrupt coalescing for ethtools */ 2561c5aff182SThomas Petazzoni static int mvneta_ethtool_set_coalesce(struct net_device *dev, 2562c5aff182SThomas Petazzoni struct ethtool_coalesce *c) 2563c5aff182SThomas Petazzoni { 2564c5aff182SThomas Petazzoni struct mvneta_port *pp = netdev_priv(dev); 2565c5aff182SThomas Petazzoni int queue; 2566c5aff182SThomas Petazzoni 2567c5aff182SThomas Petazzoni for (queue = 0; queue < rxq_number; queue++) { 2568c5aff182SThomas Petazzoni struct mvneta_rx_queue *rxq = &pp->rxqs[queue]; 2569c5aff182SThomas Petazzoni rxq->time_coal = c->rx_coalesce_usecs; 2570c5aff182SThomas Petazzoni rxq->pkts_coal = c->rx_max_coalesced_frames; 2571c5aff182SThomas Petazzoni mvneta_rx_pkts_coal_set(pp, rxq, rxq->pkts_coal); 2572c5aff182SThomas Petazzoni mvneta_rx_time_coal_set(pp, rxq, rxq->time_coal); 2573c5aff182SThomas Petazzoni } 2574c5aff182SThomas Petazzoni 2575c5aff182SThomas Petazzoni for (queue = 0; queue < txq_number; queue++) { 2576c5aff182SThomas Petazzoni struct mvneta_tx_queue *txq = &pp->txqs[queue]; 2577c5aff182SThomas Petazzoni txq->done_pkts_coal = c->tx_max_coalesced_frames; 2578c5aff182SThomas Petazzoni mvneta_tx_done_pkts_coal_set(pp, txq, txq->done_pkts_coal); 2579c5aff182SThomas Petazzoni } 2580c5aff182SThomas Petazzoni 2581c5aff182SThomas Petazzoni return 0; 2582c5aff182SThomas Petazzoni } 2583c5aff182SThomas Petazzoni 2584c5aff182SThomas Petazzoni /* get coalescing for ethtools */ 2585c5aff182SThomas Petazzoni static int mvneta_ethtool_get_coalesce(struct net_device *dev, 2586c5aff182SThomas Petazzoni struct ethtool_coalesce *c) 2587c5aff182SThomas Petazzoni { 2588c5aff182SThomas Petazzoni struct mvneta_port *pp = netdev_priv(dev); 2589c5aff182SThomas Petazzoni 2590c5aff182SThomas Petazzoni c->rx_coalesce_usecs = pp->rxqs[0].time_coal; 2591c5aff182SThomas Petazzoni c->rx_max_coalesced_frames = pp->rxqs[0].pkts_coal; 2592c5aff182SThomas Petazzoni 2593c5aff182SThomas Petazzoni c->tx_max_coalesced_frames = pp->txqs[0].done_pkts_coal; 2594c5aff182SThomas Petazzoni return 0; 2595c5aff182SThomas Petazzoni } 2596c5aff182SThomas Petazzoni 2597c5aff182SThomas Petazzoni 2598c5aff182SThomas Petazzoni static void mvneta_ethtool_get_drvinfo(struct net_device *dev, 2599c5aff182SThomas Petazzoni struct ethtool_drvinfo *drvinfo) 2600c5aff182SThomas Petazzoni { 2601c5aff182SThomas Petazzoni strlcpy(drvinfo->driver, MVNETA_DRIVER_NAME, 2602c5aff182SThomas Petazzoni sizeof(drvinfo->driver)); 2603c5aff182SThomas Petazzoni strlcpy(drvinfo->version, MVNETA_DRIVER_VERSION, 2604c5aff182SThomas Petazzoni sizeof(drvinfo->version)); 2605c5aff182SThomas Petazzoni strlcpy(drvinfo->bus_info, dev_name(&dev->dev), 2606c5aff182SThomas Petazzoni sizeof(drvinfo->bus_info)); 2607c5aff182SThomas Petazzoni } 2608c5aff182SThomas Petazzoni 2609c5aff182SThomas Petazzoni 2610c5aff182SThomas Petazzoni static void mvneta_ethtool_get_ringparam(struct net_device *netdev, 2611c5aff182SThomas Petazzoni struct ethtool_ringparam *ring) 2612c5aff182SThomas Petazzoni { 2613c5aff182SThomas Petazzoni struct mvneta_port *pp = netdev_priv(netdev); 2614c5aff182SThomas Petazzoni 2615c5aff182SThomas Petazzoni ring->rx_max_pending = MVNETA_MAX_RXD; 2616c5aff182SThomas Petazzoni ring->tx_max_pending = MVNETA_MAX_TXD; 2617c5aff182SThomas Petazzoni ring->rx_pending = pp->rx_ring_size; 2618c5aff182SThomas Petazzoni ring->tx_pending = pp->tx_ring_size; 2619c5aff182SThomas Petazzoni } 2620c5aff182SThomas Petazzoni 2621c5aff182SThomas Petazzoni static int mvneta_ethtool_set_ringparam(struct net_device *dev, 2622c5aff182SThomas Petazzoni struct ethtool_ringparam *ring) 2623c5aff182SThomas Petazzoni { 2624c5aff182SThomas Petazzoni struct mvneta_port *pp = netdev_priv(dev); 2625c5aff182SThomas Petazzoni 2626c5aff182SThomas Petazzoni if ((ring->rx_pending == 0) || (ring->tx_pending == 0)) 2627c5aff182SThomas Petazzoni return -EINVAL; 2628c5aff182SThomas Petazzoni pp->rx_ring_size = ring->rx_pending < MVNETA_MAX_RXD ? 2629c5aff182SThomas Petazzoni ring->rx_pending : MVNETA_MAX_RXD; 2630c5aff182SThomas Petazzoni pp->tx_ring_size = ring->tx_pending < MVNETA_MAX_TXD ? 2631c5aff182SThomas Petazzoni ring->tx_pending : MVNETA_MAX_TXD; 2632c5aff182SThomas Petazzoni 2633c5aff182SThomas Petazzoni if (netif_running(dev)) { 2634c5aff182SThomas Petazzoni mvneta_stop(dev); 2635c5aff182SThomas Petazzoni if (mvneta_open(dev)) { 2636c5aff182SThomas Petazzoni netdev_err(dev, 2637c5aff182SThomas Petazzoni "error on opening device after ring param change\n"); 2638c5aff182SThomas Petazzoni return -ENOMEM; 2639c5aff182SThomas Petazzoni } 2640c5aff182SThomas Petazzoni } 2641c5aff182SThomas Petazzoni 2642c5aff182SThomas Petazzoni return 0; 2643c5aff182SThomas Petazzoni } 2644c5aff182SThomas Petazzoni 2645c5aff182SThomas Petazzoni static const struct net_device_ops mvneta_netdev_ops = { 2646c5aff182SThomas Petazzoni .ndo_open = mvneta_open, 2647c5aff182SThomas Petazzoni .ndo_stop = mvneta_stop, 2648c5aff182SThomas Petazzoni .ndo_start_xmit = mvneta_tx, 2649c5aff182SThomas Petazzoni .ndo_set_rx_mode = mvneta_set_rx_mode, 2650c5aff182SThomas Petazzoni .ndo_set_mac_address = mvneta_set_mac_addr, 2651c5aff182SThomas Petazzoni .ndo_change_mtu = mvneta_change_mtu, 2652c5aff182SThomas Petazzoni .ndo_get_stats64 = mvneta_get_stats64, 265315f59456SThomas Petazzoni .ndo_do_ioctl = mvneta_ioctl, 2654c5aff182SThomas Petazzoni }; 2655c5aff182SThomas Petazzoni 2656c5aff182SThomas Petazzoni const struct ethtool_ops mvneta_eth_tool_ops = { 2657c5aff182SThomas Petazzoni .get_link = ethtool_op_get_link, 2658c5aff182SThomas Petazzoni .get_settings = mvneta_ethtool_get_settings, 2659c5aff182SThomas Petazzoni .set_settings = mvneta_ethtool_set_settings, 2660c5aff182SThomas Petazzoni .set_coalesce = mvneta_ethtool_set_coalesce, 2661c5aff182SThomas Petazzoni .get_coalesce = mvneta_ethtool_get_coalesce, 2662c5aff182SThomas Petazzoni .get_drvinfo = mvneta_ethtool_get_drvinfo, 2663c5aff182SThomas Petazzoni .get_ringparam = mvneta_ethtool_get_ringparam, 2664c5aff182SThomas Petazzoni .set_ringparam = mvneta_ethtool_set_ringparam, 2665c5aff182SThomas Petazzoni }; 2666c5aff182SThomas Petazzoni 2667c5aff182SThomas Petazzoni /* Initialize hw */ 266803ce758eSGreg KH static int mvneta_init(struct mvneta_port *pp, int phy_addr) 2669c5aff182SThomas Petazzoni { 2670c5aff182SThomas Petazzoni int queue; 2671c5aff182SThomas Petazzoni 2672c5aff182SThomas Petazzoni /* Disable port */ 2673c5aff182SThomas Petazzoni mvneta_port_disable(pp); 2674c5aff182SThomas Petazzoni 2675c5aff182SThomas Petazzoni /* Set port default values */ 2676c5aff182SThomas Petazzoni mvneta_defaults_set(pp); 2677c5aff182SThomas Petazzoni 2678c5aff182SThomas Petazzoni pp->txqs = kzalloc(txq_number * sizeof(struct mvneta_tx_queue), 2679c5aff182SThomas Petazzoni GFP_KERNEL); 2680c5aff182SThomas Petazzoni if (!pp->txqs) 2681c5aff182SThomas Petazzoni return -ENOMEM; 2682c5aff182SThomas Petazzoni 2683c5aff182SThomas Petazzoni /* Initialize TX descriptor rings */ 2684c5aff182SThomas Petazzoni for (queue = 0; queue < txq_number; queue++) { 2685c5aff182SThomas Petazzoni struct mvneta_tx_queue *txq = &pp->txqs[queue]; 2686c5aff182SThomas Petazzoni txq->id = queue; 2687c5aff182SThomas Petazzoni txq->size = pp->tx_ring_size; 2688c5aff182SThomas Petazzoni txq->done_pkts_coal = MVNETA_TXDONE_COAL_PKTS; 2689c5aff182SThomas Petazzoni } 2690c5aff182SThomas Petazzoni 2691c5aff182SThomas Petazzoni pp->rxqs = kzalloc(rxq_number * sizeof(struct mvneta_rx_queue), 2692c5aff182SThomas Petazzoni GFP_KERNEL); 2693c5aff182SThomas Petazzoni if (!pp->rxqs) { 2694c5aff182SThomas Petazzoni kfree(pp->txqs); 2695c5aff182SThomas Petazzoni return -ENOMEM; 2696c5aff182SThomas Petazzoni } 2697c5aff182SThomas Petazzoni 2698c5aff182SThomas Petazzoni /* Create Rx descriptor rings */ 2699c5aff182SThomas Petazzoni for (queue = 0; queue < rxq_number; queue++) { 2700c5aff182SThomas Petazzoni struct mvneta_rx_queue *rxq = &pp->rxqs[queue]; 2701c5aff182SThomas Petazzoni rxq->id = queue; 2702c5aff182SThomas Petazzoni rxq->size = pp->rx_ring_size; 2703c5aff182SThomas Petazzoni rxq->pkts_coal = MVNETA_RX_COAL_PKTS; 2704c5aff182SThomas Petazzoni rxq->time_coal = MVNETA_RX_COAL_USEC; 2705c5aff182SThomas Petazzoni } 2706c5aff182SThomas Petazzoni 2707c5aff182SThomas Petazzoni return 0; 2708c5aff182SThomas Petazzoni } 2709c5aff182SThomas Petazzoni 271070eeaf98SThomas Petazzoni static void mvneta_deinit(struct mvneta_port *pp) 2711c5aff182SThomas Petazzoni { 2712c5aff182SThomas Petazzoni kfree(pp->txqs); 2713c5aff182SThomas Petazzoni kfree(pp->rxqs); 2714c5aff182SThomas Petazzoni } 2715c5aff182SThomas Petazzoni 2716c5aff182SThomas Petazzoni /* platform glue : initialize decoding windows */ 271703ce758eSGreg KH static void mvneta_conf_mbus_windows(struct mvneta_port *pp, 2718c5aff182SThomas Petazzoni const struct mbus_dram_target_info *dram) 2719c5aff182SThomas Petazzoni { 2720c5aff182SThomas Petazzoni u32 win_enable; 2721c5aff182SThomas Petazzoni u32 win_protect; 2722c5aff182SThomas Petazzoni int i; 2723c5aff182SThomas Petazzoni 2724c5aff182SThomas Petazzoni for (i = 0; i < 6; i++) { 2725c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_WIN_BASE(i), 0); 2726c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_WIN_SIZE(i), 0); 2727c5aff182SThomas Petazzoni 2728c5aff182SThomas Petazzoni if (i < 4) 2729c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_WIN_REMAP(i), 0); 2730c5aff182SThomas Petazzoni } 2731c5aff182SThomas Petazzoni 2732c5aff182SThomas Petazzoni win_enable = 0x3f; 2733c5aff182SThomas Petazzoni win_protect = 0; 2734c5aff182SThomas Petazzoni 2735c5aff182SThomas Petazzoni for (i = 0; i < dram->num_cs; i++) { 2736c5aff182SThomas Petazzoni const struct mbus_dram_window *cs = dram->cs + i; 2737c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_WIN_BASE(i), (cs->base & 0xffff0000) | 2738c5aff182SThomas Petazzoni (cs->mbus_attr << 8) | dram->mbus_dram_target_id); 2739c5aff182SThomas Petazzoni 2740c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_WIN_SIZE(i), 2741c5aff182SThomas Petazzoni (cs->size - 1) & 0xffff0000); 2742c5aff182SThomas Petazzoni 2743c5aff182SThomas Petazzoni win_enable &= ~(1 << i); 2744c5aff182SThomas Petazzoni win_protect |= 3 << (2 * i); 2745c5aff182SThomas Petazzoni } 2746c5aff182SThomas Petazzoni 2747c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_BASE_ADDR_ENABLE, win_enable); 2748c5aff182SThomas Petazzoni } 2749c5aff182SThomas Petazzoni 2750c5aff182SThomas Petazzoni /* Power up the port */ 275103ce758eSGreg KH static void mvneta_port_power_up(struct mvneta_port *pp, int phy_mode) 2752c5aff182SThomas Petazzoni { 2753c5aff182SThomas Petazzoni u32 val; 2754c5aff182SThomas Petazzoni 2755c5aff182SThomas Petazzoni /* MAC Cause register should be cleared */ 2756c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_UNIT_INTR_CAUSE, 0); 2757c5aff182SThomas Petazzoni 2758c5aff182SThomas Petazzoni if (phy_mode == PHY_INTERFACE_MODE_SGMII) 2759c5aff182SThomas Petazzoni mvneta_port_sgmii_config(pp); 2760c5aff182SThomas Petazzoni 2761c5aff182SThomas Petazzoni mvneta_gmac_rgmii_set(pp, 1); 2762c5aff182SThomas Petazzoni 2763c5aff182SThomas Petazzoni /* Cancel Port Reset */ 2764c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_GMAC_CTRL_2); 2765c5aff182SThomas Petazzoni val &= ~MVNETA_GMAC2_PORT_RESET; 2766c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_GMAC_CTRL_2, val); 2767c5aff182SThomas Petazzoni 2768c5aff182SThomas Petazzoni while ((mvreg_read(pp, MVNETA_GMAC_CTRL_2) & 2769c5aff182SThomas Petazzoni MVNETA_GMAC2_PORT_RESET) != 0) 2770c5aff182SThomas Petazzoni continue; 2771c5aff182SThomas Petazzoni } 2772c5aff182SThomas Petazzoni 2773c5aff182SThomas Petazzoni /* Device initialization routine */ 277403ce758eSGreg KH static int mvneta_probe(struct platform_device *pdev) 2775c5aff182SThomas Petazzoni { 2776c5aff182SThomas Petazzoni const struct mbus_dram_target_info *dram_target_info; 2777c5aff182SThomas Petazzoni struct device_node *dn = pdev->dev.of_node; 2778c5aff182SThomas Petazzoni struct device_node *phy_node; 2779189dd626SThomas Petazzoni u32 phy_addr; 2780c5aff182SThomas Petazzoni struct mvneta_port *pp; 2781c5aff182SThomas Petazzoni struct net_device *dev; 27828cc3e439SThomas Petazzoni const char *dt_mac_addr; 27838cc3e439SThomas Petazzoni char hw_mac_addr[ETH_ALEN]; 27848cc3e439SThomas Petazzoni const char *mac_from; 2785c5aff182SThomas Petazzoni int phy_mode; 2786c5aff182SThomas Petazzoni int err; 2787c5aff182SThomas Petazzoni 27886a20c175SThomas Petazzoni /* Our multiqueue support is not complete, so for now, only 2789c5aff182SThomas Petazzoni * allow the usage of the first RX queue 2790c5aff182SThomas Petazzoni */ 2791c5aff182SThomas Petazzoni if (rxq_def != 0) { 2792c5aff182SThomas Petazzoni dev_err(&pdev->dev, "Invalid rxq_def argument: %d\n", rxq_def); 2793c5aff182SThomas Petazzoni return -EINVAL; 2794c5aff182SThomas Petazzoni } 2795c5aff182SThomas Petazzoni 2796ee40a116SWilly Tarreau dev = alloc_etherdev_mqs(sizeof(struct mvneta_port), txq_number, rxq_number); 2797c5aff182SThomas Petazzoni if (!dev) 2798c5aff182SThomas Petazzoni return -ENOMEM; 2799c5aff182SThomas Petazzoni 2800c5aff182SThomas Petazzoni dev->irq = irq_of_parse_and_map(dn, 0); 2801c5aff182SThomas Petazzoni if (dev->irq == 0) { 2802c5aff182SThomas Petazzoni err = -EINVAL; 2803c5aff182SThomas Petazzoni goto err_free_netdev; 2804c5aff182SThomas Petazzoni } 2805c5aff182SThomas Petazzoni 2806c5aff182SThomas Petazzoni phy_node = of_parse_phandle(dn, "phy", 0); 2807c5aff182SThomas Petazzoni if (!phy_node) { 2808c5aff182SThomas Petazzoni dev_err(&pdev->dev, "no associated PHY\n"); 2809c5aff182SThomas Petazzoni err = -ENODEV; 2810c5aff182SThomas Petazzoni goto err_free_irq; 2811c5aff182SThomas Petazzoni } 2812c5aff182SThomas Petazzoni 2813c5aff182SThomas Petazzoni phy_mode = of_get_phy_mode(dn); 2814c5aff182SThomas Petazzoni if (phy_mode < 0) { 2815c5aff182SThomas Petazzoni dev_err(&pdev->dev, "incorrect phy-mode\n"); 2816c5aff182SThomas Petazzoni err = -EINVAL; 2817c5aff182SThomas Petazzoni goto err_free_irq; 2818c5aff182SThomas Petazzoni } 2819c5aff182SThomas Petazzoni 2820c5aff182SThomas Petazzoni dev->tx_queue_len = MVNETA_MAX_TXD; 2821c5aff182SThomas Petazzoni dev->watchdog_timeo = 5 * HZ; 2822c5aff182SThomas Petazzoni dev->netdev_ops = &mvneta_netdev_ops; 2823c5aff182SThomas Petazzoni 2824c5aff182SThomas Petazzoni SET_ETHTOOL_OPS(dev, &mvneta_eth_tool_ops); 2825c5aff182SThomas Petazzoni 2826c5aff182SThomas Petazzoni pp = netdev_priv(dev); 2827c5aff182SThomas Petazzoni 2828c5aff182SThomas Petazzoni pp->weight = MVNETA_RX_POLL_WEIGHT; 2829c5aff182SThomas Petazzoni pp->phy_node = phy_node; 2830c5aff182SThomas Petazzoni pp->phy_interface = phy_mode; 2831c5aff182SThomas Petazzoni 2832189dd626SThomas Petazzoni pp->clk = devm_clk_get(&pdev->dev, NULL); 2833189dd626SThomas Petazzoni if (IS_ERR(pp->clk)) { 2834189dd626SThomas Petazzoni err = PTR_ERR(pp->clk); 28355445eaf3SArnaud Patard \(Rtp\) goto err_free_irq; 2836189dd626SThomas Petazzoni } 2837189dd626SThomas Petazzoni 2838189dd626SThomas Petazzoni clk_prepare_enable(pp->clk); 2839189dd626SThomas Petazzoni 28405445eaf3SArnaud Patard \(Rtp\) pp->base = of_iomap(dn, 0); 28415445eaf3SArnaud Patard \(Rtp\) if (pp->base == NULL) { 28425445eaf3SArnaud Patard \(Rtp\) err = -ENOMEM; 28435445eaf3SArnaud Patard \(Rtp\) goto err_clk; 28445445eaf3SArnaud Patard \(Rtp\) } 28455445eaf3SArnaud Patard \(Rtp\) 284674c41b04Swilly tarreau /* Alloc per-cpu stats */ 28471c213bd2SWANG Cong pp->stats = netdev_alloc_pcpu_stats(struct mvneta_pcpu_stats); 284874c41b04Swilly tarreau if (!pp->stats) { 284974c41b04Swilly tarreau err = -ENOMEM; 285074c41b04Swilly tarreau goto err_unmap; 285174c41b04Swilly tarreau } 285274c41b04Swilly tarreau 28538cc3e439SThomas Petazzoni dt_mac_addr = of_get_mac_address(dn); 28546c7a9a3cSLuka Perkov if (dt_mac_addr) { 28558cc3e439SThomas Petazzoni mac_from = "device tree"; 28568cc3e439SThomas Petazzoni memcpy(dev->dev_addr, dt_mac_addr, ETH_ALEN); 28578cc3e439SThomas Petazzoni } else { 28588cc3e439SThomas Petazzoni mvneta_get_mac_addr(pp, hw_mac_addr); 28598cc3e439SThomas Petazzoni if (is_valid_ether_addr(hw_mac_addr)) { 28608cc3e439SThomas Petazzoni mac_from = "hardware"; 28618cc3e439SThomas Petazzoni memcpy(dev->dev_addr, hw_mac_addr, ETH_ALEN); 28628cc3e439SThomas Petazzoni } else { 28638cc3e439SThomas Petazzoni mac_from = "random"; 28648cc3e439SThomas Petazzoni eth_hw_addr_random(dev); 28658cc3e439SThomas Petazzoni } 28668cc3e439SThomas Petazzoni } 28678cc3e439SThomas Petazzoni 2868c5aff182SThomas Petazzoni pp->tx_ring_size = MVNETA_MAX_TXD; 2869c5aff182SThomas Petazzoni pp->rx_ring_size = MVNETA_MAX_RXD; 2870c5aff182SThomas Petazzoni 2871c5aff182SThomas Petazzoni pp->dev = dev; 2872c5aff182SThomas Petazzoni SET_NETDEV_DEV(dev, &pdev->dev); 2873c5aff182SThomas Petazzoni 2874c5aff182SThomas Petazzoni err = mvneta_init(pp, phy_addr); 2875c5aff182SThomas Petazzoni if (err < 0) { 2876c5aff182SThomas Petazzoni dev_err(&pdev->dev, "can't init eth hal\n"); 287774c41b04Swilly tarreau goto err_free_stats; 2878c5aff182SThomas Petazzoni } 2879c5aff182SThomas Petazzoni mvneta_port_power_up(pp, phy_mode); 2880c5aff182SThomas Petazzoni 2881c5aff182SThomas Petazzoni dram_target_info = mv_mbus_dram_info(); 2882c5aff182SThomas Petazzoni if (dram_target_info) 2883c5aff182SThomas Petazzoni mvneta_conf_mbus_windows(pp, dram_target_info); 2884c5aff182SThomas Petazzoni 2885c5aff182SThomas Petazzoni netif_napi_add(dev, &pp->napi, mvneta_poll, pp->weight); 2886c5aff182SThomas Petazzoni 2887b50b72deSwilly tarreau dev->features = NETIF_F_SG | NETIF_F_IP_CSUM; 2888b50b72deSwilly tarreau dev->hw_features |= NETIF_F_SG | NETIF_F_IP_CSUM; 2889b50b72deSwilly tarreau dev->vlan_features |= NETIF_F_SG | NETIF_F_IP_CSUM; 2890b50b72deSwilly tarreau dev->priv_flags |= IFF_UNICAST_FLT; 2891b50b72deSwilly tarreau 2892c5aff182SThomas Petazzoni err = register_netdev(dev); 2893c5aff182SThomas Petazzoni if (err < 0) { 2894c5aff182SThomas Petazzoni dev_err(&pdev->dev, "failed to register\n"); 2895c5aff182SThomas Petazzoni goto err_deinit; 2896c5aff182SThomas Petazzoni } 2897c5aff182SThomas Petazzoni 28988cc3e439SThomas Petazzoni netdev_info(dev, "Using %s mac address %pM\n", mac_from, 28998cc3e439SThomas Petazzoni dev->dev_addr); 2900c5aff182SThomas Petazzoni 2901c5aff182SThomas Petazzoni platform_set_drvdata(pdev, pp->dev); 2902c5aff182SThomas Petazzoni 2903c5aff182SThomas Petazzoni return 0; 2904c5aff182SThomas Petazzoni 2905c5aff182SThomas Petazzoni err_deinit: 2906c5aff182SThomas Petazzoni mvneta_deinit(pp); 290774c41b04Swilly tarreau err_free_stats: 290874c41b04Swilly tarreau free_percpu(pp->stats); 2909c5aff182SThomas Petazzoni err_unmap: 2910c5aff182SThomas Petazzoni iounmap(pp->base); 29115445eaf3SArnaud Patard \(Rtp\) err_clk: 29125445eaf3SArnaud Patard \(Rtp\) clk_disable_unprepare(pp->clk); 2913c5aff182SThomas Petazzoni err_free_irq: 2914c5aff182SThomas Petazzoni irq_dispose_mapping(dev->irq); 2915c5aff182SThomas Petazzoni err_free_netdev: 2916c5aff182SThomas Petazzoni free_netdev(dev); 2917c5aff182SThomas Petazzoni return err; 2918c5aff182SThomas Petazzoni } 2919c5aff182SThomas Petazzoni 2920c5aff182SThomas Petazzoni /* Device removal routine */ 292103ce758eSGreg KH static int mvneta_remove(struct platform_device *pdev) 2922c5aff182SThomas Petazzoni { 2923c5aff182SThomas Petazzoni struct net_device *dev = platform_get_drvdata(pdev); 2924c5aff182SThomas Petazzoni struct mvneta_port *pp = netdev_priv(dev); 2925c5aff182SThomas Petazzoni 2926c5aff182SThomas Petazzoni unregister_netdev(dev); 2927c5aff182SThomas Petazzoni mvneta_deinit(pp); 2928189dd626SThomas Petazzoni clk_disable_unprepare(pp->clk); 292974c41b04Swilly tarreau free_percpu(pp->stats); 2930c5aff182SThomas Petazzoni iounmap(pp->base); 2931c5aff182SThomas Petazzoni irq_dispose_mapping(dev->irq); 2932c5aff182SThomas Petazzoni free_netdev(dev); 2933c5aff182SThomas Petazzoni 2934c5aff182SThomas Petazzoni return 0; 2935c5aff182SThomas Petazzoni } 2936c5aff182SThomas Petazzoni 2937c5aff182SThomas Petazzoni static const struct of_device_id mvneta_match[] = { 2938c5aff182SThomas Petazzoni { .compatible = "marvell,armada-370-neta" }, 2939c5aff182SThomas Petazzoni { } 2940c5aff182SThomas Petazzoni }; 2941c5aff182SThomas Petazzoni MODULE_DEVICE_TABLE(of, mvneta_match); 2942c5aff182SThomas Petazzoni 2943c5aff182SThomas Petazzoni static struct platform_driver mvneta_driver = { 2944c5aff182SThomas Petazzoni .probe = mvneta_probe, 294503ce758eSGreg KH .remove = mvneta_remove, 2946c5aff182SThomas Petazzoni .driver = { 2947c5aff182SThomas Petazzoni .name = MVNETA_DRIVER_NAME, 2948c5aff182SThomas Petazzoni .of_match_table = mvneta_match, 2949c5aff182SThomas Petazzoni }, 2950c5aff182SThomas Petazzoni }; 2951c5aff182SThomas Petazzoni 2952c5aff182SThomas Petazzoni module_platform_driver(mvneta_driver); 2953c5aff182SThomas Petazzoni 2954c5aff182SThomas Petazzoni MODULE_DESCRIPTION("Marvell NETA Ethernet Driver - www.marvell.com"); 2955c5aff182SThomas Petazzoni MODULE_AUTHOR("Rami Rosen <rosenr@marvell.com>, Thomas Petazzoni <thomas.petazzoni@free-electrons.com>"); 2956c5aff182SThomas Petazzoni MODULE_LICENSE("GPL"); 2957c5aff182SThomas Petazzoni 2958c5aff182SThomas Petazzoni module_param(rxq_number, int, S_IRUGO); 2959c5aff182SThomas Petazzoni module_param(txq_number, int, S_IRUGO); 2960c5aff182SThomas Petazzoni 2961c5aff182SThomas Petazzoni module_param(rxq_def, int, S_IRUGO); 2962f19fadfcSwilly tarreau module_param(rx_copybreak, int, S_IRUGO | S_IWUSR); 2963