1c5aff182SThomas Petazzoni /* 2c5aff182SThomas Petazzoni * Driver for Marvell NETA network card for Armada XP and Armada 370 SoCs. 3c5aff182SThomas Petazzoni * 4c5aff182SThomas Petazzoni * Copyright (C) 2012 Marvell 5c5aff182SThomas Petazzoni * 6c5aff182SThomas Petazzoni * Rami Rosen <rosenr@marvell.com> 7c5aff182SThomas Petazzoni * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> 8c5aff182SThomas Petazzoni * 9c5aff182SThomas Petazzoni * This file is licensed under the terms of the GNU General Public 10c5aff182SThomas Petazzoni * License version 2. This program is licensed "as is" without any 11c5aff182SThomas Petazzoni * warranty of any kind, whether express or implied. 12c5aff182SThomas Petazzoni */ 13c5aff182SThomas Petazzoni 140e03f563SJisheng Zhang #include <linux/clk.h> 150e03f563SJisheng Zhang #include <linux/cpu.h> 16c5aff182SThomas Petazzoni #include <linux/etherdevice.h> 170e03f563SJisheng Zhang #include <linux/if_vlan.h> 18c5aff182SThomas Petazzoni #include <linux/inetdevice.h> 190e03f563SJisheng Zhang #include <linux/interrupt.h> 200e03f563SJisheng Zhang #include <linux/io.h> 210e03f563SJisheng Zhang #include <linux/kernel.h> 22c5aff182SThomas Petazzoni #include <linux/mbus.h> 23c5aff182SThomas Petazzoni #include <linux/module.h> 240e03f563SJisheng Zhang #include <linux/netdevice.h> 25c5aff182SThomas Petazzoni #include <linux/of.h> 260e03f563SJisheng Zhang #include <linux/of_address.h> 27c5aff182SThomas Petazzoni #include <linux/of_irq.h> 28c5aff182SThomas Petazzoni #include <linux/of_mdio.h> 29c5aff182SThomas Petazzoni #include <linux/of_net.h> 30a10c1c81SRussell King #include <linux/phy/phy.h> 31c5aff182SThomas Petazzoni #include <linux/phy.h> 32503f9aa9SRussell King #include <linux/phylink.h> 330e03f563SJisheng Zhang #include <linux/platform_device.h> 340e03f563SJisheng Zhang #include <linux/skbuff.h> 35baa11ebcSGregory CLEMENT #include <net/hwbm.h> 36dc35a10fSMarcin Wojtas #include "mvneta_bm.h" 370e03f563SJisheng Zhang #include <net/ip.h> 380e03f563SJisheng Zhang #include <net/ipv6.h> 390e03f563SJisheng Zhang #include <net/tso.h> 40568a3fa2SLorenzo Bianconi #include <net/page_pool.h> 41c5aff182SThomas Petazzoni 42c5aff182SThomas Petazzoni /* Registers */ 43c5aff182SThomas Petazzoni #define MVNETA_RXQ_CONFIG_REG(q) (0x1400 + ((q) << 2)) 44e5bdf689SMarcin Wojtas #define MVNETA_RXQ_HW_BUF_ALLOC BIT(0) 45dc35a10fSMarcin Wojtas #define MVNETA_RXQ_SHORT_POOL_ID_SHIFT 4 46dc35a10fSMarcin Wojtas #define MVNETA_RXQ_SHORT_POOL_ID_MASK 0x30 47dc35a10fSMarcin Wojtas #define MVNETA_RXQ_LONG_POOL_ID_SHIFT 6 48dc35a10fSMarcin Wojtas #define MVNETA_RXQ_LONG_POOL_ID_MASK 0xc0 49c5aff182SThomas Petazzoni #define MVNETA_RXQ_PKT_OFFSET_ALL_MASK (0xf << 8) 50c5aff182SThomas Petazzoni #define MVNETA_RXQ_PKT_OFFSET_MASK(offs) ((offs) << 8) 51c5aff182SThomas Petazzoni #define MVNETA_RXQ_THRESHOLD_REG(q) (0x14c0 + ((q) << 2)) 52c5aff182SThomas Petazzoni #define MVNETA_RXQ_NON_OCCUPIED(v) ((v) << 16) 53c5aff182SThomas Petazzoni #define MVNETA_RXQ_BASE_ADDR_REG(q) (0x1480 + ((q) << 2)) 54c5aff182SThomas Petazzoni #define MVNETA_RXQ_SIZE_REG(q) (0x14a0 + ((q) << 2)) 55c5aff182SThomas Petazzoni #define MVNETA_RXQ_BUF_SIZE_SHIFT 19 56c5aff182SThomas Petazzoni #define MVNETA_RXQ_BUF_SIZE_MASK (0x1fff << 19) 57c5aff182SThomas Petazzoni #define MVNETA_RXQ_STATUS_REG(q) (0x14e0 + ((q) << 2)) 58c5aff182SThomas Petazzoni #define MVNETA_RXQ_OCCUPIED_ALL_MASK 0x3fff 59c5aff182SThomas Petazzoni #define MVNETA_RXQ_STATUS_UPDATE_REG(q) (0x1500 + ((q) << 2)) 60c5aff182SThomas Petazzoni #define MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT 16 61c5aff182SThomas Petazzoni #define MVNETA_RXQ_ADD_NON_OCCUPIED_MAX 255 62dc35a10fSMarcin Wojtas #define MVNETA_PORT_POOL_BUFFER_SZ_REG(pool) (0x1700 + ((pool) << 2)) 63dc35a10fSMarcin Wojtas #define MVNETA_PORT_POOL_BUFFER_SZ_SHIFT 3 64dc35a10fSMarcin Wojtas #define MVNETA_PORT_POOL_BUFFER_SZ_MASK 0xfff8 65c5aff182SThomas Petazzoni #define MVNETA_PORT_RX_RESET 0x1cc0 66c5aff182SThomas Petazzoni #define MVNETA_PORT_RX_DMA_RESET BIT(0) 67c5aff182SThomas Petazzoni #define MVNETA_PHY_ADDR 0x2000 68c5aff182SThomas Petazzoni #define MVNETA_PHY_ADDR_MASK 0x1f 69c5aff182SThomas Petazzoni #define MVNETA_MBUS_RETRY 0x2010 70c5aff182SThomas Petazzoni #define MVNETA_UNIT_INTR_CAUSE 0x2080 71c5aff182SThomas Petazzoni #define MVNETA_UNIT_CONTROL 0x20B0 72c5aff182SThomas Petazzoni #define MVNETA_PHY_POLLING_ENABLE BIT(1) 73c5aff182SThomas Petazzoni #define MVNETA_WIN_BASE(w) (0x2200 + ((w) << 3)) 74c5aff182SThomas Petazzoni #define MVNETA_WIN_SIZE(w) (0x2204 + ((w) << 3)) 75c5aff182SThomas Petazzoni #define MVNETA_WIN_REMAP(w) (0x2280 + ((w) << 2)) 76c5aff182SThomas Petazzoni #define MVNETA_BASE_ADDR_ENABLE 0x2290 77db6ba9a5SMarcin Wojtas #define MVNETA_ACCESS_PROTECT_ENABLE 0x2294 78c5aff182SThomas Petazzoni #define MVNETA_PORT_CONFIG 0x2400 79c5aff182SThomas Petazzoni #define MVNETA_UNI_PROMISC_MODE BIT(0) 80c5aff182SThomas Petazzoni #define MVNETA_DEF_RXQ(q) ((q) << 1) 81c5aff182SThomas Petazzoni #define MVNETA_DEF_RXQ_ARP(q) ((q) << 4) 82c5aff182SThomas Petazzoni #define MVNETA_TX_UNSET_ERR_SUM BIT(12) 83c5aff182SThomas Petazzoni #define MVNETA_DEF_RXQ_TCP(q) ((q) << 16) 84c5aff182SThomas Petazzoni #define MVNETA_DEF_RXQ_UDP(q) ((q) << 19) 85c5aff182SThomas Petazzoni #define MVNETA_DEF_RXQ_BPDU(q) ((q) << 22) 86c5aff182SThomas Petazzoni #define MVNETA_RX_CSUM_WITH_PSEUDO_HDR BIT(25) 87c5aff182SThomas Petazzoni #define MVNETA_PORT_CONFIG_DEFL_VALUE(q) (MVNETA_DEF_RXQ(q) | \ 88c5aff182SThomas Petazzoni MVNETA_DEF_RXQ_ARP(q) | \ 89c5aff182SThomas Petazzoni MVNETA_DEF_RXQ_TCP(q) | \ 90c5aff182SThomas Petazzoni MVNETA_DEF_RXQ_UDP(q) | \ 91c5aff182SThomas Petazzoni MVNETA_DEF_RXQ_BPDU(q) | \ 92c5aff182SThomas Petazzoni MVNETA_TX_UNSET_ERR_SUM | \ 93c5aff182SThomas Petazzoni MVNETA_RX_CSUM_WITH_PSEUDO_HDR) 94c5aff182SThomas Petazzoni #define MVNETA_PORT_CONFIG_EXTEND 0x2404 95c5aff182SThomas Petazzoni #define MVNETA_MAC_ADDR_LOW 0x2414 96c5aff182SThomas Petazzoni #define MVNETA_MAC_ADDR_HIGH 0x2418 97c5aff182SThomas Petazzoni #define MVNETA_SDMA_CONFIG 0x241c 98c5aff182SThomas Petazzoni #define MVNETA_SDMA_BRST_SIZE_16 4 99c5aff182SThomas Petazzoni #define MVNETA_RX_BRST_SZ_MASK(burst) ((burst) << 1) 100c5aff182SThomas Petazzoni #define MVNETA_RX_NO_DATA_SWAP BIT(4) 101c5aff182SThomas Petazzoni #define MVNETA_TX_NO_DATA_SWAP BIT(5) 1029ad8fef6SThomas Petazzoni #define MVNETA_DESC_SWAP BIT(6) 103c5aff182SThomas Petazzoni #define MVNETA_TX_BRST_SZ_MASK(burst) ((burst) << 22) 104c5aff182SThomas Petazzoni #define MVNETA_PORT_STATUS 0x2444 105c5aff182SThomas Petazzoni #define MVNETA_TX_IN_PRGRS BIT(1) 106c5aff182SThomas Petazzoni #define MVNETA_TX_FIFO_EMPTY BIT(8) 107c5aff182SThomas Petazzoni #define MVNETA_RX_MIN_FRAME_SIZE 0x247c 1083f1dd4bcSThomas Petazzoni #define MVNETA_SERDES_CFG 0x24A0 1095445eaf3SArnaud Patard \(Rtp\) #define MVNETA_SGMII_SERDES_PROTO 0x0cc7 1103f1dd4bcSThomas Petazzoni #define MVNETA_QSGMII_SERDES_PROTO 0x0667 111c5aff182SThomas Petazzoni #define MVNETA_TYPE_PRIO 0x24bc 112c5aff182SThomas Petazzoni #define MVNETA_FORCE_UNI BIT(21) 113c5aff182SThomas Petazzoni #define MVNETA_TXQ_CMD_1 0x24e4 114c5aff182SThomas Petazzoni #define MVNETA_TXQ_CMD 0x2448 115c5aff182SThomas Petazzoni #define MVNETA_TXQ_DISABLE_SHIFT 8 116c5aff182SThomas Petazzoni #define MVNETA_TXQ_ENABLE_MASK 0x000000ff 117e483911fSAndrew Lunn #define MVNETA_RX_DISCARD_FRAME_COUNT 0x2484 118e483911fSAndrew Lunn #define MVNETA_OVERRUN_FRAME_COUNT 0x2488 119898b2970SStas Sergeev #define MVNETA_GMAC_CLOCK_DIVIDER 0x24f4 120898b2970SStas Sergeev #define MVNETA_GMAC_1MS_CLOCK_ENABLE BIT(31) 121c5aff182SThomas Petazzoni #define MVNETA_ACC_MODE 0x2500 122dc35a10fSMarcin Wojtas #define MVNETA_BM_ADDRESS 0x2504 123c5aff182SThomas Petazzoni #define MVNETA_CPU_MAP(cpu) (0x2540 + ((cpu) << 2)) 124c5aff182SThomas Petazzoni #define MVNETA_CPU_RXQ_ACCESS_ALL_MASK 0x000000ff 125c5aff182SThomas Petazzoni #define MVNETA_CPU_TXQ_ACCESS_ALL_MASK 0x0000ff00 1262dcf75e2SGregory CLEMENT #define MVNETA_CPU_RXQ_ACCESS(rxq) BIT(rxq) 12750bf8cb6SGregory CLEMENT #define MVNETA_CPU_TXQ_ACCESS(txq) BIT(txq + 8) 128c5aff182SThomas Petazzoni #define MVNETA_RXQ_TIME_COAL_REG(q) (0x2580 + ((q) << 2)) 12940ba35e7Swilly tarreau 1302dcf75e2SGregory CLEMENT /* Exception Interrupt Port/Queue Cause register 1312dcf75e2SGregory CLEMENT * 1322dcf75e2SGregory CLEMENT * Their behavior depend of the mapping done using the PCPX2Q 1332dcf75e2SGregory CLEMENT * registers. For a given CPU if the bit associated to a queue is not 1342dcf75e2SGregory CLEMENT * set, then for the register a read from this CPU will always return 1352dcf75e2SGregory CLEMENT * 0 and a write won't do anything 1362dcf75e2SGregory CLEMENT */ 13740ba35e7Swilly tarreau 138c5aff182SThomas Petazzoni #define MVNETA_INTR_NEW_CAUSE 0x25a0 139c5aff182SThomas Petazzoni #define MVNETA_INTR_NEW_MASK 0x25a4 14040ba35e7Swilly tarreau 14140ba35e7Swilly tarreau /* bits 0..7 = TXQ SENT, one bit per queue. 14240ba35e7Swilly tarreau * bits 8..15 = RXQ OCCUP, one bit per queue. 14340ba35e7Swilly tarreau * bits 16..23 = RXQ FREE, one bit per queue. 14440ba35e7Swilly tarreau * bit 29 = OLD_REG_SUM, see old reg ? 14540ba35e7Swilly tarreau * bit 30 = TX_ERR_SUM, one bit for 4 ports 14640ba35e7Swilly tarreau * bit 31 = MISC_SUM, one bit for 4 ports 14740ba35e7Swilly tarreau */ 14840ba35e7Swilly tarreau #define MVNETA_TX_INTR_MASK(nr_txqs) (((1 << nr_txqs) - 1) << 0) 14940ba35e7Swilly tarreau #define MVNETA_TX_INTR_MASK_ALL (0xff << 0) 15040ba35e7Swilly tarreau #define MVNETA_RX_INTR_MASK(nr_rxqs) (((1 << nr_rxqs) - 1) << 8) 15140ba35e7Swilly tarreau #define MVNETA_RX_INTR_MASK_ALL (0xff << 8) 152898b2970SStas Sergeev #define MVNETA_MISCINTR_INTR_MASK BIT(31) 15340ba35e7Swilly tarreau 154c5aff182SThomas Petazzoni #define MVNETA_INTR_OLD_CAUSE 0x25a8 155c5aff182SThomas Petazzoni #define MVNETA_INTR_OLD_MASK 0x25ac 15640ba35e7Swilly tarreau 15740ba35e7Swilly tarreau /* Data Path Port/Queue Cause Register */ 158c5aff182SThomas Petazzoni #define MVNETA_INTR_MISC_CAUSE 0x25b0 159c5aff182SThomas Petazzoni #define MVNETA_INTR_MISC_MASK 0x25b4 16040ba35e7Swilly tarreau 16140ba35e7Swilly tarreau #define MVNETA_CAUSE_PHY_STATUS_CHANGE BIT(0) 16240ba35e7Swilly tarreau #define MVNETA_CAUSE_LINK_CHANGE BIT(1) 16340ba35e7Swilly tarreau #define MVNETA_CAUSE_PTP BIT(4) 16440ba35e7Swilly tarreau 16540ba35e7Swilly tarreau #define MVNETA_CAUSE_INTERNAL_ADDR_ERR BIT(7) 16640ba35e7Swilly tarreau #define MVNETA_CAUSE_RX_OVERRUN BIT(8) 16740ba35e7Swilly tarreau #define MVNETA_CAUSE_RX_CRC_ERROR BIT(9) 16840ba35e7Swilly tarreau #define MVNETA_CAUSE_RX_LARGE_PKT BIT(10) 16940ba35e7Swilly tarreau #define MVNETA_CAUSE_TX_UNDERUN BIT(11) 17040ba35e7Swilly tarreau #define MVNETA_CAUSE_PRBS_ERR BIT(12) 17140ba35e7Swilly tarreau #define MVNETA_CAUSE_PSC_SYNC_CHANGE BIT(13) 17240ba35e7Swilly tarreau #define MVNETA_CAUSE_SERDES_SYNC_ERR BIT(14) 17340ba35e7Swilly tarreau 17440ba35e7Swilly tarreau #define MVNETA_CAUSE_BMU_ALLOC_ERR_SHIFT 16 17540ba35e7Swilly tarreau #define MVNETA_CAUSE_BMU_ALLOC_ERR_ALL_MASK (0xF << MVNETA_CAUSE_BMU_ALLOC_ERR_SHIFT) 17640ba35e7Swilly tarreau #define MVNETA_CAUSE_BMU_ALLOC_ERR_MASK(pool) (1 << (MVNETA_CAUSE_BMU_ALLOC_ERR_SHIFT + (pool))) 17740ba35e7Swilly tarreau 17840ba35e7Swilly tarreau #define MVNETA_CAUSE_TXQ_ERROR_SHIFT 24 17940ba35e7Swilly tarreau #define MVNETA_CAUSE_TXQ_ERROR_ALL_MASK (0xFF << MVNETA_CAUSE_TXQ_ERROR_SHIFT) 18040ba35e7Swilly tarreau #define MVNETA_CAUSE_TXQ_ERROR_MASK(q) (1 << (MVNETA_CAUSE_TXQ_ERROR_SHIFT + (q))) 18140ba35e7Swilly tarreau 182c5aff182SThomas Petazzoni #define MVNETA_INTR_ENABLE 0x25b8 183c5aff182SThomas Petazzoni #define MVNETA_TXQ_INTR_ENABLE_ALL_MASK 0x0000ff00 184dc1aadf6SMarcin Wojtas #define MVNETA_RXQ_INTR_ENABLE_ALL_MASK 0x000000ff 18540ba35e7Swilly tarreau 186c5aff182SThomas Petazzoni #define MVNETA_RXQ_CMD 0x2680 187c5aff182SThomas Petazzoni #define MVNETA_RXQ_DISABLE_SHIFT 8 188c5aff182SThomas Petazzoni #define MVNETA_RXQ_ENABLE_MASK 0x000000ff 189c5aff182SThomas Petazzoni #define MVETH_TXQ_TOKEN_COUNT_REG(q) (0x2700 + ((q) << 4)) 190c5aff182SThomas Petazzoni #define MVETH_TXQ_TOKEN_CFG_REG(q) (0x2704 + ((q) << 4)) 191c5aff182SThomas Petazzoni #define MVNETA_GMAC_CTRL_0 0x2c00 192c5aff182SThomas Petazzoni #define MVNETA_GMAC_MAX_RX_SIZE_SHIFT 2 193c5aff182SThomas Petazzoni #define MVNETA_GMAC_MAX_RX_SIZE_MASK 0x7ffc 19422f4bf8aSRussell King #define MVNETA_GMAC0_PORT_1000BASE_X BIT(1) 195c5aff182SThomas Petazzoni #define MVNETA_GMAC0_PORT_ENABLE BIT(0) 196c5aff182SThomas Petazzoni #define MVNETA_GMAC_CTRL_2 0x2c08 197898b2970SStas Sergeev #define MVNETA_GMAC2_INBAND_AN_ENABLE BIT(0) 198a79121d3SThomas Petazzoni #define MVNETA_GMAC2_PCS_ENABLE BIT(3) 199c5aff182SThomas Petazzoni #define MVNETA_GMAC2_PORT_RGMII BIT(4) 200c5aff182SThomas Petazzoni #define MVNETA_GMAC2_PORT_RESET BIT(6) 201c5aff182SThomas Petazzoni #define MVNETA_GMAC_STATUS 0x2c10 202c5aff182SThomas Petazzoni #define MVNETA_GMAC_LINK_UP BIT(0) 203c5aff182SThomas Petazzoni #define MVNETA_GMAC_SPEED_1000 BIT(1) 204c5aff182SThomas Petazzoni #define MVNETA_GMAC_SPEED_100 BIT(2) 205c5aff182SThomas Petazzoni #define MVNETA_GMAC_FULL_DUPLEX BIT(3) 206c5aff182SThomas Petazzoni #define MVNETA_GMAC_RX_FLOW_CTRL_ENABLE BIT(4) 207c5aff182SThomas Petazzoni #define MVNETA_GMAC_TX_FLOW_CTRL_ENABLE BIT(5) 208c5aff182SThomas Petazzoni #define MVNETA_GMAC_RX_FLOW_CTRL_ACTIVE BIT(6) 209c5aff182SThomas Petazzoni #define MVNETA_GMAC_TX_FLOW_CTRL_ACTIVE BIT(7) 210503f9aa9SRussell King #define MVNETA_GMAC_AN_COMPLETE BIT(11) 211503f9aa9SRussell King #define MVNETA_GMAC_SYNC_OK BIT(14) 212c5aff182SThomas Petazzoni #define MVNETA_GMAC_AUTONEG_CONFIG 0x2c0c 213c5aff182SThomas Petazzoni #define MVNETA_GMAC_FORCE_LINK_DOWN BIT(0) 214c5aff182SThomas Petazzoni #define MVNETA_GMAC_FORCE_LINK_PASS BIT(1) 215898b2970SStas Sergeev #define MVNETA_GMAC_INBAND_AN_ENABLE BIT(2) 21622f4bf8aSRussell King #define MVNETA_GMAC_AN_BYPASS_ENABLE BIT(3) 21722f4bf8aSRussell King #define MVNETA_GMAC_INBAND_RESTART_AN BIT(4) 218c5aff182SThomas Petazzoni #define MVNETA_GMAC_CONFIG_MII_SPEED BIT(5) 219c5aff182SThomas Petazzoni #define MVNETA_GMAC_CONFIG_GMII_SPEED BIT(6) 22071408602SThomas Petazzoni #define MVNETA_GMAC_AN_SPEED_EN BIT(7) 22122f4bf8aSRussell King #define MVNETA_GMAC_CONFIG_FLOW_CTRL BIT(8) 22222f4bf8aSRussell King #define MVNETA_GMAC_ADVERT_SYM_FLOW_CTRL BIT(9) 223898b2970SStas Sergeev #define MVNETA_GMAC_AN_FLOW_CTRL_EN BIT(11) 224c5aff182SThomas Petazzoni #define MVNETA_GMAC_CONFIG_FULL_DUPLEX BIT(12) 22571408602SThomas Petazzoni #define MVNETA_GMAC_AN_DUPLEX_EN BIT(13) 226da58a931SMaxime Chevallier #define MVNETA_GMAC_CTRL_4 0x2c90 227da58a931SMaxime Chevallier #define MVNETA_GMAC4_SHORT_PREAMBLE_ENABLE BIT(1) 228e483911fSAndrew Lunn #define MVNETA_MIB_COUNTERS_BASE 0x3000 229c5aff182SThomas Petazzoni #define MVNETA_MIB_LATE_COLLISION 0x7c 230c5aff182SThomas Petazzoni #define MVNETA_DA_FILT_SPEC_MCAST 0x3400 231c5aff182SThomas Petazzoni #define MVNETA_DA_FILT_OTH_MCAST 0x3500 232c5aff182SThomas Petazzoni #define MVNETA_DA_FILT_UCAST_BASE 0x3600 233c5aff182SThomas Petazzoni #define MVNETA_TXQ_BASE_ADDR_REG(q) (0x3c00 + ((q) << 2)) 234c5aff182SThomas Petazzoni #define MVNETA_TXQ_SIZE_REG(q) (0x3c20 + ((q) << 2)) 235c5aff182SThomas Petazzoni #define MVNETA_TXQ_SENT_THRESH_ALL_MASK 0x3fff0000 236c5aff182SThomas Petazzoni #define MVNETA_TXQ_SENT_THRESH_MASK(coal) ((coal) << 16) 237c5aff182SThomas Petazzoni #define MVNETA_TXQ_UPDATE_REG(q) (0x3c60 + ((q) << 2)) 238c5aff182SThomas Petazzoni #define MVNETA_TXQ_DEC_SENT_SHIFT 16 2392a90f7e1SSimon Guinot #define MVNETA_TXQ_DEC_SENT_MASK 0xff 240c5aff182SThomas Petazzoni #define MVNETA_TXQ_STATUS_REG(q) (0x3c40 + ((q) << 2)) 241c5aff182SThomas Petazzoni #define MVNETA_TXQ_SENT_DESC_SHIFT 16 242c5aff182SThomas Petazzoni #define MVNETA_TXQ_SENT_DESC_MASK 0x3fff0000 243c5aff182SThomas Petazzoni #define MVNETA_PORT_TX_RESET 0x3cf0 244c5aff182SThomas Petazzoni #define MVNETA_PORT_TX_DMA_RESET BIT(0) 245c5aff182SThomas Petazzoni #define MVNETA_TX_MTU 0x3e0c 246c5aff182SThomas Petazzoni #define MVNETA_TX_TOKEN_SIZE 0x3e14 247c5aff182SThomas Petazzoni #define MVNETA_TX_TOKEN_SIZE_MAX 0xffffffff 248c5aff182SThomas Petazzoni #define MVNETA_TXQ_TOKEN_SIZE_REG(q) (0x3e40 + ((q) << 2)) 249c5aff182SThomas Petazzoni #define MVNETA_TXQ_TOKEN_SIZE_MAX 0x7fffffff 250c5aff182SThomas Petazzoni 2516d81f451SRussell King #define MVNETA_LPI_CTRL_0 0x2cc0 2526d81f451SRussell King #define MVNETA_LPI_CTRL_1 0x2cc4 2536d81f451SRussell King #define MVNETA_LPI_REQUEST_ENABLE BIT(0) 2546d81f451SRussell King #define MVNETA_LPI_CTRL_2 0x2cc8 2556d81f451SRussell King #define MVNETA_LPI_STATUS 0x2ccc 2566d81f451SRussell King 257c5aff182SThomas Petazzoni #define MVNETA_CAUSE_TXQ_SENT_DESC_ALL_MASK 0xff 258c5aff182SThomas Petazzoni 259c5aff182SThomas Petazzoni /* Descriptor ring Macros */ 260c5aff182SThomas Petazzoni #define MVNETA_QUEUE_NEXT_DESC(q, index) \ 261c5aff182SThomas Petazzoni (((index) < (q)->last_desc) ? ((index) + 1) : 0) 262c5aff182SThomas Petazzoni 263c5aff182SThomas Petazzoni /* Various constants */ 264c5aff182SThomas Petazzoni 265c5aff182SThomas Petazzoni /* Coalescing */ 26606708f81SDmitri Epshtein #define MVNETA_TXDONE_COAL_PKTS 0 /* interrupt per packet */ 267c5aff182SThomas Petazzoni #define MVNETA_RX_COAL_PKTS 32 268c5aff182SThomas Petazzoni #define MVNETA_RX_COAL_USEC 100 269c5aff182SThomas Petazzoni 2706a20c175SThomas Petazzoni /* The two bytes Marvell header. Either contains a special value used 271c5aff182SThomas Petazzoni * by Marvell switches when a specific hardware mode is enabled (not 272c5aff182SThomas Petazzoni * supported by this driver) or is filled automatically by zeroes on 273c5aff182SThomas Petazzoni * the RX side. Those two bytes being at the front of the Ethernet 274c5aff182SThomas Petazzoni * header, they allow to have the IP header aligned on a 4 bytes 275c5aff182SThomas Petazzoni * boundary automatically: the hardware skips those two bytes on its 276c5aff182SThomas Petazzoni * own. 277c5aff182SThomas Petazzoni */ 278c5aff182SThomas Petazzoni #define MVNETA_MH_SIZE 2 279c5aff182SThomas Petazzoni 280c5aff182SThomas Petazzoni #define MVNETA_VLAN_TAG_LEN 4 281c5aff182SThomas Petazzoni 2829110ee07SMarcin Wojtas #define MVNETA_TX_CSUM_DEF_SIZE 1600 283c5aff182SThomas Petazzoni #define MVNETA_TX_CSUM_MAX_SIZE 9800 284dc35a10fSMarcin Wojtas #define MVNETA_ACC_MODE_EXT1 1 285dc35a10fSMarcin Wojtas #define MVNETA_ACC_MODE_EXT2 2 286dc35a10fSMarcin Wojtas 287dc35a10fSMarcin Wojtas #define MVNETA_MAX_DECODE_WIN 6 288c5aff182SThomas Petazzoni 289c5aff182SThomas Petazzoni /* Timeout constants */ 290c5aff182SThomas Petazzoni #define MVNETA_TX_DISABLE_TIMEOUT_MSEC 1000 291c5aff182SThomas Petazzoni #define MVNETA_RX_DISABLE_TIMEOUT_MSEC 1000 292c5aff182SThomas Petazzoni #define MVNETA_TX_FIFO_EMPTY_TIMEOUT 10000 293c5aff182SThomas Petazzoni 294c5aff182SThomas Petazzoni #define MVNETA_TX_MTU_MAX 0x3ffff 295c5aff182SThomas Petazzoni 2969a401deaSGregory CLEMENT /* The RSS lookup table actually has 256 entries but we do not use 2979a401deaSGregory CLEMENT * them yet 2989a401deaSGregory CLEMENT */ 2999a401deaSGregory CLEMENT #define MVNETA_RSS_LU_TABLE_SIZE 1 3009a401deaSGregory CLEMENT 301c5aff182SThomas Petazzoni /* Max number of Rx descriptors */ 302c307e2a8SYelena Krivosheev #define MVNETA_MAX_RXD 512 303c5aff182SThomas Petazzoni 304c5aff182SThomas Petazzoni /* Max number of Tx descriptors */ 305c307e2a8SYelena Krivosheev #define MVNETA_MAX_TXD 1024 306c5aff182SThomas Petazzoni 3078eef5f97SEzequiel Garcia /* Max number of allowed TCP segments for software TSO */ 3088eef5f97SEzequiel Garcia #define MVNETA_MAX_TSO_SEGS 100 3098eef5f97SEzequiel Garcia 3108eef5f97SEzequiel Garcia #define MVNETA_MAX_SKB_DESCS (MVNETA_MAX_TSO_SEGS * 2 + MAX_SKB_FRAGS) 3118eef5f97SEzequiel Garcia 312c5aff182SThomas Petazzoni /* descriptor aligned size */ 313c5aff182SThomas Petazzoni #define MVNETA_DESC_ALIGNED_SIZE 32 314c5aff182SThomas Petazzoni 3158d5047cfSMarcin Wojtas /* Number of bytes to be taken into account by HW when putting incoming data 3168d5047cfSMarcin Wojtas * to the buffers. It is needed in case NET_SKB_PAD exceeds maximum packet 3178d5047cfSMarcin Wojtas * offset supported in MVNETA_RXQ_CONFIG_REG(q) registers. 3188d5047cfSMarcin Wojtas */ 3198d5047cfSMarcin Wojtas #define MVNETA_RX_PKT_OFFSET_CORRECTION 64 3208d5047cfSMarcin Wojtas 321c5aff182SThomas Petazzoni #define MVNETA_RX_PKT_SIZE(mtu) \ 322c5aff182SThomas Petazzoni ALIGN((mtu) + MVNETA_MH_SIZE + MVNETA_VLAN_TAG_LEN + \ 323c5aff182SThomas Petazzoni ETH_HLEN + ETH_FCS_LEN, \ 324c66e98c9SJisheng Zhang cache_line_size()) 325c5aff182SThomas Petazzoni 3262e3173a3SEzequiel Garcia #define IS_TSO_HEADER(txq, addr) \ 3272e3173a3SEzequiel Garcia ((addr >= txq->tso_hdrs_phys) && \ 3282e3173a3SEzequiel Garcia (addr < txq->tso_hdrs_phys + txq->size * TSO_HEADER_SIZE)) 3292e3173a3SEzequiel Garcia 330dc35a10fSMarcin Wojtas #define MVNETA_RX_GET_BM_POOL_ID(rxd) \ 331dc35a10fSMarcin Wojtas (((rxd)->status & MVNETA_RXD_BM_POOL_MASK) >> MVNETA_RXD_BM_POOL_SHIFT) 332c5aff182SThomas Petazzoni 3336d81f451SRussell King enum { 3346d81f451SRussell King ETHTOOL_STAT_EEE_WAKEUP, 33517a96da6SGregory CLEMENT ETHTOOL_STAT_SKB_ALLOC_ERR, 33617a96da6SGregory CLEMENT ETHTOOL_STAT_REFILL_ERR, 3376d81f451SRussell King ETHTOOL_MAX_STATS, 3386d81f451SRussell King }; 3396d81f451SRussell King 3409b0cdefaSRussell King struct mvneta_statistic { 3419b0cdefaSRussell King unsigned short offset; 3429b0cdefaSRussell King unsigned short type; 3439b0cdefaSRussell King const char name[ETH_GSTRING_LEN]; 3449b0cdefaSRussell King }; 3459b0cdefaSRussell King 3469b0cdefaSRussell King #define T_REG_32 32 3479b0cdefaSRussell King #define T_REG_64 64 3486d81f451SRussell King #define T_SW 1 3499b0cdefaSRussell King 3509b0cdefaSRussell King static const struct mvneta_statistic mvneta_statistics[] = { 3519b0cdefaSRussell King { 0x3000, T_REG_64, "good_octets_received", }, 3529b0cdefaSRussell King { 0x3010, T_REG_32, "good_frames_received", }, 3539b0cdefaSRussell King { 0x3008, T_REG_32, "bad_octets_received", }, 3549b0cdefaSRussell King { 0x3014, T_REG_32, "bad_frames_received", }, 3559b0cdefaSRussell King { 0x3018, T_REG_32, "broadcast_frames_received", }, 3569b0cdefaSRussell King { 0x301c, T_REG_32, "multicast_frames_received", }, 3579b0cdefaSRussell King { 0x3050, T_REG_32, "unrec_mac_control_received", }, 3589b0cdefaSRussell King { 0x3058, T_REG_32, "good_fc_received", }, 3599b0cdefaSRussell King { 0x305c, T_REG_32, "bad_fc_received", }, 3609b0cdefaSRussell King { 0x3060, T_REG_32, "undersize_received", }, 3619b0cdefaSRussell King { 0x3064, T_REG_32, "fragments_received", }, 3629b0cdefaSRussell King { 0x3068, T_REG_32, "oversize_received", }, 3639b0cdefaSRussell King { 0x306c, T_REG_32, "jabber_received", }, 3649b0cdefaSRussell King { 0x3070, T_REG_32, "mac_receive_error", }, 3659b0cdefaSRussell King { 0x3074, T_REG_32, "bad_crc_event", }, 3669b0cdefaSRussell King { 0x3078, T_REG_32, "collision", }, 3679b0cdefaSRussell King { 0x307c, T_REG_32, "late_collision", }, 3689b0cdefaSRussell King { 0x2484, T_REG_32, "rx_discard", }, 3699b0cdefaSRussell King { 0x2488, T_REG_32, "rx_overrun", }, 3709b0cdefaSRussell King { 0x3020, T_REG_32, "frames_64_octets", }, 3719b0cdefaSRussell King { 0x3024, T_REG_32, "frames_65_to_127_octets", }, 3729b0cdefaSRussell King { 0x3028, T_REG_32, "frames_128_to_255_octets", }, 3739b0cdefaSRussell King { 0x302c, T_REG_32, "frames_256_to_511_octets", }, 3749b0cdefaSRussell King { 0x3030, T_REG_32, "frames_512_to_1023_octets", }, 3759b0cdefaSRussell King { 0x3034, T_REG_32, "frames_1024_to_max_octets", }, 3769b0cdefaSRussell King { 0x3038, T_REG_64, "good_octets_sent", }, 3779b0cdefaSRussell King { 0x3040, T_REG_32, "good_frames_sent", }, 3789b0cdefaSRussell King { 0x3044, T_REG_32, "excessive_collision", }, 3799b0cdefaSRussell King { 0x3048, T_REG_32, "multicast_frames_sent", }, 3809b0cdefaSRussell King { 0x304c, T_REG_32, "broadcast_frames_sent", }, 3819b0cdefaSRussell King { 0x3054, T_REG_32, "fc_sent", }, 3829b0cdefaSRussell King { 0x300c, T_REG_32, "internal_mac_transmit_err", }, 3836d81f451SRussell King { ETHTOOL_STAT_EEE_WAKEUP, T_SW, "eee_wakeup_errors", }, 38417a96da6SGregory CLEMENT { ETHTOOL_STAT_SKB_ALLOC_ERR, T_SW, "skb_alloc_errors", }, 38517a96da6SGregory CLEMENT { ETHTOOL_STAT_REFILL_ERR, T_SW, "refill_errors", }, 3869b0cdefaSRussell King }; 3879b0cdefaSRussell King 38874c41b04Swilly tarreau struct mvneta_pcpu_stats { 389c5aff182SThomas Petazzoni struct u64_stats_sync syncp; 39074c41b04Swilly tarreau u64 rx_packets; 39174c41b04Swilly tarreau u64 rx_bytes; 39274c41b04Swilly tarreau u64 tx_packets; 39374c41b04Swilly tarreau u64 tx_bytes; 394c5aff182SThomas Petazzoni }; 395c5aff182SThomas Petazzoni 39612bb03b4SMaxime Ripard struct mvneta_pcpu_port { 39712bb03b4SMaxime Ripard /* Pointer to the shared port */ 39812bb03b4SMaxime Ripard struct mvneta_port *pp; 39912bb03b4SMaxime Ripard 40012bb03b4SMaxime Ripard /* Pointer to the CPU-local NAPI struct */ 40112bb03b4SMaxime Ripard struct napi_struct napi; 40212bb03b4SMaxime Ripard 40312bb03b4SMaxime Ripard /* Cause of the previous interrupt */ 40412bb03b4SMaxime Ripard u32 cause_rx_tx; 40512bb03b4SMaxime Ripard }; 40612bb03b4SMaxime Ripard 407c5aff182SThomas Petazzoni struct mvneta_port { 408dc35a10fSMarcin Wojtas u8 id; 40912bb03b4SMaxime Ripard struct mvneta_pcpu_port __percpu *ports; 41012bb03b4SMaxime Ripard struct mvneta_pcpu_stats __percpu *stats; 41112bb03b4SMaxime Ripard 412c5aff182SThomas Petazzoni int pkt_size; 413c5aff182SThomas Petazzoni void __iomem *base; 414c5aff182SThomas Petazzoni struct mvneta_rx_queue *rxqs; 415c5aff182SThomas Petazzoni struct mvneta_tx_queue *txqs; 416c5aff182SThomas Petazzoni struct net_device *dev; 41784a3f4dbSSebastian Andrzej Siewior struct hlist_node node_online; 41884a3f4dbSSebastian Andrzej Siewior struct hlist_node node_dead; 41990b74c01SGregory CLEMENT int rxq_def; 4205888511eSGregory CLEMENT /* Protect the access to the percpu interrupt registers, 4215888511eSGregory CLEMENT * ensuring that the configuration remains coherent. 4225888511eSGregory CLEMENT */ 4235888511eSGregory CLEMENT spinlock_t lock; 424120cfa50SGregory CLEMENT bool is_stopped; 425c5aff182SThomas Petazzoni 4262636ac3cSMarcin Wojtas u32 cause_rx_tx; 4272636ac3cSMarcin Wojtas struct napi_struct napi; 4282636ac3cSMarcin Wojtas 429c5aff182SThomas Petazzoni /* Core clock */ 430189dd626SThomas Petazzoni struct clk *clk; 43115cc4a4aSJisheng Zhang /* AXI clock */ 43215cc4a4aSJisheng Zhang struct clk *clk_bus; 433c5aff182SThomas Petazzoni u8 mcast_count[256]; 434c5aff182SThomas Petazzoni u16 tx_ring_size; 435c5aff182SThomas Petazzoni u16 rx_ring_size; 436c5aff182SThomas Petazzoni 437c5aff182SThomas Petazzoni phy_interface_t phy_interface; 438503f9aa9SRussell King struct device_node *dn; 439b65657fcSSimon Guinot unsigned int tx_csum_limit; 440503f9aa9SRussell King struct phylink *phylink; 44144cc27e4SIoana Ciornei struct phylink_config phylink_config; 442a10c1c81SRussell King struct phy *comphy; 4439b0cdefaSRussell King 444dc35a10fSMarcin Wojtas struct mvneta_bm *bm_priv; 445dc35a10fSMarcin Wojtas struct mvneta_bm_pool *pool_long; 446dc35a10fSMarcin Wojtas struct mvneta_bm_pool *pool_short; 447dc35a10fSMarcin Wojtas int bm_win_id; 448dc35a10fSMarcin Wojtas 4496d81f451SRussell King bool eee_enabled; 4506d81f451SRussell King bool eee_active; 4516d81f451SRussell King bool tx_lpi_enabled; 4526d81f451SRussell King 4539b0cdefaSRussell King u64 ethtool_stats[ARRAY_SIZE(mvneta_statistics)]; 4549a401deaSGregory CLEMENT 4559a401deaSGregory CLEMENT u32 indir[MVNETA_RSS_LU_TABLE_SIZE]; 4562636ac3cSMarcin Wojtas 4572636ac3cSMarcin Wojtas /* Flags for special SoC configurations */ 4582636ac3cSMarcin Wojtas bool neta_armada3700; 4598d5047cfSMarcin Wojtas u16 rx_offset_correction; 4609768b45cSJane Li const struct mbus_dram_target_info *dram_target_info; 461c5aff182SThomas Petazzoni }; 462c5aff182SThomas Petazzoni 4636a20c175SThomas Petazzoni /* The mvneta_tx_desc and mvneta_rx_desc structures describe the 464c5aff182SThomas Petazzoni * layout of the transmit and reception DMA descriptors, and their 465c5aff182SThomas Petazzoni * layout is therefore defined by the hardware design 466c5aff182SThomas Petazzoni */ 4676083ed44SThomas Petazzoni 468c5aff182SThomas Petazzoni #define MVNETA_TX_L3_OFF_SHIFT 0 469c5aff182SThomas Petazzoni #define MVNETA_TX_IP_HLEN_SHIFT 8 470c5aff182SThomas Petazzoni #define MVNETA_TX_L4_UDP BIT(16) 471c5aff182SThomas Petazzoni #define MVNETA_TX_L3_IP6 BIT(17) 472c5aff182SThomas Petazzoni #define MVNETA_TXD_IP_CSUM BIT(18) 473c5aff182SThomas Petazzoni #define MVNETA_TXD_Z_PAD BIT(19) 474c5aff182SThomas Petazzoni #define MVNETA_TXD_L_DESC BIT(20) 475c5aff182SThomas Petazzoni #define MVNETA_TXD_F_DESC BIT(21) 476c5aff182SThomas Petazzoni #define MVNETA_TXD_FLZ_DESC (MVNETA_TXD_Z_PAD | \ 477c5aff182SThomas Petazzoni MVNETA_TXD_L_DESC | \ 478c5aff182SThomas Petazzoni MVNETA_TXD_F_DESC) 479c5aff182SThomas Petazzoni #define MVNETA_TX_L4_CSUM_FULL BIT(30) 480c5aff182SThomas Petazzoni #define MVNETA_TX_L4_CSUM_NOT BIT(31) 481c5aff182SThomas Petazzoni 482c5aff182SThomas Petazzoni #define MVNETA_RXD_ERR_CRC 0x0 483dc35a10fSMarcin Wojtas #define MVNETA_RXD_BM_POOL_SHIFT 13 484dc35a10fSMarcin Wojtas #define MVNETA_RXD_BM_POOL_MASK (BIT(13) | BIT(14)) 485c5aff182SThomas Petazzoni #define MVNETA_RXD_ERR_SUMMARY BIT(16) 486c5aff182SThomas Petazzoni #define MVNETA_RXD_ERR_OVERRUN BIT(17) 487c5aff182SThomas Petazzoni #define MVNETA_RXD_ERR_LEN BIT(18) 488c5aff182SThomas Petazzoni #define MVNETA_RXD_ERR_RESOURCE (BIT(17) | BIT(18)) 489c5aff182SThomas Petazzoni #define MVNETA_RXD_ERR_CODE_MASK (BIT(17) | BIT(18)) 490c5aff182SThomas Petazzoni #define MVNETA_RXD_L3_IP4 BIT(25) 491562e2f46SYelena Krivosheev #define MVNETA_RXD_LAST_DESC BIT(26) 492562e2f46SYelena Krivosheev #define MVNETA_RXD_FIRST_DESC BIT(27) 493562e2f46SYelena Krivosheev #define MVNETA_RXD_FIRST_LAST_DESC (MVNETA_RXD_FIRST_DESC | \ 494562e2f46SYelena Krivosheev MVNETA_RXD_LAST_DESC) 495c5aff182SThomas Petazzoni #define MVNETA_RXD_L4_CSUM_OK BIT(30) 496c5aff182SThomas Petazzoni 4979ad8fef6SThomas Petazzoni #if defined(__LITTLE_ENDIAN) 4986083ed44SThomas Petazzoni struct mvneta_tx_desc { 4996083ed44SThomas Petazzoni u32 command; /* Options used by HW for packet transmitting.*/ 500fbd1d524SAlexandre Belloni u16 reserved1; /* csum_l4 (for future use) */ 5016083ed44SThomas Petazzoni u16 data_size; /* Data size of transmitted packet in bytes */ 5026083ed44SThomas Petazzoni u32 buf_phys_addr; /* Physical addr of transmitted buffer */ 5036083ed44SThomas Petazzoni u32 reserved2; /* hw_cmd - (for future use, PMT) */ 5046083ed44SThomas Petazzoni u32 reserved3[4]; /* Reserved - (for future use) */ 5056083ed44SThomas Petazzoni }; 5066083ed44SThomas Petazzoni 5076083ed44SThomas Petazzoni struct mvneta_rx_desc { 5086083ed44SThomas Petazzoni u32 status; /* Info about received packet */ 509c5aff182SThomas Petazzoni u16 reserved1; /* pnc_info - (for future use, PnC) */ 510c5aff182SThomas Petazzoni u16 data_size; /* Size of received packet in bytes */ 5116083ed44SThomas Petazzoni 512c5aff182SThomas Petazzoni u32 buf_phys_addr; /* Physical address of the buffer */ 513c5aff182SThomas Petazzoni u32 reserved2; /* pnc_flow_id (for future use, PnC) */ 5146083ed44SThomas Petazzoni 515c5aff182SThomas Petazzoni u32 buf_cookie; /* cookie for access to RX buffer in rx path */ 516c5aff182SThomas Petazzoni u16 reserved3; /* prefetch_cmd, for future use */ 517c5aff182SThomas Petazzoni u16 reserved4; /* csum_l4 - (for future use, PnC) */ 5186083ed44SThomas Petazzoni 519c5aff182SThomas Petazzoni u32 reserved5; /* pnc_extra PnC (for future use, PnC) */ 520c5aff182SThomas Petazzoni u32 reserved6; /* hw_cmd (for future use, PnC and HWF) */ 521c5aff182SThomas Petazzoni }; 5229ad8fef6SThomas Petazzoni #else 5239ad8fef6SThomas Petazzoni struct mvneta_tx_desc { 5249ad8fef6SThomas Petazzoni u16 data_size; /* Data size of transmitted packet in bytes */ 525fbd1d524SAlexandre Belloni u16 reserved1; /* csum_l4 (for future use) */ 5269ad8fef6SThomas Petazzoni u32 command; /* Options used by HW for packet transmitting.*/ 5279ad8fef6SThomas Petazzoni u32 reserved2; /* hw_cmd - (for future use, PMT) */ 5289ad8fef6SThomas Petazzoni u32 buf_phys_addr; /* Physical addr of transmitted buffer */ 5299ad8fef6SThomas Petazzoni u32 reserved3[4]; /* Reserved - (for future use) */ 5309ad8fef6SThomas Petazzoni }; 5319ad8fef6SThomas Petazzoni 5329ad8fef6SThomas Petazzoni struct mvneta_rx_desc { 5339ad8fef6SThomas Petazzoni u16 data_size; /* Size of received packet in bytes */ 5349ad8fef6SThomas Petazzoni u16 reserved1; /* pnc_info - (for future use, PnC) */ 5359ad8fef6SThomas Petazzoni u32 status; /* Info about received packet */ 5369ad8fef6SThomas Petazzoni 5379ad8fef6SThomas Petazzoni u32 reserved2; /* pnc_flow_id (for future use, PnC) */ 5389ad8fef6SThomas Petazzoni u32 buf_phys_addr; /* Physical address of the buffer */ 5399ad8fef6SThomas Petazzoni 5409ad8fef6SThomas Petazzoni u16 reserved4; /* csum_l4 - (for future use, PnC) */ 5419ad8fef6SThomas Petazzoni u16 reserved3; /* prefetch_cmd, for future use */ 5429ad8fef6SThomas Petazzoni u32 buf_cookie; /* cookie for access to RX buffer in rx path */ 5439ad8fef6SThomas Petazzoni 5449ad8fef6SThomas Petazzoni u32 reserved5; /* pnc_extra PnC (for future use, PnC) */ 5459ad8fef6SThomas Petazzoni u32 reserved6; /* hw_cmd (for future use, PnC and HWF) */ 5469ad8fef6SThomas Petazzoni }; 5479ad8fef6SThomas Petazzoni #endif 548c5aff182SThomas Petazzoni 549c5aff182SThomas Petazzoni struct mvneta_tx_queue { 550c5aff182SThomas Petazzoni /* Number of this TX queue, in the range 0-7 */ 551c5aff182SThomas Petazzoni u8 id; 552c5aff182SThomas Petazzoni 553c5aff182SThomas Petazzoni /* Number of TX DMA descriptors in the descriptor ring */ 554c5aff182SThomas Petazzoni int size; 555c5aff182SThomas Petazzoni 556c5aff182SThomas Petazzoni /* Number of currently used TX DMA descriptor in the 5576a20c175SThomas Petazzoni * descriptor ring 5586a20c175SThomas Petazzoni */ 559c5aff182SThomas Petazzoni int count; 5602a90f7e1SSimon Guinot int pending; 5618eef5f97SEzequiel Garcia int tx_stop_threshold; 5628eef5f97SEzequiel Garcia int tx_wake_threshold; 563c5aff182SThomas Petazzoni 564c5aff182SThomas Petazzoni /* Array of transmitted skb */ 565c5aff182SThomas Petazzoni struct sk_buff **tx_skb; 566c5aff182SThomas Petazzoni 567c5aff182SThomas Petazzoni /* Index of last TX DMA descriptor that was inserted */ 568c5aff182SThomas Petazzoni int txq_put_index; 569c5aff182SThomas Petazzoni 570c5aff182SThomas Petazzoni /* Index of the TX DMA descriptor to be cleaned up */ 571c5aff182SThomas Petazzoni int txq_get_index; 572c5aff182SThomas Petazzoni 573c5aff182SThomas Petazzoni u32 done_pkts_coal; 574c5aff182SThomas Petazzoni 575c5aff182SThomas Petazzoni /* Virtual address of the TX DMA descriptors array */ 576c5aff182SThomas Petazzoni struct mvneta_tx_desc *descs; 577c5aff182SThomas Petazzoni 578c5aff182SThomas Petazzoni /* DMA address of the TX DMA descriptors array */ 579c5aff182SThomas Petazzoni dma_addr_t descs_phys; 580c5aff182SThomas Petazzoni 581c5aff182SThomas Petazzoni /* Index of the last TX DMA descriptor */ 582c5aff182SThomas Petazzoni int last_desc; 583c5aff182SThomas Petazzoni 584c5aff182SThomas Petazzoni /* Index of the next TX DMA descriptor to process */ 585c5aff182SThomas Petazzoni int next_desc_to_proc; 5862adb719dSEzequiel Garcia 5872adb719dSEzequiel Garcia /* DMA buffers for TSO headers */ 5882adb719dSEzequiel Garcia char *tso_hdrs; 5892adb719dSEzequiel Garcia 5902adb719dSEzequiel Garcia /* DMA address of TSO headers */ 5912adb719dSEzequiel Garcia dma_addr_t tso_hdrs_phys; 59250bf8cb6SGregory CLEMENT 59350bf8cb6SGregory CLEMENT /* Affinity mask for CPUs*/ 59450bf8cb6SGregory CLEMENT cpumask_t affinity_mask; 595c5aff182SThomas Petazzoni }; 596c5aff182SThomas Petazzoni 597c5aff182SThomas Petazzoni struct mvneta_rx_queue { 598c5aff182SThomas Petazzoni /* rx queue number, in the range 0-7 */ 599c5aff182SThomas Petazzoni u8 id; 600c5aff182SThomas Petazzoni 601c5aff182SThomas Petazzoni /* num of rx descriptors in the rx descriptor ring */ 602c5aff182SThomas Petazzoni int size; 603c5aff182SThomas Petazzoni 604c5aff182SThomas Petazzoni u32 pkts_coal; 605c5aff182SThomas Petazzoni u32 time_coal; 606c5aff182SThomas Petazzoni 607568a3fa2SLorenzo Bianconi /* page_pool */ 608568a3fa2SLorenzo Bianconi struct page_pool *page_pool; 609568a3fa2SLorenzo Bianconi struct xdp_rxq_info xdp_rxq; 610568a3fa2SLorenzo Bianconi 611f88bee1cSGregory CLEMENT /* Virtual address of the RX buffer */ 612f88bee1cSGregory CLEMENT void **buf_virt_addr; 613f88bee1cSGregory CLEMENT 614c5aff182SThomas Petazzoni /* Virtual address of the RX DMA descriptors array */ 615c5aff182SThomas Petazzoni struct mvneta_rx_desc *descs; 616c5aff182SThomas Petazzoni 617c5aff182SThomas Petazzoni /* DMA address of the RX DMA descriptors array */ 618c5aff182SThomas Petazzoni dma_addr_t descs_phys; 619c5aff182SThomas Petazzoni 620c5aff182SThomas Petazzoni /* Index of the last RX DMA descriptor */ 621c5aff182SThomas Petazzoni int last_desc; 622c5aff182SThomas Petazzoni 623c5aff182SThomas Petazzoni /* Index of the next RX DMA descriptor to process */ 624c5aff182SThomas Petazzoni int next_desc_to_proc; 62517a96da6SGregory CLEMENT 626562e2f46SYelena Krivosheev /* Index of first RX DMA descriptor to refill */ 627562e2f46SYelena Krivosheev int first_to_refill; 628562e2f46SYelena Krivosheev u32 refill_num; 629562e2f46SYelena Krivosheev 630562e2f46SYelena Krivosheev /* pointer to uncomplete skb buffer */ 631562e2f46SYelena Krivosheev struct sk_buff *skb; 632562e2f46SYelena Krivosheev int left_size; 633562e2f46SYelena Krivosheev 63417a96da6SGregory CLEMENT /* error counters */ 63517a96da6SGregory CLEMENT u32 skb_alloc_err; 63617a96da6SGregory CLEMENT u32 refill_err; 637c5aff182SThomas Petazzoni }; 638c5aff182SThomas Petazzoni 63984a3f4dbSSebastian Andrzej Siewior static enum cpuhp_state online_hpstate; 640edadb7faSEzequiel Garcia /* The hardware supports eight (8) rx queues, but we are only allowing 641edadb7faSEzequiel Garcia * the first one to be used. Therefore, let's just allocate one queue. 642edadb7faSEzequiel Garcia */ 643d8936657SMaxime Ripard static int rxq_number = 8; 644c5aff182SThomas Petazzoni static int txq_number = 8; 645c5aff182SThomas Petazzoni 646c5aff182SThomas Petazzoni static int rxq_def; 647c5aff182SThomas Petazzoni 648f19fadfcSwilly tarreau static int rx_copybreak __read_mostly = 256; 649562e2f46SYelena Krivosheev static int rx_header_size __read_mostly = 128; 650f19fadfcSwilly tarreau 651dc35a10fSMarcin Wojtas /* HW BM need that each port be identify by a unique ID */ 652dc35a10fSMarcin Wojtas static int global_port_id; 653dc35a10fSMarcin Wojtas 654c5aff182SThomas Petazzoni #define MVNETA_DRIVER_NAME "mvneta" 655c5aff182SThomas Petazzoni #define MVNETA_DRIVER_VERSION "1.0" 656c5aff182SThomas Petazzoni 657c5aff182SThomas Petazzoni /* Utility/helper methods */ 658c5aff182SThomas Petazzoni 659c5aff182SThomas Petazzoni /* Write helper method */ 660c5aff182SThomas Petazzoni static void mvreg_write(struct mvneta_port *pp, u32 offset, u32 data) 661c5aff182SThomas Petazzoni { 662c5aff182SThomas Petazzoni writel(data, pp->base + offset); 663c5aff182SThomas Petazzoni } 664c5aff182SThomas Petazzoni 665c5aff182SThomas Petazzoni /* Read helper method */ 666c5aff182SThomas Petazzoni static u32 mvreg_read(struct mvneta_port *pp, u32 offset) 667c5aff182SThomas Petazzoni { 668c5aff182SThomas Petazzoni return readl(pp->base + offset); 669c5aff182SThomas Petazzoni } 670c5aff182SThomas Petazzoni 671c5aff182SThomas Petazzoni /* Increment txq get counter */ 672c5aff182SThomas Petazzoni static void mvneta_txq_inc_get(struct mvneta_tx_queue *txq) 673c5aff182SThomas Petazzoni { 674c5aff182SThomas Petazzoni txq->txq_get_index++; 675c5aff182SThomas Petazzoni if (txq->txq_get_index == txq->size) 676c5aff182SThomas Petazzoni txq->txq_get_index = 0; 677c5aff182SThomas Petazzoni } 678c5aff182SThomas Petazzoni 679c5aff182SThomas Petazzoni /* Increment txq put counter */ 680c5aff182SThomas Petazzoni static void mvneta_txq_inc_put(struct mvneta_tx_queue *txq) 681c5aff182SThomas Petazzoni { 682c5aff182SThomas Petazzoni txq->txq_put_index++; 683c5aff182SThomas Petazzoni if (txq->txq_put_index == txq->size) 684c5aff182SThomas Petazzoni txq->txq_put_index = 0; 685c5aff182SThomas Petazzoni } 686c5aff182SThomas Petazzoni 687c5aff182SThomas Petazzoni 688c5aff182SThomas Petazzoni /* Clear all MIB counters */ 689c5aff182SThomas Petazzoni static void mvneta_mib_counters_clear(struct mvneta_port *pp) 690c5aff182SThomas Petazzoni { 691c5aff182SThomas Petazzoni int i; 692c5aff182SThomas Petazzoni u32 dummy; 693c5aff182SThomas Petazzoni 694c5aff182SThomas Petazzoni /* Perform dummy reads from MIB counters */ 695c5aff182SThomas Petazzoni for (i = 0; i < MVNETA_MIB_LATE_COLLISION; i += 4) 696c5aff182SThomas Petazzoni dummy = mvreg_read(pp, (MVNETA_MIB_COUNTERS_BASE + i)); 697e483911fSAndrew Lunn dummy = mvreg_read(pp, MVNETA_RX_DISCARD_FRAME_COUNT); 698e483911fSAndrew Lunn dummy = mvreg_read(pp, MVNETA_OVERRUN_FRAME_COUNT); 699c5aff182SThomas Petazzoni } 700c5aff182SThomas Petazzoni 701c5aff182SThomas Petazzoni /* Get System Network Statistics */ 702bc1f4470Sstephen hemminger static void 7032dc0d2b4SBaoyou Xie mvneta_get_stats64(struct net_device *dev, 704c5aff182SThomas Petazzoni struct rtnl_link_stats64 *stats) 705c5aff182SThomas Petazzoni { 706c5aff182SThomas Petazzoni struct mvneta_port *pp = netdev_priv(dev); 707c5aff182SThomas Petazzoni unsigned int start; 70874c41b04Swilly tarreau int cpu; 709c5aff182SThomas Petazzoni 71074c41b04Swilly tarreau for_each_possible_cpu(cpu) { 71174c41b04Swilly tarreau struct mvneta_pcpu_stats *cpu_stats; 71274c41b04Swilly tarreau u64 rx_packets; 71374c41b04Swilly tarreau u64 rx_bytes; 71474c41b04Swilly tarreau u64 tx_packets; 71574c41b04Swilly tarreau u64 tx_bytes; 716c5aff182SThomas Petazzoni 71774c41b04Swilly tarreau cpu_stats = per_cpu_ptr(pp->stats, cpu); 718c5aff182SThomas Petazzoni do { 71957a7744eSEric W. Biederman start = u64_stats_fetch_begin_irq(&cpu_stats->syncp); 72074c41b04Swilly tarreau rx_packets = cpu_stats->rx_packets; 72174c41b04Swilly tarreau rx_bytes = cpu_stats->rx_bytes; 72274c41b04Swilly tarreau tx_packets = cpu_stats->tx_packets; 72374c41b04Swilly tarreau tx_bytes = cpu_stats->tx_bytes; 72457a7744eSEric W. Biederman } while (u64_stats_fetch_retry_irq(&cpu_stats->syncp, start)); 725c5aff182SThomas Petazzoni 72674c41b04Swilly tarreau stats->rx_packets += rx_packets; 72774c41b04Swilly tarreau stats->rx_bytes += rx_bytes; 72874c41b04Swilly tarreau stats->tx_packets += tx_packets; 72974c41b04Swilly tarreau stats->tx_bytes += tx_bytes; 73074c41b04Swilly tarreau } 731c5aff182SThomas Petazzoni 732c5aff182SThomas Petazzoni stats->rx_errors = dev->stats.rx_errors; 733c5aff182SThomas Petazzoni stats->rx_dropped = dev->stats.rx_dropped; 734c5aff182SThomas Petazzoni 735c5aff182SThomas Petazzoni stats->tx_dropped = dev->stats.tx_dropped; 736c5aff182SThomas Petazzoni } 737c5aff182SThomas Petazzoni 738c5aff182SThomas Petazzoni /* Rx descriptors helper methods */ 739c5aff182SThomas Petazzoni 7405428213cSwilly tarreau /* Checks whether the RX descriptor having this status is both the first 7415428213cSwilly tarreau * and the last descriptor for the RX packet. Each RX packet is currently 742c5aff182SThomas Petazzoni * received through a single RX descriptor, so not having each RX 743c5aff182SThomas Petazzoni * descriptor with its first and last bits set is an error 744c5aff182SThomas Petazzoni */ 7455428213cSwilly tarreau static int mvneta_rxq_desc_is_first_last(u32 status) 746c5aff182SThomas Petazzoni { 7475428213cSwilly tarreau return (status & MVNETA_RXD_FIRST_LAST_DESC) == 748c5aff182SThomas Petazzoni MVNETA_RXD_FIRST_LAST_DESC; 749c5aff182SThomas Petazzoni } 750c5aff182SThomas Petazzoni 751c5aff182SThomas Petazzoni /* Add number of descriptors ready to receive new packets */ 752c5aff182SThomas Petazzoni static void mvneta_rxq_non_occup_desc_add(struct mvneta_port *pp, 753c5aff182SThomas Petazzoni struct mvneta_rx_queue *rxq, 754c5aff182SThomas Petazzoni int ndescs) 755c5aff182SThomas Petazzoni { 756c5aff182SThomas Petazzoni /* Only MVNETA_RXQ_ADD_NON_OCCUPIED_MAX (255) descriptors can 7576a20c175SThomas Petazzoni * be added at once 7586a20c175SThomas Petazzoni */ 759c5aff182SThomas Petazzoni while (ndescs > MVNETA_RXQ_ADD_NON_OCCUPIED_MAX) { 760c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id), 761c5aff182SThomas Petazzoni (MVNETA_RXQ_ADD_NON_OCCUPIED_MAX << 762c5aff182SThomas Petazzoni MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT)); 763c5aff182SThomas Petazzoni ndescs -= MVNETA_RXQ_ADD_NON_OCCUPIED_MAX; 764c5aff182SThomas Petazzoni } 765c5aff182SThomas Petazzoni 766c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id), 767c5aff182SThomas Petazzoni (ndescs << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT)); 768c5aff182SThomas Petazzoni } 769c5aff182SThomas Petazzoni 770c5aff182SThomas Petazzoni /* Get number of RX descriptors occupied by received packets */ 771c5aff182SThomas Petazzoni static int mvneta_rxq_busy_desc_num_get(struct mvneta_port *pp, 772c5aff182SThomas Petazzoni struct mvneta_rx_queue *rxq) 773c5aff182SThomas Petazzoni { 774c5aff182SThomas Petazzoni u32 val; 775c5aff182SThomas Petazzoni 776c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_RXQ_STATUS_REG(rxq->id)); 777c5aff182SThomas Petazzoni return val & MVNETA_RXQ_OCCUPIED_ALL_MASK; 778c5aff182SThomas Petazzoni } 779c5aff182SThomas Petazzoni 7806a20c175SThomas Petazzoni /* Update num of rx desc called upon return from rx path or 781c5aff182SThomas Petazzoni * from mvneta_rxq_drop_pkts(). 782c5aff182SThomas Petazzoni */ 783c5aff182SThomas Petazzoni static void mvneta_rxq_desc_num_update(struct mvneta_port *pp, 784c5aff182SThomas Petazzoni struct mvneta_rx_queue *rxq, 785c5aff182SThomas Petazzoni int rx_done, int rx_filled) 786c5aff182SThomas Petazzoni { 787c5aff182SThomas Petazzoni u32 val; 788c5aff182SThomas Petazzoni 789c5aff182SThomas Petazzoni if ((rx_done <= 0xff) && (rx_filled <= 0xff)) { 790c5aff182SThomas Petazzoni val = rx_done | 791c5aff182SThomas Petazzoni (rx_filled << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT); 792c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id), val); 793c5aff182SThomas Petazzoni return; 794c5aff182SThomas Petazzoni } 795c5aff182SThomas Petazzoni 796c5aff182SThomas Petazzoni /* Only 255 descriptors can be added at once */ 797c5aff182SThomas Petazzoni while ((rx_done > 0) || (rx_filled > 0)) { 798c5aff182SThomas Petazzoni if (rx_done <= 0xff) { 799c5aff182SThomas Petazzoni val = rx_done; 800c5aff182SThomas Petazzoni rx_done = 0; 801c5aff182SThomas Petazzoni } else { 802c5aff182SThomas Petazzoni val = 0xff; 803c5aff182SThomas Petazzoni rx_done -= 0xff; 804c5aff182SThomas Petazzoni } 805c5aff182SThomas Petazzoni if (rx_filled <= 0xff) { 806c5aff182SThomas Petazzoni val |= rx_filled << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT; 807c5aff182SThomas Petazzoni rx_filled = 0; 808c5aff182SThomas Petazzoni } else { 809c5aff182SThomas Petazzoni val |= 0xff << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT; 810c5aff182SThomas Petazzoni rx_filled -= 0xff; 811c5aff182SThomas Petazzoni } 812c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id), val); 813c5aff182SThomas Petazzoni } 814c5aff182SThomas Petazzoni } 815c5aff182SThomas Petazzoni 816c5aff182SThomas Petazzoni /* Get pointer to next RX descriptor to be processed by SW */ 817c5aff182SThomas Petazzoni static struct mvneta_rx_desc * 818c5aff182SThomas Petazzoni mvneta_rxq_next_desc_get(struct mvneta_rx_queue *rxq) 819c5aff182SThomas Petazzoni { 820c5aff182SThomas Petazzoni int rx_desc = rxq->next_desc_to_proc; 821c5aff182SThomas Petazzoni 822c5aff182SThomas Petazzoni rxq->next_desc_to_proc = MVNETA_QUEUE_NEXT_DESC(rxq, rx_desc); 82334e4179dSwilly tarreau prefetch(rxq->descs + rxq->next_desc_to_proc); 824c5aff182SThomas Petazzoni return rxq->descs + rx_desc; 825c5aff182SThomas Petazzoni } 826c5aff182SThomas Petazzoni 827c5aff182SThomas Petazzoni /* Change maximum receive size of the port. */ 828c5aff182SThomas Petazzoni static void mvneta_max_rx_size_set(struct mvneta_port *pp, int max_rx_size) 829c5aff182SThomas Petazzoni { 830c5aff182SThomas Petazzoni u32 val; 831c5aff182SThomas Petazzoni 832c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_GMAC_CTRL_0); 833c5aff182SThomas Petazzoni val &= ~MVNETA_GMAC_MAX_RX_SIZE_MASK; 834c5aff182SThomas Petazzoni val |= ((max_rx_size - MVNETA_MH_SIZE) / 2) << 835c5aff182SThomas Petazzoni MVNETA_GMAC_MAX_RX_SIZE_SHIFT; 836c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_GMAC_CTRL_0, val); 837c5aff182SThomas Petazzoni } 838c5aff182SThomas Petazzoni 839c5aff182SThomas Petazzoni 840c5aff182SThomas Petazzoni /* Set rx queue offset */ 841c5aff182SThomas Petazzoni static void mvneta_rxq_offset_set(struct mvneta_port *pp, 842c5aff182SThomas Petazzoni struct mvneta_rx_queue *rxq, 843c5aff182SThomas Petazzoni int offset) 844c5aff182SThomas Petazzoni { 845c5aff182SThomas Petazzoni u32 val; 846c5aff182SThomas Petazzoni 847c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_RXQ_CONFIG_REG(rxq->id)); 848c5aff182SThomas Petazzoni val &= ~MVNETA_RXQ_PKT_OFFSET_ALL_MASK; 849c5aff182SThomas Petazzoni 850c5aff182SThomas Petazzoni /* Offset is in */ 851c5aff182SThomas Petazzoni val |= MVNETA_RXQ_PKT_OFFSET_MASK(offset >> 3); 852c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_RXQ_CONFIG_REG(rxq->id), val); 853c5aff182SThomas Petazzoni } 854c5aff182SThomas Petazzoni 855c5aff182SThomas Petazzoni 856c5aff182SThomas Petazzoni /* Tx descriptors helper methods */ 857c5aff182SThomas Petazzoni 858c5aff182SThomas Petazzoni /* Update HW with number of TX descriptors to be sent */ 859c5aff182SThomas Petazzoni static void mvneta_txq_pend_desc_add(struct mvneta_port *pp, 860c5aff182SThomas Petazzoni struct mvneta_tx_queue *txq, 861c5aff182SThomas Petazzoni int pend_desc) 862c5aff182SThomas Petazzoni { 863c5aff182SThomas Petazzoni u32 val; 864c5aff182SThomas Petazzoni 8650d63785cSSimon Guinot pend_desc += txq->pending; 8660d63785cSSimon Guinot 8670d63785cSSimon Guinot /* Only 255 Tx descriptors can be added at once */ 8680d63785cSSimon Guinot do { 8690d63785cSSimon Guinot val = min(pend_desc, 255); 870c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val); 8710d63785cSSimon Guinot pend_desc -= val; 8720d63785cSSimon Guinot } while (pend_desc > 0); 8732a90f7e1SSimon Guinot txq->pending = 0; 874c5aff182SThomas Petazzoni } 875c5aff182SThomas Petazzoni 876c5aff182SThomas Petazzoni /* Get pointer to next TX descriptor to be processed (send) by HW */ 877c5aff182SThomas Petazzoni static struct mvneta_tx_desc * 878c5aff182SThomas Petazzoni mvneta_txq_next_desc_get(struct mvneta_tx_queue *txq) 879c5aff182SThomas Petazzoni { 880c5aff182SThomas Petazzoni int tx_desc = txq->next_desc_to_proc; 881c5aff182SThomas Petazzoni 882c5aff182SThomas Petazzoni txq->next_desc_to_proc = MVNETA_QUEUE_NEXT_DESC(txq, tx_desc); 883c5aff182SThomas Petazzoni return txq->descs + tx_desc; 884c5aff182SThomas Petazzoni } 885c5aff182SThomas Petazzoni 886c5aff182SThomas Petazzoni /* Release the last allocated TX descriptor. Useful to handle DMA 8876a20c175SThomas Petazzoni * mapping failures in the TX path. 8886a20c175SThomas Petazzoni */ 889c5aff182SThomas Petazzoni static void mvneta_txq_desc_put(struct mvneta_tx_queue *txq) 890c5aff182SThomas Petazzoni { 891c5aff182SThomas Petazzoni if (txq->next_desc_to_proc == 0) 892c5aff182SThomas Petazzoni txq->next_desc_to_proc = txq->last_desc - 1; 893c5aff182SThomas Petazzoni else 894c5aff182SThomas Petazzoni txq->next_desc_to_proc--; 895c5aff182SThomas Petazzoni } 896c5aff182SThomas Petazzoni 897c5aff182SThomas Petazzoni /* Set rxq buf size */ 898c5aff182SThomas Petazzoni static void mvneta_rxq_buf_size_set(struct mvneta_port *pp, 899c5aff182SThomas Petazzoni struct mvneta_rx_queue *rxq, 900c5aff182SThomas Petazzoni int buf_size) 901c5aff182SThomas Petazzoni { 902c5aff182SThomas Petazzoni u32 val; 903c5aff182SThomas Petazzoni 904c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_RXQ_SIZE_REG(rxq->id)); 905c5aff182SThomas Petazzoni 906c5aff182SThomas Petazzoni val &= ~MVNETA_RXQ_BUF_SIZE_MASK; 907c5aff182SThomas Petazzoni val |= ((buf_size >> 3) << MVNETA_RXQ_BUF_SIZE_SHIFT); 908c5aff182SThomas Petazzoni 909c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_RXQ_SIZE_REG(rxq->id), val); 910c5aff182SThomas Petazzoni } 911c5aff182SThomas Petazzoni 912c5aff182SThomas Petazzoni /* Disable buffer management (BM) */ 913c5aff182SThomas Petazzoni static void mvneta_rxq_bm_disable(struct mvneta_port *pp, 914c5aff182SThomas Petazzoni struct mvneta_rx_queue *rxq) 915c5aff182SThomas Petazzoni { 916c5aff182SThomas Petazzoni u32 val; 917c5aff182SThomas Petazzoni 918c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_RXQ_CONFIG_REG(rxq->id)); 919c5aff182SThomas Petazzoni val &= ~MVNETA_RXQ_HW_BUF_ALLOC; 920c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_RXQ_CONFIG_REG(rxq->id), val); 921c5aff182SThomas Petazzoni } 922c5aff182SThomas Petazzoni 923dc35a10fSMarcin Wojtas /* Enable buffer management (BM) */ 924dc35a10fSMarcin Wojtas static void mvneta_rxq_bm_enable(struct mvneta_port *pp, 925dc35a10fSMarcin Wojtas struct mvneta_rx_queue *rxq) 926dc35a10fSMarcin Wojtas { 927dc35a10fSMarcin Wojtas u32 val; 928dc35a10fSMarcin Wojtas 929dc35a10fSMarcin Wojtas val = mvreg_read(pp, MVNETA_RXQ_CONFIG_REG(rxq->id)); 930dc35a10fSMarcin Wojtas val |= MVNETA_RXQ_HW_BUF_ALLOC; 931dc35a10fSMarcin Wojtas mvreg_write(pp, MVNETA_RXQ_CONFIG_REG(rxq->id), val); 932dc35a10fSMarcin Wojtas } 933dc35a10fSMarcin Wojtas 934dc35a10fSMarcin Wojtas /* Notify HW about port's assignment of pool for bigger packets */ 935dc35a10fSMarcin Wojtas static void mvneta_rxq_long_pool_set(struct mvneta_port *pp, 936dc35a10fSMarcin Wojtas struct mvneta_rx_queue *rxq) 937dc35a10fSMarcin Wojtas { 938dc35a10fSMarcin Wojtas u32 val; 939dc35a10fSMarcin Wojtas 940dc35a10fSMarcin Wojtas val = mvreg_read(pp, MVNETA_RXQ_CONFIG_REG(rxq->id)); 941dc35a10fSMarcin Wojtas val &= ~MVNETA_RXQ_LONG_POOL_ID_MASK; 942dc35a10fSMarcin Wojtas val |= (pp->pool_long->id << MVNETA_RXQ_LONG_POOL_ID_SHIFT); 943dc35a10fSMarcin Wojtas 944dc35a10fSMarcin Wojtas mvreg_write(pp, MVNETA_RXQ_CONFIG_REG(rxq->id), val); 945dc35a10fSMarcin Wojtas } 946dc35a10fSMarcin Wojtas 947dc35a10fSMarcin Wojtas /* Notify HW about port's assignment of pool for smaller packets */ 948dc35a10fSMarcin Wojtas static void mvneta_rxq_short_pool_set(struct mvneta_port *pp, 949dc35a10fSMarcin Wojtas struct mvneta_rx_queue *rxq) 950dc35a10fSMarcin Wojtas { 951dc35a10fSMarcin Wojtas u32 val; 952dc35a10fSMarcin Wojtas 953dc35a10fSMarcin Wojtas val = mvreg_read(pp, MVNETA_RXQ_CONFIG_REG(rxq->id)); 954dc35a10fSMarcin Wojtas val &= ~MVNETA_RXQ_SHORT_POOL_ID_MASK; 955dc35a10fSMarcin Wojtas val |= (pp->pool_short->id << MVNETA_RXQ_SHORT_POOL_ID_SHIFT); 956dc35a10fSMarcin Wojtas 957dc35a10fSMarcin Wojtas mvreg_write(pp, MVNETA_RXQ_CONFIG_REG(rxq->id), val); 958dc35a10fSMarcin Wojtas } 959dc35a10fSMarcin Wojtas 960dc35a10fSMarcin Wojtas /* Set port's receive buffer size for assigned BM pool */ 961dc35a10fSMarcin Wojtas static inline void mvneta_bm_pool_bufsize_set(struct mvneta_port *pp, 962dc35a10fSMarcin Wojtas int buf_size, 963dc35a10fSMarcin Wojtas u8 pool_id) 964dc35a10fSMarcin Wojtas { 965dc35a10fSMarcin Wojtas u32 val; 966dc35a10fSMarcin Wojtas 967dc35a10fSMarcin Wojtas if (!IS_ALIGNED(buf_size, 8)) { 968dc35a10fSMarcin Wojtas dev_warn(pp->dev->dev.parent, 969dc35a10fSMarcin Wojtas "illegal buf_size value %d, round to %d\n", 970dc35a10fSMarcin Wojtas buf_size, ALIGN(buf_size, 8)); 971dc35a10fSMarcin Wojtas buf_size = ALIGN(buf_size, 8); 972dc35a10fSMarcin Wojtas } 973dc35a10fSMarcin Wojtas 974dc35a10fSMarcin Wojtas val = mvreg_read(pp, MVNETA_PORT_POOL_BUFFER_SZ_REG(pool_id)); 975dc35a10fSMarcin Wojtas val |= buf_size & MVNETA_PORT_POOL_BUFFER_SZ_MASK; 976dc35a10fSMarcin Wojtas mvreg_write(pp, MVNETA_PORT_POOL_BUFFER_SZ_REG(pool_id), val); 977dc35a10fSMarcin Wojtas } 978dc35a10fSMarcin Wojtas 979dc35a10fSMarcin Wojtas /* Configure MBUS window in order to enable access BM internal SRAM */ 980dc35a10fSMarcin Wojtas static int mvneta_mbus_io_win_set(struct mvneta_port *pp, u32 base, u32 wsize, 981dc35a10fSMarcin Wojtas u8 target, u8 attr) 982dc35a10fSMarcin Wojtas { 983dc35a10fSMarcin Wojtas u32 win_enable, win_protect; 984dc35a10fSMarcin Wojtas int i; 985dc35a10fSMarcin Wojtas 986dc35a10fSMarcin Wojtas win_enable = mvreg_read(pp, MVNETA_BASE_ADDR_ENABLE); 987dc35a10fSMarcin Wojtas 988dc35a10fSMarcin Wojtas if (pp->bm_win_id < 0) { 989dc35a10fSMarcin Wojtas /* Find first not occupied window */ 990dc35a10fSMarcin Wojtas for (i = 0; i < MVNETA_MAX_DECODE_WIN; i++) { 991dc35a10fSMarcin Wojtas if (win_enable & (1 << i)) { 992dc35a10fSMarcin Wojtas pp->bm_win_id = i; 993dc35a10fSMarcin Wojtas break; 994dc35a10fSMarcin Wojtas } 995dc35a10fSMarcin Wojtas } 996dc35a10fSMarcin Wojtas if (i == MVNETA_MAX_DECODE_WIN) 997dc35a10fSMarcin Wojtas return -ENOMEM; 998dc35a10fSMarcin Wojtas } else { 999dc35a10fSMarcin Wojtas i = pp->bm_win_id; 1000dc35a10fSMarcin Wojtas } 1001dc35a10fSMarcin Wojtas 1002dc35a10fSMarcin Wojtas mvreg_write(pp, MVNETA_WIN_BASE(i), 0); 1003dc35a10fSMarcin Wojtas mvreg_write(pp, MVNETA_WIN_SIZE(i), 0); 1004dc35a10fSMarcin Wojtas 1005dc35a10fSMarcin Wojtas if (i < 4) 1006dc35a10fSMarcin Wojtas mvreg_write(pp, MVNETA_WIN_REMAP(i), 0); 1007dc35a10fSMarcin Wojtas 1008dc35a10fSMarcin Wojtas mvreg_write(pp, MVNETA_WIN_BASE(i), (base & 0xffff0000) | 1009dc35a10fSMarcin Wojtas (attr << 8) | target); 1010dc35a10fSMarcin Wojtas 1011dc35a10fSMarcin Wojtas mvreg_write(pp, MVNETA_WIN_SIZE(i), (wsize - 1) & 0xffff0000); 1012dc35a10fSMarcin Wojtas 1013dc35a10fSMarcin Wojtas win_protect = mvreg_read(pp, MVNETA_ACCESS_PROTECT_ENABLE); 1014dc35a10fSMarcin Wojtas win_protect |= 3 << (2 * i); 1015dc35a10fSMarcin Wojtas mvreg_write(pp, MVNETA_ACCESS_PROTECT_ENABLE, win_protect); 1016dc35a10fSMarcin Wojtas 1017dc35a10fSMarcin Wojtas win_enable &= ~(1 << i); 1018dc35a10fSMarcin Wojtas mvreg_write(pp, MVNETA_BASE_ADDR_ENABLE, win_enable); 1019dc35a10fSMarcin Wojtas 1020dc35a10fSMarcin Wojtas return 0; 1021dc35a10fSMarcin Wojtas } 1022dc35a10fSMarcin Wojtas 10232636ac3cSMarcin Wojtas static int mvneta_bm_port_mbus_init(struct mvneta_port *pp) 1024dc35a10fSMarcin Wojtas { 10252636ac3cSMarcin Wojtas u32 wsize; 1026dc35a10fSMarcin Wojtas u8 target, attr; 1027dc35a10fSMarcin Wojtas int err; 1028dc35a10fSMarcin Wojtas 1029dc35a10fSMarcin Wojtas /* Get BM window information */ 1030dc35a10fSMarcin Wojtas err = mvebu_mbus_get_io_win_info(pp->bm_priv->bppi_phys_addr, &wsize, 1031dc35a10fSMarcin Wojtas &target, &attr); 1032dc35a10fSMarcin Wojtas if (err < 0) 1033dc35a10fSMarcin Wojtas return err; 1034dc35a10fSMarcin Wojtas 1035dc35a10fSMarcin Wojtas pp->bm_win_id = -1; 1036dc35a10fSMarcin Wojtas 1037dc35a10fSMarcin Wojtas /* Open NETA -> BM window */ 1038dc35a10fSMarcin Wojtas err = mvneta_mbus_io_win_set(pp, pp->bm_priv->bppi_phys_addr, wsize, 1039dc35a10fSMarcin Wojtas target, attr); 1040dc35a10fSMarcin Wojtas if (err < 0) { 1041dc35a10fSMarcin Wojtas netdev_info(pp->dev, "fail to configure mbus window to BM\n"); 1042dc35a10fSMarcin Wojtas return err; 1043dc35a10fSMarcin Wojtas } 10442636ac3cSMarcin Wojtas return 0; 10452636ac3cSMarcin Wojtas } 10462636ac3cSMarcin Wojtas 10472636ac3cSMarcin Wojtas /* Assign and initialize pools for port. In case of fail 10482636ac3cSMarcin Wojtas * buffer manager will remain disabled for current port. 10492636ac3cSMarcin Wojtas */ 10502636ac3cSMarcin Wojtas static int mvneta_bm_port_init(struct platform_device *pdev, 10512636ac3cSMarcin Wojtas struct mvneta_port *pp) 10522636ac3cSMarcin Wojtas { 10532636ac3cSMarcin Wojtas struct device_node *dn = pdev->dev.of_node; 10542636ac3cSMarcin Wojtas u32 long_pool_id, short_pool_id; 10552636ac3cSMarcin Wojtas 10562636ac3cSMarcin Wojtas if (!pp->neta_armada3700) { 10572636ac3cSMarcin Wojtas int ret; 10582636ac3cSMarcin Wojtas 10592636ac3cSMarcin Wojtas ret = mvneta_bm_port_mbus_init(pp); 10602636ac3cSMarcin Wojtas if (ret) 10612636ac3cSMarcin Wojtas return ret; 10622636ac3cSMarcin Wojtas } 1063dc35a10fSMarcin Wojtas 1064dc35a10fSMarcin Wojtas if (of_property_read_u32(dn, "bm,pool-long", &long_pool_id)) { 1065dc35a10fSMarcin Wojtas netdev_info(pp->dev, "missing long pool id\n"); 1066dc35a10fSMarcin Wojtas return -EINVAL; 1067dc35a10fSMarcin Wojtas } 1068dc35a10fSMarcin Wojtas 1069dc35a10fSMarcin Wojtas /* Create port's long pool depending on mtu */ 1070dc35a10fSMarcin Wojtas pp->pool_long = mvneta_bm_pool_use(pp->bm_priv, long_pool_id, 1071dc35a10fSMarcin Wojtas MVNETA_BM_LONG, pp->id, 1072dc35a10fSMarcin Wojtas MVNETA_RX_PKT_SIZE(pp->dev->mtu)); 1073dc35a10fSMarcin Wojtas if (!pp->pool_long) { 1074dc35a10fSMarcin Wojtas netdev_info(pp->dev, "fail to obtain long pool for port\n"); 1075dc35a10fSMarcin Wojtas return -ENOMEM; 1076dc35a10fSMarcin Wojtas } 1077dc35a10fSMarcin Wojtas 1078dc35a10fSMarcin Wojtas pp->pool_long->port_map |= 1 << pp->id; 1079dc35a10fSMarcin Wojtas 1080dc35a10fSMarcin Wojtas mvneta_bm_pool_bufsize_set(pp, pp->pool_long->buf_size, 1081dc35a10fSMarcin Wojtas pp->pool_long->id); 1082dc35a10fSMarcin Wojtas 1083dc35a10fSMarcin Wojtas /* If short pool id is not defined, assume using single pool */ 1084dc35a10fSMarcin Wojtas if (of_property_read_u32(dn, "bm,pool-short", &short_pool_id)) 1085dc35a10fSMarcin Wojtas short_pool_id = long_pool_id; 1086dc35a10fSMarcin Wojtas 1087dc35a10fSMarcin Wojtas /* Create port's short pool */ 1088dc35a10fSMarcin Wojtas pp->pool_short = mvneta_bm_pool_use(pp->bm_priv, short_pool_id, 1089dc35a10fSMarcin Wojtas MVNETA_BM_SHORT, pp->id, 1090dc35a10fSMarcin Wojtas MVNETA_BM_SHORT_PKT_SIZE); 1091dc35a10fSMarcin Wojtas if (!pp->pool_short) { 1092dc35a10fSMarcin Wojtas netdev_info(pp->dev, "fail to obtain short pool for port\n"); 1093dc35a10fSMarcin Wojtas mvneta_bm_pool_destroy(pp->bm_priv, pp->pool_long, 1 << pp->id); 1094dc35a10fSMarcin Wojtas return -ENOMEM; 1095dc35a10fSMarcin Wojtas } 1096dc35a10fSMarcin Wojtas 1097dc35a10fSMarcin Wojtas if (short_pool_id != long_pool_id) { 1098dc35a10fSMarcin Wojtas pp->pool_short->port_map |= 1 << pp->id; 1099dc35a10fSMarcin Wojtas mvneta_bm_pool_bufsize_set(pp, pp->pool_short->buf_size, 1100dc35a10fSMarcin Wojtas pp->pool_short->id); 1101dc35a10fSMarcin Wojtas } 1102dc35a10fSMarcin Wojtas 1103dc35a10fSMarcin Wojtas return 0; 1104dc35a10fSMarcin Wojtas } 1105dc35a10fSMarcin Wojtas 1106dc35a10fSMarcin Wojtas /* Update settings of a pool for bigger packets */ 1107dc35a10fSMarcin Wojtas static void mvneta_bm_update_mtu(struct mvneta_port *pp, int mtu) 1108dc35a10fSMarcin Wojtas { 1109dc35a10fSMarcin Wojtas struct mvneta_bm_pool *bm_pool = pp->pool_long; 1110baa11ebcSGregory CLEMENT struct hwbm_pool *hwbm_pool = &bm_pool->hwbm_pool; 1111dc35a10fSMarcin Wojtas int num; 1112dc35a10fSMarcin Wojtas 1113dc35a10fSMarcin Wojtas /* Release all buffers from long pool */ 1114dc35a10fSMarcin Wojtas mvneta_bm_bufs_free(pp->bm_priv, bm_pool, 1 << pp->id); 1115baa11ebcSGregory CLEMENT if (hwbm_pool->buf_num) { 1116dc35a10fSMarcin Wojtas WARN(1, "cannot free all buffers in pool %d\n", 1117dc35a10fSMarcin Wojtas bm_pool->id); 1118dc35a10fSMarcin Wojtas goto bm_mtu_err; 1119dc35a10fSMarcin Wojtas } 1120dc35a10fSMarcin Wojtas 1121dc35a10fSMarcin Wojtas bm_pool->pkt_size = MVNETA_RX_PKT_SIZE(mtu); 1122dc35a10fSMarcin Wojtas bm_pool->buf_size = MVNETA_RX_BUF_SIZE(bm_pool->pkt_size); 1123baa11ebcSGregory CLEMENT hwbm_pool->frag_size = SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) + 1124dc35a10fSMarcin Wojtas SKB_DATA_ALIGN(MVNETA_RX_BUF_SIZE(bm_pool->pkt_size)); 1125dc35a10fSMarcin Wojtas 1126dc35a10fSMarcin Wojtas /* Fill entire long pool */ 11276dcdd884SSebastian Andrzej Siewior num = hwbm_pool_add(hwbm_pool, hwbm_pool->size); 1128baa11ebcSGregory CLEMENT if (num != hwbm_pool->size) { 1129dc35a10fSMarcin Wojtas WARN(1, "pool %d: %d of %d allocated\n", 1130baa11ebcSGregory CLEMENT bm_pool->id, num, hwbm_pool->size); 1131dc35a10fSMarcin Wojtas goto bm_mtu_err; 1132dc35a10fSMarcin Wojtas } 1133dc35a10fSMarcin Wojtas mvneta_bm_pool_bufsize_set(pp, bm_pool->buf_size, bm_pool->id); 1134dc35a10fSMarcin Wojtas 1135dc35a10fSMarcin Wojtas return; 1136dc35a10fSMarcin Wojtas 1137dc35a10fSMarcin Wojtas bm_mtu_err: 1138dc35a10fSMarcin Wojtas mvneta_bm_pool_destroy(pp->bm_priv, pp->pool_long, 1 << pp->id); 1139dc35a10fSMarcin Wojtas mvneta_bm_pool_destroy(pp->bm_priv, pp->pool_short, 1 << pp->id); 1140dc35a10fSMarcin Wojtas 1141dc35a10fSMarcin Wojtas pp->bm_priv = NULL; 1142dc35a10fSMarcin Wojtas mvreg_write(pp, MVNETA_ACC_MODE, MVNETA_ACC_MODE_EXT1); 1143dc35a10fSMarcin Wojtas netdev_info(pp->dev, "fail to update MTU, fall back to software BM\n"); 1144dc35a10fSMarcin Wojtas } 1145dc35a10fSMarcin Wojtas 1146c5aff182SThomas Petazzoni /* Start the Ethernet port RX and TX activity */ 1147c5aff182SThomas Petazzoni static void mvneta_port_up(struct mvneta_port *pp) 1148c5aff182SThomas Petazzoni { 1149c5aff182SThomas Petazzoni int queue; 1150c5aff182SThomas Petazzoni u32 q_map; 1151c5aff182SThomas Petazzoni 1152c5aff182SThomas Petazzoni /* Enable all initialized TXs. */ 1153c5aff182SThomas Petazzoni q_map = 0; 1154c5aff182SThomas Petazzoni for (queue = 0; queue < txq_number; queue++) { 1155c5aff182SThomas Petazzoni struct mvneta_tx_queue *txq = &pp->txqs[queue]; 1156f95936ccSMarkus Elfring if (txq->descs) 1157c5aff182SThomas Petazzoni q_map |= (1 << queue); 1158c5aff182SThomas Petazzoni } 1159c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_TXQ_CMD, q_map); 1160c5aff182SThomas Petazzoni 1161e81b5e01SYelena Krivosheev q_map = 0; 1162c5aff182SThomas Petazzoni /* Enable all initialized RXQs. */ 11632dcf75e2SGregory CLEMENT for (queue = 0; queue < rxq_number; queue++) { 11642dcf75e2SGregory CLEMENT struct mvneta_rx_queue *rxq = &pp->rxqs[queue]; 11652dcf75e2SGregory CLEMENT 1166f95936ccSMarkus Elfring if (rxq->descs) 11672dcf75e2SGregory CLEMENT q_map |= (1 << queue); 11682dcf75e2SGregory CLEMENT } 11692dcf75e2SGregory CLEMENT mvreg_write(pp, MVNETA_RXQ_CMD, q_map); 1170c5aff182SThomas Petazzoni } 1171c5aff182SThomas Petazzoni 1172c5aff182SThomas Petazzoni /* Stop the Ethernet port activity */ 1173c5aff182SThomas Petazzoni static void mvneta_port_down(struct mvneta_port *pp) 1174c5aff182SThomas Petazzoni { 1175c5aff182SThomas Petazzoni u32 val; 1176c5aff182SThomas Petazzoni int count; 1177c5aff182SThomas Petazzoni 1178c5aff182SThomas Petazzoni /* Stop Rx port activity. Check port Rx activity. */ 1179c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_RXQ_CMD) & MVNETA_RXQ_ENABLE_MASK; 1180c5aff182SThomas Petazzoni 1181c5aff182SThomas Petazzoni /* Issue stop command for active channels only */ 1182c5aff182SThomas Petazzoni if (val != 0) 1183c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_RXQ_CMD, 1184c5aff182SThomas Petazzoni val << MVNETA_RXQ_DISABLE_SHIFT); 1185c5aff182SThomas Petazzoni 1186c5aff182SThomas Petazzoni /* Wait for all Rx activity to terminate. */ 1187c5aff182SThomas Petazzoni count = 0; 1188c5aff182SThomas Petazzoni do { 1189c5aff182SThomas Petazzoni if (count++ >= MVNETA_RX_DISABLE_TIMEOUT_MSEC) { 1190c5aff182SThomas Petazzoni netdev_warn(pp->dev, 11910838abb3SDmitri Epshtein "TIMEOUT for RX stopped ! rx_queue_cmd: 0x%08x\n", 1192c5aff182SThomas Petazzoni val); 1193c5aff182SThomas Petazzoni break; 1194c5aff182SThomas Petazzoni } 1195c5aff182SThomas Petazzoni mdelay(1); 1196c5aff182SThomas Petazzoni 1197c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_RXQ_CMD); 1198a3703fb3SDmitri Epshtein } while (val & MVNETA_RXQ_ENABLE_MASK); 1199c5aff182SThomas Petazzoni 1200c5aff182SThomas Petazzoni /* Stop Tx port activity. Check port Tx activity. Issue stop 12016a20c175SThomas Petazzoni * command for active channels only 12026a20c175SThomas Petazzoni */ 1203c5aff182SThomas Petazzoni val = (mvreg_read(pp, MVNETA_TXQ_CMD)) & MVNETA_TXQ_ENABLE_MASK; 1204c5aff182SThomas Petazzoni 1205c5aff182SThomas Petazzoni if (val != 0) 1206c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_TXQ_CMD, 1207c5aff182SThomas Petazzoni (val << MVNETA_TXQ_DISABLE_SHIFT)); 1208c5aff182SThomas Petazzoni 1209c5aff182SThomas Petazzoni /* Wait for all Tx activity to terminate. */ 1210c5aff182SThomas Petazzoni count = 0; 1211c5aff182SThomas Petazzoni do { 1212c5aff182SThomas Petazzoni if (count++ >= MVNETA_TX_DISABLE_TIMEOUT_MSEC) { 1213c5aff182SThomas Petazzoni netdev_warn(pp->dev, 1214c5aff182SThomas Petazzoni "TIMEOUT for TX stopped status=0x%08x\n", 1215c5aff182SThomas Petazzoni val); 1216c5aff182SThomas Petazzoni break; 1217c5aff182SThomas Petazzoni } 1218c5aff182SThomas Petazzoni mdelay(1); 1219c5aff182SThomas Petazzoni 1220c5aff182SThomas Petazzoni /* Check TX Command reg that all Txqs are stopped */ 1221c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_TXQ_CMD); 1222c5aff182SThomas Petazzoni 1223a3703fb3SDmitri Epshtein } while (val & MVNETA_TXQ_ENABLE_MASK); 1224c5aff182SThomas Petazzoni 1225c5aff182SThomas Petazzoni /* Double check to verify that TX FIFO is empty */ 1226c5aff182SThomas Petazzoni count = 0; 1227c5aff182SThomas Petazzoni do { 1228c5aff182SThomas Petazzoni if (count++ >= MVNETA_TX_FIFO_EMPTY_TIMEOUT) { 1229c5aff182SThomas Petazzoni netdev_warn(pp->dev, 12300838abb3SDmitri Epshtein "TX FIFO empty timeout status=0x%08x\n", 1231c5aff182SThomas Petazzoni val); 1232c5aff182SThomas Petazzoni break; 1233c5aff182SThomas Petazzoni } 1234c5aff182SThomas Petazzoni mdelay(1); 1235c5aff182SThomas Petazzoni 1236c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_PORT_STATUS); 1237c5aff182SThomas Petazzoni } while (!(val & MVNETA_TX_FIFO_EMPTY) && 1238c5aff182SThomas Petazzoni (val & MVNETA_TX_IN_PRGRS)); 1239c5aff182SThomas Petazzoni 1240c5aff182SThomas Petazzoni udelay(200); 1241c5aff182SThomas Petazzoni } 1242c5aff182SThomas Petazzoni 1243c5aff182SThomas Petazzoni /* Enable the port by setting the port enable bit of the MAC control register */ 1244c5aff182SThomas Petazzoni static void mvneta_port_enable(struct mvneta_port *pp) 1245c5aff182SThomas Petazzoni { 1246c5aff182SThomas Petazzoni u32 val; 1247c5aff182SThomas Petazzoni 1248c5aff182SThomas Petazzoni /* Enable port */ 1249c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_GMAC_CTRL_0); 1250c5aff182SThomas Petazzoni val |= MVNETA_GMAC0_PORT_ENABLE; 1251c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_GMAC_CTRL_0, val); 1252c5aff182SThomas Petazzoni } 1253c5aff182SThomas Petazzoni 1254c5aff182SThomas Petazzoni /* Disable the port and wait for about 200 usec before retuning */ 1255c5aff182SThomas Petazzoni static void mvneta_port_disable(struct mvneta_port *pp) 1256c5aff182SThomas Petazzoni { 1257c5aff182SThomas Petazzoni u32 val; 1258c5aff182SThomas Petazzoni 1259c5aff182SThomas Petazzoni /* Reset the Enable bit in the Serial Control Register */ 1260c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_GMAC_CTRL_0); 1261c5aff182SThomas Petazzoni val &= ~MVNETA_GMAC0_PORT_ENABLE; 1262c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_GMAC_CTRL_0, val); 1263c5aff182SThomas Petazzoni 1264c5aff182SThomas Petazzoni udelay(200); 1265c5aff182SThomas Petazzoni } 1266c5aff182SThomas Petazzoni 1267c5aff182SThomas Petazzoni /* Multicast tables methods */ 1268c5aff182SThomas Petazzoni 1269c5aff182SThomas Petazzoni /* Set all entries in Unicast MAC Table; queue==-1 means reject all */ 1270c5aff182SThomas Petazzoni static void mvneta_set_ucast_table(struct mvneta_port *pp, int queue) 1271c5aff182SThomas Petazzoni { 1272c5aff182SThomas Petazzoni int offset; 1273c5aff182SThomas Petazzoni u32 val; 1274c5aff182SThomas Petazzoni 1275c5aff182SThomas Petazzoni if (queue == -1) { 1276c5aff182SThomas Petazzoni val = 0; 1277c5aff182SThomas Petazzoni } else { 1278c5aff182SThomas Petazzoni val = 0x1 | (queue << 1); 1279c5aff182SThomas Petazzoni val |= (val << 24) | (val << 16) | (val << 8); 1280c5aff182SThomas Petazzoni } 1281c5aff182SThomas Petazzoni 1282c5aff182SThomas Petazzoni for (offset = 0; offset <= 0xc; offset += 4) 1283c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_DA_FILT_UCAST_BASE + offset, val); 1284c5aff182SThomas Petazzoni } 1285c5aff182SThomas Petazzoni 1286c5aff182SThomas Petazzoni /* Set all entries in Special Multicast MAC Table; queue==-1 means reject all */ 1287c5aff182SThomas Petazzoni static void mvneta_set_special_mcast_table(struct mvneta_port *pp, int queue) 1288c5aff182SThomas Petazzoni { 1289c5aff182SThomas Petazzoni int offset; 1290c5aff182SThomas Petazzoni u32 val; 1291c5aff182SThomas Petazzoni 1292c5aff182SThomas Petazzoni if (queue == -1) { 1293c5aff182SThomas Petazzoni val = 0; 1294c5aff182SThomas Petazzoni } else { 1295c5aff182SThomas Petazzoni val = 0x1 | (queue << 1); 1296c5aff182SThomas Petazzoni val |= (val << 24) | (val << 16) | (val << 8); 1297c5aff182SThomas Petazzoni } 1298c5aff182SThomas Petazzoni 1299c5aff182SThomas Petazzoni for (offset = 0; offset <= 0xfc; offset += 4) 1300c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_DA_FILT_SPEC_MCAST + offset, val); 1301c5aff182SThomas Petazzoni 1302c5aff182SThomas Petazzoni } 1303c5aff182SThomas Petazzoni 1304c5aff182SThomas Petazzoni /* Set all entries in Other Multicast MAC Table. queue==-1 means reject all */ 1305c5aff182SThomas Petazzoni static void mvneta_set_other_mcast_table(struct mvneta_port *pp, int queue) 1306c5aff182SThomas Petazzoni { 1307c5aff182SThomas Petazzoni int offset; 1308c5aff182SThomas Petazzoni u32 val; 1309c5aff182SThomas Petazzoni 1310c5aff182SThomas Petazzoni if (queue == -1) { 1311c5aff182SThomas Petazzoni memset(pp->mcast_count, 0, sizeof(pp->mcast_count)); 1312c5aff182SThomas Petazzoni val = 0; 1313c5aff182SThomas Petazzoni } else { 1314c5aff182SThomas Petazzoni memset(pp->mcast_count, 1, sizeof(pp->mcast_count)); 1315c5aff182SThomas Petazzoni val = 0x1 | (queue << 1); 1316c5aff182SThomas Petazzoni val |= (val << 24) | (val << 16) | (val << 8); 1317c5aff182SThomas Petazzoni } 1318c5aff182SThomas Petazzoni 1319c5aff182SThomas Petazzoni for (offset = 0; offset <= 0xfc; offset += 4) 1320c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_DA_FILT_OTH_MCAST + offset, val); 1321c5aff182SThomas Petazzoni } 1322c5aff182SThomas Petazzoni 1323db488c10SGregory CLEMENT static void mvneta_percpu_unmask_interrupt(void *arg) 1324db488c10SGregory CLEMENT { 1325db488c10SGregory CLEMENT struct mvneta_port *pp = arg; 1326db488c10SGregory CLEMENT 1327db488c10SGregory CLEMENT /* All the queue are unmasked, but actually only the ones 1328db488c10SGregory CLEMENT * mapped to this CPU will be unmasked 1329db488c10SGregory CLEMENT */ 1330db488c10SGregory CLEMENT mvreg_write(pp, MVNETA_INTR_NEW_MASK, 1331db488c10SGregory CLEMENT MVNETA_RX_INTR_MASK_ALL | 1332db488c10SGregory CLEMENT MVNETA_TX_INTR_MASK_ALL | 1333db488c10SGregory CLEMENT MVNETA_MISCINTR_INTR_MASK); 1334db488c10SGregory CLEMENT } 1335db488c10SGregory CLEMENT 1336db488c10SGregory CLEMENT static void mvneta_percpu_mask_interrupt(void *arg) 1337db488c10SGregory CLEMENT { 1338db488c10SGregory CLEMENT struct mvneta_port *pp = arg; 1339db488c10SGregory CLEMENT 1340db488c10SGregory CLEMENT /* All the queue are masked, but actually only the ones 1341db488c10SGregory CLEMENT * mapped to this CPU will be masked 1342db488c10SGregory CLEMENT */ 1343db488c10SGregory CLEMENT mvreg_write(pp, MVNETA_INTR_NEW_MASK, 0); 1344db488c10SGregory CLEMENT mvreg_write(pp, MVNETA_INTR_OLD_MASK, 0); 1345db488c10SGregory CLEMENT mvreg_write(pp, MVNETA_INTR_MISC_MASK, 0); 1346db488c10SGregory CLEMENT } 1347db488c10SGregory CLEMENT 1348db488c10SGregory CLEMENT static void mvneta_percpu_clear_intr_cause(void *arg) 1349db488c10SGregory CLEMENT { 1350db488c10SGregory CLEMENT struct mvneta_port *pp = arg; 1351db488c10SGregory CLEMENT 1352db488c10SGregory CLEMENT /* All the queue are cleared, but actually only the ones 1353db488c10SGregory CLEMENT * mapped to this CPU will be cleared 1354db488c10SGregory CLEMENT */ 1355db488c10SGregory CLEMENT mvreg_write(pp, MVNETA_INTR_NEW_CAUSE, 0); 1356db488c10SGregory CLEMENT mvreg_write(pp, MVNETA_INTR_MISC_CAUSE, 0); 1357db488c10SGregory CLEMENT mvreg_write(pp, MVNETA_INTR_OLD_CAUSE, 0); 1358db488c10SGregory CLEMENT } 1359db488c10SGregory CLEMENT 1360c5aff182SThomas Petazzoni /* This method sets defaults to the NETA port: 1361c5aff182SThomas Petazzoni * Clears interrupt Cause and Mask registers. 1362c5aff182SThomas Petazzoni * Clears all MAC tables. 1363c5aff182SThomas Petazzoni * Sets defaults to all registers. 1364c5aff182SThomas Petazzoni * Resets RX and TX descriptor rings. 1365c5aff182SThomas Petazzoni * Resets PHY. 1366c5aff182SThomas Petazzoni * This method can be called after mvneta_port_down() to return the port 1367c5aff182SThomas Petazzoni * settings to defaults. 1368c5aff182SThomas Petazzoni */ 1369c5aff182SThomas Petazzoni static void mvneta_defaults_set(struct mvneta_port *pp) 1370c5aff182SThomas Petazzoni { 1371c5aff182SThomas Petazzoni int cpu; 1372c5aff182SThomas Petazzoni int queue; 1373c5aff182SThomas Petazzoni u32 val; 13742dcf75e2SGregory CLEMENT int max_cpu = num_present_cpus(); 1375c5aff182SThomas Petazzoni 1376c5aff182SThomas Petazzoni /* Clear all Cause registers */ 1377db488c10SGregory CLEMENT on_each_cpu(mvneta_percpu_clear_intr_cause, pp, true); 1378c5aff182SThomas Petazzoni 1379c5aff182SThomas Petazzoni /* Mask all interrupts */ 1380db488c10SGregory CLEMENT on_each_cpu(mvneta_percpu_mask_interrupt, pp, true); 1381c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_INTR_ENABLE, 0); 1382c5aff182SThomas Petazzoni 1383c5aff182SThomas Petazzoni /* Enable MBUS Retry bit16 */ 1384c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_MBUS_RETRY, 0x20); 1385c5aff182SThomas Petazzoni 138650bf8cb6SGregory CLEMENT /* Set CPU queue access map. CPUs are assigned to the RX and 138750bf8cb6SGregory CLEMENT * TX queues modulo their number. If there is only one TX 138850bf8cb6SGregory CLEMENT * queue then it is assigned to the CPU associated to the 138950bf8cb6SGregory CLEMENT * default RX queue. 13906a20c175SThomas Petazzoni */ 13912dcf75e2SGregory CLEMENT for_each_present_cpu(cpu) { 13922dcf75e2SGregory CLEMENT int rxq_map = 0, txq_map = 0; 139350bf8cb6SGregory CLEMENT int rxq, txq; 13942636ac3cSMarcin Wojtas if (!pp->neta_armada3700) { 13952dcf75e2SGregory CLEMENT for (rxq = 0; rxq < rxq_number; rxq++) 13962dcf75e2SGregory CLEMENT if ((rxq % max_cpu) == cpu) 13972dcf75e2SGregory CLEMENT rxq_map |= MVNETA_CPU_RXQ_ACCESS(rxq); 13982dcf75e2SGregory CLEMENT 139950bf8cb6SGregory CLEMENT for (txq = 0; txq < txq_number; txq++) 140050bf8cb6SGregory CLEMENT if ((txq % max_cpu) == cpu) 140150bf8cb6SGregory CLEMENT txq_map |= MVNETA_CPU_TXQ_ACCESS(txq); 140250bf8cb6SGregory CLEMENT 140350bf8cb6SGregory CLEMENT /* With only one TX queue we configure a special case 140450bf8cb6SGregory CLEMENT * which will allow to get all the irq on a single 140550bf8cb6SGregory CLEMENT * CPU 140650bf8cb6SGregory CLEMENT */ 140750bf8cb6SGregory CLEMENT if (txq_number == 1) 140850bf8cb6SGregory CLEMENT txq_map = (cpu == pp->rxq_def) ? 140950bf8cb6SGregory CLEMENT MVNETA_CPU_TXQ_ACCESS(1) : 0; 14102dcf75e2SGregory CLEMENT 14112636ac3cSMarcin Wojtas } else { 14122636ac3cSMarcin Wojtas txq_map = MVNETA_CPU_TXQ_ACCESS_ALL_MASK; 14132636ac3cSMarcin Wojtas rxq_map = MVNETA_CPU_RXQ_ACCESS_ALL_MASK; 14142636ac3cSMarcin Wojtas } 14152636ac3cSMarcin Wojtas 14162dcf75e2SGregory CLEMENT mvreg_write(pp, MVNETA_CPU_MAP(cpu), rxq_map | txq_map); 14172dcf75e2SGregory CLEMENT } 1418c5aff182SThomas Petazzoni 1419c5aff182SThomas Petazzoni /* Reset RX and TX DMAs */ 1420c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_PORT_RX_RESET, MVNETA_PORT_RX_DMA_RESET); 1421c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_PORT_TX_RESET, MVNETA_PORT_TX_DMA_RESET); 1422c5aff182SThomas Petazzoni 1423c5aff182SThomas Petazzoni /* Disable Legacy WRR, Disable EJP, Release from reset */ 1424c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_TXQ_CMD_1, 0); 1425c5aff182SThomas Petazzoni for (queue = 0; queue < txq_number; queue++) { 1426c5aff182SThomas Petazzoni mvreg_write(pp, MVETH_TXQ_TOKEN_COUNT_REG(queue), 0); 1427c5aff182SThomas Petazzoni mvreg_write(pp, MVETH_TXQ_TOKEN_CFG_REG(queue), 0); 1428c5aff182SThomas Petazzoni } 1429c5aff182SThomas Petazzoni 1430c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_PORT_TX_RESET, 0); 1431c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_PORT_RX_RESET, 0); 1432c5aff182SThomas Petazzoni 1433c5aff182SThomas Petazzoni /* Set Port Acceleration Mode */ 1434dc35a10fSMarcin Wojtas if (pp->bm_priv) 1435dc35a10fSMarcin Wojtas /* HW buffer management + legacy parser */ 1436dc35a10fSMarcin Wojtas val = MVNETA_ACC_MODE_EXT2; 1437dc35a10fSMarcin Wojtas else 1438dc35a10fSMarcin Wojtas /* SW buffer management + legacy parser */ 1439dc35a10fSMarcin Wojtas val = MVNETA_ACC_MODE_EXT1; 1440c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_ACC_MODE, val); 1441c5aff182SThomas Petazzoni 1442dc35a10fSMarcin Wojtas if (pp->bm_priv) 1443dc35a10fSMarcin Wojtas mvreg_write(pp, MVNETA_BM_ADDRESS, pp->bm_priv->bppi_phys_addr); 1444dc35a10fSMarcin Wojtas 1445c5aff182SThomas Petazzoni /* Update val of portCfg register accordingly with all RxQueue types */ 144690b74c01SGregory CLEMENT val = MVNETA_PORT_CONFIG_DEFL_VALUE(pp->rxq_def); 1447c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_PORT_CONFIG, val); 1448c5aff182SThomas Petazzoni 1449c5aff182SThomas Petazzoni val = 0; 1450c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_PORT_CONFIG_EXTEND, val); 1451c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_RX_MIN_FRAME_SIZE, 64); 1452c5aff182SThomas Petazzoni 1453c5aff182SThomas Petazzoni /* Build PORT_SDMA_CONFIG_REG */ 1454c5aff182SThomas Petazzoni val = 0; 1455c5aff182SThomas Petazzoni 1456c5aff182SThomas Petazzoni /* Default burst size */ 1457c5aff182SThomas Petazzoni val |= MVNETA_TX_BRST_SZ_MASK(MVNETA_SDMA_BRST_SIZE_16); 1458c5aff182SThomas Petazzoni val |= MVNETA_RX_BRST_SZ_MASK(MVNETA_SDMA_BRST_SIZE_16); 14599ad8fef6SThomas Petazzoni val |= MVNETA_RX_NO_DATA_SWAP | MVNETA_TX_NO_DATA_SWAP; 1460c5aff182SThomas Petazzoni 14619ad8fef6SThomas Petazzoni #if defined(__BIG_ENDIAN) 14629ad8fef6SThomas Petazzoni val |= MVNETA_DESC_SWAP; 14639ad8fef6SThomas Petazzoni #endif 1464c5aff182SThomas Petazzoni 1465c5aff182SThomas Petazzoni /* Assign port SDMA configuration */ 1466c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_SDMA_CONFIG, val); 1467c5aff182SThomas Petazzoni 146871408602SThomas Petazzoni /* Disable PHY polling in hardware, since we're using the 146971408602SThomas Petazzoni * kernel phylib to do this. 147071408602SThomas Petazzoni */ 147171408602SThomas Petazzoni val = mvreg_read(pp, MVNETA_UNIT_CONTROL); 147271408602SThomas Petazzoni val &= ~MVNETA_PHY_POLLING_ENABLE; 147371408602SThomas Petazzoni mvreg_write(pp, MVNETA_UNIT_CONTROL, val); 147471408602SThomas Petazzoni 1475c5aff182SThomas Petazzoni mvneta_set_ucast_table(pp, -1); 1476c5aff182SThomas Petazzoni mvneta_set_special_mcast_table(pp, -1); 1477c5aff182SThomas Petazzoni mvneta_set_other_mcast_table(pp, -1); 1478c5aff182SThomas Petazzoni 1479c5aff182SThomas Petazzoni /* Set port interrupt enable register - default enable all */ 1480c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_INTR_ENABLE, 1481c5aff182SThomas Petazzoni (MVNETA_RXQ_INTR_ENABLE_ALL_MASK 1482c5aff182SThomas Petazzoni | MVNETA_TXQ_INTR_ENABLE_ALL_MASK)); 1483e483911fSAndrew Lunn 1484e483911fSAndrew Lunn mvneta_mib_counters_clear(pp); 1485c5aff182SThomas Petazzoni } 1486c5aff182SThomas Petazzoni 1487c5aff182SThomas Petazzoni /* Set max sizes for tx queues */ 1488c5aff182SThomas Petazzoni static void mvneta_txq_max_tx_size_set(struct mvneta_port *pp, int max_tx_size) 1489c5aff182SThomas Petazzoni 1490c5aff182SThomas Petazzoni { 1491c5aff182SThomas Petazzoni u32 val, size, mtu; 1492c5aff182SThomas Petazzoni int queue; 1493c5aff182SThomas Petazzoni 1494c5aff182SThomas Petazzoni mtu = max_tx_size * 8; 1495c5aff182SThomas Petazzoni if (mtu > MVNETA_TX_MTU_MAX) 1496c5aff182SThomas Petazzoni mtu = MVNETA_TX_MTU_MAX; 1497c5aff182SThomas Petazzoni 1498c5aff182SThomas Petazzoni /* Set MTU */ 1499c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_TX_MTU); 1500c5aff182SThomas Petazzoni val &= ~MVNETA_TX_MTU_MAX; 1501c5aff182SThomas Petazzoni val |= mtu; 1502c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_TX_MTU, val); 1503c5aff182SThomas Petazzoni 1504c5aff182SThomas Petazzoni /* TX token size and all TXQs token size must be larger that MTU */ 1505c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_TX_TOKEN_SIZE); 1506c5aff182SThomas Petazzoni 1507c5aff182SThomas Petazzoni size = val & MVNETA_TX_TOKEN_SIZE_MAX; 1508c5aff182SThomas Petazzoni if (size < mtu) { 1509c5aff182SThomas Petazzoni size = mtu; 1510c5aff182SThomas Petazzoni val &= ~MVNETA_TX_TOKEN_SIZE_MAX; 1511c5aff182SThomas Petazzoni val |= size; 1512c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_TX_TOKEN_SIZE, val); 1513c5aff182SThomas Petazzoni } 1514c5aff182SThomas Petazzoni for (queue = 0; queue < txq_number; queue++) { 1515c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_TXQ_TOKEN_SIZE_REG(queue)); 1516c5aff182SThomas Petazzoni 1517c5aff182SThomas Petazzoni size = val & MVNETA_TXQ_TOKEN_SIZE_MAX; 1518c5aff182SThomas Petazzoni if (size < mtu) { 1519c5aff182SThomas Petazzoni size = mtu; 1520c5aff182SThomas Petazzoni val &= ~MVNETA_TXQ_TOKEN_SIZE_MAX; 1521c5aff182SThomas Petazzoni val |= size; 1522c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_TXQ_TOKEN_SIZE_REG(queue), val); 1523c5aff182SThomas Petazzoni } 1524c5aff182SThomas Petazzoni } 1525c5aff182SThomas Petazzoni } 1526c5aff182SThomas Petazzoni 1527c5aff182SThomas Petazzoni /* Set unicast address */ 1528c5aff182SThomas Petazzoni static void mvneta_set_ucast_addr(struct mvneta_port *pp, u8 last_nibble, 1529c5aff182SThomas Petazzoni int queue) 1530c5aff182SThomas Petazzoni { 1531c5aff182SThomas Petazzoni unsigned int unicast_reg; 1532c5aff182SThomas Petazzoni unsigned int tbl_offset; 1533c5aff182SThomas Petazzoni unsigned int reg_offset; 1534c5aff182SThomas Petazzoni 1535c5aff182SThomas Petazzoni /* Locate the Unicast table entry */ 1536c5aff182SThomas Petazzoni last_nibble = (0xf & last_nibble); 1537c5aff182SThomas Petazzoni 1538c5aff182SThomas Petazzoni /* offset from unicast tbl base */ 1539c5aff182SThomas Petazzoni tbl_offset = (last_nibble / 4) * 4; 1540c5aff182SThomas Petazzoni 1541c5aff182SThomas Petazzoni /* offset within the above reg */ 1542c5aff182SThomas Petazzoni reg_offset = last_nibble % 4; 1543c5aff182SThomas Petazzoni 1544c5aff182SThomas Petazzoni unicast_reg = mvreg_read(pp, (MVNETA_DA_FILT_UCAST_BASE + tbl_offset)); 1545c5aff182SThomas Petazzoni 1546c5aff182SThomas Petazzoni if (queue == -1) { 1547c5aff182SThomas Petazzoni /* Clear accepts frame bit at specified unicast DA tbl entry */ 1548c5aff182SThomas Petazzoni unicast_reg &= ~(0xff << (8 * reg_offset)); 1549c5aff182SThomas Petazzoni } else { 1550c5aff182SThomas Petazzoni unicast_reg &= ~(0xff << (8 * reg_offset)); 1551c5aff182SThomas Petazzoni unicast_reg |= ((0x01 | (queue << 1)) << (8 * reg_offset)); 1552c5aff182SThomas Petazzoni } 1553c5aff182SThomas Petazzoni 1554c5aff182SThomas Petazzoni mvreg_write(pp, (MVNETA_DA_FILT_UCAST_BASE + tbl_offset), unicast_reg); 1555c5aff182SThomas Petazzoni } 1556c5aff182SThomas Petazzoni 1557c5aff182SThomas Petazzoni /* Set mac address */ 1558c5aff182SThomas Petazzoni static void mvneta_mac_addr_set(struct mvneta_port *pp, unsigned char *addr, 1559c5aff182SThomas Petazzoni int queue) 1560c5aff182SThomas Petazzoni { 1561c5aff182SThomas Petazzoni unsigned int mac_h; 1562c5aff182SThomas Petazzoni unsigned int mac_l; 1563c5aff182SThomas Petazzoni 1564c5aff182SThomas Petazzoni if (queue != -1) { 1565c5aff182SThomas Petazzoni mac_l = (addr[4] << 8) | (addr[5]); 1566c5aff182SThomas Petazzoni mac_h = (addr[0] << 24) | (addr[1] << 16) | 1567c5aff182SThomas Petazzoni (addr[2] << 8) | (addr[3] << 0); 1568c5aff182SThomas Petazzoni 1569c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_MAC_ADDR_LOW, mac_l); 1570c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_MAC_ADDR_HIGH, mac_h); 1571c5aff182SThomas Petazzoni } 1572c5aff182SThomas Petazzoni 1573c5aff182SThomas Petazzoni /* Accept frames of this address */ 1574c5aff182SThomas Petazzoni mvneta_set_ucast_addr(pp, addr[5], queue); 1575c5aff182SThomas Petazzoni } 1576c5aff182SThomas Petazzoni 15776a20c175SThomas Petazzoni /* Set the number of packets that will be received before RX interrupt 15786a20c175SThomas Petazzoni * will be generated by HW. 1579c5aff182SThomas Petazzoni */ 1580c5aff182SThomas Petazzoni static void mvneta_rx_pkts_coal_set(struct mvneta_port *pp, 1581c5aff182SThomas Petazzoni struct mvneta_rx_queue *rxq, u32 value) 1582c5aff182SThomas Petazzoni { 1583c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_RXQ_THRESHOLD_REG(rxq->id), 1584c5aff182SThomas Petazzoni value | MVNETA_RXQ_NON_OCCUPIED(0)); 1585c5aff182SThomas Petazzoni } 1586c5aff182SThomas Petazzoni 15876a20c175SThomas Petazzoni /* Set the time delay in usec before RX interrupt will be generated by 15886a20c175SThomas Petazzoni * HW. 1589c5aff182SThomas Petazzoni */ 1590c5aff182SThomas Petazzoni static void mvneta_rx_time_coal_set(struct mvneta_port *pp, 1591c5aff182SThomas Petazzoni struct mvneta_rx_queue *rxq, u32 value) 1592c5aff182SThomas Petazzoni { 1593189dd626SThomas Petazzoni u32 val; 1594189dd626SThomas Petazzoni unsigned long clk_rate; 1595189dd626SThomas Petazzoni 1596189dd626SThomas Petazzoni clk_rate = clk_get_rate(pp->clk); 1597189dd626SThomas Petazzoni val = (clk_rate / 1000000) * value; 1598c5aff182SThomas Petazzoni 1599c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_RXQ_TIME_COAL_REG(rxq->id), val); 1600c5aff182SThomas Petazzoni } 1601c5aff182SThomas Petazzoni 1602c5aff182SThomas Petazzoni /* Set threshold for TX_DONE pkts coalescing */ 1603c5aff182SThomas Petazzoni static void mvneta_tx_done_pkts_coal_set(struct mvneta_port *pp, 1604c5aff182SThomas Petazzoni struct mvneta_tx_queue *txq, u32 value) 1605c5aff182SThomas Petazzoni { 1606c5aff182SThomas Petazzoni u32 val; 1607c5aff182SThomas Petazzoni 1608c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_TXQ_SIZE_REG(txq->id)); 1609c5aff182SThomas Petazzoni 1610c5aff182SThomas Petazzoni val &= ~MVNETA_TXQ_SENT_THRESH_ALL_MASK; 1611c5aff182SThomas Petazzoni val |= MVNETA_TXQ_SENT_THRESH_MASK(value); 1612c5aff182SThomas Petazzoni 1613c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_TXQ_SIZE_REG(txq->id), val); 1614c5aff182SThomas Petazzoni } 1615c5aff182SThomas Petazzoni 1616c5aff182SThomas Petazzoni /* Handle rx descriptor fill by setting buf_cookie and buf_phys_addr */ 1617c5aff182SThomas Petazzoni static void mvneta_rx_desc_fill(struct mvneta_rx_desc *rx_desc, 1618f88bee1cSGregory CLEMENT u32 phys_addr, void *virt_addr, 1619f88bee1cSGregory CLEMENT struct mvneta_rx_queue *rxq) 1620c5aff182SThomas Petazzoni { 1621f88bee1cSGregory CLEMENT int i; 1622f88bee1cSGregory CLEMENT 1623c5aff182SThomas Petazzoni rx_desc->buf_phys_addr = phys_addr; 1624f88bee1cSGregory CLEMENT i = rx_desc - rxq->descs; 1625f88bee1cSGregory CLEMENT rxq->buf_virt_addr[i] = virt_addr; 1626c5aff182SThomas Petazzoni } 1627c5aff182SThomas Petazzoni 1628c5aff182SThomas Petazzoni /* Decrement sent descriptors counter */ 1629c5aff182SThomas Petazzoni static void mvneta_txq_sent_desc_dec(struct mvneta_port *pp, 1630c5aff182SThomas Petazzoni struct mvneta_tx_queue *txq, 1631c5aff182SThomas Petazzoni int sent_desc) 1632c5aff182SThomas Petazzoni { 1633c5aff182SThomas Petazzoni u32 val; 1634c5aff182SThomas Petazzoni 1635c5aff182SThomas Petazzoni /* Only 255 TX descriptors can be updated at once */ 1636c5aff182SThomas Petazzoni while (sent_desc > 0xff) { 1637c5aff182SThomas Petazzoni val = 0xff << MVNETA_TXQ_DEC_SENT_SHIFT; 1638c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val); 1639c5aff182SThomas Petazzoni sent_desc = sent_desc - 0xff; 1640c5aff182SThomas Petazzoni } 1641c5aff182SThomas Petazzoni 1642c5aff182SThomas Petazzoni val = sent_desc << MVNETA_TXQ_DEC_SENT_SHIFT; 1643c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val); 1644c5aff182SThomas Petazzoni } 1645c5aff182SThomas Petazzoni 1646c5aff182SThomas Petazzoni /* Get number of TX descriptors already sent by HW */ 1647c5aff182SThomas Petazzoni static int mvneta_txq_sent_desc_num_get(struct mvneta_port *pp, 1648c5aff182SThomas Petazzoni struct mvneta_tx_queue *txq) 1649c5aff182SThomas Petazzoni { 1650c5aff182SThomas Petazzoni u32 val; 1651c5aff182SThomas Petazzoni int sent_desc; 1652c5aff182SThomas Petazzoni 1653c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_TXQ_STATUS_REG(txq->id)); 1654c5aff182SThomas Petazzoni sent_desc = (val & MVNETA_TXQ_SENT_DESC_MASK) >> 1655c5aff182SThomas Petazzoni MVNETA_TXQ_SENT_DESC_SHIFT; 1656c5aff182SThomas Petazzoni 1657c5aff182SThomas Petazzoni return sent_desc; 1658c5aff182SThomas Petazzoni } 1659c5aff182SThomas Petazzoni 16606a20c175SThomas Petazzoni /* Get number of sent descriptors and decrement counter. 1661c5aff182SThomas Petazzoni * The number of sent descriptors is returned. 1662c5aff182SThomas Petazzoni */ 1663c5aff182SThomas Petazzoni static int mvneta_txq_sent_desc_proc(struct mvneta_port *pp, 1664c5aff182SThomas Petazzoni struct mvneta_tx_queue *txq) 1665c5aff182SThomas Petazzoni { 1666c5aff182SThomas Petazzoni int sent_desc; 1667c5aff182SThomas Petazzoni 1668c5aff182SThomas Petazzoni /* Get number of sent descriptors */ 1669c5aff182SThomas Petazzoni sent_desc = mvneta_txq_sent_desc_num_get(pp, txq); 1670c5aff182SThomas Petazzoni 1671c5aff182SThomas Petazzoni /* Decrement sent descriptors counter */ 1672c5aff182SThomas Petazzoni if (sent_desc) 1673c5aff182SThomas Petazzoni mvneta_txq_sent_desc_dec(pp, txq, sent_desc); 1674c5aff182SThomas Petazzoni 1675c5aff182SThomas Petazzoni return sent_desc; 1676c5aff182SThomas Petazzoni } 1677c5aff182SThomas Petazzoni 1678c5aff182SThomas Petazzoni /* Set TXQ descriptors fields relevant for CSUM calculation */ 1679c5aff182SThomas Petazzoni static u32 mvneta_txq_desc_csum(int l3_offs, int l3_proto, 1680c5aff182SThomas Petazzoni int ip_hdr_len, int l4_proto) 1681c5aff182SThomas Petazzoni { 1682c5aff182SThomas Petazzoni u32 command; 1683c5aff182SThomas Petazzoni 1684c5aff182SThomas Petazzoni /* Fields: L3_offset, IP_hdrlen, L3_type, G_IPv4_chk, 16856a20c175SThomas Petazzoni * G_L4_chk, L4_type; required only for checksum 16866a20c175SThomas Petazzoni * calculation 16876a20c175SThomas Petazzoni */ 1688c5aff182SThomas Petazzoni command = l3_offs << MVNETA_TX_L3_OFF_SHIFT; 1689c5aff182SThomas Petazzoni command |= ip_hdr_len << MVNETA_TX_IP_HLEN_SHIFT; 1690c5aff182SThomas Petazzoni 16910a198587SThomas Fitzsimmons if (l3_proto == htons(ETH_P_IP)) 1692c5aff182SThomas Petazzoni command |= MVNETA_TXD_IP_CSUM; 1693c5aff182SThomas Petazzoni else 1694c5aff182SThomas Petazzoni command |= MVNETA_TX_L3_IP6; 1695c5aff182SThomas Petazzoni 1696c5aff182SThomas Petazzoni if (l4_proto == IPPROTO_TCP) 1697c5aff182SThomas Petazzoni command |= MVNETA_TX_L4_CSUM_FULL; 1698c5aff182SThomas Petazzoni else if (l4_proto == IPPROTO_UDP) 1699c5aff182SThomas Petazzoni command |= MVNETA_TX_L4_UDP | MVNETA_TX_L4_CSUM_FULL; 1700c5aff182SThomas Petazzoni else 1701c5aff182SThomas Petazzoni command |= MVNETA_TX_L4_CSUM_NOT; 1702c5aff182SThomas Petazzoni 1703c5aff182SThomas Petazzoni return command; 1704c5aff182SThomas Petazzoni } 1705c5aff182SThomas Petazzoni 1706c5aff182SThomas Petazzoni 1707c5aff182SThomas Petazzoni /* Display more error info */ 1708c5aff182SThomas Petazzoni static void mvneta_rx_error(struct mvneta_port *pp, 1709c5aff182SThomas Petazzoni struct mvneta_rx_desc *rx_desc) 1710c5aff182SThomas Petazzoni { 1711c5aff182SThomas Petazzoni u32 status = rx_desc->status; 1712c5aff182SThomas Petazzoni 1713c5aff182SThomas Petazzoni switch (status & MVNETA_RXD_ERR_CODE_MASK) { 1714c5aff182SThomas Petazzoni case MVNETA_RXD_ERR_CRC: 1715c5aff182SThomas Petazzoni netdev_err(pp->dev, "bad rx status %08x (crc error), size=%d\n", 1716c5aff182SThomas Petazzoni status, rx_desc->data_size); 1717c5aff182SThomas Petazzoni break; 1718c5aff182SThomas Petazzoni case MVNETA_RXD_ERR_OVERRUN: 1719c5aff182SThomas Petazzoni netdev_err(pp->dev, "bad rx status %08x (overrun error), size=%d\n", 1720c5aff182SThomas Petazzoni status, rx_desc->data_size); 1721c5aff182SThomas Petazzoni break; 1722c5aff182SThomas Petazzoni case MVNETA_RXD_ERR_LEN: 1723c5aff182SThomas Petazzoni netdev_err(pp->dev, "bad rx status %08x (max frame length error), size=%d\n", 1724c5aff182SThomas Petazzoni status, rx_desc->data_size); 1725c5aff182SThomas Petazzoni break; 1726c5aff182SThomas Petazzoni case MVNETA_RXD_ERR_RESOURCE: 1727c5aff182SThomas Petazzoni netdev_err(pp->dev, "bad rx status %08x (resource error), size=%d\n", 1728c5aff182SThomas Petazzoni status, rx_desc->data_size); 1729c5aff182SThomas Petazzoni break; 1730c5aff182SThomas Petazzoni } 1731c5aff182SThomas Petazzoni } 1732c5aff182SThomas Petazzoni 17335428213cSwilly tarreau /* Handle RX checksum offload based on the descriptor's status */ 17345428213cSwilly tarreau static void mvneta_rx_csum(struct mvneta_port *pp, u32 status, 1735c5aff182SThomas Petazzoni struct sk_buff *skb) 1736c5aff182SThomas Petazzoni { 1737f945cec8SYelena Krivosheev if ((pp->dev->features & NETIF_F_RXCSUM) && 1738f945cec8SYelena Krivosheev (status & MVNETA_RXD_L3_IP4) && 17395428213cSwilly tarreau (status & MVNETA_RXD_L4_CSUM_OK)) { 1740c5aff182SThomas Petazzoni skb->csum = 0; 1741c5aff182SThomas Petazzoni skb->ip_summed = CHECKSUM_UNNECESSARY; 1742c5aff182SThomas Petazzoni return; 1743c5aff182SThomas Petazzoni } 1744c5aff182SThomas Petazzoni 1745c5aff182SThomas Petazzoni skb->ip_summed = CHECKSUM_NONE; 1746c5aff182SThomas Petazzoni } 1747c5aff182SThomas Petazzoni 17486c498974Swilly tarreau /* Return tx queue pointer (find last set bit) according to <cause> returned 17496c498974Swilly tarreau * form tx_done reg. <cause> must not be null. The return value is always a 17506c498974Swilly tarreau * valid queue for matching the first one found in <cause>. 17516c498974Swilly tarreau */ 1752c5aff182SThomas Petazzoni static struct mvneta_tx_queue *mvneta_tx_done_policy(struct mvneta_port *pp, 1753c5aff182SThomas Petazzoni u32 cause) 1754c5aff182SThomas Petazzoni { 1755c5aff182SThomas Petazzoni int queue = fls(cause) - 1; 1756c5aff182SThomas Petazzoni 17576c498974Swilly tarreau return &pp->txqs[queue]; 1758c5aff182SThomas Petazzoni } 1759c5aff182SThomas Petazzoni 1760c5aff182SThomas Petazzoni /* Free tx queue skbuffs */ 1761c5aff182SThomas Petazzoni static void mvneta_txq_bufs_free(struct mvneta_port *pp, 1762a29b6235SMarcin Wojtas struct mvneta_tx_queue *txq, int num, 1763a29b6235SMarcin Wojtas struct netdev_queue *nq) 1764c5aff182SThomas Petazzoni { 1765a29b6235SMarcin Wojtas unsigned int bytes_compl = 0, pkts_compl = 0; 1766c5aff182SThomas Petazzoni int i; 1767c5aff182SThomas Petazzoni 1768c5aff182SThomas Petazzoni for (i = 0; i < num; i++) { 1769c5aff182SThomas Petazzoni struct mvneta_tx_desc *tx_desc = txq->descs + 1770c5aff182SThomas Petazzoni txq->txq_get_index; 1771c5aff182SThomas Petazzoni struct sk_buff *skb = txq->tx_skb[txq->txq_get_index]; 1772c5aff182SThomas Petazzoni 1773a29b6235SMarcin Wojtas if (skb) { 1774a29b6235SMarcin Wojtas bytes_compl += skb->len; 1775a29b6235SMarcin Wojtas pkts_compl++; 1776a29b6235SMarcin Wojtas } 1777a29b6235SMarcin Wojtas 1778c5aff182SThomas Petazzoni mvneta_txq_inc_get(txq); 1779c5aff182SThomas Petazzoni 17802e3173a3SEzequiel Garcia if (!IS_TSO_HEADER(txq, tx_desc->buf_phys_addr)) 17812e3173a3SEzequiel Garcia dma_unmap_single(pp->dev->dev.parent, 17822e3173a3SEzequiel Garcia tx_desc->buf_phys_addr, 1783c5aff182SThomas Petazzoni tx_desc->data_size, DMA_TO_DEVICE); 1784ba7e46efSEzequiel Garcia if (!skb) 1785ba7e46efSEzequiel Garcia continue; 1786c5aff182SThomas Petazzoni dev_kfree_skb_any(skb); 1787c5aff182SThomas Petazzoni } 1788a29b6235SMarcin Wojtas 1789a29b6235SMarcin Wojtas netdev_tx_completed_queue(nq, pkts_compl, bytes_compl); 1790c5aff182SThomas Petazzoni } 1791c5aff182SThomas Petazzoni 1792c5aff182SThomas Petazzoni /* Handle end of transmission */ 1793cd713199SArnaud Ebalard static void mvneta_txq_done(struct mvneta_port *pp, 1794c5aff182SThomas Petazzoni struct mvneta_tx_queue *txq) 1795c5aff182SThomas Petazzoni { 1796c5aff182SThomas Petazzoni struct netdev_queue *nq = netdev_get_tx_queue(pp->dev, txq->id); 1797c5aff182SThomas Petazzoni int tx_done; 1798c5aff182SThomas Petazzoni 1799c5aff182SThomas Petazzoni tx_done = mvneta_txq_sent_desc_proc(pp, txq); 1800cd713199SArnaud Ebalard if (!tx_done) 1801cd713199SArnaud Ebalard return; 1802cd713199SArnaud Ebalard 1803a29b6235SMarcin Wojtas mvneta_txq_bufs_free(pp, txq, tx_done, nq); 1804c5aff182SThomas Petazzoni 1805c5aff182SThomas Petazzoni txq->count -= tx_done; 1806c5aff182SThomas Petazzoni 1807c5aff182SThomas Petazzoni if (netif_tx_queue_stopped(nq)) { 18088eef5f97SEzequiel Garcia if (txq->count <= txq->tx_wake_threshold) 1809c5aff182SThomas Petazzoni netif_tx_wake_queue(nq); 1810c5aff182SThomas Petazzoni } 1811c5aff182SThomas Petazzoni } 1812c5aff182SThomas Petazzoni 1813dc35a10fSMarcin Wojtas /* Refill processing for SW buffer management */ 18147e47fd84SGregory CLEMENT /* Allocate page per descriptor */ 1815c5aff182SThomas Petazzoni static int mvneta_rx_refill(struct mvneta_port *pp, 1816f88bee1cSGregory CLEMENT struct mvneta_rx_desc *rx_desc, 18177e47fd84SGregory CLEMENT struct mvneta_rx_queue *rxq, 18187e47fd84SGregory CLEMENT gfp_t gfp_mask) 1819c5aff182SThomas Petazzoni { 1820568a3fa2SLorenzo Bianconi enum dma_data_direction dma_dir; 1821c5aff182SThomas Petazzoni dma_addr_t phys_addr; 18227e47fd84SGregory CLEMENT struct page *page; 1823c5aff182SThomas Petazzoni 1824568a3fa2SLorenzo Bianconi page = page_pool_alloc_pages(rxq->page_pool, 1825568a3fa2SLorenzo Bianconi gfp_mask | __GFP_NOWARN); 18267e47fd84SGregory CLEMENT if (!page) 1827c5aff182SThomas Petazzoni return -ENOMEM; 1828c5aff182SThomas Petazzoni 1829568a3fa2SLorenzo Bianconi phys_addr = page_pool_get_dma_addr(page) + pp->rx_offset_correction; 1830568a3fa2SLorenzo Bianconi dma_dir = page_pool_get_dma_dir(rxq->page_pool); 1831568a3fa2SLorenzo Bianconi dma_sync_single_for_device(pp->dev->dev.parent, phys_addr, 1832568a3fa2SLorenzo Bianconi PAGE_SIZE, dma_dir); 18337e47fd84SGregory CLEMENT mvneta_rx_desc_fill(rx_desc, phys_addr, page, rxq); 1834568a3fa2SLorenzo Bianconi 1835c5aff182SThomas Petazzoni return 0; 1836c5aff182SThomas Petazzoni } 1837c5aff182SThomas Petazzoni 1838c5aff182SThomas Petazzoni /* Handle tx checksum */ 1839c5aff182SThomas Petazzoni static u32 mvneta_skb_tx_csum(struct mvneta_port *pp, struct sk_buff *skb) 1840c5aff182SThomas Petazzoni { 1841c5aff182SThomas Petazzoni if (skb->ip_summed == CHECKSUM_PARTIAL) { 1842c5aff182SThomas Petazzoni int ip_hdr_len = 0; 1843817dbfa5SVlad Yasevich __be16 l3_proto = vlan_get_protocol(skb); 1844c5aff182SThomas Petazzoni u8 l4_proto; 1845c5aff182SThomas Petazzoni 1846817dbfa5SVlad Yasevich if (l3_proto == htons(ETH_P_IP)) { 1847c5aff182SThomas Petazzoni struct iphdr *ip4h = ip_hdr(skb); 1848c5aff182SThomas Petazzoni 1849c5aff182SThomas Petazzoni /* Calculate IPv4 checksum and L4 checksum */ 1850c5aff182SThomas Petazzoni ip_hdr_len = ip4h->ihl; 1851c5aff182SThomas Petazzoni l4_proto = ip4h->protocol; 1852817dbfa5SVlad Yasevich } else if (l3_proto == htons(ETH_P_IPV6)) { 1853c5aff182SThomas Petazzoni struct ipv6hdr *ip6h = ipv6_hdr(skb); 1854c5aff182SThomas Petazzoni 1855c5aff182SThomas Petazzoni /* Read l4_protocol from one of IPv6 extra headers */ 1856c5aff182SThomas Petazzoni if (skb_network_header_len(skb) > 0) 1857c5aff182SThomas Petazzoni ip_hdr_len = (skb_network_header_len(skb) >> 2); 1858c5aff182SThomas Petazzoni l4_proto = ip6h->nexthdr; 1859c5aff182SThomas Petazzoni } else 1860c5aff182SThomas Petazzoni return MVNETA_TX_L4_CSUM_NOT; 1861c5aff182SThomas Petazzoni 1862c5aff182SThomas Petazzoni return mvneta_txq_desc_csum(skb_network_offset(skb), 1863817dbfa5SVlad Yasevich l3_proto, ip_hdr_len, l4_proto); 1864c5aff182SThomas Petazzoni } 1865c5aff182SThomas Petazzoni 1866c5aff182SThomas Petazzoni return MVNETA_TX_L4_CSUM_NOT; 1867c5aff182SThomas Petazzoni } 1868c5aff182SThomas Petazzoni 1869c5aff182SThomas Petazzoni /* Drop packets received by the RXQ and free buffers */ 1870c5aff182SThomas Petazzoni static void mvneta_rxq_drop_pkts(struct mvneta_port *pp, 1871c5aff182SThomas Petazzoni struct mvneta_rx_queue *rxq) 1872c5aff182SThomas Petazzoni { 1873c5aff182SThomas Petazzoni int rx_done, i; 1874c5aff182SThomas Petazzoni 1875c5aff182SThomas Petazzoni rx_done = mvneta_rxq_busy_desc_num_get(pp, rxq); 1876dc35a10fSMarcin Wojtas if (rx_done) 1877dc35a10fSMarcin Wojtas mvneta_rxq_desc_num_update(pp, rxq, rx_done, rx_done); 1878dc35a10fSMarcin Wojtas 1879dc35a10fSMarcin Wojtas if (pp->bm_priv) { 1880dc35a10fSMarcin Wojtas for (i = 0; i < rx_done; i++) { 1881dc35a10fSMarcin Wojtas struct mvneta_rx_desc *rx_desc = 1882dc35a10fSMarcin Wojtas mvneta_rxq_next_desc_get(rxq); 1883dc35a10fSMarcin Wojtas u8 pool_id = MVNETA_RX_GET_BM_POOL_ID(rx_desc); 1884dc35a10fSMarcin Wojtas struct mvneta_bm_pool *bm_pool; 1885dc35a10fSMarcin Wojtas 1886dc35a10fSMarcin Wojtas bm_pool = &pp->bm_priv->bm_pools[pool_id]; 1887dc35a10fSMarcin Wojtas /* Return dropped buffer to the pool */ 1888dc35a10fSMarcin Wojtas mvneta_bm_pool_put_bp(pp->bm_priv, bm_pool, 1889dc35a10fSMarcin Wojtas rx_desc->buf_phys_addr); 1890dc35a10fSMarcin Wojtas } 1891dc35a10fSMarcin Wojtas return; 1892dc35a10fSMarcin Wojtas } 1893dc35a10fSMarcin Wojtas 1894c5aff182SThomas Petazzoni for (i = 0; i < rxq->size; i++) { 1895c5aff182SThomas Petazzoni struct mvneta_rx_desc *rx_desc = rxq->descs + i; 1896f88bee1cSGregory CLEMENT void *data = rxq->buf_virt_addr[i]; 1897562e2f46SYelena Krivosheev if (!data || !(rx_desc->buf_phys_addr)) 1898562e2f46SYelena Krivosheev continue; 1899c5aff182SThomas Petazzoni 1900568a3fa2SLorenzo Bianconi page_pool_put_page(rxq->page_pool, data, false); 1901dc35a10fSMarcin Wojtas } 1902568a3fa2SLorenzo Bianconi if (xdp_rxq_info_is_reg(&rxq->xdp_rxq)) 1903568a3fa2SLorenzo Bianconi xdp_rxq_info_unreg(&rxq->xdp_rxq); 1904568a3fa2SLorenzo Bianconi page_pool_destroy(rxq->page_pool); 1905568a3fa2SLorenzo Bianconi rxq->page_pool = NULL; 1906c5aff182SThomas Petazzoni } 1907c5aff182SThomas Petazzoni 1908ff519e2aSLorenzo Bianconi static void 1909ff519e2aSLorenzo Bianconi mvneta_update_stats(struct mvneta_port *pp, u32 pkts, 1910ff519e2aSLorenzo Bianconi u32 len, bool tx) 1911ff519e2aSLorenzo Bianconi { 1912ff519e2aSLorenzo Bianconi struct mvneta_pcpu_stats *stats = this_cpu_ptr(pp->stats); 1913ff519e2aSLorenzo Bianconi 1914ff519e2aSLorenzo Bianconi u64_stats_update_begin(&stats->syncp); 1915ff519e2aSLorenzo Bianconi if (tx) { 1916ff519e2aSLorenzo Bianconi stats->tx_packets += pkts; 1917ff519e2aSLorenzo Bianconi stats->tx_bytes += len; 1918ff519e2aSLorenzo Bianconi } else { 1919ff519e2aSLorenzo Bianconi stats->rx_packets += pkts; 1920ff519e2aSLorenzo Bianconi stats->rx_bytes += len; 1921ff519e2aSLorenzo Bianconi } 1922ff519e2aSLorenzo Bianconi u64_stats_update_end(&stats->syncp); 1923ff519e2aSLorenzo Bianconi } 1924ff519e2aSLorenzo Bianconi 1925562e2f46SYelena Krivosheev static inline 1926562e2f46SYelena Krivosheev int mvneta_rx_refill_queue(struct mvneta_port *pp, struct mvneta_rx_queue *rxq) 1927562e2f46SYelena Krivosheev { 1928562e2f46SYelena Krivosheev struct mvneta_rx_desc *rx_desc; 1929562e2f46SYelena Krivosheev int curr_desc = rxq->first_to_refill; 1930562e2f46SYelena Krivosheev int i; 1931562e2f46SYelena Krivosheev 1932562e2f46SYelena Krivosheev for (i = 0; (i < rxq->refill_num) && (i < 64); i++) { 1933562e2f46SYelena Krivosheev rx_desc = rxq->descs + curr_desc; 1934562e2f46SYelena Krivosheev if (!(rx_desc->buf_phys_addr)) { 1935562e2f46SYelena Krivosheev if (mvneta_rx_refill(pp, rx_desc, rxq, GFP_ATOMIC)) { 1936562e2f46SYelena Krivosheev pr_err("Can't refill queue %d. Done %d from %d\n", 1937562e2f46SYelena Krivosheev rxq->id, i, rxq->refill_num); 1938562e2f46SYelena Krivosheev rxq->refill_err++; 1939562e2f46SYelena Krivosheev break; 1940562e2f46SYelena Krivosheev } 1941562e2f46SYelena Krivosheev } 1942562e2f46SYelena Krivosheev curr_desc = MVNETA_QUEUE_NEXT_DESC(rxq, curr_desc); 1943562e2f46SYelena Krivosheev } 1944562e2f46SYelena Krivosheev rxq->refill_num -= i; 1945562e2f46SYelena Krivosheev rxq->first_to_refill = curr_desc; 1946562e2f46SYelena Krivosheev 1947562e2f46SYelena Krivosheev return i; 1948562e2f46SYelena Krivosheev } 1949562e2f46SYelena Krivosheev 1950dc35a10fSMarcin Wojtas /* Main rx processing when using software buffer management */ 19517a86f05fSAndrew Lunn static int mvneta_rx_swbm(struct napi_struct *napi, 1952562e2f46SYelena Krivosheev struct mvneta_port *pp, int budget, 1953c5aff182SThomas Petazzoni struct mvneta_rx_queue *rxq) 1954c5aff182SThomas Petazzoni { 1955c5aff182SThomas Petazzoni struct net_device *dev = pp->dev; 1956562e2f46SYelena Krivosheev int rx_todo, rx_proc; 1957562e2f46SYelena Krivosheev int refill = 0; 1958dc4277ddSwilly tarreau u32 rcvd_pkts = 0; 1959dc4277ddSwilly tarreau u32 rcvd_bytes = 0; 1960c5aff182SThomas Petazzoni 1961c5aff182SThomas Petazzoni /* Get number of received packets */ 1962562e2f46SYelena Krivosheev rx_todo = mvneta_rxq_busy_desc_num_get(pp, rxq); 1963562e2f46SYelena Krivosheev rx_proc = 0; 1964c5aff182SThomas Petazzoni 1965c5aff182SThomas Petazzoni /* Fairness NAPI loop */ 1966562e2f46SYelena Krivosheev while ((rcvd_pkts < budget) && (rx_proc < rx_todo)) { 1967c5aff182SThomas Petazzoni struct mvneta_rx_desc *rx_desc = mvneta_rxq_next_desc_get(rxq); 19688ec2cd48Swilly tarreau unsigned char *data; 19697e47fd84SGregory CLEMENT struct page *page; 1970daf158d0SSimon Guinot dma_addr_t phys_addr; 1971562e2f46SYelena Krivosheev u32 rx_status, index; 1972562e2f46SYelena Krivosheev int rx_bytes, skb_size, copy_size; 1973562e2f46SYelena Krivosheev int frag_num, frag_size, frag_offset; 1974c5aff182SThomas Petazzoni 1975f88bee1cSGregory CLEMENT index = rx_desc - rxq->descs; 19767e47fd84SGregory CLEMENT page = (struct page *)rxq->buf_virt_addr[index]; 19777e47fd84SGregory CLEMENT data = page_address(page); 19787e47fd84SGregory CLEMENT /* Prefetch header */ 19797e47fd84SGregory CLEMENT prefetch(data); 1980c5aff182SThomas Petazzoni 1981562e2f46SYelena Krivosheev phys_addr = rx_desc->buf_phys_addr; 1982562e2f46SYelena Krivosheev rx_status = rx_desc->status; 1983562e2f46SYelena Krivosheev rx_proc++; 1984562e2f46SYelena Krivosheev rxq->refill_num++; 1985562e2f46SYelena Krivosheev 1986562e2f46SYelena Krivosheev if (rx_status & MVNETA_RXD_FIRST_DESC) { 1987562e2f46SYelena Krivosheev /* Check errors only for FIRST descriptor */ 1988562e2f46SYelena Krivosheev if (rx_status & MVNETA_RXD_ERR_SUMMARY) { 19892eecb2e0SYelena Krivosheev mvneta_rx_error(pp, rx_desc); 1990c5aff182SThomas Petazzoni dev->stats.rx_errors++; 19918ec2cd48Swilly tarreau /* leave the descriptor untouched */ 1992c5aff182SThomas Petazzoni continue; 1993c5aff182SThomas Petazzoni } 1994562e2f46SYelena Krivosheev rx_bytes = rx_desc->data_size - 1995562e2f46SYelena Krivosheev (ETH_FCS_LEN + MVNETA_MH_SIZE); 1996c5aff182SThomas Petazzoni 1997562e2f46SYelena Krivosheev /* Allocate small skb for each new packet */ 1998562e2f46SYelena Krivosheev skb_size = max(rx_copybreak, rx_header_size); 1999562e2f46SYelena Krivosheev rxq->skb = netdev_alloc_skb_ip_align(dev, skb_size); 2000562e2f46SYelena Krivosheev if (unlikely(!rxq->skb)) { 200117a96da6SGregory CLEMENT netdev_err(dev, 200217a96da6SGregory CLEMENT "Can't allocate skb on queue %d\n", 200317a96da6SGregory CLEMENT rxq->id); 2004562e2f46SYelena Krivosheev dev->stats.rx_dropped++; 200517a96da6SGregory CLEMENT rxq->skb_alloc_err++; 2006f19fadfcSwilly tarreau continue; 2007f19fadfcSwilly tarreau } 2008562e2f46SYelena Krivosheev copy_size = min(skb_size, rx_bytes); 2009f19fadfcSwilly tarreau 2010562e2f46SYelena Krivosheev /* Copy data from buffer to SKB, skip Marvell header */ 2011562e2f46SYelena Krivosheev memcpy(rxq->skb->data, data + MVNETA_MH_SIZE, 2012562e2f46SYelena Krivosheev copy_size); 2013562e2f46SYelena Krivosheev skb_put(rxq->skb, copy_size); 2014562e2f46SYelena Krivosheev rxq->left_size = rx_bytes - copy_size; 2015a84e3289SSimon Guinot 2016562e2f46SYelena Krivosheev mvneta_rx_csum(pp, rx_status, rxq->skb); 2017562e2f46SYelena Krivosheev if (rxq->left_size == 0) { 2018562e2f46SYelena Krivosheev int size = copy_size + MVNETA_MH_SIZE; 2019dc35a10fSMarcin Wojtas 2020562e2f46SYelena Krivosheev dma_sync_single_range_for_cpu(dev->dev.parent, 2021562e2f46SYelena Krivosheev phys_addr, 0, 2022562e2f46SYelena Krivosheev size, 2023dc35a10fSMarcin Wojtas DMA_FROM_DEVICE); 2024c5aff182SThomas Petazzoni 2025562e2f46SYelena Krivosheev /* leave the descriptor and buffer untouched */ 2026562e2f46SYelena Krivosheev } else { 2027562e2f46SYelena Krivosheev /* refill descriptor with new buffer later */ 2028562e2f46SYelena Krivosheev rx_desc->buf_phys_addr = 0; 202926c17a17SMarcin Wojtas 2030562e2f46SYelena Krivosheev frag_num = 0; 2031562e2f46SYelena Krivosheev frag_offset = copy_size + MVNETA_MH_SIZE; 2032562e2f46SYelena Krivosheev frag_size = min(rxq->left_size, 2033562e2f46SYelena Krivosheev (int)(PAGE_SIZE - frag_offset)); 2034562e2f46SYelena Krivosheev skb_add_rx_frag(rxq->skb, frag_num, page, 2035562e2f46SYelena Krivosheev frag_offset, frag_size, 2036562e2f46SYelena Krivosheev PAGE_SIZE); 2037568a3fa2SLorenzo Bianconi page_pool_release_page(rxq->page_pool, page); 2038562e2f46SYelena Krivosheev rxq->left_size -= frag_size; 2039562e2f46SYelena Krivosheev } 2040562e2f46SYelena Krivosheev } else { 2041562e2f46SYelena Krivosheev /* Middle or Last descriptor */ 2042562e2f46SYelena Krivosheev if (unlikely(!rxq->skb)) { 2043562e2f46SYelena Krivosheev pr_debug("no skb for rx_status 0x%x\n", 2044562e2f46SYelena Krivosheev rx_status); 2045562e2f46SYelena Krivosheev continue; 2046562e2f46SYelena Krivosheev } 2047562e2f46SYelena Krivosheev if (!rxq->left_size) { 2048562e2f46SYelena Krivosheev /* last descriptor has only FCS */ 2049562e2f46SYelena Krivosheev /* and can be discarded */ 2050562e2f46SYelena Krivosheev dma_sync_single_range_for_cpu(dev->dev.parent, 2051562e2f46SYelena Krivosheev phys_addr, 0, 2052562e2f46SYelena Krivosheev ETH_FCS_LEN, 2053562e2f46SYelena Krivosheev DMA_FROM_DEVICE); 2054562e2f46SYelena Krivosheev /* leave the descriptor and buffer untouched */ 2055562e2f46SYelena Krivosheev } else { 2056562e2f46SYelena Krivosheev /* refill descriptor with new buffer later */ 2057562e2f46SYelena Krivosheev rx_desc->buf_phys_addr = 0; 2058562e2f46SYelena Krivosheev 2059562e2f46SYelena Krivosheev frag_num = skb_shinfo(rxq->skb)->nr_frags; 2060562e2f46SYelena Krivosheev frag_offset = 0; 2061562e2f46SYelena Krivosheev frag_size = min(rxq->left_size, 2062562e2f46SYelena Krivosheev (int)(PAGE_SIZE - frag_offset)); 2063562e2f46SYelena Krivosheev skb_add_rx_frag(rxq->skb, frag_num, page, 2064562e2f46SYelena Krivosheev frag_offset, frag_size, 2065562e2f46SYelena Krivosheev PAGE_SIZE); 2066562e2f46SYelena Krivosheev 2067568a3fa2SLorenzo Bianconi page_pool_release_page(rxq->page_pool, page); 2068562e2f46SYelena Krivosheev rxq->left_size -= frag_size; 2069562e2f46SYelena Krivosheev } 2070562e2f46SYelena Krivosheev } /* Middle or Last descriptor */ 2071562e2f46SYelena Krivosheev 2072562e2f46SYelena Krivosheev if (!(rx_status & MVNETA_RXD_LAST_DESC)) 2073562e2f46SYelena Krivosheev /* no last descriptor this time */ 2074562e2f46SYelena Krivosheev continue; 2075562e2f46SYelena Krivosheev 2076562e2f46SYelena Krivosheev if (rxq->left_size) { 2077562e2f46SYelena Krivosheev pr_err("get last desc, but left_size (%d) != 0\n", 2078562e2f46SYelena Krivosheev rxq->left_size); 2079562e2f46SYelena Krivosheev dev_kfree_skb_any(rxq->skb); 2080562e2f46SYelena Krivosheev rxq->left_size = 0; 2081562e2f46SYelena Krivosheev rxq->skb = NULL; 2082562e2f46SYelena Krivosheev continue; 2083562e2f46SYelena Krivosheev } 2084dc4277ddSwilly tarreau rcvd_pkts++; 2085562e2f46SYelena Krivosheev rcvd_bytes += rxq->skb->len; 2086c5aff182SThomas Petazzoni 2087c5aff182SThomas Petazzoni /* Linux processing */ 2088562e2f46SYelena Krivosheev rxq->skb->protocol = eth_type_trans(rxq->skb, dev); 2089c5aff182SThomas Petazzoni 2090562e2f46SYelena Krivosheev napi_gro_receive(napi, rxq->skb); 2091c5aff182SThomas Petazzoni 2092562e2f46SYelena Krivosheev /* clean uncomplete skb pointer in queue */ 2093562e2f46SYelena Krivosheev rxq->skb = NULL; 2094562e2f46SYelena Krivosheev rxq->left_size = 0; 2095c5aff182SThomas Petazzoni } 2096c5aff182SThomas Petazzoni 2097ff519e2aSLorenzo Bianconi if (rcvd_pkts) 2098ff519e2aSLorenzo Bianconi mvneta_update_stats(pp, rcvd_pkts, rcvd_bytes, false); 2099dc4277ddSwilly tarreau 2100562e2f46SYelena Krivosheev /* return some buffers to hardware queue, one at a time is too slow */ 2101562e2f46SYelena Krivosheev refill = mvneta_rx_refill_queue(pp, rxq); 2102c5aff182SThomas Petazzoni 2103562e2f46SYelena Krivosheev /* Update rxq management counters */ 2104562e2f46SYelena Krivosheev mvneta_rxq_desc_num_update(pp, rxq, rx_proc, refill); 2105562e2f46SYelena Krivosheev 2106562e2f46SYelena Krivosheev return rcvd_pkts; 2107c5aff182SThomas Petazzoni } 2108c5aff182SThomas Petazzoni 2109dc35a10fSMarcin Wojtas /* Main rx processing when using hardware buffer management */ 21107a86f05fSAndrew Lunn static int mvneta_rx_hwbm(struct napi_struct *napi, 21117a86f05fSAndrew Lunn struct mvneta_port *pp, int rx_todo, 2112dc35a10fSMarcin Wojtas struct mvneta_rx_queue *rxq) 2113dc35a10fSMarcin Wojtas { 2114dc35a10fSMarcin Wojtas struct net_device *dev = pp->dev; 2115dc35a10fSMarcin Wojtas int rx_done; 2116dc35a10fSMarcin Wojtas u32 rcvd_pkts = 0; 2117dc35a10fSMarcin Wojtas u32 rcvd_bytes = 0; 2118dc35a10fSMarcin Wojtas 2119dc35a10fSMarcin Wojtas /* Get number of received packets */ 2120dc35a10fSMarcin Wojtas rx_done = mvneta_rxq_busy_desc_num_get(pp, rxq); 2121dc35a10fSMarcin Wojtas 2122dc35a10fSMarcin Wojtas if (rx_todo > rx_done) 2123dc35a10fSMarcin Wojtas rx_todo = rx_done; 2124dc35a10fSMarcin Wojtas 2125dc35a10fSMarcin Wojtas rx_done = 0; 2126dc35a10fSMarcin Wojtas 2127dc35a10fSMarcin Wojtas /* Fairness NAPI loop */ 2128dc35a10fSMarcin Wojtas while (rx_done < rx_todo) { 2129dc35a10fSMarcin Wojtas struct mvneta_rx_desc *rx_desc = mvneta_rxq_next_desc_get(rxq); 2130dc35a10fSMarcin Wojtas struct mvneta_bm_pool *bm_pool = NULL; 2131dc35a10fSMarcin Wojtas struct sk_buff *skb; 2132dc35a10fSMarcin Wojtas unsigned char *data; 2133dc35a10fSMarcin Wojtas dma_addr_t phys_addr; 2134dc35a10fSMarcin Wojtas u32 rx_status, frag_size; 2135dc35a10fSMarcin Wojtas int rx_bytes, err; 2136dc35a10fSMarcin Wojtas u8 pool_id; 2137dc35a10fSMarcin Wojtas 2138dc35a10fSMarcin Wojtas rx_done++; 2139dc35a10fSMarcin Wojtas rx_status = rx_desc->status; 2140dc35a10fSMarcin Wojtas rx_bytes = rx_desc->data_size - (ETH_FCS_LEN + MVNETA_MH_SIZE); 2141f88bee1cSGregory CLEMENT data = (u8 *)(uintptr_t)rx_desc->buf_cookie; 2142dc35a10fSMarcin Wojtas phys_addr = rx_desc->buf_phys_addr; 2143dc35a10fSMarcin Wojtas pool_id = MVNETA_RX_GET_BM_POOL_ID(rx_desc); 2144dc35a10fSMarcin Wojtas bm_pool = &pp->bm_priv->bm_pools[pool_id]; 2145dc35a10fSMarcin Wojtas 2146dc35a10fSMarcin Wojtas if (!mvneta_rxq_desc_is_first_last(rx_status) || 2147dc35a10fSMarcin Wojtas (rx_status & MVNETA_RXD_ERR_SUMMARY)) { 2148dc35a10fSMarcin Wojtas err_drop_frame_ret_pool: 2149dc35a10fSMarcin Wojtas /* Return the buffer to the pool */ 2150dc35a10fSMarcin Wojtas mvneta_bm_pool_put_bp(pp->bm_priv, bm_pool, 2151dc35a10fSMarcin Wojtas rx_desc->buf_phys_addr); 2152dc35a10fSMarcin Wojtas err_drop_frame: 2153dc35a10fSMarcin Wojtas dev->stats.rx_errors++; 2154dc35a10fSMarcin Wojtas mvneta_rx_error(pp, rx_desc); 2155dc35a10fSMarcin Wojtas /* leave the descriptor untouched */ 2156dc35a10fSMarcin Wojtas continue; 2157dc35a10fSMarcin Wojtas } 2158dc35a10fSMarcin Wojtas 2159dc35a10fSMarcin Wojtas if (rx_bytes <= rx_copybreak) { 2160dc35a10fSMarcin Wojtas /* better copy a small frame and not unmap the DMA region */ 2161dc35a10fSMarcin Wojtas skb = netdev_alloc_skb_ip_align(dev, rx_bytes); 2162dc35a10fSMarcin Wojtas if (unlikely(!skb)) 2163dc35a10fSMarcin Wojtas goto err_drop_frame_ret_pool; 2164dc35a10fSMarcin Wojtas 2165a8fef9baSRussell King dma_sync_single_range_for_cpu(&pp->bm_priv->pdev->dev, 2166dc35a10fSMarcin Wojtas rx_desc->buf_phys_addr, 2167dc35a10fSMarcin Wojtas MVNETA_MH_SIZE + NET_SKB_PAD, 2168dc35a10fSMarcin Wojtas rx_bytes, 2169dc35a10fSMarcin Wojtas DMA_FROM_DEVICE); 217059ae1d12SJohannes Berg skb_put_data(skb, data + MVNETA_MH_SIZE + NET_SKB_PAD, 2171dc35a10fSMarcin Wojtas rx_bytes); 2172dc35a10fSMarcin Wojtas 2173dc35a10fSMarcin Wojtas skb->protocol = eth_type_trans(skb, dev); 2174dc35a10fSMarcin Wojtas mvneta_rx_csum(pp, rx_status, skb); 21757a86f05fSAndrew Lunn napi_gro_receive(napi, skb); 2176dc35a10fSMarcin Wojtas 2177dc35a10fSMarcin Wojtas rcvd_pkts++; 2178dc35a10fSMarcin Wojtas rcvd_bytes += rx_bytes; 2179dc35a10fSMarcin Wojtas 2180dc35a10fSMarcin Wojtas /* Return the buffer to the pool */ 2181dc35a10fSMarcin Wojtas mvneta_bm_pool_put_bp(pp->bm_priv, bm_pool, 2182dc35a10fSMarcin Wojtas rx_desc->buf_phys_addr); 2183dc35a10fSMarcin Wojtas 2184dc35a10fSMarcin Wojtas /* leave the descriptor and buffer untouched */ 2185dc35a10fSMarcin Wojtas continue; 2186dc35a10fSMarcin Wojtas } 2187dc35a10fSMarcin Wojtas 2188dc35a10fSMarcin Wojtas /* Refill processing */ 2189baa11ebcSGregory CLEMENT err = hwbm_pool_refill(&bm_pool->hwbm_pool, GFP_ATOMIC); 2190dc35a10fSMarcin Wojtas if (err) { 2191dc35a10fSMarcin Wojtas netdev_err(dev, "Linux processing - Can't refill\n"); 219217a96da6SGregory CLEMENT rxq->refill_err++; 2193dc35a10fSMarcin Wojtas goto err_drop_frame_ret_pool; 2194dc35a10fSMarcin Wojtas } 2195dc35a10fSMarcin Wojtas 2196baa11ebcSGregory CLEMENT frag_size = bm_pool->hwbm_pool.frag_size; 2197dc35a10fSMarcin Wojtas 2198dc35a10fSMarcin Wojtas skb = build_skb(data, frag_size > PAGE_SIZE ? 0 : frag_size); 2199dc35a10fSMarcin Wojtas 2200dc35a10fSMarcin Wojtas /* After refill old buffer has to be unmapped regardless 2201dc35a10fSMarcin Wojtas * the skb is successfully built or not. 2202dc35a10fSMarcin Wojtas */ 2203dc35a10fSMarcin Wojtas dma_unmap_single(&pp->bm_priv->pdev->dev, phys_addr, 2204dc35a10fSMarcin Wojtas bm_pool->buf_size, DMA_FROM_DEVICE); 2205dc35a10fSMarcin Wojtas if (!skb) 2206dc35a10fSMarcin Wojtas goto err_drop_frame; 2207dc35a10fSMarcin Wojtas 2208dc35a10fSMarcin Wojtas rcvd_pkts++; 2209dc35a10fSMarcin Wojtas rcvd_bytes += rx_bytes; 2210dc35a10fSMarcin Wojtas 2211dc35a10fSMarcin Wojtas /* Linux processing */ 2212dc35a10fSMarcin Wojtas skb_reserve(skb, MVNETA_MH_SIZE + NET_SKB_PAD); 2213dc35a10fSMarcin Wojtas skb_put(skb, rx_bytes); 2214dc35a10fSMarcin Wojtas 2215dc35a10fSMarcin Wojtas skb->protocol = eth_type_trans(skb, dev); 2216dc35a10fSMarcin Wojtas 2217dc35a10fSMarcin Wojtas mvneta_rx_csum(pp, rx_status, skb); 2218dc35a10fSMarcin Wojtas 22197a86f05fSAndrew Lunn napi_gro_receive(napi, skb); 2220dc35a10fSMarcin Wojtas } 2221dc35a10fSMarcin Wojtas 2222ff519e2aSLorenzo Bianconi if (rcvd_pkts) 2223ff519e2aSLorenzo Bianconi mvneta_update_stats(pp, rcvd_pkts, rcvd_bytes, false); 2224dc35a10fSMarcin Wojtas 2225dc35a10fSMarcin Wojtas /* Update rxq management counters */ 2226dc35a10fSMarcin Wojtas mvneta_rxq_desc_num_update(pp, rxq, rx_done, rx_done); 2227dc35a10fSMarcin Wojtas 2228dc35a10fSMarcin Wojtas return rx_done; 2229dc35a10fSMarcin Wojtas } 2230dc35a10fSMarcin Wojtas 22312adb719dSEzequiel Garcia static inline void 22322adb719dSEzequiel Garcia mvneta_tso_put_hdr(struct sk_buff *skb, 22332adb719dSEzequiel Garcia struct mvneta_port *pp, struct mvneta_tx_queue *txq) 22342adb719dSEzequiel Garcia { 22352adb719dSEzequiel Garcia struct mvneta_tx_desc *tx_desc; 22362adb719dSEzequiel Garcia int hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb); 22372adb719dSEzequiel Garcia 22382adb719dSEzequiel Garcia txq->tx_skb[txq->txq_put_index] = NULL; 22392adb719dSEzequiel Garcia tx_desc = mvneta_txq_next_desc_get(txq); 22402adb719dSEzequiel Garcia tx_desc->data_size = hdr_len; 22412adb719dSEzequiel Garcia tx_desc->command = mvneta_skb_tx_csum(pp, skb); 22422adb719dSEzequiel Garcia tx_desc->command |= MVNETA_TXD_F_DESC; 22432adb719dSEzequiel Garcia tx_desc->buf_phys_addr = txq->tso_hdrs_phys + 22442adb719dSEzequiel Garcia txq->txq_put_index * TSO_HEADER_SIZE; 22452adb719dSEzequiel Garcia mvneta_txq_inc_put(txq); 22462adb719dSEzequiel Garcia } 22472adb719dSEzequiel Garcia 22482adb719dSEzequiel Garcia static inline int 22492adb719dSEzequiel Garcia mvneta_tso_put_data(struct net_device *dev, struct mvneta_tx_queue *txq, 22502adb719dSEzequiel Garcia struct sk_buff *skb, char *data, int size, 22512adb719dSEzequiel Garcia bool last_tcp, bool is_last) 22522adb719dSEzequiel Garcia { 22532adb719dSEzequiel Garcia struct mvneta_tx_desc *tx_desc; 22542adb719dSEzequiel Garcia 22552adb719dSEzequiel Garcia tx_desc = mvneta_txq_next_desc_get(txq); 22562adb719dSEzequiel Garcia tx_desc->data_size = size; 22572adb719dSEzequiel Garcia tx_desc->buf_phys_addr = dma_map_single(dev->dev.parent, data, 22582adb719dSEzequiel Garcia size, DMA_TO_DEVICE); 22592adb719dSEzequiel Garcia if (unlikely(dma_mapping_error(dev->dev.parent, 22602adb719dSEzequiel Garcia tx_desc->buf_phys_addr))) { 22612adb719dSEzequiel Garcia mvneta_txq_desc_put(txq); 22622adb719dSEzequiel Garcia return -ENOMEM; 22632adb719dSEzequiel Garcia } 22642adb719dSEzequiel Garcia 22652adb719dSEzequiel Garcia tx_desc->command = 0; 22662adb719dSEzequiel Garcia txq->tx_skb[txq->txq_put_index] = NULL; 22672adb719dSEzequiel Garcia 22682adb719dSEzequiel Garcia if (last_tcp) { 22692adb719dSEzequiel Garcia /* last descriptor in the TCP packet */ 22702adb719dSEzequiel Garcia tx_desc->command = MVNETA_TXD_L_DESC; 22712adb719dSEzequiel Garcia 22722adb719dSEzequiel Garcia /* last descriptor in SKB */ 22732adb719dSEzequiel Garcia if (is_last) 22742adb719dSEzequiel Garcia txq->tx_skb[txq->txq_put_index] = skb; 22752adb719dSEzequiel Garcia } 22762adb719dSEzequiel Garcia mvneta_txq_inc_put(txq); 22772adb719dSEzequiel Garcia return 0; 22782adb719dSEzequiel Garcia } 22792adb719dSEzequiel Garcia 22802adb719dSEzequiel Garcia static int mvneta_tx_tso(struct sk_buff *skb, struct net_device *dev, 22812adb719dSEzequiel Garcia struct mvneta_tx_queue *txq) 22822adb719dSEzequiel Garcia { 22832adb719dSEzequiel Garcia int total_len, data_left; 22842adb719dSEzequiel Garcia int desc_count = 0; 22852adb719dSEzequiel Garcia struct mvneta_port *pp = netdev_priv(dev); 22862adb719dSEzequiel Garcia struct tso_t tso; 22872adb719dSEzequiel Garcia int hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb); 22882adb719dSEzequiel Garcia int i; 22892adb719dSEzequiel Garcia 22902adb719dSEzequiel Garcia /* Count needed descriptors */ 22912adb719dSEzequiel Garcia if ((txq->count + tso_count_descs(skb)) >= txq->size) 22922adb719dSEzequiel Garcia return 0; 22932adb719dSEzequiel Garcia 22942adb719dSEzequiel Garcia if (skb_headlen(skb) < (skb_transport_offset(skb) + tcp_hdrlen(skb))) { 22952adb719dSEzequiel Garcia pr_info("*** Is this even possible???!?!?\n"); 22962adb719dSEzequiel Garcia return 0; 22972adb719dSEzequiel Garcia } 22982adb719dSEzequiel Garcia 22992adb719dSEzequiel Garcia /* Initialize the TSO handler, and prepare the first payload */ 23002adb719dSEzequiel Garcia tso_start(skb, &tso); 23012adb719dSEzequiel Garcia 23022adb719dSEzequiel Garcia total_len = skb->len - hdr_len; 23032adb719dSEzequiel Garcia while (total_len > 0) { 23042adb719dSEzequiel Garcia char *hdr; 23052adb719dSEzequiel Garcia 23062adb719dSEzequiel Garcia data_left = min_t(int, skb_shinfo(skb)->gso_size, total_len); 23072adb719dSEzequiel Garcia total_len -= data_left; 23082adb719dSEzequiel Garcia desc_count++; 23092adb719dSEzequiel Garcia 23102adb719dSEzequiel Garcia /* prepare packet headers: MAC + IP + TCP */ 23112adb719dSEzequiel Garcia hdr = txq->tso_hdrs + txq->txq_put_index * TSO_HEADER_SIZE; 23122adb719dSEzequiel Garcia tso_build_hdr(skb, hdr, &tso, data_left, total_len == 0); 23132adb719dSEzequiel Garcia 23142adb719dSEzequiel Garcia mvneta_tso_put_hdr(skb, pp, txq); 23152adb719dSEzequiel Garcia 23162adb719dSEzequiel Garcia while (data_left > 0) { 23172adb719dSEzequiel Garcia int size; 23182adb719dSEzequiel Garcia desc_count++; 23192adb719dSEzequiel Garcia 23202adb719dSEzequiel Garcia size = min_t(int, tso.size, data_left); 23212adb719dSEzequiel Garcia 23222adb719dSEzequiel Garcia if (mvneta_tso_put_data(dev, txq, skb, 23232adb719dSEzequiel Garcia tso.data, size, 23242adb719dSEzequiel Garcia size == data_left, 23252adb719dSEzequiel Garcia total_len == 0)) 23262adb719dSEzequiel Garcia goto err_release; 23272adb719dSEzequiel Garcia data_left -= size; 23282adb719dSEzequiel Garcia 23292adb719dSEzequiel Garcia tso_build_data(skb, &tso, size); 23302adb719dSEzequiel Garcia } 23312adb719dSEzequiel Garcia } 23322adb719dSEzequiel Garcia 23332adb719dSEzequiel Garcia return desc_count; 23342adb719dSEzequiel Garcia 23352adb719dSEzequiel Garcia err_release: 23362adb719dSEzequiel Garcia /* Release all used data descriptors; header descriptors must not 23372adb719dSEzequiel Garcia * be DMA-unmapped. 23382adb719dSEzequiel Garcia */ 23392adb719dSEzequiel Garcia for (i = desc_count - 1; i >= 0; i--) { 23402adb719dSEzequiel Garcia struct mvneta_tx_desc *tx_desc = txq->descs + i; 23412e3173a3SEzequiel Garcia if (!IS_TSO_HEADER(txq, tx_desc->buf_phys_addr)) 23422adb719dSEzequiel Garcia dma_unmap_single(pp->dev->dev.parent, 23432adb719dSEzequiel Garcia tx_desc->buf_phys_addr, 23442adb719dSEzequiel Garcia tx_desc->data_size, 23452adb719dSEzequiel Garcia DMA_TO_DEVICE); 23462adb719dSEzequiel Garcia mvneta_txq_desc_put(txq); 23472adb719dSEzequiel Garcia } 23482adb719dSEzequiel Garcia return 0; 23492adb719dSEzequiel Garcia } 23502adb719dSEzequiel Garcia 2351c5aff182SThomas Petazzoni /* Handle tx fragmentation processing */ 2352c5aff182SThomas Petazzoni static int mvneta_tx_frag_process(struct mvneta_port *pp, struct sk_buff *skb, 2353c5aff182SThomas Petazzoni struct mvneta_tx_queue *txq) 2354c5aff182SThomas Petazzoni { 2355c5aff182SThomas Petazzoni struct mvneta_tx_desc *tx_desc; 23563d4ea02fSEzequiel Garcia int i, nr_frags = skb_shinfo(skb)->nr_frags; 2357c5aff182SThomas Petazzoni 23583d4ea02fSEzequiel Garcia for (i = 0; i < nr_frags; i++) { 2359c5aff182SThomas Petazzoni skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 2360d7840976SMatthew Wilcox (Oracle) void *addr = skb_frag_address(frag); 2361c5aff182SThomas Petazzoni 2362c5aff182SThomas Petazzoni tx_desc = mvneta_txq_next_desc_get(txq); 2363d7840976SMatthew Wilcox (Oracle) tx_desc->data_size = skb_frag_size(frag); 2364c5aff182SThomas Petazzoni 2365c5aff182SThomas Petazzoni tx_desc->buf_phys_addr = 2366c5aff182SThomas Petazzoni dma_map_single(pp->dev->dev.parent, addr, 2367c5aff182SThomas Petazzoni tx_desc->data_size, DMA_TO_DEVICE); 2368c5aff182SThomas Petazzoni 2369c5aff182SThomas Petazzoni if (dma_mapping_error(pp->dev->dev.parent, 2370c5aff182SThomas Petazzoni tx_desc->buf_phys_addr)) { 2371c5aff182SThomas Petazzoni mvneta_txq_desc_put(txq); 2372c5aff182SThomas Petazzoni goto error; 2373c5aff182SThomas Petazzoni } 2374c5aff182SThomas Petazzoni 23753d4ea02fSEzequiel Garcia if (i == nr_frags - 1) { 2376c5aff182SThomas Petazzoni /* Last descriptor */ 2377c5aff182SThomas Petazzoni tx_desc->command = MVNETA_TXD_L_DESC | MVNETA_TXD_Z_PAD; 2378c5aff182SThomas Petazzoni txq->tx_skb[txq->txq_put_index] = skb; 2379c5aff182SThomas Petazzoni } else { 2380c5aff182SThomas Petazzoni /* Descriptor in the middle: Not First, Not Last */ 2381c5aff182SThomas Petazzoni tx_desc->command = 0; 2382c5aff182SThomas Petazzoni txq->tx_skb[txq->txq_put_index] = NULL; 2383c5aff182SThomas Petazzoni } 23843d4ea02fSEzequiel Garcia mvneta_txq_inc_put(txq); 2385c5aff182SThomas Petazzoni } 2386c5aff182SThomas Petazzoni 2387c5aff182SThomas Petazzoni return 0; 2388c5aff182SThomas Petazzoni 2389c5aff182SThomas Petazzoni error: 2390c5aff182SThomas Petazzoni /* Release all descriptors that were used to map fragments of 23916a20c175SThomas Petazzoni * this packet, as well as the corresponding DMA mappings 23926a20c175SThomas Petazzoni */ 2393c5aff182SThomas Petazzoni for (i = i - 1; i >= 0; i--) { 2394c5aff182SThomas Petazzoni tx_desc = txq->descs + i; 2395c5aff182SThomas Petazzoni dma_unmap_single(pp->dev->dev.parent, 2396c5aff182SThomas Petazzoni tx_desc->buf_phys_addr, 2397c5aff182SThomas Petazzoni tx_desc->data_size, 2398c5aff182SThomas Petazzoni DMA_TO_DEVICE); 2399c5aff182SThomas Petazzoni mvneta_txq_desc_put(txq); 2400c5aff182SThomas Petazzoni } 2401c5aff182SThomas Petazzoni 2402c5aff182SThomas Petazzoni return -ENOMEM; 2403c5aff182SThomas Petazzoni } 2404c5aff182SThomas Petazzoni 2405c5aff182SThomas Petazzoni /* Main tx processing */ 2406f03508ceSYueHaibing static netdev_tx_t mvneta_tx(struct sk_buff *skb, struct net_device *dev) 2407c5aff182SThomas Petazzoni { 2408c5aff182SThomas Petazzoni struct mvneta_port *pp = netdev_priv(dev); 2409ee40a116SWilly Tarreau u16 txq_id = skb_get_queue_mapping(skb); 2410ee40a116SWilly Tarreau struct mvneta_tx_queue *txq = &pp->txqs[txq_id]; 2411c5aff182SThomas Petazzoni struct mvneta_tx_desc *tx_desc; 24125f478b41SEric Dumazet int len = skb->len; 2413c5aff182SThomas Petazzoni int frags = 0; 2414c5aff182SThomas Petazzoni u32 tx_cmd; 2415c5aff182SThomas Petazzoni 2416c5aff182SThomas Petazzoni if (!netif_running(dev)) 2417c5aff182SThomas Petazzoni goto out; 2418c5aff182SThomas Petazzoni 24192adb719dSEzequiel Garcia if (skb_is_gso(skb)) { 24202adb719dSEzequiel Garcia frags = mvneta_tx_tso(skb, dev, txq); 24212adb719dSEzequiel Garcia goto out; 24222adb719dSEzequiel Garcia } 24232adb719dSEzequiel Garcia 2424c5aff182SThomas Petazzoni frags = skb_shinfo(skb)->nr_frags + 1; 2425c5aff182SThomas Petazzoni 2426c5aff182SThomas Petazzoni /* Get a descriptor for the first part of the packet */ 2427c5aff182SThomas Petazzoni tx_desc = mvneta_txq_next_desc_get(txq); 2428c5aff182SThomas Petazzoni 2429c5aff182SThomas Petazzoni tx_cmd = mvneta_skb_tx_csum(pp, skb); 2430c5aff182SThomas Petazzoni 2431c5aff182SThomas Petazzoni tx_desc->data_size = skb_headlen(skb); 2432c5aff182SThomas Petazzoni 2433c5aff182SThomas Petazzoni tx_desc->buf_phys_addr = dma_map_single(dev->dev.parent, skb->data, 2434c5aff182SThomas Petazzoni tx_desc->data_size, 2435c5aff182SThomas Petazzoni DMA_TO_DEVICE); 2436c5aff182SThomas Petazzoni if (unlikely(dma_mapping_error(dev->dev.parent, 2437c5aff182SThomas Petazzoni tx_desc->buf_phys_addr))) { 2438c5aff182SThomas Petazzoni mvneta_txq_desc_put(txq); 2439c5aff182SThomas Petazzoni frags = 0; 2440c5aff182SThomas Petazzoni goto out; 2441c5aff182SThomas Petazzoni } 2442c5aff182SThomas Petazzoni 2443c5aff182SThomas Petazzoni if (frags == 1) { 2444c5aff182SThomas Petazzoni /* First and Last descriptor */ 2445c5aff182SThomas Petazzoni tx_cmd |= MVNETA_TXD_FLZ_DESC; 2446c5aff182SThomas Petazzoni tx_desc->command = tx_cmd; 2447c5aff182SThomas Petazzoni txq->tx_skb[txq->txq_put_index] = skb; 2448c5aff182SThomas Petazzoni mvneta_txq_inc_put(txq); 2449c5aff182SThomas Petazzoni } else { 2450c5aff182SThomas Petazzoni /* First but not Last */ 2451c5aff182SThomas Petazzoni tx_cmd |= MVNETA_TXD_F_DESC; 2452c5aff182SThomas Petazzoni txq->tx_skb[txq->txq_put_index] = NULL; 2453c5aff182SThomas Petazzoni mvneta_txq_inc_put(txq); 2454c5aff182SThomas Petazzoni tx_desc->command = tx_cmd; 2455c5aff182SThomas Petazzoni /* Continue with other skb fragments */ 2456c5aff182SThomas Petazzoni if (mvneta_tx_frag_process(pp, skb, txq)) { 2457c5aff182SThomas Petazzoni dma_unmap_single(dev->dev.parent, 2458c5aff182SThomas Petazzoni tx_desc->buf_phys_addr, 2459c5aff182SThomas Petazzoni tx_desc->data_size, 2460c5aff182SThomas Petazzoni DMA_TO_DEVICE); 2461c5aff182SThomas Petazzoni mvneta_txq_desc_put(txq); 2462c5aff182SThomas Petazzoni frags = 0; 2463c5aff182SThomas Petazzoni goto out; 2464c5aff182SThomas Petazzoni } 2465c5aff182SThomas Petazzoni } 2466c5aff182SThomas Petazzoni 2467e19d2ddaSEzequiel Garcia out: 2468e19d2ddaSEzequiel Garcia if (frags > 0) { 2469e19d2ddaSEzequiel Garcia struct netdev_queue *nq = netdev_get_tx_queue(dev, txq_id); 2470e19d2ddaSEzequiel Garcia 2471a29b6235SMarcin Wojtas netdev_tx_sent_queue(nq, len); 2472a29b6235SMarcin Wojtas 2473c5aff182SThomas Petazzoni txq->count += frags; 24748eef5f97SEzequiel Garcia if (txq->count >= txq->tx_stop_threshold) 2475c5aff182SThomas Petazzoni netif_tx_stop_queue(nq); 2476c5aff182SThomas Petazzoni 24776b16f9eeSFlorian Westphal if (!netdev_xmit_more() || netif_xmit_stopped(nq) || 24782a90f7e1SSimon Guinot txq->pending + frags > MVNETA_TXQ_DEC_SENT_MASK) 24792a90f7e1SSimon Guinot mvneta_txq_pend_desc_add(pp, txq, frags); 24802a90f7e1SSimon Guinot else 24812a90f7e1SSimon Guinot txq->pending += frags; 24822a90f7e1SSimon Guinot 2483ff519e2aSLorenzo Bianconi mvneta_update_stats(pp, 1, len, true); 2484c5aff182SThomas Petazzoni } else { 2485c5aff182SThomas Petazzoni dev->stats.tx_dropped++; 2486c5aff182SThomas Petazzoni dev_kfree_skb_any(skb); 2487c5aff182SThomas Petazzoni } 2488c5aff182SThomas Petazzoni 2489c5aff182SThomas Petazzoni return NETDEV_TX_OK; 2490c5aff182SThomas Petazzoni } 2491c5aff182SThomas Petazzoni 2492c5aff182SThomas Petazzoni 2493c5aff182SThomas Petazzoni /* Free tx resources, when resetting a port */ 2494c5aff182SThomas Petazzoni static void mvneta_txq_done_force(struct mvneta_port *pp, 2495c5aff182SThomas Petazzoni struct mvneta_tx_queue *txq) 2496c5aff182SThomas Petazzoni 2497c5aff182SThomas Petazzoni { 2498a29b6235SMarcin Wojtas struct netdev_queue *nq = netdev_get_tx_queue(pp->dev, txq->id); 2499c5aff182SThomas Petazzoni int tx_done = txq->count; 2500c5aff182SThomas Petazzoni 2501a29b6235SMarcin Wojtas mvneta_txq_bufs_free(pp, txq, tx_done, nq); 2502c5aff182SThomas Petazzoni 2503c5aff182SThomas Petazzoni /* reset txq */ 2504c5aff182SThomas Petazzoni txq->count = 0; 2505c5aff182SThomas Petazzoni txq->txq_put_index = 0; 2506c5aff182SThomas Petazzoni txq->txq_get_index = 0; 2507c5aff182SThomas Petazzoni } 2508c5aff182SThomas Petazzoni 25096c498974Swilly tarreau /* Handle tx done - called in softirq context. The <cause_tx_done> argument 25106c498974Swilly tarreau * must be a valid cause according to MVNETA_TXQ_INTR_MASK_ALL. 25116c498974Swilly tarreau */ 25120713a86aSArnaud Ebalard static void mvneta_tx_done_gbe(struct mvneta_port *pp, u32 cause_tx_done) 2513c5aff182SThomas Petazzoni { 2514c5aff182SThomas Petazzoni struct mvneta_tx_queue *txq; 2515c5aff182SThomas Petazzoni struct netdev_queue *nq; 2516bd9f1ee3SJisheng Zhang int cpu = smp_processor_id(); 2517c5aff182SThomas Petazzoni 25186c498974Swilly tarreau while (cause_tx_done) { 2519c5aff182SThomas Petazzoni txq = mvneta_tx_done_policy(pp, cause_tx_done); 2520c5aff182SThomas Petazzoni 2521c5aff182SThomas Petazzoni nq = netdev_get_tx_queue(pp->dev, txq->id); 2522bd9f1ee3SJisheng Zhang __netif_tx_lock(nq, cpu); 2523c5aff182SThomas Petazzoni 25240713a86aSArnaud Ebalard if (txq->count) 25250713a86aSArnaud Ebalard mvneta_txq_done(pp, txq); 2526c5aff182SThomas Petazzoni 2527c5aff182SThomas Petazzoni __netif_tx_unlock(nq); 2528c5aff182SThomas Petazzoni cause_tx_done &= ~((1 << txq->id)); 2529c5aff182SThomas Petazzoni } 2530c5aff182SThomas Petazzoni } 2531c5aff182SThomas Petazzoni 25326a20c175SThomas Petazzoni /* Compute crc8 of the specified address, using a unique algorithm , 2533c5aff182SThomas Petazzoni * according to hw spec, different than generic crc8 algorithm 2534c5aff182SThomas Petazzoni */ 2535c5aff182SThomas Petazzoni static int mvneta_addr_crc(unsigned char *addr) 2536c5aff182SThomas Petazzoni { 2537c5aff182SThomas Petazzoni int crc = 0; 2538c5aff182SThomas Petazzoni int i; 2539c5aff182SThomas Petazzoni 2540c5aff182SThomas Petazzoni for (i = 0; i < ETH_ALEN; i++) { 2541c5aff182SThomas Petazzoni int j; 2542c5aff182SThomas Petazzoni 2543c5aff182SThomas Petazzoni crc = (crc ^ addr[i]) << 8; 2544c5aff182SThomas Petazzoni for (j = 7; j >= 0; j--) { 2545c5aff182SThomas Petazzoni if (crc & (0x100 << j)) 2546c5aff182SThomas Petazzoni crc ^= 0x107 << j; 2547c5aff182SThomas Petazzoni } 2548c5aff182SThomas Petazzoni } 2549c5aff182SThomas Petazzoni 2550c5aff182SThomas Petazzoni return crc; 2551c5aff182SThomas Petazzoni } 2552c5aff182SThomas Petazzoni 2553c5aff182SThomas Petazzoni /* This method controls the net device special MAC multicast support. 2554c5aff182SThomas Petazzoni * The Special Multicast Table for MAC addresses supports MAC of the form 2555c5aff182SThomas Petazzoni * 0x01-00-5E-00-00-XX (where XX is between 0x00 and 0xFF). 2556c5aff182SThomas Petazzoni * The MAC DA[7:0] bits are used as a pointer to the Special Multicast 2557c5aff182SThomas Petazzoni * Table entries in the DA-Filter table. This method set the Special 2558c5aff182SThomas Petazzoni * Multicast Table appropriate entry. 2559c5aff182SThomas Petazzoni */ 2560c5aff182SThomas Petazzoni static void mvneta_set_special_mcast_addr(struct mvneta_port *pp, 2561c5aff182SThomas Petazzoni unsigned char last_byte, 2562c5aff182SThomas Petazzoni int queue) 2563c5aff182SThomas Petazzoni { 2564c5aff182SThomas Petazzoni unsigned int smc_table_reg; 2565c5aff182SThomas Petazzoni unsigned int tbl_offset; 2566c5aff182SThomas Petazzoni unsigned int reg_offset; 2567c5aff182SThomas Petazzoni 2568c5aff182SThomas Petazzoni /* Register offset from SMC table base */ 2569c5aff182SThomas Petazzoni tbl_offset = (last_byte / 4); 2570c5aff182SThomas Petazzoni /* Entry offset within the above reg */ 2571c5aff182SThomas Petazzoni reg_offset = last_byte % 4; 2572c5aff182SThomas Petazzoni 2573c5aff182SThomas Petazzoni smc_table_reg = mvreg_read(pp, (MVNETA_DA_FILT_SPEC_MCAST 2574c5aff182SThomas Petazzoni + tbl_offset * 4)); 2575c5aff182SThomas Petazzoni 2576c5aff182SThomas Petazzoni if (queue == -1) 2577c5aff182SThomas Petazzoni smc_table_reg &= ~(0xff << (8 * reg_offset)); 2578c5aff182SThomas Petazzoni else { 2579c5aff182SThomas Petazzoni smc_table_reg &= ~(0xff << (8 * reg_offset)); 2580c5aff182SThomas Petazzoni smc_table_reg |= ((0x01 | (queue << 1)) << (8 * reg_offset)); 2581c5aff182SThomas Petazzoni } 2582c5aff182SThomas Petazzoni 2583c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_DA_FILT_SPEC_MCAST + tbl_offset * 4, 2584c5aff182SThomas Petazzoni smc_table_reg); 2585c5aff182SThomas Petazzoni } 2586c5aff182SThomas Petazzoni 2587c5aff182SThomas Petazzoni /* This method controls the network device Other MAC multicast support. 2588c5aff182SThomas Petazzoni * The Other Multicast Table is used for multicast of another type. 2589c5aff182SThomas Petazzoni * A CRC-8 is used as an index to the Other Multicast Table entries 2590c5aff182SThomas Petazzoni * in the DA-Filter table. 2591c5aff182SThomas Petazzoni * The method gets the CRC-8 value from the calling routine and 2592c5aff182SThomas Petazzoni * sets the Other Multicast Table appropriate entry according to the 2593c5aff182SThomas Petazzoni * specified CRC-8 . 2594c5aff182SThomas Petazzoni */ 2595c5aff182SThomas Petazzoni static void mvneta_set_other_mcast_addr(struct mvneta_port *pp, 2596c5aff182SThomas Petazzoni unsigned char crc8, 2597c5aff182SThomas Petazzoni int queue) 2598c5aff182SThomas Petazzoni { 2599c5aff182SThomas Petazzoni unsigned int omc_table_reg; 2600c5aff182SThomas Petazzoni unsigned int tbl_offset; 2601c5aff182SThomas Petazzoni unsigned int reg_offset; 2602c5aff182SThomas Petazzoni 2603c5aff182SThomas Petazzoni tbl_offset = (crc8 / 4) * 4; /* Register offset from OMC table base */ 2604c5aff182SThomas Petazzoni reg_offset = crc8 % 4; /* Entry offset within the above reg */ 2605c5aff182SThomas Petazzoni 2606c5aff182SThomas Petazzoni omc_table_reg = mvreg_read(pp, MVNETA_DA_FILT_OTH_MCAST + tbl_offset); 2607c5aff182SThomas Petazzoni 2608c5aff182SThomas Petazzoni if (queue == -1) { 2609c5aff182SThomas Petazzoni /* Clear accepts frame bit at specified Other DA table entry */ 2610c5aff182SThomas Petazzoni omc_table_reg &= ~(0xff << (8 * reg_offset)); 2611c5aff182SThomas Petazzoni } else { 2612c5aff182SThomas Petazzoni omc_table_reg &= ~(0xff << (8 * reg_offset)); 2613c5aff182SThomas Petazzoni omc_table_reg |= ((0x01 | (queue << 1)) << (8 * reg_offset)); 2614c5aff182SThomas Petazzoni } 2615c5aff182SThomas Petazzoni 2616c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_DA_FILT_OTH_MCAST + tbl_offset, omc_table_reg); 2617c5aff182SThomas Petazzoni } 2618c5aff182SThomas Petazzoni 2619c5aff182SThomas Petazzoni /* The network device supports multicast using two tables: 2620c5aff182SThomas Petazzoni * 1) Special Multicast Table for MAC addresses of the form 2621c5aff182SThomas Petazzoni * 0x01-00-5E-00-00-XX (where XX is between 0x00 and 0xFF). 2622c5aff182SThomas Petazzoni * The MAC DA[7:0] bits are used as a pointer to the Special Multicast 2623c5aff182SThomas Petazzoni * Table entries in the DA-Filter table. 2624c5aff182SThomas Petazzoni * 2) Other Multicast Table for multicast of another type. A CRC-8 value 2625c5aff182SThomas Petazzoni * is used as an index to the Other Multicast Table entries in the 2626c5aff182SThomas Petazzoni * DA-Filter table. 2627c5aff182SThomas Petazzoni */ 2628c5aff182SThomas Petazzoni static int mvneta_mcast_addr_set(struct mvneta_port *pp, unsigned char *p_addr, 2629c5aff182SThomas Petazzoni int queue) 2630c5aff182SThomas Petazzoni { 2631c5aff182SThomas Petazzoni unsigned char crc_result = 0; 2632c5aff182SThomas Petazzoni 2633c5aff182SThomas Petazzoni if (memcmp(p_addr, "\x01\x00\x5e\x00\x00", 5) == 0) { 2634c5aff182SThomas Petazzoni mvneta_set_special_mcast_addr(pp, p_addr[5], queue); 2635c5aff182SThomas Petazzoni return 0; 2636c5aff182SThomas Petazzoni } 2637c5aff182SThomas Petazzoni 2638c5aff182SThomas Petazzoni crc_result = mvneta_addr_crc(p_addr); 2639c5aff182SThomas Petazzoni if (queue == -1) { 2640c5aff182SThomas Petazzoni if (pp->mcast_count[crc_result] == 0) { 2641c5aff182SThomas Petazzoni netdev_info(pp->dev, "No valid Mcast for crc8=0x%02x\n", 2642c5aff182SThomas Petazzoni crc_result); 2643c5aff182SThomas Petazzoni return -EINVAL; 2644c5aff182SThomas Petazzoni } 2645c5aff182SThomas Petazzoni 2646c5aff182SThomas Petazzoni pp->mcast_count[crc_result]--; 2647c5aff182SThomas Petazzoni if (pp->mcast_count[crc_result] != 0) { 2648c5aff182SThomas Petazzoni netdev_info(pp->dev, 2649c5aff182SThomas Petazzoni "After delete there are %d valid Mcast for crc8=0x%02x\n", 2650c5aff182SThomas Petazzoni pp->mcast_count[crc_result], crc_result); 2651c5aff182SThomas Petazzoni return -EINVAL; 2652c5aff182SThomas Petazzoni } 2653c5aff182SThomas Petazzoni } else 2654c5aff182SThomas Petazzoni pp->mcast_count[crc_result]++; 2655c5aff182SThomas Petazzoni 2656c5aff182SThomas Petazzoni mvneta_set_other_mcast_addr(pp, crc_result, queue); 2657c5aff182SThomas Petazzoni 2658c5aff182SThomas Petazzoni return 0; 2659c5aff182SThomas Petazzoni } 2660c5aff182SThomas Petazzoni 2661c5aff182SThomas Petazzoni /* Configure Fitering mode of Ethernet port */ 2662c5aff182SThomas Petazzoni static void mvneta_rx_unicast_promisc_set(struct mvneta_port *pp, 2663c5aff182SThomas Petazzoni int is_promisc) 2664c5aff182SThomas Petazzoni { 2665c5aff182SThomas Petazzoni u32 port_cfg_reg, val; 2666c5aff182SThomas Petazzoni 2667c5aff182SThomas Petazzoni port_cfg_reg = mvreg_read(pp, MVNETA_PORT_CONFIG); 2668c5aff182SThomas Petazzoni 2669c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_TYPE_PRIO); 2670c5aff182SThomas Petazzoni 2671c5aff182SThomas Petazzoni /* Set / Clear UPM bit in port configuration register */ 2672c5aff182SThomas Petazzoni if (is_promisc) { 2673c5aff182SThomas Petazzoni /* Accept all Unicast addresses */ 2674c5aff182SThomas Petazzoni port_cfg_reg |= MVNETA_UNI_PROMISC_MODE; 2675c5aff182SThomas Petazzoni val |= MVNETA_FORCE_UNI; 2676c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_MAC_ADDR_LOW, 0xffff); 2677c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_MAC_ADDR_HIGH, 0xffffffff); 2678c5aff182SThomas Petazzoni } else { 2679c5aff182SThomas Petazzoni /* Reject all Unicast addresses */ 2680c5aff182SThomas Petazzoni port_cfg_reg &= ~MVNETA_UNI_PROMISC_MODE; 2681c5aff182SThomas Petazzoni val &= ~MVNETA_FORCE_UNI; 2682c5aff182SThomas Petazzoni } 2683c5aff182SThomas Petazzoni 2684c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_PORT_CONFIG, port_cfg_reg); 2685c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_TYPE_PRIO, val); 2686c5aff182SThomas Petazzoni } 2687c5aff182SThomas Petazzoni 2688c5aff182SThomas Petazzoni /* register unicast and multicast addresses */ 2689c5aff182SThomas Petazzoni static void mvneta_set_rx_mode(struct net_device *dev) 2690c5aff182SThomas Petazzoni { 2691c5aff182SThomas Petazzoni struct mvneta_port *pp = netdev_priv(dev); 2692c5aff182SThomas Petazzoni struct netdev_hw_addr *ha; 2693c5aff182SThomas Petazzoni 2694c5aff182SThomas Petazzoni if (dev->flags & IFF_PROMISC) { 2695c5aff182SThomas Petazzoni /* Accept all: Multicast + Unicast */ 2696c5aff182SThomas Petazzoni mvneta_rx_unicast_promisc_set(pp, 1); 269790b74c01SGregory CLEMENT mvneta_set_ucast_table(pp, pp->rxq_def); 269890b74c01SGregory CLEMENT mvneta_set_special_mcast_table(pp, pp->rxq_def); 269990b74c01SGregory CLEMENT mvneta_set_other_mcast_table(pp, pp->rxq_def); 2700c5aff182SThomas Petazzoni } else { 2701c5aff182SThomas Petazzoni /* Accept single Unicast */ 2702c5aff182SThomas Petazzoni mvneta_rx_unicast_promisc_set(pp, 0); 2703c5aff182SThomas Petazzoni mvneta_set_ucast_table(pp, -1); 270490b74c01SGregory CLEMENT mvneta_mac_addr_set(pp, dev->dev_addr, pp->rxq_def); 2705c5aff182SThomas Petazzoni 2706c5aff182SThomas Petazzoni if (dev->flags & IFF_ALLMULTI) { 2707c5aff182SThomas Petazzoni /* Accept all multicast */ 270890b74c01SGregory CLEMENT mvneta_set_special_mcast_table(pp, pp->rxq_def); 270990b74c01SGregory CLEMENT mvneta_set_other_mcast_table(pp, pp->rxq_def); 2710c5aff182SThomas Petazzoni } else { 2711c5aff182SThomas Petazzoni /* Accept only initialized multicast */ 2712c5aff182SThomas Petazzoni mvneta_set_special_mcast_table(pp, -1); 2713c5aff182SThomas Petazzoni mvneta_set_other_mcast_table(pp, -1); 2714c5aff182SThomas Petazzoni 2715c5aff182SThomas Petazzoni if (!netdev_mc_empty(dev)) { 2716c5aff182SThomas Petazzoni netdev_for_each_mc_addr(ha, dev) { 2717c5aff182SThomas Petazzoni mvneta_mcast_addr_set(pp, ha->addr, 271890b74c01SGregory CLEMENT pp->rxq_def); 2719c5aff182SThomas Petazzoni } 2720c5aff182SThomas Petazzoni } 2721c5aff182SThomas Petazzoni } 2722c5aff182SThomas Petazzoni } 2723c5aff182SThomas Petazzoni } 2724c5aff182SThomas Petazzoni 2725c5aff182SThomas Petazzoni /* Interrupt handling - the callback for request_irq() */ 2726c5aff182SThomas Petazzoni static irqreturn_t mvneta_isr(int irq, void *dev_id) 2727c5aff182SThomas Petazzoni { 27282636ac3cSMarcin Wojtas struct mvneta_port *pp = (struct mvneta_port *)dev_id; 27292636ac3cSMarcin Wojtas 27302636ac3cSMarcin Wojtas mvreg_write(pp, MVNETA_INTR_NEW_MASK, 0); 27312636ac3cSMarcin Wojtas napi_schedule(&pp->napi); 27322636ac3cSMarcin Wojtas 27332636ac3cSMarcin Wojtas return IRQ_HANDLED; 27342636ac3cSMarcin Wojtas } 27352636ac3cSMarcin Wojtas 27362636ac3cSMarcin Wojtas /* Interrupt handling - the callback for request_percpu_irq() */ 27372636ac3cSMarcin Wojtas static irqreturn_t mvneta_percpu_isr(int irq, void *dev_id) 27382636ac3cSMarcin Wojtas { 273912bb03b4SMaxime Ripard struct mvneta_pcpu_port *port = (struct mvneta_pcpu_port *)dev_id; 2740c5aff182SThomas Petazzoni 274112bb03b4SMaxime Ripard disable_percpu_irq(port->pp->dev->irq); 274212bb03b4SMaxime Ripard napi_schedule(&port->napi); 2743c5aff182SThomas Petazzoni 2744c5aff182SThomas Petazzoni return IRQ_HANDLED; 2745c5aff182SThomas Petazzoni } 2746c5aff182SThomas Petazzoni 2747503f9aa9SRussell King static void mvneta_link_change(struct mvneta_port *pp) 2748898b2970SStas Sergeev { 2749898b2970SStas Sergeev u32 gmac_stat = mvreg_read(pp, MVNETA_GMAC_STATUS); 2750898b2970SStas Sergeev 2751503f9aa9SRussell King phylink_mac_change(pp->phylink, !!(gmac_stat & MVNETA_GMAC_LINK_UP)); 2752898b2970SStas Sergeev } 2753898b2970SStas Sergeev 2754c5aff182SThomas Petazzoni /* NAPI handler 2755c5aff182SThomas Petazzoni * Bits 0 - 7 of the causeRxTx register indicate that are transmitted 2756c5aff182SThomas Petazzoni * packets on the corresponding TXQ (Bit 0 is for TX queue 1). 2757c5aff182SThomas Petazzoni * Bits 8 -15 of the cause Rx Tx register indicate that are received 2758c5aff182SThomas Petazzoni * packets on the corresponding RXQ (Bit 8 is for RX queue 0). 2759c5aff182SThomas Petazzoni * Each CPU has its own causeRxTx register 2760c5aff182SThomas Petazzoni */ 2761c5aff182SThomas Petazzoni static int mvneta_poll(struct napi_struct *napi, int budget) 2762c5aff182SThomas Petazzoni { 2763c5aff182SThomas Petazzoni int rx_done = 0; 2764c5aff182SThomas Petazzoni u32 cause_rx_tx; 27652dcf75e2SGregory CLEMENT int rx_queue; 2766c5aff182SThomas Petazzoni struct mvneta_port *pp = netdev_priv(napi->dev); 276712bb03b4SMaxime Ripard struct mvneta_pcpu_port *port = this_cpu_ptr(pp->ports); 2768c5aff182SThomas Petazzoni 2769c5aff182SThomas Petazzoni if (!netif_running(pp->dev)) { 27702636ac3cSMarcin Wojtas napi_complete(napi); 2771c5aff182SThomas Petazzoni return rx_done; 2772c5aff182SThomas Petazzoni } 2773c5aff182SThomas Petazzoni 2774c5aff182SThomas Petazzoni /* Read cause register */ 2775898b2970SStas Sergeev cause_rx_tx = mvreg_read(pp, MVNETA_INTR_NEW_CAUSE); 2776898b2970SStas Sergeev if (cause_rx_tx & MVNETA_MISCINTR_INTR_MASK) { 2777898b2970SStas Sergeev u32 cause_misc = mvreg_read(pp, MVNETA_INTR_MISC_CAUSE); 2778898b2970SStas Sergeev 2779898b2970SStas Sergeev mvreg_write(pp, MVNETA_INTR_MISC_CAUSE, 0); 2780503f9aa9SRussell King 2781503f9aa9SRussell King if (cause_misc & (MVNETA_CAUSE_PHY_STATUS_CHANGE | 2782856b2cc5SRussell King MVNETA_CAUSE_LINK_CHANGE)) 2783503f9aa9SRussell King mvneta_link_change(pp); 2784898b2970SStas Sergeev } 278571f6d1b3Swilly tarreau 278671f6d1b3Swilly tarreau /* Release Tx descriptors */ 278771f6d1b3Swilly tarreau if (cause_rx_tx & MVNETA_TX_INTR_MASK_ALL) { 27880713a86aSArnaud Ebalard mvneta_tx_done_gbe(pp, (cause_rx_tx & MVNETA_TX_INTR_MASK_ALL)); 278971f6d1b3Swilly tarreau cause_rx_tx &= ~MVNETA_TX_INTR_MASK_ALL; 279071f6d1b3Swilly tarreau } 2791c5aff182SThomas Petazzoni 27926a20c175SThomas Petazzoni /* For the case where the last mvneta_poll did not process all 2793c5aff182SThomas Petazzoni * RX packets 2794c5aff182SThomas Petazzoni */ 27952dcf75e2SGregory CLEMENT rx_queue = fls(((cause_rx_tx >> 8) & 0xff)); 27962dcf75e2SGregory CLEMENT 27972636ac3cSMarcin Wojtas cause_rx_tx |= pp->neta_armada3700 ? pp->cause_rx_tx : 27982636ac3cSMarcin Wojtas port->cause_rx_tx; 27992dcf75e2SGregory CLEMENT 28002dcf75e2SGregory CLEMENT if (rx_queue) { 28012dcf75e2SGregory CLEMENT rx_queue = rx_queue - 1; 2802dc35a10fSMarcin Wojtas if (pp->bm_priv) 28037a86f05fSAndrew Lunn rx_done = mvneta_rx_hwbm(napi, pp, budget, 28047a86f05fSAndrew Lunn &pp->rxqs[rx_queue]); 2805dc35a10fSMarcin Wojtas else 28067a86f05fSAndrew Lunn rx_done = mvneta_rx_swbm(napi, pp, budget, 28077a86f05fSAndrew Lunn &pp->rxqs[rx_queue]); 28082dcf75e2SGregory CLEMENT } 28092dcf75e2SGregory CLEMENT 28106ad20165SEric Dumazet if (rx_done < budget) { 2811c5aff182SThomas Petazzoni cause_rx_tx = 0; 28126ad20165SEric Dumazet napi_complete_done(napi, rx_done); 28132636ac3cSMarcin Wojtas 28142636ac3cSMarcin Wojtas if (pp->neta_armada3700) { 28152636ac3cSMarcin Wojtas unsigned long flags; 28162636ac3cSMarcin Wojtas 28172636ac3cSMarcin Wojtas local_irq_save(flags); 28182636ac3cSMarcin Wojtas mvreg_write(pp, MVNETA_INTR_NEW_MASK, 28192636ac3cSMarcin Wojtas MVNETA_RX_INTR_MASK(rxq_number) | 28202636ac3cSMarcin Wojtas MVNETA_TX_INTR_MASK(txq_number) | 28212636ac3cSMarcin Wojtas MVNETA_MISCINTR_INTR_MASK); 28222636ac3cSMarcin Wojtas local_irq_restore(flags); 28232636ac3cSMarcin Wojtas } else { 282412bb03b4SMaxime Ripard enable_percpu_irq(pp->dev->irq, 0); 2825c5aff182SThomas Petazzoni } 28262636ac3cSMarcin Wojtas } 2827c5aff182SThomas Petazzoni 28282636ac3cSMarcin Wojtas if (pp->neta_armada3700) 28292636ac3cSMarcin Wojtas pp->cause_rx_tx = cause_rx_tx; 28302636ac3cSMarcin Wojtas else 283112bb03b4SMaxime Ripard port->cause_rx_tx = cause_rx_tx; 28322636ac3cSMarcin Wojtas 2833c5aff182SThomas Petazzoni return rx_done; 2834c5aff182SThomas Petazzoni } 2835c5aff182SThomas Petazzoni 2836568a3fa2SLorenzo Bianconi static int mvneta_create_page_pool(struct mvneta_port *pp, 2837568a3fa2SLorenzo Bianconi struct mvneta_rx_queue *rxq, int size) 2838568a3fa2SLorenzo Bianconi { 2839568a3fa2SLorenzo Bianconi struct page_pool_params pp_params = { 2840568a3fa2SLorenzo Bianconi .order = 0, 2841568a3fa2SLorenzo Bianconi .flags = PP_FLAG_DMA_MAP, 2842568a3fa2SLorenzo Bianconi .pool_size = size, 2843568a3fa2SLorenzo Bianconi .nid = cpu_to_node(0), 2844568a3fa2SLorenzo Bianconi .dev = pp->dev->dev.parent, 2845568a3fa2SLorenzo Bianconi .dma_dir = DMA_FROM_DEVICE, 2846568a3fa2SLorenzo Bianconi }; 2847568a3fa2SLorenzo Bianconi int err; 2848568a3fa2SLorenzo Bianconi 2849568a3fa2SLorenzo Bianconi rxq->page_pool = page_pool_create(&pp_params); 2850568a3fa2SLorenzo Bianconi if (IS_ERR(rxq->page_pool)) { 2851568a3fa2SLorenzo Bianconi err = PTR_ERR(rxq->page_pool); 2852568a3fa2SLorenzo Bianconi rxq->page_pool = NULL; 2853568a3fa2SLorenzo Bianconi return err; 2854568a3fa2SLorenzo Bianconi } 2855568a3fa2SLorenzo Bianconi 2856568a3fa2SLorenzo Bianconi err = xdp_rxq_info_reg(&rxq->xdp_rxq, pp->dev, rxq->id); 2857568a3fa2SLorenzo Bianconi if (err < 0) 2858568a3fa2SLorenzo Bianconi goto err_free_pp; 2859568a3fa2SLorenzo Bianconi 2860568a3fa2SLorenzo Bianconi err = xdp_rxq_info_reg_mem_model(&rxq->xdp_rxq, MEM_TYPE_PAGE_POOL, 2861568a3fa2SLorenzo Bianconi rxq->page_pool); 2862568a3fa2SLorenzo Bianconi if (err) 2863568a3fa2SLorenzo Bianconi goto err_unregister_rxq; 2864568a3fa2SLorenzo Bianconi 2865568a3fa2SLorenzo Bianconi return 0; 2866568a3fa2SLorenzo Bianconi 2867568a3fa2SLorenzo Bianconi err_unregister_rxq: 2868568a3fa2SLorenzo Bianconi xdp_rxq_info_unreg(&rxq->xdp_rxq); 2869568a3fa2SLorenzo Bianconi err_free_pp: 2870568a3fa2SLorenzo Bianconi page_pool_destroy(rxq->page_pool); 2871568a3fa2SLorenzo Bianconi rxq->page_pool = NULL; 2872568a3fa2SLorenzo Bianconi return err; 2873568a3fa2SLorenzo Bianconi } 2874568a3fa2SLorenzo Bianconi 2875c5aff182SThomas Petazzoni /* Handle rxq fill: allocates rxq skbs; called when initializing a port */ 2876c5aff182SThomas Petazzoni static int mvneta_rxq_fill(struct mvneta_port *pp, struct mvneta_rx_queue *rxq, 2877c5aff182SThomas Petazzoni int num) 2878c5aff182SThomas Petazzoni { 2879568a3fa2SLorenzo Bianconi int i, err; 2880568a3fa2SLorenzo Bianconi 2881568a3fa2SLorenzo Bianconi err = mvneta_create_page_pool(pp, rxq, num); 2882568a3fa2SLorenzo Bianconi if (err < 0) 2883568a3fa2SLorenzo Bianconi return err; 2884c5aff182SThomas Petazzoni 2885c5aff182SThomas Petazzoni for (i = 0; i < num; i++) { 2886a1a65ab1Swilly tarreau memset(rxq->descs + i, 0, sizeof(struct mvneta_rx_desc)); 28877e47fd84SGregory CLEMENT if (mvneta_rx_refill(pp, rxq->descs + i, rxq, 28887e47fd84SGregory CLEMENT GFP_KERNEL) != 0) { 28897e47fd84SGregory CLEMENT netdev_err(pp->dev, 28907e47fd84SGregory CLEMENT "%s:rxq %d, %d of %d buffs filled\n", 2891c5aff182SThomas Petazzoni __func__, rxq->id, i, num); 2892c5aff182SThomas Petazzoni break; 2893c5aff182SThomas Petazzoni } 2894c5aff182SThomas Petazzoni } 2895c5aff182SThomas Petazzoni 2896c5aff182SThomas Petazzoni /* Add this number of RX descriptors as non occupied (ready to 28976a20c175SThomas Petazzoni * get packets) 28986a20c175SThomas Petazzoni */ 2899c5aff182SThomas Petazzoni mvneta_rxq_non_occup_desc_add(pp, rxq, i); 2900c5aff182SThomas Petazzoni 2901c5aff182SThomas Petazzoni return i; 2902c5aff182SThomas Petazzoni } 2903c5aff182SThomas Petazzoni 2904c5aff182SThomas Petazzoni /* Free all packets pending transmit from all TXQs and reset TX port */ 2905c5aff182SThomas Petazzoni static void mvneta_tx_reset(struct mvneta_port *pp) 2906c5aff182SThomas Petazzoni { 2907c5aff182SThomas Petazzoni int queue; 2908c5aff182SThomas Petazzoni 29099672850bSEzequiel Garcia /* free the skb's in the tx ring */ 2910c5aff182SThomas Petazzoni for (queue = 0; queue < txq_number; queue++) 2911c5aff182SThomas Petazzoni mvneta_txq_done_force(pp, &pp->txqs[queue]); 2912c5aff182SThomas Petazzoni 2913c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_PORT_TX_RESET, MVNETA_PORT_TX_DMA_RESET); 2914c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_PORT_TX_RESET, 0); 2915c5aff182SThomas Petazzoni } 2916c5aff182SThomas Petazzoni 2917c5aff182SThomas Petazzoni static void mvneta_rx_reset(struct mvneta_port *pp) 2918c5aff182SThomas Petazzoni { 2919c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_PORT_RX_RESET, MVNETA_PORT_RX_DMA_RESET); 2920c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_PORT_RX_RESET, 0); 2921c5aff182SThomas Petazzoni } 2922c5aff182SThomas Petazzoni 2923c5aff182SThomas Petazzoni /* Rx/Tx queue initialization/cleanup methods */ 2924c5aff182SThomas Petazzoni 29254a188a63SJisheng Zhang static int mvneta_rxq_sw_init(struct mvneta_port *pp, 2926c5aff182SThomas Petazzoni struct mvneta_rx_queue *rxq) 2927c5aff182SThomas Petazzoni { 2928c5aff182SThomas Petazzoni rxq->size = pp->rx_ring_size; 2929c5aff182SThomas Petazzoni 2930c5aff182SThomas Petazzoni /* Allocate memory for RX descriptors */ 2931c5aff182SThomas Petazzoni rxq->descs = dma_alloc_coherent(pp->dev->dev.parent, 2932c5aff182SThomas Petazzoni rxq->size * MVNETA_DESC_ALIGNED_SIZE, 2933c5aff182SThomas Petazzoni &rxq->descs_phys, GFP_KERNEL); 2934f95936ccSMarkus Elfring if (!rxq->descs) 2935c5aff182SThomas Petazzoni return -ENOMEM; 2936c5aff182SThomas Petazzoni 2937c5aff182SThomas Petazzoni rxq->last_desc = rxq->size - 1; 2938c5aff182SThomas Petazzoni 29394a188a63SJisheng Zhang return 0; 29404a188a63SJisheng Zhang } 29414a188a63SJisheng Zhang 29424a188a63SJisheng Zhang static void mvneta_rxq_hw_init(struct mvneta_port *pp, 29434a188a63SJisheng Zhang struct mvneta_rx_queue *rxq) 29444a188a63SJisheng Zhang { 2945c5aff182SThomas Petazzoni /* Set Rx descriptors queue starting address */ 2946c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_RXQ_BASE_ADDR_REG(rxq->id), rxq->descs_phys); 2947c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_RXQ_SIZE_REG(rxq->id), rxq->size); 2948c5aff182SThomas Petazzoni 2949c5aff182SThomas Petazzoni /* Set coalescing pkts and time */ 2950c5aff182SThomas Petazzoni mvneta_rx_pkts_coal_set(pp, rxq, rxq->pkts_coal); 2951c5aff182SThomas Petazzoni mvneta_rx_time_coal_set(pp, rxq, rxq->time_coal); 2952c5aff182SThomas Petazzoni 2953dc35a10fSMarcin Wojtas if (!pp->bm_priv) { 2954562e2f46SYelena Krivosheev /* Set Offset */ 2955562e2f46SYelena Krivosheev mvneta_rxq_offset_set(pp, rxq, 0); 2956e735fd55SMarcin Wojtas mvneta_rxq_buf_size_set(pp, rxq, PAGE_SIZE < SZ_64K ? 2957e735fd55SMarcin Wojtas PAGE_SIZE : 2958e735fd55SMarcin Wojtas MVNETA_RX_BUF_SIZE(pp->pkt_size)); 2959c5aff182SThomas Petazzoni mvneta_rxq_bm_disable(pp, rxq); 2960e9f64999SGregory CLEMENT mvneta_rxq_fill(pp, rxq, rxq->size); 2961dc35a10fSMarcin Wojtas } else { 2962562e2f46SYelena Krivosheev /* Set Offset */ 2963562e2f46SYelena Krivosheev mvneta_rxq_offset_set(pp, rxq, 2964562e2f46SYelena Krivosheev NET_SKB_PAD - pp->rx_offset_correction); 2965562e2f46SYelena Krivosheev 2966dc35a10fSMarcin Wojtas mvneta_rxq_bm_enable(pp, rxq); 2967562e2f46SYelena Krivosheev /* Fill RXQ with buffers from RX pool */ 2968dc35a10fSMarcin Wojtas mvneta_rxq_long_pool_set(pp, rxq); 2969dc35a10fSMarcin Wojtas mvneta_rxq_short_pool_set(pp, rxq); 2970e9f64999SGregory CLEMENT mvneta_rxq_non_occup_desc_add(pp, rxq, rxq->size); 2971dc35a10fSMarcin Wojtas } 29724a188a63SJisheng Zhang } 29734a188a63SJisheng Zhang 29744a188a63SJisheng Zhang /* Create a specified RX queue */ 29754a188a63SJisheng Zhang static int mvneta_rxq_init(struct mvneta_port *pp, 29764a188a63SJisheng Zhang struct mvneta_rx_queue *rxq) 29774a188a63SJisheng Zhang 29784a188a63SJisheng Zhang { 29794a188a63SJisheng Zhang int ret; 29804a188a63SJisheng Zhang 29814a188a63SJisheng Zhang ret = mvneta_rxq_sw_init(pp, rxq); 29824a188a63SJisheng Zhang if (ret < 0) 29834a188a63SJisheng Zhang return ret; 29844a188a63SJisheng Zhang 29854a188a63SJisheng Zhang mvneta_rxq_hw_init(pp, rxq); 2986dc35a10fSMarcin Wojtas 2987c5aff182SThomas Petazzoni return 0; 2988c5aff182SThomas Petazzoni } 2989c5aff182SThomas Petazzoni 2990c5aff182SThomas Petazzoni /* Cleanup Rx queue */ 2991c5aff182SThomas Petazzoni static void mvneta_rxq_deinit(struct mvneta_port *pp, 2992c5aff182SThomas Petazzoni struct mvneta_rx_queue *rxq) 2993c5aff182SThomas Petazzoni { 2994c5aff182SThomas Petazzoni mvneta_rxq_drop_pkts(pp, rxq); 2995c5aff182SThomas Petazzoni 2996562e2f46SYelena Krivosheev if (rxq->skb) 2997562e2f46SYelena Krivosheev dev_kfree_skb_any(rxq->skb); 2998562e2f46SYelena Krivosheev 2999c5aff182SThomas Petazzoni if (rxq->descs) 3000c5aff182SThomas Petazzoni dma_free_coherent(pp->dev->dev.parent, 3001c5aff182SThomas Petazzoni rxq->size * MVNETA_DESC_ALIGNED_SIZE, 3002c5aff182SThomas Petazzoni rxq->descs, 3003c5aff182SThomas Petazzoni rxq->descs_phys); 3004c5aff182SThomas Petazzoni 3005c5aff182SThomas Petazzoni rxq->descs = NULL; 3006c5aff182SThomas Petazzoni rxq->last_desc = 0; 3007c5aff182SThomas Petazzoni rxq->next_desc_to_proc = 0; 3008c5aff182SThomas Petazzoni rxq->descs_phys = 0; 3009562e2f46SYelena Krivosheev rxq->first_to_refill = 0; 3010562e2f46SYelena Krivosheev rxq->refill_num = 0; 3011562e2f46SYelena Krivosheev rxq->skb = NULL; 3012562e2f46SYelena Krivosheev rxq->left_size = 0; 3013c5aff182SThomas Petazzoni } 3014c5aff182SThomas Petazzoni 30154a188a63SJisheng Zhang static int mvneta_txq_sw_init(struct mvneta_port *pp, 3016c5aff182SThomas Petazzoni struct mvneta_tx_queue *txq) 3017c5aff182SThomas Petazzoni { 301850bf8cb6SGregory CLEMENT int cpu; 301950bf8cb6SGregory CLEMENT 3020c5aff182SThomas Petazzoni txq->size = pp->tx_ring_size; 3021c5aff182SThomas Petazzoni 30228eef5f97SEzequiel Garcia /* A queue must always have room for at least one skb. 30238eef5f97SEzequiel Garcia * Therefore, stop the queue when the free entries reaches 30248eef5f97SEzequiel Garcia * the maximum number of descriptors per skb. 30258eef5f97SEzequiel Garcia */ 30268eef5f97SEzequiel Garcia txq->tx_stop_threshold = txq->size - MVNETA_MAX_SKB_DESCS; 30278eef5f97SEzequiel Garcia txq->tx_wake_threshold = txq->tx_stop_threshold / 2; 30288eef5f97SEzequiel Garcia 3029c5aff182SThomas Petazzoni /* Allocate memory for TX descriptors */ 3030c5aff182SThomas Petazzoni txq->descs = dma_alloc_coherent(pp->dev->dev.parent, 3031c5aff182SThomas Petazzoni txq->size * MVNETA_DESC_ALIGNED_SIZE, 3032c5aff182SThomas Petazzoni &txq->descs_phys, GFP_KERNEL); 3033f95936ccSMarkus Elfring if (!txq->descs) 3034c5aff182SThomas Petazzoni return -ENOMEM; 3035c5aff182SThomas Petazzoni 3036c5aff182SThomas Petazzoni txq->last_desc = txq->size - 1; 3037c5aff182SThomas Petazzoni 3038d441b688SMarkus Elfring txq->tx_skb = kmalloc_array(txq->size, sizeof(*txq->tx_skb), 3039d441b688SMarkus Elfring GFP_KERNEL); 3040f95936ccSMarkus Elfring if (!txq->tx_skb) { 3041c5aff182SThomas Petazzoni dma_free_coherent(pp->dev->dev.parent, 3042c5aff182SThomas Petazzoni txq->size * MVNETA_DESC_ALIGNED_SIZE, 3043c5aff182SThomas Petazzoni txq->descs, txq->descs_phys); 3044c5aff182SThomas Petazzoni return -ENOMEM; 3045c5aff182SThomas Petazzoni } 30462adb719dSEzequiel Garcia 30472adb719dSEzequiel Garcia /* Allocate DMA buffers for TSO MAC/IP/TCP headers */ 30482adb719dSEzequiel Garcia txq->tso_hdrs = dma_alloc_coherent(pp->dev->dev.parent, 30492adb719dSEzequiel Garcia txq->size * TSO_HEADER_SIZE, 30502adb719dSEzequiel Garcia &txq->tso_hdrs_phys, GFP_KERNEL); 3051f95936ccSMarkus Elfring if (!txq->tso_hdrs) { 30522adb719dSEzequiel Garcia kfree(txq->tx_skb); 30532adb719dSEzequiel Garcia dma_free_coherent(pp->dev->dev.parent, 30542adb719dSEzequiel Garcia txq->size * MVNETA_DESC_ALIGNED_SIZE, 30552adb719dSEzequiel Garcia txq->descs, txq->descs_phys); 30562adb719dSEzequiel Garcia return -ENOMEM; 30572adb719dSEzequiel Garcia } 3058c5aff182SThomas Petazzoni 305950bf8cb6SGregory CLEMENT /* Setup XPS mapping */ 306050bf8cb6SGregory CLEMENT if (txq_number > 1) 306150bf8cb6SGregory CLEMENT cpu = txq->id % num_present_cpus(); 306250bf8cb6SGregory CLEMENT else 306350bf8cb6SGregory CLEMENT cpu = pp->rxq_def % num_present_cpus(); 306450bf8cb6SGregory CLEMENT cpumask_set_cpu(cpu, &txq->affinity_mask); 306550bf8cb6SGregory CLEMENT netif_set_xps_queue(pp->dev, &txq->affinity_mask, txq->id); 306650bf8cb6SGregory CLEMENT 3067c5aff182SThomas Petazzoni return 0; 3068c5aff182SThomas Petazzoni } 3069c5aff182SThomas Petazzoni 30704a188a63SJisheng Zhang static void mvneta_txq_hw_init(struct mvneta_port *pp, 30714a188a63SJisheng Zhang struct mvneta_tx_queue *txq) 30724a188a63SJisheng Zhang { 30734a188a63SJisheng Zhang /* Set maximum bandwidth for enabled TXQs */ 30744a188a63SJisheng Zhang mvreg_write(pp, MVETH_TXQ_TOKEN_CFG_REG(txq->id), 0x03ffffff); 30754a188a63SJisheng Zhang mvreg_write(pp, MVETH_TXQ_TOKEN_COUNT_REG(txq->id), 0x3fffffff); 30764a188a63SJisheng Zhang 30774a188a63SJisheng Zhang /* Set Tx descriptors queue starting address */ 30784a188a63SJisheng Zhang mvreg_write(pp, MVNETA_TXQ_BASE_ADDR_REG(txq->id), txq->descs_phys); 30794a188a63SJisheng Zhang mvreg_write(pp, MVNETA_TXQ_SIZE_REG(txq->id), txq->size); 30804a188a63SJisheng Zhang 30814a188a63SJisheng Zhang mvneta_tx_done_pkts_coal_set(pp, txq, txq->done_pkts_coal); 30824a188a63SJisheng Zhang } 30834a188a63SJisheng Zhang 30844a188a63SJisheng Zhang /* Create and initialize a tx queue */ 30854a188a63SJisheng Zhang static int mvneta_txq_init(struct mvneta_port *pp, 30864a188a63SJisheng Zhang struct mvneta_tx_queue *txq) 30874a188a63SJisheng Zhang { 30884a188a63SJisheng Zhang int ret; 30894a188a63SJisheng Zhang 30904a188a63SJisheng Zhang ret = mvneta_txq_sw_init(pp, txq); 30914a188a63SJisheng Zhang if (ret < 0) 30924a188a63SJisheng Zhang return ret; 30934a188a63SJisheng Zhang 30944a188a63SJisheng Zhang mvneta_txq_hw_init(pp, txq); 30954a188a63SJisheng Zhang 30964a188a63SJisheng Zhang return 0; 30974a188a63SJisheng Zhang } 30984a188a63SJisheng Zhang 3099c5aff182SThomas Petazzoni /* Free allocated resources when mvneta_txq_init() fails to allocate memory*/ 31004a188a63SJisheng Zhang static void mvneta_txq_sw_deinit(struct mvneta_port *pp, 3101c5aff182SThomas Petazzoni struct mvneta_tx_queue *txq) 3102c5aff182SThomas Petazzoni { 3103a29b6235SMarcin Wojtas struct netdev_queue *nq = netdev_get_tx_queue(pp->dev, txq->id); 3104a29b6235SMarcin Wojtas 3105c5aff182SThomas Petazzoni kfree(txq->tx_skb); 3106c5aff182SThomas Petazzoni 31072adb719dSEzequiel Garcia if (txq->tso_hdrs) 31082adb719dSEzequiel Garcia dma_free_coherent(pp->dev->dev.parent, 31092adb719dSEzequiel Garcia txq->size * TSO_HEADER_SIZE, 31102adb719dSEzequiel Garcia txq->tso_hdrs, txq->tso_hdrs_phys); 3111c5aff182SThomas Petazzoni if (txq->descs) 3112c5aff182SThomas Petazzoni dma_free_coherent(pp->dev->dev.parent, 3113c5aff182SThomas Petazzoni txq->size * MVNETA_DESC_ALIGNED_SIZE, 3114c5aff182SThomas Petazzoni txq->descs, txq->descs_phys); 3115c5aff182SThomas Petazzoni 3116a29b6235SMarcin Wojtas netdev_tx_reset_queue(nq); 3117a29b6235SMarcin Wojtas 3118c5aff182SThomas Petazzoni txq->descs = NULL; 3119c5aff182SThomas Petazzoni txq->last_desc = 0; 3120c5aff182SThomas Petazzoni txq->next_desc_to_proc = 0; 3121c5aff182SThomas Petazzoni txq->descs_phys = 0; 31224a188a63SJisheng Zhang } 3123c5aff182SThomas Petazzoni 31244a188a63SJisheng Zhang static void mvneta_txq_hw_deinit(struct mvneta_port *pp, 31254a188a63SJisheng Zhang struct mvneta_tx_queue *txq) 31264a188a63SJisheng Zhang { 3127c5aff182SThomas Petazzoni /* Set minimum bandwidth for disabled TXQs */ 3128c5aff182SThomas Petazzoni mvreg_write(pp, MVETH_TXQ_TOKEN_CFG_REG(txq->id), 0); 3129c5aff182SThomas Petazzoni mvreg_write(pp, MVETH_TXQ_TOKEN_COUNT_REG(txq->id), 0); 3130c5aff182SThomas Petazzoni 3131c5aff182SThomas Petazzoni /* Set Tx descriptors queue starting address and size */ 3132c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_TXQ_BASE_ADDR_REG(txq->id), 0); 3133c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_TXQ_SIZE_REG(txq->id), 0); 3134c5aff182SThomas Petazzoni } 3135c5aff182SThomas Petazzoni 31364a188a63SJisheng Zhang static void mvneta_txq_deinit(struct mvneta_port *pp, 31374a188a63SJisheng Zhang struct mvneta_tx_queue *txq) 31384a188a63SJisheng Zhang { 31394a188a63SJisheng Zhang mvneta_txq_sw_deinit(pp, txq); 31404a188a63SJisheng Zhang mvneta_txq_hw_deinit(pp, txq); 31414a188a63SJisheng Zhang } 31424a188a63SJisheng Zhang 3143c5aff182SThomas Petazzoni /* Cleanup all Tx queues */ 3144c5aff182SThomas Petazzoni static void mvneta_cleanup_txqs(struct mvneta_port *pp) 3145c5aff182SThomas Petazzoni { 3146c5aff182SThomas Petazzoni int queue; 3147c5aff182SThomas Petazzoni 3148c5aff182SThomas Petazzoni for (queue = 0; queue < txq_number; queue++) 3149c5aff182SThomas Petazzoni mvneta_txq_deinit(pp, &pp->txqs[queue]); 3150c5aff182SThomas Petazzoni } 3151c5aff182SThomas Petazzoni 3152c5aff182SThomas Petazzoni /* Cleanup all Rx queues */ 3153c5aff182SThomas Petazzoni static void mvneta_cleanup_rxqs(struct mvneta_port *pp) 3154c5aff182SThomas Petazzoni { 31552dcf75e2SGregory CLEMENT int queue; 31562dcf75e2SGregory CLEMENT 3157ca5902a6SYelena Krivosheev for (queue = 0; queue < rxq_number; queue++) 31582dcf75e2SGregory CLEMENT mvneta_rxq_deinit(pp, &pp->rxqs[queue]); 3159c5aff182SThomas Petazzoni } 3160c5aff182SThomas Petazzoni 3161c5aff182SThomas Petazzoni 3162c5aff182SThomas Petazzoni /* Init all Rx queues */ 3163c5aff182SThomas Petazzoni static int mvneta_setup_rxqs(struct mvneta_port *pp) 3164c5aff182SThomas Petazzoni { 31652dcf75e2SGregory CLEMENT int queue; 31662dcf75e2SGregory CLEMENT 31672dcf75e2SGregory CLEMENT for (queue = 0; queue < rxq_number; queue++) { 31682dcf75e2SGregory CLEMENT int err = mvneta_rxq_init(pp, &pp->rxqs[queue]); 31692dcf75e2SGregory CLEMENT 3170c5aff182SThomas Petazzoni if (err) { 3171c5aff182SThomas Petazzoni netdev_err(pp->dev, "%s: can't create rxq=%d\n", 31722dcf75e2SGregory CLEMENT __func__, queue); 3173c5aff182SThomas Petazzoni mvneta_cleanup_rxqs(pp); 3174c5aff182SThomas Petazzoni return err; 3175c5aff182SThomas Petazzoni } 31762dcf75e2SGregory CLEMENT } 3177c5aff182SThomas Petazzoni 3178c5aff182SThomas Petazzoni return 0; 3179c5aff182SThomas Petazzoni } 3180c5aff182SThomas Petazzoni 3181c5aff182SThomas Petazzoni /* Init all tx queues */ 3182c5aff182SThomas Petazzoni static int mvneta_setup_txqs(struct mvneta_port *pp) 3183c5aff182SThomas Petazzoni { 3184c5aff182SThomas Petazzoni int queue; 3185c5aff182SThomas Petazzoni 3186c5aff182SThomas Petazzoni for (queue = 0; queue < txq_number; queue++) { 3187c5aff182SThomas Petazzoni int err = mvneta_txq_init(pp, &pp->txqs[queue]); 3188c5aff182SThomas Petazzoni if (err) { 3189c5aff182SThomas Petazzoni netdev_err(pp->dev, "%s: can't create txq=%d\n", 3190c5aff182SThomas Petazzoni __func__, queue); 3191c5aff182SThomas Petazzoni mvneta_cleanup_txqs(pp); 3192c5aff182SThomas Petazzoni return err; 3193c5aff182SThomas Petazzoni } 3194c5aff182SThomas Petazzoni } 3195c5aff182SThomas Petazzoni 3196c5aff182SThomas Petazzoni return 0; 3197c5aff182SThomas Petazzoni } 3198c5aff182SThomas Petazzoni 3199031b922bSMarek Behún static int mvneta_comphy_init(struct mvneta_port *pp) 3200031b922bSMarek Behún { 3201031b922bSMarek Behún int ret; 3202031b922bSMarek Behún 3203031b922bSMarek Behún if (!pp->comphy) 3204031b922bSMarek Behún return 0; 3205031b922bSMarek Behún 3206031b922bSMarek Behún ret = phy_set_mode_ext(pp->comphy, PHY_MODE_ETHERNET, 3207031b922bSMarek Behún pp->phy_interface); 3208031b922bSMarek Behún if (ret) 3209031b922bSMarek Behún return ret; 3210031b922bSMarek Behún 3211031b922bSMarek Behún return phy_power_on(pp->comphy); 3212031b922bSMarek Behún } 3213031b922bSMarek Behún 3214c5aff182SThomas Petazzoni static void mvneta_start_dev(struct mvneta_port *pp) 3215c5aff182SThomas Petazzoni { 32166b125d63SGregory CLEMENT int cpu; 321712bb03b4SMaxime Ripard 3218031b922bSMarek Behún WARN_ON(mvneta_comphy_init(pp)); 3219a10c1c81SRussell King 3220c5aff182SThomas Petazzoni mvneta_max_rx_size_set(pp, pp->pkt_size); 3221c5aff182SThomas Petazzoni mvneta_txq_max_tx_size_set(pp, pp->pkt_size); 3222c5aff182SThomas Petazzoni 3223c5aff182SThomas Petazzoni /* start the Rx/Tx activity */ 3224c5aff182SThomas Petazzoni mvneta_port_enable(pp); 3225c5aff182SThomas Petazzoni 32262636ac3cSMarcin Wojtas if (!pp->neta_armada3700) { 3227c5aff182SThomas Petazzoni /* Enable polling on the port */ 3228129219e4SGregory CLEMENT for_each_online_cpu(cpu) { 32292636ac3cSMarcin Wojtas struct mvneta_pcpu_port *port = 32302636ac3cSMarcin Wojtas per_cpu_ptr(pp->ports, cpu); 323112bb03b4SMaxime Ripard 323212bb03b4SMaxime Ripard napi_enable(&port->napi); 323312bb03b4SMaxime Ripard } 32342636ac3cSMarcin Wojtas } else { 32352636ac3cSMarcin Wojtas napi_enable(&pp->napi); 32362636ac3cSMarcin Wojtas } 3237c5aff182SThomas Petazzoni 32382dcf75e2SGregory CLEMENT /* Unmask interrupts. It has to be done from each CPU */ 32396b125d63SGregory CLEMENT on_each_cpu(mvneta_percpu_unmask_interrupt, pp, true); 32406b125d63SGregory CLEMENT 3241898b2970SStas Sergeev mvreg_write(pp, MVNETA_INTR_MISC_MASK, 3242898b2970SStas Sergeev MVNETA_CAUSE_PHY_STATUS_CHANGE | 3243856b2cc5SRussell King MVNETA_CAUSE_LINK_CHANGE); 3244c5aff182SThomas Petazzoni 3245503f9aa9SRussell King phylink_start(pp->phylink); 3246c5aff182SThomas Petazzoni netif_tx_start_all_queues(pp->dev); 3247c5aff182SThomas Petazzoni } 3248c5aff182SThomas Petazzoni 3249c5aff182SThomas Petazzoni static void mvneta_stop_dev(struct mvneta_port *pp) 3250c5aff182SThomas Petazzoni { 325112bb03b4SMaxime Ripard unsigned int cpu; 325212bb03b4SMaxime Ripard 3253503f9aa9SRussell King phylink_stop(pp->phylink); 3254c5aff182SThomas Petazzoni 32552636ac3cSMarcin Wojtas if (!pp->neta_armada3700) { 3256129219e4SGregory CLEMENT for_each_online_cpu(cpu) { 32572636ac3cSMarcin Wojtas struct mvneta_pcpu_port *port = 32582636ac3cSMarcin Wojtas per_cpu_ptr(pp->ports, cpu); 325912bb03b4SMaxime Ripard 326012bb03b4SMaxime Ripard napi_disable(&port->napi); 326112bb03b4SMaxime Ripard } 32622636ac3cSMarcin Wojtas } else { 32632636ac3cSMarcin Wojtas napi_disable(&pp->napi); 32642636ac3cSMarcin Wojtas } 3265c5aff182SThomas Petazzoni 3266c5aff182SThomas Petazzoni netif_carrier_off(pp->dev); 3267c5aff182SThomas Petazzoni 3268c5aff182SThomas Petazzoni mvneta_port_down(pp); 3269c5aff182SThomas Petazzoni netif_tx_stop_all_queues(pp->dev); 3270c5aff182SThomas Petazzoni 3271c5aff182SThomas Petazzoni /* Stop the port activity */ 3272c5aff182SThomas Petazzoni mvneta_port_disable(pp); 3273c5aff182SThomas Petazzoni 3274c5aff182SThomas Petazzoni /* Clear all ethernet port interrupts */ 3275db488c10SGregory CLEMENT on_each_cpu(mvneta_percpu_clear_intr_cause, pp, true); 3276c5aff182SThomas Petazzoni 3277c5aff182SThomas Petazzoni /* Mask all ethernet port interrupts */ 3278db488c10SGregory CLEMENT on_each_cpu(mvneta_percpu_mask_interrupt, pp, true); 3279c5aff182SThomas Petazzoni 3280c5aff182SThomas Petazzoni mvneta_tx_reset(pp); 3281c5aff182SThomas Petazzoni mvneta_rx_reset(pp); 3282a10c1c81SRussell King 3283a10c1c81SRussell King WARN_ON(phy_power_off(pp->comphy)); 3284c5aff182SThomas Petazzoni } 3285c5aff182SThomas Petazzoni 3286db5dd0dbSMarcin Wojtas static void mvneta_percpu_enable(void *arg) 3287db5dd0dbSMarcin Wojtas { 3288db5dd0dbSMarcin Wojtas struct mvneta_port *pp = arg; 3289db5dd0dbSMarcin Wojtas 3290db5dd0dbSMarcin Wojtas enable_percpu_irq(pp->dev->irq, IRQ_TYPE_NONE); 3291db5dd0dbSMarcin Wojtas } 3292db5dd0dbSMarcin Wojtas 3293db5dd0dbSMarcin Wojtas static void mvneta_percpu_disable(void *arg) 3294db5dd0dbSMarcin Wojtas { 3295db5dd0dbSMarcin Wojtas struct mvneta_port *pp = arg; 3296db5dd0dbSMarcin Wojtas 3297db5dd0dbSMarcin Wojtas disable_percpu_irq(pp->dev->irq); 3298db5dd0dbSMarcin Wojtas } 3299db5dd0dbSMarcin Wojtas 3300c5aff182SThomas Petazzoni /* Change the device mtu */ 3301c5aff182SThomas Petazzoni static int mvneta_change_mtu(struct net_device *dev, int mtu) 3302c5aff182SThomas Petazzoni { 3303c5aff182SThomas Petazzoni struct mvneta_port *pp = netdev_priv(dev); 3304c5aff182SThomas Petazzoni int ret; 3305c5aff182SThomas Petazzoni 33065777987eSJarod Wilson if (!IS_ALIGNED(MVNETA_RX_PKT_SIZE(mtu), 8)) { 33075777987eSJarod Wilson netdev_info(dev, "Illegal MTU value %d, rounding to %d\n", 33085777987eSJarod Wilson mtu, ALIGN(MVNETA_RX_PKT_SIZE(mtu), 8)); 33095777987eSJarod Wilson mtu = ALIGN(MVNETA_RX_PKT_SIZE(mtu), 8); 33105777987eSJarod Wilson } 3311c5aff182SThomas Petazzoni 3312c5aff182SThomas Petazzoni dev->mtu = mtu; 3313c5aff182SThomas Petazzoni 3314b65657fcSSimon Guinot if (!netif_running(dev)) { 3315dc35a10fSMarcin Wojtas if (pp->bm_priv) 3316dc35a10fSMarcin Wojtas mvneta_bm_update_mtu(pp, mtu); 3317dc35a10fSMarcin Wojtas 3318b65657fcSSimon Guinot netdev_update_features(dev); 3319c5aff182SThomas Petazzoni return 0; 3320b65657fcSSimon Guinot } 3321c5aff182SThomas Petazzoni 33226a20c175SThomas Petazzoni /* The interface is running, so we have to force a 3323a92dbd96SEzequiel Garcia * reallocation of the queues 3324c5aff182SThomas Petazzoni */ 3325c5aff182SThomas Petazzoni mvneta_stop_dev(pp); 3326db5dd0dbSMarcin Wojtas on_each_cpu(mvneta_percpu_disable, pp, true); 3327c5aff182SThomas Petazzoni 3328c5aff182SThomas Petazzoni mvneta_cleanup_txqs(pp); 3329c5aff182SThomas Petazzoni mvneta_cleanup_rxqs(pp); 3330c5aff182SThomas Petazzoni 3331dc35a10fSMarcin Wojtas if (pp->bm_priv) 3332dc35a10fSMarcin Wojtas mvneta_bm_update_mtu(pp, mtu); 3333dc35a10fSMarcin Wojtas 3334a92dbd96SEzequiel Garcia pp->pkt_size = MVNETA_RX_PKT_SIZE(dev->mtu); 3335c5aff182SThomas Petazzoni 3336c5aff182SThomas Petazzoni ret = mvneta_setup_rxqs(pp); 3337c5aff182SThomas Petazzoni if (ret) { 3338a92dbd96SEzequiel Garcia netdev_err(dev, "unable to setup rxqs after MTU change\n"); 3339c5aff182SThomas Petazzoni return ret; 3340c5aff182SThomas Petazzoni } 3341c5aff182SThomas Petazzoni 3342a92dbd96SEzequiel Garcia ret = mvneta_setup_txqs(pp); 3343a92dbd96SEzequiel Garcia if (ret) { 3344a92dbd96SEzequiel Garcia netdev_err(dev, "unable to setup txqs after MTU change\n"); 3345a92dbd96SEzequiel Garcia return ret; 3346a92dbd96SEzequiel Garcia } 3347c5aff182SThomas Petazzoni 3348db5dd0dbSMarcin Wojtas on_each_cpu(mvneta_percpu_enable, pp, true); 3349c5aff182SThomas Petazzoni mvneta_start_dev(pp); 3350c5aff182SThomas Petazzoni 3351b65657fcSSimon Guinot netdev_update_features(dev); 3352b65657fcSSimon Guinot 3353c5aff182SThomas Petazzoni return 0; 3354c5aff182SThomas Petazzoni } 3355c5aff182SThomas Petazzoni 3356b65657fcSSimon Guinot static netdev_features_t mvneta_fix_features(struct net_device *dev, 3357b65657fcSSimon Guinot netdev_features_t features) 3358b65657fcSSimon Guinot { 3359b65657fcSSimon Guinot struct mvneta_port *pp = netdev_priv(dev); 3360b65657fcSSimon Guinot 3361b65657fcSSimon Guinot if (pp->tx_csum_limit && dev->mtu > pp->tx_csum_limit) { 3362b65657fcSSimon Guinot features &= ~(NETIF_F_IP_CSUM | NETIF_F_TSO); 3363b65657fcSSimon Guinot netdev_info(dev, 3364b65657fcSSimon Guinot "Disable IP checksum for MTU greater than %dB\n", 3365b65657fcSSimon Guinot pp->tx_csum_limit); 3366b65657fcSSimon Guinot } 3367b65657fcSSimon Guinot 3368b65657fcSSimon Guinot return features; 3369b65657fcSSimon Guinot } 3370b65657fcSSimon Guinot 33718cc3e439SThomas Petazzoni /* Get mac address */ 33728cc3e439SThomas Petazzoni static void mvneta_get_mac_addr(struct mvneta_port *pp, unsigned char *addr) 33738cc3e439SThomas Petazzoni { 33748cc3e439SThomas Petazzoni u32 mac_addr_l, mac_addr_h; 33758cc3e439SThomas Petazzoni 33768cc3e439SThomas Petazzoni mac_addr_l = mvreg_read(pp, MVNETA_MAC_ADDR_LOW); 33778cc3e439SThomas Petazzoni mac_addr_h = mvreg_read(pp, MVNETA_MAC_ADDR_HIGH); 33788cc3e439SThomas Petazzoni addr[0] = (mac_addr_h >> 24) & 0xFF; 33798cc3e439SThomas Petazzoni addr[1] = (mac_addr_h >> 16) & 0xFF; 33808cc3e439SThomas Petazzoni addr[2] = (mac_addr_h >> 8) & 0xFF; 33818cc3e439SThomas Petazzoni addr[3] = mac_addr_h & 0xFF; 33828cc3e439SThomas Petazzoni addr[4] = (mac_addr_l >> 8) & 0xFF; 33838cc3e439SThomas Petazzoni addr[5] = mac_addr_l & 0xFF; 33848cc3e439SThomas Petazzoni } 33858cc3e439SThomas Petazzoni 3386c5aff182SThomas Petazzoni /* Handle setting mac address */ 3387c5aff182SThomas Petazzoni static int mvneta_set_mac_addr(struct net_device *dev, void *addr) 3388c5aff182SThomas Petazzoni { 3389c5aff182SThomas Petazzoni struct mvneta_port *pp = netdev_priv(dev); 3390e68de360SEzequiel Garcia struct sockaddr *sockaddr = addr; 3391e68de360SEzequiel Garcia int ret; 3392c5aff182SThomas Petazzoni 3393e68de360SEzequiel Garcia ret = eth_prepare_mac_addr_change(dev, addr); 3394e68de360SEzequiel Garcia if (ret < 0) 3395e68de360SEzequiel Garcia return ret; 3396c5aff182SThomas Petazzoni /* Remove previous address table entry */ 3397c5aff182SThomas Petazzoni mvneta_mac_addr_set(pp, dev->dev_addr, -1); 3398c5aff182SThomas Petazzoni 3399c5aff182SThomas Petazzoni /* Set new addr in hw */ 340090b74c01SGregory CLEMENT mvneta_mac_addr_set(pp, sockaddr->sa_data, pp->rxq_def); 3401c5aff182SThomas Petazzoni 3402e68de360SEzequiel Garcia eth_commit_mac_addr_change(dev, addr); 3403c5aff182SThomas Petazzoni return 0; 3404c5aff182SThomas Petazzoni } 3405c5aff182SThomas Petazzoni 340644cc27e4SIoana Ciornei static void mvneta_validate(struct phylink_config *config, 340744cc27e4SIoana Ciornei unsigned long *supported, 3408503f9aa9SRussell King struct phylink_link_state *state) 3409503f9aa9SRussell King { 341044cc27e4SIoana Ciornei struct net_device *ndev = to_net_dev(config->dev); 3411a10c1c81SRussell King struct mvneta_port *pp = netdev_priv(ndev); 3412503f9aa9SRussell King __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, }; 3413503f9aa9SRussell King 341422f4bf8aSRussell King /* We only support QSGMII, SGMII, 802.3z and RGMII modes */ 3415503f9aa9SRussell King if (state->interface != PHY_INTERFACE_MODE_NA && 3416503f9aa9SRussell King state->interface != PHY_INTERFACE_MODE_QSGMII && 3417503f9aa9SRussell King state->interface != PHY_INTERFACE_MODE_SGMII && 341822f4bf8aSRussell King !phy_interface_mode_is_8023z(state->interface) && 3419503f9aa9SRussell King !phy_interface_mode_is_rgmii(state->interface)) { 3420503f9aa9SRussell King bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS); 3421503f9aa9SRussell King return; 3422503f9aa9SRussell King } 3423503f9aa9SRussell King 3424503f9aa9SRussell King /* Allow all the expected bits */ 3425503f9aa9SRussell King phylink_set(mask, Autoneg); 3426503f9aa9SRussell King phylink_set_port_modes(mask); 3427503f9aa9SRussell King 34284932a918SRussell King /* Asymmetric pause is unsupported */ 34294932a918SRussell King phylink_set(mask, Pause); 3430da58a931SMaxime Chevallier 343183e65df6SMaxime Chevallier /* Half-duplex at speeds higher than 100Mbit is unsupported */ 3432a10c1c81SRussell King if (pp->comphy || state->interface != PHY_INTERFACE_MODE_2500BASEX) { 3433503f9aa9SRussell King phylink_set(mask, 1000baseT_Full); 3434503f9aa9SRussell King phylink_set(mask, 1000baseX_Full); 3435a10c1c81SRussell King } 3436a10c1c81SRussell King if (pp->comphy || state->interface == PHY_INTERFACE_MODE_2500BASEX) { 3437eda3d1b0SMaxime Chevallier phylink_set(mask, 2500baseT_Full); 3438a10c1c81SRussell King phylink_set(mask, 2500baseX_Full); 3439a10c1c81SRussell King } 344022f4bf8aSRussell King 344122f4bf8aSRussell King if (!phy_interface_mode_is_8023z(state->interface)) { 344222f4bf8aSRussell King /* 10M and 100M are only supported in non-802.3z mode */ 3443503f9aa9SRussell King phylink_set(mask, 10baseT_Half); 3444503f9aa9SRussell King phylink_set(mask, 10baseT_Full); 3445503f9aa9SRussell King phylink_set(mask, 100baseT_Half); 3446503f9aa9SRussell King phylink_set(mask, 100baseT_Full); 344722f4bf8aSRussell King } 3448503f9aa9SRussell King 3449503f9aa9SRussell King bitmap_and(supported, supported, mask, 3450503f9aa9SRussell King __ETHTOOL_LINK_MODE_MASK_NBITS); 3451503f9aa9SRussell King bitmap_and(state->advertising, state->advertising, mask, 3452503f9aa9SRussell King __ETHTOOL_LINK_MODE_MASK_NBITS); 3453a10c1c81SRussell King 3454a10c1c81SRussell King /* We can only operate at 2500BaseX or 1000BaseX. If requested 3455a10c1c81SRussell King * to advertise both, only report advertising at 2500BaseX. 3456a10c1c81SRussell King */ 3457a10c1c81SRussell King phylink_helper_basex_speed(state); 3458503f9aa9SRussell King } 3459503f9aa9SRussell King 346044cc27e4SIoana Ciornei static int mvneta_mac_link_state(struct phylink_config *config, 3461503f9aa9SRussell King struct phylink_link_state *state) 3462c5aff182SThomas Petazzoni { 346344cc27e4SIoana Ciornei struct net_device *ndev = to_net_dev(config->dev); 3464c5aff182SThomas Petazzoni struct mvneta_port *pp = netdev_priv(ndev); 3465503f9aa9SRussell King u32 gmac_stat; 3466c5aff182SThomas Petazzoni 3467503f9aa9SRussell King gmac_stat = mvreg_read(pp, MVNETA_GMAC_STATUS); 3468503f9aa9SRussell King 3469503f9aa9SRussell King if (gmac_stat & MVNETA_GMAC_SPEED_1000) 3470a10c1c81SRussell King state->speed = 3471a10c1c81SRussell King state->interface == PHY_INTERFACE_MODE_2500BASEX ? 3472a10c1c81SRussell King SPEED_2500 : SPEED_1000; 3473503f9aa9SRussell King else if (gmac_stat & MVNETA_GMAC_SPEED_100) 3474503f9aa9SRussell King state->speed = SPEED_100; 3475503f9aa9SRussell King else 3476503f9aa9SRussell King state->speed = SPEED_10; 3477503f9aa9SRussell King 3478503f9aa9SRussell King state->an_complete = !!(gmac_stat & MVNETA_GMAC_AN_COMPLETE); 3479503f9aa9SRussell King state->link = !!(gmac_stat & MVNETA_GMAC_LINK_UP); 3480503f9aa9SRussell King state->duplex = !!(gmac_stat & MVNETA_GMAC_FULL_DUPLEX); 3481503f9aa9SRussell King 3482503f9aa9SRussell King state->pause = 0; 34834932a918SRussell King if (gmac_stat & MVNETA_GMAC_RX_FLOW_CTRL_ENABLE) 34844932a918SRussell King state->pause |= MLO_PAUSE_RX; 34854932a918SRussell King if (gmac_stat & MVNETA_GMAC_TX_FLOW_CTRL_ENABLE) 34864932a918SRussell King state->pause |= MLO_PAUSE_TX; 3487503f9aa9SRussell King 3488503f9aa9SRussell King return 1; 3489503f9aa9SRussell King } 3490503f9aa9SRussell King 349144cc27e4SIoana Ciornei static void mvneta_mac_an_restart(struct phylink_config *config) 349222f4bf8aSRussell King { 349344cc27e4SIoana Ciornei struct net_device *ndev = to_net_dev(config->dev); 349422f4bf8aSRussell King struct mvneta_port *pp = netdev_priv(ndev); 349522f4bf8aSRussell King u32 gmac_an = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG); 349622f4bf8aSRussell King 349722f4bf8aSRussell King mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, 349822f4bf8aSRussell King gmac_an | MVNETA_GMAC_INBAND_RESTART_AN); 349922f4bf8aSRussell King mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, 350022f4bf8aSRussell King gmac_an & ~MVNETA_GMAC_INBAND_RESTART_AN); 350122f4bf8aSRussell King } 350222f4bf8aSRussell King 350344cc27e4SIoana Ciornei static void mvneta_mac_config(struct phylink_config *config, unsigned int mode, 3504503f9aa9SRussell King const struct phylink_link_state *state) 3505503f9aa9SRussell King { 350644cc27e4SIoana Ciornei struct net_device *ndev = to_net_dev(config->dev); 3507503f9aa9SRussell King struct mvneta_port *pp = netdev_priv(ndev); 350822f4bf8aSRussell King u32 new_ctrl0, gmac_ctrl0 = mvreg_read(pp, MVNETA_GMAC_CTRL_0); 3509503f9aa9SRussell King u32 new_ctrl2, gmac_ctrl2 = mvreg_read(pp, MVNETA_GMAC_CTRL_2); 3510da58a931SMaxime Chevallier u32 new_ctrl4, gmac_ctrl4 = mvreg_read(pp, MVNETA_GMAC_CTRL_4); 3511503f9aa9SRussell King u32 new_clk, gmac_clk = mvreg_read(pp, MVNETA_GMAC_CLOCK_DIVIDER); 3512503f9aa9SRussell King u32 new_an, gmac_an = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG); 3513503f9aa9SRussell King 351422f4bf8aSRussell King new_ctrl0 = gmac_ctrl0 & ~MVNETA_GMAC0_PORT_1000BASE_X; 351532699954SRussell King new_ctrl2 = gmac_ctrl2 & ~(MVNETA_GMAC2_INBAND_AN_ENABLE | 351632699954SRussell King MVNETA_GMAC2_PORT_RESET); 3517da58a931SMaxime Chevallier new_ctrl4 = gmac_ctrl4 & ~(MVNETA_GMAC4_SHORT_PREAMBLE_ENABLE); 3518503f9aa9SRussell King new_clk = gmac_clk & ~MVNETA_GMAC_1MS_CLOCK_ENABLE; 3519503f9aa9SRussell King new_an = gmac_an & ~(MVNETA_GMAC_INBAND_AN_ENABLE | 3520503f9aa9SRussell King MVNETA_GMAC_INBAND_RESTART_AN | 3521503f9aa9SRussell King MVNETA_GMAC_CONFIG_MII_SPEED | 3522c5aff182SThomas Petazzoni MVNETA_GMAC_CONFIG_GMII_SPEED | 3523503f9aa9SRussell King MVNETA_GMAC_AN_SPEED_EN | 352422f4bf8aSRussell King MVNETA_GMAC_ADVERT_SYM_FLOW_CTRL | 352522f4bf8aSRussell King MVNETA_GMAC_CONFIG_FLOW_CTRL | 3526503f9aa9SRussell King MVNETA_GMAC_AN_FLOW_CTRL_EN | 3527503f9aa9SRussell King MVNETA_GMAC_CONFIG_FULL_DUPLEX | 3528503f9aa9SRussell King MVNETA_GMAC_AN_DUPLEX_EN); 3529c5aff182SThomas Petazzoni 353032699954SRussell King /* Even though it might look weird, when we're configured in 353132699954SRussell King * SGMII or QSGMII mode, the RGMII bit needs to be set. 353232699954SRussell King */ 353332699954SRussell King new_ctrl2 |= MVNETA_GMAC2_PORT_RGMII; 353432699954SRussell King 353532699954SRussell King if (state->interface == PHY_INTERFACE_MODE_QSGMII || 353622f4bf8aSRussell King state->interface == PHY_INTERFACE_MODE_SGMII || 353722f4bf8aSRussell King phy_interface_mode_is_8023z(state->interface)) 353832699954SRussell King new_ctrl2 |= MVNETA_GMAC2_PCS_ENABLE; 353932699954SRussell King 35404932a918SRussell King if (phylink_test(state->advertising, Pause)) 35414932a918SRussell King new_an |= MVNETA_GMAC_ADVERT_SYM_FLOW_CTRL; 35424932a918SRussell King if (state->pause & MLO_PAUSE_TXRX_MASK) 35434932a918SRussell King new_an |= MVNETA_GMAC_CONFIG_FLOW_CTRL; 35444932a918SRussell King 3545503f9aa9SRussell King if (!phylink_autoneg_inband(mode)) { 3546503f9aa9SRussell King /* Phy or fixed speed */ 3547503f9aa9SRussell King if (state->duplex) 3548503f9aa9SRussell King new_an |= MVNETA_GMAC_CONFIG_FULL_DUPLEX; 3549c5aff182SThomas Petazzoni 3550da58a931SMaxime Chevallier if (state->speed == SPEED_1000 || state->speed == SPEED_2500) 3551503f9aa9SRussell King new_an |= MVNETA_GMAC_CONFIG_GMII_SPEED; 3552503f9aa9SRussell King else if (state->speed == SPEED_100) 3553503f9aa9SRussell King new_an |= MVNETA_GMAC_CONFIG_MII_SPEED; 355422f4bf8aSRussell King } else if (state->interface == PHY_INTERFACE_MODE_SGMII) { 3555503f9aa9SRussell King /* SGMII mode receives the state from the PHY */ 3556503f9aa9SRussell King new_ctrl2 |= MVNETA_GMAC2_INBAND_AN_ENABLE; 3557503f9aa9SRussell King new_clk |= MVNETA_GMAC_1MS_CLOCK_ENABLE; 3558503f9aa9SRussell King new_an = (new_an & ~(MVNETA_GMAC_FORCE_LINK_DOWN | 3559503f9aa9SRussell King MVNETA_GMAC_FORCE_LINK_PASS)) | 3560503f9aa9SRussell King MVNETA_GMAC_INBAND_AN_ENABLE | 3561503f9aa9SRussell King MVNETA_GMAC_AN_SPEED_EN | 3562503f9aa9SRussell King MVNETA_GMAC_AN_DUPLEX_EN; 356322f4bf8aSRussell King } else { 356422f4bf8aSRussell King /* 802.3z negotiation - only 1000base-X */ 356522f4bf8aSRussell King new_ctrl0 |= MVNETA_GMAC0_PORT_1000BASE_X; 356622f4bf8aSRussell King new_clk |= MVNETA_GMAC_1MS_CLOCK_ENABLE; 356722f4bf8aSRussell King new_an = (new_an & ~(MVNETA_GMAC_FORCE_LINK_DOWN | 356822f4bf8aSRussell King MVNETA_GMAC_FORCE_LINK_PASS)) | 356922f4bf8aSRussell King MVNETA_GMAC_INBAND_AN_ENABLE | 357022f4bf8aSRussell King MVNETA_GMAC_CONFIG_GMII_SPEED | 357122f4bf8aSRussell King /* The MAC only supports FD mode */ 357222f4bf8aSRussell King MVNETA_GMAC_CONFIG_FULL_DUPLEX; 35734932a918SRussell King 35744932a918SRussell King if (state->pause & MLO_PAUSE_AN && state->an_enabled) 35754932a918SRussell King new_an |= MVNETA_GMAC_AN_FLOW_CTRL_EN; 3576c5aff182SThomas Petazzoni } 3577c5aff182SThomas Petazzoni 3578503f9aa9SRussell King /* Armada 370 documentation says we can only change the port mode 3579503f9aa9SRussell King * and in-band enable when the link is down, so force it down 3580503f9aa9SRussell King * while making these changes. We also do this for GMAC_CTRL2 */ 358122f4bf8aSRussell King if ((new_ctrl0 ^ gmac_ctrl0) & MVNETA_GMAC0_PORT_1000BASE_X || 358222f4bf8aSRussell King (new_ctrl2 ^ gmac_ctrl2) & MVNETA_GMAC2_INBAND_AN_ENABLE || 3583503f9aa9SRussell King (new_an ^ gmac_an) & MVNETA_GMAC_INBAND_AN_ENABLE) { 3584503f9aa9SRussell King mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, 3585503f9aa9SRussell King (gmac_an & ~MVNETA_GMAC_FORCE_LINK_PASS) | 3586503f9aa9SRussell King MVNETA_GMAC_FORCE_LINK_DOWN); 3587503f9aa9SRussell King } 3588503f9aa9SRussell King 3589a10c1c81SRussell King 3590da58a931SMaxime Chevallier /* When at 2.5G, the link partner can send frames with shortened 3591da58a931SMaxime Chevallier * preambles. 3592da58a931SMaxime Chevallier */ 3593da58a931SMaxime Chevallier if (state->speed == SPEED_2500) 3594da58a931SMaxime Chevallier new_ctrl4 |= MVNETA_GMAC4_SHORT_PREAMBLE_ENABLE; 3595da58a931SMaxime Chevallier 3596031b922bSMarek Behún if (pp->comphy && pp->phy_interface != state->interface && 3597a10c1c81SRussell King (state->interface == PHY_INTERFACE_MODE_SGMII || 3598a10c1c81SRussell King state->interface == PHY_INTERFACE_MODE_1000BASEX || 3599031b922bSMarek Behún state->interface == PHY_INTERFACE_MODE_2500BASEX)) { 3600031b922bSMarek Behún pp->phy_interface = state->interface; 3601031b922bSMarek Behún 3602031b922bSMarek Behún WARN_ON(phy_power_off(pp->comphy)); 3603031b922bSMarek Behún WARN_ON(mvneta_comphy_init(pp)); 3604031b922bSMarek Behún } 3605a10c1c81SRussell King 360622f4bf8aSRussell King if (new_ctrl0 != gmac_ctrl0) 360722f4bf8aSRussell King mvreg_write(pp, MVNETA_GMAC_CTRL_0, new_ctrl0); 3608503f9aa9SRussell King if (new_ctrl2 != gmac_ctrl2) 3609503f9aa9SRussell King mvreg_write(pp, MVNETA_GMAC_CTRL_2, new_ctrl2); 3610da58a931SMaxime Chevallier if (new_ctrl4 != gmac_ctrl4) 3611da58a931SMaxime Chevallier mvreg_write(pp, MVNETA_GMAC_CTRL_4, new_ctrl4); 3612503f9aa9SRussell King if (new_clk != gmac_clk) 3613503f9aa9SRussell King mvreg_write(pp, MVNETA_GMAC_CLOCK_DIVIDER, new_clk); 3614503f9aa9SRussell King if (new_an != gmac_an) 3615503f9aa9SRussell King mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, new_an); 361632699954SRussell King 361732699954SRussell King if (gmac_ctrl2 & MVNETA_GMAC2_PORT_RESET) { 361832699954SRussell King while ((mvreg_read(pp, MVNETA_GMAC_CTRL_2) & 361932699954SRussell King MVNETA_GMAC2_PORT_RESET) != 0) 362032699954SRussell King continue; 362132699954SRussell King } 3622503f9aa9SRussell King } 3623503f9aa9SRussell King 36246d81f451SRussell King static void mvneta_set_eee(struct mvneta_port *pp, bool enable) 36256d81f451SRussell King { 36266d81f451SRussell King u32 lpi_ctl1; 36276d81f451SRussell King 36286d81f451SRussell King lpi_ctl1 = mvreg_read(pp, MVNETA_LPI_CTRL_1); 36296d81f451SRussell King if (enable) 36306d81f451SRussell King lpi_ctl1 |= MVNETA_LPI_REQUEST_ENABLE; 36316d81f451SRussell King else 36326d81f451SRussell King lpi_ctl1 &= ~MVNETA_LPI_REQUEST_ENABLE; 36336d81f451SRussell King mvreg_write(pp, MVNETA_LPI_CTRL_1, lpi_ctl1); 36346d81f451SRussell King } 36356d81f451SRussell King 363644cc27e4SIoana Ciornei static void mvneta_mac_link_down(struct phylink_config *config, 363744cc27e4SIoana Ciornei unsigned int mode, phy_interface_t interface) 3638fc548b99SRussell King { 363944cc27e4SIoana Ciornei struct net_device *ndev = to_net_dev(config->dev); 3640fc548b99SRussell King struct mvneta_port *pp = netdev_priv(ndev); 3641fc548b99SRussell King u32 val; 3642fc548b99SRussell King 3643503f9aa9SRussell King mvneta_port_down(pp); 3644503f9aa9SRussell King 3645503f9aa9SRussell King if (!phylink_autoneg_inband(mode)) { 3646fc548b99SRussell King val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG); 3647fc548b99SRussell King val &= ~MVNETA_GMAC_FORCE_LINK_PASS; 3648fc548b99SRussell King val |= MVNETA_GMAC_FORCE_LINK_DOWN; 3649fc548b99SRussell King mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val); 3650fc548b99SRussell King } 36516d81f451SRussell King 36526d81f451SRussell King pp->eee_active = false; 36536d81f451SRussell King mvneta_set_eee(pp, false); 3654fc548b99SRussell King } 3655fc548b99SRussell King 365644cc27e4SIoana Ciornei static void mvneta_mac_link_up(struct phylink_config *config, unsigned int mode, 3657c6ab3008SFlorian Fainelli phy_interface_t interface, 3658503f9aa9SRussell King struct phy_device *phy) 3659fc548b99SRussell King { 366044cc27e4SIoana Ciornei struct net_device *ndev = to_net_dev(config->dev); 3661fc548b99SRussell King struct mvneta_port *pp = netdev_priv(ndev); 3662fc548b99SRussell King u32 val; 3663fc548b99SRussell King 3664503f9aa9SRussell King if (!phylink_autoneg_inband(mode)) { 3665fc548b99SRussell King val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG); 3666fc548b99SRussell King val &= ~MVNETA_GMAC_FORCE_LINK_DOWN; 3667fc548b99SRussell King val |= MVNETA_GMAC_FORCE_LINK_PASS; 3668fc548b99SRussell King mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val); 3669fc548b99SRussell King } 3670fc548b99SRussell King 3671fc548b99SRussell King mvneta_port_up(pp); 36726d81f451SRussell King 36736d81f451SRussell King if (phy && pp->eee_enabled) { 36746d81f451SRussell King pp->eee_active = phy_init_eee(phy, 0) >= 0; 36756d81f451SRussell King mvneta_set_eee(pp, pp->eee_active && pp->tx_lpi_enabled); 36766d81f451SRussell King } 3677fc548b99SRussell King } 3678fc548b99SRussell King 3679503f9aa9SRussell King static const struct phylink_mac_ops mvneta_phylink_ops = { 3680503f9aa9SRussell King .validate = mvneta_validate, 3681503f9aa9SRussell King .mac_link_state = mvneta_mac_link_state, 368222f4bf8aSRussell King .mac_an_restart = mvneta_mac_an_restart, 3683503f9aa9SRussell King .mac_config = mvneta_mac_config, 3684503f9aa9SRussell King .mac_link_down = mvneta_mac_link_down, 3685503f9aa9SRussell King .mac_link_up = mvneta_mac_link_up, 3686503f9aa9SRussell King }; 3687c5aff182SThomas Petazzoni 3688c5aff182SThomas Petazzoni static int mvneta_mdio_probe(struct mvneta_port *pp) 3689c5aff182SThomas Petazzoni { 369082960fffSJisheng Zhang struct ethtool_wolinfo wol = { .cmd = ETHTOOL_GWOL }; 3691503f9aa9SRussell King int err = phylink_of_phy_connect(pp->phylink, pp->dn, 0); 3692c5aff182SThomas Petazzoni 3693503f9aa9SRussell King if (err) 3694503f9aa9SRussell King netdev_err(pp->dev, "could not attach PHY: %d\n", err); 3695c5aff182SThomas Petazzoni 3696503f9aa9SRussell King phylink_ethtool_get_wol(pp->phylink, &wol); 369782960fffSJisheng Zhang device_set_wakeup_capable(&pp->dev->dev, !!wol.supported); 369882960fffSJisheng Zhang 3699503f9aa9SRussell King return err; 3700c5aff182SThomas Petazzoni } 3701c5aff182SThomas Petazzoni 3702c5aff182SThomas Petazzoni static void mvneta_mdio_remove(struct mvneta_port *pp) 3703c5aff182SThomas Petazzoni { 3704503f9aa9SRussell King phylink_disconnect_phy(pp->phylink); 3705c5aff182SThomas Petazzoni } 3706c5aff182SThomas Petazzoni 3707120cfa50SGregory CLEMENT /* Electing a CPU must be done in an atomic way: it should be done 3708120cfa50SGregory CLEMENT * after or before the removal/insertion of a CPU and this function is 3709120cfa50SGregory CLEMENT * not reentrant. 3710120cfa50SGregory CLEMENT */ 3711f8642885SMaxime Ripard static void mvneta_percpu_elect(struct mvneta_port *pp) 3712f8642885SMaxime Ripard { 3713cad5d847SGregory CLEMENT int elected_cpu = 0, max_cpu, cpu, i = 0; 3714f8642885SMaxime Ripard 3715cad5d847SGregory CLEMENT /* Use the cpu associated to the rxq when it is online, in all 3716cad5d847SGregory CLEMENT * the other cases, use the cpu 0 which can't be offline. 3717cad5d847SGregory CLEMENT */ 3718cad5d847SGregory CLEMENT if (cpu_online(pp->rxq_def)) 3719cad5d847SGregory CLEMENT elected_cpu = pp->rxq_def; 3720cad5d847SGregory CLEMENT 37212dcf75e2SGregory CLEMENT max_cpu = num_present_cpus(); 3722f8642885SMaxime Ripard 3723f8642885SMaxime Ripard for_each_online_cpu(cpu) { 37242dcf75e2SGregory CLEMENT int rxq_map = 0, txq_map = 0; 37252dcf75e2SGregory CLEMENT int rxq; 37262dcf75e2SGregory CLEMENT 37272dcf75e2SGregory CLEMENT for (rxq = 0; rxq < rxq_number; rxq++) 37282dcf75e2SGregory CLEMENT if ((rxq % max_cpu) == cpu) 37292dcf75e2SGregory CLEMENT rxq_map |= MVNETA_CPU_RXQ_ACCESS(rxq); 37302dcf75e2SGregory CLEMENT 3731cad5d847SGregory CLEMENT if (cpu == elected_cpu) 373250bf8cb6SGregory CLEMENT /* Map the default receive queue queue to the 373350bf8cb6SGregory CLEMENT * elected CPU 3734f8642885SMaxime Ripard */ 37352dcf75e2SGregory CLEMENT rxq_map |= MVNETA_CPU_RXQ_ACCESS(pp->rxq_def); 373650bf8cb6SGregory CLEMENT 373750bf8cb6SGregory CLEMENT /* We update the TX queue map only if we have one 373850bf8cb6SGregory CLEMENT * queue. In this case we associate the TX queue to 373950bf8cb6SGregory CLEMENT * the CPU bound to the default RX queue 374050bf8cb6SGregory CLEMENT */ 374150bf8cb6SGregory CLEMENT if (txq_number == 1) 3742cad5d847SGregory CLEMENT txq_map = (cpu == elected_cpu) ? 374350bf8cb6SGregory CLEMENT MVNETA_CPU_TXQ_ACCESS(1) : 0; 374450bf8cb6SGregory CLEMENT else 374550bf8cb6SGregory CLEMENT txq_map = mvreg_read(pp, MVNETA_CPU_MAP(cpu)) & 374650bf8cb6SGregory CLEMENT MVNETA_CPU_TXQ_ACCESS_ALL_MASK; 374750bf8cb6SGregory CLEMENT 37482dcf75e2SGregory CLEMENT mvreg_write(pp, MVNETA_CPU_MAP(cpu), rxq_map | txq_map); 37492dcf75e2SGregory CLEMENT 37502dcf75e2SGregory CLEMENT /* Update the interrupt mask on each CPU according the 37512dcf75e2SGregory CLEMENT * new mapping 37522dcf75e2SGregory CLEMENT */ 37532dcf75e2SGregory CLEMENT smp_call_function_single(cpu, mvneta_percpu_unmask_interrupt, 3754f8642885SMaxime Ripard pp, true); 3755f8642885SMaxime Ripard i++; 37562dcf75e2SGregory CLEMENT 3757f8642885SMaxime Ripard } 3758f8642885SMaxime Ripard }; 3759f8642885SMaxime Ripard 376084a3f4dbSSebastian Andrzej Siewior static int mvneta_cpu_online(unsigned int cpu, struct hlist_node *node) 3761f8642885SMaxime Ripard { 376284a3f4dbSSebastian Andrzej Siewior int other_cpu; 376384a3f4dbSSebastian Andrzej Siewior struct mvneta_port *pp = hlist_entry_safe(node, struct mvneta_port, 376484a3f4dbSSebastian Andrzej Siewior node_online); 3765f8642885SMaxime Ripard struct mvneta_pcpu_port *port = per_cpu_ptr(pp->ports, cpu); 3766f8642885SMaxime Ripard 376784a3f4dbSSebastian Andrzej Siewior 3768120cfa50SGregory CLEMENT spin_lock(&pp->lock); 376984a3f4dbSSebastian Andrzej Siewior /* 377084a3f4dbSSebastian Andrzej Siewior * Configuring the driver for a new CPU while the driver is 377184a3f4dbSSebastian Andrzej Siewior * stopping is racy, so just avoid it. 3772120cfa50SGregory CLEMENT */ 3773120cfa50SGregory CLEMENT if (pp->is_stopped) { 3774120cfa50SGregory CLEMENT spin_unlock(&pp->lock); 377584a3f4dbSSebastian Andrzej Siewior return 0; 3776120cfa50SGregory CLEMENT } 3777f8642885SMaxime Ripard netif_tx_stop_all_queues(pp->dev); 3778f8642885SMaxime Ripard 377984a3f4dbSSebastian Andrzej Siewior /* 378084a3f4dbSSebastian Andrzej Siewior * We have to synchronise on tha napi of each CPU except the one 378184a3f4dbSSebastian Andrzej Siewior * just being woken up 3782f8642885SMaxime Ripard */ 3783f8642885SMaxime Ripard for_each_online_cpu(other_cpu) { 3784f8642885SMaxime Ripard if (other_cpu != cpu) { 3785f8642885SMaxime Ripard struct mvneta_pcpu_port *other_port = 3786f8642885SMaxime Ripard per_cpu_ptr(pp->ports, other_cpu); 3787f8642885SMaxime Ripard 3788f8642885SMaxime Ripard napi_synchronize(&other_port->napi); 3789f8642885SMaxime Ripard } 3790f8642885SMaxime Ripard } 3791f8642885SMaxime Ripard 3792f8642885SMaxime Ripard /* Mask all ethernet port interrupts */ 3793db488c10SGregory CLEMENT on_each_cpu(mvneta_percpu_mask_interrupt, pp, true); 3794f8642885SMaxime Ripard napi_enable(&port->napi); 3795f8642885SMaxime Ripard 379684a3f4dbSSebastian Andrzej Siewior /* 379784a3f4dbSSebastian Andrzej Siewior * Enable per-CPU interrupts on the CPU that is 37982dcf75e2SGregory CLEMENT * brought up. 37992dcf75e2SGregory CLEMENT */ 38000e28bf93SAnna-Maria Gleixner mvneta_percpu_enable(pp); 38012dcf75e2SGregory CLEMENT 380284a3f4dbSSebastian Andrzej Siewior /* 380384a3f4dbSSebastian Andrzej Siewior * Enable per-CPU interrupt on the one CPU we care 3804f8642885SMaxime Ripard * about. 3805f8642885SMaxime Ripard */ 3806f8642885SMaxime Ripard mvneta_percpu_elect(pp); 3807f8642885SMaxime Ripard 3808db488c10SGregory CLEMENT /* Unmask all ethernet port interrupts */ 3809db488c10SGregory CLEMENT on_each_cpu(mvneta_percpu_unmask_interrupt, pp, true); 3810f8642885SMaxime Ripard mvreg_write(pp, MVNETA_INTR_MISC_MASK, 3811f8642885SMaxime Ripard MVNETA_CAUSE_PHY_STATUS_CHANGE | 3812856b2cc5SRussell King MVNETA_CAUSE_LINK_CHANGE); 3813f8642885SMaxime Ripard netif_tx_start_all_queues(pp->dev); 3814120cfa50SGregory CLEMENT spin_unlock(&pp->lock); 381584a3f4dbSSebastian Andrzej Siewior return 0; 381684a3f4dbSSebastian Andrzej Siewior } 381784a3f4dbSSebastian Andrzej Siewior 381884a3f4dbSSebastian Andrzej Siewior static int mvneta_cpu_down_prepare(unsigned int cpu, struct hlist_node *node) 381984a3f4dbSSebastian Andrzej Siewior { 382084a3f4dbSSebastian Andrzej Siewior struct mvneta_port *pp = hlist_entry_safe(node, struct mvneta_port, 382184a3f4dbSSebastian Andrzej Siewior node_online); 382284a3f4dbSSebastian Andrzej Siewior struct mvneta_pcpu_port *port = per_cpu_ptr(pp->ports, cpu); 382384a3f4dbSSebastian Andrzej Siewior 382484a3f4dbSSebastian Andrzej Siewior /* 382584a3f4dbSSebastian Andrzej Siewior * Thanks to this lock we are sure that any pending cpu election is 382684a3f4dbSSebastian Andrzej Siewior * done. 38275888511eSGregory CLEMENT */ 38285888511eSGregory CLEMENT spin_lock(&pp->lock); 3829f8642885SMaxime Ripard /* Mask all ethernet port interrupts */ 3830db488c10SGregory CLEMENT on_each_cpu(mvneta_percpu_mask_interrupt, pp, true); 38315888511eSGregory CLEMENT spin_unlock(&pp->lock); 3832f8642885SMaxime Ripard 3833f8642885SMaxime Ripard napi_synchronize(&port->napi); 3834f8642885SMaxime Ripard napi_disable(&port->napi); 383584a3f4dbSSebastian Andrzej Siewior /* Disable per-CPU interrupts on the CPU that is brought down. */ 38360e28bf93SAnna-Maria Gleixner mvneta_percpu_disable(pp); 383784a3f4dbSSebastian Andrzej Siewior return 0; 383884a3f4dbSSebastian Andrzej Siewior } 3839f8642885SMaxime Ripard 384084a3f4dbSSebastian Andrzej Siewior static int mvneta_cpu_dead(unsigned int cpu, struct hlist_node *node) 384184a3f4dbSSebastian Andrzej Siewior { 384284a3f4dbSSebastian Andrzej Siewior struct mvneta_port *pp = hlist_entry_safe(node, struct mvneta_port, 384384a3f4dbSSebastian Andrzej Siewior node_dead); 384484a3f4dbSSebastian Andrzej Siewior 3845f8642885SMaxime Ripard /* Check if a new CPU must be elected now this on is down */ 3846120cfa50SGregory CLEMENT spin_lock(&pp->lock); 3847f8642885SMaxime Ripard mvneta_percpu_elect(pp); 3848120cfa50SGregory CLEMENT spin_unlock(&pp->lock); 3849f8642885SMaxime Ripard /* Unmask all ethernet port interrupts */ 3850db488c10SGregory CLEMENT on_each_cpu(mvneta_percpu_unmask_interrupt, pp, true); 3851f8642885SMaxime Ripard mvreg_write(pp, MVNETA_INTR_MISC_MASK, 3852f8642885SMaxime Ripard MVNETA_CAUSE_PHY_STATUS_CHANGE | 3853856b2cc5SRussell King MVNETA_CAUSE_LINK_CHANGE); 3854f8642885SMaxime Ripard netif_tx_start_all_queues(pp->dev); 385584a3f4dbSSebastian Andrzej Siewior return 0; 3856f8642885SMaxime Ripard } 3857f8642885SMaxime Ripard 3858c5aff182SThomas Petazzoni static int mvneta_open(struct net_device *dev) 3859c5aff182SThomas Petazzoni { 3860c5aff182SThomas Petazzoni struct mvneta_port *pp = netdev_priv(dev); 38616b125d63SGregory CLEMENT int ret; 3862c5aff182SThomas Petazzoni 3863c5aff182SThomas Petazzoni pp->pkt_size = MVNETA_RX_PKT_SIZE(pp->dev->mtu); 3864c5aff182SThomas Petazzoni 3865c5aff182SThomas Petazzoni ret = mvneta_setup_rxqs(pp); 3866c5aff182SThomas Petazzoni if (ret) 3867c5aff182SThomas Petazzoni return ret; 3868c5aff182SThomas Petazzoni 3869c5aff182SThomas Petazzoni ret = mvneta_setup_txqs(pp); 3870c5aff182SThomas Petazzoni if (ret) 3871c5aff182SThomas Petazzoni goto err_cleanup_rxqs; 3872c5aff182SThomas Petazzoni 3873c5aff182SThomas Petazzoni /* Connect to port interrupt line */ 38742636ac3cSMarcin Wojtas if (pp->neta_armada3700) 38752636ac3cSMarcin Wojtas ret = request_irq(pp->dev->irq, mvneta_isr, 0, 38762636ac3cSMarcin Wojtas dev->name, pp); 38772636ac3cSMarcin Wojtas else 38782636ac3cSMarcin Wojtas ret = request_percpu_irq(pp->dev->irq, mvneta_percpu_isr, 38792636ac3cSMarcin Wojtas dev->name, pp->ports); 3880c5aff182SThomas Petazzoni if (ret) { 3881c5aff182SThomas Petazzoni netdev_err(pp->dev, "cannot request irq %d\n", pp->dev->irq); 3882c5aff182SThomas Petazzoni goto err_cleanup_txqs; 3883c5aff182SThomas Petazzoni } 3884c5aff182SThomas Petazzoni 38852636ac3cSMarcin Wojtas if (!pp->neta_armada3700) { 38862dcf75e2SGregory CLEMENT /* Enable per-CPU interrupt on all the CPU to handle our RX 38872dcf75e2SGregory CLEMENT * queue interrupts 38882dcf75e2SGregory CLEMENT */ 38896b125d63SGregory CLEMENT on_each_cpu(mvneta_percpu_enable, pp, true); 38902dcf75e2SGregory CLEMENT 3891120cfa50SGregory CLEMENT pp->is_stopped = false; 3892f8642885SMaxime Ripard /* Register a CPU notifier to handle the case where our CPU 3893f8642885SMaxime Ripard * might be taken offline. 3894f8642885SMaxime Ripard */ 389584a3f4dbSSebastian Andrzej Siewior ret = cpuhp_state_add_instance_nocalls(online_hpstate, 389684a3f4dbSSebastian Andrzej Siewior &pp->node_online); 389784a3f4dbSSebastian Andrzej Siewior if (ret) 389884a3f4dbSSebastian Andrzej Siewior goto err_free_irq; 389984a3f4dbSSebastian Andrzej Siewior 390084a3f4dbSSebastian Andrzej Siewior ret = cpuhp_state_add_instance_nocalls(CPUHP_NET_MVNETA_DEAD, 390184a3f4dbSSebastian Andrzej Siewior &pp->node_dead); 390284a3f4dbSSebastian Andrzej Siewior if (ret) 390384a3f4dbSSebastian Andrzej Siewior goto err_free_online_hp; 39042636ac3cSMarcin Wojtas } 3905f8642885SMaxime Ripard 3906c5aff182SThomas Petazzoni ret = mvneta_mdio_probe(pp); 3907c5aff182SThomas Petazzoni if (ret < 0) { 3908c5aff182SThomas Petazzoni netdev_err(dev, "cannot probe MDIO bus\n"); 390984a3f4dbSSebastian Andrzej Siewior goto err_free_dead_hp; 3910c5aff182SThomas Petazzoni } 3911c5aff182SThomas Petazzoni 3912c5aff182SThomas Petazzoni mvneta_start_dev(pp); 3913c5aff182SThomas Petazzoni 3914c5aff182SThomas Petazzoni return 0; 3915c5aff182SThomas Petazzoni 391684a3f4dbSSebastian Andrzej Siewior err_free_dead_hp: 39172636ac3cSMarcin Wojtas if (!pp->neta_armada3700) 391884a3f4dbSSebastian Andrzej Siewior cpuhp_state_remove_instance_nocalls(CPUHP_NET_MVNETA_DEAD, 391984a3f4dbSSebastian Andrzej Siewior &pp->node_dead); 392084a3f4dbSSebastian Andrzej Siewior err_free_online_hp: 39212636ac3cSMarcin Wojtas if (!pp->neta_armada3700) 39222636ac3cSMarcin Wojtas cpuhp_state_remove_instance_nocalls(online_hpstate, 39232636ac3cSMarcin Wojtas &pp->node_online); 3924c5aff182SThomas Petazzoni err_free_irq: 39252636ac3cSMarcin Wojtas if (pp->neta_armada3700) { 39262636ac3cSMarcin Wojtas free_irq(pp->dev->irq, pp); 39272636ac3cSMarcin Wojtas } else { 39283d8c4530SRussell King - ARM Linux on_each_cpu(mvneta_percpu_disable, pp, true); 392912bb03b4SMaxime Ripard free_percpu_irq(pp->dev->irq, pp->ports); 39302636ac3cSMarcin Wojtas } 3931c5aff182SThomas Petazzoni err_cleanup_txqs: 3932c5aff182SThomas Petazzoni mvneta_cleanup_txqs(pp); 3933c5aff182SThomas Petazzoni err_cleanup_rxqs: 3934c5aff182SThomas Petazzoni mvneta_cleanup_rxqs(pp); 3935c5aff182SThomas Petazzoni return ret; 3936c5aff182SThomas Petazzoni } 3937c5aff182SThomas Petazzoni 3938c5aff182SThomas Petazzoni /* Stop the port, free port interrupt line */ 3939c5aff182SThomas Petazzoni static int mvneta_stop(struct net_device *dev) 3940c5aff182SThomas Petazzoni { 3941c5aff182SThomas Petazzoni struct mvneta_port *pp = netdev_priv(dev); 3942c5aff182SThomas Petazzoni 39432636ac3cSMarcin Wojtas if (!pp->neta_armada3700) { 3944120cfa50SGregory CLEMENT /* Inform that we are stopping so we don't want to setup the 39451c2722a9SGregory CLEMENT * driver for new CPUs in the notifiers. The code of the 39461c2722a9SGregory CLEMENT * notifier for CPU online is protected by the same spinlock, 39471c2722a9SGregory CLEMENT * so when we get the lock, the notifer work is done. 3948120cfa50SGregory CLEMENT */ 3949120cfa50SGregory CLEMENT spin_lock(&pp->lock); 3950120cfa50SGregory CLEMENT pp->is_stopped = true; 39511c2722a9SGregory CLEMENT spin_unlock(&pp->lock); 39521c2722a9SGregory CLEMENT 3953c5aff182SThomas Petazzoni mvneta_stop_dev(pp); 3954c5aff182SThomas Petazzoni mvneta_mdio_remove(pp); 395584a3f4dbSSebastian Andrzej Siewior 3956d26aac2dSDan Carpenter cpuhp_state_remove_instance_nocalls(online_hpstate, 3957d26aac2dSDan Carpenter &pp->node_online); 395884a3f4dbSSebastian Andrzej Siewior cpuhp_state_remove_instance_nocalls(CPUHP_NET_MVNETA_DEAD, 395984a3f4dbSSebastian Andrzej Siewior &pp->node_dead); 3960129219e4SGregory CLEMENT on_each_cpu(mvneta_percpu_disable, pp, true); 396112bb03b4SMaxime Ripard free_percpu_irq(dev->irq, pp->ports); 39622636ac3cSMarcin Wojtas } else { 39632636ac3cSMarcin Wojtas mvneta_stop_dev(pp); 39642636ac3cSMarcin Wojtas mvneta_mdio_remove(pp); 39652636ac3cSMarcin Wojtas free_irq(dev->irq, pp); 39662636ac3cSMarcin Wojtas } 39672636ac3cSMarcin Wojtas 3968c5aff182SThomas Petazzoni mvneta_cleanup_rxqs(pp); 3969c5aff182SThomas Petazzoni mvneta_cleanup_txqs(pp); 3970c5aff182SThomas Petazzoni 3971c5aff182SThomas Petazzoni return 0; 3972c5aff182SThomas Petazzoni } 3973c5aff182SThomas Petazzoni 397415f59456SThomas Petazzoni static int mvneta_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) 397515f59456SThomas Petazzoni { 3976503f9aa9SRussell King struct mvneta_port *pp = netdev_priv(dev); 397715f59456SThomas Petazzoni 3978503f9aa9SRussell King return phylink_mii_ioctl(pp->phylink, ifr, cmd); 397915f59456SThomas Petazzoni } 398015f59456SThomas Petazzoni 3981c5aff182SThomas Petazzoni /* Ethtool methods */ 3982c5aff182SThomas Petazzoni 3983013ad40dSPhilippe Reynes /* Set link ksettings (phy address, speed) for ethtools */ 39842dc0d2b4SBaoyou Xie static int 39852dc0d2b4SBaoyou Xie mvneta_ethtool_set_link_ksettings(struct net_device *ndev, 3986013ad40dSPhilippe Reynes const struct ethtool_link_ksettings *cmd) 3987c5aff182SThomas Petazzoni { 3988013ad40dSPhilippe Reynes struct mvneta_port *pp = netdev_priv(ndev); 3989c5aff182SThomas Petazzoni 3990503f9aa9SRussell King return phylink_ethtool_ksettings_set(pp->phylink, cmd); 39910c0744fcSStas Sergeev } 39920c0744fcSStas Sergeev 3993503f9aa9SRussell King /* Get link ksettings for ethtools */ 3994503f9aa9SRussell King static int 3995503f9aa9SRussell King mvneta_ethtool_get_link_ksettings(struct net_device *ndev, 3996503f9aa9SRussell King struct ethtool_link_ksettings *cmd) 3997503f9aa9SRussell King { 3998503f9aa9SRussell King struct mvneta_port *pp = netdev_priv(ndev); 39990c0744fcSStas Sergeev 4000503f9aa9SRussell King return phylink_ethtool_ksettings_get(pp->phylink, cmd); 40010c0744fcSStas Sergeev } 40020c0744fcSStas Sergeev 4003503f9aa9SRussell King static int mvneta_ethtool_nway_reset(struct net_device *dev) 4004503f9aa9SRussell King { 4005503f9aa9SRussell King struct mvneta_port *pp = netdev_priv(dev); 4006503f9aa9SRussell King 4007503f9aa9SRussell King return phylink_ethtool_nway_reset(pp->phylink); 4008c5aff182SThomas Petazzoni } 4009c5aff182SThomas Petazzoni 4010c5aff182SThomas Petazzoni /* Set interrupt coalescing for ethtools */ 4011c5aff182SThomas Petazzoni static int mvneta_ethtool_set_coalesce(struct net_device *dev, 4012c5aff182SThomas Petazzoni struct ethtool_coalesce *c) 4013c5aff182SThomas Petazzoni { 4014c5aff182SThomas Petazzoni struct mvneta_port *pp = netdev_priv(dev); 4015c5aff182SThomas Petazzoni int queue; 4016c5aff182SThomas Petazzoni 4017c5aff182SThomas Petazzoni for (queue = 0; queue < rxq_number; queue++) { 4018c5aff182SThomas Petazzoni struct mvneta_rx_queue *rxq = &pp->rxqs[queue]; 4019c5aff182SThomas Petazzoni rxq->time_coal = c->rx_coalesce_usecs; 4020c5aff182SThomas Petazzoni rxq->pkts_coal = c->rx_max_coalesced_frames; 4021c5aff182SThomas Petazzoni mvneta_rx_pkts_coal_set(pp, rxq, rxq->pkts_coal); 4022c5aff182SThomas Petazzoni mvneta_rx_time_coal_set(pp, rxq, rxq->time_coal); 4023c5aff182SThomas Petazzoni } 4024c5aff182SThomas Petazzoni 4025c5aff182SThomas Petazzoni for (queue = 0; queue < txq_number; queue++) { 4026c5aff182SThomas Petazzoni struct mvneta_tx_queue *txq = &pp->txqs[queue]; 4027c5aff182SThomas Petazzoni txq->done_pkts_coal = c->tx_max_coalesced_frames; 4028c5aff182SThomas Petazzoni mvneta_tx_done_pkts_coal_set(pp, txq, txq->done_pkts_coal); 4029c5aff182SThomas Petazzoni } 4030c5aff182SThomas Petazzoni 4031c5aff182SThomas Petazzoni return 0; 4032c5aff182SThomas Petazzoni } 4033c5aff182SThomas Petazzoni 4034c5aff182SThomas Petazzoni /* get coalescing for ethtools */ 4035c5aff182SThomas Petazzoni static int mvneta_ethtool_get_coalesce(struct net_device *dev, 4036c5aff182SThomas Petazzoni struct ethtool_coalesce *c) 4037c5aff182SThomas Petazzoni { 4038c5aff182SThomas Petazzoni struct mvneta_port *pp = netdev_priv(dev); 4039c5aff182SThomas Petazzoni 4040c5aff182SThomas Petazzoni c->rx_coalesce_usecs = pp->rxqs[0].time_coal; 4041c5aff182SThomas Petazzoni c->rx_max_coalesced_frames = pp->rxqs[0].pkts_coal; 4042c5aff182SThomas Petazzoni 4043c5aff182SThomas Petazzoni c->tx_max_coalesced_frames = pp->txqs[0].done_pkts_coal; 4044c5aff182SThomas Petazzoni return 0; 4045c5aff182SThomas Petazzoni } 4046c5aff182SThomas Petazzoni 4047c5aff182SThomas Petazzoni 4048c5aff182SThomas Petazzoni static void mvneta_ethtool_get_drvinfo(struct net_device *dev, 4049c5aff182SThomas Petazzoni struct ethtool_drvinfo *drvinfo) 4050c5aff182SThomas Petazzoni { 4051c5aff182SThomas Petazzoni strlcpy(drvinfo->driver, MVNETA_DRIVER_NAME, 4052c5aff182SThomas Petazzoni sizeof(drvinfo->driver)); 4053c5aff182SThomas Petazzoni strlcpy(drvinfo->version, MVNETA_DRIVER_VERSION, 4054c5aff182SThomas Petazzoni sizeof(drvinfo->version)); 4055c5aff182SThomas Petazzoni strlcpy(drvinfo->bus_info, dev_name(&dev->dev), 4056c5aff182SThomas Petazzoni sizeof(drvinfo->bus_info)); 4057c5aff182SThomas Petazzoni } 4058c5aff182SThomas Petazzoni 4059c5aff182SThomas Petazzoni 4060c5aff182SThomas Petazzoni static void mvneta_ethtool_get_ringparam(struct net_device *netdev, 4061c5aff182SThomas Petazzoni struct ethtool_ringparam *ring) 4062c5aff182SThomas Petazzoni { 4063c5aff182SThomas Petazzoni struct mvneta_port *pp = netdev_priv(netdev); 4064c5aff182SThomas Petazzoni 4065c5aff182SThomas Petazzoni ring->rx_max_pending = MVNETA_MAX_RXD; 4066c5aff182SThomas Petazzoni ring->tx_max_pending = MVNETA_MAX_TXD; 4067c5aff182SThomas Petazzoni ring->rx_pending = pp->rx_ring_size; 4068c5aff182SThomas Petazzoni ring->tx_pending = pp->tx_ring_size; 4069c5aff182SThomas Petazzoni } 4070c5aff182SThomas Petazzoni 4071c5aff182SThomas Petazzoni static int mvneta_ethtool_set_ringparam(struct net_device *dev, 4072c5aff182SThomas Petazzoni struct ethtool_ringparam *ring) 4073c5aff182SThomas Petazzoni { 4074c5aff182SThomas Petazzoni struct mvneta_port *pp = netdev_priv(dev); 4075c5aff182SThomas Petazzoni 4076c5aff182SThomas Petazzoni if ((ring->rx_pending == 0) || (ring->tx_pending == 0)) 4077c5aff182SThomas Petazzoni return -EINVAL; 4078c5aff182SThomas Petazzoni pp->rx_ring_size = ring->rx_pending < MVNETA_MAX_RXD ? 4079c5aff182SThomas Petazzoni ring->rx_pending : MVNETA_MAX_RXD; 40808eef5f97SEzequiel Garcia 40818eef5f97SEzequiel Garcia pp->tx_ring_size = clamp_t(u16, ring->tx_pending, 40828eef5f97SEzequiel Garcia MVNETA_MAX_SKB_DESCS * 2, MVNETA_MAX_TXD); 40838eef5f97SEzequiel Garcia if (pp->tx_ring_size != ring->tx_pending) 40848eef5f97SEzequiel Garcia netdev_warn(dev, "TX queue size set to %u (requested %u)\n", 40858eef5f97SEzequiel Garcia pp->tx_ring_size, ring->tx_pending); 4086c5aff182SThomas Petazzoni 4087c5aff182SThomas Petazzoni if (netif_running(dev)) { 4088c5aff182SThomas Petazzoni mvneta_stop(dev); 4089c5aff182SThomas Petazzoni if (mvneta_open(dev)) { 4090c5aff182SThomas Petazzoni netdev_err(dev, 4091c5aff182SThomas Petazzoni "error on opening device after ring param change\n"); 4092c5aff182SThomas Petazzoni return -ENOMEM; 4093c5aff182SThomas Petazzoni } 4094c5aff182SThomas Petazzoni } 4095c5aff182SThomas Petazzoni 4096c5aff182SThomas Petazzoni return 0; 4097c5aff182SThomas Petazzoni } 4098c5aff182SThomas Petazzoni 40994932a918SRussell King static void mvneta_ethtool_get_pauseparam(struct net_device *dev, 41004932a918SRussell King struct ethtool_pauseparam *pause) 41014932a918SRussell King { 41024932a918SRussell King struct mvneta_port *pp = netdev_priv(dev); 41034932a918SRussell King 41044932a918SRussell King phylink_ethtool_get_pauseparam(pp->phylink, pause); 41054932a918SRussell King } 41064932a918SRussell King 41074932a918SRussell King static int mvneta_ethtool_set_pauseparam(struct net_device *dev, 41084932a918SRussell King struct ethtool_pauseparam *pause) 41094932a918SRussell King { 41104932a918SRussell King struct mvneta_port *pp = netdev_priv(dev); 41114932a918SRussell King 41124932a918SRussell King return phylink_ethtool_set_pauseparam(pp->phylink, pause); 41134932a918SRussell King } 41144932a918SRussell King 41159b0cdefaSRussell King static void mvneta_ethtool_get_strings(struct net_device *netdev, u32 sset, 41169b0cdefaSRussell King u8 *data) 41179b0cdefaSRussell King { 41189b0cdefaSRussell King if (sset == ETH_SS_STATS) { 41199b0cdefaSRussell King int i; 41209b0cdefaSRussell King 41219b0cdefaSRussell King for (i = 0; i < ARRAY_SIZE(mvneta_statistics); i++) 41229b0cdefaSRussell King memcpy(data + i * ETH_GSTRING_LEN, 41239b0cdefaSRussell King mvneta_statistics[i].name, ETH_GSTRING_LEN); 41249b0cdefaSRussell King } 41259b0cdefaSRussell King } 41269b0cdefaSRussell King 41279b0cdefaSRussell King static void mvneta_ethtool_update_stats(struct mvneta_port *pp) 41289b0cdefaSRussell King { 41299b0cdefaSRussell King const struct mvneta_statistic *s; 41309b0cdefaSRussell King void __iomem *base = pp->base; 41316d81f451SRussell King u32 high, low; 41326d81f451SRussell King u64 val; 41339b0cdefaSRussell King int i; 41349b0cdefaSRussell King 41359b0cdefaSRussell King for (i = 0, s = mvneta_statistics; 41369b0cdefaSRussell King s < mvneta_statistics + ARRAY_SIZE(mvneta_statistics); 41379b0cdefaSRussell King s++, i++) { 41386d81f451SRussell King val = 0; 41396d81f451SRussell King 41409b0cdefaSRussell King switch (s->type) { 41419b0cdefaSRussell King case T_REG_32: 41429b0cdefaSRussell King val = readl_relaxed(base + s->offset); 41439b0cdefaSRussell King break; 41449b0cdefaSRussell King case T_REG_64: 41459b0cdefaSRussell King /* Docs say to read low 32-bit then high */ 41469b0cdefaSRussell King low = readl_relaxed(base + s->offset); 41479b0cdefaSRussell King high = readl_relaxed(base + s->offset + 4); 41486d81f451SRussell King val = (u64)high << 32 | low; 41496d81f451SRussell King break; 41506d81f451SRussell King case T_SW: 41516d81f451SRussell King switch (s->offset) { 41526d81f451SRussell King case ETHTOOL_STAT_EEE_WAKEUP: 41536d81f451SRussell King val = phylink_get_eee_err(pp->phylink); 41549b0cdefaSRussell King break; 415517a96da6SGregory CLEMENT case ETHTOOL_STAT_SKB_ALLOC_ERR: 415617a96da6SGregory CLEMENT val = pp->rxqs[0].skb_alloc_err; 415717a96da6SGregory CLEMENT break; 415817a96da6SGregory CLEMENT case ETHTOOL_STAT_REFILL_ERR: 415917a96da6SGregory CLEMENT val = pp->rxqs[0].refill_err; 416017a96da6SGregory CLEMENT break; 41619b0cdefaSRussell King } 41626d81f451SRussell King break; 41636d81f451SRussell King } 41646d81f451SRussell King 41656d81f451SRussell King pp->ethtool_stats[i] += val; 41669b0cdefaSRussell King } 41679b0cdefaSRussell King } 41689b0cdefaSRussell King 41699b0cdefaSRussell King static void mvneta_ethtool_get_stats(struct net_device *dev, 41709b0cdefaSRussell King struct ethtool_stats *stats, u64 *data) 41719b0cdefaSRussell King { 41729b0cdefaSRussell King struct mvneta_port *pp = netdev_priv(dev); 41739b0cdefaSRussell King int i; 41749b0cdefaSRussell King 41759b0cdefaSRussell King mvneta_ethtool_update_stats(pp); 41769b0cdefaSRussell King 41779b0cdefaSRussell King for (i = 0; i < ARRAY_SIZE(mvneta_statistics); i++) 41789b0cdefaSRussell King *data++ = pp->ethtool_stats[i]; 41799b0cdefaSRussell King } 41809b0cdefaSRussell King 41819b0cdefaSRussell King static int mvneta_ethtool_get_sset_count(struct net_device *dev, int sset) 41829b0cdefaSRussell King { 41839b0cdefaSRussell King if (sset == ETH_SS_STATS) 41849b0cdefaSRussell King return ARRAY_SIZE(mvneta_statistics); 41859b0cdefaSRussell King return -EOPNOTSUPP; 41869b0cdefaSRussell King } 41879b0cdefaSRussell King 41889a401deaSGregory CLEMENT static u32 mvneta_ethtool_get_rxfh_indir_size(struct net_device *dev) 41899a401deaSGregory CLEMENT { 41909a401deaSGregory CLEMENT return MVNETA_RSS_LU_TABLE_SIZE; 41919a401deaSGregory CLEMENT } 41929a401deaSGregory CLEMENT 41939a401deaSGregory CLEMENT static int mvneta_ethtool_get_rxnfc(struct net_device *dev, 41949a401deaSGregory CLEMENT struct ethtool_rxnfc *info, 41959a401deaSGregory CLEMENT u32 *rules __always_unused) 41969a401deaSGregory CLEMENT { 41979a401deaSGregory CLEMENT switch (info->cmd) { 41989a401deaSGregory CLEMENT case ETHTOOL_GRXRINGS: 41999a401deaSGregory CLEMENT info->data = rxq_number; 42009a401deaSGregory CLEMENT return 0; 42019a401deaSGregory CLEMENT case ETHTOOL_GRXFH: 42029a401deaSGregory CLEMENT return -EOPNOTSUPP; 42039a401deaSGregory CLEMENT default: 42049a401deaSGregory CLEMENT return -EOPNOTSUPP; 42059a401deaSGregory CLEMENT } 42069a401deaSGregory CLEMENT } 42079a401deaSGregory CLEMENT 42089a401deaSGregory CLEMENT static int mvneta_config_rss(struct mvneta_port *pp) 42099a401deaSGregory CLEMENT { 42109a401deaSGregory CLEMENT int cpu; 42119a401deaSGregory CLEMENT u32 val; 42129a401deaSGregory CLEMENT 42139a401deaSGregory CLEMENT netif_tx_stop_all_queues(pp->dev); 42149a401deaSGregory CLEMENT 42156b125d63SGregory CLEMENT on_each_cpu(mvneta_percpu_mask_interrupt, pp, true); 42169a401deaSGregory CLEMENT 42170f5c6c30SJisheng Zhang if (!pp->neta_armada3700) { 42189a401deaSGregory CLEMENT /* We have to synchronise on the napi of each CPU */ 42199a401deaSGregory CLEMENT for_each_online_cpu(cpu) { 42209a401deaSGregory CLEMENT struct mvneta_pcpu_port *pcpu_port = 42219a401deaSGregory CLEMENT per_cpu_ptr(pp->ports, cpu); 42229a401deaSGregory CLEMENT 42239a401deaSGregory CLEMENT napi_synchronize(&pcpu_port->napi); 42249a401deaSGregory CLEMENT napi_disable(&pcpu_port->napi); 42259a401deaSGregory CLEMENT } 42260f5c6c30SJisheng Zhang } else { 42270f5c6c30SJisheng Zhang napi_synchronize(&pp->napi); 42280f5c6c30SJisheng Zhang napi_disable(&pp->napi); 42290f5c6c30SJisheng Zhang } 42309a401deaSGregory CLEMENT 42319a401deaSGregory CLEMENT pp->rxq_def = pp->indir[0]; 42329a401deaSGregory CLEMENT 42339a401deaSGregory CLEMENT /* Update unicast mapping */ 42349a401deaSGregory CLEMENT mvneta_set_rx_mode(pp->dev); 42359a401deaSGregory CLEMENT 42369a401deaSGregory CLEMENT /* Update val of portCfg register accordingly with all RxQueue types */ 42379a401deaSGregory CLEMENT val = MVNETA_PORT_CONFIG_DEFL_VALUE(pp->rxq_def); 42389a401deaSGregory CLEMENT mvreg_write(pp, MVNETA_PORT_CONFIG, val); 42399a401deaSGregory CLEMENT 42409a401deaSGregory CLEMENT /* Update the elected CPU matching the new rxq_def */ 4241120cfa50SGregory CLEMENT spin_lock(&pp->lock); 42429a401deaSGregory CLEMENT mvneta_percpu_elect(pp); 4243120cfa50SGregory CLEMENT spin_unlock(&pp->lock); 42449a401deaSGregory CLEMENT 42450f5c6c30SJisheng Zhang if (!pp->neta_armada3700) { 42469a401deaSGregory CLEMENT /* We have to synchronise on the napi of each CPU */ 42479a401deaSGregory CLEMENT for_each_online_cpu(cpu) { 42489a401deaSGregory CLEMENT struct mvneta_pcpu_port *pcpu_port = 42499a401deaSGregory CLEMENT per_cpu_ptr(pp->ports, cpu); 42509a401deaSGregory CLEMENT 42519a401deaSGregory CLEMENT napi_enable(&pcpu_port->napi); 42529a401deaSGregory CLEMENT } 42530f5c6c30SJisheng Zhang } else { 42540f5c6c30SJisheng Zhang napi_enable(&pp->napi); 42550f5c6c30SJisheng Zhang } 42569a401deaSGregory CLEMENT 42579a401deaSGregory CLEMENT netif_tx_start_all_queues(pp->dev); 42589a401deaSGregory CLEMENT 42599a401deaSGregory CLEMENT return 0; 42609a401deaSGregory CLEMENT } 42619a401deaSGregory CLEMENT 42629a401deaSGregory CLEMENT static int mvneta_ethtool_set_rxfh(struct net_device *dev, const u32 *indir, 42639a401deaSGregory CLEMENT const u8 *key, const u8 hfunc) 42649a401deaSGregory CLEMENT { 42659a401deaSGregory CLEMENT struct mvneta_port *pp = netdev_priv(dev); 42662636ac3cSMarcin Wojtas 42672636ac3cSMarcin Wojtas /* Current code for Armada 3700 doesn't support RSS features yet */ 42682636ac3cSMarcin Wojtas if (pp->neta_armada3700) 42692636ac3cSMarcin Wojtas return -EOPNOTSUPP; 42702636ac3cSMarcin Wojtas 42719a401deaSGregory CLEMENT /* We require at least one supported parameter to be changed 42729a401deaSGregory CLEMENT * and no change in any of the unsupported parameters 42739a401deaSGregory CLEMENT */ 42749a401deaSGregory CLEMENT if (key || 42759a401deaSGregory CLEMENT (hfunc != ETH_RSS_HASH_NO_CHANGE && hfunc != ETH_RSS_HASH_TOP)) 42769a401deaSGregory CLEMENT return -EOPNOTSUPP; 42779a401deaSGregory CLEMENT 42789a401deaSGregory CLEMENT if (!indir) 42799a401deaSGregory CLEMENT return 0; 42809a401deaSGregory CLEMENT 42819a401deaSGregory CLEMENT memcpy(pp->indir, indir, MVNETA_RSS_LU_TABLE_SIZE); 42829a401deaSGregory CLEMENT 42839a401deaSGregory CLEMENT return mvneta_config_rss(pp); 42849a401deaSGregory CLEMENT } 42859a401deaSGregory CLEMENT 42869a401deaSGregory CLEMENT static int mvneta_ethtool_get_rxfh(struct net_device *dev, u32 *indir, u8 *key, 42879a401deaSGregory CLEMENT u8 *hfunc) 42889a401deaSGregory CLEMENT { 42899a401deaSGregory CLEMENT struct mvneta_port *pp = netdev_priv(dev); 42909a401deaSGregory CLEMENT 42912636ac3cSMarcin Wojtas /* Current code for Armada 3700 doesn't support RSS features yet */ 42922636ac3cSMarcin Wojtas if (pp->neta_armada3700) 42932636ac3cSMarcin Wojtas return -EOPNOTSUPP; 42942636ac3cSMarcin Wojtas 42959a401deaSGregory CLEMENT if (hfunc) 42969a401deaSGregory CLEMENT *hfunc = ETH_RSS_HASH_TOP; 42979a401deaSGregory CLEMENT 42989a401deaSGregory CLEMENT if (!indir) 42999a401deaSGregory CLEMENT return 0; 43009a401deaSGregory CLEMENT 43019a401deaSGregory CLEMENT memcpy(indir, pp->indir, MVNETA_RSS_LU_TABLE_SIZE); 43029a401deaSGregory CLEMENT 43039a401deaSGregory CLEMENT return 0; 43049a401deaSGregory CLEMENT } 43059a401deaSGregory CLEMENT 4306b60a00f9SJingju Hou static void mvneta_ethtool_get_wol(struct net_device *dev, 4307b60a00f9SJingju Hou struct ethtool_wolinfo *wol) 4308b60a00f9SJingju Hou { 4309503f9aa9SRussell King struct mvneta_port *pp = netdev_priv(dev); 4310b60a00f9SJingju Hou 4311503f9aa9SRussell King phylink_ethtool_get_wol(pp->phylink, wol); 4312b60a00f9SJingju Hou } 4313b60a00f9SJingju Hou 4314b60a00f9SJingju Hou static int mvneta_ethtool_set_wol(struct net_device *dev, 4315b60a00f9SJingju Hou struct ethtool_wolinfo *wol) 4316b60a00f9SJingju Hou { 4317503f9aa9SRussell King struct mvneta_port *pp = netdev_priv(dev); 431882960fffSJisheng Zhang int ret; 431982960fffSJisheng Zhang 4320503f9aa9SRussell King ret = phylink_ethtool_set_wol(pp->phylink, wol); 432182960fffSJisheng Zhang if (!ret) 432282960fffSJisheng Zhang device_set_wakeup_enable(&dev->dev, !!wol->wolopts); 432382960fffSJisheng Zhang 432482960fffSJisheng Zhang return ret; 4325b60a00f9SJingju Hou } 4326b60a00f9SJingju Hou 43276d81f451SRussell King static int mvneta_ethtool_get_eee(struct net_device *dev, 43286d81f451SRussell King struct ethtool_eee *eee) 43296d81f451SRussell King { 43306d81f451SRussell King struct mvneta_port *pp = netdev_priv(dev); 43316d81f451SRussell King u32 lpi_ctl0; 43326d81f451SRussell King 43336d81f451SRussell King lpi_ctl0 = mvreg_read(pp, MVNETA_LPI_CTRL_0); 43346d81f451SRussell King 43356d81f451SRussell King eee->eee_enabled = pp->eee_enabled; 43366d81f451SRussell King eee->eee_active = pp->eee_active; 43376d81f451SRussell King eee->tx_lpi_enabled = pp->tx_lpi_enabled; 43386d81f451SRussell King eee->tx_lpi_timer = (lpi_ctl0) >> 8; // * scale; 43396d81f451SRussell King 43406d81f451SRussell King return phylink_ethtool_get_eee(pp->phylink, eee); 43416d81f451SRussell King } 43426d81f451SRussell King 43436d81f451SRussell King static int mvneta_ethtool_set_eee(struct net_device *dev, 43446d81f451SRussell King struct ethtool_eee *eee) 43456d81f451SRussell King { 43466d81f451SRussell King struct mvneta_port *pp = netdev_priv(dev); 43476d81f451SRussell King u32 lpi_ctl0; 43486d81f451SRussell King 43496d81f451SRussell King /* The Armada 37x documents do not give limits for this other than 43506d81f451SRussell King * it being an 8-bit register. */ 4351e4a3e9ffSYueHaibing if (eee->tx_lpi_enabled && eee->tx_lpi_timer > 255) 43526d81f451SRussell King return -EINVAL; 43536d81f451SRussell King 43546d81f451SRussell King lpi_ctl0 = mvreg_read(pp, MVNETA_LPI_CTRL_0); 43556d81f451SRussell King lpi_ctl0 &= ~(0xff << 8); 43566d81f451SRussell King lpi_ctl0 |= eee->tx_lpi_timer << 8; 43576d81f451SRussell King mvreg_write(pp, MVNETA_LPI_CTRL_0, lpi_ctl0); 43586d81f451SRussell King 43596d81f451SRussell King pp->eee_enabled = eee->eee_enabled; 43606d81f451SRussell King pp->tx_lpi_enabled = eee->tx_lpi_enabled; 43616d81f451SRussell King 43626d81f451SRussell King mvneta_set_eee(pp, eee->tx_lpi_enabled && eee->eee_enabled); 43636d81f451SRussell King 43646d81f451SRussell King return phylink_ethtool_set_eee(pp->phylink, eee); 43656d81f451SRussell King } 43666d81f451SRussell King 4367c5aff182SThomas Petazzoni static const struct net_device_ops mvneta_netdev_ops = { 4368c5aff182SThomas Petazzoni .ndo_open = mvneta_open, 4369c5aff182SThomas Petazzoni .ndo_stop = mvneta_stop, 4370c5aff182SThomas Petazzoni .ndo_start_xmit = mvneta_tx, 4371c5aff182SThomas Petazzoni .ndo_set_rx_mode = mvneta_set_rx_mode, 4372c5aff182SThomas Petazzoni .ndo_set_mac_address = mvneta_set_mac_addr, 4373c5aff182SThomas Petazzoni .ndo_change_mtu = mvneta_change_mtu, 4374b65657fcSSimon Guinot .ndo_fix_features = mvneta_fix_features, 4375c5aff182SThomas Petazzoni .ndo_get_stats64 = mvneta_get_stats64, 437615f59456SThomas Petazzoni .ndo_do_ioctl = mvneta_ioctl, 4377c5aff182SThomas Petazzoni }; 4378c5aff182SThomas Petazzoni 43794581be42SJisheng Zhang static const struct ethtool_ops mvneta_eth_tool_ops = { 4380503f9aa9SRussell King .nway_reset = mvneta_ethtool_nway_reset, 4381c5aff182SThomas Petazzoni .get_link = ethtool_op_get_link, 4382c5aff182SThomas Petazzoni .set_coalesce = mvneta_ethtool_set_coalesce, 4383c5aff182SThomas Petazzoni .get_coalesce = mvneta_ethtool_get_coalesce, 4384c5aff182SThomas Petazzoni .get_drvinfo = mvneta_ethtool_get_drvinfo, 4385c5aff182SThomas Petazzoni .get_ringparam = mvneta_ethtool_get_ringparam, 4386c5aff182SThomas Petazzoni .set_ringparam = mvneta_ethtool_set_ringparam, 43874932a918SRussell King .get_pauseparam = mvneta_ethtool_get_pauseparam, 43884932a918SRussell King .set_pauseparam = mvneta_ethtool_set_pauseparam, 43899b0cdefaSRussell King .get_strings = mvneta_ethtool_get_strings, 43909b0cdefaSRussell King .get_ethtool_stats = mvneta_ethtool_get_stats, 43919b0cdefaSRussell King .get_sset_count = mvneta_ethtool_get_sset_count, 43929a401deaSGregory CLEMENT .get_rxfh_indir_size = mvneta_ethtool_get_rxfh_indir_size, 43939a401deaSGregory CLEMENT .get_rxnfc = mvneta_ethtool_get_rxnfc, 43949a401deaSGregory CLEMENT .get_rxfh = mvneta_ethtool_get_rxfh, 43959a401deaSGregory CLEMENT .set_rxfh = mvneta_ethtool_set_rxfh, 4396503f9aa9SRussell King .get_link_ksettings = mvneta_ethtool_get_link_ksettings, 4397013ad40dSPhilippe Reynes .set_link_ksettings = mvneta_ethtool_set_link_ksettings, 4398b60a00f9SJingju Hou .get_wol = mvneta_ethtool_get_wol, 4399b60a00f9SJingju Hou .set_wol = mvneta_ethtool_set_wol, 44006d81f451SRussell King .get_eee = mvneta_ethtool_get_eee, 44016d81f451SRussell King .set_eee = mvneta_ethtool_set_eee, 4402c5aff182SThomas Petazzoni }; 4403c5aff182SThomas Petazzoni 4404c5aff182SThomas Petazzoni /* Initialize hw */ 44059672850bSEzequiel Garcia static int mvneta_init(struct device *dev, struct mvneta_port *pp) 4406c5aff182SThomas Petazzoni { 4407c5aff182SThomas Petazzoni int queue; 4408c5aff182SThomas Petazzoni 4409c5aff182SThomas Petazzoni /* Disable port */ 4410c5aff182SThomas Petazzoni mvneta_port_disable(pp); 4411c5aff182SThomas Petazzoni 4412c5aff182SThomas Petazzoni /* Set port default values */ 4413c5aff182SThomas Petazzoni mvneta_defaults_set(pp); 4414c5aff182SThomas Petazzoni 44155d6312edSMarkus Elfring pp->txqs = devm_kcalloc(dev, txq_number, sizeof(*pp->txqs), GFP_KERNEL); 4416c5aff182SThomas Petazzoni if (!pp->txqs) 4417c5aff182SThomas Petazzoni return -ENOMEM; 4418c5aff182SThomas Petazzoni 4419c5aff182SThomas Petazzoni /* Initialize TX descriptor rings */ 4420c5aff182SThomas Petazzoni for (queue = 0; queue < txq_number; queue++) { 4421c5aff182SThomas Petazzoni struct mvneta_tx_queue *txq = &pp->txqs[queue]; 4422c5aff182SThomas Petazzoni txq->id = queue; 4423c5aff182SThomas Petazzoni txq->size = pp->tx_ring_size; 4424c5aff182SThomas Petazzoni txq->done_pkts_coal = MVNETA_TXDONE_COAL_PKTS; 4425c5aff182SThomas Petazzoni } 4426c5aff182SThomas Petazzoni 44275d6312edSMarkus Elfring pp->rxqs = devm_kcalloc(dev, rxq_number, sizeof(*pp->rxqs), GFP_KERNEL); 44289672850bSEzequiel Garcia if (!pp->rxqs) 4429c5aff182SThomas Petazzoni return -ENOMEM; 4430c5aff182SThomas Petazzoni 4431c5aff182SThomas Petazzoni /* Create Rx descriptor rings */ 4432c5aff182SThomas Petazzoni for (queue = 0; queue < rxq_number; queue++) { 4433c5aff182SThomas Petazzoni struct mvneta_rx_queue *rxq = &pp->rxqs[queue]; 4434c5aff182SThomas Petazzoni rxq->id = queue; 4435c5aff182SThomas Petazzoni rxq->size = pp->rx_ring_size; 4436c5aff182SThomas Petazzoni rxq->pkts_coal = MVNETA_RX_COAL_PKTS; 4437c5aff182SThomas Petazzoni rxq->time_coal = MVNETA_RX_COAL_USEC; 443829110630SMarkus Elfring rxq->buf_virt_addr 443929110630SMarkus Elfring = devm_kmalloc_array(pp->dev->dev.parent, 444029110630SMarkus Elfring rxq->size, 444129110630SMarkus Elfring sizeof(*rxq->buf_virt_addr), 4442f88bee1cSGregory CLEMENT GFP_KERNEL); 4443f88bee1cSGregory CLEMENT if (!rxq->buf_virt_addr) 4444f88bee1cSGregory CLEMENT return -ENOMEM; 4445c5aff182SThomas Petazzoni } 4446c5aff182SThomas Petazzoni 4447c5aff182SThomas Petazzoni return 0; 4448c5aff182SThomas Petazzoni } 4449c5aff182SThomas Petazzoni 4450c5aff182SThomas Petazzoni /* platform glue : initialize decoding windows */ 445103ce758eSGreg KH static void mvneta_conf_mbus_windows(struct mvneta_port *pp, 4452c5aff182SThomas Petazzoni const struct mbus_dram_target_info *dram) 4453c5aff182SThomas Petazzoni { 4454c5aff182SThomas Petazzoni u32 win_enable; 4455c5aff182SThomas Petazzoni u32 win_protect; 4456c5aff182SThomas Petazzoni int i; 4457c5aff182SThomas Petazzoni 4458c5aff182SThomas Petazzoni for (i = 0; i < 6; i++) { 4459c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_WIN_BASE(i), 0); 4460c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_WIN_SIZE(i), 0); 4461c5aff182SThomas Petazzoni 4462c5aff182SThomas Petazzoni if (i < 4) 4463c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_WIN_REMAP(i), 0); 4464c5aff182SThomas Petazzoni } 4465c5aff182SThomas Petazzoni 4466c5aff182SThomas Petazzoni win_enable = 0x3f; 4467c5aff182SThomas Petazzoni win_protect = 0; 4468c5aff182SThomas Petazzoni 44692636ac3cSMarcin Wojtas if (dram) { 4470c5aff182SThomas Petazzoni for (i = 0; i < dram->num_cs; i++) { 4471c5aff182SThomas Petazzoni const struct mbus_dram_window *cs = dram->cs + i; 44722636ac3cSMarcin Wojtas 44732636ac3cSMarcin Wojtas mvreg_write(pp, MVNETA_WIN_BASE(i), 44742636ac3cSMarcin Wojtas (cs->base & 0xffff0000) | 44752636ac3cSMarcin Wojtas (cs->mbus_attr << 8) | 44762636ac3cSMarcin Wojtas dram->mbus_dram_target_id); 4477c5aff182SThomas Petazzoni 4478c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_WIN_SIZE(i), 4479c5aff182SThomas Petazzoni (cs->size - 1) & 0xffff0000); 4480c5aff182SThomas Petazzoni 4481c5aff182SThomas Petazzoni win_enable &= ~(1 << i); 4482c5aff182SThomas Petazzoni win_protect |= 3 << (2 * i); 4483c5aff182SThomas Petazzoni } 44842636ac3cSMarcin Wojtas } else { 44852636ac3cSMarcin Wojtas /* For Armada3700 open default 4GB Mbus window, leaving 44862636ac3cSMarcin Wojtas * arbitration of target/attribute to a different layer 44872636ac3cSMarcin Wojtas * of configuration. 44882636ac3cSMarcin Wojtas */ 44892636ac3cSMarcin Wojtas mvreg_write(pp, MVNETA_WIN_SIZE(0), 0xffff0000); 44902636ac3cSMarcin Wojtas win_enable &= ~BIT(0); 44912636ac3cSMarcin Wojtas win_protect = 3; 44922636ac3cSMarcin Wojtas } 4493c5aff182SThomas Petazzoni 4494c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_BASE_ADDR_ENABLE, win_enable); 4495db6ba9a5SMarcin Wojtas mvreg_write(pp, MVNETA_ACCESS_PROTECT_ENABLE, win_protect); 4496c5aff182SThomas Petazzoni } 4497c5aff182SThomas Petazzoni 4498c5aff182SThomas Petazzoni /* Power up the port */ 44993f1dd4bcSThomas Petazzoni static int mvneta_port_power_up(struct mvneta_port *pp, int phy_mode) 4500c5aff182SThomas Petazzoni { 4501c5aff182SThomas Petazzoni /* MAC Cause register should be cleared */ 4502c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_UNIT_INTR_CAUSE, 0); 4503c5aff182SThomas Petazzoni 450432699954SRussell King if (phy_mode == PHY_INTERFACE_MODE_QSGMII) 45053f1dd4bcSThomas Petazzoni mvreg_write(pp, MVNETA_SERDES_CFG, MVNETA_QSGMII_SERDES_PROTO); 450622f4bf8aSRussell King else if (phy_mode == PHY_INTERFACE_MODE_SGMII || 4507a10c1c81SRussell King phy_interface_mode_is_8023z(phy_mode)) 45083f1dd4bcSThomas Petazzoni mvreg_write(pp, MVNETA_SERDES_CFG, MVNETA_SGMII_SERDES_PROTO); 450932699954SRussell King else if (!phy_interface_mode_is_rgmii(phy_mode)) 45103f1dd4bcSThomas Petazzoni return -EINVAL; 45113f1dd4bcSThomas Petazzoni 45123f1dd4bcSThomas Petazzoni return 0; 4513c5aff182SThomas Petazzoni } 4514c5aff182SThomas Petazzoni 4515c5aff182SThomas Petazzoni /* Device initialization routine */ 451603ce758eSGreg KH static int mvneta_probe(struct platform_device *pdev) 4517c5aff182SThomas Petazzoni { 4518c5aff182SThomas Petazzoni struct device_node *dn = pdev->dev.of_node; 4519dc35a10fSMarcin Wojtas struct device_node *bm_node; 4520c5aff182SThomas Petazzoni struct mvneta_port *pp; 4521c5aff182SThomas Petazzoni struct net_device *dev; 4522503f9aa9SRussell King struct phylink *phylink; 4523a10c1c81SRussell King struct phy *comphy; 45248cc3e439SThomas Petazzoni const char *dt_mac_addr; 45258cc3e439SThomas Petazzoni char hw_mac_addr[ETH_ALEN]; 45268cc3e439SThomas Petazzoni const char *mac_from; 45279110ee07SMarcin Wojtas int tx_csum_limit; 4528c5aff182SThomas Petazzoni int phy_mode; 4529c5aff182SThomas Petazzoni int err; 453012bb03b4SMaxime Ripard int cpu; 4531c5aff182SThomas Petazzoni 4532a3ddd94fSRosen Penev dev = devm_alloc_etherdev_mqs(&pdev->dev, sizeof(struct mvneta_port), 4533a3ddd94fSRosen Penev txq_number, rxq_number); 4534c5aff182SThomas Petazzoni if (!dev) 4535c5aff182SThomas Petazzoni return -ENOMEM; 4536c5aff182SThomas Petazzoni 4537c5aff182SThomas Petazzoni dev->irq = irq_of_parse_and_map(dn, 0); 4538a3ddd94fSRosen Penev if (dev->irq == 0) 4539a3ddd94fSRosen Penev return -EINVAL; 4540c5aff182SThomas Petazzoni 4541c5aff182SThomas Petazzoni phy_mode = of_get_phy_mode(dn); 4542c5aff182SThomas Petazzoni if (phy_mode < 0) { 4543c5aff182SThomas Petazzoni dev_err(&pdev->dev, "incorrect phy-mode\n"); 4544c5aff182SThomas Petazzoni err = -EINVAL; 4545503f9aa9SRussell King goto err_free_irq; 4546503f9aa9SRussell King } 4547503f9aa9SRussell King 4548a10c1c81SRussell King comphy = devm_of_phy_get(&pdev->dev, dn, NULL); 4549a10c1c81SRussell King if (comphy == ERR_PTR(-EPROBE_DEFER)) { 4550a10c1c81SRussell King err = -EPROBE_DEFER; 4551a10c1c81SRussell King goto err_free_irq; 4552a10c1c81SRussell King } else if (IS_ERR(comphy)) { 4553a10c1c81SRussell King comphy = NULL; 4554a10c1c81SRussell King } 4555a10c1c81SRussell King 455644cc27e4SIoana Ciornei pp = netdev_priv(dev); 455744cc27e4SIoana Ciornei spin_lock_init(&pp->lock); 455844cc27e4SIoana Ciornei 455944cc27e4SIoana Ciornei pp->phylink_config.dev = &dev->dev; 456044cc27e4SIoana Ciornei pp->phylink_config.type = PHYLINK_NETDEV; 456144cc27e4SIoana Ciornei 456244cc27e4SIoana Ciornei phylink = phylink_create(&pp->phylink_config, pdev->dev.fwnode, 456344cc27e4SIoana Ciornei phy_mode, &mvneta_phylink_ops); 4564503f9aa9SRussell King if (IS_ERR(phylink)) { 4565503f9aa9SRussell King err = PTR_ERR(phylink); 4566503f9aa9SRussell King goto err_free_irq; 4567c5aff182SThomas Petazzoni } 4568c5aff182SThomas Petazzoni 4569c5aff182SThomas Petazzoni dev->tx_queue_len = MVNETA_MAX_TXD; 4570c5aff182SThomas Petazzoni dev->watchdog_timeo = 5 * HZ; 4571c5aff182SThomas Petazzoni dev->netdev_ops = &mvneta_netdev_ops; 4572c5aff182SThomas Petazzoni 45737ad24ea4SWilfried Klaebe dev->ethtool_ops = &mvneta_eth_tool_ops; 4574c5aff182SThomas Petazzoni 4575503f9aa9SRussell King pp->phylink = phylink; 4576a10c1c81SRussell King pp->comphy = comphy; 4577c5aff182SThomas Petazzoni pp->phy_interface = phy_mode; 4578503f9aa9SRussell King pp->dn = dn; 4579c5aff182SThomas Petazzoni 458090b74c01SGregory CLEMENT pp->rxq_def = rxq_def; 45819a401deaSGregory CLEMENT pp->indir[0] = rxq_def; 45829a401deaSGregory CLEMENT 45832636ac3cSMarcin Wojtas /* Get special SoC configurations */ 45842636ac3cSMarcin Wojtas if (of_device_is_compatible(dn, "marvell,armada-3700-neta")) 45852636ac3cSMarcin Wojtas pp->neta_armada3700 = true; 45862636ac3cSMarcin Wojtas 45872804ba4eSJisheng Zhang pp->clk = devm_clk_get(&pdev->dev, "core"); 45882804ba4eSJisheng Zhang if (IS_ERR(pp->clk)) 4589189dd626SThomas Petazzoni pp->clk = devm_clk_get(&pdev->dev, NULL); 4590189dd626SThomas Petazzoni if (IS_ERR(pp->clk)) { 4591189dd626SThomas Petazzoni err = PTR_ERR(pp->clk); 4592503f9aa9SRussell King goto err_free_phylink; 4593189dd626SThomas Petazzoni } 4594189dd626SThomas Petazzoni 4595189dd626SThomas Petazzoni clk_prepare_enable(pp->clk); 4596189dd626SThomas Petazzoni 459715cc4a4aSJisheng Zhang pp->clk_bus = devm_clk_get(&pdev->dev, "bus"); 459815cc4a4aSJisheng Zhang if (!IS_ERR(pp->clk_bus)) 459915cc4a4aSJisheng Zhang clk_prepare_enable(pp->clk_bus); 460015cc4a4aSJisheng Zhang 460100c33afbSJisheng Zhang pp->base = devm_platform_ioremap_resource(pdev, 0); 4602c3f0dd38SThomas Petazzoni if (IS_ERR(pp->base)) { 4603c3f0dd38SThomas Petazzoni err = PTR_ERR(pp->base); 46045445eaf3SArnaud Patard \(Rtp\) goto err_clk; 46055445eaf3SArnaud Patard \(Rtp\) } 46065445eaf3SArnaud Patard \(Rtp\) 460712bb03b4SMaxime Ripard /* Alloc per-cpu port structure */ 460812bb03b4SMaxime Ripard pp->ports = alloc_percpu(struct mvneta_pcpu_port); 460912bb03b4SMaxime Ripard if (!pp->ports) { 461012bb03b4SMaxime Ripard err = -ENOMEM; 461112bb03b4SMaxime Ripard goto err_clk; 461212bb03b4SMaxime Ripard } 461312bb03b4SMaxime Ripard 461474c41b04Swilly tarreau /* Alloc per-cpu stats */ 46151c213bd2SWANG Cong pp->stats = netdev_alloc_pcpu_stats(struct mvneta_pcpu_stats); 461674c41b04Swilly tarreau if (!pp->stats) { 461774c41b04Swilly tarreau err = -ENOMEM; 461812bb03b4SMaxime Ripard goto err_free_ports; 461974c41b04Swilly tarreau } 462074c41b04Swilly tarreau 46218cc3e439SThomas Petazzoni dt_mac_addr = of_get_mac_address(dn); 4622a51645f7SPetr Štetiar if (!IS_ERR(dt_mac_addr)) { 46238cc3e439SThomas Petazzoni mac_from = "device tree"; 46242d2924afSPetr Štetiar ether_addr_copy(dev->dev_addr, dt_mac_addr); 46258cc3e439SThomas Petazzoni } else { 46268cc3e439SThomas Petazzoni mvneta_get_mac_addr(pp, hw_mac_addr); 46278cc3e439SThomas Petazzoni if (is_valid_ether_addr(hw_mac_addr)) { 46288cc3e439SThomas Petazzoni mac_from = "hardware"; 46298cc3e439SThomas Petazzoni memcpy(dev->dev_addr, hw_mac_addr, ETH_ALEN); 46308cc3e439SThomas Petazzoni } else { 46318cc3e439SThomas Petazzoni mac_from = "random"; 46328cc3e439SThomas Petazzoni eth_hw_addr_random(dev); 46338cc3e439SThomas Petazzoni } 46348cc3e439SThomas Petazzoni } 46358cc3e439SThomas Petazzoni 46369110ee07SMarcin Wojtas if (!of_property_read_u32(dn, "tx-csum-limit", &tx_csum_limit)) { 46379110ee07SMarcin Wojtas if (tx_csum_limit < 0 || 46389110ee07SMarcin Wojtas tx_csum_limit > MVNETA_TX_CSUM_MAX_SIZE) { 46399110ee07SMarcin Wojtas tx_csum_limit = MVNETA_TX_CSUM_DEF_SIZE; 46409110ee07SMarcin Wojtas dev_info(&pdev->dev, 46419110ee07SMarcin Wojtas "Wrong TX csum limit in DT, set to %dB\n", 46429110ee07SMarcin Wojtas MVNETA_TX_CSUM_DEF_SIZE); 46439110ee07SMarcin Wojtas } 46449110ee07SMarcin Wojtas } else if (of_device_is_compatible(dn, "marvell,armada-370-neta")) { 46459110ee07SMarcin Wojtas tx_csum_limit = MVNETA_TX_CSUM_DEF_SIZE; 46469110ee07SMarcin Wojtas } else { 46479110ee07SMarcin Wojtas tx_csum_limit = MVNETA_TX_CSUM_MAX_SIZE; 46489110ee07SMarcin Wojtas } 46499110ee07SMarcin Wojtas 46509110ee07SMarcin Wojtas pp->tx_csum_limit = tx_csum_limit; 4651b65657fcSSimon Guinot 46529768b45cSJane Li pp->dram_target_info = mv_mbus_dram_info(); 46532636ac3cSMarcin Wojtas /* Armada3700 requires setting default configuration of Mbus 46542636ac3cSMarcin Wojtas * windows, however without using filled mbus_dram_target_info 46552636ac3cSMarcin Wojtas * structure. 46562636ac3cSMarcin Wojtas */ 46579768b45cSJane Li if (pp->dram_target_info || pp->neta_armada3700) 46589768b45cSJane Li mvneta_conf_mbus_windows(pp, pp->dram_target_info); 4659dc35a10fSMarcin Wojtas 4660c5aff182SThomas Petazzoni pp->tx_ring_size = MVNETA_MAX_TXD; 4661c5aff182SThomas Petazzoni pp->rx_ring_size = MVNETA_MAX_RXD; 4662c5aff182SThomas Petazzoni 4663c5aff182SThomas Petazzoni pp->dev = dev; 4664c5aff182SThomas Petazzoni SET_NETDEV_DEV(dev, &pdev->dev); 4665c5aff182SThomas Petazzoni 4666dc35a10fSMarcin Wojtas pp->id = global_port_id++; 4667562e2f46SYelena Krivosheev pp->rx_offset_correction = 0; /* not relevant for SW BM */ 4668dc35a10fSMarcin Wojtas 4669dc35a10fSMarcin Wojtas /* Obtain access to BM resources if enabled and already initialized */ 4670dc35a10fSMarcin Wojtas bm_node = of_parse_phandle(dn, "buffer-manager", 0); 4671965cbbecSGregory CLEMENT if (bm_node) { 4672965cbbecSGregory CLEMENT pp->bm_priv = mvneta_bm_get(bm_node); 4673965cbbecSGregory CLEMENT if (pp->bm_priv) { 4674dc35a10fSMarcin Wojtas err = mvneta_bm_port_init(pdev, pp); 4675dc35a10fSMarcin Wojtas if (err < 0) { 4676965cbbecSGregory CLEMENT dev_info(&pdev->dev, 4677965cbbecSGregory CLEMENT "use SW buffer management\n"); 4678965cbbecSGregory CLEMENT mvneta_bm_put(pp->bm_priv); 4679dc35a10fSMarcin Wojtas pp->bm_priv = NULL; 4680dc35a10fSMarcin Wojtas } 4681dc35a10fSMarcin Wojtas } 4682562e2f46SYelena Krivosheev /* Set RX packet offset correction for platforms, whose 4683562e2f46SYelena Krivosheev * NET_SKB_PAD, exceeds 64B. It should be 64B for 64-bit 4684562e2f46SYelena Krivosheev * platforms and 0B for 32-bit ones. 4685562e2f46SYelena Krivosheev */ 4686562e2f46SYelena Krivosheev pp->rx_offset_correction = max(0, 4687562e2f46SYelena Krivosheev NET_SKB_PAD - 4688562e2f46SYelena Krivosheev MVNETA_RX_PKT_OFFSET_CORRECTION); 4689965cbbecSGregory CLEMENT } 4690d4e4da00SPeter Chen of_node_put(bm_node); 4691dc35a10fSMarcin Wojtas 46929672850bSEzequiel Garcia err = mvneta_init(&pdev->dev, pp); 46939672850bSEzequiel Garcia if (err < 0) 4694dc35a10fSMarcin Wojtas goto err_netdev; 46953f1dd4bcSThomas Petazzoni 46963f1dd4bcSThomas Petazzoni err = mvneta_port_power_up(pp, phy_mode); 46973f1dd4bcSThomas Petazzoni if (err < 0) { 46983f1dd4bcSThomas Petazzoni dev_err(&pdev->dev, "can't power up port\n"); 4699dc35a10fSMarcin Wojtas goto err_netdev; 47003f1dd4bcSThomas Petazzoni } 4701c5aff182SThomas Petazzoni 47022636ac3cSMarcin Wojtas /* Armada3700 network controller does not support per-cpu 47032636ac3cSMarcin Wojtas * operation, so only single NAPI should be initialized. 47042636ac3cSMarcin Wojtas */ 47052636ac3cSMarcin Wojtas if (pp->neta_armada3700) { 47062636ac3cSMarcin Wojtas netif_napi_add(dev, &pp->napi, mvneta_poll, NAPI_POLL_WEIGHT); 47072636ac3cSMarcin Wojtas } else { 470812bb03b4SMaxime Ripard for_each_present_cpu(cpu) { 47092636ac3cSMarcin Wojtas struct mvneta_pcpu_port *port = 47102636ac3cSMarcin Wojtas per_cpu_ptr(pp->ports, cpu); 471112bb03b4SMaxime Ripard 47122636ac3cSMarcin Wojtas netif_napi_add(dev, &port->napi, mvneta_poll, 47132636ac3cSMarcin Wojtas NAPI_POLL_WEIGHT); 471412bb03b4SMaxime Ripard port->pp = pp; 471512bb03b4SMaxime Ripard } 47162636ac3cSMarcin Wojtas } 4717c5aff182SThomas Petazzoni 47187772988aSJisheng Zhang dev->features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | 47197772988aSJisheng Zhang NETIF_F_TSO | NETIF_F_RXCSUM; 472001ef26caSEzequiel Garcia dev->hw_features |= dev->features; 472101ef26caSEzequiel Garcia dev->vlan_features |= dev->features; 472297db8afaSAndrew Lunn dev->priv_flags |= IFF_LIVE_ADDR_CHANGE; 47238eef5f97SEzequiel Garcia dev->gso_max_segs = MVNETA_MAX_TSO_SEGS; 4724b50b72deSwilly tarreau 47255777987eSJarod Wilson /* MTU range: 68 - 9676 */ 47265777987eSJarod Wilson dev->min_mtu = ETH_MIN_MTU; 47275777987eSJarod Wilson /* 9676 == 9700 - 20 and rounding to 8 */ 47285777987eSJarod Wilson dev->max_mtu = 9676; 47295777987eSJarod Wilson 4730c5aff182SThomas Petazzoni err = register_netdev(dev); 4731c5aff182SThomas Petazzoni if (err < 0) { 4732c5aff182SThomas Petazzoni dev_err(&pdev->dev, "failed to register\n"); 4733d484e06eSJisheng Zhang goto err_netdev; 4734c5aff182SThomas Petazzoni } 4735c5aff182SThomas Petazzoni 47368cc3e439SThomas Petazzoni netdev_info(dev, "Using %s mac address %pM\n", mac_from, 47378cc3e439SThomas Petazzoni dev->dev_addr); 4738c5aff182SThomas Petazzoni 4739c5aff182SThomas Petazzoni platform_set_drvdata(pdev, pp->dev); 4740c5aff182SThomas Petazzoni 4741c5aff182SThomas Petazzoni return 0; 4742c5aff182SThomas Petazzoni 4743dc35a10fSMarcin Wojtas err_netdev: 4744dc35a10fSMarcin Wojtas if (pp->bm_priv) { 4745dc35a10fSMarcin Wojtas mvneta_bm_pool_destroy(pp->bm_priv, pp->pool_long, 1 << pp->id); 4746dc35a10fSMarcin Wojtas mvneta_bm_pool_destroy(pp->bm_priv, pp->pool_short, 4747dc35a10fSMarcin Wojtas 1 << pp->id); 4748965cbbecSGregory CLEMENT mvneta_bm_put(pp->bm_priv); 4749dc35a10fSMarcin Wojtas } 475074c41b04Swilly tarreau free_percpu(pp->stats); 475112bb03b4SMaxime Ripard err_free_ports: 475212bb03b4SMaxime Ripard free_percpu(pp->ports); 47535445eaf3SArnaud Patard \(Rtp\) err_clk: 475415cc4a4aSJisheng Zhang clk_disable_unprepare(pp->clk_bus); 47555445eaf3SArnaud Patard \(Rtp\) clk_disable_unprepare(pp->clk); 4756503f9aa9SRussell King err_free_phylink: 4757503f9aa9SRussell King if (pp->phylink) 4758503f9aa9SRussell King phylink_destroy(pp->phylink); 4759c5aff182SThomas Petazzoni err_free_irq: 4760c5aff182SThomas Petazzoni irq_dispose_mapping(dev->irq); 4761c5aff182SThomas Petazzoni return err; 4762c5aff182SThomas Petazzoni } 4763c5aff182SThomas Petazzoni 4764c5aff182SThomas Petazzoni /* Device removal routine */ 476503ce758eSGreg KH static int mvneta_remove(struct platform_device *pdev) 4766c5aff182SThomas Petazzoni { 4767c5aff182SThomas Petazzoni struct net_device *dev = platform_get_drvdata(pdev); 4768c5aff182SThomas Petazzoni struct mvneta_port *pp = netdev_priv(dev); 4769c5aff182SThomas Petazzoni 4770c5aff182SThomas Petazzoni unregister_netdev(dev); 477115cc4a4aSJisheng Zhang clk_disable_unprepare(pp->clk_bus); 4772189dd626SThomas Petazzoni clk_disable_unprepare(pp->clk); 477312bb03b4SMaxime Ripard free_percpu(pp->ports); 477474c41b04Swilly tarreau free_percpu(pp->stats); 4775c5aff182SThomas Petazzoni irq_dispose_mapping(dev->irq); 4776503f9aa9SRussell King phylink_destroy(pp->phylink); 4777c5aff182SThomas Petazzoni 4778dc35a10fSMarcin Wojtas if (pp->bm_priv) { 4779dc35a10fSMarcin Wojtas mvneta_bm_pool_destroy(pp->bm_priv, pp->pool_long, 1 << pp->id); 4780dc35a10fSMarcin Wojtas mvneta_bm_pool_destroy(pp->bm_priv, pp->pool_short, 4781dc35a10fSMarcin Wojtas 1 << pp->id); 4782965cbbecSGregory CLEMENT mvneta_bm_put(pp->bm_priv); 4783dc35a10fSMarcin Wojtas } 4784dc35a10fSMarcin Wojtas 4785c5aff182SThomas Petazzoni return 0; 4786c5aff182SThomas Petazzoni } 4787c5aff182SThomas Petazzoni 47889768b45cSJane Li #ifdef CONFIG_PM_SLEEP 47899768b45cSJane Li static int mvneta_suspend(struct device *device) 47909768b45cSJane Li { 47911799cdd2SJisheng Zhang int queue; 47929768b45cSJane Li struct net_device *dev = dev_get_drvdata(device); 47939768b45cSJane Li struct mvneta_port *pp = netdev_priv(dev); 47949768b45cSJane Li 47951799cdd2SJisheng Zhang if (!netif_running(dev)) 47961799cdd2SJisheng Zhang goto clean_exit; 47971799cdd2SJisheng Zhang 47981799cdd2SJisheng Zhang if (!pp->neta_armada3700) { 47991799cdd2SJisheng Zhang spin_lock(&pp->lock); 48001799cdd2SJisheng Zhang pp->is_stopped = true; 48011799cdd2SJisheng Zhang spin_unlock(&pp->lock); 48021799cdd2SJisheng Zhang 48031799cdd2SJisheng Zhang cpuhp_state_remove_instance_nocalls(online_hpstate, 48041799cdd2SJisheng Zhang &pp->node_online); 48051799cdd2SJisheng Zhang cpuhp_state_remove_instance_nocalls(CPUHP_NET_MVNETA_DEAD, 48061799cdd2SJisheng Zhang &pp->node_dead); 48071799cdd2SJisheng Zhang } 48081799cdd2SJisheng Zhang 48093b8bc674SRussell King rtnl_lock(); 48101799cdd2SJisheng Zhang mvneta_stop_dev(pp); 48113b8bc674SRussell King rtnl_unlock(); 48121799cdd2SJisheng Zhang 48131799cdd2SJisheng Zhang for (queue = 0; queue < rxq_number; queue++) { 48141799cdd2SJisheng Zhang struct mvneta_rx_queue *rxq = &pp->rxqs[queue]; 48151799cdd2SJisheng Zhang 48161799cdd2SJisheng Zhang mvneta_rxq_drop_pkts(pp, rxq); 48171799cdd2SJisheng Zhang } 48181799cdd2SJisheng Zhang 48191799cdd2SJisheng Zhang for (queue = 0; queue < txq_number; queue++) { 48201799cdd2SJisheng Zhang struct mvneta_tx_queue *txq = &pp->txqs[queue]; 48211799cdd2SJisheng Zhang 48221799cdd2SJisheng Zhang mvneta_txq_hw_deinit(pp, txq); 48231799cdd2SJisheng Zhang } 48241799cdd2SJisheng Zhang 48251799cdd2SJisheng Zhang clean_exit: 48269768b45cSJane Li netif_device_detach(dev); 48279768b45cSJane Li clk_disable_unprepare(pp->clk_bus); 48289768b45cSJane Li clk_disable_unprepare(pp->clk); 48291799cdd2SJisheng Zhang 48309768b45cSJane Li return 0; 48319768b45cSJane Li } 48329768b45cSJane Li 48339768b45cSJane Li static int mvneta_resume(struct device *device) 48349768b45cSJane Li { 48359768b45cSJane Li struct platform_device *pdev = to_platform_device(device); 48369768b45cSJane Li struct net_device *dev = dev_get_drvdata(device); 48379768b45cSJane Li struct mvneta_port *pp = netdev_priv(dev); 48381799cdd2SJisheng Zhang int err, queue; 48399768b45cSJane Li 48409768b45cSJane Li clk_prepare_enable(pp->clk); 48419768b45cSJane Li if (!IS_ERR(pp->clk_bus)) 48429768b45cSJane Li clk_prepare_enable(pp->clk_bus); 48439768b45cSJane Li if (pp->dram_target_info || pp->neta_armada3700) 48449768b45cSJane Li mvneta_conf_mbus_windows(pp, pp->dram_target_info); 48459768b45cSJane Li if (pp->bm_priv) { 48469768b45cSJane Li err = mvneta_bm_port_init(pdev, pp); 48479768b45cSJane Li if (err < 0) { 48489768b45cSJane Li dev_info(&pdev->dev, "use SW buffer management\n"); 48499768b45cSJane Li pp->bm_priv = NULL; 48509768b45cSJane Li } 48519768b45cSJane Li } 48529768b45cSJane Li mvneta_defaults_set(pp); 48539768b45cSJane Li err = mvneta_port_power_up(pp, pp->phy_interface); 48549768b45cSJane Li if (err < 0) { 48559768b45cSJane Li dev_err(device, "can't power up port\n"); 48569768b45cSJane Li return err; 48579768b45cSJane Li } 48589768b45cSJane Li 48599768b45cSJane Li netif_device_attach(dev); 48601799cdd2SJisheng Zhang 48611799cdd2SJisheng Zhang if (!netif_running(dev)) 48621799cdd2SJisheng Zhang return 0; 48631799cdd2SJisheng Zhang 48641799cdd2SJisheng Zhang for (queue = 0; queue < rxq_number; queue++) { 48651799cdd2SJisheng Zhang struct mvneta_rx_queue *rxq = &pp->rxqs[queue]; 48661799cdd2SJisheng Zhang 48671799cdd2SJisheng Zhang rxq->next_desc_to_proc = 0; 48681799cdd2SJisheng Zhang mvneta_rxq_hw_init(pp, rxq); 4869d6956ac8SJisheng Zhang } 48701799cdd2SJisheng Zhang 48711799cdd2SJisheng Zhang for (queue = 0; queue < txq_number; queue++) { 48721799cdd2SJisheng Zhang struct mvneta_tx_queue *txq = &pp->txqs[queue]; 48731799cdd2SJisheng Zhang 48741799cdd2SJisheng Zhang txq->next_desc_to_proc = 0; 48751799cdd2SJisheng Zhang mvneta_txq_hw_init(pp, txq); 48761799cdd2SJisheng Zhang } 48771799cdd2SJisheng Zhang 48781799cdd2SJisheng Zhang if (!pp->neta_armada3700) { 48791799cdd2SJisheng Zhang spin_lock(&pp->lock); 48801799cdd2SJisheng Zhang pp->is_stopped = false; 48811799cdd2SJisheng Zhang spin_unlock(&pp->lock); 48821799cdd2SJisheng Zhang cpuhp_state_add_instance_nocalls(online_hpstate, 48831799cdd2SJisheng Zhang &pp->node_online); 48841799cdd2SJisheng Zhang cpuhp_state_add_instance_nocalls(CPUHP_NET_MVNETA_DEAD, 48851799cdd2SJisheng Zhang &pp->node_dead); 48861799cdd2SJisheng Zhang } 48871799cdd2SJisheng Zhang 48881799cdd2SJisheng Zhang rtnl_lock(); 48891799cdd2SJisheng Zhang mvneta_start_dev(pp); 48903b8bc674SRussell King rtnl_unlock(); 48911799cdd2SJisheng Zhang mvneta_set_rx_mode(dev); 4892d6956ac8SJisheng Zhang 48939768b45cSJane Li return 0; 48949768b45cSJane Li } 48959768b45cSJane Li #endif 48969768b45cSJane Li 48979768b45cSJane Li static SIMPLE_DEV_PM_OPS(mvneta_pm_ops, mvneta_suspend, mvneta_resume); 48989768b45cSJane Li 4899c5aff182SThomas Petazzoni static const struct of_device_id mvneta_match[] = { 4900c5aff182SThomas Petazzoni { .compatible = "marvell,armada-370-neta" }, 4901f522a975SSimon Guinot { .compatible = "marvell,armada-xp-neta" }, 49022636ac3cSMarcin Wojtas { .compatible = "marvell,armada-3700-neta" }, 4903c5aff182SThomas Petazzoni { } 4904c5aff182SThomas Petazzoni }; 4905c5aff182SThomas Petazzoni MODULE_DEVICE_TABLE(of, mvneta_match); 4906c5aff182SThomas Petazzoni 4907c5aff182SThomas Petazzoni static struct platform_driver mvneta_driver = { 4908c5aff182SThomas Petazzoni .probe = mvneta_probe, 490903ce758eSGreg KH .remove = mvneta_remove, 4910c5aff182SThomas Petazzoni .driver = { 4911c5aff182SThomas Petazzoni .name = MVNETA_DRIVER_NAME, 4912c5aff182SThomas Petazzoni .of_match_table = mvneta_match, 49139768b45cSJane Li .pm = &mvneta_pm_ops, 4914c5aff182SThomas Petazzoni }, 4915c5aff182SThomas Petazzoni }; 4916c5aff182SThomas Petazzoni 491784a3f4dbSSebastian Andrzej Siewior static int __init mvneta_driver_init(void) 491884a3f4dbSSebastian Andrzej Siewior { 491984a3f4dbSSebastian Andrzej Siewior int ret; 492084a3f4dbSSebastian Andrzej Siewior 492184a3f4dbSSebastian Andrzej Siewior ret = cpuhp_setup_state_multi(CPUHP_AP_ONLINE_DYN, "net/mvmeta:online", 492284a3f4dbSSebastian Andrzej Siewior mvneta_cpu_online, 492384a3f4dbSSebastian Andrzej Siewior mvneta_cpu_down_prepare); 492484a3f4dbSSebastian Andrzej Siewior if (ret < 0) 492584a3f4dbSSebastian Andrzej Siewior goto out; 492684a3f4dbSSebastian Andrzej Siewior online_hpstate = ret; 492784a3f4dbSSebastian Andrzej Siewior ret = cpuhp_setup_state_multi(CPUHP_NET_MVNETA_DEAD, "net/mvneta:dead", 492884a3f4dbSSebastian Andrzej Siewior NULL, mvneta_cpu_dead); 492984a3f4dbSSebastian Andrzej Siewior if (ret) 493084a3f4dbSSebastian Andrzej Siewior goto err_dead; 493184a3f4dbSSebastian Andrzej Siewior 493284a3f4dbSSebastian Andrzej Siewior ret = platform_driver_register(&mvneta_driver); 493384a3f4dbSSebastian Andrzej Siewior if (ret) 493484a3f4dbSSebastian Andrzej Siewior goto err; 493584a3f4dbSSebastian Andrzej Siewior return 0; 493684a3f4dbSSebastian Andrzej Siewior 493784a3f4dbSSebastian Andrzej Siewior err: 493884a3f4dbSSebastian Andrzej Siewior cpuhp_remove_multi_state(CPUHP_NET_MVNETA_DEAD); 493984a3f4dbSSebastian Andrzej Siewior err_dead: 494084a3f4dbSSebastian Andrzej Siewior cpuhp_remove_multi_state(online_hpstate); 494184a3f4dbSSebastian Andrzej Siewior out: 494284a3f4dbSSebastian Andrzej Siewior return ret; 494384a3f4dbSSebastian Andrzej Siewior } 494484a3f4dbSSebastian Andrzej Siewior module_init(mvneta_driver_init); 494584a3f4dbSSebastian Andrzej Siewior 494684a3f4dbSSebastian Andrzej Siewior static void __exit mvneta_driver_exit(void) 494784a3f4dbSSebastian Andrzej Siewior { 494884a3f4dbSSebastian Andrzej Siewior platform_driver_unregister(&mvneta_driver); 494984a3f4dbSSebastian Andrzej Siewior cpuhp_remove_multi_state(CPUHP_NET_MVNETA_DEAD); 495084a3f4dbSSebastian Andrzej Siewior cpuhp_remove_multi_state(online_hpstate); 495184a3f4dbSSebastian Andrzej Siewior } 495284a3f4dbSSebastian Andrzej Siewior module_exit(mvneta_driver_exit); 4953c5aff182SThomas Petazzoni 4954c5aff182SThomas Petazzoni MODULE_DESCRIPTION("Marvell NETA Ethernet Driver - www.marvell.com"); 4955c5aff182SThomas Petazzoni MODULE_AUTHOR("Rami Rosen <rosenr@marvell.com>, Thomas Petazzoni <thomas.petazzoni@free-electrons.com>"); 4956c5aff182SThomas Petazzoni MODULE_LICENSE("GPL"); 4957c5aff182SThomas Petazzoni 4958d3757ba4SJoe Perches module_param(rxq_number, int, 0444); 4959d3757ba4SJoe Perches module_param(txq_number, int, 0444); 4960c5aff182SThomas Petazzoni 4961d3757ba4SJoe Perches module_param(rxq_def, int, 0444); 4962d3757ba4SJoe Perches module_param(rx_copybreak, int, 0644); 4963