1c5aff182SThomas Petazzoni /* 2c5aff182SThomas Petazzoni * Driver for Marvell NETA network card for Armada XP and Armada 370 SoCs. 3c5aff182SThomas Petazzoni * 4c5aff182SThomas Petazzoni * Copyright (C) 2012 Marvell 5c5aff182SThomas Petazzoni * 6c5aff182SThomas Petazzoni * Rami Rosen <rosenr@marvell.com> 7c5aff182SThomas Petazzoni * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> 8c5aff182SThomas Petazzoni * 9c5aff182SThomas Petazzoni * This file is licensed under the terms of the GNU General Public 10c5aff182SThomas Petazzoni * License version 2. This program is licensed "as is" without any 11c5aff182SThomas Petazzoni * warranty of any kind, whether express or implied. 12c5aff182SThomas Petazzoni */ 13c5aff182SThomas Petazzoni 140e03f563SJisheng Zhang #include <linux/clk.h> 150e03f563SJisheng Zhang #include <linux/cpu.h> 16c5aff182SThomas Petazzoni #include <linux/etherdevice.h> 170e03f563SJisheng Zhang #include <linux/if_vlan.h> 18c5aff182SThomas Petazzoni #include <linux/inetdevice.h> 190e03f563SJisheng Zhang #include <linux/interrupt.h> 200e03f563SJisheng Zhang #include <linux/io.h> 210e03f563SJisheng Zhang #include <linux/kernel.h> 22c5aff182SThomas Petazzoni #include <linux/mbus.h> 23c5aff182SThomas Petazzoni #include <linux/module.h> 240e03f563SJisheng Zhang #include <linux/netdevice.h> 25c5aff182SThomas Petazzoni #include <linux/of.h> 260e03f563SJisheng Zhang #include <linux/of_address.h> 27c5aff182SThomas Petazzoni #include <linux/of_irq.h> 28c5aff182SThomas Petazzoni #include <linux/of_mdio.h> 29c5aff182SThomas Petazzoni #include <linux/of_net.h> 30a10c1c81SRussell King #include <linux/phy/phy.h> 31c5aff182SThomas Petazzoni #include <linux/phy.h> 32503f9aa9SRussell King #include <linux/phylink.h> 330e03f563SJisheng Zhang #include <linux/platform_device.h> 340e03f563SJisheng Zhang #include <linux/skbuff.h> 35baa11ebcSGregory CLEMENT #include <net/hwbm.h> 36dc35a10fSMarcin Wojtas #include "mvneta_bm.h" 370e03f563SJisheng Zhang #include <net/ip.h> 380e03f563SJisheng Zhang #include <net/ipv6.h> 390e03f563SJisheng Zhang #include <net/tso.h> 40568a3fa2SLorenzo Bianconi #include <net/page_pool.h> 410db51da7SLorenzo Bianconi #include <linux/bpf_trace.h> 42c5aff182SThomas Petazzoni 43c5aff182SThomas Petazzoni /* Registers */ 44c5aff182SThomas Petazzoni #define MVNETA_RXQ_CONFIG_REG(q) (0x1400 + ((q) << 2)) 45e5bdf689SMarcin Wojtas #define MVNETA_RXQ_HW_BUF_ALLOC BIT(0) 46dc35a10fSMarcin Wojtas #define MVNETA_RXQ_SHORT_POOL_ID_SHIFT 4 47dc35a10fSMarcin Wojtas #define MVNETA_RXQ_SHORT_POOL_ID_MASK 0x30 48dc35a10fSMarcin Wojtas #define MVNETA_RXQ_LONG_POOL_ID_SHIFT 6 49dc35a10fSMarcin Wojtas #define MVNETA_RXQ_LONG_POOL_ID_MASK 0xc0 50c5aff182SThomas Petazzoni #define MVNETA_RXQ_PKT_OFFSET_ALL_MASK (0xf << 8) 51c5aff182SThomas Petazzoni #define MVNETA_RXQ_PKT_OFFSET_MASK(offs) ((offs) << 8) 52c5aff182SThomas Petazzoni #define MVNETA_RXQ_THRESHOLD_REG(q) (0x14c0 + ((q) << 2)) 53c5aff182SThomas Petazzoni #define MVNETA_RXQ_NON_OCCUPIED(v) ((v) << 16) 54c5aff182SThomas Petazzoni #define MVNETA_RXQ_BASE_ADDR_REG(q) (0x1480 + ((q) << 2)) 55c5aff182SThomas Petazzoni #define MVNETA_RXQ_SIZE_REG(q) (0x14a0 + ((q) << 2)) 56c5aff182SThomas Petazzoni #define MVNETA_RXQ_BUF_SIZE_SHIFT 19 57c5aff182SThomas Petazzoni #define MVNETA_RXQ_BUF_SIZE_MASK (0x1fff << 19) 58c5aff182SThomas Petazzoni #define MVNETA_RXQ_STATUS_REG(q) (0x14e0 + ((q) << 2)) 59c5aff182SThomas Petazzoni #define MVNETA_RXQ_OCCUPIED_ALL_MASK 0x3fff 60c5aff182SThomas Petazzoni #define MVNETA_RXQ_STATUS_UPDATE_REG(q) (0x1500 + ((q) << 2)) 61c5aff182SThomas Petazzoni #define MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT 16 62c5aff182SThomas Petazzoni #define MVNETA_RXQ_ADD_NON_OCCUPIED_MAX 255 63dc35a10fSMarcin Wojtas #define MVNETA_PORT_POOL_BUFFER_SZ_REG(pool) (0x1700 + ((pool) << 2)) 64dc35a10fSMarcin Wojtas #define MVNETA_PORT_POOL_BUFFER_SZ_SHIFT 3 65dc35a10fSMarcin Wojtas #define MVNETA_PORT_POOL_BUFFER_SZ_MASK 0xfff8 66c5aff182SThomas Petazzoni #define MVNETA_PORT_RX_RESET 0x1cc0 67c5aff182SThomas Petazzoni #define MVNETA_PORT_RX_DMA_RESET BIT(0) 68c5aff182SThomas Petazzoni #define MVNETA_PHY_ADDR 0x2000 69c5aff182SThomas Petazzoni #define MVNETA_PHY_ADDR_MASK 0x1f 70c5aff182SThomas Petazzoni #define MVNETA_MBUS_RETRY 0x2010 71c5aff182SThomas Petazzoni #define MVNETA_UNIT_INTR_CAUSE 0x2080 72c5aff182SThomas Petazzoni #define MVNETA_UNIT_CONTROL 0x20B0 73c5aff182SThomas Petazzoni #define MVNETA_PHY_POLLING_ENABLE BIT(1) 74c5aff182SThomas Petazzoni #define MVNETA_WIN_BASE(w) (0x2200 + ((w) << 3)) 75c5aff182SThomas Petazzoni #define MVNETA_WIN_SIZE(w) (0x2204 + ((w) << 3)) 76c5aff182SThomas Petazzoni #define MVNETA_WIN_REMAP(w) (0x2280 + ((w) << 2)) 77c5aff182SThomas Petazzoni #define MVNETA_BASE_ADDR_ENABLE 0x2290 78db6ba9a5SMarcin Wojtas #define MVNETA_ACCESS_PROTECT_ENABLE 0x2294 79c5aff182SThomas Petazzoni #define MVNETA_PORT_CONFIG 0x2400 80c5aff182SThomas Petazzoni #define MVNETA_UNI_PROMISC_MODE BIT(0) 81c5aff182SThomas Petazzoni #define MVNETA_DEF_RXQ(q) ((q) << 1) 82c5aff182SThomas Petazzoni #define MVNETA_DEF_RXQ_ARP(q) ((q) << 4) 83c5aff182SThomas Petazzoni #define MVNETA_TX_UNSET_ERR_SUM BIT(12) 84c5aff182SThomas Petazzoni #define MVNETA_DEF_RXQ_TCP(q) ((q) << 16) 85c5aff182SThomas Petazzoni #define MVNETA_DEF_RXQ_UDP(q) ((q) << 19) 86c5aff182SThomas Petazzoni #define MVNETA_DEF_RXQ_BPDU(q) ((q) << 22) 87c5aff182SThomas Petazzoni #define MVNETA_RX_CSUM_WITH_PSEUDO_HDR BIT(25) 88c5aff182SThomas Petazzoni #define MVNETA_PORT_CONFIG_DEFL_VALUE(q) (MVNETA_DEF_RXQ(q) | \ 89c5aff182SThomas Petazzoni MVNETA_DEF_RXQ_ARP(q) | \ 90c5aff182SThomas Petazzoni MVNETA_DEF_RXQ_TCP(q) | \ 91c5aff182SThomas Petazzoni MVNETA_DEF_RXQ_UDP(q) | \ 92c5aff182SThomas Petazzoni MVNETA_DEF_RXQ_BPDU(q) | \ 93c5aff182SThomas Petazzoni MVNETA_TX_UNSET_ERR_SUM | \ 94c5aff182SThomas Petazzoni MVNETA_RX_CSUM_WITH_PSEUDO_HDR) 95c5aff182SThomas Petazzoni #define MVNETA_PORT_CONFIG_EXTEND 0x2404 96c5aff182SThomas Petazzoni #define MVNETA_MAC_ADDR_LOW 0x2414 97c5aff182SThomas Petazzoni #define MVNETA_MAC_ADDR_HIGH 0x2418 98c5aff182SThomas Petazzoni #define MVNETA_SDMA_CONFIG 0x241c 99c5aff182SThomas Petazzoni #define MVNETA_SDMA_BRST_SIZE_16 4 100c5aff182SThomas Petazzoni #define MVNETA_RX_BRST_SZ_MASK(burst) ((burst) << 1) 101c5aff182SThomas Petazzoni #define MVNETA_RX_NO_DATA_SWAP BIT(4) 102c5aff182SThomas Petazzoni #define MVNETA_TX_NO_DATA_SWAP BIT(5) 1039ad8fef6SThomas Petazzoni #define MVNETA_DESC_SWAP BIT(6) 104c5aff182SThomas Petazzoni #define MVNETA_TX_BRST_SZ_MASK(burst) ((burst) << 22) 105c5aff182SThomas Petazzoni #define MVNETA_PORT_STATUS 0x2444 106c5aff182SThomas Petazzoni #define MVNETA_TX_IN_PRGRS BIT(1) 107c5aff182SThomas Petazzoni #define MVNETA_TX_FIFO_EMPTY BIT(8) 108c5aff182SThomas Petazzoni #define MVNETA_RX_MIN_FRAME_SIZE 0x247c 1093f1dd4bcSThomas Petazzoni #define MVNETA_SERDES_CFG 0x24A0 1105445eaf3SArnaud Patard \(Rtp\) #define MVNETA_SGMII_SERDES_PROTO 0x0cc7 1113f1dd4bcSThomas Petazzoni #define MVNETA_QSGMII_SERDES_PROTO 0x0667 112c5aff182SThomas Petazzoni #define MVNETA_TYPE_PRIO 0x24bc 113c5aff182SThomas Petazzoni #define MVNETA_FORCE_UNI BIT(21) 114c5aff182SThomas Petazzoni #define MVNETA_TXQ_CMD_1 0x24e4 115c5aff182SThomas Petazzoni #define MVNETA_TXQ_CMD 0x2448 116c5aff182SThomas Petazzoni #define MVNETA_TXQ_DISABLE_SHIFT 8 117c5aff182SThomas Petazzoni #define MVNETA_TXQ_ENABLE_MASK 0x000000ff 118e483911fSAndrew Lunn #define MVNETA_RX_DISCARD_FRAME_COUNT 0x2484 119e483911fSAndrew Lunn #define MVNETA_OVERRUN_FRAME_COUNT 0x2488 120898b2970SStas Sergeev #define MVNETA_GMAC_CLOCK_DIVIDER 0x24f4 121898b2970SStas Sergeev #define MVNETA_GMAC_1MS_CLOCK_ENABLE BIT(31) 122c5aff182SThomas Petazzoni #define MVNETA_ACC_MODE 0x2500 123dc35a10fSMarcin Wojtas #define MVNETA_BM_ADDRESS 0x2504 124c5aff182SThomas Petazzoni #define MVNETA_CPU_MAP(cpu) (0x2540 + ((cpu) << 2)) 125c5aff182SThomas Petazzoni #define MVNETA_CPU_RXQ_ACCESS_ALL_MASK 0x000000ff 126c5aff182SThomas Petazzoni #define MVNETA_CPU_TXQ_ACCESS_ALL_MASK 0x0000ff00 1272dcf75e2SGregory CLEMENT #define MVNETA_CPU_RXQ_ACCESS(rxq) BIT(rxq) 12850bf8cb6SGregory CLEMENT #define MVNETA_CPU_TXQ_ACCESS(txq) BIT(txq + 8) 129c5aff182SThomas Petazzoni #define MVNETA_RXQ_TIME_COAL_REG(q) (0x2580 + ((q) << 2)) 13040ba35e7Swilly tarreau 1312dcf75e2SGregory CLEMENT /* Exception Interrupt Port/Queue Cause register 1322dcf75e2SGregory CLEMENT * 1332dcf75e2SGregory CLEMENT * Their behavior depend of the mapping done using the PCPX2Q 1342dcf75e2SGregory CLEMENT * registers. For a given CPU if the bit associated to a queue is not 1352dcf75e2SGregory CLEMENT * set, then for the register a read from this CPU will always return 1362dcf75e2SGregory CLEMENT * 0 and a write won't do anything 1372dcf75e2SGregory CLEMENT */ 13840ba35e7Swilly tarreau 139c5aff182SThomas Petazzoni #define MVNETA_INTR_NEW_CAUSE 0x25a0 140c5aff182SThomas Petazzoni #define MVNETA_INTR_NEW_MASK 0x25a4 14140ba35e7Swilly tarreau 14240ba35e7Swilly tarreau /* bits 0..7 = TXQ SENT, one bit per queue. 14340ba35e7Swilly tarreau * bits 8..15 = RXQ OCCUP, one bit per queue. 14440ba35e7Swilly tarreau * bits 16..23 = RXQ FREE, one bit per queue. 14540ba35e7Swilly tarreau * bit 29 = OLD_REG_SUM, see old reg ? 14640ba35e7Swilly tarreau * bit 30 = TX_ERR_SUM, one bit for 4 ports 14740ba35e7Swilly tarreau * bit 31 = MISC_SUM, one bit for 4 ports 14840ba35e7Swilly tarreau */ 14940ba35e7Swilly tarreau #define MVNETA_TX_INTR_MASK(nr_txqs) (((1 << nr_txqs) - 1) << 0) 15040ba35e7Swilly tarreau #define MVNETA_TX_INTR_MASK_ALL (0xff << 0) 15140ba35e7Swilly tarreau #define MVNETA_RX_INTR_MASK(nr_rxqs) (((1 << nr_rxqs) - 1) << 8) 15240ba35e7Swilly tarreau #define MVNETA_RX_INTR_MASK_ALL (0xff << 8) 153898b2970SStas Sergeev #define MVNETA_MISCINTR_INTR_MASK BIT(31) 15440ba35e7Swilly tarreau 155c5aff182SThomas Petazzoni #define MVNETA_INTR_OLD_CAUSE 0x25a8 156c5aff182SThomas Petazzoni #define MVNETA_INTR_OLD_MASK 0x25ac 15740ba35e7Swilly tarreau 15840ba35e7Swilly tarreau /* Data Path Port/Queue Cause Register */ 159c5aff182SThomas Petazzoni #define MVNETA_INTR_MISC_CAUSE 0x25b0 160c5aff182SThomas Petazzoni #define MVNETA_INTR_MISC_MASK 0x25b4 16140ba35e7Swilly tarreau 16240ba35e7Swilly tarreau #define MVNETA_CAUSE_PHY_STATUS_CHANGE BIT(0) 16340ba35e7Swilly tarreau #define MVNETA_CAUSE_LINK_CHANGE BIT(1) 16440ba35e7Swilly tarreau #define MVNETA_CAUSE_PTP BIT(4) 16540ba35e7Swilly tarreau 16640ba35e7Swilly tarreau #define MVNETA_CAUSE_INTERNAL_ADDR_ERR BIT(7) 16740ba35e7Swilly tarreau #define MVNETA_CAUSE_RX_OVERRUN BIT(8) 16840ba35e7Swilly tarreau #define MVNETA_CAUSE_RX_CRC_ERROR BIT(9) 16940ba35e7Swilly tarreau #define MVNETA_CAUSE_RX_LARGE_PKT BIT(10) 17040ba35e7Swilly tarreau #define MVNETA_CAUSE_TX_UNDERUN BIT(11) 17140ba35e7Swilly tarreau #define MVNETA_CAUSE_PRBS_ERR BIT(12) 17240ba35e7Swilly tarreau #define MVNETA_CAUSE_PSC_SYNC_CHANGE BIT(13) 17340ba35e7Swilly tarreau #define MVNETA_CAUSE_SERDES_SYNC_ERR BIT(14) 17440ba35e7Swilly tarreau 17540ba35e7Swilly tarreau #define MVNETA_CAUSE_BMU_ALLOC_ERR_SHIFT 16 17640ba35e7Swilly tarreau #define MVNETA_CAUSE_BMU_ALLOC_ERR_ALL_MASK (0xF << MVNETA_CAUSE_BMU_ALLOC_ERR_SHIFT) 17740ba35e7Swilly tarreau #define MVNETA_CAUSE_BMU_ALLOC_ERR_MASK(pool) (1 << (MVNETA_CAUSE_BMU_ALLOC_ERR_SHIFT + (pool))) 17840ba35e7Swilly tarreau 17940ba35e7Swilly tarreau #define MVNETA_CAUSE_TXQ_ERROR_SHIFT 24 18040ba35e7Swilly tarreau #define MVNETA_CAUSE_TXQ_ERROR_ALL_MASK (0xFF << MVNETA_CAUSE_TXQ_ERROR_SHIFT) 18140ba35e7Swilly tarreau #define MVNETA_CAUSE_TXQ_ERROR_MASK(q) (1 << (MVNETA_CAUSE_TXQ_ERROR_SHIFT + (q))) 18240ba35e7Swilly tarreau 183c5aff182SThomas Petazzoni #define MVNETA_INTR_ENABLE 0x25b8 184c5aff182SThomas Petazzoni #define MVNETA_TXQ_INTR_ENABLE_ALL_MASK 0x0000ff00 185dc1aadf6SMarcin Wojtas #define MVNETA_RXQ_INTR_ENABLE_ALL_MASK 0x000000ff 18640ba35e7Swilly tarreau 187c5aff182SThomas Petazzoni #define MVNETA_RXQ_CMD 0x2680 188c5aff182SThomas Petazzoni #define MVNETA_RXQ_DISABLE_SHIFT 8 189c5aff182SThomas Petazzoni #define MVNETA_RXQ_ENABLE_MASK 0x000000ff 190c5aff182SThomas Petazzoni #define MVETH_TXQ_TOKEN_COUNT_REG(q) (0x2700 + ((q) << 4)) 191c5aff182SThomas Petazzoni #define MVETH_TXQ_TOKEN_CFG_REG(q) (0x2704 + ((q) << 4)) 192c5aff182SThomas Petazzoni #define MVNETA_GMAC_CTRL_0 0x2c00 193c5aff182SThomas Petazzoni #define MVNETA_GMAC_MAX_RX_SIZE_SHIFT 2 194c5aff182SThomas Petazzoni #define MVNETA_GMAC_MAX_RX_SIZE_MASK 0x7ffc 19522f4bf8aSRussell King #define MVNETA_GMAC0_PORT_1000BASE_X BIT(1) 196c5aff182SThomas Petazzoni #define MVNETA_GMAC0_PORT_ENABLE BIT(0) 197c5aff182SThomas Petazzoni #define MVNETA_GMAC_CTRL_2 0x2c08 198898b2970SStas Sergeev #define MVNETA_GMAC2_INBAND_AN_ENABLE BIT(0) 199a79121d3SThomas Petazzoni #define MVNETA_GMAC2_PCS_ENABLE BIT(3) 200c5aff182SThomas Petazzoni #define MVNETA_GMAC2_PORT_RGMII BIT(4) 201c5aff182SThomas Petazzoni #define MVNETA_GMAC2_PORT_RESET BIT(6) 202c5aff182SThomas Petazzoni #define MVNETA_GMAC_STATUS 0x2c10 203c5aff182SThomas Petazzoni #define MVNETA_GMAC_LINK_UP BIT(0) 204c5aff182SThomas Petazzoni #define MVNETA_GMAC_SPEED_1000 BIT(1) 205c5aff182SThomas Petazzoni #define MVNETA_GMAC_SPEED_100 BIT(2) 206c5aff182SThomas Petazzoni #define MVNETA_GMAC_FULL_DUPLEX BIT(3) 207c5aff182SThomas Petazzoni #define MVNETA_GMAC_RX_FLOW_CTRL_ENABLE BIT(4) 208c5aff182SThomas Petazzoni #define MVNETA_GMAC_TX_FLOW_CTRL_ENABLE BIT(5) 209c5aff182SThomas Petazzoni #define MVNETA_GMAC_RX_FLOW_CTRL_ACTIVE BIT(6) 210c5aff182SThomas Petazzoni #define MVNETA_GMAC_TX_FLOW_CTRL_ACTIVE BIT(7) 211503f9aa9SRussell King #define MVNETA_GMAC_AN_COMPLETE BIT(11) 212503f9aa9SRussell King #define MVNETA_GMAC_SYNC_OK BIT(14) 213c5aff182SThomas Petazzoni #define MVNETA_GMAC_AUTONEG_CONFIG 0x2c0c 214c5aff182SThomas Petazzoni #define MVNETA_GMAC_FORCE_LINK_DOWN BIT(0) 215c5aff182SThomas Petazzoni #define MVNETA_GMAC_FORCE_LINK_PASS BIT(1) 216898b2970SStas Sergeev #define MVNETA_GMAC_INBAND_AN_ENABLE BIT(2) 21722f4bf8aSRussell King #define MVNETA_GMAC_AN_BYPASS_ENABLE BIT(3) 21822f4bf8aSRussell King #define MVNETA_GMAC_INBAND_RESTART_AN BIT(4) 219c5aff182SThomas Petazzoni #define MVNETA_GMAC_CONFIG_MII_SPEED BIT(5) 220c5aff182SThomas Petazzoni #define MVNETA_GMAC_CONFIG_GMII_SPEED BIT(6) 22171408602SThomas Petazzoni #define MVNETA_GMAC_AN_SPEED_EN BIT(7) 22222f4bf8aSRussell King #define MVNETA_GMAC_CONFIG_FLOW_CTRL BIT(8) 22322f4bf8aSRussell King #define MVNETA_GMAC_ADVERT_SYM_FLOW_CTRL BIT(9) 224898b2970SStas Sergeev #define MVNETA_GMAC_AN_FLOW_CTRL_EN BIT(11) 225c5aff182SThomas Petazzoni #define MVNETA_GMAC_CONFIG_FULL_DUPLEX BIT(12) 22671408602SThomas Petazzoni #define MVNETA_GMAC_AN_DUPLEX_EN BIT(13) 227da58a931SMaxime Chevallier #define MVNETA_GMAC_CTRL_4 0x2c90 228da58a931SMaxime Chevallier #define MVNETA_GMAC4_SHORT_PREAMBLE_ENABLE BIT(1) 229e483911fSAndrew Lunn #define MVNETA_MIB_COUNTERS_BASE 0x3000 230c5aff182SThomas Petazzoni #define MVNETA_MIB_LATE_COLLISION 0x7c 231c5aff182SThomas Petazzoni #define MVNETA_DA_FILT_SPEC_MCAST 0x3400 232c5aff182SThomas Petazzoni #define MVNETA_DA_FILT_OTH_MCAST 0x3500 233c5aff182SThomas Petazzoni #define MVNETA_DA_FILT_UCAST_BASE 0x3600 234c5aff182SThomas Petazzoni #define MVNETA_TXQ_BASE_ADDR_REG(q) (0x3c00 + ((q) << 2)) 235c5aff182SThomas Petazzoni #define MVNETA_TXQ_SIZE_REG(q) (0x3c20 + ((q) << 2)) 236c5aff182SThomas Petazzoni #define MVNETA_TXQ_SENT_THRESH_ALL_MASK 0x3fff0000 237c5aff182SThomas Petazzoni #define MVNETA_TXQ_SENT_THRESH_MASK(coal) ((coal) << 16) 238c5aff182SThomas Petazzoni #define MVNETA_TXQ_UPDATE_REG(q) (0x3c60 + ((q) << 2)) 239c5aff182SThomas Petazzoni #define MVNETA_TXQ_DEC_SENT_SHIFT 16 2402a90f7e1SSimon Guinot #define MVNETA_TXQ_DEC_SENT_MASK 0xff 241c5aff182SThomas Petazzoni #define MVNETA_TXQ_STATUS_REG(q) (0x3c40 + ((q) << 2)) 242c5aff182SThomas Petazzoni #define MVNETA_TXQ_SENT_DESC_SHIFT 16 243c5aff182SThomas Petazzoni #define MVNETA_TXQ_SENT_DESC_MASK 0x3fff0000 244c5aff182SThomas Petazzoni #define MVNETA_PORT_TX_RESET 0x3cf0 245c5aff182SThomas Petazzoni #define MVNETA_PORT_TX_DMA_RESET BIT(0) 246c5aff182SThomas Petazzoni #define MVNETA_TX_MTU 0x3e0c 247c5aff182SThomas Petazzoni #define MVNETA_TX_TOKEN_SIZE 0x3e14 248c5aff182SThomas Petazzoni #define MVNETA_TX_TOKEN_SIZE_MAX 0xffffffff 249c5aff182SThomas Petazzoni #define MVNETA_TXQ_TOKEN_SIZE_REG(q) (0x3e40 + ((q) << 2)) 250c5aff182SThomas Petazzoni #define MVNETA_TXQ_TOKEN_SIZE_MAX 0x7fffffff 251c5aff182SThomas Petazzoni 2526d81f451SRussell King #define MVNETA_LPI_CTRL_0 0x2cc0 2536d81f451SRussell King #define MVNETA_LPI_CTRL_1 0x2cc4 2546d81f451SRussell King #define MVNETA_LPI_REQUEST_ENABLE BIT(0) 2556d81f451SRussell King #define MVNETA_LPI_CTRL_2 0x2cc8 2566d81f451SRussell King #define MVNETA_LPI_STATUS 0x2ccc 2576d81f451SRussell King 258c5aff182SThomas Petazzoni #define MVNETA_CAUSE_TXQ_SENT_DESC_ALL_MASK 0xff 259c5aff182SThomas Petazzoni 260c5aff182SThomas Petazzoni /* Descriptor ring Macros */ 261c5aff182SThomas Petazzoni #define MVNETA_QUEUE_NEXT_DESC(q, index) \ 262c5aff182SThomas Petazzoni (((index) < (q)->last_desc) ? ((index) + 1) : 0) 263c5aff182SThomas Petazzoni 264c5aff182SThomas Petazzoni /* Various constants */ 265c5aff182SThomas Petazzoni 266c5aff182SThomas Petazzoni /* Coalescing */ 26706708f81SDmitri Epshtein #define MVNETA_TXDONE_COAL_PKTS 0 /* interrupt per packet */ 268c5aff182SThomas Petazzoni #define MVNETA_RX_COAL_PKTS 32 269c5aff182SThomas Petazzoni #define MVNETA_RX_COAL_USEC 100 270c5aff182SThomas Petazzoni 2716a20c175SThomas Petazzoni /* The two bytes Marvell header. Either contains a special value used 272c5aff182SThomas Petazzoni * by Marvell switches when a specific hardware mode is enabled (not 273c5aff182SThomas Petazzoni * supported by this driver) or is filled automatically by zeroes on 274c5aff182SThomas Petazzoni * the RX side. Those two bytes being at the front of the Ethernet 275c5aff182SThomas Petazzoni * header, they allow to have the IP header aligned on a 4 bytes 276c5aff182SThomas Petazzoni * boundary automatically: the hardware skips those two bytes on its 277c5aff182SThomas Petazzoni * own. 278c5aff182SThomas Petazzoni */ 279c5aff182SThomas Petazzoni #define MVNETA_MH_SIZE 2 280c5aff182SThomas Petazzoni 281c5aff182SThomas Petazzoni #define MVNETA_VLAN_TAG_LEN 4 282c5aff182SThomas Petazzoni 2839110ee07SMarcin Wojtas #define MVNETA_TX_CSUM_DEF_SIZE 1600 284c5aff182SThomas Petazzoni #define MVNETA_TX_CSUM_MAX_SIZE 9800 285dc35a10fSMarcin Wojtas #define MVNETA_ACC_MODE_EXT1 1 286dc35a10fSMarcin Wojtas #define MVNETA_ACC_MODE_EXT2 2 287dc35a10fSMarcin Wojtas 288dc35a10fSMarcin Wojtas #define MVNETA_MAX_DECODE_WIN 6 289c5aff182SThomas Petazzoni 290c5aff182SThomas Petazzoni /* Timeout constants */ 291c5aff182SThomas Petazzoni #define MVNETA_TX_DISABLE_TIMEOUT_MSEC 1000 292c5aff182SThomas Petazzoni #define MVNETA_RX_DISABLE_TIMEOUT_MSEC 1000 293c5aff182SThomas Petazzoni #define MVNETA_TX_FIFO_EMPTY_TIMEOUT 10000 294c5aff182SThomas Petazzoni 295c5aff182SThomas Petazzoni #define MVNETA_TX_MTU_MAX 0x3ffff 296c5aff182SThomas Petazzoni 2979a401deaSGregory CLEMENT /* The RSS lookup table actually has 256 entries but we do not use 2989a401deaSGregory CLEMENT * them yet 2999a401deaSGregory CLEMENT */ 3009a401deaSGregory CLEMENT #define MVNETA_RSS_LU_TABLE_SIZE 1 3019a401deaSGregory CLEMENT 302c5aff182SThomas Petazzoni /* Max number of Rx descriptors */ 303c307e2a8SYelena Krivosheev #define MVNETA_MAX_RXD 512 304c5aff182SThomas Petazzoni 305c5aff182SThomas Petazzoni /* Max number of Tx descriptors */ 306c307e2a8SYelena Krivosheev #define MVNETA_MAX_TXD 1024 307c5aff182SThomas Petazzoni 3088eef5f97SEzequiel Garcia /* Max number of allowed TCP segments for software TSO */ 3098eef5f97SEzequiel Garcia #define MVNETA_MAX_TSO_SEGS 100 3108eef5f97SEzequiel Garcia 3118eef5f97SEzequiel Garcia #define MVNETA_MAX_SKB_DESCS (MVNETA_MAX_TSO_SEGS * 2 + MAX_SKB_FRAGS) 3128eef5f97SEzequiel Garcia 313c5aff182SThomas Petazzoni /* descriptor aligned size */ 314c5aff182SThomas Petazzoni #define MVNETA_DESC_ALIGNED_SIZE 32 315c5aff182SThomas Petazzoni 3168d5047cfSMarcin Wojtas /* Number of bytes to be taken into account by HW when putting incoming data 3178d5047cfSMarcin Wojtas * to the buffers. It is needed in case NET_SKB_PAD exceeds maximum packet 3188d5047cfSMarcin Wojtas * offset supported in MVNETA_RXQ_CONFIG_REG(q) registers. 3198d5047cfSMarcin Wojtas */ 3208d5047cfSMarcin Wojtas #define MVNETA_RX_PKT_OFFSET_CORRECTION 64 3218d5047cfSMarcin Wojtas 322c5aff182SThomas Petazzoni #define MVNETA_RX_PKT_SIZE(mtu) \ 323c5aff182SThomas Petazzoni ALIGN((mtu) + MVNETA_MH_SIZE + MVNETA_VLAN_TAG_LEN + \ 324c5aff182SThomas Petazzoni ETH_HLEN + ETH_FCS_LEN, \ 325c66e98c9SJisheng Zhang cache_line_size()) 326c5aff182SThomas Petazzoni 32744efc78dSLorenzo Bianconi #define MVNETA_SKB_HEADROOM max(XDP_PACKET_HEADROOM, NET_SKB_PAD) 3288dc9a088SLorenzo Bianconi #define MVNETA_SKB_PAD (SKB_DATA_ALIGN(sizeof(struct skb_shared_info) + \ 3290db51da7SLorenzo Bianconi MVNETA_SKB_HEADROOM)) 3308dc9a088SLorenzo Bianconi #define MVNETA_SKB_SIZE(len) (SKB_DATA_ALIGN(len) + MVNETA_SKB_PAD) 3318dc9a088SLorenzo Bianconi #define MVNETA_MAX_RX_BUF_SIZE (PAGE_SIZE - MVNETA_SKB_PAD) 3328dc9a088SLorenzo Bianconi 3332e3173a3SEzequiel Garcia #define IS_TSO_HEADER(txq, addr) \ 3342e3173a3SEzequiel Garcia ((addr >= txq->tso_hdrs_phys) && \ 3352e3173a3SEzequiel Garcia (addr < txq->tso_hdrs_phys + txq->size * TSO_HEADER_SIZE)) 3362e3173a3SEzequiel Garcia 337dc35a10fSMarcin Wojtas #define MVNETA_RX_GET_BM_POOL_ID(rxd) \ 338dc35a10fSMarcin Wojtas (((rxd)->status & MVNETA_RXD_BM_POOL_MASK) >> MVNETA_RXD_BM_POOL_SHIFT) 339c5aff182SThomas Petazzoni 3406d81f451SRussell King enum { 3416d81f451SRussell King ETHTOOL_STAT_EEE_WAKEUP, 34217a96da6SGregory CLEMENT ETHTOOL_STAT_SKB_ALLOC_ERR, 34317a96da6SGregory CLEMENT ETHTOOL_STAT_REFILL_ERR, 3443d866523SLorenzo Bianconi ETHTOOL_XDP_REDIRECT, 3453d866523SLorenzo Bianconi ETHTOOL_XDP_PASS, 3463d866523SLorenzo Bianconi ETHTOOL_XDP_DROP, 3477d51a015SLorenzo Bianconi ETHTOOL_XDP_XMIT, 3483d866523SLorenzo Bianconi ETHTOOL_XDP_TX, 3496d81f451SRussell King ETHTOOL_MAX_STATS, 3506d81f451SRussell King }; 3516d81f451SRussell King 3529b0cdefaSRussell King struct mvneta_statistic { 3539b0cdefaSRussell King unsigned short offset; 3549b0cdefaSRussell King unsigned short type; 3559b0cdefaSRussell King const char name[ETH_GSTRING_LEN]; 3569b0cdefaSRussell King }; 3579b0cdefaSRussell King 3589b0cdefaSRussell King #define T_REG_32 32 3599b0cdefaSRussell King #define T_REG_64 64 3606d81f451SRussell King #define T_SW 1 3619b0cdefaSRussell King 3626c8a8cfdSLorenzo Bianconi #define MVNETA_XDP_PASS 0 3636c8a8cfdSLorenzo Bianconi #define MVNETA_XDP_DROPPED BIT(0) 3646c8a8cfdSLorenzo Bianconi #define MVNETA_XDP_TX BIT(1) 3656c8a8cfdSLorenzo Bianconi #define MVNETA_XDP_REDIR BIT(2) 3660db51da7SLorenzo Bianconi 3679b0cdefaSRussell King static const struct mvneta_statistic mvneta_statistics[] = { 3689b0cdefaSRussell King { 0x3000, T_REG_64, "good_octets_received", }, 3699b0cdefaSRussell King { 0x3010, T_REG_32, "good_frames_received", }, 3709b0cdefaSRussell King { 0x3008, T_REG_32, "bad_octets_received", }, 3719b0cdefaSRussell King { 0x3014, T_REG_32, "bad_frames_received", }, 3729b0cdefaSRussell King { 0x3018, T_REG_32, "broadcast_frames_received", }, 3739b0cdefaSRussell King { 0x301c, T_REG_32, "multicast_frames_received", }, 3749b0cdefaSRussell King { 0x3050, T_REG_32, "unrec_mac_control_received", }, 3759b0cdefaSRussell King { 0x3058, T_REG_32, "good_fc_received", }, 3769b0cdefaSRussell King { 0x305c, T_REG_32, "bad_fc_received", }, 3779b0cdefaSRussell King { 0x3060, T_REG_32, "undersize_received", }, 3789b0cdefaSRussell King { 0x3064, T_REG_32, "fragments_received", }, 3799b0cdefaSRussell King { 0x3068, T_REG_32, "oversize_received", }, 3809b0cdefaSRussell King { 0x306c, T_REG_32, "jabber_received", }, 3819b0cdefaSRussell King { 0x3070, T_REG_32, "mac_receive_error", }, 3829b0cdefaSRussell King { 0x3074, T_REG_32, "bad_crc_event", }, 3839b0cdefaSRussell King { 0x3078, T_REG_32, "collision", }, 3849b0cdefaSRussell King { 0x307c, T_REG_32, "late_collision", }, 3859b0cdefaSRussell King { 0x2484, T_REG_32, "rx_discard", }, 3869b0cdefaSRussell King { 0x2488, T_REG_32, "rx_overrun", }, 3879b0cdefaSRussell King { 0x3020, T_REG_32, "frames_64_octets", }, 3889b0cdefaSRussell King { 0x3024, T_REG_32, "frames_65_to_127_octets", }, 3899b0cdefaSRussell King { 0x3028, T_REG_32, "frames_128_to_255_octets", }, 3909b0cdefaSRussell King { 0x302c, T_REG_32, "frames_256_to_511_octets", }, 3919b0cdefaSRussell King { 0x3030, T_REG_32, "frames_512_to_1023_octets", }, 3929b0cdefaSRussell King { 0x3034, T_REG_32, "frames_1024_to_max_octets", }, 3939b0cdefaSRussell King { 0x3038, T_REG_64, "good_octets_sent", }, 3949b0cdefaSRussell King { 0x3040, T_REG_32, "good_frames_sent", }, 3959b0cdefaSRussell King { 0x3044, T_REG_32, "excessive_collision", }, 3969b0cdefaSRussell King { 0x3048, T_REG_32, "multicast_frames_sent", }, 3979b0cdefaSRussell King { 0x304c, T_REG_32, "broadcast_frames_sent", }, 3989b0cdefaSRussell King { 0x3054, T_REG_32, "fc_sent", }, 3999b0cdefaSRussell King { 0x300c, T_REG_32, "internal_mac_transmit_err", }, 4006d81f451SRussell King { ETHTOOL_STAT_EEE_WAKEUP, T_SW, "eee_wakeup_errors", }, 40117a96da6SGregory CLEMENT { ETHTOOL_STAT_SKB_ALLOC_ERR, T_SW, "skb_alloc_errors", }, 40217a96da6SGregory CLEMENT { ETHTOOL_STAT_REFILL_ERR, T_SW, "refill_errors", }, 4037d51a015SLorenzo Bianconi { ETHTOOL_XDP_REDIRECT, T_SW, "rx_xdp_redirect", }, 4047d51a015SLorenzo Bianconi { ETHTOOL_XDP_PASS, T_SW, "rx_xdp_pass", }, 4057d51a015SLorenzo Bianconi { ETHTOOL_XDP_DROP, T_SW, "rx_xdp_drop", }, 4067d51a015SLorenzo Bianconi { ETHTOOL_XDP_TX, T_SW, "rx_xdp_tx", }, 4077d51a015SLorenzo Bianconi { ETHTOOL_XDP_XMIT, T_SW, "tx_xdp_xmit", }, 4089b0cdefaSRussell King }; 4099b0cdefaSRussell King 410320d5441SLorenzo Bianconi struct mvneta_stats { 411320d5441SLorenzo Bianconi u64 rx_packets; 412320d5441SLorenzo Bianconi u64 rx_bytes; 413320d5441SLorenzo Bianconi u64 tx_packets; 414320d5441SLorenzo Bianconi u64 tx_bytes; 4153d866523SLorenzo Bianconi /* xdp */ 4163d866523SLorenzo Bianconi u64 xdp_redirect; 4173d866523SLorenzo Bianconi u64 xdp_pass; 4183d866523SLorenzo Bianconi u64 xdp_drop; 4197d51a015SLorenzo Bianconi u64 xdp_xmit; 4203d866523SLorenzo Bianconi u64 xdp_tx; 421320d5441SLorenzo Bianconi }; 422320d5441SLorenzo Bianconi 4239ac41f3cSLorenzo Bianconi struct mvneta_ethtool_stats { 424320d5441SLorenzo Bianconi struct mvneta_stats ps; 4259ac41f3cSLorenzo Bianconi u64 skb_alloc_error; 4269ac41f3cSLorenzo Bianconi u64 refill_error; 4279ac41f3cSLorenzo Bianconi }; 4289ac41f3cSLorenzo Bianconi 42974c41b04Swilly tarreau struct mvneta_pcpu_stats { 430c5aff182SThomas Petazzoni struct u64_stats_sync syncp; 4319ac41f3cSLorenzo Bianconi 4329ac41f3cSLorenzo Bianconi struct mvneta_ethtool_stats es; 433c35947b8SLorenzo Bianconi u64 rx_dropped; 434c35947b8SLorenzo Bianconi u64 rx_errors; 435c5aff182SThomas Petazzoni }; 436c5aff182SThomas Petazzoni 43712bb03b4SMaxime Ripard struct mvneta_pcpu_port { 43812bb03b4SMaxime Ripard /* Pointer to the shared port */ 43912bb03b4SMaxime Ripard struct mvneta_port *pp; 44012bb03b4SMaxime Ripard 44112bb03b4SMaxime Ripard /* Pointer to the CPU-local NAPI struct */ 44212bb03b4SMaxime Ripard struct napi_struct napi; 44312bb03b4SMaxime Ripard 44412bb03b4SMaxime Ripard /* Cause of the previous interrupt */ 44512bb03b4SMaxime Ripard u32 cause_rx_tx; 44612bb03b4SMaxime Ripard }; 44712bb03b4SMaxime Ripard 448c5aff182SThomas Petazzoni struct mvneta_port { 449dc35a10fSMarcin Wojtas u8 id; 45012bb03b4SMaxime Ripard struct mvneta_pcpu_port __percpu *ports; 45112bb03b4SMaxime Ripard struct mvneta_pcpu_stats __percpu *stats; 45212bb03b4SMaxime Ripard 453c5aff182SThomas Petazzoni int pkt_size; 454c5aff182SThomas Petazzoni void __iomem *base; 455c5aff182SThomas Petazzoni struct mvneta_rx_queue *rxqs; 456c5aff182SThomas Petazzoni struct mvneta_tx_queue *txqs; 457c5aff182SThomas Petazzoni struct net_device *dev; 45884a3f4dbSSebastian Andrzej Siewior struct hlist_node node_online; 45984a3f4dbSSebastian Andrzej Siewior struct hlist_node node_dead; 46090b74c01SGregory CLEMENT int rxq_def; 4615888511eSGregory CLEMENT /* Protect the access to the percpu interrupt registers, 4625888511eSGregory CLEMENT * ensuring that the configuration remains coherent. 4635888511eSGregory CLEMENT */ 4645888511eSGregory CLEMENT spinlock_t lock; 465120cfa50SGregory CLEMENT bool is_stopped; 466c5aff182SThomas Petazzoni 4672636ac3cSMarcin Wojtas u32 cause_rx_tx; 4682636ac3cSMarcin Wojtas struct napi_struct napi; 4692636ac3cSMarcin Wojtas 4700db51da7SLorenzo Bianconi struct bpf_prog *xdp_prog; 4710db51da7SLorenzo Bianconi 472c5aff182SThomas Petazzoni /* Core clock */ 473189dd626SThomas Petazzoni struct clk *clk; 47415cc4a4aSJisheng Zhang /* AXI clock */ 47515cc4a4aSJisheng Zhang struct clk *clk_bus; 476c5aff182SThomas Petazzoni u8 mcast_count[256]; 477c5aff182SThomas Petazzoni u16 tx_ring_size; 478c5aff182SThomas Petazzoni u16 rx_ring_size; 479c5aff182SThomas Petazzoni 480c5aff182SThomas Petazzoni phy_interface_t phy_interface; 481503f9aa9SRussell King struct device_node *dn; 482b65657fcSSimon Guinot unsigned int tx_csum_limit; 483503f9aa9SRussell King struct phylink *phylink; 48444cc27e4SIoana Ciornei struct phylink_config phylink_config; 485a10c1c81SRussell King struct phy *comphy; 4869b0cdefaSRussell King 487dc35a10fSMarcin Wojtas struct mvneta_bm *bm_priv; 488dc35a10fSMarcin Wojtas struct mvneta_bm_pool *pool_long; 489dc35a10fSMarcin Wojtas struct mvneta_bm_pool *pool_short; 490dc35a10fSMarcin Wojtas int bm_win_id; 491dc35a10fSMarcin Wojtas 4926d81f451SRussell King bool eee_enabled; 4936d81f451SRussell King bool eee_active; 4946d81f451SRussell King bool tx_lpi_enabled; 4956d81f451SRussell King 4969b0cdefaSRussell King u64 ethtool_stats[ARRAY_SIZE(mvneta_statistics)]; 4979a401deaSGregory CLEMENT 4989a401deaSGregory CLEMENT u32 indir[MVNETA_RSS_LU_TABLE_SIZE]; 4992636ac3cSMarcin Wojtas 5002636ac3cSMarcin Wojtas /* Flags for special SoC configurations */ 5012636ac3cSMarcin Wojtas bool neta_armada3700; 5028d5047cfSMarcin Wojtas u16 rx_offset_correction; 5039768b45cSJane Li const struct mbus_dram_target_info *dram_target_info; 504c5aff182SThomas Petazzoni }; 505c5aff182SThomas Petazzoni 5066a20c175SThomas Petazzoni /* The mvneta_tx_desc and mvneta_rx_desc structures describe the 507c5aff182SThomas Petazzoni * layout of the transmit and reception DMA descriptors, and their 508c5aff182SThomas Petazzoni * layout is therefore defined by the hardware design 509c5aff182SThomas Petazzoni */ 5106083ed44SThomas Petazzoni 511c5aff182SThomas Petazzoni #define MVNETA_TX_L3_OFF_SHIFT 0 512c5aff182SThomas Petazzoni #define MVNETA_TX_IP_HLEN_SHIFT 8 513c5aff182SThomas Petazzoni #define MVNETA_TX_L4_UDP BIT(16) 514c5aff182SThomas Petazzoni #define MVNETA_TX_L3_IP6 BIT(17) 515c5aff182SThomas Petazzoni #define MVNETA_TXD_IP_CSUM BIT(18) 516c5aff182SThomas Petazzoni #define MVNETA_TXD_Z_PAD BIT(19) 517c5aff182SThomas Petazzoni #define MVNETA_TXD_L_DESC BIT(20) 518c5aff182SThomas Petazzoni #define MVNETA_TXD_F_DESC BIT(21) 519c5aff182SThomas Petazzoni #define MVNETA_TXD_FLZ_DESC (MVNETA_TXD_Z_PAD | \ 520c5aff182SThomas Petazzoni MVNETA_TXD_L_DESC | \ 521c5aff182SThomas Petazzoni MVNETA_TXD_F_DESC) 522c5aff182SThomas Petazzoni #define MVNETA_TX_L4_CSUM_FULL BIT(30) 523c5aff182SThomas Petazzoni #define MVNETA_TX_L4_CSUM_NOT BIT(31) 524c5aff182SThomas Petazzoni 525c5aff182SThomas Petazzoni #define MVNETA_RXD_ERR_CRC 0x0 526dc35a10fSMarcin Wojtas #define MVNETA_RXD_BM_POOL_SHIFT 13 527dc35a10fSMarcin Wojtas #define MVNETA_RXD_BM_POOL_MASK (BIT(13) | BIT(14)) 528c5aff182SThomas Petazzoni #define MVNETA_RXD_ERR_SUMMARY BIT(16) 529c5aff182SThomas Petazzoni #define MVNETA_RXD_ERR_OVERRUN BIT(17) 530c5aff182SThomas Petazzoni #define MVNETA_RXD_ERR_LEN BIT(18) 531c5aff182SThomas Petazzoni #define MVNETA_RXD_ERR_RESOURCE (BIT(17) | BIT(18)) 532c5aff182SThomas Petazzoni #define MVNETA_RXD_ERR_CODE_MASK (BIT(17) | BIT(18)) 533c5aff182SThomas Petazzoni #define MVNETA_RXD_L3_IP4 BIT(25) 534562e2f46SYelena Krivosheev #define MVNETA_RXD_LAST_DESC BIT(26) 535562e2f46SYelena Krivosheev #define MVNETA_RXD_FIRST_DESC BIT(27) 536562e2f46SYelena Krivosheev #define MVNETA_RXD_FIRST_LAST_DESC (MVNETA_RXD_FIRST_DESC | \ 537562e2f46SYelena Krivosheev MVNETA_RXD_LAST_DESC) 538c5aff182SThomas Petazzoni #define MVNETA_RXD_L4_CSUM_OK BIT(30) 539c5aff182SThomas Petazzoni 5409ad8fef6SThomas Petazzoni #if defined(__LITTLE_ENDIAN) 5416083ed44SThomas Petazzoni struct mvneta_tx_desc { 5426083ed44SThomas Petazzoni u32 command; /* Options used by HW for packet transmitting.*/ 543fbd1d524SAlexandre Belloni u16 reserved1; /* csum_l4 (for future use) */ 5446083ed44SThomas Petazzoni u16 data_size; /* Data size of transmitted packet in bytes */ 5456083ed44SThomas Petazzoni u32 buf_phys_addr; /* Physical addr of transmitted buffer */ 5466083ed44SThomas Petazzoni u32 reserved2; /* hw_cmd - (for future use, PMT) */ 5476083ed44SThomas Petazzoni u32 reserved3[4]; /* Reserved - (for future use) */ 5486083ed44SThomas Petazzoni }; 5496083ed44SThomas Petazzoni 5506083ed44SThomas Petazzoni struct mvneta_rx_desc { 5516083ed44SThomas Petazzoni u32 status; /* Info about received packet */ 552c5aff182SThomas Petazzoni u16 reserved1; /* pnc_info - (for future use, PnC) */ 553c5aff182SThomas Petazzoni u16 data_size; /* Size of received packet in bytes */ 5546083ed44SThomas Petazzoni 555c5aff182SThomas Petazzoni u32 buf_phys_addr; /* Physical address of the buffer */ 556c5aff182SThomas Petazzoni u32 reserved2; /* pnc_flow_id (for future use, PnC) */ 5576083ed44SThomas Petazzoni 558c5aff182SThomas Petazzoni u32 buf_cookie; /* cookie for access to RX buffer in rx path */ 559c5aff182SThomas Petazzoni u16 reserved3; /* prefetch_cmd, for future use */ 560c5aff182SThomas Petazzoni u16 reserved4; /* csum_l4 - (for future use, PnC) */ 5616083ed44SThomas Petazzoni 562c5aff182SThomas Petazzoni u32 reserved5; /* pnc_extra PnC (for future use, PnC) */ 563c5aff182SThomas Petazzoni u32 reserved6; /* hw_cmd (for future use, PnC and HWF) */ 564c5aff182SThomas Petazzoni }; 5659ad8fef6SThomas Petazzoni #else 5669ad8fef6SThomas Petazzoni struct mvneta_tx_desc { 5679ad8fef6SThomas Petazzoni u16 data_size; /* Data size of transmitted packet in bytes */ 568fbd1d524SAlexandre Belloni u16 reserved1; /* csum_l4 (for future use) */ 5699ad8fef6SThomas Petazzoni u32 command; /* Options used by HW for packet transmitting.*/ 5709ad8fef6SThomas Petazzoni u32 reserved2; /* hw_cmd - (for future use, PMT) */ 5719ad8fef6SThomas Petazzoni u32 buf_phys_addr; /* Physical addr of transmitted buffer */ 5729ad8fef6SThomas Petazzoni u32 reserved3[4]; /* Reserved - (for future use) */ 5739ad8fef6SThomas Petazzoni }; 5749ad8fef6SThomas Petazzoni 5759ad8fef6SThomas Petazzoni struct mvneta_rx_desc { 5769ad8fef6SThomas Petazzoni u16 data_size; /* Size of received packet in bytes */ 5779ad8fef6SThomas Petazzoni u16 reserved1; /* pnc_info - (for future use, PnC) */ 5789ad8fef6SThomas Petazzoni u32 status; /* Info about received packet */ 5799ad8fef6SThomas Petazzoni 5809ad8fef6SThomas Petazzoni u32 reserved2; /* pnc_flow_id (for future use, PnC) */ 5819ad8fef6SThomas Petazzoni u32 buf_phys_addr; /* Physical address of the buffer */ 5829ad8fef6SThomas Petazzoni 5839ad8fef6SThomas Petazzoni u16 reserved4; /* csum_l4 - (for future use, PnC) */ 5849ad8fef6SThomas Petazzoni u16 reserved3; /* prefetch_cmd, for future use */ 5859ad8fef6SThomas Petazzoni u32 buf_cookie; /* cookie for access to RX buffer in rx path */ 5869ad8fef6SThomas Petazzoni 5879ad8fef6SThomas Petazzoni u32 reserved5; /* pnc_extra PnC (for future use, PnC) */ 5889ad8fef6SThomas Petazzoni u32 reserved6; /* hw_cmd (for future use, PnC and HWF) */ 5899ad8fef6SThomas Petazzoni }; 5909ad8fef6SThomas Petazzoni #endif 591c5aff182SThomas Petazzoni 5929e58c8b4SLorenzo Bianconi enum mvneta_tx_buf_type { 5939e58c8b4SLorenzo Bianconi MVNETA_TYPE_SKB, 5949e58c8b4SLorenzo Bianconi MVNETA_TYPE_XDP_TX, 5959e58c8b4SLorenzo Bianconi MVNETA_TYPE_XDP_NDO, 5969e58c8b4SLorenzo Bianconi }; 5979e58c8b4SLorenzo Bianconi 5989e58c8b4SLorenzo Bianconi struct mvneta_tx_buf { 5999e58c8b4SLorenzo Bianconi enum mvneta_tx_buf_type type; 6009e58c8b4SLorenzo Bianconi union { 6019e58c8b4SLorenzo Bianconi struct xdp_frame *xdpf; 6029e58c8b4SLorenzo Bianconi struct sk_buff *skb; 6039e58c8b4SLorenzo Bianconi }; 6049e58c8b4SLorenzo Bianconi }; 6059e58c8b4SLorenzo Bianconi 606c5aff182SThomas Petazzoni struct mvneta_tx_queue { 607c5aff182SThomas Petazzoni /* Number of this TX queue, in the range 0-7 */ 608c5aff182SThomas Petazzoni u8 id; 609c5aff182SThomas Petazzoni 610c5aff182SThomas Petazzoni /* Number of TX DMA descriptors in the descriptor ring */ 611c5aff182SThomas Petazzoni int size; 612c5aff182SThomas Petazzoni 613c5aff182SThomas Petazzoni /* Number of currently used TX DMA descriptor in the 6146a20c175SThomas Petazzoni * descriptor ring 6156a20c175SThomas Petazzoni */ 616c5aff182SThomas Petazzoni int count; 6172a90f7e1SSimon Guinot int pending; 6188eef5f97SEzequiel Garcia int tx_stop_threshold; 6198eef5f97SEzequiel Garcia int tx_wake_threshold; 620c5aff182SThomas Petazzoni 6219e58c8b4SLorenzo Bianconi /* Array of transmitted buffers */ 6229e58c8b4SLorenzo Bianconi struct mvneta_tx_buf *buf; 623c5aff182SThomas Petazzoni 624c5aff182SThomas Petazzoni /* Index of last TX DMA descriptor that was inserted */ 625c5aff182SThomas Petazzoni int txq_put_index; 626c5aff182SThomas Petazzoni 627c5aff182SThomas Petazzoni /* Index of the TX DMA descriptor to be cleaned up */ 628c5aff182SThomas Petazzoni int txq_get_index; 629c5aff182SThomas Petazzoni 630c5aff182SThomas Petazzoni u32 done_pkts_coal; 631c5aff182SThomas Petazzoni 632c5aff182SThomas Petazzoni /* Virtual address of the TX DMA descriptors array */ 633c5aff182SThomas Petazzoni struct mvneta_tx_desc *descs; 634c5aff182SThomas Petazzoni 635c5aff182SThomas Petazzoni /* DMA address of the TX DMA descriptors array */ 636c5aff182SThomas Petazzoni dma_addr_t descs_phys; 637c5aff182SThomas Petazzoni 638c5aff182SThomas Petazzoni /* Index of the last TX DMA descriptor */ 639c5aff182SThomas Petazzoni int last_desc; 640c5aff182SThomas Petazzoni 641c5aff182SThomas Petazzoni /* Index of the next TX DMA descriptor to process */ 642c5aff182SThomas Petazzoni int next_desc_to_proc; 6432adb719dSEzequiel Garcia 6442adb719dSEzequiel Garcia /* DMA buffers for TSO headers */ 6452adb719dSEzequiel Garcia char *tso_hdrs; 6462adb719dSEzequiel Garcia 6472adb719dSEzequiel Garcia /* DMA address of TSO headers */ 6482adb719dSEzequiel Garcia dma_addr_t tso_hdrs_phys; 64950bf8cb6SGregory CLEMENT 65050bf8cb6SGregory CLEMENT /* Affinity mask for CPUs*/ 65150bf8cb6SGregory CLEMENT cpumask_t affinity_mask; 652c5aff182SThomas Petazzoni }; 653c5aff182SThomas Petazzoni 654c5aff182SThomas Petazzoni struct mvneta_rx_queue { 655c5aff182SThomas Petazzoni /* rx queue number, in the range 0-7 */ 656c5aff182SThomas Petazzoni u8 id; 657c5aff182SThomas Petazzoni 658c5aff182SThomas Petazzoni /* num of rx descriptors in the rx descriptor ring */ 659c5aff182SThomas Petazzoni int size; 660c5aff182SThomas Petazzoni 661c5aff182SThomas Petazzoni u32 pkts_coal; 662c5aff182SThomas Petazzoni u32 time_coal; 663c5aff182SThomas Petazzoni 664568a3fa2SLorenzo Bianconi /* page_pool */ 665568a3fa2SLorenzo Bianconi struct page_pool *page_pool; 666568a3fa2SLorenzo Bianconi struct xdp_rxq_info xdp_rxq; 667568a3fa2SLorenzo Bianconi 668f88bee1cSGregory CLEMENT /* Virtual address of the RX buffer */ 669f88bee1cSGregory CLEMENT void **buf_virt_addr; 670f88bee1cSGregory CLEMENT 671c5aff182SThomas Petazzoni /* Virtual address of the RX DMA descriptors array */ 672c5aff182SThomas Petazzoni struct mvneta_rx_desc *descs; 673c5aff182SThomas Petazzoni 674c5aff182SThomas Petazzoni /* DMA address of the RX DMA descriptors array */ 675c5aff182SThomas Petazzoni dma_addr_t descs_phys; 676c5aff182SThomas Petazzoni 677c5aff182SThomas Petazzoni /* Index of the last RX DMA descriptor */ 678c5aff182SThomas Petazzoni int last_desc; 679c5aff182SThomas Petazzoni 680c5aff182SThomas Petazzoni /* Index of the next RX DMA descriptor to process */ 681c5aff182SThomas Petazzoni int next_desc_to_proc; 68217a96da6SGregory CLEMENT 683562e2f46SYelena Krivosheev /* Index of first RX DMA descriptor to refill */ 684562e2f46SYelena Krivosheev int first_to_refill; 685562e2f46SYelena Krivosheev u32 refill_num; 686562e2f46SYelena Krivosheev 687562e2f46SYelena Krivosheev /* pointer to uncomplete skb buffer */ 688562e2f46SYelena Krivosheev struct sk_buff *skb; 689562e2f46SYelena Krivosheev int left_size; 690c5aff182SThomas Petazzoni }; 691c5aff182SThomas Petazzoni 69284a3f4dbSSebastian Andrzej Siewior static enum cpuhp_state online_hpstate; 693edadb7faSEzequiel Garcia /* The hardware supports eight (8) rx queues, but we are only allowing 694edadb7faSEzequiel Garcia * the first one to be used. Therefore, let's just allocate one queue. 695edadb7faSEzequiel Garcia */ 696d8936657SMaxime Ripard static int rxq_number = 8; 697c5aff182SThomas Petazzoni static int txq_number = 8; 698c5aff182SThomas Petazzoni 699c5aff182SThomas Petazzoni static int rxq_def; 700c5aff182SThomas Petazzoni 701f19fadfcSwilly tarreau static int rx_copybreak __read_mostly = 256; 702f19fadfcSwilly tarreau 703dc35a10fSMarcin Wojtas /* HW BM need that each port be identify by a unique ID */ 704dc35a10fSMarcin Wojtas static int global_port_id; 705dc35a10fSMarcin Wojtas 706c5aff182SThomas Petazzoni #define MVNETA_DRIVER_NAME "mvneta" 707c5aff182SThomas Petazzoni #define MVNETA_DRIVER_VERSION "1.0" 708c5aff182SThomas Petazzoni 709c5aff182SThomas Petazzoni /* Utility/helper methods */ 710c5aff182SThomas Petazzoni 711c5aff182SThomas Petazzoni /* Write helper method */ 712c5aff182SThomas Petazzoni static void mvreg_write(struct mvneta_port *pp, u32 offset, u32 data) 713c5aff182SThomas Petazzoni { 714c5aff182SThomas Petazzoni writel(data, pp->base + offset); 715c5aff182SThomas Petazzoni } 716c5aff182SThomas Petazzoni 717c5aff182SThomas Petazzoni /* Read helper method */ 718c5aff182SThomas Petazzoni static u32 mvreg_read(struct mvneta_port *pp, u32 offset) 719c5aff182SThomas Petazzoni { 720c5aff182SThomas Petazzoni return readl(pp->base + offset); 721c5aff182SThomas Petazzoni } 722c5aff182SThomas Petazzoni 723c5aff182SThomas Petazzoni /* Increment txq get counter */ 724c5aff182SThomas Petazzoni static void mvneta_txq_inc_get(struct mvneta_tx_queue *txq) 725c5aff182SThomas Petazzoni { 726c5aff182SThomas Petazzoni txq->txq_get_index++; 727c5aff182SThomas Petazzoni if (txq->txq_get_index == txq->size) 728c5aff182SThomas Petazzoni txq->txq_get_index = 0; 729c5aff182SThomas Petazzoni } 730c5aff182SThomas Petazzoni 731c5aff182SThomas Petazzoni /* Increment txq put counter */ 732c5aff182SThomas Petazzoni static void mvneta_txq_inc_put(struct mvneta_tx_queue *txq) 733c5aff182SThomas Petazzoni { 734c5aff182SThomas Petazzoni txq->txq_put_index++; 735c5aff182SThomas Petazzoni if (txq->txq_put_index == txq->size) 736c5aff182SThomas Petazzoni txq->txq_put_index = 0; 737c5aff182SThomas Petazzoni } 738c5aff182SThomas Petazzoni 739c5aff182SThomas Petazzoni 740c5aff182SThomas Petazzoni /* Clear all MIB counters */ 741c5aff182SThomas Petazzoni static void mvneta_mib_counters_clear(struct mvneta_port *pp) 742c5aff182SThomas Petazzoni { 743c5aff182SThomas Petazzoni int i; 744c5aff182SThomas Petazzoni u32 dummy; 745c5aff182SThomas Petazzoni 746c5aff182SThomas Petazzoni /* Perform dummy reads from MIB counters */ 747c5aff182SThomas Petazzoni for (i = 0; i < MVNETA_MIB_LATE_COLLISION; i += 4) 748c5aff182SThomas Petazzoni dummy = mvreg_read(pp, (MVNETA_MIB_COUNTERS_BASE + i)); 749e483911fSAndrew Lunn dummy = mvreg_read(pp, MVNETA_RX_DISCARD_FRAME_COUNT); 750e483911fSAndrew Lunn dummy = mvreg_read(pp, MVNETA_OVERRUN_FRAME_COUNT); 751c5aff182SThomas Petazzoni } 752c5aff182SThomas Petazzoni 753c5aff182SThomas Petazzoni /* Get System Network Statistics */ 754bc1f4470Sstephen hemminger static void 7552dc0d2b4SBaoyou Xie mvneta_get_stats64(struct net_device *dev, 756c5aff182SThomas Petazzoni struct rtnl_link_stats64 *stats) 757c5aff182SThomas Petazzoni { 758c5aff182SThomas Petazzoni struct mvneta_port *pp = netdev_priv(dev); 759c5aff182SThomas Petazzoni unsigned int start; 76074c41b04Swilly tarreau int cpu; 761c5aff182SThomas Petazzoni 76274c41b04Swilly tarreau for_each_possible_cpu(cpu) { 76374c41b04Swilly tarreau struct mvneta_pcpu_stats *cpu_stats; 76474c41b04Swilly tarreau u64 rx_packets; 76574c41b04Swilly tarreau u64 rx_bytes; 766c35947b8SLorenzo Bianconi u64 rx_dropped; 767c35947b8SLorenzo Bianconi u64 rx_errors; 76874c41b04Swilly tarreau u64 tx_packets; 76974c41b04Swilly tarreau u64 tx_bytes; 770c5aff182SThomas Petazzoni 77174c41b04Swilly tarreau cpu_stats = per_cpu_ptr(pp->stats, cpu); 772c5aff182SThomas Petazzoni do { 77357a7744eSEric W. Biederman start = u64_stats_fetch_begin_irq(&cpu_stats->syncp); 774320d5441SLorenzo Bianconi rx_packets = cpu_stats->es.ps.rx_packets; 775320d5441SLorenzo Bianconi rx_bytes = cpu_stats->es.ps.rx_bytes; 776c35947b8SLorenzo Bianconi rx_dropped = cpu_stats->rx_dropped; 777c35947b8SLorenzo Bianconi rx_errors = cpu_stats->rx_errors; 778320d5441SLorenzo Bianconi tx_packets = cpu_stats->es.ps.tx_packets; 779320d5441SLorenzo Bianconi tx_bytes = cpu_stats->es.ps.tx_bytes; 78057a7744eSEric W. Biederman } while (u64_stats_fetch_retry_irq(&cpu_stats->syncp, start)); 781c5aff182SThomas Petazzoni 78274c41b04Swilly tarreau stats->rx_packets += rx_packets; 78374c41b04Swilly tarreau stats->rx_bytes += rx_bytes; 784c35947b8SLorenzo Bianconi stats->rx_dropped += rx_dropped; 785c35947b8SLorenzo Bianconi stats->rx_errors += rx_errors; 78674c41b04Swilly tarreau stats->tx_packets += tx_packets; 78774c41b04Swilly tarreau stats->tx_bytes += tx_bytes; 78874c41b04Swilly tarreau } 789c5aff182SThomas Petazzoni 790c5aff182SThomas Petazzoni stats->tx_dropped = dev->stats.tx_dropped; 791c5aff182SThomas Petazzoni } 792c5aff182SThomas Petazzoni 793c5aff182SThomas Petazzoni /* Rx descriptors helper methods */ 794c5aff182SThomas Petazzoni 7955428213cSwilly tarreau /* Checks whether the RX descriptor having this status is both the first 7965428213cSwilly tarreau * and the last descriptor for the RX packet. Each RX packet is currently 797c5aff182SThomas Petazzoni * received through a single RX descriptor, so not having each RX 798c5aff182SThomas Petazzoni * descriptor with its first and last bits set is an error 799c5aff182SThomas Petazzoni */ 8005428213cSwilly tarreau static int mvneta_rxq_desc_is_first_last(u32 status) 801c5aff182SThomas Petazzoni { 8025428213cSwilly tarreau return (status & MVNETA_RXD_FIRST_LAST_DESC) == 803c5aff182SThomas Petazzoni MVNETA_RXD_FIRST_LAST_DESC; 804c5aff182SThomas Petazzoni } 805c5aff182SThomas Petazzoni 806c5aff182SThomas Petazzoni /* Add number of descriptors ready to receive new packets */ 807c5aff182SThomas Petazzoni static void mvneta_rxq_non_occup_desc_add(struct mvneta_port *pp, 808c5aff182SThomas Petazzoni struct mvneta_rx_queue *rxq, 809c5aff182SThomas Petazzoni int ndescs) 810c5aff182SThomas Petazzoni { 811c5aff182SThomas Petazzoni /* Only MVNETA_RXQ_ADD_NON_OCCUPIED_MAX (255) descriptors can 8126a20c175SThomas Petazzoni * be added at once 8136a20c175SThomas Petazzoni */ 814c5aff182SThomas Petazzoni while (ndescs > MVNETA_RXQ_ADD_NON_OCCUPIED_MAX) { 815c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id), 816c5aff182SThomas Petazzoni (MVNETA_RXQ_ADD_NON_OCCUPIED_MAX << 817c5aff182SThomas Petazzoni MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT)); 818c5aff182SThomas Petazzoni ndescs -= MVNETA_RXQ_ADD_NON_OCCUPIED_MAX; 819c5aff182SThomas Petazzoni } 820c5aff182SThomas Petazzoni 821c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id), 822c5aff182SThomas Petazzoni (ndescs << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT)); 823c5aff182SThomas Petazzoni } 824c5aff182SThomas Petazzoni 825c5aff182SThomas Petazzoni /* Get number of RX descriptors occupied by received packets */ 826c5aff182SThomas Petazzoni static int mvneta_rxq_busy_desc_num_get(struct mvneta_port *pp, 827c5aff182SThomas Petazzoni struct mvneta_rx_queue *rxq) 828c5aff182SThomas Petazzoni { 829c5aff182SThomas Petazzoni u32 val; 830c5aff182SThomas Petazzoni 831c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_RXQ_STATUS_REG(rxq->id)); 832c5aff182SThomas Petazzoni return val & MVNETA_RXQ_OCCUPIED_ALL_MASK; 833c5aff182SThomas Petazzoni } 834c5aff182SThomas Petazzoni 8356a20c175SThomas Petazzoni /* Update num of rx desc called upon return from rx path or 836c5aff182SThomas Petazzoni * from mvneta_rxq_drop_pkts(). 837c5aff182SThomas Petazzoni */ 838c5aff182SThomas Petazzoni static void mvneta_rxq_desc_num_update(struct mvneta_port *pp, 839c5aff182SThomas Petazzoni struct mvneta_rx_queue *rxq, 840c5aff182SThomas Petazzoni int rx_done, int rx_filled) 841c5aff182SThomas Petazzoni { 842c5aff182SThomas Petazzoni u32 val; 843c5aff182SThomas Petazzoni 844c5aff182SThomas Petazzoni if ((rx_done <= 0xff) && (rx_filled <= 0xff)) { 845c5aff182SThomas Petazzoni val = rx_done | 846c5aff182SThomas Petazzoni (rx_filled << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT); 847c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id), val); 848c5aff182SThomas Petazzoni return; 849c5aff182SThomas Petazzoni } 850c5aff182SThomas Petazzoni 851c5aff182SThomas Petazzoni /* Only 255 descriptors can be added at once */ 852c5aff182SThomas Petazzoni while ((rx_done > 0) || (rx_filled > 0)) { 853c5aff182SThomas Petazzoni if (rx_done <= 0xff) { 854c5aff182SThomas Petazzoni val = rx_done; 855c5aff182SThomas Petazzoni rx_done = 0; 856c5aff182SThomas Petazzoni } else { 857c5aff182SThomas Petazzoni val = 0xff; 858c5aff182SThomas Petazzoni rx_done -= 0xff; 859c5aff182SThomas Petazzoni } 860c5aff182SThomas Petazzoni if (rx_filled <= 0xff) { 861c5aff182SThomas Petazzoni val |= rx_filled << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT; 862c5aff182SThomas Petazzoni rx_filled = 0; 863c5aff182SThomas Petazzoni } else { 864c5aff182SThomas Petazzoni val |= 0xff << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT; 865c5aff182SThomas Petazzoni rx_filled -= 0xff; 866c5aff182SThomas Petazzoni } 867c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id), val); 868c5aff182SThomas Petazzoni } 869c5aff182SThomas Petazzoni } 870c5aff182SThomas Petazzoni 871c5aff182SThomas Petazzoni /* Get pointer to next RX descriptor to be processed by SW */ 872c5aff182SThomas Petazzoni static struct mvneta_rx_desc * 873c5aff182SThomas Petazzoni mvneta_rxq_next_desc_get(struct mvneta_rx_queue *rxq) 874c5aff182SThomas Petazzoni { 875c5aff182SThomas Petazzoni int rx_desc = rxq->next_desc_to_proc; 876c5aff182SThomas Petazzoni 877c5aff182SThomas Petazzoni rxq->next_desc_to_proc = MVNETA_QUEUE_NEXT_DESC(rxq, rx_desc); 87834e4179dSwilly tarreau prefetch(rxq->descs + rxq->next_desc_to_proc); 879c5aff182SThomas Petazzoni return rxq->descs + rx_desc; 880c5aff182SThomas Petazzoni } 881c5aff182SThomas Petazzoni 882c5aff182SThomas Petazzoni /* Change maximum receive size of the port. */ 883c5aff182SThomas Petazzoni static void mvneta_max_rx_size_set(struct mvneta_port *pp, int max_rx_size) 884c5aff182SThomas Petazzoni { 885c5aff182SThomas Petazzoni u32 val; 886c5aff182SThomas Petazzoni 887c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_GMAC_CTRL_0); 888c5aff182SThomas Petazzoni val &= ~MVNETA_GMAC_MAX_RX_SIZE_MASK; 889c5aff182SThomas Petazzoni val |= ((max_rx_size - MVNETA_MH_SIZE) / 2) << 890c5aff182SThomas Petazzoni MVNETA_GMAC_MAX_RX_SIZE_SHIFT; 891c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_GMAC_CTRL_0, val); 892c5aff182SThomas Petazzoni } 893c5aff182SThomas Petazzoni 894c5aff182SThomas Petazzoni 895c5aff182SThomas Petazzoni /* Set rx queue offset */ 896c5aff182SThomas Petazzoni static void mvneta_rxq_offset_set(struct mvneta_port *pp, 897c5aff182SThomas Petazzoni struct mvneta_rx_queue *rxq, 898c5aff182SThomas Petazzoni int offset) 899c5aff182SThomas Petazzoni { 900c5aff182SThomas Petazzoni u32 val; 901c5aff182SThomas Petazzoni 902c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_RXQ_CONFIG_REG(rxq->id)); 903c5aff182SThomas Petazzoni val &= ~MVNETA_RXQ_PKT_OFFSET_ALL_MASK; 904c5aff182SThomas Petazzoni 905c5aff182SThomas Petazzoni /* Offset is in */ 906c5aff182SThomas Petazzoni val |= MVNETA_RXQ_PKT_OFFSET_MASK(offset >> 3); 907c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_RXQ_CONFIG_REG(rxq->id), val); 908c5aff182SThomas Petazzoni } 909c5aff182SThomas Petazzoni 910c5aff182SThomas Petazzoni 911c5aff182SThomas Petazzoni /* Tx descriptors helper methods */ 912c5aff182SThomas Petazzoni 913c5aff182SThomas Petazzoni /* Update HW with number of TX descriptors to be sent */ 914c5aff182SThomas Petazzoni static void mvneta_txq_pend_desc_add(struct mvneta_port *pp, 915c5aff182SThomas Petazzoni struct mvneta_tx_queue *txq, 916c5aff182SThomas Petazzoni int pend_desc) 917c5aff182SThomas Petazzoni { 918c5aff182SThomas Petazzoni u32 val; 919c5aff182SThomas Petazzoni 9200d63785cSSimon Guinot pend_desc += txq->pending; 9210d63785cSSimon Guinot 9220d63785cSSimon Guinot /* Only 255 Tx descriptors can be added at once */ 9230d63785cSSimon Guinot do { 9240d63785cSSimon Guinot val = min(pend_desc, 255); 925c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val); 9260d63785cSSimon Guinot pend_desc -= val; 9270d63785cSSimon Guinot } while (pend_desc > 0); 9282a90f7e1SSimon Guinot txq->pending = 0; 929c5aff182SThomas Petazzoni } 930c5aff182SThomas Petazzoni 931c5aff182SThomas Petazzoni /* Get pointer to next TX descriptor to be processed (send) by HW */ 932c5aff182SThomas Petazzoni static struct mvneta_tx_desc * 933c5aff182SThomas Petazzoni mvneta_txq_next_desc_get(struct mvneta_tx_queue *txq) 934c5aff182SThomas Petazzoni { 935c5aff182SThomas Petazzoni int tx_desc = txq->next_desc_to_proc; 936c5aff182SThomas Petazzoni 937c5aff182SThomas Petazzoni txq->next_desc_to_proc = MVNETA_QUEUE_NEXT_DESC(txq, tx_desc); 938c5aff182SThomas Petazzoni return txq->descs + tx_desc; 939c5aff182SThomas Petazzoni } 940c5aff182SThomas Petazzoni 941c5aff182SThomas Petazzoni /* Release the last allocated TX descriptor. Useful to handle DMA 9426a20c175SThomas Petazzoni * mapping failures in the TX path. 9436a20c175SThomas Petazzoni */ 944c5aff182SThomas Petazzoni static void mvneta_txq_desc_put(struct mvneta_tx_queue *txq) 945c5aff182SThomas Petazzoni { 946c5aff182SThomas Petazzoni if (txq->next_desc_to_proc == 0) 947c5aff182SThomas Petazzoni txq->next_desc_to_proc = txq->last_desc - 1; 948c5aff182SThomas Petazzoni else 949c5aff182SThomas Petazzoni txq->next_desc_to_proc--; 950c5aff182SThomas Petazzoni } 951c5aff182SThomas Petazzoni 952c5aff182SThomas Petazzoni /* Set rxq buf size */ 953c5aff182SThomas Petazzoni static void mvneta_rxq_buf_size_set(struct mvneta_port *pp, 954c5aff182SThomas Petazzoni struct mvneta_rx_queue *rxq, 955c5aff182SThomas Petazzoni int buf_size) 956c5aff182SThomas Petazzoni { 957c5aff182SThomas Petazzoni u32 val; 958c5aff182SThomas Petazzoni 959c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_RXQ_SIZE_REG(rxq->id)); 960c5aff182SThomas Petazzoni 961c5aff182SThomas Petazzoni val &= ~MVNETA_RXQ_BUF_SIZE_MASK; 962c5aff182SThomas Petazzoni val |= ((buf_size >> 3) << MVNETA_RXQ_BUF_SIZE_SHIFT); 963c5aff182SThomas Petazzoni 964c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_RXQ_SIZE_REG(rxq->id), val); 965c5aff182SThomas Petazzoni } 966c5aff182SThomas Petazzoni 967c5aff182SThomas Petazzoni /* Disable buffer management (BM) */ 968c5aff182SThomas Petazzoni static void mvneta_rxq_bm_disable(struct mvneta_port *pp, 969c5aff182SThomas Petazzoni struct mvneta_rx_queue *rxq) 970c5aff182SThomas Petazzoni { 971c5aff182SThomas Petazzoni u32 val; 972c5aff182SThomas Petazzoni 973c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_RXQ_CONFIG_REG(rxq->id)); 974c5aff182SThomas Petazzoni val &= ~MVNETA_RXQ_HW_BUF_ALLOC; 975c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_RXQ_CONFIG_REG(rxq->id), val); 976c5aff182SThomas Petazzoni } 977c5aff182SThomas Petazzoni 978dc35a10fSMarcin Wojtas /* Enable buffer management (BM) */ 979dc35a10fSMarcin Wojtas static void mvneta_rxq_bm_enable(struct mvneta_port *pp, 980dc35a10fSMarcin Wojtas struct mvneta_rx_queue *rxq) 981dc35a10fSMarcin Wojtas { 982dc35a10fSMarcin Wojtas u32 val; 983dc35a10fSMarcin Wojtas 984dc35a10fSMarcin Wojtas val = mvreg_read(pp, MVNETA_RXQ_CONFIG_REG(rxq->id)); 985dc35a10fSMarcin Wojtas val |= MVNETA_RXQ_HW_BUF_ALLOC; 986dc35a10fSMarcin Wojtas mvreg_write(pp, MVNETA_RXQ_CONFIG_REG(rxq->id), val); 987dc35a10fSMarcin Wojtas } 988dc35a10fSMarcin Wojtas 989dc35a10fSMarcin Wojtas /* Notify HW about port's assignment of pool for bigger packets */ 990dc35a10fSMarcin Wojtas static void mvneta_rxq_long_pool_set(struct mvneta_port *pp, 991dc35a10fSMarcin Wojtas struct mvneta_rx_queue *rxq) 992dc35a10fSMarcin Wojtas { 993dc35a10fSMarcin Wojtas u32 val; 994dc35a10fSMarcin Wojtas 995dc35a10fSMarcin Wojtas val = mvreg_read(pp, MVNETA_RXQ_CONFIG_REG(rxq->id)); 996dc35a10fSMarcin Wojtas val &= ~MVNETA_RXQ_LONG_POOL_ID_MASK; 997dc35a10fSMarcin Wojtas val |= (pp->pool_long->id << MVNETA_RXQ_LONG_POOL_ID_SHIFT); 998dc35a10fSMarcin Wojtas 999dc35a10fSMarcin Wojtas mvreg_write(pp, MVNETA_RXQ_CONFIG_REG(rxq->id), val); 1000dc35a10fSMarcin Wojtas } 1001dc35a10fSMarcin Wojtas 1002dc35a10fSMarcin Wojtas /* Notify HW about port's assignment of pool for smaller packets */ 1003dc35a10fSMarcin Wojtas static void mvneta_rxq_short_pool_set(struct mvneta_port *pp, 1004dc35a10fSMarcin Wojtas struct mvneta_rx_queue *rxq) 1005dc35a10fSMarcin Wojtas { 1006dc35a10fSMarcin Wojtas u32 val; 1007dc35a10fSMarcin Wojtas 1008dc35a10fSMarcin Wojtas val = mvreg_read(pp, MVNETA_RXQ_CONFIG_REG(rxq->id)); 1009dc35a10fSMarcin Wojtas val &= ~MVNETA_RXQ_SHORT_POOL_ID_MASK; 1010dc35a10fSMarcin Wojtas val |= (pp->pool_short->id << MVNETA_RXQ_SHORT_POOL_ID_SHIFT); 1011dc35a10fSMarcin Wojtas 1012dc35a10fSMarcin Wojtas mvreg_write(pp, MVNETA_RXQ_CONFIG_REG(rxq->id), val); 1013dc35a10fSMarcin Wojtas } 1014dc35a10fSMarcin Wojtas 1015dc35a10fSMarcin Wojtas /* Set port's receive buffer size for assigned BM pool */ 1016dc35a10fSMarcin Wojtas static inline void mvneta_bm_pool_bufsize_set(struct mvneta_port *pp, 1017dc35a10fSMarcin Wojtas int buf_size, 1018dc35a10fSMarcin Wojtas u8 pool_id) 1019dc35a10fSMarcin Wojtas { 1020dc35a10fSMarcin Wojtas u32 val; 1021dc35a10fSMarcin Wojtas 1022dc35a10fSMarcin Wojtas if (!IS_ALIGNED(buf_size, 8)) { 1023dc35a10fSMarcin Wojtas dev_warn(pp->dev->dev.parent, 1024dc35a10fSMarcin Wojtas "illegal buf_size value %d, round to %d\n", 1025dc35a10fSMarcin Wojtas buf_size, ALIGN(buf_size, 8)); 1026dc35a10fSMarcin Wojtas buf_size = ALIGN(buf_size, 8); 1027dc35a10fSMarcin Wojtas } 1028dc35a10fSMarcin Wojtas 1029dc35a10fSMarcin Wojtas val = mvreg_read(pp, MVNETA_PORT_POOL_BUFFER_SZ_REG(pool_id)); 1030dc35a10fSMarcin Wojtas val |= buf_size & MVNETA_PORT_POOL_BUFFER_SZ_MASK; 1031dc35a10fSMarcin Wojtas mvreg_write(pp, MVNETA_PORT_POOL_BUFFER_SZ_REG(pool_id), val); 1032dc35a10fSMarcin Wojtas } 1033dc35a10fSMarcin Wojtas 1034dc35a10fSMarcin Wojtas /* Configure MBUS window in order to enable access BM internal SRAM */ 1035dc35a10fSMarcin Wojtas static int mvneta_mbus_io_win_set(struct mvneta_port *pp, u32 base, u32 wsize, 1036dc35a10fSMarcin Wojtas u8 target, u8 attr) 1037dc35a10fSMarcin Wojtas { 1038dc35a10fSMarcin Wojtas u32 win_enable, win_protect; 1039dc35a10fSMarcin Wojtas int i; 1040dc35a10fSMarcin Wojtas 1041dc35a10fSMarcin Wojtas win_enable = mvreg_read(pp, MVNETA_BASE_ADDR_ENABLE); 1042dc35a10fSMarcin Wojtas 1043dc35a10fSMarcin Wojtas if (pp->bm_win_id < 0) { 1044dc35a10fSMarcin Wojtas /* Find first not occupied window */ 1045dc35a10fSMarcin Wojtas for (i = 0; i < MVNETA_MAX_DECODE_WIN; i++) { 1046dc35a10fSMarcin Wojtas if (win_enable & (1 << i)) { 1047dc35a10fSMarcin Wojtas pp->bm_win_id = i; 1048dc35a10fSMarcin Wojtas break; 1049dc35a10fSMarcin Wojtas } 1050dc35a10fSMarcin Wojtas } 1051dc35a10fSMarcin Wojtas if (i == MVNETA_MAX_DECODE_WIN) 1052dc35a10fSMarcin Wojtas return -ENOMEM; 1053dc35a10fSMarcin Wojtas } else { 1054dc35a10fSMarcin Wojtas i = pp->bm_win_id; 1055dc35a10fSMarcin Wojtas } 1056dc35a10fSMarcin Wojtas 1057dc35a10fSMarcin Wojtas mvreg_write(pp, MVNETA_WIN_BASE(i), 0); 1058dc35a10fSMarcin Wojtas mvreg_write(pp, MVNETA_WIN_SIZE(i), 0); 1059dc35a10fSMarcin Wojtas 1060dc35a10fSMarcin Wojtas if (i < 4) 1061dc35a10fSMarcin Wojtas mvreg_write(pp, MVNETA_WIN_REMAP(i), 0); 1062dc35a10fSMarcin Wojtas 1063dc35a10fSMarcin Wojtas mvreg_write(pp, MVNETA_WIN_BASE(i), (base & 0xffff0000) | 1064dc35a10fSMarcin Wojtas (attr << 8) | target); 1065dc35a10fSMarcin Wojtas 1066dc35a10fSMarcin Wojtas mvreg_write(pp, MVNETA_WIN_SIZE(i), (wsize - 1) & 0xffff0000); 1067dc35a10fSMarcin Wojtas 1068dc35a10fSMarcin Wojtas win_protect = mvreg_read(pp, MVNETA_ACCESS_PROTECT_ENABLE); 1069dc35a10fSMarcin Wojtas win_protect |= 3 << (2 * i); 1070dc35a10fSMarcin Wojtas mvreg_write(pp, MVNETA_ACCESS_PROTECT_ENABLE, win_protect); 1071dc35a10fSMarcin Wojtas 1072dc35a10fSMarcin Wojtas win_enable &= ~(1 << i); 1073dc35a10fSMarcin Wojtas mvreg_write(pp, MVNETA_BASE_ADDR_ENABLE, win_enable); 1074dc35a10fSMarcin Wojtas 1075dc35a10fSMarcin Wojtas return 0; 1076dc35a10fSMarcin Wojtas } 1077dc35a10fSMarcin Wojtas 10782636ac3cSMarcin Wojtas static int mvneta_bm_port_mbus_init(struct mvneta_port *pp) 1079dc35a10fSMarcin Wojtas { 10802636ac3cSMarcin Wojtas u32 wsize; 1081dc35a10fSMarcin Wojtas u8 target, attr; 1082dc35a10fSMarcin Wojtas int err; 1083dc35a10fSMarcin Wojtas 1084dc35a10fSMarcin Wojtas /* Get BM window information */ 1085dc35a10fSMarcin Wojtas err = mvebu_mbus_get_io_win_info(pp->bm_priv->bppi_phys_addr, &wsize, 1086dc35a10fSMarcin Wojtas &target, &attr); 1087dc35a10fSMarcin Wojtas if (err < 0) 1088dc35a10fSMarcin Wojtas return err; 1089dc35a10fSMarcin Wojtas 1090dc35a10fSMarcin Wojtas pp->bm_win_id = -1; 1091dc35a10fSMarcin Wojtas 1092dc35a10fSMarcin Wojtas /* Open NETA -> BM window */ 1093dc35a10fSMarcin Wojtas err = mvneta_mbus_io_win_set(pp, pp->bm_priv->bppi_phys_addr, wsize, 1094dc35a10fSMarcin Wojtas target, attr); 1095dc35a10fSMarcin Wojtas if (err < 0) { 1096dc35a10fSMarcin Wojtas netdev_info(pp->dev, "fail to configure mbus window to BM\n"); 1097dc35a10fSMarcin Wojtas return err; 1098dc35a10fSMarcin Wojtas } 10992636ac3cSMarcin Wojtas return 0; 11002636ac3cSMarcin Wojtas } 11012636ac3cSMarcin Wojtas 11022636ac3cSMarcin Wojtas /* Assign and initialize pools for port. In case of fail 11032636ac3cSMarcin Wojtas * buffer manager will remain disabled for current port. 11042636ac3cSMarcin Wojtas */ 11052636ac3cSMarcin Wojtas static int mvneta_bm_port_init(struct platform_device *pdev, 11062636ac3cSMarcin Wojtas struct mvneta_port *pp) 11072636ac3cSMarcin Wojtas { 11082636ac3cSMarcin Wojtas struct device_node *dn = pdev->dev.of_node; 11092636ac3cSMarcin Wojtas u32 long_pool_id, short_pool_id; 11102636ac3cSMarcin Wojtas 11112636ac3cSMarcin Wojtas if (!pp->neta_armada3700) { 11122636ac3cSMarcin Wojtas int ret; 11132636ac3cSMarcin Wojtas 11142636ac3cSMarcin Wojtas ret = mvneta_bm_port_mbus_init(pp); 11152636ac3cSMarcin Wojtas if (ret) 11162636ac3cSMarcin Wojtas return ret; 11172636ac3cSMarcin Wojtas } 1118dc35a10fSMarcin Wojtas 1119dc35a10fSMarcin Wojtas if (of_property_read_u32(dn, "bm,pool-long", &long_pool_id)) { 1120dc35a10fSMarcin Wojtas netdev_info(pp->dev, "missing long pool id\n"); 1121dc35a10fSMarcin Wojtas return -EINVAL; 1122dc35a10fSMarcin Wojtas } 1123dc35a10fSMarcin Wojtas 1124dc35a10fSMarcin Wojtas /* Create port's long pool depending on mtu */ 1125dc35a10fSMarcin Wojtas pp->pool_long = mvneta_bm_pool_use(pp->bm_priv, long_pool_id, 1126dc35a10fSMarcin Wojtas MVNETA_BM_LONG, pp->id, 1127dc35a10fSMarcin Wojtas MVNETA_RX_PKT_SIZE(pp->dev->mtu)); 1128dc35a10fSMarcin Wojtas if (!pp->pool_long) { 1129dc35a10fSMarcin Wojtas netdev_info(pp->dev, "fail to obtain long pool for port\n"); 1130dc35a10fSMarcin Wojtas return -ENOMEM; 1131dc35a10fSMarcin Wojtas } 1132dc35a10fSMarcin Wojtas 1133dc35a10fSMarcin Wojtas pp->pool_long->port_map |= 1 << pp->id; 1134dc35a10fSMarcin Wojtas 1135dc35a10fSMarcin Wojtas mvneta_bm_pool_bufsize_set(pp, pp->pool_long->buf_size, 1136dc35a10fSMarcin Wojtas pp->pool_long->id); 1137dc35a10fSMarcin Wojtas 1138dc35a10fSMarcin Wojtas /* If short pool id is not defined, assume using single pool */ 1139dc35a10fSMarcin Wojtas if (of_property_read_u32(dn, "bm,pool-short", &short_pool_id)) 1140dc35a10fSMarcin Wojtas short_pool_id = long_pool_id; 1141dc35a10fSMarcin Wojtas 1142dc35a10fSMarcin Wojtas /* Create port's short pool */ 1143dc35a10fSMarcin Wojtas pp->pool_short = mvneta_bm_pool_use(pp->bm_priv, short_pool_id, 1144dc35a10fSMarcin Wojtas MVNETA_BM_SHORT, pp->id, 1145dc35a10fSMarcin Wojtas MVNETA_BM_SHORT_PKT_SIZE); 1146dc35a10fSMarcin Wojtas if (!pp->pool_short) { 1147dc35a10fSMarcin Wojtas netdev_info(pp->dev, "fail to obtain short pool for port\n"); 1148dc35a10fSMarcin Wojtas mvneta_bm_pool_destroy(pp->bm_priv, pp->pool_long, 1 << pp->id); 1149dc35a10fSMarcin Wojtas return -ENOMEM; 1150dc35a10fSMarcin Wojtas } 1151dc35a10fSMarcin Wojtas 1152dc35a10fSMarcin Wojtas if (short_pool_id != long_pool_id) { 1153dc35a10fSMarcin Wojtas pp->pool_short->port_map |= 1 << pp->id; 1154dc35a10fSMarcin Wojtas mvneta_bm_pool_bufsize_set(pp, pp->pool_short->buf_size, 1155dc35a10fSMarcin Wojtas pp->pool_short->id); 1156dc35a10fSMarcin Wojtas } 1157dc35a10fSMarcin Wojtas 1158dc35a10fSMarcin Wojtas return 0; 1159dc35a10fSMarcin Wojtas } 1160dc35a10fSMarcin Wojtas 1161dc35a10fSMarcin Wojtas /* Update settings of a pool for bigger packets */ 1162dc35a10fSMarcin Wojtas static void mvneta_bm_update_mtu(struct mvneta_port *pp, int mtu) 1163dc35a10fSMarcin Wojtas { 1164dc35a10fSMarcin Wojtas struct mvneta_bm_pool *bm_pool = pp->pool_long; 1165baa11ebcSGregory CLEMENT struct hwbm_pool *hwbm_pool = &bm_pool->hwbm_pool; 1166dc35a10fSMarcin Wojtas int num; 1167dc35a10fSMarcin Wojtas 1168dc35a10fSMarcin Wojtas /* Release all buffers from long pool */ 1169dc35a10fSMarcin Wojtas mvneta_bm_bufs_free(pp->bm_priv, bm_pool, 1 << pp->id); 1170baa11ebcSGregory CLEMENT if (hwbm_pool->buf_num) { 1171dc35a10fSMarcin Wojtas WARN(1, "cannot free all buffers in pool %d\n", 1172dc35a10fSMarcin Wojtas bm_pool->id); 1173dc35a10fSMarcin Wojtas goto bm_mtu_err; 1174dc35a10fSMarcin Wojtas } 1175dc35a10fSMarcin Wojtas 1176dc35a10fSMarcin Wojtas bm_pool->pkt_size = MVNETA_RX_PKT_SIZE(mtu); 1177dc35a10fSMarcin Wojtas bm_pool->buf_size = MVNETA_RX_BUF_SIZE(bm_pool->pkt_size); 1178baa11ebcSGregory CLEMENT hwbm_pool->frag_size = SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) + 1179dc35a10fSMarcin Wojtas SKB_DATA_ALIGN(MVNETA_RX_BUF_SIZE(bm_pool->pkt_size)); 1180dc35a10fSMarcin Wojtas 1181dc35a10fSMarcin Wojtas /* Fill entire long pool */ 11826dcdd884SSebastian Andrzej Siewior num = hwbm_pool_add(hwbm_pool, hwbm_pool->size); 1183baa11ebcSGregory CLEMENT if (num != hwbm_pool->size) { 1184dc35a10fSMarcin Wojtas WARN(1, "pool %d: %d of %d allocated\n", 1185baa11ebcSGregory CLEMENT bm_pool->id, num, hwbm_pool->size); 1186dc35a10fSMarcin Wojtas goto bm_mtu_err; 1187dc35a10fSMarcin Wojtas } 1188dc35a10fSMarcin Wojtas mvneta_bm_pool_bufsize_set(pp, bm_pool->buf_size, bm_pool->id); 1189dc35a10fSMarcin Wojtas 1190dc35a10fSMarcin Wojtas return; 1191dc35a10fSMarcin Wojtas 1192dc35a10fSMarcin Wojtas bm_mtu_err: 1193dc35a10fSMarcin Wojtas mvneta_bm_pool_destroy(pp->bm_priv, pp->pool_long, 1 << pp->id); 1194dc35a10fSMarcin Wojtas mvneta_bm_pool_destroy(pp->bm_priv, pp->pool_short, 1 << pp->id); 1195dc35a10fSMarcin Wojtas 1196dc35a10fSMarcin Wojtas pp->bm_priv = NULL; 119744efc78dSLorenzo Bianconi pp->rx_offset_correction = MVNETA_SKB_HEADROOM; 1198dc35a10fSMarcin Wojtas mvreg_write(pp, MVNETA_ACC_MODE, MVNETA_ACC_MODE_EXT1); 1199dc35a10fSMarcin Wojtas netdev_info(pp->dev, "fail to update MTU, fall back to software BM\n"); 1200dc35a10fSMarcin Wojtas } 1201dc35a10fSMarcin Wojtas 1202c5aff182SThomas Petazzoni /* Start the Ethernet port RX and TX activity */ 1203c5aff182SThomas Petazzoni static void mvneta_port_up(struct mvneta_port *pp) 1204c5aff182SThomas Petazzoni { 1205c5aff182SThomas Petazzoni int queue; 1206c5aff182SThomas Petazzoni u32 q_map; 1207c5aff182SThomas Petazzoni 1208c5aff182SThomas Petazzoni /* Enable all initialized TXs. */ 1209c5aff182SThomas Petazzoni q_map = 0; 1210c5aff182SThomas Petazzoni for (queue = 0; queue < txq_number; queue++) { 1211c5aff182SThomas Petazzoni struct mvneta_tx_queue *txq = &pp->txqs[queue]; 1212f95936ccSMarkus Elfring if (txq->descs) 1213c5aff182SThomas Petazzoni q_map |= (1 << queue); 1214c5aff182SThomas Petazzoni } 1215c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_TXQ_CMD, q_map); 1216c5aff182SThomas Petazzoni 1217e81b5e01SYelena Krivosheev q_map = 0; 1218c5aff182SThomas Petazzoni /* Enable all initialized RXQs. */ 12192dcf75e2SGregory CLEMENT for (queue = 0; queue < rxq_number; queue++) { 12202dcf75e2SGregory CLEMENT struct mvneta_rx_queue *rxq = &pp->rxqs[queue]; 12212dcf75e2SGregory CLEMENT 1222f95936ccSMarkus Elfring if (rxq->descs) 12232dcf75e2SGregory CLEMENT q_map |= (1 << queue); 12242dcf75e2SGregory CLEMENT } 12252dcf75e2SGregory CLEMENT mvreg_write(pp, MVNETA_RXQ_CMD, q_map); 1226c5aff182SThomas Petazzoni } 1227c5aff182SThomas Petazzoni 1228c5aff182SThomas Petazzoni /* Stop the Ethernet port activity */ 1229c5aff182SThomas Petazzoni static void mvneta_port_down(struct mvneta_port *pp) 1230c5aff182SThomas Petazzoni { 1231c5aff182SThomas Petazzoni u32 val; 1232c5aff182SThomas Petazzoni int count; 1233c5aff182SThomas Petazzoni 1234c5aff182SThomas Petazzoni /* Stop Rx port activity. Check port Rx activity. */ 1235c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_RXQ_CMD) & MVNETA_RXQ_ENABLE_MASK; 1236c5aff182SThomas Petazzoni 1237c5aff182SThomas Petazzoni /* Issue stop command for active channels only */ 1238c5aff182SThomas Petazzoni if (val != 0) 1239c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_RXQ_CMD, 1240c5aff182SThomas Petazzoni val << MVNETA_RXQ_DISABLE_SHIFT); 1241c5aff182SThomas Petazzoni 1242c5aff182SThomas Petazzoni /* Wait for all Rx activity to terminate. */ 1243c5aff182SThomas Petazzoni count = 0; 1244c5aff182SThomas Petazzoni do { 1245c5aff182SThomas Petazzoni if (count++ >= MVNETA_RX_DISABLE_TIMEOUT_MSEC) { 1246c5aff182SThomas Petazzoni netdev_warn(pp->dev, 12470838abb3SDmitri Epshtein "TIMEOUT for RX stopped ! rx_queue_cmd: 0x%08x\n", 1248c5aff182SThomas Petazzoni val); 1249c5aff182SThomas Petazzoni break; 1250c5aff182SThomas Petazzoni } 1251c5aff182SThomas Petazzoni mdelay(1); 1252c5aff182SThomas Petazzoni 1253c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_RXQ_CMD); 1254a3703fb3SDmitri Epshtein } while (val & MVNETA_RXQ_ENABLE_MASK); 1255c5aff182SThomas Petazzoni 1256c5aff182SThomas Petazzoni /* Stop Tx port activity. Check port Tx activity. Issue stop 12576a20c175SThomas Petazzoni * command for active channels only 12586a20c175SThomas Petazzoni */ 1259c5aff182SThomas Petazzoni val = (mvreg_read(pp, MVNETA_TXQ_CMD)) & MVNETA_TXQ_ENABLE_MASK; 1260c5aff182SThomas Petazzoni 1261c5aff182SThomas Petazzoni if (val != 0) 1262c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_TXQ_CMD, 1263c5aff182SThomas Petazzoni (val << MVNETA_TXQ_DISABLE_SHIFT)); 1264c5aff182SThomas Petazzoni 1265c5aff182SThomas Petazzoni /* Wait for all Tx activity to terminate. */ 1266c5aff182SThomas Petazzoni count = 0; 1267c5aff182SThomas Petazzoni do { 1268c5aff182SThomas Petazzoni if (count++ >= MVNETA_TX_DISABLE_TIMEOUT_MSEC) { 1269c5aff182SThomas Petazzoni netdev_warn(pp->dev, 1270c5aff182SThomas Petazzoni "TIMEOUT for TX stopped status=0x%08x\n", 1271c5aff182SThomas Petazzoni val); 1272c5aff182SThomas Petazzoni break; 1273c5aff182SThomas Petazzoni } 1274c5aff182SThomas Petazzoni mdelay(1); 1275c5aff182SThomas Petazzoni 1276c5aff182SThomas Petazzoni /* Check TX Command reg that all Txqs are stopped */ 1277c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_TXQ_CMD); 1278c5aff182SThomas Petazzoni 1279a3703fb3SDmitri Epshtein } while (val & MVNETA_TXQ_ENABLE_MASK); 1280c5aff182SThomas Petazzoni 1281c5aff182SThomas Petazzoni /* Double check to verify that TX FIFO is empty */ 1282c5aff182SThomas Petazzoni count = 0; 1283c5aff182SThomas Petazzoni do { 1284c5aff182SThomas Petazzoni if (count++ >= MVNETA_TX_FIFO_EMPTY_TIMEOUT) { 1285c5aff182SThomas Petazzoni netdev_warn(pp->dev, 12860838abb3SDmitri Epshtein "TX FIFO empty timeout status=0x%08x\n", 1287c5aff182SThomas Petazzoni val); 1288c5aff182SThomas Petazzoni break; 1289c5aff182SThomas Petazzoni } 1290c5aff182SThomas Petazzoni mdelay(1); 1291c5aff182SThomas Petazzoni 1292c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_PORT_STATUS); 1293c5aff182SThomas Petazzoni } while (!(val & MVNETA_TX_FIFO_EMPTY) && 1294c5aff182SThomas Petazzoni (val & MVNETA_TX_IN_PRGRS)); 1295c5aff182SThomas Petazzoni 1296c5aff182SThomas Petazzoni udelay(200); 1297c5aff182SThomas Petazzoni } 1298c5aff182SThomas Petazzoni 1299c5aff182SThomas Petazzoni /* Enable the port by setting the port enable bit of the MAC control register */ 1300c5aff182SThomas Petazzoni static void mvneta_port_enable(struct mvneta_port *pp) 1301c5aff182SThomas Petazzoni { 1302c5aff182SThomas Petazzoni u32 val; 1303c5aff182SThomas Petazzoni 1304c5aff182SThomas Petazzoni /* Enable port */ 1305c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_GMAC_CTRL_0); 1306c5aff182SThomas Petazzoni val |= MVNETA_GMAC0_PORT_ENABLE; 1307c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_GMAC_CTRL_0, val); 1308c5aff182SThomas Petazzoni } 1309c5aff182SThomas Petazzoni 1310c5aff182SThomas Petazzoni /* Disable the port and wait for about 200 usec before retuning */ 1311c5aff182SThomas Petazzoni static void mvneta_port_disable(struct mvneta_port *pp) 1312c5aff182SThomas Petazzoni { 1313c5aff182SThomas Petazzoni u32 val; 1314c5aff182SThomas Petazzoni 1315c5aff182SThomas Petazzoni /* Reset the Enable bit in the Serial Control Register */ 1316c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_GMAC_CTRL_0); 1317c5aff182SThomas Petazzoni val &= ~MVNETA_GMAC0_PORT_ENABLE; 1318c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_GMAC_CTRL_0, val); 1319c5aff182SThomas Petazzoni 1320c5aff182SThomas Petazzoni udelay(200); 1321c5aff182SThomas Petazzoni } 1322c5aff182SThomas Petazzoni 1323c5aff182SThomas Petazzoni /* Multicast tables methods */ 1324c5aff182SThomas Petazzoni 1325c5aff182SThomas Petazzoni /* Set all entries in Unicast MAC Table; queue==-1 means reject all */ 1326c5aff182SThomas Petazzoni static void mvneta_set_ucast_table(struct mvneta_port *pp, int queue) 1327c5aff182SThomas Petazzoni { 1328c5aff182SThomas Petazzoni int offset; 1329c5aff182SThomas Petazzoni u32 val; 1330c5aff182SThomas Petazzoni 1331c5aff182SThomas Petazzoni if (queue == -1) { 1332c5aff182SThomas Petazzoni val = 0; 1333c5aff182SThomas Petazzoni } else { 1334c5aff182SThomas Petazzoni val = 0x1 | (queue << 1); 1335c5aff182SThomas Petazzoni val |= (val << 24) | (val << 16) | (val << 8); 1336c5aff182SThomas Petazzoni } 1337c5aff182SThomas Petazzoni 1338c5aff182SThomas Petazzoni for (offset = 0; offset <= 0xc; offset += 4) 1339c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_DA_FILT_UCAST_BASE + offset, val); 1340c5aff182SThomas Petazzoni } 1341c5aff182SThomas Petazzoni 1342c5aff182SThomas Petazzoni /* Set all entries in Special Multicast MAC Table; queue==-1 means reject all */ 1343c5aff182SThomas Petazzoni static void mvneta_set_special_mcast_table(struct mvneta_port *pp, int queue) 1344c5aff182SThomas Petazzoni { 1345c5aff182SThomas Petazzoni int offset; 1346c5aff182SThomas Petazzoni u32 val; 1347c5aff182SThomas Petazzoni 1348c5aff182SThomas Petazzoni if (queue == -1) { 1349c5aff182SThomas Petazzoni val = 0; 1350c5aff182SThomas Petazzoni } else { 1351c5aff182SThomas Petazzoni val = 0x1 | (queue << 1); 1352c5aff182SThomas Petazzoni val |= (val << 24) | (val << 16) | (val << 8); 1353c5aff182SThomas Petazzoni } 1354c5aff182SThomas Petazzoni 1355c5aff182SThomas Petazzoni for (offset = 0; offset <= 0xfc; offset += 4) 1356c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_DA_FILT_SPEC_MCAST + offset, val); 1357c5aff182SThomas Petazzoni 1358c5aff182SThomas Petazzoni } 1359c5aff182SThomas Petazzoni 1360c5aff182SThomas Petazzoni /* Set all entries in Other Multicast MAC Table. queue==-1 means reject all */ 1361c5aff182SThomas Petazzoni static void mvneta_set_other_mcast_table(struct mvneta_port *pp, int queue) 1362c5aff182SThomas Petazzoni { 1363c5aff182SThomas Petazzoni int offset; 1364c5aff182SThomas Petazzoni u32 val; 1365c5aff182SThomas Petazzoni 1366c5aff182SThomas Petazzoni if (queue == -1) { 1367c5aff182SThomas Petazzoni memset(pp->mcast_count, 0, sizeof(pp->mcast_count)); 1368c5aff182SThomas Petazzoni val = 0; 1369c5aff182SThomas Petazzoni } else { 1370c5aff182SThomas Petazzoni memset(pp->mcast_count, 1, sizeof(pp->mcast_count)); 1371c5aff182SThomas Petazzoni val = 0x1 | (queue << 1); 1372c5aff182SThomas Petazzoni val |= (val << 24) | (val << 16) | (val << 8); 1373c5aff182SThomas Petazzoni } 1374c5aff182SThomas Petazzoni 1375c5aff182SThomas Petazzoni for (offset = 0; offset <= 0xfc; offset += 4) 1376c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_DA_FILT_OTH_MCAST + offset, val); 1377c5aff182SThomas Petazzoni } 1378c5aff182SThomas Petazzoni 1379db488c10SGregory CLEMENT static void mvneta_percpu_unmask_interrupt(void *arg) 1380db488c10SGregory CLEMENT { 1381db488c10SGregory CLEMENT struct mvneta_port *pp = arg; 1382db488c10SGregory CLEMENT 1383db488c10SGregory CLEMENT /* All the queue are unmasked, but actually only the ones 1384db488c10SGregory CLEMENT * mapped to this CPU will be unmasked 1385db488c10SGregory CLEMENT */ 1386db488c10SGregory CLEMENT mvreg_write(pp, MVNETA_INTR_NEW_MASK, 1387db488c10SGregory CLEMENT MVNETA_RX_INTR_MASK_ALL | 1388db488c10SGregory CLEMENT MVNETA_TX_INTR_MASK_ALL | 1389db488c10SGregory CLEMENT MVNETA_MISCINTR_INTR_MASK); 1390db488c10SGregory CLEMENT } 1391db488c10SGregory CLEMENT 1392db488c10SGregory CLEMENT static void mvneta_percpu_mask_interrupt(void *arg) 1393db488c10SGregory CLEMENT { 1394db488c10SGregory CLEMENT struct mvneta_port *pp = arg; 1395db488c10SGregory CLEMENT 1396db488c10SGregory CLEMENT /* All the queue are masked, but actually only the ones 1397db488c10SGregory CLEMENT * mapped to this CPU will be masked 1398db488c10SGregory CLEMENT */ 1399db488c10SGregory CLEMENT mvreg_write(pp, MVNETA_INTR_NEW_MASK, 0); 1400db488c10SGregory CLEMENT mvreg_write(pp, MVNETA_INTR_OLD_MASK, 0); 1401db488c10SGregory CLEMENT mvreg_write(pp, MVNETA_INTR_MISC_MASK, 0); 1402db488c10SGregory CLEMENT } 1403db488c10SGregory CLEMENT 1404db488c10SGregory CLEMENT static void mvneta_percpu_clear_intr_cause(void *arg) 1405db488c10SGregory CLEMENT { 1406db488c10SGregory CLEMENT struct mvneta_port *pp = arg; 1407db488c10SGregory CLEMENT 1408db488c10SGregory CLEMENT /* All the queue are cleared, but actually only the ones 1409db488c10SGregory CLEMENT * mapped to this CPU will be cleared 1410db488c10SGregory CLEMENT */ 1411db488c10SGregory CLEMENT mvreg_write(pp, MVNETA_INTR_NEW_CAUSE, 0); 1412db488c10SGregory CLEMENT mvreg_write(pp, MVNETA_INTR_MISC_CAUSE, 0); 1413db488c10SGregory CLEMENT mvreg_write(pp, MVNETA_INTR_OLD_CAUSE, 0); 1414db488c10SGregory CLEMENT } 1415db488c10SGregory CLEMENT 1416c5aff182SThomas Petazzoni /* This method sets defaults to the NETA port: 1417c5aff182SThomas Petazzoni * Clears interrupt Cause and Mask registers. 1418c5aff182SThomas Petazzoni * Clears all MAC tables. 1419c5aff182SThomas Petazzoni * Sets defaults to all registers. 1420c5aff182SThomas Petazzoni * Resets RX and TX descriptor rings. 1421c5aff182SThomas Petazzoni * Resets PHY. 1422c5aff182SThomas Petazzoni * This method can be called after mvneta_port_down() to return the port 1423c5aff182SThomas Petazzoni * settings to defaults. 1424c5aff182SThomas Petazzoni */ 1425c5aff182SThomas Petazzoni static void mvneta_defaults_set(struct mvneta_port *pp) 1426c5aff182SThomas Petazzoni { 1427c5aff182SThomas Petazzoni int cpu; 1428c5aff182SThomas Petazzoni int queue; 1429c5aff182SThomas Petazzoni u32 val; 14302dcf75e2SGregory CLEMENT int max_cpu = num_present_cpus(); 1431c5aff182SThomas Petazzoni 1432c5aff182SThomas Petazzoni /* Clear all Cause registers */ 1433db488c10SGregory CLEMENT on_each_cpu(mvneta_percpu_clear_intr_cause, pp, true); 1434c5aff182SThomas Petazzoni 1435c5aff182SThomas Petazzoni /* Mask all interrupts */ 1436db488c10SGregory CLEMENT on_each_cpu(mvneta_percpu_mask_interrupt, pp, true); 1437c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_INTR_ENABLE, 0); 1438c5aff182SThomas Petazzoni 1439c5aff182SThomas Petazzoni /* Enable MBUS Retry bit16 */ 1440c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_MBUS_RETRY, 0x20); 1441c5aff182SThomas Petazzoni 144250bf8cb6SGregory CLEMENT /* Set CPU queue access map. CPUs are assigned to the RX and 144350bf8cb6SGregory CLEMENT * TX queues modulo their number. If there is only one TX 144450bf8cb6SGregory CLEMENT * queue then it is assigned to the CPU associated to the 144550bf8cb6SGregory CLEMENT * default RX queue. 14466a20c175SThomas Petazzoni */ 14472dcf75e2SGregory CLEMENT for_each_present_cpu(cpu) { 14482dcf75e2SGregory CLEMENT int rxq_map = 0, txq_map = 0; 144950bf8cb6SGregory CLEMENT int rxq, txq; 14502636ac3cSMarcin Wojtas if (!pp->neta_armada3700) { 14512dcf75e2SGregory CLEMENT for (rxq = 0; rxq < rxq_number; rxq++) 14522dcf75e2SGregory CLEMENT if ((rxq % max_cpu) == cpu) 14532dcf75e2SGregory CLEMENT rxq_map |= MVNETA_CPU_RXQ_ACCESS(rxq); 14542dcf75e2SGregory CLEMENT 145550bf8cb6SGregory CLEMENT for (txq = 0; txq < txq_number; txq++) 145650bf8cb6SGregory CLEMENT if ((txq % max_cpu) == cpu) 145750bf8cb6SGregory CLEMENT txq_map |= MVNETA_CPU_TXQ_ACCESS(txq); 145850bf8cb6SGregory CLEMENT 145950bf8cb6SGregory CLEMENT /* With only one TX queue we configure a special case 146050bf8cb6SGregory CLEMENT * which will allow to get all the irq on a single 146150bf8cb6SGregory CLEMENT * CPU 146250bf8cb6SGregory CLEMENT */ 146350bf8cb6SGregory CLEMENT if (txq_number == 1) 146450bf8cb6SGregory CLEMENT txq_map = (cpu == pp->rxq_def) ? 146550bf8cb6SGregory CLEMENT MVNETA_CPU_TXQ_ACCESS(1) : 0; 14662dcf75e2SGregory CLEMENT 14672636ac3cSMarcin Wojtas } else { 14682636ac3cSMarcin Wojtas txq_map = MVNETA_CPU_TXQ_ACCESS_ALL_MASK; 14692636ac3cSMarcin Wojtas rxq_map = MVNETA_CPU_RXQ_ACCESS_ALL_MASK; 14702636ac3cSMarcin Wojtas } 14712636ac3cSMarcin Wojtas 14722dcf75e2SGregory CLEMENT mvreg_write(pp, MVNETA_CPU_MAP(cpu), rxq_map | txq_map); 14732dcf75e2SGregory CLEMENT } 1474c5aff182SThomas Petazzoni 1475c5aff182SThomas Petazzoni /* Reset RX and TX DMAs */ 1476c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_PORT_RX_RESET, MVNETA_PORT_RX_DMA_RESET); 1477c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_PORT_TX_RESET, MVNETA_PORT_TX_DMA_RESET); 1478c5aff182SThomas Petazzoni 1479c5aff182SThomas Petazzoni /* Disable Legacy WRR, Disable EJP, Release from reset */ 1480c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_TXQ_CMD_1, 0); 1481c5aff182SThomas Petazzoni for (queue = 0; queue < txq_number; queue++) { 1482c5aff182SThomas Petazzoni mvreg_write(pp, MVETH_TXQ_TOKEN_COUNT_REG(queue), 0); 1483c5aff182SThomas Petazzoni mvreg_write(pp, MVETH_TXQ_TOKEN_CFG_REG(queue), 0); 1484c5aff182SThomas Petazzoni } 1485c5aff182SThomas Petazzoni 1486c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_PORT_TX_RESET, 0); 1487c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_PORT_RX_RESET, 0); 1488c5aff182SThomas Petazzoni 1489c5aff182SThomas Petazzoni /* Set Port Acceleration Mode */ 1490dc35a10fSMarcin Wojtas if (pp->bm_priv) 1491dc35a10fSMarcin Wojtas /* HW buffer management + legacy parser */ 1492dc35a10fSMarcin Wojtas val = MVNETA_ACC_MODE_EXT2; 1493dc35a10fSMarcin Wojtas else 1494dc35a10fSMarcin Wojtas /* SW buffer management + legacy parser */ 1495dc35a10fSMarcin Wojtas val = MVNETA_ACC_MODE_EXT1; 1496c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_ACC_MODE, val); 1497c5aff182SThomas Petazzoni 1498dc35a10fSMarcin Wojtas if (pp->bm_priv) 1499dc35a10fSMarcin Wojtas mvreg_write(pp, MVNETA_BM_ADDRESS, pp->bm_priv->bppi_phys_addr); 1500dc35a10fSMarcin Wojtas 1501c5aff182SThomas Petazzoni /* Update val of portCfg register accordingly with all RxQueue types */ 150290b74c01SGregory CLEMENT val = MVNETA_PORT_CONFIG_DEFL_VALUE(pp->rxq_def); 1503c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_PORT_CONFIG, val); 1504c5aff182SThomas Petazzoni 1505c5aff182SThomas Petazzoni val = 0; 1506c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_PORT_CONFIG_EXTEND, val); 1507c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_RX_MIN_FRAME_SIZE, 64); 1508c5aff182SThomas Petazzoni 1509c5aff182SThomas Petazzoni /* Build PORT_SDMA_CONFIG_REG */ 1510c5aff182SThomas Petazzoni val = 0; 1511c5aff182SThomas Petazzoni 1512c5aff182SThomas Petazzoni /* Default burst size */ 1513c5aff182SThomas Petazzoni val |= MVNETA_TX_BRST_SZ_MASK(MVNETA_SDMA_BRST_SIZE_16); 1514c5aff182SThomas Petazzoni val |= MVNETA_RX_BRST_SZ_MASK(MVNETA_SDMA_BRST_SIZE_16); 15159ad8fef6SThomas Petazzoni val |= MVNETA_RX_NO_DATA_SWAP | MVNETA_TX_NO_DATA_SWAP; 1516c5aff182SThomas Petazzoni 15179ad8fef6SThomas Petazzoni #if defined(__BIG_ENDIAN) 15189ad8fef6SThomas Petazzoni val |= MVNETA_DESC_SWAP; 15199ad8fef6SThomas Petazzoni #endif 1520c5aff182SThomas Petazzoni 1521c5aff182SThomas Petazzoni /* Assign port SDMA configuration */ 1522c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_SDMA_CONFIG, val); 1523c5aff182SThomas Petazzoni 152471408602SThomas Petazzoni /* Disable PHY polling in hardware, since we're using the 152571408602SThomas Petazzoni * kernel phylib to do this. 152671408602SThomas Petazzoni */ 152771408602SThomas Petazzoni val = mvreg_read(pp, MVNETA_UNIT_CONTROL); 152871408602SThomas Petazzoni val &= ~MVNETA_PHY_POLLING_ENABLE; 152971408602SThomas Petazzoni mvreg_write(pp, MVNETA_UNIT_CONTROL, val); 153071408602SThomas Petazzoni 1531c5aff182SThomas Petazzoni mvneta_set_ucast_table(pp, -1); 1532c5aff182SThomas Petazzoni mvneta_set_special_mcast_table(pp, -1); 1533c5aff182SThomas Petazzoni mvneta_set_other_mcast_table(pp, -1); 1534c5aff182SThomas Petazzoni 1535c5aff182SThomas Petazzoni /* Set port interrupt enable register - default enable all */ 1536c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_INTR_ENABLE, 1537c5aff182SThomas Petazzoni (MVNETA_RXQ_INTR_ENABLE_ALL_MASK 1538c5aff182SThomas Petazzoni | MVNETA_TXQ_INTR_ENABLE_ALL_MASK)); 1539e483911fSAndrew Lunn 1540e483911fSAndrew Lunn mvneta_mib_counters_clear(pp); 1541c5aff182SThomas Petazzoni } 1542c5aff182SThomas Petazzoni 1543c5aff182SThomas Petazzoni /* Set max sizes for tx queues */ 1544c5aff182SThomas Petazzoni static void mvneta_txq_max_tx_size_set(struct mvneta_port *pp, int max_tx_size) 1545c5aff182SThomas Petazzoni 1546c5aff182SThomas Petazzoni { 1547c5aff182SThomas Petazzoni u32 val, size, mtu; 1548c5aff182SThomas Petazzoni int queue; 1549c5aff182SThomas Petazzoni 1550c5aff182SThomas Petazzoni mtu = max_tx_size * 8; 1551c5aff182SThomas Petazzoni if (mtu > MVNETA_TX_MTU_MAX) 1552c5aff182SThomas Petazzoni mtu = MVNETA_TX_MTU_MAX; 1553c5aff182SThomas Petazzoni 1554c5aff182SThomas Petazzoni /* Set MTU */ 1555c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_TX_MTU); 1556c5aff182SThomas Petazzoni val &= ~MVNETA_TX_MTU_MAX; 1557c5aff182SThomas Petazzoni val |= mtu; 1558c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_TX_MTU, val); 1559c5aff182SThomas Petazzoni 1560c5aff182SThomas Petazzoni /* TX token size and all TXQs token size must be larger that MTU */ 1561c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_TX_TOKEN_SIZE); 1562c5aff182SThomas Petazzoni 1563c5aff182SThomas Petazzoni size = val & MVNETA_TX_TOKEN_SIZE_MAX; 1564c5aff182SThomas Petazzoni if (size < mtu) { 1565c5aff182SThomas Petazzoni size = mtu; 1566c5aff182SThomas Petazzoni val &= ~MVNETA_TX_TOKEN_SIZE_MAX; 1567c5aff182SThomas Petazzoni val |= size; 1568c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_TX_TOKEN_SIZE, val); 1569c5aff182SThomas Petazzoni } 1570c5aff182SThomas Petazzoni for (queue = 0; queue < txq_number; queue++) { 1571c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_TXQ_TOKEN_SIZE_REG(queue)); 1572c5aff182SThomas Petazzoni 1573c5aff182SThomas Petazzoni size = val & MVNETA_TXQ_TOKEN_SIZE_MAX; 1574c5aff182SThomas Petazzoni if (size < mtu) { 1575c5aff182SThomas Petazzoni size = mtu; 1576c5aff182SThomas Petazzoni val &= ~MVNETA_TXQ_TOKEN_SIZE_MAX; 1577c5aff182SThomas Petazzoni val |= size; 1578c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_TXQ_TOKEN_SIZE_REG(queue), val); 1579c5aff182SThomas Petazzoni } 1580c5aff182SThomas Petazzoni } 1581c5aff182SThomas Petazzoni } 1582c5aff182SThomas Petazzoni 1583c5aff182SThomas Petazzoni /* Set unicast address */ 1584c5aff182SThomas Petazzoni static void mvneta_set_ucast_addr(struct mvneta_port *pp, u8 last_nibble, 1585c5aff182SThomas Petazzoni int queue) 1586c5aff182SThomas Petazzoni { 1587c5aff182SThomas Petazzoni unsigned int unicast_reg; 1588c5aff182SThomas Petazzoni unsigned int tbl_offset; 1589c5aff182SThomas Petazzoni unsigned int reg_offset; 1590c5aff182SThomas Petazzoni 1591c5aff182SThomas Petazzoni /* Locate the Unicast table entry */ 1592c5aff182SThomas Petazzoni last_nibble = (0xf & last_nibble); 1593c5aff182SThomas Petazzoni 1594c5aff182SThomas Petazzoni /* offset from unicast tbl base */ 1595c5aff182SThomas Petazzoni tbl_offset = (last_nibble / 4) * 4; 1596c5aff182SThomas Petazzoni 1597c5aff182SThomas Petazzoni /* offset within the above reg */ 1598c5aff182SThomas Petazzoni reg_offset = last_nibble % 4; 1599c5aff182SThomas Petazzoni 1600c5aff182SThomas Petazzoni unicast_reg = mvreg_read(pp, (MVNETA_DA_FILT_UCAST_BASE + tbl_offset)); 1601c5aff182SThomas Petazzoni 1602c5aff182SThomas Petazzoni if (queue == -1) { 1603c5aff182SThomas Petazzoni /* Clear accepts frame bit at specified unicast DA tbl entry */ 1604c5aff182SThomas Petazzoni unicast_reg &= ~(0xff << (8 * reg_offset)); 1605c5aff182SThomas Petazzoni } else { 1606c5aff182SThomas Petazzoni unicast_reg &= ~(0xff << (8 * reg_offset)); 1607c5aff182SThomas Petazzoni unicast_reg |= ((0x01 | (queue << 1)) << (8 * reg_offset)); 1608c5aff182SThomas Petazzoni } 1609c5aff182SThomas Petazzoni 1610c5aff182SThomas Petazzoni mvreg_write(pp, (MVNETA_DA_FILT_UCAST_BASE + tbl_offset), unicast_reg); 1611c5aff182SThomas Petazzoni } 1612c5aff182SThomas Petazzoni 1613c5aff182SThomas Petazzoni /* Set mac address */ 1614c5aff182SThomas Petazzoni static void mvneta_mac_addr_set(struct mvneta_port *pp, unsigned char *addr, 1615c5aff182SThomas Petazzoni int queue) 1616c5aff182SThomas Petazzoni { 1617c5aff182SThomas Petazzoni unsigned int mac_h; 1618c5aff182SThomas Petazzoni unsigned int mac_l; 1619c5aff182SThomas Petazzoni 1620c5aff182SThomas Petazzoni if (queue != -1) { 1621c5aff182SThomas Petazzoni mac_l = (addr[4] << 8) | (addr[5]); 1622c5aff182SThomas Petazzoni mac_h = (addr[0] << 24) | (addr[1] << 16) | 1623c5aff182SThomas Petazzoni (addr[2] << 8) | (addr[3] << 0); 1624c5aff182SThomas Petazzoni 1625c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_MAC_ADDR_LOW, mac_l); 1626c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_MAC_ADDR_HIGH, mac_h); 1627c5aff182SThomas Petazzoni } 1628c5aff182SThomas Petazzoni 1629c5aff182SThomas Petazzoni /* Accept frames of this address */ 1630c5aff182SThomas Petazzoni mvneta_set_ucast_addr(pp, addr[5], queue); 1631c5aff182SThomas Petazzoni } 1632c5aff182SThomas Petazzoni 16336a20c175SThomas Petazzoni /* Set the number of packets that will be received before RX interrupt 16346a20c175SThomas Petazzoni * will be generated by HW. 1635c5aff182SThomas Petazzoni */ 1636c5aff182SThomas Petazzoni static void mvneta_rx_pkts_coal_set(struct mvneta_port *pp, 1637c5aff182SThomas Petazzoni struct mvneta_rx_queue *rxq, u32 value) 1638c5aff182SThomas Petazzoni { 1639c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_RXQ_THRESHOLD_REG(rxq->id), 1640c5aff182SThomas Petazzoni value | MVNETA_RXQ_NON_OCCUPIED(0)); 1641c5aff182SThomas Petazzoni } 1642c5aff182SThomas Petazzoni 16436a20c175SThomas Petazzoni /* Set the time delay in usec before RX interrupt will be generated by 16446a20c175SThomas Petazzoni * HW. 1645c5aff182SThomas Petazzoni */ 1646c5aff182SThomas Petazzoni static void mvneta_rx_time_coal_set(struct mvneta_port *pp, 1647c5aff182SThomas Petazzoni struct mvneta_rx_queue *rxq, u32 value) 1648c5aff182SThomas Petazzoni { 1649189dd626SThomas Petazzoni u32 val; 1650189dd626SThomas Petazzoni unsigned long clk_rate; 1651189dd626SThomas Petazzoni 1652189dd626SThomas Petazzoni clk_rate = clk_get_rate(pp->clk); 1653189dd626SThomas Petazzoni val = (clk_rate / 1000000) * value; 1654c5aff182SThomas Petazzoni 1655c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_RXQ_TIME_COAL_REG(rxq->id), val); 1656c5aff182SThomas Petazzoni } 1657c5aff182SThomas Petazzoni 1658c5aff182SThomas Petazzoni /* Set threshold for TX_DONE pkts coalescing */ 1659c5aff182SThomas Petazzoni static void mvneta_tx_done_pkts_coal_set(struct mvneta_port *pp, 1660c5aff182SThomas Petazzoni struct mvneta_tx_queue *txq, u32 value) 1661c5aff182SThomas Petazzoni { 1662c5aff182SThomas Petazzoni u32 val; 1663c5aff182SThomas Petazzoni 1664c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_TXQ_SIZE_REG(txq->id)); 1665c5aff182SThomas Petazzoni 1666c5aff182SThomas Petazzoni val &= ~MVNETA_TXQ_SENT_THRESH_ALL_MASK; 1667c5aff182SThomas Petazzoni val |= MVNETA_TXQ_SENT_THRESH_MASK(value); 1668c5aff182SThomas Petazzoni 1669c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_TXQ_SIZE_REG(txq->id), val); 1670c5aff182SThomas Petazzoni } 1671c5aff182SThomas Petazzoni 1672c5aff182SThomas Petazzoni /* Handle rx descriptor fill by setting buf_cookie and buf_phys_addr */ 1673c5aff182SThomas Petazzoni static void mvneta_rx_desc_fill(struct mvneta_rx_desc *rx_desc, 1674f88bee1cSGregory CLEMENT u32 phys_addr, void *virt_addr, 1675f88bee1cSGregory CLEMENT struct mvneta_rx_queue *rxq) 1676c5aff182SThomas Petazzoni { 1677f88bee1cSGregory CLEMENT int i; 1678f88bee1cSGregory CLEMENT 1679c5aff182SThomas Petazzoni rx_desc->buf_phys_addr = phys_addr; 1680f88bee1cSGregory CLEMENT i = rx_desc - rxq->descs; 1681f88bee1cSGregory CLEMENT rxq->buf_virt_addr[i] = virt_addr; 1682c5aff182SThomas Petazzoni } 1683c5aff182SThomas Petazzoni 1684c5aff182SThomas Petazzoni /* Decrement sent descriptors counter */ 1685c5aff182SThomas Petazzoni static void mvneta_txq_sent_desc_dec(struct mvneta_port *pp, 1686c5aff182SThomas Petazzoni struct mvneta_tx_queue *txq, 1687c5aff182SThomas Petazzoni int sent_desc) 1688c5aff182SThomas Petazzoni { 1689c5aff182SThomas Petazzoni u32 val; 1690c5aff182SThomas Petazzoni 1691c5aff182SThomas Petazzoni /* Only 255 TX descriptors can be updated at once */ 1692c5aff182SThomas Petazzoni while (sent_desc > 0xff) { 1693c5aff182SThomas Petazzoni val = 0xff << MVNETA_TXQ_DEC_SENT_SHIFT; 1694c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val); 1695c5aff182SThomas Petazzoni sent_desc = sent_desc - 0xff; 1696c5aff182SThomas Petazzoni } 1697c5aff182SThomas Petazzoni 1698c5aff182SThomas Petazzoni val = sent_desc << MVNETA_TXQ_DEC_SENT_SHIFT; 1699c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val); 1700c5aff182SThomas Petazzoni } 1701c5aff182SThomas Petazzoni 1702c5aff182SThomas Petazzoni /* Get number of TX descriptors already sent by HW */ 1703c5aff182SThomas Petazzoni static int mvneta_txq_sent_desc_num_get(struct mvneta_port *pp, 1704c5aff182SThomas Petazzoni struct mvneta_tx_queue *txq) 1705c5aff182SThomas Petazzoni { 1706c5aff182SThomas Petazzoni u32 val; 1707c5aff182SThomas Petazzoni int sent_desc; 1708c5aff182SThomas Petazzoni 1709c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_TXQ_STATUS_REG(txq->id)); 1710c5aff182SThomas Petazzoni sent_desc = (val & MVNETA_TXQ_SENT_DESC_MASK) >> 1711c5aff182SThomas Petazzoni MVNETA_TXQ_SENT_DESC_SHIFT; 1712c5aff182SThomas Petazzoni 1713c5aff182SThomas Petazzoni return sent_desc; 1714c5aff182SThomas Petazzoni } 1715c5aff182SThomas Petazzoni 17166a20c175SThomas Petazzoni /* Get number of sent descriptors and decrement counter. 1717c5aff182SThomas Petazzoni * The number of sent descriptors is returned. 1718c5aff182SThomas Petazzoni */ 1719c5aff182SThomas Petazzoni static int mvneta_txq_sent_desc_proc(struct mvneta_port *pp, 1720c5aff182SThomas Petazzoni struct mvneta_tx_queue *txq) 1721c5aff182SThomas Petazzoni { 1722c5aff182SThomas Petazzoni int sent_desc; 1723c5aff182SThomas Petazzoni 1724c5aff182SThomas Petazzoni /* Get number of sent descriptors */ 1725c5aff182SThomas Petazzoni sent_desc = mvneta_txq_sent_desc_num_get(pp, txq); 1726c5aff182SThomas Petazzoni 1727c5aff182SThomas Petazzoni /* Decrement sent descriptors counter */ 1728c5aff182SThomas Petazzoni if (sent_desc) 1729c5aff182SThomas Petazzoni mvneta_txq_sent_desc_dec(pp, txq, sent_desc); 1730c5aff182SThomas Petazzoni 1731c5aff182SThomas Petazzoni return sent_desc; 1732c5aff182SThomas Petazzoni } 1733c5aff182SThomas Petazzoni 1734c5aff182SThomas Petazzoni /* Set TXQ descriptors fields relevant for CSUM calculation */ 1735c5aff182SThomas Petazzoni static u32 mvneta_txq_desc_csum(int l3_offs, int l3_proto, 1736c5aff182SThomas Petazzoni int ip_hdr_len, int l4_proto) 1737c5aff182SThomas Petazzoni { 1738c5aff182SThomas Petazzoni u32 command; 1739c5aff182SThomas Petazzoni 1740c5aff182SThomas Petazzoni /* Fields: L3_offset, IP_hdrlen, L3_type, G_IPv4_chk, 17416a20c175SThomas Petazzoni * G_L4_chk, L4_type; required only for checksum 17426a20c175SThomas Petazzoni * calculation 17436a20c175SThomas Petazzoni */ 1744c5aff182SThomas Petazzoni command = l3_offs << MVNETA_TX_L3_OFF_SHIFT; 1745c5aff182SThomas Petazzoni command |= ip_hdr_len << MVNETA_TX_IP_HLEN_SHIFT; 1746c5aff182SThomas Petazzoni 17470a198587SThomas Fitzsimmons if (l3_proto == htons(ETH_P_IP)) 1748c5aff182SThomas Petazzoni command |= MVNETA_TXD_IP_CSUM; 1749c5aff182SThomas Petazzoni else 1750c5aff182SThomas Petazzoni command |= MVNETA_TX_L3_IP6; 1751c5aff182SThomas Petazzoni 1752c5aff182SThomas Petazzoni if (l4_proto == IPPROTO_TCP) 1753c5aff182SThomas Petazzoni command |= MVNETA_TX_L4_CSUM_FULL; 1754c5aff182SThomas Petazzoni else if (l4_proto == IPPROTO_UDP) 1755c5aff182SThomas Petazzoni command |= MVNETA_TX_L4_UDP | MVNETA_TX_L4_CSUM_FULL; 1756c5aff182SThomas Petazzoni else 1757c5aff182SThomas Petazzoni command |= MVNETA_TX_L4_CSUM_NOT; 1758c5aff182SThomas Petazzoni 1759c5aff182SThomas Petazzoni return command; 1760c5aff182SThomas Petazzoni } 1761c5aff182SThomas Petazzoni 1762c5aff182SThomas Petazzoni 1763c5aff182SThomas Petazzoni /* Display more error info */ 1764c5aff182SThomas Petazzoni static void mvneta_rx_error(struct mvneta_port *pp, 1765c5aff182SThomas Petazzoni struct mvneta_rx_desc *rx_desc) 1766c5aff182SThomas Petazzoni { 1767c35947b8SLorenzo Bianconi struct mvneta_pcpu_stats *stats = this_cpu_ptr(pp->stats); 1768c5aff182SThomas Petazzoni u32 status = rx_desc->status; 1769c5aff182SThomas Petazzoni 1770c35947b8SLorenzo Bianconi /* update per-cpu counter */ 1771c35947b8SLorenzo Bianconi u64_stats_update_begin(&stats->syncp); 1772c35947b8SLorenzo Bianconi stats->rx_errors++; 1773c35947b8SLorenzo Bianconi u64_stats_update_end(&stats->syncp); 1774c35947b8SLorenzo Bianconi 1775c5aff182SThomas Petazzoni switch (status & MVNETA_RXD_ERR_CODE_MASK) { 1776c5aff182SThomas Petazzoni case MVNETA_RXD_ERR_CRC: 1777c5aff182SThomas Petazzoni netdev_err(pp->dev, "bad rx status %08x (crc error), size=%d\n", 1778c5aff182SThomas Petazzoni status, rx_desc->data_size); 1779c5aff182SThomas Petazzoni break; 1780c5aff182SThomas Petazzoni case MVNETA_RXD_ERR_OVERRUN: 1781c5aff182SThomas Petazzoni netdev_err(pp->dev, "bad rx status %08x (overrun error), size=%d\n", 1782c5aff182SThomas Petazzoni status, rx_desc->data_size); 1783c5aff182SThomas Petazzoni break; 1784c5aff182SThomas Petazzoni case MVNETA_RXD_ERR_LEN: 1785c5aff182SThomas Petazzoni netdev_err(pp->dev, "bad rx status %08x (max frame length error), size=%d\n", 1786c5aff182SThomas Petazzoni status, rx_desc->data_size); 1787c5aff182SThomas Petazzoni break; 1788c5aff182SThomas Petazzoni case MVNETA_RXD_ERR_RESOURCE: 1789c5aff182SThomas Petazzoni netdev_err(pp->dev, "bad rx status %08x (resource error), size=%d\n", 1790c5aff182SThomas Petazzoni status, rx_desc->data_size); 1791c5aff182SThomas Petazzoni break; 1792c5aff182SThomas Petazzoni } 1793c5aff182SThomas Petazzoni } 1794c5aff182SThomas Petazzoni 17955428213cSwilly tarreau /* Handle RX checksum offload based on the descriptor's status */ 17965428213cSwilly tarreau static void mvneta_rx_csum(struct mvneta_port *pp, u32 status, 1797c5aff182SThomas Petazzoni struct sk_buff *skb) 1798c5aff182SThomas Petazzoni { 1799f945cec8SYelena Krivosheev if ((pp->dev->features & NETIF_F_RXCSUM) && 1800f945cec8SYelena Krivosheev (status & MVNETA_RXD_L3_IP4) && 18015428213cSwilly tarreau (status & MVNETA_RXD_L4_CSUM_OK)) { 1802c5aff182SThomas Petazzoni skb->csum = 0; 1803c5aff182SThomas Petazzoni skb->ip_summed = CHECKSUM_UNNECESSARY; 1804c5aff182SThomas Petazzoni return; 1805c5aff182SThomas Petazzoni } 1806c5aff182SThomas Petazzoni 1807c5aff182SThomas Petazzoni skb->ip_summed = CHECKSUM_NONE; 1808c5aff182SThomas Petazzoni } 1809c5aff182SThomas Petazzoni 18106c498974Swilly tarreau /* Return tx queue pointer (find last set bit) according to <cause> returned 18116c498974Swilly tarreau * form tx_done reg. <cause> must not be null. The return value is always a 18126c498974Swilly tarreau * valid queue for matching the first one found in <cause>. 18136c498974Swilly tarreau */ 1814c5aff182SThomas Petazzoni static struct mvneta_tx_queue *mvneta_tx_done_policy(struct mvneta_port *pp, 1815c5aff182SThomas Petazzoni u32 cause) 1816c5aff182SThomas Petazzoni { 1817c5aff182SThomas Petazzoni int queue = fls(cause) - 1; 1818c5aff182SThomas Petazzoni 18196c498974Swilly tarreau return &pp->txqs[queue]; 1820c5aff182SThomas Petazzoni } 1821c5aff182SThomas Petazzoni 1822c5aff182SThomas Petazzoni /* Free tx queue skbuffs */ 1823c5aff182SThomas Petazzoni static void mvneta_txq_bufs_free(struct mvneta_port *pp, 1824a29b6235SMarcin Wojtas struct mvneta_tx_queue *txq, int num, 1825a29b6235SMarcin Wojtas struct netdev_queue *nq) 1826c5aff182SThomas Petazzoni { 1827a29b6235SMarcin Wojtas unsigned int bytes_compl = 0, pkts_compl = 0; 1828c5aff182SThomas Petazzoni int i; 1829c5aff182SThomas Petazzoni 1830c5aff182SThomas Petazzoni for (i = 0; i < num; i++) { 18319e58c8b4SLorenzo Bianconi struct mvneta_tx_buf *buf = &txq->buf[txq->txq_get_index]; 1832c5aff182SThomas Petazzoni struct mvneta_tx_desc *tx_desc = txq->descs + 1833c5aff182SThomas Petazzoni txq->txq_get_index; 1834a29b6235SMarcin Wojtas 1835c5aff182SThomas Petazzoni mvneta_txq_inc_get(txq); 1836c5aff182SThomas Petazzoni 1837b0a43db9SLorenzo Bianconi if (!IS_TSO_HEADER(txq, tx_desc->buf_phys_addr) && 1838b0a43db9SLorenzo Bianconi buf->type != MVNETA_TYPE_XDP_TX) 18392e3173a3SEzequiel Garcia dma_unmap_single(pp->dev->dev.parent, 18402e3173a3SEzequiel Garcia tx_desc->buf_phys_addr, 1841c5aff182SThomas Petazzoni tx_desc->data_size, DMA_TO_DEVICE); 1842b0a43db9SLorenzo Bianconi if (buf->type == MVNETA_TYPE_SKB && buf->skb) { 18439e58c8b4SLorenzo Bianconi bytes_compl += buf->skb->len; 18449e58c8b4SLorenzo Bianconi pkts_compl++; 18459e58c8b4SLorenzo Bianconi dev_kfree_skb_any(buf->skb); 1846b0a43db9SLorenzo Bianconi } else if (buf->type == MVNETA_TYPE_XDP_TX || 1847b0a43db9SLorenzo Bianconi buf->type == MVNETA_TYPE_XDP_NDO) { 1848b0a43db9SLorenzo Bianconi xdp_return_frame(buf->xdpf); 1849b0a43db9SLorenzo Bianconi } 1850c5aff182SThomas Petazzoni } 1851a29b6235SMarcin Wojtas 1852a29b6235SMarcin Wojtas netdev_tx_completed_queue(nq, pkts_compl, bytes_compl); 1853c5aff182SThomas Petazzoni } 1854c5aff182SThomas Petazzoni 1855c5aff182SThomas Petazzoni /* Handle end of transmission */ 1856cd713199SArnaud Ebalard static void mvneta_txq_done(struct mvneta_port *pp, 1857c5aff182SThomas Petazzoni struct mvneta_tx_queue *txq) 1858c5aff182SThomas Petazzoni { 1859c5aff182SThomas Petazzoni struct netdev_queue *nq = netdev_get_tx_queue(pp->dev, txq->id); 1860c5aff182SThomas Petazzoni int tx_done; 1861c5aff182SThomas Petazzoni 1862c5aff182SThomas Petazzoni tx_done = mvneta_txq_sent_desc_proc(pp, txq); 1863cd713199SArnaud Ebalard if (!tx_done) 1864cd713199SArnaud Ebalard return; 1865cd713199SArnaud Ebalard 1866a29b6235SMarcin Wojtas mvneta_txq_bufs_free(pp, txq, tx_done, nq); 1867c5aff182SThomas Petazzoni 1868c5aff182SThomas Petazzoni txq->count -= tx_done; 1869c5aff182SThomas Petazzoni 1870c5aff182SThomas Petazzoni if (netif_tx_queue_stopped(nq)) { 18718eef5f97SEzequiel Garcia if (txq->count <= txq->tx_wake_threshold) 1872c5aff182SThomas Petazzoni netif_tx_wake_queue(nq); 1873c5aff182SThomas Petazzoni } 1874c5aff182SThomas Petazzoni } 1875c5aff182SThomas Petazzoni 1876dc35a10fSMarcin Wojtas /* Refill processing for SW buffer management */ 18777e47fd84SGregory CLEMENT /* Allocate page per descriptor */ 1878c5aff182SThomas Petazzoni static int mvneta_rx_refill(struct mvneta_port *pp, 1879f88bee1cSGregory CLEMENT struct mvneta_rx_desc *rx_desc, 18807e47fd84SGregory CLEMENT struct mvneta_rx_queue *rxq, 18817e47fd84SGregory CLEMENT gfp_t gfp_mask) 1882c5aff182SThomas Petazzoni { 1883c5aff182SThomas Petazzoni dma_addr_t phys_addr; 18847e47fd84SGregory CLEMENT struct page *page; 1885c5aff182SThomas Petazzoni 1886568a3fa2SLorenzo Bianconi page = page_pool_alloc_pages(rxq->page_pool, 1887568a3fa2SLorenzo Bianconi gfp_mask | __GFP_NOWARN); 18887e47fd84SGregory CLEMENT if (!page) 1889c5aff182SThomas Petazzoni return -ENOMEM; 1890c5aff182SThomas Petazzoni 1891568a3fa2SLorenzo Bianconi phys_addr = page_pool_get_dma_addr(page) + pp->rx_offset_correction; 18927e47fd84SGregory CLEMENT mvneta_rx_desc_fill(rx_desc, phys_addr, page, rxq); 1893568a3fa2SLorenzo Bianconi 1894c5aff182SThomas Petazzoni return 0; 1895c5aff182SThomas Petazzoni } 1896c5aff182SThomas Petazzoni 1897c5aff182SThomas Petazzoni /* Handle tx checksum */ 1898c5aff182SThomas Petazzoni static u32 mvneta_skb_tx_csum(struct mvneta_port *pp, struct sk_buff *skb) 1899c5aff182SThomas Petazzoni { 1900c5aff182SThomas Petazzoni if (skb->ip_summed == CHECKSUM_PARTIAL) { 1901c5aff182SThomas Petazzoni int ip_hdr_len = 0; 1902817dbfa5SVlad Yasevich __be16 l3_proto = vlan_get_protocol(skb); 1903c5aff182SThomas Petazzoni u8 l4_proto; 1904c5aff182SThomas Petazzoni 1905817dbfa5SVlad Yasevich if (l3_proto == htons(ETH_P_IP)) { 1906c5aff182SThomas Petazzoni struct iphdr *ip4h = ip_hdr(skb); 1907c5aff182SThomas Petazzoni 1908c5aff182SThomas Petazzoni /* Calculate IPv4 checksum and L4 checksum */ 1909c5aff182SThomas Petazzoni ip_hdr_len = ip4h->ihl; 1910c5aff182SThomas Petazzoni l4_proto = ip4h->protocol; 1911817dbfa5SVlad Yasevich } else if (l3_proto == htons(ETH_P_IPV6)) { 1912c5aff182SThomas Petazzoni struct ipv6hdr *ip6h = ipv6_hdr(skb); 1913c5aff182SThomas Petazzoni 1914c5aff182SThomas Petazzoni /* Read l4_protocol from one of IPv6 extra headers */ 1915c5aff182SThomas Petazzoni if (skb_network_header_len(skb) > 0) 1916c5aff182SThomas Petazzoni ip_hdr_len = (skb_network_header_len(skb) >> 2); 1917c5aff182SThomas Petazzoni l4_proto = ip6h->nexthdr; 1918c5aff182SThomas Petazzoni } else 1919c5aff182SThomas Petazzoni return MVNETA_TX_L4_CSUM_NOT; 1920c5aff182SThomas Petazzoni 1921c5aff182SThomas Petazzoni return mvneta_txq_desc_csum(skb_network_offset(skb), 1922817dbfa5SVlad Yasevich l3_proto, ip_hdr_len, l4_proto); 1923c5aff182SThomas Petazzoni } 1924c5aff182SThomas Petazzoni 1925c5aff182SThomas Petazzoni return MVNETA_TX_L4_CSUM_NOT; 1926c5aff182SThomas Petazzoni } 1927c5aff182SThomas Petazzoni 1928c5aff182SThomas Petazzoni /* Drop packets received by the RXQ and free buffers */ 1929c5aff182SThomas Petazzoni static void mvneta_rxq_drop_pkts(struct mvneta_port *pp, 1930c5aff182SThomas Petazzoni struct mvneta_rx_queue *rxq) 1931c5aff182SThomas Petazzoni { 1932c5aff182SThomas Petazzoni int rx_done, i; 1933c5aff182SThomas Petazzoni 1934c5aff182SThomas Petazzoni rx_done = mvneta_rxq_busy_desc_num_get(pp, rxq); 1935dc35a10fSMarcin Wojtas if (rx_done) 1936dc35a10fSMarcin Wojtas mvneta_rxq_desc_num_update(pp, rxq, rx_done, rx_done); 1937dc35a10fSMarcin Wojtas 1938dc35a10fSMarcin Wojtas if (pp->bm_priv) { 1939dc35a10fSMarcin Wojtas for (i = 0; i < rx_done; i++) { 1940dc35a10fSMarcin Wojtas struct mvneta_rx_desc *rx_desc = 1941dc35a10fSMarcin Wojtas mvneta_rxq_next_desc_get(rxq); 1942dc35a10fSMarcin Wojtas u8 pool_id = MVNETA_RX_GET_BM_POOL_ID(rx_desc); 1943dc35a10fSMarcin Wojtas struct mvneta_bm_pool *bm_pool; 1944dc35a10fSMarcin Wojtas 1945dc35a10fSMarcin Wojtas bm_pool = &pp->bm_priv->bm_pools[pool_id]; 1946dc35a10fSMarcin Wojtas /* Return dropped buffer to the pool */ 1947dc35a10fSMarcin Wojtas mvneta_bm_pool_put_bp(pp->bm_priv, bm_pool, 1948dc35a10fSMarcin Wojtas rx_desc->buf_phys_addr); 1949dc35a10fSMarcin Wojtas } 1950dc35a10fSMarcin Wojtas return; 1951dc35a10fSMarcin Wojtas } 1952dc35a10fSMarcin Wojtas 1953c5aff182SThomas Petazzoni for (i = 0; i < rxq->size; i++) { 1954c5aff182SThomas Petazzoni struct mvneta_rx_desc *rx_desc = rxq->descs + i; 1955f88bee1cSGregory CLEMENT void *data = rxq->buf_virt_addr[i]; 1956562e2f46SYelena Krivosheev if (!data || !(rx_desc->buf_phys_addr)) 1957562e2f46SYelena Krivosheev continue; 1958c5aff182SThomas Petazzoni 1959458de8a9SIlias Apalodimas page_pool_put_full_page(rxq->page_pool, data, false); 1960dc35a10fSMarcin Wojtas } 1961568a3fa2SLorenzo Bianconi if (xdp_rxq_info_is_reg(&rxq->xdp_rxq)) 1962568a3fa2SLorenzo Bianconi xdp_rxq_info_unreg(&rxq->xdp_rxq); 1963568a3fa2SLorenzo Bianconi page_pool_destroy(rxq->page_pool); 1964568a3fa2SLorenzo Bianconi rxq->page_pool = NULL; 1965c5aff182SThomas Petazzoni } 1966c5aff182SThomas Petazzoni 1967ff519e2aSLorenzo Bianconi static void 1968320d5441SLorenzo Bianconi mvneta_update_stats(struct mvneta_port *pp, 1969320d5441SLorenzo Bianconi struct mvneta_stats *ps) 1970ff519e2aSLorenzo Bianconi { 1971ff519e2aSLorenzo Bianconi struct mvneta_pcpu_stats *stats = this_cpu_ptr(pp->stats); 1972ff519e2aSLorenzo Bianconi 1973ff519e2aSLorenzo Bianconi u64_stats_update_begin(&stats->syncp); 1974320d5441SLorenzo Bianconi stats->es.ps.rx_packets += ps->rx_packets; 1975320d5441SLorenzo Bianconi stats->es.ps.rx_bytes += ps->rx_bytes; 19763d866523SLorenzo Bianconi /* xdp */ 19773d866523SLorenzo Bianconi stats->es.ps.xdp_redirect += ps->xdp_redirect; 19783d866523SLorenzo Bianconi stats->es.ps.xdp_pass += ps->xdp_pass; 19793d866523SLorenzo Bianconi stats->es.ps.xdp_drop += ps->xdp_drop; 1980ff519e2aSLorenzo Bianconi u64_stats_update_end(&stats->syncp); 1981ff519e2aSLorenzo Bianconi } 1982ff519e2aSLorenzo Bianconi 1983562e2f46SYelena Krivosheev static inline 1984562e2f46SYelena Krivosheev int mvneta_rx_refill_queue(struct mvneta_port *pp, struct mvneta_rx_queue *rxq) 1985562e2f46SYelena Krivosheev { 1986562e2f46SYelena Krivosheev struct mvneta_rx_desc *rx_desc; 1987562e2f46SYelena Krivosheev int curr_desc = rxq->first_to_refill; 1988562e2f46SYelena Krivosheev int i; 1989562e2f46SYelena Krivosheev 1990562e2f46SYelena Krivosheev for (i = 0; (i < rxq->refill_num) && (i < 64); i++) { 1991562e2f46SYelena Krivosheev rx_desc = rxq->descs + curr_desc; 1992562e2f46SYelena Krivosheev if (!(rx_desc->buf_phys_addr)) { 1993562e2f46SYelena Krivosheev if (mvneta_rx_refill(pp, rx_desc, rxq, GFP_ATOMIC)) { 19949ac41f3cSLorenzo Bianconi struct mvneta_pcpu_stats *stats; 19959ac41f3cSLorenzo Bianconi 1996562e2f46SYelena Krivosheev pr_err("Can't refill queue %d. Done %d from %d\n", 1997562e2f46SYelena Krivosheev rxq->id, i, rxq->refill_num); 19989ac41f3cSLorenzo Bianconi 19999ac41f3cSLorenzo Bianconi stats = this_cpu_ptr(pp->stats); 20009ac41f3cSLorenzo Bianconi u64_stats_update_begin(&stats->syncp); 20019ac41f3cSLorenzo Bianconi stats->es.refill_error++; 20029ac41f3cSLorenzo Bianconi u64_stats_update_end(&stats->syncp); 2003562e2f46SYelena Krivosheev break; 2004562e2f46SYelena Krivosheev } 2005562e2f46SYelena Krivosheev } 2006562e2f46SYelena Krivosheev curr_desc = MVNETA_QUEUE_NEXT_DESC(rxq, curr_desc); 2007562e2f46SYelena Krivosheev } 2008562e2f46SYelena Krivosheev rxq->refill_num -= i; 2009562e2f46SYelena Krivosheev rxq->first_to_refill = curr_desc; 2010562e2f46SYelena Krivosheev 2011562e2f46SYelena Krivosheev return i; 2012562e2f46SYelena Krivosheev } 2013562e2f46SYelena Krivosheev 20148dc9a088SLorenzo Bianconi static int 2015b0a43db9SLorenzo Bianconi mvneta_xdp_submit_frame(struct mvneta_port *pp, struct mvneta_tx_queue *txq, 2016b0a43db9SLorenzo Bianconi struct xdp_frame *xdpf, bool dma_map) 2017b0a43db9SLorenzo Bianconi { 2018b0a43db9SLorenzo Bianconi struct mvneta_tx_desc *tx_desc; 2019b0a43db9SLorenzo Bianconi struct mvneta_tx_buf *buf; 2020b0a43db9SLorenzo Bianconi dma_addr_t dma_addr; 2021b0a43db9SLorenzo Bianconi 2022b0a43db9SLorenzo Bianconi if (txq->count >= txq->tx_stop_threshold) 2023b0a43db9SLorenzo Bianconi return MVNETA_XDP_DROPPED; 2024b0a43db9SLorenzo Bianconi 2025b0a43db9SLorenzo Bianconi tx_desc = mvneta_txq_next_desc_get(txq); 2026b0a43db9SLorenzo Bianconi 2027b0a43db9SLorenzo Bianconi buf = &txq->buf[txq->txq_put_index]; 2028b0a43db9SLorenzo Bianconi if (dma_map) { 2029b0a43db9SLorenzo Bianconi /* ndo_xdp_xmit */ 2030b0a43db9SLorenzo Bianconi dma_addr = dma_map_single(pp->dev->dev.parent, xdpf->data, 2031b0a43db9SLorenzo Bianconi xdpf->len, DMA_TO_DEVICE); 2032b0a43db9SLorenzo Bianconi if (dma_mapping_error(pp->dev->dev.parent, dma_addr)) { 2033b0a43db9SLorenzo Bianconi mvneta_txq_desc_put(txq); 2034b0a43db9SLorenzo Bianconi return MVNETA_XDP_DROPPED; 2035b0a43db9SLorenzo Bianconi } 2036b0a43db9SLorenzo Bianconi buf->type = MVNETA_TYPE_XDP_NDO; 2037b0a43db9SLorenzo Bianconi } else { 2038b0a43db9SLorenzo Bianconi struct page *page = virt_to_page(xdpf->data); 2039b0a43db9SLorenzo Bianconi 2040b0a43db9SLorenzo Bianconi dma_addr = page_pool_get_dma_addr(page) + 2041b0a43db9SLorenzo Bianconi sizeof(*xdpf) + xdpf->headroom; 2042b0a43db9SLorenzo Bianconi dma_sync_single_for_device(pp->dev->dev.parent, dma_addr, 2043b0a43db9SLorenzo Bianconi xdpf->len, DMA_BIDIRECTIONAL); 2044b0a43db9SLorenzo Bianconi buf->type = MVNETA_TYPE_XDP_TX; 2045b0a43db9SLorenzo Bianconi } 2046b0a43db9SLorenzo Bianconi buf->xdpf = xdpf; 2047b0a43db9SLorenzo Bianconi 2048b0a43db9SLorenzo Bianconi tx_desc->command = MVNETA_TXD_FLZ_DESC; 2049b0a43db9SLorenzo Bianconi tx_desc->buf_phys_addr = dma_addr; 2050b0a43db9SLorenzo Bianconi tx_desc->data_size = xdpf->len; 2051b0a43db9SLorenzo Bianconi 2052b0a43db9SLorenzo Bianconi mvneta_txq_inc_put(txq); 2053b0a43db9SLorenzo Bianconi txq->pending++; 2054b0a43db9SLorenzo Bianconi txq->count++; 2055b0a43db9SLorenzo Bianconi 2056b0a43db9SLorenzo Bianconi return MVNETA_XDP_TX; 2057b0a43db9SLorenzo Bianconi } 2058b0a43db9SLorenzo Bianconi 2059b0a43db9SLorenzo Bianconi static int 2060b0a43db9SLorenzo Bianconi mvneta_xdp_xmit_back(struct mvneta_port *pp, struct xdp_buff *xdp) 2061b0a43db9SLorenzo Bianconi { 2062b0a43db9SLorenzo Bianconi struct mvneta_tx_queue *txq; 2063b0a43db9SLorenzo Bianconi struct netdev_queue *nq; 2064b0a43db9SLorenzo Bianconi struct xdp_frame *xdpf; 2065b0a43db9SLorenzo Bianconi int cpu; 2066b0a43db9SLorenzo Bianconi u32 ret; 2067b0a43db9SLorenzo Bianconi 2068b0a43db9SLorenzo Bianconi xdpf = convert_to_xdp_frame(xdp); 2069b0a43db9SLorenzo Bianconi if (unlikely(!xdpf)) 2070b0a43db9SLorenzo Bianconi return MVNETA_XDP_DROPPED; 2071b0a43db9SLorenzo Bianconi 2072b0a43db9SLorenzo Bianconi cpu = smp_processor_id(); 2073b0a43db9SLorenzo Bianconi txq = &pp->txqs[cpu % txq_number]; 2074b0a43db9SLorenzo Bianconi nq = netdev_get_tx_queue(pp->dev, txq->id); 2075b0a43db9SLorenzo Bianconi 2076b0a43db9SLorenzo Bianconi __netif_tx_lock(nq, cpu); 2077b0a43db9SLorenzo Bianconi ret = mvneta_xdp_submit_frame(pp, txq, xdpf, false); 20787d51a015SLorenzo Bianconi if (ret == MVNETA_XDP_TX) { 20797d51a015SLorenzo Bianconi struct mvneta_pcpu_stats *stats = this_cpu_ptr(pp->stats); 20807d51a015SLorenzo Bianconi 20817d51a015SLorenzo Bianconi u64_stats_update_begin(&stats->syncp); 20827d51a015SLorenzo Bianconi stats->es.ps.tx_bytes += xdpf->len; 20837d51a015SLorenzo Bianconi stats->es.ps.tx_packets++; 20847d51a015SLorenzo Bianconi stats->es.ps.xdp_tx++; 20857d51a015SLorenzo Bianconi u64_stats_update_end(&stats->syncp); 20867d51a015SLorenzo Bianconi 2087b0a43db9SLorenzo Bianconi mvneta_txq_pend_desc_add(pp, txq, 0); 20887d51a015SLorenzo Bianconi } 2089b0a43db9SLorenzo Bianconi __netif_tx_unlock(nq); 2090b0a43db9SLorenzo Bianconi 2091b0a43db9SLorenzo Bianconi return ret; 2092b0a43db9SLorenzo Bianconi } 2093b0a43db9SLorenzo Bianconi 2094b0a43db9SLorenzo Bianconi static int 2095b0a43db9SLorenzo Bianconi mvneta_xdp_xmit(struct net_device *dev, int num_frame, 2096b0a43db9SLorenzo Bianconi struct xdp_frame **frames, u32 flags) 2097b0a43db9SLorenzo Bianconi { 2098b0a43db9SLorenzo Bianconi struct mvneta_port *pp = netdev_priv(dev); 20997d51a015SLorenzo Bianconi struct mvneta_pcpu_stats *stats = this_cpu_ptr(pp->stats); 21007d51a015SLorenzo Bianconi int i, nxmit_byte = 0, nxmit = num_frame; 2101b0a43db9SLorenzo Bianconi int cpu = smp_processor_id(); 2102b0a43db9SLorenzo Bianconi struct mvneta_tx_queue *txq; 2103b0a43db9SLorenzo Bianconi struct netdev_queue *nq; 2104b0a43db9SLorenzo Bianconi u32 ret; 2105b0a43db9SLorenzo Bianconi 2106b0a43db9SLorenzo Bianconi if (unlikely(flags & ~XDP_XMIT_FLAGS_MASK)) 2107b0a43db9SLorenzo Bianconi return -EINVAL; 2108b0a43db9SLorenzo Bianconi 2109b0a43db9SLorenzo Bianconi txq = &pp->txqs[cpu % txq_number]; 2110b0a43db9SLorenzo Bianconi nq = netdev_get_tx_queue(pp->dev, txq->id); 2111b0a43db9SLorenzo Bianconi 2112b0a43db9SLorenzo Bianconi __netif_tx_lock(nq, cpu); 2113b0a43db9SLorenzo Bianconi for (i = 0; i < num_frame; i++) { 2114b0a43db9SLorenzo Bianconi ret = mvneta_xdp_submit_frame(pp, txq, frames[i], true); 21157d51a015SLorenzo Bianconi if (ret == MVNETA_XDP_TX) { 21167d51a015SLorenzo Bianconi nxmit_byte += frames[i]->len; 21177d51a015SLorenzo Bianconi } else { 2118b0a43db9SLorenzo Bianconi xdp_return_frame_rx_napi(frames[i]); 21197d51a015SLorenzo Bianconi nxmit--; 2120b0a43db9SLorenzo Bianconi } 2121b0a43db9SLorenzo Bianconi } 2122b0a43db9SLorenzo Bianconi 2123b0a43db9SLorenzo Bianconi if (unlikely(flags & XDP_XMIT_FLUSH)) 2124b0a43db9SLorenzo Bianconi mvneta_txq_pend_desc_add(pp, txq, 0); 2125b0a43db9SLorenzo Bianconi __netif_tx_unlock(nq); 2126b0a43db9SLorenzo Bianconi 21277d51a015SLorenzo Bianconi u64_stats_update_begin(&stats->syncp); 21287d51a015SLorenzo Bianconi stats->es.ps.tx_bytes += nxmit_byte; 21297d51a015SLorenzo Bianconi stats->es.ps.tx_packets += nxmit; 21307d51a015SLorenzo Bianconi stats->es.ps.xdp_xmit += nxmit; 21317d51a015SLorenzo Bianconi u64_stats_update_end(&stats->syncp); 21327d51a015SLorenzo Bianconi 21337d51a015SLorenzo Bianconi return nxmit; 2134b0a43db9SLorenzo Bianconi } 2135b0a43db9SLorenzo Bianconi 2136b0a43db9SLorenzo Bianconi static int 21370db51da7SLorenzo Bianconi mvneta_run_xdp(struct mvneta_port *pp, struct mvneta_rx_queue *rxq, 2138320d5441SLorenzo Bianconi struct bpf_prog *prog, struct xdp_buff *xdp, 2139320d5441SLorenzo Bianconi struct mvneta_stats *stats) 21400db51da7SLorenzo Bianconi { 21418c4df83fSLorenzo Bianconi unsigned int len; 21428c4df83fSLorenzo Bianconi u32 ret, act; 21438c4df83fSLorenzo Bianconi 21448c4df83fSLorenzo Bianconi len = xdp->data_end - xdp->data_hard_start - pp->rx_offset_correction; 21458c4df83fSLorenzo Bianconi act = bpf_prog_run_xdp(prog, xdp); 21460db51da7SLorenzo Bianconi 21470db51da7SLorenzo Bianconi switch (act) { 21480db51da7SLorenzo Bianconi case XDP_PASS: 21493d866523SLorenzo Bianconi stats->xdp_pass++; 2150320d5441SLorenzo Bianconi return MVNETA_XDP_PASS; 21510db51da7SLorenzo Bianconi case XDP_REDIRECT: { 21520db51da7SLorenzo Bianconi int err; 21530db51da7SLorenzo Bianconi 21540db51da7SLorenzo Bianconi err = xdp_do_redirect(pp->dev, xdp, prog); 21550db51da7SLorenzo Bianconi if (err) { 21560db51da7SLorenzo Bianconi ret = MVNETA_XDP_DROPPED; 2157458de8a9SIlias Apalodimas page_pool_put_page(rxq->page_pool, 2158458de8a9SIlias Apalodimas virt_to_head_page(xdp->data), len, 2159458de8a9SIlias Apalodimas true); 21600db51da7SLorenzo Bianconi } else { 21610db51da7SLorenzo Bianconi ret = MVNETA_XDP_REDIR; 21623d866523SLorenzo Bianconi stats->xdp_redirect++; 21630db51da7SLorenzo Bianconi } 21640db51da7SLorenzo Bianconi break; 21650db51da7SLorenzo Bianconi } 2166b0a43db9SLorenzo Bianconi case XDP_TX: 2167b0a43db9SLorenzo Bianconi ret = mvneta_xdp_xmit_back(pp, xdp); 2168b0a43db9SLorenzo Bianconi if (ret != MVNETA_XDP_TX) 2169458de8a9SIlias Apalodimas page_pool_put_page(rxq->page_pool, 2170458de8a9SIlias Apalodimas virt_to_head_page(xdp->data), len, 2171458de8a9SIlias Apalodimas true); 2172b0a43db9SLorenzo Bianconi break; 21730db51da7SLorenzo Bianconi default: 21740db51da7SLorenzo Bianconi bpf_warn_invalid_xdp_action(act); 21750db51da7SLorenzo Bianconi /* fall through */ 21760db51da7SLorenzo Bianconi case XDP_ABORTED: 21770db51da7SLorenzo Bianconi trace_xdp_exception(pp->dev, prog, act); 21780db51da7SLorenzo Bianconi /* fall through */ 21790db51da7SLorenzo Bianconi case XDP_DROP: 2180458de8a9SIlias Apalodimas page_pool_put_page(rxq->page_pool, 2181458de8a9SIlias Apalodimas virt_to_head_page(xdp->data), len, true); 21820db51da7SLorenzo Bianconi ret = MVNETA_XDP_DROPPED; 21833d866523SLorenzo Bianconi stats->xdp_drop++; 21840db51da7SLorenzo Bianconi break; 21850db51da7SLorenzo Bianconi } 21860db51da7SLorenzo Bianconi 2187320d5441SLorenzo Bianconi stats->rx_bytes += xdp->data_end - xdp->data; 2188320d5441SLorenzo Bianconi stats->rx_packets++; 2189320d5441SLorenzo Bianconi 21900db51da7SLorenzo Bianconi return ret; 21910db51da7SLorenzo Bianconi } 21920db51da7SLorenzo Bianconi 21930db51da7SLorenzo Bianconi static int 21948dc9a088SLorenzo Bianconi mvneta_swbm_rx_frame(struct mvneta_port *pp, 21958dc9a088SLorenzo Bianconi struct mvneta_rx_desc *rx_desc, 21968dc9a088SLorenzo Bianconi struct mvneta_rx_queue *rxq, 21970db51da7SLorenzo Bianconi struct xdp_buff *xdp, 21980db51da7SLorenzo Bianconi struct bpf_prog *xdp_prog, 21996c8a8cfdSLorenzo Bianconi struct page *page, 2200320d5441SLorenzo Bianconi struct mvneta_stats *stats) 22018dc9a088SLorenzo Bianconi { 22028dc9a088SLorenzo Bianconi unsigned char *data = page_address(page); 22038dc9a088SLorenzo Bianconi int data_len = -MVNETA_MH_SIZE, len; 22048dc9a088SLorenzo Bianconi struct net_device *dev = pp->dev; 22058dc9a088SLorenzo Bianconi enum dma_data_direction dma_dir; 22066c8a8cfdSLorenzo Bianconi int ret = 0; 22078dc9a088SLorenzo Bianconi 22088dc9a088SLorenzo Bianconi if (MVNETA_SKB_SIZE(rx_desc->data_size) > PAGE_SIZE) { 22098dc9a088SLorenzo Bianconi len = MVNETA_MAX_RX_BUF_SIZE; 22108dc9a088SLorenzo Bianconi data_len += len; 22118dc9a088SLorenzo Bianconi } else { 22128dc9a088SLorenzo Bianconi len = rx_desc->data_size; 22138dc9a088SLorenzo Bianconi data_len += len - ETH_FCS_LEN; 22148dc9a088SLorenzo Bianconi } 22158dc9a088SLorenzo Bianconi 22168dc9a088SLorenzo Bianconi dma_dir = page_pool_get_dma_dir(rxq->page_pool); 22178dc9a088SLorenzo Bianconi dma_sync_single_for_cpu(dev->dev.parent, 22188dc9a088SLorenzo Bianconi rx_desc->buf_phys_addr, 22198dc9a088SLorenzo Bianconi len, dma_dir); 22208dc9a088SLorenzo Bianconi 2221fa383f6bSLorenzo Bianconi /* Prefetch header */ 2222fa383f6bSLorenzo Bianconi prefetch(data); 2223fa383f6bSLorenzo Bianconi 22240db51da7SLorenzo Bianconi xdp->data_hard_start = data; 2225b37fa92eSLorenzo Bianconi xdp->data = data + pp->rx_offset_correction + MVNETA_MH_SIZE; 22260db51da7SLorenzo Bianconi xdp->data_end = xdp->data + data_len; 22270db51da7SLorenzo Bianconi xdp_set_data_meta_invalid(xdp); 22280db51da7SLorenzo Bianconi 22290db51da7SLorenzo Bianconi if (xdp_prog) { 2230320d5441SLorenzo Bianconi ret = mvneta_run_xdp(pp, rxq, xdp_prog, xdp, stats); 22316c8a8cfdSLorenzo Bianconi if (ret) 22326c8a8cfdSLorenzo Bianconi goto out; 22330db51da7SLorenzo Bianconi } 22340db51da7SLorenzo Bianconi 22350db51da7SLorenzo Bianconi rxq->skb = build_skb(xdp->data_hard_start, PAGE_SIZE); 22368dc9a088SLorenzo Bianconi if (unlikely(!rxq->skb)) { 2237c35947b8SLorenzo Bianconi struct mvneta_pcpu_stats *stats = this_cpu_ptr(pp->stats); 2238c35947b8SLorenzo Bianconi 2239c35947b8SLorenzo Bianconi netdev_err(dev, "Can't allocate skb on queue %d\n", rxq->id); 2240c35947b8SLorenzo Bianconi 2241c35947b8SLorenzo Bianconi u64_stats_update_begin(&stats->syncp); 22429ac41f3cSLorenzo Bianconi stats->es.skb_alloc_error++; 2243c35947b8SLorenzo Bianconi stats->rx_dropped++; 2244c35947b8SLorenzo Bianconi u64_stats_update_end(&stats->syncp); 2245c35947b8SLorenzo Bianconi 22468dc9a088SLorenzo Bianconi return -ENOMEM; 22478dc9a088SLorenzo Bianconi } 22488dc9a088SLorenzo Bianconi page_pool_release_page(rxq->page_pool, page); 22498dc9a088SLorenzo Bianconi 22500db51da7SLorenzo Bianconi skb_reserve(rxq->skb, 22510db51da7SLorenzo Bianconi xdp->data - xdp->data_hard_start); 22520db51da7SLorenzo Bianconi skb_put(rxq->skb, xdp->data_end - xdp->data); 22538dc9a088SLorenzo Bianconi mvneta_rx_csum(pp, rx_desc->status, rxq->skb); 22548dc9a088SLorenzo Bianconi 22558dc9a088SLorenzo Bianconi rxq->left_size = rx_desc->data_size - len; 22566c8a8cfdSLorenzo Bianconi 22576c8a8cfdSLorenzo Bianconi out: 22588dc9a088SLorenzo Bianconi rx_desc->buf_phys_addr = 0; 22598dc9a088SLorenzo Bianconi 22606c8a8cfdSLorenzo Bianconi return ret; 22618dc9a088SLorenzo Bianconi } 22628dc9a088SLorenzo Bianconi 22638dc9a088SLorenzo Bianconi static void 22648dc9a088SLorenzo Bianconi mvneta_swbm_add_rx_fragment(struct mvneta_port *pp, 22658dc9a088SLorenzo Bianconi struct mvneta_rx_desc *rx_desc, 22668dc9a088SLorenzo Bianconi struct mvneta_rx_queue *rxq, 22678dc9a088SLorenzo Bianconi struct page *page) 22688dc9a088SLorenzo Bianconi { 22698dc9a088SLorenzo Bianconi struct net_device *dev = pp->dev; 22708dc9a088SLorenzo Bianconi enum dma_data_direction dma_dir; 22718dc9a088SLorenzo Bianconi int data_len, len; 22728dc9a088SLorenzo Bianconi 22738dc9a088SLorenzo Bianconi if (rxq->left_size > MVNETA_MAX_RX_BUF_SIZE) { 22748dc9a088SLorenzo Bianconi len = MVNETA_MAX_RX_BUF_SIZE; 22758dc9a088SLorenzo Bianconi data_len = len; 22768dc9a088SLorenzo Bianconi } else { 22778dc9a088SLorenzo Bianconi len = rxq->left_size; 22788dc9a088SLorenzo Bianconi data_len = len - ETH_FCS_LEN; 22798dc9a088SLorenzo Bianconi } 22808dc9a088SLorenzo Bianconi dma_dir = page_pool_get_dma_dir(rxq->page_pool); 22818dc9a088SLorenzo Bianconi dma_sync_single_for_cpu(dev->dev.parent, 22828dc9a088SLorenzo Bianconi rx_desc->buf_phys_addr, 22838dc9a088SLorenzo Bianconi len, dma_dir); 22848dc9a088SLorenzo Bianconi if (data_len > 0) { 22858dc9a088SLorenzo Bianconi /* refill descriptor with new buffer later */ 22868dc9a088SLorenzo Bianconi skb_add_rx_frag(rxq->skb, 22878dc9a088SLorenzo Bianconi skb_shinfo(rxq->skb)->nr_frags, 2288b37fa92eSLorenzo Bianconi page, pp->rx_offset_correction, data_len, 22898dc9a088SLorenzo Bianconi PAGE_SIZE); 22908dc9a088SLorenzo Bianconi } 22918dc9a088SLorenzo Bianconi page_pool_release_page(rxq->page_pool, page); 22928dc9a088SLorenzo Bianconi rx_desc->buf_phys_addr = 0; 22938dc9a088SLorenzo Bianconi rxq->left_size -= len; 22948dc9a088SLorenzo Bianconi } 22958dc9a088SLorenzo Bianconi 2296dc35a10fSMarcin Wojtas /* Main rx processing when using software buffer management */ 22977a86f05fSAndrew Lunn static int mvneta_rx_swbm(struct napi_struct *napi, 2298562e2f46SYelena Krivosheev struct mvneta_port *pp, int budget, 2299c5aff182SThomas Petazzoni struct mvneta_rx_queue *rxq) 2300c5aff182SThomas Petazzoni { 2301320d5441SLorenzo Bianconi int rx_proc = 0, rx_todo, refill; 2302c5aff182SThomas Petazzoni struct net_device *dev = pp->dev; 2303320d5441SLorenzo Bianconi struct mvneta_stats ps = {}; 23040db51da7SLorenzo Bianconi struct bpf_prog *xdp_prog; 23050db51da7SLorenzo Bianconi struct xdp_buff xdp_buf; 2306c5aff182SThomas Petazzoni 2307c5aff182SThomas Petazzoni /* Get number of received packets */ 2308562e2f46SYelena Krivosheev rx_todo = mvneta_rxq_busy_desc_num_get(pp, rxq); 2309c5aff182SThomas Petazzoni 23100db51da7SLorenzo Bianconi rcu_read_lock(); 23110db51da7SLorenzo Bianconi xdp_prog = READ_ONCE(pp->xdp_prog); 23120db51da7SLorenzo Bianconi xdp_buf.rxq = &rxq->xdp_rxq; 23130db51da7SLorenzo Bianconi 2314c5aff182SThomas Petazzoni /* Fairness NAPI loop */ 23158dc9a088SLorenzo Bianconi while (rx_proc < budget && rx_proc < rx_todo) { 2316c5aff182SThomas Petazzoni struct mvneta_rx_desc *rx_desc = mvneta_rxq_next_desc_get(rxq); 23178dc9a088SLorenzo Bianconi u32 rx_status, index; 23187e47fd84SGregory CLEMENT struct page *page; 2319c5aff182SThomas Petazzoni 2320f88bee1cSGregory CLEMENT index = rx_desc - rxq->descs; 23217e47fd84SGregory CLEMENT page = (struct page *)rxq->buf_virt_addr[index]; 2322c5aff182SThomas Petazzoni 2323562e2f46SYelena Krivosheev rx_status = rx_desc->status; 2324562e2f46SYelena Krivosheev rx_proc++; 2325562e2f46SYelena Krivosheev rxq->refill_num++; 2326562e2f46SYelena Krivosheev 2327562e2f46SYelena Krivosheev if (rx_status & MVNETA_RXD_FIRST_DESC) { 23288dc9a088SLorenzo Bianconi int err; 23298dc9a088SLorenzo Bianconi 2330562e2f46SYelena Krivosheev /* Check errors only for FIRST descriptor */ 2331562e2f46SYelena Krivosheev if (rx_status & MVNETA_RXD_ERR_SUMMARY) { 23322eecb2e0SYelena Krivosheev mvneta_rx_error(pp, rx_desc); 23338ec2cd48Swilly tarreau /* leave the descriptor untouched */ 2334c5aff182SThomas Petazzoni continue; 2335c5aff182SThomas Petazzoni } 2336c5aff182SThomas Petazzoni 23370db51da7SLorenzo Bianconi err = mvneta_swbm_rx_frame(pp, rx_desc, rxq, &xdp_buf, 23386c8a8cfdSLorenzo Bianconi xdp_prog, page, &ps); 23398dc9a088SLorenzo Bianconi if (err) 2340f19fadfcSwilly tarreau continue; 2341562e2f46SYelena Krivosheev } else { 2342562e2f46SYelena Krivosheev if (unlikely(!rxq->skb)) { 2343562e2f46SYelena Krivosheev pr_debug("no skb for rx_status 0x%x\n", 2344562e2f46SYelena Krivosheev rx_status); 2345562e2f46SYelena Krivosheev continue; 2346562e2f46SYelena Krivosheev } 23478dc9a088SLorenzo Bianconi mvneta_swbm_add_rx_fragment(pp, rx_desc, rxq, page); 2348562e2f46SYelena Krivosheev } /* Middle or Last descriptor */ 2349562e2f46SYelena Krivosheev 2350562e2f46SYelena Krivosheev if (!(rx_status & MVNETA_RXD_LAST_DESC)) 2351562e2f46SYelena Krivosheev /* no last descriptor this time */ 2352562e2f46SYelena Krivosheev continue; 2353562e2f46SYelena Krivosheev 2354562e2f46SYelena Krivosheev if (rxq->left_size) { 2355562e2f46SYelena Krivosheev pr_err("get last desc, but left_size (%d) != 0\n", 2356562e2f46SYelena Krivosheev rxq->left_size); 2357562e2f46SYelena Krivosheev dev_kfree_skb_any(rxq->skb); 2358562e2f46SYelena Krivosheev rxq->left_size = 0; 2359562e2f46SYelena Krivosheev rxq->skb = NULL; 2360562e2f46SYelena Krivosheev continue; 2361562e2f46SYelena Krivosheev } 2362320d5441SLorenzo Bianconi 2363320d5441SLorenzo Bianconi ps.rx_bytes += rxq->skb->len; 2364320d5441SLorenzo Bianconi ps.rx_packets++; 2365c5aff182SThomas Petazzoni 2366c5aff182SThomas Petazzoni /* Linux processing */ 2367562e2f46SYelena Krivosheev rxq->skb->protocol = eth_type_trans(rxq->skb, dev); 2368c5aff182SThomas Petazzoni 2369562e2f46SYelena Krivosheev napi_gro_receive(napi, rxq->skb); 2370c5aff182SThomas Petazzoni 2371562e2f46SYelena Krivosheev /* clean uncomplete skb pointer in queue */ 2372562e2f46SYelena Krivosheev rxq->skb = NULL; 2373c5aff182SThomas Petazzoni } 23740db51da7SLorenzo Bianconi rcu_read_unlock(); 23750db51da7SLorenzo Bianconi 23766c8a8cfdSLorenzo Bianconi if (ps.xdp_redirect) 23770db51da7SLorenzo Bianconi xdp_do_flush_map(); 2378c5aff182SThomas Petazzoni 2379320d5441SLorenzo Bianconi if (ps.rx_packets) 2380320d5441SLorenzo Bianconi mvneta_update_stats(pp, &ps); 2381dc4277ddSwilly tarreau 2382562e2f46SYelena Krivosheev /* return some buffers to hardware queue, one at a time is too slow */ 2383562e2f46SYelena Krivosheev refill = mvneta_rx_refill_queue(pp, rxq); 2384c5aff182SThomas Petazzoni 2385562e2f46SYelena Krivosheev /* Update rxq management counters */ 2386562e2f46SYelena Krivosheev mvneta_rxq_desc_num_update(pp, rxq, rx_proc, refill); 2387562e2f46SYelena Krivosheev 2388320d5441SLorenzo Bianconi return ps.rx_packets; 2389c5aff182SThomas Petazzoni } 2390c5aff182SThomas Petazzoni 2391dc35a10fSMarcin Wojtas /* Main rx processing when using hardware buffer management */ 23927a86f05fSAndrew Lunn static int mvneta_rx_hwbm(struct napi_struct *napi, 23937a86f05fSAndrew Lunn struct mvneta_port *pp, int rx_todo, 2394dc35a10fSMarcin Wojtas struct mvneta_rx_queue *rxq) 2395dc35a10fSMarcin Wojtas { 2396dc35a10fSMarcin Wojtas struct net_device *dev = pp->dev; 2397dc35a10fSMarcin Wojtas int rx_done; 2398dc35a10fSMarcin Wojtas u32 rcvd_pkts = 0; 2399dc35a10fSMarcin Wojtas u32 rcvd_bytes = 0; 2400dc35a10fSMarcin Wojtas 2401dc35a10fSMarcin Wojtas /* Get number of received packets */ 2402dc35a10fSMarcin Wojtas rx_done = mvneta_rxq_busy_desc_num_get(pp, rxq); 2403dc35a10fSMarcin Wojtas 2404dc35a10fSMarcin Wojtas if (rx_todo > rx_done) 2405dc35a10fSMarcin Wojtas rx_todo = rx_done; 2406dc35a10fSMarcin Wojtas 2407dc35a10fSMarcin Wojtas rx_done = 0; 2408dc35a10fSMarcin Wojtas 2409dc35a10fSMarcin Wojtas /* Fairness NAPI loop */ 2410dc35a10fSMarcin Wojtas while (rx_done < rx_todo) { 2411dc35a10fSMarcin Wojtas struct mvneta_rx_desc *rx_desc = mvneta_rxq_next_desc_get(rxq); 2412dc35a10fSMarcin Wojtas struct mvneta_bm_pool *bm_pool = NULL; 2413dc35a10fSMarcin Wojtas struct sk_buff *skb; 2414dc35a10fSMarcin Wojtas unsigned char *data; 2415dc35a10fSMarcin Wojtas dma_addr_t phys_addr; 2416dc35a10fSMarcin Wojtas u32 rx_status, frag_size; 2417dc35a10fSMarcin Wojtas int rx_bytes, err; 2418dc35a10fSMarcin Wojtas u8 pool_id; 2419dc35a10fSMarcin Wojtas 2420dc35a10fSMarcin Wojtas rx_done++; 2421dc35a10fSMarcin Wojtas rx_status = rx_desc->status; 2422dc35a10fSMarcin Wojtas rx_bytes = rx_desc->data_size - (ETH_FCS_LEN + MVNETA_MH_SIZE); 2423f88bee1cSGregory CLEMENT data = (u8 *)(uintptr_t)rx_desc->buf_cookie; 2424dc35a10fSMarcin Wojtas phys_addr = rx_desc->buf_phys_addr; 2425dc35a10fSMarcin Wojtas pool_id = MVNETA_RX_GET_BM_POOL_ID(rx_desc); 2426dc35a10fSMarcin Wojtas bm_pool = &pp->bm_priv->bm_pools[pool_id]; 2427dc35a10fSMarcin Wojtas 2428dc35a10fSMarcin Wojtas if (!mvneta_rxq_desc_is_first_last(rx_status) || 2429dc35a10fSMarcin Wojtas (rx_status & MVNETA_RXD_ERR_SUMMARY)) { 2430dc35a10fSMarcin Wojtas err_drop_frame_ret_pool: 2431dc35a10fSMarcin Wojtas /* Return the buffer to the pool */ 2432dc35a10fSMarcin Wojtas mvneta_bm_pool_put_bp(pp->bm_priv, bm_pool, 2433dc35a10fSMarcin Wojtas rx_desc->buf_phys_addr); 2434dc35a10fSMarcin Wojtas err_drop_frame: 2435dc35a10fSMarcin Wojtas mvneta_rx_error(pp, rx_desc); 2436dc35a10fSMarcin Wojtas /* leave the descriptor untouched */ 2437dc35a10fSMarcin Wojtas continue; 2438dc35a10fSMarcin Wojtas } 2439dc35a10fSMarcin Wojtas 2440dc35a10fSMarcin Wojtas if (rx_bytes <= rx_copybreak) { 2441dc35a10fSMarcin Wojtas /* better copy a small frame and not unmap the DMA region */ 2442dc35a10fSMarcin Wojtas skb = netdev_alloc_skb_ip_align(dev, rx_bytes); 2443dc35a10fSMarcin Wojtas if (unlikely(!skb)) 2444dc35a10fSMarcin Wojtas goto err_drop_frame_ret_pool; 2445dc35a10fSMarcin Wojtas 2446a8fef9baSRussell King dma_sync_single_range_for_cpu(&pp->bm_priv->pdev->dev, 2447dc35a10fSMarcin Wojtas rx_desc->buf_phys_addr, 2448dc35a10fSMarcin Wojtas MVNETA_MH_SIZE + NET_SKB_PAD, 2449dc35a10fSMarcin Wojtas rx_bytes, 2450dc35a10fSMarcin Wojtas DMA_FROM_DEVICE); 245159ae1d12SJohannes Berg skb_put_data(skb, data + MVNETA_MH_SIZE + NET_SKB_PAD, 2452dc35a10fSMarcin Wojtas rx_bytes); 2453dc35a10fSMarcin Wojtas 2454dc35a10fSMarcin Wojtas skb->protocol = eth_type_trans(skb, dev); 2455dc35a10fSMarcin Wojtas mvneta_rx_csum(pp, rx_status, skb); 24567a86f05fSAndrew Lunn napi_gro_receive(napi, skb); 2457dc35a10fSMarcin Wojtas 2458dc35a10fSMarcin Wojtas rcvd_pkts++; 2459dc35a10fSMarcin Wojtas rcvd_bytes += rx_bytes; 2460dc35a10fSMarcin Wojtas 2461dc35a10fSMarcin Wojtas /* Return the buffer to the pool */ 2462dc35a10fSMarcin Wojtas mvneta_bm_pool_put_bp(pp->bm_priv, bm_pool, 2463dc35a10fSMarcin Wojtas rx_desc->buf_phys_addr); 2464dc35a10fSMarcin Wojtas 2465dc35a10fSMarcin Wojtas /* leave the descriptor and buffer untouched */ 2466dc35a10fSMarcin Wojtas continue; 2467dc35a10fSMarcin Wojtas } 2468dc35a10fSMarcin Wojtas 2469dc35a10fSMarcin Wojtas /* Refill processing */ 2470baa11ebcSGregory CLEMENT err = hwbm_pool_refill(&bm_pool->hwbm_pool, GFP_ATOMIC); 2471dc35a10fSMarcin Wojtas if (err) { 24729ac41f3cSLorenzo Bianconi struct mvneta_pcpu_stats *stats; 24739ac41f3cSLorenzo Bianconi 2474dc35a10fSMarcin Wojtas netdev_err(dev, "Linux processing - Can't refill\n"); 24759ac41f3cSLorenzo Bianconi 24769ac41f3cSLorenzo Bianconi stats = this_cpu_ptr(pp->stats); 24779ac41f3cSLorenzo Bianconi u64_stats_update_begin(&stats->syncp); 24789ac41f3cSLorenzo Bianconi stats->es.refill_error++; 24799ac41f3cSLorenzo Bianconi u64_stats_update_end(&stats->syncp); 24809ac41f3cSLorenzo Bianconi 2481dc35a10fSMarcin Wojtas goto err_drop_frame_ret_pool; 2482dc35a10fSMarcin Wojtas } 2483dc35a10fSMarcin Wojtas 2484baa11ebcSGregory CLEMENT frag_size = bm_pool->hwbm_pool.frag_size; 2485dc35a10fSMarcin Wojtas 2486dc35a10fSMarcin Wojtas skb = build_skb(data, frag_size > PAGE_SIZE ? 0 : frag_size); 2487dc35a10fSMarcin Wojtas 2488dc35a10fSMarcin Wojtas /* After refill old buffer has to be unmapped regardless 2489dc35a10fSMarcin Wojtas * the skb is successfully built or not. 2490dc35a10fSMarcin Wojtas */ 2491dc35a10fSMarcin Wojtas dma_unmap_single(&pp->bm_priv->pdev->dev, phys_addr, 2492dc35a10fSMarcin Wojtas bm_pool->buf_size, DMA_FROM_DEVICE); 2493dc35a10fSMarcin Wojtas if (!skb) 2494dc35a10fSMarcin Wojtas goto err_drop_frame; 2495dc35a10fSMarcin Wojtas 2496dc35a10fSMarcin Wojtas rcvd_pkts++; 2497dc35a10fSMarcin Wojtas rcvd_bytes += rx_bytes; 2498dc35a10fSMarcin Wojtas 2499dc35a10fSMarcin Wojtas /* Linux processing */ 2500dc35a10fSMarcin Wojtas skb_reserve(skb, MVNETA_MH_SIZE + NET_SKB_PAD); 2501dc35a10fSMarcin Wojtas skb_put(skb, rx_bytes); 2502dc35a10fSMarcin Wojtas 2503dc35a10fSMarcin Wojtas skb->protocol = eth_type_trans(skb, dev); 2504dc35a10fSMarcin Wojtas 2505dc35a10fSMarcin Wojtas mvneta_rx_csum(pp, rx_status, skb); 2506dc35a10fSMarcin Wojtas 25077a86f05fSAndrew Lunn napi_gro_receive(napi, skb); 2508dc35a10fSMarcin Wojtas } 2509dc35a10fSMarcin Wojtas 251069de66fcSLorenzo Bianconi if (rcvd_pkts) { 251169de66fcSLorenzo Bianconi struct mvneta_pcpu_stats *stats = this_cpu_ptr(pp->stats); 251269de66fcSLorenzo Bianconi 251369de66fcSLorenzo Bianconi u64_stats_update_begin(&stats->syncp); 2514320d5441SLorenzo Bianconi stats->es.ps.rx_packets += rcvd_pkts; 2515320d5441SLorenzo Bianconi stats->es.ps.rx_bytes += rcvd_bytes; 251669de66fcSLorenzo Bianconi u64_stats_update_end(&stats->syncp); 251769de66fcSLorenzo Bianconi } 2518dc35a10fSMarcin Wojtas 2519dc35a10fSMarcin Wojtas /* Update rxq management counters */ 2520dc35a10fSMarcin Wojtas mvneta_rxq_desc_num_update(pp, rxq, rx_done, rx_done); 2521dc35a10fSMarcin Wojtas 2522dc35a10fSMarcin Wojtas return rx_done; 2523dc35a10fSMarcin Wojtas } 2524dc35a10fSMarcin Wojtas 25252adb719dSEzequiel Garcia static inline void 25262adb719dSEzequiel Garcia mvneta_tso_put_hdr(struct sk_buff *skb, 25272adb719dSEzequiel Garcia struct mvneta_port *pp, struct mvneta_tx_queue *txq) 25282adb719dSEzequiel Garcia { 25292adb719dSEzequiel Garcia int hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb); 25309e58c8b4SLorenzo Bianconi struct mvneta_tx_buf *buf = &txq->buf[txq->txq_put_index]; 25319e58c8b4SLorenzo Bianconi struct mvneta_tx_desc *tx_desc; 25322adb719dSEzequiel Garcia 25332adb719dSEzequiel Garcia tx_desc = mvneta_txq_next_desc_get(txq); 25342adb719dSEzequiel Garcia tx_desc->data_size = hdr_len; 25352adb719dSEzequiel Garcia tx_desc->command = mvneta_skb_tx_csum(pp, skb); 25362adb719dSEzequiel Garcia tx_desc->command |= MVNETA_TXD_F_DESC; 25372adb719dSEzequiel Garcia tx_desc->buf_phys_addr = txq->tso_hdrs_phys + 25382adb719dSEzequiel Garcia txq->txq_put_index * TSO_HEADER_SIZE; 25399e58c8b4SLorenzo Bianconi buf->type = MVNETA_TYPE_SKB; 25409e58c8b4SLorenzo Bianconi buf->skb = NULL; 25419e58c8b4SLorenzo Bianconi 25422adb719dSEzequiel Garcia mvneta_txq_inc_put(txq); 25432adb719dSEzequiel Garcia } 25442adb719dSEzequiel Garcia 25452adb719dSEzequiel Garcia static inline int 25462adb719dSEzequiel Garcia mvneta_tso_put_data(struct net_device *dev, struct mvneta_tx_queue *txq, 25472adb719dSEzequiel Garcia struct sk_buff *skb, char *data, int size, 25482adb719dSEzequiel Garcia bool last_tcp, bool is_last) 25492adb719dSEzequiel Garcia { 25509e58c8b4SLorenzo Bianconi struct mvneta_tx_buf *buf = &txq->buf[txq->txq_put_index]; 25512adb719dSEzequiel Garcia struct mvneta_tx_desc *tx_desc; 25522adb719dSEzequiel Garcia 25532adb719dSEzequiel Garcia tx_desc = mvneta_txq_next_desc_get(txq); 25542adb719dSEzequiel Garcia tx_desc->data_size = size; 25552adb719dSEzequiel Garcia tx_desc->buf_phys_addr = dma_map_single(dev->dev.parent, data, 25562adb719dSEzequiel Garcia size, DMA_TO_DEVICE); 25572adb719dSEzequiel Garcia if (unlikely(dma_mapping_error(dev->dev.parent, 25582adb719dSEzequiel Garcia tx_desc->buf_phys_addr))) { 25592adb719dSEzequiel Garcia mvneta_txq_desc_put(txq); 25602adb719dSEzequiel Garcia return -ENOMEM; 25612adb719dSEzequiel Garcia } 25622adb719dSEzequiel Garcia 25632adb719dSEzequiel Garcia tx_desc->command = 0; 25649e58c8b4SLorenzo Bianconi buf->type = MVNETA_TYPE_SKB; 25659e58c8b4SLorenzo Bianconi buf->skb = NULL; 25662adb719dSEzequiel Garcia 25672adb719dSEzequiel Garcia if (last_tcp) { 25682adb719dSEzequiel Garcia /* last descriptor in the TCP packet */ 25692adb719dSEzequiel Garcia tx_desc->command = MVNETA_TXD_L_DESC; 25702adb719dSEzequiel Garcia 25712adb719dSEzequiel Garcia /* last descriptor in SKB */ 25722adb719dSEzequiel Garcia if (is_last) 25739e58c8b4SLorenzo Bianconi buf->skb = skb; 25742adb719dSEzequiel Garcia } 25752adb719dSEzequiel Garcia mvneta_txq_inc_put(txq); 25762adb719dSEzequiel Garcia return 0; 25772adb719dSEzequiel Garcia } 25782adb719dSEzequiel Garcia 25792adb719dSEzequiel Garcia static int mvneta_tx_tso(struct sk_buff *skb, struct net_device *dev, 25802adb719dSEzequiel Garcia struct mvneta_tx_queue *txq) 25812adb719dSEzequiel Garcia { 25822adb719dSEzequiel Garcia int total_len, data_left; 25832adb719dSEzequiel Garcia int desc_count = 0; 25842adb719dSEzequiel Garcia struct mvneta_port *pp = netdev_priv(dev); 25852adb719dSEzequiel Garcia struct tso_t tso; 25862adb719dSEzequiel Garcia int hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb); 25872adb719dSEzequiel Garcia int i; 25882adb719dSEzequiel Garcia 25892adb719dSEzequiel Garcia /* Count needed descriptors */ 25902adb719dSEzequiel Garcia if ((txq->count + tso_count_descs(skb)) >= txq->size) 25912adb719dSEzequiel Garcia return 0; 25922adb719dSEzequiel Garcia 25932adb719dSEzequiel Garcia if (skb_headlen(skb) < (skb_transport_offset(skb) + tcp_hdrlen(skb))) { 25942adb719dSEzequiel Garcia pr_info("*** Is this even possible???!?!?\n"); 25952adb719dSEzequiel Garcia return 0; 25962adb719dSEzequiel Garcia } 25972adb719dSEzequiel Garcia 25982adb719dSEzequiel Garcia /* Initialize the TSO handler, and prepare the first payload */ 25992adb719dSEzequiel Garcia tso_start(skb, &tso); 26002adb719dSEzequiel Garcia 26012adb719dSEzequiel Garcia total_len = skb->len - hdr_len; 26022adb719dSEzequiel Garcia while (total_len > 0) { 26032adb719dSEzequiel Garcia char *hdr; 26042adb719dSEzequiel Garcia 26052adb719dSEzequiel Garcia data_left = min_t(int, skb_shinfo(skb)->gso_size, total_len); 26062adb719dSEzequiel Garcia total_len -= data_left; 26072adb719dSEzequiel Garcia desc_count++; 26082adb719dSEzequiel Garcia 26092adb719dSEzequiel Garcia /* prepare packet headers: MAC + IP + TCP */ 26102adb719dSEzequiel Garcia hdr = txq->tso_hdrs + txq->txq_put_index * TSO_HEADER_SIZE; 26112adb719dSEzequiel Garcia tso_build_hdr(skb, hdr, &tso, data_left, total_len == 0); 26122adb719dSEzequiel Garcia 26132adb719dSEzequiel Garcia mvneta_tso_put_hdr(skb, pp, txq); 26142adb719dSEzequiel Garcia 26152adb719dSEzequiel Garcia while (data_left > 0) { 26162adb719dSEzequiel Garcia int size; 26172adb719dSEzequiel Garcia desc_count++; 26182adb719dSEzequiel Garcia 26192adb719dSEzequiel Garcia size = min_t(int, tso.size, data_left); 26202adb719dSEzequiel Garcia 26212adb719dSEzequiel Garcia if (mvneta_tso_put_data(dev, txq, skb, 26222adb719dSEzequiel Garcia tso.data, size, 26232adb719dSEzequiel Garcia size == data_left, 26242adb719dSEzequiel Garcia total_len == 0)) 26252adb719dSEzequiel Garcia goto err_release; 26262adb719dSEzequiel Garcia data_left -= size; 26272adb719dSEzequiel Garcia 26282adb719dSEzequiel Garcia tso_build_data(skb, &tso, size); 26292adb719dSEzequiel Garcia } 26302adb719dSEzequiel Garcia } 26312adb719dSEzequiel Garcia 26322adb719dSEzequiel Garcia return desc_count; 26332adb719dSEzequiel Garcia 26342adb719dSEzequiel Garcia err_release: 26352adb719dSEzequiel Garcia /* Release all used data descriptors; header descriptors must not 26362adb719dSEzequiel Garcia * be DMA-unmapped. 26372adb719dSEzequiel Garcia */ 26382adb719dSEzequiel Garcia for (i = desc_count - 1; i >= 0; i--) { 26392adb719dSEzequiel Garcia struct mvneta_tx_desc *tx_desc = txq->descs + i; 26402e3173a3SEzequiel Garcia if (!IS_TSO_HEADER(txq, tx_desc->buf_phys_addr)) 26412adb719dSEzequiel Garcia dma_unmap_single(pp->dev->dev.parent, 26422adb719dSEzequiel Garcia tx_desc->buf_phys_addr, 26432adb719dSEzequiel Garcia tx_desc->data_size, 26442adb719dSEzequiel Garcia DMA_TO_DEVICE); 26452adb719dSEzequiel Garcia mvneta_txq_desc_put(txq); 26462adb719dSEzequiel Garcia } 26472adb719dSEzequiel Garcia return 0; 26482adb719dSEzequiel Garcia } 26492adb719dSEzequiel Garcia 2650c5aff182SThomas Petazzoni /* Handle tx fragmentation processing */ 2651c5aff182SThomas Petazzoni static int mvneta_tx_frag_process(struct mvneta_port *pp, struct sk_buff *skb, 2652c5aff182SThomas Petazzoni struct mvneta_tx_queue *txq) 2653c5aff182SThomas Petazzoni { 2654c5aff182SThomas Petazzoni struct mvneta_tx_desc *tx_desc; 26553d4ea02fSEzequiel Garcia int i, nr_frags = skb_shinfo(skb)->nr_frags; 2656c5aff182SThomas Petazzoni 26573d4ea02fSEzequiel Garcia for (i = 0; i < nr_frags; i++) { 26589e58c8b4SLorenzo Bianconi struct mvneta_tx_buf *buf = &txq->buf[txq->txq_put_index]; 2659c5aff182SThomas Petazzoni skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 2660d7840976SMatthew Wilcox (Oracle) void *addr = skb_frag_address(frag); 2661c5aff182SThomas Petazzoni 2662c5aff182SThomas Petazzoni tx_desc = mvneta_txq_next_desc_get(txq); 2663d7840976SMatthew Wilcox (Oracle) tx_desc->data_size = skb_frag_size(frag); 2664c5aff182SThomas Petazzoni 2665c5aff182SThomas Petazzoni tx_desc->buf_phys_addr = 2666c5aff182SThomas Petazzoni dma_map_single(pp->dev->dev.parent, addr, 2667c5aff182SThomas Petazzoni tx_desc->data_size, DMA_TO_DEVICE); 2668c5aff182SThomas Petazzoni 2669c5aff182SThomas Petazzoni if (dma_mapping_error(pp->dev->dev.parent, 2670c5aff182SThomas Petazzoni tx_desc->buf_phys_addr)) { 2671c5aff182SThomas Petazzoni mvneta_txq_desc_put(txq); 2672c5aff182SThomas Petazzoni goto error; 2673c5aff182SThomas Petazzoni } 2674c5aff182SThomas Petazzoni 26753d4ea02fSEzequiel Garcia if (i == nr_frags - 1) { 2676c5aff182SThomas Petazzoni /* Last descriptor */ 2677c5aff182SThomas Petazzoni tx_desc->command = MVNETA_TXD_L_DESC | MVNETA_TXD_Z_PAD; 26789e58c8b4SLorenzo Bianconi buf->skb = skb; 2679c5aff182SThomas Petazzoni } else { 2680c5aff182SThomas Petazzoni /* Descriptor in the middle: Not First, Not Last */ 2681c5aff182SThomas Petazzoni tx_desc->command = 0; 26829e58c8b4SLorenzo Bianconi buf->skb = NULL; 2683c5aff182SThomas Petazzoni } 26849e58c8b4SLorenzo Bianconi buf->type = MVNETA_TYPE_SKB; 26853d4ea02fSEzequiel Garcia mvneta_txq_inc_put(txq); 2686c5aff182SThomas Petazzoni } 2687c5aff182SThomas Petazzoni 2688c5aff182SThomas Petazzoni return 0; 2689c5aff182SThomas Petazzoni 2690c5aff182SThomas Petazzoni error: 2691c5aff182SThomas Petazzoni /* Release all descriptors that were used to map fragments of 26926a20c175SThomas Petazzoni * this packet, as well as the corresponding DMA mappings 26936a20c175SThomas Petazzoni */ 2694c5aff182SThomas Petazzoni for (i = i - 1; i >= 0; i--) { 2695c5aff182SThomas Petazzoni tx_desc = txq->descs + i; 2696c5aff182SThomas Petazzoni dma_unmap_single(pp->dev->dev.parent, 2697c5aff182SThomas Petazzoni tx_desc->buf_phys_addr, 2698c5aff182SThomas Petazzoni tx_desc->data_size, 2699c5aff182SThomas Petazzoni DMA_TO_DEVICE); 2700c5aff182SThomas Petazzoni mvneta_txq_desc_put(txq); 2701c5aff182SThomas Petazzoni } 2702c5aff182SThomas Petazzoni 2703c5aff182SThomas Petazzoni return -ENOMEM; 2704c5aff182SThomas Petazzoni } 2705c5aff182SThomas Petazzoni 2706c5aff182SThomas Petazzoni /* Main tx processing */ 2707f03508ceSYueHaibing static netdev_tx_t mvneta_tx(struct sk_buff *skb, struct net_device *dev) 2708c5aff182SThomas Petazzoni { 2709c5aff182SThomas Petazzoni struct mvneta_port *pp = netdev_priv(dev); 2710ee40a116SWilly Tarreau u16 txq_id = skb_get_queue_mapping(skb); 2711ee40a116SWilly Tarreau struct mvneta_tx_queue *txq = &pp->txqs[txq_id]; 27129e58c8b4SLorenzo Bianconi struct mvneta_tx_buf *buf = &txq->buf[txq->txq_put_index]; 2713c5aff182SThomas Petazzoni struct mvneta_tx_desc *tx_desc; 27145f478b41SEric Dumazet int len = skb->len; 2715c5aff182SThomas Petazzoni int frags = 0; 2716c5aff182SThomas Petazzoni u32 tx_cmd; 2717c5aff182SThomas Petazzoni 2718c5aff182SThomas Petazzoni if (!netif_running(dev)) 2719c5aff182SThomas Petazzoni goto out; 2720c5aff182SThomas Petazzoni 27212adb719dSEzequiel Garcia if (skb_is_gso(skb)) { 27222adb719dSEzequiel Garcia frags = mvneta_tx_tso(skb, dev, txq); 27232adb719dSEzequiel Garcia goto out; 27242adb719dSEzequiel Garcia } 27252adb719dSEzequiel Garcia 2726c5aff182SThomas Petazzoni frags = skb_shinfo(skb)->nr_frags + 1; 2727c5aff182SThomas Petazzoni 2728c5aff182SThomas Petazzoni /* Get a descriptor for the first part of the packet */ 2729c5aff182SThomas Petazzoni tx_desc = mvneta_txq_next_desc_get(txq); 2730c5aff182SThomas Petazzoni 2731c5aff182SThomas Petazzoni tx_cmd = mvneta_skb_tx_csum(pp, skb); 2732c5aff182SThomas Petazzoni 2733c5aff182SThomas Petazzoni tx_desc->data_size = skb_headlen(skb); 2734c5aff182SThomas Petazzoni 2735c5aff182SThomas Petazzoni tx_desc->buf_phys_addr = dma_map_single(dev->dev.parent, skb->data, 2736c5aff182SThomas Petazzoni tx_desc->data_size, 2737c5aff182SThomas Petazzoni DMA_TO_DEVICE); 2738c5aff182SThomas Petazzoni if (unlikely(dma_mapping_error(dev->dev.parent, 2739c5aff182SThomas Petazzoni tx_desc->buf_phys_addr))) { 2740c5aff182SThomas Petazzoni mvneta_txq_desc_put(txq); 2741c5aff182SThomas Petazzoni frags = 0; 2742c5aff182SThomas Petazzoni goto out; 2743c5aff182SThomas Petazzoni } 2744c5aff182SThomas Petazzoni 27459e58c8b4SLorenzo Bianconi buf->type = MVNETA_TYPE_SKB; 2746c5aff182SThomas Petazzoni if (frags == 1) { 2747c5aff182SThomas Petazzoni /* First and Last descriptor */ 2748c5aff182SThomas Petazzoni tx_cmd |= MVNETA_TXD_FLZ_DESC; 2749c5aff182SThomas Petazzoni tx_desc->command = tx_cmd; 27509e58c8b4SLorenzo Bianconi buf->skb = skb; 2751c5aff182SThomas Petazzoni mvneta_txq_inc_put(txq); 2752c5aff182SThomas Petazzoni } else { 2753c5aff182SThomas Petazzoni /* First but not Last */ 2754c5aff182SThomas Petazzoni tx_cmd |= MVNETA_TXD_F_DESC; 27559e58c8b4SLorenzo Bianconi buf->skb = NULL; 2756c5aff182SThomas Petazzoni mvneta_txq_inc_put(txq); 2757c5aff182SThomas Petazzoni tx_desc->command = tx_cmd; 2758c5aff182SThomas Petazzoni /* Continue with other skb fragments */ 2759c5aff182SThomas Petazzoni if (mvneta_tx_frag_process(pp, skb, txq)) { 2760c5aff182SThomas Petazzoni dma_unmap_single(dev->dev.parent, 2761c5aff182SThomas Petazzoni tx_desc->buf_phys_addr, 2762c5aff182SThomas Petazzoni tx_desc->data_size, 2763c5aff182SThomas Petazzoni DMA_TO_DEVICE); 2764c5aff182SThomas Petazzoni mvneta_txq_desc_put(txq); 2765c5aff182SThomas Petazzoni frags = 0; 2766c5aff182SThomas Petazzoni goto out; 2767c5aff182SThomas Petazzoni } 2768c5aff182SThomas Petazzoni } 2769c5aff182SThomas Petazzoni 2770e19d2ddaSEzequiel Garcia out: 2771e19d2ddaSEzequiel Garcia if (frags > 0) { 2772e19d2ddaSEzequiel Garcia struct netdev_queue *nq = netdev_get_tx_queue(dev, txq_id); 277369de66fcSLorenzo Bianconi struct mvneta_pcpu_stats *stats = this_cpu_ptr(pp->stats); 2774e19d2ddaSEzequiel Garcia 2775a29b6235SMarcin Wojtas netdev_tx_sent_queue(nq, len); 2776a29b6235SMarcin Wojtas 2777c5aff182SThomas Petazzoni txq->count += frags; 27788eef5f97SEzequiel Garcia if (txq->count >= txq->tx_stop_threshold) 2779c5aff182SThomas Petazzoni netif_tx_stop_queue(nq); 2780c5aff182SThomas Petazzoni 27816b16f9eeSFlorian Westphal if (!netdev_xmit_more() || netif_xmit_stopped(nq) || 27822a90f7e1SSimon Guinot txq->pending + frags > MVNETA_TXQ_DEC_SENT_MASK) 27832a90f7e1SSimon Guinot mvneta_txq_pend_desc_add(pp, txq, frags); 27842a90f7e1SSimon Guinot else 27852a90f7e1SSimon Guinot txq->pending += frags; 27862a90f7e1SSimon Guinot 278769de66fcSLorenzo Bianconi u64_stats_update_begin(&stats->syncp); 2788320d5441SLorenzo Bianconi stats->es.ps.tx_bytes += len; 2789320d5441SLorenzo Bianconi stats->es.ps.tx_packets++; 279069de66fcSLorenzo Bianconi u64_stats_update_end(&stats->syncp); 2791c5aff182SThomas Petazzoni } else { 2792c5aff182SThomas Petazzoni dev->stats.tx_dropped++; 2793c5aff182SThomas Petazzoni dev_kfree_skb_any(skb); 2794c5aff182SThomas Petazzoni } 2795c5aff182SThomas Petazzoni 2796c5aff182SThomas Petazzoni return NETDEV_TX_OK; 2797c5aff182SThomas Petazzoni } 2798c5aff182SThomas Petazzoni 2799c5aff182SThomas Petazzoni 2800c5aff182SThomas Petazzoni /* Free tx resources, when resetting a port */ 2801c5aff182SThomas Petazzoni static void mvneta_txq_done_force(struct mvneta_port *pp, 2802c5aff182SThomas Petazzoni struct mvneta_tx_queue *txq) 2803c5aff182SThomas Petazzoni 2804c5aff182SThomas Petazzoni { 2805a29b6235SMarcin Wojtas struct netdev_queue *nq = netdev_get_tx_queue(pp->dev, txq->id); 2806c5aff182SThomas Petazzoni int tx_done = txq->count; 2807c5aff182SThomas Petazzoni 2808a29b6235SMarcin Wojtas mvneta_txq_bufs_free(pp, txq, tx_done, nq); 2809c5aff182SThomas Petazzoni 2810c5aff182SThomas Petazzoni /* reset txq */ 2811c5aff182SThomas Petazzoni txq->count = 0; 2812c5aff182SThomas Petazzoni txq->txq_put_index = 0; 2813c5aff182SThomas Petazzoni txq->txq_get_index = 0; 2814c5aff182SThomas Petazzoni } 2815c5aff182SThomas Petazzoni 28166c498974Swilly tarreau /* Handle tx done - called in softirq context. The <cause_tx_done> argument 28176c498974Swilly tarreau * must be a valid cause according to MVNETA_TXQ_INTR_MASK_ALL. 28186c498974Swilly tarreau */ 28190713a86aSArnaud Ebalard static void mvneta_tx_done_gbe(struct mvneta_port *pp, u32 cause_tx_done) 2820c5aff182SThomas Petazzoni { 2821c5aff182SThomas Petazzoni struct mvneta_tx_queue *txq; 2822c5aff182SThomas Petazzoni struct netdev_queue *nq; 2823bd9f1ee3SJisheng Zhang int cpu = smp_processor_id(); 2824c5aff182SThomas Petazzoni 28256c498974Swilly tarreau while (cause_tx_done) { 2826c5aff182SThomas Petazzoni txq = mvneta_tx_done_policy(pp, cause_tx_done); 2827c5aff182SThomas Petazzoni 2828c5aff182SThomas Petazzoni nq = netdev_get_tx_queue(pp->dev, txq->id); 2829bd9f1ee3SJisheng Zhang __netif_tx_lock(nq, cpu); 2830c5aff182SThomas Petazzoni 28310713a86aSArnaud Ebalard if (txq->count) 28320713a86aSArnaud Ebalard mvneta_txq_done(pp, txq); 2833c5aff182SThomas Petazzoni 2834c5aff182SThomas Petazzoni __netif_tx_unlock(nq); 2835c5aff182SThomas Petazzoni cause_tx_done &= ~((1 << txq->id)); 2836c5aff182SThomas Petazzoni } 2837c5aff182SThomas Petazzoni } 2838c5aff182SThomas Petazzoni 28396a20c175SThomas Petazzoni /* Compute crc8 of the specified address, using a unique algorithm , 2840c5aff182SThomas Petazzoni * according to hw spec, different than generic crc8 algorithm 2841c5aff182SThomas Petazzoni */ 2842c5aff182SThomas Petazzoni static int mvneta_addr_crc(unsigned char *addr) 2843c5aff182SThomas Petazzoni { 2844c5aff182SThomas Petazzoni int crc = 0; 2845c5aff182SThomas Petazzoni int i; 2846c5aff182SThomas Petazzoni 2847c5aff182SThomas Petazzoni for (i = 0; i < ETH_ALEN; i++) { 2848c5aff182SThomas Petazzoni int j; 2849c5aff182SThomas Petazzoni 2850c5aff182SThomas Petazzoni crc = (crc ^ addr[i]) << 8; 2851c5aff182SThomas Petazzoni for (j = 7; j >= 0; j--) { 2852c5aff182SThomas Petazzoni if (crc & (0x100 << j)) 2853c5aff182SThomas Petazzoni crc ^= 0x107 << j; 2854c5aff182SThomas Petazzoni } 2855c5aff182SThomas Petazzoni } 2856c5aff182SThomas Petazzoni 2857c5aff182SThomas Petazzoni return crc; 2858c5aff182SThomas Petazzoni } 2859c5aff182SThomas Petazzoni 2860c5aff182SThomas Petazzoni /* This method controls the net device special MAC multicast support. 2861c5aff182SThomas Petazzoni * The Special Multicast Table for MAC addresses supports MAC of the form 2862c5aff182SThomas Petazzoni * 0x01-00-5E-00-00-XX (where XX is between 0x00 and 0xFF). 2863c5aff182SThomas Petazzoni * The MAC DA[7:0] bits are used as a pointer to the Special Multicast 2864c5aff182SThomas Petazzoni * Table entries in the DA-Filter table. This method set the Special 2865c5aff182SThomas Petazzoni * Multicast Table appropriate entry. 2866c5aff182SThomas Petazzoni */ 2867c5aff182SThomas Petazzoni static void mvneta_set_special_mcast_addr(struct mvneta_port *pp, 2868c5aff182SThomas Petazzoni unsigned char last_byte, 2869c5aff182SThomas Petazzoni int queue) 2870c5aff182SThomas Petazzoni { 2871c5aff182SThomas Petazzoni unsigned int smc_table_reg; 2872c5aff182SThomas Petazzoni unsigned int tbl_offset; 2873c5aff182SThomas Petazzoni unsigned int reg_offset; 2874c5aff182SThomas Petazzoni 2875c5aff182SThomas Petazzoni /* Register offset from SMC table base */ 2876c5aff182SThomas Petazzoni tbl_offset = (last_byte / 4); 2877c5aff182SThomas Petazzoni /* Entry offset within the above reg */ 2878c5aff182SThomas Petazzoni reg_offset = last_byte % 4; 2879c5aff182SThomas Petazzoni 2880c5aff182SThomas Petazzoni smc_table_reg = mvreg_read(pp, (MVNETA_DA_FILT_SPEC_MCAST 2881c5aff182SThomas Petazzoni + tbl_offset * 4)); 2882c5aff182SThomas Petazzoni 2883c5aff182SThomas Petazzoni if (queue == -1) 2884c5aff182SThomas Petazzoni smc_table_reg &= ~(0xff << (8 * reg_offset)); 2885c5aff182SThomas Petazzoni else { 2886c5aff182SThomas Petazzoni smc_table_reg &= ~(0xff << (8 * reg_offset)); 2887c5aff182SThomas Petazzoni smc_table_reg |= ((0x01 | (queue << 1)) << (8 * reg_offset)); 2888c5aff182SThomas Petazzoni } 2889c5aff182SThomas Petazzoni 2890c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_DA_FILT_SPEC_MCAST + tbl_offset * 4, 2891c5aff182SThomas Petazzoni smc_table_reg); 2892c5aff182SThomas Petazzoni } 2893c5aff182SThomas Petazzoni 2894c5aff182SThomas Petazzoni /* This method controls the network device Other MAC multicast support. 2895c5aff182SThomas Petazzoni * The Other Multicast Table is used for multicast of another type. 2896c5aff182SThomas Petazzoni * A CRC-8 is used as an index to the Other Multicast Table entries 2897c5aff182SThomas Petazzoni * in the DA-Filter table. 2898c5aff182SThomas Petazzoni * The method gets the CRC-8 value from the calling routine and 2899c5aff182SThomas Petazzoni * sets the Other Multicast Table appropriate entry according to the 2900c5aff182SThomas Petazzoni * specified CRC-8 . 2901c5aff182SThomas Petazzoni */ 2902c5aff182SThomas Petazzoni static void mvneta_set_other_mcast_addr(struct mvneta_port *pp, 2903c5aff182SThomas Petazzoni unsigned char crc8, 2904c5aff182SThomas Petazzoni int queue) 2905c5aff182SThomas Petazzoni { 2906c5aff182SThomas Petazzoni unsigned int omc_table_reg; 2907c5aff182SThomas Petazzoni unsigned int tbl_offset; 2908c5aff182SThomas Petazzoni unsigned int reg_offset; 2909c5aff182SThomas Petazzoni 2910c5aff182SThomas Petazzoni tbl_offset = (crc8 / 4) * 4; /* Register offset from OMC table base */ 2911c5aff182SThomas Petazzoni reg_offset = crc8 % 4; /* Entry offset within the above reg */ 2912c5aff182SThomas Petazzoni 2913c5aff182SThomas Petazzoni omc_table_reg = mvreg_read(pp, MVNETA_DA_FILT_OTH_MCAST + tbl_offset); 2914c5aff182SThomas Petazzoni 2915c5aff182SThomas Petazzoni if (queue == -1) { 2916c5aff182SThomas Petazzoni /* Clear accepts frame bit at specified Other DA table entry */ 2917c5aff182SThomas Petazzoni omc_table_reg &= ~(0xff << (8 * reg_offset)); 2918c5aff182SThomas Petazzoni } else { 2919c5aff182SThomas Petazzoni omc_table_reg &= ~(0xff << (8 * reg_offset)); 2920c5aff182SThomas Petazzoni omc_table_reg |= ((0x01 | (queue << 1)) << (8 * reg_offset)); 2921c5aff182SThomas Petazzoni } 2922c5aff182SThomas Petazzoni 2923c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_DA_FILT_OTH_MCAST + tbl_offset, omc_table_reg); 2924c5aff182SThomas Petazzoni } 2925c5aff182SThomas Petazzoni 2926c5aff182SThomas Petazzoni /* The network device supports multicast using two tables: 2927c5aff182SThomas Petazzoni * 1) Special Multicast Table for MAC addresses of the form 2928c5aff182SThomas Petazzoni * 0x01-00-5E-00-00-XX (where XX is between 0x00 and 0xFF). 2929c5aff182SThomas Petazzoni * The MAC DA[7:0] bits are used as a pointer to the Special Multicast 2930c5aff182SThomas Petazzoni * Table entries in the DA-Filter table. 2931c5aff182SThomas Petazzoni * 2) Other Multicast Table for multicast of another type. A CRC-8 value 2932c5aff182SThomas Petazzoni * is used as an index to the Other Multicast Table entries in the 2933c5aff182SThomas Petazzoni * DA-Filter table. 2934c5aff182SThomas Petazzoni */ 2935c5aff182SThomas Petazzoni static int mvneta_mcast_addr_set(struct mvneta_port *pp, unsigned char *p_addr, 2936c5aff182SThomas Petazzoni int queue) 2937c5aff182SThomas Petazzoni { 2938c5aff182SThomas Petazzoni unsigned char crc_result = 0; 2939c5aff182SThomas Petazzoni 2940c5aff182SThomas Petazzoni if (memcmp(p_addr, "\x01\x00\x5e\x00\x00", 5) == 0) { 2941c5aff182SThomas Petazzoni mvneta_set_special_mcast_addr(pp, p_addr[5], queue); 2942c5aff182SThomas Petazzoni return 0; 2943c5aff182SThomas Petazzoni } 2944c5aff182SThomas Petazzoni 2945c5aff182SThomas Petazzoni crc_result = mvneta_addr_crc(p_addr); 2946c5aff182SThomas Petazzoni if (queue == -1) { 2947c5aff182SThomas Petazzoni if (pp->mcast_count[crc_result] == 0) { 2948c5aff182SThomas Petazzoni netdev_info(pp->dev, "No valid Mcast for crc8=0x%02x\n", 2949c5aff182SThomas Petazzoni crc_result); 2950c5aff182SThomas Petazzoni return -EINVAL; 2951c5aff182SThomas Petazzoni } 2952c5aff182SThomas Petazzoni 2953c5aff182SThomas Petazzoni pp->mcast_count[crc_result]--; 2954c5aff182SThomas Petazzoni if (pp->mcast_count[crc_result] != 0) { 2955c5aff182SThomas Petazzoni netdev_info(pp->dev, 2956c5aff182SThomas Petazzoni "After delete there are %d valid Mcast for crc8=0x%02x\n", 2957c5aff182SThomas Petazzoni pp->mcast_count[crc_result], crc_result); 2958c5aff182SThomas Petazzoni return -EINVAL; 2959c5aff182SThomas Petazzoni } 2960c5aff182SThomas Petazzoni } else 2961c5aff182SThomas Petazzoni pp->mcast_count[crc_result]++; 2962c5aff182SThomas Petazzoni 2963c5aff182SThomas Petazzoni mvneta_set_other_mcast_addr(pp, crc_result, queue); 2964c5aff182SThomas Petazzoni 2965c5aff182SThomas Petazzoni return 0; 2966c5aff182SThomas Petazzoni } 2967c5aff182SThomas Petazzoni 2968c5aff182SThomas Petazzoni /* Configure Fitering mode of Ethernet port */ 2969c5aff182SThomas Petazzoni static void mvneta_rx_unicast_promisc_set(struct mvneta_port *pp, 2970c5aff182SThomas Petazzoni int is_promisc) 2971c5aff182SThomas Petazzoni { 2972c5aff182SThomas Petazzoni u32 port_cfg_reg, val; 2973c5aff182SThomas Petazzoni 2974c5aff182SThomas Petazzoni port_cfg_reg = mvreg_read(pp, MVNETA_PORT_CONFIG); 2975c5aff182SThomas Petazzoni 2976c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_TYPE_PRIO); 2977c5aff182SThomas Petazzoni 2978c5aff182SThomas Petazzoni /* Set / Clear UPM bit in port configuration register */ 2979c5aff182SThomas Petazzoni if (is_promisc) { 2980c5aff182SThomas Petazzoni /* Accept all Unicast addresses */ 2981c5aff182SThomas Petazzoni port_cfg_reg |= MVNETA_UNI_PROMISC_MODE; 2982c5aff182SThomas Petazzoni val |= MVNETA_FORCE_UNI; 2983c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_MAC_ADDR_LOW, 0xffff); 2984c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_MAC_ADDR_HIGH, 0xffffffff); 2985c5aff182SThomas Petazzoni } else { 2986c5aff182SThomas Petazzoni /* Reject all Unicast addresses */ 2987c5aff182SThomas Petazzoni port_cfg_reg &= ~MVNETA_UNI_PROMISC_MODE; 2988c5aff182SThomas Petazzoni val &= ~MVNETA_FORCE_UNI; 2989c5aff182SThomas Petazzoni } 2990c5aff182SThomas Petazzoni 2991c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_PORT_CONFIG, port_cfg_reg); 2992c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_TYPE_PRIO, val); 2993c5aff182SThomas Petazzoni } 2994c5aff182SThomas Petazzoni 2995c5aff182SThomas Petazzoni /* register unicast and multicast addresses */ 2996c5aff182SThomas Petazzoni static void mvneta_set_rx_mode(struct net_device *dev) 2997c5aff182SThomas Petazzoni { 2998c5aff182SThomas Petazzoni struct mvneta_port *pp = netdev_priv(dev); 2999c5aff182SThomas Petazzoni struct netdev_hw_addr *ha; 3000c5aff182SThomas Petazzoni 3001c5aff182SThomas Petazzoni if (dev->flags & IFF_PROMISC) { 3002c5aff182SThomas Petazzoni /* Accept all: Multicast + Unicast */ 3003c5aff182SThomas Petazzoni mvneta_rx_unicast_promisc_set(pp, 1); 300490b74c01SGregory CLEMENT mvneta_set_ucast_table(pp, pp->rxq_def); 300590b74c01SGregory CLEMENT mvneta_set_special_mcast_table(pp, pp->rxq_def); 300690b74c01SGregory CLEMENT mvneta_set_other_mcast_table(pp, pp->rxq_def); 3007c5aff182SThomas Petazzoni } else { 3008c5aff182SThomas Petazzoni /* Accept single Unicast */ 3009c5aff182SThomas Petazzoni mvneta_rx_unicast_promisc_set(pp, 0); 3010c5aff182SThomas Petazzoni mvneta_set_ucast_table(pp, -1); 301190b74c01SGregory CLEMENT mvneta_mac_addr_set(pp, dev->dev_addr, pp->rxq_def); 3012c5aff182SThomas Petazzoni 3013c5aff182SThomas Petazzoni if (dev->flags & IFF_ALLMULTI) { 3014c5aff182SThomas Petazzoni /* Accept all multicast */ 301590b74c01SGregory CLEMENT mvneta_set_special_mcast_table(pp, pp->rxq_def); 301690b74c01SGregory CLEMENT mvneta_set_other_mcast_table(pp, pp->rxq_def); 3017c5aff182SThomas Petazzoni } else { 3018c5aff182SThomas Petazzoni /* Accept only initialized multicast */ 3019c5aff182SThomas Petazzoni mvneta_set_special_mcast_table(pp, -1); 3020c5aff182SThomas Petazzoni mvneta_set_other_mcast_table(pp, -1); 3021c5aff182SThomas Petazzoni 3022c5aff182SThomas Petazzoni if (!netdev_mc_empty(dev)) { 3023c5aff182SThomas Petazzoni netdev_for_each_mc_addr(ha, dev) { 3024c5aff182SThomas Petazzoni mvneta_mcast_addr_set(pp, ha->addr, 302590b74c01SGregory CLEMENT pp->rxq_def); 3026c5aff182SThomas Petazzoni } 3027c5aff182SThomas Petazzoni } 3028c5aff182SThomas Petazzoni } 3029c5aff182SThomas Petazzoni } 3030c5aff182SThomas Petazzoni } 3031c5aff182SThomas Petazzoni 3032c5aff182SThomas Petazzoni /* Interrupt handling - the callback for request_irq() */ 3033c5aff182SThomas Petazzoni static irqreturn_t mvneta_isr(int irq, void *dev_id) 3034c5aff182SThomas Petazzoni { 30352636ac3cSMarcin Wojtas struct mvneta_port *pp = (struct mvneta_port *)dev_id; 30362636ac3cSMarcin Wojtas 30372636ac3cSMarcin Wojtas mvreg_write(pp, MVNETA_INTR_NEW_MASK, 0); 30382636ac3cSMarcin Wojtas napi_schedule(&pp->napi); 30392636ac3cSMarcin Wojtas 30402636ac3cSMarcin Wojtas return IRQ_HANDLED; 30412636ac3cSMarcin Wojtas } 30422636ac3cSMarcin Wojtas 30432636ac3cSMarcin Wojtas /* Interrupt handling - the callback for request_percpu_irq() */ 30442636ac3cSMarcin Wojtas static irqreturn_t mvneta_percpu_isr(int irq, void *dev_id) 30452636ac3cSMarcin Wojtas { 304612bb03b4SMaxime Ripard struct mvneta_pcpu_port *port = (struct mvneta_pcpu_port *)dev_id; 3047c5aff182SThomas Petazzoni 304812bb03b4SMaxime Ripard disable_percpu_irq(port->pp->dev->irq); 304912bb03b4SMaxime Ripard napi_schedule(&port->napi); 3050c5aff182SThomas Petazzoni 3051c5aff182SThomas Petazzoni return IRQ_HANDLED; 3052c5aff182SThomas Petazzoni } 3053c5aff182SThomas Petazzoni 3054503f9aa9SRussell King static void mvneta_link_change(struct mvneta_port *pp) 3055898b2970SStas Sergeev { 3056898b2970SStas Sergeev u32 gmac_stat = mvreg_read(pp, MVNETA_GMAC_STATUS); 3057898b2970SStas Sergeev 3058503f9aa9SRussell King phylink_mac_change(pp->phylink, !!(gmac_stat & MVNETA_GMAC_LINK_UP)); 3059898b2970SStas Sergeev } 3060898b2970SStas Sergeev 3061c5aff182SThomas Petazzoni /* NAPI handler 3062c5aff182SThomas Petazzoni * Bits 0 - 7 of the causeRxTx register indicate that are transmitted 3063c5aff182SThomas Petazzoni * packets on the corresponding TXQ (Bit 0 is for TX queue 1). 3064c5aff182SThomas Petazzoni * Bits 8 -15 of the cause Rx Tx register indicate that are received 3065c5aff182SThomas Petazzoni * packets on the corresponding RXQ (Bit 8 is for RX queue 0). 3066c5aff182SThomas Petazzoni * Each CPU has its own causeRxTx register 3067c5aff182SThomas Petazzoni */ 3068c5aff182SThomas Petazzoni static int mvneta_poll(struct napi_struct *napi, int budget) 3069c5aff182SThomas Petazzoni { 3070c5aff182SThomas Petazzoni int rx_done = 0; 3071c5aff182SThomas Petazzoni u32 cause_rx_tx; 30722dcf75e2SGregory CLEMENT int rx_queue; 3073c5aff182SThomas Petazzoni struct mvneta_port *pp = netdev_priv(napi->dev); 307412bb03b4SMaxime Ripard struct mvneta_pcpu_port *port = this_cpu_ptr(pp->ports); 3075c5aff182SThomas Petazzoni 3076c5aff182SThomas Petazzoni if (!netif_running(pp->dev)) { 30772636ac3cSMarcin Wojtas napi_complete(napi); 3078c5aff182SThomas Petazzoni return rx_done; 3079c5aff182SThomas Petazzoni } 3080c5aff182SThomas Petazzoni 3081c5aff182SThomas Petazzoni /* Read cause register */ 3082898b2970SStas Sergeev cause_rx_tx = mvreg_read(pp, MVNETA_INTR_NEW_CAUSE); 3083898b2970SStas Sergeev if (cause_rx_tx & MVNETA_MISCINTR_INTR_MASK) { 3084898b2970SStas Sergeev u32 cause_misc = mvreg_read(pp, MVNETA_INTR_MISC_CAUSE); 3085898b2970SStas Sergeev 3086898b2970SStas Sergeev mvreg_write(pp, MVNETA_INTR_MISC_CAUSE, 0); 3087503f9aa9SRussell King 3088503f9aa9SRussell King if (cause_misc & (MVNETA_CAUSE_PHY_STATUS_CHANGE | 3089856b2cc5SRussell King MVNETA_CAUSE_LINK_CHANGE)) 3090503f9aa9SRussell King mvneta_link_change(pp); 3091898b2970SStas Sergeev } 309271f6d1b3Swilly tarreau 309371f6d1b3Swilly tarreau /* Release Tx descriptors */ 309471f6d1b3Swilly tarreau if (cause_rx_tx & MVNETA_TX_INTR_MASK_ALL) { 30950713a86aSArnaud Ebalard mvneta_tx_done_gbe(pp, (cause_rx_tx & MVNETA_TX_INTR_MASK_ALL)); 309671f6d1b3Swilly tarreau cause_rx_tx &= ~MVNETA_TX_INTR_MASK_ALL; 309771f6d1b3Swilly tarreau } 3098c5aff182SThomas Petazzoni 30996a20c175SThomas Petazzoni /* For the case where the last mvneta_poll did not process all 3100c5aff182SThomas Petazzoni * RX packets 3101c5aff182SThomas Petazzoni */ 31022dcf75e2SGregory CLEMENT rx_queue = fls(((cause_rx_tx >> 8) & 0xff)); 31032dcf75e2SGregory CLEMENT 31042636ac3cSMarcin Wojtas cause_rx_tx |= pp->neta_armada3700 ? pp->cause_rx_tx : 31052636ac3cSMarcin Wojtas port->cause_rx_tx; 31062dcf75e2SGregory CLEMENT 31072dcf75e2SGregory CLEMENT if (rx_queue) { 31082dcf75e2SGregory CLEMENT rx_queue = rx_queue - 1; 3109dc35a10fSMarcin Wojtas if (pp->bm_priv) 31107a86f05fSAndrew Lunn rx_done = mvneta_rx_hwbm(napi, pp, budget, 31117a86f05fSAndrew Lunn &pp->rxqs[rx_queue]); 3112dc35a10fSMarcin Wojtas else 31137a86f05fSAndrew Lunn rx_done = mvneta_rx_swbm(napi, pp, budget, 31147a86f05fSAndrew Lunn &pp->rxqs[rx_queue]); 31152dcf75e2SGregory CLEMENT } 31162dcf75e2SGregory CLEMENT 31176ad20165SEric Dumazet if (rx_done < budget) { 3118c5aff182SThomas Petazzoni cause_rx_tx = 0; 31196ad20165SEric Dumazet napi_complete_done(napi, rx_done); 31202636ac3cSMarcin Wojtas 31212636ac3cSMarcin Wojtas if (pp->neta_armada3700) { 31222636ac3cSMarcin Wojtas unsigned long flags; 31232636ac3cSMarcin Wojtas 31242636ac3cSMarcin Wojtas local_irq_save(flags); 31252636ac3cSMarcin Wojtas mvreg_write(pp, MVNETA_INTR_NEW_MASK, 31262636ac3cSMarcin Wojtas MVNETA_RX_INTR_MASK(rxq_number) | 31272636ac3cSMarcin Wojtas MVNETA_TX_INTR_MASK(txq_number) | 31282636ac3cSMarcin Wojtas MVNETA_MISCINTR_INTR_MASK); 31292636ac3cSMarcin Wojtas local_irq_restore(flags); 31302636ac3cSMarcin Wojtas } else { 313112bb03b4SMaxime Ripard enable_percpu_irq(pp->dev->irq, 0); 3132c5aff182SThomas Petazzoni } 31332636ac3cSMarcin Wojtas } 3134c5aff182SThomas Petazzoni 31352636ac3cSMarcin Wojtas if (pp->neta_armada3700) 31362636ac3cSMarcin Wojtas pp->cause_rx_tx = cause_rx_tx; 31372636ac3cSMarcin Wojtas else 313812bb03b4SMaxime Ripard port->cause_rx_tx = cause_rx_tx; 31392636ac3cSMarcin Wojtas 3140c5aff182SThomas Petazzoni return rx_done; 3141c5aff182SThomas Petazzoni } 3142c5aff182SThomas Petazzoni 3143568a3fa2SLorenzo Bianconi static int mvneta_create_page_pool(struct mvneta_port *pp, 3144568a3fa2SLorenzo Bianconi struct mvneta_rx_queue *rxq, int size) 3145568a3fa2SLorenzo Bianconi { 31460db51da7SLorenzo Bianconi struct bpf_prog *xdp_prog = READ_ONCE(pp->xdp_prog); 3147568a3fa2SLorenzo Bianconi struct page_pool_params pp_params = { 3148568a3fa2SLorenzo Bianconi .order = 0, 314907e13edbSLorenzo Bianconi .flags = PP_FLAG_DMA_MAP | PP_FLAG_DMA_SYNC_DEV, 3150568a3fa2SLorenzo Bianconi .pool_size = size, 31511657adccSLorenzo Bianconi .nid = NUMA_NO_NODE, 3152568a3fa2SLorenzo Bianconi .dev = pp->dev->dev.parent, 31530db51da7SLorenzo Bianconi .dma_dir = xdp_prog ? DMA_BIDIRECTIONAL : DMA_FROM_DEVICE, 315407e13edbSLorenzo Bianconi .offset = pp->rx_offset_correction, 315507e13edbSLorenzo Bianconi .max_len = MVNETA_MAX_RX_BUF_SIZE, 3156568a3fa2SLorenzo Bianconi }; 3157568a3fa2SLorenzo Bianconi int err; 3158568a3fa2SLorenzo Bianconi 3159568a3fa2SLorenzo Bianconi rxq->page_pool = page_pool_create(&pp_params); 3160568a3fa2SLorenzo Bianconi if (IS_ERR(rxq->page_pool)) { 3161568a3fa2SLorenzo Bianconi err = PTR_ERR(rxq->page_pool); 3162568a3fa2SLorenzo Bianconi rxq->page_pool = NULL; 3163568a3fa2SLorenzo Bianconi return err; 3164568a3fa2SLorenzo Bianconi } 3165568a3fa2SLorenzo Bianconi 3166568a3fa2SLorenzo Bianconi err = xdp_rxq_info_reg(&rxq->xdp_rxq, pp->dev, rxq->id); 3167568a3fa2SLorenzo Bianconi if (err < 0) 3168568a3fa2SLorenzo Bianconi goto err_free_pp; 3169568a3fa2SLorenzo Bianconi 3170568a3fa2SLorenzo Bianconi err = xdp_rxq_info_reg_mem_model(&rxq->xdp_rxq, MEM_TYPE_PAGE_POOL, 3171568a3fa2SLorenzo Bianconi rxq->page_pool); 3172568a3fa2SLorenzo Bianconi if (err) 3173568a3fa2SLorenzo Bianconi goto err_unregister_rxq; 3174568a3fa2SLorenzo Bianconi 3175568a3fa2SLorenzo Bianconi return 0; 3176568a3fa2SLorenzo Bianconi 3177568a3fa2SLorenzo Bianconi err_unregister_rxq: 3178568a3fa2SLorenzo Bianconi xdp_rxq_info_unreg(&rxq->xdp_rxq); 3179568a3fa2SLorenzo Bianconi err_free_pp: 3180568a3fa2SLorenzo Bianconi page_pool_destroy(rxq->page_pool); 3181568a3fa2SLorenzo Bianconi rxq->page_pool = NULL; 3182568a3fa2SLorenzo Bianconi return err; 3183568a3fa2SLorenzo Bianconi } 3184568a3fa2SLorenzo Bianconi 3185c5aff182SThomas Petazzoni /* Handle rxq fill: allocates rxq skbs; called when initializing a port */ 3186c5aff182SThomas Petazzoni static int mvneta_rxq_fill(struct mvneta_port *pp, struct mvneta_rx_queue *rxq, 3187c5aff182SThomas Petazzoni int num) 3188c5aff182SThomas Petazzoni { 3189568a3fa2SLorenzo Bianconi int i, err; 3190568a3fa2SLorenzo Bianconi 3191568a3fa2SLorenzo Bianconi err = mvneta_create_page_pool(pp, rxq, num); 3192568a3fa2SLorenzo Bianconi if (err < 0) 3193568a3fa2SLorenzo Bianconi return err; 3194c5aff182SThomas Petazzoni 3195c5aff182SThomas Petazzoni for (i = 0; i < num; i++) { 3196a1a65ab1Swilly tarreau memset(rxq->descs + i, 0, sizeof(struct mvneta_rx_desc)); 31977e47fd84SGregory CLEMENT if (mvneta_rx_refill(pp, rxq->descs + i, rxq, 31987e47fd84SGregory CLEMENT GFP_KERNEL) != 0) { 31997e47fd84SGregory CLEMENT netdev_err(pp->dev, 32007e47fd84SGregory CLEMENT "%s:rxq %d, %d of %d buffs filled\n", 3201c5aff182SThomas Petazzoni __func__, rxq->id, i, num); 3202c5aff182SThomas Petazzoni break; 3203c5aff182SThomas Petazzoni } 3204c5aff182SThomas Petazzoni } 3205c5aff182SThomas Petazzoni 3206c5aff182SThomas Petazzoni /* Add this number of RX descriptors as non occupied (ready to 32076a20c175SThomas Petazzoni * get packets) 32086a20c175SThomas Petazzoni */ 3209c5aff182SThomas Petazzoni mvneta_rxq_non_occup_desc_add(pp, rxq, i); 3210c5aff182SThomas Petazzoni 3211c5aff182SThomas Petazzoni return i; 3212c5aff182SThomas Petazzoni } 3213c5aff182SThomas Petazzoni 3214c5aff182SThomas Petazzoni /* Free all packets pending transmit from all TXQs and reset TX port */ 3215c5aff182SThomas Petazzoni static void mvneta_tx_reset(struct mvneta_port *pp) 3216c5aff182SThomas Petazzoni { 3217c5aff182SThomas Petazzoni int queue; 3218c5aff182SThomas Petazzoni 32199672850bSEzequiel Garcia /* free the skb's in the tx ring */ 3220c5aff182SThomas Petazzoni for (queue = 0; queue < txq_number; queue++) 3221c5aff182SThomas Petazzoni mvneta_txq_done_force(pp, &pp->txqs[queue]); 3222c5aff182SThomas Petazzoni 3223c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_PORT_TX_RESET, MVNETA_PORT_TX_DMA_RESET); 3224c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_PORT_TX_RESET, 0); 3225c5aff182SThomas Petazzoni } 3226c5aff182SThomas Petazzoni 3227c5aff182SThomas Petazzoni static void mvneta_rx_reset(struct mvneta_port *pp) 3228c5aff182SThomas Petazzoni { 3229c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_PORT_RX_RESET, MVNETA_PORT_RX_DMA_RESET); 3230c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_PORT_RX_RESET, 0); 3231c5aff182SThomas Petazzoni } 3232c5aff182SThomas Petazzoni 3233c5aff182SThomas Petazzoni /* Rx/Tx queue initialization/cleanup methods */ 3234c5aff182SThomas Petazzoni 32354a188a63SJisheng Zhang static int mvneta_rxq_sw_init(struct mvneta_port *pp, 3236c5aff182SThomas Petazzoni struct mvneta_rx_queue *rxq) 3237c5aff182SThomas Petazzoni { 3238c5aff182SThomas Petazzoni rxq->size = pp->rx_ring_size; 3239c5aff182SThomas Petazzoni 3240c5aff182SThomas Petazzoni /* Allocate memory for RX descriptors */ 3241c5aff182SThomas Petazzoni rxq->descs = dma_alloc_coherent(pp->dev->dev.parent, 3242c5aff182SThomas Petazzoni rxq->size * MVNETA_DESC_ALIGNED_SIZE, 3243c5aff182SThomas Petazzoni &rxq->descs_phys, GFP_KERNEL); 3244f95936ccSMarkus Elfring if (!rxq->descs) 3245c5aff182SThomas Petazzoni return -ENOMEM; 3246c5aff182SThomas Petazzoni 3247c5aff182SThomas Petazzoni rxq->last_desc = rxq->size - 1; 3248c5aff182SThomas Petazzoni 32494a188a63SJisheng Zhang return 0; 32504a188a63SJisheng Zhang } 32514a188a63SJisheng Zhang 32524a188a63SJisheng Zhang static void mvneta_rxq_hw_init(struct mvneta_port *pp, 32534a188a63SJisheng Zhang struct mvneta_rx_queue *rxq) 32544a188a63SJisheng Zhang { 3255c5aff182SThomas Petazzoni /* Set Rx descriptors queue starting address */ 3256c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_RXQ_BASE_ADDR_REG(rxq->id), rxq->descs_phys); 3257c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_RXQ_SIZE_REG(rxq->id), rxq->size); 3258c5aff182SThomas Petazzoni 3259c5aff182SThomas Petazzoni /* Set coalescing pkts and time */ 3260c5aff182SThomas Petazzoni mvneta_rx_pkts_coal_set(pp, rxq, rxq->pkts_coal); 3261c5aff182SThomas Petazzoni mvneta_rx_time_coal_set(pp, rxq, rxq->time_coal); 3262c5aff182SThomas Petazzoni 3263dc35a10fSMarcin Wojtas if (!pp->bm_priv) { 3264562e2f46SYelena Krivosheev /* Set Offset */ 3265562e2f46SYelena Krivosheev mvneta_rxq_offset_set(pp, rxq, 0); 3266e735fd55SMarcin Wojtas mvneta_rxq_buf_size_set(pp, rxq, PAGE_SIZE < SZ_64K ? 32678dc9a088SLorenzo Bianconi MVNETA_MAX_RX_BUF_SIZE : 3268e735fd55SMarcin Wojtas MVNETA_RX_BUF_SIZE(pp->pkt_size)); 3269c5aff182SThomas Petazzoni mvneta_rxq_bm_disable(pp, rxq); 3270e9f64999SGregory CLEMENT mvneta_rxq_fill(pp, rxq, rxq->size); 3271dc35a10fSMarcin Wojtas } else { 3272562e2f46SYelena Krivosheev /* Set Offset */ 3273562e2f46SYelena Krivosheev mvneta_rxq_offset_set(pp, rxq, 3274562e2f46SYelena Krivosheev NET_SKB_PAD - pp->rx_offset_correction); 3275562e2f46SYelena Krivosheev 3276dc35a10fSMarcin Wojtas mvneta_rxq_bm_enable(pp, rxq); 3277562e2f46SYelena Krivosheev /* Fill RXQ with buffers from RX pool */ 3278dc35a10fSMarcin Wojtas mvneta_rxq_long_pool_set(pp, rxq); 3279dc35a10fSMarcin Wojtas mvneta_rxq_short_pool_set(pp, rxq); 3280e9f64999SGregory CLEMENT mvneta_rxq_non_occup_desc_add(pp, rxq, rxq->size); 3281dc35a10fSMarcin Wojtas } 32824a188a63SJisheng Zhang } 32834a188a63SJisheng Zhang 32844a188a63SJisheng Zhang /* Create a specified RX queue */ 32854a188a63SJisheng Zhang static int mvneta_rxq_init(struct mvneta_port *pp, 32864a188a63SJisheng Zhang struct mvneta_rx_queue *rxq) 32874a188a63SJisheng Zhang 32884a188a63SJisheng Zhang { 32894a188a63SJisheng Zhang int ret; 32904a188a63SJisheng Zhang 32914a188a63SJisheng Zhang ret = mvneta_rxq_sw_init(pp, rxq); 32924a188a63SJisheng Zhang if (ret < 0) 32934a188a63SJisheng Zhang return ret; 32944a188a63SJisheng Zhang 32954a188a63SJisheng Zhang mvneta_rxq_hw_init(pp, rxq); 3296dc35a10fSMarcin Wojtas 3297c5aff182SThomas Petazzoni return 0; 3298c5aff182SThomas Petazzoni } 3299c5aff182SThomas Petazzoni 3300c5aff182SThomas Petazzoni /* Cleanup Rx queue */ 3301c5aff182SThomas Petazzoni static void mvneta_rxq_deinit(struct mvneta_port *pp, 3302c5aff182SThomas Petazzoni struct mvneta_rx_queue *rxq) 3303c5aff182SThomas Petazzoni { 3304c5aff182SThomas Petazzoni mvneta_rxq_drop_pkts(pp, rxq); 3305c5aff182SThomas Petazzoni 3306562e2f46SYelena Krivosheev if (rxq->skb) 3307562e2f46SYelena Krivosheev dev_kfree_skb_any(rxq->skb); 3308562e2f46SYelena Krivosheev 3309c5aff182SThomas Petazzoni if (rxq->descs) 3310c5aff182SThomas Petazzoni dma_free_coherent(pp->dev->dev.parent, 3311c5aff182SThomas Petazzoni rxq->size * MVNETA_DESC_ALIGNED_SIZE, 3312c5aff182SThomas Petazzoni rxq->descs, 3313c5aff182SThomas Petazzoni rxq->descs_phys); 3314c5aff182SThomas Petazzoni 3315c5aff182SThomas Petazzoni rxq->descs = NULL; 3316c5aff182SThomas Petazzoni rxq->last_desc = 0; 3317c5aff182SThomas Petazzoni rxq->next_desc_to_proc = 0; 3318c5aff182SThomas Petazzoni rxq->descs_phys = 0; 3319562e2f46SYelena Krivosheev rxq->first_to_refill = 0; 3320562e2f46SYelena Krivosheev rxq->refill_num = 0; 3321562e2f46SYelena Krivosheev rxq->skb = NULL; 3322562e2f46SYelena Krivosheev rxq->left_size = 0; 3323c5aff182SThomas Petazzoni } 3324c5aff182SThomas Petazzoni 33254a188a63SJisheng Zhang static int mvneta_txq_sw_init(struct mvneta_port *pp, 3326c5aff182SThomas Petazzoni struct mvneta_tx_queue *txq) 3327c5aff182SThomas Petazzoni { 332850bf8cb6SGregory CLEMENT int cpu; 332950bf8cb6SGregory CLEMENT 3330c5aff182SThomas Petazzoni txq->size = pp->tx_ring_size; 3331c5aff182SThomas Petazzoni 33328eef5f97SEzequiel Garcia /* A queue must always have room for at least one skb. 33338eef5f97SEzequiel Garcia * Therefore, stop the queue when the free entries reaches 33348eef5f97SEzequiel Garcia * the maximum number of descriptors per skb. 33358eef5f97SEzequiel Garcia */ 33368eef5f97SEzequiel Garcia txq->tx_stop_threshold = txq->size - MVNETA_MAX_SKB_DESCS; 33378eef5f97SEzequiel Garcia txq->tx_wake_threshold = txq->tx_stop_threshold / 2; 33388eef5f97SEzequiel Garcia 3339c5aff182SThomas Petazzoni /* Allocate memory for TX descriptors */ 3340c5aff182SThomas Petazzoni txq->descs = dma_alloc_coherent(pp->dev->dev.parent, 3341c5aff182SThomas Petazzoni txq->size * MVNETA_DESC_ALIGNED_SIZE, 3342c5aff182SThomas Petazzoni &txq->descs_phys, GFP_KERNEL); 3343f95936ccSMarkus Elfring if (!txq->descs) 3344c5aff182SThomas Petazzoni return -ENOMEM; 3345c5aff182SThomas Petazzoni 3346c5aff182SThomas Petazzoni txq->last_desc = txq->size - 1; 3347c5aff182SThomas Petazzoni 33489e58c8b4SLorenzo Bianconi txq->buf = kmalloc_array(txq->size, sizeof(*txq->buf), GFP_KERNEL); 33499e58c8b4SLorenzo Bianconi if (!txq->buf) { 3350c5aff182SThomas Petazzoni dma_free_coherent(pp->dev->dev.parent, 3351c5aff182SThomas Petazzoni txq->size * MVNETA_DESC_ALIGNED_SIZE, 3352c5aff182SThomas Petazzoni txq->descs, txq->descs_phys); 3353c5aff182SThomas Petazzoni return -ENOMEM; 3354c5aff182SThomas Petazzoni } 33552adb719dSEzequiel Garcia 33562adb719dSEzequiel Garcia /* Allocate DMA buffers for TSO MAC/IP/TCP headers */ 33572adb719dSEzequiel Garcia txq->tso_hdrs = dma_alloc_coherent(pp->dev->dev.parent, 33582adb719dSEzequiel Garcia txq->size * TSO_HEADER_SIZE, 33592adb719dSEzequiel Garcia &txq->tso_hdrs_phys, GFP_KERNEL); 3360f95936ccSMarkus Elfring if (!txq->tso_hdrs) { 33619e58c8b4SLorenzo Bianconi kfree(txq->buf); 33622adb719dSEzequiel Garcia dma_free_coherent(pp->dev->dev.parent, 33632adb719dSEzequiel Garcia txq->size * MVNETA_DESC_ALIGNED_SIZE, 33642adb719dSEzequiel Garcia txq->descs, txq->descs_phys); 33652adb719dSEzequiel Garcia return -ENOMEM; 33662adb719dSEzequiel Garcia } 3367c5aff182SThomas Petazzoni 336850bf8cb6SGregory CLEMENT /* Setup XPS mapping */ 336950bf8cb6SGregory CLEMENT if (txq_number > 1) 337050bf8cb6SGregory CLEMENT cpu = txq->id % num_present_cpus(); 337150bf8cb6SGregory CLEMENT else 337250bf8cb6SGregory CLEMENT cpu = pp->rxq_def % num_present_cpus(); 337350bf8cb6SGregory CLEMENT cpumask_set_cpu(cpu, &txq->affinity_mask); 337450bf8cb6SGregory CLEMENT netif_set_xps_queue(pp->dev, &txq->affinity_mask, txq->id); 337550bf8cb6SGregory CLEMENT 3376c5aff182SThomas Petazzoni return 0; 3377c5aff182SThomas Petazzoni } 3378c5aff182SThomas Petazzoni 33794a188a63SJisheng Zhang static void mvneta_txq_hw_init(struct mvneta_port *pp, 33804a188a63SJisheng Zhang struct mvneta_tx_queue *txq) 33814a188a63SJisheng Zhang { 33824a188a63SJisheng Zhang /* Set maximum bandwidth for enabled TXQs */ 33834a188a63SJisheng Zhang mvreg_write(pp, MVETH_TXQ_TOKEN_CFG_REG(txq->id), 0x03ffffff); 33844a188a63SJisheng Zhang mvreg_write(pp, MVETH_TXQ_TOKEN_COUNT_REG(txq->id), 0x3fffffff); 33854a188a63SJisheng Zhang 33864a188a63SJisheng Zhang /* Set Tx descriptors queue starting address */ 33874a188a63SJisheng Zhang mvreg_write(pp, MVNETA_TXQ_BASE_ADDR_REG(txq->id), txq->descs_phys); 33884a188a63SJisheng Zhang mvreg_write(pp, MVNETA_TXQ_SIZE_REG(txq->id), txq->size); 33894a188a63SJisheng Zhang 33904a188a63SJisheng Zhang mvneta_tx_done_pkts_coal_set(pp, txq, txq->done_pkts_coal); 33914a188a63SJisheng Zhang } 33924a188a63SJisheng Zhang 33934a188a63SJisheng Zhang /* Create and initialize a tx queue */ 33944a188a63SJisheng Zhang static int mvneta_txq_init(struct mvneta_port *pp, 33954a188a63SJisheng Zhang struct mvneta_tx_queue *txq) 33964a188a63SJisheng Zhang { 33974a188a63SJisheng Zhang int ret; 33984a188a63SJisheng Zhang 33994a188a63SJisheng Zhang ret = mvneta_txq_sw_init(pp, txq); 34004a188a63SJisheng Zhang if (ret < 0) 34014a188a63SJisheng Zhang return ret; 34024a188a63SJisheng Zhang 34034a188a63SJisheng Zhang mvneta_txq_hw_init(pp, txq); 34044a188a63SJisheng Zhang 34054a188a63SJisheng Zhang return 0; 34064a188a63SJisheng Zhang } 34074a188a63SJisheng Zhang 3408c5aff182SThomas Petazzoni /* Free allocated resources when mvneta_txq_init() fails to allocate memory*/ 34094a188a63SJisheng Zhang static void mvneta_txq_sw_deinit(struct mvneta_port *pp, 3410c5aff182SThomas Petazzoni struct mvneta_tx_queue *txq) 3411c5aff182SThomas Petazzoni { 3412a29b6235SMarcin Wojtas struct netdev_queue *nq = netdev_get_tx_queue(pp->dev, txq->id); 3413a29b6235SMarcin Wojtas 34149e58c8b4SLorenzo Bianconi kfree(txq->buf); 3415c5aff182SThomas Petazzoni 34162adb719dSEzequiel Garcia if (txq->tso_hdrs) 34172adb719dSEzequiel Garcia dma_free_coherent(pp->dev->dev.parent, 34182adb719dSEzequiel Garcia txq->size * TSO_HEADER_SIZE, 34192adb719dSEzequiel Garcia txq->tso_hdrs, txq->tso_hdrs_phys); 3420c5aff182SThomas Petazzoni if (txq->descs) 3421c5aff182SThomas Petazzoni dma_free_coherent(pp->dev->dev.parent, 3422c5aff182SThomas Petazzoni txq->size * MVNETA_DESC_ALIGNED_SIZE, 3423c5aff182SThomas Petazzoni txq->descs, txq->descs_phys); 3424c5aff182SThomas Petazzoni 3425a29b6235SMarcin Wojtas netdev_tx_reset_queue(nq); 3426a29b6235SMarcin Wojtas 3427c5aff182SThomas Petazzoni txq->descs = NULL; 3428c5aff182SThomas Petazzoni txq->last_desc = 0; 3429c5aff182SThomas Petazzoni txq->next_desc_to_proc = 0; 3430c5aff182SThomas Petazzoni txq->descs_phys = 0; 34314a188a63SJisheng Zhang } 3432c5aff182SThomas Petazzoni 34334a188a63SJisheng Zhang static void mvneta_txq_hw_deinit(struct mvneta_port *pp, 34344a188a63SJisheng Zhang struct mvneta_tx_queue *txq) 34354a188a63SJisheng Zhang { 3436c5aff182SThomas Petazzoni /* Set minimum bandwidth for disabled TXQs */ 3437c5aff182SThomas Petazzoni mvreg_write(pp, MVETH_TXQ_TOKEN_CFG_REG(txq->id), 0); 3438c5aff182SThomas Petazzoni mvreg_write(pp, MVETH_TXQ_TOKEN_COUNT_REG(txq->id), 0); 3439c5aff182SThomas Petazzoni 3440c5aff182SThomas Petazzoni /* Set Tx descriptors queue starting address and size */ 3441c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_TXQ_BASE_ADDR_REG(txq->id), 0); 3442c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_TXQ_SIZE_REG(txq->id), 0); 3443c5aff182SThomas Petazzoni } 3444c5aff182SThomas Petazzoni 34454a188a63SJisheng Zhang static void mvneta_txq_deinit(struct mvneta_port *pp, 34464a188a63SJisheng Zhang struct mvneta_tx_queue *txq) 34474a188a63SJisheng Zhang { 34484a188a63SJisheng Zhang mvneta_txq_sw_deinit(pp, txq); 34494a188a63SJisheng Zhang mvneta_txq_hw_deinit(pp, txq); 34504a188a63SJisheng Zhang } 34514a188a63SJisheng Zhang 3452c5aff182SThomas Petazzoni /* Cleanup all Tx queues */ 3453c5aff182SThomas Petazzoni static void mvneta_cleanup_txqs(struct mvneta_port *pp) 3454c5aff182SThomas Petazzoni { 3455c5aff182SThomas Petazzoni int queue; 3456c5aff182SThomas Petazzoni 3457c5aff182SThomas Petazzoni for (queue = 0; queue < txq_number; queue++) 3458c5aff182SThomas Petazzoni mvneta_txq_deinit(pp, &pp->txqs[queue]); 3459c5aff182SThomas Petazzoni } 3460c5aff182SThomas Petazzoni 3461c5aff182SThomas Petazzoni /* Cleanup all Rx queues */ 3462c5aff182SThomas Petazzoni static void mvneta_cleanup_rxqs(struct mvneta_port *pp) 3463c5aff182SThomas Petazzoni { 34642dcf75e2SGregory CLEMENT int queue; 34652dcf75e2SGregory CLEMENT 3466ca5902a6SYelena Krivosheev for (queue = 0; queue < rxq_number; queue++) 34672dcf75e2SGregory CLEMENT mvneta_rxq_deinit(pp, &pp->rxqs[queue]); 3468c5aff182SThomas Petazzoni } 3469c5aff182SThomas Petazzoni 3470c5aff182SThomas Petazzoni 3471c5aff182SThomas Petazzoni /* Init all Rx queues */ 3472c5aff182SThomas Petazzoni static int mvneta_setup_rxqs(struct mvneta_port *pp) 3473c5aff182SThomas Petazzoni { 34742dcf75e2SGregory CLEMENT int queue; 34752dcf75e2SGregory CLEMENT 34762dcf75e2SGregory CLEMENT for (queue = 0; queue < rxq_number; queue++) { 34772dcf75e2SGregory CLEMENT int err = mvneta_rxq_init(pp, &pp->rxqs[queue]); 34782dcf75e2SGregory CLEMENT 3479c5aff182SThomas Petazzoni if (err) { 3480c5aff182SThomas Petazzoni netdev_err(pp->dev, "%s: can't create rxq=%d\n", 34812dcf75e2SGregory CLEMENT __func__, queue); 3482c5aff182SThomas Petazzoni mvneta_cleanup_rxqs(pp); 3483c5aff182SThomas Petazzoni return err; 3484c5aff182SThomas Petazzoni } 34852dcf75e2SGregory CLEMENT } 3486c5aff182SThomas Petazzoni 3487c5aff182SThomas Petazzoni return 0; 3488c5aff182SThomas Petazzoni } 3489c5aff182SThomas Petazzoni 3490c5aff182SThomas Petazzoni /* Init all tx queues */ 3491c5aff182SThomas Petazzoni static int mvneta_setup_txqs(struct mvneta_port *pp) 3492c5aff182SThomas Petazzoni { 3493c5aff182SThomas Petazzoni int queue; 3494c5aff182SThomas Petazzoni 3495c5aff182SThomas Petazzoni for (queue = 0; queue < txq_number; queue++) { 3496c5aff182SThomas Petazzoni int err = mvneta_txq_init(pp, &pp->txqs[queue]); 3497c5aff182SThomas Petazzoni if (err) { 3498c5aff182SThomas Petazzoni netdev_err(pp->dev, "%s: can't create txq=%d\n", 3499c5aff182SThomas Petazzoni __func__, queue); 3500c5aff182SThomas Petazzoni mvneta_cleanup_txqs(pp); 3501c5aff182SThomas Petazzoni return err; 3502c5aff182SThomas Petazzoni } 3503c5aff182SThomas Petazzoni } 3504c5aff182SThomas Petazzoni 3505c5aff182SThomas Petazzoni return 0; 3506c5aff182SThomas Petazzoni } 3507c5aff182SThomas Petazzoni 3508031b922bSMarek Behún static int mvneta_comphy_init(struct mvneta_port *pp) 3509031b922bSMarek Behún { 3510031b922bSMarek Behún int ret; 3511031b922bSMarek Behún 3512031b922bSMarek Behún if (!pp->comphy) 3513031b922bSMarek Behún return 0; 3514031b922bSMarek Behún 3515031b922bSMarek Behún ret = phy_set_mode_ext(pp->comphy, PHY_MODE_ETHERNET, 3516031b922bSMarek Behún pp->phy_interface); 3517031b922bSMarek Behún if (ret) 3518031b922bSMarek Behún return ret; 3519031b922bSMarek Behún 3520031b922bSMarek Behún return phy_power_on(pp->comphy); 3521031b922bSMarek Behún } 3522031b922bSMarek Behún 3523c5aff182SThomas Petazzoni static void mvneta_start_dev(struct mvneta_port *pp) 3524c5aff182SThomas Petazzoni { 35256b125d63SGregory CLEMENT int cpu; 352612bb03b4SMaxime Ripard 3527031b922bSMarek Behún WARN_ON(mvneta_comphy_init(pp)); 3528a10c1c81SRussell King 3529c5aff182SThomas Petazzoni mvneta_max_rx_size_set(pp, pp->pkt_size); 3530c5aff182SThomas Petazzoni mvneta_txq_max_tx_size_set(pp, pp->pkt_size); 3531c5aff182SThomas Petazzoni 3532c5aff182SThomas Petazzoni /* start the Rx/Tx activity */ 3533c5aff182SThomas Petazzoni mvneta_port_enable(pp); 3534c5aff182SThomas Petazzoni 35352636ac3cSMarcin Wojtas if (!pp->neta_armada3700) { 3536c5aff182SThomas Petazzoni /* Enable polling on the port */ 3537129219e4SGregory CLEMENT for_each_online_cpu(cpu) { 35382636ac3cSMarcin Wojtas struct mvneta_pcpu_port *port = 35392636ac3cSMarcin Wojtas per_cpu_ptr(pp->ports, cpu); 354012bb03b4SMaxime Ripard 354112bb03b4SMaxime Ripard napi_enable(&port->napi); 354212bb03b4SMaxime Ripard } 35432636ac3cSMarcin Wojtas } else { 35442636ac3cSMarcin Wojtas napi_enable(&pp->napi); 35452636ac3cSMarcin Wojtas } 3546c5aff182SThomas Petazzoni 35472dcf75e2SGregory CLEMENT /* Unmask interrupts. It has to be done from each CPU */ 35486b125d63SGregory CLEMENT on_each_cpu(mvneta_percpu_unmask_interrupt, pp, true); 35496b125d63SGregory CLEMENT 3550898b2970SStas Sergeev mvreg_write(pp, MVNETA_INTR_MISC_MASK, 3551898b2970SStas Sergeev MVNETA_CAUSE_PHY_STATUS_CHANGE | 3552856b2cc5SRussell King MVNETA_CAUSE_LINK_CHANGE); 3553c5aff182SThomas Petazzoni 3554503f9aa9SRussell King phylink_start(pp->phylink); 3555c5aff182SThomas Petazzoni netif_tx_start_all_queues(pp->dev); 3556c5aff182SThomas Petazzoni } 3557c5aff182SThomas Petazzoni 3558c5aff182SThomas Petazzoni static void mvneta_stop_dev(struct mvneta_port *pp) 3559c5aff182SThomas Petazzoni { 356012bb03b4SMaxime Ripard unsigned int cpu; 356112bb03b4SMaxime Ripard 3562503f9aa9SRussell King phylink_stop(pp->phylink); 3563c5aff182SThomas Petazzoni 35642636ac3cSMarcin Wojtas if (!pp->neta_armada3700) { 3565129219e4SGregory CLEMENT for_each_online_cpu(cpu) { 35662636ac3cSMarcin Wojtas struct mvneta_pcpu_port *port = 35672636ac3cSMarcin Wojtas per_cpu_ptr(pp->ports, cpu); 356812bb03b4SMaxime Ripard 356912bb03b4SMaxime Ripard napi_disable(&port->napi); 357012bb03b4SMaxime Ripard } 35712636ac3cSMarcin Wojtas } else { 35722636ac3cSMarcin Wojtas napi_disable(&pp->napi); 35732636ac3cSMarcin Wojtas } 3574c5aff182SThomas Petazzoni 3575c5aff182SThomas Petazzoni netif_carrier_off(pp->dev); 3576c5aff182SThomas Petazzoni 3577c5aff182SThomas Petazzoni mvneta_port_down(pp); 3578c5aff182SThomas Petazzoni netif_tx_stop_all_queues(pp->dev); 3579c5aff182SThomas Petazzoni 3580c5aff182SThomas Petazzoni /* Stop the port activity */ 3581c5aff182SThomas Petazzoni mvneta_port_disable(pp); 3582c5aff182SThomas Petazzoni 3583c5aff182SThomas Petazzoni /* Clear all ethernet port interrupts */ 3584db488c10SGregory CLEMENT on_each_cpu(mvneta_percpu_clear_intr_cause, pp, true); 3585c5aff182SThomas Petazzoni 3586c5aff182SThomas Petazzoni /* Mask all ethernet port interrupts */ 3587db488c10SGregory CLEMENT on_each_cpu(mvneta_percpu_mask_interrupt, pp, true); 3588c5aff182SThomas Petazzoni 3589c5aff182SThomas Petazzoni mvneta_tx_reset(pp); 3590c5aff182SThomas Petazzoni mvneta_rx_reset(pp); 3591a10c1c81SRussell King 3592a10c1c81SRussell King WARN_ON(phy_power_off(pp->comphy)); 3593c5aff182SThomas Petazzoni } 3594c5aff182SThomas Petazzoni 3595db5dd0dbSMarcin Wojtas static void mvneta_percpu_enable(void *arg) 3596db5dd0dbSMarcin Wojtas { 3597db5dd0dbSMarcin Wojtas struct mvneta_port *pp = arg; 3598db5dd0dbSMarcin Wojtas 3599db5dd0dbSMarcin Wojtas enable_percpu_irq(pp->dev->irq, IRQ_TYPE_NONE); 3600db5dd0dbSMarcin Wojtas } 3601db5dd0dbSMarcin Wojtas 3602db5dd0dbSMarcin Wojtas static void mvneta_percpu_disable(void *arg) 3603db5dd0dbSMarcin Wojtas { 3604db5dd0dbSMarcin Wojtas struct mvneta_port *pp = arg; 3605db5dd0dbSMarcin Wojtas 3606db5dd0dbSMarcin Wojtas disable_percpu_irq(pp->dev->irq); 3607db5dd0dbSMarcin Wojtas } 3608db5dd0dbSMarcin Wojtas 3609c5aff182SThomas Petazzoni /* Change the device mtu */ 3610c5aff182SThomas Petazzoni static int mvneta_change_mtu(struct net_device *dev, int mtu) 3611c5aff182SThomas Petazzoni { 3612c5aff182SThomas Petazzoni struct mvneta_port *pp = netdev_priv(dev); 3613c5aff182SThomas Petazzoni int ret; 3614c5aff182SThomas Petazzoni 36155777987eSJarod Wilson if (!IS_ALIGNED(MVNETA_RX_PKT_SIZE(mtu), 8)) { 36165777987eSJarod Wilson netdev_info(dev, "Illegal MTU value %d, rounding to %d\n", 36175777987eSJarod Wilson mtu, ALIGN(MVNETA_RX_PKT_SIZE(mtu), 8)); 36185777987eSJarod Wilson mtu = ALIGN(MVNETA_RX_PKT_SIZE(mtu), 8); 36195777987eSJarod Wilson } 3620c5aff182SThomas Petazzoni 36210db51da7SLorenzo Bianconi if (pp->xdp_prog && mtu > MVNETA_MAX_RX_BUF_SIZE) { 36220db51da7SLorenzo Bianconi netdev_info(dev, "Illegal MTU value %d for XDP mode\n", mtu); 36230db51da7SLorenzo Bianconi return -EINVAL; 36240db51da7SLorenzo Bianconi } 36250db51da7SLorenzo Bianconi 3626c5aff182SThomas Petazzoni dev->mtu = mtu; 3627c5aff182SThomas Petazzoni 3628b65657fcSSimon Guinot if (!netif_running(dev)) { 3629dc35a10fSMarcin Wojtas if (pp->bm_priv) 3630dc35a10fSMarcin Wojtas mvneta_bm_update_mtu(pp, mtu); 3631dc35a10fSMarcin Wojtas 3632b65657fcSSimon Guinot netdev_update_features(dev); 3633c5aff182SThomas Petazzoni return 0; 3634b65657fcSSimon Guinot } 3635c5aff182SThomas Petazzoni 36366a20c175SThomas Petazzoni /* The interface is running, so we have to force a 3637a92dbd96SEzequiel Garcia * reallocation of the queues 3638c5aff182SThomas Petazzoni */ 3639c5aff182SThomas Petazzoni mvneta_stop_dev(pp); 3640db5dd0dbSMarcin Wojtas on_each_cpu(mvneta_percpu_disable, pp, true); 3641c5aff182SThomas Petazzoni 3642c5aff182SThomas Petazzoni mvneta_cleanup_txqs(pp); 3643c5aff182SThomas Petazzoni mvneta_cleanup_rxqs(pp); 3644c5aff182SThomas Petazzoni 3645dc35a10fSMarcin Wojtas if (pp->bm_priv) 3646dc35a10fSMarcin Wojtas mvneta_bm_update_mtu(pp, mtu); 3647dc35a10fSMarcin Wojtas 3648a92dbd96SEzequiel Garcia pp->pkt_size = MVNETA_RX_PKT_SIZE(dev->mtu); 3649c5aff182SThomas Petazzoni 3650c5aff182SThomas Petazzoni ret = mvneta_setup_rxqs(pp); 3651c5aff182SThomas Petazzoni if (ret) { 3652a92dbd96SEzequiel Garcia netdev_err(dev, "unable to setup rxqs after MTU change\n"); 3653c5aff182SThomas Petazzoni return ret; 3654c5aff182SThomas Petazzoni } 3655c5aff182SThomas Petazzoni 3656a92dbd96SEzequiel Garcia ret = mvneta_setup_txqs(pp); 3657a92dbd96SEzequiel Garcia if (ret) { 3658a92dbd96SEzequiel Garcia netdev_err(dev, "unable to setup txqs after MTU change\n"); 3659a92dbd96SEzequiel Garcia return ret; 3660a92dbd96SEzequiel Garcia } 3661c5aff182SThomas Petazzoni 3662db5dd0dbSMarcin Wojtas on_each_cpu(mvneta_percpu_enable, pp, true); 3663c5aff182SThomas Petazzoni mvneta_start_dev(pp); 3664c5aff182SThomas Petazzoni 3665b65657fcSSimon Guinot netdev_update_features(dev); 3666b65657fcSSimon Guinot 3667c5aff182SThomas Petazzoni return 0; 3668c5aff182SThomas Petazzoni } 3669c5aff182SThomas Petazzoni 3670b65657fcSSimon Guinot static netdev_features_t mvneta_fix_features(struct net_device *dev, 3671b65657fcSSimon Guinot netdev_features_t features) 3672b65657fcSSimon Guinot { 3673b65657fcSSimon Guinot struct mvneta_port *pp = netdev_priv(dev); 3674b65657fcSSimon Guinot 3675b65657fcSSimon Guinot if (pp->tx_csum_limit && dev->mtu > pp->tx_csum_limit) { 3676b65657fcSSimon Guinot features &= ~(NETIF_F_IP_CSUM | NETIF_F_TSO); 3677b65657fcSSimon Guinot netdev_info(dev, 3678b65657fcSSimon Guinot "Disable IP checksum for MTU greater than %dB\n", 3679b65657fcSSimon Guinot pp->tx_csum_limit); 3680b65657fcSSimon Guinot } 3681b65657fcSSimon Guinot 3682b65657fcSSimon Guinot return features; 3683b65657fcSSimon Guinot } 3684b65657fcSSimon Guinot 36858cc3e439SThomas Petazzoni /* Get mac address */ 36868cc3e439SThomas Petazzoni static void mvneta_get_mac_addr(struct mvneta_port *pp, unsigned char *addr) 36878cc3e439SThomas Petazzoni { 36888cc3e439SThomas Petazzoni u32 mac_addr_l, mac_addr_h; 36898cc3e439SThomas Petazzoni 36908cc3e439SThomas Petazzoni mac_addr_l = mvreg_read(pp, MVNETA_MAC_ADDR_LOW); 36918cc3e439SThomas Petazzoni mac_addr_h = mvreg_read(pp, MVNETA_MAC_ADDR_HIGH); 36928cc3e439SThomas Petazzoni addr[0] = (mac_addr_h >> 24) & 0xFF; 36938cc3e439SThomas Petazzoni addr[1] = (mac_addr_h >> 16) & 0xFF; 36948cc3e439SThomas Petazzoni addr[2] = (mac_addr_h >> 8) & 0xFF; 36958cc3e439SThomas Petazzoni addr[3] = mac_addr_h & 0xFF; 36968cc3e439SThomas Petazzoni addr[4] = (mac_addr_l >> 8) & 0xFF; 36978cc3e439SThomas Petazzoni addr[5] = mac_addr_l & 0xFF; 36988cc3e439SThomas Petazzoni } 36998cc3e439SThomas Petazzoni 3700c5aff182SThomas Petazzoni /* Handle setting mac address */ 3701c5aff182SThomas Petazzoni static int mvneta_set_mac_addr(struct net_device *dev, void *addr) 3702c5aff182SThomas Petazzoni { 3703c5aff182SThomas Petazzoni struct mvneta_port *pp = netdev_priv(dev); 3704e68de360SEzequiel Garcia struct sockaddr *sockaddr = addr; 3705e68de360SEzequiel Garcia int ret; 3706c5aff182SThomas Petazzoni 3707e68de360SEzequiel Garcia ret = eth_prepare_mac_addr_change(dev, addr); 3708e68de360SEzequiel Garcia if (ret < 0) 3709e68de360SEzequiel Garcia return ret; 3710c5aff182SThomas Petazzoni /* Remove previous address table entry */ 3711c5aff182SThomas Petazzoni mvneta_mac_addr_set(pp, dev->dev_addr, -1); 3712c5aff182SThomas Petazzoni 3713c5aff182SThomas Petazzoni /* Set new addr in hw */ 371490b74c01SGregory CLEMENT mvneta_mac_addr_set(pp, sockaddr->sa_data, pp->rxq_def); 3715c5aff182SThomas Petazzoni 3716e68de360SEzequiel Garcia eth_commit_mac_addr_change(dev, addr); 3717c5aff182SThomas Petazzoni return 0; 3718c5aff182SThomas Petazzoni } 3719c5aff182SThomas Petazzoni 372044cc27e4SIoana Ciornei static void mvneta_validate(struct phylink_config *config, 372144cc27e4SIoana Ciornei unsigned long *supported, 3722503f9aa9SRussell King struct phylink_link_state *state) 3723503f9aa9SRussell King { 372444cc27e4SIoana Ciornei struct net_device *ndev = to_net_dev(config->dev); 3725a10c1c81SRussell King struct mvneta_port *pp = netdev_priv(ndev); 3726503f9aa9SRussell King __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, }; 3727503f9aa9SRussell King 372822f4bf8aSRussell King /* We only support QSGMII, SGMII, 802.3z and RGMII modes */ 3729503f9aa9SRussell King if (state->interface != PHY_INTERFACE_MODE_NA && 3730503f9aa9SRussell King state->interface != PHY_INTERFACE_MODE_QSGMII && 3731503f9aa9SRussell King state->interface != PHY_INTERFACE_MODE_SGMII && 373222f4bf8aSRussell King !phy_interface_mode_is_8023z(state->interface) && 3733503f9aa9SRussell King !phy_interface_mode_is_rgmii(state->interface)) { 3734503f9aa9SRussell King bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS); 3735503f9aa9SRussell King return; 3736503f9aa9SRussell King } 3737503f9aa9SRussell King 3738503f9aa9SRussell King /* Allow all the expected bits */ 3739503f9aa9SRussell King phylink_set(mask, Autoneg); 3740503f9aa9SRussell King phylink_set_port_modes(mask); 3741503f9aa9SRussell King 37424932a918SRussell King /* Asymmetric pause is unsupported */ 37434932a918SRussell King phylink_set(mask, Pause); 3744da58a931SMaxime Chevallier 374583e65df6SMaxime Chevallier /* Half-duplex at speeds higher than 100Mbit is unsupported */ 3746a10c1c81SRussell King if (pp->comphy || state->interface != PHY_INTERFACE_MODE_2500BASEX) { 3747503f9aa9SRussell King phylink_set(mask, 1000baseT_Full); 3748503f9aa9SRussell King phylink_set(mask, 1000baseX_Full); 3749a10c1c81SRussell King } 3750a10c1c81SRussell King if (pp->comphy || state->interface == PHY_INTERFACE_MODE_2500BASEX) { 3751eda3d1b0SMaxime Chevallier phylink_set(mask, 2500baseT_Full); 3752a10c1c81SRussell King phylink_set(mask, 2500baseX_Full); 3753a10c1c81SRussell King } 375422f4bf8aSRussell King 375522f4bf8aSRussell King if (!phy_interface_mode_is_8023z(state->interface)) { 375622f4bf8aSRussell King /* 10M and 100M are only supported in non-802.3z mode */ 3757503f9aa9SRussell King phylink_set(mask, 10baseT_Half); 3758503f9aa9SRussell King phylink_set(mask, 10baseT_Full); 3759503f9aa9SRussell King phylink_set(mask, 100baseT_Half); 3760503f9aa9SRussell King phylink_set(mask, 100baseT_Full); 376122f4bf8aSRussell King } 3762503f9aa9SRussell King 3763503f9aa9SRussell King bitmap_and(supported, supported, mask, 3764503f9aa9SRussell King __ETHTOOL_LINK_MODE_MASK_NBITS); 3765503f9aa9SRussell King bitmap_and(state->advertising, state->advertising, mask, 3766503f9aa9SRussell King __ETHTOOL_LINK_MODE_MASK_NBITS); 3767a10c1c81SRussell King 3768a10c1c81SRussell King /* We can only operate at 2500BaseX or 1000BaseX. If requested 3769a10c1c81SRussell King * to advertise both, only report advertising at 2500BaseX. 3770a10c1c81SRussell King */ 3771a10c1c81SRussell King phylink_helper_basex_speed(state); 3772503f9aa9SRussell King } 3773503f9aa9SRussell King 3774d46b7e4fSRussell King static void mvneta_mac_pcs_get_state(struct phylink_config *config, 3775503f9aa9SRussell King struct phylink_link_state *state) 3776c5aff182SThomas Petazzoni { 377744cc27e4SIoana Ciornei struct net_device *ndev = to_net_dev(config->dev); 3778c5aff182SThomas Petazzoni struct mvneta_port *pp = netdev_priv(ndev); 3779503f9aa9SRussell King u32 gmac_stat; 3780c5aff182SThomas Petazzoni 3781503f9aa9SRussell King gmac_stat = mvreg_read(pp, MVNETA_GMAC_STATUS); 3782503f9aa9SRussell King 3783503f9aa9SRussell King if (gmac_stat & MVNETA_GMAC_SPEED_1000) 3784a10c1c81SRussell King state->speed = 3785a10c1c81SRussell King state->interface == PHY_INTERFACE_MODE_2500BASEX ? 3786a10c1c81SRussell King SPEED_2500 : SPEED_1000; 3787503f9aa9SRussell King else if (gmac_stat & MVNETA_GMAC_SPEED_100) 3788503f9aa9SRussell King state->speed = SPEED_100; 3789503f9aa9SRussell King else 3790503f9aa9SRussell King state->speed = SPEED_10; 3791503f9aa9SRussell King 3792503f9aa9SRussell King state->an_complete = !!(gmac_stat & MVNETA_GMAC_AN_COMPLETE); 3793503f9aa9SRussell King state->link = !!(gmac_stat & MVNETA_GMAC_LINK_UP); 3794503f9aa9SRussell King state->duplex = !!(gmac_stat & MVNETA_GMAC_FULL_DUPLEX); 3795503f9aa9SRussell King 3796503f9aa9SRussell King state->pause = 0; 37974932a918SRussell King if (gmac_stat & MVNETA_GMAC_RX_FLOW_CTRL_ENABLE) 37984932a918SRussell King state->pause |= MLO_PAUSE_RX; 37994932a918SRussell King if (gmac_stat & MVNETA_GMAC_TX_FLOW_CTRL_ENABLE) 38004932a918SRussell King state->pause |= MLO_PAUSE_TX; 3801503f9aa9SRussell King } 3802503f9aa9SRussell King 380344cc27e4SIoana Ciornei static void mvneta_mac_an_restart(struct phylink_config *config) 380422f4bf8aSRussell King { 380544cc27e4SIoana Ciornei struct net_device *ndev = to_net_dev(config->dev); 380622f4bf8aSRussell King struct mvneta_port *pp = netdev_priv(ndev); 380722f4bf8aSRussell King u32 gmac_an = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG); 380822f4bf8aSRussell King 380922f4bf8aSRussell King mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, 381022f4bf8aSRussell King gmac_an | MVNETA_GMAC_INBAND_RESTART_AN); 381122f4bf8aSRussell King mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, 381222f4bf8aSRussell King gmac_an & ~MVNETA_GMAC_INBAND_RESTART_AN); 381322f4bf8aSRussell King } 381422f4bf8aSRussell King 381544cc27e4SIoana Ciornei static void mvneta_mac_config(struct phylink_config *config, unsigned int mode, 3816503f9aa9SRussell King const struct phylink_link_state *state) 3817503f9aa9SRussell King { 381844cc27e4SIoana Ciornei struct net_device *ndev = to_net_dev(config->dev); 3819503f9aa9SRussell King struct mvneta_port *pp = netdev_priv(ndev); 382022f4bf8aSRussell King u32 new_ctrl0, gmac_ctrl0 = mvreg_read(pp, MVNETA_GMAC_CTRL_0); 3821503f9aa9SRussell King u32 new_ctrl2, gmac_ctrl2 = mvreg_read(pp, MVNETA_GMAC_CTRL_2); 3822da58a931SMaxime Chevallier u32 new_ctrl4, gmac_ctrl4 = mvreg_read(pp, MVNETA_GMAC_CTRL_4); 3823503f9aa9SRussell King u32 new_clk, gmac_clk = mvreg_read(pp, MVNETA_GMAC_CLOCK_DIVIDER); 3824503f9aa9SRussell King u32 new_an, gmac_an = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG); 3825503f9aa9SRussell King 382622f4bf8aSRussell King new_ctrl0 = gmac_ctrl0 & ~MVNETA_GMAC0_PORT_1000BASE_X; 382732699954SRussell King new_ctrl2 = gmac_ctrl2 & ~(MVNETA_GMAC2_INBAND_AN_ENABLE | 382832699954SRussell King MVNETA_GMAC2_PORT_RESET); 3829da58a931SMaxime Chevallier new_ctrl4 = gmac_ctrl4 & ~(MVNETA_GMAC4_SHORT_PREAMBLE_ENABLE); 3830503f9aa9SRussell King new_clk = gmac_clk & ~MVNETA_GMAC_1MS_CLOCK_ENABLE; 3831503f9aa9SRussell King new_an = gmac_an & ~(MVNETA_GMAC_INBAND_AN_ENABLE | 3832503f9aa9SRussell King MVNETA_GMAC_INBAND_RESTART_AN | 3833503f9aa9SRussell King MVNETA_GMAC_CONFIG_MII_SPEED | 3834c5aff182SThomas Petazzoni MVNETA_GMAC_CONFIG_GMII_SPEED | 3835503f9aa9SRussell King MVNETA_GMAC_AN_SPEED_EN | 383622f4bf8aSRussell King MVNETA_GMAC_ADVERT_SYM_FLOW_CTRL | 383722f4bf8aSRussell King MVNETA_GMAC_CONFIG_FLOW_CTRL | 3838503f9aa9SRussell King MVNETA_GMAC_AN_FLOW_CTRL_EN | 3839503f9aa9SRussell King MVNETA_GMAC_CONFIG_FULL_DUPLEX | 3840503f9aa9SRussell King MVNETA_GMAC_AN_DUPLEX_EN); 3841c5aff182SThomas Petazzoni 384232699954SRussell King /* Even though it might look weird, when we're configured in 384332699954SRussell King * SGMII or QSGMII mode, the RGMII bit needs to be set. 384432699954SRussell King */ 384532699954SRussell King new_ctrl2 |= MVNETA_GMAC2_PORT_RGMII; 384632699954SRussell King 384732699954SRussell King if (state->interface == PHY_INTERFACE_MODE_QSGMII || 384822f4bf8aSRussell King state->interface == PHY_INTERFACE_MODE_SGMII || 384922f4bf8aSRussell King phy_interface_mode_is_8023z(state->interface)) 385032699954SRussell King new_ctrl2 |= MVNETA_GMAC2_PCS_ENABLE; 385132699954SRussell King 38524932a918SRussell King if (phylink_test(state->advertising, Pause)) 38534932a918SRussell King new_an |= MVNETA_GMAC_ADVERT_SYM_FLOW_CTRL; 38544932a918SRussell King if (state->pause & MLO_PAUSE_TXRX_MASK) 38554932a918SRussell King new_an |= MVNETA_GMAC_CONFIG_FLOW_CTRL; 38564932a918SRussell King 3857503f9aa9SRussell King if (!phylink_autoneg_inband(mode)) { 3858503f9aa9SRussell King /* Phy or fixed speed */ 3859503f9aa9SRussell King if (state->duplex) 3860503f9aa9SRussell King new_an |= MVNETA_GMAC_CONFIG_FULL_DUPLEX; 3861c5aff182SThomas Petazzoni 3862da58a931SMaxime Chevallier if (state->speed == SPEED_1000 || state->speed == SPEED_2500) 3863503f9aa9SRussell King new_an |= MVNETA_GMAC_CONFIG_GMII_SPEED; 3864503f9aa9SRussell King else if (state->speed == SPEED_100) 3865503f9aa9SRussell King new_an |= MVNETA_GMAC_CONFIG_MII_SPEED; 386622f4bf8aSRussell King } else if (state->interface == PHY_INTERFACE_MODE_SGMII) { 3867503f9aa9SRussell King /* SGMII mode receives the state from the PHY */ 3868503f9aa9SRussell King new_ctrl2 |= MVNETA_GMAC2_INBAND_AN_ENABLE; 3869503f9aa9SRussell King new_clk |= MVNETA_GMAC_1MS_CLOCK_ENABLE; 3870503f9aa9SRussell King new_an = (new_an & ~(MVNETA_GMAC_FORCE_LINK_DOWN | 3871503f9aa9SRussell King MVNETA_GMAC_FORCE_LINK_PASS)) | 3872503f9aa9SRussell King MVNETA_GMAC_INBAND_AN_ENABLE | 3873503f9aa9SRussell King MVNETA_GMAC_AN_SPEED_EN | 3874503f9aa9SRussell King MVNETA_GMAC_AN_DUPLEX_EN; 387522f4bf8aSRussell King } else { 387622f4bf8aSRussell King /* 802.3z negotiation - only 1000base-X */ 387722f4bf8aSRussell King new_ctrl0 |= MVNETA_GMAC0_PORT_1000BASE_X; 387822f4bf8aSRussell King new_clk |= MVNETA_GMAC_1MS_CLOCK_ENABLE; 387922f4bf8aSRussell King new_an = (new_an & ~(MVNETA_GMAC_FORCE_LINK_DOWN | 388022f4bf8aSRussell King MVNETA_GMAC_FORCE_LINK_PASS)) | 388122f4bf8aSRussell King MVNETA_GMAC_INBAND_AN_ENABLE | 388222f4bf8aSRussell King MVNETA_GMAC_CONFIG_GMII_SPEED | 388322f4bf8aSRussell King /* The MAC only supports FD mode */ 388422f4bf8aSRussell King MVNETA_GMAC_CONFIG_FULL_DUPLEX; 38854932a918SRussell King 38864932a918SRussell King if (state->pause & MLO_PAUSE_AN && state->an_enabled) 38874932a918SRussell King new_an |= MVNETA_GMAC_AN_FLOW_CTRL_EN; 3888c5aff182SThomas Petazzoni } 3889c5aff182SThomas Petazzoni 3890503f9aa9SRussell King /* Armada 370 documentation says we can only change the port mode 3891503f9aa9SRussell King * and in-band enable when the link is down, so force it down 3892503f9aa9SRussell King * while making these changes. We also do this for GMAC_CTRL2 */ 389322f4bf8aSRussell King if ((new_ctrl0 ^ gmac_ctrl0) & MVNETA_GMAC0_PORT_1000BASE_X || 389422f4bf8aSRussell King (new_ctrl2 ^ gmac_ctrl2) & MVNETA_GMAC2_INBAND_AN_ENABLE || 3895503f9aa9SRussell King (new_an ^ gmac_an) & MVNETA_GMAC_INBAND_AN_ENABLE) { 3896503f9aa9SRussell King mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, 3897503f9aa9SRussell King (gmac_an & ~MVNETA_GMAC_FORCE_LINK_PASS) | 3898503f9aa9SRussell King MVNETA_GMAC_FORCE_LINK_DOWN); 3899503f9aa9SRussell King } 3900503f9aa9SRussell King 3901a10c1c81SRussell King 3902da58a931SMaxime Chevallier /* When at 2.5G, the link partner can send frames with shortened 3903da58a931SMaxime Chevallier * preambles. 3904da58a931SMaxime Chevallier */ 3905da58a931SMaxime Chevallier if (state->speed == SPEED_2500) 3906da58a931SMaxime Chevallier new_ctrl4 |= MVNETA_GMAC4_SHORT_PREAMBLE_ENABLE; 3907da58a931SMaxime Chevallier 3908031b922bSMarek Behún if (pp->comphy && pp->phy_interface != state->interface && 3909a10c1c81SRussell King (state->interface == PHY_INTERFACE_MODE_SGMII || 3910a10c1c81SRussell King state->interface == PHY_INTERFACE_MODE_1000BASEX || 3911031b922bSMarek Behún state->interface == PHY_INTERFACE_MODE_2500BASEX)) { 3912031b922bSMarek Behún pp->phy_interface = state->interface; 3913031b922bSMarek Behún 3914031b922bSMarek Behún WARN_ON(phy_power_off(pp->comphy)); 3915031b922bSMarek Behún WARN_ON(mvneta_comphy_init(pp)); 3916031b922bSMarek Behún } 3917a10c1c81SRussell King 391822f4bf8aSRussell King if (new_ctrl0 != gmac_ctrl0) 391922f4bf8aSRussell King mvreg_write(pp, MVNETA_GMAC_CTRL_0, new_ctrl0); 3920503f9aa9SRussell King if (new_ctrl2 != gmac_ctrl2) 3921503f9aa9SRussell King mvreg_write(pp, MVNETA_GMAC_CTRL_2, new_ctrl2); 3922da58a931SMaxime Chevallier if (new_ctrl4 != gmac_ctrl4) 3923da58a931SMaxime Chevallier mvreg_write(pp, MVNETA_GMAC_CTRL_4, new_ctrl4); 3924503f9aa9SRussell King if (new_clk != gmac_clk) 3925503f9aa9SRussell King mvreg_write(pp, MVNETA_GMAC_CLOCK_DIVIDER, new_clk); 3926503f9aa9SRussell King if (new_an != gmac_an) 3927503f9aa9SRussell King mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, new_an); 392832699954SRussell King 392932699954SRussell King if (gmac_ctrl2 & MVNETA_GMAC2_PORT_RESET) { 393032699954SRussell King while ((mvreg_read(pp, MVNETA_GMAC_CTRL_2) & 393132699954SRussell King MVNETA_GMAC2_PORT_RESET) != 0) 393232699954SRussell King continue; 393332699954SRussell King } 3934503f9aa9SRussell King } 3935503f9aa9SRussell King 39366d81f451SRussell King static void mvneta_set_eee(struct mvneta_port *pp, bool enable) 39376d81f451SRussell King { 39386d81f451SRussell King u32 lpi_ctl1; 39396d81f451SRussell King 39406d81f451SRussell King lpi_ctl1 = mvreg_read(pp, MVNETA_LPI_CTRL_1); 39416d81f451SRussell King if (enable) 39426d81f451SRussell King lpi_ctl1 |= MVNETA_LPI_REQUEST_ENABLE; 39436d81f451SRussell King else 39446d81f451SRussell King lpi_ctl1 &= ~MVNETA_LPI_REQUEST_ENABLE; 39456d81f451SRussell King mvreg_write(pp, MVNETA_LPI_CTRL_1, lpi_ctl1); 39466d81f451SRussell King } 39476d81f451SRussell King 394844cc27e4SIoana Ciornei static void mvneta_mac_link_down(struct phylink_config *config, 394944cc27e4SIoana Ciornei unsigned int mode, phy_interface_t interface) 3950fc548b99SRussell King { 395144cc27e4SIoana Ciornei struct net_device *ndev = to_net_dev(config->dev); 3952fc548b99SRussell King struct mvneta_port *pp = netdev_priv(ndev); 3953fc548b99SRussell King u32 val; 3954fc548b99SRussell King 3955503f9aa9SRussell King mvneta_port_down(pp); 3956503f9aa9SRussell King 3957503f9aa9SRussell King if (!phylink_autoneg_inband(mode)) { 3958fc548b99SRussell King val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG); 3959fc548b99SRussell King val &= ~MVNETA_GMAC_FORCE_LINK_PASS; 3960fc548b99SRussell King val |= MVNETA_GMAC_FORCE_LINK_DOWN; 3961fc548b99SRussell King mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val); 3962fc548b99SRussell King } 39636d81f451SRussell King 39646d81f451SRussell King pp->eee_active = false; 39656d81f451SRussell King mvneta_set_eee(pp, false); 3966fc548b99SRussell King } 3967fc548b99SRussell King 396844cc27e4SIoana Ciornei static void mvneta_mac_link_up(struct phylink_config *config, unsigned int mode, 3969c6ab3008SFlorian Fainelli phy_interface_t interface, 3970503f9aa9SRussell King struct phy_device *phy) 3971fc548b99SRussell King { 397244cc27e4SIoana Ciornei struct net_device *ndev = to_net_dev(config->dev); 3973fc548b99SRussell King struct mvneta_port *pp = netdev_priv(ndev); 3974fc548b99SRussell King u32 val; 3975fc548b99SRussell King 3976503f9aa9SRussell King if (!phylink_autoneg_inband(mode)) { 3977fc548b99SRussell King val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG); 3978fc548b99SRussell King val &= ~MVNETA_GMAC_FORCE_LINK_DOWN; 3979fc548b99SRussell King val |= MVNETA_GMAC_FORCE_LINK_PASS; 3980fc548b99SRussell King mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val); 3981fc548b99SRussell King } 3982fc548b99SRussell King 3983fc548b99SRussell King mvneta_port_up(pp); 39846d81f451SRussell King 39856d81f451SRussell King if (phy && pp->eee_enabled) { 39866d81f451SRussell King pp->eee_active = phy_init_eee(phy, 0) >= 0; 39876d81f451SRussell King mvneta_set_eee(pp, pp->eee_active && pp->tx_lpi_enabled); 39886d81f451SRussell King } 3989fc548b99SRussell King } 3990fc548b99SRussell King 3991503f9aa9SRussell King static const struct phylink_mac_ops mvneta_phylink_ops = { 3992503f9aa9SRussell King .validate = mvneta_validate, 3993d46b7e4fSRussell King .mac_pcs_get_state = mvneta_mac_pcs_get_state, 399422f4bf8aSRussell King .mac_an_restart = mvneta_mac_an_restart, 3995503f9aa9SRussell King .mac_config = mvneta_mac_config, 3996503f9aa9SRussell King .mac_link_down = mvneta_mac_link_down, 3997503f9aa9SRussell King .mac_link_up = mvneta_mac_link_up, 3998503f9aa9SRussell King }; 3999c5aff182SThomas Petazzoni 4000c5aff182SThomas Petazzoni static int mvneta_mdio_probe(struct mvneta_port *pp) 4001c5aff182SThomas Petazzoni { 400282960fffSJisheng Zhang struct ethtool_wolinfo wol = { .cmd = ETHTOOL_GWOL }; 4003503f9aa9SRussell King int err = phylink_of_phy_connect(pp->phylink, pp->dn, 0); 4004c5aff182SThomas Petazzoni 4005503f9aa9SRussell King if (err) 4006503f9aa9SRussell King netdev_err(pp->dev, "could not attach PHY: %d\n", err); 4007c5aff182SThomas Petazzoni 4008503f9aa9SRussell King phylink_ethtool_get_wol(pp->phylink, &wol); 400982960fffSJisheng Zhang device_set_wakeup_capable(&pp->dev->dev, !!wol.supported); 401082960fffSJisheng Zhang 4011503f9aa9SRussell King return err; 4012c5aff182SThomas Petazzoni } 4013c5aff182SThomas Petazzoni 4014c5aff182SThomas Petazzoni static void mvneta_mdio_remove(struct mvneta_port *pp) 4015c5aff182SThomas Petazzoni { 4016503f9aa9SRussell King phylink_disconnect_phy(pp->phylink); 4017c5aff182SThomas Petazzoni } 4018c5aff182SThomas Petazzoni 4019120cfa50SGregory CLEMENT /* Electing a CPU must be done in an atomic way: it should be done 4020120cfa50SGregory CLEMENT * after or before the removal/insertion of a CPU and this function is 4021120cfa50SGregory CLEMENT * not reentrant. 4022120cfa50SGregory CLEMENT */ 4023f8642885SMaxime Ripard static void mvneta_percpu_elect(struct mvneta_port *pp) 4024f8642885SMaxime Ripard { 4025cad5d847SGregory CLEMENT int elected_cpu = 0, max_cpu, cpu, i = 0; 4026f8642885SMaxime Ripard 4027cad5d847SGregory CLEMENT /* Use the cpu associated to the rxq when it is online, in all 4028cad5d847SGregory CLEMENT * the other cases, use the cpu 0 which can't be offline. 4029cad5d847SGregory CLEMENT */ 4030cad5d847SGregory CLEMENT if (cpu_online(pp->rxq_def)) 4031cad5d847SGregory CLEMENT elected_cpu = pp->rxq_def; 4032cad5d847SGregory CLEMENT 40332dcf75e2SGregory CLEMENT max_cpu = num_present_cpus(); 4034f8642885SMaxime Ripard 4035f8642885SMaxime Ripard for_each_online_cpu(cpu) { 40362dcf75e2SGregory CLEMENT int rxq_map = 0, txq_map = 0; 40372dcf75e2SGregory CLEMENT int rxq; 40382dcf75e2SGregory CLEMENT 40392dcf75e2SGregory CLEMENT for (rxq = 0; rxq < rxq_number; rxq++) 40402dcf75e2SGregory CLEMENT if ((rxq % max_cpu) == cpu) 40412dcf75e2SGregory CLEMENT rxq_map |= MVNETA_CPU_RXQ_ACCESS(rxq); 40422dcf75e2SGregory CLEMENT 4043cad5d847SGregory CLEMENT if (cpu == elected_cpu) 404450bf8cb6SGregory CLEMENT /* Map the default receive queue queue to the 404550bf8cb6SGregory CLEMENT * elected CPU 4046f8642885SMaxime Ripard */ 40472dcf75e2SGregory CLEMENT rxq_map |= MVNETA_CPU_RXQ_ACCESS(pp->rxq_def); 404850bf8cb6SGregory CLEMENT 404950bf8cb6SGregory CLEMENT /* We update the TX queue map only if we have one 405050bf8cb6SGregory CLEMENT * queue. In this case we associate the TX queue to 405150bf8cb6SGregory CLEMENT * the CPU bound to the default RX queue 405250bf8cb6SGregory CLEMENT */ 405350bf8cb6SGregory CLEMENT if (txq_number == 1) 4054cad5d847SGregory CLEMENT txq_map = (cpu == elected_cpu) ? 405550bf8cb6SGregory CLEMENT MVNETA_CPU_TXQ_ACCESS(1) : 0; 405650bf8cb6SGregory CLEMENT else 405750bf8cb6SGregory CLEMENT txq_map = mvreg_read(pp, MVNETA_CPU_MAP(cpu)) & 405850bf8cb6SGregory CLEMENT MVNETA_CPU_TXQ_ACCESS_ALL_MASK; 405950bf8cb6SGregory CLEMENT 40602dcf75e2SGregory CLEMENT mvreg_write(pp, MVNETA_CPU_MAP(cpu), rxq_map | txq_map); 40612dcf75e2SGregory CLEMENT 40622dcf75e2SGregory CLEMENT /* Update the interrupt mask on each CPU according the 40632dcf75e2SGregory CLEMENT * new mapping 40642dcf75e2SGregory CLEMENT */ 40652dcf75e2SGregory CLEMENT smp_call_function_single(cpu, mvneta_percpu_unmask_interrupt, 4066f8642885SMaxime Ripard pp, true); 4067f8642885SMaxime Ripard i++; 40682dcf75e2SGregory CLEMENT 4069f8642885SMaxime Ripard } 4070f8642885SMaxime Ripard }; 4071f8642885SMaxime Ripard 407284a3f4dbSSebastian Andrzej Siewior static int mvneta_cpu_online(unsigned int cpu, struct hlist_node *node) 4073f8642885SMaxime Ripard { 407484a3f4dbSSebastian Andrzej Siewior int other_cpu; 407584a3f4dbSSebastian Andrzej Siewior struct mvneta_port *pp = hlist_entry_safe(node, struct mvneta_port, 407684a3f4dbSSebastian Andrzej Siewior node_online); 4077f8642885SMaxime Ripard struct mvneta_pcpu_port *port = per_cpu_ptr(pp->ports, cpu); 4078f8642885SMaxime Ripard 407984a3f4dbSSebastian Andrzej Siewior 4080120cfa50SGregory CLEMENT spin_lock(&pp->lock); 408184a3f4dbSSebastian Andrzej Siewior /* 408284a3f4dbSSebastian Andrzej Siewior * Configuring the driver for a new CPU while the driver is 408384a3f4dbSSebastian Andrzej Siewior * stopping is racy, so just avoid it. 4084120cfa50SGregory CLEMENT */ 4085120cfa50SGregory CLEMENT if (pp->is_stopped) { 4086120cfa50SGregory CLEMENT spin_unlock(&pp->lock); 408784a3f4dbSSebastian Andrzej Siewior return 0; 4088120cfa50SGregory CLEMENT } 4089f8642885SMaxime Ripard netif_tx_stop_all_queues(pp->dev); 4090f8642885SMaxime Ripard 409184a3f4dbSSebastian Andrzej Siewior /* 409284a3f4dbSSebastian Andrzej Siewior * We have to synchronise on tha napi of each CPU except the one 409384a3f4dbSSebastian Andrzej Siewior * just being woken up 4094f8642885SMaxime Ripard */ 4095f8642885SMaxime Ripard for_each_online_cpu(other_cpu) { 4096f8642885SMaxime Ripard if (other_cpu != cpu) { 4097f8642885SMaxime Ripard struct mvneta_pcpu_port *other_port = 4098f8642885SMaxime Ripard per_cpu_ptr(pp->ports, other_cpu); 4099f8642885SMaxime Ripard 4100f8642885SMaxime Ripard napi_synchronize(&other_port->napi); 4101f8642885SMaxime Ripard } 4102f8642885SMaxime Ripard } 4103f8642885SMaxime Ripard 4104f8642885SMaxime Ripard /* Mask all ethernet port interrupts */ 4105db488c10SGregory CLEMENT on_each_cpu(mvneta_percpu_mask_interrupt, pp, true); 4106f8642885SMaxime Ripard napi_enable(&port->napi); 4107f8642885SMaxime Ripard 410884a3f4dbSSebastian Andrzej Siewior /* 410984a3f4dbSSebastian Andrzej Siewior * Enable per-CPU interrupts on the CPU that is 41102dcf75e2SGregory CLEMENT * brought up. 41112dcf75e2SGregory CLEMENT */ 41120e28bf93SAnna-Maria Gleixner mvneta_percpu_enable(pp); 41132dcf75e2SGregory CLEMENT 411484a3f4dbSSebastian Andrzej Siewior /* 411584a3f4dbSSebastian Andrzej Siewior * Enable per-CPU interrupt on the one CPU we care 4116f8642885SMaxime Ripard * about. 4117f8642885SMaxime Ripard */ 4118f8642885SMaxime Ripard mvneta_percpu_elect(pp); 4119f8642885SMaxime Ripard 4120db488c10SGregory CLEMENT /* Unmask all ethernet port interrupts */ 4121db488c10SGregory CLEMENT on_each_cpu(mvneta_percpu_unmask_interrupt, pp, true); 4122f8642885SMaxime Ripard mvreg_write(pp, MVNETA_INTR_MISC_MASK, 4123f8642885SMaxime Ripard MVNETA_CAUSE_PHY_STATUS_CHANGE | 4124856b2cc5SRussell King MVNETA_CAUSE_LINK_CHANGE); 4125f8642885SMaxime Ripard netif_tx_start_all_queues(pp->dev); 4126120cfa50SGregory CLEMENT spin_unlock(&pp->lock); 412784a3f4dbSSebastian Andrzej Siewior return 0; 412884a3f4dbSSebastian Andrzej Siewior } 412984a3f4dbSSebastian Andrzej Siewior 413084a3f4dbSSebastian Andrzej Siewior static int mvneta_cpu_down_prepare(unsigned int cpu, struct hlist_node *node) 413184a3f4dbSSebastian Andrzej Siewior { 413284a3f4dbSSebastian Andrzej Siewior struct mvneta_port *pp = hlist_entry_safe(node, struct mvneta_port, 413384a3f4dbSSebastian Andrzej Siewior node_online); 413484a3f4dbSSebastian Andrzej Siewior struct mvneta_pcpu_port *port = per_cpu_ptr(pp->ports, cpu); 413584a3f4dbSSebastian Andrzej Siewior 413684a3f4dbSSebastian Andrzej Siewior /* 413784a3f4dbSSebastian Andrzej Siewior * Thanks to this lock we are sure that any pending cpu election is 413884a3f4dbSSebastian Andrzej Siewior * done. 41395888511eSGregory CLEMENT */ 41405888511eSGregory CLEMENT spin_lock(&pp->lock); 4141f8642885SMaxime Ripard /* Mask all ethernet port interrupts */ 4142db488c10SGregory CLEMENT on_each_cpu(mvneta_percpu_mask_interrupt, pp, true); 41435888511eSGregory CLEMENT spin_unlock(&pp->lock); 4144f8642885SMaxime Ripard 4145f8642885SMaxime Ripard napi_synchronize(&port->napi); 4146f8642885SMaxime Ripard napi_disable(&port->napi); 414784a3f4dbSSebastian Andrzej Siewior /* Disable per-CPU interrupts on the CPU that is brought down. */ 41480e28bf93SAnna-Maria Gleixner mvneta_percpu_disable(pp); 414984a3f4dbSSebastian Andrzej Siewior return 0; 415084a3f4dbSSebastian Andrzej Siewior } 4151f8642885SMaxime Ripard 415284a3f4dbSSebastian Andrzej Siewior static int mvneta_cpu_dead(unsigned int cpu, struct hlist_node *node) 415384a3f4dbSSebastian Andrzej Siewior { 415484a3f4dbSSebastian Andrzej Siewior struct mvneta_port *pp = hlist_entry_safe(node, struct mvneta_port, 415584a3f4dbSSebastian Andrzej Siewior node_dead); 415684a3f4dbSSebastian Andrzej Siewior 4157f8642885SMaxime Ripard /* Check if a new CPU must be elected now this on is down */ 4158120cfa50SGregory CLEMENT spin_lock(&pp->lock); 4159f8642885SMaxime Ripard mvneta_percpu_elect(pp); 4160120cfa50SGregory CLEMENT spin_unlock(&pp->lock); 4161f8642885SMaxime Ripard /* Unmask all ethernet port interrupts */ 4162db488c10SGregory CLEMENT on_each_cpu(mvneta_percpu_unmask_interrupt, pp, true); 4163f8642885SMaxime Ripard mvreg_write(pp, MVNETA_INTR_MISC_MASK, 4164f8642885SMaxime Ripard MVNETA_CAUSE_PHY_STATUS_CHANGE | 4165856b2cc5SRussell King MVNETA_CAUSE_LINK_CHANGE); 4166f8642885SMaxime Ripard netif_tx_start_all_queues(pp->dev); 416784a3f4dbSSebastian Andrzej Siewior return 0; 4168f8642885SMaxime Ripard } 4169f8642885SMaxime Ripard 4170c5aff182SThomas Petazzoni static int mvneta_open(struct net_device *dev) 4171c5aff182SThomas Petazzoni { 4172c5aff182SThomas Petazzoni struct mvneta_port *pp = netdev_priv(dev); 41736b125d63SGregory CLEMENT int ret; 4174c5aff182SThomas Petazzoni 4175c5aff182SThomas Petazzoni pp->pkt_size = MVNETA_RX_PKT_SIZE(pp->dev->mtu); 4176c5aff182SThomas Petazzoni 4177c5aff182SThomas Petazzoni ret = mvneta_setup_rxqs(pp); 4178c5aff182SThomas Petazzoni if (ret) 4179c5aff182SThomas Petazzoni return ret; 4180c5aff182SThomas Petazzoni 4181c5aff182SThomas Petazzoni ret = mvneta_setup_txqs(pp); 4182c5aff182SThomas Petazzoni if (ret) 4183c5aff182SThomas Petazzoni goto err_cleanup_rxqs; 4184c5aff182SThomas Petazzoni 4185c5aff182SThomas Petazzoni /* Connect to port interrupt line */ 41862636ac3cSMarcin Wojtas if (pp->neta_armada3700) 41872636ac3cSMarcin Wojtas ret = request_irq(pp->dev->irq, mvneta_isr, 0, 41882636ac3cSMarcin Wojtas dev->name, pp); 41892636ac3cSMarcin Wojtas else 41902636ac3cSMarcin Wojtas ret = request_percpu_irq(pp->dev->irq, mvneta_percpu_isr, 41912636ac3cSMarcin Wojtas dev->name, pp->ports); 4192c5aff182SThomas Petazzoni if (ret) { 4193c5aff182SThomas Petazzoni netdev_err(pp->dev, "cannot request irq %d\n", pp->dev->irq); 4194c5aff182SThomas Petazzoni goto err_cleanup_txqs; 4195c5aff182SThomas Petazzoni } 4196c5aff182SThomas Petazzoni 41972636ac3cSMarcin Wojtas if (!pp->neta_armada3700) { 41982dcf75e2SGregory CLEMENT /* Enable per-CPU interrupt on all the CPU to handle our RX 41992dcf75e2SGregory CLEMENT * queue interrupts 42002dcf75e2SGregory CLEMENT */ 42016b125d63SGregory CLEMENT on_each_cpu(mvneta_percpu_enable, pp, true); 42022dcf75e2SGregory CLEMENT 4203120cfa50SGregory CLEMENT pp->is_stopped = false; 4204f8642885SMaxime Ripard /* Register a CPU notifier to handle the case where our CPU 4205f8642885SMaxime Ripard * might be taken offline. 4206f8642885SMaxime Ripard */ 420784a3f4dbSSebastian Andrzej Siewior ret = cpuhp_state_add_instance_nocalls(online_hpstate, 420884a3f4dbSSebastian Andrzej Siewior &pp->node_online); 420984a3f4dbSSebastian Andrzej Siewior if (ret) 421084a3f4dbSSebastian Andrzej Siewior goto err_free_irq; 421184a3f4dbSSebastian Andrzej Siewior 421284a3f4dbSSebastian Andrzej Siewior ret = cpuhp_state_add_instance_nocalls(CPUHP_NET_MVNETA_DEAD, 421384a3f4dbSSebastian Andrzej Siewior &pp->node_dead); 421484a3f4dbSSebastian Andrzej Siewior if (ret) 421584a3f4dbSSebastian Andrzej Siewior goto err_free_online_hp; 42162636ac3cSMarcin Wojtas } 4217f8642885SMaxime Ripard 4218c5aff182SThomas Petazzoni ret = mvneta_mdio_probe(pp); 4219c5aff182SThomas Petazzoni if (ret < 0) { 4220c5aff182SThomas Petazzoni netdev_err(dev, "cannot probe MDIO bus\n"); 422184a3f4dbSSebastian Andrzej Siewior goto err_free_dead_hp; 4222c5aff182SThomas Petazzoni } 4223c5aff182SThomas Petazzoni 4224c5aff182SThomas Petazzoni mvneta_start_dev(pp); 4225c5aff182SThomas Petazzoni 4226c5aff182SThomas Petazzoni return 0; 4227c5aff182SThomas Petazzoni 422884a3f4dbSSebastian Andrzej Siewior err_free_dead_hp: 42292636ac3cSMarcin Wojtas if (!pp->neta_armada3700) 423084a3f4dbSSebastian Andrzej Siewior cpuhp_state_remove_instance_nocalls(CPUHP_NET_MVNETA_DEAD, 423184a3f4dbSSebastian Andrzej Siewior &pp->node_dead); 423284a3f4dbSSebastian Andrzej Siewior err_free_online_hp: 42332636ac3cSMarcin Wojtas if (!pp->neta_armada3700) 42342636ac3cSMarcin Wojtas cpuhp_state_remove_instance_nocalls(online_hpstate, 42352636ac3cSMarcin Wojtas &pp->node_online); 4236c5aff182SThomas Petazzoni err_free_irq: 42372636ac3cSMarcin Wojtas if (pp->neta_armada3700) { 42382636ac3cSMarcin Wojtas free_irq(pp->dev->irq, pp); 42392636ac3cSMarcin Wojtas } else { 42403d8c4530SRussell King - ARM Linux on_each_cpu(mvneta_percpu_disable, pp, true); 424112bb03b4SMaxime Ripard free_percpu_irq(pp->dev->irq, pp->ports); 42422636ac3cSMarcin Wojtas } 4243c5aff182SThomas Petazzoni err_cleanup_txqs: 4244c5aff182SThomas Petazzoni mvneta_cleanup_txqs(pp); 4245c5aff182SThomas Petazzoni err_cleanup_rxqs: 4246c5aff182SThomas Petazzoni mvneta_cleanup_rxqs(pp); 4247c5aff182SThomas Petazzoni return ret; 4248c5aff182SThomas Petazzoni } 4249c5aff182SThomas Petazzoni 4250c5aff182SThomas Petazzoni /* Stop the port, free port interrupt line */ 4251c5aff182SThomas Petazzoni static int mvneta_stop(struct net_device *dev) 4252c5aff182SThomas Petazzoni { 4253c5aff182SThomas Petazzoni struct mvneta_port *pp = netdev_priv(dev); 4254c5aff182SThomas Petazzoni 42552636ac3cSMarcin Wojtas if (!pp->neta_armada3700) { 4256120cfa50SGregory CLEMENT /* Inform that we are stopping so we don't want to setup the 42571c2722a9SGregory CLEMENT * driver for new CPUs in the notifiers. The code of the 42581c2722a9SGregory CLEMENT * notifier for CPU online is protected by the same spinlock, 42591c2722a9SGregory CLEMENT * so when we get the lock, the notifer work is done. 4260120cfa50SGregory CLEMENT */ 4261120cfa50SGregory CLEMENT spin_lock(&pp->lock); 4262120cfa50SGregory CLEMENT pp->is_stopped = true; 42631c2722a9SGregory CLEMENT spin_unlock(&pp->lock); 42641c2722a9SGregory CLEMENT 4265c5aff182SThomas Petazzoni mvneta_stop_dev(pp); 4266c5aff182SThomas Petazzoni mvneta_mdio_remove(pp); 426784a3f4dbSSebastian Andrzej Siewior 4268d26aac2dSDan Carpenter cpuhp_state_remove_instance_nocalls(online_hpstate, 4269d26aac2dSDan Carpenter &pp->node_online); 427084a3f4dbSSebastian Andrzej Siewior cpuhp_state_remove_instance_nocalls(CPUHP_NET_MVNETA_DEAD, 427184a3f4dbSSebastian Andrzej Siewior &pp->node_dead); 4272129219e4SGregory CLEMENT on_each_cpu(mvneta_percpu_disable, pp, true); 427312bb03b4SMaxime Ripard free_percpu_irq(dev->irq, pp->ports); 42742636ac3cSMarcin Wojtas } else { 42752636ac3cSMarcin Wojtas mvneta_stop_dev(pp); 42762636ac3cSMarcin Wojtas mvneta_mdio_remove(pp); 42772636ac3cSMarcin Wojtas free_irq(dev->irq, pp); 42782636ac3cSMarcin Wojtas } 42792636ac3cSMarcin Wojtas 4280c5aff182SThomas Petazzoni mvneta_cleanup_rxqs(pp); 4281c5aff182SThomas Petazzoni mvneta_cleanup_txqs(pp); 4282c5aff182SThomas Petazzoni 4283c5aff182SThomas Petazzoni return 0; 4284c5aff182SThomas Petazzoni } 4285c5aff182SThomas Petazzoni 428615f59456SThomas Petazzoni static int mvneta_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) 428715f59456SThomas Petazzoni { 4288503f9aa9SRussell King struct mvneta_port *pp = netdev_priv(dev); 428915f59456SThomas Petazzoni 4290503f9aa9SRussell King return phylink_mii_ioctl(pp->phylink, ifr, cmd); 429115f59456SThomas Petazzoni } 429215f59456SThomas Petazzoni 42930db51da7SLorenzo Bianconi static int mvneta_xdp_setup(struct net_device *dev, struct bpf_prog *prog, 42940db51da7SLorenzo Bianconi struct netlink_ext_ack *extack) 42950db51da7SLorenzo Bianconi { 42960db51da7SLorenzo Bianconi bool need_update, running = netif_running(dev); 42970db51da7SLorenzo Bianconi struct mvneta_port *pp = netdev_priv(dev); 42980db51da7SLorenzo Bianconi struct bpf_prog *old_prog; 42990db51da7SLorenzo Bianconi 43000db51da7SLorenzo Bianconi if (prog && dev->mtu > MVNETA_MAX_RX_BUF_SIZE) { 43010db51da7SLorenzo Bianconi NL_SET_ERR_MSG_MOD(extack, "Jumbo frames not supported on XDP"); 43020db51da7SLorenzo Bianconi return -EOPNOTSUPP; 43030db51da7SLorenzo Bianconi } 43040db51da7SLorenzo Bianconi 430579572c98SSven Auhagen if (pp->bm_priv) { 430679572c98SSven Auhagen NL_SET_ERR_MSG_MOD(extack, 430779572c98SSven Auhagen "Hardware Buffer Management not supported on XDP"); 430879572c98SSven Auhagen return -EOPNOTSUPP; 430979572c98SSven Auhagen } 431079572c98SSven Auhagen 43110db51da7SLorenzo Bianconi need_update = !!pp->xdp_prog != !!prog; 43120db51da7SLorenzo Bianconi if (running && need_update) 43130db51da7SLorenzo Bianconi mvneta_stop(dev); 43140db51da7SLorenzo Bianconi 43150db51da7SLorenzo Bianconi old_prog = xchg(&pp->xdp_prog, prog); 43160db51da7SLorenzo Bianconi if (old_prog) 43170db51da7SLorenzo Bianconi bpf_prog_put(old_prog); 43180db51da7SLorenzo Bianconi 43190db51da7SLorenzo Bianconi if (running && need_update) 43200db51da7SLorenzo Bianconi return mvneta_open(dev); 43210db51da7SLorenzo Bianconi 43220db51da7SLorenzo Bianconi return 0; 43230db51da7SLorenzo Bianconi } 43240db51da7SLorenzo Bianconi 43250db51da7SLorenzo Bianconi static int mvneta_xdp(struct net_device *dev, struct netdev_bpf *xdp) 43260db51da7SLorenzo Bianconi { 43270db51da7SLorenzo Bianconi struct mvneta_port *pp = netdev_priv(dev); 43280db51da7SLorenzo Bianconi 43290db51da7SLorenzo Bianconi switch (xdp->command) { 43300db51da7SLorenzo Bianconi case XDP_SETUP_PROG: 43310db51da7SLorenzo Bianconi return mvneta_xdp_setup(dev, xdp->prog, xdp->extack); 43320db51da7SLorenzo Bianconi case XDP_QUERY_PROG: 43330db51da7SLorenzo Bianconi xdp->prog_id = pp->xdp_prog ? pp->xdp_prog->aux->id : 0; 43340db51da7SLorenzo Bianconi return 0; 43350db51da7SLorenzo Bianconi default: 43360db51da7SLorenzo Bianconi return -EINVAL; 43370db51da7SLorenzo Bianconi } 43380db51da7SLorenzo Bianconi } 43390db51da7SLorenzo Bianconi 4340c5aff182SThomas Petazzoni /* Ethtool methods */ 4341c5aff182SThomas Petazzoni 4342013ad40dSPhilippe Reynes /* Set link ksettings (phy address, speed) for ethtools */ 43432dc0d2b4SBaoyou Xie static int 43442dc0d2b4SBaoyou Xie mvneta_ethtool_set_link_ksettings(struct net_device *ndev, 4345013ad40dSPhilippe Reynes const struct ethtool_link_ksettings *cmd) 4346c5aff182SThomas Petazzoni { 4347013ad40dSPhilippe Reynes struct mvneta_port *pp = netdev_priv(ndev); 4348c5aff182SThomas Petazzoni 4349503f9aa9SRussell King return phylink_ethtool_ksettings_set(pp->phylink, cmd); 43500c0744fcSStas Sergeev } 43510c0744fcSStas Sergeev 4352503f9aa9SRussell King /* Get link ksettings for ethtools */ 4353503f9aa9SRussell King static int 4354503f9aa9SRussell King mvneta_ethtool_get_link_ksettings(struct net_device *ndev, 4355503f9aa9SRussell King struct ethtool_link_ksettings *cmd) 4356503f9aa9SRussell King { 4357503f9aa9SRussell King struct mvneta_port *pp = netdev_priv(ndev); 43580c0744fcSStas Sergeev 4359503f9aa9SRussell King return phylink_ethtool_ksettings_get(pp->phylink, cmd); 43600c0744fcSStas Sergeev } 43610c0744fcSStas Sergeev 4362503f9aa9SRussell King static int mvneta_ethtool_nway_reset(struct net_device *dev) 4363503f9aa9SRussell King { 4364503f9aa9SRussell King struct mvneta_port *pp = netdev_priv(dev); 4365503f9aa9SRussell King 4366503f9aa9SRussell King return phylink_ethtool_nway_reset(pp->phylink); 4367c5aff182SThomas Petazzoni } 4368c5aff182SThomas Petazzoni 4369c5aff182SThomas Petazzoni /* Set interrupt coalescing for ethtools */ 4370c5aff182SThomas Petazzoni static int mvneta_ethtool_set_coalesce(struct net_device *dev, 4371c5aff182SThomas Petazzoni struct ethtool_coalesce *c) 4372c5aff182SThomas Petazzoni { 4373c5aff182SThomas Petazzoni struct mvneta_port *pp = netdev_priv(dev); 4374c5aff182SThomas Petazzoni int queue; 4375c5aff182SThomas Petazzoni 4376c5aff182SThomas Petazzoni for (queue = 0; queue < rxq_number; queue++) { 4377c5aff182SThomas Petazzoni struct mvneta_rx_queue *rxq = &pp->rxqs[queue]; 4378c5aff182SThomas Petazzoni rxq->time_coal = c->rx_coalesce_usecs; 4379c5aff182SThomas Petazzoni rxq->pkts_coal = c->rx_max_coalesced_frames; 4380c5aff182SThomas Petazzoni mvneta_rx_pkts_coal_set(pp, rxq, rxq->pkts_coal); 4381c5aff182SThomas Petazzoni mvneta_rx_time_coal_set(pp, rxq, rxq->time_coal); 4382c5aff182SThomas Petazzoni } 4383c5aff182SThomas Petazzoni 4384c5aff182SThomas Petazzoni for (queue = 0; queue < txq_number; queue++) { 4385c5aff182SThomas Petazzoni struct mvneta_tx_queue *txq = &pp->txqs[queue]; 4386c5aff182SThomas Petazzoni txq->done_pkts_coal = c->tx_max_coalesced_frames; 4387c5aff182SThomas Petazzoni mvneta_tx_done_pkts_coal_set(pp, txq, txq->done_pkts_coal); 4388c5aff182SThomas Petazzoni } 4389c5aff182SThomas Petazzoni 4390c5aff182SThomas Petazzoni return 0; 4391c5aff182SThomas Petazzoni } 4392c5aff182SThomas Petazzoni 4393c5aff182SThomas Petazzoni /* get coalescing for ethtools */ 4394c5aff182SThomas Petazzoni static int mvneta_ethtool_get_coalesce(struct net_device *dev, 4395c5aff182SThomas Petazzoni struct ethtool_coalesce *c) 4396c5aff182SThomas Petazzoni { 4397c5aff182SThomas Petazzoni struct mvneta_port *pp = netdev_priv(dev); 4398c5aff182SThomas Petazzoni 4399c5aff182SThomas Petazzoni c->rx_coalesce_usecs = pp->rxqs[0].time_coal; 4400c5aff182SThomas Petazzoni c->rx_max_coalesced_frames = pp->rxqs[0].pkts_coal; 4401c5aff182SThomas Petazzoni 4402c5aff182SThomas Petazzoni c->tx_max_coalesced_frames = pp->txqs[0].done_pkts_coal; 4403c5aff182SThomas Petazzoni return 0; 4404c5aff182SThomas Petazzoni } 4405c5aff182SThomas Petazzoni 4406c5aff182SThomas Petazzoni 4407c5aff182SThomas Petazzoni static void mvneta_ethtool_get_drvinfo(struct net_device *dev, 4408c5aff182SThomas Petazzoni struct ethtool_drvinfo *drvinfo) 4409c5aff182SThomas Petazzoni { 4410c5aff182SThomas Petazzoni strlcpy(drvinfo->driver, MVNETA_DRIVER_NAME, 4411c5aff182SThomas Petazzoni sizeof(drvinfo->driver)); 4412c5aff182SThomas Petazzoni strlcpy(drvinfo->version, MVNETA_DRIVER_VERSION, 4413c5aff182SThomas Petazzoni sizeof(drvinfo->version)); 4414c5aff182SThomas Petazzoni strlcpy(drvinfo->bus_info, dev_name(&dev->dev), 4415c5aff182SThomas Petazzoni sizeof(drvinfo->bus_info)); 4416c5aff182SThomas Petazzoni } 4417c5aff182SThomas Petazzoni 4418c5aff182SThomas Petazzoni 4419c5aff182SThomas Petazzoni static void mvneta_ethtool_get_ringparam(struct net_device *netdev, 4420c5aff182SThomas Petazzoni struct ethtool_ringparam *ring) 4421c5aff182SThomas Petazzoni { 4422c5aff182SThomas Petazzoni struct mvneta_port *pp = netdev_priv(netdev); 4423c5aff182SThomas Petazzoni 4424c5aff182SThomas Petazzoni ring->rx_max_pending = MVNETA_MAX_RXD; 4425c5aff182SThomas Petazzoni ring->tx_max_pending = MVNETA_MAX_TXD; 4426c5aff182SThomas Petazzoni ring->rx_pending = pp->rx_ring_size; 4427c5aff182SThomas Petazzoni ring->tx_pending = pp->tx_ring_size; 4428c5aff182SThomas Petazzoni } 4429c5aff182SThomas Petazzoni 4430c5aff182SThomas Petazzoni static int mvneta_ethtool_set_ringparam(struct net_device *dev, 4431c5aff182SThomas Petazzoni struct ethtool_ringparam *ring) 4432c5aff182SThomas Petazzoni { 4433c5aff182SThomas Petazzoni struct mvneta_port *pp = netdev_priv(dev); 4434c5aff182SThomas Petazzoni 4435c5aff182SThomas Petazzoni if ((ring->rx_pending == 0) || (ring->tx_pending == 0)) 4436c5aff182SThomas Petazzoni return -EINVAL; 4437c5aff182SThomas Petazzoni pp->rx_ring_size = ring->rx_pending < MVNETA_MAX_RXD ? 4438c5aff182SThomas Petazzoni ring->rx_pending : MVNETA_MAX_RXD; 44398eef5f97SEzequiel Garcia 44408eef5f97SEzequiel Garcia pp->tx_ring_size = clamp_t(u16, ring->tx_pending, 44418eef5f97SEzequiel Garcia MVNETA_MAX_SKB_DESCS * 2, MVNETA_MAX_TXD); 44428eef5f97SEzequiel Garcia if (pp->tx_ring_size != ring->tx_pending) 44438eef5f97SEzequiel Garcia netdev_warn(dev, "TX queue size set to %u (requested %u)\n", 44448eef5f97SEzequiel Garcia pp->tx_ring_size, ring->tx_pending); 4445c5aff182SThomas Petazzoni 4446c5aff182SThomas Petazzoni if (netif_running(dev)) { 4447c5aff182SThomas Petazzoni mvneta_stop(dev); 4448c5aff182SThomas Petazzoni if (mvneta_open(dev)) { 4449c5aff182SThomas Petazzoni netdev_err(dev, 4450c5aff182SThomas Petazzoni "error on opening device after ring param change\n"); 4451c5aff182SThomas Petazzoni return -ENOMEM; 4452c5aff182SThomas Petazzoni } 4453c5aff182SThomas Petazzoni } 4454c5aff182SThomas Petazzoni 4455c5aff182SThomas Petazzoni return 0; 4456c5aff182SThomas Petazzoni } 4457c5aff182SThomas Petazzoni 44584932a918SRussell King static void mvneta_ethtool_get_pauseparam(struct net_device *dev, 44594932a918SRussell King struct ethtool_pauseparam *pause) 44604932a918SRussell King { 44614932a918SRussell King struct mvneta_port *pp = netdev_priv(dev); 44624932a918SRussell King 44634932a918SRussell King phylink_ethtool_get_pauseparam(pp->phylink, pause); 44644932a918SRussell King } 44654932a918SRussell King 44664932a918SRussell King static int mvneta_ethtool_set_pauseparam(struct net_device *dev, 44674932a918SRussell King struct ethtool_pauseparam *pause) 44684932a918SRussell King { 44694932a918SRussell King struct mvneta_port *pp = netdev_priv(dev); 44704932a918SRussell King 44714932a918SRussell King return phylink_ethtool_set_pauseparam(pp->phylink, pause); 44724932a918SRussell King } 44734932a918SRussell King 44749b0cdefaSRussell King static void mvneta_ethtool_get_strings(struct net_device *netdev, u32 sset, 44759b0cdefaSRussell King u8 *data) 44769b0cdefaSRussell King { 44779b0cdefaSRussell King if (sset == ETH_SS_STATS) { 44789b0cdefaSRussell King int i; 44799b0cdefaSRussell King 44809b0cdefaSRussell King for (i = 0; i < ARRAY_SIZE(mvneta_statistics); i++) 44819b0cdefaSRussell King memcpy(data + i * ETH_GSTRING_LEN, 44829b0cdefaSRussell King mvneta_statistics[i].name, ETH_GSTRING_LEN); 44839b0cdefaSRussell King } 44849b0cdefaSRussell King } 44859b0cdefaSRussell King 44869ac41f3cSLorenzo Bianconi static void 44879ac41f3cSLorenzo Bianconi mvneta_ethtool_update_pcpu_stats(struct mvneta_port *pp, 44889ac41f3cSLorenzo Bianconi struct mvneta_ethtool_stats *es) 44899ac41f3cSLorenzo Bianconi { 44909ac41f3cSLorenzo Bianconi unsigned int start; 44919ac41f3cSLorenzo Bianconi int cpu; 44929ac41f3cSLorenzo Bianconi 44939ac41f3cSLorenzo Bianconi for_each_possible_cpu(cpu) { 44949ac41f3cSLorenzo Bianconi struct mvneta_pcpu_stats *stats; 44959ac41f3cSLorenzo Bianconi u64 skb_alloc_error; 44969ac41f3cSLorenzo Bianconi u64 refill_error; 44973d866523SLorenzo Bianconi u64 xdp_redirect; 44983d866523SLorenzo Bianconi u64 xdp_pass; 44993d866523SLorenzo Bianconi u64 xdp_drop; 45007d51a015SLorenzo Bianconi u64 xdp_xmit; 45013d866523SLorenzo Bianconi u64 xdp_tx; 45029ac41f3cSLorenzo Bianconi 45039ac41f3cSLorenzo Bianconi stats = per_cpu_ptr(pp->stats, cpu); 45049ac41f3cSLorenzo Bianconi do { 45059ac41f3cSLorenzo Bianconi start = u64_stats_fetch_begin_irq(&stats->syncp); 45069ac41f3cSLorenzo Bianconi skb_alloc_error = stats->es.skb_alloc_error; 45079ac41f3cSLorenzo Bianconi refill_error = stats->es.refill_error; 45083d866523SLorenzo Bianconi xdp_redirect = stats->es.ps.xdp_redirect; 45093d866523SLorenzo Bianconi xdp_pass = stats->es.ps.xdp_pass; 45103d866523SLorenzo Bianconi xdp_drop = stats->es.ps.xdp_drop; 45117d51a015SLorenzo Bianconi xdp_xmit = stats->es.ps.xdp_xmit; 45123d866523SLorenzo Bianconi xdp_tx = stats->es.ps.xdp_tx; 45139ac41f3cSLorenzo Bianconi } while (u64_stats_fetch_retry_irq(&stats->syncp, start)); 45149ac41f3cSLorenzo Bianconi 45159ac41f3cSLorenzo Bianconi es->skb_alloc_error += skb_alloc_error; 45169ac41f3cSLorenzo Bianconi es->refill_error += refill_error; 45173d866523SLorenzo Bianconi es->ps.xdp_redirect += xdp_redirect; 45183d866523SLorenzo Bianconi es->ps.xdp_pass += xdp_pass; 45193d866523SLorenzo Bianconi es->ps.xdp_drop += xdp_drop; 45207d51a015SLorenzo Bianconi es->ps.xdp_xmit += xdp_xmit; 45213d866523SLorenzo Bianconi es->ps.xdp_tx += xdp_tx; 45229ac41f3cSLorenzo Bianconi } 45239ac41f3cSLorenzo Bianconi } 45249ac41f3cSLorenzo Bianconi 45259b0cdefaSRussell King static void mvneta_ethtool_update_stats(struct mvneta_port *pp) 45269b0cdefaSRussell King { 45279ac41f3cSLorenzo Bianconi struct mvneta_ethtool_stats stats = {}; 45289b0cdefaSRussell King const struct mvneta_statistic *s; 45299b0cdefaSRussell King void __iomem *base = pp->base; 45306d81f451SRussell King u32 high, low; 45316d81f451SRussell King u64 val; 45329b0cdefaSRussell King int i; 45339b0cdefaSRussell King 45349ac41f3cSLorenzo Bianconi mvneta_ethtool_update_pcpu_stats(pp, &stats); 45359b0cdefaSRussell King for (i = 0, s = mvneta_statistics; 45369b0cdefaSRussell King s < mvneta_statistics + ARRAY_SIZE(mvneta_statistics); 45379b0cdefaSRussell King s++, i++) { 45389b0cdefaSRussell King switch (s->type) { 45399b0cdefaSRussell King case T_REG_32: 45409b0cdefaSRussell King val = readl_relaxed(base + s->offset); 45419ac41f3cSLorenzo Bianconi pp->ethtool_stats[i] += val; 45429b0cdefaSRussell King break; 45439b0cdefaSRussell King case T_REG_64: 45449b0cdefaSRussell King /* Docs say to read low 32-bit then high */ 45459b0cdefaSRussell King low = readl_relaxed(base + s->offset); 45469b0cdefaSRussell King high = readl_relaxed(base + s->offset + 4); 45476d81f451SRussell King val = (u64)high << 32 | low; 45489ac41f3cSLorenzo Bianconi pp->ethtool_stats[i] += val; 45496d81f451SRussell King break; 45506d81f451SRussell King case T_SW: 45516d81f451SRussell King switch (s->offset) { 45526d81f451SRussell King case ETHTOOL_STAT_EEE_WAKEUP: 45536d81f451SRussell King val = phylink_get_eee_err(pp->phylink); 45549ac41f3cSLorenzo Bianconi pp->ethtool_stats[i] += val; 45559b0cdefaSRussell King break; 455617a96da6SGregory CLEMENT case ETHTOOL_STAT_SKB_ALLOC_ERR: 45579ac41f3cSLorenzo Bianconi pp->ethtool_stats[i] = stats.skb_alloc_error; 455817a96da6SGregory CLEMENT break; 455917a96da6SGregory CLEMENT case ETHTOOL_STAT_REFILL_ERR: 45609ac41f3cSLorenzo Bianconi pp->ethtool_stats[i] = stats.refill_error; 456117a96da6SGregory CLEMENT break; 45623d866523SLorenzo Bianconi case ETHTOOL_XDP_REDIRECT: 45633d866523SLorenzo Bianconi pp->ethtool_stats[i] = stats.ps.xdp_redirect; 45643d866523SLorenzo Bianconi break; 45653d866523SLorenzo Bianconi case ETHTOOL_XDP_PASS: 45663d866523SLorenzo Bianconi pp->ethtool_stats[i] = stats.ps.xdp_pass; 45673d866523SLorenzo Bianconi break; 45683d866523SLorenzo Bianconi case ETHTOOL_XDP_DROP: 45693d866523SLorenzo Bianconi pp->ethtool_stats[i] = stats.ps.xdp_drop; 45703d866523SLorenzo Bianconi break; 45713d866523SLorenzo Bianconi case ETHTOOL_XDP_TX: 45723d866523SLorenzo Bianconi pp->ethtool_stats[i] = stats.ps.xdp_tx; 45733d866523SLorenzo Bianconi break; 45747d51a015SLorenzo Bianconi case ETHTOOL_XDP_XMIT: 45757d51a015SLorenzo Bianconi pp->ethtool_stats[i] = stats.ps.xdp_xmit; 45767d51a015SLorenzo Bianconi break; 45779b0cdefaSRussell King } 45786d81f451SRussell King break; 45796d81f451SRussell King } 45809b0cdefaSRussell King } 45819b0cdefaSRussell King } 45829b0cdefaSRussell King 45839b0cdefaSRussell King static void mvneta_ethtool_get_stats(struct net_device *dev, 45849b0cdefaSRussell King struct ethtool_stats *stats, u64 *data) 45859b0cdefaSRussell King { 45869b0cdefaSRussell King struct mvneta_port *pp = netdev_priv(dev); 45879b0cdefaSRussell King int i; 45889b0cdefaSRussell King 45899b0cdefaSRussell King mvneta_ethtool_update_stats(pp); 45909b0cdefaSRussell King 45919b0cdefaSRussell King for (i = 0; i < ARRAY_SIZE(mvneta_statistics); i++) 45929b0cdefaSRussell King *data++ = pp->ethtool_stats[i]; 45939b0cdefaSRussell King } 45949b0cdefaSRussell King 45959b0cdefaSRussell King static int mvneta_ethtool_get_sset_count(struct net_device *dev, int sset) 45969b0cdefaSRussell King { 45979b0cdefaSRussell King if (sset == ETH_SS_STATS) 45989b0cdefaSRussell King return ARRAY_SIZE(mvneta_statistics); 45999b0cdefaSRussell King return -EOPNOTSUPP; 46009b0cdefaSRussell King } 46019b0cdefaSRussell King 46029a401deaSGregory CLEMENT static u32 mvneta_ethtool_get_rxfh_indir_size(struct net_device *dev) 46039a401deaSGregory CLEMENT { 46049a401deaSGregory CLEMENT return MVNETA_RSS_LU_TABLE_SIZE; 46059a401deaSGregory CLEMENT } 46069a401deaSGregory CLEMENT 46079a401deaSGregory CLEMENT static int mvneta_ethtool_get_rxnfc(struct net_device *dev, 46089a401deaSGregory CLEMENT struct ethtool_rxnfc *info, 46099a401deaSGregory CLEMENT u32 *rules __always_unused) 46109a401deaSGregory CLEMENT { 46119a401deaSGregory CLEMENT switch (info->cmd) { 46129a401deaSGregory CLEMENT case ETHTOOL_GRXRINGS: 46139a401deaSGregory CLEMENT info->data = rxq_number; 46149a401deaSGregory CLEMENT return 0; 46159a401deaSGregory CLEMENT case ETHTOOL_GRXFH: 46169a401deaSGregory CLEMENT return -EOPNOTSUPP; 46179a401deaSGregory CLEMENT default: 46189a401deaSGregory CLEMENT return -EOPNOTSUPP; 46199a401deaSGregory CLEMENT } 46209a401deaSGregory CLEMENT } 46219a401deaSGregory CLEMENT 46229a401deaSGregory CLEMENT static int mvneta_config_rss(struct mvneta_port *pp) 46239a401deaSGregory CLEMENT { 46249a401deaSGregory CLEMENT int cpu; 46259a401deaSGregory CLEMENT u32 val; 46269a401deaSGregory CLEMENT 46279a401deaSGregory CLEMENT netif_tx_stop_all_queues(pp->dev); 46289a401deaSGregory CLEMENT 46296b125d63SGregory CLEMENT on_each_cpu(mvneta_percpu_mask_interrupt, pp, true); 46309a401deaSGregory CLEMENT 46310f5c6c30SJisheng Zhang if (!pp->neta_armada3700) { 46329a401deaSGregory CLEMENT /* We have to synchronise on the napi of each CPU */ 46339a401deaSGregory CLEMENT for_each_online_cpu(cpu) { 46349a401deaSGregory CLEMENT struct mvneta_pcpu_port *pcpu_port = 46359a401deaSGregory CLEMENT per_cpu_ptr(pp->ports, cpu); 46369a401deaSGregory CLEMENT 46379a401deaSGregory CLEMENT napi_synchronize(&pcpu_port->napi); 46389a401deaSGregory CLEMENT napi_disable(&pcpu_port->napi); 46399a401deaSGregory CLEMENT } 46400f5c6c30SJisheng Zhang } else { 46410f5c6c30SJisheng Zhang napi_synchronize(&pp->napi); 46420f5c6c30SJisheng Zhang napi_disable(&pp->napi); 46430f5c6c30SJisheng Zhang } 46449a401deaSGregory CLEMENT 46459a401deaSGregory CLEMENT pp->rxq_def = pp->indir[0]; 46469a401deaSGregory CLEMENT 46479a401deaSGregory CLEMENT /* Update unicast mapping */ 46489a401deaSGregory CLEMENT mvneta_set_rx_mode(pp->dev); 46499a401deaSGregory CLEMENT 46509a401deaSGregory CLEMENT /* Update val of portCfg register accordingly with all RxQueue types */ 46519a401deaSGregory CLEMENT val = MVNETA_PORT_CONFIG_DEFL_VALUE(pp->rxq_def); 46529a401deaSGregory CLEMENT mvreg_write(pp, MVNETA_PORT_CONFIG, val); 46539a401deaSGregory CLEMENT 46549a401deaSGregory CLEMENT /* Update the elected CPU matching the new rxq_def */ 4655120cfa50SGregory CLEMENT spin_lock(&pp->lock); 46569a401deaSGregory CLEMENT mvneta_percpu_elect(pp); 4657120cfa50SGregory CLEMENT spin_unlock(&pp->lock); 46589a401deaSGregory CLEMENT 46590f5c6c30SJisheng Zhang if (!pp->neta_armada3700) { 46609a401deaSGregory CLEMENT /* We have to synchronise on the napi of each CPU */ 46619a401deaSGregory CLEMENT for_each_online_cpu(cpu) { 46629a401deaSGregory CLEMENT struct mvneta_pcpu_port *pcpu_port = 46639a401deaSGregory CLEMENT per_cpu_ptr(pp->ports, cpu); 46649a401deaSGregory CLEMENT 46659a401deaSGregory CLEMENT napi_enable(&pcpu_port->napi); 46669a401deaSGregory CLEMENT } 46670f5c6c30SJisheng Zhang } else { 46680f5c6c30SJisheng Zhang napi_enable(&pp->napi); 46690f5c6c30SJisheng Zhang } 46709a401deaSGregory CLEMENT 46719a401deaSGregory CLEMENT netif_tx_start_all_queues(pp->dev); 46729a401deaSGregory CLEMENT 46739a401deaSGregory CLEMENT return 0; 46749a401deaSGregory CLEMENT } 46759a401deaSGregory CLEMENT 46769a401deaSGregory CLEMENT static int mvneta_ethtool_set_rxfh(struct net_device *dev, const u32 *indir, 46779a401deaSGregory CLEMENT const u8 *key, const u8 hfunc) 46789a401deaSGregory CLEMENT { 46799a401deaSGregory CLEMENT struct mvneta_port *pp = netdev_priv(dev); 46802636ac3cSMarcin Wojtas 46812636ac3cSMarcin Wojtas /* Current code for Armada 3700 doesn't support RSS features yet */ 46822636ac3cSMarcin Wojtas if (pp->neta_armada3700) 46832636ac3cSMarcin Wojtas return -EOPNOTSUPP; 46842636ac3cSMarcin Wojtas 46859a401deaSGregory CLEMENT /* We require at least one supported parameter to be changed 46869a401deaSGregory CLEMENT * and no change in any of the unsupported parameters 46879a401deaSGregory CLEMENT */ 46889a401deaSGregory CLEMENT if (key || 46899a401deaSGregory CLEMENT (hfunc != ETH_RSS_HASH_NO_CHANGE && hfunc != ETH_RSS_HASH_TOP)) 46909a401deaSGregory CLEMENT return -EOPNOTSUPP; 46919a401deaSGregory CLEMENT 46929a401deaSGregory CLEMENT if (!indir) 46939a401deaSGregory CLEMENT return 0; 46949a401deaSGregory CLEMENT 46959a401deaSGregory CLEMENT memcpy(pp->indir, indir, MVNETA_RSS_LU_TABLE_SIZE); 46969a401deaSGregory CLEMENT 46979a401deaSGregory CLEMENT return mvneta_config_rss(pp); 46989a401deaSGregory CLEMENT } 46999a401deaSGregory CLEMENT 47009a401deaSGregory CLEMENT static int mvneta_ethtool_get_rxfh(struct net_device *dev, u32 *indir, u8 *key, 47019a401deaSGregory CLEMENT u8 *hfunc) 47029a401deaSGregory CLEMENT { 47039a401deaSGregory CLEMENT struct mvneta_port *pp = netdev_priv(dev); 47049a401deaSGregory CLEMENT 47052636ac3cSMarcin Wojtas /* Current code for Armada 3700 doesn't support RSS features yet */ 47062636ac3cSMarcin Wojtas if (pp->neta_armada3700) 47072636ac3cSMarcin Wojtas return -EOPNOTSUPP; 47082636ac3cSMarcin Wojtas 47099a401deaSGregory CLEMENT if (hfunc) 47109a401deaSGregory CLEMENT *hfunc = ETH_RSS_HASH_TOP; 47119a401deaSGregory CLEMENT 47129a401deaSGregory CLEMENT if (!indir) 47139a401deaSGregory CLEMENT return 0; 47149a401deaSGregory CLEMENT 47159a401deaSGregory CLEMENT memcpy(indir, pp->indir, MVNETA_RSS_LU_TABLE_SIZE); 47169a401deaSGregory CLEMENT 47179a401deaSGregory CLEMENT return 0; 47189a401deaSGregory CLEMENT } 47199a401deaSGregory CLEMENT 4720b60a00f9SJingju Hou static void mvneta_ethtool_get_wol(struct net_device *dev, 4721b60a00f9SJingju Hou struct ethtool_wolinfo *wol) 4722b60a00f9SJingju Hou { 4723503f9aa9SRussell King struct mvneta_port *pp = netdev_priv(dev); 4724b60a00f9SJingju Hou 4725503f9aa9SRussell King phylink_ethtool_get_wol(pp->phylink, wol); 4726b60a00f9SJingju Hou } 4727b60a00f9SJingju Hou 4728b60a00f9SJingju Hou static int mvneta_ethtool_set_wol(struct net_device *dev, 4729b60a00f9SJingju Hou struct ethtool_wolinfo *wol) 4730b60a00f9SJingju Hou { 4731503f9aa9SRussell King struct mvneta_port *pp = netdev_priv(dev); 473282960fffSJisheng Zhang int ret; 473382960fffSJisheng Zhang 4734503f9aa9SRussell King ret = phylink_ethtool_set_wol(pp->phylink, wol); 473582960fffSJisheng Zhang if (!ret) 473682960fffSJisheng Zhang device_set_wakeup_enable(&dev->dev, !!wol->wolopts); 473782960fffSJisheng Zhang 473882960fffSJisheng Zhang return ret; 4739b60a00f9SJingju Hou } 4740b60a00f9SJingju Hou 47416d81f451SRussell King static int mvneta_ethtool_get_eee(struct net_device *dev, 47426d81f451SRussell King struct ethtool_eee *eee) 47436d81f451SRussell King { 47446d81f451SRussell King struct mvneta_port *pp = netdev_priv(dev); 47456d81f451SRussell King u32 lpi_ctl0; 47466d81f451SRussell King 47476d81f451SRussell King lpi_ctl0 = mvreg_read(pp, MVNETA_LPI_CTRL_0); 47486d81f451SRussell King 47496d81f451SRussell King eee->eee_enabled = pp->eee_enabled; 47506d81f451SRussell King eee->eee_active = pp->eee_active; 47516d81f451SRussell King eee->tx_lpi_enabled = pp->tx_lpi_enabled; 47526d81f451SRussell King eee->tx_lpi_timer = (lpi_ctl0) >> 8; // * scale; 47536d81f451SRussell King 47546d81f451SRussell King return phylink_ethtool_get_eee(pp->phylink, eee); 47556d81f451SRussell King } 47566d81f451SRussell King 47576d81f451SRussell King static int mvneta_ethtool_set_eee(struct net_device *dev, 47586d81f451SRussell King struct ethtool_eee *eee) 47596d81f451SRussell King { 47606d81f451SRussell King struct mvneta_port *pp = netdev_priv(dev); 47616d81f451SRussell King u32 lpi_ctl0; 47626d81f451SRussell King 47636d81f451SRussell King /* The Armada 37x documents do not give limits for this other than 47646d81f451SRussell King * it being an 8-bit register. */ 4765e4a3e9ffSYueHaibing if (eee->tx_lpi_enabled && eee->tx_lpi_timer > 255) 47666d81f451SRussell King return -EINVAL; 47676d81f451SRussell King 47686d81f451SRussell King lpi_ctl0 = mvreg_read(pp, MVNETA_LPI_CTRL_0); 47696d81f451SRussell King lpi_ctl0 &= ~(0xff << 8); 47706d81f451SRussell King lpi_ctl0 |= eee->tx_lpi_timer << 8; 47716d81f451SRussell King mvreg_write(pp, MVNETA_LPI_CTRL_0, lpi_ctl0); 47726d81f451SRussell King 47736d81f451SRussell King pp->eee_enabled = eee->eee_enabled; 47746d81f451SRussell King pp->tx_lpi_enabled = eee->tx_lpi_enabled; 47756d81f451SRussell King 47766d81f451SRussell King mvneta_set_eee(pp, eee->tx_lpi_enabled && eee->eee_enabled); 47776d81f451SRussell King 47786d81f451SRussell King return phylink_ethtool_set_eee(pp->phylink, eee); 47796d81f451SRussell King } 47806d81f451SRussell King 4781c5aff182SThomas Petazzoni static const struct net_device_ops mvneta_netdev_ops = { 4782c5aff182SThomas Petazzoni .ndo_open = mvneta_open, 4783c5aff182SThomas Petazzoni .ndo_stop = mvneta_stop, 4784c5aff182SThomas Petazzoni .ndo_start_xmit = mvneta_tx, 4785c5aff182SThomas Petazzoni .ndo_set_rx_mode = mvneta_set_rx_mode, 4786c5aff182SThomas Petazzoni .ndo_set_mac_address = mvneta_set_mac_addr, 4787c5aff182SThomas Petazzoni .ndo_change_mtu = mvneta_change_mtu, 4788b65657fcSSimon Guinot .ndo_fix_features = mvneta_fix_features, 4789c5aff182SThomas Petazzoni .ndo_get_stats64 = mvneta_get_stats64, 479015f59456SThomas Petazzoni .ndo_do_ioctl = mvneta_ioctl, 47910db51da7SLorenzo Bianconi .ndo_bpf = mvneta_xdp, 4792b0a43db9SLorenzo Bianconi .ndo_xdp_xmit = mvneta_xdp_xmit, 4793c5aff182SThomas Petazzoni }; 4794c5aff182SThomas Petazzoni 47954581be42SJisheng Zhang static const struct ethtool_ops mvneta_eth_tool_ops = { 4796503f9aa9SRussell King .nway_reset = mvneta_ethtool_nway_reset, 4797c5aff182SThomas Petazzoni .get_link = ethtool_op_get_link, 4798c5aff182SThomas Petazzoni .set_coalesce = mvneta_ethtool_set_coalesce, 4799c5aff182SThomas Petazzoni .get_coalesce = mvneta_ethtool_get_coalesce, 4800c5aff182SThomas Petazzoni .get_drvinfo = mvneta_ethtool_get_drvinfo, 4801c5aff182SThomas Petazzoni .get_ringparam = mvneta_ethtool_get_ringparam, 4802c5aff182SThomas Petazzoni .set_ringparam = mvneta_ethtool_set_ringparam, 48034932a918SRussell King .get_pauseparam = mvneta_ethtool_get_pauseparam, 48044932a918SRussell King .set_pauseparam = mvneta_ethtool_set_pauseparam, 48059b0cdefaSRussell King .get_strings = mvneta_ethtool_get_strings, 48069b0cdefaSRussell King .get_ethtool_stats = mvneta_ethtool_get_stats, 48079b0cdefaSRussell King .get_sset_count = mvneta_ethtool_get_sset_count, 48089a401deaSGregory CLEMENT .get_rxfh_indir_size = mvneta_ethtool_get_rxfh_indir_size, 48099a401deaSGregory CLEMENT .get_rxnfc = mvneta_ethtool_get_rxnfc, 48109a401deaSGregory CLEMENT .get_rxfh = mvneta_ethtool_get_rxfh, 48119a401deaSGregory CLEMENT .set_rxfh = mvneta_ethtool_set_rxfh, 4812503f9aa9SRussell King .get_link_ksettings = mvneta_ethtool_get_link_ksettings, 4813013ad40dSPhilippe Reynes .set_link_ksettings = mvneta_ethtool_set_link_ksettings, 4814b60a00f9SJingju Hou .get_wol = mvneta_ethtool_get_wol, 4815b60a00f9SJingju Hou .set_wol = mvneta_ethtool_set_wol, 48166d81f451SRussell King .get_eee = mvneta_ethtool_get_eee, 48176d81f451SRussell King .set_eee = mvneta_ethtool_set_eee, 4818c5aff182SThomas Petazzoni }; 4819c5aff182SThomas Petazzoni 4820c5aff182SThomas Petazzoni /* Initialize hw */ 48219672850bSEzequiel Garcia static int mvneta_init(struct device *dev, struct mvneta_port *pp) 4822c5aff182SThomas Petazzoni { 4823c5aff182SThomas Petazzoni int queue; 4824c5aff182SThomas Petazzoni 4825c5aff182SThomas Petazzoni /* Disable port */ 4826c5aff182SThomas Petazzoni mvneta_port_disable(pp); 4827c5aff182SThomas Petazzoni 4828c5aff182SThomas Petazzoni /* Set port default values */ 4829c5aff182SThomas Petazzoni mvneta_defaults_set(pp); 4830c5aff182SThomas Petazzoni 48315d6312edSMarkus Elfring pp->txqs = devm_kcalloc(dev, txq_number, sizeof(*pp->txqs), GFP_KERNEL); 4832c5aff182SThomas Petazzoni if (!pp->txqs) 4833c5aff182SThomas Petazzoni return -ENOMEM; 4834c5aff182SThomas Petazzoni 4835c5aff182SThomas Petazzoni /* Initialize TX descriptor rings */ 4836c5aff182SThomas Petazzoni for (queue = 0; queue < txq_number; queue++) { 4837c5aff182SThomas Petazzoni struct mvneta_tx_queue *txq = &pp->txqs[queue]; 4838c5aff182SThomas Petazzoni txq->id = queue; 4839c5aff182SThomas Petazzoni txq->size = pp->tx_ring_size; 4840c5aff182SThomas Petazzoni txq->done_pkts_coal = MVNETA_TXDONE_COAL_PKTS; 4841c5aff182SThomas Petazzoni } 4842c5aff182SThomas Petazzoni 48435d6312edSMarkus Elfring pp->rxqs = devm_kcalloc(dev, rxq_number, sizeof(*pp->rxqs), GFP_KERNEL); 48449672850bSEzequiel Garcia if (!pp->rxqs) 4845c5aff182SThomas Petazzoni return -ENOMEM; 4846c5aff182SThomas Petazzoni 4847c5aff182SThomas Petazzoni /* Create Rx descriptor rings */ 4848c5aff182SThomas Petazzoni for (queue = 0; queue < rxq_number; queue++) { 4849c5aff182SThomas Petazzoni struct mvneta_rx_queue *rxq = &pp->rxqs[queue]; 4850c5aff182SThomas Petazzoni rxq->id = queue; 4851c5aff182SThomas Petazzoni rxq->size = pp->rx_ring_size; 4852c5aff182SThomas Petazzoni rxq->pkts_coal = MVNETA_RX_COAL_PKTS; 4853c5aff182SThomas Petazzoni rxq->time_coal = MVNETA_RX_COAL_USEC; 485429110630SMarkus Elfring rxq->buf_virt_addr 485529110630SMarkus Elfring = devm_kmalloc_array(pp->dev->dev.parent, 485629110630SMarkus Elfring rxq->size, 485729110630SMarkus Elfring sizeof(*rxq->buf_virt_addr), 4858f88bee1cSGregory CLEMENT GFP_KERNEL); 4859f88bee1cSGregory CLEMENT if (!rxq->buf_virt_addr) 4860f88bee1cSGregory CLEMENT return -ENOMEM; 4861c5aff182SThomas Petazzoni } 4862c5aff182SThomas Petazzoni 4863c5aff182SThomas Petazzoni return 0; 4864c5aff182SThomas Petazzoni } 4865c5aff182SThomas Petazzoni 4866c5aff182SThomas Petazzoni /* platform glue : initialize decoding windows */ 486703ce758eSGreg KH static void mvneta_conf_mbus_windows(struct mvneta_port *pp, 4868c5aff182SThomas Petazzoni const struct mbus_dram_target_info *dram) 4869c5aff182SThomas Petazzoni { 4870c5aff182SThomas Petazzoni u32 win_enable; 4871c5aff182SThomas Petazzoni u32 win_protect; 4872c5aff182SThomas Petazzoni int i; 4873c5aff182SThomas Petazzoni 4874c5aff182SThomas Petazzoni for (i = 0; i < 6; i++) { 4875c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_WIN_BASE(i), 0); 4876c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_WIN_SIZE(i), 0); 4877c5aff182SThomas Petazzoni 4878c5aff182SThomas Petazzoni if (i < 4) 4879c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_WIN_REMAP(i), 0); 4880c5aff182SThomas Petazzoni } 4881c5aff182SThomas Petazzoni 4882c5aff182SThomas Petazzoni win_enable = 0x3f; 4883c5aff182SThomas Petazzoni win_protect = 0; 4884c5aff182SThomas Petazzoni 48852636ac3cSMarcin Wojtas if (dram) { 4886c5aff182SThomas Petazzoni for (i = 0; i < dram->num_cs; i++) { 4887c5aff182SThomas Petazzoni const struct mbus_dram_window *cs = dram->cs + i; 48882636ac3cSMarcin Wojtas 48892636ac3cSMarcin Wojtas mvreg_write(pp, MVNETA_WIN_BASE(i), 48902636ac3cSMarcin Wojtas (cs->base & 0xffff0000) | 48912636ac3cSMarcin Wojtas (cs->mbus_attr << 8) | 48922636ac3cSMarcin Wojtas dram->mbus_dram_target_id); 4893c5aff182SThomas Petazzoni 4894c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_WIN_SIZE(i), 4895c5aff182SThomas Petazzoni (cs->size - 1) & 0xffff0000); 4896c5aff182SThomas Petazzoni 4897c5aff182SThomas Petazzoni win_enable &= ~(1 << i); 4898c5aff182SThomas Petazzoni win_protect |= 3 << (2 * i); 4899c5aff182SThomas Petazzoni } 49002636ac3cSMarcin Wojtas } else { 49012636ac3cSMarcin Wojtas /* For Armada3700 open default 4GB Mbus window, leaving 49022636ac3cSMarcin Wojtas * arbitration of target/attribute to a different layer 49032636ac3cSMarcin Wojtas * of configuration. 49042636ac3cSMarcin Wojtas */ 49052636ac3cSMarcin Wojtas mvreg_write(pp, MVNETA_WIN_SIZE(0), 0xffff0000); 49062636ac3cSMarcin Wojtas win_enable &= ~BIT(0); 49072636ac3cSMarcin Wojtas win_protect = 3; 49082636ac3cSMarcin Wojtas } 4909c5aff182SThomas Petazzoni 4910c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_BASE_ADDR_ENABLE, win_enable); 4911db6ba9a5SMarcin Wojtas mvreg_write(pp, MVNETA_ACCESS_PROTECT_ENABLE, win_protect); 4912c5aff182SThomas Petazzoni } 4913c5aff182SThomas Petazzoni 4914c5aff182SThomas Petazzoni /* Power up the port */ 49153f1dd4bcSThomas Petazzoni static int mvneta_port_power_up(struct mvneta_port *pp, int phy_mode) 4916c5aff182SThomas Petazzoni { 4917c5aff182SThomas Petazzoni /* MAC Cause register should be cleared */ 4918c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_UNIT_INTR_CAUSE, 0); 4919c5aff182SThomas Petazzoni 492032699954SRussell King if (phy_mode == PHY_INTERFACE_MODE_QSGMII) 49213f1dd4bcSThomas Petazzoni mvreg_write(pp, MVNETA_SERDES_CFG, MVNETA_QSGMII_SERDES_PROTO); 492222f4bf8aSRussell King else if (phy_mode == PHY_INTERFACE_MODE_SGMII || 4923a10c1c81SRussell King phy_interface_mode_is_8023z(phy_mode)) 49243f1dd4bcSThomas Petazzoni mvreg_write(pp, MVNETA_SERDES_CFG, MVNETA_SGMII_SERDES_PROTO); 492532699954SRussell King else if (!phy_interface_mode_is_rgmii(phy_mode)) 49263f1dd4bcSThomas Petazzoni return -EINVAL; 49273f1dd4bcSThomas Petazzoni 49283f1dd4bcSThomas Petazzoni return 0; 4929c5aff182SThomas Petazzoni } 4930c5aff182SThomas Petazzoni 4931c5aff182SThomas Petazzoni /* Device initialization routine */ 493203ce758eSGreg KH static int mvneta_probe(struct platform_device *pdev) 4933c5aff182SThomas Petazzoni { 4934c5aff182SThomas Petazzoni struct device_node *dn = pdev->dev.of_node; 4935dc35a10fSMarcin Wojtas struct device_node *bm_node; 4936c5aff182SThomas Petazzoni struct mvneta_port *pp; 4937c5aff182SThomas Petazzoni struct net_device *dev; 4938503f9aa9SRussell King struct phylink *phylink; 4939a10c1c81SRussell King struct phy *comphy; 49408cc3e439SThomas Petazzoni const char *dt_mac_addr; 49418cc3e439SThomas Petazzoni char hw_mac_addr[ETH_ALEN]; 49420c65b2b9SAndrew Lunn phy_interface_t phy_mode; 49438cc3e439SThomas Petazzoni const char *mac_from; 49449110ee07SMarcin Wojtas int tx_csum_limit; 4945c5aff182SThomas Petazzoni int err; 494612bb03b4SMaxime Ripard int cpu; 4947c5aff182SThomas Petazzoni 4948a3ddd94fSRosen Penev dev = devm_alloc_etherdev_mqs(&pdev->dev, sizeof(struct mvneta_port), 4949a3ddd94fSRosen Penev txq_number, rxq_number); 4950c5aff182SThomas Petazzoni if (!dev) 4951c5aff182SThomas Petazzoni return -ENOMEM; 4952c5aff182SThomas Petazzoni 4953c5aff182SThomas Petazzoni dev->irq = irq_of_parse_and_map(dn, 0); 4954a3ddd94fSRosen Penev if (dev->irq == 0) 4955a3ddd94fSRosen Penev return -EINVAL; 4956c5aff182SThomas Petazzoni 49570c65b2b9SAndrew Lunn err = of_get_phy_mode(dn, &phy_mode); 49580c65b2b9SAndrew Lunn if (err) { 4959c5aff182SThomas Petazzoni dev_err(&pdev->dev, "incorrect phy-mode\n"); 4960503f9aa9SRussell King goto err_free_irq; 4961503f9aa9SRussell King } 4962503f9aa9SRussell King 4963a10c1c81SRussell King comphy = devm_of_phy_get(&pdev->dev, dn, NULL); 4964a10c1c81SRussell King if (comphy == ERR_PTR(-EPROBE_DEFER)) { 4965a10c1c81SRussell King err = -EPROBE_DEFER; 4966a10c1c81SRussell King goto err_free_irq; 4967a10c1c81SRussell King } else if (IS_ERR(comphy)) { 4968a10c1c81SRussell King comphy = NULL; 4969a10c1c81SRussell King } 4970a10c1c81SRussell King 497144cc27e4SIoana Ciornei pp = netdev_priv(dev); 497244cc27e4SIoana Ciornei spin_lock_init(&pp->lock); 497344cc27e4SIoana Ciornei 497444cc27e4SIoana Ciornei pp->phylink_config.dev = &dev->dev; 497544cc27e4SIoana Ciornei pp->phylink_config.type = PHYLINK_NETDEV; 497644cc27e4SIoana Ciornei 497744cc27e4SIoana Ciornei phylink = phylink_create(&pp->phylink_config, pdev->dev.fwnode, 497844cc27e4SIoana Ciornei phy_mode, &mvneta_phylink_ops); 4979503f9aa9SRussell King if (IS_ERR(phylink)) { 4980503f9aa9SRussell King err = PTR_ERR(phylink); 4981503f9aa9SRussell King goto err_free_irq; 4982c5aff182SThomas Petazzoni } 4983c5aff182SThomas Petazzoni 4984c5aff182SThomas Petazzoni dev->tx_queue_len = MVNETA_MAX_TXD; 4985c5aff182SThomas Petazzoni dev->watchdog_timeo = 5 * HZ; 4986c5aff182SThomas Petazzoni dev->netdev_ops = &mvneta_netdev_ops; 4987c5aff182SThomas Petazzoni 49887ad24ea4SWilfried Klaebe dev->ethtool_ops = &mvneta_eth_tool_ops; 4989c5aff182SThomas Petazzoni 4990503f9aa9SRussell King pp->phylink = phylink; 4991a10c1c81SRussell King pp->comphy = comphy; 4992c5aff182SThomas Petazzoni pp->phy_interface = phy_mode; 4993503f9aa9SRussell King pp->dn = dn; 4994c5aff182SThomas Petazzoni 499590b74c01SGregory CLEMENT pp->rxq_def = rxq_def; 49969a401deaSGregory CLEMENT pp->indir[0] = rxq_def; 49979a401deaSGregory CLEMENT 49982636ac3cSMarcin Wojtas /* Get special SoC configurations */ 49992636ac3cSMarcin Wojtas if (of_device_is_compatible(dn, "marvell,armada-3700-neta")) 50002636ac3cSMarcin Wojtas pp->neta_armada3700 = true; 50012636ac3cSMarcin Wojtas 50022804ba4eSJisheng Zhang pp->clk = devm_clk_get(&pdev->dev, "core"); 50032804ba4eSJisheng Zhang if (IS_ERR(pp->clk)) 5004189dd626SThomas Petazzoni pp->clk = devm_clk_get(&pdev->dev, NULL); 5005189dd626SThomas Petazzoni if (IS_ERR(pp->clk)) { 5006189dd626SThomas Petazzoni err = PTR_ERR(pp->clk); 5007503f9aa9SRussell King goto err_free_phylink; 5008189dd626SThomas Petazzoni } 5009189dd626SThomas Petazzoni 5010189dd626SThomas Petazzoni clk_prepare_enable(pp->clk); 5011189dd626SThomas Petazzoni 501215cc4a4aSJisheng Zhang pp->clk_bus = devm_clk_get(&pdev->dev, "bus"); 501315cc4a4aSJisheng Zhang if (!IS_ERR(pp->clk_bus)) 501415cc4a4aSJisheng Zhang clk_prepare_enable(pp->clk_bus); 501515cc4a4aSJisheng Zhang 501600c33afbSJisheng Zhang pp->base = devm_platform_ioremap_resource(pdev, 0); 5017c3f0dd38SThomas Petazzoni if (IS_ERR(pp->base)) { 5018c3f0dd38SThomas Petazzoni err = PTR_ERR(pp->base); 50195445eaf3SArnaud Patard \(Rtp\) goto err_clk; 50205445eaf3SArnaud Patard \(Rtp\) } 50215445eaf3SArnaud Patard \(Rtp\) 502212bb03b4SMaxime Ripard /* Alloc per-cpu port structure */ 502312bb03b4SMaxime Ripard pp->ports = alloc_percpu(struct mvneta_pcpu_port); 502412bb03b4SMaxime Ripard if (!pp->ports) { 502512bb03b4SMaxime Ripard err = -ENOMEM; 502612bb03b4SMaxime Ripard goto err_clk; 502712bb03b4SMaxime Ripard } 502812bb03b4SMaxime Ripard 502974c41b04Swilly tarreau /* Alloc per-cpu stats */ 50301c213bd2SWANG Cong pp->stats = netdev_alloc_pcpu_stats(struct mvneta_pcpu_stats); 503174c41b04Swilly tarreau if (!pp->stats) { 503274c41b04Swilly tarreau err = -ENOMEM; 503312bb03b4SMaxime Ripard goto err_free_ports; 503474c41b04Swilly tarreau } 503574c41b04Swilly tarreau 50368cc3e439SThomas Petazzoni dt_mac_addr = of_get_mac_address(dn); 5037a51645f7SPetr Štetiar if (!IS_ERR(dt_mac_addr)) { 50388cc3e439SThomas Petazzoni mac_from = "device tree"; 50392d2924afSPetr Štetiar ether_addr_copy(dev->dev_addr, dt_mac_addr); 50408cc3e439SThomas Petazzoni } else { 50418cc3e439SThomas Petazzoni mvneta_get_mac_addr(pp, hw_mac_addr); 50428cc3e439SThomas Petazzoni if (is_valid_ether_addr(hw_mac_addr)) { 50438cc3e439SThomas Petazzoni mac_from = "hardware"; 50448cc3e439SThomas Petazzoni memcpy(dev->dev_addr, hw_mac_addr, ETH_ALEN); 50458cc3e439SThomas Petazzoni } else { 50468cc3e439SThomas Petazzoni mac_from = "random"; 50478cc3e439SThomas Petazzoni eth_hw_addr_random(dev); 50488cc3e439SThomas Petazzoni } 50498cc3e439SThomas Petazzoni } 50508cc3e439SThomas Petazzoni 50519110ee07SMarcin Wojtas if (!of_property_read_u32(dn, "tx-csum-limit", &tx_csum_limit)) { 50529110ee07SMarcin Wojtas if (tx_csum_limit < 0 || 50539110ee07SMarcin Wojtas tx_csum_limit > MVNETA_TX_CSUM_MAX_SIZE) { 50549110ee07SMarcin Wojtas tx_csum_limit = MVNETA_TX_CSUM_DEF_SIZE; 50559110ee07SMarcin Wojtas dev_info(&pdev->dev, 50569110ee07SMarcin Wojtas "Wrong TX csum limit in DT, set to %dB\n", 50579110ee07SMarcin Wojtas MVNETA_TX_CSUM_DEF_SIZE); 50589110ee07SMarcin Wojtas } 50599110ee07SMarcin Wojtas } else if (of_device_is_compatible(dn, "marvell,armada-370-neta")) { 50609110ee07SMarcin Wojtas tx_csum_limit = MVNETA_TX_CSUM_DEF_SIZE; 50619110ee07SMarcin Wojtas } else { 50629110ee07SMarcin Wojtas tx_csum_limit = MVNETA_TX_CSUM_MAX_SIZE; 50639110ee07SMarcin Wojtas } 50649110ee07SMarcin Wojtas 50659110ee07SMarcin Wojtas pp->tx_csum_limit = tx_csum_limit; 5066b65657fcSSimon Guinot 50679768b45cSJane Li pp->dram_target_info = mv_mbus_dram_info(); 50682636ac3cSMarcin Wojtas /* Armada3700 requires setting default configuration of Mbus 50692636ac3cSMarcin Wojtas * windows, however without using filled mbus_dram_target_info 50702636ac3cSMarcin Wojtas * structure. 50712636ac3cSMarcin Wojtas */ 50729768b45cSJane Li if (pp->dram_target_info || pp->neta_armada3700) 50739768b45cSJane Li mvneta_conf_mbus_windows(pp, pp->dram_target_info); 5074dc35a10fSMarcin Wojtas 5075c5aff182SThomas Petazzoni pp->tx_ring_size = MVNETA_MAX_TXD; 5076c5aff182SThomas Petazzoni pp->rx_ring_size = MVNETA_MAX_RXD; 5077c5aff182SThomas Petazzoni 5078c5aff182SThomas Petazzoni pp->dev = dev; 5079c5aff182SThomas Petazzoni SET_NETDEV_DEV(dev, &pdev->dev); 5080c5aff182SThomas Petazzoni 5081dc35a10fSMarcin Wojtas pp->id = global_port_id++; 5082dc35a10fSMarcin Wojtas 5083dc35a10fSMarcin Wojtas /* Obtain access to BM resources if enabled and already initialized */ 5084dc35a10fSMarcin Wojtas bm_node = of_parse_phandle(dn, "buffer-manager", 0); 5085965cbbecSGregory CLEMENT if (bm_node) { 5086965cbbecSGregory CLEMENT pp->bm_priv = mvneta_bm_get(bm_node); 5087965cbbecSGregory CLEMENT if (pp->bm_priv) { 5088dc35a10fSMarcin Wojtas err = mvneta_bm_port_init(pdev, pp); 5089dc35a10fSMarcin Wojtas if (err < 0) { 5090965cbbecSGregory CLEMENT dev_info(&pdev->dev, 5091965cbbecSGregory CLEMENT "use SW buffer management\n"); 5092965cbbecSGregory CLEMENT mvneta_bm_put(pp->bm_priv); 5093dc35a10fSMarcin Wojtas pp->bm_priv = NULL; 5094dc35a10fSMarcin Wojtas } 5095dc35a10fSMarcin Wojtas } 5096562e2f46SYelena Krivosheev /* Set RX packet offset correction for platforms, whose 5097562e2f46SYelena Krivosheev * NET_SKB_PAD, exceeds 64B. It should be 64B for 64-bit 5098562e2f46SYelena Krivosheev * platforms and 0B for 32-bit ones. 5099562e2f46SYelena Krivosheev */ 5100562e2f46SYelena Krivosheev pp->rx_offset_correction = max(0, 5101562e2f46SYelena Krivosheev NET_SKB_PAD - 5102562e2f46SYelena Krivosheev MVNETA_RX_PKT_OFFSET_CORRECTION); 5103965cbbecSGregory CLEMENT } 5104d4e4da00SPeter Chen of_node_put(bm_node); 5105dc35a10fSMarcin Wojtas 510644efc78dSLorenzo Bianconi /* sw buffer management */ 510744efc78dSLorenzo Bianconi if (!pp->bm_priv) 510844efc78dSLorenzo Bianconi pp->rx_offset_correction = MVNETA_SKB_HEADROOM; 510944efc78dSLorenzo Bianconi 51109672850bSEzequiel Garcia err = mvneta_init(&pdev->dev, pp); 51119672850bSEzequiel Garcia if (err < 0) 5112dc35a10fSMarcin Wojtas goto err_netdev; 51133f1dd4bcSThomas Petazzoni 51143f1dd4bcSThomas Petazzoni err = mvneta_port_power_up(pp, phy_mode); 51153f1dd4bcSThomas Petazzoni if (err < 0) { 51163f1dd4bcSThomas Petazzoni dev_err(&pdev->dev, "can't power up port\n"); 5117dc35a10fSMarcin Wojtas goto err_netdev; 51183f1dd4bcSThomas Petazzoni } 5119c5aff182SThomas Petazzoni 51202636ac3cSMarcin Wojtas /* Armada3700 network controller does not support per-cpu 51212636ac3cSMarcin Wojtas * operation, so only single NAPI should be initialized. 51222636ac3cSMarcin Wojtas */ 51232636ac3cSMarcin Wojtas if (pp->neta_armada3700) { 51242636ac3cSMarcin Wojtas netif_napi_add(dev, &pp->napi, mvneta_poll, NAPI_POLL_WEIGHT); 51252636ac3cSMarcin Wojtas } else { 512612bb03b4SMaxime Ripard for_each_present_cpu(cpu) { 51272636ac3cSMarcin Wojtas struct mvneta_pcpu_port *port = 51282636ac3cSMarcin Wojtas per_cpu_ptr(pp->ports, cpu); 512912bb03b4SMaxime Ripard 51302636ac3cSMarcin Wojtas netif_napi_add(dev, &port->napi, mvneta_poll, 51312636ac3cSMarcin Wojtas NAPI_POLL_WEIGHT); 513212bb03b4SMaxime Ripard port->pp = pp; 513312bb03b4SMaxime Ripard } 51342636ac3cSMarcin Wojtas } 5135c5aff182SThomas Petazzoni 51367772988aSJisheng Zhang dev->features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | 51377772988aSJisheng Zhang NETIF_F_TSO | NETIF_F_RXCSUM; 513801ef26caSEzequiel Garcia dev->hw_features |= dev->features; 513901ef26caSEzequiel Garcia dev->vlan_features |= dev->features; 514097db8afaSAndrew Lunn dev->priv_flags |= IFF_LIVE_ADDR_CHANGE; 51418eef5f97SEzequiel Garcia dev->gso_max_segs = MVNETA_MAX_TSO_SEGS; 5142b50b72deSwilly tarreau 51435777987eSJarod Wilson /* MTU range: 68 - 9676 */ 51445777987eSJarod Wilson dev->min_mtu = ETH_MIN_MTU; 51455777987eSJarod Wilson /* 9676 == 9700 - 20 and rounding to 8 */ 51465777987eSJarod Wilson dev->max_mtu = 9676; 51475777987eSJarod Wilson 5148c5aff182SThomas Petazzoni err = register_netdev(dev); 5149c5aff182SThomas Petazzoni if (err < 0) { 5150c5aff182SThomas Petazzoni dev_err(&pdev->dev, "failed to register\n"); 5151d484e06eSJisheng Zhang goto err_netdev; 5152c5aff182SThomas Petazzoni } 5153c5aff182SThomas Petazzoni 51548cc3e439SThomas Petazzoni netdev_info(dev, "Using %s mac address %pM\n", mac_from, 51558cc3e439SThomas Petazzoni dev->dev_addr); 5156c5aff182SThomas Petazzoni 5157c5aff182SThomas Petazzoni platform_set_drvdata(pdev, pp->dev); 5158c5aff182SThomas Petazzoni 5159c5aff182SThomas Petazzoni return 0; 5160c5aff182SThomas Petazzoni 5161dc35a10fSMarcin Wojtas err_netdev: 5162dc35a10fSMarcin Wojtas if (pp->bm_priv) { 5163dc35a10fSMarcin Wojtas mvneta_bm_pool_destroy(pp->bm_priv, pp->pool_long, 1 << pp->id); 5164dc35a10fSMarcin Wojtas mvneta_bm_pool_destroy(pp->bm_priv, pp->pool_short, 5165dc35a10fSMarcin Wojtas 1 << pp->id); 5166965cbbecSGregory CLEMENT mvneta_bm_put(pp->bm_priv); 5167dc35a10fSMarcin Wojtas } 516874c41b04Swilly tarreau free_percpu(pp->stats); 516912bb03b4SMaxime Ripard err_free_ports: 517012bb03b4SMaxime Ripard free_percpu(pp->ports); 51715445eaf3SArnaud Patard \(Rtp\) err_clk: 517215cc4a4aSJisheng Zhang clk_disable_unprepare(pp->clk_bus); 51735445eaf3SArnaud Patard \(Rtp\) clk_disable_unprepare(pp->clk); 5174503f9aa9SRussell King err_free_phylink: 5175503f9aa9SRussell King if (pp->phylink) 5176503f9aa9SRussell King phylink_destroy(pp->phylink); 5177c5aff182SThomas Petazzoni err_free_irq: 5178c5aff182SThomas Petazzoni irq_dispose_mapping(dev->irq); 5179c5aff182SThomas Petazzoni return err; 5180c5aff182SThomas Petazzoni } 5181c5aff182SThomas Petazzoni 5182c5aff182SThomas Petazzoni /* Device removal routine */ 518303ce758eSGreg KH static int mvneta_remove(struct platform_device *pdev) 5184c5aff182SThomas Petazzoni { 5185c5aff182SThomas Petazzoni struct net_device *dev = platform_get_drvdata(pdev); 5186c5aff182SThomas Petazzoni struct mvneta_port *pp = netdev_priv(dev); 5187c5aff182SThomas Petazzoni 5188c5aff182SThomas Petazzoni unregister_netdev(dev); 518915cc4a4aSJisheng Zhang clk_disable_unprepare(pp->clk_bus); 5190189dd626SThomas Petazzoni clk_disable_unprepare(pp->clk); 519112bb03b4SMaxime Ripard free_percpu(pp->ports); 519274c41b04Swilly tarreau free_percpu(pp->stats); 5193c5aff182SThomas Petazzoni irq_dispose_mapping(dev->irq); 5194503f9aa9SRussell King phylink_destroy(pp->phylink); 5195c5aff182SThomas Petazzoni 5196dc35a10fSMarcin Wojtas if (pp->bm_priv) { 5197dc35a10fSMarcin Wojtas mvneta_bm_pool_destroy(pp->bm_priv, pp->pool_long, 1 << pp->id); 5198dc35a10fSMarcin Wojtas mvneta_bm_pool_destroy(pp->bm_priv, pp->pool_short, 5199dc35a10fSMarcin Wojtas 1 << pp->id); 5200965cbbecSGregory CLEMENT mvneta_bm_put(pp->bm_priv); 5201dc35a10fSMarcin Wojtas } 5202dc35a10fSMarcin Wojtas 5203c5aff182SThomas Petazzoni return 0; 5204c5aff182SThomas Petazzoni } 5205c5aff182SThomas Petazzoni 52069768b45cSJane Li #ifdef CONFIG_PM_SLEEP 52079768b45cSJane Li static int mvneta_suspend(struct device *device) 52089768b45cSJane Li { 52091799cdd2SJisheng Zhang int queue; 52109768b45cSJane Li struct net_device *dev = dev_get_drvdata(device); 52119768b45cSJane Li struct mvneta_port *pp = netdev_priv(dev); 52129768b45cSJane Li 52131799cdd2SJisheng Zhang if (!netif_running(dev)) 52141799cdd2SJisheng Zhang goto clean_exit; 52151799cdd2SJisheng Zhang 52161799cdd2SJisheng Zhang if (!pp->neta_armada3700) { 52171799cdd2SJisheng Zhang spin_lock(&pp->lock); 52181799cdd2SJisheng Zhang pp->is_stopped = true; 52191799cdd2SJisheng Zhang spin_unlock(&pp->lock); 52201799cdd2SJisheng Zhang 52211799cdd2SJisheng Zhang cpuhp_state_remove_instance_nocalls(online_hpstate, 52221799cdd2SJisheng Zhang &pp->node_online); 52231799cdd2SJisheng Zhang cpuhp_state_remove_instance_nocalls(CPUHP_NET_MVNETA_DEAD, 52241799cdd2SJisheng Zhang &pp->node_dead); 52251799cdd2SJisheng Zhang } 52261799cdd2SJisheng Zhang 52273b8bc674SRussell King rtnl_lock(); 52281799cdd2SJisheng Zhang mvneta_stop_dev(pp); 52293b8bc674SRussell King rtnl_unlock(); 52301799cdd2SJisheng Zhang 52311799cdd2SJisheng Zhang for (queue = 0; queue < rxq_number; queue++) { 52321799cdd2SJisheng Zhang struct mvneta_rx_queue *rxq = &pp->rxqs[queue]; 52331799cdd2SJisheng Zhang 52341799cdd2SJisheng Zhang mvneta_rxq_drop_pkts(pp, rxq); 52351799cdd2SJisheng Zhang } 52361799cdd2SJisheng Zhang 52371799cdd2SJisheng Zhang for (queue = 0; queue < txq_number; queue++) { 52381799cdd2SJisheng Zhang struct mvneta_tx_queue *txq = &pp->txqs[queue]; 52391799cdd2SJisheng Zhang 52401799cdd2SJisheng Zhang mvneta_txq_hw_deinit(pp, txq); 52411799cdd2SJisheng Zhang } 52421799cdd2SJisheng Zhang 52431799cdd2SJisheng Zhang clean_exit: 52449768b45cSJane Li netif_device_detach(dev); 52459768b45cSJane Li clk_disable_unprepare(pp->clk_bus); 52469768b45cSJane Li clk_disable_unprepare(pp->clk); 52471799cdd2SJisheng Zhang 52489768b45cSJane Li return 0; 52499768b45cSJane Li } 52509768b45cSJane Li 52519768b45cSJane Li static int mvneta_resume(struct device *device) 52529768b45cSJane Li { 52539768b45cSJane Li struct platform_device *pdev = to_platform_device(device); 52549768b45cSJane Li struct net_device *dev = dev_get_drvdata(device); 52559768b45cSJane Li struct mvneta_port *pp = netdev_priv(dev); 52561799cdd2SJisheng Zhang int err, queue; 52579768b45cSJane Li 52589768b45cSJane Li clk_prepare_enable(pp->clk); 52599768b45cSJane Li if (!IS_ERR(pp->clk_bus)) 52609768b45cSJane Li clk_prepare_enable(pp->clk_bus); 52619768b45cSJane Li if (pp->dram_target_info || pp->neta_armada3700) 52629768b45cSJane Li mvneta_conf_mbus_windows(pp, pp->dram_target_info); 52639768b45cSJane Li if (pp->bm_priv) { 52649768b45cSJane Li err = mvneta_bm_port_init(pdev, pp); 52659768b45cSJane Li if (err < 0) { 52669768b45cSJane Li dev_info(&pdev->dev, "use SW buffer management\n"); 526744efc78dSLorenzo Bianconi pp->rx_offset_correction = MVNETA_SKB_HEADROOM; 52689768b45cSJane Li pp->bm_priv = NULL; 52699768b45cSJane Li } 52709768b45cSJane Li } 52719768b45cSJane Li mvneta_defaults_set(pp); 52729768b45cSJane Li err = mvneta_port_power_up(pp, pp->phy_interface); 52739768b45cSJane Li if (err < 0) { 52749768b45cSJane Li dev_err(device, "can't power up port\n"); 52759768b45cSJane Li return err; 52769768b45cSJane Li } 52779768b45cSJane Li 52789768b45cSJane Li netif_device_attach(dev); 52791799cdd2SJisheng Zhang 52801799cdd2SJisheng Zhang if (!netif_running(dev)) 52811799cdd2SJisheng Zhang return 0; 52821799cdd2SJisheng Zhang 52831799cdd2SJisheng Zhang for (queue = 0; queue < rxq_number; queue++) { 52841799cdd2SJisheng Zhang struct mvneta_rx_queue *rxq = &pp->rxqs[queue]; 52851799cdd2SJisheng Zhang 52861799cdd2SJisheng Zhang rxq->next_desc_to_proc = 0; 52871799cdd2SJisheng Zhang mvneta_rxq_hw_init(pp, rxq); 5288d6956ac8SJisheng Zhang } 52891799cdd2SJisheng Zhang 52901799cdd2SJisheng Zhang for (queue = 0; queue < txq_number; queue++) { 52911799cdd2SJisheng Zhang struct mvneta_tx_queue *txq = &pp->txqs[queue]; 52921799cdd2SJisheng Zhang 52931799cdd2SJisheng Zhang txq->next_desc_to_proc = 0; 52941799cdd2SJisheng Zhang mvneta_txq_hw_init(pp, txq); 52951799cdd2SJisheng Zhang } 52961799cdd2SJisheng Zhang 52971799cdd2SJisheng Zhang if (!pp->neta_armada3700) { 52981799cdd2SJisheng Zhang spin_lock(&pp->lock); 52991799cdd2SJisheng Zhang pp->is_stopped = false; 53001799cdd2SJisheng Zhang spin_unlock(&pp->lock); 53011799cdd2SJisheng Zhang cpuhp_state_add_instance_nocalls(online_hpstate, 53021799cdd2SJisheng Zhang &pp->node_online); 53031799cdd2SJisheng Zhang cpuhp_state_add_instance_nocalls(CPUHP_NET_MVNETA_DEAD, 53041799cdd2SJisheng Zhang &pp->node_dead); 53051799cdd2SJisheng Zhang } 53061799cdd2SJisheng Zhang 53071799cdd2SJisheng Zhang rtnl_lock(); 53081799cdd2SJisheng Zhang mvneta_start_dev(pp); 53093b8bc674SRussell King rtnl_unlock(); 53101799cdd2SJisheng Zhang mvneta_set_rx_mode(dev); 5311d6956ac8SJisheng Zhang 53129768b45cSJane Li return 0; 53139768b45cSJane Li } 53149768b45cSJane Li #endif 53159768b45cSJane Li 53169768b45cSJane Li static SIMPLE_DEV_PM_OPS(mvneta_pm_ops, mvneta_suspend, mvneta_resume); 53179768b45cSJane Li 5318c5aff182SThomas Petazzoni static const struct of_device_id mvneta_match[] = { 5319c5aff182SThomas Petazzoni { .compatible = "marvell,armada-370-neta" }, 5320f522a975SSimon Guinot { .compatible = "marvell,armada-xp-neta" }, 53212636ac3cSMarcin Wojtas { .compatible = "marvell,armada-3700-neta" }, 5322c5aff182SThomas Petazzoni { } 5323c5aff182SThomas Petazzoni }; 5324c5aff182SThomas Petazzoni MODULE_DEVICE_TABLE(of, mvneta_match); 5325c5aff182SThomas Petazzoni 5326c5aff182SThomas Petazzoni static struct platform_driver mvneta_driver = { 5327c5aff182SThomas Petazzoni .probe = mvneta_probe, 532803ce758eSGreg KH .remove = mvneta_remove, 5329c5aff182SThomas Petazzoni .driver = { 5330c5aff182SThomas Petazzoni .name = MVNETA_DRIVER_NAME, 5331c5aff182SThomas Petazzoni .of_match_table = mvneta_match, 53329768b45cSJane Li .pm = &mvneta_pm_ops, 5333c5aff182SThomas Petazzoni }, 5334c5aff182SThomas Petazzoni }; 5335c5aff182SThomas Petazzoni 533684a3f4dbSSebastian Andrzej Siewior static int __init mvneta_driver_init(void) 533784a3f4dbSSebastian Andrzej Siewior { 533884a3f4dbSSebastian Andrzej Siewior int ret; 533984a3f4dbSSebastian Andrzej Siewior 534084a3f4dbSSebastian Andrzej Siewior ret = cpuhp_setup_state_multi(CPUHP_AP_ONLINE_DYN, "net/mvmeta:online", 534184a3f4dbSSebastian Andrzej Siewior mvneta_cpu_online, 534284a3f4dbSSebastian Andrzej Siewior mvneta_cpu_down_prepare); 534384a3f4dbSSebastian Andrzej Siewior if (ret < 0) 534484a3f4dbSSebastian Andrzej Siewior goto out; 534584a3f4dbSSebastian Andrzej Siewior online_hpstate = ret; 534684a3f4dbSSebastian Andrzej Siewior ret = cpuhp_setup_state_multi(CPUHP_NET_MVNETA_DEAD, "net/mvneta:dead", 534784a3f4dbSSebastian Andrzej Siewior NULL, mvneta_cpu_dead); 534884a3f4dbSSebastian Andrzej Siewior if (ret) 534984a3f4dbSSebastian Andrzej Siewior goto err_dead; 535084a3f4dbSSebastian Andrzej Siewior 535184a3f4dbSSebastian Andrzej Siewior ret = platform_driver_register(&mvneta_driver); 535284a3f4dbSSebastian Andrzej Siewior if (ret) 535384a3f4dbSSebastian Andrzej Siewior goto err; 535484a3f4dbSSebastian Andrzej Siewior return 0; 535584a3f4dbSSebastian Andrzej Siewior 535684a3f4dbSSebastian Andrzej Siewior err: 535784a3f4dbSSebastian Andrzej Siewior cpuhp_remove_multi_state(CPUHP_NET_MVNETA_DEAD); 535884a3f4dbSSebastian Andrzej Siewior err_dead: 535984a3f4dbSSebastian Andrzej Siewior cpuhp_remove_multi_state(online_hpstate); 536084a3f4dbSSebastian Andrzej Siewior out: 536184a3f4dbSSebastian Andrzej Siewior return ret; 536284a3f4dbSSebastian Andrzej Siewior } 536384a3f4dbSSebastian Andrzej Siewior module_init(mvneta_driver_init); 536484a3f4dbSSebastian Andrzej Siewior 536584a3f4dbSSebastian Andrzej Siewior static void __exit mvneta_driver_exit(void) 536684a3f4dbSSebastian Andrzej Siewior { 536784a3f4dbSSebastian Andrzej Siewior platform_driver_unregister(&mvneta_driver); 536884a3f4dbSSebastian Andrzej Siewior cpuhp_remove_multi_state(CPUHP_NET_MVNETA_DEAD); 536984a3f4dbSSebastian Andrzej Siewior cpuhp_remove_multi_state(online_hpstate); 537084a3f4dbSSebastian Andrzej Siewior } 537184a3f4dbSSebastian Andrzej Siewior module_exit(mvneta_driver_exit); 5372c5aff182SThomas Petazzoni 5373c5aff182SThomas Petazzoni MODULE_DESCRIPTION("Marvell NETA Ethernet Driver - www.marvell.com"); 5374c5aff182SThomas Petazzoni MODULE_AUTHOR("Rami Rosen <rosenr@marvell.com>, Thomas Petazzoni <thomas.petazzoni@free-electrons.com>"); 5375c5aff182SThomas Petazzoni MODULE_LICENSE("GPL"); 5376c5aff182SThomas Petazzoni 5377d3757ba4SJoe Perches module_param(rxq_number, int, 0444); 5378d3757ba4SJoe Perches module_param(txq_number, int, 0444); 5379c5aff182SThomas Petazzoni 5380d3757ba4SJoe Perches module_param(rxq_def, int, 0444); 5381d3757ba4SJoe Perches module_param(rx_copybreak, int, 0644); 5382