1c5aff182SThomas Petazzoni /* 2c5aff182SThomas Petazzoni * Driver for Marvell NETA network card for Armada XP and Armada 370 SoCs. 3c5aff182SThomas Petazzoni * 4c5aff182SThomas Petazzoni * Copyright (C) 2012 Marvell 5c5aff182SThomas Petazzoni * 6c5aff182SThomas Petazzoni * Rami Rosen <rosenr@marvell.com> 7c5aff182SThomas Petazzoni * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> 8c5aff182SThomas Petazzoni * 9c5aff182SThomas Petazzoni * This file is licensed under the terms of the GNU General Public 10c5aff182SThomas Petazzoni * License version 2. This program is licensed "as is" without any 11c5aff182SThomas Petazzoni * warranty of any kind, whether express or implied. 12c5aff182SThomas Petazzoni */ 13c5aff182SThomas Petazzoni 14c5aff182SThomas Petazzoni #include <linux/kernel.h> 15c5aff182SThomas Petazzoni #include <linux/netdevice.h> 16c5aff182SThomas Petazzoni #include <linux/etherdevice.h> 17c5aff182SThomas Petazzoni #include <linux/platform_device.h> 18c5aff182SThomas Petazzoni #include <linux/skbuff.h> 19c5aff182SThomas Petazzoni #include <linux/inetdevice.h> 20c5aff182SThomas Petazzoni #include <linux/mbus.h> 21c5aff182SThomas Petazzoni #include <linux/module.h> 22c5aff182SThomas Petazzoni #include <linux/interrupt.h> 23c5aff182SThomas Petazzoni #include <net/ip.h> 24c5aff182SThomas Petazzoni #include <net/ipv6.h> 25c3f0dd38SThomas Petazzoni #include <linux/io.h> 262adb719dSEzequiel Garcia #include <net/tso.h> 27c5aff182SThomas Petazzoni #include <linux/of.h> 28c5aff182SThomas Petazzoni #include <linux/of_irq.h> 29c5aff182SThomas Petazzoni #include <linux/of_mdio.h> 30c5aff182SThomas Petazzoni #include <linux/of_net.h> 31c5aff182SThomas Petazzoni #include <linux/of_address.h> 32c5aff182SThomas Petazzoni #include <linux/phy.h> 33189dd626SThomas Petazzoni #include <linux/clk.h> 34c5aff182SThomas Petazzoni 35c5aff182SThomas Petazzoni /* Registers */ 36c5aff182SThomas Petazzoni #define MVNETA_RXQ_CONFIG_REG(q) (0x1400 + ((q) << 2)) 37c5aff182SThomas Petazzoni #define MVNETA_RXQ_HW_BUF_ALLOC BIT(1) 38c5aff182SThomas Petazzoni #define MVNETA_RXQ_PKT_OFFSET_ALL_MASK (0xf << 8) 39c5aff182SThomas Petazzoni #define MVNETA_RXQ_PKT_OFFSET_MASK(offs) ((offs) << 8) 40c5aff182SThomas Petazzoni #define MVNETA_RXQ_THRESHOLD_REG(q) (0x14c0 + ((q) << 2)) 41c5aff182SThomas Petazzoni #define MVNETA_RXQ_NON_OCCUPIED(v) ((v) << 16) 42c5aff182SThomas Petazzoni #define MVNETA_RXQ_BASE_ADDR_REG(q) (0x1480 + ((q) << 2)) 43c5aff182SThomas Petazzoni #define MVNETA_RXQ_SIZE_REG(q) (0x14a0 + ((q) << 2)) 44c5aff182SThomas Petazzoni #define MVNETA_RXQ_BUF_SIZE_SHIFT 19 45c5aff182SThomas Petazzoni #define MVNETA_RXQ_BUF_SIZE_MASK (0x1fff << 19) 46c5aff182SThomas Petazzoni #define MVNETA_RXQ_STATUS_REG(q) (0x14e0 + ((q) << 2)) 47c5aff182SThomas Petazzoni #define MVNETA_RXQ_OCCUPIED_ALL_MASK 0x3fff 48c5aff182SThomas Petazzoni #define MVNETA_RXQ_STATUS_UPDATE_REG(q) (0x1500 + ((q) << 2)) 49c5aff182SThomas Petazzoni #define MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT 16 50c5aff182SThomas Petazzoni #define MVNETA_RXQ_ADD_NON_OCCUPIED_MAX 255 51c5aff182SThomas Petazzoni #define MVNETA_PORT_RX_RESET 0x1cc0 52c5aff182SThomas Petazzoni #define MVNETA_PORT_RX_DMA_RESET BIT(0) 53c5aff182SThomas Petazzoni #define MVNETA_PHY_ADDR 0x2000 54c5aff182SThomas Petazzoni #define MVNETA_PHY_ADDR_MASK 0x1f 55c5aff182SThomas Petazzoni #define MVNETA_MBUS_RETRY 0x2010 56c5aff182SThomas Petazzoni #define MVNETA_UNIT_INTR_CAUSE 0x2080 57c5aff182SThomas Petazzoni #define MVNETA_UNIT_CONTROL 0x20B0 58c5aff182SThomas Petazzoni #define MVNETA_PHY_POLLING_ENABLE BIT(1) 59c5aff182SThomas Petazzoni #define MVNETA_WIN_BASE(w) (0x2200 + ((w) << 3)) 60c5aff182SThomas Petazzoni #define MVNETA_WIN_SIZE(w) (0x2204 + ((w) << 3)) 61c5aff182SThomas Petazzoni #define MVNETA_WIN_REMAP(w) (0x2280 + ((w) << 2)) 62c5aff182SThomas Petazzoni #define MVNETA_BASE_ADDR_ENABLE 0x2290 63c5aff182SThomas Petazzoni #define MVNETA_PORT_CONFIG 0x2400 64c5aff182SThomas Petazzoni #define MVNETA_UNI_PROMISC_MODE BIT(0) 65c5aff182SThomas Petazzoni #define MVNETA_DEF_RXQ(q) ((q) << 1) 66c5aff182SThomas Petazzoni #define MVNETA_DEF_RXQ_ARP(q) ((q) << 4) 67c5aff182SThomas Petazzoni #define MVNETA_TX_UNSET_ERR_SUM BIT(12) 68c5aff182SThomas Petazzoni #define MVNETA_DEF_RXQ_TCP(q) ((q) << 16) 69c5aff182SThomas Petazzoni #define MVNETA_DEF_RXQ_UDP(q) ((q) << 19) 70c5aff182SThomas Petazzoni #define MVNETA_DEF_RXQ_BPDU(q) ((q) << 22) 71c5aff182SThomas Petazzoni #define MVNETA_RX_CSUM_WITH_PSEUDO_HDR BIT(25) 72c5aff182SThomas Petazzoni #define MVNETA_PORT_CONFIG_DEFL_VALUE(q) (MVNETA_DEF_RXQ(q) | \ 73c5aff182SThomas Petazzoni MVNETA_DEF_RXQ_ARP(q) | \ 74c5aff182SThomas Petazzoni MVNETA_DEF_RXQ_TCP(q) | \ 75c5aff182SThomas Petazzoni MVNETA_DEF_RXQ_UDP(q) | \ 76c5aff182SThomas Petazzoni MVNETA_DEF_RXQ_BPDU(q) | \ 77c5aff182SThomas Petazzoni MVNETA_TX_UNSET_ERR_SUM | \ 78c5aff182SThomas Petazzoni MVNETA_RX_CSUM_WITH_PSEUDO_HDR) 79c5aff182SThomas Petazzoni #define MVNETA_PORT_CONFIG_EXTEND 0x2404 80c5aff182SThomas Petazzoni #define MVNETA_MAC_ADDR_LOW 0x2414 81c5aff182SThomas Petazzoni #define MVNETA_MAC_ADDR_HIGH 0x2418 82c5aff182SThomas Petazzoni #define MVNETA_SDMA_CONFIG 0x241c 83c5aff182SThomas Petazzoni #define MVNETA_SDMA_BRST_SIZE_16 4 84c5aff182SThomas Petazzoni #define MVNETA_RX_BRST_SZ_MASK(burst) ((burst) << 1) 85c5aff182SThomas Petazzoni #define MVNETA_RX_NO_DATA_SWAP BIT(4) 86c5aff182SThomas Petazzoni #define MVNETA_TX_NO_DATA_SWAP BIT(5) 879ad8fef6SThomas Petazzoni #define MVNETA_DESC_SWAP BIT(6) 88c5aff182SThomas Petazzoni #define MVNETA_TX_BRST_SZ_MASK(burst) ((burst) << 22) 89c5aff182SThomas Petazzoni #define MVNETA_PORT_STATUS 0x2444 90c5aff182SThomas Petazzoni #define MVNETA_TX_IN_PRGRS BIT(1) 91c5aff182SThomas Petazzoni #define MVNETA_TX_FIFO_EMPTY BIT(8) 92c5aff182SThomas Petazzoni #define MVNETA_RX_MIN_FRAME_SIZE 0x247c 933f1dd4bcSThomas Petazzoni #define MVNETA_SERDES_CFG 0x24A0 945445eaf3SArnaud Patard \(Rtp\) #define MVNETA_SGMII_SERDES_PROTO 0x0cc7 953f1dd4bcSThomas Petazzoni #define MVNETA_QSGMII_SERDES_PROTO 0x0667 96c5aff182SThomas Petazzoni #define MVNETA_TYPE_PRIO 0x24bc 97c5aff182SThomas Petazzoni #define MVNETA_FORCE_UNI BIT(21) 98c5aff182SThomas Petazzoni #define MVNETA_TXQ_CMD_1 0x24e4 99c5aff182SThomas Petazzoni #define MVNETA_TXQ_CMD 0x2448 100c5aff182SThomas Petazzoni #define MVNETA_TXQ_DISABLE_SHIFT 8 101c5aff182SThomas Petazzoni #define MVNETA_TXQ_ENABLE_MASK 0x000000ff 102c5aff182SThomas Petazzoni #define MVNETA_ACC_MODE 0x2500 103c5aff182SThomas Petazzoni #define MVNETA_CPU_MAP(cpu) (0x2540 + ((cpu) << 2)) 104c5aff182SThomas Petazzoni #define MVNETA_CPU_RXQ_ACCESS_ALL_MASK 0x000000ff 105c5aff182SThomas Petazzoni #define MVNETA_CPU_TXQ_ACCESS_ALL_MASK 0x0000ff00 106c5aff182SThomas Petazzoni #define MVNETA_RXQ_TIME_COAL_REG(q) (0x2580 + ((q) << 2)) 10740ba35e7Swilly tarreau 10840ba35e7Swilly tarreau /* Exception Interrupt Port/Queue Cause register */ 10940ba35e7Swilly tarreau 110c5aff182SThomas Petazzoni #define MVNETA_INTR_NEW_CAUSE 0x25a0 111c5aff182SThomas Petazzoni #define MVNETA_INTR_NEW_MASK 0x25a4 11240ba35e7Swilly tarreau 11340ba35e7Swilly tarreau /* bits 0..7 = TXQ SENT, one bit per queue. 11440ba35e7Swilly tarreau * bits 8..15 = RXQ OCCUP, one bit per queue. 11540ba35e7Swilly tarreau * bits 16..23 = RXQ FREE, one bit per queue. 11640ba35e7Swilly tarreau * bit 29 = OLD_REG_SUM, see old reg ? 11740ba35e7Swilly tarreau * bit 30 = TX_ERR_SUM, one bit for 4 ports 11840ba35e7Swilly tarreau * bit 31 = MISC_SUM, one bit for 4 ports 11940ba35e7Swilly tarreau */ 12040ba35e7Swilly tarreau #define MVNETA_TX_INTR_MASK(nr_txqs) (((1 << nr_txqs) - 1) << 0) 12140ba35e7Swilly tarreau #define MVNETA_TX_INTR_MASK_ALL (0xff << 0) 12240ba35e7Swilly tarreau #define MVNETA_RX_INTR_MASK(nr_rxqs) (((1 << nr_rxqs) - 1) << 8) 12340ba35e7Swilly tarreau #define MVNETA_RX_INTR_MASK_ALL (0xff << 8) 12440ba35e7Swilly tarreau 125c5aff182SThomas Petazzoni #define MVNETA_INTR_OLD_CAUSE 0x25a8 126c5aff182SThomas Petazzoni #define MVNETA_INTR_OLD_MASK 0x25ac 12740ba35e7Swilly tarreau 12840ba35e7Swilly tarreau /* Data Path Port/Queue Cause Register */ 129c5aff182SThomas Petazzoni #define MVNETA_INTR_MISC_CAUSE 0x25b0 130c5aff182SThomas Petazzoni #define MVNETA_INTR_MISC_MASK 0x25b4 13140ba35e7Swilly tarreau 13240ba35e7Swilly tarreau #define MVNETA_CAUSE_PHY_STATUS_CHANGE BIT(0) 13340ba35e7Swilly tarreau #define MVNETA_CAUSE_LINK_CHANGE BIT(1) 13440ba35e7Swilly tarreau #define MVNETA_CAUSE_PTP BIT(4) 13540ba35e7Swilly tarreau 13640ba35e7Swilly tarreau #define MVNETA_CAUSE_INTERNAL_ADDR_ERR BIT(7) 13740ba35e7Swilly tarreau #define MVNETA_CAUSE_RX_OVERRUN BIT(8) 13840ba35e7Swilly tarreau #define MVNETA_CAUSE_RX_CRC_ERROR BIT(9) 13940ba35e7Swilly tarreau #define MVNETA_CAUSE_RX_LARGE_PKT BIT(10) 14040ba35e7Swilly tarreau #define MVNETA_CAUSE_TX_UNDERUN BIT(11) 14140ba35e7Swilly tarreau #define MVNETA_CAUSE_PRBS_ERR BIT(12) 14240ba35e7Swilly tarreau #define MVNETA_CAUSE_PSC_SYNC_CHANGE BIT(13) 14340ba35e7Swilly tarreau #define MVNETA_CAUSE_SERDES_SYNC_ERR BIT(14) 14440ba35e7Swilly tarreau 14540ba35e7Swilly tarreau #define MVNETA_CAUSE_BMU_ALLOC_ERR_SHIFT 16 14640ba35e7Swilly tarreau #define MVNETA_CAUSE_BMU_ALLOC_ERR_ALL_MASK (0xF << MVNETA_CAUSE_BMU_ALLOC_ERR_SHIFT) 14740ba35e7Swilly tarreau #define MVNETA_CAUSE_BMU_ALLOC_ERR_MASK(pool) (1 << (MVNETA_CAUSE_BMU_ALLOC_ERR_SHIFT + (pool))) 14840ba35e7Swilly tarreau 14940ba35e7Swilly tarreau #define MVNETA_CAUSE_TXQ_ERROR_SHIFT 24 15040ba35e7Swilly tarreau #define MVNETA_CAUSE_TXQ_ERROR_ALL_MASK (0xFF << MVNETA_CAUSE_TXQ_ERROR_SHIFT) 15140ba35e7Swilly tarreau #define MVNETA_CAUSE_TXQ_ERROR_MASK(q) (1 << (MVNETA_CAUSE_TXQ_ERROR_SHIFT + (q))) 15240ba35e7Swilly tarreau 153c5aff182SThomas Petazzoni #define MVNETA_INTR_ENABLE 0x25b8 154c5aff182SThomas Petazzoni #define MVNETA_TXQ_INTR_ENABLE_ALL_MASK 0x0000ff00 15540ba35e7Swilly tarreau #define MVNETA_RXQ_INTR_ENABLE_ALL_MASK 0xff000000 // note: neta says it's 0x000000FF 15640ba35e7Swilly tarreau 157c5aff182SThomas Petazzoni #define MVNETA_RXQ_CMD 0x2680 158c5aff182SThomas Petazzoni #define MVNETA_RXQ_DISABLE_SHIFT 8 159c5aff182SThomas Petazzoni #define MVNETA_RXQ_ENABLE_MASK 0x000000ff 160c5aff182SThomas Petazzoni #define MVETH_TXQ_TOKEN_COUNT_REG(q) (0x2700 + ((q) << 4)) 161c5aff182SThomas Petazzoni #define MVETH_TXQ_TOKEN_CFG_REG(q) (0x2704 + ((q) << 4)) 162c5aff182SThomas Petazzoni #define MVNETA_GMAC_CTRL_0 0x2c00 163c5aff182SThomas Petazzoni #define MVNETA_GMAC_MAX_RX_SIZE_SHIFT 2 164c5aff182SThomas Petazzoni #define MVNETA_GMAC_MAX_RX_SIZE_MASK 0x7ffc 165c5aff182SThomas Petazzoni #define MVNETA_GMAC0_PORT_ENABLE BIT(0) 166c5aff182SThomas Petazzoni #define MVNETA_GMAC_CTRL_2 0x2c08 167a79121d3SThomas Petazzoni #define MVNETA_GMAC2_PCS_ENABLE BIT(3) 168c5aff182SThomas Petazzoni #define MVNETA_GMAC2_PORT_RGMII BIT(4) 169c5aff182SThomas Petazzoni #define MVNETA_GMAC2_PORT_RESET BIT(6) 170c5aff182SThomas Petazzoni #define MVNETA_GMAC_STATUS 0x2c10 171c5aff182SThomas Petazzoni #define MVNETA_GMAC_LINK_UP BIT(0) 172c5aff182SThomas Petazzoni #define MVNETA_GMAC_SPEED_1000 BIT(1) 173c5aff182SThomas Petazzoni #define MVNETA_GMAC_SPEED_100 BIT(2) 174c5aff182SThomas Petazzoni #define MVNETA_GMAC_FULL_DUPLEX BIT(3) 175c5aff182SThomas Petazzoni #define MVNETA_GMAC_RX_FLOW_CTRL_ENABLE BIT(4) 176c5aff182SThomas Petazzoni #define MVNETA_GMAC_TX_FLOW_CTRL_ENABLE BIT(5) 177c5aff182SThomas Petazzoni #define MVNETA_GMAC_RX_FLOW_CTRL_ACTIVE BIT(6) 178c5aff182SThomas Petazzoni #define MVNETA_GMAC_TX_FLOW_CTRL_ACTIVE BIT(7) 179c5aff182SThomas Petazzoni #define MVNETA_GMAC_AUTONEG_CONFIG 0x2c0c 180c5aff182SThomas Petazzoni #define MVNETA_GMAC_FORCE_LINK_DOWN BIT(0) 181c5aff182SThomas Petazzoni #define MVNETA_GMAC_FORCE_LINK_PASS BIT(1) 182c5aff182SThomas Petazzoni #define MVNETA_GMAC_CONFIG_MII_SPEED BIT(5) 183c5aff182SThomas Petazzoni #define MVNETA_GMAC_CONFIG_GMII_SPEED BIT(6) 18471408602SThomas Petazzoni #define MVNETA_GMAC_AN_SPEED_EN BIT(7) 185c5aff182SThomas Petazzoni #define MVNETA_GMAC_CONFIG_FULL_DUPLEX BIT(12) 18671408602SThomas Petazzoni #define MVNETA_GMAC_AN_DUPLEX_EN BIT(13) 187c5aff182SThomas Petazzoni #define MVNETA_MIB_COUNTERS_BASE 0x3080 188c5aff182SThomas Petazzoni #define MVNETA_MIB_LATE_COLLISION 0x7c 189c5aff182SThomas Petazzoni #define MVNETA_DA_FILT_SPEC_MCAST 0x3400 190c5aff182SThomas Petazzoni #define MVNETA_DA_FILT_OTH_MCAST 0x3500 191c5aff182SThomas Petazzoni #define MVNETA_DA_FILT_UCAST_BASE 0x3600 192c5aff182SThomas Petazzoni #define MVNETA_TXQ_BASE_ADDR_REG(q) (0x3c00 + ((q) << 2)) 193c5aff182SThomas Petazzoni #define MVNETA_TXQ_SIZE_REG(q) (0x3c20 + ((q) << 2)) 194c5aff182SThomas Petazzoni #define MVNETA_TXQ_SENT_THRESH_ALL_MASK 0x3fff0000 195c5aff182SThomas Petazzoni #define MVNETA_TXQ_SENT_THRESH_MASK(coal) ((coal) << 16) 196c5aff182SThomas Petazzoni #define MVNETA_TXQ_UPDATE_REG(q) (0x3c60 + ((q) << 2)) 197c5aff182SThomas Petazzoni #define MVNETA_TXQ_DEC_SENT_SHIFT 16 198c5aff182SThomas Petazzoni #define MVNETA_TXQ_STATUS_REG(q) (0x3c40 + ((q) << 2)) 199c5aff182SThomas Petazzoni #define MVNETA_TXQ_SENT_DESC_SHIFT 16 200c5aff182SThomas Petazzoni #define MVNETA_TXQ_SENT_DESC_MASK 0x3fff0000 201c5aff182SThomas Petazzoni #define MVNETA_PORT_TX_RESET 0x3cf0 202c5aff182SThomas Petazzoni #define MVNETA_PORT_TX_DMA_RESET BIT(0) 203c5aff182SThomas Petazzoni #define MVNETA_TX_MTU 0x3e0c 204c5aff182SThomas Petazzoni #define MVNETA_TX_TOKEN_SIZE 0x3e14 205c5aff182SThomas Petazzoni #define MVNETA_TX_TOKEN_SIZE_MAX 0xffffffff 206c5aff182SThomas Petazzoni #define MVNETA_TXQ_TOKEN_SIZE_REG(q) (0x3e40 + ((q) << 2)) 207c5aff182SThomas Petazzoni #define MVNETA_TXQ_TOKEN_SIZE_MAX 0x7fffffff 208c5aff182SThomas Petazzoni 209c5aff182SThomas Petazzoni #define MVNETA_CAUSE_TXQ_SENT_DESC_ALL_MASK 0xff 210c5aff182SThomas Petazzoni 211c5aff182SThomas Petazzoni /* Descriptor ring Macros */ 212c5aff182SThomas Petazzoni #define MVNETA_QUEUE_NEXT_DESC(q, index) \ 213c5aff182SThomas Petazzoni (((index) < (q)->last_desc) ? ((index) + 1) : 0) 214c5aff182SThomas Petazzoni 215c5aff182SThomas Petazzoni /* Various constants */ 216c5aff182SThomas Petazzoni 217c5aff182SThomas Petazzoni /* Coalescing */ 218c5aff182SThomas Petazzoni #define MVNETA_TXDONE_COAL_PKTS 16 219c5aff182SThomas Petazzoni #define MVNETA_RX_COAL_PKTS 32 220c5aff182SThomas Petazzoni #define MVNETA_RX_COAL_USEC 100 221c5aff182SThomas Petazzoni 222c5aff182SThomas Petazzoni /* Napi polling weight */ 223c5aff182SThomas Petazzoni #define MVNETA_RX_POLL_WEIGHT 64 224c5aff182SThomas Petazzoni 2256a20c175SThomas Petazzoni /* The two bytes Marvell header. Either contains a special value used 226c5aff182SThomas Petazzoni * by Marvell switches when a specific hardware mode is enabled (not 227c5aff182SThomas Petazzoni * supported by this driver) or is filled automatically by zeroes on 228c5aff182SThomas Petazzoni * the RX side. Those two bytes being at the front of the Ethernet 229c5aff182SThomas Petazzoni * header, they allow to have the IP header aligned on a 4 bytes 230c5aff182SThomas Petazzoni * boundary automatically: the hardware skips those two bytes on its 231c5aff182SThomas Petazzoni * own. 232c5aff182SThomas Petazzoni */ 233c5aff182SThomas Petazzoni #define MVNETA_MH_SIZE 2 234c5aff182SThomas Petazzoni 235c5aff182SThomas Petazzoni #define MVNETA_VLAN_TAG_LEN 4 236c5aff182SThomas Petazzoni 237c5aff182SThomas Petazzoni #define MVNETA_CPU_D_CACHE_LINE_SIZE 32 238c5aff182SThomas Petazzoni #define MVNETA_TX_CSUM_MAX_SIZE 9800 239c5aff182SThomas Petazzoni #define MVNETA_ACC_MODE_EXT 1 240c5aff182SThomas Petazzoni 241c5aff182SThomas Petazzoni /* Timeout constants */ 242c5aff182SThomas Petazzoni #define MVNETA_TX_DISABLE_TIMEOUT_MSEC 1000 243c5aff182SThomas Petazzoni #define MVNETA_RX_DISABLE_TIMEOUT_MSEC 1000 244c5aff182SThomas Petazzoni #define MVNETA_TX_FIFO_EMPTY_TIMEOUT 10000 245c5aff182SThomas Petazzoni 246c5aff182SThomas Petazzoni #define MVNETA_TX_MTU_MAX 0x3ffff 247c5aff182SThomas Petazzoni 2482adb719dSEzequiel Garcia /* TSO header size */ 2492adb719dSEzequiel Garcia #define TSO_HEADER_SIZE 128 2502adb719dSEzequiel Garcia 251c5aff182SThomas Petazzoni /* Max number of Rx descriptors */ 252c5aff182SThomas Petazzoni #define MVNETA_MAX_RXD 128 253c5aff182SThomas Petazzoni 254c5aff182SThomas Petazzoni /* Max number of Tx descriptors */ 255c5aff182SThomas Petazzoni #define MVNETA_MAX_TXD 532 256c5aff182SThomas Petazzoni 257c5aff182SThomas Petazzoni /* descriptor aligned size */ 258c5aff182SThomas Petazzoni #define MVNETA_DESC_ALIGNED_SIZE 32 259c5aff182SThomas Petazzoni 260c5aff182SThomas Petazzoni #define MVNETA_RX_PKT_SIZE(mtu) \ 261c5aff182SThomas Petazzoni ALIGN((mtu) + MVNETA_MH_SIZE + MVNETA_VLAN_TAG_LEN + \ 262c5aff182SThomas Petazzoni ETH_HLEN + ETH_FCS_LEN, \ 263c5aff182SThomas Petazzoni MVNETA_CPU_D_CACHE_LINE_SIZE) 264c5aff182SThomas Petazzoni 265c5aff182SThomas Petazzoni #define MVNETA_RX_BUF_SIZE(pkt_size) ((pkt_size) + NET_SKB_PAD) 266c5aff182SThomas Petazzoni 26774c41b04Swilly tarreau struct mvneta_pcpu_stats { 268c5aff182SThomas Petazzoni struct u64_stats_sync syncp; 26974c41b04Swilly tarreau u64 rx_packets; 27074c41b04Swilly tarreau u64 rx_bytes; 27174c41b04Swilly tarreau u64 tx_packets; 27274c41b04Swilly tarreau u64 tx_bytes; 273c5aff182SThomas Petazzoni }; 274c5aff182SThomas Petazzoni 275c5aff182SThomas Petazzoni struct mvneta_port { 276c5aff182SThomas Petazzoni int pkt_size; 2778ec2cd48Swilly tarreau unsigned int frag_size; 278c5aff182SThomas Petazzoni void __iomem *base; 279c5aff182SThomas Petazzoni struct mvneta_rx_queue *rxqs; 280c5aff182SThomas Petazzoni struct mvneta_tx_queue *txqs; 281c5aff182SThomas Petazzoni struct net_device *dev; 282c5aff182SThomas Petazzoni 283c5aff182SThomas Petazzoni u32 cause_rx_tx; 284c5aff182SThomas Petazzoni struct napi_struct napi; 285c5aff182SThomas Petazzoni 286c5aff182SThomas Petazzoni /* Napi weight */ 287c5aff182SThomas Petazzoni int weight; 288c5aff182SThomas Petazzoni 289c5aff182SThomas Petazzoni /* Core clock */ 290189dd626SThomas Petazzoni struct clk *clk; 291c5aff182SThomas Petazzoni u8 mcast_count[256]; 292c5aff182SThomas Petazzoni u16 tx_ring_size; 293c5aff182SThomas Petazzoni u16 rx_ring_size; 29474c41b04Swilly tarreau struct mvneta_pcpu_stats *stats; 295c5aff182SThomas Petazzoni 296c5aff182SThomas Petazzoni struct mii_bus *mii_bus; 297c5aff182SThomas Petazzoni struct phy_device *phy_dev; 298c5aff182SThomas Petazzoni phy_interface_t phy_interface; 299c5aff182SThomas Petazzoni struct device_node *phy_node; 300c5aff182SThomas Petazzoni unsigned int link; 301c5aff182SThomas Petazzoni unsigned int duplex; 302c5aff182SThomas Petazzoni unsigned int speed; 303c5aff182SThomas Petazzoni }; 304c5aff182SThomas Petazzoni 3056a20c175SThomas Petazzoni /* The mvneta_tx_desc and mvneta_rx_desc structures describe the 306c5aff182SThomas Petazzoni * layout of the transmit and reception DMA descriptors, and their 307c5aff182SThomas Petazzoni * layout is therefore defined by the hardware design 308c5aff182SThomas Petazzoni */ 3096083ed44SThomas Petazzoni 310c5aff182SThomas Petazzoni #define MVNETA_TX_L3_OFF_SHIFT 0 311c5aff182SThomas Petazzoni #define MVNETA_TX_IP_HLEN_SHIFT 8 312c5aff182SThomas Petazzoni #define MVNETA_TX_L4_UDP BIT(16) 313c5aff182SThomas Petazzoni #define MVNETA_TX_L3_IP6 BIT(17) 314c5aff182SThomas Petazzoni #define MVNETA_TXD_IP_CSUM BIT(18) 315c5aff182SThomas Petazzoni #define MVNETA_TXD_Z_PAD BIT(19) 316c5aff182SThomas Petazzoni #define MVNETA_TXD_L_DESC BIT(20) 317c5aff182SThomas Petazzoni #define MVNETA_TXD_F_DESC BIT(21) 318c5aff182SThomas Petazzoni #define MVNETA_TXD_FLZ_DESC (MVNETA_TXD_Z_PAD | \ 319c5aff182SThomas Petazzoni MVNETA_TXD_L_DESC | \ 320c5aff182SThomas Petazzoni MVNETA_TXD_F_DESC) 321c5aff182SThomas Petazzoni #define MVNETA_TX_L4_CSUM_FULL BIT(30) 322c5aff182SThomas Petazzoni #define MVNETA_TX_L4_CSUM_NOT BIT(31) 323c5aff182SThomas Petazzoni 324c5aff182SThomas Petazzoni #define MVNETA_RXD_ERR_CRC 0x0 325c5aff182SThomas Petazzoni #define MVNETA_RXD_ERR_SUMMARY BIT(16) 326c5aff182SThomas Petazzoni #define MVNETA_RXD_ERR_OVERRUN BIT(17) 327c5aff182SThomas Petazzoni #define MVNETA_RXD_ERR_LEN BIT(18) 328c5aff182SThomas Petazzoni #define MVNETA_RXD_ERR_RESOURCE (BIT(17) | BIT(18)) 329c5aff182SThomas Petazzoni #define MVNETA_RXD_ERR_CODE_MASK (BIT(17) | BIT(18)) 330c5aff182SThomas Petazzoni #define MVNETA_RXD_L3_IP4 BIT(25) 331c5aff182SThomas Petazzoni #define MVNETA_RXD_FIRST_LAST_DESC (BIT(26) | BIT(27)) 332c5aff182SThomas Petazzoni #define MVNETA_RXD_L4_CSUM_OK BIT(30) 333c5aff182SThomas Petazzoni 3349ad8fef6SThomas Petazzoni #if defined(__LITTLE_ENDIAN) 3356083ed44SThomas Petazzoni struct mvneta_tx_desc { 3366083ed44SThomas Petazzoni u32 command; /* Options used by HW for packet transmitting.*/ 3376083ed44SThomas Petazzoni u16 reserverd1; /* csum_l4 (for future use) */ 3386083ed44SThomas Petazzoni u16 data_size; /* Data size of transmitted packet in bytes */ 3396083ed44SThomas Petazzoni u32 buf_phys_addr; /* Physical addr of transmitted buffer */ 3406083ed44SThomas Petazzoni u32 reserved2; /* hw_cmd - (for future use, PMT) */ 3416083ed44SThomas Petazzoni u32 reserved3[4]; /* Reserved - (for future use) */ 3426083ed44SThomas Petazzoni }; 3436083ed44SThomas Petazzoni 3446083ed44SThomas Petazzoni struct mvneta_rx_desc { 3456083ed44SThomas Petazzoni u32 status; /* Info about received packet */ 346c5aff182SThomas Petazzoni u16 reserved1; /* pnc_info - (for future use, PnC) */ 347c5aff182SThomas Petazzoni u16 data_size; /* Size of received packet in bytes */ 3486083ed44SThomas Petazzoni 349c5aff182SThomas Petazzoni u32 buf_phys_addr; /* Physical address of the buffer */ 350c5aff182SThomas Petazzoni u32 reserved2; /* pnc_flow_id (for future use, PnC) */ 3516083ed44SThomas Petazzoni 352c5aff182SThomas Petazzoni u32 buf_cookie; /* cookie for access to RX buffer in rx path */ 353c5aff182SThomas Petazzoni u16 reserved3; /* prefetch_cmd, for future use */ 354c5aff182SThomas Petazzoni u16 reserved4; /* csum_l4 - (for future use, PnC) */ 3556083ed44SThomas Petazzoni 356c5aff182SThomas Petazzoni u32 reserved5; /* pnc_extra PnC (for future use, PnC) */ 357c5aff182SThomas Petazzoni u32 reserved6; /* hw_cmd (for future use, PnC and HWF) */ 358c5aff182SThomas Petazzoni }; 3599ad8fef6SThomas Petazzoni #else 3609ad8fef6SThomas Petazzoni struct mvneta_tx_desc { 3619ad8fef6SThomas Petazzoni u16 data_size; /* Data size of transmitted packet in bytes */ 3629ad8fef6SThomas Petazzoni u16 reserverd1; /* csum_l4 (for future use) */ 3639ad8fef6SThomas Petazzoni u32 command; /* Options used by HW for packet transmitting.*/ 3649ad8fef6SThomas Petazzoni u32 reserved2; /* hw_cmd - (for future use, PMT) */ 3659ad8fef6SThomas Petazzoni u32 buf_phys_addr; /* Physical addr of transmitted buffer */ 3669ad8fef6SThomas Petazzoni u32 reserved3[4]; /* Reserved - (for future use) */ 3679ad8fef6SThomas Petazzoni }; 3689ad8fef6SThomas Petazzoni 3699ad8fef6SThomas Petazzoni struct mvneta_rx_desc { 3709ad8fef6SThomas Petazzoni u16 data_size; /* Size of received packet in bytes */ 3719ad8fef6SThomas Petazzoni u16 reserved1; /* pnc_info - (for future use, PnC) */ 3729ad8fef6SThomas Petazzoni u32 status; /* Info about received packet */ 3739ad8fef6SThomas Petazzoni 3749ad8fef6SThomas Petazzoni u32 reserved2; /* pnc_flow_id (for future use, PnC) */ 3759ad8fef6SThomas Petazzoni u32 buf_phys_addr; /* Physical address of the buffer */ 3769ad8fef6SThomas Petazzoni 3779ad8fef6SThomas Petazzoni u16 reserved4; /* csum_l4 - (for future use, PnC) */ 3789ad8fef6SThomas Petazzoni u16 reserved3; /* prefetch_cmd, for future use */ 3799ad8fef6SThomas Petazzoni u32 buf_cookie; /* cookie for access to RX buffer in rx path */ 3809ad8fef6SThomas Petazzoni 3819ad8fef6SThomas Petazzoni u32 reserved5; /* pnc_extra PnC (for future use, PnC) */ 3829ad8fef6SThomas Petazzoni u32 reserved6; /* hw_cmd (for future use, PnC and HWF) */ 3839ad8fef6SThomas Petazzoni }; 3849ad8fef6SThomas Petazzoni #endif 385c5aff182SThomas Petazzoni 386c5aff182SThomas Petazzoni struct mvneta_tx_queue { 387c5aff182SThomas Petazzoni /* Number of this TX queue, in the range 0-7 */ 388c5aff182SThomas Petazzoni u8 id; 389c5aff182SThomas Petazzoni 390c5aff182SThomas Petazzoni /* Number of TX DMA descriptors in the descriptor ring */ 391c5aff182SThomas Petazzoni int size; 392c5aff182SThomas Petazzoni 393c5aff182SThomas Petazzoni /* Number of currently used TX DMA descriptor in the 3946a20c175SThomas Petazzoni * descriptor ring 3956a20c175SThomas Petazzoni */ 396c5aff182SThomas Petazzoni int count; 397c5aff182SThomas Petazzoni 398c5aff182SThomas Petazzoni /* Array of transmitted skb */ 399c5aff182SThomas Petazzoni struct sk_buff **tx_skb; 400c5aff182SThomas Petazzoni 401c5aff182SThomas Petazzoni /* Index of last TX DMA descriptor that was inserted */ 402c5aff182SThomas Petazzoni int txq_put_index; 403c5aff182SThomas Petazzoni 404c5aff182SThomas Petazzoni /* Index of the TX DMA descriptor to be cleaned up */ 405c5aff182SThomas Petazzoni int txq_get_index; 406c5aff182SThomas Petazzoni 407c5aff182SThomas Petazzoni u32 done_pkts_coal; 408c5aff182SThomas Petazzoni 409c5aff182SThomas Petazzoni /* Virtual address of the TX DMA descriptors array */ 410c5aff182SThomas Petazzoni struct mvneta_tx_desc *descs; 411c5aff182SThomas Petazzoni 412c5aff182SThomas Petazzoni /* DMA address of the TX DMA descriptors array */ 413c5aff182SThomas Petazzoni dma_addr_t descs_phys; 414c5aff182SThomas Petazzoni 415c5aff182SThomas Petazzoni /* Index of the last TX DMA descriptor */ 416c5aff182SThomas Petazzoni int last_desc; 417c5aff182SThomas Petazzoni 418c5aff182SThomas Petazzoni /* Index of the next TX DMA descriptor to process */ 419c5aff182SThomas Petazzoni int next_desc_to_proc; 4202adb719dSEzequiel Garcia 4212adb719dSEzequiel Garcia /* DMA buffers for TSO headers */ 4222adb719dSEzequiel Garcia char *tso_hdrs; 4232adb719dSEzequiel Garcia 4242adb719dSEzequiel Garcia /* DMA address of TSO headers */ 4252adb719dSEzequiel Garcia dma_addr_t tso_hdrs_phys; 426c5aff182SThomas Petazzoni }; 427c5aff182SThomas Petazzoni 428c5aff182SThomas Petazzoni struct mvneta_rx_queue { 429c5aff182SThomas Petazzoni /* rx queue number, in the range 0-7 */ 430c5aff182SThomas Petazzoni u8 id; 431c5aff182SThomas Petazzoni 432c5aff182SThomas Petazzoni /* num of rx descriptors in the rx descriptor ring */ 433c5aff182SThomas Petazzoni int size; 434c5aff182SThomas Petazzoni 435c5aff182SThomas Petazzoni /* counter of times when mvneta_refill() failed */ 436c5aff182SThomas Petazzoni int missed; 437c5aff182SThomas Petazzoni 438c5aff182SThomas Petazzoni u32 pkts_coal; 439c5aff182SThomas Petazzoni u32 time_coal; 440c5aff182SThomas Petazzoni 441c5aff182SThomas Petazzoni /* Virtual address of the RX DMA descriptors array */ 442c5aff182SThomas Petazzoni struct mvneta_rx_desc *descs; 443c5aff182SThomas Petazzoni 444c5aff182SThomas Petazzoni /* DMA address of the RX DMA descriptors array */ 445c5aff182SThomas Petazzoni dma_addr_t descs_phys; 446c5aff182SThomas Petazzoni 447c5aff182SThomas Petazzoni /* Index of the last RX DMA descriptor */ 448c5aff182SThomas Petazzoni int last_desc; 449c5aff182SThomas Petazzoni 450c5aff182SThomas Petazzoni /* Index of the next RX DMA descriptor to process */ 451c5aff182SThomas Petazzoni int next_desc_to_proc; 452c5aff182SThomas Petazzoni }; 453c5aff182SThomas Petazzoni 454c5aff182SThomas Petazzoni static int rxq_number = 8; 455c5aff182SThomas Petazzoni static int txq_number = 8; 456c5aff182SThomas Petazzoni 457c5aff182SThomas Petazzoni static int rxq_def; 458c5aff182SThomas Petazzoni 459f19fadfcSwilly tarreau static int rx_copybreak __read_mostly = 256; 460f19fadfcSwilly tarreau 461c5aff182SThomas Petazzoni #define MVNETA_DRIVER_NAME "mvneta" 462c5aff182SThomas Petazzoni #define MVNETA_DRIVER_VERSION "1.0" 463c5aff182SThomas Petazzoni 464c5aff182SThomas Petazzoni /* Utility/helper methods */ 465c5aff182SThomas Petazzoni 466c5aff182SThomas Petazzoni /* Write helper method */ 467c5aff182SThomas Petazzoni static void mvreg_write(struct mvneta_port *pp, u32 offset, u32 data) 468c5aff182SThomas Petazzoni { 469c5aff182SThomas Petazzoni writel(data, pp->base + offset); 470c5aff182SThomas Petazzoni } 471c5aff182SThomas Petazzoni 472c5aff182SThomas Petazzoni /* Read helper method */ 473c5aff182SThomas Petazzoni static u32 mvreg_read(struct mvneta_port *pp, u32 offset) 474c5aff182SThomas Petazzoni { 475c5aff182SThomas Petazzoni return readl(pp->base + offset); 476c5aff182SThomas Petazzoni } 477c5aff182SThomas Petazzoni 478c5aff182SThomas Petazzoni /* Increment txq get counter */ 479c5aff182SThomas Petazzoni static void mvneta_txq_inc_get(struct mvneta_tx_queue *txq) 480c5aff182SThomas Petazzoni { 481c5aff182SThomas Petazzoni txq->txq_get_index++; 482c5aff182SThomas Petazzoni if (txq->txq_get_index == txq->size) 483c5aff182SThomas Petazzoni txq->txq_get_index = 0; 484c5aff182SThomas Petazzoni } 485c5aff182SThomas Petazzoni 486c5aff182SThomas Petazzoni /* Increment txq put counter */ 487c5aff182SThomas Petazzoni static void mvneta_txq_inc_put(struct mvneta_tx_queue *txq) 488c5aff182SThomas Petazzoni { 489c5aff182SThomas Petazzoni txq->txq_put_index++; 490c5aff182SThomas Petazzoni if (txq->txq_put_index == txq->size) 491c5aff182SThomas Petazzoni txq->txq_put_index = 0; 492c5aff182SThomas Petazzoni } 493c5aff182SThomas Petazzoni 494c5aff182SThomas Petazzoni 495c5aff182SThomas Petazzoni /* Clear all MIB counters */ 496c5aff182SThomas Petazzoni static void mvneta_mib_counters_clear(struct mvneta_port *pp) 497c5aff182SThomas Petazzoni { 498c5aff182SThomas Petazzoni int i; 499c5aff182SThomas Petazzoni u32 dummy; 500c5aff182SThomas Petazzoni 501c5aff182SThomas Petazzoni /* Perform dummy reads from MIB counters */ 502c5aff182SThomas Petazzoni for (i = 0; i < MVNETA_MIB_LATE_COLLISION; i += 4) 503c5aff182SThomas Petazzoni dummy = mvreg_read(pp, (MVNETA_MIB_COUNTERS_BASE + i)); 504c5aff182SThomas Petazzoni } 505c5aff182SThomas Petazzoni 506c5aff182SThomas Petazzoni /* Get System Network Statistics */ 507c5aff182SThomas Petazzoni struct rtnl_link_stats64 *mvneta_get_stats64(struct net_device *dev, 508c5aff182SThomas Petazzoni struct rtnl_link_stats64 *stats) 509c5aff182SThomas Petazzoni { 510c5aff182SThomas Petazzoni struct mvneta_port *pp = netdev_priv(dev); 511c5aff182SThomas Petazzoni unsigned int start; 51274c41b04Swilly tarreau int cpu; 513c5aff182SThomas Petazzoni 51474c41b04Swilly tarreau for_each_possible_cpu(cpu) { 51574c41b04Swilly tarreau struct mvneta_pcpu_stats *cpu_stats; 51674c41b04Swilly tarreau u64 rx_packets; 51774c41b04Swilly tarreau u64 rx_bytes; 51874c41b04Swilly tarreau u64 tx_packets; 51974c41b04Swilly tarreau u64 tx_bytes; 520c5aff182SThomas Petazzoni 52174c41b04Swilly tarreau cpu_stats = per_cpu_ptr(pp->stats, cpu); 522c5aff182SThomas Petazzoni do { 52357a7744eSEric W. Biederman start = u64_stats_fetch_begin_irq(&cpu_stats->syncp); 52474c41b04Swilly tarreau rx_packets = cpu_stats->rx_packets; 52574c41b04Swilly tarreau rx_bytes = cpu_stats->rx_bytes; 52674c41b04Swilly tarreau tx_packets = cpu_stats->tx_packets; 52774c41b04Swilly tarreau tx_bytes = cpu_stats->tx_bytes; 52857a7744eSEric W. Biederman } while (u64_stats_fetch_retry_irq(&cpu_stats->syncp, start)); 529c5aff182SThomas Petazzoni 53074c41b04Swilly tarreau stats->rx_packets += rx_packets; 53174c41b04Swilly tarreau stats->rx_bytes += rx_bytes; 53274c41b04Swilly tarreau stats->tx_packets += tx_packets; 53374c41b04Swilly tarreau stats->tx_bytes += tx_bytes; 53474c41b04Swilly tarreau } 535c5aff182SThomas Petazzoni 536c5aff182SThomas Petazzoni stats->rx_errors = dev->stats.rx_errors; 537c5aff182SThomas Petazzoni stats->rx_dropped = dev->stats.rx_dropped; 538c5aff182SThomas Petazzoni 539c5aff182SThomas Petazzoni stats->tx_dropped = dev->stats.tx_dropped; 540c5aff182SThomas Petazzoni 541c5aff182SThomas Petazzoni return stats; 542c5aff182SThomas Petazzoni } 543c5aff182SThomas Petazzoni 544c5aff182SThomas Petazzoni /* Rx descriptors helper methods */ 545c5aff182SThomas Petazzoni 5465428213cSwilly tarreau /* Checks whether the RX descriptor having this status is both the first 5475428213cSwilly tarreau * and the last descriptor for the RX packet. Each RX packet is currently 548c5aff182SThomas Petazzoni * received through a single RX descriptor, so not having each RX 549c5aff182SThomas Petazzoni * descriptor with its first and last bits set is an error 550c5aff182SThomas Petazzoni */ 5515428213cSwilly tarreau static int mvneta_rxq_desc_is_first_last(u32 status) 552c5aff182SThomas Petazzoni { 5535428213cSwilly tarreau return (status & MVNETA_RXD_FIRST_LAST_DESC) == 554c5aff182SThomas Petazzoni MVNETA_RXD_FIRST_LAST_DESC; 555c5aff182SThomas Petazzoni } 556c5aff182SThomas Petazzoni 557c5aff182SThomas Petazzoni /* Add number of descriptors ready to receive new packets */ 558c5aff182SThomas Petazzoni static void mvneta_rxq_non_occup_desc_add(struct mvneta_port *pp, 559c5aff182SThomas Petazzoni struct mvneta_rx_queue *rxq, 560c5aff182SThomas Petazzoni int ndescs) 561c5aff182SThomas Petazzoni { 562c5aff182SThomas Petazzoni /* Only MVNETA_RXQ_ADD_NON_OCCUPIED_MAX (255) descriptors can 5636a20c175SThomas Petazzoni * be added at once 5646a20c175SThomas Petazzoni */ 565c5aff182SThomas Petazzoni while (ndescs > MVNETA_RXQ_ADD_NON_OCCUPIED_MAX) { 566c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id), 567c5aff182SThomas Petazzoni (MVNETA_RXQ_ADD_NON_OCCUPIED_MAX << 568c5aff182SThomas Petazzoni MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT)); 569c5aff182SThomas Petazzoni ndescs -= MVNETA_RXQ_ADD_NON_OCCUPIED_MAX; 570c5aff182SThomas Petazzoni } 571c5aff182SThomas Petazzoni 572c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id), 573c5aff182SThomas Petazzoni (ndescs << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT)); 574c5aff182SThomas Petazzoni } 575c5aff182SThomas Petazzoni 576c5aff182SThomas Petazzoni /* Get number of RX descriptors occupied by received packets */ 577c5aff182SThomas Petazzoni static int mvneta_rxq_busy_desc_num_get(struct mvneta_port *pp, 578c5aff182SThomas Petazzoni struct mvneta_rx_queue *rxq) 579c5aff182SThomas Petazzoni { 580c5aff182SThomas Petazzoni u32 val; 581c5aff182SThomas Petazzoni 582c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_RXQ_STATUS_REG(rxq->id)); 583c5aff182SThomas Petazzoni return val & MVNETA_RXQ_OCCUPIED_ALL_MASK; 584c5aff182SThomas Petazzoni } 585c5aff182SThomas Petazzoni 5866a20c175SThomas Petazzoni /* Update num of rx desc called upon return from rx path or 587c5aff182SThomas Petazzoni * from mvneta_rxq_drop_pkts(). 588c5aff182SThomas Petazzoni */ 589c5aff182SThomas Petazzoni static void mvneta_rxq_desc_num_update(struct mvneta_port *pp, 590c5aff182SThomas Petazzoni struct mvneta_rx_queue *rxq, 591c5aff182SThomas Petazzoni int rx_done, int rx_filled) 592c5aff182SThomas Petazzoni { 593c5aff182SThomas Petazzoni u32 val; 594c5aff182SThomas Petazzoni 595c5aff182SThomas Petazzoni if ((rx_done <= 0xff) && (rx_filled <= 0xff)) { 596c5aff182SThomas Petazzoni val = rx_done | 597c5aff182SThomas Petazzoni (rx_filled << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT); 598c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id), val); 599c5aff182SThomas Petazzoni return; 600c5aff182SThomas Petazzoni } 601c5aff182SThomas Petazzoni 602c5aff182SThomas Petazzoni /* Only 255 descriptors can be added at once */ 603c5aff182SThomas Petazzoni while ((rx_done > 0) || (rx_filled > 0)) { 604c5aff182SThomas Petazzoni if (rx_done <= 0xff) { 605c5aff182SThomas Petazzoni val = rx_done; 606c5aff182SThomas Petazzoni rx_done = 0; 607c5aff182SThomas Petazzoni } else { 608c5aff182SThomas Petazzoni val = 0xff; 609c5aff182SThomas Petazzoni rx_done -= 0xff; 610c5aff182SThomas Petazzoni } 611c5aff182SThomas Petazzoni if (rx_filled <= 0xff) { 612c5aff182SThomas Petazzoni val |= rx_filled << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT; 613c5aff182SThomas Petazzoni rx_filled = 0; 614c5aff182SThomas Petazzoni } else { 615c5aff182SThomas Petazzoni val |= 0xff << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT; 616c5aff182SThomas Petazzoni rx_filled -= 0xff; 617c5aff182SThomas Petazzoni } 618c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id), val); 619c5aff182SThomas Petazzoni } 620c5aff182SThomas Petazzoni } 621c5aff182SThomas Petazzoni 622c5aff182SThomas Petazzoni /* Get pointer to next RX descriptor to be processed by SW */ 623c5aff182SThomas Petazzoni static struct mvneta_rx_desc * 624c5aff182SThomas Petazzoni mvneta_rxq_next_desc_get(struct mvneta_rx_queue *rxq) 625c5aff182SThomas Petazzoni { 626c5aff182SThomas Petazzoni int rx_desc = rxq->next_desc_to_proc; 627c5aff182SThomas Petazzoni 628c5aff182SThomas Petazzoni rxq->next_desc_to_proc = MVNETA_QUEUE_NEXT_DESC(rxq, rx_desc); 62934e4179dSwilly tarreau prefetch(rxq->descs + rxq->next_desc_to_proc); 630c5aff182SThomas Petazzoni return rxq->descs + rx_desc; 631c5aff182SThomas Petazzoni } 632c5aff182SThomas Petazzoni 633c5aff182SThomas Petazzoni /* Change maximum receive size of the port. */ 634c5aff182SThomas Petazzoni static void mvneta_max_rx_size_set(struct mvneta_port *pp, int max_rx_size) 635c5aff182SThomas Petazzoni { 636c5aff182SThomas Petazzoni u32 val; 637c5aff182SThomas Petazzoni 638c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_GMAC_CTRL_0); 639c5aff182SThomas Petazzoni val &= ~MVNETA_GMAC_MAX_RX_SIZE_MASK; 640c5aff182SThomas Petazzoni val |= ((max_rx_size - MVNETA_MH_SIZE) / 2) << 641c5aff182SThomas Petazzoni MVNETA_GMAC_MAX_RX_SIZE_SHIFT; 642c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_GMAC_CTRL_0, val); 643c5aff182SThomas Petazzoni } 644c5aff182SThomas Petazzoni 645c5aff182SThomas Petazzoni 646c5aff182SThomas Petazzoni /* Set rx queue offset */ 647c5aff182SThomas Petazzoni static void mvneta_rxq_offset_set(struct mvneta_port *pp, 648c5aff182SThomas Petazzoni struct mvneta_rx_queue *rxq, 649c5aff182SThomas Petazzoni int offset) 650c5aff182SThomas Petazzoni { 651c5aff182SThomas Petazzoni u32 val; 652c5aff182SThomas Petazzoni 653c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_RXQ_CONFIG_REG(rxq->id)); 654c5aff182SThomas Petazzoni val &= ~MVNETA_RXQ_PKT_OFFSET_ALL_MASK; 655c5aff182SThomas Petazzoni 656c5aff182SThomas Petazzoni /* Offset is in */ 657c5aff182SThomas Petazzoni val |= MVNETA_RXQ_PKT_OFFSET_MASK(offset >> 3); 658c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_RXQ_CONFIG_REG(rxq->id), val); 659c5aff182SThomas Petazzoni } 660c5aff182SThomas Petazzoni 661c5aff182SThomas Petazzoni 662c5aff182SThomas Petazzoni /* Tx descriptors helper methods */ 663c5aff182SThomas Petazzoni 664c5aff182SThomas Petazzoni /* Update HW with number of TX descriptors to be sent */ 665c5aff182SThomas Petazzoni static void mvneta_txq_pend_desc_add(struct mvneta_port *pp, 666c5aff182SThomas Petazzoni struct mvneta_tx_queue *txq, 667c5aff182SThomas Petazzoni int pend_desc) 668c5aff182SThomas Petazzoni { 669c5aff182SThomas Petazzoni u32 val; 670c5aff182SThomas Petazzoni 671c5aff182SThomas Petazzoni /* Only 255 descriptors can be added at once ; Assume caller 6726a20c175SThomas Petazzoni * process TX desriptors in quanta less than 256 6736a20c175SThomas Petazzoni */ 674c5aff182SThomas Petazzoni val = pend_desc; 675c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val); 676c5aff182SThomas Petazzoni } 677c5aff182SThomas Petazzoni 678c5aff182SThomas Petazzoni /* Get pointer to next TX descriptor to be processed (send) by HW */ 679c5aff182SThomas Petazzoni static struct mvneta_tx_desc * 680c5aff182SThomas Petazzoni mvneta_txq_next_desc_get(struct mvneta_tx_queue *txq) 681c5aff182SThomas Petazzoni { 682c5aff182SThomas Petazzoni int tx_desc = txq->next_desc_to_proc; 683c5aff182SThomas Petazzoni 684c5aff182SThomas Petazzoni txq->next_desc_to_proc = MVNETA_QUEUE_NEXT_DESC(txq, tx_desc); 685c5aff182SThomas Petazzoni return txq->descs + tx_desc; 686c5aff182SThomas Petazzoni } 687c5aff182SThomas Petazzoni 688c5aff182SThomas Petazzoni /* Release the last allocated TX descriptor. Useful to handle DMA 6896a20c175SThomas Petazzoni * mapping failures in the TX path. 6906a20c175SThomas Petazzoni */ 691c5aff182SThomas Petazzoni static void mvneta_txq_desc_put(struct mvneta_tx_queue *txq) 692c5aff182SThomas Petazzoni { 693c5aff182SThomas Petazzoni if (txq->next_desc_to_proc == 0) 694c5aff182SThomas Petazzoni txq->next_desc_to_proc = txq->last_desc - 1; 695c5aff182SThomas Petazzoni else 696c5aff182SThomas Petazzoni txq->next_desc_to_proc--; 697c5aff182SThomas Petazzoni } 698c5aff182SThomas Petazzoni 699c5aff182SThomas Petazzoni /* Set rxq buf size */ 700c5aff182SThomas Petazzoni static void mvneta_rxq_buf_size_set(struct mvneta_port *pp, 701c5aff182SThomas Petazzoni struct mvneta_rx_queue *rxq, 702c5aff182SThomas Petazzoni int buf_size) 703c5aff182SThomas Petazzoni { 704c5aff182SThomas Petazzoni u32 val; 705c5aff182SThomas Petazzoni 706c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_RXQ_SIZE_REG(rxq->id)); 707c5aff182SThomas Petazzoni 708c5aff182SThomas Petazzoni val &= ~MVNETA_RXQ_BUF_SIZE_MASK; 709c5aff182SThomas Petazzoni val |= ((buf_size >> 3) << MVNETA_RXQ_BUF_SIZE_SHIFT); 710c5aff182SThomas Petazzoni 711c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_RXQ_SIZE_REG(rxq->id), val); 712c5aff182SThomas Petazzoni } 713c5aff182SThomas Petazzoni 714c5aff182SThomas Petazzoni /* Disable buffer management (BM) */ 715c5aff182SThomas Petazzoni static void mvneta_rxq_bm_disable(struct mvneta_port *pp, 716c5aff182SThomas Petazzoni struct mvneta_rx_queue *rxq) 717c5aff182SThomas Petazzoni { 718c5aff182SThomas Petazzoni u32 val; 719c5aff182SThomas Petazzoni 720c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_RXQ_CONFIG_REG(rxq->id)); 721c5aff182SThomas Petazzoni val &= ~MVNETA_RXQ_HW_BUF_ALLOC; 722c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_RXQ_CONFIG_REG(rxq->id), val); 723c5aff182SThomas Petazzoni } 724c5aff182SThomas Petazzoni 725c5aff182SThomas Petazzoni /* Start the Ethernet port RX and TX activity */ 726c5aff182SThomas Petazzoni static void mvneta_port_up(struct mvneta_port *pp) 727c5aff182SThomas Petazzoni { 728c5aff182SThomas Petazzoni int queue; 729c5aff182SThomas Petazzoni u32 q_map; 730c5aff182SThomas Petazzoni 731c5aff182SThomas Petazzoni /* Enable all initialized TXs. */ 732c5aff182SThomas Petazzoni mvneta_mib_counters_clear(pp); 733c5aff182SThomas Petazzoni q_map = 0; 734c5aff182SThomas Petazzoni for (queue = 0; queue < txq_number; queue++) { 735c5aff182SThomas Petazzoni struct mvneta_tx_queue *txq = &pp->txqs[queue]; 736c5aff182SThomas Petazzoni if (txq->descs != NULL) 737c5aff182SThomas Petazzoni q_map |= (1 << queue); 738c5aff182SThomas Petazzoni } 739c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_TXQ_CMD, q_map); 740c5aff182SThomas Petazzoni 741c5aff182SThomas Petazzoni /* Enable all initialized RXQs. */ 742c5aff182SThomas Petazzoni q_map = 0; 743c5aff182SThomas Petazzoni for (queue = 0; queue < rxq_number; queue++) { 744c5aff182SThomas Petazzoni struct mvneta_rx_queue *rxq = &pp->rxqs[queue]; 745c5aff182SThomas Petazzoni if (rxq->descs != NULL) 746c5aff182SThomas Petazzoni q_map |= (1 << queue); 747c5aff182SThomas Petazzoni } 748c5aff182SThomas Petazzoni 749c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_RXQ_CMD, q_map); 750c5aff182SThomas Petazzoni } 751c5aff182SThomas Petazzoni 752c5aff182SThomas Petazzoni /* Stop the Ethernet port activity */ 753c5aff182SThomas Petazzoni static void mvneta_port_down(struct mvneta_port *pp) 754c5aff182SThomas Petazzoni { 755c5aff182SThomas Petazzoni u32 val; 756c5aff182SThomas Petazzoni int count; 757c5aff182SThomas Petazzoni 758c5aff182SThomas Petazzoni /* Stop Rx port activity. Check port Rx activity. */ 759c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_RXQ_CMD) & MVNETA_RXQ_ENABLE_MASK; 760c5aff182SThomas Petazzoni 761c5aff182SThomas Petazzoni /* Issue stop command for active channels only */ 762c5aff182SThomas Petazzoni if (val != 0) 763c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_RXQ_CMD, 764c5aff182SThomas Petazzoni val << MVNETA_RXQ_DISABLE_SHIFT); 765c5aff182SThomas Petazzoni 766c5aff182SThomas Petazzoni /* Wait for all Rx activity to terminate. */ 767c5aff182SThomas Petazzoni count = 0; 768c5aff182SThomas Petazzoni do { 769c5aff182SThomas Petazzoni if (count++ >= MVNETA_RX_DISABLE_TIMEOUT_MSEC) { 770c5aff182SThomas Petazzoni netdev_warn(pp->dev, 771c5aff182SThomas Petazzoni "TIMEOUT for RX stopped ! rx_queue_cmd: 0x08%x\n", 772c5aff182SThomas Petazzoni val); 773c5aff182SThomas Petazzoni break; 774c5aff182SThomas Petazzoni } 775c5aff182SThomas Petazzoni mdelay(1); 776c5aff182SThomas Petazzoni 777c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_RXQ_CMD); 778c5aff182SThomas Petazzoni } while (val & 0xff); 779c5aff182SThomas Petazzoni 780c5aff182SThomas Petazzoni /* Stop Tx port activity. Check port Tx activity. Issue stop 7816a20c175SThomas Petazzoni * command for active channels only 7826a20c175SThomas Petazzoni */ 783c5aff182SThomas Petazzoni val = (mvreg_read(pp, MVNETA_TXQ_CMD)) & MVNETA_TXQ_ENABLE_MASK; 784c5aff182SThomas Petazzoni 785c5aff182SThomas Petazzoni if (val != 0) 786c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_TXQ_CMD, 787c5aff182SThomas Petazzoni (val << MVNETA_TXQ_DISABLE_SHIFT)); 788c5aff182SThomas Petazzoni 789c5aff182SThomas Petazzoni /* Wait for all Tx activity to terminate. */ 790c5aff182SThomas Petazzoni count = 0; 791c5aff182SThomas Petazzoni do { 792c5aff182SThomas Petazzoni if (count++ >= MVNETA_TX_DISABLE_TIMEOUT_MSEC) { 793c5aff182SThomas Petazzoni netdev_warn(pp->dev, 794c5aff182SThomas Petazzoni "TIMEOUT for TX stopped status=0x%08x\n", 795c5aff182SThomas Petazzoni val); 796c5aff182SThomas Petazzoni break; 797c5aff182SThomas Petazzoni } 798c5aff182SThomas Petazzoni mdelay(1); 799c5aff182SThomas Petazzoni 800c5aff182SThomas Petazzoni /* Check TX Command reg that all Txqs are stopped */ 801c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_TXQ_CMD); 802c5aff182SThomas Petazzoni 803c5aff182SThomas Petazzoni } while (val & 0xff); 804c5aff182SThomas Petazzoni 805c5aff182SThomas Petazzoni /* Double check to verify that TX FIFO is empty */ 806c5aff182SThomas Petazzoni count = 0; 807c5aff182SThomas Petazzoni do { 808c5aff182SThomas Petazzoni if (count++ >= MVNETA_TX_FIFO_EMPTY_TIMEOUT) { 809c5aff182SThomas Petazzoni netdev_warn(pp->dev, 810c5aff182SThomas Petazzoni "TX FIFO empty timeout status=0x08%x\n", 811c5aff182SThomas Petazzoni val); 812c5aff182SThomas Petazzoni break; 813c5aff182SThomas Petazzoni } 814c5aff182SThomas Petazzoni mdelay(1); 815c5aff182SThomas Petazzoni 816c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_PORT_STATUS); 817c5aff182SThomas Petazzoni } while (!(val & MVNETA_TX_FIFO_EMPTY) && 818c5aff182SThomas Petazzoni (val & MVNETA_TX_IN_PRGRS)); 819c5aff182SThomas Petazzoni 820c5aff182SThomas Petazzoni udelay(200); 821c5aff182SThomas Petazzoni } 822c5aff182SThomas Petazzoni 823c5aff182SThomas Petazzoni /* Enable the port by setting the port enable bit of the MAC control register */ 824c5aff182SThomas Petazzoni static void mvneta_port_enable(struct mvneta_port *pp) 825c5aff182SThomas Petazzoni { 826c5aff182SThomas Petazzoni u32 val; 827c5aff182SThomas Petazzoni 828c5aff182SThomas Petazzoni /* Enable port */ 829c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_GMAC_CTRL_0); 830c5aff182SThomas Petazzoni val |= MVNETA_GMAC0_PORT_ENABLE; 831c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_GMAC_CTRL_0, val); 832c5aff182SThomas Petazzoni } 833c5aff182SThomas Petazzoni 834c5aff182SThomas Petazzoni /* Disable the port and wait for about 200 usec before retuning */ 835c5aff182SThomas Petazzoni static void mvneta_port_disable(struct mvneta_port *pp) 836c5aff182SThomas Petazzoni { 837c5aff182SThomas Petazzoni u32 val; 838c5aff182SThomas Petazzoni 839c5aff182SThomas Petazzoni /* Reset the Enable bit in the Serial Control Register */ 840c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_GMAC_CTRL_0); 841c5aff182SThomas Petazzoni val &= ~MVNETA_GMAC0_PORT_ENABLE; 842c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_GMAC_CTRL_0, val); 843c5aff182SThomas Petazzoni 844c5aff182SThomas Petazzoni udelay(200); 845c5aff182SThomas Petazzoni } 846c5aff182SThomas Petazzoni 847c5aff182SThomas Petazzoni /* Multicast tables methods */ 848c5aff182SThomas Petazzoni 849c5aff182SThomas Petazzoni /* Set all entries in Unicast MAC Table; queue==-1 means reject all */ 850c5aff182SThomas Petazzoni static void mvneta_set_ucast_table(struct mvneta_port *pp, int queue) 851c5aff182SThomas Petazzoni { 852c5aff182SThomas Petazzoni int offset; 853c5aff182SThomas Petazzoni u32 val; 854c5aff182SThomas Petazzoni 855c5aff182SThomas Petazzoni if (queue == -1) { 856c5aff182SThomas Petazzoni val = 0; 857c5aff182SThomas Petazzoni } else { 858c5aff182SThomas Petazzoni val = 0x1 | (queue << 1); 859c5aff182SThomas Petazzoni val |= (val << 24) | (val << 16) | (val << 8); 860c5aff182SThomas Petazzoni } 861c5aff182SThomas Petazzoni 862c5aff182SThomas Petazzoni for (offset = 0; offset <= 0xc; offset += 4) 863c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_DA_FILT_UCAST_BASE + offset, val); 864c5aff182SThomas Petazzoni } 865c5aff182SThomas Petazzoni 866c5aff182SThomas Petazzoni /* Set all entries in Special Multicast MAC Table; queue==-1 means reject all */ 867c5aff182SThomas Petazzoni static void mvneta_set_special_mcast_table(struct mvneta_port *pp, int queue) 868c5aff182SThomas Petazzoni { 869c5aff182SThomas Petazzoni int offset; 870c5aff182SThomas Petazzoni u32 val; 871c5aff182SThomas Petazzoni 872c5aff182SThomas Petazzoni if (queue == -1) { 873c5aff182SThomas Petazzoni val = 0; 874c5aff182SThomas Petazzoni } else { 875c5aff182SThomas Petazzoni val = 0x1 | (queue << 1); 876c5aff182SThomas Petazzoni val |= (val << 24) | (val << 16) | (val << 8); 877c5aff182SThomas Petazzoni } 878c5aff182SThomas Petazzoni 879c5aff182SThomas Petazzoni for (offset = 0; offset <= 0xfc; offset += 4) 880c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_DA_FILT_SPEC_MCAST + offset, val); 881c5aff182SThomas Petazzoni 882c5aff182SThomas Petazzoni } 883c5aff182SThomas Petazzoni 884c5aff182SThomas Petazzoni /* Set all entries in Other Multicast MAC Table. queue==-1 means reject all */ 885c5aff182SThomas Petazzoni static void mvneta_set_other_mcast_table(struct mvneta_port *pp, int queue) 886c5aff182SThomas Petazzoni { 887c5aff182SThomas Petazzoni int offset; 888c5aff182SThomas Petazzoni u32 val; 889c5aff182SThomas Petazzoni 890c5aff182SThomas Petazzoni if (queue == -1) { 891c5aff182SThomas Petazzoni memset(pp->mcast_count, 0, sizeof(pp->mcast_count)); 892c5aff182SThomas Petazzoni val = 0; 893c5aff182SThomas Petazzoni } else { 894c5aff182SThomas Petazzoni memset(pp->mcast_count, 1, sizeof(pp->mcast_count)); 895c5aff182SThomas Petazzoni val = 0x1 | (queue << 1); 896c5aff182SThomas Petazzoni val |= (val << 24) | (val << 16) | (val << 8); 897c5aff182SThomas Petazzoni } 898c5aff182SThomas Petazzoni 899c5aff182SThomas Petazzoni for (offset = 0; offset <= 0xfc; offset += 4) 900c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_DA_FILT_OTH_MCAST + offset, val); 901c5aff182SThomas Petazzoni } 902c5aff182SThomas Petazzoni 903c5aff182SThomas Petazzoni /* This method sets defaults to the NETA port: 904c5aff182SThomas Petazzoni * Clears interrupt Cause and Mask registers. 905c5aff182SThomas Petazzoni * Clears all MAC tables. 906c5aff182SThomas Petazzoni * Sets defaults to all registers. 907c5aff182SThomas Petazzoni * Resets RX and TX descriptor rings. 908c5aff182SThomas Petazzoni * Resets PHY. 909c5aff182SThomas Petazzoni * This method can be called after mvneta_port_down() to return the port 910c5aff182SThomas Petazzoni * settings to defaults. 911c5aff182SThomas Petazzoni */ 912c5aff182SThomas Petazzoni static void mvneta_defaults_set(struct mvneta_port *pp) 913c5aff182SThomas Petazzoni { 914c5aff182SThomas Petazzoni int cpu; 915c5aff182SThomas Petazzoni int queue; 916c5aff182SThomas Petazzoni u32 val; 917c5aff182SThomas Petazzoni 918c5aff182SThomas Petazzoni /* Clear all Cause registers */ 919c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_INTR_NEW_CAUSE, 0); 920c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_INTR_OLD_CAUSE, 0); 921c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_INTR_MISC_CAUSE, 0); 922c5aff182SThomas Petazzoni 923c5aff182SThomas Petazzoni /* Mask all interrupts */ 924c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_INTR_NEW_MASK, 0); 925c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_INTR_OLD_MASK, 0); 926c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_INTR_MISC_MASK, 0); 927c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_INTR_ENABLE, 0); 928c5aff182SThomas Petazzoni 929c5aff182SThomas Petazzoni /* Enable MBUS Retry bit16 */ 930c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_MBUS_RETRY, 0x20); 931c5aff182SThomas Petazzoni 932c5aff182SThomas Petazzoni /* Set CPU queue access map - all CPUs have access to all RX 9336a20c175SThomas Petazzoni * queues and to all TX queues 9346a20c175SThomas Petazzoni */ 935c5aff182SThomas Petazzoni for (cpu = 0; cpu < CONFIG_NR_CPUS; cpu++) 936c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_CPU_MAP(cpu), 937c5aff182SThomas Petazzoni (MVNETA_CPU_RXQ_ACCESS_ALL_MASK | 938c5aff182SThomas Petazzoni MVNETA_CPU_TXQ_ACCESS_ALL_MASK)); 939c5aff182SThomas Petazzoni 940c5aff182SThomas Petazzoni /* Reset RX and TX DMAs */ 941c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_PORT_RX_RESET, MVNETA_PORT_RX_DMA_RESET); 942c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_PORT_TX_RESET, MVNETA_PORT_TX_DMA_RESET); 943c5aff182SThomas Petazzoni 944c5aff182SThomas Petazzoni /* Disable Legacy WRR, Disable EJP, Release from reset */ 945c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_TXQ_CMD_1, 0); 946c5aff182SThomas Petazzoni for (queue = 0; queue < txq_number; queue++) { 947c5aff182SThomas Petazzoni mvreg_write(pp, MVETH_TXQ_TOKEN_COUNT_REG(queue), 0); 948c5aff182SThomas Petazzoni mvreg_write(pp, MVETH_TXQ_TOKEN_CFG_REG(queue), 0); 949c5aff182SThomas Petazzoni } 950c5aff182SThomas Petazzoni 951c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_PORT_TX_RESET, 0); 952c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_PORT_RX_RESET, 0); 953c5aff182SThomas Petazzoni 954c5aff182SThomas Petazzoni /* Set Port Acceleration Mode */ 955c5aff182SThomas Petazzoni val = MVNETA_ACC_MODE_EXT; 956c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_ACC_MODE, val); 957c5aff182SThomas Petazzoni 958c5aff182SThomas Petazzoni /* Update val of portCfg register accordingly with all RxQueue types */ 959c5aff182SThomas Petazzoni val = MVNETA_PORT_CONFIG_DEFL_VALUE(rxq_def); 960c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_PORT_CONFIG, val); 961c5aff182SThomas Petazzoni 962c5aff182SThomas Petazzoni val = 0; 963c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_PORT_CONFIG_EXTEND, val); 964c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_RX_MIN_FRAME_SIZE, 64); 965c5aff182SThomas Petazzoni 966c5aff182SThomas Petazzoni /* Build PORT_SDMA_CONFIG_REG */ 967c5aff182SThomas Petazzoni val = 0; 968c5aff182SThomas Petazzoni 969c5aff182SThomas Petazzoni /* Default burst size */ 970c5aff182SThomas Petazzoni val |= MVNETA_TX_BRST_SZ_MASK(MVNETA_SDMA_BRST_SIZE_16); 971c5aff182SThomas Petazzoni val |= MVNETA_RX_BRST_SZ_MASK(MVNETA_SDMA_BRST_SIZE_16); 9729ad8fef6SThomas Petazzoni val |= MVNETA_RX_NO_DATA_SWAP | MVNETA_TX_NO_DATA_SWAP; 973c5aff182SThomas Petazzoni 9749ad8fef6SThomas Petazzoni #if defined(__BIG_ENDIAN) 9759ad8fef6SThomas Petazzoni val |= MVNETA_DESC_SWAP; 9769ad8fef6SThomas Petazzoni #endif 977c5aff182SThomas Petazzoni 978c5aff182SThomas Petazzoni /* Assign port SDMA configuration */ 979c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_SDMA_CONFIG, val); 980c5aff182SThomas Petazzoni 98171408602SThomas Petazzoni /* Disable PHY polling in hardware, since we're using the 98271408602SThomas Petazzoni * kernel phylib to do this. 98371408602SThomas Petazzoni */ 98471408602SThomas Petazzoni val = mvreg_read(pp, MVNETA_UNIT_CONTROL); 98571408602SThomas Petazzoni val &= ~MVNETA_PHY_POLLING_ENABLE; 98671408602SThomas Petazzoni mvreg_write(pp, MVNETA_UNIT_CONTROL, val); 98771408602SThomas Petazzoni 988c5aff182SThomas Petazzoni mvneta_set_ucast_table(pp, -1); 989c5aff182SThomas Petazzoni mvneta_set_special_mcast_table(pp, -1); 990c5aff182SThomas Petazzoni mvneta_set_other_mcast_table(pp, -1); 991c5aff182SThomas Petazzoni 992c5aff182SThomas Petazzoni /* Set port interrupt enable register - default enable all */ 993c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_INTR_ENABLE, 994c5aff182SThomas Petazzoni (MVNETA_RXQ_INTR_ENABLE_ALL_MASK 995c5aff182SThomas Petazzoni | MVNETA_TXQ_INTR_ENABLE_ALL_MASK)); 996c5aff182SThomas Petazzoni } 997c5aff182SThomas Petazzoni 998c5aff182SThomas Petazzoni /* Set max sizes for tx queues */ 999c5aff182SThomas Petazzoni static void mvneta_txq_max_tx_size_set(struct mvneta_port *pp, int max_tx_size) 1000c5aff182SThomas Petazzoni 1001c5aff182SThomas Petazzoni { 1002c5aff182SThomas Petazzoni u32 val, size, mtu; 1003c5aff182SThomas Petazzoni int queue; 1004c5aff182SThomas Petazzoni 1005c5aff182SThomas Petazzoni mtu = max_tx_size * 8; 1006c5aff182SThomas Petazzoni if (mtu > MVNETA_TX_MTU_MAX) 1007c5aff182SThomas Petazzoni mtu = MVNETA_TX_MTU_MAX; 1008c5aff182SThomas Petazzoni 1009c5aff182SThomas Petazzoni /* Set MTU */ 1010c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_TX_MTU); 1011c5aff182SThomas Petazzoni val &= ~MVNETA_TX_MTU_MAX; 1012c5aff182SThomas Petazzoni val |= mtu; 1013c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_TX_MTU, val); 1014c5aff182SThomas Petazzoni 1015c5aff182SThomas Petazzoni /* TX token size and all TXQs token size must be larger that MTU */ 1016c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_TX_TOKEN_SIZE); 1017c5aff182SThomas Petazzoni 1018c5aff182SThomas Petazzoni size = val & MVNETA_TX_TOKEN_SIZE_MAX; 1019c5aff182SThomas Petazzoni if (size < mtu) { 1020c5aff182SThomas Petazzoni size = mtu; 1021c5aff182SThomas Petazzoni val &= ~MVNETA_TX_TOKEN_SIZE_MAX; 1022c5aff182SThomas Petazzoni val |= size; 1023c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_TX_TOKEN_SIZE, val); 1024c5aff182SThomas Petazzoni } 1025c5aff182SThomas Petazzoni for (queue = 0; queue < txq_number; queue++) { 1026c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_TXQ_TOKEN_SIZE_REG(queue)); 1027c5aff182SThomas Petazzoni 1028c5aff182SThomas Petazzoni size = val & MVNETA_TXQ_TOKEN_SIZE_MAX; 1029c5aff182SThomas Petazzoni if (size < mtu) { 1030c5aff182SThomas Petazzoni size = mtu; 1031c5aff182SThomas Petazzoni val &= ~MVNETA_TXQ_TOKEN_SIZE_MAX; 1032c5aff182SThomas Petazzoni val |= size; 1033c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_TXQ_TOKEN_SIZE_REG(queue), val); 1034c5aff182SThomas Petazzoni } 1035c5aff182SThomas Petazzoni } 1036c5aff182SThomas Petazzoni } 1037c5aff182SThomas Petazzoni 1038c5aff182SThomas Petazzoni /* Set unicast address */ 1039c5aff182SThomas Petazzoni static void mvneta_set_ucast_addr(struct mvneta_port *pp, u8 last_nibble, 1040c5aff182SThomas Petazzoni int queue) 1041c5aff182SThomas Petazzoni { 1042c5aff182SThomas Petazzoni unsigned int unicast_reg; 1043c5aff182SThomas Petazzoni unsigned int tbl_offset; 1044c5aff182SThomas Petazzoni unsigned int reg_offset; 1045c5aff182SThomas Petazzoni 1046c5aff182SThomas Petazzoni /* Locate the Unicast table entry */ 1047c5aff182SThomas Petazzoni last_nibble = (0xf & last_nibble); 1048c5aff182SThomas Petazzoni 1049c5aff182SThomas Petazzoni /* offset from unicast tbl base */ 1050c5aff182SThomas Petazzoni tbl_offset = (last_nibble / 4) * 4; 1051c5aff182SThomas Petazzoni 1052c5aff182SThomas Petazzoni /* offset within the above reg */ 1053c5aff182SThomas Petazzoni reg_offset = last_nibble % 4; 1054c5aff182SThomas Petazzoni 1055c5aff182SThomas Petazzoni unicast_reg = mvreg_read(pp, (MVNETA_DA_FILT_UCAST_BASE + tbl_offset)); 1056c5aff182SThomas Petazzoni 1057c5aff182SThomas Petazzoni if (queue == -1) { 1058c5aff182SThomas Petazzoni /* Clear accepts frame bit at specified unicast DA tbl entry */ 1059c5aff182SThomas Petazzoni unicast_reg &= ~(0xff << (8 * reg_offset)); 1060c5aff182SThomas Petazzoni } else { 1061c5aff182SThomas Petazzoni unicast_reg &= ~(0xff << (8 * reg_offset)); 1062c5aff182SThomas Petazzoni unicast_reg |= ((0x01 | (queue << 1)) << (8 * reg_offset)); 1063c5aff182SThomas Petazzoni } 1064c5aff182SThomas Petazzoni 1065c5aff182SThomas Petazzoni mvreg_write(pp, (MVNETA_DA_FILT_UCAST_BASE + tbl_offset), unicast_reg); 1066c5aff182SThomas Petazzoni } 1067c5aff182SThomas Petazzoni 1068c5aff182SThomas Petazzoni /* Set mac address */ 1069c5aff182SThomas Petazzoni static void mvneta_mac_addr_set(struct mvneta_port *pp, unsigned char *addr, 1070c5aff182SThomas Petazzoni int queue) 1071c5aff182SThomas Petazzoni { 1072c5aff182SThomas Petazzoni unsigned int mac_h; 1073c5aff182SThomas Petazzoni unsigned int mac_l; 1074c5aff182SThomas Petazzoni 1075c5aff182SThomas Petazzoni if (queue != -1) { 1076c5aff182SThomas Petazzoni mac_l = (addr[4] << 8) | (addr[5]); 1077c5aff182SThomas Petazzoni mac_h = (addr[0] << 24) | (addr[1] << 16) | 1078c5aff182SThomas Petazzoni (addr[2] << 8) | (addr[3] << 0); 1079c5aff182SThomas Petazzoni 1080c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_MAC_ADDR_LOW, mac_l); 1081c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_MAC_ADDR_HIGH, mac_h); 1082c5aff182SThomas Petazzoni } 1083c5aff182SThomas Petazzoni 1084c5aff182SThomas Petazzoni /* Accept frames of this address */ 1085c5aff182SThomas Petazzoni mvneta_set_ucast_addr(pp, addr[5], queue); 1086c5aff182SThomas Petazzoni } 1087c5aff182SThomas Petazzoni 10886a20c175SThomas Petazzoni /* Set the number of packets that will be received before RX interrupt 10896a20c175SThomas Petazzoni * will be generated by HW. 1090c5aff182SThomas Petazzoni */ 1091c5aff182SThomas Petazzoni static void mvneta_rx_pkts_coal_set(struct mvneta_port *pp, 1092c5aff182SThomas Petazzoni struct mvneta_rx_queue *rxq, u32 value) 1093c5aff182SThomas Petazzoni { 1094c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_RXQ_THRESHOLD_REG(rxq->id), 1095c5aff182SThomas Petazzoni value | MVNETA_RXQ_NON_OCCUPIED(0)); 1096c5aff182SThomas Petazzoni rxq->pkts_coal = value; 1097c5aff182SThomas Petazzoni } 1098c5aff182SThomas Petazzoni 10996a20c175SThomas Petazzoni /* Set the time delay in usec before RX interrupt will be generated by 11006a20c175SThomas Petazzoni * HW. 1101c5aff182SThomas Petazzoni */ 1102c5aff182SThomas Petazzoni static void mvneta_rx_time_coal_set(struct mvneta_port *pp, 1103c5aff182SThomas Petazzoni struct mvneta_rx_queue *rxq, u32 value) 1104c5aff182SThomas Petazzoni { 1105189dd626SThomas Petazzoni u32 val; 1106189dd626SThomas Petazzoni unsigned long clk_rate; 1107189dd626SThomas Petazzoni 1108189dd626SThomas Petazzoni clk_rate = clk_get_rate(pp->clk); 1109189dd626SThomas Petazzoni val = (clk_rate / 1000000) * value; 1110c5aff182SThomas Petazzoni 1111c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_RXQ_TIME_COAL_REG(rxq->id), val); 1112c5aff182SThomas Petazzoni rxq->time_coal = value; 1113c5aff182SThomas Petazzoni } 1114c5aff182SThomas Petazzoni 1115c5aff182SThomas Petazzoni /* Set threshold for TX_DONE pkts coalescing */ 1116c5aff182SThomas Petazzoni static void mvneta_tx_done_pkts_coal_set(struct mvneta_port *pp, 1117c5aff182SThomas Petazzoni struct mvneta_tx_queue *txq, u32 value) 1118c5aff182SThomas Petazzoni { 1119c5aff182SThomas Petazzoni u32 val; 1120c5aff182SThomas Petazzoni 1121c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_TXQ_SIZE_REG(txq->id)); 1122c5aff182SThomas Petazzoni 1123c5aff182SThomas Petazzoni val &= ~MVNETA_TXQ_SENT_THRESH_ALL_MASK; 1124c5aff182SThomas Petazzoni val |= MVNETA_TXQ_SENT_THRESH_MASK(value); 1125c5aff182SThomas Petazzoni 1126c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_TXQ_SIZE_REG(txq->id), val); 1127c5aff182SThomas Petazzoni 1128c5aff182SThomas Petazzoni txq->done_pkts_coal = value; 1129c5aff182SThomas Petazzoni } 1130c5aff182SThomas Petazzoni 1131c5aff182SThomas Petazzoni /* Handle rx descriptor fill by setting buf_cookie and buf_phys_addr */ 1132c5aff182SThomas Petazzoni static void mvneta_rx_desc_fill(struct mvneta_rx_desc *rx_desc, 1133c5aff182SThomas Petazzoni u32 phys_addr, u32 cookie) 1134c5aff182SThomas Petazzoni { 1135c5aff182SThomas Petazzoni rx_desc->buf_cookie = cookie; 1136c5aff182SThomas Petazzoni rx_desc->buf_phys_addr = phys_addr; 1137c5aff182SThomas Petazzoni } 1138c5aff182SThomas Petazzoni 1139c5aff182SThomas Petazzoni /* Decrement sent descriptors counter */ 1140c5aff182SThomas Petazzoni static void mvneta_txq_sent_desc_dec(struct mvneta_port *pp, 1141c5aff182SThomas Petazzoni struct mvneta_tx_queue *txq, 1142c5aff182SThomas Petazzoni int sent_desc) 1143c5aff182SThomas Petazzoni { 1144c5aff182SThomas Petazzoni u32 val; 1145c5aff182SThomas Petazzoni 1146c5aff182SThomas Petazzoni /* Only 255 TX descriptors can be updated at once */ 1147c5aff182SThomas Petazzoni while (sent_desc > 0xff) { 1148c5aff182SThomas Petazzoni val = 0xff << MVNETA_TXQ_DEC_SENT_SHIFT; 1149c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val); 1150c5aff182SThomas Petazzoni sent_desc = sent_desc - 0xff; 1151c5aff182SThomas Petazzoni } 1152c5aff182SThomas Petazzoni 1153c5aff182SThomas Petazzoni val = sent_desc << MVNETA_TXQ_DEC_SENT_SHIFT; 1154c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val); 1155c5aff182SThomas Petazzoni } 1156c5aff182SThomas Petazzoni 1157c5aff182SThomas Petazzoni /* Get number of TX descriptors already sent by HW */ 1158c5aff182SThomas Petazzoni static int mvneta_txq_sent_desc_num_get(struct mvneta_port *pp, 1159c5aff182SThomas Petazzoni struct mvneta_tx_queue *txq) 1160c5aff182SThomas Petazzoni { 1161c5aff182SThomas Petazzoni u32 val; 1162c5aff182SThomas Petazzoni int sent_desc; 1163c5aff182SThomas Petazzoni 1164c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_TXQ_STATUS_REG(txq->id)); 1165c5aff182SThomas Petazzoni sent_desc = (val & MVNETA_TXQ_SENT_DESC_MASK) >> 1166c5aff182SThomas Petazzoni MVNETA_TXQ_SENT_DESC_SHIFT; 1167c5aff182SThomas Petazzoni 1168c5aff182SThomas Petazzoni return sent_desc; 1169c5aff182SThomas Petazzoni } 1170c5aff182SThomas Petazzoni 11716a20c175SThomas Petazzoni /* Get number of sent descriptors and decrement counter. 1172c5aff182SThomas Petazzoni * The number of sent descriptors is returned. 1173c5aff182SThomas Petazzoni */ 1174c5aff182SThomas Petazzoni static int mvneta_txq_sent_desc_proc(struct mvneta_port *pp, 1175c5aff182SThomas Petazzoni struct mvneta_tx_queue *txq) 1176c5aff182SThomas Petazzoni { 1177c5aff182SThomas Petazzoni int sent_desc; 1178c5aff182SThomas Petazzoni 1179c5aff182SThomas Petazzoni /* Get number of sent descriptors */ 1180c5aff182SThomas Petazzoni sent_desc = mvneta_txq_sent_desc_num_get(pp, txq); 1181c5aff182SThomas Petazzoni 1182c5aff182SThomas Petazzoni /* Decrement sent descriptors counter */ 1183c5aff182SThomas Petazzoni if (sent_desc) 1184c5aff182SThomas Petazzoni mvneta_txq_sent_desc_dec(pp, txq, sent_desc); 1185c5aff182SThomas Petazzoni 1186c5aff182SThomas Petazzoni return sent_desc; 1187c5aff182SThomas Petazzoni } 1188c5aff182SThomas Petazzoni 1189c5aff182SThomas Petazzoni /* Set TXQ descriptors fields relevant for CSUM calculation */ 1190c5aff182SThomas Petazzoni static u32 mvneta_txq_desc_csum(int l3_offs, int l3_proto, 1191c5aff182SThomas Petazzoni int ip_hdr_len, int l4_proto) 1192c5aff182SThomas Petazzoni { 1193c5aff182SThomas Petazzoni u32 command; 1194c5aff182SThomas Petazzoni 1195c5aff182SThomas Petazzoni /* Fields: L3_offset, IP_hdrlen, L3_type, G_IPv4_chk, 11966a20c175SThomas Petazzoni * G_L4_chk, L4_type; required only for checksum 11976a20c175SThomas Petazzoni * calculation 11986a20c175SThomas Petazzoni */ 1199c5aff182SThomas Petazzoni command = l3_offs << MVNETA_TX_L3_OFF_SHIFT; 1200c5aff182SThomas Petazzoni command |= ip_hdr_len << MVNETA_TX_IP_HLEN_SHIFT; 1201c5aff182SThomas Petazzoni 1202c5aff182SThomas Petazzoni if (l3_proto == swab16(ETH_P_IP)) 1203c5aff182SThomas Petazzoni command |= MVNETA_TXD_IP_CSUM; 1204c5aff182SThomas Petazzoni else 1205c5aff182SThomas Petazzoni command |= MVNETA_TX_L3_IP6; 1206c5aff182SThomas Petazzoni 1207c5aff182SThomas Petazzoni if (l4_proto == IPPROTO_TCP) 1208c5aff182SThomas Petazzoni command |= MVNETA_TX_L4_CSUM_FULL; 1209c5aff182SThomas Petazzoni else if (l4_proto == IPPROTO_UDP) 1210c5aff182SThomas Petazzoni command |= MVNETA_TX_L4_UDP | MVNETA_TX_L4_CSUM_FULL; 1211c5aff182SThomas Petazzoni else 1212c5aff182SThomas Petazzoni command |= MVNETA_TX_L4_CSUM_NOT; 1213c5aff182SThomas Petazzoni 1214c5aff182SThomas Petazzoni return command; 1215c5aff182SThomas Petazzoni } 1216c5aff182SThomas Petazzoni 1217c5aff182SThomas Petazzoni 1218c5aff182SThomas Petazzoni /* Display more error info */ 1219c5aff182SThomas Petazzoni static void mvneta_rx_error(struct mvneta_port *pp, 1220c5aff182SThomas Petazzoni struct mvneta_rx_desc *rx_desc) 1221c5aff182SThomas Petazzoni { 1222c5aff182SThomas Petazzoni u32 status = rx_desc->status; 1223c5aff182SThomas Petazzoni 12245428213cSwilly tarreau if (!mvneta_rxq_desc_is_first_last(status)) { 1225c5aff182SThomas Petazzoni netdev_err(pp->dev, 1226c5aff182SThomas Petazzoni "bad rx status %08x (buffer oversize), size=%d\n", 12275428213cSwilly tarreau status, rx_desc->data_size); 1228c5aff182SThomas Petazzoni return; 1229c5aff182SThomas Petazzoni } 1230c5aff182SThomas Petazzoni 1231c5aff182SThomas Petazzoni switch (status & MVNETA_RXD_ERR_CODE_MASK) { 1232c5aff182SThomas Petazzoni case MVNETA_RXD_ERR_CRC: 1233c5aff182SThomas Petazzoni netdev_err(pp->dev, "bad rx status %08x (crc error), size=%d\n", 1234c5aff182SThomas Petazzoni status, rx_desc->data_size); 1235c5aff182SThomas Petazzoni break; 1236c5aff182SThomas Petazzoni case MVNETA_RXD_ERR_OVERRUN: 1237c5aff182SThomas Petazzoni netdev_err(pp->dev, "bad rx status %08x (overrun error), size=%d\n", 1238c5aff182SThomas Petazzoni status, rx_desc->data_size); 1239c5aff182SThomas Petazzoni break; 1240c5aff182SThomas Petazzoni case MVNETA_RXD_ERR_LEN: 1241c5aff182SThomas Petazzoni netdev_err(pp->dev, "bad rx status %08x (max frame length error), size=%d\n", 1242c5aff182SThomas Petazzoni status, rx_desc->data_size); 1243c5aff182SThomas Petazzoni break; 1244c5aff182SThomas Petazzoni case MVNETA_RXD_ERR_RESOURCE: 1245c5aff182SThomas Petazzoni netdev_err(pp->dev, "bad rx status %08x (resource error), size=%d\n", 1246c5aff182SThomas Petazzoni status, rx_desc->data_size); 1247c5aff182SThomas Petazzoni break; 1248c5aff182SThomas Petazzoni } 1249c5aff182SThomas Petazzoni } 1250c5aff182SThomas Petazzoni 12515428213cSwilly tarreau /* Handle RX checksum offload based on the descriptor's status */ 12525428213cSwilly tarreau static void mvneta_rx_csum(struct mvneta_port *pp, u32 status, 1253c5aff182SThomas Petazzoni struct sk_buff *skb) 1254c5aff182SThomas Petazzoni { 12555428213cSwilly tarreau if ((status & MVNETA_RXD_L3_IP4) && 12565428213cSwilly tarreau (status & MVNETA_RXD_L4_CSUM_OK)) { 1257c5aff182SThomas Petazzoni skb->csum = 0; 1258c5aff182SThomas Petazzoni skb->ip_summed = CHECKSUM_UNNECESSARY; 1259c5aff182SThomas Petazzoni return; 1260c5aff182SThomas Petazzoni } 1261c5aff182SThomas Petazzoni 1262c5aff182SThomas Petazzoni skb->ip_summed = CHECKSUM_NONE; 1263c5aff182SThomas Petazzoni } 1264c5aff182SThomas Petazzoni 12656c498974Swilly tarreau /* Return tx queue pointer (find last set bit) according to <cause> returned 12666c498974Swilly tarreau * form tx_done reg. <cause> must not be null. The return value is always a 12676c498974Swilly tarreau * valid queue for matching the first one found in <cause>. 12686c498974Swilly tarreau */ 1269c5aff182SThomas Petazzoni static struct mvneta_tx_queue *mvneta_tx_done_policy(struct mvneta_port *pp, 1270c5aff182SThomas Petazzoni u32 cause) 1271c5aff182SThomas Petazzoni { 1272c5aff182SThomas Petazzoni int queue = fls(cause) - 1; 1273c5aff182SThomas Petazzoni 12746c498974Swilly tarreau return &pp->txqs[queue]; 1275c5aff182SThomas Petazzoni } 1276c5aff182SThomas Petazzoni 1277c5aff182SThomas Petazzoni /* Free tx queue skbuffs */ 1278c5aff182SThomas Petazzoni static void mvneta_txq_bufs_free(struct mvneta_port *pp, 1279c5aff182SThomas Petazzoni struct mvneta_tx_queue *txq, int num) 1280c5aff182SThomas Petazzoni { 1281c5aff182SThomas Petazzoni int i; 1282c5aff182SThomas Petazzoni 1283c5aff182SThomas Petazzoni for (i = 0; i < num; i++) { 1284c5aff182SThomas Petazzoni struct mvneta_tx_desc *tx_desc = txq->descs + 1285c5aff182SThomas Petazzoni txq->txq_get_index; 1286c5aff182SThomas Petazzoni struct sk_buff *skb = txq->tx_skb[txq->txq_get_index]; 1287c5aff182SThomas Petazzoni 1288c5aff182SThomas Petazzoni mvneta_txq_inc_get(txq); 1289c5aff182SThomas Petazzoni 1290c5aff182SThomas Petazzoni if (!skb) 1291c5aff182SThomas Petazzoni continue; 1292c5aff182SThomas Petazzoni 1293c5aff182SThomas Petazzoni dma_unmap_single(pp->dev->dev.parent, tx_desc->buf_phys_addr, 1294c5aff182SThomas Petazzoni tx_desc->data_size, DMA_TO_DEVICE); 1295c5aff182SThomas Petazzoni dev_kfree_skb_any(skb); 1296c5aff182SThomas Petazzoni } 1297c5aff182SThomas Petazzoni } 1298c5aff182SThomas Petazzoni 1299c5aff182SThomas Petazzoni /* Handle end of transmission */ 1300cd713199SArnaud Ebalard static void mvneta_txq_done(struct mvneta_port *pp, 1301c5aff182SThomas Petazzoni struct mvneta_tx_queue *txq) 1302c5aff182SThomas Petazzoni { 1303c5aff182SThomas Petazzoni struct netdev_queue *nq = netdev_get_tx_queue(pp->dev, txq->id); 1304c5aff182SThomas Petazzoni int tx_done; 1305c5aff182SThomas Petazzoni 1306c5aff182SThomas Petazzoni tx_done = mvneta_txq_sent_desc_proc(pp, txq); 1307cd713199SArnaud Ebalard if (!tx_done) 1308cd713199SArnaud Ebalard return; 1309cd713199SArnaud Ebalard 1310c5aff182SThomas Petazzoni mvneta_txq_bufs_free(pp, txq, tx_done); 1311c5aff182SThomas Petazzoni 1312c5aff182SThomas Petazzoni txq->count -= tx_done; 1313c5aff182SThomas Petazzoni 1314c5aff182SThomas Petazzoni if (netif_tx_queue_stopped(nq)) { 1315c5aff182SThomas Petazzoni if (txq->size - txq->count >= MAX_SKB_FRAGS + 1) 1316c5aff182SThomas Petazzoni netif_tx_wake_queue(nq); 1317c5aff182SThomas Petazzoni } 1318c5aff182SThomas Petazzoni } 1319c5aff182SThomas Petazzoni 13208ec2cd48Swilly tarreau static void *mvneta_frag_alloc(const struct mvneta_port *pp) 13218ec2cd48Swilly tarreau { 13228ec2cd48Swilly tarreau if (likely(pp->frag_size <= PAGE_SIZE)) 13238ec2cd48Swilly tarreau return netdev_alloc_frag(pp->frag_size); 13248ec2cd48Swilly tarreau else 13258ec2cd48Swilly tarreau return kmalloc(pp->frag_size, GFP_ATOMIC); 13268ec2cd48Swilly tarreau } 13278ec2cd48Swilly tarreau 13288ec2cd48Swilly tarreau static void mvneta_frag_free(const struct mvneta_port *pp, void *data) 13298ec2cd48Swilly tarreau { 13308ec2cd48Swilly tarreau if (likely(pp->frag_size <= PAGE_SIZE)) 13318ec2cd48Swilly tarreau put_page(virt_to_head_page(data)); 13328ec2cd48Swilly tarreau else 13338ec2cd48Swilly tarreau kfree(data); 13348ec2cd48Swilly tarreau } 13358ec2cd48Swilly tarreau 1336c5aff182SThomas Petazzoni /* Refill processing */ 1337c5aff182SThomas Petazzoni static int mvneta_rx_refill(struct mvneta_port *pp, 1338c5aff182SThomas Petazzoni struct mvneta_rx_desc *rx_desc) 1339c5aff182SThomas Petazzoni 1340c5aff182SThomas Petazzoni { 1341c5aff182SThomas Petazzoni dma_addr_t phys_addr; 13428ec2cd48Swilly tarreau void *data; 1343c5aff182SThomas Petazzoni 13448ec2cd48Swilly tarreau data = mvneta_frag_alloc(pp); 13458ec2cd48Swilly tarreau if (!data) 1346c5aff182SThomas Petazzoni return -ENOMEM; 1347c5aff182SThomas Petazzoni 13488ec2cd48Swilly tarreau phys_addr = dma_map_single(pp->dev->dev.parent, data, 1349c5aff182SThomas Petazzoni MVNETA_RX_BUF_SIZE(pp->pkt_size), 1350c5aff182SThomas Petazzoni DMA_FROM_DEVICE); 1351c5aff182SThomas Petazzoni if (unlikely(dma_mapping_error(pp->dev->dev.parent, phys_addr))) { 13528ec2cd48Swilly tarreau mvneta_frag_free(pp, data); 1353c5aff182SThomas Petazzoni return -ENOMEM; 1354c5aff182SThomas Petazzoni } 1355c5aff182SThomas Petazzoni 13568ec2cd48Swilly tarreau mvneta_rx_desc_fill(rx_desc, phys_addr, (u32)data); 1357c5aff182SThomas Petazzoni return 0; 1358c5aff182SThomas Petazzoni } 1359c5aff182SThomas Petazzoni 1360c5aff182SThomas Petazzoni /* Handle tx checksum */ 1361c5aff182SThomas Petazzoni static u32 mvneta_skb_tx_csum(struct mvneta_port *pp, struct sk_buff *skb) 1362c5aff182SThomas Petazzoni { 1363c5aff182SThomas Petazzoni if (skb->ip_summed == CHECKSUM_PARTIAL) { 1364c5aff182SThomas Petazzoni int ip_hdr_len = 0; 1365c5aff182SThomas Petazzoni u8 l4_proto; 1366c5aff182SThomas Petazzoni 1367c5aff182SThomas Petazzoni if (skb->protocol == htons(ETH_P_IP)) { 1368c5aff182SThomas Petazzoni struct iphdr *ip4h = ip_hdr(skb); 1369c5aff182SThomas Petazzoni 1370c5aff182SThomas Petazzoni /* Calculate IPv4 checksum and L4 checksum */ 1371c5aff182SThomas Petazzoni ip_hdr_len = ip4h->ihl; 1372c5aff182SThomas Petazzoni l4_proto = ip4h->protocol; 1373c5aff182SThomas Petazzoni } else if (skb->protocol == htons(ETH_P_IPV6)) { 1374c5aff182SThomas Petazzoni struct ipv6hdr *ip6h = ipv6_hdr(skb); 1375c5aff182SThomas Petazzoni 1376c5aff182SThomas Petazzoni /* Read l4_protocol from one of IPv6 extra headers */ 1377c5aff182SThomas Petazzoni if (skb_network_header_len(skb) > 0) 1378c5aff182SThomas Petazzoni ip_hdr_len = (skb_network_header_len(skb) >> 2); 1379c5aff182SThomas Petazzoni l4_proto = ip6h->nexthdr; 1380c5aff182SThomas Petazzoni } else 1381c5aff182SThomas Petazzoni return MVNETA_TX_L4_CSUM_NOT; 1382c5aff182SThomas Petazzoni 1383c5aff182SThomas Petazzoni return mvneta_txq_desc_csum(skb_network_offset(skb), 1384c5aff182SThomas Petazzoni skb->protocol, ip_hdr_len, l4_proto); 1385c5aff182SThomas Petazzoni } 1386c5aff182SThomas Petazzoni 1387c5aff182SThomas Petazzoni return MVNETA_TX_L4_CSUM_NOT; 1388c5aff182SThomas Petazzoni } 1389c5aff182SThomas Petazzoni 13906a20c175SThomas Petazzoni /* Returns rx queue pointer (find last set bit) according to causeRxTx 1391c5aff182SThomas Petazzoni * value 1392c5aff182SThomas Petazzoni */ 1393c5aff182SThomas Petazzoni static struct mvneta_rx_queue *mvneta_rx_policy(struct mvneta_port *pp, 1394c5aff182SThomas Petazzoni u32 cause) 1395c5aff182SThomas Petazzoni { 1396c5aff182SThomas Petazzoni int queue = fls(cause >> 8) - 1; 1397c5aff182SThomas Petazzoni 1398c5aff182SThomas Petazzoni return (queue < 0 || queue >= rxq_number) ? NULL : &pp->rxqs[queue]; 1399c5aff182SThomas Petazzoni } 1400c5aff182SThomas Petazzoni 1401c5aff182SThomas Petazzoni /* Drop packets received by the RXQ and free buffers */ 1402c5aff182SThomas Petazzoni static void mvneta_rxq_drop_pkts(struct mvneta_port *pp, 1403c5aff182SThomas Petazzoni struct mvneta_rx_queue *rxq) 1404c5aff182SThomas Petazzoni { 1405c5aff182SThomas Petazzoni int rx_done, i; 1406c5aff182SThomas Petazzoni 1407c5aff182SThomas Petazzoni rx_done = mvneta_rxq_busy_desc_num_get(pp, rxq); 1408c5aff182SThomas Petazzoni for (i = 0; i < rxq->size; i++) { 1409c5aff182SThomas Petazzoni struct mvneta_rx_desc *rx_desc = rxq->descs + i; 14108ec2cd48Swilly tarreau void *data = (void *)rx_desc->buf_cookie; 1411c5aff182SThomas Petazzoni 14128ec2cd48Swilly tarreau mvneta_frag_free(pp, data); 1413c5aff182SThomas Petazzoni dma_unmap_single(pp->dev->dev.parent, rx_desc->buf_phys_addr, 1414a328f3a0SEzequiel Garcia MVNETA_RX_BUF_SIZE(pp->pkt_size), DMA_FROM_DEVICE); 1415c5aff182SThomas Petazzoni } 1416c5aff182SThomas Petazzoni 1417c5aff182SThomas Petazzoni if (rx_done) 1418c5aff182SThomas Petazzoni mvneta_rxq_desc_num_update(pp, rxq, rx_done, rx_done); 1419c5aff182SThomas Petazzoni } 1420c5aff182SThomas Petazzoni 1421c5aff182SThomas Petazzoni /* Main rx processing */ 1422c5aff182SThomas Petazzoni static int mvneta_rx(struct mvneta_port *pp, int rx_todo, 1423c5aff182SThomas Petazzoni struct mvneta_rx_queue *rxq) 1424c5aff182SThomas Petazzoni { 1425c5aff182SThomas Petazzoni struct net_device *dev = pp->dev; 1426c5aff182SThomas Petazzoni int rx_done, rx_filled; 1427dc4277ddSwilly tarreau u32 rcvd_pkts = 0; 1428dc4277ddSwilly tarreau u32 rcvd_bytes = 0; 1429c5aff182SThomas Petazzoni 1430c5aff182SThomas Petazzoni /* Get number of received packets */ 1431c5aff182SThomas Petazzoni rx_done = mvneta_rxq_busy_desc_num_get(pp, rxq); 1432c5aff182SThomas Petazzoni 1433c5aff182SThomas Petazzoni if (rx_todo > rx_done) 1434c5aff182SThomas Petazzoni rx_todo = rx_done; 1435c5aff182SThomas Petazzoni 1436c5aff182SThomas Petazzoni rx_done = 0; 1437c5aff182SThomas Petazzoni rx_filled = 0; 1438c5aff182SThomas Petazzoni 1439c5aff182SThomas Petazzoni /* Fairness NAPI loop */ 1440c5aff182SThomas Petazzoni while (rx_done < rx_todo) { 1441c5aff182SThomas Petazzoni struct mvneta_rx_desc *rx_desc = mvneta_rxq_next_desc_get(rxq); 1442c5aff182SThomas Petazzoni struct sk_buff *skb; 14438ec2cd48Swilly tarreau unsigned char *data; 1444c5aff182SThomas Petazzoni u32 rx_status; 1445c5aff182SThomas Petazzoni int rx_bytes, err; 1446c5aff182SThomas Petazzoni 1447c5aff182SThomas Petazzoni rx_done++; 1448c5aff182SThomas Petazzoni rx_filled++; 1449c5aff182SThomas Petazzoni rx_status = rx_desc->status; 1450f19fadfcSwilly tarreau rx_bytes = rx_desc->data_size - (ETH_FCS_LEN + MVNETA_MH_SIZE); 14518ec2cd48Swilly tarreau data = (unsigned char *)rx_desc->buf_cookie; 1452c5aff182SThomas Petazzoni 14535428213cSwilly tarreau if (!mvneta_rxq_desc_is_first_last(rx_status) || 1454f19fadfcSwilly tarreau (rx_status & MVNETA_RXD_ERR_SUMMARY)) { 1455f19fadfcSwilly tarreau err_drop_frame: 1456c5aff182SThomas Petazzoni dev->stats.rx_errors++; 1457c5aff182SThomas Petazzoni mvneta_rx_error(pp, rx_desc); 14588ec2cd48Swilly tarreau /* leave the descriptor untouched */ 1459c5aff182SThomas Petazzoni continue; 1460c5aff182SThomas Petazzoni } 1461c5aff182SThomas Petazzoni 1462f19fadfcSwilly tarreau if (rx_bytes <= rx_copybreak) { 1463f19fadfcSwilly tarreau /* better copy a small frame and not unmap the DMA region */ 1464f19fadfcSwilly tarreau skb = netdev_alloc_skb_ip_align(dev, rx_bytes); 1465f19fadfcSwilly tarreau if (unlikely(!skb)) 1466f19fadfcSwilly tarreau goto err_drop_frame; 1467f19fadfcSwilly tarreau 1468f19fadfcSwilly tarreau dma_sync_single_range_for_cpu(dev->dev.parent, 1469f19fadfcSwilly tarreau rx_desc->buf_phys_addr, 1470f19fadfcSwilly tarreau MVNETA_MH_SIZE + NET_SKB_PAD, 1471f19fadfcSwilly tarreau rx_bytes, 1472f19fadfcSwilly tarreau DMA_FROM_DEVICE); 1473f19fadfcSwilly tarreau memcpy(skb_put(skb, rx_bytes), 1474f19fadfcSwilly tarreau data + MVNETA_MH_SIZE + NET_SKB_PAD, 1475f19fadfcSwilly tarreau rx_bytes); 1476f19fadfcSwilly tarreau 1477f19fadfcSwilly tarreau skb->protocol = eth_type_trans(skb, dev); 1478f19fadfcSwilly tarreau mvneta_rx_csum(pp, rx_status, skb); 1479f19fadfcSwilly tarreau napi_gro_receive(&pp->napi, skb); 1480f19fadfcSwilly tarreau 1481f19fadfcSwilly tarreau rcvd_pkts++; 1482f19fadfcSwilly tarreau rcvd_bytes += rx_bytes; 1483f19fadfcSwilly tarreau 1484f19fadfcSwilly tarreau /* leave the descriptor and buffer untouched */ 1485f19fadfcSwilly tarreau continue; 1486f19fadfcSwilly tarreau } 1487f19fadfcSwilly tarreau 1488f19fadfcSwilly tarreau skb = build_skb(data, pp->frag_size > PAGE_SIZE ? 0 : pp->frag_size); 1489f19fadfcSwilly tarreau if (!skb) 1490f19fadfcSwilly tarreau goto err_drop_frame; 1491f19fadfcSwilly tarreau 1492f19fadfcSwilly tarreau dma_unmap_single(dev->dev.parent, rx_desc->buf_phys_addr, 1493a328f3a0SEzequiel Garcia MVNETA_RX_BUF_SIZE(pp->pkt_size), DMA_FROM_DEVICE); 1494c5aff182SThomas Petazzoni 1495dc4277ddSwilly tarreau rcvd_pkts++; 1496dc4277ddSwilly tarreau rcvd_bytes += rx_bytes; 1497c5aff182SThomas Petazzoni 1498c5aff182SThomas Petazzoni /* Linux processing */ 14998ec2cd48Swilly tarreau skb_reserve(skb, MVNETA_MH_SIZE + NET_SKB_PAD); 1500c5aff182SThomas Petazzoni skb_put(skb, rx_bytes); 1501c5aff182SThomas Petazzoni 1502c5aff182SThomas Petazzoni skb->protocol = eth_type_trans(skb, dev); 1503c5aff182SThomas Petazzoni 15045428213cSwilly tarreau mvneta_rx_csum(pp, rx_status, skb); 1505c5aff182SThomas Petazzoni 1506c5aff182SThomas Petazzoni napi_gro_receive(&pp->napi, skb); 1507c5aff182SThomas Petazzoni 1508c5aff182SThomas Petazzoni /* Refill processing */ 1509c5aff182SThomas Petazzoni err = mvneta_rx_refill(pp, rx_desc); 1510c5aff182SThomas Petazzoni if (err) { 1511f19fadfcSwilly tarreau netdev_err(dev, "Linux processing - Can't refill\n"); 1512c5aff182SThomas Petazzoni rxq->missed++; 1513c5aff182SThomas Petazzoni rx_filled--; 1514c5aff182SThomas Petazzoni } 1515c5aff182SThomas Petazzoni } 1516c5aff182SThomas Petazzoni 1517dc4277ddSwilly tarreau if (rcvd_pkts) { 151874c41b04Swilly tarreau struct mvneta_pcpu_stats *stats = this_cpu_ptr(pp->stats); 151974c41b04Swilly tarreau 152074c41b04Swilly tarreau u64_stats_update_begin(&stats->syncp); 152174c41b04Swilly tarreau stats->rx_packets += rcvd_pkts; 152274c41b04Swilly tarreau stats->rx_bytes += rcvd_bytes; 152374c41b04Swilly tarreau u64_stats_update_end(&stats->syncp); 1524dc4277ddSwilly tarreau } 1525dc4277ddSwilly tarreau 1526c5aff182SThomas Petazzoni /* Update rxq management counters */ 1527c5aff182SThomas Petazzoni mvneta_rxq_desc_num_update(pp, rxq, rx_done, rx_filled); 1528c5aff182SThomas Petazzoni 1529c5aff182SThomas Petazzoni return rx_done; 1530c5aff182SThomas Petazzoni } 1531c5aff182SThomas Petazzoni 15322adb719dSEzequiel Garcia static inline void 15332adb719dSEzequiel Garcia mvneta_tso_put_hdr(struct sk_buff *skb, 15342adb719dSEzequiel Garcia struct mvneta_port *pp, struct mvneta_tx_queue *txq) 15352adb719dSEzequiel Garcia { 15362adb719dSEzequiel Garcia struct mvneta_tx_desc *tx_desc; 15372adb719dSEzequiel Garcia int hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb); 15382adb719dSEzequiel Garcia 15392adb719dSEzequiel Garcia txq->tx_skb[txq->txq_put_index] = NULL; 15402adb719dSEzequiel Garcia tx_desc = mvneta_txq_next_desc_get(txq); 15412adb719dSEzequiel Garcia tx_desc->data_size = hdr_len; 15422adb719dSEzequiel Garcia tx_desc->command = mvneta_skb_tx_csum(pp, skb); 15432adb719dSEzequiel Garcia tx_desc->command |= MVNETA_TXD_F_DESC; 15442adb719dSEzequiel Garcia tx_desc->buf_phys_addr = txq->tso_hdrs_phys + 15452adb719dSEzequiel Garcia txq->txq_put_index * TSO_HEADER_SIZE; 15462adb719dSEzequiel Garcia mvneta_txq_inc_put(txq); 15472adb719dSEzequiel Garcia } 15482adb719dSEzequiel Garcia 15492adb719dSEzequiel Garcia static inline int 15502adb719dSEzequiel Garcia mvneta_tso_put_data(struct net_device *dev, struct mvneta_tx_queue *txq, 15512adb719dSEzequiel Garcia struct sk_buff *skb, char *data, int size, 15522adb719dSEzequiel Garcia bool last_tcp, bool is_last) 15532adb719dSEzequiel Garcia { 15542adb719dSEzequiel Garcia struct mvneta_tx_desc *tx_desc; 15552adb719dSEzequiel Garcia 15562adb719dSEzequiel Garcia tx_desc = mvneta_txq_next_desc_get(txq); 15572adb719dSEzequiel Garcia tx_desc->data_size = size; 15582adb719dSEzequiel Garcia tx_desc->buf_phys_addr = dma_map_single(dev->dev.parent, data, 15592adb719dSEzequiel Garcia size, DMA_TO_DEVICE); 15602adb719dSEzequiel Garcia if (unlikely(dma_mapping_error(dev->dev.parent, 15612adb719dSEzequiel Garcia tx_desc->buf_phys_addr))) { 15622adb719dSEzequiel Garcia mvneta_txq_desc_put(txq); 15632adb719dSEzequiel Garcia return -ENOMEM; 15642adb719dSEzequiel Garcia } 15652adb719dSEzequiel Garcia 15662adb719dSEzequiel Garcia tx_desc->command = 0; 15672adb719dSEzequiel Garcia txq->tx_skb[txq->txq_put_index] = NULL; 15682adb719dSEzequiel Garcia 15692adb719dSEzequiel Garcia if (last_tcp) { 15702adb719dSEzequiel Garcia /* last descriptor in the TCP packet */ 15712adb719dSEzequiel Garcia tx_desc->command = MVNETA_TXD_L_DESC; 15722adb719dSEzequiel Garcia 15732adb719dSEzequiel Garcia /* last descriptor in SKB */ 15742adb719dSEzequiel Garcia if (is_last) 15752adb719dSEzequiel Garcia txq->tx_skb[txq->txq_put_index] = skb; 15762adb719dSEzequiel Garcia } 15772adb719dSEzequiel Garcia mvneta_txq_inc_put(txq); 15782adb719dSEzequiel Garcia return 0; 15792adb719dSEzequiel Garcia } 15802adb719dSEzequiel Garcia 15812adb719dSEzequiel Garcia static int mvneta_tx_tso(struct sk_buff *skb, struct net_device *dev, 15822adb719dSEzequiel Garcia struct mvneta_tx_queue *txq) 15832adb719dSEzequiel Garcia { 15842adb719dSEzequiel Garcia int total_len, data_left; 15852adb719dSEzequiel Garcia int desc_count = 0; 15862adb719dSEzequiel Garcia struct mvneta_port *pp = netdev_priv(dev); 15872adb719dSEzequiel Garcia struct tso_t tso; 15882adb719dSEzequiel Garcia int hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb); 15892adb719dSEzequiel Garcia int i; 15902adb719dSEzequiel Garcia 15912adb719dSEzequiel Garcia /* Count needed descriptors */ 15922adb719dSEzequiel Garcia if ((txq->count + tso_count_descs(skb)) >= txq->size) 15932adb719dSEzequiel Garcia return 0; 15942adb719dSEzequiel Garcia 15952adb719dSEzequiel Garcia if (skb_headlen(skb) < (skb_transport_offset(skb) + tcp_hdrlen(skb))) { 15962adb719dSEzequiel Garcia pr_info("*** Is this even possible???!?!?\n"); 15972adb719dSEzequiel Garcia return 0; 15982adb719dSEzequiel Garcia } 15992adb719dSEzequiel Garcia 16002adb719dSEzequiel Garcia /* Initialize the TSO handler, and prepare the first payload */ 16012adb719dSEzequiel Garcia tso_start(skb, &tso); 16022adb719dSEzequiel Garcia 16032adb719dSEzequiel Garcia total_len = skb->len - hdr_len; 16042adb719dSEzequiel Garcia while (total_len > 0) { 16052adb719dSEzequiel Garcia char *hdr; 16062adb719dSEzequiel Garcia 16072adb719dSEzequiel Garcia data_left = min_t(int, skb_shinfo(skb)->gso_size, total_len); 16082adb719dSEzequiel Garcia total_len -= data_left; 16092adb719dSEzequiel Garcia desc_count++; 16102adb719dSEzequiel Garcia 16112adb719dSEzequiel Garcia /* prepare packet headers: MAC + IP + TCP */ 16122adb719dSEzequiel Garcia hdr = txq->tso_hdrs + txq->txq_put_index * TSO_HEADER_SIZE; 16132adb719dSEzequiel Garcia tso_build_hdr(skb, hdr, &tso, data_left, total_len == 0); 16142adb719dSEzequiel Garcia 16152adb719dSEzequiel Garcia mvneta_tso_put_hdr(skb, pp, txq); 16162adb719dSEzequiel Garcia 16172adb719dSEzequiel Garcia while (data_left > 0) { 16182adb719dSEzequiel Garcia int size; 16192adb719dSEzequiel Garcia desc_count++; 16202adb719dSEzequiel Garcia 16212adb719dSEzequiel Garcia size = min_t(int, tso.size, data_left); 16222adb719dSEzequiel Garcia 16232adb719dSEzequiel Garcia if (mvneta_tso_put_data(dev, txq, skb, 16242adb719dSEzequiel Garcia tso.data, size, 16252adb719dSEzequiel Garcia size == data_left, 16262adb719dSEzequiel Garcia total_len == 0)) 16272adb719dSEzequiel Garcia goto err_release; 16282adb719dSEzequiel Garcia data_left -= size; 16292adb719dSEzequiel Garcia 16302adb719dSEzequiel Garcia tso_build_data(skb, &tso, size); 16312adb719dSEzequiel Garcia } 16322adb719dSEzequiel Garcia } 16332adb719dSEzequiel Garcia 16342adb719dSEzequiel Garcia return desc_count; 16352adb719dSEzequiel Garcia 16362adb719dSEzequiel Garcia err_release: 16372adb719dSEzequiel Garcia /* Release all used data descriptors; header descriptors must not 16382adb719dSEzequiel Garcia * be DMA-unmapped. 16392adb719dSEzequiel Garcia */ 16402adb719dSEzequiel Garcia for (i = desc_count - 1; i >= 0; i--) { 16412adb719dSEzequiel Garcia struct mvneta_tx_desc *tx_desc = txq->descs + i; 16422adb719dSEzequiel Garcia if (!(tx_desc->command & MVNETA_TXD_F_DESC)) 16432adb719dSEzequiel Garcia dma_unmap_single(pp->dev->dev.parent, 16442adb719dSEzequiel Garcia tx_desc->buf_phys_addr, 16452adb719dSEzequiel Garcia tx_desc->data_size, 16462adb719dSEzequiel Garcia DMA_TO_DEVICE); 16472adb719dSEzequiel Garcia mvneta_txq_desc_put(txq); 16482adb719dSEzequiel Garcia } 16492adb719dSEzequiel Garcia return 0; 16502adb719dSEzequiel Garcia } 16512adb719dSEzequiel Garcia 1652c5aff182SThomas Petazzoni /* Handle tx fragmentation processing */ 1653c5aff182SThomas Petazzoni static int mvneta_tx_frag_process(struct mvneta_port *pp, struct sk_buff *skb, 1654c5aff182SThomas Petazzoni struct mvneta_tx_queue *txq) 1655c5aff182SThomas Petazzoni { 1656c5aff182SThomas Petazzoni struct mvneta_tx_desc *tx_desc; 16573d4ea02fSEzequiel Garcia int i, nr_frags = skb_shinfo(skb)->nr_frags; 1658c5aff182SThomas Petazzoni 16593d4ea02fSEzequiel Garcia for (i = 0; i < nr_frags; i++) { 1660c5aff182SThomas Petazzoni skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 1661c5aff182SThomas Petazzoni void *addr = page_address(frag->page.p) + frag->page_offset; 1662c5aff182SThomas Petazzoni 1663c5aff182SThomas Petazzoni tx_desc = mvneta_txq_next_desc_get(txq); 1664c5aff182SThomas Petazzoni tx_desc->data_size = frag->size; 1665c5aff182SThomas Petazzoni 1666c5aff182SThomas Petazzoni tx_desc->buf_phys_addr = 1667c5aff182SThomas Petazzoni dma_map_single(pp->dev->dev.parent, addr, 1668c5aff182SThomas Petazzoni tx_desc->data_size, DMA_TO_DEVICE); 1669c5aff182SThomas Petazzoni 1670c5aff182SThomas Petazzoni if (dma_mapping_error(pp->dev->dev.parent, 1671c5aff182SThomas Petazzoni tx_desc->buf_phys_addr)) { 1672c5aff182SThomas Petazzoni mvneta_txq_desc_put(txq); 1673c5aff182SThomas Petazzoni goto error; 1674c5aff182SThomas Petazzoni } 1675c5aff182SThomas Petazzoni 16763d4ea02fSEzequiel Garcia if (i == nr_frags - 1) { 1677c5aff182SThomas Petazzoni /* Last descriptor */ 1678c5aff182SThomas Petazzoni tx_desc->command = MVNETA_TXD_L_DESC | MVNETA_TXD_Z_PAD; 1679c5aff182SThomas Petazzoni txq->tx_skb[txq->txq_put_index] = skb; 1680c5aff182SThomas Petazzoni } else { 1681c5aff182SThomas Petazzoni /* Descriptor in the middle: Not First, Not Last */ 1682c5aff182SThomas Petazzoni tx_desc->command = 0; 1683c5aff182SThomas Petazzoni txq->tx_skb[txq->txq_put_index] = NULL; 1684c5aff182SThomas Petazzoni } 16853d4ea02fSEzequiel Garcia mvneta_txq_inc_put(txq); 1686c5aff182SThomas Petazzoni } 1687c5aff182SThomas Petazzoni 1688c5aff182SThomas Petazzoni return 0; 1689c5aff182SThomas Petazzoni 1690c5aff182SThomas Petazzoni error: 1691c5aff182SThomas Petazzoni /* Release all descriptors that were used to map fragments of 16926a20c175SThomas Petazzoni * this packet, as well as the corresponding DMA mappings 16936a20c175SThomas Petazzoni */ 1694c5aff182SThomas Petazzoni for (i = i - 1; i >= 0; i--) { 1695c5aff182SThomas Petazzoni tx_desc = txq->descs + i; 1696c5aff182SThomas Petazzoni dma_unmap_single(pp->dev->dev.parent, 1697c5aff182SThomas Petazzoni tx_desc->buf_phys_addr, 1698c5aff182SThomas Petazzoni tx_desc->data_size, 1699c5aff182SThomas Petazzoni DMA_TO_DEVICE); 1700c5aff182SThomas Petazzoni mvneta_txq_desc_put(txq); 1701c5aff182SThomas Petazzoni } 1702c5aff182SThomas Petazzoni 1703c5aff182SThomas Petazzoni return -ENOMEM; 1704c5aff182SThomas Petazzoni } 1705c5aff182SThomas Petazzoni 1706c5aff182SThomas Petazzoni /* Main tx processing */ 1707c5aff182SThomas Petazzoni static int mvneta_tx(struct sk_buff *skb, struct net_device *dev) 1708c5aff182SThomas Petazzoni { 1709c5aff182SThomas Petazzoni struct mvneta_port *pp = netdev_priv(dev); 1710ee40a116SWilly Tarreau u16 txq_id = skb_get_queue_mapping(skb); 1711ee40a116SWilly Tarreau struct mvneta_tx_queue *txq = &pp->txqs[txq_id]; 1712c5aff182SThomas Petazzoni struct mvneta_tx_desc *tx_desc; 1713c5aff182SThomas Petazzoni int frags = 0; 1714c5aff182SThomas Petazzoni u32 tx_cmd; 1715c5aff182SThomas Petazzoni 1716c5aff182SThomas Petazzoni if (!netif_running(dev)) 1717c5aff182SThomas Petazzoni goto out; 1718c5aff182SThomas Petazzoni 17192adb719dSEzequiel Garcia if (skb_is_gso(skb)) { 17202adb719dSEzequiel Garcia frags = mvneta_tx_tso(skb, dev, txq); 17212adb719dSEzequiel Garcia goto out; 17222adb719dSEzequiel Garcia } 17232adb719dSEzequiel Garcia 1724c5aff182SThomas Petazzoni frags = skb_shinfo(skb)->nr_frags + 1; 1725c5aff182SThomas Petazzoni 1726c5aff182SThomas Petazzoni /* Get a descriptor for the first part of the packet */ 1727c5aff182SThomas Petazzoni tx_desc = mvneta_txq_next_desc_get(txq); 1728c5aff182SThomas Petazzoni 1729c5aff182SThomas Petazzoni tx_cmd = mvneta_skb_tx_csum(pp, skb); 1730c5aff182SThomas Petazzoni 1731c5aff182SThomas Petazzoni tx_desc->data_size = skb_headlen(skb); 1732c5aff182SThomas Petazzoni 1733c5aff182SThomas Petazzoni tx_desc->buf_phys_addr = dma_map_single(dev->dev.parent, skb->data, 1734c5aff182SThomas Petazzoni tx_desc->data_size, 1735c5aff182SThomas Petazzoni DMA_TO_DEVICE); 1736c5aff182SThomas Petazzoni if (unlikely(dma_mapping_error(dev->dev.parent, 1737c5aff182SThomas Petazzoni tx_desc->buf_phys_addr))) { 1738c5aff182SThomas Petazzoni mvneta_txq_desc_put(txq); 1739c5aff182SThomas Petazzoni frags = 0; 1740c5aff182SThomas Petazzoni goto out; 1741c5aff182SThomas Petazzoni } 1742c5aff182SThomas Petazzoni 1743c5aff182SThomas Petazzoni if (frags == 1) { 1744c5aff182SThomas Petazzoni /* First and Last descriptor */ 1745c5aff182SThomas Petazzoni tx_cmd |= MVNETA_TXD_FLZ_DESC; 1746c5aff182SThomas Petazzoni tx_desc->command = tx_cmd; 1747c5aff182SThomas Petazzoni txq->tx_skb[txq->txq_put_index] = skb; 1748c5aff182SThomas Petazzoni mvneta_txq_inc_put(txq); 1749c5aff182SThomas Petazzoni } else { 1750c5aff182SThomas Petazzoni /* First but not Last */ 1751c5aff182SThomas Petazzoni tx_cmd |= MVNETA_TXD_F_DESC; 1752c5aff182SThomas Petazzoni txq->tx_skb[txq->txq_put_index] = NULL; 1753c5aff182SThomas Petazzoni mvneta_txq_inc_put(txq); 1754c5aff182SThomas Petazzoni tx_desc->command = tx_cmd; 1755c5aff182SThomas Petazzoni /* Continue with other skb fragments */ 1756c5aff182SThomas Petazzoni if (mvneta_tx_frag_process(pp, skb, txq)) { 1757c5aff182SThomas Petazzoni dma_unmap_single(dev->dev.parent, 1758c5aff182SThomas Petazzoni tx_desc->buf_phys_addr, 1759c5aff182SThomas Petazzoni tx_desc->data_size, 1760c5aff182SThomas Petazzoni DMA_TO_DEVICE); 1761c5aff182SThomas Petazzoni mvneta_txq_desc_put(txq); 1762c5aff182SThomas Petazzoni frags = 0; 1763c5aff182SThomas Petazzoni goto out; 1764c5aff182SThomas Petazzoni } 1765c5aff182SThomas Petazzoni } 1766c5aff182SThomas Petazzoni 1767e19d2ddaSEzequiel Garcia out: 1768e19d2ddaSEzequiel Garcia if (frags > 0) { 1769e19d2ddaSEzequiel Garcia struct mvneta_pcpu_stats *stats = this_cpu_ptr(pp->stats); 1770e19d2ddaSEzequiel Garcia struct netdev_queue *nq = netdev_get_tx_queue(dev, txq_id); 1771e19d2ddaSEzequiel Garcia 1772c5aff182SThomas Petazzoni txq->count += frags; 1773c5aff182SThomas Petazzoni mvneta_txq_pend_desc_add(pp, txq, frags); 1774c5aff182SThomas Petazzoni 1775c5aff182SThomas Petazzoni if (txq->size - txq->count < MAX_SKB_FRAGS + 1) 1776c5aff182SThomas Petazzoni netif_tx_stop_queue(nq); 1777c5aff182SThomas Petazzoni 177874c41b04Swilly tarreau u64_stats_update_begin(&stats->syncp); 177974c41b04Swilly tarreau stats->tx_packets++; 178074c41b04Swilly tarreau stats->tx_bytes += skb->len; 178174c41b04Swilly tarreau u64_stats_update_end(&stats->syncp); 1782c5aff182SThomas Petazzoni } else { 1783c5aff182SThomas Petazzoni dev->stats.tx_dropped++; 1784c5aff182SThomas Petazzoni dev_kfree_skb_any(skb); 1785c5aff182SThomas Petazzoni } 1786c5aff182SThomas Petazzoni 1787c5aff182SThomas Petazzoni return NETDEV_TX_OK; 1788c5aff182SThomas Petazzoni } 1789c5aff182SThomas Petazzoni 1790c5aff182SThomas Petazzoni 1791c5aff182SThomas Petazzoni /* Free tx resources, when resetting a port */ 1792c5aff182SThomas Petazzoni static void mvneta_txq_done_force(struct mvneta_port *pp, 1793c5aff182SThomas Petazzoni struct mvneta_tx_queue *txq) 1794c5aff182SThomas Petazzoni 1795c5aff182SThomas Petazzoni { 1796c5aff182SThomas Petazzoni int tx_done = txq->count; 1797c5aff182SThomas Petazzoni 1798c5aff182SThomas Petazzoni mvneta_txq_bufs_free(pp, txq, tx_done); 1799c5aff182SThomas Petazzoni 1800c5aff182SThomas Petazzoni /* reset txq */ 1801c5aff182SThomas Petazzoni txq->count = 0; 1802c5aff182SThomas Petazzoni txq->txq_put_index = 0; 1803c5aff182SThomas Petazzoni txq->txq_get_index = 0; 1804c5aff182SThomas Petazzoni } 1805c5aff182SThomas Petazzoni 18066c498974Swilly tarreau /* Handle tx done - called in softirq context. The <cause_tx_done> argument 18076c498974Swilly tarreau * must be a valid cause according to MVNETA_TXQ_INTR_MASK_ALL. 18086c498974Swilly tarreau */ 18090713a86aSArnaud Ebalard static void mvneta_tx_done_gbe(struct mvneta_port *pp, u32 cause_tx_done) 1810c5aff182SThomas Petazzoni { 1811c5aff182SThomas Petazzoni struct mvneta_tx_queue *txq; 1812c5aff182SThomas Petazzoni struct netdev_queue *nq; 1813c5aff182SThomas Petazzoni 18146c498974Swilly tarreau while (cause_tx_done) { 1815c5aff182SThomas Petazzoni txq = mvneta_tx_done_policy(pp, cause_tx_done); 1816c5aff182SThomas Petazzoni 1817c5aff182SThomas Petazzoni nq = netdev_get_tx_queue(pp->dev, txq->id); 1818c5aff182SThomas Petazzoni __netif_tx_lock(nq, smp_processor_id()); 1819c5aff182SThomas Petazzoni 18200713a86aSArnaud Ebalard if (txq->count) 18210713a86aSArnaud Ebalard mvneta_txq_done(pp, txq); 1822c5aff182SThomas Petazzoni 1823c5aff182SThomas Petazzoni __netif_tx_unlock(nq); 1824c5aff182SThomas Petazzoni cause_tx_done &= ~((1 << txq->id)); 1825c5aff182SThomas Petazzoni } 1826c5aff182SThomas Petazzoni } 1827c5aff182SThomas Petazzoni 18286a20c175SThomas Petazzoni /* Compute crc8 of the specified address, using a unique algorithm , 1829c5aff182SThomas Petazzoni * according to hw spec, different than generic crc8 algorithm 1830c5aff182SThomas Petazzoni */ 1831c5aff182SThomas Petazzoni static int mvneta_addr_crc(unsigned char *addr) 1832c5aff182SThomas Petazzoni { 1833c5aff182SThomas Petazzoni int crc = 0; 1834c5aff182SThomas Petazzoni int i; 1835c5aff182SThomas Petazzoni 1836c5aff182SThomas Petazzoni for (i = 0; i < ETH_ALEN; i++) { 1837c5aff182SThomas Petazzoni int j; 1838c5aff182SThomas Petazzoni 1839c5aff182SThomas Petazzoni crc = (crc ^ addr[i]) << 8; 1840c5aff182SThomas Petazzoni for (j = 7; j >= 0; j--) { 1841c5aff182SThomas Petazzoni if (crc & (0x100 << j)) 1842c5aff182SThomas Petazzoni crc ^= 0x107 << j; 1843c5aff182SThomas Petazzoni } 1844c5aff182SThomas Petazzoni } 1845c5aff182SThomas Petazzoni 1846c5aff182SThomas Petazzoni return crc; 1847c5aff182SThomas Petazzoni } 1848c5aff182SThomas Petazzoni 1849c5aff182SThomas Petazzoni /* This method controls the net device special MAC multicast support. 1850c5aff182SThomas Petazzoni * The Special Multicast Table for MAC addresses supports MAC of the form 1851c5aff182SThomas Petazzoni * 0x01-00-5E-00-00-XX (where XX is between 0x00 and 0xFF). 1852c5aff182SThomas Petazzoni * The MAC DA[7:0] bits are used as a pointer to the Special Multicast 1853c5aff182SThomas Petazzoni * Table entries in the DA-Filter table. This method set the Special 1854c5aff182SThomas Petazzoni * Multicast Table appropriate entry. 1855c5aff182SThomas Petazzoni */ 1856c5aff182SThomas Petazzoni static void mvneta_set_special_mcast_addr(struct mvneta_port *pp, 1857c5aff182SThomas Petazzoni unsigned char last_byte, 1858c5aff182SThomas Petazzoni int queue) 1859c5aff182SThomas Petazzoni { 1860c5aff182SThomas Petazzoni unsigned int smc_table_reg; 1861c5aff182SThomas Petazzoni unsigned int tbl_offset; 1862c5aff182SThomas Petazzoni unsigned int reg_offset; 1863c5aff182SThomas Petazzoni 1864c5aff182SThomas Petazzoni /* Register offset from SMC table base */ 1865c5aff182SThomas Petazzoni tbl_offset = (last_byte / 4); 1866c5aff182SThomas Petazzoni /* Entry offset within the above reg */ 1867c5aff182SThomas Petazzoni reg_offset = last_byte % 4; 1868c5aff182SThomas Petazzoni 1869c5aff182SThomas Petazzoni smc_table_reg = mvreg_read(pp, (MVNETA_DA_FILT_SPEC_MCAST 1870c5aff182SThomas Petazzoni + tbl_offset * 4)); 1871c5aff182SThomas Petazzoni 1872c5aff182SThomas Petazzoni if (queue == -1) 1873c5aff182SThomas Petazzoni smc_table_reg &= ~(0xff << (8 * reg_offset)); 1874c5aff182SThomas Petazzoni else { 1875c5aff182SThomas Petazzoni smc_table_reg &= ~(0xff << (8 * reg_offset)); 1876c5aff182SThomas Petazzoni smc_table_reg |= ((0x01 | (queue << 1)) << (8 * reg_offset)); 1877c5aff182SThomas Petazzoni } 1878c5aff182SThomas Petazzoni 1879c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_DA_FILT_SPEC_MCAST + tbl_offset * 4, 1880c5aff182SThomas Petazzoni smc_table_reg); 1881c5aff182SThomas Petazzoni } 1882c5aff182SThomas Petazzoni 1883c5aff182SThomas Petazzoni /* This method controls the network device Other MAC multicast support. 1884c5aff182SThomas Petazzoni * The Other Multicast Table is used for multicast of another type. 1885c5aff182SThomas Petazzoni * A CRC-8 is used as an index to the Other Multicast Table entries 1886c5aff182SThomas Petazzoni * in the DA-Filter table. 1887c5aff182SThomas Petazzoni * The method gets the CRC-8 value from the calling routine and 1888c5aff182SThomas Petazzoni * sets the Other Multicast Table appropriate entry according to the 1889c5aff182SThomas Petazzoni * specified CRC-8 . 1890c5aff182SThomas Petazzoni */ 1891c5aff182SThomas Petazzoni static void mvneta_set_other_mcast_addr(struct mvneta_port *pp, 1892c5aff182SThomas Petazzoni unsigned char crc8, 1893c5aff182SThomas Petazzoni int queue) 1894c5aff182SThomas Petazzoni { 1895c5aff182SThomas Petazzoni unsigned int omc_table_reg; 1896c5aff182SThomas Petazzoni unsigned int tbl_offset; 1897c5aff182SThomas Petazzoni unsigned int reg_offset; 1898c5aff182SThomas Petazzoni 1899c5aff182SThomas Petazzoni tbl_offset = (crc8 / 4) * 4; /* Register offset from OMC table base */ 1900c5aff182SThomas Petazzoni reg_offset = crc8 % 4; /* Entry offset within the above reg */ 1901c5aff182SThomas Petazzoni 1902c5aff182SThomas Petazzoni omc_table_reg = mvreg_read(pp, MVNETA_DA_FILT_OTH_MCAST + tbl_offset); 1903c5aff182SThomas Petazzoni 1904c5aff182SThomas Petazzoni if (queue == -1) { 1905c5aff182SThomas Petazzoni /* Clear accepts frame bit at specified Other DA table entry */ 1906c5aff182SThomas Petazzoni omc_table_reg &= ~(0xff << (8 * reg_offset)); 1907c5aff182SThomas Petazzoni } else { 1908c5aff182SThomas Petazzoni omc_table_reg &= ~(0xff << (8 * reg_offset)); 1909c5aff182SThomas Petazzoni omc_table_reg |= ((0x01 | (queue << 1)) << (8 * reg_offset)); 1910c5aff182SThomas Petazzoni } 1911c5aff182SThomas Petazzoni 1912c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_DA_FILT_OTH_MCAST + tbl_offset, omc_table_reg); 1913c5aff182SThomas Petazzoni } 1914c5aff182SThomas Petazzoni 1915c5aff182SThomas Petazzoni /* The network device supports multicast using two tables: 1916c5aff182SThomas Petazzoni * 1) Special Multicast Table for MAC addresses of the form 1917c5aff182SThomas Petazzoni * 0x01-00-5E-00-00-XX (where XX is between 0x00 and 0xFF). 1918c5aff182SThomas Petazzoni * The MAC DA[7:0] bits are used as a pointer to the Special Multicast 1919c5aff182SThomas Petazzoni * Table entries in the DA-Filter table. 1920c5aff182SThomas Petazzoni * 2) Other Multicast Table for multicast of another type. A CRC-8 value 1921c5aff182SThomas Petazzoni * is used as an index to the Other Multicast Table entries in the 1922c5aff182SThomas Petazzoni * DA-Filter table. 1923c5aff182SThomas Petazzoni */ 1924c5aff182SThomas Petazzoni static int mvneta_mcast_addr_set(struct mvneta_port *pp, unsigned char *p_addr, 1925c5aff182SThomas Petazzoni int queue) 1926c5aff182SThomas Petazzoni { 1927c5aff182SThomas Petazzoni unsigned char crc_result = 0; 1928c5aff182SThomas Petazzoni 1929c5aff182SThomas Petazzoni if (memcmp(p_addr, "\x01\x00\x5e\x00\x00", 5) == 0) { 1930c5aff182SThomas Petazzoni mvneta_set_special_mcast_addr(pp, p_addr[5], queue); 1931c5aff182SThomas Petazzoni return 0; 1932c5aff182SThomas Petazzoni } 1933c5aff182SThomas Petazzoni 1934c5aff182SThomas Petazzoni crc_result = mvneta_addr_crc(p_addr); 1935c5aff182SThomas Petazzoni if (queue == -1) { 1936c5aff182SThomas Petazzoni if (pp->mcast_count[crc_result] == 0) { 1937c5aff182SThomas Petazzoni netdev_info(pp->dev, "No valid Mcast for crc8=0x%02x\n", 1938c5aff182SThomas Petazzoni crc_result); 1939c5aff182SThomas Petazzoni return -EINVAL; 1940c5aff182SThomas Petazzoni } 1941c5aff182SThomas Petazzoni 1942c5aff182SThomas Petazzoni pp->mcast_count[crc_result]--; 1943c5aff182SThomas Petazzoni if (pp->mcast_count[crc_result] != 0) { 1944c5aff182SThomas Petazzoni netdev_info(pp->dev, 1945c5aff182SThomas Petazzoni "After delete there are %d valid Mcast for crc8=0x%02x\n", 1946c5aff182SThomas Petazzoni pp->mcast_count[crc_result], crc_result); 1947c5aff182SThomas Petazzoni return -EINVAL; 1948c5aff182SThomas Petazzoni } 1949c5aff182SThomas Petazzoni } else 1950c5aff182SThomas Petazzoni pp->mcast_count[crc_result]++; 1951c5aff182SThomas Petazzoni 1952c5aff182SThomas Petazzoni mvneta_set_other_mcast_addr(pp, crc_result, queue); 1953c5aff182SThomas Petazzoni 1954c5aff182SThomas Petazzoni return 0; 1955c5aff182SThomas Petazzoni } 1956c5aff182SThomas Petazzoni 1957c5aff182SThomas Petazzoni /* Configure Fitering mode of Ethernet port */ 1958c5aff182SThomas Petazzoni static void mvneta_rx_unicast_promisc_set(struct mvneta_port *pp, 1959c5aff182SThomas Petazzoni int is_promisc) 1960c5aff182SThomas Petazzoni { 1961c5aff182SThomas Petazzoni u32 port_cfg_reg, val; 1962c5aff182SThomas Petazzoni 1963c5aff182SThomas Petazzoni port_cfg_reg = mvreg_read(pp, MVNETA_PORT_CONFIG); 1964c5aff182SThomas Petazzoni 1965c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_TYPE_PRIO); 1966c5aff182SThomas Petazzoni 1967c5aff182SThomas Petazzoni /* Set / Clear UPM bit in port configuration register */ 1968c5aff182SThomas Petazzoni if (is_promisc) { 1969c5aff182SThomas Petazzoni /* Accept all Unicast addresses */ 1970c5aff182SThomas Petazzoni port_cfg_reg |= MVNETA_UNI_PROMISC_MODE; 1971c5aff182SThomas Petazzoni val |= MVNETA_FORCE_UNI; 1972c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_MAC_ADDR_LOW, 0xffff); 1973c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_MAC_ADDR_HIGH, 0xffffffff); 1974c5aff182SThomas Petazzoni } else { 1975c5aff182SThomas Petazzoni /* Reject all Unicast addresses */ 1976c5aff182SThomas Petazzoni port_cfg_reg &= ~MVNETA_UNI_PROMISC_MODE; 1977c5aff182SThomas Petazzoni val &= ~MVNETA_FORCE_UNI; 1978c5aff182SThomas Petazzoni } 1979c5aff182SThomas Petazzoni 1980c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_PORT_CONFIG, port_cfg_reg); 1981c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_TYPE_PRIO, val); 1982c5aff182SThomas Petazzoni } 1983c5aff182SThomas Petazzoni 1984c5aff182SThomas Petazzoni /* register unicast and multicast addresses */ 1985c5aff182SThomas Petazzoni static void mvneta_set_rx_mode(struct net_device *dev) 1986c5aff182SThomas Petazzoni { 1987c5aff182SThomas Petazzoni struct mvneta_port *pp = netdev_priv(dev); 1988c5aff182SThomas Petazzoni struct netdev_hw_addr *ha; 1989c5aff182SThomas Petazzoni 1990c5aff182SThomas Petazzoni if (dev->flags & IFF_PROMISC) { 1991c5aff182SThomas Petazzoni /* Accept all: Multicast + Unicast */ 1992c5aff182SThomas Petazzoni mvneta_rx_unicast_promisc_set(pp, 1); 1993c5aff182SThomas Petazzoni mvneta_set_ucast_table(pp, rxq_def); 1994c5aff182SThomas Petazzoni mvneta_set_special_mcast_table(pp, rxq_def); 1995c5aff182SThomas Petazzoni mvneta_set_other_mcast_table(pp, rxq_def); 1996c5aff182SThomas Petazzoni } else { 1997c5aff182SThomas Petazzoni /* Accept single Unicast */ 1998c5aff182SThomas Petazzoni mvneta_rx_unicast_promisc_set(pp, 0); 1999c5aff182SThomas Petazzoni mvneta_set_ucast_table(pp, -1); 2000c5aff182SThomas Petazzoni mvneta_mac_addr_set(pp, dev->dev_addr, rxq_def); 2001c5aff182SThomas Petazzoni 2002c5aff182SThomas Petazzoni if (dev->flags & IFF_ALLMULTI) { 2003c5aff182SThomas Petazzoni /* Accept all multicast */ 2004c5aff182SThomas Petazzoni mvneta_set_special_mcast_table(pp, rxq_def); 2005c5aff182SThomas Petazzoni mvneta_set_other_mcast_table(pp, rxq_def); 2006c5aff182SThomas Petazzoni } else { 2007c5aff182SThomas Petazzoni /* Accept only initialized multicast */ 2008c5aff182SThomas Petazzoni mvneta_set_special_mcast_table(pp, -1); 2009c5aff182SThomas Petazzoni mvneta_set_other_mcast_table(pp, -1); 2010c5aff182SThomas Petazzoni 2011c5aff182SThomas Petazzoni if (!netdev_mc_empty(dev)) { 2012c5aff182SThomas Petazzoni netdev_for_each_mc_addr(ha, dev) { 2013c5aff182SThomas Petazzoni mvneta_mcast_addr_set(pp, ha->addr, 2014c5aff182SThomas Petazzoni rxq_def); 2015c5aff182SThomas Petazzoni } 2016c5aff182SThomas Petazzoni } 2017c5aff182SThomas Petazzoni } 2018c5aff182SThomas Petazzoni } 2019c5aff182SThomas Petazzoni } 2020c5aff182SThomas Petazzoni 2021c5aff182SThomas Petazzoni /* Interrupt handling - the callback for request_irq() */ 2022c5aff182SThomas Petazzoni static irqreturn_t mvneta_isr(int irq, void *dev_id) 2023c5aff182SThomas Petazzoni { 2024c5aff182SThomas Petazzoni struct mvneta_port *pp = (struct mvneta_port *)dev_id; 2025c5aff182SThomas Petazzoni 2026c5aff182SThomas Petazzoni /* Mask all interrupts */ 2027c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_INTR_NEW_MASK, 0); 2028c5aff182SThomas Petazzoni 2029c5aff182SThomas Petazzoni napi_schedule(&pp->napi); 2030c5aff182SThomas Petazzoni 2031c5aff182SThomas Petazzoni return IRQ_HANDLED; 2032c5aff182SThomas Petazzoni } 2033c5aff182SThomas Petazzoni 2034c5aff182SThomas Petazzoni /* NAPI handler 2035c5aff182SThomas Petazzoni * Bits 0 - 7 of the causeRxTx register indicate that are transmitted 2036c5aff182SThomas Petazzoni * packets on the corresponding TXQ (Bit 0 is for TX queue 1). 2037c5aff182SThomas Petazzoni * Bits 8 -15 of the cause Rx Tx register indicate that are received 2038c5aff182SThomas Petazzoni * packets on the corresponding RXQ (Bit 8 is for RX queue 0). 2039c5aff182SThomas Petazzoni * Each CPU has its own causeRxTx register 2040c5aff182SThomas Petazzoni */ 2041c5aff182SThomas Petazzoni static int mvneta_poll(struct napi_struct *napi, int budget) 2042c5aff182SThomas Petazzoni { 2043c5aff182SThomas Petazzoni int rx_done = 0; 2044c5aff182SThomas Petazzoni u32 cause_rx_tx; 2045c5aff182SThomas Petazzoni unsigned long flags; 2046c5aff182SThomas Petazzoni struct mvneta_port *pp = netdev_priv(napi->dev); 2047c5aff182SThomas Petazzoni 2048c5aff182SThomas Petazzoni if (!netif_running(pp->dev)) { 2049c5aff182SThomas Petazzoni napi_complete(napi); 2050c5aff182SThomas Petazzoni return rx_done; 2051c5aff182SThomas Petazzoni } 2052c5aff182SThomas Petazzoni 2053c5aff182SThomas Petazzoni /* Read cause register */ 2054c5aff182SThomas Petazzoni cause_rx_tx = mvreg_read(pp, MVNETA_INTR_NEW_CAUSE) & 205571f6d1b3Swilly tarreau (MVNETA_RX_INTR_MASK(rxq_number) | MVNETA_TX_INTR_MASK(txq_number)); 205671f6d1b3Swilly tarreau 205771f6d1b3Swilly tarreau /* Release Tx descriptors */ 205871f6d1b3Swilly tarreau if (cause_rx_tx & MVNETA_TX_INTR_MASK_ALL) { 20590713a86aSArnaud Ebalard mvneta_tx_done_gbe(pp, (cause_rx_tx & MVNETA_TX_INTR_MASK_ALL)); 206071f6d1b3Swilly tarreau cause_rx_tx &= ~MVNETA_TX_INTR_MASK_ALL; 206171f6d1b3Swilly tarreau } 2062c5aff182SThomas Petazzoni 20636a20c175SThomas Petazzoni /* For the case where the last mvneta_poll did not process all 2064c5aff182SThomas Petazzoni * RX packets 2065c5aff182SThomas Petazzoni */ 2066c5aff182SThomas Petazzoni cause_rx_tx |= pp->cause_rx_tx; 2067c5aff182SThomas Petazzoni if (rxq_number > 1) { 206871f6d1b3Swilly tarreau while ((cause_rx_tx & MVNETA_RX_INTR_MASK_ALL) && (budget > 0)) { 2069c5aff182SThomas Petazzoni int count; 2070c5aff182SThomas Petazzoni struct mvneta_rx_queue *rxq; 2071c5aff182SThomas Petazzoni /* get rx queue number from cause_rx_tx */ 2072c5aff182SThomas Petazzoni rxq = mvneta_rx_policy(pp, cause_rx_tx); 2073c5aff182SThomas Petazzoni if (!rxq) 2074c5aff182SThomas Petazzoni break; 2075c5aff182SThomas Petazzoni 2076c5aff182SThomas Petazzoni /* process the packet in that rx queue */ 2077c5aff182SThomas Petazzoni count = mvneta_rx(pp, budget, rxq); 2078c5aff182SThomas Petazzoni rx_done += count; 2079c5aff182SThomas Petazzoni budget -= count; 2080c5aff182SThomas Petazzoni if (budget > 0) { 20816a20c175SThomas Petazzoni /* set off the rx bit of the 20826a20c175SThomas Petazzoni * corresponding bit in the cause rx 20836a20c175SThomas Petazzoni * tx register, so that next iteration 20846a20c175SThomas Petazzoni * will find the next rx queue where 20856a20c175SThomas Petazzoni * packets are received on 20866a20c175SThomas Petazzoni */ 2087c5aff182SThomas Petazzoni cause_rx_tx &= ~((1 << rxq->id) << 8); 2088c5aff182SThomas Petazzoni } 2089c5aff182SThomas Petazzoni } 2090c5aff182SThomas Petazzoni } else { 2091c5aff182SThomas Petazzoni rx_done = mvneta_rx(pp, budget, &pp->rxqs[rxq_def]); 2092c5aff182SThomas Petazzoni budget -= rx_done; 2093c5aff182SThomas Petazzoni } 2094c5aff182SThomas Petazzoni 2095c5aff182SThomas Petazzoni if (budget > 0) { 2096c5aff182SThomas Petazzoni cause_rx_tx = 0; 2097c5aff182SThomas Petazzoni napi_complete(napi); 2098c5aff182SThomas Petazzoni local_irq_save(flags); 2099c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_INTR_NEW_MASK, 210071f6d1b3Swilly tarreau MVNETA_RX_INTR_MASK(rxq_number) | MVNETA_TX_INTR_MASK(txq_number)); 2101c5aff182SThomas Petazzoni local_irq_restore(flags); 2102c5aff182SThomas Petazzoni } 2103c5aff182SThomas Petazzoni 2104c5aff182SThomas Petazzoni pp->cause_rx_tx = cause_rx_tx; 2105c5aff182SThomas Petazzoni return rx_done; 2106c5aff182SThomas Petazzoni } 2107c5aff182SThomas Petazzoni 2108c5aff182SThomas Petazzoni /* Handle rxq fill: allocates rxq skbs; called when initializing a port */ 2109c5aff182SThomas Petazzoni static int mvneta_rxq_fill(struct mvneta_port *pp, struct mvneta_rx_queue *rxq, 2110c5aff182SThomas Petazzoni int num) 2111c5aff182SThomas Petazzoni { 2112c5aff182SThomas Petazzoni int i; 2113c5aff182SThomas Petazzoni 2114c5aff182SThomas Petazzoni for (i = 0; i < num; i++) { 2115a1a65ab1Swilly tarreau memset(rxq->descs + i, 0, sizeof(struct mvneta_rx_desc)); 2116a1a65ab1Swilly tarreau if (mvneta_rx_refill(pp, rxq->descs + i) != 0) { 2117a1a65ab1Swilly tarreau netdev_err(pp->dev, "%s:rxq %d, %d of %d buffs filled\n", 2118c5aff182SThomas Petazzoni __func__, rxq->id, i, num); 2119c5aff182SThomas Petazzoni break; 2120c5aff182SThomas Petazzoni } 2121c5aff182SThomas Petazzoni } 2122c5aff182SThomas Petazzoni 2123c5aff182SThomas Petazzoni /* Add this number of RX descriptors as non occupied (ready to 21246a20c175SThomas Petazzoni * get packets) 21256a20c175SThomas Petazzoni */ 2126c5aff182SThomas Petazzoni mvneta_rxq_non_occup_desc_add(pp, rxq, i); 2127c5aff182SThomas Petazzoni 2128c5aff182SThomas Petazzoni return i; 2129c5aff182SThomas Petazzoni } 2130c5aff182SThomas Petazzoni 2131c5aff182SThomas Petazzoni /* Free all packets pending transmit from all TXQs and reset TX port */ 2132c5aff182SThomas Petazzoni static void mvneta_tx_reset(struct mvneta_port *pp) 2133c5aff182SThomas Petazzoni { 2134c5aff182SThomas Petazzoni int queue; 2135c5aff182SThomas Petazzoni 2136c5aff182SThomas Petazzoni /* free the skb's in the hal tx ring */ 2137c5aff182SThomas Petazzoni for (queue = 0; queue < txq_number; queue++) 2138c5aff182SThomas Petazzoni mvneta_txq_done_force(pp, &pp->txqs[queue]); 2139c5aff182SThomas Petazzoni 2140c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_PORT_TX_RESET, MVNETA_PORT_TX_DMA_RESET); 2141c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_PORT_TX_RESET, 0); 2142c5aff182SThomas Petazzoni } 2143c5aff182SThomas Petazzoni 2144c5aff182SThomas Petazzoni static void mvneta_rx_reset(struct mvneta_port *pp) 2145c5aff182SThomas Petazzoni { 2146c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_PORT_RX_RESET, MVNETA_PORT_RX_DMA_RESET); 2147c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_PORT_RX_RESET, 0); 2148c5aff182SThomas Petazzoni } 2149c5aff182SThomas Petazzoni 2150c5aff182SThomas Petazzoni /* Rx/Tx queue initialization/cleanup methods */ 2151c5aff182SThomas Petazzoni 2152c5aff182SThomas Petazzoni /* Create a specified RX queue */ 2153c5aff182SThomas Petazzoni static int mvneta_rxq_init(struct mvneta_port *pp, 2154c5aff182SThomas Petazzoni struct mvneta_rx_queue *rxq) 2155c5aff182SThomas Petazzoni 2156c5aff182SThomas Petazzoni { 2157c5aff182SThomas Petazzoni rxq->size = pp->rx_ring_size; 2158c5aff182SThomas Petazzoni 2159c5aff182SThomas Petazzoni /* Allocate memory for RX descriptors */ 2160c5aff182SThomas Petazzoni rxq->descs = dma_alloc_coherent(pp->dev->dev.parent, 2161c5aff182SThomas Petazzoni rxq->size * MVNETA_DESC_ALIGNED_SIZE, 2162c5aff182SThomas Petazzoni &rxq->descs_phys, GFP_KERNEL); 2163d0320f75SJoe Perches if (rxq->descs == NULL) 2164c5aff182SThomas Petazzoni return -ENOMEM; 2165c5aff182SThomas Petazzoni 2166c5aff182SThomas Petazzoni BUG_ON(rxq->descs != 2167c5aff182SThomas Petazzoni PTR_ALIGN(rxq->descs, MVNETA_CPU_D_CACHE_LINE_SIZE)); 2168c5aff182SThomas Petazzoni 2169c5aff182SThomas Petazzoni rxq->last_desc = rxq->size - 1; 2170c5aff182SThomas Petazzoni 2171c5aff182SThomas Petazzoni /* Set Rx descriptors queue starting address */ 2172c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_RXQ_BASE_ADDR_REG(rxq->id), rxq->descs_phys); 2173c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_RXQ_SIZE_REG(rxq->id), rxq->size); 2174c5aff182SThomas Petazzoni 2175c5aff182SThomas Petazzoni /* Set Offset */ 2176c5aff182SThomas Petazzoni mvneta_rxq_offset_set(pp, rxq, NET_SKB_PAD); 2177c5aff182SThomas Petazzoni 2178c5aff182SThomas Petazzoni /* Set coalescing pkts and time */ 2179c5aff182SThomas Petazzoni mvneta_rx_pkts_coal_set(pp, rxq, rxq->pkts_coal); 2180c5aff182SThomas Petazzoni mvneta_rx_time_coal_set(pp, rxq, rxq->time_coal); 2181c5aff182SThomas Petazzoni 2182c5aff182SThomas Petazzoni /* Fill RXQ with buffers from RX pool */ 2183c5aff182SThomas Petazzoni mvneta_rxq_buf_size_set(pp, rxq, MVNETA_RX_BUF_SIZE(pp->pkt_size)); 2184c5aff182SThomas Petazzoni mvneta_rxq_bm_disable(pp, rxq); 2185c5aff182SThomas Petazzoni mvneta_rxq_fill(pp, rxq, rxq->size); 2186c5aff182SThomas Petazzoni 2187c5aff182SThomas Petazzoni return 0; 2188c5aff182SThomas Petazzoni } 2189c5aff182SThomas Petazzoni 2190c5aff182SThomas Petazzoni /* Cleanup Rx queue */ 2191c5aff182SThomas Petazzoni static void mvneta_rxq_deinit(struct mvneta_port *pp, 2192c5aff182SThomas Petazzoni struct mvneta_rx_queue *rxq) 2193c5aff182SThomas Petazzoni { 2194c5aff182SThomas Petazzoni mvneta_rxq_drop_pkts(pp, rxq); 2195c5aff182SThomas Petazzoni 2196c5aff182SThomas Petazzoni if (rxq->descs) 2197c5aff182SThomas Petazzoni dma_free_coherent(pp->dev->dev.parent, 2198c5aff182SThomas Petazzoni rxq->size * MVNETA_DESC_ALIGNED_SIZE, 2199c5aff182SThomas Petazzoni rxq->descs, 2200c5aff182SThomas Petazzoni rxq->descs_phys); 2201c5aff182SThomas Petazzoni 2202c5aff182SThomas Petazzoni rxq->descs = NULL; 2203c5aff182SThomas Petazzoni rxq->last_desc = 0; 2204c5aff182SThomas Petazzoni rxq->next_desc_to_proc = 0; 2205c5aff182SThomas Petazzoni rxq->descs_phys = 0; 2206c5aff182SThomas Petazzoni } 2207c5aff182SThomas Petazzoni 2208c5aff182SThomas Petazzoni /* Create and initialize a tx queue */ 2209c5aff182SThomas Petazzoni static int mvneta_txq_init(struct mvneta_port *pp, 2210c5aff182SThomas Petazzoni struct mvneta_tx_queue *txq) 2211c5aff182SThomas Petazzoni { 2212c5aff182SThomas Petazzoni txq->size = pp->tx_ring_size; 2213c5aff182SThomas Petazzoni 2214c5aff182SThomas Petazzoni /* Allocate memory for TX descriptors */ 2215c5aff182SThomas Petazzoni txq->descs = dma_alloc_coherent(pp->dev->dev.parent, 2216c5aff182SThomas Petazzoni txq->size * MVNETA_DESC_ALIGNED_SIZE, 2217c5aff182SThomas Petazzoni &txq->descs_phys, GFP_KERNEL); 2218d0320f75SJoe Perches if (txq->descs == NULL) 2219c5aff182SThomas Petazzoni return -ENOMEM; 2220c5aff182SThomas Petazzoni 2221c5aff182SThomas Petazzoni /* Make sure descriptor address is cache line size aligned */ 2222c5aff182SThomas Petazzoni BUG_ON(txq->descs != 2223c5aff182SThomas Petazzoni PTR_ALIGN(txq->descs, MVNETA_CPU_D_CACHE_LINE_SIZE)); 2224c5aff182SThomas Petazzoni 2225c5aff182SThomas Petazzoni txq->last_desc = txq->size - 1; 2226c5aff182SThomas Petazzoni 2227c5aff182SThomas Petazzoni /* Set maximum bandwidth for enabled TXQs */ 2228c5aff182SThomas Petazzoni mvreg_write(pp, MVETH_TXQ_TOKEN_CFG_REG(txq->id), 0x03ffffff); 2229c5aff182SThomas Petazzoni mvreg_write(pp, MVETH_TXQ_TOKEN_COUNT_REG(txq->id), 0x3fffffff); 2230c5aff182SThomas Petazzoni 2231c5aff182SThomas Petazzoni /* Set Tx descriptors queue starting address */ 2232c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_TXQ_BASE_ADDR_REG(txq->id), txq->descs_phys); 2233c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_TXQ_SIZE_REG(txq->id), txq->size); 2234c5aff182SThomas Petazzoni 2235c5aff182SThomas Petazzoni txq->tx_skb = kmalloc(txq->size * sizeof(*txq->tx_skb), GFP_KERNEL); 2236c5aff182SThomas Petazzoni if (txq->tx_skb == NULL) { 2237c5aff182SThomas Petazzoni dma_free_coherent(pp->dev->dev.parent, 2238c5aff182SThomas Petazzoni txq->size * MVNETA_DESC_ALIGNED_SIZE, 2239c5aff182SThomas Petazzoni txq->descs, txq->descs_phys); 2240c5aff182SThomas Petazzoni return -ENOMEM; 2241c5aff182SThomas Petazzoni } 22422adb719dSEzequiel Garcia 22432adb719dSEzequiel Garcia /* Allocate DMA buffers for TSO MAC/IP/TCP headers */ 22442adb719dSEzequiel Garcia txq->tso_hdrs = dma_alloc_coherent(pp->dev->dev.parent, 22452adb719dSEzequiel Garcia txq->size * TSO_HEADER_SIZE, 22462adb719dSEzequiel Garcia &txq->tso_hdrs_phys, GFP_KERNEL); 22472adb719dSEzequiel Garcia if (txq->tso_hdrs == NULL) { 22482adb719dSEzequiel Garcia kfree(txq->tx_skb); 22492adb719dSEzequiel Garcia dma_free_coherent(pp->dev->dev.parent, 22502adb719dSEzequiel Garcia txq->size * MVNETA_DESC_ALIGNED_SIZE, 22512adb719dSEzequiel Garcia txq->descs, txq->descs_phys); 22522adb719dSEzequiel Garcia return -ENOMEM; 22532adb719dSEzequiel Garcia } 2254c5aff182SThomas Petazzoni mvneta_tx_done_pkts_coal_set(pp, txq, txq->done_pkts_coal); 2255c5aff182SThomas Petazzoni 2256c5aff182SThomas Petazzoni return 0; 2257c5aff182SThomas Petazzoni } 2258c5aff182SThomas Petazzoni 2259c5aff182SThomas Petazzoni /* Free allocated resources when mvneta_txq_init() fails to allocate memory*/ 2260c5aff182SThomas Petazzoni static void mvneta_txq_deinit(struct mvneta_port *pp, 2261c5aff182SThomas Petazzoni struct mvneta_tx_queue *txq) 2262c5aff182SThomas Petazzoni { 2263c5aff182SThomas Petazzoni kfree(txq->tx_skb); 2264c5aff182SThomas Petazzoni 22652adb719dSEzequiel Garcia if (txq->tso_hdrs) 22662adb719dSEzequiel Garcia dma_free_coherent(pp->dev->dev.parent, 22672adb719dSEzequiel Garcia txq->size * TSO_HEADER_SIZE, 22682adb719dSEzequiel Garcia txq->tso_hdrs, txq->tso_hdrs_phys); 2269c5aff182SThomas Petazzoni if (txq->descs) 2270c5aff182SThomas Petazzoni dma_free_coherent(pp->dev->dev.parent, 2271c5aff182SThomas Petazzoni txq->size * MVNETA_DESC_ALIGNED_SIZE, 2272c5aff182SThomas Petazzoni txq->descs, txq->descs_phys); 2273c5aff182SThomas Petazzoni 2274c5aff182SThomas Petazzoni txq->descs = NULL; 2275c5aff182SThomas Petazzoni txq->last_desc = 0; 2276c5aff182SThomas Petazzoni txq->next_desc_to_proc = 0; 2277c5aff182SThomas Petazzoni txq->descs_phys = 0; 2278c5aff182SThomas Petazzoni 2279c5aff182SThomas Petazzoni /* Set minimum bandwidth for disabled TXQs */ 2280c5aff182SThomas Petazzoni mvreg_write(pp, MVETH_TXQ_TOKEN_CFG_REG(txq->id), 0); 2281c5aff182SThomas Petazzoni mvreg_write(pp, MVETH_TXQ_TOKEN_COUNT_REG(txq->id), 0); 2282c5aff182SThomas Petazzoni 2283c5aff182SThomas Petazzoni /* Set Tx descriptors queue starting address and size */ 2284c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_TXQ_BASE_ADDR_REG(txq->id), 0); 2285c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_TXQ_SIZE_REG(txq->id), 0); 2286c5aff182SThomas Petazzoni } 2287c5aff182SThomas Petazzoni 2288c5aff182SThomas Petazzoni /* Cleanup all Tx queues */ 2289c5aff182SThomas Petazzoni static void mvneta_cleanup_txqs(struct mvneta_port *pp) 2290c5aff182SThomas Petazzoni { 2291c5aff182SThomas Petazzoni int queue; 2292c5aff182SThomas Petazzoni 2293c5aff182SThomas Petazzoni for (queue = 0; queue < txq_number; queue++) 2294c5aff182SThomas Petazzoni mvneta_txq_deinit(pp, &pp->txqs[queue]); 2295c5aff182SThomas Petazzoni } 2296c5aff182SThomas Petazzoni 2297c5aff182SThomas Petazzoni /* Cleanup all Rx queues */ 2298c5aff182SThomas Petazzoni static void mvneta_cleanup_rxqs(struct mvneta_port *pp) 2299c5aff182SThomas Petazzoni { 2300c5aff182SThomas Petazzoni int queue; 2301c5aff182SThomas Petazzoni 2302c5aff182SThomas Petazzoni for (queue = 0; queue < rxq_number; queue++) 2303c5aff182SThomas Petazzoni mvneta_rxq_deinit(pp, &pp->rxqs[queue]); 2304c5aff182SThomas Petazzoni } 2305c5aff182SThomas Petazzoni 2306c5aff182SThomas Petazzoni 2307c5aff182SThomas Petazzoni /* Init all Rx queues */ 2308c5aff182SThomas Petazzoni static int mvneta_setup_rxqs(struct mvneta_port *pp) 2309c5aff182SThomas Petazzoni { 2310c5aff182SThomas Petazzoni int queue; 2311c5aff182SThomas Petazzoni 2312c5aff182SThomas Petazzoni for (queue = 0; queue < rxq_number; queue++) { 2313c5aff182SThomas Petazzoni int err = mvneta_rxq_init(pp, &pp->rxqs[queue]); 2314c5aff182SThomas Petazzoni if (err) { 2315c5aff182SThomas Petazzoni netdev_err(pp->dev, "%s: can't create rxq=%d\n", 2316c5aff182SThomas Petazzoni __func__, queue); 2317c5aff182SThomas Petazzoni mvneta_cleanup_rxqs(pp); 2318c5aff182SThomas Petazzoni return err; 2319c5aff182SThomas Petazzoni } 2320c5aff182SThomas Petazzoni } 2321c5aff182SThomas Petazzoni 2322c5aff182SThomas Petazzoni return 0; 2323c5aff182SThomas Petazzoni } 2324c5aff182SThomas Petazzoni 2325c5aff182SThomas Petazzoni /* Init all tx queues */ 2326c5aff182SThomas Petazzoni static int mvneta_setup_txqs(struct mvneta_port *pp) 2327c5aff182SThomas Petazzoni { 2328c5aff182SThomas Petazzoni int queue; 2329c5aff182SThomas Petazzoni 2330c5aff182SThomas Petazzoni for (queue = 0; queue < txq_number; queue++) { 2331c5aff182SThomas Petazzoni int err = mvneta_txq_init(pp, &pp->txqs[queue]); 2332c5aff182SThomas Petazzoni if (err) { 2333c5aff182SThomas Petazzoni netdev_err(pp->dev, "%s: can't create txq=%d\n", 2334c5aff182SThomas Petazzoni __func__, queue); 2335c5aff182SThomas Petazzoni mvneta_cleanup_txqs(pp); 2336c5aff182SThomas Petazzoni return err; 2337c5aff182SThomas Petazzoni } 2338c5aff182SThomas Petazzoni } 2339c5aff182SThomas Petazzoni 2340c5aff182SThomas Petazzoni return 0; 2341c5aff182SThomas Petazzoni } 2342c5aff182SThomas Petazzoni 2343c5aff182SThomas Petazzoni static void mvneta_start_dev(struct mvneta_port *pp) 2344c5aff182SThomas Petazzoni { 2345c5aff182SThomas Petazzoni mvneta_max_rx_size_set(pp, pp->pkt_size); 2346c5aff182SThomas Petazzoni mvneta_txq_max_tx_size_set(pp, pp->pkt_size); 2347c5aff182SThomas Petazzoni 2348c5aff182SThomas Petazzoni /* start the Rx/Tx activity */ 2349c5aff182SThomas Petazzoni mvneta_port_enable(pp); 2350c5aff182SThomas Petazzoni 2351c5aff182SThomas Petazzoni /* Enable polling on the port */ 2352c5aff182SThomas Petazzoni napi_enable(&pp->napi); 2353c5aff182SThomas Petazzoni 2354c5aff182SThomas Petazzoni /* Unmask interrupts */ 2355c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_INTR_NEW_MASK, 235671f6d1b3Swilly tarreau MVNETA_RX_INTR_MASK(rxq_number) | MVNETA_TX_INTR_MASK(txq_number)); 2357c5aff182SThomas Petazzoni 2358c5aff182SThomas Petazzoni phy_start(pp->phy_dev); 2359c5aff182SThomas Petazzoni netif_tx_start_all_queues(pp->dev); 2360c5aff182SThomas Petazzoni } 2361c5aff182SThomas Petazzoni 2362c5aff182SThomas Petazzoni static void mvneta_stop_dev(struct mvneta_port *pp) 2363c5aff182SThomas Petazzoni { 2364c5aff182SThomas Petazzoni phy_stop(pp->phy_dev); 2365c5aff182SThomas Petazzoni 2366c5aff182SThomas Petazzoni napi_disable(&pp->napi); 2367c5aff182SThomas Petazzoni 2368c5aff182SThomas Petazzoni netif_carrier_off(pp->dev); 2369c5aff182SThomas Petazzoni 2370c5aff182SThomas Petazzoni mvneta_port_down(pp); 2371c5aff182SThomas Petazzoni netif_tx_stop_all_queues(pp->dev); 2372c5aff182SThomas Petazzoni 2373c5aff182SThomas Petazzoni /* Stop the port activity */ 2374c5aff182SThomas Petazzoni mvneta_port_disable(pp); 2375c5aff182SThomas Petazzoni 2376c5aff182SThomas Petazzoni /* Clear all ethernet port interrupts */ 2377c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_INTR_MISC_CAUSE, 0); 2378c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_INTR_OLD_CAUSE, 0); 2379c5aff182SThomas Petazzoni 2380c5aff182SThomas Petazzoni /* Mask all ethernet port interrupts */ 2381c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_INTR_NEW_MASK, 0); 2382c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_INTR_OLD_MASK, 0); 2383c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_INTR_MISC_MASK, 0); 2384c5aff182SThomas Petazzoni 2385c5aff182SThomas Petazzoni mvneta_tx_reset(pp); 2386c5aff182SThomas Petazzoni mvneta_rx_reset(pp); 2387c5aff182SThomas Petazzoni } 2388c5aff182SThomas Petazzoni 2389c5aff182SThomas Petazzoni /* Return positive if MTU is valid */ 2390c5aff182SThomas Petazzoni static int mvneta_check_mtu_valid(struct net_device *dev, int mtu) 2391c5aff182SThomas Petazzoni { 2392c5aff182SThomas Petazzoni if (mtu < 68) { 2393c5aff182SThomas Petazzoni netdev_err(dev, "cannot change mtu to less than 68\n"); 2394c5aff182SThomas Petazzoni return -EINVAL; 2395c5aff182SThomas Petazzoni } 2396c5aff182SThomas Petazzoni 2397c5aff182SThomas Petazzoni /* 9676 == 9700 - 20 and rounding to 8 */ 2398c5aff182SThomas Petazzoni if (mtu > 9676) { 2399c5aff182SThomas Petazzoni netdev_info(dev, "Illegal MTU value %d, round to 9676\n", mtu); 2400c5aff182SThomas Petazzoni mtu = 9676; 2401c5aff182SThomas Petazzoni } 2402c5aff182SThomas Petazzoni 2403c5aff182SThomas Petazzoni if (!IS_ALIGNED(MVNETA_RX_PKT_SIZE(mtu), 8)) { 2404c5aff182SThomas Petazzoni netdev_info(dev, "Illegal MTU value %d, rounding to %d\n", 2405c5aff182SThomas Petazzoni mtu, ALIGN(MVNETA_RX_PKT_SIZE(mtu), 8)); 2406c5aff182SThomas Petazzoni mtu = ALIGN(MVNETA_RX_PKT_SIZE(mtu), 8); 2407c5aff182SThomas Petazzoni } 2408c5aff182SThomas Petazzoni 2409c5aff182SThomas Petazzoni return mtu; 2410c5aff182SThomas Petazzoni } 2411c5aff182SThomas Petazzoni 2412c5aff182SThomas Petazzoni /* Change the device mtu */ 2413c5aff182SThomas Petazzoni static int mvneta_change_mtu(struct net_device *dev, int mtu) 2414c5aff182SThomas Petazzoni { 2415c5aff182SThomas Petazzoni struct mvneta_port *pp = netdev_priv(dev); 2416c5aff182SThomas Petazzoni int ret; 2417c5aff182SThomas Petazzoni 2418c5aff182SThomas Petazzoni mtu = mvneta_check_mtu_valid(dev, mtu); 2419c5aff182SThomas Petazzoni if (mtu < 0) 2420c5aff182SThomas Petazzoni return -EINVAL; 2421c5aff182SThomas Petazzoni 2422c5aff182SThomas Petazzoni dev->mtu = mtu; 2423c5aff182SThomas Petazzoni 2424c5aff182SThomas Petazzoni if (!netif_running(dev)) 2425c5aff182SThomas Petazzoni return 0; 2426c5aff182SThomas Petazzoni 24276a20c175SThomas Petazzoni /* The interface is running, so we have to force a 2428c5aff182SThomas Petazzoni * reallocation of the RXQs 2429c5aff182SThomas Petazzoni */ 2430c5aff182SThomas Petazzoni mvneta_stop_dev(pp); 2431c5aff182SThomas Petazzoni 2432c5aff182SThomas Petazzoni mvneta_cleanup_txqs(pp); 2433c5aff182SThomas Petazzoni mvneta_cleanup_rxqs(pp); 2434c5aff182SThomas Petazzoni 2435c5aff182SThomas Petazzoni pp->pkt_size = MVNETA_RX_PKT_SIZE(pp->dev->mtu); 24368ec2cd48Swilly tarreau pp->frag_size = SKB_DATA_ALIGN(MVNETA_RX_BUF_SIZE(pp->pkt_size)) + 24378ec2cd48Swilly tarreau SKB_DATA_ALIGN(sizeof(struct skb_shared_info)); 2438c5aff182SThomas Petazzoni 2439c5aff182SThomas Petazzoni ret = mvneta_setup_rxqs(pp); 2440c5aff182SThomas Petazzoni if (ret) { 2441c5aff182SThomas Petazzoni netdev_err(pp->dev, "unable to setup rxqs after MTU change\n"); 2442c5aff182SThomas Petazzoni return ret; 2443c5aff182SThomas Petazzoni } 2444c5aff182SThomas Petazzoni 2445c5aff182SThomas Petazzoni mvneta_setup_txqs(pp); 2446c5aff182SThomas Petazzoni 2447c5aff182SThomas Petazzoni mvneta_start_dev(pp); 2448c5aff182SThomas Petazzoni mvneta_port_up(pp); 2449c5aff182SThomas Petazzoni 2450c5aff182SThomas Petazzoni return 0; 2451c5aff182SThomas Petazzoni } 2452c5aff182SThomas Petazzoni 24538cc3e439SThomas Petazzoni /* Get mac address */ 24548cc3e439SThomas Petazzoni static void mvneta_get_mac_addr(struct mvneta_port *pp, unsigned char *addr) 24558cc3e439SThomas Petazzoni { 24568cc3e439SThomas Petazzoni u32 mac_addr_l, mac_addr_h; 24578cc3e439SThomas Petazzoni 24588cc3e439SThomas Petazzoni mac_addr_l = mvreg_read(pp, MVNETA_MAC_ADDR_LOW); 24598cc3e439SThomas Petazzoni mac_addr_h = mvreg_read(pp, MVNETA_MAC_ADDR_HIGH); 24608cc3e439SThomas Petazzoni addr[0] = (mac_addr_h >> 24) & 0xFF; 24618cc3e439SThomas Petazzoni addr[1] = (mac_addr_h >> 16) & 0xFF; 24628cc3e439SThomas Petazzoni addr[2] = (mac_addr_h >> 8) & 0xFF; 24638cc3e439SThomas Petazzoni addr[3] = mac_addr_h & 0xFF; 24648cc3e439SThomas Petazzoni addr[4] = (mac_addr_l >> 8) & 0xFF; 24658cc3e439SThomas Petazzoni addr[5] = mac_addr_l & 0xFF; 24668cc3e439SThomas Petazzoni } 24678cc3e439SThomas Petazzoni 2468c5aff182SThomas Petazzoni /* Handle setting mac address */ 2469c5aff182SThomas Petazzoni static int mvneta_set_mac_addr(struct net_device *dev, void *addr) 2470c5aff182SThomas Petazzoni { 2471c5aff182SThomas Petazzoni struct mvneta_port *pp = netdev_priv(dev); 2472c5aff182SThomas Petazzoni u8 *mac = addr + 2; 2473c5aff182SThomas Petazzoni int i; 2474c5aff182SThomas Petazzoni 2475c5aff182SThomas Petazzoni if (netif_running(dev)) 2476c5aff182SThomas Petazzoni return -EBUSY; 2477c5aff182SThomas Petazzoni 2478c5aff182SThomas Petazzoni /* Remove previous address table entry */ 2479c5aff182SThomas Petazzoni mvneta_mac_addr_set(pp, dev->dev_addr, -1); 2480c5aff182SThomas Petazzoni 2481c5aff182SThomas Petazzoni /* Set new addr in hw */ 2482c5aff182SThomas Petazzoni mvneta_mac_addr_set(pp, mac, rxq_def); 2483c5aff182SThomas Petazzoni 2484c5aff182SThomas Petazzoni /* Set addr in the device */ 2485c5aff182SThomas Petazzoni for (i = 0; i < ETH_ALEN; i++) 2486c5aff182SThomas Petazzoni dev->dev_addr[i] = mac[i]; 2487c5aff182SThomas Petazzoni 2488c5aff182SThomas Petazzoni return 0; 2489c5aff182SThomas Petazzoni } 2490c5aff182SThomas Petazzoni 2491c5aff182SThomas Petazzoni static void mvneta_adjust_link(struct net_device *ndev) 2492c5aff182SThomas Petazzoni { 2493c5aff182SThomas Petazzoni struct mvneta_port *pp = netdev_priv(ndev); 2494c5aff182SThomas Petazzoni struct phy_device *phydev = pp->phy_dev; 2495c5aff182SThomas Petazzoni int status_change = 0; 2496c5aff182SThomas Petazzoni 2497c5aff182SThomas Petazzoni if (phydev->link) { 2498c5aff182SThomas Petazzoni if ((pp->speed != phydev->speed) || 2499c5aff182SThomas Petazzoni (pp->duplex != phydev->duplex)) { 2500c5aff182SThomas Petazzoni u32 val; 2501c5aff182SThomas Petazzoni 2502c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG); 2503c5aff182SThomas Petazzoni val &= ~(MVNETA_GMAC_CONFIG_MII_SPEED | 2504c5aff182SThomas Petazzoni MVNETA_GMAC_CONFIG_GMII_SPEED | 250571408602SThomas Petazzoni MVNETA_GMAC_CONFIG_FULL_DUPLEX | 250671408602SThomas Petazzoni MVNETA_GMAC_AN_SPEED_EN | 250771408602SThomas Petazzoni MVNETA_GMAC_AN_DUPLEX_EN); 2508c5aff182SThomas Petazzoni 2509c5aff182SThomas Petazzoni if (phydev->duplex) 2510c5aff182SThomas Petazzoni val |= MVNETA_GMAC_CONFIG_FULL_DUPLEX; 2511c5aff182SThomas Petazzoni 2512c5aff182SThomas Petazzoni if (phydev->speed == SPEED_1000) 2513c5aff182SThomas Petazzoni val |= MVNETA_GMAC_CONFIG_GMII_SPEED; 2514c5aff182SThomas Petazzoni else 2515c5aff182SThomas Petazzoni val |= MVNETA_GMAC_CONFIG_MII_SPEED; 2516c5aff182SThomas Petazzoni 2517c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val); 2518c5aff182SThomas Petazzoni 2519c5aff182SThomas Petazzoni pp->duplex = phydev->duplex; 2520c5aff182SThomas Petazzoni pp->speed = phydev->speed; 2521c5aff182SThomas Petazzoni } 2522c5aff182SThomas Petazzoni } 2523c5aff182SThomas Petazzoni 2524c5aff182SThomas Petazzoni if (phydev->link != pp->link) { 2525c5aff182SThomas Petazzoni if (!phydev->link) { 2526c5aff182SThomas Petazzoni pp->duplex = -1; 2527c5aff182SThomas Petazzoni pp->speed = 0; 2528c5aff182SThomas Petazzoni } 2529c5aff182SThomas Petazzoni 2530c5aff182SThomas Petazzoni pp->link = phydev->link; 2531c5aff182SThomas Petazzoni status_change = 1; 2532c5aff182SThomas Petazzoni } 2533c5aff182SThomas Petazzoni 2534c5aff182SThomas Petazzoni if (status_change) { 2535c5aff182SThomas Petazzoni if (phydev->link) { 2536c5aff182SThomas Petazzoni u32 val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG); 2537c5aff182SThomas Petazzoni val |= (MVNETA_GMAC_FORCE_LINK_PASS | 2538c5aff182SThomas Petazzoni MVNETA_GMAC_FORCE_LINK_DOWN); 2539c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val); 2540c5aff182SThomas Petazzoni mvneta_port_up(pp); 2541c5aff182SThomas Petazzoni netdev_info(pp->dev, "link up\n"); 2542c5aff182SThomas Petazzoni } else { 2543c5aff182SThomas Petazzoni mvneta_port_down(pp); 2544c5aff182SThomas Petazzoni netdev_info(pp->dev, "link down\n"); 2545c5aff182SThomas Petazzoni } 2546c5aff182SThomas Petazzoni } 2547c5aff182SThomas Petazzoni } 2548c5aff182SThomas Petazzoni 2549c5aff182SThomas Petazzoni static int mvneta_mdio_probe(struct mvneta_port *pp) 2550c5aff182SThomas Petazzoni { 2551c5aff182SThomas Petazzoni struct phy_device *phy_dev; 2552c5aff182SThomas Petazzoni 2553c5aff182SThomas Petazzoni phy_dev = of_phy_connect(pp->dev, pp->phy_node, mvneta_adjust_link, 0, 2554c5aff182SThomas Petazzoni pp->phy_interface); 2555c5aff182SThomas Petazzoni if (!phy_dev) { 2556c5aff182SThomas Petazzoni netdev_err(pp->dev, "could not find the PHY\n"); 2557c5aff182SThomas Petazzoni return -ENODEV; 2558c5aff182SThomas Petazzoni } 2559c5aff182SThomas Petazzoni 2560c5aff182SThomas Petazzoni phy_dev->supported &= PHY_GBIT_FEATURES; 2561c5aff182SThomas Petazzoni phy_dev->advertising = phy_dev->supported; 2562c5aff182SThomas Petazzoni 2563c5aff182SThomas Petazzoni pp->phy_dev = phy_dev; 2564c5aff182SThomas Petazzoni pp->link = 0; 2565c5aff182SThomas Petazzoni pp->duplex = 0; 2566c5aff182SThomas Petazzoni pp->speed = 0; 2567c5aff182SThomas Petazzoni 2568c5aff182SThomas Petazzoni return 0; 2569c5aff182SThomas Petazzoni } 2570c5aff182SThomas Petazzoni 2571c5aff182SThomas Petazzoni static void mvneta_mdio_remove(struct mvneta_port *pp) 2572c5aff182SThomas Petazzoni { 2573c5aff182SThomas Petazzoni phy_disconnect(pp->phy_dev); 2574c5aff182SThomas Petazzoni pp->phy_dev = NULL; 2575c5aff182SThomas Petazzoni } 2576c5aff182SThomas Petazzoni 2577c5aff182SThomas Petazzoni static int mvneta_open(struct net_device *dev) 2578c5aff182SThomas Petazzoni { 2579c5aff182SThomas Petazzoni struct mvneta_port *pp = netdev_priv(dev); 2580c5aff182SThomas Petazzoni int ret; 2581c5aff182SThomas Petazzoni 2582c5aff182SThomas Petazzoni mvneta_mac_addr_set(pp, dev->dev_addr, rxq_def); 2583c5aff182SThomas Petazzoni 2584c5aff182SThomas Petazzoni pp->pkt_size = MVNETA_RX_PKT_SIZE(pp->dev->mtu); 25858ec2cd48Swilly tarreau pp->frag_size = SKB_DATA_ALIGN(MVNETA_RX_BUF_SIZE(pp->pkt_size)) + 25868ec2cd48Swilly tarreau SKB_DATA_ALIGN(sizeof(struct skb_shared_info)); 2587c5aff182SThomas Petazzoni 2588c5aff182SThomas Petazzoni ret = mvneta_setup_rxqs(pp); 2589c5aff182SThomas Petazzoni if (ret) 2590c5aff182SThomas Petazzoni return ret; 2591c5aff182SThomas Petazzoni 2592c5aff182SThomas Petazzoni ret = mvneta_setup_txqs(pp); 2593c5aff182SThomas Petazzoni if (ret) 2594c5aff182SThomas Petazzoni goto err_cleanup_rxqs; 2595c5aff182SThomas Petazzoni 2596c5aff182SThomas Petazzoni /* Connect to port interrupt line */ 2597c5aff182SThomas Petazzoni ret = request_irq(pp->dev->irq, mvneta_isr, 0, 2598c5aff182SThomas Petazzoni MVNETA_DRIVER_NAME, pp); 2599c5aff182SThomas Petazzoni if (ret) { 2600c5aff182SThomas Petazzoni netdev_err(pp->dev, "cannot request irq %d\n", pp->dev->irq); 2601c5aff182SThomas Petazzoni goto err_cleanup_txqs; 2602c5aff182SThomas Petazzoni } 2603c5aff182SThomas Petazzoni 2604c5aff182SThomas Petazzoni /* In default link is down */ 2605c5aff182SThomas Petazzoni netif_carrier_off(pp->dev); 2606c5aff182SThomas Petazzoni 2607c5aff182SThomas Petazzoni ret = mvneta_mdio_probe(pp); 2608c5aff182SThomas Petazzoni if (ret < 0) { 2609c5aff182SThomas Petazzoni netdev_err(dev, "cannot probe MDIO bus\n"); 2610c5aff182SThomas Petazzoni goto err_free_irq; 2611c5aff182SThomas Petazzoni } 2612c5aff182SThomas Petazzoni 2613c5aff182SThomas Petazzoni mvneta_start_dev(pp); 2614c5aff182SThomas Petazzoni 2615c5aff182SThomas Petazzoni return 0; 2616c5aff182SThomas Petazzoni 2617c5aff182SThomas Petazzoni err_free_irq: 2618c5aff182SThomas Petazzoni free_irq(pp->dev->irq, pp); 2619c5aff182SThomas Petazzoni err_cleanup_txqs: 2620c5aff182SThomas Petazzoni mvneta_cleanup_txqs(pp); 2621c5aff182SThomas Petazzoni err_cleanup_rxqs: 2622c5aff182SThomas Petazzoni mvneta_cleanup_rxqs(pp); 2623c5aff182SThomas Petazzoni return ret; 2624c5aff182SThomas Petazzoni } 2625c5aff182SThomas Petazzoni 2626c5aff182SThomas Petazzoni /* Stop the port, free port interrupt line */ 2627c5aff182SThomas Petazzoni static int mvneta_stop(struct net_device *dev) 2628c5aff182SThomas Petazzoni { 2629c5aff182SThomas Petazzoni struct mvneta_port *pp = netdev_priv(dev); 2630c5aff182SThomas Petazzoni 2631c5aff182SThomas Petazzoni mvneta_stop_dev(pp); 2632c5aff182SThomas Petazzoni mvneta_mdio_remove(pp); 2633c5aff182SThomas Petazzoni free_irq(dev->irq, pp); 2634c5aff182SThomas Petazzoni mvneta_cleanup_rxqs(pp); 2635c5aff182SThomas Petazzoni mvneta_cleanup_txqs(pp); 2636c5aff182SThomas Petazzoni 2637c5aff182SThomas Petazzoni return 0; 2638c5aff182SThomas Petazzoni } 2639c5aff182SThomas Petazzoni 264015f59456SThomas Petazzoni static int mvneta_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) 264115f59456SThomas Petazzoni { 264215f59456SThomas Petazzoni struct mvneta_port *pp = netdev_priv(dev); 264315f59456SThomas Petazzoni int ret; 264415f59456SThomas Petazzoni 264515f59456SThomas Petazzoni if (!pp->phy_dev) 264615f59456SThomas Petazzoni return -ENOTSUPP; 264715f59456SThomas Petazzoni 264815f59456SThomas Petazzoni ret = phy_mii_ioctl(pp->phy_dev, ifr, cmd); 264915f59456SThomas Petazzoni if (!ret) 265015f59456SThomas Petazzoni mvneta_adjust_link(dev); 265115f59456SThomas Petazzoni 265215f59456SThomas Petazzoni return ret; 265315f59456SThomas Petazzoni } 265415f59456SThomas Petazzoni 2655c5aff182SThomas Petazzoni /* Ethtool methods */ 2656c5aff182SThomas Petazzoni 2657c5aff182SThomas Petazzoni /* Get settings (phy address, speed) for ethtools */ 2658c5aff182SThomas Petazzoni int mvneta_ethtool_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) 2659c5aff182SThomas Petazzoni { 2660c5aff182SThomas Petazzoni struct mvneta_port *pp = netdev_priv(dev); 2661c5aff182SThomas Petazzoni 2662c5aff182SThomas Petazzoni if (!pp->phy_dev) 2663c5aff182SThomas Petazzoni return -ENODEV; 2664c5aff182SThomas Petazzoni 2665c5aff182SThomas Petazzoni return phy_ethtool_gset(pp->phy_dev, cmd); 2666c5aff182SThomas Petazzoni } 2667c5aff182SThomas Petazzoni 2668c5aff182SThomas Petazzoni /* Set settings (phy address, speed) for ethtools */ 2669c5aff182SThomas Petazzoni int mvneta_ethtool_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) 2670c5aff182SThomas Petazzoni { 2671c5aff182SThomas Petazzoni struct mvneta_port *pp = netdev_priv(dev); 2672c5aff182SThomas Petazzoni 2673c5aff182SThomas Petazzoni if (!pp->phy_dev) 2674c5aff182SThomas Petazzoni return -ENODEV; 2675c5aff182SThomas Petazzoni 2676c5aff182SThomas Petazzoni return phy_ethtool_sset(pp->phy_dev, cmd); 2677c5aff182SThomas Petazzoni } 2678c5aff182SThomas Petazzoni 2679c5aff182SThomas Petazzoni /* Set interrupt coalescing for ethtools */ 2680c5aff182SThomas Petazzoni static int mvneta_ethtool_set_coalesce(struct net_device *dev, 2681c5aff182SThomas Petazzoni struct ethtool_coalesce *c) 2682c5aff182SThomas Petazzoni { 2683c5aff182SThomas Petazzoni struct mvneta_port *pp = netdev_priv(dev); 2684c5aff182SThomas Petazzoni int queue; 2685c5aff182SThomas Petazzoni 2686c5aff182SThomas Petazzoni for (queue = 0; queue < rxq_number; queue++) { 2687c5aff182SThomas Petazzoni struct mvneta_rx_queue *rxq = &pp->rxqs[queue]; 2688c5aff182SThomas Petazzoni rxq->time_coal = c->rx_coalesce_usecs; 2689c5aff182SThomas Petazzoni rxq->pkts_coal = c->rx_max_coalesced_frames; 2690c5aff182SThomas Petazzoni mvneta_rx_pkts_coal_set(pp, rxq, rxq->pkts_coal); 2691c5aff182SThomas Petazzoni mvneta_rx_time_coal_set(pp, rxq, rxq->time_coal); 2692c5aff182SThomas Petazzoni } 2693c5aff182SThomas Petazzoni 2694c5aff182SThomas Petazzoni for (queue = 0; queue < txq_number; queue++) { 2695c5aff182SThomas Petazzoni struct mvneta_tx_queue *txq = &pp->txqs[queue]; 2696c5aff182SThomas Petazzoni txq->done_pkts_coal = c->tx_max_coalesced_frames; 2697c5aff182SThomas Petazzoni mvneta_tx_done_pkts_coal_set(pp, txq, txq->done_pkts_coal); 2698c5aff182SThomas Petazzoni } 2699c5aff182SThomas Petazzoni 2700c5aff182SThomas Petazzoni return 0; 2701c5aff182SThomas Petazzoni } 2702c5aff182SThomas Petazzoni 2703c5aff182SThomas Petazzoni /* get coalescing for ethtools */ 2704c5aff182SThomas Petazzoni static int mvneta_ethtool_get_coalesce(struct net_device *dev, 2705c5aff182SThomas Petazzoni struct ethtool_coalesce *c) 2706c5aff182SThomas Petazzoni { 2707c5aff182SThomas Petazzoni struct mvneta_port *pp = netdev_priv(dev); 2708c5aff182SThomas Petazzoni 2709c5aff182SThomas Petazzoni c->rx_coalesce_usecs = pp->rxqs[0].time_coal; 2710c5aff182SThomas Petazzoni c->rx_max_coalesced_frames = pp->rxqs[0].pkts_coal; 2711c5aff182SThomas Petazzoni 2712c5aff182SThomas Petazzoni c->tx_max_coalesced_frames = pp->txqs[0].done_pkts_coal; 2713c5aff182SThomas Petazzoni return 0; 2714c5aff182SThomas Petazzoni } 2715c5aff182SThomas Petazzoni 2716c5aff182SThomas Petazzoni 2717c5aff182SThomas Petazzoni static void mvneta_ethtool_get_drvinfo(struct net_device *dev, 2718c5aff182SThomas Petazzoni struct ethtool_drvinfo *drvinfo) 2719c5aff182SThomas Petazzoni { 2720c5aff182SThomas Petazzoni strlcpy(drvinfo->driver, MVNETA_DRIVER_NAME, 2721c5aff182SThomas Petazzoni sizeof(drvinfo->driver)); 2722c5aff182SThomas Petazzoni strlcpy(drvinfo->version, MVNETA_DRIVER_VERSION, 2723c5aff182SThomas Petazzoni sizeof(drvinfo->version)); 2724c5aff182SThomas Petazzoni strlcpy(drvinfo->bus_info, dev_name(&dev->dev), 2725c5aff182SThomas Petazzoni sizeof(drvinfo->bus_info)); 2726c5aff182SThomas Petazzoni } 2727c5aff182SThomas Petazzoni 2728c5aff182SThomas Petazzoni 2729c5aff182SThomas Petazzoni static void mvneta_ethtool_get_ringparam(struct net_device *netdev, 2730c5aff182SThomas Petazzoni struct ethtool_ringparam *ring) 2731c5aff182SThomas Petazzoni { 2732c5aff182SThomas Petazzoni struct mvneta_port *pp = netdev_priv(netdev); 2733c5aff182SThomas Petazzoni 2734c5aff182SThomas Petazzoni ring->rx_max_pending = MVNETA_MAX_RXD; 2735c5aff182SThomas Petazzoni ring->tx_max_pending = MVNETA_MAX_TXD; 2736c5aff182SThomas Petazzoni ring->rx_pending = pp->rx_ring_size; 2737c5aff182SThomas Petazzoni ring->tx_pending = pp->tx_ring_size; 2738c5aff182SThomas Petazzoni } 2739c5aff182SThomas Petazzoni 2740c5aff182SThomas Petazzoni static int mvneta_ethtool_set_ringparam(struct net_device *dev, 2741c5aff182SThomas Petazzoni struct ethtool_ringparam *ring) 2742c5aff182SThomas Petazzoni { 2743c5aff182SThomas Petazzoni struct mvneta_port *pp = netdev_priv(dev); 2744c5aff182SThomas Petazzoni 2745c5aff182SThomas Petazzoni if ((ring->rx_pending == 0) || (ring->tx_pending == 0)) 2746c5aff182SThomas Petazzoni return -EINVAL; 2747c5aff182SThomas Petazzoni pp->rx_ring_size = ring->rx_pending < MVNETA_MAX_RXD ? 2748c5aff182SThomas Petazzoni ring->rx_pending : MVNETA_MAX_RXD; 2749c5aff182SThomas Petazzoni pp->tx_ring_size = ring->tx_pending < MVNETA_MAX_TXD ? 2750c5aff182SThomas Petazzoni ring->tx_pending : MVNETA_MAX_TXD; 2751c5aff182SThomas Petazzoni 2752c5aff182SThomas Petazzoni if (netif_running(dev)) { 2753c5aff182SThomas Petazzoni mvneta_stop(dev); 2754c5aff182SThomas Petazzoni if (mvneta_open(dev)) { 2755c5aff182SThomas Petazzoni netdev_err(dev, 2756c5aff182SThomas Petazzoni "error on opening device after ring param change\n"); 2757c5aff182SThomas Petazzoni return -ENOMEM; 2758c5aff182SThomas Petazzoni } 2759c5aff182SThomas Petazzoni } 2760c5aff182SThomas Petazzoni 2761c5aff182SThomas Petazzoni return 0; 2762c5aff182SThomas Petazzoni } 2763c5aff182SThomas Petazzoni 2764c5aff182SThomas Petazzoni static const struct net_device_ops mvneta_netdev_ops = { 2765c5aff182SThomas Petazzoni .ndo_open = mvneta_open, 2766c5aff182SThomas Petazzoni .ndo_stop = mvneta_stop, 2767c5aff182SThomas Petazzoni .ndo_start_xmit = mvneta_tx, 2768c5aff182SThomas Petazzoni .ndo_set_rx_mode = mvneta_set_rx_mode, 2769c5aff182SThomas Petazzoni .ndo_set_mac_address = mvneta_set_mac_addr, 2770c5aff182SThomas Petazzoni .ndo_change_mtu = mvneta_change_mtu, 2771c5aff182SThomas Petazzoni .ndo_get_stats64 = mvneta_get_stats64, 277215f59456SThomas Petazzoni .ndo_do_ioctl = mvneta_ioctl, 2773c5aff182SThomas Petazzoni }; 2774c5aff182SThomas Petazzoni 2775c5aff182SThomas Petazzoni const struct ethtool_ops mvneta_eth_tool_ops = { 2776c5aff182SThomas Petazzoni .get_link = ethtool_op_get_link, 2777c5aff182SThomas Petazzoni .get_settings = mvneta_ethtool_get_settings, 2778c5aff182SThomas Petazzoni .set_settings = mvneta_ethtool_set_settings, 2779c5aff182SThomas Petazzoni .set_coalesce = mvneta_ethtool_set_coalesce, 2780c5aff182SThomas Petazzoni .get_coalesce = mvneta_ethtool_get_coalesce, 2781c5aff182SThomas Petazzoni .get_drvinfo = mvneta_ethtool_get_drvinfo, 2782c5aff182SThomas Petazzoni .get_ringparam = mvneta_ethtool_get_ringparam, 2783c5aff182SThomas Petazzoni .set_ringparam = mvneta_ethtool_set_ringparam, 2784c5aff182SThomas Petazzoni }; 2785c5aff182SThomas Petazzoni 2786c5aff182SThomas Petazzoni /* Initialize hw */ 278703ce758eSGreg KH static int mvneta_init(struct mvneta_port *pp, int phy_addr) 2788c5aff182SThomas Petazzoni { 2789c5aff182SThomas Petazzoni int queue; 2790c5aff182SThomas Petazzoni 2791c5aff182SThomas Petazzoni /* Disable port */ 2792c5aff182SThomas Petazzoni mvneta_port_disable(pp); 2793c5aff182SThomas Petazzoni 2794c5aff182SThomas Petazzoni /* Set port default values */ 2795c5aff182SThomas Petazzoni mvneta_defaults_set(pp); 2796c5aff182SThomas Petazzoni 2797c5aff182SThomas Petazzoni pp->txqs = kzalloc(txq_number * sizeof(struct mvneta_tx_queue), 2798c5aff182SThomas Petazzoni GFP_KERNEL); 2799c5aff182SThomas Petazzoni if (!pp->txqs) 2800c5aff182SThomas Petazzoni return -ENOMEM; 2801c5aff182SThomas Petazzoni 2802c5aff182SThomas Petazzoni /* Initialize TX descriptor rings */ 2803c5aff182SThomas Petazzoni for (queue = 0; queue < txq_number; queue++) { 2804c5aff182SThomas Petazzoni struct mvneta_tx_queue *txq = &pp->txqs[queue]; 2805c5aff182SThomas Petazzoni txq->id = queue; 2806c5aff182SThomas Petazzoni txq->size = pp->tx_ring_size; 2807c5aff182SThomas Petazzoni txq->done_pkts_coal = MVNETA_TXDONE_COAL_PKTS; 2808c5aff182SThomas Petazzoni } 2809c5aff182SThomas Petazzoni 2810c5aff182SThomas Petazzoni pp->rxqs = kzalloc(rxq_number * sizeof(struct mvneta_rx_queue), 2811c5aff182SThomas Petazzoni GFP_KERNEL); 2812c5aff182SThomas Petazzoni if (!pp->rxqs) { 2813c5aff182SThomas Petazzoni kfree(pp->txqs); 2814c5aff182SThomas Petazzoni return -ENOMEM; 2815c5aff182SThomas Petazzoni } 2816c5aff182SThomas Petazzoni 2817c5aff182SThomas Petazzoni /* Create Rx descriptor rings */ 2818c5aff182SThomas Petazzoni for (queue = 0; queue < rxq_number; queue++) { 2819c5aff182SThomas Petazzoni struct mvneta_rx_queue *rxq = &pp->rxqs[queue]; 2820c5aff182SThomas Petazzoni rxq->id = queue; 2821c5aff182SThomas Petazzoni rxq->size = pp->rx_ring_size; 2822c5aff182SThomas Petazzoni rxq->pkts_coal = MVNETA_RX_COAL_PKTS; 2823c5aff182SThomas Petazzoni rxq->time_coal = MVNETA_RX_COAL_USEC; 2824c5aff182SThomas Petazzoni } 2825c5aff182SThomas Petazzoni 2826c5aff182SThomas Petazzoni return 0; 2827c5aff182SThomas Petazzoni } 2828c5aff182SThomas Petazzoni 282970eeaf98SThomas Petazzoni static void mvneta_deinit(struct mvneta_port *pp) 2830c5aff182SThomas Petazzoni { 2831c5aff182SThomas Petazzoni kfree(pp->txqs); 2832c5aff182SThomas Petazzoni kfree(pp->rxqs); 2833c5aff182SThomas Petazzoni } 2834c5aff182SThomas Petazzoni 2835c5aff182SThomas Petazzoni /* platform glue : initialize decoding windows */ 283603ce758eSGreg KH static void mvneta_conf_mbus_windows(struct mvneta_port *pp, 2837c5aff182SThomas Petazzoni const struct mbus_dram_target_info *dram) 2838c5aff182SThomas Petazzoni { 2839c5aff182SThomas Petazzoni u32 win_enable; 2840c5aff182SThomas Petazzoni u32 win_protect; 2841c5aff182SThomas Petazzoni int i; 2842c5aff182SThomas Petazzoni 2843c5aff182SThomas Petazzoni for (i = 0; i < 6; i++) { 2844c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_WIN_BASE(i), 0); 2845c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_WIN_SIZE(i), 0); 2846c5aff182SThomas Petazzoni 2847c5aff182SThomas Petazzoni if (i < 4) 2848c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_WIN_REMAP(i), 0); 2849c5aff182SThomas Petazzoni } 2850c5aff182SThomas Petazzoni 2851c5aff182SThomas Petazzoni win_enable = 0x3f; 2852c5aff182SThomas Petazzoni win_protect = 0; 2853c5aff182SThomas Petazzoni 2854c5aff182SThomas Petazzoni for (i = 0; i < dram->num_cs; i++) { 2855c5aff182SThomas Petazzoni const struct mbus_dram_window *cs = dram->cs + i; 2856c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_WIN_BASE(i), (cs->base & 0xffff0000) | 2857c5aff182SThomas Petazzoni (cs->mbus_attr << 8) | dram->mbus_dram_target_id); 2858c5aff182SThomas Petazzoni 2859c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_WIN_SIZE(i), 2860c5aff182SThomas Petazzoni (cs->size - 1) & 0xffff0000); 2861c5aff182SThomas Petazzoni 2862c5aff182SThomas Petazzoni win_enable &= ~(1 << i); 2863c5aff182SThomas Petazzoni win_protect |= 3 << (2 * i); 2864c5aff182SThomas Petazzoni } 2865c5aff182SThomas Petazzoni 2866c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_BASE_ADDR_ENABLE, win_enable); 2867c5aff182SThomas Petazzoni } 2868c5aff182SThomas Petazzoni 2869c5aff182SThomas Petazzoni /* Power up the port */ 28703f1dd4bcSThomas Petazzoni static int mvneta_port_power_up(struct mvneta_port *pp, int phy_mode) 2871c5aff182SThomas Petazzoni { 28723f1dd4bcSThomas Petazzoni u32 ctrl; 2873c5aff182SThomas Petazzoni 2874c5aff182SThomas Petazzoni /* MAC Cause register should be cleared */ 2875c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_UNIT_INTR_CAUSE, 0); 2876c5aff182SThomas Petazzoni 28773f1dd4bcSThomas Petazzoni ctrl = mvreg_read(pp, MVNETA_GMAC_CTRL_2); 2878c5aff182SThomas Petazzoni 28793f1dd4bcSThomas Petazzoni /* Even though it might look weird, when we're configured in 28803f1dd4bcSThomas Petazzoni * SGMII or QSGMII mode, the RGMII bit needs to be set. 28813f1dd4bcSThomas Petazzoni */ 28823f1dd4bcSThomas Petazzoni switch(phy_mode) { 28833f1dd4bcSThomas Petazzoni case PHY_INTERFACE_MODE_QSGMII: 28843f1dd4bcSThomas Petazzoni mvreg_write(pp, MVNETA_SERDES_CFG, MVNETA_QSGMII_SERDES_PROTO); 28853f1dd4bcSThomas Petazzoni ctrl |= MVNETA_GMAC2_PCS_ENABLE | MVNETA_GMAC2_PORT_RGMII; 28863f1dd4bcSThomas Petazzoni break; 28873f1dd4bcSThomas Petazzoni case PHY_INTERFACE_MODE_SGMII: 28883f1dd4bcSThomas Petazzoni mvreg_write(pp, MVNETA_SERDES_CFG, MVNETA_SGMII_SERDES_PROTO); 28893f1dd4bcSThomas Petazzoni ctrl |= MVNETA_GMAC2_PCS_ENABLE | MVNETA_GMAC2_PORT_RGMII; 28903f1dd4bcSThomas Petazzoni break; 28913f1dd4bcSThomas Petazzoni case PHY_INTERFACE_MODE_RGMII: 28923f1dd4bcSThomas Petazzoni case PHY_INTERFACE_MODE_RGMII_ID: 28933f1dd4bcSThomas Petazzoni ctrl |= MVNETA_GMAC2_PORT_RGMII; 28943f1dd4bcSThomas Petazzoni break; 28953f1dd4bcSThomas Petazzoni default: 28963f1dd4bcSThomas Petazzoni return -EINVAL; 28973f1dd4bcSThomas Petazzoni } 2898c5aff182SThomas Petazzoni 2899c5aff182SThomas Petazzoni /* Cancel Port Reset */ 29003f1dd4bcSThomas Petazzoni ctrl &= ~MVNETA_GMAC2_PORT_RESET; 29013f1dd4bcSThomas Petazzoni mvreg_write(pp, MVNETA_GMAC_CTRL_2, ctrl); 2902c5aff182SThomas Petazzoni 2903c5aff182SThomas Petazzoni while ((mvreg_read(pp, MVNETA_GMAC_CTRL_2) & 2904c5aff182SThomas Petazzoni MVNETA_GMAC2_PORT_RESET) != 0) 2905c5aff182SThomas Petazzoni continue; 29063f1dd4bcSThomas Petazzoni 29073f1dd4bcSThomas Petazzoni return 0; 2908c5aff182SThomas Petazzoni } 2909c5aff182SThomas Petazzoni 2910c5aff182SThomas Petazzoni /* Device initialization routine */ 291103ce758eSGreg KH static int mvneta_probe(struct platform_device *pdev) 2912c5aff182SThomas Petazzoni { 2913c5aff182SThomas Petazzoni const struct mbus_dram_target_info *dram_target_info; 2914c3f0dd38SThomas Petazzoni struct resource *res; 2915c5aff182SThomas Petazzoni struct device_node *dn = pdev->dev.of_node; 2916c5aff182SThomas Petazzoni struct device_node *phy_node; 2917189dd626SThomas Petazzoni u32 phy_addr; 2918c5aff182SThomas Petazzoni struct mvneta_port *pp; 2919c5aff182SThomas Petazzoni struct net_device *dev; 29208cc3e439SThomas Petazzoni const char *dt_mac_addr; 29218cc3e439SThomas Petazzoni char hw_mac_addr[ETH_ALEN]; 29228cc3e439SThomas Petazzoni const char *mac_from; 2923c5aff182SThomas Petazzoni int phy_mode; 2924c5aff182SThomas Petazzoni int err; 2925c5aff182SThomas Petazzoni 29266a20c175SThomas Petazzoni /* Our multiqueue support is not complete, so for now, only 2927c5aff182SThomas Petazzoni * allow the usage of the first RX queue 2928c5aff182SThomas Petazzoni */ 2929c5aff182SThomas Petazzoni if (rxq_def != 0) { 2930c5aff182SThomas Petazzoni dev_err(&pdev->dev, "Invalid rxq_def argument: %d\n", rxq_def); 2931c5aff182SThomas Petazzoni return -EINVAL; 2932c5aff182SThomas Petazzoni } 2933c5aff182SThomas Petazzoni 2934ee40a116SWilly Tarreau dev = alloc_etherdev_mqs(sizeof(struct mvneta_port), txq_number, rxq_number); 2935c5aff182SThomas Petazzoni if (!dev) 2936c5aff182SThomas Petazzoni return -ENOMEM; 2937c5aff182SThomas Petazzoni 2938c5aff182SThomas Petazzoni dev->irq = irq_of_parse_and_map(dn, 0); 2939c5aff182SThomas Petazzoni if (dev->irq == 0) { 2940c5aff182SThomas Petazzoni err = -EINVAL; 2941c5aff182SThomas Petazzoni goto err_free_netdev; 2942c5aff182SThomas Petazzoni } 2943c5aff182SThomas Petazzoni 2944c5aff182SThomas Petazzoni phy_node = of_parse_phandle(dn, "phy", 0); 2945c5aff182SThomas Petazzoni if (!phy_node) { 294683895bedSThomas Petazzoni if (!of_phy_is_fixed_link(dn)) { 294783895bedSThomas Petazzoni dev_err(&pdev->dev, "no PHY specified\n"); 2948c5aff182SThomas Petazzoni err = -ENODEV; 2949c5aff182SThomas Petazzoni goto err_free_irq; 2950c5aff182SThomas Petazzoni } 2951c5aff182SThomas Petazzoni 295283895bedSThomas Petazzoni err = of_phy_register_fixed_link(dn); 295383895bedSThomas Petazzoni if (err < 0) { 295483895bedSThomas Petazzoni dev_err(&pdev->dev, "cannot register fixed PHY\n"); 295583895bedSThomas Petazzoni goto err_free_irq; 295683895bedSThomas Petazzoni } 295783895bedSThomas Petazzoni 295883895bedSThomas Petazzoni /* In the case of a fixed PHY, the DT node associated 295983895bedSThomas Petazzoni * to the PHY is the Ethernet MAC DT node. 296083895bedSThomas Petazzoni */ 296183895bedSThomas Petazzoni phy_node = dn; 296283895bedSThomas Petazzoni } 296383895bedSThomas Petazzoni 2964c5aff182SThomas Petazzoni phy_mode = of_get_phy_mode(dn); 2965c5aff182SThomas Petazzoni if (phy_mode < 0) { 2966c5aff182SThomas Petazzoni dev_err(&pdev->dev, "incorrect phy-mode\n"); 2967c5aff182SThomas Petazzoni err = -EINVAL; 2968c5aff182SThomas Petazzoni goto err_free_irq; 2969c5aff182SThomas Petazzoni } 2970c5aff182SThomas Petazzoni 2971c5aff182SThomas Petazzoni dev->tx_queue_len = MVNETA_MAX_TXD; 2972c5aff182SThomas Petazzoni dev->watchdog_timeo = 5 * HZ; 2973c5aff182SThomas Petazzoni dev->netdev_ops = &mvneta_netdev_ops; 2974c5aff182SThomas Petazzoni 29757ad24ea4SWilfried Klaebe dev->ethtool_ops = &mvneta_eth_tool_ops; 2976c5aff182SThomas Petazzoni 2977c5aff182SThomas Petazzoni pp = netdev_priv(dev); 2978c5aff182SThomas Petazzoni 2979c5aff182SThomas Petazzoni pp->weight = MVNETA_RX_POLL_WEIGHT; 2980c5aff182SThomas Petazzoni pp->phy_node = phy_node; 2981c5aff182SThomas Petazzoni pp->phy_interface = phy_mode; 2982c5aff182SThomas Petazzoni 2983189dd626SThomas Petazzoni pp->clk = devm_clk_get(&pdev->dev, NULL); 2984189dd626SThomas Petazzoni if (IS_ERR(pp->clk)) { 2985189dd626SThomas Petazzoni err = PTR_ERR(pp->clk); 29865445eaf3SArnaud Patard \(Rtp\) goto err_free_irq; 2987189dd626SThomas Petazzoni } 2988189dd626SThomas Petazzoni 2989189dd626SThomas Petazzoni clk_prepare_enable(pp->clk); 2990189dd626SThomas Petazzoni 2991c3f0dd38SThomas Petazzoni res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2992c3f0dd38SThomas Petazzoni pp->base = devm_ioremap_resource(&pdev->dev, res); 2993c3f0dd38SThomas Petazzoni if (IS_ERR(pp->base)) { 2994c3f0dd38SThomas Petazzoni err = PTR_ERR(pp->base); 29955445eaf3SArnaud Patard \(Rtp\) goto err_clk; 29965445eaf3SArnaud Patard \(Rtp\) } 29975445eaf3SArnaud Patard \(Rtp\) 299874c41b04Swilly tarreau /* Alloc per-cpu stats */ 29991c213bd2SWANG Cong pp->stats = netdev_alloc_pcpu_stats(struct mvneta_pcpu_stats); 300074c41b04Swilly tarreau if (!pp->stats) { 300174c41b04Swilly tarreau err = -ENOMEM; 3002c3f0dd38SThomas Petazzoni goto err_clk; 300374c41b04Swilly tarreau } 300474c41b04Swilly tarreau 30058cc3e439SThomas Petazzoni dt_mac_addr = of_get_mac_address(dn); 30066c7a9a3cSLuka Perkov if (dt_mac_addr) { 30078cc3e439SThomas Petazzoni mac_from = "device tree"; 30088cc3e439SThomas Petazzoni memcpy(dev->dev_addr, dt_mac_addr, ETH_ALEN); 30098cc3e439SThomas Petazzoni } else { 30108cc3e439SThomas Petazzoni mvneta_get_mac_addr(pp, hw_mac_addr); 30118cc3e439SThomas Petazzoni if (is_valid_ether_addr(hw_mac_addr)) { 30128cc3e439SThomas Petazzoni mac_from = "hardware"; 30138cc3e439SThomas Petazzoni memcpy(dev->dev_addr, hw_mac_addr, ETH_ALEN); 30148cc3e439SThomas Petazzoni } else { 30158cc3e439SThomas Petazzoni mac_from = "random"; 30168cc3e439SThomas Petazzoni eth_hw_addr_random(dev); 30178cc3e439SThomas Petazzoni } 30188cc3e439SThomas Petazzoni } 30198cc3e439SThomas Petazzoni 3020c5aff182SThomas Petazzoni pp->tx_ring_size = MVNETA_MAX_TXD; 3021c5aff182SThomas Petazzoni pp->rx_ring_size = MVNETA_MAX_RXD; 3022c5aff182SThomas Petazzoni 3023c5aff182SThomas Petazzoni pp->dev = dev; 3024c5aff182SThomas Petazzoni SET_NETDEV_DEV(dev, &pdev->dev); 3025c5aff182SThomas Petazzoni 3026c5aff182SThomas Petazzoni err = mvneta_init(pp, phy_addr); 3027c5aff182SThomas Petazzoni if (err < 0) { 3028c5aff182SThomas Petazzoni dev_err(&pdev->dev, "can't init eth hal\n"); 302974c41b04Swilly tarreau goto err_free_stats; 3030c5aff182SThomas Petazzoni } 30313f1dd4bcSThomas Petazzoni 30323f1dd4bcSThomas Petazzoni err = mvneta_port_power_up(pp, phy_mode); 30333f1dd4bcSThomas Petazzoni if (err < 0) { 30343f1dd4bcSThomas Petazzoni dev_err(&pdev->dev, "can't power up port\n"); 30353f1dd4bcSThomas Petazzoni goto err_deinit; 30363f1dd4bcSThomas Petazzoni } 3037c5aff182SThomas Petazzoni 3038c5aff182SThomas Petazzoni dram_target_info = mv_mbus_dram_info(); 3039c5aff182SThomas Petazzoni if (dram_target_info) 3040c5aff182SThomas Petazzoni mvneta_conf_mbus_windows(pp, dram_target_info); 3041c5aff182SThomas Petazzoni 3042c5aff182SThomas Petazzoni netif_napi_add(dev, &pp->napi, mvneta_poll, pp->weight); 3043c5aff182SThomas Petazzoni 30442adb719dSEzequiel Garcia dev->features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO; 304501ef26caSEzequiel Garcia dev->hw_features |= dev->features; 304601ef26caSEzequiel Garcia dev->vlan_features |= dev->features; 3047b50b72deSwilly tarreau dev->priv_flags |= IFF_UNICAST_FLT; 3048b50b72deSwilly tarreau 3049c5aff182SThomas Petazzoni err = register_netdev(dev); 3050c5aff182SThomas Petazzoni if (err < 0) { 3051c5aff182SThomas Petazzoni dev_err(&pdev->dev, "failed to register\n"); 3052c5aff182SThomas Petazzoni goto err_deinit; 3053c5aff182SThomas Petazzoni } 3054c5aff182SThomas Petazzoni 30558cc3e439SThomas Petazzoni netdev_info(dev, "Using %s mac address %pM\n", mac_from, 30568cc3e439SThomas Petazzoni dev->dev_addr); 3057c5aff182SThomas Petazzoni 3058c5aff182SThomas Petazzoni platform_set_drvdata(pdev, pp->dev); 3059c5aff182SThomas Petazzoni 3060c5aff182SThomas Petazzoni return 0; 3061c5aff182SThomas Petazzoni 3062c5aff182SThomas Petazzoni err_deinit: 3063c5aff182SThomas Petazzoni mvneta_deinit(pp); 306474c41b04Swilly tarreau err_free_stats: 306574c41b04Swilly tarreau free_percpu(pp->stats); 30665445eaf3SArnaud Patard \(Rtp\) err_clk: 30675445eaf3SArnaud Patard \(Rtp\) clk_disable_unprepare(pp->clk); 3068c5aff182SThomas Petazzoni err_free_irq: 3069c5aff182SThomas Petazzoni irq_dispose_mapping(dev->irq); 3070c5aff182SThomas Petazzoni err_free_netdev: 3071c5aff182SThomas Petazzoni free_netdev(dev); 3072c5aff182SThomas Petazzoni return err; 3073c5aff182SThomas Petazzoni } 3074c5aff182SThomas Petazzoni 3075c5aff182SThomas Petazzoni /* Device removal routine */ 307603ce758eSGreg KH static int mvneta_remove(struct platform_device *pdev) 3077c5aff182SThomas Petazzoni { 3078c5aff182SThomas Petazzoni struct net_device *dev = platform_get_drvdata(pdev); 3079c5aff182SThomas Petazzoni struct mvneta_port *pp = netdev_priv(dev); 3080c5aff182SThomas Petazzoni 3081c5aff182SThomas Petazzoni unregister_netdev(dev); 3082c5aff182SThomas Petazzoni mvneta_deinit(pp); 3083189dd626SThomas Petazzoni clk_disable_unprepare(pp->clk); 308474c41b04Swilly tarreau free_percpu(pp->stats); 3085c5aff182SThomas Petazzoni irq_dispose_mapping(dev->irq); 3086c5aff182SThomas Petazzoni free_netdev(dev); 3087c5aff182SThomas Petazzoni 3088c5aff182SThomas Petazzoni return 0; 3089c5aff182SThomas Petazzoni } 3090c5aff182SThomas Petazzoni 3091c5aff182SThomas Petazzoni static const struct of_device_id mvneta_match[] = { 3092c5aff182SThomas Petazzoni { .compatible = "marvell,armada-370-neta" }, 3093c5aff182SThomas Petazzoni { } 3094c5aff182SThomas Petazzoni }; 3095c5aff182SThomas Petazzoni MODULE_DEVICE_TABLE(of, mvneta_match); 3096c5aff182SThomas Petazzoni 3097c5aff182SThomas Petazzoni static struct platform_driver mvneta_driver = { 3098c5aff182SThomas Petazzoni .probe = mvneta_probe, 309903ce758eSGreg KH .remove = mvneta_remove, 3100c5aff182SThomas Petazzoni .driver = { 3101c5aff182SThomas Petazzoni .name = MVNETA_DRIVER_NAME, 3102c5aff182SThomas Petazzoni .of_match_table = mvneta_match, 3103c5aff182SThomas Petazzoni }, 3104c5aff182SThomas Petazzoni }; 3105c5aff182SThomas Petazzoni 3106c5aff182SThomas Petazzoni module_platform_driver(mvneta_driver); 3107c5aff182SThomas Petazzoni 3108c5aff182SThomas Petazzoni MODULE_DESCRIPTION("Marvell NETA Ethernet Driver - www.marvell.com"); 3109c5aff182SThomas Petazzoni MODULE_AUTHOR("Rami Rosen <rosenr@marvell.com>, Thomas Petazzoni <thomas.petazzoni@free-electrons.com>"); 3110c5aff182SThomas Petazzoni MODULE_LICENSE("GPL"); 3111c5aff182SThomas Petazzoni 3112c5aff182SThomas Petazzoni module_param(rxq_number, int, S_IRUGO); 3113c5aff182SThomas Petazzoni module_param(txq_number, int, S_IRUGO); 3114c5aff182SThomas Petazzoni 3115c5aff182SThomas Petazzoni module_param(rxq_def, int, S_IRUGO); 3116f19fadfcSwilly tarreau module_param(rx_copybreak, int, S_IRUGO | S_IWUSR); 3117