1c5aff182SThomas Petazzoni /* 2c5aff182SThomas Petazzoni * Driver for Marvell NETA network card for Armada XP and Armada 370 SoCs. 3c5aff182SThomas Petazzoni * 4c5aff182SThomas Petazzoni * Copyright (C) 2012 Marvell 5c5aff182SThomas Petazzoni * 6c5aff182SThomas Petazzoni * Rami Rosen <rosenr@marvell.com> 7c5aff182SThomas Petazzoni * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> 8c5aff182SThomas Petazzoni * 9c5aff182SThomas Petazzoni * This file is licensed under the terms of the GNU General Public 10c5aff182SThomas Petazzoni * License version 2. This program is licensed "as is" without any 11c5aff182SThomas Petazzoni * warranty of any kind, whether express or implied. 12c5aff182SThomas Petazzoni */ 13c5aff182SThomas Petazzoni 140e03f563SJisheng Zhang #include <linux/clk.h> 150e03f563SJisheng Zhang #include <linux/cpu.h> 16c5aff182SThomas Petazzoni #include <linux/etherdevice.h> 170e03f563SJisheng Zhang #include <linux/if_vlan.h> 18c5aff182SThomas Petazzoni #include <linux/inetdevice.h> 190e03f563SJisheng Zhang #include <linux/interrupt.h> 200e03f563SJisheng Zhang #include <linux/io.h> 210e03f563SJisheng Zhang #include <linux/kernel.h> 22c5aff182SThomas Petazzoni #include <linux/mbus.h> 23c5aff182SThomas Petazzoni #include <linux/module.h> 240e03f563SJisheng Zhang #include <linux/netdevice.h> 25c5aff182SThomas Petazzoni #include <linux/of.h> 260e03f563SJisheng Zhang #include <linux/of_address.h> 27c5aff182SThomas Petazzoni #include <linux/of_irq.h> 28c5aff182SThomas Petazzoni #include <linux/of_mdio.h> 29c5aff182SThomas Petazzoni #include <linux/of_net.h> 30a10c1c81SRussell King #include <linux/phy/phy.h> 31c5aff182SThomas Petazzoni #include <linux/phy.h> 32503f9aa9SRussell King #include <linux/phylink.h> 330e03f563SJisheng Zhang #include <linux/platform_device.h> 340e03f563SJisheng Zhang #include <linux/skbuff.h> 35baa11ebcSGregory CLEMENT #include <net/hwbm.h> 36dc35a10fSMarcin Wojtas #include "mvneta_bm.h" 370e03f563SJisheng Zhang #include <net/ip.h> 380e03f563SJisheng Zhang #include <net/ipv6.h> 390e03f563SJisheng Zhang #include <net/tso.h> 40568a3fa2SLorenzo Bianconi #include <net/page_pool.h> 419adafe2bSVladimir Oltean #include <net/pkt_sched.h> 420db51da7SLorenzo Bianconi #include <linux/bpf_trace.h> 43c5aff182SThomas Petazzoni 44c5aff182SThomas Petazzoni /* Registers */ 45c5aff182SThomas Petazzoni #define MVNETA_RXQ_CONFIG_REG(q) (0x1400 + ((q) << 2)) 46e5bdf689SMarcin Wojtas #define MVNETA_RXQ_HW_BUF_ALLOC BIT(0) 47dc35a10fSMarcin Wojtas #define MVNETA_RXQ_SHORT_POOL_ID_SHIFT 4 48dc35a10fSMarcin Wojtas #define MVNETA_RXQ_SHORT_POOL_ID_MASK 0x30 49dc35a10fSMarcin Wojtas #define MVNETA_RXQ_LONG_POOL_ID_SHIFT 6 50dc35a10fSMarcin Wojtas #define MVNETA_RXQ_LONG_POOL_ID_MASK 0xc0 51c5aff182SThomas Petazzoni #define MVNETA_RXQ_PKT_OFFSET_ALL_MASK (0xf << 8) 52c5aff182SThomas Petazzoni #define MVNETA_RXQ_PKT_OFFSET_MASK(offs) ((offs) << 8) 53c5aff182SThomas Petazzoni #define MVNETA_RXQ_THRESHOLD_REG(q) (0x14c0 + ((q) << 2)) 54c5aff182SThomas Petazzoni #define MVNETA_RXQ_NON_OCCUPIED(v) ((v) << 16) 55c5aff182SThomas Petazzoni #define MVNETA_RXQ_BASE_ADDR_REG(q) (0x1480 + ((q) << 2)) 56c5aff182SThomas Petazzoni #define MVNETA_RXQ_SIZE_REG(q) (0x14a0 + ((q) << 2)) 57c5aff182SThomas Petazzoni #define MVNETA_RXQ_BUF_SIZE_SHIFT 19 58c5aff182SThomas Petazzoni #define MVNETA_RXQ_BUF_SIZE_MASK (0x1fff << 19) 59c5aff182SThomas Petazzoni #define MVNETA_RXQ_STATUS_REG(q) (0x14e0 + ((q) << 2)) 60c5aff182SThomas Petazzoni #define MVNETA_RXQ_OCCUPIED_ALL_MASK 0x3fff 61c5aff182SThomas Petazzoni #define MVNETA_RXQ_STATUS_UPDATE_REG(q) (0x1500 + ((q) << 2)) 62c5aff182SThomas Petazzoni #define MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT 16 63c5aff182SThomas Petazzoni #define MVNETA_RXQ_ADD_NON_OCCUPIED_MAX 255 64dc35a10fSMarcin Wojtas #define MVNETA_PORT_POOL_BUFFER_SZ_REG(pool) (0x1700 + ((pool) << 2)) 65dc35a10fSMarcin Wojtas #define MVNETA_PORT_POOL_BUFFER_SZ_SHIFT 3 66dc35a10fSMarcin Wojtas #define MVNETA_PORT_POOL_BUFFER_SZ_MASK 0xfff8 67c5aff182SThomas Petazzoni #define MVNETA_PORT_RX_RESET 0x1cc0 68c5aff182SThomas Petazzoni #define MVNETA_PORT_RX_DMA_RESET BIT(0) 69c5aff182SThomas Petazzoni #define MVNETA_PHY_ADDR 0x2000 70c5aff182SThomas Petazzoni #define MVNETA_PHY_ADDR_MASK 0x1f 71c5aff182SThomas Petazzoni #define MVNETA_MBUS_RETRY 0x2010 72c5aff182SThomas Petazzoni #define MVNETA_UNIT_INTR_CAUSE 0x2080 73c5aff182SThomas Petazzoni #define MVNETA_UNIT_CONTROL 0x20B0 74c5aff182SThomas Petazzoni #define MVNETA_PHY_POLLING_ENABLE BIT(1) 75c5aff182SThomas Petazzoni #define MVNETA_WIN_BASE(w) (0x2200 + ((w) << 3)) 76c5aff182SThomas Petazzoni #define MVNETA_WIN_SIZE(w) (0x2204 + ((w) << 3)) 77c5aff182SThomas Petazzoni #define MVNETA_WIN_REMAP(w) (0x2280 + ((w) << 2)) 78c5aff182SThomas Petazzoni #define MVNETA_BASE_ADDR_ENABLE 0x2290 792d2a514cSChris Packham #define MVNETA_AC5_CNM_DDR_TARGET 0x2 802d2a514cSChris Packham #define MVNETA_AC5_CNM_DDR_ATTR 0xb 81db6ba9a5SMarcin Wojtas #define MVNETA_ACCESS_PROTECT_ENABLE 0x2294 82c5aff182SThomas Petazzoni #define MVNETA_PORT_CONFIG 0x2400 83c5aff182SThomas Petazzoni #define MVNETA_UNI_PROMISC_MODE BIT(0) 84c5aff182SThomas Petazzoni #define MVNETA_DEF_RXQ(q) ((q) << 1) 85c5aff182SThomas Petazzoni #define MVNETA_DEF_RXQ_ARP(q) ((q) << 4) 86c5aff182SThomas Petazzoni #define MVNETA_TX_UNSET_ERR_SUM BIT(12) 87c5aff182SThomas Petazzoni #define MVNETA_DEF_RXQ_TCP(q) ((q) << 16) 88c5aff182SThomas Petazzoni #define MVNETA_DEF_RXQ_UDP(q) ((q) << 19) 89c5aff182SThomas Petazzoni #define MVNETA_DEF_RXQ_BPDU(q) ((q) << 22) 90c5aff182SThomas Petazzoni #define MVNETA_RX_CSUM_WITH_PSEUDO_HDR BIT(25) 91c5aff182SThomas Petazzoni #define MVNETA_PORT_CONFIG_DEFL_VALUE(q) (MVNETA_DEF_RXQ(q) | \ 92c5aff182SThomas Petazzoni MVNETA_DEF_RXQ_ARP(q) | \ 93c5aff182SThomas Petazzoni MVNETA_DEF_RXQ_TCP(q) | \ 94c5aff182SThomas Petazzoni MVNETA_DEF_RXQ_UDP(q) | \ 95c5aff182SThomas Petazzoni MVNETA_DEF_RXQ_BPDU(q) | \ 96c5aff182SThomas Petazzoni MVNETA_TX_UNSET_ERR_SUM | \ 97c5aff182SThomas Petazzoni MVNETA_RX_CSUM_WITH_PSEUDO_HDR) 98c5aff182SThomas Petazzoni #define MVNETA_PORT_CONFIG_EXTEND 0x2404 99c5aff182SThomas Petazzoni #define MVNETA_MAC_ADDR_LOW 0x2414 100c5aff182SThomas Petazzoni #define MVNETA_MAC_ADDR_HIGH 0x2418 101c5aff182SThomas Petazzoni #define MVNETA_SDMA_CONFIG 0x241c 102c5aff182SThomas Petazzoni #define MVNETA_SDMA_BRST_SIZE_16 4 103c5aff182SThomas Petazzoni #define MVNETA_RX_BRST_SZ_MASK(burst) ((burst) << 1) 104c5aff182SThomas Petazzoni #define MVNETA_RX_NO_DATA_SWAP BIT(4) 105c5aff182SThomas Petazzoni #define MVNETA_TX_NO_DATA_SWAP BIT(5) 1069ad8fef6SThomas Petazzoni #define MVNETA_DESC_SWAP BIT(6) 107c5aff182SThomas Petazzoni #define MVNETA_TX_BRST_SZ_MASK(burst) ((burst) << 22) 1084906887aSMaxime Chevallier #define MVNETA_VLAN_PRIO_TO_RXQ 0x2440 1094906887aSMaxime Chevallier #define MVNETA_VLAN_PRIO_RXQ_MAP(prio, rxq) ((rxq) << ((prio) * 3)) 110c5aff182SThomas Petazzoni #define MVNETA_PORT_STATUS 0x2444 111359f4cddSMaxim Kiselev #define MVNETA_TX_IN_PRGRS BIT(0) 112c5aff182SThomas Petazzoni #define MVNETA_TX_FIFO_EMPTY BIT(8) 113c5aff182SThomas Petazzoni #define MVNETA_RX_MIN_FRAME_SIZE 0x247c 114b4748553SSascha Hauer /* Only exists on Armada XP and Armada 370 */ 1153f1dd4bcSThomas Petazzoni #define MVNETA_SERDES_CFG 0x24A0 1165445eaf3SArnaud Patard \(Rtp\) #define MVNETA_SGMII_SERDES_PROTO 0x0cc7 1173f1dd4bcSThomas Petazzoni #define MVNETA_QSGMII_SERDES_PROTO 0x0667 1181a642ca7SSascha Hauer #define MVNETA_HSGMII_SERDES_PROTO 0x1107 119c5aff182SThomas Petazzoni #define MVNETA_TYPE_PRIO 0x24bc 120c5aff182SThomas Petazzoni #define MVNETA_FORCE_UNI BIT(21) 121c5aff182SThomas Petazzoni #define MVNETA_TXQ_CMD_1 0x24e4 122c5aff182SThomas Petazzoni #define MVNETA_TXQ_CMD 0x2448 123c5aff182SThomas Petazzoni #define MVNETA_TXQ_DISABLE_SHIFT 8 124c5aff182SThomas Petazzoni #define MVNETA_TXQ_ENABLE_MASK 0x000000ff 125e483911fSAndrew Lunn #define MVNETA_RX_DISCARD_FRAME_COUNT 0x2484 126e483911fSAndrew Lunn #define MVNETA_OVERRUN_FRAME_COUNT 0x2488 127898b2970SStas Sergeev #define MVNETA_GMAC_CLOCK_DIVIDER 0x24f4 128898b2970SStas Sergeev #define MVNETA_GMAC_1MS_CLOCK_ENABLE BIT(31) 129c5aff182SThomas Petazzoni #define MVNETA_ACC_MODE 0x2500 130dc35a10fSMarcin Wojtas #define MVNETA_BM_ADDRESS 0x2504 131c5aff182SThomas Petazzoni #define MVNETA_CPU_MAP(cpu) (0x2540 + ((cpu) << 2)) 132c5aff182SThomas Petazzoni #define MVNETA_CPU_RXQ_ACCESS_ALL_MASK 0x000000ff 133c5aff182SThomas Petazzoni #define MVNETA_CPU_TXQ_ACCESS_ALL_MASK 0x0000ff00 1342dcf75e2SGregory CLEMENT #define MVNETA_CPU_RXQ_ACCESS(rxq) BIT(rxq) 13550bf8cb6SGregory CLEMENT #define MVNETA_CPU_TXQ_ACCESS(txq) BIT(txq + 8) 136c5aff182SThomas Petazzoni #define MVNETA_RXQ_TIME_COAL_REG(q) (0x2580 + ((q) << 2)) 13740ba35e7Swilly tarreau 1382dcf75e2SGregory CLEMENT /* Exception Interrupt Port/Queue Cause register 1392dcf75e2SGregory CLEMENT * 1402dcf75e2SGregory CLEMENT * Their behavior depend of the mapping done using the PCPX2Q 1412dcf75e2SGregory CLEMENT * registers. For a given CPU if the bit associated to a queue is not 1422dcf75e2SGregory CLEMENT * set, then for the register a read from this CPU will always return 1432dcf75e2SGregory CLEMENT * 0 and a write won't do anything 1442dcf75e2SGregory CLEMENT */ 14540ba35e7Swilly tarreau 146c5aff182SThomas Petazzoni #define MVNETA_INTR_NEW_CAUSE 0x25a0 147c5aff182SThomas Petazzoni #define MVNETA_INTR_NEW_MASK 0x25a4 14840ba35e7Swilly tarreau 14940ba35e7Swilly tarreau /* bits 0..7 = TXQ SENT, one bit per queue. 15040ba35e7Swilly tarreau * bits 8..15 = RXQ OCCUP, one bit per queue. 15140ba35e7Swilly tarreau * bits 16..23 = RXQ FREE, one bit per queue. 15240ba35e7Swilly tarreau * bit 29 = OLD_REG_SUM, see old reg ? 15340ba35e7Swilly tarreau * bit 30 = TX_ERR_SUM, one bit for 4 ports 15440ba35e7Swilly tarreau * bit 31 = MISC_SUM, one bit for 4 ports 15540ba35e7Swilly tarreau */ 15640ba35e7Swilly tarreau #define MVNETA_TX_INTR_MASK(nr_txqs) (((1 << nr_txqs) - 1) << 0) 15740ba35e7Swilly tarreau #define MVNETA_TX_INTR_MASK_ALL (0xff << 0) 15840ba35e7Swilly tarreau #define MVNETA_RX_INTR_MASK(nr_rxqs) (((1 << nr_rxqs) - 1) << 8) 15940ba35e7Swilly tarreau #define MVNETA_RX_INTR_MASK_ALL (0xff << 8) 160898b2970SStas Sergeev #define MVNETA_MISCINTR_INTR_MASK BIT(31) 16140ba35e7Swilly tarreau 162c5aff182SThomas Petazzoni #define MVNETA_INTR_OLD_CAUSE 0x25a8 163c5aff182SThomas Petazzoni #define MVNETA_INTR_OLD_MASK 0x25ac 16440ba35e7Swilly tarreau 16540ba35e7Swilly tarreau /* Data Path Port/Queue Cause Register */ 166c5aff182SThomas Petazzoni #define MVNETA_INTR_MISC_CAUSE 0x25b0 167c5aff182SThomas Petazzoni #define MVNETA_INTR_MISC_MASK 0x25b4 16840ba35e7Swilly tarreau 16940ba35e7Swilly tarreau #define MVNETA_CAUSE_PHY_STATUS_CHANGE BIT(0) 17040ba35e7Swilly tarreau #define MVNETA_CAUSE_LINK_CHANGE BIT(1) 17140ba35e7Swilly tarreau #define MVNETA_CAUSE_PTP BIT(4) 17240ba35e7Swilly tarreau 17340ba35e7Swilly tarreau #define MVNETA_CAUSE_INTERNAL_ADDR_ERR BIT(7) 17440ba35e7Swilly tarreau #define MVNETA_CAUSE_RX_OVERRUN BIT(8) 17540ba35e7Swilly tarreau #define MVNETA_CAUSE_RX_CRC_ERROR BIT(9) 17640ba35e7Swilly tarreau #define MVNETA_CAUSE_RX_LARGE_PKT BIT(10) 17740ba35e7Swilly tarreau #define MVNETA_CAUSE_TX_UNDERUN BIT(11) 17840ba35e7Swilly tarreau #define MVNETA_CAUSE_PRBS_ERR BIT(12) 17940ba35e7Swilly tarreau #define MVNETA_CAUSE_PSC_SYNC_CHANGE BIT(13) 18040ba35e7Swilly tarreau #define MVNETA_CAUSE_SERDES_SYNC_ERR BIT(14) 18140ba35e7Swilly tarreau 18240ba35e7Swilly tarreau #define MVNETA_CAUSE_BMU_ALLOC_ERR_SHIFT 16 18340ba35e7Swilly tarreau #define MVNETA_CAUSE_BMU_ALLOC_ERR_ALL_MASK (0xF << MVNETA_CAUSE_BMU_ALLOC_ERR_SHIFT) 18440ba35e7Swilly tarreau #define MVNETA_CAUSE_BMU_ALLOC_ERR_MASK(pool) (1 << (MVNETA_CAUSE_BMU_ALLOC_ERR_SHIFT + (pool))) 18540ba35e7Swilly tarreau 18640ba35e7Swilly tarreau #define MVNETA_CAUSE_TXQ_ERROR_SHIFT 24 18740ba35e7Swilly tarreau #define MVNETA_CAUSE_TXQ_ERROR_ALL_MASK (0xFF << MVNETA_CAUSE_TXQ_ERROR_SHIFT) 18840ba35e7Swilly tarreau #define MVNETA_CAUSE_TXQ_ERROR_MASK(q) (1 << (MVNETA_CAUSE_TXQ_ERROR_SHIFT + (q))) 18940ba35e7Swilly tarreau 190c5aff182SThomas Petazzoni #define MVNETA_INTR_ENABLE 0x25b8 191c5aff182SThomas Petazzoni #define MVNETA_TXQ_INTR_ENABLE_ALL_MASK 0x0000ff00 192dc1aadf6SMarcin Wojtas #define MVNETA_RXQ_INTR_ENABLE_ALL_MASK 0x000000ff 19340ba35e7Swilly tarreau 194c5aff182SThomas Petazzoni #define MVNETA_RXQ_CMD 0x2680 195c5aff182SThomas Petazzoni #define MVNETA_RXQ_DISABLE_SHIFT 8 196c5aff182SThomas Petazzoni #define MVNETA_RXQ_ENABLE_MASK 0x000000ff 197c5aff182SThomas Petazzoni #define MVETH_TXQ_TOKEN_COUNT_REG(q) (0x2700 + ((q) << 4)) 198c5aff182SThomas Petazzoni #define MVETH_TXQ_TOKEN_CFG_REG(q) (0x2704 + ((q) << 4)) 199c5aff182SThomas Petazzoni #define MVNETA_GMAC_CTRL_0 0x2c00 200c5aff182SThomas Petazzoni #define MVNETA_GMAC_MAX_RX_SIZE_SHIFT 2 201c5aff182SThomas Petazzoni #define MVNETA_GMAC_MAX_RX_SIZE_MASK 0x7ffc 20222f4bf8aSRussell King #define MVNETA_GMAC0_PORT_1000BASE_X BIT(1) 203c5aff182SThomas Petazzoni #define MVNETA_GMAC0_PORT_ENABLE BIT(0) 204c5aff182SThomas Petazzoni #define MVNETA_GMAC_CTRL_2 0x2c08 205898b2970SStas Sergeev #define MVNETA_GMAC2_INBAND_AN_ENABLE BIT(0) 206a79121d3SThomas Petazzoni #define MVNETA_GMAC2_PCS_ENABLE BIT(3) 207c5aff182SThomas Petazzoni #define MVNETA_GMAC2_PORT_RGMII BIT(4) 208c5aff182SThomas Petazzoni #define MVNETA_GMAC2_PORT_RESET BIT(6) 209c5aff182SThomas Petazzoni #define MVNETA_GMAC_STATUS 0x2c10 210c5aff182SThomas Petazzoni #define MVNETA_GMAC_LINK_UP BIT(0) 211c5aff182SThomas Petazzoni #define MVNETA_GMAC_SPEED_1000 BIT(1) 212c5aff182SThomas Petazzoni #define MVNETA_GMAC_SPEED_100 BIT(2) 213c5aff182SThomas Petazzoni #define MVNETA_GMAC_FULL_DUPLEX BIT(3) 214c5aff182SThomas Petazzoni #define MVNETA_GMAC_RX_FLOW_CTRL_ENABLE BIT(4) 215c5aff182SThomas Petazzoni #define MVNETA_GMAC_TX_FLOW_CTRL_ENABLE BIT(5) 216c5aff182SThomas Petazzoni #define MVNETA_GMAC_RX_FLOW_CTRL_ACTIVE BIT(6) 217c5aff182SThomas Petazzoni #define MVNETA_GMAC_TX_FLOW_CTRL_ACTIVE BIT(7) 218503f9aa9SRussell King #define MVNETA_GMAC_AN_COMPLETE BIT(11) 219503f9aa9SRussell King #define MVNETA_GMAC_SYNC_OK BIT(14) 220c5aff182SThomas Petazzoni #define MVNETA_GMAC_AUTONEG_CONFIG 0x2c0c 221c5aff182SThomas Petazzoni #define MVNETA_GMAC_FORCE_LINK_DOWN BIT(0) 222c5aff182SThomas Petazzoni #define MVNETA_GMAC_FORCE_LINK_PASS BIT(1) 223898b2970SStas Sergeev #define MVNETA_GMAC_INBAND_AN_ENABLE BIT(2) 22422f4bf8aSRussell King #define MVNETA_GMAC_AN_BYPASS_ENABLE BIT(3) 22522f4bf8aSRussell King #define MVNETA_GMAC_INBAND_RESTART_AN BIT(4) 226c5aff182SThomas Petazzoni #define MVNETA_GMAC_CONFIG_MII_SPEED BIT(5) 227c5aff182SThomas Petazzoni #define MVNETA_GMAC_CONFIG_GMII_SPEED BIT(6) 22871408602SThomas Petazzoni #define MVNETA_GMAC_AN_SPEED_EN BIT(7) 22922f4bf8aSRussell King #define MVNETA_GMAC_CONFIG_FLOW_CTRL BIT(8) 23022f4bf8aSRussell King #define MVNETA_GMAC_ADVERT_SYM_FLOW_CTRL BIT(9) 231898b2970SStas Sergeev #define MVNETA_GMAC_AN_FLOW_CTRL_EN BIT(11) 232c5aff182SThomas Petazzoni #define MVNETA_GMAC_CONFIG_FULL_DUPLEX BIT(12) 23371408602SThomas Petazzoni #define MVNETA_GMAC_AN_DUPLEX_EN BIT(13) 234da58a931SMaxime Chevallier #define MVNETA_GMAC_CTRL_4 0x2c90 235da58a931SMaxime Chevallier #define MVNETA_GMAC4_SHORT_PREAMBLE_ENABLE BIT(1) 236e483911fSAndrew Lunn #define MVNETA_MIB_COUNTERS_BASE 0x3000 237c5aff182SThomas Petazzoni #define MVNETA_MIB_LATE_COLLISION 0x7c 238c5aff182SThomas Petazzoni #define MVNETA_DA_FILT_SPEC_MCAST 0x3400 239c5aff182SThomas Petazzoni #define MVNETA_DA_FILT_OTH_MCAST 0x3500 240c5aff182SThomas Petazzoni #define MVNETA_DA_FILT_UCAST_BASE 0x3600 241c5aff182SThomas Petazzoni #define MVNETA_TXQ_BASE_ADDR_REG(q) (0x3c00 + ((q) << 2)) 242c5aff182SThomas Petazzoni #define MVNETA_TXQ_SIZE_REG(q) (0x3c20 + ((q) << 2)) 243c5aff182SThomas Petazzoni #define MVNETA_TXQ_SENT_THRESH_ALL_MASK 0x3fff0000 244c5aff182SThomas Petazzoni #define MVNETA_TXQ_SENT_THRESH_MASK(coal) ((coal) << 16) 245c5aff182SThomas Petazzoni #define MVNETA_TXQ_UPDATE_REG(q) (0x3c60 + ((q) << 2)) 246c5aff182SThomas Petazzoni #define MVNETA_TXQ_DEC_SENT_SHIFT 16 2472a90f7e1SSimon Guinot #define MVNETA_TXQ_DEC_SENT_MASK 0xff 248c5aff182SThomas Petazzoni #define MVNETA_TXQ_STATUS_REG(q) (0x3c40 + ((q) << 2)) 249c5aff182SThomas Petazzoni #define MVNETA_TXQ_SENT_DESC_SHIFT 16 250c5aff182SThomas Petazzoni #define MVNETA_TXQ_SENT_DESC_MASK 0x3fff0000 251c5aff182SThomas Petazzoni #define MVNETA_PORT_TX_RESET 0x3cf0 252c5aff182SThomas Petazzoni #define MVNETA_PORT_TX_DMA_RESET BIT(0) 2532551dc9eSMaxime Chevallier #define MVNETA_TXQ_CMD1_REG 0x3e00 2542551dc9eSMaxime Chevallier #define MVNETA_TXQ_CMD1_BW_LIM_SEL_V1 BIT(3) 2552551dc9eSMaxime Chevallier #define MVNETA_TXQ_CMD1_BW_LIM_EN BIT(0) 2562551dc9eSMaxime Chevallier #define MVNETA_REFILL_NUM_CLK_REG 0x3e08 2572551dc9eSMaxime Chevallier #define MVNETA_REFILL_MAX_NUM_CLK 0x0000ffff 258c5aff182SThomas Petazzoni #define MVNETA_TX_MTU 0x3e0c 259c5aff182SThomas Petazzoni #define MVNETA_TX_TOKEN_SIZE 0x3e14 260c5aff182SThomas Petazzoni #define MVNETA_TX_TOKEN_SIZE_MAX 0xffffffff 2612551dc9eSMaxime Chevallier #define MVNETA_TXQ_BUCKET_REFILL_REG(q) (0x3e20 + ((q) << 2)) 2622551dc9eSMaxime Chevallier #define MVNETA_TXQ_BUCKET_REFILL_PERIOD_MASK 0x3ff00000 2632551dc9eSMaxime Chevallier #define MVNETA_TXQ_BUCKET_REFILL_PERIOD_SHIFT 20 2642551dc9eSMaxime Chevallier #define MVNETA_TXQ_BUCKET_REFILL_VALUE_MAX 0x0007ffff 265c5aff182SThomas Petazzoni #define MVNETA_TXQ_TOKEN_SIZE_REG(q) (0x3e40 + ((q) << 2)) 266c5aff182SThomas Petazzoni #define MVNETA_TXQ_TOKEN_SIZE_MAX 0x7fffffff 267c5aff182SThomas Petazzoni 2682551dc9eSMaxime Chevallier /* The values of the bucket refill base period and refill period are taken from 2692551dc9eSMaxime Chevallier * the reference manual, and adds up to a base resolution of 10Kbps. This allows 2702551dc9eSMaxime Chevallier * to cover all rate-limit values from 10Kbps up to 5Gbps 2712551dc9eSMaxime Chevallier */ 2722551dc9eSMaxime Chevallier 2732551dc9eSMaxime Chevallier /* Base period for the rate limit algorithm */ 2742551dc9eSMaxime Chevallier #define MVNETA_TXQ_BUCKET_REFILL_BASE_PERIOD_NS 100 2752551dc9eSMaxime Chevallier 2762551dc9eSMaxime Chevallier /* Number of Base Period to wait between each bucket refill */ 2772551dc9eSMaxime Chevallier #define MVNETA_TXQ_BUCKET_REFILL_PERIOD 1000 2782551dc9eSMaxime Chevallier 2792551dc9eSMaxime Chevallier /* The base resolution for rate limiting, in bps. Any max_rate value should be 2802551dc9eSMaxime Chevallier * a multiple of that value. 2812551dc9eSMaxime Chevallier */ 2822551dc9eSMaxime Chevallier #define MVNETA_TXQ_RATE_LIMIT_RESOLUTION (NSEC_PER_SEC / \ 2832551dc9eSMaxime Chevallier (MVNETA_TXQ_BUCKET_REFILL_BASE_PERIOD_NS * \ 2842551dc9eSMaxime Chevallier MVNETA_TXQ_BUCKET_REFILL_PERIOD)) 2852551dc9eSMaxime Chevallier 2866d81f451SRussell King #define MVNETA_LPI_CTRL_0 0x2cc0 2876d81f451SRussell King #define MVNETA_LPI_CTRL_1 0x2cc4 2886d81f451SRussell King #define MVNETA_LPI_REQUEST_ENABLE BIT(0) 2896d81f451SRussell King #define MVNETA_LPI_CTRL_2 0x2cc8 2906d81f451SRussell King #define MVNETA_LPI_STATUS 0x2ccc 2916d81f451SRussell King 292c5aff182SThomas Petazzoni #define MVNETA_CAUSE_TXQ_SENT_DESC_ALL_MASK 0xff 293c5aff182SThomas Petazzoni 294c5aff182SThomas Petazzoni /* Descriptor ring Macros */ 295c5aff182SThomas Petazzoni #define MVNETA_QUEUE_NEXT_DESC(q, index) \ 296c5aff182SThomas Petazzoni (((index) < (q)->last_desc) ? ((index) + 1) : 0) 297c5aff182SThomas Petazzoni 298c5aff182SThomas Petazzoni /* Various constants */ 299c5aff182SThomas Petazzoni 300c5aff182SThomas Petazzoni /* Coalescing */ 30106708f81SDmitri Epshtein #define MVNETA_TXDONE_COAL_PKTS 0 /* interrupt per packet */ 302c5aff182SThomas Petazzoni #define MVNETA_RX_COAL_PKTS 32 303c5aff182SThomas Petazzoni #define MVNETA_RX_COAL_USEC 100 304c5aff182SThomas Petazzoni 3056a20c175SThomas Petazzoni /* The two bytes Marvell header. Either contains a special value used 306c5aff182SThomas Petazzoni * by Marvell switches when a specific hardware mode is enabled (not 307c5aff182SThomas Petazzoni * supported by this driver) or is filled automatically by zeroes on 308c5aff182SThomas Petazzoni * the RX side. Those two bytes being at the front of the Ethernet 309c5aff182SThomas Petazzoni * header, they allow to have the IP header aligned on a 4 bytes 310c5aff182SThomas Petazzoni * boundary automatically: the hardware skips those two bytes on its 311c5aff182SThomas Petazzoni * own. 312c5aff182SThomas Petazzoni */ 313c5aff182SThomas Petazzoni #define MVNETA_MH_SIZE 2 314c5aff182SThomas Petazzoni 315c5aff182SThomas Petazzoni #define MVNETA_VLAN_TAG_LEN 4 316c5aff182SThomas Petazzoni 3179110ee07SMarcin Wojtas #define MVNETA_TX_CSUM_DEF_SIZE 1600 318c5aff182SThomas Petazzoni #define MVNETA_TX_CSUM_MAX_SIZE 9800 319dc35a10fSMarcin Wojtas #define MVNETA_ACC_MODE_EXT1 1 320dc35a10fSMarcin Wojtas #define MVNETA_ACC_MODE_EXT2 2 321dc35a10fSMarcin Wojtas 322dc35a10fSMarcin Wojtas #define MVNETA_MAX_DECODE_WIN 6 323c5aff182SThomas Petazzoni 324c5aff182SThomas Petazzoni /* Timeout constants */ 325c5aff182SThomas Petazzoni #define MVNETA_TX_DISABLE_TIMEOUT_MSEC 1000 326c5aff182SThomas Petazzoni #define MVNETA_RX_DISABLE_TIMEOUT_MSEC 1000 327c5aff182SThomas Petazzoni #define MVNETA_TX_FIFO_EMPTY_TIMEOUT 10000 328c5aff182SThomas Petazzoni 329c5aff182SThomas Petazzoni #define MVNETA_TX_MTU_MAX 0x3ffff 330c5aff182SThomas Petazzoni 3319a401deaSGregory CLEMENT /* The RSS lookup table actually has 256 entries but we do not use 3329a401deaSGregory CLEMENT * them yet 3339a401deaSGregory CLEMENT */ 3349a401deaSGregory CLEMENT #define MVNETA_RSS_LU_TABLE_SIZE 1 3359a401deaSGregory CLEMENT 336c5aff182SThomas Petazzoni /* Max number of Rx descriptors */ 337c307e2a8SYelena Krivosheev #define MVNETA_MAX_RXD 512 338c5aff182SThomas Petazzoni 339c5aff182SThomas Petazzoni /* Max number of Tx descriptors */ 340c307e2a8SYelena Krivosheev #define MVNETA_MAX_TXD 1024 341c5aff182SThomas Petazzoni 3428eef5f97SEzequiel Garcia /* Max number of allowed TCP segments for software TSO */ 3438eef5f97SEzequiel Garcia #define MVNETA_MAX_TSO_SEGS 100 3448eef5f97SEzequiel Garcia 3458eef5f97SEzequiel Garcia #define MVNETA_MAX_SKB_DESCS (MVNETA_MAX_TSO_SEGS * 2 + MAX_SKB_FRAGS) 3468eef5f97SEzequiel Garcia 347c5aff182SThomas Petazzoni /* descriptor aligned size */ 348c5aff182SThomas Petazzoni #define MVNETA_DESC_ALIGNED_SIZE 32 349c5aff182SThomas Petazzoni 3508d5047cfSMarcin Wojtas /* Number of bytes to be taken into account by HW when putting incoming data 3518d5047cfSMarcin Wojtas * to the buffers. It is needed in case NET_SKB_PAD exceeds maximum packet 3528d5047cfSMarcin Wojtas * offset supported in MVNETA_RXQ_CONFIG_REG(q) registers. 3538d5047cfSMarcin Wojtas */ 3548d5047cfSMarcin Wojtas #define MVNETA_RX_PKT_OFFSET_CORRECTION 64 3558d5047cfSMarcin Wojtas 356c5aff182SThomas Petazzoni #define MVNETA_RX_PKT_SIZE(mtu) \ 357c5aff182SThomas Petazzoni ALIGN((mtu) + MVNETA_MH_SIZE + MVNETA_VLAN_TAG_LEN + \ 358c5aff182SThomas Petazzoni ETH_HLEN + ETH_FCS_LEN, \ 359c66e98c9SJisheng Zhang cache_line_size()) 360c5aff182SThomas Petazzoni 361ca23cb0bSSven Auhagen /* Driver assumes that the last 3 bits are 0 */ 362e2243720SAlexander Lobakin #define MVNETA_SKB_HEADROOM ALIGN(max(NET_SKB_PAD, XDP_PACKET_HEADROOM), 8) 3638dc9a088SLorenzo Bianconi #define MVNETA_SKB_PAD (SKB_DATA_ALIGN(sizeof(struct skb_shared_info) + \ 3640db51da7SLorenzo Bianconi MVNETA_SKB_HEADROOM)) 3658dc9a088SLorenzo Bianconi #define MVNETA_MAX_RX_BUF_SIZE (PAGE_SIZE - MVNETA_SKB_PAD) 3668dc9a088SLorenzo Bianconi 3672e3173a3SEzequiel Garcia #define IS_TSO_HEADER(txq, addr) \ 3682e3173a3SEzequiel Garcia ((addr >= txq->tso_hdrs_phys) && \ 3692e3173a3SEzequiel Garcia (addr < txq->tso_hdrs_phys + txq->size * TSO_HEADER_SIZE)) 3702e3173a3SEzequiel Garcia 371dc35a10fSMarcin Wojtas #define MVNETA_RX_GET_BM_POOL_ID(rxd) \ 372dc35a10fSMarcin Wojtas (((rxd)->status & MVNETA_RXD_BM_POOL_MASK) >> MVNETA_RXD_BM_POOL_SHIFT) 373c5aff182SThomas Petazzoni 3746d81f451SRussell King enum { 3756d81f451SRussell King ETHTOOL_STAT_EEE_WAKEUP, 37617a96da6SGregory CLEMENT ETHTOOL_STAT_SKB_ALLOC_ERR, 37717a96da6SGregory CLEMENT ETHTOOL_STAT_REFILL_ERR, 3783d866523SLorenzo Bianconi ETHTOOL_XDP_REDIRECT, 3793d866523SLorenzo Bianconi ETHTOOL_XDP_PASS, 3803d866523SLorenzo Bianconi ETHTOOL_XDP_DROP, 3813d866523SLorenzo Bianconi ETHTOOL_XDP_TX, 38215070919SJesper Dangaard Brouer ETHTOOL_XDP_TX_ERR, 38315070919SJesper Dangaard Brouer ETHTOOL_XDP_XMIT, 38415070919SJesper Dangaard Brouer ETHTOOL_XDP_XMIT_ERR, 3856d81f451SRussell King ETHTOOL_MAX_STATS, 3866d81f451SRussell King }; 3876d81f451SRussell King 3889b0cdefaSRussell King struct mvneta_statistic { 3899b0cdefaSRussell King unsigned short offset; 3909b0cdefaSRussell King unsigned short type; 3919b0cdefaSRussell King const char name[ETH_GSTRING_LEN]; 3929b0cdefaSRussell King }; 3939b0cdefaSRussell King 3949b0cdefaSRussell King #define T_REG_32 32 3959b0cdefaSRussell King #define T_REG_64 64 3966d81f451SRussell King #define T_SW 1 3979b0cdefaSRussell King 3986c8a8cfdSLorenzo Bianconi #define MVNETA_XDP_PASS 0 3996c8a8cfdSLorenzo Bianconi #define MVNETA_XDP_DROPPED BIT(0) 4006c8a8cfdSLorenzo Bianconi #define MVNETA_XDP_TX BIT(1) 4016c8a8cfdSLorenzo Bianconi #define MVNETA_XDP_REDIR BIT(2) 4020db51da7SLorenzo Bianconi 4039b0cdefaSRussell King static const struct mvneta_statistic mvneta_statistics[] = { 4049b0cdefaSRussell King { 0x3000, T_REG_64, "good_octets_received", }, 4059b0cdefaSRussell King { 0x3010, T_REG_32, "good_frames_received", }, 4069b0cdefaSRussell King { 0x3008, T_REG_32, "bad_octets_received", }, 4079b0cdefaSRussell King { 0x3014, T_REG_32, "bad_frames_received", }, 4089b0cdefaSRussell King { 0x3018, T_REG_32, "broadcast_frames_received", }, 4099b0cdefaSRussell King { 0x301c, T_REG_32, "multicast_frames_received", }, 4109b0cdefaSRussell King { 0x3050, T_REG_32, "unrec_mac_control_received", }, 4119b0cdefaSRussell King { 0x3058, T_REG_32, "good_fc_received", }, 4129b0cdefaSRussell King { 0x305c, T_REG_32, "bad_fc_received", }, 4139b0cdefaSRussell King { 0x3060, T_REG_32, "undersize_received", }, 4149b0cdefaSRussell King { 0x3064, T_REG_32, "fragments_received", }, 4159b0cdefaSRussell King { 0x3068, T_REG_32, "oversize_received", }, 4169b0cdefaSRussell King { 0x306c, T_REG_32, "jabber_received", }, 4179b0cdefaSRussell King { 0x3070, T_REG_32, "mac_receive_error", }, 4189b0cdefaSRussell King { 0x3074, T_REG_32, "bad_crc_event", }, 4199b0cdefaSRussell King { 0x3078, T_REG_32, "collision", }, 4209b0cdefaSRussell King { 0x307c, T_REG_32, "late_collision", }, 4219b0cdefaSRussell King { 0x2484, T_REG_32, "rx_discard", }, 4229b0cdefaSRussell King { 0x2488, T_REG_32, "rx_overrun", }, 4239b0cdefaSRussell King { 0x3020, T_REG_32, "frames_64_octets", }, 4249b0cdefaSRussell King { 0x3024, T_REG_32, "frames_65_to_127_octets", }, 4259b0cdefaSRussell King { 0x3028, T_REG_32, "frames_128_to_255_octets", }, 4269b0cdefaSRussell King { 0x302c, T_REG_32, "frames_256_to_511_octets", }, 4279b0cdefaSRussell King { 0x3030, T_REG_32, "frames_512_to_1023_octets", }, 4289b0cdefaSRussell King { 0x3034, T_REG_32, "frames_1024_to_max_octets", }, 4299b0cdefaSRussell King { 0x3038, T_REG_64, "good_octets_sent", }, 4309b0cdefaSRussell King { 0x3040, T_REG_32, "good_frames_sent", }, 4319b0cdefaSRussell King { 0x3044, T_REG_32, "excessive_collision", }, 4329b0cdefaSRussell King { 0x3048, T_REG_32, "multicast_frames_sent", }, 4339b0cdefaSRussell King { 0x304c, T_REG_32, "broadcast_frames_sent", }, 4349b0cdefaSRussell King { 0x3054, T_REG_32, "fc_sent", }, 4359b0cdefaSRussell King { 0x300c, T_REG_32, "internal_mac_transmit_err", }, 4366d81f451SRussell King { ETHTOOL_STAT_EEE_WAKEUP, T_SW, "eee_wakeup_errors", }, 43717a96da6SGregory CLEMENT { ETHTOOL_STAT_SKB_ALLOC_ERR, T_SW, "skb_alloc_errors", }, 43817a96da6SGregory CLEMENT { ETHTOOL_STAT_REFILL_ERR, T_SW, "refill_errors", }, 4397d51a015SLorenzo Bianconi { ETHTOOL_XDP_REDIRECT, T_SW, "rx_xdp_redirect", }, 4407d51a015SLorenzo Bianconi { ETHTOOL_XDP_PASS, T_SW, "rx_xdp_pass", }, 4417d51a015SLorenzo Bianconi { ETHTOOL_XDP_DROP, T_SW, "rx_xdp_drop", }, 4427d51a015SLorenzo Bianconi { ETHTOOL_XDP_TX, T_SW, "rx_xdp_tx", }, 44315070919SJesper Dangaard Brouer { ETHTOOL_XDP_TX_ERR, T_SW, "rx_xdp_tx_errors", }, 4447d51a015SLorenzo Bianconi { ETHTOOL_XDP_XMIT, T_SW, "tx_xdp_xmit", }, 44515070919SJesper Dangaard Brouer { ETHTOOL_XDP_XMIT_ERR, T_SW, "tx_xdp_xmit_errors", }, 4469b0cdefaSRussell King }; 4479b0cdefaSRussell King 448320d5441SLorenzo Bianconi struct mvneta_stats { 449320d5441SLorenzo Bianconi u64 rx_packets; 450320d5441SLorenzo Bianconi u64 rx_bytes; 451320d5441SLorenzo Bianconi u64 tx_packets; 452320d5441SLorenzo Bianconi u64 tx_bytes; 4533d866523SLorenzo Bianconi /* xdp */ 4543d866523SLorenzo Bianconi u64 xdp_redirect; 4553d866523SLorenzo Bianconi u64 xdp_pass; 4563d866523SLorenzo Bianconi u64 xdp_drop; 4577d51a015SLorenzo Bianconi u64 xdp_xmit; 45815070919SJesper Dangaard Brouer u64 xdp_xmit_err; 4593d866523SLorenzo Bianconi u64 xdp_tx; 46015070919SJesper Dangaard Brouer u64 xdp_tx_err; 461320d5441SLorenzo Bianconi }; 462320d5441SLorenzo Bianconi 4639ac41f3cSLorenzo Bianconi struct mvneta_ethtool_stats { 464320d5441SLorenzo Bianconi struct mvneta_stats ps; 4659ac41f3cSLorenzo Bianconi u64 skb_alloc_error; 4669ac41f3cSLorenzo Bianconi u64 refill_error; 4679ac41f3cSLorenzo Bianconi }; 4689ac41f3cSLorenzo Bianconi 46974c41b04Swilly tarreau struct mvneta_pcpu_stats { 470c5aff182SThomas Petazzoni struct u64_stats_sync syncp; 4719ac41f3cSLorenzo Bianconi 4729ac41f3cSLorenzo Bianconi struct mvneta_ethtool_stats es; 473c35947b8SLorenzo Bianconi u64 rx_dropped; 474c35947b8SLorenzo Bianconi u64 rx_errors; 475c5aff182SThomas Petazzoni }; 476c5aff182SThomas Petazzoni 47712bb03b4SMaxime Ripard struct mvneta_pcpu_port { 47812bb03b4SMaxime Ripard /* Pointer to the shared port */ 47912bb03b4SMaxime Ripard struct mvneta_port *pp; 48012bb03b4SMaxime Ripard 48112bb03b4SMaxime Ripard /* Pointer to the CPU-local NAPI struct */ 48212bb03b4SMaxime Ripard struct napi_struct napi; 48312bb03b4SMaxime Ripard 48412bb03b4SMaxime Ripard /* Cause of the previous interrupt */ 48512bb03b4SMaxime Ripard u32 cause_rx_tx; 48612bb03b4SMaxime Ripard }; 48712bb03b4SMaxime Ripard 48862a502ccSLorenzo Bianconi enum { 48962a502ccSLorenzo Bianconi __MVNETA_DOWN, 49062a502ccSLorenzo Bianconi }; 49162a502ccSLorenzo Bianconi 492c5aff182SThomas Petazzoni struct mvneta_port { 493dc35a10fSMarcin Wojtas u8 id; 49412bb03b4SMaxime Ripard struct mvneta_pcpu_port __percpu *ports; 49512bb03b4SMaxime Ripard struct mvneta_pcpu_stats __percpu *stats; 49612bb03b4SMaxime Ripard 49762a502ccSLorenzo Bianconi unsigned long state; 49862a502ccSLorenzo Bianconi 499c5aff182SThomas Petazzoni int pkt_size; 500c5aff182SThomas Petazzoni void __iomem *base; 501c5aff182SThomas Petazzoni struct mvneta_rx_queue *rxqs; 502c5aff182SThomas Petazzoni struct mvneta_tx_queue *txqs; 503c5aff182SThomas Petazzoni struct net_device *dev; 50484a3f4dbSSebastian Andrzej Siewior struct hlist_node node_online; 50584a3f4dbSSebastian Andrzej Siewior struct hlist_node node_dead; 50690b74c01SGregory CLEMENT int rxq_def; 5075888511eSGregory CLEMENT /* Protect the access to the percpu interrupt registers, 5085888511eSGregory CLEMENT * ensuring that the configuration remains coherent. 5095888511eSGregory CLEMENT */ 5105888511eSGregory CLEMENT spinlock_t lock; 511120cfa50SGregory CLEMENT bool is_stopped; 512c5aff182SThomas Petazzoni 5132636ac3cSMarcin Wojtas u32 cause_rx_tx; 5142636ac3cSMarcin Wojtas struct napi_struct napi; 5152636ac3cSMarcin Wojtas 5160db51da7SLorenzo Bianconi struct bpf_prog *xdp_prog; 5170db51da7SLorenzo Bianconi 518c5aff182SThomas Petazzoni /* Core clock */ 519189dd626SThomas Petazzoni struct clk *clk; 52015cc4a4aSJisheng Zhang /* AXI clock */ 52115cc4a4aSJisheng Zhang struct clk *clk_bus; 522c5aff182SThomas Petazzoni u8 mcast_count[256]; 523c5aff182SThomas Petazzoni u16 tx_ring_size; 524c5aff182SThomas Petazzoni u16 rx_ring_size; 525c5aff182SThomas Petazzoni 526c5aff182SThomas Petazzoni phy_interface_t phy_interface; 527503f9aa9SRussell King struct device_node *dn; 528b65657fcSSimon Guinot unsigned int tx_csum_limit; 529503f9aa9SRussell King struct phylink *phylink; 53044cc27e4SIoana Ciornei struct phylink_config phylink_config; 531c2e7d2dfSRussell King struct phylink_pcs phylink_pcs; 532a10c1c81SRussell King struct phy *comphy; 5339b0cdefaSRussell King 534dc35a10fSMarcin Wojtas struct mvneta_bm *bm_priv; 535dc35a10fSMarcin Wojtas struct mvneta_bm_pool *pool_long; 536dc35a10fSMarcin Wojtas struct mvneta_bm_pool *pool_short; 537dc35a10fSMarcin Wojtas int bm_win_id; 538dc35a10fSMarcin Wojtas 5396d81f451SRussell King bool eee_enabled; 5406d81f451SRussell King bool eee_active; 5416d81f451SRussell King bool tx_lpi_enabled; 5426d81f451SRussell King 5439b0cdefaSRussell King u64 ethtool_stats[ARRAY_SIZE(mvneta_statistics)]; 5449a401deaSGregory CLEMENT 5459a401deaSGregory CLEMENT u32 indir[MVNETA_RSS_LU_TABLE_SIZE]; 5462636ac3cSMarcin Wojtas 5472636ac3cSMarcin Wojtas /* Flags for special SoC configurations */ 5482636ac3cSMarcin Wojtas bool neta_armada3700; 5492d2a514cSChris Packham bool neta_ac5; 5508d5047cfSMarcin Wojtas u16 rx_offset_correction; 5519768b45cSJane Li const struct mbus_dram_target_info *dram_target_info; 552c5aff182SThomas Petazzoni }; 553c5aff182SThomas Petazzoni 5546a20c175SThomas Petazzoni /* The mvneta_tx_desc and mvneta_rx_desc structures describe the 555c5aff182SThomas Petazzoni * layout of the transmit and reception DMA descriptors, and their 556c5aff182SThomas Petazzoni * layout is therefore defined by the hardware design 557c5aff182SThomas Petazzoni */ 5586083ed44SThomas Petazzoni 559c5aff182SThomas Petazzoni #define MVNETA_TX_L3_OFF_SHIFT 0 560c5aff182SThomas Petazzoni #define MVNETA_TX_IP_HLEN_SHIFT 8 561c5aff182SThomas Petazzoni #define MVNETA_TX_L4_UDP BIT(16) 562c5aff182SThomas Petazzoni #define MVNETA_TX_L3_IP6 BIT(17) 563c5aff182SThomas Petazzoni #define MVNETA_TXD_IP_CSUM BIT(18) 564c5aff182SThomas Petazzoni #define MVNETA_TXD_Z_PAD BIT(19) 565c5aff182SThomas Petazzoni #define MVNETA_TXD_L_DESC BIT(20) 566c5aff182SThomas Petazzoni #define MVNETA_TXD_F_DESC BIT(21) 567c5aff182SThomas Petazzoni #define MVNETA_TXD_FLZ_DESC (MVNETA_TXD_Z_PAD | \ 568c5aff182SThomas Petazzoni MVNETA_TXD_L_DESC | \ 569c5aff182SThomas Petazzoni MVNETA_TXD_F_DESC) 570c5aff182SThomas Petazzoni #define MVNETA_TX_L4_CSUM_FULL BIT(30) 571c5aff182SThomas Petazzoni #define MVNETA_TX_L4_CSUM_NOT BIT(31) 572c5aff182SThomas Petazzoni 573c5aff182SThomas Petazzoni #define MVNETA_RXD_ERR_CRC 0x0 574dc35a10fSMarcin Wojtas #define MVNETA_RXD_BM_POOL_SHIFT 13 575dc35a10fSMarcin Wojtas #define MVNETA_RXD_BM_POOL_MASK (BIT(13) | BIT(14)) 576c5aff182SThomas Petazzoni #define MVNETA_RXD_ERR_SUMMARY BIT(16) 577c5aff182SThomas Petazzoni #define MVNETA_RXD_ERR_OVERRUN BIT(17) 578c5aff182SThomas Petazzoni #define MVNETA_RXD_ERR_LEN BIT(18) 579c5aff182SThomas Petazzoni #define MVNETA_RXD_ERR_RESOURCE (BIT(17) | BIT(18)) 580c5aff182SThomas Petazzoni #define MVNETA_RXD_ERR_CODE_MASK (BIT(17) | BIT(18)) 581c5aff182SThomas Petazzoni #define MVNETA_RXD_L3_IP4 BIT(25) 582562e2f46SYelena Krivosheev #define MVNETA_RXD_LAST_DESC BIT(26) 583562e2f46SYelena Krivosheev #define MVNETA_RXD_FIRST_DESC BIT(27) 584562e2f46SYelena Krivosheev #define MVNETA_RXD_FIRST_LAST_DESC (MVNETA_RXD_FIRST_DESC | \ 585562e2f46SYelena Krivosheev MVNETA_RXD_LAST_DESC) 586c5aff182SThomas Petazzoni #define MVNETA_RXD_L4_CSUM_OK BIT(30) 587c5aff182SThomas Petazzoni 5889ad8fef6SThomas Petazzoni #if defined(__LITTLE_ENDIAN) 5896083ed44SThomas Petazzoni struct mvneta_tx_desc { 5906083ed44SThomas Petazzoni u32 command; /* Options used by HW for packet transmitting.*/ 591fbd1d524SAlexandre Belloni u16 reserved1; /* csum_l4 (for future use) */ 5926083ed44SThomas Petazzoni u16 data_size; /* Data size of transmitted packet in bytes */ 5936083ed44SThomas Petazzoni u32 buf_phys_addr; /* Physical addr of transmitted buffer */ 5946083ed44SThomas Petazzoni u32 reserved2; /* hw_cmd - (for future use, PMT) */ 5956083ed44SThomas Petazzoni u32 reserved3[4]; /* Reserved - (for future use) */ 5966083ed44SThomas Petazzoni }; 5976083ed44SThomas Petazzoni 5986083ed44SThomas Petazzoni struct mvneta_rx_desc { 5996083ed44SThomas Petazzoni u32 status; /* Info about received packet */ 600c5aff182SThomas Petazzoni u16 reserved1; /* pnc_info - (for future use, PnC) */ 601c5aff182SThomas Petazzoni u16 data_size; /* Size of received packet in bytes */ 6026083ed44SThomas Petazzoni 603c5aff182SThomas Petazzoni u32 buf_phys_addr; /* Physical address of the buffer */ 604c5aff182SThomas Petazzoni u32 reserved2; /* pnc_flow_id (for future use, PnC) */ 6056083ed44SThomas Petazzoni 606c5aff182SThomas Petazzoni u32 buf_cookie; /* cookie for access to RX buffer in rx path */ 607c5aff182SThomas Petazzoni u16 reserved3; /* prefetch_cmd, for future use */ 608c5aff182SThomas Petazzoni u16 reserved4; /* csum_l4 - (for future use, PnC) */ 6096083ed44SThomas Petazzoni 610c5aff182SThomas Petazzoni u32 reserved5; /* pnc_extra PnC (for future use, PnC) */ 611c5aff182SThomas Petazzoni u32 reserved6; /* hw_cmd (for future use, PnC and HWF) */ 612c5aff182SThomas Petazzoni }; 6139ad8fef6SThomas Petazzoni #else 6149ad8fef6SThomas Petazzoni struct mvneta_tx_desc { 6159ad8fef6SThomas Petazzoni u16 data_size; /* Data size of transmitted packet in bytes */ 616fbd1d524SAlexandre Belloni u16 reserved1; /* csum_l4 (for future use) */ 6179ad8fef6SThomas Petazzoni u32 command; /* Options used by HW for packet transmitting.*/ 6189ad8fef6SThomas Petazzoni u32 reserved2; /* hw_cmd - (for future use, PMT) */ 6199ad8fef6SThomas Petazzoni u32 buf_phys_addr; /* Physical addr of transmitted buffer */ 6209ad8fef6SThomas Petazzoni u32 reserved3[4]; /* Reserved - (for future use) */ 6219ad8fef6SThomas Petazzoni }; 6229ad8fef6SThomas Petazzoni 6239ad8fef6SThomas Petazzoni struct mvneta_rx_desc { 6249ad8fef6SThomas Petazzoni u16 data_size; /* Size of received packet in bytes */ 6259ad8fef6SThomas Petazzoni u16 reserved1; /* pnc_info - (for future use, PnC) */ 6269ad8fef6SThomas Petazzoni u32 status; /* Info about received packet */ 6279ad8fef6SThomas Petazzoni 6289ad8fef6SThomas Petazzoni u32 reserved2; /* pnc_flow_id (for future use, PnC) */ 6299ad8fef6SThomas Petazzoni u32 buf_phys_addr; /* Physical address of the buffer */ 6309ad8fef6SThomas Petazzoni 6319ad8fef6SThomas Petazzoni u16 reserved4; /* csum_l4 - (for future use, PnC) */ 6329ad8fef6SThomas Petazzoni u16 reserved3; /* prefetch_cmd, for future use */ 6339ad8fef6SThomas Petazzoni u32 buf_cookie; /* cookie for access to RX buffer in rx path */ 6349ad8fef6SThomas Petazzoni 6359ad8fef6SThomas Petazzoni u32 reserved5; /* pnc_extra PnC (for future use, PnC) */ 6369ad8fef6SThomas Petazzoni u32 reserved6; /* hw_cmd (for future use, PnC and HWF) */ 6379ad8fef6SThomas Petazzoni }; 6389ad8fef6SThomas Petazzoni #endif 639c5aff182SThomas Petazzoni 6409e58c8b4SLorenzo Bianconi enum mvneta_tx_buf_type { 6419e58c8b4SLorenzo Bianconi MVNETA_TYPE_SKB, 6429e58c8b4SLorenzo Bianconi MVNETA_TYPE_XDP_TX, 6439e58c8b4SLorenzo Bianconi MVNETA_TYPE_XDP_NDO, 6449e58c8b4SLorenzo Bianconi }; 6459e58c8b4SLorenzo Bianconi 6469e58c8b4SLorenzo Bianconi struct mvneta_tx_buf { 6479e58c8b4SLorenzo Bianconi enum mvneta_tx_buf_type type; 6489e58c8b4SLorenzo Bianconi union { 6499e58c8b4SLorenzo Bianconi struct xdp_frame *xdpf; 6509e58c8b4SLorenzo Bianconi struct sk_buff *skb; 6519e58c8b4SLorenzo Bianconi }; 6529e58c8b4SLorenzo Bianconi }; 6539e58c8b4SLorenzo Bianconi 654c5aff182SThomas Petazzoni struct mvneta_tx_queue { 655c5aff182SThomas Petazzoni /* Number of this TX queue, in the range 0-7 */ 656c5aff182SThomas Petazzoni u8 id; 657c5aff182SThomas Petazzoni 658c5aff182SThomas Petazzoni /* Number of TX DMA descriptors in the descriptor ring */ 659c5aff182SThomas Petazzoni int size; 660c5aff182SThomas Petazzoni 661c5aff182SThomas Petazzoni /* Number of currently used TX DMA descriptor in the 6626a20c175SThomas Petazzoni * descriptor ring 6636a20c175SThomas Petazzoni */ 664c5aff182SThomas Petazzoni int count; 6652a90f7e1SSimon Guinot int pending; 6668eef5f97SEzequiel Garcia int tx_stop_threshold; 6678eef5f97SEzequiel Garcia int tx_wake_threshold; 668c5aff182SThomas Petazzoni 6699e58c8b4SLorenzo Bianconi /* Array of transmitted buffers */ 6709e58c8b4SLorenzo Bianconi struct mvneta_tx_buf *buf; 671c5aff182SThomas Petazzoni 672c5aff182SThomas Petazzoni /* Index of last TX DMA descriptor that was inserted */ 673c5aff182SThomas Petazzoni int txq_put_index; 674c5aff182SThomas Petazzoni 675c5aff182SThomas Petazzoni /* Index of the TX DMA descriptor to be cleaned up */ 676c5aff182SThomas Petazzoni int txq_get_index; 677c5aff182SThomas Petazzoni 678c5aff182SThomas Petazzoni u32 done_pkts_coal; 679c5aff182SThomas Petazzoni 680c5aff182SThomas Petazzoni /* Virtual address of the TX DMA descriptors array */ 681c5aff182SThomas Petazzoni struct mvneta_tx_desc *descs; 682c5aff182SThomas Petazzoni 683c5aff182SThomas Petazzoni /* DMA address of the TX DMA descriptors array */ 684c5aff182SThomas Petazzoni dma_addr_t descs_phys; 685c5aff182SThomas Petazzoni 686c5aff182SThomas Petazzoni /* Index of the last TX DMA descriptor */ 687c5aff182SThomas Petazzoni int last_desc; 688c5aff182SThomas Petazzoni 689c5aff182SThomas Petazzoni /* Index of the next TX DMA descriptor to process */ 690c5aff182SThomas Petazzoni int next_desc_to_proc; 6912adb719dSEzequiel Garcia 6922adb719dSEzequiel Garcia /* DMA buffers for TSO headers */ 6932adb719dSEzequiel Garcia char *tso_hdrs; 6942adb719dSEzequiel Garcia 6952adb719dSEzequiel Garcia /* DMA address of TSO headers */ 6962adb719dSEzequiel Garcia dma_addr_t tso_hdrs_phys; 69750bf8cb6SGregory CLEMENT 69850bf8cb6SGregory CLEMENT /* Affinity mask for CPUs*/ 69950bf8cb6SGregory CLEMENT cpumask_t affinity_mask; 700c5aff182SThomas Petazzoni }; 701c5aff182SThomas Petazzoni 702c5aff182SThomas Petazzoni struct mvneta_rx_queue { 703c5aff182SThomas Petazzoni /* rx queue number, in the range 0-7 */ 704c5aff182SThomas Petazzoni u8 id; 705c5aff182SThomas Petazzoni 706c5aff182SThomas Petazzoni /* num of rx descriptors in the rx descriptor ring */ 707c5aff182SThomas Petazzoni int size; 708c5aff182SThomas Petazzoni 709c5aff182SThomas Petazzoni u32 pkts_coal; 710c5aff182SThomas Petazzoni u32 time_coal; 711c5aff182SThomas Petazzoni 712568a3fa2SLorenzo Bianconi /* page_pool */ 713568a3fa2SLorenzo Bianconi struct page_pool *page_pool; 714568a3fa2SLorenzo Bianconi struct xdp_rxq_info xdp_rxq; 715568a3fa2SLorenzo Bianconi 716f88bee1cSGregory CLEMENT /* Virtual address of the RX buffer */ 717f88bee1cSGregory CLEMENT void **buf_virt_addr; 718f88bee1cSGregory CLEMENT 719c5aff182SThomas Petazzoni /* Virtual address of the RX DMA descriptors array */ 720c5aff182SThomas Petazzoni struct mvneta_rx_desc *descs; 721c5aff182SThomas Petazzoni 722c5aff182SThomas Petazzoni /* DMA address of the RX DMA descriptors array */ 723c5aff182SThomas Petazzoni dma_addr_t descs_phys; 724c5aff182SThomas Petazzoni 725c5aff182SThomas Petazzoni /* Index of the last RX DMA descriptor */ 726c5aff182SThomas Petazzoni int last_desc; 727c5aff182SThomas Petazzoni 728c5aff182SThomas Petazzoni /* Index of the next RX DMA descriptor to process */ 729c5aff182SThomas Petazzoni int next_desc_to_proc; 73017a96da6SGregory CLEMENT 731562e2f46SYelena Krivosheev /* Index of first RX DMA descriptor to refill */ 732562e2f46SYelena Krivosheev int first_to_refill; 733562e2f46SYelena Krivosheev u32 refill_num; 734c5aff182SThomas Petazzoni }; 735c5aff182SThomas Petazzoni 73684a3f4dbSSebastian Andrzej Siewior static enum cpuhp_state online_hpstate; 737edadb7faSEzequiel Garcia /* The hardware supports eight (8) rx queues, but we are only allowing 738edadb7faSEzequiel Garcia * the first one to be used. Therefore, let's just allocate one queue. 739edadb7faSEzequiel Garcia */ 740d8936657SMaxime Ripard static int rxq_number = 8; 741c5aff182SThomas Petazzoni static int txq_number = 8; 742c5aff182SThomas Petazzoni 743c5aff182SThomas Petazzoni static int rxq_def; 744c5aff182SThomas Petazzoni 745f19fadfcSwilly tarreau static int rx_copybreak __read_mostly = 256; 746f19fadfcSwilly tarreau 747dc35a10fSMarcin Wojtas /* HW BM need that each port be identify by a unique ID */ 748dc35a10fSMarcin Wojtas static int global_port_id; 749dc35a10fSMarcin Wojtas 750c5aff182SThomas Petazzoni #define MVNETA_DRIVER_NAME "mvneta" 751c5aff182SThomas Petazzoni #define MVNETA_DRIVER_VERSION "1.0" 752c5aff182SThomas Petazzoni 753c5aff182SThomas Petazzoni /* Utility/helper methods */ 754c5aff182SThomas Petazzoni 755c5aff182SThomas Petazzoni /* Write helper method */ 756c5aff182SThomas Petazzoni static void mvreg_write(struct mvneta_port *pp, u32 offset, u32 data) 757c5aff182SThomas Petazzoni { 758c5aff182SThomas Petazzoni writel(data, pp->base + offset); 759c5aff182SThomas Petazzoni } 760c5aff182SThomas Petazzoni 761c5aff182SThomas Petazzoni /* Read helper method */ 762c5aff182SThomas Petazzoni static u32 mvreg_read(struct mvneta_port *pp, u32 offset) 763c5aff182SThomas Petazzoni { 764c5aff182SThomas Petazzoni return readl(pp->base + offset); 765c5aff182SThomas Petazzoni } 766c5aff182SThomas Petazzoni 767c5aff182SThomas Petazzoni /* Increment txq get counter */ 768c5aff182SThomas Petazzoni static void mvneta_txq_inc_get(struct mvneta_tx_queue *txq) 769c5aff182SThomas Petazzoni { 770c5aff182SThomas Petazzoni txq->txq_get_index++; 771c5aff182SThomas Petazzoni if (txq->txq_get_index == txq->size) 772c5aff182SThomas Petazzoni txq->txq_get_index = 0; 773c5aff182SThomas Petazzoni } 774c5aff182SThomas Petazzoni 775c5aff182SThomas Petazzoni /* Increment txq put counter */ 776c5aff182SThomas Petazzoni static void mvneta_txq_inc_put(struct mvneta_tx_queue *txq) 777c5aff182SThomas Petazzoni { 778c5aff182SThomas Petazzoni txq->txq_put_index++; 779c5aff182SThomas Petazzoni if (txq->txq_put_index == txq->size) 780c5aff182SThomas Petazzoni txq->txq_put_index = 0; 781c5aff182SThomas Petazzoni } 782c5aff182SThomas Petazzoni 783c5aff182SThomas Petazzoni 784c5aff182SThomas Petazzoni /* Clear all MIB counters */ 785c5aff182SThomas Petazzoni static void mvneta_mib_counters_clear(struct mvneta_port *pp) 786c5aff182SThomas Petazzoni { 787c5aff182SThomas Petazzoni int i; 788c5aff182SThomas Petazzoni 789c5aff182SThomas Petazzoni /* Perform dummy reads from MIB counters */ 790c5aff182SThomas Petazzoni for (i = 0; i < MVNETA_MIB_LATE_COLLISION; i += 4) 791098c2fc6SZhang Changzhong mvreg_read(pp, (MVNETA_MIB_COUNTERS_BASE + i)); 792098c2fc6SZhang Changzhong mvreg_read(pp, MVNETA_RX_DISCARD_FRAME_COUNT); 793098c2fc6SZhang Changzhong mvreg_read(pp, MVNETA_OVERRUN_FRAME_COUNT); 794c5aff182SThomas Petazzoni } 795c5aff182SThomas Petazzoni 796c5aff182SThomas Petazzoni /* Get System Network Statistics */ 797bc1f4470Sstephen hemminger static void 7982dc0d2b4SBaoyou Xie mvneta_get_stats64(struct net_device *dev, 799c5aff182SThomas Petazzoni struct rtnl_link_stats64 *stats) 800c5aff182SThomas Petazzoni { 801c5aff182SThomas Petazzoni struct mvneta_port *pp = netdev_priv(dev); 802c5aff182SThomas Petazzoni unsigned int start; 80374c41b04Swilly tarreau int cpu; 804c5aff182SThomas Petazzoni 80574c41b04Swilly tarreau for_each_possible_cpu(cpu) { 80674c41b04Swilly tarreau struct mvneta_pcpu_stats *cpu_stats; 80774c41b04Swilly tarreau u64 rx_packets; 80874c41b04Swilly tarreau u64 rx_bytes; 809c35947b8SLorenzo Bianconi u64 rx_dropped; 810c35947b8SLorenzo Bianconi u64 rx_errors; 81174c41b04Swilly tarreau u64 tx_packets; 81274c41b04Swilly tarreau u64 tx_bytes; 813c5aff182SThomas Petazzoni 81474c41b04Swilly tarreau cpu_stats = per_cpu_ptr(pp->stats, cpu); 815c5aff182SThomas Petazzoni do { 816068c38adSThomas Gleixner start = u64_stats_fetch_begin(&cpu_stats->syncp); 817320d5441SLorenzo Bianconi rx_packets = cpu_stats->es.ps.rx_packets; 818320d5441SLorenzo Bianconi rx_bytes = cpu_stats->es.ps.rx_bytes; 819c35947b8SLorenzo Bianconi rx_dropped = cpu_stats->rx_dropped; 820c35947b8SLorenzo Bianconi rx_errors = cpu_stats->rx_errors; 821320d5441SLorenzo Bianconi tx_packets = cpu_stats->es.ps.tx_packets; 822320d5441SLorenzo Bianconi tx_bytes = cpu_stats->es.ps.tx_bytes; 823068c38adSThomas Gleixner } while (u64_stats_fetch_retry(&cpu_stats->syncp, start)); 824c5aff182SThomas Petazzoni 82574c41b04Swilly tarreau stats->rx_packets += rx_packets; 82674c41b04Swilly tarreau stats->rx_bytes += rx_bytes; 827c35947b8SLorenzo Bianconi stats->rx_dropped += rx_dropped; 828c35947b8SLorenzo Bianconi stats->rx_errors += rx_errors; 82974c41b04Swilly tarreau stats->tx_packets += tx_packets; 83074c41b04Swilly tarreau stats->tx_bytes += tx_bytes; 83174c41b04Swilly tarreau } 832c5aff182SThomas Petazzoni 833c5aff182SThomas Petazzoni stats->tx_dropped = dev->stats.tx_dropped; 834c5aff182SThomas Petazzoni } 835c5aff182SThomas Petazzoni 836c5aff182SThomas Petazzoni /* Rx descriptors helper methods */ 837c5aff182SThomas Petazzoni 8385428213cSwilly tarreau /* Checks whether the RX descriptor having this status is both the first 8395428213cSwilly tarreau * and the last descriptor for the RX packet. Each RX packet is currently 840c5aff182SThomas Petazzoni * received through a single RX descriptor, so not having each RX 841c5aff182SThomas Petazzoni * descriptor with its first and last bits set is an error 842c5aff182SThomas Petazzoni */ 8435428213cSwilly tarreau static int mvneta_rxq_desc_is_first_last(u32 status) 844c5aff182SThomas Petazzoni { 8455428213cSwilly tarreau return (status & MVNETA_RXD_FIRST_LAST_DESC) == 846c5aff182SThomas Petazzoni MVNETA_RXD_FIRST_LAST_DESC; 847c5aff182SThomas Petazzoni } 848c5aff182SThomas Petazzoni 849c5aff182SThomas Petazzoni /* Add number of descriptors ready to receive new packets */ 850c5aff182SThomas Petazzoni static void mvneta_rxq_non_occup_desc_add(struct mvneta_port *pp, 851c5aff182SThomas Petazzoni struct mvneta_rx_queue *rxq, 852c5aff182SThomas Petazzoni int ndescs) 853c5aff182SThomas Petazzoni { 854c5aff182SThomas Petazzoni /* Only MVNETA_RXQ_ADD_NON_OCCUPIED_MAX (255) descriptors can 8556a20c175SThomas Petazzoni * be added at once 8566a20c175SThomas Petazzoni */ 857c5aff182SThomas Petazzoni while (ndescs > MVNETA_RXQ_ADD_NON_OCCUPIED_MAX) { 858c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id), 859c5aff182SThomas Petazzoni (MVNETA_RXQ_ADD_NON_OCCUPIED_MAX << 860c5aff182SThomas Petazzoni MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT)); 861c5aff182SThomas Petazzoni ndescs -= MVNETA_RXQ_ADD_NON_OCCUPIED_MAX; 862c5aff182SThomas Petazzoni } 863c5aff182SThomas Petazzoni 864c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id), 865c5aff182SThomas Petazzoni (ndescs << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT)); 866c5aff182SThomas Petazzoni } 867c5aff182SThomas Petazzoni 868c5aff182SThomas Petazzoni /* Get number of RX descriptors occupied by received packets */ 869c5aff182SThomas Petazzoni static int mvneta_rxq_busy_desc_num_get(struct mvneta_port *pp, 870c5aff182SThomas Petazzoni struct mvneta_rx_queue *rxq) 871c5aff182SThomas Petazzoni { 872c5aff182SThomas Petazzoni u32 val; 873c5aff182SThomas Petazzoni 874c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_RXQ_STATUS_REG(rxq->id)); 875c5aff182SThomas Petazzoni return val & MVNETA_RXQ_OCCUPIED_ALL_MASK; 876c5aff182SThomas Petazzoni } 877c5aff182SThomas Petazzoni 8786a20c175SThomas Petazzoni /* Update num of rx desc called upon return from rx path or 879c5aff182SThomas Petazzoni * from mvneta_rxq_drop_pkts(). 880c5aff182SThomas Petazzoni */ 881c5aff182SThomas Petazzoni static void mvneta_rxq_desc_num_update(struct mvneta_port *pp, 882c5aff182SThomas Petazzoni struct mvneta_rx_queue *rxq, 883c5aff182SThomas Petazzoni int rx_done, int rx_filled) 884c5aff182SThomas Petazzoni { 885c5aff182SThomas Petazzoni u32 val; 886c5aff182SThomas Petazzoni 887c5aff182SThomas Petazzoni if ((rx_done <= 0xff) && (rx_filled <= 0xff)) { 888c5aff182SThomas Petazzoni val = rx_done | 889c5aff182SThomas Petazzoni (rx_filled << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT); 890c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id), val); 891c5aff182SThomas Petazzoni return; 892c5aff182SThomas Petazzoni } 893c5aff182SThomas Petazzoni 894c5aff182SThomas Petazzoni /* Only 255 descriptors can be added at once */ 895c5aff182SThomas Petazzoni while ((rx_done > 0) || (rx_filled > 0)) { 896c5aff182SThomas Petazzoni if (rx_done <= 0xff) { 897c5aff182SThomas Petazzoni val = rx_done; 898c5aff182SThomas Petazzoni rx_done = 0; 899c5aff182SThomas Petazzoni } else { 900c5aff182SThomas Petazzoni val = 0xff; 901c5aff182SThomas Petazzoni rx_done -= 0xff; 902c5aff182SThomas Petazzoni } 903c5aff182SThomas Petazzoni if (rx_filled <= 0xff) { 904c5aff182SThomas Petazzoni val |= rx_filled << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT; 905c5aff182SThomas Petazzoni rx_filled = 0; 906c5aff182SThomas Petazzoni } else { 907c5aff182SThomas Petazzoni val |= 0xff << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT; 908c5aff182SThomas Petazzoni rx_filled -= 0xff; 909c5aff182SThomas Petazzoni } 910c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id), val); 911c5aff182SThomas Petazzoni } 912c5aff182SThomas Petazzoni } 913c5aff182SThomas Petazzoni 914c5aff182SThomas Petazzoni /* Get pointer to next RX descriptor to be processed by SW */ 915c5aff182SThomas Petazzoni static struct mvneta_rx_desc * 916c5aff182SThomas Petazzoni mvneta_rxq_next_desc_get(struct mvneta_rx_queue *rxq) 917c5aff182SThomas Petazzoni { 918c5aff182SThomas Petazzoni int rx_desc = rxq->next_desc_to_proc; 919c5aff182SThomas Petazzoni 920c5aff182SThomas Petazzoni rxq->next_desc_to_proc = MVNETA_QUEUE_NEXT_DESC(rxq, rx_desc); 92134e4179dSwilly tarreau prefetch(rxq->descs + rxq->next_desc_to_proc); 922c5aff182SThomas Petazzoni return rxq->descs + rx_desc; 923c5aff182SThomas Petazzoni } 924c5aff182SThomas Petazzoni 925c5aff182SThomas Petazzoni /* Change maximum receive size of the port. */ 926c5aff182SThomas Petazzoni static void mvneta_max_rx_size_set(struct mvneta_port *pp, int max_rx_size) 927c5aff182SThomas Petazzoni { 928c5aff182SThomas Petazzoni u32 val; 929c5aff182SThomas Petazzoni 930c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_GMAC_CTRL_0); 931c5aff182SThomas Petazzoni val &= ~MVNETA_GMAC_MAX_RX_SIZE_MASK; 932c5aff182SThomas Petazzoni val |= ((max_rx_size - MVNETA_MH_SIZE) / 2) << 933c5aff182SThomas Petazzoni MVNETA_GMAC_MAX_RX_SIZE_SHIFT; 934c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_GMAC_CTRL_0, val); 935c5aff182SThomas Petazzoni } 936c5aff182SThomas Petazzoni 937c5aff182SThomas Petazzoni 938c5aff182SThomas Petazzoni /* Set rx queue offset */ 939c5aff182SThomas Petazzoni static void mvneta_rxq_offset_set(struct mvneta_port *pp, 940c5aff182SThomas Petazzoni struct mvneta_rx_queue *rxq, 941c5aff182SThomas Petazzoni int offset) 942c5aff182SThomas Petazzoni { 943c5aff182SThomas Petazzoni u32 val; 944c5aff182SThomas Petazzoni 945c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_RXQ_CONFIG_REG(rxq->id)); 946c5aff182SThomas Petazzoni val &= ~MVNETA_RXQ_PKT_OFFSET_ALL_MASK; 947c5aff182SThomas Petazzoni 948c5aff182SThomas Petazzoni /* Offset is in */ 949c5aff182SThomas Petazzoni val |= MVNETA_RXQ_PKT_OFFSET_MASK(offset >> 3); 950c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_RXQ_CONFIG_REG(rxq->id), val); 951c5aff182SThomas Petazzoni } 952c5aff182SThomas Petazzoni 953c5aff182SThomas Petazzoni 954c5aff182SThomas Petazzoni /* Tx descriptors helper methods */ 955c5aff182SThomas Petazzoni 956c5aff182SThomas Petazzoni /* Update HW with number of TX descriptors to be sent */ 957c5aff182SThomas Petazzoni static void mvneta_txq_pend_desc_add(struct mvneta_port *pp, 958c5aff182SThomas Petazzoni struct mvneta_tx_queue *txq, 959c5aff182SThomas Petazzoni int pend_desc) 960c5aff182SThomas Petazzoni { 961c5aff182SThomas Petazzoni u32 val; 962c5aff182SThomas Petazzoni 9630d63785cSSimon Guinot pend_desc += txq->pending; 9640d63785cSSimon Guinot 9650d63785cSSimon Guinot /* Only 255 Tx descriptors can be added at once */ 9660d63785cSSimon Guinot do { 9670d63785cSSimon Guinot val = min(pend_desc, 255); 968c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val); 9690d63785cSSimon Guinot pend_desc -= val; 9700d63785cSSimon Guinot } while (pend_desc > 0); 9712a90f7e1SSimon Guinot txq->pending = 0; 972c5aff182SThomas Petazzoni } 973c5aff182SThomas Petazzoni 974c5aff182SThomas Petazzoni /* Get pointer to next TX descriptor to be processed (send) by HW */ 975c5aff182SThomas Petazzoni static struct mvneta_tx_desc * 976c5aff182SThomas Petazzoni mvneta_txq_next_desc_get(struct mvneta_tx_queue *txq) 977c5aff182SThomas Petazzoni { 978c5aff182SThomas Petazzoni int tx_desc = txq->next_desc_to_proc; 979c5aff182SThomas Petazzoni 980c5aff182SThomas Petazzoni txq->next_desc_to_proc = MVNETA_QUEUE_NEXT_DESC(txq, tx_desc); 981c5aff182SThomas Petazzoni return txq->descs + tx_desc; 982c5aff182SThomas Petazzoni } 983c5aff182SThomas Petazzoni 984c5aff182SThomas Petazzoni /* Release the last allocated TX descriptor. Useful to handle DMA 9856a20c175SThomas Petazzoni * mapping failures in the TX path. 9866a20c175SThomas Petazzoni */ 987c5aff182SThomas Petazzoni static void mvneta_txq_desc_put(struct mvneta_tx_queue *txq) 988c5aff182SThomas Petazzoni { 989c5aff182SThomas Petazzoni if (txq->next_desc_to_proc == 0) 990c5aff182SThomas Petazzoni txq->next_desc_to_proc = txq->last_desc - 1; 991c5aff182SThomas Petazzoni else 992c5aff182SThomas Petazzoni txq->next_desc_to_proc--; 993c5aff182SThomas Petazzoni } 994c5aff182SThomas Petazzoni 995c5aff182SThomas Petazzoni /* Set rxq buf size */ 996c5aff182SThomas Petazzoni static void mvneta_rxq_buf_size_set(struct mvneta_port *pp, 997c5aff182SThomas Petazzoni struct mvneta_rx_queue *rxq, 998c5aff182SThomas Petazzoni int buf_size) 999c5aff182SThomas Petazzoni { 1000c5aff182SThomas Petazzoni u32 val; 1001c5aff182SThomas Petazzoni 1002c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_RXQ_SIZE_REG(rxq->id)); 1003c5aff182SThomas Petazzoni 1004c5aff182SThomas Petazzoni val &= ~MVNETA_RXQ_BUF_SIZE_MASK; 1005c5aff182SThomas Petazzoni val |= ((buf_size >> 3) << MVNETA_RXQ_BUF_SIZE_SHIFT); 1006c5aff182SThomas Petazzoni 1007c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_RXQ_SIZE_REG(rxq->id), val); 1008c5aff182SThomas Petazzoni } 1009c5aff182SThomas Petazzoni 1010c5aff182SThomas Petazzoni /* Disable buffer management (BM) */ 1011c5aff182SThomas Petazzoni static void mvneta_rxq_bm_disable(struct mvneta_port *pp, 1012c5aff182SThomas Petazzoni struct mvneta_rx_queue *rxq) 1013c5aff182SThomas Petazzoni { 1014c5aff182SThomas Petazzoni u32 val; 1015c5aff182SThomas Petazzoni 1016c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_RXQ_CONFIG_REG(rxq->id)); 1017c5aff182SThomas Petazzoni val &= ~MVNETA_RXQ_HW_BUF_ALLOC; 1018c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_RXQ_CONFIG_REG(rxq->id), val); 1019c5aff182SThomas Petazzoni } 1020c5aff182SThomas Petazzoni 1021dc35a10fSMarcin Wojtas /* Enable buffer management (BM) */ 1022dc35a10fSMarcin Wojtas static void mvneta_rxq_bm_enable(struct mvneta_port *pp, 1023dc35a10fSMarcin Wojtas struct mvneta_rx_queue *rxq) 1024dc35a10fSMarcin Wojtas { 1025dc35a10fSMarcin Wojtas u32 val; 1026dc35a10fSMarcin Wojtas 1027dc35a10fSMarcin Wojtas val = mvreg_read(pp, MVNETA_RXQ_CONFIG_REG(rxq->id)); 1028dc35a10fSMarcin Wojtas val |= MVNETA_RXQ_HW_BUF_ALLOC; 1029dc35a10fSMarcin Wojtas mvreg_write(pp, MVNETA_RXQ_CONFIG_REG(rxq->id), val); 1030dc35a10fSMarcin Wojtas } 1031dc35a10fSMarcin Wojtas 1032dc35a10fSMarcin Wojtas /* Notify HW about port's assignment of pool for bigger packets */ 1033dc35a10fSMarcin Wojtas static void mvneta_rxq_long_pool_set(struct mvneta_port *pp, 1034dc35a10fSMarcin Wojtas struct mvneta_rx_queue *rxq) 1035dc35a10fSMarcin Wojtas { 1036dc35a10fSMarcin Wojtas u32 val; 1037dc35a10fSMarcin Wojtas 1038dc35a10fSMarcin Wojtas val = mvreg_read(pp, MVNETA_RXQ_CONFIG_REG(rxq->id)); 1039dc35a10fSMarcin Wojtas val &= ~MVNETA_RXQ_LONG_POOL_ID_MASK; 1040dc35a10fSMarcin Wojtas val |= (pp->pool_long->id << MVNETA_RXQ_LONG_POOL_ID_SHIFT); 1041dc35a10fSMarcin Wojtas 1042dc35a10fSMarcin Wojtas mvreg_write(pp, MVNETA_RXQ_CONFIG_REG(rxq->id), val); 1043dc35a10fSMarcin Wojtas } 1044dc35a10fSMarcin Wojtas 1045dc35a10fSMarcin Wojtas /* Notify HW about port's assignment of pool for smaller packets */ 1046dc35a10fSMarcin Wojtas static void mvneta_rxq_short_pool_set(struct mvneta_port *pp, 1047dc35a10fSMarcin Wojtas struct mvneta_rx_queue *rxq) 1048dc35a10fSMarcin Wojtas { 1049dc35a10fSMarcin Wojtas u32 val; 1050dc35a10fSMarcin Wojtas 1051dc35a10fSMarcin Wojtas val = mvreg_read(pp, MVNETA_RXQ_CONFIG_REG(rxq->id)); 1052dc35a10fSMarcin Wojtas val &= ~MVNETA_RXQ_SHORT_POOL_ID_MASK; 1053dc35a10fSMarcin Wojtas val |= (pp->pool_short->id << MVNETA_RXQ_SHORT_POOL_ID_SHIFT); 1054dc35a10fSMarcin Wojtas 1055dc35a10fSMarcin Wojtas mvreg_write(pp, MVNETA_RXQ_CONFIG_REG(rxq->id), val); 1056dc35a10fSMarcin Wojtas } 1057dc35a10fSMarcin Wojtas 1058dc35a10fSMarcin Wojtas /* Set port's receive buffer size for assigned BM pool */ 1059dc35a10fSMarcin Wojtas static inline void mvneta_bm_pool_bufsize_set(struct mvneta_port *pp, 1060dc35a10fSMarcin Wojtas int buf_size, 1061dc35a10fSMarcin Wojtas u8 pool_id) 1062dc35a10fSMarcin Wojtas { 1063dc35a10fSMarcin Wojtas u32 val; 1064dc35a10fSMarcin Wojtas 1065dc35a10fSMarcin Wojtas if (!IS_ALIGNED(buf_size, 8)) { 1066dc35a10fSMarcin Wojtas dev_warn(pp->dev->dev.parent, 1067dc35a10fSMarcin Wojtas "illegal buf_size value %d, round to %d\n", 1068dc35a10fSMarcin Wojtas buf_size, ALIGN(buf_size, 8)); 1069dc35a10fSMarcin Wojtas buf_size = ALIGN(buf_size, 8); 1070dc35a10fSMarcin Wojtas } 1071dc35a10fSMarcin Wojtas 1072dc35a10fSMarcin Wojtas val = mvreg_read(pp, MVNETA_PORT_POOL_BUFFER_SZ_REG(pool_id)); 1073dc35a10fSMarcin Wojtas val |= buf_size & MVNETA_PORT_POOL_BUFFER_SZ_MASK; 1074dc35a10fSMarcin Wojtas mvreg_write(pp, MVNETA_PORT_POOL_BUFFER_SZ_REG(pool_id), val); 1075dc35a10fSMarcin Wojtas } 1076dc35a10fSMarcin Wojtas 1077dc35a10fSMarcin Wojtas /* Configure MBUS window in order to enable access BM internal SRAM */ 1078dc35a10fSMarcin Wojtas static int mvneta_mbus_io_win_set(struct mvneta_port *pp, u32 base, u32 wsize, 1079dc35a10fSMarcin Wojtas u8 target, u8 attr) 1080dc35a10fSMarcin Wojtas { 1081dc35a10fSMarcin Wojtas u32 win_enable, win_protect; 1082dc35a10fSMarcin Wojtas int i; 1083dc35a10fSMarcin Wojtas 1084dc35a10fSMarcin Wojtas win_enable = mvreg_read(pp, MVNETA_BASE_ADDR_ENABLE); 1085dc35a10fSMarcin Wojtas 1086dc35a10fSMarcin Wojtas if (pp->bm_win_id < 0) { 1087dc35a10fSMarcin Wojtas /* Find first not occupied window */ 1088dc35a10fSMarcin Wojtas for (i = 0; i < MVNETA_MAX_DECODE_WIN; i++) { 1089dc35a10fSMarcin Wojtas if (win_enable & (1 << i)) { 1090dc35a10fSMarcin Wojtas pp->bm_win_id = i; 1091dc35a10fSMarcin Wojtas break; 1092dc35a10fSMarcin Wojtas } 1093dc35a10fSMarcin Wojtas } 1094dc35a10fSMarcin Wojtas if (i == MVNETA_MAX_DECODE_WIN) 1095dc35a10fSMarcin Wojtas return -ENOMEM; 1096dc35a10fSMarcin Wojtas } else { 1097dc35a10fSMarcin Wojtas i = pp->bm_win_id; 1098dc35a10fSMarcin Wojtas } 1099dc35a10fSMarcin Wojtas 1100dc35a10fSMarcin Wojtas mvreg_write(pp, MVNETA_WIN_BASE(i), 0); 1101dc35a10fSMarcin Wojtas mvreg_write(pp, MVNETA_WIN_SIZE(i), 0); 1102dc35a10fSMarcin Wojtas 1103dc35a10fSMarcin Wojtas if (i < 4) 1104dc35a10fSMarcin Wojtas mvreg_write(pp, MVNETA_WIN_REMAP(i), 0); 1105dc35a10fSMarcin Wojtas 1106dc35a10fSMarcin Wojtas mvreg_write(pp, MVNETA_WIN_BASE(i), (base & 0xffff0000) | 1107dc35a10fSMarcin Wojtas (attr << 8) | target); 1108dc35a10fSMarcin Wojtas 1109dc35a10fSMarcin Wojtas mvreg_write(pp, MVNETA_WIN_SIZE(i), (wsize - 1) & 0xffff0000); 1110dc35a10fSMarcin Wojtas 1111dc35a10fSMarcin Wojtas win_protect = mvreg_read(pp, MVNETA_ACCESS_PROTECT_ENABLE); 1112dc35a10fSMarcin Wojtas win_protect |= 3 << (2 * i); 1113dc35a10fSMarcin Wojtas mvreg_write(pp, MVNETA_ACCESS_PROTECT_ENABLE, win_protect); 1114dc35a10fSMarcin Wojtas 1115dc35a10fSMarcin Wojtas win_enable &= ~(1 << i); 1116dc35a10fSMarcin Wojtas mvreg_write(pp, MVNETA_BASE_ADDR_ENABLE, win_enable); 1117dc35a10fSMarcin Wojtas 1118dc35a10fSMarcin Wojtas return 0; 1119dc35a10fSMarcin Wojtas } 1120dc35a10fSMarcin Wojtas 11212636ac3cSMarcin Wojtas static int mvneta_bm_port_mbus_init(struct mvneta_port *pp) 1122dc35a10fSMarcin Wojtas { 11232636ac3cSMarcin Wojtas u32 wsize; 1124dc35a10fSMarcin Wojtas u8 target, attr; 1125dc35a10fSMarcin Wojtas int err; 1126dc35a10fSMarcin Wojtas 1127dc35a10fSMarcin Wojtas /* Get BM window information */ 1128dc35a10fSMarcin Wojtas err = mvebu_mbus_get_io_win_info(pp->bm_priv->bppi_phys_addr, &wsize, 1129dc35a10fSMarcin Wojtas &target, &attr); 1130dc35a10fSMarcin Wojtas if (err < 0) 1131dc35a10fSMarcin Wojtas return err; 1132dc35a10fSMarcin Wojtas 1133dc35a10fSMarcin Wojtas pp->bm_win_id = -1; 1134dc35a10fSMarcin Wojtas 1135dc35a10fSMarcin Wojtas /* Open NETA -> BM window */ 1136dc35a10fSMarcin Wojtas err = mvneta_mbus_io_win_set(pp, pp->bm_priv->bppi_phys_addr, wsize, 1137dc35a10fSMarcin Wojtas target, attr); 1138dc35a10fSMarcin Wojtas if (err < 0) { 1139dc35a10fSMarcin Wojtas netdev_info(pp->dev, "fail to configure mbus window to BM\n"); 1140dc35a10fSMarcin Wojtas return err; 1141dc35a10fSMarcin Wojtas } 11422636ac3cSMarcin Wojtas return 0; 11432636ac3cSMarcin Wojtas } 11442636ac3cSMarcin Wojtas 11452636ac3cSMarcin Wojtas /* Assign and initialize pools for port. In case of fail 11462636ac3cSMarcin Wojtas * buffer manager will remain disabled for current port. 11472636ac3cSMarcin Wojtas */ 11482636ac3cSMarcin Wojtas static int mvneta_bm_port_init(struct platform_device *pdev, 11492636ac3cSMarcin Wojtas struct mvneta_port *pp) 11502636ac3cSMarcin Wojtas { 11512636ac3cSMarcin Wojtas struct device_node *dn = pdev->dev.of_node; 11522636ac3cSMarcin Wojtas u32 long_pool_id, short_pool_id; 11532636ac3cSMarcin Wojtas 11542636ac3cSMarcin Wojtas if (!pp->neta_armada3700) { 11552636ac3cSMarcin Wojtas int ret; 11562636ac3cSMarcin Wojtas 11572636ac3cSMarcin Wojtas ret = mvneta_bm_port_mbus_init(pp); 11582636ac3cSMarcin Wojtas if (ret) 11592636ac3cSMarcin Wojtas return ret; 11602636ac3cSMarcin Wojtas } 1161dc35a10fSMarcin Wojtas 1162dc35a10fSMarcin Wojtas if (of_property_read_u32(dn, "bm,pool-long", &long_pool_id)) { 1163dc35a10fSMarcin Wojtas netdev_info(pp->dev, "missing long pool id\n"); 1164dc35a10fSMarcin Wojtas return -EINVAL; 1165dc35a10fSMarcin Wojtas } 1166dc35a10fSMarcin Wojtas 1167dc35a10fSMarcin Wojtas /* Create port's long pool depending on mtu */ 1168dc35a10fSMarcin Wojtas pp->pool_long = mvneta_bm_pool_use(pp->bm_priv, long_pool_id, 1169dc35a10fSMarcin Wojtas MVNETA_BM_LONG, pp->id, 1170dc35a10fSMarcin Wojtas MVNETA_RX_PKT_SIZE(pp->dev->mtu)); 1171dc35a10fSMarcin Wojtas if (!pp->pool_long) { 1172dc35a10fSMarcin Wojtas netdev_info(pp->dev, "fail to obtain long pool for port\n"); 1173dc35a10fSMarcin Wojtas return -ENOMEM; 1174dc35a10fSMarcin Wojtas } 1175dc35a10fSMarcin Wojtas 1176dc35a10fSMarcin Wojtas pp->pool_long->port_map |= 1 << pp->id; 1177dc35a10fSMarcin Wojtas 1178dc35a10fSMarcin Wojtas mvneta_bm_pool_bufsize_set(pp, pp->pool_long->buf_size, 1179dc35a10fSMarcin Wojtas pp->pool_long->id); 1180dc35a10fSMarcin Wojtas 1181dc35a10fSMarcin Wojtas /* If short pool id is not defined, assume using single pool */ 1182dc35a10fSMarcin Wojtas if (of_property_read_u32(dn, "bm,pool-short", &short_pool_id)) 1183dc35a10fSMarcin Wojtas short_pool_id = long_pool_id; 1184dc35a10fSMarcin Wojtas 1185dc35a10fSMarcin Wojtas /* Create port's short pool */ 1186dc35a10fSMarcin Wojtas pp->pool_short = mvneta_bm_pool_use(pp->bm_priv, short_pool_id, 1187dc35a10fSMarcin Wojtas MVNETA_BM_SHORT, pp->id, 1188dc35a10fSMarcin Wojtas MVNETA_BM_SHORT_PKT_SIZE); 1189dc35a10fSMarcin Wojtas if (!pp->pool_short) { 1190dc35a10fSMarcin Wojtas netdev_info(pp->dev, "fail to obtain short pool for port\n"); 1191dc35a10fSMarcin Wojtas mvneta_bm_pool_destroy(pp->bm_priv, pp->pool_long, 1 << pp->id); 1192dc35a10fSMarcin Wojtas return -ENOMEM; 1193dc35a10fSMarcin Wojtas } 1194dc35a10fSMarcin Wojtas 1195dc35a10fSMarcin Wojtas if (short_pool_id != long_pool_id) { 1196dc35a10fSMarcin Wojtas pp->pool_short->port_map |= 1 << pp->id; 1197dc35a10fSMarcin Wojtas mvneta_bm_pool_bufsize_set(pp, pp->pool_short->buf_size, 1198dc35a10fSMarcin Wojtas pp->pool_short->id); 1199dc35a10fSMarcin Wojtas } 1200dc35a10fSMarcin Wojtas 1201dc35a10fSMarcin Wojtas return 0; 1202dc35a10fSMarcin Wojtas } 1203dc35a10fSMarcin Wojtas 1204dc35a10fSMarcin Wojtas /* Update settings of a pool for bigger packets */ 1205dc35a10fSMarcin Wojtas static void mvneta_bm_update_mtu(struct mvneta_port *pp, int mtu) 1206dc35a10fSMarcin Wojtas { 1207dc35a10fSMarcin Wojtas struct mvneta_bm_pool *bm_pool = pp->pool_long; 1208baa11ebcSGregory CLEMENT struct hwbm_pool *hwbm_pool = &bm_pool->hwbm_pool; 1209dc35a10fSMarcin Wojtas int num; 1210dc35a10fSMarcin Wojtas 1211dc35a10fSMarcin Wojtas /* Release all buffers from long pool */ 1212dc35a10fSMarcin Wojtas mvneta_bm_bufs_free(pp->bm_priv, bm_pool, 1 << pp->id); 1213baa11ebcSGregory CLEMENT if (hwbm_pool->buf_num) { 1214dc35a10fSMarcin Wojtas WARN(1, "cannot free all buffers in pool %d\n", 1215dc35a10fSMarcin Wojtas bm_pool->id); 1216dc35a10fSMarcin Wojtas goto bm_mtu_err; 1217dc35a10fSMarcin Wojtas } 1218dc35a10fSMarcin Wojtas 1219dc35a10fSMarcin Wojtas bm_pool->pkt_size = MVNETA_RX_PKT_SIZE(mtu); 1220dc35a10fSMarcin Wojtas bm_pool->buf_size = MVNETA_RX_BUF_SIZE(bm_pool->pkt_size); 1221baa11ebcSGregory CLEMENT hwbm_pool->frag_size = SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) + 1222dc35a10fSMarcin Wojtas SKB_DATA_ALIGN(MVNETA_RX_BUF_SIZE(bm_pool->pkt_size)); 1223dc35a10fSMarcin Wojtas 1224dc35a10fSMarcin Wojtas /* Fill entire long pool */ 12256dcdd884SSebastian Andrzej Siewior num = hwbm_pool_add(hwbm_pool, hwbm_pool->size); 1226baa11ebcSGregory CLEMENT if (num != hwbm_pool->size) { 1227dc35a10fSMarcin Wojtas WARN(1, "pool %d: %d of %d allocated\n", 1228baa11ebcSGregory CLEMENT bm_pool->id, num, hwbm_pool->size); 1229dc35a10fSMarcin Wojtas goto bm_mtu_err; 1230dc35a10fSMarcin Wojtas } 1231dc35a10fSMarcin Wojtas mvneta_bm_pool_bufsize_set(pp, bm_pool->buf_size, bm_pool->id); 1232dc35a10fSMarcin Wojtas 1233dc35a10fSMarcin Wojtas return; 1234dc35a10fSMarcin Wojtas 1235dc35a10fSMarcin Wojtas bm_mtu_err: 1236dc35a10fSMarcin Wojtas mvneta_bm_pool_destroy(pp->bm_priv, pp->pool_long, 1 << pp->id); 1237dc35a10fSMarcin Wojtas mvneta_bm_pool_destroy(pp->bm_priv, pp->pool_short, 1 << pp->id); 1238dc35a10fSMarcin Wojtas 1239dc35a10fSMarcin Wojtas pp->bm_priv = NULL; 124044efc78dSLorenzo Bianconi pp->rx_offset_correction = MVNETA_SKB_HEADROOM; 1241dc35a10fSMarcin Wojtas mvreg_write(pp, MVNETA_ACC_MODE, MVNETA_ACC_MODE_EXT1); 1242dc35a10fSMarcin Wojtas netdev_info(pp->dev, "fail to update MTU, fall back to software BM\n"); 1243dc35a10fSMarcin Wojtas } 1244dc35a10fSMarcin Wojtas 1245c5aff182SThomas Petazzoni /* Start the Ethernet port RX and TX activity */ 1246c5aff182SThomas Petazzoni static void mvneta_port_up(struct mvneta_port *pp) 1247c5aff182SThomas Petazzoni { 1248c5aff182SThomas Petazzoni int queue; 1249c5aff182SThomas Petazzoni u32 q_map; 1250c5aff182SThomas Petazzoni 1251c5aff182SThomas Petazzoni /* Enable all initialized TXs. */ 1252c5aff182SThomas Petazzoni q_map = 0; 1253c5aff182SThomas Petazzoni for (queue = 0; queue < txq_number; queue++) { 1254c5aff182SThomas Petazzoni struct mvneta_tx_queue *txq = &pp->txqs[queue]; 1255f95936ccSMarkus Elfring if (txq->descs) 1256c5aff182SThomas Petazzoni q_map |= (1 << queue); 1257c5aff182SThomas Petazzoni } 1258c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_TXQ_CMD, q_map); 1259c5aff182SThomas Petazzoni 1260e81b5e01SYelena Krivosheev q_map = 0; 1261c5aff182SThomas Petazzoni /* Enable all initialized RXQs. */ 12622dcf75e2SGregory CLEMENT for (queue = 0; queue < rxq_number; queue++) { 12632dcf75e2SGregory CLEMENT struct mvneta_rx_queue *rxq = &pp->rxqs[queue]; 12642dcf75e2SGregory CLEMENT 1265f95936ccSMarkus Elfring if (rxq->descs) 12662dcf75e2SGregory CLEMENT q_map |= (1 << queue); 12672dcf75e2SGregory CLEMENT } 12682dcf75e2SGregory CLEMENT mvreg_write(pp, MVNETA_RXQ_CMD, q_map); 1269c5aff182SThomas Petazzoni } 1270c5aff182SThomas Petazzoni 1271c5aff182SThomas Petazzoni /* Stop the Ethernet port activity */ 1272c5aff182SThomas Petazzoni static void mvneta_port_down(struct mvneta_port *pp) 1273c5aff182SThomas Petazzoni { 1274c5aff182SThomas Petazzoni u32 val; 1275c5aff182SThomas Petazzoni int count; 1276c5aff182SThomas Petazzoni 1277c5aff182SThomas Petazzoni /* Stop Rx port activity. Check port Rx activity. */ 1278c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_RXQ_CMD) & MVNETA_RXQ_ENABLE_MASK; 1279c5aff182SThomas Petazzoni 1280c5aff182SThomas Petazzoni /* Issue stop command for active channels only */ 1281c5aff182SThomas Petazzoni if (val != 0) 1282c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_RXQ_CMD, 1283c5aff182SThomas Petazzoni val << MVNETA_RXQ_DISABLE_SHIFT); 1284c5aff182SThomas Petazzoni 1285c5aff182SThomas Petazzoni /* Wait for all Rx activity to terminate. */ 1286c5aff182SThomas Petazzoni count = 0; 1287c5aff182SThomas Petazzoni do { 1288c5aff182SThomas Petazzoni if (count++ >= MVNETA_RX_DISABLE_TIMEOUT_MSEC) { 1289c5aff182SThomas Petazzoni netdev_warn(pp->dev, 12900838abb3SDmitri Epshtein "TIMEOUT for RX stopped ! rx_queue_cmd: 0x%08x\n", 1291c5aff182SThomas Petazzoni val); 1292c5aff182SThomas Petazzoni break; 1293c5aff182SThomas Petazzoni } 1294c5aff182SThomas Petazzoni mdelay(1); 1295c5aff182SThomas Petazzoni 1296c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_RXQ_CMD); 1297a3703fb3SDmitri Epshtein } while (val & MVNETA_RXQ_ENABLE_MASK); 1298c5aff182SThomas Petazzoni 1299c5aff182SThomas Petazzoni /* Stop Tx port activity. Check port Tx activity. Issue stop 13006a20c175SThomas Petazzoni * command for active channels only 13016a20c175SThomas Petazzoni */ 1302c5aff182SThomas Petazzoni val = (mvreg_read(pp, MVNETA_TXQ_CMD)) & MVNETA_TXQ_ENABLE_MASK; 1303c5aff182SThomas Petazzoni 1304c5aff182SThomas Petazzoni if (val != 0) 1305c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_TXQ_CMD, 1306c5aff182SThomas Petazzoni (val << MVNETA_TXQ_DISABLE_SHIFT)); 1307c5aff182SThomas Petazzoni 1308c5aff182SThomas Petazzoni /* Wait for all Tx activity to terminate. */ 1309c5aff182SThomas Petazzoni count = 0; 1310c5aff182SThomas Petazzoni do { 1311c5aff182SThomas Petazzoni if (count++ >= MVNETA_TX_DISABLE_TIMEOUT_MSEC) { 1312c5aff182SThomas Petazzoni netdev_warn(pp->dev, 1313c5aff182SThomas Petazzoni "TIMEOUT for TX stopped status=0x%08x\n", 1314c5aff182SThomas Petazzoni val); 1315c5aff182SThomas Petazzoni break; 1316c5aff182SThomas Petazzoni } 1317c5aff182SThomas Petazzoni mdelay(1); 1318c5aff182SThomas Petazzoni 1319c5aff182SThomas Petazzoni /* Check TX Command reg that all Txqs are stopped */ 1320c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_TXQ_CMD); 1321c5aff182SThomas Petazzoni 1322a3703fb3SDmitri Epshtein } while (val & MVNETA_TXQ_ENABLE_MASK); 1323c5aff182SThomas Petazzoni 1324c5aff182SThomas Petazzoni /* Double check to verify that TX FIFO is empty */ 1325c5aff182SThomas Petazzoni count = 0; 1326c5aff182SThomas Petazzoni do { 1327c5aff182SThomas Petazzoni if (count++ >= MVNETA_TX_FIFO_EMPTY_TIMEOUT) { 1328c5aff182SThomas Petazzoni netdev_warn(pp->dev, 13290838abb3SDmitri Epshtein "TX FIFO empty timeout status=0x%08x\n", 1330c5aff182SThomas Petazzoni val); 1331c5aff182SThomas Petazzoni break; 1332c5aff182SThomas Petazzoni } 1333c5aff182SThomas Petazzoni mdelay(1); 1334c5aff182SThomas Petazzoni 1335c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_PORT_STATUS); 1336c5aff182SThomas Petazzoni } while (!(val & MVNETA_TX_FIFO_EMPTY) && 1337c5aff182SThomas Petazzoni (val & MVNETA_TX_IN_PRGRS)); 1338c5aff182SThomas Petazzoni 1339c5aff182SThomas Petazzoni udelay(200); 1340c5aff182SThomas Petazzoni } 1341c5aff182SThomas Petazzoni 1342c5aff182SThomas Petazzoni /* Enable the port by setting the port enable bit of the MAC control register */ 1343c5aff182SThomas Petazzoni static void mvneta_port_enable(struct mvneta_port *pp) 1344c5aff182SThomas Petazzoni { 1345c5aff182SThomas Petazzoni u32 val; 1346c5aff182SThomas Petazzoni 1347c5aff182SThomas Petazzoni /* Enable port */ 1348c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_GMAC_CTRL_0); 1349c5aff182SThomas Petazzoni val |= MVNETA_GMAC0_PORT_ENABLE; 1350c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_GMAC_CTRL_0, val); 1351c5aff182SThomas Petazzoni } 1352c5aff182SThomas Petazzoni 1353c5aff182SThomas Petazzoni /* Disable the port and wait for about 200 usec before retuning */ 1354c5aff182SThomas Petazzoni static void mvneta_port_disable(struct mvneta_port *pp) 1355c5aff182SThomas Petazzoni { 1356c5aff182SThomas Petazzoni u32 val; 1357c5aff182SThomas Petazzoni 1358c5aff182SThomas Petazzoni /* Reset the Enable bit in the Serial Control Register */ 1359c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_GMAC_CTRL_0); 1360c5aff182SThomas Petazzoni val &= ~MVNETA_GMAC0_PORT_ENABLE; 1361c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_GMAC_CTRL_0, val); 1362c5aff182SThomas Petazzoni 1363c5aff182SThomas Petazzoni udelay(200); 1364c5aff182SThomas Petazzoni } 1365c5aff182SThomas Petazzoni 1366c5aff182SThomas Petazzoni /* Multicast tables methods */ 1367c5aff182SThomas Petazzoni 1368c5aff182SThomas Petazzoni /* Set all entries in Unicast MAC Table; queue==-1 means reject all */ 1369c5aff182SThomas Petazzoni static void mvneta_set_ucast_table(struct mvneta_port *pp, int queue) 1370c5aff182SThomas Petazzoni { 1371c5aff182SThomas Petazzoni int offset; 1372c5aff182SThomas Petazzoni u32 val; 1373c5aff182SThomas Petazzoni 1374c5aff182SThomas Petazzoni if (queue == -1) { 1375c5aff182SThomas Petazzoni val = 0; 1376c5aff182SThomas Petazzoni } else { 1377c5aff182SThomas Petazzoni val = 0x1 | (queue << 1); 1378c5aff182SThomas Petazzoni val |= (val << 24) | (val << 16) | (val << 8); 1379c5aff182SThomas Petazzoni } 1380c5aff182SThomas Petazzoni 1381c5aff182SThomas Petazzoni for (offset = 0; offset <= 0xc; offset += 4) 1382c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_DA_FILT_UCAST_BASE + offset, val); 1383c5aff182SThomas Petazzoni } 1384c5aff182SThomas Petazzoni 1385c5aff182SThomas Petazzoni /* Set all entries in Special Multicast MAC Table; queue==-1 means reject all */ 1386c5aff182SThomas Petazzoni static void mvneta_set_special_mcast_table(struct mvneta_port *pp, int queue) 1387c5aff182SThomas Petazzoni { 1388c5aff182SThomas Petazzoni int offset; 1389c5aff182SThomas Petazzoni u32 val; 1390c5aff182SThomas Petazzoni 1391c5aff182SThomas Petazzoni if (queue == -1) { 1392c5aff182SThomas Petazzoni val = 0; 1393c5aff182SThomas Petazzoni } else { 1394c5aff182SThomas Petazzoni val = 0x1 | (queue << 1); 1395c5aff182SThomas Petazzoni val |= (val << 24) | (val << 16) | (val << 8); 1396c5aff182SThomas Petazzoni } 1397c5aff182SThomas Petazzoni 1398c5aff182SThomas Petazzoni for (offset = 0; offset <= 0xfc; offset += 4) 1399c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_DA_FILT_SPEC_MCAST + offset, val); 1400c5aff182SThomas Petazzoni 1401c5aff182SThomas Petazzoni } 1402c5aff182SThomas Petazzoni 1403c5aff182SThomas Petazzoni /* Set all entries in Other Multicast MAC Table. queue==-1 means reject all */ 1404c5aff182SThomas Petazzoni static void mvneta_set_other_mcast_table(struct mvneta_port *pp, int queue) 1405c5aff182SThomas Petazzoni { 1406c5aff182SThomas Petazzoni int offset; 1407c5aff182SThomas Petazzoni u32 val; 1408c5aff182SThomas Petazzoni 1409c5aff182SThomas Petazzoni if (queue == -1) { 1410c5aff182SThomas Petazzoni memset(pp->mcast_count, 0, sizeof(pp->mcast_count)); 1411c5aff182SThomas Petazzoni val = 0; 1412c5aff182SThomas Petazzoni } else { 1413c5aff182SThomas Petazzoni memset(pp->mcast_count, 1, sizeof(pp->mcast_count)); 1414c5aff182SThomas Petazzoni val = 0x1 | (queue << 1); 1415c5aff182SThomas Petazzoni val |= (val << 24) | (val << 16) | (val << 8); 1416c5aff182SThomas Petazzoni } 1417c5aff182SThomas Petazzoni 1418c5aff182SThomas Petazzoni for (offset = 0; offset <= 0xfc; offset += 4) 1419c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_DA_FILT_OTH_MCAST + offset, val); 1420c5aff182SThomas Petazzoni } 1421c5aff182SThomas Petazzoni 1422db488c10SGregory CLEMENT static void mvneta_percpu_unmask_interrupt(void *arg) 1423db488c10SGregory CLEMENT { 1424db488c10SGregory CLEMENT struct mvneta_port *pp = arg; 1425db488c10SGregory CLEMENT 1426db488c10SGregory CLEMENT /* All the queue are unmasked, but actually only the ones 1427db488c10SGregory CLEMENT * mapped to this CPU will be unmasked 1428db488c10SGregory CLEMENT */ 1429db488c10SGregory CLEMENT mvreg_write(pp, MVNETA_INTR_NEW_MASK, 1430db488c10SGregory CLEMENT MVNETA_RX_INTR_MASK_ALL | 1431db488c10SGregory CLEMENT MVNETA_TX_INTR_MASK_ALL | 1432db488c10SGregory CLEMENT MVNETA_MISCINTR_INTR_MASK); 1433db488c10SGregory CLEMENT } 1434db488c10SGregory CLEMENT 1435db488c10SGregory CLEMENT static void mvneta_percpu_mask_interrupt(void *arg) 1436db488c10SGregory CLEMENT { 1437db488c10SGregory CLEMENT struct mvneta_port *pp = arg; 1438db488c10SGregory CLEMENT 1439db488c10SGregory CLEMENT /* All the queue are masked, but actually only the ones 1440db488c10SGregory CLEMENT * mapped to this CPU will be masked 1441db488c10SGregory CLEMENT */ 1442db488c10SGregory CLEMENT mvreg_write(pp, MVNETA_INTR_NEW_MASK, 0); 1443db488c10SGregory CLEMENT mvreg_write(pp, MVNETA_INTR_OLD_MASK, 0); 1444db488c10SGregory CLEMENT mvreg_write(pp, MVNETA_INTR_MISC_MASK, 0); 1445db488c10SGregory CLEMENT } 1446db488c10SGregory CLEMENT 1447db488c10SGregory CLEMENT static void mvneta_percpu_clear_intr_cause(void *arg) 1448db488c10SGregory CLEMENT { 1449db488c10SGregory CLEMENT struct mvneta_port *pp = arg; 1450db488c10SGregory CLEMENT 1451db488c10SGregory CLEMENT /* All the queue are cleared, but actually only the ones 1452db488c10SGregory CLEMENT * mapped to this CPU will be cleared 1453db488c10SGregory CLEMENT */ 1454db488c10SGregory CLEMENT mvreg_write(pp, MVNETA_INTR_NEW_CAUSE, 0); 1455db488c10SGregory CLEMENT mvreg_write(pp, MVNETA_INTR_MISC_CAUSE, 0); 1456db488c10SGregory CLEMENT mvreg_write(pp, MVNETA_INTR_OLD_CAUSE, 0); 1457db488c10SGregory CLEMENT } 1458db488c10SGregory CLEMENT 1459c5aff182SThomas Petazzoni /* This method sets defaults to the NETA port: 1460c5aff182SThomas Petazzoni * Clears interrupt Cause and Mask registers. 1461c5aff182SThomas Petazzoni * Clears all MAC tables. 1462c5aff182SThomas Petazzoni * Sets defaults to all registers. 1463c5aff182SThomas Petazzoni * Resets RX and TX descriptor rings. 1464c5aff182SThomas Petazzoni * Resets PHY. 1465c5aff182SThomas Petazzoni * This method can be called after mvneta_port_down() to return the port 1466c5aff182SThomas Petazzoni * settings to defaults. 1467c5aff182SThomas Petazzoni */ 1468c5aff182SThomas Petazzoni static void mvneta_defaults_set(struct mvneta_port *pp) 1469c5aff182SThomas Petazzoni { 1470c5aff182SThomas Petazzoni int cpu; 1471c5aff182SThomas Petazzoni int queue; 1472c5aff182SThomas Petazzoni u32 val; 14732dcf75e2SGregory CLEMENT int max_cpu = num_present_cpus(); 1474c5aff182SThomas Petazzoni 1475c5aff182SThomas Petazzoni /* Clear all Cause registers */ 1476db488c10SGregory CLEMENT on_each_cpu(mvneta_percpu_clear_intr_cause, pp, true); 1477c5aff182SThomas Petazzoni 1478c5aff182SThomas Petazzoni /* Mask all interrupts */ 1479db488c10SGregory CLEMENT on_each_cpu(mvneta_percpu_mask_interrupt, pp, true); 1480c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_INTR_ENABLE, 0); 1481c5aff182SThomas Petazzoni 1482c5aff182SThomas Petazzoni /* Enable MBUS Retry bit16 */ 1483c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_MBUS_RETRY, 0x20); 1484c5aff182SThomas Petazzoni 148550bf8cb6SGregory CLEMENT /* Set CPU queue access map. CPUs are assigned to the RX and 148650bf8cb6SGregory CLEMENT * TX queues modulo their number. If there is only one TX 148750bf8cb6SGregory CLEMENT * queue then it is assigned to the CPU associated to the 148850bf8cb6SGregory CLEMENT * default RX queue. 14896a20c175SThomas Petazzoni */ 14902dcf75e2SGregory CLEMENT for_each_present_cpu(cpu) { 14912dcf75e2SGregory CLEMENT int rxq_map = 0, txq_map = 0; 149250bf8cb6SGregory CLEMENT int rxq, txq; 14932636ac3cSMarcin Wojtas if (!pp->neta_armada3700) { 14942dcf75e2SGregory CLEMENT for (rxq = 0; rxq < rxq_number; rxq++) 14952dcf75e2SGregory CLEMENT if ((rxq % max_cpu) == cpu) 14962dcf75e2SGregory CLEMENT rxq_map |= MVNETA_CPU_RXQ_ACCESS(rxq); 14972dcf75e2SGregory CLEMENT 149850bf8cb6SGregory CLEMENT for (txq = 0; txq < txq_number; txq++) 149950bf8cb6SGregory CLEMENT if ((txq % max_cpu) == cpu) 150050bf8cb6SGregory CLEMENT txq_map |= MVNETA_CPU_TXQ_ACCESS(txq); 150150bf8cb6SGregory CLEMENT 150250bf8cb6SGregory CLEMENT /* With only one TX queue we configure a special case 150350bf8cb6SGregory CLEMENT * which will allow to get all the irq on a single 150450bf8cb6SGregory CLEMENT * CPU 150550bf8cb6SGregory CLEMENT */ 150650bf8cb6SGregory CLEMENT if (txq_number == 1) 150750bf8cb6SGregory CLEMENT txq_map = (cpu == pp->rxq_def) ? 150850bf8cb6SGregory CLEMENT MVNETA_CPU_TXQ_ACCESS(1) : 0; 15092dcf75e2SGregory CLEMENT 15102636ac3cSMarcin Wojtas } else { 15112636ac3cSMarcin Wojtas txq_map = MVNETA_CPU_TXQ_ACCESS_ALL_MASK; 15122636ac3cSMarcin Wojtas rxq_map = MVNETA_CPU_RXQ_ACCESS_ALL_MASK; 15132636ac3cSMarcin Wojtas } 15142636ac3cSMarcin Wojtas 15152dcf75e2SGregory CLEMENT mvreg_write(pp, MVNETA_CPU_MAP(cpu), rxq_map | txq_map); 15162dcf75e2SGregory CLEMENT } 1517c5aff182SThomas Petazzoni 1518c5aff182SThomas Petazzoni /* Reset RX and TX DMAs */ 1519c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_PORT_RX_RESET, MVNETA_PORT_RX_DMA_RESET); 1520c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_PORT_TX_RESET, MVNETA_PORT_TX_DMA_RESET); 1521c5aff182SThomas Petazzoni 1522c5aff182SThomas Petazzoni /* Disable Legacy WRR, Disable EJP, Release from reset */ 1523c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_TXQ_CMD_1, 0); 1524c5aff182SThomas Petazzoni for (queue = 0; queue < txq_number; queue++) { 1525c5aff182SThomas Petazzoni mvreg_write(pp, MVETH_TXQ_TOKEN_COUNT_REG(queue), 0); 1526c5aff182SThomas Petazzoni mvreg_write(pp, MVETH_TXQ_TOKEN_CFG_REG(queue), 0); 1527c5aff182SThomas Petazzoni } 1528c5aff182SThomas Petazzoni 1529c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_PORT_TX_RESET, 0); 1530c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_PORT_RX_RESET, 0); 1531c5aff182SThomas Petazzoni 1532c5aff182SThomas Petazzoni /* Set Port Acceleration Mode */ 1533dc35a10fSMarcin Wojtas if (pp->bm_priv) 1534dc35a10fSMarcin Wojtas /* HW buffer management + legacy parser */ 1535dc35a10fSMarcin Wojtas val = MVNETA_ACC_MODE_EXT2; 1536dc35a10fSMarcin Wojtas else 1537dc35a10fSMarcin Wojtas /* SW buffer management + legacy parser */ 1538dc35a10fSMarcin Wojtas val = MVNETA_ACC_MODE_EXT1; 1539c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_ACC_MODE, val); 1540c5aff182SThomas Petazzoni 1541dc35a10fSMarcin Wojtas if (pp->bm_priv) 1542dc35a10fSMarcin Wojtas mvreg_write(pp, MVNETA_BM_ADDRESS, pp->bm_priv->bppi_phys_addr); 1543dc35a10fSMarcin Wojtas 1544c5aff182SThomas Petazzoni /* Update val of portCfg register accordingly with all RxQueue types */ 154590b74c01SGregory CLEMENT val = MVNETA_PORT_CONFIG_DEFL_VALUE(pp->rxq_def); 1546c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_PORT_CONFIG, val); 1547c5aff182SThomas Petazzoni 1548c5aff182SThomas Petazzoni val = 0; 1549c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_PORT_CONFIG_EXTEND, val); 1550c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_RX_MIN_FRAME_SIZE, 64); 1551c5aff182SThomas Petazzoni 1552c5aff182SThomas Petazzoni /* Build PORT_SDMA_CONFIG_REG */ 1553c5aff182SThomas Petazzoni val = 0; 1554c5aff182SThomas Petazzoni 1555c5aff182SThomas Petazzoni /* Default burst size */ 1556c5aff182SThomas Petazzoni val |= MVNETA_TX_BRST_SZ_MASK(MVNETA_SDMA_BRST_SIZE_16); 1557c5aff182SThomas Petazzoni val |= MVNETA_RX_BRST_SZ_MASK(MVNETA_SDMA_BRST_SIZE_16); 15589ad8fef6SThomas Petazzoni val |= MVNETA_RX_NO_DATA_SWAP | MVNETA_TX_NO_DATA_SWAP; 1559c5aff182SThomas Petazzoni 15609ad8fef6SThomas Petazzoni #if defined(__BIG_ENDIAN) 15619ad8fef6SThomas Petazzoni val |= MVNETA_DESC_SWAP; 15629ad8fef6SThomas Petazzoni #endif 1563c5aff182SThomas Petazzoni 1564c5aff182SThomas Petazzoni /* Assign port SDMA configuration */ 1565c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_SDMA_CONFIG, val); 1566c5aff182SThomas Petazzoni 156771408602SThomas Petazzoni /* Disable PHY polling in hardware, since we're using the 156871408602SThomas Petazzoni * kernel phylib to do this. 156971408602SThomas Petazzoni */ 157071408602SThomas Petazzoni val = mvreg_read(pp, MVNETA_UNIT_CONTROL); 157171408602SThomas Petazzoni val &= ~MVNETA_PHY_POLLING_ENABLE; 157271408602SThomas Petazzoni mvreg_write(pp, MVNETA_UNIT_CONTROL, val); 157371408602SThomas Petazzoni 1574c5aff182SThomas Petazzoni mvneta_set_ucast_table(pp, -1); 1575c5aff182SThomas Petazzoni mvneta_set_special_mcast_table(pp, -1); 1576c5aff182SThomas Petazzoni mvneta_set_other_mcast_table(pp, -1); 1577c5aff182SThomas Petazzoni 1578c5aff182SThomas Petazzoni /* Set port interrupt enable register - default enable all */ 1579c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_INTR_ENABLE, 1580c5aff182SThomas Petazzoni (MVNETA_RXQ_INTR_ENABLE_ALL_MASK 1581c5aff182SThomas Petazzoni | MVNETA_TXQ_INTR_ENABLE_ALL_MASK)); 1582e483911fSAndrew Lunn 1583e483911fSAndrew Lunn mvneta_mib_counters_clear(pp); 1584c5aff182SThomas Petazzoni } 1585c5aff182SThomas Petazzoni 1586c5aff182SThomas Petazzoni /* Set max sizes for tx queues */ 1587c5aff182SThomas Petazzoni static void mvneta_txq_max_tx_size_set(struct mvneta_port *pp, int max_tx_size) 1588c5aff182SThomas Petazzoni 1589c5aff182SThomas Petazzoni { 1590c5aff182SThomas Petazzoni u32 val, size, mtu; 1591c5aff182SThomas Petazzoni int queue; 1592c5aff182SThomas Petazzoni 1593c5aff182SThomas Petazzoni mtu = max_tx_size * 8; 1594c5aff182SThomas Petazzoni if (mtu > MVNETA_TX_MTU_MAX) 1595c5aff182SThomas Petazzoni mtu = MVNETA_TX_MTU_MAX; 1596c5aff182SThomas Petazzoni 1597c5aff182SThomas Petazzoni /* Set MTU */ 1598c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_TX_MTU); 1599c5aff182SThomas Petazzoni val &= ~MVNETA_TX_MTU_MAX; 1600c5aff182SThomas Petazzoni val |= mtu; 1601c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_TX_MTU, val); 1602c5aff182SThomas Petazzoni 1603c5aff182SThomas Petazzoni /* TX token size and all TXQs token size must be larger that MTU */ 1604c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_TX_TOKEN_SIZE); 1605c5aff182SThomas Petazzoni 1606c5aff182SThomas Petazzoni size = val & MVNETA_TX_TOKEN_SIZE_MAX; 1607c5aff182SThomas Petazzoni if (size < mtu) { 1608c5aff182SThomas Petazzoni size = mtu; 1609c5aff182SThomas Petazzoni val &= ~MVNETA_TX_TOKEN_SIZE_MAX; 1610c5aff182SThomas Petazzoni val |= size; 1611c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_TX_TOKEN_SIZE, val); 1612c5aff182SThomas Petazzoni } 1613c5aff182SThomas Petazzoni for (queue = 0; queue < txq_number; queue++) { 1614c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_TXQ_TOKEN_SIZE_REG(queue)); 1615c5aff182SThomas Petazzoni 1616c5aff182SThomas Petazzoni size = val & MVNETA_TXQ_TOKEN_SIZE_MAX; 1617c5aff182SThomas Petazzoni if (size < mtu) { 1618c5aff182SThomas Petazzoni size = mtu; 1619c5aff182SThomas Petazzoni val &= ~MVNETA_TXQ_TOKEN_SIZE_MAX; 1620c5aff182SThomas Petazzoni val |= size; 1621c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_TXQ_TOKEN_SIZE_REG(queue), val); 1622c5aff182SThomas Petazzoni } 1623c5aff182SThomas Petazzoni } 1624c5aff182SThomas Petazzoni } 1625c5aff182SThomas Petazzoni 1626c5aff182SThomas Petazzoni /* Set unicast address */ 1627c5aff182SThomas Petazzoni static void mvneta_set_ucast_addr(struct mvneta_port *pp, u8 last_nibble, 1628c5aff182SThomas Petazzoni int queue) 1629c5aff182SThomas Petazzoni { 1630c5aff182SThomas Petazzoni unsigned int unicast_reg; 1631c5aff182SThomas Petazzoni unsigned int tbl_offset; 1632c5aff182SThomas Petazzoni unsigned int reg_offset; 1633c5aff182SThomas Petazzoni 1634c5aff182SThomas Petazzoni /* Locate the Unicast table entry */ 1635c5aff182SThomas Petazzoni last_nibble = (0xf & last_nibble); 1636c5aff182SThomas Petazzoni 1637c5aff182SThomas Petazzoni /* offset from unicast tbl base */ 1638c5aff182SThomas Petazzoni tbl_offset = (last_nibble / 4) * 4; 1639c5aff182SThomas Petazzoni 1640c5aff182SThomas Petazzoni /* offset within the above reg */ 1641c5aff182SThomas Petazzoni reg_offset = last_nibble % 4; 1642c5aff182SThomas Petazzoni 1643c5aff182SThomas Petazzoni unicast_reg = mvreg_read(pp, (MVNETA_DA_FILT_UCAST_BASE + tbl_offset)); 1644c5aff182SThomas Petazzoni 1645c5aff182SThomas Petazzoni if (queue == -1) { 1646c5aff182SThomas Petazzoni /* Clear accepts frame bit at specified unicast DA tbl entry */ 1647c5aff182SThomas Petazzoni unicast_reg &= ~(0xff << (8 * reg_offset)); 1648c5aff182SThomas Petazzoni } else { 1649c5aff182SThomas Petazzoni unicast_reg &= ~(0xff << (8 * reg_offset)); 1650c5aff182SThomas Petazzoni unicast_reg |= ((0x01 | (queue << 1)) << (8 * reg_offset)); 1651c5aff182SThomas Petazzoni } 1652c5aff182SThomas Petazzoni 1653c5aff182SThomas Petazzoni mvreg_write(pp, (MVNETA_DA_FILT_UCAST_BASE + tbl_offset), unicast_reg); 1654c5aff182SThomas Petazzoni } 1655c5aff182SThomas Petazzoni 1656c5aff182SThomas Petazzoni /* Set mac address */ 165776660757SJakub Kicinski static void mvneta_mac_addr_set(struct mvneta_port *pp, 165876660757SJakub Kicinski const unsigned char *addr, int queue) 1659c5aff182SThomas Petazzoni { 1660c5aff182SThomas Petazzoni unsigned int mac_h; 1661c5aff182SThomas Petazzoni unsigned int mac_l; 1662c5aff182SThomas Petazzoni 1663c5aff182SThomas Petazzoni if (queue != -1) { 1664c5aff182SThomas Petazzoni mac_l = (addr[4] << 8) | (addr[5]); 1665c5aff182SThomas Petazzoni mac_h = (addr[0] << 24) | (addr[1] << 16) | 1666c5aff182SThomas Petazzoni (addr[2] << 8) | (addr[3] << 0); 1667c5aff182SThomas Petazzoni 1668c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_MAC_ADDR_LOW, mac_l); 1669c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_MAC_ADDR_HIGH, mac_h); 1670c5aff182SThomas Petazzoni } 1671c5aff182SThomas Petazzoni 1672c5aff182SThomas Petazzoni /* Accept frames of this address */ 1673c5aff182SThomas Petazzoni mvneta_set_ucast_addr(pp, addr[5], queue); 1674c5aff182SThomas Petazzoni } 1675c5aff182SThomas Petazzoni 16766a20c175SThomas Petazzoni /* Set the number of packets that will be received before RX interrupt 16776a20c175SThomas Petazzoni * will be generated by HW. 1678c5aff182SThomas Petazzoni */ 1679c5aff182SThomas Petazzoni static void mvneta_rx_pkts_coal_set(struct mvneta_port *pp, 1680c5aff182SThomas Petazzoni struct mvneta_rx_queue *rxq, u32 value) 1681c5aff182SThomas Petazzoni { 1682c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_RXQ_THRESHOLD_REG(rxq->id), 1683c5aff182SThomas Petazzoni value | MVNETA_RXQ_NON_OCCUPIED(0)); 1684c5aff182SThomas Petazzoni } 1685c5aff182SThomas Petazzoni 16866a20c175SThomas Petazzoni /* Set the time delay in usec before RX interrupt will be generated by 16876a20c175SThomas Petazzoni * HW. 1688c5aff182SThomas Petazzoni */ 1689c5aff182SThomas Petazzoni static void mvneta_rx_time_coal_set(struct mvneta_port *pp, 1690c5aff182SThomas Petazzoni struct mvneta_rx_queue *rxq, u32 value) 1691c5aff182SThomas Petazzoni { 1692189dd626SThomas Petazzoni u32 val; 1693189dd626SThomas Petazzoni unsigned long clk_rate; 1694189dd626SThomas Petazzoni 1695189dd626SThomas Petazzoni clk_rate = clk_get_rate(pp->clk); 1696189dd626SThomas Petazzoni val = (clk_rate / 1000000) * value; 1697c5aff182SThomas Petazzoni 1698c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_RXQ_TIME_COAL_REG(rxq->id), val); 1699c5aff182SThomas Petazzoni } 1700c5aff182SThomas Petazzoni 1701c5aff182SThomas Petazzoni /* Set threshold for TX_DONE pkts coalescing */ 1702c5aff182SThomas Petazzoni static void mvneta_tx_done_pkts_coal_set(struct mvneta_port *pp, 1703c5aff182SThomas Petazzoni struct mvneta_tx_queue *txq, u32 value) 1704c5aff182SThomas Petazzoni { 1705c5aff182SThomas Petazzoni u32 val; 1706c5aff182SThomas Petazzoni 1707c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_TXQ_SIZE_REG(txq->id)); 1708c5aff182SThomas Petazzoni 1709c5aff182SThomas Petazzoni val &= ~MVNETA_TXQ_SENT_THRESH_ALL_MASK; 1710c5aff182SThomas Petazzoni val |= MVNETA_TXQ_SENT_THRESH_MASK(value); 1711c5aff182SThomas Petazzoni 1712c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_TXQ_SIZE_REG(txq->id), val); 1713c5aff182SThomas Petazzoni } 1714c5aff182SThomas Petazzoni 1715c5aff182SThomas Petazzoni /* Handle rx descriptor fill by setting buf_cookie and buf_phys_addr */ 1716c5aff182SThomas Petazzoni static void mvneta_rx_desc_fill(struct mvneta_rx_desc *rx_desc, 1717f88bee1cSGregory CLEMENT u32 phys_addr, void *virt_addr, 1718f88bee1cSGregory CLEMENT struct mvneta_rx_queue *rxq) 1719c5aff182SThomas Petazzoni { 1720f88bee1cSGregory CLEMENT int i; 1721f88bee1cSGregory CLEMENT 1722c5aff182SThomas Petazzoni rx_desc->buf_phys_addr = phys_addr; 1723f88bee1cSGregory CLEMENT i = rx_desc - rxq->descs; 1724f88bee1cSGregory CLEMENT rxq->buf_virt_addr[i] = virt_addr; 1725c5aff182SThomas Petazzoni } 1726c5aff182SThomas Petazzoni 1727c5aff182SThomas Petazzoni /* Decrement sent descriptors counter */ 1728c5aff182SThomas Petazzoni static void mvneta_txq_sent_desc_dec(struct mvneta_port *pp, 1729c5aff182SThomas Petazzoni struct mvneta_tx_queue *txq, 1730c5aff182SThomas Petazzoni int sent_desc) 1731c5aff182SThomas Petazzoni { 1732c5aff182SThomas Petazzoni u32 val; 1733c5aff182SThomas Petazzoni 1734c5aff182SThomas Petazzoni /* Only 255 TX descriptors can be updated at once */ 1735c5aff182SThomas Petazzoni while (sent_desc > 0xff) { 1736c5aff182SThomas Petazzoni val = 0xff << MVNETA_TXQ_DEC_SENT_SHIFT; 1737c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val); 1738c5aff182SThomas Petazzoni sent_desc = sent_desc - 0xff; 1739c5aff182SThomas Petazzoni } 1740c5aff182SThomas Petazzoni 1741c5aff182SThomas Petazzoni val = sent_desc << MVNETA_TXQ_DEC_SENT_SHIFT; 1742c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val); 1743c5aff182SThomas Petazzoni } 1744c5aff182SThomas Petazzoni 1745c5aff182SThomas Petazzoni /* Get number of TX descriptors already sent by HW */ 1746c5aff182SThomas Petazzoni static int mvneta_txq_sent_desc_num_get(struct mvneta_port *pp, 1747c5aff182SThomas Petazzoni struct mvneta_tx_queue *txq) 1748c5aff182SThomas Petazzoni { 1749c5aff182SThomas Petazzoni u32 val; 1750c5aff182SThomas Petazzoni int sent_desc; 1751c5aff182SThomas Petazzoni 1752c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_TXQ_STATUS_REG(txq->id)); 1753c5aff182SThomas Petazzoni sent_desc = (val & MVNETA_TXQ_SENT_DESC_MASK) >> 1754c5aff182SThomas Petazzoni MVNETA_TXQ_SENT_DESC_SHIFT; 1755c5aff182SThomas Petazzoni 1756c5aff182SThomas Petazzoni return sent_desc; 1757c5aff182SThomas Petazzoni } 1758c5aff182SThomas Petazzoni 17596a20c175SThomas Petazzoni /* Get number of sent descriptors and decrement counter. 1760c5aff182SThomas Petazzoni * The number of sent descriptors is returned. 1761c5aff182SThomas Petazzoni */ 1762c5aff182SThomas Petazzoni static int mvneta_txq_sent_desc_proc(struct mvneta_port *pp, 1763c5aff182SThomas Petazzoni struct mvneta_tx_queue *txq) 1764c5aff182SThomas Petazzoni { 1765c5aff182SThomas Petazzoni int sent_desc; 1766c5aff182SThomas Petazzoni 1767c5aff182SThomas Petazzoni /* Get number of sent descriptors */ 1768c5aff182SThomas Petazzoni sent_desc = mvneta_txq_sent_desc_num_get(pp, txq); 1769c5aff182SThomas Petazzoni 1770c5aff182SThomas Petazzoni /* Decrement sent descriptors counter */ 1771c5aff182SThomas Petazzoni if (sent_desc) 1772c5aff182SThomas Petazzoni mvneta_txq_sent_desc_dec(pp, txq, sent_desc); 1773c5aff182SThomas Petazzoni 1774c5aff182SThomas Petazzoni return sent_desc; 1775c5aff182SThomas Petazzoni } 1776c5aff182SThomas Petazzoni 1777c5aff182SThomas Petazzoni /* Set TXQ descriptors fields relevant for CSUM calculation */ 1778c5aff182SThomas Petazzoni static u32 mvneta_txq_desc_csum(int l3_offs, int l3_proto, 1779c5aff182SThomas Petazzoni int ip_hdr_len, int l4_proto) 1780c5aff182SThomas Petazzoni { 1781c5aff182SThomas Petazzoni u32 command; 1782c5aff182SThomas Petazzoni 1783c5aff182SThomas Petazzoni /* Fields: L3_offset, IP_hdrlen, L3_type, G_IPv4_chk, 17846a20c175SThomas Petazzoni * G_L4_chk, L4_type; required only for checksum 17856a20c175SThomas Petazzoni * calculation 17866a20c175SThomas Petazzoni */ 1787c5aff182SThomas Petazzoni command = l3_offs << MVNETA_TX_L3_OFF_SHIFT; 1788c5aff182SThomas Petazzoni command |= ip_hdr_len << MVNETA_TX_IP_HLEN_SHIFT; 1789c5aff182SThomas Petazzoni 17900a198587SThomas Fitzsimmons if (l3_proto == htons(ETH_P_IP)) 1791c5aff182SThomas Petazzoni command |= MVNETA_TXD_IP_CSUM; 1792c5aff182SThomas Petazzoni else 1793c5aff182SThomas Petazzoni command |= MVNETA_TX_L3_IP6; 1794c5aff182SThomas Petazzoni 1795c5aff182SThomas Petazzoni if (l4_proto == IPPROTO_TCP) 1796c5aff182SThomas Petazzoni command |= MVNETA_TX_L4_CSUM_FULL; 1797c5aff182SThomas Petazzoni else if (l4_proto == IPPROTO_UDP) 1798c5aff182SThomas Petazzoni command |= MVNETA_TX_L4_UDP | MVNETA_TX_L4_CSUM_FULL; 1799c5aff182SThomas Petazzoni else 1800c5aff182SThomas Petazzoni command |= MVNETA_TX_L4_CSUM_NOT; 1801c5aff182SThomas Petazzoni 1802c5aff182SThomas Petazzoni return command; 1803c5aff182SThomas Petazzoni } 1804c5aff182SThomas Petazzoni 1805c5aff182SThomas Petazzoni 1806c5aff182SThomas Petazzoni /* Display more error info */ 1807c5aff182SThomas Petazzoni static void mvneta_rx_error(struct mvneta_port *pp, 1808c5aff182SThomas Petazzoni struct mvneta_rx_desc *rx_desc) 1809c5aff182SThomas Petazzoni { 1810c35947b8SLorenzo Bianconi struct mvneta_pcpu_stats *stats = this_cpu_ptr(pp->stats); 1811c5aff182SThomas Petazzoni u32 status = rx_desc->status; 1812c5aff182SThomas Petazzoni 1813c35947b8SLorenzo Bianconi /* update per-cpu counter */ 1814c35947b8SLorenzo Bianconi u64_stats_update_begin(&stats->syncp); 1815c35947b8SLorenzo Bianconi stats->rx_errors++; 1816c35947b8SLorenzo Bianconi u64_stats_update_end(&stats->syncp); 1817c35947b8SLorenzo Bianconi 1818c5aff182SThomas Petazzoni switch (status & MVNETA_RXD_ERR_CODE_MASK) { 1819c5aff182SThomas Petazzoni case MVNETA_RXD_ERR_CRC: 1820c5aff182SThomas Petazzoni netdev_err(pp->dev, "bad rx status %08x (crc error), size=%d\n", 1821c5aff182SThomas Petazzoni status, rx_desc->data_size); 1822c5aff182SThomas Petazzoni break; 1823c5aff182SThomas Petazzoni case MVNETA_RXD_ERR_OVERRUN: 1824c5aff182SThomas Petazzoni netdev_err(pp->dev, "bad rx status %08x (overrun error), size=%d\n", 1825c5aff182SThomas Petazzoni status, rx_desc->data_size); 1826c5aff182SThomas Petazzoni break; 1827c5aff182SThomas Petazzoni case MVNETA_RXD_ERR_LEN: 1828c5aff182SThomas Petazzoni netdev_err(pp->dev, "bad rx status %08x (max frame length error), size=%d\n", 1829c5aff182SThomas Petazzoni status, rx_desc->data_size); 1830c5aff182SThomas Petazzoni break; 1831c5aff182SThomas Petazzoni case MVNETA_RXD_ERR_RESOURCE: 1832c5aff182SThomas Petazzoni netdev_err(pp->dev, "bad rx status %08x (resource error), size=%d\n", 1833c5aff182SThomas Petazzoni status, rx_desc->data_size); 1834c5aff182SThomas Petazzoni break; 1835c5aff182SThomas Petazzoni } 1836c5aff182SThomas Petazzoni } 1837c5aff182SThomas Petazzoni 18385428213cSwilly tarreau /* Handle RX checksum offload based on the descriptor's status */ 1839aff0824dSLorenzo Bianconi static int mvneta_rx_csum(struct mvneta_port *pp, u32 status) 1840c5aff182SThomas Petazzoni { 1841f945cec8SYelena Krivosheev if ((pp->dev->features & NETIF_F_RXCSUM) && 1842f945cec8SYelena Krivosheev (status & MVNETA_RXD_L3_IP4) && 1843aff0824dSLorenzo Bianconi (status & MVNETA_RXD_L4_CSUM_OK)) 1844aff0824dSLorenzo Bianconi return CHECKSUM_UNNECESSARY; 1845c5aff182SThomas Petazzoni 1846aff0824dSLorenzo Bianconi return CHECKSUM_NONE; 1847c5aff182SThomas Petazzoni } 1848c5aff182SThomas Petazzoni 18496c498974Swilly tarreau /* Return tx queue pointer (find last set bit) according to <cause> returned 18506c498974Swilly tarreau * form tx_done reg. <cause> must not be null. The return value is always a 18516c498974Swilly tarreau * valid queue for matching the first one found in <cause>. 18526c498974Swilly tarreau */ 1853c5aff182SThomas Petazzoni static struct mvneta_tx_queue *mvneta_tx_done_policy(struct mvneta_port *pp, 1854c5aff182SThomas Petazzoni u32 cause) 1855c5aff182SThomas Petazzoni { 1856c5aff182SThomas Petazzoni int queue = fls(cause) - 1; 1857c5aff182SThomas Petazzoni 18586c498974Swilly tarreau return &pp->txqs[queue]; 1859c5aff182SThomas Petazzoni } 1860c5aff182SThomas Petazzoni 1861c5aff182SThomas Petazzoni /* Free tx queue skbuffs */ 1862c5aff182SThomas Petazzoni static void mvneta_txq_bufs_free(struct mvneta_port *pp, 1863a29b6235SMarcin Wojtas struct mvneta_tx_queue *txq, int num, 1864632bb64fSLorenzo Bianconi struct netdev_queue *nq, bool napi) 1865c5aff182SThomas Petazzoni { 1866a29b6235SMarcin Wojtas unsigned int bytes_compl = 0, pkts_compl = 0; 18672f9d0939SLorenzo Bianconi struct xdp_frame_bulk bq; 1868c5aff182SThomas Petazzoni int i; 1869c5aff182SThomas Petazzoni 18702f9d0939SLorenzo Bianconi xdp_frame_bulk_init(&bq); 18712f9d0939SLorenzo Bianconi 18722f9d0939SLorenzo Bianconi rcu_read_lock(); /* need for xdp_return_frame_bulk */ 18732f9d0939SLorenzo Bianconi 1874c5aff182SThomas Petazzoni for (i = 0; i < num; i++) { 18759e58c8b4SLorenzo Bianconi struct mvneta_tx_buf *buf = &txq->buf[txq->txq_get_index]; 1876c5aff182SThomas Petazzoni struct mvneta_tx_desc *tx_desc = txq->descs + 1877c5aff182SThomas Petazzoni txq->txq_get_index; 1878a29b6235SMarcin Wojtas 1879c5aff182SThomas Petazzoni mvneta_txq_inc_get(txq); 1880c5aff182SThomas Petazzoni 1881b0a43db9SLorenzo Bianconi if (!IS_TSO_HEADER(txq, tx_desc->buf_phys_addr) && 1882b0a43db9SLorenzo Bianconi buf->type != MVNETA_TYPE_XDP_TX) 18832e3173a3SEzequiel Garcia dma_unmap_single(pp->dev->dev.parent, 18842e3173a3SEzequiel Garcia tx_desc->buf_phys_addr, 1885c5aff182SThomas Petazzoni tx_desc->data_size, DMA_TO_DEVICE); 1886b0a43db9SLorenzo Bianconi if (buf->type == MVNETA_TYPE_SKB && buf->skb) { 18879e58c8b4SLorenzo Bianconi bytes_compl += buf->skb->len; 18889e58c8b4SLorenzo Bianconi pkts_compl++; 18899e58c8b4SLorenzo Bianconi dev_kfree_skb_any(buf->skb); 1890c41ced02SLorenzo Bianconi } else if ((buf->type == MVNETA_TYPE_XDP_TX || 1891c41ced02SLorenzo Bianconi buf->type == MVNETA_TYPE_XDP_NDO) && buf->xdpf) { 1892632bb64fSLorenzo Bianconi if (napi && buf->type == MVNETA_TYPE_XDP_TX) 1893632bb64fSLorenzo Bianconi xdp_return_frame_rx_napi(buf->xdpf); 1894632bb64fSLorenzo Bianconi else 18952f9d0939SLorenzo Bianconi xdp_return_frame_bulk(buf->xdpf, &bq); 1896b0a43db9SLorenzo Bianconi } 1897c5aff182SThomas Petazzoni } 18982f9d0939SLorenzo Bianconi xdp_flush_frame_bulk(&bq); 18992f9d0939SLorenzo Bianconi 19002f9d0939SLorenzo Bianconi rcu_read_unlock(); 1901a29b6235SMarcin Wojtas 1902a29b6235SMarcin Wojtas netdev_tx_completed_queue(nq, pkts_compl, bytes_compl); 1903c5aff182SThomas Petazzoni } 1904c5aff182SThomas Petazzoni 1905c5aff182SThomas Petazzoni /* Handle end of transmission */ 1906cd713199SArnaud Ebalard static void mvneta_txq_done(struct mvneta_port *pp, 1907c5aff182SThomas Petazzoni struct mvneta_tx_queue *txq) 1908c5aff182SThomas Petazzoni { 1909c5aff182SThomas Petazzoni struct netdev_queue *nq = netdev_get_tx_queue(pp->dev, txq->id); 1910c5aff182SThomas Petazzoni int tx_done; 1911c5aff182SThomas Petazzoni 1912c5aff182SThomas Petazzoni tx_done = mvneta_txq_sent_desc_proc(pp, txq); 1913cd713199SArnaud Ebalard if (!tx_done) 1914cd713199SArnaud Ebalard return; 1915cd713199SArnaud Ebalard 1916632bb64fSLorenzo Bianconi mvneta_txq_bufs_free(pp, txq, tx_done, nq, true); 1917c5aff182SThomas Petazzoni 1918c5aff182SThomas Petazzoni txq->count -= tx_done; 1919c5aff182SThomas Petazzoni 1920c5aff182SThomas Petazzoni if (netif_tx_queue_stopped(nq)) { 19218eef5f97SEzequiel Garcia if (txq->count <= txq->tx_wake_threshold) 1922c5aff182SThomas Petazzoni netif_tx_wake_queue(nq); 1923c5aff182SThomas Petazzoni } 1924c5aff182SThomas Petazzoni } 1925c5aff182SThomas Petazzoni 1926dc35a10fSMarcin Wojtas /* Refill processing for SW buffer management */ 19277e47fd84SGregory CLEMENT /* Allocate page per descriptor */ 1928c5aff182SThomas Petazzoni static int mvneta_rx_refill(struct mvneta_port *pp, 1929f88bee1cSGregory CLEMENT struct mvneta_rx_desc *rx_desc, 19307e47fd84SGregory CLEMENT struct mvneta_rx_queue *rxq, 19317e47fd84SGregory CLEMENT gfp_t gfp_mask) 1932c5aff182SThomas Petazzoni { 1933c5aff182SThomas Petazzoni dma_addr_t phys_addr; 19347e47fd84SGregory CLEMENT struct page *page; 1935c5aff182SThomas Petazzoni 1936568a3fa2SLorenzo Bianconi page = page_pool_alloc_pages(rxq->page_pool, 1937568a3fa2SLorenzo Bianconi gfp_mask | __GFP_NOWARN); 19387e47fd84SGregory CLEMENT if (!page) 1939c5aff182SThomas Petazzoni return -ENOMEM; 1940c5aff182SThomas Petazzoni 1941568a3fa2SLorenzo Bianconi phys_addr = page_pool_get_dma_addr(page) + pp->rx_offset_correction; 19427e47fd84SGregory CLEMENT mvneta_rx_desc_fill(rx_desc, phys_addr, page, rxq); 1943568a3fa2SLorenzo Bianconi 1944c5aff182SThomas Petazzoni return 0; 1945c5aff182SThomas Petazzoni } 1946c5aff182SThomas Petazzoni 1947c5aff182SThomas Petazzoni /* Handle tx checksum */ 194820d446f2SYuval Shaia static u32 mvneta_skb_tx_csum(struct sk_buff *skb) 1949c5aff182SThomas Petazzoni { 1950c5aff182SThomas Petazzoni if (skb->ip_summed == CHECKSUM_PARTIAL) { 1951c5aff182SThomas Petazzoni int ip_hdr_len = 0; 1952817dbfa5SVlad Yasevich __be16 l3_proto = vlan_get_protocol(skb); 1953c5aff182SThomas Petazzoni u8 l4_proto; 1954c5aff182SThomas Petazzoni 1955817dbfa5SVlad Yasevich if (l3_proto == htons(ETH_P_IP)) { 1956c5aff182SThomas Petazzoni struct iphdr *ip4h = ip_hdr(skb); 1957c5aff182SThomas Petazzoni 1958c5aff182SThomas Petazzoni /* Calculate IPv4 checksum and L4 checksum */ 1959c5aff182SThomas Petazzoni ip_hdr_len = ip4h->ihl; 1960c5aff182SThomas Petazzoni l4_proto = ip4h->protocol; 1961817dbfa5SVlad Yasevich } else if (l3_proto == htons(ETH_P_IPV6)) { 1962c5aff182SThomas Petazzoni struct ipv6hdr *ip6h = ipv6_hdr(skb); 1963c5aff182SThomas Petazzoni 1964c5aff182SThomas Petazzoni /* Read l4_protocol from one of IPv6 extra headers */ 1965c5aff182SThomas Petazzoni if (skb_network_header_len(skb) > 0) 1966c5aff182SThomas Petazzoni ip_hdr_len = (skb_network_header_len(skb) >> 2); 1967c5aff182SThomas Petazzoni l4_proto = ip6h->nexthdr; 1968c5aff182SThomas Petazzoni } else 1969c5aff182SThomas Petazzoni return MVNETA_TX_L4_CSUM_NOT; 1970c5aff182SThomas Petazzoni 1971c5aff182SThomas Petazzoni return mvneta_txq_desc_csum(skb_network_offset(skb), 1972817dbfa5SVlad Yasevich l3_proto, ip_hdr_len, l4_proto); 1973c5aff182SThomas Petazzoni } 1974c5aff182SThomas Petazzoni 1975c5aff182SThomas Petazzoni return MVNETA_TX_L4_CSUM_NOT; 1976c5aff182SThomas Petazzoni } 1977c5aff182SThomas Petazzoni 1978c5aff182SThomas Petazzoni /* Drop packets received by the RXQ and free buffers */ 1979c5aff182SThomas Petazzoni static void mvneta_rxq_drop_pkts(struct mvneta_port *pp, 1980c5aff182SThomas Petazzoni struct mvneta_rx_queue *rxq) 1981c5aff182SThomas Petazzoni { 1982c5aff182SThomas Petazzoni int rx_done, i; 1983c5aff182SThomas Petazzoni 1984c5aff182SThomas Petazzoni rx_done = mvneta_rxq_busy_desc_num_get(pp, rxq); 1985dc35a10fSMarcin Wojtas if (rx_done) 1986dc35a10fSMarcin Wojtas mvneta_rxq_desc_num_update(pp, rxq, rx_done, rx_done); 1987dc35a10fSMarcin Wojtas 1988dc35a10fSMarcin Wojtas if (pp->bm_priv) { 1989dc35a10fSMarcin Wojtas for (i = 0; i < rx_done; i++) { 1990dc35a10fSMarcin Wojtas struct mvneta_rx_desc *rx_desc = 1991dc35a10fSMarcin Wojtas mvneta_rxq_next_desc_get(rxq); 1992dc35a10fSMarcin Wojtas u8 pool_id = MVNETA_RX_GET_BM_POOL_ID(rx_desc); 1993dc35a10fSMarcin Wojtas struct mvneta_bm_pool *bm_pool; 1994dc35a10fSMarcin Wojtas 1995dc35a10fSMarcin Wojtas bm_pool = &pp->bm_priv->bm_pools[pool_id]; 1996dc35a10fSMarcin Wojtas /* Return dropped buffer to the pool */ 1997dc35a10fSMarcin Wojtas mvneta_bm_pool_put_bp(pp->bm_priv, bm_pool, 1998dc35a10fSMarcin Wojtas rx_desc->buf_phys_addr); 1999dc35a10fSMarcin Wojtas } 2000dc35a10fSMarcin Wojtas return; 2001dc35a10fSMarcin Wojtas } 2002dc35a10fSMarcin Wojtas 2003c5aff182SThomas Petazzoni for (i = 0; i < rxq->size; i++) { 2004c5aff182SThomas Petazzoni struct mvneta_rx_desc *rx_desc = rxq->descs + i; 2005f88bee1cSGregory CLEMENT void *data = rxq->buf_virt_addr[i]; 2006562e2f46SYelena Krivosheev if (!data || !(rx_desc->buf_phys_addr)) 2007562e2f46SYelena Krivosheev continue; 2008c5aff182SThomas Petazzoni 2009458de8a9SIlias Apalodimas page_pool_put_full_page(rxq->page_pool, data, false); 2010dc35a10fSMarcin Wojtas } 2011568a3fa2SLorenzo Bianconi if (xdp_rxq_info_is_reg(&rxq->xdp_rxq)) 2012568a3fa2SLorenzo Bianconi xdp_rxq_info_unreg(&rxq->xdp_rxq); 2013568a3fa2SLorenzo Bianconi page_pool_destroy(rxq->page_pool); 2014568a3fa2SLorenzo Bianconi rxq->page_pool = NULL; 2015c5aff182SThomas Petazzoni } 2016c5aff182SThomas Petazzoni 2017ff519e2aSLorenzo Bianconi static void 2018320d5441SLorenzo Bianconi mvneta_update_stats(struct mvneta_port *pp, 2019320d5441SLorenzo Bianconi struct mvneta_stats *ps) 2020ff519e2aSLorenzo Bianconi { 2021ff519e2aSLorenzo Bianconi struct mvneta_pcpu_stats *stats = this_cpu_ptr(pp->stats); 2022ff519e2aSLorenzo Bianconi 2023ff519e2aSLorenzo Bianconi u64_stats_update_begin(&stats->syncp); 2024320d5441SLorenzo Bianconi stats->es.ps.rx_packets += ps->rx_packets; 2025320d5441SLorenzo Bianconi stats->es.ps.rx_bytes += ps->rx_bytes; 20263d866523SLorenzo Bianconi /* xdp */ 20273d866523SLorenzo Bianconi stats->es.ps.xdp_redirect += ps->xdp_redirect; 20283d866523SLorenzo Bianconi stats->es.ps.xdp_pass += ps->xdp_pass; 20293d866523SLorenzo Bianconi stats->es.ps.xdp_drop += ps->xdp_drop; 2030ff519e2aSLorenzo Bianconi u64_stats_update_end(&stats->syncp); 2031ff519e2aSLorenzo Bianconi } 2032ff519e2aSLorenzo Bianconi 2033562e2f46SYelena Krivosheev static inline 2034562e2f46SYelena Krivosheev int mvneta_rx_refill_queue(struct mvneta_port *pp, struct mvneta_rx_queue *rxq) 2035562e2f46SYelena Krivosheev { 2036562e2f46SYelena Krivosheev struct mvneta_rx_desc *rx_desc; 2037562e2f46SYelena Krivosheev int curr_desc = rxq->first_to_refill; 2038562e2f46SYelena Krivosheev int i; 2039562e2f46SYelena Krivosheev 2040562e2f46SYelena Krivosheev for (i = 0; (i < rxq->refill_num) && (i < 64); i++) { 2041562e2f46SYelena Krivosheev rx_desc = rxq->descs + curr_desc; 2042562e2f46SYelena Krivosheev if (!(rx_desc->buf_phys_addr)) { 2043562e2f46SYelena Krivosheev if (mvneta_rx_refill(pp, rx_desc, rxq, GFP_ATOMIC)) { 20449ac41f3cSLorenzo Bianconi struct mvneta_pcpu_stats *stats; 20459ac41f3cSLorenzo Bianconi 2046562e2f46SYelena Krivosheev pr_err("Can't refill queue %d. Done %d from %d\n", 2047562e2f46SYelena Krivosheev rxq->id, i, rxq->refill_num); 20489ac41f3cSLorenzo Bianconi 20499ac41f3cSLorenzo Bianconi stats = this_cpu_ptr(pp->stats); 20509ac41f3cSLorenzo Bianconi u64_stats_update_begin(&stats->syncp); 20519ac41f3cSLorenzo Bianconi stats->es.refill_error++; 20529ac41f3cSLorenzo Bianconi u64_stats_update_end(&stats->syncp); 2053562e2f46SYelena Krivosheev break; 2054562e2f46SYelena Krivosheev } 2055562e2f46SYelena Krivosheev } 2056562e2f46SYelena Krivosheev curr_desc = MVNETA_QUEUE_NEXT_DESC(rxq, curr_desc); 2057562e2f46SYelena Krivosheev } 2058562e2f46SYelena Krivosheev rxq->refill_num -= i; 2059562e2f46SYelena Krivosheev rxq->first_to_refill = curr_desc; 2060562e2f46SYelena Krivosheev 2061562e2f46SYelena Krivosheev return i; 2062562e2f46SYelena Krivosheev } 2063562e2f46SYelena Krivosheev 2064ca0e0146SLorenzo Bianconi static void 2065ca0e0146SLorenzo Bianconi mvneta_xdp_put_buff(struct mvneta_port *pp, struct mvneta_rx_queue *rxq, 2066d094c985SLorenzo Bianconi struct xdp_buff *xdp, int sync_len) 2067ca0e0146SLorenzo Bianconi { 2068d094c985SLorenzo Bianconi struct skb_shared_info *sinfo = xdp_get_shared_info_from_buff(xdp); 2069ca0e0146SLorenzo Bianconi int i; 2070ca0e0146SLorenzo Bianconi 207176a67694SLorenzo Bianconi if (likely(!xdp_buff_has_frags(xdp))) 207276a67694SLorenzo Bianconi goto out; 207376a67694SLorenzo Bianconi 2074ca0e0146SLorenzo Bianconi for (i = 0; i < sinfo->nr_frags; i++) 2075ca0e0146SLorenzo Bianconi page_pool_put_full_page(rxq->page_pool, 2076eb33f118SLorenzo Bianconi skb_frag_page(&sinfo->frags[i]), true); 207776a67694SLorenzo Bianconi 207876a67694SLorenzo Bianconi out: 20799d3b2d3eSLorenzo Bianconi page_pool_put_page(rxq->page_pool, virt_to_head_page(xdp->data), 2080eb33f118SLorenzo Bianconi sync_len, true); 2081ca0e0146SLorenzo Bianconi } 2082ca0e0146SLorenzo Bianconi 20838dc9a088SLorenzo Bianconi static int 2084b0a43db9SLorenzo Bianconi mvneta_xdp_submit_frame(struct mvneta_port *pp, struct mvneta_tx_queue *txq, 2085c41ced02SLorenzo Bianconi struct xdp_frame *xdpf, int *nxmit_byte, bool dma_map) 2086b0a43db9SLorenzo Bianconi { 2087c41ced02SLorenzo Bianconi struct skb_shared_info *sinfo = xdp_get_shared_info_from_frame(xdpf); 2088c41ced02SLorenzo Bianconi struct device *dev = pp->dev->dev.parent; 2089c52db246SLorenzo Bianconi struct mvneta_tx_desc *tx_desc; 2090c41ced02SLorenzo Bianconi int i, num_frames = 1; 2091c41ced02SLorenzo Bianconi struct page *page; 2092c41ced02SLorenzo Bianconi 2093c41ced02SLorenzo Bianconi if (unlikely(xdp_frame_has_frags(xdpf))) 2094c41ced02SLorenzo Bianconi num_frames += sinfo->nr_frags; 2095c41ced02SLorenzo Bianconi 2096c41ced02SLorenzo Bianconi if (txq->count + num_frames >= txq->size) 2097c41ced02SLorenzo Bianconi return MVNETA_XDP_DROPPED; 2098c41ced02SLorenzo Bianconi 2099c41ced02SLorenzo Bianconi for (i = 0; i < num_frames; i++) { 2100c41ced02SLorenzo Bianconi struct mvneta_tx_buf *buf = &txq->buf[txq->txq_put_index]; 2101c41ced02SLorenzo Bianconi skb_frag_t *frag = NULL; 2102c41ced02SLorenzo Bianconi int len = xdpf->len; 2103b0a43db9SLorenzo Bianconi dma_addr_t dma_addr; 2104b0a43db9SLorenzo Bianconi 2105c41ced02SLorenzo Bianconi if (unlikely(i)) { /* paged area */ 2106c41ced02SLorenzo Bianconi frag = &sinfo->frags[i - 1]; 2107c41ced02SLorenzo Bianconi len = skb_frag_size(frag); 2108c41ced02SLorenzo Bianconi } 2109b0a43db9SLorenzo Bianconi 2110b0a43db9SLorenzo Bianconi tx_desc = mvneta_txq_next_desc_get(txq); 2111b0a43db9SLorenzo Bianconi if (dma_map) { 2112b0a43db9SLorenzo Bianconi /* ndo_xdp_xmit */ 2113c41ced02SLorenzo Bianconi void *data; 2114c41ced02SLorenzo Bianconi 2115c41ced02SLorenzo Bianconi data = unlikely(frag) ? skb_frag_address(frag) 2116c41ced02SLorenzo Bianconi : xdpf->data; 2117c41ced02SLorenzo Bianconi dma_addr = dma_map_single(dev, data, len, 2118c41ced02SLorenzo Bianconi DMA_TO_DEVICE); 2119c41ced02SLorenzo Bianconi if (dma_mapping_error(dev, dma_addr)) { 2120b0a43db9SLorenzo Bianconi mvneta_txq_desc_put(txq); 2121c41ced02SLorenzo Bianconi goto unmap; 2122b0a43db9SLorenzo Bianconi } 2123c41ced02SLorenzo Bianconi 2124b0a43db9SLorenzo Bianconi buf->type = MVNETA_TYPE_XDP_NDO; 2125b0a43db9SLorenzo Bianconi } else { 2126c41ced02SLorenzo Bianconi page = unlikely(frag) ? skb_frag_page(frag) 2127c41ced02SLorenzo Bianconi : virt_to_page(xdpf->data); 2128c41ced02SLorenzo Bianconi dma_addr = page_pool_get_dma_addr(page); 2129c41ced02SLorenzo Bianconi if (unlikely(frag)) 2130c41ced02SLorenzo Bianconi dma_addr += skb_frag_off(frag); 2131c41ced02SLorenzo Bianconi else 2132c41ced02SLorenzo Bianconi dma_addr += sizeof(*xdpf) + xdpf->headroom; 2133c41ced02SLorenzo Bianconi dma_sync_single_for_device(dev, dma_addr, len, 2134c41ced02SLorenzo Bianconi DMA_BIDIRECTIONAL); 2135b0a43db9SLorenzo Bianconi buf->type = MVNETA_TYPE_XDP_TX; 2136b0a43db9SLorenzo Bianconi } 2137c41ced02SLorenzo Bianconi buf->xdpf = unlikely(i) ? NULL : xdpf; 2138b0a43db9SLorenzo Bianconi 2139c41ced02SLorenzo Bianconi tx_desc->command = unlikely(i) ? 0 : MVNETA_TXD_F_DESC; 2140b0a43db9SLorenzo Bianconi tx_desc->buf_phys_addr = dma_addr; 2141c41ced02SLorenzo Bianconi tx_desc->data_size = len; 2142c41ced02SLorenzo Bianconi *nxmit_byte += len; 2143b0a43db9SLorenzo Bianconi 2144b0a43db9SLorenzo Bianconi mvneta_txq_inc_put(txq); 2145c41ced02SLorenzo Bianconi } 2146c41ced02SLorenzo Bianconi /*last descriptor */ 2147c41ced02SLorenzo Bianconi tx_desc->command |= MVNETA_TXD_L_DESC | MVNETA_TXD_Z_PAD; 2148c41ced02SLorenzo Bianconi 2149c41ced02SLorenzo Bianconi txq->pending += num_frames; 2150c41ced02SLorenzo Bianconi txq->count += num_frames; 2151b0a43db9SLorenzo Bianconi 2152b0a43db9SLorenzo Bianconi return MVNETA_XDP_TX; 2153c41ced02SLorenzo Bianconi 2154c41ced02SLorenzo Bianconi unmap: 2155c41ced02SLorenzo Bianconi for (i--; i >= 0; i--) { 2156c41ced02SLorenzo Bianconi mvneta_txq_desc_put(txq); 2157c41ced02SLorenzo Bianconi tx_desc = txq->descs + txq->next_desc_to_proc; 2158c41ced02SLorenzo Bianconi dma_unmap_single(dev, tx_desc->buf_phys_addr, 2159c41ced02SLorenzo Bianconi tx_desc->data_size, 2160c41ced02SLorenzo Bianconi DMA_TO_DEVICE); 2161c41ced02SLorenzo Bianconi } 2162c41ced02SLorenzo Bianconi 2163c41ced02SLorenzo Bianconi return MVNETA_XDP_DROPPED; 2164b0a43db9SLorenzo Bianconi } 2165b0a43db9SLorenzo Bianconi 2166b0a43db9SLorenzo Bianconi static int 2167b0a43db9SLorenzo Bianconi mvneta_xdp_xmit_back(struct mvneta_port *pp, struct xdp_buff *xdp) 2168b0a43db9SLorenzo Bianconi { 216915070919SJesper Dangaard Brouer struct mvneta_pcpu_stats *stats = this_cpu_ptr(pp->stats); 2170b0a43db9SLorenzo Bianconi struct mvneta_tx_queue *txq; 2171b0a43db9SLorenzo Bianconi struct netdev_queue *nq; 2172c41ced02SLorenzo Bianconi int cpu, nxmit_byte = 0; 2173b0a43db9SLorenzo Bianconi struct xdp_frame *xdpf; 2174b0a43db9SLorenzo Bianconi u32 ret; 2175b0a43db9SLorenzo Bianconi 21761b698fa5SLorenzo Bianconi xdpf = xdp_convert_buff_to_frame(xdp); 2177b0a43db9SLorenzo Bianconi if (unlikely(!xdpf)) 2178b0a43db9SLorenzo Bianconi return MVNETA_XDP_DROPPED; 2179b0a43db9SLorenzo Bianconi 2180b0a43db9SLorenzo Bianconi cpu = smp_processor_id(); 2181b0a43db9SLorenzo Bianconi txq = &pp->txqs[cpu % txq_number]; 2182b0a43db9SLorenzo Bianconi nq = netdev_get_tx_queue(pp->dev, txq->id); 2183b0a43db9SLorenzo Bianconi 2184b0a43db9SLorenzo Bianconi __netif_tx_lock(nq, cpu); 2185c41ced02SLorenzo Bianconi ret = mvneta_xdp_submit_frame(pp, txq, xdpf, &nxmit_byte, false); 21867d51a015SLorenzo Bianconi if (ret == MVNETA_XDP_TX) { 21877d51a015SLorenzo Bianconi u64_stats_update_begin(&stats->syncp); 2188c41ced02SLorenzo Bianconi stats->es.ps.tx_bytes += nxmit_byte; 21897d51a015SLorenzo Bianconi stats->es.ps.tx_packets++; 21907d51a015SLorenzo Bianconi stats->es.ps.xdp_tx++; 21917d51a015SLorenzo Bianconi u64_stats_update_end(&stats->syncp); 21927d51a015SLorenzo Bianconi 2193b0a43db9SLorenzo Bianconi mvneta_txq_pend_desc_add(pp, txq, 0); 219415070919SJesper Dangaard Brouer } else { 219515070919SJesper Dangaard Brouer u64_stats_update_begin(&stats->syncp); 219615070919SJesper Dangaard Brouer stats->es.ps.xdp_tx_err++; 219715070919SJesper Dangaard Brouer u64_stats_update_end(&stats->syncp); 21987d51a015SLorenzo Bianconi } 2199b0a43db9SLorenzo Bianconi __netif_tx_unlock(nq); 2200b0a43db9SLorenzo Bianconi 2201b0a43db9SLorenzo Bianconi return ret; 2202b0a43db9SLorenzo Bianconi } 2203b0a43db9SLorenzo Bianconi 2204b0a43db9SLorenzo Bianconi static int 2205b0a43db9SLorenzo Bianconi mvneta_xdp_xmit(struct net_device *dev, int num_frame, 2206b0a43db9SLorenzo Bianconi struct xdp_frame **frames, u32 flags) 2207b0a43db9SLorenzo Bianconi { 2208b0a43db9SLorenzo Bianconi struct mvneta_port *pp = netdev_priv(dev); 22097d51a015SLorenzo Bianconi struct mvneta_pcpu_stats *stats = this_cpu_ptr(pp->stats); 2210fdc13979SLorenzo Bianconi int i, nxmit_byte = 0, nxmit = 0; 2211b0a43db9SLorenzo Bianconi int cpu = smp_processor_id(); 2212b0a43db9SLorenzo Bianconi struct mvneta_tx_queue *txq; 2213b0a43db9SLorenzo Bianconi struct netdev_queue *nq; 2214b0a43db9SLorenzo Bianconi u32 ret; 2215b0a43db9SLorenzo Bianconi 221662a502ccSLorenzo Bianconi if (unlikely(test_bit(__MVNETA_DOWN, &pp->state))) 221762a502ccSLorenzo Bianconi return -ENETDOWN; 221862a502ccSLorenzo Bianconi 2219b0a43db9SLorenzo Bianconi if (unlikely(flags & ~XDP_XMIT_FLAGS_MASK)) 2220b0a43db9SLorenzo Bianconi return -EINVAL; 2221b0a43db9SLorenzo Bianconi 2222b0a43db9SLorenzo Bianconi txq = &pp->txqs[cpu % txq_number]; 2223b0a43db9SLorenzo Bianconi nq = netdev_get_tx_queue(pp->dev, txq->id); 2224b0a43db9SLorenzo Bianconi 2225b0a43db9SLorenzo Bianconi __netif_tx_lock(nq, cpu); 2226b0a43db9SLorenzo Bianconi for (i = 0; i < num_frame; i++) { 2227c41ced02SLorenzo Bianconi ret = mvneta_xdp_submit_frame(pp, txq, frames[i], &nxmit_byte, 2228c41ced02SLorenzo Bianconi true); 2229fdc13979SLorenzo Bianconi if (ret != MVNETA_XDP_TX) 2230fdc13979SLorenzo Bianconi break; 2231fdc13979SLorenzo Bianconi 2232fdc13979SLorenzo Bianconi nxmit++; 2233b0a43db9SLorenzo Bianconi } 2234b0a43db9SLorenzo Bianconi 2235b0a43db9SLorenzo Bianconi if (unlikely(flags & XDP_XMIT_FLUSH)) 2236b0a43db9SLorenzo Bianconi mvneta_txq_pend_desc_add(pp, txq, 0); 2237b0a43db9SLorenzo Bianconi __netif_tx_unlock(nq); 2238b0a43db9SLorenzo Bianconi 22397d51a015SLorenzo Bianconi u64_stats_update_begin(&stats->syncp); 22407d51a015SLorenzo Bianconi stats->es.ps.tx_bytes += nxmit_byte; 22417d51a015SLorenzo Bianconi stats->es.ps.tx_packets += nxmit; 22427d51a015SLorenzo Bianconi stats->es.ps.xdp_xmit += nxmit; 224315070919SJesper Dangaard Brouer stats->es.ps.xdp_xmit_err += num_frame - nxmit; 22447d51a015SLorenzo Bianconi u64_stats_update_end(&stats->syncp); 22457d51a015SLorenzo Bianconi 22467d51a015SLorenzo Bianconi return nxmit; 2247b0a43db9SLorenzo Bianconi } 2248b0a43db9SLorenzo Bianconi 2249b0a43db9SLorenzo Bianconi static int 22500db51da7SLorenzo Bianconi mvneta_run_xdp(struct mvneta_port *pp, struct mvneta_rx_queue *rxq, 2251320d5441SLorenzo Bianconi struct bpf_prog *prog, struct xdp_buff *xdp, 22527d1643ebSLorenzo Bianconi u32 frame_sz, struct mvneta_stats *stats) 22530db51da7SLorenzo Bianconi { 22547d1643ebSLorenzo Bianconi unsigned int len, data_len, sync; 22558c4df83fSLorenzo Bianconi u32 ret, act; 22568c4df83fSLorenzo Bianconi 22578c4df83fSLorenzo Bianconi len = xdp->data_end - xdp->data_hard_start - pp->rx_offset_correction; 22587d1643ebSLorenzo Bianconi data_len = xdp->data_end - xdp->data; 22598c4df83fSLorenzo Bianconi act = bpf_prog_run_xdp(prog, xdp); 22600db51da7SLorenzo Bianconi 2261494f44d5SJesper Dangaard Brouer /* Due xdp_adjust_tail: DMA sync for_device cover max len CPU touch */ 2262494f44d5SJesper Dangaard Brouer sync = xdp->data_end - xdp->data_hard_start - pp->rx_offset_correction; 2263494f44d5SJesper Dangaard Brouer sync = max(sync, len); 2264494f44d5SJesper Dangaard Brouer 22650db51da7SLorenzo Bianconi switch (act) { 22660db51da7SLorenzo Bianconi case XDP_PASS: 22673d866523SLorenzo Bianconi stats->xdp_pass++; 2268320d5441SLorenzo Bianconi return MVNETA_XDP_PASS; 22690db51da7SLorenzo Bianconi case XDP_REDIRECT: { 22700db51da7SLorenzo Bianconi int err; 22710db51da7SLorenzo Bianconi 22720db51da7SLorenzo Bianconi err = xdp_do_redirect(pp->dev, xdp, prog); 227315070919SJesper Dangaard Brouer if (unlikely(err)) { 2274d094c985SLorenzo Bianconi mvneta_xdp_put_buff(pp, rxq, xdp, sync); 22750db51da7SLorenzo Bianconi ret = MVNETA_XDP_DROPPED; 22760db51da7SLorenzo Bianconi } else { 22770db51da7SLorenzo Bianconi ret = MVNETA_XDP_REDIR; 22783d866523SLorenzo Bianconi stats->xdp_redirect++; 22790db51da7SLorenzo Bianconi } 22800db51da7SLorenzo Bianconi break; 22810db51da7SLorenzo Bianconi } 2282b0a43db9SLorenzo Bianconi case XDP_TX: 2283b0a43db9SLorenzo Bianconi ret = mvneta_xdp_xmit_back(pp, xdp); 22847d1643ebSLorenzo Bianconi if (ret != MVNETA_XDP_TX) 2285d094c985SLorenzo Bianconi mvneta_xdp_put_buff(pp, rxq, xdp, sync); 2286b0a43db9SLorenzo Bianconi break; 22870db51da7SLorenzo Bianconi default: 2288c8064e5bSPaolo Abeni bpf_warn_invalid_xdp_action(pp->dev, prog, act); 2289df561f66SGustavo A. R. Silva fallthrough; 22900db51da7SLorenzo Bianconi case XDP_ABORTED: 22910db51da7SLorenzo Bianconi trace_xdp_exception(pp->dev, prog, act); 2292df561f66SGustavo A. R. Silva fallthrough; 22930db51da7SLorenzo Bianconi case XDP_DROP: 2294d094c985SLorenzo Bianconi mvneta_xdp_put_buff(pp, rxq, xdp, sync); 22950db51da7SLorenzo Bianconi ret = MVNETA_XDP_DROPPED; 22963d866523SLorenzo Bianconi stats->xdp_drop++; 22970db51da7SLorenzo Bianconi break; 22980db51da7SLorenzo Bianconi } 22990db51da7SLorenzo Bianconi 23007d1643ebSLorenzo Bianconi stats->rx_bytes += frame_sz + xdp->data_end - xdp->data - data_len; 2301320d5441SLorenzo Bianconi stats->rx_packets++; 2302320d5441SLorenzo Bianconi 23030db51da7SLorenzo Bianconi return ret; 23040db51da7SLorenzo Bianconi } 23050db51da7SLorenzo Bianconi 2306afda408bSLorenzo Bianconi static void 23078dc9a088SLorenzo Bianconi mvneta_swbm_rx_frame(struct mvneta_port *pp, 23088dc9a088SLorenzo Bianconi struct mvneta_rx_desc *rx_desc, 23098dc9a088SLorenzo Bianconi struct mvneta_rx_queue *rxq, 2310c7a3a8cdSLorenzo Bianconi struct xdp_buff *xdp, int *size, 23113a8c4ad1SLorenzo Bianconi struct page *page) 23128dc9a088SLorenzo Bianconi { 23138dc9a088SLorenzo Bianconi unsigned char *data = page_address(page); 23148dc9a088SLorenzo Bianconi int data_len = -MVNETA_MH_SIZE, len; 23158dc9a088SLorenzo Bianconi struct net_device *dev = pp->dev; 23168dc9a088SLorenzo Bianconi enum dma_data_direction dma_dir; 23178dc9a088SLorenzo Bianconi 2318879456beSLorenzo Bianconi if (*size > MVNETA_MAX_RX_BUF_SIZE) { 23198dc9a088SLorenzo Bianconi len = MVNETA_MAX_RX_BUF_SIZE; 23208dc9a088SLorenzo Bianconi data_len += len; 23218dc9a088SLorenzo Bianconi } else { 2322879456beSLorenzo Bianconi len = *size; 23238dc9a088SLorenzo Bianconi data_len += len - ETH_FCS_LEN; 23248dc9a088SLorenzo Bianconi } 2325879456beSLorenzo Bianconi *size = *size - len; 23268dc9a088SLorenzo Bianconi 23278dc9a088SLorenzo Bianconi dma_dir = page_pool_get_dma_dir(rxq->page_pool); 23288dc9a088SLorenzo Bianconi dma_sync_single_for_cpu(dev->dev.parent, 23298dc9a088SLorenzo Bianconi rx_desc->buf_phys_addr, 23308dc9a088SLorenzo Bianconi len, dma_dir); 23318dc9a088SLorenzo Bianconi 2332879456beSLorenzo Bianconi rx_desc->buf_phys_addr = 0; 2333879456beSLorenzo Bianconi 2334fa383f6bSLorenzo Bianconi /* Prefetch header */ 2335fa383f6bSLorenzo Bianconi prefetch(data); 233676a67694SLorenzo Bianconi xdp_buff_clear_frags_flag(xdp); 2337be9df4afSLorenzo Bianconi xdp_prepare_buff(xdp, data, pp->rx_offset_correction + MVNETA_MH_SIZE, 2338be9df4afSLorenzo Bianconi data_len, false); 23398dc9a088SLorenzo Bianconi } 23408dc9a088SLorenzo Bianconi 23418dc9a088SLorenzo Bianconi static void 23428dc9a088SLorenzo Bianconi mvneta_swbm_add_rx_fragment(struct mvneta_port *pp, 23438dc9a088SLorenzo Bianconi struct mvneta_rx_desc *rx_desc, 23448dc9a088SLorenzo Bianconi struct mvneta_rx_queue *rxq, 2345c7a3a8cdSLorenzo Bianconi struct xdp_buff *xdp, int *size, 23468dc9a088SLorenzo Bianconi struct page *page) 23478dc9a088SLorenzo Bianconi { 2348d094c985SLorenzo Bianconi struct skb_shared_info *sinfo = xdp_get_shared_info_from_buff(xdp); 23498dc9a088SLorenzo Bianconi struct net_device *dev = pp->dev; 23508dc9a088SLorenzo Bianconi enum dma_data_direction dma_dir; 23518dc9a088SLorenzo Bianconi int data_len, len; 23528dc9a088SLorenzo Bianconi 2353c7a3a8cdSLorenzo Bianconi if (*size > MVNETA_MAX_RX_BUF_SIZE) { 23548dc9a088SLorenzo Bianconi len = MVNETA_MAX_RX_BUF_SIZE; 23558dc9a088SLorenzo Bianconi data_len = len; 23568dc9a088SLorenzo Bianconi } else { 2357c7a3a8cdSLorenzo Bianconi len = *size; 23588dc9a088SLorenzo Bianconi data_len = len - ETH_FCS_LEN; 23598dc9a088SLorenzo Bianconi } 23608dc9a088SLorenzo Bianconi dma_dir = page_pool_get_dma_dir(rxq->page_pool); 23618dc9a088SLorenzo Bianconi dma_sync_single_for_cpu(dev->dev.parent, 23628dc9a088SLorenzo Bianconi rx_desc->buf_phys_addr, 23638dc9a088SLorenzo Bianconi len, dma_dir); 23649c79a8abSLorenzo Bianconi rx_desc->buf_phys_addr = 0; 2365ca0e0146SLorenzo Bianconi 2366d094c985SLorenzo Bianconi if (!xdp_buff_has_frags(xdp)) 2367d094c985SLorenzo Bianconi sinfo->nr_frags = 0; 2368d094c985SLorenzo Bianconi 2369d094c985SLorenzo Bianconi if (data_len > 0 && sinfo->nr_frags < MAX_SKB_FRAGS) { 2370d094c985SLorenzo Bianconi skb_frag_t *frag = &sinfo->frags[sinfo->nr_frags++]; 2371ca0e0146SLorenzo Bianconi 2372ca0e0146SLorenzo Bianconi skb_frag_off_set(frag, pp->rx_offset_correction); 2373ca0e0146SLorenzo Bianconi skb_frag_size_set(frag, data_len); 2374ca0e0146SLorenzo Bianconi __skb_frag_set_page(frag, page); 237576a67694SLorenzo Bianconi 2376ed7a58cbSLorenzo Bianconi if (!xdp_buff_has_frags(xdp)) { 2377ed7a58cbSLorenzo Bianconi sinfo->xdp_frags_size = *size; 237876a67694SLorenzo Bianconi xdp_buff_set_frags_flag(xdp); 2379ed7a58cbSLorenzo Bianconi } 2380ed7a58cbSLorenzo Bianconi if (page_is_pfmemalloc(page)) 2381ed7a58cbSLorenzo Bianconi xdp_buff_set_frag_pfmemalloc(xdp); 23826ff63a15SLorenzo Bianconi } else { 23836ff63a15SLorenzo Bianconi page_pool_put_full_page(rxq->page_pool, page, true); 23846ff63a15SLorenzo Bianconi } 2385c7a3a8cdSLorenzo Bianconi *size -= len; 23868dc9a088SLorenzo Bianconi } 23878dc9a088SLorenzo Bianconi 2388ca0e0146SLorenzo Bianconi static struct sk_buff * 2389e4017570SMatteo Croce mvneta_swbm_build_skb(struct mvneta_port *pp, struct page_pool *pool, 2390ca0e0146SLorenzo Bianconi struct xdp_buff *xdp, u32 desc_status) 2391ca0e0146SLorenzo Bianconi { 2392ca0e0146SLorenzo Bianconi struct skb_shared_info *sinfo = xdp_get_shared_info_from_buff(xdp); 2393ca0e0146SLorenzo Bianconi struct sk_buff *skb; 239476a67694SLorenzo Bianconi u8 num_frags; 239576a67694SLorenzo Bianconi 239676a67694SLorenzo Bianconi if (unlikely(xdp_buff_has_frags(xdp))) 239776a67694SLorenzo Bianconi num_frags = sinfo->nr_frags; 2398ca0e0146SLorenzo Bianconi 2399ca0e0146SLorenzo Bianconi skb = build_skb(xdp->data_hard_start, PAGE_SIZE); 2400ca0e0146SLorenzo Bianconi if (!skb) 2401ca0e0146SLorenzo Bianconi return ERR_PTR(-ENOMEM); 2402ca0e0146SLorenzo Bianconi 240357f05bc2SYunsheng Lin skb_mark_for_recycle(skb); 2404ca0e0146SLorenzo Bianconi 2405ca0e0146SLorenzo Bianconi skb_reserve(skb, xdp->data - xdp->data_hard_start); 2406ca0e0146SLorenzo Bianconi skb_put(skb, xdp->data_end - xdp->data); 2407aff0824dSLorenzo Bianconi skb->ip_summed = mvneta_rx_csum(pp, desc_status); 2408ca0e0146SLorenzo Bianconi 2409ed7a58cbSLorenzo Bianconi if (unlikely(xdp_buff_has_frags(xdp))) 2410ed7a58cbSLorenzo Bianconi xdp_update_skb_shared_info(skb, num_frags, 2411ed7a58cbSLorenzo Bianconi sinfo->xdp_frags_size, 2412ed7a58cbSLorenzo Bianconi num_frags * xdp->frame_sz, 2413ed7a58cbSLorenzo Bianconi xdp_buff_is_frag_pfmemalloc(xdp)); 241476a67694SLorenzo Bianconi 2415ca0e0146SLorenzo Bianconi return skb; 2416ca0e0146SLorenzo Bianconi } 2417ca0e0146SLorenzo Bianconi 2418dc35a10fSMarcin Wojtas /* Main rx processing when using software buffer management */ 24197a86f05fSAndrew Lunn static int mvneta_rx_swbm(struct napi_struct *napi, 2420562e2f46SYelena Krivosheev struct mvneta_port *pp, int budget, 2421c5aff182SThomas Petazzoni struct mvneta_rx_queue *rxq) 2422c5aff182SThomas Petazzoni { 2423c7a3a8cdSLorenzo Bianconi int rx_proc = 0, rx_todo, refill, size = 0; 2424c5aff182SThomas Petazzoni struct net_device *dev = pp->dev; 2425320d5441SLorenzo Bianconi struct mvneta_stats ps = {}; 24260db51da7SLorenzo Bianconi struct bpf_prog *xdp_prog; 24277d1643ebSLorenzo Bianconi u32 desc_status, frame_sz; 242805c748f7SLorenzo Bianconi struct xdp_buff xdp_buf; 242905c748f7SLorenzo Bianconi 243043b5169dSLorenzo Bianconi xdp_init_buff(&xdp_buf, PAGE_SIZE, &rxq->xdp_rxq); 243105c748f7SLorenzo Bianconi xdp_buf.data_hard_start = NULL; 2432c5aff182SThomas Petazzoni 2433c5aff182SThomas Petazzoni /* Get number of received packets */ 2434562e2f46SYelena Krivosheev rx_todo = mvneta_rxq_busy_desc_num_get(pp, rxq); 2435c5aff182SThomas Petazzoni 24360db51da7SLorenzo Bianconi xdp_prog = READ_ONCE(pp->xdp_prog); 24370db51da7SLorenzo Bianconi 2438c5aff182SThomas Petazzoni /* Fairness NAPI loop */ 24398dc9a088SLorenzo Bianconi while (rx_proc < budget && rx_proc < rx_todo) { 2440c5aff182SThomas Petazzoni struct mvneta_rx_desc *rx_desc = mvneta_rxq_next_desc_get(rxq); 24418dc9a088SLorenzo Bianconi u32 rx_status, index; 2442ca0e0146SLorenzo Bianconi struct sk_buff *skb; 24437e47fd84SGregory CLEMENT struct page *page; 2444c5aff182SThomas Petazzoni 2445f88bee1cSGregory CLEMENT index = rx_desc - rxq->descs; 24467e47fd84SGregory CLEMENT page = (struct page *)rxq->buf_virt_addr[index]; 2447c5aff182SThomas Petazzoni 2448562e2f46SYelena Krivosheev rx_status = rx_desc->status; 2449562e2f46SYelena Krivosheev rx_proc++; 2450562e2f46SYelena Krivosheev rxq->refill_num++; 2451562e2f46SYelena Krivosheev 2452562e2f46SYelena Krivosheev if (rx_status & MVNETA_RXD_FIRST_DESC) { 2453562e2f46SYelena Krivosheev /* Check errors only for FIRST descriptor */ 2454562e2f46SYelena Krivosheev if (rx_status & MVNETA_RXD_ERR_SUMMARY) { 24552eecb2e0SYelena Krivosheev mvneta_rx_error(pp, rx_desc); 2456ca0e0146SLorenzo Bianconi goto next; 2457c5aff182SThomas Petazzoni } 2458c5aff182SThomas Petazzoni 2459c7a3a8cdSLorenzo Bianconi size = rx_desc->data_size; 2460c7a3a8cdSLorenzo Bianconi frame_sz = size - ETH_FCS_LEN; 2461879456beSLorenzo Bianconi desc_status = rx_status; 24627d1643ebSLorenzo Bianconi 2463c7a3a8cdSLorenzo Bianconi mvneta_swbm_rx_frame(pp, rx_desc, rxq, &xdp_buf, 24643a8c4ad1SLorenzo Bianconi &size, page); 2465562e2f46SYelena Krivosheev } else { 2466b6e11785SLorenzo Bianconi if (unlikely(!xdp_buf.data_hard_start)) { 2467b6e11785SLorenzo Bianconi rx_desc->buf_phys_addr = 0; 2468b6e11785SLorenzo Bianconi page_pool_put_full_page(rxq->page_pool, page, 2469b6e11785SLorenzo Bianconi true); 2470039fbc47SLorenzo Bianconi goto next; 2471b6e11785SLorenzo Bianconi } 2472ca0e0146SLorenzo Bianconi 2473ca0e0146SLorenzo Bianconi mvneta_swbm_add_rx_fragment(pp, rx_desc, rxq, &xdp_buf, 2474d094c985SLorenzo Bianconi &size, page); 2475562e2f46SYelena Krivosheev } /* Middle or Last descriptor */ 2476562e2f46SYelena Krivosheev 2477562e2f46SYelena Krivosheev if (!(rx_status & MVNETA_RXD_LAST_DESC)) 2478562e2f46SYelena Krivosheev /* no last descriptor this time */ 2479562e2f46SYelena Krivosheev continue; 2480562e2f46SYelena Krivosheev 2481c7a3a8cdSLorenzo Bianconi if (size) { 2482d094c985SLorenzo Bianconi mvneta_xdp_put_buff(pp, rxq, &xdp_buf, -1); 2483ca0e0146SLorenzo Bianconi goto next; 2484562e2f46SYelena Krivosheev } 2485320d5441SLorenzo Bianconi 2486afda408bSLorenzo Bianconi if (xdp_prog && 24877d1643ebSLorenzo Bianconi mvneta_run_xdp(pp, rxq, xdp_prog, &xdp_buf, frame_sz, &ps)) 2488afda408bSLorenzo Bianconi goto next; 2489afda408bSLorenzo Bianconi 2490e4017570SMatteo Croce skb = mvneta_swbm_build_skb(pp, rxq->page_pool, &xdp_buf, desc_status); 2491ca0e0146SLorenzo Bianconi if (IS_ERR(skb)) { 2492ca0e0146SLorenzo Bianconi struct mvneta_pcpu_stats *stats = this_cpu_ptr(pp->stats); 2493ca0e0146SLorenzo Bianconi 2494d094c985SLorenzo Bianconi mvneta_xdp_put_buff(pp, rxq, &xdp_buf, -1); 2495ca0e0146SLorenzo Bianconi 2496ca0e0146SLorenzo Bianconi u64_stats_update_begin(&stats->syncp); 2497ca0e0146SLorenzo Bianconi stats->es.skb_alloc_error++; 2498ca0e0146SLorenzo Bianconi stats->rx_dropped++; 2499ca0e0146SLorenzo Bianconi u64_stats_update_end(&stats->syncp); 2500ca0e0146SLorenzo Bianconi 2501ca0e0146SLorenzo Bianconi goto next; 2502ca0e0146SLorenzo Bianconi } 2503ca0e0146SLorenzo Bianconi 2504ca0e0146SLorenzo Bianconi ps.rx_bytes += skb->len; 2505320d5441SLorenzo Bianconi ps.rx_packets++; 2506c5aff182SThomas Petazzoni 2507ca0e0146SLorenzo Bianconi skb->protocol = eth_type_trans(skb, dev); 2508ca0e0146SLorenzo Bianconi napi_gro_receive(napi, skb); 2509ca0e0146SLorenzo Bianconi next: 2510ca0e0146SLorenzo Bianconi xdp_buf.data_hard_start = NULL; 2511c5aff182SThomas Petazzoni } 25120db51da7SLorenzo Bianconi 2513039fbc47SLorenzo Bianconi if (xdp_buf.data_hard_start) 2514d094c985SLorenzo Bianconi mvneta_xdp_put_buff(pp, rxq, &xdp_buf, -1); 2515ca0e0146SLorenzo Bianconi 25166c8a8cfdSLorenzo Bianconi if (ps.xdp_redirect) 25170db51da7SLorenzo Bianconi xdp_do_flush_map(); 2518c5aff182SThomas Petazzoni 2519320d5441SLorenzo Bianconi if (ps.rx_packets) 2520320d5441SLorenzo Bianconi mvneta_update_stats(pp, &ps); 2521dc4277ddSwilly tarreau 2522562e2f46SYelena Krivosheev /* return some buffers to hardware queue, one at a time is too slow */ 2523562e2f46SYelena Krivosheev refill = mvneta_rx_refill_queue(pp, rxq); 2524c5aff182SThomas Petazzoni 2525562e2f46SYelena Krivosheev /* Update rxq management counters */ 2526562e2f46SYelena Krivosheev mvneta_rxq_desc_num_update(pp, rxq, rx_proc, refill); 2527562e2f46SYelena Krivosheev 2528320d5441SLorenzo Bianconi return ps.rx_packets; 2529c5aff182SThomas Petazzoni } 2530c5aff182SThomas Petazzoni 2531dc35a10fSMarcin Wojtas /* Main rx processing when using hardware buffer management */ 25327a86f05fSAndrew Lunn static int mvneta_rx_hwbm(struct napi_struct *napi, 25337a86f05fSAndrew Lunn struct mvneta_port *pp, int rx_todo, 2534dc35a10fSMarcin Wojtas struct mvneta_rx_queue *rxq) 2535dc35a10fSMarcin Wojtas { 2536dc35a10fSMarcin Wojtas struct net_device *dev = pp->dev; 2537dc35a10fSMarcin Wojtas int rx_done; 2538dc35a10fSMarcin Wojtas u32 rcvd_pkts = 0; 2539dc35a10fSMarcin Wojtas u32 rcvd_bytes = 0; 2540dc35a10fSMarcin Wojtas 2541dc35a10fSMarcin Wojtas /* Get number of received packets */ 2542dc35a10fSMarcin Wojtas rx_done = mvneta_rxq_busy_desc_num_get(pp, rxq); 2543dc35a10fSMarcin Wojtas 2544dc35a10fSMarcin Wojtas if (rx_todo > rx_done) 2545dc35a10fSMarcin Wojtas rx_todo = rx_done; 2546dc35a10fSMarcin Wojtas 2547dc35a10fSMarcin Wojtas rx_done = 0; 2548dc35a10fSMarcin Wojtas 2549dc35a10fSMarcin Wojtas /* Fairness NAPI loop */ 2550dc35a10fSMarcin Wojtas while (rx_done < rx_todo) { 2551dc35a10fSMarcin Wojtas struct mvneta_rx_desc *rx_desc = mvneta_rxq_next_desc_get(rxq); 2552dc35a10fSMarcin Wojtas struct mvneta_bm_pool *bm_pool = NULL; 2553dc35a10fSMarcin Wojtas struct sk_buff *skb; 2554dc35a10fSMarcin Wojtas unsigned char *data; 2555dc35a10fSMarcin Wojtas dma_addr_t phys_addr; 2556dc35a10fSMarcin Wojtas u32 rx_status, frag_size; 2557dc35a10fSMarcin Wojtas int rx_bytes, err; 2558dc35a10fSMarcin Wojtas u8 pool_id; 2559dc35a10fSMarcin Wojtas 2560dc35a10fSMarcin Wojtas rx_done++; 2561dc35a10fSMarcin Wojtas rx_status = rx_desc->status; 2562dc35a10fSMarcin Wojtas rx_bytes = rx_desc->data_size - (ETH_FCS_LEN + MVNETA_MH_SIZE); 2563f88bee1cSGregory CLEMENT data = (u8 *)(uintptr_t)rx_desc->buf_cookie; 2564dc35a10fSMarcin Wojtas phys_addr = rx_desc->buf_phys_addr; 2565dc35a10fSMarcin Wojtas pool_id = MVNETA_RX_GET_BM_POOL_ID(rx_desc); 2566dc35a10fSMarcin Wojtas bm_pool = &pp->bm_priv->bm_pools[pool_id]; 2567dc35a10fSMarcin Wojtas 2568dc35a10fSMarcin Wojtas if (!mvneta_rxq_desc_is_first_last(rx_status) || 2569dc35a10fSMarcin Wojtas (rx_status & MVNETA_RXD_ERR_SUMMARY)) { 2570dc35a10fSMarcin Wojtas err_drop_frame_ret_pool: 2571dc35a10fSMarcin Wojtas /* Return the buffer to the pool */ 2572dc35a10fSMarcin Wojtas mvneta_bm_pool_put_bp(pp->bm_priv, bm_pool, 2573dc35a10fSMarcin Wojtas rx_desc->buf_phys_addr); 2574dc35a10fSMarcin Wojtas err_drop_frame: 2575dc35a10fSMarcin Wojtas mvneta_rx_error(pp, rx_desc); 2576dc35a10fSMarcin Wojtas /* leave the descriptor untouched */ 2577dc35a10fSMarcin Wojtas continue; 2578dc35a10fSMarcin Wojtas } 2579dc35a10fSMarcin Wojtas 2580dc35a10fSMarcin Wojtas if (rx_bytes <= rx_copybreak) { 2581dc35a10fSMarcin Wojtas /* better copy a small frame and not unmap the DMA region */ 2582dc35a10fSMarcin Wojtas skb = netdev_alloc_skb_ip_align(dev, rx_bytes); 2583dc35a10fSMarcin Wojtas if (unlikely(!skb)) 2584dc35a10fSMarcin Wojtas goto err_drop_frame_ret_pool; 2585dc35a10fSMarcin Wojtas 2586a8fef9baSRussell King dma_sync_single_range_for_cpu(&pp->bm_priv->pdev->dev, 2587dc35a10fSMarcin Wojtas rx_desc->buf_phys_addr, 2588dc35a10fSMarcin Wojtas MVNETA_MH_SIZE + NET_SKB_PAD, 2589dc35a10fSMarcin Wojtas rx_bytes, 2590dc35a10fSMarcin Wojtas DMA_FROM_DEVICE); 259159ae1d12SJohannes Berg skb_put_data(skb, data + MVNETA_MH_SIZE + NET_SKB_PAD, 2592dc35a10fSMarcin Wojtas rx_bytes); 2593dc35a10fSMarcin Wojtas 2594dc35a10fSMarcin Wojtas skb->protocol = eth_type_trans(skb, dev); 2595aff0824dSLorenzo Bianconi skb->ip_summed = mvneta_rx_csum(pp, rx_status); 25967a86f05fSAndrew Lunn napi_gro_receive(napi, skb); 2597dc35a10fSMarcin Wojtas 2598dc35a10fSMarcin Wojtas rcvd_pkts++; 2599dc35a10fSMarcin Wojtas rcvd_bytes += rx_bytes; 2600dc35a10fSMarcin Wojtas 2601dc35a10fSMarcin Wojtas /* Return the buffer to the pool */ 2602dc35a10fSMarcin Wojtas mvneta_bm_pool_put_bp(pp->bm_priv, bm_pool, 2603dc35a10fSMarcin Wojtas rx_desc->buf_phys_addr); 2604dc35a10fSMarcin Wojtas 2605dc35a10fSMarcin Wojtas /* leave the descriptor and buffer untouched */ 2606dc35a10fSMarcin Wojtas continue; 2607dc35a10fSMarcin Wojtas } 2608dc35a10fSMarcin Wojtas 2609dc35a10fSMarcin Wojtas /* Refill processing */ 2610baa11ebcSGregory CLEMENT err = hwbm_pool_refill(&bm_pool->hwbm_pool, GFP_ATOMIC); 2611dc35a10fSMarcin Wojtas if (err) { 26129ac41f3cSLorenzo Bianconi struct mvneta_pcpu_stats *stats; 26139ac41f3cSLorenzo Bianconi 2614dc35a10fSMarcin Wojtas netdev_err(dev, "Linux processing - Can't refill\n"); 26159ac41f3cSLorenzo Bianconi 26169ac41f3cSLorenzo Bianconi stats = this_cpu_ptr(pp->stats); 26179ac41f3cSLorenzo Bianconi u64_stats_update_begin(&stats->syncp); 26189ac41f3cSLorenzo Bianconi stats->es.refill_error++; 26199ac41f3cSLorenzo Bianconi u64_stats_update_end(&stats->syncp); 26209ac41f3cSLorenzo Bianconi 2621dc35a10fSMarcin Wojtas goto err_drop_frame_ret_pool; 2622dc35a10fSMarcin Wojtas } 2623dc35a10fSMarcin Wojtas 2624baa11ebcSGregory CLEMENT frag_size = bm_pool->hwbm_pool.frag_size; 2625dc35a10fSMarcin Wojtas 2626dc35a10fSMarcin Wojtas skb = build_skb(data, frag_size > PAGE_SIZE ? 0 : frag_size); 2627dc35a10fSMarcin Wojtas 2628dc35a10fSMarcin Wojtas /* After refill old buffer has to be unmapped regardless 2629dc35a10fSMarcin Wojtas * the skb is successfully built or not. 2630dc35a10fSMarcin Wojtas */ 2631dc35a10fSMarcin Wojtas dma_unmap_single(&pp->bm_priv->pdev->dev, phys_addr, 2632dc35a10fSMarcin Wojtas bm_pool->buf_size, DMA_FROM_DEVICE); 2633dc35a10fSMarcin Wojtas if (!skb) 2634dc35a10fSMarcin Wojtas goto err_drop_frame; 2635dc35a10fSMarcin Wojtas 2636dc35a10fSMarcin Wojtas rcvd_pkts++; 2637dc35a10fSMarcin Wojtas rcvd_bytes += rx_bytes; 2638dc35a10fSMarcin Wojtas 2639dc35a10fSMarcin Wojtas /* Linux processing */ 2640dc35a10fSMarcin Wojtas skb_reserve(skb, MVNETA_MH_SIZE + NET_SKB_PAD); 2641dc35a10fSMarcin Wojtas skb_put(skb, rx_bytes); 2642dc35a10fSMarcin Wojtas 2643dc35a10fSMarcin Wojtas skb->protocol = eth_type_trans(skb, dev); 2644aff0824dSLorenzo Bianconi skb->ip_summed = mvneta_rx_csum(pp, rx_status); 2645dc35a10fSMarcin Wojtas 26467a86f05fSAndrew Lunn napi_gro_receive(napi, skb); 2647dc35a10fSMarcin Wojtas } 2648dc35a10fSMarcin Wojtas 264969de66fcSLorenzo Bianconi if (rcvd_pkts) { 265069de66fcSLorenzo Bianconi struct mvneta_pcpu_stats *stats = this_cpu_ptr(pp->stats); 265169de66fcSLorenzo Bianconi 265269de66fcSLorenzo Bianconi u64_stats_update_begin(&stats->syncp); 2653320d5441SLorenzo Bianconi stats->es.ps.rx_packets += rcvd_pkts; 2654320d5441SLorenzo Bianconi stats->es.ps.rx_bytes += rcvd_bytes; 265569de66fcSLorenzo Bianconi u64_stats_update_end(&stats->syncp); 265669de66fcSLorenzo Bianconi } 2657dc35a10fSMarcin Wojtas 2658dc35a10fSMarcin Wojtas /* Update rxq management counters */ 2659dc35a10fSMarcin Wojtas mvneta_rxq_desc_num_update(pp, rxq, rx_done, rx_done); 2660dc35a10fSMarcin Wojtas 2661dc35a10fSMarcin Wojtas return rx_done; 2662dc35a10fSMarcin Wojtas } 2663dc35a10fSMarcin Wojtas 26642adb719dSEzequiel Garcia static inline void 266520d446f2SYuval Shaia mvneta_tso_put_hdr(struct sk_buff *skb, struct mvneta_tx_queue *txq) 26662adb719dSEzequiel Garcia { 26679e58c8b4SLorenzo Bianconi struct mvneta_tx_buf *buf = &txq->buf[txq->txq_put_index]; 2668504148feSEric Dumazet int hdr_len = skb_tcp_all_headers(skb); 26699e58c8b4SLorenzo Bianconi struct mvneta_tx_desc *tx_desc; 26702adb719dSEzequiel Garcia 26712adb719dSEzequiel Garcia tx_desc = mvneta_txq_next_desc_get(txq); 26722adb719dSEzequiel Garcia tx_desc->data_size = hdr_len; 267320d446f2SYuval Shaia tx_desc->command = mvneta_skb_tx_csum(skb); 26742adb719dSEzequiel Garcia tx_desc->command |= MVNETA_TXD_F_DESC; 26752adb719dSEzequiel Garcia tx_desc->buf_phys_addr = txq->tso_hdrs_phys + 26762adb719dSEzequiel Garcia txq->txq_put_index * TSO_HEADER_SIZE; 26779e58c8b4SLorenzo Bianconi buf->type = MVNETA_TYPE_SKB; 26789e58c8b4SLorenzo Bianconi buf->skb = NULL; 26799e58c8b4SLorenzo Bianconi 26802adb719dSEzequiel Garcia mvneta_txq_inc_put(txq); 26812adb719dSEzequiel Garcia } 26822adb719dSEzequiel Garcia 26832adb719dSEzequiel Garcia static inline int 26842adb719dSEzequiel Garcia mvneta_tso_put_data(struct net_device *dev, struct mvneta_tx_queue *txq, 26852adb719dSEzequiel Garcia struct sk_buff *skb, char *data, int size, 26862adb719dSEzequiel Garcia bool last_tcp, bool is_last) 26872adb719dSEzequiel Garcia { 26889e58c8b4SLorenzo Bianconi struct mvneta_tx_buf *buf = &txq->buf[txq->txq_put_index]; 26892adb719dSEzequiel Garcia struct mvneta_tx_desc *tx_desc; 26902adb719dSEzequiel Garcia 26912adb719dSEzequiel Garcia tx_desc = mvneta_txq_next_desc_get(txq); 26922adb719dSEzequiel Garcia tx_desc->data_size = size; 26932adb719dSEzequiel Garcia tx_desc->buf_phys_addr = dma_map_single(dev->dev.parent, data, 26942adb719dSEzequiel Garcia size, DMA_TO_DEVICE); 26952adb719dSEzequiel Garcia if (unlikely(dma_mapping_error(dev->dev.parent, 26962adb719dSEzequiel Garcia tx_desc->buf_phys_addr))) { 26972adb719dSEzequiel Garcia mvneta_txq_desc_put(txq); 26982adb719dSEzequiel Garcia return -ENOMEM; 26992adb719dSEzequiel Garcia } 27002adb719dSEzequiel Garcia 27012adb719dSEzequiel Garcia tx_desc->command = 0; 27029e58c8b4SLorenzo Bianconi buf->type = MVNETA_TYPE_SKB; 27039e58c8b4SLorenzo Bianconi buf->skb = NULL; 27042adb719dSEzequiel Garcia 27052adb719dSEzequiel Garcia if (last_tcp) { 27062adb719dSEzequiel Garcia /* last descriptor in the TCP packet */ 27072adb719dSEzequiel Garcia tx_desc->command = MVNETA_TXD_L_DESC; 27082adb719dSEzequiel Garcia 27092adb719dSEzequiel Garcia /* last descriptor in SKB */ 27102adb719dSEzequiel Garcia if (is_last) 27119e58c8b4SLorenzo Bianconi buf->skb = skb; 27122adb719dSEzequiel Garcia } 27132adb719dSEzequiel Garcia mvneta_txq_inc_put(txq); 27142adb719dSEzequiel Garcia return 0; 27152adb719dSEzequiel Garcia } 27162adb719dSEzequiel Garcia 27172adb719dSEzequiel Garcia static int mvneta_tx_tso(struct sk_buff *skb, struct net_device *dev, 27182adb719dSEzequiel Garcia struct mvneta_tx_queue *txq) 27192adb719dSEzequiel Garcia { 2720761b331cSEric Dumazet int hdr_len, total_len, data_left; 27212adb719dSEzequiel Garcia int desc_count = 0; 27222adb719dSEzequiel Garcia struct mvneta_port *pp = netdev_priv(dev); 27232adb719dSEzequiel Garcia struct tso_t tso; 27242adb719dSEzequiel Garcia int i; 27252adb719dSEzequiel Garcia 27262adb719dSEzequiel Garcia /* Count needed descriptors */ 27272adb719dSEzequiel Garcia if ((txq->count + tso_count_descs(skb)) >= txq->size) 27282adb719dSEzequiel Garcia return 0; 27292adb719dSEzequiel Garcia 2730504148feSEric Dumazet if (skb_headlen(skb) < skb_tcp_all_headers(skb)) { 2731fa660684SColin Ian King pr_info("*** Is this even possible?\n"); 27322adb719dSEzequiel Garcia return 0; 27332adb719dSEzequiel Garcia } 27342adb719dSEzequiel Garcia 27352adb719dSEzequiel Garcia /* Initialize the TSO handler, and prepare the first payload */ 2736761b331cSEric Dumazet hdr_len = tso_start(skb, &tso); 27372adb719dSEzequiel Garcia 27382adb719dSEzequiel Garcia total_len = skb->len - hdr_len; 27392adb719dSEzequiel Garcia while (total_len > 0) { 27402adb719dSEzequiel Garcia char *hdr; 27412adb719dSEzequiel Garcia 27422adb719dSEzequiel Garcia data_left = min_t(int, skb_shinfo(skb)->gso_size, total_len); 27432adb719dSEzequiel Garcia total_len -= data_left; 27442adb719dSEzequiel Garcia desc_count++; 27452adb719dSEzequiel Garcia 27462adb719dSEzequiel Garcia /* prepare packet headers: MAC + IP + TCP */ 27472adb719dSEzequiel Garcia hdr = txq->tso_hdrs + txq->txq_put_index * TSO_HEADER_SIZE; 27482adb719dSEzequiel Garcia tso_build_hdr(skb, hdr, &tso, data_left, total_len == 0); 27492adb719dSEzequiel Garcia 275020d446f2SYuval Shaia mvneta_tso_put_hdr(skb, txq); 27512adb719dSEzequiel Garcia 27522adb719dSEzequiel Garcia while (data_left > 0) { 27532adb719dSEzequiel Garcia int size; 27542adb719dSEzequiel Garcia desc_count++; 27552adb719dSEzequiel Garcia 27562adb719dSEzequiel Garcia size = min_t(int, tso.size, data_left); 27572adb719dSEzequiel Garcia 27582adb719dSEzequiel Garcia if (mvneta_tso_put_data(dev, txq, skb, 27592adb719dSEzequiel Garcia tso.data, size, 27602adb719dSEzequiel Garcia size == data_left, 27612adb719dSEzequiel Garcia total_len == 0)) 27622adb719dSEzequiel Garcia goto err_release; 27632adb719dSEzequiel Garcia data_left -= size; 27642adb719dSEzequiel Garcia 27652adb719dSEzequiel Garcia tso_build_data(skb, &tso, size); 27662adb719dSEzequiel Garcia } 27672adb719dSEzequiel Garcia } 27682adb719dSEzequiel Garcia 27692adb719dSEzequiel Garcia return desc_count; 27702adb719dSEzequiel Garcia 27712adb719dSEzequiel Garcia err_release: 27722adb719dSEzequiel Garcia /* Release all used data descriptors; header descriptors must not 27732adb719dSEzequiel Garcia * be DMA-unmapped. 27742adb719dSEzequiel Garcia */ 27752adb719dSEzequiel Garcia for (i = desc_count - 1; i >= 0; i--) { 27762adb719dSEzequiel Garcia struct mvneta_tx_desc *tx_desc = txq->descs + i; 27772e3173a3SEzequiel Garcia if (!IS_TSO_HEADER(txq, tx_desc->buf_phys_addr)) 27782adb719dSEzequiel Garcia dma_unmap_single(pp->dev->dev.parent, 27792adb719dSEzequiel Garcia tx_desc->buf_phys_addr, 27802adb719dSEzequiel Garcia tx_desc->data_size, 27812adb719dSEzequiel Garcia DMA_TO_DEVICE); 27822adb719dSEzequiel Garcia mvneta_txq_desc_put(txq); 27832adb719dSEzequiel Garcia } 27842adb719dSEzequiel Garcia return 0; 27852adb719dSEzequiel Garcia } 27862adb719dSEzequiel Garcia 2787c5aff182SThomas Petazzoni /* Handle tx fragmentation processing */ 2788c5aff182SThomas Petazzoni static int mvneta_tx_frag_process(struct mvneta_port *pp, struct sk_buff *skb, 2789c5aff182SThomas Petazzoni struct mvneta_tx_queue *txq) 2790c5aff182SThomas Petazzoni { 2791c5aff182SThomas Petazzoni struct mvneta_tx_desc *tx_desc; 27923d4ea02fSEzequiel Garcia int i, nr_frags = skb_shinfo(skb)->nr_frags; 2793c5aff182SThomas Petazzoni 27943d4ea02fSEzequiel Garcia for (i = 0; i < nr_frags; i++) { 27959e58c8b4SLorenzo Bianconi struct mvneta_tx_buf *buf = &txq->buf[txq->txq_put_index]; 2796c5aff182SThomas Petazzoni skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 2797d7840976SMatthew Wilcox (Oracle) void *addr = skb_frag_address(frag); 2798c5aff182SThomas Petazzoni 2799c5aff182SThomas Petazzoni tx_desc = mvneta_txq_next_desc_get(txq); 2800d7840976SMatthew Wilcox (Oracle) tx_desc->data_size = skb_frag_size(frag); 2801c5aff182SThomas Petazzoni 2802c5aff182SThomas Petazzoni tx_desc->buf_phys_addr = 2803c5aff182SThomas Petazzoni dma_map_single(pp->dev->dev.parent, addr, 2804c5aff182SThomas Petazzoni tx_desc->data_size, DMA_TO_DEVICE); 2805c5aff182SThomas Petazzoni 2806c5aff182SThomas Petazzoni if (dma_mapping_error(pp->dev->dev.parent, 2807c5aff182SThomas Petazzoni tx_desc->buf_phys_addr)) { 2808c5aff182SThomas Petazzoni mvneta_txq_desc_put(txq); 2809c5aff182SThomas Petazzoni goto error; 2810c5aff182SThomas Petazzoni } 2811c5aff182SThomas Petazzoni 28123d4ea02fSEzequiel Garcia if (i == nr_frags - 1) { 2813c5aff182SThomas Petazzoni /* Last descriptor */ 2814c5aff182SThomas Petazzoni tx_desc->command = MVNETA_TXD_L_DESC | MVNETA_TXD_Z_PAD; 28159e58c8b4SLorenzo Bianconi buf->skb = skb; 2816c5aff182SThomas Petazzoni } else { 2817c5aff182SThomas Petazzoni /* Descriptor in the middle: Not First, Not Last */ 2818c5aff182SThomas Petazzoni tx_desc->command = 0; 28199e58c8b4SLorenzo Bianconi buf->skb = NULL; 2820c5aff182SThomas Petazzoni } 28219e58c8b4SLorenzo Bianconi buf->type = MVNETA_TYPE_SKB; 28223d4ea02fSEzequiel Garcia mvneta_txq_inc_put(txq); 2823c5aff182SThomas Petazzoni } 2824c5aff182SThomas Petazzoni 2825c5aff182SThomas Petazzoni return 0; 2826c5aff182SThomas Petazzoni 2827c5aff182SThomas Petazzoni error: 2828c5aff182SThomas Petazzoni /* Release all descriptors that were used to map fragments of 28296a20c175SThomas Petazzoni * this packet, as well as the corresponding DMA mappings 28306a20c175SThomas Petazzoni */ 2831c5aff182SThomas Petazzoni for (i = i - 1; i >= 0; i--) { 2832c5aff182SThomas Petazzoni tx_desc = txq->descs + i; 2833c5aff182SThomas Petazzoni dma_unmap_single(pp->dev->dev.parent, 2834c5aff182SThomas Petazzoni tx_desc->buf_phys_addr, 2835c5aff182SThomas Petazzoni tx_desc->data_size, 2836c5aff182SThomas Petazzoni DMA_TO_DEVICE); 2837c5aff182SThomas Petazzoni mvneta_txq_desc_put(txq); 2838c5aff182SThomas Petazzoni } 2839c5aff182SThomas Petazzoni 2840c5aff182SThomas Petazzoni return -ENOMEM; 2841c5aff182SThomas Petazzoni } 2842c5aff182SThomas Petazzoni 2843c5aff182SThomas Petazzoni /* Main tx processing */ 2844f03508ceSYueHaibing static netdev_tx_t mvneta_tx(struct sk_buff *skb, struct net_device *dev) 2845c5aff182SThomas Petazzoni { 2846c5aff182SThomas Petazzoni struct mvneta_port *pp = netdev_priv(dev); 2847ee40a116SWilly Tarreau u16 txq_id = skb_get_queue_mapping(skb); 2848ee40a116SWilly Tarreau struct mvneta_tx_queue *txq = &pp->txqs[txq_id]; 28499e58c8b4SLorenzo Bianconi struct mvneta_tx_buf *buf = &txq->buf[txq->txq_put_index]; 2850c5aff182SThomas Petazzoni struct mvneta_tx_desc *tx_desc; 28515f478b41SEric Dumazet int len = skb->len; 2852c5aff182SThomas Petazzoni int frags = 0; 2853c5aff182SThomas Petazzoni u32 tx_cmd; 2854c5aff182SThomas Petazzoni 2855c5aff182SThomas Petazzoni if (!netif_running(dev)) 2856c5aff182SThomas Petazzoni goto out; 2857c5aff182SThomas Petazzoni 28582adb719dSEzequiel Garcia if (skb_is_gso(skb)) { 28592adb719dSEzequiel Garcia frags = mvneta_tx_tso(skb, dev, txq); 28602adb719dSEzequiel Garcia goto out; 28612adb719dSEzequiel Garcia } 28622adb719dSEzequiel Garcia 2863c5aff182SThomas Petazzoni frags = skb_shinfo(skb)->nr_frags + 1; 2864c5aff182SThomas Petazzoni 2865c5aff182SThomas Petazzoni /* Get a descriptor for the first part of the packet */ 2866c5aff182SThomas Petazzoni tx_desc = mvneta_txq_next_desc_get(txq); 2867c5aff182SThomas Petazzoni 286820d446f2SYuval Shaia tx_cmd = mvneta_skb_tx_csum(skb); 2869c5aff182SThomas Petazzoni 2870c5aff182SThomas Petazzoni tx_desc->data_size = skb_headlen(skb); 2871c5aff182SThomas Petazzoni 2872c5aff182SThomas Petazzoni tx_desc->buf_phys_addr = dma_map_single(dev->dev.parent, skb->data, 2873c5aff182SThomas Petazzoni tx_desc->data_size, 2874c5aff182SThomas Petazzoni DMA_TO_DEVICE); 2875c5aff182SThomas Petazzoni if (unlikely(dma_mapping_error(dev->dev.parent, 2876c5aff182SThomas Petazzoni tx_desc->buf_phys_addr))) { 2877c5aff182SThomas Petazzoni mvneta_txq_desc_put(txq); 2878c5aff182SThomas Petazzoni frags = 0; 2879c5aff182SThomas Petazzoni goto out; 2880c5aff182SThomas Petazzoni } 2881c5aff182SThomas Petazzoni 28829e58c8b4SLorenzo Bianconi buf->type = MVNETA_TYPE_SKB; 2883c5aff182SThomas Petazzoni if (frags == 1) { 2884c5aff182SThomas Petazzoni /* First and Last descriptor */ 2885c5aff182SThomas Petazzoni tx_cmd |= MVNETA_TXD_FLZ_DESC; 2886c5aff182SThomas Petazzoni tx_desc->command = tx_cmd; 28879e58c8b4SLorenzo Bianconi buf->skb = skb; 2888c5aff182SThomas Petazzoni mvneta_txq_inc_put(txq); 2889c5aff182SThomas Petazzoni } else { 2890c5aff182SThomas Petazzoni /* First but not Last */ 2891c5aff182SThomas Petazzoni tx_cmd |= MVNETA_TXD_F_DESC; 28929e58c8b4SLorenzo Bianconi buf->skb = NULL; 2893c5aff182SThomas Petazzoni mvneta_txq_inc_put(txq); 2894c5aff182SThomas Petazzoni tx_desc->command = tx_cmd; 2895c5aff182SThomas Petazzoni /* Continue with other skb fragments */ 2896c5aff182SThomas Petazzoni if (mvneta_tx_frag_process(pp, skb, txq)) { 2897c5aff182SThomas Petazzoni dma_unmap_single(dev->dev.parent, 2898c5aff182SThomas Petazzoni tx_desc->buf_phys_addr, 2899c5aff182SThomas Petazzoni tx_desc->data_size, 2900c5aff182SThomas Petazzoni DMA_TO_DEVICE); 2901c5aff182SThomas Petazzoni mvneta_txq_desc_put(txq); 2902c5aff182SThomas Petazzoni frags = 0; 2903c5aff182SThomas Petazzoni goto out; 2904c5aff182SThomas Petazzoni } 2905c5aff182SThomas Petazzoni } 2906c5aff182SThomas Petazzoni 2907e19d2ddaSEzequiel Garcia out: 2908e19d2ddaSEzequiel Garcia if (frags > 0) { 2909e19d2ddaSEzequiel Garcia struct netdev_queue *nq = netdev_get_tx_queue(dev, txq_id); 291069de66fcSLorenzo Bianconi struct mvneta_pcpu_stats *stats = this_cpu_ptr(pp->stats); 2911e19d2ddaSEzequiel Garcia 2912a29b6235SMarcin Wojtas netdev_tx_sent_queue(nq, len); 2913a29b6235SMarcin Wojtas 2914c5aff182SThomas Petazzoni txq->count += frags; 29158eef5f97SEzequiel Garcia if (txq->count >= txq->tx_stop_threshold) 2916c5aff182SThomas Petazzoni netif_tx_stop_queue(nq); 2917c5aff182SThomas Petazzoni 29186b16f9eeSFlorian Westphal if (!netdev_xmit_more() || netif_xmit_stopped(nq) || 29192a90f7e1SSimon Guinot txq->pending + frags > MVNETA_TXQ_DEC_SENT_MASK) 29202a90f7e1SSimon Guinot mvneta_txq_pend_desc_add(pp, txq, frags); 29212a90f7e1SSimon Guinot else 29222a90f7e1SSimon Guinot txq->pending += frags; 29232a90f7e1SSimon Guinot 292469de66fcSLorenzo Bianconi u64_stats_update_begin(&stats->syncp); 2925320d5441SLorenzo Bianconi stats->es.ps.tx_bytes += len; 2926320d5441SLorenzo Bianconi stats->es.ps.tx_packets++; 292769de66fcSLorenzo Bianconi u64_stats_update_end(&stats->syncp); 2928c5aff182SThomas Petazzoni } else { 2929c5aff182SThomas Petazzoni dev->stats.tx_dropped++; 2930c5aff182SThomas Petazzoni dev_kfree_skb_any(skb); 2931c5aff182SThomas Petazzoni } 2932c5aff182SThomas Petazzoni 2933c5aff182SThomas Petazzoni return NETDEV_TX_OK; 2934c5aff182SThomas Petazzoni } 2935c5aff182SThomas Petazzoni 2936c5aff182SThomas Petazzoni 2937c5aff182SThomas Petazzoni /* Free tx resources, when resetting a port */ 2938c5aff182SThomas Petazzoni static void mvneta_txq_done_force(struct mvneta_port *pp, 2939c5aff182SThomas Petazzoni struct mvneta_tx_queue *txq) 2940c5aff182SThomas Petazzoni 2941c5aff182SThomas Petazzoni { 2942a29b6235SMarcin Wojtas struct netdev_queue *nq = netdev_get_tx_queue(pp->dev, txq->id); 2943c5aff182SThomas Petazzoni int tx_done = txq->count; 2944c5aff182SThomas Petazzoni 2945632bb64fSLorenzo Bianconi mvneta_txq_bufs_free(pp, txq, tx_done, nq, false); 2946c5aff182SThomas Petazzoni 2947c5aff182SThomas Petazzoni /* reset txq */ 2948c5aff182SThomas Petazzoni txq->count = 0; 2949c5aff182SThomas Petazzoni txq->txq_put_index = 0; 2950c5aff182SThomas Petazzoni txq->txq_get_index = 0; 2951c5aff182SThomas Petazzoni } 2952c5aff182SThomas Petazzoni 29536c498974Swilly tarreau /* Handle tx done - called in softirq context. The <cause_tx_done> argument 29546c498974Swilly tarreau * must be a valid cause according to MVNETA_TXQ_INTR_MASK_ALL. 29556c498974Swilly tarreau */ 29560713a86aSArnaud Ebalard static void mvneta_tx_done_gbe(struct mvneta_port *pp, u32 cause_tx_done) 2957c5aff182SThomas Petazzoni { 2958c5aff182SThomas Petazzoni struct mvneta_tx_queue *txq; 2959c5aff182SThomas Petazzoni struct netdev_queue *nq; 2960bd9f1ee3SJisheng Zhang int cpu = smp_processor_id(); 2961c5aff182SThomas Petazzoni 29626c498974Swilly tarreau while (cause_tx_done) { 2963c5aff182SThomas Petazzoni txq = mvneta_tx_done_policy(pp, cause_tx_done); 2964c5aff182SThomas Petazzoni 2965c5aff182SThomas Petazzoni nq = netdev_get_tx_queue(pp->dev, txq->id); 2966bd9f1ee3SJisheng Zhang __netif_tx_lock(nq, cpu); 2967c5aff182SThomas Petazzoni 29680713a86aSArnaud Ebalard if (txq->count) 29690713a86aSArnaud Ebalard mvneta_txq_done(pp, txq); 2970c5aff182SThomas Petazzoni 2971c5aff182SThomas Petazzoni __netif_tx_unlock(nq); 2972c5aff182SThomas Petazzoni cause_tx_done &= ~((1 << txq->id)); 2973c5aff182SThomas Petazzoni } 2974c5aff182SThomas Petazzoni } 2975c5aff182SThomas Petazzoni 29766a20c175SThomas Petazzoni /* Compute crc8 of the specified address, using a unique algorithm , 2977c5aff182SThomas Petazzoni * according to hw spec, different than generic crc8 algorithm 2978c5aff182SThomas Petazzoni */ 2979c5aff182SThomas Petazzoni static int mvneta_addr_crc(unsigned char *addr) 2980c5aff182SThomas Petazzoni { 2981c5aff182SThomas Petazzoni int crc = 0; 2982c5aff182SThomas Petazzoni int i; 2983c5aff182SThomas Petazzoni 2984c5aff182SThomas Petazzoni for (i = 0; i < ETH_ALEN; i++) { 2985c5aff182SThomas Petazzoni int j; 2986c5aff182SThomas Petazzoni 2987c5aff182SThomas Petazzoni crc = (crc ^ addr[i]) << 8; 2988c5aff182SThomas Petazzoni for (j = 7; j >= 0; j--) { 2989c5aff182SThomas Petazzoni if (crc & (0x100 << j)) 2990c5aff182SThomas Petazzoni crc ^= 0x107 << j; 2991c5aff182SThomas Petazzoni } 2992c5aff182SThomas Petazzoni } 2993c5aff182SThomas Petazzoni 2994c5aff182SThomas Petazzoni return crc; 2995c5aff182SThomas Petazzoni } 2996c5aff182SThomas Petazzoni 2997c5aff182SThomas Petazzoni /* This method controls the net device special MAC multicast support. 2998c5aff182SThomas Petazzoni * The Special Multicast Table for MAC addresses supports MAC of the form 2999c5aff182SThomas Petazzoni * 0x01-00-5E-00-00-XX (where XX is between 0x00 and 0xFF). 3000c5aff182SThomas Petazzoni * The MAC DA[7:0] bits are used as a pointer to the Special Multicast 3001c5aff182SThomas Petazzoni * Table entries in the DA-Filter table. This method set the Special 3002c5aff182SThomas Petazzoni * Multicast Table appropriate entry. 3003c5aff182SThomas Petazzoni */ 3004c5aff182SThomas Petazzoni static void mvneta_set_special_mcast_addr(struct mvneta_port *pp, 3005c5aff182SThomas Petazzoni unsigned char last_byte, 3006c5aff182SThomas Petazzoni int queue) 3007c5aff182SThomas Petazzoni { 3008c5aff182SThomas Petazzoni unsigned int smc_table_reg; 3009c5aff182SThomas Petazzoni unsigned int tbl_offset; 3010c5aff182SThomas Petazzoni unsigned int reg_offset; 3011c5aff182SThomas Petazzoni 3012c5aff182SThomas Petazzoni /* Register offset from SMC table base */ 3013c5aff182SThomas Petazzoni tbl_offset = (last_byte / 4); 3014c5aff182SThomas Petazzoni /* Entry offset within the above reg */ 3015c5aff182SThomas Petazzoni reg_offset = last_byte % 4; 3016c5aff182SThomas Petazzoni 3017c5aff182SThomas Petazzoni smc_table_reg = mvreg_read(pp, (MVNETA_DA_FILT_SPEC_MCAST 3018c5aff182SThomas Petazzoni + tbl_offset * 4)); 3019c5aff182SThomas Petazzoni 3020c5aff182SThomas Petazzoni if (queue == -1) 3021c5aff182SThomas Petazzoni smc_table_reg &= ~(0xff << (8 * reg_offset)); 3022c5aff182SThomas Petazzoni else { 3023c5aff182SThomas Petazzoni smc_table_reg &= ~(0xff << (8 * reg_offset)); 3024c5aff182SThomas Petazzoni smc_table_reg |= ((0x01 | (queue << 1)) << (8 * reg_offset)); 3025c5aff182SThomas Petazzoni } 3026c5aff182SThomas Petazzoni 3027c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_DA_FILT_SPEC_MCAST + tbl_offset * 4, 3028c5aff182SThomas Petazzoni smc_table_reg); 3029c5aff182SThomas Petazzoni } 3030c5aff182SThomas Petazzoni 3031c5aff182SThomas Petazzoni /* This method controls the network device Other MAC multicast support. 3032c5aff182SThomas Petazzoni * The Other Multicast Table is used for multicast of another type. 3033c5aff182SThomas Petazzoni * A CRC-8 is used as an index to the Other Multicast Table entries 3034c5aff182SThomas Petazzoni * in the DA-Filter table. 3035c5aff182SThomas Petazzoni * The method gets the CRC-8 value from the calling routine and 3036c5aff182SThomas Petazzoni * sets the Other Multicast Table appropriate entry according to the 3037c5aff182SThomas Petazzoni * specified CRC-8 . 3038c5aff182SThomas Petazzoni */ 3039c5aff182SThomas Petazzoni static void mvneta_set_other_mcast_addr(struct mvneta_port *pp, 3040c5aff182SThomas Petazzoni unsigned char crc8, 3041c5aff182SThomas Petazzoni int queue) 3042c5aff182SThomas Petazzoni { 3043c5aff182SThomas Petazzoni unsigned int omc_table_reg; 3044c5aff182SThomas Petazzoni unsigned int tbl_offset; 3045c5aff182SThomas Petazzoni unsigned int reg_offset; 3046c5aff182SThomas Petazzoni 3047c5aff182SThomas Petazzoni tbl_offset = (crc8 / 4) * 4; /* Register offset from OMC table base */ 3048c5aff182SThomas Petazzoni reg_offset = crc8 % 4; /* Entry offset within the above reg */ 3049c5aff182SThomas Petazzoni 3050c5aff182SThomas Petazzoni omc_table_reg = mvreg_read(pp, MVNETA_DA_FILT_OTH_MCAST + tbl_offset); 3051c5aff182SThomas Petazzoni 3052c5aff182SThomas Petazzoni if (queue == -1) { 3053c5aff182SThomas Petazzoni /* Clear accepts frame bit at specified Other DA table entry */ 3054c5aff182SThomas Petazzoni omc_table_reg &= ~(0xff << (8 * reg_offset)); 3055c5aff182SThomas Petazzoni } else { 3056c5aff182SThomas Petazzoni omc_table_reg &= ~(0xff << (8 * reg_offset)); 3057c5aff182SThomas Petazzoni omc_table_reg |= ((0x01 | (queue << 1)) << (8 * reg_offset)); 3058c5aff182SThomas Petazzoni } 3059c5aff182SThomas Petazzoni 3060c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_DA_FILT_OTH_MCAST + tbl_offset, omc_table_reg); 3061c5aff182SThomas Petazzoni } 3062c5aff182SThomas Petazzoni 3063c5aff182SThomas Petazzoni /* The network device supports multicast using two tables: 3064c5aff182SThomas Petazzoni * 1) Special Multicast Table for MAC addresses of the form 3065c5aff182SThomas Petazzoni * 0x01-00-5E-00-00-XX (where XX is between 0x00 and 0xFF). 3066c5aff182SThomas Petazzoni * The MAC DA[7:0] bits are used as a pointer to the Special Multicast 3067c5aff182SThomas Petazzoni * Table entries in the DA-Filter table. 3068c5aff182SThomas Petazzoni * 2) Other Multicast Table for multicast of another type. A CRC-8 value 3069c5aff182SThomas Petazzoni * is used as an index to the Other Multicast Table entries in the 3070c5aff182SThomas Petazzoni * DA-Filter table. 3071c5aff182SThomas Petazzoni */ 3072c5aff182SThomas Petazzoni static int mvneta_mcast_addr_set(struct mvneta_port *pp, unsigned char *p_addr, 3073c5aff182SThomas Petazzoni int queue) 3074c5aff182SThomas Petazzoni { 3075c5aff182SThomas Petazzoni unsigned char crc_result = 0; 3076c5aff182SThomas Petazzoni 3077c5aff182SThomas Petazzoni if (memcmp(p_addr, "\x01\x00\x5e\x00\x00", 5) == 0) { 3078c5aff182SThomas Petazzoni mvneta_set_special_mcast_addr(pp, p_addr[5], queue); 3079c5aff182SThomas Petazzoni return 0; 3080c5aff182SThomas Petazzoni } 3081c5aff182SThomas Petazzoni 3082c5aff182SThomas Petazzoni crc_result = mvneta_addr_crc(p_addr); 3083c5aff182SThomas Petazzoni if (queue == -1) { 3084c5aff182SThomas Petazzoni if (pp->mcast_count[crc_result] == 0) { 3085c5aff182SThomas Petazzoni netdev_info(pp->dev, "No valid Mcast for crc8=0x%02x\n", 3086c5aff182SThomas Petazzoni crc_result); 3087c5aff182SThomas Petazzoni return -EINVAL; 3088c5aff182SThomas Petazzoni } 3089c5aff182SThomas Petazzoni 3090c5aff182SThomas Petazzoni pp->mcast_count[crc_result]--; 3091c5aff182SThomas Petazzoni if (pp->mcast_count[crc_result] != 0) { 3092c5aff182SThomas Petazzoni netdev_info(pp->dev, 3093c5aff182SThomas Petazzoni "After delete there are %d valid Mcast for crc8=0x%02x\n", 3094c5aff182SThomas Petazzoni pp->mcast_count[crc_result], crc_result); 3095c5aff182SThomas Petazzoni return -EINVAL; 3096c5aff182SThomas Petazzoni } 3097c5aff182SThomas Petazzoni } else 3098c5aff182SThomas Petazzoni pp->mcast_count[crc_result]++; 3099c5aff182SThomas Petazzoni 3100c5aff182SThomas Petazzoni mvneta_set_other_mcast_addr(pp, crc_result, queue); 3101c5aff182SThomas Petazzoni 3102c5aff182SThomas Petazzoni return 0; 3103c5aff182SThomas Petazzoni } 3104c5aff182SThomas Petazzoni 3105c5aff182SThomas Petazzoni /* Configure Fitering mode of Ethernet port */ 3106c5aff182SThomas Petazzoni static void mvneta_rx_unicast_promisc_set(struct mvneta_port *pp, 3107c5aff182SThomas Petazzoni int is_promisc) 3108c5aff182SThomas Petazzoni { 3109c5aff182SThomas Petazzoni u32 port_cfg_reg, val; 3110c5aff182SThomas Petazzoni 3111c5aff182SThomas Petazzoni port_cfg_reg = mvreg_read(pp, MVNETA_PORT_CONFIG); 3112c5aff182SThomas Petazzoni 3113c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_TYPE_PRIO); 3114c5aff182SThomas Petazzoni 3115c5aff182SThomas Petazzoni /* Set / Clear UPM bit in port configuration register */ 3116c5aff182SThomas Petazzoni if (is_promisc) { 3117c5aff182SThomas Petazzoni /* Accept all Unicast addresses */ 3118c5aff182SThomas Petazzoni port_cfg_reg |= MVNETA_UNI_PROMISC_MODE; 3119c5aff182SThomas Petazzoni val |= MVNETA_FORCE_UNI; 3120c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_MAC_ADDR_LOW, 0xffff); 3121c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_MAC_ADDR_HIGH, 0xffffffff); 3122c5aff182SThomas Petazzoni } else { 3123c5aff182SThomas Petazzoni /* Reject all Unicast addresses */ 3124c5aff182SThomas Petazzoni port_cfg_reg &= ~MVNETA_UNI_PROMISC_MODE; 3125c5aff182SThomas Petazzoni val &= ~MVNETA_FORCE_UNI; 3126c5aff182SThomas Petazzoni } 3127c5aff182SThomas Petazzoni 3128c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_PORT_CONFIG, port_cfg_reg); 3129c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_TYPE_PRIO, val); 3130c5aff182SThomas Petazzoni } 3131c5aff182SThomas Petazzoni 3132c5aff182SThomas Petazzoni /* register unicast and multicast addresses */ 3133c5aff182SThomas Petazzoni static void mvneta_set_rx_mode(struct net_device *dev) 3134c5aff182SThomas Petazzoni { 3135c5aff182SThomas Petazzoni struct mvneta_port *pp = netdev_priv(dev); 3136c5aff182SThomas Petazzoni struct netdev_hw_addr *ha; 3137c5aff182SThomas Petazzoni 3138c5aff182SThomas Petazzoni if (dev->flags & IFF_PROMISC) { 3139c5aff182SThomas Petazzoni /* Accept all: Multicast + Unicast */ 3140c5aff182SThomas Petazzoni mvneta_rx_unicast_promisc_set(pp, 1); 314190b74c01SGregory CLEMENT mvneta_set_ucast_table(pp, pp->rxq_def); 314290b74c01SGregory CLEMENT mvneta_set_special_mcast_table(pp, pp->rxq_def); 314390b74c01SGregory CLEMENT mvneta_set_other_mcast_table(pp, pp->rxq_def); 3144c5aff182SThomas Petazzoni } else { 3145c5aff182SThomas Petazzoni /* Accept single Unicast */ 3146c5aff182SThomas Petazzoni mvneta_rx_unicast_promisc_set(pp, 0); 3147c5aff182SThomas Petazzoni mvneta_set_ucast_table(pp, -1); 314890b74c01SGregory CLEMENT mvneta_mac_addr_set(pp, dev->dev_addr, pp->rxq_def); 3149c5aff182SThomas Petazzoni 3150c5aff182SThomas Petazzoni if (dev->flags & IFF_ALLMULTI) { 3151c5aff182SThomas Petazzoni /* Accept all multicast */ 315290b74c01SGregory CLEMENT mvneta_set_special_mcast_table(pp, pp->rxq_def); 315390b74c01SGregory CLEMENT mvneta_set_other_mcast_table(pp, pp->rxq_def); 3154c5aff182SThomas Petazzoni } else { 3155c5aff182SThomas Petazzoni /* Accept only initialized multicast */ 3156c5aff182SThomas Petazzoni mvneta_set_special_mcast_table(pp, -1); 3157c5aff182SThomas Petazzoni mvneta_set_other_mcast_table(pp, -1); 3158c5aff182SThomas Petazzoni 3159c5aff182SThomas Petazzoni if (!netdev_mc_empty(dev)) { 3160c5aff182SThomas Petazzoni netdev_for_each_mc_addr(ha, dev) { 3161c5aff182SThomas Petazzoni mvneta_mcast_addr_set(pp, ha->addr, 316290b74c01SGregory CLEMENT pp->rxq_def); 3163c5aff182SThomas Petazzoni } 3164c5aff182SThomas Petazzoni } 3165c5aff182SThomas Petazzoni } 3166c5aff182SThomas Petazzoni } 3167c5aff182SThomas Petazzoni } 3168c5aff182SThomas Petazzoni 3169c5aff182SThomas Petazzoni /* Interrupt handling - the callback for request_irq() */ 3170c5aff182SThomas Petazzoni static irqreturn_t mvneta_isr(int irq, void *dev_id) 3171c5aff182SThomas Petazzoni { 31722636ac3cSMarcin Wojtas struct mvneta_port *pp = (struct mvneta_port *)dev_id; 31732636ac3cSMarcin Wojtas 31742636ac3cSMarcin Wojtas mvreg_write(pp, MVNETA_INTR_NEW_MASK, 0); 31752636ac3cSMarcin Wojtas napi_schedule(&pp->napi); 31762636ac3cSMarcin Wojtas 31772636ac3cSMarcin Wojtas return IRQ_HANDLED; 31782636ac3cSMarcin Wojtas } 31792636ac3cSMarcin Wojtas 31802636ac3cSMarcin Wojtas /* Interrupt handling - the callback for request_percpu_irq() */ 31812636ac3cSMarcin Wojtas static irqreturn_t mvneta_percpu_isr(int irq, void *dev_id) 31822636ac3cSMarcin Wojtas { 318312bb03b4SMaxime Ripard struct mvneta_pcpu_port *port = (struct mvneta_pcpu_port *)dev_id; 3184c5aff182SThomas Petazzoni 318512bb03b4SMaxime Ripard disable_percpu_irq(port->pp->dev->irq); 318612bb03b4SMaxime Ripard napi_schedule(&port->napi); 3187c5aff182SThomas Petazzoni 3188c5aff182SThomas Petazzoni return IRQ_HANDLED; 3189c5aff182SThomas Petazzoni } 3190c5aff182SThomas Petazzoni 3191503f9aa9SRussell King static void mvneta_link_change(struct mvneta_port *pp) 3192898b2970SStas Sergeev { 3193898b2970SStas Sergeev u32 gmac_stat = mvreg_read(pp, MVNETA_GMAC_STATUS); 3194898b2970SStas Sergeev 3195503f9aa9SRussell King phylink_mac_change(pp->phylink, !!(gmac_stat & MVNETA_GMAC_LINK_UP)); 3196898b2970SStas Sergeev } 3197898b2970SStas Sergeev 3198c5aff182SThomas Petazzoni /* NAPI handler 3199c5aff182SThomas Petazzoni * Bits 0 - 7 of the causeRxTx register indicate that are transmitted 3200c5aff182SThomas Petazzoni * packets on the corresponding TXQ (Bit 0 is for TX queue 1). 3201c5aff182SThomas Petazzoni * Bits 8 -15 of the cause Rx Tx register indicate that are received 3202c5aff182SThomas Petazzoni * packets on the corresponding RXQ (Bit 8 is for RX queue 0). 3203c5aff182SThomas Petazzoni * Each CPU has its own causeRxTx register 3204c5aff182SThomas Petazzoni */ 3205c5aff182SThomas Petazzoni static int mvneta_poll(struct napi_struct *napi, int budget) 3206c5aff182SThomas Petazzoni { 3207c5aff182SThomas Petazzoni int rx_done = 0; 3208c5aff182SThomas Petazzoni u32 cause_rx_tx; 32092dcf75e2SGregory CLEMENT int rx_queue; 3210c5aff182SThomas Petazzoni struct mvneta_port *pp = netdev_priv(napi->dev); 321112bb03b4SMaxime Ripard struct mvneta_pcpu_port *port = this_cpu_ptr(pp->ports); 3212c5aff182SThomas Petazzoni 3213c5aff182SThomas Petazzoni if (!netif_running(pp->dev)) { 32142636ac3cSMarcin Wojtas napi_complete(napi); 3215c5aff182SThomas Petazzoni return rx_done; 3216c5aff182SThomas Petazzoni } 3217c5aff182SThomas Petazzoni 3218c5aff182SThomas Petazzoni /* Read cause register */ 3219898b2970SStas Sergeev cause_rx_tx = mvreg_read(pp, MVNETA_INTR_NEW_CAUSE); 3220898b2970SStas Sergeev if (cause_rx_tx & MVNETA_MISCINTR_INTR_MASK) { 3221898b2970SStas Sergeev u32 cause_misc = mvreg_read(pp, MVNETA_INTR_MISC_CAUSE); 3222898b2970SStas Sergeev 3223898b2970SStas Sergeev mvreg_write(pp, MVNETA_INTR_MISC_CAUSE, 0); 3224503f9aa9SRussell King 3225503f9aa9SRussell King if (cause_misc & (MVNETA_CAUSE_PHY_STATUS_CHANGE | 3226856b2cc5SRussell King MVNETA_CAUSE_LINK_CHANGE)) 3227503f9aa9SRussell King mvneta_link_change(pp); 3228898b2970SStas Sergeev } 322971f6d1b3Swilly tarreau 323071f6d1b3Swilly tarreau /* Release Tx descriptors */ 323171f6d1b3Swilly tarreau if (cause_rx_tx & MVNETA_TX_INTR_MASK_ALL) { 32320713a86aSArnaud Ebalard mvneta_tx_done_gbe(pp, (cause_rx_tx & MVNETA_TX_INTR_MASK_ALL)); 323371f6d1b3Swilly tarreau cause_rx_tx &= ~MVNETA_TX_INTR_MASK_ALL; 323471f6d1b3Swilly tarreau } 3235c5aff182SThomas Petazzoni 32366a20c175SThomas Petazzoni /* For the case where the last mvneta_poll did not process all 3237c5aff182SThomas Petazzoni * RX packets 3238c5aff182SThomas Petazzoni */ 32392636ac3cSMarcin Wojtas cause_rx_tx |= pp->neta_armada3700 ? pp->cause_rx_tx : 32402636ac3cSMarcin Wojtas port->cause_rx_tx; 32412dcf75e2SGregory CLEMENT 3242065fd83eSJisheng Zhang rx_queue = fls(((cause_rx_tx >> 8) & 0xff)); 32432dcf75e2SGregory CLEMENT if (rx_queue) { 32442dcf75e2SGregory CLEMENT rx_queue = rx_queue - 1; 3245dc35a10fSMarcin Wojtas if (pp->bm_priv) 32467a86f05fSAndrew Lunn rx_done = mvneta_rx_hwbm(napi, pp, budget, 32477a86f05fSAndrew Lunn &pp->rxqs[rx_queue]); 3248dc35a10fSMarcin Wojtas else 32497a86f05fSAndrew Lunn rx_done = mvneta_rx_swbm(napi, pp, budget, 32507a86f05fSAndrew Lunn &pp->rxqs[rx_queue]); 32512dcf75e2SGregory CLEMENT } 32522dcf75e2SGregory CLEMENT 32536ad20165SEric Dumazet if (rx_done < budget) { 3254c5aff182SThomas Petazzoni cause_rx_tx = 0; 32556ad20165SEric Dumazet napi_complete_done(napi, rx_done); 32562636ac3cSMarcin Wojtas 32572636ac3cSMarcin Wojtas if (pp->neta_armada3700) { 32582636ac3cSMarcin Wojtas unsigned long flags; 32592636ac3cSMarcin Wojtas 32602636ac3cSMarcin Wojtas local_irq_save(flags); 32612636ac3cSMarcin Wojtas mvreg_write(pp, MVNETA_INTR_NEW_MASK, 32622636ac3cSMarcin Wojtas MVNETA_RX_INTR_MASK(rxq_number) | 32632636ac3cSMarcin Wojtas MVNETA_TX_INTR_MASK(txq_number) | 32642636ac3cSMarcin Wojtas MVNETA_MISCINTR_INTR_MASK); 32652636ac3cSMarcin Wojtas local_irq_restore(flags); 32662636ac3cSMarcin Wojtas } else { 326712bb03b4SMaxime Ripard enable_percpu_irq(pp->dev->irq, 0); 3268c5aff182SThomas Petazzoni } 32692636ac3cSMarcin Wojtas } 3270c5aff182SThomas Petazzoni 32712636ac3cSMarcin Wojtas if (pp->neta_armada3700) 32722636ac3cSMarcin Wojtas pp->cause_rx_tx = cause_rx_tx; 32732636ac3cSMarcin Wojtas else 327412bb03b4SMaxime Ripard port->cause_rx_tx = cause_rx_tx; 32752636ac3cSMarcin Wojtas 3276c5aff182SThomas Petazzoni return rx_done; 3277c5aff182SThomas Petazzoni } 3278c5aff182SThomas Petazzoni 3279568a3fa2SLorenzo Bianconi static int mvneta_create_page_pool(struct mvneta_port *pp, 3280568a3fa2SLorenzo Bianconi struct mvneta_rx_queue *rxq, int size) 3281568a3fa2SLorenzo Bianconi { 32820db51da7SLorenzo Bianconi struct bpf_prog *xdp_prog = READ_ONCE(pp->xdp_prog); 3283568a3fa2SLorenzo Bianconi struct page_pool_params pp_params = { 3284568a3fa2SLorenzo Bianconi .order = 0, 328507e13edbSLorenzo Bianconi .flags = PP_FLAG_DMA_MAP | PP_FLAG_DMA_SYNC_DEV, 3286568a3fa2SLorenzo Bianconi .pool_size = size, 32871657adccSLorenzo Bianconi .nid = NUMA_NO_NODE, 3288568a3fa2SLorenzo Bianconi .dev = pp->dev->dev.parent, 32890db51da7SLorenzo Bianconi .dma_dir = xdp_prog ? DMA_BIDIRECTIONAL : DMA_FROM_DEVICE, 329007e13edbSLorenzo Bianconi .offset = pp->rx_offset_correction, 329107e13edbSLorenzo Bianconi .max_len = MVNETA_MAX_RX_BUF_SIZE, 3292568a3fa2SLorenzo Bianconi }; 3293568a3fa2SLorenzo Bianconi int err; 3294568a3fa2SLorenzo Bianconi 3295568a3fa2SLorenzo Bianconi rxq->page_pool = page_pool_create(&pp_params); 3296568a3fa2SLorenzo Bianconi if (IS_ERR(rxq->page_pool)) { 3297568a3fa2SLorenzo Bianconi err = PTR_ERR(rxq->page_pool); 3298568a3fa2SLorenzo Bianconi rxq->page_pool = NULL; 3299568a3fa2SLorenzo Bianconi return err; 3300568a3fa2SLorenzo Bianconi } 3301568a3fa2SLorenzo Bianconi 3302bf25146aSEelco Chaudron err = __xdp_rxq_info_reg(&rxq->xdp_rxq, pp->dev, rxq->id, 0, 3303bf25146aSEelco Chaudron PAGE_SIZE); 3304568a3fa2SLorenzo Bianconi if (err < 0) 3305568a3fa2SLorenzo Bianconi goto err_free_pp; 3306568a3fa2SLorenzo Bianconi 3307568a3fa2SLorenzo Bianconi err = xdp_rxq_info_reg_mem_model(&rxq->xdp_rxq, MEM_TYPE_PAGE_POOL, 3308568a3fa2SLorenzo Bianconi rxq->page_pool); 3309568a3fa2SLorenzo Bianconi if (err) 3310568a3fa2SLorenzo Bianconi goto err_unregister_rxq; 3311568a3fa2SLorenzo Bianconi 3312568a3fa2SLorenzo Bianconi return 0; 3313568a3fa2SLorenzo Bianconi 3314568a3fa2SLorenzo Bianconi err_unregister_rxq: 3315568a3fa2SLorenzo Bianconi xdp_rxq_info_unreg(&rxq->xdp_rxq); 3316568a3fa2SLorenzo Bianconi err_free_pp: 3317568a3fa2SLorenzo Bianconi page_pool_destroy(rxq->page_pool); 3318568a3fa2SLorenzo Bianconi rxq->page_pool = NULL; 3319568a3fa2SLorenzo Bianconi return err; 3320568a3fa2SLorenzo Bianconi } 3321568a3fa2SLorenzo Bianconi 3322c5aff182SThomas Petazzoni /* Handle rxq fill: allocates rxq skbs; called when initializing a port */ 3323c5aff182SThomas Petazzoni static int mvneta_rxq_fill(struct mvneta_port *pp, struct mvneta_rx_queue *rxq, 3324c5aff182SThomas Petazzoni int num) 3325c5aff182SThomas Petazzoni { 3326568a3fa2SLorenzo Bianconi int i, err; 3327568a3fa2SLorenzo Bianconi 3328568a3fa2SLorenzo Bianconi err = mvneta_create_page_pool(pp, rxq, num); 3329568a3fa2SLorenzo Bianconi if (err < 0) 3330568a3fa2SLorenzo Bianconi return err; 3331c5aff182SThomas Petazzoni 3332c5aff182SThomas Petazzoni for (i = 0; i < num; i++) { 3333a1a65ab1Swilly tarreau memset(rxq->descs + i, 0, sizeof(struct mvneta_rx_desc)); 33347e47fd84SGregory CLEMENT if (mvneta_rx_refill(pp, rxq->descs + i, rxq, 33357e47fd84SGregory CLEMENT GFP_KERNEL) != 0) { 33367e47fd84SGregory CLEMENT netdev_err(pp->dev, 33377e47fd84SGregory CLEMENT "%s:rxq %d, %d of %d buffs filled\n", 3338c5aff182SThomas Petazzoni __func__, rxq->id, i, num); 3339c5aff182SThomas Petazzoni break; 3340c5aff182SThomas Petazzoni } 3341c5aff182SThomas Petazzoni } 3342c5aff182SThomas Petazzoni 3343c5aff182SThomas Petazzoni /* Add this number of RX descriptors as non occupied (ready to 33446a20c175SThomas Petazzoni * get packets) 33456a20c175SThomas Petazzoni */ 3346c5aff182SThomas Petazzoni mvneta_rxq_non_occup_desc_add(pp, rxq, i); 3347c5aff182SThomas Petazzoni 3348c5aff182SThomas Petazzoni return i; 3349c5aff182SThomas Petazzoni } 3350c5aff182SThomas Petazzoni 3351c5aff182SThomas Petazzoni /* Free all packets pending transmit from all TXQs and reset TX port */ 3352c5aff182SThomas Petazzoni static void mvneta_tx_reset(struct mvneta_port *pp) 3353c5aff182SThomas Petazzoni { 3354c5aff182SThomas Petazzoni int queue; 3355c5aff182SThomas Petazzoni 33569672850bSEzequiel Garcia /* free the skb's in the tx ring */ 3357c5aff182SThomas Petazzoni for (queue = 0; queue < txq_number; queue++) 3358c5aff182SThomas Petazzoni mvneta_txq_done_force(pp, &pp->txqs[queue]); 3359c5aff182SThomas Petazzoni 3360c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_PORT_TX_RESET, MVNETA_PORT_TX_DMA_RESET); 3361c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_PORT_TX_RESET, 0); 3362c5aff182SThomas Petazzoni } 3363c5aff182SThomas Petazzoni 3364c5aff182SThomas Petazzoni static void mvneta_rx_reset(struct mvneta_port *pp) 3365c5aff182SThomas Petazzoni { 3366c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_PORT_RX_RESET, MVNETA_PORT_RX_DMA_RESET); 3367c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_PORT_RX_RESET, 0); 3368c5aff182SThomas Petazzoni } 3369c5aff182SThomas Petazzoni 3370c5aff182SThomas Petazzoni /* Rx/Tx queue initialization/cleanup methods */ 3371c5aff182SThomas Petazzoni 33724a188a63SJisheng Zhang static int mvneta_rxq_sw_init(struct mvneta_port *pp, 3373c5aff182SThomas Petazzoni struct mvneta_rx_queue *rxq) 3374c5aff182SThomas Petazzoni { 3375c5aff182SThomas Petazzoni rxq->size = pp->rx_ring_size; 3376c5aff182SThomas Petazzoni 3377c5aff182SThomas Petazzoni /* Allocate memory for RX descriptors */ 3378c5aff182SThomas Petazzoni rxq->descs = dma_alloc_coherent(pp->dev->dev.parent, 3379c5aff182SThomas Petazzoni rxq->size * MVNETA_DESC_ALIGNED_SIZE, 3380c5aff182SThomas Petazzoni &rxq->descs_phys, GFP_KERNEL); 3381f95936ccSMarkus Elfring if (!rxq->descs) 3382c5aff182SThomas Petazzoni return -ENOMEM; 3383c5aff182SThomas Petazzoni 3384c5aff182SThomas Petazzoni rxq->last_desc = rxq->size - 1; 3385c5aff182SThomas Petazzoni 33864a188a63SJisheng Zhang return 0; 33874a188a63SJisheng Zhang } 33884a188a63SJisheng Zhang 33894a188a63SJisheng Zhang static void mvneta_rxq_hw_init(struct mvneta_port *pp, 33904a188a63SJisheng Zhang struct mvneta_rx_queue *rxq) 33914a188a63SJisheng Zhang { 3392c5aff182SThomas Petazzoni /* Set Rx descriptors queue starting address */ 3393c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_RXQ_BASE_ADDR_REG(rxq->id), rxq->descs_phys); 3394c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_RXQ_SIZE_REG(rxq->id), rxq->size); 3395c5aff182SThomas Petazzoni 3396c5aff182SThomas Petazzoni /* Set coalescing pkts and time */ 3397c5aff182SThomas Petazzoni mvneta_rx_pkts_coal_set(pp, rxq, rxq->pkts_coal); 3398c5aff182SThomas Petazzoni mvneta_rx_time_coal_set(pp, rxq, rxq->time_coal); 3399c5aff182SThomas Petazzoni 3400dc35a10fSMarcin Wojtas if (!pp->bm_priv) { 3401562e2f46SYelena Krivosheev /* Set Offset */ 3402562e2f46SYelena Krivosheev mvneta_rxq_offset_set(pp, rxq, 0); 3403e735fd55SMarcin Wojtas mvneta_rxq_buf_size_set(pp, rxq, PAGE_SIZE < SZ_64K ? 34048dc9a088SLorenzo Bianconi MVNETA_MAX_RX_BUF_SIZE : 3405e735fd55SMarcin Wojtas MVNETA_RX_BUF_SIZE(pp->pkt_size)); 3406c5aff182SThomas Petazzoni mvneta_rxq_bm_disable(pp, rxq); 3407e9f64999SGregory CLEMENT mvneta_rxq_fill(pp, rxq, rxq->size); 3408dc35a10fSMarcin Wojtas } else { 3409562e2f46SYelena Krivosheev /* Set Offset */ 3410562e2f46SYelena Krivosheev mvneta_rxq_offset_set(pp, rxq, 3411562e2f46SYelena Krivosheev NET_SKB_PAD - pp->rx_offset_correction); 3412562e2f46SYelena Krivosheev 3413dc35a10fSMarcin Wojtas mvneta_rxq_bm_enable(pp, rxq); 3414562e2f46SYelena Krivosheev /* Fill RXQ with buffers from RX pool */ 3415dc35a10fSMarcin Wojtas mvneta_rxq_long_pool_set(pp, rxq); 3416dc35a10fSMarcin Wojtas mvneta_rxq_short_pool_set(pp, rxq); 3417e9f64999SGregory CLEMENT mvneta_rxq_non_occup_desc_add(pp, rxq, rxq->size); 3418dc35a10fSMarcin Wojtas } 34194a188a63SJisheng Zhang } 34204a188a63SJisheng Zhang 34214a188a63SJisheng Zhang /* Create a specified RX queue */ 34224a188a63SJisheng Zhang static int mvneta_rxq_init(struct mvneta_port *pp, 34234a188a63SJisheng Zhang struct mvneta_rx_queue *rxq) 34244a188a63SJisheng Zhang 34254a188a63SJisheng Zhang { 34264a188a63SJisheng Zhang int ret; 34274a188a63SJisheng Zhang 34284a188a63SJisheng Zhang ret = mvneta_rxq_sw_init(pp, rxq); 34294a188a63SJisheng Zhang if (ret < 0) 34304a188a63SJisheng Zhang return ret; 34314a188a63SJisheng Zhang 34324a188a63SJisheng Zhang mvneta_rxq_hw_init(pp, rxq); 3433dc35a10fSMarcin Wojtas 3434c5aff182SThomas Petazzoni return 0; 3435c5aff182SThomas Petazzoni } 3436c5aff182SThomas Petazzoni 3437c5aff182SThomas Petazzoni /* Cleanup Rx queue */ 3438c5aff182SThomas Petazzoni static void mvneta_rxq_deinit(struct mvneta_port *pp, 3439c5aff182SThomas Petazzoni struct mvneta_rx_queue *rxq) 3440c5aff182SThomas Petazzoni { 3441c5aff182SThomas Petazzoni mvneta_rxq_drop_pkts(pp, rxq); 3442c5aff182SThomas Petazzoni 3443c5aff182SThomas Petazzoni if (rxq->descs) 3444c5aff182SThomas Petazzoni dma_free_coherent(pp->dev->dev.parent, 3445c5aff182SThomas Petazzoni rxq->size * MVNETA_DESC_ALIGNED_SIZE, 3446c5aff182SThomas Petazzoni rxq->descs, 3447c5aff182SThomas Petazzoni rxq->descs_phys); 3448c5aff182SThomas Petazzoni 3449c5aff182SThomas Petazzoni rxq->descs = NULL; 3450c5aff182SThomas Petazzoni rxq->last_desc = 0; 3451c5aff182SThomas Petazzoni rxq->next_desc_to_proc = 0; 3452c5aff182SThomas Petazzoni rxq->descs_phys = 0; 3453562e2f46SYelena Krivosheev rxq->first_to_refill = 0; 3454562e2f46SYelena Krivosheev rxq->refill_num = 0; 3455c5aff182SThomas Petazzoni } 3456c5aff182SThomas Petazzoni 34574a188a63SJisheng Zhang static int mvneta_txq_sw_init(struct mvneta_port *pp, 3458c5aff182SThomas Petazzoni struct mvneta_tx_queue *txq) 3459c5aff182SThomas Petazzoni { 346050bf8cb6SGregory CLEMENT int cpu; 346150bf8cb6SGregory CLEMENT 3462c5aff182SThomas Petazzoni txq->size = pp->tx_ring_size; 3463c5aff182SThomas Petazzoni 34648eef5f97SEzequiel Garcia /* A queue must always have room for at least one skb. 34658eef5f97SEzequiel Garcia * Therefore, stop the queue when the free entries reaches 34668eef5f97SEzequiel Garcia * the maximum number of descriptors per skb. 34678eef5f97SEzequiel Garcia */ 34688eef5f97SEzequiel Garcia txq->tx_stop_threshold = txq->size - MVNETA_MAX_SKB_DESCS; 34698eef5f97SEzequiel Garcia txq->tx_wake_threshold = txq->tx_stop_threshold / 2; 34708eef5f97SEzequiel Garcia 3471c5aff182SThomas Petazzoni /* Allocate memory for TX descriptors */ 3472c5aff182SThomas Petazzoni txq->descs = dma_alloc_coherent(pp->dev->dev.parent, 3473c5aff182SThomas Petazzoni txq->size * MVNETA_DESC_ALIGNED_SIZE, 3474c5aff182SThomas Petazzoni &txq->descs_phys, GFP_KERNEL); 3475f95936ccSMarkus Elfring if (!txq->descs) 3476c5aff182SThomas Petazzoni return -ENOMEM; 3477c5aff182SThomas Petazzoni 3478c5aff182SThomas Petazzoni txq->last_desc = txq->size - 1; 3479c5aff182SThomas Petazzoni 34809e58c8b4SLorenzo Bianconi txq->buf = kmalloc_array(txq->size, sizeof(*txq->buf), GFP_KERNEL); 3481f4544e53STom Rix if (!txq->buf) 3482c5aff182SThomas Petazzoni return -ENOMEM; 34832adb719dSEzequiel Garcia 34842adb719dSEzequiel Garcia /* Allocate DMA buffers for TSO MAC/IP/TCP headers */ 34852adb719dSEzequiel Garcia txq->tso_hdrs = dma_alloc_coherent(pp->dev->dev.parent, 34862adb719dSEzequiel Garcia txq->size * TSO_HEADER_SIZE, 34872adb719dSEzequiel Garcia &txq->tso_hdrs_phys, GFP_KERNEL); 3488f4544e53STom Rix if (!txq->tso_hdrs) 34892adb719dSEzequiel Garcia return -ENOMEM; 3490c5aff182SThomas Petazzoni 349150bf8cb6SGregory CLEMENT /* Setup XPS mapping */ 3492cf9bf871SMaxime Chevallier if (pp->neta_armada3700) 3493cf9bf871SMaxime Chevallier cpu = 0; 3494cf9bf871SMaxime Chevallier else if (txq_number > 1) 349550bf8cb6SGregory CLEMENT cpu = txq->id % num_present_cpus(); 349650bf8cb6SGregory CLEMENT else 349750bf8cb6SGregory CLEMENT cpu = pp->rxq_def % num_present_cpus(); 349850bf8cb6SGregory CLEMENT cpumask_set_cpu(cpu, &txq->affinity_mask); 349950bf8cb6SGregory CLEMENT netif_set_xps_queue(pp->dev, &txq->affinity_mask, txq->id); 350050bf8cb6SGregory CLEMENT 3501c5aff182SThomas Petazzoni return 0; 3502c5aff182SThomas Petazzoni } 3503c5aff182SThomas Petazzoni 35044a188a63SJisheng Zhang static void mvneta_txq_hw_init(struct mvneta_port *pp, 35054a188a63SJisheng Zhang struct mvneta_tx_queue *txq) 35064a188a63SJisheng Zhang { 35074a188a63SJisheng Zhang /* Set maximum bandwidth for enabled TXQs */ 35084a188a63SJisheng Zhang mvreg_write(pp, MVETH_TXQ_TOKEN_CFG_REG(txq->id), 0x03ffffff); 35094a188a63SJisheng Zhang mvreg_write(pp, MVETH_TXQ_TOKEN_COUNT_REG(txq->id), 0x3fffffff); 35104a188a63SJisheng Zhang 35114a188a63SJisheng Zhang /* Set Tx descriptors queue starting address */ 35124a188a63SJisheng Zhang mvreg_write(pp, MVNETA_TXQ_BASE_ADDR_REG(txq->id), txq->descs_phys); 35134a188a63SJisheng Zhang mvreg_write(pp, MVNETA_TXQ_SIZE_REG(txq->id), txq->size); 35144a188a63SJisheng Zhang 35154a188a63SJisheng Zhang mvneta_tx_done_pkts_coal_set(pp, txq, txq->done_pkts_coal); 35164a188a63SJisheng Zhang } 35174a188a63SJisheng Zhang 35184a188a63SJisheng Zhang /* Create and initialize a tx queue */ 35194a188a63SJisheng Zhang static int mvneta_txq_init(struct mvneta_port *pp, 35204a188a63SJisheng Zhang struct mvneta_tx_queue *txq) 35214a188a63SJisheng Zhang { 35224a188a63SJisheng Zhang int ret; 35234a188a63SJisheng Zhang 35244a188a63SJisheng Zhang ret = mvneta_txq_sw_init(pp, txq); 35254a188a63SJisheng Zhang if (ret < 0) 35264a188a63SJisheng Zhang return ret; 35274a188a63SJisheng Zhang 35284a188a63SJisheng Zhang mvneta_txq_hw_init(pp, txq); 35294a188a63SJisheng Zhang 35304a188a63SJisheng Zhang return 0; 35314a188a63SJisheng Zhang } 35324a188a63SJisheng Zhang 3533c5aff182SThomas Petazzoni /* Free allocated resources when mvneta_txq_init() fails to allocate memory*/ 35344a188a63SJisheng Zhang static void mvneta_txq_sw_deinit(struct mvneta_port *pp, 3535c5aff182SThomas Petazzoni struct mvneta_tx_queue *txq) 3536c5aff182SThomas Petazzoni { 3537a29b6235SMarcin Wojtas struct netdev_queue *nq = netdev_get_tx_queue(pp->dev, txq->id); 3538a29b6235SMarcin Wojtas 35399e58c8b4SLorenzo Bianconi kfree(txq->buf); 3540c5aff182SThomas Petazzoni 35412adb719dSEzequiel Garcia if (txq->tso_hdrs) 35422adb719dSEzequiel Garcia dma_free_coherent(pp->dev->dev.parent, 35432adb719dSEzequiel Garcia txq->size * TSO_HEADER_SIZE, 35442adb719dSEzequiel Garcia txq->tso_hdrs, txq->tso_hdrs_phys); 3545c5aff182SThomas Petazzoni if (txq->descs) 3546c5aff182SThomas Petazzoni dma_free_coherent(pp->dev->dev.parent, 3547c5aff182SThomas Petazzoni txq->size * MVNETA_DESC_ALIGNED_SIZE, 3548c5aff182SThomas Petazzoni txq->descs, txq->descs_phys); 3549c5aff182SThomas Petazzoni 3550a29b6235SMarcin Wojtas netdev_tx_reset_queue(nq); 3551a29b6235SMarcin Wojtas 3552*2960a2d3SRussell King (Oracle) txq->buf = NULL; 3553*2960a2d3SRussell King (Oracle) txq->tso_hdrs = NULL; 3554c5aff182SThomas Petazzoni txq->descs = NULL; 3555c5aff182SThomas Petazzoni txq->last_desc = 0; 3556c5aff182SThomas Petazzoni txq->next_desc_to_proc = 0; 3557c5aff182SThomas Petazzoni txq->descs_phys = 0; 35584a188a63SJisheng Zhang } 3559c5aff182SThomas Petazzoni 35604a188a63SJisheng Zhang static void mvneta_txq_hw_deinit(struct mvneta_port *pp, 35614a188a63SJisheng Zhang struct mvneta_tx_queue *txq) 35624a188a63SJisheng Zhang { 3563c5aff182SThomas Petazzoni /* Set minimum bandwidth for disabled TXQs */ 3564c5aff182SThomas Petazzoni mvreg_write(pp, MVETH_TXQ_TOKEN_CFG_REG(txq->id), 0); 3565c5aff182SThomas Petazzoni mvreg_write(pp, MVETH_TXQ_TOKEN_COUNT_REG(txq->id), 0); 3566c5aff182SThomas Petazzoni 3567c5aff182SThomas Petazzoni /* Set Tx descriptors queue starting address and size */ 3568c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_TXQ_BASE_ADDR_REG(txq->id), 0); 3569c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_TXQ_SIZE_REG(txq->id), 0); 3570c5aff182SThomas Petazzoni } 3571c5aff182SThomas Petazzoni 35724a188a63SJisheng Zhang static void mvneta_txq_deinit(struct mvneta_port *pp, 35734a188a63SJisheng Zhang struct mvneta_tx_queue *txq) 35744a188a63SJisheng Zhang { 35754a188a63SJisheng Zhang mvneta_txq_sw_deinit(pp, txq); 35764a188a63SJisheng Zhang mvneta_txq_hw_deinit(pp, txq); 35774a188a63SJisheng Zhang } 35784a188a63SJisheng Zhang 3579c5aff182SThomas Petazzoni /* Cleanup all Tx queues */ 3580c5aff182SThomas Petazzoni static void mvneta_cleanup_txqs(struct mvneta_port *pp) 3581c5aff182SThomas Petazzoni { 3582c5aff182SThomas Petazzoni int queue; 3583c5aff182SThomas Petazzoni 3584c5aff182SThomas Petazzoni for (queue = 0; queue < txq_number; queue++) 3585c5aff182SThomas Petazzoni mvneta_txq_deinit(pp, &pp->txqs[queue]); 3586c5aff182SThomas Petazzoni } 3587c5aff182SThomas Petazzoni 3588c5aff182SThomas Petazzoni /* Cleanup all Rx queues */ 3589c5aff182SThomas Petazzoni static void mvneta_cleanup_rxqs(struct mvneta_port *pp) 3590c5aff182SThomas Petazzoni { 35912dcf75e2SGregory CLEMENT int queue; 35922dcf75e2SGregory CLEMENT 3593ca5902a6SYelena Krivosheev for (queue = 0; queue < rxq_number; queue++) 35942dcf75e2SGregory CLEMENT mvneta_rxq_deinit(pp, &pp->rxqs[queue]); 3595c5aff182SThomas Petazzoni } 3596c5aff182SThomas Petazzoni 3597c5aff182SThomas Petazzoni 3598c5aff182SThomas Petazzoni /* Init all Rx queues */ 3599c5aff182SThomas Petazzoni static int mvneta_setup_rxqs(struct mvneta_port *pp) 3600c5aff182SThomas Petazzoni { 36012dcf75e2SGregory CLEMENT int queue; 36022dcf75e2SGregory CLEMENT 36032dcf75e2SGregory CLEMENT for (queue = 0; queue < rxq_number; queue++) { 36042dcf75e2SGregory CLEMENT int err = mvneta_rxq_init(pp, &pp->rxqs[queue]); 36052dcf75e2SGregory CLEMENT 3606c5aff182SThomas Petazzoni if (err) { 3607c5aff182SThomas Petazzoni netdev_err(pp->dev, "%s: can't create rxq=%d\n", 36082dcf75e2SGregory CLEMENT __func__, queue); 3609c5aff182SThomas Petazzoni mvneta_cleanup_rxqs(pp); 3610c5aff182SThomas Petazzoni return err; 3611c5aff182SThomas Petazzoni } 36122dcf75e2SGregory CLEMENT } 3613c5aff182SThomas Petazzoni 3614c5aff182SThomas Petazzoni return 0; 3615c5aff182SThomas Petazzoni } 3616c5aff182SThomas Petazzoni 3617c5aff182SThomas Petazzoni /* Init all tx queues */ 3618c5aff182SThomas Petazzoni static int mvneta_setup_txqs(struct mvneta_port *pp) 3619c5aff182SThomas Petazzoni { 3620c5aff182SThomas Petazzoni int queue; 3621c5aff182SThomas Petazzoni 3622c5aff182SThomas Petazzoni for (queue = 0; queue < txq_number; queue++) { 3623c5aff182SThomas Petazzoni int err = mvneta_txq_init(pp, &pp->txqs[queue]); 3624c5aff182SThomas Petazzoni if (err) { 3625c5aff182SThomas Petazzoni netdev_err(pp->dev, "%s: can't create txq=%d\n", 3626c5aff182SThomas Petazzoni __func__, queue); 3627c5aff182SThomas Petazzoni mvneta_cleanup_txqs(pp); 3628c5aff182SThomas Petazzoni return err; 3629c5aff182SThomas Petazzoni } 3630c5aff182SThomas Petazzoni } 3631c5aff182SThomas Petazzoni 3632c5aff182SThomas Petazzoni return 0; 3633c5aff182SThomas Petazzoni } 3634c5aff182SThomas Petazzoni 3635b4748553SSascha Hauer static int mvneta_comphy_init(struct mvneta_port *pp, phy_interface_t interface) 3636031b922bSMarek Behún { 3637031b922bSMarek Behún int ret; 3638031b922bSMarek Behún 3639b4748553SSascha Hauer ret = phy_set_mode_ext(pp->comphy, PHY_MODE_ETHERNET, interface); 3640031b922bSMarek Behún if (ret) 3641031b922bSMarek Behún return ret; 3642031b922bSMarek Behún 3643031b922bSMarek Behún return phy_power_on(pp->comphy); 3644031b922bSMarek Behún } 3645031b922bSMarek Behún 3646b4748553SSascha Hauer static int mvneta_config_interface(struct mvneta_port *pp, 3647b4748553SSascha Hauer phy_interface_t interface) 3648b4748553SSascha Hauer { 3649b4748553SSascha Hauer int ret = 0; 3650b4748553SSascha Hauer 3651b4748553SSascha Hauer if (pp->comphy) { 3652b4748553SSascha Hauer if (interface == PHY_INTERFACE_MODE_SGMII || 3653b4748553SSascha Hauer interface == PHY_INTERFACE_MODE_1000BASEX || 3654b4748553SSascha Hauer interface == PHY_INTERFACE_MODE_2500BASEX) { 3655b4748553SSascha Hauer ret = mvneta_comphy_init(pp, interface); 3656b4748553SSascha Hauer } 3657b4748553SSascha Hauer } else { 3658b4748553SSascha Hauer switch (interface) { 3659b4748553SSascha Hauer case PHY_INTERFACE_MODE_QSGMII: 3660b4748553SSascha Hauer mvreg_write(pp, MVNETA_SERDES_CFG, 3661b4748553SSascha Hauer MVNETA_QSGMII_SERDES_PROTO); 3662b4748553SSascha Hauer break; 3663b4748553SSascha Hauer 3664b4748553SSascha Hauer case PHY_INTERFACE_MODE_SGMII: 3665b4748553SSascha Hauer case PHY_INTERFACE_MODE_1000BASEX: 3666b4748553SSascha Hauer mvreg_write(pp, MVNETA_SERDES_CFG, 3667b4748553SSascha Hauer MVNETA_SGMII_SERDES_PROTO); 3668b4748553SSascha Hauer break; 36691a642ca7SSascha Hauer 36701a642ca7SSascha Hauer case PHY_INTERFACE_MODE_2500BASEX: 36711a642ca7SSascha Hauer mvreg_write(pp, MVNETA_SERDES_CFG, 36721a642ca7SSascha Hauer MVNETA_HSGMII_SERDES_PROTO); 36731a642ca7SSascha Hauer break; 3674b4748553SSascha Hauer default: 3675d3d239dcSSascha Hauer break; 3676b4748553SSascha Hauer } 3677b4748553SSascha Hauer } 3678b4748553SSascha Hauer 3679b4748553SSascha Hauer pp->phy_interface = interface; 3680b4748553SSascha Hauer 3681b4748553SSascha Hauer return ret; 3682b4748553SSascha Hauer } 3683b4748553SSascha Hauer 3684c5aff182SThomas Petazzoni static void mvneta_start_dev(struct mvneta_port *pp) 3685c5aff182SThomas Petazzoni { 36866b125d63SGregory CLEMENT int cpu; 368712bb03b4SMaxime Ripard 3688b4748553SSascha Hauer WARN_ON(mvneta_config_interface(pp, pp->phy_interface)); 3689a10c1c81SRussell King 3690c5aff182SThomas Petazzoni mvneta_max_rx_size_set(pp, pp->pkt_size); 3691c5aff182SThomas Petazzoni mvneta_txq_max_tx_size_set(pp, pp->pkt_size); 3692c5aff182SThomas Petazzoni 3693c5aff182SThomas Petazzoni /* start the Rx/Tx activity */ 3694c5aff182SThomas Petazzoni mvneta_port_enable(pp); 3695c5aff182SThomas Petazzoni 36962636ac3cSMarcin Wojtas if (!pp->neta_armada3700) { 3697c5aff182SThomas Petazzoni /* Enable polling on the port */ 3698129219e4SGregory CLEMENT for_each_online_cpu(cpu) { 36992636ac3cSMarcin Wojtas struct mvneta_pcpu_port *port = 37002636ac3cSMarcin Wojtas per_cpu_ptr(pp->ports, cpu); 370112bb03b4SMaxime Ripard 370212bb03b4SMaxime Ripard napi_enable(&port->napi); 370312bb03b4SMaxime Ripard } 37042636ac3cSMarcin Wojtas } else { 37052636ac3cSMarcin Wojtas napi_enable(&pp->napi); 37062636ac3cSMarcin Wojtas } 3707c5aff182SThomas Petazzoni 37082dcf75e2SGregory CLEMENT /* Unmask interrupts. It has to be done from each CPU */ 37096b125d63SGregory CLEMENT on_each_cpu(mvneta_percpu_unmask_interrupt, pp, true); 37106b125d63SGregory CLEMENT 3711898b2970SStas Sergeev mvreg_write(pp, MVNETA_INTR_MISC_MASK, 3712898b2970SStas Sergeev MVNETA_CAUSE_PHY_STATUS_CHANGE | 3713856b2cc5SRussell King MVNETA_CAUSE_LINK_CHANGE); 3714c5aff182SThomas Petazzoni 3715503f9aa9SRussell King phylink_start(pp->phylink); 371661b5cc20SDaniel González Cabanelas 37175ba2254bSJisheng Zhang /* We may have called phylink_speed_down before */ 371861b5cc20SDaniel González Cabanelas phylink_speed_up(pp->phylink); 371961b5cc20SDaniel González Cabanelas 3720c5aff182SThomas Petazzoni netif_tx_start_all_queues(pp->dev); 372162a502ccSLorenzo Bianconi 372262a502ccSLorenzo Bianconi clear_bit(__MVNETA_DOWN, &pp->state); 3723c5aff182SThomas Petazzoni } 3724c5aff182SThomas Petazzoni 3725c5aff182SThomas Petazzoni static void mvneta_stop_dev(struct mvneta_port *pp) 3726c5aff182SThomas Petazzoni { 372712bb03b4SMaxime Ripard unsigned int cpu; 372812bb03b4SMaxime Ripard 372962a502ccSLorenzo Bianconi set_bit(__MVNETA_DOWN, &pp->state); 373062a502ccSLorenzo Bianconi 373161b5cc20SDaniel González Cabanelas if (device_may_wakeup(&pp->dev->dev)) 373261b5cc20SDaniel González Cabanelas phylink_speed_down(pp->phylink, false); 373361b5cc20SDaniel González Cabanelas 3734503f9aa9SRussell King phylink_stop(pp->phylink); 3735c5aff182SThomas Petazzoni 37362636ac3cSMarcin Wojtas if (!pp->neta_armada3700) { 3737129219e4SGregory CLEMENT for_each_online_cpu(cpu) { 37382636ac3cSMarcin Wojtas struct mvneta_pcpu_port *port = 37392636ac3cSMarcin Wojtas per_cpu_ptr(pp->ports, cpu); 374012bb03b4SMaxime Ripard 374112bb03b4SMaxime Ripard napi_disable(&port->napi); 374212bb03b4SMaxime Ripard } 37432636ac3cSMarcin Wojtas } else { 37442636ac3cSMarcin Wojtas napi_disable(&pp->napi); 37452636ac3cSMarcin Wojtas } 3746c5aff182SThomas Petazzoni 3747c5aff182SThomas Petazzoni netif_carrier_off(pp->dev); 3748c5aff182SThomas Petazzoni 3749c5aff182SThomas Petazzoni mvneta_port_down(pp); 3750c5aff182SThomas Petazzoni netif_tx_stop_all_queues(pp->dev); 3751c5aff182SThomas Petazzoni 3752c5aff182SThomas Petazzoni /* Stop the port activity */ 3753c5aff182SThomas Petazzoni mvneta_port_disable(pp); 3754c5aff182SThomas Petazzoni 3755c5aff182SThomas Petazzoni /* Clear all ethernet port interrupts */ 3756db488c10SGregory CLEMENT on_each_cpu(mvneta_percpu_clear_intr_cause, pp, true); 3757c5aff182SThomas Petazzoni 3758c5aff182SThomas Petazzoni /* Mask all ethernet port interrupts */ 3759db488c10SGregory CLEMENT on_each_cpu(mvneta_percpu_mask_interrupt, pp, true); 3760c5aff182SThomas Petazzoni 3761c5aff182SThomas Petazzoni mvneta_tx_reset(pp); 3762c5aff182SThomas Petazzoni mvneta_rx_reset(pp); 3763a10c1c81SRussell King 3764a10c1c81SRussell King WARN_ON(phy_power_off(pp->comphy)); 3765c5aff182SThomas Petazzoni } 3766c5aff182SThomas Petazzoni 3767db5dd0dbSMarcin Wojtas static void mvneta_percpu_enable(void *arg) 3768db5dd0dbSMarcin Wojtas { 3769db5dd0dbSMarcin Wojtas struct mvneta_port *pp = arg; 3770db5dd0dbSMarcin Wojtas 3771db5dd0dbSMarcin Wojtas enable_percpu_irq(pp->dev->irq, IRQ_TYPE_NONE); 3772db5dd0dbSMarcin Wojtas } 3773db5dd0dbSMarcin Wojtas 3774db5dd0dbSMarcin Wojtas static void mvneta_percpu_disable(void *arg) 3775db5dd0dbSMarcin Wojtas { 3776db5dd0dbSMarcin Wojtas struct mvneta_port *pp = arg; 3777db5dd0dbSMarcin Wojtas 3778db5dd0dbSMarcin Wojtas disable_percpu_irq(pp->dev->irq); 3779db5dd0dbSMarcin Wojtas } 3780db5dd0dbSMarcin Wojtas 3781c5aff182SThomas Petazzoni /* Change the device mtu */ 3782c5aff182SThomas Petazzoni static int mvneta_change_mtu(struct net_device *dev, int mtu) 3783c5aff182SThomas Petazzoni { 3784c5aff182SThomas Petazzoni struct mvneta_port *pp = netdev_priv(dev); 3785e121d270SLorenzo Bianconi struct bpf_prog *prog = pp->xdp_prog; 3786c5aff182SThomas Petazzoni int ret; 3787c5aff182SThomas Petazzoni 37885777987eSJarod Wilson if (!IS_ALIGNED(MVNETA_RX_PKT_SIZE(mtu), 8)) { 37895777987eSJarod Wilson netdev_info(dev, "Illegal MTU value %d, rounding to %d\n", 37905777987eSJarod Wilson mtu, ALIGN(MVNETA_RX_PKT_SIZE(mtu), 8)); 37915777987eSJarod Wilson mtu = ALIGN(MVNETA_RX_PKT_SIZE(mtu), 8); 37925777987eSJarod Wilson } 3793c5aff182SThomas Petazzoni 3794e121d270SLorenzo Bianconi if (prog && !prog->aux->xdp_has_frags && 3795e121d270SLorenzo Bianconi mtu > MVNETA_MAX_RX_BUF_SIZE) { 3796e121d270SLorenzo Bianconi netdev_info(dev, "Illegal MTU %d for XDP prog without frags\n", 3797e121d270SLorenzo Bianconi mtu); 3798e121d270SLorenzo Bianconi 37990db51da7SLorenzo Bianconi return -EINVAL; 38000db51da7SLorenzo Bianconi } 38010db51da7SLorenzo Bianconi 3802c5aff182SThomas Petazzoni dev->mtu = mtu; 3803c5aff182SThomas Petazzoni 3804b65657fcSSimon Guinot if (!netif_running(dev)) { 3805dc35a10fSMarcin Wojtas if (pp->bm_priv) 3806dc35a10fSMarcin Wojtas mvneta_bm_update_mtu(pp, mtu); 3807dc35a10fSMarcin Wojtas 3808b65657fcSSimon Guinot netdev_update_features(dev); 3809c5aff182SThomas Petazzoni return 0; 3810b65657fcSSimon Guinot } 3811c5aff182SThomas Petazzoni 38126a20c175SThomas Petazzoni /* The interface is running, so we have to force a 3813a92dbd96SEzequiel Garcia * reallocation of the queues 3814c5aff182SThomas Petazzoni */ 3815c5aff182SThomas Petazzoni mvneta_stop_dev(pp); 3816db5dd0dbSMarcin Wojtas on_each_cpu(mvneta_percpu_disable, pp, true); 3817c5aff182SThomas Petazzoni 3818c5aff182SThomas Petazzoni mvneta_cleanup_txqs(pp); 3819c5aff182SThomas Petazzoni mvneta_cleanup_rxqs(pp); 3820c5aff182SThomas Petazzoni 3821dc35a10fSMarcin Wojtas if (pp->bm_priv) 3822dc35a10fSMarcin Wojtas mvneta_bm_update_mtu(pp, mtu); 3823dc35a10fSMarcin Wojtas 3824a92dbd96SEzequiel Garcia pp->pkt_size = MVNETA_RX_PKT_SIZE(dev->mtu); 3825c5aff182SThomas Petazzoni 3826c5aff182SThomas Petazzoni ret = mvneta_setup_rxqs(pp); 3827c5aff182SThomas Petazzoni if (ret) { 3828a92dbd96SEzequiel Garcia netdev_err(dev, "unable to setup rxqs after MTU change\n"); 3829c5aff182SThomas Petazzoni return ret; 3830c5aff182SThomas Petazzoni } 3831c5aff182SThomas Petazzoni 3832a92dbd96SEzequiel Garcia ret = mvneta_setup_txqs(pp); 3833a92dbd96SEzequiel Garcia if (ret) { 3834a92dbd96SEzequiel Garcia netdev_err(dev, "unable to setup txqs after MTU change\n"); 3835a92dbd96SEzequiel Garcia return ret; 3836a92dbd96SEzequiel Garcia } 3837c5aff182SThomas Petazzoni 3838db5dd0dbSMarcin Wojtas on_each_cpu(mvneta_percpu_enable, pp, true); 3839c5aff182SThomas Petazzoni mvneta_start_dev(pp); 3840c5aff182SThomas Petazzoni 3841b65657fcSSimon Guinot netdev_update_features(dev); 3842b65657fcSSimon Guinot 3843c5aff182SThomas Petazzoni return 0; 3844c5aff182SThomas Petazzoni } 3845c5aff182SThomas Petazzoni 3846b65657fcSSimon Guinot static netdev_features_t mvneta_fix_features(struct net_device *dev, 3847b65657fcSSimon Guinot netdev_features_t features) 3848b65657fcSSimon Guinot { 3849b65657fcSSimon Guinot struct mvneta_port *pp = netdev_priv(dev); 3850b65657fcSSimon Guinot 3851b65657fcSSimon Guinot if (pp->tx_csum_limit && dev->mtu > pp->tx_csum_limit) { 3852b65657fcSSimon Guinot features &= ~(NETIF_F_IP_CSUM | NETIF_F_TSO); 3853b65657fcSSimon Guinot netdev_info(dev, 3854b65657fcSSimon Guinot "Disable IP checksum for MTU greater than %dB\n", 3855b65657fcSSimon Guinot pp->tx_csum_limit); 3856b65657fcSSimon Guinot } 3857b65657fcSSimon Guinot 3858b65657fcSSimon Guinot return features; 3859b65657fcSSimon Guinot } 3860b65657fcSSimon Guinot 38618cc3e439SThomas Petazzoni /* Get mac address */ 38628cc3e439SThomas Petazzoni static void mvneta_get_mac_addr(struct mvneta_port *pp, unsigned char *addr) 38638cc3e439SThomas Petazzoni { 38648cc3e439SThomas Petazzoni u32 mac_addr_l, mac_addr_h; 38658cc3e439SThomas Petazzoni 38668cc3e439SThomas Petazzoni mac_addr_l = mvreg_read(pp, MVNETA_MAC_ADDR_LOW); 38678cc3e439SThomas Petazzoni mac_addr_h = mvreg_read(pp, MVNETA_MAC_ADDR_HIGH); 38688cc3e439SThomas Petazzoni addr[0] = (mac_addr_h >> 24) & 0xFF; 38698cc3e439SThomas Petazzoni addr[1] = (mac_addr_h >> 16) & 0xFF; 38708cc3e439SThomas Petazzoni addr[2] = (mac_addr_h >> 8) & 0xFF; 38718cc3e439SThomas Petazzoni addr[3] = mac_addr_h & 0xFF; 38728cc3e439SThomas Petazzoni addr[4] = (mac_addr_l >> 8) & 0xFF; 38738cc3e439SThomas Petazzoni addr[5] = mac_addr_l & 0xFF; 38748cc3e439SThomas Petazzoni } 38758cc3e439SThomas Petazzoni 3876c5aff182SThomas Petazzoni /* Handle setting mac address */ 3877c5aff182SThomas Petazzoni static int mvneta_set_mac_addr(struct net_device *dev, void *addr) 3878c5aff182SThomas Petazzoni { 3879c5aff182SThomas Petazzoni struct mvneta_port *pp = netdev_priv(dev); 3880e68de360SEzequiel Garcia struct sockaddr *sockaddr = addr; 3881e68de360SEzequiel Garcia int ret; 3882c5aff182SThomas Petazzoni 3883e68de360SEzequiel Garcia ret = eth_prepare_mac_addr_change(dev, addr); 3884e68de360SEzequiel Garcia if (ret < 0) 3885e68de360SEzequiel Garcia return ret; 3886c5aff182SThomas Petazzoni /* Remove previous address table entry */ 3887c5aff182SThomas Petazzoni mvneta_mac_addr_set(pp, dev->dev_addr, -1); 3888c5aff182SThomas Petazzoni 3889c5aff182SThomas Petazzoni /* Set new addr in hw */ 389090b74c01SGregory CLEMENT mvneta_mac_addr_set(pp, sockaddr->sa_data, pp->rxq_def); 3891c5aff182SThomas Petazzoni 3892e68de360SEzequiel Garcia eth_commit_mac_addr_change(dev, addr); 3893c5aff182SThomas Petazzoni return 0; 3894c5aff182SThomas Petazzoni } 3895c5aff182SThomas Petazzoni 3896c2e7d2dfSRussell King static struct mvneta_port *mvneta_pcs_to_port(struct phylink_pcs *pcs) 3897503f9aa9SRussell King { 3898c2e7d2dfSRussell King return container_of(pcs, struct mvneta_port, phylink_pcs); 3899503f9aa9SRussell King } 3900503f9aa9SRussell King 3901d8c36693SRussell King (Oracle) static int mvneta_pcs_validate(struct phylink_pcs *pcs, 3902d8c36693SRussell King (Oracle) unsigned long *supported, 3903d8c36693SRussell King (Oracle) const struct phylink_link_state *state) 3904d8c36693SRussell King (Oracle) { 3905d8c36693SRussell King (Oracle) /* We only support QSGMII, SGMII, 802.3z and RGMII modes. 3906d8c36693SRussell King (Oracle) * When in 802.3z mode, we must have AN enabled: 3907d8c36693SRussell King (Oracle) * "Bit 2 Field InBandAnEn In-band Auto-Negotiation enable. ... 3908d8c36693SRussell King (Oracle) * When <PortType> = 1 (1000BASE-X) this field must be set to 1." 3909d8c36693SRussell King (Oracle) */ 3910d8c36693SRussell King (Oracle) if (phy_interface_mode_is_8023z(state->interface) && 3911d8c36693SRussell King (Oracle) !phylink_test(state->advertising, Autoneg)) 3912d8c36693SRussell King (Oracle) return -EINVAL; 3913d8c36693SRussell King (Oracle) 3914d8c36693SRussell King (Oracle) return 0; 3915d8c36693SRussell King (Oracle) } 3916d8c36693SRussell King (Oracle) 3917c2e7d2dfSRussell King static void mvneta_pcs_get_state(struct phylink_pcs *pcs, 3918503f9aa9SRussell King struct phylink_link_state *state) 3919c5aff182SThomas Petazzoni { 3920c2e7d2dfSRussell King struct mvneta_port *pp = mvneta_pcs_to_port(pcs); 3921503f9aa9SRussell King u32 gmac_stat; 3922c5aff182SThomas Petazzoni 3923503f9aa9SRussell King gmac_stat = mvreg_read(pp, MVNETA_GMAC_STATUS); 3924503f9aa9SRussell King 3925503f9aa9SRussell King if (gmac_stat & MVNETA_GMAC_SPEED_1000) 3926a10c1c81SRussell King state->speed = 3927a10c1c81SRussell King state->interface == PHY_INTERFACE_MODE_2500BASEX ? 3928a10c1c81SRussell King SPEED_2500 : SPEED_1000; 3929503f9aa9SRussell King else if (gmac_stat & MVNETA_GMAC_SPEED_100) 3930503f9aa9SRussell King state->speed = SPEED_100; 3931503f9aa9SRussell King else 3932503f9aa9SRussell King state->speed = SPEED_10; 3933503f9aa9SRussell King 3934503f9aa9SRussell King state->an_complete = !!(gmac_stat & MVNETA_GMAC_AN_COMPLETE); 3935503f9aa9SRussell King state->link = !!(gmac_stat & MVNETA_GMAC_LINK_UP); 3936503f9aa9SRussell King state->duplex = !!(gmac_stat & MVNETA_GMAC_FULL_DUPLEX); 3937503f9aa9SRussell King 39384932a918SRussell King if (gmac_stat & MVNETA_GMAC_RX_FLOW_CTRL_ENABLE) 39394932a918SRussell King state->pause |= MLO_PAUSE_RX; 39404932a918SRussell King if (gmac_stat & MVNETA_GMAC_TX_FLOW_CTRL_ENABLE) 39414932a918SRussell King state->pause |= MLO_PAUSE_TX; 3942503f9aa9SRussell King } 3943503f9aa9SRussell King 3944c2e7d2dfSRussell King static int mvneta_pcs_config(struct phylink_pcs *pcs, 3945c2e7d2dfSRussell King unsigned int mode, phy_interface_t interface, 3946c2e7d2dfSRussell King const unsigned long *advertising, 3947c2e7d2dfSRussell King bool permit_pause_to_mac) 394822f4bf8aSRussell King { 3949c2e7d2dfSRussell King struct mvneta_port *pp = mvneta_pcs_to_port(pcs); 3950c2e7d2dfSRussell King u32 mask, val, an, old_an, changed; 3951c2e7d2dfSRussell King 3952c2e7d2dfSRussell King mask = MVNETA_GMAC_INBAND_AN_ENABLE | 3953c2e7d2dfSRussell King MVNETA_GMAC_INBAND_RESTART_AN | 3954c2e7d2dfSRussell King MVNETA_GMAC_AN_SPEED_EN | 3955c2e7d2dfSRussell King MVNETA_GMAC_AN_FLOW_CTRL_EN | 3956c2e7d2dfSRussell King MVNETA_GMAC_AN_DUPLEX_EN; 3957c2e7d2dfSRussell King 3958c2e7d2dfSRussell King if (phylink_autoneg_inband(mode)) { 3959c2e7d2dfSRussell King mask |= MVNETA_GMAC_CONFIG_MII_SPEED | 3960c2e7d2dfSRussell King MVNETA_GMAC_CONFIG_GMII_SPEED | 3961c2e7d2dfSRussell King MVNETA_GMAC_CONFIG_FULL_DUPLEX; 3962c2e7d2dfSRussell King val = MVNETA_GMAC_INBAND_AN_ENABLE; 3963c2e7d2dfSRussell King 3964c2e7d2dfSRussell King if (interface == PHY_INTERFACE_MODE_SGMII) { 3965c2e7d2dfSRussell King /* SGMII mode receives the speed and duplex from PHY */ 3966c2e7d2dfSRussell King val |= MVNETA_GMAC_AN_SPEED_EN | 3967c2e7d2dfSRussell King MVNETA_GMAC_AN_DUPLEX_EN; 3968c2e7d2dfSRussell King } else { 3969c2e7d2dfSRussell King /* 802.3z mode has fixed speed and duplex */ 3970c2e7d2dfSRussell King val |= MVNETA_GMAC_CONFIG_GMII_SPEED | 3971c2e7d2dfSRussell King MVNETA_GMAC_CONFIG_FULL_DUPLEX; 3972c2e7d2dfSRussell King 3973c2e7d2dfSRussell King /* The FLOW_CTRL_EN bit selects either the hardware 3974c2e7d2dfSRussell King * automatically or the CONFIG_FLOW_CTRL manually 3975c2e7d2dfSRussell King * controls the GMAC pause mode. 3976c2e7d2dfSRussell King */ 3977c2e7d2dfSRussell King if (permit_pause_to_mac) 3978c2e7d2dfSRussell King val |= MVNETA_GMAC_AN_FLOW_CTRL_EN; 3979c2e7d2dfSRussell King 3980c2e7d2dfSRussell King /* Update the advertisement bits */ 3981c2e7d2dfSRussell King mask |= MVNETA_GMAC_ADVERT_SYM_FLOW_CTRL; 3982c2e7d2dfSRussell King if (phylink_test(advertising, Pause)) 3983c2e7d2dfSRussell King val |= MVNETA_GMAC_ADVERT_SYM_FLOW_CTRL; 3984c2e7d2dfSRussell King } 3985c2e7d2dfSRussell King } else { 3986c2e7d2dfSRussell King /* Phy or fixed speed - disable in-band AN modes */ 3987c2e7d2dfSRussell King val = 0; 3988c2e7d2dfSRussell King } 3989c2e7d2dfSRussell King 3990c2e7d2dfSRussell King old_an = an = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG); 3991c2e7d2dfSRussell King an = (an & ~mask) | val; 3992c2e7d2dfSRussell King changed = old_an ^ an; 3993c2e7d2dfSRussell King if (changed) 3994c2e7d2dfSRussell King mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, an); 3995c2e7d2dfSRussell King 3996c2e7d2dfSRussell King /* We are only interested in the advertisement bits changing */ 3997c2e7d2dfSRussell King return !!(changed & MVNETA_GMAC_ADVERT_SYM_FLOW_CTRL); 3998c2e7d2dfSRussell King } 3999c2e7d2dfSRussell King 4000c2e7d2dfSRussell King static void mvneta_pcs_an_restart(struct phylink_pcs *pcs) 4001c2e7d2dfSRussell King { 4002c2e7d2dfSRussell King struct mvneta_port *pp = mvneta_pcs_to_port(pcs); 400322f4bf8aSRussell King u32 gmac_an = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG); 400422f4bf8aSRussell King 400522f4bf8aSRussell King mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, 400622f4bf8aSRussell King gmac_an | MVNETA_GMAC_INBAND_RESTART_AN); 400722f4bf8aSRussell King mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, 400822f4bf8aSRussell King gmac_an & ~MVNETA_GMAC_INBAND_RESTART_AN); 400922f4bf8aSRussell King } 401022f4bf8aSRussell King 4011c2e7d2dfSRussell King static const struct phylink_pcs_ops mvneta_phylink_pcs_ops = { 4012d8c36693SRussell King (Oracle) .pcs_validate = mvneta_pcs_validate, 4013c2e7d2dfSRussell King .pcs_get_state = mvneta_pcs_get_state, 4014c2e7d2dfSRussell King .pcs_config = mvneta_pcs_config, 4015c2e7d2dfSRussell King .pcs_an_restart = mvneta_pcs_an_restart, 4016c2e7d2dfSRussell King }; 4017c2e7d2dfSRussell King 40180ac4a71fSRussell King (Oracle) static struct phylink_pcs *mvneta_mac_select_pcs(struct phylink_config *config, 40190ac4a71fSRussell King (Oracle) phy_interface_t interface) 40200ac4a71fSRussell King (Oracle) { 40210ac4a71fSRussell King (Oracle) struct net_device *ndev = to_net_dev(config->dev); 40220ac4a71fSRussell King (Oracle) struct mvneta_port *pp = netdev_priv(ndev); 40230ac4a71fSRussell King (Oracle) 40240ac4a71fSRussell King (Oracle) return &pp->phylink_pcs; 40250ac4a71fSRussell King (Oracle) } 40260ac4a71fSRussell King (Oracle) 40275a7d8953SRussell King static int mvneta_mac_prepare(struct phylink_config *config, unsigned int mode, 40285a7d8953SRussell King phy_interface_t interface) 40295a7d8953SRussell King { 40305a7d8953SRussell King struct net_device *ndev = to_net_dev(config->dev); 40315a7d8953SRussell King struct mvneta_port *pp = netdev_priv(ndev); 40325a7d8953SRussell King u32 val; 40335a7d8953SRussell King 40345a7d8953SRussell King if (pp->phy_interface != interface || 40355a7d8953SRussell King phylink_autoneg_inband(mode)) { 40365a7d8953SRussell King /* Force the link down when changing the interface or if in 40375a7d8953SRussell King * in-band mode. According to Armada 370 documentation, we 40385a7d8953SRussell King * can only change the port mode and in-band enable when the 40395a7d8953SRussell King * link is down. 40405a7d8953SRussell King */ 40415a7d8953SRussell King val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG); 40425a7d8953SRussell King val &= ~MVNETA_GMAC_FORCE_LINK_PASS; 40435a7d8953SRussell King val |= MVNETA_GMAC_FORCE_LINK_DOWN; 40445a7d8953SRussell King mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val); 40455a7d8953SRussell King } 40465a7d8953SRussell King 40475a7d8953SRussell King if (pp->phy_interface != interface) 40485a7d8953SRussell King WARN_ON(phy_power_off(pp->comphy)); 40495a7d8953SRussell King 40505a7d8953SRussell King /* Enable the 1ms clock */ 40515a7d8953SRussell King if (phylink_autoneg_inband(mode)) { 40525a7d8953SRussell King unsigned long rate = clk_get_rate(pp->clk); 40535a7d8953SRussell King 40545a7d8953SRussell King mvreg_write(pp, MVNETA_GMAC_CLOCK_DIVIDER, 40555a7d8953SRussell King MVNETA_GMAC_1MS_CLOCK_ENABLE | (rate / 1000)); 40565a7d8953SRussell King } 40575a7d8953SRussell King 40585a7d8953SRussell King return 0; 40595a7d8953SRussell King } 40605a7d8953SRussell King 406144cc27e4SIoana Ciornei static void mvneta_mac_config(struct phylink_config *config, unsigned int mode, 4062503f9aa9SRussell King const struct phylink_link_state *state) 4063503f9aa9SRussell King { 406444cc27e4SIoana Ciornei struct net_device *ndev = to_net_dev(config->dev); 4065503f9aa9SRussell King struct mvneta_port *pp = netdev_priv(ndev); 406622f4bf8aSRussell King u32 new_ctrl0, gmac_ctrl0 = mvreg_read(pp, MVNETA_GMAC_CTRL_0); 4067503f9aa9SRussell King u32 new_ctrl2, gmac_ctrl2 = mvreg_read(pp, MVNETA_GMAC_CTRL_2); 4068da58a931SMaxime Chevallier u32 new_ctrl4, gmac_ctrl4 = mvreg_read(pp, MVNETA_GMAC_CTRL_4); 4069503f9aa9SRussell King 407022f4bf8aSRussell King new_ctrl0 = gmac_ctrl0 & ~MVNETA_GMAC0_PORT_1000BASE_X; 407132699954SRussell King new_ctrl2 = gmac_ctrl2 & ~(MVNETA_GMAC2_INBAND_AN_ENABLE | 407232699954SRussell King MVNETA_GMAC2_PORT_RESET); 4073da58a931SMaxime Chevallier new_ctrl4 = gmac_ctrl4 & ~(MVNETA_GMAC4_SHORT_PREAMBLE_ENABLE); 4074c5aff182SThomas Petazzoni 407532699954SRussell King /* Even though it might look weird, when we're configured in 407632699954SRussell King * SGMII or QSGMII mode, the RGMII bit needs to be set. 407732699954SRussell King */ 407832699954SRussell King new_ctrl2 |= MVNETA_GMAC2_PORT_RGMII; 407932699954SRussell King 408032699954SRussell King if (state->interface == PHY_INTERFACE_MODE_QSGMII || 408122f4bf8aSRussell King state->interface == PHY_INTERFACE_MODE_SGMII || 408222f4bf8aSRussell King phy_interface_mode_is_8023z(state->interface)) 408332699954SRussell King new_ctrl2 |= MVNETA_GMAC2_PCS_ENABLE; 408432699954SRussell King 4085503f9aa9SRussell King if (!phylink_autoneg_inband(mode)) { 4086ff03f0b1SRussell King /* Phy or fixed speed - nothing to do, leave the 4087ff03f0b1SRussell King * configured speed, duplex and flow control as-is. 4088ff03f0b1SRussell King */ 408922f4bf8aSRussell King } else if (state->interface == PHY_INTERFACE_MODE_SGMII) { 4090503f9aa9SRussell King /* SGMII mode receives the state from the PHY */ 4091503f9aa9SRussell King new_ctrl2 |= MVNETA_GMAC2_INBAND_AN_ENABLE; 409222f4bf8aSRussell King } else { 409322f4bf8aSRussell King /* 802.3z negotiation - only 1000base-X */ 409422f4bf8aSRussell King new_ctrl0 |= MVNETA_GMAC0_PORT_1000BASE_X; 4095c5aff182SThomas Petazzoni } 4096c5aff182SThomas Petazzoni 4097da58a931SMaxime Chevallier /* When at 2.5G, the link partner can send frames with shortened 4098da58a931SMaxime Chevallier * preambles. 4099da58a931SMaxime Chevallier */ 4100f2ca673dSRussell King if (state->interface == PHY_INTERFACE_MODE_2500BASEX) 4101da58a931SMaxime Chevallier new_ctrl4 |= MVNETA_GMAC4_SHORT_PREAMBLE_ENABLE; 4102da58a931SMaxime Chevallier 410322f4bf8aSRussell King if (new_ctrl0 != gmac_ctrl0) 410422f4bf8aSRussell King mvreg_write(pp, MVNETA_GMAC_CTRL_0, new_ctrl0); 4105503f9aa9SRussell King if (new_ctrl2 != gmac_ctrl2) 4106503f9aa9SRussell King mvreg_write(pp, MVNETA_GMAC_CTRL_2, new_ctrl2); 4107da58a931SMaxime Chevallier if (new_ctrl4 != gmac_ctrl4) 4108da58a931SMaxime Chevallier mvreg_write(pp, MVNETA_GMAC_CTRL_4, new_ctrl4); 410932699954SRussell King 411032699954SRussell King if (gmac_ctrl2 & MVNETA_GMAC2_PORT_RESET) { 411132699954SRussell King while ((mvreg_read(pp, MVNETA_GMAC_CTRL_2) & 411232699954SRussell King MVNETA_GMAC2_PORT_RESET) != 0) 411332699954SRussell King continue; 411432699954SRussell King } 4115503f9aa9SRussell King } 4116503f9aa9SRussell King 41175a7d8953SRussell King static int mvneta_mac_finish(struct phylink_config *config, unsigned int mode, 41185a7d8953SRussell King phy_interface_t interface) 41195a7d8953SRussell King { 41205a7d8953SRussell King struct net_device *ndev = to_net_dev(config->dev); 41215a7d8953SRussell King struct mvneta_port *pp = netdev_priv(ndev); 41225a7d8953SRussell King u32 val, clk; 41235a7d8953SRussell King 41245a7d8953SRussell King /* Disable 1ms clock if not in in-band mode */ 41255a7d8953SRussell King if (!phylink_autoneg_inband(mode)) { 41265a7d8953SRussell King clk = mvreg_read(pp, MVNETA_GMAC_CLOCK_DIVIDER); 41275a7d8953SRussell King clk &= ~MVNETA_GMAC_1MS_CLOCK_ENABLE; 41285a7d8953SRussell King mvreg_write(pp, MVNETA_GMAC_CLOCK_DIVIDER, clk); 41295a7d8953SRussell King } 41305a7d8953SRussell King 41315a7d8953SRussell King if (pp->phy_interface != interface) 41325a7d8953SRussell King /* Enable the Serdes PHY */ 41335a7d8953SRussell King WARN_ON(mvneta_config_interface(pp, interface)); 41345a7d8953SRussell King 41355a7d8953SRussell King /* Allow the link to come up if in in-band mode, otherwise the 41365a7d8953SRussell King * link is forced via mac_link_down()/mac_link_up() 41375a7d8953SRussell King */ 41385a7d8953SRussell King if (phylink_autoneg_inband(mode)) { 41395a7d8953SRussell King val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG); 41405a7d8953SRussell King val &= ~MVNETA_GMAC_FORCE_LINK_DOWN; 41415a7d8953SRussell King mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val); 41425a7d8953SRussell King } 41435a7d8953SRussell King 41445a7d8953SRussell King return 0; 41455a7d8953SRussell King } 41465a7d8953SRussell King 41476d81f451SRussell King static void mvneta_set_eee(struct mvneta_port *pp, bool enable) 41486d81f451SRussell King { 41496d81f451SRussell King u32 lpi_ctl1; 41506d81f451SRussell King 41516d81f451SRussell King lpi_ctl1 = mvreg_read(pp, MVNETA_LPI_CTRL_1); 41526d81f451SRussell King if (enable) 41536d81f451SRussell King lpi_ctl1 |= MVNETA_LPI_REQUEST_ENABLE; 41546d81f451SRussell King else 41556d81f451SRussell King lpi_ctl1 &= ~MVNETA_LPI_REQUEST_ENABLE; 41566d81f451SRussell King mvreg_write(pp, MVNETA_LPI_CTRL_1, lpi_ctl1); 41576d81f451SRussell King } 41586d81f451SRussell King 415944cc27e4SIoana Ciornei static void mvneta_mac_link_down(struct phylink_config *config, 416044cc27e4SIoana Ciornei unsigned int mode, phy_interface_t interface) 4161fc548b99SRussell King { 416244cc27e4SIoana Ciornei struct net_device *ndev = to_net_dev(config->dev); 4163fc548b99SRussell King struct mvneta_port *pp = netdev_priv(ndev); 4164fc548b99SRussell King u32 val; 4165fc548b99SRussell King 4166503f9aa9SRussell King mvneta_port_down(pp); 4167503f9aa9SRussell King 4168503f9aa9SRussell King if (!phylink_autoneg_inband(mode)) { 4169fc548b99SRussell King val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG); 4170fc548b99SRussell King val &= ~MVNETA_GMAC_FORCE_LINK_PASS; 4171fc548b99SRussell King val |= MVNETA_GMAC_FORCE_LINK_DOWN; 4172fc548b99SRussell King mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val); 4173fc548b99SRussell King } 41746d81f451SRussell King 41756d81f451SRussell King pp->eee_active = false; 41766d81f451SRussell King mvneta_set_eee(pp, false); 4177fc548b99SRussell King } 4178fc548b99SRussell King 417991a208f2SRussell King static void mvneta_mac_link_up(struct phylink_config *config, 418091a208f2SRussell King struct phy_device *phy, 418191a208f2SRussell King unsigned int mode, phy_interface_t interface, 418291a208f2SRussell King int speed, int duplex, 418391a208f2SRussell King bool tx_pause, bool rx_pause) 4184fc548b99SRussell King { 418544cc27e4SIoana Ciornei struct net_device *ndev = to_net_dev(config->dev); 4186fc548b99SRussell King struct mvneta_port *pp = netdev_priv(ndev); 4187fc548b99SRussell King u32 val; 4188fc548b99SRussell King 4189503f9aa9SRussell King if (!phylink_autoneg_inband(mode)) { 4190fc548b99SRussell King val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG); 4191ff03f0b1SRussell King val &= ~(MVNETA_GMAC_FORCE_LINK_DOWN | 4192ff03f0b1SRussell King MVNETA_GMAC_CONFIG_MII_SPEED | 4193ff03f0b1SRussell King MVNETA_GMAC_CONFIG_GMII_SPEED | 4194ff03f0b1SRussell King MVNETA_GMAC_CONFIG_FLOW_CTRL | 4195ff03f0b1SRussell King MVNETA_GMAC_CONFIG_FULL_DUPLEX); 4196fc548b99SRussell King val |= MVNETA_GMAC_FORCE_LINK_PASS; 4197ff03f0b1SRussell King 4198ff03f0b1SRussell King if (speed == SPEED_1000 || speed == SPEED_2500) 4199ff03f0b1SRussell King val |= MVNETA_GMAC_CONFIG_GMII_SPEED; 4200ff03f0b1SRussell King else if (speed == SPEED_100) 4201ff03f0b1SRussell King val |= MVNETA_GMAC_CONFIG_MII_SPEED; 4202ff03f0b1SRussell King 4203ff03f0b1SRussell King if (duplex == DUPLEX_FULL) 4204ff03f0b1SRussell King val |= MVNETA_GMAC_CONFIG_FULL_DUPLEX; 4205ff03f0b1SRussell King 4206ff03f0b1SRussell King if (tx_pause || rx_pause) 4207ff03f0b1SRussell King val |= MVNETA_GMAC_CONFIG_FLOW_CTRL; 4208ff03f0b1SRussell King 4209ff03f0b1SRussell King mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val); 4210ff03f0b1SRussell King } else { 4211ff03f0b1SRussell King /* When inband doesn't cover flow control or flow control is 4212ff03f0b1SRussell King * disabled, we need to manually configure it. This bit will 4213ff03f0b1SRussell King * only have effect if MVNETA_GMAC_AN_FLOW_CTRL_EN is unset. 4214ff03f0b1SRussell King */ 4215ff03f0b1SRussell King val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG); 4216ff03f0b1SRussell King val &= ~MVNETA_GMAC_CONFIG_FLOW_CTRL; 4217ff03f0b1SRussell King 4218ff03f0b1SRussell King if (tx_pause || rx_pause) 4219ff03f0b1SRussell King val |= MVNETA_GMAC_CONFIG_FLOW_CTRL; 4220ff03f0b1SRussell King 4221fc548b99SRussell King mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val); 4222fc548b99SRussell King } 4223fc548b99SRussell King 4224fc548b99SRussell King mvneta_port_up(pp); 42256d81f451SRussell King 42266d81f451SRussell King if (phy && pp->eee_enabled) { 422753243d41SJisheng Zhang pp->eee_active = phy_init_eee(phy, false) >= 0; 42286d81f451SRussell King mvneta_set_eee(pp, pp->eee_active && pp->tx_lpi_enabled); 42296d81f451SRussell King } 4230fc548b99SRussell King } 4231fc548b99SRussell King 4232503f9aa9SRussell King static const struct phylink_mac_ops mvneta_phylink_ops = { 42330ac4a71fSRussell King (Oracle) .mac_select_pcs = mvneta_mac_select_pcs, 42345a7d8953SRussell King .mac_prepare = mvneta_mac_prepare, 4235503f9aa9SRussell King .mac_config = mvneta_mac_config, 42365a7d8953SRussell King .mac_finish = mvneta_mac_finish, 4237503f9aa9SRussell King .mac_link_down = mvneta_mac_link_down, 4238503f9aa9SRussell King .mac_link_up = mvneta_mac_link_up, 4239503f9aa9SRussell King }; 4240c5aff182SThomas Petazzoni 4241c5aff182SThomas Petazzoni static int mvneta_mdio_probe(struct mvneta_port *pp) 4242c5aff182SThomas Petazzoni { 424382960fffSJisheng Zhang struct ethtool_wolinfo wol = { .cmd = ETHTOOL_GWOL }; 4244503f9aa9SRussell King int err = phylink_of_phy_connect(pp->phylink, pp->dn, 0); 4245c5aff182SThomas Petazzoni 4246503f9aa9SRussell King if (err) 4247503f9aa9SRussell King netdev_err(pp->dev, "could not attach PHY: %d\n", err); 4248c5aff182SThomas Petazzoni 4249503f9aa9SRussell King phylink_ethtool_get_wol(pp->phylink, &wol); 425082960fffSJisheng Zhang device_set_wakeup_capable(&pp->dev->dev, !!wol.supported); 425182960fffSJisheng Zhang 425261b5cc20SDaniel González Cabanelas /* PHY WoL may be enabled but device wakeup disabled */ 425361b5cc20SDaniel González Cabanelas if (wol.supported) 425461b5cc20SDaniel González Cabanelas device_set_wakeup_enable(&pp->dev->dev, !!wol.wolopts); 425561b5cc20SDaniel González Cabanelas 4256503f9aa9SRussell King return err; 4257c5aff182SThomas Petazzoni } 4258c5aff182SThomas Petazzoni 4259c5aff182SThomas Petazzoni static void mvneta_mdio_remove(struct mvneta_port *pp) 4260c5aff182SThomas Petazzoni { 4261503f9aa9SRussell King phylink_disconnect_phy(pp->phylink); 4262c5aff182SThomas Petazzoni } 4263c5aff182SThomas Petazzoni 4264120cfa50SGregory CLEMENT /* Electing a CPU must be done in an atomic way: it should be done 4265120cfa50SGregory CLEMENT * after or before the removal/insertion of a CPU and this function is 4266120cfa50SGregory CLEMENT * not reentrant. 4267120cfa50SGregory CLEMENT */ 4268f8642885SMaxime Ripard static void mvneta_percpu_elect(struct mvneta_port *pp) 4269f8642885SMaxime Ripard { 42700cf9deb3SColin Ian King int elected_cpu = 0, max_cpu, cpu; 4271f8642885SMaxime Ripard 4272cad5d847SGregory CLEMENT /* Use the cpu associated to the rxq when it is online, in all 4273cad5d847SGregory CLEMENT * the other cases, use the cpu 0 which can't be offline. 4274cad5d847SGregory CLEMENT */ 4275cdd97383SDan Carpenter if (pp->rxq_def < nr_cpu_ids && cpu_online(pp->rxq_def)) 4276cad5d847SGregory CLEMENT elected_cpu = pp->rxq_def; 4277cad5d847SGregory CLEMENT 42782dcf75e2SGregory CLEMENT max_cpu = num_present_cpus(); 4279f8642885SMaxime Ripard 4280f8642885SMaxime Ripard for_each_online_cpu(cpu) { 42812dcf75e2SGregory CLEMENT int rxq_map = 0, txq_map = 0; 42822dcf75e2SGregory CLEMENT int rxq; 42832dcf75e2SGregory CLEMENT 42842dcf75e2SGregory CLEMENT for (rxq = 0; rxq < rxq_number; rxq++) 42852dcf75e2SGregory CLEMENT if ((rxq % max_cpu) == cpu) 42862dcf75e2SGregory CLEMENT rxq_map |= MVNETA_CPU_RXQ_ACCESS(rxq); 42872dcf75e2SGregory CLEMENT 4288cad5d847SGregory CLEMENT if (cpu == elected_cpu) 4289b52f6425SYangyang Li /* Map the default receive queue to the elected CPU */ 42902dcf75e2SGregory CLEMENT rxq_map |= MVNETA_CPU_RXQ_ACCESS(pp->rxq_def); 429150bf8cb6SGregory CLEMENT 429250bf8cb6SGregory CLEMENT /* We update the TX queue map only if we have one 429350bf8cb6SGregory CLEMENT * queue. In this case we associate the TX queue to 429450bf8cb6SGregory CLEMENT * the CPU bound to the default RX queue 429550bf8cb6SGregory CLEMENT */ 429650bf8cb6SGregory CLEMENT if (txq_number == 1) 4297cad5d847SGregory CLEMENT txq_map = (cpu == elected_cpu) ? 429850bf8cb6SGregory CLEMENT MVNETA_CPU_TXQ_ACCESS(1) : 0; 429950bf8cb6SGregory CLEMENT else 430050bf8cb6SGregory CLEMENT txq_map = mvreg_read(pp, MVNETA_CPU_MAP(cpu)) & 430150bf8cb6SGregory CLEMENT MVNETA_CPU_TXQ_ACCESS_ALL_MASK; 430250bf8cb6SGregory CLEMENT 43032dcf75e2SGregory CLEMENT mvreg_write(pp, MVNETA_CPU_MAP(cpu), rxq_map | txq_map); 43042dcf75e2SGregory CLEMENT 43052dcf75e2SGregory CLEMENT /* Update the interrupt mask on each CPU according the 43062dcf75e2SGregory CLEMENT * new mapping 43072dcf75e2SGregory CLEMENT */ 43082dcf75e2SGregory CLEMENT smp_call_function_single(cpu, mvneta_percpu_unmask_interrupt, 4309f8642885SMaxime Ripard pp, true); 4310f8642885SMaxime Ripard } 4311f8642885SMaxime Ripard }; 4312f8642885SMaxime Ripard 431384a3f4dbSSebastian Andrzej Siewior static int mvneta_cpu_online(unsigned int cpu, struct hlist_node *node) 4314f8642885SMaxime Ripard { 431584a3f4dbSSebastian Andrzej Siewior int other_cpu; 431684a3f4dbSSebastian Andrzej Siewior struct mvneta_port *pp = hlist_entry_safe(node, struct mvneta_port, 431784a3f4dbSSebastian Andrzej Siewior node_online); 4318f8642885SMaxime Ripard struct mvneta_pcpu_port *port = per_cpu_ptr(pp->ports, cpu); 4319f8642885SMaxime Ripard 4320cf9bf871SMaxime Chevallier /* Armada 3700's per-cpu interrupt for mvneta is broken, all interrupts 4321cf9bf871SMaxime Chevallier * are routed to CPU 0, so we don't need all the cpu-hotplug support 4322cf9bf871SMaxime Chevallier */ 4323cf9bf871SMaxime Chevallier if (pp->neta_armada3700) 4324cf9bf871SMaxime Chevallier return 0; 432584a3f4dbSSebastian Andrzej Siewior 4326120cfa50SGregory CLEMENT spin_lock(&pp->lock); 432784a3f4dbSSebastian Andrzej Siewior /* 432884a3f4dbSSebastian Andrzej Siewior * Configuring the driver for a new CPU while the driver is 432984a3f4dbSSebastian Andrzej Siewior * stopping is racy, so just avoid it. 4330120cfa50SGregory CLEMENT */ 4331120cfa50SGregory CLEMENT if (pp->is_stopped) { 4332120cfa50SGregory CLEMENT spin_unlock(&pp->lock); 433384a3f4dbSSebastian Andrzej Siewior return 0; 4334120cfa50SGregory CLEMENT } 4335f8642885SMaxime Ripard netif_tx_stop_all_queues(pp->dev); 4336f8642885SMaxime Ripard 433784a3f4dbSSebastian Andrzej Siewior /* 433884a3f4dbSSebastian Andrzej Siewior * We have to synchronise on tha napi of each CPU except the one 433984a3f4dbSSebastian Andrzej Siewior * just being woken up 4340f8642885SMaxime Ripard */ 4341f8642885SMaxime Ripard for_each_online_cpu(other_cpu) { 4342f8642885SMaxime Ripard if (other_cpu != cpu) { 4343f8642885SMaxime Ripard struct mvneta_pcpu_port *other_port = 4344f8642885SMaxime Ripard per_cpu_ptr(pp->ports, other_cpu); 4345f8642885SMaxime Ripard 4346f8642885SMaxime Ripard napi_synchronize(&other_port->napi); 4347f8642885SMaxime Ripard } 4348f8642885SMaxime Ripard } 4349f8642885SMaxime Ripard 4350f8642885SMaxime Ripard /* Mask all ethernet port interrupts */ 4351db488c10SGregory CLEMENT on_each_cpu(mvneta_percpu_mask_interrupt, pp, true); 4352f8642885SMaxime Ripard napi_enable(&port->napi); 4353f8642885SMaxime Ripard 435484a3f4dbSSebastian Andrzej Siewior /* 435584a3f4dbSSebastian Andrzej Siewior * Enable per-CPU interrupts on the CPU that is 43562dcf75e2SGregory CLEMENT * brought up. 43572dcf75e2SGregory CLEMENT */ 43580e28bf93SAnna-Maria Gleixner mvneta_percpu_enable(pp); 43592dcf75e2SGregory CLEMENT 436084a3f4dbSSebastian Andrzej Siewior /* 436184a3f4dbSSebastian Andrzej Siewior * Enable per-CPU interrupt on the one CPU we care 4362f8642885SMaxime Ripard * about. 4363f8642885SMaxime Ripard */ 4364f8642885SMaxime Ripard mvneta_percpu_elect(pp); 4365f8642885SMaxime Ripard 4366db488c10SGregory CLEMENT /* Unmask all ethernet port interrupts */ 4367db488c10SGregory CLEMENT on_each_cpu(mvneta_percpu_unmask_interrupt, pp, true); 4368f8642885SMaxime Ripard mvreg_write(pp, MVNETA_INTR_MISC_MASK, 4369f8642885SMaxime Ripard MVNETA_CAUSE_PHY_STATUS_CHANGE | 4370856b2cc5SRussell King MVNETA_CAUSE_LINK_CHANGE); 4371f8642885SMaxime Ripard netif_tx_start_all_queues(pp->dev); 4372120cfa50SGregory CLEMENT spin_unlock(&pp->lock); 437384a3f4dbSSebastian Andrzej Siewior return 0; 437484a3f4dbSSebastian Andrzej Siewior } 437584a3f4dbSSebastian Andrzej Siewior 437684a3f4dbSSebastian Andrzej Siewior static int mvneta_cpu_down_prepare(unsigned int cpu, struct hlist_node *node) 437784a3f4dbSSebastian Andrzej Siewior { 437884a3f4dbSSebastian Andrzej Siewior struct mvneta_port *pp = hlist_entry_safe(node, struct mvneta_port, 437984a3f4dbSSebastian Andrzej Siewior node_online); 438084a3f4dbSSebastian Andrzej Siewior struct mvneta_pcpu_port *port = per_cpu_ptr(pp->ports, cpu); 438184a3f4dbSSebastian Andrzej Siewior 438284a3f4dbSSebastian Andrzej Siewior /* 438384a3f4dbSSebastian Andrzej Siewior * Thanks to this lock we are sure that any pending cpu election is 438484a3f4dbSSebastian Andrzej Siewior * done. 43855888511eSGregory CLEMENT */ 43865888511eSGregory CLEMENT spin_lock(&pp->lock); 4387f8642885SMaxime Ripard /* Mask all ethernet port interrupts */ 4388db488c10SGregory CLEMENT on_each_cpu(mvneta_percpu_mask_interrupt, pp, true); 43895888511eSGregory CLEMENT spin_unlock(&pp->lock); 4390f8642885SMaxime Ripard 4391f8642885SMaxime Ripard napi_synchronize(&port->napi); 4392f8642885SMaxime Ripard napi_disable(&port->napi); 439384a3f4dbSSebastian Andrzej Siewior /* Disable per-CPU interrupts on the CPU that is brought down. */ 43940e28bf93SAnna-Maria Gleixner mvneta_percpu_disable(pp); 439584a3f4dbSSebastian Andrzej Siewior return 0; 439684a3f4dbSSebastian Andrzej Siewior } 4397f8642885SMaxime Ripard 439884a3f4dbSSebastian Andrzej Siewior static int mvneta_cpu_dead(unsigned int cpu, struct hlist_node *node) 439984a3f4dbSSebastian Andrzej Siewior { 440084a3f4dbSSebastian Andrzej Siewior struct mvneta_port *pp = hlist_entry_safe(node, struct mvneta_port, 440184a3f4dbSSebastian Andrzej Siewior node_dead); 440284a3f4dbSSebastian Andrzej Siewior 4403f8642885SMaxime Ripard /* Check if a new CPU must be elected now this on is down */ 4404120cfa50SGregory CLEMENT spin_lock(&pp->lock); 4405f8642885SMaxime Ripard mvneta_percpu_elect(pp); 4406120cfa50SGregory CLEMENT spin_unlock(&pp->lock); 4407f8642885SMaxime Ripard /* Unmask all ethernet port interrupts */ 4408db488c10SGregory CLEMENT on_each_cpu(mvneta_percpu_unmask_interrupt, pp, true); 4409f8642885SMaxime Ripard mvreg_write(pp, MVNETA_INTR_MISC_MASK, 4410f8642885SMaxime Ripard MVNETA_CAUSE_PHY_STATUS_CHANGE | 4411856b2cc5SRussell King MVNETA_CAUSE_LINK_CHANGE); 4412f8642885SMaxime Ripard netif_tx_start_all_queues(pp->dev); 441384a3f4dbSSebastian Andrzej Siewior return 0; 4414f8642885SMaxime Ripard } 4415f8642885SMaxime Ripard 4416c5aff182SThomas Petazzoni static int mvneta_open(struct net_device *dev) 4417c5aff182SThomas Petazzoni { 4418c5aff182SThomas Petazzoni struct mvneta_port *pp = netdev_priv(dev); 44196b125d63SGregory CLEMENT int ret; 4420c5aff182SThomas Petazzoni 4421c5aff182SThomas Petazzoni pp->pkt_size = MVNETA_RX_PKT_SIZE(pp->dev->mtu); 4422c5aff182SThomas Petazzoni 4423c5aff182SThomas Petazzoni ret = mvneta_setup_rxqs(pp); 4424c5aff182SThomas Petazzoni if (ret) 4425c5aff182SThomas Petazzoni return ret; 4426c5aff182SThomas Petazzoni 4427c5aff182SThomas Petazzoni ret = mvneta_setup_txqs(pp); 4428c5aff182SThomas Petazzoni if (ret) 4429c5aff182SThomas Petazzoni goto err_cleanup_rxqs; 4430c5aff182SThomas Petazzoni 4431c5aff182SThomas Petazzoni /* Connect to port interrupt line */ 44322636ac3cSMarcin Wojtas if (pp->neta_armada3700) 44332636ac3cSMarcin Wojtas ret = request_irq(pp->dev->irq, mvneta_isr, 0, 44342636ac3cSMarcin Wojtas dev->name, pp); 44352636ac3cSMarcin Wojtas else 44362636ac3cSMarcin Wojtas ret = request_percpu_irq(pp->dev->irq, mvneta_percpu_isr, 44372636ac3cSMarcin Wojtas dev->name, pp->ports); 4438c5aff182SThomas Petazzoni if (ret) { 4439c5aff182SThomas Petazzoni netdev_err(pp->dev, "cannot request irq %d\n", pp->dev->irq); 4440c5aff182SThomas Petazzoni goto err_cleanup_txqs; 4441c5aff182SThomas Petazzoni } 4442c5aff182SThomas Petazzoni 44432636ac3cSMarcin Wojtas if (!pp->neta_armada3700) { 44442dcf75e2SGregory CLEMENT /* Enable per-CPU interrupt on all the CPU to handle our RX 44452dcf75e2SGregory CLEMENT * queue interrupts 44462dcf75e2SGregory CLEMENT */ 44476b125d63SGregory CLEMENT on_each_cpu(mvneta_percpu_enable, pp, true); 44482dcf75e2SGregory CLEMENT 4449120cfa50SGregory CLEMENT pp->is_stopped = false; 4450f8642885SMaxime Ripard /* Register a CPU notifier to handle the case where our CPU 4451f8642885SMaxime Ripard * might be taken offline. 4452f8642885SMaxime Ripard */ 445384a3f4dbSSebastian Andrzej Siewior ret = cpuhp_state_add_instance_nocalls(online_hpstate, 445484a3f4dbSSebastian Andrzej Siewior &pp->node_online); 445584a3f4dbSSebastian Andrzej Siewior if (ret) 445684a3f4dbSSebastian Andrzej Siewior goto err_free_irq; 445784a3f4dbSSebastian Andrzej Siewior 445884a3f4dbSSebastian Andrzej Siewior ret = cpuhp_state_add_instance_nocalls(CPUHP_NET_MVNETA_DEAD, 445984a3f4dbSSebastian Andrzej Siewior &pp->node_dead); 446084a3f4dbSSebastian Andrzej Siewior if (ret) 446184a3f4dbSSebastian Andrzej Siewior goto err_free_online_hp; 44622636ac3cSMarcin Wojtas } 4463f8642885SMaxime Ripard 4464c5aff182SThomas Petazzoni ret = mvneta_mdio_probe(pp); 4465c5aff182SThomas Petazzoni if (ret < 0) { 4466c5aff182SThomas Petazzoni netdev_err(dev, "cannot probe MDIO bus\n"); 446784a3f4dbSSebastian Andrzej Siewior goto err_free_dead_hp; 4468c5aff182SThomas Petazzoni } 4469c5aff182SThomas Petazzoni 4470c5aff182SThomas Petazzoni mvneta_start_dev(pp); 4471c5aff182SThomas Petazzoni 4472c5aff182SThomas Petazzoni return 0; 4473c5aff182SThomas Petazzoni 447484a3f4dbSSebastian Andrzej Siewior err_free_dead_hp: 44752636ac3cSMarcin Wojtas if (!pp->neta_armada3700) 447684a3f4dbSSebastian Andrzej Siewior cpuhp_state_remove_instance_nocalls(CPUHP_NET_MVNETA_DEAD, 447784a3f4dbSSebastian Andrzej Siewior &pp->node_dead); 447884a3f4dbSSebastian Andrzej Siewior err_free_online_hp: 44792636ac3cSMarcin Wojtas if (!pp->neta_armada3700) 44802636ac3cSMarcin Wojtas cpuhp_state_remove_instance_nocalls(online_hpstate, 44812636ac3cSMarcin Wojtas &pp->node_online); 4482c5aff182SThomas Petazzoni err_free_irq: 44832636ac3cSMarcin Wojtas if (pp->neta_armada3700) { 44842636ac3cSMarcin Wojtas free_irq(pp->dev->irq, pp); 44852636ac3cSMarcin Wojtas } else { 44863d8c4530SRussell King - ARM Linux on_each_cpu(mvneta_percpu_disable, pp, true); 448712bb03b4SMaxime Ripard free_percpu_irq(pp->dev->irq, pp->ports); 44882636ac3cSMarcin Wojtas } 4489c5aff182SThomas Petazzoni err_cleanup_txqs: 4490c5aff182SThomas Petazzoni mvneta_cleanup_txqs(pp); 4491c5aff182SThomas Petazzoni err_cleanup_rxqs: 4492c5aff182SThomas Petazzoni mvneta_cleanup_rxqs(pp); 4493c5aff182SThomas Petazzoni return ret; 4494c5aff182SThomas Petazzoni } 4495c5aff182SThomas Petazzoni 4496c5aff182SThomas Petazzoni /* Stop the port, free port interrupt line */ 4497c5aff182SThomas Petazzoni static int mvneta_stop(struct net_device *dev) 4498c5aff182SThomas Petazzoni { 4499c5aff182SThomas Petazzoni struct mvneta_port *pp = netdev_priv(dev); 4500c5aff182SThomas Petazzoni 45012636ac3cSMarcin Wojtas if (!pp->neta_armada3700) { 4502120cfa50SGregory CLEMENT /* Inform that we are stopping so we don't want to setup the 45031c2722a9SGregory CLEMENT * driver for new CPUs in the notifiers. The code of the 45041c2722a9SGregory CLEMENT * notifier for CPU online is protected by the same spinlock, 45051c2722a9SGregory CLEMENT * so when we get the lock, the notifer work is done. 4506120cfa50SGregory CLEMENT */ 4507120cfa50SGregory CLEMENT spin_lock(&pp->lock); 4508120cfa50SGregory CLEMENT pp->is_stopped = true; 45091c2722a9SGregory CLEMENT spin_unlock(&pp->lock); 45101c2722a9SGregory CLEMENT 4511c5aff182SThomas Petazzoni mvneta_stop_dev(pp); 4512c5aff182SThomas Petazzoni mvneta_mdio_remove(pp); 451384a3f4dbSSebastian Andrzej Siewior 4514d26aac2dSDan Carpenter cpuhp_state_remove_instance_nocalls(online_hpstate, 4515d26aac2dSDan Carpenter &pp->node_online); 451684a3f4dbSSebastian Andrzej Siewior cpuhp_state_remove_instance_nocalls(CPUHP_NET_MVNETA_DEAD, 451784a3f4dbSSebastian Andrzej Siewior &pp->node_dead); 4518129219e4SGregory CLEMENT on_each_cpu(mvneta_percpu_disable, pp, true); 451912bb03b4SMaxime Ripard free_percpu_irq(dev->irq, pp->ports); 45202636ac3cSMarcin Wojtas } else { 45212636ac3cSMarcin Wojtas mvneta_stop_dev(pp); 45222636ac3cSMarcin Wojtas mvneta_mdio_remove(pp); 45232636ac3cSMarcin Wojtas free_irq(dev->irq, pp); 45242636ac3cSMarcin Wojtas } 45252636ac3cSMarcin Wojtas 4526c5aff182SThomas Petazzoni mvneta_cleanup_rxqs(pp); 4527c5aff182SThomas Petazzoni mvneta_cleanup_txqs(pp); 4528c5aff182SThomas Petazzoni 4529c5aff182SThomas Petazzoni return 0; 4530c5aff182SThomas Petazzoni } 4531c5aff182SThomas Petazzoni 453215f59456SThomas Petazzoni static int mvneta_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) 453315f59456SThomas Petazzoni { 4534503f9aa9SRussell King struct mvneta_port *pp = netdev_priv(dev); 453515f59456SThomas Petazzoni 4536503f9aa9SRussell King return phylink_mii_ioctl(pp->phylink, ifr, cmd); 453715f59456SThomas Petazzoni } 453815f59456SThomas Petazzoni 45390db51da7SLorenzo Bianconi static int mvneta_xdp_setup(struct net_device *dev, struct bpf_prog *prog, 45400db51da7SLorenzo Bianconi struct netlink_ext_ack *extack) 45410db51da7SLorenzo Bianconi { 45420db51da7SLorenzo Bianconi bool need_update, running = netif_running(dev); 45430db51da7SLorenzo Bianconi struct mvneta_port *pp = netdev_priv(dev); 45440db51da7SLorenzo Bianconi struct bpf_prog *old_prog; 45450db51da7SLorenzo Bianconi 4546e121d270SLorenzo Bianconi if (prog && !prog->aux->xdp_has_frags && 4547e121d270SLorenzo Bianconi dev->mtu > MVNETA_MAX_RX_BUF_SIZE) { 4548e121d270SLorenzo Bianconi NL_SET_ERR_MSG_MOD(extack, "prog does not support XDP frags"); 45490db51da7SLorenzo Bianconi return -EOPNOTSUPP; 45500db51da7SLorenzo Bianconi } 45510db51da7SLorenzo Bianconi 455279572c98SSven Auhagen if (pp->bm_priv) { 455379572c98SSven Auhagen NL_SET_ERR_MSG_MOD(extack, 455479572c98SSven Auhagen "Hardware Buffer Management not supported on XDP"); 455579572c98SSven Auhagen return -EOPNOTSUPP; 455679572c98SSven Auhagen } 455779572c98SSven Auhagen 45580db51da7SLorenzo Bianconi need_update = !!pp->xdp_prog != !!prog; 45590db51da7SLorenzo Bianconi if (running && need_update) 45600db51da7SLorenzo Bianconi mvneta_stop(dev); 45610db51da7SLorenzo Bianconi 45620db51da7SLorenzo Bianconi old_prog = xchg(&pp->xdp_prog, prog); 45630db51da7SLorenzo Bianconi if (old_prog) 45640db51da7SLorenzo Bianconi bpf_prog_put(old_prog); 45650db51da7SLorenzo Bianconi 45660db51da7SLorenzo Bianconi if (running && need_update) 45670db51da7SLorenzo Bianconi return mvneta_open(dev); 45680db51da7SLorenzo Bianconi 45690db51da7SLorenzo Bianconi return 0; 45700db51da7SLorenzo Bianconi } 45710db51da7SLorenzo Bianconi 45720db51da7SLorenzo Bianconi static int mvneta_xdp(struct net_device *dev, struct netdev_bpf *xdp) 45730db51da7SLorenzo Bianconi { 45740db51da7SLorenzo Bianconi switch (xdp->command) { 45750db51da7SLorenzo Bianconi case XDP_SETUP_PROG: 45760db51da7SLorenzo Bianconi return mvneta_xdp_setup(dev, xdp->prog, xdp->extack); 45770db51da7SLorenzo Bianconi default: 45780db51da7SLorenzo Bianconi return -EINVAL; 45790db51da7SLorenzo Bianconi } 45800db51da7SLorenzo Bianconi } 45810db51da7SLorenzo Bianconi 4582c5aff182SThomas Petazzoni /* Ethtool methods */ 4583c5aff182SThomas Petazzoni 4584013ad40dSPhilippe Reynes /* Set link ksettings (phy address, speed) for ethtools */ 45852dc0d2b4SBaoyou Xie static int 45862dc0d2b4SBaoyou Xie mvneta_ethtool_set_link_ksettings(struct net_device *ndev, 4587013ad40dSPhilippe Reynes const struct ethtool_link_ksettings *cmd) 4588c5aff182SThomas Petazzoni { 4589013ad40dSPhilippe Reynes struct mvneta_port *pp = netdev_priv(ndev); 4590c5aff182SThomas Petazzoni 4591503f9aa9SRussell King return phylink_ethtool_ksettings_set(pp->phylink, cmd); 45920c0744fcSStas Sergeev } 45930c0744fcSStas Sergeev 4594503f9aa9SRussell King /* Get link ksettings for ethtools */ 4595503f9aa9SRussell King static int 4596503f9aa9SRussell King mvneta_ethtool_get_link_ksettings(struct net_device *ndev, 4597503f9aa9SRussell King struct ethtool_link_ksettings *cmd) 4598503f9aa9SRussell King { 4599503f9aa9SRussell King struct mvneta_port *pp = netdev_priv(ndev); 46000c0744fcSStas Sergeev 4601503f9aa9SRussell King return phylink_ethtool_ksettings_get(pp->phylink, cmd); 46020c0744fcSStas Sergeev } 46030c0744fcSStas Sergeev 4604503f9aa9SRussell King static int mvneta_ethtool_nway_reset(struct net_device *dev) 4605503f9aa9SRussell King { 4606503f9aa9SRussell King struct mvneta_port *pp = netdev_priv(dev); 4607503f9aa9SRussell King 4608503f9aa9SRussell King return phylink_ethtool_nway_reset(pp->phylink); 4609c5aff182SThomas Petazzoni } 4610c5aff182SThomas Petazzoni 4611c5aff182SThomas Petazzoni /* Set interrupt coalescing for ethtools */ 4612f3ccfda1SYufeng Mo static int 4613f3ccfda1SYufeng Mo mvneta_ethtool_set_coalesce(struct net_device *dev, 4614f3ccfda1SYufeng Mo struct ethtool_coalesce *c, 4615f3ccfda1SYufeng Mo struct kernel_ethtool_coalesce *kernel_coal, 4616f3ccfda1SYufeng Mo struct netlink_ext_ack *extack) 4617c5aff182SThomas Petazzoni { 4618c5aff182SThomas Petazzoni struct mvneta_port *pp = netdev_priv(dev); 4619c5aff182SThomas Petazzoni int queue; 4620c5aff182SThomas Petazzoni 4621c5aff182SThomas Petazzoni for (queue = 0; queue < rxq_number; queue++) { 4622c5aff182SThomas Petazzoni struct mvneta_rx_queue *rxq = &pp->rxqs[queue]; 4623c5aff182SThomas Petazzoni rxq->time_coal = c->rx_coalesce_usecs; 4624c5aff182SThomas Petazzoni rxq->pkts_coal = c->rx_max_coalesced_frames; 4625c5aff182SThomas Petazzoni mvneta_rx_pkts_coal_set(pp, rxq, rxq->pkts_coal); 4626c5aff182SThomas Petazzoni mvneta_rx_time_coal_set(pp, rxq, rxq->time_coal); 4627c5aff182SThomas Petazzoni } 4628c5aff182SThomas Petazzoni 4629c5aff182SThomas Petazzoni for (queue = 0; queue < txq_number; queue++) { 4630c5aff182SThomas Petazzoni struct mvneta_tx_queue *txq = &pp->txqs[queue]; 4631c5aff182SThomas Petazzoni txq->done_pkts_coal = c->tx_max_coalesced_frames; 4632c5aff182SThomas Petazzoni mvneta_tx_done_pkts_coal_set(pp, txq, txq->done_pkts_coal); 4633c5aff182SThomas Petazzoni } 4634c5aff182SThomas Petazzoni 4635c5aff182SThomas Petazzoni return 0; 4636c5aff182SThomas Petazzoni } 4637c5aff182SThomas Petazzoni 4638c5aff182SThomas Petazzoni /* get coalescing for ethtools */ 4639f3ccfda1SYufeng Mo static int 4640f3ccfda1SYufeng Mo mvneta_ethtool_get_coalesce(struct net_device *dev, 4641f3ccfda1SYufeng Mo struct ethtool_coalesce *c, 4642f3ccfda1SYufeng Mo struct kernel_ethtool_coalesce *kernel_coal, 4643f3ccfda1SYufeng Mo struct netlink_ext_ack *extack) 4644c5aff182SThomas Petazzoni { 4645c5aff182SThomas Petazzoni struct mvneta_port *pp = netdev_priv(dev); 4646c5aff182SThomas Petazzoni 4647c5aff182SThomas Petazzoni c->rx_coalesce_usecs = pp->rxqs[0].time_coal; 4648c5aff182SThomas Petazzoni c->rx_max_coalesced_frames = pp->rxqs[0].pkts_coal; 4649c5aff182SThomas Petazzoni 4650c5aff182SThomas Petazzoni c->tx_max_coalesced_frames = pp->txqs[0].done_pkts_coal; 4651c5aff182SThomas Petazzoni return 0; 4652c5aff182SThomas Petazzoni } 4653c5aff182SThomas Petazzoni 4654c5aff182SThomas Petazzoni 4655c5aff182SThomas Petazzoni static void mvneta_ethtool_get_drvinfo(struct net_device *dev, 4656c5aff182SThomas Petazzoni struct ethtool_drvinfo *drvinfo) 4657c5aff182SThomas Petazzoni { 4658f029c781SWolfram Sang strscpy(drvinfo->driver, MVNETA_DRIVER_NAME, 4659c5aff182SThomas Petazzoni sizeof(drvinfo->driver)); 4660f029c781SWolfram Sang strscpy(drvinfo->version, MVNETA_DRIVER_VERSION, 4661c5aff182SThomas Petazzoni sizeof(drvinfo->version)); 4662f029c781SWolfram Sang strscpy(drvinfo->bus_info, dev_name(&dev->dev), 4663c5aff182SThomas Petazzoni sizeof(drvinfo->bus_info)); 4664c5aff182SThomas Petazzoni } 4665c5aff182SThomas Petazzoni 4666c5aff182SThomas Petazzoni 466774624944SHao Chen static void 466874624944SHao Chen mvneta_ethtool_get_ringparam(struct net_device *netdev, 466974624944SHao Chen struct ethtool_ringparam *ring, 467074624944SHao Chen struct kernel_ethtool_ringparam *kernel_ring, 467174624944SHao Chen struct netlink_ext_ack *extack) 4672c5aff182SThomas Petazzoni { 4673c5aff182SThomas Petazzoni struct mvneta_port *pp = netdev_priv(netdev); 4674c5aff182SThomas Petazzoni 4675c5aff182SThomas Petazzoni ring->rx_max_pending = MVNETA_MAX_RXD; 4676c5aff182SThomas Petazzoni ring->tx_max_pending = MVNETA_MAX_TXD; 4677c5aff182SThomas Petazzoni ring->rx_pending = pp->rx_ring_size; 4678c5aff182SThomas Petazzoni ring->tx_pending = pp->tx_ring_size; 4679c5aff182SThomas Petazzoni } 4680c5aff182SThomas Petazzoni 468174624944SHao Chen static int 468274624944SHao Chen mvneta_ethtool_set_ringparam(struct net_device *dev, 468374624944SHao Chen struct ethtool_ringparam *ring, 468474624944SHao Chen struct kernel_ethtool_ringparam *kernel_ring, 468574624944SHao Chen struct netlink_ext_ack *extack) 4686c5aff182SThomas Petazzoni { 4687c5aff182SThomas Petazzoni struct mvneta_port *pp = netdev_priv(dev); 4688c5aff182SThomas Petazzoni 4689c5aff182SThomas Petazzoni if ((ring->rx_pending == 0) || (ring->tx_pending == 0)) 4690c5aff182SThomas Petazzoni return -EINVAL; 4691c5aff182SThomas Petazzoni pp->rx_ring_size = ring->rx_pending < MVNETA_MAX_RXD ? 4692c5aff182SThomas Petazzoni ring->rx_pending : MVNETA_MAX_RXD; 46938eef5f97SEzequiel Garcia 46948eef5f97SEzequiel Garcia pp->tx_ring_size = clamp_t(u16, ring->tx_pending, 46958eef5f97SEzequiel Garcia MVNETA_MAX_SKB_DESCS * 2, MVNETA_MAX_TXD); 46968eef5f97SEzequiel Garcia if (pp->tx_ring_size != ring->tx_pending) 46978eef5f97SEzequiel Garcia netdev_warn(dev, "TX queue size set to %u (requested %u)\n", 46988eef5f97SEzequiel Garcia pp->tx_ring_size, ring->tx_pending); 4699c5aff182SThomas Petazzoni 4700c5aff182SThomas Petazzoni if (netif_running(dev)) { 4701c5aff182SThomas Petazzoni mvneta_stop(dev); 4702c5aff182SThomas Petazzoni if (mvneta_open(dev)) { 4703c5aff182SThomas Petazzoni netdev_err(dev, 4704c5aff182SThomas Petazzoni "error on opening device after ring param change\n"); 4705c5aff182SThomas Petazzoni return -ENOMEM; 4706c5aff182SThomas Petazzoni } 4707c5aff182SThomas Petazzoni } 4708c5aff182SThomas Petazzoni 4709c5aff182SThomas Petazzoni return 0; 4710c5aff182SThomas Petazzoni } 4711c5aff182SThomas Petazzoni 47124932a918SRussell King static void mvneta_ethtool_get_pauseparam(struct net_device *dev, 47134932a918SRussell King struct ethtool_pauseparam *pause) 47144932a918SRussell King { 47154932a918SRussell King struct mvneta_port *pp = netdev_priv(dev); 47164932a918SRussell King 47174932a918SRussell King phylink_ethtool_get_pauseparam(pp->phylink, pause); 47184932a918SRussell King } 47194932a918SRussell King 47204932a918SRussell King static int mvneta_ethtool_set_pauseparam(struct net_device *dev, 47214932a918SRussell King struct ethtool_pauseparam *pause) 47224932a918SRussell King { 47234932a918SRussell King struct mvneta_port *pp = netdev_priv(dev); 47244932a918SRussell King 47254932a918SRussell King return phylink_ethtool_set_pauseparam(pp->phylink, pause); 47264932a918SRussell King } 47274932a918SRussell King 47289b0cdefaSRussell King static void mvneta_ethtool_get_strings(struct net_device *netdev, u32 sset, 47299b0cdefaSRussell King u8 *data) 47309b0cdefaSRussell King { 47319b0cdefaSRussell King if (sset == ETH_SS_STATS) { 47329b0cdefaSRussell King int i; 47339b0cdefaSRussell King 47349b0cdefaSRussell King for (i = 0; i < ARRAY_SIZE(mvneta_statistics); i++) 47359b0cdefaSRussell King memcpy(data + i * ETH_GSTRING_LEN, 47369b0cdefaSRussell King mvneta_statistics[i].name, ETH_GSTRING_LEN); 4737b3fc7922SLorenzo Bianconi 4738b3fc7922SLorenzo Bianconi data += ETH_GSTRING_LEN * ARRAY_SIZE(mvneta_statistics); 4739b3fc7922SLorenzo Bianconi page_pool_ethtool_stats_get_strings(data); 47409b0cdefaSRussell King } 47419b0cdefaSRussell King } 47429b0cdefaSRussell King 47439ac41f3cSLorenzo Bianconi static void 47449ac41f3cSLorenzo Bianconi mvneta_ethtool_update_pcpu_stats(struct mvneta_port *pp, 47459ac41f3cSLorenzo Bianconi struct mvneta_ethtool_stats *es) 47469ac41f3cSLorenzo Bianconi { 47479ac41f3cSLorenzo Bianconi unsigned int start; 47489ac41f3cSLorenzo Bianconi int cpu; 47499ac41f3cSLorenzo Bianconi 47509ac41f3cSLorenzo Bianconi for_each_possible_cpu(cpu) { 47519ac41f3cSLorenzo Bianconi struct mvneta_pcpu_stats *stats; 47529ac41f3cSLorenzo Bianconi u64 skb_alloc_error; 47539ac41f3cSLorenzo Bianconi u64 refill_error; 47543d866523SLorenzo Bianconi u64 xdp_redirect; 475515070919SJesper Dangaard Brouer u64 xdp_xmit_err; 475615070919SJesper Dangaard Brouer u64 xdp_tx_err; 47573d866523SLorenzo Bianconi u64 xdp_pass; 47583d866523SLorenzo Bianconi u64 xdp_drop; 47597d51a015SLorenzo Bianconi u64 xdp_xmit; 47603d866523SLorenzo Bianconi u64 xdp_tx; 47619ac41f3cSLorenzo Bianconi 47629ac41f3cSLorenzo Bianconi stats = per_cpu_ptr(pp->stats, cpu); 47639ac41f3cSLorenzo Bianconi do { 4764068c38adSThomas Gleixner start = u64_stats_fetch_begin(&stats->syncp); 47659ac41f3cSLorenzo Bianconi skb_alloc_error = stats->es.skb_alloc_error; 47669ac41f3cSLorenzo Bianconi refill_error = stats->es.refill_error; 47673d866523SLorenzo Bianconi xdp_redirect = stats->es.ps.xdp_redirect; 47683d866523SLorenzo Bianconi xdp_pass = stats->es.ps.xdp_pass; 47693d866523SLorenzo Bianconi xdp_drop = stats->es.ps.xdp_drop; 47707d51a015SLorenzo Bianconi xdp_xmit = stats->es.ps.xdp_xmit; 477115070919SJesper Dangaard Brouer xdp_xmit_err = stats->es.ps.xdp_xmit_err; 47723d866523SLorenzo Bianconi xdp_tx = stats->es.ps.xdp_tx; 477315070919SJesper Dangaard Brouer xdp_tx_err = stats->es.ps.xdp_tx_err; 4774068c38adSThomas Gleixner } while (u64_stats_fetch_retry(&stats->syncp, start)); 47759ac41f3cSLorenzo Bianconi 47769ac41f3cSLorenzo Bianconi es->skb_alloc_error += skb_alloc_error; 47779ac41f3cSLorenzo Bianconi es->refill_error += refill_error; 47783d866523SLorenzo Bianconi es->ps.xdp_redirect += xdp_redirect; 47793d866523SLorenzo Bianconi es->ps.xdp_pass += xdp_pass; 47803d866523SLorenzo Bianconi es->ps.xdp_drop += xdp_drop; 47817d51a015SLorenzo Bianconi es->ps.xdp_xmit += xdp_xmit; 478215070919SJesper Dangaard Brouer es->ps.xdp_xmit_err += xdp_xmit_err; 47833d866523SLorenzo Bianconi es->ps.xdp_tx += xdp_tx; 478415070919SJesper Dangaard Brouer es->ps.xdp_tx_err += xdp_tx_err; 47859ac41f3cSLorenzo Bianconi } 47869ac41f3cSLorenzo Bianconi } 47879ac41f3cSLorenzo Bianconi 47889b0cdefaSRussell King static void mvneta_ethtool_update_stats(struct mvneta_port *pp) 47899b0cdefaSRussell King { 47909ac41f3cSLorenzo Bianconi struct mvneta_ethtool_stats stats = {}; 47919b0cdefaSRussell King const struct mvneta_statistic *s; 47929b0cdefaSRussell King void __iomem *base = pp->base; 47936d81f451SRussell King u32 high, low; 47946d81f451SRussell King u64 val; 47959b0cdefaSRussell King int i; 47969b0cdefaSRussell King 47979ac41f3cSLorenzo Bianconi mvneta_ethtool_update_pcpu_stats(pp, &stats); 47989b0cdefaSRussell King for (i = 0, s = mvneta_statistics; 47999b0cdefaSRussell King s < mvneta_statistics + ARRAY_SIZE(mvneta_statistics); 48009b0cdefaSRussell King s++, i++) { 48019b0cdefaSRussell King switch (s->type) { 48029b0cdefaSRussell King case T_REG_32: 48039b0cdefaSRussell King val = readl_relaxed(base + s->offset); 48049ac41f3cSLorenzo Bianconi pp->ethtool_stats[i] += val; 48059b0cdefaSRussell King break; 48069b0cdefaSRussell King case T_REG_64: 48079b0cdefaSRussell King /* Docs say to read low 32-bit then high */ 48089b0cdefaSRussell King low = readl_relaxed(base + s->offset); 48099b0cdefaSRussell King high = readl_relaxed(base + s->offset + 4); 48106d81f451SRussell King val = (u64)high << 32 | low; 48119ac41f3cSLorenzo Bianconi pp->ethtool_stats[i] += val; 48126d81f451SRussell King break; 48136d81f451SRussell King case T_SW: 48146d81f451SRussell King switch (s->offset) { 48156d81f451SRussell King case ETHTOOL_STAT_EEE_WAKEUP: 48166d81f451SRussell King val = phylink_get_eee_err(pp->phylink); 48179ac41f3cSLorenzo Bianconi pp->ethtool_stats[i] += val; 48189b0cdefaSRussell King break; 481917a96da6SGregory CLEMENT case ETHTOOL_STAT_SKB_ALLOC_ERR: 48209ac41f3cSLorenzo Bianconi pp->ethtool_stats[i] = stats.skb_alloc_error; 482117a96da6SGregory CLEMENT break; 482217a96da6SGregory CLEMENT case ETHTOOL_STAT_REFILL_ERR: 48239ac41f3cSLorenzo Bianconi pp->ethtool_stats[i] = stats.refill_error; 482417a96da6SGregory CLEMENT break; 48253d866523SLorenzo Bianconi case ETHTOOL_XDP_REDIRECT: 48263d866523SLorenzo Bianconi pp->ethtool_stats[i] = stats.ps.xdp_redirect; 48273d866523SLorenzo Bianconi break; 48283d866523SLorenzo Bianconi case ETHTOOL_XDP_PASS: 48293d866523SLorenzo Bianconi pp->ethtool_stats[i] = stats.ps.xdp_pass; 48303d866523SLorenzo Bianconi break; 48313d866523SLorenzo Bianconi case ETHTOOL_XDP_DROP: 48323d866523SLorenzo Bianconi pp->ethtool_stats[i] = stats.ps.xdp_drop; 48333d866523SLorenzo Bianconi break; 48343d866523SLorenzo Bianconi case ETHTOOL_XDP_TX: 48353d866523SLorenzo Bianconi pp->ethtool_stats[i] = stats.ps.xdp_tx; 48363d866523SLorenzo Bianconi break; 483715070919SJesper Dangaard Brouer case ETHTOOL_XDP_TX_ERR: 483815070919SJesper Dangaard Brouer pp->ethtool_stats[i] = stats.ps.xdp_tx_err; 483915070919SJesper Dangaard Brouer break; 48407d51a015SLorenzo Bianconi case ETHTOOL_XDP_XMIT: 48417d51a015SLorenzo Bianconi pp->ethtool_stats[i] = stats.ps.xdp_xmit; 48427d51a015SLorenzo Bianconi break; 484315070919SJesper Dangaard Brouer case ETHTOOL_XDP_XMIT_ERR: 484415070919SJesper Dangaard Brouer pp->ethtool_stats[i] = stats.ps.xdp_xmit_err; 484515070919SJesper Dangaard Brouer break; 48469b0cdefaSRussell King } 48476d81f451SRussell King break; 48486d81f451SRussell King } 48499b0cdefaSRussell King } 48509b0cdefaSRussell King } 48519b0cdefaSRussell King 4852b3fc7922SLorenzo Bianconi static void mvneta_ethtool_pp_stats(struct mvneta_port *pp, u64 *data) 4853b3fc7922SLorenzo Bianconi { 4854b3fc7922SLorenzo Bianconi struct page_pool_stats stats = {}; 4855b3fc7922SLorenzo Bianconi int i; 4856b3fc7922SLorenzo Bianconi 4857b3fc7922SLorenzo Bianconi for (i = 0; i < rxq_number; i++) 4858b3fc7922SLorenzo Bianconi page_pool_get_stats(pp->rxqs[i].page_pool, &stats); 4859b3fc7922SLorenzo Bianconi 4860b3fc7922SLorenzo Bianconi page_pool_ethtool_stats_get(data, &stats); 4861b3fc7922SLorenzo Bianconi } 4862b3fc7922SLorenzo Bianconi 48639b0cdefaSRussell King static void mvneta_ethtool_get_stats(struct net_device *dev, 48649b0cdefaSRussell King struct ethtool_stats *stats, u64 *data) 48659b0cdefaSRussell King { 48669b0cdefaSRussell King struct mvneta_port *pp = netdev_priv(dev); 48679b0cdefaSRussell King int i; 48689b0cdefaSRussell King 48699b0cdefaSRussell King mvneta_ethtool_update_stats(pp); 48709b0cdefaSRussell King 48719b0cdefaSRussell King for (i = 0; i < ARRAY_SIZE(mvneta_statistics); i++) 48729b0cdefaSRussell King *data++ = pp->ethtool_stats[i]; 4873b3fc7922SLorenzo Bianconi 4874b3fc7922SLorenzo Bianconi mvneta_ethtool_pp_stats(pp, data); 48759b0cdefaSRussell King } 48769b0cdefaSRussell King 48779b0cdefaSRussell King static int mvneta_ethtool_get_sset_count(struct net_device *dev, int sset) 48789b0cdefaSRussell King { 48799b0cdefaSRussell King if (sset == ETH_SS_STATS) 4880b3fc7922SLorenzo Bianconi return ARRAY_SIZE(mvneta_statistics) + 4881b3fc7922SLorenzo Bianconi page_pool_ethtool_stats_get_count(); 4882b3fc7922SLorenzo Bianconi 48839b0cdefaSRussell King return -EOPNOTSUPP; 48849b0cdefaSRussell King } 48859b0cdefaSRussell King 48869a401deaSGregory CLEMENT static u32 mvneta_ethtool_get_rxfh_indir_size(struct net_device *dev) 48879a401deaSGregory CLEMENT { 48889a401deaSGregory CLEMENT return MVNETA_RSS_LU_TABLE_SIZE; 48899a401deaSGregory CLEMENT } 48909a401deaSGregory CLEMENT 48919a401deaSGregory CLEMENT static int mvneta_ethtool_get_rxnfc(struct net_device *dev, 48929a401deaSGregory CLEMENT struct ethtool_rxnfc *info, 48939a401deaSGregory CLEMENT u32 *rules __always_unused) 48949a401deaSGregory CLEMENT { 48959a401deaSGregory CLEMENT switch (info->cmd) { 48969a401deaSGregory CLEMENT case ETHTOOL_GRXRINGS: 48979a401deaSGregory CLEMENT info->data = rxq_number; 48989a401deaSGregory CLEMENT return 0; 48999a401deaSGregory CLEMENT case ETHTOOL_GRXFH: 49009a401deaSGregory CLEMENT return -EOPNOTSUPP; 49019a401deaSGregory CLEMENT default: 49029a401deaSGregory CLEMENT return -EOPNOTSUPP; 49039a401deaSGregory CLEMENT } 49049a401deaSGregory CLEMENT } 49059a401deaSGregory CLEMENT 49069a401deaSGregory CLEMENT static int mvneta_config_rss(struct mvneta_port *pp) 49079a401deaSGregory CLEMENT { 49089a401deaSGregory CLEMENT int cpu; 49099a401deaSGregory CLEMENT u32 val; 49109a401deaSGregory CLEMENT 49119a401deaSGregory CLEMENT netif_tx_stop_all_queues(pp->dev); 49129a401deaSGregory CLEMENT 49136b125d63SGregory CLEMENT on_each_cpu(mvneta_percpu_mask_interrupt, pp, true); 49149a401deaSGregory CLEMENT 49150f5c6c30SJisheng Zhang if (!pp->neta_armada3700) { 49169a401deaSGregory CLEMENT /* We have to synchronise on the napi of each CPU */ 49179a401deaSGregory CLEMENT for_each_online_cpu(cpu) { 49189a401deaSGregory CLEMENT struct mvneta_pcpu_port *pcpu_port = 49199a401deaSGregory CLEMENT per_cpu_ptr(pp->ports, cpu); 49209a401deaSGregory CLEMENT 49219a401deaSGregory CLEMENT napi_synchronize(&pcpu_port->napi); 49229a401deaSGregory CLEMENT napi_disable(&pcpu_port->napi); 49239a401deaSGregory CLEMENT } 49240f5c6c30SJisheng Zhang } else { 49250f5c6c30SJisheng Zhang napi_synchronize(&pp->napi); 49260f5c6c30SJisheng Zhang napi_disable(&pp->napi); 49270f5c6c30SJisheng Zhang } 49289a401deaSGregory CLEMENT 49299a401deaSGregory CLEMENT pp->rxq_def = pp->indir[0]; 49309a401deaSGregory CLEMENT 49319a401deaSGregory CLEMENT /* Update unicast mapping */ 49329a401deaSGregory CLEMENT mvneta_set_rx_mode(pp->dev); 49339a401deaSGregory CLEMENT 49349a401deaSGregory CLEMENT /* Update val of portCfg register accordingly with all RxQueue types */ 49359a401deaSGregory CLEMENT val = MVNETA_PORT_CONFIG_DEFL_VALUE(pp->rxq_def); 49369a401deaSGregory CLEMENT mvreg_write(pp, MVNETA_PORT_CONFIG, val); 49379a401deaSGregory CLEMENT 49389a401deaSGregory CLEMENT /* Update the elected CPU matching the new rxq_def */ 4939120cfa50SGregory CLEMENT spin_lock(&pp->lock); 49409a401deaSGregory CLEMENT mvneta_percpu_elect(pp); 4941120cfa50SGregory CLEMENT spin_unlock(&pp->lock); 49429a401deaSGregory CLEMENT 49430f5c6c30SJisheng Zhang if (!pp->neta_armada3700) { 49449a401deaSGregory CLEMENT /* We have to synchronise on the napi of each CPU */ 49459a401deaSGregory CLEMENT for_each_online_cpu(cpu) { 49469a401deaSGregory CLEMENT struct mvneta_pcpu_port *pcpu_port = 49479a401deaSGregory CLEMENT per_cpu_ptr(pp->ports, cpu); 49489a401deaSGregory CLEMENT 49499a401deaSGregory CLEMENT napi_enable(&pcpu_port->napi); 49509a401deaSGregory CLEMENT } 49510f5c6c30SJisheng Zhang } else { 49520f5c6c30SJisheng Zhang napi_enable(&pp->napi); 49530f5c6c30SJisheng Zhang } 49549a401deaSGregory CLEMENT 49559a401deaSGregory CLEMENT netif_tx_start_all_queues(pp->dev); 49569a401deaSGregory CLEMENT 49579a401deaSGregory CLEMENT return 0; 49589a401deaSGregory CLEMENT } 49599a401deaSGregory CLEMENT 49609a401deaSGregory CLEMENT static int mvneta_ethtool_set_rxfh(struct net_device *dev, const u32 *indir, 49619a401deaSGregory CLEMENT const u8 *key, const u8 hfunc) 49629a401deaSGregory CLEMENT { 49639a401deaSGregory CLEMENT struct mvneta_port *pp = netdev_priv(dev); 49642636ac3cSMarcin Wojtas 49652636ac3cSMarcin Wojtas /* Current code for Armada 3700 doesn't support RSS features yet */ 49662636ac3cSMarcin Wojtas if (pp->neta_armada3700) 49672636ac3cSMarcin Wojtas return -EOPNOTSUPP; 49682636ac3cSMarcin Wojtas 49699a401deaSGregory CLEMENT /* We require at least one supported parameter to be changed 49709a401deaSGregory CLEMENT * and no change in any of the unsupported parameters 49719a401deaSGregory CLEMENT */ 49729a401deaSGregory CLEMENT if (key || 49739a401deaSGregory CLEMENT (hfunc != ETH_RSS_HASH_NO_CHANGE && hfunc != ETH_RSS_HASH_TOP)) 49749a401deaSGregory CLEMENT return -EOPNOTSUPP; 49759a401deaSGregory CLEMENT 49769a401deaSGregory CLEMENT if (!indir) 49779a401deaSGregory CLEMENT return 0; 49789a401deaSGregory CLEMENT 49799a401deaSGregory CLEMENT memcpy(pp->indir, indir, MVNETA_RSS_LU_TABLE_SIZE); 49809a401deaSGregory CLEMENT 49819a401deaSGregory CLEMENT return mvneta_config_rss(pp); 49829a401deaSGregory CLEMENT } 49839a401deaSGregory CLEMENT 49849a401deaSGregory CLEMENT static int mvneta_ethtool_get_rxfh(struct net_device *dev, u32 *indir, u8 *key, 49859a401deaSGregory CLEMENT u8 *hfunc) 49869a401deaSGregory CLEMENT { 49879a401deaSGregory CLEMENT struct mvneta_port *pp = netdev_priv(dev); 49889a401deaSGregory CLEMENT 49892636ac3cSMarcin Wojtas /* Current code for Armada 3700 doesn't support RSS features yet */ 49902636ac3cSMarcin Wojtas if (pp->neta_armada3700) 49912636ac3cSMarcin Wojtas return -EOPNOTSUPP; 49922636ac3cSMarcin Wojtas 49939a401deaSGregory CLEMENT if (hfunc) 49949a401deaSGregory CLEMENT *hfunc = ETH_RSS_HASH_TOP; 49959a401deaSGregory CLEMENT 49969a401deaSGregory CLEMENT if (!indir) 49979a401deaSGregory CLEMENT return 0; 49989a401deaSGregory CLEMENT 49999a401deaSGregory CLEMENT memcpy(indir, pp->indir, MVNETA_RSS_LU_TABLE_SIZE); 50009a401deaSGregory CLEMENT 50019a401deaSGregory CLEMENT return 0; 50029a401deaSGregory CLEMENT } 50039a401deaSGregory CLEMENT 5004b60a00f9SJingju Hou static void mvneta_ethtool_get_wol(struct net_device *dev, 5005b60a00f9SJingju Hou struct ethtool_wolinfo *wol) 5006b60a00f9SJingju Hou { 5007503f9aa9SRussell King struct mvneta_port *pp = netdev_priv(dev); 5008b60a00f9SJingju Hou 5009503f9aa9SRussell King phylink_ethtool_get_wol(pp->phylink, wol); 5010b60a00f9SJingju Hou } 5011b60a00f9SJingju Hou 5012b60a00f9SJingju Hou static int mvneta_ethtool_set_wol(struct net_device *dev, 5013b60a00f9SJingju Hou struct ethtool_wolinfo *wol) 5014b60a00f9SJingju Hou { 5015503f9aa9SRussell King struct mvneta_port *pp = netdev_priv(dev); 501682960fffSJisheng Zhang int ret; 501782960fffSJisheng Zhang 5018503f9aa9SRussell King ret = phylink_ethtool_set_wol(pp->phylink, wol); 501982960fffSJisheng Zhang if (!ret) 502082960fffSJisheng Zhang device_set_wakeup_enable(&dev->dev, !!wol->wolopts); 502182960fffSJisheng Zhang 502282960fffSJisheng Zhang return ret; 5023b60a00f9SJingju Hou } 5024b60a00f9SJingju Hou 50256d81f451SRussell King static int mvneta_ethtool_get_eee(struct net_device *dev, 50266d81f451SRussell King struct ethtool_eee *eee) 50276d81f451SRussell King { 50286d81f451SRussell King struct mvneta_port *pp = netdev_priv(dev); 50296d81f451SRussell King u32 lpi_ctl0; 50306d81f451SRussell King 50316d81f451SRussell King lpi_ctl0 = mvreg_read(pp, MVNETA_LPI_CTRL_0); 50326d81f451SRussell King 50336d81f451SRussell King eee->eee_enabled = pp->eee_enabled; 50346d81f451SRussell King eee->eee_active = pp->eee_active; 50356d81f451SRussell King eee->tx_lpi_enabled = pp->tx_lpi_enabled; 50366d81f451SRussell King eee->tx_lpi_timer = (lpi_ctl0) >> 8; // * scale; 50376d81f451SRussell King 50386d81f451SRussell King return phylink_ethtool_get_eee(pp->phylink, eee); 50396d81f451SRussell King } 50406d81f451SRussell King 50416d81f451SRussell King static int mvneta_ethtool_set_eee(struct net_device *dev, 50426d81f451SRussell King struct ethtool_eee *eee) 50436d81f451SRussell King { 50446d81f451SRussell King struct mvneta_port *pp = netdev_priv(dev); 50456d81f451SRussell King u32 lpi_ctl0; 50466d81f451SRussell King 50476d81f451SRussell King /* The Armada 37x documents do not give limits for this other than 5048df4a17a9SYangyang Li * it being an 8-bit register. 5049df4a17a9SYangyang Li */ 5050e4a3e9ffSYueHaibing if (eee->tx_lpi_enabled && eee->tx_lpi_timer > 255) 50516d81f451SRussell King return -EINVAL; 50526d81f451SRussell King 50536d81f451SRussell King lpi_ctl0 = mvreg_read(pp, MVNETA_LPI_CTRL_0); 50546d81f451SRussell King lpi_ctl0 &= ~(0xff << 8); 50556d81f451SRussell King lpi_ctl0 |= eee->tx_lpi_timer << 8; 50566d81f451SRussell King mvreg_write(pp, MVNETA_LPI_CTRL_0, lpi_ctl0); 50576d81f451SRussell King 50586d81f451SRussell King pp->eee_enabled = eee->eee_enabled; 50596d81f451SRussell King pp->tx_lpi_enabled = eee->tx_lpi_enabled; 50606d81f451SRussell King 50616d81f451SRussell King mvneta_set_eee(pp, eee->tx_lpi_enabled && eee->eee_enabled); 50626d81f451SRussell King 50636d81f451SRussell King return phylink_ethtool_set_eee(pp->phylink, eee); 50646d81f451SRussell King } 50656d81f451SRussell King 50664906887aSMaxime Chevallier static void mvneta_clear_rx_prio_map(struct mvneta_port *pp) 50674906887aSMaxime Chevallier { 50684906887aSMaxime Chevallier mvreg_write(pp, MVNETA_VLAN_PRIO_TO_RXQ, 0); 50694906887aSMaxime Chevallier } 50704906887aSMaxime Chevallier 5071e9f7099dSMaxime Chevallier static void mvneta_map_vlan_prio_to_rxq(struct mvneta_port *pp, u8 pri, u8 rxq) 50724906887aSMaxime Chevallier { 5073e9f7099dSMaxime Chevallier u32 val = mvreg_read(pp, MVNETA_VLAN_PRIO_TO_RXQ); 50744906887aSMaxime Chevallier 5075e9f7099dSMaxime Chevallier val &= ~MVNETA_VLAN_PRIO_RXQ_MAP(pri, 0x7); 5076e9f7099dSMaxime Chevallier val |= MVNETA_VLAN_PRIO_RXQ_MAP(pri, rxq); 50774906887aSMaxime Chevallier 50784906887aSMaxime Chevallier mvreg_write(pp, MVNETA_VLAN_PRIO_TO_RXQ, val); 50794906887aSMaxime Chevallier } 50804906887aSMaxime Chevallier 50812551dc9eSMaxime Chevallier static int mvneta_enable_per_queue_rate_limit(struct mvneta_port *pp) 50822551dc9eSMaxime Chevallier { 50832551dc9eSMaxime Chevallier unsigned long core_clk_rate; 50842551dc9eSMaxime Chevallier u32 refill_cycles; 50852551dc9eSMaxime Chevallier u32 val; 50862551dc9eSMaxime Chevallier 50872551dc9eSMaxime Chevallier core_clk_rate = clk_get_rate(pp->clk); 50882551dc9eSMaxime Chevallier if (!core_clk_rate) 50892551dc9eSMaxime Chevallier return -EINVAL; 50902551dc9eSMaxime Chevallier 50912551dc9eSMaxime Chevallier refill_cycles = MVNETA_TXQ_BUCKET_REFILL_BASE_PERIOD_NS / 50922551dc9eSMaxime Chevallier (NSEC_PER_SEC / core_clk_rate); 50932551dc9eSMaxime Chevallier 50942551dc9eSMaxime Chevallier if (refill_cycles > MVNETA_REFILL_MAX_NUM_CLK) 50952551dc9eSMaxime Chevallier return -EINVAL; 50962551dc9eSMaxime Chevallier 50972551dc9eSMaxime Chevallier /* Enable bw limit algorithm version 3 */ 50982551dc9eSMaxime Chevallier val = mvreg_read(pp, MVNETA_TXQ_CMD1_REG); 50992551dc9eSMaxime Chevallier val &= ~(MVNETA_TXQ_CMD1_BW_LIM_SEL_V1 | MVNETA_TXQ_CMD1_BW_LIM_EN); 51002551dc9eSMaxime Chevallier mvreg_write(pp, MVNETA_TXQ_CMD1_REG, val); 51012551dc9eSMaxime Chevallier 51022551dc9eSMaxime Chevallier /* Set the base refill rate */ 51032551dc9eSMaxime Chevallier mvreg_write(pp, MVNETA_REFILL_NUM_CLK_REG, refill_cycles); 51042551dc9eSMaxime Chevallier 51052551dc9eSMaxime Chevallier return 0; 51062551dc9eSMaxime Chevallier } 51072551dc9eSMaxime Chevallier 51082551dc9eSMaxime Chevallier static void mvneta_disable_per_queue_rate_limit(struct mvneta_port *pp) 51092551dc9eSMaxime Chevallier { 51102551dc9eSMaxime Chevallier u32 val = mvreg_read(pp, MVNETA_TXQ_CMD1_REG); 51112551dc9eSMaxime Chevallier 51122551dc9eSMaxime Chevallier val |= (MVNETA_TXQ_CMD1_BW_LIM_SEL_V1 | MVNETA_TXQ_CMD1_BW_LIM_EN); 51132551dc9eSMaxime Chevallier mvreg_write(pp, MVNETA_TXQ_CMD1_REG, val); 51142551dc9eSMaxime Chevallier } 51152551dc9eSMaxime Chevallier 51162551dc9eSMaxime Chevallier static int mvneta_setup_queue_rates(struct mvneta_port *pp, int queue, 51172551dc9eSMaxime Chevallier u64 min_rate, u64 max_rate) 51182551dc9eSMaxime Chevallier { 51192551dc9eSMaxime Chevallier u32 refill_val, rem; 51202551dc9eSMaxime Chevallier u32 val = 0; 51212551dc9eSMaxime Chevallier 51222551dc9eSMaxime Chevallier /* Convert to from Bps to bps */ 51232551dc9eSMaxime Chevallier max_rate *= 8; 51242551dc9eSMaxime Chevallier 51252551dc9eSMaxime Chevallier if (min_rate) 51262551dc9eSMaxime Chevallier return -EINVAL; 51272551dc9eSMaxime Chevallier 51282551dc9eSMaxime Chevallier refill_val = div_u64_rem(max_rate, MVNETA_TXQ_RATE_LIMIT_RESOLUTION, 51292551dc9eSMaxime Chevallier &rem); 51302551dc9eSMaxime Chevallier 51312551dc9eSMaxime Chevallier if (rem || !refill_val || 51322551dc9eSMaxime Chevallier refill_val > MVNETA_TXQ_BUCKET_REFILL_VALUE_MAX) 51332551dc9eSMaxime Chevallier return -EINVAL; 51342551dc9eSMaxime Chevallier 51352551dc9eSMaxime Chevallier val = refill_val; 51362551dc9eSMaxime Chevallier val |= (MVNETA_TXQ_BUCKET_REFILL_PERIOD << 51372551dc9eSMaxime Chevallier MVNETA_TXQ_BUCKET_REFILL_PERIOD_SHIFT); 51382551dc9eSMaxime Chevallier 51392551dc9eSMaxime Chevallier mvreg_write(pp, MVNETA_TXQ_BUCKET_REFILL_REG(queue), val); 51402551dc9eSMaxime Chevallier 51412551dc9eSMaxime Chevallier return 0; 51422551dc9eSMaxime Chevallier } 51432551dc9eSMaxime Chevallier 51444906887aSMaxime Chevallier static int mvneta_setup_mqprio(struct net_device *dev, 514575fa71e3SMaxime Chevallier struct tc_mqprio_qopt_offload *mqprio) 51464906887aSMaxime Chevallier { 51474906887aSMaxime Chevallier struct mvneta_port *pp = netdev_priv(dev); 51482551dc9eSMaxime Chevallier int rxq, txq, tc, ret; 51494906887aSMaxime Chevallier u8 num_tc; 51504906887aSMaxime Chevallier 5151e7ca75feSMaxime Chevallier if (mqprio->qopt.hw != TC_MQPRIO_HW_OFFLOAD_TCS) 5152e7ca75feSMaxime Chevallier return 0; 5153e7ca75feSMaxime Chevallier 515475fa71e3SMaxime Chevallier num_tc = mqprio->qopt.num_tc; 51554906887aSMaxime Chevallier 51564906887aSMaxime Chevallier if (num_tc > rxq_number) 51574906887aSMaxime Chevallier return -EINVAL; 51584906887aSMaxime Chevallier 51594906887aSMaxime Chevallier mvneta_clear_rx_prio_map(pp); 5160e9f7099dSMaxime Chevallier 5161e9f7099dSMaxime Chevallier if (!num_tc) { 51622551dc9eSMaxime Chevallier mvneta_disable_per_queue_rate_limit(pp); 51634906887aSMaxime Chevallier netdev_reset_tc(dev); 51644906887aSMaxime Chevallier return 0; 51654906887aSMaxime Chevallier } 51664906887aSMaxime Chevallier 516775fa71e3SMaxime Chevallier netdev_set_num_tc(dev, mqprio->qopt.num_tc); 5168e9f7099dSMaxime Chevallier 5169e9f7099dSMaxime Chevallier for (tc = 0; tc < mqprio->qopt.num_tc; tc++) { 5170e9f7099dSMaxime Chevallier netdev_set_tc_queue(dev, tc, mqprio->qopt.count[tc], 5171e9f7099dSMaxime Chevallier mqprio->qopt.offset[tc]); 5172e9f7099dSMaxime Chevallier 5173e9f7099dSMaxime Chevallier for (rxq = mqprio->qopt.offset[tc]; 5174e9f7099dSMaxime Chevallier rxq < mqprio->qopt.count[tc] + mqprio->qopt.offset[tc]; 5175e9f7099dSMaxime Chevallier rxq++) { 5176e9f7099dSMaxime Chevallier if (rxq >= rxq_number) 5177e9f7099dSMaxime Chevallier return -EINVAL; 5178e9f7099dSMaxime Chevallier 5179e9f7099dSMaxime Chevallier mvneta_map_vlan_prio_to_rxq(pp, tc, rxq); 5180e9f7099dSMaxime Chevallier } 5181e9f7099dSMaxime Chevallier } 51824906887aSMaxime Chevallier 51832551dc9eSMaxime Chevallier if (mqprio->shaper != TC_MQPRIO_SHAPER_BW_RATE) { 51842551dc9eSMaxime Chevallier mvneta_disable_per_queue_rate_limit(pp); 51852551dc9eSMaxime Chevallier return 0; 51862551dc9eSMaxime Chevallier } 51872551dc9eSMaxime Chevallier 51882551dc9eSMaxime Chevallier if (mqprio->qopt.num_tc > txq_number) 51892551dc9eSMaxime Chevallier return -EINVAL; 51902551dc9eSMaxime Chevallier 51912551dc9eSMaxime Chevallier ret = mvneta_enable_per_queue_rate_limit(pp); 51922551dc9eSMaxime Chevallier if (ret) 51932551dc9eSMaxime Chevallier return ret; 51942551dc9eSMaxime Chevallier 51952551dc9eSMaxime Chevallier for (tc = 0; tc < mqprio->qopt.num_tc; tc++) { 51962551dc9eSMaxime Chevallier for (txq = mqprio->qopt.offset[tc]; 51972551dc9eSMaxime Chevallier txq < mqprio->qopt.count[tc] + mqprio->qopt.offset[tc]; 51982551dc9eSMaxime Chevallier txq++) { 51992551dc9eSMaxime Chevallier if (txq >= txq_number) 52002551dc9eSMaxime Chevallier return -EINVAL; 52012551dc9eSMaxime Chevallier 52022551dc9eSMaxime Chevallier ret = mvneta_setup_queue_rates(pp, txq, 52032551dc9eSMaxime Chevallier mqprio->min_rate[tc], 52042551dc9eSMaxime Chevallier mqprio->max_rate[tc]); 52052551dc9eSMaxime Chevallier if (ret) 52062551dc9eSMaxime Chevallier return ret; 52072551dc9eSMaxime Chevallier } 52082551dc9eSMaxime Chevallier } 52092551dc9eSMaxime Chevallier 52104906887aSMaxime Chevallier return 0; 52114906887aSMaxime Chevallier } 52124906887aSMaxime Chevallier 52134906887aSMaxime Chevallier static int mvneta_setup_tc(struct net_device *dev, enum tc_setup_type type, 52144906887aSMaxime Chevallier void *type_data) 52154906887aSMaxime Chevallier { 52164906887aSMaxime Chevallier switch (type) { 52174906887aSMaxime Chevallier case TC_SETUP_QDISC_MQPRIO: 52184906887aSMaxime Chevallier return mvneta_setup_mqprio(dev, type_data); 52194906887aSMaxime Chevallier default: 52204906887aSMaxime Chevallier return -EOPNOTSUPP; 52214906887aSMaxime Chevallier } 52224906887aSMaxime Chevallier } 52234906887aSMaxime Chevallier 5224c5aff182SThomas Petazzoni static const struct net_device_ops mvneta_netdev_ops = { 5225c5aff182SThomas Petazzoni .ndo_open = mvneta_open, 5226c5aff182SThomas Petazzoni .ndo_stop = mvneta_stop, 5227c5aff182SThomas Petazzoni .ndo_start_xmit = mvneta_tx, 5228c5aff182SThomas Petazzoni .ndo_set_rx_mode = mvneta_set_rx_mode, 5229c5aff182SThomas Petazzoni .ndo_set_mac_address = mvneta_set_mac_addr, 5230c5aff182SThomas Petazzoni .ndo_change_mtu = mvneta_change_mtu, 5231b65657fcSSimon Guinot .ndo_fix_features = mvneta_fix_features, 5232c5aff182SThomas Petazzoni .ndo_get_stats64 = mvneta_get_stats64, 5233a7605370SArnd Bergmann .ndo_eth_ioctl = mvneta_ioctl, 52340db51da7SLorenzo Bianconi .ndo_bpf = mvneta_xdp, 5235b0a43db9SLorenzo Bianconi .ndo_xdp_xmit = mvneta_xdp_xmit, 52364906887aSMaxime Chevallier .ndo_setup_tc = mvneta_setup_tc, 5237c5aff182SThomas Petazzoni }; 5238c5aff182SThomas Petazzoni 52394581be42SJisheng Zhang static const struct ethtool_ops mvneta_eth_tool_ops = { 524016e8d8b3SJakub Kicinski .supported_coalesce_params = ETHTOOL_COALESCE_RX_USECS | 524116e8d8b3SJakub Kicinski ETHTOOL_COALESCE_MAX_FRAMES, 5242503f9aa9SRussell King .nway_reset = mvneta_ethtool_nway_reset, 5243c5aff182SThomas Petazzoni .get_link = ethtool_op_get_link, 5244c5aff182SThomas Petazzoni .set_coalesce = mvneta_ethtool_set_coalesce, 5245c5aff182SThomas Petazzoni .get_coalesce = mvneta_ethtool_get_coalesce, 5246c5aff182SThomas Petazzoni .get_drvinfo = mvneta_ethtool_get_drvinfo, 5247c5aff182SThomas Petazzoni .get_ringparam = mvneta_ethtool_get_ringparam, 5248c5aff182SThomas Petazzoni .set_ringparam = mvneta_ethtool_set_ringparam, 52494932a918SRussell King .get_pauseparam = mvneta_ethtool_get_pauseparam, 52504932a918SRussell King .set_pauseparam = mvneta_ethtool_set_pauseparam, 52519b0cdefaSRussell King .get_strings = mvneta_ethtool_get_strings, 52529b0cdefaSRussell King .get_ethtool_stats = mvneta_ethtool_get_stats, 52539b0cdefaSRussell King .get_sset_count = mvneta_ethtool_get_sset_count, 52549a401deaSGregory CLEMENT .get_rxfh_indir_size = mvneta_ethtool_get_rxfh_indir_size, 52559a401deaSGregory CLEMENT .get_rxnfc = mvneta_ethtool_get_rxnfc, 52569a401deaSGregory CLEMENT .get_rxfh = mvneta_ethtool_get_rxfh, 52579a401deaSGregory CLEMENT .set_rxfh = mvneta_ethtool_set_rxfh, 5258503f9aa9SRussell King .get_link_ksettings = mvneta_ethtool_get_link_ksettings, 5259013ad40dSPhilippe Reynes .set_link_ksettings = mvneta_ethtool_set_link_ksettings, 5260b60a00f9SJingju Hou .get_wol = mvneta_ethtool_get_wol, 5261b60a00f9SJingju Hou .set_wol = mvneta_ethtool_set_wol, 52626d81f451SRussell King .get_eee = mvneta_ethtool_get_eee, 52636d81f451SRussell King .set_eee = mvneta_ethtool_set_eee, 5264c5aff182SThomas Petazzoni }; 5265c5aff182SThomas Petazzoni 5266c5aff182SThomas Petazzoni /* Initialize hw */ 52679672850bSEzequiel Garcia static int mvneta_init(struct device *dev, struct mvneta_port *pp) 5268c5aff182SThomas Petazzoni { 5269c5aff182SThomas Petazzoni int queue; 5270c5aff182SThomas Petazzoni 5271c5aff182SThomas Petazzoni /* Disable port */ 5272c5aff182SThomas Petazzoni mvneta_port_disable(pp); 5273c5aff182SThomas Petazzoni 5274c5aff182SThomas Petazzoni /* Set port default values */ 5275c5aff182SThomas Petazzoni mvneta_defaults_set(pp); 5276c5aff182SThomas Petazzoni 52775d6312edSMarkus Elfring pp->txqs = devm_kcalloc(dev, txq_number, sizeof(*pp->txqs), GFP_KERNEL); 5278c5aff182SThomas Petazzoni if (!pp->txqs) 5279c5aff182SThomas Petazzoni return -ENOMEM; 5280c5aff182SThomas Petazzoni 5281c5aff182SThomas Petazzoni /* Initialize TX descriptor rings */ 5282c5aff182SThomas Petazzoni for (queue = 0; queue < txq_number; queue++) { 5283c5aff182SThomas Petazzoni struct mvneta_tx_queue *txq = &pp->txqs[queue]; 5284c5aff182SThomas Petazzoni txq->id = queue; 5285c5aff182SThomas Petazzoni txq->size = pp->tx_ring_size; 5286c5aff182SThomas Petazzoni txq->done_pkts_coal = MVNETA_TXDONE_COAL_PKTS; 5287c5aff182SThomas Petazzoni } 5288c5aff182SThomas Petazzoni 52895d6312edSMarkus Elfring pp->rxqs = devm_kcalloc(dev, rxq_number, sizeof(*pp->rxqs), GFP_KERNEL); 52909672850bSEzequiel Garcia if (!pp->rxqs) 5291c5aff182SThomas Petazzoni return -ENOMEM; 5292c5aff182SThomas Petazzoni 5293c5aff182SThomas Petazzoni /* Create Rx descriptor rings */ 5294c5aff182SThomas Petazzoni for (queue = 0; queue < rxq_number; queue++) { 5295c5aff182SThomas Petazzoni struct mvneta_rx_queue *rxq = &pp->rxqs[queue]; 5296c5aff182SThomas Petazzoni rxq->id = queue; 5297c5aff182SThomas Petazzoni rxq->size = pp->rx_ring_size; 5298c5aff182SThomas Petazzoni rxq->pkts_coal = MVNETA_RX_COAL_PKTS; 5299c5aff182SThomas Petazzoni rxq->time_coal = MVNETA_RX_COAL_USEC; 530029110630SMarkus Elfring rxq->buf_virt_addr 530129110630SMarkus Elfring = devm_kmalloc_array(pp->dev->dev.parent, 530229110630SMarkus Elfring rxq->size, 530329110630SMarkus Elfring sizeof(*rxq->buf_virt_addr), 5304f88bee1cSGregory CLEMENT GFP_KERNEL); 5305f88bee1cSGregory CLEMENT if (!rxq->buf_virt_addr) 5306f88bee1cSGregory CLEMENT return -ENOMEM; 5307c5aff182SThomas Petazzoni } 5308c5aff182SThomas Petazzoni 5309c5aff182SThomas Petazzoni return 0; 5310c5aff182SThomas Petazzoni } 5311c5aff182SThomas Petazzoni 5312c5aff182SThomas Petazzoni /* platform glue : initialize decoding windows */ 531303ce758eSGreg KH static void mvneta_conf_mbus_windows(struct mvneta_port *pp, 5314c5aff182SThomas Petazzoni const struct mbus_dram_target_info *dram) 5315c5aff182SThomas Petazzoni { 5316c5aff182SThomas Petazzoni u32 win_enable; 5317c5aff182SThomas Petazzoni u32 win_protect; 5318c5aff182SThomas Petazzoni int i; 5319c5aff182SThomas Petazzoni 5320c5aff182SThomas Petazzoni for (i = 0; i < 6; i++) { 5321c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_WIN_BASE(i), 0); 5322c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_WIN_SIZE(i), 0); 5323c5aff182SThomas Petazzoni 5324c5aff182SThomas Petazzoni if (i < 4) 5325c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_WIN_REMAP(i), 0); 5326c5aff182SThomas Petazzoni } 5327c5aff182SThomas Petazzoni 5328c5aff182SThomas Petazzoni win_enable = 0x3f; 5329c5aff182SThomas Petazzoni win_protect = 0; 5330c5aff182SThomas Petazzoni 53312636ac3cSMarcin Wojtas if (dram) { 5332c5aff182SThomas Petazzoni for (i = 0; i < dram->num_cs; i++) { 5333c5aff182SThomas Petazzoni const struct mbus_dram_window *cs = dram->cs + i; 53342636ac3cSMarcin Wojtas 53352636ac3cSMarcin Wojtas mvreg_write(pp, MVNETA_WIN_BASE(i), 53362636ac3cSMarcin Wojtas (cs->base & 0xffff0000) | 53372636ac3cSMarcin Wojtas (cs->mbus_attr << 8) | 53382636ac3cSMarcin Wojtas dram->mbus_dram_target_id); 5339c5aff182SThomas Petazzoni 5340c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_WIN_SIZE(i), 5341c5aff182SThomas Petazzoni (cs->size - 1) & 0xffff0000); 5342c5aff182SThomas Petazzoni 5343c5aff182SThomas Petazzoni win_enable &= ~(1 << i); 5344c5aff182SThomas Petazzoni win_protect |= 3 << (2 * i); 5345c5aff182SThomas Petazzoni } 53462636ac3cSMarcin Wojtas } else { 53472d2a514cSChris Packham if (pp->neta_ac5) 53482d2a514cSChris Packham mvreg_write(pp, MVNETA_WIN_BASE(0), 53492d2a514cSChris Packham (MVNETA_AC5_CNM_DDR_ATTR << 8) | 53502d2a514cSChris Packham MVNETA_AC5_CNM_DDR_TARGET); 53512636ac3cSMarcin Wojtas /* For Armada3700 open default 4GB Mbus window, leaving 53522636ac3cSMarcin Wojtas * arbitration of target/attribute to a different layer 53532636ac3cSMarcin Wojtas * of configuration. 53542636ac3cSMarcin Wojtas */ 53552636ac3cSMarcin Wojtas mvreg_write(pp, MVNETA_WIN_SIZE(0), 0xffff0000); 53562636ac3cSMarcin Wojtas win_enable &= ~BIT(0); 53572636ac3cSMarcin Wojtas win_protect = 3; 53582636ac3cSMarcin Wojtas } 5359c5aff182SThomas Petazzoni 5360c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_BASE_ADDR_ENABLE, win_enable); 5361db6ba9a5SMarcin Wojtas mvreg_write(pp, MVNETA_ACCESS_PROTECT_ENABLE, win_protect); 5362c5aff182SThomas Petazzoni } 5363c5aff182SThomas Petazzoni 5364c5aff182SThomas Petazzoni /* Power up the port */ 53653f1dd4bcSThomas Petazzoni static int mvneta_port_power_up(struct mvneta_port *pp, int phy_mode) 5366c5aff182SThomas Petazzoni { 5367c5aff182SThomas Petazzoni /* MAC Cause register should be cleared */ 5368c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_UNIT_INTR_CAUSE, 0); 5369c5aff182SThomas Petazzoni 537041c2b6b4SSascha Hauer if (phy_mode != PHY_INTERFACE_MODE_QSGMII && 537141c2b6b4SSascha Hauer phy_mode != PHY_INTERFACE_MODE_SGMII && 537241c2b6b4SSascha Hauer !phy_interface_mode_is_8023z(phy_mode) && 537341c2b6b4SSascha Hauer !phy_interface_mode_is_rgmii(phy_mode)) 53743f1dd4bcSThomas Petazzoni return -EINVAL; 53753f1dd4bcSThomas Petazzoni 53763f1dd4bcSThomas Petazzoni return 0; 5377c5aff182SThomas Petazzoni } 5378c5aff182SThomas Petazzoni 5379c5aff182SThomas Petazzoni /* Device initialization routine */ 538003ce758eSGreg KH static int mvneta_probe(struct platform_device *pdev) 5381c5aff182SThomas Petazzoni { 5382c5aff182SThomas Petazzoni struct device_node *dn = pdev->dev.of_node; 5383dc35a10fSMarcin Wojtas struct device_node *bm_node; 5384c5aff182SThomas Petazzoni struct mvneta_port *pp; 5385c5aff182SThomas Petazzoni struct net_device *dev; 5386503f9aa9SRussell King struct phylink *phylink; 5387a10c1c81SRussell King struct phy *comphy; 53888cc3e439SThomas Petazzoni char hw_mac_addr[ETH_ALEN]; 53890c65b2b9SAndrew Lunn phy_interface_t phy_mode; 53908cc3e439SThomas Petazzoni const char *mac_from; 53919110ee07SMarcin Wojtas int tx_csum_limit; 5392c5aff182SThomas Petazzoni int err; 539312bb03b4SMaxime Ripard int cpu; 5394c5aff182SThomas Petazzoni 5395a3ddd94fSRosen Penev dev = devm_alloc_etherdev_mqs(&pdev->dev, sizeof(struct mvneta_port), 5396a3ddd94fSRosen Penev txq_number, rxq_number); 5397c5aff182SThomas Petazzoni if (!dev) 5398c5aff182SThomas Petazzoni return -ENOMEM; 5399c5aff182SThomas Petazzoni 540072bb9531SRussell King (Oracle) dev->tx_queue_len = MVNETA_MAX_TXD; 540172bb9531SRussell King (Oracle) dev->watchdog_timeo = 5 * HZ; 540272bb9531SRussell King (Oracle) dev->netdev_ops = &mvneta_netdev_ops; 540372bb9531SRussell King (Oracle) dev->ethtool_ops = &mvneta_eth_tool_ops; 540472bb9531SRussell King (Oracle) 540572bb9531SRussell King (Oracle) pp = netdev_priv(dev); 540672bb9531SRussell King (Oracle) spin_lock_init(&pp->lock); 540772bb9531SRussell King (Oracle) pp->dn = dn; 540872bb9531SRussell King (Oracle) 540972bb9531SRussell King (Oracle) pp->rxq_def = rxq_def; 541072bb9531SRussell King (Oracle) pp->indir[0] = rxq_def; 5411c5aff182SThomas Petazzoni 54120c65b2b9SAndrew Lunn err = of_get_phy_mode(dn, &phy_mode); 54130c65b2b9SAndrew Lunn if (err) { 5414c5aff182SThomas Petazzoni dev_err(&pdev->dev, "incorrect phy-mode\n"); 541572bb9531SRussell King (Oracle) return err; 5416503f9aa9SRussell King } 5417503f9aa9SRussell King 541872bb9531SRussell King (Oracle) pp->phy_interface = phy_mode; 541972bb9531SRussell King (Oracle) 5420a10c1c81SRussell King comphy = devm_of_phy_get(&pdev->dev, dn, NULL); 542172bb9531SRussell King (Oracle) if (comphy == ERR_PTR(-EPROBE_DEFER)) 542272bb9531SRussell King (Oracle) return -EPROBE_DEFER; 542372bb9531SRussell King (Oracle) 542472bb9531SRussell King (Oracle) if (IS_ERR(comphy)) 5425a10c1c81SRussell King comphy = NULL; 542672bb9531SRussell King (Oracle) 542772bb9531SRussell King (Oracle) pp->comphy = comphy; 542872bb9531SRussell King (Oracle) 542972bb9531SRussell King (Oracle) pp->base = devm_platform_ioremap_resource(pdev, 0); 543072bb9531SRussell King (Oracle) if (IS_ERR(pp->base)) 543172bb9531SRussell King (Oracle) return PTR_ERR(pp->base); 543272bb9531SRussell King (Oracle) 543372bb9531SRussell King (Oracle) /* Get special SoC configurations */ 543472bb9531SRussell King (Oracle) if (of_device_is_compatible(dn, "marvell,armada-3700-neta")) 543572bb9531SRussell King (Oracle) pp->neta_armada3700 = true; 54362d2a514cSChris Packham if (of_device_is_compatible(dn, "marvell,armada-ac5-neta")) { 54372d2a514cSChris Packham pp->neta_armada3700 = true; 54382d2a514cSChris Packham pp->neta_ac5 = true; 54392d2a514cSChris Packham } 544072bb9531SRussell King (Oracle) 544172bb9531SRussell King (Oracle) dev->irq = irq_of_parse_and_map(dn, 0); 544272bb9531SRussell King (Oracle) if (dev->irq == 0) 544372bb9531SRussell King (Oracle) return -EINVAL; 544472bb9531SRussell King (Oracle) 544572bb9531SRussell King (Oracle) pp->clk = devm_clk_get(&pdev->dev, "core"); 544672bb9531SRussell King (Oracle) if (IS_ERR(pp->clk)) 544772bb9531SRussell King (Oracle) pp->clk = devm_clk_get(&pdev->dev, NULL); 544872bb9531SRussell King (Oracle) if (IS_ERR(pp->clk)) { 544972bb9531SRussell King (Oracle) err = PTR_ERR(pp->clk); 545072bb9531SRussell King (Oracle) goto err_free_irq; 5451a10c1c81SRussell King } 5452a10c1c81SRussell King 545372bb9531SRussell King (Oracle) clk_prepare_enable(pp->clk); 545472bb9531SRussell King (Oracle) 545572bb9531SRussell King (Oracle) pp->clk_bus = devm_clk_get(&pdev->dev, "bus"); 545672bb9531SRussell King (Oracle) if (!IS_ERR(pp->clk_bus)) 545772bb9531SRussell King (Oracle) clk_prepare_enable(pp->clk_bus); 545872bb9531SRussell King (Oracle) 545972bb9531SRussell King (Oracle) pp->phylink_pcs.ops = &mvneta_phylink_pcs_ops; 546044cc27e4SIoana Ciornei 546144cc27e4SIoana Ciornei pp->phylink_config.dev = &dev->dev; 546244cc27e4SIoana Ciornei pp->phylink_config.type = PHYLINK_NETDEV; 546302a0988bSRussell King (Oracle) pp->phylink_config.mac_capabilities = MAC_SYM_PAUSE | MAC_10 | 546402a0988bSRussell King (Oracle) MAC_100 | MAC_1000FD | MAC_2500FD; 546502a0988bSRussell King (Oracle) 5466fdedb695SRussell King phy_interface_set_rgmii(pp->phylink_config.supported_interfaces); 5467fdedb695SRussell King __set_bit(PHY_INTERFACE_MODE_QSGMII, 5468fdedb695SRussell King pp->phylink_config.supported_interfaces); 5469fdedb695SRussell King if (comphy) { 5470fdedb695SRussell King /* If a COMPHY is present, we can support any of the serdes 5471fdedb695SRussell King * modes and switch between them. 5472fdedb695SRussell King */ 5473fdedb695SRussell King __set_bit(PHY_INTERFACE_MODE_SGMII, 5474fdedb695SRussell King pp->phylink_config.supported_interfaces); 5475fdedb695SRussell King __set_bit(PHY_INTERFACE_MODE_1000BASEX, 5476fdedb695SRussell King pp->phylink_config.supported_interfaces); 5477fdedb695SRussell King __set_bit(PHY_INTERFACE_MODE_2500BASEX, 5478fdedb695SRussell King pp->phylink_config.supported_interfaces); 5479fdedb695SRussell King } else if (phy_mode == PHY_INTERFACE_MODE_2500BASEX) { 5480fdedb695SRussell King /* No COMPHY, with only 2500BASE-X mode supported */ 5481fdedb695SRussell King __set_bit(PHY_INTERFACE_MODE_2500BASEX, 5482fdedb695SRussell King pp->phylink_config.supported_interfaces); 5483fdedb695SRussell King } else if (phy_mode == PHY_INTERFACE_MODE_1000BASEX || 5484fdedb695SRussell King phy_mode == PHY_INTERFACE_MODE_SGMII) { 5485fdedb695SRussell King /* No COMPHY, we can switch between 1000BASE-X and SGMII */ 5486fdedb695SRussell King __set_bit(PHY_INTERFACE_MODE_1000BASEX, 5487fdedb695SRussell King pp->phylink_config.supported_interfaces); 5488fdedb695SRussell King __set_bit(PHY_INTERFACE_MODE_SGMII, 5489fdedb695SRussell King pp->phylink_config.supported_interfaces); 5490fdedb695SRussell King } 549144cc27e4SIoana Ciornei 549244cc27e4SIoana Ciornei phylink = phylink_create(&pp->phylink_config, pdev->dev.fwnode, 549344cc27e4SIoana Ciornei phy_mode, &mvneta_phylink_ops); 5494503f9aa9SRussell King if (IS_ERR(phylink)) { 5495503f9aa9SRussell King err = PTR_ERR(phylink); 54965445eaf3SArnaud Patard \(Rtp\) goto err_clk; 54975445eaf3SArnaud Patard \(Rtp\) } 54985445eaf3SArnaud Patard \(Rtp\) 549972bb9531SRussell King (Oracle) pp->phylink = phylink; 550072bb9531SRussell King (Oracle) 550112bb03b4SMaxime Ripard /* Alloc per-cpu port structure */ 550212bb03b4SMaxime Ripard pp->ports = alloc_percpu(struct mvneta_pcpu_port); 550312bb03b4SMaxime Ripard if (!pp->ports) { 550412bb03b4SMaxime Ripard err = -ENOMEM; 550572bb9531SRussell King (Oracle) goto err_free_phylink; 550612bb03b4SMaxime Ripard } 550712bb03b4SMaxime Ripard 550874c41b04Swilly tarreau /* Alloc per-cpu stats */ 55091c213bd2SWANG Cong pp->stats = netdev_alloc_pcpu_stats(struct mvneta_pcpu_stats); 551074c41b04Swilly tarreau if (!pp->stats) { 551174c41b04Swilly tarreau err = -ENOMEM; 551212bb03b4SMaxime Ripard goto err_free_ports; 551374c41b04Swilly tarreau } 551474c41b04Swilly tarreau 55159ca01b25SJakub Kicinski err = of_get_ethdev_address(dn, dev); 551683216e39SMichael Walle if (!err) { 55178cc3e439SThomas Petazzoni mac_from = "device tree"; 55188cc3e439SThomas Petazzoni } else { 55198cc3e439SThomas Petazzoni mvneta_get_mac_addr(pp, hw_mac_addr); 55208cc3e439SThomas Petazzoni if (is_valid_ether_addr(hw_mac_addr)) { 55218cc3e439SThomas Petazzoni mac_from = "hardware"; 5522a96d317fSJakub Kicinski eth_hw_addr_set(dev, hw_mac_addr); 55238cc3e439SThomas Petazzoni } else { 55248cc3e439SThomas Petazzoni mac_from = "random"; 55258cc3e439SThomas Petazzoni eth_hw_addr_random(dev); 55268cc3e439SThomas Petazzoni } 55278cc3e439SThomas Petazzoni } 55288cc3e439SThomas Petazzoni 55299110ee07SMarcin Wojtas if (!of_property_read_u32(dn, "tx-csum-limit", &tx_csum_limit)) { 55309110ee07SMarcin Wojtas if (tx_csum_limit < 0 || 55319110ee07SMarcin Wojtas tx_csum_limit > MVNETA_TX_CSUM_MAX_SIZE) { 55329110ee07SMarcin Wojtas tx_csum_limit = MVNETA_TX_CSUM_DEF_SIZE; 55339110ee07SMarcin Wojtas dev_info(&pdev->dev, 55349110ee07SMarcin Wojtas "Wrong TX csum limit in DT, set to %dB\n", 55359110ee07SMarcin Wojtas MVNETA_TX_CSUM_DEF_SIZE); 55369110ee07SMarcin Wojtas } 55379110ee07SMarcin Wojtas } else if (of_device_is_compatible(dn, "marvell,armada-370-neta")) { 55389110ee07SMarcin Wojtas tx_csum_limit = MVNETA_TX_CSUM_DEF_SIZE; 55399110ee07SMarcin Wojtas } else { 55409110ee07SMarcin Wojtas tx_csum_limit = MVNETA_TX_CSUM_MAX_SIZE; 55419110ee07SMarcin Wojtas } 55429110ee07SMarcin Wojtas 55439110ee07SMarcin Wojtas pp->tx_csum_limit = tx_csum_limit; 5544b65657fcSSimon Guinot 55459768b45cSJane Li pp->dram_target_info = mv_mbus_dram_info(); 55462636ac3cSMarcin Wojtas /* Armada3700 requires setting default configuration of Mbus 55472636ac3cSMarcin Wojtas * windows, however without using filled mbus_dram_target_info 55482636ac3cSMarcin Wojtas * structure. 55492636ac3cSMarcin Wojtas */ 55509768b45cSJane Li if (pp->dram_target_info || pp->neta_armada3700) 55519768b45cSJane Li mvneta_conf_mbus_windows(pp, pp->dram_target_info); 5552dc35a10fSMarcin Wojtas 5553c5aff182SThomas Petazzoni pp->tx_ring_size = MVNETA_MAX_TXD; 5554c5aff182SThomas Petazzoni pp->rx_ring_size = MVNETA_MAX_RXD; 5555c5aff182SThomas Petazzoni 5556c5aff182SThomas Petazzoni pp->dev = dev; 5557c5aff182SThomas Petazzoni SET_NETDEV_DEV(dev, &pdev->dev); 5558c5aff182SThomas Petazzoni 5559dc35a10fSMarcin Wojtas pp->id = global_port_id++; 5560dc35a10fSMarcin Wojtas 5561dc35a10fSMarcin Wojtas /* Obtain access to BM resources if enabled and already initialized */ 5562dc35a10fSMarcin Wojtas bm_node = of_parse_phandle(dn, "buffer-manager", 0); 5563965cbbecSGregory CLEMENT if (bm_node) { 5564965cbbecSGregory CLEMENT pp->bm_priv = mvneta_bm_get(bm_node); 5565965cbbecSGregory CLEMENT if (pp->bm_priv) { 5566dc35a10fSMarcin Wojtas err = mvneta_bm_port_init(pdev, pp); 5567dc35a10fSMarcin Wojtas if (err < 0) { 5568965cbbecSGregory CLEMENT dev_info(&pdev->dev, 5569965cbbecSGregory CLEMENT "use SW buffer management\n"); 5570965cbbecSGregory CLEMENT mvneta_bm_put(pp->bm_priv); 5571dc35a10fSMarcin Wojtas pp->bm_priv = NULL; 5572dc35a10fSMarcin Wojtas } 5573dc35a10fSMarcin Wojtas } 5574562e2f46SYelena Krivosheev /* Set RX packet offset correction for platforms, whose 5575562e2f46SYelena Krivosheev * NET_SKB_PAD, exceeds 64B. It should be 64B for 64-bit 5576562e2f46SYelena Krivosheev * platforms and 0B for 32-bit ones. 5577562e2f46SYelena Krivosheev */ 5578562e2f46SYelena Krivosheev pp->rx_offset_correction = max(0, 5579562e2f46SYelena Krivosheev NET_SKB_PAD - 5580562e2f46SYelena Krivosheev MVNETA_RX_PKT_OFFSET_CORRECTION); 5581965cbbecSGregory CLEMENT } 5582d4e4da00SPeter Chen of_node_put(bm_node); 5583dc35a10fSMarcin Wojtas 558444efc78dSLorenzo Bianconi /* sw buffer management */ 558544efc78dSLorenzo Bianconi if (!pp->bm_priv) 558644efc78dSLorenzo Bianconi pp->rx_offset_correction = MVNETA_SKB_HEADROOM; 558744efc78dSLorenzo Bianconi 55889672850bSEzequiel Garcia err = mvneta_init(&pdev->dev, pp); 55899672850bSEzequiel Garcia if (err < 0) 5590dc35a10fSMarcin Wojtas goto err_netdev; 55913f1dd4bcSThomas Petazzoni 559241c2b6b4SSascha Hauer err = mvneta_port_power_up(pp, pp->phy_interface); 55933f1dd4bcSThomas Petazzoni if (err < 0) { 55943f1dd4bcSThomas Petazzoni dev_err(&pdev->dev, "can't power up port\n"); 559558f60329SDinghao Liu goto err_netdev; 55963f1dd4bcSThomas Petazzoni } 5597c5aff182SThomas Petazzoni 55982636ac3cSMarcin Wojtas /* Armada3700 network controller does not support per-cpu 55992636ac3cSMarcin Wojtas * operation, so only single NAPI should be initialized. 56002636ac3cSMarcin Wojtas */ 56012636ac3cSMarcin Wojtas if (pp->neta_armada3700) { 5602b48b89f9SJakub Kicinski netif_napi_add(dev, &pp->napi, mvneta_poll); 56032636ac3cSMarcin Wojtas } else { 560412bb03b4SMaxime Ripard for_each_present_cpu(cpu) { 56052636ac3cSMarcin Wojtas struct mvneta_pcpu_port *port = 56062636ac3cSMarcin Wojtas per_cpu_ptr(pp->ports, cpu); 560712bb03b4SMaxime Ripard 5608b48b89f9SJakub Kicinski netif_napi_add(dev, &port->napi, mvneta_poll); 560912bb03b4SMaxime Ripard port->pp = pp; 561012bb03b4SMaxime Ripard } 56112636ac3cSMarcin Wojtas } 5612c5aff182SThomas Petazzoni 56137772988aSJisheng Zhang dev->features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | 56147772988aSJisheng Zhang NETIF_F_TSO | NETIF_F_RXCSUM; 561501ef26caSEzequiel Garcia dev->hw_features |= dev->features; 561601ef26caSEzequiel Garcia dev->vlan_features |= dev->features; 56171dc55923SLorenzo Bianconi if (!pp->bm_priv) 56181dc55923SLorenzo Bianconi dev->xdp_features = NETDEV_XDP_ACT_BASIC | 56191dc55923SLorenzo Bianconi NETDEV_XDP_ACT_REDIRECT | 56201dc55923SLorenzo Bianconi NETDEV_XDP_ACT_NDO_XMIT | 56211dc55923SLorenzo Bianconi NETDEV_XDP_ACT_RX_SG | 562266c0e13aSMarek Majtyka NETDEV_XDP_ACT_NDO_XMIT_SG; 562397db8afaSAndrew Lunn dev->priv_flags |= IFF_LIVE_ADDR_CHANGE; 5624ee8b7a11SJakub Kicinski netif_set_tso_max_segs(dev, MVNETA_MAX_TSO_SEGS); 5625b50b72deSwilly tarreau 56265777987eSJarod Wilson /* MTU range: 68 - 9676 */ 56275777987eSJarod Wilson dev->min_mtu = ETH_MIN_MTU; 56285777987eSJarod Wilson /* 9676 == 9700 - 20 and rounding to 8 */ 56295777987eSJarod Wilson dev->max_mtu = 9676; 56305777987eSJarod Wilson 5631c5aff182SThomas Petazzoni err = register_netdev(dev); 5632c5aff182SThomas Petazzoni if (err < 0) { 5633c5aff182SThomas Petazzoni dev_err(&pdev->dev, "failed to register\n"); 5634d484e06eSJisheng Zhang goto err_netdev; 5635c5aff182SThomas Petazzoni } 5636c5aff182SThomas Petazzoni 56378cc3e439SThomas Petazzoni netdev_info(dev, "Using %s mac address %pM\n", mac_from, 56388cc3e439SThomas Petazzoni dev->dev_addr); 5639c5aff182SThomas Petazzoni 5640c5aff182SThomas Petazzoni platform_set_drvdata(pdev, pp->dev); 5641c5aff182SThomas Petazzoni 5642c5aff182SThomas Petazzoni return 0; 5643c5aff182SThomas Petazzoni 5644dc35a10fSMarcin Wojtas err_netdev: 5645dc35a10fSMarcin Wojtas if (pp->bm_priv) { 5646dc35a10fSMarcin Wojtas mvneta_bm_pool_destroy(pp->bm_priv, pp->pool_long, 1 << pp->id); 5647dc35a10fSMarcin Wojtas mvneta_bm_pool_destroy(pp->bm_priv, pp->pool_short, 5648dc35a10fSMarcin Wojtas 1 << pp->id); 5649965cbbecSGregory CLEMENT mvneta_bm_put(pp->bm_priv); 5650dc35a10fSMarcin Wojtas } 565174c41b04Swilly tarreau free_percpu(pp->stats); 565212bb03b4SMaxime Ripard err_free_ports: 565312bb03b4SMaxime Ripard free_percpu(pp->ports); 5654503f9aa9SRussell King err_free_phylink: 5655503f9aa9SRussell King if (pp->phylink) 5656503f9aa9SRussell King phylink_destroy(pp->phylink); 565772bb9531SRussell King (Oracle) err_clk: 565872bb9531SRussell King (Oracle) clk_disable_unprepare(pp->clk_bus); 565972bb9531SRussell King (Oracle) clk_disable_unprepare(pp->clk); 5660c5aff182SThomas Petazzoni err_free_irq: 5661c5aff182SThomas Petazzoni irq_dispose_mapping(dev->irq); 5662c5aff182SThomas Petazzoni return err; 5663c5aff182SThomas Petazzoni } 5664c5aff182SThomas Petazzoni 5665c5aff182SThomas Petazzoni /* Device removal routine */ 566603ce758eSGreg KH static int mvneta_remove(struct platform_device *pdev) 5667c5aff182SThomas Petazzoni { 5668c5aff182SThomas Petazzoni struct net_device *dev = platform_get_drvdata(pdev); 5669c5aff182SThomas Petazzoni struct mvneta_port *pp = netdev_priv(dev); 5670c5aff182SThomas Petazzoni 5671c5aff182SThomas Petazzoni unregister_netdev(dev); 567215cc4a4aSJisheng Zhang clk_disable_unprepare(pp->clk_bus); 5673189dd626SThomas Petazzoni clk_disable_unprepare(pp->clk); 567412bb03b4SMaxime Ripard free_percpu(pp->ports); 567574c41b04Swilly tarreau free_percpu(pp->stats); 5676c5aff182SThomas Petazzoni irq_dispose_mapping(dev->irq); 5677503f9aa9SRussell King phylink_destroy(pp->phylink); 5678c5aff182SThomas Petazzoni 5679dc35a10fSMarcin Wojtas if (pp->bm_priv) { 5680dc35a10fSMarcin Wojtas mvneta_bm_pool_destroy(pp->bm_priv, pp->pool_long, 1 << pp->id); 5681dc35a10fSMarcin Wojtas mvneta_bm_pool_destroy(pp->bm_priv, pp->pool_short, 5682dc35a10fSMarcin Wojtas 1 << pp->id); 5683965cbbecSGregory CLEMENT mvneta_bm_put(pp->bm_priv); 5684dc35a10fSMarcin Wojtas } 5685dc35a10fSMarcin Wojtas 5686c5aff182SThomas Petazzoni return 0; 5687c5aff182SThomas Petazzoni } 5688c5aff182SThomas Petazzoni 56899768b45cSJane Li #ifdef CONFIG_PM_SLEEP 56909768b45cSJane Li static int mvneta_suspend(struct device *device) 56919768b45cSJane Li { 56921799cdd2SJisheng Zhang int queue; 56939768b45cSJane Li struct net_device *dev = dev_get_drvdata(device); 56949768b45cSJane Li struct mvneta_port *pp = netdev_priv(dev); 56959768b45cSJane Li 56961799cdd2SJisheng Zhang if (!netif_running(dev)) 56971799cdd2SJisheng Zhang goto clean_exit; 56981799cdd2SJisheng Zhang 56991799cdd2SJisheng Zhang if (!pp->neta_armada3700) { 57001799cdd2SJisheng Zhang spin_lock(&pp->lock); 57011799cdd2SJisheng Zhang pp->is_stopped = true; 57021799cdd2SJisheng Zhang spin_unlock(&pp->lock); 57031799cdd2SJisheng Zhang 57041799cdd2SJisheng Zhang cpuhp_state_remove_instance_nocalls(online_hpstate, 57051799cdd2SJisheng Zhang &pp->node_online); 57061799cdd2SJisheng Zhang cpuhp_state_remove_instance_nocalls(CPUHP_NET_MVNETA_DEAD, 57071799cdd2SJisheng Zhang &pp->node_dead); 57081799cdd2SJisheng Zhang } 57091799cdd2SJisheng Zhang 57103b8bc674SRussell King rtnl_lock(); 57111799cdd2SJisheng Zhang mvneta_stop_dev(pp); 57123b8bc674SRussell King rtnl_unlock(); 57131799cdd2SJisheng Zhang 57141799cdd2SJisheng Zhang for (queue = 0; queue < rxq_number; queue++) { 57151799cdd2SJisheng Zhang struct mvneta_rx_queue *rxq = &pp->rxqs[queue]; 57161799cdd2SJisheng Zhang 57171799cdd2SJisheng Zhang mvneta_rxq_drop_pkts(pp, rxq); 57181799cdd2SJisheng Zhang } 57191799cdd2SJisheng Zhang 57201799cdd2SJisheng Zhang for (queue = 0; queue < txq_number; queue++) { 57211799cdd2SJisheng Zhang struct mvneta_tx_queue *txq = &pp->txqs[queue]; 57221799cdd2SJisheng Zhang 57231799cdd2SJisheng Zhang mvneta_txq_hw_deinit(pp, txq); 57241799cdd2SJisheng Zhang } 57251799cdd2SJisheng Zhang 57261799cdd2SJisheng Zhang clean_exit: 57279768b45cSJane Li netif_device_detach(dev); 57289768b45cSJane Li clk_disable_unprepare(pp->clk_bus); 57299768b45cSJane Li clk_disable_unprepare(pp->clk); 57301799cdd2SJisheng Zhang 57319768b45cSJane Li return 0; 57329768b45cSJane Li } 57339768b45cSJane Li 57349768b45cSJane Li static int mvneta_resume(struct device *device) 57359768b45cSJane Li { 57369768b45cSJane Li struct platform_device *pdev = to_platform_device(device); 57379768b45cSJane Li struct net_device *dev = dev_get_drvdata(device); 57389768b45cSJane Li struct mvneta_port *pp = netdev_priv(dev); 57391799cdd2SJisheng Zhang int err, queue; 57409768b45cSJane Li 57419768b45cSJane Li clk_prepare_enable(pp->clk); 57429768b45cSJane Li if (!IS_ERR(pp->clk_bus)) 57439768b45cSJane Li clk_prepare_enable(pp->clk_bus); 57449768b45cSJane Li if (pp->dram_target_info || pp->neta_armada3700) 57459768b45cSJane Li mvneta_conf_mbus_windows(pp, pp->dram_target_info); 57469768b45cSJane Li if (pp->bm_priv) { 57479768b45cSJane Li err = mvneta_bm_port_init(pdev, pp); 57489768b45cSJane Li if (err < 0) { 57499768b45cSJane Li dev_info(&pdev->dev, "use SW buffer management\n"); 575044efc78dSLorenzo Bianconi pp->rx_offset_correction = MVNETA_SKB_HEADROOM; 57519768b45cSJane Li pp->bm_priv = NULL; 57529768b45cSJane Li } 57539768b45cSJane Li } 57549768b45cSJane Li mvneta_defaults_set(pp); 57559768b45cSJane Li err = mvneta_port_power_up(pp, pp->phy_interface); 57569768b45cSJane Li if (err < 0) { 57579768b45cSJane Li dev_err(device, "can't power up port\n"); 57589768b45cSJane Li return err; 57599768b45cSJane Li } 57609768b45cSJane Li 57619768b45cSJane Li netif_device_attach(dev); 57621799cdd2SJisheng Zhang 57631799cdd2SJisheng Zhang if (!netif_running(dev)) 57641799cdd2SJisheng Zhang return 0; 57651799cdd2SJisheng Zhang 57661799cdd2SJisheng Zhang for (queue = 0; queue < rxq_number; queue++) { 57671799cdd2SJisheng Zhang struct mvneta_rx_queue *rxq = &pp->rxqs[queue]; 57681799cdd2SJisheng Zhang 57691799cdd2SJisheng Zhang rxq->next_desc_to_proc = 0; 57701799cdd2SJisheng Zhang mvneta_rxq_hw_init(pp, rxq); 5771d6956ac8SJisheng Zhang } 57721799cdd2SJisheng Zhang 57731799cdd2SJisheng Zhang for (queue = 0; queue < txq_number; queue++) { 57741799cdd2SJisheng Zhang struct mvneta_tx_queue *txq = &pp->txqs[queue]; 57751799cdd2SJisheng Zhang 57761799cdd2SJisheng Zhang txq->next_desc_to_proc = 0; 57771799cdd2SJisheng Zhang mvneta_txq_hw_init(pp, txq); 57781799cdd2SJisheng Zhang } 57791799cdd2SJisheng Zhang 57801799cdd2SJisheng Zhang if (!pp->neta_armada3700) { 57811799cdd2SJisheng Zhang spin_lock(&pp->lock); 57821799cdd2SJisheng Zhang pp->is_stopped = false; 57831799cdd2SJisheng Zhang spin_unlock(&pp->lock); 57841799cdd2SJisheng Zhang cpuhp_state_add_instance_nocalls(online_hpstate, 57851799cdd2SJisheng Zhang &pp->node_online); 57861799cdd2SJisheng Zhang cpuhp_state_add_instance_nocalls(CPUHP_NET_MVNETA_DEAD, 57871799cdd2SJisheng Zhang &pp->node_dead); 57881799cdd2SJisheng Zhang } 57891799cdd2SJisheng Zhang 57901799cdd2SJisheng Zhang rtnl_lock(); 57911799cdd2SJisheng Zhang mvneta_start_dev(pp); 57923b8bc674SRussell King rtnl_unlock(); 57931799cdd2SJisheng Zhang mvneta_set_rx_mode(dev); 5794d6956ac8SJisheng Zhang 57959768b45cSJane Li return 0; 57969768b45cSJane Li } 57979768b45cSJane Li #endif 57989768b45cSJane Li 57999768b45cSJane Li static SIMPLE_DEV_PM_OPS(mvneta_pm_ops, mvneta_suspend, mvneta_resume); 58009768b45cSJane Li 5801c5aff182SThomas Petazzoni static const struct of_device_id mvneta_match[] = { 5802c5aff182SThomas Petazzoni { .compatible = "marvell,armada-370-neta" }, 5803f522a975SSimon Guinot { .compatible = "marvell,armada-xp-neta" }, 58042636ac3cSMarcin Wojtas { .compatible = "marvell,armada-3700-neta" }, 58052d2a514cSChris Packham { .compatible = "marvell,armada-ac5-neta" }, 5806c5aff182SThomas Petazzoni { } 5807c5aff182SThomas Petazzoni }; 5808c5aff182SThomas Petazzoni MODULE_DEVICE_TABLE(of, mvneta_match); 5809c5aff182SThomas Petazzoni 5810c5aff182SThomas Petazzoni static struct platform_driver mvneta_driver = { 5811c5aff182SThomas Petazzoni .probe = mvneta_probe, 581203ce758eSGreg KH .remove = mvneta_remove, 5813c5aff182SThomas Petazzoni .driver = { 5814c5aff182SThomas Petazzoni .name = MVNETA_DRIVER_NAME, 5815c5aff182SThomas Petazzoni .of_match_table = mvneta_match, 58169768b45cSJane Li .pm = &mvneta_pm_ops, 5817c5aff182SThomas Petazzoni }, 5818c5aff182SThomas Petazzoni }; 5819c5aff182SThomas Petazzoni 582084a3f4dbSSebastian Andrzej Siewior static int __init mvneta_driver_init(void) 582184a3f4dbSSebastian Andrzej Siewior { 582284a3f4dbSSebastian Andrzej Siewior int ret; 582384a3f4dbSSebastian Andrzej Siewior 5824664d035cSChristophe JAILLET ret = cpuhp_setup_state_multi(CPUHP_AP_ONLINE_DYN, "net/mvneta:online", 582584a3f4dbSSebastian Andrzej Siewior mvneta_cpu_online, 582684a3f4dbSSebastian Andrzej Siewior mvneta_cpu_down_prepare); 582784a3f4dbSSebastian Andrzej Siewior if (ret < 0) 582884a3f4dbSSebastian Andrzej Siewior goto out; 582984a3f4dbSSebastian Andrzej Siewior online_hpstate = ret; 583084a3f4dbSSebastian Andrzej Siewior ret = cpuhp_setup_state_multi(CPUHP_NET_MVNETA_DEAD, "net/mvneta:dead", 583184a3f4dbSSebastian Andrzej Siewior NULL, mvneta_cpu_dead); 583284a3f4dbSSebastian Andrzej Siewior if (ret) 583384a3f4dbSSebastian Andrzej Siewior goto err_dead; 583484a3f4dbSSebastian Andrzej Siewior 583584a3f4dbSSebastian Andrzej Siewior ret = platform_driver_register(&mvneta_driver); 583684a3f4dbSSebastian Andrzej Siewior if (ret) 583784a3f4dbSSebastian Andrzej Siewior goto err; 583884a3f4dbSSebastian Andrzej Siewior return 0; 583984a3f4dbSSebastian Andrzej Siewior 584084a3f4dbSSebastian Andrzej Siewior err: 584184a3f4dbSSebastian Andrzej Siewior cpuhp_remove_multi_state(CPUHP_NET_MVNETA_DEAD); 584284a3f4dbSSebastian Andrzej Siewior err_dead: 584384a3f4dbSSebastian Andrzej Siewior cpuhp_remove_multi_state(online_hpstate); 584484a3f4dbSSebastian Andrzej Siewior out: 584584a3f4dbSSebastian Andrzej Siewior return ret; 584684a3f4dbSSebastian Andrzej Siewior } 584784a3f4dbSSebastian Andrzej Siewior module_init(mvneta_driver_init); 584884a3f4dbSSebastian Andrzej Siewior 584984a3f4dbSSebastian Andrzej Siewior static void __exit mvneta_driver_exit(void) 585084a3f4dbSSebastian Andrzej Siewior { 585184a3f4dbSSebastian Andrzej Siewior platform_driver_unregister(&mvneta_driver); 585284a3f4dbSSebastian Andrzej Siewior cpuhp_remove_multi_state(CPUHP_NET_MVNETA_DEAD); 585384a3f4dbSSebastian Andrzej Siewior cpuhp_remove_multi_state(online_hpstate); 585484a3f4dbSSebastian Andrzej Siewior } 585584a3f4dbSSebastian Andrzej Siewior module_exit(mvneta_driver_exit); 5856c5aff182SThomas Petazzoni 5857c5aff182SThomas Petazzoni MODULE_DESCRIPTION("Marvell NETA Ethernet Driver - www.marvell.com"); 5858c5aff182SThomas Petazzoni MODULE_AUTHOR("Rami Rosen <rosenr@marvell.com>, Thomas Petazzoni <thomas.petazzoni@free-electrons.com>"); 5859c5aff182SThomas Petazzoni MODULE_LICENSE("GPL"); 5860c5aff182SThomas Petazzoni 5861d3757ba4SJoe Perches module_param(rxq_number, int, 0444); 5862d3757ba4SJoe Perches module_param(txq_number, int, 0444); 5863c5aff182SThomas Petazzoni 5864d3757ba4SJoe Perches module_param(rxq_def, int, 0444); 5865d3757ba4SJoe Perches module_param(rx_copybreak, int, 0644); 5866