1c5aff182SThomas Petazzoni /* 2c5aff182SThomas Petazzoni * Driver for Marvell NETA network card for Armada XP and Armada 370 SoCs. 3c5aff182SThomas Petazzoni * 4c5aff182SThomas Petazzoni * Copyright (C) 2012 Marvell 5c5aff182SThomas Petazzoni * 6c5aff182SThomas Petazzoni * Rami Rosen <rosenr@marvell.com> 7c5aff182SThomas Petazzoni * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> 8c5aff182SThomas Petazzoni * 9c5aff182SThomas Petazzoni * This file is licensed under the terms of the GNU General Public 10c5aff182SThomas Petazzoni * License version 2. This program is licensed "as is" without any 11c5aff182SThomas Petazzoni * warranty of any kind, whether express or implied. 12c5aff182SThomas Petazzoni */ 13c5aff182SThomas Petazzoni 140e03f563SJisheng Zhang #include <linux/clk.h> 150e03f563SJisheng Zhang #include <linux/cpu.h> 16c5aff182SThomas Petazzoni #include <linux/etherdevice.h> 170e03f563SJisheng Zhang #include <linux/if_vlan.h> 18c5aff182SThomas Petazzoni #include <linux/inetdevice.h> 190e03f563SJisheng Zhang #include <linux/interrupt.h> 200e03f563SJisheng Zhang #include <linux/io.h> 210e03f563SJisheng Zhang #include <linux/kernel.h> 22c5aff182SThomas Petazzoni #include <linux/mbus.h> 23c5aff182SThomas Petazzoni #include <linux/module.h> 240e03f563SJisheng Zhang #include <linux/netdevice.h> 25c5aff182SThomas Petazzoni #include <linux/of.h> 260e03f563SJisheng Zhang #include <linux/of_address.h> 27c5aff182SThomas Petazzoni #include <linux/of_irq.h> 28c5aff182SThomas Petazzoni #include <linux/of_mdio.h> 29c5aff182SThomas Petazzoni #include <linux/of_net.h> 30c5aff182SThomas Petazzoni #include <linux/phy.h> 31503f9aa9SRussell King #include <linux/phylink.h> 320e03f563SJisheng Zhang #include <linux/platform_device.h> 330e03f563SJisheng Zhang #include <linux/skbuff.h> 34baa11ebcSGregory CLEMENT #include <net/hwbm.h> 35dc35a10fSMarcin Wojtas #include "mvneta_bm.h" 360e03f563SJisheng Zhang #include <net/ip.h> 370e03f563SJisheng Zhang #include <net/ipv6.h> 380e03f563SJisheng Zhang #include <net/tso.h> 39c5aff182SThomas Petazzoni 40c5aff182SThomas Petazzoni /* Registers */ 41c5aff182SThomas Petazzoni #define MVNETA_RXQ_CONFIG_REG(q) (0x1400 + ((q) << 2)) 42e5bdf689SMarcin Wojtas #define MVNETA_RXQ_HW_BUF_ALLOC BIT(0) 43dc35a10fSMarcin Wojtas #define MVNETA_RXQ_SHORT_POOL_ID_SHIFT 4 44dc35a10fSMarcin Wojtas #define MVNETA_RXQ_SHORT_POOL_ID_MASK 0x30 45dc35a10fSMarcin Wojtas #define MVNETA_RXQ_LONG_POOL_ID_SHIFT 6 46dc35a10fSMarcin Wojtas #define MVNETA_RXQ_LONG_POOL_ID_MASK 0xc0 47c5aff182SThomas Petazzoni #define MVNETA_RXQ_PKT_OFFSET_ALL_MASK (0xf << 8) 48c5aff182SThomas Petazzoni #define MVNETA_RXQ_PKT_OFFSET_MASK(offs) ((offs) << 8) 49c5aff182SThomas Petazzoni #define MVNETA_RXQ_THRESHOLD_REG(q) (0x14c0 + ((q) << 2)) 50c5aff182SThomas Petazzoni #define MVNETA_RXQ_NON_OCCUPIED(v) ((v) << 16) 51c5aff182SThomas Petazzoni #define MVNETA_RXQ_BASE_ADDR_REG(q) (0x1480 + ((q) << 2)) 52c5aff182SThomas Petazzoni #define MVNETA_RXQ_SIZE_REG(q) (0x14a0 + ((q) << 2)) 53c5aff182SThomas Petazzoni #define MVNETA_RXQ_BUF_SIZE_SHIFT 19 54c5aff182SThomas Petazzoni #define MVNETA_RXQ_BUF_SIZE_MASK (0x1fff << 19) 55c5aff182SThomas Petazzoni #define MVNETA_RXQ_STATUS_REG(q) (0x14e0 + ((q) << 2)) 56c5aff182SThomas Petazzoni #define MVNETA_RXQ_OCCUPIED_ALL_MASK 0x3fff 57c5aff182SThomas Petazzoni #define MVNETA_RXQ_STATUS_UPDATE_REG(q) (0x1500 + ((q) << 2)) 58c5aff182SThomas Petazzoni #define MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT 16 59c5aff182SThomas Petazzoni #define MVNETA_RXQ_ADD_NON_OCCUPIED_MAX 255 60dc35a10fSMarcin Wojtas #define MVNETA_PORT_POOL_BUFFER_SZ_REG(pool) (0x1700 + ((pool) << 2)) 61dc35a10fSMarcin Wojtas #define MVNETA_PORT_POOL_BUFFER_SZ_SHIFT 3 62dc35a10fSMarcin Wojtas #define MVNETA_PORT_POOL_BUFFER_SZ_MASK 0xfff8 63c5aff182SThomas Petazzoni #define MVNETA_PORT_RX_RESET 0x1cc0 64c5aff182SThomas Petazzoni #define MVNETA_PORT_RX_DMA_RESET BIT(0) 65c5aff182SThomas Petazzoni #define MVNETA_PHY_ADDR 0x2000 66c5aff182SThomas Petazzoni #define MVNETA_PHY_ADDR_MASK 0x1f 67c5aff182SThomas Petazzoni #define MVNETA_MBUS_RETRY 0x2010 68c5aff182SThomas Petazzoni #define MVNETA_UNIT_INTR_CAUSE 0x2080 69c5aff182SThomas Petazzoni #define MVNETA_UNIT_CONTROL 0x20B0 70c5aff182SThomas Petazzoni #define MVNETA_PHY_POLLING_ENABLE BIT(1) 71c5aff182SThomas Petazzoni #define MVNETA_WIN_BASE(w) (0x2200 + ((w) << 3)) 72c5aff182SThomas Petazzoni #define MVNETA_WIN_SIZE(w) (0x2204 + ((w) << 3)) 73c5aff182SThomas Petazzoni #define MVNETA_WIN_REMAP(w) (0x2280 + ((w) << 2)) 74c5aff182SThomas Petazzoni #define MVNETA_BASE_ADDR_ENABLE 0x2290 75db6ba9a5SMarcin Wojtas #define MVNETA_ACCESS_PROTECT_ENABLE 0x2294 76c5aff182SThomas Petazzoni #define MVNETA_PORT_CONFIG 0x2400 77c5aff182SThomas Petazzoni #define MVNETA_UNI_PROMISC_MODE BIT(0) 78c5aff182SThomas Petazzoni #define MVNETA_DEF_RXQ(q) ((q) << 1) 79c5aff182SThomas Petazzoni #define MVNETA_DEF_RXQ_ARP(q) ((q) << 4) 80c5aff182SThomas Petazzoni #define MVNETA_TX_UNSET_ERR_SUM BIT(12) 81c5aff182SThomas Petazzoni #define MVNETA_DEF_RXQ_TCP(q) ((q) << 16) 82c5aff182SThomas Petazzoni #define MVNETA_DEF_RXQ_UDP(q) ((q) << 19) 83c5aff182SThomas Petazzoni #define MVNETA_DEF_RXQ_BPDU(q) ((q) << 22) 84c5aff182SThomas Petazzoni #define MVNETA_RX_CSUM_WITH_PSEUDO_HDR BIT(25) 85c5aff182SThomas Petazzoni #define MVNETA_PORT_CONFIG_DEFL_VALUE(q) (MVNETA_DEF_RXQ(q) | \ 86c5aff182SThomas Petazzoni MVNETA_DEF_RXQ_ARP(q) | \ 87c5aff182SThomas Petazzoni MVNETA_DEF_RXQ_TCP(q) | \ 88c5aff182SThomas Petazzoni MVNETA_DEF_RXQ_UDP(q) | \ 89c5aff182SThomas Petazzoni MVNETA_DEF_RXQ_BPDU(q) | \ 90c5aff182SThomas Petazzoni MVNETA_TX_UNSET_ERR_SUM | \ 91c5aff182SThomas Petazzoni MVNETA_RX_CSUM_WITH_PSEUDO_HDR) 92c5aff182SThomas Petazzoni #define MVNETA_PORT_CONFIG_EXTEND 0x2404 93c5aff182SThomas Petazzoni #define MVNETA_MAC_ADDR_LOW 0x2414 94c5aff182SThomas Petazzoni #define MVNETA_MAC_ADDR_HIGH 0x2418 95c5aff182SThomas Petazzoni #define MVNETA_SDMA_CONFIG 0x241c 96c5aff182SThomas Petazzoni #define MVNETA_SDMA_BRST_SIZE_16 4 97c5aff182SThomas Petazzoni #define MVNETA_RX_BRST_SZ_MASK(burst) ((burst) << 1) 98c5aff182SThomas Petazzoni #define MVNETA_RX_NO_DATA_SWAP BIT(4) 99c5aff182SThomas Petazzoni #define MVNETA_TX_NO_DATA_SWAP BIT(5) 1009ad8fef6SThomas Petazzoni #define MVNETA_DESC_SWAP BIT(6) 101c5aff182SThomas Petazzoni #define MVNETA_TX_BRST_SZ_MASK(burst) ((burst) << 22) 102c5aff182SThomas Petazzoni #define MVNETA_PORT_STATUS 0x2444 103c5aff182SThomas Petazzoni #define MVNETA_TX_IN_PRGRS BIT(1) 104c5aff182SThomas Petazzoni #define MVNETA_TX_FIFO_EMPTY BIT(8) 105c5aff182SThomas Petazzoni #define MVNETA_RX_MIN_FRAME_SIZE 0x247c 1063f1dd4bcSThomas Petazzoni #define MVNETA_SERDES_CFG 0x24A0 1075445eaf3SArnaud Patard \(Rtp\) #define MVNETA_SGMII_SERDES_PROTO 0x0cc7 1083f1dd4bcSThomas Petazzoni #define MVNETA_QSGMII_SERDES_PROTO 0x0667 109c5aff182SThomas Petazzoni #define MVNETA_TYPE_PRIO 0x24bc 110c5aff182SThomas Petazzoni #define MVNETA_FORCE_UNI BIT(21) 111c5aff182SThomas Petazzoni #define MVNETA_TXQ_CMD_1 0x24e4 112c5aff182SThomas Petazzoni #define MVNETA_TXQ_CMD 0x2448 113c5aff182SThomas Petazzoni #define MVNETA_TXQ_DISABLE_SHIFT 8 114c5aff182SThomas Petazzoni #define MVNETA_TXQ_ENABLE_MASK 0x000000ff 115e483911fSAndrew Lunn #define MVNETA_RX_DISCARD_FRAME_COUNT 0x2484 116e483911fSAndrew Lunn #define MVNETA_OVERRUN_FRAME_COUNT 0x2488 117898b2970SStas Sergeev #define MVNETA_GMAC_CLOCK_DIVIDER 0x24f4 118898b2970SStas Sergeev #define MVNETA_GMAC_1MS_CLOCK_ENABLE BIT(31) 119c5aff182SThomas Petazzoni #define MVNETA_ACC_MODE 0x2500 120dc35a10fSMarcin Wojtas #define MVNETA_BM_ADDRESS 0x2504 121c5aff182SThomas Petazzoni #define MVNETA_CPU_MAP(cpu) (0x2540 + ((cpu) << 2)) 122c5aff182SThomas Petazzoni #define MVNETA_CPU_RXQ_ACCESS_ALL_MASK 0x000000ff 123c5aff182SThomas Petazzoni #define MVNETA_CPU_TXQ_ACCESS_ALL_MASK 0x0000ff00 1242dcf75e2SGregory CLEMENT #define MVNETA_CPU_RXQ_ACCESS(rxq) BIT(rxq) 12550bf8cb6SGregory CLEMENT #define MVNETA_CPU_TXQ_ACCESS(txq) BIT(txq + 8) 126c5aff182SThomas Petazzoni #define MVNETA_RXQ_TIME_COAL_REG(q) (0x2580 + ((q) << 2)) 12740ba35e7Swilly tarreau 1282dcf75e2SGregory CLEMENT /* Exception Interrupt Port/Queue Cause register 1292dcf75e2SGregory CLEMENT * 1302dcf75e2SGregory CLEMENT * Their behavior depend of the mapping done using the PCPX2Q 1312dcf75e2SGregory CLEMENT * registers. For a given CPU if the bit associated to a queue is not 1322dcf75e2SGregory CLEMENT * set, then for the register a read from this CPU will always return 1332dcf75e2SGregory CLEMENT * 0 and a write won't do anything 1342dcf75e2SGregory CLEMENT */ 13540ba35e7Swilly tarreau 136c5aff182SThomas Petazzoni #define MVNETA_INTR_NEW_CAUSE 0x25a0 137c5aff182SThomas Petazzoni #define MVNETA_INTR_NEW_MASK 0x25a4 13840ba35e7Swilly tarreau 13940ba35e7Swilly tarreau /* bits 0..7 = TXQ SENT, one bit per queue. 14040ba35e7Swilly tarreau * bits 8..15 = RXQ OCCUP, one bit per queue. 14140ba35e7Swilly tarreau * bits 16..23 = RXQ FREE, one bit per queue. 14240ba35e7Swilly tarreau * bit 29 = OLD_REG_SUM, see old reg ? 14340ba35e7Swilly tarreau * bit 30 = TX_ERR_SUM, one bit for 4 ports 14440ba35e7Swilly tarreau * bit 31 = MISC_SUM, one bit for 4 ports 14540ba35e7Swilly tarreau */ 14640ba35e7Swilly tarreau #define MVNETA_TX_INTR_MASK(nr_txqs) (((1 << nr_txqs) - 1) << 0) 14740ba35e7Swilly tarreau #define MVNETA_TX_INTR_MASK_ALL (0xff << 0) 14840ba35e7Swilly tarreau #define MVNETA_RX_INTR_MASK(nr_rxqs) (((1 << nr_rxqs) - 1) << 8) 14940ba35e7Swilly tarreau #define MVNETA_RX_INTR_MASK_ALL (0xff << 8) 150898b2970SStas Sergeev #define MVNETA_MISCINTR_INTR_MASK BIT(31) 15140ba35e7Swilly tarreau 152c5aff182SThomas Petazzoni #define MVNETA_INTR_OLD_CAUSE 0x25a8 153c5aff182SThomas Petazzoni #define MVNETA_INTR_OLD_MASK 0x25ac 15440ba35e7Swilly tarreau 15540ba35e7Swilly tarreau /* Data Path Port/Queue Cause Register */ 156c5aff182SThomas Petazzoni #define MVNETA_INTR_MISC_CAUSE 0x25b0 157c5aff182SThomas Petazzoni #define MVNETA_INTR_MISC_MASK 0x25b4 15840ba35e7Swilly tarreau 15940ba35e7Swilly tarreau #define MVNETA_CAUSE_PHY_STATUS_CHANGE BIT(0) 16040ba35e7Swilly tarreau #define MVNETA_CAUSE_LINK_CHANGE BIT(1) 16140ba35e7Swilly tarreau #define MVNETA_CAUSE_PTP BIT(4) 16240ba35e7Swilly tarreau 16340ba35e7Swilly tarreau #define MVNETA_CAUSE_INTERNAL_ADDR_ERR BIT(7) 16440ba35e7Swilly tarreau #define MVNETA_CAUSE_RX_OVERRUN BIT(8) 16540ba35e7Swilly tarreau #define MVNETA_CAUSE_RX_CRC_ERROR BIT(9) 16640ba35e7Swilly tarreau #define MVNETA_CAUSE_RX_LARGE_PKT BIT(10) 16740ba35e7Swilly tarreau #define MVNETA_CAUSE_TX_UNDERUN BIT(11) 16840ba35e7Swilly tarreau #define MVNETA_CAUSE_PRBS_ERR BIT(12) 16940ba35e7Swilly tarreau #define MVNETA_CAUSE_PSC_SYNC_CHANGE BIT(13) 17040ba35e7Swilly tarreau #define MVNETA_CAUSE_SERDES_SYNC_ERR BIT(14) 17140ba35e7Swilly tarreau 17240ba35e7Swilly tarreau #define MVNETA_CAUSE_BMU_ALLOC_ERR_SHIFT 16 17340ba35e7Swilly tarreau #define MVNETA_CAUSE_BMU_ALLOC_ERR_ALL_MASK (0xF << MVNETA_CAUSE_BMU_ALLOC_ERR_SHIFT) 17440ba35e7Swilly tarreau #define MVNETA_CAUSE_BMU_ALLOC_ERR_MASK(pool) (1 << (MVNETA_CAUSE_BMU_ALLOC_ERR_SHIFT + (pool))) 17540ba35e7Swilly tarreau 17640ba35e7Swilly tarreau #define MVNETA_CAUSE_TXQ_ERROR_SHIFT 24 17740ba35e7Swilly tarreau #define MVNETA_CAUSE_TXQ_ERROR_ALL_MASK (0xFF << MVNETA_CAUSE_TXQ_ERROR_SHIFT) 17840ba35e7Swilly tarreau #define MVNETA_CAUSE_TXQ_ERROR_MASK(q) (1 << (MVNETA_CAUSE_TXQ_ERROR_SHIFT + (q))) 17940ba35e7Swilly tarreau 180c5aff182SThomas Petazzoni #define MVNETA_INTR_ENABLE 0x25b8 181c5aff182SThomas Petazzoni #define MVNETA_TXQ_INTR_ENABLE_ALL_MASK 0x0000ff00 182dc1aadf6SMarcin Wojtas #define MVNETA_RXQ_INTR_ENABLE_ALL_MASK 0x000000ff 18340ba35e7Swilly tarreau 184c5aff182SThomas Petazzoni #define MVNETA_RXQ_CMD 0x2680 185c5aff182SThomas Petazzoni #define MVNETA_RXQ_DISABLE_SHIFT 8 186c5aff182SThomas Petazzoni #define MVNETA_RXQ_ENABLE_MASK 0x000000ff 187c5aff182SThomas Petazzoni #define MVETH_TXQ_TOKEN_COUNT_REG(q) (0x2700 + ((q) << 4)) 188c5aff182SThomas Petazzoni #define MVETH_TXQ_TOKEN_CFG_REG(q) (0x2704 + ((q) << 4)) 189c5aff182SThomas Petazzoni #define MVNETA_GMAC_CTRL_0 0x2c00 190c5aff182SThomas Petazzoni #define MVNETA_GMAC_MAX_RX_SIZE_SHIFT 2 191c5aff182SThomas Petazzoni #define MVNETA_GMAC_MAX_RX_SIZE_MASK 0x7ffc 19222f4bf8aSRussell King #define MVNETA_GMAC0_PORT_1000BASE_X BIT(1) 193c5aff182SThomas Petazzoni #define MVNETA_GMAC0_PORT_ENABLE BIT(0) 194c5aff182SThomas Petazzoni #define MVNETA_GMAC_CTRL_2 0x2c08 195898b2970SStas Sergeev #define MVNETA_GMAC2_INBAND_AN_ENABLE BIT(0) 196a79121d3SThomas Petazzoni #define MVNETA_GMAC2_PCS_ENABLE BIT(3) 197c5aff182SThomas Petazzoni #define MVNETA_GMAC2_PORT_RGMII BIT(4) 198c5aff182SThomas Petazzoni #define MVNETA_GMAC2_PORT_RESET BIT(6) 199c5aff182SThomas Petazzoni #define MVNETA_GMAC_STATUS 0x2c10 200c5aff182SThomas Petazzoni #define MVNETA_GMAC_LINK_UP BIT(0) 201c5aff182SThomas Petazzoni #define MVNETA_GMAC_SPEED_1000 BIT(1) 202c5aff182SThomas Petazzoni #define MVNETA_GMAC_SPEED_100 BIT(2) 203c5aff182SThomas Petazzoni #define MVNETA_GMAC_FULL_DUPLEX BIT(3) 204c5aff182SThomas Petazzoni #define MVNETA_GMAC_RX_FLOW_CTRL_ENABLE BIT(4) 205c5aff182SThomas Petazzoni #define MVNETA_GMAC_TX_FLOW_CTRL_ENABLE BIT(5) 206c5aff182SThomas Petazzoni #define MVNETA_GMAC_RX_FLOW_CTRL_ACTIVE BIT(6) 207c5aff182SThomas Petazzoni #define MVNETA_GMAC_TX_FLOW_CTRL_ACTIVE BIT(7) 208503f9aa9SRussell King #define MVNETA_GMAC_AN_COMPLETE BIT(11) 209503f9aa9SRussell King #define MVNETA_GMAC_SYNC_OK BIT(14) 210c5aff182SThomas Petazzoni #define MVNETA_GMAC_AUTONEG_CONFIG 0x2c0c 211c5aff182SThomas Petazzoni #define MVNETA_GMAC_FORCE_LINK_DOWN BIT(0) 212c5aff182SThomas Petazzoni #define MVNETA_GMAC_FORCE_LINK_PASS BIT(1) 213898b2970SStas Sergeev #define MVNETA_GMAC_INBAND_AN_ENABLE BIT(2) 21422f4bf8aSRussell King #define MVNETA_GMAC_AN_BYPASS_ENABLE BIT(3) 21522f4bf8aSRussell King #define MVNETA_GMAC_INBAND_RESTART_AN BIT(4) 216c5aff182SThomas Petazzoni #define MVNETA_GMAC_CONFIG_MII_SPEED BIT(5) 217c5aff182SThomas Petazzoni #define MVNETA_GMAC_CONFIG_GMII_SPEED BIT(6) 21871408602SThomas Petazzoni #define MVNETA_GMAC_AN_SPEED_EN BIT(7) 21922f4bf8aSRussell King #define MVNETA_GMAC_CONFIG_FLOW_CTRL BIT(8) 22022f4bf8aSRussell King #define MVNETA_GMAC_ADVERT_SYM_FLOW_CTRL BIT(9) 221898b2970SStas Sergeev #define MVNETA_GMAC_AN_FLOW_CTRL_EN BIT(11) 222c5aff182SThomas Petazzoni #define MVNETA_GMAC_CONFIG_FULL_DUPLEX BIT(12) 22371408602SThomas Petazzoni #define MVNETA_GMAC_AN_DUPLEX_EN BIT(13) 224e483911fSAndrew Lunn #define MVNETA_MIB_COUNTERS_BASE 0x3000 225c5aff182SThomas Petazzoni #define MVNETA_MIB_LATE_COLLISION 0x7c 226c5aff182SThomas Petazzoni #define MVNETA_DA_FILT_SPEC_MCAST 0x3400 227c5aff182SThomas Petazzoni #define MVNETA_DA_FILT_OTH_MCAST 0x3500 228c5aff182SThomas Petazzoni #define MVNETA_DA_FILT_UCAST_BASE 0x3600 229c5aff182SThomas Petazzoni #define MVNETA_TXQ_BASE_ADDR_REG(q) (0x3c00 + ((q) << 2)) 230c5aff182SThomas Petazzoni #define MVNETA_TXQ_SIZE_REG(q) (0x3c20 + ((q) << 2)) 231c5aff182SThomas Petazzoni #define MVNETA_TXQ_SENT_THRESH_ALL_MASK 0x3fff0000 232c5aff182SThomas Petazzoni #define MVNETA_TXQ_SENT_THRESH_MASK(coal) ((coal) << 16) 233c5aff182SThomas Petazzoni #define MVNETA_TXQ_UPDATE_REG(q) (0x3c60 + ((q) << 2)) 234c5aff182SThomas Petazzoni #define MVNETA_TXQ_DEC_SENT_SHIFT 16 2352a90f7e1SSimon Guinot #define MVNETA_TXQ_DEC_SENT_MASK 0xff 236c5aff182SThomas Petazzoni #define MVNETA_TXQ_STATUS_REG(q) (0x3c40 + ((q) << 2)) 237c5aff182SThomas Petazzoni #define MVNETA_TXQ_SENT_DESC_SHIFT 16 238c5aff182SThomas Petazzoni #define MVNETA_TXQ_SENT_DESC_MASK 0x3fff0000 239c5aff182SThomas Petazzoni #define MVNETA_PORT_TX_RESET 0x3cf0 240c5aff182SThomas Petazzoni #define MVNETA_PORT_TX_DMA_RESET BIT(0) 241c5aff182SThomas Petazzoni #define MVNETA_TX_MTU 0x3e0c 242c5aff182SThomas Petazzoni #define MVNETA_TX_TOKEN_SIZE 0x3e14 243c5aff182SThomas Petazzoni #define MVNETA_TX_TOKEN_SIZE_MAX 0xffffffff 244c5aff182SThomas Petazzoni #define MVNETA_TXQ_TOKEN_SIZE_REG(q) (0x3e40 + ((q) << 2)) 245c5aff182SThomas Petazzoni #define MVNETA_TXQ_TOKEN_SIZE_MAX 0x7fffffff 246c5aff182SThomas Petazzoni 2476d81f451SRussell King #define MVNETA_LPI_CTRL_0 0x2cc0 2486d81f451SRussell King #define MVNETA_LPI_CTRL_1 0x2cc4 2496d81f451SRussell King #define MVNETA_LPI_REQUEST_ENABLE BIT(0) 2506d81f451SRussell King #define MVNETA_LPI_CTRL_2 0x2cc8 2516d81f451SRussell King #define MVNETA_LPI_STATUS 0x2ccc 2526d81f451SRussell King 253c5aff182SThomas Petazzoni #define MVNETA_CAUSE_TXQ_SENT_DESC_ALL_MASK 0xff 254c5aff182SThomas Petazzoni 255c5aff182SThomas Petazzoni /* Descriptor ring Macros */ 256c5aff182SThomas Petazzoni #define MVNETA_QUEUE_NEXT_DESC(q, index) \ 257c5aff182SThomas Petazzoni (((index) < (q)->last_desc) ? ((index) + 1) : 0) 258c5aff182SThomas Petazzoni 259c5aff182SThomas Petazzoni /* Various constants */ 260c5aff182SThomas Petazzoni 261c5aff182SThomas Petazzoni /* Coalescing */ 26206708f81SDmitri Epshtein #define MVNETA_TXDONE_COAL_PKTS 0 /* interrupt per packet */ 263c5aff182SThomas Petazzoni #define MVNETA_RX_COAL_PKTS 32 264c5aff182SThomas Petazzoni #define MVNETA_RX_COAL_USEC 100 265c5aff182SThomas Petazzoni 2666a20c175SThomas Petazzoni /* The two bytes Marvell header. Either contains a special value used 267c5aff182SThomas Petazzoni * by Marvell switches when a specific hardware mode is enabled (not 268c5aff182SThomas Petazzoni * supported by this driver) or is filled automatically by zeroes on 269c5aff182SThomas Petazzoni * the RX side. Those two bytes being at the front of the Ethernet 270c5aff182SThomas Petazzoni * header, they allow to have the IP header aligned on a 4 bytes 271c5aff182SThomas Petazzoni * boundary automatically: the hardware skips those two bytes on its 272c5aff182SThomas Petazzoni * own. 273c5aff182SThomas Petazzoni */ 274c5aff182SThomas Petazzoni #define MVNETA_MH_SIZE 2 275c5aff182SThomas Petazzoni 276c5aff182SThomas Petazzoni #define MVNETA_VLAN_TAG_LEN 4 277c5aff182SThomas Petazzoni 2789110ee07SMarcin Wojtas #define MVNETA_TX_CSUM_DEF_SIZE 1600 279c5aff182SThomas Petazzoni #define MVNETA_TX_CSUM_MAX_SIZE 9800 280dc35a10fSMarcin Wojtas #define MVNETA_ACC_MODE_EXT1 1 281dc35a10fSMarcin Wojtas #define MVNETA_ACC_MODE_EXT2 2 282dc35a10fSMarcin Wojtas 283dc35a10fSMarcin Wojtas #define MVNETA_MAX_DECODE_WIN 6 284c5aff182SThomas Petazzoni 285c5aff182SThomas Petazzoni /* Timeout constants */ 286c5aff182SThomas Petazzoni #define MVNETA_TX_DISABLE_TIMEOUT_MSEC 1000 287c5aff182SThomas Petazzoni #define MVNETA_RX_DISABLE_TIMEOUT_MSEC 1000 288c5aff182SThomas Petazzoni #define MVNETA_TX_FIFO_EMPTY_TIMEOUT 10000 289c5aff182SThomas Petazzoni 290c5aff182SThomas Petazzoni #define MVNETA_TX_MTU_MAX 0x3ffff 291c5aff182SThomas Petazzoni 2929a401deaSGregory CLEMENT /* The RSS lookup table actually has 256 entries but we do not use 2939a401deaSGregory CLEMENT * them yet 2949a401deaSGregory CLEMENT */ 2959a401deaSGregory CLEMENT #define MVNETA_RSS_LU_TABLE_SIZE 1 2969a401deaSGregory CLEMENT 297c5aff182SThomas Petazzoni /* Max number of Rx descriptors */ 298c5aff182SThomas Petazzoni #define MVNETA_MAX_RXD 128 299c5aff182SThomas Petazzoni 300c5aff182SThomas Petazzoni /* Max number of Tx descriptors */ 301c5aff182SThomas Petazzoni #define MVNETA_MAX_TXD 532 302c5aff182SThomas Petazzoni 3038eef5f97SEzequiel Garcia /* Max number of allowed TCP segments for software TSO */ 3048eef5f97SEzequiel Garcia #define MVNETA_MAX_TSO_SEGS 100 3058eef5f97SEzequiel Garcia 3068eef5f97SEzequiel Garcia #define MVNETA_MAX_SKB_DESCS (MVNETA_MAX_TSO_SEGS * 2 + MAX_SKB_FRAGS) 3078eef5f97SEzequiel Garcia 308c5aff182SThomas Petazzoni /* descriptor aligned size */ 309c5aff182SThomas Petazzoni #define MVNETA_DESC_ALIGNED_SIZE 32 310c5aff182SThomas Petazzoni 3118d5047cfSMarcin Wojtas /* Number of bytes to be taken into account by HW when putting incoming data 3128d5047cfSMarcin Wojtas * to the buffers. It is needed in case NET_SKB_PAD exceeds maximum packet 3138d5047cfSMarcin Wojtas * offset supported in MVNETA_RXQ_CONFIG_REG(q) registers. 3148d5047cfSMarcin Wojtas */ 3158d5047cfSMarcin Wojtas #define MVNETA_RX_PKT_OFFSET_CORRECTION 64 3168d5047cfSMarcin Wojtas 317c5aff182SThomas Petazzoni #define MVNETA_RX_PKT_SIZE(mtu) \ 318c5aff182SThomas Petazzoni ALIGN((mtu) + MVNETA_MH_SIZE + MVNETA_VLAN_TAG_LEN + \ 319c5aff182SThomas Petazzoni ETH_HLEN + ETH_FCS_LEN, \ 320c66e98c9SJisheng Zhang cache_line_size()) 321c5aff182SThomas Petazzoni 3222e3173a3SEzequiel Garcia #define IS_TSO_HEADER(txq, addr) \ 3232e3173a3SEzequiel Garcia ((addr >= txq->tso_hdrs_phys) && \ 3242e3173a3SEzequiel Garcia (addr < txq->tso_hdrs_phys + txq->size * TSO_HEADER_SIZE)) 3252e3173a3SEzequiel Garcia 326dc35a10fSMarcin Wojtas #define MVNETA_RX_GET_BM_POOL_ID(rxd) \ 327dc35a10fSMarcin Wojtas (((rxd)->status & MVNETA_RXD_BM_POOL_MASK) >> MVNETA_RXD_BM_POOL_SHIFT) 328c5aff182SThomas Petazzoni 3296d81f451SRussell King enum { 3306d81f451SRussell King ETHTOOL_STAT_EEE_WAKEUP, 3316d81f451SRussell King ETHTOOL_MAX_STATS, 3326d81f451SRussell King }; 3336d81f451SRussell King 3349b0cdefaSRussell King struct mvneta_statistic { 3359b0cdefaSRussell King unsigned short offset; 3369b0cdefaSRussell King unsigned short type; 3379b0cdefaSRussell King const char name[ETH_GSTRING_LEN]; 3389b0cdefaSRussell King }; 3399b0cdefaSRussell King 3409b0cdefaSRussell King #define T_REG_32 32 3419b0cdefaSRussell King #define T_REG_64 64 3426d81f451SRussell King #define T_SW 1 3439b0cdefaSRussell King 3449b0cdefaSRussell King static const struct mvneta_statistic mvneta_statistics[] = { 3459b0cdefaSRussell King { 0x3000, T_REG_64, "good_octets_received", }, 3469b0cdefaSRussell King { 0x3010, T_REG_32, "good_frames_received", }, 3479b0cdefaSRussell King { 0x3008, T_REG_32, "bad_octets_received", }, 3489b0cdefaSRussell King { 0x3014, T_REG_32, "bad_frames_received", }, 3499b0cdefaSRussell King { 0x3018, T_REG_32, "broadcast_frames_received", }, 3509b0cdefaSRussell King { 0x301c, T_REG_32, "multicast_frames_received", }, 3519b0cdefaSRussell King { 0x3050, T_REG_32, "unrec_mac_control_received", }, 3529b0cdefaSRussell King { 0x3058, T_REG_32, "good_fc_received", }, 3539b0cdefaSRussell King { 0x305c, T_REG_32, "bad_fc_received", }, 3549b0cdefaSRussell King { 0x3060, T_REG_32, "undersize_received", }, 3559b0cdefaSRussell King { 0x3064, T_REG_32, "fragments_received", }, 3569b0cdefaSRussell King { 0x3068, T_REG_32, "oversize_received", }, 3579b0cdefaSRussell King { 0x306c, T_REG_32, "jabber_received", }, 3589b0cdefaSRussell King { 0x3070, T_REG_32, "mac_receive_error", }, 3599b0cdefaSRussell King { 0x3074, T_REG_32, "bad_crc_event", }, 3609b0cdefaSRussell King { 0x3078, T_REG_32, "collision", }, 3619b0cdefaSRussell King { 0x307c, T_REG_32, "late_collision", }, 3629b0cdefaSRussell King { 0x2484, T_REG_32, "rx_discard", }, 3639b0cdefaSRussell King { 0x2488, T_REG_32, "rx_overrun", }, 3649b0cdefaSRussell King { 0x3020, T_REG_32, "frames_64_octets", }, 3659b0cdefaSRussell King { 0x3024, T_REG_32, "frames_65_to_127_octets", }, 3669b0cdefaSRussell King { 0x3028, T_REG_32, "frames_128_to_255_octets", }, 3679b0cdefaSRussell King { 0x302c, T_REG_32, "frames_256_to_511_octets", }, 3689b0cdefaSRussell King { 0x3030, T_REG_32, "frames_512_to_1023_octets", }, 3699b0cdefaSRussell King { 0x3034, T_REG_32, "frames_1024_to_max_octets", }, 3709b0cdefaSRussell King { 0x3038, T_REG_64, "good_octets_sent", }, 3719b0cdefaSRussell King { 0x3040, T_REG_32, "good_frames_sent", }, 3729b0cdefaSRussell King { 0x3044, T_REG_32, "excessive_collision", }, 3739b0cdefaSRussell King { 0x3048, T_REG_32, "multicast_frames_sent", }, 3749b0cdefaSRussell King { 0x304c, T_REG_32, "broadcast_frames_sent", }, 3759b0cdefaSRussell King { 0x3054, T_REG_32, "fc_sent", }, 3769b0cdefaSRussell King { 0x300c, T_REG_32, "internal_mac_transmit_err", }, 3776d81f451SRussell King { ETHTOOL_STAT_EEE_WAKEUP, T_SW, "eee_wakeup_errors", }, 3789b0cdefaSRussell King }; 3799b0cdefaSRussell King 38074c41b04Swilly tarreau struct mvneta_pcpu_stats { 381c5aff182SThomas Petazzoni struct u64_stats_sync syncp; 38274c41b04Swilly tarreau u64 rx_packets; 38374c41b04Swilly tarreau u64 rx_bytes; 38474c41b04Swilly tarreau u64 tx_packets; 38574c41b04Swilly tarreau u64 tx_bytes; 386c5aff182SThomas Petazzoni }; 387c5aff182SThomas Petazzoni 38812bb03b4SMaxime Ripard struct mvneta_pcpu_port { 38912bb03b4SMaxime Ripard /* Pointer to the shared port */ 39012bb03b4SMaxime Ripard struct mvneta_port *pp; 39112bb03b4SMaxime Ripard 39212bb03b4SMaxime Ripard /* Pointer to the CPU-local NAPI struct */ 39312bb03b4SMaxime Ripard struct napi_struct napi; 39412bb03b4SMaxime Ripard 39512bb03b4SMaxime Ripard /* Cause of the previous interrupt */ 39612bb03b4SMaxime Ripard u32 cause_rx_tx; 39712bb03b4SMaxime Ripard }; 39812bb03b4SMaxime Ripard 399c5aff182SThomas Petazzoni struct mvneta_port { 400dc35a10fSMarcin Wojtas u8 id; 40112bb03b4SMaxime Ripard struct mvneta_pcpu_port __percpu *ports; 40212bb03b4SMaxime Ripard struct mvneta_pcpu_stats __percpu *stats; 40312bb03b4SMaxime Ripard 404c5aff182SThomas Petazzoni int pkt_size; 4058ec2cd48Swilly tarreau unsigned int frag_size; 406c5aff182SThomas Petazzoni void __iomem *base; 407c5aff182SThomas Petazzoni struct mvneta_rx_queue *rxqs; 408c5aff182SThomas Petazzoni struct mvneta_tx_queue *txqs; 409c5aff182SThomas Petazzoni struct net_device *dev; 41084a3f4dbSSebastian Andrzej Siewior struct hlist_node node_online; 41184a3f4dbSSebastian Andrzej Siewior struct hlist_node node_dead; 41290b74c01SGregory CLEMENT int rxq_def; 4135888511eSGregory CLEMENT /* Protect the access to the percpu interrupt registers, 4145888511eSGregory CLEMENT * ensuring that the configuration remains coherent. 4155888511eSGregory CLEMENT */ 4165888511eSGregory CLEMENT spinlock_t lock; 417120cfa50SGregory CLEMENT bool is_stopped; 418c5aff182SThomas Petazzoni 4192636ac3cSMarcin Wojtas u32 cause_rx_tx; 4202636ac3cSMarcin Wojtas struct napi_struct napi; 4212636ac3cSMarcin Wojtas 422c5aff182SThomas Petazzoni /* Core clock */ 423189dd626SThomas Petazzoni struct clk *clk; 42415cc4a4aSJisheng Zhang /* AXI clock */ 42515cc4a4aSJisheng Zhang struct clk *clk_bus; 426c5aff182SThomas Petazzoni u8 mcast_count[256]; 427c5aff182SThomas Petazzoni u16 tx_ring_size; 428c5aff182SThomas Petazzoni u16 rx_ring_size; 429c5aff182SThomas Petazzoni 430c5aff182SThomas Petazzoni phy_interface_t phy_interface; 431503f9aa9SRussell King struct device_node *dn; 432b65657fcSSimon Guinot unsigned int tx_csum_limit; 433503f9aa9SRussell King struct phylink *phylink; 4349b0cdefaSRussell King 435dc35a10fSMarcin Wojtas struct mvneta_bm *bm_priv; 436dc35a10fSMarcin Wojtas struct mvneta_bm_pool *pool_long; 437dc35a10fSMarcin Wojtas struct mvneta_bm_pool *pool_short; 438dc35a10fSMarcin Wojtas int bm_win_id; 439dc35a10fSMarcin Wojtas 4406d81f451SRussell King bool eee_enabled; 4416d81f451SRussell King bool eee_active; 4426d81f451SRussell King bool tx_lpi_enabled; 4436d81f451SRussell King 4449b0cdefaSRussell King u64 ethtool_stats[ARRAY_SIZE(mvneta_statistics)]; 4459a401deaSGregory CLEMENT 4469a401deaSGregory CLEMENT u32 indir[MVNETA_RSS_LU_TABLE_SIZE]; 4472636ac3cSMarcin Wojtas 4482636ac3cSMarcin Wojtas /* Flags for special SoC configurations */ 4492636ac3cSMarcin Wojtas bool neta_armada3700; 4508d5047cfSMarcin Wojtas u16 rx_offset_correction; 4519768b45cSJane Li const struct mbus_dram_target_info *dram_target_info; 452c5aff182SThomas Petazzoni }; 453c5aff182SThomas Petazzoni 4546a20c175SThomas Petazzoni /* The mvneta_tx_desc and mvneta_rx_desc structures describe the 455c5aff182SThomas Petazzoni * layout of the transmit and reception DMA descriptors, and their 456c5aff182SThomas Petazzoni * layout is therefore defined by the hardware design 457c5aff182SThomas Petazzoni */ 4586083ed44SThomas Petazzoni 459c5aff182SThomas Petazzoni #define MVNETA_TX_L3_OFF_SHIFT 0 460c5aff182SThomas Petazzoni #define MVNETA_TX_IP_HLEN_SHIFT 8 461c5aff182SThomas Petazzoni #define MVNETA_TX_L4_UDP BIT(16) 462c5aff182SThomas Petazzoni #define MVNETA_TX_L3_IP6 BIT(17) 463c5aff182SThomas Petazzoni #define MVNETA_TXD_IP_CSUM BIT(18) 464c5aff182SThomas Petazzoni #define MVNETA_TXD_Z_PAD BIT(19) 465c5aff182SThomas Petazzoni #define MVNETA_TXD_L_DESC BIT(20) 466c5aff182SThomas Petazzoni #define MVNETA_TXD_F_DESC BIT(21) 467c5aff182SThomas Petazzoni #define MVNETA_TXD_FLZ_DESC (MVNETA_TXD_Z_PAD | \ 468c5aff182SThomas Petazzoni MVNETA_TXD_L_DESC | \ 469c5aff182SThomas Petazzoni MVNETA_TXD_F_DESC) 470c5aff182SThomas Petazzoni #define MVNETA_TX_L4_CSUM_FULL BIT(30) 471c5aff182SThomas Petazzoni #define MVNETA_TX_L4_CSUM_NOT BIT(31) 472c5aff182SThomas Petazzoni 473c5aff182SThomas Petazzoni #define MVNETA_RXD_ERR_CRC 0x0 474dc35a10fSMarcin Wojtas #define MVNETA_RXD_BM_POOL_SHIFT 13 475dc35a10fSMarcin Wojtas #define MVNETA_RXD_BM_POOL_MASK (BIT(13) | BIT(14)) 476c5aff182SThomas Petazzoni #define MVNETA_RXD_ERR_SUMMARY BIT(16) 477c5aff182SThomas Petazzoni #define MVNETA_RXD_ERR_OVERRUN BIT(17) 478c5aff182SThomas Petazzoni #define MVNETA_RXD_ERR_LEN BIT(18) 479c5aff182SThomas Petazzoni #define MVNETA_RXD_ERR_RESOURCE (BIT(17) | BIT(18)) 480c5aff182SThomas Petazzoni #define MVNETA_RXD_ERR_CODE_MASK (BIT(17) | BIT(18)) 481c5aff182SThomas Petazzoni #define MVNETA_RXD_L3_IP4 BIT(25) 482c5aff182SThomas Petazzoni #define MVNETA_RXD_FIRST_LAST_DESC (BIT(26) | BIT(27)) 483c5aff182SThomas Petazzoni #define MVNETA_RXD_L4_CSUM_OK BIT(30) 484c5aff182SThomas Petazzoni 4859ad8fef6SThomas Petazzoni #if defined(__LITTLE_ENDIAN) 4866083ed44SThomas Petazzoni struct mvneta_tx_desc { 4876083ed44SThomas Petazzoni u32 command; /* Options used by HW for packet transmitting.*/ 4886083ed44SThomas Petazzoni u16 reserverd1; /* csum_l4 (for future use) */ 4896083ed44SThomas Petazzoni u16 data_size; /* Data size of transmitted packet in bytes */ 4906083ed44SThomas Petazzoni u32 buf_phys_addr; /* Physical addr of transmitted buffer */ 4916083ed44SThomas Petazzoni u32 reserved2; /* hw_cmd - (for future use, PMT) */ 4926083ed44SThomas Petazzoni u32 reserved3[4]; /* Reserved - (for future use) */ 4936083ed44SThomas Petazzoni }; 4946083ed44SThomas Petazzoni 4956083ed44SThomas Petazzoni struct mvneta_rx_desc { 4966083ed44SThomas Petazzoni u32 status; /* Info about received packet */ 497c5aff182SThomas Petazzoni u16 reserved1; /* pnc_info - (for future use, PnC) */ 498c5aff182SThomas Petazzoni u16 data_size; /* Size of received packet in bytes */ 4996083ed44SThomas Petazzoni 500c5aff182SThomas Petazzoni u32 buf_phys_addr; /* Physical address of the buffer */ 501c5aff182SThomas Petazzoni u32 reserved2; /* pnc_flow_id (for future use, PnC) */ 5026083ed44SThomas Petazzoni 503c5aff182SThomas Petazzoni u32 buf_cookie; /* cookie for access to RX buffer in rx path */ 504c5aff182SThomas Petazzoni u16 reserved3; /* prefetch_cmd, for future use */ 505c5aff182SThomas Petazzoni u16 reserved4; /* csum_l4 - (for future use, PnC) */ 5066083ed44SThomas Petazzoni 507c5aff182SThomas Petazzoni u32 reserved5; /* pnc_extra PnC (for future use, PnC) */ 508c5aff182SThomas Petazzoni u32 reserved6; /* hw_cmd (for future use, PnC and HWF) */ 509c5aff182SThomas Petazzoni }; 5109ad8fef6SThomas Petazzoni #else 5119ad8fef6SThomas Petazzoni struct mvneta_tx_desc { 5129ad8fef6SThomas Petazzoni u16 data_size; /* Data size of transmitted packet in bytes */ 5139ad8fef6SThomas Petazzoni u16 reserverd1; /* csum_l4 (for future use) */ 5149ad8fef6SThomas Petazzoni u32 command; /* Options used by HW for packet transmitting.*/ 5159ad8fef6SThomas Petazzoni u32 reserved2; /* hw_cmd - (for future use, PMT) */ 5169ad8fef6SThomas Petazzoni u32 buf_phys_addr; /* Physical addr of transmitted buffer */ 5179ad8fef6SThomas Petazzoni u32 reserved3[4]; /* Reserved - (for future use) */ 5189ad8fef6SThomas Petazzoni }; 5199ad8fef6SThomas Petazzoni 5209ad8fef6SThomas Petazzoni struct mvneta_rx_desc { 5219ad8fef6SThomas Petazzoni u16 data_size; /* Size of received packet in bytes */ 5229ad8fef6SThomas Petazzoni u16 reserved1; /* pnc_info - (for future use, PnC) */ 5239ad8fef6SThomas Petazzoni u32 status; /* Info about received packet */ 5249ad8fef6SThomas Petazzoni 5259ad8fef6SThomas Petazzoni u32 reserved2; /* pnc_flow_id (for future use, PnC) */ 5269ad8fef6SThomas Petazzoni u32 buf_phys_addr; /* Physical address of the buffer */ 5279ad8fef6SThomas Petazzoni 5289ad8fef6SThomas Petazzoni u16 reserved4; /* csum_l4 - (for future use, PnC) */ 5299ad8fef6SThomas Petazzoni u16 reserved3; /* prefetch_cmd, for future use */ 5309ad8fef6SThomas Petazzoni u32 buf_cookie; /* cookie for access to RX buffer in rx path */ 5319ad8fef6SThomas Petazzoni 5329ad8fef6SThomas Petazzoni u32 reserved5; /* pnc_extra PnC (for future use, PnC) */ 5339ad8fef6SThomas Petazzoni u32 reserved6; /* hw_cmd (for future use, PnC and HWF) */ 5349ad8fef6SThomas Petazzoni }; 5359ad8fef6SThomas Petazzoni #endif 536c5aff182SThomas Petazzoni 537c5aff182SThomas Petazzoni struct mvneta_tx_queue { 538c5aff182SThomas Petazzoni /* Number of this TX queue, in the range 0-7 */ 539c5aff182SThomas Petazzoni u8 id; 540c5aff182SThomas Petazzoni 541c5aff182SThomas Petazzoni /* Number of TX DMA descriptors in the descriptor ring */ 542c5aff182SThomas Petazzoni int size; 543c5aff182SThomas Petazzoni 544c5aff182SThomas Petazzoni /* Number of currently used TX DMA descriptor in the 5456a20c175SThomas Petazzoni * descriptor ring 5466a20c175SThomas Petazzoni */ 547c5aff182SThomas Petazzoni int count; 5482a90f7e1SSimon Guinot int pending; 5498eef5f97SEzequiel Garcia int tx_stop_threshold; 5508eef5f97SEzequiel Garcia int tx_wake_threshold; 551c5aff182SThomas Petazzoni 552c5aff182SThomas Petazzoni /* Array of transmitted skb */ 553c5aff182SThomas Petazzoni struct sk_buff **tx_skb; 554c5aff182SThomas Petazzoni 555c5aff182SThomas Petazzoni /* Index of last TX DMA descriptor that was inserted */ 556c5aff182SThomas Petazzoni int txq_put_index; 557c5aff182SThomas Petazzoni 558c5aff182SThomas Petazzoni /* Index of the TX DMA descriptor to be cleaned up */ 559c5aff182SThomas Petazzoni int txq_get_index; 560c5aff182SThomas Petazzoni 561c5aff182SThomas Petazzoni u32 done_pkts_coal; 562c5aff182SThomas Petazzoni 563c5aff182SThomas Petazzoni /* Virtual address of the TX DMA descriptors array */ 564c5aff182SThomas Petazzoni struct mvneta_tx_desc *descs; 565c5aff182SThomas Petazzoni 566c5aff182SThomas Petazzoni /* DMA address of the TX DMA descriptors array */ 567c5aff182SThomas Petazzoni dma_addr_t descs_phys; 568c5aff182SThomas Petazzoni 569c5aff182SThomas Petazzoni /* Index of the last TX DMA descriptor */ 570c5aff182SThomas Petazzoni int last_desc; 571c5aff182SThomas Petazzoni 572c5aff182SThomas Petazzoni /* Index of the next TX DMA descriptor to process */ 573c5aff182SThomas Petazzoni int next_desc_to_proc; 5742adb719dSEzequiel Garcia 5752adb719dSEzequiel Garcia /* DMA buffers for TSO headers */ 5762adb719dSEzequiel Garcia char *tso_hdrs; 5772adb719dSEzequiel Garcia 5782adb719dSEzequiel Garcia /* DMA address of TSO headers */ 5792adb719dSEzequiel Garcia dma_addr_t tso_hdrs_phys; 58050bf8cb6SGregory CLEMENT 58150bf8cb6SGregory CLEMENT /* Affinity mask for CPUs*/ 58250bf8cb6SGregory CLEMENT cpumask_t affinity_mask; 583c5aff182SThomas Petazzoni }; 584c5aff182SThomas Petazzoni 585c5aff182SThomas Petazzoni struct mvneta_rx_queue { 586c5aff182SThomas Petazzoni /* rx queue number, in the range 0-7 */ 587c5aff182SThomas Petazzoni u8 id; 588c5aff182SThomas Petazzoni 589c5aff182SThomas Petazzoni /* num of rx descriptors in the rx descriptor ring */ 590c5aff182SThomas Petazzoni int size; 591c5aff182SThomas Petazzoni 592c5aff182SThomas Petazzoni /* counter of times when mvneta_refill() failed */ 593c5aff182SThomas Petazzoni int missed; 594c5aff182SThomas Petazzoni 595c5aff182SThomas Petazzoni u32 pkts_coal; 596c5aff182SThomas Petazzoni u32 time_coal; 597c5aff182SThomas Petazzoni 598f88bee1cSGregory CLEMENT /* Virtual address of the RX buffer */ 599f88bee1cSGregory CLEMENT void **buf_virt_addr; 600f88bee1cSGregory CLEMENT 601c5aff182SThomas Petazzoni /* Virtual address of the RX DMA descriptors array */ 602c5aff182SThomas Petazzoni struct mvneta_rx_desc *descs; 603c5aff182SThomas Petazzoni 604c5aff182SThomas Petazzoni /* DMA address of the RX DMA descriptors array */ 605c5aff182SThomas Petazzoni dma_addr_t descs_phys; 606c5aff182SThomas Petazzoni 607c5aff182SThomas Petazzoni /* Index of the last RX DMA descriptor */ 608c5aff182SThomas Petazzoni int last_desc; 609c5aff182SThomas Petazzoni 610c5aff182SThomas Petazzoni /* Index of the next RX DMA descriptor to process */ 611c5aff182SThomas Petazzoni int next_desc_to_proc; 612c5aff182SThomas Petazzoni }; 613c5aff182SThomas Petazzoni 61484a3f4dbSSebastian Andrzej Siewior static enum cpuhp_state online_hpstate; 615edadb7faSEzequiel Garcia /* The hardware supports eight (8) rx queues, but we are only allowing 616edadb7faSEzequiel Garcia * the first one to be used. Therefore, let's just allocate one queue. 617edadb7faSEzequiel Garcia */ 618d8936657SMaxime Ripard static int rxq_number = 8; 619c5aff182SThomas Petazzoni static int txq_number = 8; 620c5aff182SThomas Petazzoni 621c5aff182SThomas Petazzoni static int rxq_def; 622c5aff182SThomas Petazzoni 623f19fadfcSwilly tarreau static int rx_copybreak __read_mostly = 256; 624f19fadfcSwilly tarreau 625dc35a10fSMarcin Wojtas /* HW BM need that each port be identify by a unique ID */ 626dc35a10fSMarcin Wojtas static int global_port_id; 627dc35a10fSMarcin Wojtas 628c5aff182SThomas Petazzoni #define MVNETA_DRIVER_NAME "mvneta" 629c5aff182SThomas Petazzoni #define MVNETA_DRIVER_VERSION "1.0" 630c5aff182SThomas Petazzoni 631c5aff182SThomas Petazzoni /* Utility/helper methods */ 632c5aff182SThomas Petazzoni 633c5aff182SThomas Petazzoni /* Write helper method */ 634c5aff182SThomas Petazzoni static void mvreg_write(struct mvneta_port *pp, u32 offset, u32 data) 635c5aff182SThomas Petazzoni { 636c5aff182SThomas Petazzoni writel(data, pp->base + offset); 637c5aff182SThomas Petazzoni } 638c5aff182SThomas Petazzoni 639c5aff182SThomas Petazzoni /* Read helper method */ 640c5aff182SThomas Petazzoni static u32 mvreg_read(struct mvneta_port *pp, u32 offset) 641c5aff182SThomas Petazzoni { 642c5aff182SThomas Petazzoni return readl(pp->base + offset); 643c5aff182SThomas Petazzoni } 644c5aff182SThomas Petazzoni 645c5aff182SThomas Petazzoni /* Increment txq get counter */ 646c5aff182SThomas Petazzoni static void mvneta_txq_inc_get(struct mvneta_tx_queue *txq) 647c5aff182SThomas Petazzoni { 648c5aff182SThomas Petazzoni txq->txq_get_index++; 649c5aff182SThomas Petazzoni if (txq->txq_get_index == txq->size) 650c5aff182SThomas Petazzoni txq->txq_get_index = 0; 651c5aff182SThomas Petazzoni } 652c5aff182SThomas Petazzoni 653c5aff182SThomas Petazzoni /* Increment txq put counter */ 654c5aff182SThomas Petazzoni static void mvneta_txq_inc_put(struct mvneta_tx_queue *txq) 655c5aff182SThomas Petazzoni { 656c5aff182SThomas Petazzoni txq->txq_put_index++; 657c5aff182SThomas Petazzoni if (txq->txq_put_index == txq->size) 658c5aff182SThomas Petazzoni txq->txq_put_index = 0; 659c5aff182SThomas Petazzoni } 660c5aff182SThomas Petazzoni 661c5aff182SThomas Petazzoni 662c5aff182SThomas Petazzoni /* Clear all MIB counters */ 663c5aff182SThomas Petazzoni static void mvneta_mib_counters_clear(struct mvneta_port *pp) 664c5aff182SThomas Petazzoni { 665c5aff182SThomas Petazzoni int i; 666c5aff182SThomas Petazzoni u32 dummy; 667c5aff182SThomas Petazzoni 668c5aff182SThomas Petazzoni /* Perform dummy reads from MIB counters */ 669c5aff182SThomas Petazzoni for (i = 0; i < MVNETA_MIB_LATE_COLLISION; i += 4) 670c5aff182SThomas Petazzoni dummy = mvreg_read(pp, (MVNETA_MIB_COUNTERS_BASE + i)); 671e483911fSAndrew Lunn dummy = mvreg_read(pp, MVNETA_RX_DISCARD_FRAME_COUNT); 672e483911fSAndrew Lunn dummy = mvreg_read(pp, MVNETA_OVERRUN_FRAME_COUNT); 673c5aff182SThomas Petazzoni } 674c5aff182SThomas Petazzoni 675c5aff182SThomas Petazzoni /* Get System Network Statistics */ 676bc1f4470Sstephen hemminger static void 6772dc0d2b4SBaoyou Xie mvneta_get_stats64(struct net_device *dev, 678c5aff182SThomas Petazzoni struct rtnl_link_stats64 *stats) 679c5aff182SThomas Petazzoni { 680c5aff182SThomas Petazzoni struct mvneta_port *pp = netdev_priv(dev); 681c5aff182SThomas Petazzoni unsigned int start; 68274c41b04Swilly tarreau int cpu; 683c5aff182SThomas Petazzoni 68474c41b04Swilly tarreau for_each_possible_cpu(cpu) { 68574c41b04Swilly tarreau struct mvneta_pcpu_stats *cpu_stats; 68674c41b04Swilly tarreau u64 rx_packets; 68774c41b04Swilly tarreau u64 rx_bytes; 68874c41b04Swilly tarreau u64 tx_packets; 68974c41b04Swilly tarreau u64 tx_bytes; 690c5aff182SThomas Petazzoni 69174c41b04Swilly tarreau cpu_stats = per_cpu_ptr(pp->stats, cpu); 692c5aff182SThomas Petazzoni do { 69357a7744eSEric W. Biederman start = u64_stats_fetch_begin_irq(&cpu_stats->syncp); 69474c41b04Swilly tarreau rx_packets = cpu_stats->rx_packets; 69574c41b04Swilly tarreau rx_bytes = cpu_stats->rx_bytes; 69674c41b04Swilly tarreau tx_packets = cpu_stats->tx_packets; 69774c41b04Swilly tarreau tx_bytes = cpu_stats->tx_bytes; 69857a7744eSEric W. Biederman } while (u64_stats_fetch_retry_irq(&cpu_stats->syncp, start)); 699c5aff182SThomas Petazzoni 70074c41b04Swilly tarreau stats->rx_packets += rx_packets; 70174c41b04Swilly tarreau stats->rx_bytes += rx_bytes; 70274c41b04Swilly tarreau stats->tx_packets += tx_packets; 70374c41b04Swilly tarreau stats->tx_bytes += tx_bytes; 70474c41b04Swilly tarreau } 705c5aff182SThomas Petazzoni 706c5aff182SThomas Petazzoni stats->rx_errors = dev->stats.rx_errors; 707c5aff182SThomas Petazzoni stats->rx_dropped = dev->stats.rx_dropped; 708c5aff182SThomas Petazzoni 709c5aff182SThomas Petazzoni stats->tx_dropped = dev->stats.tx_dropped; 710c5aff182SThomas Petazzoni } 711c5aff182SThomas Petazzoni 712c5aff182SThomas Petazzoni /* Rx descriptors helper methods */ 713c5aff182SThomas Petazzoni 7145428213cSwilly tarreau /* Checks whether the RX descriptor having this status is both the first 7155428213cSwilly tarreau * and the last descriptor for the RX packet. Each RX packet is currently 716c5aff182SThomas Petazzoni * received through a single RX descriptor, so not having each RX 717c5aff182SThomas Petazzoni * descriptor with its first and last bits set is an error 718c5aff182SThomas Petazzoni */ 7195428213cSwilly tarreau static int mvneta_rxq_desc_is_first_last(u32 status) 720c5aff182SThomas Petazzoni { 7215428213cSwilly tarreau return (status & MVNETA_RXD_FIRST_LAST_DESC) == 722c5aff182SThomas Petazzoni MVNETA_RXD_FIRST_LAST_DESC; 723c5aff182SThomas Petazzoni } 724c5aff182SThomas Petazzoni 725c5aff182SThomas Petazzoni /* Add number of descriptors ready to receive new packets */ 726c5aff182SThomas Petazzoni static void mvneta_rxq_non_occup_desc_add(struct mvneta_port *pp, 727c5aff182SThomas Petazzoni struct mvneta_rx_queue *rxq, 728c5aff182SThomas Petazzoni int ndescs) 729c5aff182SThomas Petazzoni { 730c5aff182SThomas Petazzoni /* Only MVNETA_RXQ_ADD_NON_OCCUPIED_MAX (255) descriptors can 7316a20c175SThomas Petazzoni * be added at once 7326a20c175SThomas Petazzoni */ 733c5aff182SThomas Petazzoni while (ndescs > MVNETA_RXQ_ADD_NON_OCCUPIED_MAX) { 734c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id), 735c5aff182SThomas Petazzoni (MVNETA_RXQ_ADD_NON_OCCUPIED_MAX << 736c5aff182SThomas Petazzoni MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT)); 737c5aff182SThomas Petazzoni ndescs -= MVNETA_RXQ_ADD_NON_OCCUPIED_MAX; 738c5aff182SThomas Petazzoni } 739c5aff182SThomas Petazzoni 740c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id), 741c5aff182SThomas Petazzoni (ndescs << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT)); 742c5aff182SThomas Petazzoni } 743c5aff182SThomas Petazzoni 744c5aff182SThomas Petazzoni /* Get number of RX descriptors occupied by received packets */ 745c5aff182SThomas Petazzoni static int mvneta_rxq_busy_desc_num_get(struct mvneta_port *pp, 746c5aff182SThomas Petazzoni struct mvneta_rx_queue *rxq) 747c5aff182SThomas Petazzoni { 748c5aff182SThomas Petazzoni u32 val; 749c5aff182SThomas Petazzoni 750c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_RXQ_STATUS_REG(rxq->id)); 751c5aff182SThomas Petazzoni return val & MVNETA_RXQ_OCCUPIED_ALL_MASK; 752c5aff182SThomas Petazzoni } 753c5aff182SThomas Petazzoni 7546a20c175SThomas Petazzoni /* Update num of rx desc called upon return from rx path or 755c5aff182SThomas Petazzoni * from mvneta_rxq_drop_pkts(). 756c5aff182SThomas Petazzoni */ 757c5aff182SThomas Petazzoni static void mvneta_rxq_desc_num_update(struct mvneta_port *pp, 758c5aff182SThomas Petazzoni struct mvneta_rx_queue *rxq, 759c5aff182SThomas Petazzoni int rx_done, int rx_filled) 760c5aff182SThomas Petazzoni { 761c5aff182SThomas Petazzoni u32 val; 762c5aff182SThomas Petazzoni 763c5aff182SThomas Petazzoni if ((rx_done <= 0xff) && (rx_filled <= 0xff)) { 764c5aff182SThomas Petazzoni val = rx_done | 765c5aff182SThomas Petazzoni (rx_filled << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT); 766c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id), val); 767c5aff182SThomas Petazzoni return; 768c5aff182SThomas Petazzoni } 769c5aff182SThomas Petazzoni 770c5aff182SThomas Petazzoni /* Only 255 descriptors can be added at once */ 771c5aff182SThomas Petazzoni while ((rx_done > 0) || (rx_filled > 0)) { 772c5aff182SThomas Petazzoni if (rx_done <= 0xff) { 773c5aff182SThomas Petazzoni val = rx_done; 774c5aff182SThomas Petazzoni rx_done = 0; 775c5aff182SThomas Petazzoni } else { 776c5aff182SThomas Petazzoni val = 0xff; 777c5aff182SThomas Petazzoni rx_done -= 0xff; 778c5aff182SThomas Petazzoni } 779c5aff182SThomas Petazzoni if (rx_filled <= 0xff) { 780c5aff182SThomas Petazzoni val |= rx_filled << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT; 781c5aff182SThomas Petazzoni rx_filled = 0; 782c5aff182SThomas Petazzoni } else { 783c5aff182SThomas Petazzoni val |= 0xff << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT; 784c5aff182SThomas Petazzoni rx_filled -= 0xff; 785c5aff182SThomas Petazzoni } 786c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id), val); 787c5aff182SThomas Petazzoni } 788c5aff182SThomas Petazzoni } 789c5aff182SThomas Petazzoni 790c5aff182SThomas Petazzoni /* Get pointer to next RX descriptor to be processed by SW */ 791c5aff182SThomas Petazzoni static struct mvneta_rx_desc * 792c5aff182SThomas Petazzoni mvneta_rxq_next_desc_get(struct mvneta_rx_queue *rxq) 793c5aff182SThomas Petazzoni { 794c5aff182SThomas Petazzoni int rx_desc = rxq->next_desc_to_proc; 795c5aff182SThomas Petazzoni 796c5aff182SThomas Petazzoni rxq->next_desc_to_proc = MVNETA_QUEUE_NEXT_DESC(rxq, rx_desc); 79734e4179dSwilly tarreau prefetch(rxq->descs + rxq->next_desc_to_proc); 798c5aff182SThomas Petazzoni return rxq->descs + rx_desc; 799c5aff182SThomas Petazzoni } 800c5aff182SThomas Petazzoni 801c5aff182SThomas Petazzoni /* Change maximum receive size of the port. */ 802c5aff182SThomas Petazzoni static void mvneta_max_rx_size_set(struct mvneta_port *pp, int max_rx_size) 803c5aff182SThomas Petazzoni { 804c5aff182SThomas Petazzoni u32 val; 805c5aff182SThomas Petazzoni 806c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_GMAC_CTRL_0); 807c5aff182SThomas Petazzoni val &= ~MVNETA_GMAC_MAX_RX_SIZE_MASK; 808c5aff182SThomas Petazzoni val |= ((max_rx_size - MVNETA_MH_SIZE) / 2) << 809c5aff182SThomas Petazzoni MVNETA_GMAC_MAX_RX_SIZE_SHIFT; 810c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_GMAC_CTRL_0, val); 811c5aff182SThomas Petazzoni } 812c5aff182SThomas Petazzoni 813c5aff182SThomas Petazzoni 814c5aff182SThomas Petazzoni /* Set rx queue offset */ 815c5aff182SThomas Petazzoni static void mvneta_rxq_offset_set(struct mvneta_port *pp, 816c5aff182SThomas Petazzoni struct mvneta_rx_queue *rxq, 817c5aff182SThomas Petazzoni int offset) 818c5aff182SThomas Petazzoni { 819c5aff182SThomas Petazzoni u32 val; 820c5aff182SThomas Petazzoni 821c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_RXQ_CONFIG_REG(rxq->id)); 822c5aff182SThomas Petazzoni val &= ~MVNETA_RXQ_PKT_OFFSET_ALL_MASK; 823c5aff182SThomas Petazzoni 824c5aff182SThomas Petazzoni /* Offset is in */ 825c5aff182SThomas Petazzoni val |= MVNETA_RXQ_PKT_OFFSET_MASK(offset >> 3); 826c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_RXQ_CONFIG_REG(rxq->id), val); 827c5aff182SThomas Petazzoni } 828c5aff182SThomas Petazzoni 829c5aff182SThomas Petazzoni 830c5aff182SThomas Petazzoni /* Tx descriptors helper methods */ 831c5aff182SThomas Petazzoni 832c5aff182SThomas Petazzoni /* Update HW with number of TX descriptors to be sent */ 833c5aff182SThomas Petazzoni static void mvneta_txq_pend_desc_add(struct mvneta_port *pp, 834c5aff182SThomas Petazzoni struct mvneta_tx_queue *txq, 835c5aff182SThomas Petazzoni int pend_desc) 836c5aff182SThomas Petazzoni { 837c5aff182SThomas Petazzoni u32 val; 838c5aff182SThomas Petazzoni 8390d63785cSSimon Guinot pend_desc += txq->pending; 8400d63785cSSimon Guinot 8410d63785cSSimon Guinot /* Only 255 Tx descriptors can be added at once */ 8420d63785cSSimon Guinot do { 8430d63785cSSimon Guinot val = min(pend_desc, 255); 844c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val); 8450d63785cSSimon Guinot pend_desc -= val; 8460d63785cSSimon Guinot } while (pend_desc > 0); 8472a90f7e1SSimon Guinot txq->pending = 0; 848c5aff182SThomas Petazzoni } 849c5aff182SThomas Petazzoni 850c5aff182SThomas Petazzoni /* Get pointer to next TX descriptor to be processed (send) by HW */ 851c5aff182SThomas Petazzoni static struct mvneta_tx_desc * 852c5aff182SThomas Petazzoni mvneta_txq_next_desc_get(struct mvneta_tx_queue *txq) 853c5aff182SThomas Petazzoni { 854c5aff182SThomas Petazzoni int tx_desc = txq->next_desc_to_proc; 855c5aff182SThomas Petazzoni 856c5aff182SThomas Petazzoni txq->next_desc_to_proc = MVNETA_QUEUE_NEXT_DESC(txq, tx_desc); 857c5aff182SThomas Petazzoni return txq->descs + tx_desc; 858c5aff182SThomas Petazzoni } 859c5aff182SThomas Petazzoni 860c5aff182SThomas Petazzoni /* Release the last allocated TX descriptor. Useful to handle DMA 8616a20c175SThomas Petazzoni * mapping failures in the TX path. 8626a20c175SThomas Petazzoni */ 863c5aff182SThomas Petazzoni static void mvneta_txq_desc_put(struct mvneta_tx_queue *txq) 864c5aff182SThomas Petazzoni { 865c5aff182SThomas Petazzoni if (txq->next_desc_to_proc == 0) 866c5aff182SThomas Petazzoni txq->next_desc_to_proc = txq->last_desc - 1; 867c5aff182SThomas Petazzoni else 868c5aff182SThomas Petazzoni txq->next_desc_to_proc--; 869c5aff182SThomas Petazzoni } 870c5aff182SThomas Petazzoni 871c5aff182SThomas Petazzoni /* Set rxq buf size */ 872c5aff182SThomas Petazzoni static void mvneta_rxq_buf_size_set(struct mvneta_port *pp, 873c5aff182SThomas Petazzoni struct mvneta_rx_queue *rxq, 874c5aff182SThomas Petazzoni int buf_size) 875c5aff182SThomas Petazzoni { 876c5aff182SThomas Petazzoni u32 val; 877c5aff182SThomas Petazzoni 878c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_RXQ_SIZE_REG(rxq->id)); 879c5aff182SThomas Petazzoni 880c5aff182SThomas Petazzoni val &= ~MVNETA_RXQ_BUF_SIZE_MASK; 881c5aff182SThomas Petazzoni val |= ((buf_size >> 3) << MVNETA_RXQ_BUF_SIZE_SHIFT); 882c5aff182SThomas Petazzoni 883c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_RXQ_SIZE_REG(rxq->id), val); 884c5aff182SThomas Petazzoni } 885c5aff182SThomas Petazzoni 886c5aff182SThomas Petazzoni /* Disable buffer management (BM) */ 887c5aff182SThomas Petazzoni static void mvneta_rxq_bm_disable(struct mvneta_port *pp, 888c5aff182SThomas Petazzoni struct mvneta_rx_queue *rxq) 889c5aff182SThomas Petazzoni { 890c5aff182SThomas Petazzoni u32 val; 891c5aff182SThomas Petazzoni 892c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_RXQ_CONFIG_REG(rxq->id)); 893c5aff182SThomas Petazzoni val &= ~MVNETA_RXQ_HW_BUF_ALLOC; 894c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_RXQ_CONFIG_REG(rxq->id), val); 895c5aff182SThomas Petazzoni } 896c5aff182SThomas Petazzoni 897dc35a10fSMarcin Wojtas /* Enable buffer management (BM) */ 898dc35a10fSMarcin Wojtas static void mvneta_rxq_bm_enable(struct mvneta_port *pp, 899dc35a10fSMarcin Wojtas struct mvneta_rx_queue *rxq) 900dc35a10fSMarcin Wojtas { 901dc35a10fSMarcin Wojtas u32 val; 902dc35a10fSMarcin Wojtas 903dc35a10fSMarcin Wojtas val = mvreg_read(pp, MVNETA_RXQ_CONFIG_REG(rxq->id)); 904dc35a10fSMarcin Wojtas val |= MVNETA_RXQ_HW_BUF_ALLOC; 905dc35a10fSMarcin Wojtas mvreg_write(pp, MVNETA_RXQ_CONFIG_REG(rxq->id), val); 906dc35a10fSMarcin Wojtas } 907dc35a10fSMarcin Wojtas 908dc35a10fSMarcin Wojtas /* Notify HW about port's assignment of pool for bigger packets */ 909dc35a10fSMarcin Wojtas static void mvneta_rxq_long_pool_set(struct mvneta_port *pp, 910dc35a10fSMarcin Wojtas struct mvneta_rx_queue *rxq) 911dc35a10fSMarcin Wojtas { 912dc35a10fSMarcin Wojtas u32 val; 913dc35a10fSMarcin Wojtas 914dc35a10fSMarcin Wojtas val = mvreg_read(pp, MVNETA_RXQ_CONFIG_REG(rxq->id)); 915dc35a10fSMarcin Wojtas val &= ~MVNETA_RXQ_LONG_POOL_ID_MASK; 916dc35a10fSMarcin Wojtas val |= (pp->pool_long->id << MVNETA_RXQ_LONG_POOL_ID_SHIFT); 917dc35a10fSMarcin Wojtas 918dc35a10fSMarcin Wojtas mvreg_write(pp, MVNETA_RXQ_CONFIG_REG(rxq->id), val); 919dc35a10fSMarcin Wojtas } 920dc35a10fSMarcin Wojtas 921dc35a10fSMarcin Wojtas /* Notify HW about port's assignment of pool for smaller packets */ 922dc35a10fSMarcin Wojtas static void mvneta_rxq_short_pool_set(struct mvneta_port *pp, 923dc35a10fSMarcin Wojtas struct mvneta_rx_queue *rxq) 924dc35a10fSMarcin Wojtas { 925dc35a10fSMarcin Wojtas u32 val; 926dc35a10fSMarcin Wojtas 927dc35a10fSMarcin Wojtas val = mvreg_read(pp, MVNETA_RXQ_CONFIG_REG(rxq->id)); 928dc35a10fSMarcin Wojtas val &= ~MVNETA_RXQ_SHORT_POOL_ID_MASK; 929dc35a10fSMarcin Wojtas val |= (pp->pool_short->id << MVNETA_RXQ_SHORT_POOL_ID_SHIFT); 930dc35a10fSMarcin Wojtas 931dc35a10fSMarcin Wojtas mvreg_write(pp, MVNETA_RXQ_CONFIG_REG(rxq->id), val); 932dc35a10fSMarcin Wojtas } 933dc35a10fSMarcin Wojtas 934dc35a10fSMarcin Wojtas /* Set port's receive buffer size for assigned BM pool */ 935dc35a10fSMarcin Wojtas static inline void mvneta_bm_pool_bufsize_set(struct mvneta_port *pp, 936dc35a10fSMarcin Wojtas int buf_size, 937dc35a10fSMarcin Wojtas u8 pool_id) 938dc35a10fSMarcin Wojtas { 939dc35a10fSMarcin Wojtas u32 val; 940dc35a10fSMarcin Wojtas 941dc35a10fSMarcin Wojtas if (!IS_ALIGNED(buf_size, 8)) { 942dc35a10fSMarcin Wojtas dev_warn(pp->dev->dev.parent, 943dc35a10fSMarcin Wojtas "illegal buf_size value %d, round to %d\n", 944dc35a10fSMarcin Wojtas buf_size, ALIGN(buf_size, 8)); 945dc35a10fSMarcin Wojtas buf_size = ALIGN(buf_size, 8); 946dc35a10fSMarcin Wojtas } 947dc35a10fSMarcin Wojtas 948dc35a10fSMarcin Wojtas val = mvreg_read(pp, MVNETA_PORT_POOL_BUFFER_SZ_REG(pool_id)); 949dc35a10fSMarcin Wojtas val |= buf_size & MVNETA_PORT_POOL_BUFFER_SZ_MASK; 950dc35a10fSMarcin Wojtas mvreg_write(pp, MVNETA_PORT_POOL_BUFFER_SZ_REG(pool_id), val); 951dc35a10fSMarcin Wojtas } 952dc35a10fSMarcin Wojtas 953dc35a10fSMarcin Wojtas /* Configure MBUS window in order to enable access BM internal SRAM */ 954dc35a10fSMarcin Wojtas static int mvneta_mbus_io_win_set(struct mvneta_port *pp, u32 base, u32 wsize, 955dc35a10fSMarcin Wojtas u8 target, u8 attr) 956dc35a10fSMarcin Wojtas { 957dc35a10fSMarcin Wojtas u32 win_enable, win_protect; 958dc35a10fSMarcin Wojtas int i; 959dc35a10fSMarcin Wojtas 960dc35a10fSMarcin Wojtas win_enable = mvreg_read(pp, MVNETA_BASE_ADDR_ENABLE); 961dc35a10fSMarcin Wojtas 962dc35a10fSMarcin Wojtas if (pp->bm_win_id < 0) { 963dc35a10fSMarcin Wojtas /* Find first not occupied window */ 964dc35a10fSMarcin Wojtas for (i = 0; i < MVNETA_MAX_DECODE_WIN; i++) { 965dc35a10fSMarcin Wojtas if (win_enable & (1 << i)) { 966dc35a10fSMarcin Wojtas pp->bm_win_id = i; 967dc35a10fSMarcin Wojtas break; 968dc35a10fSMarcin Wojtas } 969dc35a10fSMarcin Wojtas } 970dc35a10fSMarcin Wojtas if (i == MVNETA_MAX_DECODE_WIN) 971dc35a10fSMarcin Wojtas return -ENOMEM; 972dc35a10fSMarcin Wojtas } else { 973dc35a10fSMarcin Wojtas i = pp->bm_win_id; 974dc35a10fSMarcin Wojtas } 975dc35a10fSMarcin Wojtas 976dc35a10fSMarcin Wojtas mvreg_write(pp, MVNETA_WIN_BASE(i), 0); 977dc35a10fSMarcin Wojtas mvreg_write(pp, MVNETA_WIN_SIZE(i), 0); 978dc35a10fSMarcin Wojtas 979dc35a10fSMarcin Wojtas if (i < 4) 980dc35a10fSMarcin Wojtas mvreg_write(pp, MVNETA_WIN_REMAP(i), 0); 981dc35a10fSMarcin Wojtas 982dc35a10fSMarcin Wojtas mvreg_write(pp, MVNETA_WIN_BASE(i), (base & 0xffff0000) | 983dc35a10fSMarcin Wojtas (attr << 8) | target); 984dc35a10fSMarcin Wojtas 985dc35a10fSMarcin Wojtas mvreg_write(pp, MVNETA_WIN_SIZE(i), (wsize - 1) & 0xffff0000); 986dc35a10fSMarcin Wojtas 987dc35a10fSMarcin Wojtas win_protect = mvreg_read(pp, MVNETA_ACCESS_PROTECT_ENABLE); 988dc35a10fSMarcin Wojtas win_protect |= 3 << (2 * i); 989dc35a10fSMarcin Wojtas mvreg_write(pp, MVNETA_ACCESS_PROTECT_ENABLE, win_protect); 990dc35a10fSMarcin Wojtas 991dc35a10fSMarcin Wojtas win_enable &= ~(1 << i); 992dc35a10fSMarcin Wojtas mvreg_write(pp, MVNETA_BASE_ADDR_ENABLE, win_enable); 993dc35a10fSMarcin Wojtas 994dc35a10fSMarcin Wojtas return 0; 995dc35a10fSMarcin Wojtas } 996dc35a10fSMarcin Wojtas 9972636ac3cSMarcin Wojtas static int mvneta_bm_port_mbus_init(struct mvneta_port *pp) 998dc35a10fSMarcin Wojtas { 9992636ac3cSMarcin Wojtas u32 wsize; 1000dc35a10fSMarcin Wojtas u8 target, attr; 1001dc35a10fSMarcin Wojtas int err; 1002dc35a10fSMarcin Wojtas 1003dc35a10fSMarcin Wojtas /* Get BM window information */ 1004dc35a10fSMarcin Wojtas err = mvebu_mbus_get_io_win_info(pp->bm_priv->bppi_phys_addr, &wsize, 1005dc35a10fSMarcin Wojtas &target, &attr); 1006dc35a10fSMarcin Wojtas if (err < 0) 1007dc35a10fSMarcin Wojtas return err; 1008dc35a10fSMarcin Wojtas 1009dc35a10fSMarcin Wojtas pp->bm_win_id = -1; 1010dc35a10fSMarcin Wojtas 1011dc35a10fSMarcin Wojtas /* Open NETA -> BM window */ 1012dc35a10fSMarcin Wojtas err = mvneta_mbus_io_win_set(pp, pp->bm_priv->bppi_phys_addr, wsize, 1013dc35a10fSMarcin Wojtas target, attr); 1014dc35a10fSMarcin Wojtas if (err < 0) { 1015dc35a10fSMarcin Wojtas netdev_info(pp->dev, "fail to configure mbus window to BM\n"); 1016dc35a10fSMarcin Wojtas return err; 1017dc35a10fSMarcin Wojtas } 10182636ac3cSMarcin Wojtas return 0; 10192636ac3cSMarcin Wojtas } 10202636ac3cSMarcin Wojtas 10212636ac3cSMarcin Wojtas /* Assign and initialize pools for port. In case of fail 10222636ac3cSMarcin Wojtas * buffer manager will remain disabled for current port. 10232636ac3cSMarcin Wojtas */ 10242636ac3cSMarcin Wojtas static int mvneta_bm_port_init(struct platform_device *pdev, 10252636ac3cSMarcin Wojtas struct mvneta_port *pp) 10262636ac3cSMarcin Wojtas { 10272636ac3cSMarcin Wojtas struct device_node *dn = pdev->dev.of_node; 10282636ac3cSMarcin Wojtas u32 long_pool_id, short_pool_id; 10292636ac3cSMarcin Wojtas 10302636ac3cSMarcin Wojtas if (!pp->neta_armada3700) { 10312636ac3cSMarcin Wojtas int ret; 10322636ac3cSMarcin Wojtas 10332636ac3cSMarcin Wojtas ret = mvneta_bm_port_mbus_init(pp); 10342636ac3cSMarcin Wojtas if (ret) 10352636ac3cSMarcin Wojtas return ret; 10362636ac3cSMarcin Wojtas } 1037dc35a10fSMarcin Wojtas 1038dc35a10fSMarcin Wojtas if (of_property_read_u32(dn, "bm,pool-long", &long_pool_id)) { 1039dc35a10fSMarcin Wojtas netdev_info(pp->dev, "missing long pool id\n"); 1040dc35a10fSMarcin Wojtas return -EINVAL; 1041dc35a10fSMarcin Wojtas } 1042dc35a10fSMarcin Wojtas 1043dc35a10fSMarcin Wojtas /* Create port's long pool depending on mtu */ 1044dc35a10fSMarcin Wojtas pp->pool_long = mvneta_bm_pool_use(pp->bm_priv, long_pool_id, 1045dc35a10fSMarcin Wojtas MVNETA_BM_LONG, pp->id, 1046dc35a10fSMarcin Wojtas MVNETA_RX_PKT_SIZE(pp->dev->mtu)); 1047dc35a10fSMarcin Wojtas if (!pp->pool_long) { 1048dc35a10fSMarcin Wojtas netdev_info(pp->dev, "fail to obtain long pool for port\n"); 1049dc35a10fSMarcin Wojtas return -ENOMEM; 1050dc35a10fSMarcin Wojtas } 1051dc35a10fSMarcin Wojtas 1052dc35a10fSMarcin Wojtas pp->pool_long->port_map |= 1 << pp->id; 1053dc35a10fSMarcin Wojtas 1054dc35a10fSMarcin Wojtas mvneta_bm_pool_bufsize_set(pp, pp->pool_long->buf_size, 1055dc35a10fSMarcin Wojtas pp->pool_long->id); 1056dc35a10fSMarcin Wojtas 1057dc35a10fSMarcin Wojtas /* If short pool id is not defined, assume using single pool */ 1058dc35a10fSMarcin Wojtas if (of_property_read_u32(dn, "bm,pool-short", &short_pool_id)) 1059dc35a10fSMarcin Wojtas short_pool_id = long_pool_id; 1060dc35a10fSMarcin Wojtas 1061dc35a10fSMarcin Wojtas /* Create port's short pool */ 1062dc35a10fSMarcin Wojtas pp->pool_short = mvneta_bm_pool_use(pp->bm_priv, short_pool_id, 1063dc35a10fSMarcin Wojtas MVNETA_BM_SHORT, pp->id, 1064dc35a10fSMarcin Wojtas MVNETA_BM_SHORT_PKT_SIZE); 1065dc35a10fSMarcin Wojtas if (!pp->pool_short) { 1066dc35a10fSMarcin Wojtas netdev_info(pp->dev, "fail to obtain short pool for port\n"); 1067dc35a10fSMarcin Wojtas mvneta_bm_pool_destroy(pp->bm_priv, pp->pool_long, 1 << pp->id); 1068dc35a10fSMarcin Wojtas return -ENOMEM; 1069dc35a10fSMarcin Wojtas } 1070dc35a10fSMarcin Wojtas 1071dc35a10fSMarcin Wojtas if (short_pool_id != long_pool_id) { 1072dc35a10fSMarcin Wojtas pp->pool_short->port_map |= 1 << pp->id; 1073dc35a10fSMarcin Wojtas mvneta_bm_pool_bufsize_set(pp, pp->pool_short->buf_size, 1074dc35a10fSMarcin Wojtas pp->pool_short->id); 1075dc35a10fSMarcin Wojtas } 1076dc35a10fSMarcin Wojtas 1077dc35a10fSMarcin Wojtas return 0; 1078dc35a10fSMarcin Wojtas } 1079dc35a10fSMarcin Wojtas 1080dc35a10fSMarcin Wojtas /* Update settings of a pool for bigger packets */ 1081dc35a10fSMarcin Wojtas static void mvneta_bm_update_mtu(struct mvneta_port *pp, int mtu) 1082dc35a10fSMarcin Wojtas { 1083dc35a10fSMarcin Wojtas struct mvneta_bm_pool *bm_pool = pp->pool_long; 1084baa11ebcSGregory CLEMENT struct hwbm_pool *hwbm_pool = &bm_pool->hwbm_pool; 1085dc35a10fSMarcin Wojtas int num; 1086dc35a10fSMarcin Wojtas 1087dc35a10fSMarcin Wojtas /* Release all buffers from long pool */ 1088dc35a10fSMarcin Wojtas mvneta_bm_bufs_free(pp->bm_priv, bm_pool, 1 << pp->id); 1089baa11ebcSGregory CLEMENT if (hwbm_pool->buf_num) { 1090dc35a10fSMarcin Wojtas WARN(1, "cannot free all buffers in pool %d\n", 1091dc35a10fSMarcin Wojtas bm_pool->id); 1092dc35a10fSMarcin Wojtas goto bm_mtu_err; 1093dc35a10fSMarcin Wojtas } 1094dc35a10fSMarcin Wojtas 1095dc35a10fSMarcin Wojtas bm_pool->pkt_size = MVNETA_RX_PKT_SIZE(mtu); 1096dc35a10fSMarcin Wojtas bm_pool->buf_size = MVNETA_RX_BUF_SIZE(bm_pool->pkt_size); 1097baa11ebcSGregory CLEMENT hwbm_pool->frag_size = SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) + 1098dc35a10fSMarcin Wojtas SKB_DATA_ALIGN(MVNETA_RX_BUF_SIZE(bm_pool->pkt_size)); 1099dc35a10fSMarcin Wojtas 1100dc35a10fSMarcin Wojtas /* Fill entire long pool */ 1101baa11ebcSGregory CLEMENT num = hwbm_pool_add(hwbm_pool, hwbm_pool->size, GFP_ATOMIC); 1102baa11ebcSGregory CLEMENT if (num != hwbm_pool->size) { 1103dc35a10fSMarcin Wojtas WARN(1, "pool %d: %d of %d allocated\n", 1104baa11ebcSGregory CLEMENT bm_pool->id, num, hwbm_pool->size); 1105dc35a10fSMarcin Wojtas goto bm_mtu_err; 1106dc35a10fSMarcin Wojtas } 1107dc35a10fSMarcin Wojtas mvneta_bm_pool_bufsize_set(pp, bm_pool->buf_size, bm_pool->id); 1108dc35a10fSMarcin Wojtas 1109dc35a10fSMarcin Wojtas return; 1110dc35a10fSMarcin Wojtas 1111dc35a10fSMarcin Wojtas bm_mtu_err: 1112dc35a10fSMarcin Wojtas mvneta_bm_pool_destroy(pp->bm_priv, pp->pool_long, 1 << pp->id); 1113dc35a10fSMarcin Wojtas mvneta_bm_pool_destroy(pp->bm_priv, pp->pool_short, 1 << pp->id); 1114dc35a10fSMarcin Wojtas 1115dc35a10fSMarcin Wojtas pp->bm_priv = NULL; 1116dc35a10fSMarcin Wojtas mvreg_write(pp, MVNETA_ACC_MODE, MVNETA_ACC_MODE_EXT1); 1117dc35a10fSMarcin Wojtas netdev_info(pp->dev, "fail to update MTU, fall back to software BM\n"); 1118dc35a10fSMarcin Wojtas } 1119dc35a10fSMarcin Wojtas 1120c5aff182SThomas Petazzoni /* Start the Ethernet port RX and TX activity */ 1121c5aff182SThomas Petazzoni static void mvneta_port_up(struct mvneta_port *pp) 1122c5aff182SThomas Petazzoni { 1123c5aff182SThomas Petazzoni int queue; 1124c5aff182SThomas Petazzoni u32 q_map; 1125c5aff182SThomas Petazzoni 1126c5aff182SThomas Petazzoni /* Enable all initialized TXs. */ 1127c5aff182SThomas Petazzoni q_map = 0; 1128c5aff182SThomas Petazzoni for (queue = 0; queue < txq_number; queue++) { 1129c5aff182SThomas Petazzoni struct mvneta_tx_queue *txq = &pp->txqs[queue]; 1130f95936ccSMarkus Elfring if (txq->descs) 1131c5aff182SThomas Petazzoni q_map |= (1 << queue); 1132c5aff182SThomas Petazzoni } 1133c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_TXQ_CMD, q_map); 1134c5aff182SThomas Petazzoni 1135e81b5e01SYelena Krivosheev q_map = 0; 1136c5aff182SThomas Petazzoni /* Enable all initialized RXQs. */ 11372dcf75e2SGregory CLEMENT for (queue = 0; queue < rxq_number; queue++) { 11382dcf75e2SGregory CLEMENT struct mvneta_rx_queue *rxq = &pp->rxqs[queue]; 11392dcf75e2SGregory CLEMENT 1140f95936ccSMarkus Elfring if (rxq->descs) 11412dcf75e2SGregory CLEMENT q_map |= (1 << queue); 11422dcf75e2SGregory CLEMENT } 11432dcf75e2SGregory CLEMENT mvreg_write(pp, MVNETA_RXQ_CMD, q_map); 1144c5aff182SThomas Petazzoni } 1145c5aff182SThomas Petazzoni 1146c5aff182SThomas Petazzoni /* Stop the Ethernet port activity */ 1147c5aff182SThomas Petazzoni static void mvneta_port_down(struct mvneta_port *pp) 1148c5aff182SThomas Petazzoni { 1149c5aff182SThomas Petazzoni u32 val; 1150c5aff182SThomas Petazzoni int count; 1151c5aff182SThomas Petazzoni 1152c5aff182SThomas Petazzoni /* Stop Rx port activity. Check port Rx activity. */ 1153c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_RXQ_CMD) & MVNETA_RXQ_ENABLE_MASK; 1154c5aff182SThomas Petazzoni 1155c5aff182SThomas Petazzoni /* Issue stop command for active channels only */ 1156c5aff182SThomas Petazzoni if (val != 0) 1157c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_RXQ_CMD, 1158c5aff182SThomas Petazzoni val << MVNETA_RXQ_DISABLE_SHIFT); 1159c5aff182SThomas Petazzoni 1160c5aff182SThomas Petazzoni /* Wait for all Rx activity to terminate. */ 1161c5aff182SThomas Petazzoni count = 0; 1162c5aff182SThomas Petazzoni do { 1163c5aff182SThomas Petazzoni if (count++ >= MVNETA_RX_DISABLE_TIMEOUT_MSEC) { 1164c5aff182SThomas Petazzoni netdev_warn(pp->dev, 11650838abb3SDmitri Epshtein "TIMEOUT for RX stopped ! rx_queue_cmd: 0x%08x\n", 1166c5aff182SThomas Petazzoni val); 1167c5aff182SThomas Petazzoni break; 1168c5aff182SThomas Petazzoni } 1169c5aff182SThomas Petazzoni mdelay(1); 1170c5aff182SThomas Petazzoni 1171c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_RXQ_CMD); 1172a3703fb3SDmitri Epshtein } while (val & MVNETA_RXQ_ENABLE_MASK); 1173c5aff182SThomas Petazzoni 1174c5aff182SThomas Petazzoni /* Stop Tx port activity. Check port Tx activity. Issue stop 11756a20c175SThomas Petazzoni * command for active channels only 11766a20c175SThomas Petazzoni */ 1177c5aff182SThomas Petazzoni val = (mvreg_read(pp, MVNETA_TXQ_CMD)) & MVNETA_TXQ_ENABLE_MASK; 1178c5aff182SThomas Petazzoni 1179c5aff182SThomas Petazzoni if (val != 0) 1180c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_TXQ_CMD, 1181c5aff182SThomas Petazzoni (val << MVNETA_TXQ_DISABLE_SHIFT)); 1182c5aff182SThomas Petazzoni 1183c5aff182SThomas Petazzoni /* Wait for all Tx activity to terminate. */ 1184c5aff182SThomas Petazzoni count = 0; 1185c5aff182SThomas Petazzoni do { 1186c5aff182SThomas Petazzoni if (count++ >= MVNETA_TX_DISABLE_TIMEOUT_MSEC) { 1187c5aff182SThomas Petazzoni netdev_warn(pp->dev, 1188c5aff182SThomas Petazzoni "TIMEOUT for TX stopped status=0x%08x\n", 1189c5aff182SThomas Petazzoni val); 1190c5aff182SThomas Petazzoni break; 1191c5aff182SThomas Petazzoni } 1192c5aff182SThomas Petazzoni mdelay(1); 1193c5aff182SThomas Petazzoni 1194c5aff182SThomas Petazzoni /* Check TX Command reg that all Txqs are stopped */ 1195c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_TXQ_CMD); 1196c5aff182SThomas Petazzoni 1197a3703fb3SDmitri Epshtein } while (val & MVNETA_TXQ_ENABLE_MASK); 1198c5aff182SThomas Petazzoni 1199c5aff182SThomas Petazzoni /* Double check to verify that TX FIFO is empty */ 1200c5aff182SThomas Petazzoni count = 0; 1201c5aff182SThomas Petazzoni do { 1202c5aff182SThomas Petazzoni if (count++ >= MVNETA_TX_FIFO_EMPTY_TIMEOUT) { 1203c5aff182SThomas Petazzoni netdev_warn(pp->dev, 12040838abb3SDmitri Epshtein "TX FIFO empty timeout status=0x%08x\n", 1205c5aff182SThomas Petazzoni val); 1206c5aff182SThomas Petazzoni break; 1207c5aff182SThomas Petazzoni } 1208c5aff182SThomas Petazzoni mdelay(1); 1209c5aff182SThomas Petazzoni 1210c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_PORT_STATUS); 1211c5aff182SThomas Petazzoni } while (!(val & MVNETA_TX_FIFO_EMPTY) && 1212c5aff182SThomas Petazzoni (val & MVNETA_TX_IN_PRGRS)); 1213c5aff182SThomas Petazzoni 1214c5aff182SThomas Petazzoni udelay(200); 1215c5aff182SThomas Petazzoni } 1216c5aff182SThomas Petazzoni 1217c5aff182SThomas Petazzoni /* Enable the port by setting the port enable bit of the MAC control register */ 1218c5aff182SThomas Petazzoni static void mvneta_port_enable(struct mvneta_port *pp) 1219c5aff182SThomas Petazzoni { 1220c5aff182SThomas Petazzoni u32 val; 1221c5aff182SThomas Petazzoni 1222c5aff182SThomas Petazzoni /* Enable port */ 1223c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_GMAC_CTRL_0); 1224c5aff182SThomas Petazzoni val |= MVNETA_GMAC0_PORT_ENABLE; 1225c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_GMAC_CTRL_0, val); 1226c5aff182SThomas Petazzoni } 1227c5aff182SThomas Petazzoni 1228c5aff182SThomas Petazzoni /* Disable the port and wait for about 200 usec before retuning */ 1229c5aff182SThomas Petazzoni static void mvneta_port_disable(struct mvneta_port *pp) 1230c5aff182SThomas Petazzoni { 1231c5aff182SThomas Petazzoni u32 val; 1232c5aff182SThomas Petazzoni 1233c5aff182SThomas Petazzoni /* Reset the Enable bit in the Serial Control Register */ 1234c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_GMAC_CTRL_0); 1235c5aff182SThomas Petazzoni val &= ~MVNETA_GMAC0_PORT_ENABLE; 1236c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_GMAC_CTRL_0, val); 1237c5aff182SThomas Petazzoni 1238c5aff182SThomas Petazzoni udelay(200); 1239c5aff182SThomas Petazzoni } 1240c5aff182SThomas Petazzoni 1241c5aff182SThomas Petazzoni /* Multicast tables methods */ 1242c5aff182SThomas Petazzoni 1243c5aff182SThomas Petazzoni /* Set all entries in Unicast MAC Table; queue==-1 means reject all */ 1244c5aff182SThomas Petazzoni static void mvneta_set_ucast_table(struct mvneta_port *pp, int queue) 1245c5aff182SThomas Petazzoni { 1246c5aff182SThomas Petazzoni int offset; 1247c5aff182SThomas Petazzoni u32 val; 1248c5aff182SThomas Petazzoni 1249c5aff182SThomas Petazzoni if (queue == -1) { 1250c5aff182SThomas Petazzoni val = 0; 1251c5aff182SThomas Petazzoni } else { 1252c5aff182SThomas Petazzoni val = 0x1 | (queue << 1); 1253c5aff182SThomas Petazzoni val |= (val << 24) | (val << 16) | (val << 8); 1254c5aff182SThomas Petazzoni } 1255c5aff182SThomas Petazzoni 1256c5aff182SThomas Petazzoni for (offset = 0; offset <= 0xc; offset += 4) 1257c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_DA_FILT_UCAST_BASE + offset, val); 1258c5aff182SThomas Petazzoni } 1259c5aff182SThomas Petazzoni 1260c5aff182SThomas Petazzoni /* Set all entries in Special Multicast MAC Table; queue==-1 means reject all */ 1261c5aff182SThomas Petazzoni static void mvneta_set_special_mcast_table(struct mvneta_port *pp, int queue) 1262c5aff182SThomas Petazzoni { 1263c5aff182SThomas Petazzoni int offset; 1264c5aff182SThomas Petazzoni u32 val; 1265c5aff182SThomas Petazzoni 1266c5aff182SThomas Petazzoni if (queue == -1) { 1267c5aff182SThomas Petazzoni val = 0; 1268c5aff182SThomas Petazzoni } else { 1269c5aff182SThomas Petazzoni val = 0x1 | (queue << 1); 1270c5aff182SThomas Petazzoni val |= (val << 24) | (val << 16) | (val << 8); 1271c5aff182SThomas Petazzoni } 1272c5aff182SThomas Petazzoni 1273c5aff182SThomas Petazzoni for (offset = 0; offset <= 0xfc; offset += 4) 1274c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_DA_FILT_SPEC_MCAST + offset, val); 1275c5aff182SThomas Petazzoni 1276c5aff182SThomas Petazzoni } 1277c5aff182SThomas Petazzoni 1278c5aff182SThomas Petazzoni /* Set all entries in Other Multicast MAC Table. queue==-1 means reject all */ 1279c5aff182SThomas Petazzoni static void mvneta_set_other_mcast_table(struct mvneta_port *pp, int queue) 1280c5aff182SThomas Petazzoni { 1281c5aff182SThomas Petazzoni int offset; 1282c5aff182SThomas Petazzoni u32 val; 1283c5aff182SThomas Petazzoni 1284c5aff182SThomas Petazzoni if (queue == -1) { 1285c5aff182SThomas Petazzoni memset(pp->mcast_count, 0, sizeof(pp->mcast_count)); 1286c5aff182SThomas Petazzoni val = 0; 1287c5aff182SThomas Petazzoni } else { 1288c5aff182SThomas Petazzoni memset(pp->mcast_count, 1, sizeof(pp->mcast_count)); 1289c5aff182SThomas Petazzoni val = 0x1 | (queue << 1); 1290c5aff182SThomas Petazzoni val |= (val << 24) | (val << 16) | (val << 8); 1291c5aff182SThomas Petazzoni } 1292c5aff182SThomas Petazzoni 1293c5aff182SThomas Petazzoni for (offset = 0; offset <= 0xfc; offset += 4) 1294c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_DA_FILT_OTH_MCAST + offset, val); 1295c5aff182SThomas Petazzoni } 1296c5aff182SThomas Petazzoni 1297db488c10SGregory CLEMENT static void mvneta_percpu_unmask_interrupt(void *arg) 1298db488c10SGregory CLEMENT { 1299db488c10SGregory CLEMENT struct mvneta_port *pp = arg; 1300db488c10SGregory CLEMENT 1301db488c10SGregory CLEMENT /* All the queue are unmasked, but actually only the ones 1302db488c10SGregory CLEMENT * mapped to this CPU will be unmasked 1303db488c10SGregory CLEMENT */ 1304db488c10SGregory CLEMENT mvreg_write(pp, MVNETA_INTR_NEW_MASK, 1305db488c10SGregory CLEMENT MVNETA_RX_INTR_MASK_ALL | 1306db488c10SGregory CLEMENT MVNETA_TX_INTR_MASK_ALL | 1307db488c10SGregory CLEMENT MVNETA_MISCINTR_INTR_MASK); 1308db488c10SGregory CLEMENT } 1309db488c10SGregory CLEMENT 1310db488c10SGregory CLEMENT static void mvneta_percpu_mask_interrupt(void *arg) 1311db488c10SGregory CLEMENT { 1312db488c10SGregory CLEMENT struct mvneta_port *pp = arg; 1313db488c10SGregory CLEMENT 1314db488c10SGregory CLEMENT /* All the queue are masked, but actually only the ones 1315db488c10SGregory CLEMENT * mapped to this CPU will be masked 1316db488c10SGregory CLEMENT */ 1317db488c10SGregory CLEMENT mvreg_write(pp, MVNETA_INTR_NEW_MASK, 0); 1318db488c10SGregory CLEMENT mvreg_write(pp, MVNETA_INTR_OLD_MASK, 0); 1319db488c10SGregory CLEMENT mvreg_write(pp, MVNETA_INTR_MISC_MASK, 0); 1320db488c10SGregory CLEMENT } 1321db488c10SGregory CLEMENT 1322db488c10SGregory CLEMENT static void mvneta_percpu_clear_intr_cause(void *arg) 1323db488c10SGregory CLEMENT { 1324db488c10SGregory CLEMENT struct mvneta_port *pp = arg; 1325db488c10SGregory CLEMENT 1326db488c10SGregory CLEMENT /* All the queue are cleared, but actually only the ones 1327db488c10SGregory CLEMENT * mapped to this CPU will be cleared 1328db488c10SGregory CLEMENT */ 1329db488c10SGregory CLEMENT mvreg_write(pp, MVNETA_INTR_NEW_CAUSE, 0); 1330db488c10SGregory CLEMENT mvreg_write(pp, MVNETA_INTR_MISC_CAUSE, 0); 1331db488c10SGregory CLEMENT mvreg_write(pp, MVNETA_INTR_OLD_CAUSE, 0); 1332db488c10SGregory CLEMENT } 1333db488c10SGregory CLEMENT 1334c5aff182SThomas Petazzoni /* This method sets defaults to the NETA port: 1335c5aff182SThomas Petazzoni * Clears interrupt Cause and Mask registers. 1336c5aff182SThomas Petazzoni * Clears all MAC tables. 1337c5aff182SThomas Petazzoni * Sets defaults to all registers. 1338c5aff182SThomas Petazzoni * Resets RX and TX descriptor rings. 1339c5aff182SThomas Petazzoni * Resets PHY. 1340c5aff182SThomas Petazzoni * This method can be called after mvneta_port_down() to return the port 1341c5aff182SThomas Petazzoni * settings to defaults. 1342c5aff182SThomas Petazzoni */ 1343c5aff182SThomas Petazzoni static void mvneta_defaults_set(struct mvneta_port *pp) 1344c5aff182SThomas Petazzoni { 1345c5aff182SThomas Petazzoni int cpu; 1346c5aff182SThomas Petazzoni int queue; 1347c5aff182SThomas Petazzoni u32 val; 13482dcf75e2SGregory CLEMENT int max_cpu = num_present_cpus(); 1349c5aff182SThomas Petazzoni 1350c5aff182SThomas Petazzoni /* Clear all Cause registers */ 1351db488c10SGregory CLEMENT on_each_cpu(mvneta_percpu_clear_intr_cause, pp, true); 1352c5aff182SThomas Petazzoni 1353c5aff182SThomas Petazzoni /* Mask all interrupts */ 1354db488c10SGregory CLEMENT on_each_cpu(mvneta_percpu_mask_interrupt, pp, true); 1355c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_INTR_ENABLE, 0); 1356c5aff182SThomas Petazzoni 1357c5aff182SThomas Petazzoni /* Enable MBUS Retry bit16 */ 1358c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_MBUS_RETRY, 0x20); 1359c5aff182SThomas Petazzoni 136050bf8cb6SGregory CLEMENT /* Set CPU queue access map. CPUs are assigned to the RX and 136150bf8cb6SGregory CLEMENT * TX queues modulo their number. If there is only one TX 136250bf8cb6SGregory CLEMENT * queue then it is assigned to the CPU associated to the 136350bf8cb6SGregory CLEMENT * default RX queue. 13646a20c175SThomas Petazzoni */ 13652dcf75e2SGregory CLEMENT for_each_present_cpu(cpu) { 13662dcf75e2SGregory CLEMENT int rxq_map = 0, txq_map = 0; 136750bf8cb6SGregory CLEMENT int rxq, txq; 13682636ac3cSMarcin Wojtas if (!pp->neta_armada3700) { 13692dcf75e2SGregory CLEMENT for (rxq = 0; rxq < rxq_number; rxq++) 13702dcf75e2SGregory CLEMENT if ((rxq % max_cpu) == cpu) 13712dcf75e2SGregory CLEMENT rxq_map |= MVNETA_CPU_RXQ_ACCESS(rxq); 13722dcf75e2SGregory CLEMENT 137350bf8cb6SGregory CLEMENT for (txq = 0; txq < txq_number; txq++) 137450bf8cb6SGregory CLEMENT if ((txq % max_cpu) == cpu) 137550bf8cb6SGregory CLEMENT txq_map |= MVNETA_CPU_TXQ_ACCESS(txq); 137650bf8cb6SGregory CLEMENT 137750bf8cb6SGregory CLEMENT /* With only one TX queue we configure a special case 137850bf8cb6SGregory CLEMENT * which will allow to get all the irq on a single 137950bf8cb6SGregory CLEMENT * CPU 138050bf8cb6SGregory CLEMENT */ 138150bf8cb6SGregory CLEMENT if (txq_number == 1) 138250bf8cb6SGregory CLEMENT txq_map = (cpu == pp->rxq_def) ? 138350bf8cb6SGregory CLEMENT MVNETA_CPU_TXQ_ACCESS(1) : 0; 13842dcf75e2SGregory CLEMENT 13852636ac3cSMarcin Wojtas } else { 13862636ac3cSMarcin Wojtas txq_map = MVNETA_CPU_TXQ_ACCESS_ALL_MASK; 13872636ac3cSMarcin Wojtas rxq_map = MVNETA_CPU_RXQ_ACCESS_ALL_MASK; 13882636ac3cSMarcin Wojtas } 13892636ac3cSMarcin Wojtas 13902dcf75e2SGregory CLEMENT mvreg_write(pp, MVNETA_CPU_MAP(cpu), rxq_map | txq_map); 13912dcf75e2SGregory CLEMENT } 1392c5aff182SThomas Petazzoni 1393c5aff182SThomas Petazzoni /* Reset RX and TX DMAs */ 1394c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_PORT_RX_RESET, MVNETA_PORT_RX_DMA_RESET); 1395c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_PORT_TX_RESET, MVNETA_PORT_TX_DMA_RESET); 1396c5aff182SThomas Petazzoni 1397c5aff182SThomas Petazzoni /* Disable Legacy WRR, Disable EJP, Release from reset */ 1398c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_TXQ_CMD_1, 0); 1399c5aff182SThomas Petazzoni for (queue = 0; queue < txq_number; queue++) { 1400c5aff182SThomas Petazzoni mvreg_write(pp, MVETH_TXQ_TOKEN_COUNT_REG(queue), 0); 1401c5aff182SThomas Petazzoni mvreg_write(pp, MVETH_TXQ_TOKEN_CFG_REG(queue), 0); 1402c5aff182SThomas Petazzoni } 1403c5aff182SThomas Petazzoni 1404c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_PORT_TX_RESET, 0); 1405c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_PORT_RX_RESET, 0); 1406c5aff182SThomas Petazzoni 1407c5aff182SThomas Petazzoni /* Set Port Acceleration Mode */ 1408dc35a10fSMarcin Wojtas if (pp->bm_priv) 1409dc35a10fSMarcin Wojtas /* HW buffer management + legacy parser */ 1410dc35a10fSMarcin Wojtas val = MVNETA_ACC_MODE_EXT2; 1411dc35a10fSMarcin Wojtas else 1412dc35a10fSMarcin Wojtas /* SW buffer management + legacy parser */ 1413dc35a10fSMarcin Wojtas val = MVNETA_ACC_MODE_EXT1; 1414c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_ACC_MODE, val); 1415c5aff182SThomas Petazzoni 1416dc35a10fSMarcin Wojtas if (pp->bm_priv) 1417dc35a10fSMarcin Wojtas mvreg_write(pp, MVNETA_BM_ADDRESS, pp->bm_priv->bppi_phys_addr); 1418dc35a10fSMarcin Wojtas 1419c5aff182SThomas Petazzoni /* Update val of portCfg register accordingly with all RxQueue types */ 142090b74c01SGregory CLEMENT val = MVNETA_PORT_CONFIG_DEFL_VALUE(pp->rxq_def); 1421c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_PORT_CONFIG, val); 1422c5aff182SThomas Petazzoni 1423c5aff182SThomas Petazzoni val = 0; 1424c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_PORT_CONFIG_EXTEND, val); 1425c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_RX_MIN_FRAME_SIZE, 64); 1426c5aff182SThomas Petazzoni 1427c5aff182SThomas Petazzoni /* Build PORT_SDMA_CONFIG_REG */ 1428c5aff182SThomas Petazzoni val = 0; 1429c5aff182SThomas Petazzoni 1430c5aff182SThomas Petazzoni /* Default burst size */ 1431c5aff182SThomas Petazzoni val |= MVNETA_TX_BRST_SZ_MASK(MVNETA_SDMA_BRST_SIZE_16); 1432c5aff182SThomas Petazzoni val |= MVNETA_RX_BRST_SZ_MASK(MVNETA_SDMA_BRST_SIZE_16); 14339ad8fef6SThomas Petazzoni val |= MVNETA_RX_NO_DATA_SWAP | MVNETA_TX_NO_DATA_SWAP; 1434c5aff182SThomas Petazzoni 14359ad8fef6SThomas Petazzoni #if defined(__BIG_ENDIAN) 14369ad8fef6SThomas Petazzoni val |= MVNETA_DESC_SWAP; 14379ad8fef6SThomas Petazzoni #endif 1438c5aff182SThomas Petazzoni 1439c5aff182SThomas Petazzoni /* Assign port SDMA configuration */ 1440c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_SDMA_CONFIG, val); 1441c5aff182SThomas Petazzoni 144271408602SThomas Petazzoni /* Disable PHY polling in hardware, since we're using the 144371408602SThomas Petazzoni * kernel phylib to do this. 144471408602SThomas Petazzoni */ 144571408602SThomas Petazzoni val = mvreg_read(pp, MVNETA_UNIT_CONTROL); 144671408602SThomas Petazzoni val &= ~MVNETA_PHY_POLLING_ENABLE; 144771408602SThomas Petazzoni mvreg_write(pp, MVNETA_UNIT_CONTROL, val); 144871408602SThomas Petazzoni 1449c5aff182SThomas Petazzoni mvneta_set_ucast_table(pp, -1); 1450c5aff182SThomas Petazzoni mvneta_set_special_mcast_table(pp, -1); 1451c5aff182SThomas Petazzoni mvneta_set_other_mcast_table(pp, -1); 1452c5aff182SThomas Petazzoni 1453c5aff182SThomas Petazzoni /* Set port interrupt enable register - default enable all */ 1454c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_INTR_ENABLE, 1455c5aff182SThomas Petazzoni (MVNETA_RXQ_INTR_ENABLE_ALL_MASK 1456c5aff182SThomas Petazzoni | MVNETA_TXQ_INTR_ENABLE_ALL_MASK)); 1457e483911fSAndrew Lunn 1458e483911fSAndrew Lunn mvneta_mib_counters_clear(pp); 1459c5aff182SThomas Petazzoni } 1460c5aff182SThomas Petazzoni 1461c5aff182SThomas Petazzoni /* Set max sizes for tx queues */ 1462c5aff182SThomas Petazzoni static void mvneta_txq_max_tx_size_set(struct mvneta_port *pp, int max_tx_size) 1463c5aff182SThomas Petazzoni 1464c5aff182SThomas Petazzoni { 1465c5aff182SThomas Petazzoni u32 val, size, mtu; 1466c5aff182SThomas Petazzoni int queue; 1467c5aff182SThomas Petazzoni 1468c5aff182SThomas Petazzoni mtu = max_tx_size * 8; 1469c5aff182SThomas Petazzoni if (mtu > MVNETA_TX_MTU_MAX) 1470c5aff182SThomas Petazzoni mtu = MVNETA_TX_MTU_MAX; 1471c5aff182SThomas Petazzoni 1472c5aff182SThomas Petazzoni /* Set MTU */ 1473c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_TX_MTU); 1474c5aff182SThomas Petazzoni val &= ~MVNETA_TX_MTU_MAX; 1475c5aff182SThomas Petazzoni val |= mtu; 1476c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_TX_MTU, val); 1477c5aff182SThomas Petazzoni 1478c5aff182SThomas Petazzoni /* TX token size and all TXQs token size must be larger that MTU */ 1479c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_TX_TOKEN_SIZE); 1480c5aff182SThomas Petazzoni 1481c5aff182SThomas Petazzoni size = val & MVNETA_TX_TOKEN_SIZE_MAX; 1482c5aff182SThomas Petazzoni if (size < mtu) { 1483c5aff182SThomas Petazzoni size = mtu; 1484c5aff182SThomas Petazzoni val &= ~MVNETA_TX_TOKEN_SIZE_MAX; 1485c5aff182SThomas Petazzoni val |= size; 1486c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_TX_TOKEN_SIZE, val); 1487c5aff182SThomas Petazzoni } 1488c5aff182SThomas Petazzoni for (queue = 0; queue < txq_number; queue++) { 1489c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_TXQ_TOKEN_SIZE_REG(queue)); 1490c5aff182SThomas Petazzoni 1491c5aff182SThomas Petazzoni size = val & MVNETA_TXQ_TOKEN_SIZE_MAX; 1492c5aff182SThomas Petazzoni if (size < mtu) { 1493c5aff182SThomas Petazzoni size = mtu; 1494c5aff182SThomas Petazzoni val &= ~MVNETA_TXQ_TOKEN_SIZE_MAX; 1495c5aff182SThomas Petazzoni val |= size; 1496c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_TXQ_TOKEN_SIZE_REG(queue), val); 1497c5aff182SThomas Petazzoni } 1498c5aff182SThomas Petazzoni } 1499c5aff182SThomas Petazzoni } 1500c5aff182SThomas Petazzoni 1501c5aff182SThomas Petazzoni /* Set unicast address */ 1502c5aff182SThomas Petazzoni static void mvneta_set_ucast_addr(struct mvneta_port *pp, u8 last_nibble, 1503c5aff182SThomas Petazzoni int queue) 1504c5aff182SThomas Petazzoni { 1505c5aff182SThomas Petazzoni unsigned int unicast_reg; 1506c5aff182SThomas Petazzoni unsigned int tbl_offset; 1507c5aff182SThomas Petazzoni unsigned int reg_offset; 1508c5aff182SThomas Petazzoni 1509c5aff182SThomas Petazzoni /* Locate the Unicast table entry */ 1510c5aff182SThomas Petazzoni last_nibble = (0xf & last_nibble); 1511c5aff182SThomas Petazzoni 1512c5aff182SThomas Petazzoni /* offset from unicast tbl base */ 1513c5aff182SThomas Petazzoni tbl_offset = (last_nibble / 4) * 4; 1514c5aff182SThomas Petazzoni 1515c5aff182SThomas Petazzoni /* offset within the above reg */ 1516c5aff182SThomas Petazzoni reg_offset = last_nibble % 4; 1517c5aff182SThomas Petazzoni 1518c5aff182SThomas Petazzoni unicast_reg = mvreg_read(pp, (MVNETA_DA_FILT_UCAST_BASE + tbl_offset)); 1519c5aff182SThomas Petazzoni 1520c5aff182SThomas Petazzoni if (queue == -1) { 1521c5aff182SThomas Petazzoni /* Clear accepts frame bit at specified unicast DA tbl entry */ 1522c5aff182SThomas Petazzoni unicast_reg &= ~(0xff << (8 * reg_offset)); 1523c5aff182SThomas Petazzoni } else { 1524c5aff182SThomas Petazzoni unicast_reg &= ~(0xff << (8 * reg_offset)); 1525c5aff182SThomas Petazzoni unicast_reg |= ((0x01 | (queue << 1)) << (8 * reg_offset)); 1526c5aff182SThomas Petazzoni } 1527c5aff182SThomas Petazzoni 1528c5aff182SThomas Petazzoni mvreg_write(pp, (MVNETA_DA_FILT_UCAST_BASE + tbl_offset), unicast_reg); 1529c5aff182SThomas Petazzoni } 1530c5aff182SThomas Petazzoni 1531c5aff182SThomas Petazzoni /* Set mac address */ 1532c5aff182SThomas Petazzoni static void mvneta_mac_addr_set(struct mvneta_port *pp, unsigned char *addr, 1533c5aff182SThomas Petazzoni int queue) 1534c5aff182SThomas Petazzoni { 1535c5aff182SThomas Petazzoni unsigned int mac_h; 1536c5aff182SThomas Petazzoni unsigned int mac_l; 1537c5aff182SThomas Petazzoni 1538c5aff182SThomas Petazzoni if (queue != -1) { 1539c5aff182SThomas Petazzoni mac_l = (addr[4] << 8) | (addr[5]); 1540c5aff182SThomas Petazzoni mac_h = (addr[0] << 24) | (addr[1] << 16) | 1541c5aff182SThomas Petazzoni (addr[2] << 8) | (addr[3] << 0); 1542c5aff182SThomas Petazzoni 1543c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_MAC_ADDR_LOW, mac_l); 1544c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_MAC_ADDR_HIGH, mac_h); 1545c5aff182SThomas Petazzoni } 1546c5aff182SThomas Petazzoni 1547c5aff182SThomas Petazzoni /* Accept frames of this address */ 1548c5aff182SThomas Petazzoni mvneta_set_ucast_addr(pp, addr[5], queue); 1549c5aff182SThomas Petazzoni } 1550c5aff182SThomas Petazzoni 15516a20c175SThomas Petazzoni /* Set the number of packets that will be received before RX interrupt 15526a20c175SThomas Petazzoni * will be generated by HW. 1553c5aff182SThomas Petazzoni */ 1554c5aff182SThomas Petazzoni static void mvneta_rx_pkts_coal_set(struct mvneta_port *pp, 1555c5aff182SThomas Petazzoni struct mvneta_rx_queue *rxq, u32 value) 1556c5aff182SThomas Petazzoni { 1557c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_RXQ_THRESHOLD_REG(rxq->id), 1558c5aff182SThomas Petazzoni value | MVNETA_RXQ_NON_OCCUPIED(0)); 1559c5aff182SThomas Petazzoni } 1560c5aff182SThomas Petazzoni 15616a20c175SThomas Petazzoni /* Set the time delay in usec before RX interrupt will be generated by 15626a20c175SThomas Petazzoni * HW. 1563c5aff182SThomas Petazzoni */ 1564c5aff182SThomas Petazzoni static void mvneta_rx_time_coal_set(struct mvneta_port *pp, 1565c5aff182SThomas Petazzoni struct mvneta_rx_queue *rxq, u32 value) 1566c5aff182SThomas Petazzoni { 1567189dd626SThomas Petazzoni u32 val; 1568189dd626SThomas Petazzoni unsigned long clk_rate; 1569189dd626SThomas Petazzoni 1570189dd626SThomas Petazzoni clk_rate = clk_get_rate(pp->clk); 1571189dd626SThomas Petazzoni val = (clk_rate / 1000000) * value; 1572c5aff182SThomas Petazzoni 1573c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_RXQ_TIME_COAL_REG(rxq->id), val); 1574c5aff182SThomas Petazzoni } 1575c5aff182SThomas Petazzoni 1576c5aff182SThomas Petazzoni /* Set threshold for TX_DONE pkts coalescing */ 1577c5aff182SThomas Petazzoni static void mvneta_tx_done_pkts_coal_set(struct mvneta_port *pp, 1578c5aff182SThomas Petazzoni struct mvneta_tx_queue *txq, u32 value) 1579c5aff182SThomas Petazzoni { 1580c5aff182SThomas Petazzoni u32 val; 1581c5aff182SThomas Petazzoni 1582c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_TXQ_SIZE_REG(txq->id)); 1583c5aff182SThomas Petazzoni 1584c5aff182SThomas Petazzoni val &= ~MVNETA_TXQ_SENT_THRESH_ALL_MASK; 1585c5aff182SThomas Petazzoni val |= MVNETA_TXQ_SENT_THRESH_MASK(value); 1586c5aff182SThomas Petazzoni 1587c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_TXQ_SIZE_REG(txq->id), val); 1588c5aff182SThomas Petazzoni } 1589c5aff182SThomas Petazzoni 1590c5aff182SThomas Petazzoni /* Handle rx descriptor fill by setting buf_cookie and buf_phys_addr */ 1591c5aff182SThomas Petazzoni static void mvneta_rx_desc_fill(struct mvneta_rx_desc *rx_desc, 1592f88bee1cSGregory CLEMENT u32 phys_addr, void *virt_addr, 1593f88bee1cSGregory CLEMENT struct mvneta_rx_queue *rxq) 1594c5aff182SThomas Petazzoni { 1595f88bee1cSGregory CLEMENT int i; 1596f88bee1cSGregory CLEMENT 1597c5aff182SThomas Petazzoni rx_desc->buf_phys_addr = phys_addr; 1598f88bee1cSGregory CLEMENT i = rx_desc - rxq->descs; 1599f88bee1cSGregory CLEMENT rxq->buf_virt_addr[i] = virt_addr; 1600c5aff182SThomas Petazzoni } 1601c5aff182SThomas Petazzoni 1602c5aff182SThomas Petazzoni /* Decrement sent descriptors counter */ 1603c5aff182SThomas Petazzoni static void mvneta_txq_sent_desc_dec(struct mvneta_port *pp, 1604c5aff182SThomas Petazzoni struct mvneta_tx_queue *txq, 1605c5aff182SThomas Petazzoni int sent_desc) 1606c5aff182SThomas Petazzoni { 1607c5aff182SThomas Petazzoni u32 val; 1608c5aff182SThomas Petazzoni 1609c5aff182SThomas Petazzoni /* Only 255 TX descriptors can be updated at once */ 1610c5aff182SThomas Petazzoni while (sent_desc > 0xff) { 1611c5aff182SThomas Petazzoni val = 0xff << MVNETA_TXQ_DEC_SENT_SHIFT; 1612c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val); 1613c5aff182SThomas Petazzoni sent_desc = sent_desc - 0xff; 1614c5aff182SThomas Petazzoni } 1615c5aff182SThomas Petazzoni 1616c5aff182SThomas Petazzoni val = sent_desc << MVNETA_TXQ_DEC_SENT_SHIFT; 1617c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val); 1618c5aff182SThomas Petazzoni } 1619c5aff182SThomas Petazzoni 1620c5aff182SThomas Petazzoni /* Get number of TX descriptors already sent by HW */ 1621c5aff182SThomas Petazzoni static int mvneta_txq_sent_desc_num_get(struct mvneta_port *pp, 1622c5aff182SThomas Petazzoni struct mvneta_tx_queue *txq) 1623c5aff182SThomas Petazzoni { 1624c5aff182SThomas Petazzoni u32 val; 1625c5aff182SThomas Petazzoni int sent_desc; 1626c5aff182SThomas Petazzoni 1627c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_TXQ_STATUS_REG(txq->id)); 1628c5aff182SThomas Petazzoni sent_desc = (val & MVNETA_TXQ_SENT_DESC_MASK) >> 1629c5aff182SThomas Petazzoni MVNETA_TXQ_SENT_DESC_SHIFT; 1630c5aff182SThomas Petazzoni 1631c5aff182SThomas Petazzoni return sent_desc; 1632c5aff182SThomas Petazzoni } 1633c5aff182SThomas Petazzoni 16346a20c175SThomas Petazzoni /* Get number of sent descriptors and decrement counter. 1635c5aff182SThomas Petazzoni * The number of sent descriptors is returned. 1636c5aff182SThomas Petazzoni */ 1637c5aff182SThomas Petazzoni static int mvneta_txq_sent_desc_proc(struct mvneta_port *pp, 1638c5aff182SThomas Petazzoni struct mvneta_tx_queue *txq) 1639c5aff182SThomas Petazzoni { 1640c5aff182SThomas Petazzoni int sent_desc; 1641c5aff182SThomas Petazzoni 1642c5aff182SThomas Petazzoni /* Get number of sent descriptors */ 1643c5aff182SThomas Petazzoni sent_desc = mvneta_txq_sent_desc_num_get(pp, txq); 1644c5aff182SThomas Petazzoni 1645c5aff182SThomas Petazzoni /* Decrement sent descriptors counter */ 1646c5aff182SThomas Petazzoni if (sent_desc) 1647c5aff182SThomas Petazzoni mvneta_txq_sent_desc_dec(pp, txq, sent_desc); 1648c5aff182SThomas Petazzoni 1649c5aff182SThomas Petazzoni return sent_desc; 1650c5aff182SThomas Petazzoni } 1651c5aff182SThomas Petazzoni 1652c5aff182SThomas Petazzoni /* Set TXQ descriptors fields relevant for CSUM calculation */ 1653c5aff182SThomas Petazzoni static u32 mvneta_txq_desc_csum(int l3_offs, int l3_proto, 1654c5aff182SThomas Petazzoni int ip_hdr_len, int l4_proto) 1655c5aff182SThomas Petazzoni { 1656c5aff182SThomas Petazzoni u32 command; 1657c5aff182SThomas Petazzoni 1658c5aff182SThomas Petazzoni /* Fields: L3_offset, IP_hdrlen, L3_type, G_IPv4_chk, 16596a20c175SThomas Petazzoni * G_L4_chk, L4_type; required only for checksum 16606a20c175SThomas Petazzoni * calculation 16616a20c175SThomas Petazzoni */ 1662c5aff182SThomas Petazzoni command = l3_offs << MVNETA_TX_L3_OFF_SHIFT; 1663c5aff182SThomas Petazzoni command |= ip_hdr_len << MVNETA_TX_IP_HLEN_SHIFT; 1664c5aff182SThomas Petazzoni 16650a198587SThomas Fitzsimmons if (l3_proto == htons(ETH_P_IP)) 1666c5aff182SThomas Petazzoni command |= MVNETA_TXD_IP_CSUM; 1667c5aff182SThomas Petazzoni else 1668c5aff182SThomas Petazzoni command |= MVNETA_TX_L3_IP6; 1669c5aff182SThomas Petazzoni 1670c5aff182SThomas Petazzoni if (l4_proto == IPPROTO_TCP) 1671c5aff182SThomas Petazzoni command |= MVNETA_TX_L4_CSUM_FULL; 1672c5aff182SThomas Petazzoni else if (l4_proto == IPPROTO_UDP) 1673c5aff182SThomas Petazzoni command |= MVNETA_TX_L4_UDP | MVNETA_TX_L4_CSUM_FULL; 1674c5aff182SThomas Petazzoni else 1675c5aff182SThomas Petazzoni command |= MVNETA_TX_L4_CSUM_NOT; 1676c5aff182SThomas Petazzoni 1677c5aff182SThomas Petazzoni return command; 1678c5aff182SThomas Petazzoni } 1679c5aff182SThomas Petazzoni 1680c5aff182SThomas Petazzoni 1681c5aff182SThomas Petazzoni /* Display more error info */ 1682c5aff182SThomas Petazzoni static void mvneta_rx_error(struct mvneta_port *pp, 1683c5aff182SThomas Petazzoni struct mvneta_rx_desc *rx_desc) 1684c5aff182SThomas Petazzoni { 1685c5aff182SThomas Petazzoni u32 status = rx_desc->status; 1686c5aff182SThomas Petazzoni 16875428213cSwilly tarreau if (!mvneta_rxq_desc_is_first_last(status)) { 1688c5aff182SThomas Petazzoni netdev_err(pp->dev, 1689c5aff182SThomas Petazzoni "bad rx status %08x (buffer oversize), size=%d\n", 16905428213cSwilly tarreau status, rx_desc->data_size); 1691c5aff182SThomas Petazzoni return; 1692c5aff182SThomas Petazzoni } 1693c5aff182SThomas Petazzoni 1694c5aff182SThomas Petazzoni switch (status & MVNETA_RXD_ERR_CODE_MASK) { 1695c5aff182SThomas Petazzoni case MVNETA_RXD_ERR_CRC: 1696c5aff182SThomas Petazzoni netdev_err(pp->dev, "bad rx status %08x (crc error), size=%d\n", 1697c5aff182SThomas Petazzoni status, rx_desc->data_size); 1698c5aff182SThomas Petazzoni break; 1699c5aff182SThomas Petazzoni case MVNETA_RXD_ERR_OVERRUN: 1700c5aff182SThomas Petazzoni netdev_err(pp->dev, "bad rx status %08x (overrun error), size=%d\n", 1701c5aff182SThomas Petazzoni status, rx_desc->data_size); 1702c5aff182SThomas Petazzoni break; 1703c5aff182SThomas Petazzoni case MVNETA_RXD_ERR_LEN: 1704c5aff182SThomas Petazzoni netdev_err(pp->dev, "bad rx status %08x (max frame length error), size=%d\n", 1705c5aff182SThomas Petazzoni status, rx_desc->data_size); 1706c5aff182SThomas Petazzoni break; 1707c5aff182SThomas Petazzoni case MVNETA_RXD_ERR_RESOURCE: 1708c5aff182SThomas Petazzoni netdev_err(pp->dev, "bad rx status %08x (resource error), size=%d\n", 1709c5aff182SThomas Petazzoni status, rx_desc->data_size); 1710c5aff182SThomas Petazzoni break; 1711c5aff182SThomas Petazzoni } 1712c5aff182SThomas Petazzoni } 1713c5aff182SThomas Petazzoni 17145428213cSwilly tarreau /* Handle RX checksum offload based on the descriptor's status */ 17155428213cSwilly tarreau static void mvneta_rx_csum(struct mvneta_port *pp, u32 status, 1716c5aff182SThomas Petazzoni struct sk_buff *skb) 1717c5aff182SThomas Petazzoni { 17185428213cSwilly tarreau if ((status & MVNETA_RXD_L3_IP4) && 17195428213cSwilly tarreau (status & MVNETA_RXD_L4_CSUM_OK)) { 1720c5aff182SThomas Petazzoni skb->csum = 0; 1721c5aff182SThomas Petazzoni skb->ip_summed = CHECKSUM_UNNECESSARY; 1722c5aff182SThomas Petazzoni return; 1723c5aff182SThomas Petazzoni } 1724c5aff182SThomas Petazzoni 1725c5aff182SThomas Petazzoni skb->ip_summed = CHECKSUM_NONE; 1726c5aff182SThomas Petazzoni } 1727c5aff182SThomas Petazzoni 17286c498974Swilly tarreau /* Return tx queue pointer (find last set bit) according to <cause> returned 17296c498974Swilly tarreau * form tx_done reg. <cause> must not be null. The return value is always a 17306c498974Swilly tarreau * valid queue for matching the first one found in <cause>. 17316c498974Swilly tarreau */ 1732c5aff182SThomas Petazzoni static struct mvneta_tx_queue *mvneta_tx_done_policy(struct mvneta_port *pp, 1733c5aff182SThomas Petazzoni u32 cause) 1734c5aff182SThomas Petazzoni { 1735c5aff182SThomas Petazzoni int queue = fls(cause) - 1; 1736c5aff182SThomas Petazzoni 17376c498974Swilly tarreau return &pp->txqs[queue]; 1738c5aff182SThomas Petazzoni } 1739c5aff182SThomas Petazzoni 1740c5aff182SThomas Petazzoni /* Free tx queue skbuffs */ 1741c5aff182SThomas Petazzoni static void mvneta_txq_bufs_free(struct mvneta_port *pp, 1742a29b6235SMarcin Wojtas struct mvneta_tx_queue *txq, int num, 1743a29b6235SMarcin Wojtas struct netdev_queue *nq) 1744c5aff182SThomas Petazzoni { 1745a29b6235SMarcin Wojtas unsigned int bytes_compl = 0, pkts_compl = 0; 1746c5aff182SThomas Petazzoni int i; 1747c5aff182SThomas Petazzoni 1748c5aff182SThomas Petazzoni for (i = 0; i < num; i++) { 1749c5aff182SThomas Petazzoni struct mvneta_tx_desc *tx_desc = txq->descs + 1750c5aff182SThomas Petazzoni txq->txq_get_index; 1751c5aff182SThomas Petazzoni struct sk_buff *skb = txq->tx_skb[txq->txq_get_index]; 1752c5aff182SThomas Petazzoni 1753a29b6235SMarcin Wojtas if (skb) { 1754a29b6235SMarcin Wojtas bytes_compl += skb->len; 1755a29b6235SMarcin Wojtas pkts_compl++; 1756a29b6235SMarcin Wojtas } 1757a29b6235SMarcin Wojtas 1758c5aff182SThomas Petazzoni mvneta_txq_inc_get(txq); 1759c5aff182SThomas Petazzoni 17602e3173a3SEzequiel Garcia if (!IS_TSO_HEADER(txq, tx_desc->buf_phys_addr)) 17612e3173a3SEzequiel Garcia dma_unmap_single(pp->dev->dev.parent, 17622e3173a3SEzequiel Garcia tx_desc->buf_phys_addr, 1763c5aff182SThomas Petazzoni tx_desc->data_size, DMA_TO_DEVICE); 1764ba7e46efSEzequiel Garcia if (!skb) 1765ba7e46efSEzequiel Garcia continue; 1766c5aff182SThomas Petazzoni dev_kfree_skb_any(skb); 1767c5aff182SThomas Petazzoni } 1768a29b6235SMarcin Wojtas 1769a29b6235SMarcin Wojtas netdev_tx_completed_queue(nq, pkts_compl, bytes_compl); 1770c5aff182SThomas Petazzoni } 1771c5aff182SThomas Petazzoni 1772c5aff182SThomas Petazzoni /* Handle end of transmission */ 1773cd713199SArnaud Ebalard static void mvneta_txq_done(struct mvneta_port *pp, 1774c5aff182SThomas Petazzoni struct mvneta_tx_queue *txq) 1775c5aff182SThomas Petazzoni { 1776c5aff182SThomas Petazzoni struct netdev_queue *nq = netdev_get_tx_queue(pp->dev, txq->id); 1777c5aff182SThomas Petazzoni int tx_done; 1778c5aff182SThomas Petazzoni 1779c5aff182SThomas Petazzoni tx_done = mvneta_txq_sent_desc_proc(pp, txq); 1780cd713199SArnaud Ebalard if (!tx_done) 1781cd713199SArnaud Ebalard return; 1782cd713199SArnaud Ebalard 1783a29b6235SMarcin Wojtas mvneta_txq_bufs_free(pp, txq, tx_done, nq); 1784c5aff182SThomas Petazzoni 1785c5aff182SThomas Petazzoni txq->count -= tx_done; 1786c5aff182SThomas Petazzoni 1787c5aff182SThomas Petazzoni if (netif_tx_queue_stopped(nq)) { 17888eef5f97SEzequiel Garcia if (txq->count <= txq->tx_wake_threshold) 1789c5aff182SThomas Petazzoni netif_tx_wake_queue(nq); 1790c5aff182SThomas Petazzoni } 1791c5aff182SThomas Petazzoni } 1792c5aff182SThomas Petazzoni 1793dc35a10fSMarcin Wojtas void *mvneta_frag_alloc(unsigned int frag_size) 17948ec2cd48Swilly tarreau { 1795dc35a10fSMarcin Wojtas if (likely(frag_size <= PAGE_SIZE)) 1796dc35a10fSMarcin Wojtas return netdev_alloc_frag(frag_size); 17978ec2cd48Swilly tarreau else 1798dc35a10fSMarcin Wojtas return kmalloc(frag_size, GFP_ATOMIC); 17998ec2cd48Swilly tarreau } 1800dc35a10fSMarcin Wojtas EXPORT_SYMBOL_GPL(mvneta_frag_alloc); 18018ec2cd48Swilly tarreau 1802dc35a10fSMarcin Wojtas void mvneta_frag_free(unsigned int frag_size, void *data) 18038ec2cd48Swilly tarreau { 1804dc35a10fSMarcin Wojtas if (likely(frag_size <= PAGE_SIZE)) 180513dc0d2bSAlexander Duyck skb_free_frag(data); 18068ec2cd48Swilly tarreau else 18078ec2cd48Swilly tarreau kfree(data); 18088ec2cd48Swilly tarreau } 1809dc35a10fSMarcin Wojtas EXPORT_SYMBOL_GPL(mvneta_frag_free); 18108ec2cd48Swilly tarreau 1811dc35a10fSMarcin Wojtas /* Refill processing for SW buffer management */ 1812c5aff182SThomas Petazzoni static int mvneta_rx_refill(struct mvneta_port *pp, 1813f88bee1cSGregory CLEMENT struct mvneta_rx_desc *rx_desc, 1814f88bee1cSGregory CLEMENT struct mvneta_rx_queue *rxq) 1815c5aff182SThomas Petazzoni 1816c5aff182SThomas Petazzoni { 1817c5aff182SThomas Petazzoni dma_addr_t phys_addr; 18188ec2cd48Swilly tarreau void *data; 1819c5aff182SThomas Petazzoni 1820dc35a10fSMarcin Wojtas data = mvneta_frag_alloc(pp->frag_size); 18218ec2cd48Swilly tarreau if (!data) 1822c5aff182SThomas Petazzoni return -ENOMEM; 1823c5aff182SThomas Petazzoni 18248ec2cd48Swilly tarreau phys_addr = dma_map_single(pp->dev->dev.parent, data, 1825c5aff182SThomas Petazzoni MVNETA_RX_BUF_SIZE(pp->pkt_size), 1826c5aff182SThomas Petazzoni DMA_FROM_DEVICE); 1827c5aff182SThomas Petazzoni if (unlikely(dma_mapping_error(pp->dev->dev.parent, phys_addr))) { 1828dc35a10fSMarcin Wojtas mvneta_frag_free(pp->frag_size, data); 1829c5aff182SThomas Petazzoni return -ENOMEM; 1830c5aff182SThomas Petazzoni } 1831c5aff182SThomas Petazzoni 18328d5047cfSMarcin Wojtas phys_addr += pp->rx_offset_correction; 1833f88bee1cSGregory CLEMENT mvneta_rx_desc_fill(rx_desc, phys_addr, data, rxq); 1834c5aff182SThomas Petazzoni return 0; 1835c5aff182SThomas Petazzoni } 1836c5aff182SThomas Petazzoni 1837c5aff182SThomas Petazzoni /* Handle tx checksum */ 1838c5aff182SThomas Petazzoni static u32 mvneta_skb_tx_csum(struct mvneta_port *pp, struct sk_buff *skb) 1839c5aff182SThomas Petazzoni { 1840c5aff182SThomas Petazzoni if (skb->ip_summed == CHECKSUM_PARTIAL) { 1841c5aff182SThomas Petazzoni int ip_hdr_len = 0; 1842817dbfa5SVlad Yasevich __be16 l3_proto = vlan_get_protocol(skb); 1843c5aff182SThomas Petazzoni u8 l4_proto; 1844c5aff182SThomas Petazzoni 1845817dbfa5SVlad Yasevich if (l3_proto == htons(ETH_P_IP)) { 1846c5aff182SThomas Petazzoni struct iphdr *ip4h = ip_hdr(skb); 1847c5aff182SThomas Petazzoni 1848c5aff182SThomas Petazzoni /* Calculate IPv4 checksum and L4 checksum */ 1849c5aff182SThomas Petazzoni ip_hdr_len = ip4h->ihl; 1850c5aff182SThomas Petazzoni l4_proto = ip4h->protocol; 1851817dbfa5SVlad Yasevich } else if (l3_proto == htons(ETH_P_IPV6)) { 1852c5aff182SThomas Petazzoni struct ipv6hdr *ip6h = ipv6_hdr(skb); 1853c5aff182SThomas Petazzoni 1854c5aff182SThomas Petazzoni /* Read l4_protocol from one of IPv6 extra headers */ 1855c5aff182SThomas Petazzoni if (skb_network_header_len(skb) > 0) 1856c5aff182SThomas Petazzoni ip_hdr_len = (skb_network_header_len(skb) >> 2); 1857c5aff182SThomas Petazzoni l4_proto = ip6h->nexthdr; 1858c5aff182SThomas Petazzoni } else 1859c5aff182SThomas Petazzoni return MVNETA_TX_L4_CSUM_NOT; 1860c5aff182SThomas Petazzoni 1861c5aff182SThomas Petazzoni return mvneta_txq_desc_csum(skb_network_offset(skb), 1862817dbfa5SVlad Yasevich l3_proto, ip_hdr_len, l4_proto); 1863c5aff182SThomas Petazzoni } 1864c5aff182SThomas Petazzoni 1865c5aff182SThomas Petazzoni return MVNETA_TX_L4_CSUM_NOT; 1866c5aff182SThomas Petazzoni } 1867c5aff182SThomas Petazzoni 1868c5aff182SThomas Petazzoni /* Drop packets received by the RXQ and free buffers */ 1869c5aff182SThomas Petazzoni static void mvneta_rxq_drop_pkts(struct mvneta_port *pp, 1870c5aff182SThomas Petazzoni struct mvneta_rx_queue *rxq) 1871c5aff182SThomas Petazzoni { 1872c5aff182SThomas Petazzoni int rx_done, i; 1873c5aff182SThomas Petazzoni 1874c5aff182SThomas Petazzoni rx_done = mvneta_rxq_busy_desc_num_get(pp, rxq); 1875dc35a10fSMarcin Wojtas if (rx_done) 1876dc35a10fSMarcin Wojtas mvneta_rxq_desc_num_update(pp, rxq, rx_done, rx_done); 1877dc35a10fSMarcin Wojtas 1878dc35a10fSMarcin Wojtas if (pp->bm_priv) { 1879dc35a10fSMarcin Wojtas for (i = 0; i < rx_done; i++) { 1880dc35a10fSMarcin Wojtas struct mvneta_rx_desc *rx_desc = 1881dc35a10fSMarcin Wojtas mvneta_rxq_next_desc_get(rxq); 1882dc35a10fSMarcin Wojtas u8 pool_id = MVNETA_RX_GET_BM_POOL_ID(rx_desc); 1883dc35a10fSMarcin Wojtas struct mvneta_bm_pool *bm_pool; 1884dc35a10fSMarcin Wojtas 1885dc35a10fSMarcin Wojtas bm_pool = &pp->bm_priv->bm_pools[pool_id]; 1886dc35a10fSMarcin Wojtas /* Return dropped buffer to the pool */ 1887dc35a10fSMarcin Wojtas mvneta_bm_pool_put_bp(pp->bm_priv, bm_pool, 1888dc35a10fSMarcin Wojtas rx_desc->buf_phys_addr); 1889dc35a10fSMarcin Wojtas } 1890dc35a10fSMarcin Wojtas return; 1891dc35a10fSMarcin Wojtas } 1892dc35a10fSMarcin Wojtas 1893c5aff182SThomas Petazzoni for (i = 0; i < rxq->size; i++) { 1894c5aff182SThomas Petazzoni struct mvneta_rx_desc *rx_desc = rxq->descs + i; 1895f88bee1cSGregory CLEMENT void *data = rxq->buf_virt_addr[i]; 1896c5aff182SThomas Petazzoni 1897c5aff182SThomas Petazzoni dma_unmap_single(pp->dev->dev.parent, rx_desc->buf_phys_addr, 1898a328f3a0SEzequiel Garcia MVNETA_RX_BUF_SIZE(pp->pkt_size), DMA_FROM_DEVICE); 1899dc35a10fSMarcin Wojtas mvneta_frag_free(pp->frag_size, data); 1900dc35a10fSMarcin Wojtas } 1901c5aff182SThomas Petazzoni } 1902c5aff182SThomas Petazzoni 1903dc35a10fSMarcin Wojtas /* Main rx processing when using software buffer management */ 1904dc35a10fSMarcin Wojtas static int mvneta_rx_swbm(struct mvneta_port *pp, int rx_todo, 1905c5aff182SThomas Petazzoni struct mvneta_rx_queue *rxq) 1906c5aff182SThomas Petazzoni { 190712bb03b4SMaxime Ripard struct mvneta_pcpu_port *port = this_cpu_ptr(pp->ports); 1908c5aff182SThomas Petazzoni struct net_device *dev = pp->dev; 1909a84e3289SSimon Guinot int rx_done; 1910dc4277ddSwilly tarreau u32 rcvd_pkts = 0; 1911dc4277ddSwilly tarreau u32 rcvd_bytes = 0; 1912c5aff182SThomas Petazzoni 1913c5aff182SThomas Petazzoni /* Get number of received packets */ 1914c5aff182SThomas Petazzoni rx_done = mvneta_rxq_busy_desc_num_get(pp, rxq); 1915c5aff182SThomas Petazzoni 1916c5aff182SThomas Petazzoni if (rx_todo > rx_done) 1917c5aff182SThomas Petazzoni rx_todo = rx_done; 1918c5aff182SThomas Petazzoni 1919c5aff182SThomas Petazzoni rx_done = 0; 1920c5aff182SThomas Petazzoni 1921c5aff182SThomas Petazzoni /* Fairness NAPI loop */ 1922c5aff182SThomas Petazzoni while (rx_done < rx_todo) { 1923c5aff182SThomas Petazzoni struct mvneta_rx_desc *rx_desc = mvneta_rxq_next_desc_get(rxq); 1924c5aff182SThomas Petazzoni struct sk_buff *skb; 19258ec2cd48Swilly tarreau unsigned char *data; 1926daf158d0SSimon Guinot dma_addr_t phys_addr; 1927dc35a10fSMarcin Wojtas u32 rx_status, frag_size; 1928f88bee1cSGregory CLEMENT int rx_bytes, err, index; 1929c5aff182SThomas Petazzoni 1930c5aff182SThomas Petazzoni rx_done++; 1931c5aff182SThomas Petazzoni rx_status = rx_desc->status; 1932f19fadfcSwilly tarreau rx_bytes = rx_desc->data_size - (ETH_FCS_LEN + MVNETA_MH_SIZE); 1933f88bee1cSGregory CLEMENT index = rx_desc - rxq->descs; 1934f88bee1cSGregory CLEMENT data = rxq->buf_virt_addr[index]; 1935daf158d0SSimon Guinot phys_addr = rx_desc->buf_phys_addr; 1936c5aff182SThomas Petazzoni 19375428213cSwilly tarreau if (!mvneta_rxq_desc_is_first_last(rx_status) || 1938f19fadfcSwilly tarreau (rx_status & MVNETA_RXD_ERR_SUMMARY)) { 19392eecb2e0SYelena Krivosheev mvneta_rx_error(pp, rx_desc); 1940f19fadfcSwilly tarreau err_drop_frame: 1941c5aff182SThomas Petazzoni dev->stats.rx_errors++; 19428ec2cd48Swilly tarreau /* leave the descriptor untouched */ 1943c5aff182SThomas Petazzoni continue; 1944c5aff182SThomas Petazzoni } 1945c5aff182SThomas Petazzoni 1946f19fadfcSwilly tarreau if (rx_bytes <= rx_copybreak) { 1947f19fadfcSwilly tarreau /* better copy a small frame and not unmap the DMA region */ 1948f19fadfcSwilly tarreau skb = netdev_alloc_skb_ip_align(dev, rx_bytes); 1949f19fadfcSwilly tarreau if (unlikely(!skb)) 1950f19fadfcSwilly tarreau goto err_drop_frame; 1951f19fadfcSwilly tarreau 1952f19fadfcSwilly tarreau dma_sync_single_range_for_cpu(dev->dev.parent, 1953ac83b7ddSGregory CLEMENT phys_addr, 1954f19fadfcSwilly tarreau MVNETA_MH_SIZE + NET_SKB_PAD, 1955f19fadfcSwilly tarreau rx_bytes, 1956f19fadfcSwilly tarreau DMA_FROM_DEVICE); 195759ae1d12SJohannes Berg skb_put_data(skb, data + MVNETA_MH_SIZE + NET_SKB_PAD, 1958f19fadfcSwilly tarreau rx_bytes); 1959f19fadfcSwilly tarreau 1960f19fadfcSwilly tarreau skb->protocol = eth_type_trans(skb, dev); 1961f19fadfcSwilly tarreau mvneta_rx_csum(pp, rx_status, skb); 196212bb03b4SMaxime Ripard napi_gro_receive(&port->napi, skb); 1963f19fadfcSwilly tarreau 1964f19fadfcSwilly tarreau rcvd_pkts++; 1965f19fadfcSwilly tarreau rcvd_bytes += rx_bytes; 1966f19fadfcSwilly tarreau 1967f19fadfcSwilly tarreau /* leave the descriptor and buffer untouched */ 1968f19fadfcSwilly tarreau continue; 1969f19fadfcSwilly tarreau } 1970f19fadfcSwilly tarreau 1971a84e3289SSimon Guinot /* Refill processing */ 1972f88bee1cSGregory CLEMENT err = mvneta_rx_refill(pp, rx_desc, rxq); 1973a84e3289SSimon Guinot if (err) { 1974a84e3289SSimon Guinot netdev_err(dev, "Linux processing - Can't refill\n"); 1975a84e3289SSimon Guinot rxq->missed++; 1976a84e3289SSimon Guinot goto err_drop_frame; 1977a84e3289SSimon Guinot } 1978a84e3289SSimon Guinot 1979dc35a10fSMarcin Wojtas frag_size = pp->frag_size; 1980dc35a10fSMarcin Wojtas 1981dc35a10fSMarcin Wojtas skb = build_skb(data, frag_size > PAGE_SIZE ? 0 : frag_size); 1982f19fadfcSwilly tarreau 198326c17a17SMarcin Wojtas /* After refill old buffer has to be unmapped regardless 198426c17a17SMarcin Wojtas * the skb is successfully built or not. 198526c17a17SMarcin Wojtas */ 1986daf158d0SSimon Guinot dma_unmap_single(dev->dev.parent, phys_addr, 1987dc35a10fSMarcin Wojtas MVNETA_RX_BUF_SIZE(pp->pkt_size), 1988dc35a10fSMarcin Wojtas DMA_FROM_DEVICE); 1989c5aff182SThomas Petazzoni 199026c17a17SMarcin Wojtas if (!skb) 199126c17a17SMarcin Wojtas goto err_drop_frame; 199226c17a17SMarcin Wojtas 1993dc4277ddSwilly tarreau rcvd_pkts++; 1994dc4277ddSwilly tarreau rcvd_bytes += rx_bytes; 1995c5aff182SThomas Petazzoni 1996c5aff182SThomas Petazzoni /* Linux processing */ 19978ec2cd48Swilly tarreau skb_reserve(skb, MVNETA_MH_SIZE + NET_SKB_PAD); 1998c5aff182SThomas Petazzoni skb_put(skb, rx_bytes); 1999c5aff182SThomas Petazzoni 2000c5aff182SThomas Petazzoni skb->protocol = eth_type_trans(skb, dev); 2001c5aff182SThomas Petazzoni 20025428213cSwilly tarreau mvneta_rx_csum(pp, rx_status, skb); 2003c5aff182SThomas Petazzoni 200412bb03b4SMaxime Ripard napi_gro_receive(&port->napi, skb); 2005c5aff182SThomas Petazzoni } 2006c5aff182SThomas Petazzoni 2007dc4277ddSwilly tarreau if (rcvd_pkts) { 200874c41b04Swilly tarreau struct mvneta_pcpu_stats *stats = this_cpu_ptr(pp->stats); 200974c41b04Swilly tarreau 201074c41b04Swilly tarreau u64_stats_update_begin(&stats->syncp); 201174c41b04Swilly tarreau stats->rx_packets += rcvd_pkts; 201274c41b04Swilly tarreau stats->rx_bytes += rcvd_bytes; 201374c41b04Swilly tarreau u64_stats_update_end(&stats->syncp); 2014dc4277ddSwilly tarreau } 2015dc4277ddSwilly tarreau 2016c5aff182SThomas Petazzoni /* Update rxq management counters */ 2017a84e3289SSimon Guinot mvneta_rxq_desc_num_update(pp, rxq, rx_done, rx_done); 2018c5aff182SThomas Petazzoni 2019c5aff182SThomas Petazzoni return rx_done; 2020c5aff182SThomas Petazzoni } 2021c5aff182SThomas Petazzoni 2022dc35a10fSMarcin Wojtas /* Main rx processing when using hardware buffer management */ 2023dc35a10fSMarcin Wojtas static int mvneta_rx_hwbm(struct mvneta_port *pp, int rx_todo, 2024dc35a10fSMarcin Wojtas struct mvneta_rx_queue *rxq) 2025dc35a10fSMarcin Wojtas { 2026dc35a10fSMarcin Wojtas struct mvneta_pcpu_port *port = this_cpu_ptr(pp->ports); 2027dc35a10fSMarcin Wojtas struct net_device *dev = pp->dev; 2028dc35a10fSMarcin Wojtas int rx_done; 2029dc35a10fSMarcin Wojtas u32 rcvd_pkts = 0; 2030dc35a10fSMarcin Wojtas u32 rcvd_bytes = 0; 2031dc35a10fSMarcin Wojtas 2032dc35a10fSMarcin Wojtas /* Get number of received packets */ 2033dc35a10fSMarcin Wojtas rx_done = mvneta_rxq_busy_desc_num_get(pp, rxq); 2034dc35a10fSMarcin Wojtas 2035dc35a10fSMarcin Wojtas if (rx_todo > rx_done) 2036dc35a10fSMarcin Wojtas rx_todo = rx_done; 2037dc35a10fSMarcin Wojtas 2038dc35a10fSMarcin Wojtas rx_done = 0; 2039dc35a10fSMarcin Wojtas 2040dc35a10fSMarcin Wojtas /* Fairness NAPI loop */ 2041dc35a10fSMarcin Wojtas while (rx_done < rx_todo) { 2042dc35a10fSMarcin Wojtas struct mvneta_rx_desc *rx_desc = mvneta_rxq_next_desc_get(rxq); 2043dc35a10fSMarcin Wojtas struct mvneta_bm_pool *bm_pool = NULL; 2044dc35a10fSMarcin Wojtas struct sk_buff *skb; 2045dc35a10fSMarcin Wojtas unsigned char *data; 2046dc35a10fSMarcin Wojtas dma_addr_t phys_addr; 2047dc35a10fSMarcin Wojtas u32 rx_status, frag_size; 2048dc35a10fSMarcin Wojtas int rx_bytes, err; 2049dc35a10fSMarcin Wojtas u8 pool_id; 2050dc35a10fSMarcin Wojtas 2051dc35a10fSMarcin Wojtas rx_done++; 2052dc35a10fSMarcin Wojtas rx_status = rx_desc->status; 2053dc35a10fSMarcin Wojtas rx_bytes = rx_desc->data_size - (ETH_FCS_LEN + MVNETA_MH_SIZE); 2054f88bee1cSGregory CLEMENT data = (u8 *)(uintptr_t)rx_desc->buf_cookie; 2055dc35a10fSMarcin Wojtas phys_addr = rx_desc->buf_phys_addr; 2056dc35a10fSMarcin Wojtas pool_id = MVNETA_RX_GET_BM_POOL_ID(rx_desc); 2057dc35a10fSMarcin Wojtas bm_pool = &pp->bm_priv->bm_pools[pool_id]; 2058dc35a10fSMarcin Wojtas 2059dc35a10fSMarcin Wojtas if (!mvneta_rxq_desc_is_first_last(rx_status) || 2060dc35a10fSMarcin Wojtas (rx_status & MVNETA_RXD_ERR_SUMMARY)) { 2061dc35a10fSMarcin Wojtas err_drop_frame_ret_pool: 2062dc35a10fSMarcin Wojtas /* Return the buffer to the pool */ 2063dc35a10fSMarcin Wojtas mvneta_bm_pool_put_bp(pp->bm_priv, bm_pool, 2064dc35a10fSMarcin Wojtas rx_desc->buf_phys_addr); 2065dc35a10fSMarcin Wojtas err_drop_frame: 2066dc35a10fSMarcin Wojtas dev->stats.rx_errors++; 2067dc35a10fSMarcin Wojtas mvneta_rx_error(pp, rx_desc); 2068dc35a10fSMarcin Wojtas /* leave the descriptor untouched */ 2069dc35a10fSMarcin Wojtas continue; 2070dc35a10fSMarcin Wojtas } 2071dc35a10fSMarcin Wojtas 2072dc35a10fSMarcin Wojtas if (rx_bytes <= rx_copybreak) { 2073dc35a10fSMarcin Wojtas /* better copy a small frame and not unmap the DMA region */ 2074dc35a10fSMarcin Wojtas skb = netdev_alloc_skb_ip_align(dev, rx_bytes); 2075dc35a10fSMarcin Wojtas if (unlikely(!skb)) 2076dc35a10fSMarcin Wojtas goto err_drop_frame_ret_pool; 2077dc35a10fSMarcin Wojtas 2078dc35a10fSMarcin Wojtas dma_sync_single_range_for_cpu(dev->dev.parent, 2079dc35a10fSMarcin Wojtas rx_desc->buf_phys_addr, 2080dc35a10fSMarcin Wojtas MVNETA_MH_SIZE + NET_SKB_PAD, 2081dc35a10fSMarcin Wojtas rx_bytes, 2082dc35a10fSMarcin Wojtas DMA_FROM_DEVICE); 208359ae1d12SJohannes Berg skb_put_data(skb, data + MVNETA_MH_SIZE + NET_SKB_PAD, 2084dc35a10fSMarcin Wojtas rx_bytes); 2085dc35a10fSMarcin Wojtas 2086dc35a10fSMarcin Wojtas skb->protocol = eth_type_trans(skb, dev); 2087dc35a10fSMarcin Wojtas mvneta_rx_csum(pp, rx_status, skb); 2088dc35a10fSMarcin Wojtas napi_gro_receive(&port->napi, skb); 2089dc35a10fSMarcin Wojtas 2090dc35a10fSMarcin Wojtas rcvd_pkts++; 2091dc35a10fSMarcin Wojtas rcvd_bytes += rx_bytes; 2092dc35a10fSMarcin Wojtas 2093dc35a10fSMarcin Wojtas /* Return the buffer to the pool */ 2094dc35a10fSMarcin Wojtas mvneta_bm_pool_put_bp(pp->bm_priv, bm_pool, 2095dc35a10fSMarcin Wojtas rx_desc->buf_phys_addr); 2096dc35a10fSMarcin Wojtas 2097dc35a10fSMarcin Wojtas /* leave the descriptor and buffer untouched */ 2098dc35a10fSMarcin Wojtas continue; 2099dc35a10fSMarcin Wojtas } 2100dc35a10fSMarcin Wojtas 2101dc35a10fSMarcin Wojtas /* Refill processing */ 2102baa11ebcSGregory CLEMENT err = hwbm_pool_refill(&bm_pool->hwbm_pool, GFP_ATOMIC); 2103dc35a10fSMarcin Wojtas if (err) { 2104dc35a10fSMarcin Wojtas netdev_err(dev, "Linux processing - Can't refill\n"); 2105dc35a10fSMarcin Wojtas rxq->missed++; 2106dc35a10fSMarcin Wojtas goto err_drop_frame_ret_pool; 2107dc35a10fSMarcin Wojtas } 2108dc35a10fSMarcin Wojtas 2109baa11ebcSGregory CLEMENT frag_size = bm_pool->hwbm_pool.frag_size; 2110dc35a10fSMarcin Wojtas 2111dc35a10fSMarcin Wojtas skb = build_skb(data, frag_size > PAGE_SIZE ? 0 : frag_size); 2112dc35a10fSMarcin Wojtas 2113dc35a10fSMarcin Wojtas /* After refill old buffer has to be unmapped regardless 2114dc35a10fSMarcin Wojtas * the skb is successfully built or not. 2115dc35a10fSMarcin Wojtas */ 2116dc35a10fSMarcin Wojtas dma_unmap_single(&pp->bm_priv->pdev->dev, phys_addr, 2117dc35a10fSMarcin Wojtas bm_pool->buf_size, DMA_FROM_DEVICE); 2118dc35a10fSMarcin Wojtas if (!skb) 2119dc35a10fSMarcin Wojtas goto err_drop_frame; 2120dc35a10fSMarcin Wojtas 2121dc35a10fSMarcin Wojtas rcvd_pkts++; 2122dc35a10fSMarcin Wojtas rcvd_bytes += rx_bytes; 2123dc35a10fSMarcin Wojtas 2124dc35a10fSMarcin Wojtas /* Linux processing */ 2125dc35a10fSMarcin Wojtas skb_reserve(skb, MVNETA_MH_SIZE + NET_SKB_PAD); 2126dc35a10fSMarcin Wojtas skb_put(skb, rx_bytes); 2127dc35a10fSMarcin Wojtas 2128dc35a10fSMarcin Wojtas skb->protocol = eth_type_trans(skb, dev); 2129dc35a10fSMarcin Wojtas 2130dc35a10fSMarcin Wojtas mvneta_rx_csum(pp, rx_status, skb); 2131dc35a10fSMarcin Wojtas 2132dc35a10fSMarcin Wojtas napi_gro_receive(&port->napi, skb); 2133dc35a10fSMarcin Wojtas } 2134dc35a10fSMarcin Wojtas 2135dc35a10fSMarcin Wojtas if (rcvd_pkts) { 2136dc35a10fSMarcin Wojtas struct mvneta_pcpu_stats *stats = this_cpu_ptr(pp->stats); 2137dc35a10fSMarcin Wojtas 2138dc35a10fSMarcin Wojtas u64_stats_update_begin(&stats->syncp); 2139dc35a10fSMarcin Wojtas stats->rx_packets += rcvd_pkts; 2140dc35a10fSMarcin Wojtas stats->rx_bytes += rcvd_bytes; 2141dc35a10fSMarcin Wojtas u64_stats_update_end(&stats->syncp); 2142dc35a10fSMarcin Wojtas } 2143dc35a10fSMarcin Wojtas 2144dc35a10fSMarcin Wojtas /* Update rxq management counters */ 2145dc35a10fSMarcin Wojtas mvneta_rxq_desc_num_update(pp, rxq, rx_done, rx_done); 2146dc35a10fSMarcin Wojtas 2147dc35a10fSMarcin Wojtas return rx_done; 2148dc35a10fSMarcin Wojtas } 2149dc35a10fSMarcin Wojtas 21502adb719dSEzequiel Garcia static inline void 21512adb719dSEzequiel Garcia mvneta_tso_put_hdr(struct sk_buff *skb, 21522adb719dSEzequiel Garcia struct mvneta_port *pp, struct mvneta_tx_queue *txq) 21532adb719dSEzequiel Garcia { 21542adb719dSEzequiel Garcia struct mvneta_tx_desc *tx_desc; 21552adb719dSEzequiel Garcia int hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb); 21562adb719dSEzequiel Garcia 21572adb719dSEzequiel Garcia txq->tx_skb[txq->txq_put_index] = NULL; 21582adb719dSEzequiel Garcia tx_desc = mvneta_txq_next_desc_get(txq); 21592adb719dSEzequiel Garcia tx_desc->data_size = hdr_len; 21602adb719dSEzequiel Garcia tx_desc->command = mvneta_skb_tx_csum(pp, skb); 21612adb719dSEzequiel Garcia tx_desc->command |= MVNETA_TXD_F_DESC; 21622adb719dSEzequiel Garcia tx_desc->buf_phys_addr = txq->tso_hdrs_phys + 21632adb719dSEzequiel Garcia txq->txq_put_index * TSO_HEADER_SIZE; 21642adb719dSEzequiel Garcia mvneta_txq_inc_put(txq); 21652adb719dSEzequiel Garcia } 21662adb719dSEzequiel Garcia 21672adb719dSEzequiel Garcia static inline int 21682adb719dSEzequiel Garcia mvneta_tso_put_data(struct net_device *dev, struct mvneta_tx_queue *txq, 21692adb719dSEzequiel Garcia struct sk_buff *skb, char *data, int size, 21702adb719dSEzequiel Garcia bool last_tcp, bool is_last) 21712adb719dSEzequiel Garcia { 21722adb719dSEzequiel Garcia struct mvneta_tx_desc *tx_desc; 21732adb719dSEzequiel Garcia 21742adb719dSEzequiel Garcia tx_desc = mvneta_txq_next_desc_get(txq); 21752adb719dSEzequiel Garcia tx_desc->data_size = size; 21762adb719dSEzequiel Garcia tx_desc->buf_phys_addr = dma_map_single(dev->dev.parent, data, 21772adb719dSEzequiel Garcia size, DMA_TO_DEVICE); 21782adb719dSEzequiel Garcia if (unlikely(dma_mapping_error(dev->dev.parent, 21792adb719dSEzequiel Garcia tx_desc->buf_phys_addr))) { 21802adb719dSEzequiel Garcia mvneta_txq_desc_put(txq); 21812adb719dSEzequiel Garcia return -ENOMEM; 21822adb719dSEzequiel Garcia } 21832adb719dSEzequiel Garcia 21842adb719dSEzequiel Garcia tx_desc->command = 0; 21852adb719dSEzequiel Garcia txq->tx_skb[txq->txq_put_index] = NULL; 21862adb719dSEzequiel Garcia 21872adb719dSEzequiel Garcia if (last_tcp) { 21882adb719dSEzequiel Garcia /* last descriptor in the TCP packet */ 21892adb719dSEzequiel Garcia tx_desc->command = MVNETA_TXD_L_DESC; 21902adb719dSEzequiel Garcia 21912adb719dSEzequiel Garcia /* last descriptor in SKB */ 21922adb719dSEzequiel Garcia if (is_last) 21932adb719dSEzequiel Garcia txq->tx_skb[txq->txq_put_index] = skb; 21942adb719dSEzequiel Garcia } 21952adb719dSEzequiel Garcia mvneta_txq_inc_put(txq); 21962adb719dSEzequiel Garcia return 0; 21972adb719dSEzequiel Garcia } 21982adb719dSEzequiel Garcia 21992adb719dSEzequiel Garcia static int mvneta_tx_tso(struct sk_buff *skb, struct net_device *dev, 22002adb719dSEzequiel Garcia struct mvneta_tx_queue *txq) 22012adb719dSEzequiel Garcia { 22022adb719dSEzequiel Garcia int total_len, data_left; 22032adb719dSEzequiel Garcia int desc_count = 0; 22042adb719dSEzequiel Garcia struct mvneta_port *pp = netdev_priv(dev); 22052adb719dSEzequiel Garcia struct tso_t tso; 22062adb719dSEzequiel Garcia int hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb); 22072adb719dSEzequiel Garcia int i; 22082adb719dSEzequiel Garcia 22092adb719dSEzequiel Garcia /* Count needed descriptors */ 22102adb719dSEzequiel Garcia if ((txq->count + tso_count_descs(skb)) >= txq->size) 22112adb719dSEzequiel Garcia return 0; 22122adb719dSEzequiel Garcia 22132adb719dSEzequiel Garcia if (skb_headlen(skb) < (skb_transport_offset(skb) + tcp_hdrlen(skb))) { 22142adb719dSEzequiel Garcia pr_info("*** Is this even possible???!?!?\n"); 22152adb719dSEzequiel Garcia return 0; 22162adb719dSEzequiel Garcia } 22172adb719dSEzequiel Garcia 22182adb719dSEzequiel Garcia /* Initialize the TSO handler, and prepare the first payload */ 22192adb719dSEzequiel Garcia tso_start(skb, &tso); 22202adb719dSEzequiel Garcia 22212adb719dSEzequiel Garcia total_len = skb->len - hdr_len; 22222adb719dSEzequiel Garcia while (total_len > 0) { 22232adb719dSEzequiel Garcia char *hdr; 22242adb719dSEzequiel Garcia 22252adb719dSEzequiel Garcia data_left = min_t(int, skb_shinfo(skb)->gso_size, total_len); 22262adb719dSEzequiel Garcia total_len -= data_left; 22272adb719dSEzequiel Garcia desc_count++; 22282adb719dSEzequiel Garcia 22292adb719dSEzequiel Garcia /* prepare packet headers: MAC + IP + TCP */ 22302adb719dSEzequiel Garcia hdr = txq->tso_hdrs + txq->txq_put_index * TSO_HEADER_SIZE; 22312adb719dSEzequiel Garcia tso_build_hdr(skb, hdr, &tso, data_left, total_len == 0); 22322adb719dSEzequiel Garcia 22332adb719dSEzequiel Garcia mvneta_tso_put_hdr(skb, pp, txq); 22342adb719dSEzequiel Garcia 22352adb719dSEzequiel Garcia while (data_left > 0) { 22362adb719dSEzequiel Garcia int size; 22372adb719dSEzequiel Garcia desc_count++; 22382adb719dSEzequiel Garcia 22392adb719dSEzequiel Garcia size = min_t(int, tso.size, data_left); 22402adb719dSEzequiel Garcia 22412adb719dSEzequiel Garcia if (mvneta_tso_put_data(dev, txq, skb, 22422adb719dSEzequiel Garcia tso.data, size, 22432adb719dSEzequiel Garcia size == data_left, 22442adb719dSEzequiel Garcia total_len == 0)) 22452adb719dSEzequiel Garcia goto err_release; 22462adb719dSEzequiel Garcia data_left -= size; 22472adb719dSEzequiel Garcia 22482adb719dSEzequiel Garcia tso_build_data(skb, &tso, size); 22492adb719dSEzequiel Garcia } 22502adb719dSEzequiel Garcia } 22512adb719dSEzequiel Garcia 22522adb719dSEzequiel Garcia return desc_count; 22532adb719dSEzequiel Garcia 22542adb719dSEzequiel Garcia err_release: 22552adb719dSEzequiel Garcia /* Release all used data descriptors; header descriptors must not 22562adb719dSEzequiel Garcia * be DMA-unmapped. 22572adb719dSEzequiel Garcia */ 22582adb719dSEzequiel Garcia for (i = desc_count - 1; i >= 0; i--) { 22592adb719dSEzequiel Garcia struct mvneta_tx_desc *tx_desc = txq->descs + i; 22602e3173a3SEzequiel Garcia if (!IS_TSO_HEADER(txq, tx_desc->buf_phys_addr)) 22612adb719dSEzequiel Garcia dma_unmap_single(pp->dev->dev.parent, 22622adb719dSEzequiel Garcia tx_desc->buf_phys_addr, 22632adb719dSEzequiel Garcia tx_desc->data_size, 22642adb719dSEzequiel Garcia DMA_TO_DEVICE); 22652adb719dSEzequiel Garcia mvneta_txq_desc_put(txq); 22662adb719dSEzequiel Garcia } 22672adb719dSEzequiel Garcia return 0; 22682adb719dSEzequiel Garcia } 22692adb719dSEzequiel Garcia 2270c5aff182SThomas Petazzoni /* Handle tx fragmentation processing */ 2271c5aff182SThomas Petazzoni static int mvneta_tx_frag_process(struct mvneta_port *pp, struct sk_buff *skb, 2272c5aff182SThomas Petazzoni struct mvneta_tx_queue *txq) 2273c5aff182SThomas Petazzoni { 2274c5aff182SThomas Petazzoni struct mvneta_tx_desc *tx_desc; 22753d4ea02fSEzequiel Garcia int i, nr_frags = skb_shinfo(skb)->nr_frags; 2276c5aff182SThomas Petazzoni 22773d4ea02fSEzequiel Garcia for (i = 0; i < nr_frags; i++) { 2278c5aff182SThomas Petazzoni skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 2279c5aff182SThomas Petazzoni void *addr = page_address(frag->page.p) + frag->page_offset; 2280c5aff182SThomas Petazzoni 2281c5aff182SThomas Petazzoni tx_desc = mvneta_txq_next_desc_get(txq); 2282c5aff182SThomas Petazzoni tx_desc->data_size = frag->size; 2283c5aff182SThomas Petazzoni 2284c5aff182SThomas Petazzoni tx_desc->buf_phys_addr = 2285c5aff182SThomas Petazzoni dma_map_single(pp->dev->dev.parent, addr, 2286c5aff182SThomas Petazzoni tx_desc->data_size, DMA_TO_DEVICE); 2287c5aff182SThomas Petazzoni 2288c5aff182SThomas Petazzoni if (dma_mapping_error(pp->dev->dev.parent, 2289c5aff182SThomas Petazzoni tx_desc->buf_phys_addr)) { 2290c5aff182SThomas Petazzoni mvneta_txq_desc_put(txq); 2291c5aff182SThomas Petazzoni goto error; 2292c5aff182SThomas Petazzoni } 2293c5aff182SThomas Petazzoni 22943d4ea02fSEzequiel Garcia if (i == nr_frags - 1) { 2295c5aff182SThomas Petazzoni /* Last descriptor */ 2296c5aff182SThomas Petazzoni tx_desc->command = MVNETA_TXD_L_DESC | MVNETA_TXD_Z_PAD; 2297c5aff182SThomas Petazzoni txq->tx_skb[txq->txq_put_index] = skb; 2298c5aff182SThomas Petazzoni } else { 2299c5aff182SThomas Petazzoni /* Descriptor in the middle: Not First, Not Last */ 2300c5aff182SThomas Petazzoni tx_desc->command = 0; 2301c5aff182SThomas Petazzoni txq->tx_skb[txq->txq_put_index] = NULL; 2302c5aff182SThomas Petazzoni } 23033d4ea02fSEzequiel Garcia mvneta_txq_inc_put(txq); 2304c5aff182SThomas Petazzoni } 2305c5aff182SThomas Petazzoni 2306c5aff182SThomas Petazzoni return 0; 2307c5aff182SThomas Petazzoni 2308c5aff182SThomas Petazzoni error: 2309c5aff182SThomas Petazzoni /* Release all descriptors that were used to map fragments of 23106a20c175SThomas Petazzoni * this packet, as well as the corresponding DMA mappings 23116a20c175SThomas Petazzoni */ 2312c5aff182SThomas Petazzoni for (i = i - 1; i >= 0; i--) { 2313c5aff182SThomas Petazzoni tx_desc = txq->descs + i; 2314c5aff182SThomas Petazzoni dma_unmap_single(pp->dev->dev.parent, 2315c5aff182SThomas Petazzoni tx_desc->buf_phys_addr, 2316c5aff182SThomas Petazzoni tx_desc->data_size, 2317c5aff182SThomas Petazzoni DMA_TO_DEVICE); 2318c5aff182SThomas Petazzoni mvneta_txq_desc_put(txq); 2319c5aff182SThomas Petazzoni } 2320c5aff182SThomas Petazzoni 2321c5aff182SThomas Petazzoni return -ENOMEM; 2322c5aff182SThomas Petazzoni } 2323c5aff182SThomas Petazzoni 2324c5aff182SThomas Petazzoni /* Main tx processing */ 2325c5aff182SThomas Petazzoni static int mvneta_tx(struct sk_buff *skb, struct net_device *dev) 2326c5aff182SThomas Petazzoni { 2327c5aff182SThomas Petazzoni struct mvneta_port *pp = netdev_priv(dev); 2328ee40a116SWilly Tarreau u16 txq_id = skb_get_queue_mapping(skb); 2329ee40a116SWilly Tarreau struct mvneta_tx_queue *txq = &pp->txqs[txq_id]; 2330c5aff182SThomas Petazzoni struct mvneta_tx_desc *tx_desc; 23315f478b41SEric Dumazet int len = skb->len; 2332c5aff182SThomas Petazzoni int frags = 0; 2333c5aff182SThomas Petazzoni u32 tx_cmd; 2334c5aff182SThomas Petazzoni 2335c5aff182SThomas Petazzoni if (!netif_running(dev)) 2336c5aff182SThomas Petazzoni goto out; 2337c5aff182SThomas Petazzoni 23382adb719dSEzequiel Garcia if (skb_is_gso(skb)) { 23392adb719dSEzequiel Garcia frags = mvneta_tx_tso(skb, dev, txq); 23402adb719dSEzequiel Garcia goto out; 23412adb719dSEzequiel Garcia } 23422adb719dSEzequiel Garcia 2343c5aff182SThomas Petazzoni frags = skb_shinfo(skb)->nr_frags + 1; 2344c5aff182SThomas Petazzoni 2345c5aff182SThomas Petazzoni /* Get a descriptor for the first part of the packet */ 2346c5aff182SThomas Petazzoni tx_desc = mvneta_txq_next_desc_get(txq); 2347c5aff182SThomas Petazzoni 2348c5aff182SThomas Petazzoni tx_cmd = mvneta_skb_tx_csum(pp, skb); 2349c5aff182SThomas Petazzoni 2350c5aff182SThomas Petazzoni tx_desc->data_size = skb_headlen(skb); 2351c5aff182SThomas Petazzoni 2352c5aff182SThomas Petazzoni tx_desc->buf_phys_addr = dma_map_single(dev->dev.parent, skb->data, 2353c5aff182SThomas Petazzoni tx_desc->data_size, 2354c5aff182SThomas Petazzoni DMA_TO_DEVICE); 2355c5aff182SThomas Petazzoni if (unlikely(dma_mapping_error(dev->dev.parent, 2356c5aff182SThomas Petazzoni tx_desc->buf_phys_addr))) { 2357c5aff182SThomas Petazzoni mvneta_txq_desc_put(txq); 2358c5aff182SThomas Petazzoni frags = 0; 2359c5aff182SThomas Petazzoni goto out; 2360c5aff182SThomas Petazzoni } 2361c5aff182SThomas Petazzoni 2362c5aff182SThomas Petazzoni if (frags == 1) { 2363c5aff182SThomas Petazzoni /* First and Last descriptor */ 2364c5aff182SThomas Petazzoni tx_cmd |= MVNETA_TXD_FLZ_DESC; 2365c5aff182SThomas Petazzoni tx_desc->command = tx_cmd; 2366c5aff182SThomas Petazzoni txq->tx_skb[txq->txq_put_index] = skb; 2367c5aff182SThomas Petazzoni mvneta_txq_inc_put(txq); 2368c5aff182SThomas Petazzoni } else { 2369c5aff182SThomas Petazzoni /* First but not Last */ 2370c5aff182SThomas Petazzoni tx_cmd |= MVNETA_TXD_F_DESC; 2371c5aff182SThomas Petazzoni txq->tx_skb[txq->txq_put_index] = NULL; 2372c5aff182SThomas Petazzoni mvneta_txq_inc_put(txq); 2373c5aff182SThomas Petazzoni tx_desc->command = tx_cmd; 2374c5aff182SThomas Petazzoni /* Continue with other skb fragments */ 2375c5aff182SThomas Petazzoni if (mvneta_tx_frag_process(pp, skb, txq)) { 2376c5aff182SThomas Petazzoni dma_unmap_single(dev->dev.parent, 2377c5aff182SThomas Petazzoni tx_desc->buf_phys_addr, 2378c5aff182SThomas Petazzoni tx_desc->data_size, 2379c5aff182SThomas Petazzoni DMA_TO_DEVICE); 2380c5aff182SThomas Petazzoni mvneta_txq_desc_put(txq); 2381c5aff182SThomas Petazzoni frags = 0; 2382c5aff182SThomas Petazzoni goto out; 2383c5aff182SThomas Petazzoni } 2384c5aff182SThomas Petazzoni } 2385c5aff182SThomas Petazzoni 2386e19d2ddaSEzequiel Garcia out: 2387e19d2ddaSEzequiel Garcia if (frags > 0) { 2388e19d2ddaSEzequiel Garcia struct mvneta_pcpu_stats *stats = this_cpu_ptr(pp->stats); 2389e19d2ddaSEzequiel Garcia struct netdev_queue *nq = netdev_get_tx_queue(dev, txq_id); 2390e19d2ddaSEzequiel Garcia 2391a29b6235SMarcin Wojtas netdev_tx_sent_queue(nq, len); 2392a29b6235SMarcin Wojtas 2393c5aff182SThomas Petazzoni txq->count += frags; 23948eef5f97SEzequiel Garcia if (txq->count >= txq->tx_stop_threshold) 2395c5aff182SThomas Petazzoni netif_tx_stop_queue(nq); 2396c5aff182SThomas Petazzoni 23972a90f7e1SSimon Guinot if (!skb->xmit_more || netif_xmit_stopped(nq) || 23982a90f7e1SSimon Guinot txq->pending + frags > MVNETA_TXQ_DEC_SENT_MASK) 23992a90f7e1SSimon Guinot mvneta_txq_pend_desc_add(pp, txq, frags); 24002a90f7e1SSimon Guinot else 24012a90f7e1SSimon Guinot txq->pending += frags; 24022a90f7e1SSimon Guinot 240374c41b04Swilly tarreau u64_stats_update_begin(&stats->syncp); 240474c41b04Swilly tarreau stats->tx_packets++; 24055f478b41SEric Dumazet stats->tx_bytes += len; 240674c41b04Swilly tarreau u64_stats_update_end(&stats->syncp); 2407c5aff182SThomas Petazzoni } else { 2408c5aff182SThomas Petazzoni dev->stats.tx_dropped++; 2409c5aff182SThomas Petazzoni dev_kfree_skb_any(skb); 2410c5aff182SThomas Petazzoni } 2411c5aff182SThomas Petazzoni 2412c5aff182SThomas Petazzoni return NETDEV_TX_OK; 2413c5aff182SThomas Petazzoni } 2414c5aff182SThomas Petazzoni 2415c5aff182SThomas Petazzoni 2416c5aff182SThomas Petazzoni /* Free tx resources, when resetting a port */ 2417c5aff182SThomas Petazzoni static void mvneta_txq_done_force(struct mvneta_port *pp, 2418c5aff182SThomas Petazzoni struct mvneta_tx_queue *txq) 2419c5aff182SThomas Petazzoni 2420c5aff182SThomas Petazzoni { 2421a29b6235SMarcin Wojtas struct netdev_queue *nq = netdev_get_tx_queue(pp->dev, txq->id); 2422c5aff182SThomas Petazzoni int tx_done = txq->count; 2423c5aff182SThomas Petazzoni 2424a29b6235SMarcin Wojtas mvneta_txq_bufs_free(pp, txq, tx_done, nq); 2425c5aff182SThomas Petazzoni 2426c5aff182SThomas Petazzoni /* reset txq */ 2427c5aff182SThomas Petazzoni txq->count = 0; 2428c5aff182SThomas Petazzoni txq->txq_put_index = 0; 2429c5aff182SThomas Petazzoni txq->txq_get_index = 0; 2430c5aff182SThomas Petazzoni } 2431c5aff182SThomas Petazzoni 24326c498974Swilly tarreau /* Handle tx done - called in softirq context. The <cause_tx_done> argument 24336c498974Swilly tarreau * must be a valid cause according to MVNETA_TXQ_INTR_MASK_ALL. 24346c498974Swilly tarreau */ 24350713a86aSArnaud Ebalard static void mvneta_tx_done_gbe(struct mvneta_port *pp, u32 cause_tx_done) 2436c5aff182SThomas Petazzoni { 2437c5aff182SThomas Petazzoni struct mvneta_tx_queue *txq; 2438c5aff182SThomas Petazzoni struct netdev_queue *nq; 2439c5aff182SThomas Petazzoni 24406c498974Swilly tarreau while (cause_tx_done) { 2441c5aff182SThomas Petazzoni txq = mvneta_tx_done_policy(pp, cause_tx_done); 2442c5aff182SThomas Petazzoni 2443c5aff182SThomas Petazzoni nq = netdev_get_tx_queue(pp->dev, txq->id); 2444c5aff182SThomas Petazzoni __netif_tx_lock(nq, smp_processor_id()); 2445c5aff182SThomas Petazzoni 24460713a86aSArnaud Ebalard if (txq->count) 24470713a86aSArnaud Ebalard mvneta_txq_done(pp, txq); 2448c5aff182SThomas Petazzoni 2449c5aff182SThomas Petazzoni __netif_tx_unlock(nq); 2450c5aff182SThomas Petazzoni cause_tx_done &= ~((1 << txq->id)); 2451c5aff182SThomas Petazzoni } 2452c5aff182SThomas Petazzoni } 2453c5aff182SThomas Petazzoni 24546a20c175SThomas Petazzoni /* Compute crc8 of the specified address, using a unique algorithm , 2455c5aff182SThomas Petazzoni * according to hw spec, different than generic crc8 algorithm 2456c5aff182SThomas Petazzoni */ 2457c5aff182SThomas Petazzoni static int mvneta_addr_crc(unsigned char *addr) 2458c5aff182SThomas Petazzoni { 2459c5aff182SThomas Petazzoni int crc = 0; 2460c5aff182SThomas Petazzoni int i; 2461c5aff182SThomas Petazzoni 2462c5aff182SThomas Petazzoni for (i = 0; i < ETH_ALEN; i++) { 2463c5aff182SThomas Petazzoni int j; 2464c5aff182SThomas Petazzoni 2465c5aff182SThomas Petazzoni crc = (crc ^ addr[i]) << 8; 2466c5aff182SThomas Petazzoni for (j = 7; j >= 0; j--) { 2467c5aff182SThomas Petazzoni if (crc & (0x100 << j)) 2468c5aff182SThomas Petazzoni crc ^= 0x107 << j; 2469c5aff182SThomas Petazzoni } 2470c5aff182SThomas Petazzoni } 2471c5aff182SThomas Petazzoni 2472c5aff182SThomas Petazzoni return crc; 2473c5aff182SThomas Petazzoni } 2474c5aff182SThomas Petazzoni 2475c5aff182SThomas Petazzoni /* This method controls the net device special MAC multicast support. 2476c5aff182SThomas Petazzoni * The Special Multicast Table for MAC addresses supports MAC of the form 2477c5aff182SThomas Petazzoni * 0x01-00-5E-00-00-XX (where XX is between 0x00 and 0xFF). 2478c5aff182SThomas Petazzoni * The MAC DA[7:0] bits are used as a pointer to the Special Multicast 2479c5aff182SThomas Petazzoni * Table entries in the DA-Filter table. This method set the Special 2480c5aff182SThomas Petazzoni * Multicast Table appropriate entry. 2481c5aff182SThomas Petazzoni */ 2482c5aff182SThomas Petazzoni static void mvneta_set_special_mcast_addr(struct mvneta_port *pp, 2483c5aff182SThomas Petazzoni unsigned char last_byte, 2484c5aff182SThomas Petazzoni int queue) 2485c5aff182SThomas Petazzoni { 2486c5aff182SThomas Petazzoni unsigned int smc_table_reg; 2487c5aff182SThomas Petazzoni unsigned int tbl_offset; 2488c5aff182SThomas Petazzoni unsigned int reg_offset; 2489c5aff182SThomas Petazzoni 2490c5aff182SThomas Petazzoni /* Register offset from SMC table base */ 2491c5aff182SThomas Petazzoni tbl_offset = (last_byte / 4); 2492c5aff182SThomas Petazzoni /* Entry offset within the above reg */ 2493c5aff182SThomas Petazzoni reg_offset = last_byte % 4; 2494c5aff182SThomas Petazzoni 2495c5aff182SThomas Petazzoni smc_table_reg = mvreg_read(pp, (MVNETA_DA_FILT_SPEC_MCAST 2496c5aff182SThomas Petazzoni + tbl_offset * 4)); 2497c5aff182SThomas Petazzoni 2498c5aff182SThomas Petazzoni if (queue == -1) 2499c5aff182SThomas Petazzoni smc_table_reg &= ~(0xff << (8 * reg_offset)); 2500c5aff182SThomas Petazzoni else { 2501c5aff182SThomas Petazzoni smc_table_reg &= ~(0xff << (8 * reg_offset)); 2502c5aff182SThomas Petazzoni smc_table_reg |= ((0x01 | (queue << 1)) << (8 * reg_offset)); 2503c5aff182SThomas Petazzoni } 2504c5aff182SThomas Petazzoni 2505c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_DA_FILT_SPEC_MCAST + tbl_offset * 4, 2506c5aff182SThomas Petazzoni smc_table_reg); 2507c5aff182SThomas Petazzoni } 2508c5aff182SThomas Petazzoni 2509c5aff182SThomas Petazzoni /* This method controls the network device Other MAC multicast support. 2510c5aff182SThomas Petazzoni * The Other Multicast Table is used for multicast of another type. 2511c5aff182SThomas Petazzoni * A CRC-8 is used as an index to the Other Multicast Table entries 2512c5aff182SThomas Petazzoni * in the DA-Filter table. 2513c5aff182SThomas Petazzoni * The method gets the CRC-8 value from the calling routine and 2514c5aff182SThomas Petazzoni * sets the Other Multicast Table appropriate entry according to the 2515c5aff182SThomas Petazzoni * specified CRC-8 . 2516c5aff182SThomas Petazzoni */ 2517c5aff182SThomas Petazzoni static void mvneta_set_other_mcast_addr(struct mvneta_port *pp, 2518c5aff182SThomas Petazzoni unsigned char crc8, 2519c5aff182SThomas Petazzoni int queue) 2520c5aff182SThomas Petazzoni { 2521c5aff182SThomas Petazzoni unsigned int omc_table_reg; 2522c5aff182SThomas Petazzoni unsigned int tbl_offset; 2523c5aff182SThomas Petazzoni unsigned int reg_offset; 2524c5aff182SThomas Petazzoni 2525c5aff182SThomas Petazzoni tbl_offset = (crc8 / 4) * 4; /* Register offset from OMC table base */ 2526c5aff182SThomas Petazzoni reg_offset = crc8 % 4; /* Entry offset within the above reg */ 2527c5aff182SThomas Petazzoni 2528c5aff182SThomas Petazzoni omc_table_reg = mvreg_read(pp, MVNETA_DA_FILT_OTH_MCAST + tbl_offset); 2529c5aff182SThomas Petazzoni 2530c5aff182SThomas Petazzoni if (queue == -1) { 2531c5aff182SThomas Petazzoni /* Clear accepts frame bit at specified Other DA table entry */ 2532c5aff182SThomas Petazzoni omc_table_reg &= ~(0xff << (8 * reg_offset)); 2533c5aff182SThomas Petazzoni } else { 2534c5aff182SThomas Petazzoni omc_table_reg &= ~(0xff << (8 * reg_offset)); 2535c5aff182SThomas Petazzoni omc_table_reg |= ((0x01 | (queue << 1)) << (8 * reg_offset)); 2536c5aff182SThomas Petazzoni } 2537c5aff182SThomas Petazzoni 2538c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_DA_FILT_OTH_MCAST + tbl_offset, omc_table_reg); 2539c5aff182SThomas Petazzoni } 2540c5aff182SThomas Petazzoni 2541c5aff182SThomas Petazzoni /* The network device supports multicast using two tables: 2542c5aff182SThomas Petazzoni * 1) Special Multicast Table for MAC addresses of the form 2543c5aff182SThomas Petazzoni * 0x01-00-5E-00-00-XX (where XX is between 0x00 and 0xFF). 2544c5aff182SThomas Petazzoni * The MAC DA[7:0] bits are used as a pointer to the Special Multicast 2545c5aff182SThomas Petazzoni * Table entries in the DA-Filter table. 2546c5aff182SThomas Petazzoni * 2) Other Multicast Table for multicast of another type. A CRC-8 value 2547c5aff182SThomas Petazzoni * is used as an index to the Other Multicast Table entries in the 2548c5aff182SThomas Petazzoni * DA-Filter table. 2549c5aff182SThomas Petazzoni */ 2550c5aff182SThomas Petazzoni static int mvneta_mcast_addr_set(struct mvneta_port *pp, unsigned char *p_addr, 2551c5aff182SThomas Petazzoni int queue) 2552c5aff182SThomas Petazzoni { 2553c5aff182SThomas Petazzoni unsigned char crc_result = 0; 2554c5aff182SThomas Petazzoni 2555c5aff182SThomas Petazzoni if (memcmp(p_addr, "\x01\x00\x5e\x00\x00", 5) == 0) { 2556c5aff182SThomas Petazzoni mvneta_set_special_mcast_addr(pp, p_addr[5], queue); 2557c5aff182SThomas Petazzoni return 0; 2558c5aff182SThomas Petazzoni } 2559c5aff182SThomas Petazzoni 2560c5aff182SThomas Petazzoni crc_result = mvneta_addr_crc(p_addr); 2561c5aff182SThomas Petazzoni if (queue == -1) { 2562c5aff182SThomas Petazzoni if (pp->mcast_count[crc_result] == 0) { 2563c5aff182SThomas Petazzoni netdev_info(pp->dev, "No valid Mcast for crc8=0x%02x\n", 2564c5aff182SThomas Petazzoni crc_result); 2565c5aff182SThomas Petazzoni return -EINVAL; 2566c5aff182SThomas Petazzoni } 2567c5aff182SThomas Petazzoni 2568c5aff182SThomas Petazzoni pp->mcast_count[crc_result]--; 2569c5aff182SThomas Petazzoni if (pp->mcast_count[crc_result] != 0) { 2570c5aff182SThomas Petazzoni netdev_info(pp->dev, 2571c5aff182SThomas Petazzoni "After delete there are %d valid Mcast for crc8=0x%02x\n", 2572c5aff182SThomas Petazzoni pp->mcast_count[crc_result], crc_result); 2573c5aff182SThomas Petazzoni return -EINVAL; 2574c5aff182SThomas Petazzoni } 2575c5aff182SThomas Petazzoni } else 2576c5aff182SThomas Petazzoni pp->mcast_count[crc_result]++; 2577c5aff182SThomas Petazzoni 2578c5aff182SThomas Petazzoni mvneta_set_other_mcast_addr(pp, crc_result, queue); 2579c5aff182SThomas Petazzoni 2580c5aff182SThomas Petazzoni return 0; 2581c5aff182SThomas Petazzoni } 2582c5aff182SThomas Petazzoni 2583c5aff182SThomas Petazzoni /* Configure Fitering mode of Ethernet port */ 2584c5aff182SThomas Petazzoni static void mvneta_rx_unicast_promisc_set(struct mvneta_port *pp, 2585c5aff182SThomas Petazzoni int is_promisc) 2586c5aff182SThomas Petazzoni { 2587c5aff182SThomas Petazzoni u32 port_cfg_reg, val; 2588c5aff182SThomas Petazzoni 2589c5aff182SThomas Petazzoni port_cfg_reg = mvreg_read(pp, MVNETA_PORT_CONFIG); 2590c5aff182SThomas Petazzoni 2591c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_TYPE_PRIO); 2592c5aff182SThomas Petazzoni 2593c5aff182SThomas Petazzoni /* Set / Clear UPM bit in port configuration register */ 2594c5aff182SThomas Petazzoni if (is_promisc) { 2595c5aff182SThomas Petazzoni /* Accept all Unicast addresses */ 2596c5aff182SThomas Petazzoni port_cfg_reg |= MVNETA_UNI_PROMISC_MODE; 2597c5aff182SThomas Petazzoni val |= MVNETA_FORCE_UNI; 2598c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_MAC_ADDR_LOW, 0xffff); 2599c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_MAC_ADDR_HIGH, 0xffffffff); 2600c5aff182SThomas Petazzoni } else { 2601c5aff182SThomas Petazzoni /* Reject all Unicast addresses */ 2602c5aff182SThomas Petazzoni port_cfg_reg &= ~MVNETA_UNI_PROMISC_MODE; 2603c5aff182SThomas Petazzoni val &= ~MVNETA_FORCE_UNI; 2604c5aff182SThomas Petazzoni } 2605c5aff182SThomas Petazzoni 2606c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_PORT_CONFIG, port_cfg_reg); 2607c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_TYPE_PRIO, val); 2608c5aff182SThomas Petazzoni } 2609c5aff182SThomas Petazzoni 2610c5aff182SThomas Petazzoni /* register unicast and multicast addresses */ 2611c5aff182SThomas Petazzoni static void mvneta_set_rx_mode(struct net_device *dev) 2612c5aff182SThomas Petazzoni { 2613c5aff182SThomas Petazzoni struct mvneta_port *pp = netdev_priv(dev); 2614c5aff182SThomas Petazzoni struct netdev_hw_addr *ha; 2615c5aff182SThomas Petazzoni 2616c5aff182SThomas Petazzoni if (dev->flags & IFF_PROMISC) { 2617c5aff182SThomas Petazzoni /* Accept all: Multicast + Unicast */ 2618c5aff182SThomas Petazzoni mvneta_rx_unicast_promisc_set(pp, 1); 261990b74c01SGregory CLEMENT mvneta_set_ucast_table(pp, pp->rxq_def); 262090b74c01SGregory CLEMENT mvneta_set_special_mcast_table(pp, pp->rxq_def); 262190b74c01SGregory CLEMENT mvneta_set_other_mcast_table(pp, pp->rxq_def); 2622c5aff182SThomas Petazzoni } else { 2623c5aff182SThomas Petazzoni /* Accept single Unicast */ 2624c5aff182SThomas Petazzoni mvneta_rx_unicast_promisc_set(pp, 0); 2625c5aff182SThomas Petazzoni mvneta_set_ucast_table(pp, -1); 262690b74c01SGregory CLEMENT mvneta_mac_addr_set(pp, dev->dev_addr, pp->rxq_def); 2627c5aff182SThomas Petazzoni 2628c5aff182SThomas Petazzoni if (dev->flags & IFF_ALLMULTI) { 2629c5aff182SThomas Petazzoni /* Accept all multicast */ 263090b74c01SGregory CLEMENT mvneta_set_special_mcast_table(pp, pp->rxq_def); 263190b74c01SGregory CLEMENT mvneta_set_other_mcast_table(pp, pp->rxq_def); 2632c5aff182SThomas Petazzoni } else { 2633c5aff182SThomas Petazzoni /* Accept only initialized multicast */ 2634c5aff182SThomas Petazzoni mvneta_set_special_mcast_table(pp, -1); 2635c5aff182SThomas Petazzoni mvneta_set_other_mcast_table(pp, -1); 2636c5aff182SThomas Petazzoni 2637c5aff182SThomas Petazzoni if (!netdev_mc_empty(dev)) { 2638c5aff182SThomas Petazzoni netdev_for_each_mc_addr(ha, dev) { 2639c5aff182SThomas Petazzoni mvneta_mcast_addr_set(pp, ha->addr, 264090b74c01SGregory CLEMENT pp->rxq_def); 2641c5aff182SThomas Petazzoni } 2642c5aff182SThomas Petazzoni } 2643c5aff182SThomas Petazzoni } 2644c5aff182SThomas Petazzoni } 2645c5aff182SThomas Petazzoni } 2646c5aff182SThomas Petazzoni 2647c5aff182SThomas Petazzoni /* Interrupt handling - the callback for request_irq() */ 2648c5aff182SThomas Petazzoni static irqreturn_t mvneta_isr(int irq, void *dev_id) 2649c5aff182SThomas Petazzoni { 26502636ac3cSMarcin Wojtas struct mvneta_port *pp = (struct mvneta_port *)dev_id; 26512636ac3cSMarcin Wojtas 26522636ac3cSMarcin Wojtas mvreg_write(pp, MVNETA_INTR_NEW_MASK, 0); 26532636ac3cSMarcin Wojtas napi_schedule(&pp->napi); 26542636ac3cSMarcin Wojtas 26552636ac3cSMarcin Wojtas return IRQ_HANDLED; 26562636ac3cSMarcin Wojtas } 26572636ac3cSMarcin Wojtas 26582636ac3cSMarcin Wojtas /* Interrupt handling - the callback for request_percpu_irq() */ 26592636ac3cSMarcin Wojtas static irqreturn_t mvneta_percpu_isr(int irq, void *dev_id) 26602636ac3cSMarcin Wojtas { 266112bb03b4SMaxime Ripard struct mvneta_pcpu_port *port = (struct mvneta_pcpu_port *)dev_id; 2662c5aff182SThomas Petazzoni 266312bb03b4SMaxime Ripard disable_percpu_irq(port->pp->dev->irq); 266412bb03b4SMaxime Ripard napi_schedule(&port->napi); 2665c5aff182SThomas Petazzoni 2666c5aff182SThomas Petazzoni return IRQ_HANDLED; 2667c5aff182SThomas Petazzoni } 2668c5aff182SThomas Petazzoni 2669503f9aa9SRussell King static void mvneta_link_change(struct mvneta_port *pp) 2670898b2970SStas Sergeev { 2671898b2970SStas Sergeev u32 gmac_stat = mvreg_read(pp, MVNETA_GMAC_STATUS); 2672898b2970SStas Sergeev 2673503f9aa9SRussell King phylink_mac_change(pp->phylink, !!(gmac_stat & MVNETA_GMAC_LINK_UP)); 2674898b2970SStas Sergeev } 2675898b2970SStas Sergeev 2676c5aff182SThomas Petazzoni /* NAPI handler 2677c5aff182SThomas Petazzoni * Bits 0 - 7 of the causeRxTx register indicate that are transmitted 2678c5aff182SThomas Petazzoni * packets on the corresponding TXQ (Bit 0 is for TX queue 1). 2679c5aff182SThomas Petazzoni * Bits 8 -15 of the cause Rx Tx register indicate that are received 2680c5aff182SThomas Petazzoni * packets on the corresponding RXQ (Bit 8 is for RX queue 0). 2681c5aff182SThomas Petazzoni * Each CPU has its own causeRxTx register 2682c5aff182SThomas Petazzoni */ 2683c5aff182SThomas Petazzoni static int mvneta_poll(struct napi_struct *napi, int budget) 2684c5aff182SThomas Petazzoni { 2685c5aff182SThomas Petazzoni int rx_done = 0; 2686c5aff182SThomas Petazzoni u32 cause_rx_tx; 26872dcf75e2SGregory CLEMENT int rx_queue; 2688c5aff182SThomas Petazzoni struct mvneta_port *pp = netdev_priv(napi->dev); 268912bb03b4SMaxime Ripard struct mvneta_pcpu_port *port = this_cpu_ptr(pp->ports); 2690c5aff182SThomas Petazzoni 2691c5aff182SThomas Petazzoni if (!netif_running(pp->dev)) { 26922636ac3cSMarcin Wojtas napi_complete(napi); 2693c5aff182SThomas Petazzoni return rx_done; 2694c5aff182SThomas Petazzoni } 2695c5aff182SThomas Petazzoni 2696c5aff182SThomas Petazzoni /* Read cause register */ 2697898b2970SStas Sergeev cause_rx_tx = mvreg_read(pp, MVNETA_INTR_NEW_CAUSE); 2698898b2970SStas Sergeev if (cause_rx_tx & MVNETA_MISCINTR_INTR_MASK) { 2699898b2970SStas Sergeev u32 cause_misc = mvreg_read(pp, MVNETA_INTR_MISC_CAUSE); 2700898b2970SStas Sergeev 2701898b2970SStas Sergeev mvreg_write(pp, MVNETA_INTR_MISC_CAUSE, 0); 2702503f9aa9SRussell King 2703503f9aa9SRussell King if (cause_misc & (MVNETA_CAUSE_PHY_STATUS_CHANGE | 2704856b2cc5SRussell King MVNETA_CAUSE_LINK_CHANGE)) 2705503f9aa9SRussell King mvneta_link_change(pp); 2706898b2970SStas Sergeev } 270771f6d1b3Swilly tarreau 270871f6d1b3Swilly tarreau /* Release Tx descriptors */ 270971f6d1b3Swilly tarreau if (cause_rx_tx & MVNETA_TX_INTR_MASK_ALL) { 27100713a86aSArnaud Ebalard mvneta_tx_done_gbe(pp, (cause_rx_tx & MVNETA_TX_INTR_MASK_ALL)); 271171f6d1b3Swilly tarreau cause_rx_tx &= ~MVNETA_TX_INTR_MASK_ALL; 271271f6d1b3Swilly tarreau } 2713c5aff182SThomas Petazzoni 27146a20c175SThomas Petazzoni /* For the case where the last mvneta_poll did not process all 2715c5aff182SThomas Petazzoni * RX packets 2716c5aff182SThomas Petazzoni */ 27172dcf75e2SGregory CLEMENT rx_queue = fls(((cause_rx_tx >> 8) & 0xff)); 27182dcf75e2SGregory CLEMENT 27192636ac3cSMarcin Wojtas cause_rx_tx |= pp->neta_armada3700 ? pp->cause_rx_tx : 27202636ac3cSMarcin Wojtas port->cause_rx_tx; 27212dcf75e2SGregory CLEMENT 27222dcf75e2SGregory CLEMENT if (rx_queue) { 27232dcf75e2SGregory CLEMENT rx_queue = rx_queue - 1; 2724dc35a10fSMarcin Wojtas if (pp->bm_priv) 2725dc35a10fSMarcin Wojtas rx_done = mvneta_rx_hwbm(pp, budget, &pp->rxqs[rx_queue]); 2726dc35a10fSMarcin Wojtas else 2727dc35a10fSMarcin Wojtas rx_done = mvneta_rx_swbm(pp, budget, &pp->rxqs[rx_queue]); 27282dcf75e2SGregory CLEMENT } 27292dcf75e2SGregory CLEMENT 27306ad20165SEric Dumazet if (rx_done < budget) { 2731c5aff182SThomas Petazzoni cause_rx_tx = 0; 27326ad20165SEric Dumazet napi_complete_done(napi, rx_done); 27332636ac3cSMarcin Wojtas 27342636ac3cSMarcin Wojtas if (pp->neta_armada3700) { 27352636ac3cSMarcin Wojtas unsigned long flags; 27362636ac3cSMarcin Wojtas 27372636ac3cSMarcin Wojtas local_irq_save(flags); 27382636ac3cSMarcin Wojtas mvreg_write(pp, MVNETA_INTR_NEW_MASK, 27392636ac3cSMarcin Wojtas MVNETA_RX_INTR_MASK(rxq_number) | 27402636ac3cSMarcin Wojtas MVNETA_TX_INTR_MASK(txq_number) | 27412636ac3cSMarcin Wojtas MVNETA_MISCINTR_INTR_MASK); 27422636ac3cSMarcin Wojtas local_irq_restore(flags); 27432636ac3cSMarcin Wojtas } else { 274412bb03b4SMaxime Ripard enable_percpu_irq(pp->dev->irq, 0); 2745c5aff182SThomas Petazzoni } 27462636ac3cSMarcin Wojtas } 2747c5aff182SThomas Petazzoni 27482636ac3cSMarcin Wojtas if (pp->neta_armada3700) 27492636ac3cSMarcin Wojtas pp->cause_rx_tx = cause_rx_tx; 27502636ac3cSMarcin Wojtas else 275112bb03b4SMaxime Ripard port->cause_rx_tx = cause_rx_tx; 27522636ac3cSMarcin Wojtas 2753c5aff182SThomas Petazzoni return rx_done; 2754c5aff182SThomas Petazzoni } 2755c5aff182SThomas Petazzoni 2756c5aff182SThomas Petazzoni /* Handle rxq fill: allocates rxq skbs; called when initializing a port */ 2757c5aff182SThomas Petazzoni static int mvneta_rxq_fill(struct mvneta_port *pp, struct mvneta_rx_queue *rxq, 2758c5aff182SThomas Petazzoni int num) 2759c5aff182SThomas Petazzoni { 2760c5aff182SThomas Petazzoni int i; 2761c5aff182SThomas Petazzoni 2762c5aff182SThomas Petazzoni for (i = 0; i < num; i++) { 2763a1a65ab1Swilly tarreau memset(rxq->descs + i, 0, sizeof(struct mvneta_rx_desc)); 2764f88bee1cSGregory CLEMENT if (mvneta_rx_refill(pp, rxq->descs + i, rxq) != 0) { 2765a1a65ab1Swilly tarreau netdev_err(pp->dev, "%s:rxq %d, %d of %d buffs filled\n", 2766c5aff182SThomas Petazzoni __func__, rxq->id, i, num); 2767c5aff182SThomas Petazzoni break; 2768c5aff182SThomas Petazzoni } 2769c5aff182SThomas Petazzoni } 2770c5aff182SThomas Petazzoni 2771c5aff182SThomas Petazzoni /* Add this number of RX descriptors as non occupied (ready to 27726a20c175SThomas Petazzoni * get packets) 27736a20c175SThomas Petazzoni */ 2774c5aff182SThomas Petazzoni mvneta_rxq_non_occup_desc_add(pp, rxq, i); 2775c5aff182SThomas Petazzoni 2776c5aff182SThomas Petazzoni return i; 2777c5aff182SThomas Petazzoni } 2778c5aff182SThomas Petazzoni 2779c5aff182SThomas Petazzoni /* Free all packets pending transmit from all TXQs and reset TX port */ 2780c5aff182SThomas Petazzoni static void mvneta_tx_reset(struct mvneta_port *pp) 2781c5aff182SThomas Petazzoni { 2782c5aff182SThomas Petazzoni int queue; 2783c5aff182SThomas Petazzoni 27849672850bSEzequiel Garcia /* free the skb's in the tx ring */ 2785c5aff182SThomas Petazzoni for (queue = 0; queue < txq_number; queue++) 2786c5aff182SThomas Petazzoni mvneta_txq_done_force(pp, &pp->txqs[queue]); 2787c5aff182SThomas Petazzoni 2788c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_PORT_TX_RESET, MVNETA_PORT_TX_DMA_RESET); 2789c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_PORT_TX_RESET, 0); 2790c5aff182SThomas Petazzoni } 2791c5aff182SThomas Petazzoni 2792c5aff182SThomas Petazzoni static void mvneta_rx_reset(struct mvneta_port *pp) 2793c5aff182SThomas Petazzoni { 2794c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_PORT_RX_RESET, MVNETA_PORT_RX_DMA_RESET); 2795c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_PORT_RX_RESET, 0); 2796c5aff182SThomas Petazzoni } 2797c5aff182SThomas Petazzoni 2798c5aff182SThomas Petazzoni /* Rx/Tx queue initialization/cleanup methods */ 2799c5aff182SThomas Petazzoni 28004a188a63SJisheng Zhang static int mvneta_rxq_sw_init(struct mvneta_port *pp, 2801c5aff182SThomas Petazzoni struct mvneta_rx_queue *rxq) 2802c5aff182SThomas Petazzoni { 2803c5aff182SThomas Petazzoni rxq->size = pp->rx_ring_size; 2804c5aff182SThomas Petazzoni 2805c5aff182SThomas Petazzoni /* Allocate memory for RX descriptors */ 2806c5aff182SThomas Petazzoni rxq->descs = dma_alloc_coherent(pp->dev->dev.parent, 2807c5aff182SThomas Petazzoni rxq->size * MVNETA_DESC_ALIGNED_SIZE, 2808c5aff182SThomas Petazzoni &rxq->descs_phys, GFP_KERNEL); 2809f95936ccSMarkus Elfring if (!rxq->descs) 2810c5aff182SThomas Petazzoni return -ENOMEM; 2811c5aff182SThomas Petazzoni 2812c5aff182SThomas Petazzoni rxq->last_desc = rxq->size - 1; 2813c5aff182SThomas Petazzoni 28144a188a63SJisheng Zhang return 0; 28154a188a63SJisheng Zhang } 28164a188a63SJisheng Zhang 28174a188a63SJisheng Zhang static void mvneta_rxq_hw_init(struct mvneta_port *pp, 28184a188a63SJisheng Zhang struct mvneta_rx_queue *rxq) 28194a188a63SJisheng Zhang { 2820c5aff182SThomas Petazzoni /* Set Rx descriptors queue starting address */ 2821c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_RXQ_BASE_ADDR_REG(rxq->id), rxq->descs_phys); 2822c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_RXQ_SIZE_REG(rxq->id), rxq->size); 2823c5aff182SThomas Petazzoni 2824c5aff182SThomas Petazzoni /* Set Offset */ 28258d5047cfSMarcin Wojtas mvneta_rxq_offset_set(pp, rxq, NET_SKB_PAD - pp->rx_offset_correction); 2826c5aff182SThomas Petazzoni 2827c5aff182SThomas Petazzoni /* Set coalescing pkts and time */ 2828c5aff182SThomas Petazzoni mvneta_rx_pkts_coal_set(pp, rxq, rxq->pkts_coal); 2829c5aff182SThomas Petazzoni mvneta_rx_time_coal_set(pp, rxq, rxq->time_coal); 2830c5aff182SThomas Petazzoni 2831dc35a10fSMarcin Wojtas if (!pp->bm_priv) { 2832c5aff182SThomas Petazzoni /* Fill RXQ with buffers from RX pool */ 2833dc35a10fSMarcin Wojtas mvneta_rxq_buf_size_set(pp, rxq, 2834dc35a10fSMarcin Wojtas MVNETA_RX_BUF_SIZE(pp->pkt_size)); 2835c5aff182SThomas Petazzoni mvneta_rxq_bm_disable(pp, rxq); 2836e9f64999SGregory CLEMENT mvneta_rxq_fill(pp, rxq, rxq->size); 2837dc35a10fSMarcin Wojtas } else { 2838dc35a10fSMarcin Wojtas mvneta_rxq_bm_enable(pp, rxq); 2839dc35a10fSMarcin Wojtas mvneta_rxq_long_pool_set(pp, rxq); 2840dc35a10fSMarcin Wojtas mvneta_rxq_short_pool_set(pp, rxq); 2841e9f64999SGregory CLEMENT mvneta_rxq_non_occup_desc_add(pp, rxq, rxq->size); 2842dc35a10fSMarcin Wojtas } 28434a188a63SJisheng Zhang } 28444a188a63SJisheng Zhang 28454a188a63SJisheng Zhang /* Create a specified RX queue */ 28464a188a63SJisheng Zhang static int mvneta_rxq_init(struct mvneta_port *pp, 28474a188a63SJisheng Zhang struct mvneta_rx_queue *rxq) 28484a188a63SJisheng Zhang 28494a188a63SJisheng Zhang { 28504a188a63SJisheng Zhang int ret; 28514a188a63SJisheng Zhang 28524a188a63SJisheng Zhang ret = mvneta_rxq_sw_init(pp, rxq); 28534a188a63SJisheng Zhang if (ret < 0) 28544a188a63SJisheng Zhang return ret; 28554a188a63SJisheng Zhang 28564a188a63SJisheng Zhang mvneta_rxq_hw_init(pp, rxq); 2857dc35a10fSMarcin Wojtas 2858c5aff182SThomas Petazzoni return 0; 2859c5aff182SThomas Petazzoni } 2860c5aff182SThomas Petazzoni 2861c5aff182SThomas Petazzoni /* Cleanup Rx queue */ 2862c5aff182SThomas Petazzoni static void mvneta_rxq_deinit(struct mvneta_port *pp, 2863c5aff182SThomas Petazzoni struct mvneta_rx_queue *rxq) 2864c5aff182SThomas Petazzoni { 2865c5aff182SThomas Petazzoni mvneta_rxq_drop_pkts(pp, rxq); 2866c5aff182SThomas Petazzoni 2867c5aff182SThomas Petazzoni if (rxq->descs) 2868c5aff182SThomas Petazzoni dma_free_coherent(pp->dev->dev.parent, 2869c5aff182SThomas Petazzoni rxq->size * MVNETA_DESC_ALIGNED_SIZE, 2870c5aff182SThomas Petazzoni rxq->descs, 2871c5aff182SThomas Petazzoni rxq->descs_phys); 2872c5aff182SThomas Petazzoni 2873c5aff182SThomas Petazzoni rxq->descs = NULL; 2874c5aff182SThomas Petazzoni rxq->last_desc = 0; 2875c5aff182SThomas Petazzoni rxq->next_desc_to_proc = 0; 2876c5aff182SThomas Petazzoni rxq->descs_phys = 0; 2877c5aff182SThomas Petazzoni } 2878c5aff182SThomas Petazzoni 28794a188a63SJisheng Zhang static int mvneta_txq_sw_init(struct mvneta_port *pp, 2880c5aff182SThomas Petazzoni struct mvneta_tx_queue *txq) 2881c5aff182SThomas Petazzoni { 288250bf8cb6SGregory CLEMENT int cpu; 288350bf8cb6SGregory CLEMENT 2884c5aff182SThomas Petazzoni txq->size = pp->tx_ring_size; 2885c5aff182SThomas Petazzoni 28868eef5f97SEzequiel Garcia /* A queue must always have room for at least one skb. 28878eef5f97SEzequiel Garcia * Therefore, stop the queue when the free entries reaches 28888eef5f97SEzequiel Garcia * the maximum number of descriptors per skb. 28898eef5f97SEzequiel Garcia */ 28908eef5f97SEzequiel Garcia txq->tx_stop_threshold = txq->size - MVNETA_MAX_SKB_DESCS; 28918eef5f97SEzequiel Garcia txq->tx_wake_threshold = txq->tx_stop_threshold / 2; 28928eef5f97SEzequiel Garcia 2893c5aff182SThomas Petazzoni /* Allocate memory for TX descriptors */ 2894c5aff182SThomas Petazzoni txq->descs = dma_alloc_coherent(pp->dev->dev.parent, 2895c5aff182SThomas Petazzoni txq->size * MVNETA_DESC_ALIGNED_SIZE, 2896c5aff182SThomas Petazzoni &txq->descs_phys, GFP_KERNEL); 2897f95936ccSMarkus Elfring if (!txq->descs) 2898c5aff182SThomas Petazzoni return -ENOMEM; 2899c5aff182SThomas Petazzoni 2900c5aff182SThomas Petazzoni txq->last_desc = txq->size - 1; 2901c5aff182SThomas Petazzoni 2902d441b688SMarkus Elfring txq->tx_skb = kmalloc_array(txq->size, sizeof(*txq->tx_skb), 2903d441b688SMarkus Elfring GFP_KERNEL); 2904f95936ccSMarkus Elfring if (!txq->tx_skb) { 2905c5aff182SThomas Petazzoni dma_free_coherent(pp->dev->dev.parent, 2906c5aff182SThomas Petazzoni txq->size * MVNETA_DESC_ALIGNED_SIZE, 2907c5aff182SThomas Petazzoni txq->descs, txq->descs_phys); 2908c5aff182SThomas Petazzoni return -ENOMEM; 2909c5aff182SThomas Petazzoni } 29102adb719dSEzequiel Garcia 29112adb719dSEzequiel Garcia /* Allocate DMA buffers for TSO MAC/IP/TCP headers */ 29122adb719dSEzequiel Garcia txq->tso_hdrs = dma_alloc_coherent(pp->dev->dev.parent, 29132adb719dSEzequiel Garcia txq->size * TSO_HEADER_SIZE, 29142adb719dSEzequiel Garcia &txq->tso_hdrs_phys, GFP_KERNEL); 2915f95936ccSMarkus Elfring if (!txq->tso_hdrs) { 29162adb719dSEzequiel Garcia kfree(txq->tx_skb); 29172adb719dSEzequiel Garcia dma_free_coherent(pp->dev->dev.parent, 29182adb719dSEzequiel Garcia txq->size * MVNETA_DESC_ALIGNED_SIZE, 29192adb719dSEzequiel Garcia txq->descs, txq->descs_phys); 29202adb719dSEzequiel Garcia return -ENOMEM; 29212adb719dSEzequiel Garcia } 2922c5aff182SThomas Petazzoni 292350bf8cb6SGregory CLEMENT /* Setup XPS mapping */ 292450bf8cb6SGregory CLEMENT if (txq_number > 1) 292550bf8cb6SGregory CLEMENT cpu = txq->id % num_present_cpus(); 292650bf8cb6SGregory CLEMENT else 292750bf8cb6SGregory CLEMENT cpu = pp->rxq_def % num_present_cpus(); 292850bf8cb6SGregory CLEMENT cpumask_set_cpu(cpu, &txq->affinity_mask); 292950bf8cb6SGregory CLEMENT netif_set_xps_queue(pp->dev, &txq->affinity_mask, txq->id); 293050bf8cb6SGregory CLEMENT 2931c5aff182SThomas Petazzoni return 0; 2932c5aff182SThomas Petazzoni } 2933c5aff182SThomas Petazzoni 29344a188a63SJisheng Zhang static void mvneta_txq_hw_init(struct mvneta_port *pp, 29354a188a63SJisheng Zhang struct mvneta_tx_queue *txq) 29364a188a63SJisheng Zhang { 29374a188a63SJisheng Zhang /* Set maximum bandwidth for enabled TXQs */ 29384a188a63SJisheng Zhang mvreg_write(pp, MVETH_TXQ_TOKEN_CFG_REG(txq->id), 0x03ffffff); 29394a188a63SJisheng Zhang mvreg_write(pp, MVETH_TXQ_TOKEN_COUNT_REG(txq->id), 0x3fffffff); 29404a188a63SJisheng Zhang 29414a188a63SJisheng Zhang /* Set Tx descriptors queue starting address */ 29424a188a63SJisheng Zhang mvreg_write(pp, MVNETA_TXQ_BASE_ADDR_REG(txq->id), txq->descs_phys); 29434a188a63SJisheng Zhang mvreg_write(pp, MVNETA_TXQ_SIZE_REG(txq->id), txq->size); 29444a188a63SJisheng Zhang 29454a188a63SJisheng Zhang mvneta_tx_done_pkts_coal_set(pp, txq, txq->done_pkts_coal); 29464a188a63SJisheng Zhang } 29474a188a63SJisheng Zhang 29484a188a63SJisheng Zhang /* Create and initialize a tx queue */ 29494a188a63SJisheng Zhang static int mvneta_txq_init(struct mvneta_port *pp, 29504a188a63SJisheng Zhang struct mvneta_tx_queue *txq) 29514a188a63SJisheng Zhang { 29524a188a63SJisheng Zhang int ret; 29534a188a63SJisheng Zhang 29544a188a63SJisheng Zhang ret = mvneta_txq_sw_init(pp, txq); 29554a188a63SJisheng Zhang if (ret < 0) 29564a188a63SJisheng Zhang return ret; 29574a188a63SJisheng Zhang 29584a188a63SJisheng Zhang mvneta_txq_hw_init(pp, txq); 29594a188a63SJisheng Zhang 29604a188a63SJisheng Zhang return 0; 29614a188a63SJisheng Zhang } 29624a188a63SJisheng Zhang 2963c5aff182SThomas Petazzoni /* Free allocated resources when mvneta_txq_init() fails to allocate memory*/ 29644a188a63SJisheng Zhang static void mvneta_txq_sw_deinit(struct mvneta_port *pp, 2965c5aff182SThomas Petazzoni struct mvneta_tx_queue *txq) 2966c5aff182SThomas Petazzoni { 2967a29b6235SMarcin Wojtas struct netdev_queue *nq = netdev_get_tx_queue(pp->dev, txq->id); 2968a29b6235SMarcin Wojtas 2969c5aff182SThomas Petazzoni kfree(txq->tx_skb); 2970c5aff182SThomas Petazzoni 29712adb719dSEzequiel Garcia if (txq->tso_hdrs) 29722adb719dSEzequiel Garcia dma_free_coherent(pp->dev->dev.parent, 29732adb719dSEzequiel Garcia txq->size * TSO_HEADER_SIZE, 29742adb719dSEzequiel Garcia txq->tso_hdrs, txq->tso_hdrs_phys); 2975c5aff182SThomas Petazzoni if (txq->descs) 2976c5aff182SThomas Petazzoni dma_free_coherent(pp->dev->dev.parent, 2977c5aff182SThomas Petazzoni txq->size * MVNETA_DESC_ALIGNED_SIZE, 2978c5aff182SThomas Petazzoni txq->descs, txq->descs_phys); 2979c5aff182SThomas Petazzoni 2980a29b6235SMarcin Wojtas netdev_tx_reset_queue(nq); 2981a29b6235SMarcin Wojtas 2982c5aff182SThomas Petazzoni txq->descs = NULL; 2983c5aff182SThomas Petazzoni txq->last_desc = 0; 2984c5aff182SThomas Petazzoni txq->next_desc_to_proc = 0; 2985c5aff182SThomas Petazzoni txq->descs_phys = 0; 29864a188a63SJisheng Zhang } 2987c5aff182SThomas Petazzoni 29884a188a63SJisheng Zhang static void mvneta_txq_hw_deinit(struct mvneta_port *pp, 29894a188a63SJisheng Zhang struct mvneta_tx_queue *txq) 29904a188a63SJisheng Zhang { 2991c5aff182SThomas Petazzoni /* Set minimum bandwidth for disabled TXQs */ 2992c5aff182SThomas Petazzoni mvreg_write(pp, MVETH_TXQ_TOKEN_CFG_REG(txq->id), 0); 2993c5aff182SThomas Petazzoni mvreg_write(pp, MVETH_TXQ_TOKEN_COUNT_REG(txq->id), 0); 2994c5aff182SThomas Petazzoni 2995c5aff182SThomas Petazzoni /* Set Tx descriptors queue starting address and size */ 2996c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_TXQ_BASE_ADDR_REG(txq->id), 0); 2997c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_TXQ_SIZE_REG(txq->id), 0); 2998c5aff182SThomas Petazzoni } 2999c5aff182SThomas Petazzoni 30004a188a63SJisheng Zhang static void mvneta_txq_deinit(struct mvneta_port *pp, 30014a188a63SJisheng Zhang struct mvneta_tx_queue *txq) 30024a188a63SJisheng Zhang { 30034a188a63SJisheng Zhang mvneta_txq_sw_deinit(pp, txq); 30044a188a63SJisheng Zhang mvneta_txq_hw_deinit(pp, txq); 30054a188a63SJisheng Zhang } 30064a188a63SJisheng Zhang 3007c5aff182SThomas Petazzoni /* Cleanup all Tx queues */ 3008c5aff182SThomas Petazzoni static void mvneta_cleanup_txqs(struct mvneta_port *pp) 3009c5aff182SThomas Petazzoni { 3010c5aff182SThomas Petazzoni int queue; 3011c5aff182SThomas Petazzoni 3012c5aff182SThomas Petazzoni for (queue = 0; queue < txq_number; queue++) 3013c5aff182SThomas Petazzoni mvneta_txq_deinit(pp, &pp->txqs[queue]); 3014c5aff182SThomas Petazzoni } 3015c5aff182SThomas Petazzoni 3016c5aff182SThomas Petazzoni /* Cleanup all Rx queues */ 3017c5aff182SThomas Petazzoni static void mvneta_cleanup_rxqs(struct mvneta_port *pp) 3018c5aff182SThomas Petazzoni { 30192dcf75e2SGregory CLEMENT int queue; 30202dcf75e2SGregory CLEMENT 3021ca5902a6SYelena Krivosheev for (queue = 0; queue < rxq_number; queue++) 30222dcf75e2SGregory CLEMENT mvneta_rxq_deinit(pp, &pp->rxqs[queue]); 3023c5aff182SThomas Petazzoni } 3024c5aff182SThomas Petazzoni 3025c5aff182SThomas Petazzoni 3026c5aff182SThomas Petazzoni /* Init all Rx queues */ 3027c5aff182SThomas Petazzoni static int mvneta_setup_rxqs(struct mvneta_port *pp) 3028c5aff182SThomas Petazzoni { 30292dcf75e2SGregory CLEMENT int queue; 30302dcf75e2SGregory CLEMENT 30312dcf75e2SGregory CLEMENT for (queue = 0; queue < rxq_number; queue++) { 30322dcf75e2SGregory CLEMENT int err = mvneta_rxq_init(pp, &pp->rxqs[queue]); 30332dcf75e2SGregory CLEMENT 3034c5aff182SThomas Petazzoni if (err) { 3035c5aff182SThomas Petazzoni netdev_err(pp->dev, "%s: can't create rxq=%d\n", 30362dcf75e2SGregory CLEMENT __func__, queue); 3037c5aff182SThomas Petazzoni mvneta_cleanup_rxqs(pp); 3038c5aff182SThomas Petazzoni return err; 3039c5aff182SThomas Petazzoni } 30402dcf75e2SGregory CLEMENT } 3041c5aff182SThomas Petazzoni 3042c5aff182SThomas Petazzoni return 0; 3043c5aff182SThomas Petazzoni } 3044c5aff182SThomas Petazzoni 3045c5aff182SThomas Petazzoni /* Init all tx queues */ 3046c5aff182SThomas Petazzoni static int mvneta_setup_txqs(struct mvneta_port *pp) 3047c5aff182SThomas Petazzoni { 3048c5aff182SThomas Petazzoni int queue; 3049c5aff182SThomas Petazzoni 3050c5aff182SThomas Petazzoni for (queue = 0; queue < txq_number; queue++) { 3051c5aff182SThomas Petazzoni int err = mvneta_txq_init(pp, &pp->txqs[queue]); 3052c5aff182SThomas Petazzoni if (err) { 3053c5aff182SThomas Petazzoni netdev_err(pp->dev, "%s: can't create txq=%d\n", 3054c5aff182SThomas Petazzoni __func__, queue); 3055c5aff182SThomas Petazzoni mvneta_cleanup_txqs(pp); 3056c5aff182SThomas Petazzoni return err; 3057c5aff182SThomas Petazzoni } 3058c5aff182SThomas Petazzoni } 3059c5aff182SThomas Petazzoni 3060c5aff182SThomas Petazzoni return 0; 3061c5aff182SThomas Petazzoni } 3062c5aff182SThomas Petazzoni 3063c5aff182SThomas Petazzoni static void mvneta_start_dev(struct mvneta_port *pp) 3064c5aff182SThomas Petazzoni { 30656b125d63SGregory CLEMENT int cpu; 306612bb03b4SMaxime Ripard 3067c5aff182SThomas Petazzoni mvneta_max_rx_size_set(pp, pp->pkt_size); 3068c5aff182SThomas Petazzoni mvneta_txq_max_tx_size_set(pp, pp->pkt_size); 3069c5aff182SThomas Petazzoni 3070c5aff182SThomas Petazzoni /* start the Rx/Tx activity */ 3071c5aff182SThomas Petazzoni mvneta_port_enable(pp); 3072c5aff182SThomas Petazzoni 30732636ac3cSMarcin Wojtas if (!pp->neta_armada3700) { 3074c5aff182SThomas Petazzoni /* Enable polling on the port */ 3075129219e4SGregory CLEMENT for_each_online_cpu(cpu) { 30762636ac3cSMarcin Wojtas struct mvneta_pcpu_port *port = 30772636ac3cSMarcin Wojtas per_cpu_ptr(pp->ports, cpu); 307812bb03b4SMaxime Ripard 307912bb03b4SMaxime Ripard napi_enable(&port->napi); 308012bb03b4SMaxime Ripard } 30812636ac3cSMarcin Wojtas } else { 30822636ac3cSMarcin Wojtas napi_enable(&pp->napi); 30832636ac3cSMarcin Wojtas } 3084c5aff182SThomas Petazzoni 30852dcf75e2SGregory CLEMENT /* Unmask interrupts. It has to be done from each CPU */ 30866b125d63SGregory CLEMENT on_each_cpu(mvneta_percpu_unmask_interrupt, pp, true); 30876b125d63SGregory CLEMENT 3088898b2970SStas Sergeev mvreg_write(pp, MVNETA_INTR_MISC_MASK, 3089898b2970SStas Sergeev MVNETA_CAUSE_PHY_STATUS_CHANGE | 3090856b2cc5SRussell King MVNETA_CAUSE_LINK_CHANGE); 3091c5aff182SThomas Petazzoni 3092503f9aa9SRussell King phylink_start(pp->phylink); 3093c5aff182SThomas Petazzoni netif_tx_start_all_queues(pp->dev); 3094c5aff182SThomas Petazzoni } 3095c5aff182SThomas Petazzoni 3096c5aff182SThomas Petazzoni static void mvneta_stop_dev(struct mvneta_port *pp) 3097c5aff182SThomas Petazzoni { 309812bb03b4SMaxime Ripard unsigned int cpu; 309912bb03b4SMaxime Ripard 3100503f9aa9SRussell King phylink_stop(pp->phylink); 3101c5aff182SThomas Petazzoni 31022636ac3cSMarcin Wojtas if (!pp->neta_armada3700) { 3103129219e4SGregory CLEMENT for_each_online_cpu(cpu) { 31042636ac3cSMarcin Wojtas struct mvneta_pcpu_port *port = 31052636ac3cSMarcin Wojtas per_cpu_ptr(pp->ports, cpu); 310612bb03b4SMaxime Ripard 310712bb03b4SMaxime Ripard napi_disable(&port->napi); 310812bb03b4SMaxime Ripard } 31092636ac3cSMarcin Wojtas } else { 31102636ac3cSMarcin Wojtas napi_disable(&pp->napi); 31112636ac3cSMarcin Wojtas } 3112c5aff182SThomas Petazzoni 3113c5aff182SThomas Petazzoni netif_carrier_off(pp->dev); 3114c5aff182SThomas Petazzoni 3115c5aff182SThomas Petazzoni mvneta_port_down(pp); 3116c5aff182SThomas Petazzoni netif_tx_stop_all_queues(pp->dev); 3117c5aff182SThomas Petazzoni 3118c5aff182SThomas Petazzoni /* Stop the port activity */ 3119c5aff182SThomas Petazzoni mvneta_port_disable(pp); 3120c5aff182SThomas Petazzoni 3121c5aff182SThomas Petazzoni /* Clear all ethernet port interrupts */ 3122db488c10SGregory CLEMENT on_each_cpu(mvneta_percpu_clear_intr_cause, pp, true); 3123c5aff182SThomas Petazzoni 3124c5aff182SThomas Petazzoni /* Mask all ethernet port interrupts */ 3125db488c10SGregory CLEMENT on_each_cpu(mvneta_percpu_mask_interrupt, pp, true); 3126c5aff182SThomas Petazzoni 3127c5aff182SThomas Petazzoni mvneta_tx_reset(pp); 3128c5aff182SThomas Petazzoni mvneta_rx_reset(pp); 3129c5aff182SThomas Petazzoni } 3130c5aff182SThomas Petazzoni 3131db5dd0dbSMarcin Wojtas static void mvneta_percpu_enable(void *arg) 3132db5dd0dbSMarcin Wojtas { 3133db5dd0dbSMarcin Wojtas struct mvneta_port *pp = arg; 3134db5dd0dbSMarcin Wojtas 3135db5dd0dbSMarcin Wojtas enable_percpu_irq(pp->dev->irq, IRQ_TYPE_NONE); 3136db5dd0dbSMarcin Wojtas } 3137db5dd0dbSMarcin Wojtas 3138db5dd0dbSMarcin Wojtas static void mvneta_percpu_disable(void *arg) 3139db5dd0dbSMarcin Wojtas { 3140db5dd0dbSMarcin Wojtas struct mvneta_port *pp = arg; 3141db5dd0dbSMarcin Wojtas 3142db5dd0dbSMarcin Wojtas disable_percpu_irq(pp->dev->irq); 3143db5dd0dbSMarcin Wojtas } 3144db5dd0dbSMarcin Wojtas 3145c5aff182SThomas Petazzoni /* Change the device mtu */ 3146c5aff182SThomas Petazzoni static int mvneta_change_mtu(struct net_device *dev, int mtu) 3147c5aff182SThomas Petazzoni { 3148c5aff182SThomas Petazzoni struct mvneta_port *pp = netdev_priv(dev); 3149c5aff182SThomas Petazzoni int ret; 3150c5aff182SThomas Petazzoni 31515777987eSJarod Wilson if (!IS_ALIGNED(MVNETA_RX_PKT_SIZE(mtu), 8)) { 31525777987eSJarod Wilson netdev_info(dev, "Illegal MTU value %d, rounding to %d\n", 31535777987eSJarod Wilson mtu, ALIGN(MVNETA_RX_PKT_SIZE(mtu), 8)); 31545777987eSJarod Wilson mtu = ALIGN(MVNETA_RX_PKT_SIZE(mtu), 8); 31555777987eSJarod Wilson } 3156c5aff182SThomas Petazzoni 3157c5aff182SThomas Petazzoni dev->mtu = mtu; 3158c5aff182SThomas Petazzoni 3159b65657fcSSimon Guinot if (!netif_running(dev)) { 3160dc35a10fSMarcin Wojtas if (pp->bm_priv) 3161dc35a10fSMarcin Wojtas mvneta_bm_update_mtu(pp, mtu); 3162dc35a10fSMarcin Wojtas 3163b65657fcSSimon Guinot netdev_update_features(dev); 3164c5aff182SThomas Petazzoni return 0; 3165b65657fcSSimon Guinot } 3166c5aff182SThomas Petazzoni 31676a20c175SThomas Petazzoni /* The interface is running, so we have to force a 3168a92dbd96SEzequiel Garcia * reallocation of the queues 3169c5aff182SThomas Petazzoni */ 3170c5aff182SThomas Petazzoni mvneta_stop_dev(pp); 3171db5dd0dbSMarcin Wojtas on_each_cpu(mvneta_percpu_disable, pp, true); 3172c5aff182SThomas Petazzoni 3173c5aff182SThomas Petazzoni mvneta_cleanup_txqs(pp); 3174c5aff182SThomas Petazzoni mvneta_cleanup_rxqs(pp); 3175c5aff182SThomas Petazzoni 3176dc35a10fSMarcin Wojtas if (pp->bm_priv) 3177dc35a10fSMarcin Wojtas mvneta_bm_update_mtu(pp, mtu); 3178dc35a10fSMarcin Wojtas 3179a92dbd96SEzequiel Garcia pp->pkt_size = MVNETA_RX_PKT_SIZE(dev->mtu); 31808ec2cd48Swilly tarreau pp->frag_size = SKB_DATA_ALIGN(MVNETA_RX_BUF_SIZE(pp->pkt_size)) + 31818ec2cd48Swilly tarreau SKB_DATA_ALIGN(sizeof(struct skb_shared_info)); 3182c5aff182SThomas Petazzoni 3183c5aff182SThomas Petazzoni ret = mvneta_setup_rxqs(pp); 3184c5aff182SThomas Petazzoni if (ret) { 3185a92dbd96SEzequiel Garcia netdev_err(dev, "unable to setup rxqs after MTU change\n"); 3186c5aff182SThomas Petazzoni return ret; 3187c5aff182SThomas Petazzoni } 3188c5aff182SThomas Petazzoni 3189a92dbd96SEzequiel Garcia ret = mvneta_setup_txqs(pp); 3190a92dbd96SEzequiel Garcia if (ret) { 3191a92dbd96SEzequiel Garcia netdev_err(dev, "unable to setup txqs after MTU change\n"); 3192a92dbd96SEzequiel Garcia return ret; 3193a92dbd96SEzequiel Garcia } 3194c5aff182SThomas Petazzoni 3195db5dd0dbSMarcin Wojtas on_each_cpu(mvneta_percpu_enable, pp, true); 3196c5aff182SThomas Petazzoni mvneta_start_dev(pp); 3197c5aff182SThomas Petazzoni mvneta_port_up(pp); 3198c5aff182SThomas Petazzoni 3199b65657fcSSimon Guinot netdev_update_features(dev); 3200b65657fcSSimon Guinot 3201c5aff182SThomas Petazzoni return 0; 3202c5aff182SThomas Petazzoni } 3203c5aff182SThomas Petazzoni 3204b65657fcSSimon Guinot static netdev_features_t mvneta_fix_features(struct net_device *dev, 3205b65657fcSSimon Guinot netdev_features_t features) 3206b65657fcSSimon Guinot { 3207b65657fcSSimon Guinot struct mvneta_port *pp = netdev_priv(dev); 3208b65657fcSSimon Guinot 3209b65657fcSSimon Guinot if (pp->tx_csum_limit && dev->mtu > pp->tx_csum_limit) { 3210b65657fcSSimon Guinot features &= ~(NETIF_F_IP_CSUM | NETIF_F_TSO); 3211b65657fcSSimon Guinot netdev_info(dev, 3212b65657fcSSimon Guinot "Disable IP checksum for MTU greater than %dB\n", 3213b65657fcSSimon Guinot pp->tx_csum_limit); 3214b65657fcSSimon Guinot } 3215b65657fcSSimon Guinot 3216b65657fcSSimon Guinot return features; 3217b65657fcSSimon Guinot } 3218b65657fcSSimon Guinot 32198cc3e439SThomas Petazzoni /* Get mac address */ 32208cc3e439SThomas Petazzoni static void mvneta_get_mac_addr(struct mvneta_port *pp, unsigned char *addr) 32218cc3e439SThomas Petazzoni { 32228cc3e439SThomas Petazzoni u32 mac_addr_l, mac_addr_h; 32238cc3e439SThomas Petazzoni 32248cc3e439SThomas Petazzoni mac_addr_l = mvreg_read(pp, MVNETA_MAC_ADDR_LOW); 32258cc3e439SThomas Petazzoni mac_addr_h = mvreg_read(pp, MVNETA_MAC_ADDR_HIGH); 32268cc3e439SThomas Petazzoni addr[0] = (mac_addr_h >> 24) & 0xFF; 32278cc3e439SThomas Petazzoni addr[1] = (mac_addr_h >> 16) & 0xFF; 32288cc3e439SThomas Petazzoni addr[2] = (mac_addr_h >> 8) & 0xFF; 32298cc3e439SThomas Petazzoni addr[3] = mac_addr_h & 0xFF; 32308cc3e439SThomas Petazzoni addr[4] = (mac_addr_l >> 8) & 0xFF; 32318cc3e439SThomas Petazzoni addr[5] = mac_addr_l & 0xFF; 32328cc3e439SThomas Petazzoni } 32338cc3e439SThomas Petazzoni 3234c5aff182SThomas Petazzoni /* Handle setting mac address */ 3235c5aff182SThomas Petazzoni static int mvneta_set_mac_addr(struct net_device *dev, void *addr) 3236c5aff182SThomas Petazzoni { 3237c5aff182SThomas Petazzoni struct mvneta_port *pp = netdev_priv(dev); 3238e68de360SEzequiel Garcia struct sockaddr *sockaddr = addr; 3239e68de360SEzequiel Garcia int ret; 3240c5aff182SThomas Petazzoni 3241e68de360SEzequiel Garcia ret = eth_prepare_mac_addr_change(dev, addr); 3242e68de360SEzequiel Garcia if (ret < 0) 3243e68de360SEzequiel Garcia return ret; 3244c5aff182SThomas Petazzoni /* Remove previous address table entry */ 3245c5aff182SThomas Petazzoni mvneta_mac_addr_set(pp, dev->dev_addr, -1); 3246c5aff182SThomas Petazzoni 3247c5aff182SThomas Petazzoni /* Set new addr in hw */ 324890b74c01SGregory CLEMENT mvneta_mac_addr_set(pp, sockaddr->sa_data, pp->rxq_def); 3249c5aff182SThomas Petazzoni 3250e68de360SEzequiel Garcia eth_commit_mac_addr_change(dev, addr); 3251c5aff182SThomas Petazzoni return 0; 3252c5aff182SThomas Petazzoni } 3253c5aff182SThomas Petazzoni 3254503f9aa9SRussell King static void mvneta_validate(struct net_device *ndev, unsigned long *supported, 3255503f9aa9SRussell King struct phylink_link_state *state) 3256503f9aa9SRussell King { 3257503f9aa9SRussell King __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, }; 3258503f9aa9SRussell King 325922f4bf8aSRussell King /* We only support QSGMII, SGMII, 802.3z and RGMII modes */ 3260503f9aa9SRussell King if (state->interface != PHY_INTERFACE_MODE_NA && 3261503f9aa9SRussell King state->interface != PHY_INTERFACE_MODE_QSGMII && 3262503f9aa9SRussell King state->interface != PHY_INTERFACE_MODE_SGMII && 326322f4bf8aSRussell King !phy_interface_mode_is_8023z(state->interface) && 3264503f9aa9SRussell King !phy_interface_mode_is_rgmii(state->interface)) { 3265503f9aa9SRussell King bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS); 3266503f9aa9SRussell King return; 3267503f9aa9SRussell King } 3268503f9aa9SRussell King 3269503f9aa9SRussell King /* Allow all the expected bits */ 3270503f9aa9SRussell King phylink_set(mask, Autoneg); 3271503f9aa9SRussell King phylink_set_port_modes(mask); 3272503f9aa9SRussell King 32734932a918SRussell King /* Asymmetric pause is unsupported */ 32744932a918SRussell King phylink_set(mask, Pause); 3275503f9aa9SRussell King /* Half-duplex at speeds higher than 100Mbit is unsupported */ 3276503f9aa9SRussell King phylink_set(mask, 1000baseT_Full); 3277503f9aa9SRussell King phylink_set(mask, 1000baseX_Full); 327822f4bf8aSRussell King 327922f4bf8aSRussell King if (!phy_interface_mode_is_8023z(state->interface)) { 328022f4bf8aSRussell King /* 10M and 100M are only supported in non-802.3z mode */ 3281503f9aa9SRussell King phylink_set(mask, 10baseT_Half); 3282503f9aa9SRussell King phylink_set(mask, 10baseT_Full); 3283503f9aa9SRussell King phylink_set(mask, 100baseT_Half); 3284503f9aa9SRussell King phylink_set(mask, 100baseT_Full); 328522f4bf8aSRussell King } 3286503f9aa9SRussell King 3287503f9aa9SRussell King bitmap_and(supported, supported, mask, 3288503f9aa9SRussell King __ETHTOOL_LINK_MODE_MASK_NBITS); 3289503f9aa9SRussell King bitmap_and(state->advertising, state->advertising, mask, 3290503f9aa9SRussell King __ETHTOOL_LINK_MODE_MASK_NBITS); 3291503f9aa9SRussell King } 3292503f9aa9SRussell King 3293503f9aa9SRussell King static int mvneta_mac_link_state(struct net_device *ndev, 3294503f9aa9SRussell King struct phylink_link_state *state) 3295c5aff182SThomas Petazzoni { 3296c5aff182SThomas Petazzoni struct mvneta_port *pp = netdev_priv(ndev); 3297503f9aa9SRussell King u32 gmac_stat; 3298c5aff182SThomas Petazzoni 3299503f9aa9SRussell King gmac_stat = mvreg_read(pp, MVNETA_GMAC_STATUS); 3300503f9aa9SRussell King 3301503f9aa9SRussell King if (gmac_stat & MVNETA_GMAC_SPEED_1000) 3302503f9aa9SRussell King state->speed = SPEED_1000; 3303503f9aa9SRussell King else if (gmac_stat & MVNETA_GMAC_SPEED_100) 3304503f9aa9SRussell King state->speed = SPEED_100; 3305503f9aa9SRussell King else 3306503f9aa9SRussell King state->speed = SPEED_10; 3307503f9aa9SRussell King 3308503f9aa9SRussell King state->an_complete = !!(gmac_stat & MVNETA_GMAC_AN_COMPLETE); 3309503f9aa9SRussell King state->link = !!(gmac_stat & MVNETA_GMAC_LINK_UP); 3310503f9aa9SRussell King state->duplex = !!(gmac_stat & MVNETA_GMAC_FULL_DUPLEX); 3311503f9aa9SRussell King 3312503f9aa9SRussell King state->pause = 0; 33134932a918SRussell King if (gmac_stat & MVNETA_GMAC_RX_FLOW_CTRL_ENABLE) 33144932a918SRussell King state->pause |= MLO_PAUSE_RX; 33154932a918SRussell King if (gmac_stat & MVNETA_GMAC_TX_FLOW_CTRL_ENABLE) 33164932a918SRussell King state->pause |= MLO_PAUSE_TX; 3317503f9aa9SRussell King 3318503f9aa9SRussell King return 1; 3319503f9aa9SRussell King } 3320503f9aa9SRussell King 332122f4bf8aSRussell King static void mvneta_mac_an_restart(struct net_device *ndev) 332222f4bf8aSRussell King { 332322f4bf8aSRussell King struct mvneta_port *pp = netdev_priv(ndev); 332422f4bf8aSRussell King u32 gmac_an = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG); 332522f4bf8aSRussell King 332622f4bf8aSRussell King mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, 332722f4bf8aSRussell King gmac_an | MVNETA_GMAC_INBAND_RESTART_AN); 332822f4bf8aSRussell King mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, 332922f4bf8aSRussell King gmac_an & ~MVNETA_GMAC_INBAND_RESTART_AN); 333022f4bf8aSRussell King } 333122f4bf8aSRussell King 3332503f9aa9SRussell King static void mvneta_mac_config(struct net_device *ndev, unsigned int mode, 3333503f9aa9SRussell King const struct phylink_link_state *state) 3334503f9aa9SRussell King { 3335503f9aa9SRussell King struct mvneta_port *pp = netdev_priv(ndev); 333622f4bf8aSRussell King u32 new_ctrl0, gmac_ctrl0 = mvreg_read(pp, MVNETA_GMAC_CTRL_0); 3337503f9aa9SRussell King u32 new_ctrl2, gmac_ctrl2 = mvreg_read(pp, MVNETA_GMAC_CTRL_2); 3338503f9aa9SRussell King u32 new_clk, gmac_clk = mvreg_read(pp, MVNETA_GMAC_CLOCK_DIVIDER); 3339503f9aa9SRussell King u32 new_an, gmac_an = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG); 3340503f9aa9SRussell King 334122f4bf8aSRussell King new_ctrl0 = gmac_ctrl0 & ~MVNETA_GMAC0_PORT_1000BASE_X; 334232699954SRussell King new_ctrl2 = gmac_ctrl2 & ~(MVNETA_GMAC2_INBAND_AN_ENABLE | 334332699954SRussell King MVNETA_GMAC2_PORT_RESET); 3344503f9aa9SRussell King new_clk = gmac_clk & ~MVNETA_GMAC_1MS_CLOCK_ENABLE; 3345503f9aa9SRussell King new_an = gmac_an & ~(MVNETA_GMAC_INBAND_AN_ENABLE | 3346503f9aa9SRussell King MVNETA_GMAC_INBAND_RESTART_AN | 3347503f9aa9SRussell King MVNETA_GMAC_CONFIG_MII_SPEED | 3348c5aff182SThomas Petazzoni MVNETA_GMAC_CONFIG_GMII_SPEED | 3349503f9aa9SRussell King MVNETA_GMAC_AN_SPEED_EN | 335022f4bf8aSRussell King MVNETA_GMAC_ADVERT_SYM_FLOW_CTRL | 335122f4bf8aSRussell King MVNETA_GMAC_CONFIG_FLOW_CTRL | 3352503f9aa9SRussell King MVNETA_GMAC_AN_FLOW_CTRL_EN | 3353503f9aa9SRussell King MVNETA_GMAC_CONFIG_FULL_DUPLEX | 3354503f9aa9SRussell King MVNETA_GMAC_AN_DUPLEX_EN); 3355c5aff182SThomas Petazzoni 335632699954SRussell King /* Even though it might look weird, when we're configured in 335732699954SRussell King * SGMII or QSGMII mode, the RGMII bit needs to be set. 335832699954SRussell King */ 335932699954SRussell King new_ctrl2 |= MVNETA_GMAC2_PORT_RGMII; 336032699954SRussell King 336132699954SRussell King if (state->interface == PHY_INTERFACE_MODE_QSGMII || 336222f4bf8aSRussell King state->interface == PHY_INTERFACE_MODE_SGMII || 336322f4bf8aSRussell King phy_interface_mode_is_8023z(state->interface)) 336432699954SRussell King new_ctrl2 |= MVNETA_GMAC2_PCS_ENABLE; 336532699954SRussell King 33664932a918SRussell King if (phylink_test(state->advertising, Pause)) 33674932a918SRussell King new_an |= MVNETA_GMAC_ADVERT_SYM_FLOW_CTRL; 33684932a918SRussell King if (state->pause & MLO_PAUSE_TXRX_MASK) 33694932a918SRussell King new_an |= MVNETA_GMAC_CONFIG_FLOW_CTRL; 33704932a918SRussell King 3371503f9aa9SRussell King if (!phylink_autoneg_inband(mode)) { 3372503f9aa9SRussell King /* Phy or fixed speed */ 3373503f9aa9SRussell King if (state->duplex) 3374503f9aa9SRussell King new_an |= MVNETA_GMAC_CONFIG_FULL_DUPLEX; 3375c5aff182SThomas Petazzoni 3376503f9aa9SRussell King if (state->speed == SPEED_1000) 3377503f9aa9SRussell King new_an |= MVNETA_GMAC_CONFIG_GMII_SPEED; 3378503f9aa9SRussell King else if (state->speed == SPEED_100) 3379503f9aa9SRussell King new_an |= MVNETA_GMAC_CONFIG_MII_SPEED; 338022f4bf8aSRussell King } else if (state->interface == PHY_INTERFACE_MODE_SGMII) { 3381503f9aa9SRussell King /* SGMII mode receives the state from the PHY */ 3382503f9aa9SRussell King new_ctrl2 |= MVNETA_GMAC2_INBAND_AN_ENABLE; 3383503f9aa9SRussell King new_clk |= MVNETA_GMAC_1MS_CLOCK_ENABLE; 3384503f9aa9SRussell King new_an = (new_an & ~(MVNETA_GMAC_FORCE_LINK_DOWN | 3385503f9aa9SRussell King MVNETA_GMAC_FORCE_LINK_PASS)) | 3386503f9aa9SRussell King MVNETA_GMAC_INBAND_AN_ENABLE | 3387503f9aa9SRussell King MVNETA_GMAC_AN_SPEED_EN | 3388503f9aa9SRussell King MVNETA_GMAC_AN_DUPLEX_EN; 338922f4bf8aSRussell King } else { 339022f4bf8aSRussell King /* 802.3z negotiation - only 1000base-X */ 339122f4bf8aSRussell King new_ctrl0 |= MVNETA_GMAC0_PORT_1000BASE_X; 339222f4bf8aSRussell King new_clk |= MVNETA_GMAC_1MS_CLOCK_ENABLE; 339322f4bf8aSRussell King new_an = (new_an & ~(MVNETA_GMAC_FORCE_LINK_DOWN | 339422f4bf8aSRussell King MVNETA_GMAC_FORCE_LINK_PASS)) | 339522f4bf8aSRussell King MVNETA_GMAC_INBAND_AN_ENABLE | 339622f4bf8aSRussell King MVNETA_GMAC_CONFIG_GMII_SPEED | 339722f4bf8aSRussell King /* The MAC only supports FD mode */ 339822f4bf8aSRussell King MVNETA_GMAC_CONFIG_FULL_DUPLEX; 33994932a918SRussell King 34004932a918SRussell King if (state->pause & MLO_PAUSE_AN && state->an_enabled) 34014932a918SRussell King new_an |= MVNETA_GMAC_AN_FLOW_CTRL_EN; 3402c5aff182SThomas Petazzoni } 3403c5aff182SThomas Petazzoni 3404503f9aa9SRussell King /* Armada 370 documentation says we can only change the port mode 3405503f9aa9SRussell King * and in-band enable when the link is down, so force it down 3406503f9aa9SRussell King * while making these changes. We also do this for GMAC_CTRL2 */ 340722f4bf8aSRussell King if ((new_ctrl0 ^ gmac_ctrl0) & MVNETA_GMAC0_PORT_1000BASE_X || 340822f4bf8aSRussell King (new_ctrl2 ^ gmac_ctrl2) & MVNETA_GMAC2_INBAND_AN_ENABLE || 3409503f9aa9SRussell King (new_an ^ gmac_an) & MVNETA_GMAC_INBAND_AN_ENABLE) { 3410503f9aa9SRussell King mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, 3411503f9aa9SRussell King (gmac_an & ~MVNETA_GMAC_FORCE_LINK_PASS) | 3412503f9aa9SRussell King MVNETA_GMAC_FORCE_LINK_DOWN); 3413503f9aa9SRussell King } 3414503f9aa9SRussell King 341522f4bf8aSRussell King if (new_ctrl0 != gmac_ctrl0) 341622f4bf8aSRussell King mvreg_write(pp, MVNETA_GMAC_CTRL_0, new_ctrl0); 3417503f9aa9SRussell King if (new_ctrl2 != gmac_ctrl2) 3418503f9aa9SRussell King mvreg_write(pp, MVNETA_GMAC_CTRL_2, new_ctrl2); 3419503f9aa9SRussell King if (new_clk != gmac_clk) 3420503f9aa9SRussell King mvreg_write(pp, MVNETA_GMAC_CLOCK_DIVIDER, new_clk); 3421503f9aa9SRussell King if (new_an != gmac_an) 3422503f9aa9SRussell King mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, new_an); 342332699954SRussell King 342432699954SRussell King if (gmac_ctrl2 & MVNETA_GMAC2_PORT_RESET) { 342532699954SRussell King while ((mvreg_read(pp, MVNETA_GMAC_CTRL_2) & 342632699954SRussell King MVNETA_GMAC2_PORT_RESET) != 0) 342732699954SRussell King continue; 342832699954SRussell King } 3429503f9aa9SRussell King } 3430503f9aa9SRussell King 34316d81f451SRussell King static void mvneta_set_eee(struct mvneta_port *pp, bool enable) 34326d81f451SRussell King { 34336d81f451SRussell King u32 lpi_ctl1; 34346d81f451SRussell King 34356d81f451SRussell King lpi_ctl1 = mvreg_read(pp, MVNETA_LPI_CTRL_1); 34366d81f451SRussell King if (enable) 34376d81f451SRussell King lpi_ctl1 |= MVNETA_LPI_REQUEST_ENABLE; 34386d81f451SRussell King else 34396d81f451SRussell King lpi_ctl1 &= ~MVNETA_LPI_REQUEST_ENABLE; 34406d81f451SRussell King mvreg_write(pp, MVNETA_LPI_CTRL_1, lpi_ctl1); 34416d81f451SRussell King } 34426d81f451SRussell King 3443c6ab3008SFlorian Fainelli static void mvneta_mac_link_down(struct net_device *ndev, unsigned int mode, 3444c6ab3008SFlorian Fainelli phy_interface_t interface) 3445fc548b99SRussell King { 3446fc548b99SRussell King struct mvneta_port *pp = netdev_priv(ndev); 3447fc548b99SRussell King u32 val; 3448fc548b99SRussell King 3449503f9aa9SRussell King mvneta_port_down(pp); 3450503f9aa9SRussell King 3451503f9aa9SRussell King if (!phylink_autoneg_inband(mode)) { 3452fc548b99SRussell King val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG); 3453fc548b99SRussell King val &= ~MVNETA_GMAC_FORCE_LINK_PASS; 3454fc548b99SRussell King val |= MVNETA_GMAC_FORCE_LINK_DOWN; 3455fc548b99SRussell King mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val); 3456fc548b99SRussell King } 34576d81f451SRussell King 34586d81f451SRussell King pp->eee_active = false; 34596d81f451SRussell King mvneta_set_eee(pp, false); 3460fc548b99SRussell King } 3461fc548b99SRussell King 3462503f9aa9SRussell King static void mvneta_mac_link_up(struct net_device *ndev, unsigned int mode, 3463c6ab3008SFlorian Fainelli phy_interface_t interface, 3464503f9aa9SRussell King struct phy_device *phy) 3465fc548b99SRussell King { 3466fc548b99SRussell King struct mvneta_port *pp = netdev_priv(ndev); 3467fc548b99SRussell King u32 val; 3468fc548b99SRussell King 3469503f9aa9SRussell King if (!phylink_autoneg_inband(mode)) { 3470fc548b99SRussell King val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG); 3471fc548b99SRussell King val &= ~MVNETA_GMAC_FORCE_LINK_DOWN; 3472fc548b99SRussell King val |= MVNETA_GMAC_FORCE_LINK_PASS; 3473fc548b99SRussell King mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val); 3474fc548b99SRussell King } 3475fc548b99SRussell King 3476fc548b99SRussell King mvneta_port_up(pp); 34776d81f451SRussell King 34786d81f451SRussell King if (phy && pp->eee_enabled) { 34796d81f451SRussell King pp->eee_active = phy_init_eee(phy, 0) >= 0; 34806d81f451SRussell King mvneta_set_eee(pp, pp->eee_active && pp->tx_lpi_enabled); 34816d81f451SRussell King } 3482fc548b99SRussell King } 3483fc548b99SRussell King 3484503f9aa9SRussell King static const struct phylink_mac_ops mvneta_phylink_ops = { 3485503f9aa9SRussell King .validate = mvneta_validate, 3486503f9aa9SRussell King .mac_link_state = mvneta_mac_link_state, 348722f4bf8aSRussell King .mac_an_restart = mvneta_mac_an_restart, 3488503f9aa9SRussell King .mac_config = mvneta_mac_config, 3489503f9aa9SRussell King .mac_link_down = mvneta_mac_link_down, 3490503f9aa9SRussell King .mac_link_up = mvneta_mac_link_up, 3491503f9aa9SRussell King }; 3492c5aff182SThomas Petazzoni 3493c5aff182SThomas Petazzoni static int mvneta_mdio_probe(struct mvneta_port *pp) 3494c5aff182SThomas Petazzoni { 349582960fffSJisheng Zhang struct ethtool_wolinfo wol = { .cmd = ETHTOOL_GWOL }; 3496503f9aa9SRussell King int err = phylink_of_phy_connect(pp->phylink, pp->dn, 0); 3497c5aff182SThomas Petazzoni 3498503f9aa9SRussell King if (err) 3499503f9aa9SRussell King netdev_err(pp->dev, "could not attach PHY: %d\n", err); 3500c5aff182SThomas Petazzoni 3501503f9aa9SRussell King phylink_ethtool_get_wol(pp->phylink, &wol); 350282960fffSJisheng Zhang device_set_wakeup_capable(&pp->dev->dev, !!wol.supported); 350382960fffSJisheng Zhang 3504503f9aa9SRussell King return err; 3505c5aff182SThomas Petazzoni } 3506c5aff182SThomas Petazzoni 3507c5aff182SThomas Petazzoni static void mvneta_mdio_remove(struct mvneta_port *pp) 3508c5aff182SThomas Petazzoni { 3509503f9aa9SRussell King phylink_disconnect_phy(pp->phylink); 3510c5aff182SThomas Petazzoni } 3511c5aff182SThomas Petazzoni 3512120cfa50SGregory CLEMENT /* Electing a CPU must be done in an atomic way: it should be done 3513120cfa50SGregory CLEMENT * after or before the removal/insertion of a CPU and this function is 3514120cfa50SGregory CLEMENT * not reentrant. 3515120cfa50SGregory CLEMENT */ 3516f8642885SMaxime Ripard static void mvneta_percpu_elect(struct mvneta_port *pp) 3517f8642885SMaxime Ripard { 3518cad5d847SGregory CLEMENT int elected_cpu = 0, max_cpu, cpu, i = 0; 3519f8642885SMaxime Ripard 3520cad5d847SGregory CLEMENT /* Use the cpu associated to the rxq when it is online, in all 3521cad5d847SGregory CLEMENT * the other cases, use the cpu 0 which can't be offline. 3522cad5d847SGregory CLEMENT */ 3523cad5d847SGregory CLEMENT if (cpu_online(pp->rxq_def)) 3524cad5d847SGregory CLEMENT elected_cpu = pp->rxq_def; 3525cad5d847SGregory CLEMENT 35262dcf75e2SGregory CLEMENT max_cpu = num_present_cpus(); 3527f8642885SMaxime Ripard 3528f8642885SMaxime Ripard for_each_online_cpu(cpu) { 35292dcf75e2SGregory CLEMENT int rxq_map = 0, txq_map = 0; 35302dcf75e2SGregory CLEMENT int rxq; 35312dcf75e2SGregory CLEMENT 35322dcf75e2SGregory CLEMENT for (rxq = 0; rxq < rxq_number; rxq++) 35332dcf75e2SGregory CLEMENT if ((rxq % max_cpu) == cpu) 35342dcf75e2SGregory CLEMENT rxq_map |= MVNETA_CPU_RXQ_ACCESS(rxq); 35352dcf75e2SGregory CLEMENT 3536cad5d847SGregory CLEMENT if (cpu == elected_cpu) 353750bf8cb6SGregory CLEMENT /* Map the default receive queue queue to the 353850bf8cb6SGregory CLEMENT * elected CPU 3539f8642885SMaxime Ripard */ 35402dcf75e2SGregory CLEMENT rxq_map |= MVNETA_CPU_RXQ_ACCESS(pp->rxq_def); 354150bf8cb6SGregory CLEMENT 354250bf8cb6SGregory CLEMENT /* We update the TX queue map only if we have one 354350bf8cb6SGregory CLEMENT * queue. In this case we associate the TX queue to 354450bf8cb6SGregory CLEMENT * the CPU bound to the default RX queue 354550bf8cb6SGregory CLEMENT */ 354650bf8cb6SGregory CLEMENT if (txq_number == 1) 3547cad5d847SGregory CLEMENT txq_map = (cpu == elected_cpu) ? 354850bf8cb6SGregory CLEMENT MVNETA_CPU_TXQ_ACCESS(1) : 0; 354950bf8cb6SGregory CLEMENT else 355050bf8cb6SGregory CLEMENT txq_map = mvreg_read(pp, MVNETA_CPU_MAP(cpu)) & 355150bf8cb6SGregory CLEMENT MVNETA_CPU_TXQ_ACCESS_ALL_MASK; 355250bf8cb6SGregory CLEMENT 35532dcf75e2SGregory CLEMENT mvreg_write(pp, MVNETA_CPU_MAP(cpu), rxq_map | txq_map); 35542dcf75e2SGregory CLEMENT 35552dcf75e2SGregory CLEMENT /* Update the interrupt mask on each CPU according the 35562dcf75e2SGregory CLEMENT * new mapping 35572dcf75e2SGregory CLEMENT */ 35582dcf75e2SGregory CLEMENT smp_call_function_single(cpu, mvneta_percpu_unmask_interrupt, 3559f8642885SMaxime Ripard pp, true); 3560f8642885SMaxime Ripard i++; 35612dcf75e2SGregory CLEMENT 3562f8642885SMaxime Ripard } 3563f8642885SMaxime Ripard }; 3564f8642885SMaxime Ripard 356584a3f4dbSSebastian Andrzej Siewior static int mvneta_cpu_online(unsigned int cpu, struct hlist_node *node) 3566f8642885SMaxime Ripard { 356784a3f4dbSSebastian Andrzej Siewior int other_cpu; 356884a3f4dbSSebastian Andrzej Siewior struct mvneta_port *pp = hlist_entry_safe(node, struct mvneta_port, 356984a3f4dbSSebastian Andrzej Siewior node_online); 3570f8642885SMaxime Ripard struct mvneta_pcpu_port *port = per_cpu_ptr(pp->ports, cpu); 3571f8642885SMaxime Ripard 357284a3f4dbSSebastian Andrzej Siewior 3573120cfa50SGregory CLEMENT spin_lock(&pp->lock); 357484a3f4dbSSebastian Andrzej Siewior /* 357584a3f4dbSSebastian Andrzej Siewior * Configuring the driver for a new CPU while the driver is 357684a3f4dbSSebastian Andrzej Siewior * stopping is racy, so just avoid it. 3577120cfa50SGregory CLEMENT */ 3578120cfa50SGregory CLEMENT if (pp->is_stopped) { 3579120cfa50SGregory CLEMENT spin_unlock(&pp->lock); 358084a3f4dbSSebastian Andrzej Siewior return 0; 3581120cfa50SGregory CLEMENT } 3582f8642885SMaxime Ripard netif_tx_stop_all_queues(pp->dev); 3583f8642885SMaxime Ripard 358484a3f4dbSSebastian Andrzej Siewior /* 358584a3f4dbSSebastian Andrzej Siewior * We have to synchronise on tha napi of each CPU except the one 358684a3f4dbSSebastian Andrzej Siewior * just being woken up 3587f8642885SMaxime Ripard */ 3588f8642885SMaxime Ripard for_each_online_cpu(other_cpu) { 3589f8642885SMaxime Ripard if (other_cpu != cpu) { 3590f8642885SMaxime Ripard struct mvneta_pcpu_port *other_port = 3591f8642885SMaxime Ripard per_cpu_ptr(pp->ports, other_cpu); 3592f8642885SMaxime Ripard 3593f8642885SMaxime Ripard napi_synchronize(&other_port->napi); 3594f8642885SMaxime Ripard } 3595f8642885SMaxime Ripard } 3596f8642885SMaxime Ripard 3597f8642885SMaxime Ripard /* Mask all ethernet port interrupts */ 3598db488c10SGregory CLEMENT on_each_cpu(mvneta_percpu_mask_interrupt, pp, true); 3599f8642885SMaxime Ripard napi_enable(&port->napi); 3600f8642885SMaxime Ripard 360184a3f4dbSSebastian Andrzej Siewior /* 360284a3f4dbSSebastian Andrzej Siewior * Enable per-CPU interrupts on the CPU that is 36032dcf75e2SGregory CLEMENT * brought up. 36042dcf75e2SGregory CLEMENT */ 36050e28bf93SAnna-Maria Gleixner mvneta_percpu_enable(pp); 36062dcf75e2SGregory CLEMENT 360784a3f4dbSSebastian Andrzej Siewior /* 360884a3f4dbSSebastian Andrzej Siewior * Enable per-CPU interrupt on the one CPU we care 3609f8642885SMaxime Ripard * about. 3610f8642885SMaxime Ripard */ 3611f8642885SMaxime Ripard mvneta_percpu_elect(pp); 3612f8642885SMaxime Ripard 3613db488c10SGregory CLEMENT /* Unmask all ethernet port interrupts */ 3614db488c10SGregory CLEMENT on_each_cpu(mvneta_percpu_unmask_interrupt, pp, true); 3615f8642885SMaxime Ripard mvreg_write(pp, MVNETA_INTR_MISC_MASK, 3616f8642885SMaxime Ripard MVNETA_CAUSE_PHY_STATUS_CHANGE | 3617856b2cc5SRussell King MVNETA_CAUSE_LINK_CHANGE); 3618f8642885SMaxime Ripard netif_tx_start_all_queues(pp->dev); 3619120cfa50SGregory CLEMENT spin_unlock(&pp->lock); 362084a3f4dbSSebastian Andrzej Siewior return 0; 362184a3f4dbSSebastian Andrzej Siewior } 362284a3f4dbSSebastian Andrzej Siewior 362384a3f4dbSSebastian Andrzej Siewior static int mvneta_cpu_down_prepare(unsigned int cpu, struct hlist_node *node) 362484a3f4dbSSebastian Andrzej Siewior { 362584a3f4dbSSebastian Andrzej Siewior struct mvneta_port *pp = hlist_entry_safe(node, struct mvneta_port, 362684a3f4dbSSebastian Andrzej Siewior node_online); 362784a3f4dbSSebastian Andrzej Siewior struct mvneta_pcpu_port *port = per_cpu_ptr(pp->ports, cpu); 362884a3f4dbSSebastian Andrzej Siewior 362984a3f4dbSSebastian Andrzej Siewior /* 363084a3f4dbSSebastian Andrzej Siewior * Thanks to this lock we are sure that any pending cpu election is 363184a3f4dbSSebastian Andrzej Siewior * done. 36325888511eSGregory CLEMENT */ 36335888511eSGregory CLEMENT spin_lock(&pp->lock); 3634f8642885SMaxime Ripard /* Mask all ethernet port interrupts */ 3635db488c10SGregory CLEMENT on_each_cpu(mvneta_percpu_mask_interrupt, pp, true); 36365888511eSGregory CLEMENT spin_unlock(&pp->lock); 3637f8642885SMaxime Ripard 3638f8642885SMaxime Ripard napi_synchronize(&port->napi); 3639f8642885SMaxime Ripard napi_disable(&port->napi); 364084a3f4dbSSebastian Andrzej Siewior /* Disable per-CPU interrupts on the CPU that is brought down. */ 36410e28bf93SAnna-Maria Gleixner mvneta_percpu_disable(pp); 364284a3f4dbSSebastian Andrzej Siewior return 0; 364384a3f4dbSSebastian Andrzej Siewior } 3644f8642885SMaxime Ripard 364584a3f4dbSSebastian Andrzej Siewior static int mvneta_cpu_dead(unsigned int cpu, struct hlist_node *node) 364684a3f4dbSSebastian Andrzej Siewior { 364784a3f4dbSSebastian Andrzej Siewior struct mvneta_port *pp = hlist_entry_safe(node, struct mvneta_port, 364884a3f4dbSSebastian Andrzej Siewior node_dead); 364984a3f4dbSSebastian Andrzej Siewior 3650f8642885SMaxime Ripard /* Check if a new CPU must be elected now this on is down */ 3651120cfa50SGregory CLEMENT spin_lock(&pp->lock); 3652f8642885SMaxime Ripard mvneta_percpu_elect(pp); 3653120cfa50SGregory CLEMENT spin_unlock(&pp->lock); 3654f8642885SMaxime Ripard /* Unmask all ethernet port interrupts */ 3655db488c10SGregory CLEMENT on_each_cpu(mvneta_percpu_unmask_interrupt, pp, true); 3656f8642885SMaxime Ripard mvreg_write(pp, MVNETA_INTR_MISC_MASK, 3657f8642885SMaxime Ripard MVNETA_CAUSE_PHY_STATUS_CHANGE | 3658856b2cc5SRussell King MVNETA_CAUSE_LINK_CHANGE); 3659f8642885SMaxime Ripard netif_tx_start_all_queues(pp->dev); 366084a3f4dbSSebastian Andrzej Siewior return 0; 3661f8642885SMaxime Ripard } 3662f8642885SMaxime Ripard 3663c5aff182SThomas Petazzoni static int mvneta_open(struct net_device *dev) 3664c5aff182SThomas Petazzoni { 3665c5aff182SThomas Petazzoni struct mvneta_port *pp = netdev_priv(dev); 36666b125d63SGregory CLEMENT int ret; 3667c5aff182SThomas Petazzoni 3668c5aff182SThomas Petazzoni pp->pkt_size = MVNETA_RX_PKT_SIZE(pp->dev->mtu); 36698ec2cd48Swilly tarreau pp->frag_size = SKB_DATA_ALIGN(MVNETA_RX_BUF_SIZE(pp->pkt_size)) + 36708ec2cd48Swilly tarreau SKB_DATA_ALIGN(sizeof(struct skb_shared_info)); 3671c5aff182SThomas Petazzoni 3672c5aff182SThomas Petazzoni ret = mvneta_setup_rxqs(pp); 3673c5aff182SThomas Petazzoni if (ret) 3674c5aff182SThomas Petazzoni return ret; 3675c5aff182SThomas Petazzoni 3676c5aff182SThomas Petazzoni ret = mvneta_setup_txqs(pp); 3677c5aff182SThomas Petazzoni if (ret) 3678c5aff182SThomas Petazzoni goto err_cleanup_rxqs; 3679c5aff182SThomas Petazzoni 3680c5aff182SThomas Petazzoni /* Connect to port interrupt line */ 36812636ac3cSMarcin Wojtas if (pp->neta_armada3700) 36822636ac3cSMarcin Wojtas ret = request_irq(pp->dev->irq, mvneta_isr, 0, 36832636ac3cSMarcin Wojtas dev->name, pp); 36842636ac3cSMarcin Wojtas else 36852636ac3cSMarcin Wojtas ret = request_percpu_irq(pp->dev->irq, mvneta_percpu_isr, 36862636ac3cSMarcin Wojtas dev->name, pp->ports); 3687c5aff182SThomas Petazzoni if (ret) { 3688c5aff182SThomas Petazzoni netdev_err(pp->dev, "cannot request irq %d\n", pp->dev->irq); 3689c5aff182SThomas Petazzoni goto err_cleanup_txqs; 3690c5aff182SThomas Petazzoni } 3691c5aff182SThomas Petazzoni 36922636ac3cSMarcin Wojtas if (!pp->neta_armada3700) { 36932dcf75e2SGregory CLEMENT /* Enable per-CPU interrupt on all the CPU to handle our RX 36942dcf75e2SGregory CLEMENT * queue interrupts 36952dcf75e2SGregory CLEMENT */ 36966b125d63SGregory CLEMENT on_each_cpu(mvneta_percpu_enable, pp, true); 36972dcf75e2SGregory CLEMENT 3698120cfa50SGregory CLEMENT pp->is_stopped = false; 3699f8642885SMaxime Ripard /* Register a CPU notifier to handle the case where our CPU 3700f8642885SMaxime Ripard * might be taken offline. 3701f8642885SMaxime Ripard */ 370284a3f4dbSSebastian Andrzej Siewior ret = cpuhp_state_add_instance_nocalls(online_hpstate, 370384a3f4dbSSebastian Andrzej Siewior &pp->node_online); 370484a3f4dbSSebastian Andrzej Siewior if (ret) 370584a3f4dbSSebastian Andrzej Siewior goto err_free_irq; 370684a3f4dbSSebastian Andrzej Siewior 370784a3f4dbSSebastian Andrzej Siewior ret = cpuhp_state_add_instance_nocalls(CPUHP_NET_MVNETA_DEAD, 370884a3f4dbSSebastian Andrzej Siewior &pp->node_dead); 370984a3f4dbSSebastian Andrzej Siewior if (ret) 371084a3f4dbSSebastian Andrzej Siewior goto err_free_online_hp; 37112636ac3cSMarcin Wojtas } 3712f8642885SMaxime Ripard 3713c5aff182SThomas Petazzoni /* In default link is down */ 3714c5aff182SThomas Petazzoni netif_carrier_off(pp->dev); 3715c5aff182SThomas Petazzoni 3716c5aff182SThomas Petazzoni ret = mvneta_mdio_probe(pp); 3717c5aff182SThomas Petazzoni if (ret < 0) { 3718c5aff182SThomas Petazzoni netdev_err(dev, "cannot probe MDIO bus\n"); 371984a3f4dbSSebastian Andrzej Siewior goto err_free_dead_hp; 3720c5aff182SThomas Petazzoni } 3721c5aff182SThomas Petazzoni 3722c5aff182SThomas Petazzoni mvneta_start_dev(pp); 3723c5aff182SThomas Petazzoni 3724c5aff182SThomas Petazzoni return 0; 3725c5aff182SThomas Petazzoni 372684a3f4dbSSebastian Andrzej Siewior err_free_dead_hp: 37272636ac3cSMarcin Wojtas if (!pp->neta_armada3700) 372884a3f4dbSSebastian Andrzej Siewior cpuhp_state_remove_instance_nocalls(CPUHP_NET_MVNETA_DEAD, 372984a3f4dbSSebastian Andrzej Siewior &pp->node_dead); 373084a3f4dbSSebastian Andrzej Siewior err_free_online_hp: 37312636ac3cSMarcin Wojtas if (!pp->neta_armada3700) 37322636ac3cSMarcin Wojtas cpuhp_state_remove_instance_nocalls(online_hpstate, 37332636ac3cSMarcin Wojtas &pp->node_online); 3734c5aff182SThomas Petazzoni err_free_irq: 37352636ac3cSMarcin Wojtas if (pp->neta_armada3700) { 37362636ac3cSMarcin Wojtas free_irq(pp->dev->irq, pp); 37372636ac3cSMarcin Wojtas } else { 37383d8c4530SRussell King - ARM Linux on_each_cpu(mvneta_percpu_disable, pp, true); 373912bb03b4SMaxime Ripard free_percpu_irq(pp->dev->irq, pp->ports); 37402636ac3cSMarcin Wojtas } 3741c5aff182SThomas Petazzoni err_cleanup_txqs: 3742c5aff182SThomas Petazzoni mvneta_cleanup_txqs(pp); 3743c5aff182SThomas Petazzoni err_cleanup_rxqs: 3744c5aff182SThomas Petazzoni mvneta_cleanup_rxqs(pp); 3745c5aff182SThomas Petazzoni return ret; 3746c5aff182SThomas Petazzoni } 3747c5aff182SThomas Petazzoni 3748c5aff182SThomas Petazzoni /* Stop the port, free port interrupt line */ 3749c5aff182SThomas Petazzoni static int mvneta_stop(struct net_device *dev) 3750c5aff182SThomas Petazzoni { 3751c5aff182SThomas Petazzoni struct mvneta_port *pp = netdev_priv(dev); 3752c5aff182SThomas Petazzoni 37532636ac3cSMarcin Wojtas if (!pp->neta_armada3700) { 3754120cfa50SGregory CLEMENT /* Inform that we are stopping so we don't want to setup the 37551c2722a9SGregory CLEMENT * driver for new CPUs in the notifiers. The code of the 37561c2722a9SGregory CLEMENT * notifier for CPU online is protected by the same spinlock, 37571c2722a9SGregory CLEMENT * so when we get the lock, the notifer work is done. 3758120cfa50SGregory CLEMENT */ 3759120cfa50SGregory CLEMENT spin_lock(&pp->lock); 3760120cfa50SGregory CLEMENT pp->is_stopped = true; 37611c2722a9SGregory CLEMENT spin_unlock(&pp->lock); 37621c2722a9SGregory CLEMENT 3763c5aff182SThomas Petazzoni mvneta_stop_dev(pp); 3764c5aff182SThomas Petazzoni mvneta_mdio_remove(pp); 376584a3f4dbSSebastian Andrzej Siewior 3766d26aac2dSDan Carpenter cpuhp_state_remove_instance_nocalls(online_hpstate, 3767d26aac2dSDan Carpenter &pp->node_online); 376884a3f4dbSSebastian Andrzej Siewior cpuhp_state_remove_instance_nocalls(CPUHP_NET_MVNETA_DEAD, 376984a3f4dbSSebastian Andrzej Siewior &pp->node_dead); 3770129219e4SGregory CLEMENT on_each_cpu(mvneta_percpu_disable, pp, true); 377112bb03b4SMaxime Ripard free_percpu_irq(dev->irq, pp->ports); 37722636ac3cSMarcin Wojtas } else { 37732636ac3cSMarcin Wojtas mvneta_stop_dev(pp); 37742636ac3cSMarcin Wojtas mvneta_mdio_remove(pp); 37752636ac3cSMarcin Wojtas free_irq(dev->irq, pp); 37762636ac3cSMarcin Wojtas } 37772636ac3cSMarcin Wojtas 3778c5aff182SThomas Petazzoni mvneta_cleanup_rxqs(pp); 3779c5aff182SThomas Petazzoni mvneta_cleanup_txqs(pp); 3780c5aff182SThomas Petazzoni 3781c5aff182SThomas Petazzoni return 0; 3782c5aff182SThomas Petazzoni } 3783c5aff182SThomas Petazzoni 378415f59456SThomas Petazzoni static int mvneta_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) 378515f59456SThomas Petazzoni { 3786503f9aa9SRussell King struct mvneta_port *pp = netdev_priv(dev); 378715f59456SThomas Petazzoni 3788503f9aa9SRussell King return phylink_mii_ioctl(pp->phylink, ifr, cmd); 378915f59456SThomas Petazzoni } 379015f59456SThomas Petazzoni 3791c5aff182SThomas Petazzoni /* Ethtool methods */ 3792c5aff182SThomas Petazzoni 3793013ad40dSPhilippe Reynes /* Set link ksettings (phy address, speed) for ethtools */ 37942dc0d2b4SBaoyou Xie static int 37952dc0d2b4SBaoyou Xie mvneta_ethtool_set_link_ksettings(struct net_device *ndev, 3796013ad40dSPhilippe Reynes const struct ethtool_link_ksettings *cmd) 3797c5aff182SThomas Petazzoni { 3798013ad40dSPhilippe Reynes struct mvneta_port *pp = netdev_priv(ndev); 3799c5aff182SThomas Petazzoni 3800503f9aa9SRussell King return phylink_ethtool_ksettings_set(pp->phylink, cmd); 38010c0744fcSStas Sergeev } 38020c0744fcSStas Sergeev 3803503f9aa9SRussell King /* Get link ksettings for ethtools */ 3804503f9aa9SRussell King static int 3805503f9aa9SRussell King mvneta_ethtool_get_link_ksettings(struct net_device *ndev, 3806503f9aa9SRussell King struct ethtool_link_ksettings *cmd) 3807503f9aa9SRussell King { 3808503f9aa9SRussell King struct mvneta_port *pp = netdev_priv(ndev); 38090c0744fcSStas Sergeev 3810503f9aa9SRussell King return phylink_ethtool_ksettings_get(pp->phylink, cmd); 38110c0744fcSStas Sergeev } 38120c0744fcSStas Sergeev 3813503f9aa9SRussell King static int mvneta_ethtool_nway_reset(struct net_device *dev) 3814503f9aa9SRussell King { 3815503f9aa9SRussell King struct mvneta_port *pp = netdev_priv(dev); 3816503f9aa9SRussell King 3817503f9aa9SRussell King return phylink_ethtool_nway_reset(pp->phylink); 3818c5aff182SThomas Petazzoni } 3819c5aff182SThomas Petazzoni 3820c5aff182SThomas Petazzoni /* Set interrupt coalescing for ethtools */ 3821c5aff182SThomas Petazzoni static int mvneta_ethtool_set_coalesce(struct net_device *dev, 3822c5aff182SThomas Petazzoni struct ethtool_coalesce *c) 3823c5aff182SThomas Petazzoni { 3824c5aff182SThomas Petazzoni struct mvneta_port *pp = netdev_priv(dev); 3825c5aff182SThomas Petazzoni int queue; 3826c5aff182SThomas Petazzoni 3827c5aff182SThomas Petazzoni for (queue = 0; queue < rxq_number; queue++) { 3828c5aff182SThomas Petazzoni struct mvneta_rx_queue *rxq = &pp->rxqs[queue]; 3829c5aff182SThomas Petazzoni rxq->time_coal = c->rx_coalesce_usecs; 3830c5aff182SThomas Petazzoni rxq->pkts_coal = c->rx_max_coalesced_frames; 3831c5aff182SThomas Petazzoni mvneta_rx_pkts_coal_set(pp, rxq, rxq->pkts_coal); 3832c5aff182SThomas Petazzoni mvneta_rx_time_coal_set(pp, rxq, rxq->time_coal); 3833c5aff182SThomas Petazzoni } 3834c5aff182SThomas Petazzoni 3835c5aff182SThomas Petazzoni for (queue = 0; queue < txq_number; queue++) { 3836c5aff182SThomas Petazzoni struct mvneta_tx_queue *txq = &pp->txqs[queue]; 3837c5aff182SThomas Petazzoni txq->done_pkts_coal = c->tx_max_coalesced_frames; 3838c5aff182SThomas Petazzoni mvneta_tx_done_pkts_coal_set(pp, txq, txq->done_pkts_coal); 3839c5aff182SThomas Petazzoni } 3840c5aff182SThomas Petazzoni 3841c5aff182SThomas Petazzoni return 0; 3842c5aff182SThomas Petazzoni } 3843c5aff182SThomas Petazzoni 3844c5aff182SThomas Petazzoni /* get coalescing for ethtools */ 3845c5aff182SThomas Petazzoni static int mvneta_ethtool_get_coalesce(struct net_device *dev, 3846c5aff182SThomas Petazzoni struct ethtool_coalesce *c) 3847c5aff182SThomas Petazzoni { 3848c5aff182SThomas Petazzoni struct mvneta_port *pp = netdev_priv(dev); 3849c5aff182SThomas Petazzoni 3850c5aff182SThomas Petazzoni c->rx_coalesce_usecs = pp->rxqs[0].time_coal; 3851c5aff182SThomas Petazzoni c->rx_max_coalesced_frames = pp->rxqs[0].pkts_coal; 3852c5aff182SThomas Petazzoni 3853c5aff182SThomas Petazzoni c->tx_max_coalesced_frames = pp->txqs[0].done_pkts_coal; 3854c5aff182SThomas Petazzoni return 0; 3855c5aff182SThomas Petazzoni } 3856c5aff182SThomas Petazzoni 3857c5aff182SThomas Petazzoni 3858c5aff182SThomas Petazzoni static void mvneta_ethtool_get_drvinfo(struct net_device *dev, 3859c5aff182SThomas Petazzoni struct ethtool_drvinfo *drvinfo) 3860c5aff182SThomas Petazzoni { 3861c5aff182SThomas Petazzoni strlcpy(drvinfo->driver, MVNETA_DRIVER_NAME, 3862c5aff182SThomas Petazzoni sizeof(drvinfo->driver)); 3863c5aff182SThomas Petazzoni strlcpy(drvinfo->version, MVNETA_DRIVER_VERSION, 3864c5aff182SThomas Petazzoni sizeof(drvinfo->version)); 3865c5aff182SThomas Petazzoni strlcpy(drvinfo->bus_info, dev_name(&dev->dev), 3866c5aff182SThomas Petazzoni sizeof(drvinfo->bus_info)); 3867c5aff182SThomas Petazzoni } 3868c5aff182SThomas Petazzoni 3869c5aff182SThomas Petazzoni 3870c5aff182SThomas Petazzoni static void mvneta_ethtool_get_ringparam(struct net_device *netdev, 3871c5aff182SThomas Petazzoni struct ethtool_ringparam *ring) 3872c5aff182SThomas Petazzoni { 3873c5aff182SThomas Petazzoni struct mvneta_port *pp = netdev_priv(netdev); 3874c5aff182SThomas Petazzoni 3875c5aff182SThomas Petazzoni ring->rx_max_pending = MVNETA_MAX_RXD; 3876c5aff182SThomas Petazzoni ring->tx_max_pending = MVNETA_MAX_TXD; 3877c5aff182SThomas Petazzoni ring->rx_pending = pp->rx_ring_size; 3878c5aff182SThomas Petazzoni ring->tx_pending = pp->tx_ring_size; 3879c5aff182SThomas Petazzoni } 3880c5aff182SThomas Petazzoni 3881c5aff182SThomas Petazzoni static int mvneta_ethtool_set_ringparam(struct net_device *dev, 3882c5aff182SThomas Petazzoni struct ethtool_ringparam *ring) 3883c5aff182SThomas Petazzoni { 3884c5aff182SThomas Petazzoni struct mvneta_port *pp = netdev_priv(dev); 3885c5aff182SThomas Petazzoni 3886c5aff182SThomas Petazzoni if ((ring->rx_pending == 0) || (ring->tx_pending == 0)) 3887c5aff182SThomas Petazzoni return -EINVAL; 3888c5aff182SThomas Petazzoni pp->rx_ring_size = ring->rx_pending < MVNETA_MAX_RXD ? 3889c5aff182SThomas Petazzoni ring->rx_pending : MVNETA_MAX_RXD; 38908eef5f97SEzequiel Garcia 38918eef5f97SEzequiel Garcia pp->tx_ring_size = clamp_t(u16, ring->tx_pending, 38928eef5f97SEzequiel Garcia MVNETA_MAX_SKB_DESCS * 2, MVNETA_MAX_TXD); 38938eef5f97SEzequiel Garcia if (pp->tx_ring_size != ring->tx_pending) 38948eef5f97SEzequiel Garcia netdev_warn(dev, "TX queue size set to %u (requested %u)\n", 38958eef5f97SEzequiel Garcia pp->tx_ring_size, ring->tx_pending); 3896c5aff182SThomas Petazzoni 3897c5aff182SThomas Petazzoni if (netif_running(dev)) { 3898c5aff182SThomas Petazzoni mvneta_stop(dev); 3899c5aff182SThomas Petazzoni if (mvneta_open(dev)) { 3900c5aff182SThomas Petazzoni netdev_err(dev, 3901c5aff182SThomas Petazzoni "error on opening device after ring param change\n"); 3902c5aff182SThomas Petazzoni return -ENOMEM; 3903c5aff182SThomas Petazzoni } 3904c5aff182SThomas Petazzoni } 3905c5aff182SThomas Petazzoni 3906c5aff182SThomas Petazzoni return 0; 3907c5aff182SThomas Petazzoni } 3908c5aff182SThomas Petazzoni 39094932a918SRussell King static void mvneta_ethtool_get_pauseparam(struct net_device *dev, 39104932a918SRussell King struct ethtool_pauseparam *pause) 39114932a918SRussell King { 39124932a918SRussell King struct mvneta_port *pp = netdev_priv(dev); 39134932a918SRussell King 39144932a918SRussell King phylink_ethtool_get_pauseparam(pp->phylink, pause); 39154932a918SRussell King } 39164932a918SRussell King 39174932a918SRussell King static int mvneta_ethtool_set_pauseparam(struct net_device *dev, 39184932a918SRussell King struct ethtool_pauseparam *pause) 39194932a918SRussell King { 39204932a918SRussell King struct mvneta_port *pp = netdev_priv(dev); 39214932a918SRussell King 39224932a918SRussell King return phylink_ethtool_set_pauseparam(pp->phylink, pause); 39234932a918SRussell King } 39244932a918SRussell King 39259b0cdefaSRussell King static void mvneta_ethtool_get_strings(struct net_device *netdev, u32 sset, 39269b0cdefaSRussell King u8 *data) 39279b0cdefaSRussell King { 39289b0cdefaSRussell King if (sset == ETH_SS_STATS) { 39299b0cdefaSRussell King int i; 39309b0cdefaSRussell King 39319b0cdefaSRussell King for (i = 0; i < ARRAY_SIZE(mvneta_statistics); i++) 39329b0cdefaSRussell King memcpy(data + i * ETH_GSTRING_LEN, 39339b0cdefaSRussell King mvneta_statistics[i].name, ETH_GSTRING_LEN); 39349b0cdefaSRussell King } 39359b0cdefaSRussell King } 39369b0cdefaSRussell King 39379b0cdefaSRussell King static void mvneta_ethtool_update_stats(struct mvneta_port *pp) 39389b0cdefaSRussell King { 39399b0cdefaSRussell King const struct mvneta_statistic *s; 39409b0cdefaSRussell King void __iomem *base = pp->base; 39416d81f451SRussell King u32 high, low; 39426d81f451SRussell King u64 val; 39439b0cdefaSRussell King int i; 39449b0cdefaSRussell King 39459b0cdefaSRussell King for (i = 0, s = mvneta_statistics; 39469b0cdefaSRussell King s < mvneta_statistics + ARRAY_SIZE(mvneta_statistics); 39479b0cdefaSRussell King s++, i++) { 39486d81f451SRussell King val = 0; 39496d81f451SRussell King 39509b0cdefaSRussell King switch (s->type) { 39519b0cdefaSRussell King case T_REG_32: 39529b0cdefaSRussell King val = readl_relaxed(base + s->offset); 39539b0cdefaSRussell King break; 39549b0cdefaSRussell King case T_REG_64: 39559b0cdefaSRussell King /* Docs say to read low 32-bit then high */ 39569b0cdefaSRussell King low = readl_relaxed(base + s->offset); 39579b0cdefaSRussell King high = readl_relaxed(base + s->offset + 4); 39586d81f451SRussell King val = (u64)high << 32 | low; 39596d81f451SRussell King break; 39606d81f451SRussell King case T_SW: 39616d81f451SRussell King switch (s->offset) { 39626d81f451SRussell King case ETHTOOL_STAT_EEE_WAKEUP: 39636d81f451SRussell King val = phylink_get_eee_err(pp->phylink); 39649b0cdefaSRussell King break; 39659b0cdefaSRussell King } 39666d81f451SRussell King break; 39676d81f451SRussell King } 39686d81f451SRussell King 39696d81f451SRussell King pp->ethtool_stats[i] += val; 39709b0cdefaSRussell King } 39719b0cdefaSRussell King } 39729b0cdefaSRussell King 39739b0cdefaSRussell King static void mvneta_ethtool_get_stats(struct net_device *dev, 39749b0cdefaSRussell King struct ethtool_stats *stats, u64 *data) 39759b0cdefaSRussell King { 39769b0cdefaSRussell King struct mvneta_port *pp = netdev_priv(dev); 39779b0cdefaSRussell King int i; 39789b0cdefaSRussell King 39799b0cdefaSRussell King mvneta_ethtool_update_stats(pp); 39809b0cdefaSRussell King 39819b0cdefaSRussell King for (i = 0; i < ARRAY_SIZE(mvneta_statistics); i++) 39829b0cdefaSRussell King *data++ = pp->ethtool_stats[i]; 39839b0cdefaSRussell King } 39849b0cdefaSRussell King 39859b0cdefaSRussell King static int mvneta_ethtool_get_sset_count(struct net_device *dev, int sset) 39869b0cdefaSRussell King { 39879b0cdefaSRussell King if (sset == ETH_SS_STATS) 39889b0cdefaSRussell King return ARRAY_SIZE(mvneta_statistics); 39899b0cdefaSRussell King return -EOPNOTSUPP; 39909b0cdefaSRussell King } 39919b0cdefaSRussell King 39929a401deaSGregory CLEMENT static u32 mvneta_ethtool_get_rxfh_indir_size(struct net_device *dev) 39939a401deaSGregory CLEMENT { 39949a401deaSGregory CLEMENT return MVNETA_RSS_LU_TABLE_SIZE; 39959a401deaSGregory CLEMENT } 39969a401deaSGregory CLEMENT 39979a401deaSGregory CLEMENT static int mvneta_ethtool_get_rxnfc(struct net_device *dev, 39989a401deaSGregory CLEMENT struct ethtool_rxnfc *info, 39999a401deaSGregory CLEMENT u32 *rules __always_unused) 40009a401deaSGregory CLEMENT { 40019a401deaSGregory CLEMENT switch (info->cmd) { 40029a401deaSGregory CLEMENT case ETHTOOL_GRXRINGS: 40039a401deaSGregory CLEMENT info->data = rxq_number; 40049a401deaSGregory CLEMENT return 0; 40059a401deaSGregory CLEMENT case ETHTOOL_GRXFH: 40069a401deaSGregory CLEMENT return -EOPNOTSUPP; 40079a401deaSGregory CLEMENT default: 40089a401deaSGregory CLEMENT return -EOPNOTSUPP; 40099a401deaSGregory CLEMENT } 40109a401deaSGregory CLEMENT } 40119a401deaSGregory CLEMENT 40129a401deaSGregory CLEMENT static int mvneta_config_rss(struct mvneta_port *pp) 40139a401deaSGregory CLEMENT { 40149a401deaSGregory CLEMENT int cpu; 40159a401deaSGregory CLEMENT u32 val; 40169a401deaSGregory CLEMENT 40179a401deaSGregory CLEMENT netif_tx_stop_all_queues(pp->dev); 40189a401deaSGregory CLEMENT 40196b125d63SGregory CLEMENT on_each_cpu(mvneta_percpu_mask_interrupt, pp, true); 40209a401deaSGregory CLEMENT 40219a401deaSGregory CLEMENT /* We have to synchronise on the napi of each CPU */ 40229a401deaSGregory CLEMENT for_each_online_cpu(cpu) { 40239a401deaSGregory CLEMENT struct mvneta_pcpu_port *pcpu_port = 40249a401deaSGregory CLEMENT per_cpu_ptr(pp->ports, cpu); 40259a401deaSGregory CLEMENT 40269a401deaSGregory CLEMENT napi_synchronize(&pcpu_port->napi); 40279a401deaSGregory CLEMENT napi_disable(&pcpu_port->napi); 40289a401deaSGregory CLEMENT } 40299a401deaSGregory CLEMENT 40309a401deaSGregory CLEMENT pp->rxq_def = pp->indir[0]; 40319a401deaSGregory CLEMENT 40329a401deaSGregory CLEMENT /* Update unicast mapping */ 40339a401deaSGregory CLEMENT mvneta_set_rx_mode(pp->dev); 40349a401deaSGregory CLEMENT 40359a401deaSGregory CLEMENT /* Update val of portCfg register accordingly with all RxQueue types */ 40369a401deaSGregory CLEMENT val = MVNETA_PORT_CONFIG_DEFL_VALUE(pp->rxq_def); 40379a401deaSGregory CLEMENT mvreg_write(pp, MVNETA_PORT_CONFIG, val); 40389a401deaSGregory CLEMENT 40399a401deaSGregory CLEMENT /* Update the elected CPU matching the new rxq_def */ 4040120cfa50SGregory CLEMENT spin_lock(&pp->lock); 40419a401deaSGregory CLEMENT mvneta_percpu_elect(pp); 4042120cfa50SGregory CLEMENT spin_unlock(&pp->lock); 40439a401deaSGregory CLEMENT 40449a401deaSGregory CLEMENT /* We have to synchronise on the napi of each CPU */ 40459a401deaSGregory CLEMENT for_each_online_cpu(cpu) { 40469a401deaSGregory CLEMENT struct mvneta_pcpu_port *pcpu_port = 40479a401deaSGregory CLEMENT per_cpu_ptr(pp->ports, cpu); 40489a401deaSGregory CLEMENT 40499a401deaSGregory CLEMENT napi_enable(&pcpu_port->napi); 40509a401deaSGregory CLEMENT } 40519a401deaSGregory CLEMENT 40529a401deaSGregory CLEMENT netif_tx_start_all_queues(pp->dev); 40539a401deaSGregory CLEMENT 40549a401deaSGregory CLEMENT return 0; 40559a401deaSGregory CLEMENT } 40569a401deaSGregory CLEMENT 40579a401deaSGregory CLEMENT static int mvneta_ethtool_set_rxfh(struct net_device *dev, const u32 *indir, 40589a401deaSGregory CLEMENT const u8 *key, const u8 hfunc) 40599a401deaSGregory CLEMENT { 40609a401deaSGregory CLEMENT struct mvneta_port *pp = netdev_priv(dev); 40612636ac3cSMarcin Wojtas 40622636ac3cSMarcin Wojtas /* Current code for Armada 3700 doesn't support RSS features yet */ 40632636ac3cSMarcin Wojtas if (pp->neta_armada3700) 40642636ac3cSMarcin Wojtas return -EOPNOTSUPP; 40652636ac3cSMarcin Wojtas 40669a401deaSGregory CLEMENT /* We require at least one supported parameter to be changed 40679a401deaSGregory CLEMENT * and no change in any of the unsupported parameters 40689a401deaSGregory CLEMENT */ 40699a401deaSGregory CLEMENT if (key || 40709a401deaSGregory CLEMENT (hfunc != ETH_RSS_HASH_NO_CHANGE && hfunc != ETH_RSS_HASH_TOP)) 40719a401deaSGregory CLEMENT return -EOPNOTSUPP; 40729a401deaSGregory CLEMENT 40739a401deaSGregory CLEMENT if (!indir) 40749a401deaSGregory CLEMENT return 0; 40759a401deaSGregory CLEMENT 40769a401deaSGregory CLEMENT memcpy(pp->indir, indir, MVNETA_RSS_LU_TABLE_SIZE); 40779a401deaSGregory CLEMENT 40789a401deaSGregory CLEMENT return mvneta_config_rss(pp); 40799a401deaSGregory CLEMENT } 40809a401deaSGregory CLEMENT 40819a401deaSGregory CLEMENT static int mvneta_ethtool_get_rxfh(struct net_device *dev, u32 *indir, u8 *key, 40829a401deaSGregory CLEMENT u8 *hfunc) 40839a401deaSGregory CLEMENT { 40849a401deaSGregory CLEMENT struct mvneta_port *pp = netdev_priv(dev); 40859a401deaSGregory CLEMENT 40862636ac3cSMarcin Wojtas /* Current code for Armada 3700 doesn't support RSS features yet */ 40872636ac3cSMarcin Wojtas if (pp->neta_armada3700) 40882636ac3cSMarcin Wojtas return -EOPNOTSUPP; 40892636ac3cSMarcin Wojtas 40909a401deaSGregory CLEMENT if (hfunc) 40919a401deaSGregory CLEMENT *hfunc = ETH_RSS_HASH_TOP; 40929a401deaSGregory CLEMENT 40939a401deaSGregory CLEMENT if (!indir) 40949a401deaSGregory CLEMENT return 0; 40959a401deaSGregory CLEMENT 40969a401deaSGregory CLEMENT memcpy(indir, pp->indir, MVNETA_RSS_LU_TABLE_SIZE); 40979a401deaSGregory CLEMENT 40989a401deaSGregory CLEMENT return 0; 40999a401deaSGregory CLEMENT } 41009a401deaSGregory CLEMENT 4101b60a00f9SJingju Hou static void mvneta_ethtool_get_wol(struct net_device *dev, 4102b60a00f9SJingju Hou struct ethtool_wolinfo *wol) 4103b60a00f9SJingju Hou { 4104503f9aa9SRussell King struct mvneta_port *pp = netdev_priv(dev); 4105b60a00f9SJingju Hou 4106503f9aa9SRussell King phylink_ethtool_get_wol(pp->phylink, wol); 4107b60a00f9SJingju Hou } 4108b60a00f9SJingju Hou 4109b60a00f9SJingju Hou static int mvneta_ethtool_set_wol(struct net_device *dev, 4110b60a00f9SJingju Hou struct ethtool_wolinfo *wol) 4111b60a00f9SJingju Hou { 4112503f9aa9SRussell King struct mvneta_port *pp = netdev_priv(dev); 411382960fffSJisheng Zhang int ret; 411482960fffSJisheng Zhang 4115503f9aa9SRussell King ret = phylink_ethtool_set_wol(pp->phylink, wol); 411682960fffSJisheng Zhang if (!ret) 411782960fffSJisheng Zhang device_set_wakeup_enable(&dev->dev, !!wol->wolopts); 411882960fffSJisheng Zhang 411982960fffSJisheng Zhang return ret; 4120b60a00f9SJingju Hou } 4121b60a00f9SJingju Hou 41226d81f451SRussell King static int mvneta_ethtool_get_eee(struct net_device *dev, 41236d81f451SRussell King struct ethtool_eee *eee) 41246d81f451SRussell King { 41256d81f451SRussell King struct mvneta_port *pp = netdev_priv(dev); 41266d81f451SRussell King u32 lpi_ctl0; 41276d81f451SRussell King 41286d81f451SRussell King lpi_ctl0 = mvreg_read(pp, MVNETA_LPI_CTRL_0); 41296d81f451SRussell King 41306d81f451SRussell King eee->eee_enabled = pp->eee_enabled; 41316d81f451SRussell King eee->eee_active = pp->eee_active; 41326d81f451SRussell King eee->tx_lpi_enabled = pp->tx_lpi_enabled; 41336d81f451SRussell King eee->tx_lpi_timer = (lpi_ctl0) >> 8; // * scale; 41346d81f451SRussell King 41356d81f451SRussell King return phylink_ethtool_get_eee(pp->phylink, eee); 41366d81f451SRussell King } 41376d81f451SRussell King 41386d81f451SRussell King static int mvneta_ethtool_set_eee(struct net_device *dev, 41396d81f451SRussell King struct ethtool_eee *eee) 41406d81f451SRussell King { 41416d81f451SRussell King struct mvneta_port *pp = netdev_priv(dev); 41426d81f451SRussell King u32 lpi_ctl0; 41436d81f451SRussell King 41446d81f451SRussell King /* The Armada 37x documents do not give limits for this other than 41456d81f451SRussell King * it being an 8-bit register. */ 41466d81f451SRussell King if (eee->tx_lpi_enabled && 41476d81f451SRussell King (eee->tx_lpi_timer < 0 || eee->tx_lpi_timer > 255)) 41486d81f451SRussell King return -EINVAL; 41496d81f451SRussell King 41506d81f451SRussell King lpi_ctl0 = mvreg_read(pp, MVNETA_LPI_CTRL_0); 41516d81f451SRussell King lpi_ctl0 &= ~(0xff << 8); 41526d81f451SRussell King lpi_ctl0 |= eee->tx_lpi_timer << 8; 41536d81f451SRussell King mvreg_write(pp, MVNETA_LPI_CTRL_0, lpi_ctl0); 41546d81f451SRussell King 41556d81f451SRussell King pp->eee_enabled = eee->eee_enabled; 41566d81f451SRussell King pp->tx_lpi_enabled = eee->tx_lpi_enabled; 41576d81f451SRussell King 41586d81f451SRussell King mvneta_set_eee(pp, eee->tx_lpi_enabled && eee->eee_enabled); 41596d81f451SRussell King 41606d81f451SRussell King return phylink_ethtool_set_eee(pp->phylink, eee); 41616d81f451SRussell King } 41626d81f451SRussell King 4163c5aff182SThomas Petazzoni static const struct net_device_ops mvneta_netdev_ops = { 4164c5aff182SThomas Petazzoni .ndo_open = mvneta_open, 4165c5aff182SThomas Petazzoni .ndo_stop = mvneta_stop, 4166c5aff182SThomas Petazzoni .ndo_start_xmit = mvneta_tx, 4167c5aff182SThomas Petazzoni .ndo_set_rx_mode = mvneta_set_rx_mode, 4168c5aff182SThomas Petazzoni .ndo_set_mac_address = mvneta_set_mac_addr, 4169c5aff182SThomas Petazzoni .ndo_change_mtu = mvneta_change_mtu, 4170b65657fcSSimon Guinot .ndo_fix_features = mvneta_fix_features, 4171c5aff182SThomas Petazzoni .ndo_get_stats64 = mvneta_get_stats64, 417215f59456SThomas Petazzoni .ndo_do_ioctl = mvneta_ioctl, 4173c5aff182SThomas Petazzoni }; 4174c5aff182SThomas Petazzoni 41754581be42SJisheng Zhang static const struct ethtool_ops mvneta_eth_tool_ops = { 4176503f9aa9SRussell King .nway_reset = mvneta_ethtool_nway_reset, 4177c5aff182SThomas Petazzoni .get_link = ethtool_op_get_link, 4178c5aff182SThomas Petazzoni .set_coalesce = mvneta_ethtool_set_coalesce, 4179c5aff182SThomas Petazzoni .get_coalesce = mvneta_ethtool_get_coalesce, 4180c5aff182SThomas Petazzoni .get_drvinfo = mvneta_ethtool_get_drvinfo, 4181c5aff182SThomas Petazzoni .get_ringparam = mvneta_ethtool_get_ringparam, 4182c5aff182SThomas Petazzoni .set_ringparam = mvneta_ethtool_set_ringparam, 41834932a918SRussell King .get_pauseparam = mvneta_ethtool_get_pauseparam, 41844932a918SRussell King .set_pauseparam = mvneta_ethtool_set_pauseparam, 41859b0cdefaSRussell King .get_strings = mvneta_ethtool_get_strings, 41869b0cdefaSRussell King .get_ethtool_stats = mvneta_ethtool_get_stats, 41879b0cdefaSRussell King .get_sset_count = mvneta_ethtool_get_sset_count, 41889a401deaSGregory CLEMENT .get_rxfh_indir_size = mvneta_ethtool_get_rxfh_indir_size, 41899a401deaSGregory CLEMENT .get_rxnfc = mvneta_ethtool_get_rxnfc, 41909a401deaSGregory CLEMENT .get_rxfh = mvneta_ethtool_get_rxfh, 41919a401deaSGregory CLEMENT .set_rxfh = mvneta_ethtool_set_rxfh, 4192503f9aa9SRussell King .get_link_ksettings = mvneta_ethtool_get_link_ksettings, 4193013ad40dSPhilippe Reynes .set_link_ksettings = mvneta_ethtool_set_link_ksettings, 4194b60a00f9SJingju Hou .get_wol = mvneta_ethtool_get_wol, 4195b60a00f9SJingju Hou .set_wol = mvneta_ethtool_set_wol, 41966d81f451SRussell King .get_eee = mvneta_ethtool_get_eee, 41976d81f451SRussell King .set_eee = mvneta_ethtool_set_eee, 4198c5aff182SThomas Petazzoni }; 4199c5aff182SThomas Petazzoni 4200c5aff182SThomas Petazzoni /* Initialize hw */ 42019672850bSEzequiel Garcia static int mvneta_init(struct device *dev, struct mvneta_port *pp) 4202c5aff182SThomas Petazzoni { 4203c5aff182SThomas Petazzoni int queue; 4204c5aff182SThomas Petazzoni 4205c5aff182SThomas Petazzoni /* Disable port */ 4206c5aff182SThomas Petazzoni mvneta_port_disable(pp); 4207c5aff182SThomas Petazzoni 4208c5aff182SThomas Petazzoni /* Set port default values */ 4209c5aff182SThomas Petazzoni mvneta_defaults_set(pp); 4210c5aff182SThomas Petazzoni 42115d6312edSMarkus Elfring pp->txqs = devm_kcalloc(dev, txq_number, sizeof(*pp->txqs), GFP_KERNEL); 4212c5aff182SThomas Petazzoni if (!pp->txqs) 4213c5aff182SThomas Petazzoni return -ENOMEM; 4214c5aff182SThomas Petazzoni 4215c5aff182SThomas Petazzoni /* Initialize TX descriptor rings */ 4216c5aff182SThomas Petazzoni for (queue = 0; queue < txq_number; queue++) { 4217c5aff182SThomas Petazzoni struct mvneta_tx_queue *txq = &pp->txqs[queue]; 4218c5aff182SThomas Petazzoni txq->id = queue; 4219c5aff182SThomas Petazzoni txq->size = pp->tx_ring_size; 4220c5aff182SThomas Petazzoni txq->done_pkts_coal = MVNETA_TXDONE_COAL_PKTS; 4221c5aff182SThomas Petazzoni } 4222c5aff182SThomas Petazzoni 42235d6312edSMarkus Elfring pp->rxqs = devm_kcalloc(dev, rxq_number, sizeof(*pp->rxqs), GFP_KERNEL); 42249672850bSEzequiel Garcia if (!pp->rxqs) 4225c5aff182SThomas Petazzoni return -ENOMEM; 4226c5aff182SThomas Petazzoni 4227c5aff182SThomas Petazzoni /* Create Rx descriptor rings */ 4228c5aff182SThomas Petazzoni for (queue = 0; queue < rxq_number; queue++) { 4229c5aff182SThomas Petazzoni struct mvneta_rx_queue *rxq = &pp->rxqs[queue]; 4230c5aff182SThomas Petazzoni rxq->id = queue; 4231c5aff182SThomas Petazzoni rxq->size = pp->rx_ring_size; 4232c5aff182SThomas Petazzoni rxq->pkts_coal = MVNETA_RX_COAL_PKTS; 4233c5aff182SThomas Petazzoni rxq->time_coal = MVNETA_RX_COAL_USEC; 423429110630SMarkus Elfring rxq->buf_virt_addr 423529110630SMarkus Elfring = devm_kmalloc_array(pp->dev->dev.parent, 423629110630SMarkus Elfring rxq->size, 423729110630SMarkus Elfring sizeof(*rxq->buf_virt_addr), 4238f88bee1cSGregory CLEMENT GFP_KERNEL); 4239f88bee1cSGregory CLEMENT if (!rxq->buf_virt_addr) 4240f88bee1cSGregory CLEMENT return -ENOMEM; 4241c5aff182SThomas Petazzoni } 4242c5aff182SThomas Petazzoni 4243c5aff182SThomas Petazzoni return 0; 4244c5aff182SThomas Petazzoni } 4245c5aff182SThomas Petazzoni 4246c5aff182SThomas Petazzoni /* platform glue : initialize decoding windows */ 424703ce758eSGreg KH static void mvneta_conf_mbus_windows(struct mvneta_port *pp, 4248c5aff182SThomas Petazzoni const struct mbus_dram_target_info *dram) 4249c5aff182SThomas Petazzoni { 4250c5aff182SThomas Petazzoni u32 win_enable; 4251c5aff182SThomas Petazzoni u32 win_protect; 4252c5aff182SThomas Petazzoni int i; 4253c5aff182SThomas Petazzoni 4254c5aff182SThomas Petazzoni for (i = 0; i < 6; i++) { 4255c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_WIN_BASE(i), 0); 4256c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_WIN_SIZE(i), 0); 4257c5aff182SThomas Petazzoni 4258c5aff182SThomas Petazzoni if (i < 4) 4259c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_WIN_REMAP(i), 0); 4260c5aff182SThomas Petazzoni } 4261c5aff182SThomas Petazzoni 4262c5aff182SThomas Petazzoni win_enable = 0x3f; 4263c5aff182SThomas Petazzoni win_protect = 0; 4264c5aff182SThomas Petazzoni 42652636ac3cSMarcin Wojtas if (dram) { 4266c5aff182SThomas Petazzoni for (i = 0; i < dram->num_cs; i++) { 4267c5aff182SThomas Petazzoni const struct mbus_dram_window *cs = dram->cs + i; 42682636ac3cSMarcin Wojtas 42692636ac3cSMarcin Wojtas mvreg_write(pp, MVNETA_WIN_BASE(i), 42702636ac3cSMarcin Wojtas (cs->base & 0xffff0000) | 42712636ac3cSMarcin Wojtas (cs->mbus_attr << 8) | 42722636ac3cSMarcin Wojtas dram->mbus_dram_target_id); 4273c5aff182SThomas Petazzoni 4274c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_WIN_SIZE(i), 4275c5aff182SThomas Petazzoni (cs->size - 1) & 0xffff0000); 4276c5aff182SThomas Petazzoni 4277c5aff182SThomas Petazzoni win_enable &= ~(1 << i); 4278c5aff182SThomas Petazzoni win_protect |= 3 << (2 * i); 4279c5aff182SThomas Petazzoni } 42802636ac3cSMarcin Wojtas } else { 42812636ac3cSMarcin Wojtas /* For Armada3700 open default 4GB Mbus window, leaving 42822636ac3cSMarcin Wojtas * arbitration of target/attribute to a different layer 42832636ac3cSMarcin Wojtas * of configuration. 42842636ac3cSMarcin Wojtas */ 42852636ac3cSMarcin Wojtas mvreg_write(pp, MVNETA_WIN_SIZE(0), 0xffff0000); 42862636ac3cSMarcin Wojtas win_enable &= ~BIT(0); 42872636ac3cSMarcin Wojtas win_protect = 3; 42882636ac3cSMarcin Wojtas } 4289c5aff182SThomas Petazzoni 4290c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_BASE_ADDR_ENABLE, win_enable); 4291db6ba9a5SMarcin Wojtas mvreg_write(pp, MVNETA_ACCESS_PROTECT_ENABLE, win_protect); 4292c5aff182SThomas Petazzoni } 4293c5aff182SThomas Petazzoni 4294c5aff182SThomas Petazzoni /* Power up the port */ 42953f1dd4bcSThomas Petazzoni static int mvneta_port_power_up(struct mvneta_port *pp, int phy_mode) 4296c5aff182SThomas Petazzoni { 4297c5aff182SThomas Petazzoni /* MAC Cause register should be cleared */ 4298c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_UNIT_INTR_CAUSE, 0); 4299c5aff182SThomas Petazzoni 430032699954SRussell King if (phy_mode == PHY_INTERFACE_MODE_QSGMII) 43013f1dd4bcSThomas Petazzoni mvreg_write(pp, MVNETA_SERDES_CFG, MVNETA_QSGMII_SERDES_PROTO); 430222f4bf8aSRussell King else if (phy_mode == PHY_INTERFACE_MODE_SGMII || 430322f4bf8aSRussell King phy_mode == PHY_INTERFACE_MODE_1000BASEX) 43043f1dd4bcSThomas Petazzoni mvreg_write(pp, MVNETA_SERDES_CFG, MVNETA_SGMII_SERDES_PROTO); 430532699954SRussell King else if (!phy_interface_mode_is_rgmii(phy_mode)) 43063f1dd4bcSThomas Petazzoni return -EINVAL; 43073f1dd4bcSThomas Petazzoni 43083f1dd4bcSThomas Petazzoni return 0; 4309c5aff182SThomas Petazzoni } 4310c5aff182SThomas Petazzoni 4311c5aff182SThomas Petazzoni /* Device initialization routine */ 431203ce758eSGreg KH static int mvneta_probe(struct platform_device *pdev) 4313c5aff182SThomas Petazzoni { 4314c3f0dd38SThomas Petazzoni struct resource *res; 4315c5aff182SThomas Petazzoni struct device_node *dn = pdev->dev.of_node; 4316dc35a10fSMarcin Wojtas struct device_node *bm_node; 4317c5aff182SThomas Petazzoni struct mvneta_port *pp; 4318c5aff182SThomas Petazzoni struct net_device *dev; 4319503f9aa9SRussell King struct phylink *phylink; 43208cc3e439SThomas Petazzoni const char *dt_mac_addr; 43218cc3e439SThomas Petazzoni char hw_mac_addr[ETH_ALEN]; 43228cc3e439SThomas Petazzoni const char *mac_from; 43239110ee07SMarcin Wojtas int tx_csum_limit; 4324c5aff182SThomas Petazzoni int phy_mode; 4325c5aff182SThomas Petazzoni int err; 432612bb03b4SMaxime Ripard int cpu; 4327c5aff182SThomas Petazzoni 4328ee40a116SWilly Tarreau dev = alloc_etherdev_mqs(sizeof(struct mvneta_port), txq_number, rxq_number); 4329c5aff182SThomas Petazzoni if (!dev) 4330c5aff182SThomas Petazzoni return -ENOMEM; 4331c5aff182SThomas Petazzoni 4332c5aff182SThomas Petazzoni dev->irq = irq_of_parse_and_map(dn, 0); 4333c5aff182SThomas Petazzoni if (dev->irq == 0) { 4334c5aff182SThomas Petazzoni err = -EINVAL; 4335c5aff182SThomas Petazzoni goto err_free_netdev; 4336c5aff182SThomas Petazzoni } 4337c5aff182SThomas Petazzoni 4338c5aff182SThomas Petazzoni phy_mode = of_get_phy_mode(dn); 4339c5aff182SThomas Petazzoni if (phy_mode < 0) { 4340c5aff182SThomas Petazzoni dev_err(&pdev->dev, "incorrect phy-mode\n"); 4341c5aff182SThomas Petazzoni err = -EINVAL; 4342503f9aa9SRussell King goto err_free_irq; 4343503f9aa9SRussell King } 4344503f9aa9SRussell King 4345503f9aa9SRussell King phylink = phylink_create(dev, pdev->dev.fwnode, phy_mode, 4346503f9aa9SRussell King &mvneta_phylink_ops); 4347503f9aa9SRussell King if (IS_ERR(phylink)) { 4348503f9aa9SRussell King err = PTR_ERR(phylink); 4349503f9aa9SRussell King goto err_free_irq; 4350c5aff182SThomas Petazzoni } 4351c5aff182SThomas Petazzoni 4352c5aff182SThomas Petazzoni dev->tx_queue_len = MVNETA_MAX_TXD; 4353c5aff182SThomas Petazzoni dev->watchdog_timeo = 5 * HZ; 4354c5aff182SThomas Petazzoni dev->netdev_ops = &mvneta_netdev_ops; 4355c5aff182SThomas Petazzoni 43567ad24ea4SWilfried Klaebe dev->ethtool_ops = &mvneta_eth_tool_ops; 4357c5aff182SThomas Petazzoni 4358c5aff182SThomas Petazzoni pp = netdev_priv(dev); 43591c2722a9SGregory CLEMENT spin_lock_init(&pp->lock); 4360503f9aa9SRussell King pp->phylink = phylink; 4361c5aff182SThomas Petazzoni pp->phy_interface = phy_mode; 4362503f9aa9SRussell King pp->dn = dn; 4363c5aff182SThomas Petazzoni 436490b74c01SGregory CLEMENT pp->rxq_def = rxq_def; 436590b74c01SGregory CLEMENT 43668d5047cfSMarcin Wojtas /* Set RX packet offset correction for platforms, whose 43678d5047cfSMarcin Wojtas * NET_SKB_PAD, exceeds 64B. It should be 64B for 64-bit 43688d5047cfSMarcin Wojtas * platforms and 0B for 32-bit ones. 43698d5047cfSMarcin Wojtas */ 43708d5047cfSMarcin Wojtas pp->rx_offset_correction = 43718d5047cfSMarcin Wojtas max(0, NET_SKB_PAD - MVNETA_RX_PKT_OFFSET_CORRECTION); 43728d5047cfSMarcin Wojtas 43739a401deaSGregory CLEMENT pp->indir[0] = rxq_def; 43749a401deaSGregory CLEMENT 43752636ac3cSMarcin Wojtas /* Get special SoC configurations */ 43762636ac3cSMarcin Wojtas if (of_device_is_compatible(dn, "marvell,armada-3700-neta")) 43772636ac3cSMarcin Wojtas pp->neta_armada3700 = true; 43782636ac3cSMarcin Wojtas 43792804ba4eSJisheng Zhang pp->clk = devm_clk_get(&pdev->dev, "core"); 43802804ba4eSJisheng Zhang if (IS_ERR(pp->clk)) 4381189dd626SThomas Petazzoni pp->clk = devm_clk_get(&pdev->dev, NULL); 4382189dd626SThomas Petazzoni if (IS_ERR(pp->clk)) { 4383189dd626SThomas Petazzoni err = PTR_ERR(pp->clk); 4384503f9aa9SRussell King goto err_free_phylink; 4385189dd626SThomas Petazzoni } 4386189dd626SThomas Petazzoni 4387189dd626SThomas Petazzoni clk_prepare_enable(pp->clk); 4388189dd626SThomas Petazzoni 438915cc4a4aSJisheng Zhang pp->clk_bus = devm_clk_get(&pdev->dev, "bus"); 439015cc4a4aSJisheng Zhang if (!IS_ERR(pp->clk_bus)) 439115cc4a4aSJisheng Zhang clk_prepare_enable(pp->clk_bus); 439215cc4a4aSJisheng Zhang 4393c3f0dd38SThomas Petazzoni res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 4394c3f0dd38SThomas Petazzoni pp->base = devm_ioremap_resource(&pdev->dev, res); 4395c3f0dd38SThomas Petazzoni if (IS_ERR(pp->base)) { 4396c3f0dd38SThomas Petazzoni err = PTR_ERR(pp->base); 43975445eaf3SArnaud Patard \(Rtp\) goto err_clk; 43985445eaf3SArnaud Patard \(Rtp\) } 43995445eaf3SArnaud Patard \(Rtp\) 440012bb03b4SMaxime Ripard /* Alloc per-cpu port structure */ 440112bb03b4SMaxime Ripard pp->ports = alloc_percpu(struct mvneta_pcpu_port); 440212bb03b4SMaxime Ripard if (!pp->ports) { 440312bb03b4SMaxime Ripard err = -ENOMEM; 440412bb03b4SMaxime Ripard goto err_clk; 440512bb03b4SMaxime Ripard } 440612bb03b4SMaxime Ripard 440774c41b04Swilly tarreau /* Alloc per-cpu stats */ 44081c213bd2SWANG Cong pp->stats = netdev_alloc_pcpu_stats(struct mvneta_pcpu_stats); 440974c41b04Swilly tarreau if (!pp->stats) { 441074c41b04Swilly tarreau err = -ENOMEM; 441112bb03b4SMaxime Ripard goto err_free_ports; 441274c41b04Swilly tarreau } 441374c41b04Swilly tarreau 44148cc3e439SThomas Petazzoni dt_mac_addr = of_get_mac_address(dn); 44156c7a9a3cSLuka Perkov if (dt_mac_addr) { 44168cc3e439SThomas Petazzoni mac_from = "device tree"; 44178cc3e439SThomas Petazzoni memcpy(dev->dev_addr, dt_mac_addr, ETH_ALEN); 44188cc3e439SThomas Petazzoni } else { 44198cc3e439SThomas Petazzoni mvneta_get_mac_addr(pp, hw_mac_addr); 44208cc3e439SThomas Petazzoni if (is_valid_ether_addr(hw_mac_addr)) { 44218cc3e439SThomas Petazzoni mac_from = "hardware"; 44228cc3e439SThomas Petazzoni memcpy(dev->dev_addr, hw_mac_addr, ETH_ALEN); 44238cc3e439SThomas Petazzoni } else { 44248cc3e439SThomas Petazzoni mac_from = "random"; 44258cc3e439SThomas Petazzoni eth_hw_addr_random(dev); 44268cc3e439SThomas Petazzoni } 44278cc3e439SThomas Petazzoni } 44288cc3e439SThomas Petazzoni 44299110ee07SMarcin Wojtas if (!of_property_read_u32(dn, "tx-csum-limit", &tx_csum_limit)) { 44309110ee07SMarcin Wojtas if (tx_csum_limit < 0 || 44319110ee07SMarcin Wojtas tx_csum_limit > MVNETA_TX_CSUM_MAX_SIZE) { 44329110ee07SMarcin Wojtas tx_csum_limit = MVNETA_TX_CSUM_DEF_SIZE; 44339110ee07SMarcin Wojtas dev_info(&pdev->dev, 44349110ee07SMarcin Wojtas "Wrong TX csum limit in DT, set to %dB\n", 44359110ee07SMarcin Wojtas MVNETA_TX_CSUM_DEF_SIZE); 44369110ee07SMarcin Wojtas } 44379110ee07SMarcin Wojtas } else if (of_device_is_compatible(dn, "marvell,armada-370-neta")) { 44389110ee07SMarcin Wojtas tx_csum_limit = MVNETA_TX_CSUM_DEF_SIZE; 44399110ee07SMarcin Wojtas } else { 44409110ee07SMarcin Wojtas tx_csum_limit = MVNETA_TX_CSUM_MAX_SIZE; 44419110ee07SMarcin Wojtas } 44429110ee07SMarcin Wojtas 44439110ee07SMarcin Wojtas pp->tx_csum_limit = tx_csum_limit; 4444b65657fcSSimon Guinot 44459768b45cSJane Li pp->dram_target_info = mv_mbus_dram_info(); 44462636ac3cSMarcin Wojtas /* Armada3700 requires setting default configuration of Mbus 44472636ac3cSMarcin Wojtas * windows, however without using filled mbus_dram_target_info 44482636ac3cSMarcin Wojtas * structure. 44492636ac3cSMarcin Wojtas */ 44509768b45cSJane Li if (pp->dram_target_info || pp->neta_armada3700) 44519768b45cSJane Li mvneta_conf_mbus_windows(pp, pp->dram_target_info); 4452dc35a10fSMarcin Wojtas 4453c5aff182SThomas Petazzoni pp->tx_ring_size = MVNETA_MAX_TXD; 4454c5aff182SThomas Petazzoni pp->rx_ring_size = MVNETA_MAX_RXD; 4455c5aff182SThomas Petazzoni 4456c5aff182SThomas Petazzoni pp->dev = dev; 4457c5aff182SThomas Petazzoni SET_NETDEV_DEV(dev, &pdev->dev); 4458c5aff182SThomas Petazzoni 4459dc35a10fSMarcin Wojtas pp->id = global_port_id++; 4460dc35a10fSMarcin Wojtas 4461dc35a10fSMarcin Wojtas /* Obtain access to BM resources if enabled and already initialized */ 4462dc35a10fSMarcin Wojtas bm_node = of_parse_phandle(dn, "buffer-manager", 0); 4463dc35a10fSMarcin Wojtas if (bm_node && bm_node->data) { 4464dc35a10fSMarcin Wojtas pp->bm_priv = bm_node->data; 4465dc35a10fSMarcin Wojtas err = mvneta_bm_port_init(pdev, pp); 4466dc35a10fSMarcin Wojtas if (err < 0) { 4467dc35a10fSMarcin Wojtas dev_info(&pdev->dev, "use SW buffer management\n"); 4468dc35a10fSMarcin Wojtas pp->bm_priv = NULL; 4469dc35a10fSMarcin Wojtas } 4470dc35a10fSMarcin Wojtas } 4471d4e4da00SPeter Chen of_node_put(bm_node); 4472dc35a10fSMarcin Wojtas 44739672850bSEzequiel Garcia err = mvneta_init(&pdev->dev, pp); 44749672850bSEzequiel Garcia if (err < 0) 4475dc35a10fSMarcin Wojtas goto err_netdev; 44763f1dd4bcSThomas Petazzoni 44773f1dd4bcSThomas Petazzoni err = mvneta_port_power_up(pp, phy_mode); 44783f1dd4bcSThomas Petazzoni if (err < 0) { 44793f1dd4bcSThomas Petazzoni dev_err(&pdev->dev, "can't power up port\n"); 4480dc35a10fSMarcin Wojtas goto err_netdev; 44813f1dd4bcSThomas Petazzoni } 4482c5aff182SThomas Petazzoni 44832636ac3cSMarcin Wojtas /* Armada3700 network controller does not support per-cpu 44842636ac3cSMarcin Wojtas * operation, so only single NAPI should be initialized. 44852636ac3cSMarcin Wojtas */ 44862636ac3cSMarcin Wojtas if (pp->neta_armada3700) { 44872636ac3cSMarcin Wojtas netif_napi_add(dev, &pp->napi, mvneta_poll, NAPI_POLL_WEIGHT); 44882636ac3cSMarcin Wojtas } else { 448912bb03b4SMaxime Ripard for_each_present_cpu(cpu) { 44902636ac3cSMarcin Wojtas struct mvneta_pcpu_port *port = 44912636ac3cSMarcin Wojtas per_cpu_ptr(pp->ports, cpu); 449212bb03b4SMaxime Ripard 44932636ac3cSMarcin Wojtas netif_napi_add(dev, &port->napi, mvneta_poll, 44942636ac3cSMarcin Wojtas NAPI_POLL_WEIGHT); 449512bb03b4SMaxime Ripard port->pp = pp; 449612bb03b4SMaxime Ripard } 44972636ac3cSMarcin Wojtas } 4498c5aff182SThomas Petazzoni 4499c54a5048SAndrew Pilloud dev->features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_TSO; 450001ef26caSEzequiel Garcia dev->hw_features |= dev->features; 450101ef26caSEzequiel Garcia dev->vlan_features |= dev->features; 450297db8afaSAndrew Lunn dev->priv_flags |= IFF_LIVE_ADDR_CHANGE; 45038eef5f97SEzequiel Garcia dev->gso_max_segs = MVNETA_MAX_TSO_SEGS; 4504b50b72deSwilly tarreau 45055777987eSJarod Wilson /* MTU range: 68 - 9676 */ 45065777987eSJarod Wilson dev->min_mtu = ETH_MIN_MTU; 45075777987eSJarod Wilson /* 9676 == 9700 - 20 and rounding to 8 */ 45085777987eSJarod Wilson dev->max_mtu = 9676; 45095777987eSJarod Wilson 4510c5aff182SThomas Petazzoni err = register_netdev(dev); 4511c5aff182SThomas Petazzoni if (err < 0) { 4512c5aff182SThomas Petazzoni dev_err(&pdev->dev, "failed to register\n"); 45139672850bSEzequiel Garcia goto err_free_stats; 4514c5aff182SThomas Petazzoni } 4515c5aff182SThomas Petazzoni 45168cc3e439SThomas Petazzoni netdev_info(dev, "Using %s mac address %pM\n", mac_from, 45178cc3e439SThomas Petazzoni dev->dev_addr); 4518c5aff182SThomas Petazzoni 4519c5aff182SThomas Petazzoni platform_set_drvdata(pdev, pp->dev); 4520c5aff182SThomas Petazzoni 4521c5aff182SThomas Petazzoni return 0; 4522c5aff182SThomas Petazzoni 4523dc35a10fSMarcin Wojtas err_netdev: 4524dc35a10fSMarcin Wojtas unregister_netdev(dev); 4525dc35a10fSMarcin Wojtas if (pp->bm_priv) { 4526dc35a10fSMarcin Wojtas mvneta_bm_pool_destroy(pp->bm_priv, pp->pool_long, 1 << pp->id); 4527dc35a10fSMarcin Wojtas mvneta_bm_pool_destroy(pp->bm_priv, pp->pool_short, 4528dc35a10fSMarcin Wojtas 1 << pp->id); 4529dc35a10fSMarcin Wojtas } 453074c41b04Swilly tarreau err_free_stats: 453174c41b04Swilly tarreau free_percpu(pp->stats); 453212bb03b4SMaxime Ripard err_free_ports: 453312bb03b4SMaxime Ripard free_percpu(pp->ports); 45345445eaf3SArnaud Patard \(Rtp\) err_clk: 453515cc4a4aSJisheng Zhang clk_disable_unprepare(pp->clk_bus); 45365445eaf3SArnaud Patard \(Rtp\) clk_disable_unprepare(pp->clk); 4537503f9aa9SRussell King err_free_phylink: 4538503f9aa9SRussell King if (pp->phylink) 4539503f9aa9SRussell King phylink_destroy(pp->phylink); 4540c5aff182SThomas Petazzoni err_free_irq: 4541c5aff182SThomas Petazzoni irq_dispose_mapping(dev->irq); 4542c5aff182SThomas Petazzoni err_free_netdev: 4543c5aff182SThomas Petazzoni free_netdev(dev); 4544c5aff182SThomas Petazzoni return err; 4545c5aff182SThomas Petazzoni } 4546c5aff182SThomas Petazzoni 4547c5aff182SThomas Petazzoni /* Device removal routine */ 454803ce758eSGreg KH static int mvneta_remove(struct platform_device *pdev) 4549c5aff182SThomas Petazzoni { 4550c5aff182SThomas Petazzoni struct net_device *dev = platform_get_drvdata(pdev); 4551c5aff182SThomas Petazzoni struct mvneta_port *pp = netdev_priv(dev); 4552c5aff182SThomas Petazzoni 4553c5aff182SThomas Petazzoni unregister_netdev(dev); 455415cc4a4aSJisheng Zhang clk_disable_unprepare(pp->clk_bus); 4555189dd626SThomas Petazzoni clk_disable_unprepare(pp->clk); 455612bb03b4SMaxime Ripard free_percpu(pp->ports); 455774c41b04Swilly tarreau free_percpu(pp->stats); 4558c5aff182SThomas Petazzoni irq_dispose_mapping(dev->irq); 4559503f9aa9SRussell King phylink_destroy(pp->phylink); 4560c5aff182SThomas Petazzoni free_netdev(dev); 4561c5aff182SThomas Petazzoni 4562dc35a10fSMarcin Wojtas if (pp->bm_priv) { 4563dc35a10fSMarcin Wojtas mvneta_bm_pool_destroy(pp->bm_priv, pp->pool_long, 1 << pp->id); 4564dc35a10fSMarcin Wojtas mvneta_bm_pool_destroy(pp->bm_priv, pp->pool_short, 4565dc35a10fSMarcin Wojtas 1 << pp->id); 4566dc35a10fSMarcin Wojtas } 4567dc35a10fSMarcin Wojtas 4568c5aff182SThomas Petazzoni return 0; 4569c5aff182SThomas Petazzoni } 4570c5aff182SThomas Petazzoni 45719768b45cSJane Li #ifdef CONFIG_PM_SLEEP 45729768b45cSJane Li static int mvneta_suspend(struct device *device) 45739768b45cSJane Li { 45741799cdd2SJisheng Zhang int queue; 45759768b45cSJane Li struct net_device *dev = dev_get_drvdata(device); 45769768b45cSJane Li struct mvneta_port *pp = netdev_priv(dev); 45779768b45cSJane Li 45781799cdd2SJisheng Zhang if (!netif_running(dev)) 45791799cdd2SJisheng Zhang goto clean_exit; 45801799cdd2SJisheng Zhang 45811799cdd2SJisheng Zhang if (!pp->neta_armada3700) { 45821799cdd2SJisheng Zhang spin_lock(&pp->lock); 45831799cdd2SJisheng Zhang pp->is_stopped = true; 45841799cdd2SJisheng Zhang spin_unlock(&pp->lock); 45851799cdd2SJisheng Zhang 45861799cdd2SJisheng Zhang cpuhp_state_remove_instance_nocalls(online_hpstate, 45871799cdd2SJisheng Zhang &pp->node_online); 45881799cdd2SJisheng Zhang cpuhp_state_remove_instance_nocalls(CPUHP_NET_MVNETA_DEAD, 45891799cdd2SJisheng Zhang &pp->node_dead); 45901799cdd2SJisheng Zhang } 45911799cdd2SJisheng Zhang 45923b8bc674SRussell King rtnl_lock(); 45931799cdd2SJisheng Zhang mvneta_stop_dev(pp); 45943b8bc674SRussell King rtnl_unlock(); 45951799cdd2SJisheng Zhang 45961799cdd2SJisheng Zhang for (queue = 0; queue < rxq_number; queue++) { 45971799cdd2SJisheng Zhang struct mvneta_rx_queue *rxq = &pp->rxqs[queue]; 45981799cdd2SJisheng Zhang 45991799cdd2SJisheng Zhang mvneta_rxq_drop_pkts(pp, rxq); 46001799cdd2SJisheng Zhang } 46011799cdd2SJisheng Zhang 46021799cdd2SJisheng Zhang for (queue = 0; queue < txq_number; queue++) { 46031799cdd2SJisheng Zhang struct mvneta_tx_queue *txq = &pp->txqs[queue]; 46041799cdd2SJisheng Zhang 46051799cdd2SJisheng Zhang mvneta_txq_hw_deinit(pp, txq); 46061799cdd2SJisheng Zhang } 46071799cdd2SJisheng Zhang 46081799cdd2SJisheng Zhang clean_exit: 46099768b45cSJane Li netif_device_detach(dev); 46109768b45cSJane Li clk_disable_unprepare(pp->clk_bus); 46119768b45cSJane Li clk_disable_unprepare(pp->clk); 46121799cdd2SJisheng Zhang 46139768b45cSJane Li return 0; 46149768b45cSJane Li } 46159768b45cSJane Li 46169768b45cSJane Li static int mvneta_resume(struct device *device) 46179768b45cSJane Li { 46189768b45cSJane Li struct platform_device *pdev = to_platform_device(device); 46199768b45cSJane Li struct net_device *dev = dev_get_drvdata(device); 46209768b45cSJane Li struct mvneta_port *pp = netdev_priv(dev); 46211799cdd2SJisheng Zhang int err, queue; 46229768b45cSJane Li 46239768b45cSJane Li clk_prepare_enable(pp->clk); 46249768b45cSJane Li if (!IS_ERR(pp->clk_bus)) 46259768b45cSJane Li clk_prepare_enable(pp->clk_bus); 46269768b45cSJane Li if (pp->dram_target_info || pp->neta_armada3700) 46279768b45cSJane Li mvneta_conf_mbus_windows(pp, pp->dram_target_info); 46289768b45cSJane Li if (pp->bm_priv) { 46299768b45cSJane Li err = mvneta_bm_port_init(pdev, pp); 46309768b45cSJane Li if (err < 0) { 46319768b45cSJane Li dev_info(&pdev->dev, "use SW buffer management\n"); 46329768b45cSJane Li pp->bm_priv = NULL; 46339768b45cSJane Li } 46349768b45cSJane Li } 46359768b45cSJane Li mvneta_defaults_set(pp); 46369768b45cSJane Li err = mvneta_port_power_up(pp, pp->phy_interface); 46379768b45cSJane Li if (err < 0) { 46389768b45cSJane Li dev_err(device, "can't power up port\n"); 46399768b45cSJane Li return err; 46409768b45cSJane Li } 46419768b45cSJane Li 46429768b45cSJane Li netif_device_attach(dev); 46431799cdd2SJisheng Zhang 46441799cdd2SJisheng Zhang if (!netif_running(dev)) 46451799cdd2SJisheng Zhang return 0; 46461799cdd2SJisheng Zhang 46471799cdd2SJisheng Zhang for (queue = 0; queue < rxq_number; queue++) { 46481799cdd2SJisheng Zhang struct mvneta_rx_queue *rxq = &pp->rxqs[queue]; 46491799cdd2SJisheng Zhang 46501799cdd2SJisheng Zhang rxq->next_desc_to_proc = 0; 46511799cdd2SJisheng Zhang mvneta_rxq_hw_init(pp, rxq); 4652d6956ac8SJisheng Zhang } 46531799cdd2SJisheng Zhang 46541799cdd2SJisheng Zhang for (queue = 0; queue < txq_number; queue++) { 46551799cdd2SJisheng Zhang struct mvneta_tx_queue *txq = &pp->txqs[queue]; 46561799cdd2SJisheng Zhang 46571799cdd2SJisheng Zhang txq->next_desc_to_proc = 0; 46581799cdd2SJisheng Zhang mvneta_txq_hw_init(pp, txq); 46591799cdd2SJisheng Zhang } 46601799cdd2SJisheng Zhang 46611799cdd2SJisheng Zhang if (!pp->neta_armada3700) { 46621799cdd2SJisheng Zhang spin_lock(&pp->lock); 46631799cdd2SJisheng Zhang pp->is_stopped = false; 46641799cdd2SJisheng Zhang spin_unlock(&pp->lock); 46651799cdd2SJisheng Zhang cpuhp_state_add_instance_nocalls(online_hpstate, 46661799cdd2SJisheng Zhang &pp->node_online); 46671799cdd2SJisheng Zhang cpuhp_state_add_instance_nocalls(CPUHP_NET_MVNETA_DEAD, 46681799cdd2SJisheng Zhang &pp->node_dead); 46691799cdd2SJisheng Zhang } 46701799cdd2SJisheng Zhang 46711799cdd2SJisheng Zhang rtnl_lock(); 46721799cdd2SJisheng Zhang mvneta_start_dev(pp); 46733b8bc674SRussell King rtnl_unlock(); 46741799cdd2SJisheng Zhang mvneta_set_rx_mode(dev); 4675d6956ac8SJisheng Zhang 46769768b45cSJane Li return 0; 46779768b45cSJane Li } 46789768b45cSJane Li #endif 46799768b45cSJane Li 46809768b45cSJane Li static SIMPLE_DEV_PM_OPS(mvneta_pm_ops, mvneta_suspend, mvneta_resume); 46819768b45cSJane Li 4682c5aff182SThomas Petazzoni static const struct of_device_id mvneta_match[] = { 4683c5aff182SThomas Petazzoni { .compatible = "marvell,armada-370-neta" }, 4684f522a975SSimon Guinot { .compatible = "marvell,armada-xp-neta" }, 46852636ac3cSMarcin Wojtas { .compatible = "marvell,armada-3700-neta" }, 4686c5aff182SThomas Petazzoni { } 4687c5aff182SThomas Petazzoni }; 4688c5aff182SThomas Petazzoni MODULE_DEVICE_TABLE(of, mvneta_match); 4689c5aff182SThomas Petazzoni 4690c5aff182SThomas Petazzoni static struct platform_driver mvneta_driver = { 4691c5aff182SThomas Petazzoni .probe = mvneta_probe, 469203ce758eSGreg KH .remove = mvneta_remove, 4693c5aff182SThomas Petazzoni .driver = { 4694c5aff182SThomas Petazzoni .name = MVNETA_DRIVER_NAME, 4695c5aff182SThomas Petazzoni .of_match_table = mvneta_match, 46969768b45cSJane Li .pm = &mvneta_pm_ops, 4697c5aff182SThomas Petazzoni }, 4698c5aff182SThomas Petazzoni }; 4699c5aff182SThomas Petazzoni 470084a3f4dbSSebastian Andrzej Siewior static int __init mvneta_driver_init(void) 470184a3f4dbSSebastian Andrzej Siewior { 470284a3f4dbSSebastian Andrzej Siewior int ret; 470384a3f4dbSSebastian Andrzej Siewior 470484a3f4dbSSebastian Andrzej Siewior ret = cpuhp_setup_state_multi(CPUHP_AP_ONLINE_DYN, "net/mvmeta:online", 470584a3f4dbSSebastian Andrzej Siewior mvneta_cpu_online, 470684a3f4dbSSebastian Andrzej Siewior mvneta_cpu_down_prepare); 470784a3f4dbSSebastian Andrzej Siewior if (ret < 0) 470884a3f4dbSSebastian Andrzej Siewior goto out; 470984a3f4dbSSebastian Andrzej Siewior online_hpstate = ret; 471084a3f4dbSSebastian Andrzej Siewior ret = cpuhp_setup_state_multi(CPUHP_NET_MVNETA_DEAD, "net/mvneta:dead", 471184a3f4dbSSebastian Andrzej Siewior NULL, mvneta_cpu_dead); 471284a3f4dbSSebastian Andrzej Siewior if (ret) 471384a3f4dbSSebastian Andrzej Siewior goto err_dead; 471484a3f4dbSSebastian Andrzej Siewior 471584a3f4dbSSebastian Andrzej Siewior ret = platform_driver_register(&mvneta_driver); 471684a3f4dbSSebastian Andrzej Siewior if (ret) 471784a3f4dbSSebastian Andrzej Siewior goto err; 471884a3f4dbSSebastian Andrzej Siewior return 0; 471984a3f4dbSSebastian Andrzej Siewior 472084a3f4dbSSebastian Andrzej Siewior err: 472184a3f4dbSSebastian Andrzej Siewior cpuhp_remove_multi_state(CPUHP_NET_MVNETA_DEAD); 472284a3f4dbSSebastian Andrzej Siewior err_dead: 472384a3f4dbSSebastian Andrzej Siewior cpuhp_remove_multi_state(online_hpstate); 472484a3f4dbSSebastian Andrzej Siewior out: 472584a3f4dbSSebastian Andrzej Siewior return ret; 472684a3f4dbSSebastian Andrzej Siewior } 472784a3f4dbSSebastian Andrzej Siewior module_init(mvneta_driver_init); 472884a3f4dbSSebastian Andrzej Siewior 472984a3f4dbSSebastian Andrzej Siewior static void __exit mvneta_driver_exit(void) 473084a3f4dbSSebastian Andrzej Siewior { 473184a3f4dbSSebastian Andrzej Siewior platform_driver_unregister(&mvneta_driver); 473284a3f4dbSSebastian Andrzej Siewior cpuhp_remove_multi_state(CPUHP_NET_MVNETA_DEAD); 473384a3f4dbSSebastian Andrzej Siewior cpuhp_remove_multi_state(online_hpstate); 473484a3f4dbSSebastian Andrzej Siewior } 473584a3f4dbSSebastian Andrzej Siewior module_exit(mvneta_driver_exit); 4736c5aff182SThomas Petazzoni 4737c5aff182SThomas Petazzoni MODULE_DESCRIPTION("Marvell NETA Ethernet Driver - www.marvell.com"); 4738c5aff182SThomas Petazzoni MODULE_AUTHOR("Rami Rosen <rosenr@marvell.com>, Thomas Petazzoni <thomas.petazzoni@free-electrons.com>"); 4739c5aff182SThomas Petazzoni MODULE_LICENSE("GPL"); 4740c5aff182SThomas Petazzoni 4741d3757ba4SJoe Perches module_param(rxq_number, int, 0444); 4742d3757ba4SJoe Perches module_param(txq_number, int, 0444); 4743c5aff182SThomas Petazzoni 4744d3757ba4SJoe Perches module_param(rxq_def, int, 0444); 4745d3757ba4SJoe Perches module_param(rx_copybreak, int, 0644); 4746