1c5aff182SThomas Petazzoni /* 2c5aff182SThomas Petazzoni * Driver for Marvell NETA network card for Armada XP and Armada 370 SoCs. 3c5aff182SThomas Petazzoni * 4c5aff182SThomas Petazzoni * Copyright (C) 2012 Marvell 5c5aff182SThomas Petazzoni * 6c5aff182SThomas Petazzoni * Rami Rosen <rosenr@marvell.com> 7c5aff182SThomas Petazzoni * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> 8c5aff182SThomas Petazzoni * 9c5aff182SThomas Petazzoni * This file is licensed under the terms of the GNU General Public 10c5aff182SThomas Petazzoni * License version 2. This program is licensed "as is" without any 11c5aff182SThomas Petazzoni * warranty of any kind, whether express or implied. 12c5aff182SThomas Petazzoni */ 13c5aff182SThomas Petazzoni 140e03f563SJisheng Zhang #include <linux/clk.h> 150e03f563SJisheng Zhang #include <linux/cpu.h> 16c5aff182SThomas Petazzoni #include <linux/etherdevice.h> 170e03f563SJisheng Zhang #include <linux/if_vlan.h> 18c5aff182SThomas Petazzoni #include <linux/inetdevice.h> 190e03f563SJisheng Zhang #include <linux/interrupt.h> 200e03f563SJisheng Zhang #include <linux/io.h> 210e03f563SJisheng Zhang #include <linux/kernel.h> 22c5aff182SThomas Petazzoni #include <linux/mbus.h> 23c5aff182SThomas Petazzoni #include <linux/module.h> 240e03f563SJisheng Zhang #include <linux/netdevice.h> 25c5aff182SThomas Petazzoni #include <linux/of.h> 260e03f563SJisheng Zhang #include <linux/of_address.h> 27c5aff182SThomas Petazzoni #include <linux/of_irq.h> 28c5aff182SThomas Petazzoni #include <linux/of_mdio.h> 29c5aff182SThomas Petazzoni #include <linux/of_net.h> 30a10c1c81SRussell King #include <linux/phy/phy.h> 31c5aff182SThomas Petazzoni #include <linux/phy.h> 32503f9aa9SRussell King #include <linux/phylink.h> 330e03f563SJisheng Zhang #include <linux/platform_device.h> 340e03f563SJisheng Zhang #include <linux/skbuff.h> 35baa11ebcSGregory CLEMENT #include <net/hwbm.h> 36dc35a10fSMarcin Wojtas #include "mvneta_bm.h" 370e03f563SJisheng Zhang #include <net/ip.h> 380e03f563SJisheng Zhang #include <net/ipv6.h> 390e03f563SJisheng Zhang #include <net/tso.h> 40c5aff182SThomas Petazzoni 41c5aff182SThomas Petazzoni /* Registers */ 42c5aff182SThomas Petazzoni #define MVNETA_RXQ_CONFIG_REG(q) (0x1400 + ((q) << 2)) 43e5bdf689SMarcin Wojtas #define MVNETA_RXQ_HW_BUF_ALLOC BIT(0) 44dc35a10fSMarcin Wojtas #define MVNETA_RXQ_SHORT_POOL_ID_SHIFT 4 45dc35a10fSMarcin Wojtas #define MVNETA_RXQ_SHORT_POOL_ID_MASK 0x30 46dc35a10fSMarcin Wojtas #define MVNETA_RXQ_LONG_POOL_ID_SHIFT 6 47dc35a10fSMarcin Wojtas #define MVNETA_RXQ_LONG_POOL_ID_MASK 0xc0 48c5aff182SThomas Petazzoni #define MVNETA_RXQ_PKT_OFFSET_ALL_MASK (0xf << 8) 49c5aff182SThomas Petazzoni #define MVNETA_RXQ_PKT_OFFSET_MASK(offs) ((offs) << 8) 50c5aff182SThomas Petazzoni #define MVNETA_RXQ_THRESHOLD_REG(q) (0x14c0 + ((q) << 2)) 51c5aff182SThomas Petazzoni #define MVNETA_RXQ_NON_OCCUPIED(v) ((v) << 16) 52c5aff182SThomas Petazzoni #define MVNETA_RXQ_BASE_ADDR_REG(q) (0x1480 + ((q) << 2)) 53c5aff182SThomas Petazzoni #define MVNETA_RXQ_SIZE_REG(q) (0x14a0 + ((q) << 2)) 54c5aff182SThomas Petazzoni #define MVNETA_RXQ_BUF_SIZE_SHIFT 19 55c5aff182SThomas Petazzoni #define MVNETA_RXQ_BUF_SIZE_MASK (0x1fff << 19) 56c5aff182SThomas Petazzoni #define MVNETA_RXQ_STATUS_REG(q) (0x14e0 + ((q) << 2)) 57c5aff182SThomas Petazzoni #define MVNETA_RXQ_OCCUPIED_ALL_MASK 0x3fff 58c5aff182SThomas Petazzoni #define MVNETA_RXQ_STATUS_UPDATE_REG(q) (0x1500 + ((q) << 2)) 59c5aff182SThomas Petazzoni #define MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT 16 60c5aff182SThomas Petazzoni #define MVNETA_RXQ_ADD_NON_OCCUPIED_MAX 255 61dc35a10fSMarcin Wojtas #define MVNETA_PORT_POOL_BUFFER_SZ_REG(pool) (0x1700 + ((pool) << 2)) 62dc35a10fSMarcin Wojtas #define MVNETA_PORT_POOL_BUFFER_SZ_SHIFT 3 63dc35a10fSMarcin Wojtas #define MVNETA_PORT_POOL_BUFFER_SZ_MASK 0xfff8 64c5aff182SThomas Petazzoni #define MVNETA_PORT_RX_RESET 0x1cc0 65c5aff182SThomas Petazzoni #define MVNETA_PORT_RX_DMA_RESET BIT(0) 66c5aff182SThomas Petazzoni #define MVNETA_PHY_ADDR 0x2000 67c5aff182SThomas Petazzoni #define MVNETA_PHY_ADDR_MASK 0x1f 68c5aff182SThomas Petazzoni #define MVNETA_MBUS_RETRY 0x2010 69c5aff182SThomas Petazzoni #define MVNETA_UNIT_INTR_CAUSE 0x2080 70c5aff182SThomas Petazzoni #define MVNETA_UNIT_CONTROL 0x20B0 71c5aff182SThomas Petazzoni #define MVNETA_PHY_POLLING_ENABLE BIT(1) 72c5aff182SThomas Petazzoni #define MVNETA_WIN_BASE(w) (0x2200 + ((w) << 3)) 73c5aff182SThomas Petazzoni #define MVNETA_WIN_SIZE(w) (0x2204 + ((w) << 3)) 74c5aff182SThomas Petazzoni #define MVNETA_WIN_REMAP(w) (0x2280 + ((w) << 2)) 75c5aff182SThomas Petazzoni #define MVNETA_BASE_ADDR_ENABLE 0x2290 76db6ba9a5SMarcin Wojtas #define MVNETA_ACCESS_PROTECT_ENABLE 0x2294 77c5aff182SThomas Petazzoni #define MVNETA_PORT_CONFIG 0x2400 78c5aff182SThomas Petazzoni #define MVNETA_UNI_PROMISC_MODE BIT(0) 79c5aff182SThomas Petazzoni #define MVNETA_DEF_RXQ(q) ((q) << 1) 80c5aff182SThomas Petazzoni #define MVNETA_DEF_RXQ_ARP(q) ((q) << 4) 81c5aff182SThomas Petazzoni #define MVNETA_TX_UNSET_ERR_SUM BIT(12) 82c5aff182SThomas Petazzoni #define MVNETA_DEF_RXQ_TCP(q) ((q) << 16) 83c5aff182SThomas Petazzoni #define MVNETA_DEF_RXQ_UDP(q) ((q) << 19) 84c5aff182SThomas Petazzoni #define MVNETA_DEF_RXQ_BPDU(q) ((q) << 22) 85c5aff182SThomas Petazzoni #define MVNETA_RX_CSUM_WITH_PSEUDO_HDR BIT(25) 86c5aff182SThomas Petazzoni #define MVNETA_PORT_CONFIG_DEFL_VALUE(q) (MVNETA_DEF_RXQ(q) | \ 87c5aff182SThomas Petazzoni MVNETA_DEF_RXQ_ARP(q) | \ 88c5aff182SThomas Petazzoni MVNETA_DEF_RXQ_TCP(q) | \ 89c5aff182SThomas Petazzoni MVNETA_DEF_RXQ_UDP(q) | \ 90c5aff182SThomas Petazzoni MVNETA_DEF_RXQ_BPDU(q) | \ 91c5aff182SThomas Petazzoni MVNETA_TX_UNSET_ERR_SUM | \ 92c5aff182SThomas Petazzoni MVNETA_RX_CSUM_WITH_PSEUDO_HDR) 93c5aff182SThomas Petazzoni #define MVNETA_PORT_CONFIG_EXTEND 0x2404 94c5aff182SThomas Petazzoni #define MVNETA_MAC_ADDR_LOW 0x2414 95c5aff182SThomas Petazzoni #define MVNETA_MAC_ADDR_HIGH 0x2418 96c5aff182SThomas Petazzoni #define MVNETA_SDMA_CONFIG 0x241c 97c5aff182SThomas Petazzoni #define MVNETA_SDMA_BRST_SIZE_16 4 98c5aff182SThomas Petazzoni #define MVNETA_RX_BRST_SZ_MASK(burst) ((burst) << 1) 99c5aff182SThomas Petazzoni #define MVNETA_RX_NO_DATA_SWAP BIT(4) 100c5aff182SThomas Petazzoni #define MVNETA_TX_NO_DATA_SWAP BIT(5) 1019ad8fef6SThomas Petazzoni #define MVNETA_DESC_SWAP BIT(6) 102c5aff182SThomas Petazzoni #define MVNETA_TX_BRST_SZ_MASK(burst) ((burst) << 22) 103c5aff182SThomas Petazzoni #define MVNETA_PORT_STATUS 0x2444 104c5aff182SThomas Petazzoni #define MVNETA_TX_IN_PRGRS BIT(1) 105c5aff182SThomas Petazzoni #define MVNETA_TX_FIFO_EMPTY BIT(8) 106c5aff182SThomas Petazzoni #define MVNETA_RX_MIN_FRAME_SIZE 0x247c 1073f1dd4bcSThomas Petazzoni #define MVNETA_SERDES_CFG 0x24A0 1085445eaf3SArnaud Patard \(Rtp\) #define MVNETA_SGMII_SERDES_PROTO 0x0cc7 1093f1dd4bcSThomas Petazzoni #define MVNETA_QSGMII_SERDES_PROTO 0x0667 110c5aff182SThomas Petazzoni #define MVNETA_TYPE_PRIO 0x24bc 111c5aff182SThomas Petazzoni #define MVNETA_FORCE_UNI BIT(21) 112c5aff182SThomas Petazzoni #define MVNETA_TXQ_CMD_1 0x24e4 113c5aff182SThomas Petazzoni #define MVNETA_TXQ_CMD 0x2448 114c5aff182SThomas Petazzoni #define MVNETA_TXQ_DISABLE_SHIFT 8 115c5aff182SThomas Petazzoni #define MVNETA_TXQ_ENABLE_MASK 0x000000ff 116e483911fSAndrew Lunn #define MVNETA_RX_DISCARD_FRAME_COUNT 0x2484 117e483911fSAndrew Lunn #define MVNETA_OVERRUN_FRAME_COUNT 0x2488 118898b2970SStas Sergeev #define MVNETA_GMAC_CLOCK_DIVIDER 0x24f4 119898b2970SStas Sergeev #define MVNETA_GMAC_1MS_CLOCK_ENABLE BIT(31) 120c5aff182SThomas Petazzoni #define MVNETA_ACC_MODE 0x2500 121dc35a10fSMarcin Wojtas #define MVNETA_BM_ADDRESS 0x2504 122c5aff182SThomas Petazzoni #define MVNETA_CPU_MAP(cpu) (0x2540 + ((cpu) << 2)) 123c5aff182SThomas Petazzoni #define MVNETA_CPU_RXQ_ACCESS_ALL_MASK 0x000000ff 124c5aff182SThomas Petazzoni #define MVNETA_CPU_TXQ_ACCESS_ALL_MASK 0x0000ff00 1252dcf75e2SGregory CLEMENT #define MVNETA_CPU_RXQ_ACCESS(rxq) BIT(rxq) 12650bf8cb6SGregory CLEMENT #define MVNETA_CPU_TXQ_ACCESS(txq) BIT(txq + 8) 127c5aff182SThomas Petazzoni #define MVNETA_RXQ_TIME_COAL_REG(q) (0x2580 + ((q) << 2)) 12840ba35e7Swilly tarreau 1292dcf75e2SGregory CLEMENT /* Exception Interrupt Port/Queue Cause register 1302dcf75e2SGregory CLEMENT * 1312dcf75e2SGregory CLEMENT * Their behavior depend of the mapping done using the PCPX2Q 1322dcf75e2SGregory CLEMENT * registers. For a given CPU if the bit associated to a queue is not 1332dcf75e2SGregory CLEMENT * set, then for the register a read from this CPU will always return 1342dcf75e2SGregory CLEMENT * 0 and a write won't do anything 1352dcf75e2SGregory CLEMENT */ 13640ba35e7Swilly tarreau 137c5aff182SThomas Petazzoni #define MVNETA_INTR_NEW_CAUSE 0x25a0 138c5aff182SThomas Petazzoni #define MVNETA_INTR_NEW_MASK 0x25a4 13940ba35e7Swilly tarreau 14040ba35e7Swilly tarreau /* bits 0..7 = TXQ SENT, one bit per queue. 14140ba35e7Swilly tarreau * bits 8..15 = RXQ OCCUP, one bit per queue. 14240ba35e7Swilly tarreau * bits 16..23 = RXQ FREE, one bit per queue. 14340ba35e7Swilly tarreau * bit 29 = OLD_REG_SUM, see old reg ? 14440ba35e7Swilly tarreau * bit 30 = TX_ERR_SUM, one bit for 4 ports 14540ba35e7Swilly tarreau * bit 31 = MISC_SUM, one bit for 4 ports 14640ba35e7Swilly tarreau */ 14740ba35e7Swilly tarreau #define MVNETA_TX_INTR_MASK(nr_txqs) (((1 << nr_txqs) - 1) << 0) 14840ba35e7Swilly tarreau #define MVNETA_TX_INTR_MASK_ALL (0xff << 0) 14940ba35e7Swilly tarreau #define MVNETA_RX_INTR_MASK(nr_rxqs) (((1 << nr_rxqs) - 1) << 8) 15040ba35e7Swilly tarreau #define MVNETA_RX_INTR_MASK_ALL (0xff << 8) 151898b2970SStas Sergeev #define MVNETA_MISCINTR_INTR_MASK BIT(31) 15240ba35e7Swilly tarreau 153c5aff182SThomas Petazzoni #define MVNETA_INTR_OLD_CAUSE 0x25a8 154c5aff182SThomas Petazzoni #define MVNETA_INTR_OLD_MASK 0x25ac 15540ba35e7Swilly tarreau 15640ba35e7Swilly tarreau /* Data Path Port/Queue Cause Register */ 157c5aff182SThomas Petazzoni #define MVNETA_INTR_MISC_CAUSE 0x25b0 158c5aff182SThomas Petazzoni #define MVNETA_INTR_MISC_MASK 0x25b4 15940ba35e7Swilly tarreau 16040ba35e7Swilly tarreau #define MVNETA_CAUSE_PHY_STATUS_CHANGE BIT(0) 16140ba35e7Swilly tarreau #define MVNETA_CAUSE_LINK_CHANGE BIT(1) 16240ba35e7Swilly tarreau #define MVNETA_CAUSE_PTP BIT(4) 16340ba35e7Swilly tarreau 16440ba35e7Swilly tarreau #define MVNETA_CAUSE_INTERNAL_ADDR_ERR BIT(7) 16540ba35e7Swilly tarreau #define MVNETA_CAUSE_RX_OVERRUN BIT(8) 16640ba35e7Swilly tarreau #define MVNETA_CAUSE_RX_CRC_ERROR BIT(9) 16740ba35e7Swilly tarreau #define MVNETA_CAUSE_RX_LARGE_PKT BIT(10) 16840ba35e7Swilly tarreau #define MVNETA_CAUSE_TX_UNDERUN BIT(11) 16940ba35e7Swilly tarreau #define MVNETA_CAUSE_PRBS_ERR BIT(12) 17040ba35e7Swilly tarreau #define MVNETA_CAUSE_PSC_SYNC_CHANGE BIT(13) 17140ba35e7Swilly tarreau #define MVNETA_CAUSE_SERDES_SYNC_ERR BIT(14) 17240ba35e7Swilly tarreau 17340ba35e7Swilly tarreau #define MVNETA_CAUSE_BMU_ALLOC_ERR_SHIFT 16 17440ba35e7Swilly tarreau #define MVNETA_CAUSE_BMU_ALLOC_ERR_ALL_MASK (0xF << MVNETA_CAUSE_BMU_ALLOC_ERR_SHIFT) 17540ba35e7Swilly tarreau #define MVNETA_CAUSE_BMU_ALLOC_ERR_MASK(pool) (1 << (MVNETA_CAUSE_BMU_ALLOC_ERR_SHIFT + (pool))) 17640ba35e7Swilly tarreau 17740ba35e7Swilly tarreau #define MVNETA_CAUSE_TXQ_ERROR_SHIFT 24 17840ba35e7Swilly tarreau #define MVNETA_CAUSE_TXQ_ERROR_ALL_MASK (0xFF << MVNETA_CAUSE_TXQ_ERROR_SHIFT) 17940ba35e7Swilly tarreau #define MVNETA_CAUSE_TXQ_ERROR_MASK(q) (1 << (MVNETA_CAUSE_TXQ_ERROR_SHIFT + (q))) 18040ba35e7Swilly tarreau 181c5aff182SThomas Petazzoni #define MVNETA_INTR_ENABLE 0x25b8 182c5aff182SThomas Petazzoni #define MVNETA_TXQ_INTR_ENABLE_ALL_MASK 0x0000ff00 183dc1aadf6SMarcin Wojtas #define MVNETA_RXQ_INTR_ENABLE_ALL_MASK 0x000000ff 18440ba35e7Swilly tarreau 185c5aff182SThomas Petazzoni #define MVNETA_RXQ_CMD 0x2680 186c5aff182SThomas Petazzoni #define MVNETA_RXQ_DISABLE_SHIFT 8 187c5aff182SThomas Petazzoni #define MVNETA_RXQ_ENABLE_MASK 0x000000ff 188c5aff182SThomas Petazzoni #define MVETH_TXQ_TOKEN_COUNT_REG(q) (0x2700 + ((q) << 4)) 189c5aff182SThomas Petazzoni #define MVETH_TXQ_TOKEN_CFG_REG(q) (0x2704 + ((q) << 4)) 190c5aff182SThomas Petazzoni #define MVNETA_GMAC_CTRL_0 0x2c00 191c5aff182SThomas Petazzoni #define MVNETA_GMAC_MAX_RX_SIZE_SHIFT 2 192c5aff182SThomas Petazzoni #define MVNETA_GMAC_MAX_RX_SIZE_MASK 0x7ffc 19322f4bf8aSRussell King #define MVNETA_GMAC0_PORT_1000BASE_X BIT(1) 194c5aff182SThomas Petazzoni #define MVNETA_GMAC0_PORT_ENABLE BIT(0) 195c5aff182SThomas Petazzoni #define MVNETA_GMAC_CTRL_2 0x2c08 196898b2970SStas Sergeev #define MVNETA_GMAC2_INBAND_AN_ENABLE BIT(0) 197a79121d3SThomas Petazzoni #define MVNETA_GMAC2_PCS_ENABLE BIT(3) 198c5aff182SThomas Petazzoni #define MVNETA_GMAC2_PORT_RGMII BIT(4) 199c5aff182SThomas Petazzoni #define MVNETA_GMAC2_PORT_RESET BIT(6) 200c5aff182SThomas Petazzoni #define MVNETA_GMAC_STATUS 0x2c10 201c5aff182SThomas Petazzoni #define MVNETA_GMAC_LINK_UP BIT(0) 202c5aff182SThomas Petazzoni #define MVNETA_GMAC_SPEED_1000 BIT(1) 203c5aff182SThomas Petazzoni #define MVNETA_GMAC_SPEED_100 BIT(2) 204c5aff182SThomas Petazzoni #define MVNETA_GMAC_FULL_DUPLEX BIT(3) 205c5aff182SThomas Petazzoni #define MVNETA_GMAC_RX_FLOW_CTRL_ENABLE BIT(4) 206c5aff182SThomas Petazzoni #define MVNETA_GMAC_TX_FLOW_CTRL_ENABLE BIT(5) 207c5aff182SThomas Petazzoni #define MVNETA_GMAC_RX_FLOW_CTRL_ACTIVE BIT(6) 208c5aff182SThomas Petazzoni #define MVNETA_GMAC_TX_FLOW_CTRL_ACTIVE BIT(7) 209503f9aa9SRussell King #define MVNETA_GMAC_AN_COMPLETE BIT(11) 210503f9aa9SRussell King #define MVNETA_GMAC_SYNC_OK BIT(14) 211c5aff182SThomas Petazzoni #define MVNETA_GMAC_AUTONEG_CONFIG 0x2c0c 212c5aff182SThomas Petazzoni #define MVNETA_GMAC_FORCE_LINK_DOWN BIT(0) 213c5aff182SThomas Petazzoni #define MVNETA_GMAC_FORCE_LINK_PASS BIT(1) 214898b2970SStas Sergeev #define MVNETA_GMAC_INBAND_AN_ENABLE BIT(2) 21522f4bf8aSRussell King #define MVNETA_GMAC_AN_BYPASS_ENABLE BIT(3) 21622f4bf8aSRussell King #define MVNETA_GMAC_INBAND_RESTART_AN BIT(4) 217c5aff182SThomas Petazzoni #define MVNETA_GMAC_CONFIG_MII_SPEED BIT(5) 218c5aff182SThomas Petazzoni #define MVNETA_GMAC_CONFIG_GMII_SPEED BIT(6) 21971408602SThomas Petazzoni #define MVNETA_GMAC_AN_SPEED_EN BIT(7) 22022f4bf8aSRussell King #define MVNETA_GMAC_CONFIG_FLOW_CTRL BIT(8) 22122f4bf8aSRussell King #define MVNETA_GMAC_ADVERT_SYM_FLOW_CTRL BIT(9) 222898b2970SStas Sergeev #define MVNETA_GMAC_AN_FLOW_CTRL_EN BIT(11) 223c5aff182SThomas Petazzoni #define MVNETA_GMAC_CONFIG_FULL_DUPLEX BIT(12) 22471408602SThomas Petazzoni #define MVNETA_GMAC_AN_DUPLEX_EN BIT(13) 225da58a931SMaxime Chevallier #define MVNETA_GMAC_CTRL_4 0x2c90 226da58a931SMaxime Chevallier #define MVNETA_GMAC4_SHORT_PREAMBLE_ENABLE BIT(1) 227e483911fSAndrew Lunn #define MVNETA_MIB_COUNTERS_BASE 0x3000 228c5aff182SThomas Petazzoni #define MVNETA_MIB_LATE_COLLISION 0x7c 229c5aff182SThomas Petazzoni #define MVNETA_DA_FILT_SPEC_MCAST 0x3400 230c5aff182SThomas Petazzoni #define MVNETA_DA_FILT_OTH_MCAST 0x3500 231c5aff182SThomas Petazzoni #define MVNETA_DA_FILT_UCAST_BASE 0x3600 232c5aff182SThomas Petazzoni #define MVNETA_TXQ_BASE_ADDR_REG(q) (0x3c00 + ((q) << 2)) 233c5aff182SThomas Petazzoni #define MVNETA_TXQ_SIZE_REG(q) (0x3c20 + ((q) << 2)) 234c5aff182SThomas Petazzoni #define MVNETA_TXQ_SENT_THRESH_ALL_MASK 0x3fff0000 235c5aff182SThomas Petazzoni #define MVNETA_TXQ_SENT_THRESH_MASK(coal) ((coal) << 16) 236c5aff182SThomas Petazzoni #define MVNETA_TXQ_UPDATE_REG(q) (0x3c60 + ((q) << 2)) 237c5aff182SThomas Petazzoni #define MVNETA_TXQ_DEC_SENT_SHIFT 16 2382a90f7e1SSimon Guinot #define MVNETA_TXQ_DEC_SENT_MASK 0xff 239c5aff182SThomas Petazzoni #define MVNETA_TXQ_STATUS_REG(q) (0x3c40 + ((q) << 2)) 240c5aff182SThomas Petazzoni #define MVNETA_TXQ_SENT_DESC_SHIFT 16 241c5aff182SThomas Petazzoni #define MVNETA_TXQ_SENT_DESC_MASK 0x3fff0000 242c5aff182SThomas Petazzoni #define MVNETA_PORT_TX_RESET 0x3cf0 243c5aff182SThomas Petazzoni #define MVNETA_PORT_TX_DMA_RESET BIT(0) 244c5aff182SThomas Petazzoni #define MVNETA_TX_MTU 0x3e0c 245c5aff182SThomas Petazzoni #define MVNETA_TX_TOKEN_SIZE 0x3e14 246c5aff182SThomas Petazzoni #define MVNETA_TX_TOKEN_SIZE_MAX 0xffffffff 247c5aff182SThomas Petazzoni #define MVNETA_TXQ_TOKEN_SIZE_REG(q) (0x3e40 + ((q) << 2)) 248c5aff182SThomas Petazzoni #define MVNETA_TXQ_TOKEN_SIZE_MAX 0x7fffffff 249c5aff182SThomas Petazzoni 2506d81f451SRussell King #define MVNETA_LPI_CTRL_0 0x2cc0 2516d81f451SRussell King #define MVNETA_LPI_CTRL_1 0x2cc4 2526d81f451SRussell King #define MVNETA_LPI_REQUEST_ENABLE BIT(0) 2536d81f451SRussell King #define MVNETA_LPI_CTRL_2 0x2cc8 2546d81f451SRussell King #define MVNETA_LPI_STATUS 0x2ccc 2556d81f451SRussell King 256c5aff182SThomas Petazzoni #define MVNETA_CAUSE_TXQ_SENT_DESC_ALL_MASK 0xff 257c5aff182SThomas Petazzoni 258c5aff182SThomas Petazzoni /* Descriptor ring Macros */ 259c5aff182SThomas Petazzoni #define MVNETA_QUEUE_NEXT_DESC(q, index) \ 260c5aff182SThomas Petazzoni (((index) < (q)->last_desc) ? ((index) + 1) : 0) 261c5aff182SThomas Petazzoni 262c5aff182SThomas Petazzoni /* Various constants */ 263c5aff182SThomas Petazzoni 264c5aff182SThomas Petazzoni /* Coalescing */ 26506708f81SDmitri Epshtein #define MVNETA_TXDONE_COAL_PKTS 0 /* interrupt per packet */ 266c5aff182SThomas Petazzoni #define MVNETA_RX_COAL_PKTS 32 267c5aff182SThomas Petazzoni #define MVNETA_RX_COAL_USEC 100 268c5aff182SThomas Petazzoni 2696a20c175SThomas Petazzoni /* The two bytes Marvell header. Either contains a special value used 270c5aff182SThomas Petazzoni * by Marvell switches when a specific hardware mode is enabled (not 271c5aff182SThomas Petazzoni * supported by this driver) or is filled automatically by zeroes on 272c5aff182SThomas Petazzoni * the RX side. Those two bytes being at the front of the Ethernet 273c5aff182SThomas Petazzoni * header, they allow to have the IP header aligned on a 4 bytes 274c5aff182SThomas Petazzoni * boundary automatically: the hardware skips those two bytes on its 275c5aff182SThomas Petazzoni * own. 276c5aff182SThomas Petazzoni */ 277c5aff182SThomas Petazzoni #define MVNETA_MH_SIZE 2 278c5aff182SThomas Petazzoni 279c5aff182SThomas Petazzoni #define MVNETA_VLAN_TAG_LEN 4 280c5aff182SThomas Petazzoni 2819110ee07SMarcin Wojtas #define MVNETA_TX_CSUM_DEF_SIZE 1600 282c5aff182SThomas Petazzoni #define MVNETA_TX_CSUM_MAX_SIZE 9800 283dc35a10fSMarcin Wojtas #define MVNETA_ACC_MODE_EXT1 1 284dc35a10fSMarcin Wojtas #define MVNETA_ACC_MODE_EXT2 2 285dc35a10fSMarcin Wojtas 286dc35a10fSMarcin Wojtas #define MVNETA_MAX_DECODE_WIN 6 287c5aff182SThomas Petazzoni 288c5aff182SThomas Petazzoni /* Timeout constants */ 289c5aff182SThomas Petazzoni #define MVNETA_TX_DISABLE_TIMEOUT_MSEC 1000 290c5aff182SThomas Petazzoni #define MVNETA_RX_DISABLE_TIMEOUT_MSEC 1000 291c5aff182SThomas Petazzoni #define MVNETA_TX_FIFO_EMPTY_TIMEOUT 10000 292c5aff182SThomas Petazzoni 293c5aff182SThomas Petazzoni #define MVNETA_TX_MTU_MAX 0x3ffff 294c5aff182SThomas Petazzoni 2959a401deaSGregory CLEMENT /* The RSS lookup table actually has 256 entries but we do not use 2969a401deaSGregory CLEMENT * them yet 2979a401deaSGregory CLEMENT */ 2989a401deaSGregory CLEMENT #define MVNETA_RSS_LU_TABLE_SIZE 1 2999a401deaSGregory CLEMENT 300c5aff182SThomas Petazzoni /* Max number of Rx descriptors */ 301c307e2a8SYelena Krivosheev #define MVNETA_MAX_RXD 512 302c5aff182SThomas Petazzoni 303c5aff182SThomas Petazzoni /* Max number of Tx descriptors */ 304c307e2a8SYelena Krivosheev #define MVNETA_MAX_TXD 1024 305c5aff182SThomas Petazzoni 3068eef5f97SEzequiel Garcia /* Max number of allowed TCP segments for software TSO */ 3078eef5f97SEzequiel Garcia #define MVNETA_MAX_TSO_SEGS 100 3088eef5f97SEzequiel Garcia 3098eef5f97SEzequiel Garcia #define MVNETA_MAX_SKB_DESCS (MVNETA_MAX_TSO_SEGS * 2 + MAX_SKB_FRAGS) 3108eef5f97SEzequiel Garcia 311c5aff182SThomas Petazzoni /* descriptor aligned size */ 312c5aff182SThomas Petazzoni #define MVNETA_DESC_ALIGNED_SIZE 32 313c5aff182SThomas Petazzoni 3148d5047cfSMarcin Wojtas /* Number of bytes to be taken into account by HW when putting incoming data 3158d5047cfSMarcin Wojtas * to the buffers. It is needed in case NET_SKB_PAD exceeds maximum packet 3168d5047cfSMarcin Wojtas * offset supported in MVNETA_RXQ_CONFIG_REG(q) registers. 3178d5047cfSMarcin Wojtas */ 3188d5047cfSMarcin Wojtas #define MVNETA_RX_PKT_OFFSET_CORRECTION 64 3198d5047cfSMarcin Wojtas 320c5aff182SThomas Petazzoni #define MVNETA_RX_PKT_SIZE(mtu) \ 321c5aff182SThomas Petazzoni ALIGN((mtu) + MVNETA_MH_SIZE + MVNETA_VLAN_TAG_LEN + \ 322c5aff182SThomas Petazzoni ETH_HLEN + ETH_FCS_LEN, \ 323c66e98c9SJisheng Zhang cache_line_size()) 324c5aff182SThomas Petazzoni 3252e3173a3SEzequiel Garcia #define IS_TSO_HEADER(txq, addr) \ 3262e3173a3SEzequiel Garcia ((addr >= txq->tso_hdrs_phys) && \ 3272e3173a3SEzequiel Garcia (addr < txq->tso_hdrs_phys + txq->size * TSO_HEADER_SIZE)) 3282e3173a3SEzequiel Garcia 329dc35a10fSMarcin Wojtas #define MVNETA_RX_GET_BM_POOL_ID(rxd) \ 330dc35a10fSMarcin Wojtas (((rxd)->status & MVNETA_RXD_BM_POOL_MASK) >> MVNETA_RXD_BM_POOL_SHIFT) 331c5aff182SThomas Petazzoni 3326d81f451SRussell King enum { 3336d81f451SRussell King ETHTOOL_STAT_EEE_WAKEUP, 33417a96da6SGregory CLEMENT ETHTOOL_STAT_SKB_ALLOC_ERR, 33517a96da6SGregory CLEMENT ETHTOOL_STAT_REFILL_ERR, 3366d81f451SRussell King ETHTOOL_MAX_STATS, 3376d81f451SRussell King }; 3386d81f451SRussell King 3399b0cdefaSRussell King struct mvneta_statistic { 3409b0cdefaSRussell King unsigned short offset; 3419b0cdefaSRussell King unsigned short type; 3429b0cdefaSRussell King const char name[ETH_GSTRING_LEN]; 3439b0cdefaSRussell King }; 3449b0cdefaSRussell King 3459b0cdefaSRussell King #define T_REG_32 32 3469b0cdefaSRussell King #define T_REG_64 64 3476d81f451SRussell King #define T_SW 1 3489b0cdefaSRussell King 3499b0cdefaSRussell King static const struct mvneta_statistic mvneta_statistics[] = { 3509b0cdefaSRussell King { 0x3000, T_REG_64, "good_octets_received", }, 3519b0cdefaSRussell King { 0x3010, T_REG_32, "good_frames_received", }, 3529b0cdefaSRussell King { 0x3008, T_REG_32, "bad_octets_received", }, 3539b0cdefaSRussell King { 0x3014, T_REG_32, "bad_frames_received", }, 3549b0cdefaSRussell King { 0x3018, T_REG_32, "broadcast_frames_received", }, 3559b0cdefaSRussell King { 0x301c, T_REG_32, "multicast_frames_received", }, 3569b0cdefaSRussell King { 0x3050, T_REG_32, "unrec_mac_control_received", }, 3579b0cdefaSRussell King { 0x3058, T_REG_32, "good_fc_received", }, 3589b0cdefaSRussell King { 0x305c, T_REG_32, "bad_fc_received", }, 3599b0cdefaSRussell King { 0x3060, T_REG_32, "undersize_received", }, 3609b0cdefaSRussell King { 0x3064, T_REG_32, "fragments_received", }, 3619b0cdefaSRussell King { 0x3068, T_REG_32, "oversize_received", }, 3629b0cdefaSRussell King { 0x306c, T_REG_32, "jabber_received", }, 3639b0cdefaSRussell King { 0x3070, T_REG_32, "mac_receive_error", }, 3649b0cdefaSRussell King { 0x3074, T_REG_32, "bad_crc_event", }, 3659b0cdefaSRussell King { 0x3078, T_REG_32, "collision", }, 3669b0cdefaSRussell King { 0x307c, T_REG_32, "late_collision", }, 3679b0cdefaSRussell King { 0x2484, T_REG_32, "rx_discard", }, 3689b0cdefaSRussell King { 0x2488, T_REG_32, "rx_overrun", }, 3699b0cdefaSRussell King { 0x3020, T_REG_32, "frames_64_octets", }, 3709b0cdefaSRussell King { 0x3024, T_REG_32, "frames_65_to_127_octets", }, 3719b0cdefaSRussell King { 0x3028, T_REG_32, "frames_128_to_255_octets", }, 3729b0cdefaSRussell King { 0x302c, T_REG_32, "frames_256_to_511_octets", }, 3739b0cdefaSRussell King { 0x3030, T_REG_32, "frames_512_to_1023_octets", }, 3749b0cdefaSRussell King { 0x3034, T_REG_32, "frames_1024_to_max_octets", }, 3759b0cdefaSRussell King { 0x3038, T_REG_64, "good_octets_sent", }, 3769b0cdefaSRussell King { 0x3040, T_REG_32, "good_frames_sent", }, 3779b0cdefaSRussell King { 0x3044, T_REG_32, "excessive_collision", }, 3789b0cdefaSRussell King { 0x3048, T_REG_32, "multicast_frames_sent", }, 3799b0cdefaSRussell King { 0x304c, T_REG_32, "broadcast_frames_sent", }, 3809b0cdefaSRussell King { 0x3054, T_REG_32, "fc_sent", }, 3819b0cdefaSRussell King { 0x300c, T_REG_32, "internal_mac_transmit_err", }, 3826d81f451SRussell King { ETHTOOL_STAT_EEE_WAKEUP, T_SW, "eee_wakeup_errors", }, 38317a96da6SGregory CLEMENT { ETHTOOL_STAT_SKB_ALLOC_ERR, T_SW, "skb_alloc_errors", }, 38417a96da6SGregory CLEMENT { ETHTOOL_STAT_REFILL_ERR, T_SW, "refill_errors", }, 3859b0cdefaSRussell King }; 3869b0cdefaSRussell King 38774c41b04Swilly tarreau struct mvneta_pcpu_stats { 388c5aff182SThomas Petazzoni struct u64_stats_sync syncp; 38974c41b04Swilly tarreau u64 rx_packets; 39074c41b04Swilly tarreau u64 rx_bytes; 39174c41b04Swilly tarreau u64 tx_packets; 39274c41b04Swilly tarreau u64 tx_bytes; 393c5aff182SThomas Petazzoni }; 394c5aff182SThomas Petazzoni 39512bb03b4SMaxime Ripard struct mvneta_pcpu_port { 39612bb03b4SMaxime Ripard /* Pointer to the shared port */ 39712bb03b4SMaxime Ripard struct mvneta_port *pp; 39812bb03b4SMaxime Ripard 39912bb03b4SMaxime Ripard /* Pointer to the CPU-local NAPI struct */ 40012bb03b4SMaxime Ripard struct napi_struct napi; 40112bb03b4SMaxime Ripard 40212bb03b4SMaxime Ripard /* Cause of the previous interrupt */ 40312bb03b4SMaxime Ripard u32 cause_rx_tx; 40412bb03b4SMaxime Ripard }; 40512bb03b4SMaxime Ripard 406c5aff182SThomas Petazzoni struct mvneta_port { 407dc35a10fSMarcin Wojtas u8 id; 40812bb03b4SMaxime Ripard struct mvneta_pcpu_port __percpu *ports; 40912bb03b4SMaxime Ripard struct mvneta_pcpu_stats __percpu *stats; 41012bb03b4SMaxime Ripard 411c5aff182SThomas Petazzoni int pkt_size; 412c5aff182SThomas Petazzoni void __iomem *base; 413c5aff182SThomas Petazzoni struct mvneta_rx_queue *rxqs; 414c5aff182SThomas Petazzoni struct mvneta_tx_queue *txqs; 415c5aff182SThomas Petazzoni struct net_device *dev; 41684a3f4dbSSebastian Andrzej Siewior struct hlist_node node_online; 41784a3f4dbSSebastian Andrzej Siewior struct hlist_node node_dead; 41890b74c01SGregory CLEMENT int rxq_def; 4195888511eSGregory CLEMENT /* Protect the access to the percpu interrupt registers, 4205888511eSGregory CLEMENT * ensuring that the configuration remains coherent. 4215888511eSGregory CLEMENT */ 4225888511eSGregory CLEMENT spinlock_t lock; 423120cfa50SGregory CLEMENT bool is_stopped; 424c5aff182SThomas Petazzoni 4252636ac3cSMarcin Wojtas u32 cause_rx_tx; 4262636ac3cSMarcin Wojtas struct napi_struct napi; 4272636ac3cSMarcin Wojtas 428c5aff182SThomas Petazzoni /* Core clock */ 429189dd626SThomas Petazzoni struct clk *clk; 43015cc4a4aSJisheng Zhang /* AXI clock */ 43115cc4a4aSJisheng Zhang struct clk *clk_bus; 432c5aff182SThomas Petazzoni u8 mcast_count[256]; 433c5aff182SThomas Petazzoni u16 tx_ring_size; 434c5aff182SThomas Petazzoni u16 rx_ring_size; 435c5aff182SThomas Petazzoni 436c5aff182SThomas Petazzoni phy_interface_t phy_interface; 437503f9aa9SRussell King struct device_node *dn; 438b65657fcSSimon Guinot unsigned int tx_csum_limit; 439503f9aa9SRussell King struct phylink *phylink; 44044cc27e4SIoana Ciornei struct phylink_config phylink_config; 441a10c1c81SRussell King struct phy *comphy; 4429b0cdefaSRussell King 443dc35a10fSMarcin Wojtas struct mvneta_bm *bm_priv; 444dc35a10fSMarcin Wojtas struct mvneta_bm_pool *pool_long; 445dc35a10fSMarcin Wojtas struct mvneta_bm_pool *pool_short; 446dc35a10fSMarcin Wojtas int bm_win_id; 447dc35a10fSMarcin Wojtas 4486d81f451SRussell King bool eee_enabled; 4496d81f451SRussell King bool eee_active; 4506d81f451SRussell King bool tx_lpi_enabled; 4516d81f451SRussell King 4529b0cdefaSRussell King u64 ethtool_stats[ARRAY_SIZE(mvneta_statistics)]; 4539a401deaSGregory CLEMENT 4549a401deaSGregory CLEMENT u32 indir[MVNETA_RSS_LU_TABLE_SIZE]; 4552636ac3cSMarcin Wojtas 4562636ac3cSMarcin Wojtas /* Flags for special SoC configurations */ 4572636ac3cSMarcin Wojtas bool neta_armada3700; 4588d5047cfSMarcin Wojtas u16 rx_offset_correction; 4599768b45cSJane Li const struct mbus_dram_target_info *dram_target_info; 460c5aff182SThomas Petazzoni }; 461c5aff182SThomas Petazzoni 4626a20c175SThomas Petazzoni /* The mvneta_tx_desc and mvneta_rx_desc structures describe the 463c5aff182SThomas Petazzoni * layout of the transmit and reception DMA descriptors, and their 464c5aff182SThomas Petazzoni * layout is therefore defined by the hardware design 465c5aff182SThomas Petazzoni */ 4666083ed44SThomas Petazzoni 467c5aff182SThomas Petazzoni #define MVNETA_TX_L3_OFF_SHIFT 0 468c5aff182SThomas Petazzoni #define MVNETA_TX_IP_HLEN_SHIFT 8 469c5aff182SThomas Petazzoni #define MVNETA_TX_L4_UDP BIT(16) 470c5aff182SThomas Petazzoni #define MVNETA_TX_L3_IP6 BIT(17) 471c5aff182SThomas Petazzoni #define MVNETA_TXD_IP_CSUM BIT(18) 472c5aff182SThomas Petazzoni #define MVNETA_TXD_Z_PAD BIT(19) 473c5aff182SThomas Petazzoni #define MVNETA_TXD_L_DESC BIT(20) 474c5aff182SThomas Petazzoni #define MVNETA_TXD_F_DESC BIT(21) 475c5aff182SThomas Petazzoni #define MVNETA_TXD_FLZ_DESC (MVNETA_TXD_Z_PAD | \ 476c5aff182SThomas Petazzoni MVNETA_TXD_L_DESC | \ 477c5aff182SThomas Petazzoni MVNETA_TXD_F_DESC) 478c5aff182SThomas Petazzoni #define MVNETA_TX_L4_CSUM_FULL BIT(30) 479c5aff182SThomas Petazzoni #define MVNETA_TX_L4_CSUM_NOT BIT(31) 480c5aff182SThomas Petazzoni 481c5aff182SThomas Petazzoni #define MVNETA_RXD_ERR_CRC 0x0 482dc35a10fSMarcin Wojtas #define MVNETA_RXD_BM_POOL_SHIFT 13 483dc35a10fSMarcin Wojtas #define MVNETA_RXD_BM_POOL_MASK (BIT(13) | BIT(14)) 484c5aff182SThomas Petazzoni #define MVNETA_RXD_ERR_SUMMARY BIT(16) 485c5aff182SThomas Petazzoni #define MVNETA_RXD_ERR_OVERRUN BIT(17) 486c5aff182SThomas Petazzoni #define MVNETA_RXD_ERR_LEN BIT(18) 487c5aff182SThomas Petazzoni #define MVNETA_RXD_ERR_RESOURCE (BIT(17) | BIT(18)) 488c5aff182SThomas Petazzoni #define MVNETA_RXD_ERR_CODE_MASK (BIT(17) | BIT(18)) 489c5aff182SThomas Petazzoni #define MVNETA_RXD_L3_IP4 BIT(25) 490562e2f46SYelena Krivosheev #define MVNETA_RXD_LAST_DESC BIT(26) 491562e2f46SYelena Krivosheev #define MVNETA_RXD_FIRST_DESC BIT(27) 492562e2f46SYelena Krivosheev #define MVNETA_RXD_FIRST_LAST_DESC (MVNETA_RXD_FIRST_DESC | \ 493562e2f46SYelena Krivosheev MVNETA_RXD_LAST_DESC) 494c5aff182SThomas Petazzoni #define MVNETA_RXD_L4_CSUM_OK BIT(30) 495c5aff182SThomas Petazzoni 4969ad8fef6SThomas Petazzoni #if defined(__LITTLE_ENDIAN) 4976083ed44SThomas Petazzoni struct mvneta_tx_desc { 4986083ed44SThomas Petazzoni u32 command; /* Options used by HW for packet transmitting.*/ 499fbd1d524SAlexandre Belloni u16 reserved1; /* csum_l4 (for future use) */ 5006083ed44SThomas Petazzoni u16 data_size; /* Data size of transmitted packet in bytes */ 5016083ed44SThomas Petazzoni u32 buf_phys_addr; /* Physical addr of transmitted buffer */ 5026083ed44SThomas Petazzoni u32 reserved2; /* hw_cmd - (for future use, PMT) */ 5036083ed44SThomas Petazzoni u32 reserved3[4]; /* Reserved - (for future use) */ 5046083ed44SThomas Petazzoni }; 5056083ed44SThomas Petazzoni 5066083ed44SThomas Petazzoni struct mvneta_rx_desc { 5076083ed44SThomas Petazzoni u32 status; /* Info about received packet */ 508c5aff182SThomas Petazzoni u16 reserved1; /* pnc_info - (for future use, PnC) */ 509c5aff182SThomas Petazzoni u16 data_size; /* Size of received packet in bytes */ 5106083ed44SThomas Petazzoni 511c5aff182SThomas Petazzoni u32 buf_phys_addr; /* Physical address of the buffer */ 512c5aff182SThomas Petazzoni u32 reserved2; /* pnc_flow_id (for future use, PnC) */ 5136083ed44SThomas Petazzoni 514c5aff182SThomas Petazzoni u32 buf_cookie; /* cookie for access to RX buffer in rx path */ 515c5aff182SThomas Petazzoni u16 reserved3; /* prefetch_cmd, for future use */ 516c5aff182SThomas Petazzoni u16 reserved4; /* csum_l4 - (for future use, PnC) */ 5176083ed44SThomas Petazzoni 518c5aff182SThomas Petazzoni u32 reserved5; /* pnc_extra PnC (for future use, PnC) */ 519c5aff182SThomas Petazzoni u32 reserved6; /* hw_cmd (for future use, PnC and HWF) */ 520c5aff182SThomas Petazzoni }; 5219ad8fef6SThomas Petazzoni #else 5229ad8fef6SThomas Petazzoni struct mvneta_tx_desc { 5239ad8fef6SThomas Petazzoni u16 data_size; /* Data size of transmitted packet in bytes */ 524fbd1d524SAlexandre Belloni u16 reserved1; /* csum_l4 (for future use) */ 5259ad8fef6SThomas Petazzoni u32 command; /* Options used by HW for packet transmitting.*/ 5269ad8fef6SThomas Petazzoni u32 reserved2; /* hw_cmd - (for future use, PMT) */ 5279ad8fef6SThomas Petazzoni u32 buf_phys_addr; /* Physical addr of transmitted buffer */ 5289ad8fef6SThomas Petazzoni u32 reserved3[4]; /* Reserved - (for future use) */ 5299ad8fef6SThomas Petazzoni }; 5309ad8fef6SThomas Petazzoni 5319ad8fef6SThomas Petazzoni struct mvneta_rx_desc { 5329ad8fef6SThomas Petazzoni u16 data_size; /* Size of received packet in bytes */ 5339ad8fef6SThomas Petazzoni u16 reserved1; /* pnc_info - (for future use, PnC) */ 5349ad8fef6SThomas Petazzoni u32 status; /* Info about received packet */ 5359ad8fef6SThomas Petazzoni 5369ad8fef6SThomas Petazzoni u32 reserved2; /* pnc_flow_id (for future use, PnC) */ 5379ad8fef6SThomas Petazzoni u32 buf_phys_addr; /* Physical address of the buffer */ 5389ad8fef6SThomas Petazzoni 5399ad8fef6SThomas Petazzoni u16 reserved4; /* csum_l4 - (for future use, PnC) */ 5409ad8fef6SThomas Petazzoni u16 reserved3; /* prefetch_cmd, for future use */ 5419ad8fef6SThomas Petazzoni u32 buf_cookie; /* cookie for access to RX buffer in rx path */ 5429ad8fef6SThomas Petazzoni 5439ad8fef6SThomas Petazzoni u32 reserved5; /* pnc_extra PnC (for future use, PnC) */ 5449ad8fef6SThomas Petazzoni u32 reserved6; /* hw_cmd (for future use, PnC and HWF) */ 5459ad8fef6SThomas Petazzoni }; 5469ad8fef6SThomas Petazzoni #endif 547c5aff182SThomas Petazzoni 548c5aff182SThomas Petazzoni struct mvneta_tx_queue { 549c5aff182SThomas Petazzoni /* Number of this TX queue, in the range 0-7 */ 550c5aff182SThomas Petazzoni u8 id; 551c5aff182SThomas Petazzoni 552c5aff182SThomas Petazzoni /* Number of TX DMA descriptors in the descriptor ring */ 553c5aff182SThomas Petazzoni int size; 554c5aff182SThomas Petazzoni 555c5aff182SThomas Petazzoni /* Number of currently used TX DMA descriptor in the 5566a20c175SThomas Petazzoni * descriptor ring 5576a20c175SThomas Petazzoni */ 558c5aff182SThomas Petazzoni int count; 5592a90f7e1SSimon Guinot int pending; 5608eef5f97SEzequiel Garcia int tx_stop_threshold; 5618eef5f97SEzequiel Garcia int tx_wake_threshold; 562c5aff182SThomas Petazzoni 563c5aff182SThomas Petazzoni /* Array of transmitted skb */ 564c5aff182SThomas Petazzoni struct sk_buff **tx_skb; 565c5aff182SThomas Petazzoni 566c5aff182SThomas Petazzoni /* Index of last TX DMA descriptor that was inserted */ 567c5aff182SThomas Petazzoni int txq_put_index; 568c5aff182SThomas Petazzoni 569c5aff182SThomas Petazzoni /* Index of the TX DMA descriptor to be cleaned up */ 570c5aff182SThomas Petazzoni int txq_get_index; 571c5aff182SThomas Petazzoni 572c5aff182SThomas Petazzoni u32 done_pkts_coal; 573c5aff182SThomas Petazzoni 574c5aff182SThomas Petazzoni /* Virtual address of the TX DMA descriptors array */ 575c5aff182SThomas Petazzoni struct mvneta_tx_desc *descs; 576c5aff182SThomas Petazzoni 577c5aff182SThomas Petazzoni /* DMA address of the TX DMA descriptors array */ 578c5aff182SThomas Petazzoni dma_addr_t descs_phys; 579c5aff182SThomas Petazzoni 580c5aff182SThomas Petazzoni /* Index of the last TX DMA descriptor */ 581c5aff182SThomas Petazzoni int last_desc; 582c5aff182SThomas Petazzoni 583c5aff182SThomas Petazzoni /* Index of the next TX DMA descriptor to process */ 584c5aff182SThomas Petazzoni int next_desc_to_proc; 5852adb719dSEzequiel Garcia 5862adb719dSEzequiel Garcia /* DMA buffers for TSO headers */ 5872adb719dSEzequiel Garcia char *tso_hdrs; 5882adb719dSEzequiel Garcia 5892adb719dSEzequiel Garcia /* DMA address of TSO headers */ 5902adb719dSEzequiel Garcia dma_addr_t tso_hdrs_phys; 59150bf8cb6SGregory CLEMENT 59250bf8cb6SGregory CLEMENT /* Affinity mask for CPUs*/ 59350bf8cb6SGregory CLEMENT cpumask_t affinity_mask; 594c5aff182SThomas Petazzoni }; 595c5aff182SThomas Petazzoni 596c5aff182SThomas Petazzoni struct mvneta_rx_queue { 597c5aff182SThomas Petazzoni /* rx queue number, in the range 0-7 */ 598c5aff182SThomas Petazzoni u8 id; 599c5aff182SThomas Petazzoni 600c5aff182SThomas Petazzoni /* num of rx descriptors in the rx descriptor ring */ 601c5aff182SThomas Petazzoni int size; 602c5aff182SThomas Petazzoni 603c5aff182SThomas Petazzoni u32 pkts_coal; 604c5aff182SThomas Petazzoni u32 time_coal; 605c5aff182SThomas Petazzoni 606f88bee1cSGregory CLEMENT /* Virtual address of the RX buffer */ 607f88bee1cSGregory CLEMENT void **buf_virt_addr; 608f88bee1cSGregory CLEMENT 609c5aff182SThomas Petazzoni /* Virtual address of the RX DMA descriptors array */ 610c5aff182SThomas Petazzoni struct mvneta_rx_desc *descs; 611c5aff182SThomas Petazzoni 612c5aff182SThomas Petazzoni /* DMA address of the RX DMA descriptors array */ 613c5aff182SThomas Petazzoni dma_addr_t descs_phys; 614c5aff182SThomas Petazzoni 615c5aff182SThomas Petazzoni /* Index of the last RX DMA descriptor */ 616c5aff182SThomas Petazzoni int last_desc; 617c5aff182SThomas Petazzoni 618c5aff182SThomas Petazzoni /* Index of the next RX DMA descriptor to process */ 619c5aff182SThomas Petazzoni int next_desc_to_proc; 62017a96da6SGregory CLEMENT 621562e2f46SYelena Krivosheev /* Index of first RX DMA descriptor to refill */ 622562e2f46SYelena Krivosheev int first_to_refill; 623562e2f46SYelena Krivosheev u32 refill_num; 624562e2f46SYelena Krivosheev 625562e2f46SYelena Krivosheev /* pointer to uncomplete skb buffer */ 626562e2f46SYelena Krivosheev struct sk_buff *skb; 627562e2f46SYelena Krivosheev int left_size; 628562e2f46SYelena Krivosheev 62917a96da6SGregory CLEMENT /* error counters */ 63017a96da6SGregory CLEMENT u32 skb_alloc_err; 63117a96da6SGregory CLEMENT u32 refill_err; 632c5aff182SThomas Petazzoni }; 633c5aff182SThomas Petazzoni 63484a3f4dbSSebastian Andrzej Siewior static enum cpuhp_state online_hpstate; 635edadb7faSEzequiel Garcia /* The hardware supports eight (8) rx queues, but we are only allowing 636edadb7faSEzequiel Garcia * the first one to be used. Therefore, let's just allocate one queue. 637edadb7faSEzequiel Garcia */ 638d8936657SMaxime Ripard static int rxq_number = 8; 639c5aff182SThomas Petazzoni static int txq_number = 8; 640c5aff182SThomas Petazzoni 641c5aff182SThomas Petazzoni static int rxq_def; 642c5aff182SThomas Petazzoni 643f19fadfcSwilly tarreau static int rx_copybreak __read_mostly = 256; 644562e2f46SYelena Krivosheev static int rx_header_size __read_mostly = 128; 645f19fadfcSwilly tarreau 646dc35a10fSMarcin Wojtas /* HW BM need that each port be identify by a unique ID */ 647dc35a10fSMarcin Wojtas static int global_port_id; 648dc35a10fSMarcin Wojtas 649c5aff182SThomas Petazzoni #define MVNETA_DRIVER_NAME "mvneta" 650c5aff182SThomas Petazzoni #define MVNETA_DRIVER_VERSION "1.0" 651c5aff182SThomas Petazzoni 652c5aff182SThomas Petazzoni /* Utility/helper methods */ 653c5aff182SThomas Petazzoni 654c5aff182SThomas Petazzoni /* Write helper method */ 655c5aff182SThomas Petazzoni static void mvreg_write(struct mvneta_port *pp, u32 offset, u32 data) 656c5aff182SThomas Petazzoni { 657c5aff182SThomas Petazzoni writel(data, pp->base + offset); 658c5aff182SThomas Petazzoni } 659c5aff182SThomas Petazzoni 660c5aff182SThomas Petazzoni /* Read helper method */ 661c5aff182SThomas Petazzoni static u32 mvreg_read(struct mvneta_port *pp, u32 offset) 662c5aff182SThomas Petazzoni { 663c5aff182SThomas Petazzoni return readl(pp->base + offset); 664c5aff182SThomas Petazzoni } 665c5aff182SThomas Petazzoni 666c5aff182SThomas Petazzoni /* Increment txq get counter */ 667c5aff182SThomas Petazzoni static void mvneta_txq_inc_get(struct mvneta_tx_queue *txq) 668c5aff182SThomas Petazzoni { 669c5aff182SThomas Petazzoni txq->txq_get_index++; 670c5aff182SThomas Petazzoni if (txq->txq_get_index == txq->size) 671c5aff182SThomas Petazzoni txq->txq_get_index = 0; 672c5aff182SThomas Petazzoni } 673c5aff182SThomas Petazzoni 674c5aff182SThomas Petazzoni /* Increment txq put counter */ 675c5aff182SThomas Petazzoni static void mvneta_txq_inc_put(struct mvneta_tx_queue *txq) 676c5aff182SThomas Petazzoni { 677c5aff182SThomas Petazzoni txq->txq_put_index++; 678c5aff182SThomas Petazzoni if (txq->txq_put_index == txq->size) 679c5aff182SThomas Petazzoni txq->txq_put_index = 0; 680c5aff182SThomas Petazzoni } 681c5aff182SThomas Petazzoni 682c5aff182SThomas Petazzoni 683c5aff182SThomas Petazzoni /* Clear all MIB counters */ 684c5aff182SThomas Petazzoni static void mvneta_mib_counters_clear(struct mvneta_port *pp) 685c5aff182SThomas Petazzoni { 686c5aff182SThomas Petazzoni int i; 687c5aff182SThomas Petazzoni u32 dummy; 688c5aff182SThomas Petazzoni 689c5aff182SThomas Petazzoni /* Perform dummy reads from MIB counters */ 690c5aff182SThomas Petazzoni for (i = 0; i < MVNETA_MIB_LATE_COLLISION; i += 4) 691c5aff182SThomas Petazzoni dummy = mvreg_read(pp, (MVNETA_MIB_COUNTERS_BASE + i)); 692e483911fSAndrew Lunn dummy = mvreg_read(pp, MVNETA_RX_DISCARD_FRAME_COUNT); 693e483911fSAndrew Lunn dummy = mvreg_read(pp, MVNETA_OVERRUN_FRAME_COUNT); 694c5aff182SThomas Petazzoni } 695c5aff182SThomas Petazzoni 696c5aff182SThomas Petazzoni /* Get System Network Statistics */ 697bc1f4470Sstephen hemminger static void 6982dc0d2b4SBaoyou Xie mvneta_get_stats64(struct net_device *dev, 699c5aff182SThomas Petazzoni struct rtnl_link_stats64 *stats) 700c5aff182SThomas Petazzoni { 701c5aff182SThomas Petazzoni struct mvneta_port *pp = netdev_priv(dev); 702c5aff182SThomas Petazzoni unsigned int start; 70374c41b04Swilly tarreau int cpu; 704c5aff182SThomas Petazzoni 70574c41b04Swilly tarreau for_each_possible_cpu(cpu) { 70674c41b04Swilly tarreau struct mvneta_pcpu_stats *cpu_stats; 70774c41b04Swilly tarreau u64 rx_packets; 70874c41b04Swilly tarreau u64 rx_bytes; 70974c41b04Swilly tarreau u64 tx_packets; 71074c41b04Swilly tarreau u64 tx_bytes; 711c5aff182SThomas Petazzoni 71274c41b04Swilly tarreau cpu_stats = per_cpu_ptr(pp->stats, cpu); 713c5aff182SThomas Petazzoni do { 71457a7744eSEric W. Biederman start = u64_stats_fetch_begin_irq(&cpu_stats->syncp); 71574c41b04Swilly tarreau rx_packets = cpu_stats->rx_packets; 71674c41b04Swilly tarreau rx_bytes = cpu_stats->rx_bytes; 71774c41b04Swilly tarreau tx_packets = cpu_stats->tx_packets; 71874c41b04Swilly tarreau tx_bytes = cpu_stats->tx_bytes; 71957a7744eSEric W. Biederman } while (u64_stats_fetch_retry_irq(&cpu_stats->syncp, start)); 720c5aff182SThomas Petazzoni 72174c41b04Swilly tarreau stats->rx_packets += rx_packets; 72274c41b04Swilly tarreau stats->rx_bytes += rx_bytes; 72374c41b04Swilly tarreau stats->tx_packets += tx_packets; 72474c41b04Swilly tarreau stats->tx_bytes += tx_bytes; 72574c41b04Swilly tarreau } 726c5aff182SThomas Petazzoni 727c5aff182SThomas Petazzoni stats->rx_errors = dev->stats.rx_errors; 728c5aff182SThomas Petazzoni stats->rx_dropped = dev->stats.rx_dropped; 729c5aff182SThomas Petazzoni 730c5aff182SThomas Petazzoni stats->tx_dropped = dev->stats.tx_dropped; 731c5aff182SThomas Petazzoni } 732c5aff182SThomas Petazzoni 733c5aff182SThomas Petazzoni /* Rx descriptors helper methods */ 734c5aff182SThomas Petazzoni 7355428213cSwilly tarreau /* Checks whether the RX descriptor having this status is both the first 7365428213cSwilly tarreau * and the last descriptor for the RX packet. Each RX packet is currently 737c5aff182SThomas Petazzoni * received through a single RX descriptor, so not having each RX 738c5aff182SThomas Petazzoni * descriptor with its first and last bits set is an error 739c5aff182SThomas Petazzoni */ 7405428213cSwilly tarreau static int mvneta_rxq_desc_is_first_last(u32 status) 741c5aff182SThomas Petazzoni { 7425428213cSwilly tarreau return (status & MVNETA_RXD_FIRST_LAST_DESC) == 743c5aff182SThomas Petazzoni MVNETA_RXD_FIRST_LAST_DESC; 744c5aff182SThomas Petazzoni } 745c5aff182SThomas Petazzoni 746c5aff182SThomas Petazzoni /* Add number of descriptors ready to receive new packets */ 747c5aff182SThomas Petazzoni static void mvneta_rxq_non_occup_desc_add(struct mvneta_port *pp, 748c5aff182SThomas Petazzoni struct mvneta_rx_queue *rxq, 749c5aff182SThomas Petazzoni int ndescs) 750c5aff182SThomas Petazzoni { 751c5aff182SThomas Petazzoni /* Only MVNETA_RXQ_ADD_NON_OCCUPIED_MAX (255) descriptors can 7526a20c175SThomas Petazzoni * be added at once 7536a20c175SThomas Petazzoni */ 754c5aff182SThomas Petazzoni while (ndescs > MVNETA_RXQ_ADD_NON_OCCUPIED_MAX) { 755c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id), 756c5aff182SThomas Petazzoni (MVNETA_RXQ_ADD_NON_OCCUPIED_MAX << 757c5aff182SThomas Petazzoni MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT)); 758c5aff182SThomas Petazzoni ndescs -= MVNETA_RXQ_ADD_NON_OCCUPIED_MAX; 759c5aff182SThomas Petazzoni } 760c5aff182SThomas Petazzoni 761c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id), 762c5aff182SThomas Petazzoni (ndescs << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT)); 763c5aff182SThomas Petazzoni } 764c5aff182SThomas Petazzoni 765c5aff182SThomas Petazzoni /* Get number of RX descriptors occupied by received packets */ 766c5aff182SThomas Petazzoni static int mvneta_rxq_busy_desc_num_get(struct mvneta_port *pp, 767c5aff182SThomas Petazzoni struct mvneta_rx_queue *rxq) 768c5aff182SThomas Petazzoni { 769c5aff182SThomas Petazzoni u32 val; 770c5aff182SThomas Petazzoni 771c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_RXQ_STATUS_REG(rxq->id)); 772c5aff182SThomas Petazzoni return val & MVNETA_RXQ_OCCUPIED_ALL_MASK; 773c5aff182SThomas Petazzoni } 774c5aff182SThomas Petazzoni 7756a20c175SThomas Petazzoni /* Update num of rx desc called upon return from rx path or 776c5aff182SThomas Petazzoni * from mvneta_rxq_drop_pkts(). 777c5aff182SThomas Petazzoni */ 778c5aff182SThomas Petazzoni static void mvneta_rxq_desc_num_update(struct mvneta_port *pp, 779c5aff182SThomas Petazzoni struct mvneta_rx_queue *rxq, 780c5aff182SThomas Petazzoni int rx_done, int rx_filled) 781c5aff182SThomas Petazzoni { 782c5aff182SThomas Petazzoni u32 val; 783c5aff182SThomas Petazzoni 784c5aff182SThomas Petazzoni if ((rx_done <= 0xff) && (rx_filled <= 0xff)) { 785c5aff182SThomas Petazzoni val = rx_done | 786c5aff182SThomas Petazzoni (rx_filled << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT); 787c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id), val); 788c5aff182SThomas Petazzoni return; 789c5aff182SThomas Petazzoni } 790c5aff182SThomas Petazzoni 791c5aff182SThomas Petazzoni /* Only 255 descriptors can be added at once */ 792c5aff182SThomas Petazzoni while ((rx_done > 0) || (rx_filled > 0)) { 793c5aff182SThomas Petazzoni if (rx_done <= 0xff) { 794c5aff182SThomas Petazzoni val = rx_done; 795c5aff182SThomas Petazzoni rx_done = 0; 796c5aff182SThomas Petazzoni } else { 797c5aff182SThomas Petazzoni val = 0xff; 798c5aff182SThomas Petazzoni rx_done -= 0xff; 799c5aff182SThomas Petazzoni } 800c5aff182SThomas Petazzoni if (rx_filled <= 0xff) { 801c5aff182SThomas Petazzoni val |= rx_filled << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT; 802c5aff182SThomas Petazzoni rx_filled = 0; 803c5aff182SThomas Petazzoni } else { 804c5aff182SThomas Petazzoni val |= 0xff << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT; 805c5aff182SThomas Petazzoni rx_filled -= 0xff; 806c5aff182SThomas Petazzoni } 807c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id), val); 808c5aff182SThomas Petazzoni } 809c5aff182SThomas Petazzoni } 810c5aff182SThomas Petazzoni 811c5aff182SThomas Petazzoni /* Get pointer to next RX descriptor to be processed by SW */ 812c5aff182SThomas Petazzoni static struct mvneta_rx_desc * 813c5aff182SThomas Petazzoni mvneta_rxq_next_desc_get(struct mvneta_rx_queue *rxq) 814c5aff182SThomas Petazzoni { 815c5aff182SThomas Petazzoni int rx_desc = rxq->next_desc_to_proc; 816c5aff182SThomas Petazzoni 817c5aff182SThomas Petazzoni rxq->next_desc_to_proc = MVNETA_QUEUE_NEXT_DESC(rxq, rx_desc); 81834e4179dSwilly tarreau prefetch(rxq->descs + rxq->next_desc_to_proc); 819c5aff182SThomas Petazzoni return rxq->descs + rx_desc; 820c5aff182SThomas Petazzoni } 821c5aff182SThomas Petazzoni 822c5aff182SThomas Petazzoni /* Change maximum receive size of the port. */ 823c5aff182SThomas Petazzoni static void mvneta_max_rx_size_set(struct mvneta_port *pp, int max_rx_size) 824c5aff182SThomas Petazzoni { 825c5aff182SThomas Petazzoni u32 val; 826c5aff182SThomas Petazzoni 827c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_GMAC_CTRL_0); 828c5aff182SThomas Petazzoni val &= ~MVNETA_GMAC_MAX_RX_SIZE_MASK; 829c5aff182SThomas Petazzoni val |= ((max_rx_size - MVNETA_MH_SIZE) / 2) << 830c5aff182SThomas Petazzoni MVNETA_GMAC_MAX_RX_SIZE_SHIFT; 831c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_GMAC_CTRL_0, val); 832c5aff182SThomas Petazzoni } 833c5aff182SThomas Petazzoni 834c5aff182SThomas Petazzoni 835c5aff182SThomas Petazzoni /* Set rx queue offset */ 836c5aff182SThomas Petazzoni static void mvneta_rxq_offset_set(struct mvneta_port *pp, 837c5aff182SThomas Petazzoni struct mvneta_rx_queue *rxq, 838c5aff182SThomas Petazzoni int offset) 839c5aff182SThomas Petazzoni { 840c5aff182SThomas Petazzoni u32 val; 841c5aff182SThomas Petazzoni 842c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_RXQ_CONFIG_REG(rxq->id)); 843c5aff182SThomas Petazzoni val &= ~MVNETA_RXQ_PKT_OFFSET_ALL_MASK; 844c5aff182SThomas Petazzoni 845c5aff182SThomas Petazzoni /* Offset is in */ 846c5aff182SThomas Petazzoni val |= MVNETA_RXQ_PKT_OFFSET_MASK(offset >> 3); 847c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_RXQ_CONFIG_REG(rxq->id), val); 848c5aff182SThomas Petazzoni } 849c5aff182SThomas Petazzoni 850c5aff182SThomas Petazzoni 851c5aff182SThomas Petazzoni /* Tx descriptors helper methods */ 852c5aff182SThomas Petazzoni 853c5aff182SThomas Petazzoni /* Update HW with number of TX descriptors to be sent */ 854c5aff182SThomas Petazzoni static void mvneta_txq_pend_desc_add(struct mvneta_port *pp, 855c5aff182SThomas Petazzoni struct mvneta_tx_queue *txq, 856c5aff182SThomas Petazzoni int pend_desc) 857c5aff182SThomas Petazzoni { 858c5aff182SThomas Petazzoni u32 val; 859c5aff182SThomas Petazzoni 8600d63785cSSimon Guinot pend_desc += txq->pending; 8610d63785cSSimon Guinot 8620d63785cSSimon Guinot /* Only 255 Tx descriptors can be added at once */ 8630d63785cSSimon Guinot do { 8640d63785cSSimon Guinot val = min(pend_desc, 255); 865c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val); 8660d63785cSSimon Guinot pend_desc -= val; 8670d63785cSSimon Guinot } while (pend_desc > 0); 8682a90f7e1SSimon Guinot txq->pending = 0; 869c5aff182SThomas Petazzoni } 870c5aff182SThomas Petazzoni 871c5aff182SThomas Petazzoni /* Get pointer to next TX descriptor to be processed (send) by HW */ 872c5aff182SThomas Petazzoni static struct mvneta_tx_desc * 873c5aff182SThomas Petazzoni mvneta_txq_next_desc_get(struct mvneta_tx_queue *txq) 874c5aff182SThomas Petazzoni { 875c5aff182SThomas Petazzoni int tx_desc = txq->next_desc_to_proc; 876c5aff182SThomas Petazzoni 877c5aff182SThomas Petazzoni txq->next_desc_to_proc = MVNETA_QUEUE_NEXT_DESC(txq, tx_desc); 878c5aff182SThomas Petazzoni return txq->descs + tx_desc; 879c5aff182SThomas Petazzoni } 880c5aff182SThomas Petazzoni 881c5aff182SThomas Petazzoni /* Release the last allocated TX descriptor. Useful to handle DMA 8826a20c175SThomas Petazzoni * mapping failures in the TX path. 8836a20c175SThomas Petazzoni */ 884c5aff182SThomas Petazzoni static void mvneta_txq_desc_put(struct mvneta_tx_queue *txq) 885c5aff182SThomas Petazzoni { 886c5aff182SThomas Petazzoni if (txq->next_desc_to_proc == 0) 887c5aff182SThomas Petazzoni txq->next_desc_to_proc = txq->last_desc - 1; 888c5aff182SThomas Petazzoni else 889c5aff182SThomas Petazzoni txq->next_desc_to_proc--; 890c5aff182SThomas Petazzoni } 891c5aff182SThomas Petazzoni 892c5aff182SThomas Petazzoni /* Set rxq buf size */ 893c5aff182SThomas Petazzoni static void mvneta_rxq_buf_size_set(struct mvneta_port *pp, 894c5aff182SThomas Petazzoni struct mvneta_rx_queue *rxq, 895c5aff182SThomas Petazzoni int buf_size) 896c5aff182SThomas Petazzoni { 897c5aff182SThomas Petazzoni u32 val; 898c5aff182SThomas Petazzoni 899c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_RXQ_SIZE_REG(rxq->id)); 900c5aff182SThomas Petazzoni 901c5aff182SThomas Petazzoni val &= ~MVNETA_RXQ_BUF_SIZE_MASK; 902c5aff182SThomas Petazzoni val |= ((buf_size >> 3) << MVNETA_RXQ_BUF_SIZE_SHIFT); 903c5aff182SThomas Petazzoni 904c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_RXQ_SIZE_REG(rxq->id), val); 905c5aff182SThomas Petazzoni } 906c5aff182SThomas Petazzoni 907c5aff182SThomas Petazzoni /* Disable buffer management (BM) */ 908c5aff182SThomas Petazzoni static void mvneta_rxq_bm_disable(struct mvneta_port *pp, 909c5aff182SThomas Petazzoni struct mvneta_rx_queue *rxq) 910c5aff182SThomas Petazzoni { 911c5aff182SThomas Petazzoni u32 val; 912c5aff182SThomas Petazzoni 913c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_RXQ_CONFIG_REG(rxq->id)); 914c5aff182SThomas Petazzoni val &= ~MVNETA_RXQ_HW_BUF_ALLOC; 915c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_RXQ_CONFIG_REG(rxq->id), val); 916c5aff182SThomas Petazzoni } 917c5aff182SThomas Petazzoni 918dc35a10fSMarcin Wojtas /* Enable buffer management (BM) */ 919dc35a10fSMarcin Wojtas static void mvneta_rxq_bm_enable(struct mvneta_port *pp, 920dc35a10fSMarcin Wojtas struct mvneta_rx_queue *rxq) 921dc35a10fSMarcin Wojtas { 922dc35a10fSMarcin Wojtas u32 val; 923dc35a10fSMarcin Wojtas 924dc35a10fSMarcin Wojtas val = mvreg_read(pp, MVNETA_RXQ_CONFIG_REG(rxq->id)); 925dc35a10fSMarcin Wojtas val |= MVNETA_RXQ_HW_BUF_ALLOC; 926dc35a10fSMarcin Wojtas mvreg_write(pp, MVNETA_RXQ_CONFIG_REG(rxq->id), val); 927dc35a10fSMarcin Wojtas } 928dc35a10fSMarcin Wojtas 929dc35a10fSMarcin Wojtas /* Notify HW about port's assignment of pool for bigger packets */ 930dc35a10fSMarcin Wojtas static void mvneta_rxq_long_pool_set(struct mvneta_port *pp, 931dc35a10fSMarcin Wojtas struct mvneta_rx_queue *rxq) 932dc35a10fSMarcin Wojtas { 933dc35a10fSMarcin Wojtas u32 val; 934dc35a10fSMarcin Wojtas 935dc35a10fSMarcin Wojtas val = mvreg_read(pp, MVNETA_RXQ_CONFIG_REG(rxq->id)); 936dc35a10fSMarcin Wojtas val &= ~MVNETA_RXQ_LONG_POOL_ID_MASK; 937dc35a10fSMarcin Wojtas val |= (pp->pool_long->id << MVNETA_RXQ_LONG_POOL_ID_SHIFT); 938dc35a10fSMarcin Wojtas 939dc35a10fSMarcin Wojtas mvreg_write(pp, MVNETA_RXQ_CONFIG_REG(rxq->id), val); 940dc35a10fSMarcin Wojtas } 941dc35a10fSMarcin Wojtas 942dc35a10fSMarcin Wojtas /* Notify HW about port's assignment of pool for smaller packets */ 943dc35a10fSMarcin Wojtas static void mvneta_rxq_short_pool_set(struct mvneta_port *pp, 944dc35a10fSMarcin Wojtas struct mvneta_rx_queue *rxq) 945dc35a10fSMarcin Wojtas { 946dc35a10fSMarcin Wojtas u32 val; 947dc35a10fSMarcin Wojtas 948dc35a10fSMarcin Wojtas val = mvreg_read(pp, MVNETA_RXQ_CONFIG_REG(rxq->id)); 949dc35a10fSMarcin Wojtas val &= ~MVNETA_RXQ_SHORT_POOL_ID_MASK; 950dc35a10fSMarcin Wojtas val |= (pp->pool_short->id << MVNETA_RXQ_SHORT_POOL_ID_SHIFT); 951dc35a10fSMarcin Wojtas 952dc35a10fSMarcin Wojtas mvreg_write(pp, MVNETA_RXQ_CONFIG_REG(rxq->id), val); 953dc35a10fSMarcin Wojtas } 954dc35a10fSMarcin Wojtas 955dc35a10fSMarcin Wojtas /* Set port's receive buffer size for assigned BM pool */ 956dc35a10fSMarcin Wojtas static inline void mvneta_bm_pool_bufsize_set(struct mvneta_port *pp, 957dc35a10fSMarcin Wojtas int buf_size, 958dc35a10fSMarcin Wojtas u8 pool_id) 959dc35a10fSMarcin Wojtas { 960dc35a10fSMarcin Wojtas u32 val; 961dc35a10fSMarcin Wojtas 962dc35a10fSMarcin Wojtas if (!IS_ALIGNED(buf_size, 8)) { 963dc35a10fSMarcin Wojtas dev_warn(pp->dev->dev.parent, 964dc35a10fSMarcin Wojtas "illegal buf_size value %d, round to %d\n", 965dc35a10fSMarcin Wojtas buf_size, ALIGN(buf_size, 8)); 966dc35a10fSMarcin Wojtas buf_size = ALIGN(buf_size, 8); 967dc35a10fSMarcin Wojtas } 968dc35a10fSMarcin Wojtas 969dc35a10fSMarcin Wojtas val = mvreg_read(pp, MVNETA_PORT_POOL_BUFFER_SZ_REG(pool_id)); 970dc35a10fSMarcin Wojtas val |= buf_size & MVNETA_PORT_POOL_BUFFER_SZ_MASK; 971dc35a10fSMarcin Wojtas mvreg_write(pp, MVNETA_PORT_POOL_BUFFER_SZ_REG(pool_id), val); 972dc35a10fSMarcin Wojtas } 973dc35a10fSMarcin Wojtas 974dc35a10fSMarcin Wojtas /* Configure MBUS window in order to enable access BM internal SRAM */ 975dc35a10fSMarcin Wojtas static int mvneta_mbus_io_win_set(struct mvneta_port *pp, u32 base, u32 wsize, 976dc35a10fSMarcin Wojtas u8 target, u8 attr) 977dc35a10fSMarcin Wojtas { 978dc35a10fSMarcin Wojtas u32 win_enable, win_protect; 979dc35a10fSMarcin Wojtas int i; 980dc35a10fSMarcin Wojtas 981dc35a10fSMarcin Wojtas win_enable = mvreg_read(pp, MVNETA_BASE_ADDR_ENABLE); 982dc35a10fSMarcin Wojtas 983dc35a10fSMarcin Wojtas if (pp->bm_win_id < 0) { 984dc35a10fSMarcin Wojtas /* Find first not occupied window */ 985dc35a10fSMarcin Wojtas for (i = 0; i < MVNETA_MAX_DECODE_WIN; i++) { 986dc35a10fSMarcin Wojtas if (win_enable & (1 << i)) { 987dc35a10fSMarcin Wojtas pp->bm_win_id = i; 988dc35a10fSMarcin Wojtas break; 989dc35a10fSMarcin Wojtas } 990dc35a10fSMarcin Wojtas } 991dc35a10fSMarcin Wojtas if (i == MVNETA_MAX_DECODE_WIN) 992dc35a10fSMarcin Wojtas return -ENOMEM; 993dc35a10fSMarcin Wojtas } else { 994dc35a10fSMarcin Wojtas i = pp->bm_win_id; 995dc35a10fSMarcin Wojtas } 996dc35a10fSMarcin Wojtas 997dc35a10fSMarcin Wojtas mvreg_write(pp, MVNETA_WIN_BASE(i), 0); 998dc35a10fSMarcin Wojtas mvreg_write(pp, MVNETA_WIN_SIZE(i), 0); 999dc35a10fSMarcin Wojtas 1000dc35a10fSMarcin Wojtas if (i < 4) 1001dc35a10fSMarcin Wojtas mvreg_write(pp, MVNETA_WIN_REMAP(i), 0); 1002dc35a10fSMarcin Wojtas 1003dc35a10fSMarcin Wojtas mvreg_write(pp, MVNETA_WIN_BASE(i), (base & 0xffff0000) | 1004dc35a10fSMarcin Wojtas (attr << 8) | target); 1005dc35a10fSMarcin Wojtas 1006dc35a10fSMarcin Wojtas mvreg_write(pp, MVNETA_WIN_SIZE(i), (wsize - 1) & 0xffff0000); 1007dc35a10fSMarcin Wojtas 1008dc35a10fSMarcin Wojtas win_protect = mvreg_read(pp, MVNETA_ACCESS_PROTECT_ENABLE); 1009dc35a10fSMarcin Wojtas win_protect |= 3 << (2 * i); 1010dc35a10fSMarcin Wojtas mvreg_write(pp, MVNETA_ACCESS_PROTECT_ENABLE, win_protect); 1011dc35a10fSMarcin Wojtas 1012dc35a10fSMarcin Wojtas win_enable &= ~(1 << i); 1013dc35a10fSMarcin Wojtas mvreg_write(pp, MVNETA_BASE_ADDR_ENABLE, win_enable); 1014dc35a10fSMarcin Wojtas 1015dc35a10fSMarcin Wojtas return 0; 1016dc35a10fSMarcin Wojtas } 1017dc35a10fSMarcin Wojtas 10182636ac3cSMarcin Wojtas static int mvneta_bm_port_mbus_init(struct mvneta_port *pp) 1019dc35a10fSMarcin Wojtas { 10202636ac3cSMarcin Wojtas u32 wsize; 1021dc35a10fSMarcin Wojtas u8 target, attr; 1022dc35a10fSMarcin Wojtas int err; 1023dc35a10fSMarcin Wojtas 1024dc35a10fSMarcin Wojtas /* Get BM window information */ 1025dc35a10fSMarcin Wojtas err = mvebu_mbus_get_io_win_info(pp->bm_priv->bppi_phys_addr, &wsize, 1026dc35a10fSMarcin Wojtas &target, &attr); 1027dc35a10fSMarcin Wojtas if (err < 0) 1028dc35a10fSMarcin Wojtas return err; 1029dc35a10fSMarcin Wojtas 1030dc35a10fSMarcin Wojtas pp->bm_win_id = -1; 1031dc35a10fSMarcin Wojtas 1032dc35a10fSMarcin Wojtas /* Open NETA -> BM window */ 1033dc35a10fSMarcin Wojtas err = mvneta_mbus_io_win_set(pp, pp->bm_priv->bppi_phys_addr, wsize, 1034dc35a10fSMarcin Wojtas target, attr); 1035dc35a10fSMarcin Wojtas if (err < 0) { 1036dc35a10fSMarcin Wojtas netdev_info(pp->dev, "fail to configure mbus window to BM\n"); 1037dc35a10fSMarcin Wojtas return err; 1038dc35a10fSMarcin Wojtas } 10392636ac3cSMarcin Wojtas return 0; 10402636ac3cSMarcin Wojtas } 10412636ac3cSMarcin Wojtas 10422636ac3cSMarcin Wojtas /* Assign and initialize pools for port. In case of fail 10432636ac3cSMarcin Wojtas * buffer manager will remain disabled for current port. 10442636ac3cSMarcin Wojtas */ 10452636ac3cSMarcin Wojtas static int mvneta_bm_port_init(struct platform_device *pdev, 10462636ac3cSMarcin Wojtas struct mvneta_port *pp) 10472636ac3cSMarcin Wojtas { 10482636ac3cSMarcin Wojtas struct device_node *dn = pdev->dev.of_node; 10492636ac3cSMarcin Wojtas u32 long_pool_id, short_pool_id; 10502636ac3cSMarcin Wojtas 10512636ac3cSMarcin Wojtas if (!pp->neta_armada3700) { 10522636ac3cSMarcin Wojtas int ret; 10532636ac3cSMarcin Wojtas 10542636ac3cSMarcin Wojtas ret = mvneta_bm_port_mbus_init(pp); 10552636ac3cSMarcin Wojtas if (ret) 10562636ac3cSMarcin Wojtas return ret; 10572636ac3cSMarcin Wojtas } 1058dc35a10fSMarcin Wojtas 1059dc35a10fSMarcin Wojtas if (of_property_read_u32(dn, "bm,pool-long", &long_pool_id)) { 1060dc35a10fSMarcin Wojtas netdev_info(pp->dev, "missing long pool id\n"); 1061dc35a10fSMarcin Wojtas return -EINVAL; 1062dc35a10fSMarcin Wojtas } 1063dc35a10fSMarcin Wojtas 1064dc35a10fSMarcin Wojtas /* Create port's long pool depending on mtu */ 1065dc35a10fSMarcin Wojtas pp->pool_long = mvneta_bm_pool_use(pp->bm_priv, long_pool_id, 1066dc35a10fSMarcin Wojtas MVNETA_BM_LONG, pp->id, 1067dc35a10fSMarcin Wojtas MVNETA_RX_PKT_SIZE(pp->dev->mtu)); 1068dc35a10fSMarcin Wojtas if (!pp->pool_long) { 1069dc35a10fSMarcin Wojtas netdev_info(pp->dev, "fail to obtain long pool for port\n"); 1070dc35a10fSMarcin Wojtas return -ENOMEM; 1071dc35a10fSMarcin Wojtas } 1072dc35a10fSMarcin Wojtas 1073dc35a10fSMarcin Wojtas pp->pool_long->port_map |= 1 << pp->id; 1074dc35a10fSMarcin Wojtas 1075dc35a10fSMarcin Wojtas mvneta_bm_pool_bufsize_set(pp, pp->pool_long->buf_size, 1076dc35a10fSMarcin Wojtas pp->pool_long->id); 1077dc35a10fSMarcin Wojtas 1078dc35a10fSMarcin Wojtas /* If short pool id is not defined, assume using single pool */ 1079dc35a10fSMarcin Wojtas if (of_property_read_u32(dn, "bm,pool-short", &short_pool_id)) 1080dc35a10fSMarcin Wojtas short_pool_id = long_pool_id; 1081dc35a10fSMarcin Wojtas 1082dc35a10fSMarcin Wojtas /* Create port's short pool */ 1083dc35a10fSMarcin Wojtas pp->pool_short = mvneta_bm_pool_use(pp->bm_priv, short_pool_id, 1084dc35a10fSMarcin Wojtas MVNETA_BM_SHORT, pp->id, 1085dc35a10fSMarcin Wojtas MVNETA_BM_SHORT_PKT_SIZE); 1086dc35a10fSMarcin Wojtas if (!pp->pool_short) { 1087dc35a10fSMarcin Wojtas netdev_info(pp->dev, "fail to obtain short pool for port\n"); 1088dc35a10fSMarcin Wojtas mvneta_bm_pool_destroy(pp->bm_priv, pp->pool_long, 1 << pp->id); 1089dc35a10fSMarcin Wojtas return -ENOMEM; 1090dc35a10fSMarcin Wojtas } 1091dc35a10fSMarcin Wojtas 1092dc35a10fSMarcin Wojtas if (short_pool_id != long_pool_id) { 1093dc35a10fSMarcin Wojtas pp->pool_short->port_map |= 1 << pp->id; 1094dc35a10fSMarcin Wojtas mvneta_bm_pool_bufsize_set(pp, pp->pool_short->buf_size, 1095dc35a10fSMarcin Wojtas pp->pool_short->id); 1096dc35a10fSMarcin Wojtas } 1097dc35a10fSMarcin Wojtas 1098dc35a10fSMarcin Wojtas return 0; 1099dc35a10fSMarcin Wojtas } 1100dc35a10fSMarcin Wojtas 1101dc35a10fSMarcin Wojtas /* Update settings of a pool for bigger packets */ 1102dc35a10fSMarcin Wojtas static void mvneta_bm_update_mtu(struct mvneta_port *pp, int mtu) 1103dc35a10fSMarcin Wojtas { 1104dc35a10fSMarcin Wojtas struct mvneta_bm_pool *bm_pool = pp->pool_long; 1105baa11ebcSGregory CLEMENT struct hwbm_pool *hwbm_pool = &bm_pool->hwbm_pool; 1106dc35a10fSMarcin Wojtas int num; 1107dc35a10fSMarcin Wojtas 1108dc35a10fSMarcin Wojtas /* Release all buffers from long pool */ 1109dc35a10fSMarcin Wojtas mvneta_bm_bufs_free(pp->bm_priv, bm_pool, 1 << pp->id); 1110baa11ebcSGregory CLEMENT if (hwbm_pool->buf_num) { 1111dc35a10fSMarcin Wojtas WARN(1, "cannot free all buffers in pool %d\n", 1112dc35a10fSMarcin Wojtas bm_pool->id); 1113dc35a10fSMarcin Wojtas goto bm_mtu_err; 1114dc35a10fSMarcin Wojtas } 1115dc35a10fSMarcin Wojtas 1116dc35a10fSMarcin Wojtas bm_pool->pkt_size = MVNETA_RX_PKT_SIZE(mtu); 1117dc35a10fSMarcin Wojtas bm_pool->buf_size = MVNETA_RX_BUF_SIZE(bm_pool->pkt_size); 1118baa11ebcSGregory CLEMENT hwbm_pool->frag_size = SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) + 1119dc35a10fSMarcin Wojtas SKB_DATA_ALIGN(MVNETA_RX_BUF_SIZE(bm_pool->pkt_size)); 1120dc35a10fSMarcin Wojtas 1121dc35a10fSMarcin Wojtas /* Fill entire long pool */ 11226dcdd884SSebastian Andrzej Siewior num = hwbm_pool_add(hwbm_pool, hwbm_pool->size); 1123baa11ebcSGregory CLEMENT if (num != hwbm_pool->size) { 1124dc35a10fSMarcin Wojtas WARN(1, "pool %d: %d of %d allocated\n", 1125baa11ebcSGregory CLEMENT bm_pool->id, num, hwbm_pool->size); 1126dc35a10fSMarcin Wojtas goto bm_mtu_err; 1127dc35a10fSMarcin Wojtas } 1128dc35a10fSMarcin Wojtas mvneta_bm_pool_bufsize_set(pp, bm_pool->buf_size, bm_pool->id); 1129dc35a10fSMarcin Wojtas 1130dc35a10fSMarcin Wojtas return; 1131dc35a10fSMarcin Wojtas 1132dc35a10fSMarcin Wojtas bm_mtu_err: 1133dc35a10fSMarcin Wojtas mvneta_bm_pool_destroy(pp->bm_priv, pp->pool_long, 1 << pp->id); 1134dc35a10fSMarcin Wojtas mvneta_bm_pool_destroy(pp->bm_priv, pp->pool_short, 1 << pp->id); 1135dc35a10fSMarcin Wojtas 1136dc35a10fSMarcin Wojtas pp->bm_priv = NULL; 1137dc35a10fSMarcin Wojtas mvreg_write(pp, MVNETA_ACC_MODE, MVNETA_ACC_MODE_EXT1); 1138dc35a10fSMarcin Wojtas netdev_info(pp->dev, "fail to update MTU, fall back to software BM\n"); 1139dc35a10fSMarcin Wojtas } 1140dc35a10fSMarcin Wojtas 1141c5aff182SThomas Petazzoni /* Start the Ethernet port RX and TX activity */ 1142c5aff182SThomas Petazzoni static void mvneta_port_up(struct mvneta_port *pp) 1143c5aff182SThomas Petazzoni { 1144c5aff182SThomas Petazzoni int queue; 1145c5aff182SThomas Petazzoni u32 q_map; 1146c5aff182SThomas Petazzoni 1147c5aff182SThomas Petazzoni /* Enable all initialized TXs. */ 1148c5aff182SThomas Petazzoni q_map = 0; 1149c5aff182SThomas Petazzoni for (queue = 0; queue < txq_number; queue++) { 1150c5aff182SThomas Petazzoni struct mvneta_tx_queue *txq = &pp->txqs[queue]; 1151f95936ccSMarkus Elfring if (txq->descs) 1152c5aff182SThomas Petazzoni q_map |= (1 << queue); 1153c5aff182SThomas Petazzoni } 1154c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_TXQ_CMD, q_map); 1155c5aff182SThomas Petazzoni 1156e81b5e01SYelena Krivosheev q_map = 0; 1157c5aff182SThomas Petazzoni /* Enable all initialized RXQs. */ 11582dcf75e2SGregory CLEMENT for (queue = 0; queue < rxq_number; queue++) { 11592dcf75e2SGregory CLEMENT struct mvneta_rx_queue *rxq = &pp->rxqs[queue]; 11602dcf75e2SGregory CLEMENT 1161f95936ccSMarkus Elfring if (rxq->descs) 11622dcf75e2SGregory CLEMENT q_map |= (1 << queue); 11632dcf75e2SGregory CLEMENT } 11642dcf75e2SGregory CLEMENT mvreg_write(pp, MVNETA_RXQ_CMD, q_map); 1165c5aff182SThomas Petazzoni } 1166c5aff182SThomas Petazzoni 1167c5aff182SThomas Petazzoni /* Stop the Ethernet port activity */ 1168c5aff182SThomas Petazzoni static void mvneta_port_down(struct mvneta_port *pp) 1169c5aff182SThomas Petazzoni { 1170c5aff182SThomas Petazzoni u32 val; 1171c5aff182SThomas Petazzoni int count; 1172c5aff182SThomas Petazzoni 1173c5aff182SThomas Petazzoni /* Stop Rx port activity. Check port Rx activity. */ 1174c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_RXQ_CMD) & MVNETA_RXQ_ENABLE_MASK; 1175c5aff182SThomas Petazzoni 1176c5aff182SThomas Petazzoni /* Issue stop command for active channels only */ 1177c5aff182SThomas Petazzoni if (val != 0) 1178c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_RXQ_CMD, 1179c5aff182SThomas Petazzoni val << MVNETA_RXQ_DISABLE_SHIFT); 1180c5aff182SThomas Petazzoni 1181c5aff182SThomas Petazzoni /* Wait for all Rx activity to terminate. */ 1182c5aff182SThomas Petazzoni count = 0; 1183c5aff182SThomas Petazzoni do { 1184c5aff182SThomas Petazzoni if (count++ >= MVNETA_RX_DISABLE_TIMEOUT_MSEC) { 1185c5aff182SThomas Petazzoni netdev_warn(pp->dev, 11860838abb3SDmitri Epshtein "TIMEOUT for RX stopped ! rx_queue_cmd: 0x%08x\n", 1187c5aff182SThomas Petazzoni val); 1188c5aff182SThomas Petazzoni break; 1189c5aff182SThomas Petazzoni } 1190c5aff182SThomas Petazzoni mdelay(1); 1191c5aff182SThomas Petazzoni 1192c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_RXQ_CMD); 1193a3703fb3SDmitri Epshtein } while (val & MVNETA_RXQ_ENABLE_MASK); 1194c5aff182SThomas Petazzoni 1195c5aff182SThomas Petazzoni /* Stop Tx port activity. Check port Tx activity. Issue stop 11966a20c175SThomas Petazzoni * command for active channels only 11976a20c175SThomas Petazzoni */ 1198c5aff182SThomas Petazzoni val = (mvreg_read(pp, MVNETA_TXQ_CMD)) & MVNETA_TXQ_ENABLE_MASK; 1199c5aff182SThomas Petazzoni 1200c5aff182SThomas Petazzoni if (val != 0) 1201c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_TXQ_CMD, 1202c5aff182SThomas Petazzoni (val << MVNETA_TXQ_DISABLE_SHIFT)); 1203c5aff182SThomas Petazzoni 1204c5aff182SThomas Petazzoni /* Wait for all Tx activity to terminate. */ 1205c5aff182SThomas Petazzoni count = 0; 1206c5aff182SThomas Petazzoni do { 1207c5aff182SThomas Petazzoni if (count++ >= MVNETA_TX_DISABLE_TIMEOUT_MSEC) { 1208c5aff182SThomas Petazzoni netdev_warn(pp->dev, 1209c5aff182SThomas Petazzoni "TIMEOUT for TX stopped status=0x%08x\n", 1210c5aff182SThomas Petazzoni val); 1211c5aff182SThomas Petazzoni break; 1212c5aff182SThomas Petazzoni } 1213c5aff182SThomas Petazzoni mdelay(1); 1214c5aff182SThomas Petazzoni 1215c5aff182SThomas Petazzoni /* Check TX Command reg that all Txqs are stopped */ 1216c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_TXQ_CMD); 1217c5aff182SThomas Petazzoni 1218a3703fb3SDmitri Epshtein } while (val & MVNETA_TXQ_ENABLE_MASK); 1219c5aff182SThomas Petazzoni 1220c5aff182SThomas Petazzoni /* Double check to verify that TX FIFO is empty */ 1221c5aff182SThomas Petazzoni count = 0; 1222c5aff182SThomas Petazzoni do { 1223c5aff182SThomas Petazzoni if (count++ >= MVNETA_TX_FIFO_EMPTY_TIMEOUT) { 1224c5aff182SThomas Petazzoni netdev_warn(pp->dev, 12250838abb3SDmitri Epshtein "TX FIFO empty timeout status=0x%08x\n", 1226c5aff182SThomas Petazzoni val); 1227c5aff182SThomas Petazzoni break; 1228c5aff182SThomas Petazzoni } 1229c5aff182SThomas Petazzoni mdelay(1); 1230c5aff182SThomas Petazzoni 1231c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_PORT_STATUS); 1232c5aff182SThomas Petazzoni } while (!(val & MVNETA_TX_FIFO_EMPTY) && 1233c5aff182SThomas Petazzoni (val & MVNETA_TX_IN_PRGRS)); 1234c5aff182SThomas Petazzoni 1235c5aff182SThomas Petazzoni udelay(200); 1236c5aff182SThomas Petazzoni } 1237c5aff182SThomas Petazzoni 1238c5aff182SThomas Petazzoni /* Enable the port by setting the port enable bit of the MAC control register */ 1239c5aff182SThomas Petazzoni static void mvneta_port_enable(struct mvneta_port *pp) 1240c5aff182SThomas Petazzoni { 1241c5aff182SThomas Petazzoni u32 val; 1242c5aff182SThomas Petazzoni 1243c5aff182SThomas Petazzoni /* Enable port */ 1244c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_GMAC_CTRL_0); 1245c5aff182SThomas Petazzoni val |= MVNETA_GMAC0_PORT_ENABLE; 1246c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_GMAC_CTRL_0, val); 1247c5aff182SThomas Petazzoni } 1248c5aff182SThomas Petazzoni 1249c5aff182SThomas Petazzoni /* Disable the port and wait for about 200 usec before retuning */ 1250c5aff182SThomas Petazzoni static void mvneta_port_disable(struct mvneta_port *pp) 1251c5aff182SThomas Petazzoni { 1252c5aff182SThomas Petazzoni u32 val; 1253c5aff182SThomas Petazzoni 1254c5aff182SThomas Petazzoni /* Reset the Enable bit in the Serial Control Register */ 1255c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_GMAC_CTRL_0); 1256c5aff182SThomas Petazzoni val &= ~MVNETA_GMAC0_PORT_ENABLE; 1257c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_GMAC_CTRL_0, val); 1258c5aff182SThomas Petazzoni 1259c5aff182SThomas Petazzoni udelay(200); 1260c5aff182SThomas Petazzoni } 1261c5aff182SThomas Petazzoni 1262c5aff182SThomas Petazzoni /* Multicast tables methods */ 1263c5aff182SThomas Petazzoni 1264c5aff182SThomas Petazzoni /* Set all entries in Unicast MAC Table; queue==-1 means reject all */ 1265c5aff182SThomas Petazzoni static void mvneta_set_ucast_table(struct mvneta_port *pp, int queue) 1266c5aff182SThomas Petazzoni { 1267c5aff182SThomas Petazzoni int offset; 1268c5aff182SThomas Petazzoni u32 val; 1269c5aff182SThomas Petazzoni 1270c5aff182SThomas Petazzoni if (queue == -1) { 1271c5aff182SThomas Petazzoni val = 0; 1272c5aff182SThomas Petazzoni } else { 1273c5aff182SThomas Petazzoni val = 0x1 | (queue << 1); 1274c5aff182SThomas Petazzoni val |= (val << 24) | (val << 16) | (val << 8); 1275c5aff182SThomas Petazzoni } 1276c5aff182SThomas Petazzoni 1277c5aff182SThomas Petazzoni for (offset = 0; offset <= 0xc; offset += 4) 1278c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_DA_FILT_UCAST_BASE + offset, val); 1279c5aff182SThomas Petazzoni } 1280c5aff182SThomas Petazzoni 1281c5aff182SThomas Petazzoni /* Set all entries in Special Multicast MAC Table; queue==-1 means reject all */ 1282c5aff182SThomas Petazzoni static void mvneta_set_special_mcast_table(struct mvneta_port *pp, int queue) 1283c5aff182SThomas Petazzoni { 1284c5aff182SThomas Petazzoni int offset; 1285c5aff182SThomas Petazzoni u32 val; 1286c5aff182SThomas Petazzoni 1287c5aff182SThomas Petazzoni if (queue == -1) { 1288c5aff182SThomas Petazzoni val = 0; 1289c5aff182SThomas Petazzoni } else { 1290c5aff182SThomas Petazzoni val = 0x1 | (queue << 1); 1291c5aff182SThomas Petazzoni val |= (val << 24) | (val << 16) | (val << 8); 1292c5aff182SThomas Petazzoni } 1293c5aff182SThomas Petazzoni 1294c5aff182SThomas Petazzoni for (offset = 0; offset <= 0xfc; offset += 4) 1295c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_DA_FILT_SPEC_MCAST + offset, val); 1296c5aff182SThomas Petazzoni 1297c5aff182SThomas Petazzoni } 1298c5aff182SThomas Petazzoni 1299c5aff182SThomas Petazzoni /* Set all entries in Other Multicast MAC Table. queue==-1 means reject all */ 1300c5aff182SThomas Petazzoni static void mvneta_set_other_mcast_table(struct mvneta_port *pp, int queue) 1301c5aff182SThomas Petazzoni { 1302c5aff182SThomas Petazzoni int offset; 1303c5aff182SThomas Petazzoni u32 val; 1304c5aff182SThomas Petazzoni 1305c5aff182SThomas Petazzoni if (queue == -1) { 1306c5aff182SThomas Petazzoni memset(pp->mcast_count, 0, sizeof(pp->mcast_count)); 1307c5aff182SThomas Petazzoni val = 0; 1308c5aff182SThomas Petazzoni } else { 1309c5aff182SThomas Petazzoni memset(pp->mcast_count, 1, sizeof(pp->mcast_count)); 1310c5aff182SThomas Petazzoni val = 0x1 | (queue << 1); 1311c5aff182SThomas Petazzoni val |= (val << 24) | (val << 16) | (val << 8); 1312c5aff182SThomas Petazzoni } 1313c5aff182SThomas Petazzoni 1314c5aff182SThomas Petazzoni for (offset = 0; offset <= 0xfc; offset += 4) 1315c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_DA_FILT_OTH_MCAST + offset, val); 1316c5aff182SThomas Petazzoni } 1317c5aff182SThomas Petazzoni 1318db488c10SGregory CLEMENT static void mvneta_percpu_unmask_interrupt(void *arg) 1319db488c10SGregory CLEMENT { 1320db488c10SGregory CLEMENT struct mvneta_port *pp = arg; 1321db488c10SGregory CLEMENT 1322db488c10SGregory CLEMENT /* All the queue are unmasked, but actually only the ones 1323db488c10SGregory CLEMENT * mapped to this CPU will be unmasked 1324db488c10SGregory CLEMENT */ 1325db488c10SGregory CLEMENT mvreg_write(pp, MVNETA_INTR_NEW_MASK, 1326db488c10SGregory CLEMENT MVNETA_RX_INTR_MASK_ALL | 1327db488c10SGregory CLEMENT MVNETA_TX_INTR_MASK_ALL | 1328db488c10SGregory CLEMENT MVNETA_MISCINTR_INTR_MASK); 1329db488c10SGregory CLEMENT } 1330db488c10SGregory CLEMENT 1331db488c10SGregory CLEMENT static void mvneta_percpu_mask_interrupt(void *arg) 1332db488c10SGregory CLEMENT { 1333db488c10SGregory CLEMENT struct mvneta_port *pp = arg; 1334db488c10SGregory CLEMENT 1335db488c10SGregory CLEMENT /* All the queue are masked, but actually only the ones 1336db488c10SGregory CLEMENT * mapped to this CPU will be masked 1337db488c10SGregory CLEMENT */ 1338db488c10SGregory CLEMENT mvreg_write(pp, MVNETA_INTR_NEW_MASK, 0); 1339db488c10SGregory CLEMENT mvreg_write(pp, MVNETA_INTR_OLD_MASK, 0); 1340db488c10SGregory CLEMENT mvreg_write(pp, MVNETA_INTR_MISC_MASK, 0); 1341db488c10SGregory CLEMENT } 1342db488c10SGregory CLEMENT 1343db488c10SGregory CLEMENT static void mvneta_percpu_clear_intr_cause(void *arg) 1344db488c10SGregory CLEMENT { 1345db488c10SGregory CLEMENT struct mvneta_port *pp = arg; 1346db488c10SGregory CLEMENT 1347db488c10SGregory CLEMENT /* All the queue are cleared, but actually only the ones 1348db488c10SGregory CLEMENT * mapped to this CPU will be cleared 1349db488c10SGregory CLEMENT */ 1350db488c10SGregory CLEMENT mvreg_write(pp, MVNETA_INTR_NEW_CAUSE, 0); 1351db488c10SGregory CLEMENT mvreg_write(pp, MVNETA_INTR_MISC_CAUSE, 0); 1352db488c10SGregory CLEMENT mvreg_write(pp, MVNETA_INTR_OLD_CAUSE, 0); 1353db488c10SGregory CLEMENT } 1354db488c10SGregory CLEMENT 1355c5aff182SThomas Petazzoni /* This method sets defaults to the NETA port: 1356c5aff182SThomas Petazzoni * Clears interrupt Cause and Mask registers. 1357c5aff182SThomas Petazzoni * Clears all MAC tables. 1358c5aff182SThomas Petazzoni * Sets defaults to all registers. 1359c5aff182SThomas Petazzoni * Resets RX and TX descriptor rings. 1360c5aff182SThomas Petazzoni * Resets PHY. 1361c5aff182SThomas Petazzoni * This method can be called after mvneta_port_down() to return the port 1362c5aff182SThomas Petazzoni * settings to defaults. 1363c5aff182SThomas Petazzoni */ 1364c5aff182SThomas Petazzoni static void mvneta_defaults_set(struct mvneta_port *pp) 1365c5aff182SThomas Petazzoni { 1366c5aff182SThomas Petazzoni int cpu; 1367c5aff182SThomas Petazzoni int queue; 1368c5aff182SThomas Petazzoni u32 val; 13692dcf75e2SGregory CLEMENT int max_cpu = num_present_cpus(); 1370c5aff182SThomas Petazzoni 1371c5aff182SThomas Petazzoni /* Clear all Cause registers */ 1372db488c10SGregory CLEMENT on_each_cpu(mvneta_percpu_clear_intr_cause, pp, true); 1373c5aff182SThomas Petazzoni 1374c5aff182SThomas Petazzoni /* Mask all interrupts */ 1375db488c10SGregory CLEMENT on_each_cpu(mvneta_percpu_mask_interrupt, pp, true); 1376c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_INTR_ENABLE, 0); 1377c5aff182SThomas Petazzoni 1378c5aff182SThomas Petazzoni /* Enable MBUS Retry bit16 */ 1379c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_MBUS_RETRY, 0x20); 1380c5aff182SThomas Petazzoni 138150bf8cb6SGregory CLEMENT /* Set CPU queue access map. CPUs are assigned to the RX and 138250bf8cb6SGregory CLEMENT * TX queues modulo their number. If there is only one TX 138350bf8cb6SGregory CLEMENT * queue then it is assigned to the CPU associated to the 138450bf8cb6SGregory CLEMENT * default RX queue. 13856a20c175SThomas Petazzoni */ 13862dcf75e2SGregory CLEMENT for_each_present_cpu(cpu) { 13872dcf75e2SGregory CLEMENT int rxq_map = 0, txq_map = 0; 138850bf8cb6SGregory CLEMENT int rxq, txq; 13892636ac3cSMarcin Wojtas if (!pp->neta_armada3700) { 13902dcf75e2SGregory CLEMENT for (rxq = 0; rxq < rxq_number; rxq++) 13912dcf75e2SGregory CLEMENT if ((rxq % max_cpu) == cpu) 13922dcf75e2SGregory CLEMENT rxq_map |= MVNETA_CPU_RXQ_ACCESS(rxq); 13932dcf75e2SGregory CLEMENT 139450bf8cb6SGregory CLEMENT for (txq = 0; txq < txq_number; txq++) 139550bf8cb6SGregory CLEMENT if ((txq % max_cpu) == cpu) 139650bf8cb6SGregory CLEMENT txq_map |= MVNETA_CPU_TXQ_ACCESS(txq); 139750bf8cb6SGregory CLEMENT 139850bf8cb6SGregory CLEMENT /* With only one TX queue we configure a special case 139950bf8cb6SGregory CLEMENT * which will allow to get all the irq on a single 140050bf8cb6SGregory CLEMENT * CPU 140150bf8cb6SGregory CLEMENT */ 140250bf8cb6SGregory CLEMENT if (txq_number == 1) 140350bf8cb6SGregory CLEMENT txq_map = (cpu == pp->rxq_def) ? 140450bf8cb6SGregory CLEMENT MVNETA_CPU_TXQ_ACCESS(1) : 0; 14052dcf75e2SGregory CLEMENT 14062636ac3cSMarcin Wojtas } else { 14072636ac3cSMarcin Wojtas txq_map = MVNETA_CPU_TXQ_ACCESS_ALL_MASK; 14082636ac3cSMarcin Wojtas rxq_map = MVNETA_CPU_RXQ_ACCESS_ALL_MASK; 14092636ac3cSMarcin Wojtas } 14102636ac3cSMarcin Wojtas 14112dcf75e2SGregory CLEMENT mvreg_write(pp, MVNETA_CPU_MAP(cpu), rxq_map | txq_map); 14122dcf75e2SGregory CLEMENT } 1413c5aff182SThomas Petazzoni 1414c5aff182SThomas Petazzoni /* Reset RX and TX DMAs */ 1415c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_PORT_RX_RESET, MVNETA_PORT_RX_DMA_RESET); 1416c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_PORT_TX_RESET, MVNETA_PORT_TX_DMA_RESET); 1417c5aff182SThomas Petazzoni 1418c5aff182SThomas Petazzoni /* Disable Legacy WRR, Disable EJP, Release from reset */ 1419c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_TXQ_CMD_1, 0); 1420c5aff182SThomas Petazzoni for (queue = 0; queue < txq_number; queue++) { 1421c5aff182SThomas Petazzoni mvreg_write(pp, MVETH_TXQ_TOKEN_COUNT_REG(queue), 0); 1422c5aff182SThomas Petazzoni mvreg_write(pp, MVETH_TXQ_TOKEN_CFG_REG(queue), 0); 1423c5aff182SThomas Petazzoni } 1424c5aff182SThomas Petazzoni 1425c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_PORT_TX_RESET, 0); 1426c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_PORT_RX_RESET, 0); 1427c5aff182SThomas Petazzoni 1428c5aff182SThomas Petazzoni /* Set Port Acceleration Mode */ 1429dc35a10fSMarcin Wojtas if (pp->bm_priv) 1430dc35a10fSMarcin Wojtas /* HW buffer management + legacy parser */ 1431dc35a10fSMarcin Wojtas val = MVNETA_ACC_MODE_EXT2; 1432dc35a10fSMarcin Wojtas else 1433dc35a10fSMarcin Wojtas /* SW buffer management + legacy parser */ 1434dc35a10fSMarcin Wojtas val = MVNETA_ACC_MODE_EXT1; 1435c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_ACC_MODE, val); 1436c5aff182SThomas Petazzoni 1437dc35a10fSMarcin Wojtas if (pp->bm_priv) 1438dc35a10fSMarcin Wojtas mvreg_write(pp, MVNETA_BM_ADDRESS, pp->bm_priv->bppi_phys_addr); 1439dc35a10fSMarcin Wojtas 1440c5aff182SThomas Petazzoni /* Update val of portCfg register accordingly with all RxQueue types */ 144190b74c01SGregory CLEMENT val = MVNETA_PORT_CONFIG_DEFL_VALUE(pp->rxq_def); 1442c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_PORT_CONFIG, val); 1443c5aff182SThomas Petazzoni 1444c5aff182SThomas Petazzoni val = 0; 1445c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_PORT_CONFIG_EXTEND, val); 1446c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_RX_MIN_FRAME_SIZE, 64); 1447c5aff182SThomas Petazzoni 1448c5aff182SThomas Petazzoni /* Build PORT_SDMA_CONFIG_REG */ 1449c5aff182SThomas Petazzoni val = 0; 1450c5aff182SThomas Petazzoni 1451c5aff182SThomas Petazzoni /* Default burst size */ 1452c5aff182SThomas Petazzoni val |= MVNETA_TX_BRST_SZ_MASK(MVNETA_SDMA_BRST_SIZE_16); 1453c5aff182SThomas Petazzoni val |= MVNETA_RX_BRST_SZ_MASK(MVNETA_SDMA_BRST_SIZE_16); 14549ad8fef6SThomas Petazzoni val |= MVNETA_RX_NO_DATA_SWAP | MVNETA_TX_NO_DATA_SWAP; 1455c5aff182SThomas Petazzoni 14569ad8fef6SThomas Petazzoni #if defined(__BIG_ENDIAN) 14579ad8fef6SThomas Petazzoni val |= MVNETA_DESC_SWAP; 14589ad8fef6SThomas Petazzoni #endif 1459c5aff182SThomas Petazzoni 1460c5aff182SThomas Petazzoni /* Assign port SDMA configuration */ 1461c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_SDMA_CONFIG, val); 1462c5aff182SThomas Petazzoni 146371408602SThomas Petazzoni /* Disable PHY polling in hardware, since we're using the 146471408602SThomas Petazzoni * kernel phylib to do this. 146571408602SThomas Petazzoni */ 146671408602SThomas Petazzoni val = mvreg_read(pp, MVNETA_UNIT_CONTROL); 146771408602SThomas Petazzoni val &= ~MVNETA_PHY_POLLING_ENABLE; 146871408602SThomas Petazzoni mvreg_write(pp, MVNETA_UNIT_CONTROL, val); 146971408602SThomas Petazzoni 1470c5aff182SThomas Petazzoni mvneta_set_ucast_table(pp, -1); 1471c5aff182SThomas Petazzoni mvneta_set_special_mcast_table(pp, -1); 1472c5aff182SThomas Petazzoni mvneta_set_other_mcast_table(pp, -1); 1473c5aff182SThomas Petazzoni 1474c5aff182SThomas Petazzoni /* Set port interrupt enable register - default enable all */ 1475c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_INTR_ENABLE, 1476c5aff182SThomas Petazzoni (MVNETA_RXQ_INTR_ENABLE_ALL_MASK 1477c5aff182SThomas Petazzoni | MVNETA_TXQ_INTR_ENABLE_ALL_MASK)); 1478e483911fSAndrew Lunn 1479e483911fSAndrew Lunn mvneta_mib_counters_clear(pp); 1480c5aff182SThomas Petazzoni } 1481c5aff182SThomas Petazzoni 1482c5aff182SThomas Petazzoni /* Set max sizes for tx queues */ 1483c5aff182SThomas Petazzoni static void mvneta_txq_max_tx_size_set(struct mvneta_port *pp, int max_tx_size) 1484c5aff182SThomas Petazzoni 1485c5aff182SThomas Petazzoni { 1486c5aff182SThomas Petazzoni u32 val, size, mtu; 1487c5aff182SThomas Petazzoni int queue; 1488c5aff182SThomas Petazzoni 1489c5aff182SThomas Petazzoni mtu = max_tx_size * 8; 1490c5aff182SThomas Petazzoni if (mtu > MVNETA_TX_MTU_MAX) 1491c5aff182SThomas Petazzoni mtu = MVNETA_TX_MTU_MAX; 1492c5aff182SThomas Petazzoni 1493c5aff182SThomas Petazzoni /* Set MTU */ 1494c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_TX_MTU); 1495c5aff182SThomas Petazzoni val &= ~MVNETA_TX_MTU_MAX; 1496c5aff182SThomas Petazzoni val |= mtu; 1497c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_TX_MTU, val); 1498c5aff182SThomas Petazzoni 1499c5aff182SThomas Petazzoni /* TX token size and all TXQs token size must be larger that MTU */ 1500c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_TX_TOKEN_SIZE); 1501c5aff182SThomas Petazzoni 1502c5aff182SThomas Petazzoni size = val & MVNETA_TX_TOKEN_SIZE_MAX; 1503c5aff182SThomas Petazzoni if (size < mtu) { 1504c5aff182SThomas Petazzoni size = mtu; 1505c5aff182SThomas Petazzoni val &= ~MVNETA_TX_TOKEN_SIZE_MAX; 1506c5aff182SThomas Petazzoni val |= size; 1507c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_TX_TOKEN_SIZE, val); 1508c5aff182SThomas Petazzoni } 1509c5aff182SThomas Petazzoni for (queue = 0; queue < txq_number; queue++) { 1510c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_TXQ_TOKEN_SIZE_REG(queue)); 1511c5aff182SThomas Petazzoni 1512c5aff182SThomas Petazzoni size = val & MVNETA_TXQ_TOKEN_SIZE_MAX; 1513c5aff182SThomas Petazzoni if (size < mtu) { 1514c5aff182SThomas Petazzoni size = mtu; 1515c5aff182SThomas Petazzoni val &= ~MVNETA_TXQ_TOKEN_SIZE_MAX; 1516c5aff182SThomas Petazzoni val |= size; 1517c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_TXQ_TOKEN_SIZE_REG(queue), val); 1518c5aff182SThomas Petazzoni } 1519c5aff182SThomas Petazzoni } 1520c5aff182SThomas Petazzoni } 1521c5aff182SThomas Petazzoni 1522c5aff182SThomas Petazzoni /* Set unicast address */ 1523c5aff182SThomas Petazzoni static void mvneta_set_ucast_addr(struct mvneta_port *pp, u8 last_nibble, 1524c5aff182SThomas Petazzoni int queue) 1525c5aff182SThomas Petazzoni { 1526c5aff182SThomas Petazzoni unsigned int unicast_reg; 1527c5aff182SThomas Petazzoni unsigned int tbl_offset; 1528c5aff182SThomas Petazzoni unsigned int reg_offset; 1529c5aff182SThomas Petazzoni 1530c5aff182SThomas Petazzoni /* Locate the Unicast table entry */ 1531c5aff182SThomas Petazzoni last_nibble = (0xf & last_nibble); 1532c5aff182SThomas Petazzoni 1533c5aff182SThomas Petazzoni /* offset from unicast tbl base */ 1534c5aff182SThomas Petazzoni tbl_offset = (last_nibble / 4) * 4; 1535c5aff182SThomas Petazzoni 1536c5aff182SThomas Petazzoni /* offset within the above reg */ 1537c5aff182SThomas Petazzoni reg_offset = last_nibble % 4; 1538c5aff182SThomas Petazzoni 1539c5aff182SThomas Petazzoni unicast_reg = mvreg_read(pp, (MVNETA_DA_FILT_UCAST_BASE + tbl_offset)); 1540c5aff182SThomas Petazzoni 1541c5aff182SThomas Petazzoni if (queue == -1) { 1542c5aff182SThomas Petazzoni /* Clear accepts frame bit at specified unicast DA tbl entry */ 1543c5aff182SThomas Petazzoni unicast_reg &= ~(0xff << (8 * reg_offset)); 1544c5aff182SThomas Petazzoni } else { 1545c5aff182SThomas Petazzoni unicast_reg &= ~(0xff << (8 * reg_offset)); 1546c5aff182SThomas Petazzoni unicast_reg |= ((0x01 | (queue << 1)) << (8 * reg_offset)); 1547c5aff182SThomas Petazzoni } 1548c5aff182SThomas Petazzoni 1549c5aff182SThomas Petazzoni mvreg_write(pp, (MVNETA_DA_FILT_UCAST_BASE + tbl_offset), unicast_reg); 1550c5aff182SThomas Petazzoni } 1551c5aff182SThomas Petazzoni 1552c5aff182SThomas Petazzoni /* Set mac address */ 1553c5aff182SThomas Petazzoni static void mvneta_mac_addr_set(struct mvneta_port *pp, unsigned char *addr, 1554c5aff182SThomas Petazzoni int queue) 1555c5aff182SThomas Petazzoni { 1556c5aff182SThomas Petazzoni unsigned int mac_h; 1557c5aff182SThomas Petazzoni unsigned int mac_l; 1558c5aff182SThomas Petazzoni 1559c5aff182SThomas Petazzoni if (queue != -1) { 1560c5aff182SThomas Petazzoni mac_l = (addr[4] << 8) | (addr[5]); 1561c5aff182SThomas Petazzoni mac_h = (addr[0] << 24) | (addr[1] << 16) | 1562c5aff182SThomas Petazzoni (addr[2] << 8) | (addr[3] << 0); 1563c5aff182SThomas Petazzoni 1564c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_MAC_ADDR_LOW, mac_l); 1565c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_MAC_ADDR_HIGH, mac_h); 1566c5aff182SThomas Petazzoni } 1567c5aff182SThomas Petazzoni 1568c5aff182SThomas Petazzoni /* Accept frames of this address */ 1569c5aff182SThomas Petazzoni mvneta_set_ucast_addr(pp, addr[5], queue); 1570c5aff182SThomas Petazzoni } 1571c5aff182SThomas Petazzoni 15726a20c175SThomas Petazzoni /* Set the number of packets that will be received before RX interrupt 15736a20c175SThomas Petazzoni * will be generated by HW. 1574c5aff182SThomas Petazzoni */ 1575c5aff182SThomas Petazzoni static void mvneta_rx_pkts_coal_set(struct mvneta_port *pp, 1576c5aff182SThomas Petazzoni struct mvneta_rx_queue *rxq, u32 value) 1577c5aff182SThomas Petazzoni { 1578c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_RXQ_THRESHOLD_REG(rxq->id), 1579c5aff182SThomas Petazzoni value | MVNETA_RXQ_NON_OCCUPIED(0)); 1580c5aff182SThomas Petazzoni } 1581c5aff182SThomas Petazzoni 15826a20c175SThomas Petazzoni /* Set the time delay in usec before RX interrupt will be generated by 15836a20c175SThomas Petazzoni * HW. 1584c5aff182SThomas Petazzoni */ 1585c5aff182SThomas Petazzoni static void mvneta_rx_time_coal_set(struct mvneta_port *pp, 1586c5aff182SThomas Petazzoni struct mvneta_rx_queue *rxq, u32 value) 1587c5aff182SThomas Petazzoni { 1588189dd626SThomas Petazzoni u32 val; 1589189dd626SThomas Petazzoni unsigned long clk_rate; 1590189dd626SThomas Petazzoni 1591189dd626SThomas Petazzoni clk_rate = clk_get_rate(pp->clk); 1592189dd626SThomas Petazzoni val = (clk_rate / 1000000) * value; 1593c5aff182SThomas Petazzoni 1594c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_RXQ_TIME_COAL_REG(rxq->id), val); 1595c5aff182SThomas Petazzoni } 1596c5aff182SThomas Petazzoni 1597c5aff182SThomas Petazzoni /* Set threshold for TX_DONE pkts coalescing */ 1598c5aff182SThomas Petazzoni static void mvneta_tx_done_pkts_coal_set(struct mvneta_port *pp, 1599c5aff182SThomas Petazzoni struct mvneta_tx_queue *txq, u32 value) 1600c5aff182SThomas Petazzoni { 1601c5aff182SThomas Petazzoni u32 val; 1602c5aff182SThomas Petazzoni 1603c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_TXQ_SIZE_REG(txq->id)); 1604c5aff182SThomas Petazzoni 1605c5aff182SThomas Petazzoni val &= ~MVNETA_TXQ_SENT_THRESH_ALL_MASK; 1606c5aff182SThomas Petazzoni val |= MVNETA_TXQ_SENT_THRESH_MASK(value); 1607c5aff182SThomas Petazzoni 1608c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_TXQ_SIZE_REG(txq->id), val); 1609c5aff182SThomas Petazzoni } 1610c5aff182SThomas Petazzoni 1611c5aff182SThomas Petazzoni /* Handle rx descriptor fill by setting buf_cookie and buf_phys_addr */ 1612c5aff182SThomas Petazzoni static void mvneta_rx_desc_fill(struct mvneta_rx_desc *rx_desc, 1613f88bee1cSGregory CLEMENT u32 phys_addr, void *virt_addr, 1614f88bee1cSGregory CLEMENT struct mvneta_rx_queue *rxq) 1615c5aff182SThomas Petazzoni { 1616f88bee1cSGregory CLEMENT int i; 1617f88bee1cSGregory CLEMENT 1618c5aff182SThomas Petazzoni rx_desc->buf_phys_addr = phys_addr; 1619f88bee1cSGregory CLEMENT i = rx_desc - rxq->descs; 1620f88bee1cSGregory CLEMENT rxq->buf_virt_addr[i] = virt_addr; 1621c5aff182SThomas Petazzoni } 1622c5aff182SThomas Petazzoni 1623c5aff182SThomas Petazzoni /* Decrement sent descriptors counter */ 1624c5aff182SThomas Petazzoni static void mvneta_txq_sent_desc_dec(struct mvneta_port *pp, 1625c5aff182SThomas Petazzoni struct mvneta_tx_queue *txq, 1626c5aff182SThomas Petazzoni int sent_desc) 1627c5aff182SThomas Petazzoni { 1628c5aff182SThomas Petazzoni u32 val; 1629c5aff182SThomas Petazzoni 1630c5aff182SThomas Petazzoni /* Only 255 TX descriptors can be updated at once */ 1631c5aff182SThomas Petazzoni while (sent_desc > 0xff) { 1632c5aff182SThomas Petazzoni val = 0xff << MVNETA_TXQ_DEC_SENT_SHIFT; 1633c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val); 1634c5aff182SThomas Petazzoni sent_desc = sent_desc - 0xff; 1635c5aff182SThomas Petazzoni } 1636c5aff182SThomas Petazzoni 1637c5aff182SThomas Petazzoni val = sent_desc << MVNETA_TXQ_DEC_SENT_SHIFT; 1638c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val); 1639c5aff182SThomas Petazzoni } 1640c5aff182SThomas Petazzoni 1641c5aff182SThomas Petazzoni /* Get number of TX descriptors already sent by HW */ 1642c5aff182SThomas Petazzoni static int mvneta_txq_sent_desc_num_get(struct mvneta_port *pp, 1643c5aff182SThomas Petazzoni struct mvneta_tx_queue *txq) 1644c5aff182SThomas Petazzoni { 1645c5aff182SThomas Petazzoni u32 val; 1646c5aff182SThomas Petazzoni int sent_desc; 1647c5aff182SThomas Petazzoni 1648c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_TXQ_STATUS_REG(txq->id)); 1649c5aff182SThomas Petazzoni sent_desc = (val & MVNETA_TXQ_SENT_DESC_MASK) >> 1650c5aff182SThomas Petazzoni MVNETA_TXQ_SENT_DESC_SHIFT; 1651c5aff182SThomas Petazzoni 1652c5aff182SThomas Petazzoni return sent_desc; 1653c5aff182SThomas Petazzoni } 1654c5aff182SThomas Petazzoni 16556a20c175SThomas Petazzoni /* Get number of sent descriptors and decrement counter. 1656c5aff182SThomas Petazzoni * The number of sent descriptors is returned. 1657c5aff182SThomas Petazzoni */ 1658c5aff182SThomas Petazzoni static int mvneta_txq_sent_desc_proc(struct mvneta_port *pp, 1659c5aff182SThomas Petazzoni struct mvneta_tx_queue *txq) 1660c5aff182SThomas Petazzoni { 1661c5aff182SThomas Petazzoni int sent_desc; 1662c5aff182SThomas Petazzoni 1663c5aff182SThomas Petazzoni /* Get number of sent descriptors */ 1664c5aff182SThomas Petazzoni sent_desc = mvneta_txq_sent_desc_num_get(pp, txq); 1665c5aff182SThomas Petazzoni 1666c5aff182SThomas Petazzoni /* Decrement sent descriptors counter */ 1667c5aff182SThomas Petazzoni if (sent_desc) 1668c5aff182SThomas Petazzoni mvneta_txq_sent_desc_dec(pp, txq, sent_desc); 1669c5aff182SThomas Petazzoni 1670c5aff182SThomas Petazzoni return sent_desc; 1671c5aff182SThomas Petazzoni } 1672c5aff182SThomas Petazzoni 1673c5aff182SThomas Petazzoni /* Set TXQ descriptors fields relevant for CSUM calculation */ 1674c5aff182SThomas Petazzoni static u32 mvneta_txq_desc_csum(int l3_offs, int l3_proto, 1675c5aff182SThomas Petazzoni int ip_hdr_len, int l4_proto) 1676c5aff182SThomas Petazzoni { 1677c5aff182SThomas Petazzoni u32 command; 1678c5aff182SThomas Petazzoni 1679c5aff182SThomas Petazzoni /* Fields: L3_offset, IP_hdrlen, L3_type, G_IPv4_chk, 16806a20c175SThomas Petazzoni * G_L4_chk, L4_type; required only for checksum 16816a20c175SThomas Petazzoni * calculation 16826a20c175SThomas Petazzoni */ 1683c5aff182SThomas Petazzoni command = l3_offs << MVNETA_TX_L3_OFF_SHIFT; 1684c5aff182SThomas Petazzoni command |= ip_hdr_len << MVNETA_TX_IP_HLEN_SHIFT; 1685c5aff182SThomas Petazzoni 16860a198587SThomas Fitzsimmons if (l3_proto == htons(ETH_P_IP)) 1687c5aff182SThomas Petazzoni command |= MVNETA_TXD_IP_CSUM; 1688c5aff182SThomas Petazzoni else 1689c5aff182SThomas Petazzoni command |= MVNETA_TX_L3_IP6; 1690c5aff182SThomas Petazzoni 1691c5aff182SThomas Petazzoni if (l4_proto == IPPROTO_TCP) 1692c5aff182SThomas Petazzoni command |= MVNETA_TX_L4_CSUM_FULL; 1693c5aff182SThomas Petazzoni else if (l4_proto == IPPROTO_UDP) 1694c5aff182SThomas Petazzoni command |= MVNETA_TX_L4_UDP | MVNETA_TX_L4_CSUM_FULL; 1695c5aff182SThomas Petazzoni else 1696c5aff182SThomas Petazzoni command |= MVNETA_TX_L4_CSUM_NOT; 1697c5aff182SThomas Petazzoni 1698c5aff182SThomas Petazzoni return command; 1699c5aff182SThomas Petazzoni } 1700c5aff182SThomas Petazzoni 1701c5aff182SThomas Petazzoni 1702c5aff182SThomas Petazzoni /* Display more error info */ 1703c5aff182SThomas Petazzoni static void mvneta_rx_error(struct mvneta_port *pp, 1704c5aff182SThomas Petazzoni struct mvneta_rx_desc *rx_desc) 1705c5aff182SThomas Petazzoni { 1706c5aff182SThomas Petazzoni u32 status = rx_desc->status; 1707c5aff182SThomas Petazzoni 1708c5aff182SThomas Petazzoni switch (status & MVNETA_RXD_ERR_CODE_MASK) { 1709c5aff182SThomas Petazzoni case MVNETA_RXD_ERR_CRC: 1710c5aff182SThomas Petazzoni netdev_err(pp->dev, "bad rx status %08x (crc error), size=%d\n", 1711c5aff182SThomas Petazzoni status, rx_desc->data_size); 1712c5aff182SThomas Petazzoni break; 1713c5aff182SThomas Petazzoni case MVNETA_RXD_ERR_OVERRUN: 1714c5aff182SThomas Petazzoni netdev_err(pp->dev, "bad rx status %08x (overrun error), size=%d\n", 1715c5aff182SThomas Petazzoni status, rx_desc->data_size); 1716c5aff182SThomas Petazzoni break; 1717c5aff182SThomas Petazzoni case MVNETA_RXD_ERR_LEN: 1718c5aff182SThomas Petazzoni netdev_err(pp->dev, "bad rx status %08x (max frame length error), size=%d\n", 1719c5aff182SThomas Petazzoni status, rx_desc->data_size); 1720c5aff182SThomas Petazzoni break; 1721c5aff182SThomas Petazzoni case MVNETA_RXD_ERR_RESOURCE: 1722c5aff182SThomas Petazzoni netdev_err(pp->dev, "bad rx status %08x (resource error), size=%d\n", 1723c5aff182SThomas Petazzoni status, rx_desc->data_size); 1724c5aff182SThomas Petazzoni break; 1725c5aff182SThomas Petazzoni } 1726c5aff182SThomas Petazzoni } 1727c5aff182SThomas Petazzoni 17285428213cSwilly tarreau /* Handle RX checksum offload based on the descriptor's status */ 17295428213cSwilly tarreau static void mvneta_rx_csum(struct mvneta_port *pp, u32 status, 1730c5aff182SThomas Petazzoni struct sk_buff *skb) 1731c5aff182SThomas Petazzoni { 1732f945cec8SYelena Krivosheev if ((pp->dev->features & NETIF_F_RXCSUM) && 1733f945cec8SYelena Krivosheev (status & MVNETA_RXD_L3_IP4) && 17345428213cSwilly tarreau (status & MVNETA_RXD_L4_CSUM_OK)) { 1735c5aff182SThomas Petazzoni skb->csum = 0; 1736c5aff182SThomas Petazzoni skb->ip_summed = CHECKSUM_UNNECESSARY; 1737c5aff182SThomas Petazzoni return; 1738c5aff182SThomas Petazzoni } 1739c5aff182SThomas Petazzoni 1740c5aff182SThomas Petazzoni skb->ip_summed = CHECKSUM_NONE; 1741c5aff182SThomas Petazzoni } 1742c5aff182SThomas Petazzoni 17436c498974Swilly tarreau /* Return tx queue pointer (find last set bit) according to <cause> returned 17446c498974Swilly tarreau * form tx_done reg. <cause> must not be null. The return value is always a 17456c498974Swilly tarreau * valid queue for matching the first one found in <cause>. 17466c498974Swilly tarreau */ 1747c5aff182SThomas Petazzoni static struct mvneta_tx_queue *mvneta_tx_done_policy(struct mvneta_port *pp, 1748c5aff182SThomas Petazzoni u32 cause) 1749c5aff182SThomas Petazzoni { 1750c5aff182SThomas Petazzoni int queue = fls(cause) - 1; 1751c5aff182SThomas Petazzoni 17526c498974Swilly tarreau return &pp->txqs[queue]; 1753c5aff182SThomas Petazzoni } 1754c5aff182SThomas Petazzoni 1755c5aff182SThomas Petazzoni /* Free tx queue skbuffs */ 1756c5aff182SThomas Petazzoni static void mvneta_txq_bufs_free(struct mvneta_port *pp, 1757a29b6235SMarcin Wojtas struct mvneta_tx_queue *txq, int num, 1758a29b6235SMarcin Wojtas struct netdev_queue *nq) 1759c5aff182SThomas Petazzoni { 1760a29b6235SMarcin Wojtas unsigned int bytes_compl = 0, pkts_compl = 0; 1761c5aff182SThomas Petazzoni int i; 1762c5aff182SThomas Petazzoni 1763c5aff182SThomas Petazzoni for (i = 0; i < num; i++) { 1764c5aff182SThomas Petazzoni struct mvneta_tx_desc *tx_desc = txq->descs + 1765c5aff182SThomas Petazzoni txq->txq_get_index; 1766c5aff182SThomas Petazzoni struct sk_buff *skb = txq->tx_skb[txq->txq_get_index]; 1767c5aff182SThomas Petazzoni 1768a29b6235SMarcin Wojtas if (skb) { 1769a29b6235SMarcin Wojtas bytes_compl += skb->len; 1770a29b6235SMarcin Wojtas pkts_compl++; 1771a29b6235SMarcin Wojtas } 1772a29b6235SMarcin Wojtas 1773c5aff182SThomas Petazzoni mvneta_txq_inc_get(txq); 1774c5aff182SThomas Petazzoni 17752e3173a3SEzequiel Garcia if (!IS_TSO_HEADER(txq, tx_desc->buf_phys_addr)) 17762e3173a3SEzequiel Garcia dma_unmap_single(pp->dev->dev.parent, 17772e3173a3SEzequiel Garcia tx_desc->buf_phys_addr, 1778c5aff182SThomas Petazzoni tx_desc->data_size, DMA_TO_DEVICE); 1779ba7e46efSEzequiel Garcia if (!skb) 1780ba7e46efSEzequiel Garcia continue; 1781c5aff182SThomas Petazzoni dev_kfree_skb_any(skb); 1782c5aff182SThomas Petazzoni } 1783a29b6235SMarcin Wojtas 1784a29b6235SMarcin Wojtas netdev_tx_completed_queue(nq, pkts_compl, bytes_compl); 1785c5aff182SThomas Petazzoni } 1786c5aff182SThomas Petazzoni 1787c5aff182SThomas Petazzoni /* Handle end of transmission */ 1788cd713199SArnaud Ebalard static void mvneta_txq_done(struct mvneta_port *pp, 1789c5aff182SThomas Petazzoni struct mvneta_tx_queue *txq) 1790c5aff182SThomas Petazzoni { 1791c5aff182SThomas Petazzoni struct netdev_queue *nq = netdev_get_tx_queue(pp->dev, txq->id); 1792c5aff182SThomas Petazzoni int tx_done; 1793c5aff182SThomas Petazzoni 1794c5aff182SThomas Petazzoni tx_done = mvneta_txq_sent_desc_proc(pp, txq); 1795cd713199SArnaud Ebalard if (!tx_done) 1796cd713199SArnaud Ebalard return; 1797cd713199SArnaud Ebalard 1798a29b6235SMarcin Wojtas mvneta_txq_bufs_free(pp, txq, tx_done, nq); 1799c5aff182SThomas Petazzoni 1800c5aff182SThomas Petazzoni txq->count -= tx_done; 1801c5aff182SThomas Petazzoni 1802c5aff182SThomas Petazzoni if (netif_tx_queue_stopped(nq)) { 18038eef5f97SEzequiel Garcia if (txq->count <= txq->tx_wake_threshold) 1804c5aff182SThomas Petazzoni netif_tx_wake_queue(nq); 1805c5aff182SThomas Petazzoni } 1806c5aff182SThomas Petazzoni } 1807c5aff182SThomas Petazzoni 1808dc35a10fSMarcin Wojtas /* Refill processing for SW buffer management */ 18097e47fd84SGregory CLEMENT /* Allocate page per descriptor */ 1810c5aff182SThomas Petazzoni static int mvneta_rx_refill(struct mvneta_port *pp, 1811f88bee1cSGregory CLEMENT struct mvneta_rx_desc *rx_desc, 18127e47fd84SGregory CLEMENT struct mvneta_rx_queue *rxq, 18137e47fd84SGregory CLEMENT gfp_t gfp_mask) 1814c5aff182SThomas Petazzoni { 1815c5aff182SThomas Petazzoni dma_addr_t phys_addr; 18167e47fd84SGregory CLEMENT struct page *page; 1817c5aff182SThomas Petazzoni 18187e47fd84SGregory CLEMENT page = __dev_alloc_page(gfp_mask); 18197e47fd84SGregory CLEMENT if (!page) 1820c5aff182SThomas Petazzoni return -ENOMEM; 1821c5aff182SThomas Petazzoni 18227e47fd84SGregory CLEMENT /* map page for use */ 18237e47fd84SGregory CLEMENT phys_addr = dma_map_page(pp->dev->dev.parent, page, 0, PAGE_SIZE, 1824c5aff182SThomas Petazzoni DMA_FROM_DEVICE); 1825c5aff182SThomas Petazzoni if (unlikely(dma_mapping_error(pp->dev->dev.parent, phys_addr))) { 18267e47fd84SGregory CLEMENT __free_page(page); 1827c5aff182SThomas Petazzoni return -ENOMEM; 1828c5aff182SThomas Petazzoni } 1829c5aff182SThomas Petazzoni 18308d5047cfSMarcin Wojtas phys_addr += pp->rx_offset_correction; 18317e47fd84SGregory CLEMENT mvneta_rx_desc_fill(rx_desc, phys_addr, page, rxq); 1832c5aff182SThomas Petazzoni return 0; 1833c5aff182SThomas Petazzoni } 1834c5aff182SThomas Petazzoni 1835c5aff182SThomas Petazzoni /* Handle tx checksum */ 1836c5aff182SThomas Petazzoni static u32 mvneta_skb_tx_csum(struct mvneta_port *pp, struct sk_buff *skb) 1837c5aff182SThomas Petazzoni { 1838c5aff182SThomas Petazzoni if (skb->ip_summed == CHECKSUM_PARTIAL) { 1839c5aff182SThomas Petazzoni int ip_hdr_len = 0; 1840817dbfa5SVlad Yasevich __be16 l3_proto = vlan_get_protocol(skb); 1841c5aff182SThomas Petazzoni u8 l4_proto; 1842c5aff182SThomas Petazzoni 1843817dbfa5SVlad Yasevich if (l3_proto == htons(ETH_P_IP)) { 1844c5aff182SThomas Petazzoni struct iphdr *ip4h = ip_hdr(skb); 1845c5aff182SThomas Petazzoni 1846c5aff182SThomas Petazzoni /* Calculate IPv4 checksum and L4 checksum */ 1847c5aff182SThomas Petazzoni ip_hdr_len = ip4h->ihl; 1848c5aff182SThomas Petazzoni l4_proto = ip4h->protocol; 1849817dbfa5SVlad Yasevich } else if (l3_proto == htons(ETH_P_IPV6)) { 1850c5aff182SThomas Petazzoni struct ipv6hdr *ip6h = ipv6_hdr(skb); 1851c5aff182SThomas Petazzoni 1852c5aff182SThomas Petazzoni /* Read l4_protocol from one of IPv6 extra headers */ 1853c5aff182SThomas Petazzoni if (skb_network_header_len(skb) > 0) 1854c5aff182SThomas Petazzoni ip_hdr_len = (skb_network_header_len(skb) >> 2); 1855c5aff182SThomas Petazzoni l4_proto = ip6h->nexthdr; 1856c5aff182SThomas Petazzoni } else 1857c5aff182SThomas Petazzoni return MVNETA_TX_L4_CSUM_NOT; 1858c5aff182SThomas Petazzoni 1859c5aff182SThomas Petazzoni return mvneta_txq_desc_csum(skb_network_offset(skb), 1860817dbfa5SVlad Yasevich l3_proto, ip_hdr_len, l4_proto); 1861c5aff182SThomas Petazzoni } 1862c5aff182SThomas Petazzoni 1863c5aff182SThomas Petazzoni return MVNETA_TX_L4_CSUM_NOT; 1864c5aff182SThomas Petazzoni } 1865c5aff182SThomas Petazzoni 1866c5aff182SThomas Petazzoni /* Drop packets received by the RXQ and free buffers */ 1867c5aff182SThomas Petazzoni static void mvneta_rxq_drop_pkts(struct mvneta_port *pp, 1868c5aff182SThomas Petazzoni struct mvneta_rx_queue *rxq) 1869c5aff182SThomas Petazzoni { 1870c5aff182SThomas Petazzoni int rx_done, i; 1871c5aff182SThomas Petazzoni 1872c5aff182SThomas Petazzoni rx_done = mvneta_rxq_busy_desc_num_get(pp, rxq); 1873dc35a10fSMarcin Wojtas if (rx_done) 1874dc35a10fSMarcin Wojtas mvneta_rxq_desc_num_update(pp, rxq, rx_done, rx_done); 1875dc35a10fSMarcin Wojtas 1876dc35a10fSMarcin Wojtas if (pp->bm_priv) { 1877dc35a10fSMarcin Wojtas for (i = 0; i < rx_done; i++) { 1878dc35a10fSMarcin Wojtas struct mvneta_rx_desc *rx_desc = 1879dc35a10fSMarcin Wojtas mvneta_rxq_next_desc_get(rxq); 1880dc35a10fSMarcin Wojtas u8 pool_id = MVNETA_RX_GET_BM_POOL_ID(rx_desc); 1881dc35a10fSMarcin Wojtas struct mvneta_bm_pool *bm_pool; 1882dc35a10fSMarcin Wojtas 1883dc35a10fSMarcin Wojtas bm_pool = &pp->bm_priv->bm_pools[pool_id]; 1884dc35a10fSMarcin Wojtas /* Return dropped buffer to the pool */ 1885dc35a10fSMarcin Wojtas mvneta_bm_pool_put_bp(pp->bm_priv, bm_pool, 1886dc35a10fSMarcin Wojtas rx_desc->buf_phys_addr); 1887dc35a10fSMarcin Wojtas } 1888dc35a10fSMarcin Wojtas return; 1889dc35a10fSMarcin Wojtas } 1890dc35a10fSMarcin Wojtas 1891c5aff182SThomas Petazzoni for (i = 0; i < rxq->size; i++) { 1892c5aff182SThomas Petazzoni struct mvneta_rx_desc *rx_desc = rxq->descs + i; 1893f88bee1cSGregory CLEMENT void *data = rxq->buf_virt_addr[i]; 1894562e2f46SYelena Krivosheev if (!data || !(rx_desc->buf_phys_addr)) 1895562e2f46SYelena Krivosheev continue; 1896c5aff182SThomas Petazzoni 1897f4a51879SAntoine Tenart dma_unmap_page(pp->dev->dev.parent, rx_desc->buf_phys_addr, 1898f4a51879SAntoine Tenart PAGE_SIZE, DMA_FROM_DEVICE); 18997e47fd84SGregory CLEMENT __free_page(data); 1900dc35a10fSMarcin Wojtas } 1901c5aff182SThomas Petazzoni } 1902c5aff182SThomas Petazzoni 1903562e2f46SYelena Krivosheev static inline 1904562e2f46SYelena Krivosheev int mvneta_rx_refill_queue(struct mvneta_port *pp, struct mvneta_rx_queue *rxq) 1905562e2f46SYelena Krivosheev { 1906562e2f46SYelena Krivosheev struct mvneta_rx_desc *rx_desc; 1907562e2f46SYelena Krivosheev int curr_desc = rxq->first_to_refill; 1908562e2f46SYelena Krivosheev int i; 1909562e2f46SYelena Krivosheev 1910562e2f46SYelena Krivosheev for (i = 0; (i < rxq->refill_num) && (i < 64); i++) { 1911562e2f46SYelena Krivosheev rx_desc = rxq->descs + curr_desc; 1912562e2f46SYelena Krivosheev if (!(rx_desc->buf_phys_addr)) { 1913562e2f46SYelena Krivosheev if (mvneta_rx_refill(pp, rx_desc, rxq, GFP_ATOMIC)) { 1914562e2f46SYelena Krivosheev pr_err("Can't refill queue %d. Done %d from %d\n", 1915562e2f46SYelena Krivosheev rxq->id, i, rxq->refill_num); 1916562e2f46SYelena Krivosheev rxq->refill_err++; 1917562e2f46SYelena Krivosheev break; 1918562e2f46SYelena Krivosheev } 1919562e2f46SYelena Krivosheev } 1920562e2f46SYelena Krivosheev curr_desc = MVNETA_QUEUE_NEXT_DESC(rxq, curr_desc); 1921562e2f46SYelena Krivosheev } 1922562e2f46SYelena Krivosheev rxq->refill_num -= i; 1923562e2f46SYelena Krivosheev rxq->first_to_refill = curr_desc; 1924562e2f46SYelena Krivosheev 1925562e2f46SYelena Krivosheev return i; 1926562e2f46SYelena Krivosheev } 1927562e2f46SYelena Krivosheev 1928dc35a10fSMarcin Wojtas /* Main rx processing when using software buffer management */ 19297a86f05fSAndrew Lunn static int mvneta_rx_swbm(struct napi_struct *napi, 1930562e2f46SYelena Krivosheev struct mvneta_port *pp, int budget, 1931c5aff182SThomas Petazzoni struct mvneta_rx_queue *rxq) 1932c5aff182SThomas Petazzoni { 1933c5aff182SThomas Petazzoni struct net_device *dev = pp->dev; 1934562e2f46SYelena Krivosheev int rx_todo, rx_proc; 1935562e2f46SYelena Krivosheev int refill = 0; 1936dc4277ddSwilly tarreau u32 rcvd_pkts = 0; 1937dc4277ddSwilly tarreau u32 rcvd_bytes = 0; 1938c5aff182SThomas Petazzoni 1939c5aff182SThomas Petazzoni /* Get number of received packets */ 1940562e2f46SYelena Krivosheev rx_todo = mvneta_rxq_busy_desc_num_get(pp, rxq); 1941562e2f46SYelena Krivosheev rx_proc = 0; 1942c5aff182SThomas Petazzoni 1943c5aff182SThomas Petazzoni /* Fairness NAPI loop */ 1944562e2f46SYelena Krivosheev while ((rcvd_pkts < budget) && (rx_proc < rx_todo)) { 1945c5aff182SThomas Petazzoni struct mvneta_rx_desc *rx_desc = mvneta_rxq_next_desc_get(rxq); 19468ec2cd48Swilly tarreau unsigned char *data; 19477e47fd84SGregory CLEMENT struct page *page; 1948daf158d0SSimon Guinot dma_addr_t phys_addr; 1949562e2f46SYelena Krivosheev u32 rx_status, index; 1950562e2f46SYelena Krivosheev int rx_bytes, skb_size, copy_size; 1951562e2f46SYelena Krivosheev int frag_num, frag_size, frag_offset; 1952c5aff182SThomas Petazzoni 1953f88bee1cSGregory CLEMENT index = rx_desc - rxq->descs; 19547e47fd84SGregory CLEMENT page = (struct page *)rxq->buf_virt_addr[index]; 19557e47fd84SGregory CLEMENT data = page_address(page); 19567e47fd84SGregory CLEMENT /* Prefetch header */ 19577e47fd84SGregory CLEMENT prefetch(data); 1958c5aff182SThomas Petazzoni 1959562e2f46SYelena Krivosheev phys_addr = rx_desc->buf_phys_addr; 1960562e2f46SYelena Krivosheev rx_status = rx_desc->status; 1961562e2f46SYelena Krivosheev rx_proc++; 1962562e2f46SYelena Krivosheev rxq->refill_num++; 1963562e2f46SYelena Krivosheev 1964562e2f46SYelena Krivosheev if (rx_status & MVNETA_RXD_FIRST_DESC) { 1965562e2f46SYelena Krivosheev /* Check errors only for FIRST descriptor */ 1966562e2f46SYelena Krivosheev if (rx_status & MVNETA_RXD_ERR_SUMMARY) { 19672eecb2e0SYelena Krivosheev mvneta_rx_error(pp, rx_desc); 1968c5aff182SThomas Petazzoni dev->stats.rx_errors++; 19698ec2cd48Swilly tarreau /* leave the descriptor untouched */ 1970c5aff182SThomas Petazzoni continue; 1971c5aff182SThomas Petazzoni } 1972562e2f46SYelena Krivosheev rx_bytes = rx_desc->data_size - 1973562e2f46SYelena Krivosheev (ETH_FCS_LEN + MVNETA_MH_SIZE); 1974c5aff182SThomas Petazzoni 1975562e2f46SYelena Krivosheev /* Allocate small skb for each new packet */ 1976562e2f46SYelena Krivosheev skb_size = max(rx_copybreak, rx_header_size); 1977562e2f46SYelena Krivosheev rxq->skb = netdev_alloc_skb_ip_align(dev, skb_size); 1978562e2f46SYelena Krivosheev if (unlikely(!rxq->skb)) { 197917a96da6SGregory CLEMENT netdev_err(dev, 198017a96da6SGregory CLEMENT "Can't allocate skb on queue %d\n", 198117a96da6SGregory CLEMENT rxq->id); 1982562e2f46SYelena Krivosheev dev->stats.rx_dropped++; 198317a96da6SGregory CLEMENT rxq->skb_alloc_err++; 1984f19fadfcSwilly tarreau continue; 1985f19fadfcSwilly tarreau } 1986562e2f46SYelena Krivosheev copy_size = min(skb_size, rx_bytes); 1987f19fadfcSwilly tarreau 1988562e2f46SYelena Krivosheev /* Copy data from buffer to SKB, skip Marvell header */ 1989562e2f46SYelena Krivosheev memcpy(rxq->skb->data, data + MVNETA_MH_SIZE, 1990562e2f46SYelena Krivosheev copy_size); 1991562e2f46SYelena Krivosheev skb_put(rxq->skb, copy_size); 1992562e2f46SYelena Krivosheev rxq->left_size = rx_bytes - copy_size; 1993a84e3289SSimon Guinot 1994562e2f46SYelena Krivosheev mvneta_rx_csum(pp, rx_status, rxq->skb); 1995562e2f46SYelena Krivosheev if (rxq->left_size == 0) { 1996562e2f46SYelena Krivosheev int size = copy_size + MVNETA_MH_SIZE; 1997dc35a10fSMarcin Wojtas 1998562e2f46SYelena Krivosheev dma_sync_single_range_for_cpu(dev->dev.parent, 1999562e2f46SYelena Krivosheev phys_addr, 0, 2000562e2f46SYelena Krivosheev size, 2001dc35a10fSMarcin Wojtas DMA_FROM_DEVICE); 2002c5aff182SThomas Petazzoni 2003562e2f46SYelena Krivosheev /* leave the descriptor and buffer untouched */ 2004562e2f46SYelena Krivosheev } else { 2005562e2f46SYelena Krivosheev /* refill descriptor with new buffer later */ 2006562e2f46SYelena Krivosheev rx_desc->buf_phys_addr = 0; 200726c17a17SMarcin Wojtas 2008562e2f46SYelena Krivosheev frag_num = 0; 2009562e2f46SYelena Krivosheev frag_offset = copy_size + MVNETA_MH_SIZE; 2010562e2f46SYelena Krivosheev frag_size = min(rxq->left_size, 2011562e2f46SYelena Krivosheev (int)(PAGE_SIZE - frag_offset)); 2012562e2f46SYelena Krivosheev skb_add_rx_frag(rxq->skb, frag_num, page, 2013562e2f46SYelena Krivosheev frag_offset, frag_size, 2014562e2f46SYelena Krivosheev PAGE_SIZE); 2015cf5cca6eSAntoine Tenart dma_unmap_page(dev->dev.parent, phys_addr, 2016562e2f46SYelena Krivosheev PAGE_SIZE, DMA_FROM_DEVICE); 2017562e2f46SYelena Krivosheev rxq->left_size -= frag_size; 2018562e2f46SYelena Krivosheev } 2019562e2f46SYelena Krivosheev } else { 2020562e2f46SYelena Krivosheev /* Middle or Last descriptor */ 2021562e2f46SYelena Krivosheev if (unlikely(!rxq->skb)) { 2022562e2f46SYelena Krivosheev pr_debug("no skb for rx_status 0x%x\n", 2023562e2f46SYelena Krivosheev rx_status); 2024562e2f46SYelena Krivosheev continue; 2025562e2f46SYelena Krivosheev } 2026562e2f46SYelena Krivosheev if (!rxq->left_size) { 2027562e2f46SYelena Krivosheev /* last descriptor has only FCS */ 2028562e2f46SYelena Krivosheev /* and can be discarded */ 2029562e2f46SYelena Krivosheev dma_sync_single_range_for_cpu(dev->dev.parent, 2030562e2f46SYelena Krivosheev phys_addr, 0, 2031562e2f46SYelena Krivosheev ETH_FCS_LEN, 2032562e2f46SYelena Krivosheev DMA_FROM_DEVICE); 2033562e2f46SYelena Krivosheev /* leave the descriptor and buffer untouched */ 2034562e2f46SYelena Krivosheev } else { 2035562e2f46SYelena Krivosheev /* refill descriptor with new buffer later */ 2036562e2f46SYelena Krivosheev rx_desc->buf_phys_addr = 0; 2037562e2f46SYelena Krivosheev 2038562e2f46SYelena Krivosheev frag_num = skb_shinfo(rxq->skb)->nr_frags; 2039562e2f46SYelena Krivosheev frag_offset = 0; 2040562e2f46SYelena Krivosheev frag_size = min(rxq->left_size, 2041562e2f46SYelena Krivosheev (int)(PAGE_SIZE - frag_offset)); 2042562e2f46SYelena Krivosheev skb_add_rx_frag(rxq->skb, frag_num, page, 2043562e2f46SYelena Krivosheev frag_offset, frag_size, 2044562e2f46SYelena Krivosheev PAGE_SIZE); 2045562e2f46SYelena Krivosheev 2046f4a51879SAntoine Tenart dma_unmap_page(dev->dev.parent, phys_addr, 2047f4a51879SAntoine Tenart PAGE_SIZE, DMA_FROM_DEVICE); 2048562e2f46SYelena Krivosheev 2049562e2f46SYelena Krivosheev rxq->left_size -= frag_size; 2050562e2f46SYelena Krivosheev } 2051562e2f46SYelena Krivosheev } /* Middle or Last descriptor */ 2052562e2f46SYelena Krivosheev 2053562e2f46SYelena Krivosheev if (!(rx_status & MVNETA_RXD_LAST_DESC)) 2054562e2f46SYelena Krivosheev /* no last descriptor this time */ 2055562e2f46SYelena Krivosheev continue; 2056562e2f46SYelena Krivosheev 2057562e2f46SYelena Krivosheev if (rxq->left_size) { 2058562e2f46SYelena Krivosheev pr_err("get last desc, but left_size (%d) != 0\n", 2059562e2f46SYelena Krivosheev rxq->left_size); 2060562e2f46SYelena Krivosheev dev_kfree_skb_any(rxq->skb); 2061562e2f46SYelena Krivosheev rxq->left_size = 0; 2062562e2f46SYelena Krivosheev rxq->skb = NULL; 2063562e2f46SYelena Krivosheev continue; 2064562e2f46SYelena Krivosheev } 2065dc4277ddSwilly tarreau rcvd_pkts++; 2066562e2f46SYelena Krivosheev rcvd_bytes += rxq->skb->len; 2067c5aff182SThomas Petazzoni 2068c5aff182SThomas Petazzoni /* Linux processing */ 2069562e2f46SYelena Krivosheev rxq->skb->protocol = eth_type_trans(rxq->skb, dev); 2070c5aff182SThomas Petazzoni 2071562e2f46SYelena Krivosheev napi_gro_receive(napi, rxq->skb); 2072c5aff182SThomas Petazzoni 2073562e2f46SYelena Krivosheev /* clean uncomplete skb pointer in queue */ 2074562e2f46SYelena Krivosheev rxq->skb = NULL; 2075562e2f46SYelena Krivosheev rxq->left_size = 0; 2076c5aff182SThomas Petazzoni } 2077c5aff182SThomas Petazzoni 2078dc4277ddSwilly tarreau if (rcvd_pkts) { 207974c41b04Swilly tarreau struct mvneta_pcpu_stats *stats = this_cpu_ptr(pp->stats); 208074c41b04Swilly tarreau 208174c41b04Swilly tarreau u64_stats_update_begin(&stats->syncp); 208274c41b04Swilly tarreau stats->rx_packets += rcvd_pkts; 208374c41b04Swilly tarreau stats->rx_bytes += rcvd_bytes; 208474c41b04Swilly tarreau u64_stats_update_end(&stats->syncp); 2085dc4277ddSwilly tarreau } 2086dc4277ddSwilly tarreau 2087562e2f46SYelena Krivosheev /* return some buffers to hardware queue, one at a time is too slow */ 2088562e2f46SYelena Krivosheev refill = mvneta_rx_refill_queue(pp, rxq); 2089c5aff182SThomas Petazzoni 2090562e2f46SYelena Krivosheev /* Update rxq management counters */ 2091562e2f46SYelena Krivosheev mvneta_rxq_desc_num_update(pp, rxq, rx_proc, refill); 2092562e2f46SYelena Krivosheev 2093562e2f46SYelena Krivosheev return rcvd_pkts; 2094c5aff182SThomas Petazzoni } 2095c5aff182SThomas Petazzoni 2096dc35a10fSMarcin Wojtas /* Main rx processing when using hardware buffer management */ 20977a86f05fSAndrew Lunn static int mvneta_rx_hwbm(struct napi_struct *napi, 20987a86f05fSAndrew Lunn struct mvneta_port *pp, int rx_todo, 2099dc35a10fSMarcin Wojtas struct mvneta_rx_queue *rxq) 2100dc35a10fSMarcin Wojtas { 2101dc35a10fSMarcin Wojtas struct net_device *dev = pp->dev; 2102dc35a10fSMarcin Wojtas int rx_done; 2103dc35a10fSMarcin Wojtas u32 rcvd_pkts = 0; 2104dc35a10fSMarcin Wojtas u32 rcvd_bytes = 0; 2105dc35a10fSMarcin Wojtas 2106dc35a10fSMarcin Wojtas /* Get number of received packets */ 2107dc35a10fSMarcin Wojtas rx_done = mvneta_rxq_busy_desc_num_get(pp, rxq); 2108dc35a10fSMarcin Wojtas 2109dc35a10fSMarcin Wojtas if (rx_todo > rx_done) 2110dc35a10fSMarcin Wojtas rx_todo = rx_done; 2111dc35a10fSMarcin Wojtas 2112dc35a10fSMarcin Wojtas rx_done = 0; 2113dc35a10fSMarcin Wojtas 2114dc35a10fSMarcin Wojtas /* Fairness NAPI loop */ 2115dc35a10fSMarcin Wojtas while (rx_done < rx_todo) { 2116dc35a10fSMarcin Wojtas struct mvneta_rx_desc *rx_desc = mvneta_rxq_next_desc_get(rxq); 2117dc35a10fSMarcin Wojtas struct mvneta_bm_pool *bm_pool = NULL; 2118dc35a10fSMarcin Wojtas struct sk_buff *skb; 2119dc35a10fSMarcin Wojtas unsigned char *data; 2120dc35a10fSMarcin Wojtas dma_addr_t phys_addr; 2121dc35a10fSMarcin Wojtas u32 rx_status, frag_size; 2122dc35a10fSMarcin Wojtas int rx_bytes, err; 2123dc35a10fSMarcin Wojtas u8 pool_id; 2124dc35a10fSMarcin Wojtas 2125dc35a10fSMarcin Wojtas rx_done++; 2126dc35a10fSMarcin Wojtas rx_status = rx_desc->status; 2127dc35a10fSMarcin Wojtas rx_bytes = rx_desc->data_size - (ETH_FCS_LEN + MVNETA_MH_SIZE); 2128f88bee1cSGregory CLEMENT data = (u8 *)(uintptr_t)rx_desc->buf_cookie; 2129dc35a10fSMarcin Wojtas phys_addr = rx_desc->buf_phys_addr; 2130dc35a10fSMarcin Wojtas pool_id = MVNETA_RX_GET_BM_POOL_ID(rx_desc); 2131dc35a10fSMarcin Wojtas bm_pool = &pp->bm_priv->bm_pools[pool_id]; 2132dc35a10fSMarcin Wojtas 2133dc35a10fSMarcin Wojtas if (!mvneta_rxq_desc_is_first_last(rx_status) || 2134dc35a10fSMarcin Wojtas (rx_status & MVNETA_RXD_ERR_SUMMARY)) { 2135dc35a10fSMarcin Wojtas err_drop_frame_ret_pool: 2136dc35a10fSMarcin Wojtas /* Return the buffer to the pool */ 2137dc35a10fSMarcin Wojtas mvneta_bm_pool_put_bp(pp->bm_priv, bm_pool, 2138dc35a10fSMarcin Wojtas rx_desc->buf_phys_addr); 2139dc35a10fSMarcin Wojtas err_drop_frame: 2140dc35a10fSMarcin Wojtas dev->stats.rx_errors++; 2141dc35a10fSMarcin Wojtas mvneta_rx_error(pp, rx_desc); 2142dc35a10fSMarcin Wojtas /* leave the descriptor untouched */ 2143dc35a10fSMarcin Wojtas continue; 2144dc35a10fSMarcin Wojtas } 2145dc35a10fSMarcin Wojtas 2146dc35a10fSMarcin Wojtas if (rx_bytes <= rx_copybreak) { 2147dc35a10fSMarcin Wojtas /* better copy a small frame and not unmap the DMA region */ 2148dc35a10fSMarcin Wojtas skb = netdev_alloc_skb_ip_align(dev, rx_bytes); 2149dc35a10fSMarcin Wojtas if (unlikely(!skb)) 2150dc35a10fSMarcin Wojtas goto err_drop_frame_ret_pool; 2151dc35a10fSMarcin Wojtas 2152a8fef9baSRussell King dma_sync_single_range_for_cpu(&pp->bm_priv->pdev->dev, 2153dc35a10fSMarcin Wojtas rx_desc->buf_phys_addr, 2154dc35a10fSMarcin Wojtas MVNETA_MH_SIZE + NET_SKB_PAD, 2155dc35a10fSMarcin Wojtas rx_bytes, 2156dc35a10fSMarcin Wojtas DMA_FROM_DEVICE); 215759ae1d12SJohannes Berg skb_put_data(skb, data + MVNETA_MH_SIZE + NET_SKB_PAD, 2158dc35a10fSMarcin Wojtas rx_bytes); 2159dc35a10fSMarcin Wojtas 2160dc35a10fSMarcin Wojtas skb->protocol = eth_type_trans(skb, dev); 2161dc35a10fSMarcin Wojtas mvneta_rx_csum(pp, rx_status, skb); 21627a86f05fSAndrew Lunn napi_gro_receive(napi, skb); 2163dc35a10fSMarcin Wojtas 2164dc35a10fSMarcin Wojtas rcvd_pkts++; 2165dc35a10fSMarcin Wojtas rcvd_bytes += rx_bytes; 2166dc35a10fSMarcin Wojtas 2167dc35a10fSMarcin Wojtas /* Return the buffer to the pool */ 2168dc35a10fSMarcin Wojtas mvneta_bm_pool_put_bp(pp->bm_priv, bm_pool, 2169dc35a10fSMarcin Wojtas rx_desc->buf_phys_addr); 2170dc35a10fSMarcin Wojtas 2171dc35a10fSMarcin Wojtas /* leave the descriptor and buffer untouched */ 2172dc35a10fSMarcin Wojtas continue; 2173dc35a10fSMarcin Wojtas } 2174dc35a10fSMarcin Wojtas 2175dc35a10fSMarcin Wojtas /* Refill processing */ 2176baa11ebcSGregory CLEMENT err = hwbm_pool_refill(&bm_pool->hwbm_pool, GFP_ATOMIC); 2177dc35a10fSMarcin Wojtas if (err) { 2178dc35a10fSMarcin Wojtas netdev_err(dev, "Linux processing - Can't refill\n"); 217917a96da6SGregory CLEMENT rxq->refill_err++; 2180dc35a10fSMarcin Wojtas goto err_drop_frame_ret_pool; 2181dc35a10fSMarcin Wojtas } 2182dc35a10fSMarcin Wojtas 2183baa11ebcSGregory CLEMENT frag_size = bm_pool->hwbm_pool.frag_size; 2184dc35a10fSMarcin Wojtas 2185dc35a10fSMarcin Wojtas skb = build_skb(data, frag_size > PAGE_SIZE ? 0 : frag_size); 2186dc35a10fSMarcin Wojtas 2187dc35a10fSMarcin Wojtas /* After refill old buffer has to be unmapped regardless 2188dc35a10fSMarcin Wojtas * the skb is successfully built or not. 2189dc35a10fSMarcin Wojtas */ 2190dc35a10fSMarcin Wojtas dma_unmap_single(&pp->bm_priv->pdev->dev, phys_addr, 2191dc35a10fSMarcin Wojtas bm_pool->buf_size, DMA_FROM_DEVICE); 2192dc35a10fSMarcin Wojtas if (!skb) 2193dc35a10fSMarcin Wojtas goto err_drop_frame; 2194dc35a10fSMarcin Wojtas 2195dc35a10fSMarcin Wojtas rcvd_pkts++; 2196dc35a10fSMarcin Wojtas rcvd_bytes += rx_bytes; 2197dc35a10fSMarcin Wojtas 2198dc35a10fSMarcin Wojtas /* Linux processing */ 2199dc35a10fSMarcin Wojtas skb_reserve(skb, MVNETA_MH_SIZE + NET_SKB_PAD); 2200dc35a10fSMarcin Wojtas skb_put(skb, rx_bytes); 2201dc35a10fSMarcin Wojtas 2202dc35a10fSMarcin Wojtas skb->protocol = eth_type_trans(skb, dev); 2203dc35a10fSMarcin Wojtas 2204dc35a10fSMarcin Wojtas mvneta_rx_csum(pp, rx_status, skb); 2205dc35a10fSMarcin Wojtas 22067a86f05fSAndrew Lunn napi_gro_receive(napi, skb); 2207dc35a10fSMarcin Wojtas } 2208dc35a10fSMarcin Wojtas 2209dc35a10fSMarcin Wojtas if (rcvd_pkts) { 2210dc35a10fSMarcin Wojtas struct mvneta_pcpu_stats *stats = this_cpu_ptr(pp->stats); 2211dc35a10fSMarcin Wojtas 2212dc35a10fSMarcin Wojtas u64_stats_update_begin(&stats->syncp); 2213dc35a10fSMarcin Wojtas stats->rx_packets += rcvd_pkts; 2214dc35a10fSMarcin Wojtas stats->rx_bytes += rcvd_bytes; 2215dc35a10fSMarcin Wojtas u64_stats_update_end(&stats->syncp); 2216dc35a10fSMarcin Wojtas } 2217dc35a10fSMarcin Wojtas 2218dc35a10fSMarcin Wojtas /* Update rxq management counters */ 2219dc35a10fSMarcin Wojtas mvneta_rxq_desc_num_update(pp, rxq, rx_done, rx_done); 2220dc35a10fSMarcin Wojtas 2221dc35a10fSMarcin Wojtas return rx_done; 2222dc35a10fSMarcin Wojtas } 2223dc35a10fSMarcin Wojtas 22242adb719dSEzequiel Garcia static inline void 22252adb719dSEzequiel Garcia mvneta_tso_put_hdr(struct sk_buff *skb, 22262adb719dSEzequiel Garcia struct mvneta_port *pp, struct mvneta_tx_queue *txq) 22272adb719dSEzequiel Garcia { 22282adb719dSEzequiel Garcia struct mvneta_tx_desc *tx_desc; 22292adb719dSEzequiel Garcia int hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb); 22302adb719dSEzequiel Garcia 22312adb719dSEzequiel Garcia txq->tx_skb[txq->txq_put_index] = NULL; 22322adb719dSEzequiel Garcia tx_desc = mvneta_txq_next_desc_get(txq); 22332adb719dSEzequiel Garcia tx_desc->data_size = hdr_len; 22342adb719dSEzequiel Garcia tx_desc->command = mvneta_skb_tx_csum(pp, skb); 22352adb719dSEzequiel Garcia tx_desc->command |= MVNETA_TXD_F_DESC; 22362adb719dSEzequiel Garcia tx_desc->buf_phys_addr = txq->tso_hdrs_phys + 22372adb719dSEzequiel Garcia txq->txq_put_index * TSO_HEADER_SIZE; 22382adb719dSEzequiel Garcia mvneta_txq_inc_put(txq); 22392adb719dSEzequiel Garcia } 22402adb719dSEzequiel Garcia 22412adb719dSEzequiel Garcia static inline int 22422adb719dSEzequiel Garcia mvneta_tso_put_data(struct net_device *dev, struct mvneta_tx_queue *txq, 22432adb719dSEzequiel Garcia struct sk_buff *skb, char *data, int size, 22442adb719dSEzequiel Garcia bool last_tcp, bool is_last) 22452adb719dSEzequiel Garcia { 22462adb719dSEzequiel Garcia struct mvneta_tx_desc *tx_desc; 22472adb719dSEzequiel Garcia 22482adb719dSEzequiel Garcia tx_desc = mvneta_txq_next_desc_get(txq); 22492adb719dSEzequiel Garcia tx_desc->data_size = size; 22502adb719dSEzequiel Garcia tx_desc->buf_phys_addr = dma_map_single(dev->dev.parent, data, 22512adb719dSEzequiel Garcia size, DMA_TO_DEVICE); 22522adb719dSEzequiel Garcia if (unlikely(dma_mapping_error(dev->dev.parent, 22532adb719dSEzequiel Garcia tx_desc->buf_phys_addr))) { 22542adb719dSEzequiel Garcia mvneta_txq_desc_put(txq); 22552adb719dSEzequiel Garcia return -ENOMEM; 22562adb719dSEzequiel Garcia } 22572adb719dSEzequiel Garcia 22582adb719dSEzequiel Garcia tx_desc->command = 0; 22592adb719dSEzequiel Garcia txq->tx_skb[txq->txq_put_index] = NULL; 22602adb719dSEzequiel Garcia 22612adb719dSEzequiel Garcia if (last_tcp) { 22622adb719dSEzequiel Garcia /* last descriptor in the TCP packet */ 22632adb719dSEzequiel Garcia tx_desc->command = MVNETA_TXD_L_DESC; 22642adb719dSEzequiel Garcia 22652adb719dSEzequiel Garcia /* last descriptor in SKB */ 22662adb719dSEzequiel Garcia if (is_last) 22672adb719dSEzequiel Garcia txq->tx_skb[txq->txq_put_index] = skb; 22682adb719dSEzequiel Garcia } 22692adb719dSEzequiel Garcia mvneta_txq_inc_put(txq); 22702adb719dSEzequiel Garcia return 0; 22712adb719dSEzequiel Garcia } 22722adb719dSEzequiel Garcia 22732adb719dSEzequiel Garcia static int mvneta_tx_tso(struct sk_buff *skb, struct net_device *dev, 22742adb719dSEzequiel Garcia struct mvneta_tx_queue *txq) 22752adb719dSEzequiel Garcia { 22762adb719dSEzequiel Garcia int total_len, data_left; 22772adb719dSEzequiel Garcia int desc_count = 0; 22782adb719dSEzequiel Garcia struct mvneta_port *pp = netdev_priv(dev); 22792adb719dSEzequiel Garcia struct tso_t tso; 22802adb719dSEzequiel Garcia int hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb); 22812adb719dSEzequiel Garcia int i; 22822adb719dSEzequiel Garcia 22832adb719dSEzequiel Garcia /* Count needed descriptors */ 22842adb719dSEzequiel Garcia if ((txq->count + tso_count_descs(skb)) >= txq->size) 22852adb719dSEzequiel Garcia return 0; 22862adb719dSEzequiel Garcia 22872adb719dSEzequiel Garcia if (skb_headlen(skb) < (skb_transport_offset(skb) + tcp_hdrlen(skb))) { 22882adb719dSEzequiel Garcia pr_info("*** Is this even possible???!?!?\n"); 22892adb719dSEzequiel Garcia return 0; 22902adb719dSEzequiel Garcia } 22912adb719dSEzequiel Garcia 22922adb719dSEzequiel Garcia /* Initialize the TSO handler, and prepare the first payload */ 22932adb719dSEzequiel Garcia tso_start(skb, &tso); 22942adb719dSEzequiel Garcia 22952adb719dSEzequiel Garcia total_len = skb->len - hdr_len; 22962adb719dSEzequiel Garcia while (total_len > 0) { 22972adb719dSEzequiel Garcia char *hdr; 22982adb719dSEzequiel Garcia 22992adb719dSEzequiel Garcia data_left = min_t(int, skb_shinfo(skb)->gso_size, total_len); 23002adb719dSEzequiel Garcia total_len -= data_left; 23012adb719dSEzequiel Garcia desc_count++; 23022adb719dSEzequiel Garcia 23032adb719dSEzequiel Garcia /* prepare packet headers: MAC + IP + TCP */ 23042adb719dSEzequiel Garcia hdr = txq->tso_hdrs + txq->txq_put_index * TSO_HEADER_SIZE; 23052adb719dSEzequiel Garcia tso_build_hdr(skb, hdr, &tso, data_left, total_len == 0); 23062adb719dSEzequiel Garcia 23072adb719dSEzequiel Garcia mvneta_tso_put_hdr(skb, pp, txq); 23082adb719dSEzequiel Garcia 23092adb719dSEzequiel Garcia while (data_left > 0) { 23102adb719dSEzequiel Garcia int size; 23112adb719dSEzequiel Garcia desc_count++; 23122adb719dSEzequiel Garcia 23132adb719dSEzequiel Garcia size = min_t(int, tso.size, data_left); 23142adb719dSEzequiel Garcia 23152adb719dSEzequiel Garcia if (mvneta_tso_put_data(dev, txq, skb, 23162adb719dSEzequiel Garcia tso.data, size, 23172adb719dSEzequiel Garcia size == data_left, 23182adb719dSEzequiel Garcia total_len == 0)) 23192adb719dSEzequiel Garcia goto err_release; 23202adb719dSEzequiel Garcia data_left -= size; 23212adb719dSEzequiel Garcia 23222adb719dSEzequiel Garcia tso_build_data(skb, &tso, size); 23232adb719dSEzequiel Garcia } 23242adb719dSEzequiel Garcia } 23252adb719dSEzequiel Garcia 23262adb719dSEzequiel Garcia return desc_count; 23272adb719dSEzequiel Garcia 23282adb719dSEzequiel Garcia err_release: 23292adb719dSEzequiel Garcia /* Release all used data descriptors; header descriptors must not 23302adb719dSEzequiel Garcia * be DMA-unmapped. 23312adb719dSEzequiel Garcia */ 23322adb719dSEzequiel Garcia for (i = desc_count - 1; i >= 0; i--) { 23332adb719dSEzequiel Garcia struct mvneta_tx_desc *tx_desc = txq->descs + i; 23342e3173a3SEzequiel Garcia if (!IS_TSO_HEADER(txq, tx_desc->buf_phys_addr)) 23352adb719dSEzequiel Garcia dma_unmap_single(pp->dev->dev.parent, 23362adb719dSEzequiel Garcia tx_desc->buf_phys_addr, 23372adb719dSEzequiel Garcia tx_desc->data_size, 23382adb719dSEzequiel Garcia DMA_TO_DEVICE); 23392adb719dSEzequiel Garcia mvneta_txq_desc_put(txq); 23402adb719dSEzequiel Garcia } 23412adb719dSEzequiel Garcia return 0; 23422adb719dSEzequiel Garcia } 23432adb719dSEzequiel Garcia 2344c5aff182SThomas Petazzoni /* Handle tx fragmentation processing */ 2345c5aff182SThomas Petazzoni static int mvneta_tx_frag_process(struct mvneta_port *pp, struct sk_buff *skb, 2346c5aff182SThomas Petazzoni struct mvneta_tx_queue *txq) 2347c5aff182SThomas Petazzoni { 2348c5aff182SThomas Petazzoni struct mvneta_tx_desc *tx_desc; 23493d4ea02fSEzequiel Garcia int i, nr_frags = skb_shinfo(skb)->nr_frags; 2350c5aff182SThomas Petazzoni 23513d4ea02fSEzequiel Garcia for (i = 0; i < nr_frags; i++) { 2352c5aff182SThomas Petazzoni skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 2353d7840976SMatthew Wilcox (Oracle) void *addr = skb_frag_address(frag); 2354c5aff182SThomas Petazzoni 2355c5aff182SThomas Petazzoni tx_desc = mvneta_txq_next_desc_get(txq); 2356d7840976SMatthew Wilcox (Oracle) tx_desc->data_size = skb_frag_size(frag); 2357c5aff182SThomas Petazzoni 2358c5aff182SThomas Petazzoni tx_desc->buf_phys_addr = 2359c5aff182SThomas Petazzoni dma_map_single(pp->dev->dev.parent, addr, 2360c5aff182SThomas Petazzoni tx_desc->data_size, DMA_TO_DEVICE); 2361c5aff182SThomas Petazzoni 2362c5aff182SThomas Petazzoni if (dma_mapping_error(pp->dev->dev.parent, 2363c5aff182SThomas Petazzoni tx_desc->buf_phys_addr)) { 2364c5aff182SThomas Petazzoni mvneta_txq_desc_put(txq); 2365c5aff182SThomas Petazzoni goto error; 2366c5aff182SThomas Petazzoni } 2367c5aff182SThomas Petazzoni 23683d4ea02fSEzequiel Garcia if (i == nr_frags - 1) { 2369c5aff182SThomas Petazzoni /* Last descriptor */ 2370c5aff182SThomas Petazzoni tx_desc->command = MVNETA_TXD_L_DESC | MVNETA_TXD_Z_PAD; 2371c5aff182SThomas Petazzoni txq->tx_skb[txq->txq_put_index] = skb; 2372c5aff182SThomas Petazzoni } else { 2373c5aff182SThomas Petazzoni /* Descriptor in the middle: Not First, Not Last */ 2374c5aff182SThomas Petazzoni tx_desc->command = 0; 2375c5aff182SThomas Petazzoni txq->tx_skb[txq->txq_put_index] = NULL; 2376c5aff182SThomas Petazzoni } 23773d4ea02fSEzequiel Garcia mvneta_txq_inc_put(txq); 2378c5aff182SThomas Petazzoni } 2379c5aff182SThomas Petazzoni 2380c5aff182SThomas Petazzoni return 0; 2381c5aff182SThomas Petazzoni 2382c5aff182SThomas Petazzoni error: 2383c5aff182SThomas Petazzoni /* Release all descriptors that were used to map fragments of 23846a20c175SThomas Petazzoni * this packet, as well as the corresponding DMA mappings 23856a20c175SThomas Petazzoni */ 2386c5aff182SThomas Petazzoni for (i = i - 1; i >= 0; i--) { 2387c5aff182SThomas Petazzoni tx_desc = txq->descs + i; 2388c5aff182SThomas Petazzoni dma_unmap_single(pp->dev->dev.parent, 2389c5aff182SThomas Petazzoni tx_desc->buf_phys_addr, 2390c5aff182SThomas Petazzoni tx_desc->data_size, 2391c5aff182SThomas Petazzoni DMA_TO_DEVICE); 2392c5aff182SThomas Petazzoni mvneta_txq_desc_put(txq); 2393c5aff182SThomas Petazzoni } 2394c5aff182SThomas Petazzoni 2395c5aff182SThomas Petazzoni return -ENOMEM; 2396c5aff182SThomas Petazzoni } 2397c5aff182SThomas Petazzoni 2398c5aff182SThomas Petazzoni /* Main tx processing */ 2399f03508ceSYueHaibing static netdev_tx_t mvneta_tx(struct sk_buff *skb, struct net_device *dev) 2400c5aff182SThomas Petazzoni { 2401c5aff182SThomas Petazzoni struct mvneta_port *pp = netdev_priv(dev); 2402ee40a116SWilly Tarreau u16 txq_id = skb_get_queue_mapping(skb); 2403ee40a116SWilly Tarreau struct mvneta_tx_queue *txq = &pp->txqs[txq_id]; 2404c5aff182SThomas Petazzoni struct mvneta_tx_desc *tx_desc; 24055f478b41SEric Dumazet int len = skb->len; 2406c5aff182SThomas Petazzoni int frags = 0; 2407c5aff182SThomas Petazzoni u32 tx_cmd; 2408c5aff182SThomas Petazzoni 2409c5aff182SThomas Petazzoni if (!netif_running(dev)) 2410c5aff182SThomas Petazzoni goto out; 2411c5aff182SThomas Petazzoni 24122adb719dSEzequiel Garcia if (skb_is_gso(skb)) { 24132adb719dSEzequiel Garcia frags = mvneta_tx_tso(skb, dev, txq); 24142adb719dSEzequiel Garcia goto out; 24152adb719dSEzequiel Garcia } 24162adb719dSEzequiel Garcia 2417c5aff182SThomas Petazzoni frags = skb_shinfo(skb)->nr_frags + 1; 2418c5aff182SThomas Petazzoni 2419c5aff182SThomas Petazzoni /* Get a descriptor for the first part of the packet */ 2420c5aff182SThomas Petazzoni tx_desc = mvneta_txq_next_desc_get(txq); 2421c5aff182SThomas Petazzoni 2422c5aff182SThomas Petazzoni tx_cmd = mvneta_skb_tx_csum(pp, skb); 2423c5aff182SThomas Petazzoni 2424c5aff182SThomas Petazzoni tx_desc->data_size = skb_headlen(skb); 2425c5aff182SThomas Petazzoni 2426c5aff182SThomas Petazzoni tx_desc->buf_phys_addr = dma_map_single(dev->dev.parent, skb->data, 2427c5aff182SThomas Petazzoni tx_desc->data_size, 2428c5aff182SThomas Petazzoni DMA_TO_DEVICE); 2429c5aff182SThomas Petazzoni if (unlikely(dma_mapping_error(dev->dev.parent, 2430c5aff182SThomas Petazzoni tx_desc->buf_phys_addr))) { 2431c5aff182SThomas Petazzoni mvneta_txq_desc_put(txq); 2432c5aff182SThomas Petazzoni frags = 0; 2433c5aff182SThomas Petazzoni goto out; 2434c5aff182SThomas Petazzoni } 2435c5aff182SThomas Petazzoni 2436c5aff182SThomas Petazzoni if (frags == 1) { 2437c5aff182SThomas Petazzoni /* First and Last descriptor */ 2438c5aff182SThomas Petazzoni tx_cmd |= MVNETA_TXD_FLZ_DESC; 2439c5aff182SThomas Petazzoni tx_desc->command = tx_cmd; 2440c5aff182SThomas Petazzoni txq->tx_skb[txq->txq_put_index] = skb; 2441c5aff182SThomas Petazzoni mvneta_txq_inc_put(txq); 2442c5aff182SThomas Petazzoni } else { 2443c5aff182SThomas Petazzoni /* First but not Last */ 2444c5aff182SThomas Petazzoni tx_cmd |= MVNETA_TXD_F_DESC; 2445c5aff182SThomas Petazzoni txq->tx_skb[txq->txq_put_index] = NULL; 2446c5aff182SThomas Petazzoni mvneta_txq_inc_put(txq); 2447c5aff182SThomas Petazzoni tx_desc->command = tx_cmd; 2448c5aff182SThomas Petazzoni /* Continue with other skb fragments */ 2449c5aff182SThomas Petazzoni if (mvneta_tx_frag_process(pp, skb, txq)) { 2450c5aff182SThomas Petazzoni dma_unmap_single(dev->dev.parent, 2451c5aff182SThomas Petazzoni tx_desc->buf_phys_addr, 2452c5aff182SThomas Petazzoni tx_desc->data_size, 2453c5aff182SThomas Petazzoni DMA_TO_DEVICE); 2454c5aff182SThomas Petazzoni mvneta_txq_desc_put(txq); 2455c5aff182SThomas Petazzoni frags = 0; 2456c5aff182SThomas Petazzoni goto out; 2457c5aff182SThomas Petazzoni } 2458c5aff182SThomas Petazzoni } 2459c5aff182SThomas Petazzoni 2460e19d2ddaSEzequiel Garcia out: 2461e19d2ddaSEzequiel Garcia if (frags > 0) { 2462e19d2ddaSEzequiel Garcia struct mvneta_pcpu_stats *stats = this_cpu_ptr(pp->stats); 2463e19d2ddaSEzequiel Garcia struct netdev_queue *nq = netdev_get_tx_queue(dev, txq_id); 2464e19d2ddaSEzequiel Garcia 2465a29b6235SMarcin Wojtas netdev_tx_sent_queue(nq, len); 2466a29b6235SMarcin Wojtas 2467c5aff182SThomas Petazzoni txq->count += frags; 24688eef5f97SEzequiel Garcia if (txq->count >= txq->tx_stop_threshold) 2469c5aff182SThomas Petazzoni netif_tx_stop_queue(nq); 2470c5aff182SThomas Petazzoni 24716b16f9eeSFlorian Westphal if (!netdev_xmit_more() || netif_xmit_stopped(nq) || 24722a90f7e1SSimon Guinot txq->pending + frags > MVNETA_TXQ_DEC_SENT_MASK) 24732a90f7e1SSimon Guinot mvneta_txq_pend_desc_add(pp, txq, frags); 24742a90f7e1SSimon Guinot else 24752a90f7e1SSimon Guinot txq->pending += frags; 24762a90f7e1SSimon Guinot 247774c41b04Swilly tarreau u64_stats_update_begin(&stats->syncp); 247874c41b04Swilly tarreau stats->tx_packets++; 24795f478b41SEric Dumazet stats->tx_bytes += len; 248074c41b04Swilly tarreau u64_stats_update_end(&stats->syncp); 2481c5aff182SThomas Petazzoni } else { 2482c5aff182SThomas Petazzoni dev->stats.tx_dropped++; 2483c5aff182SThomas Petazzoni dev_kfree_skb_any(skb); 2484c5aff182SThomas Petazzoni } 2485c5aff182SThomas Petazzoni 2486c5aff182SThomas Petazzoni return NETDEV_TX_OK; 2487c5aff182SThomas Petazzoni } 2488c5aff182SThomas Petazzoni 2489c5aff182SThomas Petazzoni 2490c5aff182SThomas Petazzoni /* Free tx resources, when resetting a port */ 2491c5aff182SThomas Petazzoni static void mvneta_txq_done_force(struct mvneta_port *pp, 2492c5aff182SThomas Petazzoni struct mvneta_tx_queue *txq) 2493c5aff182SThomas Petazzoni 2494c5aff182SThomas Petazzoni { 2495a29b6235SMarcin Wojtas struct netdev_queue *nq = netdev_get_tx_queue(pp->dev, txq->id); 2496c5aff182SThomas Petazzoni int tx_done = txq->count; 2497c5aff182SThomas Petazzoni 2498a29b6235SMarcin Wojtas mvneta_txq_bufs_free(pp, txq, tx_done, nq); 2499c5aff182SThomas Petazzoni 2500c5aff182SThomas Petazzoni /* reset txq */ 2501c5aff182SThomas Petazzoni txq->count = 0; 2502c5aff182SThomas Petazzoni txq->txq_put_index = 0; 2503c5aff182SThomas Petazzoni txq->txq_get_index = 0; 2504c5aff182SThomas Petazzoni } 2505c5aff182SThomas Petazzoni 25066c498974Swilly tarreau /* Handle tx done - called in softirq context. The <cause_tx_done> argument 25076c498974Swilly tarreau * must be a valid cause according to MVNETA_TXQ_INTR_MASK_ALL. 25086c498974Swilly tarreau */ 25090713a86aSArnaud Ebalard static void mvneta_tx_done_gbe(struct mvneta_port *pp, u32 cause_tx_done) 2510c5aff182SThomas Petazzoni { 2511c5aff182SThomas Petazzoni struct mvneta_tx_queue *txq; 2512c5aff182SThomas Petazzoni struct netdev_queue *nq; 2513bd9f1ee3SJisheng Zhang int cpu = smp_processor_id(); 2514c5aff182SThomas Petazzoni 25156c498974Swilly tarreau while (cause_tx_done) { 2516c5aff182SThomas Petazzoni txq = mvneta_tx_done_policy(pp, cause_tx_done); 2517c5aff182SThomas Petazzoni 2518c5aff182SThomas Petazzoni nq = netdev_get_tx_queue(pp->dev, txq->id); 2519bd9f1ee3SJisheng Zhang __netif_tx_lock(nq, cpu); 2520c5aff182SThomas Petazzoni 25210713a86aSArnaud Ebalard if (txq->count) 25220713a86aSArnaud Ebalard mvneta_txq_done(pp, txq); 2523c5aff182SThomas Petazzoni 2524c5aff182SThomas Petazzoni __netif_tx_unlock(nq); 2525c5aff182SThomas Petazzoni cause_tx_done &= ~((1 << txq->id)); 2526c5aff182SThomas Petazzoni } 2527c5aff182SThomas Petazzoni } 2528c5aff182SThomas Petazzoni 25296a20c175SThomas Petazzoni /* Compute crc8 of the specified address, using a unique algorithm , 2530c5aff182SThomas Petazzoni * according to hw spec, different than generic crc8 algorithm 2531c5aff182SThomas Petazzoni */ 2532c5aff182SThomas Petazzoni static int mvneta_addr_crc(unsigned char *addr) 2533c5aff182SThomas Petazzoni { 2534c5aff182SThomas Petazzoni int crc = 0; 2535c5aff182SThomas Petazzoni int i; 2536c5aff182SThomas Petazzoni 2537c5aff182SThomas Petazzoni for (i = 0; i < ETH_ALEN; i++) { 2538c5aff182SThomas Petazzoni int j; 2539c5aff182SThomas Petazzoni 2540c5aff182SThomas Petazzoni crc = (crc ^ addr[i]) << 8; 2541c5aff182SThomas Petazzoni for (j = 7; j >= 0; j--) { 2542c5aff182SThomas Petazzoni if (crc & (0x100 << j)) 2543c5aff182SThomas Petazzoni crc ^= 0x107 << j; 2544c5aff182SThomas Petazzoni } 2545c5aff182SThomas Petazzoni } 2546c5aff182SThomas Petazzoni 2547c5aff182SThomas Petazzoni return crc; 2548c5aff182SThomas Petazzoni } 2549c5aff182SThomas Petazzoni 2550c5aff182SThomas Petazzoni /* This method controls the net device special MAC multicast support. 2551c5aff182SThomas Petazzoni * The Special Multicast Table for MAC addresses supports MAC of the form 2552c5aff182SThomas Petazzoni * 0x01-00-5E-00-00-XX (where XX is between 0x00 and 0xFF). 2553c5aff182SThomas Petazzoni * The MAC DA[7:0] bits are used as a pointer to the Special Multicast 2554c5aff182SThomas Petazzoni * Table entries in the DA-Filter table. This method set the Special 2555c5aff182SThomas Petazzoni * Multicast Table appropriate entry. 2556c5aff182SThomas Petazzoni */ 2557c5aff182SThomas Petazzoni static void mvneta_set_special_mcast_addr(struct mvneta_port *pp, 2558c5aff182SThomas Petazzoni unsigned char last_byte, 2559c5aff182SThomas Petazzoni int queue) 2560c5aff182SThomas Petazzoni { 2561c5aff182SThomas Petazzoni unsigned int smc_table_reg; 2562c5aff182SThomas Petazzoni unsigned int tbl_offset; 2563c5aff182SThomas Petazzoni unsigned int reg_offset; 2564c5aff182SThomas Petazzoni 2565c5aff182SThomas Petazzoni /* Register offset from SMC table base */ 2566c5aff182SThomas Petazzoni tbl_offset = (last_byte / 4); 2567c5aff182SThomas Petazzoni /* Entry offset within the above reg */ 2568c5aff182SThomas Petazzoni reg_offset = last_byte % 4; 2569c5aff182SThomas Petazzoni 2570c5aff182SThomas Petazzoni smc_table_reg = mvreg_read(pp, (MVNETA_DA_FILT_SPEC_MCAST 2571c5aff182SThomas Petazzoni + tbl_offset * 4)); 2572c5aff182SThomas Petazzoni 2573c5aff182SThomas Petazzoni if (queue == -1) 2574c5aff182SThomas Petazzoni smc_table_reg &= ~(0xff << (8 * reg_offset)); 2575c5aff182SThomas Petazzoni else { 2576c5aff182SThomas Petazzoni smc_table_reg &= ~(0xff << (8 * reg_offset)); 2577c5aff182SThomas Petazzoni smc_table_reg |= ((0x01 | (queue << 1)) << (8 * reg_offset)); 2578c5aff182SThomas Petazzoni } 2579c5aff182SThomas Petazzoni 2580c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_DA_FILT_SPEC_MCAST + tbl_offset * 4, 2581c5aff182SThomas Petazzoni smc_table_reg); 2582c5aff182SThomas Petazzoni } 2583c5aff182SThomas Petazzoni 2584c5aff182SThomas Petazzoni /* This method controls the network device Other MAC multicast support. 2585c5aff182SThomas Petazzoni * The Other Multicast Table is used for multicast of another type. 2586c5aff182SThomas Petazzoni * A CRC-8 is used as an index to the Other Multicast Table entries 2587c5aff182SThomas Petazzoni * in the DA-Filter table. 2588c5aff182SThomas Petazzoni * The method gets the CRC-8 value from the calling routine and 2589c5aff182SThomas Petazzoni * sets the Other Multicast Table appropriate entry according to the 2590c5aff182SThomas Petazzoni * specified CRC-8 . 2591c5aff182SThomas Petazzoni */ 2592c5aff182SThomas Petazzoni static void mvneta_set_other_mcast_addr(struct mvneta_port *pp, 2593c5aff182SThomas Petazzoni unsigned char crc8, 2594c5aff182SThomas Petazzoni int queue) 2595c5aff182SThomas Petazzoni { 2596c5aff182SThomas Petazzoni unsigned int omc_table_reg; 2597c5aff182SThomas Petazzoni unsigned int tbl_offset; 2598c5aff182SThomas Petazzoni unsigned int reg_offset; 2599c5aff182SThomas Petazzoni 2600c5aff182SThomas Petazzoni tbl_offset = (crc8 / 4) * 4; /* Register offset from OMC table base */ 2601c5aff182SThomas Petazzoni reg_offset = crc8 % 4; /* Entry offset within the above reg */ 2602c5aff182SThomas Petazzoni 2603c5aff182SThomas Petazzoni omc_table_reg = mvreg_read(pp, MVNETA_DA_FILT_OTH_MCAST + tbl_offset); 2604c5aff182SThomas Petazzoni 2605c5aff182SThomas Petazzoni if (queue == -1) { 2606c5aff182SThomas Petazzoni /* Clear accepts frame bit at specified Other DA table entry */ 2607c5aff182SThomas Petazzoni omc_table_reg &= ~(0xff << (8 * reg_offset)); 2608c5aff182SThomas Petazzoni } else { 2609c5aff182SThomas Petazzoni omc_table_reg &= ~(0xff << (8 * reg_offset)); 2610c5aff182SThomas Petazzoni omc_table_reg |= ((0x01 | (queue << 1)) << (8 * reg_offset)); 2611c5aff182SThomas Petazzoni } 2612c5aff182SThomas Petazzoni 2613c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_DA_FILT_OTH_MCAST + tbl_offset, omc_table_reg); 2614c5aff182SThomas Petazzoni } 2615c5aff182SThomas Petazzoni 2616c5aff182SThomas Petazzoni /* The network device supports multicast using two tables: 2617c5aff182SThomas Petazzoni * 1) Special Multicast Table for MAC addresses of the form 2618c5aff182SThomas Petazzoni * 0x01-00-5E-00-00-XX (where XX is between 0x00 and 0xFF). 2619c5aff182SThomas Petazzoni * The MAC DA[7:0] bits are used as a pointer to the Special Multicast 2620c5aff182SThomas Petazzoni * Table entries in the DA-Filter table. 2621c5aff182SThomas Petazzoni * 2) Other Multicast Table for multicast of another type. A CRC-8 value 2622c5aff182SThomas Petazzoni * is used as an index to the Other Multicast Table entries in the 2623c5aff182SThomas Petazzoni * DA-Filter table. 2624c5aff182SThomas Petazzoni */ 2625c5aff182SThomas Petazzoni static int mvneta_mcast_addr_set(struct mvneta_port *pp, unsigned char *p_addr, 2626c5aff182SThomas Petazzoni int queue) 2627c5aff182SThomas Petazzoni { 2628c5aff182SThomas Petazzoni unsigned char crc_result = 0; 2629c5aff182SThomas Petazzoni 2630c5aff182SThomas Petazzoni if (memcmp(p_addr, "\x01\x00\x5e\x00\x00", 5) == 0) { 2631c5aff182SThomas Petazzoni mvneta_set_special_mcast_addr(pp, p_addr[5], queue); 2632c5aff182SThomas Petazzoni return 0; 2633c5aff182SThomas Petazzoni } 2634c5aff182SThomas Petazzoni 2635c5aff182SThomas Petazzoni crc_result = mvneta_addr_crc(p_addr); 2636c5aff182SThomas Petazzoni if (queue == -1) { 2637c5aff182SThomas Petazzoni if (pp->mcast_count[crc_result] == 0) { 2638c5aff182SThomas Petazzoni netdev_info(pp->dev, "No valid Mcast for crc8=0x%02x\n", 2639c5aff182SThomas Petazzoni crc_result); 2640c5aff182SThomas Petazzoni return -EINVAL; 2641c5aff182SThomas Petazzoni } 2642c5aff182SThomas Petazzoni 2643c5aff182SThomas Petazzoni pp->mcast_count[crc_result]--; 2644c5aff182SThomas Petazzoni if (pp->mcast_count[crc_result] != 0) { 2645c5aff182SThomas Petazzoni netdev_info(pp->dev, 2646c5aff182SThomas Petazzoni "After delete there are %d valid Mcast for crc8=0x%02x\n", 2647c5aff182SThomas Petazzoni pp->mcast_count[crc_result], crc_result); 2648c5aff182SThomas Petazzoni return -EINVAL; 2649c5aff182SThomas Petazzoni } 2650c5aff182SThomas Petazzoni } else 2651c5aff182SThomas Petazzoni pp->mcast_count[crc_result]++; 2652c5aff182SThomas Petazzoni 2653c5aff182SThomas Petazzoni mvneta_set_other_mcast_addr(pp, crc_result, queue); 2654c5aff182SThomas Petazzoni 2655c5aff182SThomas Petazzoni return 0; 2656c5aff182SThomas Petazzoni } 2657c5aff182SThomas Petazzoni 2658c5aff182SThomas Petazzoni /* Configure Fitering mode of Ethernet port */ 2659c5aff182SThomas Petazzoni static void mvneta_rx_unicast_promisc_set(struct mvneta_port *pp, 2660c5aff182SThomas Petazzoni int is_promisc) 2661c5aff182SThomas Petazzoni { 2662c5aff182SThomas Petazzoni u32 port_cfg_reg, val; 2663c5aff182SThomas Petazzoni 2664c5aff182SThomas Petazzoni port_cfg_reg = mvreg_read(pp, MVNETA_PORT_CONFIG); 2665c5aff182SThomas Petazzoni 2666c5aff182SThomas Petazzoni val = mvreg_read(pp, MVNETA_TYPE_PRIO); 2667c5aff182SThomas Petazzoni 2668c5aff182SThomas Petazzoni /* Set / Clear UPM bit in port configuration register */ 2669c5aff182SThomas Petazzoni if (is_promisc) { 2670c5aff182SThomas Petazzoni /* Accept all Unicast addresses */ 2671c5aff182SThomas Petazzoni port_cfg_reg |= MVNETA_UNI_PROMISC_MODE; 2672c5aff182SThomas Petazzoni val |= MVNETA_FORCE_UNI; 2673c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_MAC_ADDR_LOW, 0xffff); 2674c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_MAC_ADDR_HIGH, 0xffffffff); 2675c5aff182SThomas Petazzoni } else { 2676c5aff182SThomas Petazzoni /* Reject all Unicast addresses */ 2677c5aff182SThomas Petazzoni port_cfg_reg &= ~MVNETA_UNI_PROMISC_MODE; 2678c5aff182SThomas Petazzoni val &= ~MVNETA_FORCE_UNI; 2679c5aff182SThomas Petazzoni } 2680c5aff182SThomas Petazzoni 2681c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_PORT_CONFIG, port_cfg_reg); 2682c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_TYPE_PRIO, val); 2683c5aff182SThomas Petazzoni } 2684c5aff182SThomas Petazzoni 2685c5aff182SThomas Petazzoni /* register unicast and multicast addresses */ 2686c5aff182SThomas Petazzoni static void mvneta_set_rx_mode(struct net_device *dev) 2687c5aff182SThomas Petazzoni { 2688c5aff182SThomas Petazzoni struct mvneta_port *pp = netdev_priv(dev); 2689c5aff182SThomas Petazzoni struct netdev_hw_addr *ha; 2690c5aff182SThomas Petazzoni 2691c5aff182SThomas Petazzoni if (dev->flags & IFF_PROMISC) { 2692c5aff182SThomas Petazzoni /* Accept all: Multicast + Unicast */ 2693c5aff182SThomas Petazzoni mvneta_rx_unicast_promisc_set(pp, 1); 269490b74c01SGregory CLEMENT mvneta_set_ucast_table(pp, pp->rxq_def); 269590b74c01SGregory CLEMENT mvneta_set_special_mcast_table(pp, pp->rxq_def); 269690b74c01SGregory CLEMENT mvneta_set_other_mcast_table(pp, pp->rxq_def); 2697c5aff182SThomas Petazzoni } else { 2698c5aff182SThomas Petazzoni /* Accept single Unicast */ 2699c5aff182SThomas Petazzoni mvneta_rx_unicast_promisc_set(pp, 0); 2700c5aff182SThomas Petazzoni mvneta_set_ucast_table(pp, -1); 270190b74c01SGregory CLEMENT mvneta_mac_addr_set(pp, dev->dev_addr, pp->rxq_def); 2702c5aff182SThomas Petazzoni 2703c5aff182SThomas Petazzoni if (dev->flags & IFF_ALLMULTI) { 2704c5aff182SThomas Petazzoni /* Accept all multicast */ 270590b74c01SGregory CLEMENT mvneta_set_special_mcast_table(pp, pp->rxq_def); 270690b74c01SGregory CLEMENT mvneta_set_other_mcast_table(pp, pp->rxq_def); 2707c5aff182SThomas Petazzoni } else { 2708c5aff182SThomas Petazzoni /* Accept only initialized multicast */ 2709c5aff182SThomas Petazzoni mvneta_set_special_mcast_table(pp, -1); 2710c5aff182SThomas Petazzoni mvneta_set_other_mcast_table(pp, -1); 2711c5aff182SThomas Petazzoni 2712c5aff182SThomas Petazzoni if (!netdev_mc_empty(dev)) { 2713c5aff182SThomas Petazzoni netdev_for_each_mc_addr(ha, dev) { 2714c5aff182SThomas Petazzoni mvneta_mcast_addr_set(pp, ha->addr, 271590b74c01SGregory CLEMENT pp->rxq_def); 2716c5aff182SThomas Petazzoni } 2717c5aff182SThomas Petazzoni } 2718c5aff182SThomas Petazzoni } 2719c5aff182SThomas Petazzoni } 2720c5aff182SThomas Petazzoni } 2721c5aff182SThomas Petazzoni 2722c5aff182SThomas Petazzoni /* Interrupt handling - the callback for request_irq() */ 2723c5aff182SThomas Petazzoni static irqreturn_t mvneta_isr(int irq, void *dev_id) 2724c5aff182SThomas Petazzoni { 27252636ac3cSMarcin Wojtas struct mvneta_port *pp = (struct mvneta_port *)dev_id; 27262636ac3cSMarcin Wojtas 27272636ac3cSMarcin Wojtas mvreg_write(pp, MVNETA_INTR_NEW_MASK, 0); 27282636ac3cSMarcin Wojtas napi_schedule(&pp->napi); 27292636ac3cSMarcin Wojtas 27302636ac3cSMarcin Wojtas return IRQ_HANDLED; 27312636ac3cSMarcin Wojtas } 27322636ac3cSMarcin Wojtas 27332636ac3cSMarcin Wojtas /* Interrupt handling - the callback for request_percpu_irq() */ 27342636ac3cSMarcin Wojtas static irqreturn_t mvneta_percpu_isr(int irq, void *dev_id) 27352636ac3cSMarcin Wojtas { 273612bb03b4SMaxime Ripard struct mvneta_pcpu_port *port = (struct mvneta_pcpu_port *)dev_id; 2737c5aff182SThomas Petazzoni 273812bb03b4SMaxime Ripard disable_percpu_irq(port->pp->dev->irq); 273912bb03b4SMaxime Ripard napi_schedule(&port->napi); 2740c5aff182SThomas Petazzoni 2741c5aff182SThomas Petazzoni return IRQ_HANDLED; 2742c5aff182SThomas Petazzoni } 2743c5aff182SThomas Petazzoni 2744503f9aa9SRussell King static void mvneta_link_change(struct mvneta_port *pp) 2745898b2970SStas Sergeev { 2746898b2970SStas Sergeev u32 gmac_stat = mvreg_read(pp, MVNETA_GMAC_STATUS); 2747898b2970SStas Sergeev 2748503f9aa9SRussell King phylink_mac_change(pp->phylink, !!(gmac_stat & MVNETA_GMAC_LINK_UP)); 2749898b2970SStas Sergeev } 2750898b2970SStas Sergeev 2751c5aff182SThomas Petazzoni /* NAPI handler 2752c5aff182SThomas Petazzoni * Bits 0 - 7 of the causeRxTx register indicate that are transmitted 2753c5aff182SThomas Petazzoni * packets on the corresponding TXQ (Bit 0 is for TX queue 1). 2754c5aff182SThomas Petazzoni * Bits 8 -15 of the cause Rx Tx register indicate that are received 2755c5aff182SThomas Petazzoni * packets on the corresponding RXQ (Bit 8 is for RX queue 0). 2756c5aff182SThomas Petazzoni * Each CPU has its own causeRxTx register 2757c5aff182SThomas Petazzoni */ 2758c5aff182SThomas Petazzoni static int mvneta_poll(struct napi_struct *napi, int budget) 2759c5aff182SThomas Petazzoni { 2760c5aff182SThomas Petazzoni int rx_done = 0; 2761c5aff182SThomas Petazzoni u32 cause_rx_tx; 27622dcf75e2SGregory CLEMENT int rx_queue; 2763c5aff182SThomas Petazzoni struct mvneta_port *pp = netdev_priv(napi->dev); 276412bb03b4SMaxime Ripard struct mvneta_pcpu_port *port = this_cpu_ptr(pp->ports); 2765c5aff182SThomas Petazzoni 2766c5aff182SThomas Petazzoni if (!netif_running(pp->dev)) { 27672636ac3cSMarcin Wojtas napi_complete(napi); 2768c5aff182SThomas Petazzoni return rx_done; 2769c5aff182SThomas Petazzoni } 2770c5aff182SThomas Petazzoni 2771c5aff182SThomas Petazzoni /* Read cause register */ 2772898b2970SStas Sergeev cause_rx_tx = mvreg_read(pp, MVNETA_INTR_NEW_CAUSE); 2773898b2970SStas Sergeev if (cause_rx_tx & MVNETA_MISCINTR_INTR_MASK) { 2774898b2970SStas Sergeev u32 cause_misc = mvreg_read(pp, MVNETA_INTR_MISC_CAUSE); 2775898b2970SStas Sergeev 2776898b2970SStas Sergeev mvreg_write(pp, MVNETA_INTR_MISC_CAUSE, 0); 2777503f9aa9SRussell King 2778503f9aa9SRussell King if (cause_misc & (MVNETA_CAUSE_PHY_STATUS_CHANGE | 2779856b2cc5SRussell King MVNETA_CAUSE_LINK_CHANGE)) 2780503f9aa9SRussell King mvneta_link_change(pp); 2781898b2970SStas Sergeev } 278271f6d1b3Swilly tarreau 278371f6d1b3Swilly tarreau /* Release Tx descriptors */ 278471f6d1b3Swilly tarreau if (cause_rx_tx & MVNETA_TX_INTR_MASK_ALL) { 27850713a86aSArnaud Ebalard mvneta_tx_done_gbe(pp, (cause_rx_tx & MVNETA_TX_INTR_MASK_ALL)); 278671f6d1b3Swilly tarreau cause_rx_tx &= ~MVNETA_TX_INTR_MASK_ALL; 278771f6d1b3Swilly tarreau } 2788c5aff182SThomas Petazzoni 27896a20c175SThomas Petazzoni /* For the case where the last mvneta_poll did not process all 2790c5aff182SThomas Petazzoni * RX packets 2791c5aff182SThomas Petazzoni */ 27922dcf75e2SGregory CLEMENT rx_queue = fls(((cause_rx_tx >> 8) & 0xff)); 27932dcf75e2SGregory CLEMENT 27942636ac3cSMarcin Wojtas cause_rx_tx |= pp->neta_armada3700 ? pp->cause_rx_tx : 27952636ac3cSMarcin Wojtas port->cause_rx_tx; 27962dcf75e2SGregory CLEMENT 27972dcf75e2SGregory CLEMENT if (rx_queue) { 27982dcf75e2SGregory CLEMENT rx_queue = rx_queue - 1; 2799dc35a10fSMarcin Wojtas if (pp->bm_priv) 28007a86f05fSAndrew Lunn rx_done = mvneta_rx_hwbm(napi, pp, budget, 28017a86f05fSAndrew Lunn &pp->rxqs[rx_queue]); 2802dc35a10fSMarcin Wojtas else 28037a86f05fSAndrew Lunn rx_done = mvneta_rx_swbm(napi, pp, budget, 28047a86f05fSAndrew Lunn &pp->rxqs[rx_queue]); 28052dcf75e2SGregory CLEMENT } 28062dcf75e2SGregory CLEMENT 28076ad20165SEric Dumazet if (rx_done < budget) { 2808c5aff182SThomas Petazzoni cause_rx_tx = 0; 28096ad20165SEric Dumazet napi_complete_done(napi, rx_done); 28102636ac3cSMarcin Wojtas 28112636ac3cSMarcin Wojtas if (pp->neta_armada3700) { 28122636ac3cSMarcin Wojtas unsigned long flags; 28132636ac3cSMarcin Wojtas 28142636ac3cSMarcin Wojtas local_irq_save(flags); 28152636ac3cSMarcin Wojtas mvreg_write(pp, MVNETA_INTR_NEW_MASK, 28162636ac3cSMarcin Wojtas MVNETA_RX_INTR_MASK(rxq_number) | 28172636ac3cSMarcin Wojtas MVNETA_TX_INTR_MASK(txq_number) | 28182636ac3cSMarcin Wojtas MVNETA_MISCINTR_INTR_MASK); 28192636ac3cSMarcin Wojtas local_irq_restore(flags); 28202636ac3cSMarcin Wojtas } else { 282112bb03b4SMaxime Ripard enable_percpu_irq(pp->dev->irq, 0); 2822c5aff182SThomas Petazzoni } 28232636ac3cSMarcin Wojtas } 2824c5aff182SThomas Petazzoni 28252636ac3cSMarcin Wojtas if (pp->neta_armada3700) 28262636ac3cSMarcin Wojtas pp->cause_rx_tx = cause_rx_tx; 28272636ac3cSMarcin Wojtas else 282812bb03b4SMaxime Ripard port->cause_rx_tx = cause_rx_tx; 28292636ac3cSMarcin Wojtas 2830c5aff182SThomas Petazzoni return rx_done; 2831c5aff182SThomas Petazzoni } 2832c5aff182SThomas Petazzoni 2833c5aff182SThomas Petazzoni /* Handle rxq fill: allocates rxq skbs; called when initializing a port */ 2834c5aff182SThomas Petazzoni static int mvneta_rxq_fill(struct mvneta_port *pp, struct mvneta_rx_queue *rxq, 2835c5aff182SThomas Petazzoni int num) 2836c5aff182SThomas Petazzoni { 2837c5aff182SThomas Petazzoni int i; 2838c5aff182SThomas Petazzoni 2839c5aff182SThomas Petazzoni for (i = 0; i < num; i++) { 2840a1a65ab1Swilly tarreau memset(rxq->descs + i, 0, sizeof(struct mvneta_rx_desc)); 28417e47fd84SGregory CLEMENT if (mvneta_rx_refill(pp, rxq->descs + i, rxq, 28427e47fd84SGregory CLEMENT GFP_KERNEL) != 0) { 28437e47fd84SGregory CLEMENT netdev_err(pp->dev, 28447e47fd84SGregory CLEMENT "%s:rxq %d, %d of %d buffs filled\n", 2845c5aff182SThomas Petazzoni __func__, rxq->id, i, num); 2846c5aff182SThomas Petazzoni break; 2847c5aff182SThomas Petazzoni } 2848c5aff182SThomas Petazzoni } 2849c5aff182SThomas Petazzoni 2850c5aff182SThomas Petazzoni /* Add this number of RX descriptors as non occupied (ready to 28516a20c175SThomas Petazzoni * get packets) 28526a20c175SThomas Petazzoni */ 2853c5aff182SThomas Petazzoni mvneta_rxq_non_occup_desc_add(pp, rxq, i); 2854c5aff182SThomas Petazzoni 2855c5aff182SThomas Petazzoni return i; 2856c5aff182SThomas Petazzoni } 2857c5aff182SThomas Petazzoni 2858c5aff182SThomas Petazzoni /* Free all packets pending transmit from all TXQs and reset TX port */ 2859c5aff182SThomas Petazzoni static void mvneta_tx_reset(struct mvneta_port *pp) 2860c5aff182SThomas Petazzoni { 2861c5aff182SThomas Petazzoni int queue; 2862c5aff182SThomas Petazzoni 28639672850bSEzequiel Garcia /* free the skb's in the tx ring */ 2864c5aff182SThomas Petazzoni for (queue = 0; queue < txq_number; queue++) 2865c5aff182SThomas Petazzoni mvneta_txq_done_force(pp, &pp->txqs[queue]); 2866c5aff182SThomas Petazzoni 2867c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_PORT_TX_RESET, MVNETA_PORT_TX_DMA_RESET); 2868c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_PORT_TX_RESET, 0); 2869c5aff182SThomas Petazzoni } 2870c5aff182SThomas Petazzoni 2871c5aff182SThomas Petazzoni static void mvneta_rx_reset(struct mvneta_port *pp) 2872c5aff182SThomas Petazzoni { 2873c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_PORT_RX_RESET, MVNETA_PORT_RX_DMA_RESET); 2874c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_PORT_RX_RESET, 0); 2875c5aff182SThomas Petazzoni } 2876c5aff182SThomas Petazzoni 2877c5aff182SThomas Petazzoni /* Rx/Tx queue initialization/cleanup methods */ 2878c5aff182SThomas Petazzoni 28794a188a63SJisheng Zhang static int mvneta_rxq_sw_init(struct mvneta_port *pp, 2880c5aff182SThomas Petazzoni struct mvneta_rx_queue *rxq) 2881c5aff182SThomas Petazzoni { 2882c5aff182SThomas Petazzoni rxq->size = pp->rx_ring_size; 2883c5aff182SThomas Petazzoni 2884c5aff182SThomas Petazzoni /* Allocate memory for RX descriptors */ 2885c5aff182SThomas Petazzoni rxq->descs = dma_alloc_coherent(pp->dev->dev.parent, 2886c5aff182SThomas Petazzoni rxq->size * MVNETA_DESC_ALIGNED_SIZE, 2887c5aff182SThomas Petazzoni &rxq->descs_phys, GFP_KERNEL); 2888f95936ccSMarkus Elfring if (!rxq->descs) 2889c5aff182SThomas Petazzoni return -ENOMEM; 2890c5aff182SThomas Petazzoni 2891c5aff182SThomas Petazzoni rxq->last_desc = rxq->size - 1; 2892c5aff182SThomas Petazzoni 28934a188a63SJisheng Zhang return 0; 28944a188a63SJisheng Zhang } 28954a188a63SJisheng Zhang 28964a188a63SJisheng Zhang static void mvneta_rxq_hw_init(struct mvneta_port *pp, 28974a188a63SJisheng Zhang struct mvneta_rx_queue *rxq) 28984a188a63SJisheng Zhang { 2899c5aff182SThomas Petazzoni /* Set Rx descriptors queue starting address */ 2900c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_RXQ_BASE_ADDR_REG(rxq->id), rxq->descs_phys); 2901c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_RXQ_SIZE_REG(rxq->id), rxq->size); 2902c5aff182SThomas Petazzoni 2903c5aff182SThomas Petazzoni /* Set coalescing pkts and time */ 2904c5aff182SThomas Petazzoni mvneta_rx_pkts_coal_set(pp, rxq, rxq->pkts_coal); 2905c5aff182SThomas Petazzoni mvneta_rx_time_coal_set(pp, rxq, rxq->time_coal); 2906c5aff182SThomas Petazzoni 2907dc35a10fSMarcin Wojtas if (!pp->bm_priv) { 2908562e2f46SYelena Krivosheev /* Set Offset */ 2909562e2f46SYelena Krivosheev mvneta_rxq_offset_set(pp, rxq, 0); 2910e735fd55SMarcin Wojtas mvneta_rxq_buf_size_set(pp, rxq, PAGE_SIZE < SZ_64K ? 2911e735fd55SMarcin Wojtas PAGE_SIZE : 2912e735fd55SMarcin Wojtas MVNETA_RX_BUF_SIZE(pp->pkt_size)); 2913c5aff182SThomas Petazzoni mvneta_rxq_bm_disable(pp, rxq); 2914e9f64999SGregory CLEMENT mvneta_rxq_fill(pp, rxq, rxq->size); 2915dc35a10fSMarcin Wojtas } else { 2916562e2f46SYelena Krivosheev /* Set Offset */ 2917562e2f46SYelena Krivosheev mvneta_rxq_offset_set(pp, rxq, 2918562e2f46SYelena Krivosheev NET_SKB_PAD - pp->rx_offset_correction); 2919562e2f46SYelena Krivosheev 2920dc35a10fSMarcin Wojtas mvneta_rxq_bm_enable(pp, rxq); 2921562e2f46SYelena Krivosheev /* Fill RXQ with buffers from RX pool */ 2922dc35a10fSMarcin Wojtas mvneta_rxq_long_pool_set(pp, rxq); 2923dc35a10fSMarcin Wojtas mvneta_rxq_short_pool_set(pp, rxq); 2924e9f64999SGregory CLEMENT mvneta_rxq_non_occup_desc_add(pp, rxq, rxq->size); 2925dc35a10fSMarcin Wojtas } 29264a188a63SJisheng Zhang } 29274a188a63SJisheng Zhang 29284a188a63SJisheng Zhang /* Create a specified RX queue */ 29294a188a63SJisheng Zhang static int mvneta_rxq_init(struct mvneta_port *pp, 29304a188a63SJisheng Zhang struct mvneta_rx_queue *rxq) 29314a188a63SJisheng Zhang 29324a188a63SJisheng Zhang { 29334a188a63SJisheng Zhang int ret; 29344a188a63SJisheng Zhang 29354a188a63SJisheng Zhang ret = mvneta_rxq_sw_init(pp, rxq); 29364a188a63SJisheng Zhang if (ret < 0) 29374a188a63SJisheng Zhang return ret; 29384a188a63SJisheng Zhang 29394a188a63SJisheng Zhang mvneta_rxq_hw_init(pp, rxq); 2940dc35a10fSMarcin Wojtas 2941c5aff182SThomas Petazzoni return 0; 2942c5aff182SThomas Petazzoni } 2943c5aff182SThomas Petazzoni 2944c5aff182SThomas Petazzoni /* Cleanup Rx queue */ 2945c5aff182SThomas Petazzoni static void mvneta_rxq_deinit(struct mvneta_port *pp, 2946c5aff182SThomas Petazzoni struct mvneta_rx_queue *rxq) 2947c5aff182SThomas Petazzoni { 2948c5aff182SThomas Petazzoni mvneta_rxq_drop_pkts(pp, rxq); 2949c5aff182SThomas Petazzoni 2950562e2f46SYelena Krivosheev if (rxq->skb) 2951562e2f46SYelena Krivosheev dev_kfree_skb_any(rxq->skb); 2952562e2f46SYelena Krivosheev 2953c5aff182SThomas Petazzoni if (rxq->descs) 2954c5aff182SThomas Petazzoni dma_free_coherent(pp->dev->dev.parent, 2955c5aff182SThomas Petazzoni rxq->size * MVNETA_DESC_ALIGNED_SIZE, 2956c5aff182SThomas Petazzoni rxq->descs, 2957c5aff182SThomas Petazzoni rxq->descs_phys); 2958c5aff182SThomas Petazzoni 2959c5aff182SThomas Petazzoni rxq->descs = NULL; 2960c5aff182SThomas Petazzoni rxq->last_desc = 0; 2961c5aff182SThomas Petazzoni rxq->next_desc_to_proc = 0; 2962c5aff182SThomas Petazzoni rxq->descs_phys = 0; 2963562e2f46SYelena Krivosheev rxq->first_to_refill = 0; 2964562e2f46SYelena Krivosheev rxq->refill_num = 0; 2965562e2f46SYelena Krivosheev rxq->skb = NULL; 2966562e2f46SYelena Krivosheev rxq->left_size = 0; 2967c5aff182SThomas Petazzoni } 2968c5aff182SThomas Petazzoni 29694a188a63SJisheng Zhang static int mvneta_txq_sw_init(struct mvneta_port *pp, 2970c5aff182SThomas Petazzoni struct mvneta_tx_queue *txq) 2971c5aff182SThomas Petazzoni { 297250bf8cb6SGregory CLEMENT int cpu; 297350bf8cb6SGregory CLEMENT 2974c5aff182SThomas Petazzoni txq->size = pp->tx_ring_size; 2975c5aff182SThomas Petazzoni 29768eef5f97SEzequiel Garcia /* A queue must always have room for at least one skb. 29778eef5f97SEzequiel Garcia * Therefore, stop the queue when the free entries reaches 29788eef5f97SEzequiel Garcia * the maximum number of descriptors per skb. 29798eef5f97SEzequiel Garcia */ 29808eef5f97SEzequiel Garcia txq->tx_stop_threshold = txq->size - MVNETA_MAX_SKB_DESCS; 29818eef5f97SEzequiel Garcia txq->tx_wake_threshold = txq->tx_stop_threshold / 2; 29828eef5f97SEzequiel Garcia 2983c5aff182SThomas Petazzoni /* Allocate memory for TX descriptors */ 2984c5aff182SThomas Petazzoni txq->descs = dma_alloc_coherent(pp->dev->dev.parent, 2985c5aff182SThomas Petazzoni txq->size * MVNETA_DESC_ALIGNED_SIZE, 2986c5aff182SThomas Petazzoni &txq->descs_phys, GFP_KERNEL); 2987f95936ccSMarkus Elfring if (!txq->descs) 2988c5aff182SThomas Petazzoni return -ENOMEM; 2989c5aff182SThomas Petazzoni 2990c5aff182SThomas Petazzoni txq->last_desc = txq->size - 1; 2991c5aff182SThomas Petazzoni 2992d441b688SMarkus Elfring txq->tx_skb = kmalloc_array(txq->size, sizeof(*txq->tx_skb), 2993d441b688SMarkus Elfring GFP_KERNEL); 2994f95936ccSMarkus Elfring if (!txq->tx_skb) { 2995c5aff182SThomas Petazzoni dma_free_coherent(pp->dev->dev.parent, 2996c5aff182SThomas Petazzoni txq->size * MVNETA_DESC_ALIGNED_SIZE, 2997c5aff182SThomas Petazzoni txq->descs, txq->descs_phys); 2998c5aff182SThomas Petazzoni return -ENOMEM; 2999c5aff182SThomas Petazzoni } 30002adb719dSEzequiel Garcia 30012adb719dSEzequiel Garcia /* Allocate DMA buffers for TSO MAC/IP/TCP headers */ 30022adb719dSEzequiel Garcia txq->tso_hdrs = dma_alloc_coherent(pp->dev->dev.parent, 30032adb719dSEzequiel Garcia txq->size * TSO_HEADER_SIZE, 30042adb719dSEzequiel Garcia &txq->tso_hdrs_phys, GFP_KERNEL); 3005f95936ccSMarkus Elfring if (!txq->tso_hdrs) { 30062adb719dSEzequiel Garcia kfree(txq->tx_skb); 30072adb719dSEzequiel Garcia dma_free_coherent(pp->dev->dev.parent, 30082adb719dSEzequiel Garcia txq->size * MVNETA_DESC_ALIGNED_SIZE, 30092adb719dSEzequiel Garcia txq->descs, txq->descs_phys); 30102adb719dSEzequiel Garcia return -ENOMEM; 30112adb719dSEzequiel Garcia } 3012c5aff182SThomas Petazzoni 301350bf8cb6SGregory CLEMENT /* Setup XPS mapping */ 301450bf8cb6SGregory CLEMENT if (txq_number > 1) 301550bf8cb6SGregory CLEMENT cpu = txq->id % num_present_cpus(); 301650bf8cb6SGregory CLEMENT else 301750bf8cb6SGregory CLEMENT cpu = pp->rxq_def % num_present_cpus(); 301850bf8cb6SGregory CLEMENT cpumask_set_cpu(cpu, &txq->affinity_mask); 301950bf8cb6SGregory CLEMENT netif_set_xps_queue(pp->dev, &txq->affinity_mask, txq->id); 302050bf8cb6SGregory CLEMENT 3021c5aff182SThomas Petazzoni return 0; 3022c5aff182SThomas Petazzoni } 3023c5aff182SThomas Petazzoni 30244a188a63SJisheng Zhang static void mvneta_txq_hw_init(struct mvneta_port *pp, 30254a188a63SJisheng Zhang struct mvneta_tx_queue *txq) 30264a188a63SJisheng Zhang { 30274a188a63SJisheng Zhang /* Set maximum bandwidth for enabled TXQs */ 30284a188a63SJisheng Zhang mvreg_write(pp, MVETH_TXQ_TOKEN_CFG_REG(txq->id), 0x03ffffff); 30294a188a63SJisheng Zhang mvreg_write(pp, MVETH_TXQ_TOKEN_COUNT_REG(txq->id), 0x3fffffff); 30304a188a63SJisheng Zhang 30314a188a63SJisheng Zhang /* Set Tx descriptors queue starting address */ 30324a188a63SJisheng Zhang mvreg_write(pp, MVNETA_TXQ_BASE_ADDR_REG(txq->id), txq->descs_phys); 30334a188a63SJisheng Zhang mvreg_write(pp, MVNETA_TXQ_SIZE_REG(txq->id), txq->size); 30344a188a63SJisheng Zhang 30354a188a63SJisheng Zhang mvneta_tx_done_pkts_coal_set(pp, txq, txq->done_pkts_coal); 30364a188a63SJisheng Zhang } 30374a188a63SJisheng Zhang 30384a188a63SJisheng Zhang /* Create and initialize a tx queue */ 30394a188a63SJisheng Zhang static int mvneta_txq_init(struct mvneta_port *pp, 30404a188a63SJisheng Zhang struct mvneta_tx_queue *txq) 30414a188a63SJisheng Zhang { 30424a188a63SJisheng Zhang int ret; 30434a188a63SJisheng Zhang 30444a188a63SJisheng Zhang ret = mvneta_txq_sw_init(pp, txq); 30454a188a63SJisheng Zhang if (ret < 0) 30464a188a63SJisheng Zhang return ret; 30474a188a63SJisheng Zhang 30484a188a63SJisheng Zhang mvneta_txq_hw_init(pp, txq); 30494a188a63SJisheng Zhang 30504a188a63SJisheng Zhang return 0; 30514a188a63SJisheng Zhang } 30524a188a63SJisheng Zhang 3053c5aff182SThomas Petazzoni /* Free allocated resources when mvneta_txq_init() fails to allocate memory*/ 30544a188a63SJisheng Zhang static void mvneta_txq_sw_deinit(struct mvneta_port *pp, 3055c5aff182SThomas Petazzoni struct mvneta_tx_queue *txq) 3056c5aff182SThomas Petazzoni { 3057a29b6235SMarcin Wojtas struct netdev_queue *nq = netdev_get_tx_queue(pp->dev, txq->id); 3058a29b6235SMarcin Wojtas 3059c5aff182SThomas Petazzoni kfree(txq->tx_skb); 3060c5aff182SThomas Petazzoni 30612adb719dSEzequiel Garcia if (txq->tso_hdrs) 30622adb719dSEzequiel Garcia dma_free_coherent(pp->dev->dev.parent, 30632adb719dSEzequiel Garcia txq->size * TSO_HEADER_SIZE, 30642adb719dSEzequiel Garcia txq->tso_hdrs, txq->tso_hdrs_phys); 3065c5aff182SThomas Petazzoni if (txq->descs) 3066c5aff182SThomas Petazzoni dma_free_coherent(pp->dev->dev.parent, 3067c5aff182SThomas Petazzoni txq->size * MVNETA_DESC_ALIGNED_SIZE, 3068c5aff182SThomas Petazzoni txq->descs, txq->descs_phys); 3069c5aff182SThomas Petazzoni 3070a29b6235SMarcin Wojtas netdev_tx_reset_queue(nq); 3071a29b6235SMarcin Wojtas 3072c5aff182SThomas Petazzoni txq->descs = NULL; 3073c5aff182SThomas Petazzoni txq->last_desc = 0; 3074c5aff182SThomas Petazzoni txq->next_desc_to_proc = 0; 3075c5aff182SThomas Petazzoni txq->descs_phys = 0; 30764a188a63SJisheng Zhang } 3077c5aff182SThomas Petazzoni 30784a188a63SJisheng Zhang static void mvneta_txq_hw_deinit(struct mvneta_port *pp, 30794a188a63SJisheng Zhang struct mvneta_tx_queue *txq) 30804a188a63SJisheng Zhang { 3081c5aff182SThomas Petazzoni /* Set minimum bandwidth for disabled TXQs */ 3082c5aff182SThomas Petazzoni mvreg_write(pp, MVETH_TXQ_TOKEN_CFG_REG(txq->id), 0); 3083c5aff182SThomas Petazzoni mvreg_write(pp, MVETH_TXQ_TOKEN_COUNT_REG(txq->id), 0); 3084c5aff182SThomas Petazzoni 3085c5aff182SThomas Petazzoni /* Set Tx descriptors queue starting address and size */ 3086c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_TXQ_BASE_ADDR_REG(txq->id), 0); 3087c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_TXQ_SIZE_REG(txq->id), 0); 3088c5aff182SThomas Petazzoni } 3089c5aff182SThomas Petazzoni 30904a188a63SJisheng Zhang static void mvneta_txq_deinit(struct mvneta_port *pp, 30914a188a63SJisheng Zhang struct mvneta_tx_queue *txq) 30924a188a63SJisheng Zhang { 30934a188a63SJisheng Zhang mvneta_txq_sw_deinit(pp, txq); 30944a188a63SJisheng Zhang mvneta_txq_hw_deinit(pp, txq); 30954a188a63SJisheng Zhang } 30964a188a63SJisheng Zhang 3097c5aff182SThomas Petazzoni /* Cleanup all Tx queues */ 3098c5aff182SThomas Petazzoni static void mvneta_cleanup_txqs(struct mvneta_port *pp) 3099c5aff182SThomas Petazzoni { 3100c5aff182SThomas Petazzoni int queue; 3101c5aff182SThomas Petazzoni 3102c5aff182SThomas Petazzoni for (queue = 0; queue < txq_number; queue++) 3103c5aff182SThomas Petazzoni mvneta_txq_deinit(pp, &pp->txqs[queue]); 3104c5aff182SThomas Petazzoni } 3105c5aff182SThomas Petazzoni 3106c5aff182SThomas Petazzoni /* Cleanup all Rx queues */ 3107c5aff182SThomas Petazzoni static void mvneta_cleanup_rxqs(struct mvneta_port *pp) 3108c5aff182SThomas Petazzoni { 31092dcf75e2SGregory CLEMENT int queue; 31102dcf75e2SGregory CLEMENT 3111ca5902a6SYelena Krivosheev for (queue = 0; queue < rxq_number; queue++) 31122dcf75e2SGregory CLEMENT mvneta_rxq_deinit(pp, &pp->rxqs[queue]); 3113c5aff182SThomas Petazzoni } 3114c5aff182SThomas Petazzoni 3115c5aff182SThomas Petazzoni 3116c5aff182SThomas Petazzoni /* Init all Rx queues */ 3117c5aff182SThomas Petazzoni static int mvneta_setup_rxqs(struct mvneta_port *pp) 3118c5aff182SThomas Petazzoni { 31192dcf75e2SGregory CLEMENT int queue; 31202dcf75e2SGregory CLEMENT 31212dcf75e2SGregory CLEMENT for (queue = 0; queue < rxq_number; queue++) { 31222dcf75e2SGregory CLEMENT int err = mvneta_rxq_init(pp, &pp->rxqs[queue]); 31232dcf75e2SGregory CLEMENT 3124c5aff182SThomas Petazzoni if (err) { 3125c5aff182SThomas Petazzoni netdev_err(pp->dev, "%s: can't create rxq=%d\n", 31262dcf75e2SGregory CLEMENT __func__, queue); 3127c5aff182SThomas Petazzoni mvneta_cleanup_rxqs(pp); 3128c5aff182SThomas Petazzoni return err; 3129c5aff182SThomas Petazzoni } 31302dcf75e2SGregory CLEMENT } 3131c5aff182SThomas Petazzoni 3132c5aff182SThomas Petazzoni return 0; 3133c5aff182SThomas Petazzoni } 3134c5aff182SThomas Petazzoni 3135c5aff182SThomas Petazzoni /* Init all tx queues */ 3136c5aff182SThomas Petazzoni static int mvneta_setup_txqs(struct mvneta_port *pp) 3137c5aff182SThomas Petazzoni { 3138c5aff182SThomas Petazzoni int queue; 3139c5aff182SThomas Petazzoni 3140c5aff182SThomas Petazzoni for (queue = 0; queue < txq_number; queue++) { 3141c5aff182SThomas Petazzoni int err = mvneta_txq_init(pp, &pp->txqs[queue]); 3142c5aff182SThomas Petazzoni if (err) { 3143c5aff182SThomas Petazzoni netdev_err(pp->dev, "%s: can't create txq=%d\n", 3144c5aff182SThomas Petazzoni __func__, queue); 3145c5aff182SThomas Petazzoni mvneta_cleanup_txqs(pp); 3146c5aff182SThomas Petazzoni return err; 3147c5aff182SThomas Petazzoni } 3148c5aff182SThomas Petazzoni } 3149c5aff182SThomas Petazzoni 3150c5aff182SThomas Petazzoni return 0; 3151c5aff182SThomas Petazzoni } 3152c5aff182SThomas Petazzoni 3153031b922bSMarek Behún static int mvneta_comphy_init(struct mvneta_port *pp) 3154031b922bSMarek Behún { 3155031b922bSMarek Behún int ret; 3156031b922bSMarek Behún 3157031b922bSMarek Behún if (!pp->comphy) 3158031b922bSMarek Behún return 0; 3159031b922bSMarek Behún 3160031b922bSMarek Behún ret = phy_set_mode_ext(pp->comphy, PHY_MODE_ETHERNET, 3161031b922bSMarek Behún pp->phy_interface); 3162031b922bSMarek Behún if (ret) 3163031b922bSMarek Behún return ret; 3164031b922bSMarek Behún 3165031b922bSMarek Behún return phy_power_on(pp->comphy); 3166031b922bSMarek Behún } 3167031b922bSMarek Behún 3168c5aff182SThomas Petazzoni static void mvneta_start_dev(struct mvneta_port *pp) 3169c5aff182SThomas Petazzoni { 31706b125d63SGregory CLEMENT int cpu; 317112bb03b4SMaxime Ripard 3172031b922bSMarek Behún WARN_ON(mvneta_comphy_init(pp)); 3173a10c1c81SRussell King 3174c5aff182SThomas Petazzoni mvneta_max_rx_size_set(pp, pp->pkt_size); 3175c5aff182SThomas Petazzoni mvneta_txq_max_tx_size_set(pp, pp->pkt_size); 3176c5aff182SThomas Petazzoni 3177c5aff182SThomas Petazzoni /* start the Rx/Tx activity */ 3178c5aff182SThomas Petazzoni mvneta_port_enable(pp); 3179c5aff182SThomas Petazzoni 31802636ac3cSMarcin Wojtas if (!pp->neta_armada3700) { 3181c5aff182SThomas Petazzoni /* Enable polling on the port */ 3182129219e4SGregory CLEMENT for_each_online_cpu(cpu) { 31832636ac3cSMarcin Wojtas struct mvneta_pcpu_port *port = 31842636ac3cSMarcin Wojtas per_cpu_ptr(pp->ports, cpu); 318512bb03b4SMaxime Ripard 318612bb03b4SMaxime Ripard napi_enable(&port->napi); 318712bb03b4SMaxime Ripard } 31882636ac3cSMarcin Wojtas } else { 31892636ac3cSMarcin Wojtas napi_enable(&pp->napi); 31902636ac3cSMarcin Wojtas } 3191c5aff182SThomas Petazzoni 31922dcf75e2SGregory CLEMENT /* Unmask interrupts. It has to be done from each CPU */ 31936b125d63SGregory CLEMENT on_each_cpu(mvneta_percpu_unmask_interrupt, pp, true); 31946b125d63SGregory CLEMENT 3195898b2970SStas Sergeev mvreg_write(pp, MVNETA_INTR_MISC_MASK, 3196898b2970SStas Sergeev MVNETA_CAUSE_PHY_STATUS_CHANGE | 3197856b2cc5SRussell King MVNETA_CAUSE_LINK_CHANGE); 3198c5aff182SThomas Petazzoni 3199503f9aa9SRussell King phylink_start(pp->phylink); 3200c5aff182SThomas Petazzoni netif_tx_start_all_queues(pp->dev); 3201c5aff182SThomas Petazzoni } 3202c5aff182SThomas Petazzoni 3203c5aff182SThomas Petazzoni static void mvneta_stop_dev(struct mvneta_port *pp) 3204c5aff182SThomas Petazzoni { 320512bb03b4SMaxime Ripard unsigned int cpu; 320612bb03b4SMaxime Ripard 3207503f9aa9SRussell King phylink_stop(pp->phylink); 3208c5aff182SThomas Petazzoni 32092636ac3cSMarcin Wojtas if (!pp->neta_armada3700) { 3210129219e4SGregory CLEMENT for_each_online_cpu(cpu) { 32112636ac3cSMarcin Wojtas struct mvneta_pcpu_port *port = 32122636ac3cSMarcin Wojtas per_cpu_ptr(pp->ports, cpu); 321312bb03b4SMaxime Ripard 321412bb03b4SMaxime Ripard napi_disable(&port->napi); 321512bb03b4SMaxime Ripard } 32162636ac3cSMarcin Wojtas } else { 32172636ac3cSMarcin Wojtas napi_disable(&pp->napi); 32182636ac3cSMarcin Wojtas } 3219c5aff182SThomas Petazzoni 3220c5aff182SThomas Petazzoni netif_carrier_off(pp->dev); 3221c5aff182SThomas Petazzoni 3222c5aff182SThomas Petazzoni mvneta_port_down(pp); 3223c5aff182SThomas Petazzoni netif_tx_stop_all_queues(pp->dev); 3224c5aff182SThomas Petazzoni 3225c5aff182SThomas Petazzoni /* Stop the port activity */ 3226c5aff182SThomas Petazzoni mvneta_port_disable(pp); 3227c5aff182SThomas Petazzoni 3228c5aff182SThomas Petazzoni /* Clear all ethernet port interrupts */ 3229db488c10SGregory CLEMENT on_each_cpu(mvneta_percpu_clear_intr_cause, pp, true); 3230c5aff182SThomas Petazzoni 3231c5aff182SThomas Petazzoni /* Mask all ethernet port interrupts */ 3232db488c10SGregory CLEMENT on_each_cpu(mvneta_percpu_mask_interrupt, pp, true); 3233c5aff182SThomas Petazzoni 3234c5aff182SThomas Petazzoni mvneta_tx_reset(pp); 3235c5aff182SThomas Petazzoni mvneta_rx_reset(pp); 3236a10c1c81SRussell King 3237a10c1c81SRussell King WARN_ON(phy_power_off(pp->comphy)); 3238c5aff182SThomas Petazzoni } 3239c5aff182SThomas Petazzoni 3240db5dd0dbSMarcin Wojtas static void mvneta_percpu_enable(void *arg) 3241db5dd0dbSMarcin Wojtas { 3242db5dd0dbSMarcin Wojtas struct mvneta_port *pp = arg; 3243db5dd0dbSMarcin Wojtas 3244db5dd0dbSMarcin Wojtas enable_percpu_irq(pp->dev->irq, IRQ_TYPE_NONE); 3245db5dd0dbSMarcin Wojtas } 3246db5dd0dbSMarcin Wojtas 3247db5dd0dbSMarcin Wojtas static void mvneta_percpu_disable(void *arg) 3248db5dd0dbSMarcin Wojtas { 3249db5dd0dbSMarcin Wojtas struct mvneta_port *pp = arg; 3250db5dd0dbSMarcin Wojtas 3251db5dd0dbSMarcin Wojtas disable_percpu_irq(pp->dev->irq); 3252db5dd0dbSMarcin Wojtas } 3253db5dd0dbSMarcin Wojtas 3254c5aff182SThomas Petazzoni /* Change the device mtu */ 3255c5aff182SThomas Petazzoni static int mvneta_change_mtu(struct net_device *dev, int mtu) 3256c5aff182SThomas Petazzoni { 3257c5aff182SThomas Petazzoni struct mvneta_port *pp = netdev_priv(dev); 3258c5aff182SThomas Petazzoni int ret; 3259c5aff182SThomas Petazzoni 32605777987eSJarod Wilson if (!IS_ALIGNED(MVNETA_RX_PKT_SIZE(mtu), 8)) { 32615777987eSJarod Wilson netdev_info(dev, "Illegal MTU value %d, rounding to %d\n", 32625777987eSJarod Wilson mtu, ALIGN(MVNETA_RX_PKT_SIZE(mtu), 8)); 32635777987eSJarod Wilson mtu = ALIGN(MVNETA_RX_PKT_SIZE(mtu), 8); 32645777987eSJarod Wilson } 3265c5aff182SThomas Petazzoni 3266c5aff182SThomas Petazzoni dev->mtu = mtu; 3267c5aff182SThomas Petazzoni 3268b65657fcSSimon Guinot if (!netif_running(dev)) { 3269dc35a10fSMarcin Wojtas if (pp->bm_priv) 3270dc35a10fSMarcin Wojtas mvneta_bm_update_mtu(pp, mtu); 3271dc35a10fSMarcin Wojtas 3272b65657fcSSimon Guinot netdev_update_features(dev); 3273c5aff182SThomas Petazzoni return 0; 3274b65657fcSSimon Guinot } 3275c5aff182SThomas Petazzoni 32766a20c175SThomas Petazzoni /* The interface is running, so we have to force a 3277a92dbd96SEzequiel Garcia * reallocation of the queues 3278c5aff182SThomas Petazzoni */ 3279c5aff182SThomas Petazzoni mvneta_stop_dev(pp); 3280db5dd0dbSMarcin Wojtas on_each_cpu(mvneta_percpu_disable, pp, true); 3281c5aff182SThomas Petazzoni 3282c5aff182SThomas Petazzoni mvneta_cleanup_txqs(pp); 3283c5aff182SThomas Petazzoni mvneta_cleanup_rxqs(pp); 3284c5aff182SThomas Petazzoni 3285dc35a10fSMarcin Wojtas if (pp->bm_priv) 3286dc35a10fSMarcin Wojtas mvneta_bm_update_mtu(pp, mtu); 3287dc35a10fSMarcin Wojtas 3288a92dbd96SEzequiel Garcia pp->pkt_size = MVNETA_RX_PKT_SIZE(dev->mtu); 3289c5aff182SThomas Petazzoni 3290c5aff182SThomas Petazzoni ret = mvneta_setup_rxqs(pp); 3291c5aff182SThomas Petazzoni if (ret) { 3292a92dbd96SEzequiel Garcia netdev_err(dev, "unable to setup rxqs after MTU change\n"); 3293c5aff182SThomas Petazzoni return ret; 3294c5aff182SThomas Petazzoni } 3295c5aff182SThomas Petazzoni 3296a92dbd96SEzequiel Garcia ret = mvneta_setup_txqs(pp); 3297a92dbd96SEzequiel Garcia if (ret) { 3298a92dbd96SEzequiel Garcia netdev_err(dev, "unable to setup txqs after MTU change\n"); 3299a92dbd96SEzequiel Garcia return ret; 3300a92dbd96SEzequiel Garcia } 3301c5aff182SThomas Petazzoni 3302db5dd0dbSMarcin Wojtas on_each_cpu(mvneta_percpu_enable, pp, true); 3303c5aff182SThomas Petazzoni mvneta_start_dev(pp); 3304c5aff182SThomas Petazzoni 3305b65657fcSSimon Guinot netdev_update_features(dev); 3306b65657fcSSimon Guinot 3307c5aff182SThomas Petazzoni return 0; 3308c5aff182SThomas Petazzoni } 3309c5aff182SThomas Petazzoni 3310b65657fcSSimon Guinot static netdev_features_t mvneta_fix_features(struct net_device *dev, 3311b65657fcSSimon Guinot netdev_features_t features) 3312b65657fcSSimon Guinot { 3313b65657fcSSimon Guinot struct mvneta_port *pp = netdev_priv(dev); 3314b65657fcSSimon Guinot 3315b65657fcSSimon Guinot if (pp->tx_csum_limit && dev->mtu > pp->tx_csum_limit) { 3316b65657fcSSimon Guinot features &= ~(NETIF_F_IP_CSUM | NETIF_F_TSO); 3317b65657fcSSimon Guinot netdev_info(dev, 3318b65657fcSSimon Guinot "Disable IP checksum for MTU greater than %dB\n", 3319b65657fcSSimon Guinot pp->tx_csum_limit); 3320b65657fcSSimon Guinot } 3321b65657fcSSimon Guinot 3322b65657fcSSimon Guinot return features; 3323b65657fcSSimon Guinot } 3324b65657fcSSimon Guinot 33258cc3e439SThomas Petazzoni /* Get mac address */ 33268cc3e439SThomas Petazzoni static void mvneta_get_mac_addr(struct mvneta_port *pp, unsigned char *addr) 33278cc3e439SThomas Petazzoni { 33288cc3e439SThomas Petazzoni u32 mac_addr_l, mac_addr_h; 33298cc3e439SThomas Petazzoni 33308cc3e439SThomas Petazzoni mac_addr_l = mvreg_read(pp, MVNETA_MAC_ADDR_LOW); 33318cc3e439SThomas Petazzoni mac_addr_h = mvreg_read(pp, MVNETA_MAC_ADDR_HIGH); 33328cc3e439SThomas Petazzoni addr[0] = (mac_addr_h >> 24) & 0xFF; 33338cc3e439SThomas Petazzoni addr[1] = (mac_addr_h >> 16) & 0xFF; 33348cc3e439SThomas Petazzoni addr[2] = (mac_addr_h >> 8) & 0xFF; 33358cc3e439SThomas Petazzoni addr[3] = mac_addr_h & 0xFF; 33368cc3e439SThomas Petazzoni addr[4] = (mac_addr_l >> 8) & 0xFF; 33378cc3e439SThomas Petazzoni addr[5] = mac_addr_l & 0xFF; 33388cc3e439SThomas Petazzoni } 33398cc3e439SThomas Petazzoni 3340c5aff182SThomas Petazzoni /* Handle setting mac address */ 3341c5aff182SThomas Petazzoni static int mvneta_set_mac_addr(struct net_device *dev, void *addr) 3342c5aff182SThomas Petazzoni { 3343c5aff182SThomas Petazzoni struct mvneta_port *pp = netdev_priv(dev); 3344e68de360SEzequiel Garcia struct sockaddr *sockaddr = addr; 3345e68de360SEzequiel Garcia int ret; 3346c5aff182SThomas Petazzoni 3347e68de360SEzequiel Garcia ret = eth_prepare_mac_addr_change(dev, addr); 3348e68de360SEzequiel Garcia if (ret < 0) 3349e68de360SEzequiel Garcia return ret; 3350c5aff182SThomas Petazzoni /* Remove previous address table entry */ 3351c5aff182SThomas Petazzoni mvneta_mac_addr_set(pp, dev->dev_addr, -1); 3352c5aff182SThomas Petazzoni 3353c5aff182SThomas Petazzoni /* Set new addr in hw */ 335490b74c01SGregory CLEMENT mvneta_mac_addr_set(pp, sockaddr->sa_data, pp->rxq_def); 3355c5aff182SThomas Petazzoni 3356e68de360SEzequiel Garcia eth_commit_mac_addr_change(dev, addr); 3357c5aff182SThomas Petazzoni return 0; 3358c5aff182SThomas Petazzoni } 3359c5aff182SThomas Petazzoni 336044cc27e4SIoana Ciornei static void mvneta_validate(struct phylink_config *config, 336144cc27e4SIoana Ciornei unsigned long *supported, 3362503f9aa9SRussell King struct phylink_link_state *state) 3363503f9aa9SRussell King { 336444cc27e4SIoana Ciornei struct net_device *ndev = to_net_dev(config->dev); 3365a10c1c81SRussell King struct mvneta_port *pp = netdev_priv(ndev); 3366503f9aa9SRussell King __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, }; 3367503f9aa9SRussell King 336822f4bf8aSRussell King /* We only support QSGMII, SGMII, 802.3z and RGMII modes */ 3369503f9aa9SRussell King if (state->interface != PHY_INTERFACE_MODE_NA && 3370503f9aa9SRussell King state->interface != PHY_INTERFACE_MODE_QSGMII && 3371503f9aa9SRussell King state->interface != PHY_INTERFACE_MODE_SGMII && 337222f4bf8aSRussell King !phy_interface_mode_is_8023z(state->interface) && 3373503f9aa9SRussell King !phy_interface_mode_is_rgmii(state->interface)) { 3374503f9aa9SRussell King bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS); 3375503f9aa9SRussell King return; 3376503f9aa9SRussell King } 3377503f9aa9SRussell King 3378503f9aa9SRussell King /* Allow all the expected bits */ 3379503f9aa9SRussell King phylink_set(mask, Autoneg); 3380503f9aa9SRussell King phylink_set_port_modes(mask); 3381503f9aa9SRussell King 33824932a918SRussell King /* Asymmetric pause is unsupported */ 33834932a918SRussell King phylink_set(mask, Pause); 3384da58a931SMaxime Chevallier 338583e65df6SMaxime Chevallier /* Half-duplex at speeds higher than 100Mbit is unsupported */ 3386a10c1c81SRussell King if (pp->comphy || state->interface != PHY_INTERFACE_MODE_2500BASEX) { 3387503f9aa9SRussell King phylink_set(mask, 1000baseT_Full); 3388503f9aa9SRussell King phylink_set(mask, 1000baseX_Full); 3389a10c1c81SRussell King } 3390a10c1c81SRussell King if (pp->comphy || state->interface == PHY_INTERFACE_MODE_2500BASEX) { 3391eda3d1b0SMaxime Chevallier phylink_set(mask, 2500baseT_Full); 3392a10c1c81SRussell King phylink_set(mask, 2500baseX_Full); 3393a10c1c81SRussell King } 339422f4bf8aSRussell King 339522f4bf8aSRussell King if (!phy_interface_mode_is_8023z(state->interface)) { 339622f4bf8aSRussell King /* 10M and 100M are only supported in non-802.3z mode */ 3397503f9aa9SRussell King phylink_set(mask, 10baseT_Half); 3398503f9aa9SRussell King phylink_set(mask, 10baseT_Full); 3399503f9aa9SRussell King phylink_set(mask, 100baseT_Half); 3400503f9aa9SRussell King phylink_set(mask, 100baseT_Full); 340122f4bf8aSRussell King } 3402503f9aa9SRussell King 3403503f9aa9SRussell King bitmap_and(supported, supported, mask, 3404503f9aa9SRussell King __ETHTOOL_LINK_MODE_MASK_NBITS); 3405503f9aa9SRussell King bitmap_and(state->advertising, state->advertising, mask, 3406503f9aa9SRussell King __ETHTOOL_LINK_MODE_MASK_NBITS); 3407a10c1c81SRussell King 3408a10c1c81SRussell King /* We can only operate at 2500BaseX or 1000BaseX. If requested 3409a10c1c81SRussell King * to advertise both, only report advertising at 2500BaseX. 3410a10c1c81SRussell King */ 3411a10c1c81SRussell King phylink_helper_basex_speed(state); 3412503f9aa9SRussell King } 3413503f9aa9SRussell King 341444cc27e4SIoana Ciornei static int mvneta_mac_link_state(struct phylink_config *config, 3415503f9aa9SRussell King struct phylink_link_state *state) 3416c5aff182SThomas Petazzoni { 341744cc27e4SIoana Ciornei struct net_device *ndev = to_net_dev(config->dev); 3418c5aff182SThomas Petazzoni struct mvneta_port *pp = netdev_priv(ndev); 3419503f9aa9SRussell King u32 gmac_stat; 3420c5aff182SThomas Petazzoni 3421503f9aa9SRussell King gmac_stat = mvreg_read(pp, MVNETA_GMAC_STATUS); 3422503f9aa9SRussell King 3423503f9aa9SRussell King if (gmac_stat & MVNETA_GMAC_SPEED_1000) 3424a10c1c81SRussell King state->speed = 3425a10c1c81SRussell King state->interface == PHY_INTERFACE_MODE_2500BASEX ? 3426a10c1c81SRussell King SPEED_2500 : SPEED_1000; 3427503f9aa9SRussell King else if (gmac_stat & MVNETA_GMAC_SPEED_100) 3428503f9aa9SRussell King state->speed = SPEED_100; 3429503f9aa9SRussell King else 3430503f9aa9SRussell King state->speed = SPEED_10; 3431503f9aa9SRussell King 3432503f9aa9SRussell King state->an_complete = !!(gmac_stat & MVNETA_GMAC_AN_COMPLETE); 3433503f9aa9SRussell King state->link = !!(gmac_stat & MVNETA_GMAC_LINK_UP); 3434503f9aa9SRussell King state->duplex = !!(gmac_stat & MVNETA_GMAC_FULL_DUPLEX); 3435503f9aa9SRussell King 3436503f9aa9SRussell King state->pause = 0; 34374932a918SRussell King if (gmac_stat & MVNETA_GMAC_RX_FLOW_CTRL_ENABLE) 34384932a918SRussell King state->pause |= MLO_PAUSE_RX; 34394932a918SRussell King if (gmac_stat & MVNETA_GMAC_TX_FLOW_CTRL_ENABLE) 34404932a918SRussell King state->pause |= MLO_PAUSE_TX; 3441503f9aa9SRussell King 3442503f9aa9SRussell King return 1; 3443503f9aa9SRussell King } 3444503f9aa9SRussell King 344544cc27e4SIoana Ciornei static void mvneta_mac_an_restart(struct phylink_config *config) 344622f4bf8aSRussell King { 344744cc27e4SIoana Ciornei struct net_device *ndev = to_net_dev(config->dev); 344822f4bf8aSRussell King struct mvneta_port *pp = netdev_priv(ndev); 344922f4bf8aSRussell King u32 gmac_an = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG); 345022f4bf8aSRussell King 345122f4bf8aSRussell King mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, 345222f4bf8aSRussell King gmac_an | MVNETA_GMAC_INBAND_RESTART_AN); 345322f4bf8aSRussell King mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, 345422f4bf8aSRussell King gmac_an & ~MVNETA_GMAC_INBAND_RESTART_AN); 345522f4bf8aSRussell King } 345622f4bf8aSRussell King 345744cc27e4SIoana Ciornei static void mvneta_mac_config(struct phylink_config *config, unsigned int mode, 3458503f9aa9SRussell King const struct phylink_link_state *state) 3459503f9aa9SRussell King { 346044cc27e4SIoana Ciornei struct net_device *ndev = to_net_dev(config->dev); 3461503f9aa9SRussell King struct mvneta_port *pp = netdev_priv(ndev); 346222f4bf8aSRussell King u32 new_ctrl0, gmac_ctrl0 = mvreg_read(pp, MVNETA_GMAC_CTRL_0); 3463503f9aa9SRussell King u32 new_ctrl2, gmac_ctrl2 = mvreg_read(pp, MVNETA_GMAC_CTRL_2); 3464da58a931SMaxime Chevallier u32 new_ctrl4, gmac_ctrl4 = mvreg_read(pp, MVNETA_GMAC_CTRL_4); 3465503f9aa9SRussell King u32 new_clk, gmac_clk = mvreg_read(pp, MVNETA_GMAC_CLOCK_DIVIDER); 3466503f9aa9SRussell King u32 new_an, gmac_an = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG); 3467503f9aa9SRussell King 346822f4bf8aSRussell King new_ctrl0 = gmac_ctrl0 & ~MVNETA_GMAC0_PORT_1000BASE_X; 346932699954SRussell King new_ctrl2 = gmac_ctrl2 & ~(MVNETA_GMAC2_INBAND_AN_ENABLE | 347032699954SRussell King MVNETA_GMAC2_PORT_RESET); 3471da58a931SMaxime Chevallier new_ctrl4 = gmac_ctrl4 & ~(MVNETA_GMAC4_SHORT_PREAMBLE_ENABLE); 3472503f9aa9SRussell King new_clk = gmac_clk & ~MVNETA_GMAC_1MS_CLOCK_ENABLE; 3473503f9aa9SRussell King new_an = gmac_an & ~(MVNETA_GMAC_INBAND_AN_ENABLE | 3474503f9aa9SRussell King MVNETA_GMAC_INBAND_RESTART_AN | 3475503f9aa9SRussell King MVNETA_GMAC_CONFIG_MII_SPEED | 3476c5aff182SThomas Petazzoni MVNETA_GMAC_CONFIG_GMII_SPEED | 3477503f9aa9SRussell King MVNETA_GMAC_AN_SPEED_EN | 347822f4bf8aSRussell King MVNETA_GMAC_ADVERT_SYM_FLOW_CTRL | 347922f4bf8aSRussell King MVNETA_GMAC_CONFIG_FLOW_CTRL | 3480503f9aa9SRussell King MVNETA_GMAC_AN_FLOW_CTRL_EN | 3481503f9aa9SRussell King MVNETA_GMAC_CONFIG_FULL_DUPLEX | 3482503f9aa9SRussell King MVNETA_GMAC_AN_DUPLEX_EN); 3483c5aff182SThomas Petazzoni 348432699954SRussell King /* Even though it might look weird, when we're configured in 348532699954SRussell King * SGMII or QSGMII mode, the RGMII bit needs to be set. 348632699954SRussell King */ 348732699954SRussell King new_ctrl2 |= MVNETA_GMAC2_PORT_RGMII; 348832699954SRussell King 348932699954SRussell King if (state->interface == PHY_INTERFACE_MODE_QSGMII || 349022f4bf8aSRussell King state->interface == PHY_INTERFACE_MODE_SGMII || 349122f4bf8aSRussell King phy_interface_mode_is_8023z(state->interface)) 349232699954SRussell King new_ctrl2 |= MVNETA_GMAC2_PCS_ENABLE; 349332699954SRussell King 34944932a918SRussell King if (phylink_test(state->advertising, Pause)) 34954932a918SRussell King new_an |= MVNETA_GMAC_ADVERT_SYM_FLOW_CTRL; 34964932a918SRussell King if (state->pause & MLO_PAUSE_TXRX_MASK) 34974932a918SRussell King new_an |= MVNETA_GMAC_CONFIG_FLOW_CTRL; 34984932a918SRussell King 3499503f9aa9SRussell King if (!phylink_autoneg_inband(mode)) { 3500503f9aa9SRussell King /* Phy or fixed speed */ 3501503f9aa9SRussell King if (state->duplex) 3502503f9aa9SRussell King new_an |= MVNETA_GMAC_CONFIG_FULL_DUPLEX; 3503c5aff182SThomas Petazzoni 3504da58a931SMaxime Chevallier if (state->speed == SPEED_1000 || state->speed == SPEED_2500) 3505503f9aa9SRussell King new_an |= MVNETA_GMAC_CONFIG_GMII_SPEED; 3506503f9aa9SRussell King else if (state->speed == SPEED_100) 3507503f9aa9SRussell King new_an |= MVNETA_GMAC_CONFIG_MII_SPEED; 350822f4bf8aSRussell King } else if (state->interface == PHY_INTERFACE_MODE_SGMII) { 3509503f9aa9SRussell King /* SGMII mode receives the state from the PHY */ 3510503f9aa9SRussell King new_ctrl2 |= MVNETA_GMAC2_INBAND_AN_ENABLE; 3511503f9aa9SRussell King new_clk |= MVNETA_GMAC_1MS_CLOCK_ENABLE; 3512503f9aa9SRussell King new_an = (new_an & ~(MVNETA_GMAC_FORCE_LINK_DOWN | 3513503f9aa9SRussell King MVNETA_GMAC_FORCE_LINK_PASS)) | 3514503f9aa9SRussell King MVNETA_GMAC_INBAND_AN_ENABLE | 3515503f9aa9SRussell King MVNETA_GMAC_AN_SPEED_EN | 3516503f9aa9SRussell King MVNETA_GMAC_AN_DUPLEX_EN; 351722f4bf8aSRussell King } else { 351822f4bf8aSRussell King /* 802.3z negotiation - only 1000base-X */ 351922f4bf8aSRussell King new_ctrl0 |= MVNETA_GMAC0_PORT_1000BASE_X; 352022f4bf8aSRussell King new_clk |= MVNETA_GMAC_1MS_CLOCK_ENABLE; 352122f4bf8aSRussell King new_an = (new_an & ~(MVNETA_GMAC_FORCE_LINK_DOWN | 352222f4bf8aSRussell King MVNETA_GMAC_FORCE_LINK_PASS)) | 352322f4bf8aSRussell King MVNETA_GMAC_INBAND_AN_ENABLE | 352422f4bf8aSRussell King MVNETA_GMAC_CONFIG_GMII_SPEED | 352522f4bf8aSRussell King /* The MAC only supports FD mode */ 352622f4bf8aSRussell King MVNETA_GMAC_CONFIG_FULL_DUPLEX; 35274932a918SRussell King 35284932a918SRussell King if (state->pause & MLO_PAUSE_AN && state->an_enabled) 35294932a918SRussell King new_an |= MVNETA_GMAC_AN_FLOW_CTRL_EN; 3530c5aff182SThomas Petazzoni } 3531c5aff182SThomas Petazzoni 3532503f9aa9SRussell King /* Armada 370 documentation says we can only change the port mode 3533503f9aa9SRussell King * and in-band enable when the link is down, so force it down 3534503f9aa9SRussell King * while making these changes. We also do this for GMAC_CTRL2 */ 353522f4bf8aSRussell King if ((new_ctrl0 ^ gmac_ctrl0) & MVNETA_GMAC0_PORT_1000BASE_X || 353622f4bf8aSRussell King (new_ctrl2 ^ gmac_ctrl2) & MVNETA_GMAC2_INBAND_AN_ENABLE || 3537503f9aa9SRussell King (new_an ^ gmac_an) & MVNETA_GMAC_INBAND_AN_ENABLE) { 3538503f9aa9SRussell King mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, 3539503f9aa9SRussell King (gmac_an & ~MVNETA_GMAC_FORCE_LINK_PASS) | 3540503f9aa9SRussell King MVNETA_GMAC_FORCE_LINK_DOWN); 3541503f9aa9SRussell King } 3542503f9aa9SRussell King 3543a10c1c81SRussell King 3544da58a931SMaxime Chevallier /* When at 2.5G, the link partner can send frames with shortened 3545da58a931SMaxime Chevallier * preambles. 3546da58a931SMaxime Chevallier */ 3547da58a931SMaxime Chevallier if (state->speed == SPEED_2500) 3548da58a931SMaxime Chevallier new_ctrl4 |= MVNETA_GMAC4_SHORT_PREAMBLE_ENABLE; 3549da58a931SMaxime Chevallier 3550031b922bSMarek Behún if (pp->comphy && pp->phy_interface != state->interface && 3551a10c1c81SRussell King (state->interface == PHY_INTERFACE_MODE_SGMII || 3552a10c1c81SRussell King state->interface == PHY_INTERFACE_MODE_1000BASEX || 3553031b922bSMarek Behún state->interface == PHY_INTERFACE_MODE_2500BASEX)) { 3554031b922bSMarek Behún pp->phy_interface = state->interface; 3555031b922bSMarek Behún 3556031b922bSMarek Behún WARN_ON(phy_power_off(pp->comphy)); 3557031b922bSMarek Behún WARN_ON(mvneta_comphy_init(pp)); 3558031b922bSMarek Behún } 3559a10c1c81SRussell King 356022f4bf8aSRussell King if (new_ctrl0 != gmac_ctrl0) 356122f4bf8aSRussell King mvreg_write(pp, MVNETA_GMAC_CTRL_0, new_ctrl0); 3562503f9aa9SRussell King if (new_ctrl2 != gmac_ctrl2) 3563503f9aa9SRussell King mvreg_write(pp, MVNETA_GMAC_CTRL_2, new_ctrl2); 3564da58a931SMaxime Chevallier if (new_ctrl4 != gmac_ctrl4) 3565da58a931SMaxime Chevallier mvreg_write(pp, MVNETA_GMAC_CTRL_4, new_ctrl4); 3566503f9aa9SRussell King if (new_clk != gmac_clk) 3567503f9aa9SRussell King mvreg_write(pp, MVNETA_GMAC_CLOCK_DIVIDER, new_clk); 3568503f9aa9SRussell King if (new_an != gmac_an) 3569503f9aa9SRussell King mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, new_an); 357032699954SRussell King 357132699954SRussell King if (gmac_ctrl2 & MVNETA_GMAC2_PORT_RESET) { 357232699954SRussell King while ((mvreg_read(pp, MVNETA_GMAC_CTRL_2) & 357332699954SRussell King MVNETA_GMAC2_PORT_RESET) != 0) 357432699954SRussell King continue; 357532699954SRussell King } 3576503f9aa9SRussell King } 3577503f9aa9SRussell King 35786d81f451SRussell King static void mvneta_set_eee(struct mvneta_port *pp, bool enable) 35796d81f451SRussell King { 35806d81f451SRussell King u32 lpi_ctl1; 35816d81f451SRussell King 35826d81f451SRussell King lpi_ctl1 = mvreg_read(pp, MVNETA_LPI_CTRL_1); 35836d81f451SRussell King if (enable) 35846d81f451SRussell King lpi_ctl1 |= MVNETA_LPI_REQUEST_ENABLE; 35856d81f451SRussell King else 35866d81f451SRussell King lpi_ctl1 &= ~MVNETA_LPI_REQUEST_ENABLE; 35876d81f451SRussell King mvreg_write(pp, MVNETA_LPI_CTRL_1, lpi_ctl1); 35886d81f451SRussell King } 35896d81f451SRussell King 359044cc27e4SIoana Ciornei static void mvneta_mac_link_down(struct phylink_config *config, 359144cc27e4SIoana Ciornei unsigned int mode, phy_interface_t interface) 3592fc548b99SRussell King { 359344cc27e4SIoana Ciornei struct net_device *ndev = to_net_dev(config->dev); 3594fc548b99SRussell King struct mvneta_port *pp = netdev_priv(ndev); 3595fc548b99SRussell King u32 val; 3596fc548b99SRussell King 3597503f9aa9SRussell King mvneta_port_down(pp); 3598503f9aa9SRussell King 3599503f9aa9SRussell King if (!phylink_autoneg_inband(mode)) { 3600fc548b99SRussell King val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG); 3601fc548b99SRussell King val &= ~MVNETA_GMAC_FORCE_LINK_PASS; 3602fc548b99SRussell King val |= MVNETA_GMAC_FORCE_LINK_DOWN; 3603fc548b99SRussell King mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val); 3604fc548b99SRussell King } 36056d81f451SRussell King 36066d81f451SRussell King pp->eee_active = false; 36076d81f451SRussell King mvneta_set_eee(pp, false); 3608fc548b99SRussell King } 3609fc548b99SRussell King 361044cc27e4SIoana Ciornei static void mvneta_mac_link_up(struct phylink_config *config, unsigned int mode, 3611c6ab3008SFlorian Fainelli phy_interface_t interface, 3612503f9aa9SRussell King struct phy_device *phy) 3613fc548b99SRussell King { 361444cc27e4SIoana Ciornei struct net_device *ndev = to_net_dev(config->dev); 3615fc548b99SRussell King struct mvneta_port *pp = netdev_priv(ndev); 3616fc548b99SRussell King u32 val; 3617fc548b99SRussell King 3618503f9aa9SRussell King if (!phylink_autoneg_inband(mode)) { 3619fc548b99SRussell King val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG); 3620fc548b99SRussell King val &= ~MVNETA_GMAC_FORCE_LINK_DOWN; 3621fc548b99SRussell King val |= MVNETA_GMAC_FORCE_LINK_PASS; 3622fc548b99SRussell King mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val); 3623fc548b99SRussell King } 3624fc548b99SRussell King 3625fc548b99SRussell King mvneta_port_up(pp); 36266d81f451SRussell King 36276d81f451SRussell King if (phy && pp->eee_enabled) { 36286d81f451SRussell King pp->eee_active = phy_init_eee(phy, 0) >= 0; 36296d81f451SRussell King mvneta_set_eee(pp, pp->eee_active && pp->tx_lpi_enabled); 36306d81f451SRussell King } 3631fc548b99SRussell King } 3632fc548b99SRussell King 3633503f9aa9SRussell King static const struct phylink_mac_ops mvneta_phylink_ops = { 3634503f9aa9SRussell King .validate = mvneta_validate, 3635503f9aa9SRussell King .mac_link_state = mvneta_mac_link_state, 363622f4bf8aSRussell King .mac_an_restart = mvneta_mac_an_restart, 3637503f9aa9SRussell King .mac_config = mvneta_mac_config, 3638503f9aa9SRussell King .mac_link_down = mvneta_mac_link_down, 3639503f9aa9SRussell King .mac_link_up = mvneta_mac_link_up, 3640503f9aa9SRussell King }; 3641c5aff182SThomas Petazzoni 3642c5aff182SThomas Petazzoni static int mvneta_mdio_probe(struct mvneta_port *pp) 3643c5aff182SThomas Petazzoni { 364482960fffSJisheng Zhang struct ethtool_wolinfo wol = { .cmd = ETHTOOL_GWOL }; 3645503f9aa9SRussell King int err = phylink_of_phy_connect(pp->phylink, pp->dn, 0); 3646c5aff182SThomas Petazzoni 3647503f9aa9SRussell King if (err) 3648503f9aa9SRussell King netdev_err(pp->dev, "could not attach PHY: %d\n", err); 3649c5aff182SThomas Petazzoni 3650503f9aa9SRussell King phylink_ethtool_get_wol(pp->phylink, &wol); 365182960fffSJisheng Zhang device_set_wakeup_capable(&pp->dev->dev, !!wol.supported); 365282960fffSJisheng Zhang 3653503f9aa9SRussell King return err; 3654c5aff182SThomas Petazzoni } 3655c5aff182SThomas Petazzoni 3656c5aff182SThomas Petazzoni static void mvneta_mdio_remove(struct mvneta_port *pp) 3657c5aff182SThomas Petazzoni { 3658503f9aa9SRussell King phylink_disconnect_phy(pp->phylink); 3659c5aff182SThomas Petazzoni } 3660c5aff182SThomas Petazzoni 3661120cfa50SGregory CLEMENT /* Electing a CPU must be done in an atomic way: it should be done 3662120cfa50SGregory CLEMENT * after or before the removal/insertion of a CPU and this function is 3663120cfa50SGregory CLEMENT * not reentrant. 3664120cfa50SGregory CLEMENT */ 3665f8642885SMaxime Ripard static void mvneta_percpu_elect(struct mvneta_port *pp) 3666f8642885SMaxime Ripard { 3667cad5d847SGregory CLEMENT int elected_cpu = 0, max_cpu, cpu, i = 0; 3668f8642885SMaxime Ripard 3669cad5d847SGregory CLEMENT /* Use the cpu associated to the rxq when it is online, in all 3670cad5d847SGregory CLEMENT * the other cases, use the cpu 0 which can't be offline. 3671cad5d847SGregory CLEMENT */ 3672cad5d847SGregory CLEMENT if (cpu_online(pp->rxq_def)) 3673cad5d847SGregory CLEMENT elected_cpu = pp->rxq_def; 3674cad5d847SGregory CLEMENT 36752dcf75e2SGregory CLEMENT max_cpu = num_present_cpus(); 3676f8642885SMaxime Ripard 3677f8642885SMaxime Ripard for_each_online_cpu(cpu) { 36782dcf75e2SGregory CLEMENT int rxq_map = 0, txq_map = 0; 36792dcf75e2SGregory CLEMENT int rxq; 36802dcf75e2SGregory CLEMENT 36812dcf75e2SGregory CLEMENT for (rxq = 0; rxq < rxq_number; rxq++) 36822dcf75e2SGregory CLEMENT if ((rxq % max_cpu) == cpu) 36832dcf75e2SGregory CLEMENT rxq_map |= MVNETA_CPU_RXQ_ACCESS(rxq); 36842dcf75e2SGregory CLEMENT 3685cad5d847SGregory CLEMENT if (cpu == elected_cpu) 368650bf8cb6SGregory CLEMENT /* Map the default receive queue queue to the 368750bf8cb6SGregory CLEMENT * elected CPU 3688f8642885SMaxime Ripard */ 36892dcf75e2SGregory CLEMENT rxq_map |= MVNETA_CPU_RXQ_ACCESS(pp->rxq_def); 369050bf8cb6SGregory CLEMENT 369150bf8cb6SGregory CLEMENT /* We update the TX queue map only if we have one 369250bf8cb6SGregory CLEMENT * queue. In this case we associate the TX queue to 369350bf8cb6SGregory CLEMENT * the CPU bound to the default RX queue 369450bf8cb6SGregory CLEMENT */ 369550bf8cb6SGregory CLEMENT if (txq_number == 1) 3696cad5d847SGregory CLEMENT txq_map = (cpu == elected_cpu) ? 369750bf8cb6SGregory CLEMENT MVNETA_CPU_TXQ_ACCESS(1) : 0; 369850bf8cb6SGregory CLEMENT else 369950bf8cb6SGregory CLEMENT txq_map = mvreg_read(pp, MVNETA_CPU_MAP(cpu)) & 370050bf8cb6SGregory CLEMENT MVNETA_CPU_TXQ_ACCESS_ALL_MASK; 370150bf8cb6SGregory CLEMENT 37022dcf75e2SGregory CLEMENT mvreg_write(pp, MVNETA_CPU_MAP(cpu), rxq_map | txq_map); 37032dcf75e2SGregory CLEMENT 37042dcf75e2SGregory CLEMENT /* Update the interrupt mask on each CPU according the 37052dcf75e2SGregory CLEMENT * new mapping 37062dcf75e2SGregory CLEMENT */ 37072dcf75e2SGregory CLEMENT smp_call_function_single(cpu, mvneta_percpu_unmask_interrupt, 3708f8642885SMaxime Ripard pp, true); 3709f8642885SMaxime Ripard i++; 37102dcf75e2SGregory CLEMENT 3711f8642885SMaxime Ripard } 3712f8642885SMaxime Ripard }; 3713f8642885SMaxime Ripard 371484a3f4dbSSebastian Andrzej Siewior static int mvneta_cpu_online(unsigned int cpu, struct hlist_node *node) 3715f8642885SMaxime Ripard { 371684a3f4dbSSebastian Andrzej Siewior int other_cpu; 371784a3f4dbSSebastian Andrzej Siewior struct mvneta_port *pp = hlist_entry_safe(node, struct mvneta_port, 371884a3f4dbSSebastian Andrzej Siewior node_online); 3719f8642885SMaxime Ripard struct mvneta_pcpu_port *port = per_cpu_ptr(pp->ports, cpu); 3720f8642885SMaxime Ripard 372184a3f4dbSSebastian Andrzej Siewior 3722120cfa50SGregory CLEMENT spin_lock(&pp->lock); 372384a3f4dbSSebastian Andrzej Siewior /* 372484a3f4dbSSebastian Andrzej Siewior * Configuring the driver for a new CPU while the driver is 372584a3f4dbSSebastian Andrzej Siewior * stopping is racy, so just avoid it. 3726120cfa50SGregory CLEMENT */ 3727120cfa50SGregory CLEMENT if (pp->is_stopped) { 3728120cfa50SGregory CLEMENT spin_unlock(&pp->lock); 372984a3f4dbSSebastian Andrzej Siewior return 0; 3730120cfa50SGregory CLEMENT } 3731f8642885SMaxime Ripard netif_tx_stop_all_queues(pp->dev); 3732f8642885SMaxime Ripard 373384a3f4dbSSebastian Andrzej Siewior /* 373484a3f4dbSSebastian Andrzej Siewior * We have to synchronise on tha napi of each CPU except the one 373584a3f4dbSSebastian Andrzej Siewior * just being woken up 3736f8642885SMaxime Ripard */ 3737f8642885SMaxime Ripard for_each_online_cpu(other_cpu) { 3738f8642885SMaxime Ripard if (other_cpu != cpu) { 3739f8642885SMaxime Ripard struct mvneta_pcpu_port *other_port = 3740f8642885SMaxime Ripard per_cpu_ptr(pp->ports, other_cpu); 3741f8642885SMaxime Ripard 3742f8642885SMaxime Ripard napi_synchronize(&other_port->napi); 3743f8642885SMaxime Ripard } 3744f8642885SMaxime Ripard } 3745f8642885SMaxime Ripard 3746f8642885SMaxime Ripard /* Mask all ethernet port interrupts */ 3747db488c10SGregory CLEMENT on_each_cpu(mvneta_percpu_mask_interrupt, pp, true); 3748f8642885SMaxime Ripard napi_enable(&port->napi); 3749f8642885SMaxime Ripard 375084a3f4dbSSebastian Andrzej Siewior /* 375184a3f4dbSSebastian Andrzej Siewior * Enable per-CPU interrupts on the CPU that is 37522dcf75e2SGregory CLEMENT * brought up. 37532dcf75e2SGregory CLEMENT */ 37540e28bf93SAnna-Maria Gleixner mvneta_percpu_enable(pp); 37552dcf75e2SGregory CLEMENT 375684a3f4dbSSebastian Andrzej Siewior /* 375784a3f4dbSSebastian Andrzej Siewior * Enable per-CPU interrupt on the one CPU we care 3758f8642885SMaxime Ripard * about. 3759f8642885SMaxime Ripard */ 3760f8642885SMaxime Ripard mvneta_percpu_elect(pp); 3761f8642885SMaxime Ripard 3762db488c10SGregory CLEMENT /* Unmask all ethernet port interrupts */ 3763db488c10SGregory CLEMENT on_each_cpu(mvneta_percpu_unmask_interrupt, pp, true); 3764f8642885SMaxime Ripard mvreg_write(pp, MVNETA_INTR_MISC_MASK, 3765f8642885SMaxime Ripard MVNETA_CAUSE_PHY_STATUS_CHANGE | 3766856b2cc5SRussell King MVNETA_CAUSE_LINK_CHANGE); 3767f8642885SMaxime Ripard netif_tx_start_all_queues(pp->dev); 3768120cfa50SGregory CLEMENT spin_unlock(&pp->lock); 376984a3f4dbSSebastian Andrzej Siewior return 0; 377084a3f4dbSSebastian Andrzej Siewior } 377184a3f4dbSSebastian Andrzej Siewior 377284a3f4dbSSebastian Andrzej Siewior static int mvneta_cpu_down_prepare(unsigned int cpu, struct hlist_node *node) 377384a3f4dbSSebastian Andrzej Siewior { 377484a3f4dbSSebastian Andrzej Siewior struct mvneta_port *pp = hlist_entry_safe(node, struct mvneta_port, 377584a3f4dbSSebastian Andrzej Siewior node_online); 377684a3f4dbSSebastian Andrzej Siewior struct mvneta_pcpu_port *port = per_cpu_ptr(pp->ports, cpu); 377784a3f4dbSSebastian Andrzej Siewior 377884a3f4dbSSebastian Andrzej Siewior /* 377984a3f4dbSSebastian Andrzej Siewior * Thanks to this lock we are sure that any pending cpu election is 378084a3f4dbSSebastian Andrzej Siewior * done. 37815888511eSGregory CLEMENT */ 37825888511eSGregory CLEMENT spin_lock(&pp->lock); 3783f8642885SMaxime Ripard /* Mask all ethernet port interrupts */ 3784db488c10SGregory CLEMENT on_each_cpu(mvneta_percpu_mask_interrupt, pp, true); 37855888511eSGregory CLEMENT spin_unlock(&pp->lock); 3786f8642885SMaxime Ripard 3787f8642885SMaxime Ripard napi_synchronize(&port->napi); 3788f8642885SMaxime Ripard napi_disable(&port->napi); 378984a3f4dbSSebastian Andrzej Siewior /* Disable per-CPU interrupts on the CPU that is brought down. */ 37900e28bf93SAnna-Maria Gleixner mvneta_percpu_disable(pp); 379184a3f4dbSSebastian Andrzej Siewior return 0; 379284a3f4dbSSebastian Andrzej Siewior } 3793f8642885SMaxime Ripard 379484a3f4dbSSebastian Andrzej Siewior static int mvneta_cpu_dead(unsigned int cpu, struct hlist_node *node) 379584a3f4dbSSebastian Andrzej Siewior { 379684a3f4dbSSebastian Andrzej Siewior struct mvneta_port *pp = hlist_entry_safe(node, struct mvneta_port, 379784a3f4dbSSebastian Andrzej Siewior node_dead); 379884a3f4dbSSebastian Andrzej Siewior 3799f8642885SMaxime Ripard /* Check if a new CPU must be elected now this on is down */ 3800120cfa50SGregory CLEMENT spin_lock(&pp->lock); 3801f8642885SMaxime Ripard mvneta_percpu_elect(pp); 3802120cfa50SGregory CLEMENT spin_unlock(&pp->lock); 3803f8642885SMaxime Ripard /* Unmask all ethernet port interrupts */ 3804db488c10SGregory CLEMENT on_each_cpu(mvneta_percpu_unmask_interrupt, pp, true); 3805f8642885SMaxime Ripard mvreg_write(pp, MVNETA_INTR_MISC_MASK, 3806f8642885SMaxime Ripard MVNETA_CAUSE_PHY_STATUS_CHANGE | 3807856b2cc5SRussell King MVNETA_CAUSE_LINK_CHANGE); 3808f8642885SMaxime Ripard netif_tx_start_all_queues(pp->dev); 380984a3f4dbSSebastian Andrzej Siewior return 0; 3810f8642885SMaxime Ripard } 3811f8642885SMaxime Ripard 3812c5aff182SThomas Petazzoni static int mvneta_open(struct net_device *dev) 3813c5aff182SThomas Petazzoni { 3814c5aff182SThomas Petazzoni struct mvneta_port *pp = netdev_priv(dev); 38156b125d63SGregory CLEMENT int ret; 3816c5aff182SThomas Petazzoni 3817c5aff182SThomas Petazzoni pp->pkt_size = MVNETA_RX_PKT_SIZE(pp->dev->mtu); 3818c5aff182SThomas Petazzoni 3819c5aff182SThomas Petazzoni ret = mvneta_setup_rxqs(pp); 3820c5aff182SThomas Petazzoni if (ret) 3821c5aff182SThomas Petazzoni return ret; 3822c5aff182SThomas Petazzoni 3823c5aff182SThomas Petazzoni ret = mvneta_setup_txqs(pp); 3824c5aff182SThomas Petazzoni if (ret) 3825c5aff182SThomas Petazzoni goto err_cleanup_rxqs; 3826c5aff182SThomas Petazzoni 3827c5aff182SThomas Petazzoni /* Connect to port interrupt line */ 38282636ac3cSMarcin Wojtas if (pp->neta_armada3700) 38292636ac3cSMarcin Wojtas ret = request_irq(pp->dev->irq, mvneta_isr, 0, 38302636ac3cSMarcin Wojtas dev->name, pp); 38312636ac3cSMarcin Wojtas else 38322636ac3cSMarcin Wojtas ret = request_percpu_irq(pp->dev->irq, mvneta_percpu_isr, 38332636ac3cSMarcin Wojtas dev->name, pp->ports); 3834c5aff182SThomas Petazzoni if (ret) { 3835c5aff182SThomas Petazzoni netdev_err(pp->dev, "cannot request irq %d\n", pp->dev->irq); 3836c5aff182SThomas Petazzoni goto err_cleanup_txqs; 3837c5aff182SThomas Petazzoni } 3838c5aff182SThomas Petazzoni 38392636ac3cSMarcin Wojtas if (!pp->neta_armada3700) { 38402dcf75e2SGregory CLEMENT /* Enable per-CPU interrupt on all the CPU to handle our RX 38412dcf75e2SGregory CLEMENT * queue interrupts 38422dcf75e2SGregory CLEMENT */ 38436b125d63SGregory CLEMENT on_each_cpu(mvneta_percpu_enable, pp, true); 38442dcf75e2SGregory CLEMENT 3845120cfa50SGregory CLEMENT pp->is_stopped = false; 3846f8642885SMaxime Ripard /* Register a CPU notifier to handle the case where our CPU 3847f8642885SMaxime Ripard * might be taken offline. 3848f8642885SMaxime Ripard */ 384984a3f4dbSSebastian Andrzej Siewior ret = cpuhp_state_add_instance_nocalls(online_hpstate, 385084a3f4dbSSebastian Andrzej Siewior &pp->node_online); 385184a3f4dbSSebastian Andrzej Siewior if (ret) 385284a3f4dbSSebastian Andrzej Siewior goto err_free_irq; 385384a3f4dbSSebastian Andrzej Siewior 385484a3f4dbSSebastian Andrzej Siewior ret = cpuhp_state_add_instance_nocalls(CPUHP_NET_MVNETA_DEAD, 385584a3f4dbSSebastian Andrzej Siewior &pp->node_dead); 385684a3f4dbSSebastian Andrzej Siewior if (ret) 385784a3f4dbSSebastian Andrzej Siewior goto err_free_online_hp; 38582636ac3cSMarcin Wojtas } 3859f8642885SMaxime Ripard 3860c5aff182SThomas Petazzoni ret = mvneta_mdio_probe(pp); 3861c5aff182SThomas Petazzoni if (ret < 0) { 3862c5aff182SThomas Petazzoni netdev_err(dev, "cannot probe MDIO bus\n"); 386384a3f4dbSSebastian Andrzej Siewior goto err_free_dead_hp; 3864c5aff182SThomas Petazzoni } 3865c5aff182SThomas Petazzoni 3866c5aff182SThomas Petazzoni mvneta_start_dev(pp); 3867c5aff182SThomas Petazzoni 3868c5aff182SThomas Petazzoni return 0; 3869c5aff182SThomas Petazzoni 387084a3f4dbSSebastian Andrzej Siewior err_free_dead_hp: 38712636ac3cSMarcin Wojtas if (!pp->neta_armada3700) 387284a3f4dbSSebastian Andrzej Siewior cpuhp_state_remove_instance_nocalls(CPUHP_NET_MVNETA_DEAD, 387384a3f4dbSSebastian Andrzej Siewior &pp->node_dead); 387484a3f4dbSSebastian Andrzej Siewior err_free_online_hp: 38752636ac3cSMarcin Wojtas if (!pp->neta_armada3700) 38762636ac3cSMarcin Wojtas cpuhp_state_remove_instance_nocalls(online_hpstate, 38772636ac3cSMarcin Wojtas &pp->node_online); 3878c5aff182SThomas Petazzoni err_free_irq: 38792636ac3cSMarcin Wojtas if (pp->neta_armada3700) { 38802636ac3cSMarcin Wojtas free_irq(pp->dev->irq, pp); 38812636ac3cSMarcin Wojtas } else { 38823d8c4530SRussell King - ARM Linux on_each_cpu(mvneta_percpu_disable, pp, true); 388312bb03b4SMaxime Ripard free_percpu_irq(pp->dev->irq, pp->ports); 38842636ac3cSMarcin Wojtas } 3885c5aff182SThomas Petazzoni err_cleanup_txqs: 3886c5aff182SThomas Petazzoni mvneta_cleanup_txqs(pp); 3887c5aff182SThomas Petazzoni err_cleanup_rxqs: 3888c5aff182SThomas Petazzoni mvneta_cleanup_rxqs(pp); 3889c5aff182SThomas Petazzoni return ret; 3890c5aff182SThomas Petazzoni } 3891c5aff182SThomas Petazzoni 3892c5aff182SThomas Petazzoni /* Stop the port, free port interrupt line */ 3893c5aff182SThomas Petazzoni static int mvneta_stop(struct net_device *dev) 3894c5aff182SThomas Petazzoni { 3895c5aff182SThomas Petazzoni struct mvneta_port *pp = netdev_priv(dev); 3896c5aff182SThomas Petazzoni 38972636ac3cSMarcin Wojtas if (!pp->neta_armada3700) { 3898120cfa50SGregory CLEMENT /* Inform that we are stopping so we don't want to setup the 38991c2722a9SGregory CLEMENT * driver for new CPUs in the notifiers. The code of the 39001c2722a9SGregory CLEMENT * notifier for CPU online is protected by the same spinlock, 39011c2722a9SGregory CLEMENT * so when we get the lock, the notifer work is done. 3902120cfa50SGregory CLEMENT */ 3903120cfa50SGregory CLEMENT spin_lock(&pp->lock); 3904120cfa50SGregory CLEMENT pp->is_stopped = true; 39051c2722a9SGregory CLEMENT spin_unlock(&pp->lock); 39061c2722a9SGregory CLEMENT 3907c5aff182SThomas Petazzoni mvneta_stop_dev(pp); 3908c5aff182SThomas Petazzoni mvneta_mdio_remove(pp); 390984a3f4dbSSebastian Andrzej Siewior 3910d26aac2dSDan Carpenter cpuhp_state_remove_instance_nocalls(online_hpstate, 3911d26aac2dSDan Carpenter &pp->node_online); 391284a3f4dbSSebastian Andrzej Siewior cpuhp_state_remove_instance_nocalls(CPUHP_NET_MVNETA_DEAD, 391384a3f4dbSSebastian Andrzej Siewior &pp->node_dead); 3914129219e4SGregory CLEMENT on_each_cpu(mvneta_percpu_disable, pp, true); 391512bb03b4SMaxime Ripard free_percpu_irq(dev->irq, pp->ports); 39162636ac3cSMarcin Wojtas } else { 39172636ac3cSMarcin Wojtas mvneta_stop_dev(pp); 39182636ac3cSMarcin Wojtas mvneta_mdio_remove(pp); 39192636ac3cSMarcin Wojtas free_irq(dev->irq, pp); 39202636ac3cSMarcin Wojtas } 39212636ac3cSMarcin Wojtas 3922c5aff182SThomas Petazzoni mvneta_cleanup_rxqs(pp); 3923c5aff182SThomas Petazzoni mvneta_cleanup_txqs(pp); 3924c5aff182SThomas Petazzoni 3925c5aff182SThomas Petazzoni return 0; 3926c5aff182SThomas Petazzoni } 3927c5aff182SThomas Petazzoni 392815f59456SThomas Petazzoni static int mvneta_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) 392915f59456SThomas Petazzoni { 3930503f9aa9SRussell King struct mvneta_port *pp = netdev_priv(dev); 393115f59456SThomas Petazzoni 3932503f9aa9SRussell King return phylink_mii_ioctl(pp->phylink, ifr, cmd); 393315f59456SThomas Petazzoni } 393415f59456SThomas Petazzoni 3935c5aff182SThomas Petazzoni /* Ethtool methods */ 3936c5aff182SThomas Petazzoni 3937013ad40dSPhilippe Reynes /* Set link ksettings (phy address, speed) for ethtools */ 39382dc0d2b4SBaoyou Xie static int 39392dc0d2b4SBaoyou Xie mvneta_ethtool_set_link_ksettings(struct net_device *ndev, 3940013ad40dSPhilippe Reynes const struct ethtool_link_ksettings *cmd) 3941c5aff182SThomas Petazzoni { 3942013ad40dSPhilippe Reynes struct mvneta_port *pp = netdev_priv(ndev); 3943c5aff182SThomas Petazzoni 3944503f9aa9SRussell King return phylink_ethtool_ksettings_set(pp->phylink, cmd); 39450c0744fcSStas Sergeev } 39460c0744fcSStas Sergeev 3947503f9aa9SRussell King /* Get link ksettings for ethtools */ 3948503f9aa9SRussell King static int 3949503f9aa9SRussell King mvneta_ethtool_get_link_ksettings(struct net_device *ndev, 3950503f9aa9SRussell King struct ethtool_link_ksettings *cmd) 3951503f9aa9SRussell King { 3952503f9aa9SRussell King struct mvneta_port *pp = netdev_priv(ndev); 39530c0744fcSStas Sergeev 3954503f9aa9SRussell King return phylink_ethtool_ksettings_get(pp->phylink, cmd); 39550c0744fcSStas Sergeev } 39560c0744fcSStas Sergeev 3957503f9aa9SRussell King static int mvneta_ethtool_nway_reset(struct net_device *dev) 3958503f9aa9SRussell King { 3959503f9aa9SRussell King struct mvneta_port *pp = netdev_priv(dev); 3960503f9aa9SRussell King 3961503f9aa9SRussell King return phylink_ethtool_nway_reset(pp->phylink); 3962c5aff182SThomas Petazzoni } 3963c5aff182SThomas Petazzoni 3964c5aff182SThomas Petazzoni /* Set interrupt coalescing for ethtools */ 3965c5aff182SThomas Petazzoni static int mvneta_ethtool_set_coalesce(struct net_device *dev, 3966c5aff182SThomas Petazzoni struct ethtool_coalesce *c) 3967c5aff182SThomas Petazzoni { 3968c5aff182SThomas Petazzoni struct mvneta_port *pp = netdev_priv(dev); 3969c5aff182SThomas Petazzoni int queue; 3970c5aff182SThomas Petazzoni 3971c5aff182SThomas Petazzoni for (queue = 0; queue < rxq_number; queue++) { 3972c5aff182SThomas Petazzoni struct mvneta_rx_queue *rxq = &pp->rxqs[queue]; 3973c5aff182SThomas Petazzoni rxq->time_coal = c->rx_coalesce_usecs; 3974c5aff182SThomas Petazzoni rxq->pkts_coal = c->rx_max_coalesced_frames; 3975c5aff182SThomas Petazzoni mvneta_rx_pkts_coal_set(pp, rxq, rxq->pkts_coal); 3976c5aff182SThomas Petazzoni mvneta_rx_time_coal_set(pp, rxq, rxq->time_coal); 3977c5aff182SThomas Petazzoni } 3978c5aff182SThomas Petazzoni 3979c5aff182SThomas Petazzoni for (queue = 0; queue < txq_number; queue++) { 3980c5aff182SThomas Petazzoni struct mvneta_tx_queue *txq = &pp->txqs[queue]; 3981c5aff182SThomas Petazzoni txq->done_pkts_coal = c->tx_max_coalesced_frames; 3982c5aff182SThomas Petazzoni mvneta_tx_done_pkts_coal_set(pp, txq, txq->done_pkts_coal); 3983c5aff182SThomas Petazzoni } 3984c5aff182SThomas Petazzoni 3985c5aff182SThomas Petazzoni return 0; 3986c5aff182SThomas Petazzoni } 3987c5aff182SThomas Petazzoni 3988c5aff182SThomas Petazzoni /* get coalescing for ethtools */ 3989c5aff182SThomas Petazzoni static int mvneta_ethtool_get_coalesce(struct net_device *dev, 3990c5aff182SThomas Petazzoni struct ethtool_coalesce *c) 3991c5aff182SThomas Petazzoni { 3992c5aff182SThomas Petazzoni struct mvneta_port *pp = netdev_priv(dev); 3993c5aff182SThomas Petazzoni 3994c5aff182SThomas Petazzoni c->rx_coalesce_usecs = pp->rxqs[0].time_coal; 3995c5aff182SThomas Petazzoni c->rx_max_coalesced_frames = pp->rxqs[0].pkts_coal; 3996c5aff182SThomas Petazzoni 3997c5aff182SThomas Petazzoni c->tx_max_coalesced_frames = pp->txqs[0].done_pkts_coal; 3998c5aff182SThomas Petazzoni return 0; 3999c5aff182SThomas Petazzoni } 4000c5aff182SThomas Petazzoni 4001c5aff182SThomas Petazzoni 4002c5aff182SThomas Petazzoni static void mvneta_ethtool_get_drvinfo(struct net_device *dev, 4003c5aff182SThomas Petazzoni struct ethtool_drvinfo *drvinfo) 4004c5aff182SThomas Petazzoni { 4005c5aff182SThomas Petazzoni strlcpy(drvinfo->driver, MVNETA_DRIVER_NAME, 4006c5aff182SThomas Petazzoni sizeof(drvinfo->driver)); 4007c5aff182SThomas Petazzoni strlcpy(drvinfo->version, MVNETA_DRIVER_VERSION, 4008c5aff182SThomas Petazzoni sizeof(drvinfo->version)); 4009c5aff182SThomas Petazzoni strlcpy(drvinfo->bus_info, dev_name(&dev->dev), 4010c5aff182SThomas Petazzoni sizeof(drvinfo->bus_info)); 4011c5aff182SThomas Petazzoni } 4012c5aff182SThomas Petazzoni 4013c5aff182SThomas Petazzoni 4014c5aff182SThomas Petazzoni static void mvneta_ethtool_get_ringparam(struct net_device *netdev, 4015c5aff182SThomas Petazzoni struct ethtool_ringparam *ring) 4016c5aff182SThomas Petazzoni { 4017c5aff182SThomas Petazzoni struct mvneta_port *pp = netdev_priv(netdev); 4018c5aff182SThomas Petazzoni 4019c5aff182SThomas Petazzoni ring->rx_max_pending = MVNETA_MAX_RXD; 4020c5aff182SThomas Petazzoni ring->tx_max_pending = MVNETA_MAX_TXD; 4021c5aff182SThomas Petazzoni ring->rx_pending = pp->rx_ring_size; 4022c5aff182SThomas Petazzoni ring->tx_pending = pp->tx_ring_size; 4023c5aff182SThomas Petazzoni } 4024c5aff182SThomas Petazzoni 4025c5aff182SThomas Petazzoni static int mvneta_ethtool_set_ringparam(struct net_device *dev, 4026c5aff182SThomas Petazzoni struct ethtool_ringparam *ring) 4027c5aff182SThomas Petazzoni { 4028c5aff182SThomas Petazzoni struct mvneta_port *pp = netdev_priv(dev); 4029c5aff182SThomas Petazzoni 4030c5aff182SThomas Petazzoni if ((ring->rx_pending == 0) || (ring->tx_pending == 0)) 4031c5aff182SThomas Petazzoni return -EINVAL; 4032c5aff182SThomas Petazzoni pp->rx_ring_size = ring->rx_pending < MVNETA_MAX_RXD ? 4033c5aff182SThomas Petazzoni ring->rx_pending : MVNETA_MAX_RXD; 40348eef5f97SEzequiel Garcia 40358eef5f97SEzequiel Garcia pp->tx_ring_size = clamp_t(u16, ring->tx_pending, 40368eef5f97SEzequiel Garcia MVNETA_MAX_SKB_DESCS * 2, MVNETA_MAX_TXD); 40378eef5f97SEzequiel Garcia if (pp->tx_ring_size != ring->tx_pending) 40388eef5f97SEzequiel Garcia netdev_warn(dev, "TX queue size set to %u (requested %u)\n", 40398eef5f97SEzequiel Garcia pp->tx_ring_size, ring->tx_pending); 4040c5aff182SThomas Petazzoni 4041c5aff182SThomas Petazzoni if (netif_running(dev)) { 4042c5aff182SThomas Petazzoni mvneta_stop(dev); 4043c5aff182SThomas Petazzoni if (mvneta_open(dev)) { 4044c5aff182SThomas Petazzoni netdev_err(dev, 4045c5aff182SThomas Petazzoni "error on opening device after ring param change\n"); 4046c5aff182SThomas Petazzoni return -ENOMEM; 4047c5aff182SThomas Petazzoni } 4048c5aff182SThomas Petazzoni } 4049c5aff182SThomas Petazzoni 4050c5aff182SThomas Petazzoni return 0; 4051c5aff182SThomas Petazzoni } 4052c5aff182SThomas Petazzoni 40534932a918SRussell King static void mvneta_ethtool_get_pauseparam(struct net_device *dev, 40544932a918SRussell King struct ethtool_pauseparam *pause) 40554932a918SRussell King { 40564932a918SRussell King struct mvneta_port *pp = netdev_priv(dev); 40574932a918SRussell King 40584932a918SRussell King phylink_ethtool_get_pauseparam(pp->phylink, pause); 40594932a918SRussell King } 40604932a918SRussell King 40614932a918SRussell King static int mvneta_ethtool_set_pauseparam(struct net_device *dev, 40624932a918SRussell King struct ethtool_pauseparam *pause) 40634932a918SRussell King { 40644932a918SRussell King struct mvneta_port *pp = netdev_priv(dev); 40654932a918SRussell King 40664932a918SRussell King return phylink_ethtool_set_pauseparam(pp->phylink, pause); 40674932a918SRussell King } 40684932a918SRussell King 40699b0cdefaSRussell King static void mvneta_ethtool_get_strings(struct net_device *netdev, u32 sset, 40709b0cdefaSRussell King u8 *data) 40719b0cdefaSRussell King { 40729b0cdefaSRussell King if (sset == ETH_SS_STATS) { 40739b0cdefaSRussell King int i; 40749b0cdefaSRussell King 40759b0cdefaSRussell King for (i = 0; i < ARRAY_SIZE(mvneta_statistics); i++) 40769b0cdefaSRussell King memcpy(data + i * ETH_GSTRING_LEN, 40779b0cdefaSRussell King mvneta_statistics[i].name, ETH_GSTRING_LEN); 40789b0cdefaSRussell King } 40799b0cdefaSRussell King } 40809b0cdefaSRussell King 40819b0cdefaSRussell King static void mvneta_ethtool_update_stats(struct mvneta_port *pp) 40829b0cdefaSRussell King { 40839b0cdefaSRussell King const struct mvneta_statistic *s; 40849b0cdefaSRussell King void __iomem *base = pp->base; 40856d81f451SRussell King u32 high, low; 40866d81f451SRussell King u64 val; 40879b0cdefaSRussell King int i; 40889b0cdefaSRussell King 40899b0cdefaSRussell King for (i = 0, s = mvneta_statistics; 40909b0cdefaSRussell King s < mvneta_statistics + ARRAY_SIZE(mvneta_statistics); 40919b0cdefaSRussell King s++, i++) { 40926d81f451SRussell King val = 0; 40936d81f451SRussell King 40949b0cdefaSRussell King switch (s->type) { 40959b0cdefaSRussell King case T_REG_32: 40969b0cdefaSRussell King val = readl_relaxed(base + s->offset); 40979b0cdefaSRussell King break; 40989b0cdefaSRussell King case T_REG_64: 40999b0cdefaSRussell King /* Docs say to read low 32-bit then high */ 41009b0cdefaSRussell King low = readl_relaxed(base + s->offset); 41019b0cdefaSRussell King high = readl_relaxed(base + s->offset + 4); 41026d81f451SRussell King val = (u64)high << 32 | low; 41036d81f451SRussell King break; 41046d81f451SRussell King case T_SW: 41056d81f451SRussell King switch (s->offset) { 41066d81f451SRussell King case ETHTOOL_STAT_EEE_WAKEUP: 41076d81f451SRussell King val = phylink_get_eee_err(pp->phylink); 41089b0cdefaSRussell King break; 410917a96da6SGregory CLEMENT case ETHTOOL_STAT_SKB_ALLOC_ERR: 411017a96da6SGregory CLEMENT val = pp->rxqs[0].skb_alloc_err; 411117a96da6SGregory CLEMENT break; 411217a96da6SGregory CLEMENT case ETHTOOL_STAT_REFILL_ERR: 411317a96da6SGregory CLEMENT val = pp->rxqs[0].refill_err; 411417a96da6SGregory CLEMENT break; 41159b0cdefaSRussell King } 41166d81f451SRussell King break; 41176d81f451SRussell King } 41186d81f451SRussell King 41196d81f451SRussell King pp->ethtool_stats[i] += val; 41209b0cdefaSRussell King } 41219b0cdefaSRussell King } 41229b0cdefaSRussell King 41239b0cdefaSRussell King static void mvneta_ethtool_get_stats(struct net_device *dev, 41249b0cdefaSRussell King struct ethtool_stats *stats, u64 *data) 41259b0cdefaSRussell King { 41269b0cdefaSRussell King struct mvneta_port *pp = netdev_priv(dev); 41279b0cdefaSRussell King int i; 41289b0cdefaSRussell King 41299b0cdefaSRussell King mvneta_ethtool_update_stats(pp); 41309b0cdefaSRussell King 41319b0cdefaSRussell King for (i = 0; i < ARRAY_SIZE(mvneta_statistics); i++) 41329b0cdefaSRussell King *data++ = pp->ethtool_stats[i]; 41339b0cdefaSRussell King } 41349b0cdefaSRussell King 41359b0cdefaSRussell King static int mvneta_ethtool_get_sset_count(struct net_device *dev, int sset) 41369b0cdefaSRussell King { 41379b0cdefaSRussell King if (sset == ETH_SS_STATS) 41389b0cdefaSRussell King return ARRAY_SIZE(mvneta_statistics); 41399b0cdefaSRussell King return -EOPNOTSUPP; 41409b0cdefaSRussell King } 41419b0cdefaSRussell King 41429a401deaSGregory CLEMENT static u32 mvneta_ethtool_get_rxfh_indir_size(struct net_device *dev) 41439a401deaSGregory CLEMENT { 41449a401deaSGregory CLEMENT return MVNETA_RSS_LU_TABLE_SIZE; 41459a401deaSGregory CLEMENT } 41469a401deaSGregory CLEMENT 41479a401deaSGregory CLEMENT static int mvneta_ethtool_get_rxnfc(struct net_device *dev, 41489a401deaSGregory CLEMENT struct ethtool_rxnfc *info, 41499a401deaSGregory CLEMENT u32 *rules __always_unused) 41509a401deaSGregory CLEMENT { 41519a401deaSGregory CLEMENT switch (info->cmd) { 41529a401deaSGregory CLEMENT case ETHTOOL_GRXRINGS: 41539a401deaSGregory CLEMENT info->data = rxq_number; 41549a401deaSGregory CLEMENT return 0; 41559a401deaSGregory CLEMENT case ETHTOOL_GRXFH: 41569a401deaSGregory CLEMENT return -EOPNOTSUPP; 41579a401deaSGregory CLEMENT default: 41589a401deaSGregory CLEMENT return -EOPNOTSUPP; 41599a401deaSGregory CLEMENT } 41609a401deaSGregory CLEMENT } 41619a401deaSGregory CLEMENT 41629a401deaSGregory CLEMENT static int mvneta_config_rss(struct mvneta_port *pp) 41639a401deaSGregory CLEMENT { 41649a401deaSGregory CLEMENT int cpu; 41659a401deaSGregory CLEMENT u32 val; 41669a401deaSGregory CLEMENT 41679a401deaSGregory CLEMENT netif_tx_stop_all_queues(pp->dev); 41689a401deaSGregory CLEMENT 41696b125d63SGregory CLEMENT on_each_cpu(mvneta_percpu_mask_interrupt, pp, true); 41709a401deaSGregory CLEMENT 41710f5c6c30SJisheng Zhang if (!pp->neta_armada3700) { 41729a401deaSGregory CLEMENT /* We have to synchronise on the napi of each CPU */ 41739a401deaSGregory CLEMENT for_each_online_cpu(cpu) { 41749a401deaSGregory CLEMENT struct mvneta_pcpu_port *pcpu_port = 41759a401deaSGregory CLEMENT per_cpu_ptr(pp->ports, cpu); 41769a401deaSGregory CLEMENT 41779a401deaSGregory CLEMENT napi_synchronize(&pcpu_port->napi); 41789a401deaSGregory CLEMENT napi_disable(&pcpu_port->napi); 41799a401deaSGregory CLEMENT } 41800f5c6c30SJisheng Zhang } else { 41810f5c6c30SJisheng Zhang napi_synchronize(&pp->napi); 41820f5c6c30SJisheng Zhang napi_disable(&pp->napi); 41830f5c6c30SJisheng Zhang } 41849a401deaSGregory CLEMENT 41859a401deaSGregory CLEMENT pp->rxq_def = pp->indir[0]; 41869a401deaSGregory CLEMENT 41879a401deaSGregory CLEMENT /* Update unicast mapping */ 41889a401deaSGregory CLEMENT mvneta_set_rx_mode(pp->dev); 41899a401deaSGregory CLEMENT 41909a401deaSGregory CLEMENT /* Update val of portCfg register accordingly with all RxQueue types */ 41919a401deaSGregory CLEMENT val = MVNETA_PORT_CONFIG_DEFL_VALUE(pp->rxq_def); 41929a401deaSGregory CLEMENT mvreg_write(pp, MVNETA_PORT_CONFIG, val); 41939a401deaSGregory CLEMENT 41949a401deaSGregory CLEMENT /* Update the elected CPU matching the new rxq_def */ 4195120cfa50SGregory CLEMENT spin_lock(&pp->lock); 41969a401deaSGregory CLEMENT mvneta_percpu_elect(pp); 4197120cfa50SGregory CLEMENT spin_unlock(&pp->lock); 41989a401deaSGregory CLEMENT 41990f5c6c30SJisheng Zhang if (!pp->neta_armada3700) { 42009a401deaSGregory CLEMENT /* We have to synchronise on the napi of each CPU */ 42019a401deaSGregory CLEMENT for_each_online_cpu(cpu) { 42029a401deaSGregory CLEMENT struct mvneta_pcpu_port *pcpu_port = 42039a401deaSGregory CLEMENT per_cpu_ptr(pp->ports, cpu); 42049a401deaSGregory CLEMENT 42059a401deaSGregory CLEMENT napi_enable(&pcpu_port->napi); 42069a401deaSGregory CLEMENT } 42070f5c6c30SJisheng Zhang } else { 42080f5c6c30SJisheng Zhang napi_enable(&pp->napi); 42090f5c6c30SJisheng Zhang } 42109a401deaSGregory CLEMENT 42119a401deaSGregory CLEMENT netif_tx_start_all_queues(pp->dev); 42129a401deaSGregory CLEMENT 42139a401deaSGregory CLEMENT return 0; 42149a401deaSGregory CLEMENT } 42159a401deaSGregory CLEMENT 42169a401deaSGregory CLEMENT static int mvneta_ethtool_set_rxfh(struct net_device *dev, const u32 *indir, 42179a401deaSGregory CLEMENT const u8 *key, const u8 hfunc) 42189a401deaSGregory CLEMENT { 42199a401deaSGregory CLEMENT struct mvneta_port *pp = netdev_priv(dev); 42202636ac3cSMarcin Wojtas 42212636ac3cSMarcin Wojtas /* Current code for Armada 3700 doesn't support RSS features yet */ 42222636ac3cSMarcin Wojtas if (pp->neta_armada3700) 42232636ac3cSMarcin Wojtas return -EOPNOTSUPP; 42242636ac3cSMarcin Wojtas 42259a401deaSGregory CLEMENT /* We require at least one supported parameter to be changed 42269a401deaSGregory CLEMENT * and no change in any of the unsupported parameters 42279a401deaSGregory CLEMENT */ 42289a401deaSGregory CLEMENT if (key || 42299a401deaSGregory CLEMENT (hfunc != ETH_RSS_HASH_NO_CHANGE && hfunc != ETH_RSS_HASH_TOP)) 42309a401deaSGregory CLEMENT return -EOPNOTSUPP; 42319a401deaSGregory CLEMENT 42329a401deaSGregory CLEMENT if (!indir) 42339a401deaSGregory CLEMENT return 0; 42349a401deaSGregory CLEMENT 42359a401deaSGregory CLEMENT memcpy(pp->indir, indir, MVNETA_RSS_LU_TABLE_SIZE); 42369a401deaSGregory CLEMENT 42379a401deaSGregory CLEMENT return mvneta_config_rss(pp); 42389a401deaSGregory CLEMENT } 42399a401deaSGregory CLEMENT 42409a401deaSGregory CLEMENT static int mvneta_ethtool_get_rxfh(struct net_device *dev, u32 *indir, u8 *key, 42419a401deaSGregory CLEMENT u8 *hfunc) 42429a401deaSGregory CLEMENT { 42439a401deaSGregory CLEMENT struct mvneta_port *pp = netdev_priv(dev); 42449a401deaSGregory CLEMENT 42452636ac3cSMarcin Wojtas /* Current code for Armada 3700 doesn't support RSS features yet */ 42462636ac3cSMarcin Wojtas if (pp->neta_armada3700) 42472636ac3cSMarcin Wojtas return -EOPNOTSUPP; 42482636ac3cSMarcin Wojtas 42499a401deaSGregory CLEMENT if (hfunc) 42509a401deaSGregory CLEMENT *hfunc = ETH_RSS_HASH_TOP; 42519a401deaSGregory CLEMENT 42529a401deaSGregory CLEMENT if (!indir) 42539a401deaSGregory CLEMENT return 0; 42549a401deaSGregory CLEMENT 42559a401deaSGregory CLEMENT memcpy(indir, pp->indir, MVNETA_RSS_LU_TABLE_SIZE); 42569a401deaSGregory CLEMENT 42579a401deaSGregory CLEMENT return 0; 42589a401deaSGregory CLEMENT } 42599a401deaSGregory CLEMENT 4260b60a00f9SJingju Hou static void mvneta_ethtool_get_wol(struct net_device *dev, 4261b60a00f9SJingju Hou struct ethtool_wolinfo *wol) 4262b60a00f9SJingju Hou { 4263503f9aa9SRussell King struct mvneta_port *pp = netdev_priv(dev); 4264b60a00f9SJingju Hou 4265503f9aa9SRussell King phylink_ethtool_get_wol(pp->phylink, wol); 4266b60a00f9SJingju Hou } 4267b60a00f9SJingju Hou 4268b60a00f9SJingju Hou static int mvneta_ethtool_set_wol(struct net_device *dev, 4269b60a00f9SJingju Hou struct ethtool_wolinfo *wol) 4270b60a00f9SJingju Hou { 4271503f9aa9SRussell King struct mvneta_port *pp = netdev_priv(dev); 427282960fffSJisheng Zhang int ret; 427382960fffSJisheng Zhang 4274503f9aa9SRussell King ret = phylink_ethtool_set_wol(pp->phylink, wol); 427582960fffSJisheng Zhang if (!ret) 427682960fffSJisheng Zhang device_set_wakeup_enable(&dev->dev, !!wol->wolopts); 427782960fffSJisheng Zhang 427882960fffSJisheng Zhang return ret; 4279b60a00f9SJingju Hou } 4280b60a00f9SJingju Hou 42816d81f451SRussell King static int mvneta_ethtool_get_eee(struct net_device *dev, 42826d81f451SRussell King struct ethtool_eee *eee) 42836d81f451SRussell King { 42846d81f451SRussell King struct mvneta_port *pp = netdev_priv(dev); 42856d81f451SRussell King u32 lpi_ctl0; 42866d81f451SRussell King 42876d81f451SRussell King lpi_ctl0 = mvreg_read(pp, MVNETA_LPI_CTRL_0); 42886d81f451SRussell King 42896d81f451SRussell King eee->eee_enabled = pp->eee_enabled; 42906d81f451SRussell King eee->eee_active = pp->eee_active; 42916d81f451SRussell King eee->tx_lpi_enabled = pp->tx_lpi_enabled; 42926d81f451SRussell King eee->tx_lpi_timer = (lpi_ctl0) >> 8; // * scale; 42936d81f451SRussell King 42946d81f451SRussell King return phylink_ethtool_get_eee(pp->phylink, eee); 42956d81f451SRussell King } 42966d81f451SRussell King 42976d81f451SRussell King static int mvneta_ethtool_set_eee(struct net_device *dev, 42986d81f451SRussell King struct ethtool_eee *eee) 42996d81f451SRussell King { 43006d81f451SRussell King struct mvneta_port *pp = netdev_priv(dev); 43016d81f451SRussell King u32 lpi_ctl0; 43026d81f451SRussell King 43036d81f451SRussell King /* The Armada 37x documents do not give limits for this other than 43046d81f451SRussell King * it being an 8-bit register. */ 4305e4a3e9ffSYueHaibing if (eee->tx_lpi_enabled && eee->tx_lpi_timer > 255) 43066d81f451SRussell King return -EINVAL; 43076d81f451SRussell King 43086d81f451SRussell King lpi_ctl0 = mvreg_read(pp, MVNETA_LPI_CTRL_0); 43096d81f451SRussell King lpi_ctl0 &= ~(0xff << 8); 43106d81f451SRussell King lpi_ctl0 |= eee->tx_lpi_timer << 8; 43116d81f451SRussell King mvreg_write(pp, MVNETA_LPI_CTRL_0, lpi_ctl0); 43126d81f451SRussell King 43136d81f451SRussell King pp->eee_enabled = eee->eee_enabled; 43146d81f451SRussell King pp->tx_lpi_enabled = eee->tx_lpi_enabled; 43156d81f451SRussell King 43166d81f451SRussell King mvneta_set_eee(pp, eee->tx_lpi_enabled && eee->eee_enabled); 43176d81f451SRussell King 43186d81f451SRussell King return phylink_ethtool_set_eee(pp->phylink, eee); 43196d81f451SRussell King } 43206d81f451SRussell King 4321c5aff182SThomas Petazzoni static const struct net_device_ops mvneta_netdev_ops = { 4322c5aff182SThomas Petazzoni .ndo_open = mvneta_open, 4323c5aff182SThomas Petazzoni .ndo_stop = mvneta_stop, 4324c5aff182SThomas Petazzoni .ndo_start_xmit = mvneta_tx, 4325c5aff182SThomas Petazzoni .ndo_set_rx_mode = mvneta_set_rx_mode, 4326c5aff182SThomas Petazzoni .ndo_set_mac_address = mvneta_set_mac_addr, 4327c5aff182SThomas Petazzoni .ndo_change_mtu = mvneta_change_mtu, 4328b65657fcSSimon Guinot .ndo_fix_features = mvneta_fix_features, 4329c5aff182SThomas Petazzoni .ndo_get_stats64 = mvneta_get_stats64, 433015f59456SThomas Petazzoni .ndo_do_ioctl = mvneta_ioctl, 4331c5aff182SThomas Petazzoni }; 4332c5aff182SThomas Petazzoni 43334581be42SJisheng Zhang static const struct ethtool_ops mvneta_eth_tool_ops = { 4334503f9aa9SRussell King .nway_reset = mvneta_ethtool_nway_reset, 4335c5aff182SThomas Petazzoni .get_link = ethtool_op_get_link, 4336c5aff182SThomas Petazzoni .set_coalesce = mvneta_ethtool_set_coalesce, 4337c5aff182SThomas Petazzoni .get_coalesce = mvneta_ethtool_get_coalesce, 4338c5aff182SThomas Petazzoni .get_drvinfo = mvneta_ethtool_get_drvinfo, 4339c5aff182SThomas Petazzoni .get_ringparam = mvneta_ethtool_get_ringparam, 4340c5aff182SThomas Petazzoni .set_ringparam = mvneta_ethtool_set_ringparam, 43414932a918SRussell King .get_pauseparam = mvneta_ethtool_get_pauseparam, 43424932a918SRussell King .set_pauseparam = mvneta_ethtool_set_pauseparam, 43439b0cdefaSRussell King .get_strings = mvneta_ethtool_get_strings, 43449b0cdefaSRussell King .get_ethtool_stats = mvneta_ethtool_get_stats, 43459b0cdefaSRussell King .get_sset_count = mvneta_ethtool_get_sset_count, 43469a401deaSGregory CLEMENT .get_rxfh_indir_size = mvneta_ethtool_get_rxfh_indir_size, 43479a401deaSGregory CLEMENT .get_rxnfc = mvneta_ethtool_get_rxnfc, 43489a401deaSGregory CLEMENT .get_rxfh = mvneta_ethtool_get_rxfh, 43499a401deaSGregory CLEMENT .set_rxfh = mvneta_ethtool_set_rxfh, 4350503f9aa9SRussell King .get_link_ksettings = mvneta_ethtool_get_link_ksettings, 4351013ad40dSPhilippe Reynes .set_link_ksettings = mvneta_ethtool_set_link_ksettings, 4352b60a00f9SJingju Hou .get_wol = mvneta_ethtool_get_wol, 4353b60a00f9SJingju Hou .set_wol = mvneta_ethtool_set_wol, 43546d81f451SRussell King .get_eee = mvneta_ethtool_get_eee, 43556d81f451SRussell King .set_eee = mvneta_ethtool_set_eee, 4356c5aff182SThomas Petazzoni }; 4357c5aff182SThomas Petazzoni 4358c5aff182SThomas Petazzoni /* Initialize hw */ 43599672850bSEzequiel Garcia static int mvneta_init(struct device *dev, struct mvneta_port *pp) 4360c5aff182SThomas Petazzoni { 4361c5aff182SThomas Petazzoni int queue; 4362c5aff182SThomas Petazzoni 4363c5aff182SThomas Petazzoni /* Disable port */ 4364c5aff182SThomas Petazzoni mvneta_port_disable(pp); 4365c5aff182SThomas Petazzoni 4366c5aff182SThomas Petazzoni /* Set port default values */ 4367c5aff182SThomas Petazzoni mvneta_defaults_set(pp); 4368c5aff182SThomas Petazzoni 43695d6312edSMarkus Elfring pp->txqs = devm_kcalloc(dev, txq_number, sizeof(*pp->txqs), GFP_KERNEL); 4370c5aff182SThomas Petazzoni if (!pp->txqs) 4371c5aff182SThomas Petazzoni return -ENOMEM; 4372c5aff182SThomas Petazzoni 4373c5aff182SThomas Petazzoni /* Initialize TX descriptor rings */ 4374c5aff182SThomas Petazzoni for (queue = 0; queue < txq_number; queue++) { 4375c5aff182SThomas Petazzoni struct mvneta_tx_queue *txq = &pp->txqs[queue]; 4376c5aff182SThomas Petazzoni txq->id = queue; 4377c5aff182SThomas Petazzoni txq->size = pp->tx_ring_size; 4378c5aff182SThomas Petazzoni txq->done_pkts_coal = MVNETA_TXDONE_COAL_PKTS; 4379c5aff182SThomas Petazzoni } 4380c5aff182SThomas Petazzoni 43815d6312edSMarkus Elfring pp->rxqs = devm_kcalloc(dev, rxq_number, sizeof(*pp->rxqs), GFP_KERNEL); 43829672850bSEzequiel Garcia if (!pp->rxqs) 4383c5aff182SThomas Petazzoni return -ENOMEM; 4384c5aff182SThomas Petazzoni 4385c5aff182SThomas Petazzoni /* Create Rx descriptor rings */ 4386c5aff182SThomas Petazzoni for (queue = 0; queue < rxq_number; queue++) { 4387c5aff182SThomas Petazzoni struct mvneta_rx_queue *rxq = &pp->rxqs[queue]; 4388c5aff182SThomas Petazzoni rxq->id = queue; 4389c5aff182SThomas Petazzoni rxq->size = pp->rx_ring_size; 4390c5aff182SThomas Petazzoni rxq->pkts_coal = MVNETA_RX_COAL_PKTS; 4391c5aff182SThomas Petazzoni rxq->time_coal = MVNETA_RX_COAL_USEC; 439229110630SMarkus Elfring rxq->buf_virt_addr 439329110630SMarkus Elfring = devm_kmalloc_array(pp->dev->dev.parent, 439429110630SMarkus Elfring rxq->size, 439529110630SMarkus Elfring sizeof(*rxq->buf_virt_addr), 4396f88bee1cSGregory CLEMENT GFP_KERNEL); 4397f88bee1cSGregory CLEMENT if (!rxq->buf_virt_addr) 4398f88bee1cSGregory CLEMENT return -ENOMEM; 4399c5aff182SThomas Petazzoni } 4400c5aff182SThomas Petazzoni 4401c5aff182SThomas Petazzoni return 0; 4402c5aff182SThomas Petazzoni } 4403c5aff182SThomas Petazzoni 4404c5aff182SThomas Petazzoni /* platform glue : initialize decoding windows */ 440503ce758eSGreg KH static void mvneta_conf_mbus_windows(struct mvneta_port *pp, 4406c5aff182SThomas Petazzoni const struct mbus_dram_target_info *dram) 4407c5aff182SThomas Petazzoni { 4408c5aff182SThomas Petazzoni u32 win_enable; 4409c5aff182SThomas Petazzoni u32 win_protect; 4410c5aff182SThomas Petazzoni int i; 4411c5aff182SThomas Petazzoni 4412c5aff182SThomas Petazzoni for (i = 0; i < 6; i++) { 4413c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_WIN_BASE(i), 0); 4414c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_WIN_SIZE(i), 0); 4415c5aff182SThomas Petazzoni 4416c5aff182SThomas Petazzoni if (i < 4) 4417c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_WIN_REMAP(i), 0); 4418c5aff182SThomas Petazzoni } 4419c5aff182SThomas Petazzoni 4420c5aff182SThomas Petazzoni win_enable = 0x3f; 4421c5aff182SThomas Petazzoni win_protect = 0; 4422c5aff182SThomas Petazzoni 44232636ac3cSMarcin Wojtas if (dram) { 4424c5aff182SThomas Petazzoni for (i = 0; i < dram->num_cs; i++) { 4425c5aff182SThomas Petazzoni const struct mbus_dram_window *cs = dram->cs + i; 44262636ac3cSMarcin Wojtas 44272636ac3cSMarcin Wojtas mvreg_write(pp, MVNETA_WIN_BASE(i), 44282636ac3cSMarcin Wojtas (cs->base & 0xffff0000) | 44292636ac3cSMarcin Wojtas (cs->mbus_attr << 8) | 44302636ac3cSMarcin Wojtas dram->mbus_dram_target_id); 4431c5aff182SThomas Petazzoni 4432c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_WIN_SIZE(i), 4433c5aff182SThomas Petazzoni (cs->size - 1) & 0xffff0000); 4434c5aff182SThomas Petazzoni 4435c5aff182SThomas Petazzoni win_enable &= ~(1 << i); 4436c5aff182SThomas Petazzoni win_protect |= 3 << (2 * i); 4437c5aff182SThomas Petazzoni } 44382636ac3cSMarcin Wojtas } else { 44392636ac3cSMarcin Wojtas /* For Armada3700 open default 4GB Mbus window, leaving 44402636ac3cSMarcin Wojtas * arbitration of target/attribute to a different layer 44412636ac3cSMarcin Wojtas * of configuration. 44422636ac3cSMarcin Wojtas */ 44432636ac3cSMarcin Wojtas mvreg_write(pp, MVNETA_WIN_SIZE(0), 0xffff0000); 44442636ac3cSMarcin Wojtas win_enable &= ~BIT(0); 44452636ac3cSMarcin Wojtas win_protect = 3; 44462636ac3cSMarcin Wojtas } 4447c5aff182SThomas Petazzoni 4448c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_BASE_ADDR_ENABLE, win_enable); 4449db6ba9a5SMarcin Wojtas mvreg_write(pp, MVNETA_ACCESS_PROTECT_ENABLE, win_protect); 4450c5aff182SThomas Petazzoni } 4451c5aff182SThomas Petazzoni 4452c5aff182SThomas Petazzoni /* Power up the port */ 44533f1dd4bcSThomas Petazzoni static int mvneta_port_power_up(struct mvneta_port *pp, int phy_mode) 4454c5aff182SThomas Petazzoni { 4455c5aff182SThomas Petazzoni /* MAC Cause register should be cleared */ 4456c5aff182SThomas Petazzoni mvreg_write(pp, MVNETA_UNIT_INTR_CAUSE, 0); 4457c5aff182SThomas Petazzoni 445832699954SRussell King if (phy_mode == PHY_INTERFACE_MODE_QSGMII) 44593f1dd4bcSThomas Petazzoni mvreg_write(pp, MVNETA_SERDES_CFG, MVNETA_QSGMII_SERDES_PROTO); 446022f4bf8aSRussell King else if (phy_mode == PHY_INTERFACE_MODE_SGMII || 4461a10c1c81SRussell King phy_interface_mode_is_8023z(phy_mode)) 44623f1dd4bcSThomas Petazzoni mvreg_write(pp, MVNETA_SERDES_CFG, MVNETA_SGMII_SERDES_PROTO); 446332699954SRussell King else if (!phy_interface_mode_is_rgmii(phy_mode)) 44643f1dd4bcSThomas Petazzoni return -EINVAL; 44653f1dd4bcSThomas Petazzoni 44663f1dd4bcSThomas Petazzoni return 0; 4467c5aff182SThomas Petazzoni } 4468c5aff182SThomas Petazzoni 4469c5aff182SThomas Petazzoni /* Device initialization routine */ 447003ce758eSGreg KH static int mvneta_probe(struct platform_device *pdev) 4471c5aff182SThomas Petazzoni { 4472c5aff182SThomas Petazzoni struct device_node *dn = pdev->dev.of_node; 4473dc35a10fSMarcin Wojtas struct device_node *bm_node; 4474c5aff182SThomas Petazzoni struct mvneta_port *pp; 4475c5aff182SThomas Petazzoni struct net_device *dev; 4476503f9aa9SRussell King struct phylink *phylink; 4477a10c1c81SRussell King struct phy *comphy; 44788cc3e439SThomas Petazzoni const char *dt_mac_addr; 44798cc3e439SThomas Petazzoni char hw_mac_addr[ETH_ALEN]; 44808cc3e439SThomas Petazzoni const char *mac_from; 44819110ee07SMarcin Wojtas int tx_csum_limit; 4482c5aff182SThomas Petazzoni int phy_mode; 4483c5aff182SThomas Petazzoni int err; 448412bb03b4SMaxime Ripard int cpu; 4485c5aff182SThomas Petazzoni 4486a3ddd94fSRosen Penev dev = devm_alloc_etherdev_mqs(&pdev->dev, sizeof(struct mvneta_port), 4487a3ddd94fSRosen Penev txq_number, rxq_number); 4488c5aff182SThomas Petazzoni if (!dev) 4489c5aff182SThomas Petazzoni return -ENOMEM; 4490c5aff182SThomas Petazzoni 4491c5aff182SThomas Petazzoni dev->irq = irq_of_parse_and_map(dn, 0); 4492a3ddd94fSRosen Penev if (dev->irq == 0) 4493a3ddd94fSRosen Penev return -EINVAL; 4494c5aff182SThomas Petazzoni 4495c5aff182SThomas Petazzoni phy_mode = of_get_phy_mode(dn); 4496c5aff182SThomas Petazzoni if (phy_mode < 0) { 4497c5aff182SThomas Petazzoni dev_err(&pdev->dev, "incorrect phy-mode\n"); 4498c5aff182SThomas Petazzoni err = -EINVAL; 4499503f9aa9SRussell King goto err_free_irq; 4500503f9aa9SRussell King } 4501503f9aa9SRussell King 4502a10c1c81SRussell King comphy = devm_of_phy_get(&pdev->dev, dn, NULL); 4503a10c1c81SRussell King if (comphy == ERR_PTR(-EPROBE_DEFER)) { 4504a10c1c81SRussell King err = -EPROBE_DEFER; 4505a10c1c81SRussell King goto err_free_irq; 4506a10c1c81SRussell King } else if (IS_ERR(comphy)) { 4507a10c1c81SRussell King comphy = NULL; 4508a10c1c81SRussell King } 4509a10c1c81SRussell King 451044cc27e4SIoana Ciornei pp = netdev_priv(dev); 451144cc27e4SIoana Ciornei spin_lock_init(&pp->lock); 451244cc27e4SIoana Ciornei 451344cc27e4SIoana Ciornei pp->phylink_config.dev = &dev->dev; 451444cc27e4SIoana Ciornei pp->phylink_config.type = PHYLINK_NETDEV; 451544cc27e4SIoana Ciornei 451644cc27e4SIoana Ciornei phylink = phylink_create(&pp->phylink_config, pdev->dev.fwnode, 451744cc27e4SIoana Ciornei phy_mode, &mvneta_phylink_ops); 4518503f9aa9SRussell King if (IS_ERR(phylink)) { 4519503f9aa9SRussell King err = PTR_ERR(phylink); 4520503f9aa9SRussell King goto err_free_irq; 4521c5aff182SThomas Petazzoni } 4522c5aff182SThomas Petazzoni 4523c5aff182SThomas Petazzoni dev->tx_queue_len = MVNETA_MAX_TXD; 4524c5aff182SThomas Petazzoni dev->watchdog_timeo = 5 * HZ; 4525c5aff182SThomas Petazzoni dev->netdev_ops = &mvneta_netdev_ops; 4526c5aff182SThomas Petazzoni 45277ad24ea4SWilfried Klaebe dev->ethtool_ops = &mvneta_eth_tool_ops; 4528c5aff182SThomas Petazzoni 4529503f9aa9SRussell King pp->phylink = phylink; 4530a10c1c81SRussell King pp->comphy = comphy; 4531c5aff182SThomas Petazzoni pp->phy_interface = phy_mode; 4532503f9aa9SRussell King pp->dn = dn; 4533c5aff182SThomas Petazzoni 453490b74c01SGregory CLEMENT pp->rxq_def = rxq_def; 45359a401deaSGregory CLEMENT pp->indir[0] = rxq_def; 45369a401deaSGregory CLEMENT 45372636ac3cSMarcin Wojtas /* Get special SoC configurations */ 45382636ac3cSMarcin Wojtas if (of_device_is_compatible(dn, "marvell,armada-3700-neta")) 45392636ac3cSMarcin Wojtas pp->neta_armada3700 = true; 45402636ac3cSMarcin Wojtas 45412804ba4eSJisheng Zhang pp->clk = devm_clk_get(&pdev->dev, "core"); 45422804ba4eSJisheng Zhang if (IS_ERR(pp->clk)) 4543189dd626SThomas Petazzoni pp->clk = devm_clk_get(&pdev->dev, NULL); 4544189dd626SThomas Petazzoni if (IS_ERR(pp->clk)) { 4545189dd626SThomas Petazzoni err = PTR_ERR(pp->clk); 4546503f9aa9SRussell King goto err_free_phylink; 4547189dd626SThomas Petazzoni } 4548189dd626SThomas Petazzoni 4549189dd626SThomas Petazzoni clk_prepare_enable(pp->clk); 4550189dd626SThomas Petazzoni 455115cc4a4aSJisheng Zhang pp->clk_bus = devm_clk_get(&pdev->dev, "bus"); 455215cc4a4aSJisheng Zhang if (!IS_ERR(pp->clk_bus)) 455315cc4a4aSJisheng Zhang clk_prepare_enable(pp->clk_bus); 455415cc4a4aSJisheng Zhang 455500c33afbSJisheng Zhang pp->base = devm_platform_ioremap_resource(pdev, 0); 4556c3f0dd38SThomas Petazzoni if (IS_ERR(pp->base)) { 4557c3f0dd38SThomas Petazzoni err = PTR_ERR(pp->base); 45585445eaf3SArnaud Patard \(Rtp\) goto err_clk; 45595445eaf3SArnaud Patard \(Rtp\) } 45605445eaf3SArnaud Patard \(Rtp\) 456112bb03b4SMaxime Ripard /* Alloc per-cpu port structure */ 456212bb03b4SMaxime Ripard pp->ports = alloc_percpu(struct mvneta_pcpu_port); 456312bb03b4SMaxime Ripard if (!pp->ports) { 456412bb03b4SMaxime Ripard err = -ENOMEM; 456512bb03b4SMaxime Ripard goto err_clk; 456612bb03b4SMaxime Ripard } 456712bb03b4SMaxime Ripard 456874c41b04Swilly tarreau /* Alloc per-cpu stats */ 45691c213bd2SWANG Cong pp->stats = netdev_alloc_pcpu_stats(struct mvneta_pcpu_stats); 457074c41b04Swilly tarreau if (!pp->stats) { 457174c41b04Swilly tarreau err = -ENOMEM; 457212bb03b4SMaxime Ripard goto err_free_ports; 457374c41b04Swilly tarreau } 457474c41b04Swilly tarreau 45758cc3e439SThomas Petazzoni dt_mac_addr = of_get_mac_address(dn); 4576a51645f7SPetr Štetiar if (!IS_ERR(dt_mac_addr)) { 45778cc3e439SThomas Petazzoni mac_from = "device tree"; 45782d2924afSPetr Štetiar ether_addr_copy(dev->dev_addr, dt_mac_addr); 45798cc3e439SThomas Petazzoni } else { 45808cc3e439SThomas Petazzoni mvneta_get_mac_addr(pp, hw_mac_addr); 45818cc3e439SThomas Petazzoni if (is_valid_ether_addr(hw_mac_addr)) { 45828cc3e439SThomas Petazzoni mac_from = "hardware"; 45838cc3e439SThomas Petazzoni memcpy(dev->dev_addr, hw_mac_addr, ETH_ALEN); 45848cc3e439SThomas Petazzoni } else { 45858cc3e439SThomas Petazzoni mac_from = "random"; 45868cc3e439SThomas Petazzoni eth_hw_addr_random(dev); 45878cc3e439SThomas Petazzoni } 45888cc3e439SThomas Petazzoni } 45898cc3e439SThomas Petazzoni 45909110ee07SMarcin Wojtas if (!of_property_read_u32(dn, "tx-csum-limit", &tx_csum_limit)) { 45919110ee07SMarcin Wojtas if (tx_csum_limit < 0 || 45929110ee07SMarcin Wojtas tx_csum_limit > MVNETA_TX_CSUM_MAX_SIZE) { 45939110ee07SMarcin Wojtas tx_csum_limit = MVNETA_TX_CSUM_DEF_SIZE; 45949110ee07SMarcin Wojtas dev_info(&pdev->dev, 45959110ee07SMarcin Wojtas "Wrong TX csum limit in DT, set to %dB\n", 45969110ee07SMarcin Wojtas MVNETA_TX_CSUM_DEF_SIZE); 45979110ee07SMarcin Wojtas } 45989110ee07SMarcin Wojtas } else if (of_device_is_compatible(dn, "marvell,armada-370-neta")) { 45999110ee07SMarcin Wojtas tx_csum_limit = MVNETA_TX_CSUM_DEF_SIZE; 46009110ee07SMarcin Wojtas } else { 46019110ee07SMarcin Wojtas tx_csum_limit = MVNETA_TX_CSUM_MAX_SIZE; 46029110ee07SMarcin Wojtas } 46039110ee07SMarcin Wojtas 46049110ee07SMarcin Wojtas pp->tx_csum_limit = tx_csum_limit; 4605b65657fcSSimon Guinot 46069768b45cSJane Li pp->dram_target_info = mv_mbus_dram_info(); 46072636ac3cSMarcin Wojtas /* Armada3700 requires setting default configuration of Mbus 46082636ac3cSMarcin Wojtas * windows, however without using filled mbus_dram_target_info 46092636ac3cSMarcin Wojtas * structure. 46102636ac3cSMarcin Wojtas */ 46119768b45cSJane Li if (pp->dram_target_info || pp->neta_armada3700) 46129768b45cSJane Li mvneta_conf_mbus_windows(pp, pp->dram_target_info); 4613dc35a10fSMarcin Wojtas 4614c5aff182SThomas Petazzoni pp->tx_ring_size = MVNETA_MAX_TXD; 4615c5aff182SThomas Petazzoni pp->rx_ring_size = MVNETA_MAX_RXD; 4616c5aff182SThomas Petazzoni 4617c5aff182SThomas Petazzoni pp->dev = dev; 4618c5aff182SThomas Petazzoni SET_NETDEV_DEV(dev, &pdev->dev); 4619c5aff182SThomas Petazzoni 4620dc35a10fSMarcin Wojtas pp->id = global_port_id++; 4621562e2f46SYelena Krivosheev pp->rx_offset_correction = 0; /* not relevant for SW BM */ 4622dc35a10fSMarcin Wojtas 4623dc35a10fSMarcin Wojtas /* Obtain access to BM resources if enabled and already initialized */ 4624dc35a10fSMarcin Wojtas bm_node = of_parse_phandle(dn, "buffer-manager", 0); 4625965cbbecSGregory CLEMENT if (bm_node) { 4626965cbbecSGregory CLEMENT pp->bm_priv = mvneta_bm_get(bm_node); 4627965cbbecSGregory CLEMENT if (pp->bm_priv) { 4628dc35a10fSMarcin Wojtas err = mvneta_bm_port_init(pdev, pp); 4629dc35a10fSMarcin Wojtas if (err < 0) { 4630965cbbecSGregory CLEMENT dev_info(&pdev->dev, 4631965cbbecSGregory CLEMENT "use SW buffer management\n"); 4632965cbbecSGregory CLEMENT mvneta_bm_put(pp->bm_priv); 4633dc35a10fSMarcin Wojtas pp->bm_priv = NULL; 4634dc35a10fSMarcin Wojtas } 4635dc35a10fSMarcin Wojtas } 4636562e2f46SYelena Krivosheev /* Set RX packet offset correction for platforms, whose 4637562e2f46SYelena Krivosheev * NET_SKB_PAD, exceeds 64B. It should be 64B for 64-bit 4638562e2f46SYelena Krivosheev * platforms and 0B for 32-bit ones. 4639562e2f46SYelena Krivosheev */ 4640562e2f46SYelena Krivosheev pp->rx_offset_correction = max(0, 4641562e2f46SYelena Krivosheev NET_SKB_PAD - 4642562e2f46SYelena Krivosheev MVNETA_RX_PKT_OFFSET_CORRECTION); 4643965cbbecSGregory CLEMENT } 4644d4e4da00SPeter Chen of_node_put(bm_node); 4645dc35a10fSMarcin Wojtas 46469672850bSEzequiel Garcia err = mvneta_init(&pdev->dev, pp); 46479672850bSEzequiel Garcia if (err < 0) 4648dc35a10fSMarcin Wojtas goto err_netdev; 46493f1dd4bcSThomas Petazzoni 46503f1dd4bcSThomas Petazzoni err = mvneta_port_power_up(pp, phy_mode); 46513f1dd4bcSThomas Petazzoni if (err < 0) { 46523f1dd4bcSThomas Petazzoni dev_err(&pdev->dev, "can't power up port\n"); 4653dc35a10fSMarcin Wojtas goto err_netdev; 46543f1dd4bcSThomas Petazzoni } 4655c5aff182SThomas Petazzoni 46562636ac3cSMarcin Wojtas /* Armada3700 network controller does not support per-cpu 46572636ac3cSMarcin Wojtas * operation, so only single NAPI should be initialized. 46582636ac3cSMarcin Wojtas */ 46592636ac3cSMarcin Wojtas if (pp->neta_armada3700) { 46602636ac3cSMarcin Wojtas netif_napi_add(dev, &pp->napi, mvneta_poll, NAPI_POLL_WEIGHT); 46612636ac3cSMarcin Wojtas } else { 466212bb03b4SMaxime Ripard for_each_present_cpu(cpu) { 46632636ac3cSMarcin Wojtas struct mvneta_pcpu_port *port = 46642636ac3cSMarcin Wojtas per_cpu_ptr(pp->ports, cpu); 466512bb03b4SMaxime Ripard 46662636ac3cSMarcin Wojtas netif_napi_add(dev, &port->napi, mvneta_poll, 46672636ac3cSMarcin Wojtas NAPI_POLL_WEIGHT); 466812bb03b4SMaxime Ripard port->pp = pp; 466912bb03b4SMaxime Ripard } 46702636ac3cSMarcin Wojtas } 4671c5aff182SThomas Petazzoni 46727772988aSJisheng Zhang dev->features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | 46737772988aSJisheng Zhang NETIF_F_TSO | NETIF_F_RXCSUM; 467401ef26caSEzequiel Garcia dev->hw_features |= dev->features; 467501ef26caSEzequiel Garcia dev->vlan_features |= dev->features; 467697db8afaSAndrew Lunn dev->priv_flags |= IFF_LIVE_ADDR_CHANGE; 46778eef5f97SEzequiel Garcia dev->gso_max_segs = MVNETA_MAX_TSO_SEGS; 4678b50b72deSwilly tarreau 46795777987eSJarod Wilson /* MTU range: 68 - 9676 */ 46805777987eSJarod Wilson dev->min_mtu = ETH_MIN_MTU; 46815777987eSJarod Wilson /* 9676 == 9700 - 20 and rounding to 8 */ 46825777987eSJarod Wilson dev->max_mtu = 9676; 46835777987eSJarod Wilson 4684c5aff182SThomas Petazzoni err = register_netdev(dev); 4685c5aff182SThomas Petazzoni if (err < 0) { 4686c5aff182SThomas Petazzoni dev_err(&pdev->dev, "failed to register\n"); 4687d484e06eSJisheng Zhang goto err_netdev; 4688c5aff182SThomas Petazzoni } 4689c5aff182SThomas Petazzoni 46908cc3e439SThomas Petazzoni netdev_info(dev, "Using %s mac address %pM\n", mac_from, 46918cc3e439SThomas Petazzoni dev->dev_addr); 4692c5aff182SThomas Petazzoni 4693c5aff182SThomas Petazzoni platform_set_drvdata(pdev, pp->dev); 4694c5aff182SThomas Petazzoni 4695c5aff182SThomas Petazzoni return 0; 4696c5aff182SThomas Petazzoni 4697dc35a10fSMarcin Wojtas err_netdev: 4698dc35a10fSMarcin Wojtas if (pp->bm_priv) { 4699dc35a10fSMarcin Wojtas mvneta_bm_pool_destroy(pp->bm_priv, pp->pool_long, 1 << pp->id); 4700dc35a10fSMarcin Wojtas mvneta_bm_pool_destroy(pp->bm_priv, pp->pool_short, 4701dc35a10fSMarcin Wojtas 1 << pp->id); 4702965cbbecSGregory CLEMENT mvneta_bm_put(pp->bm_priv); 4703dc35a10fSMarcin Wojtas } 470474c41b04Swilly tarreau free_percpu(pp->stats); 470512bb03b4SMaxime Ripard err_free_ports: 470612bb03b4SMaxime Ripard free_percpu(pp->ports); 47075445eaf3SArnaud Patard \(Rtp\) err_clk: 470815cc4a4aSJisheng Zhang clk_disable_unprepare(pp->clk_bus); 47095445eaf3SArnaud Patard \(Rtp\) clk_disable_unprepare(pp->clk); 4710503f9aa9SRussell King err_free_phylink: 4711503f9aa9SRussell King if (pp->phylink) 4712503f9aa9SRussell King phylink_destroy(pp->phylink); 4713c5aff182SThomas Petazzoni err_free_irq: 4714c5aff182SThomas Petazzoni irq_dispose_mapping(dev->irq); 4715c5aff182SThomas Petazzoni return err; 4716c5aff182SThomas Petazzoni } 4717c5aff182SThomas Petazzoni 4718c5aff182SThomas Petazzoni /* Device removal routine */ 471903ce758eSGreg KH static int mvneta_remove(struct platform_device *pdev) 4720c5aff182SThomas Petazzoni { 4721c5aff182SThomas Petazzoni struct net_device *dev = platform_get_drvdata(pdev); 4722c5aff182SThomas Petazzoni struct mvneta_port *pp = netdev_priv(dev); 4723c5aff182SThomas Petazzoni 4724c5aff182SThomas Petazzoni unregister_netdev(dev); 472515cc4a4aSJisheng Zhang clk_disable_unprepare(pp->clk_bus); 4726189dd626SThomas Petazzoni clk_disable_unprepare(pp->clk); 472712bb03b4SMaxime Ripard free_percpu(pp->ports); 472874c41b04Swilly tarreau free_percpu(pp->stats); 4729c5aff182SThomas Petazzoni irq_dispose_mapping(dev->irq); 4730503f9aa9SRussell King phylink_destroy(pp->phylink); 4731c5aff182SThomas Petazzoni 4732dc35a10fSMarcin Wojtas if (pp->bm_priv) { 4733dc35a10fSMarcin Wojtas mvneta_bm_pool_destroy(pp->bm_priv, pp->pool_long, 1 << pp->id); 4734dc35a10fSMarcin Wojtas mvneta_bm_pool_destroy(pp->bm_priv, pp->pool_short, 4735dc35a10fSMarcin Wojtas 1 << pp->id); 4736965cbbecSGregory CLEMENT mvneta_bm_put(pp->bm_priv); 4737dc35a10fSMarcin Wojtas } 4738dc35a10fSMarcin Wojtas 4739c5aff182SThomas Petazzoni return 0; 4740c5aff182SThomas Petazzoni } 4741c5aff182SThomas Petazzoni 47429768b45cSJane Li #ifdef CONFIG_PM_SLEEP 47439768b45cSJane Li static int mvneta_suspend(struct device *device) 47449768b45cSJane Li { 47451799cdd2SJisheng Zhang int queue; 47469768b45cSJane Li struct net_device *dev = dev_get_drvdata(device); 47479768b45cSJane Li struct mvneta_port *pp = netdev_priv(dev); 47489768b45cSJane Li 47491799cdd2SJisheng Zhang if (!netif_running(dev)) 47501799cdd2SJisheng Zhang goto clean_exit; 47511799cdd2SJisheng Zhang 47521799cdd2SJisheng Zhang if (!pp->neta_armada3700) { 47531799cdd2SJisheng Zhang spin_lock(&pp->lock); 47541799cdd2SJisheng Zhang pp->is_stopped = true; 47551799cdd2SJisheng Zhang spin_unlock(&pp->lock); 47561799cdd2SJisheng Zhang 47571799cdd2SJisheng Zhang cpuhp_state_remove_instance_nocalls(online_hpstate, 47581799cdd2SJisheng Zhang &pp->node_online); 47591799cdd2SJisheng Zhang cpuhp_state_remove_instance_nocalls(CPUHP_NET_MVNETA_DEAD, 47601799cdd2SJisheng Zhang &pp->node_dead); 47611799cdd2SJisheng Zhang } 47621799cdd2SJisheng Zhang 47633b8bc674SRussell King rtnl_lock(); 47641799cdd2SJisheng Zhang mvneta_stop_dev(pp); 47653b8bc674SRussell King rtnl_unlock(); 47661799cdd2SJisheng Zhang 47671799cdd2SJisheng Zhang for (queue = 0; queue < rxq_number; queue++) { 47681799cdd2SJisheng Zhang struct mvneta_rx_queue *rxq = &pp->rxqs[queue]; 47691799cdd2SJisheng Zhang 47701799cdd2SJisheng Zhang mvneta_rxq_drop_pkts(pp, rxq); 47711799cdd2SJisheng Zhang } 47721799cdd2SJisheng Zhang 47731799cdd2SJisheng Zhang for (queue = 0; queue < txq_number; queue++) { 47741799cdd2SJisheng Zhang struct mvneta_tx_queue *txq = &pp->txqs[queue]; 47751799cdd2SJisheng Zhang 47761799cdd2SJisheng Zhang mvneta_txq_hw_deinit(pp, txq); 47771799cdd2SJisheng Zhang } 47781799cdd2SJisheng Zhang 47791799cdd2SJisheng Zhang clean_exit: 47809768b45cSJane Li netif_device_detach(dev); 47819768b45cSJane Li clk_disable_unprepare(pp->clk_bus); 47829768b45cSJane Li clk_disable_unprepare(pp->clk); 47831799cdd2SJisheng Zhang 47849768b45cSJane Li return 0; 47859768b45cSJane Li } 47869768b45cSJane Li 47879768b45cSJane Li static int mvneta_resume(struct device *device) 47889768b45cSJane Li { 47899768b45cSJane Li struct platform_device *pdev = to_platform_device(device); 47909768b45cSJane Li struct net_device *dev = dev_get_drvdata(device); 47919768b45cSJane Li struct mvneta_port *pp = netdev_priv(dev); 47921799cdd2SJisheng Zhang int err, queue; 47939768b45cSJane Li 47949768b45cSJane Li clk_prepare_enable(pp->clk); 47959768b45cSJane Li if (!IS_ERR(pp->clk_bus)) 47969768b45cSJane Li clk_prepare_enable(pp->clk_bus); 47979768b45cSJane Li if (pp->dram_target_info || pp->neta_armada3700) 47989768b45cSJane Li mvneta_conf_mbus_windows(pp, pp->dram_target_info); 47999768b45cSJane Li if (pp->bm_priv) { 48009768b45cSJane Li err = mvneta_bm_port_init(pdev, pp); 48019768b45cSJane Li if (err < 0) { 48029768b45cSJane Li dev_info(&pdev->dev, "use SW buffer management\n"); 48039768b45cSJane Li pp->bm_priv = NULL; 48049768b45cSJane Li } 48059768b45cSJane Li } 48069768b45cSJane Li mvneta_defaults_set(pp); 48079768b45cSJane Li err = mvneta_port_power_up(pp, pp->phy_interface); 48089768b45cSJane Li if (err < 0) { 48099768b45cSJane Li dev_err(device, "can't power up port\n"); 48109768b45cSJane Li return err; 48119768b45cSJane Li } 48129768b45cSJane Li 48139768b45cSJane Li netif_device_attach(dev); 48141799cdd2SJisheng Zhang 48151799cdd2SJisheng Zhang if (!netif_running(dev)) 48161799cdd2SJisheng Zhang return 0; 48171799cdd2SJisheng Zhang 48181799cdd2SJisheng Zhang for (queue = 0; queue < rxq_number; queue++) { 48191799cdd2SJisheng Zhang struct mvneta_rx_queue *rxq = &pp->rxqs[queue]; 48201799cdd2SJisheng Zhang 48211799cdd2SJisheng Zhang rxq->next_desc_to_proc = 0; 48221799cdd2SJisheng Zhang mvneta_rxq_hw_init(pp, rxq); 4823d6956ac8SJisheng Zhang } 48241799cdd2SJisheng Zhang 48251799cdd2SJisheng Zhang for (queue = 0; queue < txq_number; queue++) { 48261799cdd2SJisheng Zhang struct mvneta_tx_queue *txq = &pp->txqs[queue]; 48271799cdd2SJisheng Zhang 48281799cdd2SJisheng Zhang txq->next_desc_to_proc = 0; 48291799cdd2SJisheng Zhang mvneta_txq_hw_init(pp, txq); 48301799cdd2SJisheng Zhang } 48311799cdd2SJisheng Zhang 48321799cdd2SJisheng Zhang if (!pp->neta_armada3700) { 48331799cdd2SJisheng Zhang spin_lock(&pp->lock); 48341799cdd2SJisheng Zhang pp->is_stopped = false; 48351799cdd2SJisheng Zhang spin_unlock(&pp->lock); 48361799cdd2SJisheng Zhang cpuhp_state_add_instance_nocalls(online_hpstate, 48371799cdd2SJisheng Zhang &pp->node_online); 48381799cdd2SJisheng Zhang cpuhp_state_add_instance_nocalls(CPUHP_NET_MVNETA_DEAD, 48391799cdd2SJisheng Zhang &pp->node_dead); 48401799cdd2SJisheng Zhang } 48411799cdd2SJisheng Zhang 48421799cdd2SJisheng Zhang rtnl_lock(); 48431799cdd2SJisheng Zhang mvneta_start_dev(pp); 48443b8bc674SRussell King rtnl_unlock(); 48451799cdd2SJisheng Zhang mvneta_set_rx_mode(dev); 4846d6956ac8SJisheng Zhang 48479768b45cSJane Li return 0; 48489768b45cSJane Li } 48499768b45cSJane Li #endif 48509768b45cSJane Li 48519768b45cSJane Li static SIMPLE_DEV_PM_OPS(mvneta_pm_ops, mvneta_suspend, mvneta_resume); 48529768b45cSJane Li 4853c5aff182SThomas Petazzoni static const struct of_device_id mvneta_match[] = { 4854c5aff182SThomas Petazzoni { .compatible = "marvell,armada-370-neta" }, 4855f522a975SSimon Guinot { .compatible = "marvell,armada-xp-neta" }, 48562636ac3cSMarcin Wojtas { .compatible = "marvell,armada-3700-neta" }, 4857c5aff182SThomas Petazzoni { } 4858c5aff182SThomas Petazzoni }; 4859c5aff182SThomas Petazzoni MODULE_DEVICE_TABLE(of, mvneta_match); 4860c5aff182SThomas Petazzoni 4861c5aff182SThomas Petazzoni static struct platform_driver mvneta_driver = { 4862c5aff182SThomas Petazzoni .probe = mvneta_probe, 486303ce758eSGreg KH .remove = mvneta_remove, 4864c5aff182SThomas Petazzoni .driver = { 4865c5aff182SThomas Petazzoni .name = MVNETA_DRIVER_NAME, 4866c5aff182SThomas Petazzoni .of_match_table = mvneta_match, 48679768b45cSJane Li .pm = &mvneta_pm_ops, 4868c5aff182SThomas Petazzoni }, 4869c5aff182SThomas Petazzoni }; 4870c5aff182SThomas Petazzoni 487184a3f4dbSSebastian Andrzej Siewior static int __init mvneta_driver_init(void) 487284a3f4dbSSebastian Andrzej Siewior { 487384a3f4dbSSebastian Andrzej Siewior int ret; 487484a3f4dbSSebastian Andrzej Siewior 487584a3f4dbSSebastian Andrzej Siewior ret = cpuhp_setup_state_multi(CPUHP_AP_ONLINE_DYN, "net/mvmeta:online", 487684a3f4dbSSebastian Andrzej Siewior mvneta_cpu_online, 487784a3f4dbSSebastian Andrzej Siewior mvneta_cpu_down_prepare); 487884a3f4dbSSebastian Andrzej Siewior if (ret < 0) 487984a3f4dbSSebastian Andrzej Siewior goto out; 488084a3f4dbSSebastian Andrzej Siewior online_hpstate = ret; 488184a3f4dbSSebastian Andrzej Siewior ret = cpuhp_setup_state_multi(CPUHP_NET_MVNETA_DEAD, "net/mvneta:dead", 488284a3f4dbSSebastian Andrzej Siewior NULL, mvneta_cpu_dead); 488384a3f4dbSSebastian Andrzej Siewior if (ret) 488484a3f4dbSSebastian Andrzej Siewior goto err_dead; 488584a3f4dbSSebastian Andrzej Siewior 488684a3f4dbSSebastian Andrzej Siewior ret = platform_driver_register(&mvneta_driver); 488784a3f4dbSSebastian Andrzej Siewior if (ret) 488884a3f4dbSSebastian Andrzej Siewior goto err; 488984a3f4dbSSebastian Andrzej Siewior return 0; 489084a3f4dbSSebastian Andrzej Siewior 489184a3f4dbSSebastian Andrzej Siewior err: 489284a3f4dbSSebastian Andrzej Siewior cpuhp_remove_multi_state(CPUHP_NET_MVNETA_DEAD); 489384a3f4dbSSebastian Andrzej Siewior err_dead: 489484a3f4dbSSebastian Andrzej Siewior cpuhp_remove_multi_state(online_hpstate); 489584a3f4dbSSebastian Andrzej Siewior out: 489684a3f4dbSSebastian Andrzej Siewior return ret; 489784a3f4dbSSebastian Andrzej Siewior } 489884a3f4dbSSebastian Andrzej Siewior module_init(mvneta_driver_init); 489984a3f4dbSSebastian Andrzej Siewior 490084a3f4dbSSebastian Andrzej Siewior static void __exit mvneta_driver_exit(void) 490184a3f4dbSSebastian Andrzej Siewior { 490284a3f4dbSSebastian Andrzej Siewior platform_driver_unregister(&mvneta_driver); 490384a3f4dbSSebastian Andrzej Siewior cpuhp_remove_multi_state(CPUHP_NET_MVNETA_DEAD); 490484a3f4dbSSebastian Andrzej Siewior cpuhp_remove_multi_state(online_hpstate); 490584a3f4dbSSebastian Andrzej Siewior } 490684a3f4dbSSebastian Andrzej Siewior module_exit(mvneta_driver_exit); 4907c5aff182SThomas Petazzoni 4908c5aff182SThomas Petazzoni MODULE_DESCRIPTION("Marvell NETA Ethernet Driver - www.marvell.com"); 4909c5aff182SThomas Petazzoni MODULE_AUTHOR("Rami Rosen <rosenr@marvell.com>, Thomas Petazzoni <thomas.petazzoni@free-electrons.com>"); 4910c5aff182SThomas Petazzoni MODULE_LICENSE("GPL"); 4911c5aff182SThomas Petazzoni 4912d3757ba4SJoe Perches module_param(rxq_number, int, 0444); 4913d3757ba4SJoe Perches module_param(txq_number, int, 0444); 4914c5aff182SThomas Petazzoni 4915d3757ba4SJoe Perches module_param(rxq_def, int, 0444); 4916d3757ba4SJoe Perches module_param(rx_copybreak, int, 0644); 4917