1 /* 2 * Driver for Marvell Discovery (MV643XX) and Marvell Orion ethernet ports 3 * Copyright (C) 2002 Matthew Dharm <mdharm@momenco.com> 4 * 5 * Based on the 64360 driver from: 6 * Copyright (C) 2002 Rabeeh Khoury <rabeeh@galileo.co.il> 7 * Rabeeh Khoury <rabeeh@marvell.com> 8 * 9 * Copyright (C) 2003 PMC-Sierra, Inc., 10 * written by Manish Lachwani 11 * 12 * Copyright (C) 2003 Ralf Baechle <ralf@linux-mips.org> 13 * 14 * Copyright (C) 2004-2006 MontaVista Software, Inc. 15 * Dale Farnsworth <dale@farnsworth.org> 16 * 17 * Copyright (C) 2004 Steven J. Hill <sjhill1@rockwellcollins.com> 18 * <sjhill@realitydiluted.com> 19 * 20 * Copyright (C) 2007-2008 Marvell Semiconductor 21 * Lennert Buytenhek <buytenh@marvell.com> 22 * 23 * Copyright (C) 2013 Michael Stapelberg <michael@stapelberg.de> 24 * 25 * This program is free software; you can redistribute it and/or 26 * modify it under the terms of the GNU General Public License 27 * as published by the Free Software Foundation; either version 2 28 * of the License, or (at your option) any later version. 29 * 30 * This program is distributed in the hope that it will be useful, 31 * but WITHOUT ANY WARRANTY; without even the implied warranty of 32 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 33 * GNU General Public License for more details. 34 * 35 * You should have received a copy of the GNU General Public License 36 * along with this program; if not, see <http://www.gnu.org/licenses/>. 37 */ 38 39 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 40 41 #include <linux/init.h> 42 #include <linux/dma-mapping.h> 43 #include <linux/in.h> 44 #include <linux/ip.h> 45 #include <net/tso.h> 46 #include <linux/tcp.h> 47 #include <linux/udp.h> 48 #include <linux/etherdevice.h> 49 #include <linux/delay.h> 50 #include <linux/ethtool.h> 51 #include <linux/platform_device.h> 52 #include <linux/module.h> 53 #include <linux/kernel.h> 54 #include <linux/spinlock.h> 55 #include <linux/workqueue.h> 56 #include <linux/phy.h> 57 #include <linux/mv643xx_eth.h> 58 #include <linux/io.h> 59 #include <linux/interrupt.h> 60 #include <linux/types.h> 61 #include <linux/slab.h> 62 #include <linux/clk.h> 63 #include <linux/of.h> 64 #include <linux/of_irq.h> 65 #include <linux/of_net.h> 66 #include <linux/of_mdio.h> 67 68 static char mv643xx_eth_driver_name[] = "mv643xx_eth"; 69 static char mv643xx_eth_driver_version[] = "1.4"; 70 71 72 /* 73 * Registers shared between all ports. 74 */ 75 #define PHY_ADDR 0x0000 76 #define WINDOW_BASE(w) (0x0200 + ((w) << 3)) 77 #define WINDOW_SIZE(w) (0x0204 + ((w) << 3)) 78 #define WINDOW_REMAP_HIGH(w) (0x0280 + ((w) << 2)) 79 #define WINDOW_BAR_ENABLE 0x0290 80 #define WINDOW_PROTECT(w) (0x0294 + ((w) << 4)) 81 82 /* 83 * Main per-port registers. These live at offset 0x0400 for 84 * port #0, 0x0800 for port #1, and 0x0c00 for port #2. 85 */ 86 #define PORT_CONFIG 0x0000 87 #define UNICAST_PROMISCUOUS_MODE 0x00000001 88 #define PORT_CONFIG_EXT 0x0004 89 #define MAC_ADDR_LOW 0x0014 90 #define MAC_ADDR_HIGH 0x0018 91 #define SDMA_CONFIG 0x001c 92 #define TX_BURST_SIZE_16_64BIT 0x01000000 93 #define TX_BURST_SIZE_4_64BIT 0x00800000 94 #define BLM_TX_NO_SWAP 0x00000020 95 #define BLM_RX_NO_SWAP 0x00000010 96 #define RX_BURST_SIZE_16_64BIT 0x00000008 97 #define RX_BURST_SIZE_4_64BIT 0x00000004 98 #define PORT_SERIAL_CONTROL 0x003c 99 #define SET_MII_SPEED_TO_100 0x01000000 100 #define SET_GMII_SPEED_TO_1000 0x00800000 101 #define SET_FULL_DUPLEX_MODE 0x00200000 102 #define MAX_RX_PACKET_9700BYTE 0x000a0000 103 #define DISABLE_AUTO_NEG_SPEED_GMII 0x00002000 104 #define DO_NOT_FORCE_LINK_FAIL 0x00000400 105 #define SERIAL_PORT_CONTROL_RESERVED 0x00000200 106 #define DISABLE_AUTO_NEG_FOR_FLOW_CTRL 0x00000008 107 #define DISABLE_AUTO_NEG_FOR_DUPLEX 0x00000004 108 #define FORCE_LINK_PASS 0x00000002 109 #define SERIAL_PORT_ENABLE 0x00000001 110 #define PORT_STATUS 0x0044 111 #define TX_FIFO_EMPTY 0x00000400 112 #define TX_IN_PROGRESS 0x00000080 113 #define PORT_SPEED_MASK 0x00000030 114 #define PORT_SPEED_1000 0x00000010 115 #define PORT_SPEED_100 0x00000020 116 #define PORT_SPEED_10 0x00000000 117 #define FLOW_CONTROL_ENABLED 0x00000008 118 #define FULL_DUPLEX 0x00000004 119 #define LINK_UP 0x00000002 120 #define TXQ_COMMAND 0x0048 121 #define TXQ_FIX_PRIO_CONF 0x004c 122 #define PORT_SERIAL_CONTROL1 0x004c 123 #define CLK125_BYPASS_EN 0x00000010 124 #define TX_BW_RATE 0x0050 125 #define TX_BW_MTU 0x0058 126 #define TX_BW_BURST 0x005c 127 #define INT_CAUSE 0x0060 128 #define INT_TX_END 0x07f80000 129 #define INT_TX_END_0 0x00080000 130 #define INT_RX 0x000003fc 131 #define INT_RX_0 0x00000004 132 #define INT_EXT 0x00000002 133 #define INT_CAUSE_EXT 0x0064 134 #define INT_EXT_LINK_PHY 0x00110000 135 #define INT_EXT_TX 0x000000ff 136 #define INT_MASK 0x0068 137 #define INT_MASK_EXT 0x006c 138 #define TX_FIFO_URGENT_THRESHOLD 0x0074 139 #define RX_DISCARD_FRAME_CNT 0x0084 140 #define RX_OVERRUN_FRAME_CNT 0x0088 141 #define TXQ_FIX_PRIO_CONF_MOVED 0x00dc 142 #define TX_BW_RATE_MOVED 0x00e0 143 #define TX_BW_MTU_MOVED 0x00e8 144 #define TX_BW_BURST_MOVED 0x00ec 145 #define RXQ_CURRENT_DESC_PTR(q) (0x020c + ((q) << 4)) 146 #define RXQ_COMMAND 0x0280 147 #define TXQ_CURRENT_DESC_PTR(q) (0x02c0 + ((q) << 2)) 148 #define TXQ_BW_TOKENS(q) (0x0300 + ((q) << 4)) 149 #define TXQ_BW_CONF(q) (0x0304 + ((q) << 4)) 150 #define TXQ_BW_WRR_CONF(q) (0x0308 + ((q) << 4)) 151 152 /* 153 * Misc per-port registers. 154 */ 155 #define MIB_COUNTERS(p) (0x1000 + ((p) << 7)) 156 #define SPECIAL_MCAST_TABLE(p) (0x1400 + ((p) << 10)) 157 #define OTHER_MCAST_TABLE(p) (0x1500 + ((p) << 10)) 158 #define UNICAST_TABLE(p) (0x1600 + ((p) << 10)) 159 160 161 /* 162 * SDMA configuration register default value. 163 */ 164 #if defined(__BIG_ENDIAN) 165 #define PORT_SDMA_CONFIG_DEFAULT_VALUE \ 166 (RX_BURST_SIZE_4_64BIT | \ 167 TX_BURST_SIZE_4_64BIT) 168 #elif defined(__LITTLE_ENDIAN) 169 #define PORT_SDMA_CONFIG_DEFAULT_VALUE \ 170 (RX_BURST_SIZE_4_64BIT | \ 171 BLM_RX_NO_SWAP | \ 172 BLM_TX_NO_SWAP | \ 173 TX_BURST_SIZE_4_64BIT) 174 #else 175 #error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined 176 #endif 177 178 179 /* 180 * Misc definitions. 181 */ 182 #define DEFAULT_RX_QUEUE_SIZE 128 183 #define DEFAULT_TX_QUEUE_SIZE 512 184 #define SKB_DMA_REALIGN ((PAGE_SIZE - NET_SKB_PAD) % SMP_CACHE_BYTES) 185 186 #define TSO_HEADER_SIZE 128 187 188 /* Max number of allowed TCP segments for software TSO */ 189 #define MV643XX_MAX_TSO_SEGS 100 190 #define MV643XX_MAX_SKB_DESCS (MV643XX_MAX_TSO_SEGS * 2 + MAX_SKB_FRAGS) 191 192 #define IS_TSO_HEADER(txq, addr) \ 193 ((addr >= txq->tso_hdrs_dma) && \ 194 (addr < txq->tso_hdrs_dma + txq->tx_ring_size * TSO_HEADER_SIZE)) 195 196 #define DESC_DMA_MAP_SINGLE 0 197 #define DESC_DMA_MAP_PAGE 1 198 199 /* 200 * RX/TX descriptors. 201 */ 202 #if defined(__BIG_ENDIAN) 203 struct rx_desc { 204 u16 byte_cnt; /* Descriptor buffer byte count */ 205 u16 buf_size; /* Buffer size */ 206 u32 cmd_sts; /* Descriptor command status */ 207 u32 next_desc_ptr; /* Next descriptor pointer */ 208 u32 buf_ptr; /* Descriptor buffer pointer */ 209 }; 210 211 struct tx_desc { 212 u16 byte_cnt; /* buffer byte count */ 213 u16 l4i_chk; /* CPU provided TCP checksum */ 214 u32 cmd_sts; /* Command/status field */ 215 u32 next_desc_ptr; /* Pointer to next descriptor */ 216 u32 buf_ptr; /* pointer to buffer for this descriptor*/ 217 }; 218 #elif defined(__LITTLE_ENDIAN) 219 struct rx_desc { 220 u32 cmd_sts; /* Descriptor command status */ 221 u16 buf_size; /* Buffer size */ 222 u16 byte_cnt; /* Descriptor buffer byte count */ 223 u32 buf_ptr; /* Descriptor buffer pointer */ 224 u32 next_desc_ptr; /* Next descriptor pointer */ 225 }; 226 227 struct tx_desc { 228 u32 cmd_sts; /* Command/status field */ 229 u16 l4i_chk; /* CPU provided TCP checksum */ 230 u16 byte_cnt; /* buffer byte count */ 231 u32 buf_ptr; /* pointer to buffer for this descriptor*/ 232 u32 next_desc_ptr; /* Pointer to next descriptor */ 233 }; 234 #else 235 #error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined 236 #endif 237 238 /* RX & TX descriptor command */ 239 #define BUFFER_OWNED_BY_DMA 0x80000000 240 241 /* RX & TX descriptor status */ 242 #define ERROR_SUMMARY 0x00000001 243 244 /* RX descriptor status */ 245 #define LAYER_4_CHECKSUM_OK 0x40000000 246 #define RX_ENABLE_INTERRUPT 0x20000000 247 #define RX_FIRST_DESC 0x08000000 248 #define RX_LAST_DESC 0x04000000 249 #define RX_IP_HDR_OK 0x02000000 250 #define RX_PKT_IS_IPV4 0x01000000 251 #define RX_PKT_IS_ETHERNETV2 0x00800000 252 #define RX_PKT_LAYER4_TYPE_MASK 0x00600000 253 #define RX_PKT_LAYER4_TYPE_TCP_IPV4 0x00000000 254 #define RX_PKT_IS_VLAN_TAGGED 0x00080000 255 256 /* TX descriptor command */ 257 #define TX_ENABLE_INTERRUPT 0x00800000 258 #define GEN_CRC 0x00400000 259 #define TX_FIRST_DESC 0x00200000 260 #define TX_LAST_DESC 0x00100000 261 #define ZERO_PADDING 0x00080000 262 #define GEN_IP_V4_CHECKSUM 0x00040000 263 #define GEN_TCP_UDP_CHECKSUM 0x00020000 264 #define UDP_FRAME 0x00010000 265 #define MAC_HDR_EXTRA_4_BYTES 0x00008000 266 #define GEN_TCP_UDP_CHK_FULL 0x00000400 267 #define MAC_HDR_EXTRA_8_BYTES 0x00000200 268 269 #define TX_IHL_SHIFT 11 270 271 272 /* global *******************************************************************/ 273 struct mv643xx_eth_shared_private { 274 /* 275 * Ethernet controller base address. 276 */ 277 void __iomem *base; 278 279 /* 280 * Per-port MBUS window access register value. 281 */ 282 u32 win_protect; 283 284 /* 285 * Hardware-specific parameters. 286 */ 287 int extended_rx_coal_limit; 288 int tx_bw_control; 289 int tx_csum_limit; 290 struct clk *clk; 291 }; 292 293 #define TX_BW_CONTROL_ABSENT 0 294 #define TX_BW_CONTROL_OLD_LAYOUT 1 295 #define TX_BW_CONTROL_NEW_LAYOUT 2 296 297 static int mv643xx_eth_open(struct net_device *dev); 298 static int mv643xx_eth_stop(struct net_device *dev); 299 300 301 /* per-port *****************************************************************/ 302 struct mib_counters { 303 u64 good_octets_received; 304 u32 bad_octets_received; 305 u32 internal_mac_transmit_err; 306 u32 good_frames_received; 307 u32 bad_frames_received; 308 u32 broadcast_frames_received; 309 u32 multicast_frames_received; 310 u32 frames_64_octets; 311 u32 frames_65_to_127_octets; 312 u32 frames_128_to_255_octets; 313 u32 frames_256_to_511_octets; 314 u32 frames_512_to_1023_octets; 315 u32 frames_1024_to_max_octets; 316 u64 good_octets_sent; 317 u32 good_frames_sent; 318 u32 excessive_collision; 319 u32 multicast_frames_sent; 320 u32 broadcast_frames_sent; 321 u32 unrec_mac_control_received; 322 u32 fc_sent; 323 u32 good_fc_received; 324 u32 bad_fc_received; 325 u32 undersize_received; 326 u32 fragments_received; 327 u32 oversize_received; 328 u32 jabber_received; 329 u32 mac_receive_error; 330 u32 bad_crc_event; 331 u32 collision; 332 u32 late_collision; 333 /* Non MIB hardware counters */ 334 u32 rx_discard; 335 u32 rx_overrun; 336 }; 337 338 struct rx_queue { 339 int index; 340 341 int rx_ring_size; 342 343 int rx_desc_count; 344 int rx_curr_desc; 345 int rx_used_desc; 346 347 struct rx_desc *rx_desc_area; 348 dma_addr_t rx_desc_dma; 349 int rx_desc_area_size; 350 struct sk_buff **rx_skb; 351 }; 352 353 struct tx_queue { 354 int index; 355 356 int tx_ring_size; 357 358 int tx_desc_count; 359 int tx_curr_desc; 360 int tx_used_desc; 361 362 int tx_stop_threshold; 363 int tx_wake_threshold; 364 365 char *tso_hdrs; 366 dma_addr_t tso_hdrs_dma; 367 368 struct tx_desc *tx_desc_area; 369 char *tx_desc_mapping; /* array to track the type of the dma mapping */ 370 dma_addr_t tx_desc_dma; 371 int tx_desc_area_size; 372 373 struct sk_buff_head tx_skb; 374 375 unsigned long tx_packets; 376 unsigned long tx_bytes; 377 unsigned long tx_dropped; 378 }; 379 380 struct mv643xx_eth_private { 381 struct mv643xx_eth_shared_private *shared; 382 void __iomem *base; 383 int port_num; 384 385 struct net_device *dev; 386 387 struct phy_device *phy; 388 389 struct timer_list mib_counters_timer; 390 spinlock_t mib_counters_lock; 391 struct mib_counters mib_counters; 392 393 struct work_struct tx_timeout_task; 394 395 struct napi_struct napi; 396 u32 int_mask; 397 u8 oom; 398 u8 work_link; 399 u8 work_tx; 400 u8 work_tx_end; 401 u8 work_rx; 402 u8 work_rx_refill; 403 404 int skb_size; 405 406 /* 407 * RX state. 408 */ 409 int rx_ring_size; 410 unsigned long rx_desc_sram_addr; 411 int rx_desc_sram_size; 412 int rxq_count; 413 struct timer_list rx_oom; 414 struct rx_queue rxq[8]; 415 416 /* 417 * TX state. 418 */ 419 int tx_ring_size; 420 unsigned long tx_desc_sram_addr; 421 int tx_desc_sram_size; 422 int txq_count; 423 struct tx_queue txq[8]; 424 425 /* 426 * Hardware-specific parameters. 427 */ 428 struct clk *clk; 429 unsigned int t_clk; 430 }; 431 432 433 /* port register accessors **************************************************/ 434 static inline u32 rdl(struct mv643xx_eth_private *mp, int offset) 435 { 436 return readl(mp->shared->base + offset); 437 } 438 439 static inline u32 rdlp(struct mv643xx_eth_private *mp, int offset) 440 { 441 return readl(mp->base + offset); 442 } 443 444 static inline void wrl(struct mv643xx_eth_private *mp, int offset, u32 data) 445 { 446 writel(data, mp->shared->base + offset); 447 } 448 449 static inline void wrlp(struct mv643xx_eth_private *mp, int offset, u32 data) 450 { 451 writel(data, mp->base + offset); 452 } 453 454 455 /* rxq/txq helper functions *************************************************/ 456 static struct mv643xx_eth_private *rxq_to_mp(struct rx_queue *rxq) 457 { 458 return container_of(rxq, struct mv643xx_eth_private, rxq[rxq->index]); 459 } 460 461 static struct mv643xx_eth_private *txq_to_mp(struct tx_queue *txq) 462 { 463 return container_of(txq, struct mv643xx_eth_private, txq[txq->index]); 464 } 465 466 static void rxq_enable(struct rx_queue *rxq) 467 { 468 struct mv643xx_eth_private *mp = rxq_to_mp(rxq); 469 wrlp(mp, RXQ_COMMAND, 1 << rxq->index); 470 } 471 472 static void rxq_disable(struct rx_queue *rxq) 473 { 474 struct mv643xx_eth_private *mp = rxq_to_mp(rxq); 475 u8 mask = 1 << rxq->index; 476 477 wrlp(mp, RXQ_COMMAND, mask << 8); 478 while (rdlp(mp, RXQ_COMMAND) & mask) 479 udelay(10); 480 } 481 482 static void txq_reset_hw_ptr(struct tx_queue *txq) 483 { 484 struct mv643xx_eth_private *mp = txq_to_mp(txq); 485 u32 addr; 486 487 addr = (u32)txq->tx_desc_dma; 488 addr += txq->tx_curr_desc * sizeof(struct tx_desc); 489 wrlp(mp, TXQ_CURRENT_DESC_PTR(txq->index), addr); 490 } 491 492 static void txq_enable(struct tx_queue *txq) 493 { 494 struct mv643xx_eth_private *mp = txq_to_mp(txq); 495 wrlp(mp, TXQ_COMMAND, 1 << txq->index); 496 } 497 498 static void txq_disable(struct tx_queue *txq) 499 { 500 struct mv643xx_eth_private *mp = txq_to_mp(txq); 501 u8 mask = 1 << txq->index; 502 503 wrlp(mp, TXQ_COMMAND, mask << 8); 504 while (rdlp(mp, TXQ_COMMAND) & mask) 505 udelay(10); 506 } 507 508 static void txq_maybe_wake(struct tx_queue *txq) 509 { 510 struct mv643xx_eth_private *mp = txq_to_mp(txq); 511 struct netdev_queue *nq = netdev_get_tx_queue(mp->dev, txq->index); 512 513 if (netif_tx_queue_stopped(nq)) { 514 __netif_tx_lock(nq, smp_processor_id()); 515 if (txq->tx_desc_count <= txq->tx_wake_threshold) 516 netif_tx_wake_queue(nq); 517 __netif_tx_unlock(nq); 518 } 519 } 520 521 static int rxq_process(struct rx_queue *rxq, int budget) 522 { 523 struct mv643xx_eth_private *mp = rxq_to_mp(rxq); 524 struct net_device_stats *stats = &mp->dev->stats; 525 int rx; 526 527 rx = 0; 528 while (rx < budget && rxq->rx_desc_count) { 529 struct rx_desc *rx_desc; 530 unsigned int cmd_sts; 531 struct sk_buff *skb; 532 u16 byte_cnt; 533 534 rx_desc = &rxq->rx_desc_area[rxq->rx_curr_desc]; 535 536 cmd_sts = rx_desc->cmd_sts; 537 if (cmd_sts & BUFFER_OWNED_BY_DMA) 538 break; 539 rmb(); 540 541 skb = rxq->rx_skb[rxq->rx_curr_desc]; 542 rxq->rx_skb[rxq->rx_curr_desc] = NULL; 543 544 rxq->rx_curr_desc++; 545 if (rxq->rx_curr_desc == rxq->rx_ring_size) 546 rxq->rx_curr_desc = 0; 547 548 dma_unmap_single(mp->dev->dev.parent, rx_desc->buf_ptr, 549 rx_desc->buf_size, DMA_FROM_DEVICE); 550 rxq->rx_desc_count--; 551 rx++; 552 553 mp->work_rx_refill |= 1 << rxq->index; 554 555 byte_cnt = rx_desc->byte_cnt; 556 557 /* 558 * Update statistics. 559 * 560 * Note that the descriptor byte count includes 2 dummy 561 * bytes automatically inserted by the hardware at the 562 * start of the packet (which we don't count), and a 4 563 * byte CRC at the end of the packet (which we do count). 564 */ 565 stats->rx_packets++; 566 stats->rx_bytes += byte_cnt - 2; 567 568 /* 569 * In case we received a packet without first / last bits 570 * on, or the error summary bit is set, the packet needs 571 * to be dropped. 572 */ 573 if ((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC | ERROR_SUMMARY)) 574 != (RX_FIRST_DESC | RX_LAST_DESC)) 575 goto err; 576 577 /* 578 * The -4 is for the CRC in the trailer of the 579 * received packet 580 */ 581 skb_put(skb, byte_cnt - 2 - 4); 582 583 if (cmd_sts & LAYER_4_CHECKSUM_OK) 584 skb->ip_summed = CHECKSUM_UNNECESSARY; 585 skb->protocol = eth_type_trans(skb, mp->dev); 586 587 napi_gro_receive(&mp->napi, skb); 588 589 continue; 590 591 err: 592 stats->rx_dropped++; 593 594 if ((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC)) != 595 (RX_FIRST_DESC | RX_LAST_DESC)) { 596 if (net_ratelimit()) 597 netdev_err(mp->dev, 598 "received packet spanning multiple descriptors\n"); 599 } 600 601 if (cmd_sts & ERROR_SUMMARY) 602 stats->rx_errors++; 603 604 dev_kfree_skb(skb); 605 } 606 607 if (rx < budget) 608 mp->work_rx &= ~(1 << rxq->index); 609 610 return rx; 611 } 612 613 static int rxq_refill(struct rx_queue *rxq, int budget) 614 { 615 struct mv643xx_eth_private *mp = rxq_to_mp(rxq); 616 int refilled; 617 618 refilled = 0; 619 while (refilled < budget && rxq->rx_desc_count < rxq->rx_ring_size) { 620 struct sk_buff *skb; 621 int rx; 622 struct rx_desc *rx_desc; 623 int size; 624 625 skb = netdev_alloc_skb(mp->dev, mp->skb_size); 626 627 if (skb == NULL) { 628 mp->oom = 1; 629 goto oom; 630 } 631 632 if (SKB_DMA_REALIGN) 633 skb_reserve(skb, SKB_DMA_REALIGN); 634 635 refilled++; 636 rxq->rx_desc_count++; 637 638 rx = rxq->rx_used_desc++; 639 if (rxq->rx_used_desc == rxq->rx_ring_size) 640 rxq->rx_used_desc = 0; 641 642 rx_desc = rxq->rx_desc_area + rx; 643 644 size = skb_end_pointer(skb) - skb->data; 645 rx_desc->buf_ptr = dma_map_single(mp->dev->dev.parent, 646 skb->data, size, 647 DMA_FROM_DEVICE); 648 rx_desc->buf_size = size; 649 rxq->rx_skb[rx] = skb; 650 wmb(); 651 rx_desc->cmd_sts = BUFFER_OWNED_BY_DMA | RX_ENABLE_INTERRUPT; 652 wmb(); 653 654 /* 655 * The hardware automatically prepends 2 bytes of 656 * dummy data to each received packet, so that the 657 * IP header ends up 16-byte aligned. 658 */ 659 skb_reserve(skb, 2); 660 } 661 662 if (refilled < budget) 663 mp->work_rx_refill &= ~(1 << rxq->index); 664 665 oom: 666 return refilled; 667 } 668 669 670 /* tx ***********************************************************************/ 671 static inline unsigned int has_tiny_unaligned_frags(struct sk_buff *skb) 672 { 673 int frag; 674 675 for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) { 676 const skb_frag_t *fragp = &skb_shinfo(skb)->frags[frag]; 677 678 if (skb_frag_size(fragp) <= 8 && fragp->page_offset & 7) 679 return 1; 680 } 681 682 return 0; 683 } 684 685 static inline __be16 sum16_as_be(__sum16 sum) 686 { 687 return (__force __be16)sum; 688 } 689 690 static int skb_tx_csum(struct mv643xx_eth_private *mp, struct sk_buff *skb, 691 u16 *l4i_chk, u32 *command, int length) 692 { 693 int ret; 694 u32 cmd = 0; 695 696 if (skb->ip_summed == CHECKSUM_PARTIAL) { 697 int hdr_len; 698 int tag_bytes; 699 700 BUG_ON(skb->protocol != htons(ETH_P_IP) && 701 skb->protocol != htons(ETH_P_8021Q)); 702 703 hdr_len = (void *)ip_hdr(skb) - (void *)skb->data; 704 tag_bytes = hdr_len - ETH_HLEN; 705 706 if (length - hdr_len > mp->shared->tx_csum_limit || 707 unlikely(tag_bytes & ~12)) { 708 ret = skb_checksum_help(skb); 709 if (!ret) 710 goto no_csum; 711 return ret; 712 } 713 714 if (tag_bytes & 4) 715 cmd |= MAC_HDR_EXTRA_4_BYTES; 716 if (tag_bytes & 8) 717 cmd |= MAC_HDR_EXTRA_8_BYTES; 718 719 cmd |= GEN_TCP_UDP_CHECKSUM | GEN_TCP_UDP_CHK_FULL | 720 GEN_IP_V4_CHECKSUM | 721 ip_hdr(skb)->ihl << TX_IHL_SHIFT; 722 723 /* TODO: Revisit this. With the usage of GEN_TCP_UDP_CHK_FULL 724 * it seems we don't need to pass the initial checksum. */ 725 switch (ip_hdr(skb)->protocol) { 726 case IPPROTO_UDP: 727 cmd |= UDP_FRAME; 728 *l4i_chk = 0; 729 break; 730 case IPPROTO_TCP: 731 *l4i_chk = 0; 732 break; 733 default: 734 WARN(1, "protocol not supported"); 735 } 736 } else { 737 no_csum: 738 /* Errata BTS #50, IHL must be 5 if no HW checksum */ 739 cmd |= 5 << TX_IHL_SHIFT; 740 } 741 *command = cmd; 742 return 0; 743 } 744 745 static inline int 746 txq_put_data_tso(struct net_device *dev, struct tx_queue *txq, 747 struct sk_buff *skb, char *data, int length, 748 bool last_tcp, bool is_last) 749 { 750 int tx_index; 751 u32 cmd_sts; 752 struct tx_desc *desc; 753 754 tx_index = txq->tx_curr_desc++; 755 if (txq->tx_curr_desc == txq->tx_ring_size) 756 txq->tx_curr_desc = 0; 757 desc = &txq->tx_desc_area[tx_index]; 758 txq->tx_desc_mapping[tx_index] = DESC_DMA_MAP_SINGLE; 759 760 desc->l4i_chk = 0; 761 desc->byte_cnt = length; 762 desc->buf_ptr = dma_map_single(dev->dev.parent, data, 763 length, DMA_TO_DEVICE); 764 if (unlikely(dma_mapping_error(dev->dev.parent, desc->buf_ptr))) { 765 WARN(1, "dma_map_single failed!\n"); 766 return -ENOMEM; 767 } 768 769 cmd_sts = BUFFER_OWNED_BY_DMA; 770 if (last_tcp) { 771 /* last descriptor in the TCP packet */ 772 cmd_sts |= ZERO_PADDING | TX_LAST_DESC; 773 /* last descriptor in SKB */ 774 if (is_last) 775 cmd_sts |= TX_ENABLE_INTERRUPT; 776 } 777 desc->cmd_sts = cmd_sts; 778 return 0; 779 } 780 781 static inline void 782 txq_put_hdr_tso(struct sk_buff *skb, struct tx_queue *txq, int length) 783 { 784 struct mv643xx_eth_private *mp = txq_to_mp(txq); 785 int hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb); 786 int tx_index; 787 struct tx_desc *desc; 788 int ret; 789 u32 cmd_csum = 0; 790 u16 l4i_chk = 0; 791 792 tx_index = txq->tx_curr_desc; 793 desc = &txq->tx_desc_area[tx_index]; 794 795 ret = skb_tx_csum(mp, skb, &l4i_chk, &cmd_csum, length); 796 if (ret) 797 WARN(1, "failed to prepare checksum!"); 798 799 /* Should we set this? Can't use the value from skb_tx_csum() 800 * as it's not the correct initial L4 checksum to use. */ 801 desc->l4i_chk = 0; 802 803 desc->byte_cnt = hdr_len; 804 desc->buf_ptr = txq->tso_hdrs_dma + 805 txq->tx_curr_desc * TSO_HEADER_SIZE; 806 desc->cmd_sts = cmd_csum | BUFFER_OWNED_BY_DMA | TX_FIRST_DESC | 807 GEN_CRC; 808 809 txq->tx_curr_desc++; 810 if (txq->tx_curr_desc == txq->tx_ring_size) 811 txq->tx_curr_desc = 0; 812 } 813 814 static int txq_submit_tso(struct tx_queue *txq, struct sk_buff *skb, 815 struct net_device *dev) 816 { 817 struct mv643xx_eth_private *mp = txq_to_mp(txq); 818 int total_len, data_left, ret; 819 int desc_count = 0; 820 struct tso_t tso; 821 int hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb); 822 823 /* Count needed descriptors */ 824 if ((txq->tx_desc_count + tso_count_descs(skb)) >= txq->tx_ring_size) { 825 netdev_dbg(dev, "not enough descriptors for TSO!\n"); 826 return -EBUSY; 827 } 828 829 /* Initialize the TSO handler, and prepare the first payload */ 830 tso_start(skb, &tso); 831 832 total_len = skb->len - hdr_len; 833 while (total_len > 0) { 834 char *hdr; 835 836 data_left = min_t(int, skb_shinfo(skb)->gso_size, total_len); 837 total_len -= data_left; 838 desc_count++; 839 840 /* prepare packet headers: MAC + IP + TCP */ 841 hdr = txq->tso_hdrs + txq->tx_curr_desc * TSO_HEADER_SIZE; 842 tso_build_hdr(skb, hdr, &tso, data_left, total_len == 0); 843 txq_put_hdr_tso(skb, txq, data_left); 844 845 while (data_left > 0) { 846 int size; 847 desc_count++; 848 849 size = min_t(int, tso.size, data_left); 850 ret = txq_put_data_tso(dev, txq, skb, tso.data, size, 851 size == data_left, 852 total_len == 0); 853 if (ret) 854 goto err_release; 855 data_left -= size; 856 tso_build_data(skb, &tso, size); 857 } 858 } 859 860 __skb_queue_tail(&txq->tx_skb, skb); 861 skb_tx_timestamp(skb); 862 863 /* clear TX_END status */ 864 mp->work_tx_end &= ~(1 << txq->index); 865 866 /* ensure all descriptors are written before poking hardware */ 867 wmb(); 868 txq_enable(txq); 869 txq->tx_desc_count += desc_count; 870 return 0; 871 err_release: 872 /* TODO: Release all used data descriptors; header descriptors must not 873 * be DMA-unmapped. 874 */ 875 return ret; 876 } 877 878 static void txq_submit_frag_skb(struct tx_queue *txq, struct sk_buff *skb) 879 { 880 struct mv643xx_eth_private *mp = txq_to_mp(txq); 881 int nr_frags = skb_shinfo(skb)->nr_frags; 882 int frag; 883 884 for (frag = 0; frag < nr_frags; frag++) { 885 skb_frag_t *this_frag; 886 int tx_index; 887 struct tx_desc *desc; 888 889 this_frag = &skb_shinfo(skb)->frags[frag]; 890 tx_index = txq->tx_curr_desc++; 891 if (txq->tx_curr_desc == txq->tx_ring_size) 892 txq->tx_curr_desc = 0; 893 desc = &txq->tx_desc_area[tx_index]; 894 txq->tx_desc_mapping[tx_index] = DESC_DMA_MAP_PAGE; 895 896 /* 897 * The last fragment will generate an interrupt 898 * which will free the skb on TX completion. 899 */ 900 if (frag == nr_frags - 1) { 901 desc->cmd_sts = BUFFER_OWNED_BY_DMA | 902 ZERO_PADDING | TX_LAST_DESC | 903 TX_ENABLE_INTERRUPT; 904 } else { 905 desc->cmd_sts = BUFFER_OWNED_BY_DMA; 906 } 907 908 desc->l4i_chk = 0; 909 desc->byte_cnt = skb_frag_size(this_frag); 910 desc->buf_ptr = skb_frag_dma_map(mp->dev->dev.parent, 911 this_frag, 0, desc->byte_cnt, 912 DMA_TO_DEVICE); 913 } 914 } 915 916 static int txq_submit_skb(struct tx_queue *txq, struct sk_buff *skb, 917 struct net_device *dev) 918 { 919 struct mv643xx_eth_private *mp = txq_to_mp(txq); 920 int nr_frags = skb_shinfo(skb)->nr_frags; 921 int tx_index; 922 struct tx_desc *desc; 923 u32 cmd_sts; 924 u16 l4i_chk; 925 int length, ret; 926 927 cmd_sts = 0; 928 l4i_chk = 0; 929 930 if (txq->tx_ring_size - txq->tx_desc_count < MAX_SKB_FRAGS + 1) { 931 if (net_ratelimit()) 932 netdev_err(dev, "tx queue full?!\n"); 933 return -EBUSY; 934 } 935 936 ret = skb_tx_csum(mp, skb, &l4i_chk, &cmd_sts, skb->len); 937 if (ret) 938 return ret; 939 cmd_sts |= TX_FIRST_DESC | GEN_CRC | BUFFER_OWNED_BY_DMA; 940 941 tx_index = txq->tx_curr_desc++; 942 if (txq->tx_curr_desc == txq->tx_ring_size) 943 txq->tx_curr_desc = 0; 944 desc = &txq->tx_desc_area[tx_index]; 945 txq->tx_desc_mapping[tx_index] = DESC_DMA_MAP_SINGLE; 946 947 if (nr_frags) { 948 txq_submit_frag_skb(txq, skb); 949 length = skb_headlen(skb); 950 } else { 951 cmd_sts |= ZERO_PADDING | TX_LAST_DESC | TX_ENABLE_INTERRUPT; 952 length = skb->len; 953 } 954 955 desc->l4i_chk = l4i_chk; 956 desc->byte_cnt = length; 957 desc->buf_ptr = dma_map_single(mp->dev->dev.parent, skb->data, 958 length, DMA_TO_DEVICE); 959 960 __skb_queue_tail(&txq->tx_skb, skb); 961 962 skb_tx_timestamp(skb); 963 964 /* ensure all other descriptors are written before first cmd_sts */ 965 wmb(); 966 desc->cmd_sts = cmd_sts; 967 968 /* clear TX_END status */ 969 mp->work_tx_end &= ~(1 << txq->index); 970 971 /* ensure all descriptors are written before poking hardware */ 972 wmb(); 973 txq_enable(txq); 974 975 txq->tx_desc_count += nr_frags + 1; 976 977 return 0; 978 } 979 980 static netdev_tx_t mv643xx_eth_xmit(struct sk_buff *skb, struct net_device *dev) 981 { 982 struct mv643xx_eth_private *mp = netdev_priv(dev); 983 int length, queue, ret; 984 struct tx_queue *txq; 985 struct netdev_queue *nq; 986 987 queue = skb_get_queue_mapping(skb); 988 txq = mp->txq + queue; 989 nq = netdev_get_tx_queue(dev, queue); 990 991 if (has_tiny_unaligned_frags(skb) && __skb_linearize(skb)) { 992 netdev_printk(KERN_DEBUG, dev, 993 "failed to linearize skb with tiny unaligned fragment\n"); 994 return NETDEV_TX_BUSY; 995 } 996 997 length = skb->len; 998 999 if (skb_is_gso(skb)) 1000 ret = txq_submit_tso(txq, skb, dev); 1001 else 1002 ret = txq_submit_skb(txq, skb, dev); 1003 if (!ret) { 1004 txq->tx_bytes += length; 1005 txq->tx_packets++; 1006 1007 if (txq->tx_desc_count >= txq->tx_stop_threshold) 1008 netif_tx_stop_queue(nq); 1009 } else { 1010 txq->tx_dropped++; 1011 dev_kfree_skb_any(skb); 1012 } 1013 1014 return NETDEV_TX_OK; 1015 } 1016 1017 1018 /* tx napi ******************************************************************/ 1019 static void txq_kick(struct tx_queue *txq) 1020 { 1021 struct mv643xx_eth_private *mp = txq_to_mp(txq); 1022 struct netdev_queue *nq = netdev_get_tx_queue(mp->dev, txq->index); 1023 u32 hw_desc_ptr; 1024 u32 expected_ptr; 1025 1026 __netif_tx_lock(nq, smp_processor_id()); 1027 1028 if (rdlp(mp, TXQ_COMMAND) & (1 << txq->index)) 1029 goto out; 1030 1031 hw_desc_ptr = rdlp(mp, TXQ_CURRENT_DESC_PTR(txq->index)); 1032 expected_ptr = (u32)txq->tx_desc_dma + 1033 txq->tx_curr_desc * sizeof(struct tx_desc); 1034 1035 if (hw_desc_ptr != expected_ptr) 1036 txq_enable(txq); 1037 1038 out: 1039 __netif_tx_unlock(nq); 1040 1041 mp->work_tx_end &= ~(1 << txq->index); 1042 } 1043 1044 static int txq_reclaim(struct tx_queue *txq, int budget, int force) 1045 { 1046 struct mv643xx_eth_private *mp = txq_to_mp(txq); 1047 struct netdev_queue *nq = netdev_get_tx_queue(mp->dev, txq->index); 1048 int reclaimed; 1049 1050 __netif_tx_lock_bh(nq); 1051 1052 reclaimed = 0; 1053 while (reclaimed < budget && txq->tx_desc_count > 0) { 1054 int tx_index; 1055 struct tx_desc *desc; 1056 u32 cmd_sts; 1057 char desc_dma_map; 1058 1059 tx_index = txq->tx_used_desc; 1060 desc = &txq->tx_desc_area[tx_index]; 1061 desc_dma_map = txq->tx_desc_mapping[tx_index]; 1062 1063 cmd_sts = desc->cmd_sts; 1064 1065 if (cmd_sts & BUFFER_OWNED_BY_DMA) { 1066 if (!force) 1067 break; 1068 desc->cmd_sts = cmd_sts & ~BUFFER_OWNED_BY_DMA; 1069 } 1070 1071 txq->tx_used_desc = tx_index + 1; 1072 if (txq->tx_used_desc == txq->tx_ring_size) 1073 txq->tx_used_desc = 0; 1074 1075 reclaimed++; 1076 txq->tx_desc_count--; 1077 1078 if (!IS_TSO_HEADER(txq, desc->buf_ptr)) { 1079 1080 if (desc_dma_map == DESC_DMA_MAP_PAGE) 1081 dma_unmap_page(mp->dev->dev.parent, 1082 desc->buf_ptr, 1083 desc->byte_cnt, 1084 DMA_TO_DEVICE); 1085 else 1086 dma_unmap_single(mp->dev->dev.parent, 1087 desc->buf_ptr, 1088 desc->byte_cnt, 1089 DMA_TO_DEVICE); 1090 } 1091 1092 if (cmd_sts & TX_ENABLE_INTERRUPT) { 1093 struct sk_buff *skb = __skb_dequeue(&txq->tx_skb); 1094 1095 if (!WARN_ON(!skb)) 1096 dev_kfree_skb(skb); 1097 } 1098 1099 if (cmd_sts & ERROR_SUMMARY) { 1100 netdev_info(mp->dev, "tx error\n"); 1101 mp->dev->stats.tx_errors++; 1102 } 1103 1104 } 1105 1106 __netif_tx_unlock_bh(nq); 1107 1108 if (reclaimed < budget) 1109 mp->work_tx &= ~(1 << txq->index); 1110 1111 return reclaimed; 1112 } 1113 1114 1115 /* tx rate control **********************************************************/ 1116 /* 1117 * Set total maximum TX rate (shared by all TX queues for this port) 1118 * to 'rate' bits per second, with a maximum burst of 'burst' bytes. 1119 */ 1120 static void tx_set_rate(struct mv643xx_eth_private *mp, int rate, int burst) 1121 { 1122 int token_rate; 1123 int mtu; 1124 int bucket_size; 1125 1126 token_rate = ((rate / 1000) * 64) / (mp->t_clk / 1000); 1127 if (token_rate > 1023) 1128 token_rate = 1023; 1129 1130 mtu = (mp->dev->mtu + 255) >> 8; 1131 if (mtu > 63) 1132 mtu = 63; 1133 1134 bucket_size = (burst + 255) >> 8; 1135 if (bucket_size > 65535) 1136 bucket_size = 65535; 1137 1138 switch (mp->shared->tx_bw_control) { 1139 case TX_BW_CONTROL_OLD_LAYOUT: 1140 wrlp(mp, TX_BW_RATE, token_rate); 1141 wrlp(mp, TX_BW_MTU, mtu); 1142 wrlp(mp, TX_BW_BURST, bucket_size); 1143 break; 1144 case TX_BW_CONTROL_NEW_LAYOUT: 1145 wrlp(mp, TX_BW_RATE_MOVED, token_rate); 1146 wrlp(mp, TX_BW_MTU_MOVED, mtu); 1147 wrlp(mp, TX_BW_BURST_MOVED, bucket_size); 1148 break; 1149 } 1150 } 1151 1152 static void txq_set_rate(struct tx_queue *txq, int rate, int burst) 1153 { 1154 struct mv643xx_eth_private *mp = txq_to_mp(txq); 1155 int token_rate; 1156 int bucket_size; 1157 1158 token_rate = ((rate / 1000) * 64) / (mp->t_clk / 1000); 1159 if (token_rate > 1023) 1160 token_rate = 1023; 1161 1162 bucket_size = (burst + 255) >> 8; 1163 if (bucket_size > 65535) 1164 bucket_size = 65535; 1165 1166 wrlp(mp, TXQ_BW_TOKENS(txq->index), token_rate << 14); 1167 wrlp(mp, TXQ_BW_CONF(txq->index), (bucket_size << 10) | token_rate); 1168 } 1169 1170 static void txq_set_fixed_prio_mode(struct tx_queue *txq) 1171 { 1172 struct mv643xx_eth_private *mp = txq_to_mp(txq); 1173 int off; 1174 u32 val; 1175 1176 /* 1177 * Turn on fixed priority mode. 1178 */ 1179 off = 0; 1180 switch (mp->shared->tx_bw_control) { 1181 case TX_BW_CONTROL_OLD_LAYOUT: 1182 off = TXQ_FIX_PRIO_CONF; 1183 break; 1184 case TX_BW_CONTROL_NEW_LAYOUT: 1185 off = TXQ_FIX_PRIO_CONF_MOVED; 1186 break; 1187 } 1188 1189 if (off) { 1190 val = rdlp(mp, off); 1191 val |= 1 << txq->index; 1192 wrlp(mp, off, val); 1193 } 1194 } 1195 1196 1197 /* mii management interface *************************************************/ 1198 static void mv643xx_eth_adjust_link(struct net_device *dev) 1199 { 1200 struct mv643xx_eth_private *mp = netdev_priv(dev); 1201 u32 pscr = rdlp(mp, PORT_SERIAL_CONTROL); 1202 u32 autoneg_disable = FORCE_LINK_PASS | 1203 DISABLE_AUTO_NEG_SPEED_GMII | 1204 DISABLE_AUTO_NEG_FOR_FLOW_CTRL | 1205 DISABLE_AUTO_NEG_FOR_DUPLEX; 1206 1207 if (mp->phy->autoneg == AUTONEG_ENABLE) { 1208 /* enable auto negotiation */ 1209 pscr &= ~autoneg_disable; 1210 goto out_write; 1211 } 1212 1213 pscr |= autoneg_disable; 1214 1215 if (mp->phy->speed == SPEED_1000) { 1216 /* force gigabit, half duplex not supported */ 1217 pscr |= SET_GMII_SPEED_TO_1000; 1218 pscr |= SET_FULL_DUPLEX_MODE; 1219 goto out_write; 1220 } 1221 1222 pscr &= ~SET_GMII_SPEED_TO_1000; 1223 1224 if (mp->phy->speed == SPEED_100) 1225 pscr |= SET_MII_SPEED_TO_100; 1226 else 1227 pscr &= ~SET_MII_SPEED_TO_100; 1228 1229 if (mp->phy->duplex == DUPLEX_FULL) 1230 pscr |= SET_FULL_DUPLEX_MODE; 1231 else 1232 pscr &= ~SET_FULL_DUPLEX_MODE; 1233 1234 out_write: 1235 wrlp(mp, PORT_SERIAL_CONTROL, pscr); 1236 } 1237 1238 /* statistics ***************************************************************/ 1239 static struct net_device_stats *mv643xx_eth_get_stats(struct net_device *dev) 1240 { 1241 struct mv643xx_eth_private *mp = netdev_priv(dev); 1242 struct net_device_stats *stats = &dev->stats; 1243 unsigned long tx_packets = 0; 1244 unsigned long tx_bytes = 0; 1245 unsigned long tx_dropped = 0; 1246 int i; 1247 1248 for (i = 0; i < mp->txq_count; i++) { 1249 struct tx_queue *txq = mp->txq + i; 1250 1251 tx_packets += txq->tx_packets; 1252 tx_bytes += txq->tx_bytes; 1253 tx_dropped += txq->tx_dropped; 1254 } 1255 1256 stats->tx_packets = tx_packets; 1257 stats->tx_bytes = tx_bytes; 1258 stats->tx_dropped = tx_dropped; 1259 1260 return stats; 1261 } 1262 1263 static inline u32 mib_read(struct mv643xx_eth_private *mp, int offset) 1264 { 1265 return rdl(mp, MIB_COUNTERS(mp->port_num) + offset); 1266 } 1267 1268 static void mib_counters_clear(struct mv643xx_eth_private *mp) 1269 { 1270 int i; 1271 1272 for (i = 0; i < 0x80; i += 4) 1273 mib_read(mp, i); 1274 1275 /* Clear non MIB hw counters also */ 1276 rdlp(mp, RX_DISCARD_FRAME_CNT); 1277 rdlp(mp, RX_OVERRUN_FRAME_CNT); 1278 } 1279 1280 static void mib_counters_update(struct mv643xx_eth_private *mp) 1281 { 1282 struct mib_counters *p = &mp->mib_counters; 1283 1284 spin_lock_bh(&mp->mib_counters_lock); 1285 p->good_octets_received += mib_read(mp, 0x00); 1286 p->bad_octets_received += mib_read(mp, 0x08); 1287 p->internal_mac_transmit_err += mib_read(mp, 0x0c); 1288 p->good_frames_received += mib_read(mp, 0x10); 1289 p->bad_frames_received += mib_read(mp, 0x14); 1290 p->broadcast_frames_received += mib_read(mp, 0x18); 1291 p->multicast_frames_received += mib_read(mp, 0x1c); 1292 p->frames_64_octets += mib_read(mp, 0x20); 1293 p->frames_65_to_127_octets += mib_read(mp, 0x24); 1294 p->frames_128_to_255_octets += mib_read(mp, 0x28); 1295 p->frames_256_to_511_octets += mib_read(mp, 0x2c); 1296 p->frames_512_to_1023_octets += mib_read(mp, 0x30); 1297 p->frames_1024_to_max_octets += mib_read(mp, 0x34); 1298 p->good_octets_sent += mib_read(mp, 0x38); 1299 p->good_frames_sent += mib_read(mp, 0x40); 1300 p->excessive_collision += mib_read(mp, 0x44); 1301 p->multicast_frames_sent += mib_read(mp, 0x48); 1302 p->broadcast_frames_sent += mib_read(mp, 0x4c); 1303 p->unrec_mac_control_received += mib_read(mp, 0x50); 1304 p->fc_sent += mib_read(mp, 0x54); 1305 p->good_fc_received += mib_read(mp, 0x58); 1306 p->bad_fc_received += mib_read(mp, 0x5c); 1307 p->undersize_received += mib_read(mp, 0x60); 1308 p->fragments_received += mib_read(mp, 0x64); 1309 p->oversize_received += mib_read(mp, 0x68); 1310 p->jabber_received += mib_read(mp, 0x6c); 1311 p->mac_receive_error += mib_read(mp, 0x70); 1312 p->bad_crc_event += mib_read(mp, 0x74); 1313 p->collision += mib_read(mp, 0x78); 1314 p->late_collision += mib_read(mp, 0x7c); 1315 /* Non MIB hardware counters */ 1316 p->rx_discard += rdlp(mp, RX_DISCARD_FRAME_CNT); 1317 p->rx_overrun += rdlp(mp, RX_OVERRUN_FRAME_CNT); 1318 spin_unlock_bh(&mp->mib_counters_lock); 1319 } 1320 1321 static void mib_counters_timer_wrapper(unsigned long _mp) 1322 { 1323 struct mv643xx_eth_private *mp = (void *)_mp; 1324 mib_counters_update(mp); 1325 mod_timer(&mp->mib_counters_timer, jiffies + 30 * HZ); 1326 } 1327 1328 1329 /* interrupt coalescing *****************************************************/ 1330 /* 1331 * Hardware coalescing parameters are set in units of 64 t_clk 1332 * cycles. I.e.: 1333 * 1334 * coal_delay_in_usec = 64000000 * register_value / t_clk_rate 1335 * 1336 * register_value = coal_delay_in_usec * t_clk_rate / 64000000 1337 * 1338 * In the ->set*() methods, we round the computed register value 1339 * to the nearest integer. 1340 */ 1341 static unsigned int get_rx_coal(struct mv643xx_eth_private *mp) 1342 { 1343 u32 val = rdlp(mp, SDMA_CONFIG); 1344 u64 temp; 1345 1346 if (mp->shared->extended_rx_coal_limit) 1347 temp = ((val & 0x02000000) >> 10) | ((val & 0x003fff80) >> 7); 1348 else 1349 temp = (val & 0x003fff00) >> 8; 1350 1351 temp *= 64000000; 1352 do_div(temp, mp->t_clk); 1353 1354 return (unsigned int)temp; 1355 } 1356 1357 static void set_rx_coal(struct mv643xx_eth_private *mp, unsigned int usec) 1358 { 1359 u64 temp; 1360 u32 val; 1361 1362 temp = (u64)usec * mp->t_clk; 1363 temp += 31999999; 1364 do_div(temp, 64000000); 1365 1366 val = rdlp(mp, SDMA_CONFIG); 1367 if (mp->shared->extended_rx_coal_limit) { 1368 if (temp > 0xffff) 1369 temp = 0xffff; 1370 val &= ~0x023fff80; 1371 val |= (temp & 0x8000) << 10; 1372 val |= (temp & 0x7fff) << 7; 1373 } else { 1374 if (temp > 0x3fff) 1375 temp = 0x3fff; 1376 val &= ~0x003fff00; 1377 val |= (temp & 0x3fff) << 8; 1378 } 1379 wrlp(mp, SDMA_CONFIG, val); 1380 } 1381 1382 static unsigned int get_tx_coal(struct mv643xx_eth_private *mp) 1383 { 1384 u64 temp; 1385 1386 temp = (rdlp(mp, TX_FIFO_URGENT_THRESHOLD) & 0x3fff0) >> 4; 1387 temp *= 64000000; 1388 do_div(temp, mp->t_clk); 1389 1390 return (unsigned int)temp; 1391 } 1392 1393 static void set_tx_coal(struct mv643xx_eth_private *mp, unsigned int usec) 1394 { 1395 u64 temp; 1396 1397 temp = (u64)usec * mp->t_clk; 1398 temp += 31999999; 1399 do_div(temp, 64000000); 1400 1401 if (temp > 0x3fff) 1402 temp = 0x3fff; 1403 1404 wrlp(mp, TX_FIFO_URGENT_THRESHOLD, temp << 4); 1405 } 1406 1407 1408 /* ethtool ******************************************************************/ 1409 struct mv643xx_eth_stats { 1410 char stat_string[ETH_GSTRING_LEN]; 1411 int sizeof_stat; 1412 int netdev_off; 1413 int mp_off; 1414 }; 1415 1416 #define SSTAT(m) \ 1417 { #m, FIELD_SIZEOF(struct net_device_stats, m), \ 1418 offsetof(struct net_device, stats.m), -1 } 1419 1420 #define MIBSTAT(m) \ 1421 { #m, FIELD_SIZEOF(struct mib_counters, m), \ 1422 -1, offsetof(struct mv643xx_eth_private, mib_counters.m) } 1423 1424 static const struct mv643xx_eth_stats mv643xx_eth_stats[] = { 1425 SSTAT(rx_packets), 1426 SSTAT(tx_packets), 1427 SSTAT(rx_bytes), 1428 SSTAT(tx_bytes), 1429 SSTAT(rx_errors), 1430 SSTAT(tx_errors), 1431 SSTAT(rx_dropped), 1432 SSTAT(tx_dropped), 1433 MIBSTAT(good_octets_received), 1434 MIBSTAT(bad_octets_received), 1435 MIBSTAT(internal_mac_transmit_err), 1436 MIBSTAT(good_frames_received), 1437 MIBSTAT(bad_frames_received), 1438 MIBSTAT(broadcast_frames_received), 1439 MIBSTAT(multicast_frames_received), 1440 MIBSTAT(frames_64_octets), 1441 MIBSTAT(frames_65_to_127_octets), 1442 MIBSTAT(frames_128_to_255_octets), 1443 MIBSTAT(frames_256_to_511_octets), 1444 MIBSTAT(frames_512_to_1023_octets), 1445 MIBSTAT(frames_1024_to_max_octets), 1446 MIBSTAT(good_octets_sent), 1447 MIBSTAT(good_frames_sent), 1448 MIBSTAT(excessive_collision), 1449 MIBSTAT(multicast_frames_sent), 1450 MIBSTAT(broadcast_frames_sent), 1451 MIBSTAT(unrec_mac_control_received), 1452 MIBSTAT(fc_sent), 1453 MIBSTAT(good_fc_received), 1454 MIBSTAT(bad_fc_received), 1455 MIBSTAT(undersize_received), 1456 MIBSTAT(fragments_received), 1457 MIBSTAT(oversize_received), 1458 MIBSTAT(jabber_received), 1459 MIBSTAT(mac_receive_error), 1460 MIBSTAT(bad_crc_event), 1461 MIBSTAT(collision), 1462 MIBSTAT(late_collision), 1463 MIBSTAT(rx_discard), 1464 MIBSTAT(rx_overrun), 1465 }; 1466 1467 static int 1468 mv643xx_eth_get_settings_phy(struct mv643xx_eth_private *mp, 1469 struct ethtool_cmd *cmd) 1470 { 1471 int err; 1472 1473 err = phy_read_status(mp->phy); 1474 if (err == 0) 1475 err = phy_ethtool_gset(mp->phy, cmd); 1476 1477 /* 1478 * The MAC does not support 1000baseT_Half. 1479 */ 1480 cmd->supported &= ~SUPPORTED_1000baseT_Half; 1481 cmd->advertising &= ~ADVERTISED_1000baseT_Half; 1482 1483 return err; 1484 } 1485 1486 static int 1487 mv643xx_eth_get_settings_phyless(struct mv643xx_eth_private *mp, 1488 struct ethtool_cmd *cmd) 1489 { 1490 u32 port_status; 1491 1492 port_status = rdlp(mp, PORT_STATUS); 1493 1494 cmd->supported = SUPPORTED_MII; 1495 cmd->advertising = ADVERTISED_MII; 1496 switch (port_status & PORT_SPEED_MASK) { 1497 case PORT_SPEED_10: 1498 ethtool_cmd_speed_set(cmd, SPEED_10); 1499 break; 1500 case PORT_SPEED_100: 1501 ethtool_cmd_speed_set(cmd, SPEED_100); 1502 break; 1503 case PORT_SPEED_1000: 1504 ethtool_cmd_speed_set(cmd, SPEED_1000); 1505 break; 1506 default: 1507 cmd->speed = -1; 1508 break; 1509 } 1510 cmd->duplex = (port_status & FULL_DUPLEX) ? DUPLEX_FULL : DUPLEX_HALF; 1511 cmd->port = PORT_MII; 1512 cmd->phy_address = 0; 1513 cmd->transceiver = XCVR_INTERNAL; 1514 cmd->autoneg = AUTONEG_DISABLE; 1515 cmd->maxtxpkt = 1; 1516 cmd->maxrxpkt = 1; 1517 1518 return 0; 1519 } 1520 1521 static void 1522 mv643xx_eth_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 1523 { 1524 struct mv643xx_eth_private *mp = netdev_priv(dev); 1525 wol->supported = 0; 1526 wol->wolopts = 0; 1527 if (mp->phy) 1528 phy_ethtool_get_wol(mp->phy, wol); 1529 } 1530 1531 static int 1532 mv643xx_eth_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 1533 { 1534 struct mv643xx_eth_private *mp = netdev_priv(dev); 1535 int err; 1536 1537 if (mp->phy == NULL) 1538 return -EOPNOTSUPP; 1539 1540 err = phy_ethtool_set_wol(mp->phy, wol); 1541 /* Given that mv643xx_eth works without the marvell-specific PHY driver, 1542 * this debugging hint is useful to have. 1543 */ 1544 if (err == -EOPNOTSUPP) 1545 netdev_info(dev, "The PHY does not support set_wol, was CONFIG_MARVELL_PHY enabled?\n"); 1546 return err; 1547 } 1548 1549 static int 1550 mv643xx_eth_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) 1551 { 1552 struct mv643xx_eth_private *mp = netdev_priv(dev); 1553 1554 if (mp->phy != NULL) 1555 return mv643xx_eth_get_settings_phy(mp, cmd); 1556 else 1557 return mv643xx_eth_get_settings_phyless(mp, cmd); 1558 } 1559 1560 static int 1561 mv643xx_eth_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) 1562 { 1563 struct mv643xx_eth_private *mp = netdev_priv(dev); 1564 int ret; 1565 1566 if (mp->phy == NULL) 1567 return -EINVAL; 1568 1569 /* 1570 * The MAC does not support 1000baseT_Half. 1571 */ 1572 cmd->advertising &= ~ADVERTISED_1000baseT_Half; 1573 1574 ret = phy_ethtool_sset(mp->phy, cmd); 1575 if (!ret) 1576 mv643xx_eth_adjust_link(dev); 1577 return ret; 1578 } 1579 1580 static void mv643xx_eth_get_drvinfo(struct net_device *dev, 1581 struct ethtool_drvinfo *drvinfo) 1582 { 1583 strlcpy(drvinfo->driver, mv643xx_eth_driver_name, 1584 sizeof(drvinfo->driver)); 1585 strlcpy(drvinfo->version, mv643xx_eth_driver_version, 1586 sizeof(drvinfo->version)); 1587 strlcpy(drvinfo->fw_version, "N/A", sizeof(drvinfo->fw_version)); 1588 strlcpy(drvinfo->bus_info, "platform", sizeof(drvinfo->bus_info)); 1589 drvinfo->n_stats = ARRAY_SIZE(mv643xx_eth_stats); 1590 } 1591 1592 static int mv643xx_eth_nway_reset(struct net_device *dev) 1593 { 1594 struct mv643xx_eth_private *mp = netdev_priv(dev); 1595 1596 if (mp->phy == NULL) 1597 return -EINVAL; 1598 1599 return genphy_restart_aneg(mp->phy); 1600 } 1601 1602 static int 1603 mv643xx_eth_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec) 1604 { 1605 struct mv643xx_eth_private *mp = netdev_priv(dev); 1606 1607 ec->rx_coalesce_usecs = get_rx_coal(mp); 1608 ec->tx_coalesce_usecs = get_tx_coal(mp); 1609 1610 return 0; 1611 } 1612 1613 static int 1614 mv643xx_eth_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec) 1615 { 1616 struct mv643xx_eth_private *mp = netdev_priv(dev); 1617 1618 set_rx_coal(mp, ec->rx_coalesce_usecs); 1619 set_tx_coal(mp, ec->tx_coalesce_usecs); 1620 1621 return 0; 1622 } 1623 1624 static void 1625 mv643xx_eth_get_ringparam(struct net_device *dev, struct ethtool_ringparam *er) 1626 { 1627 struct mv643xx_eth_private *mp = netdev_priv(dev); 1628 1629 er->rx_max_pending = 4096; 1630 er->tx_max_pending = 4096; 1631 1632 er->rx_pending = mp->rx_ring_size; 1633 er->tx_pending = mp->tx_ring_size; 1634 } 1635 1636 static int 1637 mv643xx_eth_set_ringparam(struct net_device *dev, struct ethtool_ringparam *er) 1638 { 1639 struct mv643xx_eth_private *mp = netdev_priv(dev); 1640 1641 if (er->rx_mini_pending || er->rx_jumbo_pending) 1642 return -EINVAL; 1643 1644 mp->rx_ring_size = er->rx_pending < 4096 ? er->rx_pending : 4096; 1645 mp->tx_ring_size = clamp_t(unsigned int, er->tx_pending, 1646 MV643XX_MAX_SKB_DESCS * 2, 4096); 1647 if (mp->tx_ring_size != er->tx_pending) 1648 netdev_warn(dev, "TX queue size set to %u (requested %u)\n", 1649 mp->tx_ring_size, er->tx_pending); 1650 1651 if (netif_running(dev)) { 1652 mv643xx_eth_stop(dev); 1653 if (mv643xx_eth_open(dev)) { 1654 netdev_err(dev, 1655 "fatal error on re-opening device after ring param change\n"); 1656 return -ENOMEM; 1657 } 1658 } 1659 1660 return 0; 1661 } 1662 1663 1664 static int 1665 mv643xx_eth_set_features(struct net_device *dev, netdev_features_t features) 1666 { 1667 struct mv643xx_eth_private *mp = netdev_priv(dev); 1668 bool rx_csum = features & NETIF_F_RXCSUM; 1669 1670 wrlp(mp, PORT_CONFIG, rx_csum ? 0x02000000 : 0x00000000); 1671 1672 return 0; 1673 } 1674 1675 static void mv643xx_eth_get_strings(struct net_device *dev, 1676 uint32_t stringset, uint8_t *data) 1677 { 1678 int i; 1679 1680 if (stringset == ETH_SS_STATS) { 1681 for (i = 0; i < ARRAY_SIZE(mv643xx_eth_stats); i++) { 1682 memcpy(data + i * ETH_GSTRING_LEN, 1683 mv643xx_eth_stats[i].stat_string, 1684 ETH_GSTRING_LEN); 1685 } 1686 } 1687 } 1688 1689 static void mv643xx_eth_get_ethtool_stats(struct net_device *dev, 1690 struct ethtool_stats *stats, 1691 uint64_t *data) 1692 { 1693 struct mv643xx_eth_private *mp = netdev_priv(dev); 1694 int i; 1695 1696 mv643xx_eth_get_stats(dev); 1697 mib_counters_update(mp); 1698 1699 for (i = 0; i < ARRAY_SIZE(mv643xx_eth_stats); i++) { 1700 const struct mv643xx_eth_stats *stat; 1701 void *p; 1702 1703 stat = mv643xx_eth_stats + i; 1704 1705 if (stat->netdev_off >= 0) 1706 p = ((void *)mp->dev) + stat->netdev_off; 1707 else 1708 p = ((void *)mp) + stat->mp_off; 1709 1710 data[i] = (stat->sizeof_stat == 8) ? 1711 *(uint64_t *)p : *(uint32_t *)p; 1712 } 1713 } 1714 1715 static int mv643xx_eth_get_sset_count(struct net_device *dev, int sset) 1716 { 1717 if (sset == ETH_SS_STATS) 1718 return ARRAY_SIZE(mv643xx_eth_stats); 1719 1720 return -EOPNOTSUPP; 1721 } 1722 1723 static const struct ethtool_ops mv643xx_eth_ethtool_ops = { 1724 .get_settings = mv643xx_eth_get_settings, 1725 .set_settings = mv643xx_eth_set_settings, 1726 .get_drvinfo = mv643xx_eth_get_drvinfo, 1727 .nway_reset = mv643xx_eth_nway_reset, 1728 .get_link = ethtool_op_get_link, 1729 .get_coalesce = mv643xx_eth_get_coalesce, 1730 .set_coalesce = mv643xx_eth_set_coalesce, 1731 .get_ringparam = mv643xx_eth_get_ringparam, 1732 .set_ringparam = mv643xx_eth_set_ringparam, 1733 .get_strings = mv643xx_eth_get_strings, 1734 .get_ethtool_stats = mv643xx_eth_get_ethtool_stats, 1735 .get_sset_count = mv643xx_eth_get_sset_count, 1736 .get_ts_info = ethtool_op_get_ts_info, 1737 .get_wol = mv643xx_eth_get_wol, 1738 .set_wol = mv643xx_eth_set_wol, 1739 }; 1740 1741 1742 /* address handling *********************************************************/ 1743 static void uc_addr_get(struct mv643xx_eth_private *mp, unsigned char *addr) 1744 { 1745 unsigned int mac_h = rdlp(mp, MAC_ADDR_HIGH); 1746 unsigned int mac_l = rdlp(mp, MAC_ADDR_LOW); 1747 1748 addr[0] = (mac_h >> 24) & 0xff; 1749 addr[1] = (mac_h >> 16) & 0xff; 1750 addr[2] = (mac_h >> 8) & 0xff; 1751 addr[3] = mac_h & 0xff; 1752 addr[4] = (mac_l >> 8) & 0xff; 1753 addr[5] = mac_l & 0xff; 1754 } 1755 1756 static void uc_addr_set(struct mv643xx_eth_private *mp, unsigned char *addr) 1757 { 1758 wrlp(mp, MAC_ADDR_HIGH, 1759 (addr[0] << 24) | (addr[1] << 16) | (addr[2] << 8) | addr[3]); 1760 wrlp(mp, MAC_ADDR_LOW, (addr[4] << 8) | addr[5]); 1761 } 1762 1763 static u32 uc_addr_filter_mask(struct net_device *dev) 1764 { 1765 struct netdev_hw_addr *ha; 1766 u32 nibbles; 1767 1768 if (dev->flags & IFF_PROMISC) 1769 return 0; 1770 1771 nibbles = 1 << (dev->dev_addr[5] & 0x0f); 1772 netdev_for_each_uc_addr(ha, dev) { 1773 if (memcmp(dev->dev_addr, ha->addr, 5)) 1774 return 0; 1775 if ((dev->dev_addr[5] ^ ha->addr[5]) & 0xf0) 1776 return 0; 1777 1778 nibbles |= 1 << (ha->addr[5] & 0x0f); 1779 } 1780 1781 return nibbles; 1782 } 1783 1784 static void mv643xx_eth_program_unicast_filter(struct net_device *dev) 1785 { 1786 struct mv643xx_eth_private *mp = netdev_priv(dev); 1787 u32 port_config; 1788 u32 nibbles; 1789 int i; 1790 1791 uc_addr_set(mp, dev->dev_addr); 1792 1793 port_config = rdlp(mp, PORT_CONFIG) & ~UNICAST_PROMISCUOUS_MODE; 1794 1795 nibbles = uc_addr_filter_mask(dev); 1796 if (!nibbles) { 1797 port_config |= UNICAST_PROMISCUOUS_MODE; 1798 nibbles = 0xffff; 1799 } 1800 1801 for (i = 0; i < 16; i += 4) { 1802 int off = UNICAST_TABLE(mp->port_num) + i; 1803 u32 v; 1804 1805 v = 0; 1806 if (nibbles & 1) 1807 v |= 0x00000001; 1808 if (nibbles & 2) 1809 v |= 0x00000100; 1810 if (nibbles & 4) 1811 v |= 0x00010000; 1812 if (nibbles & 8) 1813 v |= 0x01000000; 1814 nibbles >>= 4; 1815 1816 wrl(mp, off, v); 1817 } 1818 1819 wrlp(mp, PORT_CONFIG, port_config); 1820 } 1821 1822 static int addr_crc(unsigned char *addr) 1823 { 1824 int crc = 0; 1825 int i; 1826 1827 for (i = 0; i < 6; i++) { 1828 int j; 1829 1830 crc = (crc ^ addr[i]) << 8; 1831 for (j = 7; j >= 0; j--) { 1832 if (crc & (0x100 << j)) 1833 crc ^= 0x107 << j; 1834 } 1835 } 1836 1837 return crc; 1838 } 1839 1840 static void mv643xx_eth_program_multicast_filter(struct net_device *dev) 1841 { 1842 struct mv643xx_eth_private *mp = netdev_priv(dev); 1843 u32 *mc_spec; 1844 u32 *mc_other; 1845 struct netdev_hw_addr *ha; 1846 int i; 1847 1848 if (dev->flags & (IFF_PROMISC | IFF_ALLMULTI)) { 1849 int port_num; 1850 u32 accept; 1851 1852 oom: 1853 port_num = mp->port_num; 1854 accept = 0x01010101; 1855 for (i = 0; i < 0x100; i += 4) { 1856 wrl(mp, SPECIAL_MCAST_TABLE(port_num) + i, accept); 1857 wrl(mp, OTHER_MCAST_TABLE(port_num) + i, accept); 1858 } 1859 return; 1860 } 1861 1862 mc_spec = kzalloc(0x200, GFP_ATOMIC); 1863 if (mc_spec == NULL) 1864 goto oom; 1865 mc_other = mc_spec + (0x100 >> 2); 1866 1867 netdev_for_each_mc_addr(ha, dev) { 1868 u8 *a = ha->addr; 1869 u32 *table; 1870 int entry; 1871 1872 if (memcmp(a, "\x01\x00\x5e\x00\x00", 5) == 0) { 1873 table = mc_spec; 1874 entry = a[5]; 1875 } else { 1876 table = mc_other; 1877 entry = addr_crc(a); 1878 } 1879 1880 table[entry >> 2] |= 1 << (8 * (entry & 3)); 1881 } 1882 1883 for (i = 0; i < 0x100; i += 4) { 1884 wrl(mp, SPECIAL_MCAST_TABLE(mp->port_num) + i, mc_spec[i >> 2]); 1885 wrl(mp, OTHER_MCAST_TABLE(mp->port_num) + i, mc_other[i >> 2]); 1886 } 1887 1888 kfree(mc_spec); 1889 } 1890 1891 static void mv643xx_eth_set_rx_mode(struct net_device *dev) 1892 { 1893 mv643xx_eth_program_unicast_filter(dev); 1894 mv643xx_eth_program_multicast_filter(dev); 1895 } 1896 1897 static int mv643xx_eth_set_mac_address(struct net_device *dev, void *addr) 1898 { 1899 struct sockaddr *sa = addr; 1900 1901 if (!is_valid_ether_addr(sa->sa_data)) 1902 return -EADDRNOTAVAIL; 1903 1904 memcpy(dev->dev_addr, sa->sa_data, ETH_ALEN); 1905 1906 netif_addr_lock_bh(dev); 1907 mv643xx_eth_program_unicast_filter(dev); 1908 netif_addr_unlock_bh(dev); 1909 1910 return 0; 1911 } 1912 1913 1914 /* rx/tx queue initialisation ***********************************************/ 1915 static int rxq_init(struct mv643xx_eth_private *mp, int index) 1916 { 1917 struct rx_queue *rxq = mp->rxq + index; 1918 struct rx_desc *rx_desc; 1919 int size; 1920 int i; 1921 1922 rxq->index = index; 1923 1924 rxq->rx_ring_size = mp->rx_ring_size; 1925 1926 rxq->rx_desc_count = 0; 1927 rxq->rx_curr_desc = 0; 1928 rxq->rx_used_desc = 0; 1929 1930 size = rxq->rx_ring_size * sizeof(struct rx_desc); 1931 1932 if (index == 0 && size <= mp->rx_desc_sram_size) { 1933 rxq->rx_desc_area = ioremap(mp->rx_desc_sram_addr, 1934 mp->rx_desc_sram_size); 1935 rxq->rx_desc_dma = mp->rx_desc_sram_addr; 1936 } else { 1937 rxq->rx_desc_area = dma_alloc_coherent(mp->dev->dev.parent, 1938 size, &rxq->rx_desc_dma, 1939 GFP_KERNEL); 1940 } 1941 1942 if (rxq->rx_desc_area == NULL) { 1943 netdev_err(mp->dev, 1944 "can't allocate rx ring (%d bytes)\n", size); 1945 goto out; 1946 } 1947 memset(rxq->rx_desc_area, 0, size); 1948 1949 rxq->rx_desc_area_size = size; 1950 rxq->rx_skb = kcalloc(rxq->rx_ring_size, sizeof(*rxq->rx_skb), 1951 GFP_KERNEL); 1952 if (rxq->rx_skb == NULL) 1953 goto out_free; 1954 1955 rx_desc = rxq->rx_desc_area; 1956 for (i = 0; i < rxq->rx_ring_size; i++) { 1957 int nexti; 1958 1959 nexti = i + 1; 1960 if (nexti == rxq->rx_ring_size) 1961 nexti = 0; 1962 1963 rx_desc[i].next_desc_ptr = rxq->rx_desc_dma + 1964 nexti * sizeof(struct rx_desc); 1965 } 1966 1967 return 0; 1968 1969 1970 out_free: 1971 if (index == 0 && size <= mp->rx_desc_sram_size) 1972 iounmap(rxq->rx_desc_area); 1973 else 1974 dma_free_coherent(mp->dev->dev.parent, size, 1975 rxq->rx_desc_area, 1976 rxq->rx_desc_dma); 1977 1978 out: 1979 return -ENOMEM; 1980 } 1981 1982 static void rxq_deinit(struct rx_queue *rxq) 1983 { 1984 struct mv643xx_eth_private *mp = rxq_to_mp(rxq); 1985 int i; 1986 1987 rxq_disable(rxq); 1988 1989 for (i = 0; i < rxq->rx_ring_size; i++) { 1990 if (rxq->rx_skb[i]) { 1991 dev_kfree_skb(rxq->rx_skb[i]); 1992 rxq->rx_desc_count--; 1993 } 1994 } 1995 1996 if (rxq->rx_desc_count) { 1997 netdev_err(mp->dev, "error freeing rx ring -- %d skbs stuck\n", 1998 rxq->rx_desc_count); 1999 } 2000 2001 if (rxq->index == 0 && 2002 rxq->rx_desc_area_size <= mp->rx_desc_sram_size) 2003 iounmap(rxq->rx_desc_area); 2004 else 2005 dma_free_coherent(mp->dev->dev.parent, rxq->rx_desc_area_size, 2006 rxq->rx_desc_area, rxq->rx_desc_dma); 2007 2008 kfree(rxq->rx_skb); 2009 } 2010 2011 static int txq_init(struct mv643xx_eth_private *mp, int index) 2012 { 2013 struct tx_queue *txq = mp->txq + index; 2014 struct tx_desc *tx_desc; 2015 int size; 2016 int ret; 2017 int i; 2018 2019 txq->index = index; 2020 2021 txq->tx_ring_size = mp->tx_ring_size; 2022 2023 /* A queue must always have room for at least one skb. 2024 * Therefore, stop the queue when the free entries reaches 2025 * the maximum number of descriptors per skb. 2026 */ 2027 txq->tx_stop_threshold = txq->tx_ring_size - MV643XX_MAX_SKB_DESCS; 2028 txq->tx_wake_threshold = txq->tx_stop_threshold / 2; 2029 2030 txq->tx_desc_count = 0; 2031 txq->tx_curr_desc = 0; 2032 txq->tx_used_desc = 0; 2033 2034 size = txq->tx_ring_size * sizeof(struct tx_desc); 2035 2036 if (index == 0 && size <= mp->tx_desc_sram_size) { 2037 txq->tx_desc_area = ioremap(mp->tx_desc_sram_addr, 2038 mp->tx_desc_sram_size); 2039 txq->tx_desc_dma = mp->tx_desc_sram_addr; 2040 } else { 2041 txq->tx_desc_area = dma_alloc_coherent(mp->dev->dev.parent, 2042 size, &txq->tx_desc_dma, 2043 GFP_KERNEL); 2044 } 2045 2046 if (txq->tx_desc_area == NULL) { 2047 netdev_err(mp->dev, 2048 "can't allocate tx ring (%d bytes)\n", size); 2049 return -ENOMEM; 2050 } 2051 memset(txq->tx_desc_area, 0, size); 2052 2053 txq->tx_desc_area_size = size; 2054 2055 tx_desc = txq->tx_desc_area; 2056 for (i = 0; i < txq->tx_ring_size; i++) { 2057 struct tx_desc *txd = tx_desc + i; 2058 int nexti; 2059 2060 nexti = i + 1; 2061 if (nexti == txq->tx_ring_size) 2062 nexti = 0; 2063 2064 txd->cmd_sts = 0; 2065 txd->next_desc_ptr = txq->tx_desc_dma + 2066 nexti * sizeof(struct tx_desc); 2067 } 2068 2069 txq->tx_desc_mapping = kcalloc(txq->tx_ring_size, sizeof(char), 2070 GFP_KERNEL); 2071 if (!txq->tx_desc_mapping) { 2072 ret = -ENOMEM; 2073 goto err_free_desc_area; 2074 } 2075 2076 /* Allocate DMA buffers for TSO MAC/IP/TCP headers */ 2077 txq->tso_hdrs = dma_alloc_coherent(mp->dev->dev.parent, 2078 txq->tx_ring_size * TSO_HEADER_SIZE, 2079 &txq->tso_hdrs_dma, GFP_KERNEL); 2080 if (txq->tso_hdrs == NULL) { 2081 ret = -ENOMEM; 2082 goto err_free_desc_mapping; 2083 } 2084 skb_queue_head_init(&txq->tx_skb); 2085 2086 return 0; 2087 2088 err_free_desc_mapping: 2089 kfree(txq->tx_desc_mapping); 2090 err_free_desc_area: 2091 if (index == 0 && size <= mp->tx_desc_sram_size) 2092 iounmap(txq->tx_desc_area); 2093 else 2094 dma_free_coherent(mp->dev->dev.parent, txq->tx_desc_area_size, 2095 txq->tx_desc_area, txq->tx_desc_dma); 2096 return ret; 2097 } 2098 2099 static void txq_deinit(struct tx_queue *txq) 2100 { 2101 struct mv643xx_eth_private *mp = txq_to_mp(txq); 2102 2103 txq_disable(txq); 2104 txq_reclaim(txq, txq->tx_ring_size, 1); 2105 2106 BUG_ON(txq->tx_used_desc != txq->tx_curr_desc); 2107 2108 if (txq->index == 0 && 2109 txq->tx_desc_area_size <= mp->tx_desc_sram_size) 2110 iounmap(txq->tx_desc_area); 2111 else 2112 dma_free_coherent(mp->dev->dev.parent, txq->tx_desc_area_size, 2113 txq->tx_desc_area, txq->tx_desc_dma); 2114 kfree(txq->tx_desc_mapping); 2115 2116 if (txq->tso_hdrs) 2117 dma_free_coherent(mp->dev->dev.parent, 2118 txq->tx_ring_size * TSO_HEADER_SIZE, 2119 txq->tso_hdrs, txq->tso_hdrs_dma); 2120 } 2121 2122 2123 /* netdev ops and related ***************************************************/ 2124 static int mv643xx_eth_collect_events(struct mv643xx_eth_private *mp) 2125 { 2126 u32 int_cause; 2127 u32 int_cause_ext; 2128 2129 int_cause = rdlp(mp, INT_CAUSE) & mp->int_mask; 2130 if (int_cause == 0) 2131 return 0; 2132 2133 int_cause_ext = 0; 2134 if (int_cause & INT_EXT) { 2135 int_cause &= ~INT_EXT; 2136 int_cause_ext = rdlp(mp, INT_CAUSE_EXT); 2137 } 2138 2139 if (int_cause) { 2140 wrlp(mp, INT_CAUSE, ~int_cause); 2141 mp->work_tx_end |= ((int_cause & INT_TX_END) >> 19) & 2142 ~(rdlp(mp, TXQ_COMMAND) & 0xff); 2143 mp->work_rx |= (int_cause & INT_RX) >> 2; 2144 } 2145 2146 int_cause_ext &= INT_EXT_LINK_PHY | INT_EXT_TX; 2147 if (int_cause_ext) { 2148 wrlp(mp, INT_CAUSE_EXT, ~int_cause_ext); 2149 if (int_cause_ext & INT_EXT_LINK_PHY) 2150 mp->work_link = 1; 2151 mp->work_tx |= int_cause_ext & INT_EXT_TX; 2152 } 2153 2154 return 1; 2155 } 2156 2157 static irqreturn_t mv643xx_eth_irq(int irq, void *dev_id) 2158 { 2159 struct net_device *dev = (struct net_device *)dev_id; 2160 struct mv643xx_eth_private *mp = netdev_priv(dev); 2161 2162 if (unlikely(!mv643xx_eth_collect_events(mp))) 2163 return IRQ_NONE; 2164 2165 wrlp(mp, INT_MASK, 0); 2166 napi_schedule(&mp->napi); 2167 2168 return IRQ_HANDLED; 2169 } 2170 2171 static void handle_link_event(struct mv643xx_eth_private *mp) 2172 { 2173 struct net_device *dev = mp->dev; 2174 u32 port_status; 2175 int speed; 2176 int duplex; 2177 int fc; 2178 2179 port_status = rdlp(mp, PORT_STATUS); 2180 if (!(port_status & LINK_UP)) { 2181 if (netif_carrier_ok(dev)) { 2182 int i; 2183 2184 netdev_info(dev, "link down\n"); 2185 2186 netif_carrier_off(dev); 2187 2188 for (i = 0; i < mp->txq_count; i++) { 2189 struct tx_queue *txq = mp->txq + i; 2190 2191 txq_reclaim(txq, txq->tx_ring_size, 1); 2192 txq_reset_hw_ptr(txq); 2193 } 2194 } 2195 return; 2196 } 2197 2198 switch (port_status & PORT_SPEED_MASK) { 2199 case PORT_SPEED_10: 2200 speed = 10; 2201 break; 2202 case PORT_SPEED_100: 2203 speed = 100; 2204 break; 2205 case PORT_SPEED_1000: 2206 speed = 1000; 2207 break; 2208 default: 2209 speed = -1; 2210 break; 2211 } 2212 duplex = (port_status & FULL_DUPLEX) ? 1 : 0; 2213 fc = (port_status & FLOW_CONTROL_ENABLED) ? 1 : 0; 2214 2215 netdev_info(dev, "link up, %d Mb/s, %s duplex, flow control %sabled\n", 2216 speed, duplex ? "full" : "half", fc ? "en" : "dis"); 2217 2218 if (!netif_carrier_ok(dev)) 2219 netif_carrier_on(dev); 2220 } 2221 2222 static int mv643xx_eth_poll(struct napi_struct *napi, int budget) 2223 { 2224 struct mv643xx_eth_private *mp; 2225 int work_done; 2226 2227 mp = container_of(napi, struct mv643xx_eth_private, napi); 2228 2229 if (unlikely(mp->oom)) { 2230 mp->oom = 0; 2231 del_timer(&mp->rx_oom); 2232 } 2233 2234 work_done = 0; 2235 while (work_done < budget) { 2236 u8 queue_mask; 2237 int queue; 2238 int work_tbd; 2239 2240 if (mp->work_link) { 2241 mp->work_link = 0; 2242 handle_link_event(mp); 2243 work_done++; 2244 continue; 2245 } 2246 2247 queue_mask = mp->work_tx | mp->work_tx_end | mp->work_rx; 2248 if (likely(!mp->oom)) 2249 queue_mask |= mp->work_rx_refill; 2250 2251 if (!queue_mask) { 2252 if (mv643xx_eth_collect_events(mp)) 2253 continue; 2254 break; 2255 } 2256 2257 queue = fls(queue_mask) - 1; 2258 queue_mask = 1 << queue; 2259 2260 work_tbd = budget - work_done; 2261 if (work_tbd > 16) 2262 work_tbd = 16; 2263 2264 if (mp->work_tx_end & queue_mask) { 2265 txq_kick(mp->txq + queue); 2266 } else if (mp->work_tx & queue_mask) { 2267 work_done += txq_reclaim(mp->txq + queue, work_tbd, 0); 2268 txq_maybe_wake(mp->txq + queue); 2269 } else if (mp->work_rx & queue_mask) { 2270 work_done += rxq_process(mp->rxq + queue, work_tbd); 2271 } else if (!mp->oom && (mp->work_rx_refill & queue_mask)) { 2272 work_done += rxq_refill(mp->rxq + queue, work_tbd); 2273 } else { 2274 BUG(); 2275 } 2276 } 2277 2278 if (work_done < budget) { 2279 if (mp->oom) 2280 mod_timer(&mp->rx_oom, jiffies + (HZ / 10)); 2281 napi_complete(napi); 2282 wrlp(mp, INT_MASK, mp->int_mask); 2283 } 2284 2285 return work_done; 2286 } 2287 2288 static inline void oom_timer_wrapper(unsigned long data) 2289 { 2290 struct mv643xx_eth_private *mp = (void *)data; 2291 2292 napi_schedule(&mp->napi); 2293 } 2294 2295 static void port_start(struct mv643xx_eth_private *mp) 2296 { 2297 u32 pscr; 2298 int i; 2299 2300 /* 2301 * Perform PHY reset, if there is a PHY. 2302 */ 2303 if (mp->phy != NULL) { 2304 struct ethtool_cmd cmd; 2305 2306 mv643xx_eth_get_settings(mp->dev, &cmd); 2307 phy_init_hw(mp->phy); 2308 mv643xx_eth_set_settings(mp->dev, &cmd); 2309 phy_start(mp->phy); 2310 } 2311 2312 /* 2313 * Configure basic link parameters. 2314 */ 2315 pscr = rdlp(mp, PORT_SERIAL_CONTROL); 2316 2317 pscr |= SERIAL_PORT_ENABLE; 2318 wrlp(mp, PORT_SERIAL_CONTROL, pscr); 2319 2320 pscr |= DO_NOT_FORCE_LINK_FAIL; 2321 if (mp->phy == NULL) 2322 pscr |= FORCE_LINK_PASS; 2323 wrlp(mp, PORT_SERIAL_CONTROL, pscr); 2324 2325 /* 2326 * Configure TX path and queues. 2327 */ 2328 tx_set_rate(mp, 1000000000, 16777216); 2329 for (i = 0; i < mp->txq_count; i++) { 2330 struct tx_queue *txq = mp->txq + i; 2331 2332 txq_reset_hw_ptr(txq); 2333 txq_set_rate(txq, 1000000000, 16777216); 2334 txq_set_fixed_prio_mode(txq); 2335 } 2336 2337 /* 2338 * Receive all unmatched unicast, TCP, UDP, BPDU and broadcast 2339 * frames to RX queue #0, and include the pseudo-header when 2340 * calculating receive checksums. 2341 */ 2342 mv643xx_eth_set_features(mp->dev, mp->dev->features); 2343 2344 /* 2345 * Treat BPDUs as normal multicasts, and disable partition mode. 2346 */ 2347 wrlp(mp, PORT_CONFIG_EXT, 0x00000000); 2348 2349 /* 2350 * Add configured unicast addresses to address filter table. 2351 */ 2352 mv643xx_eth_program_unicast_filter(mp->dev); 2353 2354 /* 2355 * Enable the receive queues. 2356 */ 2357 for (i = 0; i < mp->rxq_count; i++) { 2358 struct rx_queue *rxq = mp->rxq + i; 2359 u32 addr; 2360 2361 addr = (u32)rxq->rx_desc_dma; 2362 addr += rxq->rx_curr_desc * sizeof(struct rx_desc); 2363 wrlp(mp, RXQ_CURRENT_DESC_PTR(i), addr); 2364 2365 rxq_enable(rxq); 2366 } 2367 } 2368 2369 static void mv643xx_eth_recalc_skb_size(struct mv643xx_eth_private *mp) 2370 { 2371 int skb_size; 2372 2373 /* 2374 * Reserve 2+14 bytes for an ethernet header (the hardware 2375 * automatically prepends 2 bytes of dummy data to each 2376 * received packet), 16 bytes for up to four VLAN tags, and 2377 * 4 bytes for the trailing FCS -- 36 bytes total. 2378 */ 2379 skb_size = mp->dev->mtu + 36; 2380 2381 /* 2382 * Make sure that the skb size is a multiple of 8 bytes, as 2383 * the lower three bits of the receive descriptor's buffer 2384 * size field are ignored by the hardware. 2385 */ 2386 mp->skb_size = (skb_size + 7) & ~7; 2387 2388 /* 2389 * If NET_SKB_PAD is smaller than a cache line, 2390 * netdev_alloc_skb() will cause skb->data to be misaligned 2391 * to a cache line boundary. If this is the case, include 2392 * some extra space to allow re-aligning the data area. 2393 */ 2394 mp->skb_size += SKB_DMA_REALIGN; 2395 } 2396 2397 static int mv643xx_eth_open(struct net_device *dev) 2398 { 2399 struct mv643xx_eth_private *mp = netdev_priv(dev); 2400 int err; 2401 int i; 2402 2403 wrlp(mp, INT_CAUSE, 0); 2404 wrlp(mp, INT_CAUSE_EXT, 0); 2405 rdlp(mp, INT_CAUSE_EXT); 2406 2407 err = request_irq(dev->irq, mv643xx_eth_irq, 2408 IRQF_SHARED, dev->name, dev); 2409 if (err) { 2410 netdev_err(dev, "can't assign irq\n"); 2411 return -EAGAIN; 2412 } 2413 2414 mv643xx_eth_recalc_skb_size(mp); 2415 2416 napi_enable(&mp->napi); 2417 2418 mp->int_mask = INT_EXT; 2419 2420 for (i = 0; i < mp->rxq_count; i++) { 2421 err = rxq_init(mp, i); 2422 if (err) { 2423 while (--i >= 0) 2424 rxq_deinit(mp->rxq + i); 2425 goto out; 2426 } 2427 2428 rxq_refill(mp->rxq + i, INT_MAX); 2429 mp->int_mask |= INT_RX_0 << i; 2430 } 2431 2432 if (mp->oom) { 2433 mp->rx_oom.expires = jiffies + (HZ / 10); 2434 add_timer(&mp->rx_oom); 2435 } 2436 2437 for (i = 0; i < mp->txq_count; i++) { 2438 err = txq_init(mp, i); 2439 if (err) { 2440 while (--i >= 0) 2441 txq_deinit(mp->txq + i); 2442 goto out_free; 2443 } 2444 mp->int_mask |= INT_TX_END_0 << i; 2445 } 2446 2447 add_timer(&mp->mib_counters_timer); 2448 port_start(mp); 2449 2450 wrlp(mp, INT_MASK_EXT, INT_EXT_LINK_PHY | INT_EXT_TX); 2451 wrlp(mp, INT_MASK, mp->int_mask); 2452 2453 return 0; 2454 2455 2456 out_free: 2457 for (i = 0; i < mp->rxq_count; i++) 2458 rxq_deinit(mp->rxq + i); 2459 out: 2460 free_irq(dev->irq, dev); 2461 2462 return err; 2463 } 2464 2465 static void port_reset(struct mv643xx_eth_private *mp) 2466 { 2467 unsigned int data; 2468 int i; 2469 2470 for (i = 0; i < mp->rxq_count; i++) 2471 rxq_disable(mp->rxq + i); 2472 for (i = 0; i < mp->txq_count; i++) 2473 txq_disable(mp->txq + i); 2474 2475 while (1) { 2476 u32 ps = rdlp(mp, PORT_STATUS); 2477 2478 if ((ps & (TX_IN_PROGRESS | TX_FIFO_EMPTY)) == TX_FIFO_EMPTY) 2479 break; 2480 udelay(10); 2481 } 2482 2483 /* Reset the Enable bit in the Configuration Register */ 2484 data = rdlp(mp, PORT_SERIAL_CONTROL); 2485 data &= ~(SERIAL_PORT_ENABLE | 2486 DO_NOT_FORCE_LINK_FAIL | 2487 FORCE_LINK_PASS); 2488 wrlp(mp, PORT_SERIAL_CONTROL, data); 2489 } 2490 2491 static int mv643xx_eth_stop(struct net_device *dev) 2492 { 2493 struct mv643xx_eth_private *mp = netdev_priv(dev); 2494 int i; 2495 2496 wrlp(mp, INT_MASK_EXT, 0x00000000); 2497 wrlp(mp, INT_MASK, 0x00000000); 2498 rdlp(mp, INT_MASK); 2499 2500 napi_disable(&mp->napi); 2501 2502 del_timer_sync(&mp->rx_oom); 2503 2504 netif_carrier_off(dev); 2505 if (mp->phy) 2506 phy_stop(mp->phy); 2507 free_irq(dev->irq, dev); 2508 2509 port_reset(mp); 2510 mv643xx_eth_get_stats(dev); 2511 mib_counters_update(mp); 2512 del_timer_sync(&mp->mib_counters_timer); 2513 2514 for (i = 0; i < mp->rxq_count; i++) 2515 rxq_deinit(mp->rxq + i); 2516 for (i = 0; i < mp->txq_count; i++) 2517 txq_deinit(mp->txq + i); 2518 2519 return 0; 2520 } 2521 2522 static int mv643xx_eth_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) 2523 { 2524 struct mv643xx_eth_private *mp = netdev_priv(dev); 2525 int ret; 2526 2527 if (mp->phy == NULL) 2528 return -ENOTSUPP; 2529 2530 ret = phy_mii_ioctl(mp->phy, ifr, cmd); 2531 if (!ret) 2532 mv643xx_eth_adjust_link(dev); 2533 return ret; 2534 } 2535 2536 static int mv643xx_eth_change_mtu(struct net_device *dev, int new_mtu) 2537 { 2538 struct mv643xx_eth_private *mp = netdev_priv(dev); 2539 2540 if (new_mtu < 64 || new_mtu > 9500) 2541 return -EINVAL; 2542 2543 dev->mtu = new_mtu; 2544 mv643xx_eth_recalc_skb_size(mp); 2545 tx_set_rate(mp, 1000000000, 16777216); 2546 2547 if (!netif_running(dev)) 2548 return 0; 2549 2550 /* 2551 * Stop and then re-open the interface. This will allocate RX 2552 * skbs of the new MTU. 2553 * There is a possible danger that the open will not succeed, 2554 * due to memory being full. 2555 */ 2556 mv643xx_eth_stop(dev); 2557 if (mv643xx_eth_open(dev)) { 2558 netdev_err(dev, 2559 "fatal error on re-opening device after MTU change\n"); 2560 } 2561 2562 return 0; 2563 } 2564 2565 static void tx_timeout_task(struct work_struct *ugly) 2566 { 2567 struct mv643xx_eth_private *mp; 2568 2569 mp = container_of(ugly, struct mv643xx_eth_private, tx_timeout_task); 2570 if (netif_running(mp->dev)) { 2571 netif_tx_stop_all_queues(mp->dev); 2572 port_reset(mp); 2573 port_start(mp); 2574 netif_tx_wake_all_queues(mp->dev); 2575 } 2576 } 2577 2578 static void mv643xx_eth_tx_timeout(struct net_device *dev) 2579 { 2580 struct mv643xx_eth_private *mp = netdev_priv(dev); 2581 2582 netdev_info(dev, "tx timeout\n"); 2583 2584 schedule_work(&mp->tx_timeout_task); 2585 } 2586 2587 #ifdef CONFIG_NET_POLL_CONTROLLER 2588 static void mv643xx_eth_netpoll(struct net_device *dev) 2589 { 2590 struct mv643xx_eth_private *mp = netdev_priv(dev); 2591 2592 wrlp(mp, INT_MASK, 0x00000000); 2593 rdlp(mp, INT_MASK); 2594 2595 mv643xx_eth_irq(dev->irq, dev); 2596 2597 wrlp(mp, INT_MASK, mp->int_mask); 2598 } 2599 #endif 2600 2601 2602 /* platform glue ************************************************************/ 2603 static void 2604 mv643xx_eth_conf_mbus_windows(struct mv643xx_eth_shared_private *msp, 2605 const struct mbus_dram_target_info *dram) 2606 { 2607 void __iomem *base = msp->base; 2608 u32 win_enable; 2609 u32 win_protect; 2610 int i; 2611 2612 for (i = 0; i < 6; i++) { 2613 writel(0, base + WINDOW_BASE(i)); 2614 writel(0, base + WINDOW_SIZE(i)); 2615 if (i < 4) 2616 writel(0, base + WINDOW_REMAP_HIGH(i)); 2617 } 2618 2619 win_enable = 0x3f; 2620 win_protect = 0; 2621 2622 for (i = 0; i < dram->num_cs; i++) { 2623 const struct mbus_dram_window *cs = dram->cs + i; 2624 2625 writel((cs->base & 0xffff0000) | 2626 (cs->mbus_attr << 8) | 2627 dram->mbus_dram_target_id, base + WINDOW_BASE(i)); 2628 writel((cs->size - 1) & 0xffff0000, base + WINDOW_SIZE(i)); 2629 2630 win_enable &= ~(1 << i); 2631 win_protect |= 3 << (2 * i); 2632 } 2633 2634 writel(win_enable, base + WINDOW_BAR_ENABLE); 2635 msp->win_protect = win_protect; 2636 } 2637 2638 static void infer_hw_params(struct mv643xx_eth_shared_private *msp) 2639 { 2640 /* 2641 * Check whether we have a 14-bit coal limit field in bits 2642 * [21:8], or a 16-bit coal limit in bits [25,21:7] of the 2643 * SDMA config register. 2644 */ 2645 writel(0x02000000, msp->base + 0x0400 + SDMA_CONFIG); 2646 if (readl(msp->base + 0x0400 + SDMA_CONFIG) & 0x02000000) 2647 msp->extended_rx_coal_limit = 1; 2648 else 2649 msp->extended_rx_coal_limit = 0; 2650 2651 /* 2652 * Check whether the MAC supports TX rate control, and if 2653 * yes, whether its associated registers are in the old or 2654 * the new place. 2655 */ 2656 writel(1, msp->base + 0x0400 + TX_BW_MTU_MOVED); 2657 if (readl(msp->base + 0x0400 + TX_BW_MTU_MOVED) & 1) { 2658 msp->tx_bw_control = TX_BW_CONTROL_NEW_LAYOUT; 2659 } else { 2660 writel(7, msp->base + 0x0400 + TX_BW_RATE); 2661 if (readl(msp->base + 0x0400 + TX_BW_RATE) & 7) 2662 msp->tx_bw_control = TX_BW_CONTROL_OLD_LAYOUT; 2663 else 2664 msp->tx_bw_control = TX_BW_CONTROL_ABSENT; 2665 } 2666 } 2667 2668 #if defined(CONFIG_OF) 2669 static const struct of_device_id mv643xx_eth_shared_ids[] = { 2670 { .compatible = "marvell,orion-eth", }, 2671 { .compatible = "marvell,kirkwood-eth", }, 2672 { } 2673 }; 2674 MODULE_DEVICE_TABLE(of, mv643xx_eth_shared_ids); 2675 #endif 2676 2677 #if defined(CONFIG_OF) && !defined(CONFIG_MV64X60) 2678 #define mv643xx_eth_property(_np, _name, _v) \ 2679 do { \ 2680 u32 tmp; \ 2681 if (!of_property_read_u32(_np, "marvell," _name, &tmp)) \ 2682 _v = tmp; \ 2683 } while (0) 2684 2685 static struct platform_device *port_platdev[3]; 2686 2687 static int mv643xx_eth_shared_of_add_port(struct platform_device *pdev, 2688 struct device_node *pnp) 2689 { 2690 struct platform_device *ppdev; 2691 struct mv643xx_eth_platform_data ppd; 2692 struct resource res; 2693 const char *mac_addr; 2694 int ret; 2695 int dev_num = 0; 2696 2697 memset(&ppd, 0, sizeof(ppd)); 2698 ppd.shared = pdev; 2699 2700 memset(&res, 0, sizeof(res)); 2701 if (!of_irq_to_resource(pnp, 0, &res)) { 2702 dev_err(&pdev->dev, "missing interrupt on %s\n", pnp->name); 2703 return -EINVAL; 2704 } 2705 2706 if (of_property_read_u32(pnp, "reg", &ppd.port_number)) { 2707 dev_err(&pdev->dev, "missing reg property on %s\n", pnp->name); 2708 return -EINVAL; 2709 } 2710 2711 if (ppd.port_number >= 3) { 2712 dev_err(&pdev->dev, "invalid reg property on %s\n", pnp->name); 2713 return -EINVAL; 2714 } 2715 2716 while (dev_num < 3 && port_platdev[dev_num]) 2717 dev_num++; 2718 2719 if (dev_num == 3) { 2720 dev_err(&pdev->dev, "too many ports registered\n"); 2721 return -EINVAL; 2722 } 2723 2724 mac_addr = of_get_mac_address(pnp); 2725 if (mac_addr) 2726 memcpy(ppd.mac_addr, mac_addr, ETH_ALEN); 2727 2728 mv643xx_eth_property(pnp, "tx-queue-size", ppd.tx_queue_size); 2729 mv643xx_eth_property(pnp, "tx-sram-addr", ppd.tx_sram_addr); 2730 mv643xx_eth_property(pnp, "tx-sram-size", ppd.tx_sram_size); 2731 mv643xx_eth_property(pnp, "rx-queue-size", ppd.rx_queue_size); 2732 mv643xx_eth_property(pnp, "rx-sram-addr", ppd.rx_sram_addr); 2733 mv643xx_eth_property(pnp, "rx-sram-size", ppd.rx_sram_size); 2734 2735 ppd.phy_node = of_parse_phandle(pnp, "phy-handle", 0); 2736 if (!ppd.phy_node) { 2737 ppd.phy_addr = MV643XX_ETH_PHY_NONE; 2738 of_property_read_u32(pnp, "speed", &ppd.speed); 2739 of_property_read_u32(pnp, "duplex", &ppd.duplex); 2740 } 2741 2742 ppdev = platform_device_alloc(MV643XX_ETH_NAME, dev_num); 2743 if (!ppdev) 2744 return -ENOMEM; 2745 ppdev->dev.coherent_dma_mask = DMA_BIT_MASK(32); 2746 ppdev->dev.of_node = pnp; 2747 2748 ret = platform_device_add_resources(ppdev, &res, 1); 2749 if (ret) 2750 goto port_err; 2751 2752 ret = platform_device_add_data(ppdev, &ppd, sizeof(ppd)); 2753 if (ret) 2754 goto port_err; 2755 2756 ret = platform_device_add(ppdev); 2757 if (ret) 2758 goto port_err; 2759 2760 port_platdev[dev_num] = ppdev; 2761 2762 return 0; 2763 2764 port_err: 2765 platform_device_put(ppdev); 2766 return ret; 2767 } 2768 2769 static int mv643xx_eth_shared_of_probe(struct platform_device *pdev) 2770 { 2771 struct mv643xx_eth_shared_platform_data *pd; 2772 struct device_node *pnp, *np = pdev->dev.of_node; 2773 int ret; 2774 2775 /* bail out if not registered from DT */ 2776 if (!np) 2777 return 0; 2778 2779 pd = devm_kzalloc(&pdev->dev, sizeof(*pd), GFP_KERNEL); 2780 if (!pd) 2781 return -ENOMEM; 2782 pdev->dev.platform_data = pd; 2783 2784 mv643xx_eth_property(np, "tx-checksum-limit", pd->tx_csum_limit); 2785 2786 for_each_available_child_of_node(np, pnp) { 2787 ret = mv643xx_eth_shared_of_add_port(pdev, pnp); 2788 if (ret) 2789 return ret; 2790 } 2791 return 0; 2792 } 2793 2794 static void mv643xx_eth_shared_of_remove(void) 2795 { 2796 int n; 2797 2798 for (n = 0; n < 3; n++) { 2799 platform_device_del(port_platdev[n]); 2800 port_platdev[n] = NULL; 2801 } 2802 } 2803 #else 2804 static inline int mv643xx_eth_shared_of_probe(struct platform_device *pdev) 2805 { 2806 return 0; 2807 } 2808 2809 static inline void mv643xx_eth_shared_of_remove(void) 2810 { 2811 } 2812 #endif 2813 2814 static int mv643xx_eth_shared_probe(struct platform_device *pdev) 2815 { 2816 static int mv643xx_eth_version_printed; 2817 struct mv643xx_eth_shared_platform_data *pd; 2818 struct mv643xx_eth_shared_private *msp; 2819 const struct mbus_dram_target_info *dram; 2820 struct resource *res; 2821 int ret; 2822 2823 if (!mv643xx_eth_version_printed++) 2824 pr_notice("MV-643xx 10/100/1000 ethernet driver version %s\n", 2825 mv643xx_eth_driver_version); 2826 2827 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2828 if (res == NULL) 2829 return -EINVAL; 2830 2831 msp = devm_kzalloc(&pdev->dev, sizeof(*msp), GFP_KERNEL); 2832 if (msp == NULL) 2833 return -ENOMEM; 2834 platform_set_drvdata(pdev, msp); 2835 2836 msp->base = devm_ioremap(&pdev->dev, res->start, resource_size(res)); 2837 if (msp->base == NULL) 2838 return -ENOMEM; 2839 2840 msp->clk = devm_clk_get(&pdev->dev, NULL); 2841 if (!IS_ERR(msp->clk)) 2842 clk_prepare_enable(msp->clk); 2843 2844 /* 2845 * (Re-)program MBUS remapping windows if we are asked to. 2846 */ 2847 dram = mv_mbus_dram_info(); 2848 if (dram) 2849 mv643xx_eth_conf_mbus_windows(msp, dram); 2850 2851 ret = mv643xx_eth_shared_of_probe(pdev); 2852 if (ret) 2853 return ret; 2854 pd = dev_get_platdata(&pdev->dev); 2855 2856 msp->tx_csum_limit = (pd != NULL && pd->tx_csum_limit) ? 2857 pd->tx_csum_limit : 9 * 1024; 2858 infer_hw_params(msp); 2859 2860 return 0; 2861 } 2862 2863 static int mv643xx_eth_shared_remove(struct platform_device *pdev) 2864 { 2865 struct mv643xx_eth_shared_private *msp = platform_get_drvdata(pdev); 2866 2867 mv643xx_eth_shared_of_remove(); 2868 if (!IS_ERR(msp->clk)) 2869 clk_disable_unprepare(msp->clk); 2870 return 0; 2871 } 2872 2873 static struct platform_driver mv643xx_eth_shared_driver = { 2874 .probe = mv643xx_eth_shared_probe, 2875 .remove = mv643xx_eth_shared_remove, 2876 .driver = { 2877 .name = MV643XX_ETH_SHARED_NAME, 2878 .of_match_table = of_match_ptr(mv643xx_eth_shared_ids), 2879 }, 2880 }; 2881 2882 static void phy_addr_set(struct mv643xx_eth_private *mp, int phy_addr) 2883 { 2884 int addr_shift = 5 * mp->port_num; 2885 u32 data; 2886 2887 data = rdl(mp, PHY_ADDR); 2888 data &= ~(0x1f << addr_shift); 2889 data |= (phy_addr & 0x1f) << addr_shift; 2890 wrl(mp, PHY_ADDR, data); 2891 } 2892 2893 static int phy_addr_get(struct mv643xx_eth_private *mp) 2894 { 2895 unsigned int data; 2896 2897 data = rdl(mp, PHY_ADDR); 2898 2899 return (data >> (5 * mp->port_num)) & 0x1f; 2900 } 2901 2902 static void set_params(struct mv643xx_eth_private *mp, 2903 struct mv643xx_eth_platform_data *pd) 2904 { 2905 struct net_device *dev = mp->dev; 2906 unsigned int tx_ring_size; 2907 2908 if (is_valid_ether_addr(pd->mac_addr)) 2909 memcpy(dev->dev_addr, pd->mac_addr, ETH_ALEN); 2910 else 2911 uc_addr_get(mp, dev->dev_addr); 2912 2913 mp->rx_ring_size = DEFAULT_RX_QUEUE_SIZE; 2914 if (pd->rx_queue_size) 2915 mp->rx_ring_size = pd->rx_queue_size; 2916 mp->rx_desc_sram_addr = pd->rx_sram_addr; 2917 mp->rx_desc_sram_size = pd->rx_sram_size; 2918 2919 mp->rxq_count = pd->rx_queue_count ? : 1; 2920 2921 tx_ring_size = DEFAULT_TX_QUEUE_SIZE; 2922 if (pd->tx_queue_size) 2923 tx_ring_size = pd->tx_queue_size; 2924 2925 mp->tx_ring_size = clamp_t(unsigned int, tx_ring_size, 2926 MV643XX_MAX_SKB_DESCS * 2, 4096); 2927 if (mp->tx_ring_size != tx_ring_size) 2928 netdev_warn(dev, "TX queue size set to %u (requested %u)\n", 2929 mp->tx_ring_size, tx_ring_size); 2930 2931 mp->tx_desc_sram_addr = pd->tx_sram_addr; 2932 mp->tx_desc_sram_size = pd->tx_sram_size; 2933 2934 mp->txq_count = pd->tx_queue_count ? : 1; 2935 } 2936 2937 static struct phy_device *phy_scan(struct mv643xx_eth_private *mp, 2938 int phy_addr) 2939 { 2940 struct phy_device *phydev; 2941 int start; 2942 int num; 2943 int i; 2944 char phy_id[MII_BUS_ID_SIZE + 3]; 2945 2946 if (phy_addr == MV643XX_ETH_PHY_ADDR_DEFAULT) { 2947 start = phy_addr_get(mp) & 0x1f; 2948 num = 32; 2949 } else { 2950 start = phy_addr & 0x1f; 2951 num = 1; 2952 } 2953 2954 /* Attempt to connect to the PHY using orion-mdio */ 2955 phydev = ERR_PTR(-ENODEV); 2956 for (i = 0; i < num; i++) { 2957 int addr = (start + i) & 0x1f; 2958 2959 snprintf(phy_id, sizeof(phy_id), PHY_ID_FMT, 2960 "orion-mdio-mii", addr); 2961 2962 phydev = phy_connect(mp->dev, phy_id, mv643xx_eth_adjust_link, 2963 PHY_INTERFACE_MODE_GMII); 2964 if (!IS_ERR(phydev)) { 2965 phy_addr_set(mp, addr); 2966 break; 2967 } 2968 } 2969 2970 return phydev; 2971 } 2972 2973 static void phy_init(struct mv643xx_eth_private *mp, int speed, int duplex) 2974 { 2975 struct phy_device *phy = mp->phy; 2976 2977 if (speed == 0) { 2978 phy->autoneg = AUTONEG_ENABLE; 2979 phy->speed = 0; 2980 phy->duplex = 0; 2981 phy->advertising = phy->supported | ADVERTISED_Autoneg; 2982 } else { 2983 phy->autoneg = AUTONEG_DISABLE; 2984 phy->advertising = 0; 2985 phy->speed = speed; 2986 phy->duplex = duplex; 2987 } 2988 phy_start_aneg(phy); 2989 } 2990 2991 static void init_pscr(struct mv643xx_eth_private *mp, int speed, int duplex) 2992 { 2993 u32 pscr; 2994 2995 pscr = rdlp(mp, PORT_SERIAL_CONTROL); 2996 if (pscr & SERIAL_PORT_ENABLE) { 2997 pscr &= ~SERIAL_PORT_ENABLE; 2998 wrlp(mp, PORT_SERIAL_CONTROL, pscr); 2999 } 3000 3001 pscr = MAX_RX_PACKET_9700BYTE | SERIAL_PORT_CONTROL_RESERVED; 3002 if (mp->phy == NULL) { 3003 pscr |= DISABLE_AUTO_NEG_SPEED_GMII; 3004 if (speed == SPEED_1000) 3005 pscr |= SET_GMII_SPEED_TO_1000; 3006 else if (speed == SPEED_100) 3007 pscr |= SET_MII_SPEED_TO_100; 3008 3009 pscr |= DISABLE_AUTO_NEG_FOR_FLOW_CTRL; 3010 3011 pscr |= DISABLE_AUTO_NEG_FOR_DUPLEX; 3012 if (duplex == DUPLEX_FULL) 3013 pscr |= SET_FULL_DUPLEX_MODE; 3014 } 3015 3016 wrlp(mp, PORT_SERIAL_CONTROL, pscr); 3017 } 3018 3019 static const struct net_device_ops mv643xx_eth_netdev_ops = { 3020 .ndo_open = mv643xx_eth_open, 3021 .ndo_stop = mv643xx_eth_stop, 3022 .ndo_start_xmit = mv643xx_eth_xmit, 3023 .ndo_set_rx_mode = mv643xx_eth_set_rx_mode, 3024 .ndo_set_mac_address = mv643xx_eth_set_mac_address, 3025 .ndo_validate_addr = eth_validate_addr, 3026 .ndo_do_ioctl = mv643xx_eth_ioctl, 3027 .ndo_change_mtu = mv643xx_eth_change_mtu, 3028 .ndo_set_features = mv643xx_eth_set_features, 3029 .ndo_tx_timeout = mv643xx_eth_tx_timeout, 3030 .ndo_get_stats = mv643xx_eth_get_stats, 3031 #ifdef CONFIG_NET_POLL_CONTROLLER 3032 .ndo_poll_controller = mv643xx_eth_netpoll, 3033 #endif 3034 }; 3035 3036 static int mv643xx_eth_probe(struct platform_device *pdev) 3037 { 3038 struct mv643xx_eth_platform_data *pd; 3039 struct mv643xx_eth_private *mp; 3040 struct net_device *dev; 3041 struct resource *res; 3042 int err; 3043 3044 pd = dev_get_platdata(&pdev->dev); 3045 if (pd == NULL) { 3046 dev_err(&pdev->dev, "no mv643xx_eth_platform_data\n"); 3047 return -ENODEV; 3048 } 3049 3050 if (pd->shared == NULL) { 3051 dev_err(&pdev->dev, "no mv643xx_eth_platform_data->shared\n"); 3052 return -ENODEV; 3053 } 3054 3055 dev = alloc_etherdev_mq(sizeof(struct mv643xx_eth_private), 8); 3056 if (!dev) 3057 return -ENOMEM; 3058 3059 mp = netdev_priv(dev); 3060 platform_set_drvdata(pdev, mp); 3061 3062 mp->shared = platform_get_drvdata(pd->shared); 3063 mp->base = mp->shared->base + 0x0400 + (pd->port_number << 10); 3064 mp->port_num = pd->port_number; 3065 3066 mp->dev = dev; 3067 3068 /* Kirkwood resets some registers on gated clocks. Especially 3069 * CLK125_BYPASS_EN must be cleared but is not available on 3070 * all other SoCs/System Controllers using this driver. 3071 */ 3072 if (of_device_is_compatible(pdev->dev.of_node, 3073 "marvell,kirkwood-eth-port")) 3074 wrlp(mp, PORT_SERIAL_CONTROL1, 3075 rdlp(mp, PORT_SERIAL_CONTROL1) & ~CLK125_BYPASS_EN); 3076 3077 /* 3078 * Start with a default rate, and if there is a clock, allow 3079 * it to override the default. 3080 */ 3081 mp->t_clk = 133000000; 3082 mp->clk = devm_clk_get(&pdev->dev, NULL); 3083 if (!IS_ERR(mp->clk)) { 3084 clk_prepare_enable(mp->clk); 3085 mp->t_clk = clk_get_rate(mp->clk); 3086 } else if (!IS_ERR(mp->shared->clk)) { 3087 mp->t_clk = clk_get_rate(mp->shared->clk); 3088 } 3089 3090 set_params(mp, pd); 3091 netif_set_real_num_tx_queues(dev, mp->txq_count); 3092 netif_set_real_num_rx_queues(dev, mp->rxq_count); 3093 3094 err = 0; 3095 if (pd->phy_node) { 3096 mp->phy = of_phy_connect(mp->dev, pd->phy_node, 3097 mv643xx_eth_adjust_link, 0, 3098 PHY_INTERFACE_MODE_GMII); 3099 if (!mp->phy) 3100 err = -ENODEV; 3101 else 3102 phy_addr_set(mp, mp->phy->addr); 3103 } else if (pd->phy_addr != MV643XX_ETH_PHY_NONE) { 3104 mp->phy = phy_scan(mp, pd->phy_addr); 3105 3106 if (IS_ERR(mp->phy)) 3107 err = PTR_ERR(mp->phy); 3108 else 3109 phy_init(mp, pd->speed, pd->duplex); 3110 } 3111 if (err == -ENODEV) { 3112 err = -EPROBE_DEFER; 3113 goto out; 3114 } 3115 if (err) 3116 goto out; 3117 3118 dev->ethtool_ops = &mv643xx_eth_ethtool_ops; 3119 3120 init_pscr(mp, pd->speed, pd->duplex); 3121 3122 3123 mib_counters_clear(mp); 3124 3125 setup_timer(&mp->mib_counters_timer, mib_counters_timer_wrapper, 3126 (unsigned long)mp); 3127 mp->mib_counters_timer.expires = jiffies + 30 * HZ; 3128 3129 spin_lock_init(&mp->mib_counters_lock); 3130 3131 INIT_WORK(&mp->tx_timeout_task, tx_timeout_task); 3132 3133 netif_napi_add(dev, &mp->napi, mv643xx_eth_poll, NAPI_POLL_WEIGHT); 3134 3135 setup_timer(&mp->rx_oom, oom_timer_wrapper, (unsigned long)mp); 3136 3137 3138 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); 3139 BUG_ON(!res); 3140 dev->irq = res->start; 3141 3142 dev->netdev_ops = &mv643xx_eth_netdev_ops; 3143 3144 dev->watchdog_timeo = 2 * HZ; 3145 dev->base_addr = 0; 3146 3147 dev->features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO; 3148 dev->vlan_features = dev->features; 3149 3150 dev->features |= NETIF_F_RXCSUM; 3151 dev->hw_features = dev->features; 3152 3153 dev->priv_flags |= IFF_UNICAST_FLT; 3154 dev->gso_max_segs = MV643XX_MAX_TSO_SEGS; 3155 3156 SET_NETDEV_DEV(dev, &pdev->dev); 3157 3158 if (mp->shared->win_protect) 3159 wrl(mp, WINDOW_PROTECT(mp->port_num), mp->shared->win_protect); 3160 3161 netif_carrier_off(dev); 3162 3163 wrlp(mp, SDMA_CONFIG, PORT_SDMA_CONFIG_DEFAULT_VALUE); 3164 3165 set_rx_coal(mp, 250); 3166 set_tx_coal(mp, 0); 3167 3168 err = register_netdev(dev); 3169 if (err) 3170 goto out; 3171 3172 netdev_notice(dev, "port %d with MAC address %pM\n", 3173 mp->port_num, dev->dev_addr); 3174 3175 if (mp->tx_desc_sram_size > 0) 3176 netdev_notice(dev, "configured with sram\n"); 3177 3178 return 0; 3179 3180 out: 3181 if (!IS_ERR(mp->clk)) 3182 clk_disable_unprepare(mp->clk); 3183 free_netdev(dev); 3184 3185 return err; 3186 } 3187 3188 static int mv643xx_eth_remove(struct platform_device *pdev) 3189 { 3190 struct mv643xx_eth_private *mp = platform_get_drvdata(pdev); 3191 3192 unregister_netdev(mp->dev); 3193 if (mp->phy != NULL) 3194 phy_disconnect(mp->phy); 3195 cancel_work_sync(&mp->tx_timeout_task); 3196 3197 if (!IS_ERR(mp->clk)) 3198 clk_disable_unprepare(mp->clk); 3199 3200 free_netdev(mp->dev); 3201 3202 return 0; 3203 } 3204 3205 static void mv643xx_eth_shutdown(struct platform_device *pdev) 3206 { 3207 struct mv643xx_eth_private *mp = platform_get_drvdata(pdev); 3208 3209 /* Mask all interrupts on ethernet port */ 3210 wrlp(mp, INT_MASK, 0); 3211 rdlp(mp, INT_MASK); 3212 3213 if (netif_running(mp->dev)) 3214 port_reset(mp); 3215 } 3216 3217 static struct platform_driver mv643xx_eth_driver = { 3218 .probe = mv643xx_eth_probe, 3219 .remove = mv643xx_eth_remove, 3220 .shutdown = mv643xx_eth_shutdown, 3221 .driver = { 3222 .name = MV643XX_ETH_NAME, 3223 }, 3224 }; 3225 3226 static int __init mv643xx_eth_init_module(void) 3227 { 3228 int rc; 3229 3230 rc = platform_driver_register(&mv643xx_eth_shared_driver); 3231 if (!rc) { 3232 rc = platform_driver_register(&mv643xx_eth_driver); 3233 if (rc) 3234 platform_driver_unregister(&mv643xx_eth_shared_driver); 3235 } 3236 3237 return rc; 3238 } 3239 module_init(mv643xx_eth_init_module); 3240 3241 static void __exit mv643xx_eth_cleanup_module(void) 3242 { 3243 platform_driver_unregister(&mv643xx_eth_driver); 3244 platform_driver_unregister(&mv643xx_eth_shared_driver); 3245 } 3246 module_exit(mv643xx_eth_cleanup_module); 3247 3248 MODULE_AUTHOR("Rabeeh Khoury, Assaf Hoffman, Matthew Dharm, " 3249 "Manish Lachwani, Dale Farnsworth and Lennert Buytenhek"); 3250 MODULE_DESCRIPTION("Ethernet driver for Marvell MV643XX"); 3251 MODULE_LICENSE("GPL"); 3252 MODULE_ALIAS("platform:" MV643XX_ETH_SHARED_NAME); 3253 MODULE_ALIAS("platform:" MV643XX_ETH_NAME); 3254