1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3  * Driver for Marvell Discovery (MV643XX) and Marvell Orion ethernet ports
4  * Copyright (C) 2002 Matthew Dharm <mdharm@momenco.com>
5  *
6  * Based on the 64360 driver from:
7  * Copyright (C) 2002 Rabeeh Khoury <rabeeh@galileo.co.il>
8  *		      Rabeeh Khoury <rabeeh@marvell.com>
9  *
10  * Copyright (C) 2003 PMC-Sierra, Inc.,
11  *	written by Manish Lachwani
12  *
13  * Copyright (C) 2003 Ralf Baechle <ralf@linux-mips.org>
14  *
15  * Copyright (C) 2004-2006 MontaVista Software, Inc.
16  *			   Dale Farnsworth <dale@farnsworth.org>
17  *
18  * Copyright (C) 2004 Steven J. Hill <sjhill1@rockwellcollins.com>
19  *				     <sjhill@realitydiluted.com>
20  *
21  * Copyright (C) 2007-2008 Marvell Semiconductor
22  *			   Lennert Buytenhek <buytenh@marvell.com>
23  *
24  * Copyright (C) 2013 Michael Stapelberg <michael@stapelberg.de>
25  */
26 
27 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
28 
29 #include <linux/init.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/in.h>
32 #include <linux/ip.h>
33 #include <net/tso.h>
34 #include <linux/tcp.h>
35 #include <linux/udp.h>
36 #include <linux/etherdevice.h>
37 #include <linux/delay.h>
38 #include <linux/ethtool.h>
39 #include <linux/platform_device.h>
40 #include <linux/module.h>
41 #include <linux/kernel.h>
42 #include <linux/spinlock.h>
43 #include <linux/workqueue.h>
44 #include <linux/phy.h>
45 #include <linux/mv643xx_eth.h>
46 #include <linux/io.h>
47 #include <linux/interrupt.h>
48 #include <linux/types.h>
49 #include <linux/slab.h>
50 #include <linux/clk.h>
51 #include <linux/of.h>
52 #include <linux/of_irq.h>
53 #include <linux/of_net.h>
54 #include <linux/of_mdio.h>
55 
56 static char mv643xx_eth_driver_name[] = "mv643xx_eth";
57 static char mv643xx_eth_driver_version[] = "1.4";
58 
59 
60 /*
61  * Registers shared between all ports.
62  */
63 #define PHY_ADDR			0x0000
64 #define WINDOW_BASE(w)			(0x0200 + ((w) << 3))
65 #define WINDOW_SIZE(w)			(0x0204 + ((w) << 3))
66 #define WINDOW_REMAP_HIGH(w)		(0x0280 + ((w) << 2))
67 #define WINDOW_BAR_ENABLE		0x0290
68 #define WINDOW_PROTECT(w)		(0x0294 + ((w) << 4))
69 
70 /*
71  * Main per-port registers.  These live at offset 0x0400 for
72  * port #0, 0x0800 for port #1, and 0x0c00 for port #2.
73  */
74 #define PORT_CONFIG			0x0000
75 #define  UNICAST_PROMISCUOUS_MODE	0x00000001
76 #define PORT_CONFIG_EXT			0x0004
77 #define MAC_ADDR_LOW			0x0014
78 #define MAC_ADDR_HIGH			0x0018
79 #define SDMA_CONFIG			0x001c
80 #define  TX_BURST_SIZE_16_64BIT		0x01000000
81 #define  TX_BURST_SIZE_4_64BIT		0x00800000
82 #define  BLM_TX_NO_SWAP			0x00000020
83 #define  BLM_RX_NO_SWAP			0x00000010
84 #define  RX_BURST_SIZE_16_64BIT		0x00000008
85 #define  RX_BURST_SIZE_4_64BIT		0x00000004
86 #define PORT_SERIAL_CONTROL		0x003c
87 #define  SET_MII_SPEED_TO_100		0x01000000
88 #define  SET_GMII_SPEED_TO_1000		0x00800000
89 #define  SET_FULL_DUPLEX_MODE		0x00200000
90 #define  MAX_RX_PACKET_9700BYTE		0x000a0000
91 #define  DISABLE_AUTO_NEG_SPEED_GMII	0x00002000
92 #define  DO_NOT_FORCE_LINK_FAIL		0x00000400
93 #define  SERIAL_PORT_CONTROL_RESERVED	0x00000200
94 #define  DISABLE_AUTO_NEG_FOR_FLOW_CTRL	0x00000008
95 #define  DISABLE_AUTO_NEG_FOR_DUPLEX	0x00000004
96 #define  FORCE_LINK_PASS		0x00000002
97 #define  SERIAL_PORT_ENABLE		0x00000001
98 #define PORT_STATUS			0x0044
99 #define  TX_FIFO_EMPTY			0x00000400
100 #define  TX_IN_PROGRESS			0x00000080
101 #define  PORT_SPEED_MASK		0x00000030
102 #define  PORT_SPEED_1000		0x00000010
103 #define  PORT_SPEED_100			0x00000020
104 #define  PORT_SPEED_10			0x00000000
105 #define  FLOW_CONTROL_ENABLED		0x00000008
106 #define  FULL_DUPLEX			0x00000004
107 #define  LINK_UP			0x00000002
108 #define TXQ_COMMAND			0x0048
109 #define TXQ_FIX_PRIO_CONF		0x004c
110 #define PORT_SERIAL_CONTROL1		0x004c
111 #define  CLK125_BYPASS_EN		0x00000010
112 #define TX_BW_RATE			0x0050
113 #define TX_BW_MTU			0x0058
114 #define TX_BW_BURST			0x005c
115 #define INT_CAUSE			0x0060
116 #define  INT_TX_END			0x07f80000
117 #define  INT_TX_END_0			0x00080000
118 #define  INT_RX				0x000003fc
119 #define  INT_RX_0			0x00000004
120 #define  INT_EXT			0x00000002
121 #define INT_CAUSE_EXT			0x0064
122 #define  INT_EXT_LINK_PHY		0x00110000
123 #define  INT_EXT_TX			0x000000ff
124 #define INT_MASK			0x0068
125 #define INT_MASK_EXT			0x006c
126 #define TX_FIFO_URGENT_THRESHOLD	0x0074
127 #define RX_DISCARD_FRAME_CNT		0x0084
128 #define RX_OVERRUN_FRAME_CNT		0x0088
129 #define TXQ_FIX_PRIO_CONF_MOVED		0x00dc
130 #define TX_BW_RATE_MOVED		0x00e0
131 #define TX_BW_MTU_MOVED			0x00e8
132 #define TX_BW_BURST_MOVED		0x00ec
133 #define RXQ_CURRENT_DESC_PTR(q)		(0x020c + ((q) << 4))
134 #define RXQ_COMMAND			0x0280
135 #define TXQ_CURRENT_DESC_PTR(q)		(0x02c0 + ((q) << 2))
136 #define TXQ_BW_TOKENS(q)		(0x0300 + ((q) << 4))
137 #define TXQ_BW_CONF(q)			(0x0304 + ((q) << 4))
138 #define TXQ_BW_WRR_CONF(q)		(0x0308 + ((q) << 4))
139 
140 /*
141  * Misc per-port registers.
142  */
143 #define MIB_COUNTERS(p)			(0x1000 + ((p) << 7))
144 #define SPECIAL_MCAST_TABLE(p)		(0x1400 + ((p) << 10))
145 #define OTHER_MCAST_TABLE(p)		(0x1500 + ((p) << 10))
146 #define UNICAST_TABLE(p)		(0x1600 + ((p) << 10))
147 
148 
149 /*
150  * SDMA configuration register default value.
151  */
152 #if defined(__BIG_ENDIAN)
153 #define PORT_SDMA_CONFIG_DEFAULT_VALUE		\
154 		(RX_BURST_SIZE_4_64BIT	|	\
155 		 TX_BURST_SIZE_4_64BIT)
156 #elif defined(__LITTLE_ENDIAN)
157 #define PORT_SDMA_CONFIG_DEFAULT_VALUE		\
158 		(RX_BURST_SIZE_4_64BIT	|	\
159 		 BLM_RX_NO_SWAP		|	\
160 		 BLM_TX_NO_SWAP		|	\
161 		 TX_BURST_SIZE_4_64BIT)
162 #else
163 #error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
164 #endif
165 
166 
167 /*
168  * Misc definitions.
169  */
170 #define DEFAULT_RX_QUEUE_SIZE	128
171 #define DEFAULT_TX_QUEUE_SIZE	512
172 #define SKB_DMA_REALIGN		((PAGE_SIZE - NET_SKB_PAD) % SMP_CACHE_BYTES)
173 
174 /* Max number of allowed TCP segments for software TSO */
175 #define MV643XX_MAX_TSO_SEGS 100
176 #define MV643XX_MAX_SKB_DESCS (MV643XX_MAX_TSO_SEGS * 2 + MAX_SKB_FRAGS)
177 
178 #define IS_TSO_HEADER(txq, addr) \
179 	((addr >= txq->tso_hdrs_dma) && \
180 	 (addr < txq->tso_hdrs_dma + txq->tx_ring_size * TSO_HEADER_SIZE))
181 
182 #define DESC_DMA_MAP_SINGLE 0
183 #define DESC_DMA_MAP_PAGE 1
184 
185 /*
186  * RX/TX descriptors.
187  */
188 #if defined(__BIG_ENDIAN)
189 struct rx_desc {
190 	u16 byte_cnt;		/* Descriptor buffer byte count		*/
191 	u16 buf_size;		/* Buffer size				*/
192 	u32 cmd_sts;		/* Descriptor command status		*/
193 	u32 next_desc_ptr;	/* Next descriptor pointer		*/
194 	u32 buf_ptr;		/* Descriptor buffer pointer		*/
195 };
196 
197 struct tx_desc {
198 	u16 byte_cnt;		/* buffer byte count			*/
199 	u16 l4i_chk;		/* CPU provided TCP checksum		*/
200 	u32 cmd_sts;		/* Command/status field			*/
201 	u32 next_desc_ptr;	/* Pointer to next descriptor		*/
202 	u32 buf_ptr;		/* pointer to buffer for this descriptor*/
203 };
204 #elif defined(__LITTLE_ENDIAN)
205 struct rx_desc {
206 	u32 cmd_sts;		/* Descriptor command status		*/
207 	u16 buf_size;		/* Buffer size				*/
208 	u16 byte_cnt;		/* Descriptor buffer byte count		*/
209 	u32 buf_ptr;		/* Descriptor buffer pointer		*/
210 	u32 next_desc_ptr;	/* Next descriptor pointer		*/
211 };
212 
213 struct tx_desc {
214 	u32 cmd_sts;		/* Command/status field			*/
215 	u16 l4i_chk;		/* CPU provided TCP checksum		*/
216 	u16 byte_cnt;		/* buffer byte count			*/
217 	u32 buf_ptr;		/* pointer to buffer for this descriptor*/
218 	u32 next_desc_ptr;	/* Pointer to next descriptor		*/
219 };
220 #else
221 #error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
222 #endif
223 
224 /* RX & TX descriptor command */
225 #define BUFFER_OWNED_BY_DMA		0x80000000
226 
227 /* RX & TX descriptor status */
228 #define ERROR_SUMMARY			0x00000001
229 
230 /* RX descriptor status */
231 #define LAYER_4_CHECKSUM_OK		0x40000000
232 #define RX_ENABLE_INTERRUPT		0x20000000
233 #define RX_FIRST_DESC			0x08000000
234 #define RX_LAST_DESC			0x04000000
235 #define RX_IP_HDR_OK			0x02000000
236 #define RX_PKT_IS_IPV4			0x01000000
237 #define RX_PKT_IS_ETHERNETV2		0x00800000
238 #define RX_PKT_LAYER4_TYPE_MASK		0x00600000
239 #define RX_PKT_LAYER4_TYPE_TCP_IPV4	0x00000000
240 #define RX_PKT_IS_VLAN_TAGGED		0x00080000
241 
242 /* TX descriptor command */
243 #define TX_ENABLE_INTERRUPT		0x00800000
244 #define GEN_CRC				0x00400000
245 #define TX_FIRST_DESC			0x00200000
246 #define TX_LAST_DESC			0x00100000
247 #define ZERO_PADDING			0x00080000
248 #define GEN_IP_V4_CHECKSUM		0x00040000
249 #define GEN_TCP_UDP_CHECKSUM		0x00020000
250 #define UDP_FRAME			0x00010000
251 #define MAC_HDR_EXTRA_4_BYTES		0x00008000
252 #define GEN_TCP_UDP_CHK_FULL		0x00000400
253 #define MAC_HDR_EXTRA_8_BYTES		0x00000200
254 
255 #define TX_IHL_SHIFT			11
256 
257 
258 /* global *******************************************************************/
259 struct mv643xx_eth_shared_private {
260 	/*
261 	 * Ethernet controller base address.
262 	 */
263 	void __iomem *base;
264 
265 	/*
266 	 * Per-port MBUS window access register value.
267 	 */
268 	u32 win_protect;
269 
270 	/*
271 	 * Hardware-specific parameters.
272 	 */
273 	int extended_rx_coal_limit;
274 	int tx_bw_control;
275 	int tx_csum_limit;
276 	struct clk *clk;
277 };
278 
279 #define TX_BW_CONTROL_ABSENT		0
280 #define TX_BW_CONTROL_OLD_LAYOUT	1
281 #define TX_BW_CONTROL_NEW_LAYOUT	2
282 
283 static int mv643xx_eth_open(struct net_device *dev);
284 static int mv643xx_eth_stop(struct net_device *dev);
285 
286 
287 /* per-port *****************************************************************/
288 struct mib_counters {
289 	u64 good_octets_received;
290 	u32 bad_octets_received;
291 	u32 internal_mac_transmit_err;
292 	u32 good_frames_received;
293 	u32 bad_frames_received;
294 	u32 broadcast_frames_received;
295 	u32 multicast_frames_received;
296 	u32 frames_64_octets;
297 	u32 frames_65_to_127_octets;
298 	u32 frames_128_to_255_octets;
299 	u32 frames_256_to_511_octets;
300 	u32 frames_512_to_1023_octets;
301 	u32 frames_1024_to_max_octets;
302 	u64 good_octets_sent;
303 	u32 good_frames_sent;
304 	u32 excessive_collision;
305 	u32 multicast_frames_sent;
306 	u32 broadcast_frames_sent;
307 	u32 unrec_mac_control_received;
308 	u32 fc_sent;
309 	u32 good_fc_received;
310 	u32 bad_fc_received;
311 	u32 undersize_received;
312 	u32 fragments_received;
313 	u32 oversize_received;
314 	u32 jabber_received;
315 	u32 mac_receive_error;
316 	u32 bad_crc_event;
317 	u32 collision;
318 	u32 late_collision;
319 	/* Non MIB hardware counters */
320 	u32 rx_discard;
321 	u32 rx_overrun;
322 };
323 
324 struct rx_queue {
325 	int index;
326 
327 	int rx_ring_size;
328 
329 	int rx_desc_count;
330 	int rx_curr_desc;
331 	int rx_used_desc;
332 
333 	struct rx_desc *rx_desc_area;
334 	dma_addr_t rx_desc_dma;
335 	int rx_desc_area_size;
336 	struct sk_buff **rx_skb;
337 };
338 
339 struct tx_queue {
340 	int index;
341 
342 	int tx_ring_size;
343 
344 	int tx_desc_count;
345 	int tx_curr_desc;
346 	int tx_used_desc;
347 
348 	int tx_stop_threshold;
349 	int tx_wake_threshold;
350 
351 	char *tso_hdrs;
352 	dma_addr_t tso_hdrs_dma;
353 
354 	struct tx_desc *tx_desc_area;
355 	char *tx_desc_mapping; /* array to track the type of the dma mapping */
356 	dma_addr_t tx_desc_dma;
357 	int tx_desc_area_size;
358 
359 	struct sk_buff_head tx_skb;
360 
361 	unsigned long tx_packets;
362 	unsigned long tx_bytes;
363 	unsigned long tx_dropped;
364 };
365 
366 struct mv643xx_eth_private {
367 	struct mv643xx_eth_shared_private *shared;
368 	void __iomem *base;
369 	int port_num;
370 
371 	struct net_device *dev;
372 
373 	struct timer_list mib_counters_timer;
374 	spinlock_t mib_counters_lock;
375 	struct mib_counters mib_counters;
376 
377 	struct work_struct tx_timeout_task;
378 
379 	struct napi_struct napi;
380 	u32 int_mask;
381 	u8 oom;
382 	u8 work_link;
383 	u8 work_tx;
384 	u8 work_tx_end;
385 	u8 work_rx;
386 	u8 work_rx_refill;
387 
388 	int skb_size;
389 
390 	/*
391 	 * RX state.
392 	 */
393 	int rx_ring_size;
394 	unsigned long rx_desc_sram_addr;
395 	int rx_desc_sram_size;
396 	int rxq_count;
397 	struct timer_list rx_oom;
398 	struct rx_queue rxq[8];
399 
400 	/*
401 	 * TX state.
402 	 */
403 	int tx_ring_size;
404 	unsigned long tx_desc_sram_addr;
405 	int tx_desc_sram_size;
406 	int txq_count;
407 	struct tx_queue txq[8];
408 
409 	/*
410 	 * Hardware-specific parameters.
411 	 */
412 	struct clk *clk;
413 	unsigned int t_clk;
414 };
415 
416 
417 /* port register accessors **************************************************/
418 static inline u32 rdl(struct mv643xx_eth_private *mp, int offset)
419 {
420 	return readl(mp->shared->base + offset);
421 }
422 
423 static inline u32 rdlp(struct mv643xx_eth_private *mp, int offset)
424 {
425 	return readl(mp->base + offset);
426 }
427 
428 static inline void wrl(struct mv643xx_eth_private *mp, int offset, u32 data)
429 {
430 	writel(data, mp->shared->base + offset);
431 }
432 
433 static inline void wrlp(struct mv643xx_eth_private *mp, int offset, u32 data)
434 {
435 	writel(data, mp->base + offset);
436 }
437 
438 
439 /* rxq/txq helper functions *************************************************/
440 static struct mv643xx_eth_private *rxq_to_mp(struct rx_queue *rxq)
441 {
442 	return container_of(rxq, struct mv643xx_eth_private, rxq[rxq->index]);
443 }
444 
445 static struct mv643xx_eth_private *txq_to_mp(struct tx_queue *txq)
446 {
447 	return container_of(txq, struct mv643xx_eth_private, txq[txq->index]);
448 }
449 
450 static void rxq_enable(struct rx_queue *rxq)
451 {
452 	struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
453 	wrlp(mp, RXQ_COMMAND, 1 << rxq->index);
454 }
455 
456 static void rxq_disable(struct rx_queue *rxq)
457 {
458 	struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
459 	u8 mask = 1 << rxq->index;
460 
461 	wrlp(mp, RXQ_COMMAND, mask << 8);
462 	while (rdlp(mp, RXQ_COMMAND) & mask)
463 		udelay(10);
464 }
465 
466 static void txq_reset_hw_ptr(struct tx_queue *txq)
467 {
468 	struct mv643xx_eth_private *mp = txq_to_mp(txq);
469 	u32 addr;
470 
471 	addr = (u32)txq->tx_desc_dma;
472 	addr += txq->tx_curr_desc * sizeof(struct tx_desc);
473 	wrlp(mp, TXQ_CURRENT_DESC_PTR(txq->index), addr);
474 }
475 
476 static void txq_enable(struct tx_queue *txq)
477 {
478 	struct mv643xx_eth_private *mp = txq_to_mp(txq);
479 	wrlp(mp, TXQ_COMMAND, 1 << txq->index);
480 }
481 
482 static void txq_disable(struct tx_queue *txq)
483 {
484 	struct mv643xx_eth_private *mp = txq_to_mp(txq);
485 	u8 mask = 1 << txq->index;
486 
487 	wrlp(mp, TXQ_COMMAND, mask << 8);
488 	while (rdlp(mp, TXQ_COMMAND) & mask)
489 		udelay(10);
490 }
491 
492 static void txq_maybe_wake(struct tx_queue *txq)
493 {
494 	struct mv643xx_eth_private *mp = txq_to_mp(txq);
495 	struct netdev_queue *nq = netdev_get_tx_queue(mp->dev, txq->index);
496 
497 	if (netif_tx_queue_stopped(nq)) {
498 		__netif_tx_lock(nq, smp_processor_id());
499 		if (txq->tx_desc_count <= txq->tx_wake_threshold)
500 			netif_tx_wake_queue(nq);
501 		__netif_tx_unlock(nq);
502 	}
503 }
504 
505 static int rxq_process(struct rx_queue *rxq, int budget)
506 {
507 	struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
508 	struct net_device_stats *stats = &mp->dev->stats;
509 	int rx;
510 
511 	rx = 0;
512 	while (rx < budget && rxq->rx_desc_count) {
513 		struct rx_desc *rx_desc;
514 		unsigned int cmd_sts;
515 		struct sk_buff *skb;
516 		u16 byte_cnt;
517 
518 		rx_desc = &rxq->rx_desc_area[rxq->rx_curr_desc];
519 
520 		cmd_sts = rx_desc->cmd_sts;
521 		if (cmd_sts & BUFFER_OWNED_BY_DMA)
522 			break;
523 		rmb();
524 
525 		skb = rxq->rx_skb[rxq->rx_curr_desc];
526 		rxq->rx_skb[rxq->rx_curr_desc] = NULL;
527 
528 		rxq->rx_curr_desc++;
529 		if (rxq->rx_curr_desc == rxq->rx_ring_size)
530 			rxq->rx_curr_desc = 0;
531 
532 		dma_unmap_single(mp->dev->dev.parent, rx_desc->buf_ptr,
533 				 rx_desc->buf_size, DMA_FROM_DEVICE);
534 		rxq->rx_desc_count--;
535 		rx++;
536 
537 		mp->work_rx_refill |= 1 << rxq->index;
538 
539 		byte_cnt = rx_desc->byte_cnt;
540 
541 		/*
542 		 * Update statistics.
543 		 *
544 		 * Note that the descriptor byte count includes 2 dummy
545 		 * bytes automatically inserted by the hardware at the
546 		 * start of the packet (which we don't count), and a 4
547 		 * byte CRC at the end of the packet (which we do count).
548 		 */
549 		stats->rx_packets++;
550 		stats->rx_bytes += byte_cnt - 2;
551 
552 		/*
553 		 * In case we received a packet without first / last bits
554 		 * on, or the error summary bit is set, the packet needs
555 		 * to be dropped.
556 		 */
557 		if ((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC | ERROR_SUMMARY))
558 			!= (RX_FIRST_DESC | RX_LAST_DESC))
559 			goto err;
560 
561 		/*
562 		 * The -4 is for the CRC in the trailer of the
563 		 * received packet
564 		 */
565 		skb_put(skb, byte_cnt - 2 - 4);
566 
567 		if (cmd_sts & LAYER_4_CHECKSUM_OK)
568 			skb->ip_summed = CHECKSUM_UNNECESSARY;
569 		skb->protocol = eth_type_trans(skb, mp->dev);
570 
571 		napi_gro_receive(&mp->napi, skb);
572 
573 		continue;
574 
575 err:
576 		stats->rx_dropped++;
577 
578 		if ((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC)) !=
579 			(RX_FIRST_DESC | RX_LAST_DESC)) {
580 			if (net_ratelimit())
581 				netdev_err(mp->dev,
582 					   "received packet spanning multiple descriptors\n");
583 		}
584 
585 		if (cmd_sts & ERROR_SUMMARY)
586 			stats->rx_errors++;
587 
588 		dev_kfree_skb(skb);
589 	}
590 
591 	if (rx < budget)
592 		mp->work_rx &= ~(1 << rxq->index);
593 
594 	return rx;
595 }
596 
597 static int rxq_refill(struct rx_queue *rxq, int budget)
598 {
599 	struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
600 	int refilled;
601 
602 	refilled = 0;
603 	while (refilled < budget && rxq->rx_desc_count < rxq->rx_ring_size) {
604 		struct sk_buff *skb;
605 		int rx;
606 		struct rx_desc *rx_desc;
607 		int size;
608 
609 		skb = netdev_alloc_skb(mp->dev, mp->skb_size);
610 
611 		if (skb == NULL) {
612 			mp->oom = 1;
613 			goto oom;
614 		}
615 
616 		if (SKB_DMA_REALIGN)
617 			skb_reserve(skb, SKB_DMA_REALIGN);
618 
619 		refilled++;
620 		rxq->rx_desc_count++;
621 
622 		rx = rxq->rx_used_desc++;
623 		if (rxq->rx_used_desc == rxq->rx_ring_size)
624 			rxq->rx_used_desc = 0;
625 
626 		rx_desc = rxq->rx_desc_area + rx;
627 
628 		size = skb_end_pointer(skb) - skb->data;
629 		rx_desc->buf_ptr = dma_map_single(mp->dev->dev.parent,
630 						  skb->data, size,
631 						  DMA_FROM_DEVICE);
632 		rx_desc->buf_size = size;
633 		rxq->rx_skb[rx] = skb;
634 		wmb();
635 		rx_desc->cmd_sts = BUFFER_OWNED_BY_DMA | RX_ENABLE_INTERRUPT;
636 		wmb();
637 
638 		/*
639 		 * The hardware automatically prepends 2 bytes of
640 		 * dummy data to each received packet, so that the
641 		 * IP header ends up 16-byte aligned.
642 		 */
643 		skb_reserve(skb, 2);
644 	}
645 
646 	if (refilled < budget)
647 		mp->work_rx_refill &= ~(1 << rxq->index);
648 
649 oom:
650 	return refilled;
651 }
652 
653 
654 /* tx ***********************************************************************/
655 static inline unsigned int has_tiny_unaligned_frags(struct sk_buff *skb)
656 {
657 	int frag;
658 
659 	for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
660 		const skb_frag_t *fragp = &skb_shinfo(skb)->frags[frag];
661 
662 		if (skb_frag_size(fragp) <= 8 && skb_frag_off(fragp) & 7)
663 			return 1;
664 	}
665 
666 	return 0;
667 }
668 
669 static inline __be16 sum16_as_be(__sum16 sum)
670 {
671 	return (__force __be16)sum;
672 }
673 
674 static int skb_tx_csum(struct mv643xx_eth_private *mp, struct sk_buff *skb,
675 		       u16 *l4i_chk, u32 *command, int length)
676 {
677 	int ret;
678 	u32 cmd = 0;
679 
680 	if (skb->ip_summed == CHECKSUM_PARTIAL) {
681 		int hdr_len;
682 		int tag_bytes;
683 
684 		BUG_ON(skb->protocol != htons(ETH_P_IP) &&
685 		       skb->protocol != htons(ETH_P_8021Q));
686 
687 		hdr_len = (void *)ip_hdr(skb) - (void *)skb->data;
688 		tag_bytes = hdr_len - ETH_HLEN;
689 
690 		if (length - hdr_len > mp->shared->tx_csum_limit ||
691 		    unlikely(tag_bytes & ~12)) {
692 			ret = skb_checksum_help(skb);
693 			if (!ret)
694 				goto no_csum;
695 			return ret;
696 		}
697 
698 		if (tag_bytes & 4)
699 			cmd |= MAC_HDR_EXTRA_4_BYTES;
700 		if (tag_bytes & 8)
701 			cmd |= MAC_HDR_EXTRA_8_BYTES;
702 
703 		cmd |= GEN_TCP_UDP_CHECKSUM | GEN_TCP_UDP_CHK_FULL |
704 			   GEN_IP_V4_CHECKSUM   |
705 			   ip_hdr(skb)->ihl << TX_IHL_SHIFT;
706 
707 		/* TODO: Revisit this. With the usage of GEN_TCP_UDP_CHK_FULL
708 		 * it seems we don't need to pass the initial checksum. */
709 		switch (ip_hdr(skb)->protocol) {
710 		case IPPROTO_UDP:
711 			cmd |= UDP_FRAME;
712 			*l4i_chk = 0;
713 			break;
714 		case IPPROTO_TCP:
715 			*l4i_chk = 0;
716 			break;
717 		default:
718 			WARN(1, "protocol not supported");
719 		}
720 	} else {
721 no_csum:
722 		/* Errata BTS #50, IHL must be 5 if no HW checksum */
723 		cmd |= 5 << TX_IHL_SHIFT;
724 	}
725 	*command = cmd;
726 	return 0;
727 }
728 
729 static inline int
730 txq_put_data_tso(struct net_device *dev, struct tx_queue *txq,
731 		 struct sk_buff *skb, char *data, int length,
732 		 bool last_tcp, bool is_last)
733 {
734 	int tx_index;
735 	u32 cmd_sts;
736 	struct tx_desc *desc;
737 
738 	tx_index = txq->tx_curr_desc++;
739 	if (txq->tx_curr_desc == txq->tx_ring_size)
740 		txq->tx_curr_desc = 0;
741 	desc = &txq->tx_desc_area[tx_index];
742 	txq->tx_desc_mapping[tx_index] = DESC_DMA_MAP_SINGLE;
743 
744 	desc->l4i_chk = 0;
745 	desc->byte_cnt = length;
746 
747 	if (length <= 8 && (uintptr_t)data & 0x7) {
748 		/* Copy unaligned small data fragment to TSO header data area */
749 		memcpy(txq->tso_hdrs + tx_index * TSO_HEADER_SIZE,
750 		       data, length);
751 		desc->buf_ptr = txq->tso_hdrs_dma
752 			+ tx_index * TSO_HEADER_SIZE;
753 	} else {
754 		/* Alignment is okay, map buffer and hand off to hardware */
755 		txq->tx_desc_mapping[tx_index] = DESC_DMA_MAP_SINGLE;
756 		desc->buf_ptr = dma_map_single(dev->dev.parent, data,
757 			length, DMA_TO_DEVICE);
758 		if (unlikely(dma_mapping_error(dev->dev.parent,
759 					       desc->buf_ptr))) {
760 			WARN(1, "dma_map_single failed!\n");
761 			return -ENOMEM;
762 		}
763 	}
764 
765 	cmd_sts = BUFFER_OWNED_BY_DMA;
766 	if (last_tcp) {
767 		/* last descriptor in the TCP packet */
768 		cmd_sts |= ZERO_PADDING | TX_LAST_DESC;
769 		/* last descriptor in SKB */
770 		if (is_last)
771 			cmd_sts |= TX_ENABLE_INTERRUPT;
772 	}
773 	desc->cmd_sts = cmd_sts;
774 	return 0;
775 }
776 
777 static inline void
778 txq_put_hdr_tso(struct sk_buff *skb, struct tx_queue *txq, int length,
779 		u32 *first_cmd_sts, bool first_desc)
780 {
781 	struct mv643xx_eth_private *mp = txq_to_mp(txq);
782 	int hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
783 	int tx_index;
784 	struct tx_desc *desc;
785 	int ret;
786 	u32 cmd_csum = 0;
787 	u16 l4i_chk = 0;
788 	u32 cmd_sts;
789 
790 	tx_index = txq->tx_curr_desc;
791 	desc = &txq->tx_desc_area[tx_index];
792 
793 	ret = skb_tx_csum(mp, skb, &l4i_chk, &cmd_csum, length);
794 	if (ret)
795 		WARN(1, "failed to prepare checksum!");
796 
797 	/* Should we set this? Can't use the value from skb_tx_csum()
798 	 * as it's not the correct initial L4 checksum to use. */
799 	desc->l4i_chk = 0;
800 
801 	desc->byte_cnt = hdr_len;
802 	desc->buf_ptr = txq->tso_hdrs_dma +
803 			txq->tx_curr_desc * TSO_HEADER_SIZE;
804 	cmd_sts = cmd_csum | BUFFER_OWNED_BY_DMA  | TX_FIRST_DESC |
805 				   GEN_CRC;
806 
807 	/* Defer updating the first command descriptor until all
808 	 * following descriptors have been written.
809 	 */
810 	if (first_desc)
811 		*first_cmd_sts = cmd_sts;
812 	else
813 		desc->cmd_sts = cmd_sts;
814 
815 	txq->tx_curr_desc++;
816 	if (txq->tx_curr_desc == txq->tx_ring_size)
817 		txq->tx_curr_desc = 0;
818 }
819 
820 static int txq_submit_tso(struct tx_queue *txq, struct sk_buff *skb,
821 			  struct net_device *dev)
822 {
823 	struct mv643xx_eth_private *mp = txq_to_mp(txq);
824 	int total_len, data_left, ret;
825 	int desc_count = 0;
826 	struct tso_t tso;
827 	int hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
828 	struct tx_desc *first_tx_desc;
829 	u32 first_cmd_sts = 0;
830 
831 	/* Count needed descriptors */
832 	if ((txq->tx_desc_count + tso_count_descs(skb)) >= txq->tx_ring_size) {
833 		netdev_dbg(dev, "not enough descriptors for TSO!\n");
834 		return -EBUSY;
835 	}
836 
837 	first_tx_desc = &txq->tx_desc_area[txq->tx_curr_desc];
838 
839 	/* Initialize the TSO handler, and prepare the first payload */
840 	tso_start(skb, &tso);
841 
842 	total_len = skb->len - hdr_len;
843 	while (total_len > 0) {
844 		bool first_desc = (desc_count == 0);
845 		char *hdr;
846 
847 		data_left = min_t(int, skb_shinfo(skb)->gso_size, total_len);
848 		total_len -= data_left;
849 		desc_count++;
850 
851 		/* prepare packet headers: MAC + IP + TCP */
852 		hdr = txq->tso_hdrs + txq->tx_curr_desc * TSO_HEADER_SIZE;
853 		tso_build_hdr(skb, hdr, &tso, data_left, total_len == 0);
854 		txq_put_hdr_tso(skb, txq, data_left, &first_cmd_sts,
855 				first_desc);
856 
857 		while (data_left > 0) {
858 			int size;
859 			desc_count++;
860 
861 			size = min_t(int, tso.size, data_left);
862 			ret = txq_put_data_tso(dev, txq, skb, tso.data, size,
863 					       size == data_left,
864 					       total_len == 0);
865 			if (ret)
866 				goto err_release;
867 			data_left -= size;
868 			tso_build_data(skb, &tso, size);
869 		}
870 	}
871 
872 	__skb_queue_tail(&txq->tx_skb, skb);
873 	skb_tx_timestamp(skb);
874 
875 	/* ensure all other descriptors are written before first cmd_sts */
876 	wmb();
877 	first_tx_desc->cmd_sts = first_cmd_sts;
878 
879 	/* clear TX_END status */
880 	mp->work_tx_end &= ~(1 << txq->index);
881 
882 	/* ensure all descriptors are written before poking hardware */
883 	wmb();
884 	txq_enable(txq);
885 	txq->tx_desc_count += desc_count;
886 	return 0;
887 err_release:
888 	/* TODO: Release all used data descriptors; header descriptors must not
889 	 * be DMA-unmapped.
890 	 */
891 	return ret;
892 }
893 
894 static void txq_submit_frag_skb(struct tx_queue *txq, struct sk_buff *skb)
895 {
896 	struct mv643xx_eth_private *mp = txq_to_mp(txq);
897 	int nr_frags = skb_shinfo(skb)->nr_frags;
898 	int frag;
899 
900 	for (frag = 0; frag < nr_frags; frag++) {
901 		skb_frag_t *this_frag;
902 		int tx_index;
903 		struct tx_desc *desc;
904 
905 		this_frag = &skb_shinfo(skb)->frags[frag];
906 		tx_index = txq->tx_curr_desc++;
907 		if (txq->tx_curr_desc == txq->tx_ring_size)
908 			txq->tx_curr_desc = 0;
909 		desc = &txq->tx_desc_area[tx_index];
910 		txq->tx_desc_mapping[tx_index] = DESC_DMA_MAP_PAGE;
911 
912 		/*
913 		 * The last fragment will generate an interrupt
914 		 * which will free the skb on TX completion.
915 		 */
916 		if (frag == nr_frags - 1) {
917 			desc->cmd_sts = BUFFER_OWNED_BY_DMA |
918 					ZERO_PADDING | TX_LAST_DESC |
919 					TX_ENABLE_INTERRUPT;
920 		} else {
921 			desc->cmd_sts = BUFFER_OWNED_BY_DMA;
922 		}
923 
924 		desc->l4i_chk = 0;
925 		desc->byte_cnt = skb_frag_size(this_frag);
926 		desc->buf_ptr = skb_frag_dma_map(mp->dev->dev.parent,
927 						 this_frag, 0, desc->byte_cnt,
928 						 DMA_TO_DEVICE);
929 	}
930 }
931 
932 static int txq_submit_skb(struct tx_queue *txq, struct sk_buff *skb,
933 			  struct net_device *dev)
934 {
935 	struct mv643xx_eth_private *mp = txq_to_mp(txq);
936 	int nr_frags = skb_shinfo(skb)->nr_frags;
937 	int tx_index;
938 	struct tx_desc *desc;
939 	u32 cmd_sts;
940 	u16 l4i_chk;
941 	int length, ret;
942 
943 	cmd_sts = 0;
944 	l4i_chk = 0;
945 
946 	if (txq->tx_ring_size - txq->tx_desc_count < MAX_SKB_FRAGS + 1) {
947 		if (net_ratelimit())
948 			netdev_err(dev, "tx queue full?!\n");
949 		return -EBUSY;
950 	}
951 
952 	ret = skb_tx_csum(mp, skb, &l4i_chk, &cmd_sts, skb->len);
953 	if (ret)
954 		return ret;
955 	cmd_sts |= TX_FIRST_DESC | GEN_CRC | BUFFER_OWNED_BY_DMA;
956 
957 	tx_index = txq->tx_curr_desc++;
958 	if (txq->tx_curr_desc == txq->tx_ring_size)
959 		txq->tx_curr_desc = 0;
960 	desc = &txq->tx_desc_area[tx_index];
961 	txq->tx_desc_mapping[tx_index] = DESC_DMA_MAP_SINGLE;
962 
963 	if (nr_frags) {
964 		txq_submit_frag_skb(txq, skb);
965 		length = skb_headlen(skb);
966 	} else {
967 		cmd_sts |= ZERO_PADDING | TX_LAST_DESC | TX_ENABLE_INTERRUPT;
968 		length = skb->len;
969 	}
970 
971 	desc->l4i_chk = l4i_chk;
972 	desc->byte_cnt = length;
973 	desc->buf_ptr = dma_map_single(mp->dev->dev.parent, skb->data,
974 				       length, DMA_TO_DEVICE);
975 
976 	__skb_queue_tail(&txq->tx_skb, skb);
977 
978 	skb_tx_timestamp(skb);
979 
980 	/* ensure all other descriptors are written before first cmd_sts */
981 	wmb();
982 	desc->cmd_sts = cmd_sts;
983 
984 	/* clear TX_END status */
985 	mp->work_tx_end &= ~(1 << txq->index);
986 
987 	/* ensure all descriptors are written before poking hardware */
988 	wmb();
989 	txq_enable(txq);
990 
991 	txq->tx_desc_count += nr_frags + 1;
992 
993 	return 0;
994 }
995 
996 static netdev_tx_t mv643xx_eth_xmit(struct sk_buff *skb, struct net_device *dev)
997 {
998 	struct mv643xx_eth_private *mp = netdev_priv(dev);
999 	int length, queue, ret;
1000 	struct tx_queue *txq;
1001 	struct netdev_queue *nq;
1002 
1003 	queue = skb_get_queue_mapping(skb);
1004 	txq = mp->txq + queue;
1005 	nq = netdev_get_tx_queue(dev, queue);
1006 
1007 	if (has_tiny_unaligned_frags(skb) && __skb_linearize(skb)) {
1008 		netdev_printk(KERN_DEBUG, dev,
1009 			      "failed to linearize skb with tiny unaligned fragment\n");
1010 		return NETDEV_TX_BUSY;
1011 	}
1012 
1013 	length = skb->len;
1014 
1015 	if (skb_is_gso(skb))
1016 		ret = txq_submit_tso(txq, skb, dev);
1017 	else
1018 		ret = txq_submit_skb(txq, skb, dev);
1019 	if (!ret) {
1020 		txq->tx_bytes += length;
1021 		txq->tx_packets++;
1022 
1023 		if (txq->tx_desc_count >= txq->tx_stop_threshold)
1024 			netif_tx_stop_queue(nq);
1025 	} else {
1026 		txq->tx_dropped++;
1027 		dev_kfree_skb_any(skb);
1028 	}
1029 
1030 	return NETDEV_TX_OK;
1031 }
1032 
1033 
1034 /* tx napi ******************************************************************/
1035 static void txq_kick(struct tx_queue *txq)
1036 {
1037 	struct mv643xx_eth_private *mp = txq_to_mp(txq);
1038 	struct netdev_queue *nq = netdev_get_tx_queue(mp->dev, txq->index);
1039 	u32 hw_desc_ptr;
1040 	u32 expected_ptr;
1041 
1042 	__netif_tx_lock(nq, smp_processor_id());
1043 
1044 	if (rdlp(mp, TXQ_COMMAND) & (1 << txq->index))
1045 		goto out;
1046 
1047 	hw_desc_ptr = rdlp(mp, TXQ_CURRENT_DESC_PTR(txq->index));
1048 	expected_ptr = (u32)txq->tx_desc_dma +
1049 				txq->tx_curr_desc * sizeof(struct tx_desc);
1050 
1051 	if (hw_desc_ptr != expected_ptr)
1052 		txq_enable(txq);
1053 
1054 out:
1055 	__netif_tx_unlock(nq);
1056 
1057 	mp->work_tx_end &= ~(1 << txq->index);
1058 }
1059 
1060 static int txq_reclaim(struct tx_queue *txq, int budget, int force)
1061 {
1062 	struct mv643xx_eth_private *mp = txq_to_mp(txq);
1063 	struct netdev_queue *nq = netdev_get_tx_queue(mp->dev, txq->index);
1064 	int reclaimed;
1065 
1066 	__netif_tx_lock_bh(nq);
1067 
1068 	reclaimed = 0;
1069 	while (reclaimed < budget && txq->tx_desc_count > 0) {
1070 		int tx_index;
1071 		struct tx_desc *desc;
1072 		u32 cmd_sts;
1073 		char desc_dma_map;
1074 
1075 		tx_index = txq->tx_used_desc;
1076 		desc = &txq->tx_desc_area[tx_index];
1077 		desc_dma_map = txq->tx_desc_mapping[tx_index];
1078 
1079 		cmd_sts = desc->cmd_sts;
1080 
1081 		if (cmd_sts & BUFFER_OWNED_BY_DMA) {
1082 			if (!force)
1083 				break;
1084 			desc->cmd_sts = cmd_sts & ~BUFFER_OWNED_BY_DMA;
1085 		}
1086 
1087 		txq->tx_used_desc = tx_index + 1;
1088 		if (txq->tx_used_desc == txq->tx_ring_size)
1089 			txq->tx_used_desc = 0;
1090 
1091 		reclaimed++;
1092 		txq->tx_desc_count--;
1093 
1094 		if (!IS_TSO_HEADER(txq, desc->buf_ptr)) {
1095 
1096 			if (desc_dma_map == DESC_DMA_MAP_PAGE)
1097 				dma_unmap_page(mp->dev->dev.parent,
1098 					       desc->buf_ptr,
1099 					       desc->byte_cnt,
1100 					       DMA_TO_DEVICE);
1101 			else
1102 				dma_unmap_single(mp->dev->dev.parent,
1103 						 desc->buf_ptr,
1104 						 desc->byte_cnt,
1105 						 DMA_TO_DEVICE);
1106 		}
1107 
1108 		if (cmd_sts & TX_ENABLE_INTERRUPT) {
1109 			struct sk_buff *skb = __skb_dequeue(&txq->tx_skb);
1110 
1111 			if (!WARN_ON(!skb))
1112 				dev_consume_skb_any(skb);
1113 		}
1114 
1115 		if (cmd_sts & ERROR_SUMMARY) {
1116 			netdev_info(mp->dev, "tx error\n");
1117 			mp->dev->stats.tx_errors++;
1118 		}
1119 
1120 	}
1121 
1122 	__netif_tx_unlock_bh(nq);
1123 
1124 	if (reclaimed < budget)
1125 		mp->work_tx &= ~(1 << txq->index);
1126 
1127 	return reclaimed;
1128 }
1129 
1130 
1131 /* tx rate control **********************************************************/
1132 /*
1133  * Set total maximum TX rate (shared by all TX queues for this port)
1134  * to 'rate' bits per second, with a maximum burst of 'burst' bytes.
1135  */
1136 static void tx_set_rate(struct mv643xx_eth_private *mp, int rate, int burst)
1137 {
1138 	int token_rate;
1139 	int mtu;
1140 	int bucket_size;
1141 
1142 	token_rate = ((rate / 1000) * 64) / (mp->t_clk / 1000);
1143 	if (token_rate > 1023)
1144 		token_rate = 1023;
1145 
1146 	mtu = (mp->dev->mtu + 255) >> 8;
1147 	if (mtu > 63)
1148 		mtu = 63;
1149 
1150 	bucket_size = (burst + 255) >> 8;
1151 	if (bucket_size > 65535)
1152 		bucket_size = 65535;
1153 
1154 	switch (mp->shared->tx_bw_control) {
1155 	case TX_BW_CONTROL_OLD_LAYOUT:
1156 		wrlp(mp, TX_BW_RATE, token_rate);
1157 		wrlp(mp, TX_BW_MTU, mtu);
1158 		wrlp(mp, TX_BW_BURST, bucket_size);
1159 		break;
1160 	case TX_BW_CONTROL_NEW_LAYOUT:
1161 		wrlp(mp, TX_BW_RATE_MOVED, token_rate);
1162 		wrlp(mp, TX_BW_MTU_MOVED, mtu);
1163 		wrlp(mp, TX_BW_BURST_MOVED, bucket_size);
1164 		break;
1165 	}
1166 }
1167 
1168 static void txq_set_rate(struct tx_queue *txq, int rate, int burst)
1169 {
1170 	struct mv643xx_eth_private *mp = txq_to_mp(txq);
1171 	int token_rate;
1172 	int bucket_size;
1173 
1174 	token_rate = ((rate / 1000) * 64) / (mp->t_clk / 1000);
1175 	if (token_rate > 1023)
1176 		token_rate = 1023;
1177 
1178 	bucket_size = (burst + 255) >> 8;
1179 	if (bucket_size > 65535)
1180 		bucket_size = 65535;
1181 
1182 	wrlp(mp, TXQ_BW_TOKENS(txq->index), token_rate << 14);
1183 	wrlp(mp, TXQ_BW_CONF(txq->index), (bucket_size << 10) | token_rate);
1184 }
1185 
1186 static void txq_set_fixed_prio_mode(struct tx_queue *txq)
1187 {
1188 	struct mv643xx_eth_private *mp = txq_to_mp(txq);
1189 	int off;
1190 	u32 val;
1191 
1192 	/*
1193 	 * Turn on fixed priority mode.
1194 	 */
1195 	off = 0;
1196 	switch (mp->shared->tx_bw_control) {
1197 	case TX_BW_CONTROL_OLD_LAYOUT:
1198 		off = TXQ_FIX_PRIO_CONF;
1199 		break;
1200 	case TX_BW_CONTROL_NEW_LAYOUT:
1201 		off = TXQ_FIX_PRIO_CONF_MOVED;
1202 		break;
1203 	}
1204 
1205 	if (off) {
1206 		val = rdlp(mp, off);
1207 		val |= 1 << txq->index;
1208 		wrlp(mp, off, val);
1209 	}
1210 }
1211 
1212 
1213 /* mii management interface *************************************************/
1214 static void mv643xx_eth_adjust_link(struct net_device *dev)
1215 {
1216 	struct mv643xx_eth_private *mp = netdev_priv(dev);
1217 	u32 pscr = rdlp(mp, PORT_SERIAL_CONTROL);
1218 	u32 autoneg_disable = FORCE_LINK_PASS |
1219 	             DISABLE_AUTO_NEG_SPEED_GMII |
1220 		     DISABLE_AUTO_NEG_FOR_FLOW_CTRL |
1221 		     DISABLE_AUTO_NEG_FOR_DUPLEX;
1222 
1223 	if (dev->phydev->autoneg == AUTONEG_ENABLE) {
1224 		/* enable auto negotiation */
1225 		pscr &= ~autoneg_disable;
1226 		goto out_write;
1227 	}
1228 
1229 	pscr |= autoneg_disable;
1230 
1231 	if (dev->phydev->speed == SPEED_1000) {
1232 		/* force gigabit, half duplex not supported */
1233 		pscr |= SET_GMII_SPEED_TO_1000;
1234 		pscr |= SET_FULL_DUPLEX_MODE;
1235 		goto out_write;
1236 	}
1237 
1238 	pscr &= ~SET_GMII_SPEED_TO_1000;
1239 
1240 	if (dev->phydev->speed == SPEED_100)
1241 		pscr |= SET_MII_SPEED_TO_100;
1242 	else
1243 		pscr &= ~SET_MII_SPEED_TO_100;
1244 
1245 	if (dev->phydev->duplex == DUPLEX_FULL)
1246 		pscr |= SET_FULL_DUPLEX_MODE;
1247 	else
1248 		pscr &= ~SET_FULL_DUPLEX_MODE;
1249 
1250 out_write:
1251 	wrlp(mp, PORT_SERIAL_CONTROL, pscr);
1252 }
1253 
1254 /* statistics ***************************************************************/
1255 static struct net_device_stats *mv643xx_eth_get_stats(struct net_device *dev)
1256 {
1257 	struct mv643xx_eth_private *mp = netdev_priv(dev);
1258 	struct net_device_stats *stats = &dev->stats;
1259 	unsigned long tx_packets = 0;
1260 	unsigned long tx_bytes = 0;
1261 	unsigned long tx_dropped = 0;
1262 	int i;
1263 
1264 	for (i = 0; i < mp->txq_count; i++) {
1265 		struct tx_queue *txq = mp->txq + i;
1266 
1267 		tx_packets += txq->tx_packets;
1268 		tx_bytes += txq->tx_bytes;
1269 		tx_dropped += txq->tx_dropped;
1270 	}
1271 
1272 	stats->tx_packets = tx_packets;
1273 	stats->tx_bytes = tx_bytes;
1274 	stats->tx_dropped = tx_dropped;
1275 
1276 	return stats;
1277 }
1278 
1279 static inline u32 mib_read(struct mv643xx_eth_private *mp, int offset)
1280 {
1281 	return rdl(mp, MIB_COUNTERS(mp->port_num) + offset);
1282 }
1283 
1284 static void mib_counters_clear(struct mv643xx_eth_private *mp)
1285 {
1286 	int i;
1287 
1288 	for (i = 0; i < 0x80; i += 4)
1289 		mib_read(mp, i);
1290 
1291 	/* Clear non MIB hw counters also */
1292 	rdlp(mp, RX_DISCARD_FRAME_CNT);
1293 	rdlp(mp, RX_OVERRUN_FRAME_CNT);
1294 }
1295 
1296 static void mib_counters_update(struct mv643xx_eth_private *mp)
1297 {
1298 	struct mib_counters *p = &mp->mib_counters;
1299 
1300 	spin_lock_bh(&mp->mib_counters_lock);
1301 	p->good_octets_received += mib_read(mp, 0x00);
1302 	p->bad_octets_received += mib_read(mp, 0x08);
1303 	p->internal_mac_transmit_err += mib_read(mp, 0x0c);
1304 	p->good_frames_received += mib_read(mp, 0x10);
1305 	p->bad_frames_received += mib_read(mp, 0x14);
1306 	p->broadcast_frames_received += mib_read(mp, 0x18);
1307 	p->multicast_frames_received += mib_read(mp, 0x1c);
1308 	p->frames_64_octets += mib_read(mp, 0x20);
1309 	p->frames_65_to_127_octets += mib_read(mp, 0x24);
1310 	p->frames_128_to_255_octets += mib_read(mp, 0x28);
1311 	p->frames_256_to_511_octets += mib_read(mp, 0x2c);
1312 	p->frames_512_to_1023_octets += mib_read(mp, 0x30);
1313 	p->frames_1024_to_max_octets += mib_read(mp, 0x34);
1314 	p->good_octets_sent += mib_read(mp, 0x38);
1315 	p->good_frames_sent += mib_read(mp, 0x40);
1316 	p->excessive_collision += mib_read(mp, 0x44);
1317 	p->multicast_frames_sent += mib_read(mp, 0x48);
1318 	p->broadcast_frames_sent += mib_read(mp, 0x4c);
1319 	p->unrec_mac_control_received += mib_read(mp, 0x50);
1320 	p->fc_sent += mib_read(mp, 0x54);
1321 	p->good_fc_received += mib_read(mp, 0x58);
1322 	p->bad_fc_received += mib_read(mp, 0x5c);
1323 	p->undersize_received += mib_read(mp, 0x60);
1324 	p->fragments_received += mib_read(mp, 0x64);
1325 	p->oversize_received += mib_read(mp, 0x68);
1326 	p->jabber_received += mib_read(mp, 0x6c);
1327 	p->mac_receive_error += mib_read(mp, 0x70);
1328 	p->bad_crc_event += mib_read(mp, 0x74);
1329 	p->collision += mib_read(mp, 0x78);
1330 	p->late_collision += mib_read(mp, 0x7c);
1331 	/* Non MIB hardware counters */
1332 	p->rx_discard += rdlp(mp, RX_DISCARD_FRAME_CNT);
1333 	p->rx_overrun += rdlp(mp, RX_OVERRUN_FRAME_CNT);
1334 	spin_unlock_bh(&mp->mib_counters_lock);
1335 }
1336 
1337 static void mib_counters_timer_wrapper(struct timer_list *t)
1338 {
1339 	struct mv643xx_eth_private *mp = from_timer(mp, t, mib_counters_timer);
1340 	mib_counters_update(mp);
1341 	mod_timer(&mp->mib_counters_timer, jiffies + 30 * HZ);
1342 }
1343 
1344 
1345 /* interrupt coalescing *****************************************************/
1346 /*
1347  * Hardware coalescing parameters are set in units of 64 t_clk
1348  * cycles.  I.e.:
1349  *
1350  *	coal_delay_in_usec = 64000000 * register_value / t_clk_rate
1351  *
1352  *	register_value = coal_delay_in_usec * t_clk_rate / 64000000
1353  *
1354  * In the ->set*() methods, we round the computed register value
1355  * to the nearest integer.
1356  */
1357 static unsigned int get_rx_coal(struct mv643xx_eth_private *mp)
1358 {
1359 	u32 val = rdlp(mp, SDMA_CONFIG);
1360 	u64 temp;
1361 
1362 	if (mp->shared->extended_rx_coal_limit)
1363 		temp = ((val & 0x02000000) >> 10) | ((val & 0x003fff80) >> 7);
1364 	else
1365 		temp = (val & 0x003fff00) >> 8;
1366 
1367 	temp *= 64000000;
1368 	temp += mp->t_clk / 2;
1369 	do_div(temp, mp->t_clk);
1370 
1371 	return (unsigned int)temp;
1372 }
1373 
1374 static void set_rx_coal(struct mv643xx_eth_private *mp, unsigned int usec)
1375 {
1376 	u64 temp;
1377 	u32 val;
1378 
1379 	temp = (u64)usec * mp->t_clk;
1380 	temp += 31999999;
1381 	do_div(temp, 64000000);
1382 
1383 	val = rdlp(mp, SDMA_CONFIG);
1384 	if (mp->shared->extended_rx_coal_limit) {
1385 		if (temp > 0xffff)
1386 			temp = 0xffff;
1387 		val &= ~0x023fff80;
1388 		val |= (temp & 0x8000) << 10;
1389 		val |= (temp & 0x7fff) << 7;
1390 	} else {
1391 		if (temp > 0x3fff)
1392 			temp = 0x3fff;
1393 		val &= ~0x003fff00;
1394 		val |= (temp & 0x3fff) << 8;
1395 	}
1396 	wrlp(mp, SDMA_CONFIG, val);
1397 }
1398 
1399 static unsigned int get_tx_coal(struct mv643xx_eth_private *mp)
1400 {
1401 	u64 temp;
1402 
1403 	temp = (rdlp(mp, TX_FIFO_URGENT_THRESHOLD) & 0x3fff0) >> 4;
1404 	temp *= 64000000;
1405 	temp += mp->t_clk / 2;
1406 	do_div(temp, mp->t_clk);
1407 
1408 	return (unsigned int)temp;
1409 }
1410 
1411 static void set_tx_coal(struct mv643xx_eth_private *mp, unsigned int usec)
1412 {
1413 	u64 temp;
1414 
1415 	temp = (u64)usec * mp->t_clk;
1416 	temp += 31999999;
1417 	do_div(temp, 64000000);
1418 
1419 	if (temp > 0x3fff)
1420 		temp = 0x3fff;
1421 
1422 	wrlp(mp, TX_FIFO_URGENT_THRESHOLD, temp << 4);
1423 }
1424 
1425 
1426 /* ethtool ******************************************************************/
1427 struct mv643xx_eth_stats {
1428 	char stat_string[ETH_GSTRING_LEN];
1429 	int sizeof_stat;
1430 	int netdev_off;
1431 	int mp_off;
1432 };
1433 
1434 #define SSTAT(m)						\
1435 	{ #m, sizeof_field(struct net_device_stats, m),		\
1436 	  offsetof(struct net_device, stats.m), -1 }
1437 
1438 #define MIBSTAT(m)						\
1439 	{ #m, sizeof_field(struct mib_counters, m),		\
1440 	  -1, offsetof(struct mv643xx_eth_private, mib_counters.m) }
1441 
1442 static const struct mv643xx_eth_stats mv643xx_eth_stats[] = {
1443 	SSTAT(rx_packets),
1444 	SSTAT(tx_packets),
1445 	SSTAT(rx_bytes),
1446 	SSTAT(tx_bytes),
1447 	SSTAT(rx_errors),
1448 	SSTAT(tx_errors),
1449 	SSTAT(rx_dropped),
1450 	SSTAT(tx_dropped),
1451 	MIBSTAT(good_octets_received),
1452 	MIBSTAT(bad_octets_received),
1453 	MIBSTAT(internal_mac_transmit_err),
1454 	MIBSTAT(good_frames_received),
1455 	MIBSTAT(bad_frames_received),
1456 	MIBSTAT(broadcast_frames_received),
1457 	MIBSTAT(multicast_frames_received),
1458 	MIBSTAT(frames_64_octets),
1459 	MIBSTAT(frames_65_to_127_octets),
1460 	MIBSTAT(frames_128_to_255_octets),
1461 	MIBSTAT(frames_256_to_511_octets),
1462 	MIBSTAT(frames_512_to_1023_octets),
1463 	MIBSTAT(frames_1024_to_max_octets),
1464 	MIBSTAT(good_octets_sent),
1465 	MIBSTAT(good_frames_sent),
1466 	MIBSTAT(excessive_collision),
1467 	MIBSTAT(multicast_frames_sent),
1468 	MIBSTAT(broadcast_frames_sent),
1469 	MIBSTAT(unrec_mac_control_received),
1470 	MIBSTAT(fc_sent),
1471 	MIBSTAT(good_fc_received),
1472 	MIBSTAT(bad_fc_received),
1473 	MIBSTAT(undersize_received),
1474 	MIBSTAT(fragments_received),
1475 	MIBSTAT(oversize_received),
1476 	MIBSTAT(jabber_received),
1477 	MIBSTAT(mac_receive_error),
1478 	MIBSTAT(bad_crc_event),
1479 	MIBSTAT(collision),
1480 	MIBSTAT(late_collision),
1481 	MIBSTAT(rx_discard),
1482 	MIBSTAT(rx_overrun),
1483 };
1484 
1485 static int
1486 mv643xx_eth_get_link_ksettings_phy(struct mv643xx_eth_private *mp,
1487 				   struct ethtool_link_ksettings *cmd)
1488 {
1489 	struct net_device *dev = mp->dev;
1490 
1491 	phy_ethtool_ksettings_get(dev->phydev, cmd);
1492 
1493 	/*
1494 	 * The MAC does not support 1000baseT_Half.
1495 	 */
1496 	linkmode_clear_bit(ETHTOOL_LINK_MODE_1000baseT_Half_BIT,
1497 			   cmd->link_modes.supported);
1498 	linkmode_clear_bit(ETHTOOL_LINK_MODE_1000baseT_Half_BIT,
1499 			   cmd->link_modes.advertising);
1500 
1501 	return 0;
1502 }
1503 
1504 static int
1505 mv643xx_eth_get_link_ksettings_phyless(struct mv643xx_eth_private *mp,
1506 				       struct ethtool_link_ksettings *cmd)
1507 {
1508 	u32 port_status;
1509 	u32 supported, advertising;
1510 
1511 	port_status = rdlp(mp, PORT_STATUS);
1512 
1513 	supported = SUPPORTED_MII;
1514 	advertising = ADVERTISED_MII;
1515 	switch (port_status & PORT_SPEED_MASK) {
1516 	case PORT_SPEED_10:
1517 		cmd->base.speed = SPEED_10;
1518 		break;
1519 	case PORT_SPEED_100:
1520 		cmd->base.speed = SPEED_100;
1521 		break;
1522 	case PORT_SPEED_1000:
1523 		cmd->base.speed = SPEED_1000;
1524 		break;
1525 	default:
1526 		cmd->base.speed = -1;
1527 		break;
1528 	}
1529 	cmd->base.duplex = (port_status & FULL_DUPLEX) ?
1530 		DUPLEX_FULL : DUPLEX_HALF;
1531 	cmd->base.port = PORT_MII;
1532 	cmd->base.phy_address = 0;
1533 	cmd->base.autoneg = AUTONEG_DISABLE;
1534 
1535 	ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.supported,
1536 						supported);
1537 	ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.advertising,
1538 						advertising);
1539 
1540 	return 0;
1541 }
1542 
1543 static void
1544 mv643xx_eth_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1545 {
1546 	wol->supported = 0;
1547 	wol->wolopts = 0;
1548 	if (dev->phydev)
1549 		phy_ethtool_get_wol(dev->phydev, wol);
1550 }
1551 
1552 static int
1553 mv643xx_eth_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1554 {
1555 	int err;
1556 
1557 	if (!dev->phydev)
1558 		return -EOPNOTSUPP;
1559 
1560 	err = phy_ethtool_set_wol(dev->phydev, wol);
1561 	/* Given that mv643xx_eth works without the marvell-specific PHY driver,
1562 	 * this debugging hint is useful to have.
1563 	 */
1564 	if (err == -EOPNOTSUPP)
1565 		netdev_info(dev, "The PHY does not support set_wol, was CONFIG_MARVELL_PHY enabled?\n");
1566 	return err;
1567 }
1568 
1569 static int
1570 mv643xx_eth_get_link_ksettings(struct net_device *dev,
1571 			       struct ethtool_link_ksettings *cmd)
1572 {
1573 	struct mv643xx_eth_private *mp = netdev_priv(dev);
1574 
1575 	if (dev->phydev)
1576 		return mv643xx_eth_get_link_ksettings_phy(mp, cmd);
1577 	else
1578 		return mv643xx_eth_get_link_ksettings_phyless(mp, cmd);
1579 }
1580 
1581 static int
1582 mv643xx_eth_set_link_ksettings(struct net_device *dev,
1583 			       const struct ethtool_link_ksettings *cmd)
1584 {
1585 	struct ethtool_link_ksettings c = *cmd;
1586 	u32 advertising;
1587 	int ret;
1588 
1589 	if (!dev->phydev)
1590 		return -EINVAL;
1591 
1592 	/*
1593 	 * The MAC does not support 1000baseT_Half.
1594 	 */
1595 	ethtool_convert_link_mode_to_legacy_u32(&advertising,
1596 						c.link_modes.advertising);
1597 	advertising &= ~ADVERTISED_1000baseT_Half;
1598 	ethtool_convert_legacy_u32_to_link_mode(c.link_modes.advertising,
1599 						advertising);
1600 
1601 	ret = phy_ethtool_ksettings_set(dev->phydev, &c);
1602 	if (!ret)
1603 		mv643xx_eth_adjust_link(dev);
1604 	return ret;
1605 }
1606 
1607 static void mv643xx_eth_get_drvinfo(struct net_device *dev,
1608 				    struct ethtool_drvinfo *drvinfo)
1609 {
1610 	strlcpy(drvinfo->driver, mv643xx_eth_driver_name,
1611 		sizeof(drvinfo->driver));
1612 	strlcpy(drvinfo->version, mv643xx_eth_driver_version,
1613 		sizeof(drvinfo->version));
1614 	strlcpy(drvinfo->fw_version, "N/A", sizeof(drvinfo->fw_version));
1615 	strlcpy(drvinfo->bus_info, "platform", sizeof(drvinfo->bus_info));
1616 }
1617 
1618 static int
1619 mv643xx_eth_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
1620 {
1621 	struct mv643xx_eth_private *mp = netdev_priv(dev);
1622 
1623 	ec->rx_coalesce_usecs = get_rx_coal(mp);
1624 	ec->tx_coalesce_usecs = get_tx_coal(mp);
1625 
1626 	return 0;
1627 }
1628 
1629 static int
1630 mv643xx_eth_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
1631 {
1632 	struct mv643xx_eth_private *mp = netdev_priv(dev);
1633 
1634 	set_rx_coal(mp, ec->rx_coalesce_usecs);
1635 	set_tx_coal(mp, ec->tx_coalesce_usecs);
1636 
1637 	return 0;
1638 }
1639 
1640 static void
1641 mv643xx_eth_get_ringparam(struct net_device *dev, struct ethtool_ringparam *er)
1642 {
1643 	struct mv643xx_eth_private *mp = netdev_priv(dev);
1644 
1645 	er->rx_max_pending = 4096;
1646 	er->tx_max_pending = 4096;
1647 
1648 	er->rx_pending = mp->rx_ring_size;
1649 	er->tx_pending = mp->tx_ring_size;
1650 }
1651 
1652 static int
1653 mv643xx_eth_set_ringparam(struct net_device *dev, struct ethtool_ringparam *er)
1654 {
1655 	struct mv643xx_eth_private *mp = netdev_priv(dev);
1656 
1657 	if (er->rx_mini_pending || er->rx_jumbo_pending)
1658 		return -EINVAL;
1659 
1660 	mp->rx_ring_size = er->rx_pending < 4096 ? er->rx_pending : 4096;
1661 	mp->tx_ring_size = clamp_t(unsigned int, er->tx_pending,
1662 				   MV643XX_MAX_SKB_DESCS * 2, 4096);
1663 	if (mp->tx_ring_size != er->tx_pending)
1664 		netdev_warn(dev, "TX queue size set to %u (requested %u)\n",
1665 			    mp->tx_ring_size, er->tx_pending);
1666 
1667 	if (netif_running(dev)) {
1668 		mv643xx_eth_stop(dev);
1669 		if (mv643xx_eth_open(dev)) {
1670 			netdev_err(dev,
1671 				   "fatal error on re-opening device after ring param change\n");
1672 			return -ENOMEM;
1673 		}
1674 	}
1675 
1676 	return 0;
1677 }
1678 
1679 
1680 static int
1681 mv643xx_eth_set_features(struct net_device *dev, netdev_features_t features)
1682 {
1683 	struct mv643xx_eth_private *mp = netdev_priv(dev);
1684 	bool rx_csum = features & NETIF_F_RXCSUM;
1685 
1686 	wrlp(mp, PORT_CONFIG, rx_csum ? 0x02000000 : 0x00000000);
1687 
1688 	return 0;
1689 }
1690 
1691 static void mv643xx_eth_get_strings(struct net_device *dev,
1692 				    uint32_t stringset, uint8_t *data)
1693 {
1694 	int i;
1695 
1696 	if (stringset == ETH_SS_STATS) {
1697 		for (i = 0; i < ARRAY_SIZE(mv643xx_eth_stats); i++) {
1698 			memcpy(data + i * ETH_GSTRING_LEN,
1699 				mv643xx_eth_stats[i].stat_string,
1700 				ETH_GSTRING_LEN);
1701 		}
1702 	}
1703 }
1704 
1705 static void mv643xx_eth_get_ethtool_stats(struct net_device *dev,
1706 					  struct ethtool_stats *stats,
1707 					  uint64_t *data)
1708 {
1709 	struct mv643xx_eth_private *mp = netdev_priv(dev);
1710 	int i;
1711 
1712 	mv643xx_eth_get_stats(dev);
1713 	mib_counters_update(mp);
1714 
1715 	for (i = 0; i < ARRAY_SIZE(mv643xx_eth_stats); i++) {
1716 		const struct mv643xx_eth_stats *stat;
1717 		void *p;
1718 
1719 		stat = mv643xx_eth_stats + i;
1720 
1721 		if (stat->netdev_off >= 0)
1722 			p = ((void *)mp->dev) + stat->netdev_off;
1723 		else
1724 			p = ((void *)mp) + stat->mp_off;
1725 
1726 		data[i] = (stat->sizeof_stat == 8) ?
1727 				*(uint64_t *)p : *(uint32_t *)p;
1728 	}
1729 }
1730 
1731 static int mv643xx_eth_get_sset_count(struct net_device *dev, int sset)
1732 {
1733 	if (sset == ETH_SS_STATS)
1734 		return ARRAY_SIZE(mv643xx_eth_stats);
1735 
1736 	return -EOPNOTSUPP;
1737 }
1738 
1739 static const struct ethtool_ops mv643xx_eth_ethtool_ops = {
1740 	.get_drvinfo		= mv643xx_eth_get_drvinfo,
1741 	.nway_reset		= phy_ethtool_nway_reset,
1742 	.get_link		= ethtool_op_get_link,
1743 	.get_coalesce		= mv643xx_eth_get_coalesce,
1744 	.set_coalesce		= mv643xx_eth_set_coalesce,
1745 	.get_ringparam		= mv643xx_eth_get_ringparam,
1746 	.set_ringparam		= mv643xx_eth_set_ringparam,
1747 	.get_strings		= mv643xx_eth_get_strings,
1748 	.get_ethtool_stats	= mv643xx_eth_get_ethtool_stats,
1749 	.get_sset_count		= mv643xx_eth_get_sset_count,
1750 	.get_ts_info		= ethtool_op_get_ts_info,
1751 	.get_wol                = mv643xx_eth_get_wol,
1752 	.set_wol                = mv643xx_eth_set_wol,
1753 	.get_link_ksettings	= mv643xx_eth_get_link_ksettings,
1754 	.set_link_ksettings	= mv643xx_eth_set_link_ksettings,
1755 };
1756 
1757 
1758 /* address handling *********************************************************/
1759 static void uc_addr_get(struct mv643xx_eth_private *mp, unsigned char *addr)
1760 {
1761 	unsigned int mac_h = rdlp(mp, MAC_ADDR_HIGH);
1762 	unsigned int mac_l = rdlp(mp, MAC_ADDR_LOW);
1763 
1764 	addr[0] = (mac_h >> 24) & 0xff;
1765 	addr[1] = (mac_h >> 16) & 0xff;
1766 	addr[2] = (mac_h >> 8) & 0xff;
1767 	addr[3] = mac_h & 0xff;
1768 	addr[4] = (mac_l >> 8) & 0xff;
1769 	addr[5] = mac_l & 0xff;
1770 }
1771 
1772 static void uc_addr_set(struct mv643xx_eth_private *mp, unsigned char *addr)
1773 {
1774 	wrlp(mp, MAC_ADDR_HIGH,
1775 		(addr[0] << 24) | (addr[1] << 16) | (addr[2] << 8) | addr[3]);
1776 	wrlp(mp, MAC_ADDR_LOW, (addr[4] << 8) | addr[5]);
1777 }
1778 
1779 static u32 uc_addr_filter_mask(struct net_device *dev)
1780 {
1781 	struct netdev_hw_addr *ha;
1782 	u32 nibbles;
1783 
1784 	if (dev->flags & IFF_PROMISC)
1785 		return 0;
1786 
1787 	nibbles = 1 << (dev->dev_addr[5] & 0x0f);
1788 	netdev_for_each_uc_addr(ha, dev) {
1789 		if (memcmp(dev->dev_addr, ha->addr, 5))
1790 			return 0;
1791 		if ((dev->dev_addr[5] ^ ha->addr[5]) & 0xf0)
1792 			return 0;
1793 
1794 		nibbles |= 1 << (ha->addr[5] & 0x0f);
1795 	}
1796 
1797 	return nibbles;
1798 }
1799 
1800 static void mv643xx_eth_program_unicast_filter(struct net_device *dev)
1801 {
1802 	struct mv643xx_eth_private *mp = netdev_priv(dev);
1803 	u32 port_config;
1804 	u32 nibbles;
1805 	int i;
1806 
1807 	uc_addr_set(mp, dev->dev_addr);
1808 
1809 	port_config = rdlp(mp, PORT_CONFIG) & ~UNICAST_PROMISCUOUS_MODE;
1810 
1811 	nibbles = uc_addr_filter_mask(dev);
1812 	if (!nibbles) {
1813 		port_config |= UNICAST_PROMISCUOUS_MODE;
1814 		nibbles = 0xffff;
1815 	}
1816 
1817 	for (i = 0; i < 16; i += 4) {
1818 		int off = UNICAST_TABLE(mp->port_num) + i;
1819 		u32 v;
1820 
1821 		v = 0;
1822 		if (nibbles & 1)
1823 			v |= 0x00000001;
1824 		if (nibbles & 2)
1825 			v |= 0x00000100;
1826 		if (nibbles & 4)
1827 			v |= 0x00010000;
1828 		if (nibbles & 8)
1829 			v |= 0x01000000;
1830 		nibbles >>= 4;
1831 
1832 		wrl(mp, off, v);
1833 	}
1834 
1835 	wrlp(mp, PORT_CONFIG, port_config);
1836 }
1837 
1838 static int addr_crc(unsigned char *addr)
1839 {
1840 	int crc = 0;
1841 	int i;
1842 
1843 	for (i = 0; i < 6; i++) {
1844 		int j;
1845 
1846 		crc = (crc ^ addr[i]) << 8;
1847 		for (j = 7; j >= 0; j--) {
1848 			if (crc & (0x100 << j))
1849 				crc ^= 0x107 << j;
1850 		}
1851 	}
1852 
1853 	return crc;
1854 }
1855 
1856 static void mv643xx_eth_program_multicast_filter(struct net_device *dev)
1857 {
1858 	struct mv643xx_eth_private *mp = netdev_priv(dev);
1859 	u32 *mc_spec;
1860 	u32 *mc_other;
1861 	struct netdev_hw_addr *ha;
1862 	int i;
1863 
1864 	if (dev->flags & (IFF_PROMISC | IFF_ALLMULTI))
1865 		goto promiscuous;
1866 
1867 	/* Allocate both mc_spec and mc_other tables */
1868 	mc_spec = kcalloc(128, sizeof(u32), GFP_ATOMIC);
1869 	if (!mc_spec)
1870 		goto promiscuous;
1871 	mc_other = &mc_spec[64];
1872 
1873 	netdev_for_each_mc_addr(ha, dev) {
1874 		u8 *a = ha->addr;
1875 		u32 *table;
1876 		u8 entry;
1877 
1878 		if (memcmp(a, "\x01\x00\x5e\x00\x00", 5) == 0) {
1879 			table = mc_spec;
1880 			entry = a[5];
1881 		} else {
1882 			table = mc_other;
1883 			entry = addr_crc(a);
1884 		}
1885 
1886 		table[entry >> 2] |= 1 << (8 * (entry & 3));
1887 	}
1888 
1889 	for (i = 0; i < 64; i++) {
1890 		wrl(mp, SPECIAL_MCAST_TABLE(mp->port_num) + i * sizeof(u32),
1891 		    mc_spec[i]);
1892 		wrl(mp, OTHER_MCAST_TABLE(mp->port_num) + i * sizeof(u32),
1893 		    mc_other[i]);
1894 	}
1895 
1896 	kfree(mc_spec);
1897 	return;
1898 
1899 promiscuous:
1900 	for (i = 0; i < 64; i++) {
1901 		wrl(mp, SPECIAL_MCAST_TABLE(mp->port_num) + i * sizeof(u32),
1902 		    0x01010101u);
1903 		wrl(mp, OTHER_MCAST_TABLE(mp->port_num) + i * sizeof(u32),
1904 		    0x01010101u);
1905 	}
1906 }
1907 
1908 static void mv643xx_eth_set_rx_mode(struct net_device *dev)
1909 {
1910 	mv643xx_eth_program_unicast_filter(dev);
1911 	mv643xx_eth_program_multicast_filter(dev);
1912 }
1913 
1914 static int mv643xx_eth_set_mac_address(struct net_device *dev, void *addr)
1915 {
1916 	struct sockaddr *sa = addr;
1917 
1918 	if (!is_valid_ether_addr(sa->sa_data))
1919 		return -EADDRNOTAVAIL;
1920 
1921 	memcpy(dev->dev_addr, sa->sa_data, ETH_ALEN);
1922 
1923 	netif_addr_lock_bh(dev);
1924 	mv643xx_eth_program_unicast_filter(dev);
1925 	netif_addr_unlock_bh(dev);
1926 
1927 	return 0;
1928 }
1929 
1930 
1931 /* rx/tx queue initialisation ***********************************************/
1932 static int rxq_init(struct mv643xx_eth_private *mp, int index)
1933 {
1934 	struct rx_queue *rxq = mp->rxq + index;
1935 	struct rx_desc *rx_desc;
1936 	int size;
1937 	int i;
1938 
1939 	rxq->index = index;
1940 
1941 	rxq->rx_ring_size = mp->rx_ring_size;
1942 
1943 	rxq->rx_desc_count = 0;
1944 	rxq->rx_curr_desc = 0;
1945 	rxq->rx_used_desc = 0;
1946 
1947 	size = rxq->rx_ring_size * sizeof(struct rx_desc);
1948 
1949 	if (index == 0 && size <= mp->rx_desc_sram_size) {
1950 		rxq->rx_desc_area = ioremap(mp->rx_desc_sram_addr,
1951 						mp->rx_desc_sram_size);
1952 		rxq->rx_desc_dma = mp->rx_desc_sram_addr;
1953 	} else {
1954 		rxq->rx_desc_area = dma_alloc_coherent(mp->dev->dev.parent,
1955 						       size, &rxq->rx_desc_dma,
1956 						       GFP_KERNEL);
1957 	}
1958 
1959 	if (rxq->rx_desc_area == NULL) {
1960 		netdev_err(mp->dev,
1961 			   "can't allocate rx ring (%d bytes)\n", size);
1962 		goto out;
1963 	}
1964 	memset(rxq->rx_desc_area, 0, size);
1965 
1966 	rxq->rx_desc_area_size = size;
1967 	rxq->rx_skb = kcalloc(rxq->rx_ring_size, sizeof(*rxq->rx_skb),
1968 				    GFP_KERNEL);
1969 	if (rxq->rx_skb == NULL)
1970 		goto out_free;
1971 
1972 	rx_desc = rxq->rx_desc_area;
1973 	for (i = 0; i < rxq->rx_ring_size; i++) {
1974 		int nexti;
1975 
1976 		nexti = i + 1;
1977 		if (nexti == rxq->rx_ring_size)
1978 			nexti = 0;
1979 
1980 		rx_desc[i].next_desc_ptr = rxq->rx_desc_dma +
1981 					nexti * sizeof(struct rx_desc);
1982 	}
1983 
1984 	return 0;
1985 
1986 
1987 out_free:
1988 	if (index == 0 && size <= mp->rx_desc_sram_size)
1989 		iounmap(rxq->rx_desc_area);
1990 	else
1991 		dma_free_coherent(mp->dev->dev.parent, size,
1992 				  rxq->rx_desc_area,
1993 				  rxq->rx_desc_dma);
1994 
1995 out:
1996 	return -ENOMEM;
1997 }
1998 
1999 static void rxq_deinit(struct rx_queue *rxq)
2000 {
2001 	struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
2002 	int i;
2003 
2004 	rxq_disable(rxq);
2005 
2006 	for (i = 0; i < rxq->rx_ring_size; i++) {
2007 		if (rxq->rx_skb[i]) {
2008 			dev_consume_skb_any(rxq->rx_skb[i]);
2009 			rxq->rx_desc_count--;
2010 		}
2011 	}
2012 
2013 	if (rxq->rx_desc_count) {
2014 		netdev_err(mp->dev, "error freeing rx ring -- %d skbs stuck\n",
2015 			   rxq->rx_desc_count);
2016 	}
2017 
2018 	if (rxq->index == 0 &&
2019 	    rxq->rx_desc_area_size <= mp->rx_desc_sram_size)
2020 		iounmap(rxq->rx_desc_area);
2021 	else
2022 		dma_free_coherent(mp->dev->dev.parent, rxq->rx_desc_area_size,
2023 				  rxq->rx_desc_area, rxq->rx_desc_dma);
2024 
2025 	kfree(rxq->rx_skb);
2026 }
2027 
2028 static int txq_init(struct mv643xx_eth_private *mp, int index)
2029 {
2030 	struct tx_queue *txq = mp->txq + index;
2031 	struct tx_desc *tx_desc;
2032 	int size;
2033 	int ret;
2034 	int i;
2035 
2036 	txq->index = index;
2037 
2038 	txq->tx_ring_size = mp->tx_ring_size;
2039 
2040 	/* A queue must always have room for at least one skb.
2041 	 * Therefore, stop the queue when the free entries reaches
2042 	 * the maximum number of descriptors per skb.
2043 	 */
2044 	txq->tx_stop_threshold = txq->tx_ring_size - MV643XX_MAX_SKB_DESCS;
2045 	txq->tx_wake_threshold = txq->tx_stop_threshold / 2;
2046 
2047 	txq->tx_desc_count = 0;
2048 	txq->tx_curr_desc = 0;
2049 	txq->tx_used_desc = 0;
2050 
2051 	size = txq->tx_ring_size * sizeof(struct tx_desc);
2052 
2053 	if (index == 0 && size <= mp->tx_desc_sram_size) {
2054 		txq->tx_desc_area = ioremap(mp->tx_desc_sram_addr,
2055 						mp->tx_desc_sram_size);
2056 		txq->tx_desc_dma = mp->tx_desc_sram_addr;
2057 	} else {
2058 		txq->tx_desc_area = dma_alloc_coherent(mp->dev->dev.parent,
2059 						       size, &txq->tx_desc_dma,
2060 						       GFP_KERNEL);
2061 	}
2062 
2063 	if (txq->tx_desc_area == NULL) {
2064 		netdev_err(mp->dev,
2065 			   "can't allocate tx ring (%d bytes)\n", size);
2066 		return -ENOMEM;
2067 	}
2068 	memset(txq->tx_desc_area, 0, size);
2069 
2070 	txq->tx_desc_area_size = size;
2071 
2072 	tx_desc = txq->tx_desc_area;
2073 	for (i = 0; i < txq->tx_ring_size; i++) {
2074 		struct tx_desc *txd = tx_desc + i;
2075 		int nexti;
2076 
2077 		nexti = i + 1;
2078 		if (nexti == txq->tx_ring_size)
2079 			nexti = 0;
2080 
2081 		txd->cmd_sts = 0;
2082 		txd->next_desc_ptr = txq->tx_desc_dma +
2083 					nexti * sizeof(struct tx_desc);
2084 	}
2085 
2086 	txq->tx_desc_mapping = kcalloc(txq->tx_ring_size, sizeof(char),
2087 				       GFP_KERNEL);
2088 	if (!txq->tx_desc_mapping) {
2089 		ret = -ENOMEM;
2090 		goto err_free_desc_area;
2091 	}
2092 
2093 	/* Allocate DMA buffers for TSO MAC/IP/TCP headers */
2094 	txq->tso_hdrs = dma_alloc_coherent(mp->dev->dev.parent,
2095 					   txq->tx_ring_size * TSO_HEADER_SIZE,
2096 					   &txq->tso_hdrs_dma, GFP_KERNEL);
2097 	if (txq->tso_hdrs == NULL) {
2098 		ret = -ENOMEM;
2099 		goto err_free_desc_mapping;
2100 	}
2101 	skb_queue_head_init(&txq->tx_skb);
2102 
2103 	return 0;
2104 
2105 err_free_desc_mapping:
2106 	kfree(txq->tx_desc_mapping);
2107 err_free_desc_area:
2108 	if (index == 0 && size <= mp->tx_desc_sram_size)
2109 		iounmap(txq->tx_desc_area);
2110 	else
2111 		dma_free_coherent(mp->dev->dev.parent, txq->tx_desc_area_size,
2112 				  txq->tx_desc_area, txq->tx_desc_dma);
2113 	return ret;
2114 }
2115 
2116 static void txq_deinit(struct tx_queue *txq)
2117 {
2118 	struct mv643xx_eth_private *mp = txq_to_mp(txq);
2119 
2120 	txq_disable(txq);
2121 	txq_reclaim(txq, txq->tx_ring_size, 1);
2122 
2123 	BUG_ON(txq->tx_used_desc != txq->tx_curr_desc);
2124 
2125 	if (txq->index == 0 &&
2126 	    txq->tx_desc_area_size <= mp->tx_desc_sram_size)
2127 		iounmap(txq->tx_desc_area);
2128 	else
2129 		dma_free_coherent(mp->dev->dev.parent, txq->tx_desc_area_size,
2130 				  txq->tx_desc_area, txq->tx_desc_dma);
2131 	kfree(txq->tx_desc_mapping);
2132 
2133 	if (txq->tso_hdrs)
2134 		dma_free_coherent(mp->dev->dev.parent,
2135 				  txq->tx_ring_size * TSO_HEADER_SIZE,
2136 				  txq->tso_hdrs, txq->tso_hdrs_dma);
2137 }
2138 
2139 
2140 /* netdev ops and related ***************************************************/
2141 static int mv643xx_eth_collect_events(struct mv643xx_eth_private *mp)
2142 {
2143 	u32 int_cause;
2144 	u32 int_cause_ext;
2145 
2146 	int_cause = rdlp(mp, INT_CAUSE) & mp->int_mask;
2147 	if (int_cause == 0)
2148 		return 0;
2149 
2150 	int_cause_ext = 0;
2151 	if (int_cause & INT_EXT) {
2152 		int_cause &= ~INT_EXT;
2153 		int_cause_ext = rdlp(mp, INT_CAUSE_EXT);
2154 	}
2155 
2156 	if (int_cause) {
2157 		wrlp(mp, INT_CAUSE, ~int_cause);
2158 		mp->work_tx_end |= ((int_cause & INT_TX_END) >> 19) &
2159 				~(rdlp(mp, TXQ_COMMAND) & 0xff);
2160 		mp->work_rx |= (int_cause & INT_RX) >> 2;
2161 	}
2162 
2163 	int_cause_ext &= INT_EXT_LINK_PHY | INT_EXT_TX;
2164 	if (int_cause_ext) {
2165 		wrlp(mp, INT_CAUSE_EXT, ~int_cause_ext);
2166 		if (int_cause_ext & INT_EXT_LINK_PHY)
2167 			mp->work_link = 1;
2168 		mp->work_tx |= int_cause_ext & INT_EXT_TX;
2169 	}
2170 
2171 	return 1;
2172 }
2173 
2174 static irqreturn_t mv643xx_eth_irq(int irq, void *dev_id)
2175 {
2176 	struct net_device *dev = (struct net_device *)dev_id;
2177 	struct mv643xx_eth_private *mp = netdev_priv(dev);
2178 
2179 	if (unlikely(!mv643xx_eth_collect_events(mp)))
2180 		return IRQ_NONE;
2181 
2182 	wrlp(mp, INT_MASK, 0);
2183 	napi_schedule(&mp->napi);
2184 
2185 	return IRQ_HANDLED;
2186 }
2187 
2188 static void handle_link_event(struct mv643xx_eth_private *mp)
2189 {
2190 	struct net_device *dev = mp->dev;
2191 	u32 port_status;
2192 	int speed;
2193 	int duplex;
2194 	int fc;
2195 
2196 	port_status = rdlp(mp, PORT_STATUS);
2197 	if (!(port_status & LINK_UP)) {
2198 		if (netif_carrier_ok(dev)) {
2199 			int i;
2200 
2201 			netdev_info(dev, "link down\n");
2202 
2203 			netif_carrier_off(dev);
2204 
2205 			for (i = 0; i < mp->txq_count; i++) {
2206 				struct tx_queue *txq = mp->txq + i;
2207 
2208 				txq_reclaim(txq, txq->tx_ring_size, 1);
2209 				txq_reset_hw_ptr(txq);
2210 			}
2211 		}
2212 		return;
2213 	}
2214 
2215 	switch (port_status & PORT_SPEED_MASK) {
2216 	case PORT_SPEED_10:
2217 		speed = 10;
2218 		break;
2219 	case PORT_SPEED_100:
2220 		speed = 100;
2221 		break;
2222 	case PORT_SPEED_1000:
2223 		speed = 1000;
2224 		break;
2225 	default:
2226 		speed = -1;
2227 		break;
2228 	}
2229 	duplex = (port_status & FULL_DUPLEX) ? 1 : 0;
2230 	fc = (port_status & FLOW_CONTROL_ENABLED) ? 1 : 0;
2231 
2232 	netdev_info(dev, "link up, %d Mb/s, %s duplex, flow control %sabled\n",
2233 		    speed, duplex ? "full" : "half", fc ? "en" : "dis");
2234 
2235 	if (!netif_carrier_ok(dev))
2236 		netif_carrier_on(dev);
2237 }
2238 
2239 static int mv643xx_eth_poll(struct napi_struct *napi, int budget)
2240 {
2241 	struct mv643xx_eth_private *mp;
2242 	int work_done;
2243 
2244 	mp = container_of(napi, struct mv643xx_eth_private, napi);
2245 
2246 	if (unlikely(mp->oom)) {
2247 		mp->oom = 0;
2248 		del_timer(&mp->rx_oom);
2249 	}
2250 
2251 	work_done = 0;
2252 	while (work_done < budget) {
2253 		u8 queue_mask;
2254 		int queue;
2255 		int work_tbd;
2256 
2257 		if (mp->work_link) {
2258 			mp->work_link = 0;
2259 			handle_link_event(mp);
2260 			work_done++;
2261 			continue;
2262 		}
2263 
2264 		queue_mask = mp->work_tx | mp->work_tx_end | mp->work_rx;
2265 		if (likely(!mp->oom))
2266 			queue_mask |= mp->work_rx_refill;
2267 
2268 		if (!queue_mask) {
2269 			if (mv643xx_eth_collect_events(mp))
2270 				continue;
2271 			break;
2272 		}
2273 
2274 		queue = fls(queue_mask) - 1;
2275 		queue_mask = 1 << queue;
2276 
2277 		work_tbd = budget - work_done;
2278 		if (work_tbd > 16)
2279 			work_tbd = 16;
2280 
2281 		if (mp->work_tx_end & queue_mask) {
2282 			txq_kick(mp->txq + queue);
2283 		} else if (mp->work_tx & queue_mask) {
2284 			work_done += txq_reclaim(mp->txq + queue, work_tbd, 0);
2285 			txq_maybe_wake(mp->txq + queue);
2286 		} else if (mp->work_rx & queue_mask) {
2287 			work_done += rxq_process(mp->rxq + queue, work_tbd);
2288 		} else if (!mp->oom && (mp->work_rx_refill & queue_mask)) {
2289 			work_done += rxq_refill(mp->rxq + queue, work_tbd);
2290 		} else {
2291 			BUG();
2292 		}
2293 	}
2294 
2295 	if (work_done < budget) {
2296 		if (mp->oom)
2297 			mod_timer(&mp->rx_oom, jiffies + (HZ / 10));
2298 		napi_complete_done(napi, work_done);
2299 		wrlp(mp, INT_MASK, mp->int_mask);
2300 	}
2301 
2302 	return work_done;
2303 }
2304 
2305 static inline void oom_timer_wrapper(struct timer_list *t)
2306 {
2307 	struct mv643xx_eth_private *mp = from_timer(mp, t, rx_oom);
2308 
2309 	napi_schedule(&mp->napi);
2310 }
2311 
2312 static void port_start(struct mv643xx_eth_private *mp)
2313 {
2314 	struct net_device *dev = mp->dev;
2315 	u32 pscr;
2316 	int i;
2317 
2318 	/*
2319 	 * Perform PHY reset, if there is a PHY.
2320 	 */
2321 	if (dev->phydev) {
2322 		struct ethtool_link_ksettings cmd;
2323 
2324 		mv643xx_eth_get_link_ksettings(dev, &cmd);
2325 		phy_init_hw(dev->phydev);
2326 		mv643xx_eth_set_link_ksettings(
2327 			dev, (const struct ethtool_link_ksettings *)&cmd);
2328 		phy_start(dev->phydev);
2329 	}
2330 
2331 	/*
2332 	 * Configure basic link parameters.
2333 	 */
2334 	pscr = rdlp(mp, PORT_SERIAL_CONTROL);
2335 
2336 	pscr |= SERIAL_PORT_ENABLE;
2337 	wrlp(mp, PORT_SERIAL_CONTROL, pscr);
2338 
2339 	pscr |= DO_NOT_FORCE_LINK_FAIL;
2340 	if (!dev->phydev)
2341 		pscr |= FORCE_LINK_PASS;
2342 	wrlp(mp, PORT_SERIAL_CONTROL, pscr);
2343 
2344 	/*
2345 	 * Configure TX path and queues.
2346 	 */
2347 	tx_set_rate(mp, 1000000000, 16777216);
2348 	for (i = 0; i < mp->txq_count; i++) {
2349 		struct tx_queue *txq = mp->txq + i;
2350 
2351 		txq_reset_hw_ptr(txq);
2352 		txq_set_rate(txq, 1000000000, 16777216);
2353 		txq_set_fixed_prio_mode(txq);
2354 	}
2355 
2356 	/*
2357 	 * Receive all unmatched unicast, TCP, UDP, BPDU and broadcast
2358 	 * frames to RX queue #0, and include the pseudo-header when
2359 	 * calculating receive checksums.
2360 	 */
2361 	mv643xx_eth_set_features(mp->dev, mp->dev->features);
2362 
2363 	/*
2364 	 * Treat BPDUs as normal multicasts, and disable partition mode.
2365 	 */
2366 	wrlp(mp, PORT_CONFIG_EXT, 0x00000000);
2367 
2368 	/*
2369 	 * Add configured unicast addresses to address filter table.
2370 	 */
2371 	mv643xx_eth_program_unicast_filter(mp->dev);
2372 
2373 	/*
2374 	 * Enable the receive queues.
2375 	 */
2376 	for (i = 0; i < mp->rxq_count; i++) {
2377 		struct rx_queue *rxq = mp->rxq + i;
2378 		u32 addr;
2379 
2380 		addr = (u32)rxq->rx_desc_dma;
2381 		addr += rxq->rx_curr_desc * sizeof(struct rx_desc);
2382 		wrlp(mp, RXQ_CURRENT_DESC_PTR(i), addr);
2383 
2384 		rxq_enable(rxq);
2385 	}
2386 }
2387 
2388 static void mv643xx_eth_recalc_skb_size(struct mv643xx_eth_private *mp)
2389 {
2390 	int skb_size;
2391 
2392 	/*
2393 	 * Reserve 2+14 bytes for an ethernet header (the hardware
2394 	 * automatically prepends 2 bytes of dummy data to each
2395 	 * received packet), 16 bytes for up to four VLAN tags, and
2396 	 * 4 bytes for the trailing FCS -- 36 bytes total.
2397 	 */
2398 	skb_size = mp->dev->mtu + 36;
2399 
2400 	/*
2401 	 * Make sure that the skb size is a multiple of 8 bytes, as
2402 	 * the lower three bits of the receive descriptor's buffer
2403 	 * size field are ignored by the hardware.
2404 	 */
2405 	mp->skb_size = (skb_size + 7) & ~7;
2406 
2407 	/*
2408 	 * If NET_SKB_PAD is smaller than a cache line,
2409 	 * netdev_alloc_skb() will cause skb->data to be misaligned
2410 	 * to a cache line boundary.  If this is the case, include
2411 	 * some extra space to allow re-aligning the data area.
2412 	 */
2413 	mp->skb_size += SKB_DMA_REALIGN;
2414 }
2415 
2416 static int mv643xx_eth_open(struct net_device *dev)
2417 {
2418 	struct mv643xx_eth_private *mp = netdev_priv(dev);
2419 	int err;
2420 	int i;
2421 
2422 	wrlp(mp, INT_CAUSE, 0);
2423 	wrlp(mp, INT_CAUSE_EXT, 0);
2424 	rdlp(mp, INT_CAUSE_EXT);
2425 
2426 	err = request_irq(dev->irq, mv643xx_eth_irq,
2427 			  IRQF_SHARED, dev->name, dev);
2428 	if (err) {
2429 		netdev_err(dev, "can't assign irq\n");
2430 		return -EAGAIN;
2431 	}
2432 
2433 	mv643xx_eth_recalc_skb_size(mp);
2434 
2435 	napi_enable(&mp->napi);
2436 
2437 	mp->int_mask = INT_EXT;
2438 
2439 	for (i = 0; i < mp->rxq_count; i++) {
2440 		err = rxq_init(mp, i);
2441 		if (err) {
2442 			while (--i >= 0)
2443 				rxq_deinit(mp->rxq + i);
2444 			goto out;
2445 		}
2446 
2447 		rxq_refill(mp->rxq + i, INT_MAX);
2448 		mp->int_mask |= INT_RX_0 << i;
2449 	}
2450 
2451 	if (mp->oom) {
2452 		mp->rx_oom.expires = jiffies + (HZ / 10);
2453 		add_timer(&mp->rx_oom);
2454 	}
2455 
2456 	for (i = 0; i < mp->txq_count; i++) {
2457 		err = txq_init(mp, i);
2458 		if (err) {
2459 			while (--i >= 0)
2460 				txq_deinit(mp->txq + i);
2461 			goto out_free;
2462 		}
2463 		mp->int_mask |= INT_TX_END_0 << i;
2464 	}
2465 
2466 	add_timer(&mp->mib_counters_timer);
2467 	port_start(mp);
2468 
2469 	wrlp(mp, INT_MASK_EXT, INT_EXT_LINK_PHY | INT_EXT_TX);
2470 	wrlp(mp, INT_MASK, mp->int_mask);
2471 
2472 	return 0;
2473 
2474 
2475 out_free:
2476 	for (i = 0; i < mp->rxq_count; i++)
2477 		rxq_deinit(mp->rxq + i);
2478 out:
2479 	free_irq(dev->irq, dev);
2480 
2481 	return err;
2482 }
2483 
2484 static void port_reset(struct mv643xx_eth_private *mp)
2485 {
2486 	unsigned int data;
2487 	int i;
2488 
2489 	for (i = 0; i < mp->rxq_count; i++)
2490 		rxq_disable(mp->rxq + i);
2491 	for (i = 0; i < mp->txq_count; i++)
2492 		txq_disable(mp->txq + i);
2493 
2494 	while (1) {
2495 		u32 ps = rdlp(mp, PORT_STATUS);
2496 
2497 		if ((ps & (TX_IN_PROGRESS | TX_FIFO_EMPTY)) == TX_FIFO_EMPTY)
2498 			break;
2499 		udelay(10);
2500 	}
2501 
2502 	/* Reset the Enable bit in the Configuration Register */
2503 	data = rdlp(mp, PORT_SERIAL_CONTROL);
2504 	data &= ~(SERIAL_PORT_ENABLE		|
2505 		  DO_NOT_FORCE_LINK_FAIL	|
2506 		  FORCE_LINK_PASS);
2507 	wrlp(mp, PORT_SERIAL_CONTROL, data);
2508 }
2509 
2510 static int mv643xx_eth_stop(struct net_device *dev)
2511 {
2512 	struct mv643xx_eth_private *mp = netdev_priv(dev);
2513 	int i;
2514 
2515 	wrlp(mp, INT_MASK_EXT, 0x00000000);
2516 	wrlp(mp, INT_MASK, 0x00000000);
2517 	rdlp(mp, INT_MASK);
2518 
2519 	napi_disable(&mp->napi);
2520 
2521 	del_timer_sync(&mp->rx_oom);
2522 
2523 	netif_carrier_off(dev);
2524 	if (dev->phydev)
2525 		phy_stop(dev->phydev);
2526 	free_irq(dev->irq, dev);
2527 
2528 	port_reset(mp);
2529 	mv643xx_eth_get_stats(dev);
2530 	mib_counters_update(mp);
2531 	del_timer_sync(&mp->mib_counters_timer);
2532 
2533 	for (i = 0; i < mp->rxq_count; i++)
2534 		rxq_deinit(mp->rxq + i);
2535 	for (i = 0; i < mp->txq_count; i++)
2536 		txq_deinit(mp->txq + i);
2537 
2538 	return 0;
2539 }
2540 
2541 static int mv643xx_eth_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2542 {
2543 	int ret;
2544 
2545 	if (!dev->phydev)
2546 		return -ENOTSUPP;
2547 
2548 	ret = phy_mii_ioctl(dev->phydev, ifr, cmd);
2549 	if (!ret)
2550 		mv643xx_eth_adjust_link(dev);
2551 	return ret;
2552 }
2553 
2554 static int mv643xx_eth_change_mtu(struct net_device *dev, int new_mtu)
2555 {
2556 	struct mv643xx_eth_private *mp = netdev_priv(dev);
2557 
2558 	dev->mtu = new_mtu;
2559 	mv643xx_eth_recalc_skb_size(mp);
2560 	tx_set_rate(mp, 1000000000, 16777216);
2561 
2562 	if (!netif_running(dev))
2563 		return 0;
2564 
2565 	/*
2566 	 * Stop and then re-open the interface. This will allocate RX
2567 	 * skbs of the new MTU.
2568 	 * There is a possible danger that the open will not succeed,
2569 	 * due to memory being full.
2570 	 */
2571 	mv643xx_eth_stop(dev);
2572 	if (mv643xx_eth_open(dev)) {
2573 		netdev_err(dev,
2574 			   "fatal error on re-opening device after MTU change\n");
2575 	}
2576 
2577 	return 0;
2578 }
2579 
2580 static void tx_timeout_task(struct work_struct *ugly)
2581 {
2582 	struct mv643xx_eth_private *mp;
2583 
2584 	mp = container_of(ugly, struct mv643xx_eth_private, tx_timeout_task);
2585 	if (netif_running(mp->dev)) {
2586 		netif_tx_stop_all_queues(mp->dev);
2587 		port_reset(mp);
2588 		port_start(mp);
2589 		netif_tx_wake_all_queues(mp->dev);
2590 	}
2591 }
2592 
2593 static void mv643xx_eth_tx_timeout(struct net_device *dev, unsigned int txqueue)
2594 {
2595 	struct mv643xx_eth_private *mp = netdev_priv(dev);
2596 
2597 	netdev_info(dev, "tx timeout\n");
2598 
2599 	schedule_work(&mp->tx_timeout_task);
2600 }
2601 
2602 #ifdef CONFIG_NET_POLL_CONTROLLER
2603 static void mv643xx_eth_netpoll(struct net_device *dev)
2604 {
2605 	struct mv643xx_eth_private *mp = netdev_priv(dev);
2606 
2607 	wrlp(mp, INT_MASK, 0x00000000);
2608 	rdlp(mp, INT_MASK);
2609 
2610 	mv643xx_eth_irq(dev->irq, dev);
2611 
2612 	wrlp(mp, INT_MASK, mp->int_mask);
2613 }
2614 #endif
2615 
2616 
2617 /* platform glue ************************************************************/
2618 static void
2619 mv643xx_eth_conf_mbus_windows(struct mv643xx_eth_shared_private *msp,
2620 			      const struct mbus_dram_target_info *dram)
2621 {
2622 	void __iomem *base = msp->base;
2623 	u32 win_enable;
2624 	u32 win_protect;
2625 	int i;
2626 
2627 	for (i = 0; i < 6; i++) {
2628 		writel(0, base + WINDOW_BASE(i));
2629 		writel(0, base + WINDOW_SIZE(i));
2630 		if (i < 4)
2631 			writel(0, base + WINDOW_REMAP_HIGH(i));
2632 	}
2633 
2634 	win_enable = 0x3f;
2635 	win_protect = 0;
2636 
2637 	for (i = 0; i < dram->num_cs; i++) {
2638 		const struct mbus_dram_window *cs = dram->cs + i;
2639 
2640 		writel((cs->base & 0xffff0000) |
2641 			(cs->mbus_attr << 8) |
2642 			dram->mbus_dram_target_id, base + WINDOW_BASE(i));
2643 		writel((cs->size - 1) & 0xffff0000, base + WINDOW_SIZE(i));
2644 
2645 		win_enable &= ~(1 << i);
2646 		win_protect |= 3 << (2 * i);
2647 	}
2648 
2649 	writel(win_enable, base + WINDOW_BAR_ENABLE);
2650 	msp->win_protect = win_protect;
2651 }
2652 
2653 static void infer_hw_params(struct mv643xx_eth_shared_private *msp)
2654 {
2655 	/*
2656 	 * Check whether we have a 14-bit coal limit field in bits
2657 	 * [21:8], or a 16-bit coal limit in bits [25,21:7] of the
2658 	 * SDMA config register.
2659 	 */
2660 	writel(0x02000000, msp->base + 0x0400 + SDMA_CONFIG);
2661 	if (readl(msp->base + 0x0400 + SDMA_CONFIG) & 0x02000000)
2662 		msp->extended_rx_coal_limit = 1;
2663 	else
2664 		msp->extended_rx_coal_limit = 0;
2665 
2666 	/*
2667 	 * Check whether the MAC supports TX rate control, and if
2668 	 * yes, whether its associated registers are in the old or
2669 	 * the new place.
2670 	 */
2671 	writel(1, msp->base + 0x0400 + TX_BW_MTU_MOVED);
2672 	if (readl(msp->base + 0x0400 + TX_BW_MTU_MOVED) & 1) {
2673 		msp->tx_bw_control = TX_BW_CONTROL_NEW_LAYOUT;
2674 	} else {
2675 		writel(7, msp->base + 0x0400 + TX_BW_RATE);
2676 		if (readl(msp->base + 0x0400 + TX_BW_RATE) & 7)
2677 			msp->tx_bw_control = TX_BW_CONTROL_OLD_LAYOUT;
2678 		else
2679 			msp->tx_bw_control = TX_BW_CONTROL_ABSENT;
2680 	}
2681 }
2682 
2683 #if defined(CONFIG_OF)
2684 static const struct of_device_id mv643xx_eth_shared_ids[] = {
2685 	{ .compatible = "marvell,orion-eth", },
2686 	{ .compatible = "marvell,kirkwood-eth", },
2687 	{ }
2688 };
2689 MODULE_DEVICE_TABLE(of, mv643xx_eth_shared_ids);
2690 #endif
2691 
2692 #if defined(CONFIG_OF_IRQ) && !defined(CONFIG_MV64X60)
2693 #define mv643xx_eth_property(_np, _name, _v)				\
2694 	do {								\
2695 		u32 tmp;						\
2696 		if (!of_property_read_u32(_np, "marvell," _name, &tmp))	\
2697 			_v = tmp;					\
2698 	} while (0)
2699 
2700 static struct platform_device *port_platdev[3];
2701 
2702 static int mv643xx_eth_shared_of_add_port(struct platform_device *pdev,
2703 					  struct device_node *pnp)
2704 {
2705 	struct platform_device *ppdev;
2706 	struct mv643xx_eth_platform_data ppd;
2707 	struct resource res;
2708 	const char *mac_addr;
2709 	int ret;
2710 	int dev_num = 0;
2711 
2712 	memset(&ppd, 0, sizeof(ppd));
2713 	ppd.shared = pdev;
2714 
2715 	memset(&res, 0, sizeof(res));
2716 	if (of_irq_to_resource(pnp, 0, &res) <= 0) {
2717 		dev_err(&pdev->dev, "missing interrupt on %pOFn\n", pnp);
2718 		return -EINVAL;
2719 	}
2720 
2721 	if (of_property_read_u32(pnp, "reg", &ppd.port_number)) {
2722 		dev_err(&pdev->dev, "missing reg property on %pOFn\n", pnp);
2723 		return -EINVAL;
2724 	}
2725 
2726 	if (ppd.port_number >= 3) {
2727 		dev_err(&pdev->dev, "invalid reg property on %pOFn\n", pnp);
2728 		return -EINVAL;
2729 	}
2730 
2731 	while (dev_num < 3 && port_platdev[dev_num])
2732 		dev_num++;
2733 
2734 	if (dev_num == 3) {
2735 		dev_err(&pdev->dev, "too many ports registered\n");
2736 		return -EINVAL;
2737 	}
2738 
2739 	mac_addr = of_get_mac_address(pnp);
2740 	if (!IS_ERR(mac_addr))
2741 		ether_addr_copy(ppd.mac_addr, mac_addr);
2742 
2743 	mv643xx_eth_property(pnp, "tx-queue-size", ppd.tx_queue_size);
2744 	mv643xx_eth_property(pnp, "tx-sram-addr", ppd.tx_sram_addr);
2745 	mv643xx_eth_property(pnp, "tx-sram-size", ppd.tx_sram_size);
2746 	mv643xx_eth_property(pnp, "rx-queue-size", ppd.rx_queue_size);
2747 	mv643xx_eth_property(pnp, "rx-sram-addr", ppd.rx_sram_addr);
2748 	mv643xx_eth_property(pnp, "rx-sram-size", ppd.rx_sram_size);
2749 
2750 	ppd.phy_node = of_parse_phandle(pnp, "phy-handle", 0);
2751 	if (!ppd.phy_node) {
2752 		ppd.phy_addr = MV643XX_ETH_PHY_NONE;
2753 		of_property_read_u32(pnp, "speed", &ppd.speed);
2754 		of_property_read_u32(pnp, "duplex", &ppd.duplex);
2755 	}
2756 
2757 	ppdev = platform_device_alloc(MV643XX_ETH_NAME, dev_num);
2758 	if (!ppdev)
2759 		return -ENOMEM;
2760 	ppdev->dev.coherent_dma_mask = DMA_BIT_MASK(32);
2761 	ppdev->dev.of_node = pnp;
2762 
2763 	ret = platform_device_add_resources(ppdev, &res, 1);
2764 	if (ret)
2765 		goto port_err;
2766 
2767 	ret = platform_device_add_data(ppdev, &ppd, sizeof(ppd));
2768 	if (ret)
2769 		goto port_err;
2770 
2771 	ret = platform_device_add(ppdev);
2772 	if (ret)
2773 		goto port_err;
2774 
2775 	port_platdev[dev_num] = ppdev;
2776 
2777 	return 0;
2778 
2779 port_err:
2780 	platform_device_put(ppdev);
2781 	return ret;
2782 }
2783 
2784 static int mv643xx_eth_shared_of_probe(struct platform_device *pdev)
2785 {
2786 	struct mv643xx_eth_shared_platform_data *pd;
2787 	struct device_node *pnp, *np = pdev->dev.of_node;
2788 	int ret;
2789 
2790 	/* bail out if not registered from DT */
2791 	if (!np)
2792 		return 0;
2793 
2794 	pd = devm_kzalloc(&pdev->dev, sizeof(*pd), GFP_KERNEL);
2795 	if (!pd)
2796 		return -ENOMEM;
2797 	pdev->dev.platform_data = pd;
2798 
2799 	mv643xx_eth_property(np, "tx-checksum-limit", pd->tx_csum_limit);
2800 
2801 	for_each_available_child_of_node(np, pnp) {
2802 		ret = mv643xx_eth_shared_of_add_port(pdev, pnp);
2803 		if (ret) {
2804 			of_node_put(pnp);
2805 			return ret;
2806 		}
2807 	}
2808 	return 0;
2809 }
2810 
2811 static void mv643xx_eth_shared_of_remove(void)
2812 {
2813 	int n;
2814 
2815 	for (n = 0; n < 3; n++) {
2816 		platform_device_del(port_platdev[n]);
2817 		port_platdev[n] = NULL;
2818 	}
2819 }
2820 #else
2821 static inline int mv643xx_eth_shared_of_probe(struct platform_device *pdev)
2822 {
2823 	return 0;
2824 }
2825 
2826 static inline void mv643xx_eth_shared_of_remove(void)
2827 {
2828 }
2829 #endif
2830 
2831 static int mv643xx_eth_shared_probe(struct platform_device *pdev)
2832 {
2833 	static int mv643xx_eth_version_printed;
2834 	struct mv643xx_eth_shared_platform_data *pd;
2835 	struct mv643xx_eth_shared_private *msp;
2836 	const struct mbus_dram_target_info *dram;
2837 	struct resource *res;
2838 	int ret;
2839 
2840 	if (!mv643xx_eth_version_printed++)
2841 		pr_notice("MV-643xx 10/100/1000 ethernet driver version %s\n",
2842 			  mv643xx_eth_driver_version);
2843 
2844 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2845 	if (res == NULL)
2846 		return -EINVAL;
2847 
2848 	msp = devm_kzalloc(&pdev->dev, sizeof(*msp), GFP_KERNEL);
2849 	if (msp == NULL)
2850 		return -ENOMEM;
2851 	platform_set_drvdata(pdev, msp);
2852 
2853 	msp->base = devm_ioremap(&pdev->dev, res->start, resource_size(res));
2854 	if (msp->base == NULL)
2855 		return -ENOMEM;
2856 
2857 	msp->clk = devm_clk_get(&pdev->dev, NULL);
2858 	if (!IS_ERR(msp->clk))
2859 		clk_prepare_enable(msp->clk);
2860 
2861 	/*
2862 	 * (Re-)program MBUS remapping windows if we are asked to.
2863 	 */
2864 	dram = mv_mbus_dram_info();
2865 	if (dram)
2866 		mv643xx_eth_conf_mbus_windows(msp, dram);
2867 
2868 	ret = mv643xx_eth_shared_of_probe(pdev);
2869 	if (ret)
2870 		goto err_put_clk;
2871 	pd = dev_get_platdata(&pdev->dev);
2872 
2873 	msp->tx_csum_limit = (pd != NULL && pd->tx_csum_limit) ?
2874 					pd->tx_csum_limit : 9 * 1024;
2875 	infer_hw_params(msp);
2876 
2877 	return 0;
2878 
2879 err_put_clk:
2880 	if (!IS_ERR(msp->clk))
2881 		clk_disable_unprepare(msp->clk);
2882 	return ret;
2883 }
2884 
2885 static int mv643xx_eth_shared_remove(struct platform_device *pdev)
2886 {
2887 	struct mv643xx_eth_shared_private *msp = platform_get_drvdata(pdev);
2888 
2889 	mv643xx_eth_shared_of_remove();
2890 	if (!IS_ERR(msp->clk))
2891 		clk_disable_unprepare(msp->clk);
2892 	return 0;
2893 }
2894 
2895 static struct platform_driver mv643xx_eth_shared_driver = {
2896 	.probe		= mv643xx_eth_shared_probe,
2897 	.remove		= mv643xx_eth_shared_remove,
2898 	.driver = {
2899 		.name	= MV643XX_ETH_SHARED_NAME,
2900 		.of_match_table = of_match_ptr(mv643xx_eth_shared_ids),
2901 	},
2902 };
2903 
2904 static void phy_addr_set(struct mv643xx_eth_private *mp, int phy_addr)
2905 {
2906 	int addr_shift = 5 * mp->port_num;
2907 	u32 data;
2908 
2909 	data = rdl(mp, PHY_ADDR);
2910 	data &= ~(0x1f << addr_shift);
2911 	data |= (phy_addr & 0x1f) << addr_shift;
2912 	wrl(mp, PHY_ADDR, data);
2913 }
2914 
2915 static int phy_addr_get(struct mv643xx_eth_private *mp)
2916 {
2917 	unsigned int data;
2918 
2919 	data = rdl(mp, PHY_ADDR);
2920 
2921 	return (data >> (5 * mp->port_num)) & 0x1f;
2922 }
2923 
2924 static void set_params(struct mv643xx_eth_private *mp,
2925 		       struct mv643xx_eth_platform_data *pd)
2926 {
2927 	struct net_device *dev = mp->dev;
2928 	unsigned int tx_ring_size;
2929 
2930 	if (is_valid_ether_addr(pd->mac_addr))
2931 		memcpy(dev->dev_addr, pd->mac_addr, ETH_ALEN);
2932 	else
2933 		uc_addr_get(mp, dev->dev_addr);
2934 
2935 	mp->rx_ring_size = DEFAULT_RX_QUEUE_SIZE;
2936 	if (pd->rx_queue_size)
2937 		mp->rx_ring_size = pd->rx_queue_size;
2938 	mp->rx_desc_sram_addr = pd->rx_sram_addr;
2939 	mp->rx_desc_sram_size = pd->rx_sram_size;
2940 
2941 	mp->rxq_count = pd->rx_queue_count ? : 1;
2942 
2943 	tx_ring_size = DEFAULT_TX_QUEUE_SIZE;
2944 	if (pd->tx_queue_size)
2945 		tx_ring_size = pd->tx_queue_size;
2946 
2947 	mp->tx_ring_size = clamp_t(unsigned int, tx_ring_size,
2948 				   MV643XX_MAX_SKB_DESCS * 2, 4096);
2949 	if (mp->tx_ring_size != tx_ring_size)
2950 		netdev_warn(dev, "TX queue size set to %u (requested %u)\n",
2951 			    mp->tx_ring_size, tx_ring_size);
2952 
2953 	mp->tx_desc_sram_addr = pd->tx_sram_addr;
2954 	mp->tx_desc_sram_size = pd->tx_sram_size;
2955 
2956 	mp->txq_count = pd->tx_queue_count ? : 1;
2957 }
2958 
2959 static int get_phy_mode(struct mv643xx_eth_private *mp)
2960 {
2961 	struct device *dev = mp->dev->dev.parent;
2962 	phy_interface_t iface;
2963 	int err;
2964 
2965 	if (dev->of_node)
2966 		err = of_get_phy_mode(dev->of_node, &iface);
2967 
2968 	/* Historical default if unspecified. We could also read/write
2969 	 * the interface state in the PSC1
2970 	 */
2971 	if (!dev->of_node || err)
2972 		iface = PHY_INTERFACE_MODE_GMII;
2973 	return iface;
2974 }
2975 
2976 static struct phy_device *phy_scan(struct mv643xx_eth_private *mp,
2977 				   int phy_addr)
2978 {
2979 	struct phy_device *phydev;
2980 	int start;
2981 	int num;
2982 	int i;
2983 	char phy_id[MII_BUS_ID_SIZE + 3];
2984 
2985 	if (phy_addr == MV643XX_ETH_PHY_ADDR_DEFAULT) {
2986 		start = phy_addr_get(mp) & 0x1f;
2987 		num = 32;
2988 	} else {
2989 		start = phy_addr & 0x1f;
2990 		num = 1;
2991 	}
2992 
2993 	/* Attempt to connect to the PHY using orion-mdio */
2994 	phydev = ERR_PTR(-ENODEV);
2995 	for (i = 0; i < num; i++) {
2996 		int addr = (start + i) & 0x1f;
2997 
2998 		snprintf(phy_id, sizeof(phy_id), PHY_ID_FMT,
2999 				"orion-mdio-mii", addr);
3000 
3001 		phydev = phy_connect(mp->dev, phy_id, mv643xx_eth_adjust_link,
3002 				     get_phy_mode(mp));
3003 		if (!IS_ERR(phydev)) {
3004 			phy_addr_set(mp, addr);
3005 			break;
3006 		}
3007 	}
3008 
3009 	return phydev;
3010 }
3011 
3012 static void phy_init(struct mv643xx_eth_private *mp, int speed, int duplex)
3013 {
3014 	struct net_device *dev = mp->dev;
3015 	struct phy_device *phy = dev->phydev;
3016 
3017 	if (speed == 0) {
3018 		phy->autoneg = AUTONEG_ENABLE;
3019 		phy->speed = 0;
3020 		phy->duplex = 0;
3021 		linkmode_copy(phy->advertising, phy->supported);
3022 		linkmode_set_bit(ETHTOOL_LINK_MODE_Autoneg_BIT,
3023 				 phy->advertising);
3024 	} else {
3025 		phy->autoneg = AUTONEG_DISABLE;
3026 		linkmode_zero(phy->advertising);
3027 		phy->speed = speed;
3028 		phy->duplex = duplex;
3029 	}
3030 	phy_start_aneg(phy);
3031 }
3032 
3033 static void init_pscr(struct mv643xx_eth_private *mp, int speed, int duplex)
3034 {
3035 	struct net_device *dev = mp->dev;
3036 	u32 pscr;
3037 
3038 	pscr = rdlp(mp, PORT_SERIAL_CONTROL);
3039 	if (pscr & SERIAL_PORT_ENABLE) {
3040 		pscr &= ~SERIAL_PORT_ENABLE;
3041 		wrlp(mp, PORT_SERIAL_CONTROL, pscr);
3042 	}
3043 
3044 	pscr = MAX_RX_PACKET_9700BYTE | SERIAL_PORT_CONTROL_RESERVED;
3045 	if (!dev->phydev) {
3046 		pscr |= DISABLE_AUTO_NEG_SPEED_GMII;
3047 		if (speed == SPEED_1000)
3048 			pscr |= SET_GMII_SPEED_TO_1000;
3049 		else if (speed == SPEED_100)
3050 			pscr |= SET_MII_SPEED_TO_100;
3051 
3052 		pscr |= DISABLE_AUTO_NEG_FOR_FLOW_CTRL;
3053 
3054 		pscr |= DISABLE_AUTO_NEG_FOR_DUPLEX;
3055 		if (duplex == DUPLEX_FULL)
3056 			pscr |= SET_FULL_DUPLEX_MODE;
3057 	}
3058 
3059 	wrlp(mp, PORT_SERIAL_CONTROL, pscr);
3060 }
3061 
3062 static const struct net_device_ops mv643xx_eth_netdev_ops = {
3063 	.ndo_open		= mv643xx_eth_open,
3064 	.ndo_stop		= mv643xx_eth_stop,
3065 	.ndo_start_xmit		= mv643xx_eth_xmit,
3066 	.ndo_set_rx_mode	= mv643xx_eth_set_rx_mode,
3067 	.ndo_set_mac_address	= mv643xx_eth_set_mac_address,
3068 	.ndo_validate_addr	= eth_validate_addr,
3069 	.ndo_do_ioctl		= mv643xx_eth_ioctl,
3070 	.ndo_change_mtu		= mv643xx_eth_change_mtu,
3071 	.ndo_set_features	= mv643xx_eth_set_features,
3072 	.ndo_tx_timeout		= mv643xx_eth_tx_timeout,
3073 	.ndo_get_stats		= mv643xx_eth_get_stats,
3074 #ifdef CONFIG_NET_POLL_CONTROLLER
3075 	.ndo_poll_controller	= mv643xx_eth_netpoll,
3076 #endif
3077 };
3078 
3079 static int mv643xx_eth_probe(struct platform_device *pdev)
3080 {
3081 	struct mv643xx_eth_platform_data *pd;
3082 	struct mv643xx_eth_private *mp;
3083 	struct net_device *dev;
3084 	struct phy_device *phydev = NULL;
3085 	struct resource *res;
3086 	int err;
3087 
3088 	pd = dev_get_platdata(&pdev->dev);
3089 	if (pd == NULL) {
3090 		dev_err(&pdev->dev, "no mv643xx_eth_platform_data\n");
3091 		return -ENODEV;
3092 	}
3093 
3094 	if (pd->shared == NULL) {
3095 		dev_err(&pdev->dev, "no mv643xx_eth_platform_data->shared\n");
3096 		return -ENODEV;
3097 	}
3098 
3099 	dev = alloc_etherdev_mq(sizeof(struct mv643xx_eth_private), 8);
3100 	if (!dev)
3101 		return -ENOMEM;
3102 
3103 	SET_NETDEV_DEV(dev, &pdev->dev);
3104 	mp = netdev_priv(dev);
3105 	platform_set_drvdata(pdev, mp);
3106 
3107 	mp->shared = platform_get_drvdata(pd->shared);
3108 	mp->base = mp->shared->base + 0x0400 + (pd->port_number << 10);
3109 	mp->port_num = pd->port_number;
3110 
3111 	mp->dev = dev;
3112 
3113 	/* Kirkwood resets some registers on gated clocks. Especially
3114 	 * CLK125_BYPASS_EN must be cleared but is not available on
3115 	 * all other SoCs/System Controllers using this driver.
3116 	 */
3117 	if (of_device_is_compatible(pdev->dev.of_node,
3118 				    "marvell,kirkwood-eth-port"))
3119 		wrlp(mp, PORT_SERIAL_CONTROL1,
3120 		     rdlp(mp, PORT_SERIAL_CONTROL1) & ~CLK125_BYPASS_EN);
3121 
3122 	/*
3123 	 * Start with a default rate, and if there is a clock, allow
3124 	 * it to override the default.
3125 	 */
3126 	mp->t_clk = 133000000;
3127 	mp->clk = devm_clk_get(&pdev->dev, NULL);
3128 	if (!IS_ERR(mp->clk)) {
3129 		clk_prepare_enable(mp->clk);
3130 		mp->t_clk = clk_get_rate(mp->clk);
3131 	} else if (!IS_ERR(mp->shared->clk)) {
3132 		mp->t_clk = clk_get_rate(mp->shared->clk);
3133 	}
3134 
3135 	set_params(mp, pd);
3136 	netif_set_real_num_tx_queues(dev, mp->txq_count);
3137 	netif_set_real_num_rx_queues(dev, mp->rxq_count);
3138 
3139 	err = 0;
3140 	if (pd->phy_node) {
3141 		phydev = of_phy_connect(mp->dev, pd->phy_node,
3142 					mv643xx_eth_adjust_link, 0,
3143 					get_phy_mode(mp));
3144 		if (!phydev)
3145 			err = -ENODEV;
3146 		else
3147 			phy_addr_set(mp, phydev->mdio.addr);
3148 	} else if (pd->phy_addr != MV643XX_ETH_PHY_NONE) {
3149 		phydev = phy_scan(mp, pd->phy_addr);
3150 
3151 		if (IS_ERR(phydev))
3152 			err = PTR_ERR(phydev);
3153 		else
3154 			phy_init(mp, pd->speed, pd->duplex);
3155 	}
3156 	if (err == -ENODEV) {
3157 		err = -EPROBE_DEFER;
3158 		goto out;
3159 	}
3160 	if (err)
3161 		goto out;
3162 
3163 	dev->ethtool_ops = &mv643xx_eth_ethtool_ops;
3164 
3165 	init_pscr(mp, pd->speed, pd->duplex);
3166 
3167 
3168 	mib_counters_clear(mp);
3169 
3170 	timer_setup(&mp->mib_counters_timer, mib_counters_timer_wrapper, 0);
3171 	mp->mib_counters_timer.expires = jiffies + 30 * HZ;
3172 
3173 	spin_lock_init(&mp->mib_counters_lock);
3174 
3175 	INIT_WORK(&mp->tx_timeout_task, tx_timeout_task);
3176 
3177 	netif_napi_add(dev, &mp->napi, mv643xx_eth_poll, NAPI_POLL_WEIGHT);
3178 
3179 	timer_setup(&mp->rx_oom, oom_timer_wrapper, 0);
3180 
3181 
3182 	res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
3183 	BUG_ON(!res);
3184 	dev->irq = res->start;
3185 
3186 	dev->netdev_ops = &mv643xx_eth_netdev_ops;
3187 
3188 	dev->watchdog_timeo = 2 * HZ;
3189 	dev->base_addr = 0;
3190 
3191 	dev->features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO;
3192 	dev->vlan_features = dev->features;
3193 
3194 	dev->features |= NETIF_F_RXCSUM;
3195 	dev->hw_features = dev->features;
3196 
3197 	dev->priv_flags |= IFF_UNICAST_FLT;
3198 	dev->gso_max_segs = MV643XX_MAX_TSO_SEGS;
3199 
3200 	/* MTU range: 64 - 9500 */
3201 	dev->min_mtu = 64;
3202 	dev->max_mtu = 9500;
3203 
3204 	if (mp->shared->win_protect)
3205 		wrl(mp, WINDOW_PROTECT(mp->port_num), mp->shared->win_protect);
3206 
3207 	netif_carrier_off(dev);
3208 
3209 	wrlp(mp, SDMA_CONFIG, PORT_SDMA_CONFIG_DEFAULT_VALUE);
3210 
3211 	set_rx_coal(mp, 250);
3212 	set_tx_coal(mp, 0);
3213 
3214 	err = register_netdev(dev);
3215 	if (err)
3216 		goto out;
3217 
3218 	netdev_notice(dev, "port %d with MAC address %pM\n",
3219 		      mp->port_num, dev->dev_addr);
3220 
3221 	if (mp->tx_desc_sram_size > 0)
3222 		netdev_notice(dev, "configured with sram\n");
3223 
3224 	return 0;
3225 
3226 out:
3227 	if (!IS_ERR(mp->clk))
3228 		clk_disable_unprepare(mp->clk);
3229 	free_netdev(dev);
3230 
3231 	return err;
3232 }
3233 
3234 static int mv643xx_eth_remove(struct platform_device *pdev)
3235 {
3236 	struct mv643xx_eth_private *mp = platform_get_drvdata(pdev);
3237 	struct net_device *dev = mp->dev;
3238 
3239 	unregister_netdev(mp->dev);
3240 	if (dev->phydev)
3241 		phy_disconnect(dev->phydev);
3242 	cancel_work_sync(&mp->tx_timeout_task);
3243 
3244 	if (!IS_ERR(mp->clk))
3245 		clk_disable_unprepare(mp->clk);
3246 
3247 	free_netdev(mp->dev);
3248 
3249 	return 0;
3250 }
3251 
3252 static void mv643xx_eth_shutdown(struct platform_device *pdev)
3253 {
3254 	struct mv643xx_eth_private *mp = platform_get_drvdata(pdev);
3255 
3256 	/* Mask all interrupts on ethernet port */
3257 	wrlp(mp, INT_MASK, 0);
3258 	rdlp(mp, INT_MASK);
3259 
3260 	if (netif_running(mp->dev))
3261 		port_reset(mp);
3262 }
3263 
3264 static struct platform_driver mv643xx_eth_driver = {
3265 	.probe		= mv643xx_eth_probe,
3266 	.remove		= mv643xx_eth_remove,
3267 	.shutdown	= mv643xx_eth_shutdown,
3268 	.driver = {
3269 		.name	= MV643XX_ETH_NAME,
3270 	},
3271 };
3272 
3273 static struct platform_driver * const drivers[] = {
3274 	&mv643xx_eth_shared_driver,
3275 	&mv643xx_eth_driver,
3276 };
3277 
3278 static int __init mv643xx_eth_init_module(void)
3279 {
3280 	return platform_register_drivers(drivers, ARRAY_SIZE(drivers));
3281 }
3282 module_init(mv643xx_eth_init_module);
3283 
3284 static void __exit mv643xx_eth_cleanup_module(void)
3285 {
3286 	platform_unregister_drivers(drivers, ARRAY_SIZE(drivers));
3287 }
3288 module_exit(mv643xx_eth_cleanup_module);
3289 
3290 MODULE_AUTHOR("Rabeeh Khoury, Assaf Hoffman, Matthew Dharm, "
3291 	      "Manish Lachwani, Dale Farnsworth and Lennert Buytenhek");
3292 MODULE_DESCRIPTION("Ethernet driver for Marvell MV643XX");
3293 MODULE_LICENSE("GPL");
3294 MODULE_ALIAS("platform:" MV643XX_ETH_SHARED_NAME);
3295 MODULE_ALIAS("platform:" MV643XX_ETH_NAME);
3296