1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Driver for Marvell Discovery (MV643XX) and Marvell Orion ethernet ports 4 * Copyright (C) 2002 Matthew Dharm <mdharm@momenco.com> 5 * 6 * Based on the 64360 driver from: 7 * Copyright (C) 2002 Rabeeh Khoury <rabeeh@galileo.co.il> 8 * Rabeeh Khoury <rabeeh@marvell.com> 9 * 10 * Copyright (C) 2003 PMC-Sierra, Inc., 11 * written by Manish Lachwani 12 * 13 * Copyright (C) 2003 Ralf Baechle <ralf@linux-mips.org> 14 * 15 * Copyright (C) 2004-2006 MontaVista Software, Inc. 16 * Dale Farnsworth <dale@farnsworth.org> 17 * 18 * Copyright (C) 2004 Steven J. Hill <sjhill1@rockwellcollins.com> 19 * <sjhill@realitydiluted.com> 20 * 21 * Copyright (C) 2007-2008 Marvell Semiconductor 22 * Lennert Buytenhek <buytenh@marvell.com> 23 * 24 * Copyright (C) 2013 Michael Stapelberg <michael@stapelberg.de> 25 */ 26 27 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 28 29 #include <linux/init.h> 30 #include <linux/dma-mapping.h> 31 #include <linux/in.h> 32 #include <linux/ip.h> 33 #include <net/tso.h> 34 #include <linux/tcp.h> 35 #include <linux/udp.h> 36 #include <linux/etherdevice.h> 37 #include <linux/delay.h> 38 #include <linux/ethtool.h> 39 #include <linux/platform_device.h> 40 #include <linux/module.h> 41 #include <linux/kernel.h> 42 #include <linux/spinlock.h> 43 #include <linux/workqueue.h> 44 #include <linux/phy.h> 45 #include <linux/mv643xx_eth.h> 46 #include <linux/io.h> 47 #include <linux/interrupt.h> 48 #include <linux/types.h> 49 #include <linux/slab.h> 50 #include <linux/clk.h> 51 #include <linux/of.h> 52 #include <linux/of_irq.h> 53 #include <linux/of_net.h> 54 #include <linux/of_mdio.h> 55 56 static char mv643xx_eth_driver_name[] = "mv643xx_eth"; 57 static char mv643xx_eth_driver_version[] = "1.4"; 58 59 60 /* 61 * Registers shared between all ports. 62 */ 63 #define PHY_ADDR 0x0000 64 #define WINDOW_BASE(w) (0x0200 + ((w) << 3)) 65 #define WINDOW_SIZE(w) (0x0204 + ((w) << 3)) 66 #define WINDOW_REMAP_HIGH(w) (0x0280 + ((w) << 2)) 67 #define WINDOW_BAR_ENABLE 0x0290 68 #define WINDOW_PROTECT(w) (0x0294 + ((w) << 4)) 69 70 /* 71 * Main per-port registers. These live at offset 0x0400 for 72 * port #0, 0x0800 for port #1, and 0x0c00 for port #2. 73 */ 74 #define PORT_CONFIG 0x0000 75 #define UNICAST_PROMISCUOUS_MODE 0x00000001 76 #define PORT_CONFIG_EXT 0x0004 77 #define MAC_ADDR_LOW 0x0014 78 #define MAC_ADDR_HIGH 0x0018 79 #define SDMA_CONFIG 0x001c 80 #define TX_BURST_SIZE_16_64BIT 0x01000000 81 #define TX_BURST_SIZE_4_64BIT 0x00800000 82 #define BLM_TX_NO_SWAP 0x00000020 83 #define BLM_RX_NO_SWAP 0x00000010 84 #define RX_BURST_SIZE_16_64BIT 0x00000008 85 #define RX_BURST_SIZE_4_64BIT 0x00000004 86 #define PORT_SERIAL_CONTROL 0x003c 87 #define SET_MII_SPEED_TO_100 0x01000000 88 #define SET_GMII_SPEED_TO_1000 0x00800000 89 #define SET_FULL_DUPLEX_MODE 0x00200000 90 #define MAX_RX_PACKET_9700BYTE 0x000a0000 91 #define DISABLE_AUTO_NEG_SPEED_GMII 0x00002000 92 #define DO_NOT_FORCE_LINK_FAIL 0x00000400 93 #define SERIAL_PORT_CONTROL_RESERVED 0x00000200 94 #define DISABLE_AUTO_NEG_FOR_FLOW_CTRL 0x00000008 95 #define DISABLE_AUTO_NEG_FOR_DUPLEX 0x00000004 96 #define FORCE_LINK_PASS 0x00000002 97 #define SERIAL_PORT_ENABLE 0x00000001 98 #define PORT_STATUS 0x0044 99 #define TX_FIFO_EMPTY 0x00000400 100 #define TX_IN_PROGRESS 0x00000080 101 #define PORT_SPEED_MASK 0x00000030 102 #define PORT_SPEED_1000 0x00000010 103 #define PORT_SPEED_100 0x00000020 104 #define PORT_SPEED_10 0x00000000 105 #define FLOW_CONTROL_ENABLED 0x00000008 106 #define FULL_DUPLEX 0x00000004 107 #define LINK_UP 0x00000002 108 #define TXQ_COMMAND 0x0048 109 #define TXQ_FIX_PRIO_CONF 0x004c 110 #define PORT_SERIAL_CONTROL1 0x004c 111 #define CLK125_BYPASS_EN 0x00000010 112 #define TX_BW_RATE 0x0050 113 #define TX_BW_MTU 0x0058 114 #define TX_BW_BURST 0x005c 115 #define INT_CAUSE 0x0060 116 #define INT_TX_END 0x07f80000 117 #define INT_TX_END_0 0x00080000 118 #define INT_RX 0x000003fc 119 #define INT_RX_0 0x00000004 120 #define INT_EXT 0x00000002 121 #define INT_CAUSE_EXT 0x0064 122 #define INT_EXT_LINK_PHY 0x00110000 123 #define INT_EXT_TX 0x000000ff 124 #define INT_MASK 0x0068 125 #define INT_MASK_EXT 0x006c 126 #define TX_FIFO_URGENT_THRESHOLD 0x0074 127 #define RX_DISCARD_FRAME_CNT 0x0084 128 #define RX_OVERRUN_FRAME_CNT 0x0088 129 #define TXQ_FIX_PRIO_CONF_MOVED 0x00dc 130 #define TX_BW_RATE_MOVED 0x00e0 131 #define TX_BW_MTU_MOVED 0x00e8 132 #define TX_BW_BURST_MOVED 0x00ec 133 #define RXQ_CURRENT_DESC_PTR(q) (0x020c + ((q) << 4)) 134 #define RXQ_COMMAND 0x0280 135 #define TXQ_CURRENT_DESC_PTR(q) (0x02c0 + ((q) << 2)) 136 #define TXQ_BW_TOKENS(q) (0x0300 + ((q) << 4)) 137 #define TXQ_BW_CONF(q) (0x0304 + ((q) << 4)) 138 #define TXQ_BW_WRR_CONF(q) (0x0308 + ((q) << 4)) 139 140 /* 141 * Misc per-port registers. 142 */ 143 #define MIB_COUNTERS(p) (0x1000 + ((p) << 7)) 144 #define SPECIAL_MCAST_TABLE(p) (0x1400 + ((p) << 10)) 145 #define OTHER_MCAST_TABLE(p) (0x1500 + ((p) << 10)) 146 #define UNICAST_TABLE(p) (0x1600 + ((p) << 10)) 147 148 149 /* 150 * SDMA configuration register default value. 151 */ 152 #if defined(__BIG_ENDIAN) 153 #define PORT_SDMA_CONFIG_DEFAULT_VALUE \ 154 (RX_BURST_SIZE_4_64BIT | \ 155 TX_BURST_SIZE_4_64BIT) 156 #elif defined(__LITTLE_ENDIAN) 157 #define PORT_SDMA_CONFIG_DEFAULT_VALUE \ 158 (RX_BURST_SIZE_4_64BIT | \ 159 BLM_RX_NO_SWAP | \ 160 BLM_TX_NO_SWAP | \ 161 TX_BURST_SIZE_4_64BIT) 162 #else 163 #error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined 164 #endif 165 166 167 /* 168 * Misc definitions. 169 */ 170 #define DEFAULT_RX_QUEUE_SIZE 128 171 #define DEFAULT_TX_QUEUE_SIZE 512 172 #define SKB_DMA_REALIGN ((PAGE_SIZE - NET_SKB_PAD) % SMP_CACHE_BYTES) 173 174 /* Max number of allowed TCP segments for software TSO */ 175 #define MV643XX_MAX_TSO_SEGS 100 176 #define MV643XX_MAX_SKB_DESCS (MV643XX_MAX_TSO_SEGS * 2 + MAX_SKB_FRAGS) 177 178 #define IS_TSO_HEADER(txq, addr) \ 179 ((addr >= txq->tso_hdrs_dma) && \ 180 (addr < txq->tso_hdrs_dma + txq->tx_ring_size * TSO_HEADER_SIZE)) 181 182 #define DESC_DMA_MAP_SINGLE 0 183 #define DESC_DMA_MAP_PAGE 1 184 185 /* 186 * RX/TX descriptors. 187 */ 188 #if defined(__BIG_ENDIAN) 189 struct rx_desc { 190 u16 byte_cnt; /* Descriptor buffer byte count */ 191 u16 buf_size; /* Buffer size */ 192 u32 cmd_sts; /* Descriptor command status */ 193 u32 next_desc_ptr; /* Next descriptor pointer */ 194 u32 buf_ptr; /* Descriptor buffer pointer */ 195 }; 196 197 struct tx_desc { 198 u16 byte_cnt; /* buffer byte count */ 199 u16 l4i_chk; /* CPU provided TCP checksum */ 200 u32 cmd_sts; /* Command/status field */ 201 u32 next_desc_ptr; /* Pointer to next descriptor */ 202 u32 buf_ptr; /* pointer to buffer for this descriptor*/ 203 }; 204 #elif defined(__LITTLE_ENDIAN) 205 struct rx_desc { 206 u32 cmd_sts; /* Descriptor command status */ 207 u16 buf_size; /* Buffer size */ 208 u16 byte_cnt; /* Descriptor buffer byte count */ 209 u32 buf_ptr; /* Descriptor buffer pointer */ 210 u32 next_desc_ptr; /* Next descriptor pointer */ 211 }; 212 213 struct tx_desc { 214 u32 cmd_sts; /* Command/status field */ 215 u16 l4i_chk; /* CPU provided TCP checksum */ 216 u16 byte_cnt; /* buffer byte count */ 217 u32 buf_ptr; /* pointer to buffer for this descriptor*/ 218 u32 next_desc_ptr; /* Pointer to next descriptor */ 219 }; 220 #else 221 #error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined 222 #endif 223 224 /* RX & TX descriptor command */ 225 #define BUFFER_OWNED_BY_DMA 0x80000000 226 227 /* RX & TX descriptor status */ 228 #define ERROR_SUMMARY 0x00000001 229 230 /* RX descriptor status */ 231 #define LAYER_4_CHECKSUM_OK 0x40000000 232 #define RX_ENABLE_INTERRUPT 0x20000000 233 #define RX_FIRST_DESC 0x08000000 234 #define RX_LAST_DESC 0x04000000 235 #define RX_IP_HDR_OK 0x02000000 236 #define RX_PKT_IS_IPV4 0x01000000 237 #define RX_PKT_IS_ETHERNETV2 0x00800000 238 #define RX_PKT_LAYER4_TYPE_MASK 0x00600000 239 #define RX_PKT_LAYER4_TYPE_TCP_IPV4 0x00000000 240 #define RX_PKT_IS_VLAN_TAGGED 0x00080000 241 242 /* TX descriptor command */ 243 #define TX_ENABLE_INTERRUPT 0x00800000 244 #define GEN_CRC 0x00400000 245 #define TX_FIRST_DESC 0x00200000 246 #define TX_LAST_DESC 0x00100000 247 #define ZERO_PADDING 0x00080000 248 #define GEN_IP_V4_CHECKSUM 0x00040000 249 #define GEN_TCP_UDP_CHECKSUM 0x00020000 250 #define UDP_FRAME 0x00010000 251 #define MAC_HDR_EXTRA_4_BYTES 0x00008000 252 #define GEN_TCP_UDP_CHK_FULL 0x00000400 253 #define MAC_HDR_EXTRA_8_BYTES 0x00000200 254 255 #define TX_IHL_SHIFT 11 256 257 258 /* global *******************************************************************/ 259 struct mv643xx_eth_shared_private { 260 /* 261 * Ethernet controller base address. 262 */ 263 void __iomem *base; 264 265 /* 266 * Per-port MBUS window access register value. 267 */ 268 u32 win_protect; 269 270 /* 271 * Hardware-specific parameters. 272 */ 273 int extended_rx_coal_limit; 274 int tx_bw_control; 275 int tx_csum_limit; 276 struct clk *clk; 277 }; 278 279 #define TX_BW_CONTROL_ABSENT 0 280 #define TX_BW_CONTROL_OLD_LAYOUT 1 281 #define TX_BW_CONTROL_NEW_LAYOUT 2 282 283 static int mv643xx_eth_open(struct net_device *dev); 284 static int mv643xx_eth_stop(struct net_device *dev); 285 286 287 /* per-port *****************************************************************/ 288 struct mib_counters { 289 u64 good_octets_received; 290 u32 bad_octets_received; 291 u32 internal_mac_transmit_err; 292 u32 good_frames_received; 293 u32 bad_frames_received; 294 u32 broadcast_frames_received; 295 u32 multicast_frames_received; 296 u32 frames_64_octets; 297 u32 frames_65_to_127_octets; 298 u32 frames_128_to_255_octets; 299 u32 frames_256_to_511_octets; 300 u32 frames_512_to_1023_octets; 301 u32 frames_1024_to_max_octets; 302 u64 good_octets_sent; 303 u32 good_frames_sent; 304 u32 excessive_collision; 305 u32 multicast_frames_sent; 306 u32 broadcast_frames_sent; 307 u32 unrec_mac_control_received; 308 u32 fc_sent; 309 u32 good_fc_received; 310 u32 bad_fc_received; 311 u32 undersize_received; 312 u32 fragments_received; 313 u32 oversize_received; 314 u32 jabber_received; 315 u32 mac_receive_error; 316 u32 bad_crc_event; 317 u32 collision; 318 u32 late_collision; 319 /* Non MIB hardware counters */ 320 u32 rx_discard; 321 u32 rx_overrun; 322 }; 323 324 struct rx_queue { 325 int index; 326 327 int rx_ring_size; 328 329 int rx_desc_count; 330 int rx_curr_desc; 331 int rx_used_desc; 332 333 struct rx_desc *rx_desc_area; 334 dma_addr_t rx_desc_dma; 335 int rx_desc_area_size; 336 struct sk_buff **rx_skb; 337 }; 338 339 struct tx_queue { 340 int index; 341 342 int tx_ring_size; 343 344 int tx_desc_count; 345 int tx_curr_desc; 346 int tx_used_desc; 347 348 int tx_stop_threshold; 349 int tx_wake_threshold; 350 351 char *tso_hdrs; 352 dma_addr_t tso_hdrs_dma; 353 354 struct tx_desc *tx_desc_area; 355 char *tx_desc_mapping; /* array to track the type of the dma mapping */ 356 dma_addr_t tx_desc_dma; 357 int tx_desc_area_size; 358 359 struct sk_buff_head tx_skb; 360 361 unsigned long tx_packets; 362 unsigned long tx_bytes; 363 unsigned long tx_dropped; 364 }; 365 366 struct mv643xx_eth_private { 367 struct mv643xx_eth_shared_private *shared; 368 void __iomem *base; 369 int port_num; 370 371 struct net_device *dev; 372 373 struct timer_list mib_counters_timer; 374 spinlock_t mib_counters_lock; 375 struct mib_counters mib_counters; 376 377 struct work_struct tx_timeout_task; 378 379 struct napi_struct napi; 380 u32 int_mask; 381 u8 oom; 382 u8 work_link; 383 u8 work_tx; 384 u8 work_tx_end; 385 u8 work_rx; 386 u8 work_rx_refill; 387 388 int skb_size; 389 390 /* 391 * RX state. 392 */ 393 int rx_ring_size; 394 unsigned long rx_desc_sram_addr; 395 int rx_desc_sram_size; 396 int rxq_count; 397 struct timer_list rx_oom; 398 struct rx_queue rxq[8]; 399 400 /* 401 * TX state. 402 */ 403 int tx_ring_size; 404 unsigned long tx_desc_sram_addr; 405 int tx_desc_sram_size; 406 int txq_count; 407 struct tx_queue txq[8]; 408 409 /* 410 * Hardware-specific parameters. 411 */ 412 struct clk *clk; 413 unsigned int t_clk; 414 }; 415 416 417 /* port register accessors **************************************************/ 418 static inline u32 rdl(struct mv643xx_eth_private *mp, int offset) 419 { 420 return readl(mp->shared->base + offset); 421 } 422 423 static inline u32 rdlp(struct mv643xx_eth_private *mp, int offset) 424 { 425 return readl(mp->base + offset); 426 } 427 428 static inline void wrl(struct mv643xx_eth_private *mp, int offset, u32 data) 429 { 430 writel(data, mp->shared->base + offset); 431 } 432 433 static inline void wrlp(struct mv643xx_eth_private *mp, int offset, u32 data) 434 { 435 writel(data, mp->base + offset); 436 } 437 438 439 /* rxq/txq helper functions *************************************************/ 440 static struct mv643xx_eth_private *rxq_to_mp(struct rx_queue *rxq) 441 { 442 return container_of(rxq, struct mv643xx_eth_private, rxq[rxq->index]); 443 } 444 445 static struct mv643xx_eth_private *txq_to_mp(struct tx_queue *txq) 446 { 447 return container_of(txq, struct mv643xx_eth_private, txq[txq->index]); 448 } 449 450 static void rxq_enable(struct rx_queue *rxq) 451 { 452 struct mv643xx_eth_private *mp = rxq_to_mp(rxq); 453 wrlp(mp, RXQ_COMMAND, 1 << rxq->index); 454 } 455 456 static void rxq_disable(struct rx_queue *rxq) 457 { 458 struct mv643xx_eth_private *mp = rxq_to_mp(rxq); 459 u8 mask = 1 << rxq->index; 460 461 wrlp(mp, RXQ_COMMAND, mask << 8); 462 while (rdlp(mp, RXQ_COMMAND) & mask) 463 udelay(10); 464 } 465 466 static void txq_reset_hw_ptr(struct tx_queue *txq) 467 { 468 struct mv643xx_eth_private *mp = txq_to_mp(txq); 469 u32 addr; 470 471 addr = (u32)txq->tx_desc_dma; 472 addr += txq->tx_curr_desc * sizeof(struct tx_desc); 473 wrlp(mp, TXQ_CURRENT_DESC_PTR(txq->index), addr); 474 } 475 476 static void txq_enable(struct tx_queue *txq) 477 { 478 struct mv643xx_eth_private *mp = txq_to_mp(txq); 479 wrlp(mp, TXQ_COMMAND, 1 << txq->index); 480 } 481 482 static void txq_disable(struct tx_queue *txq) 483 { 484 struct mv643xx_eth_private *mp = txq_to_mp(txq); 485 u8 mask = 1 << txq->index; 486 487 wrlp(mp, TXQ_COMMAND, mask << 8); 488 while (rdlp(mp, TXQ_COMMAND) & mask) 489 udelay(10); 490 } 491 492 static void txq_maybe_wake(struct tx_queue *txq) 493 { 494 struct mv643xx_eth_private *mp = txq_to_mp(txq); 495 struct netdev_queue *nq = netdev_get_tx_queue(mp->dev, txq->index); 496 497 if (netif_tx_queue_stopped(nq)) { 498 __netif_tx_lock(nq, smp_processor_id()); 499 if (txq->tx_desc_count <= txq->tx_wake_threshold) 500 netif_tx_wake_queue(nq); 501 __netif_tx_unlock(nq); 502 } 503 } 504 505 static int rxq_process(struct rx_queue *rxq, int budget) 506 { 507 struct mv643xx_eth_private *mp = rxq_to_mp(rxq); 508 struct net_device_stats *stats = &mp->dev->stats; 509 int rx; 510 511 rx = 0; 512 while (rx < budget && rxq->rx_desc_count) { 513 struct rx_desc *rx_desc; 514 unsigned int cmd_sts; 515 struct sk_buff *skb; 516 u16 byte_cnt; 517 518 rx_desc = &rxq->rx_desc_area[rxq->rx_curr_desc]; 519 520 cmd_sts = rx_desc->cmd_sts; 521 if (cmd_sts & BUFFER_OWNED_BY_DMA) 522 break; 523 rmb(); 524 525 skb = rxq->rx_skb[rxq->rx_curr_desc]; 526 rxq->rx_skb[rxq->rx_curr_desc] = NULL; 527 528 rxq->rx_curr_desc++; 529 if (rxq->rx_curr_desc == rxq->rx_ring_size) 530 rxq->rx_curr_desc = 0; 531 532 dma_unmap_single(mp->dev->dev.parent, rx_desc->buf_ptr, 533 rx_desc->buf_size, DMA_FROM_DEVICE); 534 rxq->rx_desc_count--; 535 rx++; 536 537 mp->work_rx_refill |= 1 << rxq->index; 538 539 byte_cnt = rx_desc->byte_cnt; 540 541 /* 542 * Update statistics. 543 * 544 * Note that the descriptor byte count includes 2 dummy 545 * bytes automatically inserted by the hardware at the 546 * start of the packet (which we don't count), and a 4 547 * byte CRC at the end of the packet (which we do count). 548 */ 549 stats->rx_packets++; 550 stats->rx_bytes += byte_cnt - 2; 551 552 /* 553 * In case we received a packet without first / last bits 554 * on, or the error summary bit is set, the packet needs 555 * to be dropped. 556 */ 557 if ((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC | ERROR_SUMMARY)) 558 != (RX_FIRST_DESC | RX_LAST_DESC)) 559 goto err; 560 561 /* 562 * The -4 is for the CRC in the trailer of the 563 * received packet 564 */ 565 skb_put(skb, byte_cnt - 2 - 4); 566 567 if (cmd_sts & LAYER_4_CHECKSUM_OK) 568 skb->ip_summed = CHECKSUM_UNNECESSARY; 569 skb->protocol = eth_type_trans(skb, mp->dev); 570 571 napi_gro_receive(&mp->napi, skb); 572 573 continue; 574 575 err: 576 stats->rx_dropped++; 577 578 if ((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC)) != 579 (RX_FIRST_DESC | RX_LAST_DESC)) { 580 if (net_ratelimit()) 581 netdev_err(mp->dev, 582 "received packet spanning multiple descriptors\n"); 583 } 584 585 if (cmd_sts & ERROR_SUMMARY) 586 stats->rx_errors++; 587 588 dev_kfree_skb(skb); 589 } 590 591 if (rx < budget) 592 mp->work_rx &= ~(1 << rxq->index); 593 594 return rx; 595 } 596 597 static int rxq_refill(struct rx_queue *rxq, int budget) 598 { 599 struct mv643xx_eth_private *mp = rxq_to_mp(rxq); 600 int refilled; 601 602 refilled = 0; 603 while (refilled < budget && rxq->rx_desc_count < rxq->rx_ring_size) { 604 struct sk_buff *skb; 605 int rx; 606 struct rx_desc *rx_desc; 607 int size; 608 609 skb = netdev_alloc_skb(mp->dev, mp->skb_size); 610 611 if (skb == NULL) { 612 mp->oom = 1; 613 goto oom; 614 } 615 616 if (SKB_DMA_REALIGN) 617 skb_reserve(skb, SKB_DMA_REALIGN); 618 619 refilled++; 620 rxq->rx_desc_count++; 621 622 rx = rxq->rx_used_desc++; 623 if (rxq->rx_used_desc == rxq->rx_ring_size) 624 rxq->rx_used_desc = 0; 625 626 rx_desc = rxq->rx_desc_area + rx; 627 628 size = skb_end_pointer(skb) - skb->data; 629 rx_desc->buf_ptr = dma_map_single(mp->dev->dev.parent, 630 skb->data, size, 631 DMA_FROM_DEVICE); 632 rx_desc->buf_size = size; 633 rxq->rx_skb[rx] = skb; 634 wmb(); 635 rx_desc->cmd_sts = BUFFER_OWNED_BY_DMA | RX_ENABLE_INTERRUPT; 636 wmb(); 637 638 /* 639 * The hardware automatically prepends 2 bytes of 640 * dummy data to each received packet, so that the 641 * IP header ends up 16-byte aligned. 642 */ 643 skb_reserve(skb, 2); 644 } 645 646 if (refilled < budget) 647 mp->work_rx_refill &= ~(1 << rxq->index); 648 649 oom: 650 return refilled; 651 } 652 653 654 /* tx ***********************************************************************/ 655 static inline unsigned int has_tiny_unaligned_frags(struct sk_buff *skb) 656 { 657 int frag; 658 659 for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) { 660 const skb_frag_t *fragp = &skb_shinfo(skb)->frags[frag]; 661 662 if (skb_frag_size(fragp) <= 8 && skb_frag_off(fragp) & 7) 663 return 1; 664 } 665 666 return 0; 667 } 668 669 static int skb_tx_csum(struct mv643xx_eth_private *mp, struct sk_buff *skb, 670 u16 *l4i_chk, u32 *command, int length) 671 { 672 int ret; 673 u32 cmd = 0; 674 675 if (skb->ip_summed == CHECKSUM_PARTIAL) { 676 int hdr_len; 677 int tag_bytes; 678 679 BUG_ON(skb->protocol != htons(ETH_P_IP) && 680 skb->protocol != htons(ETH_P_8021Q)); 681 682 hdr_len = (void *)ip_hdr(skb) - (void *)skb->data; 683 tag_bytes = hdr_len - ETH_HLEN; 684 685 if (length - hdr_len > mp->shared->tx_csum_limit || 686 unlikely(tag_bytes & ~12)) { 687 ret = skb_checksum_help(skb); 688 if (!ret) 689 goto no_csum; 690 return ret; 691 } 692 693 if (tag_bytes & 4) 694 cmd |= MAC_HDR_EXTRA_4_BYTES; 695 if (tag_bytes & 8) 696 cmd |= MAC_HDR_EXTRA_8_BYTES; 697 698 cmd |= GEN_TCP_UDP_CHECKSUM | GEN_TCP_UDP_CHK_FULL | 699 GEN_IP_V4_CHECKSUM | 700 ip_hdr(skb)->ihl << TX_IHL_SHIFT; 701 702 /* TODO: Revisit this. With the usage of GEN_TCP_UDP_CHK_FULL 703 * it seems we don't need to pass the initial checksum. */ 704 switch (ip_hdr(skb)->protocol) { 705 case IPPROTO_UDP: 706 cmd |= UDP_FRAME; 707 *l4i_chk = 0; 708 break; 709 case IPPROTO_TCP: 710 *l4i_chk = 0; 711 break; 712 default: 713 WARN(1, "protocol not supported"); 714 } 715 } else { 716 no_csum: 717 /* Errata BTS #50, IHL must be 5 if no HW checksum */ 718 cmd |= 5 << TX_IHL_SHIFT; 719 } 720 *command = cmd; 721 return 0; 722 } 723 724 static inline int 725 txq_put_data_tso(struct net_device *dev, struct tx_queue *txq, 726 struct sk_buff *skb, char *data, int length, 727 bool last_tcp, bool is_last) 728 { 729 int tx_index; 730 u32 cmd_sts; 731 struct tx_desc *desc; 732 733 tx_index = txq->tx_curr_desc++; 734 if (txq->tx_curr_desc == txq->tx_ring_size) 735 txq->tx_curr_desc = 0; 736 desc = &txq->tx_desc_area[tx_index]; 737 txq->tx_desc_mapping[tx_index] = DESC_DMA_MAP_SINGLE; 738 739 desc->l4i_chk = 0; 740 desc->byte_cnt = length; 741 742 if (length <= 8 && (uintptr_t)data & 0x7) { 743 /* Copy unaligned small data fragment to TSO header data area */ 744 memcpy(txq->tso_hdrs + tx_index * TSO_HEADER_SIZE, 745 data, length); 746 desc->buf_ptr = txq->tso_hdrs_dma 747 + tx_index * TSO_HEADER_SIZE; 748 } else { 749 /* Alignment is okay, map buffer and hand off to hardware */ 750 txq->tx_desc_mapping[tx_index] = DESC_DMA_MAP_SINGLE; 751 desc->buf_ptr = dma_map_single(dev->dev.parent, data, 752 length, DMA_TO_DEVICE); 753 if (unlikely(dma_mapping_error(dev->dev.parent, 754 desc->buf_ptr))) { 755 WARN(1, "dma_map_single failed!\n"); 756 return -ENOMEM; 757 } 758 } 759 760 cmd_sts = BUFFER_OWNED_BY_DMA; 761 if (last_tcp) { 762 /* last descriptor in the TCP packet */ 763 cmd_sts |= ZERO_PADDING | TX_LAST_DESC; 764 /* last descriptor in SKB */ 765 if (is_last) 766 cmd_sts |= TX_ENABLE_INTERRUPT; 767 } 768 desc->cmd_sts = cmd_sts; 769 return 0; 770 } 771 772 static inline void 773 txq_put_hdr_tso(struct sk_buff *skb, struct tx_queue *txq, int length, 774 u32 *first_cmd_sts, bool first_desc) 775 { 776 struct mv643xx_eth_private *mp = txq_to_mp(txq); 777 int hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb); 778 int tx_index; 779 struct tx_desc *desc; 780 int ret; 781 u32 cmd_csum = 0; 782 u16 l4i_chk = 0; 783 u32 cmd_sts; 784 785 tx_index = txq->tx_curr_desc; 786 desc = &txq->tx_desc_area[tx_index]; 787 788 ret = skb_tx_csum(mp, skb, &l4i_chk, &cmd_csum, length); 789 if (ret) 790 WARN(1, "failed to prepare checksum!"); 791 792 /* Should we set this? Can't use the value from skb_tx_csum() 793 * as it's not the correct initial L4 checksum to use. */ 794 desc->l4i_chk = 0; 795 796 desc->byte_cnt = hdr_len; 797 desc->buf_ptr = txq->tso_hdrs_dma + 798 txq->tx_curr_desc * TSO_HEADER_SIZE; 799 cmd_sts = cmd_csum | BUFFER_OWNED_BY_DMA | TX_FIRST_DESC | 800 GEN_CRC; 801 802 /* Defer updating the first command descriptor until all 803 * following descriptors have been written. 804 */ 805 if (first_desc) 806 *first_cmd_sts = cmd_sts; 807 else 808 desc->cmd_sts = cmd_sts; 809 810 txq->tx_curr_desc++; 811 if (txq->tx_curr_desc == txq->tx_ring_size) 812 txq->tx_curr_desc = 0; 813 } 814 815 static int txq_submit_tso(struct tx_queue *txq, struct sk_buff *skb, 816 struct net_device *dev) 817 { 818 struct mv643xx_eth_private *mp = txq_to_mp(txq); 819 int total_len, data_left, ret; 820 int desc_count = 0; 821 struct tso_t tso; 822 int hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb); 823 struct tx_desc *first_tx_desc; 824 u32 first_cmd_sts = 0; 825 826 /* Count needed descriptors */ 827 if ((txq->tx_desc_count + tso_count_descs(skb)) >= txq->tx_ring_size) { 828 netdev_dbg(dev, "not enough descriptors for TSO!\n"); 829 return -EBUSY; 830 } 831 832 first_tx_desc = &txq->tx_desc_area[txq->tx_curr_desc]; 833 834 /* Initialize the TSO handler, and prepare the first payload */ 835 tso_start(skb, &tso); 836 837 total_len = skb->len - hdr_len; 838 while (total_len > 0) { 839 bool first_desc = (desc_count == 0); 840 char *hdr; 841 842 data_left = min_t(int, skb_shinfo(skb)->gso_size, total_len); 843 total_len -= data_left; 844 desc_count++; 845 846 /* prepare packet headers: MAC + IP + TCP */ 847 hdr = txq->tso_hdrs + txq->tx_curr_desc * TSO_HEADER_SIZE; 848 tso_build_hdr(skb, hdr, &tso, data_left, total_len == 0); 849 txq_put_hdr_tso(skb, txq, data_left, &first_cmd_sts, 850 first_desc); 851 852 while (data_left > 0) { 853 int size; 854 desc_count++; 855 856 size = min_t(int, tso.size, data_left); 857 ret = txq_put_data_tso(dev, txq, skb, tso.data, size, 858 size == data_left, 859 total_len == 0); 860 if (ret) 861 goto err_release; 862 data_left -= size; 863 tso_build_data(skb, &tso, size); 864 } 865 } 866 867 __skb_queue_tail(&txq->tx_skb, skb); 868 skb_tx_timestamp(skb); 869 870 /* ensure all other descriptors are written before first cmd_sts */ 871 wmb(); 872 first_tx_desc->cmd_sts = first_cmd_sts; 873 874 /* clear TX_END status */ 875 mp->work_tx_end &= ~(1 << txq->index); 876 877 /* ensure all descriptors are written before poking hardware */ 878 wmb(); 879 txq_enable(txq); 880 txq->tx_desc_count += desc_count; 881 return 0; 882 err_release: 883 /* TODO: Release all used data descriptors; header descriptors must not 884 * be DMA-unmapped. 885 */ 886 return ret; 887 } 888 889 static void txq_submit_frag_skb(struct tx_queue *txq, struct sk_buff *skb) 890 { 891 struct mv643xx_eth_private *mp = txq_to_mp(txq); 892 int nr_frags = skb_shinfo(skb)->nr_frags; 893 int frag; 894 895 for (frag = 0; frag < nr_frags; frag++) { 896 skb_frag_t *this_frag; 897 int tx_index; 898 struct tx_desc *desc; 899 900 this_frag = &skb_shinfo(skb)->frags[frag]; 901 tx_index = txq->tx_curr_desc++; 902 if (txq->tx_curr_desc == txq->tx_ring_size) 903 txq->tx_curr_desc = 0; 904 desc = &txq->tx_desc_area[tx_index]; 905 txq->tx_desc_mapping[tx_index] = DESC_DMA_MAP_PAGE; 906 907 /* 908 * The last fragment will generate an interrupt 909 * which will free the skb on TX completion. 910 */ 911 if (frag == nr_frags - 1) { 912 desc->cmd_sts = BUFFER_OWNED_BY_DMA | 913 ZERO_PADDING | TX_LAST_DESC | 914 TX_ENABLE_INTERRUPT; 915 } else { 916 desc->cmd_sts = BUFFER_OWNED_BY_DMA; 917 } 918 919 desc->l4i_chk = 0; 920 desc->byte_cnt = skb_frag_size(this_frag); 921 desc->buf_ptr = skb_frag_dma_map(mp->dev->dev.parent, 922 this_frag, 0, desc->byte_cnt, 923 DMA_TO_DEVICE); 924 } 925 } 926 927 static int txq_submit_skb(struct tx_queue *txq, struct sk_buff *skb, 928 struct net_device *dev) 929 { 930 struct mv643xx_eth_private *mp = txq_to_mp(txq); 931 int nr_frags = skb_shinfo(skb)->nr_frags; 932 int tx_index; 933 struct tx_desc *desc; 934 u32 cmd_sts; 935 u16 l4i_chk; 936 int length, ret; 937 938 cmd_sts = 0; 939 l4i_chk = 0; 940 941 if (txq->tx_ring_size - txq->tx_desc_count < MAX_SKB_FRAGS + 1) { 942 if (net_ratelimit()) 943 netdev_err(dev, "tx queue full?!\n"); 944 return -EBUSY; 945 } 946 947 ret = skb_tx_csum(mp, skb, &l4i_chk, &cmd_sts, skb->len); 948 if (ret) 949 return ret; 950 cmd_sts |= TX_FIRST_DESC | GEN_CRC | BUFFER_OWNED_BY_DMA; 951 952 tx_index = txq->tx_curr_desc++; 953 if (txq->tx_curr_desc == txq->tx_ring_size) 954 txq->tx_curr_desc = 0; 955 desc = &txq->tx_desc_area[tx_index]; 956 txq->tx_desc_mapping[tx_index] = DESC_DMA_MAP_SINGLE; 957 958 if (nr_frags) { 959 txq_submit_frag_skb(txq, skb); 960 length = skb_headlen(skb); 961 } else { 962 cmd_sts |= ZERO_PADDING | TX_LAST_DESC | TX_ENABLE_INTERRUPT; 963 length = skb->len; 964 } 965 966 desc->l4i_chk = l4i_chk; 967 desc->byte_cnt = length; 968 desc->buf_ptr = dma_map_single(mp->dev->dev.parent, skb->data, 969 length, DMA_TO_DEVICE); 970 971 __skb_queue_tail(&txq->tx_skb, skb); 972 973 skb_tx_timestamp(skb); 974 975 /* ensure all other descriptors are written before first cmd_sts */ 976 wmb(); 977 desc->cmd_sts = cmd_sts; 978 979 /* clear TX_END status */ 980 mp->work_tx_end &= ~(1 << txq->index); 981 982 /* ensure all descriptors are written before poking hardware */ 983 wmb(); 984 txq_enable(txq); 985 986 txq->tx_desc_count += nr_frags + 1; 987 988 return 0; 989 } 990 991 static netdev_tx_t mv643xx_eth_xmit(struct sk_buff *skb, struct net_device *dev) 992 { 993 struct mv643xx_eth_private *mp = netdev_priv(dev); 994 int length, queue, ret; 995 struct tx_queue *txq; 996 struct netdev_queue *nq; 997 998 queue = skb_get_queue_mapping(skb); 999 txq = mp->txq + queue; 1000 nq = netdev_get_tx_queue(dev, queue); 1001 1002 if (has_tiny_unaligned_frags(skb) && __skb_linearize(skb)) { 1003 netdev_printk(KERN_DEBUG, dev, 1004 "failed to linearize skb with tiny unaligned fragment\n"); 1005 return NETDEV_TX_BUSY; 1006 } 1007 1008 length = skb->len; 1009 1010 if (skb_is_gso(skb)) 1011 ret = txq_submit_tso(txq, skb, dev); 1012 else 1013 ret = txq_submit_skb(txq, skb, dev); 1014 if (!ret) { 1015 txq->tx_bytes += length; 1016 txq->tx_packets++; 1017 1018 if (txq->tx_desc_count >= txq->tx_stop_threshold) 1019 netif_tx_stop_queue(nq); 1020 } else { 1021 txq->tx_dropped++; 1022 dev_kfree_skb_any(skb); 1023 } 1024 1025 return NETDEV_TX_OK; 1026 } 1027 1028 1029 /* tx napi ******************************************************************/ 1030 static void txq_kick(struct tx_queue *txq) 1031 { 1032 struct mv643xx_eth_private *mp = txq_to_mp(txq); 1033 struct netdev_queue *nq = netdev_get_tx_queue(mp->dev, txq->index); 1034 u32 hw_desc_ptr; 1035 u32 expected_ptr; 1036 1037 __netif_tx_lock(nq, smp_processor_id()); 1038 1039 if (rdlp(mp, TXQ_COMMAND) & (1 << txq->index)) 1040 goto out; 1041 1042 hw_desc_ptr = rdlp(mp, TXQ_CURRENT_DESC_PTR(txq->index)); 1043 expected_ptr = (u32)txq->tx_desc_dma + 1044 txq->tx_curr_desc * sizeof(struct tx_desc); 1045 1046 if (hw_desc_ptr != expected_ptr) 1047 txq_enable(txq); 1048 1049 out: 1050 __netif_tx_unlock(nq); 1051 1052 mp->work_tx_end &= ~(1 << txq->index); 1053 } 1054 1055 static int txq_reclaim(struct tx_queue *txq, int budget, int force) 1056 { 1057 struct mv643xx_eth_private *mp = txq_to_mp(txq); 1058 struct netdev_queue *nq = netdev_get_tx_queue(mp->dev, txq->index); 1059 int reclaimed; 1060 1061 __netif_tx_lock_bh(nq); 1062 1063 reclaimed = 0; 1064 while (reclaimed < budget && txq->tx_desc_count > 0) { 1065 int tx_index; 1066 struct tx_desc *desc; 1067 u32 cmd_sts; 1068 char desc_dma_map; 1069 1070 tx_index = txq->tx_used_desc; 1071 desc = &txq->tx_desc_area[tx_index]; 1072 desc_dma_map = txq->tx_desc_mapping[tx_index]; 1073 1074 cmd_sts = desc->cmd_sts; 1075 1076 if (cmd_sts & BUFFER_OWNED_BY_DMA) { 1077 if (!force) 1078 break; 1079 desc->cmd_sts = cmd_sts & ~BUFFER_OWNED_BY_DMA; 1080 } 1081 1082 txq->tx_used_desc = tx_index + 1; 1083 if (txq->tx_used_desc == txq->tx_ring_size) 1084 txq->tx_used_desc = 0; 1085 1086 reclaimed++; 1087 txq->tx_desc_count--; 1088 1089 if (!IS_TSO_HEADER(txq, desc->buf_ptr)) { 1090 1091 if (desc_dma_map == DESC_DMA_MAP_PAGE) 1092 dma_unmap_page(mp->dev->dev.parent, 1093 desc->buf_ptr, 1094 desc->byte_cnt, 1095 DMA_TO_DEVICE); 1096 else 1097 dma_unmap_single(mp->dev->dev.parent, 1098 desc->buf_ptr, 1099 desc->byte_cnt, 1100 DMA_TO_DEVICE); 1101 } 1102 1103 if (cmd_sts & TX_ENABLE_INTERRUPT) { 1104 struct sk_buff *skb = __skb_dequeue(&txq->tx_skb); 1105 1106 if (!WARN_ON(!skb)) 1107 dev_consume_skb_any(skb); 1108 } 1109 1110 if (cmd_sts & ERROR_SUMMARY) { 1111 netdev_info(mp->dev, "tx error\n"); 1112 mp->dev->stats.tx_errors++; 1113 } 1114 1115 } 1116 1117 __netif_tx_unlock_bh(nq); 1118 1119 if (reclaimed < budget) 1120 mp->work_tx &= ~(1 << txq->index); 1121 1122 return reclaimed; 1123 } 1124 1125 1126 /* tx rate control **********************************************************/ 1127 /* 1128 * Set total maximum TX rate (shared by all TX queues for this port) 1129 * to 'rate' bits per second, with a maximum burst of 'burst' bytes. 1130 */ 1131 static void tx_set_rate(struct mv643xx_eth_private *mp, int rate, int burst) 1132 { 1133 int token_rate; 1134 int mtu; 1135 int bucket_size; 1136 1137 token_rate = ((rate / 1000) * 64) / (mp->t_clk / 1000); 1138 if (token_rate > 1023) 1139 token_rate = 1023; 1140 1141 mtu = (mp->dev->mtu + 255) >> 8; 1142 if (mtu > 63) 1143 mtu = 63; 1144 1145 bucket_size = (burst + 255) >> 8; 1146 if (bucket_size > 65535) 1147 bucket_size = 65535; 1148 1149 switch (mp->shared->tx_bw_control) { 1150 case TX_BW_CONTROL_OLD_LAYOUT: 1151 wrlp(mp, TX_BW_RATE, token_rate); 1152 wrlp(mp, TX_BW_MTU, mtu); 1153 wrlp(mp, TX_BW_BURST, bucket_size); 1154 break; 1155 case TX_BW_CONTROL_NEW_LAYOUT: 1156 wrlp(mp, TX_BW_RATE_MOVED, token_rate); 1157 wrlp(mp, TX_BW_MTU_MOVED, mtu); 1158 wrlp(mp, TX_BW_BURST_MOVED, bucket_size); 1159 break; 1160 } 1161 } 1162 1163 static void txq_set_rate(struct tx_queue *txq, int rate, int burst) 1164 { 1165 struct mv643xx_eth_private *mp = txq_to_mp(txq); 1166 int token_rate; 1167 int bucket_size; 1168 1169 token_rate = ((rate / 1000) * 64) / (mp->t_clk / 1000); 1170 if (token_rate > 1023) 1171 token_rate = 1023; 1172 1173 bucket_size = (burst + 255) >> 8; 1174 if (bucket_size > 65535) 1175 bucket_size = 65535; 1176 1177 wrlp(mp, TXQ_BW_TOKENS(txq->index), token_rate << 14); 1178 wrlp(mp, TXQ_BW_CONF(txq->index), (bucket_size << 10) | token_rate); 1179 } 1180 1181 static void txq_set_fixed_prio_mode(struct tx_queue *txq) 1182 { 1183 struct mv643xx_eth_private *mp = txq_to_mp(txq); 1184 int off; 1185 u32 val; 1186 1187 /* 1188 * Turn on fixed priority mode. 1189 */ 1190 off = 0; 1191 switch (mp->shared->tx_bw_control) { 1192 case TX_BW_CONTROL_OLD_LAYOUT: 1193 off = TXQ_FIX_PRIO_CONF; 1194 break; 1195 case TX_BW_CONTROL_NEW_LAYOUT: 1196 off = TXQ_FIX_PRIO_CONF_MOVED; 1197 break; 1198 } 1199 1200 if (off) { 1201 val = rdlp(mp, off); 1202 val |= 1 << txq->index; 1203 wrlp(mp, off, val); 1204 } 1205 } 1206 1207 1208 /* mii management interface *************************************************/ 1209 static void mv643xx_eth_adjust_link(struct net_device *dev) 1210 { 1211 struct mv643xx_eth_private *mp = netdev_priv(dev); 1212 u32 pscr = rdlp(mp, PORT_SERIAL_CONTROL); 1213 u32 autoneg_disable = FORCE_LINK_PASS | 1214 DISABLE_AUTO_NEG_SPEED_GMII | 1215 DISABLE_AUTO_NEG_FOR_FLOW_CTRL | 1216 DISABLE_AUTO_NEG_FOR_DUPLEX; 1217 1218 if (dev->phydev->autoneg == AUTONEG_ENABLE) { 1219 /* enable auto negotiation */ 1220 pscr &= ~autoneg_disable; 1221 goto out_write; 1222 } 1223 1224 pscr |= autoneg_disable; 1225 1226 if (dev->phydev->speed == SPEED_1000) { 1227 /* force gigabit, half duplex not supported */ 1228 pscr |= SET_GMII_SPEED_TO_1000; 1229 pscr |= SET_FULL_DUPLEX_MODE; 1230 goto out_write; 1231 } 1232 1233 pscr &= ~SET_GMII_SPEED_TO_1000; 1234 1235 if (dev->phydev->speed == SPEED_100) 1236 pscr |= SET_MII_SPEED_TO_100; 1237 else 1238 pscr &= ~SET_MII_SPEED_TO_100; 1239 1240 if (dev->phydev->duplex == DUPLEX_FULL) 1241 pscr |= SET_FULL_DUPLEX_MODE; 1242 else 1243 pscr &= ~SET_FULL_DUPLEX_MODE; 1244 1245 out_write: 1246 wrlp(mp, PORT_SERIAL_CONTROL, pscr); 1247 } 1248 1249 /* statistics ***************************************************************/ 1250 static struct net_device_stats *mv643xx_eth_get_stats(struct net_device *dev) 1251 { 1252 struct mv643xx_eth_private *mp = netdev_priv(dev); 1253 struct net_device_stats *stats = &dev->stats; 1254 unsigned long tx_packets = 0; 1255 unsigned long tx_bytes = 0; 1256 unsigned long tx_dropped = 0; 1257 int i; 1258 1259 for (i = 0; i < mp->txq_count; i++) { 1260 struct tx_queue *txq = mp->txq + i; 1261 1262 tx_packets += txq->tx_packets; 1263 tx_bytes += txq->tx_bytes; 1264 tx_dropped += txq->tx_dropped; 1265 } 1266 1267 stats->tx_packets = tx_packets; 1268 stats->tx_bytes = tx_bytes; 1269 stats->tx_dropped = tx_dropped; 1270 1271 return stats; 1272 } 1273 1274 static inline u32 mib_read(struct mv643xx_eth_private *mp, int offset) 1275 { 1276 return rdl(mp, MIB_COUNTERS(mp->port_num) + offset); 1277 } 1278 1279 static void mib_counters_clear(struct mv643xx_eth_private *mp) 1280 { 1281 int i; 1282 1283 for (i = 0; i < 0x80; i += 4) 1284 mib_read(mp, i); 1285 1286 /* Clear non MIB hw counters also */ 1287 rdlp(mp, RX_DISCARD_FRAME_CNT); 1288 rdlp(mp, RX_OVERRUN_FRAME_CNT); 1289 } 1290 1291 static void mib_counters_update(struct mv643xx_eth_private *mp) 1292 { 1293 struct mib_counters *p = &mp->mib_counters; 1294 1295 spin_lock_bh(&mp->mib_counters_lock); 1296 p->good_octets_received += mib_read(mp, 0x00); 1297 p->bad_octets_received += mib_read(mp, 0x08); 1298 p->internal_mac_transmit_err += mib_read(mp, 0x0c); 1299 p->good_frames_received += mib_read(mp, 0x10); 1300 p->bad_frames_received += mib_read(mp, 0x14); 1301 p->broadcast_frames_received += mib_read(mp, 0x18); 1302 p->multicast_frames_received += mib_read(mp, 0x1c); 1303 p->frames_64_octets += mib_read(mp, 0x20); 1304 p->frames_65_to_127_octets += mib_read(mp, 0x24); 1305 p->frames_128_to_255_octets += mib_read(mp, 0x28); 1306 p->frames_256_to_511_octets += mib_read(mp, 0x2c); 1307 p->frames_512_to_1023_octets += mib_read(mp, 0x30); 1308 p->frames_1024_to_max_octets += mib_read(mp, 0x34); 1309 p->good_octets_sent += mib_read(mp, 0x38); 1310 p->good_frames_sent += mib_read(mp, 0x40); 1311 p->excessive_collision += mib_read(mp, 0x44); 1312 p->multicast_frames_sent += mib_read(mp, 0x48); 1313 p->broadcast_frames_sent += mib_read(mp, 0x4c); 1314 p->unrec_mac_control_received += mib_read(mp, 0x50); 1315 p->fc_sent += mib_read(mp, 0x54); 1316 p->good_fc_received += mib_read(mp, 0x58); 1317 p->bad_fc_received += mib_read(mp, 0x5c); 1318 p->undersize_received += mib_read(mp, 0x60); 1319 p->fragments_received += mib_read(mp, 0x64); 1320 p->oversize_received += mib_read(mp, 0x68); 1321 p->jabber_received += mib_read(mp, 0x6c); 1322 p->mac_receive_error += mib_read(mp, 0x70); 1323 p->bad_crc_event += mib_read(mp, 0x74); 1324 p->collision += mib_read(mp, 0x78); 1325 p->late_collision += mib_read(mp, 0x7c); 1326 /* Non MIB hardware counters */ 1327 p->rx_discard += rdlp(mp, RX_DISCARD_FRAME_CNT); 1328 p->rx_overrun += rdlp(mp, RX_OVERRUN_FRAME_CNT); 1329 spin_unlock_bh(&mp->mib_counters_lock); 1330 } 1331 1332 static void mib_counters_timer_wrapper(struct timer_list *t) 1333 { 1334 struct mv643xx_eth_private *mp = from_timer(mp, t, mib_counters_timer); 1335 mib_counters_update(mp); 1336 mod_timer(&mp->mib_counters_timer, jiffies + 30 * HZ); 1337 } 1338 1339 1340 /* interrupt coalescing *****************************************************/ 1341 /* 1342 * Hardware coalescing parameters are set in units of 64 t_clk 1343 * cycles. I.e.: 1344 * 1345 * coal_delay_in_usec = 64000000 * register_value / t_clk_rate 1346 * 1347 * register_value = coal_delay_in_usec * t_clk_rate / 64000000 1348 * 1349 * In the ->set*() methods, we round the computed register value 1350 * to the nearest integer. 1351 */ 1352 static unsigned int get_rx_coal(struct mv643xx_eth_private *mp) 1353 { 1354 u32 val = rdlp(mp, SDMA_CONFIG); 1355 u64 temp; 1356 1357 if (mp->shared->extended_rx_coal_limit) 1358 temp = ((val & 0x02000000) >> 10) | ((val & 0x003fff80) >> 7); 1359 else 1360 temp = (val & 0x003fff00) >> 8; 1361 1362 temp *= 64000000; 1363 temp += mp->t_clk / 2; 1364 do_div(temp, mp->t_clk); 1365 1366 return (unsigned int)temp; 1367 } 1368 1369 static void set_rx_coal(struct mv643xx_eth_private *mp, unsigned int usec) 1370 { 1371 u64 temp; 1372 u32 val; 1373 1374 temp = (u64)usec * mp->t_clk; 1375 temp += 31999999; 1376 do_div(temp, 64000000); 1377 1378 val = rdlp(mp, SDMA_CONFIG); 1379 if (mp->shared->extended_rx_coal_limit) { 1380 if (temp > 0xffff) 1381 temp = 0xffff; 1382 val &= ~0x023fff80; 1383 val |= (temp & 0x8000) << 10; 1384 val |= (temp & 0x7fff) << 7; 1385 } else { 1386 if (temp > 0x3fff) 1387 temp = 0x3fff; 1388 val &= ~0x003fff00; 1389 val |= (temp & 0x3fff) << 8; 1390 } 1391 wrlp(mp, SDMA_CONFIG, val); 1392 } 1393 1394 static unsigned int get_tx_coal(struct mv643xx_eth_private *mp) 1395 { 1396 u64 temp; 1397 1398 temp = (rdlp(mp, TX_FIFO_URGENT_THRESHOLD) & 0x3fff0) >> 4; 1399 temp *= 64000000; 1400 temp += mp->t_clk / 2; 1401 do_div(temp, mp->t_clk); 1402 1403 return (unsigned int)temp; 1404 } 1405 1406 static void set_tx_coal(struct mv643xx_eth_private *mp, unsigned int usec) 1407 { 1408 u64 temp; 1409 1410 temp = (u64)usec * mp->t_clk; 1411 temp += 31999999; 1412 do_div(temp, 64000000); 1413 1414 if (temp > 0x3fff) 1415 temp = 0x3fff; 1416 1417 wrlp(mp, TX_FIFO_URGENT_THRESHOLD, temp << 4); 1418 } 1419 1420 1421 /* ethtool ******************************************************************/ 1422 struct mv643xx_eth_stats { 1423 char stat_string[ETH_GSTRING_LEN]; 1424 int sizeof_stat; 1425 int netdev_off; 1426 int mp_off; 1427 }; 1428 1429 #define SSTAT(m) \ 1430 { #m, sizeof_field(struct net_device_stats, m), \ 1431 offsetof(struct net_device, stats.m), -1 } 1432 1433 #define MIBSTAT(m) \ 1434 { #m, sizeof_field(struct mib_counters, m), \ 1435 -1, offsetof(struct mv643xx_eth_private, mib_counters.m) } 1436 1437 static const struct mv643xx_eth_stats mv643xx_eth_stats[] = { 1438 SSTAT(rx_packets), 1439 SSTAT(tx_packets), 1440 SSTAT(rx_bytes), 1441 SSTAT(tx_bytes), 1442 SSTAT(rx_errors), 1443 SSTAT(tx_errors), 1444 SSTAT(rx_dropped), 1445 SSTAT(tx_dropped), 1446 MIBSTAT(good_octets_received), 1447 MIBSTAT(bad_octets_received), 1448 MIBSTAT(internal_mac_transmit_err), 1449 MIBSTAT(good_frames_received), 1450 MIBSTAT(bad_frames_received), 1451 MIBSTAT(broadcast_frames_received), 1452 MIBSTAT(multicast_frames_received), 1453 MIBSTAT(frames_64_octets), 1454 MIBSTAT(frames_65_to_127_octets), 1455 MIBSTAT(frames_128_to_255_octets), 1456 MIBSTAT(frames_256_to_511_octets), 1457 MIBSTAT(frames_512_to_1023_octets), 1458 MIBSTAT(frames_1024_to_max_octets), 1459 MIBSTAT(good_octets_sent), 1460 MIBSTAT(good_frames_sent), 1461 MIBSTAT(excessive_collision), 1462 MIBSTAT(multicast_frames_sent), 1463 MIBSTAT(broadcast_frames_sent), 1464 MIBSTAT(unrec_mac_control_received), 1465 MIBSTAT(fc_sent), 1466 MIBSTAT(good_fc_received), 1467 MIBSTAT(bad_fc_received), 1468 MIBSTAT(undersize_received), 1469 MIBSTAT(fragments_received), 1470 MIBSTAT(oversize_received), 1471 MIBSTAT(jabber_received), 1472 MIBSTAT(mac_receive_error), 1473 MIBSTAT(bad_crc_event), 1474 MIBSTAT(collision), 1475 MIBSTAT(late_collision), 1476 MIBSTAT(rx_discard), 1477 MIBSTAT(rx_overrun), 1478 }; 1479 1480 static int 1481 mv643xx_eth_get_link_ksettings_phy(struct mv643xx_eth_private *mp, 1482 struct ethtool_link_ksettings *cmd) 1483 { 1484 struct net_device *dev = mp->dev; 1485 1486 phy_ethtool_ksettings_get(dev->phydev, cmd); 1487 1488 /* 1489 * The MAC does not support 1000baseT_Half. 1490 */ 1491 linkmode_clear_bit(ETHTOOL_LINK_MODE_1000baseT_Half_BIT, 1492 cmd->link_modes.supported); 1493 linkmode_clear_bit(ETHTOOL_LINK_MODE_1000baseT_Half_BIT, 1494 cmd->link_modes.advertising); 1495 1496 return 0; 1497 } 1498 1499 static int 1500 mv643xx_eth_get_link_ksettings_phyless(struct mv643xx_eth_private *mp, 1501 struct ethtool_link_ksettings *cmd) 1502 { 1503 u32 port_status; 1504 u32 supported, advertising; 1505 1506 port_status = rdlp(mp, PORT_STATUS); 1507 1508 supported = SUPPORTED_MII; 1509 advertising = ADVERTISED_MII; 1510 switch (port_status & PORT_SPEED_MASK) { 1511 case PORT_SPEED_10: 1512 cmd->base.speed = SPEED_10; 1513 break; 1514 case PORT_SPEED_100: 1515 cmd->base.speed = SPEED_100; 1516 break; 1517 case PORT_SPEED_1000: 1518 cmd->base.speed = SPEED_1000; 1519 break; 1520 default: 1521 cmd->base.speed = -1; 1522 break; 1523 } 1524 cmd->base.duplex = (port_status & FULL_DUPLEX) ? 1525 DUPLEX_FULL : DUPLEX_HALF; 1526 cmd->base.port = PORT_MII; 1527 cmd->base.phy_address = 0; 1528 cmd->base.autoneg = AUTONEG_DISABLE; 1529 1530 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.supported, 1531 supported); 1532 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.advertising, 1533 advertising); 1534 1535 return 0; 1536 } 1537 1538 static void 1539 mv643xx_eth_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 1540 { 1541 wol->supported = 0; 1542 wol->wolopts = 0; 1543 if (dev->phydev) 1544 phy_ethtool_get_wol(dev->phydev, wol); 1545 } 1546 1547 static int 1548 mv643xx_eth_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 1549 { 1550 int err; 1551 1552 if (!dev->phydev) 1553 return -EOPNOTSUPP; 1554 1555 err = phy_ethtool_set_wol(dev->phydev, wol); 1556 /* Given that mv643xx_eth works without the marvell-specific PHY driver, 1557 * this debugging hint is useful to have. 1558 */ 1559 if (err == -EOPNOTSUPP) 1560 netdev_info(dev, "The PHY does not support set_wol, was CONFIG_MARVELL_PHY enabled?\n"); 1561 return err; 1562 } 1563 1564 static int 1565 mv643xx_eth_get_link_ksettings(struct net_device *dev, 1566 struct ethtool_link_ksettings *cmd) 1567 { 1568 struct mv643xx_eth_private *mp = netdev_priv(dev); 1569 1570 if (dev->phydev) 1571 return mv643xx_eth_get_link_ksettings_phy(mp, cmd); 1572 else 1573 return mv643xx_eth_get_link_ksettings_phyless(mp, cmd); 1574 } 1575 1576 static int 1577 mv643xx_eth_set_link_ksettings(struct net_device *dev, 1578 const struct ethtool_link_ksettings *cmd) 1579 { 1580 struct ethtool_link_ksettings c = *cmd; 1581 u32 advertising; 1582 int ret; 1583 1584 if (!dev->phydev) 1585 return -EINVAL; 1586 1587 /* 1588 * The MAC does not support 1000baseT_Half. 1589 */ 1590 ethtool_convert_link_mode_to_legacy_u32(&advertising, 1591 c.link_modes.advertising); 1592 advertising &= ~ADVERTISED_1000baseT_Half; 1593 ethtool_convert_legacy_u32_to_link_mode(c.link_modes.advertising, 1594 advertising); 1595 1596 ret = phy_ethtool_ksettings_set(dev->phydev, &c); 1597 if (!ret) 1598 mv643xx_eth_adjust_link(dev); 1599 return ret; 1600 } 1601 1602 static void mv643xx_eth_get_drvinfo(struct net_device *dev, 1603 struct ethtool_drvinfo *drvinfo) 1604 { 1605 strlcpy(drvinfo->driver, mv643xx_eth_driver_name, 1606 sizeof(drvinfo->driver)); 1607 strlcpy(drvinfo->version, mv643xx_eth_driver_version, 1608 sizeof(drvinfo->version)); 1609 strlcpy(drvinfo->fw_version, "N/A", sizeof(drvinfo->fw_version)); 1610 strlcpy(drvinfo->bus_info, "platform", sizeof(drvinfo->bus_info)); 1611 } 1612 1613 static int 1614 mv643xx_eth_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec) 1615 { 1616 struct mv643xx_eth_private *mp = netdev_priv(dev); 1617 1618 ec->rx_coalesce_usecs = get_rx_coal(mp); 1619 ec->tx_coalesce_usecs = get_tx_coal(mp); 1620 1621 return 0; 1622 } 1623 1624 static int 1625 mv643xx_eth_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec) 1626 { 1627 struct mv643xx_eth_private *mp = netdev_priv(dev); 1628 1629 set_rx_coal(mp, ec->rx_coalesce_usecs); 1630 set_tx_coal(mp, ec->tx_coalesce_usecs); 1631 1632 return 0; 1633 } 1634 1635 static void 1636 mv643xx_eth_get_ringparam(struct net_device *dev, struct ethtool_ringparam *er) 1637 { 1638 struct mv643xx_eth_private *mp = netdev_priv(dev); 1639 1640 er->rx_max_pending = 4096; 1641 er->tx_max_pending = 4096; 1642 1643 er->rx_pending = mp->rx_ring_size; 1644 er->tx_pending = mp->tx_ring_size; 1645 } 1646 1647 static int 1648 mv643xx_eth_set_ringparam(struct net_device *dev, struct ethtool_ringparam *er) 1649 { 1650 struct mv643xx_eth_private *mp = netdev_priv(dev); 1651 1652 if (er->rx_mini_pending || er->rx_jumbo_pending) 1653 return -EINVAL; 1654 1655 mp->rx_ring_size = er->rx_pending < 4096 ? er->rx_pending : 4096; 1656 mp->tx_ring_size = clamp_t(unsigned int, er->tx_pending, 1657 MV643XX_MAX_SKB_DESCS * 2, 4096); 1658 if (mp->tx_ring_size != er->tx_pending) 1659 netdev_warn(dev, "TX queue size set to %u (requested %u)\n", 1660 mp->tx_ring_size, er->tx_pending); 1661 1662 if (netif_running(dev)) { 1663 mv643xx_eth_stop(dev); 1664 if (mv643xx_eth_open(dev)) { 1665 netdev_err(dev, 1666 "fatal error on re-opening device after ring param change\n"); 1667 return -ENOMEM; 1668 } 1669 } 1670 1671 return 0; 1672 } 1673 1674 1675 static int 1676 mv643xx_eth_set_features(struct net_device *dev, netdev_features_t features) 1677 { 1678 struct mv643xx_eth_private *mp = netdev_priv(dev); 1679 bool rx_csum = features & NETIF_F_RXCSUM; 1680 1681 wrlp(mp, PORT_CONFIG, rx_csum ? 0x02000000 : 0x00000000); 1682 1683 return 0; 1684 } 1685 1686 static void mv643xx_eth_get_strings(struct net_device *dev, 1687 uint32_t stringset, uint8_t *data) 1688 { 1689 int i; 1690 1691 if (stringset == ETH_SS_STATS) { 1692 for (i = 0; i < ARRAY_SIZE(mv643xx_eth_stats); i++) { 1693 memcpy(data + i * ETH_GSTRING_LEN, 1694 mv643xx_eth_stats[i].stat_string, 1695 ETH_GSTRING_LEN); 1696 } 1697 } 1698 } 1699 1700 static void mv643xx_eth_get_ethtool_stats(struct net_device *dev, 1701 struct ethtool_stats *stats, 1702 uint64_t *data) 1703 { 1704 struct mv643xx_eth_private *mp = netdev_priv(dev); 1705 int i; 1706 1707 mv643xx_eth_get_stats(dev); 1708 mib_counters_update(mp); 1709 1710 for (i = 0; i < ARRAY_SIZE(mv643xx_eth_stats); i++) { 1711 const struct mv643xx_eth_stats *stat; 1712 void *p; 1713 1714 stat = mv643xx_eth_stats + i; 1715 1716 if (stat->netdev_off >= 0) 1717 p = ((void *)mp->dev) + stat->netdev_off; 1718 else 1719 p = ((void *)mp) + stat->mp_off; 1720 1721 data[i] = (stat->sizeof_stat == 8) ? 1722 *(uint64_t *)p : *(uint32_t *)p; 1723 } 1724 } 1725 1726 static int mv643xx_eth_get_sset_count(struct net_device *dev, int sset) 1727 { 1728 if (sset == ETH_SS_STATS) 1729 return ARRAY_SIZE(mv643xx_eth_stats); 1730 1731 return -EOPNOTSUPP; 1732 } 1733 1734 static const struct ethtool_ops mv643xx_eth_ethtool_ops = { 1735 .supported_coalesce_params = ETHTOOL_COALESCE_USECS, 1736 .get_drvinfo = mv643xx_eth_get_drvinfo, 1737 .nway_reset = phy_ethtool_nway_reset, 1738 .get_link = ethtool_op_get_link, 1739 .get_coalesce = mv643xx_eth_get_coalesce, 1740 .set_coalesce = mv643xx_eth_set_coalesce, 1741 .get_ringparam = mv643xx_eth_get_ringparam, 1742 .set_ringparam = mv643xx_eth_set_ringparam, 1743 .get_strings = mv643xx_eth_get_strings, 1744 .get_ethtool_stats = mv643xx_eth_get_ethtool_stats, 1745 .get_sset_count = mv643xx_eth_get_sset_count, 1746 .get_ts_info = ethtool_op_get_ts_info, 1747 .get_wol = mv643xx_eth_get_wol, 1748 .set_wol = mv643xx_eth_set_wol, 1749 .get_link_ksettings = mv643xx_eth_get_link_ksettings, 1750 .set_link_ksettings = mv643xx_eth_set_link_ksettings, 1751 }; 1752 1753 1754 /* address handling *********************************************************/ 1755 static void uc_addr_get(struct mv643xx_eth_private *mp, unsigned char *addr) 1756 { 1757 unsigned int mac_h = rdlp(mp, MAC_ADDR_HIGH); 1758 unsigned int mac_l = rdlp(mp, MAC_ADDR_LOW); 1759 1760 addr[0] = (mac_h >> 24) & 0xff; 1761 addr[1] = (mac_h >> 16) & 0xff; 1762 addr[2] = (mac_h >> 8) & 0xff; 1763 addr[3] = mac_h & 0xff; 1764 addr[4] = (mac_l >> 8) & 0xff; 1765 addr[5] = mac_l & 0xff; 1766 } 1767 1768 static void uc_addr_set(struct mv643xx_eth_private *mp, unsigned char *addr) 1769 { 1770 wrlp(mp, MAC_ADDR_HIGH, 1771 (addr[0] << 24) | (addr[1] << 16) | (addr[2] << 8) | addr[3]); 1772 wrlp(mp, MAC_ADDR_LOW, (addr[4] << 8) | addr[5]); 1773 } 1774 1775 static u32 uc_addr_filter_mask(struct net_device *dev) 1776 { 1777 struct netdev_hw_addr *ha; 1778 u32 nibbles; 1779 1780 if (dev->flags & IFF_PROMISC) 1781 return 0; 1782 1783 nibbles = 1 << (dev->dev_addr[5] & 0x0f); 1784 netdev_for_each_uc_addr(ha, dev) { 1785 if (memcmp(dev->dev_addr, ha->addr, 5)) 1786 return 0; 1787 if ((dev->dev_addr[5] ^ ha->addr[5]) & 0xf0) 1788 return 0; 1789 1790 nibbles |= 1 << (ha->addr[5] & 0x0f); 1791 } 1792 1793 return nibbles; 1794 } 1795 1796 static void mv643xx_eth_program_unicast_filter(struct net_device *dev) 1797 { 1798 struct mv643xx_eth_private *mp = netdev_priv(dev); 1799 u32 port_config; 1800 u32 nibbles; 1801 int i; 1802 1803 uc_addr_set(mp, dev->dev_addr); 1804 1805 port_config = rdlp(mp, PORT_CONFIG) & ~UNICAST_PROMISCUOUS_MODE; 1806 1807 nibbles = uc_addr_filter_mask(dev); 1808 if (!nibbles) { 1809 port_config |= UNICAST_PROMISCUOUS_MODE; 1810 nibbles = 0xffff; 1811 } 1812 1813 for (i = 0; i < 16; i += 4) { 1814 int off = UNICAST_TABLE(mp->port_num) + i; 1815 u32 v; 1816 1817 v = 0; 1818 if (nibbles & 1) 1819 v |= 0x00000001; 1820 if (nibbles & 2) 1821 v |= 0x00000100; 1822 if (nibbles & 4) 1823 v |= 0x00010000; 1824 if (nibbles & 8) 1825 v |= 0x01000000; 1826 nibbles >>= 4; 1827 1828 wrl(mp, off, v); 1829 } 1830 1831 wrlp(mp, PORT_CONFIG, port_config); 1832 } 1833 1834 static int addr_crc(unsigned char *addr) 1835 { 1836 int crc = 0; 1837 int i; 1838 1839 for (i = 0; i < 6; i++) { 1840 int j; 1841 1842 crc = (crc ^ addr[i]) << 8; 1843 for (j = 7; j >= 0; j--) { 1844 if (crc & (0x100 << j)) 1845 crc ^= 0x107 << j; 1846 } 1847 } 1848 1849 return crc; 1850 } 1851 1852 static void mv643xx_eth_program_multicast_filter(struct net_device *dev) 1853 { 1854 struct mv643xx_eth_private *mp = netdev_priv(dev); 1855 u32 *mc_spec; 1856 u32 *mc_other; 1857 struct netdev_hw_addr *ha; 1858 int i; 1859 1860 if (dev->flags & (IFF_PROMISC | IFF_ALLMULTI)) 1861 goto promiscuous; 1862 1863 /* Allocate both mc_spec and mc_other tables */ 1864 mc_spec = kcalloc(128, sizeof(u32), GFP_ATOMIC); 1865 if (!mc_spec) 1866 goto promiscuous; 1867 mc_other = &mc_spec[64]; 1868 1869 netdev_for_each_mc_addr(ha, dev) { 1870 u8 *a = ha->addr; 1871 u32 *table; 1872 u8 entry; 1873 1874 if (memcmp(a, "\x01\x00\x5e\x00\x00", 5) == 0) { 1875 table = mc_spec; 1876 entry = a[5]; 1877 } else { 1878 table = mc_other; 1879 entry = addr_crc(a); 1880 } 1881 1882 table[entry >> 2] |= 1 << (8 * (entry & 3)); 1883 } 1884 1885 for (i = 0; i < 64; i++) { 1886 wrl(mp, SPECIAL_MCAST_TABLE(mp->port_num) + i * sizeof(u32), 1887 mc_spec[i]); 1888 wrl(mp, OTHER_MCAST_TABLE(mp->port_num) + i * sizeof(u32), 1889 mc_other[i]); 1890 } 1891 1892 kfree(mc_spec); 1893 return; 1894 1895 promiscuous: 1896 for (i = 0; i < 64; i++) { 1897 wrl(mp, SPECIAL_MCAST_TABLE(mp->port_num) + i * sizeof(u32), 1898 0x01010101u); 1899 wrl(mp, OTHER_MCAST_TABLE(mp->port_num) + i * sizeof(u32), 1900 0x01010101u); 1901 } 1902 } 1903 1904 static void mv643xx_eth_set_rx_mode(struct net_device *dev) 1905 { 1906 mv643xx_eth_program_unicast_filter(dev); 1907 mv643xx_eth_program_multicast_filter(dev); 1908 } 1909 1910 static int mv643xx_eth_set_mac_address(struct net_device *dev, void *addr) 1911 { 1912 struct sockaddr *sa = addr; 1913 1914 if (!is_valid_ether_addr(sa->sa_data)) 1915 return -EADDRNOTAVAIL; 1916 1917 memcpy(dev->dev_addr, sa->sa_data, ETH_ALEN); 1918 1919 netif_addr_lock_bh(dev); 1920 mv643xx_eth_program_unicast_filter(dev); 1921 netif_addr_unlock_bh(dev); 1922 1923 return 0; 1924 } 1925 1926 1927 /* rx/tx queue initialisation ***********************************************/ 1928 static int rxq_init(struct mv643xx_eth_private *mp, int index) 1929 { 1930 struct rx_queue *rxq = mp->rxq + index; 1931 struct rx_desc *rx_desc; 1932 int size; 1933 int i; 1934 1935 rxq->index = index; 1936 1937 rxq->rx_ring_size = mp->rx_ring_size; 1938 1939 rxq->rx_desc_count = 0; 1940 rxq->rx_curr_desc = 0; 1941 rxq->rx_used_desc = 0; 1942 1943 size = rxq->rx_ring_size * sizeof(struct rx_desc); 1944 1945 if (index == 0 && size <= mp->rx_desc_sram_size) { 1946 rxq->rx_desc_area = ioremap(mp->rx_desc_sram_addr, 1947 mp->rx_desc_sram_size); 1948 rxq->rx_desc_dma = mp->rx_desc_sram_addr; 1949 } else { 1950 rxq->rx_desc_area = dma_alloc_coherent(mp->dev->dev.parent, 1951 size, &rxq->rx_desc_dma, 1952 GFP_KERNEL); 1953 } 1954 1955 if (rxq->rx_desc_area == NULL) { 1956 netdev_err(mp->dev, 1957 "can't allocate rx ring (%d bytes)\n", size); 1958 goto out; 1959 } 1960 memset(rxq->rx_desc_area, 0, size); 1961 1962 rxq->rx_desc_area_size = size; 1963 rxq->rx_skb = kcalloc(rxq->rx_ring_size, sizeof(*rxq->rx_skb), 1964 GFP_KERNEL); 1965 if (rxq->rx_skb == NULL) 1966 goto out_free; 1967 1968 rx_desc = rxq->rx_desc_area; 1969 for (i = 0; i < rxq->rx_ring_size; i++) { 1970 int nexti; 1971 1972 nexti = i + 1; 1973 if (nexti == rxq->rx_ring_size) 1974 nexti = 0; 1975 1976 rx_desc[i].next_desc_ptr = rxq->rx_desc_dma + 1977 nexti * sizeof(struct rx_desc); 1978 } 1979 1980 return 0; 1981 1982 1983 out_free: 1984 if (index == 0 && size <= mp->rx_desc_sram_size) 1985 iounmap(rxq->rx_desc_area); 1986 else 1987 dma_free_coherent(mp->dev->dev.parent, size, 1988 rxq->rx_desc_area, 1989 rxq->rx_desc_dma); 1990 1991 out: 1992 return -ENOMEM; 1993 } 1994 1995 static void rxq_deinit(struct rx_queue *rxq) 1996 { 1997 struct mv643xx_eth_private *mp = rxq_to_mp(rxq); 1998 int i; 1999 2000 rxq_disable(rxq); 2001 2002 for (i = 0; i < rxq->rx_ring_size; i++) { 2003 if (rxq->rx_skb[i]) { 2004 dev_consume_skb_any(rxq->rx_skb[i]); 2005 rxq->rx_desc_count--; 2006 } 2007 } 2008 2009 if (rxq->rx_desc_count) { 2010 netdev_err(mp->dev, "error freeing rx ring -- %d skbs stuck\n", 2011 rxq->rx_desc_count); 2012 } 2013 2014 if (rxq->index == 0 && 2015 rxq->rx_desc_area_size <= mp->rx_desc_sram_size) 2016 iounmap(rxq->rx_desc_area); 2017 else 2018 dma_free_coherent(mp->dev->dev.parent, rxq->rx_desc_area_size, 2019 rxq->rx_desc_area, rxq->rx_desc_dma); 2020 2021 kfree(rxq->rx_skb); 2022 } 2023 2024 static int txq_init(struct mv643xx_eth_private *mp, int index) 2025 { 2026 struct tx_queue *txq = mp->txq + index; 2027 struct tx_desc *tx_desc; 2028 int size; 2029 int ret; 2030 int i; 2031 2032 txq->index = index; 2033 2034 txq->tx_ring_size = mp->tx_ring_size; 2035 2036 /* A queue must always have room for at least one skb. 2037 * Therefore, stop the queue when the free entries reaches 2038 * the maximum number of descriptors per skb. 2039 */ 2040 txq->tx_stop_threshold = txq->tx_ring_size - MV643XX_MAX_SKB_DESCS; 2041 txq->tx_wake_threshold = txq->tx_stop_threshold / 2; 2042 2043 txq->tx_desc_count = 0; 2044 txq->tx_curr_desc = 0; 2045 txq->tx_used_desc = 0; 2046 2047 size = txq->tx_ring_size * sizeof(struct tx_desc); 2048 2049 if (index == 0 && size <= mp->tx_desc_sram_size) { 2050 txq->tx_desc_area = ioremap(mp->tx_desc_sram_addr, 2051 mp->tx_desc_sram_size); 2052 txq->tx_desc_dma = mp->tx_desc_sram_addr; 2053 } else { 2054 txq->tx_desc_area = dma_alloc_coherent(mp->dev->dev.parent, 2055 size, &txq->tx_desc_dma, 2056 GFP_KERNEL); 2057 } 2058 2059 if (txq->tx_desc_area == NULL) { 2060 netdev_err(mp->dev, 2061 "can't allocate tx ring (%d bytes)\n", size); 2062 return -ENOMEM; 2063 } 2064 memset(txq->tx_desc_area, 0, size); 2065 2066 txq->tx_desc_area_size = size; 2067 2068 tx_desc = txq->tx_desc_area; 2069 for (i = 0; i < txq->tx_ring_size; i++) { 2070 struct tx_desc *txd = tx_desc + i; 2071 int nexti; 2072 2073 nexti = i + 1; 2074 if (nexti == txq->tx_ring_size) 2075 nexti = 0; 2076 2077 txd->cmd_sts = 0; 2078 txd->next_desc_ptr = txq->tx_desc_dma + 2079 nexti * sizeof(struct tx_desc); 2080 } 2081 2082 txq->tx_desc_mapping = kcalloc(txq->tx_ring_size, sizeof(char), 2083 GFP_KERNEL); 2084 if (!txq->tx_desc_mapping) { 2085 ret = -ENOMEM; 2086 goto err_free_desc_area; 2087 } 2088 2089 /* Allocate DMA buffers for TSO MAC/IP/TCP headers */ 2090 txq->tso_hdrs = dma_alloc_coherent(mp->dev->dev.parent, 2091 txq->tx_ring_size * TSO_HEADER_SIZE, 2092 &txq->tso_hdrs_dma, GFP_KERNEL); 2093 if (txq->tso_hdrs == NULL) { 2094 ret = -ENOMEM; 2095 goto err_free_desc_mapping; 2096 } 2097 skb_queue_head_init(&txq->tx_skb); 2098 2099 return 0; 2100 2101 err_free_desc_mapping: 2102 kfree(txq->tx_desc_mapping); 2103 err_free_desc_area: 2104 if (index == 0 && size <= mp->tx_desc_sram_size) 2105 iounmap(txq->tx_desc_area); 2106 else 2107 dma_free_coherent(mp->dev->dev.parent, txq->tx_desc_area_size, 2108 txq->tx_desc_area, txq->tx_desc_dma); 2109 return ret; 2110 } 2111 2112 static void txq_deinit(struct tx_queue *txq) 2113 { 2114 struct mv643xx_eth_private *mp = txq_to_mp(txq); 2115 2116 txq_disable(txq); 2117 txq_reclaim(txq, txq->tx_ring_size, 1); 2118 2119 BUG_ON(txq->tx_used_desc != txq->tx_curr_desc); 2120 2121 if (txq->index == 0 && 2122 txq->tx_desc_area_size <= mp->tx_desc_sram_size) 2123 iounmap(txq->tx_desc_area); 2124 else 2125 dma_free_coherent(mp->dev->dev.parent, txq->tx_desc_area_size, 2126 txq->tx_desc_area, txq->tx_desc_dma); 2127 kfree(txq->tx_desc_mapping); 2128 2129 if (txq->tso_hdrs) 2130 dma_free_coherent(mp->dev->dev.parent, 2131 txq->tx_ring_size * TSO_HEADER_SIZE, 2132 txq->tso_hdrs, txq->tso_hdrs_dma); 2133 } 2134 2135 2136 /* netdev ops and related ***************************************************/ 2137 static int mv643xx_eth_collect_events(struct mv643xx_eth_private *mp) 2138 { 2139 u32 int_cause; 2140 u32 int_cause_ext; 2141 2142 int_cause = rdlp(mp, INT_CAUSE) & mp->int_mask; 2143 if (int_cause == 0) 2144 return 0; 2145 2146 int_cause_ext = 0; 2147 if (int_cause & INT_EXT) { 2148 int_cause &= ~INT_EXT; 2149 int_cause_ext = rdlp(mp, INT_CAUSE_EXT); 2150 } 2151 2152 if (int_cause) { 2153 wrlp(mp, INT_CAUSE, ~int_cause); 2154 mp->work_tx_end |= ((int_cause & INT_TX_END) >> 19) & 2155 ~(rdlp(mp, TXQ_COMMAND) & 0xff); 2156 mp->work_rx |= (int_cause & INT_RX) >> 2; 2157 } 2158 2159 int_cause_ext &= INT_EXT_LINK_PHY | INT_EXT_TX; 2160 if (int_cause_ext) { 2161 wrlp(mp, INT_CAUSE_EXT, ~int_cause_ext); 2162 if (int_cause_ext & INT_EXT_LINK_PHY) 2163 mp->work_link = 1; 2164 mp->work_tx |= int_cause_ext & INT_EXT_TX; 2165 } 2166 2167 return 1; 2168 } 2169 2170 static irqreturn_t mv643xx_eth_irq(int irq, void *dev_id) 2171 { 2172 struct net_device *dev = (struct net_device *)dev_id; 2173 struct mv643xx_eth_private *mp = netdev_priv(dev); 2174 2175 if (unlikely(!mv643xx_eth_collect_events(mp))) 2176 return IRQ_NONE; 2177 2178 wrlp(mp, INT_MASK, 0); 2179 napi_schedule(&mp->napi); 2180 2181 return IRQ_HANDLED; 2182 } 2183 2184 static void handle_link_event(struct mv643xx_eth_private *mp) 2185 { 2186 struct net_device *dev = mp->dev; 2187 u32 port_status; 2188 int speed; 2189 int duplex; 2190 int fc; 2191 2192 port_status = rdlp(mp, PORT_STATUS); 2193 if (!(port_status & LINK_UP)) { 2194 if (netif_carrier_ok(dev)) { 2195 int i; 2196 2197 netdev_info(dev, "link down\n"); 2198 2199 netif_carrier_off(dev); 2200 2201 for (i = 0; i < mp->txq_count; i++) { 2202 struct tx_queue *txq = mp->txq + i; 2203 2204 txq_reclaim(txq, txq->tx_ring_size, 1); 2205 txq_reset_hw_ptr(txq); 2206 } 2207 } 2208 return; 2209 } 2210 2211 switch (port_status & PORT_SPEED_MASK) { 2212 case PORT_SPEED_10: 2213 speed = 10; 2214 break; 2215 case PORT_SPEED_100: 2216 speed = 100; 2217 break; 2218 case PORT_SPEED_1000: 2219 speed = 1000; 2220 break; 2221 default: 2222 speed = -1; 2223 break; 2224 } 2225 duplex = (port_status & FULL_DUPLEX) ? 1 : 0; 2226 fc = (port_status & FLOW_CONTROL_ENABLED) ? 1 : 0; 2227 2228 netdev_info(dev, "link up, %d Mb/s, %s duplex, flow control %sabled\n", 2229 speed, duplex ? "full" : "half", fc ? "en" : "dis"); 2230 2231 if (!netif_carrier_ok(dev)) 2232 netif_carrier_on(dev); 2233 } 2234 2235 static int mv643xx_eth_poll(struct napi_struct *napi, int budget) 2236 { 2237 struct mv643xx_eth_private *mp; 2238 int work_done; 2239 2240 mp = container_of(napi, struct mv643xx_eth_private, napi); 2241 2242 if (unlikely(mp->oom)) { 2243 mp->oom = 0; 2244 del_timer(&mp->rx_oom); 2245 } 2246 2247 work_done = 0; 2248 while (work_done < budget) { 2249 u8 queue_mask; 2250 int queue; 2251 int work_tbd; 2252 2253 if (mp->work_link) { 2254 mp->work_link = 0; 2255 handle_link_event(mp); 2256 work_done++; 2257 continue; 2258 } 2259 2260 queue_mask = mp->work_tx | mp->work_tx_end | mp->work_rx; 2261 if (likely(!mp->oom)) 2262 queue_mask |= mp->work_rx_refill; 2263 2264 if (!queue_mask) { 2265 if (mv643xx_eth_collect_events(mp)) 2266 continue; 2267 break; 2268 } 2269 2270 queue = fls(queue_mask) - 1; 2271 queue_mask = 1 << queue; 2272 2273 work_tbd = budget - work_done; 2274 if (work_tbd > 16) 2275 work_tbd = 16; 2276 2277 if (mp->work_tx_end & queue_mask) { 2278 txq_kick(mp->txq + queue); 2279 } else if (mp->work_tx & queue_mask) { 2280 work_done += txq_reclaim(mp->txq + queue, work_tbd, 0); 2281 txq_maybe_wake(mp->txq + queue); 2282 } else if (mp->work_rx & queue_mask) { 2283 work_done += rxq_process(mp->rxq + queue, work_tbd); 2284 } else if (!mp->oom && (mp->work_rx_refill & queue_mask)) { 2285 work_done += rxq_refill(mp->rxq + queue, work_tbd); 2286 } else { 2287 BUG(); 2288 } 2289 } 2290 2291 if (work_done < budget) { 2292 if (mp->oom) 2293 mod_timer(&mp->rx_oom, jiffies + (HZ / 10)); 2294 napi_complete_done(napi, work_done); 2295 wrlp(mp, INT_MASK, mp->int_mask); 2296 } 2297 2298 return work_done; 2299 } 2300 2301 static inline void oom_timer_wrapper(struct timer_list *t) 2302 { 2303 struct mv643xx_eth_private *mp = from_timer(mp, t, rx_oom); 2304 2305 napi_schedule(&mp->napi); 2306 } 2307 2308 static void port_start(struct mv643xx_eth_private *mp) 2309 { 2310 struct net_device *dev = mp->dev; 2311 u32 pscr; 2312 int i; 2313 2314 /* 2315 * Perform PHY reset, if there is a PHY. 2316 */ 2317 if (dev->phydev) { 2318 struct ethtool_link_ksettings cmd; 2319 2320 mv643xx_eth_get_link_ksettings(dev, &cmd); 2321 phy_init_hw(dev->phydev); 2322 mv643xx_eth_set_link_ksettings( 2323 dev, (const struct ethtool_link_ksettings *)&cmd); 2324 phy_start(dev->phydev); 2325 } 2326 2327 /* 2328 * Configure basic link parameters. 2329 */ 2330 pscr = rdlp(mp, PORT_SERIAL_CONTROL); 2331 2332 pscr |= SERIAL_PORT_ENABLE; 2333 wrlp(mp, PORT_SERIAL_CONTROL, pscr); 2334 2335 pscr |= DO_NOT_FORCE_LINK_FAIL; 2336 if (!dev->phydev) 2337 pscr |= FORCE_LINK_PASS; 2338 wrlp(mp, PORT_SERIAL_CONTROL, pscr); 2339 2340 /* 2341 * Configure TX path and queues. 2342 */ 2343 tx_set_rate(mp, 1000000000, 16777216); 2344 for (i = 0; i < mp->txq_count; i++) { 2345 struct tx_queue *txq = mp->txq + i; 2346 2347 txq_reset_hw_ptr(txq); 2348 txq_set_rate(txq, 1000000000, 16777216); 2349 txq_set_fixed_prio_mode(txq); 2350 } 2351 2352 /* 2353 * Receive all unmatched unicast, TCP, UDP, BPDU and broadcast 2354 * frames to RX queue #0, and include the pseudo-header when 2355 * calculating receive checksums. 2356 */ 2357 mv643xx_eth_set_features(mp->dev, mp->dev->features); 2358 2359 /* 2360 * Treat BPDUs as normal multicasts, and disable partition mode. 2361 */ 2362 wrlp(mp, PORT_CONFIG_EXT, 0x00000000); 2363 2364 /* 2365 * Add configured unicast addresses to address filter table. 2366 */ 2367 mv643xx_eth_program_unicast_filter(mp->dev); 2368 2369 /* 2370 * Enable the receive queues. 2371 */ 2372 for (i = 0; i < mp->rxq_count; i++) { 2373 struct rx_queue *rxq = mp->rxq + i; 2374 u32 addr; 2375 2376 addr = (u32)rxq->rx_desc_dma; 2377 addr += rxq->rx_curr_desc * sizeof(struct rx_desc); 2378 wrlp(mp, RXQ_CURRENT_DESC_PTR(i), addr); 2379 2380 rxq_enable(rxq); 2381 } 2382 } 2383 2384 static void mv643xx_eth_recalc_skb_size(struct mv643xx_eth_private *mp) 2385 { 2386 int skb_size; 2387 2388 /* 2389 * Reserve 2+14 bytes for an ethernet header (the hardware 2390 * automatically prepends 2 bytes of dummy data to each 2391 * received packet), 16 bytes for up to four VLAN tags, and 2392 * 4 bytes for the trailing FCS -- 36 bytes total. 2393 */ 2394 skb_size = mp->dev->mtu + 36; 2395 2396 /* 2397 * Make sure that the skb size is a multiple of 8 bytes, as 2398 * the lower three bits of the receive descriptor's buffer 2399 * size field are ignored by the hardware. 2400 */ 2401 mp->skb_size = (skb_size + 7) & ~7; 2402 2403 /* 2404 * If NET_SKB_PAD is smaller than a cache line, 2405 * netdev_alloc_skb() will cause skb->data to be misaligned 2406 * to a cache line boundary. If this is the case, include 2407 * some extra space to allow re-aligning the data area. 2408 */ 2409 mp->skb_size += SKB_DMA_REALIGN; 2410 } 2411 2412 static int mv643xx_eth_open(struct net_device *dev) 2413 { 2414 struct mv643xx_eth_private *mp = netdev_priv(dev); 2415 int err; 2416 int i; 2417 2418 wrlp(mp, INT_CAUSE, 0); 2419 wrlp(mp, INT_CAUSE_EXT, 0); 2420 rdlp(mp, INT_CAUSE_EXT); 2421 2422 err = request_irq(dev->irq, mv643xx_eth_irq, 2423 IRQF_SHARED, dev->name, dev); 2424 if (err) { 2425 netdev_err(dev, "can't assign irq\n"); 2426 return -EAGAIN; 2427 } 2428 2429 mv643xx_eth_recalc_skb_size(mp); 2430 2431 napi_enable(&mp->napi); 2432 2433 mp->int_mask = INT_EXT; 2434 2435 for (i = 0; i < mp->rxq_count; i++) { 2436 err = rxq_init(mp, i); 2437 if (err) { 2438 while (--i >= 0) 2439 rxq_deinit(mp->rxq + i); 2440 goto out; 2441 } 2442 2443 rxq_refill(mp->rxq + i, INT_MAX); 2444 mp->int_mask |= INT_RX_0 << i; 2445 } 2446 2447 if (mp->oom) { 2448 mp->rx_oom.expires = jiffies + (HZ / 10); 2449 add_timer(&mp->rx_oom); 2450 } 2451 2452 for (i = 0; i < mp->txq_count; i++) { 2453 err = txq_init(mp, i); 2454 if (err) { 2455 while (--i >= 0) 2456 txq_deinit(mp->txq + i); 2457 goto out_free; 2458 } 2459 mp->int_mask |= INT_TX_END_0 << i; 2460 } 2461 2462 add_timer(&mp->mib_counters_timer); 2463 port_start(mp); 2464 2465 wrlp(mp, INT_MASK_EXT, INT_EXT_LINK_PHY | INT_EXT_TX); 2466 wrlp(mp, INT_MASK, mp->int_mask); 2467 2468 return 0; 2469 2470 2471 out_free: 2472 for (i = 0; i < mp->rxq_count; i++) 2473 rxq_deinit(mp->rxq + i); 2474 out: 2475 free_irq(dev->irq, dev); 2476 2477 return err; 2478 } 2479 2480 static void port_reset(struct mv643xx_eth_private *mp) 2481 { 2482 unsigned int data; 2483 int i; 2484 2485 for (i = 0; i < mp->rxq_count; i++) 2486 rxq_disable(mp->rxq + i); 2487 for (i = 0; i < mp->txq_count; i++) 2488 txq_disable(mp->txq + i); 2489 2490 while (1) { 2491 u32 ps = rdlp(mp, PORT_STATUS); 2492 2493 if ((ps & (TX_IN_PROGRESS | TX_FIFO_EMPTY)) == TX_FIFO_EMPTY) 2494 break; 2495 udelay(10); 2496 } 2497 2498 /* Reset the Enable bit in the Configuration Register */ 2499 data = rdlp(mp, PORT_SERIAL_CONTROL); 2500 data &= ~(SERIAL_PORT_ENABLE | 2501 DO_NOT_FORCE_LINK_FAIL | 2502 FORCE_LINK_PASS); 2503 wrlp(mp, PORT_SERIAL_CONTROL, data); 2504 } 2505 2506 static int mv643xx_eth_stop(struct net_device *dev) 2507 { 2508 struct mv643xx_eth_private *mp = netdev_priv(dev); 2509 int i; 2510 2511 wrlp(mp, INT_MASK_EXT, 0x00000000); 2512 wrlp(mp, INT_MASK, 0x00000000); 2513 rdlp(mp, INT_MASK); 2514 2515 napi_disable(&mp->napi); 2516 2517 del_timer_sync(&mp->rx_oom); 2518 2519 netif_carrier_off(dev); 2520 if (dev->phydev) 2521 phy_stop(dev->phydev); 2522 free_irq(dev->irq, dev); 2523 2524 port_reset(mp); 2525 mv643xx_eth_get_stats(dev); 2526 mib_counters_update(mp); 2527 del_timer_sync(&mp->mib_counters_timer); 2528 2529 for (i = 0; i < mp->rxq_count; i++) 2530 rxq_deinit(mp->rxq + i); 2531 for (i = 0; i < mp->txq_count; i++) 2532 txq_deinit(mp->txq + i); 2533 2534 return 0; 2535 } 2536 2537 static int mv643xx_eth_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) 2538 { 2539 int ret; 2540 2541 if (!dev->phydev) 2542 return -ENOTSUPP; 2543 2544 ret = phy_mii_ioctl(dev->phydev, ifr, cmd); 2545 if (!ret) 2546 mv643xx_eth_adjust_link(dev); 2547 return ret; 2548 } 2549 2550 static int mv643xx_eth_change_mtu(struct net_device *dev, int new_mtu) 2551 { 2552 struct mv643xx_eth_private *mp = netdev_priv(dev); 2553 2554 dev->mtu = new_mtu; 2555 mv643xx_eth_recalc_skb_size(mp); 2556 tx_set_rate(mp, 1000000000, 16777216); 2557 2558 if (!netif_running(dev)) 2559 return 0; 2560 2561 /* 2562 * Stop and then re-open the interface. This will allocate RX 2563 * skbs of the new MTU. 2564 * There is a possible danger that the open will not succeed, 2565 * due to memory being full. 2566 */ 2567 mv643xx_eth_stop(dev); 2568 if (mv643xx_eth_open(dev)) { 2569 netdev_err(dev, 2570 "fatal error on re-opening device after MTU change\n"); 2571 } 2572 2573 return 0; 2574 } 2575 2576 static void tx_timeout_task(struct work_struct *ugly) 2577 { 2578 struct mv643xx_eth_private *mp; 2579 2580 mp = container_of(ugly, struct mv643xx_eth_private, tx_timeout_task); 2581 if (netif_running(mp->dev)) { 2582 netif_tx_stop_all_queues(mp->dev); 2583 port_reset(mp); 2584 port_start(mp); 2585 netif_tx_wake_all_queues(mp->dev); 2586 } 2587 } 2588 2589 static void mv643xx_eth_tx_timeout(struct net_device *dev, unsigned int txqueue) 2590 { 2591 struct mv643xx_eth_private *mp = netdev_priv(dev); 2592 2593 netdev_info(dev, "tx timeout\n"); 2594 2595 schedule_work(&mp->tx_timeout_task); 2596 } 2597 2598 #ifdef CONFIG_NET_POLL_CONTROLLER 2599 static void mv643xx_eth_netpoll(struct net_device *dev) 2600 { 2601 struct mv643xx_eth_private *mp = netdev_priv(dev); 2602 2603 wrlp(mp, INT_MASK, 0x00000000); 2604 rdlp(mp, INT_MASK); 2605 2606 mv643xx_eth_irq(dev->irq, dev); 2607 2608 wrlp(mp, INT_MASK, mp->int_mask); 2609 } 2610 #endif 2611 2612 2613 /* platform glue ************************************************************/ 2614 static void 2615 mv643xx_eth_conf_mbus_windows(struct mv643xx_eth_shared_private *msp, 2616 const struct mbus_dram_target_info *dram) 2617 { 2618 void __iomem *base = msp->base; 2619 u32 win_enable; 2620 u32 win_protect; 2621 int i; 2622 2623 for (i = 0; i < 6; i++) { 2624 writel(0, base + WINDOW_BASE(i)); 2625 writel(0, base + WINDOW_SIZE(i)); 2626 if (i < 4) 2627 writel(0, base + WINDOW_REMAP_HIGH(i)); 2628 } 2629 2630 win_enable = 0x3f; 2631 win_protect = 0; 2632 2633 for (i = 0; i < dram->num_cs; i++) { 2634 const struct mbus_dram_window *cs = dram->cs + i; 2635 2636 writel((cs->base & 0xffff0000) | 2637 (cs->mbus_attr << 8) | 2638 dram->mbus_dram_target_id, base + WINDOW_BASE(i)); 2639 writel((cs->size - 1) & 0xffff0000, base + WINDOW_SIZE(i)); 2640 2641 win_enable &= ~(1 << i); 2642 win_protect |= 3 << (2 * i); 2643 } 2644 2645 writel(win_enable, base + WINDOW_BAR_ENABLE); 2646 msp->win_protect = win_protect; 2647 } 2648 2649 static void infer_hw_params(struct mv643xx_eth_shared_private *msp) 2650 { 2651 /* 2652 * Check whether we have a 14-bit coal limit field in bits 2653 * [21:8], or a 16-bit coal limit in bits [25,21:7] of the 2654 * SDMA config register. 2655 */ 2656 writel(0x02000000, msp->base + 0x0400 + SDMA_CONFIG); 2657 if (readl(msp->base + 0x0400 + SDMA_CONFIG) & 0x02000000) 2658 msp->extended_rx_coal_limit = 1; 2659 else 2660 msp->extended_rx_coal_limit = 0; 2661 2662 /* 2663 * Check whether the MAC supports TX rate control, and if 2664 * yes, whether its associated registers are in the old or 2665 * the new place. 2666 */ 2667 writel(1, msp->base + 0x0400 + TX_BW_MTU_MOVED); 2668 if (readl(msp->base + 0x0400 + TX_BW_MTU_MOVED) & 1) { 2669 msp->tx_bw_control = TX_BW_CONTROL_NEW_LAYOUT; 2670 } else { 2671 writel(7, msp->base + 0x0400 + TX_BW_RATE); 2672 if (readl(msp->base + 0x0400 + TX_BW_RATE) & 7) 2673 msp->tx_bw_control = TX_BW_CONTROL_OLD_LAYOUT; 2674 else 2675 msp->tx_bw_control = TX_BW_CONTROL_ABSENT; 2676 } 2677 } 2678 2679 #if defined(CONFIG_OF) 2680 static const struct of_device_id mv643xx_eth_shared_ids[] = { 2681 { .compatible = "marvell,orion-eth", }, 2682 { .compatible = "marvell,kirkwood-eth", }, 2683 { } 2684 }; 2685 MODULE_DEVICE_TABLE(of, mv643xx_eth_shared_ids); 2686 #endif 2687 2688 #if defined(CONFIG_OF_IRQ) && !defined(CONFIG_MV64X60) 2689 #define mv643xx_eth_property(_np, _name, _v) \ 2690 do { \ 2691 u32 tmp; \ 2692 if (!of_property_read_u32(_np, "marvell," _name, &tmp)) \ 2693 _v = tmp; \ 2694 } while (0) 2695 2696 static struct platform_device *port_platdev[3]; 2697 2698 static int mv643xx_eth_shared_of_add_port(struct platform_device *pdev, 2699 struct device_node *pnp) 2700 { 2701 struct platform_device *ppdev; 2702 struct mv643xx_eth_platform_data ppd; 2703 struct resource res; 2704 const char *mac_addr; 2705 int ret; 2706 int dev_num = 0; 2707 2708 memset(&ppd, 0, sizeof(ppd)); 2709 ppd.shared = pdev; 2710 2711 memset(&res, 0, sizeof(res)); 2712 if (of_irq_to_resource(pnp, 0, &res) <= 0) { 2713 dev_err(&pdev->dev, "missing interrupt on %pOFn\n", pnp); 2714 return -EINVAL; 2715 } 2716 2717 if (of_property_read_u32(pnp, "reg", &ppd.port_number)) { 2718 dev_err(&pdev->dev, "missing reg property on %pOFn\n", pnp); 2719 return -EINVAL; 2720 } 2721 2722 if (ppd.port_number >= 3) { 2723 dev_err(&pdev->dev, "invalid reg property on %pOFn\n", pnp); 2724 return -EINVAL; 2725 } 2726 2727 while (dev_num < 3 && port_platdev[dev_num]) 2728 dev_num++; 2729 2730 if (dev_num == 3) { 2731 dev_err(&pdev->dev, "too many ports registered\n"); 2732 return -EINVAL; 2733 } 2734 2735 mac_addr = of_get_mac_address(pnp); 2736 if (!IS_ERR(mac_addr)) 2737 ether_addr_copy(ppd.mac_addr, mac_addr); 2738 2739 mv643xx_eth_property(pnp, "tx-queue-size", ppd.tx_queue_size); 2740 mv643xx_eth_property(pnp, "tx-sram-addr", ppd.tx_sram_addr); 2741 mv643xx_eth_property(pnp, "tx-sram-size", ppd.tx_sram_size); 2742 mv643xx_eth_property(pnp, "rx-queue-size", ppd.rx_queue_size); 2743 mv643xx_eth_property(pnp, "rx-sram-addr", ppd.rx_sram_addr); 2744 mv643xx_eth_property(pnp, "rx-sram-size", ppd.rx_sram_size); 2745 2746 ppd.phy_node = of_parse_phandle(pnp, "phy-handle", 0); 2747 if (!ppd.phy_node) { 2748 ppd.phy_addr = MV643XX_ETH_PHY_NONE; 2749 of_property_read_u32(pnp, "speed", &ppd.speed); 2750 of_property_read_u32(pnp, "duplex", &ppd.duplex); 2751 } 2752 2753 ppdev = platform_device_alloc(MV643XX_ETH_NAME, dev_num); 2754 if (!ppdev) 2755 return -ENOMEM; 2756 ppdev->dev.coherent_dma_mask = DMA_BIT_MASK(32); 2757 ppdev->dev.of_node = pnp; 2758 2759 ret = platform_device_add_resources(ppdev, &res, 1); 2760 if (ret) 2761 goto port_err; 2762 2763 ret = platform_device_add_data(ppdev, &ppd, sizeof(ppd)); 2764 if (ret) 2765 goto port_err; 2766 2767 ret = platform_device_add(ppdev); 2768 if (ret) 2769 goto port_err; 2770 2771 port_platdev[dev_num] = ppdev; 2772 2773 return 0; 2774 2775 port_err: 2776 platform_device_put(ppdev); 2777 return ret; 2778 } 2779 2780 static int mv643xx_eth_shared_of_probe(struct platform_device *pdev) 2781 { 2782 struct mv643xx_eth_shared_platform_data *pd; 2783 struct device_node *pnp, *np = pdev->dev.of_node; 2784 int ret; 2785 2786 /* bail out if not registered from DT */ 2787 if (!np) 2788 return 0; 2789 2790 pd = devm_kzalloc(&pdev->dev, sizeof(*pd), GFP_KERNEL); 2791 if (!pd) 2792 return -ENOMEM; 2793 pdev->dev.platform_data = pd; 2794 2795 mv643xx_eth_property(np, "tx-checksum-limit", pd->tx_csum_limit); 2796 2797 for_each_available_child_of_node(np, pnp) { 2798 ret = mv643xx_eth_shared_of_add_port(pdev, pnp); 2799 if (ret) { 2800 of_node_put(pnp); 2801 return ret; 2802 } 2803 } 2804 return 0; 2805 } 2806 2807 static void mv643xx_eth_shared_of_remove(void) 2808 { 2809 int n; 2810 2811 for (n = 0; n < 3; n++) { 2812 platform_device_del(port_platdev[n]); 2813 port_platdev[n] = NULL; 2814 } 2815 } 2816 #else 2817 static inline int mv643xx_eth_shared_of_probe(struct platform_device *pdev) 2818 { 2819 return 0; 2820 } 2821 2822 static inline void mv643xx_eth_shared_of_remove(void) 2823 { 2824 } 2825 #endif 2826 2827 static int mv643xx_eth_shared_probe(struct platform_device *pdev) 2828 { 2829 static int mv643xx_eth_version_printed; 2830 struct mv643xx_eth_shared_platform_data *pd; 2831 struct mv643xx_eth_shared_private *msp; 2832 const struct mbus_dram_target_info *dram; 2833 struct resource *res; 2834 int ret; 2835 2836 if (!mv643xx_eth_version_printed++) 2837 pr_notice("MV-643xx 10/100/1000 ethernet driver version %s\n", 2838 mv643xx_eth_driver_version); 2839 2840 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2841 if (res == NULL) 2842 return -EINVAL; 2843 2844 msp = devm_kzalloc(&pdev->dev, sizeof(*msp), GFP_KERNEL); 2845 if (msp == NULL) 2846 return -ENOMEM; 2847 platform_set_drvdata(pdev, msp); 2848 2849 msp->base = devm_ioremap(&pdev->dev, res->start, resource_size(res)); 2850 if (msp->base == NULL) 2851 return -ENOMEM; 2852 2853 msp->clk = devm_clk_get(&pdev->dev, NULL); 2854 if (!IS_ERR(msp->clk)) 2855 clk_prepare_enable(msp->clk); 2856 2857 /* 2858 * (Re-)program MBUS remapping windows if we are asked to. 2859 */ 2860 dram = mv_mbus_dram_info(); 2861 if (dram) 2862 mv643xx_eth_conf_mbus_windows(msp, dram); 2863 2864 ret = mv643xx_eth_shared_of_probe(pdev); 2865 if (ret) 2866 goto err_put_clk; 2867 pd = dev_get_platdata(&pdev->dev); 2868 2869 msp->tx_csum_limit = (pd != NULL && pd->tx_csum_limit) ? 2870 pd->tx_csum_limit : 9 * 1024; 2871 infer_hw_params(msp); 2872 2873 return 0; 2874 2875 err_put_clk: 2876 if (!IS_ERR(msp->clk)) 2877 clk_disable_unprepare(msp->clk); 2878 return ret; 2879 } 2880 2881 static int mv643xx_eth_shared_remove(struct platform_device *pdev) 2882 { 2883 struct mv643xx_eth_shared_private *msp = platform_get_drvdata(pdev); 2884 2885 mv643xx_eth_shared_of_remove(); 2886 if (!IS_ERR(msp->clk)) 2887 clk_disable_unprepare(msp->clk); 2888 return 0; 2889 } 2890 2891 static struct platform_driver mv643xx_eth_shared_driver = { 2892 .probe = mv643xx_eth_shared_probe, 2893 .remove = mv643xx_eth_shared_remove, 2894 .driver = { 2895 .name = MV643XX_ETH_SHARED_NAME, 2896 .of_match_table = of_match_ptr(mv643xx_eth_shared_ids), 2897 }, 2898 }; 2899 2900 static void phy_addr_set(struct mv643xx_eth_private *mp, int phy_addr) 2901 { 2902 int addr_shift = 5 * mp->port_num; 2903 u32 data; 2904 2905 data = rdl(mp, PHY_ADDR); 2906 data &= ~(0x1f << addr_shift); 2907 data |= (phy_addr & 0x1f) << addr_shift; 2908 wrl(mp, PHY_ADDR, data); 2909 } 2910 2911 static int phy_addr_get(struct mv643xx_eth_private *mp) 2912 { 2913 unsigned int data; 2914 2915 data = rdl(mp, PHY_ADDR); 2916 2917 return (data >> (5 * mp->port_num)) & 0x1f; 2918 } 2919 2920 static void set_params(struct mv643xx_eth_private *mp, 2921 struct mv643xx_eth_platform_data *pd) 2922 { 2923 struct net_device *dev = mp->dev; 2924 unsigned int tx_ring_size; 2925 2926 if (is_valid_ether_addr(pd->mac_addr)) 2927 memcpy(dev->dev_addr, pd->mac_addr, ETH_ALEN); 2928 else 2929 uc_addr_get(mp, dev->dev_addr); 2930 2931 mp->rx_ring_size = DEFAULT_RX_QUEUE_SIZE; 2932 if (pd->rx_queue_size) 2933 mp->rx_ring_size = pd->rx_queue_size; 2934 mp->rx_desc_sram_addr = pd->rx_sram_addr; 2935 mp->rx_desc_sram_size = pd->rx_sram_size; 2936 2937 mp->rxq_count = pd->rx_queue_count ? : 1; 2938 2939 tx_ring_size = DEFAULT_TX_QUEUE_SIZE; 2940 if (pd->tx_queue_size) 2941 tx_ring_size = pd->tx_queue_size; 2942 2943 mp->tx_ring_size = clamp_t(unsigned int, tx_ring_size, 2944 MV643XX_MAX_SKB_DESCS * 2, 4096); 2945 if (mp->tx_ring_size != tx_ring_size) 2946 netdev_warn(dev, "TX queue size set to %u (requested %u)\n", 2947 mp->tx_ring_size, tx_ring_size); 2948 2949 mp->tx_desc_sram_addr = pd->tx_sram_addr; 2950 mp->tx_desc_sram_size = pd->tx_sram_size; 2951 2952 mp->txq_count = pd->tx_queue_count ? : 1; 2953 } 2954 2955 static int get_phy_mode(struct mv643xx_eth_private *mp) 2956 { 2957 struct device *dev = mp->dev->dev.parent; 2958 phy_interface_t iface; 2959 int err; 2960 2961 if (dev->of_node) 2962 err = of_get_phy_mode(dev->of_node, &iface); 2963 2964 /* Historical default if unspecified. We could also read/write 2965 * the interface state in the PSC1 2966 */ 2967 if (!dev->of_node || err) 2968 iface = PHY_INTERFACE_MODE_GMII; 2969 return iface; 2970 } 2971 2972 static struct phy_device *phy_scan(struct mv643xx_eth_private *mp, 2973 int phy_addr) 2974 { 2975 struct phy_device *phydev; 2976 int start; 2977 int num; 2978 int i; 2979 char phy_id[MII_BUS_ID_SIZE + 3]; 2980 2981 if (phy_addr == MV643XX_ETH_PHY_ADDR_DEFAULT) { 2982 start = phy_addr_get(mp) & 0x1f; 2983 num = 32; 2984 } else { 2985 start = phy_addr & 0x1f; 2986 num = 1; 2987 } 2988 2989 /* Attempt to connect to the PHY using orion-mdio */ 2990 phydev = ERR_PTR(-ENODEV); 2991 for (i = 0; i < num; i++) { 2992 int addr = (start + i) & 0x1f; 2993 2994 snprintf(phy_id, sizeof(phy_id), PHY_ID_FMT, 2995 "orion-mdio-mii", addr); 2996 2997 phydev = phy_connect(mp->dev, phy_id, mv643xx_eth_adjust_link, 2998 get_phy_mode(mp)); 2999 if (!IS_ERR(phydev)) { 3000 phy_addr_set(mp, addr); 3001 break; 3002 } 3003 } 3004 3005 return phydev; 3006 } 3007 3008 static void phy_init(struct mv643xx_eth_private *mp, int speed, int duplex) 3009 { 3010 struct net_device *dev = mp->dev; 3011 struct phy_device *phy = dev->phydev; 3012 3013 if (speed == 0) { 3014 phy->autoneg = AUTONEG_ENABLE; 3015 phy->speed = 0; 3016 phy->duplex = 0; 3017 linkmode_copy(phy->advertising, phy->supported); 3018 linkmode_set_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, 3019 phy->advertising); 3020 } else { 3021 phy->autoneg = AUTONEG_DISABLE; 3022 linkmode_zero(phy->advertising); 3023 phy->speed = speed; 3024 phy->duplex = duplex; 3025 } 3026 phy_start_aneg(phy); 3027 } 3028 3029 static void init_pscr(struct mv643xx_eth_private *mp, int speed, int duplex) 3030 { 3031 struct net_device *dev = mp->dev; 3032 u32 pscr; 3033 3034 pscr = rdlp(mp, PORT_SERIAL_CONTROL); 3035 if (pscr & SERIAL_PORT_ENABLE) { 3036 pscr &= ~SERIAL_PORT_ENABLE; 3037 wrlp(mp, PORT_SERIAL_CONTROL, pscr); 3038 } 3039 3040 pscr = MAX_RX_PACKET_9700BYTE | SERIAL_PORT_CONTROL_RESERVED; 3041 if (!dev->phydev) { 3042 pscr |= DISABLE_AUTO_NEG_SPEED_GMII; 3043 if (speed == SPEED_1000) 3044 pscr |= SET_GMII_SPEED_TO_1000; 3045 else if (speed == SPEED_100) 3046 pscr |= SET_MII_SPEED_TO_100; 3047 3048 pscr |= DISABLE_AUTO_NEG_FOR_FLOW_CTRL; 3049 3050 pscr |= DISABLE_AUTO_NEG_FOR_DUPLEX; 3051 if (duplex == DUPLEX_FULL) 3052 pscr |= SET_FULL_DUPLEX_MODE; 3053 } 3054 3055 wrlp(mp, PORT_SERIAL_CONTROL, pscr); 3056 } 3057 3058 static const struct net_device_ops mv643xx_eth_netdev_ops = { 3059 .ndo_open = mv643xx_eth_open, 3060 .ndo_stop = mv643xx_eth_stop, 3061 .ndo_start_xmit = mv643xx_eth_xmit, 3062 .ndo_set_rx_mode = mv643xx_eth_set_rx_mode, 3063 .ndo_set_mac_address = mv643xx_eth_set_mac_address, 3064 .ndo_validate_addr = eth_validate_addr, 3065 .ndo_do_ioctl = mv643xx_eth_ioctl, 3066 .ndo_change_mtu = mv643xx_eth_change_mtu, 3067 .ndo_set_features = mv643xx_eth_set_features, 3068 .ndo_tx_timeout = mv643xx_eth_tx_timeout, 3069 .ndo_get_stats = mv643xx_eth_get_stats, 3070 #ifdef CONFIG_NET_POLL_CONTROLLER 3071 .ndo_poll_controller = mv643xx_eth_netpoll, 3072 #endif 3073 }; 3074 3075 static int mv643xx_eth_probe(struct platform_device *pdev) 3076 { 3077 struct mv643xx_eth_platform_data *pd; 3078 struct mv643xx_eth_private *mp; 3079 struct net_device *dev; 3080 struct phy_device *phydev = NULL; 3081 struct resource *res; 3082 int err; 3083 3084 pd = dev_get_platdata(&pdev->dev); 3085 if (pd == NULL) { 3086 dev_err(&pdev->dev, "no mv643xx_eth_platform_data\n"); 3087 return -ENODEV; 3088 } 3089 3090 if (pd->shared == NULL) { 3091 dev_err(&pdev->dev, "no mv643xx_eth_platform_data->shared\n"); 3092 return -ENODEV; 3093 } 3094 3095 dev = alloc_etherdev_mq(sizeof(struct mv643xx_eth_private), 8); 3096 if (!dev) 3097 return -ENOMEM; 3098 3099 SET_NETDEV_DEV(dev, &pdev->dev); 3100 mp = netdev_priv(dev); 3101 platform_set_drvdata(pdev, mp); 3102 3103 mp->shared = platform_get_drvdata(pd->shared); 3104 mp->base = mp->shared->base + 0x0400 + (pd->port_number << 10); 3105 mp->port_num = pd->port_number; 3106 3107 mp->dev = dev; 3108 3109 /* Kirkwood resets some registers on gated clocks. Especially 3110 * CLK125_BYPASS_EN must be cleared but is not available on 3111 * all other SoCs/System Controllers using this driver. 3112 */ 3113 if (of_device_is_compatible(pdev->dev.of_node, 3114 "marvell,kirkwood-eth-port")) 3115 wrlp(mp, PORT_SERIAL_CONTROL1, 3116 rdlp(mp, PORT_SERIAL_CONTROL1) & ~CLK125_BYPASS_EN); 3117 3118 /* 3119 * Start with a default rate, and if there is a clock, allow 3120 * it to override the default. 3121 */ 3122 mp->t_clk = 133000000; 3123 mp->clk = devm_clk_get(&pdev->dev, NULL); 3124 if (!IS_ERR(mp->clk)) { 3125 clk_prepare_enable(mp->clk); 3126 mp->t_clk = clk_get_rate(mp->clk); 3127 } else if (!IS_ERR(mp->shared->clk)) { 3128 mp->t_clk = clk_get_rate(mp->shared->clk); 3129 } 3130 3131 set_params(mp, pd); 3132 netif_set_real_num_tx_queues(dev, mp->txq_count); 3133 netif_set_real_num_rx_queues(dev, mp->rxq_count); 3134 3135 err = 0; 3136 if (pd->phy_node) { 3137 phydev = of_phy_connect(mp->dev, pd->phy_node, 3138 mv643xx_eth_adjust_link, 0, 3139 get_phy_mode(mp)); 3140 if (!phydev) 3141 err = -ENODEV; 3142 else 3143 phy_addr_set(mp, phydev->mdio.addr); 3144 } else if (pd->phy_addr != MV643XX_ETH_PHY_NONE) { 3145 phydev = phy_scan(mp, pd->phy_addr); 3146 3147 if (IS_ERR(phydev)) 3148 err = PTR_ERR(phydev); 3149 else 3150 phy_init(mp, pd->speed, pd->duplex); 3151 } 3152 if (err == -ENODEV) { 3153 err = -EPROBE_DEFER; 3154 goto out; 3155 } 3156 if (err) 3157 goto out; 3158 3159 dev->ethtool_ops = &mv643xx_eth_ethtool_ops; 3160 3161 init_pscr(mp, pd->speed, pd->duplex); 3162 3163 3164 mib_counters_clear(mp); 3165 3166 timer_setup(&mp->mib_counters_timer, mib_counters_timer_wrapper, 0); 3167 mp->mib_counters_timer.expires = jiffies + 30 * HZ; 3168 3169 spin_lock_init(&mp->mib_counters_lock); 3170 3171 INIT_WORK(&mp->tx_timeout_task, tx_timeout_task); 3172 3173 netif_napi_add(dev, &mp->napi, mv643xx_eth_poll, NAPI_POLL_WEIGHT); 3174 3175 timer_setup(&mp->rx_oom, oom_timer_wrapper, 0); 3176 3177 3178 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); 3179 BUG_ON(!res); 3180 dev->irq = res->start; 3181 3182 dev->netdev_ops = &mv643xx_eth_netdev_ops; 3183 3184 dev->watchdog_timeo = 2 * HZ; 3185 dev->base_addr = 0; 3186 3187 dev->features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO; 3188 dev->vlan_features = dev->features; 3189 3190 dev->features |= NETIF_F_RXCSUM; 3191 dev->hw_features = dev->features; 3192 3193 dev->priv_flags |= IFF_UNICAST_FLT; 3194 dev->gso_max_segs = MV643XX_MAX_TSO_SEGS; 3195 3196 /* MTU range: 64 - 9500 */ 3197 dev->min_mtu = 64; 3198 dev->max_mtu = 9500; 3199 3200 if (mp->shared->win_protect) 3201 wrl(mp, WINDOW_PROTECT(mp->port_num), mp->shared->win_protect); 3202 3203 netif_carrier_off(dev); 3204 3205 wrlp(mp, SDMA_CONFIG, PORT_SDMA_CONFIG_DEFAULT_VALUE); 3206 3207 set_rx_coal(mp, 250); 3208 set_tx_coal(mp, 0); 3209 3210 err = register_netdev(dev); 3211 if (err) 3212 goto out; 3213 3214 netdev_notice(dev, "port %d with MAC address %pM\n", 3215 mp->port_num, dev->dev_addr); 3216 3217 if (mp->tx_desc_sram_size > 0) 3218 netdev_notice(dev, "configured with sram\n"); 3219 3220 return 0; 3221 3222 out: 3223 if (!IS_ERR(mp->clk)) 3224 clk_disable_unprepare(mp->clk); 3225 free_netdev(dev); 3226 3227 return err; 3228 } 3229 3230 static int mv643xx_eth_remove(struct platform_device *pdev) 3231 { 3232 struct mv643xx_eth_private *mp = platform_get_drvdata(pdev); 3233 struct net_device *dev = mp->dev; 3234 3235 unregister_netdev(mp->dev); 3236 if (dev->phydev) 3237 phy_disconnect(dev->phydev); 3238 cancel_work_sync(&mp->tx_timeout_task); 3239 3240 if (!IS_ERR(mp->clk)) 3241 clk_disable_unprepare(mp->clk); 3242 3243 free_netdev(mp->dev); 3244 3245 return 0; 3246 } 3247 3248 static void mv643xx_eth_shutdown(struct platform_device *pdev) 3249 { 3250 struct mv643xx_eth_private *mp = platform_get_drvdata(pdev); 3251 3252 /* Mask all interrupts on ethernet port */ 3253 wrlp(mp, INT_MASK, 0); 3254 rdlp(mp, INT_MASK); 3255 3256 if (netif_running(mp->dev)) 3257 port_reset(mp); 3258 } 3259 3260 static struct platform_driver mv643xx_eth_driver = { 3261 .probe = mv643xx_eth_probe, 3262 .remove = mv643xx_eth_remove, 3263 .shutdown = mv643xx_eth_shutdown, 3264 .driver = { 3265 .name = MV643XX_ETH_NAME, 3266 }, 3267 }; 3268 3269 static struct platform_driver * const drivers[] = { 3270 &mv643xx_eth_shared_driver, 3271 &mv643xx_eth_driver, 3272 }; 3273 3274 static int __init mv643xx_eth_init_module(void) 3275 { 3276 return platform_register_drivers(drivers, ARRAY_SIZE(drivers)); 3277 } 3278 module_init(mv643xx_eth_init_module); 3279 3280 static void __exit mv643xx_eth_cleanup_module(void) 3281 { 3282 platform_unregister_drivers(drivers, ARRAY_SIZE(drivers)); 3283 } 3284 module_exit(mv643xx_eth_cleanup_module); 3285 3286 MODULE_AUTHOR("Rabeeh Khoury, Assaf Hoffman, Matthew Dharm, " 3287 "Manish Lachwani, Dale Farnsworth and Lennert Buytenhek"); 3288 MODULE_DESCRIPTION("Ethernet driver for Marvell MV643XX"); 3289 MODULE_LICENSE("GPL"); 3290 MODULE_ALIAS("platform:" MV643XX_ETH_SHARED_NAME); 3291 MODULE_ALIAS("platform:" MV643XX_ETH_NAME); 3292