1 /* 2 * Driver for Marvell Discovery (MV643XX) and Marvell Orion ethernet ports 3 * Copyright (C) 2002 Matthew Dharm <mdharm@momenco.com> 4 * 5 * Based on the 64360 driver from: 6 * Copyright (C) 2002 Rabeeh Khoury <rabeeh@galileo.co.il> 7 * Rabeeh Khoury <rabeeh@marvell.com> 8 * 9 * Copyright (C) 2003 PMC-Sierra, Inc., 10 * written by Manish Lachwani 11 * 12 * Copyright (C) 2003 Ralf Baechle <ralf@linux-mips.org> 13 * 14 * Copyright (C) 2004-2006 MontaVista Software, Inc. 15 * Dale Farnsworth <dale@farnsworth.org> 16 * 17 * Copyright (C) 2004 Steven J. Hill <sjhill1@rockwellcollins.com> 18 * <sjhill@realitydiluted.com> 19 * 20 * Copyright (C) 2007-2008 Marvell Semiconductor 21 * Lennert Buytenhek <buytenh@marvell.com> 22 * 23 * Copyright (C) 2013 Michael Stapelberg <michael@stapelberg.de> 24 * 25 * This program is free software; you can redistribute it and/or 26 * modify it under the terms of the GNU General Public License 27 * as published by the Free Software Foundation; either version 2 28 * of the License, or (at your option) any later version. 29 * 30 * This program is distributed in the hope that it will be useful, 31 * but WITHOUT ANY WARRANTY; without even the implied warranty of 32 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 33 * GNU General Public License for more details. 34 * 35 * You should have received a copy of the GNU General Public License 36 * along with this program; if not, write to the Free Software 37 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. 38 */ 39 40 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 41 42 #include <linux/init.h> 43 #include <linux/dma-mapping.h> 44 #include <linux/in.h> 45 #include <linux/ip.h> 46 #include <linux/tcp.h> 47 #include <linux/udp.h> 48 #include <linux/etherdevice.h> 49 #include <linux/delay.h> 50 #include <linux/ethtool.h> 51 #include <linux/platform_device.h> 52 #include <linux/module.h> 53 #include <linux/kernel.h> 54 #include <linux/spinlock.h> 55 #include <linux/workqueue.h> 56 #include <linux/phy.h> 57 #include <linux/mv643xx_eth.h> 58 #include <linux/io.h> 59 #include <linux/interrupt.h> 60 #include <linux/types.h> 61 #include <linux/slab.h> 62 #include <linux/clk.h> 63 #include <linux/of.h> 64 #include <linux/of_irq.h> 65 #include <linux/of_net.h> 66 #include <linux/of_mdio.h> 67 68 static char mv643xx_eth_driver_name[] = "mv643xx_eth"; 69 static char mv643xx_eth_driver_version[] = "1.4"; 70 71 72 /* 73 * Registers shared between all ports. 74 */ 75 #define PHY_ADDR 0x0000 76 #define WINDOW_BASE(w) (0x0200 + ((w) << 3)) 77 #define WINDOW_SIZE(w) (0x0204 + ((w) << 3)) 78 #define WINDOW_REMAP_HIGH(w) (0x0280 + ((w) << 2)) 79 #define WINDOW_BAR_ENABLE 0x0290 80 #define WINDOW_PROTECT(w) (0x0294 + ((w) << 4)) 81 82 /* 83 * Main per-port registers. These live at offset 0x0400 for 84 * port #0, 0x0800 for port #1, and 0x0c00 for port #2. 85 */ 86 #define PORT_CONFIG 0x0000 87 #define UNICAST_PROMISCUOUS_MODE 0x00000001 88 #define PORT_CONFIG_EXT 0x0004 89 #define MAC_ADDR_LOW 0x0014 90 #define MAC_ADDR_HIGH 0x0018 91 #define SDMA_CONFIG 0x001c 92 #define TX_BURST_SIZE_16_64BIT 0x01000000 93 #define TX_BURST_SIZE_4_64BIT 0x00800000 94 #define BLM_TX_NO_SWAP 0x00000020 95 #define BLM_RX_NO_SWAP 0x00000010 96 #define RX_BURST_SIZE_16_64BIT 0x00000008 97 #define RX_BURST_SIZE_4_64BIT 0x00000004 98 #define PORT_SERIAL_CONTROL 0x003c 99 #define SET_MII_SPEED_TO_100 0x01000000 100 #define SET_GMII_SPEED_TO_1000 0x00800000 101 #define SET_FULL_DUPLEX_MODE 0x00200000 102 #define MAX_RX_PACKET_9700BYTE 0x000a0000 103 #define DISABLE_AUTO_NEG_SPEED_GMII 0x00002000 104 #define DO_NOT_FORCE_LINK_FAIL 0x00000400 105 #define SERIAL_PORT_CONTROL_RESERVED 0x00000200 106 #define DISABLE_AUTO_NEG_FOR_FLOW_CTRL 0x00000008 107 #define DISABLE_AUTO_NEG_FOR_DUPLEX 0x00000004 108 #define FORCE_LINK_PASS 0x00000002 109 #define SERIAL_PORT_ENABLE 0x00000001 110 #define PORT_STATUS 0x0044 111 #define TX_FIFO_EMPTY 0x00000400 112 #define TX_IN_PROGRESS 0x00000080 113 #define PORT_SPEED_MASK 0x00000030 114 #define PORT_SPEED_1000 0x00000010 115 #define PORT_SPEED_100 0x00000020 116 #define PORT_SPEED_10 0x00000000 117 #define FLOW_CONTROL_ENABLED 0x00000008 118 #define FULL_DUPLEX 0x00000004 119 #define LINK_UP 0x00000002 120 #define TXQ_COMMAND 0x0048 121 #define TXQ_FIX_PRIO_CONF 0x004c 122 #define PORT_SERIAL_CONTROL1 0x004c 123 #define CLK125_BYPASS_EN 0x00000010 124 #define TX_BW_RATE 0x0050 125 #define TX_BW_MTU 0x0058 126 #define TX_BW_BURST 0x005c 127 #define INT_CAUSE 0x0060 128 #define INT_TX_END 0x07f80000 129 #define INT_TX_END_0 0x00080000 130 #define INT_RX 0x000003fc 131 #define INT_RX_0 0x00000004 132 #define INT_EXT 0x00000002 133 #define INT_CAUSE_EXT 0x0064 134 #define INT_EXT_LINK_PHY 0x00110000 135 #define INT_EXT_TX 0x000000ff 136 #define INT_MASK 0x0068 137 #define INT_MASK_EXT 0x006c 138 #define TX_FIFO_URGENT_THRESHOLD 0x0074 139 #define RX_DISCARD_FRAME_CNT 0x0084 140 #define RX_OVERRUN_FRAME_CNT 0x0088 141 #define TXQ_FIX_PRIO_CONF_MOVED 0x00dc 142 #define TX_BW_RATE_MOVED 0x00e0 143 #define TX_BW_MTU_MOVED 0x00e8 144 #define TX_BW_BURST_MOVED 0x00ec 145 #define RXQ_CURRENT_DESC_PTR(q) (0x020c + ((q) << 4)) 146 #define RXQ_COMMAND 0x0280 147 #define TXQ_CURRENT_DESC_PTR(q) (0x02c0 + ((q) << 2)) 148 #define TXQ_BW_TOKENS(q) (0x0300 + ((q) << 4)) 149 #define TXQ_BW_CONF(q) (0x0304 + ((q) << 4)) 150 #define TXQ_BW_WRR_CONF(q) (0x0308 + ((q) << 4)) 151 152 /* 153 * Misc per-port registers. 154 */ 155 #define MIB_COUNTERS(p) (0x1000 + ((p) << 7)) 156 #define SPECIAL_MCAST_TABLE(p) (0x1400 + ((p) << 10)) 157 #define OTHER_MCAST_TABLE(p) (0x1500 + ((p) << 10)) 158 #define UNICAST_TABLE(p) (0x1600 + ((p) << 10)) 159 160 161 /* 162 * SDMA configuration register default value. 163 */ 164 #if defined(__BIG_ENDIAN) 165 #define PORT_SDMA_CONFIG_DEFAULT_VALUE \ 166 (RX_BURST_SIZE_4_64BIT | \ 167 TX_BURST_SIZE_4_64BIT) 168 #elif defined(__LITTLE_ENDIAN) 169 #define PORT_SDMA_CONFIG_DEFAULT_VALUE \ 170 (RX_BURST_SIZE_4_64BIT | \ 171 BLM_RX_NO_SWAP | \ 172 BLM_TX_NO_SWAP | \ 173 TX_BURST_SIZE_4_64BIT) 174 #else 175 #error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined 176 #endif 177 178 179 /* 180 * Misc definitions. 181 */ 182 #define DEFAULT_RX_QUEUE_SIZE 128 183 #define DEFAULT_TX_QUEUE_SIZE 256 184 #define SKB_DMA_REALIGN ((PAGE_SIZE - NET_SKB_PAD) % SMP_CACHE_BYTES) 185 186 187 /* 188 * RX/TX descriptors. 189 */ 190 #if defined(__BIG_ENDIAN) 191 struct rx_desc { 192 u16 byte_cnt; /* Descriptor buffer byte count */ 193 u16 buf_size; /* Buffer size */ 194 u32 cmd_sts; /* Descriptor command status */ 195 u32 next_desc_ptr; /* Next descriptor pointer */ 196 u32 buf_ptr; /* Descriptor buffer pointer */ 197 }; 198 199 struct tx_desc { 200 u16 byte_cnt; /* buffer byte count */ 201 u16 l4i_chk; /* CPU provided TCP checksum */ 202 u32 cmd_sts; /* Command/status field */ 203 u32 next_desc_ptr; /* Pointer to next descriptor */ 204 u32 buf_ptr; /* pointer to buffer for this descriptor*/ 205 }; 206 #elif defined(__LITTLE_ENDIAN) 207 struct rx_desc { 208 u32 cmd_sts; /* Descriptor command status */ 209 u16 buf_size; /* Buffer size */ 210 u16 byte_cnt; /* Descriptor buffer byte count */ 211 u32 buf_ptr; /* Descriptor buffer pointer */ 212 u32 next_desc_ptr; /* Next descriptor pointer */ 213 }; 214 215 struct tx_desc { 216 u32 cmd_sts; /* Command/status field */ 217 u16 l4i_chk; /* CPU provided TCP checksum */ 218 u16 byte_cnt; /* buffer byte count */ 219 u32 buf_ptr; /* pointer to buffer for this descriptor*/ 220 u32 next_desc_ptr; /* Pointer to next descriptor */ 221 }; 222 #else 223 #error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined 224 #endif 225 226 /* RX & TX descriptor command */ 227 #define BUFFER_OWNED_BY_DMA 0x80000000 228 229 /* RX & TX descriptor status */ 230 #define ERROR_SUMMARY 0x00000001 231 232 /* RX descriptor status */ 233 #define LAYER_4_CHECKSUM_OK 0x40000000 234 #define RX_ENABLE_INTERRUPT 0x20000000 235 #define RX_FIRST_DESC 0x08000000 236 #define RX_LAST_DESC 0x04000000 237 #define RX_IP_HDR_OK 0x02000000 238 #define RX_PKT_IS_IPV4 0x01000000 239 #define RX_PKT_IS_ETHERNETV2 0x00800000 240 #define RX_PKT_LAYER4_TYPE_MASK 0x00600000 241 #define RX_PKT_LAYER4_TYPE_TCP_IPV4 0x00000000 242 #define RX_PKT_IS_VLAN_TAGGED 0x00080000 243 244 /* TX descriptor command */ 245 #define TX_ENABLE_INTERRUPT 0x00800000 246 #define GEN_CRC 0x00400000 247 #define TX_FIRST_DESC 0x00200000 248 #define TX_LAST_DESC 0x00100000 249 #define ZERO_PADDING 0x00080000 250 #define GEN_IP_V4_CHECKSUM 0x00040000 251 #define GEN_TCP_UDP_CHECKSUM 0x00020000 252 #define UDP_FRAME 0x00010000 253 #define MAC_HDR_EXTRA_4_BYTES 0x00008000 254 #define MAC_HDR_EXTRA_8_BYTES 0x00000200 255 256 #define TX_IHL_SHIFT 11 257 258 259 /* global *******************************************************************/ 260 struct mv643xx_eth_shared_private { 261 /* 262 * Ethernet controller base address. 263 */ 264 void __iomem *base; 265 266 /* 267 * Per-port MBUS window access register value. 268 */ 269 u32 win_protect; 270 271 /* 272 * Hardware-specific parameters. 273 */ 274 int extended_rx_coal_limit; 275 int tx_bw_control; 276 int tx_csum_limit; 277 struct clk *clk; 278 }; 279 280 #define TX_BW_CONTROL_ABSENT 0 281 #define TX_BW_CONTROL_OLD_LAYOUT 1 282 #define TX_BW_CONTROL_NEW_LAYOUT 2 283 284 static int mv643xx_eth_open(struct net_device *dev); 285 static int mv643xx_eth_stop(struct net_device *dev); 286 287 288 /* per-port *****************************************************************/ 289 struct mib_counters { 290 u64 good_octets_received; 291 u32 bad_octets_received; 292 u32 internal_mac_transmit_err; 293 u32 good_frames_received; 294 u32 bad_frames_received; 295 u32 broadcast_frames_received; 296 u32 multicast_frames_received; 297 u32 frames_64_octets; 298 u32 frames_65_to_127_octets; 299 u32 frames_128_to_255_octets; 300 u32 frames_256_to_511_octets; 301 u32 frames_512_to_1023_octets; 302 u32 frames_1024_to_max_octets; 303 u64 good_octets_sent; 304 u32 good_frames_sent; 305 u32 excessive_collision; 306 u32 multicast_frames_sent; 307 u32 broadcast_frames_sent; 308 u32 unrec_mac_control_received; 309 u32 fc_sent; 310 u32 good_fc_received; 311 u32 bad_fc_received; 312 u32 undersize_received; 313 u32 fragments_received; 314 u32 oversize_received; 315 u32 jabber_received; 316 u32 mac_receive_error; 317 u32 bad_crc_event; 318 u32 collision; 319 u32 late_collision; 320 /* Non MIB hardware counters */ 321 u32 rx_discard; 322 u32 rx_overrun; 323 }; 324 325 struct rx_queue { 326 int index; 327 328 int rx_ring_size; 329 330 int rx_desc_count; 331 int rx_curr_desc; 332 int rx_used_desc; 333 334 struct rx_desc *rx_desc_area; 335 dma_addr_t rx_desc_dma; 336 int rx_desc_area_size; 337 struct sk_buff **rx_skb; 338 }; 339 340 struct tx_queue { 341 int index; 342 343 int tx_ring_size; 344 345 int tx_desc_count; 346 int tx_curr_desc; 347 int tx_used_desc; 348 349 struct tx_desc *tx_desc_area; 350 dma_addr_t tx_desc_dma; 351 int tx_desc_area_size; 352 353 struct sk_buff_head tx_skb; 354 355 unsigned long tx_packets; 356 unsigned long tx_bytes; 357 unsigned long tx_dropped; 358 }; 359 360 struct mv643xx_eth_private { 361 struct mv643xx_eth_shared_private *shared; 362 void __iomem *base; 363 int port_num; 364 365 struct net_device *dev; 366 367 struct phy_device *phy; 368 369 struct timer_list mib_counters_timer; 370 spinlock_t mib_counters_lock; 371 struct mib_counters mib_counters; 372 373 struct work_struct tx_timeout_task; 374 375 struct napi_struct napi; 376 u32 int_mask; 377 u8 oom; 378 u8 work_link; 379 u8 work_tx; 380 u8 work_tx_end; 381 u8 work_rx; 382 u8 work_rx_refill; 383 384 int skb_size; 385 386 /* 387 * RX state. 388 */ 389 int rx_ring_size; 390 unsigned long rx_desc_sram_addr; 391 int rx_desc_sram_size; 392 int rxq_count; 393 struct timer_list rx_oom; 394 struct rx_queue rxq[8]; 395 396 /* 397 * TX state. 398 */ 399 int tx_ring_size; 400 unsigned long tx_desc_sram_addr; 401 int tx_desc_sram_size; 402 int txq_count; 403 struct tx_queue txq[8]; 404 405 /* 406 * Hardware-specific parameters. 407 */ 408 struct clk *clk; 409 unsigned int t_clk; 410 }; 411 412 413 /* port register accessors **************************************************/ 414 static inline u32 rdl(struct mv643xx_eth_private *mp, int offset) 415 { 416 return readl(mp->shared->base + offset); 417 } 418 419 static inline u32 rdlp(struct mv643xx_eth_private *mp, int offset) 420 { 421 return readl(mp->base + offset); 422 } 423 424 static inline void wrl(struct mv643xx_eth_private *mp, int offset, u32 data) 425 { 426 writel(data, mp->shared->base + offset); 427 } 428 429 static inline void wrlp(struct mv643xx_eth_private *mp, int offset, u32 data) 430 { 431 writel(data, mp->base + offset); 432 } 433 434 435 /* rxq/txq helper functions *************************************************/ 436 static struct mv643xx_eth_private *rxq_to_mp(struct rx_queue *rxq) 437 { 438 return container_of(rxq, struct mv643xx_eth_private, rxq[rxq->index]); 439 } 440 441 static struct mv643xx_eth_private *txq_to_mp(struct tx_queue *txq) 442 { 443 return container_of(txq, struct mv643xx_eth_private, txq[txq->index]); 444 } 445 446 static void rxq_enable(struct rx_queue *rxq) 447 { 448 struct mv643xx_eth_private *mp = rxq_to_mp(rxq); 449 wrlp(mp, RXQ_COMMAND, 1 << rxq->index); 450 } 451 452 static void rxq_disable(struct rx_queue *rxq) 453 { 454 struct mv643xx_eth_private *mp = rxq_to_mp(rxq); 455 u8 mask = 1 << rxq->index; 456 457 wrlp(mp, RXQ_COMMAND, mask << 8); 458 while (rdlp(mp, RXQ_COMMAND) & mask) 459 udelay(10); 460 } 461 462 static void txq_reset_hw_ptr(struct tx_queue *txq) 463 { 464 struct mv643xx_eth_private *mp = txq_to_mp(txq); 465 u32 addr; 466 467 addr = (u32)txq->tx_desc_dma; 468 addr += txq->tx_curr_desc * sizeof(struct tx_desc); 469 wrlp(mp, TXQ_CURRENT_DESC_PTR(txq->index), addr); 470 } 471 472 static void txq_enable(struct tx_queue *txq) 473 { 474 struct mv643xx_eth_private *mp = txq_to_mp(txq); 475 wrlp(mp, TXQ_COMMAND, 1 << txq->index); 476 } 477 478 static void txq_disable(struct tx_queue *txq) 479 { 480 struct mv643xx_eth_private *mp = txq_to_mp(txq); 481 u8 mask = 1 << txq->index; 482 483 wrlp(mp, TXQ_COMMAND, mask << 8); 484 while (rdlp(mp, TXQ_COMMAND) & mask) 485 udelay(10); 486 } 487 488 static void txq_maybe_wake(struct tx_queue *txq) 489 { 490 struct mv643xx_eth_private *mp = txq_to_mp(txq); 491 struct netdev_queue *nq = netdev_get_tx_queue(mp->dev, txq->index); 492 493 if (netif_tx_queue_stopped(nq)) { 494 __netif_tx_lock(nq, smp_processor_id()); 495 if (txq->tx_ring_size - txq->tx_desc_count >= MAX_SKB_FRAGS + 1) 496 netif_tx_wake_queue(nq); 497 __netif_tx_unlock(nq); 498 } 499 } 500 501 static int rxq_process(struct rx_queue *rxq, int budget) 502 { 503 struct mv643xx_eth_private *mp = rxq_to_mp(rxq); 504 struct net_device_stats *stats = &mp->dev->stats; 505 int rx; 506 507 rx = 0; 508 while (rx < budget && rxq->rx_desc_count) { 509 struct rx_desc *rx_desc; 510 unsigned int cmd_sts; 511 struct sk_buff *skb; 512 u16 byte_cnt; 513 514 rx_desc = &rxq->rx_desc_area[rxq->rx_curr_desc]; 515 516 cmd_sts = rx_desc->cmd_sts; 517 if (cmd_sts & BUFFER_OWNED_BY_DMA) 518 break; 519 rmb(); 520 521 skb = rxq->rx_skb[rxq->rx_curr_desc]; 522 rxq->rx_skb[rxq->rx_curr_desc] = NULL; 523 524 rxq->rx_curr_desc++; 525 if (rxq->rx_curr_desc == rxq->rx_ring_size) 526 rxq->rx_curr_desc = 0; 527 528 dma_unmap_single(mp->dev->dev.parent, rx_desc->buf_ptr, 529 rx_desc->buf_size, DMA_FROM_DEVICE); 530 rxq->rx_desc_count--; 531 rx++; 532 533 mp->work_rx_refill |= 1 << rxq->index; 534 535 byte_cnt = rx_desc->byte_cnt; 536 537 /* 538 * Update statistics. 539 * 540 * Note that the descriptor byte count includes 2 dummy 541 * bytes automatically inserted by the hardware at the 542 * start of the packet (which we don't count), and a 4 543 * byte CRC at the end of the packet (which we do count). 544 */ 545 stats->rx_packets++; 546 stats->rx_bytes += byte_cnt - 2; 547 548 /* 549 * In case we received a packet without first / last bits 550 * on, or the error summary bit is set, the packet needs 551 * to be dropped. 552 */ 553 if ((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC | ERROR_SUMMARY)) 554 != (RX_FIRST_DESC | RX_LAST_DESC)) 555 goto err; 556 557 /* 558 * The -4 is for the CRC in the trailer of the 559 * received packet 560 */ 561 skb_put(skb, byte_cnt - 2 - 4); 562 563 if (cmd_sts & LAYER_4_CHECKSUM_OK) 564 skb->ip_summed = CHECKSUM_UNNECESSARY; 565 skb->protocol = eth_type_trans(skb, mp->dev); 566 567 napi_gro_receive(&mp->napi, skb); 568 569 continue; 570 571 err: 572 stats->rx_dropped++; 573 574 if ((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC)) != 575 (RX_FIRST_DESC | RX_LAST_DESC)) { 576 if (net_ratelimit()) 577 netdev_err(mp->dev, 578 "received packet spanning multiple descriptors\n"); 579 } 580 581 if (cmd_sts & ERROR_SUMMARY) 582 stats->rx_errors++; 583 584 dev_kfree_skb(skb); 585 } 586 587 if (rx < budget) 588 mp->work_rx &= ~(1 << rxq->index); 589 590 return rx; 591 } 592 593 static int rxq_refill(struct rx_queue *rxq, int budget) 594 { 595 struct mv643xx_eth_private *mp = rxq_to_mp(rxq); 596 int refilled; 597 598 refilled = 0; 599 while (refilled < budget && rxq->rx_desc_count < rxq->rx_ring_size) { 600 struct sk_buff *skb; 601 int rx; 602 struct rx_desc *rx_desc; 603 int size; 604 605 skb = netdev_alloc_skb(mp->dev, mp->skb_size); 606 607 if (skb == NULL) { 608 mp->oom = 1; 609 goto oom; 610 } 611 612 if (SKB_DMA_REALIGN) 613 skb_reserve(skb, SKB_DMA_REALIGN); 614 615 refilled++; 616 rxq->rx_desc_count++; 617 618 rx = rxq->rx_used_desc++; 619 if (rxq->rx_used_desc == rxq->rx_ring_size) 620 rxq->rx_used_desc = 0; 621 622 rx_desc = rxq->rx_desc_area + rx; 623 624 size = skb_end_pointer(skb) - skb->data; 625 rx_desc->buf_ptr = dma_map_single(mp->dev->dev.parent, 626 skb->data, size, 627 DMA_FROM_DEVICE); 628 rx_desc->buf_size = size; 629 rxq->rx_skb[rx] = skb; 630 wmb(); 631 rx_desc->cmd_sts = BUFFER_OWNED_BY_DMA | RX_ENABLE_INTERRUPT; 632 wmb(); 633 634 /* 635 * The hardware automatically prepends 2 bytes of 636 * dummy data to each received packet, so that the 637 * IP header ends up 16-byte aligned. 638 */ 639 skb_reserve(skb, 2); 640 } 641 642 if (refilled < budget) 643 mp->work_rx_refill &= ~(1 << rxq->index); 644 645 oom: 646 return refilled; 647 } 648 649 650 /* tx ***********************************************************************/ 651 static inline unsigned int has_tiny_unaligned_frags(struct sk_buff *skb) 652 { 653 int frag; 654 655 for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) { 656 const skb_frag_t *fragp = &skb_shinfo(skb)->frags[frag]; 657 658 if (skb_frag_size(fragp) <= 8 && fragp->page_offset & 7) 659 return 1; 660 } 661 662 return 0; 663 } 664 665 static void txq_submit_frag_skb(struct tx_queue *txq, struct sk_buff *skb) 666 { 667 struct mv643xx_eth_private *mp = txq_to_mp(txq); 668 int nr_frags = skb_shinfo(skb)->nr_frags; 669 int frag; 670 671 for (frag = 0; frag < nr_frags; frag++) { 672 skb_frag_t *this_frag; 673 int tx_index; 674 struct tx_desc *desc; 675 676 this_frag = &skb_shinfo(skb)->frags[frag]; 677 tx_index = txq->tx_curr_desc++; 678 if (txq->tx_curr_desc == txq->tx_ring_size) 679 txq->tx_curr_desc = 0; 680 desc = &txq->tx_desc_area[tx_index]; 681 682 /* 683 * The last fragment will generate an interrupt 684 * which will free the skb on TX completion. 685 */ 686 if (frag == nr_frags - 1) { 687 desc->cmd_sts = BUFFER_OWNED_BY_DMA | 688 ZERO_PADDING | TX_LAST_DESC | 689 TX_ENABLE_INTERRUPT; 690 } else { 691 desc->cmd_sts = BUFFER_OWNED_BY_DMA; 692 } 693 694 desc->l4i_chk = 0; 695 desc->byte_cnt = skb_frag_size(this_frag); 696 desc->buf_ptr = skb_frag_dma_map(mp->dev->dev.parent, 697 this_frag, 0, 698 skb_frag_size(this_frag), 699 DMA_TO_DEVICE); 700 } 701 } 702 703 static inline __be16 sum16_as_be(__sum16 sum) 704 { 705 return (__force __be16)sum; 706 } 707 708 static int txq_submit_skb(struct tx_queue *txq, struct sk_buff *skb) 709 { 710 struct mv643xx_eth_private *mp = txq_to_mp(txq); 711 int nr_frags = skb_shinfo(skb)->nr_frags; 712 int tx_index; 713 struct tx_desc *desc; 714 u32 cmd_sts; 715 u16 l4i_chk; 716 int length; 717 718 cmd_sts = TX_FIRST_DESC | GEN_CRC | BUFFER_OWNED_BY_DMA; 719 l4i_chk = 0; 720 721 if (skb->ip_summed == CHECKSUM_PARTIAL) { 722 int hdr_len; 723 int tag_bytes; 724 725 BUG_ON(skb->protocol != htons(ETH_P_IP) && 726 skb->protocol != htons(ETH_P_8021Q)); 727 728 hdr_len = (void *)ip_hdr(skb) - (void *)skb->data; 729 tag_bytes = hdr_len - ETH_HLEN; 730 if (skb->len - hdr_len > mp->shared->tx_csum_limit || 731 unlikely(tag_bytes & ~12)) { 732 if (skb_checksum_help(skb) == 0) 733 goto no_csum; 734 kfree_skb(skb); 735 return 1; 736 } 737 738 if (tag_bytes & 4) 739 cmd_sts |= MAC_HDR_EXTRA_4_BYTES; 740 if (tag_bytes & 8) 741 cmd_sts |= MAC_HDR_EXTRA_8_BYTES; 742 743 cmd_sts |= GEN_TCP_UDP_CHECKSUM | 744 GEN_IP_V4_CHECKSUM | 745 ip_hdr(skb)->ihl << TX_IHL_SHIFT; 746 747 switch (ip_hdr(skb)->protocol) { 748 case IPPROTO_UDP: 749 cmd_sts |= UDP_FRAME; 750 l4i_chk = ntohs(sum16_as_be(udp_hdr(skb)->check)); 751 break; 752 case IPPROTO_TCP: 753 l4i_chk = ntohs(sum16_as_be(tcp_hdr(skb)->check)); 754 break; 755 default: 756 BUG(); 757 } 758 } else { 759 no_csum: 760 /* Errata BTS #50, IHL must be 5 if no HW checksum */ 761 cmd_sts |= 5 << TX_IHL_SHIFT; 762 } 763 764 tx_index = txq->tx_curr_desc++; 765 if (txq->tx_curr_desc == txq->tx_ring_size) 766 txq->tx_curr_desc = 0; 767 desc = &txq->tx_desc_area[tx_index]; 768 769 if (nr_frags) { 770 txq_submit_frag_skb(txq, skb); 771 length = skb_headlen(skb); 772 } else { 773 cmd_sts |= ZERO_PADDING | TX_LAST_DESC | TX_ENABLE_INTERRUPT; 774 length = skb->len; 775 } 776 777 desc->l4i_chk = l4i_chk; 778 desc->byte_cnt = length; 779 desc->buf_ptr = dma_map_single(mp->dev->dev.parent, skb->data, 780 length, DMA_TO_DEVICE); 781 782 __skb_queue_tail(&txq->tx_skb, skb); 783 784 skb_tx_timestamp(skb); 785 786 /* ensure all other descriptors are written before first cmd_sts */ 787 wmb(); 788 desc->cmd_sts = cmd_sts; 789 790 /* clear TX_END status */ 791 mp->work_tx_end &= ~(1 << txq->index); 792 793 /* ensure all descriptors are written before poking hardware */ 794 wmb(); 795 txq_enable(txq); 796 797 txq->tx_desc_count += nr_frags + 1; 798 799 return 0; 800 } 801 802 static netdev_tx_t mv643xx_eth_xmit(struct sk_buff *skb, struct net_device *dev) 803 { 804 struct mv643xx_eth_private *mp = netdev_priv(dev); 805 int length, queue; 806 struct tx_queue *txq; 807 struct netdev_queue *nq; 808 809 queue = skb_get_queue_mapping(skb); 810 txq = mp->txq + queue; 811 nq = netdev_get_tx_queue(dev, queue); 812 813 if (has_tiny_unaligned_frags(skb) && __skb_linearize(skb)) { 814 txq->tx_dropped++; 815 netdev_printk(KERN_DEBUG, dev, 816 "failed to linearize skb with tiny unaligned fragment\n"); 817 return NETDEV_TX_BUSY; 818 } 819 820 if (txq->tx_ring_size - txq->tx_desc_count < MAX_SKB_FRAGS + 1) { 821 if (net_ratelimit()) 822 netdev_err(dev, "tx queue full?!\n"); 823 kfree_skb(skb); 824 return NETDEV_TX_OK; 825 } 826 827 length = skb->len; 828 829 if (!txq_submit_skb(txq, skb)) { 830 int entries_left; 831 832 txq->tx_bytes += length; 833 txq->tx_packets++; 834 835 entries_left = txq->tx_ring_size - txq->tx_desc_count; 836 if (entries_left < MAX_SKB_FRAGS + 1) 837 netif_tx_stop_queue(nq); 838 } 839 840 return NETDEV_TX_OK; 841 } 842 843 844 /* tx napi ******************************************************************/ 845 static void txq_kick(struct tx_queue *txq) 846 { 847 struct mv643xx_eth_private *mp = txq_to_mp(txq); 848 struct netdev_queue *nq = netdev_get_tx_queue(mp->dev, txq->index); 849 u32 hw_desc_ptr; 850 u32 expected_ptr; 851 852 __netif_tx_lock(nq, smp_processor_id()); 853 854 if (rdlp(mp, TXQ_COMMAND) & (1 << txq->index)) 855 goto out; 856 857 hw_desc_ptr = rdlp(mp, TXQ_CURRENT_DESC_PTR(txq->index)); 858 expected_ptr = (u32)txq->tx_desc_dma + 859 txq->tx_curr_desc * sizeof(struct tx_desc); 860 861 if (hw_desc_ptr != expected_ptr) 862 txq_enable(txq); 863 864 out: 865 __netif_tx_unlock(nq); 866 867 mp->work_tx_end &= ~(1 << txq->index); 868 } 869 870 static int txq_reclaim(struct tx_queue *txq, int budget, int force) 871 { 872 struct mv643xx_eth_private *mp = txq_to_mp(txq); 873 struct netdev_queue *nq = netdev_get_tx_queue(mp->dev, txq->index); 874 int reclaimed; 875 876 __netif_tx_lock_bh(nq); 877 878 reclaimed = 0; 879 while (reclaimed < budget && txq->tx_desc_count > 0) { 880 int tx_index; 881 struct tx_desc *desc; 882 u32 cmd_sts; 883 struct sk_buff *skb; 884 885 tx_index = txq->tx_used_desc; 886 desc = &txq->tx_desc_area[tx_index]; 887 cmd_sts = desc->cmd_sts; 888 889 if (cmd_sts & BUFFER_OWNED_BY_DMA) { 890 if (!force) 891 break; 892 desc->cmd_sts = cmd_sts & ~BUFFER_OWNED_BY_DMA; 893 } 894 895 txq->tx_used_desc = tx_index + 1; 896 if (txq->tx_used_desc == txq->tx_ring_size) 897 txq->tx_used_desc = 0; 898 899 reclaimed++; 900 txq->tx_desc_count--; 901 902 skb = NULL; 903 if (cmd_sts & TX_LAST_DESC) 904 skb = __skb_dequeue(&txq->tx_skb); 905 906 if (cmd_sts & ERROR_SUMMARY) { 907 netdev_info(mp->dev, "tx error\n"); 908 mp->dev->stats.tx_errors++; 909 } 910 911 if (cmd_sts & TX_FIRST_DESC) { 912 dma_unmap_single(mp->dev->dev.parent, desc->buf_ptr, 913 desc->byte_cnt, DMA_TO_DEVICE); 914 } else { 915 dma_unmap_page(mp->dev->dev.parent, desc->buf_ptr, 916 desc->byte_cnt, DMA_TO_DEVICE); 917 } 918 919 dev_kfree_skb(skb); 920 } 921 922 __netif_tx_unlock_bh(nq); 923 924 if (reclaimed < budget) 925 mp->work_tx &= ~(1 << txq->index); 926 927 return reclaimed; 928 } 929 930 931 /* tx rate control **********************************************************/ 932 /* 933 * Set total maximum TX rate (shared by all TX queues for this port) 934 * to 'rate' bits per second, with a maximum burst of 'burst' bytes. 935 */ 936 static void tx_set_rate(struct mv643xx_eth_private *mp, int rate, int burst) 937 { 938 int token_rate; 939 int mtu; 940 int bucket_size; 941 942 token_rate = ((rate / 1000) * 64) / (mp->t_clk / 1000); 943 if (token_rate > 1023) 944 token_rate = 1023; 945 946 mtu = (mp->dev->mtu + 255) >> 8; 947 if (mtu > 63) 948 mtu = 63; 949 950 bucket_size = (burst + 255) >> 8; 951 if (bucket_size > 65535) 952 bucket_size = 65535; 953 954 switch (mp->shared->tx_bw_control) { 955 case TX_BW_CONTROL_OLD_LAYOUT: 956 wrlp(mp, TX_BW_RATE, token_rate); 957 wrlp(mp, TX_BW_MTU, mtu); 958 wrlp(mp, TX_BW_BURST, bucket_size); 959 break; 960 case TX_BW_CONTROL_NEW_LAYOUT: 961 wrlp(mp, TX_BW_RATE_MOVED, token_rate); 962 wrlp(mp, TX_BW_MTU_MOVED, mtu); 963 wrlp(mp, TX_BW_BURST_MOVED, bucket_size); 964 break; 965 } 966 } 967 968 static void txq_set_rate(struct tx_queue *txq, int rate, int burst) 969 { 970 struct mv643xx_eth_private *mp = txq_to_mp(txq); 971 int token_rate; 972 int bucket_size; 973 974 token_rate = ((rate / 1000) * 64) / (mp->t_clk / 1000); 975 if (token_rate > 1023) 976 token_rate = 1023; 977 978 bucket_size = (burst + 255) >> 8; 979 if (bucket_size > 65535) 980 bucket_size = 65535; 981 982 wrlp(mp, TXQ_BW_TOKENS(txq->index), token_rate << 14); 983 wrlp(mp, TXQ_BW_CONF(txq->index), (bucket_size << 10) | token_rate); 984 } 985 986 static void txq_set_fixed_prio_mode(struct tx_queue *txq) 987 { 988 struct mv643xx_eth_private *mp = txq_to_mp(txq); 989 int off; 990 u32 val; 991 992 /* 993 * Turn on fixed priority mode. 994 */ 995 off = 0; 996 switch (mp->shared->tx_bw_control) { 997 case TX_BW_CONTROL_OLD_LAYOUT: 998 off = TXQ_FIX_PRIO_CONF; 999 break; 1000 case TX_BW_CONTROL_NEW_LAYOUT: 1001 off = TXQ_FIX_PRIO_CONF_MOVED; 1002 break; 1003 } 1004 1005 if (off) { 1006 val = rdlp(mp, off); 1007 val |= 1 << txq->index; 1008 wrlp(mp, off, val); 1009 } 1010 } 1011 1012 1013 /* mii management interface *************************************************/ 1014 static void mv643xx_adjust_pscr(struct mv643xx_eth_private *mp) 1015 { 1016 u32 pscr = rdlp(mp, PORT_SERIAL_CONTROL); 1017 u32 autoneg_disable = FORCE_LINK_PASS | 1018 DISABLE_AUTO_NEG_SPEED_GMII | 1019 DISABLE_AUTO_NEG_FOR_FLOW_CTRL | 1020 DISABLE_AUTO_NEG_FOR_DUPLEX; 1021 1022 if (mp->phy->autoneg == AUTONEG_ENABLE) { 1023 /* enable auto negotiation */ 1024 pscr &= ~autoneg_disable; 1025 goto out_write; 1026 } 1027 1028 pscr |= autoneg_disable; 1029 1030 if (mp->phy->speed == SPEED_1000) { 1031 /* force gigabit, half duplex not supported */ 1032 pscr |= SET_GMII_SPEED_TO_1000; 1033 pscr |= SET_FULL_DUPLEX_MODE; 1034 goto out_write; 1035 } 1036 1037 pscr &= ~SET_GMII_SPEED_TO_1000; 1038 1039 if (mp->phy->speed == SPEED_100) 1040 pscr |= SET_MII_SPEED_TO_100; 1041 else 1042 pscr &= ~SET_MII_SPEED_TO_100; 1043 1044 if (mp->phy->duplex == DUPLEX_FULL) 1045 pscr |= SET_FULL_DUPLEX_MODE; 1046 else 1047 pscr &= ~SET_FULL_DUPLEX_MODE; 1048 1049 out_write: 1050 wrlp(mp, PORT_SERIAL_CONTROL, pscr); 1051 } 1052 1053 /* statistics ***************************************************************/ 1054 static struct net_device_stats *mv643xx_eth_get_stats(struct net_device *dev) 1055 { 1056 struct mv643xx_eth_private *mp = netdev_priv(dev); 1057 struct net_device_stats *stats = &dev->stats; 1058 unsigned long tx_packets = 0; 1059 unsigned long tx_bytes = 0; 1060 unsigned long tx_dropped = 0; 1061 int i; 1062 1063 for (i = 0; i < mp->txq_count; i++) { 1064 struct tx_queue *txq = mp->txq + i; 1065 1066 tx_packets += txq->tx_packets; 1067 tx_bytes += txq->tx_bytes; 1068 tx_dropped += txq->tx_dropped; 1069 } 1070 1071 stats->tx_packets = tx_packets; 1072 stats->tx_bytes = tx_bytes; 1073 stats->tx_dropped = tx_dropped; 1074 1075 return stats; 1076 } 1077 1078 static inline u32 mib_read(struct mv643xx_eth_private *mp, int offset) 1079 { 1080 return rdl(mp, MIB_COUNTERS(mp->port_num) + offset); 1081 } 1082 1083 static void mib_counters_clear(struct mv643xx_eth_private *mp) 1084 { 1085 int i; 1086 1087 for (i = 0; i < 0x80; i += 4) 1088 mib_read(mp, i); 1089 1090 /* Clear non MIB hw counters also */ 1091 rdlp(mp, RX_DISCARD_FRAME_CNT); 1092 rdlp(mp, RX_OVERRUN_FRAME_CNT); 1093 } 1094 1095 static void mib_counters_update(struct mv643xx_eth_private *mp) 1096 { 1097 struct mib_counters *p = &mp->mib_counters; 1098 1099 spin_lock_bh(&mp->mib_counters_lock); 1100 p->good_octets_received += mib_read(mp, 0x00); 1101 p->bad_octets_received += mib_read(mp, 0x08); 1102 p->internal_mac_transmit_err += mib_read(mp, 0x0c); 1103 p->good_frames_received += mib_read(mp, 0x10); 1104 p->bad_frames_received += mib_read(mp, 0x14); 1105 p->broadcast_frames_received += mib_read(mp, 0x18); 1106 p->multicast_frames_received += mib_read(mp, 0x1c); 1107 p->frames_64_octets += mib_read(mp, 0x20); 1108 p->frames_65_to_127_octets += mib_read(mp, 0x24); 1109 p->frames_128_to_255_octets += mib_read(mp, 0x28); 1110 p->frames_256_to_511_octets += mib_read(mp, 0x2c); 1111 p->frames_512_to_1023_octets += mib_read(mp, 0x30); 1112 p->frames_1024_to_max_octets += mib_read(mp, 0x34); 1113 p->good_octets_sent += mib_read(mp, 0x38); 1114 p->good_frames_sent += mib_read(mp, 0x40); 1115 p->excessive_collision += mib_read(mp, 0x44); 1116 p->multicast_frames_sent += mib_read(mp, 0x48); 1117 p->broadcast_frames_sent += mib_read(mp, 0x4c); 1118 p->unrec_mac_control_received += mib_read(mp, 0x50); 1119 p->fc_sent += mib_read(mp, 0x54); 1120 p->good_fc_received += mib_read(mp, 0x58); 1121 p->bad_fc_received += mib_read(mp, 0x5c); 1122 p->undersize_received += mib_read(mp, 0x60); 1123 p->fragments_received += mib_read(mp, 0x64); 1124 p->oversize_received += mib_read(mp, 0x68); 1125 p->jabber_received += mib_read(mp, 0x6c); 1126 p->mac_receive_error += mib_read(mp, 0x70); 1127 p->bad_crc_event += mib_read(mp, 0x74); 1128 p->collision += mib_read(mp, 0x78); 1129 p->late_collision += mib_read(mp, 0x7c); 1130 /* Non MIB hardware counters */ 1131 p->rx_discard += rdlp(mp, RX_DISCARD_FRAME_CNT); 1132 p->rx_overrun += rdlp(mp, RX_OVERRUN_FRAME_CNT); 1133 spin_unlock_bh(&mp->mib_counters_lock); 1134 1135 mod_timer(&mp->mib_counters_timer, jiffies + 30 * HZ); 1136 } 1137 1138 static void mib_counters_timer_wrapper(unsigned long _mp) 1139 { 1140 struct mv643xx_eth_private *mp = (void *)_mp; 1141 1142 mib_counters_update(mp); 1143 } 1144 1145 1146 /* interrupt coalescing *****************************************************/ 1147 /* 1148 * Hardware coalescing parameters are set in units of 64 t_clk 1149 * cycles. I.e.: 1150 * 1151 * coal_delay_in_usec = 64000000 * register_value / t_clk_rate 1152 * 1153 * register_value = coal_delay_in_usec * t_clk_rate / 64000000 1154 * 1155 * In the ->set*() methods, we round the computed register value 1156 * to the nearest integer. 1157 */ 1158 static unsigned int get_rx_coal(struct mv643xx_eth_private *mp) 1159 { 1160 u32 val = rdlp(mp, SDMA_CONFIG); 1161 u64 temp; 1162 1163 if (mp->shared->extended_rx_coal_limit) 1164 temp = ((val & 0x02000000) >> 10) | ((val & 0x003fff80) >> 7); 1165 else 1166 temp = (val & 0x003fff00) >> 8; 1167 1168 temp *= 64000000; 1169 do_div(temp, mp->t_clk); 1170 1171 return (unsigned int)temp; 1172 } 1173 1174 static void set_rx_coal(struct mv643xx_eth_private *mp, unsigned int usec) 1175 { 1176 u64 temp; 1177 u32 val; 1178 1179 temp = (u64)usec * mp->t_clk; 1180 temp += 31999999; 1181 do_div(temp, 64000000); 1182 1183 val = rdlp(mp, SDMA_CONFIG); 1184 if (mp->shared->extended_rx_coal_limit) { 1185 if (temp > 0xffff) 1186 temp = 0xffff; 1187 val &= ~0x023fff80; 1188 val |= (temp & 0x8000) << 10; 1189 val |= (temp & 0x7fff) << 7; 1190 } else { 1191 if (temp > 0x3fff) 1192 temp = 0x3fff; 1193 val &= ~0x003fff00; 1194 val |= (temp & 0x3fff) << 8; 1195 } 1196 wrlp(mp, SDMA_CONFIG, val); 1197 } 1198 1199 static unsigned int get_tx_coal(struct mv643xx_eth_private *mp) 1200 { 1201 u64 temp; 1202 1203 temp = (rdlp(mp, TX_FIFO_URGENT_THRESHOLD) & 0x3fff0) >> 4; 1204 temp *= 64000000; 1205 do_div(temp, mp->t_clk); 1206 1207 return (unsigned int)temp; 1208 } 1209 1210 static void set_tx_coal(struct mv643xx_eth_private *mp, unsigned int usec) 1211 { 1212 u64 temp; 1213 1214 temp = (u64)usec * mp->t_clk; 1215 temp += 31999999; 1216 do_div(temp, 64000000); 1217 1218 if (temp > 0x3fff) 1219 temp = 0x3fff; 1220 1221 wrlp(mp, TX_FIFO_URGENT_THRESHOLD, temp << 4); 1222 } 1223 1224 1225 /* ethtool ******************************************************************/ 1226 struct mv643xx_eth_stats { 1227 char stat_string[ETH_GSTRING_LEN]; 1228 int sizeof_stat; 1229 int netdev_off; 1230 int mp_off; 1231 }; 1232 1233 #define SSTAT(m) \ 1234 { #m, FIELD_SIZEOF(struct net_device_stats, m), \ 1235 offsetof(struct net_device, stats.m), -1 } 1236 1237 #define MIBSTAT(m) \ 1238 { #m, FIELD_SIZEOF(struct mib_counters, m), \ 1239 -1, offsetof(struct mv643xx_eth_private, mib_counters.m) } 1240 1241 static const struct mv643xx_eth_stats mv643xx_eth_stats[] = { 1242 SSTAT(rx_packets), 1243 SSTAT(tx_packets), 1244 SSTAT(rx_bytes), 1245 SSTAT(tx_bytes), 1246 SSTAT(rx_errors), 1247 SSTAT(tx_errors), 1248 SSTAT(rx_dropped), 1249 SSTAT(tx_dropped), 1250 MIBSTAT(good_octets_received), 1251 MIBSTAT(bad_octets_received), 1252 MIBSTAT(internal_mac_transmit_err), 1253 MIBSTAT(good_frames_received), 1254 MIBSTAT(bad_frames_received), 1255 MIBSTAT(broadcast_frames_received), 1256 MIBSTAT(multicast_frames_received), 1257 MIBSTAT(frames_64_octets), 1258 MIBSTAT(frames_65_to_127_octets), 1259 MIBSTAT(frames_128_to_255_octets), 1260 MIBSTAT(frames_256_to_511_octets), 1261 MIBSTAT(frames_512_to_1023_octets), 1262 MIBSTAT(frames_1024_to_max_octets), 1263 MIBSTAT(good_octets_sent), 1264 MIBSTAT(good_frames_sent), 1265 MIBSTAT(excessive_collision), 1266 MIBSTAT(multicast_frames_sent), 1267 MIBSTAT(broadcast_frames_sent), 1268 MIBSTAT(unrec_mac_control_received), 1269 MIBSTAT(fc_sent), 1270 MIBSTAT(good_fc_received), 1271 MIBSTAT(bad_fc_received), 1272 MIBSTAT(undersize_received), 1273 MIBSTAT(fragments_received), 1274 MIBSTAT(oversize_received), 1275 MIBSTAT(jabber_received), 1276 MIBSTAT(mac_receive_error), 1277 MIBSTAT(bad_crc_event), 1278 MIBSTAT(collision), 1279 MIBSTAT(late_collision), 1280 MIBSTAT(rx_discard), 1281 MIBSTAT(rx_overrun), 1282 }; 1283 1284 static int 1285 mv643xx_eth_get_settings_phy(struct mv643xx_eth_private *mp, 1286 struct ethtool_cmd *cmd) 1287 { 1288 int err; 1289 1290 err = phy_read_status(mp->phy); 1291 if (err == 0) 1292 err = phy_ethtool_gset(mp->phy, cmd); 1293 1294 /* 1295 * The MAC does not support 1000baseT_Half. 1296 */ 1297 cmd->supported &= ~SUPPORTED_1000baseT_Half; 1298 cmd->advertising &= ~ADVERTISED_1000baseT_Half; 1299 1300 return err; 1301 } 1302 1303 static int 1304 mv643xx_eth_get_settings_phyless(struct mv643xx_eth_private *mp, 1305 struct ethtool_cmd *cmd) 1306 { 1307 u32 port_status; 1308 1309 port_status = rdlp(mp, PORT_STATUS); 1310 1311 cmd->supported = SUPPORTED_MII; 1312 cmd->advertising = ADVERTISED_MII; 1313 switch (port_status & PORT_SPEED_MASK) { 1314 case PORT_SPEED_10: 1315 ethtool_cmd_speed_set(cmd, SPEED_10); 1316 break; 1317 case PORT_SPEED_100: 1318 ethtool_cmd_speed_set(cmd, SPEED_100); 1319 break; 1320 case PORT_SPEED_1000: 1321 ethtool_cmd_speed_set(cmd, SPEED_1000); 1322 break; 1323 default: 1324 cmd->speed = -1; 1325 break; 1326 } 1327 cmd->duplex = (port_status & FULL_DUPLEX) ? DUPLEX_FULL : DUPLEX_HALF; 1328 cmd->port = PORT_MII; 1329 cmd->phy_address = 0; 1330 cmd->transceiver = XCVR_INTERNAL; 1331 cmd->autoneg = AUTONEG_DISABLE; 1332 cmd->maxtxpkt = 1; 1333 cmd->maxrxpkt = 1; 1334 1335 return 0; 1336 } 1337 1338 static void 1339 mv643xx_eth_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 1340 { 1341 struct mv643xx_eth_private *mp = netdev_priv(dev); 1342 wol->supported = 0; 1343 wol->wolopts = 0; 1344 if (mp->phy) 1345 phy_ethtool_get_wol(mp->phy, wol); 1346 } 1347 1348 static int 1349 mv643xx_eth_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 1350 { 1351 struct mv643xx_eth_private *mp = netdev_priv(dev); 1352 int err; 1353 1354 if (mp->phy == NULL) 1355 return -EOPNOTSUPP; 1356 1357 err = phy_ethtool_set_wol(mp->phy, wol); 1358 /* Given that mv643xx_eth works without the marvell-specific PHY driver, 1359 * this debugging hint is useful to have. 1360 */ 1361 if (err == -EOPNOTSUPP) 1362 netdev_info(dev, "The PHY does not support set_wol, was CONFIG_MARVELL_PHY enabled?\n"); 1363 return err; 1364 } 1365 1366 static int 1367 mv643xx_eth_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) 1368 { 1369 struct mv643xx_eth_private *mp = netdev_priv(dev); 1370 1371 if (mp->phy != NULL) 1372 return mv643xx_eth_get_settings_phy(mp, cmd); 1373 else 1374 return mv643xx_eth_get_settings_phyless(mp, cmd); 1375 } 1376 1377 static int 1378 mv643xx_eth_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) 1379 { 1380 struct mv643xx_eth_private *mp = netdev_priv(dev); 1381 int ret; 1382 1383 if (mp->phy == NULL) 1384 return -EINVAL; 1385 1386 /* 1387 * The MAC does not support 1000baseT_Half. 1388 */ 1389 cmd->advertising &= ~ADVERTISED_1000baseT_Half; 1390 1391 ret = phy_ethtool_sset(mp->phy, cmd); 1392 if (!ret) 1393 mv643xx_adjust_pscr(mp); 1394 return ret; 1395 } 1396 1397 static void mv643xx_eth_get_drvinfo(struct net_device *dev, 1398 struct ethtool_drvinfo *drvinfo) 1399 { 1400 strlcpy(drvinfo->driver, mv643xx_eth_driver_name, 1401 sizeof(drvinfo->driver)); 1402 strlcpy(drvinfo->version, mv643xx_eth_driver_version, 1403 sizeof(drvinfo->version)); 1404 strlcpy(drvinfo->fw_version, "N/A", sizeof(drvinfo->fw_version)); 1405 strlcpy(drvinfo->bus_info, "platform", sizeof(drvinfo->bus_info)); 1406 drvinfo->n_stats = ARRAY_SIZE(mv643xx_eth_stats); 1407 } 1408 1409 static int mv643xx_eth_nway_reset(struct net_device *dev) 1410 { 1411 struct mv643xx_eth_private *mp = netdev_priv(dev); 1412 1413 if (mp->phy == NULL) 1414 return -EINVAL; 1415 1416 return genphy_restart_aneg(mp->phy); 1417 } 1418 1419 static int 1420 mv643xx_eth_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec) 1421 { 1422 struct mv643xx_eth_private *mp = netdev_priv(dev); 1423 1424 ec->rx_coalesce_usecs = get_rx_coal(mp); 1425 ec->tx_coalesce_usecs = get_tx_coal(mp); 1426 1427 return 0; 1428 } 1429 1430 static int 1431 mv643xx_eth_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec) 1432 { 1433 struct mv643xx_eth_private *mp = netdev_priv(dev); 1434 1435 set_rx_coal(mp, ec->rx_coalesce_usecs); 1436 set_tx_coal(mp, ec->tx_coalesce_usecs); 1437 1438 return 0; 1439 } 1440 1441 static void 1442 mv643xx_eth_get_ringparam(struct net_device *dev, struct ethtool_ringparam *er) 1443 { 1444 struct mv643xx_eth_private *mp = netdev_priv(dev); 1445 1446 er->rx_max_pending = 4096; 1447 er->tx_max_pending = 4096; 1448 1449 er->rx_pending = mp->rx_ring_size; 1450 er->tx_pending = mp->tx_ring_size; 1451 } 1452 1453 static int 1454 mv643xx_eth_set_ringparam(struct net_device *dev, struct ethtool_ringparam *er) 1455 { 1456 struct mv643xx_eth_private *mp = netdev_priv(dev); 1457 1458 if (er->rx_mini_pending || er->rx_jumbo_pending) 1459 return -EINVAL; 1460 1461 mp->rx_ring_size = er->rx_pending < 4096 ? er->rx_pending : 4096; 1462 mp->tx_ring_size = er->tx_pending < 4096 ? er->tx_pending : 4096; 1463 1464 if (netif_running(dev)) { 1465 mv643xx_eth_stop(dev); 1466 if (mv643xx_eth_open(dev)) { 1467 netdev_err(dev, 1468 "fatal error on re-opening device after ring param change\n"); 1469 return -ENOMEM; 1470 } 1471 } 1472 1473 return 0; 1474 } 1475 1476 1477 static int 1478 mv643xx_eth_set_features(struct net_device *dev, netdev_features_t features) 1479 { 1480 struct mv643xx_eth_private *mp = netdev_priv(dev); 1481 bool rx_csum = features & NETIF_F_RXCSUM; 1482 1483 wrlp(mp, PORT_CONFIG, rx_csum ? 0x02000000 : 0x00000000); 1484 1485 return 0; 1486 } 1487 1488 static void mv643xx_eth_get_strings(struct net_device *dev, 1489 uint32_t stringset, uint8_t *data) 1490 { 1491 int i; 1492 1493 if (stringset == ETH_SS_STATS) { 1494 for (i = 0; i < ARRAY_SIZE(mv643xx_eth_stats); i++) { 1495 memcpy(data + i * ETH_GSTRING_LEN, 1496 mv643xx_eth_stats[i].stat_string, 1497 ETH_GSTRING_LEN); 1498 } 1499 } 1500 } 1501 1502 static void mv643xx_eth_get_ethtool_stats(struct net_device *dev, 1503 struct ethtool_stats *stats, 1504 uint64_t *data) 1505 { 1506 struct mv643xx_eth_private *mp = netdev_priv(dev); 1507 int i; 1508 1509 mv643xx_eth_get_stats(dev); 1510 mib_counters_update(mp); 1511 1512 for (i = 0; i < ARRAY_SIZE(mv643xx_eth_stats); i++) { 1513 const struct mv643xx_eth_stats *stat; 1514 void *p; 1515 1516 stat = mv643xx_eth_stats + i; 1517 1518 if (stat->netdev_off >= 0) 1519 p = ((void *)mp->dev) + stat->netdev_off; 1520 else 1521 p = ((void *)mp) + stat->mp_off; 1522 1523 data[i] = (stat->sizeof_stat == 8) ? 1524 *(uint64_t *)p : *(uint32_t *)p; 1525 } 1526 } 1527 1528 static int mv643xx_eth_get_sset_count(struct net_device *dev, int sset) 1529 { 1530 if (sset == ETH_SS_STATS) 1531 return ARRAY_SIZE(mv643xx_eth_stats); 1532 1533 return -EOPNOTSUPP; 1534 } 1535 1536 static const struct ethtool_ops mv643xx_eth_ethtool_ops = { 1537 .get_settings = mv643xx_eth_get_settings, 1538 .set_settings = mv643xx_eth_set_settings, 1539 .get_drvinfo = mv643xx_eth_get_drvinfo, 1540 .nway_reset = mv643xx_eth_nway_reset, 1541 .get_link = ethtool_op_get_link, 1542 .get_coalesce = mv643xx_eth_get_coalesce, 1543 .set_coalesce = mv643xx_eth_set_coalesce, 1544 .get_ringparam = mv643xx_eth_get_ringparam, 1545 .set_ringparam = mv643xx_eth_set_ringparam, 1546 .get_strings = mv643xx_eth_get_strings, 1547 .get_ethtool_stats = mv643xx_eth_get_ethtool_stats, 1548 .get_sset_count = mv643xx_eth_get_sset_count, 1549 .get_ts_info = ethtool_op_get_ts_info, 1550 .get_wol = mv643xx_eth_get_wol, 1551 .set_wol = mv643xx_eth_set_wol, 1552 }; 1553 1554 1555 /* address handling *********************************************************/ 1556 static void uc_addr_get(struct mv643xx_eth_private *mp, unsigned char *addr) 1557 { 1558 unsigned int mac_h = rdlp(mp, MAC_ADDR_HIGH); 1559 unsigned int mac_l = rdlp(mp, MAC_ADDR_LOW); 1560 1561 addr[0] = (mac_h >> 24) & 0xff; 1562 addr[1] = (mac_h >> 16) & 0xff; 1563 addr[2] = (mac_h >> 8) & 0xff; 1564 addr[3] = mac_h & 0xff; 1565 addr[4] = (mac_l >> 8) & 0xff; 1566 addr[5] = mac_l & 0xff; 1567 } 1568 1569 static void uc_addr_set(struct mv643xx_eth_private *mp, unsigned char *addr) 1570 { 1571 wrlp(mp, MAC_ADDR_HIGH, 1572 (addr[0] << 24) | (addr[1] << 16) | (addr[2] << 8) | addr[3]); 1573 wrlp(mp, MAC_ADDR_LOW, (addr[4] << 8) | addr[5]); 1574 } 1575 1576 static u32 uc_addr_filter_mask(struct net_device *dev) 1577 { 1578 struct netdev_hw_addr *ha; 1579 u32 nibbles; 1580 1581 if (dev->flags & IFF_PROMISC) 1582 return 0; 1583 1584 nibbles = 1 << (dev->dev_addr[5] & 0x0f); 1585 netdev_for_each_uc_addr(ha, dev) { 1586 if (memcmp(dev->dev_addr, ha->addr, 5)) 1587 return 0; 1588 if ((dev->dev_addr[5] ^ ha->addr[5]) & 0xf0) 1589 return 0; 1590 1591 nibbles |= 1 << (ha->addr[5] & 0x0f); 1592 } 1593 1594 return nibbles; 1595 } 1596 1597 static void mv643xx_eth_program_unicast_filter(struct net_device *dev) 1598 { 1599 struct mv643xx_eth_private *mp = netdev_priv(dev); 1600 u32 port_config; 1601 u32 nibbles; 1602 int i; 1603 1604 uc_addr_set(mp, dev->dev_addr); 1605 1606 port_config = rdlp(mp, PORT_CONFIG) & ~UNICAST_PROMISCUOUS_MODE; 1607 1608 nibbles = uc_addr_filter_mask(dev); 1609 if (!nibbles) { 1610 port_config |= UNICAST_PROMISCUOUS_MODE; 1611 nibbles = 0xffff; 1612 } 1613 1614 for (i = 0; i < 16; i += 4) { 1615 int off = UNICAST_TABLE(mp->port_num) + i; 1616 u32 v; 1617 1618 v = 0; 1619 if (nibbles & 1) 1620 v |= 0x00000001; 1621 if (nibbles & 2) 1622 v |= 0x00000100; 1623 if (nibbles & 4) 1624 v |= 0x00010000; 1625 if (nibbles & 8) 1626 v |= 0x01000000; 1627 nibbles >>= 4; 1628 1629 wrl(mp, off, v); 1630 } 1631 1632 wrlp(mp, PORT_CONFIG, port_config); 1633 } 1634 1635 static int addr_crc(unsigned char *addr) 1636 { 1637 int crc = 0; 1638 int i; 1639 1640 for (i = 0; i < 6; i++) { 1641 int j; 1642 1643 crc = (crc ^ addr[i]) << 8; 1644 for (j = 7; j >= 0; j--) { 1645 if (crc & (0x100 << j)) 1646 crc ^= 0x107 << j; 1647 } 1648 } 1649 1650 return crc; 1651 } 1652 1653 static void mv643xx_eth_program_multicast_filter(struct net_device *dev) 1654 { 1655 struct mv643xx_eth_private *mp = netdev_priv(dev); 1656 u32 *mc_spec; 1657 u32 *mc_other; 1658 struct netdev_hw_addr *ha; 1659 int i; 1660 1661 if (dev->flags & (IFF_PROMISC | IFF_ALLMULTI)) { 1662 int port_num; 1663 u32 accept; 1664 1665 oom: 1666 port_num = mp->port_num; 1667 accept = 0x01010101; 1668 for (i = 0; i < 0x100; i += 4) { 1669 wrl(mp, SPECIAL_MCAST_TABLE(port_num) + i, accept); 1670 wrl(mp, OTHER_MCAST_TABLE(port_num) + i, accept); 1671 } 1672 return; 1673 } 1674 1675 mc_spec = kmalloc(0x200, GFP_ATOMIC); 1676 if (mc_spec == NULL) 1677 goto oom; 1678 mc_other = mc_spec + (0x100 >> 2); 1679 1680 memset(mc_spec, 0, 0x100); 1681 memset(mc_other, 0, 0x100); 1682 1683 netdev_for_each_mc_addr(ha, dev) { 1684 u8 *a = ha->addr; 1685 u32 *table; 1686 int entry; 1687 1688 if (memcmp(a, "\x01\x00\x5e\x00\x00", 5) == 0) { 1689 table = mc_spec; 1690 entry = a[5]; 1691 } else { 1692 table = mc_other; 1693 entry = addr_crc(a); 1694 } 1695 1696 table[entry >> 2] |= 1 << (8 * (entry & 3)); 1697 } 1698 1699 for (i = 0; i < 0x100; i += 4) { 1700 wrl(mp, SPECIAL_MCAST_TABLE(mp->port_num) + i, mc_spec[i >> 2]); 1701 wrl(mp, OTHER_MCAST_TABLE(mp->port_num) + i, mc_other[i >> 2]); 1702 } 1703 1704 kfree(mc_spec); 1705 } 1706 1707 static void mv643xx_eth_set_rx_mode(struct net_device *dev) 1708 { 1709 mv643xx_eth_program_unicast_filter(dev); 1710 mv643xx_eth_program_multicast_filter(dev); 1711 } 1712 1713 static int mv643xx_eth_set_mac_address(struct net_device *dev, void *addr) 1714 { 1715 struct sockaddr *sa = addr; 1716 1717 if (!is_valid_ether_addr(sa->sa_data)) 1718 return -EADDRNOTAVAIL; 1719 1720 memcpy(dev->dev_addr, sa->sa_data, ETH_ALEN); 1721 1722 netif_addr_lock_bh(dev); 1723 mv643xx_eth_program_unicast_filter(dev); 1724 netif_addr_unlock_bh(dev); 1725 1726 return 0; 1727 } 1728 1729 1730 /* rx/tx queue initialisation ***********************************************/ 1731 static int rxq_init(struct mv643xx_eth_private *mp, int index) 1732 { 1733 struct rx_queue *rxq = mp->rxq + index; 1734 struct rx_desc *rx_desc; 1735 int size; 1736 int i; 1737 1738 rxq->index = index; 1739 1740 rxq->rx_ring_size = mp->rx_ring_size; 1741 1742 rxq->rx_desc_count = 0; 1743 rxq->rx_curr_desc = 0; 1744 rxq->rx_used_desc = 0; 1745 1746 size = rxq->rx_ring_size * sizeof(struct rx_desc); 1747 1748 if (index == 0 && size <= mp->rx_desc_sram_size) { 1749 rxq->rx_desc_area = ioremap(mp->rx_desc_sram_addr, 1750 mp->rx_desc_sram_size); 1751 rxq->rx_desc_dma = mp->rx_desc_sram_addr; 1752 } else { 1753 rxq->rx_desc_area = dma_alloc_coherent(mp->dev->dev.parent, 1754 size, &rxq->rx_desc_dma, 1755 GFP_KERNEL); 1756 } 1757 1758 if (rxq->rx_desc_area == NULL) { 1759 netdev_err(mp->dev, 1760 "can't allocate rx ring (%d bytes)\n", size); 1761 goto out; 1762 } 1763 memset(rxq->rx_desc_area, 0, size); 1764 1765 rxq->rx_desc_area_size = size; 1766 rxq->rx_skb = kcalloc(rxq->rx_ring_size, sizeof(*rxq->rx_skb), 1767 GFP_KERNEL); 1768 if (rxq->rx_skb == NULL) 1769 goto out_free; 1770 1771 rx_desc = rxq->rx_desc_area; 1772 for (i = 0; i < rxq->rx_ring_size; i++) { 1773 int nexti; 1774 1775 nexti = i + 1; 1776 if (nexti == rxq->rx_ring_size) 1777 nexti = 0; 1778 1779 rx_desc[i].next_desc_ptr = rxq->rx_desc_dma + 1780 nexti * sizeof(struct rx_desc); 1781 } 1782 1783 return 0; 1784 1785 1786 out_free: 1787 if (index == 0 && size <= mp->rx_desc_sram_size) 1788 iounmap(rxq->rx_desc_area); 1789 else 1790 dma_free_coherent(mp->dev->dev.parent, size, 1791 rxq->rx_desc_area, 1792 rxq->rx_desc_dma); 1793 1794 out: 1795 return -ENOMEM; 1796 } 1797 1798 static void rxq_deinit(struct rx_queue *rxq) 1799 { 1800 struct mv643xx_eth_private *mp = rxq_to_mp(rxq); 1801 int i; 1802 1803 rxq_disable(rxq); 1804 1805 for (i = 0; i < rxq->rx_ring_size; i++) { 1806 if (rxq->rx_skb[i]) { 1807 dev_kfree_skb(rxq->rx_skb[i]); 1808 rxq->rx_desc_count--; 1809 } 1810 } 1811 1812 if (rxq->rx_desc_count) { 1813 netdev_err(mp->dev, "error freeing rx ring -- %d skbs stuck\n", 1814 rxq->rx_desc_count); 1815 } 1816 1817 if (rxq->index == 0 && 1818 rxq->rx_desc_area_size <= mp->rx_desc_sram_size) 1819 iounmap(rxq->rx_desc_area); 1820 else 1821 dma_free_coherent(mp->dev->dev.parent, rxq->rx_desc_area_size, 1822 rxq->rx_desc_area, rxq->rx_desc_dma); 1823 1824 kfree(rxq->rx_skb); 1825 } 1826 1827 static int txq_init(struct mv643xx_eth_private *mp, int index) 1828 { 1829 struct tx_queue *txq = mp->txq + index; 1830 struct tx_desc *tx_desc; 1831 int size; 1832 int i; 1833 1834 txq->index = index; 1835 1836 txq->tx_ring_size = mp->tx_ring_size; 1837 1838 txq->tx_desc_count = 0; 1839 txq->tx_curr_desc = 0; 1840 txq->tx_used_desc = 0; 1841 1842 size = txq->tx_ring_size * sizeof(struct tx_desc); 1843 1844 if (index == 0 && size <= mp->tx_desc_sram_size) { 1845 txq->tx_desc_area = ioremap(mp->tx_desc_sram_addr, 1846 mp->tx_desc_sram_size); 1847 txq->tx_desc_dma = mp->tx_desc_sram_addr; 1848 } else { 1849 txq->tx_desc_area = dma_alloc_coherent(mp->dev->dev.parent, 1850 size, &txq->tx_desc_dma, 1851 GFP_KERNEL); 1852 } 1853 1854 if (txq->tx_desc_area == NULL) { 1855 netdev_err(mp->dev, 1856 "can't allocate tx ring (%d bytes)\n", size); 1857 return -ENOMEM; 1858 } 1859 memset(txq->tx_desc_area, 0, size); 1860 1861 txq->tx_desc_area_size = size; 1862 1863 tx_desc = txq->tx_desc_area; 1864 for (i = 0; i < txq->tx_ring_size; i++) { 1865 struct tx_desc *txd = tx_desc + i; 1866 int nexti; 1867 1868 nexti = i + 1; 1869 if (nexti == txq->tx_ring_size) 1870 nexti = 0; 1871 1872 txd->cmd_sts = 0; 1873 txd->next_desc_ptr = txq->tx_desc_dma + 1874 nexti * sizeof(struct tx_desc); 1875 } 1876 1877 skb_queue_head_init(&txq->tx_skb); 1878 1879 return 0; 1880 } 1881 1882 static void txq_deinit(struct tx_queue *txq) 1883 { 1884 struct mv643xx_eth_private *mp = txq_to_mp(txq); 1885 1886 txq_disable(txq); 1887 txq_reclaim(txq, txq->tx_ring_size, 1); 1888 1889 BUG_ON(txq->tx_used_desc != txq->tx_curr_desc); 1890 1891 if (txq->index == 0 && 1892 txq->tx_desc_area_size <= mp->tx_desc_sram_size) 1893 iounmap(txq->tx_desc_area); 1894 else 1895 dma_free_coherent(mp->dev->dev.parent, txq->tx_desc_area_size, 1896 txq->tx_desc_area, txq->tx_desc_dma); 1897 } 1898 1899 1900 /* netdev ops and related ***************************************************/ 1901 static int mv643xx_eth_collect_events(struct mv643xx_eth_private *mp) 1902 { 1903 u32 int_cause; 1904 u32 int_cause_ext; 1905 1906 int_cause = rdlp(mp, INT_CAUSE) & mp->int_mask; 1907 if (int_cause == 0) 1908 return 0; 1909 1910 int_cause_ext = 0; 1911 if (int_cause & INT_EXT) { 1912 int_cause &= ~INT_EXT; 1913 int_cause_ext = rdlp(mp, INT_CAUSE_EXT); 1914 } 1915 1916 if (int_cause) { 1917 wrlp(mp, INT_CAUSE, ~int_cause); 1918 mp->work_tx_end |= ((int_cause & INT_TX_END) >> 19) & 1919 ~(rdlp(mp, TXQ_COMMAND) & 0xff); 1920 mp->work_rx |= (int_cause & INT_RX) >> 2; 1921 } 1922 1923 int_cause_ext &= INT_EXT_LINK_PHY | INT_EXT_TX; 1924 if (int_cause_ext) { 1925 wrlp(mp, INT_CAUSE_EXT, ~int_cause_ext); 1926 if (int_cause_ext & INT_EXT_LINK_PHY) 1927 mp->work_link = 1; 1928 mp->work_tx |= int_cause_ext & INT_EXT_TX; 1929 } 1930 1931 return 1; 1932 } 1933 1934 static irqreturn_t mv643xx_eth_irq(int irq, void *dev_id) 1935 { 1936 struct net_device *dev = (struct net_device *)dev_id; 1937 struct mv643xx_eth_private *mp = netdev_priv(dev); 1938 1939 if (unlikely(!mv643xx_eth_collect_events(mp))) 1940 return IRQ_NONE; 1941 1942 wrlp(mp, INT_MASK, 0); 1943 napi_schedule(&mp->napi); 1944 1945 return IRQ_HANDLED; 1946 } 1947 1948 static void handle_link_event(struct mv643xx_eth_private *mp) 1949 { 1950 struct net_device *dev = mp->dev; 1951 u32 port_status; 1952 int speed; 1953 int duplex; 1954 int fc; 1955 1956 port_status = rdlp(mp, PORT_STATUS); 1957 if (!(port_status & LINK_UP)) { 1958 if (netif_carrier_ok(dev)) { 1959 int i; 1960 1961 netdev_info(dev, "link down\n"); 1962 1963 netif_carrier_off(dev); 1964 1965 for (i = 0; i < mp->txq_count; i++) { 1966 struct tx_queue *txq = mp->txq + i; 1967 1968 txq_reclaim(txq, txq->tx_ring_size, 1); 1969 txq_reset_hw_ptr(txq); 1970 } 1971 } 1972 return; 1973 } 1974 1975 switch (port_status & PORT_SPEED_MASK) { 1976 case PORT_SPEED_10: 1977 speed = 10; 1978 break; 1979 case PORT_SPEED_100: 1980 speed = 100; 1981 break; 1982 case PORT_SPEED_1000: 1983 speed = 1000; 1984 break; 1985 default: 1986 speed = -1; 1987 break; 1988 } 1989 duplex = (port_status & FULL_DUPLEX) ? 1 : 0; 1990 fc = (port_status & FLOW_CONTROL_ENABLED) ? 1 : 0; 1991 1992 netdev_info(dev, "link up, %d Mb/s, %s duplex, flow control %sabled\n", 1993 speed, duplex ? "full" : "half", fc ? "en" : "dis"); 1994 1995 if (!netif_carrier_ok(dev)) 1996 netif_carrier_on(dev); 1997 } 1998 1999 static int mv643xx_eth_poll(struct napi_struct *napi, int budget) 2000 { 2001 struct mv643xx_eth_private *mp; 2002 int work_done; 2003 2004 mp = container_of(napi, struct mv643xx_eth_private, napi); 2005 2006 if (unlikely(mp->oom)) { 2007 mp->oom = 0; 2008 del_timer(&mp->rx_oom); 2009 } 2010 2011 work_done = 0; 2012 while (work_done < budget) { 2013 u8 queue_mask; 2014 int queue; 2015 int work_tbd; 2016 2017 if (mp->work_link) { 2018 mp->work_link = 0; 2019 handle_link_event(mp); 2020 work_done++; 2021 continue; 2022 } 2023 2024 queue_mask = mp->work_tx | mp->work_tx_end | mp->work_rx; 2025 if (likely(!mp->oom)) 2026 queue_mask |= mp->work_rx_refill; 2027 2028 if (!queue_mask) { 2029 if (mv643xx_eth_collect_events(mp)) 2030 continue; 2031 break; 2032 } 2033 2034 queue = fls(queue_mask) - 1; 2035 queue_mask = 1 << queue; 2036 2037 work_tbd = budget - work_done; 2038 if (work_tbd > 16) 2039 work_tbd = 16; 2040 2041 if (mp->work_tx_end & queue_mask) { 2042 txq_kick(mp->txq + queue); 2043 } else if (mp->work_tx & queue_mask) { 2044 work_done += txq_reclaim(mp->txq + queue, work_tbd, 0); 2045 txq_maybe_wake(mp->txq + queue); 2046 } else if (mp->work_rx & queue_mask) { 2047 work_done += rxq_process(mp->rxq + queue, work_tbd); 2048 } else if (!mp->oom && (mp->work_rx_refill & queue_mask)) { 2049 work_done += rxq_refill(mp->rxq + queue, work_tbd); 2050 } else { 2051 BUG(); 2052 } 2053 } 2054 2055 if (work_done < budget) { 2056 if (mp->oom) 2057 mod_timer(&mp->rx_oom, jiffies + (HZ / 10)); 2058 napi_complete(napi); 2059 wrlp(mp, INT_MASK, mp->int_mask); 2060 } 2061 2062 return work_done; 2063 } 2064 2065 static inline void oom_timer_wrapper(unsigned long data) 2066 { 2067 struct mv643xx_eth_private *mp = (void *)data; 2068 2069 napi_schedule(&mp->napi); 2070 } 2071 2072 static void phy_reset(struct mv643xx_eth_private *mp) 2073 { 2074 int data; 2075 2076 data = phy_read(mp->phy, MII_BMCR); 2077 if (data < 0) 2078 return; 2079 2080 data |= BMCR_RESET; 2081 if (phy_write(mp->phy, MII_BMCR, data) < 0) 2082 return; 2083 2084 do { 2085 data = phy_read(mp->phy, MII_BMCR); 2086 } while (data >= 0 && data & BMCR_RESET); 2087 } 2088 2089 static void port_start(struct mv643xx_eth_private *mp) 2090 { 2091 u32 pscr; 2092 int i; 2093 2094 /* 2095 * Perform PHY reset, if there is a PHY. 2096 */ 2097 if (mp->phy != NULL) { 2098 struct ethtool_cmd cmd; 2099 2100 mv643xx_eth_get_settings(mp->dev, &cmd); 2101 phy_reset(mp); 2102 mv643xx_eth_set_settings(mp->dev, &cmd); 2103 } 2104 2105 /* 2106 * Configure basic link parameters. 2107 */ 2108 pscr = rdlp(mp, PORT_SERIAL_CONTROL); 2109 2110 pscr |= SERIAL_PORT_ENABLE; 2111 wrlp(mp, PORT_SERIAL_CONTROL, pscr); 2112 2113 pscr |= DO_NOT_FORCE_LINK_FAIL; 2114 if (mp->phy == NULL) 2115 pscr |= FORCE_LINK_PASS; 2116 wrlp(mp, PORT_SERIAL_CONTROL, pscr); 2117 2118 /* 2119 * Configure TX path and queues. 2120 */ 2121 tx_set_rate(mp, 1000000000, 16777216); 2122 for (i = 0; i < mp->txq_count; i++) { 2123 struct tx_queue *txq = mp->txq + i; 2124 2125 txq_reset_hw_ptr(txq); 2126 txq_set_rate(txq, 1000000000, 16777216); 2127 txq_set_fixed_prio_mode(txq); 2128 } 2129 2130 /* 2131 * Receive all unmatched unicast, TCP, UDP, BPDU and broadcast 2132 * frames to RX queue #0, and include the pseudo-header when 2133 * calculating receive checksums. 2134 */ 2135 mv643xx_eth_set_features(mp->dev, mp->dev->features); 2136 2137 /* 2138 * Treat BPDUs as normal multicasts, and disable partition mode. 2139 */ 2140 wrlp(mp, PORT_CONFIG_EXT, 0x00000000); 2141 2142 /* 2143 * Add configured unicast addresses to address filter table. 2144 */ 2145 mv643xx_eth_program_unicast_filter(mp->dev); 2146 2147 /* 2148 * Enable the receive queues. 2149 */ 2150 for (i = 0; i < mp->rxq_count; i++) { 2151 struct rx_queue *rxq = mp->rxq + i; 2152 u32 addr; 2153 2154 addr = (u32)rxq->rx_desc_dma; 2155 addr += rxq->rx_curr_desc * sizeof(struct rx_desc); 2156 wrlp(mp, RXQ_CURRENT_DESC_PTR(i), addr); 2157 2158 rxq_enable(rxq); 2159 } 2160 } 2161 2162 static void mv643xx_eth_recalc_skb_size(struct mv643xx_eth_private *mp) 2163 { 2164 int skb_size; 2165 2166 /* 2167 * Reserve 2+14 bytes for an ethernet header (the hardware 2168 * automatically prepends 2 bytes of dummy data to each 2169 * received packet), 16 bytes for up to four VLAN tags, and 2170 * 4 bytes for the trailing FCS -- 36 bytes total. 2171 */ 2172 skb_size = mp->dev->mtu + 36; 2173 2174 /* 2175 * Make sure that the skb size is a multiple of 8 bytes, as 2176 * the lower three bits of the receive descriptor's buffer 2177 * size field are ignored by the hardware. 2178 */ 2179 mp->skb_size = (skb_size + 7) & ~7; 2180 2181 /* 2182 * If NET_SKB_PAD is smaller than a cache line, 2183 * netdev_alloc_skb() will cause skb->data to be misaligned 2184 * to a cache line boundary. If this is the case, include 2185 * some extra space to allow re-aligning the data area. 2186 */ 2187 mp->skb_size += SKB_DMA_REALIGN; 2188 } 2189 2190 static int mv643xx_eth_open(struct net_device *dev) 2191 { 2192 struct mv643xx_eth_private *mp = netdev_priv(dev); 2193 int err; 2194 int i; 2195 2196 wrlp(mp, INT_CAUSE, 0); 2197 wrlp(mp, INT_CAUSE_EXT, 0); 2198 rdlp(mp, INT_CAUSE_EXT); 2199 2200 err = request_irq(dev->irq, mv643xx_eth_irq, 2201 IRQF_SHARED, dev->name, dev); 2202 if (err) { 2203 netdev_err(dev, "can't assign irq\n"); 2204 return -EAGAIN; 2205 } 2206 2207 mv643xx_eth_recalc_skb_size(mp); 2208 2209 napi_enable(&mp->napi); 2210 2211 mp->int_mask = INT_EXT; 2212 2213 for (i = 0; i < mp->rxq_count; i++) { 2214 err = rxq_init(mp, i); 2215 if (err) { 2216 while (--i >= 0) 2217 rxq_deinit(mp->rxq + i); 2218 goto out; 2219 } 2220 2221 rxq_refill(mp->rxq + i, INT_MAX); 2222 mp->int_mask |= INT_RX_0 << i; 2223 } 2224 2225 if (mp->oom) { 2226 mp->rx_oom.expires = jiffies + (HZ / 10); 2227 add_timer(&mp->rx_oom); 2228 } 2229 2230 for (i = 0; i < mp->txq_count; i++) { 2231 err = txq_init(mp, i); 2232 if (err) { 2233 while (--i >= 0) 2234 txq_deinit(mp->txq + i); 2235 goto out_free; 2236 } 2237 mp->int_mask |= INT_TX_END_0 << i; 2238 } 2239 2240 port_start(mp); 2241 2242 wrlp(mp, INT_MASK_EXT, INT_EXT_LINK_PHY | INT_EXT_TX); 2243 wrlp(mp, INT_MASK, mp->int_mask); 2244 2245 return 0; 2246 2247 2248 out_free: 2249 for (i = 0; i < mp->rxq_count; i++) 2250 rxq_deinit(mp->rxq + i); 2251 out: 2252 free_irq(dev->irq, dev); 2253 2254 return err; 2255 } 2256 2257 static void port_reset(struct mv643xx_eth_private *mp) 2258 { 2259 unsigned int data; 2260 int i; 2261 2262 for (i = 0; i < mp->rxq_count; i++) 2263 rxq_disable(mp->rxq + i); 2264 for (i = 0; i < mp->txq_count; i++) 2265 txq_disable(mp->txq + i); 2266 2267 while (1) { 2268 u32 ps = rdlp(mp, PORT_STATUS); 2269 2270 if ((ps & (TX_IN_PROGRESS | TX_FIFO_EMPTY)) == TX_FIFO_EMPTY) 2271 break; 2272 udelay(10); 2273 } 2274 2275 /* Reset the Enable bit in the Configuration Register */ 2276 data = rdlp(mp, PORT_SERIAL_CONTROL); 2277 data &= ~(SERIAL_PORT_ENABLE | 2278 DO_NOT_FORCE_LINK_FAIL | 2279 FORCE_LINK_PASS); 2280 wrlp(mp, PORT_SERIAL_CONTROL, data); 2281 } 2282 2283 static int mv643xx_eth_stop(struct net_device *dev) 2284 { 2285 struct mv643xx_eth_private *mp = netdev_priv(dev); 2286 int i; 2287 2288 wrlp(mp, INT_MASK_EXT, 0x00000000); 2289 wrlp(mp, INT_MASK, 0x00000000); 2290 rdlp(mp, INT_MASK); 2291 2292 napi_disable(&mp->napi); 2293 2294 del_timer_sync(&mp->rx_oom); 2295 2296 netif_carrier_off(dev); 2297 2298 free_irq(dev->irq, dev); 2299 2300 port_reset(mp); 2301 mv643xx_eth_get_stats(dev); 2302 mib_counters_update(mp); 2303 del_timer_sync(&mp->mib_counters_timer); 2304 2305 for (i = 0; i < mp->rxq_count; i++) 2306 rxq_deinit(mp->rxq + i); 2307 for (i = 0; i < mp->txq_count; i++) 2308 txq_deinit(mp->txq + i); 2309 2310 return 0; 2311 } 2312 2313 static int mv643xx_eth_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) 2314 { 2315 struct mv643xx_eth_private *mp = netdev_priv(dev); 2316 int ret; 2317 2318 if (mp->phy == NULL) 2319 return -ENOTSUPP; 2320 2321 ret = phy_mii_ioctl(mp->phy, ifr, cmd); 2322 if (!ret) 2323 mv643xx_adjust_pscr(mp); 2324 return ret; 2325 } 2326 2327 static int mv643xx_eth_change_mtu(struct net_device *dev, int new_mtu) 2328 { 2329 struct mv643xx_eth_private *mp = netdev_priv(dev); 2330 2331 if (new_mtu < 64 || new_mtu > 9500) 2332 return -EINVAL; 2333 2334 dev->mtu = new_mtu; 2335 mv643xx_eth_recalc_skb_size(mp); 2336 tx_set_rate(mp, 1000000000, 16777216); 2337 2338 if (!netif_running(dev)) 2339 return 0; 2340 2341 /* 2342 * Stop and then re-open the interface. This will allocate RX 2343 * skbs of the new MTU. 2344 * There is a possible danger that the open will not succeed, 2345 * due to memory being full. 2346 */ 2347 mv643xx_eth_stop(dev); 2348 if (mv643xx_eth_open(dev)) { 2349 netdev_err(dev, 2350 "fatal error on re-opening device after MTU change\n"); 2351 } 2352 2353 return 0; 2354 } 2355 2356 static void tx_timeout_task(struct work_struct *ugly) 2357 { 2358 struct mv643xx_eth_private *mp; 2359 2360 mp = container_of(ugly, struct mv643xx_eth_private, tx_timeout_task); 2361 if (netif_running(mp->dev)) { 2362 netif_tx_stop_all_queues(mp->dev); 2363 port_reset(mp); 2364 port_start(mp); 2365 netif_tx_wake_all_queues(mp->dev); 2366 } 2367 } 2368 2369 static void mv643xx_eth_tx_timeout(struct net_device *dev) 2370 { 2371 struct mv643xx_eth_private *mp = netdev_priv(dev); 2372 2373 netdev_info(dev, "tx timeout\n"); 2374 2375 schedule_work(&mp->tx_timeout_task); 2376 } 2377 2378 #ifdef CONFIG_NET_POLL_CONTROLLER 2379 static void mv643xx_eth_netpoll(struct net_device *dev) 2380 { 2381 struct mv643xx_eth_private *mp = netdev_priv(dev); 2382 2383 wrlp(mp, INT_MASK, 0x00000000); 2384 rdlp(mp, INT_MASK); 2385 2386 mv643xx_eth_irq(dev->irq, dev); 2387 2388 wrlp(mp, INT_MASK, mp->int_mask); 2389 } 2390 #endif 2391 2392 2393 /* platform glue ************************************************************/ 2394 static void 2395 mv643xx_eth_conf_mbus_windows(struct mv643xx_eth_shared_private *msp, 2396 const struct mbus_dram_target_info *dram) 2397 { 2398 void __iomem *base = msp->base; 2399 u32 win_enable; 2400 u32 win_protect; 2401 int i; 2402 2403 for (i = 0; i < 6; i++) { 2404 writel(0, base + WINDOW_BASE(i)); 2405 writel(0, base + WINDOW_SIZE(i)); 2406 if (i < 4) 2407 writel(0, base + WINDOW_REMAP_HIGH(i)); 2408 } 2409 2410 win_enable = 0x3f; 2411 win_protect = 0; 2412 2413 for (i = 0; i < dram->num_cs; i++) { 2414 const struct mbus_dram_window *cs = dram->cs + i; 2415 2416 writel((cs->base & 0xffff0000) | 2417 (cs->mbus_attr << 8) | 2418 dram->mbus_dram_target_id, base + WINDOW_BASE(i)); 2419 writel((cs->size - 1) & 0xffff0000, base + WINDOW_SIZE(i)); 2420 2421 win_enable &= ~(1 << i); 2422 win_protect |= 3 << (2 * i); 2423 } 2424 2425 writel(win_enable, base + WINDOW_BAR_ENABLE); 2426 msp->win_protect = win_protect; 2427 } 2428 2429 static void infer_hw_params(struct mv643xx_eth_shared_private *msp) 2430 { 2431 /* 2432 * Check whether we have a 14-bit coal limit field in bits 2433 * [21:8], or a 16-bit coal limit in bits [25,21:7] of the 2434 * SDMA config register. 2435 */ 2436 writel(0x02000000, msp->base + 0x0400 + SDMA_CONFIG); 2437 if (readl(msp->base + 0x0400 + SDMA_CONFIG) & 0x02000000) 2438 msp->extended_rx_coal_limit = 1; 2439 else 2440 msp->extended_rx_coal_limit = 0; 2441 2442 /* 2443 * Check whether the MAC supports TX rate control, and if 2444 * yes, whether its associated registers are in the old or 2445 * the new place. 2446 */ 2447 writel(1, msp->base + 0x0400 + TX_BW_MTU_MOVED); 2448 if (readl(msp->base + 0x0400 + TX_BW_MTU_MOVED) & 1) { 2449 msp->tx_bw_control = TX_BW_CONTROL_NEW_LAYOUT; 2450 } else { 2451 writel(7, msp->base + 0x0400 + TX_BW_RATE); 2452 if (readl(msp->base + 0x0400 + TX_BW_RATE) & 7) 2453 msp->tx_bw_control = TX_BW_CONTROL_OLD_LAYOUT; 2454 else 2455 msp->tx_bw_control = TX_BW_CONTROL_ABSENT; 2456 } 2457 } 2458 2459 #if defined(CONFIG_OF) 2460 static const struct of_device_id mv643xx_eth_shared_ids[] = { 2461 { .compatible = "marvell,orion-eth", }, 2462 { .compatible = "marvell,kirkwood-eth", }, 2463 { } 2464 }; 2465 MODULE_DEVICE_TABLE(of, mv643xx_eth_shared_ids); 2466 #endif 2467 2468 #if defined(CONFIG_OF) && !defined(CONFIG_MV64X60) 2469 #define mv643xx_eth_property(_np, _name, _v) \ 2470 do { \ 2471 u32 tmp; \ 2472 if (!of_property_read_u32(_np, "marvell," _name, &tmp)) \ 2473 _v = tmp; \ 2474 } while (0) 2475 2476 static struct platform_device *port_platdev[3]; 2477 2478 static int mv643xx_eth_shared_of_add_port(struct platform_device *pdev, 2479 struct device_node *pnp) 2480 { 2481 struct platform_device *ppdev; 2482 struct mv643xx_eth_platform_data ppd; 2483 struct resource res; 2484 const char *mac_addr; 2485 int ret; 2486 int dev_num = 0; 2487 2488 memset(&ppd, 0, sizeof(ppd)); 2489 ppd.shared = pdev; 2490 2491 memset(&res, 0, sizeof(res)); 2492 if (!of_irq_to_resource(pnp, 0, &res)) { 2493 dev_err(&pdev->dev, "missing interrupt on %s\n", pnp->name); 2494 return -EINVAL; 2495 } 2496 2497 if (of_property_read_u32(pnp, "reg", &ppd.port_number)) { 2498 dev_err(&pdev->dev, "missing reg property on %s\n", pnp->name); 2499 return -EINVAL; 2500 } 2501 2502 if (ppd.port_number >= 3) { 2503 dev_err(&pdev->dev, "invalid reg property on %s\n", pnp->name); 2504 return -EINVAL; 2505 } 2506 2507 while (dev_num < 3 && port_platdev[dev_num]) 2508 dev_num++; 2509 2510 if (dev_num == 3) { 2511 dev_err(&pdev->dev, "too many ports registered\n"); 2512 return -EINVAL; 2513 } 2514 2515 mac_addr = of_get_mac_address(pnp); 2516 if (mac_addr) 2517 memcpy(ppd.mac_addr, mac_addr, 6); 2518 2519 mv643xx_eth_property(pnp, "tx-queue-size", ppd.tx_queue_size); 2520 mv643xx_eth_property(pnp, "tx-sram-addr", ppd.tx_sram_addr); 2521 mv643xx_eth_property(pnp, "tx-sram-size", ppd.tx_sram_size); 2522 mv643xx_eth_property(pnp, "rx-queue-size", ppd.rx_queue_size); 2523 mv643xx_eth_property(pnp, "rx-sram-addr", ppd.rx_sram_addr); 2524 mv643xx_eth_property(pnp, "rx-sram-size", ppd.rx_sram_size); 2525 2526 ppd.phy_node = of_parse_phandle(pnp, "phy-handle", 0); 2527 if (!ppd.phy_node) { 2528 ppd.phy_addr = MV643XX_ETH_PHY_NONE; 2529 of_property_read_u32(pnp, "speed", &ppd.speed); 2530 of_property_read_u32(pnp, "duplex", &ppd.duplex); 2531 } 2532 2533 ppdev = platform_device_alloc(MV643XX_ETH_NAME, dev_num); 2534 if (!ppdev) 2535 return -ENOMEM; 2536 ppdev->dev.coherent_dma_mask = DMA_BIT_MASK(32); 2537 2538 ret = platform_device_add_resources(ppdev, &res, 1); 2539 if (ret) 2540 goto port_err; 2541 2542 ret = platform_device_add_data(ppdev, &ppd, sizeof(ppd)); 2543 if (ret) 2544 goto port_err; 2545 2546 ret = platform_device_add(ppdev); 2547 if (ret) 2548 goto port_err; 2549 2550 port_platdev[dev_num] = ppdev; 2551 2552 return 0; 2553 2554 port_err: 2555 platform_device_put(ppdev); 2556 return ret; 2557 } 2558 2559 static int mv643xx_eth_shared_of_probe(struct platform_device *pdev) 2560 { 2561 struct mv643xx_eth_shared_platform_data *pd; 2562 struct device_node *pnp, *np = pdev->dev.of_node; 2563 int ret; 2564 2565 /* bail out if not registered from DT */ 2566 if (!np) 2567 return 0; 2568 2569 pd = devm_kzalloc(&pdev->dev, sizeof(*pd), GFP_KERNEL); 2570 if (!pd) 2571 return -ENOMEM; 2572 pdev->dev.platform_data = pd; 2573 2574 mv643xx_eth_property(np, "tx-checksum-limit", pd->tx_csum_limit); 2575 2576 for_each_available_child_of_node(np, pnp) { 2577 ret = mv643xx_eth_shared_of_add_port(pdev, pnp); 2578 if (ret) 2579 return ret; 2580 } 2581 return 0; 2582 } 2583 2584 static void mv643xx_eth_shared_of_remove(void) 2585 { 2586 int n; 2587 2588 for (n = 0; n < 3; n++) { 2589 platform_device_del(port_platdev[n]); 2590 port_platdev[n] = NULL; 2591 } 2592 } 2593 #else 2594 static inline int mv643xx_eth_shared_of_probe(struct platform_device *pdev) 2595 { 2596 return 0; 2597 } 2598 2599 static inline void mv643xx_eth_shared_of_remove(void) 2600 { 2601 } 2602 #endif 2603 2604 static int mv643xx_eth_shared_probe(struct platform_device *pdev) 2605 { 2606 static int mv643xx_eth_version_printed; 2607 struct mv643xx_eth_shared_platform_data *pd; 2608 struct mv643xx_eth_shared_private *msp; 2609 const struct mbus_dram_target_info *dram; 2610 struct resource *res; 2611 int ret; 2612 2613 if (!mv643xx_eth_version_printed++) 2614 pr_notice("MV-643xx 10/100/1000 ethernet driver version %s\n", 2615 mv643xx_eth_driver_version); 2616 2617 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2618 if (res == NULL) 2619 return -EINVAL; 2620 2621 msp = devm_kzalloc(&pdev->dev, sizeof(*msp), GFP_KERNEL); 2622 if (msp == NULL) 2623 return -ENOMEM; 2624 platform_set_drvdata(pdev, msp); 2625 2626 msp->base = devm_ioremap(&pdev->dev, res->start, resource_size(res)); 2627 if (msp->base == NULL) 2628 return -ENOMEM; 2629 2630 msp->clk = devm_clk_get(&pdev->dev, NULL); 2631 if (!IS_ERR(msp->clk)) 2632 clk_prepare_enable(msp->clk); 2633 2634 /* 2635 * (Re-)program MBUS remapping windows if we are asked to. 2636 */ 2637 dram = mv_mbus_dram_info(); 2638 if (dram) 2639 mv643xx_eth_conf_mbus_windows(msp, dram); 2640 2641 ret = mv643xx_eth_shared_of_probe(pdev); 2642 if (ret) 2643 return ret; 2644 pd = dev_get_platdata(&pdev->dev); 2645 2646 msp->tx_csum_limit = (pd != NULL && pd->tx_csum_limit) ? 2647 pd->tx_csum_limit : 9 * 1024; 2648 infer_hw_params(msp); 2649 2650 return 0; 2651 } 2652 2653 static int mv643xx_eth_shared_remove(struct platform_device *pdev) 2654 { 2655 struct mv643xx_eth_shared_private *msp = platform_get_drvdata(pdev); 2656 2657 mv643xx_eth_shared_of_remove(); 2658 if (!IS_ERR(msp->clk)) 2659 clk_disable_unprepare(msp->clk); 2660 return 0; 2661 } 2662 2663 static struct platform_driver mv643xx_eth_shared_driver = { 2664 .probe = mv643xx_eth_shared_probe, 2665 .remove = mv643xx_eth_shared_remove, 2666 .driver = { 2667 .name = MV643XX_ETH_SHARED_NAME, 2668 .owner = THIS_MODULE, 2669 .of_match_table = of_match_ptr(mv643xx_eth_shared_ids), 2670 }, 2671 }; 2672 2673 static void phy_addr_set(struct mv643xx_eth_private *mp, int phy_addr) 2674 { 2675 int addr_shift = 5 * mp->port_num; 2676 u32 data; 2677 2678 data = rdl(mp, PHY_ADDR); 2679 data &= ~(0x1f << addr_shift); 2680 data |= (phy_addr & 0x1f) << addr_shift; 2681 wrl(mp, PHY_ADDR, data); 2682 } 2683 2684 static int phy_addr_get(struct mv643xx_eth_private *mp) 2685 { 2686 unsigned int data; 2687 2688 data = rdl(mp, PHY_ADDR); 2689 2690 return (data >> (5 * mp->port_num)) & 0x1f; 2691 } 2692 2693 static void set_params(struct mv643xx_eth_private *mp, 2694 struct mv643xx_eth_platform_data *pd) 2695 { 2696 struct net_device *dev = mp->dev; 2697 2698 if (is_valid_ether_addr(pd->mac_addr)) 2699 memcpy(dev->dev_addr, pd->mac_addr, 6); 2700 else 2701 uc_addr_get(mp, dev->dev_addr); 2702 2703 mp->rx_ring_size = DEFAULT_RX_QUEUE_SIZE; 2704 if (pd->rx_queue_size) 2705 mp->rx_ring_size = pd->rx_queue_size; 2706 mp->rx_desc_sram_addr = pd->rx_sram_addr; 2707 mp->rx_desc_sram_size = pd->rx_sram_size; 2708 2709 mp->rxq_count = pd->rx_queue_count ? : 1; 2710 2711 mp->tx_ring_size = DEFAULT_TX_QUEUE_SIZE; 2712 if (pd->tx_queue_size) 2713 mp->tx_ring_size = pd->tx_queue_size; 2714 mp->tx_desc_sram_addr = pd->tx_sram_addr; 2715 mp->tx_desc_sram_size = pd->tx_sram_size; 2716 2717 mp->txq_count = pd->tx_queue_count ? : 1; 2718 } 2719 2720 static void mv643xx_eth_adjust_link(struct net_device *dev) 2721 { 2722 struct mv643xx_eth_private *mp = netdev_priv(dev); 2723 2724 mv643xx_adjust_pscr(mp); 2725 } 2726 2727 static struct phy_device *phy_scan(struct mv643xx_eth_private *mp, 2728 int phy_addr) 2729 { 2730 struct phy_device *phydev; 2731 int start; 2732 int num; 2733 int i; 2734 char phy_id[MII_BUS_ID_SIZE + 3]; 2735 2736 if (phy_addr == MV643XX_ETH_PHY_ADDR_DEFAULT) { 2737 start = phy_addr_get(mp) & 0x1f; 2738 num = 32; 2739 } else { 2740 start = phy_addr & 0x1f; 2741 num = 1; 2742 } 2743 2744 /* Attempt to connect to the PHY using orion-mdio */ 2745 phydev = ERR_PTR(-ENODEV); 2746 for (i = 0; i < num; i++) { 2747 int addr = (start + i) & 0x1f; 2748 2749 snprintf(phy_id, sizeof(phy_id), PHY_ID_FMT, 2750 "orion-mdio-mii", addr); 2751 2752 phydev = phy_connect(mp->dev, phy_id, mv643xx_eth_adjust_link, 2753 PHY_INTERFACE_MODE_GMII); 2754 if (!IS_ERR(phydev)) { 2755 phy_addr_set(mp, addr); 2756 break; 2757 } 2758 } 2759 2760 return phydev; 2761 } 2762 2763 static void phy_init(struct mv643xx_eth_private *mp, int speed, int duplex) 2764 { 2765 struct phy_device *phy = mp->phy; 2766 2767 phy_reset(mp); 2768 2769 if (speed == 0) { 2770 phy->autoneg = AUTONEG_ENABLE; 2771 phy->speed = 0; 2772 phy->duplex = 0; 2773 phy->advertising = phy->supported | ADVERTISED_Autoneg; 2774 } else { 2775 phy->autoneg = AUTONEG_DISABLE; 2776 phy->advertising = 0; 2777 phy->speed = speed; 2778 phy->duplex = duplex; 2779 } 2780 phy_start_aneg(phy); 2781 } 2782 2783 static void init_pscr(struct mv643xx_eth_private *mp, int speed, int duplex) 2784 { 2785 u32 pscr; 2786 2787 pscr = rdlp(mp, PORT_SERIAL_CONTROL); 2788 if (pscr & SERIAL_PORT_ENABLE) { 2789 pscr &= ~SERIAL_PORT_ENABLE; 2790 wrlp(mp, PORT_SERIAL_CONTROL, pscr); 2791 } 2792 2793 pscr = MAX_RX_PACKET_9700BYTE | SERIAL_PORT_CONTROL_RESERVED; 2794 if (mp->phy == NULL) { 2795 pscr |= DISABLE_AUTO_NEG_SPEED_GMII; 2796 if (speed == SPEED_1000) 2797 pscr |= SET_GMII_SPEED_TO_1000; 2798 else if (speed == SPEED_100) 2799 pscr |= SET_MII_SPEED_TO_100; 2800 2801 pscr |= DISABLE_AUTO_NEG_FOR_FLOW_CTRL; 2802 2803 pscr |= DISABLE_AUTO_NEG_FOR_DUPLEX; 2804 if (duplex == DUPLEX_FULL) 2805 pscr |= SET_FULL_DUPLEX_MODE; 2806 } 2807 2808 wrlp(mp, PORT_SERIAL_CONTROL, pscr); 2809 } 2810 2811 static const struct net_device_ops mv643xx_eth_netdev_ops = { 2812 .ndo_open = mv643xx_eth_open, 2813 .ndo_stop = mv643xx_eth_stop, 2814 .ndo_start_xmit = mv643xx_eth_xmit, 2815 .ndo_set_rx_mode = mv643xx_eth_set_rx_mode, 2816 .ndo_set_mac_address = mv643xx_eth_set_mac_address, 2817 .ndo_validate_addr = eth_validate_addr, 2818 .ndo_do_ioctl = mv643xx_eth_ioctl, 2819 .ndo_change_mtu = mv643xx_eth_change_mtu, 2820 .ndo_set_features = mv643xx_eth_set_features, 2821 .ndo_tx_timeout = mv643xx_eth_tx_timeout, 2822 .ndo_get_stats = mv643xx_eth_get_stats, 2823 #ifdef CONFIG_NET_POLL_CONTROLLER 2824 .ndo_poll_controller = mv643xx_eth_netpoll, 2825 #endif 2826 }; 2827 2828 static int mv643xx_eth_probe(struct platform_device *pdev) 2829 { 2830 struct mv643xx_eth_platform_data *pd; 2831 struct mv643xx_eth_private *mp; 2832 struct net_device *dev; 2833 struct resource *res; 2834 int err; 2835 2836 pd = dev_get_platdata(&pdev->dev); 2837 if (pd == NULL) { 2838 dev_err(&pdev->dev, "no mv643xx_eth_platform_data\n"); 2839 return -ENODEV; 2840 } 2841 2842 if (pd->shared == NULL) { 2843 dev_err(&pdev->dev, "no mv643xx_eth_platform_data->shared\n"); 2844 return -ENODEV; 2845 } 2846 2847 dev = alloc_etherdev_mq(sizeof(struct mv643xx_eth_private), 8); 2848 if (!dev) 2849 return -ENOMEM; 2850 2851 mp = netdev_priv(dev); 2852 platform_set_drvdata(pdev, mp); 2853 2854 mp->shared = platform_get_drvdata(pd->shared); 2855 mp->base = mp->shared->base + 0x0400 + (pd->port_number << 10); 2856 mp->port_num = pd->port_number; 2857 2858 mp->dev = dev; 2859 2860 /* Kirkwood resets some registers on gated clocks. Especially 2861 * CLK125_BYPASS_EN must be cleared but is not available on 2862 * all other SoCs/System Controllers using this driver. 2863 */ 2864 if (of_device_is_compatible(pdev->dev.of_node, 2865 "marvell,kirkwood-eth-port")) 2866 wrlp(mp, PORT_SERIAL_CONTROL1, 2867 rdlp(mp, PORT_SERIAL_CONTROL1) & ~CLK125_BYPASS_EN); 2868 2869 /* 2870 * Start with a default rate, and if there is a clock, allow 2871 * it to override the default. 2872 */ 2873 mp->t_clk = 133000000; 2874 mp->clk = devm_clk_get(&pdev->dev, NULL); 2875 if (!IS_ERR(mp->clk)) { 2876 clk_prepare_enable(mp->clk); 2877 mp->t_clk = clk_get_rate(mp->clk); 2878 } else if (!IS_ERR(mp->shared->clk)) { 2879 mp->t_clk = clk_get_rate(mp->shared->clk); 2880 } 2881 2882 set_params(mp, pd); 2883 netif_set_real_num_tx_queues(dev, mp->txq_count); 2884 netif_set_real_num_rx_queues(dev, mp->rxq_count); 2885 2886 err = 0; 2887 if (pd->phy_node) { 2888 mp->phy = of_phy_connect(mp->dev, pd->phy_node, 2889 mv643xx_eth_adjust_link, 0, 2890 PHY_INTERFACE_MODE_GMII); 2891 if (!mp->phy) 2892 err = -ENODEV; 2893 } else if (pd->phy_addr != MV643XX_ETH_PHY_NONE) { 2894 mp->phy = phy_scan(mp, pd->phy_addr); 2895 2896 if (IS_ERR(mp->phy)) 2897 err = PTR_ERR(mp->phy); 2898 else 2899 phy_init(mp, pd->speed, pd->duplex); 2900 } 2901 if (err == -ENODEV) { 2902 err = -EPROBE_DEFER; 2903 goto out; 2904 } 2905 if (err) 2906 goto out; 2907 2908 SET_ETHTOOL_OPS(dev, &mv643xx_eth_ethtool_ops); 2909 2910 init_pscr(mp, pd->speed, pd->duplex); 2911 2912 2913 mib_counters_clear(mp); 2914 2915 init_timer(&mp->mib_counters_timer); 2916 mp->mib_counters_timer.data = (unsigned long)mp; 2917 mp->mib_counters_timer.function = mib_counters_timer_wrapper; 2918 mp->mib_counters_timer.expires = jiffies + 30 * HZ; 2919 add_timer(&mp->mib_counters_timer); 2920 2921 spin_lock_init(&mp->mib_counters_lock); 2922 2923 INIT_WORK(&mp->tx_timeout_task, tx_timeout_task); 2924 2925 netif_napi_add(dev, &mp->napi, mv643xx_eth_poll, NAPI_POLL_WEIGHT); 2926 2927 init_timer(&mp->rx_oom); 2928 mp->rx_oom.data = (unsigned long)mp; 2929 mp->rx_oom.function = oom_timer_wrapper; 2930 2931 2932 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); 2933 BUG_ON(!res); 2934 dev->irq = res->start; 2935 2936 dev->netdev_ops = &mv643xx_eth_netdev_ops; 2937 2938 dev->watchdog_timeo = 2 * HZ; 2939 dev->base_addr = 0; 2940 2941 dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_RXCSUM; 2942 dev->features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_RXCSUM; 2943 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM; 2944 2945 dev->priv_flags |= IFF_UNICAST_FLT; 2946 2947 SET_NETDEV_DEV(dev, &pdev->dev); 2948 2949 if (mp->shared->win_protect) 2950 wrl(mp, WINDOW_PROTECT(mp->port_num), mp->shared->win_protect); 2951 2952 netif_carrier_off(dev); 2953 2954 wrlp(mp, SDMA_CONFIG, PORT_SDMA_CONFIG_DEFAULT_VALUE); 2955 2956 set_rx_coal(mp, 250); 2957 set_tx_coal(mp, 0); 2958 2959 err = register_netdev(dev); 2960 if (err) 2961 goto out; 2962 2963 netdev_notice(dev, "port %d with MAC address %pM\n", 2964 mp->port_num, dev->dev_addr); 2965 2966 if (mp->tx_desc_sram_size > 0) 2967 netdev_notice(dev, "configured with sram\n"); 2968 2969 return 0; 2970 2971 out: 2972 if (!IS_ERR(mp->clk)) 2973 clk_disable_unprepare(mp->clk); 2974 free_netdev(dev); 2975 2976 return err; 2977 } 2978 2979 static int mv643xx_eth_remove(struct platform_device *pdev) 2980 { 2981 struct mv643xx_eth_private *mp = platform_get_drvdata(pdev); 2982 2983 unregister_netdev(mp->dev); 2984 if (mp->phy != NULL) 2985 phy_disconnect(mp->phy); 2986 cancel_work_sync(&mp->tx_timeout_task); 2987 2988 if (!IS_ERR(mp->clk)) 2989 clk_disable_unprepare(mp->clk); 2990 2991 free_netdev(mp->dev); 2992 2993 return 0; 2994 } 2995 2996 static void mv643xx_eth_shutdown(struct platform_device *pdev) 2997 { 2998 struct mv643xx_eth_private *mp = platform_get_drvdata(pdev); 2999 3000 /* Mask all interrupts on ethernet port */ 3001 wrlp(mp, INT_MASK, 0); 3002 rdlp(mp, INT_MASK); 3003 3004 if (netif_running(mp->dev)) 3005 port_reset(mp); 3006 } 3007 3008 static struct platform_driver mv643xx_eth_driver = { 3009 .probe = mv643xx_eth_probe, 3010 .remove = mv643xx_eth_remove, 3011 .shutdown = mv643xx_eth_shutdown, 3012 .driver = { 3013 .name = MV643XX_ETH_NAME, 3014 .owner = THIS_MODULE, 3015 }, 3016 }; 3017 3018 static int __init mv643xx_eth_init_module(void) 3019 { 3020 int rc; 3021 3022 rc = platform_driver_register(&mv643xx_eth_shared_driver); 3023 if (!rc) { 3024 rc = platform_driver_register(&mv643xx_eth_driver); 3025 if (rc) 3026 platform_driver_unregister(&mv643xx_eth_shared_driver); 3027 } 3028 3029 return rc; 3030 } 3031 module_init(mv643xx_eth_init_module); 3032 3033 static void __exit mv643xx_eth_cleanup_module(void) 3034 { 3035 platform_driver_unregister(&mv643xx_eth_driver); 3036 platform_driver_unregister(&mv643xx_eth_shared_driver); 3037 } 3038 module_exit(mv643xx_eth_cleanup_module); 3039 3040 MODULE_AUTHOR("Rabeeh Khoury, Assaf Hoffman, Matthew Dharm, " 3041 "Manish Lachwani, Dale Farnsworth and Lennert Buytenhek"); 3042 MODULE_DESCRIPTION("Ethernet driver for Marvell MV643XX"); 3043 MODULE_LICENSE("GPL"); 3044 MODULE_ALIAS("platform:" MV643XX_ETH_SHARED_NAME); 3045 MODULE_ALIAS("platform:" MV643XX_ETH_NAME); 3046