1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Lantiq / Intel PMAC driver for XRX200 SoCs 4 * 5 * Copyright (C) 2010 Lantiq Deutschland 6 * Copyright (C) 2012 John Crispin <john@phrozen.org> 7 * Copyright (C) 2017 - 2018 Hauke Mehrtens <hauke@hauke-m.de> 8 */ 9 10 #include <linux/etherdevice.h> 11 #include <linux/module.h> 12 #include <linux/platform_device.h> 13 #include <linux/interrupt.h> 14 #include <linux/clk.h> 15 #include <linux/delay.h> 16 17 #include <linux/of_net.h> 18 #include <linux/of_platform.h> 19 20 #include <xway_dma.h> 21 22 /* DMA */ 23 #define XRX200_DMA_DATA_LEN 0x600 24 #define XRX200_DMA_RX 0 25 #define XRX200_DMA_TX 1 26 27 /* cpu port mac */ 28 #define PMAC_RX_IPG 0x0024 29 #define PMAC_RX_IPG_MASK 0xf 30 31 #define PMAC_HD_CTL 0x0000 32 /* Add Ethernet header to packets from DMA to PMAC */ 33 #define PMAC_HD_CTL_ADD BIT(0) 34 /* Add VLAN tag to Packets from DMA to PMAC */ 35 #define PMAC_HD_CTL_TAG BIT(1) 36 /* Add CRC to packets from DMA to PMAC */ 37 #define PMAC_HD_CTL_AC BIT(2) 38 /* Add status header to packets from PMAC to DMA */ 39 #define PMAC_HD_CTL_AS BIT(3) 40 /* Remove CRC from packets from PMAC to DMA */ 41 #define PMAC_HD_CTL_RC BIT(4) 42 /* Remove Layer-2 header from packets from PMAC to DMA */ 43 #define PMAC_HD_CTL_RL2 BIT(5) 44 /* Status header is present from DMA to PMAC */ 45 #define PMAC_HD_CTL_RXSH BIT(6) 46 /* Add special tag from PMAC to switch */ 47 #define PMAC_HD_CTL_AST BIT(7) 48 /* Remove specail Tag from PMAC to DMA */ 49 #define PMAC_HD_CTL_RST BIT(8) 50 /* Check CRC from DMA to PMAC */ 51 #define PMAC_HD_CTL_CCRC BIT(9) 52 /* Enable reaction to Pause frames in the PMAC */ 53 #define PMAC_HD_CTL_FC BIT(10) 54 55 struct xrx200_chan { 56 int tx_free; 57 58 struct napi_struct napi; 59 struct ltq_dma_channel dma; 60 struct sk_buff *skb[LTQ_DESC_NUM]; 61 62 struct xrx200_priv *priv; 63 }; 64 65 struct xrx200_priv { 66 struct clk *clk; 67 68 struct xrx200_chan chan_tx; 69 struct xrx200_chan chan_rx; 70 71 struct net_device *net_dev; 72 struct device *dev; 73 74 __iomem void *pmac_reg; 75 }; 76 77 static u32 xrx200_pmac_r32(struct xrx200_priv *priv, u32 offset) 78 { 79 return __raw_readl(priv->pmac_reg + offset); 80 } 81 82 static void xrx200_pmac_w32(struct xrx200_priv *priv, u32 val, u32 offset) 83 { 84 __raw_writel(val, priv->pmac_reg + offset); 85 } 86 87 static void xrx200_pmac_mask(struct xrx200_priv *priv, u32 clear, u32 set, 88 u32 offset) 89 { 90 u32 val = xrx200_pmac_r32(priv, offset); 91 92 val &= ~(clear); 93 val |= set; 94 xrx200_pmac_w32(priv, val, offset); 95 } 96 97 /* drop all the packets from the DMA ring */ 98 static void xrx200_flush_dma(struct xrx200_chan *ch) 99 { 100 int i; 101 102 for (i = 0; i < LTQ_DESC_NUM; i++) { 103 struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->dma.desc]; 104 105 if ((desc->ctl & (LTQ_DMA_OWN | LTQ_DMA_C)) != LTQ_DMA_C) 106 break; 107 108 desc->ctl = LTQ_DMA_OWN | LTQ_DMA_RX_OFFSET(NET_IP_ALIGN) | 109 XRX200_DMA_DATA_LEN; 110 ch->dma.desc++; 111 ch->dma.desc %= LTQ_DESC_NUM; 112 } 113 } 114 115 static int xrx200_open(struct net_device *net_dev) 116 { 117 struct xrx200_priv *priv = netdev_priv(net_dev); 118 int err; 119 120 /* enable clock gate */ 121 err = clk_prepare_enable(priv->clk); 122 if (err) 123 return err; 124 125 napi_enable(&priv->chan_tx.napi); 126 ltq_dma_open(&priv->chan_tx.dma); 127 ltq_dma_enable_irq(&priv->chan_tx.dma); 128 129 napi_enable(&priv->chan_rx.napi); 130 ltq_dma_open(&priv->chan_rx.dma); 131 /* The boot loader does not always deactivate the receiving of frames 132 * on the ports and then some packets queue up in the PPE buffers. 133 * They already passed the PMAC so they do not have the tags 134 * configured here. Read the these packets here and drop them. 135 * The HW should have written them into memory after 10us 136 */ 137 usleep_range(20, 40); 138 xrx200_flush_dma(&priv->chan_rx); 139 ltq_dma_enable_irq(&priv->chan_rx.dma); 140 141 netif_wake_queue(net_dev); 142 143 return 0; 144 } 145 146 static int xrx200_close(struct net_device *net_dev) 147 { 148 struct xrx200_priv *priv = netdev_priv(net_dev); 149 150 netif_stop_queue(net_dev); 151 152 napi_disable(&priv->chan_rx.napi); 153 ltq_dma_close(&priv->chan_rx.dma); 154 155 napi_disable(&priv->chan_tx.napi); 156 ltq_dma_close(&priv->chan_tx.dma); 157 158 clk_disable_unprepare(priv->clk); 159 160 return 0; 161 } 162 163 static int xrx200_alloc_skb(struct xrx200_chan *ch) 164 { 165 int ret = 0; 166 167 ch->skb[ch->dma.desc] = netdev_alloc_skb_ip_align(ch->priv->net_dev, 168 XRX200_DMA_DATA_LEN); 169 if (!ch->skb[ch->dma.desc]) { 170 ret = -ENOMEM; 171 goto skip; 172 } 173 174 ch->dma.desc_base[ch->dma.desc].addr = dma_map_single(ch->priv->dev, 175 ch->skb[ch->dma.desc]->data, XRX200_DMA_DATA_LEN, 176 DMA_FROM_DEVICE); 177 if (unlikely(dma_mapping_error(ch->priv->dev, 178 ch->dma.desc_base[ch->dma.desc].addr))) { 179 dev_kfree_skb_any(ch->skb[ch->dma.desc]); 180 ret = -ENOMEM; 181 goto skip; 182 } 183 184 skip: 185 ch->dma.desc_base[ch->dma.desc].ctl = 186 LTQ_DMA_OWN | LTQ_DMA_RX_OFFSET(NET_IP_ALIGN) | 187 XRX200_DMA_DATA_LEN; 188 189 return ret; 190 } 191 192 static int xrx200_hw_receive(struct xrx200_chan *ch) 193 { 194 struct xrx200_priv *priv = ch->priv; 195 struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->dma.desc]; 196 struct sk_buff *skb = ch->skb[ch->dma.desc]; 197 int len = (desc->ctl & LTQ_DMA_SIZE_MASK); 198 struct net_device *net_dev = priv->net_dev; 199 int ret; 200 201 ret = xrx200_alloc_skb(ch); 202 203 ch->dma.desc++; 204 ch->dma.desc %= LTQ_DESC_NUM; 205 206 if (ret) { 207 netdev_err(net_dev, "failed to allocate new rx buffer\n"); 208 return ret; 209 } 210 211 skb_put(skb, len); 212 skb->protocol = eth_type_trans(skb, net_dev); 213 netif_receive_skb(skb); 214 net_dev->stats.rx_packets++; 215 net_dev->stats.rx_bytes += len - ETH_FCS_LEN; 216 217 return 0; 218 } 219 220 static int xrx200_poll_rx(struct napi_struct *napi, int budget) 221 { 222 struct xrx200_chan *ch = container_of(napi, 223 struct xrx200_chan, napi); 224 int rx = 0; 225 int ret; 226 227 while (rx < budget) { 228 struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->dma.desc]; 229 230 if ((desc->ctl & (LTQ_DMA_OWN | LTQ_DMA_C)) == LTQ_DMA_C) { 231 ret = xrx200_hw_receive(ch); 232 if (ret) 233 return ret; 234 rx++; 235 } else { 236 break; 237 } 238 } 239 240 if (rx < budget) { 241 napi_complete(&ch->napi); 242 ltq_dma_enable_irq(&ch->dma); 243 } 244 245 return rx; 246 } 247 248 static int xrx200_tx_housekeeping(struct napi_struct *napi, int budget) 249 { 250 struct xrx200_chan *ch = container_of(napi, 251 struct xrx200_chan, napi); 252 struct net_device *net_dev = ch->priv->net_dev; 253 int pkts = 0; 254 int bytes = 0; 255 256 while (pkts < budget) { 257 struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->tx_free]; 258 259 if ((desc->ctl & (LTQ_DMA_OWN | LTQ_DMA_C)) == LTQ_DMA_C) { 260 struct sk_buff *skb = ch->skb[ch->tx_free]; 261 262 pkts++; 263 bytes += skb->len; 264 ch->skb[ch->tx_free] = NULL; 265 consume_skb(skb); 266 memset(&ch->dma.desc_base[ch->tx_free], 0, 267 sizeof(struct ltq_dma_desc)); 268 ch->tx_free++; 269 ch->tx_free %= LTQ_DESC_NUM; 270 } else { 271 break; 272 } 273 } 274 275 net_dev->stats.tx_packets += pkts; 276 net_dev->stats.tx_bytes += bytes; 277 netdev_completed_queue(ch->priv->net_dev, pkts, bytes); 278 279 if (pkts < budget) { 280 napi_complete(&ch->napi); 281 ltq_dma_enable_irq(&ch->dma); 282 } 283 284 return pkts; 285 } 286 287 static int xrx200_start_xmit(struct sk_buff *skb, struct net_device *net_dev) 288 { 289 struct xrx200_priv *priv = netdev_priv(net_dev); 290 struct xrx200_chan *ch = &priv->chan_tx; 291 struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->dma.desc]; 292 u32 byte_offset; 293 dma_addr_t mapping; 294 int len; 295 296 skb->dev = net_dev; 297 if (skb_put_padto(skb, ETH_ZLEN)) { 298 net_dev->stats.tx_dropped++; 299 return NETDEV_TX_OK; 300 } 301 302 len = skb->len; 303 304 if ((desc->ctl & (LTQ_DMA_OWN | LTQ_DMA_C)) || ch->skb[ch->dma.desc]) { 305 netdev_err(net_dev, "tx ring full\n"); 306 netif_stop_queue(net_dev); 307 return NETDEV_TX_BUSY; 308 } 309 310 ch->skb[ch->dma.desc] = skb; 311 312 mapping = dma_map_single(priv->dev, skb->data, len, DMA_TO_DEVICE); 313 if (unlikely(dma_mapping_error(priv->dev, mapping))) 314 goto err_drop; 315 316 /* dma needs to start on a 16 byte aligned address */ 317 byte_offset = mapping % 16; 318 319 desc->addr = mapping - byte_offset; 320 /* Make sure the address is written before we give it to HW */ 321 wmb(); 322 desc->ctl = LTQ_DMA_OWN | LTQ_DMA_SOP | LTQ_DMA_EOP | 323 LTQ_DMA_TX_OFFSET(byte_offset) | (len & LTQ_DMA_SIZE_MASK); 324 ch->dma.desc++; 325 ch->dma.desc %= LTQ_DESC_NUM; 326 if (ch->dma.desc == ch->tx_free) 327 netif_stop_queue(net_dev); 328 329 netdev_sent_queue(net_dev, len); 330 331 return NETDEV_TX_OK; 332 333 err_drop: 334 dev_kfree_skb(skb); 335 net_dev->stats.tx_dropped++; 336 net_dev->stats.tx_errors++; 337 return NETDEV_TX_OK; 338 } 339 340 static const struct net_device_ops xrx200_netdev_ops = { 341 .ndo_open = xrx200_open, 342 .ndo_stop = xrx200_close, 343 .ndo_start_xmit = xrx200_start_xmit, 344 .ndo_set_mac_address = eth_mac_addr, 345 .ndo_validate_addr = eth_validate_addr, 346 .ndo_change_mtu = eth_change_mtu, 347 }; 348 349 static irqreturn_t xrx200_dma_irq(int irq, void *ptr) 350 { 351 struct xrx200_chan *ch = ptr; 352 353 ltq_dma_disable_irq(&ch->dma); 354 ltq_dma_ack_irq(&ch->dma); 355 356 napi_schedule(&ch->napi); 357 358 return IRQ_HANDLED; 359 } 360 361 static int xrx200_dma_init(struct xrx200_priv *priv) 362 { 363 struct xrx200_chan *ch_rx = &priv->chan_rx; 364 struct xrx200_chan *ch_tx = &priv->chan_tx; 365 int ret = 0; 366 int i; 367 368 ltq_dma_init_port(DMA_PORT_ETOP); 369 370 ch_rx->dma.nr = XRX200_DMA_RX; 371 ch_rx->dma.dev = priv->dev; 372 ch_rx->priv = priv; 373 374 ltq_dma_alloc_rx(&ch_rx->dma); 375 for (ch_rx->dma.desc = 0; ch_rx->dma.desc < LTQ_DESC_NUM; 376 ch_rx->dma.desc++) { 377 ret = xrx200_alloc_skb(ch_rx); 378 if (ret) 379 goto rx_free; 380 } 381 ch_rx->dma.desc = 0; 382 ret = devm_request_irq(priv->dev, ch_rx->dma.irq, xrx200_dma_irq, 0, 383 "xrx200_net_rx", &priv->chan_rx); 384 if (ret) { 385 dev_err(priv->dev, "failed to request RX irq %d\n", 386 ch_rx->dma.irq); 387 goto rx_ring_free; 388 } 389 390 ch_tx->dma.nr = XRX200_DMA_TX; 391 ch_tx->dma.dev = priv->dev; 392 ch_tx->priv = priv; 393 394 ltq_dma_alloc_tx(&ch_tx->dma); 395 ret = devm_request_irq(priv->dev, ch_tx->dma.irq, xrx200_dma_irq, 0, 396 "xrx200_net_tx", &priv->chan_tx); 397 if (ret) { 398 dev_err(priv->dev, "failed to request TX irq %d\n", 399 ch_tx->dma.irq); 400 goto tx_free; 401 } 402 403 return ret; 404 405 tx_free: 406 ltq_dma_free(&ch_tx->dma); 407 408 rx_ring_free: 409 /* free the allocated RX ring */ 410 for (i = 0; i < LTQ_DESC_NUM; i++) { 411 if (priv->chan_rx.skb[i]) 412 dev_kfree_skb_any(priv->chan_rx.skb[i]); 413 } 414 415 rx_free: 416 ltq_dma_free(&ch_rx->dma); 417 return ret; 418 } 419 420 static void xrx200_hw_cleanup(struct xrx200_priv *priv) 421 { 422 int i; 423 424 ltq_dma_free(&priv->chan_tx.dma); 425 ltq_dma_free(&priv->chan_rx.dma); 426 427 /* free the allocated RX ring */ 428 for (i = 0; i < LTQ_DESC_NUM; i++) 429 dev_kfree_skb_any(priv->chan_rx.skb[i]); 430 } 431 432 static int xrx200_probe(struct platform_device *pdev) 433 { 434 struct device *dev = &pdev->dev; 435 struct device_node *np = dev->of_node; 436 struct resource *res; 437 struct xrx200_priv *priv; 438 struct net_device *net_dev; 439 const u8 *mac; 440 int err; 441 442 /* alloc the network device */ 443 net_dev = devm_alloc_etherdev(dev, sizeof(struct xrx200_priv)); 444 if (!net_dev) 445 return -ENOMEM; 446 447 priv = netdev_priv(net_dev); 448 priv->net_dev = net_dev; 449 priv->dev = dev; 450 451 net_dev->netdev_ops = &xrx200_netdev_ops; 452 SET_NETDEV_DEV(net_dev, dev); 453 net_dev->min_mtu = ETH_ZLEN; 454 net_dev->max_mtu = XRX200_DMA_DATA_LEN; 455 456 /* load the memory ranges */ 457 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 458 if (!res) { 459 dev_err(dev, "failed to get resources\n"); 460 return -ENOENT; 461 } 462 463 priv->pmac_reg = devm_ioremap_resource(dev, res); 464 if (!priv->pmac_reg) { 465 dev_err(dev, "failed to request and remap io ranges\n"); 466 return -ENOMEM; 467 } 468 469 priv->chan_rx.dma.irq = platform_get_irq_byname(pdev, "rx"); 470 if (priv->chan_rx.dma.irq < 0) { 471 dev_err(dev, "failed to get RX IRQ, %i\n", 472 priv->chan_rx.dma.irq); 473 return -ENOENT; 474 } 475 priv->chan_tx.dma.irq = platform_get_irq_byname(pdev, "tx"); 476 if (priv->chan_tx.dma.irq < 0) { 477 dev_err(dev, "failed to get TX IRQ, %i\n", 478 priv->chan_tx.dma.irq); 479 return -ENOENT; 480 } 481 482 /* get the clock */ 483 priv->clk = devm_clk_get(dev, NULL); 484 if (IS_ERR(priv->clk)) { 485 dev_err(dev, "failed to get clock\n"); 486 return PTR_ERR(priv->clk); 487 } 488 489 mac = of_get_mac_address(np); 490 if (mac && is_valid_ether_addr(mac)) 491 ether_addr_copy(net_dev->dev_addr, mac); 492 else 493 eth_hw_addr_random(net_dev); 494 495 /* bring up the dma engine and IP core */ 496 err = xrx200_dma_init(priv); 497 if (err) 498 return err; 499 500 /* set IPG to 12 */ 501 xrx200_pmac_mask(priv, PMAC_RX_IPG_MASK, 0xb, PMAC_RX_IPG); 502 503 /* enable status header, enable CRC */ 504 xrx200_pmac_mask(priv, 0, 505 PMAC_HD_CTL_RST | PMAC_HD_CTL_AST | PMAC_HD_CTL_RXSH | 506 PMAC_HD_CTL_AS | PMAC_HD_CTL_AC | PMAC_HD_CTL_RC, 507 PMAC_HD_CTL); 508 509 /* setup NAPI */ 510 netif_napi_add(net_dev, &priv->chan_rx.napi, xrx200_poll_rx, 32); 511 netif_napi_add(net_dev, &priv->chan_tx.napi, xrx200_tx_housekeeping, 32); 512 513 platform_set_drvdata(pdev, priv); 514 515 err = register_netdev(net_dev); 516 if (err) 517 goto err_uninit_dma; 518 return err; 519 520 err_uninit_dma: 521 xrx200_hw_cleanup(priv); 522 523 return 0; 524 } 525 526 static int xrx200_remove(struct platform_device *pdev) 527 { 528 struct xrx200_priv *priv = platform_get_drvdata(pdev); 529 struct net_device *net_dev = priv->net_dev; 530 531 /* free stack related instances */ 532 netif_stop_queue(net_dev); 533 netif_napi_del(&priv->chan_tx.napi); 534 netif_napi_del(&priv->chan_rx.napi); 535 536 /* remove the actual device */ 537 unregister_netdev(net_dev); 538 539 /* shut down hardware */ 540 xrx200_hw_cleanup(priv); 541 542 return 0; 543 } 544 545 static const struct of_device_id xrx200_match[] = { 546 { .compatible = "lantiq,xrx200-net" }, 547 {}, 548 }; 549 MODULE_DEVICE_TABLE(of, xrx200_match); 550 551 static struct platform_driver xrx200_driver = { 552 .probe = xrx200_probe, 553 .remove = xrx200_remove, 554 .driver = { 555 .name = "lantiq,xrx200-net", 556 .of_match_table = xrx200_match, 557 }, 558 }; 559 560 module_platform_driver(xrx200_driver); 561 562 MODULE_AUTHOR("John Crispin <john@phrozen.org>"); 563 MODULE_DESCRIPTION("Lantiq SoC XRX200 ethernet"); 564 MODULE_LICENSE("GPL"); 565