1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Lantiq / Intel PMAC driver for XRX200 SoCs 4 * 5 * Copyright (C) 2010 Lantiq Deutschland 6 * Copyright (C) 2012 John Crispin <john@phrozen.org> 7 * Copyright (C) 2017 - 2018 Hauke Mehrtens <hauke@hauke-m.de> 8 */ 9 10 #include <linux/etherdevice.h> 11 #include <linux/module.h> 12 #include <linux/platform_device.h> 13 #include <linux/interrupt.h> 14 #include <linux/clk.h> 15 #include <linux/delay.h> 16 17 #include <linux/if_vlan.h> 18 19 #include <linux/of_net.h> 20 #include <linux/of_platform.h> 21 22 #include <xway_dma.h> 23 24 /* DMA */ 25 #define XRX200_DMA_DATA_LEN (SZ_64K - 1) 26 #define XRX200_DMA_RX 0 27 #define XRX200_DMA_TX 1 28 29 /* cpu port mac */ 30 #define PMAC_RX_IPG 0x0024 31 #define PMAC_RX_IPG_MASK 0xf 32 33 #define PMAC_HD_CTL 0x0000 34 /* Add Ethernet header to packets from DMA to PMAC */ 35 #define PMAC_HD_CTL_ADD BIT(0) 36 /* Add VLAN tag to Packets from DMA to PMAC */ 37 #define PMAC_HD_CTL_TAG BIT(1) 38 /* Add CRC to packets from DMA to PMAC */ 39 #define PMAC_HD_CTL_AC BIT(2) 40 /* Add status header to packets from PMAC to DMA */ 41 #define PMAC_HD_CTL_AS BIT(3) 42 /* Remove CRC from packets from PMAC to DMA */ 43 #define PMAC_HD_CTL_RC BIT(4) 44 /* Remove Layer-2 header from packets from PMAC to DMA */ 45 #define PMAC_HD_CTL_RL2 BIT(5) 46 /* Status header is present from DMA to PMAC */ 47 #define PMAC_HD_CTL_RXSH BIT(6) 48 /* Add special tag from PMAC to switch */ 49 #define PMAC_HD_CTL_AST BIT(7) 50 /* Remove specail Tag from PMAC to DMA */ 51 #define PMAC_HD_CTL_RST BIT(8) 52 /* Check CRC from DMA to PMAC */ 53 #define PMAC_HD_CTL_CCRC BIT(9) 54 /* Enable reaction to Pause frames in the PMAC */ 55 #define PMAC_HD_CTL_FC BIT(10) 56 57 struct xrx200_chan { 58 int tx_free; 59 60 struct napi_struct napi; 61 struct ltq_dma_channel dma; 62 struct sk_buff *skb[LTQ_DESC_NUM]; 63 64 struct xrx200_priv *priv; 65 }; 66 67 struct xrx200_priv { 68 struct clk *clk; 69 70 struct xrx200_chan chan_tx; 71 struct xrx200_chan chan_rx; 72 73 struct net_device *net_dev; 74 struct device *dev; 75 76 int tx_burst_len; 77 int rx_burst_len; 78 79 __iomem void *pmac_reg; 80 }; 81 82 static u32 xrx200_pmac_r32(struct xrx200_priv *priv, u32 offset) 83 { 84 return __raw_readl(priv->pmac_reg + offset); 85 } 86 87 static void xrx200_pmac_w32(struct xrx200_priv *priv, u32 val, u32 offset) 88 { 89 __raw_writel(val, priv->pmac_reg + offset); 90 } 91 92 static void xrx200_pmac_mask(struct xrx200_priv *priv, u32 clear, u32 set, 93 u32 offset) 94 { 95 u32 val = xrx200_pmac_r32(priv, offset); 96 97 val &= ~(clear); 98 val |= set; 99 xrx200_pmac_w32(priv, val, offset); 100 } 101 102 /* drop all the packets from the DMA ring */ 103 static void xrx200_flush_dma(struct xrx200_chan *ch) 104 { 105 int i; 106 107 for (i = 0; i < LTQ_DESC_NUM; i++) { 108 struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->dma.desc]; 109 110 if ((desc->ctl & (LTQ_DMA_OWN | LTQ_DMA_C)) != LTQ_DMA_C) 111 break; 112 113 desc->ctl = LTQ_DMA_OWN | LTQ_DMA_RX_OFFSET(NET_IP_ALIGN) | 114 (ch->priv->net_dev->mtu + VLAN_ETH_HLEN + 115 ETH_FCS_LEN); 116 ch->dma.desc++; 117 ch->dma.desc %= LTQ_DESC_NUM; 118 } 119 } 120 121 static int xrx200_open(struct net_device *net_dev) 122 { 123 struct xrx200_priv *priv = netdev_priv(net_dev); 124 125 napi_enable(&priv->chan_tx.napi); 126 ltq_dma_open(&priv->chan_tx.dma); 127 ltq_dma_enable_irq(&priv->chan_tx.dma); 128 129 napi_enable(&priv->chan_rx.napi); 130 ltq_dma_open(&priv->chan_rx.dma); 131 /* The boot loader does not always deactivate the receiving of frames 132 * on the ports and then some packets queue up in the PPE buffers. 133 * They already passed the PMAC so they do not have the tags 134 * configured here. Read the these packets here and drop them. 135 * The HW should have written them into memory after 10us 136 */ 137 usleep_range(20, 40); 138 xrx200_flush_dma(&priv->chan_rx); 139 ltq_dma_enable_irq(&priv->chan_rx.dma); 140 141 netif_wake_queue(net_dev); 142 143 return 0; 144 } 145 146 static int xrx200_close(struct net_device *net_dev) 147 { 148 struct xrx200_priv *priv = netdev_priv(net_dev); 149 150 netif_stop_queue(net_dev); 151 152 napi_disable(&priv->chan_rx.napi); 153 ltq_dma_close(&priv->chan_rx.dma); 154 155 napi_disable(&priv->chan_tx.napi); 156 ltq_dma_close(&priv->chan_tx.dma); 157 158 return 0; 159 } 160 161 static int xrx200_alloc_skb(struct xrx200_chan *ch) 162 { 163 int len = ch->priv->net_dev->mtu + VLAN_ETH_HLEN + ETH_FCS_LEN; 164 struct sk_buff *skb = ch->skb[ch->dma.desc]; 165 dma_addr_t mapping; 166 int ret = 0; 167 168 ch->skb[ch->dma.desc] = netdev_alloc_skb_ip_align(ch->priv->net_dev, 169 len); 170 if (!ch->skb[ch->dma.desc]) { 171 ret = -ENOMEM; 172 goto skip; 173 } 174 175 mapping = dma_map_single(ch->priv->dev, ch->skb[ch->dma.desc]->data, 176 len, DMA_FROM_DEVICE); 177 if (unlikely(dma_mapping_error(ch->priv->dev, mapping))) { 178 dev_kfree_skb_any(ch->skb[ch->dma.desc]); 179 ch->skb[ch->dma.desc] = skb; 180 ret = -ENOMEM; 181 goto skip; 182 } 183 184 ch->dma.desc_base[ch->dma.desc].addr = mapping; 185 /* Make sure the address is written before we give it to HW */ 186 wmb(); 187 skip: 188 ch->dma.desc_base[ch->dma.desc].ctl = 189 LTQ_DMA_OWN | LTQ_DMA_RX_OFFSET(NET_IP_ALIGN) | len; 190 191 return ret; 192 } 193 194 static int xrx200_hw_receive(struct xrx200_chan *ch) 195 { 196 struct xrx200_priv *priv = ch->priv; 197 struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->dma.desc]; 198 struct sk_buff *skb = ch->skb[ch->dma.desc]; 199 int len = (desc->ctl & LTQ_DMA_SIZE_MASK); 200 struct net_device *net_dev = priv->net_dev; 201 int ret; 202 203 ret = xrx200_alloc_skb(ch); 204 205 ch->dma.desc++; 206 ch->dma.desc %= LTQ_DESC_NUM; 207 208 if (ret) { 209 net_dev->stats.rx_dropped++; 210 netdev_err(net_dev, "failed to allocate new rx buffer\n"); 211 return ret; 212 } 213 214 skb_put(skb, len); 215 skb->protocol = eth_type_trans(skb, net_dev); 216 netif_receive_skb(skb); 217 net_dev->stats.rx_packets++; 218 net_dev->stats.rx_bytes += len - ETH_FCS_LEN; 219 220 return 0; 221 } 222 223 static int xrx200_poll_rx(struct napi_struct *napi, int budget) 224 { 225 struct xrx200_chan *ch = container_of(napi, 226 struct xrx200_chan, napi); 227 int rx = 0; 228 int ret; 229 230 while (rx < budget) { 231 struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->dma.desc]; 232 233 if ((desc->ctl & (LTQ_DMA_OWN | LTQ_DMA_C)) == LTQ_DMA_C) { 234 ret = xrx200_hw_receive(ch); 235 if (ret) 236 return ret; 237 rx++; 238 } else { 239 break; 240 } 241 } 242 243 if (rx < budget) { 244 if (napi_complete_done(&ch->napi, rx)) 245 ltq_dma_enable_irq(&ch->dma); 246 } 247 248 return rx; 249 } 250 251 static int xrx200_tx_housekeeping(struct napi_struct *napi, int budget) 252 { 253 struct xrx200_chan *ch = container_of(napi, 254 struct xrx200_chan, napi); 255 struct net_device *net_dev = ch->priv->net_dev; 256 int pkts = 0; 257 int bytes = 0; 258 259 netif_tx_lock(net_dev); 260 while (pkts < budget) { 261 struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->tx_free]; 262 263 if ((desc->ctl & (LTQ_DMA_OWN | LTQ_DMA_C)) == LTQ_DMA_C) { 264 struct sk_buff *skb = ch->skb[ch->tx_free]; 265 266 pkts++; 267 bytes += skb->len; 268 ch->skb[ch->tx_free] = NULL; 269 consume_skb(skb); 270 memset(&ch->dma.desc_base[ch->tx_free], 0, 271 sizeof(struct ltq_dma_desc)); 272 ch->tx_free++; 273 ch->tx_free %= LTQ_DESC_NUM; 274 } else { 275 break; 276 } 277 } 278 279 net_dev->stats.tx_packets += pkts; 280 net_dev->stats.tx_bytes += bytes; 281 netdev_completed_queue(ch->priv->net_dev, pkts, bytes); 282 283 netif_tx_unlock(net_dev); 284 if (netif_queue_stopped(net_dev)) 285 netif_wake_queue(net_dev); 286 287 if (pkts < budget) { 288 if (napi_complete_done(&ch->napi, pkts)) 289 ltq_dma_enable_irq(&ch->dma); 290 } 291 292 return pkts; 293 } 294 295 static netdev_tx_t xrx200_start_xmit(struct sk_buff *skb, 296 struct net_device *net_dev) 297 { 298 struct xrx200_priv *priv = netdev_priv(net_dev); 299 struct xrx200_chan *ch = &priv->chan_tx; 300 struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->dma.desc]; 301 u32 byte_offset; 302 dma_addr_t mapping; 303 int len; 304 305 skb->dev = net_dev; 306 if (skb_put_padto(skb, ETH_ZLEN)) { 307 net_dev->stats.tx_dropped++; 308 return NETDEV_TX_OK; 309 } 310 311 len = skb->len; 312 313 if ((desc->ctl & (LTQ_DMA_OWN | LTQ_DMA_C)) || ch->skb[ch->dma.desc]) { 314 netdev_err(net_dev, "tx ring full\n"); 315 netif_stop_queue(net_dev); 316 return NETDEV_TX_BUSY; 317 } 318 319 ch->skb[ch->dma.desc] = skb; 320 321 mapping = dma_map_single(priv->dev, skb->data, len, DMA_TO_DEVICE); 322 if (unlikely(dma_mapping_error(priv->dev, mapping))) 323 goto err_drop; 324 325 /* dma needs to start on a burst length value aligned address */ 326 byte_offset = mapping % (priv->tx_burst_len * 4); 327 328 desc->addr = mapping - byte_offset; 329 /* Make sure the address is written before we give it to HW */ 330 wmb(); 331 desc->ctl = LTQ_DMA_OWN | LTQ_DMA_SOP | LTQ_DMA_EOP | 332 LTQ_DMA_TX_OFFSET(byte_offset) | (len & LTQ_DMA_SIZE_MASK); 333 ch->dma.desc++; 334 ch->dma.desc %= LTQ_DESC_NUM; 335 if (ch->dma.desc == ch->tx_free) 336 netif_stop_queue(net_dev); 337 338 netdev_sent_queue(net_dev, len); 339 340 return NETDEV_TX_OK; 341 342 err_drop: 343 dev_kfree_skb(skb); 344 net_dev->stats.tx_dropped++; 345 net_dev->stats.tx_errors++; 346 return NETDEV_TX_OK; 347 } 348 349 static int 350 xrx200_change_mtu(struct net_device *net_dev, int new_mtu) 351 { 352 struct xrx200_priv *priv = netdev_priv(net_dev); 353 struct xrx200_chan *ch_rx = &priv->chan_rx; 354 int old_mtu = net_dev->mtu; 355 bool running = false; 356 struct sk_buff *skb; 357 int curr_desc; 358 int ret = 0; 359 360 net_dev->mtu = new_mtu; 361 362 if (new_mtu <= old_mtu) 363 return ret; 364 365 running = netif_running(net_dev); 366 if (running) { 367 napi_disable(&ch_rx->napi); 368 ltq_dma_close(&ch_rx->dma); 369 } 370 371 xrx200_poll_rx(&ch_rx->napi, LTQ_DESC_NUM); 372 curr_desc = ch_rx->dma.desc; 373 374 for (ch_rx->dma.desc = 0; ch_rx->dma.desc < LTQ_DESC_NUM; 375 ch_rx->dma.desc++) { 376 skb = ch_rx->skb[ch_rx->dma.desc]; 377 ret = xrx200_alloc_skb(ch_rx); 378 if (ret) { 379 net_dev->mtu = old_mtu; 380 break; 381 } 382 dev_kfree_skb_any(skb); 383 } 384 385 ch_rx->dma.desc = curr_desc; 386 if (running) { 387 napi_enable(&ch_rx->napi); 388 ltq_dma_open(&ch_rx->dma); 389 ltq_dma_enable_irq(&ch_rx->dma); 390 } 391 392 return ret; 393 } 394 395 static const struct net_device_ops xrx200_netdev_ops = { 396 .ndo_open = xrx200_open, 397 .ndo_stop = xrx200_close, 398 .ndo_start_xmit = xrx200_start_xmit, 399 .ndo_change_mtu = xrx200_change_mtu, 400 .ndo_set_mac_address = eth_mac_addr, 401 .ndo_validate_addr = eth_validate_addr, 402 }; 403 404 static irqreturn_t xrx200_dma_irq(int irq, void *ptr) 405 { 406 struct xrx200_chan *ch = ptr; 407 408 if (napi_schedule_prep(&ch->napi)) { 409 ltq_dma_disable_irq(&ch->dma); 410 __napi_schedule(&ch->napi); 411 } 412 413 ltq_dma_ack_irq(&ch->dma); 414 415 return IRQ_HANDLED; 416 } 417 418 static int xrx200_dma_init(struct xrx200_priv *priv) 419 { 420 struct xrx200_chan *ch_rx = &priv->chan_rx; 421 struct xrx200_chan *ch_tx = &priv->chan_tx; 422 int ret = 0; 423 int i; 424 425 ltq_dma_init_port(DMA_PORT_ETOP, priv->tx_burst_len, rx_burst_len); 426 427 ch_rx->dma.nr = XRX200_DMA_RX; 428 ch_rx->dma.dev = priv->dev; 429 ch_rx->priv = priv; 430 431 ltq_dma_alloc_rx(&ch_rx->dma); 432 for (ch_rx->dma.desc = 0; ch_rx->dma.desc < LTQ_DESC_NUM; 433 ch_rx->dma.desc++) { 434 ret = xrx200_alloc_skb(ch_rx); 435 if (ret) 436 goto rx_free; 437 } 438 ch_rx->dma.desc = 0; 439 ret = devm_request_irq(priv->dev, ch_rx->dma.irq, xrx200_dma_irq, 0, 440 "xrx200_net_rx", &priv->chan_rx); 441 if (ret) { 442 dev_err(priv->dev, "failed to request RX irq %d\n", 443 ch_rx->dma.irq); 444 goto rx_ring_free; 445 } 446 447 ch_tx->dma.nr = XRX200_DMA_TX; 448 ch_tx->dma.dev = priv->dev; 449 ch_tx->priv = priv; 450 451 ltq_dma_alloc_tx(&ch_tx->dma); 452 ret = devm_request_irq(priv->dev, ch_tx->dma.irq, xrx200_dma_irq, 0, 453 "xrx200_net_tx", &priv->chan_tx); 454 if (ret) { 455 dev_err(priv->dev, "failed to request TX irq %d\n", 456 ch_tx->dma.irq); 457 goto tx_free; 458 } 459 460 return ret; 461 462 tx_free: 463 ltq_dma_free(&ch_tx->dma); 464 465 rx_ring_free: 466 /* free the allocated RX ring */ 467 for (i = 0; i < LTQ_DESC_NUM; i++) { 468 if (priv->chan_rx.skb[i]) 469 dev_kfree_skb_any(priv->chan_rx.skb[i]); 470 } 471 472 rx_free: 473 ltq_dma_free(&ch_rx->dma); 474 return ret; 475 } 476 477 static void xrx200_hw_cleanup(struct xrx200_priv *priv) 478 { 479 int i; 480 481 ltq_dma_free(&priv->chan_tx.dma); 482 ltq_dma_free(&priv->chan_rx.dma); 483 484 /* free the allocated RX ring */ 485 for (i = 0; i < LTQ_DESC_NUM; i++) 486 dev_kfree_skb_any(priv->chan_rx.skb[i]); 487 } 488 489 static int xrx200_probe(struct platform_device *pdev) 490 { 491 struct device *dev = &pdev->dev; 492 struct device_node *np = dev->of_node; 493 struct xrx200_priv *priv; 494 struct net_device *net_dev; 495 int err; 496 497 /* alloc the network device */ 498 net_dev = devm_alloc_etherdev(dev, sizeof(struct xrx200_priv)); 499 if (!net_dev) 500 return -ENOMEM; 501 502 priv = netdev_priv(net_dev); 503 priv->net_dev = net_dev; 504 priv->dev = dev; 505 506 net_dev->netdev_ops = &xrx200_netdev_ops; 507 SET_NETDEV_DEV(net_dev, dev); 508 net_dev->min_mtu = ETH_ZLEN; 509 net_dev->max_mtu = XRX200_DMA_DATA_LEN - VLAN_ETH_HLEN - ETH_FCS_LEN; 510 511 /* load the memory ranges */ 512 priv->pmac_reg = devm_platform_get_and_ioremap_resource(pdev, 0, NULL); 513 if (IS_ERR(priv->pmac_reg)) 514 return PTR_ERR(priv->pmac_reg); 515 516 priv->chan_rx.dma.irq = platform_get_irq_byname(pdev, "rx"); 517 if (priv->chan_rx.dma.irq < 0) 518 return -ENOENT; 519 priv->chan_tx.dma.irq = platform_get_irq_byname(pdev, "tx"); 520 if (priv->chan_tx.dma.irq < 0) 521 return -ENOENT; 522 523 /* get the clock */ 524 priv->clk = devm_clk_get(dev, NULL); 525 if (IS_ERR(priv->clk)) { 526 dev_err(dev, "failed to get clock\n"); 527 return PTR_ERR(priv->clk); 528 } 529 530 err = of_get_ethdev_address(np, net_dev); 531 if (err) 532 eth_hw_addr_random(net_dev); 533 534 err = device_property_read_u32(dev, "lantiq,tx-burst-length", &priv->tx_burst_len); 535 if (err < 0) { 536 dev_err(dev, "unable to read tx-burst-length property\n"); 537 return err; 538 } 539 540 err = device_property_read_u32(dev, "lantiq,rx-burst-length", &priv->rx_burst_len); 541 if (err < 0) { 542 dev_err(dev, "unable to read rx-burst-length property\n"); 543 return err; 544 } 545 546 /* bring up the dma engine and IP core */ 547 err = xrx200_dma_init(priv); 548 if (err) 549 return err; 550 551 /* enable clock gate */ 552 err = clk_prepare_enable(priv->clk); 553 if (err) 554 goto err_uninit_dma; 555 556 /* set IPG to 12 */ 557 xrx200_pmac_mask(priv, PMAC_RX_IPG_MASK, 0xb, PMAC_RX_IPG); 558 559 /* enable status header, enable CRC */ 560 xrx200_pmac_mask(priv, 0, 561 PMAC_HD_CTL_RST | PMAC_HD_CTL_AST | PMAC_HD_CTL_RXSH | 562 PMAC_HD_CTL_AS | PMAC_HD_CTL_AC | PMAC_HD_CTL_RC, 563 PMAC_HD_CTL); 564 565 /* setup NAPI */ 566 netif_napi_add(net_dev, &priv->chan_rx.napi, xrx200_poll_rx, 32); 567 netif_tx_napi_add(net_dev, &priv->chan_tx.napi, xrx200_tx_housekeeping, 32); 568 569 platform_set_drvdata(pdev, priv); 570 571 err = register_netdev(net_dev); 572 if (err) 573 goto err_unprepare_clk; 574 575 return 0; 576 577 err_unprepare_clk: 578 clk_disable_unprepare(priv->clk); 579 580 err_uninit_dma: 581 xrx200_hw_cleanup(priv); 582 583 return err; 584 } 585 586 static int xrx200_remove(struct platform_device *pdev) 587 { 588 struct xrx200_priv *priv = platform_get_drvdata(pdev); 589 struct net_device *net_dev = priv->net_dev; 590 591 /* free stack related instances */ 592 netif_stop_queue(net_dev); 593 netif_napi_del(&priv->chan_tx.napi); 594 netif_napi_del(&priv->chan_rx.napi); 595 596 /* remove the actual device */ 597 unregister_netdev(net_dev); 598 599 /* release the clock */ 600 clk_disable_unprepare(priv->clk); 601 602 /* shut down hardware */ 603 xrx200_hw_cleanup(priv); 604 605 return 0; 606 } 607 608 static const struct of_device_id xrx200_match[] = { 609 { .compatible = "lantiq,xrx200-net" }, 610 {}, 611 }; 612 MODULE_DEVICE_TABLE(of, xrx200_match); 613 614 static struct platform_driver xrx200_driver = { 615 .probe = xrx200_probe, 616 .remove = xrx200_remove, 617 .driver = { 618 .name = "lantiq,xrx200-net", 619 .of_match_table = xrx200_match, 620 }, 621 }; 622 623 module_platform_driver(xrx200_driver); 624 625 MODULE_AUTHOR("John Crispin <john@phrozen.org>"); 626 MODULE_DESCRIPTION("Lantiq SoC XRX200 ethernet"); 627 MODULE_LICENSE("GPL"); 628