1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Lantiq / Intel PMAC driver for XRX200 SoCs 4 * 5 * Copyright (C) 2010 Lantiq Deutschland 6 * Copyright (C) 2012 John Crispin <john@phrozen.org> 7 * Copyright (C) 2017 - 2018 Hauke Mehrtens <hauke@hauke-m.de> 8 */ 9 10 #include <linux/etherdevice.h> 11 #include <linux/module.h> 12 #include <linux/platform_device.h> 13 #include <linux/interrupt.h> 14 #include <linux/clk.h> 15 #include <linux/delay.h> 16 17 #include <linux/of_net.h> 18 #include <linux/of_platform.h> 19 20 #include <xway_dma.h> 21 22 /* DMA */ 23 #define XRX200_DMA_DATA_LEN 0x600 24 #define XRX200_DMA_RX 0 25 #define XRX200_DMA_TX 1 26 27 /* cpu port mac */ 28 #define PMAC_RX_IPG 0x0024 29 #define PMAC_RX_IPG_MASK 0xf 30 31 #define PMAC_HD_CTL 0x0000 32 /* Add Ethernet header to packets from DMA to PMAC */ 33 #define PMAC_HD_CTL_ADD BIT(0) 34 /* Add VLAN tag to Packets from DMA to PMAC */ 35 #define PMAC_HD_CTL_TAG BIT(1) 36 /* Add CRC to packets from DMA to PMAC */ 37 #define PMAC_HD_CTL_AC BIT(2) 38 /* Add status header to packets from PMAC to DMA */ 39 #define PMAC_HD_CTL_AS BIT(3) 40 /* Remove CRC from packets from PMAC to DMA */ 41 #define PMAC_HD_CTL_RC BIT(4) 42 /* Remove Layer-2 header from packets from PMAC to DMA */ 43 #define PMAC_HD_CTL_RL2 BIT(5) 44 /* Status header is present from DMA to PMAC */ 45 #define PMAC_HD_CTL_RXSH BIT(6) 46 /* Add special tag from PMAC to switch */ 47 #define PMAC_HD_CTL_AST BIT(7) 48 /* Remove specail Tag from PMAC to DMA */ 49 #define PMAC_HD_CTL_RST BIT(8) 50 /* Check CRC from DMA to PMAC */ 51 #define PMAC_HD_CTL_CCRC BIT(9) 52 /* Enable reaction to Pause frames in the PMAC */ 53 #define PMAC_HD_CTL_FC BIT(10) 54 55 struct xrx200_chan { 56 int tx_free; 57 58 struct napi_struct napi; 59 struct ltq_dma_channel dma; 60 struct sk_buff *skb[LTQ_DESC_NUM]; 61 62 struct xrx200_priv *priv; 63 }; 64 65 struct xrx200_priv { 66 struct clk *clk; 67 68 struct xrx200_chan chan_tx; 69 struct xrx200_chan chan_rx; 70 71 struct net_device *net_dev; 72 struct device *dev; 73 74 __iomem void *pmac_reg; 75 }; 76 77 static u32 xrx200_pmac_r32(struct xrx200_priv *priv, u32 offset) 78 { 79 return __raw_readl(priv->pmac_reg + offset); 80 } 81 82 static void xrx200_pmac_w32(struct xrx200_priv *priv, u32 val, u32 offset) 83 { 84 __raw_writel(val, priv->pmac_reg + offset); 85 } 86 87 static void xrx200_pmac_mask(struct xrx200_priv *priv, u32 clear, u32 set, 88 u32 offset) 89 { 90 u32 val = xrx200_pmac_r32(priv, offset); 91 92 val &= ~(clear); 93 val |= set; 94 xrx200_pmac_w32(priv, val, offset); 95 } 96 97 /* drop all the packets from the DMA ring */ 98 static void xrx200_flush_dma(struct xrx200_chan *ch) 99 { 100 int i; 101 102 for (i = 0; i < LTQ_DESC_NUM; i++) { 103 struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->dma.desc]; 104 105 if ((desc->ctl & (LTQ_DMA_OWN | LTQ_DMA_C)) != LTQ_DMA_C) 106 break; 107 108 desc->ctl = LTQ_DMA_OWN | LTQ_DMA_RX_OFFSET(NET_IP_ALIGN) | 109 XRX200_DMA_DATA_LEN; 110 ch->dma.desc++; 111 ch->dma.desc %= LTQ_DESC_NUM; 112 } 113 } 114 115 static int xrx200_open(struct net_device *net_dev) 116 { 117 struct xrx200_priv *priv = netdev_priv(net_dev); 118 119 napi_enable(&priv->chan_tx.napi); 120 ltq_dma_open(&priv->chan_tx.dma); 121 ltq_dma_enable_irq(&priv->chan_tx.dma); 122 123 napi_enable(&priv->chan_rx.napi); 124 ltq_dma_open(&priv->chan_rx.dma); 125 /* The boot loader does not always deactivate the receiving of frames 126 * on the ports and then some packets queue up in the PPE buffers. 127 * They already passed the PMAC so they do not have the tags 128 * configured here. Read the these packets here and drop them. 129 * The HW should have written them into memory after 10us 130 */ 131 usleep_range(20, 40); 132 xrx200_flush_dma(&priv->chan_rx); 133 ltq_dma_enable_irq(&priv->chan_rx.dma); 134 135 netif_wake_queue(net_dev); 136 137 return 0; 138 } 139 140 static int xrx200_close(struct net_device *net_dev) 141 { 142 struct xrx200_priv *priv = netdev_priv(net_dev); 143 144 netif_stop_queue(net_dev); 145 146 napi_disable(&priv->chan_rx.napi); 147 ltq_dma_close(&priv->chan_rx.dma); 148 149 napi_disable(&priv->chan_tx.napi); 150 ltq_dma_close(&priv->chan_tx.dma); 151 152 return 0; 153 } 154 155 static int xrx200_alloc_skb(struct xrx200_chan *ch) 156 { 157 dma_addr_t mapping; 158 int ret = 0; 159 160 ch->skb[ch->dma.desc] = netdev_alloc_skb_ip_align(ch->priv->net_dev, 161 XRX200_DMA_DATA_LEN); 162 if (!ch->skb[ch->dma.desc]) { 163 ret = -ENOMEM; 164 goto skip; 165 } 166 167 mapping = dma_map_single(ch->priv->dev, ch->skb[ch->dma.desc]->data, 168 XRX200_DMA_DATA_LEN, DMA_FROM_DEVICE); 169 if (unlikely(dma_mapping_error(ch->priv->dev, mapping))) { 170 dev_kfree_skb_any(ch->skb[ch->dma.desc]); 171 ret = -ENOMEM; 172 goto skip; 173 } 174 175 ch->dma.desc_base[ch->dma.desc].addr = mapping; 176 /* Make sure the address is written before we give it to HW */ 177 wmb(); 178 skip: 179 ch->dma.desc_base[ch->dma.desc].ctl = 180 LTQ_DMA_OWN | LTQ_DMA_RX_OFFSET(NET_IP_ALIGN) | 181 XRX200_DMA_DATA_LEN; 182 183 return ret; 184 } 185 186 static int xrx200_hw_receive(struct xrx200_chan *ch) 187 { 188 struct xrx200_priv *priv = ch->priv; 189 struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->dma.desc]; 190 struct sk_buff *skb = ch->skb[ch->dma.desc]; 191 int len = (desc->ctl & LTQ_DMA_SIZE_MASK); 192 struct net_device *net_dev = priv->net_dev; 193 int ret; 194 195 ret = xrx200_alloc_skb(ch); 196 197 ch->dma.desc++; 198 ch->dma.desc %= LTQ_DESC_NUM; 199 200 if (ret) { 201 ch->skb[ch->dma.desc] = skb; 202 net_dev->stats.rx_dropped++; 203 netdev_err(net_dev, "failed to allocate new rx buffer\n"); 204 return ret; 205 } 206 207 skb_put(skb, len); 208 skb->protocol = eth_type_trans(skb, net_dev); 209 netif_receive_skb(skb); 210 net_dev->stats.rx_packets++; 211 net_dev->stats.rx_bytes += len - ETH_FCS_LEN; 212 213 return 0; 214 } 215 216 static int xrx200_poll_rx(struct napi_struct *napi, int budget) 217 { 218 struct xrx200_chan *ch = container_of(napi, 219 struct xrx200_chan, napi); 220 int rx = 0; 221 int ret; 222 223 while (rx < budget) { 224 struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->dma.desc]; 225 226 if ((desc->ctl & (LTQ_DMA_OWN | LTQ_DMA_C)) == LTQ_DMA_C) { 227 ret = xrx200_hw_receive(ch); 228 if (ret) 229 return ret; 230 rx++; 231 } else { 232 break; 233 } 234 } 235 236 if (rx < budget) { 237 if (napi_complete_done(&ch->napi, rx)) 238 ltq_dma_enable_irq(&ch->dma); 239 } 240 241 return rx; 242 } 243 244 static int xrx200_tx_housekeeping(struct napi_struct *napi, int budget) 245 { 246 struct xrx200_chan *ch = container_of(napi, 247 struct xrx200_chan, napi); 248 struct net_device *net_dev = ch->priv->net_dev; 249 int pkts = 0; 250 int bytes = 0; 251 252 netif_tx_lock(net_dev); 253 while (pkts < budget) { 254 struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->tx_free]; 255 256 if ((desc->ctl & (LTQ_DMA_OWN | LTQ_DMA_C)) == LTQ_DMA_C) { 257 struct sk_buff *skb = ch->skb[ch->tx_free]; 258 259 pkts++; 260 bytes += skb->len; 261 ch->skb[ch->tx_free] = NULL; 262 consume_skb(skb); 263 memset(&ch->dma.desc_base[ch->tx_free], 0, 264 sizeof(struct ltq_dma_desc)); 265 ch->tx_free++; 266 ch->tx_free %= LTQ_DESC_NUM; 267 } else { 268 break; 269 } 270 } 271 272 net_dev->stats.tx_packets += pkts; 273 net_dev->stats.tx_bytes += bytes; 274 netdev_completed_queue(ch->priv->net_dev, pkts, bytes); 275 276 netif_tx_unlock(net_dev); 277 if (netif_queue_stopped(net_dev)) 278 netif_wake_queue(net_dev); 279 280 if (pkts < budget) { 281 if (napi_complete_done(&ch->napi, pkts)) 282 ltq_dma_enable_irq(&ch->dma); 283 } 284 285 return pkts; 286 } 287 288 static netdev_tx_t xrx200_start_xmit(struct sk_buff *skb, 289 struct net_device *net_dev) 290 { 291 struct xrx200_priv *priv = netdev_priv(net_dev); 292 struct xrx200_chan *ch = &priv->chan_tx; 293 struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->dma.desc]; 294 u32 byte_offset; 295 dma_addr_t mapping; 296 int len; 297 298 skb->dev = net_dev; 299 if (skb_put_padto(skb, ETH_ZLEN)) { 300 net_dev->stats.tx_dropped++; 301 return NETDEV_TX_OK; 302 } 303 304 len = skb->len; 305 306 if ((desc->ctl & (LTQ_DMA_OWN | LTQ_DMA_C)) || ch->skb[ch->dma.desc]) { 307 netdev_err(net_dev, "tx ring full\n"); 308 netif_stop_queue(net_dev); 309 return NETDEV_TX_BUSY; 310 } 311 312 ch->skb[ch->dma.desc] = skb; 313 314 mapping = dma_map_single(priv->dev, skb->data, len, DMA_TO_DEVICE); 315 if (unlikely(dma_mapping_error(priv->dev, mapping))) 316 goto err_drop; 317 318 /* dma needs to start on a 16 byte aligned address */ 319 byte_offset = mapping % 16; 320 321 desc->addr = mapping - byte_offset; 322 /* Make sure the address is written before we give it to HW */ 323 wmb(); 324 desc->ctl = LTQ_DMA_OWN | LTQ_DMA_SOP | LTQ_DMA_EOP | 325 LTQ_DMA_TX_OFFSET(byte_offset) | (len & LTQ_DMA_SIZE_MASK); 326 ch->dma.desc++; 327 ch->dma.desc %= LTQ_DESC_NUM; 328 if (ch->dma.desc == ch->tx_free) 329 netif_stop_queue(net_dev); 330 331 netdev_sent_queue(net_dev, len); 332 333 return NETDEV_TX_OK; 334 335 err_drop: 336 dev_kfree_skb(skb); 337 net_dev->stats.tx_dropped++; 338 net_dev->stats.tx_errors++; 339 return NETDEV_TX_OK; 340 } 341 342 static const struct net_device_ops xrx200_netdev_ops = { 343 .ndo_open = xrx200_open, 344 .ndo_stop = xrx200_close, 345 .ndo_start_xmit = xrx200_start_xmit, 346 .ndo_set_mac_address = eth_mac_addr, 347 .ndo_validate_addr = eth_validate_addr, 348 }; 349 350 static irqreturn_t xrx200_dma_irq(int irq, void *ptr) 351 { 352 struct xrx200_chan *ch = ptr; 353 354 if (napi_schedule_prep(&ch->napi)) { 355 __napi_schedule(&ch->napi); 356 ltq_dma_disable_irq(&ch->dma); 357 } 358 359 ltq_dma_ack_irq(&ch->dma); 360 361 return IRQ_HANDLED; 362 } 363 364 static int xrx200_dma_init(struct xrx200_priv *priv) 365 { 366 struct xrx200_chan *ch_rx = &priv->chan_rx; 367 struct xrx200_chan *ch_tx = &priv->chan_tx; 368 int ret = 0; 369 int i; 370 371 ltq_dma_init_port(DMA_PORT_ETOP); 372 373 ch_rx->dma.nr = XRX200_DMA_RX; 374 ch_rx->dma.dev = priv->dev; 375 ch_rx->priv = priv; 376 377 ltq_dma_alloc_rx(&ch_rx->dma); 378 for (ch_rx->dma.desc = 0; ch_rx->dma.desc < LTQ_DESC_NUM; 379 ch_rx->dma.desc++) { 380 ret = xrx200_alloc_skb(ch_rx); 381 if (ret) 382 goto rx_free; 383 } 384 ch_rx->dma.desc = 0; 385 ret = devm_request_irq(priv->dev, ch_rx->dma.irq, xrx200_dma_irq, 0, 386 "xrx200_net_rx", &priv->chan_rx); 387 if (ret) { 388 dev_err(priv->dev, "failed to request RX irq %d\n", 389 ch_rx->dma.irq); 390 goto rx_ring_free; 391 } 392 393 ch_tx->dma.nr = XRX200_DMA_TX; 394 ch_tx->dma.dev = priv->dev; 395 ch_tx->priv = priv; 396 397 ltq_dma_alloc_tx(&ch_tx->dma); 398 ret = devm_request_irq(priv->dev, ch_tx->dma.irq, xrx200_dma_irq, 0, 399 "xrx200_net_tx", &priv->chan_tx); 400 if (ret) { 401 dev_err(priv->dev, "failed to request TX irq %d\n", 402 ch_tx->dma.irq); 403 goto tx_free; 404 } 405 406 return ret; 407 408 tx_free: 409 ltq_dma_free(&ch_tx->dma); 410 411 rx_ring_free: 412 /* free the allocated RX ring */ 413 for (i = 0; i < LTQ_DESC_NUM; i++) { 414 if (priv->chan_rx.skb[i]) 415 dev_kfree_skb_any(priv->chan_rx.skb[i]); 416 } 417 418 rx_free: 419 ltq_dma_free(&ch_rx->dma); 420 return ret; 421 } 422 423 static void xrx200_hw_cleanup(struct xrx200_priv *priv) 424 { 425 int i; 426 427 ltq_dma_free(&priv->chan_tx.dma); 428 ltq_dma_free(&priv->chan_rx.dma); 429 430 /* free the allocated RX ring */ 431 for (i = 0; i < LTQ_DESC_NUM; i++) 432 dev_kfree_skb_any(priv->chan_rx.skb[i]); 433 } 434 435 static int xrx200_probe(struct platform_device *pdev) 436 { 437 struct device *dev = &pdev->dev; 438 struct device_node *np = dev->of_node; 439 struct resource *res; 440 struct xrx200_priv *priv; 441 struct net_device *net_dev; 442 int err; 443 444 /* alloc the network device */ 445 net_dev = devm_alloc_etherdev(dev, sizeof(struct xrx200_priv)); 446 if (!net_dev) 447 return -ENOMEM; 448 449 priv = netdev_priv(net_dev); 450 priv->net_dev = net_dev; 451 priv->dev = dev; 452 453 net_dev->netdev_ops = &xrx200_netdev_ops; 454 SET_NETDEV_DEV(net_dev, dev); 455 net_dev->min_mtu = ETH_ZLEN; 456 net_dev->max_mtu = XRX200_DMA_DATA_LEN; 457 458 /* load the memory ranges */ 459 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 460 if (!res) { 461 dev_err(dev, "failed to get resources\n"); 462 return -ENOENT; 463 } 464 465 priv->pmac_reg = devm_ioremap_resource(dev, res); 466 if (IS_ERR(priv->pmac_reg)) 467 return PTR_ERR(priv->pmac_reg); 468 469 priv->chan_rx.dma.irq = platform_get_irq_byname(pdev, "rx"); 470 if (priv->chan_rx.dma.irq < 0) 471 return -ENOENT; 472 priv->chan_tx.dma.irq = platform_get_irq_byname(pdev, "tx"); 473 if (priv->chan_tx.dma.irq < 0) 474 return -ENOENT; 475 476 /* get the clock */ 477 priv->clk = devm_clk_get(dev, NULL); 478 if (IS_ERR(priv->clk)) { 479 dev_err(dev, "failed to get clock\n"); 480 return PTR_ERR(priv->clk); 481 } 482 483 err = of_get_mac_address(np, net_dev->dev_addr); 484 if (err) 485 eth_hw_addr_random(net_dev); 486 487 /* bring up the dma engine and IP core */ 488 err = xrx200_dma_init(priv); 489 if (err) 490 return err; 491 492 /* enable clock gate */ 493 err = clk_prepare_enable(priv->clk); 494 if (err) 495 goto err_uninit_dma; 496 497 /* set IPG to 12 */ 498 xrx200_pmac_mask(priv, PMAC_RX_IPG_MASK, 0xb, PMAC_RX_IPG); 499 500 /* enable status header, enable CRC */ 501 xrx200_pmac_mask(priv, 0, 502 PMAC_HD_CTL_RST | PMAC_HD_CTL_AST | PMAC_HD_CTL_RXSH | 503 PMAC_HD_CTL_AS | PMAC_HD_CTL_AC | PMAC_HD_CTL_RC, 504 PMAC_HD_CTL); 505 506 /* setup NAPI */ 507 netif_napi_add(net_dev, &priv->chan_rx.napi, xrx200_poll_rx, 32); 508 netif_tx_napi_add(net_dev, &priv->chan_tx.napi, xrx200_tx_housekeeping, 32); 509 510 platform_set_drvdata(pdev, priv); 511 512 err = register_netdev(net_dev); 513 if (err) 514 goto err_unprepare_clk; 515 516 return 0; 517 518 err_unprepare_clk: 519 clk_disable_unprepare(priv->clk); 520 521 err_uninit_dma: 522 xrx200_hw_cleanup(priv); 523 524 return err; 525 } 526 527 static int xrx200_remove(struct platform_device *pdev) 528 { 529 struct xrx200_priv *priv = platform_get_drvdata(pdev); 530 struct net_device *net_dev = priv->net_dev; 531 532 /* free stack related instances */ 533 netif_stop_queue(net_dev); 534 netif_napi_del(&priv->chan_tx.napi); 535 netif_napi_del(&priv->chan_rx.napi); 536 537 /* remove the actual device */ 538 unregister_netdev(net_dev); 539 540 /* release the clock */ 541 clk_disable_unprepare(priv->clk); 542 543 /* shut down hardware */ 544 xrx200_hw_cleanup(priv); 545 546 return 0; 547 } 548 549 static const struct of_device_id xrx200_match[] = { 550 { .compatible = "lantiq,xrx200-net" }, 551 {}, 552 }; 553 MODULE_DEVICE_TABLE(of, xrx200_match); 554 555 static struct platform_driver xrx200_driver = { 556 .probe = xrx200_probe, 557 .remove = xrx200_remove, 558 .driver = { 559 .name = "lantiq,xrx200-net", 560 .of_match_table = xrx200_match, 561 }, 562 }; 563 564 module_platform_driver(xrx200_driver); 565 566 MODULE_AUTHOR("John Crispin <john@phrozen.org>"); 567 MODULE_DESCRIPTION("Lantiq SoC XRX200 ethernet"); 568 MODULE_LICENSE("GPL"); 569