1 /* 2 * This program is free software; you can redistribute it and/or modify it 3 * under the terms of the GNU General Public License version 2 as published 4 * by the Free Software Foundation. 5 * 6 * This program is distributed in the hope that it will be useful, 7 * but WITHOUT ANY WARRANTY; without even the implied warranty of 8 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 9 * GNU General Public License for more details. 10 * 11 * You should have received a copy of the GNU General Public License 12 * along with this program; if not, see <http://www.gnu.org/licenses/>. 13 * 14 * Copyright (C) 2011 John Crispin <blogic@openwrt.org> 15 */ 16 17 #include <linux/kernel.h> 18 #include <linux/slab.h> 19 #include <linux/errno.h> 20 #include <linux/types.h> 21 #include <linux/interrupt.h> 22 #include <linux/uaccess.h> 23 #include <linux/in.h> 24 #include <linux/netdevice.h> 25 #include <linux/etherdevice.h> 26 #include <linux/phy.h> 27 #include <linux/ip.h> 28 #include <linux/tcp.h> 29 #include <linux/skbuff.h> 30 #include <linux/mm.h> 31 #include <linux/platform_device.h> 32 #include <linux/ethtool.h> 33 #include <linux/init.h> 34 #include <linux/delay.h> 35 #include <linux/io.h> 36 #include <linux/dma-mapping.h> 37 #include <linux/module.h> 38 39 #include <asm/checksum.h> 40 41 #include <lantiq_soc.h> 42 #include <xway_dma.h> 43 #include <lantiq_platform.h> 44 45 #define LTQ_ETOP_MDIO 0x11804 46 #define MDIO_REQUEST 0x80000000 47 #define MDIO_READ 0x40000000 48 #define MDIO_ADDR_MASK 0x1f 49 #define MDIO_ADDR_OFFSET 0x15 50 #define MDIO_REG_MASK 0x1f 51 #define MDIO_REG_OFFSET 0x10 52 #define MDIO_VAL_MASK 0xffff 53 54 #define PPE32_CGEN 0x800 55 #define LQ_PPE32_ENET_MAC_CFG 0x1840 56 57 #define LTQ_ETOP_ENETS0 0x11850 58 #define LTQ_ETOP_MAC_DA0 0x1186C 59 #define LTQ_ETOP_MAC_DA1 0x11870 60 #define LTQ_ETOP_CFG 0x16020 61 #define LTQ_ETOP_IGPLEN 0x16080 62 63 #define MAX_DMA_CHAN 0x8 64 #define MAX_DMA_CRC_LEN 0x4 65 #define MAX_DMA_DATA_LEN 0x600 66 67 #define ETOP_FTCU BIT(28) 68 #define ETOP_MII_MASK 0xf 69 #define ETOP_MII_NORMAL 0xd 70 #define ETOP_MII_REVERSE 0xe 71 #define ETOP_PLEN_UNDER 0x40 72 #define ETOP_CGEN 0x800 73 74 /* use 2 static channels for TX/RX */ 75 #define LTQ_ETOP_TX_CHANNEL 1 76 #define LTQ_ETOP_RX_CHANNEL 6 77 #define IS_TX(x) (x == LTQ_ETOP_TX_CHANNEL) 78 #define IS_RX(x) (x == LTQ_ETOP_RX_CHANNEL) 79 80 #define ltq_etop_r32(x) ltq_r32(ltq_etop_membase + (x)) 81 #define ltq_etop_w32(x, y) ltq_w32(x, ltq_etop_membase + (y)) 82 #define ltq_etop_w32_mask(x, y, z) \ 83 ltq_w32_mask(x, y, ltq_etop_membase + (z)) 84 85 #define DRV_VERSION "1.0" 86 87 static void __iomem *ltq_etop_membase; 88 89 struct ltq_etop_chan { 90 int idx; 91 int tx_free; 92 struct net_device *netdev; 93 struct napi_struct napi; 94 struct ltq_dma_channel dma; 95 struct sk_buff *skb[LTQ_DESC_NUM]; 96 }; 97 98 struct ltq_etop_priv { 99 struct net_device *netdev; 100 struct platform_device *pdev; 101 struct ltq_eth_data *pldata; 102 struct resource *res; 103 104 struct mii_bus *mii_bus; 105 106 struct ltq_etop_chan ch[MAX_DMA_CHAN]; 107 int tx_free[MAX_DMA_CHAN >> 1]; 108 109 spinlock_t lock; 110 }; 111 112 static int 113 ltq_etop_alloc_skb(struct ltq_etop_chan *ch) 114 { 115 ch->skb[ch->dma.desc] = netdev_alloc_skb(ch->netdev, MAX_DMA_DATA_LEN); 116 if (!ch->skb[ch->dma.desc]) 117 return -ENOMEM; 118 ch->dma.desc_base[ch->dma.desc].addr = dma_map_single(NULL, 119 ch->skb[ch->dma.desc]->data, MAX_DMA_DATA_LEN, 120 DMA_FROM_DEVICE); 121 ch->dma.desc_base[ch->dma.desc].addr = 122 CPHYSADDR(ch->skb[ch->dma.desc]->data); 123 ch->dma.desc_base[ch->dma.desc].ctl = 124 LTQ_DMA_OWN | LTQ_DMA_RX_OFFSET(NET_IP_ALIGN) | 125 MAX_DMA_DATA_LEN; 126 skb_reserve(ch->skb[ch->dma.desc], NET_IP_ALIGN); 127 return 0; 128 } 129 130 static void 131 ltq_etop_hw_receive(struct ltq_etop_chan *ch) 132 { 133 struct ltq_etop_priv *priv = netdev_priv(ch->netdev); 134 struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->dma.desc]; 135 struct sk_buff *skb = ch->skb[ch->dma.desc]; 136 int len = (desc->ctl & LTQ_DMA_SIZE_MASK) - MAX_DMA_CRC_LEN; 137 unsigned long flags; 138 139 spin_lock_irqsave(&priv->lock, flags); 140 if (ltq_etop_alloc_skb(ch)) { 141 netdev_err(ch->netdev, 142 "failed to allocate new rx buffer, stopping DMA\n"); 143 ltq_dma_close(&ch->dma); 144 } 145 ch->dma.desc++; 146 ch->dma.desc %= LTQ_DESC_NUM; 147 spin_unlock_irqrestore(&priv->lock, flags); 148 149 skb_put(skb, len); 150 skb->protocol = eth_type_trans(skb, ch->netdev); 151 netif_receive_skb(skb); 152 } 153 154 static int 155 ltq_etop_poll_rx(struct napi_struct *napi, int budget) 156 { 157 struct ltq_etop_chan *ch = container_of(napi, 158 struct ltq_etop_chan, napi); 159 int work_done = 0; 160 161 while (work_done < budget) { 162 struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->dma.desc]; 163 164 if ((desc->ctl & (LTQ_DMA_OWN | LTQ_DMA_C)) != LTQ_DMA_C) 165 break; 166 ltq_etop_hw_receive(ch); 167 work_done++; 168 } 169 if (work_done < budget) { 170 napi_complete_done(&ch->napi, work_done); 171 ltq_dma_ack_irq(&ch->dma); 172 } 173 return work_done; 174 } 175 176 static int 177 ltq_etop_poll_tx(struct napi_struct *napi, int budget) 178 { 179 struct ltq_etop_chan *ch = 180 container_of(napi, struct ltq_etop_chan, napi); 181 struct ltq_etop_priv *priv = netdev_priv(ch->netdev); 182 struct netdev_queue *txq = 183 netdev_get_tx_queue(ch->netdev, ch->idx >> 1); 184 unsigned long flags; 185 186 spin_lock_irqsave(&priv->lock, flags); 187 while ((ch->dma.desc_base[ch->tx_free].ctl & 188 (LTQ_DMA_OWN | LTQ_DMA_C)) == LTQ_DMA_C) { 189 dev_kfree_skb_any(ch->skb[ch->tx_free]); 190 ch->skb[ch->tx_free] = NULL; 191 memset(&ch->dma.desc_base[ch->tx_free], 0, 192 sizeof(struct ltq_dma_desc)); 193 ch->tx_free++; 194 ch->tx_free %= LTQ_DESC_NUM; 195 } 196 spin_unlock_irqrestore(&priv->lock, flags); 197 198 if (netif_tx_queue_stopped(txq)) 199 netif_tx_start_queue(txq); 200 napi_complete(&ch->napi); 201 ltq_dma_ack_irq(&ch->dma); 202 return 1; 203 } 204 205 static irqreturn_t 206 ltq_etop_dma_irq(int irq, void *_priv) 207 { 208 struct ltq_etop_priv *priv = _priv; 209 int ch = irq - LTQ_DMA_CH0_INT; 210 211 napi_schedule(&priv->ch[ch].napi); 212 return IRQ_HANDLED; 213 } 214 215 static void 216 ltq_etop_free_channel(struct net_device *dev, struct ltq_etop_chan *ch) 217 { 218 struct ltq_etop_priv *priv = netdev_priv(dev); 219 220 ltq_dma_free(&ch->dma); 221 if (ch->dma.irq) 222 free_irq(ch->dma.irq, priv); 223 if (IS_RX(ch->idx)) { 224 int desc; 225 for (desc = 0; desc < LTQ_DESC_NUM; desc++) 226 dev_kfree_skb_any(ch->skb[ch->dma.desc]); 227 } 228 } 229 230 static void 231 ltq_etop_hw_exit(struct net_device *dev) 232 { 233 struct ltq_etop_priv *priv = netdev_priv(dev); 234 int i; 235 236 ltq_pmu_disable(PMU_PPE); 237 for (i = 0; i < MAX_DMA_CHAN; i++) 238 if (IS_TX(i) || IS_RX(i)) 239 ltq_etop_free_channel(dev, &priv->ch[i]); 240 } 241 242 static int 243 ltq_etop_hw_init(struct net_device *dev) 244 { 245 struct ltq_etop_priv *priv = netdev_priv(dev); 246 int i; 247 248 ltq_pmu_enable(PMU_PPE); 249 250 switch (priv->pldata->mii_mode) { 251 case PHY_INTERFACE_MODE_RMII: 252 ltq_etop_w32_mask(ETOP_MII_MASK, 253 ETOP_MII_REVERSE, LTQ_ETOP_CFG); 254 break; 255 256 case PHY_INTERFACE_MODE_MII: 257 ltq_etop_w32_mask(ETOP_MII_MASK, 258 ETOP_MII_NORMAL, LTQ_ETOP_CFG); 259 break; 260 261 default: 262 netdev_err(dev, "unknown mii mode %d\n", 263 priv->pldata->mii_mode); 264 return -ENOTSUPP; 265 } 266 267 /* enable crc generation */ 268 ltq_etop_w32(PPE32_CGEN, LQ_PPE32_ENET_MAC_CFG); 269 270 ltq_dma_init_port(DMA_PORT_ETOP); 271 272 for (i = 0; i < MAX_DMA_CHAN; i++) { 273 int irq = LTQ_DMA_CH0_INT + i; 274 struct ltq_etop_chan *ch = &priv->ch[i]; 275 276 ch->idx = ch->dma.nr = i; 277 ch->dma.dev = &priv->pdev->dev; 278 279 if (IS_TX(i)) { 280 ltq_dma_alloc_tx(&ch->dma); 281 request_irq(irq, ltq_etop_dma_irq, 0, "etop_tx", priv); 282 } else if (IS_RX(i)) { 283 ltq_dma_alloc_rx(&ch->dma); 284 for (ch->dma.desc = 0; ch->dma.desc < LTQ_DESC_NUM; 285 ch->dma.desc++) 286 if (ltq_etop_alloc_skb(ch)) 287 return -ENOMEM; 288 ch->dma.desc = 0; 289 request_irq(irq, ltq_etop_dma_irq, 0, "etop_rx", priv); 290 } 291 ch->dma.irq = irq; 292 } 293 return 0; 294 } 295 296 static void 297 ltq_etop_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info) 298 { 299 strlcpy(info->driver, "Lantiq ETOP", sizeof(info->driver)); 300 strlcpy(info->bus_info, "internal", sizeof(info->bus_info)); 301 strlcpy(info->version, DRV_VERSION, sizeof(info->version)); 302 } 303 304 static const struct ethtool_ops ltq_etop_ethtool_ops = { 305 .get_drvinfo = ltq_etop_get_drvinfo, 306 .nway_reset = phy_ethtool_nway_reset, 307 .get_link_ksettings = phy_ethtool_get_link_ksettings, 308 .set_link_ksettings = phy_ethtool_set_link_ksettings, 309 }; 310 311 static int 312 ltq_etop_mdio_wr(struct mii_bus *bus, int phy_addr, int phy_reg, u16 phy_data) 313 { 314 u32 val = MDIO_REQUEST | 315 ((phy_addr & MDIO_ADDR_MASK) << MDIO_ADDR_OFFSET) | 316 ((phy_reg & MDIO_REG_MASK) << MDIO_REG_OFFSET) | 317 phy_data; 318 319 while (ltq_etop_r32(LTQ_ETOP_MDIO) & MDIO_REQUEST) 320 ; 321 ltq_etop_w32(val, LTQ_ETOP_MDIO); 322 return 0; 323 } 324 325 static int 326 ltq_etop_mdio_rd(struct mii_bus *bus, int phy_addr, int phy_reg) 327 { 328 u32 val = MDIO_REQUEST | MDIO_READ | 329 ((phy_addr & MDIO_ADDR_MASK) << MDIO_ADDR_OFFSET) | 330 ((phy_reg & MDIO_REG_MASK) << MDIO_REG_OFFSET); 331 332 while (ltq_etop_r32(LTQ_ETOP_MDIO) & MDIO_REQUEST) 333 ; 334 ltq_etop_w32(val, LTQ_ETOP_MDIO); 335 while (ltq_etop_r32(LTQ_ETOP_MDIO) & MDIO_REQUEST) 336 ; 337 val = ltq_etop_r32(LTQ_ETOP_MDIO) & MDIO_VAL_MASK; 338 return val; 339 } 340 341 static void 342 ltq_etop_mdio_link(struct net_device *dev) 343 { 344 /* nothing to do */ 345 } 346 347 static int 348 ltq_etop_mdio_probe(struct net_device *dev) 349 { 350 struct ltq_etop_priv *priv = netdev_priv(dev); 351 struct phy_device *phydev; 352 353 phydev = phy_find_first(priv->mii_bus); 354 355 if (!phydev) { 356 netdev_err(dev, "no PHY found\n"); 357 return -ENODEV; 358 } 359 360 phydev = phy_connect(dev, phydev_name(phydev), 361 <q_etop_mdio_link, priv->pldata->mii_mode); 362 363 if (IS_ERR(phydev)) { 364 netdev_err(dev, "Could not attach to PHY\n"); 365 return PTR_ERR(phydev); 366 } 367 368 phy_set_max_speed(phydev, SPEED_100); 369 370 phy_attached_info(phydev); 371 372 return 0; 373 } 374 375 static int 376 ltq_etop_mdio_init(struct net_device *dev) 377 { 378 struct ltq_etop_priv *priv = netdev_priv(dev); 379 int err; 380 381 priv->mii_bus = mdiobus_alloc(); 382 if (!priv->mii_bus) { 383 netdev_err(dev, "failed to allocate mii bus\n"); 384 err = -ENOMEM; 385 goto err_out; 386 } 387 388 priv->mii_bus->priv = dev; 389 priv->mii_bus->read = ltq_etop_mdio_rd; 390 priv->mii_bus->write = ltq_etop_mdio_wr; 391 priv->mii_bus->name = "ltq_mii"; 392 snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x", 393 priv->pdev->name, priv->pdev->id); 394 if (mdiobus_register(priv->mii_bus)) { 395 err = -ENXIO; 396 goto err_out_free_mdiobus; 397 } 398 399 if (ltq_etop_mdio_probe(dev)) { 400 err = -ENXIO; 401 goto err_out_unregister_bus; 402 } 403 return 0; 404 405 err_out_unregister_bus: 406 mdiobus_unregister(priv->mii_bus); 407 err_out_free_mdiobus: 408 mdiobus_free(priv->mii_bus); 409 err_out: 410 return err; 411 } 412 413 static void 414 ltq_etop_mdio_cleanup(struct net_device *dev) 415 { 416 struct ltq_etop_priv *priv = netdev_priv(dev); 417 418 phy_disconnect(dev->phydev); 419 mdiobus_unregister(priv->mii_bus); 420 mdiobus_free(priv->mii_bus); 421 } 422 423 static int 424 ltq_etop_open(struct net_device *dev) 425 { 426 struct ltq_etop_priv *priv = netdev_priv(dev); 427 int i; 428 429 for (i = 0; i < MAX_DMA_CHAN; i++) { 430 struct ltq_etop_chan *ch = &priv->ch[i]; 431 432 if (!IS_TX(i) && (!IS_RX(i))) 433 continue; 434 ltq_dma_open(&ch->dma); 435 ltq_dma_enable_irq(&ch->dma); 436 napi_enable(&ch->napi); 437 } 438 phy_start(dev->phydev); 439 netif_tx_start_all_queues(dev); 440 return 0; 441 } 442 443 static int 444 ltq_etop_stop(struct net_device *dev) 445 { 446 struct ltq_etop_priv *priv = netdev_priv(dev); 447 int i; 448 449 netif_tx_stop_all_queues(dev); 450 phy_stop(dev->phydev); 451 for (i = 0; i < MAX_DMA_CHAN; i++) { 452 struct ltq_etop_chan *ch = &priv->ch[i]; 453 454 if (!IS_RX(i) && !IS_TX(i)) 455 continue; 456 napi_disable(&ch->napi); 457 ltq_dma_close(&ch->dma); 458 } 459 return 0; 460 } 461 462 static int 463 ltq_etop_tx(struct sk_buff *skb, struct net_device *dev) 464 { 465 int queue = skb_get_queue_mapping(skb); 466 struct netdev_queue *txq = netdev_get_tx_queue(dev, queue); 467 struct ltq_etop_priv *priv = netdev_priv(dev); 468 struct ltq_etop_chan *ch = &priv->ch[(queue << 1) | 1]; 469 struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->dma.desc]; 470 int len; 471 unsigned long flags; 472 u32 byte_offset; 473 474 len = skb->len < ETH_ZLEN ? ETH_ZLEN : skb->len; 475 476 if ((desc->ctl & (LTQ_DMA_OWN | LTQ_DMA_C)) || ch->skb[ch->dma.desc]) { 477 dev_kfree_skb_any(skb); 478 netdev_err(dev, "tx ring full\n"); 479 netif_tx_stop_queue(txq); 480 return NETDEV_TX_BUSY; 481 } 482 483 /* dma needs to start on a 16 byte aligned address */ 484 byte_offset = CPHYSADDR(skb->data) % 16; 485 ch->skb[ch->dma.desc] = skb; 486 487 netif_trans_update(dev); 488 489 spin_lock_irqsave(&priv->lock, flags); 490 desc->addr = ((unsigned int) dma_map_single(NULL, skb->data, len, 491 DMA_TO_DEVICE)) - byte_offset; 492 wmb(); 493 desc->ctl = LTQ_DMA_OWN | LTQ_DMA_SOP | LTQ_DMA_EOP | 494 LTQ_DMA_TX_OFFSET(byte_offset) | (len & LTQ_DMA_SIZE_MASK); 495 ch->dma.desc++; 496 ch->dma.desc %= LTQ_DESC_NUM; 497 spin_unlock_irqrestore(&priv->lock, flags); 498 499 if (ch->dma.desc_base[ch->dma.desc].ctl & LTQ_DMA_OWN) 500 netif_tx_stop_queue(txq); 501 502 return NETDEV_TX_OK; 503 } 504 505 static int 506 ltq_etop_change_mtu(struct net_device *dev, int new_mtu) 507 { 508 struct ltq_etop_priv *priv = netdev_priv(dev); 509 unsigned long flags; 510 511 dev->mtu = new_mtu; 512 513 spin_lock_irqsave(&priv->lock, flags); 514 ltq_etop_w32((ETOP_PLEN_UNDER << 16) | new_mtu, LTQ_ETOP_IGPLEN); 515 spin_unlock_irqrestore(&priv->lock, flags); 516 517 return 0; 518 } 519 520 static int 521 ltq_etop_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) 522 { 523 /* TODO: mii-toll reports "No MII transceiver present!." ?!*/ 524 return phy_mii_ioctl(dev->phydev, rq, cmd); 525 } 526 527 static int 528 ltq_etop_set_mac_address(struct net_device *dev, void *p) 529 { 530 int ret = eth_mac_addr(dev, p); 531 532 if (!ret) { 533 struct ltq_etop_priv *priv = netdev_priv(dev); 534 unsigned long flags; 535 536 /* store the mac for the unicast filter */ 537 spin_lock_irqsave(&priv->lock, flags); 538 ltq_etop_w32(*((u32 *)dev->dev_addr), LTQ_ETOP_MAC_DA0); 539 ltq_etop_w32(*((u16 *)&dev->dev_addr[4]) << 16, 540 LTQ_ETOP_MAC_DA1); 541 spin_unlock_irqrestore(&priv->lock, flags); 542 } 543 return ret; 544 } 545 546 static void 547 ltq_etop_set_multicast_list(struct net_device *dev) 548 { 549 struct ltq_etop_priv *priv = netdev_priv(dev); 550 unsigned long flags; 551 552 /* ensure that the unicast filter is not enabled in promiscious mode */ 553 spin_lock_irqsave(&priv->lock, flags); 554 if ((dev->flags & IFF_PROMISC) || (dev->flags & IFF_ALLMULTI)) 555 ltq_etop_w32_mask(ETOP_FTCU, 0, LTQ_ETOP_ENETS0); 556 else 557 ltq_etop_w32_mask(0, ETOP_FTCU, LTQ_ETOP_ENETS0); 558 spin_unlock_irqrestore(&priv->lock, flags); 559 } 560 561 static int 562 ltq_etop_init(struct net_device *dev) 563 { 564 struct ltq_etop_priv *priv = netdev_priv(dev); 565 struct sockaddr mac; 566 int err; 567 bool random_mac = false; 568 569 dev->watchdog_timeo = 10 * HZ; 570 err = ltq_etop_hw_init(dev); 571 if (err) 572 goto err_hw; 573 ltq_etop_change_mtu(dev, 1500); 574 575 memcpy(&mac, &priv->pldata->mac, sizeof(struct sockaddr)); 576 if (!is_valid_ether_addr(mac.sa_data)) { 577 pr_warn("etop: invalid MAC, using random\n"); 578 eth_random_addr(mac.sa_data); 579 random_mac = true; 580 } 581 582 err = ltq_etop_set_mac_address(dev, &mac); 583 if (err) 584 goto err_netdev; 585 586 /* Set addr_assign_type here, ltq_etop_set_mac_address would reset it. */ 587 if (random_mac) 588 dev->addr_assign_type = NET_ADDR_RANDOM; 589 590 ltq_etop_set_multicast_list(dev); 591 err = ltq_etop_mdio_init(dev); 592 if (err) 593 goto err_netdev; 594 return 0; 595 596 err_netdev: 597 unregister_netdev(dev); 598 free_netdev(dev); 599 err_hw: 600 ltq_etop_hw_exit(dev); 601 return err; 602 } 603 604 static void 605 ltq_etop_tx_timeout(struct net_device *dev) 606 { 607 int err; 608 609 ltq_etop_hw_exit(dev); 610 err = ltq_etop_hw_init(dev); 611 if (err) 612 goto err_hw; 613 netif_trans_update(dev); 614 netif_wake_queue(dev); 615 return; 616 617 err_hw: 618 ltq_etop_hw_exit(dev); 619 netdev_err(dev, "failed to restart etop after TX timeout\n"); 620 } 621 622 static const struct net_device_ops ltq_eth_netdev_ops = { 623 .ndo_open = ltq_etop_open, 624 .ndo_stop = ltq_etop_stop, 625 .ndo_start_xmit = ltq_etop_tx, 626 .ndo_change_mtu = ltq_etop_change_mtu, 627 .ndo_do_ioctl = ltq_etop_ioctl, 628 .ndo_set_mac_address = ltq_etop_set_mac_address, 629 .ndo_validate_addr = eth_validate_addr, 630 .ndo_set_rx_mode = ltq_etop_set_multicast_list, 631 .ndo_select_queue = dev_pick_tx_zero, 632 .ndo_init = ltq_etop_init, 633 .ndo_tx_timeout = ltq_etop_tx_timeout, 634 }; 635 636 static int __init 637 ltq_etop_probe(struct platform_device *pdev) 638 { 639 struct net_device *dev; 640 struct ltq_etop_priv *priv; 641 struct resource *res; 642 int err; 643 int i; 644 645 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 646 if (!res) { 647 dev_err(&pdev->dev, "failed to get etop resource\n"); 648 err = -ENOENT; 649 goto err_out; 650 } 651 652 res = devm_request_mem_region(&pdev->dev, res->start, 653 resource_size(res), dev_name(&pdev->dev)); 654 if (!res) { 655 dev_err(&pdev->dev, "failed to request etop resource\n"); 656 err = -EBUSY; 657 goto err_out; 658 } 659 660 ltq_etop_membase = devm_ioremap_nocache(&pdev->dev, 661 res->start, resource_size(res)); 662 if (!ltq_etop_membase) { 663 dev_err(&pdev->dev, "failed to remap etop engine %d\n", 664 pdev->id); 665 err = -ENOMEM; 666 goto err_out; 667 } 668 669 dev = alloc_etherdev_mq(sizeof(struct ltq_etop_priv), 4); 670 if (!dev) { 671 err = -ENOMEM; 672 goto err_out; 673 } 674 strcpy(dev->name, "eth%d"); 675 dev->netdev_ops = <q_eth_netdev_ops; 676 dev->ethtool_ops = <q_etop_ethtool_ops; 677 priv = netdev_priv(dev); 678 priv->res = res; 679 priv->pdev = pdev; 680 priv->pldata = dev_get_platdata(&pdev->dev); 681 priv->netdev = dev; 682 spin_lock_init(&priv->lock); 683 SET_NETDEV_DEV(dev, &pdev->dev); 684 685 for (i = 0; i < MAX_DMA_CHAN; i++) { 686 if (IS_TX(i)) 687 netif_napi_add(dev, &priv->ch[i].napi, 688 ltq_etop_poll_tx, 8); 689 else if (IS_RX(i)) 690 netif_napi_add(dev, &priv->ch[i].napi, 691 ltq_etop_poll_rx, 32); 692 priv->ch[i].netdev = dev; 693 } 694 695 err = register_netdev(dev); 696 if (err) 697 goto err_free; 698 699 platform_set_drvdata(pdev, dev); 700 return 0; 701 702 err_free: 703 free_netdev(dev); 704 err_out: 705 return err; 706 } 707 708 static int 709 ltq_etop_remove(struct platform_device *pdev) 710 { 711 struct net_device *dev = platform_get_drvdata(pdev); 712 713 if (dev) { 714 netif_tx_stop_all_queues(dev); 715 ltq_etop_hw_exit(dev); 716 ltq_etop_mdio_cleanup(dev); 717 unregister_netdev(dev); 718 } 719 return 0; 720 } 721 722 static struct platform_driver ltq_mii_driver = { 723 .remove = ltq_etop_remove, 724 .driver = { 725 .name = "ltq_etop", 726 }, 727 }; 728 729 int __init 730 init_ltq_etop(void) 731 { 732 int ret = platform_driver_probe(<q_mii_driver, ltq_etop_probe); 733 734 if (ret) 735 pr_err("ltq_etop: Error registering platform driver!"); 736 return ret; 737 } 738 739 static void __exit 740 exit_ltq_etop(void) 741 { 742 platform_driver_unregister(<q_mii_driver); 743 } 744 745 module_init(init_ltq_etop); 746 module_exit(exit_ltq_etop); 747 748 MODULE_AUTHOR("John Crispin <blogic@openwrt.org>"); 749 MODULE_DESCRIPTION("Lantiq SoC ETOP"); 750 MODULE_LICENSE("GPL"); 751