1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * 4 * Copyright (C) 2011 John Crispin <blogic@openwrt.org> 5 */ 6 7 #include <linux/kernel.h> 8 #include <linux/slab.h> 9 #include <linux/errno.h> 10 #include <linux/types.h> 11 #include <linux/interrupt.h> 12 #include <linux/uaccess.h> 13 #include <linux/in.h> 14 #include <linux/netdevice.h> 15 #include <linux/etherdevice.h> 16 #include <linux/phy.h> 17 #include <linux/ip.h> 18 #include <linux/tcp.h> 19 #include <linux/skbuff.h> 20 #include <linux/mm.h> 21 #include <linux/platform_device.h> 22 #include <linux/ethtool.h> 23 #include <linux/init.h> 24 #include <linux/delay.h> 25 #include <linux/io.h> 26 #include <linux/dma-mapping.h> 27 #include <linux/module.h> 28 29 #include <asm/checksum.h> 30 31 #include <lantiq_soc.h> 32 #include <xway_dma.h> 33 #include <lantiq_platform.h> 34 35 #define LTQ_ETOP_MDIO 0x11804 36 #define MDIO_REQUEST 0x80000000 37 #define MDIO_READ 0x40000000 38 #define MDIO_ADDR_MASK 0x1f 39 #define MDIO_ADDR_OFFSET 0x15 40 #define MDIO_REG_MASK 0x1f 41 #define MDIO_REG_OFFSET 0x10 42 #define MDIO_VAL_MASK 0xffff 43 44 #define PPE32_CGEN 0x800 45 #define LQ_PPE32_ENET_MAC_CFG 0x1840 46 47 #define LTQ_ETOP_ENETS0 0x11850 48 #define LTQ_ETOP_MAC_DA0 0x1186C 49 #define LTQ_ETOP_MAC_DA1 0x11870 50 #define LTQ_ETOP_CFG 0x16020 51 #define LTQ_ETOP_IGPLEN 0x16080 52 53 #define MAX_DMA_CHAN 0x8 54 #define MAX_DMA_CRC_LEN 0x4 55 #define MAX_DMA_DATA_LEN 0x600 56 57 #define ETOP_FTCU BIT(28) 58 #define ETOP_MII_MASK 0xf 59 #define ETOP_MII_NORMAL 0xd 60 #define ETOP_MII_REVERSE 0xe 61 #define ETOP_PLEN_UNDER 0x40 62 #define ETOP_CGEN 0x800 63 64 /* use 2 static channels for TX/RX */ 65 #define LTQ_ETOP_TX_CHANNEL 1 66 #define LTQ_ETOP_RX_CHANNEL 6 67 #define IS_TX(x) (x == LTQ_ETOP_TX_CHANNEL) 68 #define IS_RX(x) (x == LTQ_ETOP_RX_CHANNEL) 69 70 #define ltq_etop_r32(x) ltq_r32(ltq_etop_membase + (x)) 71 #define ltq_etop_w32(x, y) ltq_w32(x, ltq_etop_membase + (y)) 72 #define ltq_etop_w32_mask(x, y, z) \ 73 ltq_w32_mask(x, y, ltq_etop_membase + (z)) 74 75 #define DRV_VERSION "1.0" 76 77 static void __iomem *ltq_etop_membase; 78 79 struct ltq_etop_chan { 80 int idx; 81 int tx_free; 82 struct net_device *netdev; 83 struct napi_struct napi; 84 struct ltq_dma_channel dma; 85 struct sk_buff *skb[LTQ_DESC_NUM]; 86 }; 87 88 struct ltq_etop_priv { 89 struct net_device *netdev; 90 struct platform_device *pdev; 91 struct ltq_eth_data *pldata; 92 struct resource *res; 93 94 struct mii_bus *mii_bus; 95 96 struct ltq_etop_chan ch[MAX_DMA_CHAN]; 97 int tx_free[MAX_DMA_CHAN >> 1]; 98 99 int tx_burst_len; 100 int rx_burst_len; 101 102 spinlock_t lock; 103 }; 104 105 static int 106 ltq_etop_alloc_skb(struct ltq_etop_chan *ch) 107 { 108 struct ltq_etop_priv *priv = netdev_priv(ch->netdev); 109 110 ch->skb[ch->dma.desc] = netdev_alloc_skb(ch->netdev, MAX_DMA_DATA_LEN); 111 if (!ch->skb[ch->dma.desc]) 112 return -ENOMEM; 113 ch->dma.desc_base[ch->dma.desc].addr = dma_map_single(&priv->pdev->dev, 114 ch->skb[ch->dma.desc]->data, MAX_DMA_DATA_LEN, 115 DMA_FROM_DEVICE); 116 ch->dma.desc_base[ch->dma.desc].addr = 117 CPHYSADDR(ch->skb[ch->dma.desc]->data); 118 ch->dma.desc_base[ch->dma.desc].ctl = 119 LTQ_DMA_OWN | LTQ_DMA_RX_OFFSET(NET_IP_ALIGN) | 120 MAX_DMA_DATA_LEN; 121 skb_reserve(ch->skb[ch->dma.desc], NET_IP_ALIGN); 122 return 0; 123 } 124 125 static void 126 ltq_etop_hw_receive(struct ltq_etop_chan *ch) 127 { 128 struct ltq_etop_priv *priv = netdev_priv(ch->netdev); 129 struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->dma.desc]; 130 struct sk_buff *skb = ch->skb[ch->dma.desc]; 131 int len = (desc->ctl & LTQ_DMA_SIZE_MASK) - MAX_DMA_CRC_LEN; 132 unsigned long flags; 133 134 spin_lock_irqsave(&priv->lock, flags); 135 if (ltq_etop_alloc_skb(ch)) { 136 netdev_err(ch->netdev, 137 "failed to allocate new rx buffer, stopping DMA\n"); 138 ltq_dma_close(&ch->dma); 139 } 140 ch->dma.desc++; 141 ch->dma.desc %= LTQ_DESC_NUM; 142 spin_unlock_irqrestore(&priv->lock, flags); 143 144 skb_put(skb, len); 145 skb->protocol = eth_type_trans(skb, ch->netdev); 146 netif_receive_skb(skb); 147 } 148 149 static int 150 ltq_etop_poll_rx(struct napi_struct *napi, int budget) 151 { 152 struct ltq_etop_chan *ch = container_of(napi, 153 struct ltq_etop_chan, napi); 154 int work_done = 0; 155 156 while (work_done < budget) { 157 struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->dma.desc]; 158 159 if ((desc->ctl & (LTQ_DMA_OWN | LTQ_DMA_C)) != LTQ_DMA_C) 160 break; 161 ltq_etop_hw_receive(ch); 162 work_done++; 163 } 164 if (work_done < budget) { 165 napi_complete_done(&ch->napi, work_done); 166 ltq_dma_ack_irq(&ch->dma); 167 } 168 return work_done; 169 } 170 171 static int 172 ltq_etop_poll_tx(struct napi_struct *napi, int budget) 173 { 174 struct ltq_etop_chan *ch = 175 container_of(napi, struct ltq_etop_chan, napi); 176 struct ltq_etop_priv *priv = netdev_priv(ch->netdev); 177 struct netdev_queue *txq = 178 netdev_get_tx_queue(ch->netdev, ch->idx >> 1); 179 unsigned long flags; 180 181 spin_lock_irqsave(&priv->lock, flags); 182 while ((ch->dma.desc_base[ch->tx_free].ctl & 183 (LTQ_DMA_OWN | LTQ_DMA_C)) == LTQ_DMA_C) { 184 dev_kfree_skb_any(ch->skb[ch->tx_free]); 185 ch->skb[ch->tx_free] = NULL; 186 memset(&ch->dma.desc_base[ch->tx_free], 0, 187 sizeof(struct ltq_dma_desc)); 188 ch->tx_free++; 189 ch->tx_free %= LTQ_DESC_NUM; 190 } 191 spin_unlock_irqrestore(&priv->lock, flags); 192 193 if (netif_tx_queue_stopped(txq)) 194 netif_tx_start_queue(txq); 195 napi_complete(&ch->napi); 196 ltq_dma_ack_irq(&ch->dma); 197 return 1; 198 } 199 200 static irqreturn_t 201 ltq_etop_dma_irq(int irq, void *_priv) 202 { 203 struct ltq_etop_priv *priv = _priv; 204 int ch = irq - LTQ_DMA_CH0_INT; 205 206 napi_schedule(&priv->ch[ch].napi); 207 return IRQ_HANDLED; 208 } 209 210 static void 211 ltq_etop_free_channel(struct net_device *dev, struct ltq_etop_chan *ch) 212 { 213 struct ltq_etop_priv *priv = netdev_priv(dev); 214 215 ltq_dma_free(&ch->dma); 216 if (ch->dma.irq) 217 free_irq(ch->dma.irq, priv); 218 if (IS_RX(ch->idx)) { 219 int desc; 220 for (desc = 0; desc < LTQ_DESC_NUM; desc++) 221 dev_kfree_skb_any(ch->skb[ch->dma.desc]); 222 } 223 } 224 225 static void 226 ltq_etop_hw_exit(struct net_device *dev) 227 { 228 struct ltq_etop_priv *priv = netdev_priv(dev); 229 int i; 230 231 ltq_pmu_disable(PMU_PPE); 232 for (i = 0; i < MAX_DMA_CHAN; i++) 233 if (IS_TX(i) || IS_RX(i)) 234 ltq_etop_free_channel(dev, &priv->ch[i]); 235 } 236 237 static int 238 ltq_etop_hw_init(struct net_device *dev) 239 { 240 struct ltq_etop_priv *priv = netdev_priv(dev); 241 int i; 242 243 ltq_pmu_enable(PMU_PPE); 244 245 switch (priv->pldata->mii_mode) { 246 case PHY_INTERFACE_MODE_RMII: 247 ltq_etop_w32_mask(ETOP_MII_MASK, 248 ETOP_MII_REVERSE, LTQ_ETOP_CFG); 249 break; 250 251 case PHY_INTERFACE_MODE_MII: 252 ltq_etop_w32_mask(ETOP_MII_MASK, 253 ETOP_MII_NORMAL, LTQ_ETOP_CFG); 254 break; 255 256 default: 257 netdev_err(dev, "unknown mii mode %d\n", 258 priv->pldata->mii_mode); 259 return -ENOTSUPP; 260 } 261 262 /* enable crc generation */ 263 ltq_etop_w32(PPE32_CGEN, LQ_PPE32_ENET_MAC_CFG); 264 265 ltq_dma_init_port(DMA_PORT_ETOP, priv->tx_burst_len, priv->rx_burst_len); 266 267 for (i = 0; i < MAX_DMA_CHAN; i++) { 268 int irq = LTQ_DMA_CH0_INT + i; 269 struct ltq_etop_chan *ch = &priv->ch[i]; 270 271 ch->idx = ch->dma.nr = i; 272 ch->dma.dev = &priv->pdev->dev; 273 274 if (IS_TX(i)) { 275 ltq_dma_alloc_tx(&ch->dma); 276 request_irq(irq, ltq_etop_dma_irq, 0, "etop_tx", priv); 277 } else if (IS_RX(i)) { 278 ltq_dma_alloc_rx(&ch->dma); 279 for (ch->dma.desc = 0; ch->dma.desc < LTQ_DESC_NUM; 280 ch->dma.desc++) 281 if (ltq_etop_alloc_skb(ch)) 282 return -ENOMEM; 283 ch->dma.desc = 0; 284 request_irq(irq, ltq_etop_dma_irq, 0, "etop_rx", priv); 285 } 286 ch->dma.irq = irq; 287 } 288 return 0; 289 } 290 291 static void 292 ltq_etop_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info) 293 { 294 strlcpy(info->driver, "Lantiq ETOP", sizeof(info->driver)); 295 strlcpy(info->bus_info, "internal", sizeof(info->bus_info)); 296 strlcpy(info->version, DRV_VERSION, sizeof(info->version)); 297 } 298 299 static const struct ethtool_ops ltq_etop_ethtool_ops = { 300 .get_drvinfo = ltq_etop_get_drvinfo, 301 .nway_reset = phy_ethtool_nway_reset, 302 .get_link_ksettings = phy_ethtool_get_link_ksettings, 303 .set_link_ksettings = phy_ethtool_set_link_ksettings, 304 }; 305 306 static int 307 ltq_etop_mdio_wr(struct mii_bus *bus, int phy_addr, int phy_reg, u16 phy_data) 308 { 309 u32 val = MDIO_REQUEST | 310 ((phy_addr & MDIO_ADDR_MASK) << MDIO_ADDR_OFFSET) | 311 ((phy_reg & MDIO_REG_MASK) << MDIO_REG_OFFSET) | 312 phy_data; 313 314 while (ltq_etop_r32(LTQ_ETOP_MDIO) & MDIO_REQUEST) 315 ; 316 ltq_etop_w32(val, LTQ_ETOP_MDIO); 317 return 0; 318 } 319 320 static int 321 ltq_etop_mdio_rd(struct mii_bus *bus, int phy_addr, int phy_reg) 322 { 323 u32 val = MDIO_REQUEST | MDIO_READ | 324 ((phy_addr & MDIO_ADDR_MASK) << MDIO_ADDR_OFFSET) | 325 ((phy_reg & MDIO_REG_MASK) << MDIO_REG_OFFSET); 326 327 while (ltq_etop_r32(LTQ_ETOP_MDIO) & MDIO_REQUEST) 328 ; 329 ltq_etop_w32(val, LTQ_ETOP_MDIO); 330 while (ltq_etop_r32(LTQ_ETOP_MDIO) & MDIO_REQUEST) 331 ; 332 val = ltq_etop_r32(LTQ_ETOP_MDIO) & MDIO_VAL_MASK; 333 return val; 334 } 335 336 static void 337 ltq_etop_mdio_link(struct net_device *dev) 338 { 339 /* nothing to do */ 340 } 341 342 static int 343 ltq_etop_mdio_probe(struct net_device *dev) 344 { 345 struct ltq_etop_priv *priv = netdev_priv(dev); 346 struct phy_device *phydev; 347 348 phydev = phy_find_first(priv->mii_bus); 349 350 if (!phydev) { 351 netdev_err(dev, "no PHY found\n"); 352 return -ENODEV; 353 } 354 355 phydev = phy_connect(dev, phydev_name(phydev), 356 <q_etop_mdio_link, priv->pldata->mii_mode); 357 358 if (IS_ERR(phydev)) { 359 netdev_err(dev, "Could not attach to PHY\n"); 360 return PTR_ERR(phydev); 361 } 362 363 phy_set_max_speed(phydev, SPEED_100); 364 365 phy_attached_info(phydev); 366 367 return 0; 368 } 369 370 static int 371 ltq_etop_mdio_init(struct net_device *dev) 372 { 373 struct ltq_etop_priv *priv = netdev_priv(dev); 374 int err; 375 376 priv->mii_bus = mdiobus_alloc(); 377 if (!priv->mii_bus) { 378 netdev_err(dev, "failed to allocate mii bus\n"); 379 err = -ENOMEM; 380 goto err_out; 381 } 382 383 priv->mii_bus->priv = dev; 384 priv->mii_bus->read = ltq_etop_mdio_rd; 385 priv->mii_bus->write = ltq_etop_mdio_wr; 386 priv->mii_bus->name = "ltq_mii"; 387 snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x", 388 priv->pdev->name, priv->pdev->id); 389 if (mdiobus_register(priv->mii_bus)) { 390 err = -ENXIO; 391 goto err_out_free_mdiobus; 392 } 393 394 if (ltq_etop_mdio_probe(dev)) { 395 err = -ENXIO; 396 goto err_out_unregister_bus; 397 } 398 return 0; 399 400 err_out_unregister_bus: 401 mdiobus_unregister(priv->mii_bus); 402 err_out_free_mdiobus: 403 mdiobus_free(priv->mii_bus); 404 err_out: 405 return err; 406 } 407 408 static void 409 ltq_etop_mdio_cleanup(struct net_device *dev) 410 { 411 struct ltq_etop_priv *priv = netdev_priv(dev); 412 413 phy_disconnect(dev->phydev); 414 mdiobus_unregister(priv->mii_bus); 415 mdiobus_free(priv->mii_bus); 416 } 417 418 static int 419 ltq_etop_open(struct net_device *dev) 420 { 421 struct ltq_etop_priv *priv = netdev_priv(dev); 422 int i; 423 424 for (i = 0; i < MAX_DMA_CHAN; i++) { 425 struct ltq_etop_chan *ch = &priv->ch[i]; 426 427 if (!IS_TX(i) && (!IS_RX(i))) 428 continue; 429 ltq_dma_open(&ch->dma); 430 ltq_dma_enable_irq(&ch->dma); 431 napi_enable(&ch->napi); 432 } 433 phy_start(dev->phydev); 434 netif_tx_start_all_queues(dev); 435 return 0; 436 } 437 438 static int 439 ltq_etop_stop(struct net_device *dev) 440 { 441 struct ltq_etop_priv *priv = netdev_priv(dev); 442 int i; 443 444 netif_tx_stop_all_queues(dev); 445 phy_stop(dev->phydev); 446 for (i = 0; i < MAX_DMA_CHAN; i++) { 447 struct ltq_etop_chan *ch = &priv->ch[i]; 448 449 if (!IS_RX(i) && !IS_TX(i)) 450 continue; 451 napi_disable(&ch->napi); 452 ltq_dma_close(&ch->dma); 453 } 454 return 0; 455 } 456 457 static int 458 ltq_etop_tx(struct sk_buff *skb, struct net_device *dev) 459 { 460 int queue = skb_get_queue_mapping(skb); 461 struct netdev_queue *txq = netdev_get_tx_queue(dev, queue); 462 struct ltq_etop_priv *priv = netdev_priv(dev); 463 struct ltq_etop_chan *ch = &priv->ch[(queue << 1) | 1]; 464 struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->dma.desc]; 465 int len; 466 unsigned long flags; 467 u32 byte_offset; 468 469 len = skb->len < ETH_ZLEN ? ETH_ZLEN : skb->len; 470 471 if ((desc->ctl & (LTQ_DMA_OWN | LTQ_DMA_C)) || ch->skb[ch->dma.desc]) { 472 dev_kfree_skb_any(skb); 473 netdev_err(dev, "tx ring full\n"); 474 netif_tx_stop_queue(txq); 475 return NETDEV_TX_BUSY; 476 } 477 478 /* dma needs to start on a burst length value aligned address */ 479 byte_offset = CPHYSADDR(skb->data) % (priv->tx_burst_len * 4); 480 ch->skb[ch->dma.desc] = skb; 481 482 netif_trans_update(dev); 483 484 spin_lock_irqsave(&priv->lock, flags); 485 desc->addr = ((unsigned int) dma_map_single(&priv->pdev->dev, skb->data, len, 486 DMA_TO_DEVICE)) - byte_offset; 487 wmb(); 488 desc->ctl = LTQ_DMA_OWN | LTQ_DMA_SOP | LTQ_DMA_EOP | 489 LTQ_DMA_TX_OFFSET(byte_offset) | (len & LTQ_DMA_SIZE_MASK); 490 ch->dma.desc++; 491 ch->dma.desc %= LTQ_DESC_NUM; 492 spin_unlock_irqrestore(&priv->lock, flags); 493 494 if (ch->dma.desc_base[ch->dma.desc].ctl & LTQ_DMA_OWN) 495 netif_tx_stop_queue(txq); 496 497 return NETDEV_TX_OK; 498 } 499 500 static int 501 ltq_etop_change_mtu(struct net_device *dev, int new_mtu) 502 { 503 struct ltq_etop_priv *priv = netdev_priv(dev); 504 unsigned long flags; 505 506 dev->mtu = new_mtu; 507 508 spin_lock_irqsave(&priv->lock, flags); 509 ltq_etop_w32((ETOP_PLEN_UNDER << 16) | new_mtu, LTQ_ETOP_IGPLEN); 510 spin_unlock_irqrestore(&priv->lock, flags); 511 512 return 0; 513 } 514 515 static int 516 ltq_etop_set_mac_address(struct net_device *dev, void *p) 517 { 518 int ret = eth_mac_addr(dev, p); 519 520 if (!ret) { 521 struct ltq_etop_priv *priv = netdev_priv(dev); 522 unsigned long flags; 523 524 /* store the mac for the unicast filter */ 525 spin_lock_irqsave(&priv->lock, flags); 526 ltq_etop_w32(*((u32 *)dev->dev_addr), LTQ_ETOP_MAC_DA0); 527 ltq_etop_w32(*((u16 *)&dev->dev_addr[4]) << 16, 528 LTQ_ETOP_MAC_DA1); 529 spin_unlock_irqrestore(&priv->lock, flags); 530 } 531 return ret; 532 } 533 534 static void 535 ltq_etop_set_multicast_list(struct net_device *dev) 536 { 537 struct ltq_etop_priv *priv = netdev_priv(dev); 538 unsigned long flags; 539 540 /* ensure that the unicast filter is not enabled in promiscious mode */ 541 spin_lock_irqsave(&priv->lock, flags); 542 if ((dev->flags & IFF_PROMISC) || (dev->flags & IFF_ALLMULTI)) 543 ltq_etop_w32_mask(ETOP_FTCU, 0, LTQ_ETOP_ENETS0); 544 else 545 ltq_etop_w32_mask(0, ETOP_FTCU, LTQ_ETOP_ENETS0); 546 spin_unlock_irqrestore(&priv->lock, flags); 547 } 548 549 static int 550 ltq_etop_init(struct net_device *dev) 551 { 552 struct ltq_etop_priv *priv = netdev_priv(dev); 553 struct sockaddr mac; 554 int err; 555 bool random_mac = false; 556 557 dev->watchdog_timeo = 10 * HZ; 558 err = ltq_etop_hw_init(dev); 559 if (err) 560 goto err_hw; 561 ltq_etop_change_mtu(dev, 1500); 562 563 memcpy(&mac, &priv->pldata->mac, sizeof(struct sockaddr)); 564 if (!is_valid_ether_addr(mac.sa_data)) { 565 pr_warn("etop: invalid MAC, using random\n"); 566 eth_random_addr(mac.sa_data); 567 random_mac = true; 568 } 569 570 err = ltq_etop_set_mac_address(dev, &mac); 571 if (err) 572 goto err_netdev; 573 574 /* Set addr_assign_type here, ltq_etop_set_mac_address would reset it. */ 575 if (random_mac) 576 dev->addr_assign_type = NET_ADDR_RANDOM; 577 578 ltq_etop_set_multicast_list(dev); 579 err = ltq_etop_mdio_init(dev); 580 if (err) 581 goto err_netdev; 582 return 0; 583 584 err_netdev: 585 unregister_netdev(dev); 586 free_netdev(dev); 587 err_hw: 588 ltq_etop_hw_exit(dev); 589 return err; 590 } 591 592 static void 593 ltq_etop_tx_timeout(struct net_device *dev, unsigned int txqueue) 594 { 595 int err; 596 597 ltq_etop_hw_exit(dev); 598 err = ltq_etop_hw_init(dev); 599 if (err) 600 goto err_hw; 601 netif_trans_update(dev); 602 netif_wake_queue(dev); 603 return; 604 605 err_hw: 606 ltq_etop_hw_exit(dev); 607 netdev_err(dev, "failed to restart etop after TX timeout\n"); 608 } 609 610 static const struct net_device_ops ltq_eth_netdev_ops = { 611 .ndo_open = ltq_etop_open, 612 .ndo_stop = ltq_etop_stop, 613 .ndo_start_xmit = ltq_etop_tx, 614 .ndo_change_mtu = ltq_etop_change_mtu, 615 .ndo_eth_ioctl = phy_do_ioctl, 616 .ndo_set_mac_address = ltq_etop_set_mac_address, 617 .ndo_validate_addr = eth_validate_addr, 618 .ndo_set_rx_mode = ltq_etop_set_multicast_list, 619 .ndo_select_queue = dev_pick_tx_zero, 620 .ndo_init = ltq_etop_init, 621 .ndo_tx_timeout = ltq_etop_tx_timeout, 622 }; 623 624 static int __init 625 ltq_etop_probe(struct platform_device *pdev) 626 { 627 struct net_device *dev; 628 struct ltq_etop_priv *priv; 629 struct resource *res; 630 int err; 631 int i; 632 633 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 634 if (!res) { 635 dev_err(&pdev->dev, "failed to get etop resource\n"); 636 err = -ENOENT; 637 goto err_out; 638 } 639 640 res = devm_request_mem_region(&pdev->dev, res->start, 641 resource_size(res), dev_name(&pdev->dev)); 642 if (!res) { 643 dev_err(&pdev->dev, "failed to request etop resource\n"); 644 err = -EBUSY; 645 goto err_out; 646 } 647 648 ltq_etop_membase = devm_ioremap(&pdev->dev, 649 res->start, resource_size(res)); 650 if (!ltq_etop_membase) { 651 dev_err(&pdev->dev, "failed to remap etop engine %d\n", 652 pdev->id); 653 err = -ENOMEM; 654 goto err_out; 655 } 656 657 dev = alloc_etherdev_mq(sizeof(struct ltq_etop_priv), 4); 658 if (!dev) { 659 err = -ENOMEM; 660 goto err_out; 661 } 662 strcpy(dev->name, "eth%d"); 663 dev->netdev_ops = <q_eth_netdev_ops; 664 dev->ethtool_ops = <q_etop_ethtool_ops; 665 priv = netdev_priv(dev); 666 priv->res = res; 667 priv->pdev = pdev; 668 priv->pldata = dev_get_platdata(&pdev->dev); 669 priv->netdev = dev; 670 spin_lock_init(&priv->lock); 671 SET_NETDEV_DEV(dev, &pdev->dev); 672 673 err = device_property_read_u32(&pdev->dev, "lantiq,tx-burst-length", &priv->tx_burst_len); 674 if (err < 0) { 675 dev_err(&pdev->dev, "unable to read tx-burst-length property\n"); 676 return err; 677 } 678 679 err = device_property_read_u32(&pdev->dev, "lantiq,rx-burst-length", &priv->rx_burst_len); 680 if (err < 0) { 681 dev_err(&pdev->dev, "unable to read rx-burst-length property\n"); 682 return err; 683 } 684 685 for (i = 0; i < MAX_DMA_CHAN; i++) { 686 if (IS_TX(i)) 687 netif_napi_add(dev, &priv->ch[i].napi, 688 ltq_etop_poll_tx, 8); 689 else if (IS_RX(i)) 690 netif_napi_add(dev, &priv->ch[i].napi, 691 ltq_etop_poll_rx, 32); 692 priv->ch[i].netdev = dev; 693 } 694 695 err = register_netdev(dev); 696 if (err) 697 goto err_free; 698 699 platform_set_drvdata(pdev, dev); 700 return 0; 701 702 err_free: 703 free_netdev(dev); 704 err_out: 705 return err; 706 } 707 708 static int 709 ltq_etop_remove(struct platform_device *pdev) 710 { 711 struct net_device *dev = platform_get_drvdata(pdev); 712 713 if (dev) { 714 netif_tx_stop_all_queues(dev); 715 ltq_etop_hw_exit(dev); 716 ltq_etop_mdio_cleanup(dev); 717 unregister_netdev(dev); 718 } 719 return 0; 720 } 721 722 static struct platform_driver ltq_mii_driver = { 723 .remove = ltq_etop_remove, 724 .driver = { 725 .name = "ltq_etop", 726 }, 727 }; 728 729 int __init 730 init_ltq_etop(void) 731 { 732 int ret = platform_driver_probe(<q_mii_driver, ltq_etop_probe); 733 734 if (ret) 735 pr_err("ltq_etop: Error registering platform driver!"); 736 return ret; 737 } 738 739 static void __exit 740 exit_ltq_etop(void) 741 { 742 platform_driver_unregister(<q_mii_driver); 743 } 744 745 module_init(init_ltq_etop); 746 module_exit(exit_ltq_etop); 747 748 MODULE_AUTHOR("John Crispin <blogic@openwrt.org>"); 749 MODULE_DESCRIPTION("Lantiq SoC ETOP"); 750 MODULE_LICENSE("GPL"); 751