1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * 4 * Copyright (C) 2011 John Crispin <blogic@openwrt.org> 5 */ 6 7 #include <linux/kernel.h> 8 #include <linux/slab.h> 9 #include <linux/errno.h> 10 #include <linux/types.h> 11 #include <linux/interrupt.h> 12 #include <linux/uaccess.h> 13 #include <linux/in.h> 14 #include <linux/netdevice.h> 15 #include <linux/etherdevice.h> 16 #include <linux/phy.h> 17 #include <linux/ip.h> 18 #include <linux/tcp.h> 19 #include <linux/skbuff.h> 20 #include <linux/mm.h> 21 #include <linux/platform_device.h> 22 #include <linux/ethtool.h> 23 #include <linux/init.h> 24 #include <linux/delay.h> 25 #include <linux/io.h> 26 #include <linux/dma-mapping.h> 27 #include <linux/module.h> 28 29 #include <asm/checksum.h> 30 31 #include <lantiq_soc.h> 32 #include <xway_dma.h> 33 #include <lantiq_platform.h> 34 35 #define LTQ_ETOP_MDIO 0x11804 36 #define MDIO_REQUEST 0x80000000 37 #define MDIO_READ 0x40000000 38 #define MDIO_ADDR_MASK 0x1f 39 #define MDIO_ADDR_OFFSET 0x15 40 #define MDIO_REG_MASK 0x1f 41 #define MDIO_REG_OFFSET 0x10 42 #define MDIO_VAL_MASK 0xffff 43 44 #define PPE32_CGEN 0x800 45 #define LQ_PPE32_ENET_MAC_CFG 0x1840 46 47 #define LTQ_ETOP_ENETS0 0x11850 48 #define LTQ_ETOP_MAC_DA0 0x1186C 49 #define LTQ_ETOP_MAC_DA1 0x11870 50 #define LTQ_ETOP_CFG 0x16020 51 #define LTQ_ETOP_IGPLEN 0x16080 52 53 #define MAX_DMA_CHAN 0x8 54 #define MAX_DMA_CRC_LEN 0x4 55 #define MAX_DMA_DATA_LEN 0x600 56 57 #define ETOP_FTCU BIT(28) 58 #define ETOP_MII_MASK 0xf 59 #define ETOP_MII_NORMAL 0xd 60 #define ETOP_MII_REVERSE 0xe 61 #define ETOP_PLEN_UNDER 0x40 62 #define ETOP_CGEN 0x800 63 64 /* use 2 static channels for TX/RX */ 65 #define LTQ_ETOP_TX_CHANNEL 1 66 #define LTQ_ETOP_RX_CHANNEL 6 67 #define IS_TX(x) (x == LTQ_ETOP_TX_CHANNEL) 68 #define IS_RX(x) (x == LTQ_ETOP_RX_CHANNEL) 69 70 #define ltq_etop_r32(x) ltq_r32(ltq_etop_membase + (x)) 71 #define ltq_etop_w32(x, y) ltq_w32(x, ltq_etop_membase + (y)) 72 #define ltq_etop_w32_mask(x, y, z) \ 73 ltq_w32_mask(x, y, ltq_etop_membase + (z)) 74 75 #define DRV_VERSION "1.0" 76 77 static void __iomem *ltq_etop_membase; 78 79 struct ltq_etop_chan { 80 int idx; 81 int tx_free; 82 struct net_device *netdev; 83 struct napi_struct napi; 84 struct ltq_dma_channel dma; 85 struct sk_buff *skb[LTQ_DESC_NUM]; 86 }; 87 88 struct ltq_etop_priv { 89 struct net_device *netdev; 90 struct platform_device *pdev; 91 struct ltq_eth_data *pldata; 92 struct resource *res; 93 94 struct mii_bus *mii_bus; 95 96 struct ltq_etop_chan ch[MAX_DMA_CHAN]; 97 int tx_free[MAX_DMA_CHAN >> 1]; 98 99 spinlock_t lock; 100 }; 101 102 static int 103 ltq_etop_alloc_skb(struct ltq_etop_chan *ch) 104 { 105 struct ltq_etop_priv *priv = netdev_priv(ch->netdev); 106 107 ch->skb[ch->dma.desc] = netdev_alloc_skb(ch->netdev, MAX_DMA_DATA_LEN); 108 if (!ch->skb[ch->dma.desc]) 109 return -ENOMEM; 110 ch->dma.desc_base[ch->dma.desc].addr = dma_map_single(&priv->pdev->dev, 111 ch->skb[ch->dma.desc]->data, MAX_DMA_DATA_LEN, 112 DMA_FROM_DEVICE); 113 ch->dma.desc_base[ch->dma.desc].addr = 114 CPHYSADDR(ch->skb[ch->dma.desc]->data); 115 ch->dma.desc_base[ch->dma.desc].ctl = 116 LTQ_DMA_OWN | LTQ_DMA_RX_OFFSET(NET_IP_ALIGN) | 117 MAX_DMA_DATA_LEN; 118 skb_reserve(ch->skb[ch->dma.desc], NET_IP_ALIGN); 119 return 0; 120 } 121 122 static void 123 ltq_etop_hw_receive(struct ltq_etop_chan *ch) 124 { 125 struct ltq_etop_priv *priv = netdev_priv(ch->netdev); 126 struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->dma.desc]; 127 struct sk_buff *skb = ch->skb[ch->dma.desc]; 128 int len = (desc->ctl & LTQ_DMA_SIZE_MASK) - MAX_DMA_CRC_LEN; 129 unsigned long flags; 130 131 spin_lock_irqsave(&priv->lock, flags); 132 if (ltq_etop_alloc_skb(ch)) { 133 netdev_err(ch->netdev, 134 "failed to allocate new rx buffer, stopping DMA\n"); 135 ltq_dma_close(&ch->dma); 136 } 137 ch->dma.desc++; 138 ch->dma.desc %= LTQ_DESC_NUM; 139 spin_unlock_irqrestore(&priv->lock, flags); 140 141 skb_put(skb, len); 142 skb->protocol = eth_type_trans(skb, ch->netdev); 143 netif_receive_skb(skb); 144 } 145 146 static int 147 ltq_etop_poll_rx(struct napi_struct *napi, int budget) 148 { 149 struct ltq_etop_chan *ch = container_of(napi, 150 struct ltq_etop_chan, napi); 151 int work_done = 0; 152 153 while (work_done < budget) { 154 struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->dma.desc]; 155 156 if ((desc->ctl & (LTQ_DMA_OWN | LTQ_DMA_C)) != LTQ_DMA_C) 157 break; 158 ltq_etop_hw_receive(ch); 159 work_done++; 160 } 161 if (work_done < budget) { 162 napi_complete_done(&ch->napi, work_done); 163 ltq_dma_ack_irq(&ch->dma); 164 } 165 return work_done; 166 } 167 168 static int 169 ltq_etop_poll_tx(struct napi_struct *napi, int budget) 170 { 171 struct ltq_etop_chan *ch = 172 container_of(napi, struct ltq_etop_chan, napi); 173 struct ltq_etop_priv *priv = netdev_priv(ch->netdev); 174 struct netdev_queue *txq = 175 netdev_get_tx_queue(ch->netdev, ch->idx >> 1); 176 unsigned long flags; 177 178 spin_lock_irqsave(&priv->lock, flags); 179 while ((ch->dma.desc_base[ch->tx_free].ctl & 180 (LTQ_DMA_OWN | LTQ_DMA_C)) == LTQ_DMA_C) { 181 dev_kfree_skb_any(ch->skb[ch->tx_free]); 182 ch->skb[ch->tx_free] = NULL; 183 memset(&ch->dma.desc_base[ch->tx_free], 0, 184 sizeof(struct ltq_dma_desc)); 185 ch->tx_free++; 186 ch->tx_free %= LTQ_DESC_NUM; 187 } 188 spin_unlock_irqrestore(&priv->lock, flags); 189 190 if (netif_tx_queue_stopped(txq)) 191 netif_tx_start_queue(txq); 192 napi_complete(&ch->napi); 193 ltq_dma_ack_irq(&ch->dma); 194 return 1; 195 } 196 197 static irqreturn_t 198 ltq_etop_dma_irq(int irq, void *_priv) 199 { 200 struct ltq_etop_priv *priv = _priv; 201 int ch = irq - LTQ_DMA_CH0_INT; 202 203 napi_schedule(&priv->ch[ch].napi); 204 return IRQ_HANDLED; 205 } 206 207 static void 208 ltq_etop_free_channel(struct net_device *dev, struct ltq_etop_chan *ch) 209 { 210 struct ltq_etop_priv *priv = netdev_priv(dev); 211 212 ltq_dma_free(&ch->dma); 213 if (ch->dma.irq) 214 free_irq(ch->dma.irq, priv); 215 if (IS_RX(ch->idx)) { 216 int desc; 217 for (desc = 0; desc < LTQ_DESC_NUM; desc++) 218 dev_kfree_skb_any(ch->skb[ch->dma.desc]); 219 } 220 } 221 222 static void 223 ltq_etop_hw_exit(struct net_device *dev) 224 { 225 struct ltq_etop_priv *priv = netdev_priv(dev); 226 int i; 227 228 ltq_pmu_disable(PMU_PPE); 229 for (i = 0; i < MAX_DMA_CHAN; i++) 230 if (IS_TX(i) || IS_RX(i)) 231 ltq_etop_free_channel(dev, &priv->ch[i]); 232 } 233 234 static int 235 ltq_etop_hw_init(struct net_device *dev) 236 { 237 struct ltq_etop_priv *priv = netdev_priv(dev); 238 int i; 239 240 ltq_pmu_enable(PMU_PPE); 241 242 switch (priv->pldata->mii_mode) { 243 case PHY_INTERFACE_MODE_RMII: 244 ltq_etop_w32_mask(ETOP_MII_MASK, 245 ETOP_MII_REVERSE, LTQ_ETOP_CFG); 246 break; 247 248 case PHY_INTERFACE_MODE_MII: 249 ltq_etop_w32_mask(ETOP_MII_MASK, 250 ETOP_MII_NORMAL, LTQ_ETOP_CFG); 251 break; 252 253 default: 254 netdev_err(dev, "unknown mii mode %d\n", 255 priv->pldata->mii_mode); 256 return -ENOTSUPP; 257 } 258 259 /* enable crc generation */ 260 ltq_etop_w32(PPE32_CGEN, LQ_PPE32_ENET_MAC_CFG); 261 262 ltq_dma_init_port(DMA_PORT_ETOP); 263 264 for (i = 0; i < MAX_DMA_CHAN; i++) { 265 int irq = LTQ_DMA_CH0_INT + i; 266 struct ltq_etop_chan *ch = &priv->ch[i]; 267 268 ch->idx = ch->dma.nr = i; 269 ch->dma.dev = &priv->pdev->dev; 270 271 if (IS_TX(i)) { 272 ltq_dma_alloc_tx(&ch->dma); 273 request_irq(irq, ltq_etop_dma_irq, 0, "etop_tx", priv); 274 } else if (IS_RX(i)) { 275 ltq_dma_alloc_rx(&ch->dma); 276 for (ch->dma.desc = 0; ch->dma.desc < LTQ_DESC_NUM; 277 ch->dma.desc++) 278 if (ltq_etop_alloc_skb(ch)) 279 return -ENOMEM; 280 ch->dma.desc = 0; 281 request_irq(irq, ltq_etop_dma_irq, 0, "etop_rx", priv); 282 } 283 ch->dma.irq = irq; 284 } 285 return 0; 286 } 287 288 static void 289 ltq_etop_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info) 290 { 291 strlcpy(info->driver, "Lantiq ETOP", sizeof(info->driver)); 292 strlcpy(info->bus_info, "internal", sizeof(info->bus_info)); 293 strlcpy(info->version, DRV_VERSION, sizeof(info->version)); 294 } 295 296 static const struct ethtool_ops ltq_etop_ethtool_ops = { 297 .get_drvinfo = ltq_etop_get_drvinfo, 298 .nway_reset = phy_ethtool_nway_reset, 299 .get_link_ksettings = phy_ethtool_get_link_ksettings, 300 .set_link_ksettings = phy_ethtool_set_link_ksettings, 301 }; 302 303 static int 304 ltq_etop_mdio_wr(struct mii_bus *bus, int phy_addr, int phy_reg, u16 phy_data) 305 { 306 u32 val = MDIO_REQUEST | 307 ((phy_addr & MDIO_ADDR_MASK) << MDIO_ADDR_OFFSET) | 308 ((phy_reg & MDIO_REG_MASK) << MDIO_REG_OFFSET) | 309 phy_data; 310 311 while (ltq_etop_r32(LTQ_ETOP_MDIO) & MDIO_REQUEST) 312 ; 313 ltq_etop_w32(val, LTQ_ETOP_MDIO); 314 return 0; 315 } 316 317 static int 318 ltq_etop_mdio_rd(struct mii_bus *bus, int phy_addr, int phy_reg) 319 { 320 u32 val = MDIO_REQUEST | MDIO_READ | 321 ((phy_addr & MDIO_ADDR_MASK) << MDIO_ADDR_OFFSET) | 322 ((phy_reg & MDIO_REG_MASK) << MDIO_REG_OFFSET); 323 324 while (ltq_etop_r32(LTQ_ETOP_MDIO) & MDIO_REQUEST) 325 ; 326 ltq_etop_w32(val, LTQ_ETOP_MDIO); 327 while (ltq_etop_r32(LTQ_ETOP_MDIO) & MDIO_REQUEST) 328 ; 329 val = ltq_etop_r32(LTQ_ETOP_MDIO) & MDIO_VAL_MASK; 330 return val; 331 } 332 333 static void 334 ltq_etop_mdio_link(struct net_device *dev) 335 { 336 /* nothing to do */ 337 } 338 339 static int 340 ltq_etop_mdio_probe(struct net_device *dev) 341 { 342 struct ltq_etop_priv *priv = netdev_priv(dev); 343 struct phy_device *phydev; 344 345 phydev = phy_find_first(priv->mii_bus); 346 347 if (!phydev) { 348 netdev_err(dev, "no PHY found\n"); 349 return -ENODEV; 350 } 351 352 phydev = phy_connect(dev, phydev_name(phydev), 353 <q_etop_mdio_link, priv->pldata->mii_mode); 354 355 if (IS_ERR(phydev)) { 356 netdev_err(dev, "Could not attach to PHY\n"); 357 return PTR_ERR(phydev); 358 } 359 360 phy_set_max_speed(phydev, SPEED_100); 361 362 phy_attached_info(phydev); 363 364 return 0; 365 } 366 367 static int 368 ltq_etop_mdio_init(struct net_device *dev) 369 { 370 struct ltq_etop_priv *priv = netdev_priv(dev); 371 int err; 372 373 priv->mii_bus = mdiobus_alloc(); 374 if (!priv->mii_bus) { 375 netdev_err(dev, "failed to allocate mii bus\n"); 376 err = -ENOMEM; 377 goto err_out; 378 } 379 380 priv->mii_bus->priv = dev; 381 priv->mii_bus->read = ltq_etop_mdio_rd; 382 priv->mii_bus->write = ltq_etop_mdio_wr; 383 priv->mii_bus->name = "ltq_mii"; 384 snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x", 385 priv->pdev->name, priv->pdev->id); 386 if (mdiobus_register(priv->mii_bus)) { 387 err = -ENXIO; 388 goto err_out_free_mdiobus; 389 } 390 391 if (ltq_etop_mdio_probe(dev)) { 392 err = -ENXIO; 393 goto err_out_unregister_bus; 394 } 395 return 0; 396 397 err_out_unregister_bus: 398 mdiobus_unregister(priv->mii_bus); 399 err_out_free_mdiobus: 400 mdiobus_free(priv->mii_bus); 401 err_out: 402 return err; 403 } 404 405 static void 406 ltq_etop_mdio_cleanup(struct net_device *dev) 407 { 408 struct ltq_etop_priv *priv = netdev_priv(dev); 409 410 phy_disconnect(dev->phydev); 411 mdiobus_unregister(priv->mii_bus); 412 mdiobus_free(priv->mii_bus); 413 } 414 415 static int 416 ltq_etop_open(struct net_device *dev) 417 { 418 struct ltq_etop_priv *priv = netdev_priv(dev); 419 int i; 420 421 for (i = 0; i < MAX_DMA_CHAN; i++) { 422 struct ltq_etop_chan *ch = &priv->ch[i]; 423 424 if (!IS_TX(i) && (!IS_RX(i))) 425 continue; 426 ltq_dma_open(&ch->dma); 427 ltq_dma_enable_irq(&ch->dma); 428 napi_enable(&ch->napi); 429 } 430 phy_start(dev->phydev); 431 netif_tx_start_all_queues(dev); 432 return 0; 433 } 434 435 static int 436 ltq_etop_stop(struct net_device *dev) 437 { 438 struct ltq_etop_priv *priv = netdev_priv(dev); 439 int i; 440 441 netif_tx_stop_all_queues(dev); 442 phy_stop(dev->phydev); 443 for (i = 0; i < MAX_DMA_CHAN; i++) { 444 struct ltq_etop_chan *ch = &priv->ch[i]; 445 446 if (!IS_RX(i) && !IS_TX(i)) 447 continue; 448 napi_disable(&ch->napi); 449 ltq_dma_close(&ch->dma); 450 } 451 return 0; 452 } 453 454 static int 455 ltq_etop_tx(struct sk_buff *skb, struct net_device *dev) 456 { 457 int queue = skb_get_queue_mapping(skb); 458 struct netdev_queue *txq = netdev_get_tx_queue(dev, queue); 459 struct ltq_etop_priv *priv = netdev_priv(dev); 460 struct ltq_etop_chan *ch = &priv->ch[(queue << 1) | 1]; 461 struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->dma.desc]; 462 int len; 463 unsigned long flags; 464 u32 byte_offset; 465 466 len = skb->len < ETH_ZLEN ? ETH_ZLEN : skb->len; 467 468 if ((desc->ctl & (LTQ_DMA_OWN | LTQ_DMA_C)) || ch->skb[ch->dma.desc]) { 469 dev_kfree_skb_any(skb); 470 netdev_err(dev, "tx ring full\n"); 471 netif_tx_stop_queue(txq); 472 return NETDEV_TX_BUSY; 473 } 474 475 /* dma needs to start on a 16 byte aligned address */ 476 byte_offset = CPHYSADDR(skb->data) % 16; 477 ch->skb[ch->dma.desc] = skb; 478 479 netif_trans_update(dev); 480 481 spin_lock_irqsave(&priv->lock, flags); 482 desc->addr = ((unsigned int) dma_map_single(&priv->pdev->dev, skb->data, len, 483 DMA_TO_DEVICE)) - byte_offset; 484 wmb(); 485 desc->ctl = LTQ_DMA_OWN | LTQ_DMA_SOP | LTQ_DMA_EOP | 486 LTQ_DMA_TX_OFFSET(byte_offset) | (len & LTQ_DMA_SIZE_MASK); 487 ch->dma.desc++; 488 ch->dma.desc %= LTQ_DESC_NUM; 489 spin_unlock_irqrestore(&priv->lock, flags); 490 491 if (ch->dma.desc_base[ch->dma.desc].ctl & LTQ_DMA_OWN) 492 netif_tx_stop_queue(txq); 493 494 return NETDEV_TX_OK; 495 } 496 497 static int 498 ltq_etop_change_mtu(struct net_device *dev, int new_mtu) 499 { 500 struct ltq_etop_priv *priv = netdev_priv(dev); 501 unsigned long flags; 502 503 dev->mtu = new_mtu; 504 505 spin_lock_irqsave(&priv->lock, flags); 506 ltq_etop_w32((ETOP_PLEN_UNDER << 16) | new_mtu, LTQ_ETOP_IGPLEN); 507 spin_unlock_irqrestore(&priv->lock, flags); 508 509 return 0; 510 } 511 512 static int 513 ltq_etop_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) 514 { 515 /* TODO: mii-toll reports "No MII transceiver present!." ?!*/ 516 return phy_mii_ioctl(dev->phydev, rq, cmd); 517 } 518 519 static int 520 ltq_etop_set_mac_address(struct net_device *dev, void *p) 521 { 522 int ret = eth_mac_addr(dev, p); 523 524 if (!ret) { 525 struct ltq_etop_priv *priv = netdev_priv(dev); 526 unsigned long flags; 527 528 /* store the mac for the unicast filter */ 529 spin_lock_irqsave(&priv->lock, flags); 530 ltq_etop_w32(*((u32 *)dev->dev_addr), LTQ_ETOP_MAC_DA0); 531 ltq_etop_w32(*((u16 *)&dev->dev_addr[4]) << 16, 532 LTQ_ETOP_MAC_DA1); 533 spin_unlock_irqrestore(&priv->lock, flags); 534 } 535 return ret; 536 } 537 538 static void 539 ltq_etop_set_multicast_list(struct net_device *dev) 540 { 541 struct ltq_etop_priv *priv = netdev_priv(dev); 542 unsigned long flags; 543 544 /* ensure that the unicast filter is not enabled in promiscious mode */ 545 spin_lock_irqsave(&priv->lock, flags); 546 if ((dev->flags & IFF_PROMISC) || (dev->flags & IFF_ALLMULTI)) 547 ltq_etop_w32_mask(ETOP_FTCU, 0, LTQ_ETOP_ENETS0); 548 else 549 ltq_etop_w32_mask(0, ETOP_FTCU, LTQ_ETOP_ENETS0); 550 spin_unlock_irqrestore(&priv->lock, flags); 551 } 552 553 static int 554 ltq_etop_init(struct net_device *dev) 555 { 556 struct ltq_etop_priv *priv = netdev_priv(dev); 557 struct sockaddr mac; 558 int err; 559 bool random_mac = false; 560 561 dev->watchdog_timeo = 10 * HZ; 562 err = ltq_etop_hw_init(dev); 563 if (err) 564 goto err_hw; 565 ltq_etop_change_mtu(dev, 1500); 566 567 memcpy(&mac, &priv->pldata->mac, sizeof(struct sockaddr)); 568 if (!is_valid_ether_addr(mac.sa_data)) { 569 pr_warn("etop: invalid MAC, using random\n"); 570 eth_random_addr(mac.sa_data); 571 random_mac = true; 572 } 573 574 err = ltq_etop_set_mac_address(dev, &mac); 575 if (err) 576 goto err_netdev; 577 578 /* Set addr_assign_type here, ltq_etop_set_mac_address would reset it. */ 579 if (random_mac) 580 dev->addr_assign_type = NET_ADDR_RANDOM; 581 582 ltq_etop_set_multicast_list(dev); 583 err = ltq_etop_mdio_init(dev); 584 if (err) 585 goto err_netdev; 586 return 0; 587 588 err_netdev: 589 unregister_netdev(dev); 590 free_netdev(dev); 591 err_hw: 592 ltq_etop_hw_exit(dev); 593 return err; 594 } 595 596 static void 597 ltq_etop_tx_timeout(struct net_device *dev) 598 { 599 int err; 600 601 ltq_etop_hw_exit(dev); 602 err = ltq_etop_hw_init(dev); 603 if (err) 604 goto err_hw; 605 netif_trans_update(dev); 606 netif_wake_queue(dev); 607 return; 608 609 err_hw: 610 ltq_etop_hw_exit(dev); 611 netdev_err(dev, "failed to restart etop after TX timeout\n"); 612 } 613 614 static const struct net_device_ops ltq_eth_netdev_ops = { 615 .ndo_open = ltq_etop_open, 616 .ndo_stop = ltq_etop_stop, 617 .ndo_start_xmit = ltq_etop_tx, 618 .ndo_change_mtu = ltq_etop_change_mtu, 619 .ndo_do_ioctl = ltq_etop_ioctl, 620 .ndo_set_mac_address = ltq_etop_set_mac_address, 621 .ndo_validate_addr = eth_validate_addr, 622 .ndo_set_rx_mode = ltq_etop_set_multicast_list, 623 .ndo_select_queue = dev_pick_tx_zero, 624 .ndo_init = ltq_etop_init, 625 .ndo_tx_timeout = ltq_etop_tx_timeout, 626 }; 627 628 static int __init 629 ltq_etop_probe(struct platform_device *pdev) 630 { 631 struct net_device *dev; 632 struct ltq_etop_priv *priv; 633 struct resource *res; 634 int err; 635 int i; 636 637 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 638 if (!res) { 639 dev_err(&pdev->dev, "failed to get etop resource\n"); 640 err = -ENOENT; 641 goto err_out; 642 } 643 644 res = devm_request_mem_region(&pdev->dev, res->start, 645 resource_size(res), dev_name(&pdev->dev)); 646 if (!res) { 647 dev_err(&pdev->dev, "failed to request etop resource\n"); 648 err = -EBUSY; 649 goto err_out; 650 } 651 652 ltq_etop_membase = devm_ioremap_nocache(&pdev->dev, 653 res->start, resource_size(res)); 654 if (!ltq_etop_membase) { 655 dev_err(&pdev->dev, "failed to remap etop engine %d\n", 656 pdev->id); 657 err = -ENOMEM; 658 goto err_out; 659 } 660 661 dev = alloc_etherdev_mq(sizeof(struct ltq_etop_priv), 4); 662 if (!dev) { 663 err = -ENOMEM; 664 goto err_out; 665 } 666 strcpy(dev->name, "eth%d"); 667 dev->netdev_ops = <q_eth_netdev_ops; 668 dev->ethtool_ops = <q_etop_ethtool_ops; 669 priv = netdev_priv(dev); 670 priv->res = res; 671 priv->pdev = pdev; 672 priv->pldata = dev_get_platdata(&pdev->dev); 673 priv->netdev = dev; 674 spin_lock_init(&priv->lock); 675 SET_NETDEV_DEV(dev, &pdev->dev); 676 677 for (i = 0; i < MAX_DMA_CHAN; i++) { 678 if (IS_TX(i)) 679 netif_napi_add(dev, &priv->ch[i].napi, 680 ltq_etop_poll_tx, 8); 681 else if (IS_RX(i)) 682 netif_napi_add(dev, &priv->ch[i].napi, 683 ltq_etop_poll_rx, 32); 684 priv->ch[i].netdev = dev; 685 } 686 687 err = register_netdev(dev); 688 if (err) 689 goto err_free; 690 691 platform_set_drvdata(pdev, dev); 692 return 0; 693 694 err_free: 695 free_netdev(dev); 696 err_out: 697 return err; 698 } 699 700 static int 701 ltq_etop_remove(struct platform_device *pdev) 702 { 703 struct net_device *dev = platform_get_drvdata(pdev); 704 705 if (dev) { 706 netif_tx_stop_all_queues(dev); 707 ltq_etop_hw_exit(dev); 708 ltq_etop_mdio_cleanup(dev); 709 unregister_netdev(dev); 710 } 711 return 0; 712 } 713 714 static struct platform_driver ltq_mii_driver = { 715 .remove = ltq_etop_remove, 716 .driver = { 717 .name = "ltq_etop", 718 }, 719 }; 720 721 int __init 722 init_ltq_etop(void) 723 { 724 int ret = platform_driver_probe(<q_mii_driver, ltq_etop_probe); 725 726 if (ret) 727 pr_err("ltq_etop: Error registering platform driver!"); 728 return ret; 729 } 730 731 static void __exit 732 exit_ltq_etop(void) 733 { 734 platform_driver_unregister(<q_mii_driver); 735 } 736 737 module_init(init_ltq_etop); 738 module_exit(exit_ltq_etop); 739 740 MODULE_AUTHOR("John Crispin <blogic@openwrt.org>"); 741 MODULE_DESCRIPTION("Lantiq SoC ETOP"); 742 MODULE_LICENSE("GPL"); 743