1 /* 2 * This program is free software; you can redistribute it and/or modify it 3 * under the terms of the GNU General Public License version 2 as published 4 * by the Free Software Foundation. 5 * 6 * This program is distributed in the hope that it will be useful, 7 * but WITHOUT ANY WARRANTY; without even the implied warranty of 8 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 9 * GNU General Public License for more details. 10 * 11 * You should have received a copy of the GNU General Public License 12 * along with this program; if not, see <http://www.gnu.org/licenses/>. 13 * 14 * Copyright (C) 2011 John Crispin <blogic@openwrt.org> 15 */ 16 17 #include <linux/kernel.h> 18 #include <linux/slab.h> 19 #include <linux/errno.h> 20 #include <linux/types.h> 21 #include <linux/interrupt.h> 22 #include <linux/uaccess.h> 23 #include <linux/in.h> 24 #include <linux/netdevice.h> 25 #include <linux/etherdevice.h> 26 #include <linux/phy.h> 27 #include <linux/ip.h> 28 #include <linux/tcp.h> 29 #include <linux/skbuff.h> 30 #include <linux/mm.h> 31 #include <linux/platform_device.h> 32 #include <linux/ethtool.h> 33 #include <linux/init.h> 34 #include <linux/delay.h> 35 #include <linux/io.h> 36 #include <linux/dma-mapping.h> 37 #include <linux/module.h> 38 39 #include <asm/checksum.h> 40 41 #include <lantiq_soc.h> 42 #include <xway_dma.h> 43 #include <lantiq_platform.h> 44 45 #define LTQ_ETOP_MDIO 0x11804 46 #define MDIO_REQUEST 0x80000000 47 #define MDIO_READ 0x40000000 48 #define MDIO_ADDR_MASK 0x1f 49 #define MDIO_ADDR_OFFSET 0x15 50 #define MDIO_REG_MASK 0x1f 51 #define MDIO_REG_OFFSET 0x10 52 #define MDIO_VAL_MASK 0xffff 53 54 #define PPE32_CGEN 0x800 55 #define LQ_PPE32_ENET_MAC_CFG 0x1840 56 57 #define LTQ_ETOP_ENETS0 0x11850 58 #define LTQ_ETOP_MAC_DA0 0x1186C 59 #define LTQ_ETOP_MAC_DA1 0x11870 60 #define LTQ_ETOP_CFG 0x16020 61 #define LTQ_ETOP_IGPLEN 0x16080 62 63 #define MAX_DMA_CHAN 0x8 64 #define MAX_DMA_CRC_LEN 0x4 65 #define MAX_DMA_DATA_LEN 0x600 66 67 #define ETOP_FTCU BIT(28) 68 #define ETOP_MII_MASK 0xf 69 #define ETOP_MII_NORMAL 0xd 70 #define ETOP_MII_REVERSE 0xe 71 #define ETOP_PLEN_UNDER 0x40 72 #define ETOP_CGEN 0x800 73 74 /* use 2 static channels for TX/RX */ 75 #define LTQ_ETOP_TX_CHANNEL 1 76 #define LTQ_ETOP_RX_CHANNEL 6 77 #define IS_TX(x) (x == LTQ_ETOP_TX_CHANNEL) 78 #define IS_RX(x) (x == LTQ_ETOP_RX_CHANNEL) 79 80 #define ltq_etop_r32(x) ltq_r32(ltq_etop_membase + (x)) 81 #define ltq_etop_w32(x, y) ltq_w32(x, ltq_etop_membase + (y)) 82 #define ltq_etop_w32_mask(x, y, z) \ 83 ltq_w32_mask(x, y, ltq_etop_membase + (z)) 84 85 #define DRV_VERSION "1.0" 86 87 static void __iomem *ltq_etop_membase; 88 89 struct ltq_etop_chan { 90 int idx; 91 int tx_free; 92 struct net_device *netdev; 93 struct napi_struct napi; 94 struct ltq_dma_channel dma; 95 struct sk_buff *skb[LTQ_DESC_NUM]; 96 }; 97 98 struct ltq_etop_priv { 99 struct net_device *netdev; 100 struct platform_device *pdev; 101 struct ltq_eth_data *pldata; 102 struct resource *res; 103 104 struct mii_bus *mii_bus; 105 106 struct ltq_etop_chan ch[MAX_DMA_CHAN]; 107 int tx_free[MAX_DMA_CHAN >> 1]; 108 109 spinlock_t lock; 110 }; 111 112 static int 113 ltq_etop_alloc_skb(struct ltq_etop_chan *ch) 114 { 115 ch->skb[ch->dma.desc] = netdev_alloc_skb(ch->netdev, MAX_DMA_DATA_LEN); 116 if (!ch->skb[ch->dma.desc]) 117 return -ENOMEM; 118 ch->dma.desc_base[ch->dma.desc].addr = dma_map_single(NULL, 119 ch->skb[ch->dma.desc]->data, MAX_DMA_DATA_LEN, 120 DMA_FROM_DEVICE); 121 ch->dma.desc_base[ch->dma.desc].addr = 122 CPHYSADDR(ch->skb[ch->dma.desc]->data); 123 ch->dma.desc_base[ch->dma.desc].ctl = 124 LTQ_DMA_OWN | LTQ_DMA_RX_OFFSET(NET_IP_ALIGN) | 125 MAX_DMA_DATA_LEN; 126 skb_reserve(ch->skb[ch->dma.desc], NET_IP_ALIGN); 127 return 0; 128 } 129 130 static void 131 ltq_etop_hw_receive(struct ltq_etop_chan *ch) 132 { 133 struct ltq_etop_priv *priv = netdev_priv(ch->netdev); 134 struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->dma.desc]; 135 struct sk_buff *skb = ch->skb[ch->dma.desc]; 136 int len = (desc->ctl & LTQ_DMA_SIZE_MASK) - MAX_DMA_CRC_LEN; 137 unsigned long flags; 138 139 spin_lock_irqsave(&priv->lock, flags); 140 if (ltq_etop_alloc_skb(ch)) { 141 netdev_err(ch->netdev, 142 "failed to allocate new rx buffer, stopping DMA\n"); 143 ltq_dma_close(&ch->dma); 144 } 145 ch->dma.desc++; 146 ch->dma.desc %= LTQ_DESC_NUM; 147 spin_unlock_irqrestore(&priv->lock, flags); 148 149 skb_put(skb, len); 150 skb->protocol = eth_type_trans(skb, ch->netdev); 151 netif_receive_skb(skb); 152 } 153 154 static int 155 ltq_etop_poll_rx(struct napi_struct *napi, int budget) 156 { 157 struct ltq_etop_chan *ch = container_of(napi, 158 struct ltq_etop_chan, napi); 159 int work_done = 0; 160 161 while (work_done < budget) { 162 struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->dma.desc]; 163 164 if ((desc->ctl & (LTQ_DMA_OWN | LTQ_DMA_C)) != LTQ_DMA_C) 165 break; 166 ltq_etop_hw_receive(ch); 167 work_done++; 168 } 169 if (work_done < budget) { 170 napi_complete_done(&ch->napi, work_done); 171 ltq_dma_ack_irq(&ch->dma); 172 } 173 return work_done; 174 } 175 176 static int 177 ltq_etop_poll_tx(struct napi_struct *napi, int budget) 178 { 179 struct ltq_etop_chan *ch = 180 container_of(napi, struct ltq_etop_chan, napi); 181 struct ltq_etop_priv *priv = netdev_priv(ch->netdev); 182 struct netdev_queue *txq = 183 netdev_get_tx_queue(ch->netdev, ch->idx >> 1); 184 unsigned long flags; 185 186 spin_lock_irqsave(&priv->lock, flags); 187 while ((ch->dma.desc_base[ch->tx_free].ctl & 188 (LTQ_DMA_OWN | LTQ_DMA_C)) == LTQ_DMA_C) { 189 dev_kfree_skb_any(ch->skb[ch->tx_free]); 190 ch->skb[ch->tx_free] = NULL; 191 memset(&ch->dma.desc_base[ch->tx_free], 0, 192 sizeof(struct ltq_dma_desc)); 193 ch->tx_free++; 194 ch->tx_free %= LTQ_DESC_NUM; 195 } 196 spin_unlock_irqrestore(&priv->lock, flags); 197 198 if (netif_tx_queue_stopped(txq)) 199 netif_tx_start_queue(txq); 200 napi_complete(&ch->napi); 201 ltq_dma_ack_irq(&ch->dma); 202 return 1; 203 } 204 205 static irqreturn_t 206 ltq_etop_dma_irq(int irq, void *_priv) 207 { 208 struct ltq_etop_priv *priv = _priv; 209 int ch = irq - LTQ_DMA_CH0_INT; 210 211 napi_schedule(&priv->ch[ch].napi); 212 return IRQ_HANDLED; 213 } 214 215 static void 216 ltq_etop_free_channel(struct net_device *dev, struct ltq_etop_chan *ch) 217 { 218 struct ltq_etop_priv *priv = netdev_priv(dev); 219 220 ltq_dma_free(&ch->dma); 221 if (ch->dma.irq) 222 free_irq(ch->dma.irq, priv); 223 if (IS_RX(ch->idx)) { 224 int desc; 225 for (desc = 0; desc < LTQ_DESC_NUM; desc++) 226 dev_kfree_skb_any(ch->skb[ch->dma.desc]); 227 } 228 } 229 230 static void 231 ltq_etop_hw_exit(struct net_device *dev) 232 { 233 struct ltq_etop_priv *priv = netdev_priv(dev); 234 int i; 235 236 ltq_pmu_disable(PMU_PPE); 237 for (i = 0; i < MAX_DMA_CHAN; i++) 238 if (IS_TX(i) || IS_RX(i)) 239 ltq_etop_free_channel(dev, &priv->ch[i]); 240 } 241 242 static int 243 ltq_etop_hw_init(struct net_device *dev) 244 { 245 struct ltq_etop_priv *priv = netdev_priv(dev); 246 int i; 247 248 ltq_pmu_enable(PMU_PPE); 249 250 switch (priv->pldata->mii_mode) { 251 case PHY_INTERFACE_MODE_RMII: 252 ltq_etop_w32_mask(ETOP_MII_MASK, 253 ETOP_MII_REVERSE, LTQ_ETOP_CFG); 254 break; 255 256 case PHY_INTERFACE_MODE_MII: 257 ltq_etop_w32_mask(ETOP_MII_MASK, 258 ETOP_MII_NORMAL, LTQ_ETOP_CFG); 259 break; 260 261 default: 262 netdev_err(dev, "unknown mii mode %d\n", 263 priv->pldata->mii_mode); 264 return -ENOTSUPP; 265 } 266 267 /* enable crc generation */ 268 ltq_etop_w32(PPE32_CGEN, LQ_PPE32_ENET_MAC_CFG); 269 270 ltq_dma_init_port(DMA_PORT_ETOP); 271 272 for (i = 0; i < MAX_DMA_CHAN; i++) { 273 int irq = LTQ_DMA_CH0_INT + i; 274 struct ltq_etop_chan *ch = &priv->ch[i]; 275 276 ch->idx = ch->dma.nr = i; 277 278 if (IS_TX(i)) { 279 ltq_dma_alloc_tx(&ch->dma); 280 request_irq(irq, ltq_etop_dma_irq, 0, "etop_tx", priv); 281 } else if (IS_RX(i)) { 282 ltq_dma_alloc_rx(&ch->dma); 283 for (ch->dma.desc = 0; ch->dma.desc < LTQ_DESC_NUM; 284 ch->dma.desc++) 285 if (ltq_etop_alloc_skb(ch)) 286 return -ENOMEM; 287 ch->dma.desc = 0; 288 request_irq(irq, ltq_etop_dma_irq, 0, "etop_rx", priv); 289 } 290 ch->dma.irq = irq; 291 } 292 return 0; 293 } 294 295 static void 296 ltq_etop_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info) 297 { 298 strlcpy(info->driver, "Lantiq ETOP", sizeof(info->driver)); 299 strlcpy(info->bus_info, "internal", sizeof(info->bus_info)); 300 strlcpy(info->version, DRV_VERSION, sizeof(info->version)); 301 } 302 303 static const struct ethtool_ops ltq_etop_ethtool_ops = { 304 .get_drvinfo = ltq_etop_get_drvinfo, 305 .nway_reset = phy_ethtool_nway_reset, 306 .get_link_ksettings = phy_ethtool_get_link_ksettings, 307 .set_link_ksettings = phy_ethtool_set_link_ksettings, 308 }; 309 310 static int 311 ltq_etop_mdio_wr(struct mii_bus *bus, int phy_addr, int phy_reg, u16 phy_data) 312 { 313 u32 val = MDIO_REQUEST | 314 ((phy_addr & MDIO_ADDR_MASK) << MDIO_ADDR_OFFSET) | 315 ((phy_reg & MDIO_REG_MASK) << MDIO_REG_OFFSET) | 316 phy_data; 317 318 while (ltq_etop_r32(LTQ_ETOP_MDIO) & MDIO_REQUEST) 319 ; 320 ltq_etop_w32(val, LTQ_ETOP_MDIO); 321 return 0; 322 } 323 324 static int 325 ltq_etop_mdio_rd(struct mii_bus *bus, int phy_addr, int phy_reg) 326 { 327 u32 val = MDIO_REQUEST | MDIO_READ | 328 ((phy_addr & MDIO_ADDR_MASK) << MDIO_ADDR_OFFSET) | 329 ((phy_reg & MDIO_REG_MASK) << MDIO_REG_OFFSET); 330 331 while (ltq_etop_r32(LTQ_ETOP_MDIO) & MDIO_REQUEST) 332 ; 333 ltq_etop_w32(val, LTQ_ETOP_MDIO); 334 while (ltq_etop_r32(LTQ_ETOP_MDIO) & MDIO_REQUEST) 335 ; 336 val = ltq_etop_r32(LTQ_ETOP_MDIO) & MDIO_VAL_MASK; 337 return val; 338 } 339 340 static void 341 ltq_etop_mdio_link(struct net_device *dev) 342 { 343 /* nothing to do */ 344 } 345 346 static int 347 ltq_etop_mdio_probe(struct net_device *dev) 348 { 349 struct ltq_etop_priv *priv = netdev_priv(dev); 350 struct phy_device *phydev; 351 352 phydev = phy_find_first(priv->mii_bus); 353 354 if (!phydev) { 355 netdev_err(dev, "no PHY found\n"); 356 return -ENODEV; 357 } 358 359 phydev = phy_connect(dev, phydev_name(phydev), 360 <q_etop_mdio_link, priv->pldata->mii_mode); 361 362 if (IS_ERR(phydev)) { 363 netdev_err(dev, "Could not attach to PHY\n"); 364 return PTR_ERR(phydev); 365 } 366 367 phydev->supported &= (SUPPORTED_10baseT_Half 368 | SUPPORTED_10baseT_Full 369 | SUPPORTED_100baseT_Half 370 | SUPPORTED_100baseT_Full 371 | SUPPORTED_Autoneg 372 | SUPPORTED_MII 373 | SUPPORTED_TP); 374 375 phydev->advertising = phydev->supported; 376 phy_attached_info(phydev); 377 378 return 0; 379 } 380 381 static int 382 ltq_etop_mdio_init(struct net_device *dev) 383 { 384 struct ltq_etop_priv *priv = netdev_priv(dev); 385 int err; 386 387 priv->mii_bus = mdiobus_alloc(); 388 if (!priv->mii_bus) { 389 netdev_err(dev, "failed to allocate mii bus\n"); 390 err = -ENOMEM; 391 goto err_out; 392 } 393 394 priv->mii_bus->priv = dev; 395 priv->mii_bus->read = ltq_etop_mdio_rd; 396 priv->mii_bus->write = ltq_etop_mdio_wr; 397 priv->mii_bus->name = "ltq_mii"; 398 snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x", 399 priv->pdev->name, priv->pdev->id); 400 if (mdiobus_register(priv->mii_bus)) { 401 err = -ENXIO; 402 goto err_out_free_mdiobus; 403 } 404 405 if (ltq_etop_mdio_probe(dev)) { 406 err = -ENXIO; 407 goto err_out_unregister_bus; 408 } 409 return 0; 410 411 err_out_unregister_bus: 412 mdiobus_unregister(priv->mii_bus); 413 err_out_free_mdiobus: 414 mdiobus_free(priv->mii_bus); 415 err_out: 416 return err; 417 } 418 419 static void 420 ltq_etop_mdio_cleanup(struct net_device *dev) 421 { 422 struct ltq_etop_priv *priv = netdev_priv(dev); 423 424 phy_disconnect(dev->phydev); 425 mdiobus_unregister(priv->mii_bus); 426 mdiobus_free(priv->mii_bus); 427 } 428 429 static int 430 ltq_etop_open(struct net_device *dev) 431 { 432 struct ltq_etop_priv *priv = netdev_priv(dev); 433 int i; 434 435 for (i = 0; i < MAX_DMA_CHAN; i++) { 436 struct ltq_etop_chan *ch = &priv->ch[i]; 437 438 if (!IS_TX(i) && (!IS_RX(i))) 439 continue; 440 ltq_dma_open(&ch->dma); 441 napi_enable(&ch->napi); 442 } 443 phy_start(dev->phydev); 444 netif_tx_start_all_queues(dev); 445 return 0; 446 } 447 448 static int 449 ltq_etop_stop(struct net_device *dev) 450 { 451 struct ltq_etop_priv *priv = netdev_priv(dev); 452 int i; 453 454 netif_tx_stop_all_queues(dev); 455 phy_stop(dev->phydev); 456 for (i = 0; i < MAX_DMA_CHAN; i++) { 457 struct ltq_etop_chan *ch = &priv->ch[i]; 458 459 if (!IS_RX(i) && !IS_TX(i)) 460 continue; 461 napi_disable(&ch->napi); 462 ltq_dma_close(&ch->dma); 463 } 464 return 0; 465 } 466 467 static int 468 ltq_etop_tx(struct sk_buff *skb, struct net_device *dev) 469 { 470 int queue = skb_get_queue_mapping(skb); 471 struct netdev_queue *txq = netdev_get_tx_queue(dev, queue); 472 struct ltq_etop_priv *priv = netdev_priv(dev); 473 struct ltq_etop_chan *ch = &priv->ch[(queue << 1) | 1]; 474 struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->dma.desc]; 475 int len; 476 unsigned long flags; 477 u32 byte_offset; 478 479 len = skb->len < ETH_ZLEN ? ETH_ZLEN : skb->len; 480 481 if ((desc->ctl & (LTQ_DMA_OWN | LTQ_DMA_C)) || ch->skb[ch->dma.desc]) { 482 dev_kfree_skb_any(skb); 483 netdev_err(dev, "tx ring full\n"); 484 netif_tx_stop_queue(txq); 485 return NETDEV_TX_BUSY; 486 } 487 488 /* dma needs to start on a 16 byte aligned address */ 489 byte_offset = CPHYSADDR(skb->data) % 16; 490 ch->skb[ch->dma.desc] = skb; 491 492 netif_trans_update(dev); 493 494 spin_lock_irqsave(&priv->lock, flags); 495 desc->addr = ((unsigned int) dma_map_single(NULL, skb->data, len, 496 DMA_TO_DEVICE)) - byte_offset; 497 wmb(); 498 desc->ctl = LTQ_DMA_OWN | LTQ_DMA_SOP | LTQ_DMA_EOP | 499 LTQ_DMA_TX_OFFSET(byte_offset) | (len & LTQ_DMA_SIZE_MASK); 500 ch->dma.desc++; 501 ch->dma.desc %= LTQ_DESC_NUM; 502 spin_unlock_irqrestore(&priv->lock, flags); 503 504 if (ch->dma.desc_base[ch->dma.desc].ctl & LTQ_DMA_OWN) 505 netif_tx_stop_queue(txq); 506 507 return NETDEV_TX_OK; 508 } 509 510 static int 511 ltq_etop_change_mtu(struct net_device *dev, int new_mtu) 512 { 513 struct ltq_etop_priv *priv = netdev_priv(dev); 514 unsigned long flags; 515 516 dev->mtu = new_mtu; 517 518 spin_lock_irqsave(&priv->lock, flags); 519 ltq_etop_w32((ETOP_PLEN_UNDER << 16) | new_mtu, LTQ_ETOP_IGPLEN); 520 spin_unlock_irqrestore(&priv->lock, flags); 521 522 return 0; 523 } 524 525 static int 526 ltq_etop_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) 527 { 528 /* TODO: mii-toll reports "No MII transceiver present!." ?!*/ 529 return phy_mii_ioctl(dev->phydev, rq, cmd); 530 } 531 532 static int 533 ltq_etop_set_mac_address(struct net_device *dev, void *p) 534 { 535 int ret = eth_mac_addr(dev, p); 536 537 if (!ret) { 538 struct ltq_etop_priv *priv = netdev_priv(dev); 539 unsigned long flags; 540 541 /* store the mac for the unicast filter */ 542 spin_lock_irqsave(&priv->lock, flags); 543 ltq_etop_w32(*((u32 *)dev->dev_addr), LTQ_ETOP_MAC_DA0); 544 ltq_etop_w32(*((u16 *)&dev->dev_addr[4]) << 16, 545 LTQ_ETOP_MAC_DA1); 546 spin_unlock_irqrestore(&priv->lock, flags); 547 } 548 return ret; 549 } 550 551 static void 552 ltq_etop_set_multicast_list(struct net_device *dev) 553 { 554 struct ltq_etop_priv *priv = netdev_priv(dev); 555 unsigned long flags; 556 557 /* ensure that the unicast filter is not enabled in promiscious mode */ 558 spin_lock_irqsave(&priv->lock, flags); 559 if ((dev->flags & IFF_PROMISC) || (dev->flags & IFF_ALLMULTI)) 560 ltq_etop_w32_mask(ETOP_FTCU, 0, LTQ_ETOP_ENETS0); 561 else 562 ltq_etop_w32_mask(0, ETOP_FTCU, LTQ_ETOP_ENETS0); 563 spin_unlock_irqrestore(&priv->lock, flags); 564 } 565 566 static u16 567 ltq_etop_select_queue(struct net_device *dev, struct sk_buff *skb, 568 void *accel_priv, select_queue_fallback_t fallback) 569 { 570 /* we are currently only using the first queue */ 571 return 0; 572 } 573 574 static int 575 ltq_etop_init(struct net_device *dev) 576 { 577 struct ltq_etop_priv *priv = netdev_priv(dev); 578 struct sockaddr mac; 579 int err; 580 bool random_mac = false; 581 582 dev->watchdog_timeo = 10 * HZ; 583 err = ltq_etop_hw_init(dev); 584 if (err) 585 goto err_hw; 586 ltq_etop_change_mtu(dev, 1500); 587 588 memcpy(&mac, &priv->pldata->mac, sizeof(struct sockaddr)); 589 if (!is_valid_ether_addr(mac.sa_data)) { 590 pr_warn("etop: invalid MAC, using random\n"); 591 eth_random_addr(mac.sa_data); 592 random_mac = true; 593 } 594 595 err = ltq_etop_set_mac_address(dev, &mac); 596 if (err) 597 goto err_netdev; 598 599 /* Set addr_assign_type here, ltq_etop_set_mac_address would reset it. */ 600 if (random_mac) 601 dev->addr_assign_type = NET_ADDR_RANDOM; 602 603 ltq_etop_set_multicast_list(dev); 604 err = ltq_etop_mdio_init(dev); 605 if (err) 606 goto err_netdev; 607 return 0; 608 609 err_netdev: 610 unregister_netdev(dev); 611 free_netdev(dev); 612 err_hw: 613 ltq_etop_hw_exit(dev); 614 return err; 615 } 616 617 static void 618 ltq_etop_tx_timeout(struct net_device *dev) 619 { 620 int err; 621 622 ltq_etop_hw_exit(dev); 623 err = ltq_etop_hw_init(dev); 624 if (err) 625 goto err_hw; 626 netif_trans_update(dev); 627 netif_wake_queue(dev); 628 return; 629 630 err_hw: 631 ltq_etop_hw_exit(dev); 632 netdev_err(dev, "failed to restart etop after TX timeout\n"); 633 } 634 635 static const struct net_device_ops ltq_eth_netdev_ops = { 636 .ndo_open = ltq_etop_open, 637 .ndo_stop = ltq_etop_stop, 638 .ndo_start_xmit = ltq_etop_tx, 639 .ndo_change_mtu = ltq_etop_change_mtu, 640 .ndo_do_ioctl = ltq_etop_ioctl, 641 .ndo_set_mac_address = ltq_etop_set_mac_address, 642 .ndo_validate_addr = eth_validate_addr, 643 .ndo_set_rx_mode = ltq_etop_set_multicast_list, 644 .ndo_select_queue = ltq_etop_select_queue, 645 .ndo_init = ltq_etop_init, 646 .ndo_tx_timeout = ltq_etop_tx_timeout, 647 }; 648 649 static int __init 650 ltq_etop_probe(struct platform_device *pdev) 651 { 652 struct net_device *dev; 653 struct ltq_etop_priv *priv; 654 struct resource *res; 655 int err; 656 int i; 657 658 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 659 if (!res) { 660 dev_err(&pdev->dev, "failed to get etop resource\n"); 661 err = -ENOENT; 662 goto err_out; 663 } 664 665 res = devm_request_mem_region(&pdev->dev, res->start, 666 resource_size(res), dev_name(&pdev->dev)); 667 if (!res) { 668 dev_err(&pdev->dev, "failed to request etop resource\n"); 669 err = -EBUSY; 670 goto err_out; 671 } 672 673 ltq_etop_membase = devm_ioremap_nocache(&pdev->dev, 674 res->start, resource_size(res)); 675 if (!ltq_etop_membase) { 676 dev_err(&pdev->dev, "failed to remap etop engine %d\n", 677 pdev->id); 678 err = -ENOMEM; 679 goto err_out; 680 } 681 682 dev = alloc_etherdev_mq(sizeof(struct ltq_etop_priv), 4); 683 if (!dev) { 684 err = -ENOMEM; 685 goto err_out; 686 } 687 strcpy(dev->name, "eth%d"); 688 dev->netdev_ops = <q_eth_netdev_ops; 689 dev->ethtool_ops = <q_etop_ethtool_ops; 690 priv = netdev_priv(dev); 691 priv->res = res; 692 priv->pdev = pdev; 693 priv->pldata = dev_get_platdata(&pdev->dev); 694 priv->netdev = dev; 695 spin_lock_init(&priv->lock); 696 SET_NETDEV_DEV(dev, &pdev->dev); 697 698 for (i = 0; i < MAX_DMA_CHAN; i++) { 699 if (IS_TX(i)) 700 netif_napi_add(dev, &priv->ch[i].napi, 701 ltq_etop_poll_tx, 8); 702 else if (IS_RX(i)) 703 netif_napi_add(dev, &priv->ch[i].napi, 704 ltq_etop_poll_rx, 32); 705 priv->ch[i].netdev = dev; 706 } 707 708 err = register_netdev(dev); 709 if (err) 710 goto err_free; 711 712 platform_set_drvdata(pdev, dev); 713 return 0; 714 715 err_free: 716 free_netdev(dev); 717 err_out: 718 return err; 719 } 720 721 static int 722 ltq_etop_remove(struct platform_device *pdev) 723 { 724 struct net_device *dev = platform_get_drvdata(pdev); 725 726 if (dev) { 727 netif_tx_stop_all_queues(dev); 728 ltq_etop_hw_exit(dev); 729 ltq_etop_mdio_cleanup(dev); 730 unregister_netdev(dev); 731 } 732 return 0; 733 } 734 735 static struct platform_driver ltq_mii_driver = { 736 .remove = ltq_etop_remove, 737 .driver = { 738 .name = "ltq_etop", 739 }, 740 }; 741 742 int __init 743 init_ltq_etop(void) 744 { 745 int ret = platform_driver_probe(<q_mii_driver, ltq_etop_probe); 746 747 if (ret) 748 pr_err("ltq_etop: Error registering platform driver!"); 749 return ret; 750 } 751 752 static void __exit 753 exit_ltq_etop(void) 754 { 755 platform_driver_unregister(<q_mii_driver); 756 } 757 758 module_init(init_ltq_etop); 759 module_exit(exit_ltq_etop); 760 761 MODULE_AUTHOR("John Crispin <blogic@openwrt.org>"); 762 MODULE_DESCRIPTION("Lantiq SoC ETOP"); 763 MODULE_LICENSE("GPL"); 764