1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * 4 * Copyright (C) 2011 John Crispin <blogic@openwrt.org> 5 */ 6 7 #include <linux/kernel.h> 8 #include <linux/slab.h> 9 #include <linux/errno.h> 10 #include <linux/types.h> 11 #include <linux/interrupt.h> 12 #include <linux/uaccess.h> 13 #include <linux/in.h> 14 #include <linux/netdevice.h> 15 #include <linux/etherdevice.h> 16 #include <linux/phy.h> 17 #include <linux/ip.h> 18 #include <linux/tcp.h> 19 #include <linux/skbuff.h> 20 #include <linux/mm.h> 21 #include <linux/platform_device.h> 22 #include <linux/ethtool.h> 23 #include <linux/init.h> 24 #include <linux/delay.h> 25 #include <linux/io.h> 26 #include <linux/dma-mapping.h> 27 #include <linux/module.h> 28 #include <linux/property.h> 29 30 #include <asm/checksum.h> 31 32 #include <lantiq_soc.h> 33 #include <xway_dma.h> 34 #include <lantiq_platform.h> 35 36 #define LTQ_ETOP_MDIO 0x11804 37 #define MDIO_REQUEST 0x80000000 38 #define MDIO_READ 0x40000000 39 #define MDIO_ADDR_MASK 0x1f 40 #define MDIO_ADDR_OFFSET 0x15 41 #define MDIO_REG_MASK 0x1f 42 #define MDIO_REG_OFFSET 0x10 43 #define MDIO_VAL_MASK 0xffff 44 45 #define PPE32_CGEN 0x800 46 #define LQ_PPE32_ENET_MAC_CFG 0x1840 47 48 #define LTQ_ETOP_ENETS0 0x11850 49 #define LTQ_ETOP_MAC_DA0 0x1186C 50 #define LTQ_ETOP_MAC_DA1 0x11870 51 #define LTQ_ETOP_CFG 0x16020 52 #define LTQ_ETOP_IGPLEN 0x16080 53 54 #define MAX_DMA_CHAN 0x8 55 #define MAX_DMA_CRC_LEN 0x4 56 #define MAX_DMA_DATA_LEN 0x600 57 58 #define ETOP_FTCU BIT(28) 59 #define ETOP_MII_MASK 0xf 60 #define ETOP_MII_NORMAL 0xd 61 #define ETOP_MII_REVERSE 0xe 62 #define ETOP_PLEN_UNDER 0x40 63 #define ETOP_CGEN 0x800 64 65 /* use 2 static channels for TX/RX */ 66 #define LTQ_ETOP_TX_CHANNEL 1 67 #define LTQ_ETOP_RX_CHANNEL 6 68 #define IS_TX(x) (x == LTQ_ETOP_TX_CHANNEL) 69 #define IS_RX(x) (x == LTQ_ETOP_RX_CHANNEL) 70 71 #define ltq_etop_r32(x) ltq_r32(ltq_etop_membase + (x)) 72 #define ltq_etop_w32(x, y) ltq_w32(x, ltq_etop_membase + (y)) 73 #define ltq_etop_w32_mask(x, y, z) \ 74 ltq_w32_mask(x, y, ltq_etop_membase + (z)) 75 76 #define DRV_VERSION "1.0" 77 78 static void __iomem *ltq_etop_membase; 79 80 struct ltq_etop_chan { 81 int idx; 82 int tx_free; 83 struct net_device *netdev; 84 struct napi_struct napi; 85 struct ltq_dma_channel dma; 86 struct sk_buff *skb[LTQ_DESC_NUM]; 87 }; 88 89 struct ltq_etop_priv { 90 struct net_device *netdev; 91 struct platform_device *pdev; 92 struct ltq_eth_data *pldata; 93 struct resource *res; 94 95 struct mii_bus *mii_bus; 96 97 struct ltq_etop_chan ch[MAX_DMA_CHAN]; 98 int tx_free[MAX_DMA_CHAN >> 1]; 99 100 int tx_burst_len; 101 int rx_burst_len; 102 103 spinlock_t lock; 104 }; 105 106 static int 107 ltq_etop_alloc_skb(struct ltq_etop_chan *ch) 108 { 109 struct ltq_etop_priv *priv = netdev_priv(ch->netdev); 110 111 ch->skb[ch->dma.desc] = netdev_alloc_skb(ch->netdev, MAX_DMA_DATA_LEN); 112 if (!ch->skb[ch->dma.desc]) 113 return -ENOMEM; 114 ch->dma.desc_base[ch->dma.desc].addr = dma_map_single(&priv->pdev->dev, 115 ch->skb[ch->dma.desc]->data, MAX_DMA_DATA_LEN, 116 DMA_FROM_DEVICE); 117 ch->dma.desc_base[ch->dma.desc].addr = 118 CPHYSADDR(ch->skb[ch->dma.desc]->data); 119 ch->dma.desc_base[ch->dma.desc].ctl = 120 LTQ_DMA_OWN | LTQ_DMA_RX_OFFSET(NET_IP_ALIGN) | 121 MAX_DMA_DATA_LEN; 122 skb_reserve(ch->skb[ch->dma.desc], NET_IP_ALIGN); 123 return 0; 124 } 125 126 static void 127 ltq_etop_hw_receive(struct ltq_etop_chan *ch) 128 { 129 struct ltq_etop_priv *priv = netdev_priv(ch->netdev); 130 struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->dma.desc]; 131 struct sk_buff *skb = ch->skb[ch->dma.desc]; 132 int len = (desc->ctl & LTQ_DMA_SIZE_MASK) - MAX_DMA_CRC_LEN; 133 unsigned long flags; 134 135 spin_lock_irqsave(&priv->lock, flags); 136 if (ltq_etop_alloc_skb(ch)) { 137 netdev_err(ch->netdev, 138 "failed to allocate new rx buffer, stopping DMA\n"); 139 ltq_dma_close(&ch->dma); 140 } 141 ch->dma.desc++; 142 ch->dma.desc %= LTQ_DESC_NUM; 143 spin_unlock_irqrestore(&priv->lock, flags); 144 145 skb_put(skb, len); 146 skb->protocol = eth_type_trans(skb, ch->netdev); 147 netif_receive_skb(skb); 148 } 149 150 static int 151 ltq_etop_poll_rx(struct napi_struct *napi, int budget) 152 { 153 struct ltq_etop_chan *ch = container_of(napi, 154 struct ltq_etop_chan, napi); 155 int work_done = 0; 156 157 while (work_done < budget) { 158 struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->dma.desc]; 159 160 if ((desc->ctl & (LTQ_DMA_OWN | LTQ_DMA_C)) != LTQ_DMA_C) 161 break; 162 ltq_etop_hw_receive(ch); 163 work_done++; 164 } 165 if (work_done < budget) { 166 napi_complete_done(&ch->napi, work_done); 167 ltq_dma_ack_irq(&ch->dma); 168 } 169 return work_done; 170 } 171 172 static int 173 ltq_etop_poll_tx(struct napi_struct *napi, int budget) 174 { 175 struct ltq_etop_chan *ch = 176 container_of(napi, struct ltq_etop_chan, napi); 177 struct ltq_etop_priv *priv = netdev_priv(ch->netdev); 178 struct netdev_queue *txq = 179 netdev_get_tx_queue(ch->netdev, ch->idx >> 1); 180 unsigned long flags; 181 182 spin_lock_irqsave(&priv->lock, flags); 183 while ((ch->dma.desc_base[ch->tx_free].ctl & 184 (LTQ_DMA_OWN | LTQ_DMA_C)) == LTQ_DMA_C) { 185 dev_kfree_skb_any(ch->skb[ch->tx_free]); 186 ch->skb[ch->tx_free] = NULL; 187 memset(&ch->dma.desc_base[ch->tx_free], 0, 188 sizeof(struct ltq_dma_desc)); 189 ch->tx_free++; 190 ch->tx_free %= LTQ_DESC_NUM; 191 } 192 spin_unlock_irqrestore(&priv->lock, flags); 193 194 if (netif_tx_queue_stopped(txq)) 195 netif_tx_start_queue(txq); 196 napi_complete(&ch->napi); 197 ltq_dma_ack_irq(&ch->dma); 198 return 1; 199 } 200 201 static irqreturn_t 202 ltq_etop_dma_irq(int irq, void *_priv) 203 { 204 struct ltq_etop_priv *priv = _priv; 205 int ch = irq - LTQ_DMA_CH0_INT; 206 207 napi_schedule(&priv->ch[ch].napi); 208 return IRQ_HANDLED; 209 } 210 211 static void 212 ltq_etop_free_channel(struct net_device *dev, struct ltq_etop_chan *ch) 213 { 214 struct ltq_etop_priv *priv = netdev_priv(dev); 215 216 ltq_dma_free(&ch->dma); 217 if (ch->dma.irq) 218 free_irq(ch->dma.irq, priv); 219 if (IS_RX(ch->idx)) { 220 int desc; 221 for (desc = 0; desc < LTQ_DESC_NUM; desc++) 222 dev_kfree_skb_any(ch->skb[ch->dma.desc]); 223 } 224 } 225 226 static void 227 ltq_etop_hw_exit(struct net_device *dev) 228 { 229 struct ltq_etop_priv *priv = netdev_priv(dev); 230 int i; 231 232 ltq_pmu_disable(PMU_PPE); 233 for (i = 0; i < MAX_DMA_CHAN; i++) 234 if (IS_TX(i) || IS_RX(i)) 235 ltq_etop_free_channel(dev, &priv->ch[i]); 236 } 237 238 static int 239 ltq_etop_hw_init(struct net_device *dev) 240 { 241 struct ltq_etop_priv *priv = netdev_priv(dev); 242 int i; 243 int err; 244 245 ltq_pmu_enable(PMU_PPE); 246 247 switch (priv->pldata->mii_mode) { 248 case PHY_INTERFACE_MODE_RMII: 249 ltq_etop_w32_mask(ETOP_MII_MASK, 250 ETOP_MII_REVERSE, LTQ_ETOP_CFG); 251 break; 252 253 case PHY_INTERFACE_MODE_MII: 254 ltq_etop_w32_mask(ETOP_MII_MASK, 255 ETOP_MII_NORMAL, LTQ_ETOP_CFG); 256 break; 257 258 default: 259 netdev_err(dev, "unknown mii mode %d\n", 260 priv->pldata->mii_mode); 261 return -ENOTSUPP; 262 } 263 264 /* enable crc generation */ 265 ltq_etop_w32(PPE32_CGEN, LQ_PPE32_ENET_MAC_CFG); 266 267 ltq_dma_init_port(DMA_PORT_ETOP, priv->tx_burst_len, priv->rx_burst_len); 268 269 for (i = 0; i < MAX_DMA_CHAN; i++) { 270 int irq = LTQ_DMA_CH0_INT + i; 271 struct ltq_etop_chan *ch = &priv->ch[i]; 272 273 ch->idx = ch->dma.nr = i; 274 ch->dma.dev = &priv->pdev->dev; 275 276 if (IS_TX(i)) { 277 ltq_dma_alloc_tx(&ch->dma); 278 err = request_irq(irq, ltq_etop_dma_irq, 0, "etop_tx", priv); 279 if (err) { 280 netdev_err(dev, 281 "Unable to get Tx DMA IRQ %d\n", 282 irq); 283 return err; 284 } 285 } else if (IS_RX(i)) { 286 ltq_dma_alloc_rx(&ch->dma); 287 for (ch->dma.desc = 0; ch->dma.desc < LTQ_DESC_NUM; 288 ch->dma.desc++) 289 if (ltq_etop_alloc_skb(ch)) 290 return -ENOMEM; 291 ch->dma.desc = 0; 292 err = request_irq(irq, ltq_etop_dma_irq, 0, "etop_rx", priv); 293 if (err) { 294 netdev_err(dev, 295 "Unable to get Rx DMA IRQ %d\n", 296 irq); 297 return err; 298 } 299 } 300 ch->dma.irq = irq; 301 } 302 return 0; 303 } 304 305 static void 306 ltq_etop_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info) 307 { 308 strlcpy(info->driver, "Lantiq ETOP", sizeof(info->driver)); 309 strlcpy(info->bus_info, "internal", sizeof(info->bus_info)); 310 strlcpy(info->version, DRV_VERSION, sizeof(info->version)); 311 } 312 313 static const struct ethtool_ops ltq_etop_ethtool_ops = { 314 .get_drvinfo = ltq_etop_get_drvinfo, 315 .nway_reset = phy_ethtool_nway_reset, 316 .get_link_ksettings = phy_ethtool_get_link_ksettings, 317 .set_link_ksettings = phy_ethtool_set_link_ksettings, 318 }; 319 320 static int 321 ltq_etop_mdio_wr(struct mii_bus *bus, int phy_addr, int phy_reg, u16 phy_data) 322 { 323 u32 val = MDIO_REQUEST | 324 ((phy_addr & MDIO_ADDR_MASK) << MDIO_ADDR_OFFSET) | 325 ((phy_reg & MDIO_REG_MASK) << MDIO_REG_OFFSET) | 326 phy_data; 327 328 while (ltq_etop_r32(LTQ_ETOP_MDIO) & MDIO_REQUEST) 329 ; 330 ltq_etop_w32(val, LTQ_ETOP_MDIO); 331 return 0; 332 } 333 334 static int 335 ltq_etop_mdio_rd(struct mii_bus *bus, int phy_addr, int phy_reg) 336 { 337 u32 val = MDIO_REQUEST | MDIO_READ | 338 ((phy_addr & MDIO_ADDR_MASK) << MDIO_ADDR_OFFSET) | 339 ((phy_reg & MDIO_REG_MASK) << MDIO_REG_OFFSET); 340 341 while (ltq_etop_r32(LTQ_ETOP_MDIO) & MDIO_REQUEST) 342 ; 343 ltq_etop_w32(val, LTQ_ETOP_MDIO); 344 while (ltq_etop_r32(LTQ_ETOP_MDIO) & MDIO_REQUEST) 345 ; 346 val = ltq_etop_r32(LTQ_ETOP_MDIO) & MDIO_VAL_MASK; 347 return val; 348 } 349 350 static void 351 ltq_etop_mdio_link(struct net_device *dev) 352 { 353 /* nothing to do */ 354 } 355 356 static int 357 ltq_etop_mdio_probe(struct net_device *dev) 358 { 359 struct ltq_etop_priv *priv = netdev_priv(dev); 360 struct phy_device *phydev; 361 362 phydev = phy_find_first(priv->mii_bus); 363 364 if (!phydev) { 365 netdev_err(dev, "no PHY found\n"); 366 return -ENODEV; 367 } 368 369 phydev = phy_connect(dev, phydev_name(phydev), 370 <q_etop_mdio_link, priv->pldata->mii_mode); 371 372 if (IS_ERR(phydev)) { 373 netdev_err(dev, "Could not attach to PHY\n"); 374 return PTR_ERR(phydev); 375 } 376 377 phy_set_max_speed(phydev, SPEED_100); 378 379 phy_attached_info(phydev); 380 381 return 0; 382 } 383 384 static int 385 ltq_etop_mdio_init(struct net_device *dev) 386 { 387 struct ltq_etop_priv *priv = netdev_priv(dev); 388 int err; 389 390 priv->mii_bus = mdiobus_alloc(); 391 if (!priv->mii_bus) { 392 netdev_err(dev, "failed to allocate mii bus\n"); 393 err = -ENOMEM; 394 goto err_out; 395 } 396 397 priv->mii_bus->priv = dev; 398 priv->mii_bus->read = ltq_etop_mdio_rd; 399 priv->mii_bus->write = ltq_etop_mdio_wr; 400 priv->mii_bus->name = "ltq_mii"; 401 snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x", 402 priv->pdev->name, priv->pdev->id); 403 if (mdiobus_register(priv->mii_bus)) { 404 err = -ENXIO; 405 goto err_out_free_mdiobus; 406 } 407 408 if (ltq_etop_mdio_probe(dev)) { 409 err = -ENXIO; 410 goto err_out_unregister_bus; 411 } 412 return 0; 413 414 err_out_unregister_bus: 415 mdiobus_unregister(priv->mii_bus); 416 err_out_free_mdiobus: 417 mdiobus_free(priv->mii_bus); 418 err_out: 419 return err; 420 } 421 422 static void 423 ltq_etop_mdio_cleanup(struct net_device *dev) 424 { 425 struct ltq_etop_priv *priv = netdev_priv(dev); 426 427 phy_disconnect(dev->phydev); 428 mdiobus_unregister(priv->mii_bus); 429 mdiobus_free(priv->mii_bus); 430 } 431 432 static int 433 ltq_etop_open(struct net_device *dev) 434 { 435 struct ltq_etop_priv *priv = netdev_priv(dev); 436 int i; 437 438 for (i = 0; i < MAX_DMA_CHAN; i++) { 439 struct ltq_etop_chan *ch = &priv->ch[i]; 440 441 if (!IS_TX(i) && (!IS_RX(i))) 442 continue; 443 ltq_dma_open(&ch->dma); 444 ltq_dma_enable_irq(&ch->dma); 445 napi_enable(&ch->napi); 446 } 447 phy_start(dev->phydev); 448 netif_tx_start_all_queues(dev); 449 return 0; 450 } 451 452 static int 453 ltq_etop_stop(struct net_device *dev) 454 { 455 struct ltq_etop_priv *priv = netdev_priv(dev); 456 int i; 457 458 netif_tx_stop_all_queues(dev); 459 phy_stop(dev->phydev); 460 for (i = 0; i < MAX_DMA_CHAN; i++) { 461 struct ltq_etop_chan *ch = &priv->ch[i]; 462 463 if (!IS_RX(i) && !IS_TX(i)) 464 continue; 465 napi_disable(&ch->napi); 466 ltq_dma_close(&ch->dma); 467 } 468 return 0; 469 } 470 471 static int 472 ltq_etop_tx(struct sk_buff *skb, struct net_device *dev) 473 { 474 int queue = skb_get_queue_mapping(skb); 475 struct netdev_queue *txq = netdev_get_tx_queue(dev, queue); 476 struct ltq_etop_priv *priv = netdev_priv(dev); 477 struct ltq_etop_chan *ch = &priv->ch[(queue << 1) | 1]; 478 struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->dma.desc]; 479 int len; 480 unsigned long flags; 481 u32 byte_offset; 482 483 len = skb->len < ETH_ZLEN ? ETH_ZLEN : skb->len; 484 485 if ((desc->ctl & (LTQ_DMA_OWN | LTQ_DMA_C)) || ch->skb[ch->dma.desc]) { 486 dev_kfree_skb_any(skb); 487 netdev_err(dev, "tx ring full\n"); 488 netif_tx_stop_queue(txq); 489 return NETDEV_TX_BUSY; 490 } 491 492 /* dma needs to start on a burst length value aligned address */ 493 byte_offset = CPHYSADDR(skb->data) % (priv->tx_burst_len * 4); 494 ch->skb[ch->dma.desc] = skb; 495 496 netif_trans_update(dev); 497 498 spin_lock_irqsave(&priv->lock, flags); 499 desc->addr = ((unsigned int) dma_map_single(&priv->pdev->dev, skb->data, len, 500 DMA_TO_DEVICE)) - byte_offset; 501 wmb(); 502 desc->ctl = LTQ_DMA_OWN | LTQ_DMA_SOP | LTQ_DMA_EOP | 503 LTQ_DMA_TX_OFFSET(byte_offset) | (len & LTQ_DMA_SIZE_MASK); 504 ch->dma.desc++; 505 ch->dma.desc %= LTQ_DESC_NUM; 506 spin_unlock_irqrestore(&priv->lock, flags); 507 508 if (ch->dma.desc_base[ch->dma.desc].ctl & LTQ_DMA_OWN) 509 netif_tx_stop_queue(txq); 510 511 return NETDEV_TX_OK; 512 } 513 514 static int 515 ltq_etop_change_mtu(struct net_device *dev, int new_mtu) 516 { 517 struct ltq_etop_priv *priv = netdev_priv(dev); 518 unsigned long flags; 519 520 dev->mtu = new_mtu; 521 522 spin_lock_irqsave(&priv->lock, flags); 523 ltq_etop_w32((ETOP_PLEN_UNDER << 16) | new_mtu, LTQ_ETOP_IGPLEN); 524 spin_unlock_irqrestore(&priv->lock, flags); 525 526 return 0; 527 } 528 529 static int 530 ltq_etop_set_mac_address(struct net_device *dev, void *p) 531 { 532 int ret = eth_mac_addr(dev, p); 533 534 if (!ret) { 535 struct ltq_etop_priv *priv = netdev_priv(dev); 536 unsigned long flags; 537 538 /* store the mac for the unicast filter */ 539 spin_lock_irqsave(&priv->lock, flags); 540 ltq_etop_w32(*((u32 *)dev->dev_addr), LTQ_ETOP_MAC_DA0); 541 ltq_etop_w32(*((u16 *)&dev->dev_addr[4]) << 16, 542 LTQ_ETOP_MAC_DA1); 543 spin_unlock_irqrestore(&priv->lock, flags); 544 } 545 return ret; 546 } 547 548 static void 549 ltq_etop_set_multicast_list(struct net_device *dev) 550 { 551 struct ltq_etop_priv *priv = netdev_priv(dev); 552 unsigned long flags; 553 554 /* ensure that the unicast filter is not enabled in promiscious mode */ 555 spin_lock_irqsave(&priv->lock, flags); 556 if ((dev->flags & IFF_PROMISC) || (dev->flags & IFF_ALLMULTI)) 557 ltq_etop_w32_mask(ETOP_FTCU, 0, LTQ_ETOP_ENETS0); 558 else 559 ltq_etop_w32_mask(0, ETOP_FTCU, LTQ_ETOP_ENETS0); 560 spin_unlock_irqrestore(&priv->lock, flags); 561 } 562 563 static int 564 ltq_etop_init(struct net_device *dev) 565 { 566 struct ltq_etop_priv *priv = netdev_priv(dev); 567 struct sockaddr mac; 568 int err; 569 bool random_mac = false; 570 571 dev->watchdog_timeo = 10 * HZ; 572 err = ltq_etop_hw_init(dev); 573 if (err) 574 goto err_hw; 575 ltq_etop_change_mtu(dev, 1500); 576 577 memcpy(&mac, &priv->pldata->mac, sizeof(struct sockaddr)); 578 if (!is_valid_ether_addr(mac.sa_data)) { 579 pr_warn("etop: invalid MAC, using random\n"); 580 eth_random_addr(mac.sa_data); 581 random_mac = true; 582 } 583 584 err = ltq_etop_set_mac_address(dev, &mac); 585 if (err) 586 goto err_netdev; 587 588 /* Set addr_assign_type here, ltq_etop_set_mac_address would reset it. */ 589 if (random_mac) 590 dev->addr_assign_type = NET_ADDR_RANDOM; 591 592 ltq_etop_set_multicast_list(dev); 593 err = ltq_etop_mdio_init(dev); 594 if (err) 595 goto err_netdev; 596 return 0; 597 598 err_netdev: 599 unregister_netdev(dev); 600 free_netdev(dev); 601 err_hw: 602 ltq_etop_hw_exit(dev); 603 return err; 604 } 605 606 static void 607 ltq_etop_tx_timeout(struct net_device *dev, unsigned int txqueue) 608 { 609 int err; 610 611 ltq_etop_hw_exit(dev); 612 err = ltq_etop_hw_init(dev); 613 if (err) 614 goto err_hw; 615 netif_trans_update(dev); 616 netif_wake_queue(dev); 617 return; 618 619 err_hw: 620 ltq_etop_hw_exit(dev); 621 netdev_err(dev, "failed to restart etop after TX timeout\n"); 622 } 623 624 static const struct net_device_ops ltq_eth_netdev_ops = { 625 .ndo_open = ltq_etop_open, 626 .ndo_stop = ltq_etop_stop, 627 .ndo_start_xmit = ltq_etop_tx, 628 .ndo_change_mtu = ltq_etop_change_mtu, 629 .ndo_eth_ioctl = phy_do_ioctl, 630 .ndo_set_mac_address = ltq_etop_set_mac_address, 631 .ndo_validate_addr = eth_validate_addr, 632 .ndo_set_rx_mode = ltq_etop_set_multicast_list, 633 .ndo_select_queue = dev_pick_tx_zero, 634 .ndo_init = ltq_etop_init, 635 .ndo_tx_timeout = ltq_etop_tx_timeout, 636 }; 637 638 static int __init 639 ltq_etop_probe(struct platform_device *pdev) 640 { 641 struct net_device *dev; 642 struct ltq_etop_priv *priv; 643 struct resource *res; 644 int err; 645 int i; 646 647 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 648 if (!res) { 649 dev_err(&pdev->dev, "failed to get etop resource\n"); 650 err = -ENOENT; 651 goto err_out; 652 } 653 654 res = devm_request_mem_region(&pdev->dev, res->start, 655 resource_size(res), dev_name(&pdev->dev)); 656 if (!res) { 657 dev_err(&pdev->dev, "failed to request etop resource\n"); 658 err = -EBUSY; 659 goto err_out; 660 } 661 662 ltq_etop_membase = devm_ioremap(&pdev->dev, 663 res->start, resource_size(res)); 664 if (!ltq_etop_membase) { 665 dev_err(&pdev->dev, "failed to remap etop engine %d\n", 666 pdev->id); 667 err = -ENOMEM; 668 goto err_out; 669 } 670 671 dev = alloc_etherdev_mq(sizeof(struct ltq_etop_priv), 4); 672 if (!dev) { 673 err = -ENOMEM; 674 goto err_out; 675 } 676 strcpy(dev->name, "eth%d"); 677 dev->netdev_ops = <q_eth_netdev_ops; 678 dev->ethtool_ops = <q_etop_ethtool_ops; 679 priv = netdev_priv(dev); 680 priv->res = res; 681 priv->pdev = pdev; 682 priv->pldata = dev_get_platdata(&pdev->dev); 683 priv->netdev = dev; 684 spin_lock_init(&priv->lock); 685 SET_NETDEV_DEV(dev, &pdev->dev); 686 687 err = device_property_read_u32(&pdev->dev, "lantiq,tx-burst-length", &priv->tx_burst_len); 688 if (err < 0) { 689 dev_err(&pdev->dev, "unable to read tx-burst-length property\n"); 690 return err; 691 } 692 693 err = device_property_read_u32(&pdev->dev, "lantiq,rx-burst-length", &priv->rx_burst_len); 694 if (err < 0) { 695 dev_err(&pdev->dev, "unable to read rx-burst-length property\n"); 696 return err; 697 } 698 699 for (i = 0; i < MAX_DMA_CHAN; i++) { 700 if (IS_TX(i)) 701 netif_napi_add(dev, &priv->ch[i].napi, 702 ltq_etop_poll_tx, 8); 703 else if (IS_RX(i)) 704 netif_napi_add(dev, &priv->ch[i].napi, 705 ltq_etop_poll_rx, 32); 706 priv->ch[i].netdev = dev; 707 } 708 709 err = register_netdev(dev); 710 if (err) 711 goto err_free; 712 713 platform_set_drvdata(pdev, dev); 714 return 0; 715 716 err_free: 717 free_netdev(dev); 718 err_out: 719 return err; 720 } 721 722 static int 723 ltq_etop_remove(struct platform_device *pdev) 724 { 725 struct net_device *dev = platform_get_drvdata(pdev); 726 727 if (dev) { 728 netif_tx_stop_all_queues(dev); 729 ltq_etop_hw_exit(dev); 730 ltq_etop_mdio_cleanup(dev); 731 unregister_netdev(dev); 732 } 733 return 0; 734 } 735 736 static struct platform_driver ltq_mii_driver = { 737 .remove = ltq_etop_remove, 738 .driver = { 739 .name = "ltq_etop", 740 }, 741 }; 742 743 static int __init 744 init_ltq_etop(void) 745 { 746 int ret = platform_driver_probe(<q_mii_driver, ltq_etop_probe); 747 748 if (ret) 749 pr_err("ltq_etop: Error registering platform driver!"); 750 return ret; 751 } 752 753 static void __exit 754 exit_ltq_etop(void) 755 { 756 platform_driver_unregister(<q_mii_driver); 757 } 758 759 module_init(init_ltq_etop); 760 module_exit(exit_ltq_etop); 761 762 MODULE_AUTHOR("John Crispin <blogic@openwrt.org>"); 763 MODULE_DESCRIPTION("Lantiq SoC ETOP"); 764 MODULE_LICENSE("GPL"); 765