1 /* 2 * Driver for the IDT RC32434 (Korina) on-chip ethernet controller. 3 * 4 * Copyright 2004 IDT Inc. (rischelp@idt.com) 5 * Copyright 2006 Felix Fietkau <nbd@openwrt.org> 6 * Copyright 2008 Florian Fainelli <florian@openwrt.org> 7 * 8 * This program is free software; you can redistribute it and/or modify it 9 * under the terms of the GNU General Public License as published by the 10 * Free Software Foundation; either version 2 of the License, or (at your 11 * option) any later version. 12 * 13 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED 14 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 15 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN 16 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 17 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 18 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF 19 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON 20 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 21 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 22 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 23 * 24 * You should have received a copy of the GNU General Public License along 25 * with this program; if not, write to the Free Software Foundation, Inc., 26 * 675 Mass Ave, Cambridge, MA 02139, USA. 27 * 28 * Writing to a DMA status register: 29 * 30 * When writing to the status register, you should mask the bit you have 31 * been testing the status register with. Both Tx and Rx DMA registers 32 * should stick to this procedure. 33 */ 34 35 #include <linux/module.h> 36 #include <linux/kernel.h> 37 #include <linux/moduleparam.h> 38 #include <linux/sched.h> 39 #include <linux/ctype.h> 40 #include <linux/types.h> 41 #include <linux/interrupt.h> 42 #include <linux/init.h> 43 #include <linux/ioport.h> 44 #include <linux/in.h> 45 #include <linux/slab.h> 46 #include <linux/string.h> 47 #include <linux/delay.h> 48 #include <linux/netdevice.h> 49 #include <linux/etherdevice.h> 50 #include <linux/skbuff.h> 51 #include <linux/errno.h> 52 #include <linux/platform_device.h> 53 #include <linux/mii.h> 54 #include <linux/ethtool.h> 55 #include <linux/crc32.h> 56 57 #include <asm/bootinfo.h> 58 #include <asm/system.h> 59 #include <asm/bitops.h> 60 #include <asm/pgtable.h> 61 #include <asm/io.h> 62 #include <asm/dma.h> 63 64 #include <asm/mach-rc32434/rb.h> 65 #include <asm/mach-rc32434/rc32434.h> 66 #include <asm/mach-rc32434/eth.h> 67 #include <asm/mach-rc32434/dma_v.h> 68 69 #define DRV_NAME "korina" 70 #define DRV_VERSION "0.10" 71 #define DRV_RELDATE "04Mar2008" 72 73 #define STATION_ADDRESS_HIGH(dev) (((dev)->dev_addr[0] << 8) | \ 74 ((dev)->dev_addr[1])) 75 #define STATION_ADDRESS_LOW(dev) (((dev)->dev_addr[2] << 24) | \ 76 ((dev)->dev_addr[3] << 16) | \ 77 ((dev)->dev_addr[4] << 8) | \ 78 ((dev)->dev_addr[5])) 79 80 #define MII_CLOCK 1250000 /* no more than 2.5MHz */ 81 82 /* the following must be powers of two */ 83 #define KORINA_NUM_RDS 64 /* number of receive descriptors */ 84 #define KORINA_NUM_TDS 64 /* number of transmit descriptors */ 85 86 /* KORINA_RBSIZE is the hardware's default maximum receive 87 * frame size in bytes. Having this hardcoded means that there 88 * is no support for MTU sizes greater than 1500. */ 89 #define KORINA_RBSIZE 1536 /* size of one resource buffer = Ether MTU */ 90 #define KORINA_RDS_MASK (KORINA_NUM_RDS - 1) 91 #define KORINA_TDS_MASK (KORINA_NUM_TDS - 1) 92 #define RD_RING_SIZE (KORINA_NUM_RDS * sizeof(struct dma_desc)) 93 #define TD_RING_SIZE (KORINA_NUM_TDS * sizeof(struct dma_desc)) 94 95 #define TX_TIMEOUT (6000 * HZ / 1000) 96 97 enum chain_status { desc_filled, desc_empty }; 98 #define IS_DMA_FINISHED(X) (((X) & (DMA_DESC_FINI)) != 0) 99 #define IS_DMA_DONE(X) (((X) & (DMA_DESC_DONE)) != 0) 100 #define RCVPKT_LENGTH(X) (((X) & ETH_RX_LEN) >> ETH_RX_LEN_BIT) 101 102 /* Information that need to be kept for each board. */ 103 struct korina_private { 104 struct eth_regs *eth_regs; 105 struct dma_reg *rx_dma_regs; 106 struct dma_reg *tx_dma_regs; 107 struct dma_desc *td_ring; /* transmit descriptor ring */ 108 struct dma_desc *rd_ring; /* receive descriptor ring */ 109 110 struct sk_buff *tx_skb[KORINA_NUM_TDS]; 111 struct sk_buff *rx_skb[KORINA_NUM_RDS]; 112 113 int rx_next_done; 114 int rx_chain_head; 115 int rx_chain_tail; 116 enum chain_status rx_chain_status; 117 118 int tx_next_done; 119 int tx_chain_head; 120 int tx_chain_tail; 121 enum chain_status tx_chain_status; 122 int tx_count; 123 int tx_full; 124 125 int rx_irq; 126 int tx_irq; 127 int ovr_irq; 128 int und_irq; 129 130 spinlock_t lock; /* NIC xmit lock */ 131 132 int dma_halt_cnt; 133 int dma_run_cnt; 134 struct napi_struct napi; 135 struct timer_list media_check_timer; 136 struct mii_if_info mii_if; 137 struct work_struct restart_task; 138 struct net_device *dev; 139 int phy_addr; 140 }; 141 142 extern unsigned int idt_cpu_freq; 143 144 static inline void korina_start_dma(struct dma_reg *ch, u32 dma_addr) 145 { 146 writel(0, &ch->dmandptr); 147 writel(dma_addr, &ch->dmadptr); 148 } 149 150 static inline void korina_abort_dma(struct net_device *dev, 151 struct dma_reg *ch) 152 { 153 if (readl(&ch->dmac) & DMA_CHAN_RUN_BIT) { 154 writel(0x10, &ch->dmac); 155 156 while (!(readl(&ch->dmas) & DMA_STAT_HALT)) 157 dev->trans_start = jiffies; 158 159 writel(0, &ch->dmas); 160 } 161 162 writel(0, &ch->dmadptr); 163 writel(0, &ch->dmandptr); 164 } 165 166 static inline void korina_chain_dma(struct dma_reg *ch, u32 dma_addr) 167 { 168 writel(dma_addr, &ch->dmandptr); 169 } 170 171 static void korina_abort_tx(struct net_device *dev) 172 { 173 struct korina_private *lp = netdev_priv(dev); 174 175 korina_abort_dma(dev, lp->tx_dma_regs); 176 } 177 178 static void korina_abort_rx(struct net_device *dev) 179 { 180 struct korina_private *lp = netdev_priv(dev); 181 182 korina_abort_dma(dev, lp->rx_dma_regs); 183 } 184 185 static void korina_start_rx(struct korina_private *lp, 186 struct dma_desc *rd) 187 { 188 korina_start_dma(lp->rx_dma_regs, CPHYSADDR(rd)); 189 } 190 191 static void korina_chain_rx(struct korina_private *lp, 192 struct dma_desc *rd) 193 { 194 korina_chain_dma(lp->rx_dma_regs, CPHYSADDR(rd)); 195 } 196 197 /* transmit packet */ 198 static int korina_send_packet(struct sk_buff *skb, struct net_device *dev) 199 { 200 struct korina_private *lp = netdev_priv(dev); 201 unsigned long flags; 202 u32 length; 203 u32 chain_prev, chain_next; 204 struct dma_desc *td; 205 206 spin_lock_irqsave(&lp->lock, flags); 207 208 td = &lp->td_ring[lp->tx_chain_tail]; 209 210 /* stop queue when full, drop pkts if queue already full */ 211 if (lp->tx_count >= (KORINA_NUM_TDS - 2)) { 212 lp->tx_full = 1; 213 214 if (lp->tx_count == (KORINA_NUM_TDS - 2)) 215 netif_stop_queue(dev); 216 else { 217 dev->stats.tx_dropped++; 218 dev_kfree_skb_any(skb); 219 spin_unlock_irqrestore(&lp->lock, flags); 220 221 return NETDEV_TX_BUSY; 222 } 223 } 224 225 lp->tx_count++; 226 227 lp->tx_skb[lp->tx_chain_tail] = skb; 228 229 length = skb->len; 230 dma_cache_wback((u32)skb->data, skb->len); 231 232 /* Setup the transmit descriptor. */ 233 dma_cache_inv((u32) td, sizeof(*td)); 234 td->ca = CPHYSADDR(skb->data); 235 chain_prev = (lp->tx_chain_tail - 1) & KORINA_TDS_MASK; 236 chain_next = (lp->tx_chain_tail + 1) & KORINA_TDS_MASK; 237 238 if (readl(&(lp->tx_dma_regs->dmandptr)) == 0) { 239 if (lp->tx_chain_status == desc_empty) { 240 /* Update tail */ 241 td->control = DMA_COUNT(length) | 242 DMA_DESC_COF | DMA_DESC_IOF; 243 /* Move tail */ 244 lp->tx_chain_tail = chain_next; 245 /* Write to NDPTR */ 246 writel(CPHYSADDR(&lp->td_ring[lp->tx_chain_head]), 247 &lp->tx_dma_regs->dmandptr); 248 /* Move head to tail */ 249 lp->tx_chain_head = lp->tx_chain_tail; 250 } else { 251 /* Update tail */ 252 td->control = DMA_COUNT(length) | 253 DMA_DESC_COF | DMA_DESC_IOF; 254 /* Link to prev */ 255 lp->td_ring[chain_prev].control &= 256 ~DMA_DESC_COF; 257 /* Link to prev */ 258 lp->td_ring[chain_prev].link = CPHYSADDR(td); 259 /* Move tail */ 260 lp->tx_chain_tail = chain_next; 261 /* Write to NDPTR */ 262 writel(CPHYSADDR(&lp->td_ring[lp->tx_chain_head]), 263 &(lp->tx_dma_regs->dmandptr)); 264 /* Move head to tail */ 265 lp->tx_chain_head = lp->tx_chain_tail; 266 lp->tx_chain_status = desc_empty; 267 } 268 } else { 269 if (lp->tx_chain_status == desc_empty) { 270 /* Update tail */ 271 td->control = DMA_COUNT(length) | 272 DMA_DESC_COF | DMA_DESC_IOF; 273 /* Move tail */ 274 lp->tx_chain_tail = chain_next; 275 lp->tx_chain_status = desc_filled; 276 } else { 277 /* Update tail */ 278 td->control = DMA_COUNT(length) | 279 DMA_DESC_COF | DMA_DESC_IOF; 280 lp->td_ring[chain_prev].control &= 281 ~DMA_DESC_COF; 282 lp->td_ring[chain_prev].link = CPHYSADDR(td); 283 lp->tx_chain_tail = chain_next; 284 } 285 } 286 dma_cache_wback((u32) td, sizeof(*td)); 287 288 dev->trans_start = jiffies; 289 spin_unlock_irqrestore(&lp->lock, flags); 290 291 return NETDEV_TX_OK; 292 } 293 294 static int mdio_read(struct net_device *dev, int mii_id, int reg) 295 { 296 struct korina_private *lp = netdev_priv(dev); 297 int ret; 298 299 mii_id = ((lp->rx_irq == 0x2c ? 1 : 0) << 8); 300 301 writel(0, &lp->eth_regs->miimcfg); 302 writel(0, &lp->eth_regs->miimcmd); 303 writel(mii_id | reg, &lp->eth_regs->miimaddr); 304 writel(ETH_MII_CMD_SCN, &lp->eth_regs->miimcmd); 305 306 ret = (int)(readl(&lp->eth_regs->miimrdd)); 307 return ret; 308 } 309 310 static void mdio_write(struct net_device *dev, int mii_id, int reg, int val) 311 { 312 struct korina_private *lp = netdev_priv(dev); 313 314 mii_id = ((lp->rx_irq == 0x2c ? 1 : 0) << 8); 315 316 writel(0, &lp->eth_regs->miimcfg); 317 writel(1, &lp->eth_regs->miimcmd); 318 writel(mii_id | reg, &lp->eth_regs->miimaddr); 319 writel(ETH_MII_CMD_SCN, &lp->eth_regs->miimcmd); 320 writel(val, &lp->eth_regs->miimwtd); 321 } 322 323 /* Ethernet Rx DMA interrupt */ 324 static irqreturn_t korina_rx_dma_interrupt(int irq, void *dev_id) 325 { 326 struct net_device *dev = dev_id; 327 struct korina_private *lp = netdev_priv(dev); 328 u32 dmas, dmasm; 329 irqreturn_t retval; 330 331 dmas = readl(&lp->rx_dma_regs->dmas); 332 if (dmas & (DMA_STAT_DONE | DMA_STAT_HALT | DMA_STAT_ERR)) { 333 dmasm = readl(&lp->rx_dma_regs->dmasm); 334 writel(dmasm | (DMA_STAT_DONE | 335 DMA_STAT_HALT | DMA_STAT_ERR), 336 &lp->rx_dma_regs->dmasm); 337 338 napi_schedule(&lp->napi); 339 340 if (dmas & DMA_STAT_ERR) 341 printk(KERN_ERR "%s: DMA error\n", dev->name); 342 343 retval = IRQ_HANDLED; 344 } else 345 retval = IRQ_NONE; 346 347 return retval; 348 } 349 350 static int korina_rx(struct net_device *dev, int limit) 351 { 352 struct korina_private *lp = netdev_priv(dev); 353 struct dma_desc *rd = &lp->rd_ring[lp->rx_next_done]; 354 struct sk_buff *skb, *skb_new; 355 u8 *pkt_buf; 356 u32 devcs, pkt_len, dmas; 357 int count; 358 359 dma_cache_inv((u32)rd, sizeof(*rd)); 360 361 for (count = 0; count < limit; count++) { 362 skb = lp->rx_skb[lp->rx_next_done]; 363 skb_new = NULL; 364 365 devcs = rd->devcs; 366 367 if ((KORINA_RBSIZE - (u32)DMA_COUNT(rd->control)) == 0) 368 break; 369 370 /* Update statistics counters */ 371 if (devcs & ETH_RX_CRC) 372 dev->stats.rx_crc_errors++; 373 if (devcs & ETH_RX_LOR) 374 dev->stats.rx_length_errors++; 375 if (devcs & ETH_RX_LE) 376 dev->stats.rx_length_errors++; 377 if (devcs & ETH_RX_OVR) 378 dev->stats.rx_fifo_errors++; 379 if (devcs & ETH_RX_CV) 380 dev->stats.rx_frame_errors++; 381 if (devcs & ETH_RX_CES) 382 dev->stats.rx_length_errors++; 383 if (devcs & ETH_RX_MP) 384 dev->stats.multicast++; 385 386 if ((devcs & ETH_RX_LD) != ETH_RX_LD) { 387 /* check that this is a whole packet 388 * WARNING: DMA_FD bit incorrectly set 389 * in Rc32434 (errata ref #077) */ 390 dev->stats.rx_errors++; 391 dev->stats.rx_dropped++; 392 } else if ((devcs & ETH_RX_ROK)) { 393 pkt_len = RCVPKT_LENGTH(devcs); 394 395 /* must be the (first and) last 396 * descriptor then */ 397 pkt_buf = (u8 *)lp->rx_skb[lp->rx_next_done]->data; 398 399 /* invalidate the cache */ 400 dma_cache_inv((unsigned long)pkt_buf, pkt_len - 4); 401 402 /* Malloc up new buffer. */ 403 skb_new = netdev_alloc_skb_ip_align(dev, KORINA_RBSIZE); 404 405 if (!skb_new) 406 break; 407 /* Do not count the CRC */ 408 skb_put(skb, pkt_len - 4); 409 skb->protocol = eth_type_trans(skb, dev); 410 411 /* Pass the packet to upper layers */ 412 netif_receive_skb(skb); 413 dev->stats.rx_packets++; 414 dev->stats.rx_bytes += pkt_len; 415 416 /* Update the mcast stats */ 417 if (devcs & ETH_RX_MP) 418 dev->stats.multicast++; 419 420 lp->rx_skb[lp->rx_next_done] = skb_new; 421 } 422 423 rd->devcs = 0; 424 425 /* Restore descriptor's curr_addr */ 426 if (skb_new) 427 rd->ca = CPHYSADDR(skb_new->data); 428 else 429 rd->ca = CPHYSADDR(skb->data); 430 431 rd->control = DMA_COUNT(KORINA_RBSIZE) | 432 DMA_DESC_COD | DMA_DESC_IOD; 433 lp->rd_ring[(lp->rx_next_done - 1) & 434 KORINA_RDS_MASK].control &= 435 ~DMA_DESC_COD; 436 437 lp->rx_next_done = (lp->rx_next_done + 1) & KORINA_RDS_MASK; 438 dma_cache_wback((u32)rd, sizeof(*rd)); 439 rd = &lp->rd_ring[lp->rx_next_done]; 440 writel(~DMA_STAT_DONE, &lp->rx_dma_regs->dmas); 441 } 442 443 dmas = readl(&lp->rx_dma_regs->dmas); 444 445 if (dmas & DMA_STAT_HALT) { 446 writel(~(DMA_STAT_HALT | DMA_STAT_ERR), 447 &lp->rx_dma_regs->dmas); 448 449 lp->dma_halt_cnt++; 450 rd->devcs = 0; 451 skb = lp->rx_skb[lp->rx_next_done]; 452 rd->ca = CPHYSADDR(skb->data); 453 dma_cache_wback((u32)rd, sizeof(*rd)); 454 korina_chain_rx(lp, rd); 455 } 456 457 return count; 458 } 459 460 static int korina_poll(struct napi_struct *napi, int budget) 461 { 462 struct korina_private *lp = 463 container_of(napi, struct korina_private, napi); 464 struct net_device *dev = lp->dev; 465 int work_done; 466 467 work_done = korina_rx(dev, budget); 468 if (work_done < budget) { 469 napi_complete(napi); 470 471 writel(readl(&lp->rx_dma_regs->dmasm) & 472 ~(DMA_STAT_DONE | DMA_STAT_HALT | DMA_STAT_ERR), 473 &lp->rx_dma_regs->dmasm); 474 } 475 return work_done; 476 } 477 478 /* 479 * Set or clear the multicast filter for this adaptor. 480 */ 481 static void korina_multicast_list(struct net_device *dev) 482 { 483 struct korina_private *lp = netdev_priv(dev); 484 unsigned long flags; 485 struct netdev_hw_addr *ha; 486 u32 recognise = ETH_ARC_AB; /* always accept broadcasts */ 487 int i; 488 489 /* Set promiscuous mode */ 490 if (dev->flags & IFF_PROMISC) 491 recognise |= ETH_ARC_PRO; 492 493 else if ((dev->flags & IFF_ALLMULTI) || (netdev_mc_count(dev) > 4)) 494 /* All multicast and broadcast */ 495 recognise |= ETH_ARC_AM; 496 497 /* Build the hash table */ 498 if (netdev_mc_count(dev) > 4) { 499 u16 hash_table[4]; 500 u32 crc; 501 502 for (i = 0; i < 4; i++) 503 hash_table[i] = 0; 504 505 netdev_for_each_mc_addr(ha, dev) { 506 crc = ether_crc_le(6, ha->addr); 507 crc >>= 26; 508 hash_table[crc >> 4] |= 1 << (15 - (crc & 0xf)); 509 } 510 /* Accept filtered multicast */ 511 recognise |= ETH_ARC_AFM; 512 513 /* Fill the MAC hash tables with their values */ 514 writel((u32)(hash_table[1] << 16 | hash_table[0]), 515 &lp->eth_regs->ethhash0); 516 writel((u32)(hash_table[3] << 16 | hash_table[2]), 517 &lp->eth_regs->ethhash1); 518 } 519 520 spin_lock_irqsave(&lp->lock, flags); 521 writel(recognise, &lp->eth_regs->etharc); 522 spin_unlock_irqrestore(&lp->lock, flags); 523 } 524 525 static void korina_tx(struct net_device *dev) 526 { 527 struct korina_private *lp = netdev_priv(dev); 528 struct dma_desc *td = &lp->td_ring[lp->tx_next_done]; 529 u32 devcs; 530 u32 dmas; 531 532 spin_lock(&lp->lock); 533 534 /* Process all desc that are done */ 535 while (IS_DMA_FINISHED(td->control)) { 536 if (lp->tx_full == 1) { 537 netif_wake_queue(dev); 538 lp->tx_full = 0; 539 } 540 541 devcs = lp->td_ring[lp->tx_next_done].devcs; 542 if ((devcs & (ETH_TX_FD | ETH_TX_LD)) != 543 (ETH_TX_FD | ETH_TX_LD)) { 544 dev->stats.tx_errors++; 545 dev->stats.tx_dropped++; 546 547 /* Should never happen */ 548 printk(KERN_ERR "%s: split tx ignored\n", 549 dev->name); 550 } else if (devcs & ETH_TX_TOK) { 551 dev->stats.tx_packets++; 552 dev->stats.tx_bytes += 553 lp->tx_skb[lp->tx_next_done]->len; 554 } else { 555 dev->stats.tx_errors++; 556 dev->stats.tx_dropped++; 557 558 /* Underflow */ 559 if (devcs & ETH_TX_UND) 560 dev->stats.tx_fifo_errors++; 561 562 /* Oversized frame */ 563 if (devcs & ETH_TX_OF) 564 dev->stats.tx_aborted_errors++; 565 566 /* Excessive deferrals */ 567 if (devcs & ETH_TX_ED) 568 dev->stats.tx_carrier_errors++; 569 570 /* Collisions: medium busy */ 571 if (devcs & ETH_TX_EC) 572 dev->stats.collisions++; 573 574 /* Late collision */ 575 if (devcs & ETH_TX_LC) 576 dev->stats.tx_window_errors++; 577 } 578 579 /* We must always free the original skb */ 580 if (lp->tx_skb[lp->tx_next_done]) { 581 dev_kfree_skb_any(lp->tx_skb[lp->tx_next_done]); 582 lp->tx_skb[lp->tx_next_done] = NULL; 583 } 584 585 lp->td_ring[lp->tx_next_done].control = DMA_DESC_IOF; 586 lp->td_ring[lp->tx_next_done].devcs = ETH_TX_FD | ETH_TX_LD; 587 lp->td_ring[lp->tx_next_done].link = 0; 588 lp->td_ring[lp->tx_next_done].ca = 0; 589 lp->tx_count--; 590 591 /* Go on to next transmission */ 592 lp->tx_next_done = (lp->tx_next_done + 1) & KORINA_TDS_MASK; 593 td = &lp->td_ring[lp->tx_next_done]; 594 595 } 596 597 /* Clear the DMA status register */ 598 dmas = readl(&lp->tx_dma_regs->dmas); 599 writel(~dmas, &lp->tx_dma_regs->dmas); 600 601 writel(readl(&lp->tx_dma_regs->dmasm) & 602 ~(DMA_STAT_FINI | DMA_STAT_ERR), 603 &lp->tx_dma_regs->dmasm); 604 605 spin_unlock(&lp->lock); 606 } 607 608 static irqreturn_t 609 korina_tx_dma_interrupt(int irq, void *dev_id) 610 { 611 struct net_device *dev = dev_id; 612 struct korina_private *lp = netdev_priv(dev); 613 u32 dmas, dmasm; 614 irqreturn_t retval; 615 616 dmas = readl(&lp->tx_dma_regs->dmas); 617 618 if (dmas & (DMA_STAT_FINI | DMA_STAT_ERR)) { 619 dmasm = readl(&lp->tx_dma_regs->dmasm); 620 writel(dmasm | (DMA_STAT_FINI | DMA_STAT_ERR), 621 &lp->tx_dma_regs->dmasm); 622 623 korina_tx(dev); 624 625 if (lp->tx_chain_status == desc_filled && 626 (readl(&(lp->tx_dma_regs->dmandptr)) == 0)) { 627 writel(CPHYSADDR(&lp->td_ring[lp->tx_chain_head]), 628 &(lp->tx_dma_regs->dmandptr)); 629 lp->tx_chain_status = desc_empty; 630 lp->tx_chain_head = lp->tx_chain_tail; 631 dev->trans_start = jiffies; 632 } 633 if (dmas & DMA_STAT_ERR) 634 printk(KERN_ERR "%s: DMA error\n", dev->name); 635 636 retval = IRQ_HANDLED; 637 } else 638 retval = IRQ_NONE; 639 640 return retval; 641 } 642 643 644 static void korina_check_media(struct net_device *dev, unsigned int init_media) 645 { 646 struct korina_private *lp = netdev_priv(dev); 647 648 mii_check_media(&lp->mii_if, 0, init_media); 649 650 if (lp->mii_if.full_duplex) 651 writel(readl(&lp->eth_regs->ethmac2) | ETH_MAC2_FD, 652 &lp->eth_regs->ethmac2); 653 else 654 writel(readl(&lp->eth_regs->ethmac2) & ~ETH_MAC2_FD, 655 &lp->eth_regs->ethmac2); 656 } 657 658 static void korina_poll_media(unsigned long data) 659 { 660 struct net_device *dev = (struct net_device *) data; 661 struct korina_private *lp = netdev_priv(dev); 662 663 korina_check_media(dev, 0); 664 mod_timer(&lp->media_check_timer, jiffies + HZ); 665 } 666 667 static void korina_set_carrier(struct mii_if_info *mii) 668 { 669 if (mii->force_media) { 670 /* autoneg is off: Link is always assumed to be up */ 671 if (!netif_carrier_ok(mii->dev)) 672 netif_carrier_on(mii->dev); 673 } else /* Let MMI library update carrier status */ 674 korina_check_media(mii->dev, 0); 675 } 676 677 static int korina_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) 678 { 679 struct korina_private *lp = netdev_priv(dev); 680 struct mii_ioctl_data *data = if_mii(rq); 681 int rc; 682 683 if (!netif_running(dev)) 684 return -EINVAL; 685 spin_lock_irq(&lp->lock); 686 rc = generic_mii_ioctl(&lp->mii_if, data, cmd, NULL); 687 spin_unlock_irq(&lp->lock); 688 korina_set_carrier(&lp->mii_if); 689 690 return rc; 691 } 692 693 /* ethtool helpers */ 694 static void netdev_get_drvinfo(struct net_device *dev, 695 struct ethtool_drvinfo *info) 696 { 697 struct korina_private *lp = netdev_priv(dev); 698 699 strcpy(info->driver, DRV_NAME); 700 strcpy(info->version, DRV_VERSION); 701 strcpy(info->bus_info, lp->dev->name); 702 } 703 704 static int netdev_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) 705 { 706 struct korina_private *lp = netdev_priv(dev); 707 int rc; 708 709 spin_lock_irq(&lp->lock); 710 rc = mii_ethtool_gset(&lp->mii_if, cmd); 711 spin_unlock_irq(&lp->lock); 712 713 return rc; 714 } 715 716 static int netdev_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) 717 { 718 struct korina_private *lp = netdev_priv(dev); 719 int rc; 720 721 spin_lock_irq(&lp->lock); 722 rc = mii_ethtool_sset(&lp->mii_if, cmd); 723 spin_unlock_irq(&lp->lock); 724 korina_set_carrier(&lp->mii_if); 725 726 return rc; 727 } 728 729 static u32 netdev_get_link(struct net_device *dev) 730 { 731 struct korina_private *lp = netdev_priv(dev); 732 733 return mii_link_ok(&lp->mii_if); 734 } 735 736 static const struct ethtool_ops netdev_ethtool_ops = { 737 .get_drvinfo = netdev_get_drvinfo, 738 .get_settings = netdev_get_settings, 739 .set_settings = netdev_set_settings, 740 .get_link = netdev_get_link, 741 }; 742 743 static int korina_alloc_ring(struct net_device *dev) 744 { 745 struct korina_private *lp = netdev_priv(dev); 746 struct sk_buff *skb; 747 int i; 748 749 /* Initialize the transmit descriptors */ 750 for (i = 0; i < KORINA_NUM_TDS; i++) { 751 lp->td_ring[i].control = DMA_DESC_IOF; 752 lp->td_ring[i].devcs = ETH_TX_FD | ETH_TX_LD; 753 lp->td_ring[i].ca = 0; 754 lp->td_ring[i].link = 0; 755 } 756 lp->tx_next_done = lp->tx_chain_head = lp->tx_chain_tail = 757 lp->tx_full = lp->tx_count = 0; 758 lp->tx_chain_status = desc_empty; 759 760 /* Initialize the receive descriptors */ 761 for (i = 0; i < KORINA_NUM_RDS; i++) { 762 skb = netdev_alloc_skb_ip_align(dev, KORINA_RBSIZE); 763 if (!skb) 764 return -ENOMEM; 765 lp->rx_skb[i] = skb; 766 lp->rd_ring[i].control = DMA_DESC_IOD | 767 DMA_COUNT(KORINA_RBSIZE); 768 lp->rd_ring[i].devcs = 0; 769 lp->rd_ring[i].ca = CPHYSADDR(skb->data); 770 lp->rd_ring[i].link = CPHYSADDR(&lp->rd_ring[i+1]); 771 } 772 773 /* loop back receive descriptors, so the last 774 * descriptor points to the first one */ 775 lp->rd_ring[i - 1].link = CPHYSADDR(&lp->rd_ring[0]); 776 lp->rd_ring[i - 1].control |= DMA_DESC_COD; 777 778 lp->rx_next_done = 0; 779 lp->rx_chain_head = 0; 780 lp->rx_chain_tail = 0; 781 lp->rx_chain_status = desc_empty; 782 783 return 0; 784 } 785 786 static void korina_free_ring(struct net_device *dev) 787 { 788 struct korina_private *lp = netdev_priv(dev); 789 int i; 790 791 for (i = 0; i < KORINA_NUM_RDS; i++) { 792 lp->rd_ring[i].control = 0; 793 if (lp->rx_skb[i]) 794 dev_kfree_skb_any(lp->rx_skb[i]); 795 lp->rx_skb[i] = NULL; 796 } 797 798 for (i = 0; i < KORINA_NUM_TDS; i++) { 799 lp->td_ring[i].control = 0; 800 if (lp->tx_skb[i]) 801 dev_kfree_skb_any(lp->tx_skb[i]); 802 lp->tx_skb[i] = NULL; 803 } 804 } 805 806 /* 807 * Initialize the RC32434 ethernet controller. 808 */ 809 static int korina_init(struct net_device *dev) 810 { 811 struct korina_private *lp = netdev_priv(dev); 812 813 /* Disable DMA */ 814 korina_abort_tx(dev); 815 korina_abort_rx(dev); 816 817 /* reset ethernet logic */ 818 writel(0, &lp->eth_regs->ethintfc); 819 while ((readl(&lp->eth_regs->ethintfc) & ETH_INT_FC_RIP)) 820 dev->trans_start = jiffies; 821 822 /* Enable Ethernet Interface */ 823 writel(ETH_INT_FC_EN, &lp->eth_regs->ethintfc); 824 825 /* Allocate rings */ 826 if (korina_alloc_ring(dev)) { 827 printk(KERN_ERR "%s: descriptor allocation failed\n", dev->name); 828 korina_free_ring(dev); 829 return -ENOMEM; 830 } 831 832 writel(0, &lp->rx_dma_regs->dmas); 833 /* Start Rx DMA */ 834 korina_start_rx(lp, &lp->rd_ring[0]); 835 836 writel(readl(&lp->tx_dma_regs->dmasm) & 837 ~(DMA_STAT_FINI | DMA_STAT_ERR), 838 &lp->tx_dma_regs->dmasm); 839 writel(readl(&lp->rx_dma_regs->dmasm) & 840 ~(DMA_STAT_DONE | DMA_STAT_HALT | DMA_STAT_ERR), 841 &lp->rx_dma_regs->dmasm); 842 843 /* Accept only packets destined for this Ethernet device address */ 844 writel(ETH_ARC_AB, &lp->eth_regs->etharc); 845 846 /* Set all Ether station address registers to their initial values */ 847 writel(STATION_ADDRESS_LOW(dev), &lp->eth_regs->ethsal0); 848 writel(STATION_ADDRESS_HIGH(dev), &lp->eth_regs->ethsah0); 849 850 writel(STATION_ADDRESS_LOW(dev), &lp->eth_regs->ethsal1); 851 writel(STATION_ADDRESS_HIGH(dev), &lp->eth_regs->ethsah1); 852 853 writel(STATION_ADDRESS_LOW(dev), &lp->eth_regs->ethsal2); 854 writel(STATION_ADDRESS_HIGH(dev), &lp->eth_regs->ethsah2); 855 856 writel(STATION_ADDRESS_LOW(dev), &lp->eth_regs->ethsal3); 857 writel(STATION_ADDRESS_HIGH(dev), &lp->eth_regs->ethsah3); 858 859 860 /* Frame Length Checking, Pad Enable, CRC Enable, Full Duplex set */ 861 writel(ETH_MAC2_PE | ETH_MAC2_CEN | ETH_MAC2_FD, 862 &lp->eth_regs->ethmac2); 863 864 /* Back to back inter-packet-gap */ 865 writel(0x15, &lp->eth_regs->ethipgt); 866 /* Non - Back to back inter-packet-gap */ 867 writel(0x12, &lp->eth_regs->ethipgr); 868 869 /* Management Clock Prescaler Divisor 870 * Clock independent setting */ 871 writel(((idt_cpu_freq) / MII_CLOCK + 1) & ~1, 872 &lp->eth_regs->ethmcp); 873 874 /* don't transmit until fifo contains 48b */ 875 writel(48, &lp->eth_regs->ethfifott); 876 877 writel(ETH_MAC1_RE, &lp->eth_regs->ethmac1); 878 879 napi_enable(&lp->napi); 880 netif_start_queue(dev); 881 882 return 0; 883 } 884 885 /* 886 * Restart the RC32434 ethernet controller. 887 */ 888 static void korina_restart_task(struct work_struct *work) 889 { 890 struct korina_private *lp = container_of(work, 891 struct korina_private, restart_task); 892 struct net_device *dev = lp->dev; 893 894 /* 895 * Disable interrupts 896 */ 897 disable_irq(lp->rx_irq); 898 disable_irq(lp->tx_irq); 899 disable_irq(lp->ovr_irq); 900 disable_irq(lp->und_irq); 901 902 writel(readl(&lp->tx_dma_regs->dmasm) | 903 DMA_STAT_FINI | DMA_STAT_ERR, 904 &lp->tx_dma_regs->dmasm); 905 writel(readl(&lp->rx_dma_regs->dmasm) | 906 DMA_STAT_DONE | DMA_STAT_HALT | DMA_STAT_ERR, 907 &lp->rx_dma_regs->dmasm); 908 909 korina_free_ring(dev); 910 911 napi_disable(&lp->napi); 912 913 if (korina_init(dev) < 0) { 914 printk(KERN_ERR "%s: cannot restart device\n", dev->name); 915 return; 916 } 917 korina_multicast_list(dev); 918 919 enable_irq(lp->und_irq); 920 enable_irq(lp->ovr_irq); 921 enable_irq(lp->tx_irq); 922 enable_irq(lp->rx_irq); 923 } 924 925 static void korina_clear_and_restart(struct net_device *dev, u32 value) 926 { 927 struct korina_private *lp = netdev_priv(dev); 928 929 netif_stop_queue(dev); 930 writel(value, &lp->eth_regs->ethintfc); 931 schedule_work(&lp->restart_task); 932 } 933 934 /* Ethernet Tx Underflow interrupt */ 935 static irqreturn_t korina_und_interrupt(int irq, void *dev_id) 936 { 937 struct net_device *dev = dev_id; 938 struct korina_private *lp = netdev_priv(dev); 939 unsigned int und; 940 941 spin_lock(&lp->lock); 942 943 und = readl(&lp->eth_regs->ethintfc); 944 945 if (und & ETH_INT_FC_UND) 946 korina_clear_and_restart(dev, und & ~ETH_INT_FC_UND); 947 948 spin_unlock(&lp->lock); 949 950 return IRQ_HANDLED; 951 } 952 953 static void korina_tx_timeout(struct net_device *dev) 954 { 955 struct korina_private *lp = netdev_priv(dev); 956 957 schedule_work(&lp->restart_task); 958 } 959 960 /* Ethernet Rx Overflow interrupt */ 961 static irqreturn_t 962 korina_ovr_interrupt(int irq, void *dev_id) 963 { 964 struct net_device *dev = dev_id; 965 struct korina_private *lp = netdev_priv(dev); 966 unsigned int ovr; 967 968 spin_lock(&lp->lock); 969 ovr = readl(&lp->eth_regs->ethintfc); 970 971 if (ovr & ETH_INT_FC_OVR) 972 korina_clear_and_restart(dev, ovr & ~ETH_INT_FC_OVR); 973 974 spin_unlock(&lp->lock); 975 976 return IRQ_HANDLED; 977 } 978 979 #ifdef CONFIG_NET_POLL_CONTROLLER 980 static void korina_poll_controller(struct net_device *dev) 981 { 982 disable_irq(dev->irq); 983 korina_tx_dma_interrupt(dev->irq, dev); 984 enable_irq(dev->irq); 985 } 986 #endif 987 988 static int korina_open(struct net_device *dev) 989 { 990 struct korina_private *lp = netdev_priv(dev); 991 int ret; 992 993 /* Initialize */ 994 ret = korina_init(dev); 995 if (ret < 0) { 996 printk(KERN_ERR "%s: cannot open device\n", dev->name); 997 goto out; 998 } 999 1000 /* Install the interrupt handler 1001 * that handles the Done Finished 1002 * Ovr and Und Events */ 1003 ret = request_irq(lp->rx_irq, korina_rx_dma_interrupt, 1004 IRQF_DISABLED, "Korina ethernet Rx", dev); 1005 if (ret < 0) { 1006 printk(KERN_ERR "%s: unable to get Rx DMA IRQ %d\n", 1007 dev->name, lp->rx_irq); 1008 goto err_release; 1009 } 1010 ret = request_irq(lp->tx_irq, korina_tx_dma_interrupt, 1011 IRQF_DISABLED, "Korina ethernet Tx", dev); 1012 if (ret < 0) { 1013 printk(KERN_ERR "%s: unable to get Tx DMA IRQ %d\n", 1014 dev->name, lp->tx_irq); 1015 goto err_free_rx_irq; 1016 } 1017 1018 /* Install handler for overrun error. */ 1019 ret = request_irq(lp->ovr_irq, korina_ovr_interrupt, 1020 IRQF_DISABLED, "Ethernet Overflow", dev); 1021 if (ret < 0) { 1022 printk(KERN_ERR "%s: unable to get OVR IRQ %d\n", 1023 dev->name, lp->ovr_irq); 1024 goto err_free_tx_irq; 1025 } 1026 1027 /* Install handler for underflow error. */ 1028 ret = request_irq(lp->und_irq, korina_und_interrupt, 1029 IRQF_DISABLED, "Ethernet Underflow", dev); 1030 if (ret < 0) { 1031 printk(KERN_ERR "%s: unable to get UND IRQ %d\n", 1032 dev->name, lp->und_irq); 1033 goto err_free_ovr_irq; 1034 } 1035 mod_timer(&lp->media_check_timer, jiffies + 1); 1036 out: 1037 return ret; 1038 1039 err_free_ovr_irq: 1040 free_irq(lp->ovr_irq, dev); 1041 err_free_tx_irq: 1042 free_irq(lp->tx_irq, dev); 1043 err_free_rx_irq: 1044 free_irq(lp->rx_irq, dev); 1045 err_release: 1046 korina_free_ring(dev); 1047 goto out; 1048 } 1049 1050 static int korina_close(struct net_device *dev) 1051 { 1052 struct korina_private *lp = netdev_priv(dev); 1053 u32 tmp; 1054 1055 del_timer(&lp->media_check_timer); 1056 1057 /* Disable interrupts */ 1058 disable_irq(lp->rx_irq); 1059 disable_irq(lp->tx_irq); 1060 disable_irq(lp->ovr_irq); 1061 disable_irq(lp->und_irq); 1062 1063 korina_abort_tx(dev); 1064 tmp = readl(&lp->tx_dma_regs->dmasm); 1065 tmp = tmp | DMA_STAT_FINI | DMA_STAT_ERR; 1066 writel(tmp, &lp->tx_dma_regs->dmasm); 1067 1068 korina_abort_rx(dev); 1069 tmp = readl(&lp->rx_dma_regs->dmasm); 1070 tmp = tmp | DMA_STAT_DONE | DMA_STAT_HALT | DMA_STAT_ERR; 1071 writel(tmp, &lp->rx_dma_regs->dmasm); 1072 1073 korina_free_ring(dev); 1074 1075 napi_disable(&lp->napi); 1076 1077 cancel_work_sync(&lp->restart_task); 1078 1079 free_irq(lp->rx_irq, dev); 1080 free_irq(lp->tx_irq, dev); 1081 free_irq(lp->ovr_irq, dev); 1082 free_irq(lp->und_irq, dev); 1083 1084 return 0; 1085 } 1086 1087 static const struct net_device_ops korina_netdev_ops = { 1088 .ndo_open = korina_open, 1089 .ndo_stop = korina_close, 1090 .ndo_start_xmit = korina_send_packet, 1091 .ndo_set_rx_mode = korina_multicast_list, 1092 .ndo_tx_timeout = korina_tx_timeout, 1093 .ndo_do_ioctl = korina_ioctl, 1094 .ndo_change_mtu = eth_change_mtu, 1095 .ndo_validate_addr = eth_validate_addr, 1096 .ndo_set_mac_address = eth_mac_addr, 1097 #ifdef CONFIG_NET_POLL_CONTROLLER 1098 .ndo_poll_controller = korina_poll_controller, 1099 #endif 1100 }; 1101 1102 static int korina_probe(struct platform_device *pdev) 1103 { 1104 struct korina_device *bif = platform_get_drvdata(pdev); 1105 struct korina_private *lp; 1106 struct net_device *dev; 1107 struct resource *r; 1108 int rc; 1109 1110 dev = alloc_etherdev(sizeof(struct korina_private)); 1111 if (!dev) 1112 return -ENOMEM; 1113 1114 SET_NETDEV_DEV(dev, &pdev->dev); 1115 lp = netdev_priv(dev); 1116 1117 bif->dev = dev; 1118 memcpy(dev->dev_addr, bif->mac, 6); 1119 1120 lp->rx_irq = platform_get_irq_byname(pdev, "korina_rx"); 1121 lp->tx_irq = platform_get_irq_byname(pdev, "korina_tx"); 1122 lp->ovr_irq = platform_get_irq_byname(pdev, "korina_ovr"); 1123 lp->und_irq = platform_get_irq_byname(pdev, "korina_und"); 1124 1125 r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "korina_regs"); 1126 dev->base_addr = r->start; 1127 lp->eth_regs = ioremap_nocache(r->start, resource_size(r)); 1128 if (!lp->eth_regs) { 1129 printk(KERN_ERR DRV_NAME ": cannot remap registers\n"); 1130 rc = -ENXIO; 1131 goto probe_err_out; 1132 } 1133 1134 r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "korina_dma_rx"); 1135 lp->rx_dma_regs = ioremap_nocache(r->start, resource_size(r)); 1136 if (!lp->rx_dma_regs) { 1137 printk(KERN_ERR DRV_NAME ": cannot remap Rx DMA registers\n"); 1138 rc = -ENXIO; 1139 goto probe_err_dma_rx; 1140 } 1141 1142 r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "korina_dma_tx"); 1143 lp->tx_dma_regs = ioremap_nocache(r->start, resource_size(r)); 1144 if (!lp->tx_dma_regs) { 1145 printk(KERN_ERR DRV_NAME ": cannot remap Tx DMA registers\n"); 1146 rc = -ENXIO; 1147 goto probe_err_dma_tx; 1148 } 1149 1150 lp->td_ring = kmalloc(TD_RING_SIZE + RD_RING_SIZE, GFP_KERNEL); 1151 if (!lp->td_ring) { 1152 rc = -ENXIO; 1153 goto probe_err_td_ring; 1154 } 1155 1156 dma_cache_inv((unsigned long)(lp->td_ring), 1157 TD_RING_SIZE + RD_RING_SIZE); 1158 1159 /* now convert TD_RING pointer to KSEG1 */ 1160 lp->td_ring = (struct dma_desc *)KSEG1ADDR(lp->td_ring); 1161 lp->rd_ring = &lp->td_ring[KORINA_NUM_TDS]; 1162 1163 spin_lock_init(&lp->lock); 1164 /* just use the rx dma irq */ 1165 dev->irq = lp->rx_irq; 1166 lp->dev = dev; 1167 1168 dev->netdev_ops = &korina_netdev_ops; 1169 dev->ethtool_ops = &netdev_ethtool_ops; 1170 dev->watchdog_timeo = TX_TIMEOUT; 1171 netif_napi_add(dev, &lp->napi, korina_poll, 64); 1172 1173 lp->phy_addr = (((lp->rx_irq == 0x2c? 1:0) << 8) | 0x05); 1174 lp->mii_if.dev = dev; 1175 lp->mii_if.mdio_read = mdio_read; 1176 lp->mii_if.mdio_write = mdio_write; 1177 lp->mii_if.phy_id = lp->phy_addr; 1178 lp->mii_if.phy_id_mask = 0x1f; 1179 lp->mii_if.reg_num_mask = 0x1f; 1180 1181 rc = register_netdev(dev); 1182 if (rc < 0) { 1183 printk(KERN_ERR DRV_NAME 1184 ": cannot register net device: %d\n", rc); 1185 goto probe_err_register; 1186 } 1187 setup_timer(&lp->media_check_timer, korina_poll_media, (unsigned long) dev); 1188 1189 INIT_WORK(&lp->restart_task, korina_restart_task); 1190 1191 printk(KERN_INFO "%s: " DRV_NAME "-" DRV_VERSION " " DRV_RELDATE "\n", 1192 dev->name); 1193 out: 1194 return rc; 1195 1196 probe_err_register: 1197 kfree(lp->td_ring); 1198 probe_err_td_ring: 1199 iounmap(lp->tx_dma_regs); 1200 probe_err_dma_tx: 1201 iounmap(lp->rx_dma_regs); 1202 probe_err_dma_rx: 1203 iounmap(lp->eth_regs); 1204 probe_err_out: 1205 free_netdev(dev); 1206 goto out; 1207 } 1208 1209 static int korina_remove(struct platform_device *pdev) 1210 { 1211 struct korina_device *bif = platform_get_drvdata(pdev); 1212 struct korina_private *lp = netdev_priv(bif->dev); 1213 1214 iounmap(lp->eth_regs); 1215 iounmap(lp->rx_dma_regs); 1216 iounmap(lp->tx_dma_regs); 1217 1218 platform_set_drvdata(pdev, NULL); 1219 unregister_netdev(bif->dev); 1220 free_netdev(bif->dev); 1221 1222 return 0; 1223 } 1224 1225 static struct platform_driver korina_driver = { 1226 .driver.name = "korina", 1227 .probe = korina_probe, 1228 .remove = korina_remove, 1229 }; 1230 1231 module_platform_driver(korina_driver); 1232 1233 MODULE_AUTHOR("Philip Rischel <rischelp@idt.com>"); 1234 MODULE_AUTHOR("Felix Fietkau <nbd@openwrt.org>"); 1235 MODULE_AUTHOR("Florian Fainelli <florian@openwrt.org>"); 1236 MODULE_DESCRIPTION("IDT RC32434 (Korina) Ethernet driver"); 1237 MODULE_LICENSE("GPL"); 1238