1 /* 2 * JMicron JMC2x0 series PCIe Ethernet Linux Device Driver 3 * 4 * Copyright 2008 JMicron Technology Corporation 5 * http://www.jmicron.com/ 6 * Copyright (c) 2009 - 2010 Guo-Fu Tseng <cooldavid@cooldavid.org> 7 * 8 * Author: Guo-Fu Tseng <cooldavid@cooldavid.org> 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License as published by 12 * the Free Software Foundation; either version 2 of the License. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program; if not, write to the Free Software 21 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 22 * 23 */ 24 25 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 26 27 #include <linux/module.h> 28 #include <linux/kernel.h> 29 #include <linux/pci.h> 30 #include <linux/pci-aspm.h> 31 #include <linux/netdevice.h> 32 #include <linux/etherdevice.h> 33 #include <linux/ethtool.h> 34 #include <linux/mii.h> 35 #include <linux/crc32.h> 36 #include <linux/delay.h> 37 #include <linux/spinlock.h> 38 #include <linux/in.h> 39 #include <linux/ip.h> 40 #include <linux/ipv6.h> 41 #include <linux/tcp.h> 42 #include <linux/udp.h> 43 #include <linux/if_vlan.h> 44 #include <linux/slab.h> 45 #include <net/ip6_checksum.h> 46 #include "jme.h" 47 48 static int force_pseudohp = -1; 49 static int no_pseudohp = -1; 50 static int no_extplug = -1; 51 module_param(force_pseudohp, int, 0); 52 MODULE_PARM_DESC(force_pseudohp, 53 "Enable pseudo hot-plug feature manually by driver instead of BIOS."); 54 module_param(no_pseudohp, int, 0); 55 MODULE_PARM_DESC(no_pseudohp, "Disable pseudo hot-plug feature."); 56 module_param(no_extplug, int, 0); 57 MODULE_PARM_DESC(no_extplug, 58 "Do not use external plug signal for pseudo hot-plug."); 59 60 static int 61 jme_mdio_read(struct net_device *netdev, int phy, int reg) 62 { 63 struct jme_adapter *jme = netdev_priv(netdev); 64 int i, val, again = (reg == MII_BMSR) ? 1 : 0; 65 66 read_again: 67 jwrite32(jme, JME_SMI, SMI_OP_REQ | 68 smi_phy_addr(phy) | 69 smi_reg_addr(reg)); 70 71 wmb(); 72 for (i = JME_PHY_TIMEOUT * 50 ; i > 0 ; --i) { 73 udelay(20); 74 val = jread32(jme, JME_SMI); 75 if ((val & SMI_OP_REQ) == 0) 76 break; 77 } 78 79 if (i == 0) { 80 pr_err("phy(%d) read timeout : %d\n", phy, reg); 81 return 0; 82 } 83 84 if (again--) 85 goto read_again; 86 87 return (val & SMI_DATA_MASK) >> SMI_DATA_SHIFT; 88 } 89 90 static void 91 jme_mdio_write(struct net_device *netdev, 92 int phy, int reg, int val) 93 { 94 struct jme_adapter *jme = netdev_priv(netdev); 95 int i; 96 97 jwrite32(jme, JME_SMI, SMI_OP_WRITE | SMI_OP_REQ | 98 ((val << SMI_DATA_SHIFT) & SMI_DATA_MASK) | 99 smi_phy_addr(phy) | smi_reg_addr(reg)); 100 101 wmb(); 102 for (i = JME_PHY_TIMEOUT * 50 ; i > 0 ; --i) { 103 udelay(20); 104 if ((jread32(jme, JME_SMI) & SMI_OP_REQ) == 0) 105 break; 106 } 107 108 if (i == 0) 109 pr_err("phy(%d) write timeout : %d\n", phy, reg); 110 } 111 112 static inline void 113 jme_reset_phy_processor(struct jme_adapter *jme) 114 { 115 u32 val; 116 117 jme_mdio_write(jme->dev, 118 jme->mii_if.phy_id, 119 MII_ADVERTISE, ADVERTISE_ALL | 120 ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM); 121 122 if (jme->pdev->device == PCI_DEVICE_ID_JMICRON_JMC250) 123 jme_mdio_write(jme->dev, 124 jme->mii_if.phy_id, 125 MII_CTRL1000, 126 ADVERTISE_1000FULL | ADVERTISE_1000HALF); 127 128 val = jme_mdio_read(jme->dev, 129 jme->mii_if.phy_id, 130 MII_BMCR); 131 132 jme_mdio_write(jme->dev, 133 jme->mii_if.phy_id, 134 MII_BMCR, val | BMCR_RESET); 135 } 136 137 static void 138 jme_setup_wakeup_frame(struct jme_adapter *jme, 139 const u32 *mask, u32 crc, int fnr) 140 { 141 int i; 142 143 /* 144 * Setup CRC pattern 145 */ 146 jwrite32(jme, JME_WFOI, WFOI_CRC_SEL | (fnr & WFOI_FRAME_SEL)); 147 wmb(); 148 jwrite32(jme, JME_WFODP, crc); 149 wmb(); 150 151 /* 152 * Setup Mask 153 */ 154 for (i = 0 ; i < WAKEUP_FRAME_MASK_DWNR ; ++i) { 155 jwrite32(jme, JME_WFOI, 156 ((i << WFOI_MASK_SHIFT) & WFOI_MASK_SEL) | 157 (fnr & WFOI_FRAME_SEL)); 158 wmb(); 159 jwrite32(jme, JME_WFODP, mask[i]); 160 wmb(); 161 } 162 } 163 164 static inline void 165 jme_mac_rxclk_off(struct jme_adapter *jme) 166 { 167 jme->reg_gpreg1 |= GPREG1_RXCLKOFF; 168 jwrite32f(jme, JME_GPREG1, jme->reg_gpreg1); 169 } 170 171 static inline void 172 jme_mac_rxclk_on(struct jme_adapter *jme) 173 { 174 jme->reg_gpreg1 &= ~GPREG1_RXCLKOFF; 175 jwrite32f(jme, JME_GPREG1, jme->reg_gpreg1); 176 } 177 178 static inline void 179 jme_mac_txclk_off(struct jme_adapter *jme) 180 { 181 jme->reg_ghc &= ~(GHC_TO_CLK_SRC | GHC_TXMAC_CLK_SRC); 182 jwrite32f(jme, JME_GHC, jme->reg_ghc); 183 } 184 185 static inline void 186 jme_mac_txclk_on(struct jme_adapter *jme) 187 { 188 u32 speed = jme->reg_ghc & GHC_SPEED; 189 if (speed == GHC_SPEED_1000M) 190 jme->reg_ghc |= GHC_TO_CLK_GPHY | GHC_TXMAC_CLK_GPHY; 191 else 192 jme->reg_ghc |= GHC_TO_CLK_PCIE | GHC_TXMAC_CLK_PCIE; 193 jwrite32f(jme, JME_GHC, jme->reg_ghc); 194 } 195 196 static inline void 197 jme_reset_ghc_speed(struct jme_adapter *jme) 198 { 199 jme->reg_ghc &= ~(GHC_SPEED | GHC_DPX); 200 jwrite32f(jme, JME_GHC, jme->reg_ghc); 201 } 202 203 static inline void 204 jme_reset_250A2_workaround(struct jme_adapter *jme) 205 { 206 jme->reg_gpreg1 &= ~(GPREG1_HALFMODEPATCH | 207 GPREG1_RSSPATCH); 208 jwrite32(jme, JME_GPREG1, jme->reg_gpreg1); 209 } 210 211 static inline void 212 jme_assert_ghc_reset(struct jme_adapter *jme) 213 { 214 jme->reg_ghc |= GHC_SWRST; 215 jwrite32f(jme, JME_GHC, jme->reg_ghc); 216 } 217 218 static inline void 219 jme_clear_ghc_reset(struct jme_adapter *jme) 220 { 221 jme->reg_ghc &= ~GHC_SWRST; 222 jwrite32f(jme, JME_GHC, jme->reg_ghc); 223 } 224 225 static inline void 226 jme_reset_mac_processor(struct jme_adapter *jme) 227 { 228 static const u32 mask[WAKEUP_FRAME_MASK_DWNR] = {0, 0, 0, 0}; 229 u32 crc = 0xCDCDCDCD; 230 u32 gpreg0; 231 int i; 232 233 jme_reset_ghc_speed(jme); 234 jme_reset_250A2_workaround(jme); 235 236 jme_mac_rxclk_on(jme); 237 jme_mac_txclk_on(jme); 238 udelay(1); 239 jme_assert_ghc_reset(jme); 240 udelay(1); 241 jme_mac_rxclk_off(jme); 242 jme_mac_txclk_off(jme); 243 udelay(1); 244 jme_clear_ghc_reset(jme); 245 udelay(1); 246 jme_mac_rxclk_on(jme); 247 jme_mac_txclk_on(jme); 248 udelay(1); 249 jme_mac_rxclk_off(jme); 250 jme_mac_txclk_off(jme); 251 252 jwrite32(jme, JME_RXDBA_LO, 0x00000000); 253 jwrite32(jme, JME_RXDBA_HI, 0x00000000); 254 jwrite32(jme, JME_RXQDC, 0x00000000); 255 jwrite32(jme, JME_RXNDA, 0x00000000); 256 jwrite32(jme, JME_TXDBA_LO, 0x00000000); 257 jwrite32(jme, JME_TXDBA_HI, 0x00000000); 258 jwrite32(jme, JME_TXQDC, 0x00000000); 259 jwrite32(jme, JME_TXNDA, 0x00000000); 260 261 jwrite32(jme, JME_RXMCHT_LO, 0x00000000); 262 jwrite32(jme, JME_RXMCHT_HI, 0x00000000); 263 for (i = 0 ; i < WAKEUP_FRAME_NR ; ++i) 264 jme_setup_wakeup_frame(jme, mask, crc, i); 265 if (jme->fpgaver) 266 gpreg0 = GPREG0_DEFAULT | GPREG0_LNKINTPOLL; 267 else 268 gpreg0 = GPREG0_DEFAULT; 269 jwrite32(jme, JME_GPREG0, gpreg0); 270 } 271 272 static inline void 273 jme_clear_pm(struct jme_adapter *jme) 274 { 275 jwrite32(jme, JME_PMCS, PMCS_STMASK | jme->reg_pmcs); 276 } 277 278 static int 279 jme_reload_eeprom(struct jme_adapter *jme) 280 { 281 u32 val; 282 int i; 283 284 val = jread32(jme, JME_SMBCSR); 285 286 if (val & SMBCSR_EEPROMD) { 287 val |= SMBCSR_CNACK; 288 jwrite32(jme, JME_SMBCSR, val); 289 val |= SMBCSR_RELOAD; 290 jwrite32(jme, JME_SMBCSR, val); 291 mdelay(12); 292 293 for (i = JME_EEPROM_RELOAD_TIMEOUT; i > 0; --i) { 294 mdelay(1); 295 if ((jread32(jme, JME_SMBCSR) & SMBCSR_RELOAD) == 0) 296 break; 297 } 298 299 if (i == 0) { 300 pr_err("eeprom reload timeout\n"); 301 return -EIO; 302 } 303 } 304 305 return 0; 306 } 307 308 static void 309 jme_load_macaddr(struct net_device *netdev) 310 { 311 struct jme_adapter *jme = netdev_priv(netdev); 312 unsigned char macaddr[ETH_ALEN]; 313 u32 val; 314 315 spin_lock_bh(&jme->macaddr_lock); 316 val = jread32(jme, JME_RXUMA_LO); 317 macaddr[0] = (val >> 0) & 0xFF; 318 macaddr[1] = (val >> 8) & 0xFF; 319 macaddr[2] = (val >> 16) & 0xFF; 320 macaddr[3] = (val >> 24) & 0xFF; 321 val = jread32(jme, JME_RXUMA_HI); 322 macaddr[4] = (val >> 0) & 0xFF; 323 macaddr[5] = (val >> 8) & 0xFF; 324 memcpy(netdev->dev_addr, macaddr, ETH_ALEN); 325 spin_unlock_bh(&jme->macaddr_lock); 326 } 327 328 static inline void 329 jme_set_rx_pcc(struct jme_adapter *jme, int p) 330 { 331 switch (p) { 332 case PCC_OFF: 333 jwrite32(jme, JME_PCCRX0, 334 ((PCC_OFF_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) | 335 ((PCC_OFF_CNT << PCCRX_SHIFT) & PCCRX_MASK)); 336 break; 337 case PCC_P1: 338 jwrite32(jme, JME_PCCRX0, 339 ((PCC_P1_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) | 340 ((PCC_P1_CNT << PCCRX_SHIFT) & PCCRX_MASK)); 341 break; 342 case PCC_P2: 343 jwrite32(jme, JME_PCCRX0, 344 ((PCC_P2_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) | 345 ((PCC_P2_CNT << PCCRX_SHIFT) & PCCRX_MASK)); 346 break; 347 case PCC_P3: 348 jwrite32(jme, JME_PCCRX0, 349 ((PCC_P3_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) | 350 ((PCC_P3_CNT << PCCRX_SHIFT) & PCCRX_MASK)); 351 break; 352 default: 353 break; 354 } 355 wmb(); 356 357 if (!(test_bit(JME_FLAG_POLL, &jme->flags))) 358 netif_info(jme, rx_status, jme->dev, "Switched to PCC_P%d\n", p); 359 } 360 361 static void 362 jme_start_irq(struct jme_adapter *jme) 363 { 364 register struct dynpcc_info *dpi = &(jme->dpi); 365 366 jme_set_rx_pcc(jme, PCC_P1); 367 dpi->cur = PCC_P1; 368 dpi->attempt = PCC_P1; 369 dpi->cnt = 0; 370 371 jwrite32(jme, JME_PCCTX, 372 ((PCC_TX_TO << PCCTXTO_SHIFT) & PCCTXTO_MASK) | 373 ((PCC_TX_CNT << PCCTX_SHIFT) & PCCTX_MASK) | 374 PCCTXQ0_EN 375 ); 376 377 /* 378 * Enable Interrupts 379 */ 380 jwrite32(jme, JME_IENS, INTR_ENABLE); 381 } 382 383 static inline void 384 jme_stop_irq(struct jme_adapter *jme) 385 { 386 /* 387 * Disable Interrupts 388 */ 389 jwrite32f(jme, JME_IENC, INTR_ENABLE); 390 } 391 392 static u32 393 jme_linkstat_from_phy(struct jme_adapter *jme) 394 { 395 u32 phylink, bmsr; 396 397 phylink = jme_mdio_read(jme->dev, jme->mii_if.phy_id, 17); 398 bmsr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMSR); 399 if (bmsr & BMSR_ANCOMP) 400 phylink |= PHY_LINK_AUTONEG_COMPLETE; 401 402 return phylink; 403 } 404 405 static inline void 406 jme_set_phyfifo_5level(struct jme_adapter *jme) 407 { 408 jme_mdio_write(jme->dev, jme->mii_if.phy_id, 27, 0x0004); 409 } 410 411 static inline void 412 jme_set_phyfifo_8level(struct jme_adapter *jme) 413 { 414 jme_mdio_write(jme->dev, jme->mii_if.phy_id, 27, 0x0000); 415 } 416 417 static int 418 jme_check_link(struct net_device *netdev, int testonly) 419 { 420 struct jme_adapter *jme = netdev_priv(netdev); 421 u32 phylink, cnt = JME_SPDRSV_TIMEOUT, bmcr; 422 char linkmsg[64]; 423 int rc = 0; 424 425 linkmsg[0] = '\0'; 426 427 if (jme->fpgaver) 428 phylink = jme_linkstat_from_phy(jme); 429 else 430 phylink = jread32(jme, JME_PHY_LINK); 431 432 if (phylink & PHY_LINK_UP) { 433 if (!(phylink & PHY_LINK_AUTONEG_COMPLETE)) { 434 /* 435 * If we did not enable AN 436 * Speed/Duplex Info should be obtained from SMI 437 */ 438 phylink = PHY_LINK_UP; 439 440 bmcr = jme_mdio_read(jme->dev, 441 jme->mii_if.phy_id, 442 MII_BMCR); 443 444 phylink |= ((bmcr & BMCR_SPEED1000) && 445 (bmcr & BMCR_SPEED100) == 0) ? 446 PHY_LINK_SPEED_1000M : 447 (bmcr & BMCR_SPEED100) ? 448 PHY_LINK_SPEED_100M : 449 PHY_LINK_SPEED_10M; 450 451 phylink |= (bmcr & BMCR_FULLDPLX) ? 452 PHY_LINK_DUPLEX : 0; 453 454 strcat(linkmsg, "Forced: "); 455 } else { 456 /* 457 * Keep polling for speed/duplex resolve complete 458 */ 459 while (!(phylink & PHY_LINK_SPEEDDPU_RESOLVED) && 460 --cnt) { 461 462 udelay(1); 463 464 if (jme->fpgaver) 465 phylink = jme_linkstat_from_phy(jme); 466 else 467 phylink = jread32(jme, JME_PHY_LINK); 468 } 469 if (!cnt) 470 pr_err("Waiting speed resolve timeout\n"); 471 472 strcat(linkmsg, "ANed: "); 473 } 474 475 if (jme->phylink == phylink) { 476 rc = 1; 477 goto out; 478 } 479 if (testonly) 480 goto out; 481 482 jme->phylink = phylink; 483 484 /* 485 * The speed/duplex setting of jme->reg_ghc already cleared 486 * by jme_reset_mac_processor() 487 */ 488 switch (phylink & PHY_LINK_SPEED_MASK) { 489 case PHY_LINK_SPEED_10M: 490 jme->reg_ghc |= GHC_SPEED_10M; 491 strcat(linkmsg, "10 Mbps, "); 492 break; 493 case PHY_LINK_SPEED_100M: 494 jme->reg_ghc |= GHC_SPEED_100M; 495 strcat(linkmsg, "100 Mbps, "); 496 break; 497 case PHY_LINK_SPEED_1000M: 498 jme->reg_ghc |= GHC_SPEED_1000M; 499 strcat(linkmsg, "1000 Mbps, "); 500 break; 501 default: 502 break; 503 } 504 505 if (phylink & PHY_LINK_DUPLEX) { 506 jwrite32(jme, JME_TXMCS, TXMCS_DEFAULT); 507 jwrite32(jme, JME_TXTRHD, TXTRHD_FULLDUPLEX); 508 jme->reg_ghc |= GHC_DPX; 509 } else { 510 jwrite32(jme, JME_TXMCS, TXMCS_DEFAULT | 511 TXMCS_BACKOFF | 512 TXMCS_CARRIERSENSE | 513 TXMCS_COLLISION); 514 jwrite32(jme, JME_TXTRHD, TXTRHD_HALFDUPLEX); 515 } 516 517 jwrite32(jme, JME_GHC, jme->reg_ghc); 518 519 if (is_buggy250(jme->pdev->device, jme->chiprev)) { 520 jme->reg_gpreg1 &= ~(GPREG1_HALFMODEPATCH | 521 GPREG1_RSSPATCH); 522 if (!(phylink & PHY_LINK_DUPLEX)) 523 jme->reg_gpreg1 |= GPREG1_HALFMODEPATCH; 524 switch (phylink & PHY_LINK_SPEED_MASK) { 525 case PHY_LINK_SPEED_10M: 526 jme_set_phyfifo_8level(jme); 527 jme->reg_gpreg1 |= GPREG1_RSSPATCH; 528 break; 529 case PHY_LINK_SPEED_100M: 530 jme_set_phyfifo_5level(jme); 531 jme->reg_gpreg1 |= GPREG1_RSSPATCH; 532 break; 533 case PHY_LINK_SPEED_1000M: 534 jme_set_phyfifo_8level(jme); 535 break; 536 default: 537 break; 538 } 539 } 540 jwrite32(jme, JME_GPREG1, jme->reg_gpreg1); 541 542 strcat(linkmsg, (phylink & PHY_LINK_DUPLEX) ? 543 "Full-Duplex, " : 544 "Half-Duplex, "); 545 strcat(linkmsg, (phylink & PHY_LINK_MDI_STAT) ? 546 "MDI-X" : 547 "MDI"); 548 netif_info(jme, link, jme->dev, "Link is up at %s\n", linkmsg); 549 netif_carrier_on(netdev); 550 } else { 551 if (testonly) 552 goto out; 553 554 netif_info(jme, link, jme->dev, "Link is down\n"); 555 jme->phylink = 0; 556 netif_carrier_off(netdev); 557 } 558 559 out: 560 return rc; 561 } 562 563 static int 564 jme_setup_tx_resources(struct jme_adapter *jme) 565 { 566 struct jme_ring *txring = &(jme->txring[0]); 567 568 txring->alloc = dma_alloc_coherent(&(jme->pdev->dev), 569 TX_RING_ALLOC_SIZE(jme->tx_ring_size), 570 &(txring->dmaalloc), 571 GFP_ATOMIC); 572 573 if (!txring->alloc) 574 goto err_set_null; 575 576 /* 577 * 16 Bytes align 578 */ 579 txring->desc = (void *)ALIGN((unsigned long)(txring->alloc), 580 RING_DESC_ALIGN); 581 txring->dma = ALIGN(txring->dmaalloc, RING_DESC_ALIGN); 582 txring->next_to_use = 0; 583 atomic_set(&txring->next_to_clean, 0); 584 atomic_set(&txring->nr_free, jme->tx_ring_size); 585 586 txring->bufinf = kzalloc(sizeof(struct jme_buffer_info) * 587 jme->tx_ring_size, GFP_ATOMIC); 588 if (unlikely(!(txring->bufinf))) 589 goto err_free_txring; 590 591 /* 592 * Initialize Transmit Descriptors 593 */ 594 memset(txring->alloc, 0, TX_RING_ALLOC_SIZE(jme->tx_ring_size)); 595 596 return 0; 597 598 err_free_txring: 599 dma_free_coherent(&(jme->pdev->dev), 600 TX_RING_ALLOC_SIZE(jme->tx_ring_size), 601 txring->alloc, 602 txring->dmaalloc); 603 604 err_set_null: 605 txring->desc = NULL; 606 txring->dmaalloc = 0; 607 txring->dma = 0; 608 txring->bufinf = NULL; 609 610 return -ENOMEM; 611 } 612 613 static void 614 jme_free_tx_resources(struct jme_adapter *jme) 615 { 616 int i; 617 struct jme_ring *txring = &(jme->txring[0]); 618 struct jme_buffer_info *txbi; 619 620 if (txring->alloc) { 621 if (txring->bufinf) { 622 for (i = 0 ; i < jme->tx_ring_size ; ++i) { 623 txbi = txring->bufinf + i; 624 if (txbi->skb) { 625 dev_kfree_skb(txbi->skb); 626 txbi->skb = NULL; 627 } 628 txbi->mapping = 0; 629 txbi->len = 0; 630 txbi->nr_desc = 0; 631 txbi->start_xmit = 0; 632 } 633 kfree(txring->bufinf); 634 } 635 636 dma_free_coherent(&(jme->pdev->dev), 637 TX_RING_ALLOC_SIZE(jme->tx_ring_size), 638 txring->alloc, 639 txring->dmaalloc); 640 641 txring->alloc = NULL; 642 txring->desc = NULL; 643 txring->dmaalloc = 0; 644 txring->dma = 0; 645 txring->bufinf = NULL; 646 } 647 txring->next_to_use = 0; 648 atomic_set(&txring->next_to_clean, 0); 649 atomic_set(&txring->nr_free, 0); 650 } 651 652 static inline void 653 jme_enable_tx_engine(struct jme_adapter *jme) 654 { 655 /* 656 * Select Queue 0 657 */ 658 jwrite32(jme, JME_TXCS, TXCS_DEFAULT | TXCS_SELECT_QUEUE0); 659 wmb(); 660 661 /* 662 * Setup TX Queue 0 DMA Bass Address 663 */ 664 jwrite32(jme, JME_TXDBA_LO, (__u64)jme->txring[0].dma & 0xFFFFFFFFUL); 665 jwrite32(jme, JME_TXDBA_HI, (__u64)(jme->txring[0].dma) >> 32); 666 jwrite32(jme, JME_TXNDA, (__u64)jme->txring[0].dma & 0xFFFFFFFFUL); 667 668 /* 669 * Setup TX Descptor Count 670 */ 671 jwrite32(jme, JME_TXQDC, jme->tx_ring_size); 672 673 /* 674 * Enable TX Engine 675 */ 676 wmb(); 677 jwrite32f(jme, JME_TXCS, jme->reg_txcs | 678 TXCS_SELECT_QUEUE0 | 679 TXCS_ENABLE); 680 681 /* 682 * Start clock for TX MAC Processor 683 */ 684 jme_mac_txclk_on(jme); 685 } 686 687 static inline void 688 jme_restart_tx_engine(struct jme_adapter *jme) 689 { 690 /* 691 * Restart TX Engine 692 */ 693 jwrite32(jme, JME_TXCS, jme->reg_txcs | 694 TXCS_SELECT_QUEUE0 | 695 TXCS_ENABLE); 696 } 697 698 static inline void 699 jme_disable_tx_engine(struct jme_adapter *jme) 700 { 701 int i; 702 u32 val; 703 704 /* 705 * Disable TX Engine 706 */ 707 jwrite32(jme, JME_TXCS, jme->reg_txcs | TXCS_SELECT_QUEUE0); 708 wmb(); 709 710 val = jread32(jme, JME_TXCS); 711 for (i = JME_TX_DISABLE_TIMEOUT ; (val & TXCS_ENABLE) && i > 0 ; --i) { 712 mdelay(1); 713 val = jread32(jme, JME_TXCS); 714 rmb(); 715 } 716 717 if (!i) 718 pr_err("Disable TX engine timeout\n"); 719 720 /* 721 * Stop clock for TX MAC Processor 722 */ 723 jme_mac_txclk_off(jme); 724 } 725 726 static void 727 jme_set_clean_rxdesc(struct jme_adapter *jme, int i) 728 { 729 struct jme_ring *rxring = &(jme->rxring[0]); 730 register struct rxdesc *rxdesc = rxring->desc; 731 struct jme_buffer_info *rxbi = rxring->bufinf; 732 rxdesc += i; 733 rxbi += i; 734 735 rxdesc->dw[0] = 0; 736 rxdesc->dw[1] = 0; 737 rxdesc->desc1.bufaddrh = cpu_to_le32((__u64)rxbi->mapping >> 32); 738 rxdesc->desc1.bufaddrl = cpu_to_le32( 739 (__u64)rxbi->mapping & 0xFFFFFFFFUL); 740 rxdesc->desc1.datalen = cpu_to_le16(rxbi->len); 741 if (jme->dev->features & NETIF_F_HIGHDMA) 742 rxdesc->desc1.flags = RXFLAG_64BIT; 743 wmb(); 744 rxdesc->desc1.flags |= RXFLAG_OWN | RXFLAG_INT; 745 } 746 747 static int 748 jme_make_new_rx_buf(struct jme_adapter *jme, int i) 749 { 750 struct jme_ring *rxring = &(jme->rxring[0]); 751 struct jme_buffer_info *rxbi = rxring->bufinf + i; 752 struct sk_buff *skb; 753 dma_addr_t mapping; 754 755 skb = netdev_alloc_skb(jme->dev, 756 jme->dev->mtu + RX_EXTRA_LEN); 757 if (unlikely(!skb)) 758 return -ENOMEM; 759 760 mapping = pci_map_page(jme->pdev, virt_to_page(skb->data), 761 offset_in_page(skb->data), skb_tailroom(skb), 762 PCI_DMA_FROMDEVICE); 763 if (unlikely(pci_dma_mapping_error(jme->pdev, mapping))) { 764 dev_kfree_skb(skb); 765 return -ENOMEM; 766 } 767 768 if (likely(rxbi->mapping)) 769 pci_unmap_page(jme->pdev, rxbi->mapping, 770 rxbi->len, PCI_DMA_FROMDEVICE); 771 772 rxbi->skb = skb; 773 rxbi->len = skb_tailroom(skb); 774 rxbi->mapping = mapping; 775 return 0; 776 } 777 778 static void 779 jme_free_rx_buf(struct jme_adapter *jme, int i) 780 { 781 struct jme_ring *rxring = &(jme->rxring[0]); 782 struct jme_buffer_info *rxbi = rxring->bufinf; 783 rxbi += i; 784 785 if (rxbi->skb) { 786 pci_unmap_page(jme->pdev, 787 rxbi->mapping, 788 rxbi->len, 789 PCI_DMA_FROMDEVICE); 790 dev_kfree_skb(rxbi->skb); 791 rxbi->skb = NULL; 792 rxbi->mapping = 0; 793 rxbi->len = 0; 794 } 795 } 796 797 static void 798 jme_free_rx_resources(struct jme_adapter *jme) 799 { 800 int i; 801 struct jme_ring *rxring = &(jme->rxring[0]); 802 803 if (rxring->alloc) { 804 if (rxring->bufinf) { 805 for (i = 0 ; i < jme->rx_ring_size ; ++i) 806 jme_free_rx_buf(jme, i); 807 kfree(rxring->bufinf); 808 } 809 810 dma_free_coherent(&(jme->pdev->dev), 811 RX_RING_ALLOC_SIZE(jme->rx_ring_size), 812 rxring->alloc, 813 rxring->dmaalloc); 814 rxring->alloc = NULL; 815 rxring->desc = NULL; 816 rxring->dmaalloc = 0; 817 rxring->dma = 0; 818 rxring->bufinf = NULL; 819 } 820 rxring->next_to_use = 0; 821 atomic_set(&rxring->next_to_clean, 0); 822 } 823 824 static int 825 jme_setup_rx_resources(struct jme_adapter *jme) 826 { 827 int i; 828 struct jme_ring *rxring = &(jme->rxring[0]); 829 830 rxring->alloc = dma_alloc_coherent(&(jme->pdev->dev), 831 RX_RING_ALLOC_SIZE(jme->rx_ring_size), 832 &(rxring->dmaalloc), 833 GFP_ATOMIC); 834 if (!rxring->alloc) 835 goto err_set_null; 836 837 /* 838 * 16 Bytes align 839 */ 840 rxring->desc = (void *)ALIGN((unsigned long)(rxring->alloc), 841 RING_DESC_ALIGN); 842 rxring->dma = ALIGN(rxring->dmaalloc, RING_DESC_ALIGN); 843 rxring->next_to_use = 0; 844 atomic_set(&rxring->next_to_clean, 0); 845 846 rxring->bufinf = kzalloc(sizeof(struct jme_buffer_info) * 847 jme->rx_ring_size, GFP_ATOMIC); 848 if (unlikely(!(rxring->bufinf))) 849 goto err_free_rxring; 850 851 /* 852 * Initiallize Receive Descriptors 853 */ 854 for (i = 0 ; i < jme->rx_ring_size ; ++i) { 855 if (unlikely(jme_make_new_rx_buf(jme, i))) { 856 jme_free_rx_resources(jme); 857 return -ENOMEM; 858 } 859 860 jme_set_clean_rxdesc(jme, i); 861 } 862 863 return 0; 864 865 err_free_rxring: 866 dma_free_coherent(&(jme->pdev->dev), 867 RX_RING_ALLOC_SIZE(jme->rx_ring_size), 868 rxring->alloc, 869 rxring->dmaalloc); 870 err_set_null: 871 rxring->desc = NULL; 872 rxring->dmaalloc = 0; 873 rxring->dma = 0; 874 rxring->bufinf = NULL; 875 876 return -ENOMEM; 877 } 878 879 static inline void 880 jme_enable_rx_engine(struct jme_adapter *jme) 881 { 882 /* 883 * Select Queue 0 884 */ 885 jwrite32(jme, JME_RXCS, jme->reg_rxcs | 886 RXCS_QUEUESEL_Q0); 887 wmb(); 888 889 /* 890 * Setup RX DMA Bass Address 891 */ 892 jwrite32(jme, JME_RXDBA_LO, (__u64)(jme->rxring[0].dma) & 0xFFFFFFFFUL); 893 jwrite32(jme, JME_RXDBA_HI, (__u64)(jme->rxring[0].dma) >> 32); 894 jwrite32(jme, JME_RXNDA, (__u64)(jme->rxring[0].dma) & 0xFFFFFFFFUL); 895 896 /* 897 * Setup RX Descriptor Count 898 */ 899 jwrite32(jme, JME_RXQDC, jme->rx_ring_size); 900 901 /* 902 * Setup Unicast Filter 903 */ 904 jme_set_unicastaddr(jme->dev); 905 jme_set_multi(jme->dev); 906 907 /* 908 * Enable RX Engine 909 */ 910 wmb(); 911 jwrite32f(jme, JME_RXCS, jme->reg_rxcs | 912 RXCS_QUEUESEL_Q0 | 913 RXCS_ENABLE | 914 RXCS_QST); 915 916 /* 917 * Start clock for RX MAC Processor 918 */ 919 jme_mac_rxclk_on(jme); 920 } 921 922 static inline void 923 jme_restart_rx_engine(struct jme_adapter *jme) 924 { 925 /* 926 * Start RX Engine 927 */ 928 jwrite32(jme, JME_RXCS, jme->reg_rxcs | 929 RXCS_QUEUESEL_Q0 | 930 RXCS_ENABLE | 931 RXCS_QST); 932 } 933 934 static inline void 935 jme_disable_rx_engine(struct jme_adapter *jme) 936 { 937 int i; 938 u32 val; 939 940 /* 941 * Disable RX Engine 942 */ 943 jwrite32(jme, JME_RXCS, jme->reg_rxcs); 944 wmb(); 945 946 val = jread32(jme, JME_RXCS); 947 for (i = JME_RX_DISABLE_TIMEOUT ; (val & RXCS_ENABLE) && i > 0 ; --i) { 948 mdelay(1); 949 val = jread32(jme, JME_RXCS); 950 rmb(); 951 } 952 953 if (!i) 954 pr_err("Disable RX engine timeout\n"); 955 956 /* 957 * Stop clock for RX MAC Processor 958 */ 959 jme_mac_rxclk_off(jme); 960 } 961 962 static u16 963 jme_udpsum(struct sk_buff *skb) 964 { 965 u16 csum = 0xFFFFu; 966 967 if (skb->len < (ETH_HLEN + sizeof(struct iphdr))) 968 return csum; 969 if (skb->protocol != htons(ETH_P_IP)) 970 return csum; 971 skb_set_network_header(skb, ETH_HLEN); 972 if ((ip_hdr(skb)->protocol != IPPROTO_UDP) || 973 (skb->len < (ETH_HLEN + 974 (ip_hdr(skb)->ihl << 2) + 975 sizeof(struct udphdr)))) { 976 skb_reset_network_header(skb); 977 return csum; 978 } 979 skb_set_transport_header(skb, 980 ETH_HLEN + (ip_hdr(skb)->ihl << 2)); 981 csum = udp_hdr(skb)->check; 982 skb_reset_transport_header(skb); 983 skb_reset_network_header(skb); 984 985 return csum; 986 } 987 988 static int 989 jme_rxsum_ok(struct jme_adapter *jme, u16 flags, struct sk_buff *skb) 990 { 991 if (!(flags & (RXWBFLAG_TCPON | RXWBFLAG_UDPON | RXWBFLAG_IPV4))) 992 return false; 993 994 if (unlikely((flags & (RXWBFLAG_MF | RXWBFLAG_TCPON | RXWBFLAG_TCPCS)) 995 == RXWBFLAG_TCPON)) { 996 if (flags & RXWBFLAG_IPV4) 997 netif_err(jme, rx_err, jme->dev, "TCP Checksum error\n"); 998 return false; 999 } 1000 1001 if (unlikely((flags & (RXWBFLAG_MF | RXWBFLAG_UDPON | RXWBFLAG_UDPCS)) 1002 == RXWBFLAG_UDPON) && jme_udpsum(skb)) { 1003 if (flags & RXWBFLAG_IPV4) 1004 netif_err(jme, rx_err, jme->dev, "UDP Checksum error\n"); 1005 return false; 1006 } 1007 1008 if (unlikely((flags & (RXWBFLAG_IPV4 | RXWBFLAG_IPCS)) 1009 == RXWBFLAG_IPV4)) { 1010 netif_err(jme, rx_err, jme->dev, "IPv4 Checksum error\n"); 1011 return false; 1012 } 1013 1014 return true; 1015 } 1016 1017 static void 1018 jme_alloc_and_feed_skb(struct jme_adapter *jme, int idx) 1019 { 1020 struct jme_ring *rxring = &(jme->rxring[0]); 1021 struct rxdesc *rxdesc = rxring->desc; 1022 struct jme_buffer_info *rxbi = rxring->bufinf; 1023 struct sk_buff *skb; 1024 int framesize; 1025 1026 rxdesc += idx; 1027 rxbi += idx; 1028 1029 skb = rxbi->skb; 1030 pci_dma_sync_single_for_cpu(jme->pdev, 1031 rxbi->mapping, 1032 rxbi->len, 1033 PCI_DMA_FROMDEVICE); 1034 1035 if (unlikely(jme_make_new_rx_buf(jme, idx))) { 1036 pci_dma_sync_single_for_device(jme->pdev, 1037 rxbi->mapping, 1038 rxbi->len, 1039 PCI_DMA_FROMDEVICE); 1040 1041 ++(NET_STAT(jme).rx_dropped); 1042 } else { 1043 framesize = le16_to_cpu(rxdesc->descwb.framesize) 1044 - RX_PREPAD_SIZE; 1045 1046 skb_reserve(skb, RX_PREPAD_SIZE); 1047 skb_put(skb, framesize); 1048 skb->protocol = eth_type_trans(skb, jme->dev); 1049 1050 if (jme_rxsum_ok(jme, le16_to_cpu(rxdesc->descwb.flags), skb)) 1051 skb->ip_summed = CHECKSUM_UNNECESSARY; 1052 else 1053 skb_checksum_none_assert(skb); 1054 1055 if (rxdesc->descwb.flags & cpu_to_le16(RXWBFLAG_TAGON)) { 1056 u16 vid = le16_to_cpu(rxdesc->descwb.vlan); 1057 1058 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vid); 1059 NET_STAT(jme).rx_bytes += 4; 1060 } 1061 jme->jme_rx(skb); 1062 1063 if ((rxdesc->descwb.flags & cpu_to_le16(RXWBFLAG_DEST)) == 1064 cpu_to_le16(RXWBFLAG_DEST_MUL)) 1065 ++(NET_STAT(jme).multicast); 1066 1067 NET_STAT(jme).rx_bytes += framesize; 1068 ++(NET_STAT(jme).rx_packets); 1069 } 1070 1071 jme_set_clean_rxdesc(jme, idx); 1072 1073 } 1074 1075 static int 1076 jme_process_receive(struct jme_adapter *jme, int limit) 1077 { 1078 struct jme_ring *rxring = &(jme->rxring[0]); 1079 struct rxdesc *rxdesc = rxring->desc; 1080 int i, j, ccnt, desccnt, mask = jme->rx_ring_mask; 1081 1082 if (unlikely(!atomic_dec_and_test(&jme->rx_cleaning))) 1083 goto out_inc; 1084 1085 if (unlikely(atomic_read(&jme->link_changing) != 1)) 1086 goto out_inc; 1087 1088 if (unlikely(!netif_carrier_ok(jme->dev))) 1089 goto out_inc; 1090 1091 i = atomic_read(&rxring->next_to_clean); 1092 while (limit > 0) { 1093 rxdesc = rxring->desc; 1094 rxdesc += i; 1095 1096 if ((rxdesc->descwb.flags & cpu_to_le16(RXWBFLAG_OWN)) || 1097 !(rxdesc->descwb.desccnt & RXWBDCNT_WBCPL)) 1098 goto out; 1099 --limit; 1100 1101 rmb(); 1102 desccnt = rxdesc->descwb.desccnt & RXWBDCNT_DCNT; 1103 1104 if (unlikely(desccnt > 1 || 1105 rxdesc->descwb.errstat & RXWBERR_ALLERR)) { 1106 1107 if (rxdesc->descwb.errstat & RXWBERR_CRCERR) 1108 ++(NET_STAT(jme).rx_crc_errors); 1109 else if (rxdesc->descwb.errstat & RXWBERR_OVERUN) 1110 ++(NET_STAT(jme).rx_fifo_errors); 1111 else 1112 ++(NET_STAT(jme).rx_errors); 1113 1114 if (desccnt > 1) 1115 limit -= desccnt - 1; 1116 1117 for (j = i, ccnt = desccnt ; ccnt-- ; ) { 1118 jme_set_clean_rxdesc(jme, j); 1119 j = (j + 1) & (mask); 1120 } 1121 1122 } else { 1123 jme_alloc_and_feed_skb(jme, i); 1124 } 1125 1126 i = (i + desccnt) & (mask); 1127 } 1128 1129 out: 1130 atomic_set(&rxring->next_to_clean, i); 1131 1132 out_inc: 1133 atomic_inc(&jme->rx_cleaning); 1134 1135 return limit > 0 ? limit : 0; 1136 1137 } 1138 1139 static void 1140 jme_attempt_pcc(struct dynpcc_info *dpi, int atmp) 1141 { 1142 if (likely(atmp == dpi->cur)) { 1143 dpi->cnt = 0; 1144 return; 1145 } 1146 1147 if (dpi->attempt == atmp) { 1148 ++(dpi->cnt); 1149 } else { 1150 dpi->attempt = atmp; 1151 dpi->cnt = 0; 1152 } 1153 1154 } 1155 1156 static void 1157 jme_dynamic_pcc(struct jme_adapter *jme) 1158 { 1159 register struct dynpcc_info *dpi = &(jme->dpi); 1160 1161 if ((NET_STAT(jme).rx_bytes - dpi->last_bytes) > PCC_P3_THRESHOLD) 1162 jme_attempt_pcc(dpi, PCC_P3); 1163 else if ((NET_STAT(jme).rx_packets - dpi->last_pkts) > PCC_P2_THRESHOLD || 1164 dpi->intr_cnt > PCC_INTR_THRESHOLD) 1165 jme_attempt_pcc(dpi, PCC_P2); 1166 else 1167 jme_attempt_pcc(dpi, PCC_P1); 1168 1169 if (unlikely(dpi->attempt != dpi->cur && dpi->cnt > 5)) { 1170 if (dpi->attempt < dpi->cur) 1171 tasklet_schedule(&jme->rxclean_task); 1172 jme_set_rx_pcc(jme, dpi->attempt); 1173 dpi->cur = dpi->attempt; 1174 dpi->cnt = 0; 1175 } 1176 } 1177 1178 static void 1179 jme_start_pcc_timer(struct jme_adapter *jme) 1180 { 1181 struct dynpcc_info *dpi = &(jme->dpi); 1182 dpi->last_bytes = NET_STAT(jme).rx_bytes; 1183 dpi->last_pkts = NET_STAT(jme).rx_packets; 1184 dpi->intr_cnt = 0; 1185 jwrite32(jme, JME_TMCSR, 1186 TMCSR_EN | ((0xFFFFFF - PCC_INTERVAL_US) & TMCSR_CNT)); 1187 } 1188 1189 static inline void 1190 jme_stop_pcc_timer(struct jme_adapter *jme) 1191 { 1192 jwrite32(jme, JME_TMCSR, 0); 1193 } 1194 1195 static void 1196 jme_shutdown_nic(struct jme_adapter *jme) 1197 { 1198 u32 phylink; 1199 1200 phylink = jme_linkstat_from_phy(jme); 1201 1202 if (!(phylink & PHY_LINK_UP)) { 1203 /* 1204 * Disable all interrupt before issue timer 1205 */ 1206 jme_stop_irq(jme); 1207 jwrite32(jme, JME_TIMER2, TMCSR_EN | 0xFFFFFE); 1208 } 1209 } 1210 1211 static void 1212 jme_pcc_tasklet(unsigned long arg) 1213 { 1214 struct jme_adapter *jme = (struct jme_adapter *)arg; 1215 struct net_device *netdev = jme->dev; 1216 1217 if (unlikely(test_bit(JME_FLAG_SHUTDOWN, &jme->flags))) { 1218 jme_shutdown_nic(jme); 1219 return; 1220 } 1221 1222 if (unlikely(!netif_carrier_ok(netdev) || 1223 (atomic_read(&jme->link_changing) != 1) 1224 )) { 1225 jme_stop_pcc_timer(jme); 1226 return; 1227 } 1228 1229 if (!(test_bit(JME_FLAG_POLL, &jme->flags))) 1230 jme_dynamic_pcc(jme); 1231 1232 jme_start_pcc_timer(jme); 1233 } 1234 1235 static inline void 1236 jme_polling_mode(struct jme_adapter *jme) 1237 { 1238 jme_set_rx_pcc(jme, PCC_OFF); 1239 } 1240 1241 static inline void 1242 jme_interrupt_mode(struct jme_adapter *jme) 1243 { 1244 jme_set_rx_pcc(jme, PCC_P1); 1245 } 1246 1247 static inline int 1248 jme_pseudo_hotplug_enabled(struct jme_adapter *jme) 1249 { 1250 u32 apmc; 1251 apmc = jread32(jme, JME_APMC); 1252 return apmc & JME_APMC_PSEUDO_HP_EN; 1253 } 1254 1255 static void 1256 jme_start_shutdown_timer(struct jme_adapter *jme) 1257 { 1258 u32 apmc; 1259 1260 apmc = jread32(jme, JME_APMC) | JME_APMC_PCIE_SD_EN; 1261 apmc &= ~JME_APMC_EPIEN_CTRL; 1262 if (!no_extplug) { 1263 jwrite32f(jme, JME_APMC, apmc | JME_APMC_EPIEN_CTRL_EN); 1264 wmb(); 1265 } 1266 jwrite32f(jme, JME_APMC, apmc); 1267 1268 jwrite32f(jme, JME_TIMER2, 0); 1269 set_bit(JME_FLAG_SHUTDOWN, &jme->flags); 1270 jwrite32(jme, JME_TMCSR, 1271 TMCSR_EN | ((0xFFFFFF - APMC_PHP_SHUTDOWN_DELAY) & TMCSR_CNT)); 1272 } 1273 1274 static void 1275 jme_stop_shutdown_timer(struct jme_adapter *jme) 1276 { 1277 u32 apmc; 1278 1279 jwrite32f(jme, JME_TMCSR, 0); 1280 jwrite32f(jme, JME_TIMER2, 0); 1281 clear_bit(JME_FLAG_SHUTDOWN, &jme->flags); 1282 1283 apmc = jread32(jme, JME_APMC); 1284 apmc &= ~(JME_APMC_PCIE_SD_EN | JME_APMC_EPIEN_CTRL); 1285 jwrite32f(jme, JME_APMC, apmc | JME_APMC_EPIEN_CTRL_DIS); 1286 wmb(); 1287 jwrite32f(jme, JME_APMC, apmc); 1288 } 1289 1290 static void 1291 jme_link_change_tasklet(unsigned long arg) 1292 { 1293 struct jme_adapter *jme = (struct jme_adapter *)arg; 1294 struct net_device *netdev = jme->dev; 1295 int rc; 1296 1297 while (!atomic_dec_and_test(&jme->link_changing)) { 1298 atomic_inc(&jme->link_changing); 1299 netif_info(jme, intr, jme->dev, "Get link change lock failed\n"); 1300 while (atomic_read(&jme->link_changing) != 1) 1301 netif_info(jme, intr, jme->dev, "Waiting link change lock\n"); 1302 } 1303 1304 if (jme_check_link(netdev, 1) && jme->old_mtu == netdev->mtu) 1305 goto out; 1306 1307 jme->old_mtu = netdev->mtu; 1308 netif_stop_queue(netdev); 1309 if (jme_pseudo_hotplug_enabled(jme)) 1310 jme_stop_shutdown_timer(jme); 1311 1312 jme_stop_pcc_timer(jme); 1313 tasklet_disable(&jme->txclean_task); 1314 tasklet_disable(&jme->rxclean_task); 1315 tasklet_disable(&jme->rxempty_task); 1316 1317 if (netif_carrier_ok(netdev)) { 1318 jme_disable_rx_engine(jme); 1319 jme_disable_tx_engine(jme); 1320 jme_reset_mac_processor(jme); 1321 jme_free_rx_resources(jme); 1322 jme_free_tx_resources(jme); 1323 1324 if (test_bit(JME_FLAG_POLL, &jme->flags)) 1325 jme_polling_mode(jme); 1326 1327 netif_carrier_off(netdev); 1328 } 1329 1330 jme_check_link(netdev, 0); 1331 if (netif_carrier_ok(netdev)) { 1332 rc = jme_setup_rx_resources(jme); 1333 if (rc) { 1334 pr_err("Allocating resources for RX error, Device STOPPED!\n"); 1335 goto out_enable_tasklet; 1336 } 1337 1338 rc = jme_setup_tx_resources(jme); 1339 if (rc) { 1340 pr_err("Allocating resources for TX error, Device STOPPED!\n"); 1341 goto err_out_free_rx_resources; 1342 } 1343 1344 jme_enable_rx_engine(jme); 1345 jme_enable_tx_engine(jme); 1346 1347 netif_start_queue(netdev); 1348 1349 if (test_bit(JME_FLAG_POLL, &jme->flags)) 1350 jme_interrupt_mode(jme); 1351 1352 jme_start_pcc_timer(jme); 1353 } else if (jme_pseudo_hotplug_enabled(jme)) { 1354 jme_start_shutdown_timer(jme); 1355 } 1356 1357 goto out_enable_tasklet; 1358 1359 err_out_free_rx_resources: 1360 jme_free_rx_resources(jme); 1361 out_enable_tasklet: 1362 tasklet_enable(&jme->txclean_task); 1363 tasklet_enable(&jme->rxclean_task); 1364 tasklet_enable(&jme->rxempty_task); 1365 out: 1366 atomic_inc(&jme->link_changing); 1367 } 1368 1369 static void 1370 jme_rx_clean_tasklet(unsigned long arg) 1371 { 1372 struct jme_adapter *jme = (struct jme_adapter *)arg; 1373 struct dynpcc_info *dpi = &(jme->dpi); 1374 1375 jme_process_receive(jme, jme->rx_ring_size); 1376 ++(dpi->intr_cnt); 1377 1378 } 1379 1380 static int 1381 jme_poll(JME_NAPI_HOLDER(holder), JME_NAPI_WEIGHT(budget)) 1382 { 1383 struct jme_adapter *jme = jme_napi_priv(holder); 1384 int rest; 1385 1386 rest = jme_process_receive(jme, JME_NAPI_WEIGHT_VAL(budget)); 1387 1388 while (atomic_read(&jme->rx_empty) > 0) { 1389 atomic_dec(&jme->rx_empty); 1390 ++(NET_STAT(jme).rx_dropped); 1391 jme_restart_rx_engine(jme); 1392 } 1393 atomic_inc(&jme->rx_empty); 1394 1395 if (rest) { 1396 JME_RX_COMPLETE(netdev, holder); 1397 jme_interrupt_mode(jme); 1398 } 1399 1400 JME_NAPI_WEIGHT_SET(budget, rest); 1401 return JME_NAPI_WEIGHT_VAL(budget) - rest; 1402 } 1403 1404 static void 1405 jme_rx_empty_tasklet(unsigned long arg) 1406 { 1407 struct jme_adapter *jme = (struct jme_adapter *)arg; 1408 1409 if (unlikely(atomic_read(&jme->link_changing) != 1)) 1410 return; 1411 1412 if (unlikely(!netif_carrier_ok(jme->dev))) 1413 return; 1414 1415 netif_info(jme, rx_status, jme->dev, "RX Queue Full!\n"); 1416 1417 jme_rx_clean_tasklet(arg); 1418 1419 while (atomic_read(&jme->rx_empty) > 0) { 1420 atomic_dec(&jme->rx_empty); 1421 ++(NET_STAT(jme).rx_dropped); 1422 jme_restart_rx_engine(jme); 1423 } 1424 atomic_inc(&jme->rx_empty); 1425 } 1426 1427 static void 1428 jme_wake_queue_if_stopped(struct jme_adapter *jme) 1429 { 1430 struct jme_ring *txring = &(jme->txring[0]); 1431 1432 smp_wmb(); 1433 if (unlikely(netif_queue_stopped(jme->dev) && 1434 atomic_read(&txring->nr_free) >= (jme->tx_wake_threshold))) { 1435 netif_info(jme, tx_done, jme->dev, "TX Queue Waked\n"); 1436 netif_wake_queue(jme->dev); 1437 } 1438 1439 } 1440 1441 static void 1442 jme_tx_clean_tasklet(unsigned long arg) 1443 { 1444 struct jme_adapter *jme = (struct jme_adapter *)arg; 1445 struct jme_ring *txring = &(jme->txring[0]); 1446 struct txdesc *txdesc = txring->desc; 1447 struct jme_buffer_info *txbi = txring->bufinf, *ctxbi, *ttxbi; 1448 int i, j, cnt = 0, max, err, mask; 1449 1450 tx_dbg(jme, "Into txclean\n"); 1451 1452 if (unlikely(!atomic_dec_and_test(&jme->tx_cleaning))) 1453 goto out; 1454 1455 if (unlikely(atomic_read(&jme->link_changing) != 1)) 1456 goto out; 1457 1458 if (unlikely(!netif_carrier_ok(jme->dev))) 1459 goto out; 1460 1461 max = jme->tx_ring_size - atomic_read(&txring->nr_free); 1462 mask = jme->tx_ring_mask; 1463 1464 for (i = atomic_read(&txring->next_to_clean) ; cnt < max ; ) { 1465 1466 ctxbi = txbi + i; 1467 1468 if (likely(ctxbi->skb && 1469 !(txdesc[i].descwb.flags & TXWBFLAG_OWN))) { 1470 1471 tx_dbg(jme, "txclean: %d+%d@%lu\n", 1472 i, ctxbi->nr_desc, jiffies); 1473 1474 err = txdesc[i].descwb.flags & TXWBFLAG_ALLERR; 1475 1476 for (j = 1 ; j < ctxbi->nr_desc ; ++j) { 1477 ttxbi = txbi + ((i + j) & (mask)); 1478 txdesc[(i + j) & (mask)].dw[0] = 0; 1479 1480 pci_unmap_page(jme->pdev, 1481 ttxbi->mapping, 1482 ttxbi->len, 1483 PCI_DMA_TODEVICE); 1484 1485 ttxbi->mapping = 0; 1486 ttxbi->len = 0; 1487 } 1488 1489 dev_kfree_skb(ctxbi->skb); 1490 1491 cnt += ctxbi->nr_desc; 1492 1493 if (unlikely(err)) { 1494 ++(NET_STAT(jme).tx_carrier_errors); 1495 } else { 1496 ++(NET_STAT(jme).tx_packets); 1497 NET_STAT(jme).tx_bytes += ctxbi->len; 1498 } 1499 1500 ctxbi->skb = NULL; 1501 ctxbi->len = 0; 1502 ctxbi->start_xmit = 0; 1503 1504 } else { 1505 break; 1506 } 1507 1508 i = (i + ctxbi->nr_desc) & mask; 1509 1510 ctxbi->nr_desc = 0; 1511 } 1512 1513 tx_dbg(jme, "txclean: done %d@%lu\n", i, jiffies); 1514 atomic_set(&txring->next_to_clean, i); 1515 atomic_add(cnt, &txring->nr_free); 1516 1517 jme_wake_queue_if_stopped(jme); 1518 1519 out: 1520 atomic_inc(&jme->tx_cleaning); 1521 } 1522 1523 static void 1524 jme_intr_msi(struct jme_adapter *jme, u32 intrstat) 1525 { 1526 /* 1527 * Disable interrupt 1528 */ 1529 jwrite32f(jme, JME_IENC, INTR_ENABLE); 1530 1531 if (intrstat & (INTR_LINKCH | INTR_SWINTR)) { 1532 /* 1533 * Link change event is critical 1534 * all other events are ignored 1535 */ 1536 jwrite32(jme, JME_IEVE, intrstat); 1537 tasklet_schedule(&jme->linkch_task); 1538 goto out_reenable; 1539 } 1540 1541 if (intrstat & INTR_TMINTR) { 1542 jwrite32(jme, JME_IEVE, INTR_TMINTR); 1543 tasklet_schedule(&jme->pcc_task); 1544 } 1545 1546 if (intrstat & (INTR_PCCTXTO | INTR_PCCTX)) { 1547 jwrite32(jme, JME_IEVE, INTR_PCCTXTO | INTR_PCCTX | INTR_TX0); 1548 tasklet_schedule(&jme->txclean_task); 1549 } 1550 1551 if ((intrstat & (INTR_PCCRX0TO | INTR_PCCRX0 | INTR_RX0EMP))) { 1552 jwrite32(jme, JME_IEVE, (intrstat & (INTR_PCCRX0TO | 1553 INTR_PCCRX0 | 1554 INTR_RX0EMP)) | 1555 INTR_RX0); 1556 } 1557 1558 if (test_bit(JME_FLAG_POLL, &jme->flags)) { 1559 if (intrstat & INTR_RX0EMP) 1560 atomic_inc(&jme->rx_empty); 1561 1562 if ((intrstat & (INTR_PCCRX0TO | INTR_PCCRX0 | INTR_RX0EMP))) { 1563 if (likely(JME_RX_SCHEDULE_PREP(jme))) { 1564 jme_polling_mode(jme); 1565 JME_RX_SCHEDULE(jme); 1566 } 1567 } 1568 } else { 1569 if (intrstat & INTR_RX0EMP) { 1570 atomic_inc(&jme->rx_empty); 1571 tasklet_hi_schedule(&jme->rxempty_task); 1572 } else if (intrstat & (INTR_PCCRX0TO | INTR_PCCRX0)) { 1573 tasklet_hi_schedule(&jme->rxclean_task); 1574 } 1575 } 1576 1577 out_reenable: 1578 /* 1579 * Re-enable interrupt 1580 */ 1581 jwrite32f(jme, JME_IENS, INTR_ENABLE); 1582 } 1583 1584 static irqreturn_t 1585 jme_intr(int irq, void *dev_id) 1586 { 1587 struct net_device *netdev = dev_id; 1588 struct jme_adapter *jme = netdev_priv(netdev); 1589 u32 intrstat; 1590 1591 intrstat = jread32(jme, JME_IEVE); 1592 1593 /* 1594 * Check if it's really an interrupt for us 1595 */ 1596 if (unlikely((intrstat & INTR_ENABLE) == 0)) 1597 return IRQ_NONE; 1598 1599 /* 1600 * Check if the device still exist 1601 */ 1602 if (unlikely(intrstat == ~((typeof(intrstat))0))) 1603 return IRQ_NONE; 1604 1605 jme_intr_msi(jme, intrstat); 1606 1607 return IRQ_HANDLED; 1608 } 1609 1610 static irqreturn_t 1611 jme_msi(int irq, void *dev_id) 1612 { 1613 struct net_device *netdev = dev_id; 1614 struct jme_adapter *jme = netdev_priv(netdev); 1615 u32 intrstat; 1616 1617 intrstat = jread32(jme, JME_IEVE); 1618 1619 jme_intr_msi(jme, intrstat); 1620 1621 return IRQ_HANDLED; 1622 } 1623 1624 static void 1625 jme_reset_link(struct jme_adapter *jme) 1626 { 1627 jwrite32(jme, JME_TMCSR, TMCSR_SWIT); 1628 } 1629 1630 static void 1631 jme_restart_an(struct jme_adapter *jme) 1632 { 1633 u32 bmcr; 1634 1635 spin_lock_bh(&jme->phy_lock); 1636 bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR); 1637 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART); 1638 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, bmcr); 1639 spin_unlock_bh(&jme->phy_lock); 1640 } 1641 1642 static int 1643 jme_request_irq(struct jme_adapter *jme) 1644 { 1645 int rc; 1646 struct net_device *netdev = jme->dev; 1647 irq_handler_t handler = jme_intr; 1648 int irq_flags = IRQF_SHARED; 1649 1650 if (!pci_enable_msi(jme->pdev)) { 1651 set_bit(JME_FLAG_MSI, &jme->flags); 1652 handler = jme_msi; 1653 irq_flags = 0; 1654 } 1655 1656 rc = request_irq(jme->pdev->irq, handler, irq_flags, netdev->name, 1657 netdev); 1658 if (rc) { 1659 netdev_err(netdev, 1660 "Unable to request %s interrupt (return: %d)\n", 1661 test_bit(JME_FLAG_MSI, &jme->flags) ? "MSI" : "INTx", 1662 rc); 1663 1664 if (test_bit(JME_FLAG_MSI, &jme->flags)) { 1665 pci_disable_msi(jme->pdev); 1666 clear_bit(JME_FLAG_MSI, &jme->flags); 1667 } 1668 } else { 1669 netdev->irq = jme->pdev->irq; 1670 } 1671 1672 return rc; 1673 } 1674 1675 static void 1676 jme_free_irq(struct jme_adapter *jme) 1677 { 1678 free_irq(jme->pdev->irq, jme->dev); 1679 if (test_bit(JME_FLAG_MSI, &jme->flags)) { 1680 pci_disable_msi(jme->pdev); 1681 clear_bit(JME_FLAG_MSI, &jme->flags); 1682 jme->dev->irq = jme->pdev->irq; 1683 } 1684 } 1685 1686 static inline void 1687 jme_new_phy_on(struct jme_adapter *jme) 1688 { 1689 u32 reg; 1690 1691 reg = jread32(jme, JME_PHY_PWR); 1692 reg &= ~(PHY_PWR_DWN1SEL | PHY_PWR_DWN1SW | 1693 PHY_PWR_DWN2 | PHY_PWR_CLKSEL); 1694 jwrite32(jme, JME_PHY_PWR, reg); 1695 1696 pci_read_config_dword(jme->pdev, PCI_PRIV_PE1, ®); 1697 reg &= ~PE1_GPREG0_PBG; 1698 reg |= PE1_GPREG0_ENBG; 1699 pci_write_config_dword(jme->pdev, PCI_PRIV_PE1, reg); 1700 } 1701 1702 static inline void 1703 jme_new_phy_off(struct jme_adapter *jme) 1704 { 1705 u32 reg; 1706 1707 reg = jread32(jme, JME_PHY_PWR); 1708 reg |= PHY_PWR_DWN1SEL | PHY_PWR_DWN1SW | 1709 PHY_PWR_DWN2 | PHY_PWR_CLKSEL; 1710 jwrite32(jme, JME_PHY_PWR, reg); 1711 1712 pci_read_config_dword(jme->pdev, PCI_PRIV_PE1, ®); 1713 reg &= ~PE1_GPREG0_PBG; 1714 reg |= PE1_GPREG0_PDD3COLD; 1715 pci_write_config_dword(jme->pdev, PCI_PRIV_PE1, reg); 1716 } 1717 1718 static inline void 1719 jme_phy_on(struct jme_adapter *jme) 1720 { 1721 u32 bmcr; 1722 1723 bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR); 1724 bmcr &= ~BMCR_PDOWN; 1725 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, bmcr); 1726 1727 if (new_phy_power_ctrl(jme->chip_main_rev)) 1728 jme_new_phy_on(jme); 1729 } 1730 1731 static inline void 1732 jme_phy_off(struct jme_adapter *jme) 1733 { 1734 u32 bmcr; 1735 1736 bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR); 1737 bmcr |= BMCR_PDOWN; 1738 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, bmcr); 1739 1740 if (new_phy_power_ctrl(jme->chip_main_rev)) 1741 jme_new_phy_off(jme); 1742 } 1743 1744 static int 1745 jme_phy_specreg_read(struct jme_adapter *jme, u32 specreg) 1746 { 1747 u32 phy_addr; 1748 1749 phy_addr = JM_PHY_SPEC_REG_READ | specreg; 1750 jme_mdio_write(jme->dev, jme->mii_if.phy_id, JM_PHY_SPEC_ADDR_REG, 1751 phy_addr); 1752 return jme_mdio_read(jme->dev, jme->mii_if.phy_id, 1753 JM_PHY_SPEC_DATA_REG); 1754 } 1755 1756 static void 1757 jme_phy_specreg_write(struct jme_adapter *jme, u32 ext_reg, u32 phy_data) 1758 { 1759 u32 phy_addr; 1760 1761 phy_addr = JM_PHY_SPEC_REG_WRITE | ext_reg; 1762 jme_mdio_write(jme->dev, jme->mii_if.phy_id, JM_PHY_SPEC_DATA_REG, 1763 phy_data); 1764 jme_mdio_write(jme->dev, jme->mii_if.phy_id, JM_PHY_SPEC_ADDR_REG, 1765 phy_addr); 1766 } 1767 1768 static int 1769 jme_phy_calibration(struct jme_adapter *jme) 1770 { 1771 u32 ctrl1000, phy_data; 1772 1773 jme_phy_off(jme); 1774 jme_phy_on(jme); 1775 /* Enabel PHY test mode 1 */ 1776 ctrl1000 = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_CTRL1000); 1777 ctrl1000 &= ~PHY_GAD_TEST_MODE_MSK; 1778 ctrl1000 |= PHY_GAD_TEST_MODE_1; 1779 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_CTRL1000, ctrl1000); 1780 1781 phy_data = jme_phy_specreg_read(jme, JM_PHY_EXT_COMM_2_REG); 1782 phy_data &= ~JM_PHY_EXT_COMM_2_CALI_MODE_0; 1783 phy_data |= JM_PHY_EXT_COMM_2_CALI_LATCH | 1784 JM_PHY_EXT_COMM_2_CALI_ENABLE; 1785 jme_phy_specreg_write(jme, JM_PHY_EXT_COMM_2_REG, phy_data); 1786 msleep(20); 1787 phy_data = jme_phy_specreg_read(jme, JM_PHY_EXT_COMM_2_REG); 1788 phy_data &= ~(JM_PHY_EXT_COMM_2_CALI_ENABLE | 1789 JM_PHY_EXT_COMM_2_CALI_MODE_0 | 1790 JM_PHY_EXT_COMM_2_CALI_LATCH); 1791 jme_phy_specreg_write(jme, JM_PHY_EXT_COMM_2_REG, phy_data); 1792 1793 /* Disable PHY test mode */ 1794 ctrl1000 = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_CTRL1000); 1795 ctrl1000 &= ~PHY_GAD_TEST_MODE_MSK; 1796 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_CTRL1000, ctrl1000); 1797 return 0; 1798 } 1799 1800 static int 1801 jme_phy_setEA(struct jme_adapter *jme) 1802 { 1803 u32 phy_comm0 = 0, phy_comm1 = 0; 1804 u8 nic_ctrl; 1805 1806 pci_read_config_byte(jme->pdev, PCI_PRIV_SHARE_NICCTRL, &nic_ctrl); 1807 if ((nic_ctrl & 0x3) == JME_FLAG_PHYEA_ENABLE) 1808 return 0; 1809 1810 switch (jme->pdev->device) { 1811 case PCI_DEVICE_ID_JMICRON_JMC250: 1812 if (((jme->chip_main_rev == 5) && 1813 ((jme->chip_sub_rev == 0) || (jme->chip_sub_rev == 1) || 1814 (jme->chip_sub_rev == 3))) || 1815 (jme->chip_main_rev >= 6)) { 1816 phy_comm0 = 0x008A; 1817 phy_comm1 = 0x4109; 1818 } 1819 if ((jme->chip_main_rev == 3) && 1820 ((jme->chip_sub_rev == 1) || (jme->chip_sub_rev == 2))) 1821 phy_comm0 = 0xE088; 1822 break; 1823 case PCI_DEVICE_ID_JMICRON_JMC260: 1824 if (((jme->chip_main_rev == 5) && 1825 ((jme->chip_sub_rev == 0) || (jme->chip_sub_rev == 1) || 1826 (jme->chip_sub_rev == 3))) || 1827 (jme->chip_main_rev >= 6)) { 1828 phy_comm0 = 0x008A; 1829 phy_comm1 = 0x4109; 1830 } 1831 if ((jme->chip_main_rev == 3) && 1832 ((jme->chip_sub_rev == 1) || (jme->chip_sub_rev == 2))) 1833 phy_comm0 = 0xE088; 1834 if ((jme->chip_main_rev == 2) && (jme->chip_sub_rev == 0)) 1835 phy_comm0 = 0x608A; 1836 if ((jme->chip_main_rev == 2) && (jme->chip_sub_rev == 2)) 1837 phy_comm0 = 0x408A; 1838 break; 1839 default: 1840 return -ENODEV; 1841 } 1842 if (phy_comm0) 1843 jme_phy_specreg_write(jme, JM_PHY_EXT_COMM_0_REG, phy_comm0); 1844 if (phy_comm1) 1845 jme_phy_specreg_write(jme, JM_PHY_EXT_COMM_1_REG, phy_comm1); 1846 1847 return 0; 1848 } 1849 1850 static int 1851 jme_open(struct net_device *netdev) 1852 { 1853 struct jme_adapter *jme = netdev_priv(netdev); 1854 int rc; 1855 1856 jme_clear_pm(jme); 1857 JME_NAPI_ENABLE(jme); 1858 1859 tasklet_init(&jme->linkch_task, jme_link_change_tasklet, 1860 (unsigned long) jme); 1861 tasklet_init(&jme->txclean_task, jme_tx_clean_tasklet, 1862 (unsigned long) jme); 1863 tasklet_init(&jme->rxclean_task, jme_rx_clean_tasklet, 1864 (unsigned long) jme); 1865 tasklet_init(&jme->rxempty_task, jme_rx_empty_tasklet, 1866 (unsigned long) jme); 1867 1868 rc = jme_request_irq(jme); 1869 if (rc) 1870 goto err_out; 1871 1872 jme_start_irq(jme); 1873 1874 jme_phy_on(jme); 1875 if (test_bit(JME_FLAG_SSET, &jme->flags)) 1876 jme_set_settings(netdev, &jme->old_ecmd); 1877 else 1878 jme_reset_phy_processor(jme); 1879 jme_phy_calibration(jme); 1880 jme_phy_setEA(jme); 1881 jme_reset_link(jme); 1882 1883 return 0; 1884 1885 err_out: 1886 netif_stop_queue(netdev); 1887 netif_carrier_off(netdev); 1888 return rc; 1889 } 1890 1891 static void 1892 jme_set_100m_half(struct jme_adapter *jme) 1893 { 1894 u32 bmcr, tmp; 1895 1896 jme_phy_on(jme); 1897 bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR); 1898 tmp = bmcr & ~(BMCR_ANENABLE | BMCR_SPEED100 | 1899 BMCR_SPEED1000 | BMCR_FULLDPLX); 1900 tmp |= BMCR_SPEED100; 1901 1902 if (bmcr != tmp) 1903 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, tmp); 1904 1905 if (jme->fpgaver) 1906 jwrite32(jme, JME_GHC, GHC_SPEED_100M | GHC_LINK_POLL); 1907 else 1908 jwrite32(jme, JME_GHC, GHC_SPEED_100M); 1909 } 1910 1911 #define JME_WAIT_LINK_TIME 2000 /* 2000ms */ 1912 static void 1913 jme_wait_link(struct jme_adapter *jme) 1914 { 1915 u32 phylink, to = JME_WAIT_LINK_TIME; 1916 1917 mdelay(1000); 1918 phylink = jme_linkstat_from_phy(jme); 1919 while (!(phylink & PHY_LINK_UP) && (to -= 10) > 0) { 1920 mdelay(10); 1921 phylink = jme_linkstat_from_phy(jme); 1922 } 1923 } 1924 1925 static void 1926 jme_powersave_phy(struct jme_adapter *jme) 1927 { 1928 if (jme->reg_pmcs) { 1929 jme_set_100m_half(jme); 1930 if (jme->reg_pmcs & (PMCS_LFEN | PMCS_LREN)) 1931 jme_wait_link(jme); 1932 jme_clear_pm(jme); 1933 } else { 1934 jme_phy_off(jme); 1935 } 1936 } 1937 1938 static int 1939 jme_close(struct net_device *netdev) 1940 { 1941 struct jme_adapter *jme = netdev_priv(netdev); 1942 1943 netif_stop_queue(netdev); 1944 netif_carrier_off(netdev); 1945 1946 jme_stop_irq(jme); 1947 jme_free_irq(jme); 1948 1949 JME_NAPI_DISABLE(jme); 1950 1951 tasklet_kill(&jme->linkch_task); 1952 tasklet_kill(&jme->txclean_task); 1953 tasklet_kill(&jme->rxclean_task); 1954 tasklet_kill(&jme->rxempty_task); 1955 1956 jme_disable_rx_engine(jme); 1957 jme_disable_tx_engine(jme); 1958 jme_reset_mac_processor(jme); 1959 jme_free_rx_resources(jme); 1960 jme_free_tx_resources(jme); 1961 jme->phylink = 0; 1962 jme_phy_off(jme); 1963 1964 return 0; 1965 } 1966 1967 static int 1968 jme_alloc_txdesc(struct jme_adapter *jme, 1969 struct sk_buff *skb) 1970 { 1971 struct jme_ring *txring = &(jme->txring[0]); 1972 int idx, nr_alloc, mask = jme->tx_ring_mask; 1973 1974 idx = txring->next_to_use; 1975 nr_alloc = skb_shinfo(skb)->nr_frags + 2; 1976 1977 if (unlikely(atomic_read(&txring->nr_free) < nr_alloc)) 1978 return -1; 1979 1980 atomic_sub(nr_alloc, &txring->nr_free); 1981 1982 txring->next_to_use = (txring->next_to_use + nr_alloc) & mask; 1983 1984 return idx; 1985 } 1986 1987 static int 1988 jme_fill_tx_map(struct pci_dev *pdev, 1989 struct txdesc *txdesc, 1990 struct jme_buffer_info *txbi, 1991 struct page *page, 1992 u32 page_offset, 1993 u32 len, 1994 bool hidma) 1995 { 1996 dma_addr_t dmaaddr; 1997 1998 dmaaddr = pci_map_page(pdev, 1999 page, 2000 page_offset, 2001 len, 2002 PCI_DMA_TODEVICE); 2003 2004 if (unlikely(pci_dma_mapping_error(pdev, dmaaddr))) 2005 return -EINVAL; 2006 2007 pci_dma_sync_single_for_device(pdev, 2008 dmaaddr, 2009 len, 2010 PCI_DMA_TODEVICE); 2011 2012 txdesc->dw[0] = 0; 2013 txdesc->dw[1] = 0; 2014 txdesc->desc2.flags = TXFLAG_OWN; 2015 txdesc->desc2.flags |= (hidma) ? TXFLAG_64BIT : 0; 2016 txdesc->desc2.datalen = cpu_to_le16(len); 2017 txdesc->desc2.bufaddrh = cpu_to_le32((__u64)dmaaddr >> 32); 2018 txdesc->desc2.bufaddrl = cpu_to_le32( 2019 (__u64)dmaaddr & 0xFFFFFFFFUL); 2020 2021 txbi->mapping = dmaaddr; 2022 txbi->len = len; 2023 return 0; 2024 } 2025 2026 static void jme_drop_tx_map(struct jme_adapter *jme, int startidx, int count) 2027 { 2028 struct jme_ring *txring = &(jme->txring[0]); 2029 struct jme_buffer_info *txbi = txring->bufinf, *ctxbi; 2030 int mask = jme->tx_ring_mask; 2031 int j; 2032 2033 for (j = 0 ; j < count ; j++) { 2034 ctxbi = txbi + ((startidx + j + 2) & (mask)); 2035 pci_unmap_page(jme->pdev, 2036 ctxbi->mapping, 2037 ctxbi->len, 2038 PCI_DMA_TODEVICE); 2039 2040 ctxbi->mapping = 0; 2041 ctxbi->len = 0; 2042 } 2043 2044 } 2045 2046 static int 2047 jme_map_tx_skb(struct jme_adapter *jme, struct sk_buff *skb, int idx) 2048 { 2049 struct jme_ring *txring = &(jme->txring[0]); 2050 struct txdesc *txdesc = txring->desc, *ctxdesc; 2051 struct jme_buffer_info *txbi = txring->bufinf, *ctxbi; 2052 bool hidma = jme->dev->features & NETIF_F_HIGHDMA; 2053 int i, nr_frags = skb_shinfo(skb)->nr_frags; 2054 int mask = jme->tx_ring_mask; 2055 const struct skb_frag_struct *frag; 2056 u32 len; 2057 int ret = 0; 2058 2059 for (i = 0 ; i < nr_frags ; ++i) { 2060 frag = &skb_shinfo(skb)->frags[i]; 2061 ctxdesc = txdesc + ((idx + i + 2) & (mask)); 2062 ctxbi = txbi + ((idx + i + 2) & (mask)); 2063 2064 ret = jme_fill_tx_map(jme->pdev, ctxdesc, ctxbi, 2065 skb_frag_page(frag), 2066 frag->page_offset, skb_frag_size(frag), hidma); 2067 if (ret) { 2068 jme_drop_tx_map(jme, idx, i); 2069 goto out; 2070 } 2071 2072 } 2073 2074 len = skb_is_nonlinear(skb) ? skb_headlen(skb) : skb->len; 2075 ctxdesc = txdesc + ((idx + 1) & (mask)); 2076 ctxbi = txbi + ((idx + 1) & (mask)); 2077 ret = jme_fill_tx_map(jme->pdev, ctxdesc, ctxbi, virt_to_page(skb->data), 2078 offset_in_page(skb->data), len, hidma); 2079 if (ret) 2080 jme_drop_tx_map(jme, idx, i); 2081 2082 out: 2083 return ret; 2084 2085 } 2086 2087 2088 static int 2089 jme_tx_tso(struct sk_buff *skb, __le16 *mss, u8 *flags) 2090 { 2091 *mss = cpu_to_le16(skb_shinfo(skb)->gso_size << TXDESC_MSS_SHIFT); 2092 if (*mss) { 2093 *flags |= TXFLAG_LSEN; 2094 2095 if (skb->protocol == htons(ETH_P_IP)) { 2096 struct iphdr *iph = ip_hdr(skb); 2097 2098 iph->check = 0; 2099 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr, 2100 iph->daddr, 0, 2101 IPPROTO_TCP, 2102 0); 2103 } else { 2104 struct ipv6hdr *ip6h = ipv6_hdr(skb); 2105 2106 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ip6h->saddr, 2107 &ip6h->daddr, 0, 2108 IPPROTO_TCP, 2109 0); 2110 } 2111 2112 return 0; 2113 } 2114 2115 return 1; 2116 } 2117 2118 static void 2119 jme_tx_csum(struct jme_adapter *jme, struct sk_buff *skb, u8 *flags) 2120 { 2121 if (skb->ip_summed == CHECKSUM_PARTIAL) { 2122 u8 ip_proto; 2123 2124 switch (skb->protocol) { 2125 case htons(ETH_P_IP): 2126 ip_proto = ip_hdr(skb)->protocol; 2127 break; 2128 case htons(ETH_P_IPV6): 2129 ip_proto = ipv6_hdr(skb)->nexthdr; 2130 break; 2131 default: 2132 ip_proto = 0; 2133 break; 2134 } 2135 2136 switch (ip_proto) { 2137 case IPPROTO_TCP: 2138 *flags |= TXFLAG_TCPCS; 2139 break; 2140 case IPPROTO_UDP: 2141 *flags |= TXFLAG_UDPCS; 2142 break; 2143 default: 2144 netif_err(jme, tx_err, jme->dev, "Error upper layer protocol\n"); 2145 break; 2146 } 2147 } 2148 } 2149 2150 static inline void 2151 jme_tx_vlan(struct sk_buff *skb, __le16 *vlan, u8 *flags) 2152 { 2153 if (skb_vlan_tag_present(skb)) { 2154 *flags |= TXFLAG_TAGON; 2155 *vlan = cpu_to_le16(skb_vlan_tag_get(skb)); 2156 } 2157 } 2158 2159 static int 2160 jme_fill_tx_desc(struct jme_adapter *jme, struct sk_buff *skb, int idx) 2161 { 2162 struct jme_ring *txring = &(jme->txring[0]); 2163 struct txdesc *txdesc; 2164 struct jme_buffer_info *txbi; 2165 u8 flags; 2166 int ret = 0; 2167 2168 txdesc = (struct txdesc *)txring->desc + idx; 2169 txbi = txring->bufinf + idx; 2170 2171 txdesc->dw[0] = 0; 2172 txdesc->dw[1] = 0; 2173 txdesc->dw[2] = 0; 2174 txdesc->dw[3] = 0; 2175 txdesc->desc1.pktsize = cpu_to_le16(skb->len); 2176 /* 2177 * Set OWN bit at final. 2178 * When kernel transmit faster than NIC. 2179 * And NIC trying to send this descriptor before we tell 2180 * it to start sending this TX queue. 2181 * Other fields are already filled correctly. 2182 */ 2183 wmb(); 2184 flags = TXFLAG_OWN | TXFLAG_INT; 2185 /* 2186 * Set checksum flags while not tso 2187 */ 2188 if (jme_tx_tso(skb, &txdesc->desc1.mss, &flags)) 2189 jme_tx_csum(jme, skb, &flags); 2190 jme_tx_vlan(skb, &txdesc->desc1.vlan, &flags); 2191 ret = jme_map_tx_skb(jme, skb, idx); 2192 if (ret) 2193 return ret; 2194 2195 txdesc->desc1.flags = flags; 2196 /* 2197 * Set tx buffer info after telling NIC to send 2198 * For better tx_clean timing 2199 */ 2200 wmb(); 2201 txbi->nr_desc = skb_shinfo(skb)->nr_frags + 2; 2202 txbi->skb = skb; 2203 txbi->len = skb->len; 2204 txbi->start_xmit = jiffies; 2205 if (!txbi->start_xmit) 2206 txbi->start_xmit = (0UL-1); 2207 2208 return 0; 2209 } 2210 2211 static void 2212 jme_stop_queue_if_full(struct jme_adapter *jme) 2213 { 2214 struct jme_ring *txring = &(jme->txring[0]); 2215 struct jme_buffer_info *txbi = txring->bufinf; 2216 int idx = atomic_read(&txring->next_to_clean); 2217 2218 txbi += idx; 2219 2220 smp_wmb(); 2221 if (unlikely(atomic_read(&txring->nr_free) < (MAX_SKB_FRAGS+2))) { 2222 netif_stop_queue(jme->dev); 2223 netif_info(jme, tx_queued, jme->dev, "TX Queue Paused\n"); 2224 smp_wmb(); 2225 if (atomic_read(&txring->nr_free) 2226 >= (jme->tx_wake_threshold)) { 2227 netif_wake_queue(jme->dev); 2228 netif_info(jme, tx_queued, jme->dev, "TX Queue Fast Waked\n"); 2229 } 2230 } 2231 2232 if (unlikely(txbi->start_xmit && 2233 (jiffies - txbi->start_xmit) >= TX_TIMEOUT && 2234 txbi->skb)) { 2235 netif_stop_queue(jme->dev); 2236 netif_info(jme, tx_queued, jme->dev, 2237 "TX Queue Stopped %d@%lu\n", idx, jiffies); 2238 } 2239 } 2240 2241 /* 2242 * This function is already protected by netif_tx_lock() 2243 */ 2244 2245 static netdev_tx_t 2246 jme_start_xmit(struct sk_buff *skb, struct net_device *netdev) 2247 { 2248 struct jme_adapter *jme = netdev_priv(netdev); 2249 int idx; 2250 2251 if (unlikely(skb_is_gso(skb) && skb_cow_head(skb, 0))) { 2252 dev_kfree_skb_any(skb); 2253 ++(NET_STAT(jme).tx_dropped); 2254 return NETDEV_TX_OK; 2255 } 2256 2257 idx = jme_alloc_txdesc(jme, skb); 2258 2259 if (unlikely(idx < 0)) { 2260 netif_stop_queue(netdev); 2261 netif_err(jme, tx_err, jme->dev, 2262 "BUG! Tx ring full when queue awake!\n"); 2263 2264 return NETDEV_TX_BUSY; 2265 } 2266 2267 if (jme_fill_tx_desc(jme, skb, idx)) 2268 return NETDEV_TX_OK; 2269 2270 jwrite32(jme, JME_TXCS, jme->reg_txcs | 2271 TXCS_SELECT_QUEUE0 | 2272 TXCS_QUEUE0S | 2273 TXCS_ENABLE); 2274 2275 tx_dbg(jme, "xmit: %d+%d@%lu\n", 2276 idx, skb_shinfo(skb)->nr_frags + 2, jiffies); 2277 jme_stop_queue_if_full(jme); 2278 2279 return NETDEV_TX_OK; 2280 } 2281 2282 static void 2283 jme_set_unicastaddr(struct net_device *netdev) 2284 { 2285 struct jme_adapter *jme = netdev_priv(netdev); 2286 u32 val; 2287 2288 val = (netdev->dev_addr[3] & 0xff) << 24 | 2289 (netdev->dev_addr[2] & 0xff) << 16 | 2290 (netdev->dev_addr[1] & 0xff) << 8 | 2291 (netdev->dev_addr[0] & 0xff); 2292 jwrite32(jme, JME_RXUMA_LO, val); 2293 val = (netdev->dev_addr[5] & 0xff) << 8 | 2294 (netdev->dev_addr[4] & 0xff); 2295 jwrite32(jme, JME_RXUMA_HI, val); 2296 } 2297 2298 static int 2299 jme_set_macaddr(struct net_device *netdev, void *p) 2300 { 2301 struct jme_adapter *jme = netdev_priv(netdev); 2302 struct sockaddr *addr = p; 2303 2304 if (netif_running(netdev)) 2305 return -EBUSY; 2306 2307 spin_lock_bh(&jme->macaddr_lock); 2308 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len); 2309 jme_set_unicastaddr(netdev); 2310 spin_unlock_bh(&jme->macaddr_lock); 2311 2312 return 0; 2313 } 2314 2315 static void 2316 jme_set_multi(struct net_device *netdev) 2317 { 2318 struct jme_adapter *jme = netdev_priv(netdev); 2319 u32 mc_hash[2] = {}; 2320 2321 spin_lock_bh(&jme->rxmcs_lock); 2322 2323 jme->reg_rxmcs |= RXMCS_BRDFRAME | RXMCS_UNIFRAME; 2324 2325 if (netdev->flags & IFF_PROMISC) { 2326 jme->reg_rxmcs |= RXMCS_ALLFRAME; 2327 } else if (netdev->flags & IFF_ALLMULTI) { 2328 jme->reg_rxmcs |= RXMCS_ALLMULFRAME; 2329 } else if (netdev->flags & IFF_MULTICAST) { 2330 struct netdev_hw_addr *ha; 2331 int bit_nr; 2332 2333 jme->reg_rxmcs |= RXMCS_MULFRAME | RXMCS_MULFILTERED; 2334 netdev_for_each_mc_addr(ha, netdev) { 2335 bit_nr = ether_crc(ETH_ALEN, ha->addr) & 0x3F; 2336 mc_hash[bit_nr >> 5] |= 1 << (bit_nr & 0x1F); 2337 } 2338 2339 jwrite32(jme, JME_RXMCHT_LO, mc_hash[0]); 2340 jwrite32(jme, JME_RXMCHT_HI, mc_hash[1]); 2341 } 2342 2343 wmb(); 2344 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs); 2345 2346 spin_unlock_bh(&jme->rxmcs_lock); 2347 } 2348 2349 static int 2350 jme_change_mtu(struct net_device *netdev, int new_mtu) 2351 { 2352 struct jme_adapter *jme = netdev_priv(netdev); 2353 2354 if (new_mtu == jme->old_mtu) 2355 return 0; 2356 2357 if (((new_mtu + ETH_HLEN) > MAX_ETHERNET_JUMBO_PACKET_SIZE) || 2358 ((new_mtu) < IPV6_MIN_MTU)) 2359 return -EINVAL; 2360 2361 2362 netdev->mtu = new_mtu; 2363 netdev_update_features(netdev); 2364 2365 jme_restart_rx_engine(jme); 2366 jme_reset_link(jme); 2367 2368 return 0; 2369 } 2370 2371 static void 2372 jme_tx_timeout(struct net_device *netdev) 2373 { 2374 struct jme_adapter *jme = netdev_priv(netdev); 2375 2376 jme->phylink = 0; 2377 jme_reset_phy_processor(jme); 2378 if (test_bit(JME_FLAG_SSET, &jme->flags)) 2379 jme_set_settings(netdev, &jme->old_ecmd); 2380 2381 /* 2382 * Force to Reset the link again 2383 */ 2384 jme_reset_link(jme); 2385 } 2386 2387 static inline void jme_pause_rx(struct jme_adapter *jme) 2388 { 2389 atomic_dec(&jme->link_changing); 2390 2391 jme_set_rx_pcc(jme, PCC_OFF); 2392 if (test_bit(JME_FLAG_POLL, &jme->flags)) { 2393 JME_NAPI_DISABLE(jme); 2394 } else { 2395 tasklet_disable(&jme->rxclean_task); 2396 tasklet_disable(&jme->rxempty_task); 2397 } 2398 } 2399 2400 static inline void jme_resume_rx(struct jme_adapter *jme) 2401 { 2402 struct dynpcc_info *dpi = &(jme->dpi); 2403 2404 if (test_bit(JME_FLAG_POLL, &jme->flags)) { 2405 JME_NAPI_ENABLE(jme); 2406 } else { 2407 tasklet_enable(&jme->rxclean_task); 2408 tasklet_enable(&jme->rxempty_task); 2409 } 2410 dpi->cur = PCC_P1; 2411 dpi->attempt = PCC_P1; 2412 dpi->cnt = 0; 2413 jme_set_rx_pcc(jme, PCC_P1); 2414 2415 atomic_inc(&jme->link_changing); 2416 } 2417 2418 static void 2419 jme_get_drvinfo(struct net_device *netdev, 2420 struct ethtool_drvinfo *info) 2421 { 2422 struct jme_adapter *jme = netdev_priv(netdev); 2423 2424 strlcpy(info->driver, DRV_NAME, sizeof(info->driver)); 2425 strlcpy(info->version, DRV_VERSION, sizeof(info->version)); 2426 strlcpy(info->bus_info, pci_name(jme->pdev), sizeof(info->bus_info)); 2427 } 2428 2429 static int 2430 jme_get_regs_len(struct net_device *netdev) 2431 { 2432 return JME_REG_LEN; 2433 } 2434 2435 static void 2436 mmapio_memcpy(struct jme_adapter *jme, u32 *p, u32 reg, int len) 2437 { 2438 int i; 2439 2440 for (i = 0 ; i < len ; i += 4) 2441 p[i >> 2] = jread32(jme, reg + i); 2442 } 2443 2444 static void 2445 mdio_memcpy(struct jme_adapter *jme, u32 *p, int reg_nr) 2446 { 2447 int i; 2448 u16 *p16 = (u16 *)p; 2449 2450 for (i = 0 ; i < reg_nr ; ++i) 2451 p16[i] = jme_mdio_read(jme->dev, jme->mii_if.phy_id, i); 2452 } 2453 2454 static void 2455 jme_get_regs(struct net_device *netdev, struct ethtool_regs *regs, void *p) 2456 { 2457 struct jme_adapter *jme = netdev_priv(netdev); 2458 u32 *p32 = (u32 *)p; 2459 2460 memset(p, 0xFF, JME_REG_LEN); 2461 2462 regs->version = 1; 2463 mmapio_memcpy(jme, p32, JME_MAC, JME_MAC_LEN); 2464 2465 p32 += 0x100 >> 2; 2466 mmapio_memcpy(jme, p32, JME_PHY, JME_PHY_LEN); 2467 2468 p32 += 0x100 >> 2; 2469 mmapio_memcpy(jme, p32, JME_MISC, JME_MISC_LEN); 2470 2471 p32 += 0x100 >> 2; 2472 mmapio_memcpy(jme, p32, JME_RSS, JME_RSS_LEN); 2473 2474 p32 += 0x100 >> 2; 2475 mdio_memcpy(jme, p32, JME_PHY_REG_NR); 2476 } 2477 2478 static int 2479 jme_get_coalesce(struct net_device *netdev, struct ethtool_coalesce *ecmd) 2480 { 2481 struct jme_adapter *jme = netdev_priv(netdev); 2482 2483 ecmd->tx_coalesce_usecs = PCC_TX_TO; 2484 ecmd->tx_max_coalesced_frames = PCC_TX_CNT; 2485 2486 if (test_bit(JME_FLAG_POLL, &jme->flags)) { 2487 ecmd->use_adaptive_rx_coalesce = false; 2488 ecmd->rx_coalesce_usecs = 0; 2489 ecmd->rx_max_coalesced_frames = 0; 2490 return 0; 2491 } 2492 2493 ecmd->use_adaptive_rx_coalesce = true; 2494 2495 switch (jme->dpi.cur) { 2496 case PCC_P1: 2497 ecmd->rx_coalesce_usecs = PCC_P1_TO; 2498 ecmd->rx_max_coalesced_frames = PCC_P1_CNT; 2499 break; 2500 case PCC_P2: 2501 ecmd->rx_coalesce_usecs = PCC_P2_TO; 2502 ecmd->rx_max_coalesced_frames = PCC_P2_CNT; 2503 break; 2504 case PCC_P3: 2505 ecmd->rx_coalesce_usecs = PCC_P3_TO; 2506 ecmd->rx_max_coalesced_frames = PCC_P3_CNT; 2507 break; 2508 default: 2509 break; 2510 } 2511 2512 return 0; 2513 } 2514 2515 static int 2516 jme_set_coalesce(struct net_device *netdev, struct ethtool_coalesce *ecmd) 2517 { 2518 struct jme_adapter *jme = netdev_priv(netdev); 2519 struct dynpcc_info *dpi = &(jme->dpi); 2520 2521 if (netif_running(netdev)) 2522 return -EBUSY; 2523 2524 if (ecmd->use_adaptive_rx_coalesce && 2525 test_bit(JME_FLAG_POLL, &jme->flags)) { 2526 clear_bit(JME_FLAG_POLL, &jme->flags); 2527 jme->jme_rx = netif_rx; 2528 dpi->cur = PCC_P1; 2529 dpi->attempt = PCC_P1; 2530 dpi->cnt = 0; 2531 jme_set_rx_pcc(jme, PCC_P1); 2532 jme_interrupt_mode(jme); 2533 } else if (!(ecmd->use_adaptive_rx_coalesce) && 2534 !(test_bit(JME_FLAG_POLL, &jme->flags))) { 2535 set_bit(JME_FLAG_POLL, &jme->flags); 2536 jme->jme_rx = netif_receive_skb; 2537 jme_interrupt_mode(jme); 2538 } 2539 2540 return 0; 2541 } 2542 2543 static void 2544 jme_get_pauseparam(struct net_device *netdev, 2545 struct ethtool_pauseparam *ecmd) 2546 { 2547 struct jme_adapter *jme = netdev_priv(netdev); 2548 u32 val; 2549 2550 ecmd->tx_pause = (jme->reg_txpfc & TXPFC_PF_EN) != 0; 2551 ecmd->rx_pause = (jme->reg_rxmcs & RXMCS_FLOWCTRL) != 0; 2552 2553 spin_lock_bh(&jme->phy_lock); 2554 val = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_ADVERTISE); 2555 spin_unlock_bh(&jme->phy_lock); 2556 2557 ecmd->autoneg = 2558 (val & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM)) != 0; 2559 } 2560 2561 static int 2562 jme_set_pauseparam(struct net_device *netdev, 2563 struct ethtool_pauseparam *ecmd) 2564 { 2565 struct jme_adapter *jme = netdev_priv(netdev); 2566 u32 val; 2567 2568 if (((jme->reg_txpfc & TXPFC_PF_EN) != 0) ^ 2569 (ecmd->tx_pause != 0)) { 2570 2571 if (ecmd->tx_pause) 2572 jme->reg_txpfc |= TXPFC_PF_EN; 2573 else 2574 jme->reg_txpfc &= ~TXPFC_PF_EN; 2575 2576 jwrite32(jme, JME_TXPFC, jme->reg_txpfc); 2577 } 2578 2579 spin_lock_bh(&jme->rxmcs_lock); 2580 if (((jme->reg_rxmcs & RXMCS_FLOWCTRL) != 0) ^ 2581 (ecmd->rx_pause != 0)) { 2582 2583 if (ecmd->rx_pause) 2584 jme->reg_rxmcs |= RXMCS_FLOWCTRL; 2585 else 2586 jme->reg_rxmcs &= ~RXMCS_FLOWCTRL; 2587 2588 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs); 2589 } 2590 spin_unlock_bh(&jme->rxmcs_lock); 2591 2592 spin_lock_bh(&jme->phy_lock); 2593 val = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_ADVERTISE); 2594 if (((val & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM)) != 0) ^ 2595 (ecmd->autoneg != 0)) { 2596 2597 if (ecmd->autoneg) 2598 val |= (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM); 2599 else 2600 val &= ~(ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM); 2601 2602 jme_mdio_write(jme->dev, jme->mii_if.phy_id, 2603 MII_ADVERTISE, val); 2604 } 2605 spin_unlock_bh(&jme->phy_lock); 2606 2607 return 0; 2608 } 2609 2610 static void 2611 jme_get_wol(struct net_device *netdev, 2612 struct ethtool_wolinfo *wol) 2613 { 2614 struct jme_adapter *jme = netdev_priv(netdev); 2615 2616 wol->supported = WAKE_MAGIC | WAKE_PHY; 2617 2618 wol->wolopts = 0; 2619 2620 if (jme->reg_pmcs & (PMCS_LFEN | PMCS_LREN)) 2621 wol->wolopts |= WAKE_PHY; 2622 2623 if (jme->reg_pmcs & PMCS_MFEN) 2624 wol->wolopts |= WAKE_MAGIC; 2625 2626 } 2627 2628 static int 2629 jme_set_wol(struct net_device *netdev, 2630 struct ethtool_wolinfo *wol) 2631 { 2632 struct jme_adapter *jme = netdev_priv(netdev); 2633 2634 if (wol->wolopts & (WAKE_MAGICSECURE | 2635 WAKE_UCAST | 2636 WAKE_MCAST | 2637 WAKE_BCAST | 2638 WAKE_ARP)) 2639 return -EOPNOTSUPP; 2640 2641 jme->reg_pmcs = 0; 2642 2643 if (wol->wolopts & WAKE_PHY) 2644 jme->reg_pmcs |= PMCS_LFEN | PMCS_LREN; 2645 2646 if (wol->wolopts & WAKE_MAGIC) 2647 jme->reg_pmcs |= PMCS_MFEN; 2648 2649 jwrite32(jme, JME_PMCS, jme->reg_pmcs); 2650 device_set_wakeup_enable(&jme->pdev->dev, !!(jme->reg_pmcs)); 2651 2652 return 0; 2653 } 2654 2655 static int 2656 jme_get_settings(struct net_device *netdev, 2657 struct ethtool_cmd *ecmd) 2658 { 2659 struct jme_adapter *jme = netdev_priv(netdev); 2660 int rc; 2661 2662 spin_lock_bh(&jme->phy_lock); 2663 rc = mii_ethtool_gset(&(jme->mii_if), ecmd); 2664 spin_unlock_bh(&jme->phy_lock); 2665 return rc; 2666 } 2667 2668 static int 2669 jme_set_settings(struct net_device *netdev, 2670 struct ethtool_cmd *ecmd) 2671 { 2672 struct jme_adapter *jme = netdev_priv(netdev); 2673 int rc, fdc = 0; 2674 2675 if (ethtool_cmd_speed(ecmd) == SPEED_1000 2676 && ecmd->autoneg != AUTONEG_ENABLE) 2677 return -EINVAL; 2678 2679 /* 2680 * Check If user changed duplex only while force_media. 2681 * Hardware would not generate link change interrupt. 2682 */ 2683 if (jme->mii_if.force_media && 2684 ecmd->autoneg != AUTONEG_ENABLE && 2685 (jme->mii_if.full_duplex != ecmd->duplex)) 2686 fdc = 1; 2687 2688 spin_lock_bh(&jme->phy_lock); 2689 rc = mii_ethtool_sset(&(jme->mii_if), ecmd); 2690 spin_unlock_bh(&jme->phy_lock); 2691 2692 if (!rc) { 2693 if (fdc) 2694 jme_reset_link(jme); 2695 jme->old_ecmd = *ecmd; 2696 set_bit(JME_FLAG_SSET, &jme->flags); 2697 } 2698 2699 return rc; 2700 } 2701 2702 static int 2703 jme_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd) 2704 { 2705 int rc; 2706 struct jme_adapter *jme = netdev_priv(netdev); 2707 struct mii_ioctl_data *mii_data = if_mii(rq); 2708 unsigned int duplex_chg; 2709 2710 if (cmd == SIOCSMIIREG) { 2711 u16 val = mii_data->val_in; 2712 if (!(val & (BMCR_RESET|BMCR_ANENABLE)) && 2713 (val & BMCR_SPEED1000)) 2714 return -EINVAL; 2715 } 2716 2717 spin_lock_bh(&jme->phy_lock); 2718 rc = generic_mii_ioctl(&jme->mii_if, mii_data, cmd, &duplex_chg); 2719 spin_unlock_bh(&jme->phy_lock); 2720 2721 if (!rc && (cmd == SIOCSMIIREG)) { 2722 if (duplex_chg) 2723 jme_reset_link(jme); 2724 jme_get_settings(netdev, &jme->old_ecmd); 2725 set_bit(JME_FLAG_SSET, &jme->flags); 2726 } 2727 2728 return rc; 2729 } 2730 2731 static u32 2732 jme_get_link(struct net_device *netdev) 2733 { 2734 struct jme_adapter *jme = netdev_priv(netdev); 2735 return jread32(jme, JME_PHY_LINK) & PHY_LINK_UP; 2736 } 2737 2738 static u32 2739 jme_get_msglevel(struct net_device *netdev) 2740 { 2741 struct jme_adapter *jme = netdev_priv(netdev); 2742 return jme->msg_enable; 2743 } 2744 2745 static void 2746 jme_set_msglevel(struct net_device *netdev, u32 value) 2747 { 2748 struct jme_adapter *jme = netdev_priv(netdev); 2749 jme->msg_enable = value; 2750 } 2751 2752 static netdev_features_t 2753 jme_fix_features(struct net_device *netdev, netdev_features_t features) 2754 { 2755 if (netdev->mtu > 1900) 2756 features &= ~(NETIF_F_ALL_TSO | NETIF_F_CSUM_MASK); 2757 return features; 2758 } 2759 2760 static int 2761 jme_set_features(struct net_device *netdev, netdev_features_t features) 2762 { 2763 struct jme_adapter *jme = netdev_priv(netdev); 2764 2765 spin_lock_bh(&jme->rxmcs_lock); 2766 if (features & NETIF_F_RXCSUM) 2767 jme->reg_rxmcs |= RXMCS_CHECKSUM; 2768 else 2769 jme->reg_rxmcs &= ~RXMCS_CHECKSUM; 2770 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs); 2771 spin_unlock_bh(&jme->rxmcs_lock); 2772 2773 return 0; 2774 } 2775 2776 #ifdef CONFIG_NET_POLL_CONTROLLER 2777 static void jme_netpoll(struct net_device *dev) 2778 { 2779 unsigned long flags; 2780 2781 local_irq_save(flags); 2782 jme_intr(dev->irq, dev); 2783 local_irq_restore(flags); 2784 } 2785 #endif 2786 2787 static int 2788 jme_nway_reset(struct net_device *netdev) 2789 { 2790 struct jme_adapter *jme = netdev_priv(netdev); 2791 jme_restart_an(jme); 2792 return 0; 2793 } 2794 2795 static u8 2796 jme_smb_read(struct jme_adapter *jme, unsigned int addr) 2797 { 2798 u32 val; 2799 int to; 2800 2801 val = jread32(jme, JME_SMBCSR); 2802 to = JME_SMB_BUSY_TIMEOUT; 2803 while ((val & SMBCSR_BUSY) && --to) { 2804 msleep(1); 2805 val = jread32(jme, JME_SMBCSR); 2806 } 2807 if (!to) { 2808 netif_err(jme, hw, jme->dev, "SMB Bus Busy\n"); 2809 return 0xFF; 2810 } 2811 2812 jwrite32(jme, JME_SMBINTF, 2813 ((addr << SMBINTF_HWADDR_SHIFT) & SMBINTF_HWADDR) | 2814 SMBINTF_HWRWN_READ | 2815 SMBINTF_HWCMD); 2816 2817 val = jread32(jme, JME_SMBINTF); 2818 to = JME_SMB_BUSY_TIMEOUT; 2819 while ((val & SMBINTF_HWCMD) && --to) { 2820 msleep(1); 2821 val = jread32(jme, JME_SMBINTF); 2822 } 2823 if (!to) { 2824 netif_err(jme, hw, jme->dev, "SMB Bus Busy\n"); 2825 return 0xFF; 2826 } 2827 2828 return (val & SMBINTF_HWDATR) >> SMBINTF_HWDATR_SHIFT; 2829 } 2830 2831 static void 2832 jme_smb_write(struct jme_adapter *jme, unsigned int addr, u8 data) 2833 { 2834 u32 val; 2835 int to; 2836 2837 val = jread32(jme, JME_SMBCSR); 2838 to = JME_SMB_BUSY_TIMEOUT; 2839 while ((val & SMBCSR_BUSY) && --to) { 2840 msleep(1); 2841 val = jread32(jme, JME_SMBCSR); 2842 } 2843 if (!to) { 2844 netif_err(jme, hw, jme->dev, "SMB Bus Busy\n"); 2845 return; 2846 } 2847 2848 jwrite32(jme, JME_SMBINTF, 2849 ((data << SMBINTF_HWDATW_SHIFT) & SMBINTF_HWDATW) | 2850 ((addr << SMBINTF_HWADDR_SHIFT) & SMBINTF_HWADDR) | 2851 SMBINTF_HWRWN_WRITE | 2852 SMBINTF_HWCMD); 2853 2854 val = jread32(jme, JME_SMBINTF); 2855 to = JME_SMB_BUSY_TIMEOUT; 2856 while ((val & SMBINTF_HWCMD) && --to) { 2857 msleep(1); 2858 val = jread32(jme, JME_SMBINTF); 2859 } 2860 if (!to) { 2861 netif_err(jme, hw, jme->dev, "SMB Bus Busy\n"); 2862 return; 2863 } 2864 2865 mdelay(2); 2866 } 2867 2868 static int 2869 jme_get_eeprom_len(struct net_device *netdev) 2870 { 2871 struct jme_adapter *jme = netdev_priv(netdev); 2872 u32 val; 2873 val = jread32(jme, JME_SMBCSR); 2874 return (val & SMBCSR_EEPROMD) ? JME_SMB_LEN : 0; 2875 } 2876 2877 static int 2878 jme_get_eeprom(struct net_device *netdev, 2879 struct ethtool_eeprom *eeprom, u8 *data) 2880 { 2881 struct jme_adapter *jme = netdev_priv(netdev); 2882 int i, offset = eeprom->offset, len = eeprom->len; 2883 2884 /* 2885 * ethtool will check the boundary for us 2886 */ 2887 eeprom->magic = JME_EEPROM_MAGIC; 2888 for (i = 0 ; i < len ; ++i) 2889 data[i] = jme_smb_read(jme, i + offset); 2890 2891 return 0; 2892 } 2893 2894 static int 2895 jme_set_eeprom(struct net_device *netdev, 2896 struct ethtool_eeprom *eeprom, u8 *data) 2897 { 2898 struct jme_adapter *jme = netdev_priv(netdev); 2899 int i, offset = eeprom->offset, len = eeprom->len; 2900 2901 if (eeprom->magic != JME_EEPROM_MAGIC) 2902 return -EINVAL; 2903 2904 /* 2905 * ethtool will check the boundary for us 2906 */ 2907 for (i = 0 ; i < len ; ++i) 2908 jme_smb_write(jme, i + offset, data[i]); 2909 2910 return 0; 2911 } 2912 2913 static const struct ethtool_ops jme_ethtool_ops = { 2914 .get_drvinfo = jme_get_drvinfo, 2915 .get_regs_len = jme_get_regs_len, 2916 .get_regs = jme_get_regs, 2917 .get_coalesce = jme_get_coalesce, 2918 .set_coalesce = jme_set_coalesce, 2919 .get_pauseparam = jme_get_pauseparam, 2920 .set_pauseparam = jme_set_pauseparam, 2921 .get_wol = jme_get_wol, 2922 .set_wol = jme_set_wol, 2923 .get_settings = jme_get_settings, 2924 .set_settings = jme_set_settings, 2925 .get_link = jme_get_link, 2926 .get_msglevel = jme_get_msglevel, 2927 .set_msglevel = jme_set_msglevel, 2928 .nway_reset = jme_nway_reset, 2929 .get_eeprom_len = jme_get_eeprom_len, 2930 .get_eeprom = jme_get_eeprom, 2931 .set_eeprom = jme_set_eeprom, 2932 }; 2933 2934 static int 2935 jme_pci_dma64(struct pci_dev *pdev) 2936 { 2937 if (pdev->device == PCI_DEVICE_ID_JMICRON_JMC250 && 2938 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) 2939 if (!pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64))) 2940 return 1; 2941 2942 if (pdev->device == PCI_DEVICE_ID_JMICRON_JMC250 && 2943 !pci_set_dma_mask(pdev, DMA_BIT_MASK(40))) 2944 if (!pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(40))) 2945 return 1; 2946 2947 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) 2948 if (!pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32))) 2949 return 0; 2950 2951 return -1; 2952 } 2953 2954 static inline void 2955 jme_phy_init(struct jme_adapter *jme) 2956 { 2957 u16 reg26; 2958 2959 reg26 = jme_mdio_read(jme->dev, jme->mii_if.phy_id, 26); 2960 jme_mdio_write(jme->dev, jme->mii_if.phy_id, 26, reg26 | 0x1000); 2961 } 2962 2963 static inline void 2964 jme_check_hw_ver(struct jme_adapter *jme) 2965 { 2966 u32 chipmode; 2967 2968 chipmode = jread32(jme, JME_CHIPMODE); 2969 2970 jme->fpgaver = (chipmode & CM_FPGAVER_MASK) >> CM_FPGAVER_SHIFT; 2971 jme->chiprev = (chipmode & CM_CHIPREV_MASK) >> CM_CHIPREV_SHIFT; 2972 jme->chip_main_rev = jme->chiprev & 0xF; 2973 jme->chip_sub_rev = (jme->chiprev >> 4) & 0xF; 2974 } 2975 2976 static const struct net_device_ops jme_netdev_ops = { 2977 .ndo_open = jme_open, 2978 .ndo_stop = jme_close, 2979 .ndo_validate_addr = eth_validate_addr, 2980 .ndo_do_ioctl = jme_ioctl, 2981 .ndo_start_xmit = jme_start_xmit, 2982 .ndo_set_mac_address = jme_set_macaddr, 2983 .ndo_set_rx_mode = jme_set_multi, 2984 .ndo_change_mtu = jme_change_mtu, 2985 .ndo_tx_timeout = jme_tx_timeout, 2986 .ndo_fix_features = jme_fix_features, 2987 .ndo_set_features = jme_set_features, 2988 #ifdef CONFIG_NET_POLL_CONTROLLER 2989 .ndo_poll_controller = jme_netpoll, 2990 #endif 2991 }; 2992 2993 static int 2994 jme_init_one(struct pci_dev *pdev, 2995 const struct pci_device_id *ent) 2996 { 2997 int rc = 0, using_dac, i; 2998 struct net_device *netdev; 2999 struct jme_adapter *jme; 3000 u16 bmcr, bmsr; 3001 u32 apmc; 3002 3003 /* 3004 * set up PCI device basics 3005 */ 3006 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 | 3007 PCIE_LINK_STATE_CLKPM); 3008 3009 rc = pci_enable_device(pdev); 3010 if (rc) { 3011 pr_err("Cannot enable PCI device\n"); 3012 goto err_out; 3013 } 3014 3015 using_dac = jme_pci_dma64(pdev); 3016 if (using_dac < 0) { 3017 pr_err("Cannot set PCI DMA Mask\n"); 3018 rc = -EIO; 3019 goto err_out_disable_pdev; 3020 } 3021 3022 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) { 3023 pr_err("No PCI resource region found\n"); 3024 rc = -ENOMEM; 3025 goto err_out_disable_pdev; 3026 } 3027 3028 rc = pci_request_regions(pdev, DRV_NAME); 3029 if (rc) { 3030 pr_err("Cannot obtain PCI resource region\n"); 3031 goto err_out_disable_pdev; 3032 } 3033 3034 pci_set_master(pdev); 3035 3036 /* 3037 * alloc and init net device 3038 */ 3039 netdev = alloc_etherdev(sizeof(*jme)); 3040 if (!netdev) { 3041 rc = -ENOMEM; 3042 goto err_out_release_regions; 3043 } 3044 netdev->netdev_ops = &jme_netdev_ops; 3045 netdev->ethtool_ops = &jme_ethtool_ops; 3046 netdev->watchdog_timeo = TX_TIMEOUT; 3047 netdev->hw_features = NETIF_F_IP_CSUM | 3048 NETIF_F_IPV6_CSUM | 3049 NETIF_F_SG | 3050 NETIF_F_TSO | 3051 NETIF_F_TSO6 | 3052 NETIF_F_RXCSUM; 3053 netdev->features = NETIF_F_IP_CSUM | 3054 NETIF_F_IPV6_CSUM | 3055 NETIF_F_SG | 3056 NETIF_F_TSO | 3057 NETIF_F_TSO6 | 3058 NETIF_F_HW_VLAN_CTAG_TX | 3059 NETIF_F_HW_VLAN_CTAG_RX; 3060 if (using_dac) 3061 netdev->features |= NETIF_F_HIGHDMA; 3062 3063 SET_NETDEV_DEV(netdev, &pdev->dev); 3064 pci_set_drvdata(pdev, netdev); 3065 3066 /* 3067 * init adapter info 3068 */ 3069 jme = netdev_priv(netdev); 3070 jme->pdev = pdev; 3071 jme->dev = netdev; 3072 jme->jme_rx = netif_rx; 3073 jme->old_mtu = netdev->mtu = 1500; 3074 jme->phylink = 0; 3075 jme->tx_ring_size = 1 << 10; 3076 jme->tx_ring_mask = jme->tx_ring_size - 1; 3077 jme->tx_wake_threshold = 1 << 9; 3078 jme->rx_ring_size = 1 << 9; 3079 jme->rx_ring_mask = jme->rx_ring_size - 1; 3080 jme->msg_enable = JME_DEF_MSG_ENABLE; 3081 jme->regs = ioremap(pci_resource_start(pdev, 0), 3082 pci_resource_len(pdev, 0)); 3083 if (!(jme->regs)) { 3084 pr_err("Mapping PCI resource region error\n"); 3085 rc = -ENOMEM; 3086 goto err_out_free_netdev; 3087 } 3088 3089 if (no_pseudohp) { 3090 apmc = jread32(jme, JME_APMC) & ~JME_APMC_PSEUDO_HP_EN; 3091 jwrite32(jme, JME_APMC, apmc); 3092 } else if (force_pseudohp) { 3093 apmc = jread32(jme, JME_APMC) | JME_APMC_PSEUDO_HP_EN; 3094 jwrite32(jme, JME_APMC, apmc); 3095 } 3096 3097 NETIF_NAPI_SET(netdev, &jme->napi, jme_poll, NAPI_POLL_WEIGHT) 3098 3099 spin_lock_init(&jme->phy_lock); 3100 spin_lock_init(&jme->macaddr_lock); 3101 spin_lock_init(&jme->rxmcs_lock); 3102 3103 atomic_set(&jme->link_changing, 1); 3104 atomic_set(&jme->rx_cleaning, 1); 3105 atomic_set(&jme->tx_cleaning, 1); 3106 atomic_set(&jme->rx_empty, 1); 3107 3108 tasklet_init(&jme->pcc_task, 3109 jme_pcc_tasklet, 3110 (unsigned long) jme); 3111 jme->dpi.cur = PCC_P1; 3112 3113 jme->reg_ghc = 0; 3114 jme->reg_rxcs = RXCS_DEFAULT; 3115 jme->reg_rxmcs = RXMCS_DEFAULT; 3116 jme->reg_txpfc = 0; 3117 jme->reg_pmcs = PMCS_MFEN; 3118 jme->reg_gpreg1 = GPREG1_DEFAULT; 3119 3120 if (jme->reg_rxmcs & RXMCS_CHECKSUM) 3121 netdev->features |= NETIF_F_RXCSUM; 3122 3123 /* 3124 * Get Max Read Req Size from PCI Config Space 3125 */ 3126 pci_read_config_byte(pdev, PCI_DCSR_MRRS, &jme->mrrs); 3127 jme->mrrs &= PCI_DCSR_MRRS_MASK; 3128 switch (jme->mrrs) { 3129 case MRRS_128B: 3130 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_128B; 3131 break; 3132 case MRRS_256B: 3133 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_256B; 3134 break; 3135 default: 3136 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_512B; 3137 break; 3138 } 3139 3140 /* 3141 * Must check before reset_mac_processor 3142 */ 3143 jme_check_hw_ver(jme); 3144 jme->mii_if.dev = netdev; 3145 if (jme->fpgaver) { 3146 jme->mii_if.phy_id = 0; 3147 for (i = 1 ; i < 32 ; ++i) { 3148 bmcr = jme_mdio_read(netdev, i, MII_BMCR); 3149 bmsr = jme_mdio_read(netdev, i, MII_BMSR); 3150 if (bmcr != 0xFFFFU && (bmcr != 0 || bmsr != 0)) { 3151 jme->mii_if.phy_id = i; 3152 break; 3153 } 3154 } 3155 3156 if (!jme->mii_if.phy_id) { 3157 rc = -EIO; 3158 pr_err("Can not find phy_id\n"); 3159 goto err_out_unmap; 3160 } 3161 3162 jme->reg_ghc |= GHC_LINK_POLL; 3163 } else { 3164 jme->mii_if.phy_id = 1; 3165 } 3166 if (pdev->device == PCI_DEVICE_ID_JMICRON_JMC250) 3167 jme->mii_if.supports_gmii = true; 3168 else 3169 jme->mii_if.supports_gmii = false; 3170 jme->mii_if.phy_id_mask = 0x1F; 3171 jme->mii_if.reg_num_mask = 0x1F; 3172 jme->mii_if.mdio_read = jme_mdio_read; 3173 jme->mii_if.mdio_write = jme_mdio_write; 3174 3175 jme_clear_pm(jme); 3176 device_set_wakeup_enable(&pdev->dev, true); 3177 3178 jme_set_phyfifo_5level(jme); 3179 jme->pcirev = pdev->revision; 3180 if (!jme->fpgaver) 3181 jme_phy_init(jme); 3182 jme_phy_off(jme); 3183 3184 /* 3185 * Reset MAC processor and reload EEPROM for MAC Address 3186 */ 3187 jme_reset_mac_processor(jme); 3188 rc = jme_reload_eeprom(jme); 3189 if (rc) { 3190 pr_err("Reload eeprom for reading MAC Address error\n"); 3191 goto err_out_unmap; 3192 } 3193 jme_load_macaddr(netdev); 3194 3195 /* 3196 * Tell stack that we are not ready to work until open() 3197 */ 3198 netif_carrier_off(netdev); 3199 3200 rc = register_netdev(netdev); 3201 if (rc) { 3202 pr_err("Cannot register net device\n"); 3203 goto err_out_unmap; 3204 } 3205 3206 netif_info(jme, probe, jme->dev, "%s%s chiprev:%x pcirev:%x macaddr:%pM\n", 3207 (jme->pdev->device == PCI_DEVICE_ID_JMICRON_JMC250) ? 3208 "JMC250 Gigabit Ethernet" : 3209 (jme->pdev->device == PCI_DEVICE_ID_JMICRON_JMC260) ? 3210 "JMC260 Fast Ethernet" : "Unknown", 3211 (jme->fpgaver != 0) ? " (FPGA)" : "", 3212 (jme->fpgaver != 0) ? jme->fpgaver : jme->chiprev, 3213 jme->pcirev, netdev->dev_addr); 3214 3215 return 0; 3216 3217 err_out_unmap: 3218 iounmap(jme->regs); 3219 err_out_free_netdev: 3220 free_netdev(netdev); 3221 err_out_release_regions: 3222 pci_release_regions(pdev); 3223 err_out_disable_pdev: 3224 pci_disable_device(pdev); 3225 err_out: 3226 return rc; 3227 } 3228 3229 static void 3230 jme_remove_one(struct pci_dev *pdev) 3231 { 3232 struct net_device *netdev = pci_get_drvdata(pdev); 3233 struct jme_adapter *jme = netdev_priv(netdev); 3234 3235 unregister_netdev(netdev); 3236 iounmap(jme->regs); 3237 free_netdev(netdev); 3238 pci_release_regions(pdev); 3239 pci_disable_device(pdev); 3240 3241 } 3242 3243 static void 3244 jme_shutdown(struct pci_dev *pdev) 3245 { 3246 struct net_device *netdev = pci_get_drvdata(pdev); 3247 struct jme_adapter *jme = netdev_priv(netdev); 3248 3249 jme_powersave_phy(jme); 3250 pci_pme_active(pdev, true); 3251 } 3252 3253 #ifdef CONFIG_PM_SLEEP 3254 static int 3255 jme_suspend(struct device *dev) 3256 { 3257 struct pci_dev *pdev = to_pci_dev(dev); 3258 struct net_device *netdev = pci_get_drvdata(pdev); 3259 struct jme_adapter *jme = netdev_priv(netdev); 3260 3261 if (!netif_running(netdev)) 3262 return 0; 3263 3264 atomic_dec(&jme->link_changing); 3265 3266 netif_device_detach(netdev); 3267 netif_stop_queue(netdev); 3268 jme_stop_irq(jme); 3269 3270 tasklet_disable(&jme->txclean_task); 3271 tasklet_disable(&jme->rxclean_task); 3272 tasklet_disable(&jme->rxempty_task); 3273 3274 if (netif_carrier_ok(netdev)) { 3275 if (test_bit(JME_FLAG_POLL, &jme->flags)) 3276 jme_polling_mode(jme); 3277 3278 jme_stop_pcc_timer(jme); 3279 jme_disable_rx_engine(jme); 3280 jme_disable_tx_engine(jme); 3281 jme_reset_mac_processor(jme); 3282 jme_free_rx_resources(jme); 3283 jme_free_tx_resources(jme); 3284 netif_carrier_off(netdev); 3285 jme->phylink = 0; 3286 } 3287 3288 tasklet_enable(&jme->txclean_task); 3289 tasklet_enable(&jme->rxclean_task); 3290 tasklet_enable(&jme->rxempty_task); 3291 3292 jme_powersave_phy(jme); 3293 3294 return 0; 3295 } 3296 3297 static int 3298 jme_resume(struct device *dev) 3299 { 3300 struct pci_dev *pdev = to_pci_dev(dev); 3301 struct net_device *netdev = pci_get_drvdata(pdev); 3302 struct jme_adapter *jme = netdev_priv(netdev); 3303 3304 if (!netif_running(netdev)) 3305 return 0; 3306 3307 jme_clear_pm(jme); 3308 jme_phy_on(jme); 3309 if (test_bit(JME_FLAG_SSET, &jme->flags)) 3310 jme_set_settings(netdev, &jme->old_ecmd); 3311 else 3312 jme_reset_phy_processor(jme); 3313 jme_phy_calibration(jme); 3314 jme_phy_setEA(jme); 3315 jme_start_irq(jme); 3316 netif_device_attach(netdev); 3317 3318 atomic_inc(&jme->link_changing); 3319 3320 jme_reset_link(jme); 3321 3322 return 0; 3323 } 3324 3325 static SIMPLE_DEV_PM_OPS(jme_pm_ops, jme_suspend, jme_resume); 3326 #define JME_PM_OPS (&jme_pm_ops) 3327 3328 #else 3329 3330 #define JME_PM_OPS NULL 3331 #endif 3332 3333 static const struct pci_device_id jme_pci_tbl[] = { 3334 { PCI_VDEVICE(JMICRON, PCI_DEVICE_ID_JMICRON_JMC250) }, 3335 { PCI_VDEVICE(JMICRON, PCI_DEVICE_ID_JMICRON_JMC260) }, 3336 { } 3337 }; 3338 3339 static struct pci_driver jme_driver = { 3340 .name = DRV_NAME, 3341 .id_table = jme_pci_tbl, 3342 .probe = jme_init_one, 3343 .remove = jme_remove_one, 3344 .shutdown = jme_shutdown, 3345 .driver.pm = JME_PM_OPS, 3346 }; 3347 3348 static int __init 3349 jme_init_module(void) 3350 { 3351 pr_info("JMicron JMC2XX ethernet driver version %s\n", DRV_VERSION); 3352 return pci_register_driver(&jme_driver); 3353 } 3354 3355 static void __exit 3356 jme_cleanup_module(void) 3357 { 3358 pci_unregister_driver(&jme_driver); 3359 } 3360 3361 module_init(jme_init_module); 3362 module_exit(jme_cleanup_module); 3363 3364 MODULE_AUTHOR("Guo-Fu Tseng <cooldavid@cooldavid.org>"); 3365 MODULE_DESCRIPTION("JMicron JMC2x0 PCI Express Ethernet driver"); 3366 MODULE_LICENSE("GPL"); 3367 MODULE_VERSION(DRV_VERSION); 3368 MODULE_DEVICE_TABLE(pci, jme_pci_tbl); 3369