1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * JMicron JMC2x0 series PCIe Ethernet Linux Device Driver 4 * 5 * Copyright 2008 JMicron Technology Corporation 6 * http://www.jmicron.com/ 7 * Copyright (c) 2009 - 2010 Guo-Fu Tseng <cooldavid@cooldavid.org> 8 * 9 * Author: Guo-Fu Tseng <cooldavid@cooldavid.org> 10 */ 11 12 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 13 14 #include <linux/module.h> 15 #include <linux/kernel.h> 16 #include <linux/pci.h> 17 #include <linux/pci-aspm.h> 18 #include <linux/netdevice.h> 19 #include <linux/etherdevice.h> 20 #include <linux/ethtool.h> 21 #include <linux/mii.h> 22 #include <linux/crc32.h> 23 #include <linux/delay.h> 24 #include <linux/spinlock.h> 25 #include <linux/in.h> 26 #include <linux/ip.h> 27 #include <linux/ipv6.h> 28 #include <linux/tcp.h> 29 #include <linux/udp.h> 30 #include <linux/if_vlan.h> 31 #include <linux/slab.h> 32 #include <net/ip6_checksum.h> 33 #include "jme.h" 34 35 static int force_pseudohp = -1; 36 static int no_pseudohp = -1; 37 static int no_extplug = -1; 38 module_param(force_pseudohp, int, 0); 39 MODULE_PARM_DESC(force_pseudohp, 40 "Enable pseudo hot-plug feature manually by driver instead of BIOS."); 41 module_param(no_pseudohp, int, 0); 42 MODULE_PARM_DESC(no_pseudohp, "Disable pseudo hot-plug feature."); 43 module_param(no_extplug, int, 0); 44 MODULE_PARM_DESC(no_extplug, 45 "Do not use external plug signal for pseudo hot-plug."); 46 47 static int 48 jme_mdio_read(struct net_device *netdev, int phy, int reg) 49 { 50 struct jme_adapter *jme = netdev_priv(netdev); 51 int i, val, again = (reg == MII_BMSR) ? 1 : 0; 52 53 read_again: 54 jwrite32(jme, JME_SMI, SMI_OP_REQ | 55 smi_phy_addr(phy) | 56 smi_reg_addr(reg)); 57 58 wmb(); 59 for (i = JME_PHY_TIMEOUT * 50 ; i > 0 ; --i) { 60 udelay(20); 61 val = jread32(jme, JME_SMI); 62 if ((val & SMI_OP_REQ) == 0) 63 break; 64 } 65 66 if (i == 0) { 67 pr_err("phy(%d) read timeout : %d\n", phy, reg); 68 return 0; 69 } 70 71 if (again--) 72 goto read_again; 73 74 return (val & SMI_DATA_MASK) >> SMI_DATA_SHIFT; 75 } 76 77 static void 78 jme_mdio_write(struct net_device *netdev, 79 int phy, int reg, int val) 80 { 81 struct jme_adapter *jme = netdev_priv(netdev); 82 int i; 83 84 jwrite32(jme, JME_SMI, SMI_OP_WRITE | SMI_OP_REQ | 85 ((val << SMI_DATA_SHIFT) & SMI_DATA_MASK) | 86 smi_phy_addr(phy) | smi_reg_addr(reg)); 87 88 wmb(); 89 for (i = JME_PHY_TIMEOUT * 50 ; i > 0 ; --i) { 90 udelay(20); 91 if ((jread32(jme, JME_SMI) & SMI_OP_REQ) == 0) 92 break; 93 } 94 95 if (i == 0) 96 pr_err("phy(%d) write timeout : %d\n", phy, reg); 97 } 98 99 static inline void 100 jme_reset_phy_processor(struct jme_adapter *jme) 101 { 102 u32 val; 103 104 jme_mdio_write(jme->dev, 105 jme->mii_if.phy_id, 106 MII_ADVERTISE, ADVERTISE_ALL | 107 ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM); 108 109 if (jme->pdev->device == PCI_DEVICE_ID_JMICRON_JMC250) 110 jme_mdio_write(jme->dev, 111 jme->mii_if.phy_id, 112 MII_CTRL1000, 113 ADVERTISE_1000FULL | ADVERTISE_1000HALF); 114 115 val = jme_mdio_read(jme->dev, 116 jme->mii_if.phy_id, 117 MII_BMCR); 118 119 jme_mdio_write(jme->dev, 120 jme->mii_if.phy_id, 121 MII_BMCR, val | BMCR_RESET); 122 } 123 124 static void 125 jme_setup_wakeup_frame(struct jme_adapter *jme, 126 const u32 *mask, u32 crc, int fnr) 127 { 128 int i; 129 130 /* 131 * Setup CRC pattern 132 */ 133 jwrite32(jme, JME_WFOI, WFOI_CRC_SEL | (fnr & WFOI_FRAME_SEL)); 134 wmb(); 135 jwrite32(jme, JME_WFODP, crc); 136 wmb(); 137 138 /* 139 * Setup Mask 140 */ 141 for (i = 0 ; i < WAKEUP_FRAME_MASK_DWNR ; ++i) { 142 jwrite32(jme, JME_WFOI, 143 ((i << WFOI_MASK_SHIFT) & WFOI_MASK_SEL) | 144 (fnr & WFOI_FRAME_SEL)); 145 wmb(); 146 jwrite32(jme, JME_WFODP, mask[i]); 147 wmb(); 148 } 149 } 150 151 static inline void 152 jme_mac_rxclk_off(struct jme_adapter *jme) 153 { 154 jme->reg_gpreg1 |= GPREG1_RXCLKOFF; 155 jwrite32f(jme, JME_GPREG1, jme->reg_gpreg1); 156 } 157 158 static inline void 159 jme_mac_rxclk_on(struct jme_adapter *jme) 160 { 161 jme->reg_gpreg1 &= ~GPREG1_RXCLKOFF; 162 jwrite32f(jme, JME_GPREG1, jme->reg_gpreg1); 163 } 164 165 static inline void 166 jme_mac_txclk_off(struct jme_adapter *jme) 167 { 168 jme->reg_ghc &= ~(GHC_TO_CLK_SRC | GHC_TXMAC_CLK_SRC); 169 jwrite32f(jme, JME_GHC, jme->reg_ghc); 170 } 171 172 static inline void 173 jme_mac_txclk_on(struct jme_adapter *jme) 174 { 175 u32 speed = jme->reg_ghc & GHC_SPEED; 176 if (speed == GHC_SPEED_1000M) 177 jme->reg_ghc |= GHC_TO_CLK_GPHY | GHC_TXMAC_CLK_GPHY; 178 else 179 jme->reg_ghc |= GHC_TO_CLK_PCIE | GHC_TXMAC_CLK_PCIE; 180 jwrite32f(jme, JME_GHC, jme->reg_ghc); 181 } 182 183 static inline void 184 jme_reset_ghc_speed(struct jme_adapter *jme) 185 { 186 jme->reg_ghc &= ~(GHC_SPEED | GHC_DPX); 187 jwrite32f(jme, JME_GHC, jme->reg_ghc); 188 } 189 190 static inline void 191 jme_reset_250A2_workaround(struct jme_adapter *jme) 192 { 193 jme->reg_gpreg1 &= ~(GPREG1_HALFMODEPATCH | 194 GPREG1_RSSPATCH); 195 jwrite32(jme, JME_GPREG1, jme->reg_gpreg1); 196 } 197 198 static inline void 199 jme_assert_ghc_reset(struct jme_adapter *jme) 200 { 201 jme->reg_ghc |= GHC_SWRST; 202 jwrite32f(jme, JME_GHC, jme->reg_ghc); 203 } 204 205 static inline void 206 jme_clear_ghc_reset(struct jme_adapter *jme) 207 { 208 jme->reg_ghc &= ~GHC_SWRST; 209 jwrite32f(jme, JME_GHC, jme->reg_ghc); 210 } 211 212 static void 213 jme_reset_mac_processor(struct jme_adapter *jme) 214 { 215 static const u32 mask[WAKEUP_FRAME_MASK_DWNR] = {0, 0, 0, 0}; 216 u32 crc = 0xCDCDCDCD; 217 u32 gpreg0; 218 int i; 219 220 jme_reset_ghc_speed(jme); 221 jme_reset_250A2_workaround(jme); 222 223 jme_mac_rxclk_on(jme); 224 jme_mac_txclk_on(jme); 225 udelay(1); 226 jme_assert_ghc_reset(jme); 227 udelay(1); 228 jme_mac_rxclk_off(jme); 229 jme_mac_txclk_off(jme); 230 udelay(1); 231 jme_clear_ghc_reset(jme); 232 udelay(1); 233 jme_mac_rxclk_on(jme); 234 jme_mac_txclk_on(jme); 235 udelay(1); 236 jme_mac_rxclk_off(jme); 237 jme_mac_txclk_off(jme); 238 239 jwrite32(jme, JME_RXDBA_LO, 0x00000000); 240 jwrite32(jme, JME_RXDBA_HI, 0x00000000); 241 jwrite32(jme, JME_RXQDC, 0x00000000); 242 jwrite32(jme, JME_RXNDA, 0x00000000); 243 jwrite32(jme, JME_TXDBA_LO, 0x00000000); 244 jwrite32(jme, JME_TXDBA_HI, 0x00000000); 245 jwrite32(jme, JME_TXQDC, 0x00000000); 246 jwrite32(jme, JME_TXNDA, 0x00000000); 247 248 jwrite32(jme, JME_RXMCHT_LO, 0x00000000); 249 jwrite32(jme, JME_RXMCHT_HI, 0x00000000); 250 for (i = 0 ; i < WAKEUP_FRAME_NR ; ++i) 251 jme_setup_wakeup_frame(jme, mask, crc, i); 252 if (jme->fpgaver) 253 gpreg0 = GPREG0_DEFAULT | GPREG0_LNKINTPOLL; 254 else 255 gpreg0 = GPREG0_DEFAULT; 256 jwrite32(jme, JME_GPREG0, gpreg0); 257 } 258 259 static inline void 260 jme_clear_pm_enable_wol(struct jme_adapter *jme) 261 { 262 jwrite32(jme, JME_PMCS, PMCS_STMASK | jme->reg_pmcs); 263 } 264 265 static inline void 266 jme_clear_pm_disable_wol(struct jme_adapter *jme) 267 { 268 jwrite32(jme, JME_PMCS, PMCS_STMASK); 269 } 270 271 static int 272 jme_reload_eeprom(struct jme_adapter *jme) 273 { 274 u32 val; 275 int i; 276 277 val = jread32(jme, JME_SMBCSR); 278 279 if (val & SMBCSR_EEPROMD) { 280 val |= SMBCSR_CNACK; 281 jwrite32(jme, JME_SMBCSR, val); 282 val |= SMBCSR_RELOAD; 283 jwrite32(jme, JME_SMBCSR, val); 284 mdelay(12); 285 286 for (i = JME_EEPROM_RELOAD_TIMEOUT; i > 0; --i) { 287 mdelay(1); 288 if ((jread32(jme, JME_SMBCSR) & SMBCSR_RELOAD) == 0) 289 break; 290 } 291 292 if (i == 0) { 293 pr_err("eeprom reload timeout\n"); 294 return -EIO; 295 } 296 } 297 298 return 0; 299 } 300 301 static void 302 jme_load_macaddr(struct net_device *netdev) 303 { 304 struct jme_adapter *jme = netdev_priv(netdev); 305 unsigned char macaddr[ETH_ALEN]; 306 u32 val; 307 308 spin_lock_bh(&jme->macaddr_lock); 309 val = jread32(jme, JME_RXUMA_LO); 310 macaddr[0] = (val >> 0) & 0xFF; 311 macaddr[1] = (val >> 8) & 0xFF; 312 macaddr[2] = (val >> 16) & 0xFF; 313 macaddr[3] = (val >> 24) & 0xFF; 314 val = jread32(jme, JME_RXUMA_HI); 315 macaddr[4] = (val >> 0) & 0xFF; 316 macaddr[5] = (val >> 8) & 0xFF; 317 memcpy(netdev->dev_addr, macaddr, ETH_ALEN); 318 spin_unlock_bh(&jme->macaddr_lock); 319 } 320 321 static inline void 322 jme_set_rx_pcc(struct jme_adapter *jme, int p) 323 { 324 switch (p) { 325 case PCC_OFF: 326 jwrite32(jme, JME_PCCRX0, 327 ((PCC_OFF_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) | 328 ((PCC_OFF_CNT << PCCRX_SHIFT) & PCCRX_MASK)); 329 break; 330 case PCC_P1: 331 jwrite32(jme, JME_PCCRX0, 332 ((PCC_P1_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) | 333 ((PCC_P1_CNT << PCCRX_SHIFT) & PCCRX_MASK)); 334 break; 335 case PCC_P2: 336 jwrite32(jme, JME_PCCRX0, 337 ((PCC_P2_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) | 338 ((PCC_P2_CNT << PCCRX_SHIFT) & PCCRX_MASK)); 339 break; 340 case PCC_P3: 341 jwrite32(jme, JME_PCCRX0, 342 ((PCC_P3_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) | 343 ((PCC_P3_CNT << PCCRX_SHIFT) & PCCRX_MASK)); 344 break; 345 default: 346 break; 347 } 348 wmb(); 349 350 if (!(test_bit(JME_FLAG_POLL, &jme->flags))) 351 netif_info(jme, rx_status, jme->dev, "Switched to PCC_P%d\n", p); 352 } 353 354 static void 355 jme_start_irq(struct jme_adapter *jme) 356 { 357 register struct dynpcc_info *dpi = &(jme->dpi); 358 359 jme_set_rx_pcc(jme, PCC_P1); 360 dpi->cur = PCC_P1; 361 dpi->attempt = PCC_P1; 362 dpi->cnt = 0; 363 364 jwrite32(jme, JME_PCCTX, 365 ((PCC_TX_TO << PCCTXTO_SHIFT) & PCCTXTO_MASK) | 366 ((PCC_TX_CNT << PCCTX_SHIFT) & PCCTX_MASK) | 367 PCCTXQ0_EN 368 ); 369 370 /* 371 * Enable Interrupts 372 */ 373 jwrite32(jme, JME_IENS, INTR_ENABLE); 374 } 375 376 static inline void 377 jme_stop_irq(struct jme_adapter *jme) 378 { 379 /* 380 * Disable Interrupts 381 */ 382 jwrite32f(jme, JME_IENC, INTR_ENABLE); 383 } 384 385 static u32 386 jme_linkstat_from_phy(struct jme_adapter *jme) 387 { 388 u32 phylink, bmsr; 389 390 phylink = jme_mdio_read(jme->dev, jme->mii_if.phy_id, 17); 391 bmsr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMSR); 392 if (bmsr & BMSR_ANCOMP) 393 phylink |= PHY_LINK_AUTONEG_COMPLETE; 394 395 return phylink; 396 } 397 398 static inline void 399 jme_set_phyfifo_5level(struct jme_adapter *jme) 400 { 401 jme_mdio_write(jme->dev, jme->mii_if.phy_id, 27, 0x0004); 402 } 403 404 static inline void 405 jme_set_phyfifo_8level(struct jme_adapter *jme) 406 { 407 jme_mdio_write(jme->dev, jme->mii_if.phy_id, 27, 0x0000); 408 } 409 410 static int 411 jme_check_link(struct net_device *netdev, int testonly) 412 { 413 struct jme_adapter *jme = netdev_priv(netdev); 414 u32 phylink, cnt = JME_SPDRSV_TIMEOUT, bmcr; 415 char linkmsg[64]; 416 int rc = 0; 417 418 linkmsg[0] = '\0'; 419 420 if (jme->fpgaver) 421 phylink = jme_linkstat_from_phy(jme); 422 else 423 phylink = jread32(jme, JME_PHY_LINK); 424 425 if (phylink & PHY_LINK_UP) { 426 if (!(phylink & PHY_LINK_AUTONEG_COMPLETE)) { 427 /* 428 * If we did not enable AN 429 * Speed/Duplex Info should be obtained from SMI 430 */ 431 phylink = PHY_LINK_UP; 432 433 bmcr = jme_mdio_read(jme->dev, 434 jme->mii_if.phy_id, 435 MII_BMCR); 436 437 phylink |= ((bmcr & BMCR_SPEED1000) && 438 (bmcr & BMCR_SPEED100) == 0) ? 439 PHY_LINK_SPEED_1000M : 440 (bmcr & BMCR_SPEED100) ? 441 PHY_LINK_SPEED_100M : 442 PHY_LINK_SPEED_10M; 443 444 phylink |= (bmcr & BMCR_FULLDPLX) ? 445 PHY_LINK_DUPLEX : 0; 446 447 strcat(linkmsg, "Forced: "); 448 } else { 449 /* 450 * Keep polling for speed/duplex resolve complete 451 */ 452 while (!(phylink & PHY_LINK_SPEEDDPU_RESOLVED) && 453 --cnt) { 454 455 udelay(1); 456 457 if (jme->fpgaver) 458 phylink = jme_linkstat_from_phy(jme); 459 else 460 phylink = jread32(jme, JME_PHY_LINK); 461 } 462 if (!cnt) 463 pr_err("Waiting speed resolve timeout\n"); 464 465 strcat(linkmsg, "ANed: "); 466 } 467 468 if (jme->phylink == phylink) { 469 rc = 1; 470 goto out; 471 } 472 if (testonly) 473 goto out; 474 475 jme->phylink = phylink; 476 477 /* 478 * The speed/duplex setting of jme->reg_ghc already cleared 479 * by jme_reset_mac_processor() 480 */ 481 switch (phylink & PHY_LINK_SPEED_MASK) { 482 case PHY_LINK_SPEED_10M: 483 jme->reg_ghc |= GHC_SPEED_10M; 484 strcat(linkmsg, "10 Mbps, "); 485 break; 486 case PHY_LINK_SPEED_100M: 487 jme->reg_ghc |= GHC_SPEED_100M; 488 strcat(linkmsg, "100 Mbps, "); 489 break; 490 case PHY_LINK_SPEED_1000M: 491 jme->reg_ghc |= GHC_SPEED_1000M; 492 strcat(linkmsg, "1000 Mbps, "); 493 break; 494 default: 495 break; 496 } 497 498 if (phylink & PHY_LINK_DUPLEX) { 499 jwrite32(jme, JME_TXMCS, TXMCS_DEFAULT); 500 jwrite32(jme, JME_TXTRHD, TXTRHD_FULLDUPLEX); 501 jme->reg_ghc |= GHC_DPX; 502 } else { 503 jwrite32(jme, JME_TXMCS, TXMCS_DEFAULT | 504 TXMCS_BACKOFF | 505 TXMCS_CARRIERSENSE | 506 TXMCS_COLLISION); 507 jwrite32(jme, JME_TXTRHD, TXTRHD_HALFDUPLEX); 508 } 509 510 jwrite32(jme, JME_GHC, jme->reg_ghc); 511 512 if (is_buggy250(jme->pdev->device, jme->chiprev)) { 513 jme->reg_gpreg1 &= ~(GPREG1_HALFMODEPATCH | 514 GPREG1_RSSPATCH); 515 if (!(phylink & PHY_LINK_DUPLEX)) 516 jme->reg_gpreg1 |= GPREG1_HALFMODEPATCH; 517 switch (phylink & PHY_LINK_SPEED_MASK) { 518 case PHY_LINK_SPEED_10M: 519 jme_set_phyfifo_8level(jme); 520 jme->reg_gpreg1 |= GPREG1_RSSPATCH; 521 break; 522 case PHY_LINK_SPEED_100M: 523 jme_set_phyfifo_5level(jme); 524 jme->reg_gpreg1 |= GPREG1_RSSPATCH; 525 break; 526 case PHY_LINK_SPEED_1000M: 527 jme_set_phyfifo_8level(jme); 528 break; 529 default: 530 break; 531 } 532 } 533 jwrite32(jme, JME_GPREG1, jme->reg_gpreg1); 534 535 strcat(linkmsg, (phylink & PHY_LINK_DUPLEX) ? 536 "Full-Duplex, " : 537 "Half-Duplex, "); 538 strcat(linkmsg, (phylink & PHY_LINK_MDI_STAT) ? 539 "MDI-X" : 540 "MDI"); 541 netif_info(jme, link, jme->dev, "Link is up at %s\n", linkmsg); 542 netif_carrier_on(netdev); 543 } else { 544 if (testonly) 545 goto out; 546 547 netif_info(jme, link, jme->dev, "Link is down\n"); 548 jme->phylink = 0; 549 netif_carrier_off(netdev); 550 } 551 552 out: 553 return rc; 554 } 555 556 static int 557 jme_setup_tx_resources(struct jme_adapter *jme) 558 { 559 struct jme_ring *txring = &(jme->txring[0]); 560 561 txring->alloc = dma_alloc_coherent(&(jme->pdev->dev), 562 TX_RING_ALLOC_SIZE(jme->tx_ring_size), 563 &(txring->dmaalloc), 564 GFP_ATOMIC); 565 566 if (!txring->alloc) 567 goto err_set_null; 568 569 /* 570 * 16 Bytes align 571 */ 572 txring->desc = (void *)ALIGN((unsigned long)(txring->alloc), 573 RING_DESC_ALIGN); 574 txring->dma = ALIGN(txring->dmaalloc, RING_DESC_ALIGN); 575 txring->next_to_use = 0; 576 atomic_set(&txring->next_to_clean, 0); 577 atomic_set(&txring->nr_free, jme->tx_ring_size); 578 579 txring->bufinf = kcalloc(jme->tx_ring_size, 580 sizeof(struct jme_buffer_info), 581 GFP_ATOMIC); 582 if (unlikely(!(txring->bufinf))) 583 goto err_free_txring; 584 585 /* 586 * Initialize Transmit Descriptors 587 */ 588 memset(txring->alloc, 0, TX_RING_ALLOC_SIZE(jme->tx_ring_size)); 589 590 return 0; 591 592 err_free_txring: 593 dma_free_coherent(&(jme->pdev->dev), 594 TX_RING_ALLOC_SIZE(jme->tx_ring_size), 595 txring->alloc, 596 txring->dmaalloc); 597 598 err_set_null: 599 txring->desc = NULL; 600 txring->dmaalloc = 0; 601 txring->dma = 0; 602 txring->bufinf = NULL; 603 604 return -ENOMEM; 605 } 606 607 static void 608 jme_free_tx_resources(struct jme_adapter *jme) 609 { 610 int i; 611 struct jme_ring *txring = &(jme->txring[0]); 612 struct jme_buffer_info *txbi; 613 614 if (txring->alloc) { 615 if (txring->bufinf) { 616 for (i = 0 ; i < jme->tx_ring_size ; ++i) { 617 txbi = txring->bufinf + i; 618 if (txbi->skb) { 619 dev_kfree_skb(txbi->skb); 620 txbi->skb = NULL; 621 } 622 txbi->mapping = 0; 623 txbi->len = 0; 624 txbi->nr_desc = 0; 625 txbi->start_xmit = 0; 626 } 627 kfree(txring->bufinf); 628 } 629 630 dma_free_coherent(&(jme->pdev->dev), 631 TX_RING_ALLOC_SIZE(jme->tx_ring_size), 632 txring->alloc, 633 txring->dmaalloc); 634 635 txring->alloc = NULL; 636 txring->desc = NULL; 637 txring->dmaalloc = 0; 638 txring->dma = 0; 639 txring->bufinf = NULL; 640 } 641 txring->next_to_use = 0; 642 atomic_set(&txring->next_to_clean, 0); 643 atomic_set(&txring->nr_free, 0); 644 } 645 646 static inline void 647 jme_enable_tx_engine(struct jme_adapter *jme) 648 { 649 /* 650 * Select Queue 0 651 */ 652 jwrite32(jme, JME_TXCS, TXCS_DEFAULT | TXCS_SELECT_QUEUE0); 653 wmb(); 654 655 /* 656 * Setup TX Queue 0 DMA Bass Address 657 */ 658 jwrite32(jme, JME_TXDBA_LO, (__u64)jme->txring[0].dma & 0xFFFFFFFFUL); 659 jwrite32(jme, JME_TXDBA_HI, (__u64)(jme->txring[0].dma) >> 32); 660 jwrite32(jme, JME_TXNDA, (__u64)jme->txring[0].dma & 0xFFFFFFFFUL); 661 662 /* 663 * Setup TX Descptor Count 664 */ 665 jwrite32(jme, JME_TXQDC, jme->tx_ring_size); 666 667 /* 668 * Enable TX Engine 669 */ 670 wmb(); 671 jwrite32f(jme, JME_TXCS, jme->reg_txcs | 672 TXCS_SELECT_QUEUE0 | 673 TXCS_ENABLE); 674 675 /* 676 * Start clock for TX MAC Processor 677 */ 678 jme_mac_txclk_on(jme); 679 } 680 681 static inline void 682 jme_disable_tx_engine(struct jme_adapter *jme) 683 { 684 int i; 685 u32 val; 686 687 /* 688 * Disable TX Engine 689 */ 690 jwrite32(jme, JME_TXCS, jme->reg_txcs | TXCS_SELECT_QUEUE0); 691 wmb(); 692 693 val = jread32(jme, JME_TXCS); 694 for (i = JME_TX_DISABLE_TIMEOUT ; (val & TXCS_ENABLE) && i > 0 ; --i) { 695 mdelay(1); 696 val = jread32(jme, JME_TXCS); 697 rmb(); 698 } 699 700 if (!i) 701 pr_err("Disable TX engine timeout\n"); 702 703 /* 704 * Stop clock for TX MAC Processor 705 */ 706 jme_mac_txclk_off(jme); 707 } 708 709 static void 710 jme_set_clean_rxdesc(struct jme_adapter *jme, int i) 711 { 712 struct jme_ring *rxring = &(jme->rxring[0]); 713 register struct rxdesc *rxdesc = rxring->desc; 714 struct jme_buffer_info *rxbi = rxring->bufinf; 715 rxdesc += i; 716 rxbi += i; 717 718 rxdesc->dw[0] = 0; 719 rxdesc->dw[1] = 0; 720 rxdesc->desc1.bufaddrh = cpu_to_le32((__u64)rxbi->mapping >> 32); 721 rxdesc->desc1.bufaddrl = cpu_to_le32( 722 (__u64)rxbi->mapping & 0xFFFFFFFFUL); 723 rxdesc->desc1.datalen = cpu_to_le16(rxbi->len); 724 if (jme->dev->features & NETIF_F_HIGHDMA) 725 rxdesc->desc1.flags = RXFLAG_64BIT; 726 wmb(); 727 rxdesc->desc1.flags |= RXFLAG_OWN | RXFLAG_INT; 728 } 729 730 static int 731 jme_make_new_rx_buf(struct jme_adapter *jme, int i) 732 { 733 struct jme_ring *rxring = &(jme->rxring[0]); 734 struct jme_buffer_info *rxbi = rxring->bufinf + i; 735 struct sk_buff *skb; 736 dma_addr_t mapping; 737 738 skb = netdev_alloc_skb(jme->dev, 739 jme->dev->mtu + RX_EXTRA_LEN); 740 if (unlikely(!skb)) 741 return -ENOMEM; 742 743 mapping = pci_map_page(jme->pdev, virt_to_page(skb->data), 744 offset_in_page(skb->data), skb_tailroom(skb), 745 PCI_DMA_FROMDEVICE); 746 if (unlikely(pci_dma_mapping_error(jme->pdev, mapping))) { 747 dev_kfree_skb(skb); 748 return -ENOMEM; 749 } 750 751 if (likely(rxbi->mapping)) 752 pci_unmap_page(jme->pdev, rxbi->mapping, 753 rxbi->len, PCI_DMA_FROMDEVICE); 754 755 rxbi->skb = skb; 756 rxbi->len = skb_tailroom(skb); 757 rxbi->mapping = mapping; 758 return 0; 759 } 760 761 static void 762 jme_free_rx_buf(struct jme_adapter *jme, int i) 763 { 764 struct jme_ring *rxring = &(jme->rxring[0]); 765 struct jme_buffer_info *rxbi = rxring->bufinf; 766 rxbi += i; 767 768 if (rxbi->skb) { 769 pci_unmap_page(jme->pdev, 770 rxbi->mapping, 771 rxbi->len, 772 PCI_DMA_FROMDEVICE); 773 dev_kfree_skb(rxbi->skb); 774 rxbi->skb = NULL; 775 rxbi->mapping = 0; 776 rxbi->len = 0; 777 } 778 } 779 780 static void 781 jme_free_rx_resources(struct jme_adapter *jme) 782 { 783 int i; 784 struct jme_ring *rxring = &(jme->rxring[0]); 785 786 if (rxring->alloc) { 787 if (rxring->bufinf) { 788 for (i = 0 ; i < jme->rx_ring_size ; ++i) 789 jme_free_rx_buf(jme, i); 790 kfree(rxring->bufinf); 791 } 792 793 dma_free_coherent(&(jme->pdev->dev), 794 RX_RING_ALLOC_SIZE(jme->rx_ring_size), 795 rxring->alloc, 796 rxring->dmaalloc); 797 rxring->alloc = NULL; 798 rxring->desc = NULL; 799 rxring->dmaalloc = 0; 800 rxring->dma = 0; 801 rxring->bufinf = NULL; 802 } 803 rxring->next_to_use = 0; 804 atomic_set(&rxring->next_to_clean, 0); 805 } 806 807 static int 808 jme_setup_rx_resources(struct jme_adapter *jme) 809 { 810 int i; 811 struct jme_ring *rxring = &(jme->rxring[0]); 812 813 rxring->alloc = dma_alloc_coherent(&(jme->pdev->dev), 814 RX_RING_ALLOC_SIZE(jme->rx_ring_size), 815 &(rxring->dmaalloc), 816 GFP_ATOMIC); 817 if (!rxring->alloc) 818 goto err_set_null; 819 820 /* 821 * 16 Bytes align 822 */ 823 rxring->desc = (void *)ALIGN((unsigned long)(rxring->alloc), 824 RING_DESC_ALIGN); 825 rxring->dma = ALIGN(rxring->dmaalloc, RING_DESC_ALIGN); 826 rxring->next_to_use = 0; 827 atomic_set(&rxring->next_to_clean, 0); 828 829 rxring->bufinf = kcalloc(jme->rx_ring_size, 830 sizeof(struct jme_buffer_info), 831 GFP_ATOMIC); 832 if (unlikely(!(rxring->bufinf))) 833 goto err_free_rxring; 834 835 /* 836 * Initiallize Receive Descriptors 837 */ 838 for (i = 0 ; i < jme->rx_ring_size ; ++i) { 839 if (unlikely(jme_make_new_rx_buf(jme, i))) { 840 jme_free_rx_resources(jme); 841 return -ENOMEM; 842 } 843 844 jme_set_clean_rxdesc(jme, i); 845 } 846 847 return 0; 848 849 err_free_rxring: 850 dma_free_coherent(&(jme->pdev->dev), 851 RX_RING_ALLOC_SIZE(jme->rx_ring_size), 852 rxring->alloc, 853 rxring->dmaalloc); 854 err_set_null: 855 rxring->desc = NULL; 856 rxring->dmaalloc = 0; 857 rxring->dma = 0; 858 rxring->bufinf = NULL; 859 860 return -ENOMEM; 861 } 862 863 static inline void 864 jme_enable_rx_engine(struct jme_adapter *jme) 865 { 866 /* 867 * Select Queue 0 868 */ 869 jwrite32(jme, JME_RXCS, jme->reg_rxcs | 870 RXCS_QUEUESEL_Q0); 871 wmb(); 872 873 /* 874 * Setup RX DMA Bass Address 875 */ 876 jwrite32(jme, JME_RXDBA_LO, (__u64)(jme->rxring[0].dma) & 0xFFFFFFFFUL); 877 jwrite32(jme, JME_RXDBA_HI, (__u64)(jme->rxring[0].dma) >> 32); 878 jwrite32(jme, JME_RXNDA, (__u64)(jme->rxring[0].dma) & 0xFFFFFFFFUL); 879 880 /* 881 * Setup RX Descriptor Count 882 */ 883 jwrite32(jme, JME_RXQDC, jme->rx_ring_size); 884 885 /* 886 * Setup Unicast Filter 887 */ 888 jme_set_unicastaddr(jme->dev); 889 jme_set_multi(jme->dev); 890 891 /* 892 * Enable RX Engine 893 */ 894 wmb(); 895 jwrite32f(jme, JME_RXCS, jme->reg_rxcs | 896 RXCS_QUEUESEL_Q0 | 897 RXCS_ENABLE | 898 RXCS_QST); 899 900 /* 901 * Start clock for RX MAC Processor 902 */ 903 jme_mac_rxclk_on(jme); 904 } 905 906 static inline void 907 jme_restart_rx_engine(struct jme_adapter *jme) 908 { 909 /* 910 * Start RX Engine 911 */ 912 jwrite32(jme, JME_RXCS, jme->reg_rxcs | 913 RXCS_QUEUESEL_Q0 | 914 RXCS_ENABLE | 915 RXCS_QST); 916 } 917 918 static inline void 919 jme_disable_rx_engine(struct jme_adapter *jme) 920 { 921 int i; 922 u32 val; 923 924 /* 925 * Disable RX Engine 926 */ 927 jwrite32(jme, JME_RXCS, jme->reg_rxcs); 928 wmb(); 929 930 val = jread32(jme, JME_RXCS); 931 for (i = JME_RX_DISABLE_TIMEOUT ; (val & RXCS_ENABLE) && i > 0 ; --i) { 932 mdelay(1); 933 val = jread32(jme, JME_RXCS); 934 rmb(); 935 } 936 937 if (!i) 938 pr_err("Disable RX engine timeout\n"); 939 940 /* 941 * Stop clock for RX MAC Processor 942 */ 943 jme_mac_rxclk_off(jme); 944 } 945 946 static u16 947 jme_udpsum(struct sk_buff *skb) 948 { 949 u16 csum = 0xFFFFu; 950 951 if (skb->len < (ETH_HLEN + sizeof(struct iphdr))) 952 return csum; 953 if (skb->protocol != htons(ETH_P_IP)) 954 return csum; 955 skb_set_network_header(skb, ETH_HLEN); 956 if ((ip_hdr(skb)->protocol != IPPROTO_UDP) || 957 (skb->len < (ETH_HLEN + 958 (ip_hdr(skb)->ihl << 2) + 959 sizeof(struct udphdr)))) { 960 skb_reset_network_header(skb); 961 return csum; 962 } 963 skb_set_transport_header(skb, 964 ETH_HLEN + (ip_hdr(skb)->ihl << 2)); 965 csum = udp_hdr(skb)->check; 966 skb_reset_transport_header(skb); 967 skb_reset_network_header(skb); 968 969 return csum; 970 } 971 972 static int 973 jme_rxsum_ok(struct jme_adapter *jme, u16 flags, struct sk_buff *skb) 974 { 975 if (!(flags & (RXWBFLAG_TCPON | RXWBFLAG_UDPON | RXWBFLAG_IPV4))) 976 return false; 977 978 if (unlikely((flags & (RXWBFLAG_MF | RXWBFLAG_TCPON | RXWBFLAG_TCPCS)) 979 == RXWBFLAG_TCPON)) { 980 if (flags & RXWBFLAG_IPV4) 981 netif_err(jme, rx_err, jme->dev, "TCP Checksum error\n"); 982 return false; 983 } 984 985 if (unlikely((flags & (RXWBFLAG_MF | RXWBFLAG_UDPON | RXWBFLAG_UDPCS)) 986 == RXWBFLAG_UDPON) && jme_udpsum(skb)) { 987 if (flags & RXWBFLAG_IPV4) 988 netif_err(jme, rx_err, jme->dev, "UDP Checksum error\n"); 989 return false; 990 } 991 992 if (unlikely((flags & (RXWBFLAG_IPV4 | RXWBFLAG_IPCS)) 993 == RXWBFLAG_IPV4)) { 994 netif_err(jme, rx_err, jme->dev, "IPv4 Checksum error\n"); 995 return false; 996 } 997 998 return true; 999 } 1000 1001 static void 1002 jme_alloc_and_feed_skb(struct jme_adapter *jme, int idx) 1003 { 1004 struct jme_ring *rxring = &(jme->rxring[0]); 1005 struct rxdesc *rxdesc = rxring->desc; 1006 struct jme_buffer_info *rxbi = rxring->bufinf; 1007 struct sk_buff *skb; 1008 int framesize; 1009 1010 rxdesc += idx; 1011 rxbi += idx; 1012 1013 skb = rxbi->skb; 1014 pci_dma_sync_single_for_cpu(jme->pdev, 1015 rxbi->mapping, 1016 rxbi->len, 1017 PCI_DMA_FROMDEVICE); 1018 1019 if (unlikely(jme_make_new_rx_buf(jme, idx))) { 1020 pci_dma_sync_single_for_device(jme->pdev, 1021 rxbi->mapping, 1022 rxbi->len, 1023 PCI_DMA_FROMDEVICE); 1024 1025 ++(NET_STAT(jme).rx_dropped); 1026 } else { 1027 framesize = le16_to_cpu(rxdesc->descwb.framesize) 1028 - RX_PREPAD_SIZE; 1029 1030 skb_reserve(skb, RX_PREPAD_SIZE); 1031 skb_put(skb, framesize); 1032 skb->protocol = eth_type_trans(skb, jme->dev); 1033 1034 if (jme_rxsum_ok(jme, le16_to_cpu(rxdesc->descwb.flags), skb)) 1035 skb->ip_summed = CHECKSUM_UNNECESSARY; 1036 else 1037 skb_checksum_none_assert(skb); 1038 1039 if (rxdesc->descwb.flags & cpu_to_le16(RXWBFLAG_TAGON)) { 1040 u16 vid = le16_to_cpu(rxdesc->descwb.vlan); 1041 1042 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vid); 1043 NET_STAT(jme).rx_bytes += 4; 1044 } 1045 jme->jme_rx(skb); 1046 1047 if ((rxdesc->descwb.flags & cpu_to_le16(RXWBFLAG_DEST)) == 1048 cpu_to_le16(RXWBFLAG_DEST_MUL)) 1049 ++(NET_STAT(jme).multicast); 1050 1051 NET_STAT(jme).rx_bytes += framesize; 1052 ++(NET_STAT(jme).rx_packets); 1053 } 1054 1055 jme_set_clean_rxdesc(jme, idx); 1056 1057 } 1058 1059 static int 1060 jme_process_receive(struct jme_adapter *jme, int limit) 1061 { 1062 struct jme_ring *rxring = &(jme->rxring[0]); 1063 struct rxdesc *rxdesc; 1064 int i, j, ccnt, desccnt, mask = jme->rx_ring_mask; 1065 1066 if (unlikely(!atomic_dec_and_test(&jme->rx_cleaning))) 1067 goto out_inc; 1068 1069 if (unlikely(atomic_read(&jme->link_changing) != 1)) 1070 goto out_inc; 1071 1072 if (unlikely(!netif_carrier_ok(jme->dev))) 1073 goto out_inc; 1074 1075 i = atomic_read(&rxring->next_to_clean); 1076 while (limit > 0) { 1077 rxdesc = rxring->desc; 1078 rxdesc += i; 1079 1080 if ((rxdesc->descwb.flags & cpu_to_le16(RXWBFLAG_OWN)) || 1081 !(rxdesc->descwb.desccnt & RXWBDCNT_WBCPL)) 1082 goto out; 1083 --limit; 1084 1085 rmb(); 1086 desccnt = rxdesc->descwb.desccnt & RXWBDCNT_DCNT; 1087 1088 if (unlikely(desccnt > 1 || 1089 rxdesc->descwb.errstat & RXWBERR_ALLERR)) { 1090 1091 if (rxdesc->descwb.errstat & RXWBERR_CRCERR) 1092 ++(NET_STAT(jme).rx_crc_errors); 1093 else if (rxdesc->descwb.errstat & RXWBERR_OVERUN) 1094 ++(NET_STAT(jme).rx_fifo_errors); 1095 else 1096 ++(NET_STAT(jme).rx_errors); 1097 1098 if (desccnt > 1) 1099 limit -= desccnt - 1; 1100 1101 for (j = i, ccnt = desccnt ; ccnt-- ; ) { 1102 jme_set_clean_rxdesc(jme, j); 1103 j = (j + 1) & (mask); 1104 } 1105 1106 } else { 1107 jme_alloc_and_feed_skb(jme, i); 1108 } 1109 1110 i = (i + desccnt) & (mask); 1111 } 1112 1113 out: 1114 atomic_set(&rxring->next_to_clean, i); 1115 1116 out_inc: 1117 atomic_inc(&jme->rx_cleaning); 1118 1119 return limit > 0 ? limit : 0; 1120 1121 } 1122 1123 static void 1124 jme_attempt_pcc(struct dynpcc_info *dpi, int atmp) 1125 { 1126 if (likely(atmp == dpi->cur)) { 1127 dpi->cnt = 0; 1128 return; 1129 } 1130 1131 if (dpi->attempt == atmp) { 1132 ++(dpi->cnt); 1133 } else { 1134 dpi->attempt = atmp; 1135 dpi->cnt = 0; 1136 } 1137 1138 } 1139 1140 static void 1141 jme_dynamic_pcc(struct jme_adapter *jme) 1142 { 1143 register struct dynpcc_info *dpi = &(jme->dpi); 1144 1145 if ((NET_STAT(jme).rx_bytes - dpi->last_bytes) > PCC_P3_THRESHOLD) 1146 jme_attempt_pcc(dpi, PCC_P3); 1147 else if ((NET_STAT(jme).rx_packets - dpi->last_pkts) > PCC_P2_THRESHOLD || 1148 dpi->intr_cnt > PCC_INTR_THRESHOLD) 1149 jme_attempt_pcc(dpi, PCC_P2); 1150 else 1151 jme_attempt_pcc(dpi, PCC_P1); 1152 1153 if (unlikely(dpi->attempt != dpi->cur && dpi->cnt > 5)) { 1154 if (dpi->attempt < dpi->cur) 1155 tasklet_schedule(&jme->rxclean_task); 1156 jme_set_rx_pcc(jme, dpi->attempt); 1157 dpi->cur = dpi->attempt; 1158 dpi->cnt = 0; 1159 } 1160 } 1161 1162 static void 1163 jme_start_pcc_timer(struct jme_adapter *jme) 1164 { 1165 struct dynpcc_info *dpi = &(jme->dpi); 1166 dpi->last_bytes = NET_STAT(jme).rx_bytes; 1167 dpi->last_pkts = NET_STAT(jme).rx_packets; 1168 dpi->intr_cnt = 0; 1169 jwrite32(jme, JME_TMCSR, 1170 TMCSR_EN | ((0xFFFFFF - PCC_INTERVAL_US) & TMCSR_CNT)); 1171 } 1172 1173 static inline void 1174 jme_stop_pcc_timer(struct jme_adapter *jme) 1175 { 1176 jwrite32(jme, JME_TMCSR, 0); 1177 } 1178 1179 static void 1180 jme_shutdown_nic(struct jme_adapter *jme) 1181 { 1182 u32 phylink; 1183 1184 phylink = jme_linkstat_from_phy(jme); 1185 1186 if (!(phylink & PHY_LINK_UP)) { 1187 /* 1188 * Disable all interrupt before issue timer 1189 */ 1190 jme_stop_irq(jme); 1191 jwrite32(jme, JME_TIMER2, TMCSR_EN | 0xFFFFFE); 1192 } 1193 } 1194 1195 static void 1196 jme_pcc_tasklet(unsigned long arg) 1197 { 1198 struct jme_adapter *jme = (struct jme_adapter *)arg; 1199 struct net_device *netdev = jme->dev; 1200 1201 if (unlikely(test_bit(JME_FLAG_SHUTDOWN, &jme->flags))) { 1202 jme_shutdown_nic(jme); 1203 return; 1204 } 1205 1206 if (unlikely(!netif_carrier_ok(netdev) || 1207 (atomic_read(&jme->link_changing) != 1) 1208 )) { 1209 jme_stop_pcc_timer(jme); 1210 return; 1211 } 1212 1213 if (!(test_bit(JME_FLAG_POLL, &jme->flags))) 1214 jme_dynamic_pcc(jme); 1215 1216 jme_start_pcc_timer(jme); 1217 } 1218 1219 static inline void 1220 jme_polling_mode(struct jme_adapter *jme) 1221 { 1222 jme_set_rx_pcc(jme, PCC_OFF); 1223 } 1224 1225 static inline void 1226 jme_interrupt_mode(struct jme_adapter *jme) 1227 { 1228 jme_set_rx_pcc(jme, PCC_P1); 1229 } 1230 1231 static inline int 1232 jme_pseudo_hotplug_enabled(struct jme_adapter *jme) 1233 { 1234 u32 apmc; 1235 apmc = jread32(jme, JME_APMC); 1236 return apmc & JME_APMC_PSEUDO_HP_EN; 1237 } 1238 1239 static void 1240 jme_start_shutdown_timer(struct jme_adapter *jme) 1241 { 1242 u32 apmc; 1243 1244 apmc = jread32(jme, JME_APMC) | JME_APMC_PCIE_SD_EN; 1245 apmc &= ~JME_APMC_EPIEN_CTRL; 1246 if (!no_extplug) { 1247 jwrite32f(jme, JME_APMC, apmc | JME_APMC_EPIEN_CTRL_EN); 1248 wmb(); 1249 } 1250 jwrite32f(jme, JME_APMC, apmc); 1251 1252 jwrite32f(jme, JME_TIMER2, 0); 1253 set_bit(JME_FLAG_SHUTDOWN, &jme->flags); 1254 jwrite32(jme, JME_TMCSR, 1255 TMCSR_EN | ((0xFFFFFF - APMC_PHP_SHUTDOWN_DELAY) & TMCSR_CNT)); 1256 } 1257 1258 static void 1259 jme_stop_shutdown_timer(struct jme_adapter *jme) 1260 { 1261 u32 apmc; 1262 1263 jwrite32f(jme, JME_TMCSR, 0); 1264 jwrite32f(jme, JME_TIMER2, 0); 1265 clear_bit(JME_FLAG_SHUTDOWN, &jme->flags); 1266 1267 apmc = jread32(jme, JME_APMC); 1268 apmc &= ~(JME_APMC_PCIE_SD_EN | JME_APMC_EPIEN_CTRL); 1269 jwrite32f(jme, JME_APMC, apmc | JME_APMC_EPIEN_CTRL_DIS); 1270 wmb(); 1271 jwrite32f(jme, JME_APMC, apmc); 1272 } 1273 1274 static void 1275 jme_link_change_tasklet(unsigned long arg) 1276 { 1277 struct jme_adapter *jme = (struct jme_adapter *)arg; 1278 struct net_device *netdev = jme->dev; 1279 int rc; 1280 1281 while (!atomic_dec_and_test(&jme->link_changing)) { 1282 atomic_inc(&jme->link_changing); 1283 netif_info(jme, intr, jme->dev, "Get link change lock failed\n"); 1284 while (atomic_read(&jme->link_changing) != 1) 1285 netif_info(jme, intr, jme->dev, "Waiting link change lock\n"); 1286 } 1287 1288 if (jme_check_link(netdev, 1) && jme->old_mtu == netdev->mtu) 1289 goto out; 1290 1291 jme->old_mtu = netdev->mtu; 1292 netif_stop_queue(netdev); 1293 if (jme_pseudo_hotplug_enabled(jme)) 1294 jme_stop_shutdown_timer(jme); 1295 1296 jme_stop_pcc_timer(jme); 1297 tasklet_disable(&jme->txclean_task); 1298 tasklet_disable(&jme->rxclean_task); 1299 tasklet_disable(&jme->rxempty_task); 1300 1301 if (netif_carrier_ok(netdev)) { 1302 jme_disable_rx_engine(jme); 1303 jme_disable_tx_engine(jme); 1304 jme_reset_mac_processor(jme); 1305 jme_free_rx_resources(jme); 1306 jme_free_tx_resources(jme); 1307 1308 if (test_bit(JME_FLAG_POLL, &jme->flags)) 1309 jme_polling_mode(jme); 1310 1311 netif_carrier_off(netdev); 1312 } 1313 1314 jme_check_link(netdev, 0); 1315 if (netif_carrier_ok(netdev)) { 1316 rc = jme_setup_rx_resources(jme); 1317 if (rc) { 1318 pr_err("Allocating resources for RX error, Device STOPPED!\n"); 1319 goto out_enable_tasklet; 1320 } 1321 1322 rc = jme_setup_tx_resources(jme); 1323 if (rc) { 1324 pr_err("Allocating resources for TX error, Device STOPPED!\n"); 1325 goto err_out_free_rx_resources; 1326 } 1327 1328 jme_enable_rx_engine(jme); 1329 jme_enable_tx_engine(jme); 1330 1331 netif_start_queue(netdev); 1332 1333 if (test_bit(JME_FLAG_POLL, &jme->flags)) 1334 jme_interrupt_mode(jme); 1335 1336 jme_start_pcc_timer(jme); 1337 } else if (jme_pseudo_hotplug_enabled(jme)) { 1338 jme_start_shutdown_timer(jme); 1339 } 1340 1341 goto out_enable_tasklet; 1342 1343 err_out_free_rx_resources: 1344 jme_free_rx_resources(jme); 1345 out_enable_tasklet: 1346 tasklet_enable(&jme->txclean_task); 1347 tasklet_enable(&jme->rxclean_task); 1348 tasklet_enable(&jme->rxempty_task); 1349 out: 1350 atomic_inc(&jme->link_changing); 1351 } 1352 1353 static void 1354 jme_rx_clean_tasklet(unsigned long arg) 1355 { 1356 struct jme_adapter *jme = (struct jme_adapter *)arg; 1357 struct dynpcc_info *dpi = &(jme->dpi); 1358 1359 jme_process_receive(jme, jme->rx_ring_size); 1360 ++(dpi->intr_cnt); 1361 1362 } 1363 1364 static int 1365 jme_poll(JME_NAPI_HOLDER(holder), JME_NAPI_WEIGHT(budget)) 1366 { 1367 struct jme_adapter *jme = jme_napi_priv(holder); 1368 int rest; 1369 1370 rest = jme_process_receive(jme, JME_NAPI_WEIGHT_VAL(budget)); 1371 1372 while (atomic_read(&jme->rx_empty) > 0) { 1373 atomic_dec(&jme->rx_empty); 1374 ++(NET_STAT(jme).rx_dropped); 1375 jme_restart_rx_engine(jme); 1376 } 1377 atomic_inc(&jme->rx_empty); 1378 1379 if (rest) { 1380 JME_RX_COMPLETE(netdev, holder); 1381 jme_interrupt_mode(jme); 1382 } 1383 1384 JME_NAPI_WEIGHT_SET(budget, rest); 1385 return JME_NAPI_WEIGHT_VAL(budget) - rest; 1386 } 1387 1388 static void 1389 jme_rx_empty_tasklet(unsigned long arg) 1390 { 1391 struct jme_adapter *jme = (struct jme_adapter *)arg; 1392 1393 if (unlikely(atomic_read(&jme->link_changing) != 1)) 1394 return; 1395 1396 if (unlikely(!netif_carrier_ok(jme->dev))) 1397 return; 1398 1399 netif_info(jme, rx_status, jme->dev, "RX Queue Full!\n"); 1400 1401 jme_rx_clean_tasklet(arg); 1402 1403 while (atomic_read(&jme->rx_empty) > 0) { 1404 atomic_dec(&jme->rx_empty); 1405 ++(NET_STAT(jme).rx_dropped); 1406 jme_restart_rx_engine(jme); 1407 } 1408 atomic_inc(&jme->rx_empty); 1409 } 1410 1411 static void 1412 jme_wake_queue_if_stopped(struct jme_adapter *jme) 1413 { 1414 struct jme_ring *txring = &(jme->txring[0]); 1415 1416 smp_wmb(); 1417 if (unlikely(netif_queue_stopped(jme->dev) && 1418 atomic_read(&txring->nr_free) >= (jme->tx_wake_threshold))) { 1419 netif_info(jme, tx_done, jme->dev, "TX Queue Waked\n"); 1420 netif_wake_queue(jme->dev); 1421 } 1422 1423 } 1424 1425 static void 1426 jme_tx_clean_tasklet(unsigned long arg) 1427 { 1428 struct jme_adapter *jme = (struct jme_adapter *)arg; 1429 struct jme_ring *txring = &(jme->txring[0]); 1430 struct txdesc *txdesc = txring->desc; 1431 struct jme_buffer_info *txbi = txring->bufinf, *ctxbi, *ttxbi; 1432 int i, j, cnt = 0, max, err, mask; 1433 1434 tx_dbg(jme, "Into txclean\n"); 1435 1436 if (unlikely(!atomic_dec_and_test(&jme->tx_cleaning))) 1437 goto out; 1438 1439 if (unlikely(atomic_read(&jme->link_changing) != 1)) 1440 goto out; 1441 1442 if (unlikely(!netif_carrier_ok(jme->dev))) 1443 goto out; 1444 1445 max = jme->tx_ring_size - atomic_read(&txring->nr_free); 1446 mask = jme->tx_ring_mask; 1447 1448 for (i = atomic_read(&txring->next_to_clean) ; cnt < max ; ) { 1449 1450 ctxbi = txbi + i; 1451 1452 if (likely(ctxbi->skb && 1453 !(txdesc[i].descwb.flags & TXWBFLAG_OWN))) { 1454 1455 tx_dbg(jme, "txclean: %d+%d@%lu\n", 1456 i, ctxbi->nr_desc, jiffies); 1457 1458 err = txdesc[i].descwb.flags & TXWBFLAG_ALLERR; 1459 1460 for (j = 1 ; j < ctxbi->nr_desc ; ++j) { 1461 ttxbi = txbi + ((i + j) & (mask)); 1462 txdesc[(i + j) & (mask)].dw[0] = 0; 1463 1464 pci_unmap_page(jme->pdev, 1465 ttxbi->mapping, 1466 ttxbi->len, 1467 PCI_DMA_TODEVICE); 1468 1469 ttxbi->mapping = 0; 1470 ttxbi->len = 0; 1471 } 1472 1473 dev_kfree_skb(ctxbi->skb); 1474 1475 cnt += ctxbi->nr_desc; 1476 1477 if (unlikely(err)) { 1478 ++(NET_STAT(jme).tx_carrier_errors); 1479 } else { 1480 ++(NET_STAT(jme).tx_packets); 1481 NET_STAT(jme).tx_bytes += ctxbi->len; 1482 } 1483 1484 ctxbi->skb = NULL; 1485 ctxbi->len = 0; 1486 ctxbi->start_xmit = 0; 1487 1488 } else { 1489 break; 1490 } 1491 1492 i = (i + ctxbi->nr_desc) & mask; 1493 1494 ctxbi->nr_desc = 0; 1495 } 1496 1497 tx_dbg(jme, "txclean: done %d@%lu\n", i, jiffies); 1498 atomic_set(&txring->next_to_clean, i); 1499 atomic_add(cnt, &txring->nr_free); 1500 1501 jme_wake_queue_if_stopped(jme); 1502 1503 out: 1504 atomic_inc(&jme->tx_cleaning); 1505 } 1506 1507 static void 1508 jme_intr_msi(struct jme_adapter *jme, u32 intrstat) 1509 { 1510 /* 1511 * Disable interrupt 1512 */ 1513 jwrite32f(jme, JME_IENC, INTR_ENABLE); 1514 1515 if (intrstat & (INTR_LINKCH | INTR_SWINTR)) { 1516 /* 1517 * Link change event is critical 1518 * all other events are ignored 1519 */ 1520 jwrite32(jme, JME_IEVE, intrstat); 1521 tasklet_schedule(&jme->linkch_task); 1522 goto out_reenable; 1523 } 1524 1525 if (intrstat & INTR_TMINTR) { 1526 jwrite32(jme, JME_IEVE, INTR_TMINTR); 1527 tasklet_schedule(&jme->pcc_task); 1528 } 1529 1530 if (intrstat & (INTR_PCCTXTO | INTR_PCCTX)) { 1531 jwrite32(jme, JME_IEVE, INTR_PCCTXTO | INTR_PCCTX | INTR_TX0); 1532 tasklet_schedule(&jme->txclean_task); 1533 } 1534 1535 if ((intrstat & (INTR_PCCRX0TO | INTR_PCCRX0 | INTR_RX0EMP))) { 1536 jwrite32(jme, JME_IEVE, (intrstat & (INTR_PCCRX0TO | 1537 INTR_PCCRX0 | 1538 INTR_RX0EMP)) | 1539 INTR_RX0); 1540 } 1541 1542 if (test_bit(JME_FLAG_POLL, &jme->flags)) { 1543 if (intrstat & INTR_RX0EMP) 1544 atomic_inc(&jme->rx_empty); 1545 1546 if ((intrstat & (INTR_PCCRX0TO | INTR_PCCRX0 | INTR_RX0EMP))) { 1547 if (likely(JME_RX_SCHEDULE_PREP(jme))) { 1548 jme_polling_mode(jme); 1549 JME_RX_SCHEDULE(jme); 1550 } 1551 } 1552 } else { 1553 if (intrstat & INTR_RX0EMP) { 1554 atomic_inc(&jme->rx_empty); 1555 tasklet_hi_schedule(&jme->rxempty_task); 1556 } else if (intrstat & (INTR_PCCRX0TO | INTR_PCCRX0)) { 1557 tasklet_hi_schedule(&jme->rxclean_task); 1558 } 1559 } 1560 1561 out_reenable: 1562 /* 1563 * Re-enable interrupt 1564 */ 1565 jwrite32f(jme, JME_IENS, INTR_ENABLE); 1566 } 1567 1568 static irqreturn_t 1569 jme_intr(int irq, void *dev_id) 1570 { 1571 struct net_device *netdev = dev_id; 1572 struct jme_adapter *jme = netdev_priv(netdev); 1573 u32 intrstat; 1574 1575 intrstat = jread32(jme, JME_IEVE); 1576 1577 /* 1578 * Check if it's really an interrupt for us 1579 */ 1580 if (unlikely((intrstat & INTR_ENABLE) == 0)) 1581 return IRQ_NONE; 1582 1583 /* 1584 * Check if the device still exist 1585 */ 1586 if (unlikely(intrstat == ~((typeof(intrstat))0))) 1587 return IRQ_NONE; 1588 1589 jme_intr_msi(jme, intrstat); 1590 1591 return IRQ_HANDLED; 1592 } 1593 1594 static irqreturn_t 1595 jme_msi(int irq, void *dev_id) 1596 { 1597 struct net_device *netdev = dev_id; 1598 struct jme_adapter *jme = netdev_priv(netdev); 1599 u32 intrstat; 1600 1601 intrstat = jread32(jme, JME_IEVE); 1602 1603 jme_intr_msi(jme, intrstat); 1604 1605 return IRQ_HANDLED; 1606 } 1607 1608 static void 1609 jme_reset_link(struct jme_adapter *jme) 1610 { 1611 jwrite32(jme, JME_TMCSR, TMCSR_SWIT); 1612 } 1613 1614 static void 1615 jme_restart_an(struct jme_adapter *jme) 1616 { 1617 u32 bmcr; 1618 1619 spin_lock_bh(&jme->phy_lock); 1620 bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR); 1621 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART); 1622 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, bmcr); 1623 spin_unlock_bh(&jme->phy_lock); 1624 } 1625 1626 static int 1627 jme_request_irq(struct jme_adapter *jme) 1628 { 1629 int rc; 1630 struct net_device *netdev = jme->dev; 1631 irq_handler_t handler = jme_intr; 1632 int irq_flags = IRQF_SHARED; 1633 1634 if (!pci_enable_msi(jme->pdev)) { 1635 set_bit(JME_FLAG_MSI, &jme->flags); 1636 handler = jme_msi; 1637 irq_flags = 0; 1638 } 1639 1640 rc = request_irq(jme->pdev->irq, handler, irq_flags, netdev->name, 1641 netdev); 1642 if (rc) { 1643 netdev_err(netdev, 1644 "Unable to request %s interrupt (return: %d)\n", 1645 test_bit(JME_FLAG_MSI, &jme->flags) ? "MSI" : "INTx", 1646 rc); 1647 1648 if (test_bit(JME_FLAG_MSI, &jme->flags)) { 1649 pci_disable_msi(jme->pdev); 1650 clear_bit(JME_FLAG_MSI, &jme->flags); 1651 } 1652 } else { 1653 netdev->irq = jme->pdev->irq; 1654 } 1655 1656 return rc; 1657 } 1658 1659 static void 1660 jme_free_irq(struct jme_adapter *jme) 1661 { 1662 free_irq(jme->pdev->irq, jme->dev); 1663 if (test_bit(JME_FLAG_MSI, &jme->flags)) { 1664 pci_disable_msi(jme->pdev); 1665 clear_bit(JME_FLAG_MSI, &jme->flags); 1666 jme->dev->irq = jme->pdev->irq; 1667 } 1668 } 1669 1670 static inline void 1671 jme_new_phy_on(struct jme_adapter *jme) 1672 { 1673 u32 reg; 1674 1675 reg = jread32(jme, JME_PHY_PWR); 1676 reg &= ~(PHY_PWR_DWN1SEL | PHY_PWR_DWN1SW | 1677 PHY_PWR_DWN2 | PHY_PWR_CLKSEL); 1678 jwrite32(jme, JME_PHY_PWR, reg); 1679 1680 pci_read_config_dword(jme->pdev, PCI_PRIV_PE1, ®); 1681 reg &= ~PE1_GPREG0_PBG; 1682 reg |= PE1_GPREG0_ENBG; 1683 pci_write_config_dword(jme->pdev, PCI_PRIV_PE1, reg); 1684 } 1685 1686 static inline void 1687 jme_new_phy_off(struct jme_adapter *jme) 1688 { 1689 u32 reg; 1690 1691 reg = jread32(jme, JME_PHY_PWR); 1692 reg |= PHY_PWR_DWN1SEL | PHY_PWR_DWN1SW | 1693 PHY_PWR_DWN2 | PHY_PWR_CLKSEL; 1694 jwrite32(jme, JME_PHY_PWR, reg); 1695 1696 pci_read_config_dword(jme->pdev, PCI_PRIV_PE1, ®); 1697 reg &= ~PE1_GPREG0_PBG; 1698 reg |= PE1_GPREG0_PDD3COLD; 1699 pci_write_config_dword(jme->pdev, PCI_PRIV_PE1, reg); 1700 } 1701 1702 static inline void 1703 jme_phy_on(struct jme_adapter *jme) 1704 { 1705 u32 bmcr; 1706 1707 bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR); 1708 bmcr &= ~BMCR_PDOWN; 1709 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, bmcr); 1710 1711 if (new_phy_power_ctrl(jme->chip_main_rev)) 1712 jme_new_phy_on(jme); 1713 } 1714 1715 static inline void 1716 jme_phy_off(struct jme_adapter *jme) 1717 { 1718 u32 bmcr; 1719 1720 bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR); 1721 bmcr |= BMCR_PDOWN; 1722 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, bmcr); 1723 1724 if (new_phy_power_ctrl(jme->chip_main_rev)) 1725 jme_new_phy_off(jme); 1726 } 1727 1728 static int 1729 jme_phy_specreg_read(struct jme_adapter *jme, u32 specreg) 1730 { 1731 u32 phy_addr; 1732 1733 phy_addr = JM_PHY_SPEC_REG_READ | specreg; 1734 jme_mdio_write(jme->dev, jme->mii_if.phy_id, JM_PHY_SPEC_ADDR_REG, 1735 phy_addr); 1736 return jme_mdio_read(jme->dev, jme->mii_if.phy_id, 1737 JM_PHY_SPEC_DATA_REG); 1738 } 1739 1740 static void 1741 jme_phy_specreg_write(struct jme_adapter *jme, u32 ext_reg, u32 phy_data) 1742 { 1743 u32 phy_addr; 1744 1745 phy_addr = JM_PHY_SPEC_REG_WRITE | ext_reg; 1746 jme_mdio_write(jme->dev, jme->mii_if.phy_id, JM_PHY_SPEC_DATA_REG, 1747 phy_data); 1748 jme_mdio_write(jme->dev, jme->mii_if.phy_id, JM_PHY_SPEC_ADDR_REG, 1749 phy_addr); 1750 } 1751 1752 static int 1753 jme_phy_calibration(struct jme_adapter *jme) 1754 { 1755 u32 ctrl1000, phy_data; 1756 1757 jme_phy_off(jme); 1758 jme_phy_on(jme); 1759 /* Enabel PHY test mode 1 */ 1760 ctrl1000 = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_CTRL1000); 1761 ctrl1000 &= ~PHY_GAD_TEST_MODE_MSK; 1762 ctrl1000 |= PHY_GAD_TEST_MODE_1; 1763 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_CTRL1000, ctrl1000); 1764 1765 phy_data = jme_phy_specreg_read(jme, JM_PHY_EXT_COMM_2_REG); 1766 phy_data &= ~JM_PHY_EXT_COMM_2_CALI_MODE_0; 1767 phy_data |= JM_PHY_EXT_COMM_2_CALI_LATCH | 1768 JM_PHY_EXT_COMM_2_CALI_ENABLE; 1769 jme_phy_specreg_write(jme, JM_PHY_EXT_COMM_2_REG, phy_data); 1770 msleep(20); 1771 phy_data = jme_phy_specreg_read(jme, JM_PHY_EXT_COMM_2_REG); 1772 phy_data &= ~(JM_PHY_EXT_COMM_2_CALI_ENABLE | 1773 JM_PHY_EXT_COMM_2_CALI_MODE_0 | 1774 JM_PHY_EXT_COMM_2_CALI_LATCH); 1775 jme_phy_specreg_write(jme, JM_PHY_EXT_COMM_2_REG, phy_data); 1776 1777 /* Disable PHY test mode */ 1778 ctrl1000 = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_CTRL1000); 1779 ctrl1000 &= ~PHY_GAD_TEST_MODE_MSK; 1780 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_CTRL1000, ctrl1000); 1781 return 0; 1782 } 1783 1784 static int 1785 jme_phy_setEA(struct jme_adapter *jme) 1786 { 1787 u32 phy_comm0 = 0, phy_comm1 = 0; 1788 u8 nic_ctrl; 1789 1790 pci_read_config_byte(jme->pdev, PCI_PRIV_SHARE_NICCTRL, &nic_ctrl); 1791 if ((nic_ctrl & 0x3) == JME_FLAG_PHYEA_ENABLE) 1792 return 0; 1793 1794 switch (jme->pdev->device) { 1795 case PCI_DEVICE_ID_JMICRON_JMC250: 1796 if (((jme->chip_main_rev == 5) && 1797 ((jme->chip_sub_rev == 0) || (jme->chip_sub_rev == 1) || 1798 (jme->chip_sub_rev == 3))) || 1799 (jme->chip_main_rev >= 6)) { 1800 phy_comm0 = 0x008A; 1801 phy_comm1 = 0x4109; 1802 } 1803 if ((jme->chip_main_rev == 3) && 1804 ((jme->chip_sub_rev == 1) || (jme->chip_sub_rev == 2))) 1805 phy_comm0 = 0xE088; 1806 break; 1807 case PCI_DEVICE_ID_JMICRON_JMC260: 1808 if (((jme->chip_main_rev == 5) && 1809 ((jme->chip_sub_rev == 0) || (jme->chip_sub_rev == 1) || 1810 (jme->chip_sub_rev == 3))) || 1811 (jme->chip_main_rev >= 6)) { 1812 phy_comm0 = 0x008A; 1813 phy_comm1 = 0x4109; 1814 } 1815 if ((jme->chip_main_rev == 3) && 1816 ((jme->chip_sub_rev == 1) || (jme->chip_sub_rev == 2))) 1817 phy_comm0 = 0xE088; 1818 if ((jme->chip_main_rev == 2) && (jme->chip_sub_rev == 0)) 1819 phy_comm0 = 0x608A; 1820 if ((jme->chip_main_rev == 2) && (jme->chip_sub_rev == 2)) 1821 phy_comm0 = 0x408A; 1822 break; 1823 default: 1824 return -ENODEV; 1825 } 1826 if (phy_comm0) 1827 jme_phy_specreg_write(jme, JM_PHY_EXT_COMM_0_REG, phy_comm0); 1828 if (phy_comm1) 1829 jme_phy_specreg_write(jme, JM_PHY_EXT_COMM_1_REG, phy_comm1); 1830 1831 return 0; 1832 } 1833 1834 static int 1835 jme_open(struct net_device *netdev) 1836 { 1837 struct jme_adapter *jme = netdev_priv(netdev); 1838 int rc; 1839 1840 jme_clear_pm_disable_wol(jme); 1841 JME_NAPI_ENABLE(jme); 1842 1843 tasklet_init(&jme->linkch_task, jme_link_change_tasklet, 1844 (unsigned long) jme); 1845 tasklet_init(&jme->txclean_task, jme_tx_clean_tasklet, 1846 (unsigned long) jme); 1847 tasklet_init(&jme->rxclean_task, jme_rx_clean_tasklet, 1848 (unsigned long) jme); 1849 tasklet_init(&jme->rxempty_task, jme_rx_empty_tasklet, 1850 (unsigned long) jme); 1851 1852 rc = jme_request_irq(jme); 1853 if (rc) 1854 goto err_out; 1855 1856 jme_start_irq(jme); 1857 1858 jme_phy_on(jme); 1859 if (test_bit(JME_FLAG_SSET, &jme->flags)) 1860 jme_set_link_ksettings(netdev, &jme->old_cmd); 1861 else 1862 jme_reset_phy_processor(jme); 1863 jme_phy_calibration(jme); 1864 jme_phy_setEA(jme); 1865 jme_reset_link(jme); 1866 1867 return 0; 1868 1869 err_out: 1870 netif_stop_queue(netdev); 1871 netif_carrier_off(netdev); 1872 return rc; 1873 } 1874 1875 static void 1876 jme_set_100m_half(struct jme_adapter *jme) 1877 { 1878 u32 bmcr, tmp; 1879 1880 jme_phy_on(jme); 1881 bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR); 1882 tmp = bmcr & ~(BMCR_ANENABLE | BMCR_SPEED100 | 1883 BMCR_SPEED1000 | BMCR_FULLDPLX); 1884 tmp |= BMCR_SPEED100; 1885 1886 if (bmcr != tmp) 1887 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, tmp); 1888 1889 if (jme->fpgaver) 1890 jwrite32(jme, JME_GHC, GHC_SPEED_100M | GHC_LINK_POLL); 1891 else 1892 jwrite32(jme, JME_GHC, GHC_SPEED_100M); 1893 } 1894 1895 #define JME_WAIT_LINK_TIME 2000 /* 2000ms */ 1896 static void 1897 jme_wait_link(struct jme_adapter *jme) 1898 { 1899 u32 phylink, to = JME_WAIT_LINK_TIME; 1900 1901 msleep(1000); 1902 phylink = jme_linkstat_from_phy(jme); 1903 while (!(phylink & PHY_LINK_UP) && (to -= 10) > 0) { 1904 usleep_range(10000, 11000); 1905 phylink = jme_linkstat_from_phy(jme); 1906 } 1907 } 1908 1909 static void 1910 jme_powersave_phy(struct jme_adapter *jme) 1911 { 1912 if (jme->reg_pmcs && device_may_wakeup(&jme->pdev->dev)) { 1913 jme_set_100m_half(jme); 1914 if (jme->reg_pmcs & (PMCS_LFEN | PMCS_LREN)) 1915 jme_wait_link(jme); 1916 jme_clear_pm_enable_wol(jme); 1917 } else { 1918 jme_phy_off(jme); 1919 } 1920 } 1921 1922 static int 1923 jme_close(struct net_device *netdev) 1924 { 1925 struct jme_adapter *jme = netdev_priv(netdev); 1926 1927 netif_stop_queue(netdev); 1928 netif_carrier_off(netdev); 1929 1930 jme_stop_irq(jme); 1931 jme_free_irq(jme); 1932 1933 JME_NAPI_DISABLE(jme); 1934 1935 tasklet_kill(&jme->linkch_task); 1936 tasklet_kill(&jme->txclean_task); 1937 tasklet_kill(&jme->rxclean_task); 1938 tasklet_kill(&jme->rxempty_task); 1939 1940 jme_disable_rx_engine(jme); 1941 jme_disable_tx_engine(jme); 1942 jme_reset_mac_processor(jme); 1943 jme_free_rx_resources(jme); 1944 jme_free_tx_resources(jme); 1945 jme->phylink = 0; 1946 jme_phy_off(jme); 1947 1948 return 0; 1949 } 1950 1951 static int 1952 jme_alloc_txdesc(struct jme_adapter *jme, 1953 struct sk_buff *skb) 1954 { 1955 struct jme_ring *txring = &(jme->txring[0]); 1956 int idx, nr_alloc, mask = jme->tx_ring_mask; 1957 1958 idx = txring->next_to_use; 1959 nr_alloc = skb_shinfo(skb)->nr_frags + 2; 1960 1961 if (unlikely(atomic_read(&txring->nr_free) < nr_alloc)) 1962 return -1; 1963 1964 atomic_sub(nr_alloc, &txring->nr_free); 1965 1966 txring->next_to_use = (txring->next_to_use + nr_alloc) & mask; 1967 1968 return idx; 1969 } 1970 1971 static int 1972 jme_fill_tx_map(struct pci_dev *pdev, 1973 struct txdesc *txdesc, 1974 struct jme_buffer_info *txbi, 1975 struct page *page, 1976 u32 page_offset, 1977 u32 len, 1978 bool hidma) 1979 { 1980 dma_addr_t dmaaddr; 1981 1982 dmaaddr = pci_map_page(pdev, 1983 page, 1984 page_offset, 1985 len, 1986 PCI_DMA_TODEVICE); 1987 1988 if (unlikely(pci_dma_mapping_error(pdev, dmaaddr))) 1989 return -EINVAL; 1990 1991 pci_dma_sync_single_for_device(pdev, 1992 dmaaddr, 1993 len, 1994 PCI_DMA_TODEVICE); 1995 1996 txdesc->dw[0] = 0; 1997 txdesc->dw[1] = 0; 1998 txdesc->desc2.flags = TXFLAG_OWN; 1999 txdesc->desc2.flags |= (hidma) ? TXFLAG_64BIT : 0; 2000 txdesc->desc2.datalen = cpu_to_le16(len); 2001 txdesc->desc2.bufaddrh = cpu_to_le32((__u64)dmaaddr >> 32); 2002 txdesc->desc2.bufaddrl = cpu_to_le32( 2003 (__u64)dmaaddr & 0xFFFFFFFFUL); 2004 2005 txbi->mapping = dmaaddr; 2006 txbi->len = len; 2007 return 0; 2008 } 2009 2010 static void jme_drop_tx_map(struct jme_adapter *jme, int startidx, int count) 2011 { 2012 struct jme_ring *txring = &(jme->txring[0]); 2013 struct jme_buffer_info *txbi = txring->bufinf, *ctxbi; 2014 int mask = jme->tx_ring_mask; 2015 int j; 2016 2017 for (j = 0 ; j < count ; j++) { 2018 ctxbi = txbi + ((startidx + j + 2) & (mask)); 2019 pci_unmap_page(jme->pdev, 2020 ctxbi->mapping, 2021 ctxbi->len, 2022 PCI_DMA_TODEVICE); 2023 2024 ctxbi->mapping = 0; 2025 ctxbi->len = 0; 2026 } 2027 } 2028 2029 static int 2030 jme_map_tx_skb(struct jme_adapter *jme, struct sk_buff *skb, int idx) 2031 { 2032 struct jme_ring *txring = &(jme->txring[0]); 2033 struct txdesc *txdesc = txring->desc, *ctxdesc; 2034 struct jme_buffer_info *txbi = txring->bufinf, *ctxbi; 2035 bool hidma = jme->dev->features & NETIF_F_HIGHDMA; 2036 int i, nr_frags = skb_shinfo(skb)->nr_frags; 2037 int mask = jme->tx_ring_mask; 2038 const struct skb_frag_struct *frag; 2039 u32 len; 2040 int ret = 0; 2041 2042 for (i = 0 ; i < nr_frags ; ++i) { 2043 frag = &skb_shinfo(skb)->frags[i]; 2044 ctxdesc = txdesc + ((idx + i + 2) & (mask)); 2045 ctxbi = txbi + ((idx + i + 2) & (mask)); 2046 2047 ret = jme_fill_tx_map(jme->pdev, ctxdesc, ctxbi, 2048 skb_frag_page(frag), 2049 frag->page_offset, skb_frag_size(frag), hidma); 2050 if (ret) { 2051 jme_drop_tx_map(jme, idx, i); 2052 goto out; 2053 } 2054 2055 } 2056 2057 len = skb_is_nonlinear(skb) ? skb_headlen(skb) : skb->len; 2058 ctxdesc = txdesc + ((idx + 1) & (mask)); 2059 ctxbi = txbi + ((idx + 1) & (mask)); 2060 ret = jme_fill_tx_map(jme->pdev, ctxdesc, ctxbi, virt_to_page(skb->data), 2061 offset_in_page(skb->data), len, hidma); 2062 if (ret) 2063 jme_drop_tx_map(jme, idx, i); 2064 2065 out: 2066 return ret; 2067 2068 } 2069 2070 2071 static int 2072 jme_tx_tso(struct sk_buff *skb, __le16 *mss, u8 *flags) 2073 { 2074 *mss = cpu_to_le16(skb_shinfo(skb)->gso_size << TXDESC_MSS_SHIFT); 2075 if (*mss) { 2076 *flags |= TXFLAG_LSEN; 2077 2078 if (skb->protocol == htons(ETH_P_IP)) { 2079 struct iphdr *iph = ip_hdr(skb); 2080 2081 iph->check = 0; 2082 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr, 2083 iph->daddr, 0, 2084 IPPROTO_TCP, 2085 0); 2086 } else { 2087 struct ipv6hdr *ip6h = ipv6_hdr(skb); 2088 2089 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ip6h->saddr, 2090 &ip6h->daddr, 0, 2091 IPPROTO_TCP, 2092 0); 2093 } 2094 2095 return 0; 2096 } 2097 2098 return 1; 2099 } 2100 2101 static void 2102 jme_tx_csum(struct jme_adapter *jme, struct sk_buff *skb, u8 *flags) 2103 { 2104 if (skb->ip_summed == CHECKSUM_PARTIAL) { 2105 u8 ip_proto; 2106 2107 switch (skb->protocol) { 2108 case htons(ETH_P_IP): 2109 ip_proto = ip_hdr(skb)->protocol; 2110 break; 2111 case htons(ETH_P_IPV6): 2112 ip_proto = ipv6_hdr(skb)->nexthdr; 2113 break; 2114 default: 2115 ip_proto = 0; 2116 break; 2117 } 2118 2119 switch (ip_proto) { 2120 case IPPROTO_TCP: 2121 *flags |= TXFLAG_TCPCS; 2122 break; 2123 case IPPROTO_UDP: 2124 *flags |= TXFLAG_UDPCS; 2125 break; 2126 default: 2127 netif_err(jme, tx_err, jme->dev, "Error upper layer protocol\n"); 2128 break; 2129 } 2130 } 2131 } 2132 2133 static inline void 2134 jme_tx_vlan(struct sk_buff *skb, __le16 *vlan, u8 *flags) 2135 { 2136 if (skb_vlan_tag_present(skb)) { 2137 *flags |= TXFLAG_TAGON; 2138 *vlan = cpu_to_le16(skb_vlan_tag_get(skb)); 2139 } 2140 } 2141 2142 static int 2143 jme_fill_tx_desc(struct jme_adapter *jme, struct sk_buff *skb, int idx) 2144 { 2145 struct jme_ring *txring = &(jme->txring[0]); 2146 struct txdesc *txdesc; 2147 struct jme_buffer_info *txbi; 2148 u8 flags; 2149 int ret = 0; 2150 2151 txdesc = (struct txdesc *)txring->desc + idx; 2152 txbi = txring->bufinf + idx; 2153 2154 txdesc->dw[0] = 0; 2155 txdesc->dw[1] = 0; 2156 txdesc->dw[2] = 0; 2157 txdesc->dw[3] = 0; 2158 txdesc->desc1.pktsize = cpu_to_le16(skb->len); 2159 /* 2160 * Set OWN bit at final. 2161 * When kernel transmit faster than NIC. 2162 * And NIC trying to send this descriptor before we tell 2163 * it to start sending this TX queue. 2164 * Other fields are already filled correctly. 2165 */ 2166 wmb(); 2167 flags = TXFLAG_OWN | TXFLAG_INT; 2168 /* 2169 * Set checksum flags while not tso 2170 */ 2171 if (jme_tx_tso(skb, &txdesc->desc1.mss, &flags)) 2172 jme_tx_csum(jme, skb, &flags); 2173 jme_tx_vlan(skb, &txdesc->desc1.vlan, &flags); 2174 ret = jme_map_tx_skb(jme, skb, idx); 2175 if (ret) 2176 return ret; 2177 2178 txdesc->desc1.flags = flags; 2179 /* 2180 * Set tx buffer info after telling NIC to send 2181 * For better tx_clean timing 2182 */ 2183 wmb(); 2184 txbi->nr_desc = skb_shinfo(skb)->nr_frags + 2; 2185 txbi->skb = skb; 2186 txbi->len = skb->len; 2187 txbi->start_xmit = jiffies; 2188 if (!txbi->start_xmit) 2189 txbi->start_xmit = (0UL-1); 2190 2191 return 0; 2192 } 2193 2194 static void 2195 jme_stop_queue_if_full(struct jme_adapter *jme) 2196 { 2197 struct jme_ring *txring = &(jme->txring[0]); 2198 struct jme_buffer_info *txbi = txring->bufinf; 2199 int idx = atomic_read(&txring->next_to_clean); 2200 2201 txbi += idx; 2202 2203 smp_wmb(); 2204 if (unlikely(atomic_read(&txring->nr_free) < (MAX_SKB_FRAGS+2))) { 2205 netif_stop_queue(jme->dev); 2206 netif_info(jme, tx_queued, jme->dev, "TX Queue Paused\n"); 2207 smp_wmb(); 2208 if (atomic_read(&txring->nr_free) 2209 >= (jme->tx_wake_threshold)) { 2210 netif_wake_queue(jme->dev); 2211 netif_info(jme, tx_queued, jme->dev, "TX Queue Fast Waked\n"); 2212 } 2213 } 2214 2215 if (unlikely(txbi->start_xmit && 2216 (jiffies - txbi->start_xmit) >= TX_TIMEOUT && 2217 txbi->skb)) { 2218 netif_stop_queue(jme->dev); 2219 netif_info(jme, tx_queued, jme->dev, 2220 "TX Queue Stopped %d@%lu\n", idx, jiffies); 2221 } 2222 } 2223 2224 /* 2225 * This function is already protected by netif_tx_lock() 2226 */ 2227 2228 static netdev_tx_t 2229 jme_start_xmit(struct sk_buff *skb, struct net_device *netdev) 2230 { 2231 struct jme_adapter *jme = netdev_priv(netdev); 2232 int idx; 2233 2234 if (unlikely(skb_is_gso(skb) && skb_cow_head(skb, 0))) { 2235 dev_kfree_skb_any(skb); 2236 ++(NET_STAT(jme).tx_dropped); 2237 return NETDEV_TX_OK; 2238 } 2239 2240 idx = jme_alloc_txdesc(jme, skb); 2241 2242 if (unlikely(idx < 0)) { 2243 netif_stop_queue(netdev); 2244 netif_err(jme, tx_err, jme->dev, 2245 "BUG! Tx ring full when queue awake!\n"); 2246 2247 return NETDEV_TX_BUSY; 2248 } 2249 2250 if (jme_fill_tx_desc(jme, skb, idx)) 2251 return NETDEV_TX_OK; 2252 2253 jwrite32(jme, JME_TXCS, jme->reg_txcs | 2254 TXCS_SELECT_QUEUE0 | 2255 TXCS_QUEUE0S | 2256 TXCS_ENABLE); 2257 2258 tx_dbg(jme, "xmit: %d+%d@%lu\n", 2259 idx, skb_shinfo(skb)->nr_frags + 2, jiffies); 2260 jme_stop_queue_if_full(jme); 2261 2262 return NETDEV_TX_OK; 2263 } 2264 2265 static void 2266 jme_set_unicastaddr(struct net_device *netdev) 2267 { 2268 struct jme_adapter *jme = netdev_priv(netdev); 2269 u32 val; 2270 2271 val = (netdev->dev_addr[3] & 0xff) << 24 | 2272 (netdev->dev_addr[2] & 0xff) << 16 | 2273 (netdev->dev_addr[1] & 0xff) << 8 | 2274 (netdev->dev_addr[0] & 0xff); 2275 jwrite32(jme, JME_RXUMA_LO, val); 2276 val = (netdev->dev_addr[5] & 0xff) << 8 | 2277 (netdev->dev_addr[4] & 0xff); 2278 jwrite32(jme, JME_RXUMA_HI, val); 2279 } 2280 2281 static int 2282 jme_set_macaddr(struct net_device *netdev, void *p) 2283 { 2284 struct jme_adapter *jme = netdev_priv(netdev); 2285 struct sockaddr *addr = p; 2286 2287 if (netif_running(netdev)) 2288 return -EBUSY; 2289 2290 spin_lock_bh(&jme->macaddr_lock); 2291 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len); 2292 jme_set_unicastaddr(netdev); 2293 spin_unlock_bh(&jme->macaddr_lock); 2294 2295 return 0; 2296 } 2297 2298 static void 2299 jme_set_multi(struct net_device *netdev) 2300 { 2301 struct jme_adapter *jme = netdev_priv(netdev); 2302 u32 mc_hash[2] = {}; 2303 2304 spin_lock_bh(&jme->rxmcs_lock); 2305 2306 jme->reg_rxmcs |= RXMCS_BRDFRAME | RXMCS_UNIFRAME; 2307 2308 if (netdev->flags & IFF_PROMISC) { 2309 jme->reg_rxmcs |= RXMCS_ALLFRAME; 2310 } else if (netdev->flags & IFF_ALLMULTI) { 2311 jme->reg_rxmcs |= RXMCS_ALLMULFRAME; 2312 } else if (netdev->flags & IFF_MULTICAST) { 2313 struct netdev_hw_addr *ha; 2314 int bit_nr; 2315 2316 jme->reg_rxmcs |= RXMCS_MULFRAME | RXMCS_MULFILTERED; 2317 netdev_for_each_mc_addr(ha, netdev) { 2318 bit_nr = ether_crc(ETH_ALEN, ha->addr) & 0x3F; 2319 mc_hash[bit_nr >> 5] |= 1 << (bit_nr & 0x1F); 2320 } 2321 2322 jwrite32(jme, JME_RXMCHT_LO, mc_hash[0]); 2323 jwrite32(jme, JME_RXMCHT_HI, mc_hash[1]); 2324 } 2325 2326 wmb(); 2327 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs); 2328 2329 spin_unlock_bh(&jme->rxmcs_lock); 2330 } 2331 2332 static int 2333 jme_change_mtu(struct net_device *netdev, int new_mtu) 2334 { 2335 struct jme_adapter *jme = netdev_priv(netdev); 2336 2337 netdev->mtu = new_mtu; 2338 netdev_update_features(netdev); 2339 2340 jme_restart_rx_engine(jme); 2341 jme_reset_link(jme); 2342 2343 return 0; 2344 } 2345 2346 static void 2347 jme_tx_timeout(struct net_device *netdev) 2348 { 2349 struct jme_adapter *jme = netdev_priv(netdev); 2350 2351 jme->phylink = 0; 2352 jme_reset_phy_processor(jme); 2353 if (test_bit(JME_FLAG_SSET, &jme->flags)) 2354 jme_set_link_ksettings(netdev, &jme->old_cmd); 2355 2356 /* 2357 * Force to Reset the link again 2358 */ 2359 jme_reset_link(jme); 2360 } 2361 2362 static void 2363 jme_get_drvinfo(struct net_device *netdev, 2364 struct ethtool_drvinfo *info) 2365 { 2366 struct jme_adapter *jme = netdev_priv(netdev); 2367 2368 strlcpy(info->driver, DRV_NAME, sizeof(info->driver)); 2369 strlcpy(info->version, DRV_VERSION, sizeof(info->version)); 2370 strlcpy(info->bus_info, pci_name(jme->pdev), sizeof(info->bus_info)); 2371 } 2372 2373 static int 2374 jme_get_regs_len(struct net_device *netdev) 2375 { 2376 return JME_REG_LEN; 2377 } 2378 2379 static void 2380 mmapio_memcpy(struct jme_adapter *jme, u32 *p, u32 reg, int len) 2381 { 2382 int i; 2383 2384 for (i = 0 ; i < len ; i += 4) 2385 p[i >> 2] = jread32(jme, reg + i); 2386 } 2387 2388 static void 2389 mdio_memcpy(struct jme_adapter *jme, u32 *p, int reg_nr) 2390 { 2391 int i; 2392 u16 *p16 = (u16 *)p; 2393 2394 for (i = 0 ; i < reg_nr ; ++i) 2395 p16[i] = jme_mdio_read(jme->dev, jme->mii_if.phy_id, i); 2396 } 2397 2398 static void 2399 jme_get_regs(struct net_device *netdev, struct ethtool_regs *regs, void *p) 2400 { 2401 struct jme_adapter *jme = netdev_priv(netdev); 2402 u32 *p32 = (u32 *)p; 2403 2404 memset(p, 0xFF, JME_REG_LEN); 2405 2406 regs->version = 1; 2407 mmapio_memcpy(jme, p32, JME_MAC, JME_MAC_LEN); 2408 2409 p32 += 0x100 >> 2; 2410 mmapio_memcpy(jme, p32, JME_PHY, JME_PHY_LEN); 2411 2412 p32 += 0x100 >> 2; 2413 mmapio_memcpy(jme, p32, JME_MISC, JME_MISC_LEN); 2414 2415 p32 += 0x100 >> 2; 2416 mmapio_memcpy(jme, p32, JME_RSS, JME_RSS_LEN); 2417 2418 p32 += 0x100 >> 2; 2419 mdio_memcpy(jme, p32, JME_PHY_REG_NR); 2420 } 2421 2422 static int 2423 jme_get_coalesce(struct net_device *netdev, struct ethtool_coalesce *ecmd) 2424 { 2425 struct jme_adapter *jme = netdev_priv(netdev); 2426 2427 ecmd->tx_coalesce_usecs = PCC_TX_TO; 2428 ecmd->tx_max_coalesced_frames = PCC_TX_CNT; 2429 2430 if (test_bit(JME_FLAG_POLL, &jme->flags)) { 2431 ecmd->use_adaptive_rx_coalesce = false; 2432 ecmd->rx_coalesce_usecs = 0; 2433 ecmd->rx_max_coalesced_frames = 0; 2434 return 0; 2435 } 2436 2437 ecmd->use_adaptive_rx_coalesce = true; 2438 2439 switch (jme->dpi.cur) { 2440 case PCC_P1: 2441 ecmd->rx_coalesce_usecs = PCC_P1_TO; 2442 ecmd->rx_max_coalesced_frames = PCC_P1_CNT; 2443 break; 2444 case PCC_P2: 2445 ecmd->rx_coalesce_usecs = PCC_P2_TO; 2446 ecmd->rx_max_coalesced_frames = PCC_P2_CNT; 2447 break; 2448 case PCC_P3: 2449 ecmd->rx_coalesce_usecs = PCC_P3_TO; 2450 ecmd->rx_max_coalesced_frames = PCC_P3_CNT; 2451 break; 2452 default: 2453 break; 2454 } 2455 2456 return 0; 2457 } 2458 2459 static int 2460 jme_set_coalesce(struct net_device *netdev, struct ethtool_coalesce *ecmd) 2461 { 2462 struct jme_adapter *jme = netdev_priv(netdev); 2463 struct dynpcc_info *dpi = &(jme->dpi); 2464 2465 if (netif_running(netdev)) 2466 return -EBUSY; 2467 2468 if (ecmd->use_adaptive_rx_coalesce && 2469 test_bit(JME_FLAG_POLL, &jme->flags)) { 2470 clear_bit(JME_FLAG_POLL, &jme->flags); 2471 jme->jme_rx = netif_rx; 2472 dpi->cur = PCC_P1; 2473 dpi->attempt = PCC_P1; 2474 dpi->cnt = 0; 2475 jme_set_rx_pcc(jme, PCC_P1); 2476 jme_interrupt_mode(jme); 2477 } else if (!(ecmd->use_adaptive_rx_coalesce) && 2478 !(test_bit(JME_FLAG_POLL, &jme->flags))) { 2479 set_bit(JME_FLAG_POLL, &jme->flags); 2480 jme->jme_rx = netif_receive_skb; 2481 jme_interrupt_mode(jme); 2482 } 2483 2484 return 0; 2485 } 2486 2487 static void 2488 jme_get_pauseparam(struct net_device *netdev, 2489 struct ethtool_pauseparam *ecmd) 2490 { 2491 struct jme_adapter *jme = netdev_priv(netdev); 2492 u32 val; 2493 2494 ecmd->tx_pause = (jme->reg_txpfc & TXPFC_PF_EN) != 0; 2495 ecmd->rx_pause = (jme->reg_rxmcs & RXMCS_FLOWCTRL) != 0; 2496 2497 spin_lock_bh(&jme->phy_lock); 2498 val = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_ADVERTISE); 2499 spin_unlock_bh(&jme->phy_lock); 2500 2501 ecmd->autoneg = 2502 (val & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM)) != 0; 2503 } 2504 2505 static int 2506 jme_set_pauseparam(struct net_device *netdev, 2507 struct ethtool_pauseparam *ecmd) 2508 { 2509 struct jme_adapter *jme = netdev_priv(netdev); 2510 u32 val; 2511 2512 if (((jme->reg_txpfc & TXPFC_PF_EN) != 0) ^ 2513 (ecmd->tx_pause != 0)) { 2514 2515 if (ecmd->tx_pause) 2516 jme->reg_txpfc |= TXPFC_PF_EN; 2517 else 2518 jme->reg_txpfc &= ~TXPFC_PF_EN; 2519 2520 jwrite32(jme, JME_TXPFC, jme->reg_txpfc); 2521 } 2522 2523 spin_lock_bh(&jme->rxmcs_lock); 2524 if (((jme->reg_rxmcs & RXMCS_FLOWCTRL) != 0) ^ 2525 (ecmd->rx_pause != 0)) { 2526 2527 if (ecmd->rx_pause) 2528 jme->reg_rxmcs |= RXMCS_FLOWCTRL; 2529 else 2530 jme->reg_rxmcs &= ~RXMCS_FLOWCTRL; 2531 2532 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs); 2533 } 2534 spin_unlock_bh(&jme->rxmcs_lock); 2535 2536 spin_lock_bh(&jme->phy_lock); 2537 val = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_ADVERTISE); 2538 if (((val & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM)) != 0) ^ 2539 (ecmd->autoneg != 0)) { 2540 2541 if (ecmd->autoneg) 2542 val |= (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM); 2543 else 2544 val &= ~(ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM); 2545 2546 jme_mdio_write(jme->dev, jme->mii_if.phy_id, 2547 MII_ADVERTISE, val); 2548 } 2549 spin_unlock_bh(&jme->phy_lock); 2550 2551 return 0; 2552 } 2553 2554 static void 2555 jme_get_wol(struct net_device *netdev, 2556 struct ethtool_wolinfo *wol) 2557 { 2558 struct jme_adapter *jme = netdev_priv(netdev); 2559 2560 wol->supported = WAKE_MAGIC | WAKE_PHY; 2561 2562 wol->wolopts = 0; 2563 2564 if (jme->reg_pmcs & (PMCS_LFEN | PMCS_LREN)) 2565 wol->wolopts |= WAKE_PHY; 2566 2567 if (jme->reg_pmcs & PMCS_MFEN) 2568 wol->wolopts |= WAKE_MAGIC; 2569 2570 } 2571 2572 static int 2573 jme_set_wol(struct net_device *netdev, 2574 struct ethtool_wolinfo *wol) 2575 { 2576 struct jme_adapter *jme = netdev_priv(netdev); 2577 2578 if (wol->wolopts & (WAKE_MAGICSECURE | 2579 WAKE_UCAST | 2580 WAKE_MCAST | 2581 WAKE_BCAST | 2582 WAKE_ARP)) 2583 return -EOPNOTSUPP; 2584 2585 jme->reg_pmcs = 0; 2586 2587 if (wol->wolopts & WAKE_PHY) 2588 jme->reg_pmcs |= PMCS_LFEN | PMCS_LREN; 2589 2590 if (wol->wolopts & WAKE_MAGIC) 2591 jme->reg_pmcs |= PMCS_MFEN; 2592 2593 return 0; 2594 } 2595 2596 static int 2597 jme_get_link_ksettings(struct net_device *netdev, 2598 struct ethtool_link_ksettings *cmd) 2599 { 2600 struct jme_adapter *jme = netdev_priv(netdev); 2601 2602 spin_lock_bh(&jme->phy_lock); 2603 mii_ethtool_get_link_ksettings(&jme->mii_if, cmd); 2604 spin_unlock_bh(&jme->phy_lock); 2605 return 0; 2606 } 2607 2608 static int 2609 jme_set_link_ksettings(struct net_device *netdev, 2610 const struct ethtool_link_ksettings *cmd) 2611 { 2612 struct jme_adapter *jme = netdev_priv(netdev); 2613 int rc, fdc = 0; 2614 2615 if (cmd->base.speed == SPEED_1000 && 2616 cmd->base.autoneg != AUTONEG_ENABLE) 2617 return -EINVAL; 2618 2619 /* 2620 * Check If user changed duplex only while force_media. 2621 * Hardware would not generate link change interrupt. 2622 */ 2623 if (jme->mii_if.force_media && 2624 cmd->base.autoneg != AUTONEG_ENABLE && 2625 (jme->mii_if.full_duplex != cmd->base.duplex)) 2626 fdc = 1; 2627 2628 spin_lock_bh(&jme->phy_lock); 2629 rc = mii_ethtool_set_link_ksettings(&jme->mii_if, cmd); 2630 spin_unlock_bh(&jme->phy_lock); 2631 2632 if (!rc) { 2633 if (fdc) 2634 jme_reset_link(jme); 2635 jme->old_cmd = *cmd; 2636 set_bit(JME_FLAG_SSET, &jme->flags); 2637 } 2638 2639 return rc; 2640 } 2641 2642 static int 2643 jme_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd) 2644 { 2645 int rc; 2646 struct jme_adapter *jme = netdev_priv(netdev); 2647 struct mii_ioctl_data *mii_data = if_mii(rq); 2648 unsigned int duplex_chg; 2649 2650 if (cmd == SIOCSMIIREG) { 2651 u16 val = mii_data->val_in; 2652 if (!(val & (BMCR_RESET|BMCR_ANENABLE)) && 2653 (val & BMCR_SPEED1000)) 2654 return -EINVAL; 2655 } 2656 2657 spin_lock_bh(&jme->phy_lock); 2658 rc = generic_mii_ioctl(&jme->mii_if, mii_data, cmd, &duplex_chg); 2659 spin_unlock_bh(&jme->phy_lock); 2660 2661 if (!rc && (cmd == SIOCSMIIREG)) { 2662 if (duplex_chg) 2663 jme_reset_link(jme); 2664 jme_get_link_ksettings(netdev, &jme->old_cmd); 2665 set_bit(JME_FLAG_SSET, &jme->flags); 2666 } 2667 2668 return rc; 2669 } 2670 2671 static u32 2672 jme_get_link(struct net_device *netdev) 2673 { 2674 struct jme_adapter *jme = netdev_priv(netdev); 2675 return jread32(jme, JME_PHY_LINK) & PHY_LINK_UP; 2676 } 2677 2678 static u32 2679 jme_get_msglevel(struct net_device *netdev) 2680 { 2681 struct jme_adapter *jme = netdev_priv(netdev); 2682 return jme->msg_enable; 2683 } 2684 2685 static void 2686 jme_set_msglevel(struct net_device *netdev, u32 value) 2687 { 2688 struct jme_adapter *jme = netdev_priv(netdev); 2689 jme->msg_enable = value; 2690 } 2691 2692 static netdev_features_t 2693 jme_fix_features(struct net_device *netdev, netdev_features_t features) 2694 { 2695 if (netdev->mtu > 1900) 2696 features &= ~(NETIF_F_ALL_TSO | NETIF_F_CSUM_MASK); 2697 return features; 2698 } 2699 2700 static int 2701 jme_set_features(struct net_device *netdev, netdev_features_t features) 2702 { 2703 struct jme_adapter *jme = netdev_priv(netdev); 2704 2705 spin_lock_bh(&jme->rxmcs_lock); 2706 if (features & NETIF_F_RXCSUM) 2707 jme->reg_rxmcs |= RXMCS_CHECKSUM; 2708 else 2709 jme->reg_rxmcs &= ~RXMCS_CHECKSUM; 2710 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs); 2711 spin_unlock_bh(&jme->rxmcs_lock); 2712 2713 return 0; 2714 } 2715 2716 #ifdef CONFIG_NET_POLL_CONTROLLER 2717 static void jme_netpoll(struct net_device *dev) 2718 { 2719 unsigned long flags; 2720 2721 local_irq_save(flags); 2722 jme_intr(dev->irq, dev); 2723 local_irq_restore(flags); 2724 } 2725 #endif 2726 2727 static int 2728 jme_nway_reset(struct net_device *netdev) 2729 { 2730 struct jme_adapter *jme = netdev_priv(netdev); 2731 jme_restart_an(jme); 2732 return 0; 2733 } 2734 2735 static u8 2736 jme_smb_read(struct jme_adapter *jme, unsigned int addr) 2737 { 2738 u32 val; 2739 int to; 2740 2741 val = jread32(jme, JME_SMBCSR); 2742 to = JME_SMB_BUSY_TIMEOUT; 2743 while ((val & SMBCSR_BUSY) && --to) { 2744 msleep(1); 2745 val = jread32(jme, JME_SMBCSR); 2746 } 2747 if (!to) { 2748 netif_err(jme, hw, jme->dev, "SMB Bus Busy\n"); 2749 return 0xFF; 2750 } 2751 2752 jwrite32(jme, JME_SMBINTF, 2753 ((addr << SMBINTF_HWADDR_SHIFT) & SMBINTF_HWADDR) | 2754 SMBINTF_HWRWN_READ | 2755 SMBINTF_HWCMD); 2756 2757 val = jread32(jme, JME_SMBINTF); 2758 to = JME_SMB_BUSY_TIMEOUT; 2759 while ((val & SMBINTF_HWCMD) && --to) { 2760 msleep(1); 2761 val = jread32(jme, JME_SMBINTF); 2762 } 2763 if (!to) { 2764 netif_err(jme, hw, jme->dev, "SMB Bus Busy\n"); 2765 return 0xFF; 2766 } 2767 2768 return (val & SMBINTF_HWDATR) >> SMBINTF_HWDATR_SHIFT; 2769 } 2770 2771 static void 2772 jme_smb_write(struct jme_adapter *jme, unsigned int addr, u8 data) 2773 { 2774 u32 val; 2775 int to; 2776 2777 val = jread32(jme, JME_SMBCSR); 2778 to = JME_SMB_BUSY_TIMEOUT; 2779 while ((val & SMBCSR_BUSY) && --to) { 2780 msleep(1); 2781 val = jread32(jme, JME_SMBCSR); 2782 } 2783 if (!to) { 2784 netif_err(jme, hw, jme->dev, "SMB Bus Busy\n"); 2785 return; 2786 } 2787 2788 jwrite32(jme, JME_SMBINTF, 2789 ((data << SMBINTF_HWDATW_SHIFT) & SMBINTF_HWDATW) | 2790 ((addr << SMBINTF_HWADDR_SHIFT) & SMBINTF_HWADDR) | 2791 SMBINTF_HWRWN_WRITE | 2792 SMBINTF_HWCMD); 2793 2794 val = jread32(jme, JME_SMBINTF); 2795 to = JME_SMB_BUSY_TIMEOUT; 2796 while ((val & SMBINTF_HWCMD) && --to) { 2797 msleep(1); 2798 val = jread32(jme, JME_SMBINTF); 2799 } 2800 if (!to) { 2801 netif_err(jme, hw, jme->dev, "SMB Bus Busy\n"); 2802 return; 2803 } 2804 2805 mdelay(2); 2806 } 2807 2808 static int 2809 jme_get_eeprom_len(struct net_device *netdev) 2810 { 2811 struct jme_adapter *jme = netdev_priv(netdev); 2812 u32 val; 2813 val = jread32(jme, JME_SMBCSR); 2814 return (val & SMBCSR_EEPROMD) ? JME_SMB_LEN : 0; 2815 } 2816 2817 static int 2818 jme_get_eeprom(struct net_device *netdev, 2819 struct ethtool_eeprom *eeprom, u8 *data) 2820 { 2821 struct jme_adapter *jme = netdev_priv(netdev); 2822 int i, offset = eeprom->offset, len = eeprom->len; 2823 2824 /* 2825 * ethtool will check the boundary for us 2826 */ 2827 eeprom->magic = JME_EEPROM_MAGIC; 2828 for (i = 0 ; i < len ; ++i) 2829 data[i] = jme_smb_read(jme, i + offset); 2830 2831 return 0; 2832 } 2833 2834 static int 2835 jme_set_eeprom(struct net_device *netdev, 2836 struct ethtool_eeprom *eeprom, u8 *data) 2837 { 2838 struct jme_adapter *jme = netdev_priv(netdev); 2839 int i, offset = eeprom->offset, len = eeprom->len; 2840 2841 if (eeprom->magic != JME_EEPROM_MAGIC) 2842 return -EINVAL; 2843 2844 /* 2845 * ethtool will check the boundary for us 2846 */ 2847 for (i = 0 ; i < len ; ++i) 2848 jme_smb_write(jme, i + offset, data[i]); 2849 2850 return 0; 2851 } 2852 2853 static const struct ethtool_ops jme_ethtool_ops = { 2854 .get_drvinfo = jme_get_drvinfo, 2855 .get_regs_len = jme_get_regs_len, 2856 .get_regs = jme_get_regs, 2857 .get_coalesce = jme_get_coalesce, 2858 .set_coalesce = jme_set_coalesce, 2859 .get_pauseparam = jme_get_pauseparam, 2860 .set_pauseparam = jme_set_pauseparam, 2861 .get_wol = jme_get_wol, 2862 .set_wol = jme_set_wol, 2863 .get_link = jme_get_link, 2864 .get_msglevel = jme_get_msglevel, 2865 .set_msglevel = jme_set_msglevel, 2866 .nway_reset = jme_nway_reset, 2867 .get_eeprom_len = jme_get_eeprom_len, 2868 .get_eeprom = jme_get_eeprom, 2869 .set_eeprom = jme_set_eeprom, 2870 .get_link_ksettings = jme_get_link_ksettings, 2871 .set_link_ksettings = jme_set_link_ksettings, 2872 }; 2873 2874 static int 2875 jme_pci_dma64(struct pci_dev *pdev) 2876 { 2877 if (pdev->device == PCI_DEVICE_ID_JMICRON_JMC250 && 2878 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) 2879 if (!pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64))) 2880 return 1; 2881 2882 if (pdev->device == PCI_DEVICE_ID_JMICRON_JMC250 && 2883 !pci_set_dma_mask(pdev, DMA_BIT_MASK(40))) 2884 if (!pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(40))) 2885 return 1; 2886 2887 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) 2888 if (!pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32))) 2889 return 0; 2890 2891 return -1; 2892 } 2893 2894 static inline void 2895 jme_phy_init(struct jme_adapter *jme) 2896 { 2897 u16 reg26; 2898 2899 reg26 = jme_mdio_read(jme->dev, jme->mii_if.phy_id, 26); 2900 jme_mdio_write(jme->dev, jme->mii_if.phy_id, 26, reg26 | 0x1000); 2901 } 2902 2903 static inline void 2904 jme_check_hw_ver(struct jme_adapter *jme) 2905 { 2906 u32 chipmode; 2907 2908 chipmode = jread32(jme, JME_CHIPMODE); 2909 2910 jme->fpgaver = (chipmode & CM_FPGAVER_MASK) >> CM_FPGAVER_SHIFT; 2911 jme->chiprev = (chipmode & CM_CHIPREV_MASK) >> CM_CHIPREV_SHIFT; 2912 jme->chip_main_rev = jme->chiprev & 0xF; 2913 jme->chip_sub_rev = (jme->chiprev >> 4) & 0xF; 2914 } 2915 2916 static const struct net_device_ops jme_netdev_ops = { 2917 .ndo_open = jme_open, 2918 .ndo_stop = jme_close, 2919 .ndo_validate_addr = eth_validate_addr, 2920 .ndo_do_ioctl = jme_ioctl, 2921 .ndo_start_xmit = jme_start_xmit, 2922 .ndo_set_mac_address = jme_set_macaddr, 2923 .ndo_set_rx_mode = jme_set_multi, 2924 .ndo_change_mtu = jme_change_mtu, 2925 .ndo_tx_timeout = jme_tx_timeout, 2926 .ndo_fix_features = jme_fix_features, 2927 .ndo_set_features = jme_set_features, 2928 #ifdef CONFIG_NET_POLL_CONTROLLER 2929 .ndo_poll_controller = jme_netpoll, 2930 #endif 2931 }; 2932 2933 static int 2934 jme_init_one(struct pci_dev *pdev, 2935 const struct pci_device_id *ent) 2936 { 2937 int rc = 0, using_dac, i; 2938 struct net_device *netdev; 2939 struct jme_adapter *jme; 2940 u16 bmcr, bmsr; 2941 u32 apmc; 2942 2943 /* 2944 * set up PCI device basics 2945 */ 2946 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 | 2947 PCIE_LINK_STATE_CLKPM); 2948 2949 rc = pci_enable_device(pdev); 2950 if (rc) { 2951 pr_err("Cannot enable PCI device\n"); 2952 goto err_out; 2953 } 2954 2955 using_dac = jme_pci_dma64(pdev); 2956 if (using_dac < 0) { 2957 pr_err("Cannot set PCI DMA Mask\n"); 2958 rc = -EIO; 2959 goto err_out_disable_pdev; 2960 } 2961 2962 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) { 2963 pr_err("No PCI resource region found\n"); 2964 rc = -ENOMEM; 2965 goto err_out_disable_pdev; 2966 } 2967 2968 rc = pci_request_regions(pdev, DRV_NAME); 2969 if (rc) { 2970 pr_err("Cannot obtain PCI resource region\n"); 2971 goto err_out_disable_pdev; 2972 } 2973 2974 pci_set_master(pdev); 2975 2976 /* 2977 * alloc and init net device 2978 */ 2979 netdev = alloc_etherdev(sizeof(*jme)); 2980 if (!netdev) { 2981 rc = -ENOMEM; 2982 goto err_out_release_regions; 2983 } 2984 netdev->netdev_ops = &jme_netdev_ops; 2985 netdev->ethtool_ops = &jme_ethtool_ops; 2986 netdev->watchdog_timeo = TX_TIMEOUT; 2987 netdev->hw_features = NETIF_F_IP_CSUM | 2988 NETIF_F_IPV6_CSUM | 2989 NETIF_F_SG | 2990 NETIF_F_TSO | 2991 NETIF_F_TSO6 | 2992 NETIF_F_RXCSUM; 2993 netdev->features = NETIF_F_IP_CSUM | 2994 NETIF_F_IPV6_CSUM | 2995 NETIF_F_SG | 2996 NETIF_F_TSO | 2997 NETIF_F_TSO6 | 2998 NETIF_F_HW_VLAN_CTAG_TX | 2999 NETIF_F_HW_VLAN_CTAG_RX; 3000 if (using_dac) 3001 netdev->features |= NETIF_F_HIGHDMA; 3002 3003 /* MTU range: 1280 - 9202*/ 3004 netdev->min_mtu = IPV6_MIN_MTU; 3005 netdev->max_mtu = MAX_ETHERNET_JUMBO_PACKET_SIZE - ETH_HLEN; 3006 3007 SET_NETDEV_DEV(netdev, &pdev->dev); 3008 pci_set_drvdata(pdev, netdev); 3009 3010 /* 3011 * init adapter info 3012 */ 3013 jme = netdev_priv(netdev); 3014 jme->pdev = pdev; 3015 jme->dev = netdev; 3016 jme->jme_rx = netif_rx; 3017 jme->old_mtu = netdev->mtu = 1500; 3018 jme->phylink = 0; 3019 jme->tx_ring_size = 1 << 10; 3020 jme->tx_ring_mask = jme->tx_ring_size - 1; 3021 jme->tx_wake_threshold = 1 << 9; 3022 jme->rx_ring_size = 1 << 9; 3023 jme->rx_ring_mask = jme->rx_ring_size - 1; 3024 jme->msg_enable = JME_DEF_MSG_ENABLE; 3025 jme->regs = ioremap(pci_resource_start(pdev, 0), 3026 pci_resource_len(pdev, 0)); 3027 if (!(jme->regs)) { 3028 pr_err("Mapping PCI resource region error\n"); 3029 rc = -ENOMEM; 3030 goto err_out_free_netdev; 3031 } 3032 3033 if (no_pseudohp) { 3034 apmc = jread32(jme, JME_APMC) & ~JME_APMC_PSEUDO_HP_EN; 3035 jwrite32(jme, JME_APMC, apmc); 3036 } else if (force_pseudohp) { 3037 apmc = jread32(jme, JME_APMC) | JME_APMC_PSEUDO_HP_EN; 3038 jwrite32(jme, JME_APMC, apmc); 3039 } 3040 3041 NETIF_NAPI_SET(netdev, &jme->napi, jme_poll, NAPI_POLL_WEIGHT) 3042 3043 spin_lock_init(&jme->phy_lock); 3044 spin_lock_init(&jme->macaddr_lock); 3045 spin_lock_init(&jme->rxmcs_lock); 3046 3047 atomic_set(&jme->link_changing, 1); 3048 atomic_set(&jme->rx_cleaning, 1); 3049 atomic_set(&jme->tx_cleaning, 1); 3050 atomic_set(&jme->rx_empty, 1); 3051 3052 tasklet_init(&jme->pcc_task, 3053 jme_pcc_tasklet, 3054 (unsigned long) jme); 3055 jme->dpi.cur = PCC_P1; 3056 3057 jme->reg_ghc = 0; 3058 jme->reg_rxcs = RXCS_DEFAULT; 3059 jme->reg_rxmcs = RXMCS_DEFAULT; 3060 jme->reg_txpfc = 0; 3061 jme->reg_pmcs = PMCS_MFEN; 3062 jme->reg_gpreg1 = GPREG1_DEFAULT; 3063 3064 if (jme->reg_rxmcs & RXMCS_CHECKSUM) 3065 netdev->features |= NETIF_F_RXCSUM; 3066 3067 /* 3068 * Get Max Read Req Size from PCI Config Space 3069 */ 3070 pci_read_config_byte(pdev, PCI_DCSR_MRRS, &jme->mrrs); 3071 jme->mrrs &= PCI_DCSR_MRRS_MASK; 3072 switch (jme->mrrs) { 3073 case MRRS_128B: 3074 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_128B; 3075 break; 3076 case MRRS_256B: 3077 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_256B; 3078 break; 3079 default: 3080 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_512B; 3081 break; 3082 } 3083 3084 /* 3085 * Must check before reset_mac_processor 3086 */ 3087 jme_check_hw_ver(jme); 3088 jme->mii_if.dev = netdev; 3089 if (jme->fpgaver) { 3090 jme->mii_if.phy_id = 0; 3091 for (i = 1 ; i < 32 ; ++i) { 3092 bmcr = jme_mdio_read(netdev, i, MII_BMCR); 3093 bmsr = jme_mdio_read(netdev, i, MII_BMSR); 3094 if (bmcr != 0xFFFFU && (bmcr != 0 || bmsr != 0)) { 3095 jme->mii_if.phy_id = i; 3096 break; 3097 } 3098 } 3099 3100 if (!jme->mii_if.phy_id) { 3101 rc = -EIO; 3102 pr_err("Can not find phy_id\n"); 3103 goto err_out_unmap; 3104 } 3105 3106 jme->reg_ghc |= GHC_LINK_POLL; 3107 } else { 3108 jme->mii_if.phy_id = 1; 3109 } 3110 if (pdev->device == PCI_DEVICE_ID_JMICRON_JMC250) 3111 jme->mii_if.supports_gmii = true; 3112 else 3113 jme->mii_if.supports_gmii = false; 3114 jme->mii_if.phy_id_mask = 0x1F; 3115 jme->mii_if.reg_num_mask = 0x1F; 3116 jme->mii_if.mdio_read = jme_mdio_read; 3117 jme->mii_if.mdio_write = jme_mdio_write; 3118 3119 jme_clear_pm_disable_wol(jme); 3120 device_init_wakeup(&pdev->dev, true); 3121 3122 jme_set_phyfifo_5level(jme); 3123 jme->pcirev = pdev->revision; 3124 if (!jme->fpgaver) 3125 jme_phy_init(jme); 3126 jme_phy_off(jme); 3127 3128 /* 3129 * Reset MAC processor and reload EEPROM for MAC Address 3130 */ 3131 jme_reset_mac_processor(jme); 3132 rc = jme_reload_eeprom(jme); 3133 if (rc) { 3134 pr_err("Reload eeprom for reading MAC Address error\n"); 3135 goto err_out_unmap; 3136 } 3137 jme_load_macaddr(netdev); 3138 3139 /* 3140 * Tell stack that we are not ready to work until open() 3141 */ 3142 netif_carrier_off(netdev); 3143 3144 rc = register_netdev(netdev); 3145 if (rc) { 3146 pr_err("Cannot register net device\n"); 3147 goto err_out_unmap; 3148 } 3149 3150 netif_info(jme, probe, jme->dev, "%s%s chiprev:%x pcirev:%x macaddr:%pM\n", 3151 (jme->pdev->device == PCI_DEVICE_ID_JMICRON_JMC250) ? 3152 "JMC250 Gigabit Ethernet" : 3153 (jme->pdev->device == PCI_DEVICE_ID_JMICRON_JMC260) ? 3154 "JMC260 Fast Ethernet" : "Unknown", 3155 (jme->fpgaver != 0) ? " (FPGA)" : "", 3156 (jme->fpgaver != 0) ? jme->fpgaver : jme->chiprev, 3157 jme->pcirev, netdev->dev_addr); 3158 3159 return 0; 3160 3161 err_out_unmap: 3162 iounmap(jme->regs); 3163 err_out_free_netdev: 3164 free_netdev(netdev); 3165 err_out_release_regions: 3166 pci_release_regions(pdev); 3167 err_out_disable_pdev: 3168 pci_disable_device(pdev); 3169 err_out: 3170 return rc; 3171 } 3172 3173 static void 3174 jme_remove_one(struct pci_dev *pdev) 3175 { 3176 struct net_device *netdev = pci_get_drvdata(pdev); 3177 struct jme_adapter *jme = netdev_priv(netdev); 3178 3179 unregister_netdev(netdev); 3180 iounmap(jme->regs); 3181 free_netdev(netdev); 3182 pci_release_regions(pdev); 3183 pci_disable_device(pdev); 3184 3185 } 3186 3187 static void 3188 jme_shutdown(struct pci_dev *pdev) 3189 { 3190 struct net_device *netdev = pci_get_drvdata(pdev); 3191 struct jme_adapter *jme = netdev_priv(netdev); 3192 3193 jme_powersave_phy(jme); 3194 pci_pme_active(pdev, true); 3195 } 3196 3197 #ifdef CONFIG_PM_SLEEP 3198 static int 3199 jme_suspend(struct device *dev) 3200 { 3201 struct pci_dev *pdev = to_pci_dev(dev); 3202 struct net_device *netdev = pci_get_drvdata(pdev); 3203 struct jme_adapter *jme = netdev_priv(netdev); 3204 3205 if (!netif_running(netdev)) 3206 return 0; 3207 3208 atomic_dec(&jme->link_changing); 3209 3210 netif_device_detach(netdev); 3211 netif_stop_queue(netdev); 3212 jme_stop_irq(jme); 3213 3214 tasklet_disable(&jme->txclean_task); 3215 tasklet_disable(&jme->rxclean_task); 3216 tasklet_disable(&jme->rxempty_task); 3217 3218 if (netif_carrier_ok(netdev)) { 3219 if (test_bit(JME_FLAG_POLL, &jme->flags)) 3220 jme_polling_mode(jme); 3221 3222 jme_stop_pcc_timer(jme); 3223 jme_disable_rx_engine(jme); 3224 jme_disable_tx_engine(jme); 3225 jme_reset_mac_processor(jme); 3226 jme_free_rx_resources(jme); 3227 jme_free_tx_resources(jme); 3228 netif_carrier_off(netdev); 3229 jme->phylink = 0; 3230 } 3231 3232 tasklet_enable(&jme->txclean_task); 3233 tasklet_enable(&jme->rxclean_task); 3234 tasklet_enable(&jme->rxempty_task); 3235 3236 jme_powersave_phy(jme); 3237 3238 return 0; 3239 } 3240 3241 static int 3242 jme_resume(struct device *dev) 3243 { 3244 struct pci_dev *pdev = to_pci_dev(dev); 3245 struct net_device *netdev = pci_get_drvdata(pdev); 3246 struct jme_adapter *jme = netdev_priv(netdev); 3247 3248 if (!netif_running(netdev)) 3249 return 0; 3250 3251 jme_clear_pm_disable_wol(jme); 3252 jme_phy_on(jme); 3253 if (test_bit(JME_FLAG_SSET, &jme->flags)) 3254 jme_set_link_ksettings(netdev, &jme->old_cmd); 3255 else 3256 jme_reset_phy_processor(jme); 3257 jme_phy_calibration(jme); 3258 jme_phy_setEA(jme); 3259 netif_device_attach(netdev); 3260 3261 atomic_inc(&jme->link_changing); 3262 3263 jme_reset_link(jme); 3264 3265 jme_start_irq(jme); 3266 3267 return 0; 3268 } 3269 3270 static SIMPLE_DEV_PM_OPS(jme_pm_ops, jme_suspend, jme_resume); 3271 #define JME_PM_OPS (&jme_pm_ops) 3272 3273 #else 3274 3275 #define JME_PM_OPS NULL 3276 #endif 3277 3278 static const struct pci_device_id jme_pci_tbl[] = { 3279 { PCI_VDEVICE(JMICRON, PCI_DEVICE_ID_JMICRON_JMC250) }, 3280 { PCI_VDEVICE(JMICRON, PCI_DEVICE_ID_JMICRON_JMC260) }, 3281 { } 3282 }; 3283 3284 static struct pci_driver jme_driver = { 3285 .name = DRV_NAME, 3286 .id_table = jme_pci_tbl, 3287 .probe = jme_init_one, 3288 .remove = jme_remove_one, 3289 .shutdown = jme_shutdown, 3290 .driver.pm = JME_PM_OPS, 3291 }; 3292 3293 static int __init 3294 jme_init_module(void) 3295 { 3296 pr_info("JMicron JMC2XX ethernet driver version %s\n", DRV_VERSION); 3297 return pci_register_driver(&jme_driver); 3298 } 3299 3300 static void __exit 3301 jme_cleanup_module(void) 3302 { 3303 pci_unregister_driver(&jme_driver); 3304 } 3305 3306 module_init(jme_init_module); 3307 module_exit(jme_cleanup_module); 3308 3309 MODULE_AUTHOR("Guo-Fu Tseng <cooldavid@cooldavid.org>"); 3310 MODULE_DESCRIPTION("JMicron JMC2x0 PCI Express Ethernet driver"); 3311 MODULE_LICENSE("GPL"); 3312 MODULE_VERSION(DRV_VERSION); 3313 MODULE_DEVICE_TABLE(pci, jme_pci_tbl); 3314