1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Copyright(c) 1999 - 2018 Intel Corporation. */ 3 4 #ifndef _IXGBEVF_H_ 5 #define _IXGBEVF_H_ 6 7 #include <linux/types.h> 8 #include <linux/bitops.h> 9 #include <linux/timer.h> 10 #include <linux/io.h> 11 #include <linux/netdevice.h> 12 #include <linux/if_vlan.h> 13 #include <linux/u64_stats_sync.h> 14 #include <net/xdp.h> 15 16 #include "vf.h" 17 18 #define IXGBE_MAX_TXD_PWR 14 19 #define IXGBE_MAX_DATA_PER_TXD BIT(IXGBE_MAX_TXD_PWR) 20 21 /* Tx Descriptors needed, worst case */ 22 #define TXD_USE_COUNT(S) DIV_ROUND_UP((S), IXGBE_MAX_DATA_PER_TXD) 23 #define DESC_NEEDED (MAX_SKB_FRAGS + 4) 24 25 /* wrapper around a pointer to a socket buffer, 26 * so a DMA handle can be stored along with the buffer 27 */ 28 struct ixgbevf_tx_buffer { 29 union ixgbe_adv_tx_desc *next_to_watch; 30 unsigned long time_stamp; 31 union { 32 struct sk_buff *skb; 33 /* XDP uses address ptr on irq_clean */ 34 void *data; 35 }; 36 unsigned int bytecount; 37 unsigned short gso_segs; 38 __be16 protocol; 39 DEFINE_DMA_UNMAP_ADDR(dma); 40 DEFINE_DMA_UNMAP_LEN(len); 41 u32 tx_flags; 42 }; 43 44 struct ixgbevf_rx_buffer { 45 dma_addr_t dma; 46 struct page *page; 47 #if (BITS_PER_LONG > 32) || (PAGE_SIZE >= 65536) 48 __u32 page_offset; 49 #else 50 __u16 page_offset; 51 #endif 52 __u16 pagecnt_bias; 53 }; 54 55 struct ixgbevf_stats { 56 u64 packets; 57 u64 bytes; 58 }; 59 60 struct ixgbevf_tx_queue_stats { 61 u64 restart_queue; 62 u64 tx_busy; 63 u64 tx_done_old; 64 }; 65 66 struct ixgbevf_rx_queue_stats { 67 u64 alloc_rx_page_failed; 68 u64 alloc_rx_buff_failed; 69 u64 alloc_rx_page; 70 u64 csum_err; 71 }; 72 73 enum ixgbevf_ring_state_t { 74 __IXGBEVF_RX_3K_BUFFER, 75 __IXGBEVF_RX_BUILD_SKB_ENABLED, 76 __IXGBEVF_TX_DETECT_HANG, 77 __IXGBEVF_HANG_CHECK_ARMED, 78 __IXGBEVF_TX_XDP_RING, 79 __IXGBEVF_TX_XDP_RING_PRIMED, 80 }; 81 82 #define ring_is_xdp(ring) \ 83 test_bit(__IXGBEVF_TX_XDP_RING, &(ring)->state) 84 #define set_ring_xdp(ring) \ 85 set_bit(__IXGBEVF_TX_XDP_RING, &(ring)->state) 86 #define clear_ring_xdp(ring) \ 87 clear_bit(__IXGBEVF_TX_XDP_RING, &(ring)->state) 88 89 struct ixgbevf_ring { 90 struct ixgbevf_ring *next; 91 struct ixgbevf_q_vector *q_vector; /* backpointer to q_vector */ 92 struct net_device *netdev; 93 struct bpf_prog *xdp_prog; 94 struct device *dev; 95 void *desc; /* descriptor ring memory */ 96 dma_addr_t dma; /* phys. address of descriptor ring */ 97 unsigned int size; /* length in bytes */ 98 u16 count; /* amount of descriptors */ 99 u16 next_to_use; 100 u16 next_to_clean; 101 u16 next_to_alloc; 102 103 union { 104 struct ixgbevf_tx_buffer *tx_buffer_info; 105 struct ixgbevf_rx_buffer *rx_buffer_info; 106 }; 107 unsigned long state; 108 struct ixgbevf_stats stats; 109 struct u64_stats_sync syncp; 110 union { 111 struct ixgbevf_tx_queue_stats tx_stats; 112 struct ixgbevf_rx_queue_stats rx_stats; 113 }; 114 struct xdp_rxq_info xdp_rxq; 115 u64 hw_csum_rx_error; 116 u8 __iomem *tail; 117 struct sk_buff *skb; 118 119 /* holds the special value that gets the hardware register offset 120 * associated with this ring, which is different for DCB and RSS modes 121 */ 122 u16 reg_idx; 123 int queue_index; /* needed for multiqueue queue management */ 124 } ____cacheline_internodealigned_in_smp; 125 126 /* How many Rx Buffers do we bundle into one write to the hardware ? */ 127 #define IXGBEVF_RX_BUFFER_WRITE 16 /* Must be power of 2 */ 128 129 #define MAX_RX_QUEUES IXGBE_VF_MAX_RX_QUEUES 130 #define MAX_TX_QUEUES IXGBE_VF_MAX_TX_QUEUES 131 #define MAX_XDP_QUEUES IXGBE_VF_MAX_TX_QUEUES 132 #define IXGBEVF_MAX_RSS_QUEUES 2 133 #define IXGBEVF_82599_RETA_SIZE 128 /* 128 entries */ 134 #define IXGBEVF_X550_VFRETA_SIZE 64 /* 64 entries */ 135 #define IXGBEVF_RSS_HASH_KEY_SIZE 40 136 #define IXGBEVF_VFRSSRK_REGS 10 /* 10 registers for RSS key */ 137 138 #define IXGBEVF_DEFAULT_TXD 1024 139 #define IXGBEVF_DEFAULT_RXD 512 140 #define IXGBEVF_MAX_TXD 4096 141 #define IXGBEVF_MIN_TXD 64 142 #define IXGBEVF_MAX_RXD 4096 143 #define IXGBEVF_MIN_RXD 64 144 145 /* Supported Rx Buffer Sizes */ 146 #define IXGBEVF_RXBUFFER_256 256 /* Used for packet split */ 147 #define IXGBEVF_RXBUFFER_2048 2048 148 #define IXGBEVF_RXBUFFER_3072 3072 149 150 #define IXGBEVF_RX_HDR_SIZE IXGBEVF_RXBUFFER_256 151 152 #define MAXIMUM_ETHERNET_VLAN_SIZE (VLAN_ETH_FRAME_LEN + ETH_FCS_LEN) 153 154 #define IXGBEVF_SKB_PAD (NET_SKB_PAD + NET_IP_ALIGN) 155 #if (PAGE_SIZE < 8192) 156 #define IXGBEVF_MAX_FRAME_BUILD_SKB \ 157 (SKB_WITH_OVERHEAD(IXGBEVF_RXBUFFER_2048) - IXGBEVF_SKB_PAD) 158 #else 159 #define IXGBEVF_MAX_FRAME_BUILD_SKB IXGBEVF_RXBUFFER_2048 160 #endif 161 162 #define IXGBE_TX_FLAGS_CSUM BIT(0) 163 #define IXGBE_TX_FLAGS_VLAN BIT(1) 164 #define IXGBE_TX_FLAGS_TSO BIT(2) 165 #define IXGBE_TX_FLAGS_IPV4 BIT(3) 166 #define IXGBE_TX_FLAGS_VLAN_MASK 0xffff0000 167 #define IXGBE_TX_FLAGS_VLAN_PRIO_MASK 0x0000e000 168 #define IXGBE_TX_FLAGS_VLAN_SHIFT 16 169 170 #define ring_uses_large_buffer(ring) \ 171 test_bit(__IXGBEVF_RX_3K_BUFFER, &(ring)->state) 172 #define set_ring_uses_large_buffer(ring) \ 173 set_bit(__IXGBEVF_RX_3K_BUFFER, &(ring)->state) 174 #define clear_ring_uses_large_buffer(ring) \ 175 clear_bit(__IXGBEVF_RX_3K_BUFFER, &(ring)->state) 176 177 #define ring_uses_build_skb(ring) \ 178 test_bit(__IXGBEVF_RX_BUILD_SKB_ENABLED, &(ring)->state) 179 #define set_ring_build_skb_enabled(ring) \ 180 set_bit(__IXGBEVF_RX_BUILD_SKB_ENABLED, &(ring)->state) 181 #define clear_ring_build_skb_enabled(ring) \ 182 clear_bit(__IXGBEVF_RX_BUILD_SKB_ENABLED, &(ring)->state) 183 184 static inline unsigned int ixgbevf_rx_bufsz(struct ixgbevf_ring *ring) 185 { 186 #if (PAGE_SIZE < 8192) 187 if (ring_uses_large_buffer(ring)) 188 return IXGBEVF_RXBUFFER_3072; 189 190 if (ring_uses_build_skb(ring)) 191 return IXGBEVF_MAX_FRAME_BUILD_SKB; 192 #endif 193 return IXGBEVF_RXBUFFER_2048; 194 } 195 196 static inline unsigned int ixgbevf_rx_pg_order(struct ixgbevf_ring *ring) 197 { 198 #if (PAGE_SIZE < 8192) 199 if (ring_uses_large_buffer(ring)) 200 return 1; 201 #endif 202 return 0; 203 } 204 205 #define ixgbevf_rx_pg_size(_ring) (PAGE_SIZE << ixgbevf_rx_pg_order(_ring)) 206 207 #define check_for_tx_hang(ring) \ 208 test_bit(__IXGBEVF_TX_DETECT_HANG, &(ring)->state) 209 #define set_check_for_tx_hang(ring) \ 210 set_bit(__IXGBEVF_TX_DETECT_HANG, &(ring)->state) 211 #define clear_check_for_tx_hang(ring) \ 212 clear_bit(__IXGBEVF_TX_DETECT_HANG, &(ring)->state) 213 214 struct ixgbevf_ring_container { 215 struct ixgbevf_ring *ring; /* pointer to linked list of rings */ 216 unsigned int total_bytes; /* total bytes processed this int */ 217 unsigned int total_packets; /* total packets processed this int */ 218 u8 count; /* total number of rings in vector */ 219 u8 itr; /* current ITR setting for ring */ 220 }; 221 222 /* iterator for handling rings in ring container */ 223 #define ixgbevf_for_each_ring(pos, head) \ 224 for (pos = (head).ring; pos != NULL; pos = pos->next) 225 226 /* MAX_MSIX_Q_VECTORS of these are allocated, 227 * but we only use one per queue-specific vector. 228 */ 229 struct ixgbevf_q_vector { 230 struct ixgbevf_adapter *adapter; 231 /* index of q_vector within array, also used for finding the bit in 232 * EICR and friends that represents the vector for this ring 233 */ 234 u16 v_idx; 235 u16 itr; /* Interrupt throttle rate written to EITR */ 236 struct napi_struct napi; 237 struct ixgbevf_ring_container rx, tx; 238 struct rcu_head rcu; /* to avoid race with update stats on free */ 239 char name[IFNAMSIZ + 9]; 240 241 /* for dynamic allocation of rings associated with this q_vector */ 242 struct ixgbevf_ring ring[0] ____cacheline_internodealigned_in_smp; 243 #ifdef CONFIG_NET_RX_BUSY_POLL 244 unsigned int state; 245 #define IXGBEVF_QV_STATE_IDLE 0 246 #define IXGBEVF_QV_STATE_NAPI 1 /* NAPI owns this QV */ 247 #define IXGBEVF_QV_STATE_POLL 2 /* poll owns this QV */ 248 #define IXGBEVF_QV_STATE_DISABLED 4 /* QV is disabled */ 249 #define IXGBEVF_QV_OWNED (IXGBEVF_QV_STATE_NAPI | IXGBEVF_QV_STATE_POLL) 250 #define IXGBEVF_QV_LOCKED (IXGBEVF_QV_OWNED | IXGBEVF_QV_STATE_DISABLED) 251 #define IXGBEVF_QV_STATE_NAPI_YIELD 8 /* NAPI yielded this QV */ 252 #define IXGBEVF_QV_STATE_POLL_YIELD 16 /* poll yielded this QV */ 253 #define IXGBEVF_QV_YIELD (IXGBEVF_QV_STATE_NAPI_YIELD | \ 254 IXGBEVF_QV_STATE_POLL_YIELD) 255 #define IXGBEVF_QV_USER_PEND (IXGBEVF_QV_STATE_POLL | \ 256 IXGBEVF_QV_STATE_POLL_YIELD) 257 spinlock_t lock; 258 #endif /* CONFIG_NET_RX_BUSY_POLL */ 259 }; 260 261 /* microsecond values for various ITR rates shifted by 2 to fit itr register 262 * with the first 3 bits reserved 0 263 */ 264 #define IXGBE_MIN_RSC_ITR 24 265 #define IXGBE_100K_ITR 40 266 #define IXGBE_20K_ITR 200 267 #define IXGBE_12K_ITR 336 268 269 /* Helper macros to switch between ints/sec and what the register uses. 270 * And yes, it's the same math going both ways. The lowest value 271 * supported by all of the ixgbe hardware is 8. 272 */ 273 #define EITR_INTS_PER_SEC_TO_REG(_eitr) \ 274 ((_eitr) ? (1000000000 / ((_eitr) * 256)) : 8) 275 #define EITR_REG_TO_INTS_PER_SEC EITR_INTS_PER_SEC_TO_REG 276 277 /* ixgbevf_test_staterr - tests bits in Rx descriptor status and error fields */ 278 static inline __le32 ixgbevf_test_staterr(union ixgbe_adv_rx_desc *rx_desc, 279 const u32 stat_err_bits) 280 { 281 return rx_desc->wb.upper.status_error & cpu_to_le32(stat_err_bits); 282 } 283 284 static inline u16 ixgbevf_desc_unused(struct ixgbevf_ring *ring) 285 { 286 u16 ntc = ring->next_to_clean; 287 u16 ntu = ring->next_to_use; 288 289 return ((ntc > ntu) ? 0 : ring->count) + ntc - ntu - 1; 290 } 291 292 static inline void ixgbevf_write_tail(struct ixgbevf_ring *ring, u32 value) 293 { 294 writel(value, ring->tail); 295 } 296 297 #define IXGBEVF_RX_DESC(R, i) \ 298 (&(((union ixgbe_adv_rx_desc *)((R)->desc))[i])) 299 #define IXGBEVF_TX_DESC(R, i) \ 300 (&(((union ixgbe_adv_tx_desc *)((R)->desc))[i])) 301 #define IXGBEVF_TX_CTXTDESC(R, i) \ 302 (&(((struct ixgbe_adv_tx_context_desc *)((R)->desc))[i])) 303 304 #define IXGBE_MAX_JUMBO_FRAME_SIZE 9728 /* Maximum Supported Size 9.5KB */ 305 306 #define OTHER_VECTOR 1 307 #define NON_Q_VECTORS (OTHER_VECTOR) 308 309 #define MAX_MSIX_Q_VECTORS 2 310 311 #define MIN_MSIX_Q_VECTORS 1 312 #define MIN_MSIX_COUNT (MIN_MSIX_Q_VECTORS + NON_Q_VECTORS) 313 314 #define IXGBEVF_RX_DMA_ATTR \ 315 (DMA_ATTR_SKIP_CPU_SYNC | DMA_ATTR_WEAK_ORDERING) 316 317 /* board specific private data structure */ 318 struct ixgbevf_adapter { 319 /* this field must be first, see ixgbevf_process_skb_fields */ 320 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)]; 321 322 struct ixgbevf_q_vector *q_vector[MAX_MSIX_Q_VECTORS]; 323 324 /* Interrupt Throttle Rate */ 325 u16 rx_itr_setting; 326 u16 tx_itr_setting; 327 328 /* interrupt masks */ 329 u32 eims_enable_mask; 330 u32 eims_other; 331 332 /* XDP */ 333 int num_xdp_queues; 334 struct ixgbevf_ring *xdp_ring[MAX_XDP_QUEUES]; 335 336 /* TX */ 337 int num_tx_queues; 338 struct ixgbevf_ring *tx_ring[MAX_TX_QUEUES]; /* One per active queue */ 339 u64 restart_queue; 340 u32 tx_timeout_count; 341 342 /* RX */ 343 int num_rx_queues; 344 struct ixgbevf_ring *rx_ring[MAX_TX_QUEUES]; /* One per active queue */ 345 u64 hw_csum_rx_error; 346 u64 hw_rx_no_dma_resources; 347 int num_msix_vectors; 348 u64 alloc_rx_page_failed; 349 u64 alloc_rx_buff_failed; 350 u64 alloc_rx_page; 351 352 struct msix_entry *msix_entries; 353 354 /* OS defined structs */ 355 struct net_device *netdev; 356 struct bpf_prog *xdp_prog; 357 struct pci_dev *pdev; 358 359 /* structs defined in ixgbe_vf.h */ 360 struct ixgbe_hw hw; 361 u16 msg_enable; 362 /* Interrupt Throttle Rate */ 363 u32 eitr_param; 364 365 struct ixgbevf_hw_stats stats; 366 367 unsigned long state; 368 u64 tx_busy; 369 unsigned int tx_ring_count; 370 unsigned int xdp_ring_count; 371 unsigned int rx_ring_count; 372 373 u8 __iomem *io_addr; /* Mainly for iounmap use */ 374 u32 link_speed; 375 bool link_up; 376 377 struct timer_list service_timer; 378 struct work_struct service_task; 379 380 spinlock_t mbx_lock; 381 unsigned long last_reset; 382 383 u32 *rss_key; 384 u8 rss_indir_tbl[IXGBEVF_X550_VFRETA_SIZE]; 385 u32 flags; 386 #define IXGBEVF_FLAGS_LEGACY_RX BIT(1) 387 }; 388 389 enum ixbgevf_state_t { 390 __IXGBEVF_TESTING, 391 __IXGBEVF_RESETTING, 392 __IXGBEVF_DOWN, 393 __IXGBEVF_DISABLED, 394 __IXGBEVF_REMOVING, 395 __IXGBEVF_SERVICE_SCHED, 396 __IXGBEVF_SERVICE_INITED, 397 __IXGBEVF_RESET_REQUESTED, 398 __IXGBEVF_QUEUE_RESET_REQUESTED, 399 }; 400 401 enum ixgbevf_boards { 402 board_82599_vf, 403 board_82599_vf_hv, 404 board_X540_vf, 405 board_X540_vf_hv, 406 board_X550_vf, 407 board_X550_vf_hv, 408 board_X550EM_x_vf, 409 board_X550EM_x_vf_hv, 410 board_x550em_a_vf, 411 }; 412 413 enum ixgbevf_xcast_modes { 414 IXGBEVF_XCAST_MODE_NONE = 0, 415 IXGBEVF_XCAST_MODE_MULTI, 416 IXGBEVF_XCAST_MODE_ALLMULTI, 417 IXGBEVF_XCAST_MODE_PROMISC, 418 }; 419 420 extern const struct ixgbevf_info ixgbevf_82599_vf_info; 421 extern const struct ixgbevf_info ixgbevf_X540_vf_info; 422 extern const struct ixgbevf_info ixgbevf_X550_vf_info; 423 extern const struct ixgbevf_info ixgbevf_X550EM_x_vf_info; 424 extern const struct ixgbe_mbx_operations ixgbevf_mbx_ops; 425 extern const struct ixgbevf_info ixgbevf_x550em_a_vf_info; 426 427 extern const struct ixgbevf_info ixgbevf_82599_vf_hv_info; 428 extern const struct ixgbevf_info ixgbevf_X540_vf_hv_info; 429 extern const struct ixgbevf_info ixgbevf_X550_vf_hv_info; 430 extern const struct ixgbevf_info ixgbevf_X550EM_x_vf_hv_info; 431 extern const struct ixgbe_mbx_operations ixgbevf_hv_mbx_ops; 432 433 /* needed by ethtool.c */ 434 extern const char ixgbevf_driver_name[]; 435 extern const char ixgbevf_driver_version[]; 436 437 int ixgbevf_open(struct net_device *netdev); 438 int ixgbevf_close(struct net_device *netdev); 439 void ixgbevf_up(struct ixgbevf_adapter *adapter); 440 void ixgbevf_down(struct ixgbevf_adapter *adapter); 441 void ixgbevf_reinit_locked(struct ixgbevf_adapter *adapter); 442 void ixgbevf_reset(struct ixgbevf_adapter *adapter); 443 void ixgbevf_set_ethtool_ops(struct net_device *netdev); 444 int ixgbevf_setup_rx_resources(struct ixgbevf_adapter *adapter, 445 struct ixgbevf_ring *rx_ring); 446 int ixgbevf_setup_tx_resources(struct ixgbevf_ring *); 447 void ixgbevf_free_rx_resources(struct ixgbevf_ring *); 448 void ixgbevf_free_tx_resources(struct ixgbevf_ring *); 449 void ixgbevf_update_stats(struct ixgbevf_adapter *adapter); 450 int ethtool_ioctl(struct ifreq *ifr); 451 452 extern void ixgbevf_write_eitr(struct ixgbevf_q_vector *q_vector); 453 454 void ixgbe_napi_add_all(struct ixgbevf_adapter *adapter); 455 void ixgbe_napi_del_all(struct ixgbevf_adapter *adapter); 456 457 #define ixgbevf_hw_to_netdev(hw) \ 458 (((struct ixgbevf_adapter *)(hw)->back)->netdev) 459 460 #define hw_dbg(hw, format, arg...) \ 461 netdev_dbg(ixgbevf_hw_to_netdev(hw), format, ## arg) 462 #endif /* _IXGBEVF_H_ */ 463