1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Copyright(c) 1999 - 2018 Intel Corporation. */ 3 4 #ifndef _IXGBEVF_H_ 5 #define _IXGBEVF_H_ 6 7 #include <linux/types.h> 8 #include <linux/bitops.h> 9 #include <linux/timer.h> 10 #include <linux/io.h> 11 #include <linux/netdevice.h> 12 #include <linux/if_vlan.h> 13 #include <linux/u64_stats_sync.h> 14 #include <net/xdp.h> 15 16 #include "vf.h" 17 18 #define IXGBE_MAX_TXD_PWR 14 19 #define IXGBE_MAX_DATA_PER_TXD BIT(IXGBE_MAX_TXD_PWR) 20 21 /* Tx Descriptors needed, worst case */ 22 #define TXD_USE_COUNT(S) DIV_ROUND_UP((S), IXGBE_MAX_DATA_PER_TXD) 23 #define DESC_NEEDED (MAX_SKB_FRAGS + 4) 24 25 /* wrapper around a pointer to a socket buffer, 26 * so a DMA handle can be stored along with the buffer 27 */ 28 struct ixgbevf_tx_buffer { 29 union ixgbe_adv_tx_desc *next_to_watch; 30 unsigned long time_stamp; 31 union { 32 struct sk_buff *skb; 33 /* XDP uses address ptr on irq_clean */ 34 void *data; 35 }; 36 unsigned int bytecount; 37 unsigned short gso_segs; 38 __be16 protocol; 39 DEFINE_DMA_UNMAP_ADDR(dma); 40 DEFINE_DMA_UNMAP_LEN(len); 41 u32 tx_flags; 42 }; 43 44 struct ixgbevf_rx_buffer { 45 dma_addr_t dma; 46 struct page *page; 47 #if (BITS_PER_LONG > 32) || (PAGE_SIZE >= 65536) 48 __u32 page_offset; 49 #else 50 __u16 page_offset; 51 #endif 52 __u16 pagecnt_bias; 53 }; 54 55 struct ixgbevf_stats { 56 u64 packets; 57 u64 bytes; 58 }; 59 60 struct ixgbevf_tx_queue_stats { 61 u64 restart_queue; 62 u64 tx_busy; 63 u64 tx_done_old; 64 }; 65 66 struct ixgbevf_rx_queue_stats { 67 u64 alloc_rx_page_failed; 68 u64 alloc_rx_buff_failed; 69 u64 alloc_rx_page; 70 u64 csum_err; 71 }; 72 73 enum ixgbevf_ring_state_t { 74 __IXGBEVF_RX_3K_BUFFER, 75 __IXGBEVF_RX_BUILD_SKB_ENABLED, 76 __IXGBEVF_TX_DETECT_HANG, 77 __IXGBEVF_HANG_CHECK_ARMED, 78 __IXGBEVF_TX_XDP_RING, 79 }; 80 81 #define ring_is_xdp(ring) \ 82 test_bit(__IXGBEVF_TX_XDP_RING, &(ring)->state) 83 #define set_ring_xdp(ring) \ 84 set_bit(__IXGBEVF_TX_XDP_RING, &(ring)->state) 85 #define clear_ring_xdp(ring) \ 86 clear_bit(__IXGBEVF_TX_XDP_RING, &(ring)->state) 87 88 struct ixgbevf_ring { 89 struct ixgbevf_ring *next; 90 struct ixgbevf_q_vector *q_vector; /* backpointer to q_vector */ 91 struct net_device *netdev; 92 struct bpf_prog *xdp_prog; 93 struct device *dev; 94 void *desc; /* descriptor ring memory */ 95 dma_addr_t dma; /* phys. address of descriptor ring */ 96 unsigned int size; /* length in bytes */ 97 u16 count; /* amount of descriptors */ 98 u16 next_to_use; 99 u16 next_to_clean; 100 u16 next_to_alloc; 101 102 union { 103 struct ixgbevf_tx_buffer *tx_buffer_info; 104 struct ixgbevf_rx_buffer *rx_buffer_info; 105 }; 106 unsigned long state; 107 struct ixgbevf_stats stats; 108 struct u64_stats_sync syncp; 109 union { 110 struct ixgbevf_tx_queue_stats tx_stats; 111 struct ixgbevf_rx_queue_stats rx_stats; 112 }; 113 struct xdp_rxq_info xdp_rxq; 114 u64 hw_csum_rx_error; 115 u8 __iomem *tail; 116 struct sk_buff *skb; 117 118 /* holds the special value that gets the hardware register offset 119 * associated with this ring, which is different for DCB and RSS modes 120 */ 121 u16 reg_idx; 122 int queue_index; /* needed for multiqueue queue management */ 123 } ____cacheline_internodealigned_in_smp; 124 125 /* How many Rx Buffers do we bundle into one write to the hardware ? */ 126 #define IXGBEVF_RX_BUFFER_WRITE 16 /* Must be power of 2 */ 127 128 #define MAX_RX_QUEUES IXGBE_VF_MAX_RX_QUEUES 129 #define MAX_TX_QUEUES IXGBE_VF_MAX_TX_QUEUES 130 #define MAX_XDP_QUEUES IXGBE_VF_MAX_TX_QUEUES 131 #define IXGBEVF_MAX_RSS_QUEUES 2 132 #define IXGBEVF_82599_RETA_SIZE 128 /* 128 entries */ 133 #define IXGBEVF_X550_VFRETA_SIZE 64 /* 64 entries */ 134 #define IXGBEVF_RSS_HASH_KEY_SIZE 40 135 #define IXGBEVF_VFRSSRK_REGS 10 /* 10 registers for RSS key */ 136 137 #define IXGBEVF_DEFAULT_TXD 1024 138 #define IXGBEVF_DEFAULT_RXD 512 139 #define IXGBEVF_MAX_TXD 4096 140 #define IXGBEVF_MIN_TXD 64 141 #define IXGBEVF_MAX_RXD 4096 142 #define IXGBEVF_MIN_RXD 64 143 144 /* Supported Rx Buffer Sizes */ 145 #define IXGBEVF_RXBUFFER_256 256 /* Used for packet split */ 146 #define IXGBEVF_RXBUFFER_2048 2048 147 #define IXGBEVF_RXBUFFER_3072 3072 148 149 #define IXGBEVF_RX_HDR_SIZE IXGBEVF_RXBUFFER_256 150 151 #define MAXIMUM_ETHERNET_VLAN_SIZE (VLAN_ETH_FRAME_LEN + ETH_FCS_LEN) 152 153 #define IXGBEVF_SKB_PAD (NET_SKB_PAD + NET_IP_ALIGN) 154 #if (PAGE_SIZE < 8192) 155 #define IXGBEVF_MAX_FRAME_BUILD_SKB \ 156 (SKB_WITH_OVERHEAD(IXGBEVF_RXBUFFER_2048) - IXGBEVF_SKB_PAD) 157 #else 158 #define IXGBEVF_MAX_FRAME_BUILD_SKB IXGBEVF_RXBUFFER_2048 159 #endif 160 161 #define IXGBE_TX_FLAGS_CSUM BIT(0) 162 #define IXGBE_TX_FLAGS_VLAN BIT(1) 163 #define IXGBE_TX_FLAGS_TSO BIT(2) 164 #define IXGBE_TX_FLAGS_IPV4 BIT(3) 165 #define IXGBE_TX_FLAGS_VLAN_MASK 0xffff0000 166 #define IXGBE_TX_FLAGS_VLAN_PRIO_MASK 0x0000e000 167 #define IXGBE_TX_FLAGS_VLAN_SHIFT 16 168 169 #define ring_uses_large_buffer(ring) \ 170 test_bit(__IXGBEVF_RX_3K_BUFFER, &(ring)->state) 171 #define set_ring_uses_large_buffer(ring) \ 172 set_bit(__IXGBEVF_RX_3K_BUFFER, &(ring)->state) 173 #define clear_ring_uses_large_buffer(ring) \ 174 clear_bit(__IXGBEVF_RX_3K_BUFFER, &(ring)->state) 175 176 #define ring_uses_build_skb(ring) \ 177 test_bit(__IXGBEVF_RX_BUILD_SKB_ENABLED, &(ring)->state) 178 #define set_ring_build_skb_enabled(ring) \ 179 set_bit(__IXGBEVF_RX_BUILD_SKB_ENABLED, &(ring)->state) 180 #define clear_ring_build_skb_enabled(ring) \ 181 clear_bit(__IXGBEVF_RX_BUILD_SKB_ENABLED, &(ring)->state) 182 183 static inline unsigned int ixgbevf_rx_bufsz(struct ixgbevf_ring *ring) 184 { 185 #if (PAGE_SIZE < 8192) 186 if (ring_uses_large_buffer(ring)) 187 return IXGBEVF_RXBUFFER_3072; 188 189 if (ring_uses_build_skb(ring)) 190 return IXGBEVF_MAX_FRAME_BUILD_SKB; 191 #endif 192 return IXGBEVF_RXBUFFER_2048; 193 } 194 195 static inline unsigned int ixgbevf_rx_pg_order(struct ixgbevf_ring *ring) 196 { 197 #if (PAGE_SIZE < 8192) 198 if (ring_uses_large_buffer(ring)) 199 return 1; 200 #endif 201 return 0; 202 } 203 204 #define ixgbevf_rx_pg_size(_ring) (PAGE_SIZE << ixgbevf_rx_pg_order(_ring)) 205 206 #define check_for_tx_hang(ring) \ 207 test_bit(__IXGBEVF_TX_DETECT_HANG, &(ring)->state) 208 #define set_check_for_tx_hang(ring) \ 209 set_bit(__IXGBEVF_TX_DETECT_HANG, &(ring)->state) 210 #define clear_check_for_tx_hang(ring) \ 211 clear_bit(__IXGBEVF_TX_DETECT_HANG, &(ring)->state) 212 213 struct ixgbevf_ring_container { 214 struct ixgbevf_ring *ring; /* pointer to linked list of rings */ 215 unsigned int total_bytes; /* total bytes processed this int */ 216 unsigned int total_packets; /* total packets processed this int */ 217 u8 count; /* total number of rings in vector */ 218 u8 itr; /* current ITR setting for ring */ 219 }; 220 221 /* iterator for handling rings in ring container */ 222 #define ixgbevf_for_each_ring(pos, head) \ 223 for (pos = (head).ring; pos != NULL; pos = pos->next) 224 225 /* MAX_MSIX_Q_VECTORS of these are allocated, 226 * but we only use one per queue-specific vector. 227 */ 228 struct ixgbevf_q_vector { 229 struct ixgbevf_adapter *adapter; 230 /* index of q_vector within array, also used for finding the bit in 231 * EICR and friends that represents the vector for this ring 232 */ 233 u16 v_idx; 234 u16 itr; /* Interrupt throttle rate written to EITR */ 235 struct napi_struct napi; 236 struct ixgbevf_ring_container rx, tx; 237 struct rcu_head rcu; /* to avoid race with update stats on free */ 238 char name[IFNAMSIZ + 9]; 239 240 /* for dynamic allocation of rings associated with this q_vector */ 241 struct ixgbevf_ring ring[0] ____cacheline_internodealigned_in_smp; 242 #ifdef CONFIG_NET_RX_BUSY_POLL 243 unsigned int state; 244 #define IXGBEVF_QV_STATE_IDLE 0 245 #define IXGBEVF_QV_STATE_NAPI 1 /* NAPI owns this QV */ 246 #define IXGBEVF_QV_STATE_POLL 2 /* poll owns this QV */ 247 #define IXGBEVF_QV_STATE_DISABLED 4 /* QV is disabled */ 248 #define IXGBEVF_QV_OWNED (IXGBEVF_QV_STATE_NAPI | IXGBEVF_QV_STATE_POLL) 249 #define IXGBEVF_QV_LOCKED (IXGBEVF_QV_OWNED | IXGBEVF_QV_STATE_DISABLED) 250 #define IXGBEVF_QV_STATE_NAPI_YIELD 8 /* NAPI yielded this QV */ 251 #define IXGBEVF_QV_STATE_POLL_YIELD 16 /* poll yielded this QV */ 252 #define IXGBEVF_QV_YIELD (IXGBEVF_QV_STATE_NAPI_YIELD | \ 253 IXGBEVF_QV_STATE_POLL_YIELD) 254 #define IXGBEVF_QV_USER_PEND (IXGBEVF_QV_STATE_POLL | \ 255 IXGBEVF_QV_STATE_POLL_YIELD) 256 spinlock_t lock; 257 #endif /* CONFIG_NET_RX_BUSY_POLL */ 258 }; 259 260 /* microsecond values for various ITR rates shifted by 2 to fit itr register 261 * with the first 3 bits reserved 0 262 */ 263 #define IXGBE_MIN_RSC_ITR 24 264 #define IXGBE_100K_ITR 40 265 #define IXGBE_20K_ITR 200 266 #define IXGBE_12K_ITR 336 267 268 /* Helper macros to switch between ints/sec and what the register uses. 269 * And yes, it's the same math going both ways. The lowest value 270 * supported by all of the ixgbe hardware is 8. 271 */ 272 #define EITR_INTS_PER_SEC_TO_REG(_eitr) \ 273 ((_eitr) ? (1000000000 / ((_eitr) * 256)) : 8) 274 #define EITR_REG_TO_INTS_PER_SEC EITR_INTS_PER_SEC_TO_REG 275 276 /* ixgbevf_test_staterr - tests bits in Rx descriptor status and error fields */ 277 static inline __le32 ixgbevf_test_staterr(union ixgbe_adv_rx_desc *rx_desc, 278 const u32 stat_err_bits) 279 { 280 return rx_desc->wb.upper.status_error & cpu_to_le32(stat_err_bits); 281 } 282 283 static inline u16 ixgbevf_desc_unused(struct ixgbevf_ring *ring) 284 { 285 u16 ntc = ring->next_to_clean; 286 u16 ntu = ring->next_to_use; 287 288 return ((ntc > ntu) ? 0 : ring->count) + ntc - ntu - 1; 289 } 290 291 static inline void ixgbevf_write_tail(struct ixgbevf_ring *ring, u32 value) 292 { 293 writel(value, ring->tail); 294 } 295 296 #define IXGBEVF_RX_DESC(R, i) \ 297 (&(((union ixgbe_adv_rx_desc *)((R)->desc))[i])) 298 #define IXGBEVF_TX_DESC(R, i) \ 299 (&(((union ixgbe_adv_tx_desc *)((R)->desc))[i])) 300 #define IXGBEVF_TX_CTXTDESC(R, i) \ 301 (&(((struct ixgbe_adv_tx_context_desc *)((R)->desc))[i])) 302 303 #define IXGBE_MAX_JUMBO_FRAME_SIZE 9728 /* Maximum Supported Size 9.5KB */ 304 305 #define OTHER_VECTOR 1 306 #define NON_Q_VECTORS (OTHER_VECTOR) 307 308 #define MAX_MSIX_Q_VECTORS 2 309 310 #define MIN_MSIX_Q_VECTORS 1 311 #define MIN_MSIX_COUNT (MIN_MSIX_Q_VECTORS + NON_Q_VECTORS) 312 313 #define IXGBEVF_RX_DMA_ATTR \ 314 (DMA_ATTR_SKIP_CPU_SYNC | DMA_ATTR_WEAK_ORDERING) 315 316 /* board specific private data structure */ 317 struct ixgbevf_adapter { 318 /* this field must be first, see ixgbevf_process_skb_fields */ 319 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)]; 320 321 struct ixgbevf_q_vector *q_vector[MAX_MSIX_Q_VECTORS]; 322 323 /* Interrupt Throttle Rate */ 324 u16 rx_itr_setting; 325 u16 tx_itr_setting; 326 327 /* interrupt masks */ 328 u32 eims_enable_mask; 329 u32 eims_other; 330 331 /* XDP */ 332 int num_xdp_queues; 333 struct ixgbevf_ring *xdp_ring[MAX_XDP_QUEUES]; 334 335 /* TX */ 336 int num_tx_queues; 337 struct ixgbevf_ring *tx_ring[MAX_TX_QUEUES]; /* One per active queue */ 338 u64 restart_queue; 339 u32 tx_timeout_count; 340 341 /* RX */ 342 int num_rx_queues; 343 struct ixgbevf_ring *rx_ring[MAX_TX_QUEUES]; /* One per active queue */ 344 u64 hw_csum_rx_error; 345 u64 hw_rx_no_dma_resources; 346 int num_msix_vectors; 347 u64 alloc_rx_page_failed; 348 u64 alloc_rx_buff_failed; 349 u64 alloc_rx_page; 350 351 struct msix_entry *msix_entries; 352 353 /* OS defined structs */ 354 struct net_device *netdev; 355 struct bpf_prog *xdp_prog; 356 struct pci_dev *pdev; 357 358 /* structs defined in ixgbe_vf.h */ 359 struct ixgbe_hw hw; 360 u16 msg_enable; 361 /* Interrupt Throttle Rate */ 362 u32 eitr_param; 363 364 struct ixgbevf_hw_stats stats; 365 366 unsigned long state; 367 u64 tx_busy; 368 unsigned int tx_ring_count; 369 unsigned int xdp_ring_count; 370 unsigned int rx_ring_count; 371 372 u8 __iomem *io_addr; /* Mainly for iounmap use */ 373 u32 link_speed; 374 bool link_up; 375 376 struct timer_list service_timer; 377 struct work_struct service_task; 378 379 spinlock_t mbx_lock; 380 unsigned long last_reset; 381 382 u32 *rss_key; 383 u8 rss_indir_tbl[IXGBEVF_X550_VFRETA_SIZE]; 384 u32 flags; 385 #define IXGBEVF_FLAGS_LEGACY_RX BIT(1) 386 }; 387 388 enum ixbgevf_state_t { 389 __IXGBEVF_TESTING, 390 __IXGBEVF_RESETTING, 391 __IXGBEVF_DOWN, 392 __IXGBEVF_DISABLED, 393 __IXGBEVF_REMOVING, 394 __IXGBEVF_SERVICE_SCHED, 395 __IXGBEVF_SERVICE_INITED, 396 __IXGBEVF_RESET_REQUESTED, 397 __IXGBEVF_QUEUE_RESET_REQUESTED, 398 }; 399 400 enum ixgbevf_boards { 401 board_82599_vf, 402 board_82599_vf_hv, 403 board_X540_vf, 404 board_X540_vf_hv, 405 board_X550_vf, 406 board_X550_vf_hv, 407 board_X550EM_x_vf, 408 board_X550EM_x_vf_hv, 409 board_x550em_a_vf, 410 }; 411 412 enum ixgbevf_xcast_modes { 413 IXGBEVF_XCAST_MODE_NONE = 0, 414 IXGBEVF_XCAST_MODE_MULTI, 415 IXGBEVF_XCAST_MODE_ALLMULTI, 416 IXGBEVF_XCAST_MODE_PROMISC, 417 }; 418 419 extern const struct ixgbevf_info ixgbevf_82599_vf_info; 420 extern const struct ixgbevf_info ixgbevf_X540_vf_info; 421 extern const struct ixgbevf_info ixgbevf_X550_vf_info; 422 extern const struct ixgbevf_info ixgbevf_X550EM_x_vf_info; 423 extern const struct ixgbe_mbx_operations ixgbevf_mbx_ops; 424 extern const struct ixgbevf_info ixgbevf_x550em_a_vf_info; 425 426 extern const struct ixgbevf_info ixgbevf_82599_vf_hv_info; 427 extern const struct ixgbevf_info ixgbevf_X540_vf_hv_info; 428 extern const struct ixgbevf_info ixgbevf_X550_vf_hv_info; 429 extern const struct ixgbevf_info ixgbevf_X550EM_x_vf_hv_info; 430 extern const struct ixgbe_mbx_operations ixgbevf_hv_mbx_ops; 431 432 /* needed by ethtool.c */ 433 extern const char ixgbevf_driver_name[]; 434 extern const char ixgbevf_driver_version[]; 435 436 int ixgbevf_open(struct net_device *netdev); 437 int ixgbevf_close(struct net_device *netdev); 438 void ixgbevf_up(struct ixgbevf_adapter *adapter); 439 void ixgbevf_down(struct ixgbevf_adapter *adapter); 440 void ixgbevf_reinit_locked(struct ixgbevf_adapter *adapter); 441 void ixgbevf_reset(struct ixgbevf_adapter *adapter); 442 void ixgbevf_set_ethtool_ops(struct net_device *netdev); 443 int ixgbevf_setup_rx_resources(struct ixgbevf_adapter *adapter, 444 struct ixgbevf_ring *rx_ring); 445 int ixgbevf_setup_tx_resources(struct ixgbevf_ring *); 446 void ixgbevf_free_rx_resources(struct ixgbevf_ring *); 447 void ixgbevf_free_tx_resources(struct ixgbevf_ring *); 448 void ixgbevf_update_stats(struct ixgbevf_adapter *adapter); 449 int ethtool_ioctl(struct ifreq *ifr); 450 451 extern void ixgbevf_write_eitr(struct ixgbevf_q_vector *q_vector); 452 453 void ixgbe_napi_add_all(struct ixgbevf_adapter *adapter); 454 void ixgbe_napi_del_all(struct ixgbevf_adapter *adapter); 455 456 #define ixgbevf_hw_to_netdev(hw) \ 457 (((struct ixgbevf_adapter *)(hw)->back)->netdev) 458 459 #define hw_dbg(hw, format, arg...) \ 460 netdev_dbg(ixgbevf_hw_to_netdev(hw), format, ## arg) 461 #endif /* _IXGBEVF_H_ */ 462