1 /******************************************************************************* 2 3 Intel 82599 Virtual Function driver 4 Copyright(c) 1999 - 2015 Intel Corporation. 5 6 This program is free software; you can redistribute it and/or modify it 7 under the terms and conditions of the GNU General Public License, 8 version 2, as published by the Free Software Foundation. 9 10 This program is distributed in the hope it will be useful, but WITHOUT 11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 more details. 14 15 You should have received a copy of the GNU General Public License along with 16 this program; if not, see <http://www.gnu.org/licenses/>. 17 18 The full GNU General Public License is included in this distribution in 19 the file called "COPYING". 20 21 Contact Information: 22 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 23 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 24 25 *******************************************************************************/ 26 27 #ifndef _IXGBEVF_DEFINES_H_ 28 #define _IXGBEVF_DEFINES_H_ 29 30 /* Device IDs */ 31 #define IXGBE_DEV_ID_82599_VF 0x10ED 32 #define IXGBE_DEV_ID_X540_VF 0x1515 33 #define IXGBE_DEV_ID_X550_VF 0x1565 34 #define IXGBE_DEV_ID_X550EM_X_VF 0x15A8 35 36 #define IXGBE_DEV_ID_82599_VF_HV 0x152E 37 #define IXGBE_DEV_ID_X540_VF_HV 0x1530 38 #define IXGBE_DEV_ID_X550_VF_HV 0x1564 39 #define IXGBE_DEV_ID_X550EM_X_VF_HV 0x15A9 40 41 #define IXGBE_VF_IRQ_CLEAR_MASK 7 42 #define IXGBE_VF_MAX_TX_QUEUES 8 43 #define IXGBE_VF_MAX_RX_QUEUES 8 44 45 /* DCB define */ 46 #define IXGBE_VF_MAX_TRAFFIC_CLASS 8 47 48 /* Link speed */ 49 typedef u32 ixgbe_link_speed; 50 #define IXGBE_LINK_SPEED_1GB_FULL 0x0020 51 #define IXGBE_LINK_SPEED_10GB_FULL 0x0080 52 #define IXGBE_LINK_SPEED_100_FULL 0x0008 53 54 #define IXGBE_CTRL_RST 0x04000000 /* Reset (SW) */ 55 #define IXGBE_RXDCTL_ENABLE 0x02000000 /* Enable specific Rx Queue */ 56 #define IXGBE_TXDCTL_ENABLE 0x02000000 /* Enable specific Tx Queue */ 57 #define IXGBE_LINKS_UP 0x40000000 58 #define IXGBE_LINKS_SPEED_82599 0x30000000 59 #define IXGBE_LINKS_SPEED_10G_82599 0x30000000 60 #define IXGBE_LINKS_SPEED_1G_82599 0x20000000 61 #define IXGBE_LINKS_SPEED_100_82599 0x10000000 62 63 /* Number of Transmit and Receive Descriptors must be a multiple of 8 */ 64 #define IXGBE_REQ_TX_DESCRIPTOR_MULTIPLE 8 65 #define IXGBE_REQ_RX_DESCRIPTOR_MULTIPLE 8 66 #define IXGBE_REQ_TX_BUFFER_GRANULARITY 1024 67 68 /* Interrupt Vector Allocation Registers */ 69 #define IXGBE_IVAR_ALLOC_VAL 0x80 /* Interrupt Allocation valid */ 70 71 #define IXGBE_VF_INIT_TIMEOUT 200 /* Number of retries to clear RSTI */ 72 73 /* Receive Config masks */ 74 #define IXGBE_RXCTRL_RXEN 0x00000001 /* Enable Receiver */ 75 #define IXGBE_RXCTRL_DMBYPS 0x00000002 /* Descriptor Monitor Bypass */ 76 #define IXGBE_RXDCTL_ENABLE 0x02000000 /* Enable specific Rx Queue */ 77 #define IXGBE_RXDCTL_VME 0x40000000 /* VLAN mode enable */ 78 #define IXGBE_RXDCTL_RLPMLMASK 0x00003FFF /* Only supported on the X540 */ 79 #define IXGBE_RXDCTL_RLPML_EN 0x00008000 80 81 /* DCA Control */ 82 #define IXGBE_DCA_TXCTRL_TX_WB_RO_EN BIT(11) /* Tx Desc writeback RO bit */ 83 84 /* PSRTYPE bit definitions */ 85 #define IXGBE_PSRTYPE_TCPHDR 0x00000010 86 #define IXGBE_PSRTYPE_UDPHDR 0x00000020 87 #define IXGBE_PSRTYPE_IPV4HDR 0x00000100 88 #define IXGBE_PSRTYPE_IPV6HDR 0x00000200 89 #define IXGBE_PSRTYPE_L2HDR 0x00001000 90 91 /* SRRCTL bit definitions */ 92 #define IXGBE_SRRCTL_BSIZEPKT_SHIFT 10 /* so many KBs */ 93 #define IXGBE_SRRCTL_RDMTS_SHIFT 22 94 #define IXGBE_SRRCTL_RDMTS_MASK 0x01C00000 95 #define IXGBE_SRRCTL_DROP_EN 0x10000000 96 #define IXGBE_SRRCTL_BSIZEPKT_MASK 0x0000007F 97 #define IXGBE_SRRCTL_BSIZEHDR_MASK 0x00003F00 98 #define IXGBE_SRRCTL_DESCTYPE_LEGACY 0x00000000 99 #define IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF 0x02000000 100 #define IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT 0x04000000 101 #define IXGBE_SRRCTL_DESCTYPE_HDR_REPLICATION_LARGE_PKT 0x08000000 102 #define IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS 0x0A000000 103 #define IXGBE_SRRCTL_DESCTYPE_MASK 0x0E000000 104 105 /* Receive Descriptor bit definitions */ 106 #define IXGBE_RXD_STAT_DD 0x01 /* Descriptor Done */ 107 #define IXGBE_RXD_STAT_EOP 0x02 /* End of Packet */ 108 #define IXGBE_RXD_STAT_FLM 0x04 /* FDir Match */ 109 #define IXGBE_RXD_STAT_VP 0x08 /* IEEE VLAN Packet */ 110 #define IXGBE_RXDADV_NEXTP_MASK 0x000FFFF0 /* Next Descriptor Index */ 111 #define IXGBE_RXDADV_NEXTP_SHIFT 0x00000004 112 #define IXGBE_RXD_STAT_UDPCS 0x10 /* UDP xsum calculated */ 113 #define IXGBE_RXD_STAT_L4CS 0x20 /* L4 xsum calculated */ 114 #define IXGBE_RXD_STAT_IPCS 0x40 /* IP xsum calculated */ 115 #define IXGBE_RXD_STAT_PIF 0x80 /* passed in-exact filter */ 116 #define IXGBE_RXD_STAT_CRCV 0x100 /* Speculative CRC Valid */ 117 #define IXGBE_RXD_STAT_VEXT 0x200 /* 1st VLAN found */ 118 #define IXGBE_RXD_STAT_UDPV 0x400 /* Valid UDP checksum */ 119 #define IXGBE_RXD_STAT_DYNINT 0x800 /* Pkt caused INT via DYNINT */ 120 #define IXGBE_RXD_STAT_TS 0x10000 /* Time Stamp */ 121 #define IXGBE_RXD_STAT_SECP 0x20000 /* Security Processing */ 122 #define IXGBE_RXD_STAT_LB 0x40000 /* Loopback Status */ 123 #define IXGBE_RXD_STAT_ACK 0x8000 /* ACK Packet indication */ 124 #define IXGBE_RXD_ERR_CE 0x01 /* CRC Error */ 125 #define IXGBE_RXD_ERR_LE 0x02 /* Length Error */ 126 #define IXGBE_RXD_ERR_PE 0x08 /* Packet Error */ 127 #define IXGBE_RXD_ERR_OSE 0x10 /* Oversize Error */ 128 #define IXGBE_RXD_ERR_USE 0x20 /* Undersize Error */ 129 #define IXGBE_RXD_ERR_TCPE 0x40 /* TCP/UDP Checksum Error */ 130 #define IXGBE_RXD_ERR_IPE 0x80 /* IP Checksum Error */ 131 #define IXGBE_RXDADV_ERR_MASK 0xFFF00000 /* RDESC.ERRORS mask */ 132 #define IXGBE_RXDADV_ERR_SHIFT 20 /* RDESC.ERRORS shift */ 133 #define IXGBE_RXDADV_ERR_HBO 0x00800000 /*Header Buffer Overflow */ 134 #define IXGBE_RXDADV_ERR_CE 0x01000000 /* CRC Error */ 135 #define IXGBE_RXDADV_ERR_LE 0x02000000 /* Length Error */ 136 #define IXGBE_RXDADV_ERR_PE 0x08000000 /* Packet Error */ 137 #define IXGBE_RXDADV_ERR_OSE 0x10000000 /* Oversize Error */ 138 #define IXGBE_RXDADV_ERR_USE 0x20000000 /* Undersize Error */ 139 #define IXGBE_RXDADV_ERR_TCPE 0x40000000 /* TCP/UDP Checksum Error */ 140 #define IXGBE_RXDADV_ERR_IPE 0x80000000 /* IP Checksum Error */ 141 #define IXGBE_RXD_VLAN_ID_MASK 0x0FFF /* VLAN ID is in lower 12 bits */ 142 #define IXGBE_RXD_PRI_MASK 0xE000 /* Priority is in upper 3 bits */ 143 #define IXGBE_RXD_PRI_SHIFT 13 144 #define IXGBE_RXD_CFI_MASK 0x1000 /* CFI is bit 12 */ 145 #define IXGBE_RXD_CFI_SHIFT 12 146 147 #define IXGBE_RXDADV_STAT_DD IXGBE_RXD_STAT_DD /* Done */ 148 #define IXGBE_RXDADV_STAT_EOP IXGBE_RXD_STAT_EOP /* End of Packet */ 149 #define IXGBE_RXDADV_STAT_FLM IXGBE_RXD_STAT_FLM /* FDir Match */ 150 #define IXGBE_RXDADV_STAT_VP IXGBE_RXD_STAT_VP /* IEEE VLAN Pkt */ 151 #define IXGBE_RXDADV_STAT_MASK 0x000FFFFF /* Stat/NEXTP: bit 0-19 */ 152 #define IXGBE_RXDADV_STAT_FCEOFS 0x00000040 /* FCoE EOF/SOF Stat */ 153 #define IXGBE_RXDADV_STAT_FCSTAT 0x00000030 /* FCoE Pkt Stat */ 154 #define IXGBE_RXDADV_STAT_FCSTAT_NOMTCH 0x00000000 /* 00: No Ctxt Match */ 155 #define IXGBE_RXDADV_STAT_FCSTAT_NODDP 0x00000010 /* 01: Ctxt w/o DDP */ 156 #define IXGBE_RXDADV_STAT_FCSTAT_FCPRSP 0x00000020 /* 10: Recv. FCP_RSP */ 157 #define IXGBE_RXDADV_STAT_FCSTAT_DDP 0x00000030 /* 11: Ctxt w/ DDP */ 158 159 #define IXGBE_RXDADV_RSSTYPE_MASK 0x0000000F 160 #define IXGBE_RXDADV_PKTTYPE_MASK 0x0000FFF0 161 #define IXGBE_RXDADV_PKTTYPE_MASK_EX 0x0001FFF0 162 #define IXGBE_RXDADV_HDRBUFLEN_MASK 0x00007FE0 163 #define IXGBE_RXDADV_RSCCNT_MASK 0x001E0000 164 #define IXGBE_RXDADV_RSCCNT_SHIFT 17 165 #define IXGBE_RXDADV_HDRBUFLEN_SHIFT 5 166 #define IXGBE_RXDADV_SPLITHEADER_EN 0x00001000 167 #define IXGBE_RXDADV_SPH 0x8000 168 169 /* RSS Hash results */ 170 #define IXGBE_RXDADV_RSSTYPE_NONE 0x00000000 171 #define IXGBE_RXDADV_RSSTYPE_IPV4_TCP 0x00000001 172 #define IXGBE_RXDADV_RSSTYPE_IPV4 0x00000002 173 #define IXGBE_RXDADV_RSSTYPE_IPV6_TCP 0x00000003 174 #define IXGBE_RXDADV_RSSTYPE_IPV6_EX 0x00000004 175 #define IXGBE_RXDADV_RSSTYPE_IPV6 0x00000005 176 #define IXGBE_RXDADV_RSSTYPE_IPV6_TCP_EX 0x00000006 177 #define IXGBE_RXDADV_RSSTYPE_IPV4_UDP 0x00000007 178 #define IXGBE_RXDADV_RSSTYPE_IPV6_UDP 0x00000008 179 #define IXGBE_RXDADV_RSSTYPE_IPV6_UDP_EX 0x00000009 180 181 #define IXGBE_RXD_ERR_FRAME_ERR_MASK ( \ 182 IXGBE_RXD_ERR_CE | \ 183 IXGBE_RXD_ERR_LE | \ 184 IXGBE_RXD_ERR_PE | \ 185 IXGBE_RXD_ERR_OSE | \ 186 IXGBE_RXD_ERR_USE) 187 188 #define IXGBE_RXDADV_ERR_FRAME_ERR_MASK ( \ 189 IXGBE_RXDADV_ERR_CE | \ 190 IXGBE_RXDADV_ERR_LE | \ 191 IXGBE_RXDADV_ERR_PE | \ 192 IXGBE_RXDADV_ERR_OSE | \ 193 IXGBE_RXDADV_ERR_USE) 194 195 #define IXGBE_TXD_POPTS_IXSM 0x01 /* Insert IP checksum */ 196 #define IXGBE_TXD_POPTS_TXSM 0x02 /* Insert TCP/UDP checksum */ 197 #define IXGBE_TXD_CMD_EOP 0x01000000 /* End of Packet */ 198 #define IXGBE_TXD_CMD_IFCS 0x02000000 /* Insert FCS (Ethernet CRC) */ 199 #define IXGBE_TXD_CMD_IC 0x04000000 /* Insert Checksum */ 200 #define IXGBE_TXD_CMD_RS 0x08000000 /* Report Status */ 201 #define IXGBE_TXD_CMD_DEXT 0x20000000 /* Descriptor ext (0 = legacy) */ 202 #define IXGBE_TXD_CMD_VLE 0x40000000 /* Add VLAN tag */ 203 #define IXGBE_TXD_STAT_DD 0x00000001 /* Descriptor Done */ 204 #define IXGBE_TXD_CMD (IXGBE_TXD_CMD_EOP | IXGBE_TXD_CMD_RS) 205 206 /* Transmit Descriptor - Advanced */ 207 union ixgbe_adv_tx_desc { 208 struct { 209 __le64 buffer_addr; /* Address of descriptor's data buf */ 210 __le32 cmd_type_len; 211 __le32 olinfo_status; 212 } read; 213 struct { 214 __le64 rsvd; /* Reserved */ 215 __le32 nxtseq_seed; 216 __le32 status; 217 } wb; 218 }; 219 220 /* Receive Descriptor - Advanced */ 221 union ixgbe_adv_rx_desc { 222 struct { 223 __le64 pkt_addr; /* Packet buffer address */ 224 __le64 hdr_addr; /* Header buffer address */ 225 } read; 226 struct { 227 struct { 228 union { 229 __le32 data; 230 struct { 231 __le16 pkt_info; /* RSS, Pkt type */ 232 __le16 hdr_info; /* Splithdr, hdrlen */ 233 } hs_rss; 234 } lo_dword; 235 union { 236 __le32 rss; /* RSS Hash */ 237 struct { 238 __le16 ip_id; /* IP id */ 239 __le16 csum; /* Packet Checksum */ 240 } csum_ip; 241 } hi_dword; 242 } lower; 243 struct { 244 __le32 status_error; /* ext status/error */ 245 __le16 length; /* Packet length */ 246 __le16 vlan; /* VLAN tag */ 247 } upper; 248 } wb; /* writeback */ 249 }; 250 251 /* Context descriptors */ 252 struct ixgbe_adv_tx_context_desc { 253 __le32 vlan_macip_lens; 254 __le32 seqnum_seed; 255 __le32 type_tucmd_mlhl; 256 __le32 mss_l4len_idx; 257 }; 258 259 /* Adv Transmit Descriptor Config Masks */ 260 #define IXGBE_ADVTXD_DTYP_MASK 0x00F00000 /* DTYP mask */ 261 #define IXGBE_ADVTXD_DTYP_CTXT 0x00200000 /* Advanced Context Desc */ 262 #define IXGBE_ADVTXD_DTYP_DATA 0x00300000 /* Advanced Data Descriptor */ 263 #define IXGBE_ADVTXD_DCMD_EOP IXGBE_TXD_CMD_EOP /* End of Packet */ 264 #define IXGBE_ADVTXD_DCMD_IFCS IXGBE_TXD_CMD_IFCS /* Insert FCS */ 265 #define IXGBE_ADVTXD_DCMD_RS IXGBE_TXD_CMD_RS /* Report Status */ 266 #define IXGBE_ADVTXD_DCMD_DEXT IXGBE_TXD_CMD_DEXT /* Desc ext (1=Adv) */ 267 #define IXGBE_ADVTXD_DCMD_VLE IXGBE_TXD_CMD_VLE /* VLAN pkt enable */ 268 #define IXGBE_ADVTXD_DCMD_TSE 0x80000000 /* TCP Seg enable */ 269 #define IXGBE_ADVTXD_STAT_DD IXGBE_TXD_STAT_DD /* Descriptor Done */ 270 #define IXGBE_ADVTXD_TUCMD_IPV4 0x00000400 /* IP Packet Type: 1=IPv4 */ 271 #define IXGBE_ADVTXD_TUCMD_IPV6 0x00000000 /* IP Packet Type: 0=IPv6 */ 272 #define IXGBE_ADVTXD_TUCMD_L4T_UDP 0x00000000 /* L4 Packet TYPE of UDP */ 273 #define IXGBE_ADVTXD_TUCMD_L4T_TCP 0x00000800 /* L4 Packet TYPE of TCP */ 274 #define IXGBE_ADVTXD_TUCMD_L4T_SCTP 0x00001000 /* L4 Packet TYPE of SCTP */ 275 #define IXGBE_ADVTXD_IDX_SHIFT 4 /* Adv desc Index shift */ 276 #define IXGBE_ADVTXD_CC 0x00000080 /* Check Context */ 277 #define IXGBE_ADVTXD_POPTS_SHIFT 8 /* Adv desc POPTS shift */ 278 #define IXGBE_ADVTXD_POPTS_IXSM (IXGBE_TXD_POPTS_IXSM << \ 279 IXGBE_ADVTXD_POPTS_SHIFT) 280 #define IXGBE_ADVTXD_POPTS_TXSM (IXGBE_TXD_POPTS_TXSM << \ 281 IXGBE_ADVTXD_POPTS_SHIFT) 282 #define IXGBE_ADVTXD_PAYLEN_SHIFT 14 /* Adv desc PAYLEN shift */ 283 #define IXGBE_ADVTXD_MACLEN_SHIFT 9 /* Adv ctxt desc mac len shift */ 284 #define IXGBE_ADVTXD_VLAN_SHIFT 16 /* Adv ctxt vlan tag shift */ 285 #define IXGBE_ADVTXD_L4LEN_SHIFT 8 /* Adv ctxt L4LEN shift */ 286 #define IXGBE_ADVTXD_MSS_SHIFT 16 /* Adv ctxt MSS shift */ 287 288 /* Interrupt register bitmasks */ 289 290 #define IXGBE_EITR_CNT_WDIS 0x80000000 291 #define IXGBE_MAX_EITR 0x00000FF8 292 #define IXGBE_MIN_EITR 8 293 294 /* Error Codes */ 295 #define IXGBE_ERR_INVALID_MAC_ADDR -1 296 #define IXGBE_ERR_RESET_FAILED -2 297 #define IXGBE_ERR_INVALID_ARGUMENT -3 298 299 /* Transmit Config masks */ 300 #define IXGBE_TXDCTL_ENABLE 0x02000000 /* Ena specific Tx Queue */ 301 #define IXGBE_TXDCTL_SWFLSH 0x04000000 /* Tx Desc. wr-bk flushing */ 302 #define IXGBE_TXDCTL_WTHRESH_SHIFT 16 /* shift to WTHRESH bits */ 303 304 #define IXGBE_DCA_RXCTRL_DESC_DCA_EN BIT(5) /* Rx Desc enable */ 305 #define IXGBE_DCA_RXCTRL_HEAD_DCA_EN BIT(6) /* Rx Desc header ena */ 306 #define IXGBE_DCA_RXCTRL_DATA_DCA_EN BIT(7) /* Rx Desc payload ena */ 307 #define IXGBE_DCA_RXCTRL_DESC_RRO_EN BIT(9) /* Rx rd Desc Relax Order */ 308 #define IXGBE_DCA_RXCTRL_DATA_WRO_EN BIT(13) /* Rx wr data Relax Order */ 309 #define IXGBE_DCA_RXCTRL_HEAD_WRO_EN BIT(15) /* Rx wr header RO */ 310 311 #define IXGBE_DCA_TXCTRL_DESC_DCA_EN BIT(5) /* DCA Tx Desc enable */ 312 #define IXGBE_DCA_TXCTRL_DESC_RRO_EN BIT(9) /* Tx rd Desc Relax Order */ 313 #define IXGBE_DCA_TXCTRL_DESC_WRO_EN BIT(11) /* Tx Desc writeback RO bit */ 314 #define IXGBE_DCA_TXCTRL_DATA_RRO_EN BIT(13) /* Tx rd data Relax Order */ 315 316 #endif /* _IXGBEVF_DEFINES_H_ */ 317