1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright(c) 2018 Intel Corporation. */ 3 4 #include <linux/bpf_trace.h> 5 #include <net/xdp_sock_drv.h> 6 #include <net/xdp.h> 7 8 #include "ixgbe.h" 9 #include "ixgbe_txrx_common.h" 10 11 struct xsk_buff_pool *ixgbe_xsk_pool(struct ixgbe_adapter *adapter, 12 struct ixgbe_ring *ring) 13 { 14 bool xdp_on = READ_ONCE(adapter->xdp_prog); 15 int qid = ring->ring_idx; 16 17 if (!xdp_on || !test_bit(qid, adapter->af_xdp_zc_qps)) 18 return NULL; 19 20 return xsk_get_pool_from_qid(adapter->netdev, qid); 21 } 22 23 static int ixgbe_xsk_pool_enable(struct ixgbe_adapter *adapter, 24 struct xsk_buff_pool *pool, 25 u16 qid) 26 { 27 struct net_device *netdev = adapter->netdev; 28 bool if_running; 29 int err; 30 31 if (qid >= adapter->num_rx_queues) 32 return -EINVAL; 33 34 if (qid >= netdev->real_num_rx_queues || 35 qid >= netdev->real_num_tx_queues) 36 return -EINVAL; 37 38 err = xsk_pool_dma_map(pool, &adapter->pdev->dev, IXGBE_RX_DMA_ATTR); 39 if (err) 40 return err; 41 42 if_running = netif_running(adapter->netdev) && 43 ixgbe_enabled_xdp_adapter(adapter); 44 45 if (if_running) 46 ixgbe_txrx_ring_disable(adapter, qid); 47 48 set_bit(qid, adapter->af_xdp_zc_qps); 49 50 if (if_running) { 51 ixgbe_txrx_ring_enable(adapter, qid); 52 53 /* Kick start the NAPI context so that receiving will start */ 54 err = ixgbe_xsk_wakeup(adapter->netdev, qid, XDP_WAKEUP_RX); 55 if (err) 56 return err; 57 } 58 59 return 0; 60 } 61 62 static int ixgbe_xsk_pool_disable(struct ixgbe_adapter *adapter, u16 qid) 63 { 64 struct xsk_buff_pool *pool; 65 bool if_running; 66 67 pool = xsk_get_pool_from_qid(adapter->netdev, qid); 68 if (!pool) 69 return -EINVAL; 70 71 if_running = netif_running(adapter->netdev) && 72 ixgbe_enabled_xdp_adapter(adapter); 73 74 if (if_running) 75 ixgbe_txrx_ring_disable(adapter, qid); 76 77 clear_bit(qid, adapter->af_xdp_zc_qps); 78 xsk_pool_dma_unmap(pool, IXGBE_RX_DMA_ATTR); 79 80 if (if_running) 81 ixgbe_txrx_ring_enable(adapter, qid); 82 83 return 0; 84 } 85 86 int ixgbe_xsk_pool_setup(struct ixgbe_adapter *adapter, 87 struct xsk_buff_pool *pool, 88 u16 qid) 89 { 90 return pool ? ixgbe_xsk_pool_enable(adapter, pool, qid) : 91 ixgbe_xsk_pool_disable(adapter, qid); 92 } 93 94 static int ixgbe_run_xdp_zc(struct ixgbe_adapter *adapter, 95 struct ixgbe_ring *rx_ring, 96 struct xdp_buff *xdp) 97 { 98 int err, result = IXGBE_XDP_PASS; 99 struct bpf_prog *xdp_prog; 100 struct xdp_frame *xdpf; 101 u32 act; 102 103 xdp_prog = READ_ONCE(rx_ring->xdp_prog); 104 act = bpf_prog_run_xdp(xdp_prog, xdp); 105 106 if (likely(act == XDP_REDIRECT)) { 107 err = xdp_do_redirect(rx_ring->netdev, xdp, xdp_prog); 108 if (err) 109 goto out_failure; 110 return IXGBE_XDP_REDIR; 111 } 112 113 switch (act) { 114 case XDP_PASS: 115 break; 116 case XDP_TX: 117 xdpf = xdp_convert_buff_to_frame(xdp); 118 if (unlikely(!xdpf)) 119 goto out_failure; 120 result = ixgbe_xmit_xdp_ring(adapter, xdpf); 121 if (result == IXGBE_XDP_CONSUMED) 122 goto out_failure; 123 break; 124 default: 125 bpf_warn_invalid_xdp_action(act); 126 fallthrough; 127 case XDP_ABORTED: 128 out_failure: 129 trace_xdp_exception(rx_ring->netdev, xdp_prog, act); 130 fallthrough; /* handle aborts by dropping packet */ 131 case XDP_DROP: 132 result = IXGBE_XDP_CONSUMED; 133 break; 134 } 135 return result; 136 } 137 138 bool ixgbe_alloc_rx_buffers_zc(struct ixgbe_ring *rx_ring, u16 count) 139 { 140 union ixgbe_adv_rx_desc *rx_desc; 141 struct ixgbe_rx_buffer *bi; 142 u16 i = rx_ring->next_to_use; 143 dma_addr_t dma; 144 bool ok = true; 145 146 /* nothing to do */ 147 if (!count) 148 return true; 149 150 rx_desc = IXGBE_RX_DESC(rx_ring, i); 151 bi = &rx_ring->rx_buffer_info[i]; 152 i -= rx_ring->count; 153 154 do { 155 bi->xdp = xsk_buff_alloc(rx_ring->xsk_pool); 156 if (!bi->xdp) { 157 ok = false; 158 break; 159 } 160 161 dma = xsk_buff_xdp_get_dma(bi->xdp); 162 163 /* Refresh the desc even if buffer_addrs didn't change 164 * because each write-back erases this info. 165 */ 166 rx_desc->read.pkt_addr = cpu_to_le64(dma); 167 168 rx_desc++; 169 bi++; 170 i++; 171 if (unlikely(!i)) { 172 rx_desc = IXGBE_RX_DESC(rx_ring, 0); 173 bi = rx_ring->rx_buffer_info; 174 i -= rx_ring->count; 175 } 176 177 /* clear the length for the next_to_use descriptor */ 178 rx_desc->wb.upper.length = 0; 179 180 count--; 181 } while (count); 182 183 i += rx_ring->count; 184 185 if (rx_ring->next_to_use != i) { 186 rx_ring->next_to_use = i; 187 188 /* Force memory writes to complete before letting h/w 189 * know there are new descriptors to fetch. (Only 190 * applicable for weak-ordered memory model archs, 191 * such as IA-64). 192 */ 193 wmb(); 194 writel(i, rx_ring->tail); 195 } 196 197 return ok; 198 } 199 200 static struct sk_buff *ixgbe_construct_skb_zc(struct ixgbe_ring *rx_ring, 201 struct ixgbe_rx_buffer *bi) 202 { 203 unsigned int metasize = bi->xdp->data - bi->xdp->data_meta; 204 unsigned int datasize = bi->xdp->data_end - bi->xdp->data; 205 struct sk_buff *skb; 206 207 /* allocate a skb to store the frags */ 208 skb = __napi_alloc_skb(&rx_ring->q_vector->napi, 209 bi->xdp->data_end - bi->xdp->data_hard_start, 210 GFP_ATOMIC | __GFP_NOWARN); 211 if (unlikely(!skb)) 212 return NULL; 213 214 skb_reserve(skb, bi->xdp->data - bi->xdp->data_hard_start); 215 memcpy(__skb_put(skb, datasize), bi->xdp->data, datasize); 216 if (metasize) 217 skb_metadata_set(skb, metasize); 218 219 xsk_buff_free(bi->xdp); 220 bi->xdp = NULL; 221 return skb; 222 } 223 224 static void ixgbe_inc_ntc(struct ixgbe_ring *rx_ring) 225 { 226 u32 ntc = rx_ring->next_to_clean + 1; 227 228 ntc = (ntc < rx_ring->count) ? ntc : 0; 229 rx_ring->next_to_clean = ntc; 230 prefetch(IXGBE_RX_DESC(rx_ring, ntc)); 231 } 232 233 int ixgbe_clean_rx_irq_zc(struct ixgbe_q_vector *q_vector, 234 struct ixgbe_ring *rx_ring, 235 const int budget) 236 { 237 unsigned int total_rx_bytes = 0, total_rx_packets = 0; 238 struct ixgbe_adapter *adapter = q_vector->adapter; 239 u16 cleaned_count = ixgbe_desc_unused(rx_ring); 240 unsigned int xdp_res, xdp_xmit = 0; 241 bool failure = false; 242 struct sk_buff *skb; 243 244 while (likely(total_rx_packets < budget)) { 245 union ixgbe_adv_rx_desc *rx_desc; 246 struct ixgbe_rx_buffer *bi; 247 unsigned int size; 248 249 /* return some buffers to hardware, one at a time is too slow */ 250 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) { 251 failure = failure || 252 !ixgbe_alloc_rx_buffers_zc(rx_ring, 253 cleaned_count); 254 cleaned_count = 0; 255 } 256 257 rx_desc = IXGBE_RX_DESC(rx_ring, rx_ring->next_to_clean); 258 size = le16_to_cpu(rx_desc->wb.upper.length); 259 if (!size) 260 break; 261 262 /* This memory barrier is needed to keep us from reading 263 * any other fields out of the rx_desc until we know the 264 * descriptor has been written back 265 */ 266 dma_rmb(); 267 268 bi = &rx_ring->rx_buffer_info[rx_ring->next_to_clean]; 269 270 if (unlikely(!ixgbe_test_staterr(rx_desc, 271 IXGBE_RXD_STAT_EOP))) { 272 struct ixgbe_rx_buffer *next_bi; 273 274 xsk_buff_free(bi->xdp); 275 bi->xdp = NULL; 276 ixgbe_inc_ntc(rx_ring); 277 next_bi = 278 &rx_ring->rx_buffer_info[rx_ring->next_to_clean]; 279 next_bi->discard = true; 280 continue; 281 } 282 283 if (unlikely(bi->discard)) { 284 xsk_buff_free(bi->xdp); 285 bi->xdp = NULL; 286 bi->discard = false; 287 ixgbe_inc_ntc(rx_ring); 288 continue; 289 } 290 291 bi->xdp->data_end = bi->xdp->data + size; 292 xsk_buff_dma_sync_for_cpu(bi->xdp, rx_ring->xsk_pool); 293 xdp_res = ixgbe_run_xdp_zc(adapter, rx_ring, bi->xdp); 294 295 if (xdp_res) { 296 if (xdp_res & (IXGBE_XDP_TX | IXGBE_XDP_REDIR)) 297 xdp_xmit |= xdp_res; 298 else 299 xsk_buff_free(bi->xdp); 300 301 bi->xdp = NULL; 302 total_rx_packets++; 303 total_rx_bytes += size; 304 305 cleaned_count++; 306 ixgbe_inc_ntc(rx_ring); 307 continue; 308 } 309 310 /* XDP_PASS path */ 311 skb = ixgbe_construct_skb_zc(rx_ring, bi); 312 if (!skb) { 313 rx_ring->rx_stats.alloc_rx_buff_failed++; 314 break; 315 } 316 317 cleaned_count++; 318 ixgbe_inc_ntc(rx_ring); 319 320 if (eth_skb_pad(skb)) 321 continue; 322 323 total_rx_bytes += skb->len; 324 total_rx_packets++; 325 326 ixgbe_process_skb_fields(rx_ring, rx_desc, skb); 327 ixgbe_rx_skb(q_vector, skb); 328 } 329 330 if (xdp_xmit & IXGBE_XDP_REDIR) 331 xdp_do_flush_map(); 332 333 if (xdp_xmit & IXGBE_XDP_TX) { 334 struct ixgbe_ring *ring = adapter->xdp_ring[smp_processor_id()]; 335 336 /* Force memory writes to complete before letting h/w 337 * know there are new descriptors to fetch. 338 */ 339 wmb(); 340 writel(ring->next_to_use, ring->tail); 341 } 342 343 u64_stats_update_begin(&rx_ring->syncp); 344 rx_ring->stats.packets += total_rx_packets; 345 rx_ring->stats.bytes += total_rx_bytes; 346 u64_stats_update_end(&rx_ring->syncp); 347 q_vector->rx.total_packets += total_rx_packets; 348 q_vector->rx.total_bytes += total_rx_bytes; 349 350 if (xsk_uses_need_wakeup(rx_ring->xsk_pool)) { 351 if (failure || rx_ring->next_to_clean == rx_ring->next_to_use) 352 xsk_set_rx_need_wakeup(rx_ring->xsk_pool); 353 else 354 xsk_clear_rx_need_wakeup(rx_ring->xsk_pool); 355 356 return (int)total_rx_packets; 357 } 358 return failure ? budget : (int)total_rx_packets; 359 } 360 361 void ixgbe_xsk_clean_rx_ring(struct ixgbe_ring *rx_ring) 362 { 363 struct ixgbe_rx_buffer *bi; 364 u16 i; 365 366 for (i = 0; i < rx_ring->count; i++) { 367 bi = &rx_ring->rx_buffer_info[i]; 368 369 if (!bi->xdp) 370 continue; 371 372 xsk_buff_free(bi->xdp); 373 bi->xdp = NULL; 374 } 375 } 376 377 static bool ixgbe_xmit_zc(struct ixgbe_ring *xdp_ring, unsigned int budget) 378 { 379 struct xsk_buff_pool *pool = xdp_ring->xsk_pool; 380 union ixgbe_adv_tx_desc *tx_desc = NULL; 381 struct ixgbe_tx_buffer *tx_bi; 382 bool work_done = true; 383 struct xdp_desc desc; 384 dma_addr_t dma; 385 u32 cmd_type; 386 387 while (budget-- > 0) { 388 if (unlikely(!ixgbe_desc_unused(xdp_ring)) || 389 !netif_carrier_ok(xdp_ring->netdev)) { 390 work_done = false; 391 break; 392 } 393 394 if (!xsk_tx_peek_desc(pool, &desc)) 395 break; 396 397 dma = xsk_buff_raw_get_dma(pool, desc.addr); 398 xsk_buff_raw_dma_sync_for_device(pool, dma, desc.len); 399 400 tx_bi = &xdp_ring->tx_buffer_info[xdp_ring->next_to_use]; 401 tx_bi->bytecount = desc.len; 402 tx_bi->xdpf = NULL; 403 tx_bi->gso_segs = 1; 404 405 tx_desc = IXGBE_TX_DESC(xdp_ring, xdp_ring->next_to_use); 406 tx_desc->read.buffer_addr = cpu_to_le64(dma); 407 408 /* put descriptor type bits */ 409 cmd_type = IXGBE_ADVTXD_DTYP_DATA | 410 IXGBE_ADVTXD_DCMD_DEXT | 411 IXGBE_ADVTXD_DCMD_IFCS; 412 cmd_type |= desc.len | IXGBE_TXD_CMD; 413 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type); 414 tx_desc->read.olinfo_status = 415 cpu_to_le32(desc.len << IXGBE_ADVTXD_PAYLEN_SHIFT); 416 417 xdp_ring->next_to_use++; 418 if (xdp_ring->next_to_use == xdp_ring->count) 419 xdp_ring->next_to_use = 0; 420 } 421 422 if (tx_desc) { 423 ixgbe_xdp_ring_update_tail(xdp_ring); 424 xsk_tx_release(pool); 425 } 426 427 return !!budget && work_done; 428 } 429 430 static void ixgbe_clean_xdp_tx_buffer(struct ixgbe_ring *tx_ring, 431 struct ixgbe_tx_buffer *tx_bi) 432 { 433 xdp_return_frame(tx_bi->xdpf); 434 dma_unmap_single(tx_ring->dev, 435 dma_unmap_addr(tx_bi, dma), 436 dma_unmap_len(tx_bi, len), DMA_TO_DEVICE); 437 dma_unmap_len_set(tx_bi, len, 0); 438 } 439 440 bool ixgbe_clean_xdp_tx_irq(struct ixgbe_q_vector *q_vector, 441 struct ixgbe_ring *tx_ring, int napi_budget) 442 { 443 u16 ntc = tx_ring->next_to_clean, ntu = tx_ring->next_to_use; 444 unsigned int total_packets = 0, total_bytes = 0; 445 struct xsk_buff_pool *pool = tx_ring->xsk_pool; 446 union ixgbe_adv_tx_desc *tx_desc; 447 struct ixgbe_tx_buffer *tx_bi; 448 u32 xsk_frames = 0; 449 450 tx_bi = &tx_ring->tx_buffer_info[ntc]; 451 tx_desc = IXGBE_TX_DESC(tx_ring, ntc); 452 453 while (ntc != ntu) { 454 if (!(tx_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD))) 455 break; 456 457 total_bytes += tx_bi->bytecount; 458 total_packets += tx_bi->gso_segs; 459 460 if (tx_bi->xdpf) 461 ixgbe_clean_xdp_tx_buffer(tx_ring, tx_bi); 462 else 463 xsk_frames++; 464 465 tx_bi->xdpf = NULL; 466 467 tx_bi++; 468 tx_desc++; 469 ntc++; 470 if (unlikely(ntc == tx_ring->count)) { 471 ntc = 0; 472 tx_bi = tx_ring->tx_buffer_info; 473 tx_desc = IXGBE_TX_DESC(tx_ring, 0); 474 } 475 476 /* issue prefetch for next Tx descriptor */ 477 prefetch(tx_desc); 478 } 479 480 tx_ring->next_to_clean = ntc; 481 482 u64_stats_update_begin(&tx_ring->syncp); 483 tx_ring->stats.bytes += total_bytes; 484 tx_ring->stats.packets += total_packets; 485 u64_stats_update_end(&tx_ring->syncp); 486 q_vector->tx.total_bytes += total_bytes; 487 q_vector->tx.total_packets += total_packets; 488 489 if (xsk_frames) 490 xsk_tx_completed(pool, xsk_frames); 491 492 if (xsk_uses_need_wakeup(pool)) 493 xsk_set_tx_need_wakeup(pool); 494 495 return ixgbe_xmit_zc(tx_ring, q_vector->tx.work_limit); 496 } 497 498 int ixgbe_xsk_wakeup(struct net_device *dev, u32 qid, u32 flags) 499 { 500 struct ixgbe_adapter *adapter = netdev_priv(dev); 501 struct ixgbe_ring *ring; 502 503 if (test_bit(__IXGBE_DOWN, &adapter->state)) 504 return -ENETDOWN; 505 506 if (!READ_ONCE(adapter->xdp_prog)) 507 return -ENXIO; 508 509 if (qid >= adapter->num_xdp_queues) 510 return -ENXIO; 511 512 ring = adapter->xdp_ring[qid]; 513 514 if (test_bit(__IXGBE_TX_DISABLED, &ring->state)) 515 return -ENETDOWN; 516 517 if (!ring->xsk_pool) 518 return -ENXIO; 519 520 if (!napi_if_scheduled_mark_missed(&ring->q_vector->napi)) { 521 u64 eics = BIT_ULL(ring->q_vector->v_idx); 522 523 ixgbe_irq_rearm_queues(adapter, eics); 524 } 525 526 return 0; 527 } 528 529 void ixgbe_xsk_clean_tx_ring(struct ixgbe_ring *tx_ring) 530 { 531 u16 ntc = tx_ring->next_to_clean, ntu = tx_ring->next_to_use; 532 struct xsk_buff_pool *pool = tx_ring->xsk_pool; 533 struct ixgbe_tx_buffer *tx_bi; 534 u32 xsk_frames = 0; 535 536 while (ntc != ntu) { 537 tx_bi = &tx_ring->tx_buffer_info[ntc]; 538 539 if (tx_bi->xdpf) 540 ixgbe_clean_xdp_tx_buffer(tx_ring, tx_bi); 541 else 542 xsk_frames++; 543 544 tx_bi->xdpf = NULL; 545 546 ntc++; 547 if (ntc == tx_ring->count) 548 ntc = 0; 549 } 550 551 if (xsk_frames) 552 xsk_tx_completed(pool, xsk_frames); 553 } 554