1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright(c) 1999 - 2018 Intel Corporation. */ 3 4 #include "ixgbe_x540.h" 5 #include "ixgbe_type.h" 6 #include "ixgbe_common.h" 7 #include "ixgbe_phy.h" 8 9 static s32 ixgbe_setup_kr_speed_x550em(struct ixgbe_hw *, ixgbe_link_speed); 10 static s32 ixgbe_setup_fc_x550em(struct ixgbe_hw *); 11 static void ixgbe_fc_autoneg_fiber_x550em_a(struct ixgbe_hw *); 12 static void ixgbe_fc_autoneg_backplane_x550em_a(struct ixgbe_hw *); 13 static s32 ixgbe_setup_fc_backplane_x550em_a(struct ixgbe_hw *); 14 15 static s32 ixgbe_get_invariants_X550_x(struct ixgbe_hw *hw) 16 { 17 struct ixgbe_mac_info *mac = &hw->mac; 18 struct ixgbe_phy_info *phy = &hw->phy; 19 struct ixgbe_link_info *link = &hw->link; 20 21 /* Start with X540 invariants, since so simular */ 22 ixgbe_get_invariants_X540(hw); 23 24 if (mac->ops.get_media_type(hw) != ixgbe_media_type_copper) 25 phy->ops.set_phy_power = NULL; 26 27 link->addr = IXGBE_CS4227; 28 29 return 0; 30 } 31 32 static s32 ixgbe_get_invariants_X550_x_fw(struct ixgbe_hw *hw) 33 { 34 struct ixgbe_phy_info *phy = &hw->phy; 35 36 /* Start with X540 invariants, since so similar */ 37 ixgbe_get_invariants_X540(hw); 38 39 phy->ops.set_phy_power = NULL; 40 41 return 0; 42 } 43 44 static s32 ixgbe_get_invariants_X550_a(struct ixgbe_hw *hw) 45 { 46 struct ixgbe_mac_info *mac = &hw->mac; 47 struct ixgbe_phy_info *phy = &hw->phy; 48 49 /* Start with X540 invariants, since so simular */ 50 ixgbe_get_invariants_X540(hw); 51 52 if (mac->ops.get_media_type(hw) != ixgbe_media_type_copper) 53 phy->ops.set_phy_power = NULL; 54 55 return 0; 56 } 57 58 static s32 ixgbe_get_invariants_X550_a_fw(struct ixgbe_hw *hw) 59 { 60 struct ixgbe_phy_info *phy = &hw->phy; 61 62 /* Start with X540 invariants, since so similar */ 63 ixgbe_get_invariants_X540(hw); 64 65 phy->ops.set_phy_power = NULL; 66 67 return 0; 68 } 69 70 /** ixgbe_setup_mux_ctl - Setup ESDP register for I2C mux control 71 * @hw: pointer to hardware structure 72 **/ 73 static void ixgbe_setup_mux_ctl(struct ixgbe_hw *hw) 74 { 75 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); 76 77 if (hw->bus.lan_id) { 78 esdp &= ~(IXGBE_ESDP_SDP1_NATIVE | IXGBE_ESDP_SDP1); 79 esdp |= IXGBE_ESDP_SDP1_DIR; 80 } 81 esdp &= ~(IXGBE_ESDP_SDP0_NATIVE | IXGBE_ESDP_SDP0_DIR); 82 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp); 83 IXGBE_WRITE_FLUSH(hw); 84 } 85 86 /** 87 * ixgbe_read_cs4227 - Read CS4227 register 88 * @hw: pointer to hardware structure 89 * @reg: register number to write 90 * @value: pointer to receive value read 91 * 92 * Returns status code 93 */ 94 static s32 ixgbe_read_cs4227(struct ixgbe_hw *hw, u16 reg, u16 *value) 95 { 96 return hw->link.ops.read_link_unlocked(hw, hw->link.addr, reg, value); 97 } 98 99 /** 100 * ixgbe_write_cs4227 - Write CS4227 register 101 * @hw: pointer to hardware structure 102 * @reg: register number to write 103 * @value: value to write to register 104 * 105 * Returns status code 106 */ 107 static s32 ixgbe_write_cs4227(struct ixgbe_hw *hw, u16 reg, u16 value) 108 { 109 return hw->link.ops.write_link_unlocked(hw, hw->link.addr, reg, value); 110 } 111 112 /** 113 * ixgbe_read_pe - Read register from port expander 114 * @hw: pointer to hardware structure 115 * @reg: register number to read 116 * @value: pointer to receive read value 117 * 118 * Returns status code 119 */ 120 static s32 ixgbe_read_pe(struct ixgbe_hw *hw, u8 reg, u8 *value) 121 { 122 s32 status; 123 124 status = ixgbe_read_i2c_byte_generic_unlocked(hw, reg, IXGBE_PE, value); 125 if (status) 126 hw_err(hw, "port expander access failed with %d\n", status); 127 return status; 128 } 129 130 /** 131 * ixgbe_write_pe - Write register to port expander 132 * @hw: pointer to hardware structure 133 * @reg: register number to write 134 * @value: value to write 135 * 136 * Returns status code 137 */ 138 static s32 ixgbe_write_pe(struct ixgbe_hw *hw, u8 reg, u8 value) 139 { 140 s32 status; 141 142 status = ixgbe_write_i2c_byte_generic_unlocked(hw, reg, IXGBE_PE, 143 value); 144 if (status) 145 hw_err(hw, "port expander access failed with %d\n", status); 146 return status; 147 } 148 149 /** 150 * ixgbe_reset_cs4227 - Reset CS4227 using port expander 151 * @hw: pointer to hardware structure 152 * 153 * This function assumes that the caller has acquired the proper semaphore. 154 * Returns error code 155 */ 156 static s32 ixgbe_reset_cs4227(struct ixgbe_hw *hw) 157 { 158 s32 status; 159 u32 retry; 160 u16 value; 161 u8 reg; 162 163 /* Trigger hard reset. */ 164 status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, ®); 165 if (status) 166 return status; 167 reg |= IXGBE_PE_BIT1; 168 status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg); 169 if (status) 170 return status; 171 172 status = ixgbe_read_pe(hw, IXGBE_PE_CONFIG, ®); 173 if (status) 174 return status; 175 reg &= ~IXGBE_PE_BIT1; 176 status = ixgbe_write_pe(hw, IXGBE_PE_CONFIG, reg); 177 if (status) 178 return status; 179 180 status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, ®); 181 if (status) 182 return status; 183 reg &= ~IXGBE_PE_BIT1; 184 status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg); 185 if (status) 186 return status; 187 188 usleep_range(IXGBE_CS4227_RESET_HOLD, IXGBE_CS4227_RESET_HOLD + 100); 189 190 status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, ®); 191 if (status) 192 return status; 193 reg |= IXGBE_PE_BIT1; 194 status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg); 195 if (status) 196 return status; 197 198 /* Wait for the reset to complete. */ 199 msleep(IXGBE_CS4227_RESET_DELAY); 200 for (retry = 0; retry < IXGBE_CS4227_RETRIES; retry++) { 201 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_EFUSE_STATUS, 202 &value); 203 if (!status && value == IXGBE_CS4227_EEPROM_LOAD_OK) 204 break; 205 msleep(IXGBE_CS4227_CHECK_DELAY); 206 } 207 if (retry == IXGBE_CS4227_RETRIES) { 208 hw_err(hw, "CS4227 reset did not complete\n"); 209 return -EIO; 210 } 211 212 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_EEPROM_STATUS, &value); 213 if (status || !(value & IXGBE_CS4227_EEPROM_LOAD_OK)) { 214 hw_err(hw, "CS4227 EEPROM did not load successfully\n"); 215 return -EIO; 216 } 217 218 return 0; 219 } 220 221 /** 222 * ixgbe_check_cs4227 - Check CS4227 and reset as needed 223 * @hw: pointer to hardware structure 224 */ 225 static void ixgbe_check_cs4227(struct ixgbe_hw *hw) 226 { 227 u32 swfw_mask = hw->phy.phy_semaphore_mask; 228 s32 status; 229 u16 value; 230 u8 retry; 231 232 for (retry = 0; retry < IXGBE_CS4227_RETRIES; retry++) { 233 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask); 234 if (status) { 235 hw_err(hw, "semaphore failed with %d\n", status); 236 msleep(IXGBE_CS4227_CHECK_DELAY); 237 continue; 238 } 239 240 /* Get status of reset flow. */ 241 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_SCRATCH, &value); 242 if (!status && value == IXGBE_CS4227_RESET_COMPLETE) 243 goto out; 244 245 if (status || value != IXGBE_CS4227_RESET_PENDING) 246 break; 247 248 /* Reset is pending. Wait and check again. */ 249 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 250 msleep(IXGBE_CS4227_CHECK_DELAY); 251 } 252 /* If still pending, assume other instance failed. */ 253 if (retry == IXGBE_CS4227_RETRIES) { 254 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask); 255 if (status) { 256 hw_err(hw, "semaphore failed with %d\n", status); 257 return; 258 } 259 } 260 261 /* Reset the CS4227. */ 262 status = ixgbe_reset_cs4227(hw); 263 if (status) { 264 hw_err(hw, "CS4227 reset failed: %d", status); 265 goto out; 266 } 267 268 /* Reset takes so long, temporarily release semaphore in case the 269 * other driver instance is waiting for the reset indication. 270 */ 271 ixgbe_write_cs4227(hw, IXGBE_CS4227_SCRATCH, 272 IXGBE_CS4227_RESET_PENDING); 273 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 274 usleep_range(10000, 12000); 275 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask); 276 if (status) { 277 hw_err(hw, "semaphore failed with %d", status); 278 return; 279 } 280 281 /* Record completion for next time. */ 282 status = ixgbe_write_cs4227(hw, IXGBE_CS4227_SCRATCH, 283 IXGBE_CS4227_RESET_COMPLETE); 284 285 out: 286 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 287 msleep(hw->eeprom.semaphore_delay); 288 } 289 290 /** ixgbe_identify_phy_x550em - Get PHY type based on device id 291 * @hw: pointer to hardware structure 292 * 293 * Returns error code 294 */ 295 static s32 ixgbe_identify_phy_x550em(struct ixgbe_hw *hw) 296 { 297 switch (hw->device_id) { 298 case IXGBE_DEV_ID_X550EM_A_SFP: 299 if (hw->bus.lan_id) 300 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY1_SM; 301 else 302 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY0_SM; 303 return ixgbe_identify_module_generic(hw); 304 case IXGBE_DEV_ID_X550EM_X_SFP: 305 /* set up for CS4227 usage */ 306 hw->phy.phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM; 307 ixgbe_setup_mux_ctl(hw); 308 ixgbe_check_cs4227(hw); 309 fallthrough; 310 case IXGBE_DEV_ID_X550EM_A_SFP_N: 311 return ixgbe_identify_module_generic(hw); 312 case IXGBE_DEV_ID_X550EM_X_KX4: 313 hw->phy.type = ixgbe_phy_x550em_kx4; 314 break; 315 case IXGBE_DEV_ID_X550EM_X_XFI: 316 hw->phy.type = ixgbe_phy_x550em_xfi; 317 break; 318 case IXGBE_DEV_ID_X550EM_X_KR: 319 case IXGBE_DEV_ID_X550EM_A_KR: 320 case IXGBE_DEV_ID_X550EM_A_KR_L: 321 hw->phy.type = ixgbe_phy_x550em_kr; 322 break; 323 case IXGBE_DEV_ID_X550EM_A_10G_T: 324 if (hw->bus.lan_id) 325 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY1_SM; 326 else 327 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY0_SM; 328 fallthrough; 329 case IXGBE_DEV_ID_X550EM_X_10G_T: 330 return ixgbe_identify_phy_generic(hw); 331 case IXGBE_DEV_ID_X550EM_X_1G_T: 332 hw->phy.type = ixgbe_phy_ext_1g_t; 333 break; 334 case IXGBE_DEV_ID_X550EM_A_1G_T: 335 case IXGBE_DEV_ID_X550EM_A_1G_T_L: 336 hw->phy.type = ixgbe_phy_fw; 337 hw->phy.ops.read_reg = NULL; 338 hw->phy.ops.write_reg = NULL; 339 if (hw->bus.lan_id) 340 hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY1_SM; 341 else 342 hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY0_SM; 343 break; 344 default: 345 break; 346 } 347 return 0; 348 } 349 350 static s32 ixgbe_read_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr, 351 u32 device_type, u16 *phy_data) 352 { 353 return -EOPNOTSUPP; 354 } 355 356 static s32 ixgbe_write_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr, 357 u32 device_type, u16 phy_data) 358 { 359 return -EOPNOTSUPP; 360 } 361 362 /** 363 * ixgbe_read_i2c_combined_generic - Perform I2C read combined operation 364 * @hw: pointer to the hardware structure 365 * @addr: I2C bus address to read from 366 * @reg: I2C device register to read from 367 * @val: pointer to location to receive read value 368 * 369 * Returns an error code on error. 370 **/ 371 static s32 ixgbe_read_i2c_combined_generic(struct ixgbe_hw *hw, u8 addr, 372 u16 reg, u16 *val) 373 { 374 return ixgbe_read_i2c_combined_generic_int(hw, addr, reg, val, true); 375 } 376 377 /** 378 * ixgbe_read_i2c_combined_generic_unlocked - Do I2C read combined operation 379 * @hw: pointer to the hardware structure 380 * @addr: I2C bus address to read from 381 * @reg: I2C device register to read from 382 * @val: pointer to location to receive read value 383 * 384 * Returns an error code on error. 385 **/ 386 static s32 387 ixgbe_read_i2c_combined_generic_unlocked(struct ixgbe_hw *hw, u8 addr, 388 u16 reg, u16 *val) 389 { 390 return ixgbe_read_i2c_combined_generic_int(hw, addr, reg, val, false); 391 } 392 393 /** 394 * ixgbe_write_i2c_combined_generic - Perform I2C write combined operation 395 * @hw: pointer to the hardware structure 396 * @addr: I2C bus address to write to 397 * @reg: I2C device register to write to 398 * @val: value to write 399 * 400 * Returns an error code on error. 401 **/ 402 static s32 ixgbe_write_i2c_combined_generic(struct ixgbe_hw *hw, 403 u8 addr, u16 reg, u16 val) 404 { 405 return ixgbe_write_i2c_combined_generic_int(hw, addr, reg, val, true); 406 } 407 408 /** 409 * ixgbe_write_i2c_combined_generic_unlocked - Do I2C write combined operation 410 * @hw: pointer to the hardware structure 411 * @addr: I2C bus address to write to 412 * @reg: I2C device register to write to 413 * @val: value to write 414 * 415 * Returns an error code on error. 416 **/ 417 static s32 418 ixgbe_write_i2c_combined_generic_unlocked(struct ixgbe_hw *hw, 419 u8 addr, u16 reg, u16 val) 420 { 421 return ixgbe_write_i2c_combined_generic_int(hw, addr, reg, val, false); 422 } 423 424 /** 425 * ixgbe_fw_phy_activity - Perform an activity on a PHY 426 * @hw: pointer to hardware structure 427 * @activity: activity to perform 428 * @data: Pointer to 4 32-bit words of data 429 */ 430 s32 ixgbe_fw_phy_activity(struct ixgbe_hw *hw, u16 activity, 431 u32 (*data)[FW_PHY_ACT_DATA_COUNT]) 432 { 433 union { 434 struct ixgbe_hic_phy_activity_req cmd; 435 struct ixgbe_hic_phy_activity_resp rsp; 436 } hic; 437 u16 retries = FW_PHY_ACT_RETRIES; 438 s32 rc; 439 u32 i; 440 441 do { 442 memset(&hic, 0, sizeof(hic)); 443 hic.cmd.hdr.cmd = FW_PHY_ACT_REQ_CMD; 444 hic.cmd.hdr.buf_len = FW_PHY_ACT_REQ_LEN; 445 hic.cmd.hdr.checksum = FW_DEFAULT_CHECKSUM; 446 hic.cmd.port_number = hw->bus.lan_id; 447 hic.cmd.activity_id = cpu_to_le16(activity); 448 for (i = 0; i < ARRAY_SIZE(hic.cmd.data); ++i) 449 hic.cmd.data[i] = cpu_to_be32((*data)[i]); 450 451 rc = ixgbe_host_interface_command(hw, &hic.cmd, sizeof(hic.cmd), 452 IXGBE_HI_COMMAND_TIMEOUT, 453 true); 454 if (rc) 455 return rc; 456 if (hic.rsp.hdr.cmd_or_resp.ret_status == 457 FW_CEM_RESP_STATUS_SUCCESS) { 458 for (i = 0; i < FW_PHY_ACT_DATA_COUNT; ++i) 459 (*data)[i] = be32_to_cpu(hic.rsp.data[i]); 460 return 0; 461 } 462 usleep_range(20, 30); 463 --retries; 464 } while (retries > 0); 465 466 return -EIO; 467 } 468 469 static const struct { 470 u16 fw_speed; 471 ixgbe_link_speed phy_speed; 472 } ixgbe_fw_map[] = { 473 { FW_PHY_ACT_LINK_SPEED_10, IXGBE_LINK_SPEED_10_FULL }, 474 { FW_PHY_ACT_LINK_SPEED_100, IXGBE_LINK_SPEED_100_FULL }, 475 { FW_PHY_ACT_LINK_SPEED_1G, IXGBE_LINK_SPEED_1GB_FULL }, 476 { FW_PHY_ACT_LINK_SPEED_2_5G, IXGBE_LINK_SPEED_2_5GB_FULL }, 477 { FW_PHY_ACT_LINK_SPEED_5G, IXGBE_LINK_SPEED_5GB_FULL }, 478 { FW_PHY_ACT_LINK_SPEED_10G, IXGBE_LINK_SPEED_10GB_FULL }, 479 }; 480 481 /** 482 * ixgbe_get_phy_id_fw - Get the phy ID via firmware command 483 * @hw: pointer to hardware structure 484 * 485 * Returns error code 486 */ 487 static s32 ixgbe_get_phy_id_fw(struct ixgbe_hw *hw) 488 { 489 u32 info[FW_PHY_ACT_DATA_COUNT] = { 0 }; 490 u16 phy_speeds; 491 u16 phy_id_lo; 492 s32 rc; 493 u16 i; 494 495 if (hw->phy.id) 496 return 0; 497 498 rc = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_GET_PHY_INFO, &info); 499 if (rc) 500 return rc; 501 502 hw->phy.speeds_supported = 0; 503 phy_speeds = info[0] & FW_PHY_INFO_SPEED_MASK; 504 for (i = 0; i < ARRAY_SIZE(ixgbe_fw_map); ++i) { 505 if (phy_speeds & ixgbe_fw_map[i].fw_speed) 506 hw->phy.speeds_supported |= ixgbe_fw_map[i].phy_speed; 507 } 508 509 hw->phy.id = info[0] & FW_PHY_INFO_ID_HI_MASK; 510 phy_id_lo = info[1] & FW_PHY_INFO_ID_LO_MASK; 511 hw->phy.id |= phy_id_lo & IXGBE_PHY_REVISION_MASK; 512 hw->phy.revision = phy_id_lo & ~IXGBE_PHY_REVISION_MASK; 513 if (!hw->phy.id || hw->phy.id == IXGBE_PHY_REVISION_MASK) 514 return -EFAULT; 515 516 hw->phy.autoneg_advertised = hw->phy.speeds_supported; 517 hw->phy.eee_speeds_supported = IXGBE_LINK_SPEED_100_FULL | 518 IXGBE_LINK_SPEED_1GB_FULL; 519 hw->phy.eee_speeds_advertised = hw->phy.eee_speeds_supported; 520 return 0; 521 } 522 523 /** 524 * ixgbe_identify_phy_fw - Get PHY type based on firmware command 525 * @hw: pointer to hardware structure 526 * 527 * Returns error code 528 */ 529 static s32 ixgbe_identify_phy_fw(struct ixgbe_hw *hw) 530 { 531 if (hw->bus.lan_id) 532 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY1_SM; 533 else 534 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY0_SM; 535 536 hw->phy.type = ixgbe_phy_fw; 537 hw->phy.ops.read_reg = NULL; 538 hw->phy.ops.write_reg = NULL; 539 return ixgbe_get_phy_id_fw(hw); 540 } 541 542 /** 543 * ixgbe_shutdown_fw_phy - Shutdown a firmware-controlled PHY 544 * @hw: pointer to hardware structure 545 * 546 * Returns error code 547 */ 548 static s32 ixgbe_shutdown_fw_phy(struct ixgbe_hw *hw) 549 { 550 u32 setup[FW_PHY_ACT_DATA_COUNT] = { 0 }; 551 552 setup[0] = FW_PHY_ACT_FORCE_LINK_DOWN_OFF; 553 return ixgbe_fw_phy_activity(hw, FW_PHY_ACT_FORCE_LINK_DOWN, &setup); 554 } 555 556 /** 557 * ixgbe_setup_fw_link - Setup firmware-controlled PHYs 558 * @hw: pointer to hardware structure 559 */ 560 static s32 ixgbe_setup_fw_link(struct ixgbe_hw *hw) 561 { 562 u32 setup[FW_PHY_ACT_DATA_COUNT] = { 0 }; 563 s32 rc; 564 u16 i; 565 566 if (hw->phy.reset_disable || ixgbe_check_reset_blocked(hw)) 567 return 0; 568 569 if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) { 570 hw_err(hw, "rx_pause not valid in strict IEEE mode\n"); 571 return -EINVAL; 572 } 573 574 switch (hw->fc.requested_mode) { 575 case ixgbe_fc_full: 576 setup[0] |= FW_PHY_ACT_SETUP_LINK_PAUSE_RXTX << 577 FW_PHY_ACT_SETUP_LINK_PAUSE_SHIFT; 578 break; 579 case ixgbe_fc_rx_pause: 580 setup[0] |= FW_PHY_ACT_SETUP_LINK_PAUSE_RX << 581 FW_PHY_ACT_SETUP_LINK_PAUSE_SHIFT; 582 break; 583 case ixgbe_fc_tx_pause: 584 setup[0] |= FW_PHY_ACT_SETUP_LINK_PAUSE_TX << 585 FW_PHY_ACT_SETUP_LINK_PAUSE_SHIFT; 586 break; 587 default: 588 break; 589 } 590 591 for (i = 0; i < ARRAY_SIZE(ixgbe_fw_map); ++i) { 592 if (hw->phy.autoneg_advertised & ixgbe_fw_map[i].phy_speed) 593 setup[0] |= ixgbe_fw_map[i].fw_speed; 594 } 595 setup[0] |= FW_PHY_ACT_SETUP_LINK_HP | FW_PHY_ACT_SETUP_LINK_AN; 596 597 if (hw->phy.eee_speeds_advertised) 598 setup[0] |= FW_PHY_ACT_SETUP_LINK_EEE; 599 600 rc = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_SETUP_LINK, &setup); 601 if (rc) 602 return rc; 603 604 if (setup[0] == FW_PHY_ACT_SETUP_LINK_RSP_DOWN) 605 return -EIO; 606 607 return 0; 608 } 609 610 /** 611 * ixgbe_fc_autoneg_fw - Set up flow control for FW-controlled PHYs 612 * @hw: pointer to hardware structure 613 * 614 * Called at init time to set up flow control. 615 */ 616 static s32 ixgbe_fc_autoneg_fw(struct ixgbe_hw *hw) 617 { 618 if (hw->fc.requested_mode == ixgbe_fc_default) 619 hw->fc.requested_mode = ixgbe_fc_full; 620 621 return ixgbe_setup_fw_link(hw); 622 } 623 624 /** ixgbe_init_eeprom_params_X550 - Initialize EEPROM params 625 * @hw: pointer to hardware structure 626 * 627 * Initializes the EEPROM parameters ixgbe_eeprom_info within the 628 * ixgbe_hw struct in order to set up EEPROM access. 629 **/ 630 static s32 ixgbe_init_eeprom_params_X550(struct ixgbe_hw *hw) 631 { 632 struct ixgbe_eeprom_info *eeprom = &hw->eeprom; 633 634 if (eeprom->type == ixgbe_eeprom_uninitialized) { 635 u16 eeprom_size; 636 u32 eec; 637 638 eeprom->semaphore_delay = 10; 639 eeprom->type = ixgbe_flash; 640 641 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw)); 642 eeprom_size = FIELD_GET(IXGBE_EEC_SIZE, eec); 643 eeprom->word_size = BIT(eeprom_size + 644 IXGBE_EEPROM_WORD_SIZE_SHIFT); 645 646 hw_dbg(hw, "Eeprom params: type = %d, size = %d\n", 647 eeprom->type, eeprom->word_size); 648 } 649 650 return 0; 651 } 652 653 /** 654 * ixgbe_iosf_wait - Wait for IOSF command completion 655 * @hw: pointer to hardware structure 656 * @ctrl: pointer to location to receive final IOSF control value 657 * 658 * Return: failing status on timeout 659 * 660 * Note: ctrl can be NULL if the IOSF control register value is not needed 661 */ 662 static s32 ixgbe_iosf_wait(struct ixgbe_hw *hw, u32 *ctrl) 663 { 664 u32 i, command; 665 666 /* Check every 10 usec to see if the address cycle completed. 667 * The SB IOSF BUSY bit will clear when the operation is 668 * complete. 669 */ 670 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { 671 command = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL); 672 if (!(command & IXGBE_SB_IOSF_CTRL_BUSY)) 673 break; 674 udelay(10); 675 } 676 if (ctrl) 677 *ctrl = command; 678 if (i == IXGBE_MDIO_COMMAND_TIMEOUT) { 679 hw_dbg(hw, "IOSF wait timed out\n"); 680 return -EIO; 681 } 682 683 return 0; 684 } 685 686 /** ixgbe_read_iosf_sb_reg_x550 - Writes a value to specified register of the 687 * IOSF device 688 * @hw: pointer to hardware structure 689 * @reg_addr: 32 bit PHY register to write 690 * @device_type: 3 bit device type 691 * @phy_data: Pointer to read data from the register 692 **/ 693 static s32 ixgbe_read_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr, 694 u32 device_type, u32 *data) 695 { 696 u32 gssr = IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_PHY0_SM; 697 u32 command, error; 698 s32 ret; 699 700 ret = hw->mac.ops.acquire_swfw_sync(hw, gssr); 701 if (ret) 702 return ret; 703 704 ret = ixgbe_iosf_wait(hw, NULL); 705 if (ret) 706 goto out; 707 708 command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) | 709 (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT)); 710 711 /* Write IOSF control register */ 712 IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command); 713 714 ret = ixgbe_iosf_wait(hw, &command); 715 716 if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) { 717 error = FIELD_GET(IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK, command); 718 hw_dbg(hw, "Failed to read, error %x\n", error); 719 ret = -EIO; 720 goto out; 721 } 722 723 if (!ret) 724 *data = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA); 725 726 out: 727 hw->mac.ops.release_swfw_sync(hw, gssr); 728 return ret; 729 } 730 731 /** 732 * ixgbe_get_phy_token - Get the token for shared PHY access 733 * @hw: Pointer to hardware structure 734 */ 735 static s32 ixgbe_get_phy_token(struct ixgbe_hw *hw) 736 { 737 struct ixgbe_hic_phy_token_req token_cmd; 738 s32 status; 739 740 token_cmd.hdr.cmd = FW_PHY_TOKEN_REQ_CMD; 741 token_cmd.hdr.buf_len = FW_PHY_TOKEN_REQ_LEN; 742 token_cmd.hdr.cmd_or_resp.cmd_resv = 0; 743 token_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM; 744 token_cmd.port_number = hw->bus.lan_id; 745 token_cmd.command_type = FW_PHY_TOKEN_REQ; 746 token_cmd.pad = 0; 747 status = ixgbe_host_interface_command(hw, &token_cmd, sizeof(token_cmd), 748 IXGBE_HI_COMMAND_TIMEOUT, 749 true); 750 if (status) 751 return status; 752 if (token_cmd.hdr.cmd_or_resp.ret_status == FW_PHY_TOKEN_OK) 753 return 0; 754 if (token_cmd.hdr.cmd_or_resp.ret_status != FW_PHY_TOKEN_RETRY) 755 return -EIO; 756 757 return -EAGAIN; 758 } 759 760 /** 761 * ixgbe_put_phy_token - Put the token for shared PHY access 762 * @hw: Pointer to hardware structure 763 */ 764 static s32 ixgbe_put_phy_token(struct ixgbe_hw *hw) 765 { 766 struct ixgbe_hic_phy_token_req token_cmd; 767 s32 status; 768 769 token_cmd.hdr.cmd = FW_PHY_TOKEN_REQ_CMD; 770 token_cmd.hdr.buf_len = FW_PHY_TOKEN_REQ_LEN; 771 token_cmd.hdr.cmd_or_resp.cmd_resv = 0; 772 token_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM; 773 token_cmd.port_number = hw->bus.lan_id; 774 token_cmd.command_type = FW_PHY_TOKEN_REL; 775 token_cmd.pad = 0; 776 status = ixgbe_host_interface_command(hw, &token_cmd, sizeof(token_cmd), 777 IXGBE_HI_COMMAND_TIMEOUT, 778 true); 779 if (status) 780 return status; 781 if (token_cmd.hdr.cmd_or_resp.ret_status == FW_PHY_TOKEN_OK) 782 return 0; 783 return -EIO; 784 } 785 786 /** 787 * ixgbe_write_iosf_sb_reg_x550a - Write to IOSF PHY register 788 * @hw: pointer to hardware structure 789 * @reg_addr: 32 bit PHY register to write 790 * @device_type: 3 bit device type 791 * @data: Data to write to the register 792 **/ 793 static s32 ixgbe_write_iosf_sb_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr, 794 __always_unused u32 device_type, 795 u32 data) 796 { 797 struct ixgbe_hic_internal_phy_req write_cmd; 798 799 memset(&write_cmd, 0, sizeof(write_cmd)); 800 write_cmd.hdr.cmd = FW_INT_PHY_REQ_CMD; 801 write_cmd.hdr.buf_len = FW_INT_PHY_REQ_LEN; 802 write_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM; 803 write_cmd.port_number = hw->bus.lan_id; 804 write_cmd.command_type = FW_INT_PHY_REQ_WRITE; 805 write_cmd.address = cpu_to_be16(reg_addr); 806 write_cmd.write_data = cpu_to_be32(data); 807 808 return ixgbe_host_interface_command(hw, &write_cmd, sizeof(write_cmd), 809 IXGBE_HI_COMMAND_TIMEOUT, false); 810 } 811 812 /** 813 * ixgbe_read_iosf_sb_reg_x550a - Read from IOSF PHY register 814 * @hw: pointer to hardware structure 815 * @reg_addr: 32 bit PHY register to write 816 * @device_type: 3 bit device type 817 * @data: Pointer to read data from the register 818 **/ 819 static s32 ixgbe_read_iosf_sb_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr, 820 __always_unused u32 device_type, 821 u32 *data) 822 { 823 union { 824 struct ixgbe_hic_internal_phy_req cmd; 825 struct ixgbe_hic_internal_phy_resp rsp; 826 } hic; 827 s32 status; 828 829 memset(&hic, 0, sizeof(hic)); 830 hic.cmd.hdr.cmd = FW_INT_PHY_REQ_CMD; 831 hic.cmd.hdr.buf_len = FW_INT_PHY_REQ_LEN; 832 hic.cmd.hdr.checksum = FW_DEFAULT_CHECKSUM; 833 hic.cmd.port_number = hw->bus.lan_id; 834 hic.cmd.command_type = FW_INT_PHY_REQ_READ; 835 hic.cmd.address = cpu_to_be16(reg_addr); 836 837 status = ixgbe_host_interface_command(hw, &hic.cmd, sizeof(hic.cmd), 838 IXGBE_HI_COMMAND_TIMEOUT, true); 839 840 /* Extract the register value from the response. */ 841 *data = be32_to_cpu(hic.rsp.read_data); 842 843 return status; 844 } 845 846 /** ixgbe_read_ee_hostif_buffer_X550- Read EEPROM word(s) using hostif 847 * @hw: pointer to hardware structure 848 * @offset: offset of word in the EEPROM to read 849 * @words: number of words 850 * @data: word(s) read from the EEPROM 851 * 852 * Reads a 16 bit word(s) from the EEPROM using the hostif. 853 **/ 854 static s32 ixgbe_read_ee_hostif_buffer_X550(struct ixgbe_hw *hw, 855 u16 offset, u16 words, u16 *data) 856 { 857 const u32 mask = IXGBE_GSSR_SW_MNG_SM | IXGBE_GSSR_EEP_SM; 858 struct ixgbe_hic_read_shadow_ram buffer; 859 u32 current_word = 0; 860 u16 words_to_read; 861 s32 status; 862 u32 i; 863 864 /* Take semaphore for the entire operation. */ 865 status = hw->mac.ops.acquire_swfw_sync(hw, mask); 866 if (status) { 867 hw_dbg(hw, "EEPROM read buffer - semaphore failed\n"); 868 return status; 869 } 870 871 while (words) { 872 if (words > FW_MAX_READ_BUFFER_SIZE / 2) 873 words_to_read = FW_MAX_READ_BUFFER_SIZE / 2; 874 else 875 words_to_read = words; 876 877 buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD; 878 buffer.hdr.req.buf_lenh = 0; 879 buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN; 880 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM; 881 882 /* convert offset from words to bytes */ 883 buffer.address = (__force u32)cpu_to_be32((offset + 884 current_word) * 2); 885 buffer.length = (__force u16)cpu_to_be16(words_to_read * 2); 886 buffer.pad2 = 0; 887 buffer.pad3 = 0; 888 889 status = ixgbe_hic_unlocked(hw, (u32 *)&buffer, sizeof(buffer), 890 IXGBE_HI_COMMAND_TIMEOUT); 891 if (status) { 892 hw_dbg(hw, "Host interface command failed\n"); 893 goto out; 894 } 895 896 for (i = 0; i < words_to_read; i++) { 897 u32 reg = IXGBE_FLEX_MNG + (FW_NVM_DATA_OFFSET << 2) + 898 2 * i; 899 u32 value = IXGBE_READ_REG(hw, reg); 900 901 data[current_word] = (u16)(value & 0xffff); 902 current_word++; 903 i++; 904 if (i < words_to_read) { 905 value >>= 16; 906 data[current_word] = (u16)(value & 0xffff); 907 current_word++; 908 } 909 } 910 words -= words_to_read; 911 } 912 913 out: 914 hw->mac.ops.release_swfw_sync(hw, mask); 915 return status; 916 } 917 918 /** ixgbe_checksum_ptr_x550 - Checksum one pointer region 919 * @hw: pointer to hardware structure 920 * @ptr: pointer offset in eeprom 921 * @size: size of section pointed by ptr, if 0 first word will be used as size 922 * @csum: address of checksum to update 923 * 924 * Returns error status for any failure 925 **/ 926 static s32 ixgbe_checksum_ptr_x550(struct ixgbe_hw *hw, u16 ptr, 927 u16 size, u16 *csum, u16 *buffer, 928 u32 buffer_size) 929 { 930 u16 buf[256]; 931 s32 status; 932 u16 length, bufsz, i, start; 933 u16 *local_buffer; 934 935 bufsz = ARRAY_SIZE(buf); 936 937 /* Read a chunk at the pointer location */ 938 if (!buffer) { 939 status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr, bufsz, buf); 940 if (status) { 941 hw_dbg(hw, "Failed to read EEPROM image\n"); 942 return status; 943 } 944 local_buffer = buf; 945 } else { 946 if (buffer_size < ptr) 947 return -EINVAL; 948 local_buffer = &buffer[ptr]; 949 } 950 951 if (size) { 952 start = 0; 953 length = size; 954 } else { 955 start = 1; 956 length = local_buffer[0]; 957 958 /* Skip pointer section if length is invalid. */ 959 if (length == 0xFFFF || length == 0 || 960 (ptr + length) >= hw->eeprom.word_size) 961 return 0; 962 } 963 964 if (buffer && ((u32)start + (u32)length > buffer_size)) 965 return -EINVAL; 966 967 for (i = start; length; i++, length--) { 968 if (i == bufsz && !buffer) { 969 ptr += bufsz; 970 i = 0; 971 if (length < bufsz) 972 bufsz = length; 973 974 /* Read a chunk at the pointer location */ 975 status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr, 976 bufsz, buf); 977 if (status) { 978 hw_dbg(hw, "Failed to read EEPROM image\n"); 979 return status; 980 } 981 } 982 *csum += local_buffer[i]; 983 } 984 return 0; 985 } 986 987 /** ixgbe_calc_checksum_X550 - Calculates and returns the checksum 988 * @hw: pointer to hardware structure 989 * @buffer: pointer to buffer containing calculated checksum 990 * @buffer_size: size of buffer 991 * 992 * Returns a negative error code on error, or the 16-bit checksum 993 **/ 994 static s32 ixgbe_calc_checksum_X550(struct ixgbe_hw *hw, u16 *buffer, 995 u32 buffer_size) 996 { 997 u16 eeprom_ptrs[IXGBE_EEPROM_LAST_WORD + 1]; 998 u16 *local_buffer; 999 s32 status; 1000 u16 checksum = 0; 1001 u16 pointer, i, size; 1002 1003 hw->eeprom.ops.init_params(hw); 1004 1005 if (!buffer) { 1006 /* Read pointer area */ 1007 status = ixgbe_read_ee_hostif_buffer_X550(hw, 0, 1008 IXGBE_EEPROM_LAST_WORD + 1, 1009 eeprom_ptrs); 1010 if (status) { 1011 hw_dbg(hw, "Failed to read EEPROM image\n"); 1012 return status; 1013 } 1014 local_buffer = eeprom_ptrs; 1015 } else { 1016 if (buffer_size < IXGBE_EEPROM_LAST_WORD) 1017 return -EINVAL; 1018 local_buffer = buffer; 1019 } 1020 1021 /* For X550 hardware include 0x0-0x41 in the checksum, skip the 1022 * checksum word itself 1023 */ 1024 for (i = 0; i <= IXGBE_EEPROM_LAST_WORD; i++) 1025 if (i != IXGBE_EEPROM_CHECKSUM) 1026 checksum += local_buffer[i]; 1027 1028 /* Include all data from pointers 0x3, 0x6-0xE. This excludes the 1029 * FW, PHY module, and PCIe Expansion/Option ROM pointers. 1030 */ 1031 for (i = IXGBE_PCIE_ANALOG_PTR_X550; i < IXGBE_FW_PTR; i++) { 1032 if (i == IXGBE_PHY_PTR || i == IXGBE_OPTION_ROM_PTR) 1033 continue; 1034 1035 pointer = local_buffer[i]; 1036 1037 /* Skip pointer section if the pointer is invalid. */ 1038 if (pointer == 0xFFFF || pointer == 0 || 1039 pointer >= hw->eeprom.word_size) 1040 continue; 1041 1042 switch (i) { 1043 case IXGBE_PCIE_GENERAL_PTR: 1044 size = IXGBE_IXGBE_PCIE_GENERAL_SIZE; 1045 break; 1046 case IXGBE_PCIE_CONFIG0_PTR: 1047 case IXGBE_PCIE_CONFIG1_PTR: 1048 size = IXGBE_PCIE_CONFIG_SIZE; 1049 break; 1050 default: 1051 size = 0; 1052 break; 1053 } 1054 1055 status = ixgbe_checksum_ptr_x550(hw, pointer, size, &checksum, 1056 buffer, buffer_size); 1057 if (status) 1058 return status; 1059 } 1060 1061 checksum = (u16)IXGBE_EEPROM_SUM - checksum; 1062 1063 return (s32)checksum; 1064 } 1065 1066 /** ixgbe_calc_eeprom_checksum_X550 - Calculates and returns the checksum 1067 * @hw: pointer to hardware structure 1068 * 1069 * Returns a negative error code on error, or the 16-bit checksum 1070 **/ 1071 static s32 ixgbe_calc_eeprom_checksum_X550(struct ixgbe_hw *hw) 1072 { 1073 return ixgbe_calc_checksum_X550(hw, NULL, 0); 1074 } 1075 1076 /** ixgbe_read_ee_hostif_X550 - Read EEPROM word using a host interface command 1077 * @hw: pointer to hardware structure 1078 * @offset: offset of word in the EEPROM to read 1079 * @data: word read from the EEPROM 1080 * 1081 * Reads a 16 bit word from the EEPROM using the hostif. 1082 **/ 1083 static s32 ixgbe_read_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset, u16 *data) 1084 { 1085 const u32 mask = IXGBE_GSSR_SW_MNG_SM | IXGBE_GSSR_EEP_SM; 1086 struct ixgbe_hic_read_shadow_ram buffer; 1087 s32 status; 1088 1089 buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD; 1090 buffer.hdr.req.buf_lenh = 0; 1091 buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN; 1092 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM; 1093 1094 /* convert offset from words to bytes */ 1095 buffer.address = (__force u32)cpu_to_be32(offset * 2); 1096 /* one word */ 1097 buffer.length = (__force u16)cpu_to_be16(sizeof(u16)); 1098 1099 status = hw->mac.ops.acquire_swfw_sync(hw, mask); 1100 if (status) 1101 return status; 1102 1103 status = ixgbe_hic_unlocked(hw, (u32 *)&buffer, sizeof(buffer), 1104 IXGBE_HI_COMMAND_TIMEOUT); 1105 if (!status) { 1106 *data = (u16)IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG, 1107 FW_NVM_DATA_OFFSET); 1108 } 1109 1110 hw->mac.ops.release_swfw_sync(hw, mask); 1111 return status; 1112 } 1113 1114 /** ixgbe_validate_eeprom_checksum_X550 - Validate EEPROM checksum 1115 * @hw: pointer to hardware structure 1116 * @checksum_val: calculated checksum 1117 * 1118 * Performs checksum calculation and validates the EEPROM checksum. If the 1119 * caller does not need checksum_val, the value can be NULL. 1120 **/ 1121 static s32 ixgbe_validate_eeprom_checksum_X550(struct ixgbe_hw *hw, 1122 u16 *checksum_val) 1123 { 1124 s32 status; 1125 u16 checksum; 1126 u16 read_checksum = 0; 1127 1128 /* Read the first word from the EEPROM. If this times out or fails, do 1129 * not continue or we could be in for a very long wait while every 1130 * EEPROM read fails 1131 */ 1132 status = hw->eeprom.ops.read(hw, 0, &checksum); 1133 if (status) { 1134 hw_dbg(hw, "EEPROM read failed\n"); 1135 return status; 1136 } 1137 1138 status = hw->eeprom.ops.calc_checksum(hw); 1139 if (status < 0) 1140 return status; 1141 1142 checksum = (u16)(status & 0xffff); 1143 1144 status = ixgbe_read_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM, 1145 &read_checksum); 1146 if (status) 1147 return status; 1148 1149 /* Verify read checksum from EEPROM is the same as 1150 * calculated checksum 1151 */ 1152 if (read_checksum != checksum) { 1153 status = -EIO; 1154 hw_dbg(hw, "Invalid EEPROM checksum"); 1155 } 1156 1157 /* If the user cares, return the calculated checksum */ 1158 if (checksum_val) 1159 *checksum_val = checksum; 1160 1161 return status; 1162 } 1163 1164 /** ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif 1165 * @hw: pointer to hardware structure 1166 * @offset: offset of word in the EEPROM to write 1167 * @data: word write to the EEPROM 1168 * 1169 * Write a 16 bit word to the EEPROM using the hostif. 1170 **/ 1171 static s32 ixgbe_write_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset, 1172 u16 data) 1173 { 1174 s32 status; 1175 struct ixgbe_hic_write_shadow_ram buffer; 1176 1177 buffer.hdr.req.cmd = FW_WRITE_SHADOW_RAM_CMD; 1178 buffer.hdr.req.buf_lenh = 0; 1179 buffer.hdr.req.buf_lenl = FW_WRITE_SHADOW_RAM_LEN; 1180 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM; 1181 1182 /* one word */ 1183 buffer.length = cpu_to_be16(sizeof(u16)); 1184 buffer.data = data; 1185 buffer.address = cpu_to_be32(offset * 2); 1186 1187 status = ixgbe_host_interface_command(hw, &buffer, sizeof(buffer), 1188 IXGBE_HI_COMMAND_TIMEOUT, false); 1189 return status; 1190 } 1191 1192 /** ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif 1193 * @hw: pointer to hardware structure 1194 * @offset: offset of word in the EEPROM to write 1195 * @data: word write to the EEPROM 1196 * 1197 * Write a 16 bit word to the EEPROM using the hostif. 1198 **/ 1199 static s32 ixgbe_write_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset, u16 data) 1200 { 1201 s32 status = 0; 1202 1203 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) == 0) { 1204 status = ixgbe_write_ee_hostif_data_X550(hw, offset, data); 1205 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 1206 } else { 1207 hw_dbg(hw, "write ee hostif failed to get semaphore"); 1208 status = -EBUSY; 1209 } 1210 1211 return status; 1212 } 1213 1214 /** ixgbe_update_flash_X550 - Instruct HW to copy EEPROM to Flash device 1215 * @hw: pointer to hardware structure 1216 * 1217 * Issue a shadow RAM dump to FW to copy EEPROM from shadow RAM to the flash. 1218 **/ 1219 static s32 ixgbe_update_flash_X550(struct ixgbe_hw *hw) 1220 { 1221 s32 status = 0; 1222 union ixgbe_hic_hdr2 buffer; 1223 1224 buffer.req.cmd = FW_SHADOW_RAM_DUMP_CMD; 1225 buffer.req.buf_lenh = 0; 1226 buffer.req.buf_lenl = FW_SHADOW_RAM_DUMP_LEN; 1227 buffer.req.checksum = FW_DEFAULT_CHECKSUM; 1228 1229 status = ixgbe_host_interface_command(hw, &buffer, sizeof(buffer), 1230 IXGBE_HI_COMMAND_TIMEOUT, false); 1231 return status; 1232 } 1233 1234 /** 1235 * ixgbe_get_bus_info_X550em - Set PCI bus info 1236 * @hw: pointer to hardware structure 1237 * 1238 * Sets bus link width and speed to unknown because X550em is 1239 * not a PCI device. 1240 **/ 1241 static s32 ixgbe_get_bus_info_X550em(struct ixgbe_hw *hw) 1242 { 1243 hw->bus.type = ixgbe_bus_type_internal; 1244 hw->bus.width = ixgbe_bus_width_unknown; 1245 hw->bus.speed = ixgbe_bus_speed_unknown; 1246 1247 hw->mac.ops.set_lan_id(hw); 1248 1249 return 0; 1250 } 1251 1252 /** 1253 * ixgbe_fw_recovery_mode_X550 - Check FW NVM recovery mode 1254 * @hw: pointer t hardware structure 1255 * 1256 * Returns true if in FW NVM recovery mode. 1257 */ 1258 static bool ixgbe_fw_recovery_mode_X550(struct ixgbe_hw *hw) 1259 { 1260 u32 fwsm; 1261 1262 fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM(hw)); 1263 return !!(fwsm & IXGBE_FWSM_FW_NVM_RECOVERY_MODE); 1264 } 1265 1266 /** ixgbe_disable_rx_x550 - Disable RX unit 1267 * 1268 * Enables the Rx DMA unit for x550 1269 **/ 1270 static void ixgbe_disable_rx_x550(struct ixgbe_hw *hw) 1271 { 1272 u32 rxctrl, pfdtxgswc; 1273 s32 status; 1274 struct ixgbe_hic_disable_rxen fw_cmd; 1275 1276 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL); 1277 if (rxctrl & IXGBE_RXCTRL_RXEN) { 1278 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC); 1279 if (pfdtxgswc & IXGBE_PFDTXGSWC_VT_LBEN) { 1280 pfdtxgswc &= ~IXGBE_PFDTXGSWC_VT_LBEN; 1281 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc); 1282 hw->mac.set_lben = true; 1283 } else { 1284 hw->mac.set_lben = false; 1285 } 1286 1287 fw_cmd.hdr.cmd = FW_DISABLE_RXEN_CMD; 1288 fw_cmd.hdr.buf_len = FW_DISABLE_RXEN_LEN; 1289 fw_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM; 1290 fw_cmd.port_number = hw->bus.lan_id; 1291 1292 status = ixgbe_host_interface_command(hw, &fw_cmd, 1293 sizeof(struct ixgbe_hic_disable_rxen), 1294 IXGBE_HI_COMMAND_TIMEOUT, true); 1295 1296 /* If we fail - disable RX using register write */ 1297 if (status) { 1298 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL); 1299 if (rxctrl & IXGBE_RXCTRL_RXEN) { 1300 rxctrl &= ~IXGBE_RXCTRL_RXEN; 1301 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl); 1302 } 1303 } 1304 } 1305 } 1306 1307 /** ixgbe_update_eeprom_checksum_X550 - Updates the EEPROM checksum and flash 1308 * @hw: pointer to hardware structure 1309 * 1310 * After writing EEPROM to shadow RAM using EEWR register, software calculates 1311 * checksum and updates the EEPROM and instructs the hardware to update 1312 * the flash. 1313 **/ 1314 static s32 ixgbe_update_eeprom_checksum_X550(struct ixgbe_hw *hw) 1315 { 1316 s32 status; 1317 u16 checksum = 0; 1318 1319 /* Read the first word from the EEPROM. If this times out or fails, do 1320 * not continue or we could be in for a very long wait while every 1321 * EEPROM read fails 1322 */ 1323 status = ixgbe_read_ee_hostif_X550(hw, 0, &checksum); 1324 if (status) { 1325 hw_dbg(hw, "EEPROM read failed\n"); 1326 return status; 1327 } 1328 1329 status = ixgbe_calc_eeprom_checksum_X550(hw); 1330 if (status < 0) 1331 return status; 1332 1333 checksum = (u16)(status & 0xffff); 1334 1335 status = ixgbe_write_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM, 1336 checksum); 1337 if (status) 1338 return status; 1339 1340 status = ixgbe_update_flash_X550(hw); 1341 1342 return status; 1343 } 1344 1345 /** ixgbe_write_ee_hostif_buffer_X550 - Write EEPROM word(s) using hostif 1346 * @hw: pointer to hardware structure 1347 * @offset: offset of word in the EEPROM to write 1348 * @words: number of words 1349 * @data: word(s) write to the EEPROM 1350 * 1351 * 1352 * Write a 16 bit word(s) to the EEPROM using the hostif. 1353 **/ 1354 static s32 ixgbe_write_ee_hostif_buffer_X550(struct ixgbe_hw *hw, 1355 u16 offset, u16 words, 1356 u16 *data) 1357 { 1358 s32 status = 0; 1359 u32 i = 0; 1360 1361 /* Take semaphore for the entire operation. */ 1362 status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 1363 if (status) { 1364 hw_dbg(hw, "EEPROM write buffer - semaphore failed\n"); 1365 return status; 1366 } 1367 1368 for (i = 0; i < words; i++) { 1369 status = ixgbe_write_ee_hostif_data_X550(hw, offset + i, 1370 data[i]); 1371 if (status) { 1372 hw_dbg(hw, "Eeprom buffered write failed\n"); 1373 break; 1374 } 1375 } 1376 1377 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 1378 1379 return status; 1380 } 1381 1382 /** ixgbe_write_iosf_sb_reg_x550 - Writes a value to specified register of the 1383 * IOSF device 1384 * 1385 * @hw: pointer to hardware structure 1386 * @reg_addr: 32 bit PHY register to write 1387 * @device_type: 3 bit device type 1388 * @data: Data to write to the register 1389 **/ 1390 static s32 ixgbe_write_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr, 1391 u32 device_type, u32 data) 1392 { 1393 u32 gssr = IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_PHY0_SM; 1394 u32 command, error; 1395 s32 ret; 1396 1397 ret = hw->mac.ops.acquire_swfw_sync(hw, gssr); 1398 if (ret) 1399 return ret; 1400 1401 ret = ixgbe_iosf_wait(hw, NULL); 1402 if (ret) 1403 goto out; 1404 1405 command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) | 1406 (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT)); 1407 1408 /* Write IOSF control register */ 1409 IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command); 1410 1411 /* Write IOSF data register */ 1412 IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA, data); 1413 1414 ret = ixgbe_iosf_wait(hw, &command); 1415 1416 if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) { 1417 error = FIELD_GET(IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK, command); 1418 hw_dbg(hw, "Failed to write, error %x\n", error); 1419 return -EIO; 1420 } 1421 1422 out: 1423 hw->mac.ops.release_swfw_sync(hw, gssr); 1424 return ret; 1425 } 1426 1427 /** 1428 * ixgbe_setup_ixfi_x550em_x - MAC specific iXFI configuration 1429 * @hw: pointer to hardware structure 1430 * 1431 * iXfI configuration needed for ixgbe_mac_X550EM_x devices. 1432 **/ 1433 static s32 ixgbe_setup_ixfi_x550em_x(struct ixgbe_hw *hw) 1434 { 1435 s32 status; 1436 u32 reg_val; 1437 1438 /* Disable training protocol FSM. */ 1439 status = ixgbe_read_iosf_sb_reg_x550(hw, 1440 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id), 1441 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val); 1442 if (status) 1443 return status; 1444 1445 reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_CONV_WO_PROTOCOL; 1446 status = ixgbe_write_iosf_sb_reg_x550(hw, 1447 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id), 1448 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val); 1449 if (status) 1450 return status; 1451 1452 /* Disable Flex from training TXFFE. */ 1453 status = ixgbe_read_iosf_sb_reg_x550(hw, 1454 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id), 1455 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val); 1456 if (status) 1457 return status; 1458 1459 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN; 1460 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN; 1461 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN; 1462 status = ixgbe_write_iosf_sb_reg_x550(hw, 1463 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id), 1464 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val); 1465 if (status) 1466 return status; 1467 1468 status = ixgbe_read_iosf_sb_reg_x550(hw, 1469 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id), 1470 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val); 1471 if (status) 1472 return status; 1473 1474 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN; 1475 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN; 1476 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN; 1477 status = ixgbe_write_iosf_sb_reg_x550(hw, 1478 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id), 1479 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val); 1480 if (status) 1481 return status; 1482 1483 /* Enable override for coefficients. */ 1484 status = ixgbe_read_iosf_sb_reg_x550(hw, 1485 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id), 1486 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val); 1487 if (status) 1488 return status; 1489 1490 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_OVRRD_EN; 1491 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CZERO_EN; 1492 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CPLUS1_OVRRD_EN; 1493 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CMINUS1_OVRRD_EN; 1494 status = ixgbe_write_iosf_sb_reg_x550(hw, 1495 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id), 1496 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val); 1497 return status; 1498 } 1499 1500 /** 1501 * ixgbe_restart_an_internal_phy_x550em - restart autonegotiation for the 1502 * internal PHY 1503 * @hw: pointer to hardware structure 1504 **/ 1505 static s32 ixgbe_restart_an_internal_phy_x550em(struct ixgbe_hw *hw) 1506 { 1507 s32 status; 1508 u32 link_ctrl; 1509 1510 /* Restart auto-negotiation. */ 1511 status = hw->mac.ops.read_iosf_sb_reg(hw, 1512 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id), 1513 IXGBE_SB_IOSF_TARGET_KR_PHY, &link_ctrl); 1514 1515 if (status) { 1516 hw_dbg(hw, "Auto-negotiation did not complete\n"); 1517 return status; 1518 } 1519 1520 link_ctrl |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART; 1521 status = hw->mac.ops.write_iosf_sb_reg(hw, 1522 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id), 1523 IXGBE_SB_IOSF_TARGET_KR_PHY, link_ctrl); 1524 1525 if (hw->mac.type == ixgbe_mac_x550em_a) { 1526 u32 flx_mask_st20; 1527 1528 /* Indicate to FW that AN restart has been asserted */ 1529 status = hw->mac.ops.read_iosf_sb_reg(hw, 1530 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id), 1531 IXGBE_SB_IOSF_TARGET_KR_PHY, &flx_mask_st20); 1532 1533 if (status) { 1534 hw_dbg(hw, "Auto-negotiation did not complete\n"); 1535 return status; 1536 } 1537 1538 flx_mask_st20 |= IXGBE_KRM_PMD_FLX_MASK_ST20_FW_AN_RESTART; 1539 status = hw->mac.ops.write_iosf_sb_reg(hw, 1540 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id), 1541 IXGBE_SB_IOSF_TARGET_KR_PHY, flx_mask_st20); 1542 } 1543 1544 return status; 1545 } 1546 1547 /** ixgbe_setup_ixfi_x550em - Configure the KR PHY for iXFI mode. 1548 * @hw: pointer to hardware structure 1549 * @speed: the link speed to force 1550 * 1551 * Configures the integrated KR PHY to use iXFI mode. Used to connect an 1552 * internal and external PHY at a specific speed, without autonegotiation. 1553 **/ 1554 static s32 ixgbe_setup_ixfi_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed) 1555 { 1556 struct ixgbe_mac_info *mac = &hw->mac; 1557 s32 status; 1558 u32 reg_val; 1559 1560 /* iXFI is only supported with X552 */ 1561 if (mac->type != ixgbe_mac_X550EM_x) 1562 return -EIO; 1563 1564 /* Disable AN and force speed to 10G Serial. */ 1565 status = ixgbe_read_iosf_sb_reg_x550(hw, 1566 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id), 1567 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val); 1568 if (status) 1569 return status; 1570 1571 reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE; 1572 reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK; 1573 1574 /* Select forced link speed for internal PHY. */ 1575 switch (*speed) { 1576 case IXGBE_LINK_SPEED_10GB_FULL: 1577 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G; 1578 break; 1579 case IXGBE_LINK_SPEED_1GB_FULL: 1580 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G; 1581 break; 1582 default: 1583 /* Other link speeds are not supported by internal KR PHY. */ 1584 return -EINVAL; 1585 } 1586 1587 status = ixgbe_write_iosf_sb_reg_x550(hw, 1588 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id), 1589 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val); 1590 if (status) 1591 return status; 1592 1593 /* Additional configuration needed for x550em_x */ 1594 if (hw->mac.type == ixgbe_mac_X550EM_x) { 1595 status = ixgbe_setup_ixfi_x550em_x(hw); 1596 if (status) 1597 return status; 1598 } 1599 1600 /* Toggle port SW reset by AN reset. */ 1601 status = ixgbe_restart_an_internal_phy_x550em(hw); 1602 1603 return status; 1604 } 1605 1606 /** 1607 * ixgbe_supported_sfp_modules_X550em - Check if SFP module type is supported 1608 * @hw: pointer to hardware structure 1609 * @linear: true if SFP module is linear 1610 */ 1611 static s32 ixgbe_supported_sfp_modules_X550em(struct ixgbe_hw *hw, bool *linear) 1612 { 1613 switch (hw->phy.sfp_type) { 1614 case ixgbe_sfp_type_not_present: 1615 return -ENOENT; 1616 case ixgbe_sfp_type_da_cu_core0: 1617 case ixgbe_sfp_type_da_cu_core1: 1618 *linear = true; 1619 break; 1620 case ixgbe_sfp_type_srlr_core0: 1621 case ixgbe_sfp_type_srlr_core1: 1622 case ixgbe_sfp_type_da_act_lmt_core0: 1623 case ixgbe_sfp_type_da_act_lmt_core1: 1624 case ixgbe_sfp_type_1g_sx_core0: 1625 case ixgbe_sfp_type_1g_sx_core1: 1626 case ixgbe_sfp_type_1g_lx_core0: 1627 case ixgbe_sfp_type_1g_lx_core1: 1628 *linear = false; 1629 break; 1630 case ixgbe_sfp_type_unknown: 1631 case ixgbe_sfp_type_1g_cu_core0: 1632 case ixgbe_sfp_type_1g_cu_core1: 1633 default: 1634 return -EOPNOTSUPP; 1635 } 1636 1637 return 0; 1638 } 1639 1640 /** 1641 * ixgbe_setup_mac_link_sfp_x550em - Configure the KR PHY for SFP. 1642 * @hw: pointer to hardware structure 1643 * @speed: the link speed to force 1644 * @autoneg_wait_to_complete: unused 1645 * 1646 * Configures the extern PHY and the integrated KR PHY for SFP support. 1647 */ 1648 static s32 1649 ixgbe_setup_mac_link_sfp_x550em(struct ixgbe_hw *hw, 1650 ixgbe_link_speed speed, 1651 __always_unused bool autoneg_wait_to_complete) 1652 { 1653 s32 status; 1654 u16 reg_slice, reg_val; 1655 bool setup_linear = false; 1656 1657 /* Check if SFP module is supported and linear */ 1658 status = ixgbe_supported_sfp_modules_X550em(hw, &setup_linear); 1659 1660 /* If no SFP module present, then return success. Return success since 1661 * there is no reason to configure CS4227 and SFP not present error is 1662 * not accepted in the setup MAC link flow. 1663 */ 1664 if (status == -ENOENT) 1665 return 0; 1666 1667 if (status) 1668 return status; 1669 1670 /* Configure internal PHY for KR/KX. */ 1671 ixgbe_setup_kr_speed_x550em(hw, speed); 1672 1673 /* Configure CS4227 LINE side to proper mode. */ 1674 reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB + (hw->bus.lan_id << 12); 1675 if (setup_linear) 1676 reg_val = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1; 1677 else 1678 reg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1; 1679 1680 status = hw->link.ops.write_link(hw, hw->link.addr, reg_slice, 1681 reg_val); 1682 1683 return status; 1684 } 1685 1686 /** 1687 * ixgbe_setup_sfi_x550a - Configure the internal PHY for native SFI mode 1688 * @hw: pointer to hardware structure 1689 * @speed: the link speed to force 1690 * 1691 * Configures the integrated PHY for native SFI mode. Used to connect the 1692 * internal PHY directly to an SFP cage, without autonegotiation. 1693 **/ 1694 static s32 ixgbe_setup_sfi_x550a(struct ixgbe_hw *hw, ixgbe_link_speed *speed) 1695 { 1696 struct ixgbe_mac_info *mac = &hw->mac; 1697 s32 status; 1698 u32 reg_val; 1699 1700 /* Disable all AN and force speed to 10G Serial. */ 1701 status = mac->ops.read_iosf_sb_reg(hw, 1702 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id), 1703 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val); 1704 if (status) 1705 return status; 1706 1707 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN_EN; 1708 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN37_EN; 1709 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SGMII_EN; 1710 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_MASK; 1711 1712 /* Select forced link speed for internal PHY. */ 1713 switch (*speed) { 1714 case IXGBE_LINK_SPEED_10GB_FULL: 1715 reg_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_10G; 1716 break; 1717 case IXGBE_LINK_SPEED_1GB_FULL: 1718 reg_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_1G; 1719 break; 1720 default: 1721 /* Other link speeds are not supported by internal PHY. */ 1722 return -EINVAL; 1723 } 1724 1725 status = mac->ops.write_iosf_sb_reg(hw, 1726 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id), 1727 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val); 1728 1729 /* Toggle port SW reset by AN reset. */ 1730 status = ixgbe_restart_an_internal_phy_x550em(hw); 1731 1732 return status; 1733 } 1734 1735 /** 1736 * ixgbe_setup_mac_link_sfp_n - Setup internal PHY for native SFP 1737 * @hw: pointer to hardware structure 1738 * @speed: link speed 1739 * @autoneg_wait_to_complete: unused 1740 * 1741 * Configure the integrated PHY for native SFP support. 1742 */ 1743 static s32 1744 ixgbe_setup_mac_link_sfp_n(struct ixgbe_hw *hw, ixgbe_link_speed speed, 1745 __always_unused bool autoneg_wait_to_complete) 1746 { 1747 bool setup_linear = false; 1748 u32 reg_phy_int; 1749 s32 ret_val; 1750 1751 /* Check if SFP module is supported and linear */ 1752 ret_val = ixgbe_supported_sfp_modules_X550em(hw, &setup_linear); 1753 1754 /* If no SFP module present, then return success. Return success since 1755 * SFP not present error is not excepted in the setup MAC link flow. 1756 */ 1757 if (ret_val == -ENOENT) 1758 return 0; 1759 1760 if (ret_val) 1761 return ret_val; 1762 1763 /* Configure internal PHY for native SFI based on module type */ 1764 ret_val = hw->mac.ops.read_iosf_sb_reg(hw, 1765 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id), 1766 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_phy_int); 1767 if (ret_val) 1768 return ret_val; 1769 1770 reg_phy_int &= IXGBE_KRM_PMD_FLX_MASK_ST20_SFI_10G_DA; 1771 if (!setup_linear) 1772 reg_phy_int |= IXGBE_KRM_PMD_FLX_MASK_ST20_SFI_10G_SR; 1773 1774 ret_val = hw->mac.ops.write_iosf_sb_reg(hw, 1775 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id), 1776 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_phy_int); 1777 if (ret_val) 1778 return ret_val; 1779 1780 /* Setup SFI internal link. */ 1781 return ixgbe_setup_sfi_x550a(hw, &speed); 1782 } 1783 1784 /** 1785 * ixgbe_setup_mac_link_sfp_x550a - Setup internal PHY for SFP 1786 * @hw: pointer to hardware structure 1787 * @speed: link speed 1788 * @autoneg_wait_to_complete: unused 1789 * 1790 * Configure the integrated PHY for SFP support. 1791 */ 1792 static s32 1793 ixgbe_setup_mac_link_sfp_x550a(struct ixgbe_hw *hw, ixgbe_link_speed speed, 1794 __always_unused bool autoneg_wait_to_complete) 1795 { 1796 u32 reg_slice, slice_offset; 1797 bool setup_linear = false; 1798 u16 reg_phy_ext; 1799 s32 ret_val; 1800 1801 /* Check if SFP module is supported and linear */ 1802 ret_val = ixgbe_supported_sfp_modules_X550em(hw, &setup_linear); 1803 1804 /* If no SFP module present, then return success. Return success since 1805 * SFP not present error is not excepted in the setup MAC link flow. 1806 */ 1807 if (ret_val == -ENOENT) 1808 return 0; 1809 1810 if (ret_val) 1811 return ret_val; 1812 1813 /* Configure internal PHY for KR/KX. */ 1814 ixgbe_setup_kr_speed_x550em(hw, speed); 1815 1816 if (hw->phy.mdio.prtad == MDIO_PRTAD_NONE) 1817 return -EFAULT; 1818 1819 /* Get external PHY SKU id */ 1820 ret_val = hw->phy.ops.read_reg(hw, IXGBE_CS4227_EFUSE_PDF_SKU, 1821 IXGBE_MDIO_ZERO_DEV_TYPE, ®_phy_ext); 1822 if (ret_val) 1823 return ret_val; 1824 1825 /* When configuring quad port CS4223, the MAC instance is part 1826 * of the slice offset. 1827 */ 1828 if (reg_phy_ext == IXGBE_CS4223_SKU_ID) 1829 slice_offset = (hw->bus.lan_id + 1830 (hw->bus.instance_id << 1)) << 12; 1831 else 1832 slice_offset = hw->bus.lan_id << 12; 1833 1834 /* Configure CS4227/CS4223 LINE side to proper mode. */ 1835 reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB + slice_offset; 1836 1837 ret_val = hw->phy.ops.read_reg(hw, reg_slice, 1838 IXGBE_MDIO_ZERO_DEV_TYPE, ®_phy_ext); 1839 if (ret_val) 1840 return ret_val; 1841 1842 reg_phy_ext &= ~((IXGBE_CS4227_EDC_MODE_CX1 << 1) | 1843 (IXGBE_CS4227_EDC_MODE_SR << 1)); 1844 1845 if (setup_linear) 1846 reg_phy_ext |= (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 1; 1847 else 1848 reg_phy_ext |= (IXGBE_CS4227_EDC_MODE_SR << 1) | 1; 1849 1850 ret_val = hw->phy.ops.write_reg(hw, reg_slice, 1851 IXGBE_MDIO_ZERO_DEV_TYPE, reg_phy_ext); 1852 if (ret_val) 1853 return ret_val; 1854 1855 /* Flush previous write with a read */ 1856 return hw->phy.ops.read_reg(hw, reg_slice, 1857 IXGBE_MDIO_ZERO_DEV_TYPE, ®_phy_ext); 1858 } 1859 1860 /** 1861 * ixgbe_setup_mac_link_t_X550em - Sets the auto advertised link speed 1862 * @hw: pointer to hardware structure 1863 * @speed: new link speed 1864 * @autoneg_wait: true when waiting for completion is needed 1865 * 1866 * Setup internal/external PHY link speed based on link speed, then set 1867 * external PHY auto advertised link speed. 1868 * 1869 * Returns error status for any failure 1870 **/ 1871 static s32 ixgbe_setup_mac_link_t_X550em(struct ixgbe_hw *hw, 1872 ixgbe_link_speed speed, 1873 bool autoneg_wait) 1874 { 1875 s32 status; 1876 ixgbe_link_speed force_speed; 1877 1878 /* Setup internal/external PHY link speed to iXFI (10G), unless 1879 * only 1G is auto advertised then setup KX link. 1880 */ 1881 if (speed & IXGBE_LINK_SPEED_10GB_FULL) 1882 force_speed = IXGBE_LINK_SPEED_10GB_FULL; 1883 else 1884 force_speed = IXGBE_LINK_SPEED_1GB_FULL; 1885 1886 /* If X552 and internal link mode is XFI, then setup XFI internal link. 1887 */ 1888 if (hw->mac.type == ixgbe_mac_X550EM_x && 1889 !(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) { 1890 status = ixgbe_setup_ixfi_x550em(hw, &force_speed); 1891 1892 if (status) 1893 return status; 1894 } 1895 1896 return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait); 1897 } 1898 1899 /** ixgbe_check_link_t_X550em - Determine link and speed status 1900 * @hw: pointer to hardware structure 1901 * @speed: pointer to link speed 1902 * @link_up: true when link is up 1903 * @link_up_wait_to_complete: bool used to wait for link up or not 1904 * 1905 * Check that both the MAC and X557 external PHY have link. 1906 **/ 1907 static s32 ixgbe_check_link_t_X550em(struct ixgbe_hw *hw, 1908 ixgbe_link_speed *speed, 1909 bool *link_up, 1910 bool link_up_wait_to_complete) 1911 { 1912 u32 status; 1913 u16 i, autoneg_status; 1914 1915 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper) 1916 return -EIO; 1917 1918 status = ixgbe_check_mac_link_generic(hw, speed, link_up, 1919 link_up_wait_to_complete); 1920 1921 /* If check link fails or MAC link is not up, then return */ 1922 if (status || !(*link_up)) 1923 return status; 1924 1925 /* MAC link is up, so check external PHY link. 1926 * Link status is latching low, and can only be used to detect link 1927 * drop, and not the current status of the link without performing 1928 * back-to-back reads. 1929 */ 1930 for (i = 0; i < 2; i++) { 1931 status = hw->phy.ops.read_reg(hw, MDIO_STAT1, MDIO_MMD_AN, 1932 &autoneg_status); 1933 1934 if (status) 1935 return status; 1936 } 1937 1938 /* If external PHY link is not up, then indicate link not up */ 1939 if (!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS)) 1940 *link_up = false; 1941 1942 return 0; 1943 } 1944 1945 /** 1946 * ixgbe_setup_sgmii - Set up link for sgmii 1947 * @hw: pointer to hardware structure 1948 * @speed: unused 1949 * @autoneg_wait_to_complete: unused 1950 */ 1951 static s32 1952 ixgbe_setup_sgmii(struct ixgbe_hw *hw, __always_unused ixgbe_link_speed speed, 1953 __always_unused bool autoneg_wait_to_complete) 1954 { 1955 struct ixgbe_mac_info *mac = &hw->mac; 1956 u32 lval, sval, flx_val; 1957 s32 rc; 1958 1959 rc = mac->ops.read_iosf_sb_reg(hw, 1960 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id), 1961 IXGBE_SB_IOSF_TARGET_KR_PHY, &lval); 1962 if (rc) 1963 return rc; 1964 1965 lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE; 1966 lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK; 1967 lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_SGMII_EN; 1968 lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CLAUSE_37_EN; 1969 lval |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G; 1970 rc = mac->ops.write_iosf_sb_reg(hw, 1971 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id), 1972 IXGBE_SB_IOSF_TARGET_KR_PHY, lval); 1973 if (rc) 1974 return rc; 1975 1976 rc = mac->ops.read_iosf_sb_reg(hw, 1977 IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id), 1978 IXGBE_SB_IOSF_TARGET_KR_PHY, &sval); 1979 if (rc) 1980 return rc; 1981 1982 sval |= IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_10_D; 1983 sval |= IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_100_D; 1984 rc = mac->ops.write_iosf_sb_reg(hw, 1985 IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id), 1986 IXGBE_SB_IOSF_TARGET_KR_PHY, sval); 1987 if (rc) 1988 return rc; 1989 1990 rc = mac->ops.read_iosf_sb_reg(hw, 1991 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id), 1992 IXGBE_SB_IOSF_TARGET_KR_PHY, &flx_val); 1993 if (rc) 1994 return rc; 1995 1996 rc = mac->ops.read_iosf_sb_reg(hw, 1997 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id), 1998 IXGBE_SB_IOSF_TARGET_KR_PHY, &flx_val); 1999 if (rc) 2000 return rc; 2001 2002 flx_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_MASK; 2003 flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_1G; 2004 flx_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN_EN; 2005 flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SGMII_EN; 2006 flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_AN37_EN; 2007 2008 rc = mac->ops.write_iosf_sb_reg(hw, 2009 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id), 2010 IXGBE_SB_IOSF_TARGET_KR_PHY, flx_val); 2011 if (rc) 2012 return rc; 2013 2014 rc = ixgbe_restart_an_internal_phy_x550em(hw); 2015 return rc; 2016 } 2017 2018 /** 2019 * ixgbe_setup_sgmii_fw - Set up link for sgmii with firmware-controlled PHYs 2020 * @hw: pointer to hardware structure 2021 * @speed: the link speed to force 2022 * @autoneg_wait: true when waiting for completion is needed 2023 */ 2024 static s32 ixgbe_setup_sgmii_fw(struct ixgbe_hw *hw, ixgbe_link_speed speed, 2025 bool autoneg_wait) 2026 { 2027 struct ixgbe_mac_info *mac = &hw->mac; 2028 u32 lval, sval, flx_val; 2029 s32 rc; 2030 2031 rc = mac->ops.read_iosf_sb_reg(hw, 2032 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id), 2033 IXGBE_SB_IOSF_TARGET_KR_PHY, &lval); 2034 if (rc) 2035 return rc; 2036 2037 lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE; 2038 lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK; 2039 lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_SGMII_EN; 2040 lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CLAUSE_37_EN; 2041 lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G; 2042 rc = mac->ops.write_iosf_sb_reg(hw, 2043 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id), 2044 IXGBE_SB_IOSF_TARGET_KR_PHY, lval); 2045 if (rc) 2046 return rc; 2047 2048 rc = mac->ops.read_iosf_sb_reg(hw, 2049 IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id), 2050 IXGBE_SB_IOSF_TARGET_KR_PHY, &sval); 2051 if (rc) 2052 return rc; 2053 2054 sval &= ~IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_10_D; 2055 sval &= ~IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_100_D; 2056 rc = mac->ops.write_iosf_sb_reg(hw, 2057 IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id), 2058 IXGBE_SB_IOSF_TARGET_KR_PHY, sval); 2059 if (rc) 2060 return rc; 2061 2062 rc = mac->ops.write_iosf_sb_reg(hw, 2063 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id), 2064 IXGBE_SB_IOSF_TARGET_KR_PHY, lval); 2065 if (rc) 2066 return rc; 2067 2068 rc = mac->ops.read_iosf_sb_reg(hw, 2069 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id), 2070 IXGBE_SB_IOSF_TARGET_KR_PHY, &flx_val); 2071 if (rc) 2072 return rc; 2073 2074 flx_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_MASK; 2075 flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_AN; 2076 flx_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN_EN; 2077 flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SGMII_EN; 2078 flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_AN37_EN; 2079 2080 rc = mac->ops.write_iosf_sb_reg(hw, 2081 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id), 2082 IXGBE_SB_IOSF_TARGET_KR_PHY, flx_val); 2083 if (rc) 2084 return rc; 2085 2086 ixgbe_restart_an_internal_phy_x550em(hw); 2087 2088 return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait); 2089 } 2090 2091 /** 2092 * ixgbe_fc_autoneg_sgmii_x550em_a - Enable flow control IEEE clause 37 2093 * @hw: pointer to hardware structure 2094 * 2095 * Enable flow control according to IEEE clause 37. 2096 */ 2097 static void ixgbe_fc_autoneg_sgmii_x550em_a(struct ixgbe_hw *hw) 2098 { 2099 u32 info[FW_PHY_ACT_DATA_COUNT] = { 0 }; 2100 ixgbe_link_speed speed; 2101 s32 status = -EIO; 2102 bool link_up; 2103 2104 /* AN should have completed when the cable was plugged in. 2105 * Look for reasons to bail out. Bail out if: 2106 * - FC autoneg is disabled, or if 2107 * - link is not up. 2108 */ 2109 if (hw->fc.disable_fc_autoneg) 2110 goto out; 2111 2112 hw->mac.ops.check_link(hw, &speed, &link_up, false); 2113 if (!link_up) 2114 goto out; 2115 2116 /* Check if auto-negotiation has completed */ 2117 status = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_GET_LINK_INFO, &info); 2118 if (status || !(info[0] & FW_PHY_ACT_GET_LINK_INFO_AN_COMPLETE)) { 2119 status = -EIO; 2120 goto out; 2121 } 2122 2123 /* Negotiate the flow control */ 2124 status = ixgbe_negotiate_fc(hw, info[0], info[0], 2125 FW_PHY_ACT_GET_LINK_INFO_FC_RX, 2126 FW_PHY_ACT_GET_LINK_INFO_FC_TX, 2127 FW_PHY_ACT_GET_LINK_INFO_LP_FC_RX, 2128 FW_PHY_ACT_GET_LINK_INFO_LP_FC_TX); 2129 2130 out: 2131 if (!status) { 2132 hw->fc.fc_was_autonegged = true; 2133 } else { 2134 hw->fc.fc_was_autonegged = false; 2135 hw->fc.current_mode = hw->fc.requested_mode; 2136 } 2137 } 2138 2139 /** ixgbe_init_mac_link_ops_X550em_a - Init mac link function pointers 2140 * @hw: pointer to hardware structure 2141 **/ 2142 static void ixgbe_init_mac_link_ops_X550em_a(struct ixgbe_hw *hw) 2143 { 2144 struct ixgbe_mac_info *mac = &hw->mac; 2145 2146 switch (mac->ops.get_media_type(hw)) { 2147 case ixgbe_media_type_fiber: 2148 mac->ops.setup_fc = NULL; 2149 mac->ops.fc_autoneg = ixgbe_fc_autoneg_fiber_x550em_a; 2150 break; 2151 case ixgbe_media_type_copper: 2152 if (hw->device_id != IXGBE_DEV_ID_X550EM_A_1G_T && 2153 hw->device_id != IXGBE_DEV_ID_X550EM_A_1G_T_L) { 2154 mac->ops.setup_link = ixgbe_setup_mac_link_t_X550em; 2155 break; 2156 } 2157 mac->ops.fc_autoneg = ixgbe_fc_autoneg_sgmii_x550em_a; 2158 mac->ops.setup_fc = ixgbe_fc_autoneg_fw; 2159 mac->ops.setup_link = ixgbe_setup_sgmii_fw; 2160 mac->ops.check_link = ixgbe_check_mac_link_generic; 2161 break; 2162 case ixgbe_media_type_backplane: 2163 mac->ops.fc_autoneg = ixgbe_fc_autoneg_backplane_x550em_a; 2164 mac->ops.setup_fc = ixgbe_setup_fc_backplane_x550em_a; 2165 break; 2166 default: 2167 break; 2168 } 2169 } 2170 2171 /** ixgbe_init_mac_link_ops_X550em - init mac link function pointers 2172 * @hw: pointer to hardware structure 2173 **/ 2174 static void ixgbe_init_mac_link_ops_X550em(struct ixgbe_hw *hw) 2175 { 2176 struct ixgbe_mac_info *mac = &hw->mac; 2177 2178 mac->ops.setup_fc = ixgbe_setup_fc_x550em; 2179 2180 switch (mac->ops.get_media_type(hw)) { 2181 case ixgbe_media_type_fiber: 2182 /* CS4227 does not support autoneg, so disable the laser control 2183 * functions for SFP+ fiber 2184 */ 2185 mac->ops.disable_tx_laser = NULL; 2186 mac->ops.enable_tx_laser = NULL; 2187 mac->ops.flap_tx_laser = NULL; 2188 mac->ops.setup_link = ixgbe_setup_mac_link_multispeed_fiber; 2189 switch (hw->device_id) { 2190 case IXGBE_DEV_ID_X550EM_A_SFP_N: 2191 mac->ops.setup_mac_link = ixgbe_setup_mac_link_sfp_n; 2192 break; 2193 case IXGBE_DEV_ID_X550EM_A_SFP: 2194 mac->ops.setup_mac_link = 2195 ixgbe_setup_mac_link_sfp_x550a; 2196 break; 2197 default: 2198 mac->ops.setup_mac_link = 2199 ixgbe_setup_mac_link_sfp_x550em; 2200 break; 2201 } 2202 mac->ops.set_rate_select_speed = 2203 ixgbe_set_soft_rate_select_speed; 2204 break; 2205 case ixgbe_media_type_copper: 2206 if (hw->device_id == IXGBE_DEV_ID_X550EM_X_1G_T) 2207 break; 2208 mac->ops.setup_link = ixgbe_setup_mac_link_t_X550em; 2209 mac->ops.setup_fc = ixgbe_setup_fc_generic; 2210 mac->ops.check_link = ixgbe_check_link_t_X550em; 2211 break; 2212 case ixgbe_media_type_backplane: 2213 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_SGMII || 2214 hw->device_id == IXGBE_DEV_ID_X550EM_A_SGMII_L) 2215 mac->ops.setup_link = ixgbe_setup_sgmii; 2216 break; 2217 default: 2218 break; 2219 } 2220 2221 /* Additional modification for X550em_a devices */ 2222 if (hw->mac.type == ixgbe_mac_x550em_a) 2223 ixgbe_init_mac_link_ops_X550em_a(hw); 2224 } 2225 2226 /** ixgbe_setup_sfp_modules_X550em - Setup SFP module 2227 * @hw: pointer to hardware structure 2228 */ 2229 static s32 ixgbe_setup_sfp_modules_X550em(struct ixgbe_hw *hw) 2230 { 2231 s32 status; 2232 bool linear; 2233 2234 /* Check if SFP module is supported */ 2235 status = ixgbe_supported_sfp_modules_X550em(hw, &linear); 2236 if (status) 2237 return status; 2238 2239 ixgbe_init_mac_link_ops_X550em(hw); 2240 hw->phy.ops.reset = NULL; 2241 2242 return 0; 2243 } 2244 2245 /** ixgbe_get_link_capabilities_x550em - Determines link capabilities 2246 * @hw: pointer to hardware structure 2247 * @speed: pointer to link speed 2248 * @autoneg: true when autoneg or autotry is enabled 2249 **/ 2250 static s32 ixgbe_get_link_capabilities_X550em(struct ixgbe_hw *hw, 2251 ixgbe_link_speed *speed, 2252 bool *autoneg) 2253 { 2254 if (hw->phy.type == ixgbe_phy_fw) { 2255 *autoneg = true; 2256 *speed = hw->phy.speeds_supported; 2257 return 0; 2258 } 2259 2260 /* SFP */ 2261 if (hw->phy.media_type == ixgbe_media_type_fiber) { 2262 /* CS4227 SFP must not enable auto-negotiation */ 2263 *autoneg = false; 2264 2265 if (hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 || 2266 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1 || 2267 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 || 2268 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1) { 2269 *speed = IXGBE_LINK_SPEED_1GB_FULL; 2270 return 0; 2271 } 2272 2273 /* Link capabilities are based on SFP */ 2274 if (hw->phy.multispeed_fiber) 2275 *speed = IXGBE_LINK_SPEED_10GB_FULL | 2276 IXGBE_LINK_SPEED_1GB_FULL; 2277 else 2278 *speed = IXGBE_LINK_SPEED_10GB_FULL; 2279 } else { 2280 switch (hw->phy.type) { 2281 case ixgbe_phy_x550em_kx4: 2282 *speed = IXGBE_LINK_SPEED_1GB_FULL | 2283 IXGBE_LINK_SPEED_2_5GB_FULL | 2284 IXGBE_LINK_SPEED_10GB_FULL; 2285 break; 2286 case ixgbe_phy_x550em_xfi: 2287 *speed = IXGBE_LINK_SPEED_1GB_FULL | 2288 IXGBE_LINK_SPEED_10GB_FULL; 2289 break; 2290 case ixgbe_phy_ext_1g_t: 2291 case ixgbe_phy_sgmii: 2292 *speed = IXGBE_LINK_SPEED_1GB_FULL; 2293 break; 2294 case ixgbe_phy_x550em_kr: 2295 if (hw->mac.type == ixgbe_mac_x550em_a) { 2296 /* check different backplane modes */ 2297 if (hw->phy.nw_mng_if_sel & 2298 IXGBE_NW_MNG_IF_SEL_PHY_SPEED_2_5G) { 2299 *speed = IXGBE_LINK_SPEED_2_5GB_FULL; 2300 break; 2301 } else if (hw->device_id == 2302 IXGBE_DEV_ID_X550EM_A_KR_L) { 2303 *speed = IXGBE_LINK_SPEED_1GB_FULL; 2304 break; 2305 } 2306 } 2307 fallthrough; 2308 default: 2309 *speed = IXGBE_LINK_SPEED_10GB_FULL | 2310 IXGBE_LINK_SPEED_1GB_FULL; 2311 break; 2312 } 2313 *autoneg = true; 2314 } 2315 return 0; 2316 } 2317 2318 /** 2319 * ixgbe_get_lasi_ext_t_x550em - Determime external Base T PHY interrupt cause 2320 * @hw: pointer to hardware structure 2321 * @lsc: pointer to boolean flag which indicates whether external Base T 2322 * PHY interrupt is lsc 2323 * @is_overtemp: indicate whether an overtemp event encountered 2324 * 2325 * Determime if external Base T PHY interrupt cause is high temperature 2326 * failure alarm or link status change. 2327 **/ 2328 static s32 ixgbe_get_lasi_ext_t_x550em(struct ixgbe_hw *hw, bool *lsc, 2329 bool *is_overtemp) 2330 { 2331 u32 status; 2332 u16 reg; 2333 2334 *is_overtemp = false; 2335 *lsc = false; 2336 2337 /* Vendor alarm triggered */ 2338 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG, 2339 MDIO_MMD_VEND1, 2340 ®); 2341 2342 if (status || !(reg & IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN)) 2343 return status; 2344 2345 /* Vendor Auto-Neg alarm triggered or Global alarm 1 triggered */ 2346 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_FLAG, 2347 MDIO_MMD_VEND1, 2348 ®); 2349 2350 if (status || !(reg & (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN | 2351 IXGBE_MDIO_GLOBAL_ALARM_1_INT))) 2352 return status; 2353 2354 /* Global alarm triggered */ 2355 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_ALARM_1, 2356 MDIO_MMD_VEND1, 2357 ®); 2358 2359 if (status) 2360 return status; 2361 2362 /* If high temperature failure, then return over temp error and exit */ 2363 if (reg & IXGBE_MDIO_GLOBAL_ALM_1_HI_TMP_FAIL) { 2364 /* power down the PHY in case the PHY FW didn't already */ 2365 ixgbe_set_copper_phy_power(hw, false); 2366 *is_overtemp = true; 2367 return -EIO; 2368 } 2369 if (reg & IXGBE_MDIO_GLOBAL_ALM_1_DEV_FAULT) { 2370 /* device fault alarm triggered */ 2371 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_FAULT_MSG, 2372 MDIO_MMD_VEND1, 2373 ®); 2374 if (status) 2375 return status; 2376 2377 /* if device fault was due to high temp alarm handle and exit */ 2378 if (reg == IXGBE_MDIO_GLOBAL_FAULT_MSG_HI_TMP) { 2379 /* power down the PHY in case the PHY FW didn't */ 2380 ixgbe_set_copper_phy_power(hw, false); 2381 *is_overtemp = true; 2382 return -EIO; 2383 } 2384 } 2385 2386 /* Vendor alarm 2 triggered */ 2387 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG, 2388 MDIO_MMD_AN, ®); 2389 2390 if (status || !(reg & IXGBE_MDIO_GLOBAL_STD_ALM2_INT)) 2391 return status; 2392 2393 /* link connect/disconnect event occurred */ 2394 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM2, 2395 MDIO_MMD_AN, ®); 2396 2397 if (status) 2398 return status; 2399 2400 /* Indicate LSC */ 2401 if (reg & IXGBE_MDIO_AUTO_NEG_VEN_LSC) 2402 *lsc = true; 2403 2404 return 0; 2405 } 2406 2407 /** 2408 * ixgbe_enable_lasi_ext_t_x550em - Enable external Base T PHY interrupts 2409 * @hw: pointer to hardware structure 2410 * 2411 * Enable link status change and temperature failure alarm for the external 2412 * Base T PHY 2413 * 2414 * Returns PHY access status 2415 **/ 2416 static s32 ixgbe_enable_lasi_ext_t_x550em(struct ixgbe_hw *hw) 2417 { 2418 bool lsc, overtemp; 2419 u32 status; 2420 u16 reg; 2421 2422 /* Clear interrupt flags */ 2423 status = ixgbe_get_lasi_ext_t_x550em(hw, &lsc, &overtemp); 2424 2425 /* Enable link status change alarm */ 2426 2427 /* Enable the LASI interrupts on X552 devices to receive notifications 2428 * of the link configurations of the external PHY and correspondingly 2429 * support the configuration of the internal iXFI link, since iXFI does 2430 * not support auto-negotiation. This is not required for X553 devices 2431 * having KR support, which performs auto-negotiations and which is used 2432 * as the internal link to the external PHY. Hence adding a check here 2433 * to avoid enabling LASI interrupts for X553 devices. 2434 */ 2435 if (hw->mac.type != ixgbe_mac_x550em_a) { 2436 status = hw->phy.ops.read_reg(hw, 2437 IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK, 2438 MDIO_MMD_AN, ®); 2439 if (status) 2440 return status; 2441 2442 reg |= IXGBE_MDIO_PMA_TX_VEN_LASI_INT_EN; 2443 2444 status = hw->phy.ops.write_reg(hw, 2445 IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK, 2446 MDIO_MMD_AN, reg); 2447 if (status) 2448 return status; 2449 } 2450 2451 /* Enable high temperature failure and global fault alarms */ 2452 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK, 2453 MDIO_MMD_VEND1, 2454 ®); 2455 if (status) 2456 return status; 2457 2458 reg |= (IXGBE_MDIO_GLOBAL_INT_HI_TEMP_EN | 2459 IXGBE_MDIO_GLOBAL_INT_DEV_FAULT_EN); 2460 2461 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK, 2462 MDIO_MMD_VEND1, 2463 reg); 2464 if (status) 2465 return status; 2466 2467 /* Enable vendor Auto-Neg alarm and Global Interrupt Mask 1 alarm */ 2468 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK, 2469 MDIO_MMD_VEND1, 2470 ®); 2471 if (status) 2472 return status; 2473 2474 reg |= (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN | 2475 IXGBE_MDIO_GLOBAL_ALARM_1_INT); 2476 2477 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK, 2478 MDIO_MMD_VEND1, 2479 reg); 2480 if (status) 2481 return status; 2482 2483 /* Enable chip-wide vendor alarm */ 2484 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK, 2485 MDIO_MMD_VEND1, 2486 ®); 2487 if (status) 2488 return status; 2489 2490 reg |= IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN; 2491 2492 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK, 2493 MDIO_MMD_VEND1, 2494 reg); 2495 2496 return status; 2497 } 2498 2499 /** 2500 * ixgbe_handle_lasi_ext_t_x550em - Handle external Base T PHY interrupt 2501 * @hw: pointer to hardware structure 2502 * @is_overtemp: indicate whether an overtemp event encountered 2503 * 2504 * Handle external Base T PHY interrupt. If high temperature 2505 * failure alarm then return error, else if link status change 2506 * then setup internal/external PHY link 2507 **/ 2508 static s32 ixgbe_handle_lasi_ext_t_x550em(struct ixgbe_hw *hw, 2509 bool *is_overtemp) 2510 { 2511 struct ixgbe_phy_info *phy = &hw->phy; 2512 bool lsc; 2513 u32 status; 2514 2515 status = ixgbe_get_lasi_ext_t_x550em(hw, &lsc, is_overtemp); 2516 if (status) 2517 return status; 2518 2519 if (lsc && phy->ops.setup_internal_link) 2520 return phy->ops.setup_internal_link(hw); 2521 2522 return 0; 2523 } 2524 2525 /** 2526 * ixgbe_setup_kr_speed_x550em - Configure the KR PHY for link speed. 2527 * @hw: pointer to hardware structure 2528 * @speed: link speed 2529 * 2530 * Configures the integrated KR PHY. 2531 **/ 2532 static s32 ixgbe_setup_kr_speed_x550em(struct ixgbe_hw *hw, 2533 ixgbe_link_speed speed) 2534 { 2535 s32 status; 2536 u32 reg_val; 2537 2538 status = hw->mac.ops.read_iosf_sb_reg(hw, 2539 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id), 2540 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val); 2541 if (status) 2542 return status; 2543 2544 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE; 2545 reg_val &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR | 2546 IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX); 2547 2548 /* Advertise 10G support. */ 2549 if (speed & IXGBE_LINK_SPEED_10GB_FULL) 2550 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR; 2551 2552 /* Advertise 1G support. */ 2553 if (speed & IXGBE_LINK_SPEED_1GB_FULL) 2554 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX; 2555 2556 status = hw->mac.ops.write_iosf_sb_reg(hw, 2557 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id), 2558 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val); 2559 2560 if (hw->mac.type == ixgbe_mac_x550em_a) { 2561 /* Set lane mode to KR auto negotiation */ 2562 status = hw->mac.ops.read_iosf_sb_reg(hw, 2563 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id), 2564 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val); 2565 2566 if (status) 2567 return status; 2568 2569 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_MASK; 2570 reg_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_AN; 2571 reg_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_AN_EN; 2572 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN37_EN; 2573 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SGMII_EN; 2574 2575 status = hw->mac.ops.write_iosf_sb_reg(hw, 2576 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id), 2577 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val); 2578 } 2579 2580 return ixgbe_restart_an_internal_phy_x550em(hw); 2581 } 2582 2583 /** 2584 * ixgbe_setup_kr_x550em - Configure the KR PHY 2585 * @hw: pointer to hardware structure 2586 **/ 2587 static s32 ixgbe_setup_kr_x550em(struct ixgbe_hw *hw) 2588 { 2589 /* leave link alone for 2.5G */ 2590 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_2_5GB_FULL) 2591 return 0; 2592 2593 if (ixgbe_check_reset_blocked(hw)) 2594 return 0; 2595 2596 return ixgbe_setup_kr_speed_x550em(hw, hw->phy.autoneg_advertised); 2597 } 2598 2599 /** ixgbe_ext_phy_t_x550em_get_link - Get ext phy link status 2600 * @hw: address of hardware structure 2601 * @link_up: address of boolean to indicate link status 2602 * 2603 * Returns error code if unable to get link status. 2604 **/ 2605 static s32 ixgbe_ext_phy_t_x550em_get_link(struct ixgbe_hw *hw, bool *link_up) 2606 { 2607 u32 ret; 2608 u16 autoneg_status; 2609 2610 *link_up = false; 2611 2612 /* read this twice back to back to indicate current status */ 2613 ret = hw->phy.ops.read_reg(hw, MDIO_STAT1, MDIO_MMD_AN, 2614 &autoneg_status); 2615 if (ret) 2616 return ret; 2617 2618 ret = hw->phy.ops.read_reg(hw, MDIO_STAT1, MDIO_MMD_AN, 2619 &autoneg_status); 2620 if (ret) 2621 return ret; 2622 2623 *link_up = !!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS); 2624 2625 return 0; 2626 } 2627 2628 /** ixgbe_setup_internal_phy_t_x550em - Configure KR PHY to X557 link 2629 * @hw: point to hardware structure 2630 * 2631 * Configures the link between the integrated KR PHY and the external X557 PHY 2632 * The driver will call this function when it gets a link status change 2633 * interrupt from the X557 PHY. This function configures the link speed 2634 * between the PHYs to match the link speed of the BASE-T link. 2635 * 2636 * A return of a non-zero value indicates an error, and the base driver should 2637 * not report link up. 2638 **/ 2639 static s32 ixgbe_setup_internal_phy_t_x550em(struct ixgbe_hw *hw) 2640 { 2641 ixgbe_link_speed force_speed; 2642 bool link_up; 2643 u32 status; 2644 u16 speed; 2645 2646 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper) 2647 return -EIO; 2648 2649 if (!(hw->mac.type == ixgbe_mac_X550EM_x && 2650 !(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE))) { 2651 speed = IXGBE_LINK_SPEED_10GB_FULL | 2652 IXGBE_LINK_SPEED_1GB_FULL; 2653 return ixgbe_setup_kr_speed_x550em(hw, speed); 2654 } 2655 2656 /* If link is not up, then there is no setup necessary so return */ 2657 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up); 2658 if (status) 2659 return status; 2660 2661 if (!link_up) 2662 return 0; 2663 2664 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_STAT, 2665 MDIO_MMD_AN, 2666 &speed); 2667 if (status) 2668 return status; 2669 2670 /* If link is not still up, then no setup is necessary so return */ 2671 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up); 2672 if (status) 2673 return status; 2674 2675 if (!link_up) 2676 return 0; 2677 2678 /* clear everything but the speed and duplex bits */ 2679 speed &= IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_MASK; 2680 2681 switch (speed) { 2682 case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB_FULL: 2683 force_speed = IXGBE_LINK_SPEED_10GB_FULL; 2684 break; 2685 case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB_FULL: 2686 force_speed = IXGBE_LINK_SPEED_1GB_FULL; 2687 break; 2688 default: 2689 /* Internal PHY does not support anything else */ 2690 return -EINVAL; 2691 } 2692 2693 return ixgbe_setup_ixfi_x550em(hw, &force_speed); 2694 } 2695 2696 /** ixgbe_reset_phy_t_X550em - Performs X557 PHY reset and enables LASI 2697 * @hw: pointer to hardware structure 2698 **/ 2699 static s32 ixgbe_reset_phy_t_X550em(struct ixgbe_hw *hw) 2700 { 2701 s32 status; 2702 2703 status = ixgbe_reset_phy_generic(hw); 2704 2705 if (status) 2706 return status; 2707 2708 /* Configure Link Status Alarm and Temperature Threshold interrupts */ 2709 return ixgbe_enable_lasi_ext_t_x550em(hw); 2710 } 2711 2712 /** 2713 * ixgbe_led_on_t_x550em - Turns on the software controllable LEDs. 2714 * @hw: pointer to hardware structure 2715 * @led_idx: led number to turn on 2716 **/ 2717 static s32 ixgbe_led_on_t_x550em(struct ixgbe_hw *hw, u32 led_idx) 2718 { 2719 u16 phy_data; 2720 2721 if (led_idx >= IXGBE_X557_MAX_LED_INDEX) 2722 return -EINVAL; 2723 2724 /* To turn on the LED, set mode to ON. */ 2725 hw->phy.ops.read_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx, 2726 MDIO_MMD_VEND1, &phy_data); 2727 phy_data |= IXGBE_X557_LED_MANUAL_SET_MASK; 2728 hw->phy.ops.write_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx, 2729 MDIO_MMD_VEND1, phy_data); 2730 2731 return 0; 2732 } 2733 2734 /** 2735 * ixgbe_led_off_t_x550em - Turns off the software controllable LEDs. 2736 * @hw: pointer to hardware structure 2737 * @led_idx: led number to turn off 2738 **/ 2739 static s32 ixgbe_led_off_t_x550em(struct ixgbe_hw *hw, u32 led_idx) 2740 { 2741 u16 phy_data; 2742 2743 if (led_idx >= IXGBE_X557_MAX_LED_INDEX) 2744 return -EINVAL; 2745 2746 /* To turn on the LED, set mode to ON. */ 2747 hw->phy.ops.read_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx, 2748 MDIO_MMD_VEND1, &phy_data); 2749 phy_data &= ~IXGBE_X557_LED_MANUAL_SET_MASK; 2750 hw->phy.ops.write_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx, 2751 MDIO_MMD_VEND1, phy_data); 2752 2753 return 0; 2754 } 2755 2756 /** 2757 * ixgbe_set_fw_drv_ver_x550 - Sends driver version to firmware 2758 * @hw: pointer to the HW structure 2759 * @maj: driver version major number 2760 * @min: driver version minor number 2761 * @build: driver version build number 2762 * @sub: driver version sub build number 2763 * @len: length of driver_ver string 2764 * @driver_ver: driver string 2765 * 2766 * Sends driver version number to firmware through the manageability 2767 * block. On success return 0 2768 * else returns -EBUSY when encountering an error acquiring 2769 * semaphore, -EIO when command fails or -ENIVAL when incorrect 2770 * params passed. 2771 **/ 2772 static s32 ixgbe_set_fw_drv_ver_x550(struct ixgbe_hw *hw, u8 maj, u8 min, 2773 u8 build, u8 sub, u16 len, 2774 const char *driver_ver) 2775 { 2776 struct ixgbe_hic_drv_info2 fw_cmd; 2777 s32 ret_val; 2778 int i; 2779 2780 if (!len || !driver_ver || (len > sizeof(fw_cmd.driver_string))) 2781 return -EINVAL; 2782 2783 fw_cmd.hdr.cmd = FW_CEM_CMD_DRIVER_INFO; 2784 fw_cmd.hdr.buf_len = FW_CEM_CMD_DRIVER_INFO_LEN + len; 2785 fw_cmd.hdr.cmd_or_resp.cmd_resv = FW_CEM_CMD_RESERVED; 2786 fw_cmd.port_num = (u8)hw->bus.func; 2787 fw_cmd.ver_maj = maj; 2788 fw_cmd.ver_min = min; 2789 fw_cmd.ver_build = build; 2790 fw_cmd.ver_sub = sub; 2791 fw_cmd.hdr.checksum = 0; 2792 memcpy(fw_cmd.driver_string, driver_ver, len); 2793 fw_cmd.hdr.checksum = ixgbe_calculate_checksum((u8 *)&fw_cmd, 2794 (FW_CEM_HDR_LEN + fw_cmd.hdr.buf_len)); 2795 2796 for (i = 0; i <= FW_CEM_MAX_RETRIES; i++) { 2797 ret_val = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd, 2798 sizeof(fw_cmd), 2799 IXGBE_HI_COMMAND_TIMEOUT, 2800 true); 2801 if (ret_val) 2802 continue; 2803 2804 if (fw_cmd.hdr.cmd_or_resp.ret_status != 2805 FW_CEM_RESP_STATUS_SUCCESS) 2806 return -EIO; 2807 return 0; 2808 } 2809 2810 return ret_val; 2811 } 2812 2813 /** ixgbe_get_lcd_x550em - Determine lowest common denominator 2814 * @hw: pointer to hardware structure 2815 * @lcd_speed: pointer to lowest common link speed 2816 * 2817 * Determine lowest common link speed with link partner. 2818 **/ 2819 static s32 ixgbe_get_lcd_t_x550em(struct ixgbe_hw *hw, 2820 ixgbe_link_speed *lcd_speed) 2821 { 2822 u16 an_lp_status; 2823 s32 status; 2824 u16 word = hw->eeprom.ctrl_word_3; 2825 2826 *lcd_speed = IXGBE_LINK_SPEED_UNKNOWN; 2827 2828 status = hw->phy.ops.read_reg(hw, IXGBE_AUTO_NEG_LP_STATUS, 2829 MDIO_MMD_AN, 2830 &an_lp_status); 2831 if (status) 2832 return status; 2833 2834 /* If link partner advertised 1G, return 1G */ 2835 if (an_lp_status & IXGBE_AUTO_NEG_LP_1000BASE_CAP) { 2836 *lcd_speed = IXGBE_LINK_SPEED_1GB_FULL; 2837 return status; 2838 } 2839 2840 /* If 10G disabled for LPLU via NVM D10GMP, then return no valid LCD */ 2841 if ((hw->bus.lan_id && (word & NVM_INIT_CTRL_3_D10GMP_PORT1)) || 2842 (word & NVM_INIT_CTRL_3_D10GMP_PORT0)) 2843 return status; 2844 2845 /* Link partner not capable of lower speeds, return 10G */ 2846 *lcd_speed = IXGBE_LINK_SPEED_10GB_FULL; 2847 return status; 2848 } 2849 2850 /** 2851 * ixgbe_setup_fc_x550em - Set up flow control 2852 * @hw: pointer to hardware structure 2853 */ 2854 static s32 ixgbe_setup_fc_x550em(struct ixgbe_hw *hw) 2855 { 2856 bool pause, asm_dir; 2857 u32 reg_val; 2858 s32 rc = 0; 2859 2860 /* Validate the requested mode */ 2861 if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) { 2862 hw_err(hw, "ixgbe_fc_rx_pause not valid in strict IEEE mode\n"); 2863 return -EINVAL; 2864 } 2865 2866 /* 10gig parts do not have a word in the EEPROM to determine the 2867 * default flow control setting, so we explicitly set it to full. 2868 */ 2869 if (hw->fc.requested_mode == ixgbe_fc_default) 2870 hw->fc.requested_mode = ixgbe_fc_full; 2871 2872 /* Determine PAUSE and ASM_DIR bits. */ 2873 switch (hw->fc.requested_mode) { 2874 case ixgbe_fc_none: 2875 pause = false; 2876 asm_dir = false; 2877 break; 2878 case ixgbe_fc_tx_pause: 2879 pause = false; 2880 asm_dir = true; 2881 break; 2882 case ixgbe_fc_rx_pause: 2883 /* Rx Flow control is enabled and Tx Flow control is 2884 * disabled by software override. Since there really 2885 * isn't a way to advertise that we are capable of RX 2886 * Pause ONLY, we will advertise that we support both 2887 * symmetric and asymmetric Rx PAUSE, as such we fall 2888 * through to the fc_full statement. Later, we will 2889 * disable the adapter's ability to send PAUSE frames. 2890 */ 2891 fallthrough; 2892 case ixgbe_fc_full: 2893 pause = true; 2894 asm_dir = true; 2895 break; 2896 default: 2897 hw_err(hw, "Flow control param set incorrectly\n"); 2898 return -EIO; 2899 } 2900 2901 switch (hw->device_id) { 2902 case IXGBE_DEV_ID_X550EM_X_KR: 2903 case IXGBE_DEV_ID_X550EM_A_KR: 2904 case IXGBE_DEV_ID_X550EM_A_KR_L: 2905 rc = hw->mac.ops.read_iosf_sb_reg(hw, 2906 IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id), 2907 IXGBE_SB_IOSF_TARGET_KR_PHY, 2908 ®_val); 2909 if (rc) 2910 return rc; 2911 2912 reg_val &= ~(IXGBE_KRM_AN_CNTL_1_SYM_PAUSE | 2913 IXGBE_KRM_AN_CNTL_1_ASM_PAUSE); 2914 if (pause) 2915 reg_val |= IXGBE_KRM_AN_CNTL_1_SYM_PAUSE; 2916 if (asm_dir) 2917 reg_val |= IXGBE_KRM_AN_CNTL_1_ASM_PAUSE; 2918 rc = hw->mac.ops.write_iosf_sb_reg(hw, 2919 IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id), 2920 IXGBE_SB_IOSF_TARGET_KR_PHY, 2921 reg_val); 2922 2923 /* This device does not fully support AN. */ 2924 hw->fc.disable_fc_autoneg = true; 2925 break; 2926 case IXGBE_DEV_ID_X550EM_X_XFI: 2927 hw->fc.disable_fc_autoneg = true; 2928 break; 2929 default: 2930 break; 2931 } 2932 return rc; 2933 } 2934 2935 /** 2936 * ixgbe_fc_autoneg_backplane_x550em_a - Enable flow control IEEE clause 37 2937 * @hw: pointer to hardware structure 2938 **/ 2939 static void ixgbe_fc_autoneg_backplane_x550em_a(struct ixgbe_hw *hw) 2940 { 2941 u32 link_s1, lp_an_page_low, an_cntl_1; 2942 ixgbe_link_speed speed; 2943 s32 status = -EIO; 2944 bool link_up; 2945 2946 /* AN should have completed when the cable was plugged in. 2947 * Look for reasons to bail out. Bail out if: 2948 * - FC autoneg is disabled, or if 2949 * - link is not up. 2950 */ 2951 if (hw->fc.disable_fc_autoneg) { 2952 hw_err(hw, "Flow control autoneg is disabled"); 2953 goto out; 2954 } 2955 2956 hw->mac.ops.check_link(hw, &speed, &link_up, false); 2957 if (!link_up) { 2958 hw_err(hw, "The link is down"); 2959 goto out; 2960 } 2961 2962 /* Check at auto-negotiation has completed */ 2963 status = hw->mac.ops.read_iosf_sb_reg(hw, 2964 IXGBE_KRM_LINK_S1(hw->bus.lan_id), 2965 IXGBE_SB_IOSF_TARGET_KR_PHY, &link_s1); 2966 2967 if (status || (link_s1 & IXGBE_KRM_LINK_S1_MAC_AN_COMPLETE) == 0) { 2968 hw_dbg(hw, "Auto-Negotiation did not complete\n"); 2969 status = -EIO; 2970 goto out; 2971 } 2972 2973 /* Read the 10g AN autoc and LP ability registers and resolve 2974 * local flow control settings accordingly 2975 */ 2976 status = hw->mac.ops.read_iosf_sb_reg(hw, 2977 IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id), 2978 IXGBE_SB_IOSF_TARGET_KR_PHY, &an_cntl_1); 2979 2980 if (status) { 2981 hw_dbg(hw, "Auto-Negotiation did not complete\n"); 2982 goto out; 2983 } 2984 2985 status = hw->mac.ops.read_iosf_sb_reg(hw, 2986 IXGBE_KRM_LP_BASE_PAGE_HIGH(hw->bus.lan_id), 2987 IXGBE_SB_IOSF_TARGET_KR_PHY, &lp_an_page_low); 2988 2989 if (status) { 2990 hw_dbg(hw, "Auto-Negotiation did not complete\n"); 2991 goto out; 2992 } 2993 2994 status = ixgbe_negotiate_fc(hw, an_cntl_1, lp_an_page_low, 2995 IXGBE_KRM_AN_CNTL_1_SYM_PAUSE, 2996 IXGBE_KRM_AN_CNTL_1_ASM_PAUSE, 2997 IXGBE_KRM_LP_BASE_PAGE_HIGH_SYM_PAUSE, 2998 IXGBE_KRM_LP_BASE_PAGE_HIGH_ASM_PAUSE); 2999 3000 out: 3001 if (!status) { 3002 hw->fc.fc_was_autonegged = true; 3003 } else { 3004 hw->fc.fc_was_autonegged = false; 3005 hw->fc.current_mode = hw->fc.requested_mode; 3006 } 3007 } 3008 3009 /** 3010 * ixgbe_fc_autoneg_fiber_x550em_a - passthrough FC settings 3011 * @hw: pointer to hardware structure 3012 **/ 3013 static void ixgbe_fc_autoneg_fiber_x550em_a(struct ixgbe_hw *hw) 3014 { 3015 hw->fc.fc_was_autonegged = false; 3016 hw->fc.current_mode = hw->fc.requested_mode; 3017 } 3018 3019 /** ixgbe_enter_lplu_x550em - Transition to low power states 3020 * @hw: pointer to hardware structure 3021 * 3022 * Configures Low Power Link Up on transition to low power states 3023 * (from D0 to non-D0). Link is required to enter LPLU so avoid resetting 3024 * the X557 PHY immediately prior to entering LPLU. 3025 **/ 3026 static s32 ixgbe_enter_lplu_t_x550em(struct ixgbe_hw *hw) 3027 { 3028 u16 an_10g_cntl_reg, autoneg_reg, speed; 3029 s32 status; 3030 ixgbe_link_speed lcd_speed; 3031 u32 save_autoneg; 3032 bool link_up; 3033 3034 /* If blocked by MNG FW, then don't restart AN */ 3035 if (ixgbe_check_reset_blocked(hw)) 3036 return 0; 3037 3038 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up); 3039 if (status) 3040 return status; 3041 3042 status = hw->eeprom.ops.read(hw, NVM_INIT_CTRL_3, 3043 &hw->eeprom.ctrl_word_3); 3044 if (status) 3045 return status; 3046 3047 /* If link is down, LPLU disabled in NVM, WoL disabled, or 3048 * manageability disabled, then force link down by entering 3049 * low power mode. 3050 */ 3051 if (!link_up || !(hw->eeprom.ctrl_word_3 & NVM_INIT_CTRL_3_LPLU) || 3052 !(hw->wol_enabled || ixgbe_mng_present(hw))) 3053 return ixgbe_set_copper_phy_power(hw, false); 3054 3055 /* Determine LCD */ 3056 status = ixgbe_get_lcd_t_x550em(hw, &lcd_speed); 3057 if (status) 3058 return status; 3059 3060 /* If no valid LCD link speed, then force link down and exit. */ 3061 if (lcd_speed == IXGBE_LINK_SPEED_UNKNOWN) 3062 return ixgbe_set_copper_phy_power(hw, false); 3063 3064 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_STAT, 3065 MDIO_MMD_AN, 3066 &speed); 3067 if (status) 3068 return status; 3069 3070 /* If no link now, speed is invalid so take link down */ 3071 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up); 3072 if (status) 3073 return ixgbe_set_copper_phy_power(hw, false); 3074 3075 /* clear everything but the speed bits */ 3076 speed &= IXGBE_MDIO_AUTO_NEG_VEN_STAT_SPEED_MASK; 3077 3078 /* If current speed is already LCD, then exit. */ 3079 if (((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB) && 3080 (lcd_speed == IXGBE_LINK_SPEED_1GB_FULL)) || 3081 ((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB) && 3082 (lcd_speed == IXGBE_LINK_SPEED_10GB_FULL))) 3083 return status; 3084 3085 /* Clear AN completed indication */ 3086 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM, 3087 MDIO_MMD_AN, 3088 &autoneg_reg); 3089 if (status) 3090 return status; 3091 3092 status = hw->phy.ops.read_reg(hw, MDIO_AN_10GBT_CTRL, 3093 MDIO_MMD_AN, 3094 &an_10g_cntl_reg); 3095 if (status) 3096 return status; 3097 3098 status = hw->phy.ops.read_reg(hw, 3099 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG, 3100 MDIO_MMD_AN, 3101 &autoneg_reg); 3102 if (status) 3103 return status; 3104 3105 save_autoneg = hw->phy.autoneg_advertised; 3106 3107 /* Setup link at least common link speed */ 3108 status = hw->mac.ops.setup_link(hw, lcd_speed, false); 3109 3110 /* restore autoneg from before setting lplu speed */ 3111 hw->phy.autoneg_advertised = save_autoneg; 3112 3113 return status; 3114 } 3115 3116 /** 3117 * ixgbe_reset_phy_fw - Reset firmware-controlled PHYs 3118 * @hw: pointer to hardware structure 3119 */ 3120 static s32 ixgbe_reset_phy_fw(struct ixgbe_hw *hw) 3121 { 3122 u32 store[FW_PHY_ACT_DATA_COUNT] = { 0 }; 3123 s32 rc; 3124 3125 if (hw->phy.reset_disable || ixgbe_check_reset_blocked(hw)) 3126 return 0; 3127 3128 rc = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_PHY_SW_RESET, &store); 3129 if (rc) 3130 return rc; 3131 memset(store, 0, sizeof(store)); 3132 3133 rc = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_INIT_PHY, &store); 3134 if (rc) 3135 return rc; 3136 3137 return ixgbe_setup_fw_link(hw); 3138 } 3139 3140 /** 3141 * ixgbe_check_overtemp_fw - Check firmware-controlled PHYs for overtemp 3142 * @hw: pointer to hardware structure 3143 * 3144 * Return true when an overtemp event detected, otherwise false. 3145 */ 3146 static bool ixgbe_check_overtemp_fw(struct ixgbe_hw *hw) 3147 { 3148 u32 store[FW_PHY_ACT_DATA_COUNT] = { 0 }; 3149 s32 rc; 3150 3151 rc = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_GET_LINK_INFO, &store); 3152 if (rc) 3153 return false; 3154 3155 if (store[0] & FW_PHY_ACT_GET_LINK_INFO_TEMP) { 3156 ixgbe_shutdown_fw_phy(hw); 3157 return true; 3158 } 3159 return false; 3160 } 3161 3162 /** 3163 * ixgbe_read_mng_if_sel_x550em - Read NW_MNG_IF_SEL register 3164 * @hw: pointer to hardware structure 3165 * 3166 * Read NW_MNG_IF_SEL register and save field values. 3167 */ 3168 static void ixgbe_read_mng_if_sel_x550em(struct ixgbe_hw *hw) 3169 { 3170 /* Save NW management interface connected on board. This is used 3171 * to determine internal PHY mode. 3172 */ 3173 hw->phy.nw_mng_if_sel = IXGBE_READ_REG(hw, IXGBE_NW_MNG_IF_SEL); 3174 3175 /* If X552 (X550EM_a) and MDIO is connected to external PHY, then set 3176 * PHY address. This register field was has only been used for X552. 3177 */ 3178 if (hw->mac.type == ixgbe_mac_x550em_a && 3179 hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_MDIO_ACT) { 3180 hw->phy.mdio.prtad = FIELD_GET(IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD, 3181 hw->phy.nw_mng_if_sel); 3182 } 3183 } 3184 3185 /** ixgbe_init_phy_ops_X550em - PHY/SFP specific init 3186 * @hw: pointer to hardware structure 3187 * 3188 * Initialize any function pointers that were not able to be 3189 * set during init_shared_code because the PHY/SFP type was 3190 * not known. Perform the SFP init if necessary. 3191 **/ 3192 static s32 ixgbe_init_phy_ops_X550em(struct ixgbe_hw *hw) 3193 { 3194 struct ixgbe_phy_info *phy = &hw->phy; 3195 s32 ret_val; 3196 3197 hw->mac.ops.set_lan_id(hw); 3198 3199 ixgbe_read_mng_if_sel_x550em(hw); 3200 3201 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) { 3202 phy->phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM; 3203 ixgbe_setup_mux_ctl(hw); 3204 } 3205 3206 /* Identify the PHY or SFP module */ 3207 ret_val = phy->ops.identify(hw); 3208 if (ret_val == -EOPNOTSUPP || ret_val == -EFAULT) 3209 return ret_val; 3210 3211 /* Setup function pointers based on detected hardware */ 3212 ixgbe_init_mac_link_ops_X550em(hw); 3213 if (phy->sfp_type != ixgbe_sfp_type_unknown) 3214 phy->ops.reset = NULL; 3215 3216 /* Set functions pointers based on phy type */ 3217 switch (hw->phy.type) { 3218 case ixgbe_phy_x550em_kx4: 3219 phy->ops.setup_link = NULL; 3220 phy->ops.read_reg = ixgbe_read_phy_reg_x550em; 3221 phy->ops.write_reg = ixgbe_write_phy_reg_x550em; 3222 break; 3223 case ixgbe_phy_x550em_kr: 3224 phy->ops.setup_link = ixgbe_setup_kr_x550em; 3225 phy->ops.read_reg = ixgbe_read_phy_reg_x550em; 3226 phy->ops.write_reg = ixgbe_write_phy_reg_x550em; 3227 break; 3228 case ixgbe_phy_x550em_xfi: 3229 /* link is managed by HW */ 3230 phy->ops.setup_link = NULL; 3231 phy->ops.read_reg = ixgbe_read_phy_reg_x550em; 3232 phy->ops.write_reg = ixgbe_write_phy_reg_x550em; 3233 break; 3234 case ixgbe_phy_x550em_ext_t: 3235 /* Save NW management interface connected on board. This is used 3236 * to determine internal PHY mode 3237 */ 3238 phy->nw_mng_if_sel = IXGBE_READ_REG(hw, IXGBE_NW_MNG_IF_SEL); 3239 3240 /* If internal link mode is XFI, then setup iXFI internal link, 3241 * else setup KR now. 3242 */ 3243 phy->ops.setup_internal_link = 3244 ixgbe_setup_internal_phy_t_x550em; 3245 3246 /* setup SW LPLU only for first revision */ 3247 if (hw->mac.type == ixgbe_mac_X550EM_x && 3248 !(IXGBE_READ_REG(hw, IXGBE_FUSES0_GROUP(0)) & 3249 IXGBE_FUSES0_REV_MASK)) 3250 phy->ops.enter_lplu = ixgbe_enter_lplu_t_x550em; 3251 3252 phy->ops.handle_lasi = ixgbe_handle_lasi_ext_t_x550em; 3253 phy->ops.reset = ixgbe_reset_phy_t_X550em; 3254 break; 3255 case ixgbe_phy_sgmii: 3256 phy->ops.setup_link = NULL; 3257 break; 3258 case ixgbe_phy_fw: 3259 phy->ops.setup_link = ixgbe_setup_fw_link; 3260 phy->ops.reset = ixgbe_reset_phy_fw; 3261 break; 3262 case ixgbe_phy_ext_1g_t: 3263 phy->ops.setup_link = NULL; 3264 phy->ops.read_reg = NULL; 3265 phy->ops.write_reg = NULL; 3266 phy->ops.reset = NULL; 3267 break; 3268 default: 3269 break; 3270 } 3271 3272 return ret_val; 3273 } 3274 3275 /** ixgbe_get_media_type_X550em - Get media type 3276 * @hw: pointer to hardware structure 3277 * 3278 * Returns the media type (fiber, copper, backplane) 3279 * 3280 */ 3281 static enum ixgbe_media_type ixgbe_get_media_type_X550em(struct ixgbe_hw *hw) 3282 { 3283 enum ixgbe_media_type media_type; 3284 3285 /* Detect if there is a copper PHY attached. */ 3286 switch (hw->device_id) { 3287 case IXGBE_DEV_ID_X550EM_A_SGMII: 3288 case IXGBE_DEV_ID_X550EM_A_SGMII_L: 3289 hw->phy.type = ixgbe_phy_sgmii; 3290 fallthrough; 3291 case IXGBE_DEV_ID_X550EM_X_KR: 3292 case IXGBE_DEV_ID_X550EM_X_KX4: 3293 case IXGBE_DEV_ID_X550EM_X_XFI: 3294 case IXGBE_DEV_ID_X550EM_A_KR: 3295 case IXGBE_DEV_ID_X550EM_A_KR_L: 3296 media_type = ixgbe_media_type_backplane; 3297 break; 3298 case IXGBE_DEV_ID_X550EM_X_SFP: 3299 case IXGBE_DEV_ID_X550EM_A_SFP: 3300 case IXGBE_DEV_ID_X550EM_A_SFP_N: 3301 media_type = ixgbe_media_type_fiber; 3302 break; 3303 case IXGBE_DEV_ID_X550EM_X_1G_T: 3304 case IXGBE_DEV_ID_X550EM_X_10G_T: 3305 case IXGBE_DEV_ID_X550EM_A_10G_T: 3306 case IXGBE_DEV_ID_X550EM_A_1G_T: 3307 case IXGBE_DEV_ID_X550EM_A_1G_T_L: 3308 media_type = ixgbe_media_type_copper; 3309 break; 3310 default: 3311 media_type = ixgbe_media_type_unknown; 3312 break; 3313 } 3314 return media_type; 3315 } 3316 3317 /** ixgbe_init_ext_t_x550em - Start (unstall) the external Base T PHY. 3318 ** @hw: pointer to hardware structure 3319 **/ 3320 static s32 ixgbe_init_ext_t_x550em(struct ixgbe_hw *hw) 3321 { 3322 s32 status; 3323 u16 reg; 3324 3325 status = hw->phy.ops.read_reg(hw, 3326 IXGBE_MDIO_TX_VENDOR_ALARMS_3, 3327 MDIO_MMD_PMAPMD, 3328 ®); 3329 if (status) 3330 return status; 3331 3332 /* If PHY FW reset completed bit is set then this is the first 3333 * SW instance after a power on so the PHY FW must be un-stalled. 3334 */ 3335 if (reg & IXGBE_MDIO_TX_VENDOR_ALARMS_3_RST_MASK) { 3336 status = hw->phy.ops.read_reg(hw, 3337 IXGBE_MDIO_GLOBAL_RES_PR_10, 3338 MDIO_MMD_VEND1, 3339 ®); 3340 if (status) 3341 return status; 3342 3343 reg &= ~IXGBE_MDIO_POWER_UP_STALL; 3344 3345 status = hw->phy.ops.write_reg(hw, 3346 IXGBE_MDIO_GLOBAL_RES_PR_10, 3347 MDIO_MMD_VEND1, 3348 reg); 3349 if (status) 3350 return status; 3351 } 3352 3353 return status; 3354 } 3355 3356 /** 3357 * ixgbe_set_mdio_speed - Set MDIO clock speed 3358 * @hw: pointer to hardware structure 3359 */ 3360 static void ixgbe_set_mdio_speed(struct ixgbe_hw *hw) 3361 { 3362 u32 hlreg0; 3363 3364 switch (hw->device_id) { 3365 case IXGBE_DEV_ID_X550EM_X_10G_T: 3366 case IXGBE_DEV_ID_X550EM_A_SGMII: 3367 case IXGBE_DEV_ID_X550EM_A_SGMII_L: 3368 case IXGBE_DEV_ID_X550EM_A_10G_T: 3369 case IXGBE_DEV_ID_X550EM_A_SFP: 3370 /* Config MDIO clock speed before the first MDIO PHY access */ 3371 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0); 3372 hlreg0 &= ~IXGBE_HLREG0_MDCSPD; 3373 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0); 3374 break; 3375 case IXGBE_DEV_ID_X550EM_A_1G_T: 3376 case IXGBE_DEV_ID_X550EM_A_1G_T_L: 3377 /* Select fast MDIO clock speed for these devices */ 3378 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0); 3379 hlreg0 |= IXGBE_HLREG0_MDCSPD; 3380 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0); 3381 break; 3382 default: 3383 break; 3384 } 3385 } 3386 3387 /** ixgbe_reset_hw_X550em - Perform hardware reset 3388 ** @hw: pointer to hardware structure 3389 ** 3390 ** Resets the hardware by resetting the transmit and receive units, masks 3391 ** and clears all interrupts, perform a PHY reset, and perform a link (MAC) 3392 ** reset. 3393 **/ 3394 static s32 ixgbe_reset_hw_X550em(struct ixgbe_hw *hw) 3395 { 3396 ixgbe_link_speed link_speed; 3397 s32 status; 3398 u32 ctrl = 0; 3399 u32 i; 3400 bool link_up = false; 3401 u32 swfw_mask = hw->phy.phy_semaphore_mask; 3402 3403 /* Call adapter stop to disable Tx/Rx and clear interrupts */ 3404 status = hw->mac.ops.stop_adapter(hw); 3405 if (status) 3406 return status; 3407 3408 /* flush pending Tx transactions */ 3409 ixgbe_clear_tx_pending(hw); 3410 3411 /* set MDIO speed before talking to the PHY in case it's the 1st time */ 3412 ixgbe_set_mdio_speed(hw); 3413 3414 /* PHY ops must be identified and initialized prior to reset */ 3415 status = hw->phy.ops.init(hw); 3416 if (status == -EOPNOTSUPP || status == -EFAULT) 3417 return status; 3418 3419 /* start the external PHY */ 3420 if (hw->phy.type == ixgbe_phy_x550em_ext_t) { 3421 status = ixgbe_init_ext_t_x550em(hw); 3422 if (status) 3423 return status; 3424 } 3425 3426 /* Setup SFP module if there is one present. */ 3427 if (hw->phy.sfp_setup_needed) { 3428 status = hw->mac.ops.setup_sfp(hw); 3429 hw->phy.sfp_setup_needed = false; 3430 } 3431 3432 if (status == -EOPNOTSUPP) 3433 return status; 3434 3435 /* Reset PHY */ 3436 if (!hw->phy.reset_disable && hw->phy.ops.reset) 3437 hw->phy.ops.reset(hw); 3438 3439 mac_reset_top: 3440 /* Issue global reset to the MAC. Needs to be SW reset if link is up. 3441 * If link reset is used when link is up, it might reset the PHY when 3442 * mng is using it. If link is down or the flag to force full link 3443 * reset is set, then perform link reset. 3444 */ 3445 ctrl = IXGBE_CTRL_LNK_RST; 3446 3447 if (!hw->force_full_reset) { 3448 hw->mac.ops.check_link(hw, &link_speed, &link_up, false); 3449 if (link_up) 3450 ctrl = IXGBE_CTRL_RST; 3451 } 3452 3453 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask); 3454 if (status) { 3455 hw_dbg(hw, "semaphore failed with %d", status); 3456 return -EBUSY; 3457 } 3458 3459 ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL); 3460 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl); 3461 IXGBE_WRITE_FLUSH(hw); 3462 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 3463 usleep_range(1000, 1200); 3464 3465 /* Poll for reset bit to self-clear meaning reset is complete */ 3466 for (i = 0; i < 10; i++) { 3467 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL); 3468 if (!(ctrl & IXGBE_CTRL_RST_MASK)) 3469 break; 3470 udelay(1); 3471 } 3472 3473 if (ctrl & IXGBE_CTRL_RST_MASK) { 3474 status = -EIO; 3475 hw_dbg(hw, "Reset polling failed to complete.\n"); 3476 } 3477 3478 msleep(50); 3479 3480 /* Double resets are required for recovery from certain error 3481 * clear the multicast table. Also reset num_rar_entries to 128, 3482 * since we modify this value when programming the SAN MAC address. 3483 */ 3484 if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) { 3485 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED; 3486 goto mac_reset_top; 3487 } 3488 3489 /* Store the permanent mac address */ 3490 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr); 3491 3492 /* Store MAC address from RAR0, clear receive address registers, and 3493 * clear the multicast table. Also reset num_rar_entries to 128, 3494 * since we modify this value when programming the SAN MAC address. 3495 */ 3496 hw->mac.num_rar_entries = 128; 3497 hw->mac.ops.init_rx_addrs(hw); 3498 3499 ixgbe_set_mdio_speed(hw); 3500 3501 if (hw->device_id == IXGBE_DEV_ID_X550EM_X_SFP) 3502 ixgbe_setup_mux_ctl(hw); 3503 3504 return status; 3505 } 3506 3507 /** ixgbe_set_ethertype_anti_spoofing_X550 - Enable/Disable Ethertype 3508 * anti-spoofing 3509 * @hw: pointer to hardware structure 3510 * @enable: enable or disable switch for Ethertype anti-spoofing 3511 * @vf: Virtual Function pool - VF Pool to set for Ethertype anti-spoofing 3512 **/ 3513 static void ixgbe_set_ethertype_anti_spoofing_X550(struct ixgbe_hw *hw, 3514 bool enable, int vf) 3515 { 3516 int vf_target_reg = vf >> 3; 3517 int vf_target_shift = vf % 8 + IXGBE_SPOOF_ETHERTYPEAS_SHIFT; 3518 u32 pfvfspoof; 3519 3520 pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg)); 3521 if (enable) 3522 pfvfspoof |= BIT(vf_target_shift); 3523 else 3524 pfvfspoof &= ~BIT(vf_target_shift); 3525 3526 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof); 3527 } 3528 3529 /** ixgbe_set_source_address_pruning_X550 - Enable/Disbale src address pruning 3530 * @hw: pointer to hardware structure 3531 * @enable: enable or disable source address pruning 3532 * @pool: Rx pool to set source address pruning for 3533 **/ 3534 static void ixgbe_set_source_address_pruning_X550(struct ixgbe_hw *hw, 3535 bool enable, 3536 unsigned int pool) 3537 { 3538 u64 pfflp; 3539 3540 /* max rx pool is 63 */ 3541 if (pool > 63) 3542 return; 3543 3544 pfflp = (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPL); 3545 pfflp |= (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPH) << 32; 3546 3547 if (enable) 3548 pfflp |= (1ULL << pool); 3549 else 3550 pfflp &= ~(1ULL << pool); 3551 3552 IXGBE_WRITE_REG(hw, IXGBE_PFFLPL, (u32)pfflp); 3553 IXGBE_WRITE_REG(hw, IXGBE_PFFLPH, (u32)(pfflp >> 32)); 3554 } 3555 3556 /** 3557 * ixgbe_setup_fc_backplane_x550em_a - Set up flow control 3558 * @hw: pointer to hardware structure 3559 * 3560 * Called at init time to set up flow control. 3561 **/ 3562 static s32 ixgbe_setup_fc_backplane_x550em_a(struct ixgbe_hw *hw) 3563 { 3564 s32 status = 0; 3565 u32 an_cntl = 0; 3566 3567 /* Validate the requested mode */ 3568 if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) { 3569 hw_err(hw, "ixgbe_fc_rx_pause not valid in strict IEEE mode\n"); 3570 return -EINVAL; 3571 } 3572 3573 if (hw->fc.requested_mode == ixgbe_fc_default) 3574 hw->fc.requested_mode = ixgbe_fc_full; 3575 3576 /* Set up the 1G and 10G flow control advertisement registers so the 3577 * HW will be able to do FC autoneg once the cable is plugged in. If 3578 * we link at 10G, the 1G advertisement is harmless and vice versa. 3579 */ 3580 status = hw->mac.ops.read_iosf_sb_reg(hw, 3581 IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id), 3582 IXGBE_SB_IOSF_TARGET_KR_PHY, &an_cntl); 3583 3584 if (status) { 3585 hw_dbg(hw, "Auto-Negotiation did not complete\n"); 3586 return status; 3587 } 3588 3589 /* The possible values of fc.requested_mode are: 3590 * 0: Flow control is completely disabled 3591 * 1: Rx flow control is enabled (we can receive pause frames, 3592 * but not send pause frames). 3593 * 2: Tx flow control is enabled (we can send pause frames but 3594 * we do not support receiving pause frames). 3595 * 3: Both Rx and Tx flow control (symmetric) are enabled. 3596 * other: Invalid. 3597 */ 3598 switch (hw->fc.requested_mode) { 3599 case ixgbe_fc_none: 3600 /* Flow control completely disabled by software override. */ 3601 an_cntl &= ~(IXGBE_KRM_AN_CNTL_1_SYM_PAUSE | 3602 IXGBE_KRM_AN_CNTL_1_ASM_PAUSE); 3603 break; 3604 case ixgbe_fc_tx_pause: 3605 /* Tx Flow control is enabled, and Rx Flow control is 3606 * disabled by software override. 3607 */ 3608 an_cntl |= IXGBE_KRM_AN_CNTL_1_ASM_PAUSE; 3609 an_cntl &= ~IXGBE_KRM_AN_CNTL_1_SYM_PAUSE; 3610 break; 3611 case ixgbe_fc_rx_pause: 3612 /* Rx Flow control is enabled and Tx Flow control is 3613 * disabled by software override. Since there really 3614 * isn't a way to advertise that we are capable of RX 3615 * Pause ONLY, we will advertise that we support both 3616 * symmetric and asymmetric Rx PAUSE, as such we fall 3617 * through to the fc_full statement. Later, we will 3618 * disable the adapter's ability to send PAUSE frames. 3619 */ 3620 case ixgbe_fc_full: 3621 /* Flow control (both Rx and Tx) is enabled by SW override. */ 3622 an_cntl |= IXGBE_KRM_AN_CNTL_1_SYM_PAUSE | 3623 IXGBE_KRM_AN_CNTL_1_ASM_PAUSE; 3624 break; 3625 default: 3626 hw_err(hw, "Flow control param set incorrectly\n"); 3627 return -EIO; 3628 } 3629 3630 status = hw->mac.ops.write_iosf_sb_reg(hw, 3631 IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id), 3632 IXGBE_SB_IOSF_TARGET_KR_PHY, an_cntl); 3633 3634 /* Restart auto-negotiation. */ 3635 status = ixgbe_restart_an_internal_phy_x550em(hw); 3636 3637 return status; 3638 } 3639 3640 /** 3641 * ixgbe_set_mux - Set mux for port 1 access with CS4227 3642 * @hw: pointer to hardware structure 3643 * @state: set mux if 1, clear if 0 3644 */ 3645 static void ixgbe_set_mux(struct ixgbe_hw *hw, u8 state) 3646 { 3647 u32 esdp; 3648 3649 if (!hw->bus.lan_id) 3650 return; 3651 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); 3652 if (state) 3653 esdp |= IXGBE_ESDP_SDP1; 3654 else 3655 esdp &= ~IXGBE_ESDP_SDP1; 3656 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp); 3657 IXGBE_WRITE_FLUSH(hw); 3658 } 3659 3660 /** 3661 * ixgbe_acquire_swfw_sync_X550em - Acquire SWFW semaphore 3662 * @hw: pointer to hardware structure 3663 * @mask: Mask to specify which semaphore to acquire 3664 * 3665 * Acquires the SWFW semaphore and sets the I2C MUX 3666 */ 3667 static s32 ixgbe_acquire_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask) 3668 { 3669 s32 status; 3670 3671 status = ixgbe_acquire_swfw_sync_X540(hw, mask); 3672 if (status) 3673 return status; 3674 3675 if (mask & IXGBE_GSSR_I2C_MASK) 3676 ixgbe_set_mux(hw, 1); 3677 3678 return 0; 3679 } 3680 3681 /** 3682 * ixgbe_release_swfw_sync_X550em - Release SWFW semaphore 3683 * @hw: pointer to hardware structure 3684 * @mask: Mask to specify which semaphore to release 3685 * 3686 * Releases the SWFW semaphore and sets the I2C MUX 3687 */ 3688 static void ixgbe_release_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask) 3689 { 3690 if (mask & IXGBE_GSSR_I2C_MASK) 3691 ixgbe_set_mux(hw, 0); 3692 3693 ixgbe_release_swfw_sync_X540(hw, mask); 3694 } 3695 3696 /** 3697 * ixgbe_acquire_swfw_sync_x550em_a - Acquire SWFW semaphore 3698 * @hw: pointer to hardware structure 3699 * @mask: Mask to specify which semaphore to acquire 3700 * 3701 * Acquires the SWFW semaphore and get the shared PHY token as needed 3702 */ 3703 static s32 ixgbe_acquire_swfw_sync_x550em_a(struct ixgbe_hw *hw, u32 mask) 3704 { 3705 u32 hmask = mask & ~IXGBE_GSSR_TOKEN_SM; 3706 int retries = FW_PHY_TOKEN_RETRIES; 3707 s32 status; 3708 3709 while (--retries) { 3710 status = 0; 3711 if (hmask) 3712 status = ixgbe_acquire_swfw_sync_X540(hw, hmask); 3713 if (status) 3714 return status; 3715 if (!(mask & IXGBE_GSSR_TOKEN_SM)) 3716 return 0; 3717 3718 status = ixgbe_get_phy_token(hw); 3719 if (!status) 3720 return 0; 3721 if (hmask) 3722 ixgbe_release_swfw_sync_X540(hw, hmask); 3723 if (status != -EAGAIN) 3724 return status; 3725 msleep(FW_PHY_TOKEN_DELAY); 3726 } 3727 3728 return status; 3729 } 3730 3731 /** 3732 * ixgbe_release_swfw_sync_x550em_a - Release SWFW semaphore 3733 * @hw: pointer to hardware structure 3734 * @mask: Mask to specify which semaphore to release 3735 * 3736 * Release the SWFW semaphore and puts the shared PHY token as needed 3737 */ 3738 static void ixgbe_release_swfw_sync_x550em_a(struct ixgbe_hw *hw, u32 mask) 3739 { 3740 u32 hmask = mask & ~IXGBE_GSSR_TOKEN_SM; 3741 3742 if (mask & IXGBE_GSSR_TOKEN_SM) 3743 ixgbe_put_phy_token(hw); 3744 3745 if (hmask) 3746 ixgbe_release_swfw_sync_X540(hw, hmask); 3747 } 3748 3749 /** 3750 * ixgbe_read_phy_reg_x550a - Reads specified PHY register 3751 * @hw: pointer to hardware structure 3752 * @reg_addr: 32 bit address of PHY register to read 3753 * @device_type: 5 bit device type 3754 * @phy_data: Pointer to read data from PHY register 3755 * 3756 * Reads a value from a specified PHY register using the SWFW lock and PHY 3757 * Token. The PHY Token is needed since the MDIO is shared between to MAC 3758 * instances. 3759 */ 3760 static s32 ixgbe_read_phy_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr, 3761 u32 device_type, u16 *phy_data) 3762 { 3763 u32 mask = hw->phy.phy_semaphore_mask | IXGBE_GSSR_TOKEN_SM; 3764 s32 status; 3765 3766 if (hw->mac.ops.acquire_swfw_sync(hw, mask)) 3767 return -EBUSY; 3768 3769 status = hw->phy.ops.read_reg_mdi(hw, reg_addr, device_type, phy_data); 3770 3771 hw->mac.ops.release_swfw_sync(hw, mask); 3772 3773 return status; 3774 } 3775 3776 /** 3777 * ixgbe_write_phy_reg_x550a - Writes specified PHY register 3778 * @hw: pointer to hardware structure 3779 * @reg_addr: 32 bit PHY register to write 3780 * @device_type: 5 bit device type 3781 * @phy_data: Data to write to the PHY register 3782 * 3783 * Writes a value to specified PHY register using the SWFW lock and PHY Token. 3784 * The PHY Token is needed since the MDIO is shared between to MAC instances. 3785 */ 3786 static s32 ixgbe_write_phy_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr, 3787 u32 device_type, u16 phy_data) 3788 { 3789 u32 mask = hw->phy.phy_semaphore_mask | IXGBE_GSSR_TOKEN_SM; 3790 s32 status; 3791 3792 if (hw->mac.ops.acquire_swfw_sync(hw, mask)) 3793 return -EBUSY; 3794 3795 status = ixgbe_write_phy_reg_mdi(hw, reg_addr, device_type, phy_data); 3796 hw->mac.ops.release_swfw_sync(hw, mask); 3797 3798 return status; 3799 } 3800 3801 #define X550_COMMON_MAC \ 3802 .init_hw = &ixgbe_init_hw_generic, \ 3803 .start_hw = &ixgbe_start_hw_X540, \ 3804 .clear_hw_cntrs = &ixgbe_clear_hw_cntrs_generic, \ 3805 .enable_rx_dma = &ixgbe_enable_rx_dma_generic, \ 3806 .get_mac_addr = &ixgbe_get_mac_addr_generic, \ 3807 .get_device_caps = &ixgbe_get_device_caps_generic, \ 3808 .stop_adapter = &ixgbe_stop_adapter_generic, \ 3809 .set_lan_id = &ixgbe_set_lan_id_multi_port_pcie, \ 3810 .read_analog_reg8 = NULL, \ 3811 .write_analog_reg8 = NULL, \ 3812 .set_rxpba = &ixgbe_set_rxpba_generic, \ 3813 .check_link = &ixgbe_check_mac_link_generic, \ 3814 .blink_led_start = &ixgbe_blink_led_start_X540, \ 3815 .blink_led_stop = &ixgbe_blink_led_stop_X540, \ 3816 .set_rar = &ixgbe_set_rar_generic, \ 3817 .clear_rar = &ixgbe_clear_rar_generic, \ 3818 .set_vmdq = &ixgbe_set_vmdq_generic, \ 3819 .set_vmdq_san_mac = &ixgbe_set_vmdq_san_mac_generic, \ 3820 .clear_vmdq = &ixgbe_clear_vmdq_generic, \ 3821 .init_rx_addrs = &ixgbe_init_rx_addrs_generic, \ 3822 .update_mc_addr_list = &ixgbe_update_mc_addr_list_generic, \ 3823 .enable_mc = &ixgbe_enable_mc_generic, \ 3824 .disable_mc = &ixgbe_disable_mc_generic, \ 3825 .clear_vfta = &ixgbe_clear_vfta_generic, \ 3826 .set_vfta = &ixgbe_set_vfta_generic, \ 3827 .fc_enable = &ixgbe_fc_enable_generic, \ 3828 .set_fw_drv_ver = &ixgbe_set_fw_drv_ver_x550, \ 3829 .init_uta_tables = &ixgbe_init_uta_tables_generic, \ 3830 .set_mac_anti_spoofing = &ixgbe_set_mac_anti_spoofing, \ 3831 .set_vlan_anti_spoofing = &ixgbe_set_vlan_anti_spoofing, \ 3832 .set_source_address_pruning = \ 3833 &ixgbe_set_source_address_pruning_X550, \ 3834 .set_ethertype_anti_spoofing = \ 3835 &ixgbe_set_ethertype_anti_spoofing_X550, \ 3836 .disable_rx_buff = &ixgbe_disable_rx_buff_generic, \ 3837 .enable_rx_buff = &ixgbe_enable_rx_buff_generic, \ 3838 .get_thermal_sensor_data = NULL, \ 3839 .init_thermal_sensor_thresh = NULL, \ 3840 .fw_recovery_mode = &ixgbe_fw_recovery_mode_X550, \ 3841 .enable_rx = &ixgbe_enable_rx_generic, \ 3842 .disable_rx = &ixgbe_disable_rx_x550, \ 3843 3844 static const struct ixgbe_mac_operations mac_ops_X550 = { 3845 X550_COMMON_MAC 3846 .led_on = ixgbe_led_on_generic, 3847 .led_off = ixgbe_led_off_generic, 3848 .init_led_link_act = ixgbe_init_led_link_act_generic, 3849 .reset_hw = &ixgbe_reset_hw_X540, 3850 .get_media_type = &ixgbe_get_media_type_X540, 3851 .get_san_mac_addr = &ixgbe_get_san_mac_addr_generic, 3852 .get_wwn_prefix = &ixgbe_get_wwn_prefix_generic, 3853 .setup_link = &ixgbe_setup_mac_link_X540, 3854 .get_link_capabilities = &ixgbe_get_copper_link_capabilities_generic, 3855 .get_bus_info = &ixgbe_get_bus_info_generic, 3856 .setup_sfp = NULL, 3857 .acquire_swfw_sync = &ixgbe_acquire_swfw_sync_X540, 3858 .release_swfw_sync = &ixgbe_release_swfw_sync_X540, 3859 .init_swfw_sync = &ixgbe_init_swfw_sync_X540, 3860 .prot_autoc_read = prot_autoc_read_generic, 3861 .prot_autoc_write = prot_autoc_write_generic, 3862 .setup_fc = ixgbe_setup_fc_generic, 3863 .fc_autoneg = ixgbe_fc_autoneg, 3864 }; 3865 3866 static const struct ixgbe_mac_operations mac_ops_X550EM_x = { 3867 X550_COMMON_MAC 3868 .led_on = ixgbe_led_on_t_x550em, 3869 .led_off = ixgbe_led_off_t_x550em, 3870 .init_led_link_act = ixgbe_init_led_link_act_generic, 3871 .reset_hw = &ixgbe_reset_hw_X550em, 3872 .get_media_type = &ixgbe_get_media_type_X550em, 3873 .get_san_mac_addr = NULL, 3874 .get_wwn_prefix = NULL, 3875 .setup_link = &ixgbe_setup_mac_link_X540, 3876 .get_link_capabilities = &ixgbe_get_link_capabilities_X550em, 3877 .get_bus_info = &ixgbe_get_bus_info_X550em, 3878 .setup_sfp = ixgbe_setup_sfp_modules_X550em, 3879 .acquire_swfw_sync = &ixgbe_acquire_swfw_sync_X550em, 3880 .release_swfw_sync = &ixgbe_release_swfw_sync_X550em, 3881 .init_swfw_sync = &ixgbe_init_swfw_sync_X540, 3882 .setup_fc = NULL, /* defined later */ 3883 .fc_autoneg = ixgbe_fc_autoneg, 3884 .read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550, 3885 .write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550, 3886 }; 3887 3888 static const struct ixgbe_mac_operations mac_ops_X550EM_x_fw = { 3889 X550_COMMON_MAC 3890 .led_on = NULL, 3891 .led_off = NULL, 3892 .init_led_link_act = NULL, 3893 .reset_hw = &ixgbe_reset_hw_X550em, 3894 .get_media_type = &ixgbe_get_media_type_X550em, 3895 .get_san_mac_addr = NULL, 3896 .get_wwn_prefix = NULL, 3897 .setup_link = &ixgbe_setup_mac_link_X540, 3898 .get_link_capabilities = &ixgbe_get_link_capabilities_X550em, 3899 .get_bus_info = &ixgbe_get_bus_info_X550em, 3900 .setup_sfp = ixgbe_setup_sfp_modules_X550em, 3901 .acquire_swfw_sync = &ixgbe_acquire_swfw_sync_X550em, 3902 .release_swfw_sync = &ixgbe_release_swfw_sync_X550em, 3903 .init_swfw_sync = &ixgbe_init_swfw_sync_X540, 3904 .setup_fc = NULL, 3905 .fc_autoneg = ixgbe_fc_autoneg, 3906 .read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550, 3907 .write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550, 3908 }; 3909 3910 static const struct ixgbe_mac_operations mac_ops_x550em_a = { 3911 X550_COMMON_MAC 3912 .led_on = ixgbe_led_on_t_x550em, 3913 .led_off = ixgbe_led_off_t_x550em, 3914 .init_led_link_act = ixgbe_init_led_link_act_generic, 3915 .reset_hw = ixgbe_reset_hw_X550em, 3916 .get_media_type = ixgbe_get_media_type_X550em, 3917 .get_san_mac_addr = NULL, 3918 .get_wwn_prefix = NULL, 3919 .setup_link = &ixgbe_setup_mac_link_X540, 3920 .get_link_capabilities = ixgbe_get_link_capabilities_X550em, 3921 .get_bus_info = ixgbe_get_bus_info_X550em, 3922 .setup_sfp = ixgbe_setup_sfp_modules_X550em, 3923 .acquire_swfw_sync = ixgbe_acquire_swfw_sync_x550em_a, 3924 .release_swfw_sync = ixgbe_release_swfw_sync_x550em_a, 3925 .setup_fc = ixgbe_setup_fc_x550em, 3926 .fc_autoneg = ixgbe_fc_autoneg, 3927 .read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550a, 3928 .write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550a, 3929 }; 3930 3931 static const struct ixgbe_mac_operations mac_ops_x550em_a_fw = { 3932 X550_COMMON_MAC 3933 .led_on = ixgbe_led_on_generic, 3934 .led_off = ixgbe_led_off_generic, 3935 .init_led_link_act = ixgbe_init_led_link_act_generic, 3936 .reset_hw = ixgbe_reset_hw_X550em, 3937 .get_media_type = ixgbe_get_media_type_X550em, 3938 .get_san_mac_addr = NULL, 3939 .get_wwn_prefix = NULL, 3940 .setup_link = NULL, /* defined later */ 3941 .get_link_capabilities = ixgbe_get_link_capabilities_X550em, 3942 .get_bus_info = ixgbe_get_bus_info_X550em, 3943 .setup_sfp = ixgbe_setup_sfp_modules_X550em, 3944 .acquire_swfw_sync = ixgbe_acquire_swfw_sync_x550em_a, 3945 .release_swfw_sync = ixgbe_release_swfw_sync_x550em_a, 3946 .setup_fc = ixgbe_setup_fc_x550em, 3947 .fc_autoneg = ixgbe_fc_autoneg, 3948 .read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550a, 3949 .write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550a, 3950 }; 3951 3952 #define X550_COMMON_EEP \ 3953 .read = &ixgbe_read_ee_hostif_X550, \ 3954 .read_buffer = &ixgbe_read_ee_hostif_buffer_X550, \ 3955 .write = &ixgbe_write_ee_hostif_X550, \ 3956 .write_buffer = &ixgbe_write_ee_hostif_buffer_X550, \ 3957 .validate_checksum = &ixgbe_validate_eeprom_checksum_X550, \ 3958 .update_checksum = &ixgbe_update_eeprom_checksum_X550, \ 3959 .calc_checksum = &ixgbe_calc_eeprom_checksum_X550, \ 3960 3961 static const struct ixgbe_eeprom_operations eeprom_ops_X550 = { 3962 X550_COMMON_EEP 3963 .init_params = &ixgbe_init_eeprom_params_X550, 3964 }; 3965 3966 static const struct ixgbe_eeprom_operations eeprom_ops_X550EM_x = { 3967 X550_COMMON_EEP 3968 .init_params = &ixgbe_init_eeprom_params_X540, 3969 }; 3970 3971 #define X550_COMMON_PHY \ 3972 .identify_sfp = &ixgbe_identify_module_generic, \ 3973 .reset = NULL, \ 3974 .setup_link_speed = &ixgbe_setup_phy_link_speed_generic, \ 3975 .read_i2c_byte = &ixgbe_read_i2c_byte_generic, \ 3976 .write_i2c_byte = &ixgbe_write_i2c_byte_generic, \ 3977 .read_i2c_sff8472 = &ixgbe_read_i2c_sff8472_generic, \ 3978 .read_i2c_eeprom = &ixgbe_read_i2c_eeprom_generic, \ 3979 .write_i2c_eeprom = &ixgbe_write_i2c_eeprom_generic, \ 3980 .setup_link = &ixgbe_setup_phy_link_generic, \ 3981 .set_phy_power = NULL, 3982 3983 static const struct ixgbe_phy_operations phy_ops_X550 = { 3984 X550_COMMON_PHY 3985 .check_overtemp = &ixgbe_tn_check_overtemp, 3986 .init = NULL, 3987 .identify = &ixgbe_identify_phy_generic, 3988 .read_reg = &ixgbe_read_phy_reg_generic, 3989 .write_reg = &ixgbe_write_phy_reg_generic, 3990 }; 3991 3992 static const struct ixgbe_phy_operations phy_ops_X550EM_x = { 3993 X550_COMMON_PHY 3994 .check_overtemp = &ixgbe_tn_check_overtemp, 3995 .init = &ixgbe_init_phy_ops_X550em, 3996 .identify = &ixgbe_identify_phy_x550em, 3997 .read_reg = &ixgbe_read_phy_reg_generic, 3998 .write_reg = &ixgbe_write_phy_reg_generic, 3999 }; 4000 4001 static const struct ixgbe_phy_operations phy_ops_x550em_x_fw = { 4002 X550_COMMON_PHY 4003 .check_overtemp = NULL, 4004 .init = ixgbe_init_phy_ops_X550em, 4005 .identify = ixgbe_identify_phy_x550em, 4006 .read_reg = NULL, 4007 .write_reg = NULL, 4008 .read_reg_mdi = NULL, 4009 .write_reg_mdi = NULL, 4010 }; 4011 4012 static const struct ixgbe_phy_operations phy_ops_x550em_a = { 4013 X550_COMMON_PHY 4014 .check_overtemp = &ixgbe_tn_check_overtemp, 4015 .init = &ixgbe_init_phy_ops_X550em, 4016 .identify = &ixgbe_identify_phy_x550em, 4017 .read_reg = &ixgbe_read_phy_reg_x550a, 4018 .write_reg = &ixgbe_write_phy_reg_x550a, 4019 .read_reg_mdi = &ixgbe_read_phy_reg_mdi, 4020 .write_reg_mdi = &ixgbe_write_phy_reg_mdi, 4021 }; 4022 4023 static const struct ixgbe_phy_operations phy_ops_x550em_a_fw = { 4024 X550_COMMON_PHY 4025 .check_overtemp = ixgbe_check_overtemp_fw, 4026 .init = ixgbe_init_phy_ops_X550em, 4027 .identify = ixgbe_identify_phy_fw, 4028 .read_reg = NULL, 4029 .write_reg = NULL, 4030 .read_reg_mdi = NULL, 4031 .write_reg_mdi = NULL, 4032 }; 4033 4034 static const struct ixgbe_link_operations link_ops_x550em_x = { 4035 .read_link = &ixgbe_read_i2c_combined_generic, 4036 .read_link_unlocked = &ixgbe_read_i2c_combined_generic_unlocked, 4037 .write_link = &ixgbe_write_i2c_combined_generic, 4038 .write_link_unlocked = &ixgbe_write_i2c_combined_generic_unlocked, 4039 }; 4040 4041 static const u32 ixgbe_mvals_X550[IXGBE_MVALS_IDX_LIMIT] = { 4042 IXGBE_MVALS_INIT(X550) 4043 }; 4044 4045 static const u32 ixgbe_mvals_X550EM_x[IXGBE_MVALS_IDX_LIMIT] = { 4046 IXGBE_MVALS_INIT(X550EM_x) 4047 }; 4048 4049 static const u32 ixgbe_mvals_x550em_a[IXGBE_MVALS_IDX_LIMIT] = { 4050 IXGBE_MVALS_INIT(X550EM_a) 4051 }; 4052 4053 const struct ixgbe_info ixgbe_X550_info = { 4054 .mac = ixgbe_mac_X550, 4055 .get_invariants = &ixgbe_get_invariants_X540, 4056 .mac_ops = &mac_ops_X550, 4057 .eeprom_ops = &eeprom_ops_X550, 4058 .phy_ops = &phy_ops_X550, 4059 .mbx_ops = &mbx_ops_generic, 4060 .mvals = ixgbe_mvals_X550, 4061 }; 4062 4063 const struct ixgbe_info ixgbe_X550EM_x_info = { 4064 .mac = ixgbe_mac_X550EM_x, 4065 .get_invariants = &ixgbe_get_invariants_X550_x, 4066 .mac_ops = &mac_ops_X550EM_x, 4067 .eeprom_ops = &eeprom_ops_X550EM_x, 4068 .phy_ops = &phy_ops_X550EM_x, 4069 .mbx_ops = &mbx_ops_generic, 4070 .mvals = ixgbe_mvals_X550EM_x, 4071 .link_ops = &link_ops_x550em_x, 4072 }; 4073 4074 const struct ixgbe_info ixgbe_x550em_x_fw_info = { 4075 .mac = ixgbe_mac_X550EM_x, 4076 .get_invariants = ixgbe_get_invariants_X550_x_fw, 4077 .mac_ops = &mac_ops_X550EM_x_fw, 4078 .eeprom_ops = &eeprom_ops_X550EM_x, 4079 .phy_ops = &phy_ops_x550em_x_fw, 4080 .mbx_ops = &mbx_ops_generic, 4081 .mvals = ixgbe_mvals_X550EM_x, 4082 }; 4083 4084 const struct ixgbe_info ixgbe_x550em_a_info = { 4085 .mac = ixgbe_mac_x550em_a, 4086 .get_invariants = &ixgbe_get_invariants_X550_a, 4087 .mac_ops = &mac_ops_x550em_a, 4088 .eeprom_ops = &eeprom_ops_X550EM_x, 4089 .phy_ops = &phy_ops_x550em_a, 4090 .mbx_ops = &mbx_ops_generic, 4091 .mvals = ixgbe_mvals_x550em_a, 4092 }; 4093 4094 const struct ixgbe_info ixgbe_x550em_a_fw_info = { 4095 .mac = ixgbe_mac_x550em_a, 4096 .get_invariants = ixgbe_get_invariants_X550_a_fw, 4097 .mac_ops = &mac_ops_x550em_a_fw, 4098 .eeprom_ops = &eeprom_ops_X550EM_x, 4099 .phy_ops = &phy_ops_x550em_a_fw, 4100 .mbx_ops = &mbx_ops_generic, 4101 .mvals = ixgbe_mvals_x550em_a, 4102 }; 4103