1 /******************************************************************************* 2 * 3 * Intel 10 Gigabit PCI Express Linux driver 4 * Copyright(c) 1999 - 2015 Intel Corporation. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * The full GNU General Public License is included in this distribution in 16 * the file called "COPYING". 17 * 18 * Contact Information: 19 * Linux NICS <linux.nics@intel.com> 20 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 21 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 22 * 23 ******************************************************************************/ 24 #include "ixgbe_x540.h" 25 #include "ixgbe_type.h" 26 #include "ixgbe_common.h" 27 #include "ixgbe_phy.h" 28 29 /** ixgbe_setup_mux_ctl - Setup ESDP register for I2C mux control 30 * @hw: pointer to hardware structure 31 **/ 32 static void ixgbe_setup_mux_ctl(struct ixgbe_hw *hw) 33 { 34 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); 35 36 if (hw->bus.lan_id) { 37 esdp &= ~(IXGBE_ESDP_SDP1_NATIVE | IXGBE_ESDP_SDP1); 38 esdp |= IXGBE_ESDP_SDP1_DIR; 39 } 40 esdp &= ~(IXGBE_ESDP_SDP0_NATIVE | IXGBE_ESDP_SDP0_DIR); 41 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp); 42 IXGBE_WRITE_FLUSH(hw); 43 } 44 45 /** ixgbe_identify_phy_x550em - Get PHY type based on device id 46 * @hw: pointer to hardware structure 47 * 48 * Returns error code 49 */ 50 static s32 ixgbe_identify_phy_x550em(struct ixgbe_hw *hw) 51 { 52 switch (hw->device_id) { 53 case IXGBE_DEV_ID_X550EM_X_SFP: 54 /* set up for CS4227 usage */ 55 hw->phy.phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM; 56 ixgbe_setup_mux_ctl(hw); 57 58 return ixgbe_identify_module_generic(hw); 59 case IXGBE_DEV_ID_X550EM_X_KX4: 60 hw->phy.type = ixgbe_phy_x550em_kx4; 61 break; 62 case IXGBE_DEV_ID_X550EM_X_KR: 63 hw->phy.type = ixgbe_phy_x550em_kr; 64 break; 65 case IXGBE_DEV_ID_X550EM_X_1G_T: 66 case IXGBE_DEV_ID_X550EM_X_10G_T: 67 return ixgbe_identify_phy_generic(hw); 68 default: 69 break; 70 } 71 return 0; 72 } 73 74 static s32 ixgbe_read_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr, 75 u32 device_type, u16 *phy_data) 76 { 77 return IXGBE_NOT_IMPLEMENTED; 78 } 79 80 static s32 ixgbe_write_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr, 81 u32 device_type, u16 phy_data) 82 { 83 return IXGBE_NOT_IMPLEMENTED; 84 } 85 86 /** ixgbe_init_eeprom_params_X550 - Initialize EEPROM params 87 * @hw: pointer to hardware structure 88 * 89 * Initializes the EEPROM parameters ixgbe_eeprom_info within the 90 * ixgbe_hw struct in order to set up EEPROM access. 91 **/ 92 static s32 ixgbe_init_eeprom_params_X550(struct ixgbe_hw *hw) 93 { 94 struct ixgbe_eeprom_info *eeprom = &hw->eeprom; 95 u32 eec; 96 u16 eeprom_size; 97 98 if (eeprom->type == ixgbe_eeprom_uninitialized) { 99 eeprom->semaphore_delay = 10; 100 eeprom->type = ixgbe_flash; 101 102 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw)); 103 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >> 104 IXGBE_EEC_SIZE_SHIFT); 105 eeprom->word_size = 1 << (eeprom_size + 106 IXGBE_EEPROM_WORD_SIZE_SHIFT); 107 108 hw_dbg(hw, "Eeprom params: type = %d, size = %d\n", 109 eeprom->type, eeprom->word_size); 110 } 111 112 return 0; 113 } 114 115 /** 116 * ixgbe_iosf_wait - Wait for IOSF command completion 117 * @hw: pointer to hardware structure 118 * @ctrl: pointer to location to receive final IOSF control value 119 * 120 * Return: failing status on timeout 121 * 122 * Note: ctrl can be NULL if the IOSF control register value is not needed 123 */ 124 static s32 ixgbe_iosf_wait(struct ixgbe_hw *hw, u32 *ctrl) 125 { 126 u32 i, command; 127 128 /* Check every 10 usec to see if the address cycle completed. 129 * The SB IOSF BUSY bit will clear when the operation is 130 * complete. 131 */ 132 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { 133 command = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL); 134 if (!(command & IXGBE_SB_IOSF_CTRL_BUSY)) 135 break; 136 usleep_range(10, 20); 137 } 138 if (ctrl) 139 *ctrl = command; 140 if (i == IXGBE_MDIO_COMMAND_TIMEOUT) { 141 hw_dbg(hw, "IOSF wait timed out\n"); 142 return IXGBE_ERR_PHY; 143 } 144 145 return 0; 146 } 147 148 /** ixgbe_read_iosf_sb_reg_x550 - Writes a value to specified register of the 149 * IOSF device 150 * @hw: pointer to hardware structure 151 * @reg_addr: 32 bit PHY register to write 152 * @device_type: 3 bit device type 153 * @phy_data: Pointer to read data from the register 154 **/ 155 static s32 ixgbe_read_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr, 156 u32 device_type, u32 *data) 157 { 158 u32 gssr = IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_PHY0_SM; 159 u32 command, error; 160 s32 ret; 161 162 ret = hw->mac.ops.acquire_swfw_sync(hw, gssr); 163 if (ret) 164 return ret; 165 166 ret = ixgbe_iosf_wait(hw, NULL); 167 if (ret) 168 goto out; 169 170 command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) | 171 (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT)); 172 173 /* Write IOSF control register */ 174 IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command); 175 176 ret = ixgbe_iosf_wait(hw, &command); 177 178 if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) { 179 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >> 180 IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT; 181 hw_dbg(hw, "Failed to read, error %x\n", error); 182 return IXGBE_ERR_PHY; 183 } 184 185 if (!ret) 186 *data = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA); 187 188 out: 189 hw->mac.ops.release_swfw_sync(hw, gssr); 190 return ret; 191 } 192 193 /** ixgbe_read_ee_hostif_data_X550 - Read EEPROM word using a host interface 194 * command assuming that the semaphore is already obtained. 195 * @hw: pointer to hardware structure 196 * @offset: offset of word in the EEPROM to read 197 * @data: word read from the EEPROM 198 * 199 * Reads a 16 bit word from the EEPROM using the hostif. 200 **/ 201 static s32 ixgbe_read_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset, 202 u16 *data) 203 { 204 s32 status; 205 struct ixgbe_hic_read_shadow_ram buffer; 206 207 buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD; 208 buffer.hdr.req.buf_lenh = 0; 209 buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN; 210 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM; 211 212 /* convert offset from words to bytes */ 213 buffer.address = cpu_to_be32(offset * 2); 214 /* one word */ 215 buffer.length = cpu_to_be16(sizeof(u16)); 216 217 status = ixgbe_host_interface_command(hw, (u32 *)&buffer, 218 sizeof(buffer), 219 IXGBE_HI_COMMAND_TIMEOUT, false); 220 if (status) 221 return status; 222 223 *data = (u16)IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG, 224 FW_NVM_DATA_OFFSET); 225 226 return 0; 227 } 228 229 /** ixgbe_read_ee_hostif_buffer_X550- Read EEPROM word(s) using hostif 230 * @hw: pointer to hardware structure 231 * @offset: offset of word in the EEPROM to read 232 * @words: number of words 233 * @data: word(s) read from the EEPROM 234 * 235 * Reads a 16 bit word(s) from the EEPROM using the hostif. 236 **/ 237 static s32 ixgbe_read_ee_hostif_buffer_X550(struct ixgbe_hw *hw, 238 u16 offset, u16 words, u16 *data) 239 { 240 struct ixgbe_hic_read_shadow_ram buffer; 241 u32 current_word = 0; 242 u16 words_to_read; 243 s32 status; 244 u32 i; 245 246 /* Take semaphore for the entire operation. */ 247 status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 248 if (status) { 249 hw_dbg(hw, "EEPROM read buffer - semaphore failed\n"); 250 return status; 251 } 252 253 while (words) { 254 if (words > FW_MAX_READ_BUFFER_SIZE / 2) 255 words_to_read = FW_MAX_READ_BUFFER_SIZE / 2; 256 else 257 words_to_read = words; 258 259 buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD; 260 buffer.hdr.req.buf_lenh = 0; 261 buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN; 262 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM; 263 264 /* convert offset from words to bytes */ 265 buffer.address = cpu_to_be32((offset + current_word) * 2); 266 buffer.length = cpu_to_be16(words_to_read * 2); 267 268 status = ixgbe_host_interface_command(hw, (u32 *)&buffer, 269 sizeof(buffer), 270 IXGBE_HI_COMMAND_TIMEOUT, 271 false); 272 if (status) { 273 hw_dbg(hw, "Host interface command failed\n"); 274 goto out; 275 } 276 277 for (i = 0; i < words_to_read; i++) { 278 u32 reg = IXGBE_FLEX_MNG + (FW_NVM_DATA_OFFSET << 2) + 279 2 * i; 280 u32 value = IXGBE_READ_REG(hw, reg); 281 282 data[current_word] = (u16)(value & 0xffff); 283 current_word++; 284 i++; 285 if (i < words_to_read) { 286 value >>= 16; 287 data[current_word] = (u16)(value & 0xffff); 288 current_word++; 289 } 290 } 291 words -= words_to_read; 292 } 293 294 out: 295 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 296 return status; 297 } 298 299 /** ixgbe_checksum_ptr_x550 - Checksum one pointer region 300 * @hw: pointer to hardware structure 301 * @ptr: pointer offset in eeprom 302 * @size: size of section pointed by ptr, if 0 first word will be used as size 303 * @csum: address of checksum to update 304 * 305 * Returns error status for any failure 306 **/ 307 static s32 ixgbe_checksum_ptr_x550(struct ixgbe_hw *hw, u16 ptr, 308 u16 size, u16 *csum, u16 *buffer, 309 u32 buffer_size) 310 { 311 u16 buf[256]; 312 s32 status; 313 u16 length, bufsz, i, start; 314 u16 *local_buffer; 315 316 bufsz = sizeof(buf) / sizeof(buf[0]); 317 318 /* Read a chunk at the pointer location */ 319 if (!buffer) { 320 status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr, bufsz, buf); 321 if (status) { 322 hw_dbg(hw, "Failed to read EEPROM image\n"); 323 return status; 324 } 325 local_buffer = buf; 326 } else { 327 if (buffer_size < ptr) 328 return IXGBE_ERR_PARAM; 329 local_buffer = &buffer[ptr]; 330 } 331 332 if (size) { 333 start = 0; 334 length = size; 335 } else { 336 start = 1; 337 length = local_buffer[0]; 338 339 /* Skip pointer section if length is invalid. */ 340 if (length == 0xFFFF || length == 0 || 341 (ptr + length) >= hw->eeprom.word_size) 342 return 0; 343 } 344 345 if (buffer && ((u32)start + (u32)length > buffer_size)) 346 return IXGBE_ERR_PARAM; 347 348 for (i = start; length; i++, length--) { 349 if (i == bufsz && !buffer) { 350 ptr += bufsz; 351 i = 0; 352 if (length < bufsz) 353 bufsz = length; 354 355 /* Read a chunk at the pointer location */ 356 status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr, 357 bufsz, buf); 358 if (status) { 359 hw_dbg(hw, "Failed to read EEPROM image\n"); 360 return status; 361 } 362 } 363 *csum += local_buffer[i]; 364 } 365 return 0; 366 } 367 368 /** ixgbe_calc_checksum_X550 - Calculates and returns the checksum 369 * @hw: pointer to hardware structure 370 * @buffer: pointer to buffer containing calculated checksum 371 * @buffer_size: size of buffer 372 * 373 * Returns a negative error code on error, or the 16-bit checksum 374 **/ 375 static s32 ixgbe_calc_checksum_X550(struct ixgbe_hw *hw, u16 *buffer, 376 u32 buffer_size) 377 { 378 u16 eeprom_ptrs[IXGBE_EEPROM_LAST_WORD + 1]; 379 u16 *local_buffer; 380 s32 status; 381 u16 checksum = 0; 382 u16 pointer, i, size; 383 384 hw->eeprom.ops.init_params(hw); 385 386 if (!buffer) { 387 /* Read pointer area */ 388 status = ixgbe_read_ee_hostif_buffer_X550(hw, 0, 389 IXGBE_EEPROM_LAST_WORD + 1, 390 eeprom_ptrs); 391 if (status) { 392 hw_dbg(hw, "Failed to read EEPROM image\n"); 393 return status; 394 } 395 local_buffer = eeprom_ptrs; 396 } else { 397 if (buffer_size < IXGBE_EEPROM_LAST_WORD) 398 return IXGBE_ERR_PARAM; 399 local_buffer = buffer; 400 } 401 402 /* For X550 hardware include 0x0-0x41 in the checksum, skip the 403 * checksum word itself 404 */ 405 for (i = 0; i <= IXGBE_EEPROM_LAST_WORD; i++) 406 if (i != IXGBE_EEPROM_CHECKSUM) 407 checksum += local_buffer[i]; 408 409 /* Include all data from pointers 0x3, 0x6-0xE. This excludes the 410 * FW, PHY module, and PCIe Expansion/Option ROM pointers. 411 */ 412 for (i = IXGBE_PCIE_ANALOG_PTR_X550; i < IXGBE_FW_PTR; i++) { 413 if (i == IXGBE_PHY_PTR || i == IXGBE_OPTION_ROM_PTR) 414 continue; 415 416 pointer = local_buffer[i]; 417 418 /* Skip pointer section if the pointer is invalid. */ 419 if (pointer == 0xFFFF || pointer == 0 || 420 pointer >= hw->eeprom.word_size) 421 continue; 422 423 switch (i) { 424 case IXGBE_PCIE_GENERAL_PTR: 425 size = IXGBE_IXGBE_PCIE_GENERAL_SIZE; 426 break; 427 case IXGBE_PCIE_CONFIG0_PTR: 428 case IXGBE_PCIE_CONFIG1_PTR: 429 size = IXGBE_PCIE_CONFIG_SIZE; 430 break; 431 default: 432 size = 0; 433 break; 434 } 435 436 status = ixgbe_checksum_ptr_x550(hw, pointer, size, &checksum, 437 buffer, buffer_size); 438 if (status) 439 return status; 440 } 441 442 checksum = (u16)IXGBE_EEPROM_SUM - checksum; 443 444 return (s32)checksum; 445 } 446 447 /** ixgbe_calc_eeprom_checksum_X550 - Calculates and returns the checksum 448 * @hw: pointer to hardware structure 449 * 450 * Returns a negative error code on error, or the 16-bit checksum 451 **/ 452 static s32 ixgbe_calc_eeprom_checksum_X550(struct ixgbe_hw *hw) 453 { 454 return ixgbe_calc_checksum_X550(hw, NULL, 0); 455 } 456 457 /** ixgbe_read_ee_hostif_X550 - Read EEPROM word using a host interface command 458 * @hw: pointer to hardware structure 459 * @offset: offset of word in the EEPROM to read 460 * @data: word read from the EEPROM 461 * 462 * Reads a 16 bit word from the EEPROM using the hostif. 463 **/ 464 static s32 ixgbe_read_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset, u16 *data) 465 { 466 s32 status = 0; 467 468 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) == 0) { 469 status = ixgbe_read_ee_hostif_data_X550(hw, offset, data); 470 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 471 } else { 472 status = IXGBE_ERR_SWFW_SYNC; 473 } 474 475 return status; 476 } 477 478 /** ixgbe_validate_eeprom_checksum_X550 - Validate EEPROM checksum 479 * @hw: pointer to hardware structure 480 * @checksum_val: calculated checksum 481 * 482 * Performs checksum calculation and validates the EEPROM checksum. If the 483 * caller does not need checksum_val, the value can be NULL. 484 **/ 485 static s32 ixgbe_validate_eeprom_checksum_X550(struct ixgbe_hw *hw, 486 u16 *checksum_val) 487 { 488 s32 status; 489 u16 checksum; 490 u16 read_checksum = 0; 491 492 /* Read the first word from the EEPROM. If this times out or fails, do 493 * not continue or we could be in for a very long wait while every 494 * EEPROM read fails 495 */ 496 status = hw->eeprom.ops.read(hw, 0, &checksum); 497 if (status) { 498 hw_dbg(hw, "EEPROM read failed\n"); 499 return status; 500 } 501 502 status = hw->eeprom.ops.calc_checksum(hw); 503 if (status < 0) 504 return status; 505 506 checksum = (u16)(status & 0xffff); 507 508 status = ixgbe_read_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM, 509 &read_checksum); 510 if (status) 511 return status; 512 513 /* Verify read checksum from EEPROM is the same as 514 * calculated checksum 515 */ 516 if (read_checksum != checksum) { 517 status = IXGBE_ERR_EEPROM_CHECKSUM; 518 hw_dbg(hw, "Invalid EEPROM checksum"); 519 } 520 521 /* If the user cares, return the calculated checksum */ 522 if (checksum_val) 523 *checksum_val = checksum; 524 525 return status; 526 } 527 528 /** ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif 529 * @hw: pointer to hardware structure 530 * @offset: offset of word in the EEPROM to write 531 * @data: word write to the EEPROM 532 * 533 * Write a 16 bit word to the EEPROM using the hostif. 534 **/ 535 static s32 ixgbe_write_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset, 536 u16 data) 537 { 538 s32 status; 539 struct ixgbe_hic_write_shadow_ram buffer; 540 541 buffer.hdr.req.cmd = FW_WRITE_SHADOW_RAM_CMD; 542 buffer.hdr.req.buf_lenh = 0; 543 buffer.hdr.req.buf_lenl = FW_WRITE_SHADOW_RAM_LEN; 544 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM; 545 546 /* one word */ 547 buffer.length = cpu_to_be16(sizeof(u16)); 548 buffer.data = data; 549 buffer.address = cpu_to_be32(offset * 2); 550 551 status = ixgbe_host_interface_command(hw, (u32 *)&buffer, 552 sizeof(buffer), 553 IXGBE_HI_COMMAND_TIMEOUT, false); 554 return status; 555 } 556 557 /** ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif 558 * @hw: pointer to hardware structure 559 * @offset: offset of word in the EEPROM to write 560 * @data: word write to the EEPROM 561 * 562 * Write a 16 bit word to the EEPROM using the hostif. 563 **/ 564 static s32 ixgbe_write_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset, u16 data) 565 { 566 s32 status = 0; 567 568 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) == 0) { 569 status = ixgbe_write_ee_hostif_data_X550(hw, offset, data); 570 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 571 } else { 572 hw_dbg(hw, "write ee hostif failed to get semaphore"); 573 status = IXGBE_ERR_SWFW_SYNC; 574 } 575 576 return status; 577 } 578 579 /** ixgbe_update_flash_X550 - Instruct HW to copy EEPROM to Flash device 580 * @hw: pointer to hardware structure 581 * 582 * Issue a shadow RAM dump to FW to copy EEPROM from shadow RAM to the flash. 583 **/ 584 static s32 ixgbe_update_flash_X550(struct ixgbe_hw *hw) 585 { 586 s32 status = 0; 587 union ixgbe_hic_hdr2 buffer; 588 589 buffer.req.cmd = FW_SHADOW_RAM_DUMP_CMD; 590 buffer.req.buf_lenh = 0; 591 buffer.req.buf_lenl = FW_SHADOW_RAM_DUMP_LEN; 592 buffer.req.checksum = FW_DEFAULT_CHECKSUM; 593 594 status = ixgbe_host_interface_command(hw, (u32 *)&buffer, 595 sizeof(buffer), 596 IXGBE_HI_COMMAND_TIMEOUT, false); 597 return status; 598 } 599 600 /** ixgbe_disable_rx_x550 - Disable RX unit 601 * 602 * Enables the Rx DMA unit for x550 603 **/ 604 static void ixgbe_disable_rx_x550(struct ixgbe_hw *hw) 605 { 606 u32 rxctrl, pfdtxgswc; 607 s32 status; 608 struct ixgbe_hic_disable_rxen fw_cmd; 609 610 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL); 611 if (rxctrl & IXGBE_RXCTRL_RXEN) { 612 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC); 613 if (pfdtxgswc & IXGBE_PFDTXGSWC_VT_LBEN) { 614 pfdtxgswc &= ~IXGBE_PFDTXGSWC_VT_LBEN; 615 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc); 616 hw->mac.set_lben = true; 617 } else { 618 hw->mac.set_lben = false; 619 } 620 621 fw_cmd.hdr.cmd = FW_DISABLE_RXEN_CMD; 622 fw_cmd.hdr.buf_len = FW_DISABLE_RXEN_LEN; 623 fw_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM; 624 fw_cmd.port_number = (u8)hw->bus.lan_id; 625 626 status = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd, 627 sizeof(struct ixgbe_hic_disable_rxen), 628 IXGBE_HI_COMMAND_TIMEOUT, true); 629 630 /* If we fail - disable RX using register write */ 631 if (status) { 632 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL); 633 if (rxctrl & IXGBE_RXCTRL_RXEN) { 634 rxctrl &= ~IXGBE_RXCTRL_RXEN; 635 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl); 636 } 637 } 638 } 639 } 640 641 /** ixgbe_update_eeprom_checksum_X550 - Updates the EEPROM checksum and flash 642 * @hw: pointer to hardware structure 643 * 644 * After writing EEPROM to shadow RAM using EEWR register, software calculates 645 * checksum and updates the EEPROM and instructs the hardware to update 646 * the flash. 647 **/ 648 static s32 ixgbe_update_eeprom_checksum_X550(struct ixgbe_hw *hw) 649 { 650 s32 status; 651 u16 checksum = 0; 652 653 /* Read the first word from the EEPROM. If this times out or fails, do 654 * not continue or we could be in for a very long wait while every 655 * EEPROM read fails 656 */ 657 status = ixgbe_read_ee_hostif_X550(hw, 0, &checksum); 658 if (status) { 659 hw_dbg(hw, "EEPROM read failed\n"); 660 return status; 661 } 662 663 status = ixgbe_calc_eeprom_checksum_X550(hw); 664 if (status < 0) 665 return status; 666 667 checksum = (u16)(status & 0xffff); 668 669 status = ixgbe_write_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM, 670 checksum); 671 if (status) 672 return status; 673 674 status = ixgbe_update_flash_X550(hw); 675 676 return status; 677 } 678 679 /** ixgbe_write_ee_hostif_buffer_X550 - Write EEPROM word(s) using hostif 680 * @hw: pointer to hardware structure 681 * @offset: offset of word in the EEPROM to write 682 * @words: number of words 683 * @data: word(s) write to the EEPROM 684 * 685 * 686 * Write a 16 bit word(s) to the EEPROM using the hostif. 687 **/ 688 static s32 ixgbe_write_ee_hostif_buffer_X550(struct ixgbe_hw *hw, 689 u16 offset, u16 words, 690 u16 *data) 691 { 692 s32 status = 0; 693 u32 i = 0; 694 695 /* Take semaphore for the entire operation. */ 696 status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 697 if (status) { 698 hw_dbg(hw, "EEPROM write buffer - semaphore failed\n"); 699 return status; 700 } 701 702 for (i = 0; i < words; i++) { 703 status = ixgbe_write_ee_hostif_data_X550(hw, offset + i, 704 data[i]); 705 if (status) { 706 hw_dbg(hw, "Eeprom buffered write failed\n"); 707 break; 708 } 709 } 710 711 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 712 713 return status; 714 } 715 716 /** ixgbe_write_iosf_sb_reg_x550 - Writes a value to specified register of the 717 * IOSF device 718 * 719 * @hw: pointer to hardware structure 720 * @reg_addr: 32 bit PHY register to write 721 * @device_type: 3 bit device type 722 * @data: Data to write to the register 723 **/ 724 static s32 ixgbe_write_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr, 725 u32 device_type, u32 data) 726 { 727 u32 gssr = IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_PHY0_SM; 728 u32 command, error; 729 s32 ret; 730 731 ret = hw->mac.ops.acquire_swfw_sync(hw, gssr); 732 if (ret) 733 return ret; 734 735 ret = ixgbe_iosf_wait(hw, NULL); 736 if (ret) 737 goto out; 738 739 command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) | 740 (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT)); 741 742 /* Write IOSF control register */ 743 IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command); 744 745 /* Write IOSF data register */ 746 IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA, data); 747 748 ret = ixgbe_iosf_wait(hw, &command); 749 750 if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) { 751 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >> 752 IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT; 753 hw_dbg(hw, "Failed to write, error %x\n", error); 754 return IXGBE_ERR_PHY; 755 } 756 757 out: 758 hw->mac.ops.release_swfw_sync(hw, gssr); 759 return ret; 760 } 761 762 /** ixgbe_setup_ixfi_x550em - Configure the KR PHY for iXFI mode. 763 * @hw: pointer to hardware structure 764 * @speed: the link speed to force 765 * 766 * Configures the integrated KR PHY to use iXFI mode. Used to connect an 767 * internal and external PHY at a specific speed, without autonegotiation. 768 **/ 769 static s32 ixgbe_setup_ixfi_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed) 770 { 771 s32 status; 772 u32 reg_val; 773 774 /* Disable AN and force speed to 10G Serial. */ 775 status = ixgbe_read_iosf_sb_reg_x550(hw, 776 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id), 777 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val); 778 if (status) 779 return status; 780 781 reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE; 782 reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK; 783 784 /* Select forced link speed for internal PHY. */ 785 switch (*speed) { 786 case IXGBE_LINK_SPEED_10GB_FULL: 787 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G; 788 break; 789 case IXGBE_LINK_SPEED_1GB_FULL: 790 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G; 791 break; 792 default: 793 /* Other link speeds are not supported by internal KR PHY. */ 794 return IXGBE_ERR_LINK_SETUP; 795 } 796 797 status = ixgbe_write_iosf_sb_reg_x550(hw, 798 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id), 799 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val); 800 if (status) 801 return status; 802 803 /* Disable training protocol FSM. */ 804 status = ixgbe_read_iosf_sb_reg_x550(hw, 805 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id), 806 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val); 807 if (status) 808 return status; 809 810 reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_CONV_WO_PROTOCOL; 811 status = ixgbe_write_iosf_sb_reg_x550(hw, 812 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id), 813 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val); 814 if (status) 815 return status; 816 817 /* Disable Flex from training TXFFE. */ 818 status = ixgbe_read_iosf_sb_reg_x550(hw, 819 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id), 820 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val); 821 if (status) 822 return status; 823 824 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN; 825 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN; 826 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN; 827 status = ixgbe_write_iosf_sb_reg_x550(hw, 828 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id), 829 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val); 830 if (status) 831 return status; 832 833 status = ixgbe_read_iosf_sb_reg_x550(hw, 834 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id), 835 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val); 836 if (status) 837 return status; 838 839 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN; 840 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN; 841 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN; 842 status = ixgbe_write_iosf_sb_reg_x550(hw, 843 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id), 844 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val); 845 if (status) 846 return status; 847 848 /* Enable override for coefficients. */ 849 status = ixgbe_read_iosf_sb_reg_x550(hw, 850 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id), 851 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val); 852 if (status) 853 return status; 854 855 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_OVRRD_EN; 856 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CZERO_EN; 857 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CPLUS1_OVRRD_EN; 858 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CMINUS1_OVRRD_EN; 859 status = ixgbe_write_iosf_sb_reg_x550(hw, 860 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id), 861 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val); 862 if (status) 863 return status; 864 865 /* Toggle port SW reset by AN reset. */ 866 status = ixgbe_read_iosf_sb_reg_x550(hw, 867 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id), 868 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val); 869 if (status) 870 return status; 871 872 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART; 873 status = ixgbe_write_iosf_sb_reg_x550(hw, 874 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id), 875 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val); 876 877 return status; 878 } 879 880 /** 881 * ixgbe_setup_mac_link_t_X550em - Sets the auto advertised link speed 882 * @hw: pointer to hardware structure 883 * @speed: new link speed 884 * @autoneg_wait_to_complete: true when waiting for completion is needed 885 * 886 * Setup internal/external PHY link speed based on link speed, then set 887 * external PHY auto advertised link speed. 888 * 889 * Returns error status for any failure 890 **/ 891 static s32 ixgbe_setup_mac_link_t_X550em(struct ixgbe_hw *hw, 892 ixgbe_link_speed speed, 893 bool autoneg_wait) 894 { 895 s32 status; 896 ixgbe_link_speed force_speed; 897 898 /* Setup internal/external PHY link speed to iXFI (10G), unless 899 * only 1G is auto advertised then setup KX link. 900 */ 901 if (speed & IXGBE_LINK_SPEED_10GB_FULL) 902 force_speed = IXGBE_LINK_SPEED_10GB_FULL; 903 else 904 force_speed = IXGBE_LINK_SPEED_1GB_FULL; 905 906 /* If internal link mode is XFI, then setup XFI internal link. */ 907 if (!(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) { 908 status = ixgbe_setup_ixfi_x550em(hw, &force_speed); 909 910 if (status) 911 return status; 912 } 913 914 return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait); 915 } 916 917 /** ixgbe_check_link_t_X550em - Determine link and speed status 918 * @hw: pointer to hardware structure 919 * @speed: pointer to link speed 920 * @link_up: true when link is up 921 * @link_up_wait_to_complete: bool used to wait for link up or not 922 * 923 * Check that both the MAC and X557 external PHY have link. 924 **/ 925 static s32 ixgbe_check_link_t_X550em(struct ixgbe_hw *hw, 926 ixgbe_link_speed *speed, 927 bool *link_up, 928 bool link_up_wait_to_complete) 929 { 930 u32 status; 931 u16 autoneg_status; 932 933 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper) 934 return IXGBE_ERR_CONFIG; 935 936 status = ixgbe_check_mac_link_generic(hw, speed, link_up, 937 link_up_wait_to_complete); 938 939 /* If check link fails or MAC link is not up, then return */ 940 if (status || !(*link_up)) 941 return status; 942 943 /* MAC link is up, so check external PHY link. 944 * Read this twice back to back to indicate current status. 945 */ 946 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS, 947 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 948 &autoneg_status); 949 if (status) 950 return status; 951 952 /* If external PHY link is not up, then indicate link not up */ 953 if (!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS)) 954 *link_up = false; 955 956 return 0; 957 } 958 959 /** ixgbe_init_mac_link_ops_X550em - init mac link function pointers 960 * @hw: pointer to hardware structure 961 **/ 962 static void ixgbe_init_mac_link_ops_X550em(struct ixgbe_hw *hw) 963 { 964 struct ixgbe_mac_info *mac = &hw->mac; 965 966 switch (mac->ops.get_media_type(hw)) { 967 case ixgbe_media_type_fiber: 968 /* CS4227 does not support autoneg, so disable the laser control 969 * functions for SFP+ fiber 970 */ 971 mac->ops.disable_tx_laser = NULL; 972 mac->ops.enable_tx_laser = NULL; 973 mac->ops.flap_tx_laser = NULL; 974 break; 975 case ixgbe_media_type_copper: 976 mac->ops.setup_link = ixgbe_setup_mac_link_t_X550em; 977 mac->ops.check_link = ixgbe_check_link_t_X550em; 978 break; 979 default: 980 break; 981 } 982 } 983 984 /** ixgbe_setup_sfp_modules_X550em - Setup SFP module 985 * @hw: pointer to hardware structure 986 */ 987 static s32 ixgbe_setup_sfp_modules_X550em(struct ixgbe_hw *hw) 988 { 989 bool setup_linear; 990 u16 reg_slice, edc_mode; 991 s32 ret_val; 992 993 switch (hw->phy.sfp_type) { 994 case ixgbe_sfp_type_unknown: 995 return 0; 996 case ixgbe_sfp_type_not_present: 997 return IXGBE_ERR_SFP_NOT_PRESENT; 998 case ixgbe_sfp_type_da_cu_core0: 999 case ixgbe_sfp_type_da_cu_core1: 1000 setup_linear = true; 1001 break; 1002 case ixgbe_sfp_type_srlr_core0: 1003 case ixgbe_sfp_type_srlr_core1: 1004 case ixgbe_sfp_type_da_act_lmt_core0: 1005 case ixgbe_sfp_type_da_act_lmt_core1: 1006 case ixgbe_sfp_type_1g_sx_core0: 1007 case ixgbe_sfp_type_1g_sx_core1: 1008 setup_linear = false; 1009 break; 1010 default: 1011 return IXGBE_ERR_SFP_NOT_SUPPORTED; 1012 } 1013 1014 ixgbe_init_mac_link_ops_X550em(hw); 1015 hw->phy.ops.reset = NULL; 1016 1017 /* The CS4227 slice address is the base address + the port-pair reg 1018 * offset. I.e. Slice 0 = 0x12B0 and slice 1 = 0x22B0. 1019 */ 1020 reg_slice = IXGBE_CS4227_SPARE24_LSB + (hw->bus.lan_id << 12); 1021 1022 if (setup_linear) 1023 edc_mode = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1; 1024 else 1025 edc_mode = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1; 1026 1027 /* Configure CS4227 for connection type. */ 1028 ret_val = hw->phy.ops.write_i2c_combined(hw, IXGBE_CS4227, reg_slice, 1029 edc_mode); 1030 1031 if (ret_val) 1032 ret_val = hw->phy.ops.write_i2c_combined(hw, 0x80, reg_slice, 1033 edc_mode); 1034 1035 return ret_val; 1036 } 1037 1038 /** ixgbe_get_link_capabilities_x550em - Determines link capabilities 1039 * @hw: pointer to hardware structure 1040 * @speed: pointer to link speed 1041 * @autoneg: true when autoneg or autotry is enabled 1042 **/ 1043 static s32 ixgbe_get_link_capabilities_X550em(struct ixgbe_hw *hw, 1044 ixgbe_link_speed *speed, 1045 bool *autoneg) 1046 { 1047 /* SFP */ 1048 if (hw->phy.media_type == ixgbe_media_type_fiber) { 1049 /* CS4227 SFP must not enable auto-negotiation */ 1050 *autoneg = false; 1051 1052 if (hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 || 1053 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1) { 1054 *speed = IXGBE_LINK_SPEED_1GB_FULL; 1055 return 0; 1056 } 1057 1058 /* Link capabilities are based on SFP */ 1059 if (hw->phy.multispeed_fiber) 1060 *speed = IXGBE_LINK_SPEED_10GB_FULL | 1061 IXGBE_LINK_SPEED_1GB_FULL; 1062 else 1063 *speed = IXGBE_LINK_SPEED_10GB_FULL; 1064 } else { 1065 *speed = IXGBE_LINK_SPEED_10GB_FULL | 1066 IXGBE_LINK_SPEED_1GB_FULL; 1067 *autoneg = true; 1068 } 1069 return 0; 1070 } 1071 1072 /** 1073 * ixgbe_get_lasi_ext_t_x550em - Determime external Base T PHY interrupt cause 1074 * @hw: pointer to hardware structure 1075 * @lsc: pointer to boolean flag which indicates whether external Base T 1076 * PHY interrupt is lsc 1077 * 1078 * Determime if external Base T PHY interrupt cause is high temperature 1079 * failure alarm or link status change. 1080 * 1081 * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature 1082 * failure alarm, else return PHY access status. 1083 **/ 1084 static s32 ixgbe_get_lasi_ext_t_x550em(struct ixgbe_hw *hw, bool *lsc) 1085 { 1086 u32 status; 1087 u16 reg; 1088 1089 *lsc = false; 1090 1091 /* Vendor alarm triggered */ 1092 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG, 1093 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 1094 ®); 1095 1096 if (status || !(reg & IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN)) 1097 return status; 1098 1099 /* Vendor Auto-Neg alarm triggered or Global alarm 1 triggered */ 1100 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_FLAG, 1101 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 1102 ®); 1103 1104 if (status || !(reg & (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN | 1105 IXGBE_MDIO_GLOBAL_ALARM_1_INT))) 1106 return status; 1107 1108 /* High temperature failure alarm triggered */ 1109 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_ALARM_1, 1110 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 1111 ®); 1112 1113 if (status) 1114 return status; 1115 1116 /* If high temperature failure, then return over temp error and exit */ 1117 if (reg & IXGBE_MDIO_GLOBAL_ALM_1_HI_TMP_FAIL) { 1118 /* power down the PHY in case the PHY FW didn't already */ 1119 ixgbe_set_copper_phy_power(hw, false); 1120 return IXGBE_ERR_OVERTEMP; 1121 } 1122 1123 /* Vendor alarm 2 triggered */ 1124 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG, 1125 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, ®); 1126 1127 if (status || !(reg & IXGBE_MDIO_GLOBAL_STD_ALM2_INT)) 1128 return status; 1129 1130 /* link connect/disconnect event occurred */ 1131 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM2, 1132 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, ®); 1133 1134 if (status) 1135 return status; 1136 1137 /* Indicate LSC */ 1138 if (reg & IXGBE_MDIO_AUTO_NEG_VEN_LSC) 1139 *lsc = true; 1140 1141 return 0; 1142 } 1143 1144 /** 1145 * ixgbe_enable_lasi_ext_t_x550em - Enable external Base T PHY interrupts 1146 * @hw: pointer to hardware structure 1147 * 1148 * Enable link status change and temperature failure alarm for the external 1149 * Base T PHY 1150 * 1151 * Returns PHY access status 1152 **/ 1153 static s32 ixgbe_enable_lasi_ext_t_x550em(struct ixgbe_hw *hw) 1154 { 1155 u32 status; 1156 u16 reg; 1157 bool lsc; 1158 1159 /* Clear interrupt flags */ 1160 status = ixgbe_get_lasi_ext_t_x550em(hw, &lsc); 1161 1162 /* Enable link status change alarm */ 1163 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK, 1164 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, ®); 1165 if (status) 1166 return status; 1167 1168 reg |= IXGBE_MDIO_PMA_TX_VEN_LASI_INT_EN; 1169 1170 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK, 1171 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, reg); 1172 if (status) 1173 return status; 1174 1175 /* Enables high temperature failure alarm */ 1176 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK, 1177 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 1178 ®); 1179 if (status) 1180 return status; 1181 1182 reg |= IXGBE_MDIO_GLOBAL_INT_HI_TEMP_EN; 1183 1184 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK, 1185 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 1186 reg); 1187 if (status) 1188 return status; 1189 1190 /* Enable vendor Auto-Neg alarm and Global Interrupt Mask 1 alarm */ 1191 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK, 1192 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 1193 ®); 1194 if (status) 1195 return status; 1196 1197 reg |= (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN | 1198 IXGBE_MDIO_GLOBAL_ALARM_1_INT); 1199 1200 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK, 1201 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 1202 reg); 1203 if (status) 1204 return status; 1205 1206 /* Enable chip-wide vendor alarm */ 1207 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK, 1208 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 1209 ®); 1210 if (status) 1211 return status; 1212 1213 reg |= IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN; 1214 1215 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK, 1216 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 1217 reg); 1218 1219 return status; 1220 } 1221 1222 /** 1223 * ixgbe_handle_lasi_ext_t_x550em - Handle external Base T PHY interrupt 1224 * @hw: pointer to hardware structure 1225 * 1226 * Handle external Base T PHY interrupt. If high temperature 1227 * failure alarm then return error, else if link status change 1228 * then setup internal/external PHY link 1229 * 1230 * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature 1231 * failure alarm, else return PHY access status. 1232 **/ 1233 static s32 ixgbe_handle_lasi_ext_t_x550em(struct ixgbe_hw *hw) 1234 { 1235 struct ixgbe_phy_info *phy = &hw->phy; 1236 bool lsc; 1237 u32 status; 1238 1239 status = ixgbe_get_lasi_ext_t_x550em(hw, &lsc); 1240 if (status) 1241 return status; 1242 1243 if (lsc) 1244 return phy->ops.setup_internal_link(hw); 1245 1246 return 0; 1247 } 1248 1249 /** 1250 * ixgbe_setup_kr_speed_x550em - Configure the KR PHY for link speed. 1251 * @hw: pointer to hardware structure 1252 * @speed: link speed 1253 * 1254 * Configures the integrated KR PHY. 1255 **/ 1256 static s32 ixgbe_setup_kr_speed_x550em(struct ixgbe_hw *hw, 1257 ixgbe_link_speed speed) 1258 { 1259 s32 status; 1260 u32 reg_val; 1261 1262 status = ixgbe_read_iosf_sb_reg_x550(hw, 1263 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id), 1264 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val); 1265 if (status) 1266 return status; 1267 1268 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE; 1269 reg_val &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_AN_FEC_REQ | 1270 IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_FEC); 1271 reg_val &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR | 1272 IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX); 1273 1274 /* Advertise 10G support. */ 1275 if (speed & IXGBE_LINK_SPEED_10GB_FULL) 1276 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR; 1277 1278 /* Advertise 1G support. */ 1279 if (speed & IXGBE_LINK_SPEED_1GB_FULL) 1280 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX; 1281 1282 /* Restart auto-negotiation. */ 1283 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART; 1284 status = ixgbe_write_iosf_sb_reg_x550(hw, 1285 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id), 1286 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val); 1287 1288 return status; 1289 } 1290 1291 /** ixgbe_setup_kx4_x550em - Configure the KX4 PHY. 1292 * @hw: pointer to hardware structure 1293 * 1294 * Configures the integrated KX4 PHY. 1295 **/ 1296 static s32 ixgbe_setup_kx4_x550em(struct ixgbe_hw *hw) 1297 { 1298 s32 status; 1299 u32 reg_val; 1300 1301 status = ixgbe_read_iosf_sb_reg_x550(hw, IXGBE_KX4_LINK_CNTL_1, 1302 IXGBE_SB_IOSF_TARGET_KX4_PCS0 + 1303 hw->bus.lan_id, ®_val); 1304 if (status) 1305 return status; 1306 1307 reg_val &= ~(IXGBE_KX4_LINK_CNTL_1_TETH_AN_CAP_KX4 | 1308 IXGBE_KX4_LINK_CNTL_1_TETH_AN_CAP_KX); 1309 1310 reg_val |= IXGBE_KX4_LINK_CNTL_1_TETH_AN_ENABLE; 1311 1312 /* Advertise 10G support. */ 1313 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL) 1314 reg_val |= IXGBE_KX4_LINK_CNTL_1_TETH_AN_CAP_KX4; 1315 1316 /* Advertise 1G support. */ 1317 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL) 1318 reg_val |= IXGBE_KX4_LINK_CNTL_1_TETH_AN_CAP_KX; 1319 1320 /* Restart auto-negotiation. */ 1321 reg_val |= IXGBE_KX4_LINK_CNTL_1_TETH_AN_RESTART; 1322 status = ixgbe_write_iosf_sb_reg_x550(hw, IXGBE_KX4_LINK_CNTL_1, 1323 IXGBE_SB_IOSF_TARGET_KX4_PCS0 + 1324 hw->bus.lan_id, reg_val); 1325 1326 return status; 1327 } 1328 1329 /** ixgbe_setup_kr_x550em - Configure the KR PHY. 1330 * @hw: pointer to hardware structure 1331 * 1332 * Configures the integrated KR PHY. 1333 **/ 1334 static s32 ixgbe_setup_kr_x550em(struct ixgbe_hw *hw) 1335 { 1336 return ixgbe_setup_kr_speed_x550em(hw, hw->phy.autoneg_advertised); 1337 } 1338 1339 /** ixgbe_ext_phy_t_x550em_get_link - Get ext phy link status 1340 * @hw: address of hardware structure 1341 * @link_up: address of boolean to indicate link status 1342 * 1343 * Returns error code if unable to get link status. 1344 **/ 1345 static s32 ixgbe_ext_phy_t_x550em_get_link(struct ixgbe_hw *hw, bool *link_up) 1346 { 1347 u32 ret; 1348 u16 autoneg_status; 1349 1350 *link_up = false; 1351 1352 /* read this twice back to back to indicate current status */ 1353 ret = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS, 1354 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 1355 &autoneg_status); 1356 if (ret) 1357 return ret; 1358 1359 ret = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS, 1360 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 1361 &autoneg_status); 1362 if (ret) 1363 return ret; 1364 1365 *link_up = !!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS); 1366 1367 return 0; 1368 } 1369 1370 /** ixgbe_setup_internal_phy_t_x550em - Configure KR PHY to X557 link 1371 * @hw: point to hardware structure 1372 * 1373 * Configures the link between the integrated KR PHY and the external X557 PHY 1374 * The driver will call this function when it gets a link status change 1375 * interrupt from the X557 PHY. This function configures the link speed 1376 * between the PHYs to match the link speed of the BASE-T link. 1377 * 1378 * A return of a non-zero value indicates an error, and the base driver should 1379 * not report link up. 1380 **/ 1381 static s32 ixgbe_setup_internal_phy_t_x550em(struct ixgbe_hw *hw) 1382 { 1383 ixgbe_link_speed force_speed; 1384 bool link_up; 1385 u32 status; 1386 u16 speed; 1387 1388 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper) 1389 return IXGBE_ERR_CONFIG; 1390 1391 /* If link is not up, then there is no setup necessary so return */ 1392 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up); 1393 if (status) 1394 return status; 1395 1396 if (!link_up) 1397 return 0; 1398 1399 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_STAT, 1400 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 1401 &speed); 1402 if (status) 1403 return status; 1404 1405 /* If link is not still up, then no setup is necessary so return */ 1406 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up); 1407 if (status) 1408 return status; 1409 1410 if (!link_up) 1411 return 0; 1412 1413 /* clear everything but the speed and duplex bits */ 1414 speed &= IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_MASK; 1415 1416 switch (speed) { 1417 case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB_FULL: 1418 force_speed = IXGBE_LINK_SPEED_10GB_FULL; 1419 break; 1420 case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB_FULL: 1421 force_speed = IXGBE_LINK_SPEED_1GB_FULL; 1422 break; 1423 default: 1424 /* Internal PHY does not support anything else */ 1425 return IXGBE_ERR_INVALID_LINK_SETTINGS; 1426 } 1427 1428 return ixgbe_setup_ixfi_x550em(hw, &force_speed); 1429 } 1430 1431 /** ixgbe_reset_phy_t_X550em - Performs X557 PHY reset and enables LASI 1432 * @hw: pointer to hardware structure 1433 **/ 1434 static s32 ixgbe_reset_phy_t_X550em(struct ixgbe_hw *hw) 1435 { 1436 s32 status; 1437 1438 status = ixgbe_reset_phy_generic(hw); 1439 1440 if (status) 1441 return status; 1442 1443 /* Configure Link Status Alarm and Temperature Threshold interrupts */ 1444 return ixgbe_enable_lasi_ext_t_x550em(hw); 1445 } 1446 1447 /** ixgbe_init_phy_ops_X550em - PHY/SFP specific init 1448 * @hw: pointer to hardware structure 1449 * 1450 * Initialize any function pointers that were not able to be 1451 * set during init_shared_code because the PHY/SFP type was 1452 * not known. Perform the SFP init if necessary. 1453 **/ 1454 static s32 ixgbe_init_phy_ops_X550em(struct ixgbe_hw *hw) 1455 { 1456 struct ixgbe_phy_info *phy = &hw->phy; 1457 ixgbe_link_speed speed; 1458 s32 ret_val; 1459 1460 hw->mac.ops.set_lan_id(hw); 1461 1462 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) { 1463 phy->phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM; 1464 ixgbe_setup_mux_ctl(hw); 1465 1466 /* Save NW management interface connected on board. This is used 1467 * to determine internal PHY mode. 1468 */ 1469 phy->nw_mng_if_sel = IXGBE_READ_REG(hw, IXGBE_NW_MNG_IF_SEL); 1470 1471 /* If internal PHY mode is KR, then initialize KR link */ 1472 if (phy->nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE) { 1473 speed = IXGBE_LINK_SPEED_10GB_FULL | 1474 IXGBE_LINK_SPEED_1GB_FULL; 1475 ret_val = ixgbe_setup_kr_speed_x550em(hw, speed); 1476 } 1477 } 1478 1479 /* Identify the PHY or SFP module */ 1480 ret_val = phy->ops.identify(hw); 1481 1482 /* Setup function pointers based on detected hardware */ 1483 ixgbe_init_mac_link_ops_X550em(hw); 1484 if (phy->sfp_type != ixgbe_sfp_type_unknown) 1485 phy->ops.reset = NULL; 1486 1487 /* Set functions pointers based on phy type */ 1488 switch (hw->phy.type) { 1489 case ixgbe_phy_x550em_kx4: 1490 phy->ops.setup_link = ixgbe_setup_kx4_x550em; 1491 phy->ops.read_reg = ixgbe_read_phy_reg_x550em; 1492 phy->ops.write_reg = ixgbe_write_phy_reg_x550em; 1493 break; 1494 case ixgbe_phy_x550em_kr: 1495 phy->ops.setup_link = ixgbe_setup_kr_x550em; 1496 phy->ops.read_reg = ixgbe_read_phy_reg_x550em; 1497 phy->ops.write_reg = ixgbe_write_phy_reg_x550em; 1498 break; 1499 case ixgbe_phy_x550em_ext_t: 1500 /* Save NW management interface connected on board. This is used 1501 * to determine internal PHY mode 1502 */ 1503 phy->nw_mng_if_sel = IXGBE_READ_REG(hw, IXGBE_NW_MNG_IF_SEL); 1504 1505 /* If internal link mode is XFI, then setup iXFI internal link, 1506 * else setup KR now. 1507 */ 1508 if (!(phy->nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) { 1509 phy->ops.setup_internal_link = 1510 ixgbe_setup_internal_phy_t_x550em; 1511 } else { 1512 speed = IXGBE_LINK_SPEED_10GB_FULL | 1513 IXGBE_LINK_SPEED_1GB_FULL; 1514 ret_val = ixgbe_setup_kr_speed_x550em(hw, speed); 1515 } 1516 1517 phy->ops.handle_lasi = ixgbe_handle_lasi_ext_t_x550em; 1518 phy->ops.reset = ixgbe_reset_phy_t_X550em; 1519 break; 1520 default: 1521 break; 1522 } 1523 1524 return ret_val; 1525 } 1526 1527 /** ixgbe_get_media_type_X550em - Get media type 1528 * @hw: pointer to hardware structure 1529 * 1530 * Returns the media type (fiber, copper, backplane) 1531 * 1532 */ 1533 static enum ixgbe_media_type ixgbe_get_media_type_X550em(struct ixgbe_hw *hw) 1534 { 1535 enum ixgbe_media_type media_type; 1536 1537 /* Detect if there is a copper PHY attached. */ 1538 switch (hw->device_id) { 1539 case IXGBE_DEV_ID_X550EM_X_KR: 1540 case IXGBE_DEV_ID_X550EM_X_KX4: 1541 media_type = ixgbe_media_type_backplane; 1542 break; 1543 case IXGBE_DEV_ID_X550EM_X_SFP: 1544 media_type = ixgbe_media_type_fiber; 1545 break; 1546 case IXGBE_DEV_ID_X550EM_X_1G_T: 1547 case IXGBE_DEV_ID_X550EM_X_10G_T: 1548 media_type = ixgbe_media_type_copper; 1549 break; 1550 default: 1551 media_type = ixgbe_media_type_unknown; 1552 break; 1553 } 1554 return media_type; 1555 } 1556 1557 /** ixgbe_init_ext_t_x550em - Start (unstall) the external Base T PHY. 1558 ** @hw: pointer to hardware structure 1559 **/ 1560 static s32 ixgbe_init_ext_t_x550em(struct ixgbe_hw *hw) 1561 { 1562 s32 status; 1563 u16 reg; 1564 1565 status = hw->phy.ops.read_reg(hw, 1566 IXGBE_MDIO_TX_VENDOR_ALARMS_3, 1567 IXGBE_MDIO_PMA_PMD_DEV_TYPE, 1568 ®); 1569 if (status) 1570 return status; 1571 1572 /* If PHY FW reset completed bit is set then this is the first 1573 * SW instance after a power on so the PHY FW must be un-stalled. 1574 */ 1575 if (reg & IXGBE_MDIO_TX_VENDOR_ALARMS_3_RST_MASK) { 1576 status = hw->phy.ops.read_reg(hw, 1577 IXGBE_MDIO_GLOBAL_RES_PR_10, 1578 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 1579 ®); 1580 if (status) 1581 return status; 1582 1583 reg &= ~IXGBE_MDIO_POWER_UP_STALL; 1584 1585 status = hw->phy.ops.write_reg(hw, 1586 IXGBE_MDIO_GLOBAL_RES_PR_10, 1587 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 1588 reg); 1589 if (status) 1590 return status; 1591 } 1592 1593 return status; 1594 } 1595 1596 /** ixgbe_reset_hw_X550em - Perform hardware reset 1597 ** @hw: pointer to hardware structure 1598 ** 1599 ** Resets the hardware by resetting the transmit and receive units, masks 1600 ** and clears all interrupts, perform a PHY reset, and perform a link (MAC) 1601 ** reset. 1602 **/ 1603 static s32 ixgbe_reset_hw_X550em(struct ixgbe_hw *hw) 1604 { 1605 ixgbe_link_speed link_speed; 1606 s32 status; 1607 u32 ctrl = 0; 1608 u32 i; 1609 u32 hlreg0; 1610 bool link_up = false; 1611 1612 /* Call adapter stop to disable Tx/Rx and clear interrupts */ 1613 status = hw->mac.ops.stop_adapter(hw); 1614 if (status) 1615 return status; 1616 1617 /* flush pending Tx transactions */ 1618 ixgbe_clear_tx_pending(hw); 1619 1620 /* PHY ops must be identified and initialized prior to reset */ 1621 1622 /* Identify PHY and related function pointers */ 1623 status = hw->phy.ops.init(hw); 1624 1625 /* start the external PHY */ 1626 if (hw->phy.type == ixgbe_phy_x550em_ext_t) { 1627 status = ixgbe_init_ext_t_x550em(hw); 1628 if (status) 1629 return status; 1630 } 1631 1632 /* Setup SFP module if there is one present. */ 1633 if (hw->phy.sfp_setup_needed) { 1634 status = hw->mac.ops.setup_sfp(hw); 1635 hw->phy.sfp_setup_needed = false; 1636 } 1637 1638 /* Reset PHY */ 1639 if (!hw->phy.reset_disable && hw->phy.ops.reset) 1640 hw->phy.ops.reset(hw); 1641 1642 mac_reset_top: 1643 /* Issue global reset to the MAC. Needs to be SW reset if link is up. 1644 * If link reset is used when link is up, it might reset the PHY when 1645 * mng is using it. If link is down or the flag to force full link 1646 * reset is set, then perform link reset. 1647 */ 1648 ctrl = IXGBE_CTRL_LNK_RST; 1649 1650 if (!hw->force_full_reset) { 1651 hw->mac.ops.check_link(hw, &link_speed, &link_up, false); 1652 if (link_up) 1653 ctrl = IXGBE_CTRL_RST; 1654 } 1655 1656 ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL); 1657 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl); 1658 IXGBE_WRITE_FLUSH(hw); 1659 1660 /* Poll for reset bit to self-clear meaning reset is complete */ 1661 for (i = 0; i < 10; i++) { 1662 udelay(1); 1663 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL); 1664 if (!(ctrl & IXGBE_CTRL_RST_MASK)) 1665 break; 1666 } 1667 1668 if (ctrl & IXGBE_CTRL_RST_MASK) { 1669 status = IXGBE_ERR_RESET_FAILED; 1670 hw_dbg(hw, "Reset polling failed to complete.\n"); 1671 } 1672 1673 msleep(50); 1674 1675 /* Double resets are required for recovery from certain error 1676 * clear the multicast table. Also reset num_rar_entries to 128, 1677 * since we modify this value when programming the SAN MAC address. 1678 */ 1679 if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) { 1680 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED; 1681 goto mac_reset_top; 1682 } 1683 1684 /* Store the permanent mac address */ 1685 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr); 1686 1687 /* Store MAC address from RAR0, clear receive address registers, and 1688 * clear the multicast table. Also reset num_rar_entries to 128, 1689 * since we modify this value when programming the SAN MAC address. 1690 */ 1691 hw->mac.num_rar_entries = 128; 1692 hw->mac.ops.init_rx_addrs(hw); 1693 1694 if (hw->device_id == IXGBE_DEV_ID_X550EM_X_10G_T) { 1695 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0); 1696 hlreg0 &= ~IXGBE_HLREG0_MDCSPD; 1697 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0); 1698 } 1699 1700 if (hw->device_id == IXGBE_DEV_ID_X550EM_X_SFP) 1701 ixgbe_setup_mux_ctl(hw); 1702 1703 return status; 1704 } 1705 1706 /** ixgbe_set_ethertype_anti_spoofing_X550 - Enable/Disable Ethertype 1707 * anti-spoofing 1708 * @hw: pointer to hardware structure 1709 * @enable: enable or disable switch for Ethertype anti-spoofing 1710 * @vf: Virtual Function pool - VF Pool to set for Ethertype anti-spoofing 1711 **/ 1712 static void ixgbe_set_ethertype_anti_spoofing_X550(struct ixgbe_hw *hw, 1713 bool enable, int vf) 1714 { 1715 int vf_target_reg = vf >> 3; 1716 int vf_target_shift = vf % 8 + IXGBE_SPOOF_ETHERTYPEAS_SHIFT; 1717 u32 pfvfspoof; 1718 1719 pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg)); 1720 if (enable) 1721 pfvfspoof |= (1 << vf_target_shift); 1722 else 1723 pfvfspoof &= ~(1 << vf_target_shift); 1724 1725 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof); 1726 } 1727 1728 /** ixgbe_set_source_address_pruning_X550 - Enable/Disbale src address pruning 1729 * @hw: pointer to hardware structure 1730 * @enable: enable or disable source address pruning 1731 * @pool: Rx pool to set source address pruning for 1732 **/ 1733 static void ixgbe_set_source_address_pruning_X550(struct ixgbe_hw *hw, 1734 bool enable, 1735 unsigned int pool) 1736 { 1737 u64 pfflp; 1738 1739 /* max rx pool is 63 */ 1740 if (pool > 63) 1741 return; 1742 1743 pfflp = (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPL); 1744 pfflp |= (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPH) << 32; 1745 1746 if (enable) 1747 pfflp |= (1ULL << pool); 1748 else 1749 pfflp &= ~(1ULL << pool); 1750 1751 IXGBE_WRITE_REG(hw, IXGBE_PFFLPL, (u32)pfflp); 1752 IXGBE_WRITE_REG(hw, IXGBE_PFFLPH, (u32)(pfflp >> 32)); 1753 } 1754 1755 #define X550_COMMON_MAC \ 1756 .init_hw = &ixgbe_init_hw_generic, \ 1757 .start_hw = &ixgbe_start_hw_X540, \ 1758 .clear_hw_cntrs = &ixgbe_clear_hw_cntrs_generic, \ 1759 .enable_rx_dma = &ixgbe_enable_rx_dma_generic, \ 1760 .get_mac_addr = &ixgbe_get_mac_addr_generic, \ 1761 .get_device_caps = &ixgbe_get_device_caps_generic, \ 1762 .stop_adapter = &ixgbe_stop_adapter_generic, \ 1763 .get_bus_info = &ixgbe_get_bus_info_generic, \ 1764 .set_lan_id = &ixgbe_set_lan_id_multi_port_pcie, \ 1765 .read_analog_reg8 = NULL, \ 1766 .write_analog_reg8 = NULL, \ 1767 .set_rxpba = &ixgbe_set_rxpba_generic, \ 1768 .check_link = &ixgbe_check_mac_link_generic, \ 1769 .led_on = &ixgbe_led_on_generic, \ 1770 .led_off = &ixgbe_led_off_generic, \ 1771 .blink_led_start = &ixgbe_blink_led_start_X540, \ 1772 .blink_led_stop = &ixgbe_blink_led_stop_X540, \ 1773 .set_rar = &ixgbe_set_rar_generic, \ 1774 .clear_rar = &ixgbe_clear_rar_generic, \ 1775 .set_vmdq = &ixgbe_set_vmdq_generic, \ 1776 .set_vmdq_san_mac = &ixgbe_set_vmdq_san_mac_generic, \ 1777 .clear_vmdq = &ixgbe_clear_vmdq_generic, \ 1778 .init_rx_addrs = &ixgbe_init_rx_addrs_generic, \ 1779 .update_mc_addr_list = &ixgbe_update_mc_addr_list_generic, \ 1780 .enable_mc = &ixgbe_enable_mc_generic, \ 1781 .disable_mc = &ixgbe_disable_mc_generic, \ 1782 .clear_vfta = &ixgbe_clear_vfta_generic, \ 1783 .set_vfta = &ixgbe_set_vfta_generic, \ 1784 .fc_enable = &ixgbe_fc_enable_generic, \ 1785 .set_fw_drv_ver = &ixgbe_set_fw_drv_ver_generic, \ 1786 .init_uta_tables = &ixgbe_init_uta_tables_generic, \ 1787 .set_mac_anti_spoofing = &ixgbe_set_mac_anti_spoofing, \ 1788 .set_vlan_anti_spoofing = &ixgbe_set_vlan_anti_spoofing, \ 1789 .set_source_address_pruning = \ 1790 &ixgbe_set_source_address_pruning_X550, \ 1791 .set_ethertype_anti_spoofing = \ 1792 &ixgbe_set_ethertype_anti_spoofing_X550, \ 1793 .acquire_swfw_sync = &ixgbe_acquire_swfw_sync_X540, \ 1794 .release_swfw_sync = &ixgbe_release_swfw_sync_X540, \ 1795 .disable_rx_buff = &ixgbe_disable_rx_buff_generic, \ 1796 .enable_rx_buff = &ixgbe_enable_rx_buff_generic, \ 1797 .get_thermal_sensor_data = NULL, \ 1798 .init_thermal_sensor_thresh = NULL, \ 1799 .prot_autoc_read = &prot_autoc_read_generic, \ 1800 .prot_autoc_write = &prot_autoc_write_generic, \ 1801 .enable_rx = &ixgbe_enable_rx_generic, \ 1802 .disable_rx = &ixgbe_disable_rx_x550, \ 1803 1804 static struct ixgbe_mac_operations mac_ops_X550 = { 1805 X550_COMMON_MAC 1806 .reset_hw = &ixgbe_reset_hw_X540, 1807 .get_media_type = &ixgbe_get_media_type_X540, 1808 .get_san_mac_addr = &ixgbe_get_san_mac_addr_generic, 1809 .get_wwn_prefix = &ixgbe_get_wwn_prefix_generic, 1810 .setup_link = &ixgbe_setup_mac_link_X540, 1811 .get_link_capabilities = &ixgbe_get_copper_link_capabilities_generic, 1812 .setup_sfp = NULL, 1813 }; 1814 1815 static struct ixgbe_mac_operations mac_ops_X550EM_x = { 1816 X550_COMMON_MAC 1817 .reset_hw = &ixgbe_reset_hw_X550em, 1818 .get_media_type = &ixgbe_get_media_type_X550em, 1819 .get_san_mac_addr = NULL, 1820 .get_wwn_prefix = NULL, 1821 .setup_link = NULL, /* defined later */ 1822 .get_link_capabilities = &ixgbe_get_link_capabilities_X550em, 1823 .setup_sfp = ixgbe_setup_sfp_modules_X550em, 1824 1825 }; 1826 1827 #define X550_COMMON_EEP \ 1828 .read = &ixgbe_read_ee_hostif_X550, \ 1829 .read_buffer = &ixgbe_read_ee_hostif_buffer_X550, \ 1830 .write = &ixgbe_write_ee_hostif_X550, \ 1831 .write_buffer = &ixgbe_write_ee_hostif_buffer_X550, \ 1832 .validate_checksum = &ixgbe_validate_eeprom_checksum_X550, \ 1833 .update_checksum = &ixgbe_update_eeprom_checksum_X550, \ 1834 .calc_checksum = &ixgbe_calc_eeprom_checksum_X550, \ 1835 1836 static struct ixgbe_eeprom_operations eeprom_ops_X550 = { 1837 X550_COMMON_EEP 1838 .init_params = &ixgbe_init_eeprom_params_X550, 1839 }; 1840 1841 static struct ixgbe_eeprom_operations eeprom_ops_X550EM_x = { 1842 X550_COMMON_EEP 1843 .init_params = &ixgbe_init_eeprom_params_X540, 1844 }; 1845 1846 #define X550_COMMON_PHY \ 1847 .identify_sfp = &ixgbe_identify_module_generic, \ 1848 .reset = NULL, \ 1849 .setup_link_speed = &ixgbe_setup_phy_link_speed_generic, \ 1850 .read_i2c_byte = &ixgbe_read_i2c_byte_generic, \ 1851 .write_i2c_byte = &ixgbe_write_i2c_byte_generic, \ 1852 .read_i2c_sff8472 = &ixgbe_read_i2c_sff8472_generic, \ 1853 .read_i2c_eeprom = &ixgbe_read_i2c_eeprom_generic, \ 1854 .write_i2c_eeprom = &ixgbe_write_i2c_eeprom_generic, \ 1855 .read_reg = &ixgbe_read_phy_reg_generic, \ 1856 .write_reg = &ixgbe_write_phy_reg_generic, \ 1857 .setup_link = &ixgbe_setup_phy_link_generic, \ 1858 .set_phy_power = &ixgbe_set_copper_phy_power, \ 1859 .check_overtemp = &ixgbe_tn_check_overtemp, \ 1860 .get_firmware_version = &ixgbe_get_phy_firmware_version_generic, 1861 1862 static struct ixgbe_phy_operations phy_ops_X550 = { 1863 X550_COMMON_PHY 1864 .init = NULL, 1865 .identify = &ixgbe_identify_phy_generic, 1866 .read_i2c_combined = &ixgbe_read_i2c_combined_generic, 1867 .write_i2c_combined = &ixgbe_write_i2c_combined_generic, 1868 }; 1869 1870 static struct ixgbe_phy_operations phy_ops_X550EM_x = { 1871 X550_COMMON_PHY 1872 .init = &ixgbe_init_phy_ops_X550em, 1873 .identify = &ixgbe_identify_phy_x550em, 1874 }; 1875 1876 static const u32 ixgbe_mvals_X550[IXGBE_MVALS_IDX_LIMIT] = { 1877 IXGBE_MVALS_INIT(X550) 1878 }; 1879 1880 static const u32 ixgbe_mvals_X550EM_x[IXGBE_MVALS_IDX_LIMIT] = { 1881 IXGBE_MVALS_INIT(X550EM_x) 1882 }; 1883 1884 struct ixgbe_info ixgbe_X550_info = { 1885 .mac = ixgbe_mac_X550, 1886 .get_invariants = &ixgbe_get_invariants_X540, 1887 .mac_ops = &mac_ops_X550, 1888 .eeprom_ops = &eeprom_ops_X550, 1889 .phy_ops = &phy_ops_X550, 1890 .mbx_ops = &mbx_ops_generic, 1891 .mvals = ixgbe_mvals_X550, 1892 }; 1893 1894 struct ixgbe_info ixgbe_X550EM_x_info = { 1895 .mac = ixgbe_mac_X550EM_x, 1896 .get_invariants = &ixgbe_get_invariants_X540, 1897 .mac_ops = &mac_ops_X550EM_x, 1898 .eeprom_ops = &eeprom_ops_X550EM_x, 1899 .phy_ops = &phy_ops_X550EM_x, 1900 .mbx_ops = &mbx_ops_generic, 1901 .mvals = ixgbe_mvals_X550EM_x, 1902 }; 1903