1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright(c) 1999 - 2018 Intel Corporation. */ 3 4 #include "ixgbe_x540.h" 5 #include "ixgbe_type.h" 6 #include "ixgbe_common.h" 7 #include "ixgbe_phy.h" 8 9 static s32 ixgbe_setup_kr_speed_x550em(struct ixgbe_hw *, ixgbe_link_speed); 10 static s32 ixgbe_setup_fc_x550em(struct ixgbe_hw *); 11 static void ixgbe_fc_autoneg_fiber_x550em_a(struct ixgbe_hw *); 12 static void ixgbe_fc_autoneg_backplane_x550em_a(struct ixgbe_hw *); 13 static s32 ixgbe_setup_fc_backplane_x550em_a(struct ixgbe_hw *); 14 15 static s32 ixgbe_get_invariants_X550_x(struct ixgbe_hw *hw) 16 { 17 struct ixgbe_mac_info *mac = &hw->mac; 18 struct ixgbe_phy_info *phy = &hw->phy; 19 struct ixgbe_link_info *link = &hw->link; 20 21 /* Start with X540 invariants, since so simular */ 22 ixgbe_get_invariants_X540(hw); 23 24 if (mac->ops.get_media_type(hw) != ixgbe_media_type_copper) 25 phy->ops.set_phy_power = NULL; 26 27 link->addr = IXGBE_CS4227; 28 29 return 0; 30 } 31 32 static s32 ixgbe_get_invariants_X550_x_fw(struct ixgbe_hw *hw) 33 { 34 struct ixgbe_phy_info *phy = &hw->phy; 35 36 /* Start with X540 invariants, since so similar */ 37 ixgbe_get_invariants_X540(hw); 38 39 phy->ops.set_phy_power = NULL; 40 41 return 0; 42 } 43 44 static s32 ixgbe_get_invariants_X550_a(struct ixgbe_hw *hw) 45 { 46 struct ixgbe_mac_info *mac = &hw->mac; 47 struct ixgbe_phy_info *phy = &hw->phy; 48 49 /* Start with X540 invariants, since so simular */ 50 ixgbe_get_invariants_X540(hw); 51 52 if (mac->ops.get_media_type(hw) != ixgbe_media_type_copper) 53 phy->ops.set_phy_power = NULL; 54 55 return 0; 56 } 57 58 static s32 ixgbe_get_invariants_X550_a_fw(struct ixgbe_hw *hw) 59 { 60 struct ixgbe_phy_info *phy = &hw->phy; 61 62 /* Start with X540 invariants, since so similar */ 63 ixgbe_get_invariants_X540(hw); 64 65 phy->ops.set_phy_power = NULL; 66 67 return 0; 68 } 69 70 /** ixgbe_setup_mux_ctl - Setup ESDP register for I2C mux control 71 * @hw: pointer to hardware structure 72 **/ 73 static void ixgbe_setup_mux_ctl(struct ixgbe_hw *hw) 74 { 75 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); 76 77 if (hw->bus.lan_id) { 78 esdp &= ~(IXGBE_ESDP_SDP1_NATIVE | IXGBE_ESDP_SDP1); 79 esdp |= IXGBE_ESDP_SDP1_DIR; 80 } 81 esdp &= ~(IXGBE_ESDP_SDP0_NATIVE | IXGBE_ESDP_SDP0_DIR); 82 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp); 83 IXGBE_WRITE_FLUSH(hw); 84 } 85 86 /** 87 * ixgbe_read_cs4227 - Read CS4227 register 88 * @hw: pointer to hardware structure 89 * @reg: register number to write 90 * @value: pointer to receive value read 91 * 92 * Returns status code 93 */ 94 static s32 ixgbe_read_cs4227(struct ixgbe_hw *hw, u16 reg, u16 *value) 95 { 96 return hw->link.ops.read_link_unlocked(hw, hw->link.addr, reg, value); 97 } 98 99 /** 100 * ixgbe_write_cs4227 - Write CS4227 register 101 * @hw: pointer to hardware structure 102 * @reg: register number to write 103 * @value: value to write to register 104 * 105 * Returns status code 106 */ 107 static s32 ixgbe_write_cs4227(struct ixgbe_hw *hw, u16 reg, u16 value) 108 { 109 return hw->link.ops.write_link_unlocked(hw, hw->link.addr, reg, value); 110 } 111 112 /** 113 * ixgbe_read_pe - Read register from port expander 114 * @hw: pointer to hardware structure 115 * @reg: register number to read 116 * @value: pointer to receive read value 117 * 118 * Returns status code 119 */ 120 static s32 ixgbe_read_pe(struct ixgbe_hw *hw, u8 reg, u8 *value) 121 { 122 s32 status; 123 124 status = ixgbe_read_i2c_byte_generic_unlocked(hw, reg, IXGBE_PE, value); 125 if (status) 126 hw_err(hw, "port expander access failed with %d\n", status); 127 return status; 128 } 129 130 /** 131 * ixgbe_write_pe - Write register to port expander 132 * @hw: pointer to hardware structure 133 * @reg: register number to write 134 * @value: value to write 135 * 136 * Returns status code 137 */ 138 static s32 ixgbe_write_pe(struct ixgbe_hw *hw, u8 reg, u8 value) 139 { 140 s32 status; 141 142 status = ixgbe_write_i2c_byte_generic_unlocked(hw, reg, IXGBE_PE, 143 value); 144 if (status) 145 hw_err(hw, "port expander access failed with %d\n", status); 146 return status; 147 } 148 149 /** 150 * ixgbe_reset_cs4227 - Reset CS4227 using port expander 151 * @hw: pointer to hardware structure 152 * 153 * This function assumes that the caller has acquired the proper semaphore. 154 * Returns error code 155 */ 156 static s32 ixgbe_reset_cs4227(struct ixgbe_hw *hw) 157 { 158 s32 status; 159 u32 retry; 160 u16 value; 161 u8 reg; 162 163 /* Trigger hard reset. */ 164 status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, ®); 165 if (status) 166 return status; 167 reg |= IXGBE_PE_BIT1; 168 status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg); 169 if (status) 170 return status; 171 172 status = ixgbe_read_pe(hw, IXGBE_PE_CONFIG, ®); 173 if (status) 174 return status; 175 reg &= ~IXGBE_PE_BIT1; 176 status = ixgbe_write_pe(hw, IXGBE_PE_CONFIG, reg); 177 if (status) 178 return status; 179 180 status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, ®); 181 if (status) 182 return status; 183 reg &= ~IXGBE_PE_BIT1; 184 status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg); 185 if (status) 186 return status; 187 188 usleep_range(IXGBE_CS4227_RESET_HOLD, IXGBE_CS4227_RESET_HOLD + 100); 189 190 status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, ®); 191 if (status) 192 return status; 193 reg |= IXGBE_PE_BIT1; 194 status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg); 195 if (status) 196 return status; 197 198 /* Wait for the reset to complete. */ 199 msleep(IXGBE_CS4227_RESET_DELAY); 200 for (retry = 0; retry < IXGBE_CS4227_RETRIES; retry++) { 201 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_EFUSE_STATUS, 202 &value); 203 if (!status && value == IXGBE_CS4227_EEPROM_LOAD_OK) 204 break; 205 msleep(IXGBE_CS4227_CHECK_DELAY); 206 } 207 if (retry == IXGBE_CS4227_RETRIES) { 208 hw_err(hw, "CS4227 reset did not complete\n"); 209 return IXGBE_ERR_PHY; 210 } 211 212 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_EEPROM_STATUS, &value); 213 if (status || !(value & IXGBE_CS4227_EEPROM_LOAD_OK)) { 214 hw_err(hw, "CS4227 EEPROM did not load successfully\n"); 215 return IXGBE_ERR_PHY; 216 } 217 218 return 0; 219 } 220 221 /** 222 * ixgbe_check_cs4227 - Check CS4227 and reset as needed 223 * @hw: pointer to hardware structure 224 */ 225 static void ixgbe_check_cs4227(struct ixgbe_hw *hw) 226 { 227 u32 swfw_mask = hw->phy.phy_semaphore_mask; 228 s32 status; 229 u16 value; 230 u8 retry; 231 232 for (retry = 0; retry < IXGBE_CS4227_RETRIES; retry++) { 233 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask); 234 if (status) { 235 hw_err(hw, "semaphore failed with %d\n", status); 236 msleep(IXGBE_CS4227_CHECK_DELAY); 237 continue; 238 } 239 240 /* Get status of reset flow. */ 241 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_SCRATCH, &value); 242 if (!status && value == IXGBE_CS4227_RESET_COMPLETE) 243 goto out; 244 245 if (status || value != IXGBE_CS4227_RESET_PENDING) 246 break; 247 248 /* Reset is pending. Wait and check again. */ 249 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 250 msleep(IXGBE_CS4227_CHECK_DELAY); 251 } 252 /* If still pending, assume other instance failed. */ 253 if (retry == IXGBE_CS4227_RETRIES) { 254 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask); 255 if (status) { 256 hw_err(hw, "semaphore failed with %d\n", status); 257 return; 258 } 259 } 260 261 /* Reset the CS4227. */ 262 status = ixgbe_reset_cs4227(hw); 263 if (status) { 264 hw_err(hw, "CS4227 reset failed: %d", status); 265 goto out; 266 } 267 268 /* Reset takes so long, temporarily release semaphore in case the 269 * other driver instance is waiting for the reset indication. 270 */ 271 ixgbe_write_cs4227(hw, IXGBE_CS4227_SCRATCH, 272 IXGBE_CS4227_RESET_PENDING); 273 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 274 usleep_range(10000, 12000); 275 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask); 276 if (status) { 277 hw_err(hw, "semaphore failed with %d", status); 278 return; 279 } 280 281 /* Record completion for next time. */ 282 status = ixgbe_write_cs4227(hw, IXGBE_CS4227_SCRATCH, 283 IXGBE_CS4227_RESET_COMPLETE); 284 285 out: 286 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 287 msleep(hw->eeprom.semaphore_delay); 288 } 289 290 /** ixgbe_identify_phy_x550em - Get PHY type based on device id 291 * @hw: pointer to hardware structure 292 * 293 * Returns error code 294 */ 295 static s32 ixgbe_identify_phy_x550em(struct ixgbe_hw *hw) 296 { 297 switch (hw->device_id) { 298 case IXGBE_DEV_ID_X550EM_A_SFP: 299 if (hw->bus.lan_id) 300 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY1_SM; 301 else 302 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY0_SM; 303 return ixgbe_identify_module_generic(hw); 304 case IXGBE_DEV_ID_X550EM_X_SFP: 305 /* set up for CS4227 usage */ 306 hw->phy.phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM; 307 ixgbe_setup_mux_ctl(hw); 308 ixgbe_check_cs4227(hw); 309 /* Fallthrough */ 310 case IXGBE_DEV_ID_X550EM_A_SFP_N: 311 return ixgbe_identify_module_generic(hw); 312 case IXGBE_DEV_ID_X550EM_X_KX4: 313 hw->phy.type = ixgbe_phy_x550em_kx4; 314 break; 315 case IXGBE_DEV_ID_X550EM_X_XFI: 316 hw->phy.type = ixgbe_phy_x550em_xfi; 317 break; 318 case IXGBE_DEV_ID_X550EM_X_KR: 319 case IXGBE_DEV_ID_X550EM_A_KR: 320 case IXGBE_DEV_ID_X550EM_A_KR_L: 321 hw->phy.type = ixgbe_phy_x550em_kr; 322 break; 323 case IXGBE_DEV_ID_X550EM_A_10G_T: 324 if (hw->bus.lan_id) 325 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY1_SM; 326 else 327 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY0_SM; 328 /* Fallthrough */ 329 case IXGBE_DEV_ID_X550EM_X_10G_T: 330 return ixgbe_identify_phy_generic(hw); 331 case IXGBE_DEV_ID_X550EM_X_1G_T: 332 hw->phy.type = ixgbe_phy_ext_1g_t; 333 break; 334 case IXGBE_DEV_ID_X550EM_A_1G_T: 335 case IXGBE_DEV_ID_X550EM_A_1G_T_L: 336 hw->phy.type = ixgbe_phy_fw; 337 hw->phy.ops.read_reg = NULL; 338 hw->phy.ops.write_reg = NULL; 339 if (hw->bus.lan_id) 340 hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY1_SM; 341 else 342 hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY0_SM; 343 break; 344 default: 345 break; 346 } 347 return 0; 348 } 349 350 static s32 ixgbe_read_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr, 351 u32 device_type, u16 *phy_data) 352 { 353 return IXGBE_NOT_IMPLEMENTED; 354 } 355 356 static s32 ixgbe_write_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr, 357 u32 device_type, u16 phy_data) 358 { 359 return IXGBE_NOT_IMPLEMENTED; 360 } 361 362 /** 363 * ixgbe_read_i2c_combined_generic - Perform I2C read combined operation 364 * @hw: pointer to the hardware structure 365 * @addr: I2C bus address to read from 366 * @reg: I2C device register to read from 367 * @val: pointer to location to receive read value 368 * 369 * Returns an error code on error. 370 **/ 371 static s32 ixgbe_read_i2c_combined_generic(struct ixgbe_hw *hw, u8 addr, 372 u16 reg, u16 *val) 373 { 374 return ixgbe_read_i2c_combined_generic_int(hw, addr, reg, val, true); 375 } 376 377 /** 378 * ixgbe_read_i2c_combined_generic_unlocked - Do I2C read combined operation 379 * @hw: pointer to the hardware structure 380 * @addr: I2C bus address to read from 381 * @reg: I2C device register to read from 382 * @val: pointer to location to receive read value 383 * 384 * Returns an error code on error. 385 **/ 386 static s32 387 ixgbe_read_i2c_combined_generic_unlocked(struct ixgbe_hw *hw, u8 addr, 388 u16 reg, u16 *val) 389 { 390 return ixgbe_read_i2c_combined_generic_int(hw, addr, reg, val, false); 391 } 392 393 /** 394 * ixgbe_write_i2c_combined_generic - Perform I2C write combined operation 395 * @hw: pointer to the hardware structure 396 * @addr: I2C bus address to write to 397 * @reg: I2C device register to write to 398 * @val: value to write 399 * 400 * Returns an error code on error. 401 **/ 402 static s32 ixgbe_write_i2c_combined_generic(struct ixgbe_hw *hw, 403 u8 addr, u16 reg, u16 val) 404 { 405 return ixgbe_write_i2c_combined_generic_int(hw, addr, reg, val, true); 406 } 407 408 /** 409 * ixgbe_write_i2c_combined_generic_unlocked - Do I2C write combined operation 410 * @hw: pointer to the hardware structure 411 * @addr: I2C bus address to write to 412 * @reg: I2C device register to write to 413 * @val: value to write 414 * 415 * Returns an error code on error. 416 **/ 417 static s32 418 ixgbe_write_i2c_combined_generic_unlocked(struct ixgbe_hw *hw, 419 u8 addr, u16 reg, u16 val) 420 { 421 return ixgbe_write_i2c_combined_generic_int(hw, addr, reg, val, false); 422 } 423 424 /** 425 * ixgbe_fw_phy_activity - Perform an activity on a PHY 426 * @hw: pointer to hardware structure 427 * @activity: activity to perform 428 * @data: Pointer to 4 32-bit words of data 429 */ 430 s32 ixgbe_fw_phy_activity(struct ixgbe_hw *hw, u16 activity, 431 u32 (*data)[FW_PHY_ACT_DATA_COUNT]) 432 { 433 union { 434 struct ixgbe_hic_phy_activity_req cmd; 435 struct ixgbe_hic_phy_activity_resp rsp; 436 } hic; 437 u16 retries = FW_PHY_ACT_RETRIES; 438 s32 rc; 439 u32 i; 440 441 do { 442 memset(&hic, 0, sizeof(hic)); 443 hic.cmd.hdr.cmd = FW_PHY_ACT_REQ_CMD; 444 hic.cmd.hdr.buf_len = FW_PHY_ACT_REQ_LEN; 445 hic.cmd.hdr.checksum = FW_DEFAULT_CHECKSUM; 446 hic.cmd.port_number = hw->bus.lan_id; 447 hic.cmd.activity_id = cpu_to_le16(activity); 448 for (i = 0; i < ARRAY_SIZE(hic.cmd.data); ++i) 449 hic.cmd.data[i] = cpu_to_be32((*data)[i]); 450 451 rc = ixgbe_host_interface_command(hw, &hic.cmd, sizeof(hic.cmd), 452 IXGBE_HI_COMMAND_TIMEOUT, 453 true); 454 if (rc) 455 return rc; 456 if (hic.rsp.hdr.cmd_or_resp.ret_status == 457 FW_CEM_RESP_STATUS_SUCCESS) { 458 for (i = 0; i < FW_PHY_ACT_DATA_COUNT; ++i) 459 (*data)[i] = be32_to_cpu(hic.rsp.data[i]); 460 return 0; 461 } 462 usleep_range(20, 30); 463 --retries; 464 } while (retries > 0); 465 466 return IXGBE_ERR_HOST_INTERFACE_COMMAND; 467 } 468 469 static const struct { 470 u16 fw_speed; 471 ixgbe_link_speed phy_speed; 472 } ixgbe_fw_map[] = { 473 { FW_PHY_ACT_LINK_SPEED_10, IXGBE_LINK_SPEED_10_FULL }, 474 { FW_PHY_ACT_LINK_SPEED_100, IXGBE_LINK_SPEED_100_FULL }, 475 { FW_PHY_ACT_LINK_SPEED_1G, IXGBE_LINK_SPEED_1GB_FULL }, 476 { FW_PHY_ACT_LINK_SPEED_2_5G, IXGBE_LINK_SPEED_2_5GB_FULL }, 477 { FW_PHY_ACT_LINK_SPEED_5G, IXGBE_LINK_SPEED_5GB_FULL }, 478 { FW_PHY_ACT_LINK_SPEED_10G, IXGBE_LINK_SPEED_10GB_FULL }, 479 }; 480 481 /** 482 * ixgbe_get_phy_id_fw - Get the phy ID via firmware command 483 * @hw: pointer to hardware structure 484 * 485 * Returns error code 486 */ 487 static s32 ixgbe_get_phy_id_fw(struct ixgbe_hw *hw) 488 { 489 u32 info[FW_PHY_ACT_DATA_COUNT] = { 0 }; 490 u16 phy_speeds; 491 u16 phy_id_lo; 492 s32 rc; 493 u16 i; 494 495 if (hw->phy.id) 496 return 0; 497 498 rc = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_GET_PHY_INFO, &info); 499 if (rc) 500 return rc; 501 502 hw->phy.speeds_supported = 0; 503 phy_speeds = info[0] & FW_PHY_INFO_SPEED_MASK; 504 for (i = 0; i < ARRAY_SIZE(ixgbe_fw_map); ++i) { 505 if (phy_speeds & ixgbe_fw_map[i].fw_speed) 506 hw->phy.speeds_supported |= ixgbe_fw_map[i].phy_speed; 507 } 508 509 hw->phy.id = info[0] & FW_PHY_INFO_ID_HI_MASK; 510 phy_id_lo = info[1] & FW_PHY_INFO_ID_LO_MASK; 511 hw->phy.id |= phy_id_lo & IXGBE_PHY_REVISION_MASK; 512 hw->phy.revision = phy_id_lo & ~IXGBE_PHY_REVISION_MASK; 513 if (!hw->phy.id || hw->phy.id == IXGBE_PHY_REVISION_MASK) 514 return IXGBE_ERR_PHY_ADDR_INVALID; 515 516 hw->phy.autoneg_advertised = hw->phy.speeds_supported; 517 hw->phy.eee_speeds_supported = IXGBE_LINK_SPEED_100_FULL | 518 IXGBE_LINK_SPEED_1GB_FULL; 519 hw->phy.eee_speeds_advertised = hw->phy.eee_speeds_supported; 520 return 0; 521 } 522 523 /** 524 * ixgbe_identify_phy_fw - Get PHY type based on firmware command 525 * @hw: pointer to hardware structure 526 * 527 * Returns error code 528 */ 529 static s32 ixgbe_identify_phy_fw(struct ixgbe_hw *hw) 530 { 531 if (hw->bus.lan_id) 532 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY1_SM; 533 else 534 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY0_SM; 535 536 hw->phy.type = ixgbe_phy_fw; 537 hw->phy.ops.read_reg = NULL; 538 hw->phy.ops.write_reg = NULL; 539 return ixgbe_get_phy_id_fw(hw); 540 } 541 542 /** 543 * ixgbe_shutdown_fw_phy - Shutdown a firmware-controlled PHY 544 * @hw: pointer to hardware structure 545 * 546 * Returns error code 547 */ 548 static s32 ixgbe_shutdown_fw_phy(struct ixgbe_hw *hw) 549 { 550 u32 setup[FW_PHY_ACT_DATA_COUNT] = { 0 }; 551 552 setup[0] = FW_PHY_ACT_FORCE_LINK_DOWN_OFF; 553 return ixgbe_fw_phy_activity(hw, FW_PHY_ACT_FORCE_LINK_DOWN, &setup); 554 } 555 556 /** 557 * ixgbe_setup_fw_link - Setup firmware-controlled PHYs 558 * @hw: pointer to hardware structure 559 */ 560 static s32 ixgbe_setup_fw_link(struct ixgbe_hw *hw) 561 { 562 u32 setup[FW_PHY_ACT_DATA_COUNT] = { 0 }; 563 s32 rc; 564 u16 i; 565 566 if (hw->phy.reset_disable || ixgbe_check_reset_blocked(hw)) 567 return 0; 568 569 if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) { 570 hw_err(hw, "rx_pause not valid in strict IEEE mode\n"); 571 return IXGBE_ERR_INVALID_LINK_SETTINGS; 572 } 573 574 switch (hw->fc.requested_mode) { 575 case ixgbe_fc_full: 576 setup[0] |= FW_PHY_ACT_SETUP_LINK_PAUSE_RXTX << 577 FW_PHY_ACT_SETUP_LINK_PAUSE_SHIFT; 578 break; 579 case ixgbe_fc_rx_pause: 580 setup[0] |= FW_PHY_ACT_SETUP_LINK_PAUSE_RX << 581 FW_PHY_ACT_SETUP_LINK_PAUSE_SHIFT; 582 break; 583 case ixgbe_fc_tx_pause: 584 setup[0] |= FW_PHY_ACT_SETUP_LINK_PAUSE_TX << 585 FW_PHY_ACT_SETUP_LINK_PAUSE_SHIFT; 586 break; 587 default: 588 break; 589 } 590 591 for (i = 0; i < ARRAY_SIZE(ixgbe_fw_map); ++i) { 592 if (hw->phy.autoneg_advertised & ixgbe_fw_map[i].phy_speed) 593 setup[0] |= ixgbe_fw_map[i].fw_speed; 594 } 595 setup[0] |= FW_PHY_ACT_SETUP_LINK_HP | FW_PHY_ACT_SETUP_LINK_AN; 596 597 if (hw->phy.eee_speeds_advertised) 598 setup[0] |= FW_PHY_ACT_SETUP_LINK_EEE; 599 600 rc = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_SETUP_LINK, &setup); 601 if (rc) 602 return rc; 603 if (setup[0] == FW_PHY_ACT_SETUP_LINK_RSP_DOWN) 604 return IXGBE_ERR_OVERTEMP; 605 return 0; 606 } 607 608 /** 609 * ixgbe_fc_autoneg_fw - Set up flow control for FW-controlled PHYs 610 * @hw: pointer to hardware structure 611 * 612 * Called at init time to set up flow control. 613 */ 614 static s32 ixgbe_fc_autoneg_fw(struct ixgbe_hw *hw) 615 { 616 if (hw->fc.requested_mode == ixgbe_fc_default) 617 hw->fc.requested_mode = ixgbe_fc_full; 618 619 return ixgbe_setup_fw_link(hw); 620 } 621 622 /** ixgbe_init_eeprom_params_X550 - Initialize EEPROM params 623 * @hw: pointer to hardware structure 624 * 625 * Initializes the EEPROM parameters ixgbe_eeprom_info within the 626 * ixgbe_hw struct in order to set up EEPROM access. 627 **/ 628 static s32 ixgbe_init_eeprom_params_X550(struct ixgbe_hw *hw) 629 { 630 struct ixgbe_eeprom_info *eeprom = &hw->eeprom; 631 u32 eec; 632 u16 eeprom_size; 633 634 if (eeprom->type == ixgbe_eeprom_uninitialized) { 635 eeprom->semaphore_delay = 10; 636 eeprom->type = ixgbe_flash; 637 638 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw)); 639 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >> 640 IXGBE_EEC_SIZE_SHIFT); 641 eeprom->word_size = BIT(eeprom_size + 642 IXGBE_EEPROM_WORD_SIZE_SHIFT); 643 644 hw_dbg(hw, "Eeprom params: type = %d, size = %d\n", 645 eeprom->type, eeprom->word_size); 646 } 647 648 return 0; 649 } 650 651 /** 652 * ixgbe_iosf_wait - Wait for IOSF command completion 653 * @hw: pointer to hardware structure 654 * @ctrl: pointer to location to receive final IOSF control value 655 * 656 * Return: failing status on timeout 657 * 658 * Note: ctrl can be NULL if the IOSF control register value is not needed 659 */ 660 static s32 ixgbe_iosf_wait(struct ixgbe_hw *hw, u32 *ctrl) 661 { 662 u32 i, command; 663 664 /* Check every 10 usec to see if the address cycle completed. 665 * The SB IOSF BUSY bit will clear when the operation is 666 * complete. 667 */ 668 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { 669 command = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL); 670 if (!(command & IXGBE_SB_IOSF_CTRL_BUSY)) 671 break; 672 udelay(10); 673 } 674 if (ctrl) 675 *ctrl = command; 676 if (i == IXGBE_MDIO_COMMAND_TIMEOUT) { 677 hw_dbg(hw, "IOSF wait timed out\n"); 678 return IXGBE_ERR_PHY; 679 } 680 681 return 0; 682 } 683 684 /** ixgbe_read_iosf_sb_reg_x550 - Writes a value to specified register of the 685 * IOSF device 686 * @hw: pointer to hardware structure 687 * @reg_addr: 32 bit PHY register to write 688 * @device_type: 3 bit device type 689 * @phy_data: Pointer to read data from the register 690 **/ 691 static s32 ixgbe_read_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr, 692 u32 device_type, u32 *data) 693 { 694 u32 gssr = IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_PHY0_SM; 695 u32 command, error; 696 s32 ret; 697 698 ret = hw->mac.ops.acquire_swfw_sync(hw, gssr); 699 if (ret) 700 return ret; 701 702 ret = ixgbe_iosf_wait(hw, NULL); 703 if (ret) 704 goto out; 705 706 command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) | 707 (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT)); 708 709 /* Write IOSF control register */ 710 IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command); 711 712 ret = ixgbe_iosf_wait(hw, &command); 713 714 if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) { 715 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >> 716 IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT; 717 hw_dbg(hw, "Failed to read, error %x\n", error); 718 return IXGBE_ERR_PHY; 719 } 720 721 if (!ret) 722 *data = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA); 723 724 out: 725 hw->mac.ops.release_swfw_sync(hw, gssr); 726 return ret; 727 } 728 729 /** 730 * ixgbe_get_phy_token - Get the token for shared PHY access 731 * @hw: Pointer to hardware structure 732 */ 733 static s32 ixgbe_get_phy_token(struct ixgbe_hw *hw) 734 { 735 struct ixgbe_hic_phy_token_req token_cmd; 736 s32 status; 737 738 token_cmd.hdr.cmd = FW_PHY_TOKEN_REQ_CMD; 739 token_cmd.hdr.buf_len = FW_PHY_TOKEN_REQ_LEN; 740 token_cmd.hdr.cmd_or_resp.cmd_resv = 0; 741 token_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM; 742 token_cmd.port_number = hw->bus.lan_id; 743 token_cmd.command_type = FW_PHY_TOKEN_REQ; 744 token_cmd.pad = 0; 745 status = ixgbe_host_interface_command(hw, &token_cmd, sizeof(token_cmd), 746 IXGBE_HI_COMMAND_TIMEOUT, 747 true); 748 if (status) 749 return status; 750 if (token_cmd.hdr.cmd_or_resp.ret_status == FW_PHY_TOKEN_OK) 751 return 0; 752 if (token_cmd.hdr.cmd_or_resp.ret_status != FW_PHY_TOKEN_RETRY) 753 return IXGBE_ERR_FW_RESP_INVALID; 754 755 return IXGBE_ERR_TOKEN_RETRY; 756 } 757 758 /** 759 * ixgbe_put_phy_token - Put the token for shared PHY access 760 * @hw: Pointer to hardware structure 761 */ 762 static s32 ixgbe_put_phy_token(struct ixgbe_hw *hw) 763 { 764 struct ixgbe_hic_phy_token_req token_cmd; 765 s32 status; 766 767 token_cmd.hdr.cmd = FW_PHY_TOKEN_REQ_CMD; 768 token_cmd.hdr.buf_len = FW_PHY_TOKEN_REQ_LEN; 769 token_cmd.hdr.cmd_or_resp.cmd_resv = 0; 770 token_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM; 771 token_cmd.port_number = hw->bus.lan_id; 772 token_cmd.command_type = FW_PHY_TOKEN_REL; 773 token_cmd.pad = 0; 774 status = ixgbe_host_interface_command(hw, &token_cmd, sizeof(token_cmd), 775 IXGBE_HI_COMMAND_TIMEOUT, 776 true); 777 if (status) 778 return status; 779 if (token_cmd.hdr.cmd_or_resp.ret_status == FW_PHY_TOKEN_OK) 780 return 0; 781 return IXGBE_ERR_FW_RESP_INVALID; 782 } 783 784 /** 785 * ixgbe_write_iosf_sb_reg_x550a - Write to IOSF PHY register 786 * @hw: pointer to hardware structure 787 * @reg_addr: 32 bit PHY register to write 788 * @device_type: 3 bit device type 789 * @data: Data to write to the register 790 **/ 791 static s32 ixgbe_write_iosf_sb_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr, 792 __always_unused u32 device_type, 793 u32 data) 794 { 795 struct ixgbe_hic_internal_phy_req write_cmd; 796 797 memset(&write_cmd, 0, sizeof(write_cmd)); 798 write_cmd.hdr.cmd = FW_INT_PHY_REQ_CMD; 799 write_cmd.hdr.buf_len = FW_INT_PHY_REQ_LEN; 800 write_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM; 801 write_cmd.port_number = hw->bus.lan_id; 802 write_cmd.command_type = FW_INT_PHY_REQ_WRITE; 803 write_cmd.address = cpu_to_be16(reg_addr); 804 write_cmd.write_data = cpu_to_be32(data); 805 806 return ixgbe_host_interface_command(hw, &write_cmd, sizeof(write_cmd), 807 IXGBE_HI_COMMAND_TIMEOUT, false); 808 } 809 810 /** 811 * ixgbe_read_iosf_sb_reg_x550a - Read from IOSF PHY register 812 * @hw: pointer to hardware structure 813 * @reg_addr: 32 bit PHY register to write 814 * @device_type: 3 bit device type 815 * @data: Pointer to read data from the register 816 **/ 817 static s32 ixgbe_read_iosf_sb_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr, 818 __always_unused u32 device_type, 819 u32 *data) 820 { 821 union { 822 struct ixgbe_hic_internal_phy_req cmd; 823 struct ixgbe_hic_internal_phy_resp rsp; 824 } hic; 825 s32 status; 826 827 memset(&hic, 0, sizeof(hic)); 828 hic.cmd.hdr.cmd = FW_INT_PHY_REQ_CMD; 829 hic.cmd.hdr.buf_len = FW_INT_PHY_REQ_LEN; 830 hic.cmd.hdr.checksum = FW_DEFAULT_CHECKSUM; 831 hic.cmd.port_number = hw->bus.lan_id; 832 hic.cmd.command_type = FW_INT_PHY_REQ_READ; 833 hic.cmd.address = cpu_to_be16(reg_addr); 834 835 status = ixgbe_host_interface_command(hw, &hic.cmd, sizeof(hic.cmd), 836 IXGBE_HI_COMMAND_TIMEOUT, true); 837 838 /* Extract the register value from the response. */ 839 *data = be32_to_cpu(hic.rsp.read_data); 840 841 return status; 842 } 843 844 /** ixgbe_read_ee_hostif_buffer_X550- Read EEPROM word(s) using hostif 845 * @hw: pointer to hardware structure 846 * @offset: offset of word in the EEPROM to read 847 * @words: number of words 848 * @data: word(s) read from the EEPROM 849 * 850 * Reads a 16 bit word(s) from the EEPROM using the hostif. 851 **/ 852 static s32 ixgbe_read_ee_hostif_buffer_X550(struct ixgbe_hw *hw, 853 u16 offset, u16 words, u16 *data) 854 { 855 const u32 mask = IXGBE_GSSR_SW_MNG_SM | IXGBE_GSSR_EEP_SM; 856 struct ixgbe_hic_read_shadow_ram buffer; 857 u32 current_word = 0; 858 u16 words_to_read; 859 s32 status; 860 u32 i; 861 862 /* Take semaphore for the entire operation. */ 863 status = hw->mac.ops.acquire_swfw_sync(hw, mask); 864 if (status) { 865 hw_dbg(hw, "EEPROM read buffer - semaphore failed\n"); 866 return status; 867 } 868 869 while (words) { 870 if (words > FW_MAX_READ_BUFFER_SIZE / 2) 871 words_to_read = FW_MAX_READ_BUFFER_SIZE / 2; 872 else 873 words_to_read = words; 874 875 buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD; 876 buffer.hdr.req.buf_lenh = 0; 877 buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN; 878 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM; 879 880 /* convert offset from words to bytes */ 881 buffer.address = (__force u32)cpu_to_be32((offset + 882 current_word) * 2); 883 buffer.length = (__force u16)cpu_to_be16(words_to_read * 2); 884 buffer.pad2 = 0; 885 buffer.pad3 = 0; 886 887 status = ixgbe_hic_unlocked(hw, (u32 *)&buffer, sizeof(buffer), 888 IXGBE_HI_COMMAND_TIMEOUT); 889 if (status) { 890 hw_dbg(hw, "Host interface command failed\n"); 891 goto out; 892 } 893 894 for (i = 0; i < words_to_read; i++) { 895 u32 reg = IXGBE_FLEX_MNG + (FW_NVM_DATA_OFFSET << 2) + 896 2 * i; 897 u32 value = IXGBE_READ_REG(hw, reg); 898 899 data[current_word] = (u16)(value & 0xffff); 900 current_word++; 901 i++; 902 if (i < words_to_read) { 903 value >>= 16; 904 data[current_word] = (u16)(value & 0xffff); 905 current_word++; 906 } 907 } 908 words -= words_to_read; 909 } 910 911 out: 912 hw->mac.ops.release_swfw_sync(hw, mask); 913 return status; 914 } 915 916 /** ixgbe_checksum_ptr_x550 - Checksum one pointer region 917 * @hw: pointer to hardware structure 918 * @ptr: pointer offset in eeprom 919 * @size: size of section pointed by ptr, if 0 first word will be used as size 920 * @csum: address of checksum to update 921 * 922 * Returns error status for any failure 923 **/ 924 static s32 ixgbe_checksum_ptr_x550(struct ixgbe_hw *hw, u16 ptr, 925 u16 size, u16 *csum, u16 *buffer, 926 u32 buffer_size) 927 { 928 u16 buf[256]; 929 s32 status; 930 u16 length, bufsz, i, start; 931 u16 *local_buffer; 932 933 bufsz = ARRAY_SIZE(buf); 934 935 /* Read a chunk at the pointer location */ 936 if (!buffer) { 937 status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr, bufsz, buf); 938 if (status) { 939 hw_dbg(hw, "Failed to read EEPROM image\n"); 940 return status; 941 } 942 local_buffer = buf; 943 } else { 944 if (buffer_size < ptr) 945 return IXGBE_ERR_PARAM; 946 local_buffer = &buffer[ptr]; 947 } 948 949 if (size) { 950 start = 0; 951 length = size; 952 } else { 953 start = 1; 954 length = local_buffer[0]; 955 956 /* Skip pointer section if length is invalid. */ 957 if (length == 0xFFFF || length == 0 || 958 (ptr + length) >= hw->eeprom.word_size) 959 return 0; 960 } 961 962 if (buffer && ((u32)start + (u32)length > buffer_size)) 963 return IXGBE_ERR_PARAM; 964 965 for (i = start; length; i++, length--) { 966 if (i == bufsz && !buffer) { 967 ptr += bufsz; 968 i = 0; 969 if (length < bufsz) 970 bufsz = length; 971 972 /* Read a chunk at the pointer location */ 973 status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr, 974 bufsz, buf); 975 if (status) { 976 hw_dbg(hw, "Failed to read EEPROM image\n"); 977 return status; 978 } 979 } 980 *csum += local_buffer[i]; 981 } 982 return 0; 983 } 984 985 /** ixgbe_calc_checksum_X550 - Calculates and returns the checksum 986 * @hw: pointer to hardware structure 987 * @buffer: pointer to buffer containing calculated checksum 988 * @buffer_size: size of buffer 989 * 990 * Returns a negative error code on error, or the 16-bit checksum 991 **/ 992 static s32 ixgbe_calc_checksum_X550(struct ixgbe_hw *hw, u16 *buffer, 993 u32 buffer_size) 994 { 995 u16 eeprom_ptrs[IXGBE_EEPROM_LAST_WORD + 1]; 996 u16 *local_buffer; 997 s32 status; 998 u16 checksum = 0; 999 u16 pointer, i, size; 1000 1001 hw->eeprom.ops.init_params(hw); 1002 1003 if (!buffer) { 1004 /* Read pointer area */ 1005 status = ixgbe_read_ee_hostif_buffer_X550(hw, 0, 1006 IXGBE_EEPROM_LAST_WORD + 1, 1007 eeprom_ptrs); 1008 if (status) { 1009 hw_dbg(hw, "Failed to read EEPROM image\n"); 1010 return status; 1011 } 1012 local_buffer = eeprom_ptrs; 1013 } else { 1014 if (buffer_size < IXGBE_EEPROM_LAST_WORD) 1015 return IXGBE_ERR_PARAM; 1016 local_buffer = buffer; 1017 } 1018 1019 /* For X550 hardware include 0x0-0x41 in the checksum, skip the 1020 * checksum word itself 1021 */ 1022 for (i = 0; i <= IXGBE_EEPROM_LAST_WORD; i++) 1023 if (i != IXGBE_EEPROM_CHECKSUM) 1024 checksum += local_buffer[i]; 1025 1026 /* Include all data from pointers 0x3, 0x6-0xE. This excludes the 1027 * FW, PHY module, and PCIe Expansion/Option ROM pointers. 1028 */ 1029 for (i = IXGBE_PCIE_ANALOG_PTR_X550; i < IXGBE_FW_PTR; i++) { 1030 if (i == IXGBE_PHY_PTR || i == IXGBE_OPTION_ROM_PTR) 1031 continue; 1032 1033 pointer = local_buffer[i]; 1034 1035 /* Skip pointer section if the pointer is invalid. */ 1036 if (pointer == 0xFFFF || pointer == 0 || 1037 pointer >= hw->eeprom.word_size) 1038 continue; 1039 1040 switch (i) { 1041 case IXGBE_PCIE_GENERAL_PTR: 1042 size = IXGBE_IXGBE_PCIE_GENERAL_SIZE; 1043 break; 1044 case IXGBE_PCIE_CONFIG0_PTR: 1045 case IXGBE_PCIE_CONFIG1_PTR: 1046 size = IXGBE_PCIE_CONFIG_SIZE; 1047 break; 1048 default: 1049 size = 0; 1050 break; 1051 } 1052 1053 status = ixgbe_checksum_ptr_x550(hw, pointer, size, &checksum, 1054 buffer, buffer_size); 1055 if (status) 1056 return status; 1057 } 1058 1059 checksum = (u16)IXGBE_EEPROM_SUM - checksum; 1060 1061 return (s32)checksum; 1062 } 1063 1064 /** ixgbe_calc_eeprom_checksum_X550 - Calculates and returns the checksum 1065 * @hw: pointer to hardware structure 1066 * 1067 * Returns a negative error code on error, or the 16-bit checksum 1068 **/ 1069 static s32 ixgbe_calc_eeprom_checksum_X550(struct ixgbe_hw *hw) 1070 { 1071 return ixgbe_calc_checksum_X550(hw, NULL, 0); 1072 } 1073 1074 /** ixgbe_read_ee_hostif_X550 - Read EEPROM word using a host interface command 1075 * @hw: pointer to hardware structure 1076 * @offset: offset of word in the EEPROM to read 1077 * @data: word read from the EEPROM 1078 * 1079 * Reads a 16 bit word from the EEPROM using the hostif. 1080 **/ 1081 static s32 ixgbe_read_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset, u16 *data) 1082 { 1083 const u32 mask = IXGBE_GSSR_SW_MNG_SM | IXGBE_GSSR_EEP_SM; 1084 struct ixgbe_hic_read_shadow_ram buffer; 1085 s32 status; 1086 1087 buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD; 1088 buffer.hdr.req.buf_lenh = 0; 1089 buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN; 1090 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM; 1091 1092 /* convert offset from words to bytes */ 1093 buffer.address = (__force u32)cpu_to_be32(offset * 2); 1094 /* one word */ 1095 buffer.length = (__force u16)cpu_to_be16(sizeof(u16)); 1096 1097 status = hw->mac.ops.acquire_swfw_sync(hw, mask); 1098 if (status) 1099 return status; 1100 1101 status = ixgbe_hic_unlocked(hw, (u32 *)&buffer, sizeof(buffer), 1102 IXGBE_HI_COMMAND_TIMEOUT); 1103 if (!status) { 1104 *data = (u16)IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG, 1105 FW_NVM_DATA_OFFSET); 1106 } 1107 1108 hw->mac.ops.release_swfw_sync(hw, mask); 1109 return status; 1110 } 1111 1112 /** ixgbe_validate_eeprom_checksum_X550 - Validate EEPROM checksum 1113 * @hw: pointer to hardware structure 1114 * @checksum_val: calculated checksum 1115 * 1116 * Performs checksum calculation and validates the EEPROM checksum. If the 1117 * caller does not need checksum_val, the value can be NULL. 1118 **/ 1119 static s32 ixgbe_validate_eeprom_checksum_X550(struct ixgbe_hw *hw, 1120 u16 *checksum_val) 1121 { 1122 s32 status; 1123 u16 checksum; 1124 u16 read_checksum = 0; 1125 1126 /* Read the first word from the EEPROM. If this times out or fails, do 1127 * not continue or we could be in for a very long wait while every 1128 * EEPROM read fails 1129 */ 1130 status = hw->eeprom.ops.read(hw, 0, &checksum); 1131 if (status) { 1132 hw_dbg(hw, "EEPROM read failed\n"); 1133 return status; 1134 } 1135 1136 status = hw->eeprom.ops.calc_checksum(hw); 1137 if (status < 0) 1138 return status; 1139 1140 checksum = (u16)(status & 0xffff); 1141 1142 status = ixgbe_read_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM, 1143 &read_checksum); 1144 if (status) 1145 return status; 1146 1147 /* Verify read checksum from EEPROM is the same as 1148 * calculated checksum 1149 */ 1150 if (read_checksum != checksum) { 1151 status = IXGBE_ERR_EEPROM_CHECKSUM; 1152 hw_dbg(hw, "Invalid EEPROM checksum"); 1153 } 1154 1155 /* If the user cares, return the calculated checksum */ 1156 if (checksum_val) 1157 *checksum_val = checksum; 1158 1159 return status; 1160 } 1161 1162 /** ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif 1163 * @hw: pointer to hardware structure 1164 * @offset: offset of word in the EEPROM to write 1165 * @data: word write to the EEPROM 1166 * 1167 * Write a 16 bit word to the EEPROM using the hostif. 1168 **/ 1169 static s32 ixgbe_write_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset, 1170 u16 data) 1171 { 1172 s32 status; 1173 struct ixgbe_hic_write_shadow_ram buffer; 1174 1175 buffer.hdr.req.cmd = FW_WRITE_SHADOW_RAM_CMD; 1176 buffer.hdr.req.buf_lenh = 0; 1177 buffer.hdr.req.buf_lenl = FW_WRITE_SHADOW_RAM_LEN; 1178 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM; 1179 1180 /* one word */ 1181 buffer.length = cpu_to_be16(sizeof(u16)); 1182 buffer.data = data; 1183 buffer.address = cpu_to_be32(offset * 2); 1184 1185 status = ixgbe_host_interface_command(hw, &buffer, sizeof(buffer), 1186 IXGBE_HI_COMMAND_TIMEOUT, false); 1187 return status; 1188 } 1189 1190 /** ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif 1191 * @hw: pointer to hardware structure 1192 * @offset: offset of word in the EEPROM to write 1193 * @data: word write to the EEPROM 1194 * 1195 * Write a 16 bit word to the EEPROM using the hostif. 1196 **/ 1197 static s32 ixgbe_write_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset, u16 data) 1198 { 1199 s32 status = 0; 1200 1201 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) == 0) { 1202 status = ixgbe_write_ee_hostif_data_X550(hw, offset, data); 1203 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 1204 } else { 1205 hw_dbg(hw, "write ee hostif failed to get semaphore"); 1206 status = IXGBE_ERR_SWFW_SYNC; 1207 } 1208 1209 return status; 1210 } 1211 1212 /** ixgbe_update_flash_X550 - Instruct HW to copy EEPROM to Flash device 1213 * @hw: pointer to hardware structure 1214 * 1215 * Issue a shadow RAM dump to FW to copy EEPROM from shadow RAM to the flash. 1216 **/ 1217 static s32 ixgbe_update_flash_X550(struct ixgbe_hw *hw) 1218 { 1219 s32 status = 0; 1220 union ixgbe_hic_hdr2 buffer; 1221 1222 buffer.req.cmd = FW_SHADOW_RAM_DUMP_CMD; 1223 buffer.req.buf_lenh = 0; 1224 buffer.req.buf_lenl = FW_SHADOW_RAM_DUMP_LEN; 1225 buffer.req.checksum = FW_DEFAULT_CHECKSUM; 1226 1227 status = ixgbe_host_interface_command(hw, &buffer, sizeof(buffer), 1228 IXGBE_HI_COMMAND_TIMEOUT, false); 1229 return status; 1230 } 1231 1232 /** 1233 * ixgbe_get_bus_info_X550em - Set PCI bus info 1234 * @hw: pointer to hardware structure 1235 * 1236 * Sets bus link width and speed to unknown because X550em is 1237 * not a PCI device. 1238 **/ 1239 static s32 ixgbe_get_bus_info_X550em(struct ixgbe_hw *hw) 1240 { 1241 hw->bus.type = ixgbe_bus_type_internal; 1242 hw->bus.width = ixgbe_bus_width_unknown; 1243 hw->bus.speed = ixgbe_bus_speed_unknown; 1244 1245 hw->mac.ops.set_lan_id(hw); 1246 1247 return 0; 1248 } 1249 1250 /** ixgbe_disable_rx_x550 - Disable RX unit 1251 * 1252 * Enables the Rx DMA unit for x550 1253 **/ 1254 static void ixgbe_disable_rx_x550(struct ixgbe_hw *hw) 1255 { 1256 u32 rxctrl, pfdtxgswc; 1257 s32 status; 1258 struct ixgbe_hic_disable_rxen fw_cmd; 1259 1260 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL); 1261 if (rxctrl & IXGBE_RXCTRL_RXEN) { 1262 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC); 1263 if (pfdtxgswc & IXGBE_PFDTXGSWC_VT_LBEN) { 1264 pfdtxgswc &= ~IXGBE_PFDTXGSWC_VT_LBEN; 1265 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc); 1266 hw->mac.set_lben = true; 1267 } else { 1268 hw->mac.set_lben = false; 1269 } 1270 1271 fw_cmd.hdr.cmd = FW_DISABLE_RXEN_CMD; 1272 fw_cmd.hdr.buf_len = FW_DISABLE_RXEN_LEN; 1273 fw_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM; 1274 fw_cmd.port_number = hw->bus.lan_id; 1275 1276 status = ixgbe_host_interface_command(hw, &fw_cmd, 1277 sizeof(struct ixgbe_hic_disable_rxen), 1278 IXGBE_HI_COMMAND_TIMEOUT, true); 1279 1280 /* If we fail - disable RX using register write */ 1281 if (status) { 1282 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL); 1283 if (rxctrl & IXGBE_RXCTRL_RXEN) { 1284 rxctrl &= ~IXGBE_RXCTRL_RXEN; 1285 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl); 1286 } 1287 } 1288 } 1289 } 1290 1291 /** ixgbe_update_eeprom_checksum_X550 - Updates the EEPROM checksum and flash 1292 * @hw: pointer to hardware structure 1293 * 1294 * After writing EEPROM to shadow RAM using EEWR register, software calculates 1295 * checksum and updates the EEPROM and instructs the hardware to update 1296 * the flash. 1297 **/ 1298 static s32 ixgbe_update_eeprom_checksum_X550(struct ixgbe_hw *hw) 1299 { 1300 s32 status; 1301 u16 checksum = 0; 1302 1303 /* Read the first word from the EEPROM. If this times out or fails, do 1304 * not continue or we could be in for a very long wait while every 1305 * EEPROM read fails 1306 */ 1307 status = ixgbe_read_ee_hostif_X550(hw, 0, &checksum); 1308 if (status) { 1309 hw_dbg(hw, "EEPROM read failed\n"); 1310 return status; 1311 } 1312 1313 status = ixgbe_calc_eeprom_checksum_X550(hw); 1314 if (status < 0) 1315 return status; 1316 1317 checksum = (u16)(status & 0xffff); 1318 1319 status = ixgbe_write_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM, 1320 checksum); 1321 if (status) 1322 return status; 1323 1324 status = ixgbe_update_flash_X550(hw); 1325 1326 return status; 1327 } 1328 1329 /** ixgbe_write_ee_hostif_buffer_X550 - Write EEPROM word(s) using hostif 1330 * @hw: pointer to hardware structure 1331 * @offset: offset of word in the EEPROM to write 1332 * @words: number of words 1333 * @data: word(s) write to the EEPROM 1334 * 1335 * 1336 * Write a 16 bit word(s) to the EEPROM using the hostif. 1337 **/ 1338 static s32 ixgbe_write_ee_hostif_buffer_X550(struct ixgbe_hw *hw, 1339 u16 offset, u16 words, 1340 u16 *data) 1341 { 1342 s32 status = 0; 1343 u32 i = 0; 1344 1345 /* Take semaphore for the entire operation. */ 1346 status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 1347 if (status) { 1348 hw_dbg(hw, "EEPROM write buffer - semaphore failed\n"); 1349 return status; 1350 } 1351 1352 for (i = 0; i < words; i++) { 1353 status = ixgbe_write_ee_hostif_data_X550(hw, offset + i, 1354 data[i]); 1355 if (status) { 1356 hw_dbg(hw, "Eeprom buffered write failed\n"); 1357 break; 1358 } 1359 } 1360 1361 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 1362 1363 return status; 1364 } 1365 1366 /** ixgbe_write_iosf_sb_reg_x550 - Writes a value to specified register of the 1367 * IOSF device 1368 * 1369 * @hw: pointer to hardware structure 1370 * @reg_addr: 32 bit PHY register to write 1371 * @device_type: 3 bit device type 1372 * @data: Data to write to the register 1373 **/ 1374 static s32 ixgbe_write_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr, 1375 u32 device_type, u32 data) 1376 { 1377 u32 gssr = IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_PHY0_SM; 1378 u32 command, error; 1379 s32 ret; 1380 1381 ret = hw->mac.ops.acquire_swfw_sync(hw, gssr); 1382 if (ret) 1383 return ret; 1384 1385 ret = ixgbe_iosf_wait(hw, NULL); 1386 if (ret) 1387 goto out; 1388 1389 command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) | 1390 (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT)); 1391 1392 /* Write IOSF control register */ 1393 IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command); 1394 1395 /* Write IOSF data register */ 1396 IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA, data); 1397 1398 ret = ixgbe_iosf_wait(hw, &command); 1399 1400 if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) { 1401 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >> 1402 IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT; 1403 hw_dbg(hw, "Failed to write, error %x\n", error); 1404 return IXGBE_ERR_PHY; 1405 } 1406 1407 out: 1408 hw->mac.ops.release_swfw_sync(hw, gssr); 1409 return ret; 1410 } 1411 1412 /** 1413 * ixgbe_setup_ixfi_x550em_x - MAC specific iXFI configuration 1414 * @hw: pointer to hardware structure 1415 * 1416 * iXfI configuration needed for ixgbe_mac_X550EM_x devices. 1417 **/ 1418 static s32 ixgbe_setup_ixfi_x550em_x(struct ixgbe_hw *hw) 1419 { 1420 s32 status; 1421 u32 reg_val; 1422 1423 /* Disable training protocol FSM. */ 1424 status = ixgbe_read_iosf_sb_reg_x550(hw, 1425 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id), 1426 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val); 1427 if (status) 1428 return status; 1429 1430 reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_CONV_WO_PROTOCOL; 1431 status = ixgbe_write_iosf_sb_reg_x550(hw, 1432 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id), 1433 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val); 1434 if (status) 1435 return status; 1436 1437 /* Disable Flex from training TXFFE. */ 1438 status = ixgbe_read_iosf_sb_reg_x550(hw, 1439 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id), 1440 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val); 1441 if (status) 1442 return status; 1443 1444 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN; 1445 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN; 1446 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN; 1447 status = ixgbe_write_iosf_sb_reg_x550(hw, 1448 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id), 1449 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val); 1450 if (status) 1451 return status; 1452 1453 status = ixgbe_read_iosf_sb_reg_x550(hw, 1454 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id), 1455 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val); 1456 if (status) 1457 return status; 1458 1459 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN; 1460 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN; 1461 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN; 1462 status = ixgbe_write_iosf_sb_reg_x550(hw, 1463 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id), 1464 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val); 1465 if (status) 1466 return status; 1467 1468 /* Enable override for coefficients. */ 1469 status = ixgbe_read_iosf_sb_reg_x550(hw, 1470 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id), 1471 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val); 1472 if (status) 1473 return status; 1474 1475 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_OVRRD_EN; 1476 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CZERO_EN; 1477 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CPLUS1_OVRRD_EN; 1478 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CMINUS1_OVRRD_EN; 1479 status = ixgbe_write_iosf_sb_reg_x550(hw, 1480 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id), 1481 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val); 1482 return status; 1483 } 1484 1485 /** 1486 * ixgbe_restart_an_internal_phy_x550em - restart autonegotiation for the 1487 * internal PHY 1488 * @hw: pointer to hardware structure 1489 **/ 1490 static s32 ixgbe_restart_an_internal_phy_x550em(struct ixgbe_hw *hw) 1491 { 1492 s32 status; 1493 u32 link_ctrl; 1494 1495 /* Restart auto-negotiation. */ 1496 status = hw->mac.ops.read_iosf_sb_reg(hw, 1497 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id), 1498 IXGBE_SB_IOSF_TARGET_KR_PHY, &link_ctrl); 1499 1500 if (status) { 1501 hw_dbg(hw, "Auto-negotiation did not complete\n"); 1502 return status; 1503 } 1504 1505 link_ctrl |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART; 1506 status = hw->mac.ops.write_iosf_sb_reg(hw, 1507 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id), 1508 IXGBE_SB_IOSF_TARGET_KR_PHY, link_ctrl); 1509 1510 if (hw->mac.type == ixgbe_mac_x550em_a) { 1511 u32 flx_mask_st20; 1512 1513 /* Indicate to FW that AN restart has been asserted */ 1514 status = hw->mac.ops.read_iosf_sb_reg(hw, 1515 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id), 1516 IXGBE_SB_IOSF_TARGET_KR_PHY, &flx_mask_st20); 1517 1518 if (status) { 1519 hw_dbg(hw, "Auto-negotiation did not complete\n"); 1520 return status; 1521 } 1522 1523 flx_mask_st20 |= IXGBE_KRM_PMD_FLX_MASK_ST20_FW_AN_RESTART; 1524 status = hw->mac.ops.write_iosf_sb_reg(hw, 1525 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id), 1526 IXGBE_SB_IOSF_TARGET_KR_PHY, flx_mask_st20); 1527 } 1528 1529 return status; 1530 } 1531 1532 /** ixgbe_setup_ixfi_x550em - Configure the KR PHY for iXFI mode. 1533 * @hw: pointer to hardware structure 1534 * @speed: the link speed to force 1535 * 1536 * Configures the integrated KR PHY to use iXFI mode. Used to connect an 1537 * internal and external PHY at a specific speed, without autonegotiation. 1538 **/ 1539 static s32 ixgbe_setup_ixfi_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed) 1540 { 1541 struct ixgbe_mac_info *mac = &hw->mac; 1542 s32 status; 1543 u32 reg_val; 1544 1545 /* iXFI is only supported with X552 */ 1546 if (mac->type != ixgbe_mac_X550EM_x) 1547 return IXGBE_ERR_LINK_SETUP; 1548 1549 /* Disable AN and force speed to 10G Serial. */ 1550 status = ixgbe_read_iosf_sb_reg_x550(hw, 1551 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id), 1552 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val); 1553 if (status) 1554 return status; 1555 1556 reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE; 1557 reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK; 1558 1559 /* Select forced link speed for internal PHY. */ 1560 switch (*speed) { 1561 case IXGBE_LINK_SPEED_10GB_FULL: 1562 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G; 1563 break; 1564 case IXGBE_LINK_SPEED_1GB_FULL: 1565 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G; 1566 break; 1567 default: 1568 /* Other link speeds are not supported by internal KR PHY. */ 1569 return IXGBE_ERR_LINK_SETUP; 1570 } 1571 1572 status = ixgbe_write_iosf_sb_reg_x550(hw, 1573 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id), 1574 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val); 1575 if (status) 1576 return status; 1577 1578 /* Additional configuration needed for x550em_x */ 1579 if (hw->mac.type == ixgbe_mac_X550EM_x) { 1580 status = ixgbe_setup_ixfi_x550em_x(hw); 1581 if (status) 1582 return status; 1583 } 1584 1585 /* Toggle port SW reset by AN reset. */ 1586 status = ixgbe_restart_an_internal_phy_x550em(hw); 1587 1588 return status; 1589 } 1590 1591 /** 1592 * ixgbe_supported_sfp_modules_X550em - Check if SFP module type is supported 1593 * @hw: pointer to hardware structure 1594 * @linear: true if SFP module is linear 1595 */ 1596 static s32 ixgbe_supported_sfp_modules_X550em(struct ixgbe_hw *hw, bool *linear) 1597 { 1598 switch (hw->phy.sfp_type) { 1599 case ixgbe_sfp_type_not_present: 1600 return IXGBE_ERR_SFP_NOT_PRESENT; 1601 case ixgbe_sfp_type_da_cu_core0: 1602 case ixgbe_sfp_type_da_cu_core1: 1603 *linear = true; 1604 break; 1605 case ixgbe_sfp_type_srlr_core0: 1606 case ixgbe_sfp_type_srlr_core1: 1607 case ixgbe_sfp_type_da_act_lmt_core0: 1608 case ixgbe_sfp_type_da_act_lmt_core1: 1609 case ixgbe_sfp_type_1g_sx_core0: 1610 case ixgbe_sfp_type_1g_sx_core1: 1611 case ixgbe_sfp_type_1g_lx_core0: 1612 case ixgbe_sfp_type_1g_lx_core1: 1613 *linear = false; 1614 break; 1615 case ixgbe_sfp_type_unknown: 1616 case ixgbe_sfp_type_1g_cu_core0: 1617 case ixgbe_sfp_type_1g_cu_core1: 1618 default: 1619 return IXGBE_ERR_SFP_NOT_SUPPORTED; 1620 } 1621 1622 return 0; 1623 } 1624 1625 /** 1626 * ixgbe_setup_mac_link_sfp_x550em - Configure the KR PHY for SFP. 1627 * @hw: pointer to hardware structure 1628 * @speed: the link speed to force 1629 * @autoneg_wait_to_complete: unused 1630 * 1631 * Configures the extern PHY and the integrated KR PHY for SFP support. 1632 */ 1633 static s32 1634 ixgbe_setup_mac_link_sfp_x550em(struct ixgbe_hw *hw, 1635 ixgbe_link_speed speed, 1636 __always_unused bool autoneg_wait_to_complete) 1637 { 1638 s32 status; 1639 u16 reg_slice, reg_val; 1640 bool setup_linear = false; 1641 1642 /* Check if SFP module is supported and linear */ 1643 status = ixgbe_supported_sfp_modules_X550em(hw, &setup_linear); 1644 1645 /* If no SFP module present, then return success. Return success since 1646 * there is no reason to configure CS4227 and SFP not present error is 1647 * not accepted in the setup MAC link flow. 1648 */ 1649 if (status == IXGBE_ERR_SFP_NOT_PRESENT) 1650 return 0; 1651 1652 if (status) 1653 return status; 1654 1655 /* Configure internal PHY for KR/KX. */ 1656 ixgbe_setup_kr_speed_x550em(hw, speed); 1657 1658 /* Configure CS4227 LINE side to proper mode. */ 1659 reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB + (hw->bus.lan_id << 12); 1660 if (setup_linear) 1661 reg_val = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1; 1662 else 1663 reg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1; 1664 1665 status = hw->link.ops.write_link(hw, hw->link.addr, reg_slice, 1666 reg_val); 1667 1668 return status; 1669 } 1670 1671 /** 1672 * ixgbe_setup_sfi_x550a - Configure the internal PHY for native SFI mode 1673 * @hw: pointer to hardware structure 1674 * @speed: the link speed to force 1675 * 1676 * Configures the integrated PHY for native SFI mode. Used to connect the 1677 * internal PHY directly to an SFP cage, without autonegotiation. 1678 **/ 1679 static s32 ixgbe_setup_sfi_x550a(struct ixgbe_hw *hw, ixgbe_link_speed *speed) 1680 { 1681 struct ixgbe_mac_info *mac = &hw->mac; 1682 s32 status; 1683 u32 reg_val; 1684 1685 /* Disable all AN and force speed to 10G Serial. */ 1686 status = mac->ops.read_iosf_sb_reg(hw, 1687 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id), 1688 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val); 1689 if (status) 1690 return status; 1691 1692 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN_EN; 1693 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN37_EN; 1694 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SGMII_EN; 1695 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_MASK; 1696 1697 /* Select forced link speed for internal PHY. */ 1698 switch (*speed) { 1699 case IXGBE_LINK_SPEED_10GB_FULL: 1700 reg_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_10G; 1701 break; 1702 case IXGBE_LINK_SPEED_1GB_FULL: 1703 reg_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_1G; 1704 break; 1705 default: 1706 /* Other link speeds are not supported by internal PHY. */ 1707 return IXGBE_ERR_LINK_SETUP; 1708 } 1709 1710 status = mac->ops.write_iosf_sb_reg(hw, 1711 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id), 1712 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val); 1713 1714 /* Toggle port SW reset by AN reset. */ 1715 status = ixgbe_restart_an_internal_phy_x550em(hw); 1716 1717 return status; 1718 } 1719 1720 /** 1721 * ixgbe_setup_mac_link_sfp_n - Setup internal PHY for native SFP 1722 * @hw: pointer to hardware structure 1723 * @speed: link speed 1724 * @autoneg_wait_to_complete: unused 1725 * 1726 * Configure the the integrated PHY for native SFP support. 1727 */ 1728 static s32 1729 ixgbe_setup_mac_link_sfp_n(struct ixgbe_hw *hw, ixgbe_link_speed speed, 1730 __always_unused bool autoneg_wait_to_complete) 1731 { 1732 bool setup_linear = false; 1733 u32 reg_phy_int; 1734 s32 ret_val; 1735 1736 /* Check if SFP module is supported and linear */ 1737 ret_val = ixgbe_supported_sfp_modules_X550em(hw, &setup_linear); 1738 1739 /* If no SFP module present, then return success. Return success since 1740 * SFP not present error is not excepted in the setup MAC link flow. 1741 */ 1742 if (ret_val == IXGBE_ERR_SFP_NOT_PRESENT) 1743 return 0; 1744 1745 if (ret_val) 1746 return ret_val; 1747 1748 /* Configure internal PHY for native SFI based on module type */ 1749 ret_val = hw->mac.ops.read_iosf_sb_reg(hw, 1750 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id), 1751 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_phy_int); 1752 if (ret_val) 1753 return ret_val; 1754 1755 reg_phy_int &= IXGBE_KRM_PMD_FLX_MASK_ST20_SFI_10G_DA; 1756 if (!setup_linear) 1757 reg_phy_int |= IXGBE_KRM_PMD_FLX_MASK_ST20_SFI_10G_SR; 1758 1759 ret_val = hw->mac.ops.write_iosf_sb_reg(hw, 1760 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id), 1761 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_phy_int); 1762 if (ret_val) 1763 return ret_val; 1764 1765 /* Setup SFI internal link. */ 1766 return ixgbe_setup_sfi_x550a(hw, &speed); 1767 } 1768 1769 /** 1770 * ixgbe_setup_mac_link_sfp_x550a - Setup internal PHY for SFP 1771 * @hw: pointer to hardware structure 1772 * @speed: link speed 1773 * @autoneg_wait_to_complete: unused 1774 * 1775 * Configure the the integrated PHY for SFP support. 1776 */ 1777 static s32 1778 ixgbe_setup_mac_link_sfp_x550a(struct ixgbe_hw *hw, ixgbe_link_speed speed, 1779 __always_unused bool autoneg_wait_to_complete) 1780 { 1781 u32 reg_slice, slice_offset; 1782 bool setup_linear = false; 1783 u16 reg_phy_ext; 1784 s32 ret_val; 1785 1786 /* Check if SFP module is supported and linear */ 1787 ret_val = ixgbe_supported_sfp_modules_X550em(hw, &setup_linear); 1788 1789 /* If no SFP module present, then return success. Return success since 1790 * SFP not present error is not excepted in the setup MAC link flow. 1791 */ 1792 if (ret_val == IXGBE_ERR_SFP_NOT_PRESENT) 1793 return 0; 1794 1795 if (ret_val) 1796 return ret_val; 1797 1798 /* Configure internal PHY for KR/KX. */ 1799 ixgbe_setup_kr_speed_x550em(hw, speed); 1800 1801 if (hw->phy.mdio.prtad == MDIO_PRTAD_NONE) 1802 return IXGBE_ERR_PHY_ADDR_INVALID; 1803 1804 /* Get external PHY SKU id */ 1805 ret_val = hw->phy.ops.read_reg(hw, IXGBE_CS4227_EFUSE_PDF_SKU, 1806 IXGBE_MDIO_ZERO_DEV_TYPE, ®_phy_ext); 1807 if (ret_val) 1808 return ret_val; 1809 1810 /* When configuring quad port CS4223, the MAC instance is part 1811 * of the slice offset. 1812 */ 1813 if (reg_phy_ext == IXGBE_CS4223_SKU_ID) 1814 slice_offset = (hw->bus.lan_id + 1815 (hw->bus.instance_id << 1)) << 12; 1816 else 1817 slice_offset = hw->bus.lan_id << 12; 1818 1819 /* Configure CS4227/CS4223 LINE side to proper mode. */ 1820 reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB + slice_offset; 1821 1822 ret_val = hw->phy.ops.read_reg(hw, reg_slice, 1823 IXGBE_MDIO_ZERO_DEV_TYPE, ®_phy_ext); 1824 if (ret_val) 1825 return ret_val; 1826 1827 reg_phy_ext &= ~((IXGBE_CS4227_EDC_MODE_CX1 << 1) | 1828 (IXGBE_CS4227_EDC_MODE_SR << 1)); 1829 1830 if (setup_linear) 1831 reg_phy_ext |= (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 1; 1832 else 1833 reg_phy_ext |= (IXGBE_CS4227_EDC_MODE_SR << 1) | 1; 1834 1835 ret_val = hw->phy.ops.write_reg(hw, reg_slice, 1836 IXGBE_MDIO_ZERO_DEV_TYPE, reg_phy_ext); 1837 if (ret_val) 1838 return ret_val; 1839 1840 /* Flush previous write with a read */ 1841 return hw->phy.ops.read_reg(hw, reg_slice, 1842 IXGBE_MDIO_ZERO_DEV_TYPE, ®_phy_ext); 1843 } 1844 1845 /** 1846 * ixgbe_setup_mac_link_t_X550em - Sets the auto advertised link speed 1847 * @hw: pointer to hardware structure 1848 * @speed: new link speed 1849 * @autoneg_wait: true when waiting for completion is needed 1850 * 1851 * Setup internal/external PHY link speed based on link speed, then set 1852 * external PHY auto advertised link speed. 1853 * 1854 * Returns error status for any failure 1855 **/ 1856 static s32 ixgbe_setup_mac_link_t_X550em(struct ixgbe_hw *hw, 1857 ixgbe_link_speed speed, 1858 bool autoneg_wait) 1859 { 1860 s32 status; 1861 ixgbe_link_speed force_speed; 1862 1863 /* Setup internal/external PHY link speed to iXFI (10G), unless 1864 * only 1G is auto advertised then setup KX link. 1865 */ 1866 if (speed & IXGBE_LINK_SPEED_10GB_FULL) 1867 force_speed = IXGBE_LINK_SPEED_10GB_FULL; 1868 else 1869 force_speed = IXGBE_LINK_SPEED_1GB_FULL; 1870 1871 /* If X552 and internal link mode is XFI, then setup XFI internal link. 1872 */ 1873 if (hw->mac.type == ixgbe_mac_X550EM_x && 1874 !(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) { 1875 status = ixgbe_setup_ixfi_x550em(hw, &force_speed); 1876 1877 if (status) 1878 return status; 1879 } 1880 1881 return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait); 1882 } 1883 1884 /** ixgbe_check_link_t_X550em - Determine link and speed status 1885 * @hw: pointer to hardware structure 1886 * @speed: pointer to link speed 1887 * @link_up: true when link is up 1888 * @link_up_wait_to_complete: bool used to wait for link up or not 1889 * 1890 * Check that both the MAC and X557 external PHY have link. 1891 **/ 1892 static s32 ixgbe_check_link_t_X550em(struct ixgbe_hw *hw, 1893 ixgbe_link_speed *speed, 1894 bool *link_up, 1895 bool link_up_wait_to_complete) 1896 { 1897 u32 status; 1898 u16 i, autoneg_status; 1899 1900 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper) 1901 return IXGBE_ERR_CONFIG; 1902 1903 status = ixgbe_check_mac_link_generic(hw, speed, link_up, 1904 link_up_wait_to_complete); 1905 1906 /* If check link fails or MAC link is not up, then return */ 1907 if (status || !(*link_up)) 1908 return status; 1909 1910 /* MAC link is up, so check external PHY link. 1911 * Link status is latching low, and can only be used to detect link 1912 * drop, and not the current status of the link without performing 1913 * back-to-back reads. 1914 */ 1915 for (i = 0; i < 2; i++) { 1916 status = hw->phy.ops.read_reg(hw, MDIO_STAT1, MDIO_MMD_AN, 1917 &autoneg_status); 1918 1919 if (status) 1920 return status; 1921 } 1922 1923 /* If external PHY link is not up, then indicate link not up */ 1924 if (!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS)) 1925 *link_up = false; 1926 1927 return 0; 1928 } 1929 1930 /** 1931 * ixgbe_setup_sgmii - Set up link for sgmii 1932 * @hw: pointer to hardware structure 1933 * @speed: unused 1934 * @autoneg_wait_to_complete: unused 1935 */ 1936 static s32 1937 ixgbe_setup_sgmii(struct ixgbe_hw *hw, __always_unused ixgbe_link_speed speed, 1938 __always_unused bool autoneg_wait_to_complete) 1939 { 1940 struct ixgbe_mac_info *mac = &hw->mac; 1941 u32 lval, sval, flx_val; 1942 s32 rc; 1943 1944 rc = mac->ops.read_iosf_sb_reg(hw, 1945 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id), 1946 IXGBE_SB_IOSF_TARGET_KR_PHY, &lval); 1947 if (rc) 1948 return rc; 1949 1950 lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE; 1951 lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK; 1952 lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_SGMII_EN; 1953 lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CLAUSE_37_EN; 1954 lval |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G; 1955 rc = mac->ops.write_iosf_sb_reg(hw, 1956 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id), 1957 IXGBE_SB_IOSF_TARGET_KR_PHY, lval); 1958 if (rc) 1959 return rc; 1960 1961 rc = mac->ops.read_iosf_sb_reg(hw, 1962 IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id), 1963 IXGBE_SB_IOSF_TARGET_KR_PHY, &sval); 1964 if (rc) 1965 return rc; 1966 1967 sval |= IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_10_D; 1968 sval |= IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_100_D; 1969 rc = mac->ops.write_iosf_sb_reg(hw, 1970 IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id), 1971 IXGBE_SB_IOSF_TARGET_KR_PHY, sval); 1972 if (rc) 1973 return rc; 1974 1975 rc = mac->ops.read_iosf_sb_reg(hw, 1976 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id), 1977 IXGBE_SB_IOSF_TARGET_KR_PHY, &flx_val); 1978 if (rc) 1979 return rc; 1980 1981 rc = mac->ops.read_iosf_sb_reg(hw, 1982 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id), 1983 IXGBE_SB_IOSF_TARGET_KR_PHY, &flx_val); 1984 if (rc) 1985 return rc; 1986 1987 flx_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_MASK; 1988 flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_1G; 1989 flx_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN_EN; 1990 flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SGMII_EN; 1991 flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_AN37_EN; 1992 1993 rc = mac->ops.write_iosf_sb_reg(hw, 1994 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id), 1995 IXGBE_SB_IOSF_TARGET_KR_PHY, flx_val); 1996 if (rc) 1997 return rc; 1998 1999 rc = ixgbe_restart_an_internal_phy_x550em(hw); 2000 return rc; 2001 } 2002 2003 /** 2004 * ixgbe_setup_sgmii_fw - Set up link for sgmii with firmware-controlled PHYs 2005 * @hw: pointer to hardware structure 2006 * @speed: the link speed to force 2007 * @autoneg_wait: true when waiting for completion is needed 2008 */ 2009 static s32 ixgbe_setup_sgmii_fw(struct ixgbe_hw *hw, ixgbe_link_speed speed, 2010 bool autoneg_wait) 2011 { 2012 struct ixgbe_mac_info *mac = &hw->mac; 2013 u32 lval, sval, flx_val; 2014 s32 rc; 2015 2016 rc = mac->ops.read_iosf_sb_reg(hw, 2017 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id), 2018 IXGBE_SB_IOSF_TARGET_KR_PHY, &lval); 2019 if (rc) 2020 return rc; 2021 2022 lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE; 2023 lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK; 2024 lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_SGMII_EN; 2025 lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CLAUSE_37_EN; 2026 lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G; 2027 rc = mac->ops.write_iosf_sb_reg(hw, 2028 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id), 2029 IXGBE_SB_IOSF_TARGET_KR_PHY, lval); 2030 if (rc) 2031 return rc; 2032 2033 rc = mac->ops.read_iosf_sb_reg(hw, 2034 IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id), 2035 IXGBE_SB_IOSF_TARGET_KR_PHY, &sval); 2036 if (rc) 2037 return rc; 2038 2039 sval &= ~IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_10_D; 2040 sval &= ~IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_100_D; 2041 rc = mac->ops.write_iosf_sb_reg(hw, 2042 IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id), 2043 IXGBE_SB_IOSF_TARGET_KR_PHY, sval); 2044 if (rc) 2045 return rc; 2046 2047 rc = mac->ops.write_iosf_sb_reg(hw, 2048 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id), 2049 IXGBE_SB_IOSF_TARGET_KR_PHY, lval); 2050 if (rc) 2051 return rc; 2052 2053 rc = mac->ops.read_iosf_sb_reg(hw, 2054 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id), 2055 IXGBE_SB_IOSF_TARGET_KR_PHY, &flx_val); 2056 if (rc) 2057 return rc; 2058 2059 flx_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_MASK; 2060 flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_AN; 2061 flx_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN_EN; 2062 flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SGMII_EN; 2063 flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_AN37_EN; 2064 2065 rc = mac->ops.write_iosf_sb_reg(hw, 2066 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id), 2067 IXGBE_SB_IOSF_TARGET_KR_PHY, flx_val); 2068 if (rc) 2069 return rc; 2070 2071 ixgbe_restart_an_internal_phy_x550em(hw); 2072 2073 return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait); 2074 } 2075 2076 /** 2077 * ixgbe_fc_autoneg_sgmii_x550em_a - Enable flow control IEEE clause 37 2078 * @hw: pointer to hardware structure 2079 * 2080 * Enable flow control according to IEEE clause 37. 2081 */ 2082 static void ixgbe_fc_autoneg_sgmii_x550em_a(struct ixgbe_hw *hw) 2083 { 2084 s32 status = IXGBE_ERR_FC_NOT_NEGOTIATED; 2085 u32 info[FW_PHY_ACT_DATA_COUNT] = { 0 }; 2086 ixgbe_link_speed speed; 2087 bool link_up; 2088 2089 /* AN should have completed when the cable was plugged in. 2090 * Look for reasons to bail out. Bail out if: 2091 * - FC autoneg is disabled, or if 2092 * - link is not up. 2093 */ 2094 if (hw->fc.disable_fc_autoneg) 2095 goto out; 2096 2097 hw->mac.ops.check_link(hw, &speed, &link_up, false); 2098 if (!link_up) 2099 goto out; 2100 2101 /* Check if auto-negotiation has completed */ 2102 status = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_GET_LINK_INFO, &info); 2103 if (status || !(info[0] & FW_PHY_ACT_GET_LINK_INFO_AN_COMPLETE)) { 2104 status = IXGBE_ERR_FC_NOT_NEGOTIATED; 2105 goto out; 2106 } 2107 2108 /* Negotiate the flow control */ 2109 status = ixgbe_negotiate_fc(hw, info[0], info[0], 2110 FW_PHY_ACT_GET_LINK_INFO_FC_RX, 2111 FW_PHY_ACT_GET_LINK_INFO_FC_TX, 2112 FW_PHY_ACT_GET_LINK_INFO_LP_FC_RX, 2113 FW_PHY_ACT_GET_LINK_INFO_LP_FC_TX); 2114 2115 out: 2116 if (!status) { 2117 hw->fc.fc_was_autonegged = true; 2118 } else { 2119 hw->fc.fc_was_autonegged = false; 2120 hw->fc.current_mode = hw->fc.requested_mode; 2121 } 2122 } 2123 2124 /** ixgbe_init_mac_link_ops_X550em_a - Init mac link function pointers 2125 * @hw: pointer to hardware structure 2126 **/ 2127 static void ixgbe_init_mac_link_ops_X550em_a(struct ixgbe_hw *hw) 2128 { 2129 struct ixgbe_mac_info *mac = &hw->mac; 2130 2131 switch (mac->ops.get_media_type(hw)) { 2132 case ixgbe_media_type_fiber: 2133 mac->ops.setup_fc = NULL; 2134 mac->ops.fc_autoneg = ixgbe_fc_autoneg_fiber_x550em_a; 2135 break; 2136 case ixgbe_media_type_copper: 2137 if (hw->device_id != IXGBE_DEV_ID_X550EM_A_1G_T && 2138 hw->device_id != IXGBE_DEV_ID_X550EM_A_1G_T_L) { 2139 mac->ops.setup_link = ixgbe_setup_mac_link_t_X550em; 2140 break; 2141 } 2142 mac->ops.fc_autoneg = ixgbe_fc_autoneg_sgmii_x550em_a; 2143 mac->ops.setup_fc = ixgbe_fc_autoneg_fw; 2144 mac->ops.setup_link = ixgbe_setup_sgmii_fw; 2145 mac->ops.check_link = ixgbe_check_mac_link_generic; 2146 break; 2147 case ixgbe_media_type_backplane: 2148 mac->ops.fc_autoneg = ixgbe_fc_autoneg_backplane_x550em_a; 2149 mac->ops.setup_fc = ixgbe_setup_fc_backplane_x550em_a; 2150 break; 2151 default: 2152 break; 2153 } 2154 } 2155 2156 /** ixgbe_init_mac_link_ops_X550em - init mac link function pointers 2157 * @hw: pointer to hardware structure 2158 **/ 2159 static void ixgbe_init_mac_link_ops_X550em(struct ixgbe_hw *hw) 2160 { 2161 struct ixgbe_mac_info *mac = &hw->mac; 2162 2163 mac->ops.setup_fc = ixgbe_setup_fc_x550em; 2164 2165 switch (mac->ops.get_media_type(hw)) { 2166 case ixgbe_media_type_fiber: 2167 /* CS4227 does not support autoneg, so disable the laser control 2168 * functions for SFP+ fiber 2169 */ 2170 mac->ops.disable_tx_laser = NULL; 2171 mac->ops.enable_tx_laser = NULL; 2172 mac->ops.flap_tx_laser = NULL; 2173 mac->ops.setup_link = ixgbe_setup_mac_link_multispeed_fiber; 2174 switch (hw->device_id) { 2175 case IXGBE_DEV_ID_X550EM_A_SFP_N: 2176 mac->ops.setup_mac_link = ixgbe_setup_mac_link_sfp_n; 2177 break; 2178 case IXGBE_DEV_ID_X550EM_A_SFP: 2179 mac->ops.setup_mac_link = 2180 ixgbe_setup_mac_link_sfp_x550a; 2181 break; 2182 default: 2183 mac->ops.setup_mac_link = 2184 ixgbe_setup_mac_link_sfp_x550em; 2185 break; 2186 } 2187 mac->ops.set_rate_select_speed = 2188 ixgbe_set_soft_rate_select_speed; 2189 break; 2190 case ixgbe_media_type_copper: 2191 if (hw->device_id == IXGBE_DEV_ID_X550EM_X_1G_T) 2192 break; 2193 mac->ops.setup_link = ixgbe_setup_mac_link_t_X550em; 2194 mac->ops.setup_fc = ixgbe_setup_fc_generic; 2195 mac->ops.check_link = ixgbe_check_link_t_X550em; 2196 break; 2197 case ixgbe_media_type_backplane: 2198 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_SGMII || 2199 hw->device_id == IXGBE_DEV_ID_X550EM_A_SGMII_L) 2200 mac->ops.setup_link = ixgbe_setup_sgmii; 2201 break; 2202 default: 2203 break; 2204 } 2205 2206 /* Additional modification for X550em_a devices */ 2207 if (hw->mac.type == ixgbe_mac_x550em_a) 2208 ixgbe_init_mac_link_ops_X550em_a(hw); 2209 } 2210 2211 /** ixgbe_setup_sfp_modules_X550em - Setup SFP module 2212 * @hw: pointer to hardware structure 2213 */ 2214 static s32 ixgbe_setup_sfp_modules_X550em(struct ixgbe_hw *hw) 2215 { 2216 s32 status; 2217 bool linear; 2218 2219 /* Check if SFP module is supported */ 2220 status = ixgbe_supported_sfp_modules_X550em(hw, &linear); 2221 if (status) 2222 return status; 2223 2224 ixgbe_init_mac_link_ops_X550em(hw); 2225 hw->phy.ops.reset = NULL; 2226 2227 return 0; 2228 } 2229 2230 /** ixgbe_get_link_capabilities_x550em - Determines link capabilities 2231 * @hw: pointer to hardware structure 2232 * @speed: pointer to link speed 2233 * @autoneg: true when autoneg or autotry is enabled 2234 **/ 2235 static s32 ixgbe_get_link_capabilities_X550em(struct ixgbe_hw *hw, 2236 ixgbe_link_speed *speed, 2237 bool *autoneg) 2238 { 2239 if (hw->phy.type == ixgbe_phy_fw) { 2240 *autoneg = true; 2241 *speed = hw->phy.speeds_supported; 2242 return 0; 2243 } 2244 2245 /* SFP */ 2246 if (hw->phy.media_type == ixgbe_media_type_fiber) { 2247 /* CS4227 SFP must not enable auto-negotiation */ 2248 *autoneg = false; 2249 2250 if (hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 || 2251 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1) { 2252 *speed = IXGBE_LINK_SPEED_1GB_FULL; 2253 return 0; 2254 } 2255 2256 /* Link capabilities are based on SFP */ 2257 if (hw->phy.multispeed_fiber) 2258 *speed = IXGBE_LINK_SPEED_10GB_FULL | 2259 IXGBE_LINK_SPEED_1GB_FULL; 2260 else 2261 *speed = IXGBE_LINK_SPEED_10GB_FULL; 2262 } else { 2263 switch (hw->phy.type) { 2264 case ixgbe_phy_x550em_kx4: 2265 *speed = IXGBE_LINK_SPEED_1GB_FULL | 2266 IXGBE_LINK_SPEED_2_5GB_FULL | 2267 IXGBE_LINK_SPEED_10GB_FULL; 2268 break; 2269 case ixgbe_phy_x550em_xfi: 2270 *speed = IXGBE_LINK_SPEED_1GB_FULL | 2271 IXGBE_LINK_SPEED_10GB_FULL; 2272 break; 2273 case ixgbe_phy_ext_1g_t: 2274 case ixgbe_phy_sgmii: 2275 *speed = IXGBE_LINK_SPEED_1GB_FULL; 2276 break; 2277 case ixgbe_phy_x550em_kr: 2278 if (hw->mac.type == ixgbe_mac_x550em_a) { 2279 /* check different backplane modes */ 2280 if (hw->phy.nw_mng_if_sel & 2281 IXGBE_NW_MNG_IF_SEL_PHY_SPEED_2_5G) { 2282 *speed = IXGBE_LINK_SPEED_2_5GB_FULL; 2283 break; 2284 } else if (hw->device_id == 2285 IXGBE_DEV_ID_X550EM_A_KR_L) { 2286 *speed = IXGBE_LINK_SPEED_1GB_FULL; 2287 break; 2288 } 2289 } 2290 /* fall through */ 2291 default: 2292 *speed = IXGBE_LINK_SPEED_10GB_FULL | 2293 IXGBE_LINK_SPEED_1GB_FULL; 2294 break; 2295 } 2296 *autoneg = true; 2297 } 2298 return 0; 2299 } 2300 2301 /** 2302 * ixgbe_get_lasi_ext_t_x550em - Determime external Base T PHY interrupt cause 2303 * @hw: pointer to hardware structure 2304 * @lsc: pointer to boolean flag which indicates whether external Base T 2305 * PHY interrupt is lsc 2306 * 2307 * Determime if external Base T PHY interrupt cause is high temperature 2308 * failure alarm or link status change. 2309 * 2310 * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature 2311 * failure alarm, else return PHY access status. 2312 **/ 2313 static s32 ixgbe_get_lasi_ext_t_x550em(struct ixgbe_hw *hw, bool *lsc) 2314 { 2315 u32 status; 2316 u16 reg; 2317 2318 *lsc = false; 2319 2320 /* Vendor alarm triggered */ 2321 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG, 2322 MDIO_MMD_VEND1, 2323 ®); 2324 2325 if (status || !(reg & IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN)) 2326 return status; 2327 2328 /* Vendor Auto-Neg alarm triggered or Global alarm 1 triggered */ 2329 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_FLAG, 2330 MDIO_MMD_VEND1, 2331 ®); 2332 2333 if (status || !(reg & (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN | 2334 IXGBE_MDIO_GLOBAL_ALARM_1_INT))) 2335 return status; 2336 2337 /* Global alarm triggered */ 2338 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_ALARM_1, 2339 MDIO_MMD_VEND1, 2340 ®); 2341 2342 if (status) 2343 return status; 2344 2345 /* If high temperature failure, then return over temp error and exit */ 2346 if (reg & IXGBE_MDIO_GLOBAL_ALM_1_HI_TMP_FAIL) { 2347 /* power down the PHY in case the PHY FW didn't already */ 2348 ixgbe_set_copper_phy_power(hw, false); 2349 return IXGBE_ERR_OVERTEMP; 2350 } 2351 if (reg & IXGBE_MDIO_GLOBAL_ALM_1_DEV_FAULT) { 2352 /* device fault alarm triggered */ 2353 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_FAULT_MSG, 2354 MDIO_MMD_VEND1, 2355 ®); 2356 if (status) 2357 return status; 2358 2359 /* if device fault was due to high temp alarm handle and exit */ 2360 if (reg == IXGBE_MDIO_GLOBAL_FAULT_MSG_HI_TMP) { 2361 /* power down the PHY in case the PHY FW didn't */ 2362 ixgbe_set_copper_phy_power(hw, false); 2363 return IXGBE_ERR_OVERTEMP; 2364 } 2365 } 2366 2367 /* Vendor alarm 2 triggered */ 2368 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG, 2369 MDIO_MMD_AN, ®); 2370 2371 if (status || !(reg & IXGBE_MDIO_GLOBAL_STD_ALM2_INT)) 2372 return status; 2373 2374 /* link connect/disconnect event occurred */ 2375 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM2, 2376 MDIO_MMD_AN, ®); 2377 2378 if (status) 2379 return status; 2380 2381 /* Indicate LSC */ 2382 if (reg & IXGBE_MDIO_AUTO_NEG_VEN_LSC) 2383 *lsc = true; 2384 2385 return 0; 2386 } 2387 2388 /** 2389 * ixgbe_enable_lasi_ext_t_x550em - Enable external Base T PHY interrupts 2390 * @hw: pointer to hardware structure 2391 * 2392 * Enable link status change and temperature failure alarm for the external 2393 * Base T PHY 2394 * 2395 * Returns PHY access status 2396 **/ 2397 static s32 ixgbe_enable_lasi_ext_t_x550em(struct ixgbe_hw *hw) 2398 { 2399 u32 status; 2400 u16 reg; 2401 bool lsc; 2402 2403 /* Clear interrupt flags */ 2404 status = ixgbe_get_lasi_ext_t_x550em(hw, &lsc); 2405 2406 /* Enable link status change alarm */ 2407 2408 /* Enable the LASI interrupts on X552 devices to receive notifications 2409 * of the link configurations of the external PHY and correspondingly 2410 * support the configuration of the internal iXFI link, since iXFI does 2411 * not support auto-negotiation. This is not required for X553 devices 2412 * having KR support, which performs auto-negotiations and which is used 2413 * as the internal link to the external PHY. Hence adding a check here 2414 * to avoid enabling LASI interrupts for X553 devices. 2415 */ 2416 if (hw->mac.type != ixgbe_mac_x550em_a) { 2417 status = hw->phy.ops.read_reg(hw, 2418 IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK, 2419 MDIO_MMD_AN, ®); 2420 if (status) 2421 return status; 2422 2423 reg |= IXGBE_MDIO_PMA_TX_VEN_LASI_INT_EN; 2424 2425 status = hw->phy.ops.write_reg(hw, 2426 IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK, 2427 MDIO_MMD_AN, reg); 2428 if (status) 2429 return status; 2430 } 2431 2432 /* Enable high temperature failure and global fault alarms */ 2433 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK, 2434 MDIO_MMD_VEND1, 2435 ®); 2436 if (status) 2437 return status; 2438 2439 reg |= (IXGBE_MDIO_GLOBAL_INT_HI_TEMP_EN | 2440 IXGBE_MDIO_GLOBAL_INT_DEV_FAULT_EN); 2441 2442 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK, 2443 MDIO_MMD_VEND1, 2444 reg); 2445 if (status) 2446 return status; 2447 2448 /* Enable vendor Auto-Neg alarm and Global Interrupt Mask 1 alarm */ 2449 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK, 2450 MDIO_MMD_VEND1, 2451 ®); 2452 if (status) 2453 return status; 2454 2455 reg |= (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN | 2456 IXGBE_MDIO_GLOBAL_ALARM_1_INT); 2457 2458 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK, 2459 MDIO_MMD_VEND1, 2460 reg); 2461 if (status) 2462 return status; 2463 2464 /* Enable chip-wide vendor alarm */ 2465 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK, 2466 MDIO_MMD_VEND1, 2467 ®); 2468 if (status) 2469 return status; 2470 2471 reg |= IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN; 2472 2473 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK, 2474 MDIO_MMD_VEND1, 2475 reg); 2476 2477 return status; 2478 } 2479 2480 /** 2481 * ixgbe_handle_lasi_ext_t_x550em - Handle external Base T PHY interrupt 2482 * @hw: pointer to hardware structure 2483 * 2484 * Handle external Base T PHY interrupt. If high temperature 2485 * failure alarm then return error, else if link status change 2486 * then setup internal/external PHY link 2487 * 2488 * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature 2489 * failure alarm, else return PHY access status. 2490 **/ 2491 static s32 ixgbe_handle_lasi_ext_t_x550em(struct ixgbe_hw *hw) 2492 { 2493 struct ixgbe_phy_info *phy = &hw->phy; 2494 bool lsc; 2495 u32 status; 2496 2497 status = ixgbe_get_lasi_ext_t_x550em(hw, &lsc); 2498 if (status) 2499 return status; 2500 2501 if (lsc && phy->ops.setup_internal_link) 2502 return phy->ops.setup_internal_link(hw); 2503 2504 return 0; 2505 } 2506 2507 /** 2508 * ixgbe_setup_kr_speed_x550em - Configure the KR PHY for link speed. 2509 * @hw: pointer to hardware structure 2510 * @speed: link speed 2511 * 2512 * Configures the integrated KR PHY. 2513 **/ 2514 static s32 ixgbe_setup_kr_speed_x550em(struct ixgbe_hw *hw, 2515 ixgbe_link_speed speed) 2516 { 2517 s32 status; 2518 u32 reg_val; 2519 2520 status = hw->mac.ops.read_iosf_sb_reg(hw, 2521 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id), 2522 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val); 2523 if (status) 2524 return status; 2525 2526 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE; 2527 reg_val &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR | 2528 IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX); 2529 2530 /* Advertise 10G support. */ 2531 if (speed & IXGBE_LINK_SPEED_10GB_FULL) 2532 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR; 2533 2534 /* Advertise 1G support. */ 2535 if (speed & IXGBE_LINK_SPEED_1GB_FULL) 2536 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX; 2537 2538 status = hw->mac.ops.write_iosf_sb_reg(hw, 2539 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id), 2540 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val); 2541 2542 if (hw->mac.type == ixgbe_mac_x550em_a) { 2543 /* Set lane mode to KR auto negotiation */ 2544 status = hw->mac.ops.read_iosf_sb_reg(hw, 2545 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id), 2546 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val); 2547 2548 if (status) 2549 return status; 2550 2551 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_MASK; 2552 reg_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_AN; 2553 reg_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_AN_EN; 2554 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN37_EN; 2555 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SGMII_EN; 2556 2557 status = hw->mac.ops.write_iosf_sb_reg(hw, 2558 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id), 2559 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val); 2560 } 2561 2562 return ixgbe_restart_an_internal_phy_x550em(hw); 2563 } 2564 2565 /** 2566 * ixgbe_setup_kr_x550em - Configure the KR PHY 2567 * @hw: pointer to hardware structure 2568 **/ 2569 static s32 ixgbe_setup_kr_x550em(struct ixgbe_hw *hw) 2570 { 2571 /* leave link alone for 2.5G */ 2572 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_2_5GB_FULL) 2573 return 0; 2574 2575 if (ixgbe_check_reset_blocked(hw)) 2576 return 0; 2577 2578 return ixgbe_setup_kr_speed_x550em(hw, hw->phy.autoneg_advertised); 2579 } 2580 2581 /** ixgbe_ext_phy_t_x550em_get_link - Get ext phy link status 2582 * @hw: address of hardware structure 2583 * @link_up: address of boolean to indicate link status 2584 * 2585 * Returns error code if unable to get link status. 2586 **/ 2587 static s32 ixgbe_ext_phy_t_x550em_get_link(struct ixgbe_hw *hw, bool *link_up) 2588 { 2589 u32 ret; 2590 u16 autoneg_status; 2591 2592 *link_up = false; 2593 2594 /* read this twice back to back to indicate current status */ 2595 ret = hw->phy.ops.read_reg(hw, MDIO_STAT1, MDIO_MMD_AN, 2596 &autoneg_status); 2597 if (ret) 2598 return ret; 2599 2600 ret = hw->phy.ops.read_reg(hw, MDIO_STAT1, MDIO_MMD_AN, 2601 &autoneg_status); 2602 if (ret) 2603 return ret; 2604 2605 *link_up = !!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS); 2606 2607 return 0; 2608 } 2609 2610 /** ixgbe_setup_internal_phy_t_x550em - Configure KR PHY to X557 link 2611 * @hw: point to hardware structure 2612 * 2613 * Configures the link between the integrated KR PHY and the external X557 PHY 2614 * The driver will call this function when it gets a link status change 2615 * interrupt from the X557 PHY. This function configures the link speed 2616 * between the PHYs to match the link speed of the BASE-T link. 2617 * 2618 * A return of a non-zero value indicates an error, and the base driver should 2619 * not report link up. 2620 **/ 2621 static s32 ixgbe_setup_internal_phy_t_x550em(struct ixgbe_hw *hw) 2622 { 2623 ixgbe_link_speed force_speed; 2624 bool link_up; 2625 u32 status; 2626 u16 speed; 2627 2628 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper) 2629 return IXGBE_ERR_CONFIG; 2630 2631 if (!(hw->mac.type == ixgbe_mac_X550EM_x && 2632 !(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE))) { 2633 speed = IXGBE_LINK_SPEED_10GB_FULL | 2634 IXGBE_LINK_SPEED_1GB_FULL; 2635 return ixgbe_setup_kr_speed_x550em(hw, speed); 2636 } 2637 2638 /* If link is not up, then there is no setup necessary so return */ 2639 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up); 2640 if (status) 2641 return status; 2642 2643 if (!link_up) 2644 return 0; 2645 2646 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_STAT, 2647 MDIO_MMD_AN, 2648 &speed); 2649 if (status) 2650 return status; 2651 2652 /* If link is not still up, then no setup is necessary so return */ 2653 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up); 2654 if (status) 2655 return status; 2656 2657 if (!link_up) 2658 return 0; 2659 2660 /* clear everything but the speed and duplex bits */ 2661 speed &= IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_MASK; 2662 2663 switch (speed) { 2664 case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB_FULL: 2665 force_speed = IXGBE_LINK_SPEED_10GB_FULL; 2666 break; 2667 case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB_FULL: 2668 force_speed = IXGBE_LINK_SPEED_1GB_FULL; 2669 break; 2670 default: 2671 /* Internal PHY does not support anything else */ 2672 return IXGBE_ERR_INVALID_LINK_SETTINGS; 2673 } 2674 2675 return ixgbe_setup_ixfi_x550em(hw, &force_speed); 2676 } 2677 2678 /** ixgbe_reset_phy_t_X550em - Performs X557 PHY reset and enables LASI 2679 * @hw: pointer to hardware structure 2680 **/ 2681 static s32 ixgbe_reset_phy_t_X550em(struct ixgbe_hw *hw) 2682 { 2683 s32 status; 2684 2685 status = ixgbe_reset_phy_generic(hw); 2686 2687 if (status) 2688 return status; 2689 2690 /* Configure Link Status Alarm and Temperature Threshold interrupts */ 2691 return ixgbe_enable_lasi_ext_t_x550em(hw); 2692 } 2693 2694 /** 2695 * ixgbe_led_on_t_x550em - Turns on the software controllable LEDs. 2696 * @hw: pointer to hardware structure 2697 * @led_idx: led number to turn on 2698 **/ 2699 static s32 ixgbe_led_on_t_x550em(struct ixgbe_hw *hw, u32 led_idx) 2700 { 2701 u16 phy_data; 2702 2703 if (led_idx >= IXGBE_X557_MAX_LED_INDEX) 2704 return IXGBE_ERR_PARAM; 2705 2706 /* To turn on the LED, set mode to ON. */ 2707 hw->phy.ops.read_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx, 2708 MDIO_MMD_VEND1, &phy_data); 2709 phy_data |= IXGBE_X557_LED_MANUAL_SET_MASK; 2710 hw->phy.ops.write_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx, 2711 MDIO_MMD_VEND1, phy_data); 2712 2713 return 0; 2714 } 2715 2716 /** 2717 * ixgbe_led_off_t_x550em - Turns off the software controllable LEDs. 2718 * @hw: pointer to hardware structure 2719 * @led_idx: led number to turn off 2720 **/ 2721 static s32 ixgbe_led_off_t_x550em(struct ixgbe_hw *hw, u32 led_idx) 2722 { 2723 u16 phy_data; 2724 2725 if (led_idx >= IXGBE_X557_MAX_LED_INDEX) 2726 return IXGBE_ERR_PARAM; 2727 2728 /* To turn on the LED, set mode to ON. */ 2729 hw->phy.ops.read_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx, 2730 MDIO_MMD_VEND1, &phy_data); 2731 phy_data &= ~IXGBE_X557_LED_MANUAL_SET_MASK; 2732 hw->phy.ops.write_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx, 2733 MDIO_MMD_VEND1, phy_data); 2734 2735 return 0; 2736 } 2737 2738 /** 2739 * ixgbe_set_fw_drv_ver_x550 - Sends driver version to firmware 2740 * @hw: pointer to the HW structure 2741 * @maj: driver version major number 2742 * @min: driver version minor number 2743 * @build: driver version build number 2744 * @sub: driver version sub build number 2745 * @len: length of driver_ver string 2746 * @driver_ver: driver string 2747 * 2748 * Sends driver version number to firmware through the manageability 2749 * block. On success return 0 2750 * else returns IXGBE_ERR_SWFW_SYNC when encountering an error acquiring 2751 * semaphore or IXGBE_ERR_HOST_INTERFACE_COMMAND when command fails. 2752 **/ 2753 static s32 ixgbe_set_fw_drv_ver_x550(struct ixgbe_hw *hw, u8 maj, u8 min, 2754 u8 build, u8 sub, u16 len, 2755 const char *driver_ver) 2756 { 2757 struct ixgbe_hic_drv_info2 fw_cmd; 2758 s32 ret_val; 2759 int i; 2760 2761 if (!len || !driver_ver || (len > sizeof(fw_cmd.driver_string))) 2762 return IXGBE_ERR_INVALID_ARGUMENT; 2763 2764 fw_cmd.hdr.cmd = FW_CEM_CMD_DRIVER_INFO; 2765 fw_cmd.hdr.buf_len = FW_CEM_CMD_DRIVER_INFO_LEN + len; 2766 fw_cmd.hdr.cmd_or_resp.cmd_resv = FW_CEM_CMD_RESERVED; 2767 fw_cmd.port_num = (u8)hw->bus.func; 2768 fw_cmd.ver_maj = maj; 2769 fw_cmd.ver_min = min; 2770 fw_cmd.ver_build = build; 2771 fw_cmd.ver_sub = sub; 2772 fw_cmd.hdr.checksum = 0; 2773 memcpy(fw_cmd.driver_string, driver_ver, len); 2774 fw_cmd.hdr.checksum = ixgbe_calculate_checksum((u8 *)&fw_cmd, 2775 (FW_CEM_HDR_LEN + fw_cmd.hdr.buf_len)); 2776 2777 for (i = 0; i <= FW_CEM_MAX_RETRIES; i++) { 2778 ret_val = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd, 2779 sizeof(fw_cmd), 2780 IXGBE_HI_COMMAND_TIMEOUT, 2781 true); 2782 if (ret_val) 2783 continue; 2784 2785 if (fw_cmd.hdr.cmd_or_resp.ret_status != 2786 FW_CEM_RESP_STATUS_SUCCESS) 2787 return IXGBE_ERR_HOST_INTERFACE_COMMAND; 2788 return 0; 2789 } 2790 2791 return ret_val; 2792 } 2793 2794 /** ixgbe_get_lcd_x550em - Determine lowest common denominator 2795 * @hw: pointer to hardware structure 2796 * @lcd_speed: pointer to lowest common link speed 2797 * 2798 * Determine lowest common link speed with link partner. 2799 **/ 2800 static s32 ixgbe_get_lcd_t_x550em(struct ixgbe_hw *hw, 2801 ixgbe_link_speed *lcd_speed) 2802 { 2803 u16 an_lp_status; 2804 s32 status; 2805 u16 word = hw->eeprom.ctrl_word_3; 2806 2807 *lcd_speed = IXGBE_LINK_SPEED_UNKNOWN; 2808 2809 status = hw->phy.ops.read_reg(hw, IXGBE_AUTO_NEG_LP_STATUS, 2810 MDIO_MMD_AN, 2811 &an_lp_status); 2812 if (status) 2813 return status; 2814 2815 /* If link partner advertised 1G, return 1G */ 2816 if (an_lp_status & IXGBE_AUTO_NEG_LP_1000BASE_CAP) { 2817 *lcd_speed = IXGBE_LINK_SPEED_1GB_FULL; 2818 return status; 2819 } 2820 2821 /* If 10G disabled for LPLU via NVM D10GMP, then return no valid LCD */ 2822 if ((hw->bus.lan_id && (word & NVM_INIT_CTRL_3_D10GMP_PORT1)) || 2823 (word & NVM_INIT_CTRL_3_D10GMP_PORT0)) 2824 return status; 2825 2826 /* Link partner not capable of lower speeds, return 10G */ 2827 *lcd_speed = IXGBE_LINK_SPEED_10GB_FULL; 2828 return status; 2829 } 2830 2831 /** 2832 * ixgbe_setup_fc_x550em - Set up flow control 2833 * @hw: pointer to hardware structure 2834 */ 2835 static s32 ixgbe_setup_fc_x550em(struct ixgbe_hw *hw) 2836 { 2837 bool pause, asm_dir; 2838 u32 reg_val; 2839 s32 rc = 0; 2840 2841 /* Validate the requested mode */ 2842 if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) { 2843 hw_err(hw, "ixgbe_fc_rx_pause not valid in strict IEEE mode\n"); 2844 return IXGBE_ERR_INVALID_LINK_SETTINGS; 2845 } 2846 2847 /* 10gig parts do not have a word in the EEPROM to determine the 2848 * default flow control setting, so we explicitly set it to full. 2849 */ 2850 if (hw->fc.requested_mode == ixgbe_fc_default) 2851 hw->fc.requested_mode = ixgbe_fc_full; 2852 2853 /* Determine PAUSE and ASM_DIR bits. */ 2854 switch (hw->fc.requested_mode) { 2855 case ixgbe_fc_none: 2856 pause = false; 2857 asm_dir = false; 2858 break; 2859 case ixgbe_fc_tx_pause: 2860 pause = false; 2861 asm_dir = true; 2862 break; 2863 case ixgbe_fc_rx_pause: 2864 /* Rx Flow control is enabled and Tx Flow control is 2865 * disabled by software override. Since there really 2866 * isn't a way to advertise that we are capable of RX 2867 * Pause ONLY, we will advertise that we support both 2868 * symmetric and asymmetric Rx PAUSE, as such we fall 2869 * through to the fc_full statement. Later, we will 2870 * disable the adapter's ability to send PAUSE frames. 2871 */ 2872 /* Fallthrough */ 2873 case ixgbe_fc_full: 2874 pause = true; 2875 asm_dir = true; 2876 break; 2877 default: 2878 hw_err(hw, "Flow control param set incorrectly\n"); 2879 return IXGBE_ERR_CONFIG; 2880 } 2881 2882 switch (hw->device_id) { 2883 case IXGBE_DEV_ID_X550EM_X_KR: 2884 case IXGBE_DEV_ID_X550EM_A_KR: 2885 case IXGBE_DEV_ID_X550EM_A_KR_L: 2886 rc = hw->mac.ops.read_iosf_sb_reg(hw, 2887 IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id), 2888 IXGBE_SB_IOSF_TARGET_KR_PHY, 2889 ®_val); 2890 if (rc) 2891 return rc; 2892 2893 reg_val &= ~(IXGBE_KRM_AN_CNTL_1_SYM_PAUSE | 2894 IXGBE_KRM_AN_CNTL_1_ASM_PAUSE); 2895 if (pause) 2896 reg_val |= IXGBE_KRM_AN_CNTL_1_SYM_PAUSE; 2897 if (asm_dir) 2898 reg_val |= IXGBE_KRM_AN_CNTL_1_ASM_PAUSE; 2899 rc = hw->mac.ops.write_iosf_sb_reg(hw, 2900 IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id), 2901 IXGBE_SB_IOSF_TARGET_KR_PHY, 2902 reg_val); 2903 2904 /* This device does not fully support AN. */ 2905 hw->fc.disable_fc_autoneg = true; 2906 break; 2907 case IXGBE_DEV_ID_X550EM_X_XFI: 2908 hw->fc.disable_fc_autoneg = true; 2909 break; 2910 default: 2911 break; 2912 } 2913 return rc; 2914 } 2915 2916 /** 2917 * ixgbe_fc_autoneg_backplane_x550em_a - Enable flow control IEEE clause 37 2918 * @hw: pointer to hardware structure 2919 **/ 2920 static void ixgbe_fc_autoneg_backplane_x550em_a(struct ixgbe_hw *hw) 2921 { 2922 u32 link_s1, lp_an_page_low, an_cntl_1; 2923 s32 status = IXGBE_ERR_FC_NOT_NEGOTIATED; 2924 ixgbe_link_speed speed; 2925 bool link_up; 2926 2927 /* AN should have completed when the cable was plugged in. 2928 * Look for reasons to bail out. Bail out if: 2929 * - FC autoneg is disabled, or if 2930 * - link is not up. 2931 */ 2932 if (hw->fc.disable_fc_autoneg) { 2933 hw_err(hw, "Flow control autoneg is disabled"); 2934 goto out; 2935 } 2936 2937 hw->mac.ops.check_link(hw, &speed, &link_up, false); 2938 if (!link_up) { 2939 hw_err(hw, "The link is down"); 2940 goto out; 2941 } 2942 2943 /* Check at auto-negotiation has completed */ 2944 status = hw->mac.ops.read_iosf_sb_reg(hw, 2945 IXGBE_KRM_LINK_S1(hw->bus.lan_id), 2946 IXGBE_SB_IOSF_TARGET_KR_PHY, &link_s1); 2947 2948 if (status || (link_s1 & IXGBE_KRM_LINK_S1_MAC_AN_COMPLETE) == 0) { 2949 hw_dbg(hw, "Auto-Negotiation did not complete\n"); 2950 status = IXGBE_ERR_FC_NOT_NEGOTIATED; 2951 goto out; 2952 } 2953 2954 /* Read the 10g AN autoc and LP ability registers and resolve 2955 * local flow control settings accordingly 2956 */ 2957 status = hw->mac.ops.read_iosf_sb_reg(hw, 2958 IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id), 2959 IXGBE_SB_IOSF_TARGET_KR_PHY, &an_cntl_1); 2960 2961 if (status) { 2962 hw_dbg(hw, "Auto-Negotiation did not complete\n"); 2963 goto out; 2964 } 2965 2966 status = hw->mac.ops.read_iosf_sb_reg(hw, 2967 IXGBE_KRM_LP_BASE_PAGE_HIGH(hw->bus.lan_id), 2968 IXGBE_SB_IOSF_TARGET_KR_PHY, &lp_an_page_low); 2969 2970 if (status) { 2971 hw_dbg(hw, "Auto-Negotiation did not complete\n"); 2972 goto out; 2973 } 2974 2975 status = ixgbe_negotiate_fc(hw, an_cntl_1, lp_an_page_low, 2976 IXGBE_KRM_AN_CNTL_1_SYM_PAUSE, 2977 IXGBE_KRM_AN_CNTL_1_ASM_PAUSE, 2978 IXGBE_KRM_LP_BASE_PAGE_HIGH_SYM_PAUSE, 2979 IXGBE_KRM_LP_BASE_PAGE_HIGH_ASM_PAUSE); 2980 2981 out: 2982 if (!status) { 2983 hw->fc.fc_was_autonegged = true; 2984 } else { 2985 hw->fc.fc_was_autonegged = false; 2986 hw->fc.current_mode = hw->fc.requested_mode; 2987 } 2988 } 2989 2990 /** 2991 * ixgbe_fc_autoneg_fiber_x550em_a - passthrough FC settings 2992 * @hw: pointer to hardware structure 2993 **/ 2994 static void ixgbe_fc_autoneg_fiber_x550em_a(struct ixgbe_hw *hw) 2995 { 2996 hw->fc.fc_was_autonegged = false; 2997 hw->fc.current_mode = hw->fc.requested_mode; 2998 } 2999 3000 /** ixgbe_enter_lplu_x550em - Transition to low power states 3001 * @hw: pointer to hardware structure 3002 * 3003 * Configures Low Power Link Up on transition to low power states 3004 * (from D0 to non-D0). Link is required to enter LPLU so avoid resetting 3005 * the X557 PHY immediately prior to entering LPLU. 3006 **/ 3007 static s32 ixgbe_enter_lplu_t_x550em(struct ixgbe_hw *hw) 3008 { 3009 u16 an_10g_cntl_reg, autoneg_reg, speed; 3010 s32 status; 3011 ixgbe_link_speed lcd_speed; 3012 u32 save_autoneg; 3013 bool link_up; 3014 3015 /* If blocked by MNG FW, then don't restart AN */ 3016 if (ixgbe_check_reset_blocked(hw)) 3017 return 0; 3018 3019 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up); 3020 if (status) 3021 return status; 3022 3023 status = hw->eeprom.ops.read(hw, NVM_INIT_CTRL_3, 3024 &hw->eeprom.ctrl_word_3); 3025 if (status) 3026 return status; 3027 3028 /* If link is down, LPLU disabled in NVM, WoL disabled, or 3029 * manageability disabled, then force link down by entering 3030 * low power mode. 3031 */ 3032 if (!link_up || !(hw->eeprom.ctrl_word_3 & NVM_INIT_CTRL_3_LPLU) || 3033 !(hw->wol_enabled || ixgbe_mng_present(hw))) 3034 return ixgbe_set_copper_phy_power(hw, false); 3035 3036 /* Determine LCD */ 3037 status = ixgbe_get_lcd_t_x550em(hw, &lcd_speed); 3038 if (status) 3039 return status; 3040 3041 /* If no valid LCD link speed, then force link down and exit. */ 3042 if (lcd_speed == IXGBE_LINK_SPEED_UNKNOWN) 3043 return ixgbe_set_copper_phy_power(hw, false); 3044 3045 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_STAT, 3046 MDIO_MMD_AN, 3047 &speed); 3048 if (status) 3049 return status; 3050 3051 /* If no link now, speed is invalid so take link down */ 3052 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up); 3053 if (status) 3054 return ixgbe_set_copper_phy_power(hw, false); 3055 3056 /* clear everything but the speed bits */ 3057 speed &= IXGBE_MDIO_AUTO_NEG_VEN_STAT_SPEED_MASK; 3058 3059 /* If current speed is already LCD, then exit. */ 3060 if (((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB) && 3061 (lcd_speed == IXGBE_LINK_SPEED_1GB_FULL)) || 3062 ((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB) && 3063 (lcd_speed == IXGBE_LINK_SPEED_10GB_FULL))) 3064 return status; 3065 3066 /* Clear AN completed indication */ 3067 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM, 3068 MDIO_MMD_AN, 3069 &autoneg_reg); 3070 if (status) 3071 return status; 3072 3073 status = hw->phy.ops.read_reg(hw, MDIO_AN_10GBT_CTRL, 3074 MDIO_MMD_AN, 3075 &an_10g_cntl_reg); 3076 if (status) 3077 return status; 3078 3079 status = hw->phy.ops.read_reg(hw, 3080 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG, 3081 MDIO_MMD_AN, 3082 &autoneg_reg); 3083 if (status) 3084 return status; 3085 3086 save_autoneg = hw->phy.autoneg_advertised; 3087 3088 /* Setup link at least common link speed */ 3089 status = hw->mac.ops.setup_link(hw, lcd_speed, false); 3090 3091 /* restore autoneg from before setting lplu speed */ 3092 hw->phy.autoneg_advertised = save_autoneg; 3093 3094 return status; 3095 } 3096 3097 /** 3098 * ixgbe_reset_phy_fw - Reset firmware-controlled PHYs 3099 * @hw: pointer to hardware structure 3100 */ 3101 static s32 ixgbe_reset_phy_fw(struct ixgbe_hw *hw) 3102 { 3103 u32 store[FW_PHY_ACT_DATA_COUNT] = { 0 }; 3104 s32 rc; 3105 3106 if (hw->phy.reset_disable || ixgbe_check_reset_blocked(hw)) 3107 return 0; 3108 3109 rc = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_PHY_SW_RESET, &store); 3110 if (rc) 3111 return rc; 3112 memset(store, 0, sizeof(store)); 3113 3114 rc = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_INIT_PHY, &store); 3115 if (rc) 3116 return rc; 3117 3118 return ixgbe_setup_fw_link(hw); 3119 } 3120 3121 /** 3122 * ixgbe_check_overtemp_fw - Check firmware-controlled PHYs for overtemp 3123 * @hw: pointer to hardware structure 3124 */ 3125 static s32 ixgbe_check_overtemp_fw(struct ixgbe_hw *hw) 3126 { 3127 u32 store[FW_PHY_ACT_DATA_COUNT] = { 0 }; 3128 s32 rc; 3129 3130 rc = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_GET_LINK_INFO, &store); 3131 if (rc) 3132 return rc; 3133 3134 if (store[0] & FW_PHY_ACT_GET_LINK_INFO_TEMP) { 3135 ixgbe_shutdown_fw_phy(hw); 3136 return IXGBE_ERR_OVERTEMP; 3137 } 3138 return 0; 3139 } 3140 3141 /** 3142 * ixgbe_read_mng_if_sel_x550em - Read NW_MNG_IF_SEL register 3143 * @hw: pointer to hardware structure 3144 * 3145 * Read NW_MNG_IF_SEL register and save field values. 3146 */ 3147 static void ixgbe_read_mng_if_sel_x550em(struct ixgbe_hw *hw) 3148 { 3149 /* Save NW management interface connected on board. This is used 3150 * to determine internal PHY mode. 3151 */ 3152 hw->phy.nw_mng_if_sel = IXGBE_READ_REG(hw, IXGBE_NW_MNG_IF_SEL); 3153 3154 /* If X552 (X550EM_a) and MDIO is connected to external PHY, then set 3155 * PHY address. This register field was has only been used for X552. 3156 */ 3157 if (hw->mac.type == ixgbe_mac_x550em_a && 3158 hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_MDIO_ACT) { 3159 hw->phy.mdio.prtad = (hw->phy.nw_mng_if_sel & 3160 IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD) >> 3161 IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD_SHIFT; 3162 } 3163 } 3164 3165 /** ixgbe_init_phy_ops_X550em - PHY/SFP specific init 3166 * @hw: pointer to hardware structure 3167 * 3168 * Initialize any function pointers that were not able to be 3169 * set during init_shared_code because the PHY/SFP type was 3170 * not known. Perform the SFP init if necessary. 3171 **/ 3172 static s32 ixgbe_init_phy_ops_X550em(struct ixgbe_hw *hw) 3173 { 3174 struct ixgbe_phy_info *phy = &hw->phy; 3175 s32 ret_val; 3176 3177 hw->mac.ops.set_lan_id(hw); 3178 3179 ixgbe_read_mng_if_sel_x550em(hw); 3180 3181 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) { 3182 phy->phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM; 3183 ixgbe_setup_mux_ctl(hw); 3184 } 3185 3186 /* Identify the PHY or SFP module */ 3187 ret_val = phy->ops.identify(hw); 3188 if (ret_val == IXGBE_ERR_SFP_NOT_SUPPORTED || 3189 ret_val == IXGBE_ERR_PHY_ADDR_INVALID) 3190 return ret_val; 3191 3192 /* Setup function pointers based on detected hardware */ 3193 ixgbe_init_mac_link_ops_X550em(hw); 3194 if (phy->sfp_type != ixgbe_sfp_type_unknown) 3195 phy->ops.reset = NULL; 3196 3197 /* Set functions pointers based on phy type */ 3198 switch (hw->phy.type) { 3199 case ixgbe_phy_x550em_kx4: 3200 phy->ops.setup_link = NULL; 3201 phy->ops.read_reg = ixgbe_read_phy_reg_x550em; 3202 phy->ops.write_reg = ixgbe_write_phy_reg_x550em; 3203 break; 3204 case ixgbe_phy_x550em_kr: 3205 phy->ops.setup_link = ixgbe_setup_kr_x550em; 3206 phy->ops.read_reg = ixgbe_read_phy_reg_x550em; 3207 phy->ops.write_reg = ixgbe_write_phy_reg_x550em; 3208 break; 3209 case ixgbe_phy_x550em_xfi: 3210 /* link is managed by HW */ 3211 phy->ops.setup_link = NULL; 3212 phy->ops.read_reg = ixgbe_read_phy_reg_x550em; 3213 phy->ops.write_reg = ixgbe_write_phy_reg_x550em; 3214 break; 3215 case ixgbe_phy_x550em_ext_t: 3216 /* Save NW management interface connected on board. This is used 3217 * to determine internal PHY mode 3218 */ 3219 phy->nw_mng_if_sel = IXGBE_READ_REG(hw, IXGBE_NW_MNG_IF_SEL); 3220 3221 /* If internal link mode is XFI, then setup iXFI internal link, 3222 * else setup KR now. 3223 */ 3224 phy->ops.setup_internal_link = 3225 ixgbe_setup_internal_phy_t_x550em; 3226 3227 /* setup SW LPLU only for first revision */ 3228 if (hw->mac.type == ixgbe_mac_X550EM_x && 3229 !(IXGBE_READ_REG(hw, IXGBE_FUSES0_GROUP(0)) & 3230 IXGBE_FUSES0_REV_MASK)) 3231 phy->ops.enter_lplu = ixgbe_enter_lplu_t_x550em; 3232 3233 phy->ops.handle_lasi = ixgbe_handle_lasi_ext_t_x550em; 3234 phy->ops.reset = ixgbe_reset_phy_t_X550em; 3235 break; 3236 case ixgbe_phy_sgmii: 3237 phy->ops.setup_link = NULL; 3238 break; 3239 case ixgbe_phy_fw: 3240 phy->ops.setup_link = ixgbe_setup_fw_link; 3241 phy->ops.reset = ixgbe_reset_phy_fw; 3242 break; 3243 case ixgbe_phy_ext_1g_t: 3244 phy->ops.setup_link = NULL; 3245 phy->ops.read_reg = NULL; 3246 phy->ops.write_reg = NULL; 3247 phy->ops.reset = NULL; 3248 break; 3249 default: 3250 break; 3251 } 3252 3253 return ret_val; 3254 } 3255 3256 /** ixgbe_get_media_type_X550em - Get media type 3257 * @hw: pointer to hardware structure 3258 * 3259 * Returns the media type (fiber, copper, backplane) 3260 * 3261 */ 3262 static enum ixgbe_media_type ixgbe_get_media_type_X550em(struct ixgbe_hw *hw) 3263 { 3264 enum ixgbe_media_type media_type; 3265 3266 /* Detect if there is a copper PHY attached. */ 3267 switch (hw->device_id) { 3268 case IXGBE_DEV_ID_X550EM_A_SGMII: 3269 case IXGBE_DEV_ID_X550EM_A_SGMII_L: 3270 hw->phy.type = ixgbe_phy_sgmii; 3271 /* Fallthrough */ 3272 case IXGBE_DEV_ID_X550EM_X_KR: 3273 case IXGBE_DEV_ID_X550EM_X_KX4: 3274 case IXGBE_DEV_ID_X550EM_X_XFI: 3275 case IXGBE_DEV_ID_X550EM_A_KR: 3276 case IXGBE_DEV_ID_X550EM_A_KR_L: 3277 media_type = ixgbe_media_type_backplane; 3278 break; 3279 case IXGBE_DEV_ID_X550EM_X_SFP: 3280 case IXGBE_DEV_ID_X550EM_A_SFP: 3281 case IXGBE_DEV_ID_X550EM_A_SFP_N: 3282 media_type = ixgbe_media_type_fiber; 3283 break; 3284 case IXGBE_DEV_ID_X550EM_X_1G_T: 3285 case IXGBE_DEV_ID_X550EM_X_10G_T: 3286 case IXGBE_DEV_ID_X550EM_A_10G_T: 3287 case IXGBE_DEV_ID_X550EM_A_1G_T: 3288 case IXGBE_DEV_ID_X550EM_A_1G_T_L: 3289 media_type = ixgbe_media_type_copper; 3290 break; 3291 default: 3292 media_type = ixgbe_media_type_unknown; 3293 break; 3294 } 3295 return media_type; 3296 } 3297 3298 /** ixgbe_init_ext_t_x550em - Start (unstall) the external Base T PHY. 3299 ** @hw: pointer to hardware structure 3300 **/ 3301 static s32 ixgbe_init_ext_t_x550em(struct ixgbe_hw *hw) 3302 { 3303 s32 status; 3304 u16 reg; 3305 3306 status = hw->phy.ops.read_reg(hw, 3307 IXGBE_MDIO_TX_VENDOR_ALARMS_3, 3308 MDIO_MMD_PMAPMD, 3309 ®); 3310 if (status) 3311 return status; 3312 3313 /* If PHY FW reset completed bit is set then this is the first 3314 * SW instance after a power on so the PHY FW must be un-stalled. 3315 */ 3316 if (reg & IXGBE_MDIO_TX_VENDOR_ALARMS_3_RST_MASK) { 3317 status = hw->phy.ops.read_reg(hw, 3318 IXGBE_MDIO_GLOBAL_RES_PR_10, 3319 MDIO_MMD_VEND1, 3320 ®); 3321 if (status) 3322 return status; 3323 3324 reg &= ~IXGBE_MDIO_POWER_UP_STALL; 3325 3326 status = hw->phy.ops.write_reg(hw, 3327 IXGBE_MDIO_GLOBAL_RES_PR_10, 3328 MDIO_MMD_VEND1, 3329 reg); 3330 if (status) 3331 return status; 3332 } 3333 3334 return status; 3335 } 3336 3337 /** 3338 * ixgbe_set_mdio_speed - Set MDIO clock speed 3339 * @hw: pointer to hardware structure 3340 */ 3341 static void ixgbe_set_mdio_speed(struct ixgbe_hw *hw) 3342 { 3343 u32 hlreg0; 3344 3345 switch (hw->device_id) { 3346 case IXGBE_DEV_ID_X550EM_X_10G_T: 3347 case IXGBE_DEV_ID_X550EM_A_SGMII: 3348 case IXGBE_DEV_ID_X550EM_A_SGMII_L: 3349 case IXGBE_DEV_ID_X550EM_A_10G_T: 3350 case IXGBE_DEV_ID_X550EM_A_SFP: 3351 /* Config MDIO clock speed before the first MDIO PHY access */ 3352 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0); 3353 hlreg0 &= ~IXGBE_HLREG0_MDCSPD; 3354 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0); 3355 break; 3356 case IXGBE_DEV_ID_X550EM_A_1G_T: 3357 case IXGBE_DEV_ID_X550EM_A_1G_T_L: 3358 /* Select fast MDIO clock speed for these devices */ 3359 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0); 3360 hlreg0 |= IXGBE_HLREG0_MDCSPD; 3361 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0); 3362 break; 3363 default: 3364 break; 3365 } 3366 } 3367 3368 /** ixgbe_reset_hw_X550em - Perform hardware reset 3369 ** @hw: pointer to hardware structure 3370 ** 3371 ** Resets the hardware by resetting the transmit and receive units, masks 3372 ** and clears all interrupts, perform a PHY reset, and perform a link (MAC) 3373 ** reset. 3374 **/ 3375 static s32 ixgbe_reset_hw_X550em(struct ixgbe_hw *hw) 3376 { 3377 ixgbe_link_speed link_speed; 3378 s32 status; 3379 u32 ctrl = 0; 3380 u32 i; 3381 bool link_up = false; 3382 u32 swfw_mask = hw->phy.phy_semaphore_mask; 3383 3384 /* Call adapter stop to disable Tx/Rx and clear interrupts */ 3385 status = hw->mac.ops.stop_adapter(hw); 3386 if (status) 3387 return status; 3388 3389 /* flush pending Tx transactions */ 3390 ixgbe_clear_tx_pending(hw); 3391 3392 /* PHY ops must be identified and initialized prior to reset */ 3393 status = hw->phy.ops.init(hw); 3394 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED || 3395 status == IXGBE_ERR_PHY_ADDR_INVALID) 3396 return status; 3397 3398 /* start the external PHY */ 3399 if (hw->phy.type == ixgbe_phy_x550em_ext_t) { 3400 status = ixgbe_init_ext_t_x550em(hw); 3401 if (status) 3402 return status; 3403 } 3404 3405 /* Setup SFP module if there is one present. */ 3406 if (hw->phy.sfp_setup_needed) { 3407 status = hw->mac.ops.setup_sfp(hw); 3408 hw->phy.sfp_setup_needed = false; 3409 } 3410 3411 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED) 3412 return status; 3413 3414 /* Reset PHY */ 3415 if (!hw->phy.reset_disable && hw->phy.ops.reset) 3416 hw->phy.ops.reset(hw); 3417 3418 mac_reset_top: 3419 /* Issue global reset to the MAC. Needs to be SW reset if link is up. 3420 * If link reset is used when link is up, it might reset the PHY when 3421 * mng is using it. If link is down or the flag to force full link 3422 * reset is set, then perform link reset. 3423 */ 3424 ctrl = IXGBE_CTRL_LNK_RST; 3425 3426 if (!hw->force_full_reset) { 3427 hw->mac.ops.check_link(hw, &link_speed, &link_up, false); 3428 if (link_up) 3429 ctrl = IXGBE_CTRL_RST; 3430 } 3431 3432 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask); 3433 if (status) { 3434 hw_dbg(hw, "semaphore failed with %d", status); 3435 return IXGBE_ERR_SWFW_SYNC; 3436 } 3437 3438 ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL); 3439 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl); 3440 IXGBE_WRITE_FLUSH(hw); 3441 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 3442 usleep_range(1000, 1200); 3443 3444 /* Poll for reset bit to self-clear meaning reset is complete */ 3445 for (i = 0; i < 10; i++) { 3446 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL); 3447 if (!(ctrl & IXGBE_CTRL_RST_MASK)) 3448 break; 3449 udelay(1); 3450 } 3451 3452 if (ctrl & IXGBE_CTRL_RST_MASK) { 3453 status = IXGBE_ERR_RESET_FAILED; 3454 hw_dbg(hw, "Reset polling failed to complete.\n"); 3455 } 3456 3457 msleep(50); 3458 3459 /* Double resets are required for recovery from certain error 3460 * clear the multicast table. Also reset num_rar_entries to 128, 3461 * since we modify this value when programming the SAN MAC address. 3462 */ 3463 if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) { 3464 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED; 3465 goto mac_reset_top; 3466 } 3467 3468 /* Store the permanent mac address */ 3469 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr); 3470 3471 /* Store MAC address from RAR0, clear receive address registers, and 3472 * clear the multicast table. Also reset num_rar_entries to 128, 3473 * since we modify this value when programming the SAN MAC address. 3474 */ 3475 hw->mac.num_rar_entries = 128; 3476 hw->mac.ops.init_rx_addrs(hw); 3477 3478 ixgbe_set_mdio_speed(hw); 3479 3480 if (hw->device_id == IXGBE_DEV_ID_X550EM_X_SFP) 3481 ixgbe_setup_mux_ctl(hw); 3482 3483 return status; 3484 } 3485 3486 /** ixgbe_set_ethertype_anti_spoofing_X550 - Enable/Disable Ethertype 3487 * anti-spoofing 3488 * @hw: pointer to hardware structure 3489 * @enable: enable or disable switch for Ethertype anti-spoofing 3490 * @vf: Virtual Function pool - VF Pool to set for Ethertype anti-spoofing 3491 **/ 3492 static void ixgbe_set_ethertype_anti_spoofing_X550(struct ixgbe_hw *hw, 3493 bool enable, int vf) 3494 { 3495 int vf_target_reg = vf >> 3; 3496 int vf_target_shift = vf % 8 + IXGBE_SPOOF_ETHERTYPEAS_SHIFT; 3497 u32 pfvfspoof; 3498 3499 pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg)); 3500 if (enable) 3501 pfvfspoof |= BIT(vf_target_shift); 3502 else 3503 pfvfspoof &= ~BIT(vf_target_shift); 3504 3505 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof); 3506 } 3507 3508 /** ixgbe_set_source_address_pruning_X550 - Enable/Disbale src address pruning 3509 * @hw: pointer to hardware structure 3510 * @enable: enable or disable source address pruning 3511 * @pool: Rx pool to set source address pruning for 3512 **/ 3513 static void ixgbe_set_source_address_pruning_X550(struct ixgbe_hw *hw, 3514 bool enable, 3515 unsigned int pool) 3516 { 3517 u64 pfflp; 3518 3519 /* max rx pool is 63 */ 3520 if (pool > 63) 3521 return; 3522 3523 pfflp = (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPL); 3524 pfflp |= (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPH) << 32; 3525 3526 if (enable) 3527 pfflp |= (1ULL << pool); 3528 else 3529 pfflp &= ~(1ULL << pool); 3530 3531 IXGBE_WRITE_REG(hw, IXGBE_PFFLPL, (u32)pfflp); 3532 IXGBE_WRITE_REG(hw, IXGBE_PFFLPH, (u32)(pfflp >> 32)); 3533 } 3534 3535 /** 3536 * ixgbe_setup_fc_backplane_x550em_a - Set up flow control 3537 * @hw: pointer to hardware structure 3538 * 3539 * Called at init time to set up flow control. 3540 **/ 3541 static s32 ixgbe_setup_fc_backplane_x550em_a(struct ixgbe_hw *hw) 3542 { 3543 s32 status = 0; 3544 u32 an_cntl = 0; 3545 3546 /* Validate the requested mode */ 3547 if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) { 3548 hw_err(hw, "ixgbe_fc_rx_pause not valid in strict IEEE mode\n"); 3549 return IXGBE_ERR_INVALID_LINK_SETTINGS; 3550 } 3551 3552 if (hw->fc.requested_mode == ixgbe_fc_default) 3553 hw->fc.requested_mode = ixgbe_fc_full; 3554 3555 /* Set up the 1G and 10G flow control advertisement registers so the 3556 * HW will be able to do FC autoneg once the cable is plugged in. If 3557 * we link at 10G, the 1G advertisement is harmless and vice versa. 3558 */ 3559 status = hw->mac.ops.read_iosf_sb_reg(hw, 3560 IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id), 3561 IXGBE_SB_IOSF_TARGET_KR_PHY, &an_cntl); 3562 3563 if (status) { 3564 hw_dbg(hw, "Auto-Negotiation did not complete\n"); 3565 return status; 3566 } 3567 3568 /* The possible values of fc.requested_mode are: 3569 * 0: Flow control is completely disabled 3570 * 1: Rx flow control is enabled (we can receive pause frames, 3571 * but not send pause frames). 3572 * 2: Tx flow control is enabled (we can send pause frames but 3573 * we do not support receiving pause frames). 3574 * 3: Both Rx and Tx flow control (symmetric) are enabled. 3575 * other: Invalid. 3576 */ 3577 switch (hw->fc.requested_mode) { 3578 case ixgbe_fc_none: 3579 /* Flow control completely disabled by software override. */ 3580 an_cntl &= ~(IXGBE_KRM_AN_CNTL_1_SYM_PAUSE | 3581 IXGBE_KRM_AN_CNTL_1_ASM_PAUSE); 3582 break; 3583 case ixgbe_fc_tx_pause: 3584 /* Tx Flow control is enabled, and Rx Flow control is 3585 * disabled by software override. 3586 */ 3587 an_cntl |= IXGBE_KRM_AN_CNTL_1_ASM_PAUSE; 3588 an_cntl &= ~IXGBE_KRM_AN_CNTL_1_SYM_PAUSE; 3589 break; 3590 case ixgbe_fc_rx_pause: 3591 /* Rx Flow control is enabled and Tx Flow control is 3592 * disabled by software override. Since there really 3593 * isn't a way to advertise that we are capable of RX 3594 * Pause ONLY, we will advertise that we support both 3595 * symmetric and asymmetric Rx PAUSE, as such we fall 3596 * through to the fc_full statement. Later, we will 3597 * disable the adapter's ability to send PAUSE frames. 3598 */ 3599 case ixgbe_fc_full: 3600 /* Flow control (both Rx and Tx) is enabled by SW override. */ 3601 an_cntl |= IXGBE_KRM_AN_CNTL_1_SYM_PAUSE | 3602 IXGBE_KRM_AN_CNTL_1_ASM_PAUSE; 3603 break; 3604 default: 3605 hw_err(hw, "Flow control param set incorrectly\n"); 3606 return IXGBE_ERR_CONFIG; 3607 } 3608 3609 status = hw->mac.ops.write_iosf_sb_reg(hw, 3610 IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id), 3611 IXGBE_SB_IOSF_TARGET_KR_PHY, an_cntl); 3612 3613 /* Restart auto-negotiation. */ 3614 status = ixgbe_restart_an_internal_phy_x550em(hw); 3615 3616 return status; 3617 } 3618 3619 /** 3620 * ixgbe_set_mux - Set mux for port 1 access with CS4227 3621 * @hw: pointer to hardware structure 3622 * @state: set mux if 1, clear if 0 3623 */ 3624 static void ixgbe_set_mux(struct ixgbe_hw *hw, u8 state) 3625 { 3626 u32 esdp; 3627 3628 if (!hw->bus.lan_id) 3629 return; 3630 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); 3631 if (state) 3632 esdp |= IXGBE_ESDP_SDP1; 3633 else 3634 esdp &= ~IXGBE_ESDP_SDP1; 3635 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp); 3636 IXGBE_WRITE_FLUSH(hw); 3637 } 3638 3639 /** 3640 * ixgbe_acquire_swfw_sync_X550em - Acquire SWFW semaphore 3641 * @hw: pointer to hardware structure 3642 * @mask: Mask to specify which semaphore to acquire 3643 * 3644 * Acquires the SWFW semaphore and sets the I2C MUX 3645 */ 3646 static s32 ixgbe_acquire_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask) 3647 { 3648 s32 status; 3649 3650 status = ixgbe_acquire_swfw_sync_X540(hw, mask); 3651 if (status) 3652 return status; 3653 3654 if (mask & IXGBE_GSSR_I2C_MASK) 3655 ixgbe_set_mux(hw, 1); 3656 3657 return 0; 3658 } 3659 3660 /** 3661 * ixgbe_release_swfw_sync_X550em - Release SWFW semaphore 3662 * @hw: pointer to hardware structure 3663 * @mask: Mask to specify which semaphore to release 3664 * 3665 * Releases the SWFW semaphore and sets the I2C MUX 3666 */ 3667 static void ixgbe_release_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask) 3668 { 3669 if (mask & IXGBE_GSSR_I2C_MASK) 3670 ixgbe_set_mux(hw, 0); 3671 3672 ixgbe_release_swfw_sync_X540(hw, mask); 3673 } 3674 3675 /** 3676 * ixgbe_acquire_swfw_sync_x550em_a - Acquire SWFW semaphore 3677 * @hw: pointer to hardware structure 3678 * @mask: Mask to specify which semaphore to acquire 3679 * 3680 * Acquires the SWFW semaphore and get the shared PHY token as needed 3681 */ 3682 static s32 ixgbe_acquire_swfw_sync_x550em_a(struct ixgbe_hw *hw, u32 mask) 3683 { 3684 u32 hmask = mask & ~IXGBE_GSSR_TOKEN_SM; 3685 int retries = FW_PHY_TOKEN_RETRIES; 3686 s32 status; 3687 3688 while (--retries) { 3689 status = 0; 3690 if (hmask) 3691 status = ixgbe_acquire_swfw_sync_X540(hw, hmask); 3692 if (status) 3693 return status; 3694 if (!(mask & IXGBE_GSSR_TOKEN_SM)) 3695 return 0; 3696 3697 status = ixgbe_get_phy_token(hw); 3698 if (!status) 3699 return 0; 3700 if (hmask) 3701 ixgbe_release_swfw_sync_X540(hw, hmask); 3702 if (status != IXGBE_ERR_TOKEN_RETRY) 3703 return status; 3704 msleep(FW_PHY_TOKEN_DELAY); 3705 } 3706 3707 return status; 3708 } 3709 3710 /** 3711 * ixgbe_release_swfw_sync_x550em_a - Release SWFW semaphore 3712 * @hw: pointer to hardware structure 3713 * @mask: Mask to specify which semaphore to release 3714 * 3715 * Release the SWFW semaphore and puts the shared PHY token as needed 3716 */ 3717 static void ixgbe_release_swfw_sync_x550em_a(struct ixgbe_hw *hw, u32 mask) 3718 { 3719 u32 hmask = mask & ~IXGBE_GSSR_TOKEN_SM; 3720 3721 if (mask & IXGBE_GSSR_TOKEN_SM) 3722 ixgbe_put_phy_token(hw); 3723 3724 if (hmask) 3725 ixgbe_release_swfw_sync_X540(hw, hmask); 3726 } 3727 3728 /** 3729 * ixgbe_read_phy_reg_x550a - Reads specified PHY register 3730 * @hw: pointer to hardware structure 3731 * @reg_addr: 32 bit address of PHY register to read 3732 * @device_type: 5 bit device type 3733 * @phy_data: Pointer to read data from PHY register 3734 * 3735 * Reads a value from a specified PHY register using the SWFW lock and PHY 3736 * Token. The PHY Token is needed since the MDIO is shared between to MAC 3737 * instances. 3738 */ 3739 static s32 ixgbe_read_phy_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr, 3740 u32 device_type, u16 *phy_data) 3741 { 3742 u32 mask = hw->phy.phy_semaphore_mask | IXGBE_GSSR_TOKEN_SM; 3743 s32 status; 3744 3745 if (hw->mac.ops.acquire_swfw_sync(hw, mask)) 3746 return IXGBE_ERR_SWFW_SYNC; 3747 3748 status = hw->phy.ops.read_reg_mdi(hw, reg_addr, device_type, phy_data); 3749 3750 hw->mac.ops.release_swfw_sync(hw, mask); 3751 3752 return status; 3753 } 3754 3755 /** 3756 * ixgbe_write_phy_reg_x550a - Writes specified PHY register 3757 * @hw: pointer to hardware structure 3758 * @reg_addr: 32 bit PHY register to write 3759 * @device_type: 5 bit device type 3760 * @phy_data: Data to write to the PHY register 3761 * 3762 * Writes a value to specified PHY register using the SWFW lock and PHY Token. 3763 * The PHY Token is needed since the MDIO is shared between to MAC instances. 3764 */ 3765 static s32 ixgbe_write_phy_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr, 3766 u32 device_type, u16 phy_data) 3767 { 3768 u32 mask = hw->phy.phy_semaphore_mask | IXGBE_GSSR_TOKEN_SM; 3769 s32 status; 3770 3771 if (hw->mac.ops.acquire_swfw_sync(hw, mask)) 3772 return IXGBE_ERR_SWFW_SYNC; 3773 3774 status = ixgbe_write_phy_reg_mdi(hw, reg_addr, device_type, phy_data); 3775 hw->mac.ops.release_swfw_sync(hw, mask); 3776 3777 return status; 3778 } 3779 3780 #define X550_COMMON_MAC \ 3781 .init_hw = &ixgbe_init_hw_generic, \ 3782 .start_hw = &ixgbe_start_hw_X540, \ 3783 .clear_hw_cntrs = &ixgbe_clear_hw_cntrs_generic, \ 3784 .enable_rx_dma = &ixgbe_enable_rx_dma_generic, \ 3785 .get_mac_addr = &ixgbe_get_mac_addr_generic, \ 3786 .get_device_caps = &ixgbe_get_device_caps_generic, \ 3787 .stop_adapter = &ixgbe_stop_adapter_generic, \ 3788 .set_lan_id = &ixgbe_set_lan_id_multi_port_pcie, \ 3789 .read_analog_reg8 = NULL, \ 3790 .write_analog_reg8 = NULL, \ 3791 .set_rxpba = &ixgbe_set_rxpba_generic, \ 3792 .check_link = &ixgbe_check_mac_link_generic, \ 3793 .blink_led_start = &ixgbe_blink_led_start_X540, \ 3794 .blink_led_stop = &ixgbe_blink_led_stop_X540, \ 3795 .set_rar = &ixgbe_set_rar_generic, \ 3796 .clear_rar = &ixgbe_clear_rar_generic, \ 3797 .set_vmdq = &ixgbe_set_vmdq_generic, \ 3798 .set_vmdq_san_mac = &ixgbe_set_vmdq_san_mac_generic, \ 3799 .clear_vmdq = &ixgbe_clear_vmdq_generic, \ 3800 .init_rx_addrs = &ixgbe_init_rx_addrs_generic, \ 3801 .update_mc_addr_list = &ixgbe_update_mc_addr_list_generic, \ 3802 .enable_mc = &ixgbe_enable_mc_generic, \ 3803 .disable_mc = &ixgbe_disable_mc_generic, \ 3804 .clear_vfta = &ixgbe_clear_vfta_generic, \ 3805 .set_vfta = &ixgbe_set_vfta_generic, \ 3806 .fc_enable = &ixgbe_fc_enable_generic, \ 3807 .set_fw_drv_ver = &ixgbe_set_fw_drv_ver_x550, \ 3808 .init_uta_tables = &ixgbe_init_uta_tables_generic, \ 3809 .set_mac_anti_spoofing = &ixgbe_set_mac_anti_spoofing, \ 3810 .set_vlan_anti_spoofing = &ixgbe_set_vlan_anti_spoofing, \ 3811 .set_source_address_pruning = \ 3812 &ixgbe_set_source_address_pruning_X550, \ 3813 .set_ethertype_anti_spoofing = \ 3814 &ixgbe_set_ethertype_anti_spoofing_X550, \ 3815 .disable_rx_buff = &ixgbe_disable_rx_buff_generic, \ 3816 .enable_rx_buff = &ixgbe_enable_rx_buff_generic, \ 3817 .get_thermal_sensor_data = NULL, \ 3818 .init_thermal_sensor_thresh = NULL, \ 3819 .enable_rx = &ixgbe_enable_rx_generic, \ 3820 .disable_rx = &ixgbe_disable_rx_x550, \ 3821 3822 static const struct ixgbe_mac_operations mac_ops_X550 = { 3823 X550_COMMON_MAC 3824 .led_on = ixgbe_led_on_generic, 3825 .led_off = ixgbe_led_off_generic, 3826 .init_led_link_act = ixgbe_init_led_link_act_generic, 3827 .reset_hw = &ixgbe_reset_hw_X540, 3828 .get_media_type = &ixgbe_get_media_type_X540, 3829 .get_san_mac_addr = &ixgbe_get_san_mac_addr_generic, 3830 .get_wwn_prefix = &ixgbe_get_wwn_prefix_generic, 3831 .setup_link = &ixgbe_setup_mac_link_X540, 3832 .get_link_capabilities = &ixgbe_get_copper_link_capabilities_generic, 3833 .get_bus_info = &ixgbe_get_bus_info_generic, 3834 .setup_sfp = NULL, 3835 .acquire_swfw_sync = &ixgbe_acquire_swfw_sync_X540, 3836 .release_swfw_sync = &ixgbe_release_swfw_sync_X540, 3837 .init_swfw_sync = &ixgbe_init_swfw_sync_X540, 3838 .prot_autoc_read = prot_autoc_read_generic, 3839 .prot_autoc_write = prot_autoc_write_generic, 3840 .setup_fc = ixgbe_setup_fc_generic, 3841 .fc_autoneg = ixgbe_fc_autoneg, 3842 }; 3843 3844 static const struct ixgbe_mac_operations mac_ops_X550EM_x = { 3845 X550_COMMON_MAC 3846 .led_on = ixgbe_led_on_t_x550em, 3847 .led_off = ixgbe_led_off_t_x550em, 3848 .init_led_link_act = ixgbe_init_led_link_act_generic, 3849 .reset_hw = &ixgbe_reset_hw_X550em, 3850 .get_media_type = &ixgbe_get_media_type_X550em, 3851 .get_san_mac_addr = NULL, 3852 .get_wwn_prefix = NULL, 3853 .setup_link = &ixgbe_setup_mac_link_X540, 3854 .get_link_capabilities = &ixgbe_get_link_capabilities_X550em, 3855 .get_bus_info = &ixgbe_get_bus_info_X550em, 3856 .setup_sfp = ixgbe_setup_sfp_modules_X550em, 3857 .acquire_swfw_sync = &ixgbe_acquire_swfw_sync_X550em, 3858 .release_swfw_sync = &ixgbe_release_swfw_sync_X550em, 3859 .init_swfw_sync = &ixgbe_init_swfw_sync_X540, 3860 .setup_fc = NULL, /* defined later */ 3861 .fc_autoneg = ixgbe_fc_autoneg, 3862 .read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550, 3863 .write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550, 3864 }; 3865 3866 static const struct ixgbe_mac_operations mac_ops_X550EM_x_fw = { 3867 X550_COMMON_MAC 3868 .led_on = NULL, 3869 .led_off = NULL, 3870 .init_led_link_act = NULL, 3871 .reset_hw = &ixgbe_reset_hw_X550em, 3872 .get_media_type = &ixgbe_get_media_type_X550em, 3873 .get_san_mac_addr = NULL, 3874 .get_wwn_prefix = NULL, 3875 .setup_link = &ixgbe_setup_mac_link_X540, 3876 .get_link_capabilities = &ixgbe_get_link_capabilities_X550em, 3877 .get_bus_info = &ixgbe_get_bus_info_X550em, 3878 .setup_sfp = ixgbe_setup_sfp_modules_X550em, 3879 .acquire_swfw_sync = &ixgbe_acquire_swfw_sync_X550em, 3880 .release_swfw_sync = &ixgbe_release_swfw_sync_X550em, 3881 .init_swfw_sync = &ixgbe_init_swfw_sync_X540, 3882 .setup_fc = NULL, 3883 .fc_autoneg = ixgbe_fc_autoneg, 3884 .read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550, 3885 .write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550, 3886 }; 3887 3888 static const struct ixgbe_mac_operations mac_ops_x550em_a = { 3889 X550_COMMON_MAC 3890 .led_on = ixgbe_led_on_t_x550em, 3891 .led_off = ixgbe_led_off_t_x550em, 3892 .init_led_link_act = ixgbe_init_led_link_act_generic, 3893 .reset_hw = ixgbe_reset_hw_X550em, 3894 .get_media_type = ixgbe_get_media_type_X550em, 3895 .get_san_mac_addr = NULL, 3896 .get_wwn_prefix = NULL, 3897 .setup_link = &ixgbe_setup_mac_link_X540, 3898 .get_link_capabilities = ixgbe_get_link_capabilities_X550em, 3899 .get_bus_info = ixgbe_get_bus_info_X550em, 3900 .setup_sfp = ixgbe_setup_sfp_modules_X550em, 3901 .acquire_swfw_sync = ixgbe_acquire_swfw_sync_x550em_a, 3902 .release_swfw_sync = ixgbe_release_swfw_sync_x550em_a, 3903 .setup_fc = ixgbe_setup_fc_x550em, 3904 .fc_autoneg = ixgbe_fc_autoneg, 3905 .read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550a, 3906 .write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550a, 3907 }; 3908 3909 static const struct ixgbe_mac_operations mac_ops_x550em_a_fw = { 3910 X550_COMMON_MAC 3911 .led_on = ixgbe_led_on_generic, 3912 .led_off = ixgbe_led_off_generic, 3913 .init_led_link_act = ixgbe_init_led_link_act_generic, 3914 .reset_hw = ixgbe_reset_hw_X550em, 3915 .get_media_type = ixgbe_get_media_type_X550em, 3916 .get_san_mac_addr = NULL, 3917 .get_wwn_prefix = NULL, 3918 .setup_link = NULL, /* defined later */ 3919 .get_link_capabilities = ixgbe_get_link_capabilities_X550em, 3920 .get_bus_info = ixgbe_get_bus_info_X550em, 3921 .setup_sfp = ixgbe_setup_sfp_modules_X550em, 3922 .acquire_swfw_sync = ixgbe_acquire_swfw_sync_x550em_a, 3923 .release_swfw_sync = ixgbe_release_swfw_sync_x550em_a, 3924 .setup_fc = ixgbe_setup_fc_x550em, 3925 .fc_autoneg = ixgbe_fc_autoneg, 3926 .read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550a, 3927 .write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550a, 3928 }; 3929 3930 #define X550_COMMON_EEP \ 3931 .read = &ixgbe_read_ee_hostif_X550, \ 3932 .read_buffer = &ixgbe_read_ee_hostif_buffer_X550, \ 3933 .write = &ixgbe_write_ee_hostif_X550, \ 3934 .write_buffer = &ixgbe_write_ee_hostif_buffer_X550, \ 3935 .validate_checksum = &ixgbe_validate_eeprom_checksum_X550, \ 3936 .update_checksum = &ixgbe_update_eeprom_checksum_X550, \ 3937 .calc_checksum = &ixgbe_calc_eeprom_checksum_X550, \ 3938 3939 static const struct ixgbe_eeprom_operations eeprom_ops_X550 = { 3940 X550_COMMON_EEP 3941 .init_params = &ixgbe_init_eeprom_params_X550, 3942 }; 3943 3944 static const struct ixgbe_eeprom_operations eeprom_ops_X550EM_x = { 3945 X550_COMMON_EEP 3946 .init_params = &ixgbe_init_eeprom_params_X540, 3947 }; 3948 3949 #define X550_COMMON_PHY \ 3950 .identify_sfp = &ixgbe_identify_module_generic, \ 3951 .reset = NULL, \ 3952 .setup_link_speed = &ixgbe_setup_phy_link_speed_generic, \ 3953 .read_i2c_byte = &ixgbe_read_i2c_byte_generic, \ 3954 .write_i2c_byte = &ixgbe_write_i2c_byte_generic, \ 3955 .read_i2c_sff8472 = &ixgbe_read_i2c_sff8472_generic, \ 3956 .read_i2c_eeprom = &ixgbe_read_i2c_eeprom_generic, \ 3957 .write_i2c_eeprom = &ixgbe_write_i2c_eeprom_generic, \ 3958 .setup_link = &ixgbe_setup_phy_link_generic, \ 3959 .set_phy_power = NULL, 3960 3961 static const struct ixgbe_phy_operations phy_ops_X550 = { 3962 X550_COMMON_PHY 3963 .check_overtemp = &ixgbe_tn_check_overtemp, 3964 .init = NULL, 3965 .identify = &ixgbe_identify_phy_generic, 3966 .read_reg = &ixgbe_read_phy_reg_generic, 3967 .write_reg = &ixgbe_write_phy_reg_generic, 3968 }; 3969 3970 static const struct ixgbe_phy_operations phy_ops_X550EM_x = { 3971 X550_COMMON_PHY 3972 .check_overtemp = &ixgbe_tn_check_overtemp, 3973 .init = &ixgbe_init_phy_ops_X550em, 3974 .identify = &ixgbe_identify_phy_x550em, 3975 .read_reg = &ixgbe_read_phy_reg_generic, 3976 .write_reg = &ixgbe_write_phy_reg_generic, 3977 }; 3978 3979 static const struct ixgbe_phy_operations phy_ops_x550em_x_fw = { 3980 X550_COMMON_PHY 3981 .check_overtemp = NULL, 3982 .init = ixgbe_init_phy_ops_X550em, 3983 .identify = ixgbe_identify_phy_x550em, 3984 .read_reg = NULL, 3985 .write_reg = NULL, 3986 .read_reg_mdi = NULL, 3987 .write_reg_mdi = NULL, 3988 }; 3989 3990 static const struct ixgbe_phy_operations phy_ops_x550em_a = { 3991 X550_COMMON_PHY 3992 .check_overtemp = &ixgbe_tn_check_overtemp, 3993 .init = &ixgbe_init_phy_ops_X550em, 3994 .identify = &ixgbe_identify_phy_x550em, 3995 .read_reg = &ixgbe_read_phy_reg_x550a, 3996 .write_reg = &ixgbe_write_phy_reg_x550a, 3997 .read_reg_mdi = &ixgbe_read_phy_reg_mdi, 3998 .write_reg_mdi = &ixgbe_write_phy_reg_mdi, 3999 }; 4000 4001 static const struct ixgbe_phy_operations phy_ops_x550em_a_fw = { 4002 X550_COMMON_PHY 4003 .check_overtemp = ixgbe_check_overtemp_fw, 4004 .init = ixgbe_init_phy_ops_X550em, 4005 .identify = ixgbe_identify_phy_fw, 4006 .read_reg = NULL, 4007 .write_reg = NULL, 4008 .read_reg_mdi = NULL, 4009 .write_reg_mdi = NULL, 4010 }; 4011 4012 static const struct ixgbe_link_operations link_ops_x550em_x = { 4013 .read_link = &ixgbe_read_i2c_combined_generic, 4014 .read_link_unlocked = &ixgbe_read_i2c_combined_generic_unlocked, 4015 .write_link = &ixgbe_write_i2c_combined_generic, 4016 .write_link_unlocked = &ixgbe_write_i2c_combined_generic_unlocked, 4017 }; 4018 4019 static const u32 ixgbe_mvals_X550[IXGBE_MVALS_IDX_LIMIT] = { 4020 IXGBE_MVALS_INIT(X550) 4021 }; 4022 4023 static const u32 ixgbe_mvals_X550EM_x[IXGBE_MVALS_IDX_LIMIT] = { 4024 IXGBE_MVALS_INIT(X550EM_x) 4025 }; 4026 4027 static const u32 ixgbe_mvals_x550em_a[IXGBE_MVALS_IDX_LIMIT] = { 4028 IXGBE_MVALS_INIT(X550EM_a) 4029 }; 4030 4031 const struct ixgbe_info ixgbe_X550_info = { 4032 .mac = ixgbe_mac_X550, 4033 .get_invariants = &ixgbe_get_invariants_X540, 4034 .mac_ops = &mac_ops_X550, 4035 .eeprom_ops = &eeprom_ops_X550, 4036 .phy_ops = &phy_ops_X550, 4037 .mbx_ops = &mbx_ops_generic, 4038 .mvals = ixgbe_mvals_X550, 4039 }; 4040 4041 const struct ixgbe_info ixgbe_X550EM_x_info = { 4042 .mac = ixgbe_mac_X550EM_x, 4043 .get_invariants = &ixgbe_get_invariants_X550_x, 4044 .mac_ops = &mac_ops_X550EM_x, 4045 .eeprom_ops = &eeprom_ops_X550EM_x, 4046 .phy_ops = &phy_ops_X550EM_x, 4047 .mbx_ops = &mbx_ops_generic, 4048 .mvals = ixgbe_mvals_X550EM_x, 4049 .link_ops = &link_ops_x550em_x, 4050 }; 4051 4052 const struct ixgbe_info ixgbe_x550em_x_fw_info = { 4053 .mac = ixgbe_mac_X550EM_x, 4054 .get_invariants = ixgbe_get_invariants_X550_x_fw, 4055 .mac_ops = &mac_ops_X550EM_x_fw, 4056 .eeprom_ops = &eeprom_ops_X550EM_x, 4057 .phy_ops = &phy_ops_x550em_x_fw, 4058 .mbx_ops = &mbx_ops_generic, 4059 .mvals = ixgbe_mvals_X550EM_x, 4060 }; 4061 4062 const struct ixgbe_info ixgbe_x550em_a_info = { 4063 .mac = ixgbe_mac_x550em_a, 4064 .get_invariants = &ixgbe_get_invariants_X550_a, 4065 .mac_ops = &mac_ops_x550em_a, 4066 .eeprom_ops = &eeprom_ops_X550EM_x, 4067 .phy_ops = &phy_ops_x550em_a, 4068 .mbx_ops = &mbx_ops_generic, 4069 .mvals = ixgbe_mvals_x550em_a, 4070 }; 4071 4072 const struct ixgbe_info ixgbe_x550em_a_fw_info = { 4073 .mac = ixgbe_mac_x550em_a, 4074 .get_invariants = ixgbe_get_invariants_X550_a_fw, 4075 .mac_ops = &mac_ops_x550em_a_fw, 4076 .eeprom_ops = &eeprom_ops_X550EM_x, 4077 .phy_ops = &phy_ops_x550em_a_fw, 4078 .mbx_ops = &mbx_ops_generic, 4079 .mvals = ixgbe_mvals_x550em_a, 4080 }; 4081