1 /******************************************************************************* 2 * 3 * Intel 10 Gigabit PCI Express Linux driver 4 * Copyright(c) 1999 - 2016 Intel Corporation. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * The full GNU General Public License is included in this distribution in 16 * the file called "COPYING". 17 * 18 * Contact Information: 19 * Linux NICS <linux.nics@intel.com> 20 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 21 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 22 * 23 ******************************************************************************/ 24 #include "ixgbe_x540.h" 25 #include "ixgbe_type.h" 26 #include "ixgbe_common.h" 27 #include "ixgbe_phy.h" 28 29 static s32 ixgbe_setup_kr_speed_x550em(struct ixgbe_hw *, ixgbe_link_speed); 30 static s32 ixgbe_setup_fc_x550em(struct ixgbe_hw *); 31 static void ixgbe_fc_autoneg_fiber_x550em_a(struct ixgbe_hw *); 32 static void ixgbe_fc_autoneg_backplane_x550em_a(struct ixgbe_hw *); 33 static s32 ixgbe_setup_fc_backplane_x550em_a(struct ixgbe_hw *); 34 35 static s32 ixgbe_get_invariants_X550_x(struct ixgbe_hw *hw) 36 { 37 struct ixgbe_mac_info *mac = &hw->mac; 38 struct ixgbe_phy_info *phy = &hw->phy; 39 struct ixgbe_link_info *link = &hw->link; 40 41 /* Start with X540 invariants, since so simular */ 42 ixgbe_get_invariants_X540(hw); 43 44 if (mac->ops.get_media_type(hw) != ixgbe_media_type_copper) 45 phy->ops.set_phy_power = NULL; 46 47 link->addr = IXGBE_CS4227; 48 49 return 0; 50 } 51 52 static s32 ixgbe_get_invariants_X550_x_fw(struct ixgbe_hw *hw) 53 { 54 struct ixgbe_phy_info *phy = &hw->phy; 55 56 /* Start with X540 invariants, since so similar */ 57 ixgbe_get_invariants_X540(hw); 58 59 phy->ops.set_phy_power = NULL; 60 61 return 0; 62 } 63 64 static s32 ixgbe_get_invariants_X550_a(struct ixgbe_hw *hw) 65 { 66 struct ixgbe_mac_info *mac = &hw->mac; 67 struct ixgbe_phy_info *phy = &hw->phy; 68 69 /* Start with X540 invariants, since so simular */ 70 ixgbe_get_invariants_X540(hw); 71 72 if (mac->ops.get_media_type(hw) != ixgbe_media_type_copper) 73 phy->ops.set_phy_power = NULL; 74 75 return 0; 76 } 77 78 static s32 ixgbe_get_invariants_X550_a_fw(struct ixgbe_hw *hw) 79 { 80 struct ixgbe_phy_info *phy = &hw->phy; 81 82 /* Start with X540 invariants, since so similar */ 83 ixgbe_get_invariants_X540(hw); 84 85 phy->ops.set_phy_power = NULL; 86 87 return 0; 88 } 89 90 /** ixgbe_setup_mux_ctl - Setup ESDP register for I2C mux control 91 * @hw: pointer to hardware structure 92 **/ 93 static void ixgbe_setup_mux_ctl(struct ixgbe_hw *hw) 94 { 95 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); 96 97 if (hw->bus.lan_id) { 98 esdp &= ~(IXGBE_ESDP_SDP1_NATIVE | IXGBE_ESDP_SDP1); 99 esdp |= IXGBE_ESDP_SDP1_DIR; 100 } 101 esdp &= ~(IXGBE_ESDP_SDP0_NATIVE | IXGBE_ESDP_SDP0_DIR); 102 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp); 103 IXGBE_WRITE_FLUSH(hw); 104 } 105 106 /** 107 * ixgbe_read_cs4227 - Read CS4227 register 108 * @hw: pointer to hardware structure 109 * @reg: register number to write 110 * @value: pointer to receive value read 111 * 112 * Returns status code 113 */ 114 static s32 ixgbe_read_cs4227(struct ixgbe_hw *hw, u16 reg, u16 *value) 115 { 116 return hw->link.ops.read_link_unlocked(hw, hw->link.addr, reg, value); 117 } 118 119 /** 120 * ixgbe_write_cs4227 - Write CS4227 register 121 * @hw: pointer to hardware structure 122 * @reg: register number to write 123 * @value: value to write to register 124 * 125 * Returns status code 126 */ 127 static s32 ixgbe_write_cs4227(struct ixgbe_hw *hw, u16 reg, u16 value) 128 { 129 return hw->link.ops.write_link_unlocked(hw, hw->link.addr, reg, value); 130 } 131 132 /** 133 * ixgbe_read_pe - Read register from port expander 134 * @hw: pointer to hardware structure 135 * @reg: register number to read 136 * @value: pointer to receive read value 137 * 138 * Returns status code 139 */ 140 static s32 ixgbe_read_pe(struct ixgbe_hw *hw, u8 reg, u8 *value) 141 { 142 s32 status; 143 144 status = ixgbe_read_i2c_byte_generic_unlocked(hw, reg, IXGBE_PE, value); 145 if (status) 146 hw_err(hw, "port expander access failed with %d\n", status); 147 return status; 148 } 149 150 /** 151 * ixgbe_write_pe - Write register to port expander 152 * @hw: pointer to hardware structure 153 * @reg: register number to write 154 * @value: value to write 155 * 156 * Returns status code 157 */ 158 static s32 ixgbe_write_pe(struct ixgbe_hw *hw, u8 reg, u8 value) 159 { 160 s32 status; 161 162 status = ixgbe_write_i2c_byte_generic_unlocked(hw, reg, IXGBE_PE, 163 value); 164 if (status) 165 hw_err(hw, "port expander access failed with %d\n", status); 166 return status; 167 } 168 169 /** 170 * ixgbe_reset_cs4227 - Reset CS4227 using port expander 171 * @hw: pointer to hardware structure 172 * 173 * This function assumes that the caller has acquired the proper semaphore. 174 * Returns error code 175 */ 176 static s32 ixgbe_reset_cs4227(struct ixgbe_hw *hw) 177 { 178 s32 status; 179 u32 retry; 180 u16 value; 181 u8 reg; 182 183 /* Trigger hard reset. */ 184 status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, ®); 185 if (status) 186 return status; 187 reg |= IXGBE_PE_BIT1; 188 status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg); 189 if (status) 190 return status; 191 192 status = ixgbe_read_pe(hw, IXGBE_PE_CONFIG, ®); 193 if (status) 194 return status; 195 reg &= ~IXGBE_PE_BIT1; 196 status = ixgbe_write_pe(hw, IXGBE_PE_CONFIG, reg); 197 if (status) 198 return status; 199 200 status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, ®); 201 if (status) 202 return status; 203 reg &= ~IXGBE_PE_BIT1; 204 status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg); 205 if (status) 206 return status; 207 208 usleep_range(IXGBE_CS4227_RESET_HOLD, IXGBE_CS4227_RESET_HOLD + 100); 209 210 status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, ®); 211 if (status) 212 return status; 213 reg |= IXGBE_PE_BIT1; 214 status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg); 215 if (status) 216 return status; 217 218 /* Wait for the reset to complete. */ 219 msleep(IXGBE_CS4227_RESET_DELAY); 220 for (retry = 0; retry < IXGBE_CS4227_RETRIES; retry++) { 221 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_EFUSE_STATUS, 222 &value); 223 if (!status && value == IXGBE_CS4227_EEPROM_LOAD_OK) 224 break; 225 msleep(IXGBE_CS4227_CHECK_DELAY); 226 } 227 if (retry == IXGBE_CS4227_RETRIES) { 228 hw_err(hw, "CS4227 reset did not complete\n"); 229 return IXGBE_ERR_PHY; 230 } 231 232 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_EEPROM_STATUS, &value); 233 if (status || !(value & IXGBE_CS4227_EEPROM_LOAD_OK)) { 234 hw_err(hw, "CS4227 EEPROM did not load successfully\n"); 235 return IXGBE_ERR_PHY; 236 } 237 238 return 0; 239 } 240 241 /** 242 * ixgbe_check_cs4227 - Check CS4227 and reset as needed 243 * @hw: pointer to hardware structure 244 */ 245 static void ixgbe_check_cs4227(struct ixgbe_hw *hw) 246 { 247 u32 swfw_mask = hw->phy.phy_semaphore_mask; 248 s32 status; 249 u16 value; 250 u8 retry; 251 252 for (retry = 0; retry < IXGBE_CS4227_RETRIES; retry++) { 253 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask); 254 if (status) { 255 hw_err(hw, "semaphore failed with %d\n", status); 256 msleep(IXGBE_CS4227_CHECK_DELAY); 257 continue; 258 } 259 260 /* Get status of reset flow. */ 261 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_SCRATCH, &value); 262 if (!status && value == IXGBE_CS4227_RESET_COMPLETE) 263 goto out; 264 265 if (status || value != IXGBE_CS4227_RESET_PENDING) 266 break; 267 268 /* Reset is pending. Wait and check again. */ 269 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 270 msleep(IXGBE_CS4227_CHECK_DELAY); 271 } 272 /* If still pending, assume other instance failed. */ 273 if (retry == IXGBE_CS4227_RETRIES) { 274 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask); 275 if (status) { 276 hw_err(hw, "semaphore failed with %d\n", status); 277 return; 278 } 279 } 280 281 /* Reset the CS4227. */ 282 status = ixgbe_reset_cs4227(hw); 283 if (status) { 284 hw_err(hw, "CS4227 reset failed: %d", status); 285 goto out; 286 } 287 288 /* Reset takes so long, temporarily release semaphore in case the 289 * other driver instance is waiting for the reset indication. 290 */ 291 ixgbe_write_cs4227(hw, IXGBE_CS4227_SCRATCH, 292 IXGBE_CS4227_RESET_PENDING); 293 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 294 usleep_range(10000, 12000); 295 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask); 296 if (status) { 297 hw_err(hw, "semaphore failed with %d", status); 298 return; 299 } 300 301 /* Record completion for next time. */ 302 status = ixgbe_write_cs4227(hw, IXGBE_CS4227_SCRATCH, 303 IXGBE_CS4227_RESET_COMPLETE); 304 305 out: 306 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 307 msleep(hw->eeprom.semaphore_delay); 308 } 309 310 /** ixgbe_identify_phy_x550em - Get PHY type based on device id 311 * @hw: pointer to hardware structure 312 * 313 * Returns error code 314 */ 315 static s32 ixgbe_identify_phy_x550em(struct ixgbe_hw *hw) 316 { 317 switch (hw->device_id) { 318 case IXGBE_DEV_ID_X550EM_A_SFP: 319 if (hw->bus.lan_id) 320 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY1_SM; 321 else 322 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY0_SM; 323 return ixgbe_identify_module_generic(hw); 324 case IXGBE_DEV_ID_X550EM_X_SFP: 325 /* set up for CS4227 usage */ 326 hw->phy.phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM; 327 ixgbe_setup_mux_ctl(hw); 328 ixgbe_check_cs4227(hw); 329 /* Fallthrough */ 330 case IXGBE_DEV_ID_X550EM_A_SFP_N: 331 return ixgbe_identify_module_generic(hw); 332 case IXGBE_DEV_ID_X550EM_X_KX4: 333 hw->phy.type = ixgbe_phy_x550em_kx4; 334 break; 335 case IXGBE_DEV_ID_X550EM_X_XFI: 336 hw->phy.type = ixgbe_phy_x550em_xfi; 337 break; 338 case IXGBE_DEV_ID_X550EM_X_KR: 339 case IXGBE_DEV_ID_X550EM_A_KR: 340 case IXGBE_DEV_ID_X550EM_A_KR_L: 341 hw->phy.type = ixgbe_phy_x550em_kr; 342 break; 343 case IXGBE_DEV_ID_X550EM_A_10G_T: 344 if (hw->bus.lan_id) 345 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY1_SM; 346 else 347 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY0_SM; 348 /* Fallthrough */ 349 case IXGBE_DEV_ID_X550EM_X_10G_T: 350 return ixgbe_identify_phy_generic(hw); 351 case IXGBE_DEV_ID_X550EM_X_1G_T: 352 hw->phy.type = ixgbe_phy_ext_1g_t; 353 break; 354 case IXGBE_DEV_ID_X550EM_A_1G_T: 355 case IXGBE_DEV_ID_X550EM_A_1G_T_L: 356 hw->phy.type = ixgbe_phy_fw; 357 hw->phy.ops.read_reg = NULL; 358 hw->phy.ops.write_reg = NULL; 359 if (hw->bus.lan_id) 360 hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY1_SM; 361 else 362 hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY0_SM; 363 break; 364 default: 365 break; 366 } 367 return 0; 368 } 369 370 static s32 ixgbe_read_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr, 371 u32 device_type, u16 *phy_data) 372 { 373 return IXGBE_NOT_IMPLEMENTED; 374 } 375 376 static s32 ixgbe_write_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr, 377 u32 device_type, u16 phy_data) 378 { 379 return IXGBE_NOT_IMPLEMENTED; 380 } 381 382 /** 383 * ixgbe_read_i2c_combined_generic - Perform I2C read combined operation 384 * @hw: pointer to the hardware structure 385 * @addr: I2C bus address to read from 386 * @reg: I2C device register to read from 387 * @val: pointer to location to receive read value 388 * 389 * Returns an error code on error. 390 **/ 391 static s32 ixgbe_read_i2c_combined_generic(struct ixgbe_hw *hw, u8 addr, 392 u16 reg, u16 *val) 393 { 394 return ixgbe_read_i2c_combined_generic_int(hw, addr, reg, val, true); 395 } 396 397 /** 398 * ixgbe_read_i2c_combined_generic_unlocked - Do I2C read combined operation 399 * @hw: pointer to the hardware structure 400 * @addr: I2C bus address to read from 401 * @reg: I2C device register to read from 402 * @val: pointer to location to receive read value 403 * 404 * Returns an error code on error. 405 **/ 406 static s32 407 ixgbe_read_i2c_combined_generic_unlocked(struct ixgbe_hw *hw, u8 addr, 408 u16 reg, u16 *val) 409 { 410 return ixgbe_read_i2c_combined_generic_int(hw, addr, reg, val, false); 411 } 412 413 /** 414 * ixgbe_write_i2c_combined_generic - Perform I2C write combined operation 415 * @hw: pointer to the hardware structure 416 * @addr: I2C bus address to write to 417 * @reg: I2C device register to write to 418 * @val: value to write 419 * 420 * Returns an error code on error. 421 **/ 422 static s32 ixgbe_write_i2c_combined_generic(struct ixgbe_hw *hw, 423 u8 addr, u16 reg, u16 val) 424 { 425 return ixgbe_write_i2c_combined_generic_int(hw, addr, reg, val, true); 426 } 427 428 /** 429 * ixgbe_write_i2c_combined_generic_unlocked - Do I2C write combined operation 430 * @hw: pointer to the hardware structure 431 * @addr: I2C bus address to write to 432 * @reg: I2C device register to write to 433 * @val: value to write 434 * 435 * Returns an error code on error. 436 **/ 437 static s32 438 ixgbe_write_i2c_combined_generic_unlocked(struct ixgbe_hw *hw, 439 u8 addr, u16 reg, u16 val) 440 { 441 return ixgbe_write_i2c_combined_generic_int(hw, addr, reg, val, false); 442 } 443 444 /** 445 * ixgbe_fw_phy_activity - Perform an activity on a PHY 446 * @hw: pointer to hardware structure 447 * @activity: activity to perform 448 * @data: Pointer to 4 32-bit words of data 449 */ 450 s32 ixgbe_fw_phy_activity(struct ixgbe_hw *hw, u16 activity, 451 u32 (*data)[FW_PHY_ACT_DATA_COUNT]) 452 { 453 union { 454 struct ixgbe_hic_phy_activity_req cmd; 455 struct ixgbe_hic_phy_activity_resp rsp; 456 } hic; 457 u16 retries = FW_PHY_ACT_RETRIES; 458 s32 rc; 459 u32 i; 460 461 do { 462 memset(&hic, 0, sizeof(hic)); 463 hic.cmd.hdr.cmd = FW_PHY_ACT_REQ_CMD; 464 hic.cmd.hdr.buf_len = FW_PHY_ACT_REQ_LEN; 465 hic.cmd.hdr.checksum = FW_DEFAULT_CHECKSUM; 466 hic.cmd.port_number = hw->bus.lan_id; 467 hic.cmd.activity_id = cpu_to_le16(activity); 468 for (i = 0; i < ARRAY_SIZE(hic.cmd.data); ++i) 469 hic.cmd.data[i] = cpu_to_be32((*data)[i]); 470 471 rc = ixgbe_host_interface_command(hw, &hic.cmd, sizeof(hic.cmd), 472 IXGBE_HI_COMMAND_TIMEOUT, 473 true); 474 if (rc) 475 return rc; 476 if (hic.rsp.hdr.cmd_or_resp.ret_status == 477 FW_CEM_RESP_STATUS_SUCCESS) { 478 for (i = 0; i < FW_PHY_ACT_DATA_COUNT; ++i) 479 (*data)[i] = be32_to_cpu(hic.rsp.data[i]); 480 return 0; 481 } 482 usleep_range(20, 30); 483 --retries; 484 } while (retries > 0); 485 486 return IXGBE_ERR_HOST_INTERFACE_COMMAND; 487 } 488 489 static const struct { 490 u16 fw_speed; 491 ixgbe_link_speed phy_speed; 492 } ixgbe_fw_map[] = { 493 { FW_PHY_ACT_LINK_SPEED_10, IXGBE_LINK_SPEED_10_FULL }, 494 { FW_PHY_ACT_LINK_SPEED_100, IXGBE_LINK_SPEED_100_FULL }, 495 { FW_PHY_ACT_LINK_SPEED_1G, IXGBE_LINK_SPEED_1GB_FULL }, 496 { FW_PHY_ACT_LINK_SPEED_2_5G, IXGBE_LINK_SPEED_2_5GB_FULL }, 497 { FW_PHY_ACT_LINK_SPEED_5G, IXGBE_LINK_SPEED_5GB_FULL }, 498 { FW_PHY_ACT_LINK_SPEED_10G, IXGBE_LINK_SPEED_10GB_FULL }, 499 }; 500 501 /** 502 * ixgbe_get_phy_id_fw - Get the phy ID via firmware command 503 * @hw: pointer to hardware structure 504 * 505 * Returns error code 506 */ 507 static s32 ixgbe_get_phy_id_fw(struct ixgbe_hw *hw) 508 { 509 u32 info[FW_PHY_ACT_DATA_COUNT] = { 0 }; 510 u16 phy_speeds; 511 u16 phy_id_lo; 512 s32 rc; 513 u16 i; 514 515 if (hw->phy.id) 516 return 0; 517 518 rc = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_GET_PHY_INFO, &info); 519 if (rc) 520 return rc; 521 522 hw->phy.speeds_supported = 0; 523 phy_speeds = info[0] & FW_PHY_INFO_SPEED_MASK; 524 for (i = 0; i < ARRAY_SIZE(ixgbe_fw_map); ++i) { 525 if (phy_speeds & ixgbe_fw_map[i].fw_speed) 526 hw->phy.speeds_supported |= ixgbe_fw_map[i].phy_speed; 527 } 528 529 hw->phy.id = info[0] & FW_PHY_INFO_ID_HI_MASK; 530 phy_id_lo = info[1] & FW_PHY_INFO_ID_LO_MASK; 531 hw->phy.id |= phy_id_lo & IXGBE_PHY_REVISION_MASK; 532 hw->phy.revision = phy_id_lo & ~IXGBE_PHY_REVISION_MASK; 533 if (!hw->phy.id || hw->phy.id == IXGBE_PHY_REVISION_MASK) 534 return IXGBE_ERR_PHY_ADDR_INVALID; 535 536 hw->phy.autoneg_advertised = hw->phy.speeds_supported; 537 hw->phy.eee_speeds_supported = IXGBE_LINK_SPEED_100_FULL | 538 IXGBE_LINK_SPEED_1GB_FULL; 539 hw->phy.eee_speeds_advertised = hw->phy.eee_speeds_supported; 540 return 0; 541 } 542 543 /** 544 * ixgbe_identify_phy_fw - Get PHY type based on firmware command 545 * @hw: pointer to hardware structure 546 * 547 * Returns error code 548 */ 549 static s32 ixgbe_identify_phy_fw(struct ixgbe_hw *hw) 550 { 551 if (hw->bus.lan_id) 552 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY1_SM; 553 else 554 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY0_SM; 555 556 hw->phy.type = ixgbe_phy_fw; 557 hw->phy.ops.read_reg = NULL; 558 hw->phy.ops.write_reg = NULL; 559 return ixgbe_get_phy_id_fw(hw); 560 } 561 562 /** 563 * ixgbe_shutdown_fw_phy - Shutdown a firmware-controlled PHY 564 * @hw: pointer to hardware structure 565 * 566 * Returns error code 567 */ 568 static s32 ixgbe_shutdown_fw_phy(struct ixgbe_hw *hw) 569 { 570 u32 setup[FW_PHY_ACT_DATA_COUNT] = { 0 }; 571 572 setup[0] = FW_PHY_ACT_FORCE_LINK_DOWN_OFF; 573 return ixgbe_fw_phy_activity(hw, FW_PHY_ACT_FORCE_LINK_DOWN, &setup); 574 } 575 576 /** 577 * ixgbe_setup_fw_link - Setup firmware-controlled PHYs 578 * @hw: pointer to hardware structure 579 */ 580 static s32 ixgbe_setup_fw_link(struct ixgbe_hw *hw) 581 { 582 u32 setup[FW_PHY_ACT_DATA_COUNT] = { 0 }; 583 s32 rc; 584 u16 i; 585 586 if (hw->phy.reset_disable || ixgbe_check_reset_blocked(hw)) 587 return 0; 588 589 if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) { 590 hw_err(hw, "rx_pause not valid in strict IEEE mode\n"); 591 return IXGBE_ERR_INVALID_LINK_SETTINGS; 592 } 593 594 switch (hw->fc.requested_mode) { 595 case ixgbe_fc_full: 596 setup[0] |= FW_PHY_ACT_SETUP_LINK_PAUSE_RXTX << 597 FW_PHY_ACT_SETUP_LINK_PAUSE_SHIFT; 598 break; 599 case ixgbe_fc_rx_pause: 600 setup[0] |= FW_PHY_ACT_SETUP_LINK_PAUSE_RX << 601 FW_PHY_ACT_SETUP_LINK_PAUSE_SHIFT; 602 break; 603 case ixgbe_fc_tx_pause: 604 setup[0] |= FW_PHY_ACT_SETUP_LINK_PAUSE_TX << 605 FW_PHY_ACT_SETUP_LINK_PAUSE_SHIFT; 606 break; 607 default: 608 break; 609 } 610 611 for (i = 0; i < ARRAY_SIZE(ixgbe_fw_map); ++i) { 612 if (hw->phy.autoneg_advertised & ixgbe_fw_map[i].phy_speed) 613 setup[0] |= ixgbe_fw_map[i].fw_speed; 614 } 615 setup[0] |= FW_PHY_ACT_SETUP_LINK_HP | FW_PHY_ACT_SETUP_LINK_AN; 616 617 if (hw->phy.eee_speeds_advertised) 618 setup[0] |= FW_PHY_ACT_SETUP_LINK_EEE; 619 620 rc = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_SETUP_LINK, &setup); 621 if (rc) 622 return rc; 623 if (setup[0] == FW_PHY_ACT_SETUP_LINK_RSP_DOWN) 624 return IXGBE_ERR_OVERTEMP; 625 return 0; 626 } 627 628 /** 629 * ixgbe_fc_autoneg_fw - Set up flow control for FW-controlled PHYs 630 * @hw: pointer to hardware structure 631 * 632 * Called at init time to set up flow control. 633 */ 634 static s32 ixgbe_fc_autoneg_fw(struct ixgbe_hw *hw) 635 { 636 if (hw->fc.requested_mode == ixgbe_fc_default) 637 hw->fc.requested_mode = ixgbe_fc_full; 638 639 return ixgbe_setup_fw_link(hw); 640 } 641 642 /** ixgbe_init_eeprom_params_X550 - Initialize EEPROM params 643 * @hw: pointer to hardware structure 644 * 645 * Initializes the EEPROM parameters ixgbe_eeprom_info within the 646 * ixgbe_hw struct in order to set up EEPROM access. 647 **/ 648 static s32 ixgbe_init_eeprom_params_X550(struct ixgbe_hw *hw) 649 { 650 struct ixgbe_eeprom_info *eeprom = &hw->eeprom; 651 u32 eec; 652 u16 eeprom_size; 653 654 if (eeprom->type == ixgbe_eeprom_uninitialized) { 655 eeprom->semaphore_delay = 10; 656 eeprom->type = ixgbe_flash; 657 658 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw)); 659 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >> 660 IXGBE_EEC_SIZE_SHIFT); 661 eeprom->word_size = BIT(eeprom_size + 662 IXGBE_EEPROM_WORD_SIZE_SHIFT); 663 664 hw_dbg(hw, "Eeprom params: type = %d, size = %d\n", 665 eeprom->type, eeprom->word_size); 666 } 667 668 return 0; 669 } 670 671 /** 672 * ixgbe_iosf_wait - Wait for IOSF command completion 673 * @hw: pointer to hardware structure 674 * @ctrl: pointer to location to receive final IOSF control value 675 * 676 * Return: failing status on timeout 677 * 678 * Note: ctrl can be NULL if the IOSF control register value is not needed 679 */ 680 static s32 ixgbe_iosf_wait(struct ixgbe_hw *hw, u32 *ctrl) 681 { 682 u32 i, command; 683 684 /* Check every 10 usec to see if the address cycle completed. 685 * The SB IOSF BUSY bit will clear when the operation is 686 * complete. 687 */ 688 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { 689 command = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL); 690 if (!(command & IXGBE_SB_IOSF_CTRL_BUSY)) 691 break; 692 udelay(10); 693 } 694 if (ctrl) 695 *ctrl = command; 696 if (i == IXGBE_MDIO_COMMAND_TIMEOUT) { 697 hw_dbg(hw, "IOSF wait timed out\n"); 698 return IXGBE_ERR_PHY; 699 } 700 701 return 0; 702 } 703 704 /** ixgbe_read_iosf_sb_reg_x550 - Writes a value to specified register of the 705 * IOSF device 706 * @hw: pointer to hardware structure 707 * @reg_addr: 32 bit PHY register to write 708 * @device_type: 3 bit device type 709 * @phy_data: Pointer to read data from the register 710 **/ 711 static s32 ixgbe_read_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr, 712 u32 device_type, u32 *data) 713 { 714 u32 gssr = IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_PHY0_SM; 715 u32 command, error; 716 s32 ret; 717 718 ret = hw->mac.ops.acquire_swfw_sync(hw, gssr); 719 if (ret) 720 return ret; 721 722 ret = ixgbe_iosf_wait(hw, NULL); 723 if (ret) 724 goto out; 725 726 command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) | 727 (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT)); 728 729 /* Write IOSF control register */ 730 IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command); 731 732 ret = ixgbe_iosf_wait(hw, &command); 733 734 if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) { 735 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >> 736 IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT; 737 hw_dbg(hw, "Failed to read, error %x\n", error); 738 return IXGBE_ERR_PHY; 739 } 740 741 if (!ret) 742 *data = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA); 743 744 out: 745 hw->mac.ops.release_swfw_sync(hw, gssr); 746 return ret; 747 } 748 749 /** 750 * ixgbe_get_phy_token - Get the token for shared PHY access 751 * @hw: Pointer to hardware structure 752 */ 753 static s32 ixgbe_get_phy_token(struct ixgbe_hw *hw) 754 { 755 struct ixgbe_hic_phy_token_req token_cmd; 756 s32 status; 757 758 token_cmd.hdr.cmd = FW_PHY_TOKEN_REQ_CMD; 759 token_cmd.hdr.buf_len = FW_PHY_TOKEN_REQ_LEN; 760 token_cmd.hdr.cmd_or_resp.cmd_resv = 0; 761 token_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM; 762 token_cmd.port_number = hw->bus.lan_id; 763 token_cmd.command_type = FW_PHY_TOKEN_REQ; 764 token_cmd.pad = 0; 765 status = ixgbe_host_interface_command(hw, &token_cmd, sizeof(token_cmd), 766 IXGBE_HI_COMMAND_TIMEOUT, 767 true); 768 if (status) 769 return status; 770 if (token_cmd.hdr.cmd_or_resp.ret_status == FW_PHY_TOKEN_OK) 771 return 0; 772 if (token_cmd.hdr.cmd_or_resp.ret_status != FW_PHY_TOKEN_RETRY) 773 return IXGBE_ERR_FW_RESP_INVALID; 774 775 return IXGBE_ERR_TOKEN_RETRY; 776 } 777 778 /** 779 * ixgbe_put_phy_token - Put the token for shared PHY access 780 * @hw: Pointer to hardware structure 781 */ 782 static s32 ixgbe_put_phy_token(struct ixgbe_hw *hw) 783 { 784 struct ixgbe_hic_phy_token_req token_cmd; 785 s32 status; 786 787 token_cmd.hdr.cmd = FW_PHY_TOKEN_REQ_CMD; 788 token_cmd.hdr.buf_len = FW_PHY_TOKEN_REQ_LEN; 789 token_cmd.hdr.cmd_or_resp.cmd_resv = 0; 790 token_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM; 791 token_cmd.port_number = hw->bus.lan_id; 792 token_cmd.command_type = FW_PHY_TOKEN_REL; 793 token_cmd.pad = 0; 794 status = ixgbe_host_interface_command(hw, &token_cmd, sizeof(token_cmd), 795 IXGBE_HI_COMMAND_TIMEOUT, 796 true); 797 if (status) 798 return status; 799 if (token_cmd.hdr.cmd_or_resp.ret_status == FW_PHY_TOKEN_OK) 800 return 0; 801 return IXGBE_ERR_FW_RESP_INVALID; 802 } 803 804 /** 805 * ixgbe_write_iosf_sb_reg_x550a - Write to IOSF PHY register 806 * @hw: pointer to hardware structure 807 * @reg_addr: 32 bit PHY register to write 808 * @device_type: 3 bit device type 809 * @data: Data to write to the register 810 **/ 811 static s32 ixgbe_write_iosf_sb_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr, 812 __always_unused u32 device_type, 813 u32 data) 814 { 815 struct ixgbe_hic_internal_phy_req write_cmd; 816 817 memset(&write_cmd, 0, sizeof(write_cmd)); 818 write_cmd.hdr.cmd = FW_INT_PHY_REQ_CMD; 819 write_cmd.hdr.buf_len = FW_INT_PHY_REQ_LEN; 820 write_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM; 821 write_cmd.port_number = hw->bus.lan_id; 822 write_cmd.command_type = FW_INT_PHY_REQ_WRITE; 823 write_cmd.address = cpu_to_be16(reg_addr); 824 write_cmd.write_data = cpu_to_be32(data); 825 826 return ixgbe_host_interface_command(hw, &write_cmd, sizeof(write_cmd), 827 IXGBE_HI_COMMAND_TIMEOUT, false); 828 } 829 830 /** 831 * ixgbe_read_iosf_sb_reg_x550a - Read from IOSF PHY register 832 * @hw: pointer to hardware structure 833 * @reg_addr: 32 bit PHY register to write 834 * @device_type: 3 bit device type 835 * @data: Pointer to read data from the register 836 **/ 837 static s32 ixgbe_read_iosf_sb_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr, 838 __always_unused u32 device_type, 839 u32 *data) 840 { 841 union { 842 struct ixgbe_hic_internal_phy_req cmd; 843 struct ixgbe_hic_internal_phy_resp rsp; 844 } hic; 845 s32 status; 846 847 memset(&hic, 0, sizeof(hic)); 848 hic.cmd.hdr.cmd = FW_INT_PHY_REQ_CMD; 849 hic.cmd.hdr.buf_len = FW_INT_PHY_REQ_LEN; 850 hic.cmd.hdr.checksum = FW_DEFAULT_CHECKSUM; 851 hic.cmd.port_number = hw->bus.lan_id; 852 hic.cmd.command_type = FW_INT_PHY_REQ_READ; 853 hic.cmd.address = cpu_to_be16(reg_addr); 854 855 status = ixgbe_host_interface_command(hw, &hic.cmd, sizeof(hic.cmd), 856 IXGBE_HI_COMMAND_TIMEOUT, true); 857 858 /* Extract the register value from the response. */ 859 *data = be32_to_cpu(hic.rsp.read_data); 860 861 return status; 862 } 863 864 /** ixgbe_read_ee_hostif_buffer_X550- Read EEPROM word(s) using hostif 865 * @hw: pointer to hardware structure 866 * @offset: offset of word in the EEPROM to read 867 * @words: number of words 868 * @data: word(s) read from the EEPROM 869 * 870 * Reads a 16 bit word(s) from the EEPROM using the hostif. 871 **/ 872 static s32 ixgbe_read_ee_hostif_buffer_X550(struct ixgbe_hw *hw, 873 u16 offset, u16 words, u16 *data) 874 { 875 const u32 mask = IXGBE_GSSR_SW_MNG_SM | IXGBE_GSSR_EEP_SM; 876 struct ixgbe_hic_read_shadow_ram buffer; 877 u32 current_word = 0; 878 u16 words_to_read; 879 s32 status; 880 u32 i; 881 882 /* Take semaphore for the entire operation. */ 883 status = hw->mac.ops.acquire_swfw_sync(hw, mask); 884 if (status) { 885 hw_dbg(hw, "EEPROM read buffer - semaphore failed\n"); 886 return status; 887 } 888 889 while (words) { 890 if (words > FW_MAX_READ_BUFFER_SIZE / 2) 891 words_to_read = FW_MAX_READ_BUFFER_SIZE / 2; 892 else 893 words_to_read = words; 894 895 buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD; 896 buffer.hdr.req.buf_lenh = 0; 897 buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN; 898 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM; 899 900 /* convert offset from words to bytes */ 901 buffer.address = cpu_to_be32((offset + current_word) * 2); 902 buffer.length = cpu_to_be16(words_to_read * 2); 903 904 status = ixgbe_hic_unlocked(hw, (u32 *)&buffer, sizeof(buffer), 905 IXGBE_HI_COMMAND_TIMEOUT); 906 if (status) { 907 hw_dbg(hw, "Host interface command failed\n"); 908 goto out; 909 } 910 911 for (i = 0; i < words_to_read; i++) { 912 u32 reg = IXGBE_FLEX_MNG + (FW_NVM_DATA_OFFSET << 2) + 913 2 * i; 914 u32 value = IXGBE_READ_REG(hw, reg); 915 916 data[current_word] = (u16)(value & 0xffff); 917 current_word++; 918 i++; 919 if (i < words_to_read) { 920 value >>= 16; 921 data[current_word] = (u16)(value & 0xffff); 922 current_word++; 923 } 924 } 925 words -= words_to_read; 926 } 927 928 out: 929 hw->mac.ops.release_swfw_sync(hw, mask); 930 return status; 931 } 932 933 /** ixgbe_checksum_ptr_x550 - Checksum one pointer region 934 * @hw: pointer to hardware structure 935 * @ptr: pointer offset in eeprom 936 * @size: size of section pointed by ptr, if 0 first word will be used as size 937 * @csum: address of checksum to update 938 * 939 * Returns error status for any failure 940 **/ 941 static s32 ixgbe_checksum_ptr_x550(struct ixgbe_hw *hw, u16 ptr, 942 u16 size, u16 *csum, u16 *buffer, 943 u32 buffer_size) 944 { 945 u16 buf[256]; 946 s32 status; 947 u16 length, bufsz, i, start; 948 u16 *local_buffer; 949 950 bufsz = sizeof(buf) / sizeof(buf[0]); 951 952 /* Read a chunk at the pointer location */ 953 if (!buffer) { 954 status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr, bufsz, buf); 955 if (status) { 956 hw_dbg(hw, "Failed to read EEPROM image\n"); 957 return status; 958 } 959 local_buffer = buf; 960 } else { 961 if (buffer_size < ptr) 962 return IXGBE_ERR_PARAM; 963 local_buffer = &buffer[ptr]; 964 } 965 966 if (size) { 967 start = 0; 968 length = size; 969 } else { 970 start = 1; 971 length = local_buffer[0]; 972 973 /* Skip pointer section if length is invalid. */ 974 if (length == 0xFFFF || length == 0 || 975 (ptr + length) >= hw->eeprom.word_size) 976 return 0; 977 } 978 979 if (buffer && ((u32)start + (u32)length > buffer_size)) 980 return IXGBE_ERR_PARAM; 981 982 for (i = start; length; i++, length--) { 983 if (i == bufsz && !buffer) { 984 ptr += bufsz; 985 i = 0; 986 if (length < bufsz) 987 bufsz = length; 988 989 /* Read a chunk at the pointer location */ 990 status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr, 991 bufsz, buf); 992 if (status) { 993 hw_dbg(hw, "Failed to read EEPROM image\n"); 994 return status; 995 } 996 } 997 *csum += local_buffer[i]; 998 } 999 return 0; 1000 } 1001 1002 /** ixgbe_calc_checksum_X550 - Calculates and returns the checksum 1003 * @hw: pointer to hardware structure 1004 * @buffer: pointer to buffer containing calculated checksum 1005 * @buffer_size: size of buffer 1006 * 1007 * Returns a negative error code on error, or the 16-bit checksum 1008 **/ 1009 static s32 ixgbe_calc_checksum_X550(struct ixgbe_hw *hw, u16 *buffer, 1010 u32 buffer_size) 1011 { 1012 u16 eeprom_ptrs[IXGBE_EEPROM_LAST_WORD + 1]; 1013 u16 *local_buffer; 1014 s32 status; 1015 u16 checksum = 0; 1016 u16 pointer, i, size; 1017 1018 hw->eeprom.ops.init_params(hw); 1019 1020 if (!buffer) { 1021 /* Read pointer area */ 1022 status = ixgbe_read_ee_hostif_buffer_X550(hw, 0, 1023 IXGBE_EEPROM_LAST_WORD + 1, 1024 eeprom_ptrs); 1025 if (status) { 1026 hw_dbg(hw, "Failed to read EEPROM image\n"); 1027 return status; 1028 } 1029 local_buffer = eeprom_ptrs; 1030 } else { 1031 if (buffer_size < IXGBE_EEPROM_LAST_WORD) 1032 return IXGBE_ERR_PARAM; 1033 local_buffer = buffer; 1034 } 1035 1036 /* For X550 hardware include 0x0-0x41 in the checksum, skip the 1037 * checksum word itself 1038 */ 1039 for (i = 0; i <= IXGBE_EEPROM_LAST_WORD; i++) 1040 if (i != IXGBE_EEPROM_CHECKSUM) 1041 checksum += local_buffer[i]; 1042 1043 /* Include all data from pointers 0x3, 0x6-0xE. This excludes the 1044 * FW, PHY module, and PCIe Expansion/Option ROM pointers. 1045 */ 1046 for (i = IXGBE_PCIE_ANALOG_PTR_X550; i < IXGBE_FW_PTR; i++) { 1047 if (i == IXGBE_PHY_PTR || i == IXGBE_OPTION_ROM_PTR) 1048 continue; 1049 1050 pointer = local_buffer[i]; 1051 1052 /* Skip pointer section if the pointer is invalid. */ 1053 if (pointer == 0xFFFF || pointer == 0 || 1054 pointer >= hw->eeprom.word_size) 1055 continue; 1056 1057 switch (i) { 1058 case IXGBE_PCIE_GENERAL_PTR: 1059 size = IXGBE_IXGBE_PCIE_GENERAL_SIZE; 1060 break; 1061 case IXGBE_PCIE_CONFIG0_PTR: 1062 case IXGBE_PCIE_CONFIG1_PTR: 1063 size = IXGBE_PCIE_CONFIG_SIZE; 1064 break; 1065 default: 1066 size = 0; 1067 break; 1068 } 1069 1070 status = ixgbe_checksum_ptr_x550(hw, pointer, size, &checksum, 1071 buffer, buffer_size); 1072 if (status) 1073 return status; 1074 } 1075 1076 checksum = (u16)IXGBE_EEPROM_SUM - checksum; 1077 1078 return (s32)checksum; 1079 } 1080 1081 /** ixgbe_calc_eeprom_checksum_X550 - Calculates and returns the checksum 1082 * @hw: pointer to hardware structure 1083 * 1084 * Returns a negative error code on error, or the 16-bit checksum 1085 **/ 1086 static s32 ixgbe_calc_eeprom_checksum_X550(struct ixgbe_hw *hw) 1087 { 1088 return ixgbe_calc_checksum_X550(hw, NULL, 0); 1089 } 1090 1091 /** ixgbe_read_ee_hostif_X550 - Read EEPROM word using a host interface command 1092 * @hw: pointer to hardware structure 1093 * @offset: offset of word in the EEPROM to read 1094 * @data: word read from the EEPROM 1095 * 1096 * Reads a 16 bit word from the EEPROM using the hostif. 1097 **/ 1098 static s32 ixgbe_read_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset, u16 *data) 1099 { 1100 const u32 mask = IXGBE_GSSR_SW_MNG_SM | IXGBE_GSSR_EEP_SM; 1101 struct ixgbe_hic_read_shadow_ram buffer; 1102 s32 status; 1103 1104 buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD; 1105 buffer.hdr.req.buf_lenh = 0; 1106 buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN; 1107 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM; 1108 1109 /* convert offset from words to bytes */ 1110 buffer.address = cpu_to_be32(offset * 2); 1111 /* one word */ 1112 buffer.length = cpu_to_be16(sizeof(u16)); 1113 1114 status = hw->mac.ops.acquire_swfw_sync(hw, mask); 1115 if (status) 1116 return status; 1117 1118 status = ixgbe_hic_unlocked(hw, (u32 *)&buffer, sizeof(buffer), 1119 IXGBE_HI_COMMAND_TIMEOUT); 1120 if (!status) { 1121 *data = (u16)IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG, 1122 FW_NVM_DATA_OFFSET); 1123 } 1124 1125 hw->mac.ops.release_swfw_sync(hw, mask); 1126 return status; 1127 } 1128 1129 /** ixgbe_validate_eeprom_checksum_X550 - Validate EEPROM checksum 1130 * @hw: pointer to hardware structure 1131 * @checksum_val: calculated checksum 1132 * 1133 * Performs checksum calculation and validates the EEPROM checksum. If the 1134 * caller does not need checksum_val, the value can be NULL. 1135 **/ 1136 static s32 ixgbe_validate_eeprom_checksum_X550(struct ixgbe_hw *hw, 1137 u16 *checksum_val) 1138 { 1139 s32 status; 1140 u16 checksum; 1141 u16 read_checksum = 0; 1142 1143 /* Read the first word from the EEPROM. If this times out or fails, do 1144 * not continue or we could be in for a very long wait while every 1145 * EEPROM read fails 1146 */ 1147 status = hw->eeprom.ops.read(hw, 0, &checksum); 1148 if (status) { 1149 hw_dbg(hw, "EEPROM read failed\n"); 1150 return status; 1151 } 1152 1153 status = hw->eeprom.ops.calc_checksum(hw); 1154 if (status < 0) 1155 return status; 1156 1157 checksum = (u16)(status & 0xffff); 1158 1159 status = ixgbe_read_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM, 1160 &read_checksum); 1161 if (status) 1162 return status; 1163 1164 /* Verify read checksum from EEPROM is the same as 1165 * calculated checksum 1166 */ 1167 if (read_checksum != checksum) { 1168 status = IXGBE_ERR_EEPROM_CHECKSUM; 1169 hw_dbg(hw, "Invalid EEPROM checksum"); 1170 } 1171 1172 /* If the user cares, return the calculated checksum */ 1173 if (checksum_val) 1174 *checksum_val = checksum; 1175 1176 return status; 1177 } 1178 1179 /** ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif 1180 * @hw: pointer to hardware structure 1181 * @offset: offset of word in the EEPROM to write 1182 * @data: word write to the EEPROM 1183 * 1184 * Write a 16 bit word to the EEPROM using the hostif. 1185 **/ 1186 static s32 ixgbe_write_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset, 1187 u16 data) 1188 { 1189 s32 status; 1190 struct ixgbe_hic_write_shadow_ram buffer; 1191 1192 buffer.hdr.req.cmd = FW_WRITE_SHADOW_RAM_CMD; 1193 buffer.hdr.req.buf_lenh = 0; 1194 buffer.hdr.req.buf_lenl = FW_WRITE_SHADOW_RAM_LEN; 1195 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM; 1196 1197 /* one word */ 1198 buffer.length = cpu_to_be16(sizeof(u16)); 1199 buffer.data = data; 1200 buffer.address = cpu_to_be32(offset * 2); 1201 1202 status = ixgbe_host_interface_command(hw, &buffer, sizeof(buffer), 1203 IXGBE_HI_COMMAND_TIMEOUT, false); 1204 return status; 1205 } 1206 1207 /** ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif 1208 * @hw: pointer to hardware structure 1209 * @offset: offset of word in the EEPROM to write 1210 * @data: word write to the EEPROM 1211 * 1212 * Write a 16 bit word to the EEPROM using the hostif. 1213 **/ 1214 static s32 ixgbe_write_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset, u16 data) 1215 { 1216 s32 status = 0; 1217 1218 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) == 0) { 1219 status = ixgbe_write_ee_hostif_data_X550(hw, offset, data); 1220 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 1221 } else { 1222 hw_dbg(hw, "write ee hostif failed to get semaphore"); 1223 status = IXGBE_ERR_SWFW_SYNC; 1224 } 1225 1226 return status; 1227 } 1228 1229 /** ixgbe_update_flash_X550 - Instruct HW to copy EEPROM to Flash device 1230 * @hw: pointer to hardware structure 1231 * 1232 * Issue a shadow RAM dump to FW to copy EEPROM from shadow RAM to the flash. 1233 **/ 1234 static s32 ixgbe_update_flash_X550(struct ixgbe_hw *hw) 1235 { 1236 s32 status = 0; 1237 union ixgbe_hic_hdr2 buffer; 1238 1239 buffer.req.cmd = FW_SHADOW_RAM_DUMP_CMD; 1240 buffer.req.buf_lenh = 0; 1241 buffer.req.buf_lenl = FW_SHADOW_RAM_DUMP_LEN; 1242 buffer.req.checksum = FW_DEFAULT_CHECKSUM; 1243 1244 status = ixgbe_host_interface_command(hw, &buffer, sizeof(buffer), 1245 IXGBE_HI_COMMAND_TIMEOUT, false); 1246 return status; 1247 } 1248 1249 /** 1250 * ixgbe_get_bus_info_X550em - Set PCI bus info 1251 * @hw: pointer to hardware structure 1252 * 1253 * Sets bus link width and speed to unknown because X550em is 1254 * not a PCI device. 1255 **/ 1256 static s32 ixgbe_get_bus_info_X550em(struct ixgbe_hw *hw) 1257 { 1258 hw->bus.type = ixgbe_bus_type_internal; 1259 hw->bus.width = ixgbe_bus_width_unknown; 1260 hw->bus.speed = ixgbe_bus_speed_unknown; 1261 1262 hw->mac.ops.set_lan_id(hw); 1263 1264 return 0; 1265 } 1266 1267 /** ixgbe_disable_rx_x550 - Disable RX unit 1268 * 1269 * Enables the Rx DMA unit for x550 1270 **/ 1271 static void ixgbe_disable_rx_x550(struct ixgbe_hw *hw) 1272 { 1273 u32 rxctrl, pfdtxgswc; 1274 s32 status; 1275 struct ixgbe_hic_disable_rxen fw_cmd; 1276 1277 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL); 1278 if (rxctrl & IXGBE_RXCTRL_RXEN) { 1279 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC); 1280 if (pfdtxgswc & IXGBE_PFDTXGSWC_VT_LBEN) { 1281 pfdtxgswc &= ~IXGBE_PFDTXGSWC_VT_LBEN; 1282 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc); 1283 hw->mac.set_lben = true; 1284 } else { 1285 hw->mac.set_lben = false; 1286 } 1287 1288 fw_cmd.hdr.cmd = FW_DISABLE_RXEN_CMD; 1289 fw_cmd.hdr.buf_len = FW_DISABLE_RXEN_LEN; 1290 fw_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM; 1291 fw_cmd.port_number = hw->bus.lan_id; 1292 1293 status = ixgbe_host_interface_command(hw, &fw_cmd, 1294 sizeof(struct ixgbe_hic_disable_rxen), 1295 IXGBE_HI_COMMAND_TIMEOUT, true); 1296 1297 /* If we fail - disable RX using register write */ 1298 if (status) { 1299 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL); 1300 if (rxctrl & IXGBE_RXCTRL_RXEN) { 1301 rxctrl &= ~IXGBE_RXCTRL_RXEN; 1302 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl); 1303 } 1304 } 1305 } 1306 } 1307 1308 /** ixgbe_update_eeprom_checksum_X550 - Updates the EEPROM checksum and flash 1309 * @hw: pointer to hardware structure 1310 * 1311 * After writing EEPROM to shadow RAM using EEWR register, software calculates 1312 * checksum and updates the EEPROM and instructs the hardware to update 1313 * the flash. 1314 **/ 1315 static s32 ixgbe_update_eeprom_checksum_X550(struct ixgbe_hw *hw) 1316 { 1317 s32 status; 1318 u16 checksum = 0; 1319 1320 /* Read the first word from the EEPROM. If this times out or fails, do 1321 * not continue or we could be in for a very long wait while every 1322 * EEPROM read fails 1323 */ 1324 status = ixgbe_read_ee_hostif_X550(hw, 0, &checksum); 1325 if (status) { 1326 hw_dbg(hw, "EEPROM read failed\n"); 1327 return status; 1328 } 1329 1330 status = ixgbe_calc_eeprom_checksum_X550(hw); 1331 if (status < 0) 1332 return status; 1333 1334 checksum = (u16)(status & 0xffff); 1335 1336 status = ixgbe_write_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM, 1337 checksum); 1338 if (status) 1339 return status; 1340 1341 status = ixgbe_update_flash_X550(hw); 1342 1343 return status; 1344 } 1345 1346 /** ixgbe_write_ee_hostif_buffer_X550 - Write EEPROM word(s) using hostif 1347 * @hw: pointer to hardware structure 1348 * @offset: offset of word in the EEPROM to write 1349 * @words: number of words 1350 * @data: word(s) write to the EEPROM 1351 * 1352 * 1353 * Write a 16 bit word(s) to the EEPROM using the hostif. 1354 **/ 1355 static s32 ixgbe_write_ee_hostif_buffer_X550(struct ixgbe_hw *hw, 1356 u16 offset, u16 words, 1357 u16 *data) 1358 { 1359 s32 status = 0; 1360 u32 i = 0; 1361 1362 /* Take semaphore for the entire operation. */ 1363 status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 1364 if (status) { 1365 hw_dbg(hw, "EEPROM write buffer - semaphore failed\n"); 1366 return status; 1367 } 1368 1369 for (i = 0; i < words; i++) { 1370 status = ixgbe_write_ee_hostif_data_X550(hw, offset + i, 1371 data[i]); 1372 if (status) { 1373 hw_dbg(hw, "Eeprom buffered write failed\n"); 1374 break; 1375 } 1376 } 1377 1378 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 1379 1380 return status; 1381 } 1382 1383 /** ixgbe_write_iosf_sb_reg_x550 - Writes a value to specified register of the 1384 * IOSF device 1385 * 1386 * @hw: pointer to hardware structure 1387 * @reg_addr: 32 bit PHY register to write 1388 * @device_type: 3 bit device type 1389 * @data: Data to write to the register 1390 **/ 1391 static s32 ixgbe_write_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr, 1392 u32 device_type, u32 data) 1393 { 1394 u32 gssr = IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_PHY0_SM; 1395 u32 command, error; 1396 s32 ret; 1397 1398 ret = hw->mac.ops.acquire_swfw_sync(hw, gssr); 1399 if (ret) 1400 return ret; 1401 1402 ret = ixgbe_iosf_wait(hw, NULL); 1403 if (ret) 1404 goto out; 1405 1406 command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) | 1407 (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT)); 1408 1409 /* Write IOSF control register */ 1410 IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command); 1411 1412 /* Write IOSF data register */ 1413 IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA, data); 1414 1415 ret = ixgbe_iosf_wait(hw, &command); 1416 1417 if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) { 1418 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >> 1419 IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT; 1420 hw_dbg(hw, "Failed to write, error %x\n", error); 1421 return IXGBE_ERR_PHY; 1422 } 1423 1424 out: 1425 hw->mac.ops.release_swfw_sync(hw, gssr); 1426 return ret; 1427 } 1428 1429 /** 1430 * ixgbe_setup_ixfi_x550em_x - MAC specific iXFI configuration 1431 * @hw: pointer to hardware structure 1432 * 1433 * iXfI configuration needed for ixgbe_mac_X550EM_x devices. 1434 **/ 1435 static s32 ixgbe_setup_ixfi_x550em_x(struct ixgbe_hw *hw) 1436 { 1437 s32 status; 1438 u32 reg_val; 1439 1440 /* Disable training protocol FSM. */ 1441 status = ixgbe_read_iosf_sb_reg_x550(hw, 1442 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id), 1443 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val); 1444 if (status) 1445 return status; 1446 1447 reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_CONV_WO_PROTOCOL; 1448 status = ixgbe_write_iosf_sb_reg_x550(hw, 1449 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id), 1450 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val); 1451 if (status) 1452 return status; 1453 1454 /* Disable Flex from training TXFFE. */ 1455 status = ixgbe_read_iosf_sb_reg_x550(hw, 1456 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id), 1457 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val); 1458 if (status) 1459 return status; 1460 1461 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN; 1462 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN; 1463 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN; 1464 status = ixgbe_write_iosf_sb_reg_x550(hw, 1465 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id), 1466 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val); 1467 if (status) 1468 return status; 1469 1470 status = ixgbe_read_iosf_sb_reg_x550(hw, 1471 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id), 1472 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val); 1473 if (status) 1474 return status; 1475 1476 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN; 1477 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN; 1478 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN; 1479 status = ixgbe_write_iosf_sb_reg_x550(hw, 1480 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id), 1481 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val); 1482 if (status) 1483 return status; 1484 1485 /* Enable override for coefficients. */ 1486 status = ixgbe_read_iosf_sb_reg_x550(hw, 1487 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id), 1488 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val); 1489 if (status) 1490 return status; 1491 1492 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_OVRRD_EN; 1493 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CZERO_EN; 1494 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CPLUS1_OVRRD_EN; 1495 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CMINUS1_OVRRD_EN; 1496 status = ixgbe_write_iosf_sb_reg_x550(hw, 1497 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id), 1498 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val); 1499 return status; 1500 } 1501 1502 /** 1503 * ixgbe_restart_an_internal_phy_x550em - restart autonegotiation for the 1504 * internal PHY 1505 * @hw: pointer to hardware structure 1506 **/ 1507 static s32 ixgbe_restart_an_internal_phy_x550em(struct ixgbe_hw *hw) 1508 { 1509 s32 status; 1510 u32 link_ctrl; 1511 1512 /* Restart auto-negotiation. */ 1513 status = hw->mac.ops.read_iosf_sb_reg(hw, 1514 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id), 1515 IXGBE_SB_IOSF_TARGET_KR_PHY, &link_ctrl); 1516 1517 if (status) { 1518 hw_dbg(hw, "Auto-negotiation did not complete\n"); 1519 return status; 1520 } 1521 1522 link_ctrl |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART; 1523 status = hw->mac.ops.write_iosf_sb_reg(hw, 1524 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id), 1525 IXGBE_SB_IOSF_TARGET_KR_PHY, link_ctrl); 1526 1527 if (hw->mac.type == ixgbe_mac_x550em_a) { 1528 u32 flx_mask_st20; 1529 1530 /* Indicate to FW that AN restart has been asserted */ 1531 status = hw->mac.ops.read_iosf_sb_reg(hw, 1532 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id), 1533 IXGBE_SB_IOSF_TARGET_KR_PHY, &flx_mask_st20); 1534 1535 if (status) { 1536 hw_dbg(hw, "Auto-negotiation did not complete\n"); 1537 return status; 1538 } 1539 1540 flx_mask_st20 |= IXGBE_KRM_PMD_FLX_MASK_ST20_FW_AN_RESTART; 1541 status = hw->mac.ops.write_iosf_sb_reg(hw, 1542 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id), 1543 IXGBE_SB_IOSF_TARGET_KR_PHY, flx_mask_st20); 1544 } 1545 1546 return status; 1547 } 1548 1549 /** ixgbe_setup_ixfi_x550em - Configure the KR PHY for iXFI mode. 1550 * @hw: pointer to hardware structure 1551 * @speed: the link speed to force 1552 * 1553 * Configures the integrated KR PHY to use iXFI mode. Used to connect an 1554 * internal and external PHY at a specific speed, without autonegotiation. 1555 **/ 1556 static s32 ixgbe_setup_ixfi_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed) 1557 { 1558 s32 status; 1559 u32 reg_val; 1560 1561 /* Disable AN and force speed to 10G Serial. */ 1562 status = ixgbe_read_iosf_sb_reg_x550(hw, 1563 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id), 1564 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val); 1565 if (status) 1566 return status; 1567 1568 reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE; 1569 reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK; 1570 1571 /* Select forced link speed for internal PHY. */ 1572 switch (*speed) { 1573 case IXGBE_LINK_SPEED_10GB_FULL: 1574 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G; 1575 break; 1576 case IXGBE_LINK_SPEED_1GB_FULL: 1577 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G; 1578 break; 1579 default: 1580 /* Other link speeds are not supported by internal KR PHY. */ 1581 return IXGBE_ERR_LINK_SETUP; 1582 } 1583 1584 status = ixgbe_write_iosf_sb_reg_x550(hw, 1585 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id), 1586 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val); 1587 if (status) 1588 return status; 1589 1590 /* Additional configuration needed for x550em_x */ 1591 if (hw->mac.type == ixgbe_mac_X550EM_x) { 1592 status = ixgbe_setup_ixfi_x550em_x(hw); 1593 if (status) 1594 return status; 1595 } 1596 1597 /* Toggle port SW reset by AN reset. */ 1598 status = ixgbe_restart_an_internal_phy_x550em(hw); 1599 1600 return status; 1601 } 1602 1603 /** 1604 * ixgbe_supported_sfp_modules_X550em - Check if SFP module type is supported 1605 * @hw: pointer to hardware structure 1606 * @linear: true if SFP module is linear 1607 */ 1608 static s32 ixgbe_supported_sfp_modules_X550em(struct ixgbe_hw *hw, bool *linear) 1609 { 1610 switch (hw->phy.sfp_type) { 1611 case ixgbe_sfp_type_not_present: 1612 return IXGBE_ERR_SFP_NOT_PRESENT; 1613 case ixgbe_sfp_type_da_cu_core0: 1614 case ixgbe_sfp_type_da_cu_core1: 1615 *linear = true; 1616 break; 1617 case ixgbe_sfp_type_srlr_core0: 1618 case ixgbe_sfp_type_srlr_core1: 1619 case ixgbe_sfp_type_da_act_lmt_core0: 1620 case ixgbe_sfp_type_da_act_lmt_core1: 1621 case ixgbe_sfp_type_1g_sx_core0: 1622 case ixgbe_sfp_type_1g_sx_core1: 1623 case ixgbe_sfp_type_1g_lx_core0: 1624 case ixgbe_sfp_type_1g_lx_core1: 1625 *linear = false; 1626 break; 1627 case ixgbe_sfp_type_unknown: 1628 case ixgbe_sfp_type_1g_cu_core0: 1629 case ixgbe_sfp_type_1g_cu_core1: 1630 default: 1631 return IXGBE_ERR_SFP_NOT_SUPPORTED; 1632 } 1633 1634 return 0; 1635 } 1636 1637 /** 1638 * ixgbe_setup_mac_link_sfp_x550em - Configure the KR PHY for SFP. 1639 * @hw: pointer to hardware structure 1640 * 1641 * Configures the extern PHY and the integrated KR PHY for SFP support. 1642 */ 1643 static s32 1644 ixgbe_setup_mac_link_sfp_x550em(struct ixgbe_hw *hw, 1645 ixgbe_link_speed speed, 1646 __always_unused bool autoneg_wait_to_complete) 1647 { 1648 s32 status; 1649 u16 reg_slice, reg_val; 1650 bool setup_linear = false; 1651 1652 /* Check if SFP module is supported and linear */ 1653 status = ixgbe_supported_sfp_modules_X550em(hw, &setup_linear); 1654 1655 /* If no SFP module present, then return success. Return success since 1656 * there is no reason to configure CS4227 and SFP not present error is 1657 * not accepted in the setup MAC link flow. 1658 */ 1659 if (status == IXGBE_ERR_SFP_NOT_PRESENT) 1660 return 0; 1661 1662 if (status) 1663 return status; 1664 1665 /* Configure internal PHY for KR/KX. */ 1666 ixgbe_setup_kr_speed_x550em(hw, speed); 1667 1668 /* Configure CS4227 LINE side to proper mode. */ 1669 reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB + (hw->bus.lan_id << 12); 1670 if (setup_linear) 1671 reg_val = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1; 1672 else 1673 reg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1; 1674 1675 status = hw->link.ops.write_link(hw, hw->link.addr, reg_slice, 1676 reg_val); 1677 1678 return status; 1679 } 1680 1681 /** 1682 * ixgbe_setup_sfi_x550a - Configure the internal PHY for native SFI mode 1683 * @hw: pointer to hardware structure 1684 * @speed: the link speed to force 1685 * 1686 * Configures the integrated PHY for native SFI mode. Used to connect the 1687 * internal PHY directly to an SFP cage, without autonegotiation. 1688 **/ 1689 static s32 ixgbe_setup_sfi_x550a(struct ixgbe_hw *hw, ixgbe_link_speed *speed) 1690 { 1691 struct ixgbe_mac_info *mac = &hw->mac; 1692 s32 status; 1693 u32 reg_val; 1694 1695 /* Disable all AN and force speed to 10G Serial. */ 1696 status = mac->ops.read_iosf_sb_reg(hw, 1697 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id), 1698 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val); 1699 if (status) 1700 return status; 1701 1702 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN_EN; 1703 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN37_EN; 1704 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SGMII_EN; 1705 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_MASK; 1706 1707 /* Select forced link speed for internal PHY. */ 1708 switch (*speed) { 1709 case IXGBE_LINK_SPEED_10GB_FULL: 1710 reg_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_10G; 1711 break; 1712 case IXGBE_LINK_SPEED_1GB_FULL: 1713 reg_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_1G; 1714 break; 1715 default: 1716 /* Other link speeds are not supported by internal PHY. */ 1717 return IXGBE_ERR_LINK_SETUP; 1718 } 1719 1720 status = mac->ops.write_iosf_sb_reg(hw, 1721 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id), 1722 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val); 1723 1724 /* Toggle port SW reset by AN reset. */ 1725 status = ixgbe_restart_an_internal_phy_x550em(hw); 1726 1727 return status; 1728 } 1729 1730 /** 1731 * ixgbe_setup_mac_link_sfp_n - Setup internal PHY for native SFP 1732 * @hw: pointer to hardware structure 1733 * 1734 * Configure the the integrated PHY for native SFP support. 1735 */ 1736 static s32 1737 ixgbe_setup_mac_link_sfp_n(struct ixgbe_hw *hw, ixgbe_link_speed speed, 1738 __always_unused bool autoneg_wait_to_complete) 1739 { 1740 bool setup_linear = false; 1741 u32 reg_phy_int; 1742 s32 ret_val; 1743 1744 /* Check if SFP module is supported and linear */ 1745 ret_val = ixgbe_supported_sfp_modules_X550em(hw, &setup_linear); 1746 1747 /* If no SFP module present, then return success. Return success since 1748 * SFP not present error is not excepted in the setup MAC link flow. 1749 */ 1750 if (ret_val == IXGBE_ERR_SFP_NOT_PRESENT) 1751 return 0; 1752 1753 if (!ret_val) 1754 return ret_val; 1755 1756 /* Configure internal PHY for native SFI based on module type */ 1757 ret_val = hw->mac.ops.read_iosf_sb_reg(hw, 1758 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id), 1759 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_phy_int); 1760 if (!ret_val) 1761 return ret_val; 1762 1763 reg_phy_int &= IXGBE_KRM_PMD_FLX_MASK_ST20_SFI_10G_DA; 1764 if (!setup_linear) 1765 reg_phy_int |= IXGBE_KRM_PMD_FLX_MASK_ST20_SFI_10G_SR; 1766 1767 ret_val = hw->mac.ops.write_iosf_sb_reg(hw, 1768 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id), 1769 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_phy_int); 1770 if (!ret_val) 1771 return ret_val; 1772 1773 /* Setup SFI internal link. */ 1774 return ixgbe_setup_sfi_x550a(hw, &speed); 1775 } 1776 1777 /** 1778 * ixgbe_setup_mac_link_sfp_x550a - Setup internal PHY for SFP 1779 * @hw: pointer to hardware structure 1780 * 1781 * Configure the the integrated PHY for SFP support. 1782 */ 1783 static s32 1784 ixgbe_setup_mac_link_sfp_x550a(struct ixgbe_hw *hw, ixgbe_link_speed speed, 1785 __always_unused bool autoneg_wait_to_complete) 1786 { 1787 u32 reg_slice, slice_offset; 1788 bool setup_linear = false; 1789 u16 reg_phy_ext; 1790 s32 ret_val; 1791 1792 /* Check if SFP module is supported and linear */ 1793 ret_val = ixgbe_supported_sfp_modules_X550em(hw, &setup_linear); 1794 1795 /* If no SFP module present, then return success. Return success since 1796 * SFP not present error is not excepted in the setup MAC link flow. 1797 */ 1798 if (ret_val == IXGBE_ERR_SFP_NOT_PRESENT) 1799 return 0; 1800 1801 if (!ret_val) 1802 return ret_val; 1803 1804 /* Configure internal PHY for KR/KX. */ 1805 ixgbe_setup_kr_speed_x550em(hw, speed); 1806 1807 if (hw->phy.mdio.prtad == MDIO_PRTAD_NONE) 1808 return IXGBE_ERR_PHY_ADDR_INVALID; 1809 1810 /* Get external PHY device id */ 1811 ret_val = hw->phy.ops.read_reg(hw, IXGBE_CS4227_GLOBAL_ID_MSB, 1812 IXGBE_MDIO_ZERO_DEV_TYPE, ®_phy_ext); 1813 if (ret_val) 1814 return ret_val; 1815 1816 /* When configuring quad port CS4223, the MAC instance is part 1817 * of the slice offset. 1818 */ 1819 if (reg_phy_ext == IXGBE_CS4223_PHY_ID) 1820 slice_offset = (hw->bus.lan_id + 1821 (hw->bus.instance_id << 1)) << 12; 1822 else 1823 slice_offset = hw->bus.lan_id << 12; 1824 1825 /* Configure CS4227/CS4223 LINE side to proper mode. */ 1826 reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB + slice_offset; 1827 if (setup_linear) 1828 reg_phy_ext = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 1; 1829 else 1830 reg_phy_ext = (IXGBE_CS4227_EDC_MODE_SR << 1) | 1; 1831 return hw->phy.ops.write_reg(hw, reg_slice, IXGBE_MDIO_ZERO_DEV_TYPE, 1832 reg_phy_ext); 1833 } 1834 1835 /** 1836 * ixgbe_setup_mac_link_t_X550em - Sets the auto advertised link speed 1837 * @hw: pointer to hardware structure 1838 * @speed: new link speed 1839 * @autoneg_wait_to_complete: true when waiting for completion is needed 1840 * 1841 * Setup internal/external PHY link speed based on link speed, then set 1842 * external PHY auto advertised link speed. 1843 * 1844 * Returns error status for any failure 1845 **/ 1846 static s32 ixgbe_setup_mac_link_t_X550em(struct ixgbe_hw *hw, 1847 ixgbe_link_speed speed, 1848 bool autoneg_wait) 1849 { 1850 s32 status; 1851 ixgbe_link_speed force_speed; 1852 1853 /* Setup internal/external PHY link speed to iXFI (10G), unless 1854 * only 1G is auto advertised then setup KX link. 1855 */ 1856 if (speed & IXGBE_LINK_SPEED_10GB_FULL) 1857 force_speed = IXGBE_LINK_SPEED_10GB_FULL; 1858 else 1859 force_speed = IXGBE_LINK_SPEED_1GB_FULL; 1860 1861 /* If internal link mode is XFI, then setup XFI internal link. */ 1862 if (!(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) { 1863 status = ixgbe_setup_ixfi_x550em(hw, &force_speed); 1864 1865 if (status) 1866 return status; 1867 } 1868 1869 return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait); 1870 } 1871 1872 /** ixgbe_check_link_t_X550em - Determine link and speed status 1873 * @hw: pointer to hardware structure 1874 * @speed: pointer to link speed 1875 * @link_up: true when link is up 1876 * @link_up_wait_to_complete: bool used to wait for link up or not 1877 * 1878 * Check that both the MAC and X557 external PHY have link. 1879 **/ 1880 static s32 ixgbe_check_link_t_X550em(struct ixgbe_hw *hw, 1881 ixgbe_link_speed *speed, 1882 bool *link_up, 1883 bool link_up_wait_to_complete) 1884 { 1885 u32 status; 1886 u16 i, autoneg_status; 1887 1888 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper) 1889 return IXGBE_ERR_CONFIG; 1890 1891 status = ixgbe_check_mac_link_generic(hw, speed, link_up, 1892 link_up_wait_to_complete); 1893 1894 /* If check link fails or MAC link is not up, then return */ 1895 if (status || !(*link_up)) 1896 return status; 1897 1898 /* MAC link is up, so check external PHY link. 1899 * Link status is latching low, and can only be used to detect link 1900 * drop, and not the current status of the link without performing 1901 * back-to-back reads. 1902 */ 1903 for (i = 0; i < 2; i++) { 1904 status = hw->phy.ops.read_reg(hw, MDIO_STAT1, MDIO_MMD_AN, 1905 &autoneg_status); 1906 1907 if (status) 1908 return status; 1909 } 1910 1911 /* If external PHY link is not up, then indicate link not up */ 1912 if (!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS)) 1913 *link_up = false; 1914 1915 return 0; 1916 } 1917 1918 /** 1919 * ixgbe_setup_sgmii - Set up link for sgmii 1920 * @hw: pointer to hardware structure 1921 */ 1922 static s32 1923 ixgbe_setup_sgmii(struct ixgbe_hw *hw, __always_unused ixgbe_link_speed speed, 1924 __always_unused bool autoneg_wait_to_complete) 1925 { 1926 struct ixgbe_mac_info *mac = &hw->mac; 1927 u32 lval, sval, flx_val; 1928 s32 rc; 1929 1930 rc = mac->ops.read_iosf_sb_reg(hw, 1931 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id), 1932 IXGBE_SB_IOSF_TARGET_KR_PHY, &lval); 1933 if (rc) 1934 return rc; 1935 1936 lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE; 1937 lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK; 1938 lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_SGMII_EN; 1939 lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CLAUSE_37_EN; 1940 lval |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G; 1941 rc = mac->ops.write_iosf_sb_reg(hw, 1942 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id), 1943 IXGBE_SB_IOSF_TARGET_KR_PHY, lval); 1944 if (rc) 1945 return rc; 1946 1947 rc = mac->ops.read_iosf_sb_reg(hw, 1948 IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id), 1949 IXGBE_SB_IOSF_TARGET_KR_PHY, &sval); 1950 if (rc) 1951 return rc; 1952 1953 sval |= IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_10_D; 1954 sval |= IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_100_D; 1955 rc = mac->ops.write_iosf_sb_reg(hw, 1956 IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id), 1957 IXGBE_SB_IOSF_TARGET_KR_PHY, sval); 1958 if (rc) 1959 return rc; 1960 1961 rc = mac->ops.read_iosf_sb_reg(hw, 1962 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id), 1963 IXGBE_SB_IOSF_TARGET_KR_PHY, &flx_val); 1964 if (rc) 1965 return rc; 1966 1967 rc = mac->ops.read_iosf_sb_reg(hw, 1968 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id), 1969 IXGBE_SB_IOSF_TARGET_KR_PHY, &flx_val); 1970 if (rc) 1971 return rc; 1972 1973 flx_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_MASK; 1974 flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_1G; 1975 flx_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN_EN; 1976 flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SGMII_EN; 1977 flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_AN37_EN; 1978 1979 rc = mac->ops.write_iosf_sb_reg(hw, 1980 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id), 1981 IXGBE_SB_IOSF_TARGET_KR_PHY, flx_val); 1982 if (rc) 1983 return rc; 1984 1985 rc = ixgbe_restart_an_internal_phy_x550em(hw); 1986 return rc; 1987 } 1988 1989 /** 1990 * ixgbe_setup_sgmii_fw - Set up link for sgmii with firmware-controlled PHYs 1991 * @hw: pointer to hardware structure 1992 */ 1993 static s32 ixgbe_setup_sgmii_fw(struct ixgbe_hw *hw, ixgbe_link_speed speed, 1994 bool autoneg_wait) 1995 { 1996 struct ixgbe_mac_info *mac = &hw->mac; 1997 u32 lval, sval, flx_val; 1998 s32 rc; 1999 2000 rc = mac->ops.read_iosf_sb_reg(hw, 2001 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id), 2002 IXGBE_SB_IOSF_TARGET_KR_PHY, &lval); 2003 if (rc) 2004 return rc; 2005 2006 lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE; 2007 lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK; 2008 lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_SGMII_EN; 2009 lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CLAUSE_37_EN; 2010 lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G; 2011 rc = mac->ops.write_iosf_sb_reg(hw, 2012 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id), 2013 IXGBE_SB_IOSF_TARGET_KR_PHY, lval); 2014 if (rc) 2015 return rc; 2016 2017 rc = mac->ops.read_iosf_sb_reg(hw, 2018 IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id), 2019 IXGBE_SB_IOSF_TARGET_KR_PHY, &sval); 2020 if (rc) 2021 return rc; 2022 2023 sval &= ~IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_10_D; 2024 sval &= ~IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_100_D; 2025 rc = mac->ops.write_iosf_sb_reg(hw, 2026 IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id), 2027 IXGBE_SB_IOSF_TARGET_KR_PHY, sval); 2028 if (rc) 2029 return rc; 2030 2031 rc = mac->ops.write_iosf_sb_reg(hw, 2032 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id), 2033 IXGBE_SB_IOSF_TARGET_KR_PHY, lval); 2034 if (rc) 2035 return rc; 2036 2037 rc = mac->ops.read_iosf_sb_reg(hw, 2038 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id), 2039 IXGBE_SB_IOSF_TARGET_KR_PHY, &flx_val); 2040 if (rc) 2041 return rc; 2042 2043 flx_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_MASK; 2044 flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_AN; 2045 flx_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN_EN; 2046 flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SGMII_EN; 2047 flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_AN37_EN; 2048 2049 rc = mac->ops.write_iosf_sb_reg(hw, 2050 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id), 2051 IXGBE_SB_IOSF_TARGET_KR_PHY, flx_val); 2052 if (rc) 2053 return rc; 2054 2055 ixgbe_restart_an_internal_phy_x550em(hw); 2056 2057 return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait); 2058 } 2059 2060 /** 2061 * ixgbe_fc_autoneg_sgmii_x550em_a - Enable flow control IEEE clause 37 2062 * @hw: pointer to hardware structure 2063 * 2064 * Enable flow control according to IEEE clause 37. 2065 */ 2066 static void ixgbe_fc_autoneg_sgmii_x550em_a(struct ixgbe_hw *hw) 2067 { 2068 s32 status = IXGBE_ERR_FC_NOT_NEGOTIATED; 2069 u32 info[FW_PHY_ACT_DATA_COUNT] = { 0 }; 2070 ixgbe_link_speed speed; 2071 bool link_up; 2072 2073 /* AN should have completed when the cable was plugged in. 2074 * Look for reasons to bail out. Bail out if: 2075 * - FC autoneg is disabled, or if 2076 * - link is not up. 2077 */ 2078 if (hw->fc.disable_fc_autoneg) 2079 goto out; 2080 2081 hw->mac.ops.check_link(hw, &speed, &link_up, false); 2082 if (!link_up) 2083 goto out; 2084 2085 /* Check if auto-negotiation has completed */ 2086 status = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_GET_LINK_INFO, &info); 2087 if (status || !(info[0] & FW_PHY_ACT_GET_LINK_INFO_AN_COMPLETE)) { 2088 status = IXGBE_ERR_FC_NOT_NEGOTIATED; 2089 goto out; 2090 } 2091 2092 /* Negotiate the flow control */ 2093 status = ixgbe_negotiate_fc(hw, info[0], info[0], 2094 FW_PHY_ACT_GET_LINK_INFO_FC_RX, 2095 FW_PHY_ACT_GET_LINK_INFO_FC_TX, 2096 FW_PHY_ACT_GET_LINK_INFO_LP_FC_RX, 2097 FW_PHY_ACT_GET_LINK_INFO_LP_FC_TX); 2098 2099 out: 2100 if (!status) { 2101 hw->fc.fc_was_autonegged = true; 2102 } else { 2103 hw->fc.fc_was_autonegged = false; 2104 hw->fc.current_mode = hw->fc.requested_mode; 2105 } 2106 } 2107 2108 /** ixgbe_init_mac_link_ops_X550em_a - Init mac link function pointers 2109 * @hw: pointer to hardware structure 2110 **/ 2111 static void ixgbe_init_mac_link_ops_X550em_a(struct ixgbe_hw *hw) 2112 { 2113 struct ixgbe_mac_info *mac = &hw->mac; 2114 2115 switch (mac->ops.get_media_type(hw)) { 2116 case ixgbe_media_type_fiber: 2117 mac->ops.setup_fc = NULL; 2118 mac->ops.fc_autoneg = ixgbe_fc_autoneg_fiber_x550em_a; 2119 break; 2120 case ixgbe_media_type_copper: 2121 if (hw->device_id != IXGBE_DEV_ID_X550EM_A_1G_T && 2122 hw->device_id != IXGBE_DEV_ID_X550EM_A_1G_T_L) { 2123 mac->ops.setup_link = ixgbe_setup_mac_link_t_X550em; 2124 break; 2125 } 2126 mac->ops.fc_autoneg = ixgbe_fc_autoneg_sgmii_x550em_a; 2127 mac->ops.setup_fc = ixgbe_fc_autoneg_fw; 2128 mac->ops.setup_link = ixgbe_setup_sgmii_fw; 2129 mac->ops.check_link = ixgbe_check_mac_link_generic; 2130 break; 2131 case ixgbe_media_type_backplane: 2132 mac->ops.fc_autoneg = ixgbe_fc_autoneg_backplane_x550em_a; 2133 mac->ops.setup_fc = ixgbe_setup_fc_backplane_x550em_a; 2134 break; 2135 default: 2136 break; 2137 } 2138 } 2139 2140 /** ixgbe_init_mac_link_ops_X550em - init mac link function pointers 2141 * @hw: pointer to hardware structure 2142 **/ 2143 static void ixgbe_init_mac_link_ops_X550em(struct ixgbe_hw *hw) 2144 { 2145 struct ixgbe_mac_info *mac = &hw->mac; 2146 2147 mac->ops.setup_fc = ixgbe_setup_fc_x550em; 2148 2149 switch (mac->ops.get_media_type(hw)) { 2150 case ixgbe_media_type_fiber: 2151 /* CS4227 does not support autoneg, so disable the laser control 2152 * functions for SFP+ fiber 2153 */ 2154 mac->ops.disable_tx_laser = NULL; 2155 mac->ops.enable_tx_laser = NULL; 2156 mac->ops.flap_tx_laser = NULL; 2157 mac->ops.setup_link = ixgbe_setup_mac_link_multispeed_fiber; 2158 switch (hw->device_id) { 2159 case IXGBE_DEV_ID_X550EM_A_SFP_N: 2160 mac->ops.setup_mac_link = ixgbe_setup_mac_link_sfp_n; 2161 break; 2162 case IXGBE_DEV_ID_X550EM_A_SFP: 2163 mac->ops.setup_mac_link = 2164 ixgbe_setup_mac_link_sfp_x550a; 2165 break; 2166 default: 2167 mac->ops.setup_mac_link = 2168 ixgbe_setup_mac_link_sfp_x550em; 2169 break; 2170 } 2171 mac->ops.set_rate_select_speed = 2172 ixgbe_set_soft_rate_select_speed; 2173 break; 2174 case ixgbe_media_type_copper: 2175 if (hw->device_id == IXGBE_DEV_ID_X550EM_X_1G_T) 2176 break; 2177 mac->ops.setup_link = ixgbe_setup_mac_link_t_X550em; 2178 mac->ops.setup_fc = ixgbe_setup_fc_generic; 2179 mac->ops.check_link = ixgbe_check_link_t_X550em; 2180 break; 2181 case ixgbe_media_type_backplane: 2182 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_SGMII || 2183 hw->device_id == IXGBE_DEV_ID_X550EM_A_SGMII_L) 2184 mac->ops.setup_link = ixgbe_setup_sgmii; 2185 break; 2186 default: 2187 break; 2188 } 2189 2190 /* Additional modification for X550em_a devices */ 2191 if (hw->mac.type == ixgbe_mac_x550em_a) 2192 ixgbe_init_mac_link_ops_X550em_a(hw); 2193 } 2194 2195 /** ixgbe_setup_sfp_modules_X550em - Setup SFP module 2196 * @hw: pointer to hardware structure 2197 */ 2198 static s32 ixgbe_setup_sfp_modules_X550em(struct ixgbe_hw *hw) 2199 { 2200 s32 status; 2201 bool linear; 2202 2203 /* Check if SFP module is supported */ 2204 status = ixgbe_supported_sfp_modules_X550em(hw, &linear); 2205 if (status) 2206 return status; 2207 2208 ixgbe_init_mac_link_ops_X550em(hw); 2209 hw->phy.ops.reset = NULL; 2210 2211 return 0; 2212 } 2213 2214 /** ixgbe_get_link_capabilities_x550em - Determines link capabilities 2215 * @hw: pointer to hardware structure 2216 * @speed: pointer to link speed 2217 * @autoneg: true when autoneg or autotry is enabled 2218 **/ 2219 static s32 ixgbe_get_link_capabilities_X550em(struct ixgbe_hw *hw, 2220 ixgbe_link_speed *speed, 2221 bool *autoneg) 2222 { 2223 if (hw->phy.type == ixgbe_phy_fw) { 2224 *autoneg = true; 2225 *speed = hw->phy.speeds_supported; 2226 return 0; 2227 } 2228 2229 /* SFP */ 2230 if (hw->phy.media_type == ixgbe_media_type_fiber) { 2231 /* CS4227 SFP must not enable auto-negotiation */ 2232 *autoneg = false; 2233 2234 if (hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 || 2235 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1) { 2236 *speed = IXGBE_LINK_SPEED_1GB_FULL; 2237 return 0; 2238 } 2239 2240 /* Link capabilities are based on SFP */ 2241 if (hw->phy.multispeed_fiber) 2242 *speed = IXGBE_LINK_SPEED_10GB_FULL | 2243 IXGBE_LINK_SPEED_1GB_FULL; 2244 else 2245 *speed = IXGBE_LINK_SPEED_10GB_FULL; 2246 } else { 2247 switch (hw->phy.type) { 2248 case ixgbe_phy_x550em_kx4: 2249 *speed = IXGBE_LINK_SPEED_1GB_FULL | 2250 IXGBE_LINK_SPEED_2_5GB_FULL | 2251 IXGBE_LINK_SPEED_10GB_FULL; 2252 break; 2253 case ixgbe_phy_x550em_xfi: 2254 *speed = IXGBE_LINK_SPEED_1GB_FULL | 2255 IXGBE_LINK_SPEED_10GB_FULL; 2256 break; 2257 case ixgbe_phy_ext_1g_t: 2258 case ixgbe_phy_sgmii: 2259 *speed = IXGBE_LINK_SPEED_1GB_FULL; 2260 break; 2261 case ixgbe_phy_x550em_kr: 2262 if (hw->mac.type == ixgbe_mac_x550em_a) { 2263 /* check different backplane modes */ 2264 if (hw->phy.nw_mng_if_sel & 2265 IXGBE_NW_MNG_IF_SEL_PHY_SPEED_2_5G) { 2266 *speed = IXGBE_LINK_SPEED_2_5GB_FULL; 2267 break; 2268 } else if (hw->device_id == 2269 IXGBE_DEV_ID_X550EM_A_KR_L) { 2270 *speed = IXGBE_LINK_SPEED_1GB_FULL; 2271 break; 2272 } 2273 } 2274 /* fall through */ 2275 default: 2276 *speed = IXGBE_LINK_SPEED_10GB_FULL | 2277 IXGBE_LINK_SPEED_1GB_FULL; 2278 break; 2279 } 2280 *autoneg = true; 2281 } 2282 return 0; 2283 } 2284 2285 /** 2286 * ixgbe_get_lasi_ext_t_x550em - Determime external Base T PHY interrupt cause 2287 * @hw: pointer to hardware structure 2288 * @lsc: pointer to boolean flag which indicates whether external Base T 2289 * PHY interrupt is lsc 2290 * 2291 * Determime if external Base T PHY interrupt cause is high temperature 2292 * failure alarm or link status change. 2293 * 2294 * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature 2295 * failure alarm, else return PHY access status. 2296 **/ 2297 static s32 ixgbe_get_lasi_ext_t_x550em(struct ixgbe_hw *hw, bool *lsc) 2298 { 2299 u32 status; 2300 u16 reg; 2301 2302 *lsc = false; 2303 2304 /* Vendor alarm triggered */ 2305 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG, 2306 MDIO_MMD_VEND1, 2307 ®); 2308 2309 if (status || !(reg & IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN)) 2310 return status; 2311 2312 /* Vendor Auto-Neg alarm triggered or Global alarm 1 triggered */ 2313 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_FLAG, 2314 MDIO_MMD_VEND1, 2315 ®); 2316 2317 if (status || !(reg & (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN | 2318 IXGBE_MDIO_GLOBAL_ALARM_1_INT))) 2319 return status; 2320 2321 /* Global alarm triggered */ 2322 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_ALARM_1, 2323 MDIO_MMD_VEND1, 2324 ®); 2325 2326 if (status) 2327 return status; 2328 2329 /* If high temperature failure, then return over temp error and exit */ 2330 if (reg & IXGBE_MDIO_GLOBAL_ALM_1_HI_TMP_FAIL) { 2331 /* power down the PHY in case the PHY FW didn't already */ 2332 ixgbe_set_copper_phy_power(hw, false); 2333 return IXGBE_ERR_OVERTEMP; 2334 } 2335 if (reg & IXGBE_MDIO_GLOBAL_ALM_1_DEV_FAULT) { 2336 /* device fault alarm triggered */ 2337 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_FAULT_MSG, 2338 MDIO_MMD_VEND1, 2339 ®); 2340 if (status) 2341 return status; 2342 2343 /* if device fault was due to high temp alarm handle and exit */ 2344 if (reg == IXGBE_MDIO_GLOBAL_FAULT_MSG_HI_TMP) { 2345 /* power down the PHY in case the PHY FW didn't */ 2346 ixgbe_set_copper_phy_power(hw, false); 2347 return IXGBE_ERR_OVERTEMP; 2348 } 2349 } 2350 2351 /* Vendor alarm 2 triggered */ 2352 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG, 2353 MDIO_MMD_AN, ®); 2354 2355 if (status || !(reg & IXGBE_MDIO_GLOBAL_STD_ALM2_INT)) 2356 return status; 2357 2358 /* link connect/disconnect event occurred */ 2359 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM2, 2360 MDIO_MMD_AN, ®); 2361 2362 if (status) 2363 return status; 2364 2365 /* Indicate LSC */ 2366 if (reg & IXGBE_MDIO_AUTO_NEG_VEN_LSC) 2367 *lsc = true; 2368 2369 return 0; 2370 } 2371 2372 /** 2373 * ixgbe_enable_lasi_ext_t_x550em - Enable external Base T PHY interrupts 2374 * @hw: pointer to hardware structure 2375 * 2376 * Enable link status change and temperature failure alarm for the external 2377 * Base T PHY 2378 * 2379 * Returns PHY access status 2380 **/ 2381 static s32 ixgbe_enable_lasi_ext_t_x550em(struct ixgbe_hw *hw) 2382 { 2383 u32 status; 2384 u16 reg; 2385 bool lsc; 2386 2387 /* Clear interrupt flags */ 2388 status = ixgbe_get_lasi_ext_t_x550em(hw, &lsc); 2389 2390 /* Enable link status change alarm */ 2391 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK, 2392 MDIO_MMD_AN, ®); 2393 if (status) 2394 return status; 2395 2396 reg |= IXGBE_MDIO_PMA_TX_VEN_LASI_INT_EN; 2397 2398 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK, 2399 MDIO_MMD_AN, reg); 2400 if (status) 2401 return status; 2402 2403 /* Enable high temperature failure and global fault alarms */ 2404 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK, 2405 MDIO_MMD_VEND1, 2406 ®); 2407 if (status) 2408 return status; 2409 2410 reg |= (IXGBE_MDIO_GLOBAL_INT_HI_TEMP_EN | 2411 IXGBE_MDIO_GLOBAL_INT_DEV_FAULT_EN); 2412 2413 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK, 2414 MDIO_MMD_VEND1, 2415 reg); 2416 if (status) 2417 return status; 2418 2419 /* Enable vendor Auto-Neg alarm and Global Interrupt Mask 1 alarm */ 2420 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK, 2421 MDIO_MMD_VEND1, 2422 ®); 2423 if (status) 2424 return status; 2425 2426 reg |= (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN | 2427 IXGBE_MDIO_GLOBAL_ALARM_1_INT); 2428 2429 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK, 2430 MDIO_MMD_VEND1, 2431 reg); 2432 if (status) 2433 return status; 2434 2435 /* Enable chip-wide vendor alarm */ 2436 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK, 2437 MDIO_MMD_VEND1, 2438 ®); 2439 if (status) 2440 return status; 2441 2442 reg |= IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN; 2443 2444 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK, 2445 MDIO_MMD_VEND1, 2446 reg); 2447 2448 return status; 2449 } 2450 2451 /** 2452 * ixgbe_handle_lasi_ext_t_x550em - Handle external Base T PHY interrupt 2453 * @hw: pointer to hardware structure 2454 * 2455 * Handle external Base T PHY interrupt. If high temperature 2456 * failure alarm then return error, else if link status change 2457 * then setup internal/external PHY link 2458 * 2459 * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature 2460 * failure alarm, else return PHY access status. 2461 **/ 2462 static s32 ixgbe_handle_lasi_ext_t_x550em(struct ixgbe_hw *hw) 2463 { 2464 struct ixgbe_phy_info *phy = &hw->phy; 2465 bool lsc; 2466 u32 status; 2467 2468 status = ixgbe_get_lasi_ext_t_x550em(hw, &lsc); 2469 if (status) 2470 return status; 2471 2472 if (lsc && phy->ops.setup_internal_link) 2473 return phy->ops.setup_internal_link(hw); 2474 2475 return 0; 2476 } 2477 2478 /** 2479 * ixgbe_setup_kr_speed_x550em - Configure the KR PHY for link speed. 2480 * @hw: pointer to hardware structure 2481 * @speed: link speed 2482 * 2483 * Configures the integrated KR PHY. 2484 **/ 2485 static s32 ixgbe_setup_kr_speed_x550em(struct ixgbe_hw *hw, 2486 ixgbe_link_speed speed) 2487 { 2488 s32 status; 2489 u32 reg_val; 2490 2491 status = hw->mac.ops.read_iosf_sb_reg(hw, 2492 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id), 2493 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val); 2494 if (status) 2495 return status; 2496 2497 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE; 2498 reg_val &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR | 2499 IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX); 2500 2501 /* Advertise 10G support. */ 2502 if (speed & IXGBE_LINK_SPEED_10GB_FULL) 2503 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR; 2504 2505 /* Advertise 1G support. */ 2506 if (speed & IXGBE_LINK_SPEED_1GB_FULL) 2507 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX; 2508 2509 status = hw->mac.ops.write_iosf_sb_reg(hw, 2510 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id), 2511 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val); 2512 2513 if (hw->mac.type == ixgbe_mac_x550em_a) { 2514 /* Set lane mode to KR auto negotiation */ 2515 status = hw->mac.ops.read_iosf_sb_reg(hw, 2516 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id), 2517 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val); 2518 2519 if (status) 2520 return status; 2521 2522 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_MASK; 2523 reg_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_AN; 2524 reg_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_AN_EN; 2525 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN37_EN; 2526 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SGMII_EN; 2527 2528 status = hw->mac.ops.write_iosf_sb_reg(hw, 2529 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id), 2530 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val); 2531 } 2532 2533 return ixgbe_restart_an_internal_phy_x550em(hw); 2534 } 2535 2536 /** 2537 * ixgbe_setup_kr_x550em - Configure the KR PHY 2538 * @hw: pointer to hardware structure 2539 **/ 2540 static s32 ixgbe_setup_kr_x550em(struct ixgbe_hw *hw) 2541 { 2542 /* leave link alone for 2.5G */ 2543 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_2_5GB_FULL) 2544 return 0; 2545 2546 if (ixgbe_check_reset_blocked(hw)) 2547 return 0; 2548 2549 return ixgbe_setup_kr_speed_x550em(hw, hw->phy.autoneg_advertised); 2550 } 2551 2552 /** ixgbe_ext_phy_t_x550em_get_link - Get ext phy link status 2553 * @hw: address of hardware structure 2554 * @link_up: address of boolean to indicate link status 2555 * 2556 * Returns error code if unable to get link status. 2557 **/ 2558 static s32 ixgbe_ext_phy_t_x550em_get_link(struct ixgbe_hw *hw, bool *link_up) 2559 { 2560 u32 ret; 2561 u16 autoneg_status; 2562 2563 *link_up = false; 2564 2565 /* read this twice back to back to indicate current status */ 2566 ret = hw->phy.ops.read_reg(hw, MDIO_STAT1, MDIO_MMD_AN, 2567 &autoneg_status); 2568 if (ret) 2569 return ret; 2570 2571 ret = hw->phy.ops.read_reg(hw, MDIO_STAT1, MDIO_MMD_AN, 2572 &autoneg_status); 2573 if (ret) 2574 return ret; 2575 2576 *link_up = !!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS); 2577 2578 return 0; 2579 } 2580 2581 /** ixgbe_setup_internal_phy_t_x550em - Configure KR PHY to X557 link 2582 * @hw: point to hardware structure 2583 * 2584 * Configures the link between the integrated KR PHY and the external X557 PHY 2585 * The driver will call this function when it gets a link status change 2586 * interrupt from the X557 PHY. This function configures the link speed 2587 * between the PHYs to match the link speed of the BASE-T link. 2588 * 2589 * A return of a non-zero value indicates an error, and the base driver should 2590 * not report link up. 2591 **/ 2592 static s32 ixgbe_setup_internal_phy_t_x550em(struct ixgbe_hw *hw) 2593 { 2594 ixgbe_link_speed force_speed; 2595 bool link_up; 2596 u32 status; 2597 u16 speed; 2598 2599 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper) 2600 return IXGBE_ERR_CONFIG; 2601 2602 if (hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE) { 2603 speed = IXGBE_LINK_SPEED_10GB_FULL | 2604 IXGBE_LINK_SPEED_1GB_FULL; 2605 return ixgbe_setup_kr_speed_x550em(hw, speed); 2606 } 2607 2608 /* If link is not up, then there is no setup necessary so return */ 2609 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up); 2610 if (status) 2611 return status; 2612 2613 if (!link_up) 2614 return 0; 2615 2616 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_STAT, 2617 MDIO_MMD_AN, 2618 &speed); 2619 if (status) 2620 return status; 2621 2622 /* If link is not still up, then no setup is necessary so return */ 2623 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up); 2624 if (status) 2625 return status; 2626 2627 if (!link_up) 2628 return 0; 2629 2630 /* clear everything but the speed and duplex bits */ 2631 speed &= IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_MASK; 2632 2633 switch (speed) { 2634 case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB_FULL: 2635 force_speed = IXGBE_LINK_SPEED_10GB_FULL; 2636 break; 2637 case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB_FULL: 2638 force_speed = IXGBE_LINK_SPEED_1GB_FULL; 2639 break; 2640 default: 2641 /* Internal PHY does not support anything else */ 2642 return IXGBE_ERR_INVALID_LINK_SETTINGS; 2643 } 2644 2645 return ixgbe_setup_ixfi_x550em(hw, &force_speed); 2646 } 2647 2648 /** ixgbe_reset_phy_t_X550em - Performs X557 PHY reset and enables LASI 2649 * @hw: pointer to hardware structure 2650 **/ 2651 static s32 ixgbe_reset_phy_t_X550em(struct ixgbe_hw *hw) 2652 { 2653 s32 status; 2654 2655 status = ixgbe_reset_phy_generic(hw); 2656 2657 if (status) 2658 return status; 2659 2660 /* Configure Link Status Alarm and Temperature Threshold interrupts */ 2661 return ixgbe_enable_lasi_ext_t_x550em(hw); 2662 } 2663 2664 /** 2665 * ixgbe_led_on_t_x550em - Turns on the software controllable LEDs. 2666 * @hw: pointer to hardware structure 2667 * @led_idx: led number to turn on 2668 **/ 2669 static s32 ixgbe_led_on_t_x550em(struct ixgbe_hw *hw, u32 led_idx) 2670 { 2671 u16 phy_data; 2672 2673 if (led_idx >= IXGBE_X557_MAX_LED_INDEX) 2674 return IXGBE_ERR_PARAM; 2675 2676 /* To turn on the LED, set mode to ON. */ 2677 hw->phy.ops.read_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx, 2678 MDIO_MMD_VEND1, &phy_data); 2679 phy_data |= IXGBE_X557_LED_MANUAL_SET_MASK; 2680 hw->phy.ops.write_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx, 2681 MDIO_MMD_VEND1, phy_data); 2682 2683 return 0; 2684 } 2685 2686 /** 2687 * ixgbe_led_off_t_x550em - Turns off the software controllable LEDs. 2688 * @hw: pointer to hardware structure 2689 * @led_idx: led number to turn off 2690 **/ 2691 static s32 ixgbe_led_off_t_x550em(struct ixgbe_hw *hw, u32 led_idx) 2692 { 2693 u16 phy_data; 2694 2695 if (led_idx >= IXGBE_X557_MAX_LED_INDEX) 2696 return IXGBE_ERR_PARAM; 2697 2698 /* To turn on the LED, set mode to ON. */ 2699 hw->phy.ops.read_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx, 2700 MDIO_MMD_VEND1, &phy_data); 2701 phy_data &= ~IXGBE_X557_LED_MANUAL_SET_MASK; 2702 hw->phy.ops.write_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx, 2703 MDIO_MMD_VEND1, phy_data); 2704 2705 return 0; 2706 } 2707 2708 /** 2709 * ixgbe_set_fw_drv_ver_x550 - Sends driver version to firmware 2710 * @hw: pointer to the HW structure 2711 * @maj: driver version major number 2712 * @min: driver version minor number 2713 * @build: driver version build number 2714 * @sub: driver version sub build number 2715 * @len: length of driver_ver string 2716 * @driver_ver: driver string 2717 * 2718 * Sends driver version number to firmware through the manageability 2719 * block. On success return 0 2720 * else returns IXGBE_ERR_SWFW_SYNC when encountering an error acquiring 2721 * semaphore or IXGBE_ERR_HOST_INTERFACE_COMMAND when command fails. 2722 **/ 2723 static s32 ixgbe_set_fw_drv_ver_x550(struct ixgbe_hw *hw, u8 maj, u8 min, 2724 u8 build, u8 sub, u16 len, 2725 const char *driver_ver) 2726 { 2727 struct ixgbe_hic_drv_info2 fw_cmd; 2728 s32 ret_val; 2729 int i; 2730 2731 if (!len || !driver_ver || (len > sizeof(fw_cmd.driver_string))) 2732 return IXGBE_ERR_INVALID_ARGUMENT; 2733 2734 fw_cmd.hdr.cmd = FW_CEM_CMD_DRIVER_INFO; 2735 fw_cmd.hdr.buf_len = FW_CEM_CMD_DRIVER_INFO_LEN + len; 2736 fw_cmd.hdr.cmd_or_resp.cmd_resv = FW_CEM_CMD_RESERVED; 2737 fw_cmd.port_num = (u8)hw->bus.func; 2738 fw_cmd.ver_maj = maj; 2739 fw_cmd.ver_min = min; 2740 fw_cmd.ver_build = build; 2741 fw_cmd.ver_sub = sub; 2742 fw_cmd.hdr.checksum = 0; 2743 memcpy(fw_cmd.driver_string, driver_ver, len); 2744 fw_cmd.hdr.checksum = ixgbe_calculate_checksum((u8 *)&fw_cmd, 2745 (FW_CEM_HDR_LEN + fw_cmd.hdr.buf_len)); 2746 2747 for (i = 0; i <= FW_CEM_MAX_RETRIES; i++) { 2748 ret_val = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd, 2749 sizeof(fw_cmd), 2750 IXGBE_HI_COMMAND_TIMEOUT, 2751 true); 2752 if (ret_val) 2753 continue; 2754 2755 if (fw_cmd.hdr.cmd_or_resp.ret_status != 2756 FW_CEM_RESP_STATUS_SUCCESS) 2757 return IXGBE_ERR_HOST_INTERFACE_COMMAND; 2758 return 0; 2759 } 2760 2761 return ret_val; 2762 } 2763 2764 /** ixgbe_get_lcd_x550em - Determine lowest common denominator 2765 * @hw: pointer to hardware structure 2766 * @lcd_speed: pointer to lowest common link speed 2767 * 2768 * Determine lowest common link speed with link partner. 2769 **/ 2770 static s32 ixgbe_get_lcd_t_x550em(struct ixgbe_hw *hw, 2771 ixgbe_link_speed *lcd_speed) 2772 { 2773 u16 an_lp_status; 2774 s32 status; 2775 u16 word = hw->eeprom.ctrl_word_3; 2776 2777 *lcd_speed = IXGBE_LINK_SPEED_UNKNOWN; 2778 2779 status = hw->phy.ops.read_reg(hw, IXGBE_AUTO_NEG_LP_STATUS, 2780 MDIO_MMD_AN, 2781 &an_lp_status); 2782 if (status) 2783 return status; 2784 2785 /* If link partner advertised 1G, return 1G */ 2786 if (an_lp_status & IXGBE_AUTO_NEG_LP_1000BASE_CAP) { 2787 *lcd_speed = IXGBE_LINK_SPEED_1GB_FULL; 2788 return status; 2789 } 2790 2791 /* If 10G disabled for LPLU via NVM D10GMP, then return no valid LCD */ 2792 if ((hw->bus.lan_id && (word & NVM_INIT_CTRL_3_D10GMP_PORT1)) || 2793 (word & NVM_INIT_CTRL_3_D10GMP_PORT0)) 2794 return status; 2795 2796 /* Link partner not capable of lower speeds, return 10G */ 2797 *lcd_speed = IXGBE_LINK_SPEED_10GB_FULL; 2798 return status; 2799 } 2800 2801 /** 2802 * ixgbe_setup_fc_x550em - Set up flow control 2803 * @hw: pointer to hardware structure 2804 */ 2805 static s32 ixgbe_setup_fc_x550em(struct ixgbe_hw *hw) 2806 { 2807 bool pause, asm_dir; 2808 u32 reg_val; 2809 s32 rc; 2810 2811 /* Validate the requested mode */ 2812 if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) { 2813 hw_err(hw, "ixgbe_fc_rx_pause not valid in strict IEEE mode\n"); 2814 return IXGBE_ERR_INVALID_LINK_SETTINGS; 2815 } 2816 2817 /* 10gig parts do not have a word in the EEPROM to determine the 2818 * default flow control setting, so we explicitly set it to full. 2819 */ 2820 if (hw->fc.requested_mode == ixgbe_fc_default) 2821 hw->fc.requested_mode = ixgbe_fc_full; 2822 2823 /* Determine PAUSE and ASM_DIR bits. */ 2824 switch (hw->fc.requested_mode) { 2825 case ixgbe_fc_none: 2826 pause = false; 2827 asm_dir = false; 2828 break; 2829 case ixgbe_fc_tx_pause: 2830 pause = false; 2831 asm_dir = true; 2832 break; 2833 case ixgbe_fc_rx_pause: 2834 /* Rx Flow control is enabled and Tx Flow control is 2835 * disabled by software override. Since there really 2836 * isn't a way to advertise that we are capable of RX 2837 * Pause ONLY, we will advertise that we support both 2838 * symmetric and asymmetric Rx PAUSE, as such we fall 2839 * through to the fc_full statement. Later, we will 2840 * disable the adapter's ability to send PAUSE frames. 2841 */ 2842 /* Fallthrough */ 2843 case ixgbe_fc_full: 2844 pause = true; 2845 asm_dir = true; 2846 break; 2847 default: 2848 hw_err(hw, "Flow control param set incorrectly\n"); 2849 return IXGBE_ERR_CONFIG; 2850 } 2851 2852 if (hw->device_id != IXGBE_DEV_ID_X550EM_X_KR && 2853 hw->device_id != IXGBE_DEV_ID_X550EM_A_KR && 2854 hw->device_id != IXGBE_DEV_ID_X550EM_A_KR_L) 2855 return 0; 2856 2857 rc = hw->mac.ops.read_iosf_sb_reg(hw, 2858 IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id), 2859 IXGBE_SB_IOSF_TARGET_KR_PHY, 2860 ®_val); 2861 if (rc) 2862 return rc; 2863 2864 reg_val &= ~(IXGBE_KRM_AN_CNTL_1_SYM_PAUSE | 2865 IXGBE_KRM_AN_CNTL_1_ASM_PAUSE); 2866 if (pause) 2867 reg_val |= IXGBE_KRM_AN_CNTL_1_SYM_PAUSE; 2868 if (asm_dir) 2869 reg_val |= IXGBE_KRM_AN_CNTL_1_ASM_PAUSE; 2870 rc = hw->mac.ops.write_iosf_sb_reg(hw, 2871 IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id), 2872 IXGBE_SB_IOSF_TARGET_KR_PHY, 2873 reg_val); 2874 2875 /* This device does not fully support AN. */ 2876 hw->fc.disable_fc_autoneg = true; 2877 2878 return rc; 2879 } 2880 2881 /** 2882 * ixgbe_fc_autoneg_backplane_x550em_a - Enable flow control IEEE clause 37 2883 * @hw: pointer to hardware structure 2884 **/ 2885 static void ixgbe_fc_autoneg_backplane_x550em_a(struct ixgbe_hw *hw) 2886 { 2887 u32 link_s1, lp_an_page_low, an_cntl_1; 2888 s32 status = IXGBE_ERR_FC_NOT_NEGOTIATED; 2889 ixgbe_link_speed speed; 2890 bool link_up; 2891 2892 /* AN should have completed when the cable was plugged in. 2893 * Look for reasons to bail out. Bail out if: 2894 * - FC autoneg is disabled, or if 2895 * - link is not up. 2896 */ 2897 if (hw->fc.disable_fc_autoneg) { 2898 hw_err(hw, "Flow control autoneg is disabled"); 2899 goto out; 2900 } 2901 2902 hw->mac.ops.check_link(hw, &speed, &link_up, false); 2903 if (!link_up) { 2904 hw_err(hw, "The link is down"); 2905 goto out; 2906 } 2907 2908 /* Check at auto-negotiation has completed */ 2909 status = hw->mac.ops.read_iosf_sb_reg(hw, 2910 IXGBE_KRM_LINK_S1(hw->bus.lan_id), 2911 IXGBE_SB_IOSF_TARGET_KR_PHY, &link_s1); 2912 2913 if (status || (link_s1 & IXGBE_KRM_LINK_S1_MAC_AN_COMPLETE) == 0) { 2914 hw_dbg(hw, "Auto-Negotiation did not complete\n"); 2915 status = IXGBE_ERR_FC_NOT_NEGOTIATED; 2916 goto out; 2917 } 2918 2919 /* Read the 10g AN autoc and LP ability registers and resolve 2920 * local flow control settings accordingly 2921 */ 2922 status = hw->mac.ops.read_iosf_sb_reg(hw, 2923 IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id), 2924 IXGBE_SB_IOSF_TARGET_KR_PHY, &an_cntl_1); 2925 2926 if (status) { 2927 hw_dbg(hw, "Auto-Negotiation did not complete\n"); 2928 goto out; 2929 } 2930 2931 status = hw->mac.ops.read_iosf_sb_reg(hw, 2932 IXGBE_KRM_LP_BASE_PAGE_HIGH(hw->bus.lan_id), 2933 IXGBE_SB_IOSF_TARGET_KR_PHY, &lp_an_page_low); 2934 2935 if (status) { 2936 hw_dbg(hw, "Auto-Negotiation did not complete\n"); 2937 goto out; 2938 } 2939 2940 status = ixgbe_negotiate_fc(hw, an_cntl_1, lp_an_page_low, 2941 IXGBE_KRM_AN_CNTL_1_SYM_PAUSE, 2942 IXGBE_KRM_AN_CNTL_1_ASM_PAUSE, 2943 IXGBE_KRM_LP_BASE_PAGE_HIGH_SYM_PAUSE, 2944 IXGBE_KRM_LP_BASE_PAGE_HIGH_ASM_PAUSE); 2945 2946 out: 2947 if (!status) { 2948 hw->fc.fc_was_autonegged = true; 2949 } else { 2950 hw->fc.fc_was_autonegged = false; 2951 hw->fc.current_mode = hw->fc.requested_mode; 2952 } 2953 } 2954 2955 /** 2956 * ixgbe_fc_autoneg_fiber_x550em_a - passthrough FC settings 2957 * @hw: pointer to hardware structure 2958 **/ 2959 static void ixgbe_fc_autoneg_fiber_x550em_a(struct ixgbe_hw *hw) 2960 { 2961 hw->fc.fc_was_autonegged = false; 2962 hw->fc.current_mode = hw->fc.requested_mode; 2963 } 2964 2965 /** ixgbe_enter_lplu_x550em - Transition to low power states 2966 * @hw: pointer to hardware structure 2967 * 2968 * Configures Low Power Link Up on transition to low power states 2969 * (from D0 to non-D0). Link is required to enter LPLU so avoid resetting 2970 * the X557 PHY immediately prior to entering LPLU. 2971 **/ 2972 static s32 ixgbe_enter_lplu_t_x550em(struct ixgbe_hw *hw) 2973 { 2974 u16 an_10g_cntl_reg, autoneg_reg, speed; 2975 s32 status; 2976 ixgbe_link_speed lcd_speed; 2977 u32 save_autoneg; 2978 bool link_up; 2979 2980 /* If blocked by MNG FW, then don't restart AN */ 2981 if (ixgbe_check_reset_blocked(hw)) 2982 return 0; 2983 2984 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up); 2985 if (status) 2986 return status; 2987 2988 status = hw->eeprom.ops.read(hw, NVM_INIT_CTRL_3, 2989 &hw->eeprom.ctrl_word_3); 2990 if (status) 2991 return status; 2992 2993 /* If link is down, LPLU disabled in NVM, WoL disabled, or 2994 * manageability disabled, then force link down by entering 2995 * low power mode. 2996 */ 2997 if (!link_up || !(hw->eeprom.ctrl_word_3 & NVM_INIT_CTRL_3_LPLU) || 2998 !(hw->wol_enabled || ixgbe_mng_present(hw))) 2999 return ixgbe_set_copper_phy_power(hw, false); 3000 3001 /* Determine LCD */ 3002 status = ixgbe_get_lcd_t_x550em(hw, &lcd_speed); 3003 if (status) 3004 return status; 3005 3006 /* If no valid LCD link speed, then force link down and exit. */ 3007 if (lcd_speed == IXGBE_LINK_SPEED_UNKNOWN) 3008 return ixgbe_set_copper_phy_power(hw, false); 3009 3010 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_STAT, 3011 MDIO_MMD_AN, 3012 &speed); 3013 if (status) 3014 return status; 3015 3016 /* If no link now, speed is invalid so take link down */ 3017 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up); 3018 if (status) 3019 return ixgbe_set_copper_phy_power(hw, false); 3020 3021 /* clear everything but the speed bits */ 3022 speed &= IXGBE_MDIO_AUTO_NEG_VEN_STAT_SPEED_MASK; 3023 3024 /* If current speed is already LCD, then exit. */ 3025 if (((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB) && 3026 (lcd_speed == IXGBE_LINK_SPEED_1GB_FULL)) || 3027 ((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB) && 3028 (lcd_speed == IXGBE_LINK_SPEED_10GB_FULL))) 3029 return status; 3030 3031 /* Clear AN completed indication */ 3032 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM, 3033 MDIO_MMD_AN, 3034 &autoneg_reg); 3035 if (status) 3036 return status; 3037 3038 status = hw->phy.ops.read_reg(hw, MDIO_AN_10GBT_CTRL, 3039 MDIO_MMD_AN, 3040 &an_10g_cntl_reg); 3041 if (status) 3042 return status; 3043 3044 status = hw->phy.ops.read_reg(hw, 3045 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG, 3046 MDIO_MMD_AN, 3047 &autoneg_reg); 3048 if (status) 3049 return status; 3050 3051 save_autoneg = hw->phy.autoneg_advertised; 3052 3053 /* Setup link at least common link speed */ 3054 status = hw->mac.ops.setup_link(hw, lcd_speed, false); 3055 3056 /* restore autoneg from before setting lplu speed */ 3057 hw->phy.autoneg_advertised = save_autoneg; 3058 3059 return status; 3060 } 3061 3062 /** 3063 * ixgbe_reset_phy_fw - Reset firmware-controlled PHYs 3064 * @hw: pointer to hardware structure 3065 */ 3066 static s32 ixgbe_reset_phy_fw(struct ixgbe_hw *hw) 3067 { 3068 u32 store[FW_PHY_ACT_DATA_COUNT] = { 0 }; 3069 s32 rc; 3070 3071 if (hw->phy.reset_disable || ixgbe_check_reset_blocked(hw)) 3072 return 0; 3073 3074 rc = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_PHY_SW_RESET, &store); 3075 if (rc) 3076 return rc; 3077 memset(store, 0, sizeof(store)); 3078 3079 rc = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_INIT_PHY, &store); 3080 if (rc) 3081 return rc; 3082 3083 return ixgbe_setup_fw_link(hw); 3084 } 3085 3086 /** 3087 * ixgbe_check_overtemp_fw - Check firmware-controlled PHYs for overtemp 3088 * @hw: pointer to hardware structure 3089 */ 3090 static s32 ixgbe_check_overtemp_fw(struct ixgbe_hw *hw) 3091 { 3092 u32 store[FW_PHY_ACT_DATA_COUNT] = { 0 }; 3093 s32 rc; 3094 3095 rc = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_GET_LINK_INFO, &store); 3096 if (rc) 3097 return rc; 3098 3099 if (store[0] & FW_PHY_ACT_GET_LINK_INFO_TEMP) { 3100 ixgbe_shutdown_fw_phy(hw); 3101 return IXGBE_ERR_OVERTEMP; 3102 } 3103 return 0; 3104 } 3105 3106 /** 3107 * ixgbe_read_mng_if_sel_x550em - Read NW_MNG_IF_SEL register 3108 * @hw: pointer to hardware structure 3109 * 3110 * Read NW_MNG_IF_SEL register and save field values. 3111 */ 3112 static void ixgbe_read_mng_if_sel_x550em(struct ixgbe_hw *hw) 3113 { 3114 /* Save NW management interface connected on board. This is used 3115 * to determine internal PHY mode. 3116 */ 3117 hw->phy.nw_mng_if_sel = IXGBE_READ_REG(hw, IXGBE_NW_MNG_IF_SEL); 3118 3119 /* If X552 (X550EM_a) and MDIO is connected to external PHY, then set 3120 * PHY address. This register field was has only been used for X552. 3121 */ 3122 if (hw->mac.type == ixgbe_mac_x550em_a && 3123 hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_MDIO_ACT) { 3124 hw->phy.mdio.prtad = (hw->phy.nw_mng_if_sel & 3125 IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD) >> 3126 IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD_SHIFT; 3127 } 3128 } 3129 3130 /** ixgbe_init_phy_ops_X550em - PHY/SFP specific init 3131 * @hw: pointer to hardware structure 3132 * 3133 * Initialize any function pointers that were not able to be 3134 * set during init_shared_code because the PHY/SFP type was 3135 * not known. Perform the SFP init if necessary. 3136 **/ 3137 static s32 ixgbe_init_phy_ops_X550em(struct ixgbe_hw *hw) 3138 { 3139 struct ixgbe_phy_info *phy = &hw->phy; 3140 s32 ret_val; 3141 3142 hw->mac.ops.set_lan_id(hw); 3143 3144 ixgbe_read_mng_if_sel_x550em(hw); 3145 3146 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) { 3147 phy->phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM; 3148 ixgbe_setup_mux_ctl(hw); 3149 } 3150 3151 /* Identify the PHY or SFP module */ 3152 ret_val = phy->ops.identify(hw); 3153 3154 /* Setup function pointers based on detected hardware */ 3155 ixgbe_init_mac_link_ops_X550em(hw); 3156 if (phy->sfp_type != ixgbe_sfp_type_unknown) 3157 phy->ops.reset = NULL; 3158 3159 /* Set functions pointers based on phy type */ 3160 switch (hw->phy.type) { 3161 case ixgbe_phy_x550em_kx4: 3162 phy->ops.setup_link = NULL; 3163 phy->ops.read_reg = ixgbe_read_phy_reg_x550em; 3164 phy->ops.write_reg = ixgbe_write_phy_reg_x550em; 3165 break; 3166 case ixgbe_phy_x550em_kr: 3167 phy->ops.setup_link = ixgbe_setup_kr_x550em; 3168 phy->ops.read_reg = ixgbe_read_phy_reg_x550em; 3169 phy->ops.write_reg = ixgbe_write_phy_reg_x550em; 3170 break; 3171 case ixgbe_phy_x550em_xfi: 3172 /* link is managed by HW */ 3173 phy->ops.setup_link = NULL; 3174 phy->ops.read_reg = ixgbe_read_phy_reg_x550em; 3175 phy->ops.write_reg = ixgbe_write_phy_reg_x550em; 3176 break; 3177 case ixgbe_phy_x550em_ext_t: 3178 /* Save NW management interface connected on board. This is used 3179 * to determine internal PHY mode 3180 */ 3181 phy->nw_mng_if_sel = IXGBE_READ_REG(hw, IXGBE_NW_MNG_IF_SEL); 3182 3183 /* If internal link mode is XFI, then setup iXFI internal link, 3184 * else setup KR now. 3185 */ 3186 phy->ops.setup_internal_link = 3187 ixgbe_setup_internal_phy_t_x550em; 3188 3189 /* setup SW LPLU only for first revision */ 3190 if (hw->mac.type == ixgbe_mac_X550EM_x && 3191 !(IXGBE_READ_REG(hw, IXGBE_FUSES0_GROUP(0)) & 3192 IXGBE_FUSES0_REV_MASK)) 3193 phy->ops.enter_lplu = ixgbe_enter_lplu_t_x550em; 3194 3195 phy->ops.handle_lasi = ixgbe_handle_lasi_ext_t_x550em; 3196 phy->ops.reset = ixgbe_reset_phy_t_X550em; 3197 break; 3198 case ixgbe_phy_sgmii: 3199 phy->ops.setup_link = NULL; 3200 break; 3201 case ixgbe_phy_fw: 3202 phy->ops.setup_link = ixgbe_setup_fw_link; 3203 phy->ops.reset = ixgbe_reset_phy_fw; 3204 break; 3205 case ixgbe_phy_ext_1g_t: 3206 phy->ops.setup_link = NULL; 3207 phy->ops.read_reg = NULL; 3208 phy->ops.write_reg = NULL; 3209 break; 3210 default: 3211 break; 3212 } 3213 3214 return ret_val; 3215 } 3216 3217 /** ixgbe_get_media_type_X550em - Get media type 3218 * @hw: pointer to hardware structure 3219 * 3220 * Returns the media type (fiber, copper, backplane) 3221 * 3222 */ 3223 static enum ixgbe_media_type ixgbe_get_media_type_X550em(struct ixgbe_hw *hw) 3224 { 3225 enum ixgbe_media_type media_type; 3226 3227 /* Detect if there is a copper PHY attached. */ 3228 switch (hw->device_id) { 3229 case IXGBE_DEV_ID_X550EM_A_SGMII: 3230 case IXGBE_DEV_ID_X550EM_A_SGMII_L: 3231 hw->phy.type = ixgbe_phy_sgmii; 3232 /* Fallthrough */ 3233 case IXGBE_DEV_ID_X550EM_X_KR: 3234 case IXGBE_DEV_ID_X550EM_X_KX4: 3235 case IXGBE_DEV_ID_X550EM_X_XFI: 3236 case IXGBE_DEV_ID_X550EM_A_KR: 3237 case IXGBE_DEV_ID_X550EM_A_KR_L: 3238 media_type = ixgbe_media_type_backplane; 3239 break; 3240 case IXGBE_DEV_ID_X550EM_X_SFP: 3241 case IXGBE_DEV_ID_X550EM_A_SFP: 3242 case IXGBE_DEV_ID_X550EM_A_SFP_N: 3243 media_type = ixgbe_media_type_fiber; 3244 break; 3245 case IXGBE_DEV_ID_X550EM_X_1G_T: 3246 case IXGBE_DEV_ID_X550EM_X_10G_T: 3247 case IXGBE_DEV_ID_X550EM_A_10G_T: 3248 case IXGBE_DEV_ID_X550EM_A_1G_T: 3249 case IXGBE_DEV_ID_X550EM_A_1G_T_L: 3250 media_type = ixgbe_media_type_copper; 3251 break; 3252 default: 3253 media_type = ixgbe_media_type_unknown; 3254 break; 3255 } 3256 return media_type; 3257 } 3258 3259 /** ixgbe_init_ext_t_x550em - Start (unstall) the external Base T PHY. 3260 ** @hw: pointer to hardware structure 3261 **/ 3262 static s32 ixgbe_init_ext_t_x550em(struct ixgbe_hw *hw) 3263 { 3264 s32 status; 3265 u16 reg; 3266 3267 status = hw->phy.ops.read_reg(hw, 3268 IXGBE_MDIO_TX_VENDOR_ALARMS_3, 3269 MDIO_MMD_PMAPMD, 3270 ®); 3271 if (status) 3272 return status; 3273 3274 /* If PHY FW reset completed bit is set then this is the first 3275 * SW instance after a power on so the PHY FW must be un-stalled. 3276 */ 3277 if (reg & IXGBE_MDIO_TX_VENDOR_ALARMS_3_RST_MASK) { 3278 status = hw->phy.ops.read_reg(hw, 3279 IXGBE_MDIO_GLOBAL_RES_PR_10, 3280 MDIO_MMD_VEND1, 3281 ®); 3282 if (status) 3283 return status; 3284 3285 reg &= ~IXGBE_MDIO_POWER_UP_STALL; 3286 3287 status = hw->phy.ops.write_reg(hw, 3288 IXGBE_MDIO_GLOBAL_RES_PR_10, 3289 MDIO_MMD_VEND1, 3290 reg); 3291 if (status) 3292 return status; 3293 } 3294 3295 return status; 3296 } 3297 3298 /** 3299 * ixgbe_set_mdio_speed - Set MDIO clock speed 3300 * @hw: pointer to hardware structure 3301 */ 3302 static void ixgbe_set_mdio_speed(struct ixgbe_hw *hw) 3303 { 3304 u32 hlreg0; 3305 3306 switch (hw->device_id) { 3307 case IXGBE_DEV_ID_X550EM_X_10G_T: 3308 case IXGBE_DEV_ID_X550EM_A_SGMII: 3309 case IXGBE_DEV_ID_X550EM_A_SGMII_L: 3310 case IXGBE_DEV_ID_X550EM_A_10G_T: 3311 case IXGBE_DEV_ID_X550EM_A_SFP: 3312 /* Config MDIO clock speed before the first MDIO PHY access */ 3313 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0); 3314 hlreg0 &= ~IXGBE_HLREG0_MDCSPD; 3315 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0); 3316 break; 3317 case IXGBE_DEV_ID_X550EM_A_1G_T: 3318 case IXGBE_DEV_ID_X550EM_A_1G_T_L: 3319 /* Select fast MDIO clock speed for these devices */ 3320 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0); 3321 hlreg0 |= IXGBE_HLREG0_MDCSPD; 3322 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0); 3323 break; 3324 default: 3325 break; 3326 } 3327 } 3328 3329 /** ixgbe_reset_hw_X550em - Perform hardware reset 3330 ** @hw: pointer to hardware structure 3331 ** 3332 ** Resets the hardware by resetting the transmit and receive units, masks 3333 ** and clears all interrupts, perform a PHY reset, and perform a link (MAC) 3334 ** reset. 3335 **/ 3336 static s32 ixgbe_reset_hw_X550em(struct ixgbe_hw *hw) 3337 { 3338 ixgbe_link_speed link_speed; 3339 s32 status; 3340 u32 ctrl = 0; 3341 u32 i; 3342 bool link_up = false; 3343 u32 swfw_mask = hw->phy.phy_semaphore_mask; 3344 3345 /* Call adapter stop to disable Tx/Rx and clear interrupts */ 3346 status = hw->mac.ops.stop_adapter(hw); 3347 if (status) 3348 return status; 3349 3350 /* flush pending Tx transactions */ 3351 ixgbe_clear_tx_pending(hw); 3352 3353 /* PHY ops must be identified and initialized prior to reset */ 3354 3355 /* Identify PHY and related function pointers */ 3356 status = hw->phy.ops.init(hw); 3357 3358 /* start the external PHY */ 3359 if (hw->phy.type == ixgbe_phy_x550em_ext_t) { 3360 status = ixgbe_init_ext_t_x550em(hw); 3361 if (status) 3362 return status; 3363 } 3364 3365 /* Setup SFP module if there is one present. */ 3366 if (hw->phy.sfp_setup_needed) { 3367 status = hw->mac.ops.setup_sfp(hw); 3368 hw->phy.sfp_setup_needed = false; 3369 } 3370 3371 /* Reset PHY */ 3372 if (!hw->phy.reset_disable && hw->phy.ops.reset) 3373 hw->phy.ops.reset(hw); 3374 3375 mac_reset_top: 3376 /* Issue global reset to the MAC. Needs to be SW reset if link is up. 3377 * If link reset is used when link is up, it might reset the PHY when 3378 * mng is using it. If link is down or the flag to force full link 3379 * reset is set, then perform link reset. 3380 */ 3381 ctrl = IXGBE_CTRL_LNK_RST; 3382 3383 if (!hw->force_full_reset) { 3384 hw->mac.ops.check_link(hw, &link_speed, &link_up, false); 3385 if (link_up) 3386 ctrl = IXGBE_CTRL_RST; 3387 } 3388 3389 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask); 3390 if (status) { 3391 hw_dbg(hw, "semaphore failed with %d", status); 3392 return IXGBE_ERR_SWFW_SYNC; 3393 } 3394 3395 ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL); 3396 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl); 3397 IXGBE_WRITE_FLUSH(hw); 3398 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 3399 usleep_range(1000, 1200); 3400 3401 /* Poll for reset bit to self-clear meaning reset is complete */ 3402 for (i = 0; i < 10; i++) { 3403 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL); 3404 if (!(ctrl & IXGBE_CTRL_RST_MASK)) 3405 break; 3406 udelay(1); 3407 } 3408 3409 if (ctrl & IXGBE_CTRL_RST_MASK) { 3410 status = IXGBE_ERR_RESET_FAILED; 3411 hw_dbg(hw, "Reset polling failed to complete.\n"); 3412 } 3413 3414 msleep(50); 3415 3416 /* Double resets are required for recovery from certain error 3417 * clear the multicast table. Also reset num_rar_entries to 128, 3418 * since we modify this value when programming the SAN MAC address. 3419 */ 3420 if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) { 3421 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED; 3422 goto mac_reset_top; 3423 } 3424 3425 /* Store the permanent mac address */ 3426 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr); 3427 3428 /* Store MAC address from RAR0, clear receive address registers, and 3429 * clear the multicast table. Also reset num_rar_entries to 128, 3430 * since we modify this value when programming the SAN MAC address. 3431 */ 3432 hw->mac.num_rar_entries = 128; 3433 hw->mac.ops.init_rx_addrs(hw); 3434 3435 ixgbe_set_mdio_speed(hw); 3436 3437 if (hw->device_id == IXGBE_DEV_ID_X550EM_X_SFP) 3438 ixgbe_setup_mux_ctl(hw); 3439 3440 return status; 3441 } 3442 3443 /** ixgbe_set_ethertype_anti_spoofing_X550 - Enable/Disable Ethertype 3444 * anti-spoofing 3445 * @hw: pointer to hardware structure 3446 * @enable: enable or disable switch for Ethertype anti-spoofing 3447 * @vf: Virtual Function pool - VF Pool to set for Ethertype anti-spoofing 3448 **/ 3449 static void ixgbe_set_ethertype_anti_spoofing_X550(struct ixgbe_hw *hw, 3450 bool enable, int vf) 3451 { 3452 int vf_target_reg = vf >> 3; 3453 int vf_target_shift = vf % 8 + IXGBE_SPOOF_ETHERTYPEAS_SHIFT; 3454 u32 pfvfspoof; 3455 3456 pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg)); 3457 if (enable) 3458 pfvfspoof |= BIT(vf_target_shift); 3459 else 3460 pfvfspoof &= ~BIT(vf_target_shift); 3461 3462 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof); 3463 } 3464 3465 /** ixgbe_set_source_address_pruning_X550 - Enable/Disbale src address pruning 3466 * @hw: pointer to hardware structure 3467 * @enable: enable or disable source address pruning 3468 * @pool: Rx pool to set source address pruning for 3469 **/ 3470 static void ixgbe_set_source_address_pruning_X550(struct ixgbe_hw *hw, 3471 bool enable, 3472 unsigned int pool) 3473 { 3474 u64 pfflp; 3475 3476 /* max rx pool is 63 */ 3477 if (pool > 63) 3478 return; 3479 3480 pfflp = (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPL); 3481 pfflp |= (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPH) << 32; 3482 3483 if (enable) 3484 pfflp |= (1ULL << pool); 3485 else 3486 pfflp &= ~(1ULL << pool); 3487 3488 IXGBE_WRITE_REG(hw, IXGBE_PFFLPL, (u32)pfflp); 3489 IXGBE_WRITE_REG(hw, IXGBE_PFFLPH, (u32)(pfflp >> 32)); 3490 } 3491 3492 /** 3493 * ixgbe_setup_fc_backplane_x550em_a - Set up flow control 3494 * @hw: pointer to hardware structure 3495 * 3496 * Called at init time to set up flow control. 3497 **/ 3498 static s32 ixgbe_setup_fc_backplane_x550em_a(struct ixgbe_hw *hw) 3499 { 3500 s32 status = 0; 3501 u32 an_cntl = 0; 3502 3503 /* Validate the requested mode */ 3504 if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) { 3505 hw_err(hw, "ixgbe_fc_rx_pause not valid in strict IEEE mode\n"); 3506 return IXGBE_ERR_INVALID_LINK_SETTINGS; 3507 } 3508 3509 if (hw->fc.requested_mode == ixgbe_fc_default) 3510 hw->fc.requested_mode = ixgbe_fc_full; 3511 3512 /* Set up the 1G and 10G flow control advertisement registers so the 3513 * HW will be able to do FC autoneg once the cable is plugged in. If 3514 * we link at 10G, the 1G advertisement is harmless and vice versa. 3515 */ 3516 status = hw->mac.ops.read_iosf_sb_reg(hw, 3517 IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id), 3518 IXGBE_SB_IOSF_TARGET_KR_PHY, &an_cntl); 3519 3520 if (status) { 3521 hw_dbg(hw, "Auto-Negotiation did not complete\n"); 3522 return status; 3523 } 3524 3525 /* The possible values of fc.requested_mode are: 3526 * 0: Flow control is completely disabled 3527 * 1: Rx flow control is enabled (we can receive pause frames, 3528 * but not send pause frames). 3529 * 2: Tx flow control is enabled (we can send pause frames but 3530 * we do not support receiving pause frames). 3531 * 3: Both Rx and Tx flow control (symmetric) are enabled. 3532 * other: Invalid. 3533 */ 3534 switch (hw->fc.requested_mode) { 3535 case ixgbe_fc_none: 3536 /* Flow control completely disabled by software override. */ 3537 an_cntl &= ~(IXGBE_KRM_AN_CNTL_1_SYM_PAUSE | 3538 IXGBE_KRM_AN_CNTL_1_ASM_PAUSE); 3539 break; 3540 case ixgbe_fc_tx_pause: 3541 /* Tx Flow control is enabled, and Rx Flow control is 3542 * disabled by software override. 3543 */ 3544 an_cntl |= IXGBE_KRM_AN_CNTL_1_ASM_PAUSE; 3545 an_cntl &= ~IXGBE_KRM_AN_CNTL_1_SYM_PAUSE; 3546 break; 3547 case ixgbe_fc_rx_pause: 3548 /* Rx Flow control is enabled and Tx Flow control is 3549 * disabled by software override. Since there really 3550 * isn't a way to advertise that we are capable of RX 3551 * Pause ONLY, we will advertise that we support both 3552 * symmetric and asymmetric Rx PAUSE, as such we fall 3553 * through to the fc_full statement. Later, we will 3554 * disable the adapter's ability to send PAUSE frames. 3555 */ 3556 case ixgbe_fc_full: 3557 /* Flow control (both Rx and Tx) is enabled by SW override. */ 3558 an_cntl |= IXGBE_KRM_AN_CNTL_1_SYM_PAUSE | 3559 IXGBE_KRM_AN_CNTL_1_ASM_PAUSE; 3560 break; 3561 default: 3562 hw_err(hw, "Flow control param set incorrectly\n"); 3563 return IXGBE_ERR_CONFIG; 3564 } 3565 3566 status = hw->mac.ops.write_iosf_sb_reg(hw, 3567 IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id), 3568 IXGBE_SB_IOSF_TARGET_KR_PHY, an_cntl); 3569 3570 /* Restart auto-negotiation. */ 3571 status = ixgbe_restart_an_internal_phy_x550em(hw); 3572 3573 return status; 3574 } 3575 3576 /** 3577 * ixgbe_set_mux - Set mux for port 1 access with CS4227 3578 * @hw: pointer to hardware structure 3579 * @state: set mux if 1, clear if 0 3580 */ 3581 static void ixgbe_set_mux(struct ixgbe_hw *hw, u8 state) 3582 { 3583 u32 esdp; 3584 3585 if (!hw->bus.lan_id) 3586 return; 3587 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); 3588 if (state) 3589 esdp |= IXGBE_ESDP_SDP1; 3590 else 3591 esdp &= ~IXGBE_ESDP_SDP1; 3592 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp); 3593 IXGBE_WRITE_FLUSH(hw); 3594 } 3595 3596 /** 3597 * ixgbe_acquire_swfw_sync_X550em - Acquire SWFW semaphore 3598 * @hw: pointer to hardware structure 3599 * @mask: Mask to specify which semaphore to acquire 3600 * 3601 * Acquires the SWFW semaphore and sets the I2C MUX 3602 */ 3603 static s32 ixgbe_acquire_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask) 3604 { 3605 s32 status; 3606 3607 status = ixgbe_acquire_swfw_sync_X540(hw, mask); 3608 if (status) 3609 return status; 3610 3611 if (mask & IXGBE_GSSR_I2C_MASK) 3612 ixgbe_set_mux(hw, 1); 3613 3614 return 0; 3615 } 3616 3617 /** 3618 * ixgbe_release_swfw_sync_X550em - Release SWFW semaphore 3619 * @hw: pointer to hardware structure 3620 * @mask: Mask to specify which semaphore to release 3621 * 3622 * Releases the SWFW semaphore and sets the I2C MUX 3623 */ 3624 static void ixgbe_release_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask) 3625 { 3626 if (mask & IXGBE_GSSR_I2C_MASK) 3627 ixgbe_set_mux(hw, 0); 3628 3629 ixgbe_release_swfw_sync_X540(hw, mask); 3630 } 3631 3632 /** 3633 * ixgbe_acquire_swfw_sync_x550em_a - Acquire SWFW semaphore 3634 * @hw: pointer to hardware structure 3635 * @mask: Mask to specify which semaphore to acquire 3636 * 3637 * Acquires the SWFW semaphore and get the shared PHY token as needed 3638 */ 3639 static s32 ixgbe_acquire_swfw_sync_x550em_a(struct ixgbe_hw *hw, u32 mask) 3640 { 3641 u32 hmask = mask & ~IXGBE_GSSR_TOKEN_SM; 3642 int retries = FW_PHY_TOKEN_RETRIES; 3643 s32 status; 3644 3645 while (--retries) { 3646 status = 0; 3647 if (hmask) 3648 status = ixgbe_acquire_swfw_sync_X540(hw, hmask); 3649 if (status) 3650 return status; 3651 if (!(mask & IXGBE_GSSR_TOKEN_SM)) 3652 return 0; 3653 3654 status = ixgbe_get_phy_token(hw); 3655 if (!status) 3656 return 0; 3657 if (hmask) 3658 ixgbe_release_swfw_sync_X540(hw, hmask); 3659 if (status != IXGBE_ERR_TOKEN_RETRY) 3660 return status; 3661 msleep(FW_PHY_TOKEN_DELAY); 3662 } 3663 3664 return status; 3665 } 3666 3667 /** 3668 * ixgbe_release_swfw_sync_x550em_a - Release SWFW semaphore 3669 * @hw: pointer to hardware structure 3670 * @mask: Mask to specify which semaphore to release 3671 * 3672 * Release the SWFW semaphore and puts the shared PHY token as needed 3673 */ 3674 static void ixgbe_release_swfw_sync_x550em_a(struct ixgbe_hw *hw, u32 mask) 3675 { 3676 u32 hmask = mask & ~IXGBE_GSSR_TOKEN_SM; 3677 3678 if (mask & IXGBE_GSSR_TOKEN_SM) 3679 ixgbe_put_phy_token(hw); 3680 3681 if (hmask) 3682 ixgbe_release_swfw_sync_X540(hw, hmask); 3683 } 3684 3685 /** 3686 * ixgbe_read_phy_reg_x550a - Reads specified PHY register 3687 * @hw: pointer to hardware structure 3688 * @reg_addr: 32 bit address of PHY register to read 3689 * @phy_data: Pointer to read data from PHY register 3690 * 3691 * Reads a value from a specified PHY register using the SWFW lock and PHY 3692 * Token. The PHY Token is needed since the MDIO is shared between to MAC 3693 * instances. 3694 */ 3695 static s32 ixgbe_read_phy_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr, 3696 u32 device_type, u16 *phy_data) 3697 { 3698 u32 mask = hw->phy.phy_semaphore_mask | IXGBE_GSSR_TOKEN_SM; 3699 s32 status; 3700 3701 if (hw->mac.ops.acquire_swfw_sync(hw, mask)) 3702 return IXGBE_ERR_SWFW_SYNC; 3703 3704 status = hw->phy.ops.read_reg_mdi(hw, reg_addr, device_type, phy_data); 3705 3706 hw->mac.ops.release_swfw_sync(hw, mask); 3707 3708 return status; 3709 } 3710 3711 /** 3712 * ixgbe_write_phy_reg_x550a - Writes specified PHY register 3713 * @hw: pointer to hardware structure 3714 * @reg_addr: 32 bit PHY register to write 3715 * @device_type: 5 bit device type 3716 * @phy_data: Data to write to the PHY register 3717 * 3718 * Writes a value to specified PHY register using the SWFW lock and PHY Token. 3719 * The PHY Token is needed since the MDIO is shared between to MAC instances. 3720 */ 3721 static s32 ixgbe_write_phy_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr, 3722 u32 device_type, u16 phy_data) 3723 { 3724 u32 mask = hw->phy.phy_semaphore_mask | IXGBE_GSSR_TOKEN_SM; 3725 s32 status; 3726 3727 if (hw->mac.ops.acquire_swfw_sync(hw, mask)) 3728 return IXGBE_ERR_SWFW_SYNC; 3729 3730 status = ixgbe_write_phy_reg_mdi(hw, reg_addr, device_type, phy_data); 3731 hw->mac.ops.release_swfw_sync(hw, mask); 3732 3733 return status; 3734 } 3735 3736 #define X550_COMMON_MAC \ 3737 .init_hw = &ixgbe_init_hw_generic, \ 3738 .start_hw = &ixgbe_start_hw_X540, \ 3739 .clear_hw_cntrs = &ixgbe_clear_hw_cntrs_generic, \ 3740 .enable_rx_dma = &ixgbe_enable_rx_dma_generic, \ 3741 .get_mac_addr = &ixgbe_get_mac_addr_generic, \ 3742 .get_device_caps = &ixgbe_get_device_caps_generic, \ 3743 .stop_adapter = &ixgbe_stop_adapter_generic, \ 3744 .set_lan_id = &ixgbe_set_lan_id_multi_port_pcie, \ 3745 .read_analog_reg8 = NULL, \ 3746 .write_analog_reg8 = NULL, \ 3747 .set_rxpba = &ixgbe_set_rxpba_generic, \ 3748 .check_link = &ixgbe_check_mac_link_generic, \ 3749 .blink_led_start = &ixgbe_blink_led_start_X540, \ 3750 .blink_led_stop = &ixgbe_blink_led_stop_X540, \ 3751 .set_rar = &ixgbe_set_rar_generic, \ 3752 .clear_rar = &ixgbe_clear_rar_generic, \ 3753 .set_vmdq = &ixgbe_set_vmdq_generic, \ 3754 .set_vmdq_san_mac = &ixgbe_set_vmdq_san_mac_generic, \ 3755 .clear_vmdq = &ixgbe_clear_vmdq_generic, \ 3756 .init_rx_addrs = &ixgbe_init_rx_addrs_generic, \ 3757 .update_mc_addr_list = &ixgbe_update_mc_addr_list_generic, \ 3758 .enable_mc = &ixgbe_enable_mc_generic, \ 3759 .disable_mc = &ixgbe_disable_mc_generic, \ 3760 .clear_vfta = &ixgbe_clear_vfta_generic, \ 3761 .set_vfta = &ixgbe_set_vfta_generic, \ 3762 .fc_enable = &ixgbe_fc_enable_generic, \ 3763 .set_fw_drv_ver = &ixgbe_set_fw_drv_ver_x550, \ 3764 .init_uta_tables = &ixgbe_init_uta_tables_generic, \ 3765 .set_mac_anti_spoofing = &ixgbe_set_mac_anti_spoofing, \ 3766 .set_vlan_anti_spoofing = &ixgbe_set_vlan_anti_spoofing, \ 3767 .set_source_address_pruning = \ 3768 &ixgbe_set_source_address_pruning_X550, \ 3769 .set_ethertype_anti_spoofing = \ 3770 &ixgbe_set_ethertype_anti_spoofing_X550, \ 3771 .disable_rx_buff = &ixgbe_disable_rx_buff_generic, \ 3772 .enable_rx_buff = &ixgbe_enable_rx_buff_generic, \ 3773 .get_thermal_sensor_data = NULL, \ 3774 .init_thermal_sensor_thresh = NULL, \ 3775 .enable_rx = &ixgbe_enable_rx_generic, \ 3776 .disable_rx = &ixgbe_disable_rx_x550, \ 3777 3778 static const struct ixgbe_mac_operations mac_ops_X550 = { 3779 X550_COMMON_MAC 3780 .led_on = ixgbe_led_on_generic, 3781 .led_off = ixgbe_led_off_generic, 3782 .init_led_link_act = ixgbe_init_led_link_act_generic, 3783 .reset_hw = &ixgbe_reset_hw_X540, 3784 .get_media_type = &ixgbe_get_media_type_X540, 3785 .get_san_mac_addr = &ixgbe_get_san_mac_addr_generic, 3786 .get_wwn_prefix = &ixgbe_get_wwn_prefix_generic, 3787 .setup_link = &ixgbe_setup_mac_link_X540, 3788 .get_link_capabilities = &ixgbe_get_copper_link_capabilities_generic, 3789 .get_bus_info = &ixgbe_get_bus_info_generic, 3790 .setup_sfp = NULL, 3791 .acquire_swfw_sync = &ixgbe_acquire_swfw_sync_X540, 3792 .release_swfw_sync = &ixgbe_release_swfw_sync_X540, 3793 .init_swfw_sync = &ixgbe_init_swfw_sync_X540, 3794 .prot_autoc_read = prot_autoc_read_generic, 3795 .prot_autoc_write = prot_autoc_write_generic, 3796 .setup_fc = ixgbe_setup_fc_generic, 3797 .fc_autoneg = ixgbe_fc_autoneg, 3798 }; 3799 3800 static const struct ixgbe_mac_operations mac_ops_X550EM_x = { 3801 X550_COMMON_MAC 3802 .led_on = ixgbe_led_on_t_x550em, 3803 .led_off = ixgbe_led_off_t_x550em, 3804 .init_led_link_act = ixgbe_init_led_link_act_generic, 3805 .reset_hw = &ixgbe_reset_hw_X550em, 3806 .get_media_type = &ixgbe_get_media_type_X550em, 3807 .get_san_mac_addr = NULL, 3808 .get_wwn_prefix = NULL, 3809 .setup_link = &ixgbe_setup_mac_link_X540, 3810 .get_link_capabilities = &ixgbe_get_link_capabilities_X550em, 3811 .get_bus_info = &ixgbe_get_bus_info_X550em, 3812 .setup_sfp = ixgbe_setup_sfp_modules_X550em, 3813 .acquire_swfw_sync = &ixgbe_acquire_swfw_sync_X550em, 3814 .release_swfw_sync = &ixgbe_release_swfw_sync_X550em, 3815 .init_swfw_sync = &ixgbe_init_swfw_sync_X540, 3816 .setup_fc = NULL, /* defined later */ 3817 .fc_autoneg = ixgbe_fc_autoneg, 3818 .read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550, 3819 .write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550, 3820 }; 3821 3822 static struct ixgbe_mac_operations mac_ops_x550em_a = { 3823 X550_COMMON_MAC 3824 .led_on = ixgbe_led_on_t_x550em, 3825 .led_off = ixgbe_led_off_t_x550em, 3826 .init_led_link_act = ixgbe_init_led_link_act_generic, 3827 .reset_hw = ixgbe_reset_hw_X550em, 3828 .get_media_type = ixgbe_get_media_type_X550em, 3829 .get_san_mac_addr = NULL, 3830 .get_wwn_prefix = NULL, 3831 .setup_link = &ixgbe_setup_mac_link_X540, 3832 .get_link_capabilities = ixgbe_get_link_capabilities_X550em, 3833 .get_bus_info = ixgbe_get_bus_info_X550em, 3834 .setup_sfp = ixgbe_setup_sfp_modules_X550em, 3835 .acquire_swfw_sync = ixgbe_acquire_swfw_sync_x550em_a, 3836 .release_swfw_sync = ixgbe_release_swfw_sync_x550em_a, 3837 .setup_fc = ixgbe_setup_fc_x550em, 3838 .fc_autoneg = ixgbe_fc_autoneg, 3839 .read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550a, 3840 .write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550a, 3841 }; 3842 3843 static struct ixgbe_mac_operations mac_ops_x550em_a_fw = { 3844 X550_COMMON_MAC 3845 .led_on = ixgbe_led_on_generic, 3846 .led_off = ixgbe_led_off_generic, 3847 .init_led_link_act = ixgbe_init_led_link_act_generic, 3848 .reset_hw = ixgbe_reset_hw_X550em, 3849 .get_media_type = ixgbe_get_media_type_X550em, 3850 .get_san_mac_addr = NULL, 3851 .get_wwn_prefix = NULL, 3852 .setup_link = NULL, /* defined later */ 3853 .get_link_capabilities = ixgbe_get_link_capabilities_X550em, 3854 .get_bus_info = ixgbe_get_bus_info_X550em, 3855 .setup_sfp = ixgbe_setup_sfp_modules_X550em, 3856 .acquire_swfw_sync = ixgbe_acquire_swfw_sync_x550em_a, 3857 .release_swfw_sync = ixgbe_release_swfw_sync_x550em_a, 3858 .setup_fc = ixgbe_setup_fc_x550em, 3859 .fc_autoneg = ixgbe_fc_autoneg, 3860 .read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550a, 3861 .write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550a, 3862 }; 3863 3864 #define X550_COMMON_EEP \ 3865 .read = &ixgbe_read_ee_hostif_X550, \ 3866 .read_buffer = &ixgbe_read_ee_hostif_buffer_X550, \ 3867 .write = &ixgbe_write_ee_hostif_X550, \ 3868 .write_buffer = &ixgbe_write_ee_hostif_buffer_X550, \ 3869 .validate_checksum = &ixgbe_validate_eeprom_checksum_X550, \ 3870 .update_checksum = &ixgbe_update_eeprom_checksum_X550, \ 3871 .calc_checksum = &ixgbe_calc_eeprom_checksum_X550, \ 3872 3873 static const struct ixgbe_eeprom_operations eeprom_ops_X550 = { 3874 X550_COMMON_EEP 3875 .init_params = &ixgbe_init_eeprom_params_X550, 3876 }; 3877 3878 static const struct ixgbe_eeprom_operations eeprom_ops_X550EM_x = { 3879 X550_COMMON_EEP 3880 .init_params = &ixgbe_init_eeprom_params_X540, 3881 }; 3882 3883 #define X550_COMMON_PHY \ 3884 .identify_sfp = &ixgbe_identify_module_generic, \ 3885 .reset = NULL, \ 3886 .setup_link_speed = &ixgbe_setup_phy_link_speed_generic, \ 3887 .read_i2c_byte = &ixgbe_read_i2c_byte_generic, \ 3888 .write_i2c_byte = &ixgbe_write_i2c_byte_generic, \ 3889 .read_i2c_sff8472 = &ixgbe_read_i2c_sff8472_generic, \ 3890 .read_i2c_eeprom = &ixgbe_read_i2c_eeprom_generic, \ 3891 .write_i2c_eeprom = &ixgbe_write_i2c_eeprom_generic, \ 3892 .setup_link = &ixgbe_setup_phy_link_generic, \ 3893 .set_phy_power = NULL, 3894 3895 static const struct ixgbe_phy_operations phy_ops_X550 = { 3896 X550_COMMON_PHY 3897 .check_overtemp = &ixgbe_tn_check_overtemp, 3898 .init = NULL, 3899 .identify = &ixgbe_identify_phy_generic, 3900 .read_reg = &ixgbe_read_phy_reg_generic, 3901 .write_reg = &ixgbe_write_phy_reg_generic, 3902 }; 3903 3904 static const struct ixgbe_phy_operations phy_ops_X550EM_x = { 3905 X550_COMMON_PHY 3906 .check_overtemp = &ixgbe_tn_check_overtemp, 3907 .init = &ixgbe_init_phy_ops_X550em, 3908 .identify = &ixgbe_identify_phy_x550em, 3909 .read_reg = &ixgbe_read_phy_reg_generic, 3910 .write_reg = &ixgbe_write_phy_reg_generic, 3911 }; 3912 3913 static const struct ixgbe_phy_operations phy_ops_x550em_x_fw = { 3914 X550_COMMON_PHY 3915 .check_overtemp = NULL, 3916 .init = ixgbe_init_phy_ops_X550em, 3917 .identify = ixgbe_identify_phy_x550em, 3918 .read_reg = NULL, 3919 .write_reg = NULL, 3920 .read_reg_mdi = NULL, 3921 .write_reg_mdi = NULL, 3922 }; 3923 3924 static const struct ixgbe_phy_operations phy_ops_x550em_a = { 3925 X550_COMMON_PHY 3926 .check_overtemp = &ixgbe_tn_check_overtemp, 3927 .init = &ixgbe_init_phy_ops_X550em, 3928 .identify = &ixgbe_identify_phy_x550em, 3929 .read_reg = &ixgbe_read_phy_reg_x550a, 3930 .write_reg = &ixgbe_write_phy_reg_x550a, 3931 .read_reg_mdi = &ixgbe_read_phy_reg_mdi, 3932 .write_reg_mdi = &ixgbe_write_phy_reg_mdi, 3933 }; 3934 3935 static const struct ixgbe_phy_operations phy_ops_x550em_a_fw = { 3936 X550_COMMON_PHY 3937 .check_overtemp = ixgbe_check_overtemp_fw, 3938 .init = ixgbe_init_phy_ops_X550em, 3939 .identify = ixgbe_identify_phy_fw, 3940 .read_reg = NULL, 3941 .write_reg = NULL, 3942 .read_reg_mdi = NULL, 3943 .write_reg_mdi = NULL, 3944 }; 3945 3946 static const struct ixgbe_link_operations link_ops_x550em_x = { 3947 .read_link = &ixgbe_read_i2c_combined_generic, 3948 .read_link_unlocked = &ixgbe_read_i2c_combined_generic_unlocked, 3949 .write_link = &ixgbe_write_i2c_combined_generic, 3950 .write_link_unlocked = &ixgbe_write_i2c_combined_generic_unlocked, 3951 }; 3952 3953 static const u32 ixgbe_mvals_X550[IXGBE_MVALS_IDX_LIMIT] = { 3954 IXGBE_MVALS_INIT(X550) 3955 }; 3956 3957 static const u32 ixgbe_mvals_X550EM_x[IXGBE_MVALS_IDX_LIMIT] = { 3958 IXGBE_MVALS_INIT(X550EM_x) 3959 }; 3960 3961 static const u32 ixgbe_mvals_x550em_a[IXGBE_MVALS_IDX_LIMIT] = { 3962 IXGBE_MVALS_INIT(X550EM_a) 3963 }; 3964 3965 const struct ixgbe_info ixgbe_X550_info = { 3966 .mac = ixgbe_mac_X550, 3967 .get_invariants = &ixgbe_get_invariants_X540, 3968 .mac_ops = &mac_ops_X550, 3969 .eeprom_ops = &eeprom_ops_X550, 3970 .phy_ops = &phy_ops_X550, 3971 .mbx_ops = &mbx_ops_generic, 3972 .mvals = ixgbe_mvals_X550, 3973 }; 3974 3975 const struct ixgbe_info ixgbe_X550EM_x_info = { 3976 .mac = ixgbe_mac_X550EM_x, 3977 .get_invariants = &ixgbe_get_invariants_X550_x, 3978 .mac_ops = &mac_ops_X550EM_x, 3979 .eeprom_ops = &eeprom_ops_X550EM_x, 3980 .phy_ops = &phy_ops_X550EM_x, 3981 .mbx_ops = &mbx_ops_generic, 3982 .mvals = ixgbe_mvals_X550EM_x, 3983 .link_ops = &link_ops_x550em_x, 3984 }; 3985 3986 const struct ixgbe_info ixgbe_x550em_x_fw_info = { 3987 .mac = ixgbe_mac_X550EM_x, 3988 .get_invariants = ixgbe_get_invariants_X550_x_fw, 3989 .mac_ops = &mac_ops_X550EM_x, 3990 .eeprom_ops = &eeprom_ops_X550EM_x, 3991 .phy_ops = &phy_ops_x550em_x_fw, 3992 .mbx_ops = &mbx_ops_generic, 3993 .mvals = ixgbe_mvals_X550EM_x, 3994 }; 3995 3996 const struct ixgbe_info ixgbe_x550em_a_info = { 3997 .mac = ixgbe_mac_x550em_a, 3998 .get_invariants = &ixgbe_get_invariants_X550_a, 3999 .mac_ops = &mac_ops_x550em_a, 4000 .eeprom_ops = &eeprom_ops_X550EM_x, 4001 .phy_ops = &phy_ops_x550em_a, 4002 .mbx_ops = &mbx_ops_generic, 4003 .mvals = ixgbe_mvals_x550em_a, 4004 }; 4005 4006 const struct ixgbe_info ixgbe_x550em_a_fw_info = { 4007 .mac = ixgbe_mac_x550em_a, 4008 .get_invariants = ixgbe_get_invariants_X550_a_fw, 4009 .mac_ops = &mac_ops_x550em_a_fw, 4010 .eeprom_ops = &eeprom_ops_X550EM_x, 4011 .phy_ops = &phy_ops_x550em_a_fw, 4012 .mbx_ops = &mbx_ops_generic, 4013 .mvals = ixgbe_mvals_x550em_a, 4014 }; 4015