1 /******************************************************************************* 2 * 3 * Intel 10 Gigabit PCI Express Linux driver 4 * Copyright(c) 1999 - 2016 Intel Corporation. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * The full GNU General Public License is included in this distribution in 16 * the file called "COPYING". 17 * 18 * Contact Information: 19 * Linux NICS <linux.nics@intel.com> 20 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 21 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 22 * 23 ******************************************************************************/ 24 #include "ixgbe_x540.h" 25 #include "ixgbe_type.h" 26 #include "ixgbe_common.h" 27 #include "ixgbe_phy.h" 28 29 static s32 ixgbe_setup_kr_speed_x550em(struct ixgbe_hw *, ixgbe_link_speed); 30 static s32 ixgbe_setup_fc_x550em(struct ixgbe_hw *); 31 static void ixgbe_fc_autoneg_fiber_x550em_a(struct ixgbe_hw *); 32 static void ixgbe_fc_autoneg_backplane_x550em_a(struct ixgbe_hw *); 33 static s32 ixgbe_setup_fc_backplane_x550em_a(struct ixgbe_hw *); 34 35 static s32 ixgbe_get_invariants_X550_x(struct ixgbe_hw *hw) 36 { 37 struct ixgbe_mac_info *mac = &hw->mac; 38 struct ixgbe_phy_info *phy = &hw->phy; 39 struct ixgbe_link_info *link = &hw->link; 40 41 /* Start with X540 invariants, since so simular */ 42 ixgbe_get_invariants_X540(hw); 43 44 if (mac->ops.get_media_type(hw) != ixgbe_media_type_copper) 45 phy->ops.set_phy_power = NULL; 46 47 link->addr = IXGBE_CS4227; 48 49 return 0; 50 } 51 52 static s32 ixgbe_get_invariants_X550_a(struct ixgbe_hw *hw) 53 { 54 struct ixgbe_mac_info *mac = &hw->mac; 55 struct ixgbe_phy_info *phy = &hw->phy; 56 57 /* Start with X540 invariants, since so simular */ 58 ixgbe_get_invariants_X540(hw); 59 60 if (mac->ops.get_media_type(hw) != ixgbe_media_type_copper) 61 phy->ops.set_phy_power = NULL; 62 63 return 0; 64 } 65 66 /** ixgbe_setup_mux_ctl - Setup ESDP register for I2C mux control 67 * @hw: pointer to hardware structure 68 **/ 69 static void ixgbe_setup_mux_ctl(struct ixgbe_hw *hw) 70 { 71 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); 72 73 if (hw->bus.lan_id) { 74 esdp &= ~(IXGBE_ESDP_SDP1_NATIVE | IXGBE_ESDP_SDP1); 75 esdp |= IXGBE_ESDP_SDP1_DIR; 76 } 77 esdp &= ~(IXGBE_ESDP_SDP0_NATIVE | IXGBE_ESDP_SDP0_DIR); 78 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp); 79 IXGBE_WRITE_FLUSH(hw); 80 } 81 82 /** 83 * ixgbe_read_cs4227 - Read CS4227 register 84 * @hw: pointer to hardware structure 85 * @reg: register number to write 86 * @value: pointer to receive value read 87 * 88 * Returns status code 89 */ 90 static s32 ixgbe_read_cs4227(struct ixgbe_hw *hw, u16 reg, u16 *value) 91 { 92 return hw->link.ops.read_link_unlocked(hw, hw->link.addr, reg, value); 93 } 94 95 /** 96 * ixgbe_write_cs4227 - Write CS4227 register 97 * @hw: pointer to hardware structure 98 * @reg: register number to write 99 * @value: value to write to register 100 * 101 * Returns status code 102 */ 103 static s32 ixgbe_write_cs4227(struct ixgbe_hw *hw, u16 reg, u16 value) 104 { 105 return hw->link.ops.write_link_unlocked(hw, hw->link.addr, reg, value); 106 } 107 108 /** 109 * ixgbe_read_pe - Read register from port expander 110 * @hw: pointer to hardware structure 111 * @reg: register number to read 112 * @value: pointer to receive read value 113 * 114 * Returns status code 115 */ 116 static s32 ixgbe_read_pe(struct ixgbe_hw *hw, u8 reg, u8 *value) 117 { 118 s32 status; 119 120 status = ixgbe_read_i2c_byte_generic_unlocked(hw, reg, IXGBE_PE, value); 121 if (status) 122 hw_err(hw, "port expander access failed with %d\n", status); 123 return status; 124 } 125 126 /** 127 * ixgbe_write_pe - Write register to port expander 128 * @hw: pointer to hardware structure 129 * @reg: register number to write 130 * @value: value to write 131 * 132 * Returns status code 133 */ 134 static s32 ixgbe_write_pe(struct ixgbe_hw *hw, u8 reg, u8 value) 135 { 136 s32 status; 137 138 status = ixgbe_write_i2c_byte_generic_unlocked(hw, reg, IXGBE_PE, 139 value); 140 if (status) 141 hw_err(hw, "port expander access failed with %d\n", status); 142 return status; 143 } 144 145 /** 146 * ixgbe_reset_cs4227 - Reset CS4227 using port expander 147 * @hw: pointer to hardware structure 148 * 149 * This function assumes that the caller has acquired the proper semaphore. 150 * Returns error code 151 */ 152 static s32 ixgbe_reset_cs4227(struct ixgbe_hw *hw) 153 { 154 s32 status; 155 u32 retry; 156 u16 value; 157 u8 reg; 158 159 /* Trigger hard reset. */ 160 status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, ®); 161 if (status) 162 return status; 163 reg |= IXGBE_PE_BIT1; 164 status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg); 165 if (status) 166 return status; 167 168 status = ixgbe_read_pe(hw, IXGBE_PE_CONFIG, ®); 169 if (status) 170 return status; 171 reg &= ~IXGBE_PE_BIT1; 172 status = ixgbe_write_pe(hw, IXGBE_PE_CONFIG, reg); 173 if (status) 174 return status; 175 176 status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, ®); 177 if (status) 178 return status; 179 reg &= ~IXGBE_PE_BIT1; 180 status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg); 181 if (status) 182 return status; 183 184 usleep_range(IXGBE_CS4227_RESET_HOLD, IXGBE_CS4227_RESET_HOLD + 100); 185 186 status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, ®); 187 if (status) 188 return status; 189 reg |= IXGBE_PE_BIT1; 190 status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg); 191 if (status) 192 return status; 193 194 /* Wait for the reset to complete. */ 195 msleep(IXGBE_CS4227_RESET_DELAY); 196 for (retry = 0; retry < IXGBE_CS4227_RETRIES; retry++) { 197 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_EFUSE_STATUS, 198 &value); 199 if (!status && value == IXGBE_CS4227_EEPROM_LOAD_OK) 200 break; 201 msleep(IXGBE_CS4227_CHECK_DELAY); 202 } 203 if (retry == IXGBE_CS4227_RETRIES) { 204 hw_err(hw, "CS4227 reset did not complete\n"); 205 return IXGBE_ERR_PHY; 206 } 207 208 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_EEPROM_STATUS, &value); 209 if (status || !(value & IXGBE_CS4227_EEPROM_LOAD_OK)) { 210 hw_err(hw, "CS4227 EEPROM did not load successfully\n"); 211 return IXGBE_ERR_PHY; 212 } 213 214 return 0; 215 } 216 217 /** 218 * ixgbe_check_cs4227 - Check CS4227 and reset as needed 219 * @hw: pointer to hardware structure 220 */ 221 static void ixgbe_check_cs4227(struct ixgbe_hw *hw) 222 { 223 u32 swfw_mask = hw->phy.phy_semaphore_mask; 224 s32 status; 225 u16 value; 226 u8 retry; 227 228 for (retry = 0; retry < IXGBE_CS4227_RETRIES; retry++) { 229 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask); 230 if (status) { 231 hw_err(hw, "semaphore failed with %d\n", status); 232 msleep(IXGBE_CS4227_CHECK_DELAY); 233 continue; 234 } 235 236 /* Get status of reset flow. */ 237 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_SCRATCH, &value); 238 if (!status && value == IXGBE_CS4227_RESET_COMPLETE) 239 goto out; 240 241 if (status || value != IXGBE_CS4227_RESET_PENDING) 242 break; 243 244 /* Reset is pending. Wait and check again. */ 245 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 246 msleep(IXGBE_CS4227_CHECK_DELAY); 247 } 248 /* If still pending, assume other instance failed. */ 249 if (retry == IXGBE_CS4227_RETRIES) { 250 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask); 251 if (status) { 252 hw_err(hw, "semaphore failed with %d\n", status); 253 return; 254 } 255 } 256 257 /* Reset the CS4227. */ 258 status = ixgbe_reset_cs4227(hw); 259 if (status) { 260 hw_err(hw, "CS4227 reset failed: %d", status); 261 goto out; 262 } 263 264 /* Reset takes so long, temporarily release semaphore in case the 265 * other driver instance is waiting for the reset indication. 266 */ 267 ixgbe_write_cs4227(hw, IXGBE_CS4227_SCRATCH, 268 IXGBE_CS4227_RESET_PENDING); 269 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 270 usleep_range(10000, 12000); 271 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask); 272 if (status) { 273 hw_err(hw, "semaphore failed with %d", status); 274 return; 275 } 276 277 /* Record completion for next time. */ 278 status = ixgbe_write_cs4227(hw, IXGBE_CS4227_SCRATCH, 279 IXGBE_CS4227_RESET_COMPLETE); 280 281 out: 282 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 283 msleep(hw->eeprom.semaphore_delay); 284 } 285 286 /** ixgbe_identify_phy_x550em - Get PHY type based on device id 287 * @hw: pointer to hardware structure 288 * 289 * Returns error code 290 */ 291 static s32 ixgbe_identify_phy_x550em(struct ixgbe_hw *hw) 292 { 293 switch (hw->device_id) { 294 case IXGBE_DEV_ID_X550EM_A_SFP: 295 if (hw->bus.lan_id) 296 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY1_SM; 297 else 298 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY0_SM; 299 return ixgbe_identify_module_generic(hw); 300 case IXGBE_DEV_ID_X550EM_X_SFP: 301 /* set up for CS4227 usage */ 302 hw->phy.phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM; 303 ixgbe_setup_mux_ctl(hw); 304 ixgbe_check_cs4227(hw); 305 /* Fallthrough */ 306 case IXGBE_DEV_ID_X550EM_A_SFP_N: 307 return ixgbe_identify_module_generic(hw); 308 case IXGBE_DEV_ID_X550EM_X_KX4: 309 hw->phy.type = ixgbe_phy_x550em_kx4; 310 break; 311 case IXGBE_DEV_ID_X550EM_X_KR: 312 case IXGBE_DEV_ID_X550EM_A_KR: 313 case IXGBE_DEV_ID_X550EM_A_KR_L: 314 hw->phy.type = ixgbe_phy_x550em_kr; 315 break; 316 case IXGBE_DEV_ID_X550EM_A_10G_T: 317 if (hw->bus.lan_id) 318 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY1_SM; 319 else 320 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY0_SM; 321 /* Fallthrough */ 322 case IXGBE_DEV_ID_X550EM_X_1G_T: 323 case IXGBE_DEV_ID_X550EM_X_10G_T: 324 return ixgbe_identify_phy_generic(hw); 325 default: 326 break; 327 } 328 return 0; 329 } 330 331 static s32 ixgbe_read_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr, 332 u32 device_type, u16 *phy_data) 333 { 334 return IXGBE_NOT_IMPLEMENTED; 335 } 336 337 static s32 ixgbe_write_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr, 338 u32 device_type, u16 phy_data) 339 { 340 return IXGBE_NOT_IMPLEMENTED; 341 } 342 343 /** 344 * ixgbe_read_i2c_combined_generic - Perform I2C read combined operation 345 * @hw: pointer to the hardware structure 346 * @addr: I2C bus address to read from 347 * @reg: I2C device register to read from 348 * @val: pointer to location to receive read value 349 * 350 * Returns an error code on error. 351 **/ 352 static s32 ixgbe_read_i2c_combined_generic(struct ixgbe_hw *hw, u8 addr, 353 u16 reg, u16 *val) 354 { 355 return ixgbe_read_i2c_combined_generic_int(hw, addr, reg, val, true); 356 } 357 358 /** 359 * ixgbe_read_i2c_combined_generic_unlocked - Do I2C read combined operation 360 * @hw: pointer to the hardware structure 361 * @addr: I2C bus address to read from 362 * @reg: I2C device register to read from 363 * @val: pointer to location to receive read value 364 * 365 * Returns an error code on error. 366 **/ 367 static s32 368 ixgbe_read_i2c_combined_generic_unlocked(struct ixgbe_hw *hw, u8 addr, 369 u16 reg, u16 *val) 370 { 371 return ixgbe_read_i2c_combined_generic_int(hw, addr, reg, val, false); 372 } 373 374 /** 375 * ixgbe_write_i2c_combined_generic - Perform I2C write combined operation 376 * @hw: pointer to the hardware structure 377 * @addr: I2C bus address to write to 378 * @reg: I2C device register to write to 379 * @val: value to write 380 * 381 * Returns an error code on error. 382 **/ 383 static s32 ixgbe_write_i2c_combined_generic(struct ixgbe_hw *hw, 384 u8 addr, u16 reg, u16 val) 385 { 386 return ixgbe_write_i2c_combined_generic_int(hw, addr, reg, val, true); 387 } 388 389 /** 390 * ixgbe_write_i2c_combined_generic_unlocked - Do I2C write combined operation 391 * @hw: pointer to the hardware structure 392 * @addr: I2C bus address to write to 393 * @reg: I2C device register to write to 394 * @val: value to write 395 * 396 * Returns an error code on error. 397 **/ 398 static s32 399 ixgbe_write_i2c_combined_generic_unlocked(struct ixgbe_hw *hw, 400 u8 addr, u16 reg, u16 val) 401 { 402 return ixgbe_write_i2c_combined_generic_int(hw, addr, reg, val, false); 403 } 404 405 /** ixgbe_init_eeprom_params_X550 - Initialize EEPROM params 406 * @hw: pointer to hardware structure 407 * 408 * Initializes the EEPROM parameters ixgbe_eeprom_info within the 409 * ixgbe_hw struct in order to set up EEPROM access. 410 **/ 411 static s32 ixgbe_init_eeprom_params_X550(struct ixgbe_hw *hw) 412 { 413 struct ixgbe_eeprom_info *eeprom = &hw->eeprom; 414 u32 eec; 415 u16 eeprom_size; 416 417 if (eeprom->type == ixgbe_eeprom_uninitialized) { 418 eeprom->semaphore_delay = 10; 419 eeprom->type = ixgbe_flash; 420 421 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw)); 422 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >> 423 IXGBE_EEC_SIZE_SHIFT); 424 eeprom->word_size = BIT(eeprom_size + 425 IXGBE_EEPROM_WORD_SIZE_SHIFT); 426 427 hw_dbg(hw, "Eeprom params: type = %d, size = %d\n", 428 eeprom->type, eeprom->word_size); 429 } 430 431 return 0; 432 } 433 434 /** 435 * ixgbe_iosf_wait - Wait for IOSF command completion 436 * @hw: pointer to hardware structure 437 * @ctrl: pointer to location to receive final IOSF control value 438 * 439 * Return: failing status on timeout 440 * 441 * Note: ctrl can be NULL if the IOSF control register value is not needed 442 */ 443 static s32 ixgbe_iosf_wait(struct ixgbe_hw *hw, u32 *ctrl) 444 { 445 u32 i, command; 446 447 /* Check every 10 usec to see if the address cycle completed. 448 * The SB IOSF BUSY bit will clear when the operation is 449 * complete. 450 */ 451 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { 452 command = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL); 453 if (!(command & IXGBE_SB_IOSF_CTRL_BUSY)) 454 break; 455 udelay(10); 456 } 457 if (ctrl) 458 *ctrl = command; 459 if (i == IXGBE_MDIO_COMMAND_TIMEOUT) { 460 hw_dbg(hw, "IOSF wait timed out\n"); 461 return IXGBE_ERR_PHY; 462 } 463 464 return 0; 465 } 466 467 /** ixgbe_read_iosf_sb_reg_x550 - Writes a value to specified register of the 468 * IOSF device 469 * @hw: pointer to hardware structure 470 * @reg_addr: 32 bit PHY register to write 471 * @device_type: 3 bit device type 472 * @phy_data: Pointer to read data from the register 473 **/ 474 static s32 ixgbe_read_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr, 475 u32 device_type, u32 *data) 476 { 477 u32 gssr = IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_PHY0_SM; 478 u32 command, error; 479 s32 ret; 480 481 ret = hw->mac.ops.acquire_swfw_sync(hw, gssr); 482 if (ret) 483 return ret; 484 485 ret = ixgbe_iosf_wait(hw, NULL); 486 if (ret) 487 goto out; 488 489 command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) | 490 (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT)); 491 492 /* Write IOSF control register */ 493 IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command); 494 495 ret = ixgbe_iosf_wait(hw, &command); 496 497 if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) { 498 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >> 499 IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT; 500 hw_dbg(hw, "Failed to read, error %x\n", error); 501 return IXGBE_ERR_PHY; 502 } 503 504 if (!ret) 505 *data = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA); 506 507 out: 508 hw->mac.ops.release_swfw_sync(hw, gssr); 509 return ret; 510 } 511 512 /** 513 * ixgbe_get_phy_token - Get the token for shared PHY access 514 * @hw: Pointer to hardware structure 515 */ 516 static s32 ixgbe_get_phy_token(struct ixgbe_hw *hw) 517 { 518 struct ixgbe_hic_phy_token_req token_cmd; 519 s32 status; 520 521 token_cmd.hdr.cmd = FW_PHY_TOKEN_REQ_CMD; 522 token_cmd.hdr.buf_len = FW_PHY_TOKEN_REQ_LEN; 523 token_cmd.hdr.cmd_or_resp.cmd_resv = 0; 524 token_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM; 525 token_cmd.port_number = hw->bus.lan_id; 526 token_cmd.command_type = FW_PHY_TOKEN_REQ; 527 token_cmd.pad = 0; 528 status = ixgbe_host_interface_command(hw, &token_cmd, sizeof(token_cmd), 529 IXGBE_HI_COMMAND_TIMEOUT, 530 true); 531 if (status) 532 return status; 533 if (token_cmd.hdr.cmd_or_resp.ret_status == FW_PHY_TOKEN_OK) 534 return 0; 535 if (token_cmd.hdr.cmd_or_resp.ret_status != FW_PHY_TOKEN_RETRY) 536 return IXGBE_ERR_FW_RESP_INVALID; 537 538 return IXGBE_ERR_TOKEN_RETRY; 539 } 540 541 /** 542 * ixgbe_put_phy_token - Put the token for shared PHY access 543 * @hw: Pointer to hardware structure 544 */ 545 static s32 ixgbe_put_phy_token(struct ixgbe_hw *hw) 546 { 547 struct ixgbe_hic_phy_token_req token_cmd; 548 s32 status; 549 550 token_cmd.hdr.cmd = FW_PHY_TOKEN_REQ_CMD; 551 token_cmd.hdr.buf_len = FW_PHY_TOKEN_REQ_LEN; 552 token_cmd.hdr.cmd_or_resp.cmd_resv = 0; 553 token_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM; 554 token_cmd.port_number = hw->bus.lan_id; 555 token_cmd.command_type = FW_PHY_TOKEN_REL; 556 token_cmd.pad = 0; 557 status = ixgbe_host_interface_command(hw, &token_cmd, sizeof(token_cmd), 558 IXGBE_HI_COMMAND_TIMEOUT, 559 true); 560 if (status) 561 return status; 562 if (token_cmd.hdr.cmd_or_resp.ret_status == FW_PHY_TOKEN_OK) 563 return 0; 564 return IXGBE_ERR_FW_RESP_INVALID; 565 } 566 567 /** 568 * ixgbe_write_iosf_sb_reg_x550a - Write to IOSF PHY register 569 * @hw: pointer to hardware structure 570 * @reg_addr: 32 bit PHY register to write 571 * @device_type: 3 bit device type 572 * @data: Data to write to the register 573 **/ 574 static s32 ixgbe_write_iosf_sb_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr, 575 __always_unused u32 device_type, 576 u32 data) 577 { 578 struct ixgbe_hic_internal_phy_req write_cmd; 579 580 memset(&write_cmd, 0, sizeof(write_cmd)); 581 write_cmd.hdr.cmd = FW_INT_PHY_REQ_CMD; 582 write_cmd.hdr.buf_len = FW_INT_PHY_REQ_LEN; 583 write_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM; 584 write_cmd.port_number = hw->bus.lan_id; 585 write_cmd.command_type = FW_INT_PHY_REQ_WRITE; 586 write_cmd.address = cpu_to_be16(reg_addr); 587 write_cmd.write_data = cpu_to_be32(data); 588 589 return ixgbe_host_interface_command(hw, &write_cmd, sizeof(write_cmd), 590 IXGBE_HI_COMMAND_TIMEOUT, false); 591 } 592 593 /** 594 * ixgbe_read_iosf_sb_reg_x550a - Read from IOSF PHY register 595 * @hw: pointer to hardware structure 596 * @reg_addr: 32 bit PHY register to write 597 * @device_type: 3 bit device type 598 * @data: Pointer to read data from the register 599 **/ 600 static s32 ixgbe_read_iosf_sb_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr, 601 __always_unused u32 device_type, 602 u32 *data) 603 { 604 union { 605 struct ixgbe_hic_internal_phy_req cmd; 606 struct ixgbe_hic_internal_phy_resp rsp; 607 } hic; 608 s32 status; 609 610 memset(&hic, 0, sizeof(hic)); 611 hic.cmd.hdr.cmd = FW_INT_PHY_REQ_CMD; 612 hic.cmd.hdr.buf_len = FW_INT_PHY_REQ_LEN; 613 hic.cmd.hdr.checksum = FW_DEFAULT_CHECKSUM; 614 hic.cmd.port_number = hw->bus.lan_id; 615 hic.cmd.command_type = FW_INT_PHY_REQ_READ; 616 hic.cmd.address = cpu_to_be16(reg_addr); 617 618 status = ixgbe_host_interface_command(hw, &hic.cmd, sizeof(hic.cmd), 619 IXGBE_HI_COMMAND_TIMEOUT, true); 620 621 /* Extract the register value from the response. */ 622 *data = be32_to_cpu(hic.rsp.read_data); 623 624 return status; 625 } 626 627 /** ixgbe_read_ee_hostif_data_X550 - Read EEPROM word using a host interface 628 * command assuming that the semaphore is already obtained. 629 * @hw: pointer to hardware structure 630 * @offset: offset of word in the EEPROM to read 631 * @data: word read from the EEPROM 632 * 633 * Reads a 16 bit word from the EEPROM using the hostif. 634 **/ 635 static s32 ixgbe_read_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset, 636 u16 *data) 637 { 638 s32 status; 639 struct ixgbe_hic_read_shadow_ram buffer; 640 641 buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD; 642 buffer.hdr.req.buf_lenh = 0; 643 buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN; 644 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM; 645 646 /* convert offset from words to bytes */ 647 buffer.address = cpu_to_be32(offset * 2); 648 /* one word */ 649 buffer.length = cpu_to_be16(sizeof(u16)); 650 651 status = ixgbe_host_interface_command(hw, &buffer, sizeof(buffer), 652 IXGBE_HI_COMMAND_TIMEOUT, false); 653 if (status) 654 return status; 655 656 *data = (u16)IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG, 657 FW_NVM_DATA_OFFSET); 658 659 return 0; 660 } 661 662 /** ixgbe_read_ee_hostif_buffer_X550- Read EEPROM word(s) using hostif 663 * @hw: pointer to hardware structure 664 * @offset: offset of word in the EEPROM to read 665 * @words: number of words 666 * @data: word(s) read from the EEPROM 667 * 668 * Reads a 16 bit word(s) from the EEPROM using the hostif. 669 **/ 670 static s32 ixgbe_read_ee_hostif_buffer_X550(struct ixgbe_hw *hw, 671 u16 offset, u16 words, u16 *data) 672 { 673 struct ixgbe_hic_read_shadow_ram buffer; 674 u32 current_word = 0; 675 u16 words_to_read; 676 s32 status; 677 u32 i; 678 679 /* Take semaphore for the entire operation. */ 680 status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 681 if (status) { 682 hw_dbg(hw, "EEPROM read buffer - semaphore failed\n"); 683 return status; 684 } 685 686 while (words) { 687 if (words > FW_MAX_READ_BUFFER_SIZE / 2) 688 words_to_read = FW_MAX_READ_BUFFER_SIZE / 2; 689 else 690 words_to_read = words; 691 692 buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD; 693 buffer.hdr.req.buf_lenh = 0; 694 buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN; 695 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM; 696 697 /* convert offset from words to bytes */ 698 buffer.address = cpu_to_be32((offset + current_word) * 2); 699 buffer.length = cpu_to_be16(words_to_read * 2); 700 701 status = ixgbe_host_interface_command(hw, &buffer, 702 sizeof(buffer), 703 IXGBE_HI_COMMAND_TIMEOUT, 704 false); 705 if (status) { 706 hw_dbg(hw, "Host interface command failed\n"); 707 goto out; 708 } 709 710 for (i = 0; i < words_to_read; i++) { 711 u32 reg = IXGBE_FLEX_MNG + (FW_NVM_DATA_OFFSET << 2) + 712 2 * i; 713 u32 value = IXGBE_READ_REG(hw, reg); 714 715 data[current_word] = (u16)(value & 0xffff); 716 current_word++; 717 i++; 718 if (i < words_to_read) { 719 value >>= 16; 720 data[current_word] = (u16)(value & 0xffff); 721 current_word++; 722 } 723 } 724 words -= words_to_read; 725 } 726 727 out: 728 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 729 return status; 730 } 731 732 /** ixgbe_checksum_ptr_x550 - Checksum one pointer region 733 * @hw: pointer to hardware structure 734 * @ptr: pointer offset in eeprom 735 * @size: size of section pointed by ptr, if 0 first word will be used as size 736 * @csum: address of checksum to update 737 * 738 * Returns error status for any failure 739 **/ 740 static s32 ixgbe_checksum_ptr_x550(struct ixgbe_hw *hw, u16 ptr, 741 u16 size, u16 *csum, u16 *buffer, 742 u32 buffer_size) 743 { 744 u16 buf[256]; 745 s32 status; 746 u16 length, bufsz, i, start; 747 u16 *local_buffer; 748 749 bufsz = sizeof(buf) / sizeof(buf[0]); 750 751 /* Read a chunk at the pointer location */ 752 if (!buffer) { 753 status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr, bufsz, buf); 754 if (status) { 755 hw_dbg(hw, "Failed to read EEPROM image\n"); 756 return status; 757 } 758 local_buffer = buf; 759 } else { 760 if (buffer_size < ptr) 761 return IXGBE_ERR_PARAM; 762 local_buffer = &buffer[ptr]; 763 } 764 765 if (size) { 766 start = 0; 767 length = size; 768 } else { 769 start = 1; 770 length = local_buffer[0]; 771 772 /* Skip pointer section if length is invalid. */ 773 if (length == 0xFFFF || length == 0 || 774 (ptr + length) >= hw->eeprom.word_size) 775 return 0; 776 } 777 778 if (buffer && ((u32)start + (u32)length > buffer_size)) 779 return IXGBE_ERR_PARAM; 780 781 for (i = start; length; i++, length--) { 782 if (i == bufsz && !buffer) { 783 ptr += bufsz; 784 i = 0; 785 if (length < bufsz) 786 bufsz = length; 787 788 /* Read a chunk at the pointer location */ 789 status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr, 790 bufsz, buf); 791 if (status) { 792 hw_dbg(hw, "Failed to read EEPROM image\n"); 793 return status; 794 } 795 } 796 *csum += local_buffer[i]; 797 } 798 return 0; 799 } 800 801 /** ixgbe_calc_checksum_X550 - Calculates and returns the checksum 802 * @hw: pointer to hardware structure 803 * @buffer: pointer to buffer containing calculated checksum 804 * @buffer_size: size of buffer 805 * 806 * Returns a negative error code on error, or the 16-bit checksum 807 **/ 808 static s32 ixgbe_calc_checksum_X550(struct ixgbe_hw *hw, u16 *buffer, 809 u32 buffer_size) 810 { 811 u16 eeprom_ptrs[IXGBE_EEPROM_LAST_WORD + 1]; 812 u16 *local_buffer; 813 s32 status; 814 u16 checksum = 0; 815 u16 pointer, i, size; 816 817 hw->eeprom.ops.init_params(hw); 818 819 if (!buffer) { 820 /* Read pointer area */ 821 status = ixgbe_read_ee_hostif_buffer_X550(hw, 0, 822 IXGBE_EEPROM_LAST_WORD + 1, 823 eeprom_ptrs); 824 if (status) { 825 hw_dbg(hw, "Failed to read EEPROM image\n"); 826 return status; 827 } 828 local_buffer = eeprom_ptrs; 829 } else { 830 if (buffer_size < IXGBE_EEPROM_LAST_WORD) 831 return IXGBE_ERR_PARAM; 832 local_buffer = buffer; 833 } 834 835 /* For X550 hardware include 0x0-0x41 in the checksum, skip the 836 * checksum word itself 837 */ 838 for (i = 0; i <= IXGBE_EEPROM_LAST_WORD; i++) 839 if (i != IXGBE_EEPROM_CHECKSUM) 840 checksum += local_buffer[i]; 841 842 /* Include all data from pointers 0x3, 0x6-0xE. This excludes the 843 * FW, PHY module, and PCIe Expansion/Option ROM pointers. 844 */ 845 for (i = IXGBE_PCIE_ANALOG_PTR_X550; i < IXGBE_FW_PTR; i++) { 846 if (i == IXGBE_PHY_PTR || i == IXGBE_OPTION_ROM_PTR) 847 continue; 848 849 pointer = local_buffer[i]; 850 851 /* Skip pointer section if the pointer is invalid. */ 852 if (pointer == 0xFFFF || pointer == 0 || 853 pointer >= hw->eeprom.word_size) 854 continue; 855 856 switch (i) { 857 case IXGBE_PCIE_GENERAL_PTR: 858 size = IXGBE_IXGBE_PCIE_GENERAL_SIZE; 859 break; 860 case IXGBE_PCIE_CONFIG0_PTR: 861 case IXGBE_PCIE_CONFIG1_PTR: 862 size = IXGBE_PCIE_CONFIG_SIZE; 863 break; 864 default: 865 size = 0; 866 break; 867 } 868 869 status = ixgbe_checksum_ptr_x550(hw, pointer, size, &checksum, 870 buffer, buffer_size); 871 if (status) 872 return status; 873 } 874 875 checksum = (u16)IXGBE_EEPROM_SUM - checksum; 876 877 return (s32)checksum; 878 } 879 880 /** ixgbe_calc_eeprom_checksum_X550 - Calculates and returns the checksum 881 * @hw: pointer to hardware structure 882 * 883 * Returns a negative error code on error, or the 16-bit checksum 884 **/ 885 static s32 ixgbe_calc_eeprom_checksum_X550(struct ixgbe_hw *hw) 886 { 887 return ixgbe_calc_checksum_X550(hw, NULL, 0); 888 } 889 890 /** ixgbe_read_ee_hostif_X550 - Read EEPROM word using a host interface command 891 * @hw: pointer to hardware structure 892 * @offset: offset of word in the EEPROM to read 893 * @data: word read from the EEPROM 894 * 895 * Reads a 16 bit word from the EEPROM using the hostif. 896 **/ 897 static s32 ixgbe_read_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset, u16 *data) 898 { 899 s32 status = 0; 900 901 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) == 0) { 902 status = ixgbe_read_ee_hostif_data_X550(hw, offset, data); 903 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 904 } else { 905 status = IXGBE_ERR_SWFW_SYNC; 906 } 907 908 return status; 909 } 910 911 /** ixgbe_validate_eeprom_checksum_X550 - Validate EEPROM checksum 912 * @hw: pointer to hardware structure 913 * @checksum_val: calculated checksum 914 * 915 * Performs checksum calculation and validates the EEPROM checksum. If the 916 * caller does not need checksum_val, the value can be NULL. 917 **/ 918 static s32 ixgbe_validate_eeprom_checksum_X550(struct ixgbe_hw *hw, 919 u16 *checksum_val) 920 { 921 s32 status; 922 u16 checksum; 923 u16 read_checksum = 0; 924 925 /* Read the first word from the EEPROM. If this times out or fails, do 926 * not continue or we could be in for a very long wait while every 927 * EEPROM read fails 928 */ 929 status = hw->eeprom.ops.read(hw, 0, &checksum); 930 if (status) { 931 hw_dbg(hw, "EEPROM read failed\n"); 932 return status; 933 } 934 935 status = hw->eeprom.ops.calc_checksum(hw); 936 if (status < 0) 937 return status; 938 939 checksum = (u16)(status & 0xffff); 940 941 status = ixgbe_read_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM, 942 &read_checksum); 943 if (status) 944 return status; 945 946 /* Verify read checksum from EEPROM is the same as 947 * calculated checksum 948 */ 949 if (read_checksum != checksum) { 950 status = IXGBE_ERR_EEPROM_CHECKSUM; 951 hw_dbg(hw, "Invalid EEPROM checksum"); 952 } 953 954 /* If the user cares, return the calculated checksum */ 955 if (checksum_val) 956 *checksum_val = checksum; 957 958 return status; 959 } 960 961 /** ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif 962 * @hw: pointer to hardware structure 963 * @offset: offset of word in the EEPROM to write 964 * @data: word write to the EEPROM 965 * 966 * Write a 16 bit word to the EEPROM using the hostif. 967 **/ 968 static s32 ixgbe_write_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset, 969 u16 data) 970 { 971 s32 status; 972 struct ixgbe_hic_write_shadow_ram buffer; 973 974 buffer.hdr.req.cmd = FW_WRITE_SHADOW_RAM_CMD; 975 buffer.hdr.req.buf_lenh = 0; 976 buffer.hdr.req.buf_lenl = FW_WRITE_SHADOW_RAM_LEN; 977 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM; 978 979 /* one word */ 980 buffer.length = cpu_to_be16(sizeof(u16)); 981 buffer.data = data; 982 buffer.address = cpu_to_be32(offset * 2); 983 984 status = ixgbe_host_interface_command(hw, &buffer, sizeof(buffer), 985 IXGBE_HI_COMMAND_TIMEOUT, false); 986 return status; 987 } 988 989 /** ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif 990 * @hw: pointer to hardware structure 991 * @offset: offset of word in the EEPROM to write 992 * @data: word write to the EEPROM 993 * 994 * Write a 16 bit word to the EEPROM using the hostif. 995 **/ 996 static s32 ixgbe_write_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset, u16 data) 997 { 998 s32 status = 0; 999 1000 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) == 0) { 1001 status = ixgbe_write_ee_hostif_data_X550(hw, offset, data); 1002 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 1003 } else { 1004 hw_dbg(hw, "write ee hostif failed to get semaphore"); 1005 status = IXGBE_ERR_SWFW_SYNC; 1006 } 1007 1008 return status; 1009 } 1010 1011 /** ixgbe_update_flash_X550 - Instruct HW to copy EEPROM to Flash device 1012 * @hw: pointer to hardware structure 1013 * 1014 * Issue a shadow RAM dump to FW to copy EEPROM from shadow RAM to the flash. 1015 **/ 1016 static s32 ixgbe_update_flash_X550(struct ixgbe_hw *hw) 1017 { 1018 s32 status = 0; 1019 union ixgbe_hic_hdr2 buffer; 1020 1021 buffer.req.cmd = FW_SHADOW_RAM_DUMP_CMD; 1022 buffer.req.buf_lenh = 0; 1023 buffer.req.buf_lenl = FW_SHADOW_RAM_DUMP_LEN; 1024 buffer.req.checksum = FW_DEFAULT_CHECKSUM; 1025 1026 status = ixgbe_host_interface_command(hw, &buffer, sizeof(buffer), 1027 IXGBE_HI_COMMAND_TIMEOUT, false); 1028 return status; 1029 } 1030 1031 /** 1032 * ixgbe_get_bus_info_X550em - Set PCI bus info 1033 * @hw: pointer to hardware structure 1034 * 1035 * Sets bus link width and speed to unknown because X550em is 1036 * not a PCI device. 1037 **/ 1038 static s32 ixgbe_get_bus_info_X550em(struct ixgbe_hw *hw) 1039 { 1040 hw->bus.type = ixgbe_bus_type_internal; 1041 hw->bus.width = ixgbe_bus_width_unknown; 1042 hw->bus.speed = ixgbe_bus_speed_unknown; 1043 1044 hw->mac.ops.set_lan_id(hw); 1045 1046 return 0; 1047 } 1048 1049 /** ixgbe_disable_rx_x550 - Disable RX unit 1050 * 1051 * Enables the Rx DMA unit for x550 1052 **/ 1053 static void ixgbe_disable_rx_x550(struct ixgbe_hw *hw) 1054 { 1055 u32 rxctrl, pfdtxgswc; 1056 s32 status; 1057 struct ixgbe_hic_disable_rxen fw_cmd; 1058 1059 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL); 1060 if (rxctrl & IXGBE_RXCTRL_RXEN) { 1061 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC); 1062 if (pfdtxgswc & IXGBE_PFDTXGSWC_VT_LBEN) { 1063 pfdtxgswc &= ~IXGBE_PFDTXGSWC_VT_LBEN; 1064 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc); 1065 hw->mac.set_lben = true; 1066 } else { 1067 hw->mac.set_lben = false; 1068 } 1069 1070 fw_cmd.hdr.cmd = FW_DISABLE_RXEN_CMD; 1071 fw_cmd.hdr.buf_len = FW_DISABLE_RXEN_LEN; 1072 fw_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM; 1073 fw_cmd.port_number = hw->bus.lan_id; 1074 1075 status = ixgbe_host_interface_command(hw, &fw_cmd, 1076 sizeof(struct ixgbe_hic_disable_rxen), 1077 IXGBE_HI_COMMAND_TIMEOUT, true); 1078 1079 /* If we fail - disable RX using register write */ 1080 if (status) { 1081 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL); 1082 if (rxctrl & IXGBE_RXCTRL_RXEN) { 1083 rxctrl &= ~IXGBE_RXCTRL_RXEN; 1084 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl); 1085 } 1086 } 1087 } 1088 } 1089 1090 /** ixgbe_update_eeprom_checksum_X550 - Updates the EEPROM checksum and flash 1091 * @hw: pointer to hardware structure 1092 * 1093 * After writing EEPROM to shadow RAM using EEWR register, software calculates 1094 * checksum and updates the EEPROM and instructs the hardware to update 1095 * the flash. 1096 **/ 1097 static s32 ixgbe_update_eeprom_checksum_X550(struct ixgbe_hw *hw) 1098 { 1099 s32 status; 1100 u16 checksum = 0; 1101 1102 /* Read the first word from the EEPROM. If this times out or fails, do 1103 * not continue or we could be in for a very long wait while every 1104 * EEPROM read fails 1105 */ 1106 status = ixgbe_read_ee_hostif_X550(hw, 0, &checksum); 1107 if (status) { 1108 hw_dbg(hw, "EEPROM read failed\n"); 1109 return status; 1110 } 1111 1112 status = ixgbe_calc_eeprom_checksum_X550(hw); 1113 if (status < 0) 1114 return status; 1115 1116 checksum = (u16)(status & 0xffff); 1117 1118 status = ixgbe_write_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM, 1119 checksum); 1120 if (status) 1121 return status; 1122 1123 status = ixgbe_update_flash_X550(hw); 1124 1125 return status; 1126 } 1127 1128 /** ixgbe_write_ee_hostif_buffer_X550 - Write EEPROM word(s) using hostif 1129 * @hw: pointer to hardware structure 1130 * @offset: offset of word in the EEPROM to write 1131 * @words: number of words 1132 * @data: word(s) write to the EEPROM 1133 * 1134 * 1135 * Write a 16 bit word(s) to the EEPROM using the hostif. 1136 **/ 1137 static s32 ixgbe_write_ee_hostif_buffer_X550(struct ixgbe_hw *hw, 1138 u16 offset, u16 words, 1139 u16 *data) 1140 { 1141 s32 status = 0; 1142 u32 i = 0; 1143 1144 /* Take semaphore for the entire operation. */ 1145 status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 1146 if (status) { 1147 hw_dbg(hw, "EEPROM write buffer - semaphore failed\n"); 1148 return status; 1149 } 1150 1151 for (i = 0; i < words; i++) { 1152 status = ixgbe_write_ee_hostif_data_X550(hw, offset + i, 1153 data[i]); 1154 if (status) { 1155 hw_dbg(hw, "Eeprom buffered write failed\n"); 1156 break; 1157 } 1158 } 1159 1160 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 1161 1162 return status; 1163 } 1164 1165 /** ixgbe_write_iosf_sb_reg_x550 - Writes a value to specified register of the 1166 * IOSF device 1167 * 1168 * @hw: pointer to hardware structure 1169 * @reg_addr: 32 bit PHY register to write 1170 * @device_type: 3 bit device type 1171 * @data: Data to write to the register 1172 **/ 1173 static s32 ixgbe_write_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr, 1174 u32 device_type, u32 data) 1175 { 1176 u32 gssr = IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_PHY0_SM; 1177 u32 command, error; 1178 s32 ret; 1179 1180 ret = hw->mac.ops.acquire_swfw_sync(hw, gssr); 1181 if (ret) 1182 return ret; 1183 1184 ret = ixgbe_iosf_wait(hw, NULL); 1185 if (ret) 1186 goto out; 1187 1188 command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) | 1189 (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT)); 1190 1191 /* Write IOSF control register */ 1192 IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command); 1193 1194 /* Write IOSF data register */ 1195 IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA, data); 1196 1197 ret = ixgbe_iosf_wait(hw, &command); 1198 1199 if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) { 1200 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >> 1201 IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT; 1202 hw_dbg(hw, "Failed to write, error %x\n", error); 1203 return IXGBE_ERR_PHY; 1204 } 1205 1206 out: 1207 hw->mac.ops.release_swfw_sync(hw, gssr); 1208 return ret; 1209 } 1210 1211 /** 1212 * ixgbe_setup_ixfi_x550em_x - MAC specific iXFI configuration 1213 * @hw: pointer to hardware structure 1214 * 1215 * iXfI configuration needed for ixgbe_mac_X550EM_x devices. 1216 **/ 1217 static s32 ixgbe_setup_ixfi_x550em_x(struct ixgbe_hw *hw) 1218 { 1219 s32 status; 1220 u32 reg_val; 1221 1222 /* Disable training protocol FSM. */ 1223 status = ixgbe_read_iosf_sb_reg_x550(hw, 1224 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id), 1225 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val); 1226 if (status) 1227 return status; 1228 1229 reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_CONV_WO_PROTOCOL; 1230 status = ixgbe_write_iosf_sb_reg_x550(hw, 1231 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id), 1232 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val); 1233 if (status) 1234 return status; 1235 1236 /* Disable Flex from training TXFFE. */ 1237 status = ixgbe_read_iosf_sb_reg_x550(hw, 1238 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id), 1239 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val); 1240 if (status) 1241 return status; 1242 1243 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN; 1244 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN; 1245 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN; 1246 status = ixgbe_write_iosf_sb_reg_x550(hw, 1247 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id), 1248 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val); 1249 if (status) 1250 return status; 1251 1252 status = ixgbe_read_iosf_sb_reg_x550(hw, 1253 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id), 1254 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val); 1255 if (status) 1256 return status; 1257 1258 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN; 1259 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN; 1260 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN; 1261 status = ixgbe_write_iosf_sb_reg_x550(hw, 1262 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id), 1263 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val); 1264 if (status) 1265 return status; 1266 1267 /* Enable override for coefficients. */ 1268 status = ixgbe_read_iosf_sb_reg_x550(hw, 1269 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id), 1270 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val); 1271 if (status) 1272 return status; 1273 1274 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_OVRRD_EN; 1275 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CZERO_EN; 1276 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CPLUS1_OVRRD_EN; 1277 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CMINUS1_OVRRD_EN; 1278 status = ixgbe_write_iosf_sb_reg_x550(hw, 1279 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id), 1280 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val); 1281 return status; 1282 } 1283 1284 /** 1285 * ixgbe_restart_an_internal_phy_x550em - restart autonegotiation for the 1286 * internal PHY 1287 * @hw: pointer to hardware structure 1288 **/ 1289 static s32 ixgbe_restart_an_internal_phy_x550em(struct ixgbe_hw *hw) 1290 { 1291 s32 status; 1292 u32 link_ctrl; 1293 1294 /* Restart auto-negotiation. */ 1295 status = hw->mac.ops.read_iosf_sb_reg(hw, 1296 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id), 1297 IXGBE_SB_IOSF_TARGET_KR_PHY, &link_ctrl); 1298 1299 if (status) { 1300 hw_dbg(hw, "Auto-negotiation did not complete\n"); 1301 return status; 1302 } 1303 1304 link_ctrl |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART; 1305 status = hw->mac.ops.write_iosf_sb_reg(hw, 1306 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id), 1307 IXGBE_SB_IOSF_TARGET_KR_PHY, link_ctrl); 1308 1309 if (hw->mac.type == ixgbe_mac_x550em_a) { 1310 u32 flx_mask_st20; 1311 1312 /* Indicate to FW that AN restart has been asserted */ 1313 status = hw->mac.ops.read_iosf_sb_reg(hw, 1314 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id), 1315 IXGBE_SB_IOSF_TARGET_KR_PHY, &flx_mask_st20); 1316 1317 if (status) { 1318 hw_dbg(hw, "Auto-negotiation did not complete\n"); 1319 return status; 1320 } 1321 1322 flx_mask_st20 |= IXGBE_KRM_PMD_FLX_MASK_ST20_FW_AN_RESTART; 1323 status = hw->mac.ops.write_iosf_sb_reg(hw, 1324 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id), 1325 IXGBE_SB_IOSF_TARGET_KR_PHY, flx_mask_st20); 1326 } 1327 1328 return status; 1329 } 1330 1331 /** ixgbe_setup_ixfi_x550em - Configure the KR PHY for iXFI mode. 1332 * @hw: pointer to hardware structure 1333 * @speed: the link speed to force 1334 * 1335 * Configures the integrated KR PHY to use iXFI mode. Used to connect an 1336 * internal and external PHY at a specific speed, without autonegotiation. 1337 **/ 1338 static s32 ixgbe_setup_ixfi_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed) 1339 { 1340 s32 status; 1341 u32 reg_val; 1342 1343 /* Disable AN and force speed to 10G Serial. */ 1344 status = ixgbe_read_iosf_sb_reg_x550(hw, 1345 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id), 1346 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val); 1347 if (status) 1348 return status; 1349 1350 reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE; 1351 reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK; 1352 1353 /* Select forced link speed for internal PHY. */ 1354 switch (*speed) { 1355 case IXGBE_LINK_SPEED_10GB_FULL: 1356 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G; 1357 break; 1358 case IXGBE_LINK_SPEED_1GB_FULL: 1359 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G; 1360 break; 1361 default: 1362 /* Other link speeds are not supported by internal KR PHY. */ 1363 return IXGBE_ERR_LINK_SETUP; 1364 } 1365 1366 status = ixgbe_write_iosf_sb_reg_x550(hw, 1367 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id), 1368 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val); 1369 if (status) 1370 return status; 1371 1372 /* Additional configuration needed for x550em_x */ 1373 if (hw->mac.type == ixgbe_mac_X550EM_x) { 1374 status = ixgbe_setup_ixfi_x550em_x(hw); 1375 if (status) 1376 return status; 1377 } 1378 1379 /* Toggle port SW reset by AN reset. */ 1380 status = ixgbe_restart_an_internal_phy_x550em(hw); 1381 1382 return status; 1383 } 1384 1385 /** 1386 * ixgbe_supported_sfp_modules_X550em - Check if SFP module type is supported 1387 * @hw: pointer to hardware structure 1388 * @linear: true if SFP module is linear 1389 */ 1390 static s32 ixgbe_supported_sfp_modules_X550em(struct ixgbe_hw *hw, bool *linear) 1391 { 1392 switch (hw->phy.sfp_type) { 1393 case ixgbe_sfp_type_not_present: 1394 return IXGBE_ERR_SFP_NOT_PRESENT; 1395 case ixgbe_sfp_type_da_cu_core0: 1396 case ixgbe_sfp_type_da_cu_core1: 1397 *linear = true; 1398 break; 1399 case ixgbe_sfp_type_srlr_core0: 1400 case ixgbe_sfp_type_srlr_core1: 1401 case ixgbe_sfp_type_da_act_lmt_core0: 1402 case ixgbe_sfp_type_da_act_lmt_core1: 1403 case ixgbe_sfp_type_1g_sx_core0: 1404 case ixgbe_sfp_type_1g_sx_core1: 1405 case ixgbe_sfp_type_1g_lx_core0: 1406 case ixgbe_sfp_type_1g_lx_core1: 1407 *linear = false; 1408 break; 1409 case ixgbe_sfp_type_unknown: 1410 case ixgbe_sfp_type_1g_cu_core0: 1411 case ixgbe_sfp_type_1g_cu_core1: 1412 default: 1413 return IXGBE_ERR_SFP_NOT_SUPPORTED; 1414 } 1415 1416 return 0; 1417 } 1418 1419 /** 1420 * ixgbe_setup_mac_link_sfp_x550em - Configure the KR PHY for SFP. 1421 * @hw: pointer to hardware structure 1422 * 1423 * Configures the extern PHY and the integrated KR PHY for SFP support. 1424 */ 1425 static s32 1426 ixgbe_setup_mac_link_sfp_x550em(struct ixgbe_hw *hw, 1427 ixgbe_link_speed speed, 1428 __always_unused bool autoneg_wait_to_complete) 1429 { 1430 s32 status; 1431 u16 reg_slice, reg_val; 1432 bool setup_linear = false; 1433 1434 /* Check if SFP module is supported and linear */ 1435 status = ixgbe_supported_sfp_modules_X550em(hw, &setup_linear); 1436 1437 /* If no SFP module present, then return success. Return success since 1438 * there is no reason to configure CS4227 and SFP not present error is 1439 * not accepted in the setup MAC link flow. 1440 */ 1441 if (status == IXGBE_ERR_SFP_NOT_PRESENT) 1442 return 0; 1443 1444 if (status) 1445 return status; 1446 1447 /* Configure internal PHY for KR/KX. */ 1448 ixgbe_setup_kr_speed_x550em(hw, speed); 1449 1450 /* Configure CS4227 LINE side to proper mode. */ 1451 reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB + (hw->bus.lan_id << 12); 1452 if (setup_linear) 1453 reg_val = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1; 1454 else 1455 reg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1; 1456 1457 status = hw->link.ops.write_link(hw, hw->link.addr, reg_slice, 1458 reg_val); 1459 1460 return status; 1461 } 1462 1463 /** 1464 * ixgbe_setup_sfi_x550a - Configure the internal PHY for native SFI mode 1465 * @hw: pointer to hardware structure 1466 * @speed: the link speed to force 1467 * 1468 * Configures the integrated PHY for native SFI mode. Used to connect the 1469 * internal PHY directly to an SFP cage, without autonegotiation. 1470 **/ 1471 static s32 ixgbe_setup_sfi_x550a(struct ixgbe_hw *hw, ixgbe_link_speed *speed) 1472 { 1473 struct ixgbe_mac_info *mac = &hw->mac; 1474 s32 status; 1475 u32 reg_val; 1476 1477 /* Disable all AN and force speed to 10G Serial. */ 1478 status = mac->ops.read_iosf_sb_reg(hw, 1479 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id), 1480 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val); 1481 if (status) 1482 return status; 1483 1484 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN_EN; 1485 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN37_EN; 1486 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SGMII_EN; 1487 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_MASK; 1488 1489 /* Select forced link speed for internal PHY. */ 1490 switch (*speed) { 1491 case IXGBE_LINK_SPEED_10GB_FULL: 1492 reg_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_10G; 1493 break; 1494 case IXGBE_LINK_SPEED_1GB_FULL: 1495 reg_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_1G; 1496 break; 1497 default: 1498 /* Other link speeds are not supported by internal PHY. */ 1499 return IXGBE_ERR_LINK_SETUP; 1500 } 1501 1502 status = mac->ops.write_iosf_sb_reg(hw, 1503 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id), 1504 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val); 1505 1506 /* Toggle port SW reset by AN reset. */ 1507 status = ixgbe_restart_an_internal_phy_x550em(hw); 1508 1509 return status; 1510 } 1511 1512 /** 1513 * ixgbe_setup_mac_link_sfp_n - Setup internal PHY for native SFP 1514 * @hw: pointer to hardware structure 1515 * 1516 * Configure the the integrated PHY for native SFP support. 1517 */ 1518 static s32 1519 ixgbe_setup_mac_link_sfp_n(struct ixgbe_hw *hw, ixgbe_link_speed speed, 1520 __always_unused bool autoneg_wait_to_complete) 1521 { 1522 bool setup_linear = false; 1523 u32 reg_phy_int; 1524 s32 ret_val; 1525 1526 /* Check if SFP module is supported and linear */ 1527 ret_val = ixgbe_supported_sfp_modules_X550em(hw, &setup_linear); 1528 1529 /* If no SFP module present, then return success. Return success since 1530 * SFP not present error is not excepted in the setup MAC link flow. 1531 */ 1532 if (ret_val == IXGBE_ERR_SFP_NOT_PRESENT) 1533 return 0; 1534 1535 if (!ret_val) 1536 return ret_val; 1537 1538 /* Configure internal PHY for native SFI based on module type */ 1539 ret_val = hw->mac.ops.read_iosf_sb_reg(hw, 1540 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id), 1541 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_phy_int); 1542 if (!ret_val) 1543 return ret_val; 1544 1545 reg_phy_int &= IXGBE_KRM_PMD_FLX_MASK_ST20_SFI_10G_DA; 1546 if (!setup_linear) 1547 reg_phy_int |= IXGBE_KRM_PMD_FLX_MASK_ST20_SFI_10G_SR; 1548 1549 ret_val = hw->mac.ops.write_iosf_sb_reg(hw, 1550 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id), 1551 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_phy_int); 1552 if (!ret_val) 1553 return ret_val; 1554 1555 /* Setup SFI internal link. */ 1556 return ixgbe_setup_sfi_x550a(hw, &speed); 1557 } 1558 1559 /** 1560 * ixgbe_setup_mac_link_sfp_x550a - Setup internal PHY for SFP 1561 * @hw: pointer to hardware structure 1562 * 1563 * Configure the the integrated PHY for SFP support. 1564 */ 1565 static s32 1566 ixgbe_setup_mac_link_sfp_x550a(struct ixgbe_hw *hw, ixgbe_link_speed speed, 1567 __always_unused bool autoneg_wait_to_complete) 1568 { 1569 u32 reg_slice, slice_offset; 1570 bool setup_linear = false; 1571 u16 reg_phy_ext; 1572 s32 ret_val; 1573 1574 /* Check if SFP module is supported and linear */ 1575 ret_val = ixgbe_supported_sfp_modules_X550em(hw, &setup_linear); 1576 1577 /* If no SFP module present, then return success. Return success since 1578 * SFP not present error is not excepted in the setup MAC link flow. 1579 */ 1580 if (ret_val == IXGBE_ERR_SFP_NOT_PRESENT) 1581 return 0; 1582 1583 if (!ret_val) 1584 return ret_val; 1585 1586 /* Configure internal PHY for KR/KX. */ 1587 ixgbe_setup_kr_speed_x550em(hw, speed); 1588 1589 if (hw->phy.mdio.prtad == MDIO_PRTAD_NONE) 1590 return IXGBE_ERR_PHY_ADDR_INVALID; 1591 1592 /* Get external PHY device id */ 1593 ret_val = hw->phy.ops.read_reg(hw, IXGBE_CS4227_GLOBAL_ID_MSB, 1594 IXGBE_MDIO_ZERO_DEV_TYPE, ®_phy_ext); 1595 if (ret_val) 1596 return ret_val; 1597 1598 /* When configuring quad port CS4223, the MAC instance is part 1599 * of the slice offset. 1600 */ 1601 if (reg_phy_ext == IXGBE_CS4223_PHY_ID) 1602 slice_offset = (hw->bus.lan_id + 1603 (hw->bus.instance_id << 1)) << 12; 1604 else 1605 slice_offset = hw->bus.lan_id << 12; 1606 1607 /* Configure CS4227/CS4223 LINE side to proper mode. */ 1608 reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB + slice_offset; 1609 if (setup_linear) 1610 reg_phy_ext = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 1; 1611 else 1612 reg_phy_ext = (IXGBE_CS4227_EDC_MODE_SR << 1) | 1; 1613 return hw->phy.ops.write_reg(hw, reg_slice, IXGBE_MDIO_ZERO_DEV_TYPE, 1614 reg_phy_ext); 1615 } 1616 1617 /** 1618 * ixgbe_setup_mac_link_t_X550em - Sets the auto advertised link speed 1619 * @hw: pointer to hardware structure 1620 * @speed: new link speed 1621 * @autoneg_wait_to_complete: true when waiting for completion is needed 1622 * 1623 * Setup internal/external PHY link speed based on link speed, then set 1624 * external PHY auto advertised link speed. 1625 * 1626 * Returns error status for any failure 1627 **/ 1628 static s32 ixgbe_setup_mac_link_t_X550em(struct ixgbe_hw *hw, 1629 ixgbe_link_speed speed, 1630 bool autoneg_wait) 1631 { 1632 s32 status; 1633 ixgbe_link_speed force_speed; 1634 1635 /* Setup internal/external PHY link speed to iXFI (10G), unless 1636 * only 1G is auto advertised then setup KX link. 1637 */ 1638 if (speed & IXGBE_LINK_SPEED_10GB_FULL) 1639 force_speed = IXGBE_LINK_SPEED_10GB_FULL; 1640 else 1641 force_speed = IXGBE_LINK_SPEED_1GB_FULL; 1642 1643 /* If internal link mode is XFI, then setup XFI internal link. */ 1644 if (!(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) { 1645 status = ixgbe_setup_ixfi_x550em(hw, &force_speed); 1646 1647 if (status) 1648 return status; 1649 } 1650 1651 return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait); 1652 } 1653 1654 /** ixgbe_check_link_t_X550em - Determine link and speed status 1655 * @hw: pointer to hardware structure 1656 * @speed: pointer to link speed 1657 * @link_up: true when link is up 1658 * @link_up_wait_to_complete: bool used to wait for link up or not 1659 * 1660 * Check that both the MAC and X557 external PHY have link. 1661 **/ 1662 static s32 ixgbe_check_link_t_X550em(struct ixgbe_hw *hw, 1663 ixgbe_link_speed *speed, 1664 bool *link_up, 1665 bool link_up_wait_to_complete) 1666 { 1667 u32 status; 1668 u16 i, autoneg_status; 1669 1670 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper) 1671 return IXGBE_ERR_CONFIG; 1672 1673 status = ixgbe_check_mac_link_generic(hw, speed, link_up, 1674 link_up_wait_to_complete); 1675 1676 /* If check link fails or MAC link is not up, then return */ 1677 if (status || !(*link_up)) 1678 return status; 1679 1680 /* MAC link is up, so check external PHY link. 1681 * Link status is latching low, and can only be used to detect link 1682 * drop, and not the current status of the link without performing 1683 * back-to-back reads. 1684 */ 1685 for (i = 0; i < 2; i++) { 1686 status = hw->phy.ops.read_reg(hw, MDIO_STAT1, MDIO_MMD_AN, 1687 &autoneg_status); 1688 1689 if (status) 1690 return status; 1691 } 1692 1693 /* If external PHY link is not up, then indicate link not up */ 1694 if (!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS)) 1695 *link_up = false; 1696 1697 return 0; 1698 } 1699 1700 /** 1701 * ixgbe_setup_sgmii - Set up link for sgmii 1702 * @hw: pointer to hardware structure 1703 */ 1704 static s32 1705 ixgbe_setup_sgmii(struct ixgbe_hw *hw, __always_unused ixgbe_link_speed speed, 1706 __always_unused bool autoneg_wait_to_complete) 1707 { 1708 struct ixgbe_mac_info *mac = &hw->mac; 1709 u32 lval, sval, flx_val; 1710 s32 rc; 1711 1712 rc = mac->ops.read_iosf_sb_reg(hw, 1713 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id), 1714 IXGBE_SB_IOSF_TARGET_KR_PHY, &lval); 1715 if (rc) 1716 return rc; 1717 1718 lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE; 1719 lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK; 1720 lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_SGMII_EN; 1721 lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CLAUSE_37_EN; 1722 lval |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G; 1723 rc = mac->ops.write_iosf_sb_reg(hw, 1724 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id), 1725 IXGBE_SB_IOSF_TARGET_KR_PHY, lval); 1726 if (rc) 1727 return rc; 1728 1729 rc = mac->ops.read_iosf_sb_reg(hw, 1730 IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id), 1731 IXGBE_SB_IOSF_TARGET_KR_PHY, &sval); 1732 if (rc) 1733 return rc; 1734 1735 sval |= IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_10_D; 1736 sval |= IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_100_D; 1737 rc = mac->ops.write_iosf_sb_reg(hw, 1738 IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id), 1739 IXGBE_SB_IOSF_TARGET_KR_PHY, sval); 1740 if (rc) 1741 return rc; 1742 1743 rc = mac->ops.read_iosf_sb_reg(hw, 1744 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id), 1745 IXGBE_SB_IOSF_TARGET_KR_PHY, &flx_val); 1746 if (rc) 1747 return rc; 1748 1749 rc = mac->ops.read_iosf_sb_reg(hw, 1750 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id), 1751 IXGBE_SB_IOSF_TARGET_KR_PHY, &flx_val); 1752 if (rc) 1753 return rc; 1754 1755 flx_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_MASK; 1756 flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_1G; 1757 flx_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN_EN; 1758 flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SGMII_EN; 1759 flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_AN37_EN; 1760 1761 rc = mac->ops.write_iosf_sb_reg(hw, 1762 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id), 1763 IXGBE_SB_IOSF_TARGET_KR_PHY, flx_val); 1764 if (rc) 1765 return rc; 1766 1767 rc = ixgbe_restart_an_internal_phy_x550em(hw); 1768 return rc; 1769 } 1770 1771 /** ixgbe_init_mac_link_ops_X550em_a - Init mac link function pointers 1772 * @hw: pointer to hardware structure 1773 **/ 1774 static void ixgbe_init_mac_link_ops_X550em_a(struct ixgbe_hw *hw) 1775 { 1776 struct ixgbe_mac_info *mac = &hw->mac; 1777 1778 switch (mac->ops.get_media_type(hw)) { 1779 case ixgbe_media_type_fiber: 1780 mac->ops.setup_fc = NULL; 1781 mac->ops.fc_autoneg = ixgbe_fc_autoneg_fiber_x550em_a; 1782 break; 1783 case ixgbe_media_type_backplane: 1784 mac->ops.fc_autoneg = ixgbe_fc_autoneg_backplane_x550em_a; 1785 mac->ops.setup_fc = ixgbe_setup_fc_backplane_x550em_a; 1786 break; 1787 default: 1788 break; 1789 } 1790 } 1791 1792 /** ixgbe_init_mac_link_ops_X550em - init mac link function pointers 1793 * @hw: pointer to hardware structure 1794 **/ 1795 static void ixgbe_init_mac_link_ops_X550em(struct ixgbe_hw *hw) 1796 { 1797 struct ixgbe_mac_info *mac = &hw->mac; 1798 1799 mac->ops.setup_fc = ixgbe_setup_fc_x550em; 1800 1801 switch (mac->ops.get_media_type(hw)) { 1802 case ixgbe_media_type_fiber: 1803 /* CS4227 does not support autoneg, so disable the laser control 1804 * functions for SFP+ fiber 1805 */ 1806 mac->ops.disable_tx_laser = NULL; 1807 mac->ops.enable_tx_laser = NULL; 1808 mac->ops.flap_tx_laser = NULL; 1809 mac->ops.setup_link = ixgbe_setup_mac_link_multispeed_fiber; 1810 switch (hw->device_id) { 1811 case IXGBE_DEV_ID_X550EM_A_SFP_N: 1812 mac->ops.setup_mac_link = ixgbe_setup_mac_link_sfp_n; 1813 break; 1814 case IXGBE_DEV_ID_X550EM_A_SFP: 1815 mac->ops.setup_mac_link = 1816 ixgbe_setup_mac_link_sfp_x550a; 1817 break; 1818 default: 1819 mac->ops.setup_mac_link = 1820 ixgbe_setup_mac_link_sfp_x550em; 1821 break; 1822 } 1823 mac->ops.set_rate_select_speed = 1824 ixgbe_set_soft_rate_select_speed; 1825 break; 1826 case ixgbe_media_type_copper: 1827 mac->ops.setup_link = ixgbe_setup_mac_link_t_X550em; 1828 mac->ops.setup_fc = ixgbe_setup_fc_generic; 1829 mac->ops.check_link = ixgbe_check_link_t_X550em; 1830 return; 1831 case ixgbe_media_type_backplane: 1832 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_SGMII || 1833 hw->device_id == IXGBE_DEV_ID_X550EM_A_SGMII_L) 1834 mac->ops.setup_link = ixgbe_setup_sgmii; 1835 break; 1836 default: 1837 break; 1838 } 1839 1840 /* Additional modification for X550em_a devices */ 1841 if (hw->mac.type == ixgbe_mac_x550em_a) 1842 ixgbe_init_mac_link_ops_X550em_a(hw); 1843 } 1844 1845 /** ixgbe_setup_sfp_modules_X550em - Setup SFP module 1846 * @hw: pointer to hardware structure 1847 */ 1848 static s32 ixgbe_setup_sfp_modules_X550em(struct ixgbe_hw *hw) 1849 { 1850 s32 status; 1851 bool linear; 1852 1853 /* Check if SFP module is supported */ 1854 status = ixgbe_supported_sfp_modules_X550em(hw, &linear); 1855 if (status) 1856 return status; 1857 1858 ixgbe_init_mac_link_ops_X550em(hw); 1859 hw->phy.ops.reset = NULL; 1860 1861 return 0; 1862 } 1863 1864 /** ixgbe_get_link_capabilities_x550em - Determines link capabilities 1865 * @hw: pointer to hardware structure 1866 * @speed: pointer to link speed 1867 * @autoneg: true when autoneg or autotry is enabled 1868 **/ 1869 static s32 ixgbe_get_link_capabilities_X550em(struct ixgbe_hw *hw, 1870 ixgbe_link_speed *speed, 1871 bool *autoneg) 1872 { 1873 /* SFP */ 1874 if (hw->phy.media_type == ixgbe_media_type_fiber) { 1875 /* CS4227 SFP must not enable auto-negotiation */ 1876 *autoneg = false; 1877 1878 if (hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 || 1879 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1) { 1880 *speed = IXGBE_LINK_SPEED_1GB_FULL; 1881 return 0; 1882 } 1883 1884 /* Link capabilities are based on SFP */ 1885 if (hw->phy.multispeed_fiber) 1886 *speed = IXGBE_LINK_SPEED_10GB_FULL | 1887 IXGBE_LINK_SPEED_1GB_FULL; 1888 else 1889 *speed = IXGBE_LINK_SPEED_10GB_FULL; 1890 } else { 1891 *speed = IXGBE_LINK_SPEED_10GB_FULL | 1892 IXGBE_LINK_SPEED_1GB_FULL; 1893 *autoneg = true; 1894 } 1895 return 0; 1896 } 1897 1898 /** 1899 * ixgbe_get_lasi_ext_t_x550em - Determime external Base T PHY interrupt cause 1900 * @hw: pointer to hardware structure 1901 * @lsc: pointer to boolean flag which indicates whether external Base T 1902 * PHY interrupt is lsc 1903 * 1904 * Determime if external Base T PHY interrupt cause is high temperature 1905 * failure alarm or link status change. 1906 * 1907 * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature 1908 * failure alarm, else return PHY access status. 1909 **/ 1910 static s32 ixgbe_get_lasi_ext_t_x550em(struct ixgbe_hw *hw, bool *lsc) 1911 { 1912 u32 status; 1913 u16 reg; 1914 1915 *lsc = false; 1916 1917 /* Vendor alarm triggered */ 1918 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG, 1919 MDIO_MMD_VEND1, 1920 ®); 1921 1922 if (status || !(reg & IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN)) 1923 return status; 1924 1925 /* Vendor Auto-Neg alarm triggered or Global alarm 1 triggered */ 1926 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_FLAG, 1927 MDIO_MMD_VEND1, 1928 ®); 1929 1930 if (status || !(reg & (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN | 1931 IXGBE_MDIO_GLOBAL_ALARM_1_INT))) 1932 return status; 1933 1934 /* Global alarm triggered */ 1935 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_ALARM_1, 1936 MDIO_MMD_VEND1, 1937 ®); 1938 1939 if (status) 1940 return status; 1941 1942 /* If high temperature failure, then return over temp error and exit */ 1943 if (reg & IXGBE_MDIO_GLOBAL_ALM_1_HI_TMP_FAIL) { 1944 /* power down the PHY in case the PHY FW didn't already */ 1945 ixgbe_set_copper_phy_power(hw, false); 1946 return IXGBE_ERR_OVERTEMP; 1947 } 1948 if (reg & IXGBE_MDIO_GLOBAL_ALM_1_DEV_FAULT) { 1949 /* device fault alarm triggered */ 1950 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_FAULT_MSG, 1951 MDIO_MMD_VEND1, 1952 ®); 1953 if (status) 1954 return status; 1955 1956 /* if device fault was due to high temp alarm handle and exit */ 1957 if (reg == IXGBE_MDIO_GLOBAL_FAULT_MSG_HI_TMP) { 1958 /* power down the PHY in case the PHY FW didn't */ 1959 ixgbe_set_copper_phy_power(hw, false); 1960 return IXGBE_ERR_OVERTEMP; 1961 } 1962 } 1963 1964 /* Vendor alarm 2 triggered */ 1965 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG, 1966 MDIO_MMD_AN, ®); 1967 1968 if (status || !(reg & IXGBE_MDIO_GLOBAL_STD_ALM2_INT)) 1969 return status; 1970 1971 /* link connect/disconnect event occurred */ 1972 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM2, 1973 MDIO_MMD_AN, ®); 1974 1975 if (status) 1976 return status; 1977 1978 /* Indicate LSC */ 1979 if (reg & IXGBE_MDIO_AUTO_NEG_VEN_LSC) 1980 *lsc = true; 1981 1982 return 0; 1983 } 1984 1985 /** 1986 * ixgbe_enable_lasi_ext_t_x550em - Enable external Base T PHY interrupts 1987 * @hw: pointer to hardware structure 1988 * 1989 * Enable link status change and temperature failure alarm for the external 1990 * Base T PHY 1991 * 1992 * Returns PHY access status 1993 **/ 1994 static s32 ixgbe_enable_lasi_ext_t_x550em(struct ixgbe_hw *hw) 1995 { 1996 u32 status; 1997 u16 reg; 1998 bool lsc; 1999 2000 /* Clear interrupt flags */ 2001 status = ixgbe_get_lasi_ext_t_x550em(hw, &lsc); 2002 2003 /* Enable link status change alarm */ 2004 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK, 2005 MDIO_MMD_AN, ®); 2006 if (status) 2007 return status; 2008 2009 reg |= IXGBE_MDIO_PMA_TX_VEN_LASI_INT_EN; 2010 2011 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK, 2012 MDIO_MMD_AN, reg); 2013 if (status) 2014 return status; 2015 2016 /* Enable high temperature failure and global fault alarms */ 2017 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK, 2018 MDIO_MMD_VEND1, 2019 ®); 2020 if (status) 2021 return status; 2022 2023 reg |= (IXGBE_MDIO_GLOBAL_INT_HI_TEMP_EN | 2024 IXGBE_MDIO_GLOBAL_INT_DEV_FAULT_EN); 2025 2026 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK, 2027 MDIO_MMD_VEND1, 2028 reg); 2029 if (status) 2030 return status; 2031 2032 /* Enable vendor Auto-Neg alarm and Global Interrupt Mask 1 alarm */ 2033 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK, 2034 MDIO_MMD_VEND1, 2035 ®); 2036 if (status) 2037 return status; 2038 2039 reg |= (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN | 2040 IXGBE_MDIO_GLOBAL_ALARM_1_INT); 2041 2042 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK, 2043 MDIO_MMD_VEND1, 2044 reg); 2045 if (status) 2046 return status; 2047 2048 /* Enable chip-wide vendor alarm */ 2049 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK, 2050 MDIO_MMD_VEND1, 2051 ®); 2052 if (status) 2053 return status; 2054 2055 reg |= IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN; 2056 2057 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK, 2058 MDIO_MMD_VEND1, 2059 reg); 2060 2061 return status; 2062 } 2063 2064 /** 2065 * ixgbe_handle_lasi_ext_t_x550em - Handle external Base T PHY interrupt 2066 * @hw: pointer to hardware structure 2067 * 2068 * Handle external Base T PHY interrupt. If high temperature 2069 * failure alarm then return error, else if link status change 2070 * then setup internal/external PHY link 2071 * 2072 * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature 2073 * failure alarm, else return PHY access status. 2074 **/ 2075 static s32 ixgbe_handle_lasi_ext_t_x550em(struct ixgbe_hw *hw) 2076 { 2077 struct ixgbe_phy_info *phy = &hw->phy; 2078 bool lsc; 2079 u32 status; 2080 2081 status = ixgbe_get_lasi_ext_t_x550em(hw, &lsc); 2082 if (status) 2083 return status; 2084 2085 if (lsc && phy->ops.setup_internal_link) 2086 return phy->ops.setup_internal_link(hw); 2087 2088 return 0; 2089 } 2090 2091 /** 2092 * ixgbe_setup_kr_speed_x550em - Configure the KR PHY for link speed. 2093 * @hw: pointer to hardware structure 2094 * @speed: link speed 2095 * 2096 * Configures the integrated KR PHY. 2097 **/ 2098 static s32 ixgbe_setup_kr_speed_x550em(struct ixgbe_hw *hw, 2099 ixgbe_link_speed speed) 2100 { 2101 s32 status; 2102 u32 reg_val; 2103 2104 status = hw->mac.ops.read_iosf_sb_reg(hw, 2105 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id), 2106 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val); 2107 if (status) 2108 return status; 2109 2110 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE; 2111 reg_val &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_AN_FEC_REQ | 2112 IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_FEC); 2113 reg_val &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR | 2114 IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX); 2115 2116 /* Advertise 10G support. */ 2117 if (speed & IXGBE_LINK_SPEED_10GB_FULL) 2118 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR; 2119 2120 /* Advertise 1G support. */ 2121 if (speed & IXGBE_LINK_SPEED_1GB_FULL) 2122 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX; 2123 2124 status = hw->mac.ops.write_iosf_sb_reg(hw, 2125 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id), 2126 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val); 2127 2128 if (hw->mac.type == ixgbe_mac_x550em_a) { 2129 /* Set lane mode to KR auto negotiation */ 2130 status = hw->mac.ops.read_iosf_sb_reg(hw, 2131 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id), 2132 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val); 2133 2134 if (status) 2135 return status; 2136 2137 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_MASK; 2138 reg_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_AN; 2139 reg_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_AN_EN; 2140 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN37_EN; 2141 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SGMII_EN; 2142 2143 status = hw->mac.ops.write_iosf_sb_reg(hw, 2144 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id), 2145 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val); 2146 } 2147 2148 return ixgbe_restart_an_internal_phy_x550em(hw); 2149 } 2150 2151 /** ixgbe_setup_kx4_x550em - Configure the KX4 PHY. 2152 * @hw: pointer to hardware structure 2153 * 2154 * Configures the integrated KX4 PHY. 2155 **/ 2156 static s32 ixgbe_setup_kx4_x550em(struct ixgbe_hw *hw) 2157 { 2158 s32 status; 2159 u32 reg_val; 2160 2161 status = hw->mac.ops.read_iosf_sb_reg(hw, IXGBE_KX4_LINK_CNTL_1, 2162 IXGBE_SB_IOSF_TARGET_KX4_PCS0 + 2163 hw->bus.lan_id, ®_val); 2164 if (status) 2165 return status; 2166 2167 reg_val &= ~(IXGBE_KX4_LINK_CNTL_1_TETH_AN_CAP_KX4 | 2168 IXGBE_KX4_LINK_CNTL_1_TETH_AN_CAP_KX); 2169 2170 reg_val |= IXGBE_KX4_LINK_CNTL_1_TETH_AN_ENABLE; 2171 2172 /* Advertise 10G support. */ 2173 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL) 2174 reg_val |= IXGBE_KX4_LINK_CNTL_1_TETH_AN_CAP_KX4; 2175 2176 /* Advertise 1G support. */ 2177 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL) 2178 reg_val |= IXGBE_KX4_LINK_CNTL_1_TETH_AN_CAP_KX; 2179 2180 /* Restart auto-negotiation. */ 2181 reg_val |= IXGBE_KX4_LINK_CNTL_1_TETH_AN_RESTART; 2182 status = hw->mac.ops.write_iosf_sb_reg(hw, IXGBE_KX4_LINK_CNTL_1, 2183 IXGBE_SB_IOSF_TARGET_KX4_PCS0 + 2184 hw->bus.lan_id, reg_val); 2185 2186 return status; 2187 } 2188 2189 /** 2190 * ixgbe_setup_kr_x550em - Configure the KR PHY 2191 * @hw: pointer to hardware structure 2192 * 2193 * Configures the integrated KR PHY for X550EM_x. 2194 **/ 2195 static s32 ixgbe_setup_kr_x550em(struct ixgbe_hw *hw) 2196 { 2197 if (hw->mac.type != ixgbe_mac_X550EM_x) 2198 return 0; 2199 2200 return ixgbe_setup_kr_speed_x550em(hw, hw->phy.autoneg_advertised); 2201 } 2202 2203 /** ixgbe_ext_phy_t_x550em_get_link - Get ext phy link status 2204 * @hw: address of hardware structure 2205 * @link_up: address of boolean to indicate link status 2206 * 2207 * Returns error code if unable to get link status. 2208 **/ 2209 static s32 ixgbe_ext_phy_t_x550em_get_link(struct ixgbe_hw *hw, bool *link_up) 2210 { 2211 u32 ret; 2212 u16 autoneg_status; 2213 2214 *link_up = false; 2215 2216 /* read this twice back to back to indicate current status */ 2217 ret = hw->phy.ops.read_reg(hw, MDIO_STAT1, MDIO_MMD_AN, 2218 &autoneg_status); 2219 if (ret) 2220 return ret; 2221 2222 ret = hw->phy.ops.read_reg(hw, MDIO_STAT1, MDIO_MMD_AN, 2223 &autoneg_status); 2224 if (ret) 2225 return ret; 2226 2227 *link_up = !!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS); 2228 2229 return 0; 2230 } 2231 2232 /** ixgbe_setup_internal_phy_t_x550em - Configure KR PHY to X557 link 2233 * @hw: point to hardware structure 2234 * 2235 * Configures the link between the integrated KR PHY and the external X557 PHY 2236 * The driver will call this function when it gets a link status change 2237 * interrupt from the X557 PHY. This function configures the link speed 2238 * between the PHYs to match the link speed of the BASE-T link. 2239 * 2240 * A return of a non-zero value indicates an error, and the base driver should 2241 * not report link up. 2242 **/ 2243 static s32 ixgbe_setup_internal_phy_t_x550em(struct ixgbe_hw *hw) 2244 { 2245 ixgbe_link_speed force_speed; 2246 bool link_up; 2247 u32 status; 2248 u16 speed; 2249 2250 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper) 2251 return IXGBE_ERR_CONFIG; 2252 2253 if (hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE) { 2254 speed = IXGBE_LINK_SPEED_10GB_FULL | 2255 IXGBE_LINK_SPEED_1GB_FULL; 2256 return ixgbe_setup_kr_speed_x550em(hw, speed); 2257 } 2258 2259 /* If link is not up, then there is no setup necessary so return */ 2260 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up); 2261 if (status) 2262 return status; 2263 2264 if (!link_up) 2265 return 0; 2266 2267 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_STAT, 2268 MDIO_MMD_AN, 2269 &speed); 2270 if (status) 2271 return status; 2272 2273 /* If link is not still up, then no setup is necessary so return */ 2274 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up); 2275 if (status) 2276 return status; 2277 2278 if (!link_up) 2279 return 0; 2280 2281 /* clear everything but the speed and duplex bits */ 2282 speed &= IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_MASK; 2283 2284 switch (speed) { 2285 case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB_FULL: 2286 force_speed = IXGBE_LINK_SPEED_10GB_FULL; 2287 break; 2288 case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB_FULL: 2289 force_speed = IXGBE_LINK_SPEED_1GB_FULL; 2290 break; 2291 default: 2292 /* Internal PHY does not support anything else */ 2293 return IXGBE_ERR_INVALID_LINK_SETTINGS; 2294 } 2295 2296 return ixgbe_setup_ixfi_x550em(hw, &force_speed); 2297 } 2298 2299 /** ixgbe_reset_phy_t_X550em - Performs X557 PHY reset and enables LASI 2300 * @hw: pointer to hardware structure 2301 **/ 2302 static s32 ixgbe_reset_phy_t_X550em(struct ixgbe_hw *hw) 2303 { 2304 s32 status; 2305 2306 status = ixgbe_reset_phy_generic(hw); 2307 2308 if (status) 2309 return status; 2310 2311 /* Configure Link Status Alarm and Temperature Threshold interrupts */ 2312 return ixgbe_enable_lasi_ext_t_x550em(hw); 2313 } 2314 2315 /** 2316 * ixgbe_led_on_t_x550em - Turns on the software controllable LEDs. 2317 * @hw: pointer to hardware structure 2318 * @led_idx: led number to turn on 2319 **/ 2320 static s32 ixgbe_led_on_t_x550em(struct ixgbe_hw *hw, u32 led_idx) 2321 { 2322 u16 phy_data; 2323 2324 if (led_idx >= IXGBE_X557_MAX_LED_INDEX) 2325 return IXGBE_ERR_PARAM; 2326 2327 /* To turn on the LED, set mode to ON. */ 2328 hw->phy.ops.read_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx, 2329 MDIO_MMD_VEND1, &phy_data); 2330 phy_data |= IXGBE_X557_LED_MANUAL_SET_MASK; 2331 hw->phy.ops.write_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx, 2332 MDIO_MMD_VEND1, phy_data); 2333 2334 return 0; 2335 } 2336 2337 /** 2338 * ixgbe_led_off_t_x550em - Turns off the software controllable LEDs. 2339 * @hw: pointer to hardware structure 2340 * @led_idx: led number to turn off 2341 **/ 2342 static s32 ixgbe_led_off_t_x550em(struct ixgbe_hw *hw, u32 led_idx) 2343 { 2344 u16 phy_data; 2345 2346 if (led_idx >= IXGBE_X557_MAX_LED_INDEX) 2347 return IXGBE_ERR_PARAM; 2348 2349 /* To turn on the LED, set mode to ON. */ 2350 hw->phy.ops.read_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx, 2351 MDIO_MMD_VEND1, &phy_data); 2352 phy_data &= ~IXGBE_X557_LED_MANUAL_SET_MASK; 2353 hw->phy.ops.write_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx, 2354 MDIO_MMD_VEND1, phy_data); 2355 2356 return 0; 2357 } 2358 2359 /** ixgbe_get_lcd_x550em - Determine lowest common denominator 2360 * @hw: pointer to hardware structure 2361 * @lcd_speed: pointer to lowest common link speed 2362 * 2363 * Determine lowest common link speed with link partner. 2364 **/ 2365 static s32 ixgbe_get_lcd_t_x550em(struct ixgbe_hw *hw, 2366 ixgbe_link_speed *lcd_speed) 2367 { 2368 u16 an_lp_status; 2369 s32 status; 2370 u16 word = hw->eeprom.ctrl_word_3; 2371 2372 *lcd_speed = IXGBE_LINK_SPEED_UNKNOWN; 2373 2374 status = hw->phy.ops.read_reg(hw, IXGBE_AUTO_NEG_LP_STATUS, 2375 MDIO_MMD_AN, 2376 &an_lp_status); 2377 if (status) 2378 return status; 2379 2380 /* If link partner advertised 1G, return 1G */ 2381 if (an_lp_status & IXGBE_AUTO_NEG_LP_1000BASE_CAP) { 2382 *lcd_speed = IXGBE_LINK_SPEED_1GB_FULL; 2383 return status; 2384 } 2385 2386 /* If 10G disabled for LPLU via NVM D10GMP, then return no valid LCD */ 2387 if ((hw->bus.lan_id && (word & NVM_INIT_CTRL_3_D10GMP_PORT1)) || 2388 (word & NVM_INIT_CTRL_3_D10GMP_PORT0)) 2389 return status; 2390 2391 /* Link partner not capable of lower speeds, return 10G */ 2392 *lcd_speed = IXGBE_LINK_SPEED_10GB_FULL; 2393 return status; 2394 } 2395 2396 /** 2397 * ixgbe_setup_fc_x550em - Set up flow control 2398 * @hw: pointer to hardware structure 2399 */ 2400 static s32 ixgbe_setup_fc_x550em(struct ixgbe_hw *hw) 2401 { 2402 bool pause, asm_dir; 2403 u32 reg_val; 2404 s32 rc; 2405 2406 /* Validate the requested mode */ 2407 if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) { 2408 hw_err(hw, "ixgbe_fc_rx_pause not valid in strict IEEE mode\n"); 2409 return IXGBE_ERR_INVALID_LINK_SETTINGS; 2410 } 2411 2412 /* 10gig parts do not have a word in the EEPROM to determine the 2413 * default flow control setting, so we explicitly set it to full. 2414 */ 2415 if (hw->fc.requested_mode == ixgbe_fc_default) 2416 hw->fc.requested_mode = ixgbe_fc_full; 2417 2418 /* Determine PAUSE and ASM_DIR bits. */ 2419 switch (hw->fc.requested_mode) { 2420 case ixgbe_fc_none: 2421 pause = false; 2422 asm_dir = false; 2423 break; 2424 case ixgbe_fc_tx_pause: 2425 pause = false; 2426 asm_dir = true; 2427 break; 2428 case ixgbe_fc_rx_pause: 2429 /* Rx Flow control is enabled and Tx Flow control is 2430 * disabled by software override. Since there really 2431 * isn't a way to advertise that we are capable of RX 2432 * Pause ONLY, we will advertise that we support both 2433 * symmetric and asymmetric Rx PAUSE, as such we fall 2434 * through to the fc_full statement. Later, we will 2435 * disable the adapter's ability to send PAUSE frames. 2436 */ 2437 /* Fallthrough */ 2438 case ixgbe_fc_full: 2439 pause = true; 2440 asm_dir = true; 2441 break; 2442 default: 2443 hw_err(hw, "Flow control param set incorrectly\n"); 2444 return IXGBE_ERR_CONFIG; 2445 } 2446 2447 if (hw->device_id != IXGBE_DEV_ID_X550EM_X_KR && 2448 hw->device_id != IXGBE_DEV_ID_X550EM_A_KR && 2449 hw->device_id != IXGBE_DEV_ID_X550EM_A_KR_L) 2450 return 0; 2451 2452 rc = hw->mac.ops.read_iosf_sb_reg(hw, 2453 IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id), 2454 IXGBE_SB_IOSF_TARGET_KR_PHY, 2455 ®_val); 2456 if (rc) 2457 return rc; 2458 2459 reg_val &= ~(IXGBE_KRM_AN_CNTL_1_SYM_PAUSE | 2460 IXGBE_KRM_AN_CNTL_1_ASM_PAUSE); 2461 if (pause) 2462 reg_val |= IXGBE_KRM_AN_CNTL_1_SYM_PAUSE; 2463 if (asm_dir) 2464 reg_val |= IXGBE_KRM_AN_CNTL_1_ASM_PAUSE; 2465 rc = hw->mac.ops.write_iosf_sb_reg(hw, 2466 IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id), 2467 IXGBE_SB_IOSF_TARGET_KR_PHY, 2468 reg_val); 2469 2470 /* This device does not fully support AN. */ 2471 hw->fc.disable_fc_autoneg = true; 2472 2473 return rc; 2474 } 2475 2476 /** 2477 * ixgbe_fc_autoneg_backplane_x550em_a - Enable flow control IEEE clause 37 2478 * @hw: pointer to hardware structure 2479 **/ 2480 static void ixgbe_fc_autoneg_backplane_x550em_a(struct ixgbe_hw *hw) 2481 { 2482 u32 link_s1, lp_an_page_low, an_cntl_1; 2483 s32 status = IXGBE_ERR_FC_NOT_NEGOTIATED; 2484 ixgbe_link_speed speed; 2485 bool link_up; 2486 2487 /* AN should have completed when the cable was plugged in. 2488 * Look for reasons to bail out. Bail out if: 2489 * - FC autoneg is disabled, or if 2490 * - link is not up. 2491 */ 2492 if (hw->fc.disable_fc_autoneg) { 2493 hw_err(hw, "Flow control autoneg is disabled"); 2494 goto out; 2495 } 2496 2497 hw->mac.ops.check_link(hw, &speed, &link_up, false); 2498 if (!link_up) { 2499 hw_err(hw, "The link is down"); 2500 goto out; 2501 } 2502 2503 /* Check at auto-negotiation has completed */ 2504 status = hw->mac.ops.read_iosf_sb_reg(hw, 2505 IXGBE_KRM_LINK_S1(hw->bus.lan_id), 2506 IXGBE_SB_IOSF_TARGET_KR_PHY, &link_s1); 2507 2508 if (status || (link_s1 & IXGBE_KRM_LINK_S1_MAC_AN_COMPLETE) == 0) { 2509 hw_dbg(hw, "Auto-Negotiation did not complete\n"); 2510 status = IXGBE_ERR_FC_NOT_NEGOTIATED; 2511 goto out; 2512 } 2513 2514 /* Read the 10g AN autoc and LP ability registers and resolve 2515 * local flow control settings accordingly 2516 */ 2517 status = hw->mac.ops.read_iosf_sb_reg(hw, 2518 IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id), 2519 IXGBE_SB_IOSF_TARGET_KR_PHY, &an_cntl_1); 2520 2521 if (status) { 2522 hw_dbg(hw, "Auto-Negotiation did not complete\n"); 2523 goto out; 2524 } 2525 2526 status = hw->mac.ops.read_iosf_sb_reg(hw, 2527 IXGBE_KRM_LP_BASE_PAGE_HIGH(hw->bus.lan_id), 2528 IXGBE_SB_IOSF_TARGET_KR_PHY, &lp_an_page_low); 2529 2530 if (status) { 2531 hw_dbg(hw, "Auto-Negotiation did not complete\n"); 2532 goto out; 2533 } 2534 2535 status = ixgbe_negotiate_fc(hw, an_cntl_1, lp_an_page_low, 2536 IXGBE_KRM_AN_CNTL_1_SYM_PAUSE, 2537 IXGBE_KRM_AN_CNTL_1_ASM_PAUSE, 2538 IXGBE_KRM_LP_BASE_PAGE_HIGH_SYM_PAUSE, 2539 IXGBE_KRM_LP_BASE_PAGE_HIGH_ASM_PAUSE); 2540 2541 out: 2542 if (!status) { 2543 hw->fc.fc_was_autonegged = true; 2544 } else { 2545 hw->fc.fc_was_autonegged = false; 2546 hw->fc.current_mode = hw->fc.requested_mode; 2547 } 2548 } 2549 2550 /** 2551 * ixgbe_fc_autoneg_fiber_x550em_a - passthrough FC settings 2552 * @hw: pointer to hardware structure 2553 **/ 2554 static void ixgbe_fc_autoneg_fiber_x550em_a(struct ixgbe_hw *hw) 2555 { 2556 hw->fc.fc_was_autonegged = false; 2557 hw->fc.current_mode = hw->fc.requested_mode; 2558 } 2559 2560 /** ixgbe_enter_lplu_x550em - Transition to low power states 2561 * @hw: pointer to hardware structure 2562 * 2563 * Configures Low Power Link Up on transition to low power states 2564 * (from D0 to non-D0). Link is required to enter LPLU so avoid resetting 2565 * the X557 PHY immediately prior to entering LPLU. 2566 **/ 2567 static s32 ixgbe_enter_lplu_t_x550em(struct ixgbe_hw *hw) 2568 { 2569 u16 an_10g_cntl_reg, autoneg_reg, speed; 2570 s32 status; 2571 ixgbe_link_speed lcd_speed; 2572 u32 save_autoneg; 2573 bool link_up; 2574 2575 /* If blocked by MNG FW, then don't restart AN */ 2576 if (ixgbe_check_reset_blocked(hw)) 2577 return 0; 2578 2579 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up); 2580 if (status) 2581 return status; 2582 2583 status = hw->eeprom.ops.read(hw, NVM_INIT_CTRL_3, 2584 &hw->eeprom.ctrl_word_3); 2585 if (status) 2586 return status; 2587 2588 /* If link is down, LPLU disabled in NVM, WoL disabled, or 2589 * manageability disabled, then force link down by entering 2590 * low power mode. 2591 */ 2592 if (!link_up || !(hw->eeprom.ctrl_word_3 & NVM_INIT_CTRL_3_LPLU) || 2593 !(hw->wol_enabled || ixgbe_mng_present(hw))) 2594 return ixgbe_set_copper_phy_power(hw, false); 2595 2596 /* Determine LCD */ 2597 status = ixgbe_get_lcd_t_x550em(hw, &lcd_speed); 2598 if (status) 2599 return status; 2600 2601 /* If no valid LCD link speed, then force link down and exit. */ 2602 if (lcd_speed == IXGBE_LINK_SPEED_UNKNOWN) 2603 return ixgbe_set_copper_phy_power(hw, false); 2604 2605 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_STAT, 2606 MDIO_MMD_AN, 2607 &speed); 2608 if (status) 2609 return status; 2610 2611 /* If no link now, speed is invalid so take link down */ 2612 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up); 2613 if (status) 2614 return ixgbe_set_copper_phy_power(hw, false); 2615 2616 /* clear everything but the speed bits */ 2617 speed &= IXGBE_MDIO_AUTO_NEG_VEN_STAT_SPEED_MASK; 2618 2619 /* If current speed is already LCD, then exit. */ 2620 if (((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB) && 2621 (lcd_speed == IXGBE_LINK_SPEED_1GB_FULL)) || 2622 ((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB) && 2623 (lcd_speed == IXGBE_LINK_SPEED_10GB_FULL))) 2624 return status; 2625 2626 /* Clear AN completed indication */ 2627 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM, 2628 MDIO_MMD_AN, 2629 &autoneg_reg); 2630 if (status) 2631 return status; 2632 2633 status = hw->phy.ops.read_reg(hw, MDIO_AN_10GBT_CTRL, 2634 MDIO_MMD_AN, 2635 &an_10g_cntl_reg); 2636 if (status) 2637 return status; 2638 2639 status = hw->phy.ops.read_reg(hw, 2640 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG, 2641 MDIO_MMD_AN, 2642 &autoneg_reg); 2643 if (status) 2644 return status; 2645 2646 save_autoneg = hw->phy.autoneg_advertised; 2647 2648 /* Setup link at least common link speed */ 2649 status = hw->mac.ops.setup_link(hw, lcd_speed, false); 2650 2651 /* restore autoneg from before setting lplu speed */ 2652 hw->phy.autoneg_advertised = save_autoneg; 2653 2654 return status; 2655 } 2656 2657 /** 2658 * ixgbe_read_mng_if_sel_x550em - Read NW_MNG_IF_SEL register 2659 * @hw: pointer to hardware structure 2660 * 2661 * Read NW_MNG_IF_SEL register and save field values. 2662 */ 2663 static void ixgbe_read_mng_if_sel_x550em(struct ixgbe_hw *hw) 2664 { 2665 /* Save NW management interface connected on board. This is used 2666 * to determine internal PHY mode. 2667 */ 2668 hw->phy.nw_mng_if_sel = IXGBE_READ_REG(hw, IXGBE_NW_MNG_IF_SEL); 2669 2670 /* If X552 (X550EM_a) and MDIO is connected to external PHY, then set 2671 * PHY address. This register field was has only been used for X552. 2672 */ 2673 if (hw->mac.type == ixgbe_mac_x550em_a && 2674 hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_MDIO_ACT) { 2675 hw->phy.mdio.prtad = (hw->phy.nw_mng_if_sel & 2676 IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD) >> 2677 IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD_SHIFT; 2678 } 2679 } 2680 2681 /** ixgbe_init_phy_ops_X550em - PHY/SFP specific init 2682 * @hw: pointer to hardware structure 2683 * 2684 * Initialize any function pointers that were not able to be 2685 * set during init_shared_code because the PHY/SFP type was 2686 * not known. Perform the SFP init if necessary. 2687 **/ 2688 static s32 ixgbe_init_phy_ops_X550em(struct ixgbe_hw *hw) 2689 { 2690 struct ixgbe_phy_info *phy = &hw->phy; 2691 s32 ret_val; 2692 2693 hw->mac.ops.set_lan_id(hw); 2694 2695 ixgbe_read_mng_if_sel_x550em(hw); 2696 2697 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) { 2698 phy->phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM; 2699 ixgbe_setup_mux_ctl(hw); 2700 } 2701 2702 /* Identify the PHY or SFP module */ 2703 ret_val = phy->ops.identify(hw); 2704 2705 /* Setup function pointers based on detected hardware */ 2706 ixgbe_init_mac_link_ops_X550em(hw); 2707 if (phy->sfp_type != ixgbe_sfp_type_unknown) 2708 phy->ops.reset = NULL; 2709 2710 /* Set functions pointers based on phy type */ 2711 switch (hw->phy.type) { 2712 case ixgbe_phy_x550em_kx4: 2713 phy->ops.setup_link = ixgbe_setup_kx4_x550em; 2714 phy->ops.read_reg = ixgbe_read_phy_reg_x550em; 2715 phy->ops.write_reg = ixgbe_write_phy_reg_x550em; 2716 break; 2717 case ixgbe_phy_x550em_kr: 2718 phy->ops.setup_link = ixgbe_setup_kr_x550em; 2719 phy->ops.read_reg = ixgbe_read_phy_reg_x550em; 2720 phy->ops.write_reg = ixgbe_write_phy_reg_x550em; 2721 break; 2722 case ixgbe_phy_x550em_ext_t: 2723 /* Save NW management interface connected on board. This is used 2724 * to determine internal PHY mode 2725 */ 2726 phy->nw_mng_if_sel = IXGBE_READ_REG(hw, IXGBE_NW_MNG_IF_SEL); 2727 2728 /* If internal link mode is XFI, then setup iXFI internal link, 2729 * else setup KR now. 2730 */ 2731 phy->ops.setup_internal_link = 2732 ixgbe_setup_internal_phy_t_x550em; 2733 2734 /* setup SW LPLU only for first revision */ 2735 if (hw->mac.type == ixgbe_mac_X550EM_x && 2736 !(IXGBE_READ_REG(hw, IXGBE_FUSES0_GROUP(0)) & 2737 IXGBE_FUSES0_REV_MASK)) 2738 phy->ops.enter_lplu = ixgbe_enter_lplu_t_x550em; 2739 2740 phy->ops.handle_lasi = ixgbe_handle_lasi_ext_t_x550em; 2741 phy->ops.reset = ixgbe_reset_phy_t_X550em; 2742 break; 2743 default: 2744 break; 2745 } 2746 2747 return ret_val; 2748 } 2749 2750 /** ixgbe_get_media_type_X550em - Get media type 2751 * @hw: pointer to hardware structure 2752 * 2753 * Returns the media type (fiber, copper, backplane) 2754 * 2755 */ 2756 static enum ixgbe_media_type ixgbe_get_media_type_X550em(struct ixgbe_hw *hw) 2757 { 2758 enum ixgbe_media_type media_type; 2759 2760 /* Detect if there is a copper PHY attached. */ 2761 switch (hw->device_id) { 2762 case IXGBE_DEV_ID_X550EM_A_SGMII: 2763 case IXGBE_DEV_ID_X550EM_A_SGMII_L: 2764 hw->phy.type = ixgbe_phy_sgmii; 2765 /* Fallthrough */ 2766 case IXGBE_DEV_ID_X550EM_X_KR: 2767 case IXGBE_DEV_ID_X550EM_X_KX4: 2768 case IXGBE_DEV_ID_X550EM_A_KR: 2769 case IXGBE_DEV_ID_X550EM_A_KR_L: 2770 media_type = ixgbe_media_type_backplane; 2771 break; 2772 case IXGBE_DEV_ID_X550EM_X_SFP: 2773 case IXGBE_DEV_ID_X550EM_A_SFP: 2774 case IXGBE_DEV_ID_X550EM_A_SFP_N: 2775 media_type = ixgbe_media_type_fiber; 2776 break; 2777 case IXGBE_DEV_ID_X550EM_X_1G_T: 2778 case IXGBE_DEV_ID_X550EM_X_10G_T: 2779 case IXGBE_DEV_ID_X550EM_A_10G_T: 2780 media_type = ixgbe_media_type_copper; 2781 break; 2782 default: 2783 media_type = ixgbe_media_type_unknown; 2784 break; 2785 } 2786 return media_type; 2787 } 2788 2789 /** ixgbe_init_ext_t_x550em - Start (unstall) the external Base T PHY. 2790 ** @hw: pointer to hardware structure 2791 **/ 2792 static s32 ixgbe_init_ext_t_x550em(struct ixgbe_hw *hw) 2793 { 2794 s32 status; 2795 u16 reg; 2796 2797 status = hw->phy.ops.read_reg(hw, 2798 IXGBE_MDIO_TX_VENDOR_ALARMS_3, 2799 MDIO_MMD_PMAPMD, 2800 ®); 2801 if (status) 2802 return status; 2803 2804 /* If PHY FW reset completed bit is set then this is the first 2805 * SW instance after a power on so the PHY FW must be un-stalled. 2806 */ 2807 if (reg & IXGBE_MDIO_TX_VENDOR_ALARMS_3_RST_MASK) { 2808 status = hw->phy.ops.read_reg(hw, 2809 IXGBE_MDIO_GLOBAL_RES_PR_10, 2810 MDIO_MMD_VEND1, 2811 ®); 2812 if (status) 2813 return status; 2814 2815 reg &= ~IXGBE_MDIO_POWER_UP_STALL; 2816 2817 status = hw->phy.ops.write_reg(hw, 2818 IXGBE_MDIO_GLOBAL_RES_PR_10, 2819 MDIO_MMD_VEND1, 2820 reg); 2821 if (status) 2822 return status; 2823 } 2824 2825 return status; 2826 } 2827 2828 /** 2829 * ixgbe_set_mdio_speed - Set MDIO clock speed 2830 * @hw: pointer to hardware structure 2831 */ 2832 static void ixgbe_set_mdio_speed(struct ixgbe_hw *hw) 2833 { 2834 u32 hlreg0; 2835 2836 switch (hw->device_id) { 2837 case IXGBE_DEV_ID_X550EM_X_10G_T: 2838 case IXGBE_DEV_ID_X550EM_A_SGMII: 2839 case IXGBE_DEV_ID_X550EM_A_SGMII_L: 2840 case IXGBE_DEV_ID_X550EM_A_10G_T: 2841 case IXGBE_DEV_ID_X550EM_A_SFP: 2842 /* Config MDIO clock speed before the first MDIO PHY access */ 2843 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0); 2844 hlreg0 &= ~IXGBE_HLREG0_MDCSPD; 2845 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0); 2846 break; 2847 default: 2848 break; 2849 } 2850 } 2851 2852 /** ixgbe_reset_hw_X550em - Perform hardware reset 2853 ** @hw: pointer to hardware structure 2854 ** 2855 ** Resets the hardware by resetting the transmit and receive units, masks 2856 ** and clears all interrupts, perform a PHY reset, and perform a link (MAC) 2857 ** reset. 2858 **/ 2859 static s32 ixgbe_reset_hw_X550em(struct ixgbe_hw *hw) 2860 { 2861 ixgbe_link_speed link_speed; 2862 s32 status; 2863 u32 ctrl = 0; 2864 u32 i; 2865 bool link_up = false; 2866 2867 /* Call adapter stop to disable Tx/Rx and clear interrupts */ 2868 status = hw->mac.ops.stop_adapter(hw); 2869 if (status) 2870 return status; 2871 2872 /* flush pending Tx transactions */ 2873 ixgbe_clear_tx_pending(hw); 2874 2875 /* PHY ops must be identified and initialized prior to reset */ 2876 2877 /* Identify PHY and related function pointers */ 2878 status = hw->phy.ops.init(hw); 2879 2880 /* start the external PHY */ 2881 if (hw->phy.type == ixgbe_phy_x550em_ext_t) { 2882 status = ixgbe_init_ext_t_x550em(hw); 2883 if (status) 2884 return status; 2885 } 2886 2887 /* Setup SFP module if there is one present. */ 2888 if (hw->phy.sfp_setup_needed) { 2889 status = hw->mac.ops.setup_sfp(hw); 2890 hw->phy.sfp_setup_needed = false; 2891 } 2892 2893 /* Reset PHY */ 2894 if (!hw->phy.reset_disable && hw->phy.ops.reset) 2895 hw->phy.ops.reset(hw); 2896 2897 mac_reset_top: 2898 /* Issue global reset to the MAC. Needs to be SW reset if link is up. 2899 * If link reset is used when link is up, it might reset the PHY when 2900 * mng is using it. If link is down or the flag to force full link 2901 * reset is set, then perform link reset. 2902 */ 2903 ctrl = IXGBE_CTRL_LNK_RST; 2904 2905 if (!hw->force_full_reset) { 2906 hw->mac.ops.check_link(hw, &link_speed, &link_up, false); 2907 if (link_up) 2908 ctrl = IXGBE_CTRL_RST; 2909 } 2910 2911 ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL); 2912 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl); 2913 IXGBE_WRITE_FLUSH(hw); 2914 usleep_range(1000, 1200); 2915 2916 /* Poll for reset bit to self-clear meaning reset is complete */ 2917 for (i = 0; i < 10; i++) { 2918 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL); 2919 if (!(ctrl & IXGBE_CTRL_RST_MASK)) 2920 break; 2921 udelay(1); 2922 } 2923 2924 if (ctrl & IXGBE_CTRL_RST_MASK) { 2925 status = IXGBE_ERR_RESET_FAILED; 2926 hw_dbg(hw, "Reset polling failed to complete.\n"); 2927 } 2928 2929 msleep(50); 2930 2931 /* Double resets are required for recovery from certain error 2932 * clear the multicast table. Also reset num_rar_entries to 128, 2933 * since we modify this value when programming the SAN MAC address. 2934 */ 2935 if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) { 2936 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED; 2937 goto mac_reset_top; 2938 } 2939 2940 /* Store the permanent mac address */ 2941 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr); 2942 2943 /* Store MAC address from RAR0, clear receive address registers, and 2944 * clear the multicast table. Also reset num_rar_entries to 128, 2945 * since we modify this value when programming the SAN MAC address. 2946 */ 2947 hw->mac.num_rar_entries = 128; 2948 hw->mac.ops.init_rx_addrs(hw); 2949 2950 ixgbe_set_mdio_speed(hw); 2951 2952 if (hw->device_id == IXGBE_DEV_ID_X550EM_X_SFP) 2953 ixgbe_setup_mux_ctl(hw); 2954 2955 return status; 2956 } 2957 2958 /** ixgbe_set_ethertype_anti_spoofing_X550 - Enable/Disable Ethertype 2959 * anti-spoofing 2960 * @hw: pointer to hardware structure 2961 * @enable: enable or disable switch for Ethertype anti-spoofing 2962 * @vf: Virtual Function pool - VF Pool to set for Ethertype anti-spoofing 2963 **/ 2964 static void ixgbe_set_ethertype_anti_spoofing_X550(struct ixgbe_hw *hw, 2965 bool enable, int vf) 2966 { 2967 int vf_target_reg = vf >> 3; 2968 int vf_target_shift = vf % 8 + IXGBE_SPOOF_ETHERTYPEAS_SHIFT; 2969 u32 pfvfspoof; 2970 2971 pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg)); 2972 if (enable) 2973 pfvfspoof |= BIT(vf_target_shift); 2974 else 2975 pfvfspoof &= ~BIT(vf_target_shift); 2976 2977 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof); 2978 } 2979 2980 /** ixgbe_set_source_address_pruning_X550 - Enable/Disbale src address pruning 2981 * @hw: pointer to hardware structure 2982 * @enable: enable or disable source address pruning 2983 * @pool: Rx pool to set source address pruning for 2984 **/ 2985 static void ixgbe_set_source_address_pruning_X550(struct ixgbe_hw *hw, 2986 bool enable, 2987 unsigned int pool) 2988 { 2989 u64 pfflp; 2990 2991 /* max rx pool is 63 */ 2992 if (pool > 63) 2993 return; 2994 2995 pfflp = (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPL); 2996 pfflp |= (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPH) << 32; 2997 2998 if (enable) 2999 pfflp |= (1ULL << pool); 3000 else 3001 pfflp &= ~(1ULL << pool); 3002 3003 IXGBE_WRITE_REG(hw, IXGBE_PFFLPL, (u32)pfflp); 3004 IXGBE_WRITE_REG(hw, IXGBE_PFFLPH, (u32)(pfflp >> 32)); 3005 } 3006 3007 /** 3008 * ixgbe_setup_fc_backplane_x550em_a - Set up flow control 3009 * @hw: pointer to hardware structure 3010 * 3011 * Called at init time to set up flow control. 3012 **/ 3013 static s32 ixgbe_setup_fc_backplane_x550em_a(struct ixgbe_hw *hw) 3014 { 3015 s32 status = 0; 3016 u32 an_cntl = 0; 3017 3018 /* Validate the requested mode */ 3019 if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) { 3020 hw_err(hw, "ixgbe_fc_rx_pause not valid in strict IEEE mode\n"); 3021 return IXGBE_ERR_INVALID_LINK_SETTINGS; 3022 } 3023 3024 if (hw->fc.requested_mode == ixgbe_fc_default) 3025 hw->fc.requested_mode = ixgbe_fc_full; 3026 3027 /* Set up the 1G and 10G flow control advertisement registers so the 3028 * HW will be able to do FC autoneg once the cable is plugged in. If 3029 * we link at 10G, the 1G advertisement is harmless and vice versa. 3030 */ 3031 status = hw->mac.ops.read_iosf_sb_reg(hw, 3032 IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id), 3033 IXGBE_SB_IOSF_TARGET_KR_PHY, &an_cntl); 3034 3035 if (status) { 3036 hw_dbg(hw, "Auto-Negotiation did not complete\n"); 3037 return status; 3038 } 3039 3040 /* The possible values of fc.requested_mode are: 3041 * 0: Flow control is completely disabled 3042 * 1: Rx flow control is enabled (we can receive pause frames, 3043 * but not send pause frames). 3044 * 2: Tx flow control is enabled (we can send pause frames but 3045 * we do not support receiving pause frames). 3046 * 3: Both Rx and Tx flow control (symmetric) are enabled. 3047 * other: Invalid. 3048 */ 3049 switch (hw->fc.requested_mode) { 3050 case ixgbe_fc_none: 3051 /* Flow control completely disabled by software override. */ 3052 an_cntl &= ~(IXGBE_KRM_AN_CNTL_1_SYM_PAUSE | 3053 IXGBE_KRM_AN_CNTL_1_ASM_PAUSE); 3054 break; 3055 case ixgbe_fc_tx_pause: 3056 /* Tx Flow control is enabled, and Rx Flow control is 3057 * disabled by software override. 3058 */ 3059 an_cntl |= IXGBE_KRM_AN_CNTL_1_ASM_PAUSE; 3060 an_cntl &= ~IXGBE_KRM_AN_CNTL_1_SYM_PAUSE; 3061 break; 3062 case ixgbe_fc_rx_pause: 3063 /* Rx Flow control is enabled and Tx Flow control is 3064 * disabled by software override. Since there really 3065 * isn't a way to advertise that we are capable of RX 3066 * Pause ONLY, we will advertise that we support both 3067 * symmetric and asymmetric Rx PAUSE, as such we fall 3068 * through to the fc_full statement. Later, we will 3069 * disable the adapter's ability to send PAUSE frames. 3070 */ 3071 case ixgbe_fc_full: 3072 /* Flow control (both Rx and Tx) is enabled by SW override. */ 3073 an_cntl |= IXGBE_KRM_AN_CNTL_1_SYM_PAUSE | 3074 IXGBE_KRM_AN_CNTL_1_ASM_PAUSE; 3075 break; 3076 default: 3077 hw_err(hw, "Flow control param set incorrectly\n"); 3078 return IXGBE_ERR_CONFIG; 3079 } 3080 3081 status = hw->mac.ops.write_iosf_sb_reg(hw, 3082 IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id), 3083 IXGBE_SB_IOSF_TARGET_KR_PHY, an_cntl); 3084 3085 /* Restart auto-negotiation. */ 3086 status = ixgbe_restart_an_internal_phy_x550em(hw); 3087 3088 return status; 3089 } 3090 3091 /** 3092 * ixgbe_set_mux - Set mux for port 1 access with CS4227 3093 * @hw: pointer to hardware structure 3094 * @state: set mux if 1, clear if 0 3095 */ 3096 static void ixgbe_set_mux(struct ixgbe_hw *hw, u8 state) 3097 { 3098 u32 esdp; 3099 3100 if (!hw->bus.lan_id) 3101 return; 3102 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); 3103 if (state) 3104 esdp |= IXGBE_ESDP_SDP1; 3105 else 3106 esdp &= ~IXGBE_ESDP_SDP1; 3107 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp); 3108 IXGBE_WRITE_FLUSH(hw); 3109 } 3110 3111 /** 3112 * ixgbe_acquire_swfw_sync_X550em - Acquire SWFW semaphore 3113 * @hw: pointer to hardware structure 3114 * @mask: Mask to specify which semaphore to acquire 3115 * 3116 * Acquires the SWFW semaphore and sets the I2C MUX 3117 */ 3118 static s32 ixgbe_acquire_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask) 3119 { 3120 s32 status; 3121 3122 status = ixgbe_acquire_swfw_sync_X540(hw, mask); 3123 if (status) 3124 return status; 3125 3126 if (mask & IXGBE_GSSR_I2C_MASK) 3127 ixgbe_set_mux(hw, 1); 3128 3129 return 0; 3130 } 3131 3132 /** 3133 * ixgbe_release_swfw_sync_X550em - Release SWFW semaphore 3134 * @hw: pointer to hardware structure 3135 * @mask: Mask to specify which semaphore to release 3136 * 3137 * Releases the SWFW semaphore and sets the I2C MUX 3138 */ 3139 static void ixgbe_release_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask) 3140 { 3141 if (mask & IXGBE_GSSR_I2C_MASK) 3142 ixgbe_set_mux(hw, 0); 3143 3144 ixgbe_release_swfw_sync_X540(hw, mask); 3145 } 3146 3147 /** 3148 * ixgbe_acquire_swfw_sync_x550em_a - Acquire SWFW semaphore 3149 * @hw: pointer to hardware structure 3150 * @mask: Mask to specify which semaphore to acquire 3151 * 3152 * Acquires the SWFW semaphore and get the shared PHY token as needed 3153 */ 3154 static s32 ixgbe_acquire_swfw_sync_x550em_a(struct ixgbe_hw *hw, u32 mask) 3155 { 3156 u32 hmask = mask & ~IXGBE_GSSR_TOKEN_SM; 3157 int retries = FW_PHY_TOKEN_RETRIES; 3158 s32 status; 3159 3160 while (--retries) { 3161 status = 0; 3162 if (hmask) 3163 status = ixgbe_acquire_swfw_sync_X540(hw, hmask); 3164 if (status) 3165 return status; 3166 if (!(mask & IXGBE_GSSR_TOKEN_SM)) 3167 return 0; 3168 3169 status = ixgbe_get_phy_token(hw); 3170 if (!status) 3171 return 0; 3172 if (hmask) 3173 ixgbe_release_swfw_sync_X540(hw, hmask); 3174 if (status != IXGBE_ERR_TOKEN_RETRY) 3175 return status; 3176 msleep(FW_PHY_TOKEN_DELAY); 3177 } 3178 3179 return status; 3180 } 3181 3182 /** 3183 * ixgbe_release_swfw_sync_x550em_a - Release SWFW semaphore 3184 * @hw: pointer to hardware structure 3185 * @mask: Mask to specify which semaphore to release 3186 * 3187 * Release the SWFW semaphore and puts the shared PHY token as needed 3188 */ 3189 static void ixgbe_release_swfw_sync_x550em_a(struct ixgbe_hw *hw, u32 mask) 3190 { 3191 u32 hmask = mask & ~IXGBE_GSSR_TOKEN_SM; 3192 3193 if (mask & IXGBE_GSSR_TOKEN_SM) 3194 ixgbe_put_phy_token(hw); 3195 3196 if (hmask) 3197 ixgbe_release_swfw_sync_X540(hw, hmask); 3198 } 3199 3200 /** 3201 * ixgbe_read_phy_reg_x550a - Reads specified PHY register 3202 * @hw: pointer to hardware structure 3203 * @reg_addr: 32 bit address of PHY register to read 3204 * @phy_data: Pointer to read data from PHY register 3205 * 3206 * Reads a value from a specified PHY register using the SWFW lock and PHY 3207 * Token. The PHY Token is needed since the MDIO is shared between to MAC 3208 * instances. 3209 */ 3210 static s32 ixgbe_read_phy_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr, 3211 u32 device_type, u16 *phy_data) 3212 { 3213 u32 mask = hw->phy.phy_semaphore_mask | IXGBE_GSSR_TOKEN_SM; 3214 s32 status; 3215 3216 if (hw->mac.ops.acquire_swfw_sync(hw, mask)) 3217 return IXGBE_ERR_SWFW_SYNC; 3218 3219 status = hw->phy.ops.read_reg_mdi(hw, reg_addr, device_type, phy_data); 3220 3221 hw->mac.ops.release_swfw_sync(hw, mask); 3222 3223 return status; 3224 } 3225 3226 /** 3227 * ixgbe_write_phy_reg_x550a - Writes specified PHY register 3228 * @hw: pointer to hardware structure 3229 * @reg_addr: 32 bit PHY register to write 3230 * @device_type: 5 bit device type 3231 * @phy_data: Data to write to the PHY register 3232 * 3233 * Writes a value to specified PHY register using the SWFW lock and PHY Token. 3234 * The PHY Token is needed since the MDIO is shared between to MAC instances. 3235 */ 3236 static s32 ixgbe_write_phy_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr, 3237 u32 device_type, u16 phy_data) 3238 { 3239 u32 mask = hw->phy.phy_semaphore_mask | IXGBE_GSSR_TOKEN_SM; 3240 s32 status; 3241 3242 if (hw->mac.ops.acquire_swfw_sync(hw, mask)) 3243 return IXGBE_ERR_SWFW_SYNC; 3244 3245 status = ixgbe_write_phy_reg_mdi(hw, reg_addr, device_type, phy_data); 3246 hw->mac.ops.release_swfw_sync(hw, mask); 3247 3248 return status; 3249 } 3250 3251 #define X550_COMMON_MAC \ 3252 .init_hw = &ixgbe_init_hw_generic, \ 3253 .start_hw = &ixgbe_start_hw_X540, \ 3254 .clear_hw_cntrs = &ixgbe_clear_hw_cntrs_generic, \ 3255 .enable_rx_dma = &ixgbe_enable_rx_dma_generic, \ 3256 .get_mac_addr = &ixgbe_get_mac_addr_generic, \ 3257 .get_device_caps = &ixgbe_get_device_caps_generic, \ 3258 .stop_adapter = &ixgbe_stop_adapter_generic, \ 3259 .set_lan_id = &ixgbe_set_lan_id_multi_port_pcie, \ 3260 .read_analog_reg8 = NULL, \ 3261 .write_analog_reg8 = NULL, \ 3262 .set_rxpba = &ixgbe_set_rxpba_generic, \ 3263 .check_link = &ixgbe_check_mac_link_generic, \ 3264 .blink_led_start = &ixgbe_blink_led_start_X540, \ 3265 .blink_led_stop = &ixgbe_blink_led_stop_X540, \ 3266 .set_rar = &ixgbe_set_rar_generic, \ 3267 .clear_rar = &ixgbe_clear_rar_generic, \ 3268 .set_vmdq = &ixgbe_set_vmdq_generic, \ 3269 .set_vmdq_san_mac = &ixgbe_set_vmdq_san_mac_generic, \ 3270 .clear_vmdq = &ixgbe_clear_vmdq_generic, \ 3271 .init_rx_addrs = &ixgbe_init_rx_addrs_generic, \ 3272 .update_mc_addr_list = &ixgbe_update_mc_addr_list_generic, \ 3273 .enable_mc = &ixgbe_enable_mc_generic, \ 3274 .disable_mc = &ixgbe_disable_mc_generic, \ 3275 .clear_vfta = &ixgbe_clear_vfta_generic, \ 3276 .set_vfta = &ixgbe_set_vfta_generic, \ 3277 .fc_enable = &ixgbe_fc_enable_generic, \ 3278 .set_fw_drv_ver = &ixgbe_set_fw_drv_ver_generic, \ 3279 .init_uta_tables = &ixgbe_init_uta_tables_generic, \ 3280 .set_mac_anti_spoofing = &ixgbe_set_mac_anti_spoofing, \ 3281 .set_vlan_anti_spoofing = &ixgbe_set_vlan_anti_spoofing, \ 3282 .set_source_address_pruning = \ 3283 &ixgbe_set_source_address_pruning_X550, \ 3284 .set_ethertype_anti_spoofing = \ 3285 &ixgbe_set_ethertype_anti_spoofing_X550, \ 3286 .disable_rx_buff = &ixgbe_disable_rx_buff_generic, \ 3287 .enable_rx_buff = &ixgbe_enable_rx_buff_generic, \ 3288 .get_thermal_sensor_data = NULL, \ 3289 .init_thermal_sensor_thresh = NULL, \ 3290 .enable_rx = &ixgbe_enable_rx_generic, \ 3291 .disable_rx = &ixgbe_disable_rx_x550, \ 3292 3293 static const struct ixgbe_mac_operations mac_ops_X550 = { 3294 X550_COMMON_MAC 3295 .led_on = ixgbe_led_on_generic, 3296 .led_off = ixgbe_led_off_generic, 3297 .init_led_link_act = ixgbe_init_led_link_act_generic, 3298 .reset_hw = &ixgbe_reset_hw_X540, 3299 .get_media_type = &ixgbe_get_media_type_X540, 3300 .get_san_mac_addr = &ixgbe_get_san_mac_addr_generic, 3301 .get_wwn_prefix = &ixgbe_get_wwn_prefix_generic, 3302 .setup_link = &ixgbe_setup_mac_link_X540, 3303 .get_link_capabilities = &ixgbe_get_copper_link_capabilities_generic, 3304 .get_bus_info = &ixgbe_get_bus_info_generic, 3305 .setup_sfp = NULL, 3306 .acquire_swfw_sync = &ixgbe_acquire_swfw_sync_X540, 3307 .release_swfw_sync = &ixgbe_release_swfw_sync_X540, 3308 .init_swfw_sync = &ixgbe_init_swfw_sync_X540, 3309 .prot_autoc_read = prot_autoc_read_generic, 3310 .prot_autoc_write = prot_autoc_write_generic, 3311 .setup_fc = ixgbe_setup_fc_generic, 3312 .fc_autoneg = ixgbe_fc_autoneg, 3313 }; 3314 3315 static const struct ixgbe_mac_operations mac_ops_X550EM_x = { 3316 X550_COMMON_MAC 3317 .led_on = ixgbe_led_on_t_x550em, 3318 .led_off = ixgbe_led_off_t_x550em, 3319 .init_led_link_act = ixgbe_init_led_link_act_generic, 3320 .reset_hw = &ixgbe_reset_hw_X550em, 3321 .get_media_type = &ixgbe_get_media_type_X550em, 3322 .get_san_mac_addr = NULL, 3323 .get_wwn_prefix = NULL, 3324 .setup_link = &ixgbe_setup_mac_link_X540, 3325 .get_link_capabilities = &ixgbe_get_link_capabilities_X550em, 3326 .get_bus_info = &ixgbe_get_bus_info_X550em, 3327 .setup_sfp = ixgbe_setup_sfp_modules_X550em, 3328 .acquire_swfw_sync = &ixgbe_acquire_swfw_sync_X550em, 3329 .release_swfw_sync = &ixgbe_release_swfw_sync_X550em, 3330 .init_swfw_sync = &ixgbe_init_swfw_sync_X540, 3331 .setup_fc = NULL, /* defined later */ 3332 .fc_autoneg = ixgbe_fc_autoneg, 3333 .read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550, 3334 .write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550, 3335 }; 3336 3337 static struct ixgbe_mac_operations mac_ops_x550em_a = { 3338 X550_COMMON_MAC 3339 .led_on = ixgbe_led_on_t_x550em, 3340 .led_off = ixgbe_led_off_t_x550em, 3341 .init_led_link_act = ixgbe_init_led_link_act_generic, 3342 .reset_hw = ixgbe_reset_hw_X550em, 3343 .get_media_type = ixgbe_get_media_type_X550em, 3344 .get_san_mac_addr = NULL, 3345 .get_wwn_prefix = NULL, 3346 .setup_link = NULL, /* defined later */ 3347 .get_link_capabilities = ixgbe_get_link_capabilities_X550em, 3348 .get_bus_info = ixgbe_get_bus_info_X550em, 3349 .setup_sfp = ixgbe_setup_sfp_modules_X550em, 3350 .acquire_swfw_sync = ixgbe_acquire_swfw_sync_x550em_a, 3351 .release_swfw_sync = ixgbe_release_swfw_sync_x550em_a, 3352 .setup_fc = ixgbe_setup_fc_x550em, 3353 .fc_autoneg = ixgbe_fc_autoneg, 3354 .read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550a, 3355 .write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550a, 3356 }; 3357 3358 #define X550_COMMON_EEP \ 3359 .read = &ixgbe_read_ee_hostif_X550, \ 3360 .read_buffer = &ixgbe_read_ee_hostif_buffer_X550, \ 3361 .write = &ixgbe_write_ee_hostif_X550, \ 3362 .write_buffer = &ixgbe_write_ee_hostif_buffer_X550, \ 3363 .validate_checksum = &ixgbe_validate_eeprom_checksum_X550, \ 3364 .update_checksum = &ixgbe_update_eeprom_checksum_X550, \ 3365 .calc_checksum = &ixgbe_calc_eeprom_checksum_X550, \ 3366 3367 static const struct ixgbe_eeprom_operations eeprom_ops_X550 = { 3368 X550_COMMON_EEP 3369 .init_params = &ixgbe_init_eeprom_params_X550, 3370 }; 3371 3372 static const struct ixgbe_eeprom_operations eeprom_ops_X550EM_x = { 3373 X550_COMMON_EEP 3374 .init_params = &ixgbe_init_eeprom_params_X540, 3375 }; 3376 3377 #define X550_COMMON_PHY \ 3378 .identify_sfp = &ixgbe_identify_module_generic, \ 3379 .reset = NULL, \ 3380 .setup_link_speed = &ixgbe_setup_phy_link_speed_generic, \ 3381 .read_i2c_byte = &ixgbe_read_i2c_byte_generic, \ 3382 .write_i2c_byte = &ixgbe_write_i2c_byte_generic, \ 3383 .read_i2c_sff8472 = &ixgbe_read_i2c_sff8472_generic, \ 3384 .read_i2c_eeprom = &ixgbe_read_i2c_eeprom_generic, \ 3385 .write_i2c_eeprom = &ixgbe_write_i2c_eeprom_generic, \ 3386 .setup_link = &ixgbe_setup_phy_link_generic, \ 3387 .set_phy_power = NULL, \ 3388 .check_overtemp = &ixgbe_tn_check_overtemp, \ 3389 .get_firmware_version = &ixgbe_get_phy_firmware_version_generic, 3390 3391 static const struct ixgbe_phy_operations phy_ops_X550 = { 3392 X550_COMMON_PHY 3393 .init = NULL, 3394 .identify = &ixgbe_identify_phy_generic, 3395 .read_reg = &ixgbe_read_phy_reg_generic, 3396 .write_reg = &ixgbe_write_phy_reg_generic, 3397 }; 3398 3399 static const struct ixgbe_phy_operations phy_ops_X550EM_x = { 3400 X550_COMMON_PHY 3401 .init = &ixgbe_init_phy_ops_X550em, 3402 .identify = &ixgbe_identify_phy_x550em, 3403 .read_reg = &ixgbe_read_phy_reg_generic, 3404 .write_reg = &ixgbe_write_phy_reg_generic, 3405 }; 3406 3407 static const struct ixgbe_phy_operations phy_ops_x550em_a = { 3408 X550_COMMON_PHY 3409 .init = &ixgbe_init_phy_ops_X550em, 3410 .identify = &ixgbe_identify_phy_x550em, 3411 .read_reg = &ixgbe_read_phy_reg_x550a, 3412 .write_reg = &ixgbe_write_phy_reg_x550a, 3413 .read_reg_mdi = &ixgbe_read_phy_reg_mdi, 3414 .write_reg_mdi = &ixgbe_write_phy_reg_mdi, 3415 }; 3416 3417 static const struct ixgbe_link_operations link_ops_x550em_x = { 3418 .read_link = &ixgbe_read_i2c_combined_generic, 3419 .read_link_unlocked = &ixgbe_read_i2c_combined_generic_unlocked, 3420 .write_link = &ixgbe_write_i2c_combined_generic, 3421 .write_link_unlocked = &ixgbe_write_i2c_combined_generic_unlocked, 3422 }; 3423 3424 static const u32 ixgbe_mvals_X550[IXGBE_MVALS_IDX_LIMIT] = { 3425 IXGBE_MVALS_INIT(X550) 3426 }; 3427 3428 static const u32 ixgbe_mvals_X550EM_x[IXGBE_MVALS_IDX_LIMIT] = { 3429 IXGBE_MVALS_INIT(X550EM_x) 3430 }; 3431 3432 static const u32 ixgbe_mvals_x550em_a[IXGBE_MVALS_IDX_LIMIT] = { 3433 IXGBE_MVALS_INIT(X550EM_a) 3434 }; 3435 3436 const struct ixgbe_info ixgbe_X550_info = { 3437 .mac = ixgbe_mac_X550, 3438 .get_invariants = &ixgbe_get_invariants_X540, 3439 .mac_ops = &mac_ops_X550, 3440 .eeprom_ops = &eeprom_ops_X550, 3441 .phy_ops = &phy_ops_X550, 3442 .mbx_ops = &mbx_ops_generic, 3443 .mvals = ixgbe_mvals_X550, 3444 }; 3445 3446 const struct ixgbe_info ixgbe_X550EM_x_info = { 3447 .mac = ixgbe_mac_X550EM_x, 3448 .get_invariants = &ixgbe_get_invariants_X550_x, 3449 .mac_ops = &mac_ops_X550EM_x, 3450 .eeprom_ops = &eeprom_ops_X550EM_x, 3451 .phy_ops = &phy_ops_X550EM_x, 3452 .mbx_ops = &mbx_ops_generic, 3453 .mvals = ixgbe_mvals_X550EM_x, 3454 .link_ops = &link_ops_x550em_x, 3455 }; 3456 3457 const struct ixgbe_info ixgbe_x550em_a_info = { 3458 .mac = ixgbe_mac_x550em_a, 3459 .get_invariants = &ixgbe_get_invariants_X550_a, 3460 .mac_ops = &mac_ops_x550em_a, 3461 .eeprom_ops = &eeprom_ops_X550EM_x, 3462 .phy_ops = &phy_ops_x550em_a, 3463 .mbx_ops = &mbx_ops_generic, 3464 .mvals = ixgbe_mvals_x550em_a, 3465 }; 3466